Commit | Line | Data |
---|---|---|
252b5132 | 1 | /* tc-mips.c -- assemble code for a MIPS chip. |
4b95cf5c | 2 | Copyright (C) 1993-2014 Free Software Foundation, Inc. |
252b5132 RH |
3 | Contributed by the OSF and Ralph Campbell. |
4 | Written by Keith Knowles and Ralph Campbell, working independently. | |
5 | Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus | |
6 | Support. | |
7 | ||
8 | This file is part of GAS. | |
9 | ||
10 | GAS is free software; you can redistribute it and/or modify | |
11 | it under the terms of the GNU General Public License as published by | |
ec2655a6 | 12 | the Free Software Foundation; either version 3, or (at your option) |
252b5132 RH |
13 | any later version. |
14 | ||
15 | GAS is distributed in the hope that it will be useful, | |
16 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | GNU General Public License for more details. | |
19 | ||
20 | You should have received a copy of the GNU General Public License | |
21 | along with GAS; see the file COPYING. If not, write to the Free | |
4b4da160 NC |
22 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
23 | 02110-1301, USA. */ | |
252b5132 RH |
24 | |
25 | #include "as.h" | |
26 | #include "config.h" | |
27 | #include "subsegs.h" | |
3882b010 | 28 | #include "safe-ctype.h" |
252b5132 | 29 | |
252b5132 RH |
30 | #include "opcode/mips.h" |
31 | #include "itbl-ops.h" | |
c5dd6aab | 32 | #include "dwarf2dbg.h" |
5862107c | 33 | #include "dw2gencfi.h" |
252b5132 | 34 | |
42429eac RS |
35 | /* Check assumptions made in this file. */ |
36 | typedef char static_assert1[sizeof (offsetT) < 8 ? -1 : 1]; | |
37 | typedef char static_assert2[sizeof (valueT) < 8 ? -1 : 1]; | |
38 | ||
252b5132 RH |
39 | #ifdef DEBUG |
40 | #define DBG(x) printf x | |
41 | #else | |
42 | #define DBG(x) | |
43 | #endif | |
44 | ||
263b2574 | 45 | #define streq(a, b) (strcmp (a, b) == 0) |
46 | ||
9e12b7a2 RS |
47 | #define SKIP_SPACE_TABS(S) \ |
48 | do { while (*(S) == ' ' || *(S) == '\t') ++(S); } while (0) | |
49 | ||
252b5132 | 50 | /* Clean up namespace so we can include obj-elf.h too. */ |
17a2f251 TS |
51 | static int mips_output_flavor (void); |
52 | static int mips_output_flavor (void) { return OUTPUT_FLAVOR; } | |
252b5132 RH |
53 | #undef OBJ_PROCESS_STAB |
54 | #undef OUTPUT_FLAVOR | |
55 | #undef S_GET_ALIGN | |
56 | #undef S_GET_SIZE | |
57 | #undef S_SET_ALIGN | |
58 | #undef S_SET_SIZE | |
252b5132 RH |
59 | #undef obj_frob_file |
60 | #undef obj_frob_file_after_relocs | |
61 | #undef obj_frob_symbol | |
62 | #undef obj_pop_insert | |
63 | #undef obj_sec_sym_ok_for_reloc | |
64 | #undef OBJ_COPY_SYMBOL_ATTRIBUTES | |
65 | ||
66 | #include "obj-elf.h" | |
67 | /* Fix any of them that we actually care about. */ | |
68 | #undef OUTPUT_FLAVOR | |
69 | #define OUTPUT_FLAVOR mips_output_flavor() | |
252b5132 | 70 | |
252b5132 | 71 | #include "elf/mips.h" |
252b5132 RH |
72 | |
73 | #ifndef ECOFF_DEBUGGING | |
74 | #define NO_ECOFF_DEBUGGING | |
75 | #define ECOFF_DEBUGGING 0 | |
76 | #endif | |
77 | ||
ecb4347a DJ |
78 | int mips_flag_mdebug = -1; |
79 | ||
dcd410fe RO |
80 | /* Control generation of .pdr sections. Off by default on IRIX: the native |
81 | linker doesn't know about and discards them, but relocations against them | |
82 | remain, leading to rld crashes. */ | |
83 | #ifdef TE_IRIX | |
84 | int mips_flag_pdr = FALSE; | |
85 | #else | |
86 | int mips_flag_pdr = TRUE; | |
87 | #endif | |
88 | ||
252b5132 RH |
89 | #include "ecoff.h" |
90 | ||
252b5132 | 91 | static char *mips_regmask_frag; |
252b5132 | 92 | |
85b51719 | 93 | #define ZERO 0 |
741fe287 | 94 | #define ATREG 1 |
df58fc94 RS |
95 | #define S0 16 |
96 | #define S7 23 | |
252b5132 RH |
97 | #define TREG 24 |
98 | #define PIC_CALL_REG 25 | |
99 | #define KT0 26 | |
100 | #define KT1 27 | |
101 | #define GP 28 | |
102 | #define SP 29 | |
103 | #define FP 30 | |
104 | #define RA 31 | |
105 | ||
106 | #define ILLEGAL_REG (32) | |
107 | ||
741fe287 MR |
108 | #define AT mips_opts.at |
109 | ||
252b5132 RH |
110 | extern int target_big_endian; |
111 | ||
252b5132 | 112 | /* The name of the readonly data section. */ |
e8044f35 | 113 | #define RDATA_SECTION_NAME ".rodata" |
252b5132 | 114 | |
a4e06468 RS |
115 | /* Ways in which an instruction can be "appended" to the output. */ |
116 | enum append_method { | |
117 | /* Just add it normally. */ | |
118 | APPEND_ADD, | |
119 | ||
120 | /* Add it normally and then add a nop. */ | |
121 | APPEND_ADD_WITH_NOP, | |
122 | ||
123 | /* Turn an instruction with a delay slot into a "compact" version. */ | |
124 | APPEND_ADD_COMPACT, | |
125 | ||
126 | /* Insert the instruction before the last one. */ | |
127 | APPEND_SWAP | |
128 | }; | |
129 | ||
47e39b9d RS |
130 | /* Information about an instruction, including its format, operands |
131 | and fixups. */ | |
132 | struct mips_cl_insn | |
133 | { | |
134 | /* The opcode's entry in mips_opcodes or mips16_opcodes. */ | |
135 | const struct mips_opcode *insn_mo; | |
136 | ||
47e39b9d | 137 | /* The 16-bit or 32-bit bitstring of the instruction itself. This is |
5c04167a RS |
138 | a copy of INSN_MO->match with the operands filled in. If we have |
139 | decided to use an extended MIPS16 instruction, this includes the | |
140 | extension. */ | |
47e39b9d RS |
141 | unsigned long insn_opcode; |
142 | ||
143 | /* The frag that contains the instruction. */ | |
144 | struct frag *frag; | |
145 | ||
146 | /* The offset into FRAG of the first instruction byte. */ | |
147 | long where; | |
148 | ||
149 | /* The relocs associated with the instruction, if any. */ | |
150 | fixS *fixp[3]; | |
151 | ||
a38419a5 RS |
152 | /* True if this entry cannot be moved from its current position. */ |
153 | unsigned int fixed_p : 1; | |
47e39b9d | 154 | |
708587a4 | 155 | /* True if this instruction occurred in a .set noreorder block. */ |
47e39b9d RS |
156 | unsigned int noreorder_p : 1; |
157 | ||
2fa15973 RS |
158 | /* True for mips16 instructions that jump to an absolute address. */ |
159 | unsigned int mips16_absolute_jump_p : 1; | |
15be625d CM |
160 | |
161 | /* True if this instruction is complete. */ | |
162 | unsigned int complete_p : 1; | |
e407c74b NC |
163 | |
164 | /* True if this instruction is cleared from history by unconditional | |
165 | branch. */ | |
166 | unsigned int cleared_p : 1; | |
47e39b9d RS |
167 | }; |
168 | ||
a325df1d TS |
169 | /* The ABI to use. */ |
170 | enum mips_abi_level | |
171 | { | |
172 | NO_ABI = 0, | |
173 | O32_ABI, | |
174 | O64_ABI, | |
175 | N32_ABI, | |
176 | N64_ABI, | |
177 | EABI_ABI | |
178 | }; | |
179 | ||
180 | /* MIPS ABI we are using for this output file. */ | |
316f5878 | 181 | static enum mips_abi_level mips_abi = NO_ABI; |
a325df1d | 182 | |
143d77c5 EC |
183 | /* Whether or not we have code that can call pic code. */ |
184 | int mips_abicalls = FALSE; | |
185 | ||
aa6975fb ILT |
186 | /* Whether or not we have code which can be put into a shared |
187 | library. */ | |
188 | static bfd_boolean mips_in_shared = TRUE; | |
189 | ||
252b5132 RH |
190 | /* This is the set of options which may be modified by the .set |
191 | pseudo-op. We use a struct so that .set push and .set pop are more | |
192 | reliable. */ | |
193 | ||
e972090a NC |
194 | struct mips_set_options |
195 | { | |
252b5132 RH |
196 | /* MIPS ISA (Instruction Set Architecture) level. This is set to -1 |
197 | if it has not been initialized. Changed by `.set mipsN', and the | |
198 | -mipsN command line option, and the default CPU. */ | |
199 | int isa; | |
846ef2d0 RS |
200 | /* Enabled Application Specific Extensions (ASEs). Changed by `.set |
201 | <asename>', by command line options, and based on the default | |
202 | architecture. */ | |
203 | int ase; | |
252b5132 RH |
204 | /* Whether we are assembling for the mips16 processor. 0 if we are |
205 | not, 1 if we are, and -1 if the value has not been initialized. | |
206 | Changed by `.set mips16' and `.set nomips16', and the -mips16 and | |
207 | -nomips16 command line options, and the default CPU. */ | |
208 | int mips16; | |
df58fc94 RS |
209 | /* Whether we are assembling for the mipsMIPS ASE. 0 if we are not, |
210 | 1 if we are, and -1 if the value has not been initialized. Changed | |
211 | by `.set micromips' and `.set nomicromips', and the -mmicromips | |
212 | and -mno-micromips command line options, and the default CPU. */ | |
213 | int micromips; | |
252b5132 RH |
214 | /* Non-zero if we should not reorder instructions. Changed by `.set |
215 | reorder' and `.set noreorder'. */ | |
216 | int noreorder; | |
741fe287 MR |
217 | /* Non-zero if we should not permit the register designated "assembler |
218 | temporary" to be used in instructions. The value is the register | |
219 | number, normally $at ($1). Changed by `.set at=REG', `.set noat' | |
220 | (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */ | |
221 | unsigned int at; | |
252b5132 RH |
222 | /* Non-zero if we should warn when a macro instruction expands into |
223 | more than one machine instruction. Changed by `.set nomacro' and | |
224 | `.set macro'. */ | |
225 | int warn_about_macros; | |
226 | /* Non-zero if we should not move instructions. Changed by `.set | |
227 | move', `.set volatile', `.set nomove', and `.set novolatile'. */ | |
228 | int nomove; | |
229 | /* Non-zero if we should not optimize branches by moving the target | |
230 | of the branch into the delay slot. Actually, we don't perform | |
231 | this optimization anyhow. Changed by `.set bopt' and `.set | |
232 | nobopt'. */ | |
233 | int nobopt; | |
234 | /* Non-zero if we should not autoextend mips16 instructions. | |
235 | Changed by `.set autoextend' and `.set noautoextend'. */ | |
236 | int noautoextend; | |
833794fc MR |
237 | /* True if we should only emit 32-bit microMIPS instructions. |
238 | Changed by `.set insn32' and `.set noinsn32', and the -minsn32 | |
239 | and -mno-insn32 command line options. */ | |
240 | bfd_boolean insn32; | |
a325df1d TS |
241 | /* Restrict general purpose registers and floating point registers |
242 | to 32 bit. This is initially determined when -mgp32 or -mfp32 | |
243 | is passed but can changed if the assembler code uses .set mipsN. */ | |
bad1aba3 | 244 | int gp; |
0b35dfee | 245 | int fp; |
fef14a42 TS |
246 | /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march |
247 | command line option, and the default CPU. */ | |
248 | int arch; | |
aed1a261 RS |
249 | /* True if ".set sym32" is in effect. */ |
250 | bfd_boolean sym32; | |
037b32b9 AN |
251 | /* True if floating-point operations are not allowed. Changed by .set |
252 | softfloat or .set hardfloat, by command line options -msoft-float or | |
253 | -mhard-float. The default is false. */ | |
254 | bfd_boolean soft_float; | |
255 | ||
256 | /* True if only single-precision floating-point operations are allowed. | |
257 | Changed by .set singlefloat or .set doublefloat, command-line options | |
258 | -msingle-float or -mdouble-float. The default is false. */ | |
259 | bfd_boolean single_float; | |
252b5132 RH |
260 | }; |
261 | ||
0b35dfee | 262 | /* True if -mnan=2008, false if -mnan=legacy. */ |
263 | static bfd_boolean mips_flag_nan2008 = FALSE; | |
a325df1d | 264 | |
0b35dfee | 265 | /* This is the struct we use to hold the module level set of options. |
bad1aba3 | 266 | Note that we must set the isa field to ISA_UNKNOWN and the ASE, gp and |
0b35dfee | 267 | fp fields to -1 to indicate that they have not been initialized. */ |
037b32b9 | 268 | |
0b35dfee | 269 | static struct mips_set_options file_mips_opts = |
270 | { | |
271 | /* isa */ ISA_UNKNOWN, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1, | |
272 | /* noreorder */ 0, /* at */ ATREG, /* warn_about_macros */ 0, | |
273 | /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE, | |
bad1aba3 | 274 | /* gp */ -1, /* fp */ -1, /* arch */ CPU_UNKNOWN, /* sym32 */ FALSE, |
0b35dfee | 275 | /* soft_float */ FALSE, /* single_float */ FALSE |
276 | }; | |
252b5132 | 277 | |
0b35dfee | 278 | /* This is similar to file_mips_opts, but for the current set of options. */ |
ba92f887 | 279 | |
e972090a NC |
280 | static struct mips_set_options mips_opts = |
281 | { | |
846ef2d0 | 282 | /* isa */ ISA_UNKNOWN, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1, |
b015e599 | 283 | /* noreorder */ 0, /* at */ ATREG, /* warn_about_macros */ 0, |
833794fc | 284 | /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE, |
bad1aba3 | 285 | /* gp */ -1, /* fp */ -1, /* arch */ CPU_UNKNOWN, /* sym32 */ FALSE, |
b015e599 | 286 | /* soft_float */ FALSE, /* single_float */ FALSE |
e7af610e | 287 | }; |
252b5132 | 288 | |
846ef2d0 RS |
289 | /* The set of ASEs that were selected on the command line, either |
290 | explicitly via ASE options or implicitly through things like -march. */ | |
291 | static unsigned int file_ase; | |
292 | ||
293 | /* Which bits of file_ase were explicitly set or cleared by ASE options. */ | |
294 | static unsigned int file_ase_explicit; | |
295 | ||
252b5132 RH |
296 | /* These variables are filled in with the masks of registers used. |
297 | The object format code reads them and puts them in the appropriate | |
298 | place. */ | |
299 | unsigned long mips_gprmask; | |
300 | unsigned long mips_cprmask[4]; | |
301 | ||
738f4d98 | 302 | /* True if any MIPS16 code was produced. */ |
a4672219 TS |
303 | static int file_ase_mips16; |
304 | ||
3994f87e TS |
305 | #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \ |
306 | || mips_opts.isa == ISA_MIPS32R2 \ | |
ae52f483 AB |
307 | || mips_opts.isa == ISA_MIPS32R3 \ |
308 | || mips_opts.isa == ISA_MIPS32R5 \ | |
3994f87e | 309 | || mips_opts.isa == ISA_MIPS64 \ |
ae52f483 AB |
310 | || mips_opts.isa == ISA_MIPS64R2 \ |
311 | || mips_opts.isa == ISA_MIPS64R3 \ | |
312 | || mips_opts.isa == ISA_MIPS64R5) | |
3994f87e | 313 | |
df58fc94 RS |
314 | /* True if any microMIPS code was produced. */ |
315 | static int file_ase_micromips; | |
316 | ||
b12dd2e4 CF |
317 | /* True if we want to create R_MIPS_JALR for jalr $25. */ |
318 | #ifdef TE_IRIX | |
1180b5a4 | 319 | #define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI |
b12dd2e4 | 320 | #else |
1180b5a4 RS |
321 | /* As a GNU extension, we use R_MIPS_JALR for o32 too. However, |
322 | because there's no place for any addend, the only acceptable | |
323 | expression is a bare symbol. */ | |
324 | #define MIPS_JALR_HINT_P(EXPR) \ | |
325 | (!HAVE_IN_PLACE_ADDENDS \ | |
326 | || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0)) | |
b12dd2e4 CF |
327 | #endif |
328 | ||
ec68c924 | 329 | /* The argument of the -march= flag. The architecture we are assembling. */ |
316f5878 | 330 | static const char *mips_arch_string; |
ec68c924 EC |
331 | |
332 | /* The argument of the -mtune= flag. The architecture for which we | |
333 | are optimizing. */ | |
334 | static int mips_tune = CPU_UNKNOWN; | |
316f5878 | 335 | static const char *mips_tune_string; |
ec68c924 | 336 | |
316f5878 | 337 | /* True when generating 32-bit code for a 64-bit processor. */ |
252b5132 RH |
338 | static int mips_32bitmode = 0; |
339 | ||
316f5878 RS |
340 | /* True if the given ABI requires 32-bit registers. */ |
341 | #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI) | |
342 | ||
343 | /* Likewise 64-bit registers. */ | |
707bfff6 TS |
344 | #define ABI_NEEDS_64BIT_REGS(ABI) \ |
345 | ((ABI) == N32_ABI \ | |
346 | || (ABI) == N64_ABI \ | |
316f5878 RS |
347 | || (ABI) == O64_ABI) |
348 | ||
ad3fea08 | 349 | /* Return true if ISA supports 64 bit wide gp registers. */ |
707bfff6 TS |
350 | #define ISA_HAS_64BIT_REGS(ISA) \ |
351 | ((ISA) == ISA_MIPS3 \ | |
352 | || (ISA) == ISA_MIPS4 \ | |
353 | || (ISA) == ISA_MIPS5 \ | |
354 | || (ISA) == ISA_MIPS64 \ | |
ae52f483 AB |
355 | || (ISA) == ISA_MIPS64R2 \ |
356 | || (ISA) == ISA_MIPS64R3 \ | |
357 | || (ISA) == ISA_MIPS64R5) | |
9ce8a5dd | 358 | |
ad3fea08 TS |
359 | /* Return true if ISA supports 64 bit wide float registers. */ |
360 | #define ISA_HAS_64BIT_FPRS(ISA) \ | |
361 | ((ISA) == ISA_MIPS3 \ | |
362 | || (ISA) == ISA_MIPS4 \ | |
363 | || (ISA) == ISA_MIPS5 \ | |
364 | || (ISA) == ISA_MIPS32R2 \ | |
ae52f483 AB |
365 | || (ISA) == ISA_MIPS32R3 \ |
366 | || (ISA) == ISA_MIPS32R5 \ | |
ad3fea08 | 367 | || (ISA) == ISA_MIPS64 \ |
ae52f483 AB |
368 | || (ISA) == ISA_MIPS64R2 \ |
369 | || (ISA) == ISA_MIPS64R3 \ | |
370 | || (ISA) == ISA_MIPS64R5 ) | |
ad3fea08 | 371 | |
af7ee8bf CD |
372 | /* Return true if ISA supports 64-bit right rotate (dror et al.) |
373 | instructions. */ | |
707bfff6 | 374 | #define ISA_HAS_DROR(ISA) \ |
df58fc94 | 375 | ((ISA) == ISA_MIPS64R2 \ |
ae52f483 AB |
376 | || (ISA) == ISA_MIPS64R3 \ |
377 | || (ISA) == ISA_MIPS64R5 \ | |
df58fc94 RS |
378 | || (mips_opts.micromips \ |
379 | && ISA_HAS_64BIT_REGS (ISA)) \ | |
380 | ) | |
af7ee8bf CD |
381 | |
382 | /* Return true if ISA supports 32-bit right rotate (ror et al.) | |
383 | instructions. */ | |
707bfff6 TS |
384 | #define ISA_HAS_ROR(ISA) \ |
385 | ((ISA) == ISA_MIPS32R2 \ | |
ae52f483 AB |
386 | || (ISA) == ISA_MIPS32R3 \ |
387 | || (ISA) == ISA_MIPS32R5 \ | |
707bfff6 | 388 | || (ISA) == ISA_MIPS64R2 \ |
ae52f483 AB |
389 | || (ISA) == ISA_MIPS64R3 \ |
390 | || (ISA) == ISA_MIPS64R5 \ | |
846ef2d0 | 391 | || (mips_opts.ase & ASE_SMARTMIPS) \ |
df58fc94 RS |
392 | || mips_opts.micromips \ |
393 | ) | |
707bfff6 | 394 | |
7455baf8 TS |
395 | /* Return true if ISA supports single-precision floats in odd registers. */ |
396 | #define ISA_HAS_ODD_SINGLE_FPR(ISA) \ | |
397 | ((ISA) == ISA_MIPS32 \ | |
398 | || (ISA) == ISA_MIPS32R2 \ | |
ae52f483 AB |
399 | || (ISA) == ISA_MIPS32R3 \ |
400 | || (ISA) == ISA_MIPS32R5 \ | |
7455baf8 | 401 | || (ISA) == ISA_MIPS64 \ |
ae52f483 AB |
402 | || (ISA) == ISA_MIPS64R2 \ |
403 | || (ISA) == ISA_MIPS64R3 \ | |
404 | || (ISA) == ISA_MIPS64R5) | |
af7ee8bf | 405 | |
ad3fea08 TS |
406 | /* Return true if ISA supports move to/from high part of a 64-bit |
407 | floating-point register. */ | |
408 | #define ISA_HAS_MXHC1(ISA) \ | |
409 | ((ISA) == ISA_MIPS32R2 \ | |
ae52f483 AB |
410 | || (ISA) == ISA_MIPS32R3 \ |
411 | || (ISA) == ISA_MIPS32R5 \ | |
412 | || (ISA) == ISA_MIPS64R2 \ | |
413 | || (ISA) == ISA_MIPS64R3 \ | |
414 | || (ISA) == ISA_MIPS64R5) | |
ad3fea08 | 415 | |
bad1aba3 | 416 | #define GPR_SIZE \ |
417 | (mips_opts.gp == 64 && !ISA_HAS_64BIT_REGS (mips_opts.isa) \ | |
418 | ? 32 \ | |
419 | : mips_opts.gp) | |
ca4e0257 | 420 | |
bad1aba3 | 421 | #define FPR_SIZE \ |
422 | (mips_opts.fp == 64 && !ISA_HAS_64BIT_FPRS (mips_opts.isa) \ | |
423 | ? 32 \ | |
424 | : mips_opts.fp) | |
ca4e0257 | 425 | |
316f5878 | 426 | #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI) |
e013f690 | 427 | |
316f5878 | 428 | #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI) |
e013f690 | 429 | |
3b91255e RS |
430 | /* True if relocations are stored in-place. */ |
431 | #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI) | |
432 | ||
aed1a261 RS |
433 | /* The ABI-derived address size. */ |
434 | #define HAVE_64BIT_ADDRESSES \ | |
bad1aba3 | 435 | (GPR_SIZE == 64 && (mips_abi == EABI_ABI || mips_abi == N64_ABI)) |
aed1a261 | 436 | #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES) |
e013f690 | 437 | |
aed1a261 RS |
438 | /* The size of symbolic constants (i.e., expressions of the form |
439 | "SYMBOL" or "SYMBOL + OFFSET"). */ | |
440 | #define HAVE_32BIT_SYMBOLS \ | |
441 | (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32) | |
442 | #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS) | |
ca4e0257 | 443 | |
b7c7d6c1 TS |
444 | /* Addresses are loaded in different ways, depending on the address size |
445 | in use. The n32 ABI Documentation also mandates the use of additions | |
446 | with overflow checking, but existing implementations don't follow it. */ | |
f899b4b8 | 447 | #define ADDRESS_ADD_INSN \ |
b7c7d6c1 | 448 | (HAVE_32BIT_ADDRESSES ? "addu" : "daddu") |
f899b4b8 TS |
449 | |
450 | #define ADDRESS_ADDI_INSN \ | |
b7c7d6c1 | 451 | (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu") |
f899b4b8 TS |
452 | |
453 | #define ADDRESS_LOAD_INSN \ | |
454 | (HAVE_32BIT_ADDRESSES ? "lw" : "ld") | |
455 | ||
456 | #define ADDRESS_STORE_INSN \ | |
457 | (HAVE_32BIT_ADDRESSES ? "sw" : "sd") | |
458 | ||
a4672219 | 459 | /* Return true if the given CPU supports the MIPS16 ASE. */ |
3396de36 TS |
460 | #define CPU_HAS_MIPS16(cpu) \ |
461 | (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \ | |
462 | || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0) | |
a4672219 | 463 | |
2309ddf2 | 464 | /* Return true if the given CPU supports the microMIPS ASE. */ |
df58fc94 RS |
465 | #define CPU_HAS_MICROMIPS(cpu) 0 |
466 | ||
60b63b72 RS |
467 | /* True if CPU has a dror instruction. */ |
468 | #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500) | |
469 | ||
470 | /* True if CPU has a ror instruction. */ | |
471 | #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU) | |
472 | ||
dd6a37e7 | 473 | /* True if CPU is in the Octeon family */ |
432233b3 | 474 | #define CPU_IS_OCTEON(CPU) ((CPU) == CPU_OCTEON || (CPU) == CPU_OCTEONP || (CPU) == CPU_OCTEON2) |
dd6a37e7 | 475 | |
dd3cbb7e | 476 | /* True if CPU has seq/sne and seqi/snei instructions. */ |
dd6a37e7 | 477 | #define CPU_HAS_SEQ(CPU) (CPU_IS_OCTEON (CPU)) |
dd3cbb7e | 478 | |
0aa27725 RS |
479 | /* True, if CPU has support for ldc1 and sdc1. */ |
480 | #define CPU_HAS_LDC1_SDC1(CPU) \ | |
481 | ((mips_opts.isa != ISA_MIPS1) && ((CPU) != CPU_R5900)) | |
482 | ||
c8978940 CD |
483 | /* True if mflo and mfhi can be immediately followed by instructions |
484 | which write to the HI and LO registers. | |
485 | ||
486 | According to MIPS specifications, MIPS ISAs I, II, and III need | |
487 | (at least) two instructions between the reads of HI/LO and | |
488 | instructions which write them, and later ISAs do not. Contradicting | |
489 | the MIPS specifications, some MIPS IV processor user manuals (e.g. | |
490 | the UM for the NEC Vr5000) document needing the instructions between | |
491 | HI/LO reads and writes, as well. Therefore, we declare only MIPS32, | |
492 | MIPS64 and later ISAs to have the interlocks, plus any specific | |
493 | earlier-ISA CPUs for which CPU documentation declares that the | |
494 | instructions are really interlocked. */ | |
495 | #define hilo_interlocks \ | |
496 | (mips_opts.isa == ISA_MIPS32 \ | |
497 | || mips_opts.isa == ISA_MIPS32R2 \ | |
ae52f483 AB |
498 | || mips_opts.isa == ISA_MIPS32R3 \ |
499 | || mips_opts.isa == ISA_MIPS32R5 \ | |
c8978940 CD |
500 | || mips_opts.isa == ISA_MIPS64 \ |
501 | || mips_opts.isa == ISA_MIPS64R2 \ | |
ae52f483 AB |
502 | || mips_opts.isa == ISA_MIPS64R3 \ |
503 | || mips_opts.isa == ISA_MIPS64R5 \ | |
c8978940 | 504 | || mips_opts.arch == CPU_R4010 \ |
e407c74b | 505 | || mips_opts.arch == CPU_R5900 \ |
c8978940 CD |
506 | || mips_opts.arch == CPU_R10000 \ |
507 | || mips_opts.arch == CPU_R12000 \ | |
3aa3176b TS |
508 | || mips_opts.arch == CPU_R14000 \ |
509 | || mips_opts.arch == CPU_R16000 \ | |
c8978940 | 510 | || mips_opts.arch == CPU_RM7000 \ |
c8978940 | 511 | || mips_opts.arch == CPU_VR5500 \ |
df58fc94 | 512 | || mips_opts.micromips \ |
c8978940 | 513 | ) |
252b5132 RH |
514 | |
515 | /* Whether the processor uses hardware interlocks to protect reads | |
81912461 ILT |
516 | from the GPRs after they are loaded from memory, and thus does not |
517 | require nops to be inserted. This applies to instructions marked | |
67dc82bc | 518 | INSN_LOAD_MEMORY. These nops are only required at MIPS ISA |
df58fc94 RS |
519 | level I and microMIPS mode instructions are always interlocked. */ |
520 | #define gpr_interlocks \ | |
521 | (mips_opts.isa != ISA_MIPS1 \ | |
522 | || mips_opts.arch == CPU_R3900 \ | |
e407c74b | 523 | || mips_opts.arch == CPU_R5900 \ |
df58fc94 RS |
524 | || mips_opts.micromips \ |
525 | ) | |
252b5132 | 526 | |
81912461 ILT |
527 | /* Whether the processor uses hardware interlocks to avoid delays |
528 | required by coprocessor instructions, and thus does not require | |
529 | nops to be inserted. This applies to instructions marked | |
530 | INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays | |
531 | between instructions marked INSN_WRITE_COND_CODE and ones marked | |
532 | INSN_READ_COND_CODE. These nops are only required at MIPS ISA | |
df58fc94 RS |
533 | levels I, II, and III and microMIPS mode instructions are always |
534 | interlocked. */ | |
bdaaa2e1 | 535 | /* Itbl support may require additional care here. */ |
81912461 ILT |
536 | #define cop_interlocks \ |
537 | ((mips_opts.isa != ISA_MIPS1 \ | |
538 | && mips_opts.isa != ISA_MIPS2 \ | |
539 | && mips_opts.isa != ISA_MIPS3) \ | |
540 | || mips_opts.arch == CPU_R4300 \ | |
df58fc94 | 541 | || mips_opts.micromips \ |
81912461 ILT |
542 | ) |
543 | ||
544 | /* Whether the processor uses hardware interlocks to protect reads | |
545 | from coprocessor registers after they are loaded from memory, and | |
546 | thus does not require nops to be inserted. This applies to | |
547 | instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only | |
df58fc94 RS |
548 | requires at MIPS ISA level I and microMIPS mode instructions are |
549 | always interlocked. */ | |
550 | #define cop_mem_interlocks \ | |
551 | (mips_opts.isa != ISA_MIPS1 \ | |
552 | || mips_opts.micromips \ | |
553 | ) | |
252b5132 | 554 | |
6b76fefe CM |
555 | /* Is this a mfhi or mflo instruction? */ |
556 | #define MF_HILO_INSN(PINFO) \ | |
b19e8a9b AN |
557 | ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO)) |
558 | ||
df58fc94 RS |
559 | /* Whether code compression (either of the MIPS16 or the microMIPS ASEs) |
560 | has been selected. This implies, in particular, that addresses of text | |
561 | labels have their LSB set. */ | |
562 | #define HAVE_CODE_COMPRESSION \ | |
563 | ((mips_opts.mips16 | mips_opts.micromips) != 0) | |
564 | ||
42429eac | 565 | /* The minimum and maximum signed values that can be stored in a GPR. */ |
bad1aba3 | 566 | #define GPR_SMAX ((offsetT) (((valueT) 1 << (GPR_SIZE - 1)) - 1)) |
42429eac RS |
567 | #define GPR_SMIN (-GPR_SMAX - 1) |
568 | ||
252b5132 RH |
569 | /* MIPS PIC level. */ |
570 | ||
a161fe53 | 571 | enum mips_pic_level mips_pic; |
252b5132 | 572 | |
c9914766 | 573 | /* 1 if we should generate 32 bit offsets from the $gp register in |
252b5132 | 574 | SVR4_PIC mode. Currently has no meaning in other modes. */ |
c9914766 | 575 | static int mips_big_got = 0; |
252b5132 RH |
576 | |
577 | /* 1 if trap instructions should used for overflow rather than break | |
578 | instructions. */ | |
c9914766 | 579 | static int mips_trap = 0; |
252b5132 | 580 | |
119d663a | 581 | /* 1 if double width floating point constants should not be constructed |
b6ff326e | 582 | by assembling two single width halves into two single width floating |
119d663a NC |
583 | point registers which just happen to alias the double width destination |
584 | register. On some architectures this aliasing can be disabled by a bit | |
d547a75e | 585 | in the status register, and the setting of this bit cannot be determined |
119d663a NC |
586 | automatically at assemble time. */ |
587 | static int mips_disable_float_construction; | |
588 | ||
252b5132 RH |
589 | /* Non-zero if any .set noreorder directives were used. */ |
590 | ||
591 | static int mips_any_noreorder; | |
592 | ||
6b76fefe CM |
593 | /* Non-zero if nops should be inserted when the register referenced in |
594 | an mfhi/mflo instruction is read in the next two instructions. */ | |
595 | static int mips_7000_hilo_fix; | |
596 | ||
02ffd3e4 | 597 | /* The size of objects in the small data section. */ |
156c2f8b | 598 | static unsigned int g_switch_value = 8; |
252b5132 RH |
599 | /* Whether the -G option was used. */ |
600 | static int g_switch_seen = 0; | |
601 | ||
602 | #define N_RMASK 0xc4 | |
603 | #define N_VFP 0xd4 | |
604 | ||
605 | /* If we can determine in advance that GP optimization won't be | |
606 | possible, we can skip the relaxation stuff that tries to produce | |
607 | GP-relative references. This makes delay slot optimization work | |
608 | better. | |
609 | ||
610 | This function can only provide a guess, but it seems to work for | |
fba2b7f9 GK |
611 | gcc output. It needs to guess right for gcc, otherwise gcc |
612 | will put what it thinks is a GP-relative instruction in a branch | |
613 | delay slot. | |
252b5132 RH |
614 | |
615 | I don't know if a fix is needed for the SVR4_PIC mode. I've only | |
616 | fixed it for the non-PIC mode. KR 95/04/07 */ | |
17a2f251 | 617 | static int nopic_need_relax (symbolS *, int); |
252b5132 RH |
618 | |
619 | /* handle of the OPCODE hash table */ | |
620 | static struct hash_control *op_hash = NULL; | |
621 | ||
622 | /* The opcode hash table we use for the mips16. */ | |
623 | static struct hash_control *mips16_op_hash = NULL; | |
624 | ||
df58fc94 RS |
625 | /* The opcode hash table we use for the microMIPS ASE. */ |
626 | static struct hash_control *micromips_op_hash = NULL; | |
627 | ||
252b5132 RH |
628 | /* This array holds the chars that always start a comment. If the |
629 | pre-processor is disabled, these aren't very useful */ | |
630 | const char comment_chars[] = "#"; | |
631 | ||
632 | /* This array holds the chars that only start a comment at the beginning of | |
633 | a line. If the line seems to have the form '# 123 filename' | |
634 | .line and .file directives will appear in the pre-processed output */ | |
635 | /* Note that input_file.c hand checks for '#' at the beginning of the | |
636 | first line of the input file. This is because the compiler outputs | |
bdaaa2e1 | 637 | #NO_APP at the beginning of its output. */ |
252b5132 RH |
638 | /* Also note that C style comments are always supported. */ |
639 | const char line_comment_chars[] = "#"; | |
640 | ||
bdaaa2e1 | 641 | /* This array holds machine specific line separator characters. */ |
63a0b638 | 642 | const char line_separator_chars[] = ";"; |
252b5132 RH |
643 | |
644 | /* Chars that can be used to separate mant from exp in floating point nums */ | |
645 | const char EXP_CHARS[] = "eE"; | |
646 | ||
647 | /* Chars that mean this number is a floating point constant */ | |
648 | /* As in 0f12.456 */ | |
649 | /* or 0d1.2345e12 */ | |
650 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; | |
651 | ||
652 | /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be | |
653 | changed in read.c . Ideally it shouldn't have to know about it at all, | |
654 | but nothing is ideal around here. | |
655 | */ | |
656 | ||
e3de51ce RS |
657 | /* Types of printf format used for instruction-related error messages. |
658 | "I" means int ("%d") and "S" means string ("%s"). */ | |
659 | enum mips_insn_error_format { | |
660 | ERR_FMT_PLAIN, | |
661 | ERR_FMT_I, | |
662 | ERR_FMT_SS, | |
663 | }; | |
664 | ||
665 | /* Information about an error that was found while assembling the current | |
666 | instruction. */ | |
667 | struct mips_insn_error { | |
668 | /* We sometimes need to match an instruction against more than one | |
669 | opcode table entry. Errors found during this matching are reported | |
670 | against a particular syntactic argument rather than against the | |
671 | instruction as a whole. We grade these messages so that errors | |
672 | against argument N have a greater priority than an error against | |
673 | any argument < N, since the former implies that arguments up to N | |
674 | were acceptable and that the opcode entry was therefore a closer match. | |
675 | If several matches report an error against the same argument, | |
676 | we only use that error if it is the same in all cases. | |
677 | ||
678 | min_argnum is the minimum argument number for which an error message | |
679 | should be accepted. It is 0 if MSG is against the instruction as | |
680 | a whole. */ | |
681 | int min_argnum; | |
682 | ||
683 | /* The printf()-style message, including its format and arguments. */ | |
684 | enum mips_insn_error_format format; | |
685 | const char *msg; | |
686 | union { | |
687 | int i; | |
688 | const char *ss[2]; | |
689 | } u; | |
690 | }; | |
691 | ||
692 | /* The error that should be reported for the current instruction. */ | |
693 | static struct mips_insn_error insn_error; | |
252b5132 RH |
694 | |
695 | static int auto_align = 1; | |
696 | ||
697 | /* When outputting SVR4 PIC code, the assembler needs to know the | |
698 | offset in the stack frame from which to restore the $gp register. | |
699 | This is set by the .cprestore pseudo-op, and saved in this | |
700 | variable. */ | |
701 | static offsetT mips_cprestore_offset = -1; | |
702 | ||
67c1ffbe | 703 | /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some |
6478892d | 704 | more optimizations, it can use a register value instead of a memory-saved |
956cd1d6 | 705 | offset and even an other register than $gp as global pointer. */ |
6478892d TS |
706 | static offsetT mips_cpreturn_offset = -1; |
707 | static int mips_cpreturn_register = -1; | |
708 | static int mips_gp_register = GP; | |
def2e0dd | 709 | static int mips_gprel_offset = 0; |
6478892d | 710 | |
7a621144 DJ |
711 | /* Whether mips_cprestore_offset has been set in the current function |
712 | (or whether it has already been warned about, if not). */ | |
713 | static int mips_cprestore_valid = 0; | |
714 | ||
252b5132 RH |
715 | /* This is the register which holds the stack frame, as set by the |
716 | .frame pseudo-op. This is needed to implement .cprestore. */ | |
717 | static int mips_frame_reg = SP; | |
718 | ||
7a621144 DJ |
719 | /* Whether mips_frame_reg has been set in the current function |
720 | (or whether it has already been warned about, if not). */ | |
721 | static int mips_frame_reg_valid = 0; | |
722 | ||
252b5132 RH |
723 | /* To output NOP instructions correctly, we need to keep information |
724 | about the previous two instructions. */ | |
725 | ||
726 | /* Whether we are optimizing. The default value of 2 means to remove | |
727 | unneeded NOPs and swap branch instructions when possible. A value | |
728 | of 1 means to not swap branches. A value of 0 means to always | |
729 | insert NOPs. */ | |
730 | static int mips_optimize = 2; | |
731 | ||
732 | /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is | |
733 | equivalent to seeing no -g option at all. */ | |
734 | static int mips_debug = 0; | |
735 | ||
7d8e00cf RS |
736 | /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */ |
737 | #define MAX_VR4130_NOPS 4 | |
738 | ||
739 | /* The maximum number of NOPs needed to fill delay slots. */ | |
740 | #define MAX_DELAY_NOPS 2 | |
741 | ||
742 | /* The maximum number of NOPs needed for any purpose. */ | |
743 | #define MAX_NOPS 4 | |
71400594 RS |
744 | |
745 | /* A list of previous instructions, with index 0 being the most recent. | |
746 | We need to look back MAX_NOPS instructions when filling delay slots | |
747 | or working around processor errata. We need to look back one | |
748 | instruction further if we're thinking about using history[0] to | |
749 | fill a branch delay slot. */ | |
750 | static struct mips_cl_insn history[1 + MAX_NOPS]; | |
252b5132 | 751 | |
fc76e730 | 752 | /* Arrays of operands for each instruction. */ |
14daeee3 | 753 | #define MAX_OPERANDS 6 |
fc76e730 RS |
754 | struct mips_operand_array { |
755 | const struct mips_operand *operand[MAX_OPERANDS]; | |
756 | }; | |
757 | static struct mips_operand_array *mips_operands; | |
758 | static struct mips_operand_array *mips16_operands; | |
759 | static struct mips_operand_array *micromips_operands; | |
760 | ||
1e915849 | 761 | /* Nop instructions used by emit_nop. */ |
df58fc94 RS |
762 | static struct mips_cl_insn nop_insn; |
763 | static struct mips_cl_insn mips16_nop_insn; | |
764 | static struct mips_cl_insn micromips_nop16_insn; | |
765 | static struct mips_cl_insn micromips_nop32_insn; | |
1e915849 RS |
766 | |
767 | /* The appropriate nop for the current mode. */ | |
833794fc MR |
768 | #define NOP_INSN (mips_opts.mips16 \ |
769 | ? &mips16_nop_insn \ | |
770 | : (mips_opts.micromips \ | |
771 | ? (mips_opts.insn32 \ | |
772 | ? µmips_nop32_insn \ | |
773 | : µmips_nop16_insn) \ | |
774 | : &nop_insn)) | |
df58fc94 RS |
775 | |
776 | /* The size of NOP_INSN in bytes. */ | |
833794fc MR |
777 | #define NOP_INSN_SIZE ((mips_opts.mips16 \ |
778 | || (mips_opts.micromips && !mips_opts.insn32)) \ | |
779 | ? 2 : 4) | |
252b5132 | 780 | |
252b5132 RH |
781 | /* If this is set, it points to a frag holding nop instructions which |
782 | were inserted before the start of a noreorder section. If those | |
783 | nops turn out to be unnecessary, the size of the frag can be | |
784 | decreased. */ | |
785 | static fragS *prev_nop_frag; | |
786 | ||
787 | /* The number of nop instructions we created in prev_nop_frag. */ | |
788 | static int prev_nop_frag_holds; | |
789 | ||
790 | /* The number of nop instructions that we know we need in | |
bdaaa2e1 | 791 | prev_nop_frag. */ |
252b5132 RH |
792 | static int prev_nop_frag_required; |
793 | ||
794 | /* The number of instructions we've seen since prev_nop_frag. */ | |
795 | static int prev_nop_frag_since; | |
796 | ||
e8044f35 RS |
797 | /* Relocations against symbols are sometimes done in two parts, with a HI |
798 | relocation and a LO relocation. Each relocation has only 16 bits of | |
799 | space to store an addend. This means that in order for the linker to | |
800 | handle carries correctly, it must be able to locate both the HI and | |
801 | the LO relocation. This means that the relocations must appear in | |
802 | order in the relocation table. | |
252b5132 RH |
803 | |
804 | In order to implement this, we keep track of each unmatched HI | |
805 | relocation. We then sort them so that they immediately precede the | |
bdaaa2e1 | 806 | corresponding LO relocation. */ |
252b5132 | 807 | |
e972090a NC |
808 | struct mips_hi_fixup |
809 | { | |
252b5132 RH |
810 | /* Next HI fixup. */ |
811 | struct mips_hi_fixup *next; | |
812 | /* This fixup. */ | |
813 | fixS *fixp; | |
814 | /* The section this fixup is in. */ | |
815 | segT seg; | |
816 | }; | |
817 | ||
818 | /* The list of unmatched HI relocs. */ | |
819 | ||
820 | static struct mips_hi_fixup *mips_hi_fixup_list; | |
821 | ||
64bdfcaf RS |
822 | /* The frag containing the last explicit relocation operator. |
823 | Null if explicit relocations have not been used. */ | |
824 | ||
825 | static fragS *prev_reloc_op_frag; | |
826 | ||
252b5132 RH |
827 | /* Map mips16 register numbers to normal MIPS register numbers. */ |
828 | ||
e972090a NC |
829 | static const unsigned int mips16_to_32_reg_map[] = |
830 | { | |
252b5132 RH |
831 | 16, 17, 2, 3, 4, 5, 6, 7 |
832 | }; | |
60b63b72 | 833 | |
df58fc94 RS |
834 | /* Map microMIPS register numbers to normal MIPS register numbers. */ |
835 | ||
df58fc94 | 836 | #define micromips_to_32_reg_d_map mips16_to_32_reg_map |
df58fc94 RS |
837 | |
838 | /* The microMIPS registers with type h. */ | |
e76ff5ab | 839 | static const unsigned int micromips_to_32_reg_h_map1[] = |
df58fc94 RS |
840 | { |
841 | 5, 5, 6, 4, 4, 4, 4, 4 | |
842 | }; | |
e76ff5ab | 843 | static const unsigned int micromips_to_32_reg_h_map2[] = |
df58fc94 RS |
844 | { |
845 | 6, 7, 7, 21, 22, 5, 6, 7 | |
846 | }; | |
847 | ||
df58fc94 RS |
848 | /* The microMIPS registers with type m. */ |
849 | static const unsigned int micromips_to_32_reg_m_map[] = | |
850 | { | |
851 | 0, 17, 2, 3, 16, 18, 19, 20 | |
852 | }; | |
853 | ||
854 | #define micromips_to_32_reg_n_map micromips_to_32_reg_m_map | |
855 | ||
71400594 RS |
856 | /* Classifies the kind of instructions we're interested in when |
857 | implementing -mfix-vr4120. */ | |
c67a084a NC |
858 | enum fix_vr4120_class |
859 | { | |
71400594 RS |
860 | FIX_VR4120_MACC, |
861 | FIX_VR4120_DMACC, | |
862 | FIX_VR4120_MULT, | |
863 | FIX_VR4120_DMULT, | |
864 | FIX_VR4120_DIV, | |
865 | FIX_VR4120_MTHILO, | |
866 | NUM_FIX_VR4120_CLASSES | |
867 | }; | |
868 | ||
c67a084a NC |
869 | /* ...likewise -mfix-loongson2f-jump. */ |
870 | static bfd_boolean mips_fix_loongson2f_jump; | |
871 | ||
872 | /* ...likewise -mfix-loongson2f-nop. */ | |
873 | static bfd_boolean mips_fix_loongson2f_nop; | |
874 | ||
875 | /* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */ | |
876 | static bfd_boolean mips_fix_loongson2f; | |
877 | ||
71400594 RS |
878 | /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if |
879 | there must be at least one other instruction between an instruction | |
880 | of type X and an instruction of type Y. */ | |
881 | static unsigned int vr4120_conflicts[NUM_FIX_VR4120_CLASSES]; | |
882 | ||
883 | /* True if -mfix-vr4120 is in force. */ | |
d766e8ec | 884 | static int mips_fix_vr4120; |
4a6a3df4 | 885 | |
7d8e00cf RS |
886 | /* ...likewise -mfix-vr4130. */ |
887 | static int mips_fix_vr4130; | |
888 | ||
6a32d874 CM |
889 | /* ...likewise -mfix-24k. */ |
890 | static int mips_fix_24k; | |
891 | ||
a8d14a88 CM |
892 | /* ...likewise -mfix-rm7000 */ |
893 | static int mips_fix_rm7000; | |
894 | ||
d954098f DD |
895 | /* ...likewise -mfix-cn63xxp1 */ |
896 | static bfd_boolean mips_fix_cn63xxp1; | |
897 | ||
4a6a3df4 AO |
898 | /* We don't relax branches by default, since this causes us to expand |
899 | `la .l2 - .l1' if there's a branch between .l1 and .l2, because we | |
900 | fail to compute the offset before expanding the macro to the most | |
901 | efficient expansion. */ | |
902 | ||
903 | static int mips_relax_branch; | |
252b5132 | 904 | \f |
4d7206a2 RS |
905 | /* The expansion of many macros depends on the type of symbol that |
906 | they refer to. For example, when generating position-dependent code, | |
907 | a macro that refers to a symbol may have two different expansions, | |
908 | one which uses GP-relative addresses and one which uses absolute | |
909 | addresses. When generating SVR4-style PIC, a macro may have | |
910 | different expansions for local and global symbols. | |
911 | ||
912 | We handle these situations by generating both sequences and putting | |
913 | them in variant frags. In position-dependent code, the first sequence | |
914 | will be the GP-relative one and the second sequence will be the | |
915 | absolute one. In SVR4 PIC, the first sequence will be for global | |
916 | symbols and the second will be for local symbols. | |
917 | ||
584892a6 RS |
918 | The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and |
919 | SECOND are the lengths of the two sequences in bytes. These fields | |
920 | can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition, | |
921 | the subtype has the following flags: | |
4d7206a2 | 922 | |
584892a6 RS |
923 | RELAX_USE_SECOND |
924 | Set if it has been decided that we should use the second | |
925 | sequence instead of the first. | |
926 | ||
927 | RELAX_SECOND_LONGER | |
928 | Set in the first variant frag if the macro's second implementation | |
929 | is longer than its first. This refers to the macro as a whole, | |
930 | not an individual relaxation. | |
931 | ||
932 | RELAX_NOMACRO | |
933 | Set in the first variant frag if the macro appeared in a .set nomacro | |
934 | block and if one alternative requires a warning but the other does not. | |
935 | ||
936 | RELAX_DELAY_SLOT | |
937 | Like RELAX_NOMACRO, but indicates that the macro appears in a branch | |
938 | delay slot. | |
4d7206a2 | 939 | |
df58fc94 RS |
940 | RELAX_DELAY_SLOT_16BIT |
941 | Like RELAX_DELAY_SLOT, but indicates that the delay slot requires a | |
942 | 16-bit instruction. | |
943 | ||
944 | RELAX_DELAY_SLOT_SIZE_FIRST | |
945 | Like RELAX_DELAY_SLOT, but indicates that the first implementation of | |
946 | the macro is of the wrong size for the branch delay slot. | |
947 | ||
948 | RELAX_DELAY_SLOT_SIZE_SECOND | |
949 | Like RELAX_DELAY_SLOT, but indicates that the second implementation of | |
950 | the macro is of the wrong size for the branch delay slot. | |
951 | ||
4d7206a2 RS |
952 | The frag's "opcode" points to the first fixup for relaxable code. |
953 | ||
954 | Relaxable macros are generated using a sequence such as: | |
955 | ||
956 | relax_start (SYMBOL); | |
957 | ... generate first expansion ... | |
958 | relax_switch (); | |
959 | ... generate second expansion ... | |
960 | relax_end (); | |
961 | ||
962 | The code and fixups for the unwanted alternative are discarded | |
963 | by md_convert_frag. */ | |
584892a6 | 964 | #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND)) |
4d7206a2 | 965 | |
584892a6 RS |
966 | #define RELAX_FIRST(X) (((X) >> 8) & 0xff) |
967 | #define RELAX_SECOND(X) ((X) & 0xff) | |
968 | #define RELAX_USE_SECOND 0x10000 | |
969 | #define RELAX_SECOND_LONGER 0x20000 | |
970 | #define RELAX_NOMACRO 0x40000 | |
971 | #define RELAX_DELAY_SLOT 0x80000 | |
df58fc94 RS |
972 | #define RELAX_DELAY_SLOT_16BIT 0x100000 |
973 | #define RELAX_DELAY_SLOT_SIZE_FIRST 0x200000 | |
974 | #define RELAX_DELAY_SLOT_SIZE_SECOND 0x400000 | |
252b5132 | 975 | |
4a6a3df4 AO |
976 | /* Branch without likely bit. If label is out of range, we turn: |
977 | ||
978 | beq reg1, reg2, label | |
979 | delay slot | |
980 | ||
981 | into | |
982 | ||
983 | bne reg1, reg2, 0f | |
984 | nop | |
985 | j label | |
986 | 0: delay slot | |
987 | ||
988 | with the following opcode replacements: | |
989 | ||
990 | beq <-> bne | |
991 | blez <-> bgtz | |
992 | bltz <-> bgez | |
993 | bc1f <-> bc1t | |
994 | ||
995 | bltzal <-> bgezal (with jal label instead of j label) | |
996 | ||
997 | Even though keeping the delay slot instruction in the delay slot of | |
998 | the branch would be more efficient, it would be very tricky to do | |
999 | correctly, because we'd have to introduce a variable frag *after* | |
1000 | the delay slot instruction, and expand that instead. Let's do it | |
1001 | the easy way for now, even if the branch-not-taken case now costs | |
1002 | one additional instruction. Out-of-range branches are not supposed | |
1003 | to be common, anyway. | |
1004 | ||
1005 | Branch likely. If label is out of range, we turn: | |
1006 | ||
1007 | beql reg1, reg2, label | |
1008 | delay slot (annulled if branch not taken) | |
1009 | ||
1010 | into | |
1011 | ||
1012 | beql reg1, reg2, 1f | |
1013 | nop | |
1014 | beql $0, $0, 2f | |
1015 | nop | |
1016 | 1: j[al] label | |
1017 | delay slot (executed only if branch taken) | |
1018 | 2: | |
1019 | ||
1020 | It would be possible to generate a shorter sequence by losing the | |
1021 | likely bit, generating something like: | |
b34976b6 | 1022 | |
4a6a3df4 AO |
1023 | bne reg1, reg2, 0f |
1024 | nop | |
1025 | j[al] label | |
1026 | delay slot (executed only if branch taken) | |
1027 | 0: | |
1028 | ||
1029 | beql -> bne | |
1030 | bnel -> beq | |
1031 | blezl -> bgtz | |
1032 | bgtzl -> blez | |
1033 | bltzl -> bgez | |
1034 | bgezl -> bltz | |
1035 | bc1fl -> bc1t | |
1036 | bc1tl -> bc1f | |
1037 | ||
1038 | bltzall -> bgezal (with jal label instead of j label) | |
1039 | bgezall -> bltzal (ditto) | |
1040 | ||
1041 | ||
1042 | but it's not clear that it would actually improve performance. */ | |
66b3e8da MR |
1043 | #define RELAX_BRANCH_ENCODE(at, uncond, likely, link, toofar) \ |
1044 | ((relax_substateT) \ | |
1045 | (0xc0000000 \ | |
1046 | | ((at) & 0x1f) \ | |
1047 | | ((toofar) ? 0x20 : 0) \ | |
1048 | | ((link) ? 0x40 : 0) \ | |
1049 | | ((likely) ? 0x80 : 0) \ | |
1050 | | ((uncond) ? 0x100 : 0))) | |
4a6a3df4 | 1051 | #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000) |
66b3e8da MR |
1052 | #define RELAX_BRANCH_UNCOND(i) (((i) & 0x100) != 0) |
1053 | #define RELAX_BRANCH_LIKELY(i) (((i) & 0x80) != 0) | |
1054 | #define RELAX_BRANCH_LINK(i) (((i) & 0x40) != 0) | |
1055 | #define RELAX_BRANCH_TOOFAR(i) (((i) & 0x20) != 0) | |
1056 | #define RELAX_BRANCH_AT(i) ((i) & 0x1f) | |
4a6a3df4 | 1057 | |
252b5132 RH |
1058 | /* For mips16 code, we use an entirely different form of relaxation. |
1059 | mips16 supports two versions of most instructions which take | |
1060 | immediate values: a small one which takes some small value, and a | |
1061 | larger one which takes a 16 bit value. Since branches also follow | |
1062 | this pattern, relaxing these values is required. | |
1063 | ||
1064 | We can assemble both mips16 and normal MIPS code in a single | |
1065 | object. Therefore, we need to support this type of relaxation at | |
1066 | the same time that we support the relaxation described above. We | |
1067 | use the high bit of the subtype field to distinguish these cases. | |
1068 | ||
1069 | The information we store for this type of relaxation is the | |
1070 | argument code found in the opcode file for this relocation, whether | |
1071 | the user explicitly requested a small or extended form, and whether | |
1072 | the relocation is in a jump or jal delay slot. That tells us the | |
1073 | size of the value, and how it should be stored. We also store | |
1074 | whether the fragment is considered to be extended or not. We also | |
1075 | store whether this is known to be a branch to a different section, | |
1076 | whether we have tried to relax this frag yet, and whether we have | |
1077 | ever extended a PC relative fragment because of a shift count. */ | |
1078 | #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \ | |
1079 | (0x80000000 \ | |
1080 | | ((type) & 0xff) \ | |
1081 | | ((small) ? 0x100 : 0) \ | |
1082 | | ((ext) ? 0x200 : 0) \ | |
1083 | | ((dslot) ? 0x400 : 0) \ | |
1084 | | ((jal_dslot) ? 0x800 : 0)) | |
4a6a3df4 | 1085 | #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000) |
252b5132 RH |
1086 | #define RELAX_MIPS16_TYPE(i) ((i) & 0xff) |
1087 | #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0) | |
1088 | #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0) | |
1089 | #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0) | |
1090 | #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0) | |
1091 | #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0) | |
1092 | #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000) | |
1093 | #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000) | |
1094 | #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0) | |
1095 | #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000) | |
1096 | #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000) | |
885add95 | 1097 | |
df58fc94 RS |
1098 | /* For microMIPS code, we use relaxation similar to one we use for |
1099 | MIPS16 code. Some instructions that take immediate values support | |
1100 | two encodings: a small one which takes some small value, and a | |
1101 | larger one which takes a 16 bit value. As some branches also follow | |
1102 | this pattern, relaxing these values is required. | |
1103 | ||
1104 | We can assemble both microMIPS and normal MIPS code in a single | |
1105 | object. Therefore, we need to support this type of relaxation at | |
1106 | the same time that we support the relaxation described above. We | |
1107 | use one of the high bits of the subtype field to distinguish these | |
1108 | cases. | |
1109 | ||
1110 | The information we store for this type of relaxation is the argument | |
1111 | code found in the opcode file for this relocation, the register | |
40209cad MR |
1112 | selected as the assembler temporary, whether the branch is |
1113 | unconditional, whether it is compact, whether it stores the link | |
1114 | address implicitly in $ra, whether relaxation of out-of-range 32-bit | |
1115 | branches to a sequence of instructions is enabled, and whether the | |
1116 | displacement of a branch is too large to fit as an immediate argument | |
1117 | of a 16-bit and a 32-bit branch, respectively. */ | |
1118 | #define RELAX_MICROMIPS_ENCODE(type, at, uncond, compact, link, \ | |
1119 | relax32, toofar16, toofar32) \ | |
1120 | (0x40000000 \ | |
1121 | | ((type) & 0xff) \ | |
1122 | | (((at) & 0x1f) << 8) \ | |
1123 | | ((uncond) ? 0x2000 : 0) \ | |
1124 | | ((compact) ? 0x4000 : 0) \ | |
1125 | | ((link) ? 0x8000 : 0) \ | |
1126 | | ((relax32) ? 0x10000 : 0) \ | |
1127 | | ((toofar16) ? 0x20000 : 0) \ | |
1128 | | ((toofar32) ? 0x40000 : 0)) | |
df58fc94 RS |
1129 | #define RELAX_MICROMIPS_P(i) (((i) & 0xc0000000) == 0x40000000) |
1130 | #define RELAX_MICROMIPS_TYPE(i) ((i) & 0xff) | |
1131 | #define RELAX_MICROMIPS_AT(i) (((i) >> 8) & 0x1f) | |
40209cad MR |
1132 | #define RELAX_MICROMIPS_UNCOND(i) (((i) & 0x2000) != 0) |
1133 | #define RELAX_MICROMIPS_COMPACT(i) (((i) & 0x4000) != 0) | |
1134 | #define RELAX_MICROMIPS_LINK(i) (((i) & 0x8000) != 0) | |
1135 | #define RELAX_MICROMIPS_RELAX32(i) (((i) & 0x10000) != 0) | |
1136 | ||
1137 | #define RELAX_MICROMIPS_TOOFAR16(i) (((i) & 0x20000) != 0) | |
1138 | #define RELAX_MICROMIPS_MARK_TOOFAR16(i) ((i) | 0x20000) | |
1139 | #define RELAX_MICROMIPS_CLEAR_TOOFAR16(i) ((i) & ~0x20000) | |
1140 | #define RELAX_MICROMIPS_TOOFAR32(i) (((i) & 0x40000) != 0) | |
1141 | #define RELAX_MICROMIPS_MARK_TOOFAR32(i) ((i) | 0x40000) | |
1142 | #define RELAX_MICROMIPS_CLEAR_TOOFAR32(i) ((i) & ~0x40000) | |
df58fc94 | 1143 | |
43c0598f RS |
1144 | /* Sign-extend 16-bit value X. */ |
1145 | #define SEXT_16BIT(X) ((((X) + 0x8000) & 0xffff) - 0x8000) | |
1146 | ||
885add95 CD |
1147 | /* Is the given value a sign-extended 32-bit value? */ |
1148 | #define IS_SEXT_32BIT_NUM(x) \ | |
1149 | (((x) &~ (offsetT) 0x7fffffff) == 0 \ | |
1150 | || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff)) | |
1151 | ||
1152 | /* Is the given value a sign-extended 16-bit value? */ | |
1153 | #define IS_SEXT_16BIT_NUM(x) \ | |
1154 | (((x) &~ (offsetT) 0x7fff) == 0 \ | |
1155 | || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff)) | |
1156 | ||
df58fc94 RS |
1157 | /* Is the given value a sign-extended 12-bit value? */ |
1158 | #define IS_SEXT_12BIT_NUM(x) \ | |
1159 | (((((x) & 0xfff) ^ 0x800LL) - 0x800LL) == (x)) | |
1160 | ||
7f3c4072 CM |
1161 | /* Is the given value a sign-extended 9-bit value? */ |
1162 | #define IS_SEXT_9BIT_NUM(x) \ | |
1163 | (((((x) & 0x1ff) ^ 0x100LL) - 0x100LL) == (x)) | |
1164 | ||
2051e8c4 MR |
1165 | /* Is the given value a zero-extended 32-bit value? Or a negated one? */ |
1166 | #define IS_ZEXT_32BIT_NUM(x) \ | |
1167 | (((x) &~ (offsetT) 0xffffffff) == 0 \ | |
1168 | || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff)) | |
1169 | ||
bf12938e RS |
1170 | /* Extract bits MASK << SHIFT from STRUCT and shift them right |
1171 | SHIFT places. */ | |
1172 | #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \ | |
1173 | (((STRUCT) >> (SHIFT)) & (MASK)) | |
1174 | ||
bf12938e | 1175 | /* Extract the operand given by FIELD from mips_cl_insn INSN. */ |
df58fc94 RS |
1176 | #define EXTRACT_OPERAND(MICROMIPS, FIELD, INSN) \ |
1177 | (!(MICROMIPS) \ | |
1178 | ? EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) \ | |
1179 | : EXTRACT_BITS ((INSN).insn_opcode, \ | |
1180 | MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD)) | |
bf12938e RS |
1181 | #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \ |
1182 | EXTRACT_BITS ((INSN).insn_opcode, \ | |
1183 | MIPS16OP_MASK_##FIELD, \ | |
1184 | MIPS16OP_SH_##FIELD) | |
5c04167a RS |
1185 | |
1186 | /* The MIPS16 EXTEND opcode, shifted left 16 places. */ | |
1187 | #define MIPS16_EXTEND (0xf000U << 16) | |
4d7206a2 | 1188 | \f |
df58fc94 RS |
1189 | /* Whether or not we are emitting a branch-likely macro. */ |
1190 | static bfd_boolean emit_branch_likely_macro = FALSE; | |
1191 | ||
4d7206a2 RS |
1192 | /* Global variables used when generating relaxable macros. See the |
1193 | comment above RELAX_ENCODE for more details about how relaxation | |
1194 | is used. */ | |
1195 | static struct { | |
1196 | /* 0 if we're not emitting a relaxable macro. | |
1197 | 1 if we're emitting the first of the two relaxation alternatives. | |
1198 | 2 if we're emitting the second alternative. */ | |
1199 | int sequence; | |
1200 | ||
1201 | /* The first relaxable fixup in the current frag. (In other words, | |
1202 | the first fixup that refers to relaxable code.) */ | |
1203 | fixS *first_fixup; | |
1204 | ||
1205 | /* sizes[0] says how many bytes of the first alternative are stored in | |
1206 | the current frag. Likewise sizes[1] for the second alternative. */ | |
1207 | unsigned int sizes[2]; | |
1208 | ||
1209 | /* The symbol on which the choice of sequence depends. */ | |
1210 | symbolS *symbol; | |
1211 | } mips_relax; | |
252b5132 | 1212 | \f |
584892a6 RS |
1213 | /* Global variables used to decide whether a macro needs a warning. */ |
1214 | static struct { | |
1215 | /* True if the macro is in a branch delay slot. */ | |
1216 | bfd_boolean delay_slot_p; | |
1217 | ||
df58fc94 RS |
1218 | /* Set to the length in bytes required if the macro is in a delay slot |
1219 | that requires a specific length of instruction, otherwise zero. */ | |
1220 | unsigned int delay_slot_length; | |
1221 | ||
584892a6 RS |
1222 | /* For relaxable macros, sizes[0] is the length of the first alternative |
1223 | in bytes and sizes[1] is the length of the second alternative. | |
1224 | For non-relaxable macros, both elements give the length of the | |
1225 | macro in bytes. */ | |
1226 | unsigned int sizes[2]; | |
1227 | ||
df58fc94 RS |
1228 | /* For relaxable macros, first_insn_sizes[0] is the length of the first |
1229 | instruction of the first alternative in bytes and first_insn_sizes[1] | |
1230 | is the length of the first instruction of the second alternative. | |
1231 | For non-relaxable macros, both elements give the length of the first | |
1232 | instruction in bytes. | |
1233 | ||
1234 | Set to zero if we haven't yet seen the first instruction. */ | |
1235 | unsigned int first_insn_sizes[2]; | |
1236 | ||
1237 | /* For relaxable macros, insns[0] is the number of instructions for the | |
1238 | first alternative and insns[1] is the number of instructions for the | |
1239 | second alternative. | |
1240 | ||
1241 | For non-relaxable macros, both elements give the number of | |
1242 | instructions for the macro. */ | |
1243 | unsigned int insns[2]; | |
1244 | ||
584892a6 RS |
1245 | /* The first variant frag for this macro. */ |
1246 | fragS *first_frag; | |
1247 | } mips_macro_warning; | |
1248 | \f | |
252b5132 RH |
1249 | /* Prototypes for static functions. */ |
1250 | ||
252b5132 RH |
1251 | enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG }; |
1252 | ||
b34976b6 | 1253 | static void append_insn |
df58fc94 RS |
1254 | (struct mips_cl_insn *, expressionS *, bfd_reloc_code_real_type *, |
1255 | bfd_boolean expansionp); | |
7d10b47d | 1256 | static void mips_no_prev_insn (void); |
c67a084a | 1257 | static void macro_build (expressionS *, const char *, const char *, ...); |
b34976b6 | 1258 | static void mips16_macro_build |
03ea81db | 1259 | (expressionS *, const char *, const char *, va_list *); |
67c0d1eb | 1260 | static void load_register (int, expressionS *, int); |
584892a6 RS |
1261 | static void macro_start (void); |
1262 | static void macro_end (void); | |
833794fc | 1263 | static void macro (struct mips_cl_insn *ip, char *str); |
17a2f251 | 1264 | static void mips16_macro (struct mips_cl_insn * ip); |
17a2f251 TS |
1265 | static void mips_ip (char *str, struct mips_cl_insn * ip); |
1266 | static void mips16_ip (char *str, struct mips_cl_insn * ip); | |
b34976b6 | 1267 | static void mips16_immed |
43c0598f RS |
1268 | (char *, unsigned int, int, bfd_reloc_code_real_type, offsetT, |
1269 | unsigned int, unsigned long *); | |
5e0116d5 | 1270 | static size_t my_getSmallExpression |
17a2f251 TS |
1271 | (expressionS *, bfd_reloc_code_real_type *, char *); |
1272 | static void my_getExpression (expressionS *, char *); | |
1273 | static void s_align (int); | |
1274 | static void s_change_sec (int); | |
1275 | static void s_change_section (int); | |
1276 | static void s_cons (int); | |
1277 | static void s_float_cons (int); | |
1278 | static void s_mips_globl (int); | |
1279 | static void s_option (int); | |
1280 | static void s_mipsset (int); | |
1281 | static void s_abicalls (int); | |
1282 | static void s_cpload (int); | |
1283 | static void s_cpsetup (int); | |
1284 | static void s_cplocal (int); | |
1285 | static void s_cprestore (int); | |
1286 | static void s_cpreturn (int); | |
741d6ea8 JM |
1287 | static void s_dtprelword (int); |
1288 | static void s_dtpreldword (int); | |
d0f13682 CLT |
1289 | static void s_tprelword (int); |
1290 | static void s_tpreldword (int); | |
17a2f251 TS |
1291 | static void s_gpvalue (int); |
1292 | static void s_gpword (int); | |
1293 | static void s_gpdword (int); | |
a3f278e2 | 1294 | static void s_ehword (int); |
17a2f251 TS |
1295 | static void s_cpadd (int); |
1296 | static void s_insn (int); | |
ba92f887 | 1297 | static void s_nan (int); |
17a2f251 TS |
1298 | static void s_mips_ent (int); |
1299 | static void s_mips_end (int); | |
1300 | static void s_mips_frame (int); | |
1301 | static void s_mips_mask (int reg_type); | |
1302 | static void s_mips_stab (int); | |
1303 | static void s_mips_weakext (int); | |
1304 | static void s_mips_file (int); | |
1305 | static void s_mips_loc (int); | |
1306 | static bfd_boolean pic_need_relax (symbolS *, asection *); | |
4a6a3df4 | 1307 | static int relaxed_branch_length (fragS *, asection *, int); |
df58fc94 RS |
1308 | static int relaxed_micromips_16bit_branch_length (fragS *, asection *, int); |
1309 | static int relaxed_micromips_32bit_branch_length (fragS *, asection *, int); | |
e7af610e NC |
1310 | |
1311 | /* Table and functions used to map between CPU/ISA names, and | |
1312 | ISA levels, and CPU numbers. */ | |
1313 | ||
e972090a NC |
1314 | struct mips_cpu_info |
1315 | { | |
e7af610e | 1316 | const char *name; /* CPU or ISA name. */ |
d16afab6 RS |
1317 | int flags; /* MIPS_CPU_* flags. */ |
1318 | int ase; /* Set of ASEs implemented by the CPU. */ | |
e7af610e NC |
1319 | int isa; /* ISA level. */ |
1320 | int cpu; /* CPU number (default CPU if ISA). */ | |
1321 | }; | |
1322 | ||
ad3fea08 | 1323 | #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */ |
ad3fea08 | 1324 | |
17a2f251 TS |
1325 | static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *); |
1326 | static const struct mips_cpu_info *mips_cpu_info_from_isa (int); | |
1327 | static const struct mips_cpu_info *mips_cpu_info_from_arch (int); | |
252b5132 | 1328 | \f |
c31f3936 RS |
1329 | /* Command-line options. */ |
1330 | const char *md_shortopts = "O::g::G:"; | |
1331 | ||
1332 | enum options | |
1333 | { | |
1334 | OPTION_MARCH = OPTION_MD_BASE, | |
1335 | OPTION_MTUNE, | |
1336 | OPTION_MIPS1, | |
1337 | OPTION_MIPS2, | |
1338 | OPTION_MIPS3, | |
1339 | OPTION_MIPS4, | |
1340 | OPTION_MIPS5, | |
1341 | OPTION_MIPS32, | |
1342 | OPTION_MIPS64, | |
1343 | OPTION_MIPS32R2, | |
ae52f483 AB |
1344 | OPTION_MIPS32R3, |
1345 | OPTION_MIPS32R5, | |
c31f3936 | 1346 | OPTION_MIPS64R2, |
ae52f483 AB |
1347 | OPTION_MIPS64R3, |
1348 | OPTION_MIPS64R5, | |
c31f3936 RS |
1349 | OPTION_MIPS16, |
1350 | OPTION_NO_MIPS16, | |
1351 | OPTION_MIPS3D, | |
1352 | OPTION_NO_MIPS3D, | |
1353 | OPTION_MDMX, | |
1354 | OPTION_NO_MDMX, | |
1355 | OPTION_DSP, | |
1356 | OPTION_NO_DSP, | |
1357 | OPTION_MT, | |
1358 | OPTION_NO_MT, | |
1359 | OPTION_VIRT, | |
1360 | OPTION_NO_VIRT, | |
56d438b1 CF |
1361 | OPTION_MSA, |
1362 | OPTION_NO_MSA, | |
c31f3936 RS |
1363 | OPTION_SMARTMIPS, |
1364 | OPTION_NO_SMARTMIPS, | |
1365 | OPTION_DSPR2, | |
1366 | OPTION_NO_DSPR2, | |
1367 | OPTION_EVA, | |
1368 | OPTION_NO_EVA, | |
7d64c587 AB |
1369 | OPTION_XPA, |
1370 | OPTION_NO_XPA, | |
c31f3936 RS |
1371 | OPTION_MICROMIPS, |
1372 | OPTION_NO_MICROMIPS, | |
1373 | OPTION_MCU, | |
1374 | OPTION_NO_MCU, | |
1375 | OPTION_COMPAT_ARCH_BASE, | |
1376 | OPTION_M4650, | |
1377 | OPTION_NO_M4650, | |
1378 | OPTION_M4010, | |
1379 | OPTION_NO_M4010, | |
1380 | OPTION_M4100, | |
1381 | OPTION_NO_M4100, | |
1382 | OPTION_M3900, | |
1383 | OPTION_NO_M3900, | |
1384 | OPTION_M7000_HILO_FIX, | |
1385 | OPTION_MNO_7000_HILO_FIX, | |
1386 | OPTION_FIX_24K, | |
1387 | OPTION_NO_FIX_24K, | |
a8d14a88 CM |
1388 | OPTION_FIX_RM7000, |
1389 | OPTION_NO_FIX_RM7000, | |
c31f3936 RS |
1390 | OPTION_FIX_LOONGSON2F_JUMP, |
1391 | OPTION_NO_FIX_LOONGSON2F_JUMP, | |
1392 | OPTION_FIX_LOONGSON2F_NOP, | |
1393 | OPTION_NO_FIX_LOONGSON2F_NOP, | |
1394 | OPTION_FIX_VR4120, | |
1395 | OPTION_NO_FIX_VR4120, | |
1396 | OPTION_FIX_VR4130, | |
1397 | OPTION_NO_FIX_VR4130, | |
1398 | OPTION_FIX_CN63XXP1, | |
1399 | OPTION_NO_FIX_CN63XXP1, | |
1400 | OPTION_TRAP, | |
1401 | OPTION_BREAK, | |
1402 | OPTION_EB, | |
1403 | OPTION_EL, | |
1404 | OPTION_FP32, | |
1405 | OPTION_GP32, | |
1406 | OPTION_CONSTRUCT_FLOATS, | |
1407 | OPTION_NO_CONSTRUCT_FLOATS, | |
1408 | OPTION_FP64, | |
1409 | OPTION_GP64, | |
1410 | OPTION_RELAX_BRANCH, | |
1411 | OPTION_NO_RELAX_BRANCH, | |
833794fc MR |
1412 | OPTION_INSN32, |
1413 | OPTION_NO_INSN32, | |
c31f3936 RS |
1414 | OPTION_MSHARED, |
1415 | OPTION_MNO_SHARED, | |
1416 | OPTION_MSYM32, | |
1417 | OPTION_MNO_SYM32, | |
1418 | OPTION_SOFT_FLOAT, | |
1419 | OPTION_HARD_FLOAT, | |
1420 | OPTION_SINGLE_FLOAT, | |
1421 | OPTION_DOUBLE_FLOAT, | |
1422 | OPTION_32, | |
c31f3936 RS |
1423 | OPTION_CALL_SHARED, |
1424 | OPTION_CALL_NONPIC, | |
1425 | OPTION_NON_SHARED, | |
1426 | OPTION_XGOT, | |
1427 | OPTION_MABI, | |
1428 | OPTION_N32, | |
1429 | OPTION_64, | |
1430 | OPTION_MDEBUG, | |
1431 | OPTION_NO_MDEBUG, | |
1432 | OPTION_PDR, | |
1433 | OPTION_NO_PDR, | |
1434 | OPTION_MVXWORKS_PIC, | |
ba92f887 | 1435 | OPTION_NAN, |
c31f3936 RS |
1436 | OPTION_END_OF_ENUM |
1437 | }; | |
1438 | ||
1439 | struct option md_longopts[] = | |
1440 | { | |
1441 | /* Options which specify architecture. */ | |
1442 | {"march", required_argument, NULL, OPTION_MARCH}, | |
1443 | {"mtune", required_argument, NULL, OPTION_MTUNE}, | |
1444 | {"mips0", no_argument, NULL, OPTION_MIPS1}, | |
1445 | {"mips1", no_argument, NULL, OPTION_MIPS1}, | |
1446 | {"mips2", no_argument, NULL, OPTION_MIPS2}, | |
1447 | {"mips3", no_argument, NULL, OPTION_MIPS3}, | |
1448 | {"mips4", no_argument, NULL, OPTION_MIPS4}, | |
1449 | {"mips5", no_argument, NULL, OPTION_MIPS5}, | |
1450 | {"mips32", no_argument, NULL, OPTION_MIPS32}, | |
1451 | {"mips64", no_argument, NULL, OPTION_MIPS64}, | |
1452 | {"mips32r2", no_argument, NULL, OPTION_MIPS32R2}, | |
ae52f483 AB |
1453 | {"mips32r3", no_argument, NULL, OPTION_MIPS32R3}, |
1454 | {"mips32r5", no_argument, NULL, OPTION_MIPS32R5}, | |
c31f3936 | 1455 | {"mips64r2", no_argument, NULL, OPTION_MIPS64R2}, |
ae52f483 AB |
1456 | {"mips64r3", no_argument, NULL, OPTION_MIPS64R3}, |
1457 | {"mips64r5", no_argument, NULL, OPTION_MIPS64R5}, | |
c31f3936 RS |
1458 | |
1459 | /* Options which specify Application Specific Extensions (ASEs). */ | |
1460 | {"mips16", no_argument, NULL, OPTION_MIPS16}, | |
1461 | {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16}, | |
1462 | {"mips3d", no_argument, NULL, OPTION_MIPS3D}, | |
1463 | {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D}, | |
1464 | {"mdmx", no_argument, NULL, OPTION_MDMX}, | |
1465 | {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX}, | |
1466 | {"mdsp", no_argument, NULL, OPTION_DSP}, | |
1467 | {"mno-dsp", no_argument, NULL, OPTION_NO_DSP}, | |
1468 | {"mmt", no_argument, NULL, OPTION_MT}, | |
1469 | {"mno-mt", no_argument, NULL, OPTION_NO_MT}, | |
1470 | {"msmartmips", no_argument, NULL, OPTION_SMARTMIPS}, | |
1471 | {"mno-smartmips", no_argument, NULL, OPTION_NO_SMARTMIPS}, | |
1472 | {"mdspr2", no_argument, NULL, OPTION_DSPR2}, | |
1473 | {"mno-dspr2", no_argument, NULL, OPTION_NO_DSPR2}, | |
1474 | {"meva", no_argument, NULL, OPTION_EVA}, | |
1475 | {"mno-eva", no_argument, NULL, OPTION_NO_EVA}, | |
1476 | {"mmicromips", no_argument, NULL, OPTION_MICROMIPS}, | |
1477 | {"mno-micromips", no_argument, NULL, OPTION_NO_MICROMIPS}, | |
1478 | {"mmcu", no_argument, NULL, OPTION_MCU}, | |
1479 | {"mno-mcu", no_argument, NULL, OPTION_NO_MCU}, | |
1480 | {"mvirt", no_argument, NULL, OPTION_VIRT}, | |
1481 | {"mno-virt", no_argument, NULL, OPTION_NO_VIRT}, | |
56d438b1 CF |
1482 | {"mmsa", no_argument, NULL, OPTION_MSA}, |
1483 | {"mno-msa", no_argument, NULL, OPTION_NO_MSA}, | |
7d64c587 AB |
1484 | {"mxpa", no_argument, NULL, OPTION_XPA}, |
1485 | {"mno-xpa", no_argument, NULL, OPTION_NO_XPA}, | |
c31f3936 RS |
1486 | |
1487 | /* Old-style architecture options. Don't add more of these. */ | |
1488 | {"m4650", no_argument, NULL, OPTION_M4650}, | |
1489 | {"no-m4650", no_argument, NULL, OPTION_NO_M4650}, | |
1490 | {"m4010", no_argument, NULL, OPTION_M4010}, | |
1491 | {"no-m4010", no_argument, NULL, OPTION_NO_M4010}, | |
1492 | {"m4100", no_argument, NULL, OPTION_M4100}, | |
1493 | {"no-m4100", no_argument, NULL, OPTION_NO_M4100}, | |
1494 | {"m3900", no_argument, NULL, OPTION_M3900}, | |
1495 | {"no-m3900", no_argument, NULL, OPTION_NO_M3900}, | |
1496 | ||
1497 | /* Options which enable bug fixes. */ | |
1498 | {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX}, | |
1499 | {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, | |
1500 | {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, | |
1501 | {"mfix-loongson2f-jump", no_argument, NULL, OPTION_FIX_LOONGSON2F_JUMP}, | |
1502 | {"mno-fix-loongson2f-jump", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_JUMP}, | |
1503 | {"mfix-loongson2f-nop", no_argument, NULL, OPTION_FIX_LOONGSON2F_NOP}, | |
1504 | {"mno-fix-loongson2f-nop", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_NOP}, | |
1505 | {"mfix-vr4120", no_argument, NULL, OPTION_FIX_VR4120}, | |
1506 | {"mno-fix-vr4120", no_argument, NULL, OPTION_NO_FIX_VR4120}, | |
1507 | {"mfix-vr4130", no_argument, NULL, OPTION_FIX_VR4130}, | |
1508 | {"mno-fix-vr4130", no_argument, NULL, OPTION_NO_FIX_VR4130}, | |
1509 | {"mfix-24k", no_argument, NULL, OPTION_FIX_24K}, | |
1510 | {"mno-fix-24k", no_argument, NULL, OPTION_NO_FIX_24K}, | |
a8d14a88 CM |
1511 | {"mfix-rm7000", no_argument, NULL, OPTION_FIX_RM7000}, |
1512 | {"mno-fix-rm7000", no_argument, NULL, OPTION_NO_FIX_RM7000}, | |
c31f3936 RS |
1513 | {"mfix-cn63xxp1", no_argument, NULL, OPTION_FIX_CN63XXP1}, |
1514 | {"mno-fix-cn63xxp1", no_argument, NULL, OPTION_NO_FIX_CN63XXP1}, | |
1515 | ||
1516 | /* Miscellaneous options. */ | |
1517 | {"trap", no_argument, NULL, OPTION_TRAP}, | |
1518 | {"no-break", no_argument, NULL, OPTION_TRAP}, | |
1519 | {"break", no_argument, NULL, OPTION_BREAK}, | |
1520 | {"no-trap", no_argument, NULL, OPTION_BREAK}, | |
1521 | {"EB", no_argument, NULL, OPTION_EB}, | |
1522 | {"EL", no_argument, NULL, OPTION_EL}, | |
1523 | {"mfp32", no_argument, NULL, OPTION_FP32}, | |
1524 | {"mgp32", no_argument, NULL, OPTION_GP32}, | |
1525 | {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS}, | |
1526 | {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS}, | |
1527 | {"mfp64", no_argument, NULL, OPTION_FP64}, | |
1528 | {"mgp64", no_argument, NULL, OPTION_GP64}, | |
1529 | {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH}, | |
1530 | {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH}, | |
833794fc MR |
1531 | {"minsn32", no_argument, NULL, OPTION_INSN32}, |
1532 | {"mno-insn32", no_argument, NULL, OPTION_NO_INSN32}, | |
c31f3936 RS |
1533 | {"mshared", no_argument, NULL, OPTION_MSHARED}, |
1534 | {"mno-shared", no_argument, NULL, OPTION_MNO_SHARED}, | |
1535 | {"msym32", no_argument, NULL, OPTION_MSYM32}, | |
1536 | {"mno-sym32", no_argument, NULL, OPTION_MNO_SYM32}, | |
1537 | {"msoft-float", no_argument, NULL, OPTION_SOFT_FLOAT}, | |
1538 | {"mhard-float", no_argument, NULL, OPTION_HARD_FLOAT}, | |
1539 | {"msingle-float", no_argument, NULL, OPTION_SINGLE_FLOAT}, | |
1540 | {"mdouble-float", no_argument, NULL, OPTION_DOUBLE_FLOAT}, | |
1541 | ||
1542 | /* Strictly speaking this next option is ELF specific, | |
1543 | but we allow it for other ports as well in order to | |
1544 | make testing easier. */ | |
1545 | {"32", no_argument, NULL, OPTION_32}, | |
1546 | ||
1547 | /* ELF-specific options. */ | |
c31f3936 RS |
1548 | {"KPIC", no_argument, NULL, OPTION_CALL_SHARED}, |
1549 | {"call_shared", no_argument, NULL, OPTION_CALL_SHARED}, | |
1550 | {"call_nonpic", no_argument, NULL, OPTION_CALL_NONPIC}, | |
1551 | {"non_shared", no_argument, NULL, OPTION_NON_SHARED}, | |
1552 | {"xgot", no_argument, NULL, OPTION_XGOT}, | |
1553 | {"mabi", required_argument, NULL, OPTION_MABI}, | |
1554 | {"n32", no_argument, NULL, OPTION_N32}, | |
1555 | {"64", no_argument, NULL, OPTION_64}, | |
1556 | {"mdebug", no_argument, NULL, OPTION_MDEBUG}, | |
1557 | {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG}, | |
1558 | {"mpdr", no_argument, NULL, OPTION_PDR}, | |
1559 | {"mno-pdr", no_argument, NULL, OPTION_NO_PDR}, | |
1560 | {"mvxworks-pic", no_argument, NULL, OPTION_MVXWORKS_PIC}, | |
ba92f887 | 1561 | {"mnan", required_argument, NULL, OPTION_NAN}, |
c31f3936 RS |
1562 | |
1563 | {NULL, no_argument, NULL, 0} | |
1564 | }; | |
1565 | size_t md_longopts_size = sizeof (md_longopts); | |
1566 | \f | |
c6278170 RS |
1567 | /* Information about either an Application Specific Extension or an |
1568 | optional architecture feature that, for simplicity, we treat in the | |
1569 | same way as an ASE. */ | |
1570 | struct mips_ase | |
1571 | { | |
1572 | /* The name of the ASE, used in both the command-line and .set options. */ | |
1573 | const char *name; | |
1574 | ||
1575 | /* The associated ASE_* flags. If the ASE is available on both 32-bit | |
1576 | and 64-bit architectures, the flags here refer to the subset that | |
1577 | is available on both. */ | |
1578 | unsigned int flags; | |
1579 | ||
1580 | /* The ASE_* flag used for instructions that are available on 64-bit | |
1581 | architectures but that are not included in FLAGS. */ | |
1582 | unsigned int flags64; | |
1583 | ||
1584 | /* The command-line options that turn the ASE on and off. */ | |
1585 | int option_on; | |
1586 | int option_off; | |
1587 | ||
1588 | /* The minimum required architecture revisions for MIPS32, MIPS64, | |
1589 | microMIPS32 and microMIPS64, or -1 if the extension isn't supported. */ | |
1590 | int mips32_rev; | |
1591 | int mips64_rev; | |
1592 | int micromips32_rev; | |
1593 | int micromips64_rev; | |
1594 | }; | |
1595 | ||
1596 | /* A table of all supported ASEs. */ | |
1597 | static const struct mips_ase mips_ases[] = { | |
1598 | { "dsp", ASE_DSP, ASE_DSP64, | |
1599 | OPTION_DSP, OPTION_NO_DSP, | |
1600 | 2, 2, 2, 2 }, | |
1601 | ||
1602 | { "dspr2", ASE_DSP | ASE_DSPR2, 0, | |
1603 | OPTION_DSPR2, OPTION_NO_DSPR2, | |
1604 | 2, 2, 2, 2 }, | |
1605 | ||
1606 | { "eva", ASE_EVA, 0, | |
1607 | OPTION_EVA, OPTION_NO_EVA, | |
1608 | 2, 2, 2, 2 }, | |
1609 | ||
1610 | { "mcu", ASE_MCU, 0, | |
1611 | OPTION_MCU, OPTION_NO_MCU, | |
1612 | 2, 2, 2, 2 }, | |
1613 | ||
1614 | /* Deprecated in MIPS64r5, but we don't implement that yet. */ | |
1615 | { "mdmx", ASE_MDMX, 0, | |
1616 | OPTION_MDMX, OPTION_NO_MDMX, | |
1617 | -1, 1, -1, -1 }, | |
1618 | ||
1619 | /* Requires 64-bit FPRs, so the minimum MIPS32 revision is 2. */ | |
1620 | { "mips3d", ASE_MIPS3D, 0, | |
1621 | OPTION_MIPS3D, OPTION_NO_MIPS3D, | |
1622 | 2, 1, -1, -1 }, | |
1623 | ||
1624 | { "mt", ASE_MT, 0, | |
1625 | OPTION_MT, OPTION_NO_MT, | |
1626 | 2, 2, -1, -1 }, | |
1627 | ||
1628 | { "smartmips", ASE_SMARTMIPS, 0, | |
1629 | OPTION_SMARTMIPS, OPTION_NO_SMARTMIPS, | |
1630 | 1, -1, -1, -1 }, | |
1631 | ||
1632 | { "virt", ASE_VIRT, ASE_VIRT64, | |
1633 | OPTION_VIRT, OPTION_NO_VIRT, | |
56d438b1 CF |
1634 | 2, 2, 2, 2 }, |
1635 | ||
1636 | { "msa", ASE_MSA, ASE_MSA64, | |
1637 | OPTION_MSA, OPTION_NO_MSA, | |
7d64c587 AB |
1638 | 2, 2, 2, 2 }, |
1639 | ||
1640 | { "xpa", ASE_XPA, 0, | |
1641 | OPTION_XPA, OPTION_NO_XPA, | |
1642 | 2, 2, -1, -1 } | |
c6278170 RS |
1643 | }; |
1644 | ||
1645 | /* The set of ASEs that require -mfp64. */ | |
1646 | #define FP64_ASES (ASE_MIPS3D | ASE_MDMX) | |
1647 | ||
1648 | /* Groups of ASE_* flags that represent different revisions of an ASE. */ | |
1649 | static const unsigned int mips_ase_groups[] = { | |
1650 | ASE_DSP | ASE_DSPR2 | |
1651 | }; | |
1652 | \f | |
252b5132 RH |
1653 | /* Pseudo-op table. |
1654 | ||
1655 | The following pseudo-ops from the Kane and Heinrich MIPS book | |
1656 | should be defined here, but are currently unsupported: .alias, | |
1657 | .galive, .gjaldef, .gjrlive, .livereg, .noalias. | |
1658 | ||
1659 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
1660 | specific to the type of debugging information being generated, and | |
1661 | should be defined by the object format: .aent, .begin, .bend, | |
1662 | .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp, | |
1663 | .vreg. | |
1664 | ||
1665 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
1666 | not MIPS CPU specific, but are also not specific to the object file | |
1667 | format. This file is probably the best place to define them, but | |
d84bcf09 | 1668 | they are not currently supported: .asm0, .endr, .lab, .struct. */ |
252b5132 | 1669 | |
e972090a NC |
1670 | static const pseudo_typeS mips_pseudo_table[] = |
1671 | { | |
beae10d5 | 1672 | /* MIPS specific pseudo-ops. */ |
252b5132 RH |
1673 | {"option", s_option, 0}, |
1674 | {"set", s_mipsset, 0}, | |
1675 | {"rdata", s_change_sec, 'r'}, | |
1676 | {"sdata", s_change_sec, 's'}, | |
1677 | {"livereg", s_ignore, 0}, | |
1678 | {"abicalls", s_abicalls, 0}, | |
1679 | {"cpload", s_cpload, 0}, | |
6478892d TS |
1680 | {"cpsetup", s_cpsetup, 0}, |
1681 | {"cplocal", s_cplocal, 0}, | |
252b5132 | 1682 | {"cprestore", s_cprestore, 0}, |
6478892d | 1683 | {"cpreturn", s_cpreturn, 0}, |
741d6ea8 JM |
1684 | {"dtprelword", s_dtprelword, 0}, |
1685 | {"dtpreldword", s_dtpreldword, 0}, | |
d0f13682 CLT |
1686 | {"tprelword", s_tprelword, 0}, |
1687 | {"tpreldword", s_tpreldword, 0}, | |
6478892d | 1688 | {"gpvalue", s_gpvalue, 0}, |
252b5132 | 1689 | {"gpword", s_gpword, 0}, |
10181a0d | 1690 | {"gpdword", s_gpdword, 0}, |
a3f278e2 | 1691 | {"ehword", s_ehword, 0}, |
252b5132 RH |
1692 | {"cpadd", s_cpadd, 0}, |
1693 | {"insn", s_insn, 0}, | |
ba92f887 | 1694 | {"nan", s_nan, 0}, |
252b5132 | 1695 | |
beae10d5 | 1696 | /* Relatively generic pseudo-ops that happen to be used on MIPS |
252b5132 | 1697 | chips. */ |
38a57ae7 | 1698 | {"asciiz", stringer, 8 + 1}, |
252b5132 RH |
1699 | {"bss", s_change_sec, 'b'}, |
1700 | {"err", s_err, 0}, | |
1701 | {"half", s_cons, 1}, | |
1702 | {"dword", s_cons, 3}, | |
1703 | {"weakext", s_mips_weakext, 0}, | |
7c752c2a TS |
1704 | {"origin", s_org, 0}, |
1705 | {"repeat", s_rept, 0}, | |
252b5132 | 1706 | |
998b3c36 MR |
1707 | /* For MIPS this is non-standard, but we define it for consistency. */ |
1708 | {"sbss", s_change_sec, 'B'}, | |
1709 | ||
beae10d5 | 1710 | /* These pseudo-ops are defined in read.c, but must be overridden |
252b5132 RH |
1711 | here for one reason or another. */ |
1712 | {"align", s_align, 0}, | |
1713 | {"byte", s_cons, 0}, | |
1714 | {"data", s_change_sec, 'd'}, | |
1715 | {"double", s_float_cons, 'd'}, | |
1716 | {"float", s_float_cons, 'f'}, | |
1717 | {"globl", s_mips_globl, 0}, | |
1718 | {"global", s_mips_globl, 0}, | |
1719 | {"hword", s_cons, 1}, | |
1720 | {"int", s_cons, 2}, | |
1721 | {"long", s_cons, 2}, | |
1722 | {"octa", s_cons, 4}, | |
1723 | {"quad", s_cons, 3}, | |
cca86cc8 | 1724 | {"section", s_change_section, 0}, |
252b5132 RH |
1725 | {"short", s_cons, 1}, |
1726 | {"single", s_float_cons, 'f'}, | |
754e2bb9 | 1727 | {"stabd", s_mips_stab, 'd'}, |
252b5132 | 1728 | {"stabn", s_mips_stab, 'n'}, |
754e2bb9 | 1729 | {"stabs", s_mips_stab, 's'}, |
252b5132 RH |
1730 | {"text", s_change_sec, 't'}, |
1731 | {"word", s_cons, 2}, | |
add56521 | 1732 | |
add56521 | 1733 | { "extern", ecoff_directive_extern, 0}, |
add56521 | 1734 | |
43841e91 | 1735 | { NULL, NULL, 0 }, |
252b5132 RH |
1736 | }; |
1737 | ||
e972090a NC |
1738 | static const pseudo_typeS mips_nonecoff_pseudo_table[] = |
1739 | { | |
beae10d5 KH |
1740 | /* These pseudo-ops should be defined by the object file format. |
1741 | However, a.out doesn't support them, so we have versions here. */ | |
252b5132 RH |
1742 | {"aent", s_mips_ent, 1}, |
1743 | {"bgnb", s_ignore, 0}, | |
1744 | {"end", s_mips_end, 0}, | |
1745 | {"endb", s_ignore, 0}, | |
1746 | {"ent", s_mips_ent, 0}, | |
c5dd6aab | 1747 | {"file", s_mips_file, 0}, |
252b5132 RH |
1748 | {"fmask", s_mips_mask, 'F'}, |
1749 | {"frame", s_mips_frame, 0}, | |
c5dd6aab | 1750 | {"loc", s_mips_loc, 0}, |
252b5132 RH |
1751 | {"mask", s_mips_mask, 'R'}, |
1752 | {"verstamp", s_ignore, 0}, | |
43841e91 | 1753 | { NULL, NULL, 0 }, |
252b5132 RH |
1754 | }; |
1755 | ||
3ae8dd8d MR |
1756 | /* Export the ABI address size for use by TC_ADDRESS_BYTES for the |
1757 | purpose of the `.dc.a' internal pseudo-op. */ | |
1758 | ||
1759 | int | |
1760 | mips_address_bytes (void) | |
1761 | { | |
1762 | return HAVE_64BIT_ADDRESSES ? 8 : 4; | |
1763 | } | |
1764 | ||
17a2f251 | 1765 | extern void pop_insert (const pseudo_typeS *); |
252b5132 RH |
1766 | |
1767 | void | |
17a2f251 | 1768 | mips_pop_insert (void) |
252b5132 RH |
1769 | { |
1770 | pop_insert (mips_pseudo_table); | |
1771 | if (! ECOFF_DEBUGGING) | |
1772 | pop_insert (mips_nonecoff_pseudo_table); | |
1773 | } | |
1774 | \f | |
1775 | /* Symbols labelling the current insn. */ | |
1776 | ||
e972090a NC |
1777 | struct insn_label_list |
1778 | { | |
252b5132 RH |
1779 | struct insn_label_list *next; |
1780 | symbolS *label; | |
1781 | }; | |
1782 | ||
252b5132 | 1783 | static struct insn_label_list *free_insn_labels; |
742a56fe | 1784 | #define label_list tc_segment_info_data.labels |
252b5132 | 1785 | |
17a2f251 | 1786 | static void mips_clear_insn_labels (void); |
df58fc94 RS |
1787 | static void mips_mark_labels (void); |
1788 | static void mips_compressed_mark_labels (void); | |
252b5132 RH |
1789 | |
1790 | static inline void | |
17a2f251 | 1791 | mips_clear_insn_labels (void) |
252b5132 RH |
1792 | { |
1793 | register struct insn_label_list **pl; | |
a8dbcb85 | 1794 | segment_info_type *si; |
252b5132 | 1795 | |
a8dbcb85 TS |
1796 | if (now_seg) |
1797 | { | |
1798 | for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next) | |
1799 | ; | |
1800 | ||
1801 | si = seg_info (now_seg); | |
1802 | *pl = si->label_list; | |
1803 | si->label_list = NULL; | |
1804 | } | |
252b5132 | 1805 | } |
a8dbcb85 | 1806 | |
df58fc94 RS |
1807 | /* Mark instruction labels in MIPS16/microMIPS mode. */ |
1808 | ||
1809 | static inline void | |
1810 | mips_mark_labels (void) | |
1811 | { | |
1812 | if (HAVE_CODE_COMPRESSION) | |
1813 | mips_compressed_mark_labels (); | |
1814 | } | |
252b5132 RH |
1815 | \f |
1816 | static char *expr_end; | |
1817 | ||
e423441d | 1818 | /* An expression in a macro instruction. This is set by mips_ip and |
b0e6f033 | 1819 | mips16_ip and when populated is always an O_constant. */ |
252b5132 RH |
1820 | |
1821 | static expressionS imm_expr; | |
252b5132 | 1822 | |
77bd4346 RS |
1823 | /* The relocatable field in an instruction and the relocs associated |
1824 | with it. These variables are used for instructions like LUI and | |
1825 | JAL as well as true offsets. They are also used for address | |
1826 | operands in macros. */ | |
252b5132 | 1827 | |
77bd4346 | 1828 | static expressionS offset_expr; |
f6688943 TS |
1829 | static bfd_reloc_code_real_type offset_reloc[3] |
1830 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 1831 | |
df58fc94 RS |
1832 | /* This is set to the resulting size of the instruction to be produced |
1833 | by mips16_ip if an explicit extension is used or by mips_ip if an | |
1834 | explicit size is supplied. */ | |
252b5132 | 1835 | |
df58fc94 | 1836 | static unsigned int forced_insn_length; |
252b5132 | 1837 | |
e1b47bd5 RS |
1838 | /* True if we are assembling an instruction. All dot symbols defined during |
1839 | this time should be treated as code labels. */ | |
1840 | ||
1841 | static bfd_boolean mips_assembling_insn; | |
1842 | ||
ecb4347a DJ |
1843 | /* The pdr segment for per procedure frame/regmask info. Not used for |
1844 | ECOFF debugging. */ | |
252b5132 RH |
1845 | |
1846 | static segT pdr_seg; | |
252b5132 | 1847 | |
e013f690 TS |
1848 | /* The default target format to use. */ |
1849 | ||
aeffff67 RS |
1850 | #if defined (TE_FreeBSD) |
1851 | #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd" | |
1852 | #elif defined (TE_TMIPS) | |
1853 | #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips" | |
1854 | #else | |
1855 | #define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips" | |
1856 | #endif | |
1857 | ||
e013f690 | 1858 | const char * |
17a2f251 | 1859 | mips_target_format (void) |
e013f690 TS |
1860 | { |
1861 | switch (OUTPUT_FLAVOR) | |
1862 | { | |
e013f690 | 1863 | case bfd_target_elf_flavour: |
0a44bf69 RS |
1864 | #ifdef TE_VXWORKS |
1865 | if (!HAVE_64BIT_OBJECTS && !HAVE_NEWABI) | |
1866 | return (target_big_endian | |
1867 | ? "elf32-bigmips-vxworks" | |
1868 | : "elf32-littlemips-vxworks"); | |
1869 | #endif | |
e013f690 | 1870 | return (target_big_endian |
cfe86eaa | 1871 | ? (HAVE_64BIT_OBJECTS |
aeffff67 | 1872 | ? ELF_TARGET ("elf64-", "big") |
cfe86eaa | 1873 | : (HAVE_NEWABI |
aeffff67 RS |
1874 | ? ELF_TARGET ("elf32-n", "big") |
1875 | : ELF_TARGET ("elf32-", "big"))) | |
cfe86eaa | 1876 | : (HAVE_64BIT_OBJECTS |
aeffff67 | 1877 | ? ELF_TARGET ("elf64-", "little") |
cfe86eaa | 1878 | : (HAVE_NEWABI |
aeffff67 RS |
1879 | ? ELF_TARGET ("elf32-n", "little") |
1880 | : ELF_TARGET ("elf32-", "little")))); | |
e013f690 TS |
1881 | default: |
1882 | abort (); | |
1883 | return NULL; | |
1884 | } | |
1885 | } | |
1886 | ||
c6278170 RS |
1887 | /* Return the ISA revision that is currently in use, or 0 if we are |
1888 | generating code for MIPS V or below. */ | |
1889 | ||
1890 | static int | |
1891 | mips_isa_rev (void) | |
1892 | { | |
1893 | if (mips_opts.isa == ISA_MIPS32R2 || mips_opts.isa == ISA_MIPS64R2) | |
1894 | return 2; | |
1895 | ||
ae52f483 AB |
1896 | if (mips_opts.isa == ISA_MIPS32R3 || mips_opts.isa == ISA_MIPS64R3) |
1897 | return 3; | |
1898 | ||
1899 | if (mips_opts.isa == ISA_MIPS32R5 || mips_opts.isa == ISA_MIPS64R5) | |
1900 | return 5; | |
1901 | ||
c6278170 RS |
1902 | /* microMIPS implies revision 2 or above. */ |
1903 | if (mips_opts.micromips) | |
1904 | return 2; | |
1905 | ||
1906 | if (mips_opts.isa == ISA_MIPS32 || mips_opts.isa == ISA_MIPS64) | |
1907 | return 1; | |
1908 | ||
1909 | return 0; | |
1910 | } | |
1911 | ||
1912 | /* Return the mask of all ASEs that are revisions of those in FLAGS. */ | |
1913 | ||
1914 | static unsigned int | |
1915 | mips_ase_mask (unsigned int flags) | |
1916 | { | |
1917 | unsigned int i; | |
1918 | ||
1919 | for (i = 0; i < ARRAY_SIZE (mips_ase_groups); i++) | |
1920 | if (flags & mips_ase_groups[i]) | |
1921 | flags |= mips_ase_groups[i]; | |
1922 | return flags; | |
1923 | } | |
1924 | ||
1925 | /* Check whether the current ISA supports ASE. Issue a warning if | |
1926 | appropriate. */ | |
1927 | ||
1928 | static void | |
1929 | mips_check_isa_supports_ase (const struct mips_ase *ase) | |
1930 | { | |
1931 | const char *base; | |
1932 | int min_rev, size; | |
1933 | static unsigned int warned_isa; | |
1934 | static unsigned int warned_fp32; | |
1935 | ||
1936 | if (ISA_HAS_64BIT_REGS (mips_opts.isa)) | |
1937 | min_rev = mips_opts.micromips ? ase->micromips64_rev : ase->mips64_rev; | |
1938 | else | |
1939 | min_rev = mips_opts.micromips ? ase->micromips32_rev : ase->mips32_rev; | |
1940 | if ((min_rev < 0 || mips_isa_rev () < min_rev) | |
1941 | && (warned_isa & ase->flags) != ase->flags) | |
1942 | { | |
1943 | warned_isa |= ase->flags; | |
1944 | base = mips_opts.micromips ? "microMIPS" : "MIPS"; | |
1945 | size = ISA_HAS_64BIT_REGS (mips_opts.isa) ? 64 : 32; | |
1946 | if (min_rev < 0) | |
1661c76c | 1947 | as_warn (_("the %d-bit %s architecture does not support the" |
c6278170 RS |
1948 | " `%s' extension"), size, base, ase->name); |
1949 | else | |
1661c76c | 1950 | as_warn (_("the `%s' extension requires %s%d revision %d or greater"), |
c6278170 RS |
1951 | ase->name, base, size, min_rev); |
1952 | } | |
1953 | if ((ase->flags & FP64_ASES) | |
0b35dfee | 1954 | && mips_opts.fp != 64 |
c6278170 RS |
1955 | && (warned_fp32 & ase->flags) != ase->flags) |
1956 | { | |
1957 | warned_fp32 |= ase->flags; | |
1661c76c | 1958 | as_warn (_("the `%s' extension requires 64-bit FPRs"), ase->name); |
c6278170 RS |
1959 | } |
1960 | } | |
1961 | ||
1962 | /* Check all enabled ASEs to see whether they are supported by the | |
1963 | chosen architecture. */ | |
1964 | ||
1965 | static void | |
1966 | mips_check_isa_supports_ases (void) | |
1967 | { | |
1968 | unsigned int i, mask; | |
1969 | ||
1970 | for (i = 0; i < ARRAY_SIZE (mips_ases); i++) | |
1971 | { | |
1972 | mask = mips_ase_mask (mips_ases[i].flags); | |
1973 | if ((mips_opts.ase & mask) == mips_ases[i].flags) | |
1974 | mips_check_isa_supports_ase (&mips_ases[i]); | |
1975 | } | |
1976 | } | |
1977 | ||
1978 | /* Set the state of ASE to ENABLED_P. Return the mask of ASE_* flags | |
1979 | that were affected. */ | |
1980 | ||
1981 | static unsigned int | |
1982 | mips_set_ase (const struct mips_ase *ase, bfd_boolean enabled_p) | |
1983 | { | |
1984 | unsigned int mask; | |
1985 | ||
1986 | mask = mips_ase_mask (ase->flags); | |
1987 | mips_opts.ase &= ~mask; | |
1988 | if (enabled_p) | |
1989 | mips_opts.ase |= ase->flags; | |
1990 | return mask; | |
1991 | } | |
1992 | ||
1993 | /* Return the ASE called NAME, or null if none. */ | |
1994 | ||
1995 | static const struct mips_ase * | |
1996 | mips_lookup_ase (const char *name) | |
1997 | { | |
1998 | unsigned int i; | |
1999 | ||
2000 | for (i = 0; i < ARRAY_SIZE (mips_ases); i++) | |
2001 | if (strcmp (name, mips_ases[i].name) == 0) | |
2002 | return &mips_ases[i]; | |
2003 | return NULL; | |
2004 | } | |
2005 | ||
df58fc94 RS |
2006 | /* Return the length of a microMIPS instruction in bytes. If bits of |
2007 | the mask beyond the low 16 are 0, then it is a 16-bit instruction. | |
2008 | Otherwise assume a 32-bit instruction; 48-bit instructions (0x1f | |
2009 | major opcode) will require further modifications to the opcode | |
2010 | table. */ | |
2011 | ||
2012 | static inline unsigned int | |
2013 | micromips_insn_length (const struct mips_opcode *mo) | |
2014 | { | |
2015 | return (mo->mask >> 16) == 0 ? 2 : 4; | |
2016 | } | |
2017 | ||
5c04167a RS |
2018 | /* Return the length of MIPS16 instruction OPCODE. */ |
2019 | ||
2020 | static inline unsigned int | |
2021 | mips16_opcode_length (unsigned long opcode) | |
2022 | { | |
2023 | return (opcode >> 16) == 0 ? 2 : 4; | |
2024 | } | |
2025 | ||
1e915849 RS |
2026 | /* Return the length of instruction INSN. */ |
2027 | ||
2028 | static inline unsigned int | |
2029 | insn_length (const struct mips_cl_insn *insn) | |
2030 | { | |
df58fc94 RS |
2031 | if (mips_opts.micromips) |
2032 | return micromips_insn_length (insn->insn_mo); | |
2033 | else if (mips_opts.mips16) | |
5c04167a | 2034 | return mips16_opcode_length (insn->insn_opcode); |
df58fc94 | 2035 | else |
1e915849 | 2036 | return 4; |
1e915849 RS |
2037 | } |
2038 | ||
2039 | /* Initialise INSN from opcode entry MO. Leave its position unspecified. */ | |
2040 | ||
2041 | static void | |
2042 | create_insn (struct mips_cl_insn *insn, const struct mips_opcode *mo) | |
2043 | { | |
2044 | size_t i; | |
2045 | ||
2046 | insn->insn_mo = mo; | |
1e915849 RS |
2047 | insn->insn_opcode = mo->match; |
2048 | insn->frag = NULL; | |
2049 | insn->where = 0; | |
2050 | for (i = 0; i < ARRAY_SIZE (insn->fixp); i++) | |
2051 | insn->fixp[i] = NULL; | |
2052 | insn->fixed_p = (mips_opts.noreorder > 0); | |
2053 | insn->noreorder_p = (mips_opts.noreorder > 0); | |
2054 | insn->mips16_absolute_jump_p = 0; | |
15be625d | 2055 | insn->complete_p = 0; |
e407c74b | 2056 | insn->cleared_p = 0; |
1e915849 RS |
2057 | } |
2058 | ||
fc76e730 RS |
2059 | /* Get a list of all the operands in INSN. */ |
2060 | ||
2061 | static const struct mips_operand_array * | |
2062 | insn_operands (const struct mips_cl_insn *insn) | |
2063 | { | |
2064 | if (insn->insn_mo >= &mips_opcodes[0] | |
2065 | && insn->insn_mo < &mips_opcodes[NUMOPCODES]) | |
2066 | return &mips_operands[insn->insn_mo - &mips_opcodes[0]]; | |
2067 | ||
2068 | if (insn->insn_mo >= &mips16_opcodes[0] | |
2069 | && insn->insn_mo < &mips16_opcodes[bfd_mips16_num_opcodes]) | |
2070 | return &mips16_operands[insn->insn_mo - &mips16_opcodes[0]]; | |
2071 | ||
2072 | if (insn->insn_mo >= µmips_opcodes[0] | |
2073 | && insn->insn_mo < µmips_opcodes[bfd_micromips_num_opcodes]) | |
2074 | return µmips_operands[insn->insn_mo - µmips_opcodes[0]]; | |
2075 | ||
2076 | abort (); | |
2077 | } | |
2078 | ||
2079 | /* Get a description of operand OPNO of INSN. */ | |
2080 | ||
2081 | static const struct mips_operand * | |
2082 | insn_opno (const struct mips_cl_insn *insn, unsigned opno) | |
2083 | { | |
2084 | const struct mips_operand_array *operands; | |
2085 | ||
2086 | operands = insn_operands (insn); | |
2087 | if (opno >= MAX_OPERANDS || !operands->operand[opno]) | |
2088 | abort (); | |
2089 | return operands->operand[opno]; | |
2090 | } | |
2091 | ||
e077a1c8 RS |
2092 | /* Install UVAL as the value of OPERAND in INSN. */ |
2093 | ||
2094 | static inline void | |
2095 | insn_insert_operand (struct mips_cl_insn *insn, | |
2096 | const struct mips_operand *operand, unsigned int uval) | |
2097 | { | |
2098 | insn->insn_opcode = mips_insert_operand (operand, insn->insn_opcode, uval); | |
2099 | } | |
2100 | ||
fc76e730 RS |
2101 | /* Extract the value of OPERAND from INSN. */ |
2102 | ||
2103 | static inline unsigned | |
2104 | insn_extract_operand (const struct mips_cl_insn *insn, | |
2105 | const struct mips_operand *operand) | |
2106 | { | |
2107 | return mips_extract_operand (operand, insn->insn_opcode); | |
2108 | } | |
2109 | ||
df58fc94 | 2110 | /* Record the current MIPS16/microMIPS mode in now_seg. */ |
742a56fe RS |
2111 | |
2112 | static void | |
df58fc94 | 2113 | mips_record_compressed_mode (void) |
742a56fe RS |
2114 | { |
2115 | segment_info_type *si; | |
2116 | ||
2117 | si = seg_info (now_seg); | |
2118 | if (si->tc_segment_info_data.mips16 != mips_opts.mips16) | |
2119 | si->tc_segment_info_data.mips16 = mips_opts.mips16; | |
df58fc94 RS |
2120 | if (si->tc_segment_info_data.micromips != mips_opts.micromips) |
2121 | si->tc_segment_info_data.micromips = mips_opts.micromips; | |
742a56fe RS |
2122 | } |
2123 | ||
4d68580a RS |
2124 | /* Read a standard MIPS instruction from BUF. */ |
2125 | ||
2126 | static unsigned long | |
2127 | read_insn (char *buf) | |
2128 | { | |
2129 | if (target_big_endian) | |
2130 | return bfd_getb32 ((bfd_byte *) buf); | |
2131 | else | |
2132 | return bfd_getl32 ((bfd_byte *) buf); | |
2133 | } | |
2134 | ||
2135 | /* Write standard MIPS instruction INSN to BUF. Return a pointer to | |
2136 | the next byte. */ | |
2137 | ||
2138 | static char * | |
2139 | write_insn (char *buf, unsigned int insn) | |
2140 | { | |
2141 | md_number_to_chars (buf, insn, 4); | |
2142 | return buf + 4; | |
2143 | } | |
2144 | ||
2145 | /* Read a microMIPS or MIPS16 opcode from BUF, given that it | |
2146 | has length LENGTH. */ | |
2147 | ||
2148 | static unsigned long | |
2149 | read_compressed_insn (char *buf, unsigned int length) | |
2150 | { | |
2151 | unsigned long insn; | |
2152 | unsigned int i; | |
2153 | ||
2154 | insn = 0; | |
2155 | for (i = 0; i < length; i += 2) | |
2156 | { | |
2157 | insn <<= 16; | |
2158 | if (target_big_endian) | |
2159 | insn |= bfd_getb16 ((char *) buf); | |
2160 | else | |
2161 | insn |= bfd_getl16 ((char *) buf); | |
2162 | buf += 2; | |
2163 | } | |
2164 | return insn; | |
2165 | } | |
2166 | ||
5c04167a RS |
2167 | /* Write microMIPS or MIPS16 instruction INSN to BUF, given that the |
2168 | instruction is LENGTH bytes long. Return a pointer to the next byte. */ | |
2169 | ||
2170 | static char * | |
2171 | write_compressed_insn (char *buf, unsigned int insn, unsigned int length) | |
2172 | { | |
2173 | unsigned int i; | |
2174 | ||
2175 | for (i = 0; i < length; i += 2) | |
2176 | md_number_to_chars (buf + i, insn >> ((length - i - 2) * 8), 2); | |
2177 | return buf + length; | |
2178 | } | |
2179 | ||
1e915849 RS |
2180 | /* Install INSN at the location specified by its "frag" and "where" fields. */ |
2181 | ||
2182 | static void | |
2183 | install_insn (const struct mips_cl_insn *insn) | |
2184 | { | |
2185 | char *f = insn->frag->fr_literal + insn->where; | |
5c04167a RS |
2186 | if (HAVE_CODE_COMPRESSION) |
2187 | write_compressed_insn (f, insn->insn_opcode, insn_length (insn)); | |
1e915849 | 2188 | else |
4d68580a | 2189 | write_insn (f, insn->insn_opcode); |
df58fc94 | 2190 | mips_record_compressed_mode (); |
1e915849 RS |
2191 | } |
2192 | ||
2193 | /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly | |
2194 | and install the opcode in the new location. */ | |
2195 | ||
2196 | static void | |
2197 | move_insn (struct mips_cl_insn *insn, fragS *frag, long where) | |
2198 | { | |
2199 | size_t i; | |
2200 | ||
2201 | insn->frag = frag; | |
2202 | insn->where = where; | |
2203 | for (i = 0; i < ARRAY_SIZE (insn->fixp); i++) | |
2204 | if (insn->fixp[i] != NULL) | |
2205 | { | |
2206 | insn->fixp[i]->fx_frag = frag; | |
2207 | insn->fixp[i]->fx_where = where; | |
2208 | } | |
2209 | install_insn (insn); | |
2210 | } | |
2211 | ||
2212 | /* Add INSN to the end of the output. */ | |
2213 | ||
2214 | static void | |
2215 | add_fixed_insn (struct mips_cl_insn *insn) | |
2216 | { | |
2217 | char *f = frag_more (insn_length (insn)); | |
2218 | move_insn (insn, frag_now, f - frag_now->fr_literal); | |
2219 | } | |
2220 | ||
2221 | /* Start a variant frag and move INSN to the start of the variant part, | |
2222 | marking it as fixed. The other arguments are as for frag_var. */ | |
2223 | ||
2224 | static void | |
2225 | add_relaxed_insn (struct mips_cl_insn *insn, int max_chars, int var, | |
2226 | relax_substateT subtype, symbolS *symbol, offsetT offset) | |
2227 | { | |
2228 | frag_grow (max_chars); | |
2229 | move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal); | |
2230 | insn->fixed_p = 1; | |
2231 | frag_var (rs_machine_dependent, max_chars, var, | |
2232 | subtype, symbol, offset, NULL); | |
2233 | } | |
2234 | ||
2235 | /* Insert N copies of INSN into the history buffer, starting at | |
2236 | position FIRST. Neither FIRST nor N need to be clipped. */ | |
2237 | ||
2238 | static void | |
2239 | insert_into_history (unsigned int first, unsigned int n, | |
2240 | const struct mips_cl_insn *insn) | |
2241 | { | |
2242 | if (mips_relax.sequence != 2) | |
2243 | { | |
2244 | unsigned int i; | |
2245 | ||
2246 | for (i = ARRAY_SIZE (history); i-- > first;) | |
2247 | if (i >= first + n) | |
2248 | history[i] = history[i - n]; | |
2249 | else | |
2250 | history[i] = *insn; | |
2251 | } | |
2252 | } | |
2253 | ||
e3de51ce RS |
2254 | /* Clear the error in insn_error. */ |
2255 | ||
2256 | static void | |
2257 | clear_insn_error (void) | |
2258 | { | |
2259 | memset (&insn_error, 0, sizeof (insn_error)); | |
2260 | } | |
2261 | ||
2262 | /* Possibly record error message MSG for the current instruction. | |
2263 | If the error is about a particular argument, ARGNUM is the 1-based | |
2264 | number of that argument, otherwise it is 0. FORMAT is the format | |
2265 | of MSG. Return true if MSG was used, false if the current message | |
2266 | was kept. */ | |
2267 | ||
2268 | static bfd_boolean | |
2269 | set_insn_error_format (int argnum, enum mips_insn_error_format format, | |
2270 | const char *msg) | |
2271 | { | |
2272 | if (argnum == 0) | |
2273 | { | |
2274 | /* Give priority to errors against specific arguments, and to | |
2275 | the first whole-instruction message. */ | |
2276 | if (insn_error.msg) | |
2277 | return FALSE; | |
2278 | } | |
2279 | else | |
2280 | { | |
2281 | /* Keep insn_error if it is against a later argument. */ | |
2282 | if (argnum < insn_error.min_argnum) | |
2283 | return FALSE; | |
2284 | ||
2285 | /* If both errors are against the same argument but are different, | |
2286 | give up on reporting a specific error for this argument. | |
2287 | See the comment about mips_insn_error for details. */ | |
2288 | if (argnum == insn_error.min_argnum | |
2289 | && insn_error.msg | |
2290 | && strcmp (insn_error.msg, msg) != 0) | |
2291 | { | |
2292 | insn_error.msg = 0; | |
2293 | insn_error.min_argnum += 1; | |
2294 | return FALSE; | |
2295 | } | |
2296 | } | |
2297 | insn_error.min_argnum = argnum; | |
2298 | insn_error.format = format; | |
2299 | insn_error.msg = msg; | |
2300 | return TRUE; | |
2301 | } | |
2302 | ||
2303 | /* Record an instruction error with no % format fields. ARGNUM and MSG are | |
2304 | as for set_insn_error_format. */ | |
2305 | ||
2306 | static void | |
2307 | set_insn_error (int argnum, const char *msg) | |
2308 | { | |
2309 | set_insn_error_format (argnum, ERR_FMT_PLAIN, msg); | |
2310 | } | |
2311 | ||
2312 | /* Record an instruction error with one %d field I. ARGNUM and MSG are | |
2313 | as for set_insn_error_format. */ | |
2314 | ||
2315 | static void | |
2316 | set_insn_error_i (int argnum, const char *msg, int i) | |
2317 | { | |
2318 | if (set_insn_error_format (argnum, ERR_FMT_I, msg)) | |
2319 | insn_error.u.i = i; | |
2320 | } | |
2321 | ||
2322 | /* Record an instruction error with two %s fields S1 and S2. ARGNUM and MSG | |
2323 | are as for set_insn_error_format. */ | |
2324 | ||
2325 | static void | |
2326 | set_insn_error_ss (int argnum, const char *msg, const char *s1, const char *s2) | |
2327 | { | |
2328 | if (set_insn_error_format (argnum, ERR_FMT_SS, msg)) | |
2329 | { | |
2330 | insn_error.u.ss[0] = s1; | |
2331 | insn_error.u.ss[1] = s2; | |
2332 | } | |
2333 | } | |
2334 | ||
2335 | /* Report the error in insn_error, which is against assembly code STR. */ | |
2336 | ||
2337 | static void | |
2338 | report_insn_error (const char *str) | |
2339 | { | |
2340 | const char *msg; | |
2341 | ||
2342 | msg = ACONCAT ((insn_error.msg, " `%s'", NULL)); | |
2343 | switch (insn_error.format) | |
2344 | { | |
2345 | case ERR_FMT_PLAIN: | |
2346 | as_bad (msg, str); | |
2347 | break; | |
2348 | ||
2349 | case ERR_FMT_I: | |
2350 | as_bad (msg, insn_error.u.i, str); | |
2351 | break; | |
2352 | ||
2353 | case ERR_FMT_SS: | |
2354 | as_bad (msg, insn_error.u.ss[0], insn_error.u.ss[1], str); | |
2355 | break; | |
2356 | } | |
2357 | } | |
2358 | ||
71400594 RS |
2359 | /* Initialize vr4120_conflicts. There is a bit of duplication here: |
2360 | the idea is to make it obvious at a glance that each errata is | |
2361 | included. */ | |
2362 | ||
2363 | static void | |
2364 | init_vr4120_conflicts (void) | |
2365 | { | |
2366 | #define CONFLICT(FIRST, SECOND) \ | |
2367 | vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND | |
2368 | ||
2369 | /* Errata 21 - [D]DIV[U] after [D]MACC */ | |
2370 | CONFLICT (MACC, DIV); | |
2371 | CONFLICT (DMACC, DIV); | |
2372 | ||
2373 | /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */ | |
2374 | CONFLICT (DMULT, DMULT); | |
2375 | CONFLICT (DMULT, DMACC); | |
2376 | CONFLICT (DMACC, DMULT); | |
2377 | CONFLICT (DMACC, DMACC); | |
2378 | ||
2379 | /* Errata 24 - MT{LO,HI} after [D]MACC */ | |
2380 | CONFLICT (MACC, MTHILO); | |
2381 | CONFLICT (DMACC, MTHILO); | |
2382 | ||
2383 | /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU | |
2384 | instruction is executed immediately after a MACC or DMACC | |
2385 | instruction, the result of [either instruction] is incorrect." */ | |
2386 | CONFLICT (MACC, MULT); | |
2387 | CONFLICT (MACC, DMULT); | |
2388 | CONFLICT (DMACC, MULT); | |
2389 | CONFLICT (DMACC, DMULT); | |
2390 | ||
2391 | /* VR4181A errata MD(4): "If a MACC or DMACC instruction is | |
2392 | executed immediately after a DMULT, DMULTU, DIV, DIVU, | |
2393 | DDIV or DDIVU instruction, the result of the MACC or | |
2394 | DMACC instruction is incorrect.". */ | |
2395 | CONFLICT (DMULT, MACC); | |
2396 | CONFLICT (DMULT, DMACC); | |
2397 | CONFLICT (DIV, MACC); | |
2398 | CONFLICT (DIV, DMACC); | |
2399 | ||
2400 | #undef CONFLICT | |
2401 | } | |
2402 | ||
707bfff6 TS |
2403 | struct regname { |
2404 | const char *name; | |
2405 | unsigned int num; | |
2406 | }; | |
2407 | ||
14daeee3 | 2408 | #define RNUM_MASK 0x00000ff |
56d438b1 | 2409 | #define RTYPE_MASK 0x0ffff00 |
14daeee3 RS |
2410 | #define RTYPE_NUM 0x0000100 |
2411 | #define RTYPE_FPU 0x0000200 | |
2412 | #define RTYPE_FCC 0x0000400 | |
2413 | #define RTYPE_VEC 0x0000800 | |
2414 | #define RTYPE_GP 0x0001000 | |
2415 | #define RTYPE_CP0 0x0002000 | |
2416 | #define RTYPE_PC 0x0004000 | |
2417 | #define RTYPE_ACC 0x0008000 | |
2418 | #define RTYPE_CCC 0x0010000 | |
2419 | #define RTYPE_VI 0x0020000 | |
2420 | #define RTYPE_VF 0x0040000 | |
2421 | #define RTYPE_R5900_I 0x0080000 | |
2422 | #define RTYPE_R5900_Q 0x0100000 | |
2423 | #define RTYPE_R5900_R 0x0200000 | |
2424 | #define RTYPE_R5900_ACC 0x0400000 | |
56d438b1 | 2425 | #define RTYPE_MSA 0x0800000 |
14daeee3 | 2426 | #define RWARN 0x8000000 |
707bfff6 TS |
2427 | |
2428 | #define GENERIC_REGISTER_NUMBERS \ | |
2429 | {"$0", RTYPE_NUM | 0}, \ | |
2430 | {"$1", RTYPE_NUM | 1}, \ | |
2431 | {"$2", RTYPE_NUM | 2}, \ | |
2432 | {"$3", RTYPE_NUM | 3}, \ | |
2433 | {"$4", RTYPE_NUM | 4}, \ | |
2434 | {"$5", RTYPE_NUM | 5}, \ | |
2435 | {"$6", RTYPE_NUM | 6}, \ | |
2436 | {"$7", RTYPE_NUM | 7}, \ | |
2437 | {"$8", RTYPE_NUM | 8}, \ | |
2438 | {"$9", RTYPE_NUM | 9}, \ | |
2439 | {"$10", RTYPE_NUM | 10}, \ | |
2440 | {"$11", RTYPE_NUM | 11}, \ | |
2441 | {"$12", RTYPE_NUM | 12}, \ | |
2442 | {"$13", RTYPE_NUM | 13}, \ | |
2443 | {"$14", RTYPE_NUM | 14}, \ | |
2444 | {"$15", RTYPE_NUM | 15}, \ | |
2445 | {"$16", RTYPE_NUM | 16}, \ | |
2446 | {"$17", RTYPE_NUM | 17}, \ | |
2447 | {"$18", RTYPE_NUM | 18}, \ | |
2448 | {"$19", RTYPE_NUM | 19}, \ | |
2449 | {"$20", RTYPE_NUM | 20}, \ | |
2450 | {"$21", RTYPE_NUM | 21}, \ | |
2451 | {"$22", RTYPE_NUM | 22}, \ | |
2452 | {"$23", RTYPE_NUM | 23}, \ | |
2453 | {"$24", RTYPE_NUM | 24}, \ | |
2454 | {"$25", RTYPE_NUM | 25}, \ | |
2455 | {"$26", RTYPE_NUM | 26}, \ | |
2456 | {"$27", RTYPE_NUM | 27}, \ | |
2457 | {"$28", RTYPE_NUM | 28}, \ | |
2458 | {"$29", RTYPE_NUM | 29}, \ | |
2459 | {"$30", RTYPE_NUM | 30}, \ | |
2460 | {"$31", RTYPE_NUM | 31} | |
2461 | ||
2462 | #define FPU_REGISTER_NAMES \ | |
2463 | {"$f0", RTYPE_FPU | 0}, \ | |
2464 | {"$f1", RTYPE_FPU | 1}, \ | |
2465 | {"$f2", RTYPE_FPU | 2}, \ | |
2466 | {"$f3", RTYPE_FPU | 3}, \ | |
2467 | {"$f4", RTYPE_FPU | 4}, \ | |
2468 | {"$f5", RTYPE_FPU | 5}, \ | |
2469 | {"$f6", RTYPE_FPU | 6}, \ | |
2470 | {"$f7", RTYPE_FPU | 7}, \ | |
2471 | {"$f8", RTYPE_FPU | 8}, \ | |
2472 | {"$f9", RTYPE_FPU | 9}, \ | |
2473 | {"$f10", RTYPE_FPU | 10}, \ | |
2474 | {"$f11", RTYPE_FPU | 11}, \ | |
2475 | {"$f12", RTYPE_FPU | 12}, \ | |
2476 | {"$f13", RTYPE_FPU | 13}, \ | |
2477 | {"$f14", RTYPE_FPU | 14}, \ | |
2478 | {"$f15", RTYPE_FPU | 15}, \ | |
2479 | {"$f16", RTYPE_FPU | 16}, \ | |
2480 | {"$f17", RTYPE_FPU | 17}, \ | |
2481 | {"$f18", RTYPE_FPU | 18}, \ | |
2482 | {"$f19", RTYPE_FPU | 19}, \ | |
2483 | {"$f20", RTYPE_FPU | 20}, \ | |
2484 | {"$f21", RTYPE_FPU | 21}, \ | |
2485 | {"$f22", RTYPE_FPU | 22}, \ | |
2486 | {"$f23", RTYPE_FPU | 23}, \ | |
2487 | {"$f24", RTYPE_FPU | 24}, \ | |
2488 | {"$f25", RTYPE_FPU | 25}, \ | |
2489 | {"$f26", RTYPE_FPU | 26}, \ | |
2490 | {"$f27", RTYPE_FPU | 27}, \ | |
2491 | {"$f28", RTYPE_FPU | 28}, \ | |
2492 | {"$f29", RTYPE_FPU | 29}, \ | |
2493 | {"$f30", RTYPE_FPU | 30}, \ | |
2494 | {"$f31", RTYPE_FPU | 31} | |
2495 | ||
2496 | #define FPU_CONDITION_CODE_NAMES \ | |
2497 | {"$fcc0", RTYPE_FCC | 0}, \ | |
2498 | {"$fcc1", RTYPE_FCC | 1}, \ | |
2499 | {"$fcc2", RTYPE_FCC | 2}, \ | |
2500 | {"$fcc3", RTYPE_FCC | 3}, \ | |
2501 | {"$fcc4", RTYPE_FCC | 4}, \ | |
2502 | {"$fcc5", RTYPE_FCC | 5}, \ | |
2503 | {"$fcc6", RTYPE_FCC | 6}, \ | |
2504 | {"$fcc7", RTYPE_FCC | 7} | |
2505 | ||
2506 | #define COPROC_CONDITION_CODE_NAMES \ | |
2507 | {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \ | |
2508 | {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \ | |
2509 | {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \ | |
2510 | {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \ | |
2511 | {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \ | |
2512 | {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \ | |
2513 | {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \ | |
2514 | {"$cc7", RTYPE_FCC | RTYPE_CCC | 7} | |
2515 | ||
2516 | #define N32N64_SYMBOLIC_REGISTER_NAMES \ | |
2517 | {"$a4", RTYPE_GP | 8}, \ | |
2518 | {"$a5", RTYPE_GP | 9}, \ | |
2519 | {"$a6", RTYPE_GP | 10}, \ | |
2520 | {"$a7", RTYPE_GP | 11}, \ | |
2521 | {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \ | |
2522 | {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \ | |
2523 | {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \ | |
2524 | {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \ | |
2525 | {"$t0", RTYPE_GP | 12}, \ | |
2526 | {"$t1", RTYPE_GP | 13}, \ | |
2527 | {"$t2", RTYPE_GP | 14}, \ | |
2528 | {"$t3", RTYPE_GP | 15} | |
2529 | ||
2530 | #define O32_SYMBOLIC_REGISTER_NAMES \ | |
2531 | {"$t0", RTYPE_GP | 8}, \ | |
2532 | {"$t1", RTYPE_GP | 9}, \ | |
2533 | {"$t2", RTYPE_GP | 10}, \ | |
2534 | {"$t3", RTYPE_GP | 11}, \ | |
2535 | {"$t4", RTYPE_GP | 12}, \ | |
2536 | {"$t5", RTYPE_GP | 13}, \ | |
2537 | {"$t6", RTYPE_GP | 14}, \ | |
2538 | {"$t7", RTYPE_GP | 15}, \ | |
2539 | {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \ | |
2540 | {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \ | |
2541 | {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \ | |
2542 | {"$ta3", RTYPE_GP | 15} /* alias for $t7 */ | |
2543 | ||
2544 | /* Remaining symbolic register names */ | |
2545 | #define SYMBOLIC_REGISTER_NAMES \ | |
2546 | {"$zero", RTYPE_GP | 0}, \ | |
2547 | {"$at", RTYPE_GP | 1}, \ | |
2548 | {"$AT", RTYPE_GP | 1}, \ | |
2549 | {"$v0", RTYPE_GP | 2}, \ | |
2550 | {"$v1", RTYPE_GP | 3}, \ | |
2551 | {"$a0", RTYPE_GP | 4}, \ | |
2552 | {"$a1", RTYPE_GP | 5}, \ | |
2553 | {"$a2", RTYPE_GP | 6}, \ | |
2554 | {"$a3", RTYPE_GP | 7}, \ | |
2555 | {"$s0", RTYPE_GP | 16}, \ | |
2556 | {"$s1", RTYPE_GP | 17}, \ | |
2557 | {"$s2", RTYPE_GP | 18}, \ | |
2558 | {"$s3", RTYPE_GP | 19}, \ | |
2559 | {"$s4", RTYPE_GP | 20}, \ | |
2560 | {"$s5", RTYPE_GP | 21}, \ | |
2561 | {"$s6", RTYPE_GP | 22}, \ | |
2562 | {"$s7", RTYPE_GP | 23}, \ | |
2563 | {"$t8", RTYPE_GP | 24}, \ | |
2564 | {"$t9", RTYPE_GP | 25}, \ | |
2565 | {"$k0", RTYPE_GP | 26}, \ | |
2566 | {"$kt0", RTYPE_GP | 26}, \ | |
2567 | {"$k1", RTYPE_GP | 27}, \ | |
2568 | {"$kt1", RTYPE_GP | 27}, \ | |
2569 | {"$gp", RTYPE_GP | 28}, \ | |
2570 | {"$sp", RTYPE_GP | 29}, \ | |
2571 | {"$s8", RTYPE_GP | 30}, \ | |
2572 | {"$fp", RTYPE_GP | 30}, \ | |
2573 | {"$ra", RTYPE_GP | 31} | |
2574 | ||
2575 | #define MIPS16_SPECIAL_REGISTER_NAMES \ | |
2576 | {"$pc", RTYPE_PC | 0} | |
2577 | ||
2578 | #define MDMX_VECTOR_REGISTER_NAMES \ | |
2579 | /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \ | |
2580 | /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \ | |
2581 | {"$v2", RTYPE_VEC | 2}, \ | |
2582 | {"$v3", RTYPE_VEC | 3}, \ | |
2583 | {"$v4", RTYPE_VEC | 4}, \ | |
2584 | {"$v5", RTYPE_VEC | 5}, \ | |
2585 | {"$v6", RTYPE_VEC | 6}, \ | |
2586 | {"$v7", RTYPE_VEC | 7}, \ | |
2587 | {"$v8", RTYPE_VEC | 8}, \ | |
2588 | {"$v9", RTYPE_VEC | 9}, \ | |
2589 | {"$v10", RTYPE_VEC | 10}, \ | |
2590 | {"$v11", RTYPE_VEC | 11}, \ | |
2591 | {"$v12", RTYPE_VEC | 12}, \ | |
2592 | {"$v13", RTYPE_VEC | 13}, \ | |
2593 | {"$v14", RTYPE_VEC | 14}, \ | |
2594 | {"$v15", RTYPE_VEC | 15}, \ | |
2595 | {"$v16", RTYPE_VEC | 16}, \ | |
2596 | {"$v17", RTYPE_VEC | 17}, \ | |
2597 | {"$v18", RTYPE_VEC | 18}, \ | |
2598 | {"$v19", RTYPE_VEC | 19}, \ | |
2599 | {"$v20", RTYPE_VEC | 20}, \ | |
2600 | {"$v21", RTYPE_VEC | 21}, \ | |
2601 | {"$v22", RTYPE_VEC | 22}, \ | |
2602 | {"$v23", RTYPE_VEC | 23}, \ | |
2603 | {"$v24", RTYPE_VEC | 24}, \ | |
2604 | {"$v25", RTYPE_VEC | 25}, \ | |
2605 | {"$v26", RTYPE_VEC | 26}, \ | |
2606 | {"$v27", RTYPE_VEC | 27}, \ | |
2607 | {"$v28", RTYPE_VEC | 28}, \ | |
2608 | {"$v29", RTYPE_VEC | 29}, \ | |
2609 | {"$v30", RTYPE_VEC | 30}, \ | |
2610 | {"$v31", RTYPE_VEC | 31} | |
2611 | ||
14daeee3 RS |
2612 | #define R5900_I_NAMES \ |
2613 | {"$I", RTYPE_R5900_I | 0} | |
2614 | ||
2615 | #define R5900_Q_NAMES \ | |
2616 | {"$Q", RTYPE_R5900_Q | 0} | |
2617 | ||
2618 | #define R5900_R_NAMES \ | |
2619 | {"$R", RTYPE_R5900_R | 0} | |
2620 | ||
2621 | #define R5900_ACC_NAMES \ | |
2622 | {"$ACC", RTYPE_R5900_ACC | 0 } | |
2623 | ||
707bfff6 TS |
2624 | #define MIPS_DSP_ACCUMULATOR_NAMES \ |
2625 | {"$ac0", RTYPE_ACC | 0}, \ | |
2626 | {"$ac1", RTYPE_ACC | 1}, \ | |
2627 | {"$ac2", RTYPE_ACC | 2}, \ | |
2628 | {"$ac3", RTYPE_ACC | 3} | |
2629 | ||
2630 | static const struct regname reg_names[] = { | |
2631 | GENERIC_REGISTER_NUMBERS, | |
2632 | FPU_REGISTER_NAMES, | |
2633 | FPU_CONDITION_CODE_NAMES, | |
2634 | COPROC_CONDITION_CODE_NAMES, | |
2635 | ||
2636 | /* The $txx registers depends on the abi, | |
2637 | these will be added later into the symbol table from | |
2638 | one of the tables below once mips_abi is set after | |
2639 | parsing of arguments from the command line. */ | |
2640 | SYMBOLIC_REGISTER_NAMES, | |
2641 | ||
2642 | MIPS16_SPECIAL_REGISTER_NAMES, | |
2643 | MDMX_VECTOR_REGISTER_NAMES, | |
14daeee3 RS |
2644 | R5900_I_NAMES, |
2645 | R5900_Q_NAMES, | |
2646 | R5900_R_NAMES, | |
2647 | R5900_ACC_NAMES, | |
707bfff6 TS |
2648 | MIPS_DSP_ACCUMULATOR_NAMES, |
2649 | {0, 0} | |
2650 | }; | |
2651 | ||
2652 | static const struct regname reg_names_o32[] = { | |
2653 | O32_SYMBOLIC_REGISTER_NAMES, | |
2654 | {0, 0} | |
2655 | }; | |
2656 | ||
2657 | static const struct regname reg_names_n32n64[] = { | |
2658 | N32N64_SYMBOLIC_REGISTER_NAMES, | |
2659 | {0, 0} | |
2660 | }; | |
2661 | ||
a92713e6 RS |
2662 | /* Register symbols $v0 and $v1 map to GPRs 2 and 3, but they can also be |
2663 | interpreted as vector registers 0 and 1. If SYMVAL is the value of one | |
2664 | of these register symbols, return the associated vector register, | |
2665 | otherwise return SYMVAL itself. */ | |
df58fc94 | 2666 | |
a92713e6 RS |
2667 | static unsigned int |
2668 | mips_prefer_vec_regno (unsigned int symval) | |
707bfff6 | 2669 | { |
a92713e6 RS |
2670 | if ((symval & -2) == (RTYPE_GP | 2)) |
2671 | return RTYPE_VEC | (symval & 1); | |
2672 | return symval; | |
2673 | } | |
2674 | ||
14daeee3 RS |
2675 | /* Return true if string [S, E) is a valid register name, storing its |
2676 | symbol value in *SYMVAL_PTR if so. */ | |
a92713e6 RS |
2677 | |
2678 | static bfd_boolean | |
14daeee3 | 2679 | mips_parse_register_1 (char *s, char *e, unsigned int *symval_ptr) |
a92713e6 | 2680 | { |
707bfff6 | 2681 | char save_c; |
14daeee3 | 2682 | symbolS *symbol; |
707bfff6 TS |
2683 | |
2684 | /* Terminate name. */ | |
2685 | save_c = *e; | |
2686 | *e = '\0'; | |
2687 | ||
a92713e6 RS |
2688 | /* Look up the name. */ |
2689 | symbol = symbol_find (s); | |
2690 | *e = save_c; | |
2691 | ||
2692 | if (!symbol || S_GET_SEGMENT (symbol) != reg_section) | |
2693 | return FALSE; | |
2694 | ||
14daeee3 RS |
2695 | *symval_ptr = S_GET_VALUE (symbol); |
2696 | return TRUE; | |
2697 | } | |
2698 | ||
2699 | /* Return true if the string at *SPTR is a valid register name. Allow it | |
2700 | to have a VU0-style channel suffix of the form x?y?z?w? if CHANNELS_PTR | |
2701 | is nonnull. | |
2702 | ||
2703 | When returning true, move *SPTR past the register, store the | |
2704 | register's symbol value in *SYMVAL_PTR and the channel mask in | |
2705 | *CHANNELS_PTR (if nonnull). The symbol value includes the register | |
2706 | number (RNUM_MASK) and register type (RTYPE_MASK). The channel mask | |
2707 | is a 4-bit value of the form XYZW and is 0 if no suffix was given. */ | |
2708 | ||
2709 | static bfd_boolean | |
2710 | mips_parse_register (char **sptr, unsigned int *symval_ptr, | |
2711 | unsigned int *channels_ptr) | |
2712 | { | |
2713 | char *s, *e, *m; | |
2714 | const char *q; | |
2715 | unsigned int channels, symval, bit; | |
2716 | ||
2717 | /* Find end of name. */ | |
2718 | s = e = *sptr; | |
2719 | if (is_name_beginner (*e)) | |
2720 | ++e; | |
2721 | while (is_part_of_name (*e)) | |
2722 | ++e; | |
2723 | ||
2724 | channels = 0; | |
2725 | if (!mips_parse_register_1 (s, e, &symval)) | |
2726 | { | |
2727 | if (!channels_ptr) | |
2728 | return FALSE; | |
2729 | ||
2730 | /* Eat characters from the end of the string that are valid | |
2731 | channel suffixes. The preceding register must be $ACC or | |
2732 | end with a digit, so there is no ambiguity. */ | |
2733 | bit = 1; | |
2734 | m = e; | |
2735 | for (q = "wzyx"; *q; q++, bit <<= 1) | |
2736 | if (m > s && m[-1] == *q) | |
2737 | { | |
2738 | --m; | |
2739 | channels |= bit; | |
2740 | } | |
2741 | ||
2742 | if (channels == 0 | |
2743 | || !mips_parse_register_1 (s, m, &symval) | |
2744 | || (symval & (RTYPE_VI | RTYPE_VF | RTYPE_R5900_ACC)) == 0) | |
2745 | return FALSE; | |
2746 | } | |
2747 | ||
a92713e6 | 2748 | *sptr = e; |
14daeee3 RS |
2749 | *symval_ptr = symval; |
2750 | if (channels_ptr) | |
2751 | *channels_ptr = channels; | |
a92713e6 RS |
2752 | return TRUE; |
2753 | } | |
2754 | ||
2755 | /* Check if SPTR points at a valid register specifier according to TYPES. | |
2756 | If so, then return 1, advance S to consume the specifier and store | |
2757 | the register's number in REGNOP, otherwise return 0. */ | |
2758 | ||
2759 | static int | |
2760 | reg_lookup (char **s, unsigned int types, unsigned int *regnop) | |
2761 | { | |
2762 | unsigned int regno; | |
2763 | ||
14daeee3 | 2764 | if (mips_parse_register (s, ®no, NULL)) |
707bfff6 | 2765 | { |
a92713e6 RS |
2766 | if (types & RTYPE_VEC) |
2767 | regno = mips_prefer_vec_regno (regno); | |
2768 | if (regno & types) | |
2769 | regno &= RNUM_MASK; | |
2770 | else | |
2771 | regno = ~0; | |
707bfff6 | 2772 | } |
a92713e6 | 2773 | else |
707bfff6 | 2774 | { |
a92713e6 | 2775 | if (types & RWARN) |
1661c76c | 2776 | as_warn (_("unrecognized register name `%s'"), *s); |
a92713e6 | 2777 | regno = ~0; |
707bfff6 | 2778 | } |
707bfff6 | 2779 | if (regnop) |
a92713e6 RS |
2780 | *regnop = regno; |
2781 | return regno <= RNUM_MASK; | |
707bfff6 TS |
2782 | } |
2783 | ||
14daeee3 RS |
2784 | /* Parse a VU0 "x?y?z?w?" channel mask at S and store the associated |
2785 | mask in *CHANNELS. Return a pointer to the first unconsumed character. */ | |
2786 | ||
2787 | static char * | |
2788 | mips_parse_vu0_channels (char *s, unsigned int *channels) | |
2789 | { | |
2790 | unsigned int i; | |
2791 | ||
2792 | *channels = 0; | |
2793 | for (i = 0; i < 4; i++) | |
2794 | if (*s == "xyzw"[i]) | |
2795 | { | |
2796 | *channels |= 1 << (3 - i); | |
2797 | ++s; | |
2798 | } | |
2799 | return s; | |
2800 | } | |
2801 | ||
a92713e6 RS |
2802 | /* Token types for parsed operand lists. */ |
2803 | enum mips_operand_token_type { | |
2804 | /* A plain register, e.g. $f2. */ | |
2805 | OT_REG, | |
df58fc94 | 2806 | |
14daeee3 RS |
2807 | /* A 4-bit XYZW channel mask. */ |
2808 | OT_CHANNELS, | |
2809 | ||
56d438b1 CF |
2810 | /* A constant vector index, e.g. [1]. */ |
2811 | OT_INTEGER_INDEX, | |
2812 | ||
2813 | /* A register vector index, e.g. [$2]. */ | |
2814 | OT_REG_INDEX, | |
df58fc94 | 2815 | |
a92713e6 RS |
2816 | /* A continuous range of registers, e.g. $s0-$s4. */ |
2817 | OT_REG_RANGE, | |
2818 | ||
2819 | /* A (possibly relocated) expression. */ | |
2820 | OT_INTEGER, | |
2821 | ||
2822 | /* A floating-point value. */ | |
2823 | OT_FLOAT, | |
2824 | ||
2825 | /* A single character. This can be '(', ')' or ',', but '(' only appears | |
2826 | before OT_REGs. */ | |
2827 | OT_CHAR, | |
2828 | ||
14daeee3 RS |
2829 | /* A doubled character, either "--" or "++". */ |
2830 | OT_DOUBLE_CHAR, | |
2831 | ||
a92713e6 RS |
2832 | /* The end of the operand list. */ |
2833 | OT_END | |
2834 | }; | |
2835 | ||
2836 | /* A parsed operand token. */ | |
2837 | struct mips_operand_token | |
2838 | { | |
2839 | /* The type of token. */ | |
2840 | enum mips_operand_token_type type; | |
2841 | union | |
2842 | { | |
56d438b1 | 2843 | /* The register symbol value for an OT_REG or OT_REG_INDEX. */ |
a92713e6 RS |
2844 | unsigned int regno; |
2845 | ||
14daeee3 RS |
2846 | /* The 4-bit channel mask for an OT_CHANNEL_SUFFIX. */ |
2847 | unsigned int channels; | |
2848 | ||
56d438b1 CF |
2849 | /* The integer value of an OT_INTEGER_INDEX. */ |
2850 | addressT index; | |
a92713e6 RS |
2851 | |
2852 | /* The two register symbol values involved in an OT_REG_RANGE. */ | |
2853 | struct { | |
2854 | unsigned int regno1; | |
2855 | unsigned int regno2; | |
2856 | } reg_range; | |
2857 | ||
2858 | /* The value of an OT_INTEGER. The value is represented as an | |
2859 | expression and the relocation operators that were applied to | |
2860 | that expression. The reloc entries are BFD_RELOC_UNUSED if no | |
2861 | relocation operators were used. */ | |
2862 | struct { | |
2863 | expressionS value; | |
2864 | bfd_reloc_code_real_type relocs[3]; | |
2865 | } integer; | |
2866 | ||
2867 | /* The binary data for an OT_FLOAT constant, and the number of bytes | |
2868 | in the constant. */ | |
2869 | struct { | |
2870 | unsigned char data[8]; | |
2871 | int length; | |
2872 | } flt; | |
2873 | ||
14daeee3 | 2874 | /* The character represented by an OT_CHAR or OT_DOUBLE_CHAR. */ |
a92713e6 RS |
2875 | char ch; |
2876 | } u; | |
2877 | }; | |
2878 | ||
2879 | /* An obstack used to construct lists of mips_operand_tokens. */ | |
2880 | static struct obstack mips_operand_tokens; | |
2881 | ||
2882 | /* Give TOKEN type TYPE and add it to mips_operand_tokens. */ | |
2883 | ||
2884 | static void | |
2885 | mips_add_token (struct mips_operand_token *token, | |
2886 | enum mips_operand_token_type type) | |
2887 | { | |
2888 | token->type = type; | |
2889 | obstack_grow (&mips_operand_tokens, token, sizeof (*token)); | |
2890 | } | |
2891 | ||
2892 | /* Check whether S is '(' followed by a register name. Add OT_CHAR | |
2893 | and OT_REG tokens for them if so, and return a pointer to the first | |
2894 | unconsumed character. Return null otherwise. */ | |
2895 | ||
2896 | static char * | |
2897 | mips_parse_base_start (char *s) | |
2898 | { | |
2899 | struct mips_operand_token token; | |
14daeee3 RS |
2900 | unsigned int regno, channels; |
2901 | bfd_boolean decrement_p; | |
df58fc94 | 2902 | |
a92713e6 RS |
2903 | if (*s != '(') |
2904 | return 0; | |
2905 | ||
2906 | ++s; | |
2907 | SKIP_SPACE_TABS (s); | |
14daeee3 RS |
2908 | |
2909 | /* Only match "--" as part of a base expression. In other contexts "--X" | |
2910 | is a double negative. */ | |
2911 | decrement_p = (s[0] == '-' && s[1] == '-'); | |
2912 | if (decrement_p) | |
2913 | { | |
2914 | s += 2; | |
2915 | SKIP_SPACE_TABS (s); | |
2916 | } | |
2917 | ||
2918 | /* Allow a channel specifier because that leads to better error messages | |
2919 | than treating something like "$vf0x++" as an expression. */ | |
2920 | if (!mips_parse_register (&s, ®no, &channels)) | |
a92713e6 RS |
2921 | return 0; |
2922 | ||
2923 | token.u.ch = '('; | |
2924 | mips_add_token (&token, OT_CHAR); | |
2925 | ||
14daeee3 RS |
2926 | if (decrement_p) |
2927 | { | |
2928 | token.u.ch = '-'; | |
2929 | mips_add_token (&token, OT_DOUBLE_CHAR); | |
2930 | } | |
2931 | ||
a92713e6 RS |
2932 | token.u.regno = regno; |
2933 | mips_add_token (&token, OT_REG); | |
2934 | ||
14daeee3 RS |
2935 | if (channels) |
2936 | { | |
2937 | token.u.channels = channels; | |
2938 | mips_add_token (&token, OT_CHANNELS); | |
2939 | } | |
2940 | ||
2941 | /* For consistency, only match "++" as part of base expressions too. */ | |
2942 | SKIP_SPACE_TABS (s); | |
2943 | if (s[0] == '+' && s[1] == '+') | |
2944 | { | |
2945 | s += 2; | |
2946 | token.u.ch = '+'; | |
2947 | mips_add_token (&token, OT_DOUBLE_CHAR); | |
2948 | } | |
2949 | ||
a92713e6 RS |
2950 | return s; |
2951 | } | |
2952 | ||
2953 | /* Parse one or more tokens from S. Return a pointer to the first | |
2954 | unconsumed character on success. Return null if an error was found | |
2955 | and store the error text in insn_error. FLOAT_FORMAT is as for | |
2956 | mips_parse_arguments. */ | |
2957 | ||
2958 | static char * | |
2959 | mips_parse_argument_token (char *s, char float_format) | |
2960 | { | |
2961 | char *end, *save_in, *err; | |
14daeee3 | 2962 | unsigned int regno1, regno2, channels; |
a92713e6 RS |
2963 | struct mips_operand_token token; |
2964 | ||
2965 | /* First look for "($reg", since we want to treat that as an | |
2966 | OT_CHAR and OT_REG rather than an expression. */ | |
2967 | end = mips_parse_base_start (s); | |
2968 | if (end) | |
2969 | return end; | |
2970 | ||
2971 | /* Handle other characters that end up as OT_CHARs. */ | |
2972 | if (*s == ')' || *s == ',') | |
2973 | { | |
2974 | token.u.ch = *s; | |
2975 | mips_add_token (&token, OT_CHAR); | |
2976 | ++s; | |
2977 | return s; | |
2978 | } | |
2979 | ||
2980 | /* Handle tokens that start with a register. */ | |
14daeee3 | 2981 | if (mips_parse_register (&s, ®no1, &channels)) |
df58fc94 | 2982 | { |
14daeee3 RS |
2983 | if (channels) |
2984 | { | |
2985 | /* A register and a VU0 channel suffix. */ | |
2986 | token.u.regno = regno1; | |
2987 | mips_add_token (&token, OT_REG); | |
2988 | ||
2989 | token.u.channels = channels; | |
2990 | mips_add_token (&token, OT_CHANNELS); | |
2991 | return s; | |
2992 | } | |
2993 | ||
a92713e6 RS |
2994 | SKIP_SPACE_TABS (s); |
2995 | if (*s == '-') | |
df58fc94 | 2996 | { |
a92713e6 RS |
2997 | /* A register range. */ |
2998 | ++s; | |
2999 | SKIP_SPACE_TABS (s); | |
14daeee3 | 3000 | if (!mips_parse_register (&s, ®no2, NULL)) |
a92713e6 | 3001 | { |
1661c76c | 3002 | set_insn_error (0, _("invalid register range")); |
a92713e6 RS |
3003 | return 0; |
3004 | } | |
df58fc94 | 3005 | |
a92713e6 RS |
3006 | token.u.reg_range.regno1 = regno1; |
3007 | token.u.reg_range.regno2 = regno2; | |
3008 | mips_add_token (&token, OT_REG_RANGE); | |
3009 | return s; | |
3010 | } | |
a92713e6 | 3011 | |
56d438b1 CF |
3012 | /* Add the register itself. */ |
3013 | token.u.regno = regno1; | |
3014 | mips_add_token (&token, OT_REG); | |
3015 | ||
3016 | /* Check for a vector index. */ | |
3017 | if (*s == '[') | |
3018 | { | |
a92713e6 RS |
3019 | ++s; |
3020 | SKIP_SPACE_TABS (s); | |
56d438b1 CF |
3021 | if (mips_parse_register (&s, &token.u.regno, NULL)) |
3022 | mips_add_token (&token, OT_REG_INDEX); | |
3023 | else | |
a92713e6 | 3024 | { |
56d438b1 CF |
3025 | expressionS element; |
3026 | ||
3027 | my_getExpression (&element, s); | |
3028 | if (element.X_op != O_constant) | |
3029 | { | |
3030 | set_insn_error (0, _("vector element must be constant")); | |
3031 | return 0; | |
3032 | } | |
3033 | s = expr_end; | |
3034 | token.u.index = element.X_add_number; | |
3035 | mips_add_token (&token, OT_INTEGER_INDEX); | |
a92713e6 | 3036 | } |
a92713e6 RS |
3037 | SKIP_SPACE_TABS (s); |
3038 | if (*s != ']') | |
3039 | { | |
1661c76c | 3040 | set_insn_error (0, _("missing `]'")); |
a92713e6 RS |
3041 | return 0; |
3042 | } | |
3043 | ++s; | |
df58fc94 | 3044 | } |
a92713e6 | 3045 | return s; |
df58fc94 RS |
3046 | } |
3047 | ||
a92713e6 RS |
3048 | if (float_format) |
3049 | { | |
3050 | /* First try to treat expressions as floats. */ | |
3051 | save_in = input_line_pointer; | |
3052 | input_line_pointer = s; | |
3053 | err = md_atof (float_format, (char *) token.u.flt.data, | |
3054 | &token.u.flt.length); | |
3055 | end = input_line_pointer; | |
3056 | input_line_pointer = save_in; | |
3057 | if (err && *err) | |
3058 | { | |
e3de51ce | 3059 | set_insn_error (0, err); |
a92713e6 RS |
3060 | return 0; |
3061 | } | |
3062 | if (s != end) | |
3063 | { | |
3064 | mips_add_token (&token, OT_FLOAT); | |
3065 | return end; | |
3066 | } | |
3067 | } | |
3068 | ||
3069 | /* Treat everything else as an integer expression. */ | |
3070 | token.u.integer.relocs[0] = BFD_RELOC_UNUSED; | |
3071 | token.u.integer.relocs[1] = BFD_RELOC_UNUSED; | |
3072 | token.u.integer.relocs[2] = BFD_RELOC_UNUSED; | |
3073 | my_getSmallExpression (&token.u.integer.value, token.u.integer.relocs, s); | |
3074 | s = expr_end; | |
3075 | mips_add_token (&token, OT_INTEGER); | |
3076 | return s; | |
3077 | } | |
3078 | ||
3079 | /* S points to the operand list for an instruction. FLOAT_FORMAT is 'f' | |
3080 | if expressions should be treated as 32-bit floating-point constants, | |
3081 | 'd' if they should be treated as 64-bit floating-point constants, | |
3082 | or 0 if they should be treated as integer expressions (the usual case). | |
3083 | ||
3084 | Return a list of tokens on success, otherwise return 0. The caller | |
3085 | must obstack_free the list after use. */ | |
3086 | ||
3087 | static struct mips_operand_token * | |
3088 | mips_parse_arguments (char *s, char float_format) | |
3089 | { | |
3090 | struct mips_operand_token token; | |
3091 | ||
3092 | SKIP_SPACE_TABS (s); | |
3093 | while (*s) | |
3094 | { | |
3095 | s = mips_parse_argument_token (s, float_format); | |
3096 | if (!s) | |
3097 | { | |
3098 | obstack_free (&mips_operand_tokens, | |
3099 | obstack_finish (&mips_operand_tokens)); | |
3100 | return 0; | |
3101 | } | |
3102 | SKIP_SPACE_TABS (s); | |
3103 | } | |
3104 | mips_add_token (&token, OT_END); | |
3105 | return (struct mips_operand_token *) obstack_finish (&mips_operand_tokens); | |
df58fc94 RS |
3106 | } |
3107 | ||
d301a56b RS |
3108 | /* Return TRUE if opcode MO is valid on the currently selected ISA, ASE |
3109 | and architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */ | |
037b32b9 AN |
3110 | |
3111 | static bfd_boolean | |
f79e2745 | 3112 | is_opcode_valid (const struct mips_opcode *mo) |
037b32b9 AN |
3113 | { |
3114 | int isa = mips_opts.isa; | |
846ef2d0 | 3115 | int ase = mips_opts.ase; |
037b32b9 | 3116 | int fp_s, fp_d; |
c6278170 | 3117 | unsigned int i; |
037b32b9 | 3118 | |
c6278170 RS |
3119 | if (ISA_HAS_64BIT_REGS (mips_opts.isa)) |
3120 | for (i = 0; i < ARRAY_SIZE (mips_ases); i++) | |
3121 | if ((ase & mips_ases[i].flags) == mips_ases[i].flags) | |
3122 | ase |= mips_ases[i].flags64; | |
037b32b9 | 3123 | |
d301a56b | 3124 | if (!opcode_is_member (mo, isa, ase, mips_opts.arch)) |
037b32b9 AN |
3125 | return FALSE; |
3126 | ||
3127 | /* Check whether the instruction or macro requires single-precision or | |
3128 | double-precision floating-point support. Note that this information is | |
3129 | stored differently in the opcode table for insns and macros. */ | |
3130 | if (mo->pinfo == INSN_MACRO) | |
3131 | { | |
3132 | fp_s = mo->pinfo2 & INSN2_M_FP_S; | |
3133 | fp_d = mo->pinfo2 & INSN2_M_FP_D; | |
3134 | } | |
3135 | else | |
3136 | { | |
3137 | fp_s = mo->pinfo & FP_S; | |
3138 | fp_d = mo->pinfo & FP_D; | |
3139 | } | |
3140 | ||
3141 | if (fp_d && (mips_opts.soft_float || mips_opts.single_float)) | |
3142 | return FALSE; | |
3143 | ||
3144 | if (fp_s && mips_opts.soft_float) | |
3145 | return FALSE; | |
3146 | ||
3147 | return TRUE; | |
3148 | } | |
3149 | ||
3150 | /* Return TRUE if the MIPS16 opcode MO is valid on the currently | |
3151 | selected ISA and architecture. */ | |
3152 | ||
3153 | static bfd_boolean | |
3154 | is_opcode_valid_16 (const struct mips_opcode *mo) | |
3155 | { | |
d301a56b | 3156 | return opcode_is_member (mo, mips_opts.isa, 0, mips_opts.arch); |
037b32b9 AN |
3157 | } |
3158 | ||
df58fc94 RS |
3159 | /* Return TRUE if the size of the microMIPS opcode MO matches one |
3160 | explicitly requested. Always TRUE in the standard MIPS mode. */ | |
3161 | ||
3162 | static bfd_boolean | |
3163 | is_size_valid (const struct mips_opcode *mo) | |
3164 | { | |
3165 | if (!mips_opts.micromips) | |
3166 | return TRUE; | |
3167 | ||
833794fc MR |
3168 | if (mips_opts.insn32) |
3169 | { | |
3170 | if (mo->pinfo != INSN_MACRO && micromips_insn_length (mo) != 4) | |
3171 | return FALSE; | |
3172 | if ((mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0) | |
3173 | return FALSE; | |
3174 | } | |
df58fc94 RS |
3175 | if (!forced_insn_length) |
3176 | return TRUE; | |
3177 | if (mo->pinfo == INSN_MACRO) | |
3178 | return FALSE; | |
3179 | return forced_insn_length == micromips_insn_length (mo); | |
3180 | } | |
3181 | ||
3182 | /* Return TRUE if the microMIPS opcode MO is valid for the delay slot | |
e64af278 MR |
3183 | of the preceding instruction. Always TRUE in the standard MIPS mode. |
3184 | ||
3185 | We don't accept macros in 16-bit delay slots to avoid a case where | |
3186 | a macro expansion fails because it relies on a preceding 32-bit real | |
3187 | instruction to have matched and does not handle the operands correctly. | |
3188 | The only macros that may expand to 16-bit instructions are JAL that | |
3189 | cannot be placed in a delay slot anyway, and corner cases of BALIGN | |
3190 | and BGT (that likewise cannot be placed in a delay slot) that decay to | |
3191 | a NOP. In all these cases the macros precede any corresponding real | |
3192 | instruction definitions in the opcode table, so they will match in the | |
3193 | second pass where the size of the delay slot is ignored and therefore | |
3194 | produce correct code. */ | |
df58fc94 RS |
3195 | |
3196 | static bfd_boolean | |
3197 | is_delay_slot_valid (const struct mips_opcode *mo) | |
3198 | { | |
3199 | if (!mips_opts.micromips) | |
3200 | return TRUE; | |
3201 | ||
3202 | if (mo->pinfo == INSN_MACRO) | |
c06dec14 | 3203 | return (history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) == 0; |
df58fc94 RS |
3204 | if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0 |
3205 | && micromips_insn_length (mo) != 4) | |
3206 | return FALSE; | |
3207 | if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 | |
3208 | && micromips_insn_length (mo) != 2) | |
3209 | return FALSE; | |
3210 | ||
3211 | return TRUE; | |
3212 | } | |
3213 | ||
fc76e730 RS |
3214 | /* For consistency checking, verify that all bits of OPCODE are specified |
3215 | either by the match/mask part of the instruction definition, or by the | |
3216 | operand list. Also build up a list of operands in OPERANDS. | |
3217 | ||
3218 | INSN_BITS says which bits of the instruction are significant. | |
3219 | If OPCODE is a standard or microMIPS instruction, DECODE_OPERAND | |
3220 | provides the mips_operand description of each operand. DECODE_OPERAND | |
3221 | is null for MIPS16 instructions. */ | |
ab902481 RS |
3222 | |
3223 | static int | |
3224 | validate_mips_insn (const struct mips_opcode *opcode, | |
3225 | unsigned long insn_bits, | |
fc76e730 RS |
3226 | const struct mips_operand *(*decode_operand) (const char *), |
3227 | struct mips_operand_array *operands) | |
ab902481 RS |
3228 | { |
3229 | const char *s; | |
fc76e730 | 3230 | unsigned long used_bits, doubled, undefined, opno, mask; |
ab902481 RS |
3231 | const struct mips_operand *operand; |
3232 | ||
fc76e730 RS |
3233 | mask = (opcode->pinfo == INSN_MACRO ? 0 : opcode->mask); |
3234 | if ((mask & opcode->match) != opcode->match) | |
ab902481 RS |
3235 | { |
3236 | as_bad (_("internal: bad mips opcode (mask error): %s %s"), | |
3237 | opcode->name, opcode->args); | |
3238 | return 0; | |
3239 | } | |
3240 | used_bits = 0; | |
fc76e730 | 3241 | opno = 0; |
14daeee3 RS |
3242 | if (opcode->pinfo2 & INSN2_VU0_CHANNEL_SUFFIX) |
3243 | used_bits = mips_insert_operand (&mips_vu0_channel_mask, used_bits, -1); | |
ab902481 RS |
3244 | for (s = opcode->args; *s; ++s) |
3245 | switch (*s) | |
3246 | { | |
3247 | case ',': | |
3248 | case '(': | |
3249 | case ')': | |
3250 | break; | |
3251 | ||
14daeee3 RS |
3252 | case '#': |
3253 | s++; | |
3254 | break; | |
3255 | ||
ab902481 | 3256 | default: |
fc76e730 RS |
3257 | if (!decode_operand) |
3258 | operand = decode_mips16_operand (*s, FALSE); | |
3259 | else | |
3260 | operand = decode_operand (s); | |
3261 | if (!operand && opcode->pinfo != INSN_MACRO) | |
ab902481 RS |
3262 | { |
3263 | as_bad (_("internal: unknown operand type: %s %s"), | |
3264 | opcode->name, opcode->args); | |
3265 | return 0; | |
3266 | } | |
fc76e730 RS |
3267 | gas_assert (opno < MAX_OPERANDS); |
3268 | operands->operand[opno] = operand; | |
14daeee3 | 3269 | if (operand && operand->type != OP_VU0_MATCH_SUFFIX) |
fc76e730 | 3270 | { |
14daeee3 | 3271 | used_bits = mips_insert_operand (operand, used_bits, -1); |
fc76e730 RS |
3272 | if (operand->type == OP_MDMX_IMM_REG) |
3273 | /* Bit 5 is the format selector (OB vs QH). The opcode table | |
3274 | has separate entries for each format. */ | |
3275 | used_bits &= ~(1 << (operand->lsb + 5)); | |
3276 | if (operand->type == OP_ENTRY_EXIT_LIST) | |
3277 | used_bits &= ~(mask & 0x700); | |
3278 | } | |
ab902481 | 3279 | /* Skip prefix characters. */ |
fc76e730 | 3280 | if (decode_operand && (*s == '+' || *s == 'm')) |
ab902481 | 3281 | ++s; |
fc76e730 | 3282 | opno += 1; |
ab902481 RS |
3283 | break; |
3284 | } | |
fc76e730 | 3285 | doubled = used_bits & mask & insn_bits; |
ab902481 RS |
3286 | if (doubled) |
3287 | { | |
3288 | as_bad (_("internal: bad mips opcode (bits 0x%08lx doubly defined):" | |
3289 | " %s %s"), doubled, opcode->name, opcode->args); | |
3290 | return 0; | |
3291 | } | |
fc76e730 | 3292 | used_bits |= mask; |
ab902481 | 3293 | undefined = ~used_bits & insn_bits; |
fc76e730 | 3294 | if (opcode->pinfo != INSN_MACRO && undefined) |
ab902481 RS |
3295 | { |
3296 | as_bad (_("internal: bad mips opcode (bits 0x%08lx undefined): %s %s"), | |
3297 | undefined, opcode->name, opcode->args); | |
3298 | return 0; | |
3299 | } | |
3300 | used_bits &= ~insn_bits; | |
3301 | if (used_bits) | |
3302 | { | |
3303 | as_bad (_("internal: bad mips opcode (bits 0x%08lx defined): %s %s"), | |
3304 | used_bits, opcode->name, opcode->args); | |
3305 | return 0; | |
3306 | } | |
3307 | return 1; | |
3308 | } | |
3309 | ||
fc76e730 RS |
3310 | /* The MIPS16 version of validate_mips_insn. */ |
3311 | ||
3312 | static int | |
3313 | validate_mips16_insn (const struct mips_opcode *opcode, | |
3314 | struct mips_operand_array *operands) | |
3315 | { | |
3316 | if (opcode->args[0] == 'a' || opcode->args[0] == 'i') | |
3317 | { | |
3318 | /* In this case OPCODE defines the first 16 bits in a 32-bit jump | |
3319 | instruction. Use TMP to describe the full instruction. */ | |
3320 | struct mips_opcode tmp; | |
3321 | ||
3322 | tmp = *opcode; | |
3323 | tmp.match <<= 16; | |
3324 | tmp.mask <<= 16; | |
3325 | return validate_mips_insn (&tmp, 0xffffffff, 0, operands); | |
3326 | } | |
3327 | return validate_mips_insn (opcode, 0xffff, 0, operands); | |
3328 | } | |
3329 | ||
ab902481 RS |
3330 | /* The microMIPS version of validate_mips_insn. */ |
3331 | ||
3332 | static int | |
fc76e730 RS |
3333 | validate_micromips_insn (const struct mips_opcode *opc, |
3334 | struct mips_operand_array *operands) | |
ab902481 RS |
3335 | { |
3336 | unsigned long insn_bits; | |
3337 | unsigned long major; | |
3338 | unsigned int length; | |
3339 | ||
fc76e730 RS |
3340 | if (opc->pinfo == INSN_MACRO) |
3341 | return validate_mips_insn (opc, 0xffffffff, decode_micromips_operand, | |
3342 | operands); | |
3343 | ||
ab902481 RS |
3344 | length = micromips_insn_length (opc); |
3345 | if (length != 2 && length != 4) | |
3346 | { | |
1661c76c | 3347 | as_bad (_("internal error: bad microMIPS opcode (incorrect length: %u): " |
ab902481 RS |
3348 | "%s %s"), length, opc->name, opc->args); |
3349 | return 0; | |
3350 | } | |
3351 | major = opc->match >> (10 + 8 * (length - 2)); | |
3352 | if ((length == 2 && (major & 7) != 1 && (major & 6) != 2) | |
3353 | || (length == 4 && (major & 7) != 0 && (major & 4) != 4)) | |
3354 | { | |
1661c76c | 3355 | as_bad (_("internal error: bad microMIPS opcode " |
ab902481 RS |
3356 | "(opcode/length mismatch): %s %s"), opc->name, opc->args); |
3357 | return 0; | |
3358 | } | |
3359 | ||
3360 | /* Shift piecewise to avoid an overflow where unsigned long is 32-bit. */ | |
3361 | insn_bits = 1 << 4 * length; | |
3362 | insn_bits <<= 4 * length; | |
3363 | insn_bits -= 1; | |
fc76e730 RS |
3364 | return validate_mips_insn (opc, insn_bits, decode_micromips_operand, |
3365 | operands); | |
ab902481 RS |
3366 | } |
3367 | ||
707bfff6 TS |
3368 | /* This function is called once, at assembler startup time. It should set up |
3369 | all the tables, etc. that the MD part of the assembler will need. */ | |
156c2f8b | 3370 | |
252b5132 | 3371 | void |
17a2f251 | 3372 | md_begin (void) |
252b5132 | 3373 | { |
3994f87e | 3374 | const char *retval = NULL; |
156c2f8b | 3375 | int i = 0; |
252b5132 | 3376 | int broken = 0; |
1f25f5d3 | 3377 | |
0a44bf69 RS |
3378 | if (mips_pic != NO_PIC) |
3379 | { | |
3380 | if (g_switch_seen && g_switch_value != 0) | |
3381 | as_bad (_("-G may not be used in position-independent code")); | |
3382 | g_switch_value = 0; | |
3383 | } | |
3384 | ||
0b35dfee | 3385 | if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_opts.arch)) |
1661c76c | 3386 | as_warn (_("could not set architecture and machine")); |
252b5132 | 3387 | |
252b5132 RH |
3388 | op_hash = hash_new (); |
3389 | ||
fc76e730 | 3390 | mips_operands = XCNEWVEC (struct mips_operand_array, NUMOPCODES); |
252b5132 RH |
3391 | for (i = 0; i < NUMOPCODES;) |
3392 | { | |
3393 | const char *name = mips_opcodes[i].name; | |
3394 | ||
17a2f251 | 3395 | retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]); |
252b5132 RH |
3396 | if (retval != NULL) |
3397 | { | |
3398 | fprintf (stderr, _("internal error: can't hash `%s': %s\n"), | |
3399 | mips_opcodes[i].name, retval); | |
3400 | /* Probably a memory allocation problem? Give up now. */ | |
1661c76c | 3401 | as_fatal (_("broken assembler, no assembly attempted")); |
252b5132 RH |
3402 | } |
3403 | do | |
3404 | { | |
fc76e730 RS |
3405 | if (!validate_mips_insn (&mips_opcodes[i], 0xffffffff, |
3406 | decode_mips_operand, &mips_operands[i])) | |
3407 | broken = 1; | |
3408 | if (nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0) | |
252b5132 | 3409 | { |
fc76e730 RS |
3410 | create_insn (&nop_insn, mips_opcodes + i); |
3411 | if (mips_fix_loongson2f_nop) | |
3412 | nop_insn.insn_opcode = LOONGSON2F_NOP_INSN; | |
3413 | nop_insn.fixed_p = 1; | |
252b5132 RH |
3414 | } |
3415 | ++i; | |
3416 | } | |
3417 | while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name)); | |
3418 | } | |
3419 | ||
3420 | mips16_op_hash = hash_new (); | |
fc76e730 RS |
3421 | mips16_operands = XCNEWVEC (struct mips_operand_array, |
3422 | bfd_mips16_num_opcodes); | |
252b5132 RH |
3423 | |
3424 | i = 0; | |
3425 | while (i < bfd_mips16_num_opcodes) | |
3426 | { | |
3427 | const char *name = mips16_opcodes[i].name; | |
3428 | ||
17a2f251 | 3429 | retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]); |
252b5132 RH |
3430 | if (retval != NULL) |
3431 | as_fatal (_("internal: can't hash `%s': %s"), | |
3432 | mips16_opcodes[i].name, retval); | |
3433 | do | |
3434 | { | |
fc76e730 RS |
3435 | if (!validate_mips16_insn (&mips16_opcodes[i], &mips16_operands[i])) |
3436 | broken = 1; | |
1e915849 RS |
3437 | if (mips16_nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0) |
3438 | { | |
3439 | create_insn (&mips16_nop_insn, mips16_opcodes + i); | |
3440 | mips16_nop_insn.fixed_p = 1; | |
3441 | } | |
252b5132 RH |
3442 | ++i; |
3443 | } | |
3444 | while (i < bfd_mips16_num_opcodes | |
3445 | && strcmp (mips16_opcodes[i].name, name) == 0); | |
3446 | } | |
3447 | ||
df58fc94 | 3448 | micromips_op_hash = hash_new (); |
fc76e730 RS |
3449 | micromips_operands = XCNEWVEC (struct mips_operand_array, |
3450 | bfd_micromips_num_opcodes); | |
df58fc94 RS |
3451 | |
3452 | i = 0; | |
3453 | while (i < bfd_micromips_num_opcodes) | |
3454 | { | |
3455 | const char *name = micromips_opcodes[i].name; | |
3456 | ||
3457 | retval = hash_insert (micromips_op_hash, name, | |
3458 | (void *) µmips_opcodes[i]); | |
3459 | if (retval != NULL) | |
3460 | as_fatal (_("internal: can't hash `%s': %s"), | |
3461 | micromips_opcodes[i].name, retval); | |
3462 | do | |
fc76e730 RS |
3463 | { |
3464 | struct mips_cl_insn *micromips_nop_insn; | |
3465 | ||
3466 | if (!validate_micromips_insn (µmips_opcodes[i], | |
3467 | µmips_operands[i])) | |
3468 | broken = 1; | |
3469 | ||
3470 | if (micromips_opcodes[i].pinfo != INSN_MACRO) | |
3471 | { | |
3472 | if (micromips_insn_length (micromips_opcodes + i) == 2) | |
3473 | micromips_nop_insn = µmips_nop16_insn; | |
3474 | else if (micromips_insn_length (micromips_opcodes + i) == 4) | |
3475 | micromips_nop_insn = µmips_nop32_insn; | |
3476 | else | |
3477 | continue; | |
3478 | ||
3479 | if (micromips_nop_insn->insn_mo == NULL | |
3480 | && strcmp (name, "nop") == 0) | |
3481 | { | |
3482 | create_insn (micromips_nop_insn, micromips_opcodes + i); | |
3483 | micromips_nop_insn->fixed_p = 1; | |
3484 | } | |
3485 | } | |
3486 | } | |
df58fc94 RS |
3487 | while (++i < bfd_micromips_num_opcodes |
3488 | && strcmp (micromips_opcodes[i].name, name) == 0); | |
3489 | } | |
3490 | ||
252b5132 | 3491 | if (broken) |
1661c76c | 3492 | as_fatal (_("broken assembler, no assembly attempted")); |
252b5132 RH |
3493 | |
3494 | /* We add all the general register names to the symbol table. This | |
3495 | helps us detect invalid uses of them. */ | |
707bfff6 TS |
3496 | for (i = 0; reg_names[i].name; i++) |
3497 | symbol_table_insert (symbol_new (reg_names[i].name, reg_section, | |
8fc4ee9b | 3498 | reg_names[i].num, /* & RNUM_MASK, */ |
707bfff6 TS |
3499 | &zero_address_frag)); |
3500 | if (HAVE_NEWABI) | |
3501 | for (i = 0; reg_names_n32n64[i].name; i++) | |
3502 | symbol_table_insert (symbol_new (reg_names_n32n64[i].name, reg_section, | |
8fc4ee9b | 3503 | reg_names_n32n64[i].num, /* & RNUM_MASK, */ |
252b5132 | 3504 | &zero_address_frag)); |
707bfff6 TS |
3505 | else |
3506 | for (i = 0; reg_names_o32[i].name; i++) | |
3507 | symbol_table_insert (symbol_new (reg_names_o32[i].name, reg_section, | |
8fc4ee9b | 3508 | reg_names_o32[i].num, /* & RNUM_MASK, */ |
6047c971 | 3509 | &zero_address_frag)); |
6047c971 | 3510 | |
14daeee3 RS |
3511 | for (i = 0; i < 32; i++) |
3512 | { | |
3513 | char regname[7]; | |
3514 | ||
3515 | /* R5900 VU0 floating-point register. */ | |
3516 | regname[sizeof (rename) - 1] = 0; | |
3517 | snprintf (regname, sizeof (regname) - 1, "$vf%d", i); | |
3518 | symbol_table_insert (symbol_new (regname, reg_section, | |
3519 | RTYPE_VF | i, &zero_address_frag)); | |
3520 | ||
3521 | /* R5900 VU0 integer register. */ | |
3522 | snprintf (regname, sizeof (regname) - 1, "$vi%d", i); | |
3523 | symbol_table_insert (symbol_new (regname, reg_section, | |
3524 | RTYPE_VI | i, &zero_address_frag)); | |
3525 | ||
56d438b1 CF |
3526 | /* MSA register. */ |
3527 | snprintf (regname, sizeof (regname) - 1, "$w%d", i); | |
3528 | symbol_table_insert (symbol_new (regname, reg_section, | |
3529 | RTYPE_MSA | i, &zero_address_frag)); | |
14daeee3 RS |
3530 | } |
3531 | ||
a92713e6 RS |
3532 | obstack_init (&mips_operand_tokens); |
3533 | ||
7d10b47d | 3534 | mips_no_prev_insn (); |
252b5132 RH |
3535 | |
3536 | mips_gprmask = 0; | |
3537 | mips_cprmask[0] = 0; | |
3538 | mips_cprmask[1] = 0; | |
3539 | mips_cprmask[2] = 0; | |
3540 | mips_cprmask[3] = 0; | |
3541 | ||
3542 | /* set the default alignment for the text section (2**2) */ | |
3543 | record_alignment (text_section, 2); | |
3544 | ||
4d0d148d | 3545 | bfd_set_gp_size (stdoutput, g_switch_value); |
252b5132 | 3546 | |
f3ded42a RS |
3547 | /* On a native system other than VxWorks, sections must be aligned |
3548 | to 16 byte boundaries. When configured for an embedded ELF | |
3549 | target, we don't bother. */ | |
3550 | if (strncmp (TARGET_OS, "elf", 3) != 0 | |
3551 | && strncmp (TARGET_OS, "vxworks", 7) != 0) | |
252b5132 | 3552 | { |
f3ded42a RS |
3553 | (void) bfd_set_section_alignment (stdoutput, text_section, 4); |
3554 | (void) bfd_set_section_alignment (stdoutput, data_section, 4); | |
3555 | (void) bfd_set_section_alignment (stdoutput, bss_section, 4); | |
3556 | } | |
252b5132 | 3557 | |
f3ded42a RS |
3558 | /* Create a .reginfo section for register masks and a .mdebug |
3559 | section for debugging information. */ | |
3560 | { | |
3561 | segT seg; | |
3562 | subsegT subseg; | |
3563 | flagword flags; | |
3564 | segT sec; | |
3565 | ||
3566 | seg = now_seg; | |
3567 | subseg = now_subseg; | |
3568 | ||
3569 | /* The ABI says this section should be loaded so that the | |
3570 | running program can access it. However, we don't load it | |
3571 | if we are configured for an embedded target */ | |
3572 | flags = SEC_READONLY | SEC_DATA; | |
3573 | if (strncmp (TARGET_OS, "elf", 3) != 0) | |
3574 | flags |= SEC_ALLOC | SEC_LOAD; | |
3575 | ||
3576 | if (mips_abi != N64_ABI) | |
252b5132 | 3577 | { |
f3ded42a | 3578 | sec = subseg_new (".reginfo", (subsegT) 0); |
bdaaa2e1 | 3579 | |
f3ded42a RS |
3580 | bfd_set_section_flags (stdoutput, sec, flags); |
3581 | bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2); | |
252b5132 | 3582 | |
f3ded42a RS |
3583 | mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo)); |
3584 | } | |
3585 | else | |
3586 | { | |
3587 | /* The 64-bit ABI uses a .MIPS.options section rather than | |
3588 | .reginfo section. */ | |
3589 | sec = subseg_new (".MIPS.options", (subsegT) 0); | |
3590 | bfd_set_section_flags (stdoutput, sec, flags); | |
3591 | bfd_set_section_alignment (stdoutput, sec, 3); | |
252b5132 | 3592 | |
f3ded42a RS |
3593 | /* Set up the option header. */ |
3594 | { | |
3595 | Elf_Internal_Options opthdr; | |
3596 | char *f; | |
3597 | ||
3598 | opthdr.kind = ODK_REGINFO; | |
3599 | opthdr.size = (sizeof (Elf_External_Options) | |
3600 | + sizeof (Elf64_External_RegInfo)); | |
3601 | opthdr.section = 0; | |
3602 | opthdr.info = 0; | |
3603 | f = frag_more (sizeof (Elf_External_Options)); | |
3604 | bfd_mips_elf_swap_options_out (stdoutput, &opthdr, | |
3605 | (Elf_External_Options *) f); | |
3606 | ||
3607 | mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo)); | |
3608 | } | |
3609 | } | |
252b5132 | 3610 | |
f3ded42a RS |
3611 | if (ECOFF_DEBUGGING) |
3612 | { | |
3613 | sec = subseg_new (".mdebug", (subsegT) 0); | |
3614 | (void) bfd_set_section_flags (stdoutput, sec, | |
3615 | SEC_HAS_CONTENTS | SEC_READONLY); | |
3616 | (void) bfd_set_section_alignment (stdoutput, sec, 2); | |
252b5132 | 3617 | } |
f3ded42a RS |
3618 | else if (mips_flag_pdr) |
3619 | { | |
3620 | pdr_seg = subseg_new (".pdr", (subsegT) 0); | |
3621 | (void) bfd_set_section_flags (stdoutput, pdr_seg, | |
3622 | SEC_READONLY | SEC_RELOC | |
3623 | | SEC_DEBUGGING); | |
3624 | (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2); | |
3625 | } | |
3626 | ||
3627 | subseg_set (seg, subseg); | |
3628 | } | |
252b5132 | 3629 | |
71400594 RS |
3630 | if (mips_fix_vr4120) |
3631 | init_vr4120_conflicts (); | |
252b5132 RH |
3632 | } |
3633 | ||
252b5132 | 3634 | void |
17a2f251 | 3635 | md_assemble (char *str) |
252b5132 RH |
3636 | { |
3637 | struct mips_cl_insn insn; | |
f6688943 TS |
3638 | bfd_reloc_code_real_type unused_reloc[3] |
3639 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 RH |
3640 | |
3641 | imm_expr.X_op = O_absent; | |
252b5132 | 3642 | offset_expr.X_op = O_absent; |
f6688943 TS |
3643 | offset_reloc[0] = BFD_RELOC_UNUSED; |
3644 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
3645 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 | 3646 | |
e1b47bd5 RS |
3647 | mips_mark_labels (); |
3648 | mips_assembling_insn = TRUE; | |
e3de51ce | 3649 | clear_insn_error (); |
e1b47bd5 | 3650 | |
252b5132 RH |
3651 | if (mips_opts.mips16) |
3652 | mips16_ip (str, &insn); | |
3653 | else | |
3654 | { | |
3655 | mips_ip (str, &insn); | |
beae10d5 KH |
3656 | DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"), |
3657 | str, insn.insn_opcode)); | |
252b5132 RH |
3658 | } |
3659 | ||
e3de51ce RS |
3660 | if (insn_error.msg) |
3661 | report_insn_error (str); | |
e1b47bd5 | 3662 | else if (insn.insn_mo->pinfo == INSN_MACRO) |
252b5132 | 3663 | { |
584892a6 | 3664 | macro_start (); |
252b5132 RH |
3665 | if (mips_opts.mips16) |
3666 | mips16_macro (&insn); | |
3667 | else | |
833794fc | 3668 | macro (&insn, str); |
584892a6 | 3669 | macro_end (); |
252b5132 RH |
3670 | } |
3671 | else | |
3672 | { | |
77bd4346 | 3673 | if (offset_expr.X_op != O_absent) |
df58fc94 | 3674 | append_insn (&insn, &offset_expr, offset_reloc, FALSE); |
252b5132 | 3675 | else |
df58fc94 | 3676 | append_insn (&insn, NULL, unused_reloc, FALSE); |
252b5132 | 3677 | } |
e1b47bd5 RS |
3678 | |
3679 | mips_assembling_insn = FALSE; | |
252b5132 RH |
3680 | } |
3681 | ||
738e5348 RS |
3682 | /* Convenience functions for abstracting away the differences between |
3683 | MIPS16 and non-MIPS16 relocations. */ | |
3684 | ||
3685 | static inline bfd_boolean | |
3686 | mips16_reloc_p (bfd_reloc_code_real_type reloc) | |
3687 | { | |
3688 | switch (reloc) | |
3689 | { | |
3690 | case BFD_RELOC_MIPS16_JMP: | |
3691 | case BFD_RELOC_MIPS16_GPREL: | |
3692 | case BFD_RELOC_MIPS16_GOT16: | |
3693 | case BFD_RELOC_MIPS16_CALL16: | |
3694 | case BFD_RELOC_MIPS16_HI16_S: | |
3695 | case BFD_RELOC_MIPS16_HI16: | |
3696 | case BFD_RELOC_MIPS16_LO16: | |
3697 | return TRUE; | |
3698 | ||
3699 | default: | |
3700 | return FALSE; | |
3701 | } | |
3702 | } | |
3703 | ||
df58fc94 RS |
3704 | static inline bfd_boolean |
3705 | micromips_reloc_p (bfd_reloc_code_real_type reloc) | |
3706 | { | |
3707 | switch (reloc) | |
3708 | { | |
3709 | case BFD_RELOC_MICROMIPS_7_PCREL_S1: | |
3710 | case BFD_RELOC_MICROMIPS_10_PCREL_S1: | |
3711 | case BFD_RELOC_MICROMIPS_16_PCREL_S1: | |
3712 | case BFD_RELOC_MICROMIPS_GPREL16: | |
3713 | case BFD_RELOC_MICROMIPS_JMP: | |
3714 | case BFD_RELOC_MICROMIPS_HI16: | |
3715 | case BFD_RELOC_MICROMIPS_HI16_S: | |
3716 | case BFD_RELOC_MICROMIPS_LO16: | |
3717 | case BFD_RELOC_MICROMIPS_LITERAL: | |
3718 | case BFD_RELOC_MICROMIPS_GOT16: | |
3719 | case BFD_RELOC_MICROMIPS_CALL16: | |
3720 | case BFD_RELOC_MICROMIPS_GOT_HI16: | |
3721 | case BFD_RELOC_MICROMIPS_GOT_LO16: | |
3722 | case BFD_RELOC_MICROMIPS_CALL_HI16: | |
3723 | case BFD_RELOC_MICROMIPS_CALL_LO16: | |
3724 | case BFD_RELOC_MICROMIPS_SUB: | |
3725 | case BFD_RELOC_MICROMIPS_GOT_PAGE: | |
3726 | case BFD_RELOC_MICROMIPS_GOT_OFST: | |
3727 | case BFD_RELOC_MICROMIPS_GOT_DISP: | |
3728 | case BFD_RELOC_MICROMIPS_HIGHEST: | |
3729 | case BFD_RELOC_MICROMIPS_HIGHER: | |
3730 | case BFD_RELOC_MICROMIPS_SCN_DISP: | |
3731 | case BFD_RELOC_MICROMIPS_JALR: | |
3732 | return TRUE; | |
3733 | ||
3734 | default: | |
3735 | return FALSE; | |
3736 | } | |
3737 | } | |
3738 | ||
2309ddf2 MR |
3739 | static inline bfd_boolean |
3740 | jmp_reloc_p (bfd_reloc_code_real_type reloc) | |
3741 | { | |
3742 | return reloc == BFD_RELOC_MIPS_JMP || reloc == BFD_RELOC_MICROMIPS_JMP; | |
3743 | } | |
3744 | ||
738e5348 RS |
3745 | static inline bfd_boolean |
3746 | got16_reloc_p (bfd_reloc_code_real_type reloc) | |
3747 | { | |
2309ddf2 | 3748 | return (reloc == BFD_RELOC_MIPS_GOT16 || reloc == BFD_RELOC_MIPS16_GOT16 |
df58fc94 | 3749 | || reloc == BFD_RELOC_MICROMIPS_GOT16); |
738e5348 RS |
3750 | } |
3751 | ||
3752 | static inline bfd_boolean | |
3753 | hi16_reloc_p (bfd_reloc_code_real_type reloc) | |
3754 | { | |
2309ddf2 | 3755 | return (reloc == BFD_RELOC_HI16_S || reloc == BFD_RELOC_MIPS16_HI16_S |
df58fc94 | 3756 | || reloc == BFD_RELOC_MICROMIPS_HI16_S); |
738e5348 RS |
3757 | } |
3758 | ||
3759 | static inline bfd_boolean | |
3760 | lo16_reloc_p (bfd_reloc_code_real_type reloc) | |
3761 | { | |
2309ddf2 | 3762 | return (reloc == BFD_RELOC_LO16 || reloc == BFD_RELOC_MIPS16_LO16 |
df58fc94 RS |
3763 | || reloc == BFD_RELOC_MICROMIPS_LO16); |
3764 | } | |
3765 | ||
df58fc94 RS |
3766 | static inline bfd_boolean |
3767 | jalr_reloc_p (bfd_reloc_code_real_type reloc) | |
3768 | { | |
2309ddf2 | 3769 | return reloc == BFD_RELOC_MIPS_JALR || reloc == BFD_RELOC_MICROMIPS_JALR; |
738e5348 RS |
3770 | } |
3771 | ||
f2ae14a1 RS |
3772 | static inline bfd_boolean |
3773 | gprel16_reloc_p (bfd_reloc_code_real_type reloc) | |
3774 | { | |
3775 | return (reloc == BFD_RELOC_GPREL16 || reloc == BFD_RELOC_MIPS16_GPREL | |
3776 | || reloc == BFD_RELOC_MICROMIPS_GPREL16); | |
3777 | } | |
3778 | ||
2de39019 CM |
3779 | /* Return true if RELOC is a PC-relative relocation that does not have |
3780 | full address range. */ | |
3781 | ||
3782 | static inline bfd_boolean | |
3783 | limited_pcrel_reloc_p (bfd_reloc_code_real_type reloc) | |
3784 | { | |
3785 | switch (reloc) | |
3786 | { | |
3787 | case BFD_RELOC_16_PCREL_S2: | |
3788 | case BFD_RELOC_MICROMIPS_7_PCREL_S1: | |
3789 | case BFD_RELOC_MICROMIPS_10_PCREL_S1: | |
3790 | case BFD_RELOC_MICROMIPS_16_PCREL_S1: | |
3791 | return TRUE; | |
3792 | ||
b47468a6 CM |
3793 | case BFD_RELOC_32_PCREL: |
3794 | return HAVE_64BIT_ADDRESSES; | |
3795 | ||
2de39019 CM |
3796 | default: |
3797 | return FALSE; | |
3798 | } | |
3799 | } | |
b47468a6 | 3800 | |
5919d012 | 3801 | /* Return true if the given relocation might need a matching %lo(). |
0a44bf69 RS |
3802 | This is only "might" because SVR4 R_MIPS_GOT16 relocations only |
3803 | need a matching %lo() when applied to local symbols. */ | |
5919d012 RS |
3804 | |
3805 | static inline bfd_boolean | |
17a2f251 | 3806 | reloc_needs_lo_p (bfd_reloc_code_real_type reloc) |
5919d012 | 3807 | { |
3b91255e | 3808 | return (HAVE_IN_PLACE_ADDENDS |
738e5348 | 3809 | && (hi16_reloc_p (reloc) |
0a44bf69 RS |
3810 | /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo(); |
3811 | all GOT16 relocations evaluate to "G". */ | |
738e5348 RS |
3812 | || (got16_reloc_p (reloc) && mips_pic != VXWORKS_PIC))); |
3813 | } | |
3814 | ||
3815 | /* Return the type of %lo() reloc needed by RELOC, given that | |
3816 | reloc_needs_lo_p. */ | |
3817 | ||
3818 | static inline bfd_reloc_code_real_type | |
3819 | matching_lo_reloc (bfd_reloc_code_real_type reloc) | |
3820 | { | |
df58fc94 RS |
3821 | return (mips16_reloc_p (reloc) ? BFD_RELOC_MIPS16_LO16 |
3822 | : (micromips_reloc_p (reloc) ? BFD_RELOC_MICROMIPS_LO16 | |
3823 | : BFD_RELOC_LO16)); | |
5919d012 RS |
3824 | } |
3825 | ||
3826 | /* Return true if the given fixup is followed by a matching R_MIPS_LO16 | |
3827 | relocation. */ | |
3828 | ||
3829 | static inline bfd_boolean | |
17a2f251 | 3830 | fixup_has_matching_lo_p (fixS *fixp) |
5919d012 RS |
3831 | { |
3832 | return (fixp->fx_next != NULL | |
738e5348 | 3833 | && fixp->fx_next->fx_r_type == matching_lo_reloc (fixp->fx_r_type) |
5919d012 RS |
3834 | && fixp->fx_addsy == fixp->fx_next->fx_addsy |
3835 | && fixp->fx_offset == fixp->fx_next->fx_offset); | |
3836 | } | |
3837 | ||
462427c4 RS |
3838 | /* Move all labels in LABELS to the current insertion point. TEXT_P |
3839 | says whether the labels refer to text or data. */ | |
404a8071 RS |
3840 | |
3841 | static void | |
462427c4 | 3842 | mips_move_labels (struct insn_label_list *labels, bfd_boolean text_p) |
404a8071 RS |
3843 | { |
3844 | struct insn_label_list *l; | |
3845 | valueT val; | |
3846 | ||
462427c4 | 3847 | for (l = labels; l != NULL; l = l->next) |
404a8071 | 3848 | { |
9c2799c2 | 3849 | gas_assert (S_GET_SEGMENT (l->label) == now_seg); |
404a8071 RS |
3850 | symbol_set_frag (l->label, frag_now); |
3851 | val = (valueT) frag_now_fix (); | |
df58fc94 | 3852 | /* MIPS16/microMIPS text labels are stored as odd. */ |
462427c4 | 3853 | if (text_p && HAVE_CODE_COMPRESSION) |
404a8071 RS |
3854 | ++val; |
3855 | S_SET_VALUE (l->label, val); | |
3856 | } | |
3857 | } | |
3858 | ||
462427c4 RS |
3859 | /* Move all labels in insn_labels to the current insertion point |
3860 | and treat them as text labels. */ | |
3861 | ||
3862 | static void | |
3863 | mips_move_text_labels (void) | |
3864 | { | |
3865 | mips_move_labels (seg_info (now_seg)->label_list, TRUE); | |
3866 | } | |
3867 | ||
5f0fe04b TS |
3868 | static bfd_boolean |
3869 | s_is_linkonce (symbolS *sym, segT from_seg) | |
3870 | { | |
3871 | bfd_boolean linkonce = FALSE; | |
3872 | segT symseg = S_GET_SEGMENT (sym); | |
3873 | ||
3874 | if (symseg != from_seg && !S_IS_LOCAL (sym)) | |
3875 | { | |
3876 | if ((bfd_get_section_flags (stdoutput, symseg) & SEC_LINK_ONCE)) | |
3877 | linkonce = TRUE; | |
5f0fe04b TS |
3878 | /* The GNU toolchain uses an extension for ELF: a section |
3879 | beginning with the magic string .gnu.linkonce is a | |
3880 | linkonce section. */ | |
3881 | if (strncmp (segment_name (symseg), ".gnu.linkonce", | |
3882 | sizeof ".gnu.linkonce" - 1) == 0) | |
3883 | linkonce = TRUE; | |
5f0fe04b TS |
3884 | } |
3885 | return linkonce; | |
3886 | } | |
3887 | ||
e1b47bd5 | 3888 | /* Mark MIPS16 or microMIPS instruction label LABEL. This permits the |
df58fc94 RS |
3889 | linker to handle them specially, such as generating jalx instructions |
3890 | when needed. We also make them odd for the duration of the assembly, | |
3891 | in order to generate the right sort of code. We will make them even | |
252b5132 RH |
3892 | in the adjust_symtab routine, while leaving them marked. This is |
3893 | convenient for the debugger and the disassembler. The linker knows | |
3894 | to make them odd again. */ | |
3895 | ||
3896 | static void | |
e1b47bd5 | 3897 | mips_compressed_mark_label (symbolS *label) |
252b5132 | 3898 | { |
df58fc94 | 3899 | gas_assert (HAVE_CODE_COMPRESSION); |
a8dbcb85 | 3900 | |
f3ded42a RS |
3901 | if (mips_opts.mips16) |
3902 | S_SET_OTHER (label, ELF_ST_SET_MIPS16 (S_GET_OTHER (label))); | |
3903 | else | |
3904 | S_SET_OTHER (label, ELF_ST_SET_MICROMIPS (S_GET_OTHER (label))); | |
e1b47bd5 RS |
3905 | if ((S_GET_VALUE (label) & 1) == 0 |
3906 | /* Don't adjust the address if the label is global or weak, or | |
3907 | in a link-once section, since we'll be emitting symbol reloc | |
3908 | references to it which will be patched up by the linker, and | |
3909 | the final value of the symbol may or may not be MIPS16/microMIPS. */ | |
3910 | && !S_IS_WEAK (label) | |
3911 | && !S_IS_EXTERNAL (label) | |
3912 | && !s_is_linkonce (label, now_seg)) | |
3913 | S_SET_VALUE (label, S_GET_VALUE (label) | 1); | |
3914 | } | |
3915 | ||
3916 | /* Mark preceding MIPS16 or microMIPS instruction labels. */ | |
3917 | ||
3918 | static void | |
3919 | mips_compressed_mark_labels (void) | |
3920 | { | |
3921 | struct insn_label_list *l; | |
3922 | ||
3923 | for (l = seg_info (now_seg)->label_list; l != NULL; l = l->next) | |
3924 | mips_compressed_mark_label (l->label); | |
252b5132 RH |
3925 | } |
3926 | ||
4d7206a2 RS |
3927 | /* End the current frag. Make it a variant frag and record the |
3928 | relaxation info. */ | |
3929 | ||
3930 | static void | |
3931 | relax_close_frag (void) | |
3932 | { | |
584892a6 | 3933 | mips_macro_warning.first_frag = frag_now; |
4d7206a2 | 3934 | frag_var (rs_machine_dependent, 0, 0, |
584892a6 | 3935 | RELAX_ENCODE (mips_relax.sizes[0], mips_relax.sizes[1]), |
4d7206a2 RS |
3936 | mips_relax.symbol, 0, (char *) mips_relax.first_fixup); |
3937 | ||
3938 | memset (&mips_relax.sizes, 0, sizeof (mips_relax.sizes)); | |
3939 | mips_relax.first_fixup = 0; | |
3940 | } | |
3941 | ||
3942 | /* Start a new relaxation sequence whose expansion depends on SYMBOL. | |
3943 | See the comment above RELAX_ENCODE for more details. */ | |
3944 | ||
3945 | static void | |
3946 | relax_start (symbolS *symbol) | |
3947 | { | |
9c2799c2 | 3948 | gas_assert (mips_relax.sequence == 0); |
4d7206a2 RS |
3949 | mips_relax.sequence = 1; |
3950 | mips_relax.symbol = symbol; | |
3951 | } | |
3952 | ||
3953 | /* Start generating the second version of a relaxable sequence. | |
3954 | See the comment above RELAX_ENCODE for more details. */ | |
252b5132 RH |
3955 | |
3956 | static void | |
4d7206a2 RS |
3957 | relax_switch (void) |
3958 | { | |
9c2799c2 | 3959 | gas_assert (mips_relax.sequence == 1); |
4d7206a2 RS |
3960 | mips_relax.sequence = 2; |
3961 | } | |
3962 | ||
3963 | /* End the current relaxable sequence. */ | |
3964 | ||
3965 | static void | |
3966 | relax_end (void) | |
3967 | { | |
9c2799c2 | 3968 | gas_assert (mips_relax.sequence == 2); |
4d7206a2 RS |
3969 | relax_close_frag (); |
3970 | mips_relax.sequence = 0; | |
3971 | } | |
3972 | ||
11625dd8 RS |
3973 | /* Return true if IP is a delayed branch or jump. */ |
3974 | ||
3975 | static inline bfd_boolean | |
3976 | delayed_branch_p (const struct mips_cl_insn *ip) | |
3977 | { | |
3978 | return (ip->insn_mo->pinfo & (INSN_UNCOND_BRANCH_DELAY | |
3979 | | INSN_COND_BRANCH_DELAY | |
3980 | | INSN_COND_BRANCH_LIKELY)) != 0; | |
3981 | } | |
3982 | ||
3983 | /* Return true if IP is a compact branch or jump. */ | |
3984 | ||
3985 | static inline bfd_boolean | |
3986 | compact_branch_p (const struct mips_cl_insn *ip) | |
3987 | { | |
26545944 RS |
3988 | return (ip->insn_mo->pinfo2 & (INSN2_UNCOND_BRANCH |
3989 | | INSN2_COND_BRANCH)) != 0; | |
11625dd8 RS |
3990 | } |
3991 | ||
3992 | /* Return true if IP is an unconditional branch or jump. */ | |
3993 | ||
3994 | static inline bfd_boolean | |
3995 | uncond_branch_p (const struct mips_cl_insn *ip) | |
3996 | { | |
3997 | return ((ip->insn_mo->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0 | |
26545944 | 3998 | || (ip->insn_mo->pinfo2 & INSN2_UNCOND_BRANCH) != 0); |
11625dd8 RS |
3999 | } |
4000 | ||
4001 | /* Return true if IP is a branch-likely instruction. */ | |
4002 | ||
4003 | static inline bfd_boolean | |
4004 | branch_likely_p (const struct mips_cl_insn *ip) | |
4005 | { | |
4006 | return (ip->insn_mo->pinfo & INSN_COND_BRANCH_LIKELY) != 0; | |
4007 | } | |
4008 | ||
14fe068b RS |
4009 | /* Return the type of nop that should be used to fill the delay slot |
4010 | of delayed branch IP. */ | |
4011 | ||
4012 | static struct mips_cl_insn * | |
4013 | get_delay_slot_nop (const struct mips_cl_insn *ip) | |
4014 | { | |
4015 | if (mips_opts.micromips | |
4016 | && (ip->insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) | |
4017 | return µmips_nop32_insn; | |
4018 | return NOP_INSN; | |
4019 | } | |
4020 | ||
fc76e730 RS |
4021 | /* Return a mask that has bit N set if OPCODE reads the register(s) |
4022 | in operand N. */ | |
df58fc94 RS |
4023 | |
4024 | static unsigned int | |
fc76e730 | 4025 | insn_read_mask (const struct mips_opcode *opcode) |
df58fc94 | 4026 | { |
fc76e730 RS |
4027 | return (opcode->pinfo & INSN_READ_ALL) >> INSN_READ_SHIFT; |
4028 | } | |
df58fc94 | 4029 | |
fc76e730 RS |
4030 | /* Return a mask that has bit N set if OPCODE writes to the register(s) |
4031 | in operand N. */ | |
4032 | ||
4033 | static unsigned int | |
4034 | insn_write_mask (const struct mips_opcode *opcode) | |
4035 | { | |
4036 | return (opcode->pinfo & INSN_WRITE_ALL) >> INSN_WRITE_SHIFT; | |
4037 | } | |
4038 | ||
4039 | /* Return a mask of the registers specified by operand OPERAND of INSN. | |
4040 | Ignore registers of type OP_REG_<t> unless bit OP_REG_<t> of TYPE_MASK | |
4041 | is set. */ | |
4042 | ||
4043 | static unsigned int | |
4044 | operand_reg_mask (const struct mips_cl_insn *insn, | |
4045 | const struct mips_operand *operand, | |
4046 | unsigned int type_mask) | |
4047 | { | |
4048 | unsigned int uval, vsel; | |
4049 | ||
4050 | switch (operand->type) | |
df58fc94 | 4051 | { |
fc76e730 RS |
4052 | case OP_INT: |
4053 | case OP_MAPPED_INT: | |
4054 | case OP_MSB: | |
4055 | case OP_PCREL: | |
4056 | case OP_PERF_REG: | |
4057 | case OP_ADDIUSP_INT: | |
4058 | case OP_ENTRY_EXIT_LIST: | |
4059 | case OP_REPEAT_DEST_REG: | |
4060 | case OP_REPEAT_PREV_REG: | |
4061 | case OP_PC: | |
14daeee3 RS |
4062 | case OP_VU0_SUFFIX: |
4063 | case OP_VU0_MATCH_SUFFIX: | |
56d438b1 | 4064 | case OP_IMM_INDEX: |
fc76e730 RS |
4065 | abort (); |
4066 | ||
4067 | case OP_REG: | |
0f35dbc4 | 4068 | case OP_OPTIONAL_REG: |
fc76e730 RS |
4069 | { |
4070 | const struct mips_reg_operand *reg_op; | |
4071 | ||
4072 | reg_op = (const struct mips_reg_operand *) operand; | |
4073 | if (!(type_mask & (1 << reg_op->reg_type))) | |
4074 | return 0; | |
4075 | uval = insn_extract_operand (insn, operand); | |
4076 | return 1 << mips_decode_reg_operand (reg_op, uval); | |
4077 | } | |
4078 | ||
4079 | case OP_REG_PAIR: | |
4080 | { | |
4081 | const struct mips_reg_pair_operand *pair_op; | |
4082 | ||
4083 | pair_op = (const struct mips_reg_pair_operand *) operand; | |
4084 | if (!(type_mask & (1 << pair_op->reg_type))) | |
4085 | return 0; | |
4086 | uval = insn_extract_operand (insn, operand); | |
4087 | return (1 << pair_op->reg1_map[uval]) | (1 << pair_op->reg2_map[uval]); | |
4088 | } | |
4089 | ||
4090 | case OP_CLO_CLZ_DEST: | |
4091 | if (!(type_mask & (1 << OP_REG_GP))) | |
4092 | return 0; | |
4093 | uval = insn_extract_operand (insn, operand); | |
4094 | return (1 << (uval & 31)) | (1 << (uval >> 5)); | |
4095 | ||
4096 | case OP_LWM_SWM_LIST: | |
4097 | abort (); | |
4098 | ||
4099 | case OP_SAVE_RESTORE_LIST: | |
4100 | abort (); | |
4101 | ||
4102 | case OP_MDMX_IMM_REG: | |
4103 | if (!(type_mask & (1 << OP_REG_VEC))) | |
4104 | return 0; | |
4105 | uval = insn_extract_operand (insn, operand); | |
4106 | vsel = uval >> 5; | |
4107 | if ((vsel & 0x18) == 0x18) | |
4108 | return 0; | |
4109 | return 1 << (uval & 31); | |
56d438b1 CF |
4110 | |
4111 | case OP_REG_INDEX: | |
4112 | if (!(type_mask & (1 << OP_REG_GP))) | |
4113 | return 0; | |
4114 | return 1 << insn_extract_operand (insn, operand); | |
df58fc94 | 4115 | } |
fc76e730 RS |
4116 | abort (); |
4117 | } | |
4118 | ||
4119 | /* Return a mask of the registers specified by operands OPNO_MASK of INSN, | |
4120 | where bit N of OPNO_MASK is set if operand N should be included. | |
4121 | Ignore registers of type OP_REG_<t> unless bit OP_REG_<t> of TYPE_MASK | |
4122 | is set. */ | |
4123 | ||
4124 | static unsigned int | |
4125 | insn_reg_mask (const struct mips_cl_insn *insn, | |
4126 | unsigned int type_mask, unsigned int opno_mask) | |
4127 | { | |
4128 | unsigned int opno, reg_mask; | |
4129 | ||
4130 | opno = 0; | |
4131 | reg_mask = 0; | |
4132 | while (opno_mask != 0) | |
4133 | { | |
4134 | if (opno_mask & 1) | |
4135 | reg_mask |= operand_reg_mask (insn, insn_opno (insn, opno), type_mask); | |
4136 | opno_mask >>= 1; | |
4137 | opno += 1; | |
4138 | } | |
4139 | return reg_mask; | |
df58fc94 RS |
4140 | } |
4141 | ||
4c260379 RS |
4142 | /* Return the mask of core registers that IP reads. */ |
4143 | ||
4144 | static unsigned int | |
4145 | gpr_read_mask (const struct mips_cl_insn *ip) | |
4146 | { | |
4147 | unsigned long pinfo, pinfo2; | |
4148 | unsigned int mask; | |
4149 | ||
fc76e730 | 4150 | mask = insn_reg_mask (ip, 1 << OP_REG_GP, insn_read_mask (ip->insn_mo)); |
4c260379 RS |
4151 | pinfo = ip->insn_mo->pinfo; |
4152 | pinfo2 = ip->insn_mo->pinfo2; | |
fc76e730 | 4153 | if (pinfo & INSN_UDI) |
4c260379 | 4154 | { |
fc76e730 RS |
4155 | /* UDI instructions have traditionally been assumed to read RS |
4156 | and RT. */ | |
4157 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RT, *ip); | |
4158 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RS, *ip); | |
4c260379 | 4159 | } |
fc76e730 RS |
4160 | if (pinfo & INSN_READ_GPR_24) |
4161 | mask |= 1 << 24; | |
4162 | if (pinfo2 & INSN2_READ_GPR_16) | |
4163 | mask |= 1 << 16; | |
4164 | if (pinfo2 & INSN2_READ_SP) | |
4165 | mask |= 1 << SP; | |
26545944 | 4166 | if (pinfo2 & INSN2_READ_GPR_31) |
fc76e730 | 4167 | mask |= 1 << 31; |
fe35f09f RS |
4168 | /* Don't include register 0. */ |
4169 | return mask & ~1; | |
4c260379 RS |
4170 | } |
4171 | ||
4172 | /* Return the mask of core registers that IP writes. */ | |
4173 | ||
4174 | static unsigned int | |
4175 | gpr_write_mask (const struct mips_cl_insn *ip) | |
4176 | { | |
4177 | unsigned long pinfo, pinfo2; | |
4178 | unsigned int mask; | |
4179 | ||
fc76e730 | 4180 | mask = insn_reg_mask (ip, 1 << OP_REG_GP, insn_write_mask (ip->insn_mo)); |
4c260379 RS |
4181 | pinfo = ip->insn_mo->pinfo; |
4182 | pinfo2 = ip->insn_mo->pinfo2; | |
fc76e730 RS |
4183 | if (pinfo & INSN_WRITE_GPR_24) |
4184 | mask |= 1 << 24; | |
4185 | if (pinfo & INSN_WRITE_GPR_31) | |
4186 | mask |= 1 << 31; | |
4187 | if (pinfo & INSN_UDI) | |
4188 | /* UDI instructions have traditionally been assumed to write to RD. */ | |
4189 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RD, *ip); | |
4190 | if (pinfo2 & INSN2_WRITE_SP) | |
4191 | mask |= 1 << SP; | |
fe35f09f RS |
4192 | /* Don't include register 0. */ |
4193 | return mask & ~1; | |
4c260379 RS |
4194 | } |
4195 | ||
4196 | /* Return the mask of floating-point registers that IP reads. */ | |
4197 | ||
4198 | static unsigned int | |
4199 | fpr_read_mask (const struct mips_cl_insn *ip) | |
4200 | { | |
fc76e730 | 4201 | unsigned long pinfo; |
4c260379 RS |
4202 | unsigned int mask; |
4203 | ||
9d5de888 CF |
4204 | mask = insn_reg_mask (ip, ((1 << OP_REG_FP) | (1 << OP_REG_VEC) |
4205 | | (1 << OP_REG_MSA)), | |
fc76e730 | 4206 | insn_read_mask (ip->insn_mo)); |
4c260379 | 4207 | pinfo = ip->insn_mo->pinfo; |
4c260379 RS |
4208 | /* Conservatively treat all operands to an FP_D instruction are doubles. |
4209 | (This is overly pessimistic for things like cvt.d.s.) */ | |
bad1aba3 | 4210 | if (FPR_SIZE != 64 && (pinfo & FP_D)) |
4c260379 RS |
4211 | mask |= mask << 1; |
4212 | return mask; | |
4213 | } | |
4214 | ||
4215 | /* Return the mask of floating-point registers that IP writes. */ | |
4216 | ||
4217 | static unsigned int | |
4218 | fpr_write_mask (const struct mips_cl_insn *ip) | |
4219 | { | |
fc76e730 | 4220 | unsigned long pinfo; |
4c260379 RS |
4221 | unsigned int mask; |
4222 | ||
9d5de888 CF |
4223 | mask = insn_reg_mask (ip, ((1 << OP_REG_FP) | (1 << OP_REG_VEC) |
4224 | | (1 << OP_REG_MSA)), | |
fc76e730 | 4225 | insn_write_mask (ip->insn_mo)); |
4c260379 | 4226 | pinfo = ip->insn_mo->pinfo; |
4c260379 RS |
4227 | /* Conservatively treat all operands to an FP_D instruction are doubles. |
4228 | (This is overly pessimistic for things like cvt.s.d.) */ | |
bad1aba3 | 4229 | if (FPR_SIZE != 64 && (pinfo & FP_D)) |
4c260379 RS |
4230 | mask |= mask << 1; |
4231 | return mask; | |
4232 | } | |
4233 | ||
a1d78564 RS |
4234 | /* Operand OPNUM of INSN is an odd-numbered floating-point register. |
4235 | Check whether that is allowed. */ | |
4236 | ||
4237 | static bfd_boolean | |
4238 | mips_oddfpreg_ok (const struct mips_opcode *insn, int opnum) | |
4239 | { | |
4240 | const char *s = insn->name; | |
4241 | ||
4242 | if (insn->pinfo == INSN_MACRO) | |
4243 | /* Let a macro pass, we'll catch it later when it is expanded. */ | |
4244 | return TRUE; | |
4245 | ||
4246 | if (ISA_HAS_ODD_SINGLE_FPR (mips_opts.isa) || mips_opts.arch == CPU_R5900) | |
4247 | { | |
4248 | /* Allow odd registers for single-precision ops. */ | |
4249 | switch (insn->pinfo & (FP_S | FP_D)) | |
4250 | { | |
4251 | case FP_S: | |
4252 | case 0: | |
4253 | return TRUE; | |
4254 | case FP_D: | |
4255 | return FALSE; | |
4256 | default: | |
4257 | break; | |
4258 | } | |
4259 | ||
4260 | /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */ | |
4261 | s = strchr (insn->name, '.'); | |
4262 | if (s != NULL && opnum == 2) | |
4263 | s = strchr (s + 1, '.'); | |
4264 | return (s != NULL && (s[1] == 'w' || s[1] == 's')); | |
4265 | } | |
4266 | ||
4267 | /* Single-precision coprocessor loads and moves are OK too. */ | |
4268 | if ((insn->pinfo & FP_S) | |
4269 | && (insn->pinfo & (INSN_COPROC_MEMORY_DELAY | INSN_STORE_MEMORY | |
4270 | | INSN_LOAD_COPROC_DELAY | INSN_COPROC_MOVE_DELAY))) | |
4271 | return TRUE; | |
4272 | ||
4273 | return FALSE; | |
4274 | } | |
4275 | ||
a1d78564 RS |
4276 | /* Information about an instruction argument that we're trying to match. */ |
4277 | struct mips_arg_info | |
4278 | { | |
4279 | /* The instruction so far. */ | |
4280 | struct mips_cl_insn *insn; | |
4281 | ||
a92713e6 RS |
4282 | /* The first unconsumed operand token. */ |
4283 | struct mips_operand_token *token; | |
4284 | ||
a1d78564 RS |
4285 | /* The 1-based operand number, in terms of insn->insn_mo->args. */ |
4286 | int opnum; | |
4287 | ||
4288 | /* The 1-based argument number, for error reporting. This does not | |
4289 | count elided optional registers, etc.. */ | |
4290 | int argnum; | |
4291 | ||
4292 | /* The last OP_REG operand seen, or ILLEGAL_REG if none. */ | |
4293 | unsigned int last_regno; | |
4294 | ||
4295 | /* If the first operand was an OP_REG, this is the register that it | |
4296 | specified, otherwise it is ILLEGAL_REG. */ | |
4297 | unsigned int dest_regno; | |
4298 | ||
4299 | /* The value of the last OP_INT operand. Only used for OP_MSB, | |
4300 | where it gives the lsb position. */ | |
4301 | unsigned int last_op_int; | |
4302 | ||
60f20e8b RS |
4303 | /* If true, match routines should assume that no later instruction |
4304 | alternative matches and should therefore be as accomodating as | |
4305 | possible. Match routines should not report errors if something | |
4306 | is only invalid for !LAX_MATCH. */ | |
4307 | bfd_boolean lax_match; | |
a1d78564 | 4308 | |
a1d78564 RS |
4309 | /* True if a reference to the current AT register was seen. */ |
4310 | bfd_boolean seen_at; | |
4311 | }; | |
4312 | ||
1a00e612 RS |
4313 | /* Record that the argument is out of range. */ |
4314 | ||
4315 | static void | |
4316 | match_out_of_range (struct mips_arg_info *arg) | |
4317 | { | |
4318 | set_insn_error_i (arg->argnum, _("operand %d out of range"), arg->argnum); | |
4319 | } | |
4320 | ||
4321 | /* Record that the argument isn't constant but needs to be. */ | |
4322 | ||
4323 | static void | |
4324 | match_not_constant (struct mips_arg_info *arg) | |
4325 | { | |
4326 | set_insn_error_i (arg->argnum, _("operand %d must be constant"), | |
4327 | arg->argnum); | |
4328 | } | |
4329 | ||
a92713e6 RS |
4330 | /* Try to match an OT_CHAR token for character CH. Consume the token |
4331 | and return true on success, otherwise return false. */ | |
a1d78564 | 4332 | |
a92713e6 RS |
4333 | static bfd_boolean |
4334 | match_char (struct mips_arg_info *arg, char ch) | |
a1d78564 | 4335 | { |
a92713e6 RS |
4336 | if (arg->token->type == OT_CHAR && arg->token->u.ch == ch) |
4337 | { | |
4338 | ++arg->token; | |
4339 | if (ch == ',') | |
4340 | arg->argnum += 1; | |
4341 | return TRUE; | |
4342 | } | |
4343 | return FALSE; | |
4344 | } | |
a1d78564 | 4345 | |
a92713e6 RS |
4346 | /* Try to get an expression from the next tokens in ARG. Consume the |
4347 | tokens and return true on success, storing the expression value in | |
4348 | VALUE and relocation types in R. */ | |
4349 | ||
4350 | static bfd_boolean | |
4351 | match_expression (struct mips_arg_info *arg, expressionS *value, | |
4352 | bfd_reloc_code_real_type *r) | |
4353 | { | |
d436c1c2 RS |
4354 | /* If the next token is a '(' that was parsed as being part of a base |
4355 | expression, assume we have an elided offset. The later match will fail | |
4356 | if this turns out to be wrong. */ | |
4357 | if (arg->token->type == OT_CHAR && arg->token->u.ch == '(') | |
a1d78564 | 4358 | { |
d436c1c2 RS |
4359 | value->X_op = O_constant; |
4360 | value->X_add_number = 0; | |
4361 | r[0] = r[1] = r[2] = BFD_RELOC_UNUSED; | |
a92713e6 RS |
4362 | return TRUE; |
4363 | } | |
4364 | ||
d436c1c2 RS |
4365 | /* Reject register-based expressions such as "0+$2" and "(($2))". |
4366 | For plain registers the default error seems more appropriate. */ | |
4367 | if (arg->token->type == OT_INTEGER | |
4368 | && arg->token->u.integer.value.X_op == O_register) | |
a92713e6 | 4369 | { |
d436c1c2 RS |
4370 | set_insn_error (arg->argnum, _("register value used as expression")); |
4371 | return FALSE; | |
a1d78564 | 4372 | } |
d436c1c2 RS |
4373 | |
4374 | if (arg->token->type == OT_INTEGER) | |
a92713e6 | 4375 | { |
d436c1c2 RS |
4376 | *value = arg->token->u.integer.value; |
4377 | memcpy (r, arg->token->u.integer.relocs, 3 * sizeof (*r)); | |
4378 | ++arg->token; | |
4379 | return TRUE; | |
a92713e6 | 4380 | } |
a92713e6 | 4381 | |
d436c1c2 RS |
4382 | set_insn_error_i |
4383 | (arg->argnum, _("operand %d must be an immediate expression"), | |
4384 | arg->argnum); | |
4385 | return FALSE; | |
a92713e6 RS |
4386 | } |
4387 | ||
4388 | /* Try to get a constant expression from the next tokens in ARG. Consume | |
4389 | the tokens and return return true on success, storing the constant value | |
4390 | in *VALUE. Use FALLBACK as the value if the match succeeded with an | |
4391 | error. */ | |
4392 | ||
4393 | static bfd_boolean | |
1a00e612 | 4394 | match_const_int (struct mips_arg_info *arg, offsetT *value) |
a92713e6 RS |
4395 | { |
4396 | expressionS ex; | |
4397 | bfd_reloc_code_real_type r[3]; | |
a1d78564 | 4398 | |
a92713e6 RS |
4399 | if (!match_expression (arg, &ex, r)) |
4400 | return FALSE; | |
4401 | ||
4402 | if (r[0] == BFD_RELOC_UNUSED && ex.X_op == O_constant) | |
a1d78564 RS |
4403 | *value = ex.X_add_number; |
4404 | else | |
4405 | { | |
1a00e612 RS |
4406 | match_not_constant (arg); |
4407 | return FALSE; | |
a1d78564 | 4408 | } |
a92713e6 | 4409 | return TRUE; |
a1d78564 RS |
4410 | } |
4411 | ||
4412 | /* Return the RTYPE_* flags for a register operand of type TYPE that | |
4413 | appears in instruction OPCODE. */ | |
4414 | ||
4415 | static unsigned int | |
4416 | convert_reg_type (const struct mips_opcode *opcode, | |
4417 | enum mips_reg_operand_type type) | |
4418 | { | |
4419 | switch (type) | |
4420 | { | |
4421 | case OP_REG_GP: | |
4422 | return RTYPE_NUM | RTYPE_GP; | |
4423 | ||
4424 | case OP_REG_FP: | |
4425 | /* Allow vector register names for MDMX if the instruction is a 64-bit | |
4426 | FPR load, store or move (including moves to and from GPRs). */ | |
4427 | if ((mips_opts.ase & ASE_MDMX) | |
4428 | && (opcode->pinfo & FP_D) | |
4429 | && (opcode->pinfo & (INSN_COPROC_MOVE_DELAY | |
4430 | | INSN_COPROC_MEMORY_DELAY | |
4431 | | INSN_LOAD_COPROC_DELAY | |
67dc82bc | 4432 | | INSN_LOAD_MEMORY |
a1d78564 RS |
4433 | | INSN_STORE_MEMORY))) |
4434 | return RTYPE_FPU | RTYPE_VEC; | |
4435 | return RTYPE_FPU; | |
4436 | ||
4437 | case OP_REG_CCC: | |
4438 | if (opcode->pinfo & (FP_D | FP_S)) | |
4439 | return RTYPE_CCC | RTYPE_FCC; | |
4440 | return RTYPE_CCC; | |
4441 | ||
4442 | case OP_REG_VEC: | |
4443 | if (opcode->membership & INSN_5400) | |
4444 | return RTYPE_FPU; | |
4445 | return RTYPE_FPU | RTYPE_VEC; | |
4446 | ||
4447 | case OP_REG_ACC: | |
4448 | return RTYPE_ACC; | |
4449 | ||
4450 | case OP_REG_COPRO: | |
4451 | if (opcode->name[strlen (opcode->name) - 1] == '0') | |
4452 | return RTYPE_NUM | RTYPE_CP0; | |
4453 | return RTYPE_NUM; | |
4454 | ||
4455 | case OP_REG_HW: | |
4456 | return RTYPE_NUM; | |
14daeee3 RS |
4457 | |
4458 | case OP_REG_VI: | |
4459 | return RTYPE_NUM | RTYPE_VI; | |
4460 | ||
4461 | case OP_REG_VF: | |
4462 | return RTYPE_NUM | RTYPE_VF; | |
4463 | ||
4464 | case OP_REG_R5900_I: | |
4465 | return RTYPE_R5900_I; | |
4466 | ||
4467 | case OP_REG_R5900_Q: | |
4468 | return RTYPE_R5900_Q; | |
4469 | ||
4470 | case OP_REG_R5900_R: | |
4471 | return RTYPE_R5900_R; | |
4472 | ||
4473 | case OP_REG_R5900_ACC: | |
4474 | return RTYPE_R5900_ACC; | |
56d438b1 CF |
4475 | |
4476 | case OP_REG_MSA: | |
4477 | return RTYPE_MSA; | |
4478 | ||
4479 | case OP_REG_MSA_CTRL: | |
4480 | return RTYPE_NUM; | |
a1d78564 RS |
4481 | } |
4482 | abort (); | |
4483 | } | |
4484 | ||
4485 | /* ARG is register REGNO, of type TYPE. Warn about any dubious registers. */ | |
4486 | ||
4487 | static void | |
4488 | check_regno (struct mips_arg_info *arg, | |
4489 | enum mips_reg_operand_type type, unsigned int regno) | |
4490 | { | |
4491 | if (AT && type == OP_REG_GP && regno == AT) | |
4492 | arg->seen_at = TRUE; | |
4493 | ||
4494 | if (type == OP_REG_FP | |
4495 | && (regno & 1) != 0 | |
bad1aba3 | 4496 | && FPR_SIZE != 64 |
a1d78564 | 4497 | && !mips_oddfpreg_ok (arg->insn->insn_mo, arg->opnum)) |
1661c76c | 4498 | as_warn (_("float register should be even, was %d"), regno); |
a1d78564 RS |
4499 | |
4500 | if (type == OP_REG_CCC) | |
4501 | { | |
4502 | const char *name; | |
4503 | size_t length; | |
4504 | ||
4505 | name = arg->insn->insn_mo->name; | |
4506 | length = strlen (name); | |
4507 | if ((regno & 1) != 0 | |
4508 | && ((length >= 3 && strcmp (name + length - 3, ".ps") == 0) | |
4509 | || (length >= 5 && strncmp (name + length - 5, "any2", 4) == 0))) | |
1661c76c | 4510 | as_warn (_("condition code register should be even for %s, was %d"), |
a1d78564 RS |
4511 | name, regno); |
4512 | ||
4513 | if ((regno & 3) != 0 | |
4514 | && (length >= 5 && strncmp (name + length - 5, "any4", 4) == 0)) | |
1661c76c | 4515 | as_warn (_("condition code register should be 0 or 4 for %s, was %d"), |
a1d78564 RS |
4516 | name, regno); |
4517 | } | |
4518 | } | |
4519 | ||
a92713e6 RS |
4520 | /* ARG is a register with symbol value SYMVAL. Try to interpret it as |
4521 | a register of type TYPE. Return true on success, storing the register | |
4522 | number in *REGNO and warning about any dubious uses. */ | |
4523 | ||
4524 | static bfd_boolean | |
4525 | match_regno (struct mips_arg_info *arg, enum mips_reg_operand_type type, | |
4526 | unsigned int symval, unsigned int *regno) | |
4527 | { | |
4528 | if (type == OP_REG_VEC) | |
4529 | symval = mips_prefer_vec_regno (symval); | |
4530 | if (!(symval & convert_reg_type (arg->insn->insn_mo, type))) | |
4531 | return FALSE; | |
4532 | ||
4533 | *regno = symval & RNUM_MASK; | |
4534 | check_regno (arg, type, *regno); | |
4535 | return TRUE; | |
4536 | } | |
4537 | ||
4538 | /* Try to interpret the next token in ARG as a register of type TYPE. | |
4539 | Consume the token and return true on success, storing the register | |
4540 | number in *REGNO. Return false on failure. */ | |
4541 | ||
4542 | static bfd_boolean | |
4543 | match_reg (struct mips_arg_info *arg, enum mips_reg_operand_type type, | |
4544 | unsigned int *regno) | |
4545 | { | |
4546 | if (arg->token->type == OT_REG | |
4547 | && match_regno (arg, type, arg->token->u.regno, regno)) | |
4548 | { | |
4549 | ++arg->token; | |
4550 | return TRUE; | |
4551 | } | |
4552 | return FALSE; | |
4553 | } | |
4554 | ||
4555 | /* Try to interpret the next token in ARG as a range of registers of type TYPE. | |
4556 | Consume the token and return true on success, storing the register numbers | |
4557 | in *REGNO1 and *REGNO2. Return false on failure. */ | |
4558 | ||
4559 | static bfd_boolean | |
4560 | match_reg_range (struct mips_arg_info *arg, enum mips_reg_operand_type type, | |
4561 | unsigned int *regno1, unsigned int *regno2) | |
4562 | { | |
4563 | if (match_reg (arg, type, regno1)) | |
4564 | { | |
4565 | *regno2 = *regno1; | |
4566 | return TRUE; | |
4567 | } | |
4568 | if (arg->token->type == OT_REG_RANGE | |
4569 | && match_regno (arg, type, arg->token->u.reg_range.regno1, regno1) | |
4570 | && match_regno (arg, type, arg->token->u.reg_range.regno2, regno2) | |
4571 | && *regno1 <= *regno2) | |
4572 | { | |
4573 | ++arg->token; | |
4574 | return TRUE; | |
4575 | } | |
4576 | return FALSE; | |
4577 | } | |
4578 | ||
a1d78564 RS |
4579 | /* OP_INT matcher. */ |
4580 | ||
a92713e6 | 4581 | static bfd_boolean |
a1d78564 | 4582 | match_int_operand (struct mips_arg_info *arg, |
a92713e6 | 4583 | const struct mips_operand *operand_base) |
a1d78564 RS |
4584 | { |
4585 | const struct mips_int_operand *operand; | |
3ccad066 | 4586 | unsigned int uval; |
a1d78564 RS |
4587 | int min_val, max_val, factor; |
4588 | offsetT sval; | |
a1d78564 RS |
4589 | |
4590 | operand = (const struct mips_int_operand *) operand_base; | |
4591 | factor = 1 << operand->shift; | |
3ccad066 RS |
4592 | min_val = mips_int_operand_min (operand); |
4593 | max_val = mips_int_operand_max (operand); | |
a1d78564 | 4594 | |
d436c1c2 RS |
4595 | if (operand_base->lsb == 0 |
4596 | && operand_base->size == 16 | |
4597 | && operand->shift == 0 | |
4598 | && operand->bias == 0 | |
4599 | && (operand->max_val == 32767 || operand->max_val == 65535)) | |
a1d78564 RS |
4600 | { |
4601 | /* The operand can be relocated. */ | |
a92713e6 RS |
4602 | if (!match_expression (arg, &offset_expr, offset_reloc)) |
4603 | return FALSE; | |
4604 | ||
4605 | if (offset_reloc[0] != BFD_RELOC_UNUSED) | |
a1d78564 RS |
4606 | /* Relocation operators were used. Accept the arguent and |
4607 | leave the relocation value in offset_expr and offset_relocs | |
4608 | for the caller to process. */ | |
a92713e6 RS |
4609 | return TRUE; |
4610 | ||
4611 | if (offset_expr.X_op != O_constant) | |
a1d78564 | 4612 | { |
60f20e8b RS |
4613 | /* Accept non-constant operands if no later alternative matches, |
4614 | leaving it for the caller to process. */ | |
4615 | if (!arg->lax_match) | |
4616 | return FALSE; | |
a92713e6 RS |
4617 | offset_reloc[0] = BFD_RELOC_LO16; |
4618 | return TRUE; | |
a1d78564 | 4619 | } |
a92713e6 | 4620 | |
a1d78564 RS |
4621 | /* Clear the global state; we're going to install the operand |
4622 | ourselves. */ | |
a92713e6 | 4623 | sval = offset_expr.X_add_number; |
a1d78564 | 4624 | offset_expr.X_op = O_absent; |
60f20e8b RS |
4625 | |
4626 | /* For compatibility with older assemblers, we accept | |
4627 | 0x8000-0xffff as signed 16-bit numbers when only | |
4628 | signed numbers are allowed. */ | |
4629 | if (sval > max_val) | |
4630 | { | |
4631 | max_val = ((1 << operand_base->size) - 1) << operand->shift; | |
4632 | if (!arg->lax_match && sval <= max_val) | |
4633 | return FALSE; | |
4634 | } | |
a1d78564 RS |
4635 | } |
4636 | else | |
4637 | { | |
1a00e612 | 4638 | if (!match_const_int (arg, &sval)) |
a92713e6 | 4639 | return FALSE; |
a1d78564 RS |
4640 | } |
4641 | ||
4642 | arg->last_op_int = sval; | |
4643 | ||
1a00e612 | 4644 | if (sval < min_val || sval > max_val || sval % factor) |
a1d78564 | 4645 | { |
1a00e612 RS |
4646 | match_out_of_range (arg); |
4647 | return FALSE; | |
a1d78564 RS |
4648 | } |
4649 | ||
4650 | uval = (unsigned int) sval >> operand->shift; | |
4651 | uval -= operand->bias; | |
4652 | ||
4653 | /* Handle -mfix-cn63xxp1. */ | |
4654 | if (arg->opnum == 1 | |
4655 | && mips_fix_cn63xxp1 | |
4656 | && !mips_opts.micromips | |
4657 | && strcmp ("pref", arg->insn->insn_mo->name) == 0) | |
4658 | switch (uval) | |
4659 | { | |
4660 | case 5: | |
4661 | case 25: | |
4662 | case 26: | |
4663 | case 27: | |
4664 | case 28: | |
4665 | case 29: | |
4666 | case 30: | |
4667 | case 31: | |
4668 | /* These are ok. */ | |
4669 | break; | |
4670 | ||
4671 | default: | |
4672 | /* The rest must be changed to 28. */ | |
4673 | uval = 28; | |
4674 | break; | |
4675 | } | |
4676 | ||
4677 | insn_insert_operand (arg->insn, operand_base, uval); | |
a92713e6 | 4678 | return TRUE; |
a1d78564 RS |
4679 | } |
4680 | ||
4681 | /* OP_MAPPED_INT matcher. */ | |
4682 | ||
a92713e6 | 4683 | static bfd_boolean |
a1d78564 | 4684 | match_mapped_int_operand (struct mips_arg_info *arg, |
a92713e6 | 4685 | const struct mips_operand *operand_base) |
a1d78564 RS |
4686 | { |
4687 | const struct mips_mapped_int_operand *operand; | |
4688 | unsigned int uval, num_vals; | |
4689 | offsetT sval; | |
4690 | ||
4691 | operand = (const struct mips_mapped_int_operand *) operand_base; | |
1a00e612 | 4692 | if (!match_const_int (arg, &sval)) |
a92713e6 | 4693 | return FALSE; |
a1d78564 RS |
4694 | |
4695 | num_vals = 1 << operand_base->size; | |
4696 | for (uval = 0; uval < num_vals; uval++) | |
4697 | if (operand->int_map[uval] == sval) | |
4698 | break; | |
4699 | if (uval == num_vals) | |
1a00e612 RS |
4700 | { |
4701 | match_out_of_range (arg); | |
4702 | return FALSE; | |
4703 | } | |
a1d78564 RS |
4704 | |
4705 | insn_insert_operand (arg->insn, operand_base, uval); | |
a92713e6 | 4706 | return TRUE; |
a1d78564 RS |
4707 | } |
4708 | ||
4709 | /* OP_MSB matcher. */ | |
4710 | ||
a92713e6 | 4711 | static bfd_boolean |
a1d78564 | 4712 | match_msb_operand (struct mips_arg_info *arg, |
a92713e6 | 4713 | const struct mips_operand *operand_base) |
a1d78564 RS |
4714 | { |
4715 | const struct mips_msb_operand *operand; | |
4716 | int min_val, max_val, max_high; | |
4717 | offsetT size, sval, high; | |
4718 | ||
4719 | operand = (const struct mips_msb_operand *) operand_base; | |
4720 | min_val = operand->bias; | |
4721 | max_val = min_val + (1 << operand_base->size) - 1; | |
4722 | max_high = operand->opsize; | |
4723 | ||
1a00e612 | 4724 | if (!match_const_int (arg, &size)) |
a92713e6 | 4725 | return FALSE; |
a1d78564 RS |
4726 | |
4727 | high = size + arg->last_op_int; | |
4728 | sval = operand->add_lsb ? high : size; | |
4729 | ||
4730 | if (size < 0 || high > max_high || sval < min_val || sval > max_val) | |
4731 | { | |
1a00e612 RS |
4732 | match_out_of_range (arg); |
4733 | return FALSE; | |
a1d78564 RS |
4734 | } |
4735 | insn_insert_operand (arg->insn, operand_base, sval - min_val); | |
a92713e6 | 4736 | return TRUE; |
a1d78564 RS |
4737 | } |
4738 | ||
4739 | /* OP_REG matcher. */ | |
4740 | ||
a92713e6 | 4741 | static bfd_boolean |
a1d78564 | 4742 | match_reg_operand (struct mips_arg_info *arg, |
a92713e6 | 4743 | const struct mips_operand *operand_base) |
a1d78564 RS |
4744 | { |
4745 | const struct mips_reg_operand *operand; | |
a92713e6 | 4746 | unsigned int regno, uval, num_vals; |
a1d78564 RS |
4747 | |
4748 | operand = (const struct mips_reg_operand *) operand_base; | |
a92713e6 RS |
4749 | if (!match_reg (arg, operand->reg_type, ®no)) |
4750 | return FALSE; | |
a1d78564 RS |
4751 | |
4752 | if (operand->reg_map) | |
4753 | { | |
4754 | num_vals = 1 << operand->root.size; | |
4755 | for (uval = 0; uval < num_vals; uval++) | |
4756 | if (operand->reg_map[uval] == regno) | |
4757 | break; | |
4758 | if (num_vals == uval) | |
a92713e6 | 4759 | return FALSE; |
a1d78564 RS |
4760 | } |
4761 | else | |
4762 | uval = regno; | |
4763 | ||
a1d78564 RS |
4764 | arg->last_regno = regno; |
4765 | if (arg->opnum == 1) | |
4766 | arg->dest_regno = regno; | |
4767 | insn_insert_operand (arg->insn, operand_base, uval); | |
a92713e6 | 4768 | return TRUE; |
a1d78564 RS |
4769 | } |
4770 | ||
4771 | /* OP_REG_PAIR matcher. */ | |
4772 | ||
a92713e6 | 4773 | static bfd_boolean |
a1d78564 | 4774 | match_reg_pair_operand (struct mips_arg_info *arg, |
a92713e6 | 4775 | const struct mips_operand *operand_base) |
a1d78564 RS |
4776 | { |
4777 | const struct mips_reg_pair_operand *operand; | |
a92713e6 | 4778 | unsigned int regno1, regno2, uval, num_vals; |
a1d78564 RS |
4779 | |
4780 | operand = (const struct mips_reg_pair_operand *) operand_base; | |
a92713e6 RS |
4781 | if (!match_reg (arg, operand->reg_type, ®no1) |
4782 | || !match_char (arg, ',') | |
4783 | || !match_reg (arg, operand->reg_type, ®no2)) | |
4784 | return FALSE; | |
a1d78564 RS |
4785 | |
4786 | num_vals = 1 << operand_base->size; | |
4787 | for (uval = 0; uval < num_vals; uval++) | |
4788 | if (operand->reg1_map[uval] == regno1 && operand->reg2_map[uval] == regno2) | |
4789 | break; | |
4790 | if (uval == num_vals) | |
a92713e6 | 4791 | return FALSE; |
a1d78564 | 4792 | |
a1d78564 | 4793 | insn_insert_operand (arg->insn, operand_base, uval); |
a92713e6 | 4794 | return TRUE; |
a1d78564 RS |
4795 | } |
4796 | ||
4797 | /* OP_PCREL matcher. The caller chooses the relocation type. */ | |
4798 | ||
a92713e6 RS |
4799 | static bfd_boolean |
4800 | match_pcrel_operand (struct mips_arg_info *arg) | |
a1d78564 | 4801 | { |
a92713e6 RS |
4802 | bfd_reloc_code_real_type r[3]; |
4803 | ||
4804 | return match_expression (arg, &offset_expr, r) && r[0] == BFD_RELOC_UNUSED; | |
a1d78564 RS |
4805 | } |
4806 | ||
4807 | /* OP_PERF_REG matcher. */ | |
4808 | ||
a92713e6 | 4809 | static bfd_boolean |
a1d78564 | 4810 | match_perf_reg_operand (struct mips_arg_info *arg, |
a92713e6 | 4811 | const struct mips_operand *operand) |
a1d78564 RS |
4812 | { |
4813 | offsetT sval; | |
4814 | ||
1a00e612 | 4815 | if (!match_const_int (arg, &sval)) |
a92713e6 | 4816 | return FALSE; |
a1d78564 RS |
4817 | |
4818 | if (sval != 0 | |
4819 | && (sval != 1 | |
4820 | || (mips_opts.arch == CPU_R5900 | |
4821 | && (strcmp (arg->insn->insn_mo->name, "mfps") == 0 | |
4822 | || strcmp (arg->insn->insn_mo->name, "mtps") == 0)))) | |
4823 | { | |
1a00e612 RS |
4824 | set_insn_error (arg->argnum, _("invalid performance register")); |
4825 | return FALSE; | |
a1d78564 RS |
4826 | } |
4827 | ||
4828 | insn_insert_operand (arg->insn, operand, sval); | |
a92713e6 | 4829 | return TRUE; |
a1d78564 RS |
4830 | } |
4831 | ||
4832 | /* OP_ADDIUSP matcher. */ | |
4833 | ||
a92713e6 | 4834 | static bfd_boolean |
a1d78564 | 4835 | match_addiusp_operand (struct mips_arg_info *arg, |
a92713e6 | 4836 | const struct mips_operand *operand) |
a1d78564 RS |
4837 | { |
4838 | offsetT sval; | |
4839 | unsigned int uval; | |
4840 | ||
1a00e612 | 4841 | if (!match_const_int (arg, &sval)) |
a92713e6 | 4842 | return FALSE; |
a1d78564 RS |
4843 | |
4844 | if (sval % 4) | |
1a00e612 RS |
4845 | { |
4846 | match_out_of_range (arg); | |
4847 | return FALSE; | |
4848 | } | |
a1d78564 RS |
4849 | |
4850 | sval /= 4; | |
4851 | if (!(sval >= -258 && sval <= 257) || (sval >= -2 && sval <= 1)) | |
1a00e612 RS |
4852 | { |
4853 | match_out_of_range (arg); | |
4854 | return FALSE; | |
4855 | } | |
a1d78564 RS |
4856 | |
4857 | uval = (unsigned int) sval; | |
4858 | uval = ((uval >> 1) & ~0xff) | (uval & 0xff); | |
4859 | insn_insert_operand (arg->insn, operand, uval); | |
a92713e6 | 4860 | return TRUE; |
a1d78564 RS |
4861 | } |
4862 | ||
4863 | /* OP_CLO_CLZ_DEST matcher. */ | |
4864 | ||
a92713e6 | 4865 | static bfd_boolean |
a1d78564 | 4866 | match_clo_clz_dest_operand (struct mips_arg_info *arg, |
a92713e6 | 4867 | const struct mips_operand *operand) |
a1d78564 RS |
4868 | { |
4869 | unsigned int regno; | |
4870 | ||
a92713e6 RS |
4871 | if (!match_reg (arg, OP_REG_GP, ®no)) |
4872 | return FALSE; | |
a1d78564 | 4873 | |
a1d78564 | 4874 | insn_insert_operand (arg->insn, operand, regno | (regno << 5)); |
a92713e6 | 4875 | return TRUE; |
a1d78564 RS |
4876 | } |
4877 | ||
4878 | /* OP_LWM_SWM_LIST matcher. */ | |
4879 | ||
a92713e6 | 4880 | static bfd_boolean |
a1d78564 | 4881 | match_lwm_swm_list_operand (struct mips_arg_info *arg, |
a92713e6 | 4882 | const struct mips_operand *operand) |
a1d78564 | 4883 | { |
a92713e6 RS |
4884 | unsigned int reglist, sregs, ra, regno1, regno2; |
4885 | struct mips_arg_info reset; | |
a1d78564 | 4886 | |
a92713e6 RS |
4887 | reglist = 0; |
4888 | if (!match_reg_range (arg, OP_REG_GP, ®no1, ®no2)) | |
4889 | return FALSE; | |
4890 | do | |
4891 | { | |
4892 | if (regno2 == FP && regno1 >= S0 && regno1 <= S7) | |
4893 | { | |
4894 | reglist |= 1 << FP; | |
4895 | regno2 = S7; | |
4896 | } | |
4897 | reglist |= ((1U << regno2 << 1) - 1) & -(1U << regno1); | |
4898 | reset = *arg; | |
4899 | } | |
4900 | while (match_char (arg, ',') | |
4901 | && match_reg_range (arg, OP_REG_GP, ®no1, ®no2)); | |
4902 | *arg = reset; | |
a1d78564 RS |
4903 | |
4904 | if (operand->size == 2) | |
4905 | { | |
4906 | /* The list must include both ra and s0-sN, for 0 <= N <= 3. E.g.: | |
4907 | ||
4908 | s0, ra | |
4909 | s0, s1, ra, s2, s3 | |
4910 | s0-s2, ra | |
4911 | ||
4912 | and any permutations of these. */ | |
4913 | if ((reglist & 0xfff1ffff) != 0x80010000) | |
a92713e6 | 4914 | return FALSE; |
a1d78564 RS |
4915 | |
4916 | sregs = (reglist >> 17) & 7; | |
4917 | ra = 0; | |
4918 | } | |
4919 | else | |
4920 | { | |
4921 | /* The list must include at least one of ra and s0-sN, | |
4922 | for 0 <= N <= 8. (Note that there is a gap between s7 and s8, | |
4923 | which are $23 and $30 respectively.) E.g.: | |
4924 | ||
4925 | ra | |
4926 | s0 | |
4927 | ra, s0, s1, s2 | |
4928 | s0-s8 | |
4929 | s0-s5, ra | |
4930 | ||
4931 | and any permutations of these. */ | |
4932 | if ((reglist & 0x3f00ffff) != 0) | |
a92713e6 | 4933 | return FALSE; |
a1d78564 RS |
4934 | |
4935 | ra = (reglist >> 27) & 0x10; | |
4936 | sregs = ((reglist >> 22) & 0x100) | ((reglist >> 16) & 0xff); | |
4937 | } | |
4938 | sregs += 1; | |
4939 | if ((sregs & -sregs) != sregs) | |
a92713e6 | 4940 | return FALSE; |
a1d78564 RS |
4941 | |
4942 | insn_insert_operand (arg->insn, operand, (ffs (sregs) - 1) | ra); | |
a92713e6 | 4943 | return TRUE; |
a1d78564 RS |
4944 | } |
4945 | ||
364215c8 RS |
4946 | /* OP_ENTRY_EXIT_LIST matcher. */ |
4947 | ||
a92713e6 | 4948 | static unsigned int |
364215c8 | 4949 | match_entry_exit_operand (struct mips_arg_info *arg, |
a92713e6 | 4950 | const struct mips_operand *operand) |
364215c8 RS |
4951 | { |
4952 | unsigned int mask; | |
4953 | bfd_boolean is_exit; | |
4954 | ||
4955 | /* The format is the same for both ENTRY and EXIT, but the constraints | |
4956 | are different. */ | |
4957 | is_exit = strcmp (arg->insn->insn_mo->name, "exit") == 0; | |
4958 | mask = (is_exit ? 7 << 3 : 0); | |
a92713e6 | 4959 | do |
364215c8 RS |
4960 | { |
4961 | unsigned int regno1, regno2; | |
4962 | bfd_boolean is_freg; | |
4963 | ||
a92713e6 | 4964 | if (match_reg_range (arg, OP_REG_GP, ®no1, ®no2)) |
364215c8 | 4965 | is_freg = FALSE; |
a92713e6 | 4966 | else if (match_reg_range (arg, OP_REG_FP, ®no1, ®no2)) |
364215c8 RS |
4967 | is_freg = TRUE; |
4968 | else | |
a92713e6 | 4969 | return FALSE; |
364215c8 RS |
4970 | |
4971 | if (is_exit && is_freg && regno1 == 0 && regno2 < 2) | |
4972 | { | |
4973 | mask &= ~(7 << 3); | |
4974 | mask |= (5 + regno2) << 3; | |
4975 | } | |
4976 | else if (!is_exit && regno1 == 4 && regno2 >= 4 && regno2 <= 7) | |
4977 | mask |= (regno2 - 3) << 3; | |
4978 | else if (regno1 == 16 && regno2 >= 16 && regno2 <= 17) | |
4979 | mask |= (regno2 - 15) << 1; | |
4980 | else if (regno1 == RA && regno2 == RA) | |
4981 | mask |= 1; | |
4982 | else | |
a92713e6 | 4983 | return FALSE; |
364215c8 | 4984 | } |
a92713e6 RS |
4985 | while (match_char (arg, ',')); |
4986 | ||
364215c8 | 4987 | insn_insert_operand (arg->insn, operand, mask); |
a92713e6 | 4988 | return TRUE; |
364215c8 RS |
4989 | } |
4990 | ||
4991 | /* OP_SAVE_RESTORE_LIST matcher. */ | |
4992 | ||
a92713e6 RS |
4993 | static bfd_boolean |
4994 | match_save_restore_list_operand (struct mips_arg_info *arg) | |
364215c8 RS |
4995 | { |
4996 | unsigned int opcode, args, statics, sregs; | |
4997 | unsigned int num_frame_sizes, num_args, num_statics, num_sregs; | |
364215c8 | 4998 | offsetT frame_size; |
364215c8 | 4999 | |
364215c8 RS |
5000 | opcode = arg->insn->insn_opcode; |
5001 | frame_size = 0; | |
5002 | num_frame_sizes = 0; | |
5003 | args = 0; | |
5004 | statics = 0; | |
5005 | sregs = 0; | |
a92713e6 | 5006 | do |
364215c8 RS |
5007 | { |
5008 | unsigned int regno1, regno2; | |
5009 | ||
a92713e6 | 5010 | if (arg->token->type == OT_INTEGER) |
364215c8 RS |
5011 | { |
5012 | /* Handle the frame size. */ | |
1a00e612 | 5013 | if (!match_const_int (arg, &frame_size)) |
a92713e6 | 5014 | return FALSE; |
364215c8 | 5015 | num_frame_sizes += 1; |
364215c8 RS |
5016 | } |
5017 | else | |
5018 | { | |
a92713e6 RS |
5019 | if (!match_reg_range (arg, OP_REG_GP, ®no1, ®no2)) |
5020 | return FALSE; | |
364215c8 RS |
5021 | |
5022 | while (regno1 <= regno2) | |
5023 | { | |
5024 | if (regno1 >= 4 && regno1 <= 7) | |
5025 | { | |
5026 | if (num_frame_sizes == 0) | |
5027 | /* args $a0-$a3 */ | |
5028 | args |= 1 << (regno1 - 4); | |
5029 | else | |
5030 | /* statics $a0-$a3 */ | |
5031 | statics |= 1 << (regno1 - 4); | |
5032 | } | |
5033 | else if (regno1 >= 16 && regno1 <= 23) | |
5034 | /* $s0-$s7 */ | |
5035 | sregs |= 1 << (regno1 - 16); | |
5036 | else if (regno1 == 30) | |
5037 | /* $s8 */ | |
5038 | sregs |= 1 << 8; | |
5039 | else if (regno1 == 31) | |
5040 | /* Add $ra to insn. */ | |
5041 | opcode |= 0x40; | |
5042 | else | |
a92713e6 | 5043 | return FALSE; |
364215c8 RS |
5044 | regno1 += 1; |
5045 | if (regno1 == 24) | |
5046 | regno1 = 30; | |
5047 | } | |
5048 | } | |
364215c8 | 5049 | } |
a92713e6 | 5050 | while (match_char (arg, ',')); |
364215c8 RS |
5051 | |
5052 | /* Encode args/statics combination. */ | |
5053 | if (args & statics) | |
a92713e6 | 5054 | return FALSE; |
364215c8 RS |
5055 | else if (args == 0xf) |
5056 | /* All $a0-$a3 are args. */ | |
5057 | opcode |= MIPS16_ALL_ARGS << 16; | |
5058 | else if (statics == 0xf) | |
5059 | /* All $a0-$a3 are statics. */ | |
5060 | opcode |= MIPS16_ALL_STATICS << 16; | |
5061 | else | |
5062 | { | |
5063 | /* Count arg registers. */ | |
5064 | num_args = 0; | |
5065 | while (args & 0x1) | |
5066 | { | |
5067 | args >>= 1; | |
5068 | num_args += 1; | |
5069 | } | |
5070 | if (args != 0) | |
a92713e6 | 5071 | return FALSE; |
364215c8 RS |
5072 | |
5073 | /* Count static registers. */ | |
5074 | num_statics = 0; | |
5075 | while (statics & 0x8) | |
5076 | { | |
5077 | statics = (statics << 1) & 0xf; | |
5078 | num_statics += 1; | |
5079 | } | |
5080 | if (statics != 0) | |
a92713e6 | 5081 | return FALSE; |
364215c8 RS |
5082 | |
5083 | /* Encode args/statics. */ | |
5084 | opcode |= ((num_args << 2) | num_statics) << 16; | |
5085 | } | |
5086 | ||
5087 | /* Encode $s0/$s1. */ | |
5088 | if (sregs & (1 << 0)) /* $s0 */ | |
5089 | opcode |= 0x20; | |
5090 | if (sregs & (1 << 1)) /* $s1 */ | |
5091 | opcode |= 0x10; | |
5092 | sregs >>= 2; | |
5093 | ||
5094 | /* Encode $s2-$s8. */ | |
5095 | num_sregs = 0; | |
5096 | while (sregs & 1) | |
5097 | { | |
5098 | sregs >>= 1; | |
5099 | num_sregs += 1; | |
5100 | } | |
5101 | if (sregs != 0) | |
a92713e6 | 5102 | return FALSE; |
364215c8 RS |
5103 | opcode |= num_sregs << 24; |
5104 | ||
5105 | /* Encode frame size. */ | |
5106 | if (num_frame_sizes == 0) | |
1a00e612 RS |
5107 | { |
5108 | set_insn_error (arg->argnum, _("missing frame size")); | |
5109 | return FALSE; | |
5110 | } | |
5111 | if (num_frame_sizes > 1) | |
5112 | { | |
5113 | set_insn_error (arg->argnum, _("frame size specified twice")); | |
5114 | return FALSE; | |
5115 | } | |
5116 | if ((frame_size & 7) != 0 || frame_size < 0 || frame_size > 0xff * 8) | |
5117 | { | |
5118 | set_insn_error (arg->argnum, _("invalid frame size")); | |
5119 | return FALSE; | |
5120 | } | |
5121 | if (frame_size != 128 || (opcode >> 16) != 0) | |
364215c8 RS |
5122 | { |
5123 | frame_size /= 8; | |
5124 | opcode |= (((frame_size & 0xf0) << 16) | |
5125 | | (frame_size & 0x0f)); | |
5126 | } | |
5127 | ||
364215c8 RS |
5128 | /* Finally build the instruction. */ |
5129 | if ((opcode >> 16) != 0 || frame_size == 0) | |
5130 | opcode |= MIPS16_EXTEND; | |
5131 | arg->insn->insn_opcode = opcode; | |
a92713e6 | 5132 | return TRUE; |
364215c8 RS |
5133 | } |
5134 | ||
a1d78564 RS |
5135 | /* OP_MDMX_IMM_REG matcher. */ |
5136 | ||
a92713e6 | 5137 | static bfd_boolean |
a1d78564 | 5138 | match_mdmx_imm_reg_operand (struct mips_arg_info *arg, |
a92713e6 | 5139 | const struct mips_operand *operand) |
a1d78564 | 5140 | { |
a92713e6 | 5141 | unsigned int regno, uval; |
a1d78564 RS |
5142 | bfd_boolean is_qh; |
5143 | const struct mips_opcode *opcode; | |
5144 | ||
5145 | /* The mips_opcode records whether this is an octobyte or quadhalf | |
5146 | instruction. Start out with that bit in place. */ | |
5147 | opcode = arg->insn->insn_mo; | |
5148 | uval = mips_extract_operand (operand, opcode->match); | |
5149 | is_qh = (uval != 0); | |
5150 | ||
56d438b1 | 5151 | if (arg->token->type == OT_REG) |
a1d78564 RS |
5152 | { |
5153 | if ((opcode->membership & INSN_5400) | |
5154 | && strcmp (opcode->name, "rzu.ob") == 0) | |
5155 | { | |
1a00e612 RS |
5156 | set_insn_error_i (arg->argnum, _("operand %d must be an immediate"), |
5157 | arg->argnum); | |
5158 | return FALSE; | |
a1d78564 RS |
5159 | } |
5160 | ||
56d438b1 CF |
5161 | if (!match_regno (arg, OP_REG_VEC, arg->token->u.regno, ®no)) |
5162 | return FALSE; | |
5163 | ++arg->token; | |
5164 | ||
a1d78564 RS |
5165 | /* Check whether this is a vector register or a broadcast of |
5166 | a single element. */ | |
56d438b1 | 5167 | if (arg->token->type == OT_INTEGER_INDEX) |
a1d78564 | 5168 | { |
56d438b1 | 5169 | if (arg->token->u.index > (is_qh ? 3 : 7)) |
a1d78564 | 5170 | { |
1a00e612 RS |
5171 | set_insn_error (arg->argnum, _("invalid element selector")); |
5172 | return FALSE; | |
a1d78564 | 5173 | } |
56d438b1 CF |
5174 | uval |= arg->token->u.index << (is_qh ? 2 : 1) << 5; |
5175 | ++arg->token; | |
a1d78564 RS |
5176 | } |
5177 | else | |
5178 | { | |
5179 | /* A full vector. */ | |
5180 | if ((opcode->membership & INSN_5400) | |
5181 | && (strcmp (opcode->name, "sll.ob") == 0 | |
5182 | || strcmp (opcode->name, "srl.ob") == 0)) | |
5183 | { | |
1a00e612 RS |
5184 | set_insn_error_i (arg->argnum, _("operand %d must be scalar"), |
5185 | arg->argnum); | |
5186 | return FALSE; | |
a1d78564 RS |
5187 | } |
5188 | ||
5189 | if (is_qh) | |
5190 | uval |= MDMX_FMTSEL_VEC_QH << 5; | |
5191 | else | |
5192 | uval |= MDMX_FMTSEL_VEC_OB << 5; | |
5193 | } | |
a1d78564 RS |
5194 | uval |= regno; |
5195 | } | |
5196 | else | |
5197 | { | |
5198 | offsetT sval; | |
5199 | ||
1a00e612 | 5200 | if (!match_const_int (arg, &sval)) |
a92713e6 | 5201 | return FALSE; |
a1d78564 RS |
5202 | if (sval < 0 || sval > 31) |
5203 | { | |
1a00e612 RS |
5204 | match_out_of_range (arg); |
5205 | return FALSE; | |
a1d78564 RS |
5206 | } |
5207 | uval |= (sval & 31); | |
5208 | if (is_qh) | |
5209 | uval |= MDMX_FMTSEL_IMM_QH << 5; | |
5210 | else | |
5211 | uval |= MDMX_FMTSEL_IMM_OB << 5; | |
5212 | } | |
5213 | insn_insert_operand (arg->insn, operand, uval); | |
a92713e6 | 5214 | return TRUE; |
a1d78564 RS |
5215 | } |
5216 | ||
56d438b1 CF |
5217 | /* OP_IMM_INDEX matcher. */ |
5218 | ||
5219 | static bfd_boolean | |
5220 | match_imm_index_operand (struct mips_arg_info *arg, | |
5221 | const struct mips_operand *operand) | |
5222 | { | |
5223 | unsigned int max_val; | |
5224 | ||
5225 | if (arg->token->type != OT_INTEGER_INDEX) | |
5226 | return FALSE; | |
5227 | ||
5228 | max_val = (1 << operand->size) - 1; | |
5229 | if (arg->token->u.index > max_val) | |
5230 | { | |
5231 | match_out_of_range (arg); | |
5232 | return FALSE; | |
5233 | } | |
5234 | insn_insert_operand (arg->insn, operand, arg->token->u.index); | |
5235 | ++arg->token; | |
5236 | return TRUE; | |
5237 | } | |
5238 | ||
5239 | /* OP_REG_INDEX matcher. */ | |
5240 | ||
5241 | static bfd_boolean | |
5242 | match_reg_index_operand (struct mips_arg_info *arg, | |
5243 | const struct mips_operand *operand) | |
5244 | { | |
5245 | unsigned int regno; | |
5246 | ||
5247 | if (arg->token->type != OT_REG_INDEX) | |
5248 | return FALSE; | |
5249 | ||
5250 | if (!match_regno (arg, OP_REG_GP, arg->token->u.regno, ®no)) | |
5251 | return FALSE; | |
5252 | ||
5253 | insn_insert_operand (arg->insn, operand, regno); | |
5254 | ++arg->token; | |
5255 | return TRUE; | |
5256 | } | |
5257 | ||
a1d78564 RS |
5258 | /* OP_PC matcher. */ |
5259 | ||
a92713e6 RS |
5260 | static bfd_boolean |
5261 | match_pc_operand (struct mips_arg_info *arg) | |
a1d78564 | 5262 | { |
a92713e6 RS |
5263 | if (arg->token->type == OT_REG && (arg->token->u.regno & RTYPE_PC)) |
5264 | { | |
5265 | ++arg->token; | |
5266 | return TRUE; | |
5267 | } | |
5268 | return FALSE; | |
a1d78564 RS |
5269 | } |
5270 | ||
5271 | /* OP_REPEAT_DEST_REG and OP_REPEAT_PREV_REG matcher. OTHER_REGNO is the | |
5272 | register that we need to match. */ | |
5273 | ||
a92713e6 RS |
5274 | static bfd_boolean |
5275 | match_tied_reg_operand (struct mips_arg_info *arg, unsigned int other_regno) | |
a1d78564 RS |
5276 | { |
5277 | unsigned int regno; | |
5278 | ||
a92713e6 | 5279 | return match_reg (arg, OP_REG_GP, ®no) && regno == other_regno; |
a1d78564 RS |
5280 | } |
5281 | ||
89565f1b RS |
5282 | /* Read a floating-point constant from S for LI.S or LI.D. LENGTH is |
5283 | the length of the value in bytes (4 for float, 8 for double) and | |
5284 | USING_GPRS says whether the destination is a GPR rather than an FPR. | |
5285 | ||
5286 | Return the constant in IMM and OFFSET as follows: | |
5287 | ||
5288 | - If the constant should be loaded via memory, set IMM to O_absent and | |
5289 | OFFSET to the memory address. | |
5290 | ||
5291 | - Otherwise, if the constant should be loaded into two 32-bit registers, | |
5292 | set IMM to the O_constant to load into the high register and OFFSET | |
5293 | to the corresponding value for the low register. | |
5294 | ||
5295 | - Otherwise, set IMM to the full O_constant and set OFFSET to O_absent. | |
5296 | ||
5297 | These constants only appear as the last operand in an instruction, | |
5298 | and every instruction that accepts them in any variant accepts them | |
5299 | in all variants. This means we don't have to worry about backing out | |
5300 | any changes if the instruction does not match. We just match | |
5301 | unconditionally and report an error if the constant is invalid. */ | |
5302 | ||
a92713e6 RS |
5303 | static bfd_boolean |
5304 | match_float_constant (struct mips_arg_info *arg, expressionS *imm, | |
5305 | expressionS *offset, int length, bfd_boolean using_gprs) | |
89565f1b | 5306 | { |
a92713e6 | 5307 | char *p; |
89565f1b RS |
5308 | segT seg, new_seg; |
5309 | subsegT subseg; | |
5310 | const char *newname; | |
a92713e6 | 5311 | unsigned char *data; |
89565f1b RS |
5312 | |
5313 | /* Where the constant is placed is based on how the MIPS assembler | |
5314 | does things: | |
5315 | ||
5316 | length == 4 && using_gprs -- immediate value only | |
5317 | length == 8 && using_gprs -- .rdata or immediate value | |
5318 | length == 4 && !using_gprs -- .lit4 or immediate value | |
5319 | length == 8 && !using_gprs -- .lit8 or immediate value | |
5320 | ||
5321 | The .lit4 and .lit8 sections are only used if permitted by the | |
5322 | -G argument. */ | |
a92713e6 | 5323 | if (arg->token->type != OT_FLOAT) |
1a00e612 RS |
5324 | { |
5325 | set_insn_error (arg->argnum, _("floating-point expression required")); | |
5326 | return FALSE; | |
5327 | } | |
a92713e6 RS |
5328 | |
5329 | gas_assert (arg->token->u.flt.length == length); | |
5330 | data = arg->token->u.flt.data; | |
5331 | ++arg->token; | |
89565f1b RS |
5332 | |
5333 | /* Handle 32-bit constants for which an immediate value is best. */ | |
5334 | if (length == 4 | |
5335 | && (using_gprs | |
5336 | || g_switch_value < 4 | |
5337 | || (data[0] == 0 && data[1] == 0) | |
5338 | || (data[2] == 0 && data[3] == 0))) | |
5339 | { | |
5340 | imm->X_op = O_constant; | |
5341 | if (!target_big_endian) | |
5342 | imm->X_add_number = bfd_getl32 (data); | |
5343 | else | |
5344 | imm->X_add_number = bfd_getb32 (data); | |
5345 | offset->X_op = O_absent; | |
a92713e6 | 5346 | return TRUE; |
89565f1b RS |
5347 | } |
5348 | ||
5349 | /* Handle 64-bit constants for which an immediate value is best. */ | |
5350 | if (length == 8 | |
5351 | && !mips_disable_float_construction | |
5352 | /* Constants can only be constructed in GPRs and copied | |
5353 | to FPRs if the GPRs are at least as wide as the FPRs. | |
5354 | Force the constant into memory if we are using 64-bit FPRs | |
5355 | but the GPRs are only 32 bits wide. */ | |
5356 | /* ??? No longer true with the addition of MTHC1, but this | |
5357 | is legacy code... */ | |
bad1aba3 | 5358 | && (using_gprs || !(FPR_SIZE == 64 && GPR_SIZE == 32)) |
89565f1b RS |
5359 | && ((data[0] == 0 && data[1] == 0) |
5360 | || (data[2] == 0 && data[3] == 0)) | |
5361 | && ((data[4] == 0 && data[5] == 0) | |
5362 | || (data[6] == 0 && data[7] == 0))) | |
5363 | { | |
5364 | /* The value is simple enough to load with a couple of instructions. | |
5365 | If using 32-bit registers, set IMM to the high order 32 bits and | |
5366 | OFFSET to the low order 32 bits. Otherwise, set IMM to the entire | |
5367 | 64 bit constant. */ | |
bad1aba3 | 5368 | if (using_gprs ? GPR_SIZE == 32 : FPR_SIZE != 64) |
89565f1b RS |
5369 | { |
5370 | imm->X_op = O_constant; | |
5371 | offset->X_op = O_constant; | |
5372 | if (!target_big_endian) | |
5373 | { | |
5374 | imm->X_add_number = bfd_getl32 (data + 4); | |
5375 | offset->X_add_number = bfd_getl32 (data); | |
5376 | } | |
5377 | else | |
5378 | { | |
5379 | imm->X_add_number = bfd_getb32 (data); | |
5380 | offset->X_add_number = bfd_getb32 (data + 4); | |
5381 | } | |
5382 | if (offset->X_add_number == 0) | |
5383 | offset->X_op = O_absent; | |
5384 | } | |
5385 | else | |
5386 | { | |
5387 | imm->X_op = O_constant; | |
5388 | if (!target_big_endian) | |
5389 | imm->X_add_number = bfd_getl64 (data); | |
5390 | else | |
5391 | imm->X_add_number = bfd_getb64 (data); | |
5392 | offset->X_op = O_absent; | |
5393 | } | |
a92713e6 | 5394 | return TRUE; |
89565f1b RS |
5395 | } |
5396 | ||
5397 | /* Switch to the right section. */ | |
5398 | seg = now_seg; | |
5399 | subseg = now_subseg; | |
5400 | if (length == 4) | |
5401 | { | |
5402 | gas_assert (!using_gprs && g_switch_value >= 4); | |
5403 | newname = ".lit4"; | |
5404 | } | |
5405 | else | |
5406 | { | |
5407 | if (using_gprs || g_switch_value < 8) | |
5408 | newname = RDATA_SECTION_NAME; | |
5409 | else | |
5410 | newname = ".lit8"; | |
5411 | } | |
5412 | ||
5413 | new_seg = subseg_new (newname, (subsegT) 0); | |
5414 | bfd_set_section_flags (stdoutput, new_seg, | |
5415 | SEC_ALLOC | SEC_LOAD | SEC_READONLY | SEC_DATA); | |
5416 | frag_align (length == 4 ? 2 : 3, 0, 0); | |
5417 | if (strncmp (TARGET_OS, "elf", 3) != 0) | |
5418 | record_alignment (new_seg, 4); | |
5419 | else | |
5420 | record_alignment (new_seg, length == 4 ? 2 : 3); | |
5421 | if (seg == now_seg) | |
1661c76c | 5422 | as_bad (_("cannot use `%s' in this section"), arg->insn->insn_mo->name); |
89565f1b RS |
5423 | |
5424 | /* Set the argument to the current address in the section. */ | |
5425 | imm->X_op = O_absent; | |
5426 | offset->X_op = O_symbol; | |
5427 | offset->X_add_symbol = symbol_temp_new_now (); | |
5428 | offset->X_add_number = 0; | |
5429 | ||
5430 | /* Put the floating point number into the section. */ | |
5431 | p = frag_more (length); | |
5432 | memcpy (p, data, length); | |
5433 | ||
5434 | /* Switch back to the original section. */ | |
5435 | subseg_set (seg, subseg); | |
a92713e6 | 5436 | return TRUE; |
89565f1b RS |
5437 | } |
5438 | ||
14daeee3 RS |
5439 | /* OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX matcher; MATCH_P selects between |
5440 | them. */ | |
5441 | ||
5442 | static bfd_boolean | |
5443 | match_vu0_suffix_operand (struct mips_arg_info *arg, | |
5444 | const struct mips_operand *operand, | |
5445 | bfd_boolean match_p) | |
5446 | { | |
5447 | unsigned int uval; | |
5448 | ||
5449 | /* The operand can be an XYZW mask or a single 2-bit channel index | |
5450 | (with X being 0). */ | |
5451 | gas_assert (operand->size == 2 || operand->size == 4); | |
5452 | ||
ee5734f0 | 5453 | /* The suffix can be omitted when it is already part of the opcode. */ |
14daeee3 | 5454 | if (arg->token->type != OT_CHANNELS) |
ee5734f0 | 5455 | return match_p; |
14daeee3 RS |
5456 | |
5457 | uval = arg->token->u.channels; | |
5458 | if (operand->size == 2) | |
5459 | { | |
5460 | /* Check that a single bit is set and convert it into a 2-bit index. */ | |
5461 | if ((uval & -uval) != uval) | |
5462 | return FALSE; | |
5463 | uval = 4 - ffs (uval); | |
5464 | } | |
5465 | ||
5466 | if (match_p && insn_extract_operand (arg->insn, operand) != uval) | |
5467 | return FALSE; | |
5468 | ||
5469 | ++arg->token; | |
5470 | if (!match_p) | |
5471 | insn_insert_operand (arg->insn, operand, uval); | |
5472 | return TRUE; | |
5473 | } | |
5474 | ||
a1d78564 RS |
5475 | /* S is the text seen for ARG. Match it against OPERAND. Return the end |
5476 | of the argument text if the match is successful, otherwise return null. */ | |
5477 | ||
a92713e6 | 5478 | static bfd_boolean |
a1d78564 | 5479 | match_operand (struct mips_arg_info *arg, |
a92713e6 | 5480 | const struct mips_operand *operand) |
a1d78564 RS |
5481 | { |
5482 | switch (operand->type) | |
5483 | { | |
5484 | case OP_INT: | |
a92713e6 | 5485 | return match_int_operand (arg, operand); |
a1d78564 RS |
5486 | |
5487 | case OP_MAPPED_INT: | |
a92713e6 | 5488 | return match_mapped_int_operand (arg, operand); |
a1d78564 RS |
5489 | |
5490 | case OP_MSB: | |
a92713e6 | 5491 | return match_msb_operand (arg, operand); |
a1d78564 RS |
5492 | |
5493 | case OP_REG: | |
0f35dbc4 | 5494 | case OP_OPTIONAL_REG: |
a92713e6 | 5495 | return match_reg_operand (arg, operand); |
a1d78564 RS |
5496 | |
5497 | case OP_REG_PAIR: | |
a92713e6 | 5498 | return match_reg_pair_operand (arg, operand); |
a1d78564 RS |
5499 | |
5500 | case OP_PCREL: | |
a92713e6 | 5501 | return match_pcrel_operand (arg); |
a1d78564 RS |
5502 | |
5503 | case OP_PERF_REG: | |
a92713e6 | 5504 | return match_perf_reg_operand (arg, operand); |
a1d78564 RS |
5505 | |
5506 | case OP_ADDIUSP_INT: | |
a92713e6 | 5507 | return match_addiusp_operand (arg, operand); |
a1d78564 RS |
5508 | |
5509 | case OP_CLO_CLZ_DEST: | |
a92713e6 | 5510 | return match_clo_clz_dest_operand (arg, operand); |
a1d78564 RS |
5511 | |
5512 | case OP_LWM_SWM_LIST: | |
a92713e6 | 5513 | return match_lwm_swm_list_operand (arg, operand); |
a1d78564 RS |
5514 | |
5515 | case OP_ENTRY_EXIT_LIST: | |
a92713e6 | 5516 | return match_entry_exit_operand (arg, operand); |
364215c8 | 5517 | |
a1d78564 | 5518 | case OP_SAVE_RESTORE_LIST: |
a92713e6 | 5519 | return match_save_restore_list_operand (arg); |
a1d78564 RS |
5520 | |
5521 | case OP_MDMX_IMM_REG: | |
a92713e6 | 5522 | return match_mdmx_imm_reg_operand (arg, operand); |
a1d78564 RS |
5523 | |
5524 | case OP_REPEAT_DEST_REG: | |
a92713e6 | 5525 | return match_tied_reg_operand (arg, arg->dest_regno); |
a1d78564 RS |
5526 | |
5527 | case OP_REPEAT_PREV_REG: | |
a92713e6 | 5528 | return match_tied_reg_operand (arg, arg->last_regno); |
a1d78564 RS |
5529 | |
5530 | case OP_PC: | |
a92713e6 | 5531 | return match_pc_operand (arg); |
14daeee3 RS |
5532 | |
5533 | case OP_VU0_SUFFIX: | |
5534 | return match_vu0_suffix_operand (arg, operand, FALSE); | |
5535 | ||
5536 | case OP_VU0_MATCH_SUFFIX: | |
5537 | return match_vu0_suffix_operand (arg, operand, TRUE); | |
56d438b1 CF |
5538 | |
5539 | case OP_IMM_INDEX: | |
5540 | return match_imm_index_operand (arg, operand); | |
5541 | ||
5542 | case OP_REG_INDEX: | |
5543 | return match_reg_index_operand (arg, operand); | |
a1d78564 RS |
5544 | } |
5545 | abort (); | |
5546 | } | |
5547 | ||
5548 | /* ARG is the state after successfully matching an instruction. | |
5549 | Issue any queued-up warnings. */ | |
5550 | ||
5551 | static void | |
5552 | check_completed_insn (struct mips_arg_info *arg) | |
5553 | { | |
5554 | if (arg->seen_at) | |
5555 | { | |
5556 | if (AT == ATREG) | |
1661c76c | 5557 | as_warn (_("used $at without \".set noat\"")); |
a1d78564 | 5558 | else |
1661c76c | 5559 | as_warn (_("used $%u with \".set at=$%u\""), AT, AT); |
a1d78564 RS |
5560 | } |
5561 | } | |
a1d78564 | 5562 | |
85fcb30f RS |
5563 | /* Return true if modifying general-purpose register REG needs a delay. */ |
5564 | ||
5565 | static bfd_boolean | |
5566 | reg_needs_delay (unsigned int reg) | |
5567 | { | |
5568 | unsigned long prev_pinfo; | |
5569 | ||
5570 | prev_pinfo = history[0].insn_mo->pinfo; | |
5571 | if (!mips_opts.noreorder | |
67dc82bc | 5572 | && (((prev_pinfo & INSN_LOAD_MEMORY) && !gpr_interlocks) |
85fcb30f RS |
5573 | || ((prev_pinfo & INSN_LOAD_COPROC_DELAY) && !cop_interlocks)) |
5574 | && (gpr_write_mask (&history[0]) & (1 << reg))) | |
5575 | return TRUE; | |
5576 | ||
5577 | return FALSE; | |
5578 | } | |
5579 | ||
71400594 RS |
5580 | /* Classify an instruction according to the FIX_VR4120_* enumeration. |
5581 | Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected | |
5582 | by VR4120 errata. */ | |
4d7206a2 | 5583 | |
71400594 RS |
5584 | static unsigned int |
5585 | classify_vr4120_insn (const char *name) | |
252b5132 | 5586 | { |
71400594 RS |
5587 | if (strncmp (name, "macc", 4) == 0) |
5588 | return FIX_VR4120_MACC; | |
5589 | if (strncmp (name, "dmacc", 5) == 0) | |
5590 | return FIX_VR4120_DMACC; | |
5591 | if (strncmp (name, "mult", 4) == 0) | |
5592 | return FIX_VR4120_MULT; | |
5593 | if (strncmp (name, "dmult", 5) == 0) | |
5594 | return FIX_VR4120_DMULT; | |
5595 | if (strstr (name, "div")) | |
5596 | return FIX_VR4120_DIV; | |
5597 | if (strcmp (name, "mtlo") == 0 || strcmp (name, "mthi") == 0) | |
5598 | return FIX_VR4120_MTHILO; | |
5599 | return NUM_FIX_VR4120_CLASSES; | |
5600 | } | |
252b5132 | 5601 | |
a8d14a88 CM |
5602 | #define INSN_ERET 0x42000018 |
5603 | #define INSN_DERET 0x4200001f | |
5604 | #define INSN_DMULT 0x1c | |
5605 | #define INSN_DMULTU 0x1d | |
ff239038 | 5606 | |
71400594 RS |
5607 | /* Return the number of instructions that must separate INSN1 and INSN2, |
5608 | where INSN1 is the earlier instruction. Return the worst-case value | |
5609 | for any INSN2 if INSN2 is null. */ | |
252b5132 | 5610 | |
71400594 RS |
5611 | static unsigned int |
5612 | insns_between (const struct mips_cl_insn *insn1, | |
5613 | const struct mips_cl_insn *insn2) | |
5614 | { | |
5615 | unsigned long pinfo1, pinfo2; | |
4c260379 | 5616 | unsigned int mask; |
71400594 | 5617 | |
85fcb30f RS |
5618 | /* If INFO2 is null, pessimistically assume that all flags are set for |
5619 | the second instruction. */ | |
71400594 RS |
5620 | pinfo1 = insn1->insn_mo->pinfo; |
5621 | pinfo2 = insn2 ? insn2->insn_mo->pinfo : ~0U; | |
252b5132 | 5622 | |
71400594 RS |
5623 | /* For most targets, write-after-read dependencies on the HI and LO |
5624 | registers must be separated by at least two instructions. */ | |
5625 | if (!hilo_interlocks) | |
252b5132 | 5626 | { |
71400594 RS |
5627 | if ((pinfo1 & INSN_READ_LO) && (pinfo2 & INSN_WRITE_LO)) |
5628 | return 2; | |
5629 | if ((pinfo1 & INSN_READ_HI) && (pinfo2 & INSN_WRITE_HI)) | |
5630 | return 2; | |
5631 | } | |
5632 | ||
5633 | /* If we're working around r7000 errata, there must be two instructions | |
5634 | between an mfhi or mflo and any instruction that uses the result. */ | |
5635 | if (mips_7000_hilo_fix | |
df58fc94 | 5636 | && !mips_opts.micromips |
71400594 | 5637 | && MF_HILO_INSN (pinfo1) |
85fcb30f | 5638 | && (insn2 == NULL || (gpr_read_mask (insn2) & gpr_write_mask (insn1)))) |
71400594 RS |
5639 | return 2; |
5640 | ||
ff239038 CM |
5641 | /* If we're working around 24K errata, one instruction is required |
5642 | if an ERET or DERET is followed by a branch instruction. */ | |
df58fc94 | 5643 | if (mips_fix_24k && !mips_opts.micromips) |
ff239038 CM |
5644 | { |
5645 | if (insn1->insn_opcode == INSN_ERET | |
5646 | || insn1->insn_opcode == INSN_DERET) | |
5647 | { | |
5648 | if (insn2 == NULL | |
5649 | || insn2->insn_opcode == INSN_ERET | |
5650 | || insn2->insn_opcode == INSN_DERET | |
11625dd8 | 5651 | || delayed_branch_p (insn2)) |
ff239038 CM |
5652 | return 1; |
5653 | } | |
5654 | } | |
5655 | ||
a8d14a88 CM |
5656 | /* If we're working around PMC RM7000 errata, there must be three |
5657 | nops between a dmult and a load instruction. */ | |
5658 | if (mips_fix_rm7000 && !mips_opts.micromips) | |
5659 | { | |
5660 | if ((insn1->insn_opcode & insn1->insn_mo->mask) == INSN_DMULT | |
5661 | || (insn1->insn_opcode & insn1->insn_mo->mask) == INSN_DMULTU) | |
5662 | { | |
5663 | if (pinfo2 & INSN_LOAD_MEMORY) | |
5664 | return 3; | |
5665 | } | |
5666 | } | |
5667 | ||
71400594 RS |
5668 | /* If working around VR4120 errata, check for combinations that need |
5669 | a single intervening instruction. */ | |
df58fc94 | 5670 | if (mips_fix_vr4120 && !mips_opts.micromips) |
71400594 RS |
5671 | { |
5672 | unsigned int class1, class2; | |
252b5132 | 5673 | |
71400594 RS |
5674 | class1 = classify_vr4120_insn (insn1->insn_mo->name); |
5675 | if (class1 != NUM_FIX_VR4120_CLASSES && vr4120_conflicts[class1] != 0) | |
252b5132 | 5676 | { |
71400594 RS |
5677 | if (insn2 == NULL) |
5678 | return 1; | |
5679 | class2 = classify_vr4120_insn (insn2->insn_mo->name); | |
5680 | if (vr4120_conflicts[class1] & (1 << class2)) | |
5681 | return 1; | |
252b5132 | 5682 | } |
71400594 RS |
5683 | } |
5684 | ||
df58fc94 | 5685 | if (!HAVE_CODE_COMPRESSION) |
71400594 RS |
5686 | { |
5687 | /* Check for GPR or coprocessor load delays. All such delays | |
5688 | are on the RT register. */ | |
5689 | /* Itbl support may require additional care here. */ | |
67dc82bc | 5690 | if ((!gpr_interlocks && (pinfo1 & INSN_LOAD_MEMORY)) |
71400594 | 5691 | || (!cop_interlocks && (pinfo1 & INSN_LOAD_COPROC_DELAY))) |
252b5132 | 5692 | { |
85fcb30f | 5693 | if (insn2 == NULL || (gpr_read_mask (insn2) & gpr_write_mask (insn1))) |
71400594 RS |
5694 | return 1; |
5695 | } | |
5696 | ||
5697 | /* Check for generic coprocessor hazards. | |
5698 | ||
5699 | This case is not handled very well. There is no special | |
5700 | knowledge of CP0 handling, and the coprocessors other than | |
5701 | the floating point unit are not distinguished at all. */ | |
5702 | /* Itbl support may require additional care here. FIXME! | |
5703 | Need to modify this to include knowledge about | |
5704 | user specified delays! */ | |
5705 | else if ((!cop_interlocks && (pinfo1 & INSN_COPROC_MOVE_DELAY)) | |
5706 | || (!cop_mem_interlocks && (pinfo1 & INSN_COPROC_MEMORY_DELAY))) | |
5707 | { | |
5708 | /* Handle cases where INSN1 writes to a known general coprocessor | |
5709 | register. There must be a one instruction delay before INSN2 | |
5710 | if INSN2 reads that register, otherwise no delay is needed. */ | |
4c260379 RS |
5711 | mask = fpr_write_mask (insn1); |
5712 | if (mask != 0) | |
252b5132 | 5713 | { |
4c260379 | 5714 | if (!insn2 || (mask & fpr_read_mask (insn2)) != 0) |
71400594 | 5715 | return 1; |
252b5132 RH |
5716 | } |
5717 | else | |
5718 | { | |
71400594 RS |
5719 | /* Read-after-write dependencies on the control registers |
5720 | require a two-instruction gap. */ | |
5721 | if ((pinfo1 & INSN_WRITE_COND_CODE) | |
5722 | && (pinfo2 & INSN_READ_COND_CODE)) | |
5723 | return 2; | |
5724 | ||
5725 | /* We don't know exactly what INSN1 does. If INSN2 is | |
5726 | also a coprocessor instruction, assume there must be | |
5727 | a one instruction gap. */ | |
5728 | if (pinfo2 & INSN_COP) | |
5729 | return 1; | |
252b5132 RH |
5730 | } |
5731 | } | |
6b76fefe | 5732 | |
71400594 RS |
5733 | /* Check for read-after-write dependencies on the coprocessor |
5734 | control registers in cases where INSN1 does not need a general | |
5735 | coprocessor delay. This means that INSN1 is a floating point | |
5736 | comparison instruction. */ | |
5737 | /* Itbl support may require additional care here. */ | |
5738 | else if (!cop_interlocks | |
5739 | && (pinfo1 & INSN_WRITE_COND_CODE) | |
5740 | && (pinfo2 & INSN_READ_COND_CODE)) | |
5741 | return 1; | |
5742 | } | |
6b76fefe | 5743 | |
71400594 RS |
5744 | return 0; |
5745 | } | |
6b76fefe | 5746 | |
7d8e00cf RS |
5747 | /* Return the number of nops that would be needed to work around the |
5748 | VR4130 mflo/mfhi errata if instruction INSN immediately followed | |
932d1a1b RS |
5749 | the MAX_VR4130_NOPS instructions described by HIST. Ignore hazards |
5750 | that are contained within the first IGNORE instructions of HIST. */ | |
7d8e00cf RS |
5751 | |
5752 | static int | |
932d1a1b | 5753 | nops_for_vr4130 (int ignore, const struct mips_cl_insn *hist, |
7d8e00cf RS |
5754 | const struct mips_cl_insn *insn) |
5755 | { | |
4c260379 RS |
5756 | int i, j; |
5757 | unsigned int mask; | |
7d8e00cf RS |
5758 | |
5759 | /* Check if the instruction writes to HI or LO. MTHI and MTLO | |
5760 | are not affected by the errata. */ | |
5761 | if (insn != 0 | |
5762 | && ((insn->insn_mo->pinfo & (INSN_WRITE_HI | INSN_WRITE_LO)) == 0 | |
5763 | || strcmp (insn->insn_mo->name, "mtlo") == 0 | |
5764 | || strcmp (insn->insn_mo->name, "mthi") == 0)) | |
5765 | return 0; | |
5766 | ||
5767 | /* Search for the first MFLO or MFHI. */ | |
5768 | for (i = 0; i < MAX_VR4130_NOPS; i++) | |
91d6fa6a | 5769 | if (MF_HILO_INSN (hist[i].insn_mo->pinfo)) |
7d8e00cf RS |
5770 | { |
5771 | /* Extract the destination register. */ | |
4c260379 | 5772 | mask = gpr_write_mask (&hist[i]); |
7d8e00cf RS |
5773 | |
5774 | /* No nops are needed if INSN reads that register. */ | |
4c260379 | 5775 | if (insn != NULL && (gpr_read_mask (insn) & mask) != 0) |
7d8e00cf RS |
5776 | return 0; |
5777 | ||
5778 | /* ...or if any of the intervening instructions do. */ | |
5779 | for (j = 0; j < i; j++) | |
4c260379 | 5780 | if (gpr_read_mask (&hist[j]) & mask) |
7d8e00cf RS |
5781 | return 0; |
5782 | ||
932d1a1b RS |
5783 | if (i >= ignore) |
5784 | return MAX_VR4130_NOPS - i; | |
7d8e00cf RS |
5785 | } |
5786 | return 0; | |
5787 | } | |
5788 | ||
15be625d CM |
5789 | #define BASE_REG_EQ(INSN1, INSN2) \ |
5790 | ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \ | |
5791 | == (((INSN2) >> OP_SH_RS) & OP_MASK_RS)) | |
5792 | ||
5793 | /* Return the minimum alignment for this store instruction. */ | |
5794 | ||
5795 | static int | |
5796 | fix_24k_align_to (const struct mips_opcode *mo) | |
5797 | { | |
5798 | if (strcmp (mo->name, "sh") == 0) | |
5799 | return 2; | |
5800 | ||
5801 | if (strcmp (mo->name, "swc1") == 0 | |
5802 | || strcmp (mo->name, "swc2") == 0 | |
5803 | || strcmp (mo->name, "sw") == 0 | |
5804 | || strcmp (mo->name, "sc") == 0 | |
5805 | || strcmp (mo->name, "s.s") == 0) | |
5806 | return 4; | |
5807 | ||
5808 | if (strcmp (mo->name, "sdc1") == 0 | |
5809 | || strcmp (mo->name, "sdc2") == 0 | |
5810 | || strcmp (mo->name, "s.d") == 0) | |
5811 | return 8; | |
5812 | ||
5813 | /* sb, swl, swr */ | |
5814 | return 1; | |
5815 | } | |
5816 | ||
5817 | struct fix_24k_store_info | |
5818 | { | |
5819 | /* Immediate offset, if any, for this store instruction. */ | |
5820 | short off; | |
5821 | /* Alignment required by this store instruction. */ | |
5822 | int align_to; | |
5823 | /* True for register offsets. */ | |
5824 | int register_offset; | |
5825 | }; | |
5826 | ||
5827 | /* Comparison function used by qsort. */ | |
5828 | ||
5829 | static int | |
5830 | fix_24k_sort (const void *a, const void *b) | |
5831 | { | |
5832 | const struct fix_24k_store_info *pos1 = a; | |
5833 | const struct fix_24k_store_info *pos2 = b; | |
5834 | ||
5835 | return (pos1->off - pos2->off); | |
5836 | } | |
5837 | ||
5838 | /* INSN is a store instruction. Try to record the store information | |
5839 | in STINFO. Return false if the information isn't known. */ | |
5840 | ||
5841 | static bfd_boolean | |
5842 | fix_24k_record_store_info (struct fix_24k_store_info *stinfo, | |
ab9794cf | 5843 | const struct mips_cl_insn *insn) |
15be625d CM |
5844 | { |
5845 | /* The instruction must have a known offset. */ | |
5846 | if (!insn->complete_p || !strstr (insn->insn_mo->args, "o(")) | |
5847 | return FALSE; | |
5848 | ||
5849 | stinfo->off = (insn->insn_opcode >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE; | |
5850 | stinfo->align_to = fix_24k_align_to (insn->insn_mo); | |
5851 | return TRUE; | |
5852 | } | |
5853 | ||
932d1a1b RS |
5854 | /* Return the number of nops that would be needed to work around the 24k |
5855 | "lost data on stores during refill" errata if instruction INSN | |
5856 | immediately followed the 2 instructions described by HIST. | |
5857 | Ignore hazards that are contained within the first IGNORE | |
5858 | instructions of HIST. | |
5859 | ||
5860 | Problem: The FSB (fetch store buffer) acts as an intermediate buffer | |
5861 | for the data cache refills and store data. The following describes | |
5862 | the scenario where the store data could be lost. | |
5863 | ||
5864 | * A data cache miss, due to either a load or a store, causing fill | |
5865 | data to be supplied by the memory subsystem | |
5866 | * The first three doublewords of fill data are returned and written | |
5867 | into the cache | |
5868 | * A sequence of four stores occurs in consecutive cycles around the | |
5869 | final doubleword of the fill: | |
5870 | * Store A | |
5871 | * Store B | |
5872 | * Store C | |
5873 | * Zero, One or more instructions | |
5874 | * Store D | |
5875 | ||
5876 | The four stores A-D must be to different doublewords of the line that | |
5877 | is being filled. The fourth instruction in the sequence above permits | |
5878 | the fill of the final doubleword to be transferred from the FSB into | |
5879 | the cache. In the sequence above, the stores may be either integer | |
5880 | (sb, sh, sw, swr, swl, sc) or coprocessor (swc1/swc2, sdc1/sdc2, | |
5881 | swxc1, sdxc1, suxc1) stores, as long as the four stores are to | |
5882 | different doublewords on the line. If the floating point unit is | |
5883 | running in 1:2 mode, it is not possible to create the sequence above | |
5884 | using only floating point store instructions. | |
15be625d CM |
5885 | |
5886 | In this case, the cache line being filled is incorrectly marked | |
5887 | invalid, thereby losing the data from any store to the line that | |
5888 | occurs between the original miss and the completion of the five | |
5889 | cycle sequence shown above. | |
5890 | ||
932d1a1b | 5891 | The workarounds are: |
15be625d | 5892 | |
932d1a1b RS |
5893 | * Run the data cache in write-through mode. |
5894 | * Insert a non-store instruction between | |
5895 | Store A and Store B or Store B and Store C. */ | |
15be625d CM |
5896 | |
5897 | static int | |
932d1a1b | 5898 | nops_for_24k (int ignore, const struct mips_cl_insn *hist, |
15be625d CM |
5899 | const struct mips_cl_insn *insn) |
5900 | { | |
5901 | struct fix_24k_store_info pos[3]; | |
5902 | int align, i, base_offset; | |
5903 | ||
932d1a1b RS |
5904 | if (ignore >= 2) |
5905 | return 0; | |
5906 | ||
ab9794cf RS |
5907 | /* If the previous instruction wasn't a store, there's nothing to |
5908 | worry about. */ | |
15be625d CM |
5909 | if ((hist[0].insn_mo->pinfo & INSN_STORE_MEMORY) == 0) |
5910 | return 0; | |
5911 | ||
ab9794cf RS |
5912 | /* If the instructions after the previous one are unknown, we have |
5913 | to assume the worst. */ | |
5914 | if (!insn) | |
15be625d CM |
5915 | return 1; |
5916 | ||
ab9794cf RS |
5917 | /* Check whether we are dealing with three consecutive stores. */ |
5918 | if ((insn->insn_mo->pinfo & INSN_STORE_MEMORY) == 0 | |
5919 | || (hist[1].insn_mo->pinfo & INSN_STORE_MEMORY) == 0) | |
15be625d CM |
5920 | return 0; |
5921 | ||
5922 | /* If we don't know the relationship between the store addresses, | |
5923 | assume the worst. */ | |
ab9794cf | 5924 | if (!BASE_REG_EQ (insn->insn_opcode, hist[0].insn_opcode) |
15be625d CM |
5925 | || !BASE_REG_EQ (insn->insn_opcode, hist[1].insn_opcode)) |
5926 | return 1; | |
5927 | ||
5928 | if (!fix_24k_record_store_info (&pos[0], insn) | |
5929 | || !fix_24k_record_store_info (&pos[1], &hist[0]) | |
5930 | || !fix_24k_record_store_info (&pos[2], &hist[1])) | |
5931 | return 1; | |
5932 | ||
5933 | qsort (&pos, 3, sizeof (struct fix_24k_store_info), fix_24k_sort); | |
5934 | ||
5935 | /* Pick a value of ALIGN and X such that all offsets are adjusted by | |
5936 | X bytes and such that the base register + X is known to be aligned | |
5937 | to align bytes. */ | |
5938 | ||
5939 | if (((insn->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == SP) | |
5940 | align = 8; | |
5941 | else | |
5942 | { | |
5943 | align = pos[0].align_to; | |
5944 | base_offset = pos[0].off; | |
5945 | for (i = 1; i < 3; i++) | |
5946 | if (align < pos[i].align_to) | |
5947 | { | |
5948 | align = pos[i].align_to; | |
5949 | base_offset = pos[i].off; | |
5950 | } | |
5951 | for (i = 0; i < 3; i++) | |
5952 | pos[i].off -= base_offset; | |
5953 | } | |
5954 | ||
5955 | pos[0].off &= ~align + 1; | |
5956 | pos[1].off &= ~align + 1; | |
5957 | pos[2].off &= ~align + 1; | |
5958 | ||
5959 | /* If any two stores write to the same chunk, they also write to the | |
5960 | same doubleword. The offsets are still sorted at this point. */ | |
5961 | if (pos[0].off == pos[1].off || pos[1].off == pos[2].off) | |
5962 | return 0; | |
5963 | ||
5964 | /* A range of at least 9 bytes is needed for the stores to be in | |
5965 | non-overlapping doublewords. */ | |
5966 | if (pos[2].off - pos[0].off <= 8) | |
5967 | return 0; | |
5968 | ||
5969 | if (pos[2].off - pos[1].off >= 24 | |
5970 | || pos[1].off - pos[0].off >= 24 | |
5971 | || pos[2].off - pos[0].off >= 32) | |
5972 | return 0; | |
5973 | ||
5974 | return 1; | |
5975 | } | |
5976 | ||
71400594 | 5977 | /* Return the number of nops that would be needed if instruction INSN |
91d6fa6a | 5978 | immediately followed the MAX_NOPS instructions given by HIST, |
932d1a1b RS |
5979 | where HIST[0] is the most recent instruction. Ignore hazards |
5980 | between INSN and the first IGNORE instructions in HIST. | |
5981 | ||
5982 | If INSN is null, return the worse-case number of nops for any | |
5983 | instruction. */ | |
bdaaa2e1 | 5984 | |
71400594 | 5985 | static int |
932d1a1b | 5986 | nops_for_insn (int ignore, const struct mips_cl_insn *hist, |
71400594 RS |
5987 | const struct mips_cl_insn *insn) |
5988 | { | |
5989 | int i, nops, tmp_nops; | |
bdaaa2e1 | 5990 | |
71400594 | 5991 | nops = 0; |
932d1a1b | 5992 | for (i = ignore; i < MAX_DELAY_NOPS; i++) |
65b02341 | 5993 | { |
91d6fa6a | 5994 | tmp_nops = insns_between (hist + i, insn) - i; |
65b02341 RS |
5995 | if (tmp_nops > nops) |
5996 | nops = tmp_nops; | |
5997 | } | |
7d8e00cf | 5998 | |
df58fc94 | 5999 | if (mips_fix_vr4130 && !mips_opts.micromips) |
7d8e00cf | 6000 | { |
932d1a1b | 6001 | tmp_nops = nops_for_vr4130 (ignore, hist, insn); |
7d8e00cf RS |
6002 | if (tmp_nops > nops) |
6003 | nops = tmp_nops; | |
6004 | } | |
6005 | ||
df58fc94 | 6006 | if (mips_fix_24k && !mips_opts.micromips) |
15be625d | 6007 | { |
932d1a1b | 6008 | tmp_nops = nops_for_24k (ignore, hist, insn); |
15be625d CM |
6009 | if (tmp_nops > nops) |
6010 | nops = tmp_nops; | |
6011 | } | |
6012 | ||
71400594 RS |
6013 | return nops; |
6014 | } | |
252b5132 | 6015 | |
71400594 | 6016 | /* The variable arguments provide NUM_INSNS extra instructions that |
91d6fa6a | 6017 | might be added to HIST. Return the largest number of nops that |
932d1a1b RS |
6018 | would be needed after the extended sequence, ignoring hazards |
6019 | in the first IGNORE instructions. */ | |
252b5132 | 6020 | |
71400594 | 6021 | static int |
932d1a1b RS |
6022 | nops_for_sequence (int num_insns, int ignore, |
6023 | const struct mips_cl_insn *hist, ...) | |
71400594 RS |
6024 | { |
6025 | va_list args; | |
6026 | struct mips_cl_insn buffer[MAX_NOPS]; | |
6027 | struct mips_cl_insn *cursor; | |
6028 | int nops; | |
6029 | ||
91d6fa6a | 6030 | va_start (args, hist); |
71400594 | 6031 | cursor = buffer + num_insns; |
91d6fa6a | 6032 | memcpy (cursor, hist, (MAX_NOPS - num_insns) * sizeof (*cursor)); |
71400594 RS |
6033 | while (cursor > buffer) |
6034 | *--cursor = *va_arg (args, const struct mips_cl_insn *); | |
6035 | ||
932d1a1b | 6036 | nops = nops_for_insn (ignore, buffer, NULL); |
71400594 RS |
6037 | va_end (args); |
6038 | return nops; | |
6039 | } | |
252b5132 | 6040 | |
71400594 RS |
6041 | /* Like nops_for_insn, but if INSN is a branch, take into account the |
6042 | worst-case delay for the branch target. */ | |
252b5132 | 6043 | |
71400594 | 6044 | static int |
932d1a1b | 6045 | nops_for_insn_or_target (int ignore, const struct mips_cl_insn *hist, |
71400594 RS |
6046 | const struct mips_cl_insn *insn) |
6047 | { | |
6048 | int nops, tmp_nops; | |
60b63b72 | 6049 | |
932d1a1b | 6050 | nops = nops_for_insn (ignore, hist, insn); |
11625dd8 | 6051 | if (delayed_branch_p (insn)) |
71400594 | 6052 | { |
932d1a1b | 6053 | tmp_nops = nops_for_sequence (2, ignore ? ignore + 2 : 0, |
14fe068b | 6054 | hist, insn, get_delay_slot_nop (insn)); |
71400594 RS |
6055 | if (tmp_nops > nops) |
6056 | nops = tmp_nops; | |
6057 | } | |
11625dd8 | 6058 | else if (compact_branch_p (insn)) |
71400594 | 6059 | { |
932d1a1b | 6060 | tmp_nops = nops_for_sequence (1, ignore ? ignore + 1 : 0, hist, insn); |
71400594 RS |
6061 | if (tmp_nops > nops) |
6062 | nops = tmp_nops; | |
6063 | } | |
6064 | return nops; | |
6065 | } | |
6066 | ||
c67a084a NC |
6067 | /* Fix NOP issue: Replace nops by "or at,at,zero". */ |
6068 | ||
6069 | static void | |
6070 | fix_loongson2f_nop (struct mips_cl_insn * ip) | |
6071 | { | |
df58fc94 | 6072 | gas_assert (!HAVE_CODE_COMPRESSION); |
c67a084a NC |
6073 | if (strcmp (ip->insn_mo->name, "nop") == 0) |
6074 | ip->insn_opcode = LOONGSON2F_NOP_INSN; | |
6075 | } | |
6076 | ||
6077 | /* Fix Jump Issue: Eliminate instruction fetch from outside 256M region | |
6078 | jr target pc &= 'hffff_ffff_cfff_ffff. */ | |
6079 | ||
6080 | static void | |
6081 | fix_loongson2f_jump (struct mips_cl_insn * ip) | |
6082 | { | |
df58fc94 | 6083 | gas_assert (!HAVE_CODE_COMPRESSION); |
c67a084a NC |
6084 | if (strcmp (ip->insn_mo->name, "j") == 0 |
6085 | || strcmp (ip->insn_mo->name, "jr") == 0 | |
6086 | || strcmp (ip->insn_mo->name, "jalr") == 0) | |
6087 | { | |
6088 | int sreg; | |
6089 | expressionS ep; | |
6090 | ||
6091 | if (! mips_opts.at) | |
6092 | return; | |
6093 | ||
df58fc94 | 6094 | sreg = EXTRACT_OPERAND (0, RS, *ip); |
c67a084a NC |
6095 | if (sreg == ZERO || sreg == KT0 || sreg == KT1 || sreg == ATREG) |
6096 | return; | |
6097 | ||
6098 | ep.X_op = O_constant; | |
6099 | ep.X_add_number = 0xcfff0000; | |
6100 | macro_build (&ep, "lui", "t,u", ATREG, BFD_RELOC_HI16); | |
6101 | ep.X_add_number = 0xffff; | |
6102 | macro_build (&ep, "ori", "t,r,i", ATREG, ATREG, BFD_RELOC_LO16); | |
6103 | macro_build (NULL, "and", "d,v,t", sreg, sreg, ATREG); | |
6104 | } | |
6105 | } | |
6106 | ||
6107 | static void | |
6108 | fix_loongson2f (struct mips_cl_insn * ip) | |
6109 | { | |
6110 | if (mips_fix_loongson2f_nop) | |
6111 | fix_loongson2f_nop (ip); | |
6112 | ||
6113 | if (mips_fix_loongson2f_jump) | |
6114 | fix_loongson2f_jump (ip); | |
6115 | } | |
6116 | ||
a4e06468 RS |
6117 | /* IP is a branch that has a delay slot, and we need to fill it |
6118 | automatically. Return true if we can do that by swapping IP | |
e407c74b NC |
6119 | with the previous instruction. |
6120 | ADDRESS_EXPR is an operand of the instruction to be used with | |
6121 | RELOC_TYPE. */ | |
a4e06468 RS |
6122 | |
6123 | static bfd_boolean | |
e407c74b | 6124 | can_swap_branch_p (struct mips_cl_insn *ip, expressionS *address_expr, |
26545944 | 6125 | bfd_reloc_code_real_type *reloc_type) |
a4e06468 | 6126 | { |
2b0c8b40 | 6127 | unsigned long pinfo, pinfo2, prev_pinfo, prev_pinfo2; |
a4e06468 | 6128 | unsigned int gpr_read, gpr_write, prev_gpr_read, prev_gpr_write; |
9d5de888 | 6129 | unsigned int fpr_read, prev_fpr_write; |
a4e06468 RS |
6130 | |
6131 | /* -O2 and above is required for this optimization. */ | |
6132 | if (mips_optimize < 2) | |
6133 | return FALSE; | |
6134 | ||
6135 | /* If we have seen .set volatile or .set nomove, don't optimize. */ | |
6136 | if (mips_opts.nomove) | |
6137 | return FALSE; | |
6138 | ||
6139 | /* We can't swap if the previous instruction's position is fixed. */ | |
6140 | if (history[0].fixed_p) | |
6141 | return FALSE; | |
6142 | ||
6143 | /* If the previous previous insn was in a .set noreorder, we can't | |
6144 | swap. Actually, the MIPS assembler will swap in this situation. | |
6145 | However, gcc configured -with-gnu-as will generate code like | |
6146 | ||
6147 | .set noreorder | |
6148 | lw $4,XXX | |
6149 | .set reorder | |
6150 | INSN | |
6151 | bne $4,$0,foo | |
6152 | ||
6153 | in which we can not swap the bne and INSN. If gcc is not configured | |
6154 | -with-gnu-as, it does not output the .set pseudo-ops. */ | |
6155 | if (history[1].noreorder_p) | |
6156 | return FALSE; | |
6157 | ||
87333bb7 MR |
6158 | /* If the previous instruction had a fixup in mips16 mode, we can not swap. |
6159 | This means that the previous instruction was a 4-byte one anyhow. */ | |
a4e06468 RS |
6160 | if (mips_opts.mips16 && history[0].fixp[0]) |
6161 | return FALSE; | |
6162 | ||
6163 | /* If the branch is itself the target of a branch, we can not swap. | |
6164 | We cheat on this; all we check for is whether there is a label on | |
6165 | this instruction. If there are any branches to anything other than | |
6166 | a label, users must use .set noreorder. */ | |
6167 | if (seg_info (now_seg)->label_list) | |
6168 | return FALSE; | |
6169 | ||
6170 | /* If the previous instruction is in a variant frag other than this | |
2309ddf2 | 6171 | branch's one, we cannot do the swap. This does not apply to |
9301f9c3 MR |
6172 | MIPS16 code, which uses variant frags for different purposes. */ |
6173 | if (!mips_opts.mips16 | |
a4e06468 RS |
6174 | && history[0].frag |
6175 | && history[0].frag->fr_type == rs_machine_dependent) | |
6176 | return FALSE; | |
6177 | ||
bcd530a7 RS |
6178 | /* We do not swap with instructions that cannot architecturally |
6179 | be placed in a branch delay slot, such as SYNC or ERET. We | |
6180 | also refrain from swapping with a trap instruction, since it | |
6181 | complicates trap handlers to have the trap instruction be in | |
6182 | a delay slot. */ | |
a4e06468 | 6183 | prev_pinfo = history[0].insn_mo->pinfo; |
bcd530a7 | 6184 | if (prev_pinfo & INSN_NO_DELAY_SLOT) |
a4e06468 RS |
6185 | return FALSE; |
6186 | ||
6187 | /* Check for conflicts between the branch and the instructions | |
6188 | before the candidate delay slot. */ | |
6189 | if (nops_for_insn (0, history + 1, ip) > 0) | |
6190 | return FALSE; | |
6191 | ||
6192 | /* Check for conflicts between the swapped sequence and the | |
6193 | target of the branch. */ | |
6194 | if (nops_for_sequence (2, 0, history + 1, ip, history) > 0) | |
6195 | return FALSE; | |
6196 | ||
6197 | /* If the branch reads a register that the previous | |
6198 | instruction sets, we can not swap. */ | |
6199 | gpr_read = gpr_read_mask (ip); | |
6200 | prev_gpr_write = gpr_write_mask (&history[0]); | |
6201 | if (gpr_read & prev_gpr_write) | |
6202 | return FALSE; | |
6203 | ||
9d5de888 CF |
6204 | fpr_read = fpr_read_mask (ip); |
6205 | prev_fpr_write = fpr_write_mask (&history[0]); | |
6206 | if (fpr_read & prev_fpr_write) | |
6207 | return FALSE; | |
6208 | ||
a4e06468 RS |
6209 | /* If the branch writes a register that the previous |
6210 | instruction sets, we can not swap. */ | |
6211 | gpr_write = gpr_write_mask (ip); | |
6212 | if (gpr_write & prev_gpr_write) | |
6213 | return FALSE; | |
6214 | ||
6215 | /* If the branch writes a register that the previous | |
6216 | instruction reads, we can not swap. */ | |
6217 | prev_gpr_read = gpr_read_mask (&history[0]); | |
6218 | if (gpr_write & prev_gpr_read) | |
6219 | return FALSE; | |
6220 | ||
6221 | /* If one instruction sets a condition code and the | |
6222 | other one uses a condition code, we can not swap. */ | |
6223 | pinfo = ip->insn_mo->pinfo; | |
6224 | if ((pinfo & INSN_READ_COND_CODE) | |
6225 | && (prev_pinfo & INSN_WRITE_COND_CODE)) | |
6226 | return FALSE; | |
6227 | if ((pinfo & INSN_WRITE_COND_CODE) | |
6228 | && (prev_pinfo & INSN_READ_COND_CODE)) | |
6229 | return FALSE; | |
6230 | ||
6231 | /* If the previous instruction uses the PC, we can not swap. */ | |
2b0c8b40 | 6232 | prev_pinfo2 = history[0].insn_mo->pinfo2; |
26545944 | 6233 | if (prev_pinfo2 & INSN2_READ_PC) |
2b0c8b40 | 6234 | return FALSE; |
a4e06468 | 6235 | |
df58fc94 RS |
6236 | /* If the previous instruction has an incorrect size for a fixed |
6237 | branch delay slot in microMIPS mode, we cannot swap. */ | |
2309ddf2 MR |
6238 | pinfo2 = ip->insn_mo->pinfo2; |
6239 | if (mips_opts.micromips | |
6240 | && (pinfo2 & INSN2_BRANCH_DELAY_16BIT) | |
6241 | && insn_length (history) != 2) | |
6242 | return FALSE; | |
6243 | if (mips_opts.micromips | |
6244 | && (pinfo2 & INSN2_BRANCH_DELAY_32BIT) | |
6245 | && insn_length (history) != 4) | |
6246 | return FALSE; | |
6247 | ||
e407c74b NC |
6248 | /* On R5900 short loops need to be fixed by inserting a nop in |
6249 | the branch delay slots. | |
6250 | A short loop can be terminated too early. */ | |
6251 | if (mips_opts.arch == CPU_R5900 | |
6252 | /* Check if instruction has a parameter, ignore "j $31". */ | |
6253 | && (address_expr != NULL) | |
6254 | /* Parameter must be 16 bit. */ | |
6255 | && (*reloc_type == BFD_RELOC_16_PCREL_S2) | |
6256 | /* Branch to same segment. */ | |
6257 | && (S_GET_SEGMENT(address_expr->X_add_symbol) == now_seg) | |
6258 | /* Branch to same code fragment. */ | |
6259 | && (symbol_get_frag(address_expr->X_add_symbol) == frag_now) | |
6260 | /* Can only calculate branch offset if value is known. */ | |
6261 | && symbol_constant_p(address_expr->X_add_symbol) | |
6262 | /* Check if branch is really conditional. */ | |
6263 | && !((ip->insn_opcode & 0xffff0000) == 0x10000000 /* beq $0,$0 */ | |
6264 | || (ip->insn_opcode & 0xffff0000) == 0x04010000 /* bgez $0 */ | |
6265 | || (ip->insn_opcode & 0xffff0000) == 0x04110000)) /* bgezal $0 */ | |
6266 | { | |
6267 | int distance; | |
6268 | /* Check if loop is shorter than 6 instructions including | |
6269 | branch and delay slot. */ | |
6270 | distance = frag_now_fix() - S_GET_VALUE(address_expr->X_add_symbol); | |
6271 | if (distance <= 20) | |
6272 | { | |
6273 | int i; | |
6274 | int rv; | |
6275 | ||
6276 | rv = FALSE; | |
6277 | /* When the loop includes branches or jumps, | |
6278 | it is not a short loop. */ | |
6279 | for (i = 0; i < (distance / 4); i++) | |
6280 | { | |
6281 | if ((history[i].cleared_p) | |
6282 | || delayed_branch_p(&history[i])) | |
6283 | { | |
6284 | rv = TRUE; | |
6285 | break; | |
6286 | } | |
6287 | } | |
6288 | if (rv == FALSE) | |
6289 | { | |
6290 | /* Insert nop after branch to fix short loop. */ | |
6291 | return FALSE; | |
6292 | } | |
6293 | } | |
6294 | } | |
6295 | ||
a4e06468 RS |
6296 | return TRUE; |
6297 | } | |
6298 | ||
e407c74b NC |
6299 | /* Decide how we should add IP to the instruction stream. |
6300 | ADDRESS_EXPR is an operand of the instruction to be used with | |
6301 | RELOC_TYPE. */ | |
a4e06468 RS |
6302 | |
6303 | static enum append_method | |
e407c74b | 6304 | get_append_method (struct mips_cl_insn *ip, expressionS *address_expr, |
26545944 | 6305 | bfd_reloc_code_real_type *reloc_type) |
a4e06468 | 6306 | { |
a4e06468 RS |
6307 | /* The relaxed version of a macro sequence must be inherently |
6308 | hazard-free. */ | |
6309 | if (mips_relax.sequence == 2) | |
6310 | return APPEND_ADD; | |
6311 | ||
6312 | /* We must not dabble with instructions in a ".set norerorder" block. */ | |
6313 | if (mips_opts.noreorder) | |
6314 | return APPEND_ADD; | |
6315 | ||
6316 | /* Otherwise, it's our responsibility to fill branch delay slots. */ | |
11625dd8 | 6317 | if (delayed_branch_p (ip)) |
a4e06468 | 6318 | { |
e407c74b NC |
6319 | if (!branch_likely_p (ip) |
6320 | && can_swap_branch_p (ip, address_expr, reloc_type)) | |
a4e06468 RS |
6321 | return APPEND_SWAP; |
6322 | ||
6323 | if (mips_opts.mips16 | |
6324 | && ISA_SUPPORTS_MIPS16E | |
fc76e730 | 6325 | && gpr_read_mask (ip) != 0) |
a4e06468 RS |
6326 | return APPEND_ADD_COMPACT; |
6327 | ||
6328 | return APPEND_ADD_WITH_NOP; | |
6329 | } | |
6330 | ||
a4e06468 RS |
6331 | return APPEND_ADD; |
6332 | } | |
6333 | ||
ceb94aa5 RS |
6334 | /* IP is a MIPS16 instruction whose opcode we have just changed. |
6335 | Point IP->insn_mo to the new opcode's definition. */ | |
6336 | ||
6337 | static void | |
6338 | find_altered_mips16_opcode (struct mips_cl_insn *ip) | |
6339 | { | |
6340 | const struct mips_opcode *mo, *end; | |
6341 | ||
6342 | end = &mips16_opcodes[bfd_mips16_num_opcodes]; | |
6343 | for (mo = ip->insn_mo; mo < end; mo++) | |
6344 | if ((ip->insn_opcode & mo->mask) == mo->match) | |
6345 | { | |
6346 | ip->insn_mo = mo; | |
6347 | return; | |
6348 | } | |
6349 | abort (); | |
6350 | } | |
6351 | ||
df58fc94 RS |
6352 | /* For microMIPS macros, we need to generate a local number label |
6353 | as the target of branches. */ | |
6354 | #define MICROMIPS_LABEL_CHAR '\037' | |
6355 | static unsigned long micromips_target_label; | |
6356 | static char micromips_target_name[32]; | |
6357 | ||
6358 | static char * | |
6359 | micromips_label_name (void) | |
6360 | { | |
6361 | char *p = micromips_target_name; | |
6362 | char symbol_name_temporary[24]; | |
6363 | unsigned long l; | |
6364 | int i; | |
6365 | ||
6366 | if (*p) | |
6367 | return p; | |
6368 | ||
6369 | i = 0; | |
6370 | l = micromips_target_label; | |
6371 | #ifdef LOCAL_LABEL_PREFIX | |
6372 | *p++ = LOCAL_LABEL_PREFIX; | |
6373 | #endif | |
6374 | *p++ = 'L'; | |
6375 | *p++ = MICROMIPS_LABEL_CHAR; | |
6376 | do | |
6377 | { | |
6378 | symbol_name_temporary[i++] = l % 10 + '0'; | |
6379 | l /= 10; | |
6380 | } | |
6381 | while (l != 0); | |
6382 | while (i > 0) | |
6383 | *p++ = symbol_name_temporary[--i]; | |
6384 | *p = '\0'; | |
6385 | ||
6386 | return micromips_target_name; | |
6387 | } | |
6388 | ||
6389 | static void | |
6390 | micromips_label_expr (expressionS *label_expr) | |
6391 | { | |
6392 | label_expr->X_op = O_symbol; | |
6393 | label_expr->X_add_symbol = symbol_find_or_make (micromips_label_name ()); | |
6394 | label_expr->X_add_number = 0; | |
6395 | } | |
6396 | ||
6397 | static void | |
6398 | micromips_label_inc (void) | |
6399 | { | |
6400 | micromips_target_label++; | |
6401 | *micromips_target_name = '\0'; | |
6402 | } | |
6403 | ||
6404 | static void | |
6405 | micromips_add_label (void) | |
6406 | { | |
6407 | symbolS *s; | |
6408 | ||
6409 | s = colon (micromips_label_name ()); | |
6410 | micromips_label_inc (); | |
f3ded42a | 6411 | S_SET_OTHER (s, ELF_ST_SET_MICROMIPS (S_GET_OTHER (s))); |
df58fc94 RS |
6412 | } |
6413 | ||
6414 | /* If assembling microMIPS code, then return the microMIPS reloc | |
6415 | corresponding to the requested one if any. Otherwise return | |
6416 | the reloc unchanged. */ | |
6417 | ||
6418 | static bfd_reloc_code_real_type | |
6419 | micromips_map_reloc (bfd_reloc_code_real_type reloc) | |
6420 | { | |
6421 | static const bfd_reloc_code_real_type relocs[][2] = | |
6422 | { | |
6423 | /* Keep sorted incrementally by the left-hand key. */ | |
6424 | { BFD_RELOC_16_PCREL_S2, BFD_RELOC_MICROMIPS_16_PCREL_S1 }, | |
6425 | { BFD_RELOC_GPREL16, BFD_RELOC_MICROMIPS_GPREL16 }, | |
6426 | { BFD_RELOC_MIPS_JMP, BFD_RELOC_MICROMIPS_JMP }, | |
6427 | { BFD_RELOC_HI16, BFD_RELOC_MICROMIPS_HI16 }, | |
6428 | { BFD_RELOC_HI16_S, BFD_RELOC_MICROMIPS_HI16_S }, | |
6429 | { BFD_RELOC_LO16, BFD_RELOC_MICROMIPS_LO16 }, | |
6430 | { BFD_RELOC_MIPS_LITERAL, BFD_RELOC_MICROMIPS_LITERAL }, | |
6431 | { BFD_RELOC_MIPS_GOT16, BFD_RELOC_MICROMIPS_GOT16 }, | |
6432 | { BFD_RELOC_MIPS_CALL16, BFD_RELOC_MICROMIPS_CALL16 }, | |
6433 | { BFD_RELOC_MIPS_GOT_HI16, BFD_RELOC_MICROMIPS_GOT_HI16 }, | |
6434 | { BFD_RELOC_MIPS_GOT_LO16, BFD_RELOC_MICROMIPS_GOT_LO16 }, | |
6435 | { BFD_RELOC_MIPS_CALL_HI16, BFD_RELOC_MICROMIPS_CALL_HI16 }, | |
6436 | { BFD_RELOC_MIPS_CALL_LO16, BFD_RELOC_MICROMIPS_CALL_LO16 }, | |
6437 | { BFD_RELOC_MIPS_SUB, BFD_RELOC_MICROMIPS_SUB }, | |
6438 | { BFD_RELOC_MIPS_GOT_PAGE, BFD_RELOC_MICROMIPS_GOT_PAGE }, | |
6439 | { BFD_RELOC_MIPS_GOT_OFST, BFD_RELOC_MICROMIPS_GOT_OFST }, | |
6440 | { BFD_RELOC_MIPS_GOT_DISP, BFD_RELOC_MICROMIPS_GOT_DISP }, | |
6441 | { BFD_RELOC_MIPS_HIGHEST, BFD_RELOC_MICROMIPS_HIGHEST }, | |
6442 | { BFD_RELOC_MIPS_HIGHER, BFD_RELOC_MICROMIPS_HIGHER }, | |
6443 | { BFD_RELOC_MIPS_SCN_DISP, BFD_RELOC_MICROMIPS_SCN_DISP }, | |
6444 | { BFD_RELOC_MIPS_TLS_GD, BFD_RELOC_MICROMIPS_TLS_GD }, | |
6445 | { BFD_RELOC_MIPS_TLS_LDM, BFD_RELOC_MICROMIPS_TLS_LDM }, | |
6446 | { BFD_RELOC_MIPS_TLS_DTPREL_HI16, BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16 }, | |
6447 | { BFD_RELOC_MIPS_TLS_DTPREL_LO16, BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16 }, | |
6448 | { BFD_RELOC_MIPS_TLS_GOTTPREL, BFD_RELOC_MICROMIPS_TLS_GOTTPREL }, | |
6449 | { BFD_RELOC_MIPS_TLS_TPREL_HI16, BFD_RELOC_MICROMIPS_TLS_TPREL_HI16 }, | |
6450 | { BFD_RELOC_MIPS_TLS_TPREL_LO16, BFD_RELOC_MICROMIPS_TLS_TPREL_LO16 } | |
6451 | }; | |
6452 | bfd_reloc_code_real_type r; | |
6453 | size_t i; | |
6454 | ||
6455 | if (!mips_opts.micromips) | |
6456 | return reloc; | |
6457 | for (i = 0; i < ARRAY_SIZE (relocs); i++) | |
6458 | { | |
6459 | r = relocs[i][0]; | |
6460 | if (r > reloc) | |
6461 | return reloc; | |
6462 | if (r == reloc) | |
6463 | return relocs[i][1]; | |
6464 | } | |
6465 | return reloc; | |
6466 | } | |
6467 | ||
b886a2ab RS |
6468 | /* Try to resolve relocation RELOC against constant OPERAND at assembly time. |
6469 | Return true on success, storing the resolved value in RESULT. */ | |
6470 | ||
6471 | static bfd_boolean | |
6472 | calculate_reloc (bfd_reloc_code_real_type reloc, offsetT operand, | |
6473 | offsetT *result) | |
6474 | { | |
6475 | switch (reloc) | |
6476 | { | |
6477 | case BFD_RELOC_MIPS_HIGHEST: | |
6478 | case BFD_RELOC_MICROMIPS_HIGHEST: | |
6479 | *result = ((operand + 0x800080008000ull) >> 48) & 0xffff; | |
6480 | return TRUE; | |
6481 | ||
6482 | case BFD_RELOC_MIPS_HIGHER: | |
6483 | case BFD_RELOC_MICROMIPS_HIGHER: | |
6484 | *result = ((operand + 0x80008000ull) >> 32) & 0xffff; | |
6485 | return TRUE; | |
6486 | ||
6487 | case BFD_RELOC_HI16_S: | |
6488 | case BFD_RELOC_MICROMIPS_HI16_S: | |
6489 | case BFD_RELOC_MIPS16_HI16_S: | |
6490 | *result = ((operand + 0x8000) >> 16) & 0xffff; | |
6491 | return TRUE; | |
6492 | ||
6493 | case BFD_RELOC_HI16: | |
6494 | case BFD_RELOC_MICROMIPS_HI16: | |
6495 | case BFD_RELOC_MIPS16_HI16: | |
6496 | *result = (operand >> 16) & 0xffff; | |
6497 | return TRUE; | |
6498 | ||
6499 | case BFD_RELOC_LO16: | |
6500 | case BFD_RELOC_MICROMIPS_LO16: | |
6501 | case BFD_RELOC_MIPS16_LO16: | |
6502 | *result = operand & 0xffff; | |
6503 | return TRUE; | |
6504 | ||
6505 | case BFD_RELOC_UNUSED: | |
6506 | *result = operand; | |
6507 | return TRUE; | |
6508 | ||
6509 | default: | |
6510 | return FALSE; | |
6511 | } | |
6512 | } | |
6513 | ||
71400594 RS |
6514 | /* Output an instruction. IP is the instruction information. |
6515 | ADDRESS_EXPR is an operand of the instruction to be used with | |
df58fc94 RS |
6516 | RELOC_TYPE. EXPANSIONP is true if the instruction is part of |
6517 | a macro expansion. */ | |
71400594 RS |
6518 | |
6519 | static void | |
6520 | append_insn (struct mips_cl_insn *ip, expressionS *address_expr, | |
df58fc94 | 6521 | bfd_reloc_code_real_type *reloc_type, bfd_boolean expansionp) |
71400594 | 6522 | { |
14fe068b | 6523 | unsigned long prev_pinfo2, pinfo; |
71400594 | 6524 | bfd_boolean relaxed_branch = FALSE; |
a4e06468 | 6525 | enum append_method method; |
2309ddf2 | 6526 | bfd_boolean relax32; |
2b0c8b40 | 6527 | int branch_disp; |
71400594 | 6528 | |
2309ddf2 | 6529 | if (mips_fix_loongson2f && !HAVE_CODE_COMPRESSION) |
c67a084a NC |
6530 | fix_loongson2f (ip); |
6531 | ||
738f4d98 | 6532 | file_ase_mips16 |= mips_opts.mips16; |
df58fc94 | 6533 | file_ase_micromips |= mips_opts.micromips; |
738f4d98 | 6534 | |
df58fc94 | 6535 | prev_pinfo2 = history[0].insn_mo->pinfo2; |
71400594 | 6536 | pinfo = ip->insn_mo->pinfo; |
df58fc94 RS |
6537 | |
6538 | if (mips_opts.micromips | |
6539 | && !expansionp | |
6540 | && (((prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 | |
6541 | && micromips_insn_length (ip->insn_mo) != 2) | |
6542 | || ((prev_pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0 | |
6543 | && micromips_insn_length (ip->insn_mo) != 4))) | |
1661c76c | 6544 | as_warn (_("wrong size instruction in a %u-bit branch delay slot"), |
df58fc94 | 6545 | (prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 ? 16 : 32); |
71400594 | 6546 | |
15be625d CM |
6547 | if (address_expr == NULL) |
6548 | ip->complete_p = 1; | |
b886a2ab RS |
6549 | else if (reloc_type[0] <= BFD_RELOC_UNUSED |
6550 | && reloc_type[1] == BFD_RELOC_UNUSED | |
6551 | && reloc_type[2] == BFD_RELOC_UNUSED | |
15be625d CM |
6552 | && address_expr->X_op == O_constant) |
6553 | { | |
15be625d CM |
6554 | switch (*reloc_type) |
6555 | { | |
15be625d | 6556 | case BFD_RELOC_MIPS_JMP: |
df58fc94 RS |
6557 | { |
6558 | int shift; | |
6559 | ||
6560 | shift = mips_opts.micromips ? 1 : 2; | |
6561 | if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0) | |
6562 | as_bad (_("jump to misaligned address (0x%lx)"), | |
6563 | (unsigned long) address_expr->X_add_number); | |
6564 | ip->insn_opcode |= ((address_expr->X_add_number >> shift) | |
6565 | & 0x3ffffff); | |
335574df | 6566 | ip->complete_p = 1; |
df58fc94 | 6567 | } |
15be625d CM |
6568 | break; |
6569 | ||
6570 | case BFD_RELOC_MIPS16_JMP: | |
6571 | if ((address_expr->X_add_number & 3) != 0) | |
6572 | as_bad (_("jump to misaligned address (0x%lx)"), | |
6573 | (unsigned long) address_expr->X_add_number); | |
6574 | ip->insn_opcode |= | |
6575 | (((address_expr->X_add_number & 0x7c0000) << 3) | |
6576 | | ((address_expr->X_add_number & 0xf800000) >> 7) | |
6577 | | ((address_expr->X_add_number & 0x3fffc) >> 2)); | |
335574df | 6578 | ip->complete_p = 1; |
15be625d CM |
6579 | break; |
6580 | ||
6581 | case BFD_RELOC_16_PCREL_S2: | |
df58fc94 RS |
6582 | { |
6583 | int shift; | |
6584 | ||
6585 | shift = mips_opts.micromips ? 1 : 2; | |
6586 | if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0) | |
6587 | as_bad (_("branch to misaligned address (0x%lx)"), | |
6588 | (unsigned long) address_expr->X_add_number); | |
6589 | if (!mips_relax_branch) | |
6590 | { | |
6591 | if ((address_expr->X_add_number + (1 << (shift + 15))) | |
6592 | & ~((1 << (shift + 16)) - 1)) | |
6593 | as_bad (_("branch address range overflow (0x%lx)"), | |
6594 | (unsigned long) address_expr->X_add_number); | |
6595 | ip->insn_opcode |= ((address_expr->X_add_number >> shift) | |
6596 | & 0xffff); | |
6597 | } | |
df58fc94 | 6598 | } |
15be625d CM |
6599 | break; |
6600 | ||
6601 | default: | |
b886a2ab RS |
6602 | { |
6603 | offsetT value; | |
6604 | ||
6605 | if (calculate_reloc (*reloc_type, address_expr->X_add_number, | |
6606 | &value)) | |
6607 | { | |
6608 | ip->insn_opcode |= value & 0xffff; | |
6609 | ip->complete_p = 1; | |
6610 | } | |
6611 | } | |
6612 | break; | |
6613 | } | |
15be625d CM |
6614 | } |
6615 | ||
71400594 RS |
6616 | if (mips_relax.sequence != 2 && !mips_opts.noreorder) |
6617 | { | |
6618 | /* There are a lot of optimizations we could do that we don't. | |
6619 | In particular, we do not, in general, reorder instructions. | |
6620 | If you use gcc with optimization, it will reorder | |
6621 | instructions and generally do much more optimization then we | |
6622 | do here; repeating all that work in the assembler would only | |
6623 | benefit hand written assembly code, and does not seem worth | |
6624 | it. */ | |
6625 | int nops = (mips_optimize == 0 | |
932d1a1b RS |
6626 | ? nops_for_insn (0, history, NULL) |
6627 | : nops_for_insn_or_target (0, history, ip)); | |
71400594 | 6628 | if (nops > 0) |
252b5132 RH |
6629 | { |
6630 | fragS *old_frag; | |
6631 | unsigned long old_frag_offset; | |
6632 | int i; | |
252b5132 RH |
6633 | |
6634 | old_frag = frag_now; | |
6635 | old_frag_offset = frag_now_fix (); | |
6636 | ||
6637 | for (i = 0; i < nops; i++) | |
14fe068b RS |
6638 | add_fixed_insn (NOP_INSN); |
6639 | insert_into_history (0, nops, NOP_INSN); | |
252b5132 RH |
6640 | |
6641 | if (listing) | |
6642 | { | |
6643 | listing_prev_line (); | |
6644 | /* We may be at the start of a variant frag. In case we | |
6645 | are, make sure there is enough space for the frag | |
6646 | after the frags created by listing_prev_line. The | |
6647 | argument to frag_grow here must be at least as large | |
6648 | as the argument to all other calls to frag_grow in | |
6649 | this file. We don't have to worry about being in the | |
6650 | middle of a variant frag, because the variants insert | |
6651 | all needed nop instructions themselves. */ | |
6652 | frag_grow (40); | |
6653 | } | |
6654 | ||
462427c4 | 6655 | mips_move_text_labels (); |
252b5132 RH |
6656 | |
6657 | #ifndef NO_ECOFF_DEBUGGING | |
6658 | if (ECOFF_DEBUGGING) | |
6659 | ecoff_fix_loc (old_frag, old_frag_offset); | |
6660 | #endif | |
6661 | } | |
71400594 RS |
6662 | } |
6663 | else if (mips_relax.sequence != 2 && prev_nop_frag != NULL) | |
6664 | { | |
932d1a1b RS |
6665 | int nops; |
6666 | ||
6667 | /* Work out how many nops in prev_nop_frag are needed by IP, | |
6668 | ignoring hazards generated by the first prev_nop_frag_since | |
6669 | instructions. */ | |
6670 | nops = nops_for_insn_or_target (prev_nop_frag_since, history, ip); | |
9c2799c2 | 6671 | gas_assert (nops <= prev_nop_frag_holds); |
252b5132 | 6672 | |
71400594 RS |
6673 | /* Enforce NOPS as a minimum. */ |
6674 | if (nops > prev_nop_frag_required) | |
6675 | prev_nop_frag_required = nops; | |
252b5132 | 6676 | |
71400594 RS |
6677 | if (prev_nop_frag_holds == prev_nop_frag_required) |
6678 | { | |
6679 | /* Settle for the current number of nops. Update the history | |
6680 | accordingly (for the benefit of any future .set reorder code). */ | |
6681 | prev_nop_frag = NULL; | |
6682 | insert_into_history (prev_nop_frag_since, | |
6683 | prev_nop_frag_holds, NOP_INSN); | |
6684 | } | |
6685 | else | |
6686 | { | |
6687 | /* Allow this instruction to replace one of the nops that was | |
6688 | tentatively added to prev_nop_frag. */ | |
df58fc94 | 6689 | prev_nop_frag->fr_fix -= NOP_INSN_SIZE; |
71400594 RS |
6690 | prev_nop_frag_holds--; |
6691 | prev_nop_frag_since++; | |
252b5132 RH |
6692 | } |
6693 | } | |
6694 | ||
e407c74b | 6695 | method = get_append_method (ip, address_expr, reloc_type); |
2b0c8b40 | 6696 | branch_disp = method == APPEND_SWAP ? insn_length (history) : 0; |
a4e06468 | 6697 | |
e410add4 RS |
6698 | dwarf2_emit_insn (0); |
6699 | /* We want MIPS16 and microMIPS debug info to use ISA-encoded addresses, | |
6700 | so "move" the instruction address accordingly. | |
6701 | ||
6702 | Also, it doesn't seem appropriate for the assembler to reorder .loc | |
6703 | entries. If this instruction is a branch that we are going to swap | |
6704 | with the previous instruction, the two instructions should be | |
6705 | treated as a unit, and the debug information for both instructions | |
6706 | should refer to the start of the branch sequence. Using the | |
6707 | current position is certainly wrong when swapping a 32-bit branch | |
6708 | and a 16-bit delay slot, since the current position would then be | |
6709 | in the middle of a branch. */ | |
6710 | dwarf2_move_insn ((HAVE_CODE_COMPRESSION ? 1 : 0) - branch_disp); | |
58e2ea4d | 6711 | |
df58fc94 RS |
6712 | relax32 = (mips_relax_branch |
6713 | /* Don't try branch relaxation within .set nomacro, or within | |
6714 | .set noat if we use $at for PIC computations. If it turns | |
6715 | out that the branch was out-of-range, we'll get an error. */ | |
6716 | && !mips_opts.warn_about_macros | |
6717 | && (mips_opts.at || mips_pic == NO_PIC) | |
3bf0dbfb MR |
6718 | /* Don't relax BPOSGE32/64 or BC1ANY2T/F and BC1ANY4T/F |
6719 | as they have no complementing branches. */ | |
6720 | && !(ip->insn_mo->ase & (ASE_MIPS3D | ASE_DSP64 | ASE_DSP))); | |
df58fc94 RS |
6721 | |
6722 | if (!HAVE_CODE_COMPRESSION | |
6723 | && address_expr | |
6724 | && relax32 | |
0b25d3e6 | 6725 | && *reloc_type == BFD_RELOC_16_PCREL_S2 |
11625dd8 | 6726 | && delayed_branch_p (ip)) |
4a6a3df4 | 6727 | { |
895921c9 | 6728 | relaxed_branch = TRUE; |
1e915849 RS |
6729 | add_relaxed_insn (ip, (relaxed_branch_length |
6730 | (NULL, NULL, | |
11625dd8 RS |
6731 | uncond_branch_p (ip) ? -1 |
6732 | : branch_likely_p (ip) ? 1 | |
1e915849 RS |
6733 | : 0)), 4, |
6734 | RELAX_BRANCH_ENCODE | |
66b3e8da | 6735 | (AT, |
11625dd8 RS |
6736 | uncond_branch_p (ip), |
6737 | branch_likely_p (ip), | |
1e915849 RS |
6738 | pinfo & INSN_WRITE_GPR_31, |
6739 | 0), | |
6740 | address_expr->X_add_symbol, | |
6741 | address_expr->X_add_number); | |
4a6a3df4 AO |
6742 | *reloc_type = BFD_RELOC_UNUSED; |
6743 | } | |
df58fc94 RS |
6744 | else if (mips_opts.micromips |
6745 | && address_expr | |
6746 | && ((relax32 && *reloc_type == BFD_RELOC_16_PCREL_S2) | |
6747 | || *reloc_type > BFD_RELOC_UNUSED) | |
40209cad MR |
6748 | && (delayed_branch_p (ip) || compact_branch_p (ip)) |
6749 | /* Don't try branch relaxation when users specify | |
6750 | 16-bit/32-bit instructions. */ | |
6751 | && !forced_insn_length) | |
df58fc94 RS |
6752 | { |
6753 | bfd_boolean relax16 = *reloc_type > BFD_RELOC_UNUSED; | |
6754 | int type = relax16 ? *reloc_type - BFD_RELOC_UNUSED : 0; | |
11625dd8 RS |
6755 | int uncond = uncond_branch_p (ip) ? -1 : 0; |
6756 | int compact = compact_branch_p (ip); | |
df58fc94 RS |
6757 | int al = pinfo & INSN_WRITE_GPR_31; |
6758 | int length32; | |
6759 | ||
6760 | gas_assert (address_expr != NULL); | |
6761 | gas_assert (!mips_relax.sequence); | |
6762 | ||
2b0c8b40 | 6763 | relaxed_branch = TRUE; |
df58fc94 RS |
6764 | length32 = relaxed_micromips_32bit_branch_length (NULL, NULL, uncond); |
6765 | add_relaxed_insn (ip, relax32 ? length32 : 4, relax16 ? 2 : 4, | |
40209cad MR |
6766 | RELAX_MICROMIPS_ENCODE (type, AT, uncond, compact, al, |
6767 | relax32, 0, 0), | |
df58fc94 RS |
6768 | address_expr->X_add_symbol, |
6769 | address_expr->X_add_number); | |
6770 | *reloc_type = BFD_RELOC_UNUSED; | |
6771 | } | |
6772 | else if (mips_opts.mips16 && *reloc_type > BFD_RELOC_UNUSED) | |
252b5132 RH |
6773 | { |
6774 | /* We need to set up a variant frag. */ | |
df58fc94 | 6775 | gas_assert (address_expr != NULL); |
1e915849 RS |
6776 | add_relaxed_insn (ip, 4, 0, |
6777 | RELAX_MIPS16_ENCODE | |
6778 | (*reloc_type - BFD_RELOC_UNUSED, | |
df58fc94 | 6779 | forced_insn_length == 2, forced_insn_length == 4, |
11625dd8 | 6780 | delayed_branch_p (&history[0]), |
1e915849 RS |
6781 | history[0].mips16_absolute_jump_p), |
6782 | make_expr_symbol (address_expr), 0); | |
252b5132 | 6783 | } |
5c04167a | 6784 | else if (mips_opts.mips16 && insn_length (ip) == 2) |
9497f5ac | 6785 | { |
11625dd8 | 6786 | if (!delayed_branch_p (ip)) |
b8ee1a6e DU |
6787 | /* Make sure there is enough room to swap this instruction with |
6788 | a following jump instruction. */ | |
6789 | frag_grow (6); | |
1e915849 | 6790 | add_fixed_insn (ip); |
252b5132 RH |
6791 | } |
6792 | else | |
6793 | { | |
6794 | if (mips_opts.mips16 | |
6795 | && mips_opts.noreorder | |
11625dd8 | 6796 | && delayed_branch_p (&history[0])) |
252b5132 RH |
6797 | as_warn (_("extended instruction in delay slot")); |
6798 | ||
4d7206a2 RS |
6799 | if (mips_relax.sequence) |
6800 | { | |
6801 | /* If we've reached the end of this frag, turn it into a variant | |
6802 | frag and record the information for the instructions we've | |
6803 | written so far. */ | |
6804 | if (frag_room () < 4) | |
6805 | relax_close_frag (); | |
df58fc94 | 6806 | mips_relax.sizes[mips_relax.sequence - 1] += insn_length (ip); |
4d7206a2 RS |
6807 | } |
6808 | ||
584892a6 | 6809 | if (mips_relax.sequence != 2) |
df58fc94 RS |
6810 | { |
6811 | if (mips_macro_warning.first_insn_sizes[0] == 0) | |
6812 | mips_macro_warning.first_insn_sizes[0] = insn_length (ip); | |
6813 | mips_macro_warning.sizes[0] += insn_length (ip); | |
6814 | mips_macro_warning.insns[0]++; | |
6815 | } | |
584892a6 | 6816 | if (mips_relax.sequence != 1) |
df58fc94 RS |
6817 | { |
6818 | if (mips_macro_warning.first_insn_sizes[1] == 0) | |
6819 | mips_macro_warning.first_insn_sizes[1] = insn_length (ip); | |
6820 | mips_macro_warning.sizes[1] += insn_length (ip); | |
6821 | mips_macro_warning.insns[1]++; | |
6822 | } | |
584892a6 | 6823 | |
1e915849 RS |
6824 | if (mips_opts.mips16) |
6825 | { | |
6826 | ip->fixed_p = 1; | |
6827 | ip->mips16_absolute_jump_p = (*reloc_type == BFD_RELOC_MIPS16_JMP); | |
6828 | } | |
6829 | add_fixed_insn (ip); | |
252b5132 RH |
6830 | } |
6831 | ||
9fe77896 | 6832 | if (!ip->complete_p && *reloc_type < BFD_RELOC_UNUSED) |
252b5132 | 6833 | { |
df58fc94 | 6834 | bfd_reloc_code_real_type final_type[3]; |
2309ddf2 | 6835 | reloc_howto_type *howto0; |
9fe77896 RS |
6836 | reloc_howto_type *howto; |
6837 | int i; | |
34ce925e | 6838 | |
df58fc94 RS |
6839 | /* Perform any necessary conversion to microMIPS relocations |
6840 | and find out how many relocations there actually are. */ | |
6841 | for (i = 0; i < 3 && reloc_type[i] != BFD_RELOC_UNUSED; i++) | |
6842 | final_type[i] = micromips_map_reloc (reloc_type[i]); | |
6843 | ||
9fe77896 RS |
6844 | /* In a compound relocation, it is the final (outermost) |
6845 | operator that determines the relocated field. */ | |
2309ddf2 | 6846 | howto = howto0 = bfd_reloc_type_lookup (stdoutput, final_type[i - 1]); |
e8044f35 RS |
6847 | if (!howto) |
6848 | abort (); | |
2309ddf2 MR |
6849 | |
6850 | if (i > 1) | |
6851 | howto0 = bfd_reloc_type_lookup (stdoutput, final_type[0]); | |
9fe77896 RS |
6852 | ip->fixp[0] = fix_new_exp (ip->frag, ip->where, |
6853 | bfd_get_reloc_size (howto), | |
6854 | address_expr, | |
2309ddf2 MR |
6855 | howto0 && howto0->pc_relative, |
6856 | final_type[0]); | |
9fe77896 RS |
6857 | |
6858 | /* Tag symbols that have a R_MIPS16_26 relocation against them. */ | |
2309ddf2 | 6859 | if (final_type[0] == BFD_RELOC_MIPS16_JMP && ip->fixp[0]->fx_addsy) |
9fe77896 RS |
6860 | *symbol_get_tc (ip->fixp[0]->fx_addsy) = 1; |
6861 | ||
6862 | /* These relocations can have an addend that won't fit in | |
6863 | 4 octets for 64bit assembly. */ | |
bad1aba3 | 6864 | if (GPR_SIZE == 64 |
9fe77896 RS |
6865 | && ! howto->partial_inplace |
6866 | && (reloc_type[0] == BFD_RELOC_16 | |
6867 | || reloc_type[0] == BFD_RELOC_32 | |
6868 | || reloc_type[0] == BFD_RELOC_MIPS_JMP | |
6869 | || reloc_type[0] == BFD_RELOC_GPREL16 | |
6870 | || reloc_type[0] == BFD_RELOC_MIPS_LITERAL | |
6871 | || reloc_type[0] == BFD_RELOC_GPREL32 | |
6872 | || reloc_type[0] == BFD_RELOC_64 | |
6873 | || reloc_type[0] == BFD_RELOC_CTOR | |
6874 | || reloc_type[0] == BFD_RELOC_MIPS_SUB | |
6875 | || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST | |
6876 | || reloc_type[0] == BFD_RELOC_MIPS_HIGHER | |
6877 | || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP | |
6878 | || reloc_type[0] == BFD_RELOC_MIPS_REL16 | |
6879 | || reloc_type[0] == BFD_RELOC_MIPS_RELGOT | |
6880 | || reloc_type[0] == BFD_RELOC_MIPS16_GPREL | |
6881 | || hi16_reloc_p (reloc_type[0]) | |
6882 | || lo16_reloc_p (reloc_type[0]))) | |
6883 | ip->fixp[0]->fx_no_overflow = 1; | |
6884 | ||
ddaf2c41 MR |
6885 | /* These relocations can have an addend that won't fit in 2 octets. */ |
6886 | if (reloc_type[0] == BFD_RELOC_MICROMIPS_7_PCREL_S1 | |
6887 | || reloc_type[0] == BFD_RELOC_MICROMIPS_10_PCREL_S1) | |
6888 | ip->fixp[0]->fx_no_overflow = 1; | |
6889 | ||
9fe77896 RS |
6890 | if (mips_relax.sequence) |
6891 | { | |
6892 | if (mips_relax.first_fixup == 0) | |
6893 | mips_relax.first_fixup = ip->fixp[0]; | |
6894 | } | |
6895 | else if (reloc_needs_lo_p (*reloc_type)) | |
6896 | { | |
6897 | struct mips_hi_fixup *hi_fixup; | |
6898 | ||
6899 | /* Reuse the last entry if it already has a matching %lo. */ | |
6900 | hi_fixup = mips_hi_fixup_list; | |
6901 | if (hi_fixup == 0 | |
6902 | || !fixup_has_matching_lo_p (hi_fixup->fixp)) | |
4d7206a2 | 6903 | { |
9fe77896 RS |
6904 | hi_fixup = ((struct mips_hi_fixup *) |
6905 | xmalloc (sizeof (struct mips_hi_fixup))); | |
6906 | hi_fixup->next = mips_hi_fixup_list; | |
6907 | mips_hi_fixup_list = hi_fixup; | |
4d7206a2 | 6908 | } |
9fe77896 RS |
6909 | hi_fixup->fixp = ip->fixp[0]; |
6910 | hi_fixup->seg = now_seg; | |
6911 | } | |
252b5132 | 6912 | |
9fe77896 RS |
6913 | /* Add fixups for the second and third relocations, if given. |
6914 | Note that the ABI allows the second relocation to be | |
6915 | against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the | |
6916 | moment we only use RSS_UNDEF, but we could add support | |
6917 | for the others if it ever becomes necessary. */ | |
6918 | for (i = 1; i < 3; i++) | |
6919 | if (reloc_type[i] != BFD_RELOC_UNUSED) | |
6920 | { | |
6921 | ip->fixp[i] = fix_new (ip->frag, ip->where, | |
6922 | ip->fixp[0]->fx_size, NULL, 0, | |
df58fc94 | 6923 | FALSE, final_type[i]); |
f6688943 | 6924 | |
9fe77896 RS |
6925 | /* Use fx_tcbit to mark compound relocs. */ |
6926 | ip->fixp[0]->fx_tcbit = 1; | |
6927 | ip->fixp[i]->fx_tcbit = 1; | |
6928 | } | |
252b5132 | 6929 | } |
1e915849 | 6930 | install_insn (ip); |
252b5132 RH |
6931 | |
6932 | /* Update the register mask information. */ | |
4c260379 RS |
6933 | mips_gprmask |= gpr_read_mask (ip) | gpr_write_mask (ip); |
6934 | mips_cprmask[1] |= fpr_read_mask (ip) | fpr_write_mask (ip); | |
252b5132 | 6935 | |
a4e06468 | 6936 | switch (method) |
252b5132 | 6937 | { |
a4e06468 RS |
6938 | case APPEND_ADD: |
6939 | insert_into_history (0, 1, ip); | |
6940 | break; | |
6941 | ||
6942 | case APPEND_ADD_WITH_NOP: | |
14fe068b RS |
6943 | { |
6944 | struct mips_cl_insn *nop; | |
6945 | ||
6946 | insert_into_history (0, 1, ip); | |
6947 | nop = get_delay_slot_nop (ip); | |
6948 | add_fixed_insn (nop); | |
6949 | insert_into_history (0, 1, nop); | |
6950 | if (mips_relax.sequence) | |
6951 | mips_relax.sizes[mips_relax.sequence - 1] += insn_length (nop); | |
6952 | } | |
a4e06468 RS |
6953 | break; |
6954 | ||
6955 | case APPEND_ADD_COMPACT: | |
6956 | /* Convert MIPS16 jr/jalr into a "compact" jump. */ | |
6957 | gas_assert (mips_opts.mips16); | |
6958 | ip->insn_opcode |= 0x0080; | |
6959 | find_altered_mips16_opcode (ip); | |
6960 | install_insn (ip); | |
6961 | insert_into_history (0, 1, ip); | |
6962 | break; | |
6963 | ||
6964 | case APPEND_SWAP: | |
6965 | { | |
6966 | struct mips_cl_insn delay = history[0]; | |
6967 | if (mips_opts.mips16) | |
6968 | { | |
6969 | know (delay.frag == ip->frag); | |
6970 | move_insn (ip, delay.frag, delay.where); | |
6971 | move_insn (&delay, ip->frag, ip->where + insn_length (ip)); | |
6972 | } | |
464ab0e5 | 6973 | else if (relaxed_branch || delay.frag != ip->frag) |
a4e06468 RS |
6974 | { |
6975 | /* Add the delay slot instruction to the end of the | |
6976 | current frag and shrink the fixed part of the | |
6977 | original frag. If the branch occupies the tail of | |
6978 | the latter, move it backwards to cover the gap. */ | |
2b0c8b40 | 6979 | delay.frag->fr_fix -= branch_disp; |
a4e06468 | 6980 | if (delay.frag == ip->frag) |
2b0c8b40 | 6981 | move_insn (ip, ip->frag, ip->where - branch_disp); |
a4e06468 RS |
6982 | add_fixed_insn (&delay); |
6983 | } | |
6984 | else | |
6985 | { | |
2b0c8b40 MR |
6986 | move_insn (&delay, ip->frag, |
6987 | ip->where - branch_disp + insn_length (ip)); | |
a4e06468 RS |
6988 | move_insn (ip, history[0].frag, history[0].where); |
6989 | } | |
6990 | history[0] = *ip; | |
6991 | delay.fixed_p = 1; | |
6992 | insert_into_history (0, 1, &delay); | |
6993 | } | |
6994 | break; | |
252b5132 RH |
6995 | } |
6996 | ||
13408f1e | 6997 | /* If we have just completed an unconditional branch, clear the history. */ |
11625dd8 RS |
6998 | if ((delayed_branch_p (&history[1]) && uncond_branch_p (&history[1])) |
6999 | || (compact_branch_p (&history[0]) && uncond_branch_p (&history[0]))) | |
e407c74b NC |
7000 | { |
7001 | unsigned int i; | |
7002 | ||
79850f26 | 7003 | mips_no_prev_insn (); |
13408f1e | 7004 | |
e407c74b | 7005 | for (i = 0; i < ARRAY_SIZE (history); i++) |
79850f26 | 7006 | history[i].cleared_p = 1; |
e407c74b NC |
7007 | } |
7008 | ||
df58fc94 RS |
7009 | /* We need to emit a label at the end of branch-likely macros. */ |
7010 | if (emit_branch_likely_macro) | |
7011 | { | |
7012 | emit_branch_likely_macro = FALSE; | |
7013 | micromips_add_label (); | |
7014 | } | |
7015 | ||
252b5132 RH |
7016 | /* We just output an insn, so the next one doesn't have a label. */ |
7017 | mips_clear_insn_labels (); | |
252b5132 RH |
7018 | } |
7019 | ||
e407c74b NC |
7020 | /* Forget that there was any previous instruction or label. |
7021 | When BRANCH is true, the branch history is also flushed. */ | |
252b5132 RH |
7022 | |
7023 | static void | |
7d10b47d | 7024 | mips_no_prev_insn (void) |
252b5132 | 7025 | { |
7d10b47d RS |
7026 | prev_nop_frag = NULL; |
7027 | insert_into_history (0, ARRAY_SIZE (history), NOP_INSN); | |
252b5132 RH |
7028 | mips_clear_insn_labels (); |
7029 | } | |
7030 | ||
7d10b47d RS |
7031 | /* This function must be called before we emit something other than |
7032 | instructions. It is like mips_no_prev_insn except that it inserts | |
7033 | any NOPS that might be needed by previous instructions. */ | |
252b5132 | 7034 | |
7d10b47d RS |
7035 | void |
7036 | mips_emit_delays (void) | |
252b5132 RH |
7037 | { |
7038 | if (! mips_opts.noreorder) | |
7039 | { | |
932d1a1b | 7040 | int nops = nops_for_insn (0, history, NULL); |
252b5132 RH |
7041 | if (nops > 0) |
7042 | { | |
7d10b47d RS |
7043 | while (nops-- > 0) |
7044 | add_fixed_insn (NOP_INSN); | |
462427c4 | 7045 | mips_move_text_labels (); |
7d10b47d RS |
7046 | } |
7047 | } | |
7048 | mips_no_prev_insn (); | |
7049 | } | |
7050 | ||
7051 | /* Start a (possibly nested) noreorder block. */ | |
7052 | ||
7053 | static void | |
7054 | start_noreorder (void) | |
7055 | { | |
7056 | if (mips_opts.noreorder == 0) | |
7057 | { | |
7058 | unsigned int i; | |
7059 | int nops; | |
7060 | ||
7061 | /* None of the instructions before the .set noreorder can be moved. */ | |
7062 | for (i = 0; i < ARRAY_SIZE (history); i++) | |
7063 | history[i].fixed_p = 1; | |
7064 | ||
7065 | /* Insert any nops that might be needed between the .set noreorder | |
7066 | block and the previous instructions. We will later remove any | |
7067 | nops that turn out not to be needed. */ | |
932d1a1b | 7068 | nops = nops_for_insn (0, history, NULL); |
7d10b47d RS |
7069 | if (nops > 0) |
7070 | { | |
7071 | if (mips_optimize != 0) | |
252b5132 RH |
7072 | { |
7073 | /* Record the frag which holds the nop instructions, so | |
7074 | that we can remove them if we don't need them. */ | |
df58fc94 | 7075 | frag_grow (nops * NOP_INSN_SIZE); |
252b5132 RH |
7076 | prev_nop_frag = frag_now; |
7077 | prev_nop_frag_holds = nops; | |
7078 | prev_nop_frag_required = 0; | |
7079 | prev_nop_frag_since = 0; | |
7080 | } | |
7081 | ||
7082 | for (; nops > 0; --nops) | |
1e915849 | 7083 | add_fixed_insn (NOP_INSN); |
252b5132 | 7084 | |
7d10b47d RS |
7085 | /* Move on to a new frag, so that it is safe to simply |
7086 | decrease the size of prev_nop_frag. */ | |
7087 | frag_wane (frag_now); | |
7088 | frag_new (0); | |
462427c4 | 7089 | mips_move_text_labels (); |
252b5132 | 7090 | } |
df58fc94 | 7091 | mips_mark_labels (); |
7d10b47d | 7092 | mips_clear_insn_labels (); |
252b5132 | 7093 | } |
7d10b47d RS |
7094 | mips_opts.noreorder++; |
7095 | mips_any_noreorder = 1; | |
7096 | } | |
252b5132 | 7097 | |
7d10b47d | 7098 | /* End a nested noreorder block. */ |
252b5132 | 7099 | |
7d10b47d RS |
7100 | static void |
7101 | end_noreorder (void) | |
7102 | { | |
7103 | mips_opts.noreorder--; | |
7104 | if (mips_opts.noreorder == 0 && prev_nop_frag != NULL) | |
7105 | { | |
7106 | /* Commit to inserting prev_nop_frag_required nops and go back to | |
7107 | handling nop insertion the .set reorder way. */ | |
7108 | prev_nop_frag->fr_fix -= ((prev_nop_frag_holds - prev_nop_frag_required) | |
df58fc94 | 7109 | * NOP_INSN_SIZE); |
7d10b47d RS |
7110 | insert_into_history (prev_nop_frag_since, |
7111 | prev_nop_frag_required, NOP_INSN); | |
7112 | prev_nop_frag = NULL; | |
7113 | } | |
252b5132 RH |
7114 | } |
7115 | ||
97d87491 RS |
7116 | /* Sign-extend 32-bit mode constants that have bit 31 set and all |
7117 | higher bits unset. */ | |
7118 | ||
7119 | static void | |
7120 | normalize_constant_expr (expressionS *ex) | |
7121 | { | |
7122 | if (ex->X_op == O_constant | |
7123 | && IS_ZEXT_32BIT_NUM (ex->X_add_number)) | |
7124 | ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000) | |
7125 | - 0x80000000); | |
7126 | } | |
7127 | ||
7128 | /* Sign-extend 32-bit mode address offsets that have bit 31 set and | |
7129 | all higher bits unset. */ | |
7130 | ||
7131 | static void | |
7132 | normalize_address_expr (expressionS *ex) | |
7133 | { | |
7134 | if (((ex->X_op == O_constant && HAVE_32BIT_ADDRESSES) | |
7135 | || (ex->X_op == O_symbol && HAVE_32BIT_SYMBOLS)) | |
7136 | && IS_ZEXT_32BIT_NUM (ex->X_add_number)) | |
7137 | ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000) | |
7138 | - 0x80000000); | |
7139 | } | |
7140 | ||
7141 | /* Try to match TOKENS against OPCODE, storing the result in INSN. | |
7142 | Return true if the match was successful. | |
7143 | ||
7144 | OPCODE_EXTRA is a value that should be ORed into the opcode | |
7145 | (used for VU0 channel suffixes, etc.). MORE_ALTS is true if | |
7146 | there are more alternatives after OPCODE and SOFT_MATCH is | |
7147 | as for mips_arg_info. */ | |
7148 | ||
7149 | static bfd_boolean | |
7150 | match_insn (struct mips_cl_insn *insn, const struct mips_opcode *opcode, | |
7151 | struct mips_operand_token *tokens, unsigned int opcode_extra, | |
60f20e8b | 7152 | bfd_boolean lax_match, bfd_boolean complete_p) |
97d87491 RS |
7153 | { |
7154 | const char *args; | |
7155 | struct mips_arg_info arg; | |
7156 | const struct mips_operand *operand; | |
7157 | char c; | |
7158 | ||
7159 | imm_expr.X_op = O_absent; | |
97d87491 RS |
7160 | offset_expr.X_op = O_absent; |
7161 | offset_reloc[0] = BFD_RELOC_UNUSED; | |
7162 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
7163 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
7164 | ||
7165 | create_insn (insn, opcode); | |
60f20e8b RS |
7166 | /* When no opcode suffix is specified, assume ".xyzw". */ |
7167 | if ((opcode->pinfo2 & INSN2_VU0_CHANNEL_SUFFIX) != 0 && opcode_extra == 0) | |
7168 | insn->insn_opcode |= 0xf << mips_vu0_channel_mask.lsb; | |
7169 | else | |
7170 | insn->insn_opcode |= opcode_extra; | |
97d87491 RS |
7171 | memset (&arg, 0, sizeof (arg)); |
7172 | arg.insn = insn; | |
7173 | arg.token = tokens; | |
7174 | arg.argnum = 1; | |
7175 | arg.last_regno = ILLEGAL_REG; | |
7176 | arg.dest_regno = ILLEGAL_REG; | |
60f20e8b | 7177 | arg.lax_match = lax_match; |
97d87491 RS |
7178 | for (args = opcode->args;; ++args) |
7179 | { | |
7180 | if (arg.token->type == OT_END) | |
7181 | { | |
7182 | /* Handle unary instructions in which only one operand is given. | |
7183 | The source is then the same as the destination. */ | |
7184 | if (arg.opnum == 1 && *args == ',') | |
7185 | { | |
7186 | operand = (mips_opts.micromips | |
7187 | ? decode_micromips_operand (args + 1) | |
7188 | : decode_mips_operand (args + 1)); | |
7189 | if (operand && mips_optional_operand_p (operand)) | |
7190 | { | |
7191 | arg.token = tokens; | |
7192 | arg.argnum = 1; | |
7193 | continue; | |
7194 | } | |
7195 | } | |
7196 | ||
7197 | /* Treat elided base registers as $0. */ | |
7198 | if (strcmp (args, "(b)") == 0) | |
7199 | args += 3; | |
7200 | ||
7201 | if (args[0] == '+') | |
7202 | switch (args[1]) | |
7203 | { | |
7204 | case 'K': | |
7205 | case 'N': | |
7206 | /* The register suffix is optional. */ | |
7207 | args += 2; | |
7208 | break; | |
7209 | } | |
7210 | ||
7211 | /* Fail the match if there were too few operands. */ | |
7212 | if (*args) | |
7213 | return FALSE; | |
7214 | ||
7215 | /* Successful match. */ | |
60f20e8b RS |
7216 | if (!complete_p) |
7217 | return TRUE; | |
e3de51ce | 7218 | clear_insn_error (); |
97d87491 RS |
7219 | if (arg.dest_regno == arg.last_regno |
7220 | && strncmp (insn->insn_mo->name, "jalr", 4) == 0) | |
7221 | { | |
7222 | if (arg.opnum == 2) | |
e3de51ce | 7223 | set_insn_error |
1661c76c | 7224 | (0, _("source and destination must be different")); |
97d87491 | 7225 | else if (arg.last_regno == 31) |
e3de51ce | 7226 | set_insn_error |
1661c76c | 7227 | (0, _("a destination register must be supplied")); |
97d87491 | 7228 | } |
173d3447 CF |
7229 | else if (arg.last_regno == 31 |
7230 | && (strncmp (insn->insn_mo->name, "bltzal", 6) == 0 | |
7231 | || strncmp (insn->insn_mo->name, "bgezal", 6) == 0)) | |
7232 | set_insn_error (0, _("the source register must not be $31")); | |
97d87491 RS |
7233 | check_completed_insn (&arg); |
7234 | return TRUE; | |
7235 | } | |
7236 | ||
7237 | /* Fail the match if the line has too many operands. */ | |
7238 | if (*args == 0) | |
7239 | return FALSE; | |
7240 | ||
7241 | /* Handle characters that need to match exactly. */ | |
7242 | if (*args == '(' || *args == ')' || *args == ',') | |
7243 | { | |
7244 | if (match_char (&arg, *args)) | |
7245 | continue; | |
7246 | return FALSE; | |
7247 | } | |
7248 | if (*args == '#') | |
7249 | { | |
7250 | ++args; | |
7251 | if (arg.token->type == OT_DOUBLE_CHAR | |
7252 | && arg.token->u.ch == *args) | |
7253 | { | |
7254 | ++arg.token; | |
7255 | continue; | |
7256 | } | |
7257 | return FALSE; | |
7258 | } | |
7259 | ||
7260 | /* Handle special macro operands. Work out the properties of | |
7261 | other operands. */ | |
7262 | arg.opnum += 1; | |
97d87491 RS |
7263 | switch (*args) |
7264 | { | |
7265 | case '+': | |
7266 | switch (args[1]) | |
7267 | { | |
97d87491 RS |
7268 | case 'i': |
7269 | *offset_reloc = BFD_RELOC_MIPS_JMP; | |
7270 | break; | |
7271 | } | |
7272 | break; | |
7273 | ||
97d87491 | 7274 | case 'I': |
1a00e612 RS |
7275 | if (!match_const_int (&arg, &imm_expr.X_add_number)) |
7276 | return FALSE; | |
7277 | imm_expr.X_op = O_constant; | |
bad1aba3 | 7278 | if (GPR_SIZE == 32) |
97d87491 RS |
7279 | normalize_constant_expr (&imm_expr); |
7280 | continue; | |
7281 | ||
7282 | case 'A': | |
7283 | if (arg.token->type == OT_CHAR && arg.token->u.ch == '(') | |
7284 | { | |
7285 | /* Assume that the offset has been elided and that what | |
7286 | we saw was a base register. The match will fail later | |
7287 | if that assumption turns out to be wrong. */ | |
7288 | offset_expr.X_op = O_constant; | |
7289 | offset_expr.X_add_number = 0; | |
7290 | } | |
97d87491 | 7291 | else |
1a00e612 RS |
7292 | { |
7293 | if (!match_expression (&arg, &offset_expr, offset_reloc)) | |
7294 | return FALSE; | |
7295 | normalize_address_expr (&offset_expr); | |
7296 | } | |
97d87491 RS |
7297 | continue; |
7298 | ||
7299 | case 'F': | |
7300 | if (!match_float_constant (&arg, &imm_expr, &offset_expr, | |
7301 | 8, TRUE)) | |
1a00e612 | 7302 | return FALSE; |
97d87491 RS |
7303 | continue; |
7304 | ||
7305 | case 'L': | |
7306 | if (!match_float_constant (&arg, &imm_expr, &offset_expr, | |
7307 | 8, FALSE)) | |
1a00e612 | 7308 | return FALSE; |
97d87491 RS |
7309 | continue; |
7310 | ||
7311 | case 'f': | |
7312 | if (!match_float_constant (&arg, &imm_expr, &offset_expr, | |
7313 | 4, TRUE)) | |
1a00e612 | 7314 | return FALSE; |
97d87491 RS |
7315 | continue; |
7316 | ||
7317 | case 'l': | |
7318 | if (!match_float_constant (&arg, &imm_expr, &offset_expr, | |
7319 | 4, FALSE)) | |
1a00e612 | 7320 | return FALSE; |
97d87491 RS |
7321 | continue; |
7322 | ||
97d87491 RS |
7323 | case 'p': |
7324 | *offset_reloc = BFD_RELOC_16_PCREL_S2; | |
7325 | break; | |
7326 | ||
7327 | case 'a': | |
7328 | *offset_reloc = BFD_RELOC_MIPS_JMP; | |
7329 | break; | |
7330 | ||
7331 | case 'm': | |
7332 | gas_assert (mips_opts.micromips); | |
7333 | c = args[1]; | |
7334 | switch (c) | |
7335 | { | |
7336 | case 'D': | |
7337 | case 'E': | |
7338 | if (!forced_insn_length) | |
7339 | *offset_reloc = (int) BFD_RELOC_UNUSED + c; | |
7340 | else if (c == 'D') | |
7341 | *offset_reloc = BFD_RELOC_MICROMIPS_10_PCREL_S1; | |
7342 | else | |
7343 | *offset_reloc = BFD_RELOC_MICROMIPS_7_PCREL_S1; | |
7344 | break; | |
7345 | } | |
7346 | break; | |
7347 | } | |
7348 | ||
7349 | operand = (mips_opts.micromips | |
7350 | ? decode_micromips_operand (args) | |
7351 | : decode_mips_operand (args)); | |
7352 | if (!operand) | |
7353 | abort (); | |
7354 | ||
7355 | /* Skip prefixes. */ | |
7356 | if (*args == '+' || *args == 'm') | |
7357 | args++; | |
7358 | ||
7359 | if (mips_optional_operand_p (operand) | |
7360 | && args[1] == ',' | |
7361 | && (arg.token[0].type != OT_REG | |
7362 | || arg.token[1].type == OT_END)) | |
7363 | { | |
7364 | /* Assume that the register has been elided and is the | |
7365 | same as the first operand. */ | |
7366 | arg.token = tokens; | |
7367 | arg.argnum = 1; | |
7368 | } | |
7369 | ||
7370 | if (!match_operand (&arg, operand)) | |
7371 | return FALSE; | |
7372 | } | |
7373 | } | |
7374 | ||
7375 | /* Like match_insn, but for MIPS16. */ | |
7376 | ||
7377 | static bfd_boolean | |
7378 | match_mips16_insn (struct mips_cl_insn *insn, const struct mips_opcode *opcode, | |
1a00e612 | 7379 | struct mips_operand_token *tokens) |
97d87491 RS |
7380 | { |
7381 | const char *args; | |
7382 | const struct mips_operand *operand; | |
7383 | const struct mips_operand *ext_operand; | |
7384 | struct mips_arg_info arg; | |
7385 | int relax_char; | |
7386 | ||
7387 | create_insn (insn, opcode); | |
7388 | imm_expr.X_op = O_absent; | |
97d87491 RS |
7389 | offset_expr.X_op = O_absent; |
7390 | offset_reloc[0] = BFD_RELOC_UNUSED; | |
7391 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
7392 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
7393 | relax_char = 0; | |
7394 | ||
7395 | memset (&arg, 0, sizeof (arg)); | |
7396 | arg.insn = insn; | |
7397 | arg.token = tokens; | |
7398 | arg.argnum = 1; | |
7399 | arg.last_regno = ILLEGAL_REG; | |
7400 | arg.dest_regno = ILLEGAL_REG; | |
97d87491 RS |
7401 | relax_char = 0; |
7402 | for (args = opcode->args;; ++args) | |
7403 | { | |
7404 | int c; | |
7405 | ||
7406 | if (arg.token->type == OT_END) | |
7407 | { | |
7408 | offsetT value; | |
7409 | ||
7410 | /* Handle unary instructions in which only one operand is given. | |
7411 | The source is then the same as the destination. */ | |
7412 | if (arg.opnum == 1 && *args == ',') | |
7413 | { | |
7414 | operand = decode_mips16_operand (args[1], FALSE); | |
7415 | if (operand && mips_optional_operand_p (operand)) | |
7416 | { | |
7417 | arg.token = tokens; | |
7418 | arg.argnum = 1; | |
7419 | continue; | |
7420 | } | |
7421 | } | |
7422 | ||
7423 | /* Fail the match if there were too few operands. */ | |
7424 | if (*args) | |
7425 | return FALSE; | |
7426 | ||
7427 | /* Successful match. Stuff the immediate value in now, if | |
7428 | we can. */ | |
e3de51ce | 7429 | clear_insn_error (); |
97d87491 RS |
7430 | if (opcode->pinfo == INSN_MACRO) |
7431 | { | |
7432 | gas_assert (relax_char == 0 || relax_char == 'p'); | |
7433 | gas_assert (*offset_reloc == BFD_RELOC_UNUSED); | |
7434 | } | |
7435 | else if (relax_char | |
7436 | && offset_expr.X_op == O_constant | |
7437 | && calculate_reloc (*offset_reloc, | |
7438 | offset_expr.X_add_number, | |
7439 | &value)) | |
7440 | { | |
7441 | mips16_immed (NULL, 0, relax_char, *offset_reloc, value, | |
7442 | forced_insn_length, &insn->insn_opcode); | |
7443 | offset_expr.X_op = O_absent; | |
7444 | *offset_reloc = BFD_RELOC_UNUSED; | |
7445 | } | |
7446 | else if (relax_char && *offset_reloc != BFD_RELOC_UNUSED) | |
7447 | { | |
7448 | if (forced_insn_length == 2) | |
e3de51ce | 7449 | set_insn_error (0, _("invalid unextended operand value")); |
97d87491 RS |
7450 | forced_insn_length = 4; |
7451 | insn->insn_opcode |= MIPS16_EXTEND; | |
7452 | } | |
7453 | else if (relax_char) | |
7454 | *offset_reloc = (int) BFD_RELOC_UNUSED + relax_char; | |
7455 | ||
7456 | check_completed_insn (&arg); | |
7457 | return TRUE; | |
7458 | } | |
7459 | ||
7460 | /* Fail the match if the line has too many operands. */ | |
7461 | if (*args == 0) | |
7462 | return FALSE; | |
7463 | ||
7464 | /* Handle characters that need to match exactly. */ | |
7465 | if (*args == '(' || *args == ')' || *args == ',') | |
7466 | { | |
7467 | if (match_char (&arg, *args)) | |
7468 | continue; | |
7469 | return FALSE; | |
7470 | } | |
7471 | ||
7472 | arg.opnum += 1; | |
7473 | c = *args; | |
7474 | switch (c) | |
7475 | { | |
7476 | case 'p': | |
7477 | case 'q': | |
7478 | case 'A': | |
7479 | case 'B': | |
7480 | case 'E': | |
7481 | relax_char = c; | |
7482 | break; | |
7483 | ||
7484 | case 'I': | |
1a00e612 RS |
7485 | if (!match_const_int (&arg, &imm_expr.X_add_number)) |
7486 | return FALSE; | |
7487 | imm_expr.X_op = O_constant; | |
bad1aba3 | 7488 | if (GPR_SIZE == 32) |
97d87491 RS |
7489 | normalize_constant_expr (&imm_expr); |
7490 | continue; | |
7491 | ||
7492 | case 'a': | |
7493 | case 'i': | |
7494 | *offset_reloc = BFD_RELOC_MIPS16_JMP; | |
7495 | insn->insn_opcode <<= 16; | |
7496 | break; | |
7497 | } | |
7498 | ||
7499 | operand = decode_mips16_operand (c, FALSE); | |
7500 | if (!operand) | |
7501 | abort (); | |
7502 | ||
7503 | /* '6' is a special case. It is used for BREAK and SDBBP, | |
7504 | whose operands are only meaningful to the software that decodes | |
7505 | them. This means that there is no architectural reason why | |
7506 | they cannot be prefixed by EXTEND, but in practice, | |
7507 | exception handlers will only look at the instruction | |
7508 | itself. We therefore allow '6' to be extended when | |
7509 | disassembling but not when assembling. */ | |
7510 | if (operand->type != OP_PCREL && c != '6') | |
7511 | { | |
7512 | ext_operand = decode_mips16_operand (c, TRUE); | |
7513 | if (operand != ext_operand) | |
7514 | { | |
7515 | if (arg.token->type == OT_CHAR && arg.token->u.ch == '(') | |
7516 | { | |
7517 | offset_expr.X_op = O_constant; | |
7518 | offset_expr.X_add_number = 0; | |
7519 | relax_char = c; | |
7520 | continue; | |
7521 | } | |
7522 | ||
7523 | /* We need the OT_INTEGER check because some MIPS16 | |
7524 | immediate variants are listed before the register ones. */ | |
7525 | if (arg.token->type != OT_INTEGER | |
7526 | || !match_expression (&arg, &offset_expr, offset_reloc)) | |
7527 | return FALSE; | |
7528 | ||
7529 | /* '8' is used for SLTI(U) and has traditionally not | |
7530 | been allowed to take relocation operators. */ | |
7531 | if (offset_reloc[0] != BFD_RELOC_UNUSED | |
7532 | && (ext_operand->size != 16 || c == '8')) | |
7533 | return FALSE; | |
7534 | ||
7535 | relax_char = c; | |
7536 | continue; | |
7537 | } | |
7538 | } | |
7539 | ||
7540 | if (mips_optional_operand_p (operand) | |
7541 | && args[1] == ',' | |
7542 | && (arg.token[0].type != OT_REG | |
7543 | || arg.token[1].type == OT_END)) | |
7544 | { | |
7545 | /* Assume that the register has been elided and is the | |
7546 | same as the first operand. */ | |
7547 | arg.token = tokens; | |
7548 | arg.argnum = 1; | |
7549 | } | |
7550 | ||
7551 | if (!match_operand (&arg, operand)) | |
7552 | return FALSE; | |
7553 | } | |
7554 | } | |
7555 | ||
60f20e8b RS |
7556 | /* Record that the current instruction is invalid for the current ISA. */ |
7557 | ||
7558 | static void | |
7559 | match_invalid_for_isa (void) | |
7560 | { | |
7561 | set_insn_error_ss | |
1661c76c | 7562 | (0, _("opcode not supported on this processor: %s (%s)"), |
60f20e8b RS |
7563 | mips_cpu_info_from_arch (mips_opts.arch)->name, |
7564 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
7565 | } | |
7566 | ||
7567 | /* Try to match TOKENS against a series of opcode entries, starting at FIRST. | |
7568 | Return true if a definite match or failure was found, storing any match | |
7569 | in INSN. OPCODE_EXTRA is a value that should be ORed into the opcode | |
7570 | (to handle things like VU0 suffixes). LAX_MATCH is true if we have already | |
7571 | tried and failed to match under normal conditions and now want to try a | |
7572 | more relaxed match. */ | |
7573 | ||
7574 | static bfd_boolean | |
7575 | match_insns (struct mips_cl_insn *insn, const struct mips_opcode *first, | |
7576 | const struct mips_opcode *past, struct mips_operand_token *tokens, | |
7577 | int opcode_extra, bfd_boolean lax_match) | |
7578 | { | |
7579 | const struct mips_opcode *opcode; | |
7580 | const struct mips_opcode *invalid_delay_slot; | |
7581 | bfd_boolean seen_valid_for_isa, seen_valid_for_size; | |
7582 | ||
7583 | /* Search for a match, ignoring alternatives that don't satisfy the | |
7584 | current ISA or forced_length. */ | |
7585 | invalid_delay_slot = 0; | |
7586 | seen_valid_for_isa = FALSE; | |
7587 | seen_valid_for_size = FALSE; | |
7588 | opcode = first; | |
7589 | do | |
7590 | { | |
7591 | gas_assert (strcmp (opcode->name, first->name) == 0); | |
7592 | if (is_opcode_valid (opcode)) | |
7593 | { | |
7594 | seen_valid_for_isa = TRUE; | |
7595 | if (is_size_valid (opcode)) | |
7596 | { | |
7597 | bfd_boolean delay_slot_ok; | |
7598 | ||
7599 | seen_valid_for_size = TRUE; | |
7600 | delay_slot_ok = is_delay_slot_valid (opcode); | |
7601 | if (match_insn (insn, opcode, tokens, opcode_extra, | |
7602 | lax_match, delay_slot_ok)) | |
7603 | { | |
7604 | if (!delay_slot_ok) | |
7605 | { | |
7606 | if (!invalid_delay_slot) | |
7607 | invalid_delay_slot = opcode; | |
7608 | } | |
7609 | else | |
7610 | return TRUE; | |
7611 | } | |
7612 | } | |
7613 | } | |
7614 | ++opcode; | |
7615 | } | |
7616 | while (opcode < past && strcmp (opcode->name, first->name) == 0); | |
7617 | ||
7618 | /* If the only matches we found had the wrong length for the delay slot, | |
7619 | pick the first such match. We'll issue an appropriate warning later. */ | |
7620 | if (invalid_delay_slot) | |
7621 | { | |
7622 | if (match_insn (insn, invalid_delay_slot, tokens, opcode_extra, | |
7623 | lax_match, TRUE)) | |
7624 | return TRUE; | |
7625 | abort (); | |
7626 | } | |
7627 | ||
7628 | /* Handle the case where we didn't try to match an instruction because | |
7629 | all the alternatives were incompatible with the current ISA. */ | |
7630 | if (!seen_valid_for_isa) | |
7631 | { | |
7632 | match_invalid_for_isa (); | |
7633 | return TRUE; | |
7634 | } | |
7635 | ||
7636 | /* Handle the case where we didn't try to match an instruction because | |
7637 | all the alternatives were of the wrong size. */ | |
7638 | if (!seen_valid_for_size) | |
7639 | { | |
7640 | if (mips_opts.insn32) | |
1661c76c | 7641 | set_insn_error (0, _("opcode not supported in the `insn32' mode")); |
60f20e8b RS |
7642 | else |
7643 | set_insn_error_i | |
1661c76c | 7644 | (0, _("unrecognized %d-bit version of microMIPS opcode"), |
60f20e8b RS |
7645 | 8 * forced_insn_length); |
7646 | return TRUE; | |
7647 | } | |
7648 | ||
7649 | return FALSE; | |
7650 | } | |
7651 | ||
7652 | /* Like match_insns, but for MIPS16. */ | |
7653 | ||
7654 | static bfd_boolean | |
7655 | match_mips16_insns (struct mips_cl_insn *insn, const struct mips_opcode *first, | |
7656 | struct mips_operand_token *tokens) | |
7657 | { | |
7658 | const struct mips_opcode *opcode; | |
7659 | bfd_boolean seen_valid_for_isa; | |
7660 | ||
7661 | /* Search for a match, ignoring alternatives that don't satisfy the | |
7662 | current ISA. There are no separate entries for extended forms so | |
7663 | we deal with forced_length later. */ | |
7664 | seen_valid_for_isa = FALSE; | |
7665 | opcode = first; | |
7666 | do | |
7667 | { | |
7668 | gas_assert (strcmp (opcode->name, first->name) == 0); | |
7669 | if (is_opcode_valid_16 (opcode)) | |
7670 | { | |
7671 | seen_valid_for_isa = TRUE; | |
7672 | if (match_mips16_insn (insn, opcode, tokens)) | |
7673 | return TRUE; | |
7674 | } | |
7675 | ++opcode; | |
7676 | } | |
7677 | while (opcode < &mips16_opcodes[bfd_mips16_num_opcodes] | |
7678 | && strcmp (opcode->name, first->name) == 0); | |
7679 | ||
7680 | /* Handle the case where we didn't try to match an instruction because | |
7681 | all the alternatives were incompatible with the current ISA. */ | |
7682 | if (!seen_valid_for_isa) | |
7683 | { | |
7684 | match_invalid_for_isa (); | |
7685 | return TRUE; | |
7686 | } | |
7687 | ||
7688 | return FALSE; | |
7689 | } | |
7690 | ||
584892a6 RS |
7691 | /* Set up global variables for the start of a new macro. */ |
7692 | ||
7693 | static void | |
7694 | macro_start (void) | |
7695 | { | |
7696 | memset (&mips_macro_warning.sizes, 0, sizeof (mips_macro_warning.sizes)); | |
df58fc94 RS |
7697 | memset (&mips_macro_warning.first_insn_sizes, 0, |
7698 | sizeof (mips_macro_warning.first_insn_sizes)); | |
7699 | memset (&mips_macro_warning.insns, 0, sizeof (mips_macro_warning.insns)); | |
584892a6 | 7700 | mips_macro_warning.delay_slot_p = (mips_opts.noreorder |
11625dd8 | 7701 | && delayed_branch_p (&history[0])); |
df58fc94 RS |
7702 | switch (history[0].insn_mo->pinfo2 |
7703 | & (INSN2_BRANCH_DELAY_32BIT | INSN2_BRANCH_DELAY_16BIT)) | |
7704 | { | |
7705 | case INSN2_BRANCH_DELAY_32BIT: | |
7706 | mips_macro_warning.delay_slot_length = 4; | |
7707 | break; | |
7708 | case INSN2_BRANCH_DELAY_16BIT: | |
7709 | mips_macro_warning.delay_slot_length = 2; | |
7710 | break; | |
7711 | default: | |
7712 | mips_macro_warning.delay_slot_length = 0; | |
7713 | break; | |
7714 | } | |
7715 | mips_macro_warning.first_frag = NULL; | |
584892a6 RS |
7716 | } |
7717 | ||
df58fc94 RS |
7718 | /* Given that a macro is longer than one instruction or of the wrong size, |
7719 | return the appropriate warning for it. Return null if no warning is | |
7720 | needed. SUBTYPE is a bitmask of RELAX_DELAY_SLOT, RELAX_DELAY_SLOT_16BIT, | |
7721 | RELAX_DELAY_SLOT_SIZE_FIRST, RELAX_DELAY_SLOT_SIZE_SECOND, | |
7722 | and RELAX_NOMACRO. */ | |
584892a6 RS |
7723 | |
7724 | static const char * | |
7725 | macro_warning (relax_substateT subtype) | |
7726 | { | |
7727 | if (subtype & RELAX_DELAY_SLOT) | |
1661c76c | 7728 | return _("macro instruction expanded into multiple instructions" |
584892a6 RS |
7729 | " in a branch delay slot"); |
7730 | else if (subtype & RELAX_NOMACRO) | |
1661c76c | 7731 | return _("macro instruction expanded into multiple instructions"); |
df58fc94 RS |
7732 | else if (subtype & (RELAX_DELAY_SLOT_SIZE_FIRST |
7733 | | RELAX_DELAY_SLOT_SIZE_SECOND)) | |
7734 | return ((subtype & RELAX_DELAY_SLOT_16BIT) | |
1661c76c | 7735 | ? _("macro instruction expanded into a wrong size instruction" |
df58fc94 | 7736 | " in a 16-bit branch delay slot") |
1661c76c | 7737 | : _("macro instruction expanded into a wrong size instruction" |
df58fc94 | 7738 | " in a 32-bit branch delay slot")); |
584892a6 RS |
7739 | else |
7740 | return 0; | |
7741 | } | |
7742 | ||
7743 | /* Finish up a macro. Emit warnings as appropriate. */ | |
7744 | ||
7745 | static void | |
7746 | macro_end (void) | |
7747 | { | |
df58fc94 RS |
7748 | /* Relaxation warning flags. */ |
7749 | relax_substateT subtype = 0; | |
7750 | ||
7751 | /* Check delay slot size requirements. */ | |
7752 | if (mips_macro_warning.delay_slot_length == 2) | |
7753 | subtype |= RELAX_DELAY_SLOT_16BIT; | |
7754 | if (mips_macro_warning.delay_slot_length != 0) | |
584892a6 | 7755 | { |
df58fc94 RS |
7756 | if (mips_macro_warning.delay_slot_length |
7757 | != mips_macro_warning.first_insn_sizes[0]) | |
7758 | subtype |= RELAX_DELAY_SLOT_SIZE_FIRST; | |
7759 | if (mips_macro_warning.delay_slot_length | |
7760 | != mips_macro_warning.first_insn_sizes[1]) | |
7761 | subtype |= RELAX_DELAY_SLOT_SIZE_SECOND; | |
7762 | } | |
584892a6 | 7763 | |
df58fc94 RS |
7764 | /* Check instruction count requirements. */ |
7765 | if (mips_macro_warning.insns[0] > 1 || mips_macro_warning.insns[1] > 1) | |
7766 | { | |
7767 | if (mips_macro_warning.insns[1] > mips_macro_warning.insns[0]) | |
584892a6 RS |
7768 | subtype |= RELAX_SECOND_LONGER; |
7769 | if (mips_opts.warn_about_macros) | |
7770 | subtype |= RELAX_NOMACRO; | |
7771 | if (mips_macro_warning.delay_slot_p) | |
7772 | subtype |= RELAX_DELAY_SLOT; | |
df58fc94 | 7773 | } |
584892a6 | 7774 | |
df58fc94 RS |
7775 | /* If both alternatives fail to fill a delay slot correctly, |
7776 | emit the warning now. */ | |
7777 | if ((subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0 | |
7778 | && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0) | |
7779 | { | |
7780 | relax_substateT s; | |
7781 | const char *msg; | |
7782 | ||
7783 | s = subtype & (RELAX_DELAY_SLOT_16BIT | |
7784 | | RELAX_DELAY_SLOT_SIZE_FIRST | |
7785 | | RELAX_DELAY_SLOT_SIZE_SECOND); | |
7786 | msg = macro_warning (s); | |
7787 | if (msg != NULL) | |
7788 | as_warn ("%s", msg); | |
7789 | subtype &= ~s; | |
7790 | } | |
7791 | ||
7792 | /* If both implementations are longer than 1 instruction, then emit the | |
7793 | warning now. */ | |
7794 | if (mips_macro_warning.insns[0] > 1 && mips_macro_warning.insns[1] > 1) | |
7795 | { | |
7796 | relax_substateT s; | |
7797 | const char *msg; | |
7798 | ||
7799 | s = subtype & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT); | |
7800 | msg = macro_warning (s); | |
7801 | if (msg != NULL) | |
7802 | as_warn ("%s", msg); | |
7803 | subtype &= ~s; | |
584892a6 | 7804 | } |
df58fc94 RS |
7805 | |
7806 | /* If any flags still set, then one implementation might need a warning | |
7807 | and the other either will need one of a different kind or none at all. | |
7808 | Pass any remaining flags over to relaxation. */ | |
7809 | if (mips_macro_warning.first_frag != NULL) | |
7810 | mips_macro_warning.first_frag->fr_subtype |= subtype; | |
584892a6 RS |
7811 | } |
7812 | ||
df58fc94 RS |
7813 | /* Instruction operand formats used in macros that vary between |
7814 | standard MIPS and microMIPS code. */ | |
7815 | ||
833794fc | 7816 | static const char * const brk_fmt[2][2] = { { "c", "c" }, { "mF", "c" } }; |
df58fc94 RS |
7817 | static const char * const cop12_fmt[2] = { "E,o(b)", "E,~(b)" }; |
7818 | static const char * const jalr_fmt[2] = { "d,s", "t,s" }; | |
7819 | static const char * const lui_fmt[2] = { "t,u", "s,u" }; | |
7820 | static const char * const mem12_fmt[2] = { "t,o(b)", "t,~(b)" }; | |
833794fc | 7821 | static const char * const mfhl_fmt[2][2] = { { "d", "d" }, { "mj", "s" } }; |
df58fc94 RS |
7822 | static const char * const shft_fmt[2] = { "d,w,<", "t,r,<" }; |
7823 | static const char * const trap_fmt[2] = { "s,t,q", "s,t,|" }; | |
7824 | ||
833794fc | 7825 | #define BRK_FMT (brk_fmt[mips_opts.micromips][mips_opts.insn32]) |
df58fc94 RS |
7826 | #define COP12_FMT (cop12_fmt[mips_opts.micromips]) |
7827 | #define JALR_FMT (jalr_fmt[mips_opts.micromips]) | |
7828 | #define LUI_FMT (lui_fmt[mips_opts.micromips]) | |
7829 | #define MEM12_FMT (mem12_fmt[mips_opts.micromips]) | |
833794fc | 7830 | #define MFHL_FMT (mfhl_fmt[mips_opts.micromips][mips_opts.insn32]) |
df58fc94 RS |
7831 | #define SHFT_FMT (shft_fmt[mips_opts.micromips]) |
7832 | #define TRAP_FMT (trap_fmt[mips_opts.micromips]) | |
7833 | ||
6e1304d8 RS |
7834 | /* Read a macro's relocation codes from *ARGS and store them in *R. |
7835 | The first argument in *ARGS will be either the code for a single | |
7836 | relocation or -1 followed by the three codes that make up a | |
7837 | composite relocation. */ | |
7838 | ||
7839 | static void | |
7840 | macro_read_relocs (va_list *args, bfd_reloc_code_real_type *r) | |
7841 | { | |
7842 | int i, next; | |
7843 | ||
7844 | next = va_arg (*args, int); | |
7845 | if (next >= 0) | |
7846 | r[0] = (bfd_reloc_code_real_type) next; | |
7847 | else | |
f2ae14a1 RS |
7848 | { |
7849 | for (i = 0; i < 3; i++) | |
7850 | r[i] = (bfd_reloc_code_real_type) va_arg (*args, int); | |
7851 | /* This function is only used for 16-bit relocation fields. | |
7852 | To make the macro code simpler, treat an unrelocated value | |
7853 | in the same way as BFD_RELOC_LO16. */ | |
7854 | if (r[0] == BFD_RELOC_UNUSED) | |
7855 | r[0] = BFD_RELOC_LO16; | |
7856 | } | |
6e1304d8 RS |
7857 | } |
7858 | ||
252b5132 RH |
7859 | /* Build an instruction created by a macro expansion. This is passed |
7860 | a pointer to the count of instructions created so far, an | |
7861 | expression, the name of the instruction to build, an operand format | |
7862 | string, and corresponding arguments. */ | |
7863 | ||
252b5132 | 7864 | static void |
67c0d1eb | 7865 | macro_build (expressionS *ep, const char *name, const char *fmt, ...) |
252b5132 | 7866 | { |
df58fc94 | 7867 | const struct mips_opcode *mo = NULL; |
f6688943 | 7868 | bfd_reloc_code_real_type r[3]; |
df58fc94 | 7869 | const struct mips_opcode *amo; |
e077a1c8 | 7870 | const struct mips_operand *operand; |
df58fc94 RS |
7871 | struct hash_control *hash; |
7872 | struct mips_cl_insn insn; | |
252b5132 | 7873 | va_list args; |
e077a1c8 | 7874 | unsigned int uval; |
252b5132 | 7875 | |
252b5132 | 7876 | va_start (args, fmt); |
252b5132 | 7877 | |
252b5132 RH |
7878 | if (mips_opts.mips16) |
7879 | { | |
03ea81db | 7880 | mips16_macro_build (ep, name, fmt, &args); |
252b5132 RH |
7881 | va_end (args); |
7882 | return; | |
7883 | } | |
7884 | ||
f6688943 TS |
7885 | r[0] = BFD_RELOC_UNUSED; |
7886 | r[1] = BFD_RELOC_UNUSED; | |
7887 | r[2] = BFD_RELOC_UNUSED; | |
df58fc94 RS |
7888 | hash = mips_opts.micromips ? micromips_op_hash : op_hash; |
7889 | amo = (struct mips_opcode *) hash_find (hash, name); | |
7890 | gas_assert (amo); | |
7891 | gas_assert (strcmp (name, amo->name) == 0); | |
1e915849 | 7892 | |
df58fc94 | 7893 | do |
8b082fb1 TS |
7894 | { |
7895 | /* Search until we get a match for NAME. It is assumed here that | |
df58fc94 RS |
7896 | macros will never generate MDMX, MIPS-3D, or MT instructions. |
7897 | We try to match an instruction that fulfils the branch delay | |
7898 | slot instruction length requirement (if any) of the previous | |
7899 | instruction. While doing this we record the first instruction | |
7900 | seen that matches all the other conditions and use it anyway | |
7901 | if the requirement cannot be met; we will issue an appropriate | |
7902 | warning later on. */ | |
7903 | if (strcmp (fmt, amo->args) == 0 | |
7904 | && amo->pinfo != INSN_MACRO | |
7905 | && is_opcode_valid (amo) | |
7906 | && is_size_valid (amo)) | |
7907 | { | |
7908 | if (is_delay_slot_valid (amo)) | |
7909 | { | |
7910 | mo = amo; | |
7911 | break; | |
7912 | } | |
7913 | else if (!mo) | |
7914 | mo = amo; | |
7915 | } | |
8b082fb1 | 7916 | |
df58fc94 RS |
7917 | ++amo; |
7918 | gas_assert (amo->name); | |
252b5132 | 7919 | } |
df58fc94 | 7920 | while (strcmp (name, amo->name) == 0); |
252b5132 | 7921 | |
df58fc94 | 7922 | gas_assert (mo); |
1e915849 | 7923 | create_insn (&insn, mo); |
e077a1c8 | 7924 | for (; *fmt; ++fmt) |
252b5132 | 7925 | { |
e077a1c8 | 7926 | switch (*fmt) |
252b5132 | 7927 | { |
252b5132 RH |
7928 | case ',': |
7929 | case '(': | |
7930 | case ')': | |
252b5132 | 7931 | case 'z': |
e077a1c8 | 7932 | break; |
252b5132 RH |
7933 | |
7934 | case 'i': | |
7935 | case 'j': | |
6e1304d8 | 7936 | macro_read_relocs (&args, r); |
9c2799c2 | 7937 | gas_assert (*r == BFD_RELOC_GPREL16 |
e391c024 RS |
7938 | || *r == BFD_RELOC_MIPS_HIGHER |
7939 | || *r == BFD_RELOC_HI16_S | |
7940 | || *r == BFD_RELOC_LO16 | |
7941 | || *r == BFD_RELOC_MIPS_GOT_OFST); | |
e077a1c8 | 7942 | break; |
e391c024 RS |
7943 | |
7944 | case 'o': | |
7945 | macro_read_relocs (&args, r); | |
e077a1c8 | 7946 | break; |
252b5132 RH |
7947 | |
7948 | case 'u': | |
6e1304d8 | 7949 | macro_read_relocs (&args, r); |
9c2799c2 | 7950 | gas_assert (ep != NULL |
90ecf173 MR |
7951 | && (ep->X_op == O_constant |
7952 | || (ep->X_op == O_symbol | |
7953 | && (*r == BFD_RELOC_MIPS_HIGHEST | |
7954 | || *r == BFD_RELOC_HI16_S | |
7955 | || *r == BFD_RELOC_HI16 | |
7956 | || *r == BFD_RELOC_GPREL16 | |
7957 | || *r == BFD_RELOC_MIPS_GOT_HI16 | |
7958 | || *r == BFD_RELOC_MIPS_CALL_HI16)))); | |
e077a1c8 | 7959 | break; |
252b5132 RH |
7960 | |
7961 | case 'p': | |
9c2799c2 | 7962 | gas_assert (ep != NULL); |
bad36eac | 7963 | |
252b5132 RH |
7964 | /* |
7965 | * This allows macro() to pass an immediate expression for | |
7966 | * creating short branches without creating a symbol. | |
bad36eac DJ |
7967 | * |
7968 | * We don't allow branch relaxation for these branches, as | |
7969 | * they should only appear in ".set nomacro" anyway. | |
252b5132 RH |
7970 | */ |
7971 | if (ep->X_op == O_constant) | |
7972 | { | |
df58fc94 RS |
7973 | /* For microMIPS we always use relocations for branches. |
7974 | So we should not resolve immediate values. */ | |
7975 | gas_assert (!mips_opts.micromips); | |
7976 | ||
bad36eac DJ |
7977 | if ((ep->X_add_number & 3) != 0) |
7978 | as_bad (_("branch to misaligned address (0x%lx)"), | |
7979 | (unsigned long) ep->X_add_number); | |
7980 | if ((ep->X_add_number + 0x20000) & ~0x3ffff) | |
7981 | as_bad (_("branch address range overflow (0x%lx)"), | |
7982 | (unsigned long) ep->X_add_number); | |
252b5132 RH |
7983 | insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff; |
7984 | ep = NULL; | |
7985 | } | |
7986 | else | |
0b25d3e6 | 7987 | *r = BFD_RELOC_16_PCREL_S2; |
e077a1c8 | 7988 | break; |
252b5132 RH |
7989 | |
7990 | case 'a': | |
9c2799c2 | 7991 | gas_assert (ep != NULL); |
f6688943 | 7992 | *r = BFD_RELOC_MIPS_JMP; |
e077a1c8 | 7993 | break; |
d43b4baf | 7994 | |
252b5132 | 7995 | default: |
e077a1c8 RS |
7996 | operand = (mips_opts.micromips |
7997 | ? decode_micromips_operand (fmt) | |
7998 | : decode_mips_operand (fmt)); | |
7999 | if (!operand) | |
8000 | abort (); | |
8001 | ||
8002 | uval = va_arg (args, int); | |
8003 | if (operand->type == OP_CLO_CLZ_DEST) | |
8004 | uval |= (uval << 5); | |
8005 | insn_insert_operand (&insn, operand, uval); | |
8006 | ||
8007 | if (*fmt == '+' || *fmt == 'm') | |
8008 | ++fmt; | |
8009 | break; | |
252b5132 | 8010 | } |
252b5132 RH |
8011 | } |
8012 | va_end (args); | |
9c2799c2 | 8013 | gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
252b5132 | 8014 | |
df58fc94 | 8015 | append_insn (&insn, ep, r, TRUE); |
252b5132 RH |
8016 | } |
8017 | ||
8018 | static void | |
67c0d1eb | 8019 | mips16_macro_build (expressionS *ep, const char *name, const char *fmt, |
03ea81db | 8020 | va_list *args) |
252b5132 | 8021 | { |
1e915849 | 8022 | struct mips_opcode *mo; |
252b5132 | 8023 | struct mips_cl_insn insn; |
e077a1c8 | 8024 | const struct mips_operand *operand; |
f6688943 TS |
8025 | bfd_reloc_code_real_type r[3] |
8026 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 8027 | |
1e915849 | 8028 | mo = (struct mips_opcode *) hash_find (mips16_op_hash, name); |
9c2799c2 NC |
8029 | gas_assert (mo); |
8030 | gas_assert (strcmp (name, mo->name) == 0); | |
252b5132 | 8031 | |
1e915849 | 8032 | while (strcmp (fmt, mo->args) != 0 || mo->pinfo == INSN_MACRO) |
252b5132 | 8033 | { |
1e915849 | 8034 | ++mo; |
9c2799c2 NC |
8035 | gas_assert (mo->name); |
8036 | gas_assert (strcmp (name, mo->name) == 0); | |
252b5132 RH |
8037 | } |
8038 | ||
1e915849 | 8039 | create_insn (&insn, mo); |
e077a1c8 | 8040 | for (; *fmt; ++fmt) |
252b5132 RH |
8041 | { |
8042 | int c; | |
8043 | ||
e077a1c8 | 8044 | c = *fmt; |
252b5132 RH |
8045 | switch (c) |
8046 | { | |
252b5132 RH |
8047 | case ',': |
8048 | case '(': | |
8049 | case ')': | |
e077a1c8 | 8050 | break; |
252b5132 RH |
8051 | |
8052 | case '0': | |
8053 | case 'S': | |
8054 | case 'P': | |
8055 | case 'R': | |
e077a1c8 | 8056 | break; |
252b5132 RH |
8057 | |
8058 | case '<': | |
8059 | case '>': | |
8060 | case '4': | |
8061 | case '5': | |
8062 | case 'H': | |
8063 | case 'W': | |
8064 | case 'D': | |
8065 | case 'j': | |
8066 | case '8': | |
8067 | case 'V': | |
8068 | case 'C': | |
8069 | case 'U': | |
8070 | case 'k': | |
8071 | case 'K': | |
8072 | case 'p': | |
8073 | case 'q': | |
8074 | { | |
b886a2ab RS |
8075 | offsetT value; |
8076 | ||
9c2799c2 | 8077 | gas_assert (ep != NULL); |
252b5132 RH |
8078 | |
8079 | if (ep->X_op != O_constant) | |
874e8986 | 8080 | *r = (int) BFD_RELOC_UNUSED + c; |
b886a2ab | 8081 | else if (calculate_reloc (*r, ep->X_add_number, &value)) |
252b5132 | 8082 | { |
b886a2ab | 8083 | mips16_immed (NULL, 0, c, *r, value, 0, &insn.insn_opcode); |
252b5132 | 8084 | ep = NULL; |
f6688943 | 8085 | *r = BFD_RELOC_UNUSED; |
252b5132 RH |
8086 | } |
8087 | } | |
e077a1c8 | 8088 | break; |
252b5132 | 8089 | |
e077a1c8 RS |
8090 | default: |
8091 | operand = decode_mips16_operand (c, FALSE); | |
8092 | if (!operand) | |
8093 | abort (); | |
252b5132 | 8094 | |
4a06e5a2 | 8095 | insn_insert_operand (&insn, operand, va_arg (*args, int)); |
e077a1c8 RS |
8096 | break; |
8097 | } | |
252b5132 RH |
8098 | } |
8099 | ||
9c2799c2 | 8100 | gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
252b5132 | 8101 | |
df58fc94 | 8102 | append_insn (&insn, ep, r, TRUE); |
252b5132 RH |
8103 | } |
8104 | ||
438c16b8 TS |
8105 | /* |
8106 | * Generate a "jalr" instruction with a relocation hint to the called | |
8107 | * function. This occurs in NewABI PIC code. | |
8108 | */ | |
8109 | static void | |
df58fc94 | 8110 | macro_build_jalr (expressionS *ep, int cprestore) |
438c16b8 | 8111 | { |
df58fc94 RS |
8112 | static const bfd_reloc_code_real_type jalr_relocs[2] |
8113 | = { BFD_RELOC_MIPS_JALR, BFD_RELOC_MICROMIPS_JALR }; | |
8114 | bfd_reloc_code_real_type jalr_reloc = jalr_relocs[mips_opts.micromips]; | |
8115 | const char *jalr; | |
685736be | 8116 | char *f = NULL; |
b34976b6 | 8117 | |
1180b5a4 | 8118 | if (MIPS_JALR_HINT_P (ep)) |
f21f8242 | 8119 | { |
cc3d92a5 | 8120 | frag_grow (8); |
f21f8242 AO |
8121 | f = frag_more (0); |
8122 | } | |
2906b037 | 8123 | if (mips_opts.micromips) |
df58fc94 | 8124 | { |
833794fc MR |
8125 | jalr = ((mips_opts.noreorder && !cprestore) || mips_opts.insn32 |
8126 | ? "jalr" : "jalrs"); | |
e64af278 | 8127 | if (MIPS_JALR_HINT_P (ep) |
833794fc | 8128 | || mips_opts.insn32 |
e64af278 | 8129 | || (history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) |
df58fc94 RS |
8130 | macro_build (NULL, jalr, "t,s", RA, PIC_CALL_REG); |
8131 | else | |
8132 | macro_build (NULL, jalr, "mj", PIC_CALL_REG); | |
8133 | } | |
2906b037 MR |
8134 | else |
8135 | macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG); | |
1180b5a4 | 8136 | if (MIPS_JALR_HINT_P (ep)) |
df58fc94 | 8137 | fix_new_exp (frag_now, f - frag_now->fr_literal, 4, ep, FALSE, jalr_reloc); |
438c16b8 TS |
8138 | } |
8139 | ||
252b5132 RH |
8140 | /* |
8141 | * Generate a "lui" instruction. | |
8142 | */ | |
8143 | static void | |
67c0d1eb | 8144 | macro_build_lui (expressionS *ep, int regnum) |
252b5132 | 8145 | { |
9c2799c2 | 8146 | gas_assert (! mips_opts.mips16); |
252b5132 | 8147 | |
df58fc94 | 8148 | if (ep->X_op != O_constant) |
252b5132 | 8149 | { |
9c2799c2 | 8150 | gas_assert (ep->X_op == O_symbol); |
bbe506e8 TS |
8151 | /* _gp_disp is a special case, used from s_cpload. |
8152 | __gnu_local_gp is used if mips_no_shared. */ | |
9c2799c2 | 8153 | gas_assert (mips_pic == NO_PIC |
78e1bb40 | 8154 | || (! HAVE_NEWABI |
aa6975fb ILT |
8155 | && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0) |
8156 | || (! mips_in_shared | |
bbe506e8 TS |
8157 | && strcmp (S_GET_NAME (ep->X_add_symbol), |
8158 | "__gnu_local_gp") == 0)); | |
252b5132 RH |
8159 | } |
8160 | ||
df58fc94 | 8161 | macro_build (ep, "lui", LUI_FMT, regnum, BFD_RELOC_HI16_S); |
252b5132 RH |
8162 | } |
8163 | ||
885add95 CD |
8164 | /* Generate a sequence of instructions to do a load or store from a constant |
8165 | offset off of a base register (breg) into/from a target register (treg), | |
8166 | using AT if necessary. */ | |
8167 | static void | |
67c0d1eb RS |
8168 | macro_build_ldst_constoffset (expressionS *ep, const char *op, |
8169 | int treg, int breg, int dbl) | |
885add95 | 8170 | { |
9c2799c2 | 8171 | gas_assert (ep->X_op == O_constant); |
885add95 | 8172 | |
256ab948 | 8173 | /* Sign-extending 32-bit constants makes their handling easier. */ |
2051e8c4 MR |
8174 | if (!dbl) |
8175 | normalize_constant_expr (ep); | |
256ab948 | 8176 | |
67c1ffbe | 8177 | /* Right now, this routine can only handle signed 32-bit constants. */ |
ecd13cd3 | 8178 | if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000)) |
885add95 CD |
8179 | as_warn (_("operand overflow")); |
8180 | ||
8181 | if (IS_SEXT_16BIT_NUM(ep->X_add_number)) | |
8182 | { | |
8183 | /* Signed 16-bit offset will fit in the op. Easy! */ | |
67c0d1eb | 8184 | macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
885add95 CD |
8185 | } |
8186 | else | |
8187 | { | |
8188 | /* 32-bit offset, need multiple instructions and AT, like: | |
8189 | lui $tempreg,const_hi (BFD_RELOC_HI16_S) | |
8190 | addu $tempreg,$tempreg,$breg | |
8191 | <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16) | |
8192 | to handle the complete offset. */ | |
67c0d1eb RS |
8193 | macro_build_lui (ep, AT); |
8194 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); | |
8195 | macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, AT); | |
885add95 | 8196 | |
741fe287 | 8197 | if (!mips_opts.at) |
1661c76c | 8198 | as_bad (_("macro used $at after \".set noat\"")); |
885add95 CD |
8199 | } |
8200 | } | |
8201 | ||
252b5132 RH |
8202 | /* set_at() |
8203 | * Generates code to set the $at register to true (one) | |
8204 | * if reg is less than the immediate expression. | |
8205 | */ | |
8206 | static void | |
67c0d1eb | 8207 | set_at (int reg, int unsignedp) |
252b5132 | 8208 | { |
b0e6f033 | 8209 | if (imm_expr.X_add_number >= -0x8000 |
252b5132 | 8210 | && imm_expr.X_add_number < 0x8000) |
67c0d1eb RS |
8211 | macro_build (&imm_expr, unsignedp ? "sltiu" : "slti", "t,r,j", |
8212 | AT, reg, BFD_RELOC_LO16); | |
252b5132 RH |
8213 | else |
8214 | { | |
bad1aba3 | 8215 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
67c0d1eb | 8216 | macro_build (NULL, unsignedp ? "sltu" : "slt", "d,v,t", AT, reg, AT); |
252b5132 RH |
8217 | } |
8218 | } | |
8219 | ||
252b5132 RH |
8220 | /* Count the leading zeroes by performing a binary chop. This is a |
8221 | bulky bit of source, but performance is a LOT better for the | |
8222 | majority of values than a simple loop to count the bits: | |
8223 | for (lcnt = 0; (lcnt < 32); lcnt++) | |
8224 | if ((v) & (1 << (31 - lcnt))) | |
8225 | break; | |
8226 | However it is not code size friendly, and the gain will drop a bit | |
8227 | on certain cached systems. | |
8228 | */ | |
8229 | #define COUNT_TOP_ZEROES(v) \ | |
8230 | (((v) & ~0xffff) == 0 \ | |
8231 | ? ((v) & ~0xff) == 0 \ | |
8232 | ? ((v) & ~0xf) == 0 \ | |
8233 | ? ((v) & ~0x3) == 0 \ | |
8234 | ? ((v) & ~0x1) == 0 \ | |
8235 | ? !(v) \ | |
8236 | ? 32 \ | |
8237 | : 31 \ | |
8238 | : 30 \ | |
8239 | : ((v) & ~0x7) == 0 \ | |
8240 | ? 29 \ | |
8241 | : 28 \ | |
8242 | : ((v) & ~0x3f) == 0 \ | |
8243 | ? ((v) & ~0x1f) == 0 \ | |
8244 | ? 27 \ | |
8245 | : 26 \ | |
8246 | : ((v) & ~0x7f) == 0 \ | |
8247 | ? 25 \ | |
8248 | : 24 \ | |
8249 | : ((v) & ~0xfff) == 0 \ | |
8250 | ? ((v) & ~0x3ff) == 0 \ | |
8251 | ? ((v) & ~0x1ff) == 0 \ | |
8252 | ? 23 \ | |
8253 | : 22 \ | |
8254 | : ((v) & ~0x7ff) == 0 \ | |
8255 | ? 21 \ | |
8256 | : 20 \ | |
8257 | : ((v) & ~0x3fff) == 0 \ | |
8258 | ? ((v) & ~0x1fff) == 0 \ | |
8259 | ? 19 \ | |
8260 | : 18 \ | |
8261 | : ((v) & ~0x7fff) == 0 \ | |
8262 | ? 17 \ | |
8263 | : 16 \ | |
8264 | : ((v) & ~0xffffff) == 0 \ | |
8265 | ? ((v) & ~0xfffff) == 0 \ | |
8266 | ? ((v) & ~0x3ffff) == 0 \ | |
8267 | ? ((v) & ~0x1ffff) == 0 \ | |
8268 | ? 15 \ | |
8269 | : 14 \ | |
8270 | : ((v) & ~0x7ffff) == 0 \ | |
8271 | ? 13 \ | |
8272 | : 12 \ | |
8273 | : ((v) & ~0x3fffff) == 0 \ | |
8274 | ? ((v) & ~0x1fffff) == 0 \ | |
8275 | ? 11 \ | |
8276 | : 10 \ | |
8277 | : ((v) & ~0x7fffff) == 0 \ | |
8278 | ? 9 \ | |
8279 | : 8 \ | |
8280 | : ((v) & ~0xfffffff) == 0 \ | |
8281 | ? ((v) & ~0x3ffffff) == 0 \ | |
8282 | ? ((v) & ~0x1ffffff) == 0 \ | |
8283 | ? 7 \ | |
8284 | : 6 \ | |
8285 | : ((v) & ~0x7ffffff) == 0 \ | |
8286 | ? 5 \ | |
8287 | : 4 \ | |
8288 | : ((v) & ~0x3fffffff) == 0 \ | |
8289 | ? ((v) & ~0x1fffffff) == 0 \ | |
8290 | ? 3 \ | |
8291 | : 2 \ | |
8292 | : ((v) & ~0x7fffffff) == 0 \ | |
8293 | ? 1 \ | |
8294 | : 0) | |
8295 | ||
8296 | /* load_register() | |
67c1ffbe | 8297 | * This routine generates the least number of instructions necessary to load |
252b5132 RH |
8298 | * an absolute expression value into a register. |
8299 | */ | |
8300 | static void | |
67c0d1eb | 8301 | load_register (int reg, expressionS *ep, int dbl) |
252b5132 RH |
8302 | { |
8303 | int freg; | |
8304 | expressionS hi32, lo32; | |
8305 | ||
8306 | if (ep->X_op != O_big) | |
8307 | { | |
9c2799c2 | 8308 | gas_assert (ep->X_op == O_constant); |
256ab948 TS |
8309 | |
8310 | /* Sign-extending 32-bit constants makes their handling easier. */ | |
2051e8c4 MR |
8311 | if (!dbl) |
8312 | normalize_constant_expr (ep); | |
256ab948 TS |
8313 | |
8314 | if (IS_SEXT_16BIT_NUM (ep->X_add_number)) | |
252b5132 RH |
8315 | { |
8316 | /* We can handle 16 bit signed values with an addiu to | |
8317 | $zero. No need to ever use daddiu here, since $zero and | |
8318 | the result are always correct in 32 bit mode. */ | |
67c0d1eb | 8319 | macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
8320 | return; |
8321 | } | |
8322 | else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000) | |
8323 | { | |
8324 | /* We can handle 16 bit unsigned values with an ori to | |
8325 | $zero. */ | |
67c0d1eb | 8326 | macro_build (ep, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
8327 | return; |
8328 | } | |
256ab948 | 8329 | else if ((IS_SEXT_32BIT_NUM (ep->X_add_number))) |
252b5132 RH |
8330 | { |
8331 | /* 32 bit values require an lui. */ | |
df58fc94 | 8332 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_HI16); |
252b5132 | 8333 | if ((ep->X_add_number & 0xffff) != 0) |
67c0d1eb | 8334 | macro_build (ep, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16); |
252b5132 RH |
8335 | return; |
8336 | } | |
8337 | } | |
8338 | ||
8339 | /* The value is larger than 32 bits. */ | |
8340 | ||
bad1aba3 | 8341 | if (!dbl || GPR_SIZE == 32) |
252b5132 | 8342 | { |
55e08f71 NC |
8343 | char value[32]; |
8344 | ||
8345 | sprintf_vma (value, ep->X_add_number); | |
1661c76c | 8346 | as_bad (_("number (0x%s) larger than 32 bits"), value); |
67c0d1eb | 8347 | macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
8348 | return; |
8349 | } | |
8350 | ||
8351 | if (ep->X_op != O_big) | |
8352 | { | |
8353 | hi32 = *ep; | |
8354 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
8355 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
8356 | hi32.X_add_number &= 0xffffffff; | |
8357 | lo32 = *ep; | |
8358 | lo32.X_add_number &= 0xffffffff; | |
8359 | } | |
8360 | else | |
8361 | { | |
9c2799c2 | 8362 | gas_assert (ep->X_add_number > 2); |
252b5132 RH |
8363 | if (ep->X_add_number == 3) |
8364 | generic_bignum[3] = 0; | |
8365 | else if (ep->X_add_number > 4) | |
1661c76c | 8366 | as_bad (_("number larger than 64 bits")); |
252b5132 RH |
8367 | lo32.X_op = O_constant; |
8368 | lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16); | |
8369 | hi32.X_op = O_constant; | |
8370 | hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16); | |
8371 | } | |
8372 | ||
8373 | if (hi32.X_add_number == 0) | |
8374 | freg = 0; | |
8375 | else | |
8376 | { | |
8377 | int shift, bit; | |
8378 | unsigned long hi, lo; | |
8379 | ||
956cd1d6 | 8380 | if (hi32.X_add_number == (offsetT) 0xffffffff) |
beae10d5 KH |
8381 | { |
8382 | if ((lo32.X_add_number & 0xffff8000) == 0xffff8000) | |
8383 | { | |
67c0d1eb | 8384 | macro_build (&lo32, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
beae10d5 KH |
8385 | return; |
8386 | } | |
8387 | if (lo32.X_add_number & 0x80000000) | |
8388 | { | |
df58fc94 | 8389 | macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16); |
252b5132 | 8390 | if (lo32.X_add_number & 0xffff) |
67c0d1eb | 8391 | macro_build (&lo32, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16); |
beae10d5 KH |
8392 | return; |
8393 | } | |
8394 | } | |
252b5132 RH |
8395 | |
8396 | /* Check for 16bit shifted constant. We know that hi32 is | |
8397 | non-zero, so start the mask on the first bit of the hi32 | |
8398 | value. */ | |
8399 | shift = 17; | |
8400 | do | |
beae10d5 KH |
8401 | { |
8402 | unsigned long himask, lomask; | |
8403 | ||
8404 | if (shift < 32) | |
8405 | { | |
8406 | himask = 0xffff >> (32 - shift); | |
8407 | lomask = (0xffff << shift) & 0xffffffff; | |
8408 | } | |
8409 | else | |
8410 | { | |
8411 | himask = 0xffff << (shift - 32); | |
8412 | lomask = 0; | |
8413 | } | |
8414 | if ((hi32.X_add_number & ~(offsetT) himask) == 0 | |
8415 | && (lo32.X_add_number & ~(offsetT) lomask) == 0) | |
8416 | { | |
8417 | expressionS tmp; | |
8418 | ||
8419 | tmp.X_op = O_constant; | |
8420 | if (shift < 32) | |
8421 | tmp.X_add_number = ((hi32.X_add_number << (32 - shift)) | |
8422 | | (lo32.X_add_number >> shift)); | |
8423 | else | |
8424 | tmp.X_add_number = hi32.X_add_number >> (shift - 32); | |
67c0d1eb | 8425 | macro_build (&tmp, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16); |
df58fc94 | 8426 | macro_build (NULL, (shift >= 32) ? "dsll32" : "dsll", SHFT_FMT, |
67c0d1eb | 8427 | reg, reg, (shift >= 32) ? shift - 32 : shift); |
beae10d5 KH |
8428 | return; |
8429 | } | |
f9419b05 | 8430 | ++shift; |
beae10d5 KH |
8431 | } |
8432 | while (shift <= (64 - 16)); | |
252b5132 RH |
8433 | |
8434 | /* Find the bit number of the lowest one bit, and store the | |
8435 | shifted value in hi/lo. */ | |
8436 | hi = (unsigned long) (hi32.X_add_number & 0xffffffff); | |
8437 | lo = (unsigned long) (lo32.X_add_number & 0xffffffff); | |
8438 | if (lo != 0) | |
8439 | { | |
8440 | bit = 0; | |
8441 | while ((lo & 1) == 0) | |
8442 | { | |
8443 | lo >>= 1; | |
8444 | ++bit; | |
8445 | } | |
8446 | lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit); | |
8447 | hi >>= bit; | |
8448 | } | |
8449 | else | |
8450 | { | |
8451 | bit = 32; | |
8452 | while ((hi & 1) == 0) | |
8453 | { | |
8454 | hi >>= 1; | |
8455 | ++bit; | |
8456 | } | |
8457 | lo = hi; | |
8458 | hi = 0; | |
8459 | } | |
8460 | ||
8461 | /* Optimize if the shifted value is a (power of 2) - 1. */ | |
8462 | if ((hi == 0 && ((lo + 1) & lo) == 0) | |
8463 | || (lo == 0xffffffff && ((hi + 1) & hi) == 0)) | |
beae10d5 KH |
8464 | { |
8465 | shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number); | |
252b5132 | 8466 | if (shift != 0) |
beae10d5 | 8467 | { |
252b5132 RH |
8468 | expressionS tmp; |
8469 | ||
8470 | /* This instruction will set the register to be all | |
8471 | ones. */ | |
beae10d5 KH |
8472 | tmp.X_op = O_constant; |
8473 | tmp.X_add_number = (offsetT) -1; | |
67c0d1eb | 8474 | macro_build (&tmp, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
beae10d5 KH |
8475 | if (bit != 0) |
8476 | { | |
8477 | bit += shift; | |
df58fc94 | 8478 | macro_build (NULL, (bit >= 32) ? "dsll32" : "dsll", SHFT_FMT, |
67c0d1eb | 8479 | reg, reg, (bit >= 32) ? bit - 32 : bit); |
beae10d5 | 8480 | } |
df58fc94 | 8481 | macro_build (NULL, (shift >= 32) ? "dsrl32" : "dsrl", SHFT_FMT, |
67c0d1eb | 8482 | reg, reg, (shift >= 32) ? shift - 32 : shift); |
beae10d5 KH |
8483 | return; |
8484 | } | |
8485 | } | |
252b5132 RH |
8486 | |
8487 | /* Sign extend hi32 before calling load_register, because we can | |
8488 | generally get better code when we load a sign extended value. */ | |
8489 | if ((hi32.X_add_number & 0x80000000) != 0) | |
beae10d5 | 8490 | hi32.X_add_number |= ~(offsetT) 0xffffffff; |
67c0d1eb | 8491 | load_register (reg, &hi32, 0); |
252b5132 RH |
8492 | freg = reg; |
8493 | } | |
8494 | if ((lo32.X_add_number & 0xffff0000) == 0) | |
8495 | { | |
8496 | if (freg != 0) | |
8497 | { | |
df58fc94 | 8498 | macro_build (NULL, "dsll32", SHFT_FMT, reg, freg, 0); |
252b5132 RH |
8499 | freg = reg; |
8500 | } | |
8501 | } | |
8502 | else | |
8503 | { | |
8504 | expressionS mid16; | |
8505 | ||
956cd1d6 | 8506 | if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff)) |
beae10d5 | 8507 | { |
df58fc94 RS |
8508 | macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16); |
8509 | macro_build (NULL, "dsrl32", SHFT_FMT, reg, reg, 0); | |
beae10d5 KH |
8510 | return; |
8511 | } | |
252b5132 RH |
8512 | |
8513 | if (freg != 0) | |
8514 | { | |
df58fc94 | 8515 | macro_build (NULL, "dsll", SHFT_FMT, reg, freg, 16); |
252b5132 RH |
8516 | freg = reg; |
8517 | } | |
8518 | mid16 = lo32; | |
8519 | mid16.X_add_number >>= 16; | |
67c0d1eb | 8520 | macro_build (&mid16, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16); |
df58fc94 | 8521 | macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16); |
252b5132 RH |
8522 | freg = reg; |
8523 | } | |
8524 | if ((lo32.X_add_number & 0xffff) != 0) | |
67c0d1eb | 8525 | macro_build (&lo32, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16); |
252b5132 RH |
8526 | } |
8527 | ||
269137b2 TS |
8528 | static inline void |
8529 | load_delay_nop (void) | |
8530 | { | |
8531 | if (!gpr_interlocks) | |
8532 | macro_build (NULL, "nop", ""); | |
8533 | } | |
8534 | ||
252b5132 RH |
8535 | /* Load an address into a register. */ |
8536 | ||
8537 | static void | |
67c0d1eb | 8538 | load_address (int reg, expressionS *ep, int *used_at) |
252b5132 | 8539 | { |
252b5132 RH |
8540 | if (ep->X_op != O_constant |
8541 | && ep->X_op != O_symbol) | |
8542 | { | |
8543 | as_bad (_("expression too complex")); | |
8544 | ep->X_op = O_constant; | |
8545 | } | |
8546 | ||
8547 | if (ep->X_op == O_constant) | |
8548 | { | |
67c0d1eb | 8549 | load_register (reg, ep, HAVE_64BIT_ADDRESSES); |
252b5132 RH |
8550 | return; |
8551 | } | |
8552 | ||
8553 | if (mips_pic == NO_PIC) | |
8554 | { | |
8555 | /* If this is a reference to a GP relative symbol, we want | |
cdf6fd85 | 8556 | addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
8557 | Otherwise we want |
8558 | lui $reg,<sym> (BFD_RELOC_HI16_S) | |
8559 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
d6bc6245 | 8560 | If we have an addend, we always use the latter form. |
76b3015f | 8561 | |
d6bc6245 TS |
8562 | With 64bit address space and a usable $at we want |
8563 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
8564 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
8565 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
8566 | daddiu $at,<sym> (BFD_RELOC_LO16) | |
8567 | dsll32 $reg,0 | |
3a482fd5 | 8568 | daddu $reg,$reg,$at |
76b3015f | 8569 | |
c03099e6 | 8570 | If $at is already in use, we use a path which is suboptimal |
d6bc6245 TS |
8571 | on superscalar processors. |
8572 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
8573 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
8574 | dsll $reg,16 | |
8575 | daddiu $reg,<sym> (BFD_RELOC_HI16_S) | |
8576 | dsll $reg,16 | |
8577 | daddiu $reg,<sym> (BFD_RELOC_LO16) | |
6caf9ef4 TS |
8578 | |
8579 | For GP relative symbols in 64bit address space we can use | |
8580 | the same sequence as in 32bit address space. */ | |
aed1a261 | 8581 | if (HAVE_64BIT_SYMBOLS) |
d6bc6245 | 8582 | { |
6caf9ef4 TS |
8583 | if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET |
8584 | && !nopic_need_relax (ep->X_add_symbol, 1)) | |
8585 | { | |
8586 | relax_start (ep->X_add_symbol); | |
8587 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, | |
8588 | mips_gp_register, BFD_RELOC_GPREL16); | |
8589 | relax_switch (); | |
8590 | } | |
d6bc6245 | 8591 | |
741fe287 | 8592 | if (*used_at == 0 && mips_opts.at) |
d6bc6245 | 8593 | { |
df58fc94 RS |
8594 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST); |
8595 | macro_build (ep, "lui", LUI_FMT, AT, BFD_RELOC_HI16_S); | |
67c0d1eb RS |
8596 | macro_build (ep, "daddiu", "t,r,j", reg, reg, |
8597 | BFD_RELOC_MIPS_HIGHER); | |
8598 | macro_build (ep, "daddiu", "t,r,j", AT, AT, BFD_RELOC_LO16); | |
df58fc94 | 8599 | macro_build (NULL, "dsll32", SHFT_FMT, reg, reg, 0); |
67c0d1eb | 8600 | macro_build (NULL, "daddu", "d,v,t", reg, reg, AT); |
d6bc6245 TS |
8601 | *used_at = 1; |
8602 | } | |
8603 | else | |
8604 | { | |
df58fc94 | 8605 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST); |
67c0d1eb RS |
8606 | macro_build (ep, "daddiu", "t,r,j", reg, reg, |
8607 | BFD_RELOC_MIPS_HIGHER); | |
df58fc94 | 8608 | macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16); |
67c0d1eb | 8609 | macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_HI16_S); |
df58fc94 | 8610 | macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16); |
67c0d1eb | 8611 | macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_LO16); |
d6bc6245 | 8612 | } |
6caf9ef4 TS |
8613 | |
8614 | if (mips_relax.sequence) | |
8615 | relax_end (); | |
d6bc6245 | 8616 | } |
252b5132 RH |
8617 | else |
8618 | { | |
d6bc6245 | 8619 | if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 8620 | && !nopic_need_relax (ep->X_add_symbol, 1)) |
d6bc6245 | 8621 | { |
4d7206a2 | 8622 | relax_start (ep->X_add_symbol); |
67c0d1eb | 8623 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, |
17a2f251 | 8624 | mips_gp_register, BFD_RELOC_GPREL16); |
4d7206a2 | 8625 | relax_switch (); |
d6bc6245 | 8626 | } |
67c0d1eb RS |
8627 | macro_build_lui (ep, reg); |
8628 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", | |
8629 | reg, reg, BFD_RELOC_LO16); | |
4d7206a2 RS |
8630 | if (mips_relax.sequence) |
8631 | relax_end (); | |
d6bc6245 | 8632 | } |
252b5132 | 8633 | } |
0a44bf69 | 8634 | else if (!mips_big_got) |
252b5132 RH |
8635 | { |
8636 | expressionS ex; | |
8637 | ||
8638 | /* If this is a reference to an external symbol, we want | |
8639 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
8640 | Otherwise we want | |
8641 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
8642 | nop | |
8643 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
f5040a92 AO |
8644 | If there is a constant, it must be added in after. |
8645 | ||
ed6fb7bd | 8646 | If we have NewABI, we want |
f5040a92 AO |
8647 | lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP) |
8648 | unless we're referencing a global symbol with a non-zero | |
8649 | offset, in which case cst must be added separately. */ | |
ed6fb7bd SC |
8650 | if (HAVE_NEWABI) |
8651 | { | |
f5040a92 AO |
8652 | if (ep->X_add_number) |
8653 | { | |
4d7206a2 | 8654 | ex.X_add_number = ep->X_add_number; |
f5040a92 | 8655 | ep->X_add_number = 0; |
4d7206a2 | 8656 | relax_start (ep->X_add_symbol); |
67c0d1eb RS |
8657 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
8658 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
8659 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) |
8660 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
8661 | ex.X_op = O_constant; | |
67c0d1eb | 8662 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 8663 | reg, reg, BFD_RELOC_LO16); |
f5040a92 | 8664 | ep->X_add_number = ex.X_add_number; |
4d7206a2 | 8665 | relax_switch (); |
f5040a92 | 8666 | } |
67c0d1eb | 8667 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 8668 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); |
4d7206a2 RS |
8669 | if (mips_relax.sequence) |
8670 | relax_end (); | |
ed6fb7bd SC |
8671 | } |
8672 | else | |
8673 | { | |
f5040a92 AO |
8674 | ex.X_add_number = ep->X_add_number; |
8675 | ep->X_add_number = 0; | |
67c0d1eb RS |
8676 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
8677 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 8678 | load_delay_nop (); |
4d7206a2 RS |
8679 | relax_start (ep->X_add_symbol); |
8680 | relax_switch (); | |
67c0d1eb | 8681 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
17a2f251 | 8682 | BFD_RELOC_LO16); |
4d7206a2 | 8683 | relax_end (); |
ed6fb7bd | 8684 | |
f5040a92 AO |
8685 | if (ex.X_add_number != 0) |
8686 | { | |
8687 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
8688 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
8689 | ex.X_op = O_constant; | |
67c0d1eb | 8690 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 8691 | reg, reg, BFD_RELOC_LO16); |
f5040a92 | 8692 | } |
252b5132 RH |
8693 | } |
8694 | } | |
0a44bf69 | 8695 | else if (mips_big_got) |
252b5132 RH |
8696 | { |
8697 | expressionS ex; | |
252b5132 RH |
8698 | |
8699 | /* This is the large GOT case. If this is a reference to an | |
8700 | external symbol, we want | |
8701 | lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
8702 | addu $reg,$reg,$gp | |
8703 | lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16) | |
f5040a92 AO |
8704 | |
8705 | Otherwise, for a reference to a local symbol in old ABI, we want | |
252b5132 RH |
8706 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) |
8707 | nop | |
8708 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
684022ea | 8709 | If there is a constant, it must be added in after. |
f5040a92 AO |
8710 | |
8711 | In the NewABI, for local symbols, with or without offsets, we want: | |
438c16b8 TS |
8712 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) |
8713 | addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) | |
f5040a92 | 8714 | */ |
438c16b8 TS |
8715 | if (HAVE_NEWABI) |
8716 | { | |
4d7206a2 | 8717 | ex.X_add_number = ep->X_add_number; |
f5040a92 | 8718 | ep->X_add_number = 0; |
4d7206a2 | 8719 | relax_start (ep->X_add_symbol); |
df58fc94 | 8720 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
8721 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
8722 | reg, reg, mips_gp_register); | |
8723 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", | |
8724 | reg, BFD_RELOC_MIPS_GOT_LO16, reg); | |
f5040a92 AO |
8725 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) |
8726 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
8727 | else if (ex.X_add_number) | |
8728 | { | |
8729 | ex.X_op = O_constant; | |
67c0d1eb RS |
8730 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
8731 | BFD_RELOC_LO16); | |
f5040a92 AO |
8732 | } |
8733 | ||
8734 | ep->X_add_number = ex.X_add_number; | |
4d7206a2 | 8735 | relax_switch (); |
67c0d1eb | 8736 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 8737 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); |
67c0d1eb RS |
8738 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
8739 | BFD_RELOC_MIPS_GOT_OFST); | |
4d7206a2 | 8740 | relax_end (); |
438c16b8 | 8741 | } |
252b5132 | 8742 | else |
438c16b8 | 8743 | { |
f5040a92 AO |
8744 | ex.X_add_number = ep->X_add_number; |
8745 | ep->X_add_number = 0; | |
4d7206a2 | 8746 | relax_start (ep->X_add_symbol); |
df58fc94 | 8747 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
8748 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
8749 | reg, reg, mips_gp_register); | |
8750 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", | |
8751 | reg, BFD_RELOC_MIPS_GOT_LO16, reg); | |
4d7206a2 RS |
8752 | relax_switch (); |
8753 | if (reg_needs_delay (mips_gp_register)) | |
438c16b8 TS |
8754 | { |
8755 | /* We need a nop before loading from $gp. This special | |
8756 | check is required because the lui which starts the main | |
8757 | instruction stream does not refer to $gp, and so will not | |
8758 | insert the nop which may be required. */ | |
67c0d1eb | 8759 | macro_build (NULL, "nop", ""); |
438c16b8 | 8760 | } |
67c0d1eb | 8761 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 8762 | BFD_RELOC_MIPS_GOT16, mips_gp_register); |
269137b2 | 8763 | load_delay_nop (); |
67c0d1eb | 8764 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
17a2f251 | 8765 | BFD_RELOC_LO16); |
4d7206a2 | 8766 | relax_end (); |
438c16b8 | 8767 | |
f5040a92 AO |
8768 | if (ex.X_add_number != 0) |
8769 | { | |
8770 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
8771 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
8772 | ex.X_op = O_constant; | |
67c0d1eb RS |
8773 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
8774 | BFD_RELOC_LO16); | |
f5040a92 | 8775 | } |
252b5132 RH |
8776 | } |
8777 | } | |
252b5132 RH |
8778 | else |
8779 | abort (); | |
8fc2e39e | 8780 | |
741fe287 | 8781 | if (!mips_opts.at && *used_at == 1) |
1661c76c | 8782 | as_bad (_("macro used $at after \".set noat\"")); |
252b5132 RH |
8783 | } |
8784 | ||
ea1fb5dc RS |
8785 | /* Move the contents of register SOURCE into register DEST. */ |
8786 | ||
8787 | static void | |
67c0d1eb | 8788 | move_register (int dest, int source) |
ea1fb5dc | 8789 | { |
df58fc94 RS |
8790 | /* Prefer to use a 16-bit microMIPS instruction unless the previous |
8791 | instruction specifically requires a 32-bit one. */ | |
8792 | if (mips_opts.micromips | |
833794fc | 8793 | && !mips_opts.insn32 |
df58fc94 | 8794 | && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) |
7951ca42 | 8795 | macro_build (NULL, "move", "mp,mj", dest, source); |
df58fc94 | 8796 | else |
bad1aba3 | 8797 | macro_build (NULL, GPR_SIZE == 32 ? "addu" : "daddu", "d,v,t", |
df58fc94 | 8798 | dest, source, 0); |
ea1fb5dc RS |
8799 | } |
8800 | ||
4d7206a2 | 8801 | /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where |
f6a22291 MR |
8802 | LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement. |
8803 | The two alternatives are: | |
4d7206a2 RS |
8804 | |
8805 | Global symbol Local sybmol | |
8806 | ------------- ------------ | |
8807 | lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET) | |
8808 | ... ... | |
8809 | addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET) | |
8810 | ||
8811 | load_got_offset emits the first instruction and add_got_offset | |
f6a22291 MR |
8812 | emits the second for a 16-bit offset or add_got_offset_hilo emits |
8813 | a sequence to add a 32-bit offset using a scratch register. */ | |
4d7206a2 RS |
8814 | |
8815 | static void | |
67c0d1eb | 8816 | load_got_offset (int dest, expressionS *local) |
4d7206a2 RS |
8817 | { |
8818 | expressionS global; | |
8819 | ||
8820 | global = *local; | |
8821 | global.X_add_number = 0; | |
8822 | ||
8823 | relax_start (local->X_add_symbol); | |
67c0d1eb RS |
8824 | macro_build (&global, ADDRESS_LOAD_INSN, "t,o(b)", dest, |
8825 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
4d7206a2 | 8826 | relax_switch (); |
67c0d1eb RS |
8827 | macro_build (local, ADDRESS_LOAD_INSN, "t,o(b)", dest, |
8828 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
4d7206a2 RS |
8829 | relax_end (); |
8830 | } | |
8831 | ||
8832 | static void | |
67c0d1eb | 8833 | add_got_offset (int dest, expressionS *local) |
4d7206a2 RS |
8834 | { |
8835 | expressionS global; | |
8836 | ||
8837 | global.X_op = O_constant; | |
8838 | global.X_op_symbol = NULL; | |
8839 | global.X_add_symbol = NULL; | |
8840 | global.X_add_number = local->X_add_number; | |
8841 | ||
8842 | relax_start (local->X_add_symbol); | |
67c0d1eb | 8843 | macro_build (&global, ADDRESS_ADDI_INSN, "t,r,j", |
4d7206a2 RS |
8844 | dest, dest, BFD_RELOC_LO16); |
8845 | relax_switch (); | |
67c0d1eb | 8846 | macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", dest, dest, BFD_RELOC_LO16); |
4d7206a2 RS |
8847 | relax_end (); |
8848 | } | |
8849 | ||
f6a22291 MR |
8850 | static void |
8851 | add_got_offset_hilo (int dest, expressionS *local, int tmp) | |
8852 | { | |
8853 | expressionS global; | |
8854 | int hold_mips_optimize; | |
8855 | ||
8856 | global.X_op = O_constant; | |
8857 | global.X_op_symbol = NULL; | |
8858 | global.X_add_symbol = NULL; | |
8859 | global.X_add_number = local->X_add_number; | |
8860 | ||
8861 | relax_start (local->X_add_symbol); | |
8862 | load_register (tmp, &global, HAVE_64BIT_ADDRESSES); | |
8863 | relax_switch (); | |
8864 | /* Set mips_optimize around the lui instruction to avoid | |
8865 | inserting an unnecessary nop after the lw. */ | |
8866 | hold_mips_optimize = mips_optimize; | |
8867 | mips_optimize = 2; | |
8868 | macro_build_lui (&global, tmp); | |
8869 | mips_optimize = hold_mips_optimize; | |
8870 | macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", tmp, tmp, BFD_RELOC_LO16); | |
8871 | relax_end (); | |
8872 | ||
8873 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dest, dest, tmp); | |
8874 | } | |
8875 | ||
df58fc94 RS |
8876 | /* Emit a sequence of instructions to emulate a branch likely operation. |
8877 | BR is an ordinary branch corresponding to one to be emulated. BRNEG | |
8878 | is its complementing branch with the original condition negated. | |
8879 | CALL is set if the original branch specified the link operation. | |
8880 | EP, FMT, SREG and TREG specify the usual macro_build() parameters. | |
8881 | ||
8882 | Code like this is produced in the noreorder mode: | |
8883 | ||
8884 | BRNEG <args>, 1f | |
8885 | nop | |
8886 | b <sym> | |
8887 | delay slot (executed only if branch taken) | |
8888 | 1: | |
8889 | ||
8890 | or, if CALL is set: | |
8891 | ||
8892 | BRNEG <args>, 1f | |
8893 | nop | |
8894 | bal <sym> | |
8895 | delay slot (executed only if branch taken) | |
8896 | 1: | |
8897 | ||
8898 | In the reorder mode the delay slot would be filled with a nop anyway, | |
8899 | so code produced is simply: | |
8900 | ||
8901 | BR <args>, <sym> | |
8902 | nop | |
8903 | ||
8904 | This function is used when producing code for the microMIPS ASE that | |
8905 | does not implement branch likely instructions in hardware. */ | |
8906 | ||
8907 | static void | |
8908 | macro_build_branch_likely (const char *br, const char *brneg, | |
8909 | int call, expressionS *ep, const char *fmt, | |
8910 | unsigned int sreg, unsigned int treg) | |
8911 | { | |
8912 | int noreorder = mips_opts.noreorder; | |
8913 | expressionS expr1; | |
8914 | ||
8915 | gas_assert (mips_opts.micromips); | |
8916 | start_noreorder (); | |
8917 | if (noreorder) | |
8918 | { | |
8919 | micromips_label_expr (&expr1); | |
8920 | macro_build (&expr1, brneg, fmt, sreg, treg); | |
8921 | macro_build (NULL, "nop", ""); | |
8922 | macro_build (ep, call ? "bal" : "b", "p"); | |
8923 | ||
8924 | /* Set to true so that append_insn adds a label. */ | |
8925 | emit_branch_likely_macro = TRUE; | |
8926 | } | |
8927 | else | |
8928 | { | |
8929 | macro_build (ep, br, fmt, sreg, treg); | |
8930 | macro_build (NULL, "nop", ""); | |
8931 | } | |
8932 | end_noreorder (); | |
8933 | } | |
8934 | ||
8935 | /* Emit a coprocessor branch-likely macro specified by TYPE, using CC as | |
8936 | the condition code tested. EP specifies the branch target. */ | |
8937 | ||
8938 | static void | |
8939 | macro_build_branch_ccl (int type, expressionS *ep, unsigned int cc) | |
8940 | { | |
8941 | const int call = 0; | |
8942 | const char *brneg; | |
8943 | const char *br; | |
8944 | ||
8945 | switch (type) | |
8946 | { | |
8947 | case M_BC1FL: | |
8948 | br = "bc1f"; | |
8949 | brneg = "bc1t"; | |
8950 | break; | |
8951 | case M_BC1TL: | |
8952 | br = "bc1t"; | |
8953 | brneg = "bc1f"; | |
8954 | break; | |
8955 | case M_BC2FL: | |
8956 | br = "bc2f"; | |
8957 | brneg = "bc2t"; | |
8958 | break; | |
8959 | case M_BC2TL: | |
8960 | br = "bc2t"; | |
8961 | brneg = "bc2f"; | |
8962 | break; | |
8963 | default: | |
8964 | abort (); | |
8965 | } | |
8966 | macro_build_branch_likely (br, brneg, call, ep, "N,p", cc, ZERO); | |
8967 | } | |
8968 | ||
8969 | /* Emit a two-argument branch macro specified by TYPE, using SREG as | |
8970 | the register tested. EP specifies the branch target. */ | |
8971 | ||
8972 | static void | |
8973 | macro_build_branch_rs (int type, expressionS *ep, unsigned int sreg) | |
8974 | { | |
8975 | const char *brneg = NULL; | |
8976 | const char *br; | |
8977 | int call = 0; | |
8978 | ||
8979 | switch (type) | |
8980 | { | |
8981 | case M_BGEZ: | |
8982 | br = "bgez"; | |
8983 | break; | |
8984 | case M_BGEZL: | |
8985 | br = mips_opts.micromips ? "bgez" : "bgezl"; | |
8986 | brneg = "bltz"; | |
8987 | break; | |
8988 | case M_BGEZALL: | |
8989 | gas_assert (mips_opts.micromips); | |
833794fc | 8990 | br = mips_opts.insn32 ? "bgezal" : "bgezals"; |
df58fc94 RS |
8991 | brneg = "bltz"; |
8992 | call = 1; | |
8993 | break; | |
8994 | case M_BGTZ: | |
8995 | br = "bgtz"; | |
8996 | break; | |
8997 | case M_BGTZL: | |
8998 | br = mips_opts.micromips ? "bgtz" : "bgtzl"; | |
8999 | brneg = "blez"; | |
9000 | break; | |
9001 | case M_BLEZ: | |
9002 | br = "blez"; | |
9003 | break; | |
9004 | case M_BLEZL: | |
9005 | br = mips_opts.micromips ? "blez" : "blezl"; | |
9006 | brneg = "bgtz"; | |
9007 | break; | |
9008 | case M_BLTZ: | |
9009 | br = "bltz"; | |
9010 | break; | |
9011 | case M_BLTZL: | |
9012 | br = mips_opts.micromips ? "bltz" : "bltzl"; | |
9013 | brneg = "bgez"; | |
9014 | break; | |
9015 | case M_BLTZALL: | |
9016 | gas_assert (mips_opts.micromips); | |
833794fc | 9017 | br = mips_opts.insn32 ? "bltzal" : "bltzals"; |
df58fc94 RS |
9018 | brneg = "bgez"; |
9019 | call = 1; | |
9020 | break; | |
9021 | default: | |
9022 | abort (); | |
9023 | } | |
9024 | if (mips_opts.micromips && brneg) | |
9025 | macro_build_branch_likely (br, brneg, call, ep, "s,p", sreg, ZERO); | |
9026 | else | |
9027 | macro_build (ep, br, "s,p", sreg); | |
9028 | } | |
9029 | ||
9030 | /* Emit a three-argument branch macro specified by TYPE, using SREG and | |
9031 | TREG as the registers tested. EP specifies the branch target. */ | |
9032 | ||
9033 | static void | |
9034 | macro_build_branch_rsrt (int type, expressionS *ep, | |
9035 | unsigned int sreg, unsigned int treg) | |
9036 | { | |
9037 | const char *brneg = NULL; | |
9038 | const int call = 0; | |
9039 | const char *br; | |
9040 | ||
9041 | switch (type) | |
9042 | { | |
9043 | case M_BEQ: | |
9044 | case M_BEQ_I: | |
9045 | br = "beq"; | |
9046 | break; | |
9047 | case M_BEQL: | |
9048 | case M_BEQL_I: | |
9049 | br = mips_opts.micromips ? "beq" : "beql"; | |
9050 | brneg = "bne"; | |
9051 | break; | |
9052 | case M_BNE: | |
9053 | case M_BNE_I: | |
9054 | br = "bne"; | |
9055 | break; | |
9056 | case M_BNEL: | |
9057 | case M_BNEL_I: | |
9058 | br = mips_opts.micromips ? "bne" : "bnel"; | |
9059 | brneg = "beq"; | |
9060 | break; | |
9061 | default: | |
9062 | abort (); | |
9063 | } | |
9064 | if (mips_opts.micromips && brneg) | |
9065 | macro_build_branch_likely (br, brneg, call, ep, "s,t,p", sreg, treg); | |
9066 | else | |
9067 | macro_build (ep, br, "s,t,p", sreg, treg); | |
9068 | } | |
9069 | ||
f2ae14a1 RS |
9070 | /* Return the high part that should be loaded in order to make the low |
9071 | part of VALUE accessible using an offset of OFFBITS bits. */ | |
9072 | ||
9073 | static offsetT | |
9074 | offset_high_part (offsetT value, unsigned int offbits) | |
9075 | { | |
9076 | offsetT bias; | |
9077 | addressT low_mask; | |
9078 | ||
9079 | if (offbits == 0) | |
9080 | return value; | |
9081 | bias = 1 << (offbits - 1); | |
9082 | low_mask = bias * 2 - 1; | |
9083 | return (value + bias) & ~low_mask; | |
9084 | } | |
9085 | ||
9086 | /* Return true if the value stored in offset_expr and offset_reloc | |
9087 | fits into a signed offset of OFFBITS bits. RANGE is the maximum | |
9088 | amount that the caller wants to add without inducing overflow | |
9089 | and ALIGN is the known alignment of the value in bytes. */ | |
9090 | ||
9091 | static bfd_boolean | |
9092 | small_offset_p (unsigned int range, unsigned int align, unsigned int offbits) | |
9093 | { | |
9094 | if (offbits == 16) | |
9095 | { | |
9096 | /* Accept any relocation operator if overflow isn't a concern. */ | |
9097 | if (range < align && *offset_reloc != BFD_RELOC_UNUSED) | |
9098 | return TRUE; | |
9099 | ||
9100 | /* These relocations are guaranteed not to overflow in correct links. */ | |
9101 | if (*offset_reloc == BFD_RELOC_MIPS_LITERAL | |
9102 | || gprel16_reloc_p (*offset_reloc)) | |
9103 | return TRUE; | |
9104 | } | |
9105 | if (offset_expr.X_op == O_constant | |
9106 | && offset_high_part (offset_expr.X_add_number, offbits) == 0 | |
9107 | && offset_high_part (offset_expr.X_add_number + range, offbits) == 0) | |
9108 | return TRUE; | |
9109 | return FALSE; | |
9110 | } | |
9111 | ||
252b5132 RH |
9112 | /* |
9113 | * Build macros | |
9114 | * This routine implements the seemingly endless macro or synthesized | |
9115 | * instructions and addressing modes in the mips assembly language. Many | |
9116 | * of these macros are simple and are similar to each other. These could | |
67c1ffbe | 9117 | * probably be handled by some kind of table or grammar approach instead of |
252b5132 RH |
9118 | * this verbose method. Others are not simple macros but are more like |
9119 | * optimizing code generation. | |
9120 | * One interesting optimization is when several store macros appear | |
67c1ffbe | 9121 | * consecutively that would load AT with the upper half of the same address. |
252b5132 RH |
9122 | * The ensuing load upper instructions are ommited. This implies some kind |
9123 | * of global optimization. We currently only optimize within a single macro. | |
9124 | * For many of the load and store macros if the address is specified as a | |
9125 | * constant expression in the first 64k of memory (ie ld $2,0x4000c) we | |
9126 | * first load register 'at' with zero and use it as the base register. The | |
9127 | * mips assembler simply uses register $zero. Just one tiny optimization | |
9128 | * we're missing. | |
9129 | */ | |
9130 | static void | |
833794fc | 9131 | macro (struct mips_cl_insn *ip, char *str) |
252b5132 | 9132 | { |
c0ebe874 RS |
9133 | const struct mips_operand_array *operands; |
9134 | unsigned int breg, i; | |
741fe287 | 9135 | unsigned int tempreg; |
252b5132 | 9136 | int mask; |
43841e91 | 9137 | int used_at = 0; |
df58fc94 | 9138 | expressionS label_expr; |
252b5132 | 9139 | expressionS expr1; |
df58fc94 | 9140 | expressionS *ep; |
252b5132 RH |
9141 | const char *s; |
9142 | const char *s2; | |
9143 | const char *fmt; | |
9144 | int likely = 0; | |
252b5132 | 9145 | int coproc = 0; |
7f3c4072 | 9146 | int offbits = 16; |
1abe91b1 | 9147 | int call = 0; |
df58fc94 RS |
9148 | int jals = 0; |
9149 | int dbl = 0; | |
9150 | int imm = 0; | |
9151 | int ust = 0; | |
9152 | int lp = 0; | |
f2ae14a1 | 9153 | bfd_boolean large_offset; |
252b5132 | 9154 | int off; |
252b5132 | 9155 | int hold_mips_optimize; |
f2ae14a1 | 9156 | unsigned int align; |
c0ebe874 | 9157 | unsigned int op[MAX_OPERANDS]; |
252b5132 | 9158 | |
9c2799c2 | 9159 | gas_assert (! mips_opts.mips16); |
252b5132 | 9160 | |
c0ebe874 RS |
9161 | operands = insn_operands (ip); |
9162 | for (i = 0; i < MAX_OPERANDS; i++) | |
9163 | if (operands->operand[i]) | |
9164 | op[i] = insn_extract_operand (ip, operands->operand[i]); | |
9165 | else | |
9166 | op[i] = -1; | |
9167 | ||
252b5132 RH |
9168 | mask = ip->insn_mo->mask; |
9169 | ||
df58fc94 RS |
9170 | label_expr.X_op = O_constant; |
9171 | label_expr.X_op_symbol = NULL; | |
9172 | label_expr.X_add_symbol = NULL; | |
9173 | label_expr.X_add_number = 0; | |
9174 | ||
252b5132 RH |
9175 | expr1.X_op = O_constant; |
9176 | expr1.X_op_symbol = NULL; | |
9177 | expr1.X_add_symbol = NULL; | |
9178 | expr1.X_add_number = 1; | |
f2ae14a1 | 9179 | align = 1; |
252b5132 RH |
9180 | |
9181 | switch (mask) | |
9182 | { | |
9183 | case M_DABS: | |
9184 | dbl = 1; | |
9185 | case M_ABS: | |
df58fc94 RS |
9186 | /* bgez $a0,1f |
9187 | move v0,$a0 | |
9188 | sub v0,$zero,$a0 | |
9189 | 1: | |
9190 | */ | |
252b5132 | 9191 | |
7d10b47d | 9192 | start_noreorder (); |
252b5132 | 9193 | |
df58fc94 RS |
9194 | if (mips_opts.micromips) |
9195 | micromips_label_expr (&label_expr); | |
9196 | else | |
9197 | label_expr.X_add_number = 8; | |
c0ebe874 RS |
9198 | macro_build (&label_expr, "bgez", "s,p", op[1]); |
9199 | if (op[0] == op[1]) | |
a605d2b3 | 9200 | macro_build (NULL, "nop", ""); |
252b5132 | 9201 | else |
c0ebe874 RS |
9202 | move_register (op[0], op[1]); |
9203 | macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", op[0], 0, op[1]); | |
df58fc94 RS |
9204 | if (mips_opts.micromips) |
9205 | micromips_add_label (); | |
252b5132 | 9206 | |
7d10b47d | 9207 | end_noreorder (); |
8fc2e39e | 9208 | break; |
252b5132 RH |
9209 | |
9210 | case M_ADD_I: | |
9211 | s = "addi"; | |
9212 | s2 = "add"; | |
9213 | goto do_addi; | |
9214 | case M_ADDU_I: | |
9215 | s = "addiu"; | |
9216 | s2 = "addu"; | |
9217 | goto do_addi; | |
9218 | case M_DADD_I: | |
9219 | dbl = 1; | |
9220 | s = "daddi"; | |
9221 | s2 = "dadd"; | |
df58fc94 RS |
9222 | if (!mips_opts.micromips) |
9223 | goto do_addi; | |
b0e6f033 | 9224 | if (imm_expr.X_add_number >= -0x200 |
df58fc94 RS |
9225 | && imm_expr.X_add_number < 0x200) |
9226 | { | |
b0e6f033 RS |
9227 | macro_build (NULL, s, "t,r,.", op[0], op[1], |
9228 | (int) imm_expr.X_add_number); | |
df58fc94 RS |
9229 | break; |
9230 | } | |
9231 | goto do_addi_i; | |
252b5132 RH |
9232 | case M_DADDU_I: |
9233 | dbl = 1; | |
9234 | s = "daddiu"; | |
9235 | s2 = "daddu"; | |
9236 | do_addi: | |
b0e6f033 | 9237 | if (imm_expr.X_add_number >= -0x8000 |
252b5132 RH |
9238 | && imm_expr.X_add_number < 0x8000) |
9239 | { | |
c0ebe874 | 9240 | macro_build (&imm_expr, s, "t,r,j", op[0], op[1], BFD_RELOC_LO16); |
8fc2e39e | 9241 | break; |
252b5132 | 9242 | } |
df58fc94 | 9243 | do_addi_i: |
8fc2e39e | 9244 | used_at = 1; |
67c0d1eb | 9245 | load_register (AT, &imm_expr, dbl); |
c0ebe874 | 9246 | macro_build (NULL, s2, "d,v,t", op[0], op[1], AT); |
252b5132 RH |
9247 | break; |
9248 | ||
9249 | case M_AND_I: | |
9250 | s = "andi"; | |
9251 | s2 = "and"; | |
9252 | goto do_bit; | |
9253 | case M_OR_I: | |
9254 | s = "ori"; | |
9255 | s2 = "or"; | |
9256 | goto do_bit; | |
9257 | case M_NOR_I: | |
9258 | s = ""; | |
9259 | s2 = "nor"; | |
9260 | goto do_bit; | |
9261 | case M_XOR_I: | |
9262 | s = "xori"; | |
9263 | s2 = "xor"; | |
9264 | do_bit: | |
b0e6f033 | 9265 | if (imm_expr.X_add_number >= 0 |
252b5132 RH |
9266 | && imm_expr.X_add_number < 0x10000) |
9267 | { | |
9268 | if (mask != M_NOR_I) | |
c0ebe874 | 9269 | macro_build (&imm_expr, s, "t,r,i", op[0], op[1], BFD_RELOC_LO16); |
252b5132 RH |
9270 | else |
9271 | { | |
67c0d1eb | 9272 | macro_build (&imm_expr, "ori", "t,r,i", |
c0ebe874 RS |
9273 | op[0], op[1], BFD_RELOC_LO16); |
9274 | macro_build (NULL, "nor", "d,v,t", op[0], op[0], 0); | |
252b5132 | 9275 | } |
8fc2e39e | 9276 | break; |
252b5132 RH |
9277 | } |
9278 | ||
8fc2e39e | 9279 | used_at = 1; |
bad1aba3 | 9280 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
c0ebe874 | 9281 | macro_build (NULL, s2, "d,v,t", op[0], op[1], AT); |
252b5132 RH |
9282 | break; |
9283 | ||
8b082fb1 TS |
9284 | case M_BALIGN: |
9285 | switch (imm_expr.X_add_number) | |
9286 | { | |
9287 | case 0: | |
9288 | macro_build (NULL, "nop", ""); | |
9289 | break; | |
9290 | case 2: | |
c0ebe874 | 9291 | macro_build (NULL, "packrl.ph", "d,s,t", op[0], op[0], op[1]); |
8b082fb1 | 9292 | break; |
03f66e8a MR |
9293 | case 1: |
9294 | case 3: | |
c0ebe874 | 9295 | macro_build (NULL, "balign", "t,s,2", op[0], op[1], |
90ecf173 | 9296 | (int) imm_expr.X_add_number); |
8b082fb1 | 9297 | break; |
03f66e8a MR |
9298 | default: |
9299 | as_bad (_("BALIGN immediate not 0, 1, 2 or 3 (%lu)"), | |
9300 | (unsigned long) imm_expr.X_add_number); | |
9301 | break; | |
8b082fb1 TS |
9302 | } |
9303 | break; | |
9304 | ||
df58fc94 RS |
9305 | case M_BC1FL: |
9306 | case M_BC1TL: | |
9307 | case M_BC2FL: | |
9308 | case M_BC2TL: | |
9309 | gas_assert (mips_opts.micromips); | |
9310 | macro_build_branch_ccl (mask, &offset_expr, | |
9311 | EXTRACT_OPERAND (1, BCC, *ip)); | |
9312 | break; | |
9313 | ||
252b5132 | 9314 | case M_BEQ_I: |
252b5132 | 9315 | case M_BEQL_I: |
252b5132 | 9316 | case M_BNE_I: |
252b5132 | 9317 | case M_BNEL_I: |
b0e6f033 | 9318 | if (imm_expr.X_add_number == 0) |
c0ebe874 | 9319 | op[1] = 0; |
df58fc94 | 9320 | else |
252b5132 | 9321 | { |
c0ebe874 | 9322 | op[1] = AT; |
df58fc94 | 9323 | used_at = 1; |
bad1aba3 | 9324 | load_register (op[1], &imm_expr, GPR_SIZE == 64); |
252b5132 | 9325 | } |
df58fc94 RS |
9326 | /* Fall through. */ |
9327 | case M_BEQL: | |
9328 | case M_BNEL: | |
c0ebe874 | 9329 | macro_build_branch_rsrt (mask, &offset_expr, op[0], op[1]); |
252b5132 RH |
9330 | break; |
9331 | ||
9332 | case M_BGEL: | |
9333 | likely = 1; | |
9334 | case M_BGE: | |
c0ebe874 RS |
9335 | if (op[1] == 0) |
9336 | macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, op[0]); | |
9337 | else if (op[0] == 0) | |
9338 | macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, op[1]); | |
df58fc94 | 9339 | else |
252b5132 | 9340 | { |
df58fc94 | 9341 | used_at = 1; |
c0ebe874 | 9342 | macro_build (NULL, "slt", "d,v,t", AT, op[0], op[1]); |
df58fc94 RS |
9343 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, |
9344 | &offset_expr, AT, ZERO); | |
252b5132 | 9345 | } |
df58fc94 RS |
9346 | break; |
9347 | ||
9348 | case M_BGEZL: | |
9349 | case M_BGEZALL: | |
9350 | case M_BGTZL: | |
9351 | case M_BLEZL: | |
9352 | case M_BLTZL: | |
9353 | case M_BLTZALL: | |
c0ebe874 | 9354 | macro_build_branch_rs (mask, &offset_expr, op[0]); |
252b5132 RH |
9355 | break; |
9356 | ||
9357 | case M_BGTL_I: | |
9358 | likely = 1; | |
9359 | case M_BGT_I: | |
90ecf173 | 9360 | /* Check for > max integer. */ |
b0e6f033 | 9361 | if (imm_expr.X_add_number >= GPR_SMAX) |
252b5132 RH |
9362 | { |
9363 | do_false: | |
90ecf173 | 9364 | /* Result is always false. */ |
252b5132 | 9365 | if (! likely) |
a605d2b3 | 9366 | macro_build (NULL, "nop", ""); |
252b5132 | 9367 | else |
df58fc94 | 9368 | macro_build_branch_rsrt (M_BNEL, &offset_expr, ZERO, ZERO); |
8fc2e39e | 9369 | break; |
252b5132 | 9370 | } |
f9419b05 | 9371 | ++imm_expr.X_add_number; |
252b5132 RH |
9372 | /* FALLTHROUGH */ |
9373 | case M_BGE_I: | |
9374 | case M_BGEL_I: | |
9375 | if (mask == M_BGEL_I) | |
9376 | likely = 1; | |
b0e6f033 | 9377 | if (imm_expr.X_add_number == 0) |
252b5132 | 9378 | { |
df58fc94 | 9379 | macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, |
c0ebe874 | 9380 | &offset_expr, op[0]); |
8fc2e39e | 9381 | break; |
252b5132 | 9382 | } |
b0e6f033 | 9383 | if (imm_expr.X_add_number == 1) |
252b5132 | 9384 | { |
df58fc94 | 9385 | macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, |
c0ebe874 | 9386 | &offset_expr, op[0]); |
8fc2e39e | 9387 | break; |
252b5132 | 9388 | } |
b0e6f033 | 9389 | if (imm_expr.X_add_number <= GPR_SMIN) |
252b5132 RH |
9390 | { |
9391 | do_true: | |
9392 | /* result is always true */ | |
1661c76c | 9393 | as_warn (_("branch %s is always true"), ip->insn_mo->name); |
67c0d1eb | 9394 | macro_build (&offset_expr, "b", "p"); |
8fc2e39e | 9395 | break; |
252b5132 | 9396 | } |
8fc2e39e | 9397 | used_at = 1; |
c0ebe874 | 9398 | set_at (op[0], 0); |
df58fc94 RS |
9399 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, |
9400 | &offset_expr, AT, ZERO); | |
252b5132 RH |
9401 | break; |
9402 | ||
9403 | case M_BGEUL: | |
9404 | likely = 1; | |
9405 | case M_BGEU: | |
c0ebe874 | 9406 | if (op[1] == 0) |
252b5132 | 9407 | goto do_true; |
c0ebe874 | 9408 | else if (op[0] == 0) |
df58fc94 | 9409 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, |
c0ebe874 | 9410 | &offset_expr, ZERO, op[1]); |
df58fc94 | 9411 | else |
252b5132 | 9412 | { |
df58fc94 | 9413 | used_at = 1; |
c0ebe874 | 9414 | macro_build (NULL, "sltu", "d,v,t", AT, op[0], op[1]); |
df58fc94 RS |
9415 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, |
9416 | &offset_expr, AT, ZERO); | |
252b5132 | 9417 | } |
252b5132 RH |
9418 | break; |
9419 | ||
9420 | case M_BGTUL_I: | |
9421 | likely = 1; | |
9422 | case M_BGTU_I: | |
c0ebe874 | 9423 | if (op[0] == 0 |
bad1aba3 | 9424 | || (GPR_SIZE == 32 |
f01dc953 | 9425 | && imm_expr.X_add_number == -1)) |
252b5132 | 9426 | goto do_false; |
f9419b05 | 9427 | ++imm_expr.X_add_number; |
252b5132 RH |
9428 | /* FALLTHROUGH */ |
9429 | case M_BGEU_I: | |
9430 | case M_BGEUL_I: | |
9431 | if (mask == M_BGEUL_I) | |
9432 | likely = 1; | |
b0e6f033 | 9433 | if (imm_expr.X_add_number == 0) |
252b5132 | 9434 | goto do_true; |
b0e6f033 | 9435 | else if (imm_expr.X_add_number == 1) |
df58fc94 | 9436 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, |
c0ebe874 | 9437 | &offset_expr, op[0], ZERO); |
df58fc94 | 9438 | else |
252b5132 | 9439 | { |
df58fc94 | 9440 | used_at = 1; |
c0ebe874 | 9441 | set_at (op[0], 1); |
df58fc94 RS |
9442 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, |
9443 | &offset_expr, AT, ZERO); | |
252b5132 | 9444 | } |
252b5132 RH |
9445 | break; |
9446 | ||
9447 | case M_BGTL: | |
9448 | likely = 1; | |
9449 | case M_BGT: | |
c0ebe874 RS |
9450 | if (op[1] == 0) |
9451 | macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, op[0]); | |
9452 | else if (op[0] == 0) | |
9453 | macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, op[1]); | |
df58fc94 | 9454 | else |
252b5132 | 9455 | { |
df58fc94 | 9456 | used_at = 1; |
c0ebe874 | 9457 | macro_build (NULL, "slt", "d,v,t", AT, op[1], op[0]); |
df58fc94 RS |
9458 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, |
9459 | &offset_expr, AT, ZERO); | |
252b5132 | 9460 | } |
252b5132 RH |
9461 | break; |
9462 | ||
9463 | case M_BGTUL: | |
9464 | likely = 1; | |
9465 | case M_BGTU: | |
c0ebe874 | 9466 | if (op[1] == 0) |
df58fc94 | 9467 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, |
c0ebe874 RS |
9468 | &offset_expr, op[0], ZERO); |
9469 | else if (op[0] == 0) | |
df58fc94 RS |
9470 | goto do_false; |
9471 | else | |
252b5132 | 9472 | { |
df58fc94 | 9473 | used_at = 1; |
c0ebe874 | 9474 | macro_build (NULL, "sltu", "d,v,t", AT, op[1], op[0]); |
df58fc94 RS |
9475 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, |
9476 | &offset_expr, AT, ZERO); | |
252b5132 | 9477 | } |
252b5132 RH |
9478 | break; |
9479 | ||
9480 | case M_BLEL: | |
9481 | likely = 1; | |
9482 | case M_BLE: | |
c0ebe874 RS |
9483 | if (op[1] == 0) |
9484 | macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, op[0]); | |
9485 | else if (op[0] == 0) | |
9486 | macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, op[1]); | |
df58fc94 | 9487 | else |
252b5132 | 9488 | { |
df58fc94 | 9489 | used_at = 1; |
c0ebe874 | 9490 | macro_build (NULL, "slt", "d,v,t", AT, op[1], op[0]); |
df58fc94 RS |
9491 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, |
9492 | &offset_expr, AT, ZERO); | |
252b5132 | 9493 | } |
252b5132 RH |
9494 | break; |
9495 | ||
9496 | case M_BLEL_I: | |
9497 | likely = 1; | |
9498 | case M_BLE_I: | |
b0e6f033 | 9499 | if (imm_expr.X_add_number >= GPR_SMAX) |
252b5132 | 9500 | goto do_true; |
f9419b05 | 9501 | ++imm_expr.X_add_number; |
252b5132 RH |
9502 | /* FALLTHROUGH */ |
9503 | case M_BLT_I: | |
9504 | case M_BLTL_I: | |
9505 | if (mask == M_BLTL_I) | |
9506 | likely = 1; | |
b0e6f033 | 9507 | if (imm_expr.X_add_number == 0) |
c0ebe874 | 9508 | macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, op[0]); |
b0e6f033 | 9509 | else if (imm_expr.X_add_number == 1) |
c0ebe874 | 9510 | macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, op[0]); |
df58fc94 | 9511 | else |
252b5132 | 9512 | { |
df58fc94 | 9513 | used_at = 1; |
c0ebe874 | 9514 | set_at (op[0], 0); |
df58fc94 RS |
9515 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, |
9516 | &offset_expr, AT, ZERO); | |
252b5132 | 9517 | } |
252b5132 RH |
9518 | break; |
9519 | ||
9520 | case M_BLEUL: | |
9521 | likely = 1; | |
9522 | case M_BLEU: | |
c0ebe874 | 9523 | if (op[1] == 0) |
df58fc94 | 9524 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, |
c0ebe874 RS |
9525 | &offset_expr, op[0], ZERO); |
9526 | else if (op[0] == 0) | |
df58fc94 RS |
9527 | goto do_true; |
9528 | else | |
252b5132 | 9529 | { |
df58fc94 | 9530 | used_at = 1; |
c0ebe874 | 9531 | macro_build (NULL, "sltu", "d,v,t", AT, op[1], op[0]); |
df58fc94 RS |
9532 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, |
9533 | &offset_expr, AT, ZERO); | |
252b5132 | 9534 | } |
252b5132 RH |
9535 | break; |
9536 | ||
9537 | case M_BLEUL_I: | |
9538 | likely = 1; | |
9539 | case M_BLEU_I: | |
c0ebe874 | 9540 | if (op[0] == 0 |
bad1aba3 | 9541 | || (GPR_SIZE == 32 |
f01dc953 | 9542 | && imm_expr.X_add_number == -1)) |
252b5132 | 9543 | goto do_true; |
f9419b05 | 9544 | ++imm_expr.X_add_number; |
252b5132 RH |
9545 | /* FALLTHROUGH */ |
9546 | case M_BLTU_I: | |
9547 | case M_BLTUL_I: | |
9548 | if (mask == M_BLTUL_I) | |
9549 | likely = 1; | |
b0e6f033 | 9550 | if (imm_expr.X_add_number == 0) |
252b5132 | 9551 | goto do_false; |
b0e6f033 | 9552 | else if (imm_expr.X_add_number == 1) |
df58fc94 | 9553 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, |
c0ebe874 | 9554 | &offset_expr, op[0], ZERO); |
df58fc94 | 9555 | else |
252b5132 | 9556 | { |
df58fc94 | 9557 | used_at = 1; |
c0ebe874 | 9558 | set_at (op[0], 1); |
df58fc94 RS |
9559 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, |
9560 | &offset_expr, AT, ZERO); | |
252b5132 | 9561 | } |
252b5132 RH |
9562 | break; |
9563 | ||
9564 | case M_BLTL: | |
9565 | likely = 1; | |
9566 | case M_BLT: | |
c0ebe874 RS |
9567 | if (op[1] == 0) |
9568 | macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, op[0]); | |
9569 | else if (op[0] == 0) | |
9570 | macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, op[1]); | |
df58fc94 | 9571 | else |
252b5132 | 9572 | { |
df58fc94 | 9573 | used_at = 1; |
c0ebe874 | 9574 | macro_build (NULL, "slt", "d,v,t", AT, op[0], op[1]); |
df58fc94 RS |
9575 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, |
9576 | &offset_expr, AT, ZERO); | |
252b5132 | 9577 | } |
252b5132 RH |
9578 | break; |
9579 | ||
9580 | case M_BLTUL: | |
9581 | likely = 1; | |
9582 | case M_BLTU: | |
c0ebe874 | 9583 | if (op[1] == 0) |
252b5132 | 9584 | goto do_false; |
c0ebe874 | 9585 | else if (op[0] == 0) |
df58fc94 | 9586 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, |
c0ebe874 | 9587 | &offset_expr, ZERO, op[1]); |
df58fc94 | 9588 | else |
252b5132 | 9589 | { |
df58fc94 | 9590 | used_at = 1; |
c0ebe874 | 9591 | macro_build (NULL, "sltu", "d,v,t", AT, op[0], op[1]); |
df58fc94 RS |
9592 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, |
9593 | &offset_expr, AT, ZERO); | |
252b5132 | 9594 | } |
252b5132 RH |
9595 | break; |
9596 | ||
9597 | case M_DDIV_3: | |
9598 | dbl = 1; | |
9599 | case M_DIV_3: | |
9600 | s = "mflo"; | |
9601 | goto do_div3; | |
9602 | case M_DREM_3: | |
9603 | dbl = 1; | |
9604 | case M_REM_3: | |
9605 | s = "mfhi"; | |
9606 | do_div3: | |
c0ebe874 | 9607 | if (op[2] == 0) |
252b5132 | 9608 | { |
1661c76c | 9609 | as_warn (_("divide by zero")); |
252b5132 | 9610 | if (mips_trap) |
df58fc94 | 9611 | macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7); |
252b5132 | 9612 | else |
df58fc94 | 9613 | macro_build (NULL, "break", BRK_FMT, 7); |
8fc2e39e | 9614 | break; |
252b5132 RH |
9615 | } |
9616 | ||
7d10b47d | 9617 | start_noreorder (); |
252b5132 RH |
9618 | if (mips_trap) |
9619 | { | |
c0ebe874 RS |
9620 | macro_build (NULL, "teq", TRAP_FMT, op[2], ZERO, 7); |
9621 | macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", op[1], op[2]); | |
252b5132 RH |
9622 | } |
9623 | else | |
9624 | { | |
df58fc94 RS |
9625 | if (mips_opts.micromips) |
9626 | micromips_label_expr (&label_expr); | |
9627 | else | |
9628 | label_expr.X_add_number = 8; | |
c0ebe874 RS |
9629 | macro_build (&label_expr, "bne", "s,t,p", op[2], ZERO); |
9630 | macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", op[1], op[2]); | |
df58fc94 RS |
9631 | macro_build (NULL, "break", BRK_FMT, 7); |
9632 | if (mips_opts.micromips) | |
9633 | micromips_add_label (); | |
252b5132 RH |
9634 | } |
9635 | expr1.X_add_number = -1; | |
8fc2e39e | 9636 | used_at = 1; |
f6a22291 | 9637 | load_register (AT, &expr1, dbl); |
df58fc94 RS |
9638 | if (mips_opts.micromips) |
9639 | micromips_label_expr (&label_expr); | |
9640 | else | |
9641 | label_expr.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16); | |
c0ebe874 | 9642 | macro_build (&label_expr, "bne", "s,t,p", op[2], AT); |
252b5132 RH |
9643 | if (dbl) |
9644 | { | |
9645 | expr1.X_add_number = 1; | |
f6a22291 | 9646 | load_register (AT, &expr1, dbl); |
df58fc94 | 9647 | macro_build (NULL, "dsll32", SHFT_FMT, AT, AT, 31); |
252b5132 RH |
9648 | } |
9649 | else | |
9650 | { | |
9651 | expr1.X_add_number = 0x80000000; | |
df58fc94 | 9652 | macro_build (&expr1, "lui", LUI_FMT, AT, BFD_RELOC_HI16); |
252b5132 RH |
9653 | } |
9654 | if (mips_trap) | |
9655 | { | |
c0ebe874 | 9656 | macro_build (NULL, "teq", TRAP_FMT, op[1], AT, 6); |
252b5132 RH |
9657 | /* We want to close the noreorder block as soon as possible, so |
9658 | that later insns are available for delay slot filling. */ | |
7d10b47d | 9659 | end_noreorder (); |
252b5132 RH |
9660 | } |
9661 | else | |
9662 | { | |
df58fc94 RS |
9663 | if (mips_opts.micromips) |
9664 | micromips_label_expr (&label_expr); | |
9665 | else | |
9666 | label_expr.X_add_number = 8; | |
c0ebe874 | 9667 | macro_build (&label_expr, "bne", "s,t,p", op[1], AT); |
a605d2b3 | 9668 | macro_build (NULL, "nop", ""); |
252b5132 RH |
9669 | |
9670 | /* We want to close the noreorder block as soon as possible, so | |
9671 | that later insns are available for delay slot filling. */ | |
7d10b47d | 9672 | end_noreorder (); |
252b5132 | 9673 | |
df58fc94 | 9674 | macro_build (NULL, "break", BRK_FMT, 6); |
252b5132 | 9675 | } |
df58fc94 RS |
9676 | if (mips_opts.micromips) |
9677 | micromips_add_label (); | |
c0ebe874 | 9678 | macro_build (NULL, s, MFHL_FMT, op[0]); |
252b5132 RH |
9679 | break; |
9680 | ||
9681 | case M_DIV_3I: | |
9682 | s = "div"; | |
9683 | s2 = "mflo"; | |
9684 | goto do_divi; | |
9685 | case M_DIVU_3I: | |
9686 | s = "divu"; | |
9687 | s2 = "mflo"; | |
9688 | goto do_divi; | |
9689 | case M_REM_3I: | |
9690 | s = "div"; | |
9691 | s2 = "mfhi"; | |
9692 | goto do_divi; | |
9693 | case M_REMU_3I: | |
9694 | s = "divu"; | |
9695 | s2 = "mfhi"; | |
9696 | goto do_divi; | |
9697 | case M_DDIV_3I: | |
9698 | dbl = 1; | |
9699 | s = "ddiv"; | |
9700 | s2 = "mflo"; | |
9701 | goto do_divi; | |
9702 | case M_DDIVU_3I: | |
9703 | dbl = 1; | |
9704 | s = "ddivu"; | |
9705 | s2 = "mflo"; | |
9706 | goto do_divi; | |
9707 | case M_DREM_3I: | |
9708 | dbl = 1; | |
9709 | s = "ddiv"; | |
9710 | s2 = "mfhi"; | |
9711 | goto do_divi; | |
9712 | case M_DREMU_3I: | |
9713 | dbl = 1; | |
9714 | s = "ddivu"; | |
9715 | s2 = "mfhi"; | |
9716 | do_divi: | |
b0e6f033 | 9717 | if (imm_expr.X_add_number == 0) |
252b5132 | 9718 | { |
1661c76c | 9719 | as_warn (_("divide by zero")); |
252b5132 | 9720 | if (mips_trap) |
df58fc94 | 9721 | macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7); |
252b5132 | 9722 | else |
df58fc94 | 9723 | macro_build (NULL, "break", BRK_FMT, 7); |
8fc2e39e | 9724 | break; |
252b5132 | 9725 | } |
b0e6f033 | 9726 | if (imm_expr.X_add_number == 1) |
252b5132 RH |
9727 | { |
9728 | if (strcmp (s2, "mflo") == 0) | |
c0ebe874 | 9729 | move_register (op[0], op[1]); |
252b5132 | 9730 | else |
c0ebe874 | 9731 | move_register (op[0], ZERO); |
8fc2e39e | 9732 | break; |
252b5132 | 9733 | } |
b0e6f033 | 9734 | if (imm_expr.X_add_number == -1 && s[strlen (s) - 1] != 'u') |
252b5132 RH |
9735 | { |
9736 | if (strcmp (s2, "mflo") == 0) | |
c0ebe874 | 9737 | macro_build (NULL, dbl ? "dneg" : "neg", "d,w", op[0], op[1]); |
252b5132 | 9738 | else |
c0ebe874 | 9739 | move_register (op[0], ZERO); |
8fc2e39e | 9740 | break; |
252b5132 RH |
9741 | } |
9742 | ||
8fc2e39e | 9743 | used_at = 1; |
67c0d1eb | 9744 | load_register (AT, &imm_expr, dbl); |
c0ebe874 RS |
9745 | macro_build (NULL, s, "z,s,t", op[1], AT); |
9746 | macro_build (NULL, s2, MFHL_FMT, op[0]); | |
252b5132 RH |
9747 | break; |
9748 | ||
9749 | case M_DIVU_3: | |
9750 | s = "divu"; | |
9751 | s2 = "mflo"; | |
9752 | goto do_divu3; | |
9753 | case M_REMU_3: | |
9754 | s = "divu"; | |
9755 | s2 = "mfhi"; | |
9756 | goto do_divu3; | |
9757 | case M_DDIVU_3: | |
9758 | s = "ddivu"; | |
9759 | s2 = "mflo"; | |
9760 | goto do_divu3; | |
9761 | case M_DREMU_3: | |
9762 | s = "ddivu"; | |
9763 | s2 = "mfhi"; | |
9764 | do_divu3: | |
7d10b47d | 9765 | start_noreorder (); |
252b5132 RH |
9766 | if (mips_trap) |
9767 | { | |
c0ebe874 RS |
9768 | macro_build (NULL, "teq", TRAP_FMT, op[2], ZERO, 7); |
9769 | macro_build (NULL, s, "z,s,t", op[1], op[2]); | |
252b5132 RH |
9770 | /* We want to close the noreorder block as soon as possible, so |
9771 | that later insns are available for delay slot filling. */ | |
7d10b47d | 9772 | end_noreorder (); |
252b5132 RH |
9773 | } |
9774 | else | |
9775 | { | |
df58fc94 RS |
9776 | if (mips_opts.micromips) |
9777 | micromips_label_expr (&label_expr); | |
9778 | else | |
9779 | label_expr.X_add_number = 8; | |
c0ebe874 RS |
9780 | macro_build (&label_expr, "bne", "s,t,p", op[2], ZERO); |
9781 | macro_build (NULL, s, "z,s,t", op[1], op[2]); | |
252b5132 RH |
9782 | |
9783 | /* We want to close the noreorder block as soon as possible, so | |
9784 | that later insns are available for delay slot filling. */ | |
7d10b47d | 9785 | end_noreorder (); |
df58fc94 RS |
9786 | macro_build (NULL, "break", BRK_FMT, 7); |
9787 | if (mips_opts.micromips) | |
9788 | micromips_add_label (); | |
252b5132 | 9789 | } |
c0ebe874 | 9790 | macro_build (NULL, s2, MFHL_FMT, op[0]); |
8fc2e39e | 9791 | break; |
252b5132 | 9792 | |
1abe91b1 MR |
9793 | case M_DLCA_AB: |
9794 | dbl = 1; | |
9795 | case M_LCA_AB: | |
9796 | call = 1; | |
9797 | goto do_la; | |
252b5132 RH |
9798 | case M_DLA_AB: |
9799 | dbl = 1; | |
9800 | case M_LA_AB: | |
1abe91b1 | 9801 | do_la: |
252b5132 RH |
9802 | /* Load the address of a symbol into a register. If breg is not |
9803 | zero, we then add a base register to it. */ | |
9804 | ||
c0ebe874 | 9805 | breg = op[2]; |
bad1aba3 | 9806 | if (dbl && GPR_SIZE == 32) |
3bec30a8 TS |
9807 | as_warn (_("dla used to load 32-bit register")); |
9808 | ||
90ecf173 | 9809 | if (!dbl && HAVE_64BIT_OBJECTS) |
3bec30a8 TS |
9810 | as_warn (_("la used to load 64-bit address")); |
9811 | ||
f2ae14a1 | 9812 | if (small_offset_p (0, align, 16)) |
0c11417f | 9813 | { |
c0ebe874 | 9814 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", op[0], breg, |
f2ae14a1 | 9815 | -1, offset_reloc[0], offset_reloc[1], offset_reloc[2]); |
8fc2e39e | 9816 | break; |
0c11417f MR |
9817 | } |
9818 | ||
c0ebe874 | 9819 | if (mips_opts.at && (op[0] == breg)) |
afdbd6d0 CD |
9820 | { |
9821 | tempreg = AT; | |
9822 | used_at = 1; | |
9823 | } | |
9824 | else | |
c0ebe874 | 9825 | tempreg = op[0]; |
afdbd6d0 | 9826 | |
252b5132 RH |
9827 | if (offset_expr.X_op != O_symbol |
9828 | && offset_expr.X_op != O_constant) | |
9829 | { | |
1661c76c | 9830 | as_bad (_("expression too complex")); |
252b5132 RH |
9831 | offset_expr.X_op = O_constant; |
9832 | } | |
9833 | ||
252b5132 | 9834 | if (offset_expr.X_op == O_constant) |
aed1a261 | 9835 | load_register (tempreg, &offset_expr, HAVE_64BIT_ADDRESSES); |
252b5132 RH |
9836 | else if (mips_pic == NO_PIC) |
9837 | { | |
d6bc6245 | 9838 | /* If this is a reference to a GP relative symbol, we want |
cdf6fd85 | 9839 | addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
9840 | Otherwise we want |
9841 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
9842 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
9843 | If we have a constant, we need two instructions anyhow, | |
d6bc6245 | 9844 | so we may as well always use the latter form. |
76b3015f | 9845 | |
6caf9ef4 TS |
9846 | With 64bit address space and a usable $at we want |
9847 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
9848 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
9849 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
9850 | daddiu $at,<sym> (BFD_RELOC_LO16) | |
9851 | dsll32 $tempreg,0 | |
9852 | daddu $tempreg,$tempreg,$at | |
9853 | ||
9854 | If $at is already in use, we use a path which is suboptimal | |
9855 | on superscalar processors. | |
9856 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
9857 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
9858 | dsll $tempreg,16 | |
9859 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
9860 | dsll $tempreg,16 | |
9861 | daddiu $tempreg,<sym> (BFD_RELOC_LO16) | |
9862 | ||
9863 | For GP relative symbols in 64bit address space we can use | |
9864 | the same sequence as in 32bit address space. */ | |
aed1a261 | 9865 | if (HAVE_64BIT_SYMBOLS) |
252b5132 | 9866 | { |
6caf9ef4 TS |
9867 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
9868 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) | |
9869 | { | |
9870 | relax_start (offset_expr.X_add_symbol); | |
9871 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
9872 | tempreg, mips_gp_register, BFD_RELOC_GPREL16); | |
9873 | relax_switch (); | |
9874 | } | |
d6bc6245 | 9875 | |
741fe287 | 9876 | if (used_at == 0 && mips_opts.at) |
98d3f06f | 9877 | { |
df58fc94 | 9878 | macro_build (&offset_expr, "lui", LUI_FMT, |
17a2f251 | 9879 | tempreg, BFD_RELOC_MIPS_HIGHEST); |
df58fc94 | 9880 | macro_build (&offset_expr, "lui", LUI_FMT, |
17a2f251 | 9881 | AT, BFD_RELOC_HI16_S); |
67c0d1eb | 9882 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 9883 | tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); |
67c0d1eb | 9884 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 9885 | AT, AT, BFD_RELOC_LO16); |
df58fc94 | 9886 | macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0); |
67c0d1eb | 9887 | macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT); |
98d3f06f KH |
9888 | used_at = 1; |
9889 | } | |
9890 | else | |
9891 | { | |
df58fc94 | 9892 | macro_build (&offset_expr, "lui", LUI_FMT, |
17a2f251 | 9893 | tempreg, BFD_RELOC_MIPS_HIGHEST); |
67c0d1eb | 9894 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 9895 | tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); |
df58fc94 | 9896 | macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16); |
67c0d1eb | 9897 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 9898 | tempreg, tempreg, BFD_RELOC_HI16_S); |
df58fc94 | 9899 | macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16); |
67c0d1eb | 9900 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 9901 | tempreg, tempreg, BFD_RELOC_LO16); |
98d3f06f | 9902 | } |
6caf9ef4 TS |
9903 | |
9904 | if (mips_relax.sequence) | |
9905 | relax_end (); | |
98d3f06f KH |
9906 | } |
9907 | else | |
9908 | { | |
9909 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET | |
6caf9ef4 | 9910 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
98d3f06f | 9911 | { |
4d7206a2 | 9912 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
9913 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
9914 | tempreg, mips_gp_register, BFD_RELOC_GPREL16); | |
4d7206a2 | 9915 | relax_switch (); |
98d3f06f | 9916 | } |
6943caf0 | 9917 | if (!IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) |
1661c76c | 9918 | as_bad (_("offset too large")); |
67c0d1eb RS |
9919 | macro_build_lui (&offset_expr, tempreg); |
9920 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
9921 | tempreg, tempreg, BFD_RELOC_LO16); | |
4d7206a2 RS |
9922 | if (mips_relax.sequence) |
9923 | relax_end (); | |
98d3f06f | 9924 | } |
252b5132 | 9925 | } |
0a44bf69 | 9926 | else if (!mips_big_got && !HAVE_NEWABI) |
252b5132 | 9927 | { |
9117d219 NC |
9928 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
9929 | ||
252b5132 RH |
9930 | /* If this is a reference to an external symbol, and there |
9931 | is no constant, we want | |
9932 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
1abe91b1 | 9933 | or for lca or if tempreg is PIC_CALL_REG |
9117d219 | 9934 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
252b5132 RH |
9935 | For a local symbol, we want |
9936 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
9937 | nop | |
9938 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
9939 | ||
9940 | If we have a small constant, and this is a reference to | |
9941 | an external symbol, we want | |
9942 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
9943 | nop | |
9944 | addiu $tempreg,$tempreg,<constant> | |
9945 | For a local symbol, we want the same instruction | |
9946 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
9947 | addiu instruction. | |
9948 | ||
9949 | If we have a large constant, and this is a reference to | |
9950 | an external symbol, we want | |
9951 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
9952 | lui $at,<hiconstant> | |
9953 | addiu $at,$at,<loconstant> | |
9954 | addu $tempreg,$tempreg,$at | |
9955 | For a local symbol, we want the same instruction | |
9956 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
ed6fb7bd | 9957 | addiu instruction. |
ed6fb7bd SC |
9958 | */ |
9959 | ||
4d7206a2 | 9960 | if (offset_expr.X_add_number == 0) |
252b5132 | 9961 | { |
0a44bf69 RS |
9962 | if (mips_pic == SVR4_PIC |
9963 | && breg == 0 | |
9964 | && (call || tempreg == PIC_CALL_REG)) | |
4d7206a2 RS |
9965 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16; |
9966 | ||
9967 | relax_start (offset_expr.X_add_symbol); | |
67c0d1eb RS |
9968 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
9969 | lw_reloc_type, mips_gp_register); | |
4d7206a2 | 9970 | if (breg != 0) |
252b5132 RH |
9971 | { |
9972 | /* We're going to put in an addu instruction using | |
9973 | tempreg, so we may as well insert the nop right | |
9974 | now. */ | |
269137b2 | 9975 | load_delay_nop (); |
252b5132 | 9976 | } |
4d7206a2 | 9977 | relax_switch (); |
67c0d1eb RS |
9978 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
9979 | tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 9980 | load_delay_nop (); |
67c0d1eb RS |
9981 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
9982 | tempreg, tempreg, BFD_RELOC_LO16); | |
4d7206a2 | 9983 | relax_end (); |
252b5132 RH |
9984 | /* FIXME: If breg == 0, and the next instruction uses |
9985 | $tempreg, then if this variant case is used an extra | |
9986 | nop will be generated. */ | |
9987 | } | |
4d7206a2 RS |
9988 | else if (offset_expr.X_add_number >= -0x8000 |
9989 | && offset_expr.X_add_number < 0x8000) | |
252b5132 | 9990 | { |
67c0d1eb | 9991 | load_got_offset (tempreg, &offset_expr); |
269137b2 | 9992 | load_delay_nop (); |
67c0d1eb | 9993 | add_got_offset (tempreg, &offset_expr); |
252b5132 RH |
9994 | } |
9995 | else | |
9996 | { | |
4d7206a2 RS |
9997 | expr1.X_add_number = offset_expr.X_add_number; |
9998 | offset_expr.X_add_number = | |
43c0598f | 9999 | SEXT_16BIT (offset_expr.X_add_number); |
67c0d1eb | 10000 | load_got_offset (tempreg, &offset_expr); |
f6a22291 | 10001 | offset_expr.X_add_number = expr1.X_add_number; |
252b5132 RH |
10002 | /* If we are going to add in a base register, and the |
10003 | target register and the base register are the same, | |
10004 | then we are using AT as a temporary register. Since | |
10005 | we want to load the constant into AT, we add our | |
10006 | current AT (from the global offset table) and the | |
10007 | register into the register now, and pretend we were | |
10008 | not using a base register. */ | |
c0ebe874 | 10009 | if (breg == op[0]) |
252b5132 | 10010 | { |
269137b2 | 10011 | load_delay_nop (); |
67c0d1eb | 10012 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
c0ebe874 | 10013 | op[0], AT, breg); |
252b5132 | 10014 | breg = 0; |
c0ebe874 | 10015 | tempreg = op[0]; |
252b5132 | 10016 | } |
f6a22291 | 10017 | add_got_offset_hilo (tempreg, &offset_expr, AT); |
252b5132 RH |
10018 | used_at = 1; |
10019 | } | |
10020 | } | |
0a44bf69 | 10021 | else if (!mips_big_got && HAVE_NEWABI) |
f5040a92 | 10022 | { |
67c0d1eb | 10023 | int add_breg_early = 0; |
f5040a92 AO |
10024 | |
10025 | /* If this is a reference to an external, and there is no | |
10026 | constant, or local symbol (*), with or without a | |
10027 | constant, we want | |
10028 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
1abe91b1 | 10029 | or for lca or if tempreg is PIC_CALL_REG |
f5040a92 AO |
10030 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
10031 | ||
10032 | If we have a small constant, and this is a reference to | |
10033 | an external symbol, we want | |
10034 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
10035 | addiu $tempreg,$tempreg,<constant> | |
10036 | ||
10037 | If we have a large constant, and this is a reference to | |
10038 | an external symbol, we want | |
10039 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
10040 | lui $at,<hiconstant> | |
10041 | addiu $at,$at,<loconstant> | |
10042 | addu $tempreg,$tempreg,$at | |
10043 | ||
10044 | (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for | |
10045 | local symbols, even though it introduces an additional | |
10046 | instruction. */ | |
10047 | ||
f5040a92 AO |
10048 | if (offset_expr.X_add_number) |
10049 | { | |
4d7206a2 | 10050 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
10051 | offset_expr.X_add_number = 0; |
10052 | ||
4d7206a2 | 10053 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
10054 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
10055 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
10056 | |
10057 | if (expr1.X_add_number >= -0x8000 | |
10058 | && expr1.X_add_number < 0x8000) | |
10059 | { | |
67c0d1eb RS |
10060 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
10061 | tempreg, tempreg, BFD_RELOC_LO16); | |
f5040a92 | 10062 | } |
ecd13cd3 | 10063 | else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000)) |
f5040a92 | 10064 | { |
c0ebe874 RS |
10065 | unsigned int dreg; |
10066 | ||
f5040a92 AO |
10067 | /* If we are going to add in a base register, and the |
10068 | target register and the base register are the same, | |
10069 | then we are using AT as a temporary register. Since | |
10070 | we want to load the constant into AT, we add our | |
10071 | current AT (from the global offset table) and the | |
10072 | register into the register now, and pretend we were | |
10073 | not using a base register. */ | |
c0ebe874 | 10074 | if (breg != op[0]) |
f5040a92 AO |
10075 | dreg = tempreg; |
10076 | else | |
10077 | { | |
9c2799c2 | 10078 | gas_assert (tempreg == AT); |
67c0d1eb | 10079 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
c0ebe874 RS |
10080 | op[0], AT, breg); |
10081 | dreg = op[0]; | |
67c0d1eb | 10082 | add_breg_early = 1; |
f5040a92 AO |
10083 | } |
10084 | ||
f6a22291 | 10085 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 10086 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 10087 | dreg, dreg, AT); |
f5040a92 | 10088 | |
f5040a92 AO |
10089 | used_at = 1; |
10090 | } | |
10091 | else | |
10092 | as_bad (_("PIC code offset overflow (max 32 signed bits)")); | |
10093 | ||
4d7206a2 | 10094 | relax_switch (); |
f5040a92 AO |
10095 | offset_expr.X_add_number = expr1.X_add_number; |
10096 | ||
67c0d1eb RS |
10097 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
10098 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
10099 | if (add_breg_early) | |
f5040a92 | 10100 | { |
67c0d1eb | 10101 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
c0ebe874 | 10102 | op[0], tempreg, breg); |
f5040a92 | 10103 | breg = 0; |
c0ebe874 | 10104 | tempreg = op[0]; |
f5040a92 | 10105 | } |
4d7206a2 | 10106 | relax_end (); |
f5040a92 | 10107 | } |
4d7206a2 | 10108 | else if (breg == 0 && (call || tempreg == PIC_CALL_REG)) |
f5040a92 | 10109 | { |
4d7206a2 | 10110 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
10111 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
10112 | BFD_RELOC_MIPS_CALL16, mips_gp_register); | |
4d7206a2 | 10113 | relax_switch (); |
67c0d1eb RS |
10114 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
10115 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
4d7206a2 | 10116 | relax_end (); |
f5040a92 | 10117 | } |
4d7206a2 | 10118 | else |
f5040a92 | 10119 | { |
67c0d1eb RS |
10120 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
10121 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
10122 | } |
10123 | } | |
0a44bf69 | 10124 | else if (mips_big_got && !HAVE_NEWABI) |
252b5132 | 10125 | { |
67c0d1eb | 10126 | int gpdelay; |
9117d219 NC |
10127 | int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; |
10128 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; | |
ed6fb7bd | 10129 | int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
252b5132 RH |
10130 | |
10131 | /* This is the large GOT case. If this is a reference to an | |
10132 | external symbol, and there is no constant, we want | |
10133 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
10134 | addu $tempreg,$tempreg,$gp | |
10135 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
1abe91b1 | 10136 | or for lca or if tempreg is PIC_CALL_REG |
9117d219 NC |
10137 | lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) |
10138 | addu $tempreg,$tempreg,$gp | |
10139 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) | |
252b5132 RH |
10140 | For a local symbol, we want |
10141 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
10142 | nop | |
10143 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
10144 | ||
10145 | If we have a small constant, and this is a reference to | |
10146 | an external symbol, we want | |
10147 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
10148 | addu $tempreg,$tempreg,$gp | |
10149 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
10150 | nop | |
10151 | addiu $tempreg,$tempreg,<constant> | |
10152 | For a local symbol, we want | |
10153 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
10154 | nop | |
10155 | addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16) | |
10156 | ||
10157 | If we have a large constant, and this is a reference to | |
10158 | an external symbol, we want | |
10159 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
10160 | addu $tempreg,$tempreg,$gp | |
10161 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
10162 | lui $at,<hiconstant> | |
10163 | addiu $at,$at,<loconstant> | |
10164 | addu $tempreg,$tempreg,$at | |
10165 | For a local symbol, we want | |
10166 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
10167 | lui $at,<hiconstant> | |
10168 | addiu $at,$at,<loconstant> (BFD_RELOC_LO16) | |
10169 | addu $tempreg,$tempreg,$at | |
f5040a92 | 10170 | */ |
438c16b8 | 10171 | |
252b5132 RH |
10172 | expr1.X_add_number = offset_expr.X_add_number; |
10173 | offset_expr.X_add_number = 0; | |
4d7206a2 | 10174 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 10175 | gpdelay = reg_needs_delay (mips_gp_register); |
1abe91b1 MR |
10176 | if (expr1.X_add_number == 0 && breg == 0 |
10177 | && (call || tempreg == PIC_CALL_REG)) | |
9117d219 NC |
10178 | { |
10179 | lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; | |
10180 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; | |
10181 | } | |
df58fc94 | 10182 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type); |
67c0d1eb | 10183 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 10184 | tempreg, tempreg, mips_gp_register); |
67c0d1eb | 10185 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
17a2f251 | 10186 | tempreg, lw_reloc_type, tempreg); |
252b5132 RH |
10187 | if (expr1.X_add_number == 0) |
10188 | { | |
67c0d1eb | 10189 | if (breg != 0) |
252b5132 RH |
10190 | { |
10191 | /* We're going to put in an addu instruction using | |
10192 | tempreg, so we may as well insert the nop right | |
10193 | now. */ | |
269137b2 | 10194 | load_delay_nop (); |
252b5132 | 10195 | } |
252b5132 RH |
10196 | } |
10197 | else if (expr1.X_add_number >= -0x8000 | |
10198 | && expr1.X_add_number < 0x8000) | |
10199 | { | |
269137b2 | 10200 | load_delay_nop (); |
67c0d1eb | 10201 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 10202 | tempreg, tempreg, BFD_RELOC_LO16); |
252b5132 RH |
10203 | } |
10204 | else | |
10205 | { | |
c0ebe874 RS |
10206 | unsigned int dreg; |
10207 | ||
252b5132 RH |
10208 | /* If we are going to add in a base register, and the |
10209 | target register and the base register are the same, | |
10210 | then we are using AT as a temporary register. Since | |
10211 | we want to load the constant into AT, we add our | |
10212 | current AT (from the global offset table) and the | |
10213 | register into the register now, and pretend we were | |
10214 | not using a base register. */ | |
c0ebe874 | 10215 | if (breg != op[0]) |
67c0d1eb | 10216 | dreg = tempreg; |
252b5132 RH |
10217 | else |
10218 | { | |
9c2799c2 | 10219 | gas_assert (tempreg == AT); |
269137b2 | 10220 | load_delay_nop (); |
67c0d1eb | 10221 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
c0ebe874 RS |
10222 | op[0], AT, breg); |
10223 | dreg = op[0]; | |
252b5132 RH |
10224 | } |
10225 | ||
f6a22291 | 10226 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 10227 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT); |
252b5132 | 10228 | |
252b5132 RH |
10229 | used_at = 1; |
10230 | } | |
43c0598f | 10231 | offset_expr.X_add_number = SEXT_16BIT (expr1.X_add_number); |
4d7206a2 | 10232 | relax_switch (); |
252b5132 | 10233 | |
67c0d1eb | 10234 | if (gpdelay) |
252b5132 RH |
10235 | { |
10236 | /* This is needed because this instruction uses $gp, but | |
f5040a92 | 10237 | the first instruction on the main stream does not. */ |
67c0d1eb | 10238 | macro_build (NULL, "nop", ""); |
252b5132 | 10239 | } |
ed6fb7bd | 10240 | |
67c0d1eb RS |
10241 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
10242 | local_reloc_type, mips_gp_register); | |
f5040a92 | 10243 | if (expr1.X_add_number >= -0x8000 |
252b5132 RH |
10244 | && expr1.X_add_number < 0x8000) |
10245 | { | |
269137b2 | 10246 | load_delay_nop (); |
67c0d1eb RS |
10247 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
10248 | tempreg, tempreg, BFD_RELOC_LO16); | |
252b5132 | 10249 | /* FIXME: If add_number is 0, and there was no base |
f5040a92 AO |
10250 | register, the external symbol case ended with a load, |
10251 | so if the symbol turns out to not be external, and | |
10252 | the next instruction uses tempreg, an unnecessary nop | |
10253 | will be inserted. */ | |
252b5132 RH |
10254 | } |
10255 | else | |
10256 | { | |
c0ebe874 | 10257 | if (breg == op[0]) |
252b5132 RH |
10258 | { |
10259 | /* We must add in the base register now, as in the | |
f5040a92 | 10260 | external symbol case. */ |
9c2799c2 | 10261 | gas_assert (tempreg == AT); |
269137b2 | 10262 | load_delay_nop (); |
67c0d1eb | 10263 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
c0ebe874 RS |
10264 | op[0], AT, breg); |
10265 | tempreg = op[0]; | |
252b5132 | 10266 | /* We set breg to 0 because we have arranged to add |
f5040a92 | 10267 | it in in both cases. */ |
252b5132 RH |
10268 | breg = 0; |
10269 | } | |
10270 | ||
67c0d1eb RS |
10271 | macro_build_lui (&expr1, AT); |
10272 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
17a2f251 | 10273 | AT, AT, BFD_RELOC_LO16); |
67c0d1eb | 10274 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 10275 | tempreg, tempreg, AT); |
8fc2e39e | 10276 | used_at = 1; |
252b5132 | 10277 | } |
4d7206a2 | 10278 | relax_end (); |
252b5132 | 10279 | } |
0a44bf69 | 10280 | else if (mips_big_got && HAVE_NEWABI) |
f5040a92 | 10281 | { |
f5040a92 AO |
10282 | int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; |
10283 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; | |
67c0d1eb | 10284 | int add_breg_early = 0; |
f5040a92 AO |
10285 | |
10286 | /* This is the large GOT case. If this is a reference to an | |
10287 | external symbol, and there is no constant, we want | |
10288 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
10289 | add $tempreg,$tempreg,$gp | |
10290 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
1abe91b1 | 10291 | or for lca or if tempreg is PIC_CALL_REG |
f5040a92 AO |
10292 | lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) |
10293 | add $tempreg,$tempreg,$gp | |
10294 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) | |
10295 | ||
10296 | If we have a small constant, and this is a reference to | |
10297 | an external symbol, we want | |
10298 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
10299 | add $tempreg,$tempreg,$gp | |
10300 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
10301 | addi $tempreg,$tempreg,<constant> | |
10302 | ||
10303 | If we have a large constant, and this is a reference to | |
10304 | an external symbol, we want | |
10305 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
10306 | addu $tempreg,$tempreg,$gp | |
10307 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
10308 | lui $at,<hiconstant> | |
10309 | addi $at,$at,<loconstant> | |
10310 | add $tempreg,$tempreg,$at | |
10311 | ||
10312 | If we have NewABI, and we know it's a local symbol, we want | |
10313 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
10314 | addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) | |
10315 | otherwise we have to resort to GOT_HI16/GOT_LO16. */ | |
10316 | ||
4d7206a2 | 10317 | relax_start (offset_expr.X_add_symbol); |
f5040a92 | 10318 | |
4d7206a2 | 10319 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
10320 | offset_expr.X_add_number = 0; |
10321 | ||
1abe91b1 MR |
10322 | if (expr1.X_add_number == 0 && breg == 0 |
10323 | && (call || tempreg == PIC_CALL_REG)) | |
f5040a92 AO |
10324 | { |
10325 | lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; | |
10326 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; | |
10327 | } | |
df58fc94 | 10328 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type); |
67c0d1eb | 10329 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 10330 | tempreg, tempreg, mips_gp_register); |
67c0d1eb RS |
10331 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
10332 | tempreg, lw_reloc_type, tempreg); | |
f5040a92 AO |
10333 | |
10334 | if (expr1.X_add_number == 0) | |
4d7206a2 | 10335 | ; |
f5040a92 AO |
10336 | else if (expr1.X_add_number >= -0x8000 |
10337 | && expr1.X_add_number < 0x8000) | |
10338 | { | |
67c0d1eb | 10339 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 10340 | tempreg, tempreg, BFD_RELOC_LO16); |
f5040a92 | 10341 | } |
ecd13cd3 | 10342 | else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000)) |
f5040a92 | 10343 | { |
c0ebe874 RS |
10344 | unsigned int dreg; |
10345 | ||
f5040a92 AO |
10346 | /* If we are going to add in a base register, and the |
10347 | target register and the base register are the same, | |
10348 | then we are using AT as a temporary register. Since | |
10349 | we want to load the constant into AT, we add our | |
10350 | current AT (from the global offset table) and the | |
10351 | register into the register now, and pretend we were | |
10352 | not using a base register. */ | |
c0ebe874 | 10353 | if (breg != op[0]) |
f5040a92 AO |
10354 | dreg = tempreg; |
10355 | else | |
10356 | { | |
9c2799c2 | 10357 | gas_assert (tempreg == AT); |
67c0d1eb | 10358 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
c0ebe874 RS |
10359 | op[0], AT, breg); |
10360 | dreg = op[0]; | |
67c0d1eb | 10361 | add_breg_early = 1; |
f5040a92 AO |
10362 | } |
10363 | ||
f6a22291 | 10364 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 10365 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT); |
f5040a92 | 10366 | |
f5040a92 AO |
10367 | used_at = 1; |
10368 | } | |
10369 | else | |
10370 | as_bad (_("PIC code offset overflow (max 32 signed bits)")); | |
10371 | ||
4d7206a2 | 10372 | relax_switch (); |
f5040a92 | 10373 | offset_expr.X_add_number = expr1.X_add_number; |
67c0d1eb RS |
10374 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
10375 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
10376 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, | |
10377 | tempreg, BFD_RELOC_MIPS_GOT_OFST); | |
10378 | if (add_breg_early) | |
f5040a92 | 10379 | { |
67c0d1eb | 10380 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
c0ebe874 | 10381 | op[0], tempreg, breg); |
f5040a92 | 10382 | breg = 0; |
c0ebe874 | 10383 | tempreg = op[0]; |
f5040a92 | 10384 | } |
4d7206a2 | 10385 | relax_end (); |
f5040a92 | 10386 | } |
252b5132 RH |
10387 | else |
10388 | abort (); | |
10389 | ||
10390 | if (breg != 0) | |
c0ebe874 | 10391 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", op[0], tempreg, breg); |
252b5132 RH |
10392 | break; |
10393 | ||
52b6b6b9 | 10394 | case M_MSGSND: |
df58fc94 | 10395 | gas_assert (!mips_opts.micromips); |
c0ebe874 | 10396 | macro_build (NULL, "c2", "C", (op[0] << 16) | 0x01); |
c7af4273 | 10397 | break; |
52b6b6b9 JM |
10398 | |
10399 | case M_MSGLD: | |
df58fc94 | 10400 | gas_assert (!mips_opts.micromips); |
c8276761 | 10401 | macro_build (NULL, "c2", "C", 0x02); |
c7af4273 | 10402 | break; |
52b6b6b9 JM |
10403 | |
10404 | case M_MSGLD_T: | |
df58fc94 | 10405 | gas_assert (!mips_opts.micromips); |
c0ebe874 | 10406 | macro_build (NULL, "c2", "C", (op[0] << 16) | 0x02); |
c7af4273 | 10407 | break; |
52b6b6b9 JM |
10408 | |
10409 | case M_MSGWAIT: | |
df58fc94 | 10410 | gas_assert (!mips_opts.micromips); |
52b6b6b9 | 10411 | macro_build (NULL, "c2", "C", 3); |
c7af4273 | 10412 | break; |
52b6b6b9 JM |
10413 | |
10414 | case M_MSGWAIT_T: | |
df58fc94 | 10415 | gas_assert (!mips_opts.micromips); |
c0ebe874 | 10416 | macro_build (NULL, "c2", "C", (op[0] << 16) | 0x03); |
c7af4273 | 10417 | break; |
52b6b6b9 | 10418 | |
252b5132 RH |
10419 | case M_J_A: |
10420 | /* The j instruction may not be used in PIC code, since it | |
10421 | requires an absolute address. We convert it to a b | |
10422 | instruction. */ | |
10423 | if (mips_pic == NO_PIC) | |
67c0d1eb | 10424 | macro_build (&offset_expr, "j", "a"); |
252b5132 | 10425 | else |
67c0d1eb | 10426 | macro_build (&offset_expr, "b", "p"); |
8fc2e39e | 10427 | break; |
252b5132 RH |
10428 | |
10429 | /* The jal instructions must be handled as macros because when | |
10430 | generating PIC code they expand to multi-instruction | |
10431 | sequences. Normally they are simple instructions. */ | |
df58fc94 | 10432 | case M_JALS_1: |
c0ebe874 RS |
10433 | op[1] = op[0]; |
10434 | op[0] = RA; | |
df58fc94 RS |
10435 | /* Fall through. */ |
10436 | case M_JALS_2: | |
10437 | gas_assert (mips_opts.micromips); | |
833794fc MR |
10438 | if (mips_opts.insn32) |
10439 | { | |
1661c76c | 10440 | as_bad (_("opcode not supported in the `insn32' mode `%s'"), str); |
833794fc MR |
10441 | break; |
10442 | } | |
df58fc94 RS |
10443 | jals = 1; |
10444 | goto jal; | |
252b5132 | 10445 | case M_JAL_1: |
c0ebe874 RS |
10446 | op[1] = op[0]; |
10447 | op[0] = RA; | |
252b5132 RH |
10448 | /* Fall through. */ |
10449 | case M_JAL_2: | |
df58fc94 | 10450 | jal: |
3e722fb5 | 10451 | if (mips_pic == NO_PIC) |
df58fc94 RS |
10452 | { |
10453 | s = jals ? "jalrs" : "jalr"; | |
e64af278 | 10454 | if (mips_opts.micromips |
833794fc | 10455 | && !mips_opts.insn32 |
c0ebe874 | 10456 | && op[0] == RA |
e64af278 | 10457 | && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) |
c0ebe874 | 10458 | macro_build (NULL, s, "mj", op[1]); |
df58fc94 | 10459 | else |
c0ebe874 | 10460 | macro_build (NULL, s, JALR_FMT, op[0], op[1]); |
df58fc94 | 10461 | } |
0a44bf69 | 10462 | else |
252b5132 | 10463 | { |
df58fc94 RS |
10464 | int cprestore = (mips_pic == SVR4_PIC && !HAVE_NEWABI |
10465 | && mips_cprestore_offset >= 0); | |
10466 | ||
c0ebe874 | 10467 | if (op[1] != PIC_CALL_REG) |
252b5132 | 10468 | as_warn (_("MIPS PIC call to register other than $25")); |
bdaaa2e1 | 10469 | |
833794fc MR |
10470 | s = ((mips_opts.micromips |
10471 | && !mips_opts.insn32 | |
10472 | && (!mips_opts.noreorder || cprestore)) | |
df58fc94 | 10473 | ? "jalrs" : "jalr"); |
e64af278 | 10474 | if (mips_opts.micromips |
833794fc | 10475 | && !mips_opts.insn32 |
c0ebe874 | 10476 | && op[0] == RA |
e64af278 | 10477 | && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) |
c0ebe874 | 10478 | macro_build (NULL, s, "mj", op[1]); |
df58fc94 | 10479 | else |
c0ebe874 | 10480 | macro_build (NULL, s, JALR_FMT, op[0], op[1]); |
0a44bf69 | 10481 | if (mips_pic == SVR4_PIC && !HAVE_NEWABI) |
252b5132 | 10482 | { |
6478892d | 10483 | if (mips_cprestore_offset < 0) |
1661c76c | 10484 | as_warn (_("no .cprestore pseudo-op used in PIC code")); |
6478892d TS |
10485 | else |
10486 | { | |
90ecf173 | 10487 | if (!mips_frame_reg_valid) |
7a621144 | 10488 | { |
1661c76c | 10489 | as_warn (_("no .frame pseudo-op used in PIC code")); |
7a621144 DJ |
10490 | /* Quiet this warning. */ |
10491 | mips_frame_reg_valid = 1; | |
10492 | } | |
90ecf173 | 10493 | if (!mips_cprestore_valid) |
7a621144 | 10494 | { |
1661c76c | 10495 | as_warn (_("no .cprestore pseudo-op used in PIC code")); |
7a621144 DJ |
10496 | /* Quiet this warning. */ |
10497 | mips_cprestore_valid = 1; | |
10498 | } | |
d3fca0b5 MR |
10499 | if (mips_opts.noreorder) |
10500 | macro_build (NULL, "nop", ""); | |
6478892d | 10501 | expr1.X_add_number = mips_cprestore_offset; |
67c0d1eb | 10502 | macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN, |
f899b4b8 | 10503 | mips_gp_register, |
256ab948 TS |
10504 | mips_frame_reg, |
10505 | HAVE_64BIT_ADDRESSES); | |
6478892d | 10506 | } |
252b5132 RH |
10507 | } |
10508 | } | |
252b5132 | 10509 | |
8fc2e39e | 10510 | break; |
252b5132 | 10511 | |
df58fc94 RS |
10512 | case M_JALS_A: |
10513 | gas_assert (mips_opts.micromips); | |
833794fc MR |
10514 | if (mips_opts.insn32) |
10515 | { | |
1661c76c | 10516 | as_bad (_("opcode not supported in the `insn32' mode `%s'"), str); |
833794fc MR |
10517 | break; |
10518 | } | |
df58fc94 RS |
10519 | jals = 1; |
10520 | /* Fall through. */ | |
252b5132 RH |
10521 | case M_JAL_A: |
10522 | if (mips_pic == NO_PIC) | |
df58fc94 | 10523 | macro_build (&offset_expr, jals ? "jals" : "jal", "a"); |
252b5132 RH |
10524 | else if (mips_pic == SVR4_PIC) |
10525 | { | |
10526 | /* If this is a reference to an external symbol, and we are | |
10527 | using a small GOT, we want | |
10528 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16) | |
10529 | nop | |
f9419b05 | 10530 | jalr $ra,$25 |
252b5132 RH |
10531 | nop |
10532 | lw $gp,cprestore($sp) | |
10533 | The cprestore value is set using the .cprestore | |
10534 | pseudo-op. If we are using a big GOT, we want | |
10535 | lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16) | |
10536 | addu $25,$25,$gp | |
10537 | lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16) | |
10538 | nop | |
f9419b05 | 10539 | jalr $ra,$25 |
252b5132 RH |
10540 | nop |
10541 | lw $gp,cprestore($sp) | |
10542 | If the symbol is not external, we want | |
10543 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
10544 | nop | |
10545 | addiu $25,$25,<sym> (BFD_RELOC_LO16) | |
f9419b05 | 10546 | jalr $ra,$25 |
252b5132 | 10547 | nop |
438c16b8 | 10548 | lw $gp,cprestore($sp) |
f5040a92 AO |
10549 | |
10550 | For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16 | |
10551 | sequences above, minus nops, unless the symbol is local, | |
10552 | which enables us to use GOT_PAGE/GOT_OFST (big got) or | |
10553 | GOT_DISP. */ | |
438c16b8 | 10554 | if (HAVE_NEWABI) |
252b5132 | 10555 | { |
90ecf173 | 10556 | if (!mips_big_got) |
f5040a92 | 10557 | { |
4d7206a2 | 10558 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
10559 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
10560 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL16, | |
f5040a92 | 10561 | mips_gp_register); |
4d7206a2 | 10562 | relax_switch (); |
67c0d1eb RS |
10563 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
10564 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT_DISP, | |
4d7206a2 RS |
10565 | mips_gp_register); |
10566 | relax_end (); | |
f5040a92 AO |
10567 | } |
10568 | else | |
10569 | { | |
4d7206a2 | 10570 | relax_start (offset_expr.X_add_symbol); |
df58fc94 | 10571 | macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG, |
67c0d1eb RS |
10572 | BFD_RELOC_MIPS_CALL_HI16); |
10573 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG, | |
10574 | PIC_CALL_REG, mips_gp_register); | |
10575 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", | |
10576 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16, | |
10577 | PIC_CALL_REG); | |
4d7206a2 | 10578 | relax_switch (); |
67c0d1eb RS |
10579 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
10580 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT_PAGE, | |
10581 | mips_gp_register); | |
10582 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
10583 | PIC_CALL_REG, PIC_CALL_REG, | |
17a2f251 | 10584 | BFD_RELOC_MIPS_GOT_OFST); |
4d7206a2 | 10585 | relax_end (); |
f5040a92 | 10586 | } |
684022ea | 10587 | |
df58fc94 | 10588 | macro_build_jalr (&offset_expr, 0); |
252b5132 RH |
10589 | } |
10590 | else | |
10591 | { | |
4d7206a2 | 10592 | relax_start (offset_expr.X_add_symbol); |
90ecf173 | 10593 | if (!mips_big_got) |
438c16b8 | 10594 | { |
67c0d1eb RS |
10595 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
10596 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL16, | |
17a2f251 | 10597 | mips_gp_register); |
269137b2 | 10598 | load_delay_nop (); |
4d7206a2 | 10599 | relax_switch (); |
438c16b8 | 10600 | } |
252b5132 | 10601 | else |
252b5132 | 10602 | { |
67c0d1eb RS |
10603 | int gpdelay; |
10604 | ||
10605 | gpdelay = reg_needs_delay (mips_gp_register); | |
df58fc94 | 10606 | macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG, |
67c0d1eb RS |
10607 | BFD_RELOC_MIPS_CALL_HI16); |
10608 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG, | |
10609 | PIC_CALL_REG, mips_gp_register); | |
10610 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", | |
10611 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16, | |
10612 | PIC_CALL_REG); | |
269137b2 | 10613 | load_delay_nop (); |
4d7206a2 | 10614 | relax_switch (); |
67c0d1eb RS |
10615 | if (gpdelay) |
10616 | macro_build (NULL, "nop", ""); | |
252b5132 | 10617 | } |
67c0d1eb RS |
10618 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
10619 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT16, | |
4d7206a2 | 10620 | mips_gp_register); |
269137b2 | 10621 | load_delay_nop (); |
67c0d1eb RS |
10622 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
10623 | PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16); | |
4d7206a2 | 10624 | relax_end (); |
df58fc94 | 10625 | macro_build_jalr (&offset_expr, mips_cprestore_offset >= 0); |
438c16b8 | 10626 | |
6478892d | 10627 | if (mips_cprestore_offset < 0) |
1661c76c | 10628 | as_warn (_("no .cprestore pseudo-op used in PIC code")); |
6478892d TS |
10629 | else |
10630 | { | |
90ecf173 | 10631 | if (!mips_frame_reg_valid) |
7a621144 | 10632 | { |
1661c76c | 10633 | as_warn (_("no .frame pseudo-op used in PIC code")); |
7a621144 DJ |
10634 | /* Quiet this warning. */ |
10635 | mips_frame_reg_valid = 1; | |
10636 | } | |
90ecf173 | 10637 | if (!mips_cprestore_valid) |
7a621144 | 10638 | { |
1661c76c | 10639 | as_warn (_("no .cprestore pseudo-op used in PIC code")); |
7a621144 DJ |
10640 | /* Quiet this warning. */ |
10641 | mips_cprestore_valid = 1; | |
10642 | } | |
6478892d | 10643 | if (mips_opts.noreorder) |
67c0d1eb | 10644 | macro_build (NULL, "nop", ""); |
6478892d | 10645 | expr1.X_add_number = mips_cprestore_offset; |
67c0d1eb | 10646 | macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN, |
f899b4b8 | 10647 | mips_gp_register, |
256ab948 TS |
10648 | mips_frame_reg, |
10649 | HAVE_64BIT_ADDRESSES); | |
6478892d | 10650 | } |
252b5132 RH |
10651 | } |
10652 | } | |
0a44bf69 | 10653 | else if (mips_pic == VXWORKS_PIC) |
1661c76c | 10654 | as_bad (_("non-PIC jump used in PIC library")); |
252b5132 RH |
10655 | else |
10656 | abort (); | |
10657 | ||
8fc2e39e | 10658 | break; |
252b5132 | 10659 | |
7f3c4072 | 10660 | case M_LBUE_AB: |
7f3c4072 CM |
10661 | s = "lbue"; |
10662 | fmt = "t,+j(b)"; | |
10663 | offbits = 9; | |
10664 | goto ld_st; | |
10665 | case M_LHUE_AB: | |
7f3c4072 CM |
10666 | s = "lhue"; |
10667 | fmt = "t,+j(b)"; | |
10668 | offbits = 9; | |
10669 | goto ld_st; | |
10670 | case M_LBE_AB: | |
7f3c4072 CM |
10671 | s = "lbe"; |
10672 | fmt = "t,+j(b)"; | |
10673 | offbits = 9; | |
10674 | goto ld_st; | |
10675 | case M_LHE_AB: | |
7f3c4072 CM |
10676 | s = "lhe"; |
10677 | fmt = "t,+j(b)"; | |
10678 | offbits = 9; | |
10679 | goto ld_st; | |
10680 | case M_LLE_AB: | |
7f3c4072 CM |
10681 | s = "lle"; |
10682 | fmt = "t,+j(b)"; | |
10683 | offbits = 9; | |
10684 | goto ld_st; | |
10685 | case M_LWE_AB: | |
7f3c4072 CM |
10686 | s = "lwe"; |
10687 | fmt = "t,+j(b)"; | |
10688 | offbits = 9; | |
10689 | goto ld_st; | |
10690 | case M_LWLE_AB: | |
7f3c4072 CM |
10691 | s = "lwle"; |
10692 | fmt = "t,+j(b)"; | |
10693 | offbits = 9; | |
10694 | goto ld_st; | |
10695 | case M_LWRE_AB: | |
7f3c4072 CM |
10696 | s = "lwre"; |
10697 | fmt = "t,+j(b)"; | |
10698 | offbits = 9; | |
10699 | goto ld_st; | |
10700 | case M_SBE_AB: | |
7f3c4072 CM |
10701 | s = "sbe"; |
10702 | fmt = "t,+j(b)"; | |
10703 | offbits = 9; | |
10704 | goto ld_st; | |
10705 | case M_SCE_AB: | |
7f3c4072 CM |
10706 | s = "sce"; |
10707 | fmt = "t,+j(b)"; | |
10708 | offbits = 9; | |
10709 | goto ld_st; | |
10710 | case M_SHE_AB: | |
7f3c4072 CM |
10711 | s = "she"; |
10712 | fmt = "t,+j(b)"; | |
10713 | offbits = 9; | |
10714 | goto ld_st; | |
10715 | case M_SWE_AB: | |
7f3c4072 CM |
10716 | s = "swe"; |
10717 | fmt = "t,+j(b)"; | |
10718 | offbits = 9; | |
10719 | goto ld_st; | |
10720 | case M_SWLE_AB: | |
7f3c4072 CM |
10721 | s = "swle"; |
10722 | fmt = "t,+j(b)"; | |
10723 | offbits = 9; | |
10724 | goto ld_st; | |
10725 | case M_SWRE_AB: | |
7f3c4072 CM |
10726 | s = "swre"; |
10727 | fmt = "t,+j(b)"; | |
10728 | offbits = 9; | |
10729 | goto ld_st; | |
dec0624d | 10730 | case M_ACLR_AB: |
dec0624d | 10731 | s = "aclr"; |
dec0624d | 10732 | fmt = "\\,~(b)"; |
7f3c4072 | 10733 | offbits = 12; |
dec0624d MR |
10734 | goto ld_st; |
10735 | case M_ASET_AB: | |
dec0624d | 10736 | s = "aset"; |
dec0624d | 10737 | fmt = "\\,~(b)"; |
7f3c4072 | 10738 | offbits = 12; |
dec0624d | 10739 | goto ld_st; |
252b5132 RH |
10740 | case M_LB_AB: |
10741 | s = "lb"; | |
df58fc94 | 10742 | fmt = "t,o(b)"; |
252b5132 RH |
10743 | goto ld; |
10744 | case M_LBU_AB: | |
10745 | s = "lbu"; | |
df58fc94 | 10746 | fmt = "t,o(b)"; |
252b5132 RH |
10747 | goto ld; |
10748 | case M_LH_AB: | |
10749 | s = "lh"; | |
df58fc94 | 10750 | fmt = "t,o(b)"; |
252b5132 RH |
10751 | goto ld; |
10752 | case M_LHU_AB: | |
10753 | s = "lhu"; | |
df58fc94 | 10754 | fmt = "t,o(b)"; |
252b5132 RH |
10755 | goto ld; |
10756 | case M_LW_AB: | |
10757 | s = "lw"; | |
df58fc94 | 10758 | fmt = "t,o(b)"; |
252b5132 RH |
10759 | goto ld; |
10760 | case M_LWC0_AB: | |
df58fc94 | 10761 | gas_assert (!mips_opts.micromips); |
252b5132 | 10762 | s = "lwc0"; |
df58fc94 | 10763 | fmt = "E,o(b)"; |
bdaaa2e1 | 10764 | /* Itbl support may require additional care here. */ |
252b5132 | 10765 | coproc = 1; |
df58fc94 | 10766 | goto ld_st; |
252b5132 RH |
10767 | case M_LWC1_AB: |
10768 | s = "lwc1"; | |
df58fc94 | 10769 | fmt = "T,o(b)"; |
bdaaa2e1 | 10770 | /* Itbl support may require additional care here. */ |
252b5132 | 10771 | coproc = 1; |
df58fc94 | 10772 | goto ld_st; |
252b5132 RH |
10773 | case M_LWC2_AB: |
10774 | s = "lwc2"; | |
df58fc94 | 10775 | fmt = COP12_FMT; |
7f3c4072 | 10776 | offbits = (mips_opts.micromips ? 12 : 16); |
bdaaa2e1 | 10777 | /* Itbl support may require additional care here. */ |
252b5132 | 10778 | coproc = 1; |
df58fc94 | 10779 | goto ld_st; |
252b5132 | 10780 | case M_LWC3_AB: |
df58fc94 | 10781 | gas_assert (!mips_opts.micromips); |
252b5132 | 10782 | s = "lwc3"; |
df58fc94 | 10783 | fmt = "E,o(b)"; |
bdaaa2e1 | 10784 | /* Itbl support may require additional care here. */ |
252b5132 | 10785 | coproc = 1; |
df58fc94 | 10786 | goto ld_st; |
252b5132 RH |
10787 | case M_LWL_AB: |
10788 | s = "lwl"; | |
df58fc94 | 10789 | fmt = MEM12_FMT; |
7f3c4072 | 10790 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 | 10791 | goto ld_st; |
252b5132 RH |
10792 | case M_LWR_AB: |
10793 | s = "lwr"; | |
df58fc94 | 10794 | fmt = MEM12_FMT; |
7f3c4072 | 10795 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 | 10796 | goto ld_st; |
252b5132 | 10797 | case M_LDC1_AB: |
252b5132 | 10798 | s = "ldc1"; |
df58fc94 | 10799 | fmt = "T,o(b)"; |
bdaaa2e1 | 10800 | /* Itbl support may require additional care here. */ |
252b5132 | 10801 | coproc = 1; |
df58fc94 | 10802 | goto ld_st; |
252b5132 RH |
10803 | case M_LDC2_AB: |
10804 | s = "ldc2"; | |
df58fc94 | 10805 | fmt = COP12_FMT; |
7f3c4072 | 10806 | offbits = (mips_opts.micromips ? 12 : 16); |
bdaaa2e1 | 10807 | /* Itbl support may require additional care here. */ |
252b5132 | 10808 | coproc = 1; |
df58fc94 | 10809 | goto ld_st; |
c77c0862 | 10810 | case M_LQC2_AB: |
c77c0862 | 10811 | s = "lqc2"; |
14daeee3 | 10812 | fmt = "+7,o(b)"; |
c77c0862 RS |
10813 | /* Itbl support may require additional care here. */ |
10814 | coproc = 1; | |
10815 | goto ld_st; | |
252b5132 RH |
10816 | case M_LDC3_AB: |
10817 | s = "ldc3"; | |
df58fc94 | 10818 | fmt = "E,o(b)"; |
bdaaa2e1 | 10819 | /* Itbl support may require additional care here. */ |
252b5132 | 10820 | coproc = 1; |
df58fc94 | 10821 | goto ld_st; |
252b5132 RH |
10822 | case M_LDL_AB: |
10823 | s = "ldl"; | |
df58fc94 | 10824 | fmt = MEM12_FMT; |
7f3c4072 | 10825 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 | 10826 | goto ld_st; |
252b5132 RH |
10827 | case M_LDR_AB: |
10828 | s = "ldr"; | |
df58fc94 | 10829 | fmt = MEM12_FMT; |
7f3c4072 | 10830 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 | 10831 | goto ld_st; |
252b5132 RH |
10832 | case M_LL_AB: |
10833 | s = "ll"; | |
df58fc94 | 10834 | fmt = MEM12_FMT; |
7f3c4072 | 10835 | offbits = (mips_opts.micromips ? 12 : 16); |
252b5132 RH |
10836 | goto ld; |
10837 | case M_LLD_AB: | |
10838 | s = "lld"; | |
df58fc94 | 10839 | fmt = MEM12_FMT; |
7f3c4072 | 10840 | offbits = (mips_opts.micromips ? 12 : 16); |
252b5132 RH |
10841 | goto ld; |
10842 | case M_LWU_AB: | |
10843 | s = "lwu"; | |
df58fc94 | 10844 | fmt = MEM12_FMT; |
7f3c4072 | 10845 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 RS |
10846 | goto ld; |
10847 | case M_LWP_AB: | |
df58fc94 RS |
10848 | gas_assert (mips_opts.micromips); |
10849 | s = "lwp"; | |
10850 | fmt = "t,~(b)"; | |
7f3c4072 | 10851 | offbits = 12; |
df58fc94 RS |
10852 | lp = 1; |
10853 | goto ld; | |
10854 | case M_LDP_AB: | |
df58fc94 RS |
10855 | gas_assert (mips_opts.micromips); |
10856 | s = "ldp"; | |
10857 | fmt = "t,~(b)"; | |
7f3c4072 | 10858 | offbits = 12; |
df58fc94 RS |
10859 | lp = 1; |
10860 | goto ld; | |
10861 | case M_LWM_AB: | |
df58fc94 RS |
10862 | gas_assert (mips_opts.micromips); |
10863 | s = "lwm"; | |
10864 | fmt = "n,~(b)"; | |
7f3c4072 | 10865 | offbits = 12; |
df58fc94 RS |
10866 | goto ld_st; |
10867 | case M_LDM_AB: | |
df58fc94 RS |
10868 | gas_assert (mips_opts.micromips); |
10869 | s = "ldm"; | |
10870 | fmt = "n,~(b)"; | |
7f3c4072 | 10871 | offbits = 12; |
df58fc94 RS |
10872 | goto ld_st; |
10873 | ||
252b5132 | 10874 | ld: |
f19ccbda | 10875 | /* We don't want to use $0 as tempreg. */ |
c0ebe874 | 10876 | if (op[2] == op[0] + lp || op[0] + lp == ZERO) |
df58fc94 | 10877 | goto ld_st; |
252b5132 | 10878 | else |
c0ebe874 | 10879 | tempreg = op[0] + lp; |
df58fc94 RS |
10880 | goto ld_noat; |
10881 | ||
252b5132 RH |
10882 | case M_SB_AB: |
10883 | s = "sb"; | |
df58fc94 RS |
10884 | fmt = "t,o(b)"; |
10885 | goto ld_st; | |
252b5132 RH |
10886 | case M_SH_AB: |
10887 | s = "sh"; | |
df58fc94 RS |
10888 | fmt = "t,o(b)"; |
10889 | goto ld_st; | |
252b5132 RH |
10890 | case M_SW_AB: |
10891 | s = "sw"; | |
df58fc94 RS |
10892 | fmt = "t,o(b)"; |
10893 | goto ld_st; | |
252b5132 | 10894 | case M_SWC0_AB: |
df58fc94 | 10895 | gas_assert (!mips_opts.micromips); |
252b5132 | 10896 | s = "swc0"; |
df58fc94 | 10897 | fmt = "E,o(b)"; |
bdaaa2e1 | 10898 | /* Itbl support may require additional care here. */ |
252b5132 | 10899 | coproc = 1; |
df58fc94 | 10900 | goto ld_st; |
252b5132 RH |
10901 | case M_SWC1_AB: |
10902 | s = "swc1"; | |
df58fc94 | 10903 | fmt = "T,o(b)"; |
bdaaa2e1 | 10904 | /* Itbl support may require additional care here. */ |
252b5132 | 10905 | coproc = 1; |
df58fc94 | 10906 | goto ld_st; |
252b5132 RH |
10907 | case M_SWC2_AB: |
10908 | s = "swc2"; | |
df58fc94 | 10909 | fmt = COP12_FMT; |
7f3c4072 | 10910 | offbits = (mips_opts.micromips ? 12 : 16); |
bdaaa2e1 | 10911 | /* Itbl support may require additional care here. */ |
252b5132 | 10912 | coproc = 1; |
df58fc94 | 10913 | goto ld_st; |
252b5132 | 10914 | case M_SWC3_AB: |
df58fc94 | 10915 | gas_assert (!mips_opts.micromips); |
252b5132 | 10916 | s = "swc3"; |
df58fc94 | 10917 | fmt = "E,o(b)"; |
bdaaa2e1 | 10918 | /* Itbl support may require additional care here. */ |
252b5132 | 10919 | coproc = 1; |
df58fc94 | 10920 | goto ld_st; |
252b5132 RH |
10921 | case M_SWL_AB: |
10922 | s = "swl"; | |
df58fc94 | 10923 | fmt = MEM12_FMT; |
7f3c4072 | 10924 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 | 10925 | goto ld_st; |
252b5132 RH |
10926 | case M_SWR_AB: |
10927 | s = "swr"; | |
df58fc94 | 10928 | fmt = MEM12_FMT; |
7f3c4072 | 10929 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 | 10930 | goto ld_st; |
252b5132 RH |
10931 | case M_SC_AB: |
10932 | s = "sc"; | |
df58fc94 | 10933 | fmt = MEM12_FMT; |
7f3c4072 | 10934 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 | 10935 | goto ld_st; |
252b5132 RH |
10936 | case M_SCD_AB: |
10937 | s = "scd"; | |
df58fc94 | 10938 | fmt = MEM12_FMT; |
7f3c4072 | 10939 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 | 10940 | goto ld_st; |
d43b4baf TS |
10941 | case M_CACHE_AB: |
10942 | s = "cache"; | |
df58fc94 | 10943 | fmt = mips_opts.micromips ? "k,~(b)" : "k,o(b)"; |
7f3c4072 CM |
10944 | offbits = (mips_opts.micromips ? 12 : 16); |
10945 | goto ld_st; | |
10946 | case M_CACHEE_AB: | |
7f3c4072 CM |
10947 | s = "cachee"; |
10948 | fmt = "k,+j(b)"; | |
10949 | offbits = 9; | |
df58fc94 | 10950 | goto ld_st; |
3eebd5eb MR |
10951 | case M_PREF_AB: |
10952 | s = "pref"; | |
df58fc94 | 10953 | fmt = !mips_opts.micromips ? "k,o(b)" : "k,~(b)"; |
7f3c4072 CM |
10954 | offbits = (mips_opts.micromips ? 12 : 16); |
10955 | goto ld_st; | |
10956 | case M_PREFE_AB: | |
7f3c4072 CM |
10957 | s = "prefe"; |
10958 | fmt = "k,+j(b)"; | |
10959 | offbits = 9; | |
df58fc94 | 10960 | goto ld_st; |
252b5132 | 10961 | case M_SDC1_AB: |
252b5132 | 10962 | s = "sdc1"; |
df58fc94 | 10963 | fmt = "T,o(b)"; |
252b5132 | 10964 | coproc = 1; |
bdaaa2e1 | 10965 | /* Itbl support may require additional care here. */ |
df58fc94 | 10966 | goto ld_st; |
252b5132 RH |
10967 | case M_SDC2_AB: |
10968 | s = "sdc2"; | |
df58fc94 | 10969 | fmt = COP12_FMT; |
7f3c4072 | 10970 | offbits = (mips_opts.micromips ? 12 : 16); |
c77c0862 RS |
10971 | /* Itbl support may require additional care here. */ |
10972 | coproc = 1; | |
10973 | goto ld_st; | |
10974 | case M_SQC2_AB: | |
c77c0862 | 10975 | s = "sqc2"; |
14daeee3 | 10976 | fmt = "+7,o(b)"; |
bdaaa2e1 | 10977 | /* Itbl support may require additional care here. */ |
252b5132 | 10978 | coproc = 1; |
df58fc94 | 10979 | goto ld_st; |
252b5132 | 10980 | case M_SDC3_AB: |
df58fc94 | 10981 | gas_assert (!mips_opts.micromips); |
252b5132 | 10982 | s = "sdc3"; |
df58fc94 | 10983 | fmt = "E,o(b)"; |
bdaaa2e1 | 10984 | /* Itbl support may require additional care here. */ |
252b5132 | 10985 | coproc = 1; |
df58fc94 | 10986 | goto ld_st; |
252b5132 RH |
10987 | case M_SDL_AB: |
10988 | s = "sdl"; | |
df58fc94 | 10989 | fmt = MEM12_FMT; |
7f3c4072 | 10990 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 | 10991 | goto ld_st; |
252b5132 RH |
10992 | case M_SDR_AB: |
10993 | s = "sdr"; | |
df58fc94 | 10994 | fmt = MEM12_FMT; |
7f3c4072 | 10995 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 RS |
10996 | goto ld_st; |
10997 | case M_SWP_AB: | |
df58fc94 RS |
10998 | gas_assert (mips_opts.micromips); |
10999 | s = "swp"; | |
11000 | fmt = "t,~(b)"; | |
7f3c4072 | 11001 | offbits = 12; |
df58fc94 RS |
11002 | goto ld_st; |
11003 | case M_SDP_AB: | |
df58fc94 RS |
11004 | gas_assert (mips_opts.micromips); |
11005 | s = "sdp"; | |
11006 | fmt = "t,~(b)"; | |
7f3c4072 | 11007 | offbits = 12; |
df58fc94 RS |
11008 | goto ld_st; |
11009 | case M_SWM_AB: | |
df58fc94 RS |
11010 | gas_assert (mips_opts.micromips); |
11011 | s = "swm"; | |
11012 | fmt = "n,~(b)"; | |
7f3c4072 | 11013 | offbits = 12; |
df58fc94 RS |
11014 | goto ld_st; |
11015 | case M_SDM_AB: | |
df58fc94 RS |
11016 | gas_assert (mips_opts.micromips); |
11017 | s = "sdm"; | |
11018 | fmt = "n,~(b)"; | |
7f3c4072 | 11019 | offbits = 12; |
df58fc94 RS |
11020 | |
11021 | ld_st: | |
8fc2e39e | 11022 | tempreg = AT; |
df58fc94 | 11023 | ld_noat: |
c0ebe874 | 11024 | breg = op[2]; |
f2ae14a1 RS |
11025 | if (small_offset_p (0, align, 16)) |
11026 | { | |
11027 | /* The first case exists for M_LD_AB and M_SD_AB, which are | |
11028 | macros for o32 but which should act like normal instructions | |
11029 | otherwise. */ | |
11030 | if (offbits == 16) | |
c0ebe874 | 11031 | macro_build (&offset_expr, s, fmt, op[0], -1, offset_reloc[0], |
f2ae14a1 RS |
11032 | offset_reloc[1], offset_reloc[2], breg); |
11033 | else if (small_offset_p (0, align, offbits)) | |
11034 | { | |
11035 | if (offbits == 0) | |
c0ebe874 | 11036 | macro_build (NULL, s, fmt, op[0], breg); |
f2ae14a1 | 11037 | else |
c0ebe874 | 11038 | macro_build (NULL, s, fmt, op[0], |
c8276761 | 11039 | (int) offset_expr.X_add_number, breg); |
f2ae14a1 RS |
11040 | } |
11041 | else | |
11042 | { | |
11043 | if (tempreg == AT) | |
11044 | used_at = 1; | |
11045 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
11046 | tempreg, breg, -1, offset_reloc[0], | |
11047 | offset_reloc[1], offset_reloc[2]); | |
11048 | if (offbits == 0) | |
c0ebe874 | 11049 | macro_build (NULL, s, fmt, op[0], tempreg); |
f2ae14a1 | 11050 | else |
c0ebe874 | 11051 | macro_build (NULL, s, fmt, op[0], 0, tempreg); |
f2ae14a1 RS |
11052 | } |
11053 | break; | |
11054 | } | |
11055 | ||
11056 | if (tempreg == AT) | |
11057 | used_at = 1; | |
11058 | ||
252b5132 RH |
11059 | if (offset_expr.X_op != O_constant |
11060 | && offset_expr.X_op != O_symbol) | |
11061 | { | |
1661c76c | 11062 | as_bad (_("expression too complex")); |
252b5132 RH |
11063 | offset_expr.X_op = O_constant; |
11064 | } | |
11065 | ||
2051e8c4 MR |
11066 | if (HAVE_32BIT_ADDRESSES |
11067 | && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) | |
55e08f71 NC |
11068 | { |
11069 | char value [32]; | |
11070 | ||
11071 | sprintf_vma (value, offset_expr.X_add_number); | |
1661c76c | 11072 | as_bad (_("number (0x%s) larger than 32 bits"), value); |
55e08f71 | 11073 | } |
2051e8c4 | 11074 | |
252b5132 RH |
11075 | /* A constant expression in PIC code can be handled just as it |
11076 | is in non PIC code. */ | |
aed1a261 RS |
11077 | if (offset_expr.X_op == O_constant) |
11078 | { | |
f2ae14a1 RS |
11079 | expr1.X_add_number = offset_high_part (offset_expr.X_add_number, |
11080 | offbits == 0 ? 16 : offbits); | |
11081 | offset_expr.X_add_number -= expr1.X_add_number; | |
df58fc94 | 11082 | |
f2ae14a1 RS |
11083 | load_register (tempreg, &expr1, HAVE_64BIT_ADDRESSES); |
11084 | if (breg != 0) | |
11085 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
11086 | tempreg, tempreg, breg); | |
7f3c4072 | 11087 | if (offbits == 0) |
dd6a37e7 | 11088 | { |
f2ae14a1 | 11089 | if (offset_expr.X_add_number != 0) |
dd6a37e7 | 11090 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, |
f2ae14a1 | 11091 | "t,r,j", tempreg, tempreg, BFD_RELOC_LO16); |
c0ebe874 | 11092 | macro_build (NULL, s, fmt, op[0], tempreg); |
dd6a37e7 | 11093 | } |
7f3c4072 | 11094 | else if (offbits == 16) |
c0ebe874 | 11095 | macro_build (&offset_expr, s, fmt, op[0], BFD_RELOC_LO16, tempreg); |
df58fc94 | 11096 | else |
c0ebe874 | 11097 | macro_build (NULL, s, fmt, op[0], |
c8276761 | 11098 | (int) offset_expr.X_add_number, tempreg); |
df58fc94 | 11099 | } |
7f3c4072 | 11100 | else if (offbits != 16) |
df58fc94 | 11101 | { |
7f3c4072 CM |
11102 | /* The offset field is too narrow to be used for a low-part |
11103 | relocation, so load the whole address into the auxillary | |
f2ae14a1 RS |
11104 | register. */ |
11105 | load_address (tempreg, &offset_expr, &used_at); | |
11106 | if (breg != 0) | |
11107 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
11108 | tempreg, tempreg, breg); | |
7f3c4072 | 11109 | if (offbits == 0) |
c0ebe874 | 11110 | macro_build (NULL, s, fmt, op[0], tempreg); |
dd6a37e7 | 11111 | else |
c0ebe874 | 11112 | macro_build (NULL, s, fmt, op[0], 0, tempreg); |
aed1a261 RS |
11113 | } |
11114 | else if (mips_pic == NO_PIC) | |
252b5132 RH |
11115 | { |
11116 | /* If this is a reference to a GP relative symbol, and there | |
11117 | is no base register, we want | |
c0ebe874 | 11118 | <op> op[0],<sym>($gp) (BFD_RELOC_GPREL16) |
252b5132 RH |
11119 | Otherwise, if there is no base register, we want |
11120 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
c0ebe874 | 11121 | <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16) |
252b5132 RH |
11122 | If we have a constant, we need two instructions anyhow, |
11123 | so we always use the latter form. | |
11124 | ||
11125 | If we have a base register, and this is a reference to a | |
11126 | GP relative symbol, we want | |
11127 | addu $tempreg,$breg,$gp | |
c0ebe874 | 11128 | <op> op[0],<sym>($tempreg) (BFD_RELOC_GPREL16) |
252b5132 RH |
11129 | Otherwise we want |
11130 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
11131 | addu $tempreg,$tempreg,$breg | |
c0ebe874 | 11132 | <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16) |
d6bc6245 | 11133 | With a constant we always use the latter case. |
76b3015f | 11134 | |
d6bc6245 TS |
11135 | With 64bit address space and no base register and $at usable, |
11136 | we want | |
11137 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
11138 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
11139 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
11140 | dsll32 $tempreg,0 | |
11141 | daddu $tempreg,$at | |
c0ebe874 | 11142 | <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16) |
d6bc6245 TS |
11143 | If we have a base register, we want |
11144 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
11145 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
11146 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
11147 | daddu $at,$breg | |
11148 | dsll32 $tempreg,0 | |
11149 | daddu $tempreg,$at | |
c0ebe874 | 11150 | <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16) |
d6bc6245 TS |
11151 | |
11152 | Without $at we can't generate the optimal path for superscalar | |
11153 | processors here since this would require two temporary registers. | |
11154 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
11155 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
11156 | dsll $tempreg,16 | |
11157 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
11158 | dsll $tempreg,16 | |
c0ebe874 | 11159 | <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16) |
d6bc6245 TS |
11160 | If we have a base register, we want |
11161 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
11162 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
11163 | dsll $tempreg,16 | |
11164 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
11165 | dsll $tempreg,16 | |
11166 | daddu $tempreg,$tempreg,$breg | |
c0ebe874 | 11167 | <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16) |
6373ee54 | 11168 | |
6caf9ef4 | 11169 | For GP relative symbols in 64bit address space we can use |
aed1a261 RS |
11170 | the same sequence as in 32bit address space. */ |
11171 | if (HAVE_64BIT_SYMBOLS) | |
d6bc6245 | 11172 | { |
aed1a261 | 11173 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 TS |
11174 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
11175 | { | |
11176 | relax_start (offset_expr.X_add_symbol); | |
11177 | if (breg == 0) | |
11178 | { | |
c0ebe874 | 11179 | macro_build (&offset_expr, s, fmt, op[0], |
6caf9ef4 TS |
11180 | BFD_RELOC_GPREL16, mips_gp_register); |
11181 | } | |
11182 | else | |
11183 | { | |
11184 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
11185 | tempreg, breg, mips_gp_register); | |
c0ebe874 | 11186 | macro_build (&offset_expr, s, fmt, op[0], |
6caf9ef4 TS |
11187 | BFD_RELOC_GPREL16, tempreg); |
11188 | } | |
11189 | relax_switch (); | |
11190 | } | |
d6bc6245 | 11191 | |
741fe287 | 11192 | if (used_at == 0 && mips_opts.at) |
d6bc6245 | 11193 | { |
df58fc94 | 11194 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, |
67c0d1eb | 11195 | BFD_RELOC_MIPS_HIGHEST); |
df58fc94 | 11196 | macro_build (&offset_expr, "lui", LUI_FMT, AT, |
67c0d1eb RS |
11197 | BFD_RELOC_HI16_S); |
11198 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
11199 | tempreg, BFD_RELOC_MIPS_HIGHER); | |
d6bc6245 | 11200 | if (breg != 0) |
67c0d1eb | 11201 | macro_build (NULL, "daddu", "d,v,t", AT, AT, breg); |
df58fc94 | 11202 | macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0); |
67c0d1eb | 11203 | macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT); |
c0ebe874 | 11204 | macro_build (&offset_expr, s, fmt, op[0], BFD_RELOC_LO16, |
67c0d1eb | 11205 | tempreg); |
d6bc6245 TS |
11206 | used_at = 1; |
11207 | } | |
11208 | else | |
11209 | { | |
df58fc94 | 11210 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, |
67c0d1eb RS |
11211 | BFD_RELOC_MIPS_HIGHEST); |
11212 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
11213 | tempreg, BFD_RELOC_MIPS_HIGHER); | |
df58fc94 | 11214 | macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16); |
67c0d1eb RS |
11215 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, |
11216 | tempreg, BFD_RELOC_HI16_S); | |
df58fc94 | 11217 | macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16); |
d6bc6245 | 11218 | if (breg != 0) |
67c0d1eb | 11219 | macro_build (NULL, "daddu", "d,v,t", |
17a2f251 | 11220 | tempreg, tempreg, breg); |
c0ebe874 | 11221 | macro_build (&offset_expr, s, fmt, op[0], |
17a2f251 | 11222 | BFD_RELOC_LO16, tempreg); |
d6bc6245 | 11223 | } |
6caf9ef4 TS |
11224 | |
11225 | if (mips_relax.sequence) | |
11226 | relax_end (); | |
8fc2e39e | 11227 | break; |
d6bc6245 | 11228 | } |
256ab948 | 11229 | |
252b5132 RH |
11230 | if (breg == 0) |
11231 | { | |
67c0d1eb | 11232 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 11233 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 11234 | { |
4d7206a2 | 11235 | relax_start (offset_expr.X_add_symbol); |
c0ebe874 | 11236 | macro_build (&offset_expr, s, fmt, op[0], BFD_RELOC_GPREL16, |
67c0d1eb | 11237 | mips_gp_register); |
4d7206a2 | 11238 | relax_switch (); |
252b5132 | 11239 | } |
67c0d1eb | 11240 | macro_build_lui (&offset_expr, tempreg); |
c0ebe874 | 11241 | macro_build (&offset_expr, s, fmt, op[0], |
17a2f251 | 11242 | BFD_RELOC_LO16, tempreg); |
4d7206a2 RS |
11243 | if (mips_relax.sequence) |
11244 | relax_end (); | |
252b5132 RH |
11245 | } |
11246 | else | |
11247 | { | |
67c0d1eb | 11248 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 11249 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 11250 | { |
4d7206a2 | 11251 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 11252 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 11253 | tempreg, breg, mips_gp_register); |
c0ebe874 | 11254 | macro_build (&offset_expr, s, fmt, op[0], |
17a2f251 | 11255 | BFD_RELOC_GPREL16, tempreg); |
4d7206a2 | 11256 | relax_switch (); |
252b5132 | 11257 | } |
67c0d1eb RS |
11258 | macro_build_lui (&offset_expr, tempreg); |
11259 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 11260 | tempreg, tempreg, breg); |
c0ebe874 | 11261 | macro_build (&offset_expr, s, fmt, op[0], |
17a2f251 | 11262 | BFD_RELOC_LO16, tempreg); |
4d7206a2 RS |
11263 | if (mips_relax.sequence) |
11264 | relax_end (); | |
252b5132 RH |
11265 | } |
11266 | } | |
0a44bf69 | 11267 | else if (!mips_big_got) |
252b5132 | 11268 | { |
ed6fb7bd | 11269 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
f9419b05 | 11270 | |
252b5132 RH |
11271 | /* If this is a reference to an external symbol, we want |
11272 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
11273 | nop | |
c0ebe874 | 11274 | <op> op[0],0($tempreg) |
252b5132 RH |
11275 | Otherwise we want |
11276 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
11277 | nop | |
11278 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
c0ebe874 | 11279 | <op> op[0],0($tempreg) |
f5040a92 AO |
11280 | |
11281 | For NewABI, we want | |
11282 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
c0ebe874 | 11283 | <op> op[0],<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) |
f5040a92 | 11284 | |
252b5132 RH |
11285 | If there is a base register, we add it to $tempreg before |
11286 | the <op>. If there is a constant, we stick it in the | |
11287 | <op> instruction. We don't handle constants larger than | |
11288 | 16 bits, because we have no way to load the upper 16 bits | |
11289 | (actually, we could handle them for the subset of cases | |
11290 | in which we are not using $at). */ | |
9c2799c2 | 11291 | gas_assert (offset_expr.X_op == O_symbol); |
f5040a92 AO |
11292 | if (HAVE_NEWABI) |
11293 | { | |
67c0d1eb RS |
11294 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
11295 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
f5040a92 | 11296 | if (breg != 0) |
67c0d1eb | 11297 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 11298 | tempreg, tempreg, breg); |
c0ebe874 | 11299 | macro_build (&offset_expr, s, fmt, op[0], |
17a2f251 | 11300 | BFD_RELOC_MIPS_GOT_OFST, tempreg); |
f5040a92 AO |
11301 | break; |
11302 | } | |
252b5132 RH |
11303 | expr1.X_add_number = offset_expr.X_add_number; |
11304 | offset_expr.X_add_number = 0; | |
11305 | if (expr1.X_add_number < -0x8000 | |
11306 | || expr1.X_add_number >= 0x8000) | |
11307 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb RS |
11308 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
11309 | lw_reloc_type, mips_gp_register); | |
269137b2 | 11310 | load_delay_nop (); |
4d7206a2 RS |
11311 | relax_start (offset_expr.X_add_symbol); |
11312 | relax_switch (); | |
67c0d1eb RS |
11313 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, |
11314 | tempreg, BFD_RELOC_LO16); | |
4d7206a2 | 11315 | relax_end (); |
252b5132 | 11316 | if (breg != 0) |
67c0d1eb | 11317 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 11318 | tempreg, tempreg, breg); |
c0ebe874 | 11319 | macro_build (&expr1, s, fmt, op[0], BFD_RELOC_LO16, tempreg); |
252b5132 | 11320 | } |
0a44bf69 | 11321 | else if (mips_big_got && !HAVE_NEWABI) |
252b5132 | 11322 | { |
67c0d1eb | 11323 | int gpdelay; |
252b5132 RH |
11324 | |
11325 | /* If this is a reference to an external symbol, we want | |
11326 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
11327 | addu $tempreg,$tempreg,$gp | |
11328 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
c0ebe874 | 11329 | <op> op[0],0($tempreg) |
252b5132 RH |
11330 | Otherwise we want |
11331 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
11332 | nop | |
11333 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
c0ebe874 | 11334 | <op> op[0],0($tempreg) |
252b5132 RH |
11335 | If there is a base register, we add it to $tempreg before |
11336 | the <op>. If there is a constant, we stick it in the | |
11337 | <op> instruction. We don't handle constants larger than | |
11338 | 16 bits, because we have no way to load the upper 16 bits | |
11339 | (actually, we could handle them for the subset of cases | |
f5040a92 | 11340 | in which we are not using $at). */ |
9c2799c2 | 11341 | gas_assert (offset_expr.X_op == O_symbol); |
252b5132 RH |
11342 | expr1.X_add_number = offset_expr.X_add_number; |
11343 | offset_expr.X_add_number = 0; | |
11344 | if (expr1.X_add_number < -0x8000 | |
11345 | || expr1.X_add_number >= 0x8000) | |
11346 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 11347 | gpdelay = reg_needs_delay (mips_gp_register); |
4d7206a2 | 11348 | relax_start (offset_expr.X_add_symbol); |
df58fc94 | 11349 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, |
17a2f251 | 11350 | BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
11351 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, |
11352 | mips_gp_register); | |
11353 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
11354 | BFD_RELOC_MIPS_GOT_LO16, tempreg); | |
4d7206a2 | 11355 | relax_switch (); |
67c0d1eb RS |
11356 | if (gpdelay) |
11357 | macro_build (NULL, "nop", ""); | |
11358 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
11359 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 11360 | load_delay_nop (); |
67c0d1eb RS |
11361 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, |
11362 | tempreg, BFD_RELOC_LO16); | |
4d7206a2 RS |
11363 | relax_end (); |
11364 | ||
252b5132 | 11365 | if (breg != 0) |
67c0d1eb | 11366 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 11367 | tempreg, tempreg, breg); |
c0ebe874 | 11368 | macro_build (&expr1, s, fmt, op[0], BFD_RELOC_LO16, tempreg); |
252b5132 | 11369 | } |
0a44bf69 | 11370 | else if (mips_big_got && HAVE_NEWABI) |
f5040a92 | 11371 | { |
f5040a92 AO |
11372 | /* If this is a reference to an external symbol, we want |
11373 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
11374 | add $tempreg,$tempreg,$gp | |
11375 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
c0ebe874 | 11376 | <op> op[0],<ofst>($tempreg) |
f5040a92 AO |
11377 | Otherwise, for local symbols, we want: |
11378 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
c0ebe874 | 11379 | <op> op[0],<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */ |
9c2799c2 | 11380 | gas_assert (offset_expr.X_op == O_symbol); |
4d7206a2 | 11381 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
11382 | offset_expr.X_add_number = 0; |
11383 | if (expr1.X_add_number < -0x8000 | |
11384 | || expr1.X_add_number >= 0x8000) | |
11385 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4d7206a2 | 11386 | relax_start (offset_expr.X_add_symbol); |
df58fc94 | 11387 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, |
17a2f251 | 11388 | BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
11389 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, |
11390 | mips_gp_register); | |
11391 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
11392 | BFD_RELOC_MIPS_GOT_LO16, tempreg); | |
f5040a92 | 11393 | if (breg != 0) |
67c0d1eb | 11394 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 11395 | tempreg, tempreg, breg); |
c0ebe874 | 11396 | macro_build (&expr1, s, fmt, op[0], BFD_RELOC_LO16, tempreg); |
684022ea | 11397 | |
4d7206a2 | 11398 | relax_switch (); |
f5040a92 | 11399 | offset_expr.X_add_number = expr1.X_add_number; |
67c0d1eb RS |
11400 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
11401 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
f5040a92 | 11402 | if (breg != 0) |
67c0d1eb | 11403 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 11404 | tempreg, tempreg, breg); |
c0ebe874 | 11405 | macro_build (&offset_expr, s, fmt, op[0], |
17a2f251 | 11406 | BFD_RELOC_MIPS_GOT_OFST, tempreg); |
4d7206a2 | 11407 | relax_end (); |
f5040a92 | 11408 | } |
252b5132 RH |
11409 | else |
11410 | abort (); | |
11411 | ||
252b5132 RH |
11412 | break; |
11413 | ||
833794fc MR |
11414 | case M_JRADDIUSP: |
11415 | gas_assert (mips_opts.micromips); | |
11416 | gas_assert (mips_opts.insn32); | |
11417 | start_noreorder (); | |
11418 | macro_build (NULL, "jr", "s", RA); | |
c0ebe874 | 11419 | expr1.X_add_number = op[0] << 2; |
833794fc MR |
11420 | macro_build (&expr1, "addiu", "t,r,j", SP, SP, BFD_RELOC_LO16); |
11421 | end_noreorder (); | |
11422 | break; | |
11423 | ||
11424 | case M_JRC: | |
11425 | gas_assert (mips_opts.micromips); | |
11426 | gas_assert (mips_opts.insn32); | |
c0ebe874 | 11427 | macro_build (NULL, "jr", "s", op[0]); |
833794fc MR |
11428 | if (mips_opts.noreorder) |
11429 | macro_build (NULL, "nop", ""); | |
11430 | break; | |
11431 | ||
252b5132 RH |
11432 | case M_LI: |
11433 | case M_LI_S: | |
c0ebe874 | 11434 | load_register (op[0], &imm_expr, 0); |
8fc2e39e | 11435 | break; |
252b5132 RH |
11436 | |
11437 | case M_DLI: | |
c0ebe874 | 11438 | load_register (op[0], &imm_expr, 1); |
8fc2e39e | 11439 | break; |
252b5132 RH |
11440 | |
11441 | case M_LI_SS: | |
11442 | if (imm_expr.X_op == O_constant) | |
11443 | { | |
8fc2e39e | 11444 | used_at = 1; |
67c0d1eb | 11445 | load_register (AT, &imm_expr, 0); |
c0ebe874 | 11446 | macro_build (NULL, "mtc1", "t,G", AT, op[0]); |
252b5132 RH |
11447 | break; |
11448 | } | |
11449 | else | |
11450 | { | |
b0e6f033 RS |
11451 | gas_assert (imm_expr.X_op == O_absent |
11452 | && offset_expr.X_op == O_symbol | |
90ecf173 MR |
11453 | && strcmp (segment_name (S_GET_SEGMENT |
11454 | (offset_expr.X_add_symbol)), | |
11455 | ".lit4") == 0 | |
11456 | && offset_expr.X_add_number == 0); | |
c0ebe874 | 11457 | macro_build (&offset_expr, "lwc1", "T,o(b)", op[0], |
17a2f251 | 11458 | BFD_RELOC_MIPS_LITERAL, mips_gp_register); |
8fc2e39e | 11459 | break; |
252b5132 RH |
11460 | } |
11461 | ||
11462 | case M_LI_D: | |
ca4e0257 RS |
11463 | /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits |
11464 | wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high | |
11465 | order 32 bits of the value and the low order 32 bits are either | |
11466 | zero or in OFFSET_EXPR. */ | |
b0e6f033 | 11467 | if (imm_expr.X_op == O_constant) |
252b5132 | 11468 | { |
bad1aba3 | 11469 | if (GPR_SIZE == 64) |
c0ebe874 | 11470 | load_register (op[0], &imm_expr, 1); |
252b5132 RH |
11471 | else |
11472 | { | |
11473 | int hreg, lreg; | |
11474 | ||
11475 | if (target_big_endian) | |
11476 | { | |
c0ebe874 RS |
11477 | hreg = op[0]; |
11478 | lreg = op[0] + 1; | |
252b5132 RH |
11479 | } |
11480 | else | |
11481 | { | |
c0ebe874 RS |
11482 | hreg = op[0] + 1; |
11483 | lreg = op[0]; | |
252b5132 RH |
11484 | } |
11485 | ||
11486 | if (hreg <= 31) | |
67c0d1eb | 11487 | load_register (hreg, &imm_expr, 0); |
252b5132 RH |
11488 | if (lreg <= 31) |
11489 | { | |
11490 | if (offset_expr.X_op == O_absent) | |
67c0d1eb | 11491 | move_register (lreg, 0); |
252b5132 RH |
11492 | else |
11493 | { | |
9c2799c2 | 11494 | gas_assert (offset_expr.X_op == O_constant); |
67c0d1eb | 11495 | load_register (lreg, &offset_expr, 0); |
252b5132 RH |
11496 | } |
11497 | } | |
11498 | } | |
8fc2e39e | 11499 | break; |
252b5132 | 11500 | } |
b0e6f033 | 11501 | gas_assert (imm_expr.X_op == O_absent); |
252b5132 RH |
11502 | |
11503 | /* We know that sym is in the .rdata section. First we get the | |
11504 | upper 16 bits of the address. */ | |
11505 | if (mips_pic == NO_PIC) | |
11506 | { | |
67c0d1eb | 11507 | macro_build_lui (&offset_expr, AT); |
8fc2e39e | 11508 | used_at = 1; |
252b5132 | 11509 | } |
0a44bf69 | 11510 | else |
252b5132 | 11511 | { |
67c0d1eb RS |
11512 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, |
11513 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
8fc2e39e | 11514 | used_at = 1; |
252b5132 | 11515 | } |
bdaaa2e1 | 11516 | |
252b5132 | 11517 | /* Now we load the register(s). */ |
bad1aba3 | 11518 | if (GPR_SIZE == 64) |
8fc2e39e TS |
11519 | { |
11520 | used_at = 1; | |
c0ebe874 RS |
11521 | macro_build (&offset_expr, "ld", "t,o(b)", op[0], |
11522 | BFD_RELOC_LO16, AT); | |
8fc2e39e | 11523 | } |
252b5132 RH |
11524 | else |
11525 | { | |
8fc2e39e | 11526 | used_at = 1; |
c0ebe874 RS |
11527 | macro_build (&offset_expr, "lw", "t,o(b)", op[0], |
11528 | BFD_RELOC_LO16, AT); | |
11529 | if (op[0] != RA) | |
252b5132 RH |
11530 | { |
11531 | /* FIXME: How in the world do we deal with the possible | |
11532 | overflow here? */ | |
11533 | offset_expr.X_add_number += 4; | |
67c0d1eb | 11534 | macro_build (&offset_expr, "lw", "t,o(b)", |
c0ebe874 | 11535 | op[0] + 1, BFD_RELOC_LO16, AT); |
252b5132 RH |
11536 | } |
11537 | } | |
252b5132 RH |
11538 | break; |
11539 | ||
11540 | case M_LI_DD: | |
ca4e0257 RS |
11541 | /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits |
11542 | wide, IMM_EXPR is the entire value and the GPRs are known to be 64 | |
11543 | bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of | |
11544 | the value and the low order 32 bits are either zero or in | |
11545 | OFFSET_EXPR. */ | |
b0e6f033 | 11546 | if (imm_expr.X_op == O_constant) |
252b5132 | 11547 | { |
8fc2e39e | 11548 | used_at = 1; |
bad1aba3 | 11549 | load_register (AT, &imm_expr, FPR_SIZE == 64); |
11550 | if (FPR_SIZE == 64) | |
ca4e0257 | 11551 | { |
bad1aba3 | 11552 | gas_assert (GPR_SIZE == 64); |
c0ebe874 | 11553 | macro_build (NULL, "dmtc1", "t,S", AT, op[0]); |
ca4e0257 | 11554 | } |
252b5132 RH |
11555 | else |
11556 | { | |
c0ebe874 | 11557 | macro_build (NULL, "mtc1", "t,G", AT, op[0] + 1); |
252b5132 | 11558 | if (offset_expr.X_op == O_absent) |
c0ebe874 | 11559 | macro_build (NULL, "mtc1", "t,G", 0, op[0]); |
252b5132 RH |
11560 | else |
11561 | { | |
9c2799c2 | 11562 | gas_assert (offset_expr.X_op == O_constant); |
67c0d1eb | 11563 | load_register (AT, &offset_expr, 0); |
c0ebe874 | 11564 | macro_build (NULL, "mtc1", "t,G", AT, op[0]); |
252b5132 RH |
11565 | } |
11566 | } | |
11567 | break; | |
11568 | } | |
11569 | ||
b0e6f033 RS |
11570 | gas_assert (imm_expr.X_op == O_absent |
11571 | && offset_expr.X_op == O_symbol | |
90ecf173 | 11572 | && offset_expr.X_add_number == 0); |
252b5132 RH |
11573 | s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol)); |
11574 | if (strcmp (s, ".lit8") == 0) | |
f2ae14a1 | 11575 | { |
c0ebe874 | 11576 | op[2] = mips_gp_register; |
f2ae14a1 RS |
11577 | offset_reloc[0] = BFD_RELOC_MIPS_LITERAL; |
11578 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
11579 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
11580 | } |
11581 | else | |
11582 | { | |
9c2799c2 | 11583 | gas_assert (strcmp (s, RDATA_SECTION_NAME) == 0); |
8fc2e39e | 11584 | used_at = 1; |
0a44bf69 | 11585 | if (mips_pic != NO_PIC) |
67c0d1eb RS |
11586 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, |
11587 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
252b5132 RH |
11588 | else |
11589 | { | |
11590 | /* FIXME: This won't work for a 64 bit address. */ | |
67c0d1eb | 11591 | macro_build_lui (&offset_expr, AT); |
252b5132 | 11592 | } |
bdaaa2e1 | 11593 | |
c0ebe874 | 11594 | op[2] = AT; |
f2ae14a1 RS |
11595 | offset_reloc[0] = BFD_RELOC_LO16; |
11596 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
11597 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
11598 | } | |
11599 | align = 8; | |
11600 | /* Fall through */ | |
c4a68bea | 11601 | |
252b5132 RH |
11602 | case M_L_DAB: |
11603 | /* | |
11604 | * The MIPS assembler seems to check for X_add_number not | |
11605 | * being double aligned and generating: | |
11606 | * lui at,%hi(foo+1) | |
11607 | * addu at,at,v1 | |
11608 | * addiu at,at,%lo(foo+1) | |
11609 | * lwc1 f2,0(at) | |
11610 | * lwc1 f3,4(at) | |
11611 | * But, the resulting address is the same after relocation so why | |
11612 | * generate the extra instruction? | |
11613 | */ | |
bdaaa2e1 | 11614 | /* Itbl support may require additional care here. */ |
252b5132 | 11615 | coproc = 1; |
df58fc94 | 11616 | fmt = "T,o(b)"; |
0aa27725 | 11617 | if (CPU_HAS_LDC1_SDC1 (mips_opts.arch)) |
252b5132 RH |
11618 | { |
11619 | s = "ldc1"; | |
df58fc94 | 11620 | goto ld_st; |
252b5132 | 11621 | } |
252b5132 | 11622 | s = "lwc1"; |
252b5132 RH |
11623 | goto ldd_std; |
11624 | ||
11625 | case M_S_DAB: | |
df58fc94 RS |
11626 | gas_assert (!mips_opts.micromips); |
11627 | /* Itbl support may require additional care here. */ | |
11628 | coproc = 1; | |
11629 | fmt = "T,o(b)"; | |
0aa27725 | 11630 | if (CPU_HAS_LDC1_SDC1 (mips_opts.arch)) |
252b5132 RH |
11631 | { |
11632 | s = "sdc1"; | |
df58fc94 | 11633 | goto ld_st; |
252b5132 | 11634 | } |
252b5132 | 11635 | s = "swc1"; |
252b5132 RH |
11636 | goto ldd_std; |
11637 | ||
e407c74b NC |
11638 | case M_LQ_AB: |
11639 | fmt = "t,o(b)"; | |
11640 | s = "lq"; | |
11641 | goto ld; | |
11642 | ||
11643 | case M_SQ_AB: | |
11644 | fmt = "t,o(b)"; | |
11645 | s = "sq"; | |
11646 | goto ld_st; | |
11647 | ||
252b5132 | 11648 | case M_LD_AB: |
df58fc94 | 11649 | fmt = "t,o(b)"; |
bad1aba3 | 11650 | if (GPR_SIZE == 64) |
252b5132 RH |
11651 | { |
11652 | s = "ld"; | |
11653 | goto ld; | |
11654 | } | |
252b5132 | 11655 | s = "lw"; |
252b5132 RH |
11656 | goto ldd_std; |
11657 | ||
11658 | case M_SD_AB: | |
df58fc94 | 11659 | fmt = "t,o(b)"; |
bad1aba3 | 11660 | if (GPR_SIZE == 64) |
252b5132 RH |
11661 | { |
11662 | s = "sd"; | |
df58fc94 | 11663 | goto ld_st; |
252b5132 | 11664 | } |
252b5132 | 11665 | s = "sw"; |
252b5132 RH |
11666 | |
11667 | ldd_std: | |
f2ae14a1 RS |
11668 | /* Even on a big endian machine $fn comes before $fn+1. We have |
11669 | to adjust when loading from memory. We set coproc if we must | |
11670 | load $fn+1 first. */ | |
11671 | /* Itbl support may require additional care here. */ | |
11672 | if (!target_big_endian) | |
11673 | coproc = 0; | |
11674 | ||
c0ebe874 | 11675 | breg = op[2]; |
f2ae14a1 RS |
11676 | if (small_offset_p (0, align, 16)) |
11677 | { | |
11678 | ep = &offset_expr; | |
11679 | if (!small_offset_p (4, align, 16)) | |
11680 | { | |
11681 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", AT, breg, | |
11682 | -1, offset_reloc[0], offset_reloc[1], | |
11683 | offset_reloc[2]); | |
11684 | expr1.X_add_number = 0; | |
11685 | ep = &expr1; | |
11686 | breg = AT; | |
11687 | used_at = 1; | |
11688 | offset_reloc[0] = BFD_RELOC_LO16; | |
11689 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
11690 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
11691 | } | |
c0ebe874 | 11692 | if (strcmp (s, "lw") == 0 && op[0] == breg) |
f2ae14a1 RS |
11693 | { |
11694 | ep->X_add_number += 4; | |
c0ebe874 | 11695 | macro_build (ep, s, fmt, op[0] + 1, -1, offset_reloc[0], |
f2ae14a1 RS |
11696 | offset_reloc[1], offset_reloc[2], breg); |
11697 | ep->X_add_number -= 4; | |
c0ebe874 | 11698 | macro_build (ep, s, fmt, op[0], -1, offset_reloc[0], |
f2ae14a1 RS |
11699 | offset_reloc[1], offset_reloc[2], breg); |
11700 | } | |
11701 | else | |
11702 | { | |
c0ebe874 | 11703 | macro_build (ep, s, fmt, coproc ? op[0] + 1 : op[0], -1, |
f2ae14a1 RS |
11704 | offset_reloc[0], offset_reloc[1], offset_reloc[2], |
11705 | breg); | |
11706 | ep->X_add_number += 4; | |
c0ebe874 | 11707 | macro_build (ep, s, fmt, coproc ? op[0] : op[0] + 1, -1, |
f2ae14a1 RS |
11708 | offset_reloc[0], offset_reloc[1], offset_reloc[2], |
11709 | breg); | |
11710 | } | |
11711 | break; | |
11712 | } | |
11713 | ||
252b5132 RH |
11714 | if (offset_expr.X_op != O_symbol |
11715 | && offset_expr.X_op != O_constant) | |
11716 | { | |
1661c76c | 11717 | as_bad (_("expression too complex")); |
252b5132 RH |
11718 | offset_expr.X_op = O_constant; |
11719 | } | |
11720 | ||
2051e8c4 MR |
11721 | if (HAVE_32BIT_ADDRESSES |
11722 | && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) | |
55e08f71 NC |
11723 | { |
11724 | char value [32]; | |
11725 | ||
11726 | sprintf_vma (value, offset_expr.X_add_number); | |
1661c76c | 11727 | as_bad (_("number (0x%s) larger than 32 bits"), value); |
55e08f71 | 11728 | } |
2051e8c4 | 11729 | |
90ecf173 | 11730 | if (mips_pic == NO_PIC || offset_expr.X_op == O_constant) |
252b5132 RH |
11731 | { |
11732 | /* If this is a reference to a GP relative symbol, we want | |
c0ebe874 RS |
11733 | <op> op[0],<sym>($gp) (BFD_RELOC_GPREL16) |
11734 | <op> op[0]+1,<sym>+4($gp) (BFD_RELOC_GPREL16) | |
252b5132 RH |
11735 | If we have a base register, we use this |
11736 | addu $at,$breg,$gp | |
c0ebe874 RS |
11737 | <op> op[0],<sym>($at) (BFD_RELOC_GPREL16) |
11738 | <op> op[0]+1,<sym>+4($at) (BFD_RELOC_GPREL16) | |
252b5132 RH |
11739 | If this is not a GP relative symbol, we want |
11740 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
c0ebe874 RS |
11741 | <op> op[0],<sym>($at) (BFD_RELOC_LO16) |
11742 | <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16) | |
252b5132 RH |
11743 | If there is a base register, we add it to $at after the |
11744 | lui instruction. If there is a constant, we always use | |
11745 | the last case. */ | |
39a59cf8 MR |
11746 | if (offset_expr.X_op == O_symbol |
11747 | && (valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET | |
6caf9ef4 | 11748 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 11749 | { |
4d7206a2 | 11750 | relax_start (offset_expr.X_add_symbol); |
252b5132 RH |
11751 | if (breg == 0) |
11752 | { | |
c9914766 | 11753 | tempreg = mips_gp_register; |
252b5132 RH |
11754 | } |
11755 | else | |
11756 | { | |
67c0d1eb | 11757 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 11758 | AT, breg, mips_gp_register); |
252b5132 | 11759 | tempreg = AT; |
252b5132 RH |
11760 | used_at = 1; |
11761 | } | |
11762 | ||
beae10d5 | 11763 | /* Itbl support may require additional care here. */ |
c0ebe874 | 11764 | macro_build (&offset_expr, s, fmt, coproc ? op[0] + 1 : op[0], |
17a2f251 | 11765 | BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
11766 | offset_expr.X_add_number += 4; |
11767 | ||
11768 | /* Set mips_optimize to 2 to avoid inserting an | |
11769 | undesired nop. */ | |
11770 | hold_mips_optimize = mips_optimize; | |
11771 | mips_optimize = 2; | |
beae10d5 | 11772 | /* Itbl support may require additional care here. */ |
c0ebe874 | 11773 | macro_build (&offset_expr, s, fmt, coproc ? op[0] : op[0] + 1, |
17a2f251 | 11774 | BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
11775 | mips_optimize = hold_mips_optimize; |
11776 | ||
4d7206a2 | 11777 | relax_switch (); |
252b5132 | 11778 | |
0970e49e | 11779 | offset_expr.X_add_number -= 4; |
252b5132 | 11780 | } |
8fc2e39e | 11781 | used_at = 1; |
f2ae14a1 RS |
11782 | if (offset_high_part (offset_expr.X_add_number, 16) |
11783 | != offset_high_part (offset_expr.X_add_number + 4, 16)) | |
11784 | { | |
11785 | load_address (AT, &offset_expr, &used_at); | |
11786 | offset_expr.X_op = O_constant; | |
11787 | offset_expr.X_add_number = 0; | |
11788 | } | |
11789 | else | |
11790 | macro_build_lui (&offset_expr, AT); | |
252b5132 | 11791 | if (breg != 0) |
67c0d1eb | 11792 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 11793 | /* Itbl support may require additional care here. */ |
c0ebe874 | 11794 | macro_build (&offset_expr, s, fmt, coproc ? op[0] + 1 : op[0], |
17a2f251 | 11795 | BFD_RELOC_LO16, AT); |
252b5132 RH |
11796 | /* FIXME: How do we handle overflow here? */ |
11797 | offset_expr.X_add_number += 4; | |
beae10d5 | 11798 | /* Itbl support may require additional care here. */ |
c0ebe874 | 11799 | macro_build (&offset_expr, s, fmt, coproc ? op[0] : op[0] + 1, |
17a2f251 | 11800 | BFD_RELOC_LO16, AT); |
4d7206a2 RS |
11801 | if (mips_relax.sequence) |
11802 | relax_end (); | |
bdaaa2e1 | 11803 | } |
0a44bf69 | 11804 | else if (!mips_big_got) |
252b5132 | 11805 | { |
252b5132 RH |
11806 | /* If this is a reference to an external symbol, we want |
11807 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
11808 | nop | |
c0ebe874 RS |
11809 | <op> op[0],0($at) |
11810 | <op> op[0]+1,4($at) | |
252b5132 RH |
11811 | Otherwise we want |
11812 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
11813 | nop | |
c0ebe874 RS |
11814 | <op> op[0],<sym>($at) (BFD_RELOC_LO16) |
11815 | <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16) | |
252b5132 RH |
11816 | If there is a base register we add it to $at before the |
11817 | lwc1 instructions. If there is a constant we include it | |
11818 | in the lwc1 instructions. */ | |
11819 | used_at = 1; | |
11820 | expr1.X_add_number = offset_expr.X_add_number; | |
252b5132 RH |
11821 | if (expr1.X_add_number < -0x8000 |
11822 | || expr1.X_add_number >= 0x8000 - 4) | |
11823 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 11824 | load_got_offset (AT, &offset_expr); |
269137b2 | 11825 | load_delay_nop (); |
252b5132 | 11826 | if (breg != 0) |
67c0d1eb | 11827 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
252b5132 RH |
11828 | |
11829 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
11830 | nop. */ | |
11831 | hold_mips_optimize = mips_optimize; | |
11832 | mips_optimize = 2; | |
4d7206a2 | 11833 | |
beae10d5 | 11834 | /* Itbl support may require additional care here. */ |
4d7206a2 | 11835 | relax_start (offset_expr.X_add_symbol); |
c0ebe874 | 11836 | macro_build (&expr1, s, fmt, coproc ? op[0] + 1 : op[0], |
67c0d1eb | 11837 | BFD_RELOC_LO16, AT); |
4d7206a2 | 11838 | expr1.X_add_number += 4; |
c0ebe874 | 11839 | macro_build (&expr1, s, fmt, coproc ? op[0] : op[0] + 1, |
67c0d1eb | 11840 | BFD_RELOC_LO16, AT); |
4d7206a2 | 11841 | relax_switch (); |
c0ebe874 | 11842 | macro_build (&offset_expr, s, fmt, coproc ? op[0] + 1 : op[0], |
67c0d1eb | 11843 | BFD_RELOC_LO16, AT); |
4d7206a2 | 11844 | offset_expr.X_add_number += 4; |
c0ebe874 | 11845 | macro_build (&offset_expr, s, fmt, coproc ? op[0] : op[0] + 1, |
67c0d1eb | 11846 | BFD_RELOC_LO16, AT); |
4d7206a2 | 11847 | relax_end (); |
252b5132 | 11848 | |
4d7206a2 | 11849 | mips_optimize = hold_mips_optimize; |
252b5132 | 11850 | } |
0a44bf69 | 11851 | else if (mips_big_got) |
252b5132 | 11852 | { |
67c0d1eb | 11853 | int gpdelay; |
252b5132 RH |
11854 | |
11855 | /* If this is a reference to an external symbol, we want | |
11856 | lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
11857 | addu $at,$at,$gp | |
11858 | lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16) | |
11859 | nop | |
c0ebe874 RS |
11860 | <op> op[0],0($at) |
11861 | <op> op[0]+1,4($at) | |
252b5132 RH |
11862 | Otherwise we want |
11863 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
11864 | nop | |
c0ebe874 RS |
11865 | <op> op[0],<sym>($at) (BFD_RELOC_LO16) |
11866 | <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16) | |
252b5132 RH |
11867 | If there is a base register we add it to $at before the |
11868 | lwc1 instructions. If there is a constant we include it | |
11869 | in the lwc1 instructions. */ | |
11870 | used_at = 1; | |
11871 | expr1.X_add_number = offset_expr.X_add_number; | |
11872 | offset_expr.X_add_number = 0; | |
11873 | if (expr1.X_add_number < -0x8000 | |
11874 | || expr1.X_add_number >= 0x8000 - 4) | |
11875 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 11876 | gpdelay = reg_needs_delay (mips_gp_register); |
4d7206a2 | 11877 | relax_start (offset_expr.X_add_symbol); |
df58fc94 | 11878 | macro_build (&offset_expr, "lui", LUI_FMT, |
67c0d1eb RS |
11879 | AT, BFD_RELOC_MIPS_GOT_HI16); |
11880 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 11881 | AT, AT, mips_gp_register); |
67c0d1eb | 11882 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
17a2f251 | 11883 | AT, BFD_RELOC_MIPS_GOT_LO16, AT); |
269137b2 | 11884 | load_delay_nop (); |
252b5132 | 11885 | if (breg != 0) |
67c0d1eb | 11886 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 11887 | /* Itbl support may require additional care here. */ |
c0ebe874 | 11888 | macro_build (&expr1, s, fmt, coproc ? op[0] + 1 : op[0], |
17a2f251 | 11889 | BFD_RELOC_LO16, AT); |
252b5132 RH |
11890 | expr1.X_add_number += 4; |
11891 | ||
11892 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
11893 | nop. */ | |
11894 | hold_mips_optimize = mips_optimize; | |
11895 | mips_optimize = 2; | |
beae10d5 | 11896 | /* Itbl support may require additional care here. */ |
c0ebe874 | 11897 | macro_build (&expr1, s, fmt, coproc ? op[0] : op[0] + 1, |
17a2f251 | 11898 | BFD_RELOC_LO16, AT); |
252b5132 RH |
11899 | mips_optimize = hold_mips_optimize; |
11900 | expr1.X_add_number -= 4; | |
11901 | ||
4d7206a2 RS |
11902 | relax_switch (); |
11903 | offset_expr.X_add_number = expr1.X_add_number; | |
67c0d1eb RS |
11904 | if (gpdelay) |
11905 | macro_build (NULL, "nop", ""); | |
11906 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, | |
11907 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 11908 | load_delay_nop (); |
252b5132 | 11909 | if (breg != 0) |
67c0d1eb | 11910 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 11911 | /* Itbl support may require additional care here. */ |
c0ebe874 | 11912 | macro_build (&offset_expr, s, fmt, coproc ? op[0] + 1 : op[0], |
67c0d1eb | 11913 | BFD_RELOC_LO16, AT); |
4d7206a2 | 11914 | offset_expr.X_add_number += 4; |
252b5132 RH |
11915 | |
11916 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
11917 | nop. */ | |
11918 | hold_mips_optimize = mips_optimize; | |
11919 | mips_optimize = 2; | |
beae10d5 | 11920 | /* Itbl support may require additional care here. */ |
c0ebe874 | 11921 | macro_build (&offset_expr, s, fmt, coproc ? op[0] : op[0] + 1, |
67c0d1eb | 11922 | BFD_RELOC_LO16, AT); |
252b5132 | 11923 | mips_optimize = hold_mips_optimize; |
4d7206a2 | 11924 | relax_end (); |
252b5132 | 11925 | } |
252b5132 RH |
11926 | else |
11927 | abort (); | |
11928 | ||
252b5132 | 11929 | break; |
dd6a37e7 AP |
11930 | |
11931 | case M_SAA_AB: | |
dd6a37e7 | 11932 | s = "saa"; |
7f3c4072 | 11933 | offbits = 0; |
dd6a37e7 AP |
11934 | fmt = "t,(b)"; |
11935 | goto ld_st; | |
11936 | case M_SAAD_AB: | |
dd6a37e7 | 11937 | s = "saad"; |
7f3c4072 | 11938 | offbits = 0; |
dd6a37e7 AP |
11939 | fmt = "t,(b)"; |
11940 | goto ld_st; | |
11941 | ||
252b5132 RH |
11942 | /* New code added to support COPZ instructions. |
11943 | This code builds table entries out of the macros in mip_opcodes. | |
11944 | R4000 uses interlocks to handle coproc delays. | |
11945 | Other chips (like the R3000) require nops to be inserted for delays. | |
11946 | ||
f72c8c98 | 11947 | FIXME: Currently, we require that the user handle delays. |
252b5132 RH |
11948 | In order to fill delay slots for non-interlocked chips, |
11949 | we must have a way to specify delays based on the coprocessor. | |
11950 | Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc. | |
11951 | What are the side-effects of the cop instruction? | |
11952 | What cache support might we have and what are its effects? | |
11953 | Both coprocessor & memory require delays. how long??? | |
bdaaa2e1 | 11954 | What registers are read/set/modified? |
252b5132 RH |
11955 | |
11956 | If an itbl is provided to interpret cop instructions, | |
bdaaa2e1 | 11957 | this knowledge can be encoded in the itbl spec. */ |
252b5132 RH |
11958 | |
11959 | case M_COP0: | |
11960 | s = "c0"; | |
11961 | goto copz; | |
11962 | case M_COP1: | |
11963 | s = "c1"; | |
11964 | goto copz; | |
11965 | case M_COP2: | |
11966 | s = "c2"; | |
11967 | goto copz; | |
11968 | case M_COP3: | |
11969 | s = "c3"; | |
11970 | copz: | |
df58fc94 | 11971 | gas_assert (!mips_opts.micromips); |
252b5132 RH |
11972 | /* For now we just do C (same as Cz). The parameter will be |
11973 | stored in insn_opcode by mips_ip. */ | |
c8276761 | 11974 | macro_build (NULL, s, "C", (int) ip->insn_opcode); |
8fc2e39e | 11975 | break; |
252b5132 | 11976 | |
ea1fb5dc | 11977 | case M_MOVE: |
c0ebe874 | 11978 | move_register (op[0], op[1]); |
8fc2e39e | 11979 | break; |
ea1fb5dc | 11980 | |
833794fc MR |
11981 | case M_MOVEP: |
11982 | gas_assert (mips_opts.micromips); | |
11983 | gas_assert (mips_opts.insn32); | |
c0ebe874 RS |
11984 | move_register (micromips_to_32_reg_h_map1[op[0]], |
11985 | micromips_to_32_reg_m_map[op[1]]); | |
11986 | move_register (micromips_to_32_reg_h_map2[op[0]], | |
11987 | micromips_to_32_reg_n_map[op[2]]); | |
833794fc MR |
11988 | break; |
11989 | ||
252b5132 RH |
11990 | case M_DMUL: |
11991 | dbl = 1; | |
11992 | case M_MUL: | |
e407c74b | 11993 | if (mips_opts.arch == CPU_R5900) |
c0ebe874 RS |
11994 | macro_build (NULL, dbl ? "dmultu" : "multu", "d,s,t", op[0], op[1], |
11995 | op[2]); | |
e407c74b NC |
11996 | else |
11997 | { | |
c0ebe874 RS |
11998 | macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", op[1], op[2]); |
11999 | macro_build (NULL, "mflo", MFHL_FMT, op[0]); | |
e407c74b | 12000 | } |
8fc2e39e | 12001 | break; |
252b5132 RH |
12002 | |
12003 | case M_DMUL_I: | |
12004 | dbl = 1; | |
12005 | case M_MUL_I: | |
12006 | /* The MIPS assembler some times generates shifts and adds. I'm | |
12007 | not trying to be that fancy. GCC should do this for us | |
12008 | anyway. */ | |
8fc2e39e | 12009 | used_at = 1; |
67c0d1eb | 12010 | load_register (AT, &imm_expr, dbl); |
c0ebe874 RS |
12011 | macro_build (NULL, dbl ? "dmult" : "mult", "s,t", op[1], AT); |
12012 | macro_build (NULL, "mflo", MFHL_FMT, op[0]); | |
252b5132 RH |
12013 | break; |
12014 | ||
12015 | case M_DMULO_I: | |
12016 | dbl = 1; | |
12017 | case M_MULO_I: | |
12018 | imm = 1; | |
12019 | goto do_mulo; | |
12020 | ||
12021 | case M_DMULO: | |
12022 | dbl = 1; | |
12023 | case M_MULO: | |
12024 | do_mulo: | |
7d10b47d | 12025 | start_noreorder (); |
8fc2e39e | 12026 | used_at = 1; |
252b5132 | 12027 | if (imm) |
67c0d1eb | 12028 | load_register (AT, &imm_expr, dbl); |
c0ebe874 RS |
12029 | macro_build (NULL, dbl ? "dmult" : "mult", "s,t", |
12030 | op[1], imm ? AT : op[2]); | |
12031 | macro_build (NULL, "mflo", MFHL_FMT, op[0]); | |
12032 | macro_build (NULL, dbl ? "dsra32" : "sra", SHFT_FMT, op[0], op[0], 31); | |
df58fc94 | 12033 | macro_build (NULL, "mfhi", MFHL_FMT, AT); |
252b5132 | 12034 | if (mips_trap) |
c0ebe874 | 12035 | macro_build (NULL, "tne", TRAP_FMT, op[0], AT, 6); |
252b5132 RH |
12036 | else |
12037 | { | |
df58fc94 RS |
12038 | if (mips_opts.micromips) |
12039 | micromips_label_expr (&label_expr); | |
12040 | else | |
12041 | label_expr.X_add_number = 8; | |
c0ebe874 | 12042 | macro_build (&label_expr, "beq", "s,t,p", op[0], AT); |
a605d2b3 | 12043 | macro_build (NULL, "nop", ""); |
df58fc94 RS |
12044 | macro_build (NULL, "break", BRK_FMT, 6); |
12045 | if (mips_opts.micromips) | |
12046 | micromips_add_label (); | |
252b5132 | 12047 | } |
7d10b47d | 12048 | end_noreorder (); |
c0ebe874 | 12049 | macro_build (NULL, "mflo", MFHL_FMT, op[0]); |
252b5132 RH |
12050 | break; |
12051 | ||
12052 | case M_DMULOU_I: | |
12053 | dbl = 1; | |
12054 | case M_MULOU_I: | |
12055 | imm = 1; | |
12056 | goto do_mulou; | |
12057 | ||
12058 | case M_DMULOU: | |
12059 | dbl = 1; | |
12060 | case M_MULOU: | |
12061 | do_mulou: | |
7d10b47d | 12062 | start_noreorder (); |
8fc2e39e | 12063 | used_at = 1; |
252b5132 | 12064 | if (imm) |
67c0d1eb RS |
12065 | load_register (AT, &imm_expr, dbl); |
12066 | macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", | |
c0ebe874 | 12067 | op[1], imm ? AT : op[2]); |
df58fc94 | 12068 | macro_build (NULL, "mfhi", MFHL_FMT, AT); |
c0ebe874 | 12069 | macro_build (NULL, "mflo", MFHL_FMT, op[0]); |
252b5132 | 12070 | if (mips_trap) |
df58fc94 | 12071 | macro_build (NULL, "tne", TRAP_FMT, AT, ZERO, 6); |
252b5132 RH |
12072 | else |
12073 | { | |
df58fc94 RS |
12074 | if (mips_opts.micromips) |
12075 | micromips_label_expr (&label_expr); | |
12076 | else | |
12077 | label_expr.X_add_number = 8; | |
12078 | macro_build (&label_expr, "beq", "s,t,p", AT, ZERO); | |
a605d2b3 | 12079 | macro_build (NULL, "nop", ""); |
df58fc94 RS |
12080 | macro_build (NULL, "break", BRK_FMT, 6); |
12081 | if (mips_opts.micromips) | |
12082 | micromips_add_label (); | |
252b5132 | 12083 | } |
7d10b47d | 12084 | end_noreorder (); |
252b5132 RH |
12085 | break; |
12086 | ||
771c7ce4 | 12087 | case M_DROL: |
fef14a42 | 12088 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 | 12089 | { |
c0ebe874 | 12090 | if (op[0] == op[1]) |
82dd0097 CD |
12091 | { |
12092 | tempreg = AT; | |
12093 | used_at = 1; | |
12094 | } | |
12095 | else | |
c0ebe874 RS |
12096 | tempreg = op[0]; |
12097 | macro_build (NULL, "dnegu", "d,w", tempreg, op[2]); | |
12098 | macro_build (NULL, "drorv", "d,t,s", op[0], op[1], tempreg); | |
8fc2e39e | 12099 | break; |
82dd0097 | 12100 | } |
8fc2e39e | 12101 | used_at = 1; |
c0ebe874 RS |
12102 | macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, op[2]); |
12103 | macro_build (NULL, "dsrlv", "d,t,s", AT, op[1], AT); | |
12104 | macro_build (NULL, "dsllv", "d,t,s", op[0], op[1], op[2]); | |
12105 | macro_build (NULL, "or", "d,v,t", op[0], op[0], AT); | |
771c7ce4 TS |
12106 | break; |
12107 | ||
252b5132 | 12108 | case M_ROL: |
fef14a42 | 12109 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 | 12110 | { |
c0ebe874 | 12111 | if (op[0] == op[1]) |
82dd0097 CD |
12112 | { |
12113 | tempreg = AT; | |
12114 | used_at = 1; | |
12115 | } | |
12116 | else | |
c0ebe874 RS |
12117 | tempreg = op[0]; |
12118 | macro_build (NULL, "negu", "d,w", tempreg, op[2]); | |
12119 | macro_build (NULL, "rorv", "d,t,s", op[0], op[1], tempreg); | |
8fc2e39e | 12120 | break; |
82dd0097 | 12121 | } |
8fc2e39e | 12122 | used_at = 1; |
c0ebe874 RS |
12123 | macro_build (NULL, "subu", "d,v,t", AT, ZERO, op[2]); |
12124 | macro_build (NULL, "srlv", "d,t,s", AT, op[1], AT); | |
12125 | macro_build (NULL, "sllv", "d,t,s", op[0], op[1], op[2]); | |
12126 | macro_build (NULL, "or", "d,v,t", op[0], op[0], AT); | |
252b5132 RH |
12127 | break; |
12128 | ||
771c7ce4 TS |
12129 | case M_DROL_I: |
12130 | { | |
12131 | unsigned int rot; | |
91d6fa6a NC |
12132 | char *l; |
12133 | char *rr; | |
771c7ce4 | 12134 | |
771c7ce4 | 12135 | rot = imm_expr.X_add_number & 0x3f; |
fef14a42 | 12136 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
60b63b72 RS |
12137 | { |
12138 | rot = (64 - rot) & 0x3f; | |
12139 | if (rot >= 32) | |
c0ebe874 | 12140 | macro_build (NULL, "dror32", SHFT_FMT, op[0], op[1], rot - 32); |
60b63b72 | 12141 | else |
c0ebe874 | 12142 | macro_build (NULL, "dror", SHFT_FMT, op[0], op[1], rot); |
8fc2e39e | 12143 | break; |
60b63b72 | 12144 | } |
483fc7cd | 12145 | if (rot == 0) |
483fc7cd | 12146 | { |
c0ebe874 | 12147 | macro_build (NULL, "dsrl", SHFT_FMT, op[0], op[1], 0); |
8fc2e39e | 12148 | break; |
483fc7cd | 12149 | } |
82dd0097 | 12150 | l = (rot < 0x20) ? "dsll" : "dsll32"; |
91d6fa6a | 12151 | rr = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32"; |
82dd0097 | 12152 | rot &= 0x1f; |
8fc2e39e | 12153 | used_at = 1; |
c0ebe874 RS |
12154 | macro_build (NULL, l, SHFT_FMT, AT, op[1], rot); |
12155 | macro_build (NULL, rr, SHFT_FMT, op[0], op[1], (0x20 - rot) & 0x1f); | |
12156 | macro_build (NULL, "or", "d,v,t", op[0], op[0], AT); | |
771c7ce4 TS |
12157 | } |
12158 | break; | |
12159 | ||
252b5132 | 12160 | case M_ROL_I: |
771c7ce4 TS |
12161 | { |
12162 | unsigned int rot; | |
12163 | ||
771c7ce4 | 12164 | rot = imm_expr.X_add_number & 0x1f; |
fef14a42 | 12165 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
60b63b72 | 12166 | { |
c0ebe874 RS |
12167 | macro_build (NULL, "ror", SHFT_FMT, op[0], op[1], |
12168 | (32 - rot) & 0x1f); | |
8fc2e39e | 12169 | break; |
60b63b72 | 12170 | } |
483fc7cd | 12171 | if (rot == 0) |
483fc7cd | 12172 | { |
c0ebe874 | 12173 | macro_build (NULL, "srl", SHFT_FMT, op[0], op[1], 0); |
8fc2e39e | 12174 | break; |
483fc7cd | 12175 | } |
8fc2e39e | 12176 | used_at = 1; |
c0ebe874 RS |
12177 | macro_build (NULL, "sll", SHFT_FMT, AT, op[1], rot); |
12178 | macro_build (NULL, "srl", SHFT_FMT, op[0], op[1], (0x20 - rot) & 0x1f); | |
12179 | macro_build (NULL, "or", "d,v,t", op[0], op[0], AT); | |
771c7ce4 TS |
12180 | } |
12181 | break; | |
12182 | ||
12183 | case M_DROR: | |
fef14a42 | 12184 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 | 12185 | { |
c0ebe874 | 12186 | macro_build (NULL, "drorv", "d,t,s", op[0], op[1], op[2]); |
8fc2e39e | 12187 | break; |
82dd0097 | 12188 | } |
8fc2e39e | 12189 | used_at = 1; |
c0ebe874 RS |
12190 | macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, op[2]); |
12191 | macro_build (NULL, "dsllv", "d,t,s", AT, op[1], AT); | |
12192 | macro_build (NULL, "dsrlv", "d,t,s", op[0], op[1], op[2]); | |
12193 | macro_build (NULL, "or", "d,v,t", op[0], op[0], AT); | |
252b5132 RH |
12194 | break; |
12195 | ||
12196 | case M_ROR: | |
fef14a42 | 12197 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 | 12198 | { |
c0ebe874 | 12199 | macro_build (NULL, "rorv", "d,t,s", op[0], op[1], op[2]); |
8fc2e39e | 12200 | break; |
82dd0097 | 12201 | } |
8fc2e39e | 12202 | used_at = 1; |
c0ebe874 RS |
12203 | macro_build (NULL, "subu", "d,v,t", AT, ZERO, op[2]); |
12204 | macro_build (NULL, "sllv", "d,t,s", AT, op[1], AT); | |
12205 | macro_build (NULL, "srlv", "d,t,s", op[0], op[1], op[2]); | |
12206 | macro_build (NULL, "or", "d,v,t", op[0], op[0], AT); | |
252b5132 RH |
12207 | break; |
12208 | ||
771c7ce4 TS |
12209 | case M_DROR_I: |
12210 | { | |
12211 | unsigned int rot; | |
91d6fa6a NC |
12212 | char *l; |
12213 | char *rr; | |
771c7ce4 | 12214 | |
771c7ce4 | 12215 | rot = imm_expr.X_add_number & 0x3f; |
fef14a42 | 12216 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 CD |
12217 | { |
12218 | if (rot >= 32) | |
c0ebe874 | 12219 | macro_build (NULL, "dror32", SHFT_FMT, op[0], op[1], rot - 32); |
82dd0097 | 12220 | else |
c0ebe874 | 12221 | macro_build (NULL, "dror", SHFT_FMT, op[0], op[1], rot); |
8fc2e39e | 12222 | break; |
82dd0097 | 12223 | } |
483fc7cd | 12224 | if (rot == 0) |
483fc7cd | 12225 | { |
c0ebe874 | 12226 | macro_build (NULL, "dsrl", SHFT_FMT, op[0], op[1], 0); |
8fc2e39e | 12227 | break; |
483fc7cd | 12228 | } |
91d6fa6a | 12229 | rr = (rot < 0x20) ? "dsrl" : "dsrl32"; |
82dd0097 CD |
12230 | l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32"; |
12231 | rot &= 0x1f; | |
8fc2e39e | 12232 | used_at = 1; |
c0ebe874 RS |
12233 | macro_build (NULL, rr, SHFT_FMT, AT, op[1], rot); |
12234 | macro_build (NULL, l, SHFT_FMT, op[0], op[1], (0x20 - rot) & 0x1f); | |
12235 | macro_build (NULL, "or", "d,v,t", op[0], op[0], AT); | |
771c7ce4 TS |
12236 | } |
12237 | break; | |
12238 | ||
252b5132 | 12239 | case M_ROR_I: |
771c7ce4 TS |
12240 | { |
12241 | unsigned int rot; | |
12242 | ||
771c7ce4 | 12243 | rot = imm_expr.X_add_number & 0x1f; |
fef14a42 | 12244 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 | 12245 | { |
c0ebe874 | 12246 | macro_build (NULL, "ror", SHFT_FMT, op[0], op[1], rot); |
8fc2e39e | 12247 | break; |
82dd0097 | 12248 | } |
483fc7cd | 12249 | if (rot == 0) |
483fc7cd | 12250 | { |
c0ebe874 | 12251 | macro_build (NULL, "srl", SHFT_FMT, op[0], op[1], 0); |
8fc2e39e | 12252 | break; |
483fc7cd | 12253 | } |
8fc2e39e | 12254 | used_at = 1; |
c0ebe874 RS |
12255 | macro_build (NULL, "srl", SHFT_FMT, AT, op[1], rot); |
12256 | macro_build (NULL, "sll", SHFT_FMT, op[0], op[1], (0x20 - rot) & 0x1f); | |
12257 | macro_build (NULL, "or", "d,v,t", op[0], op[0], AT); | |
771c7ce4 | 12258 | } |
252b5132 RH |
12259 | break; |
12260 | ||
252b5132 | 12261 | case M_SEQ: |
c0ebe874 RS |
12262 | if (op[1] == 0) |
12263 | macro_build (&expr1, "sltiu", "t,r,j", op[0], op[2], BFD_RELOC_LO16); | |
12264 | else if (op[2] == 0) | |
12265 | macro_build (&expr1, "sltiu", "t,r,j", op[0], op[1], BFD_RELOC_LO16); | |
252b5132 RH |
12266 | else |
12267 | { | |
c0ebe874 RS |
12268 | macro_build (NULL, "xor", "d,v,t", op[0], op[1], op[2]); |
12269 | macro_build (&expr1, "sltiu", "t,r,j", op[0], op[0], BFD_RELOC_LO16); | |
252b5132 | 12270 | } |
8fc2e39e | 12271 | break; |
252b5132 RH |
12272 | |
12273 | case M_SEQ_I: | |
b0e6f033 | 12274 | if (imm_expr.X_add_number == 0) |
252b5132 | 12275 | { |
c0ebe874 | 12276 | macro_build (&expr1, "sltiu", "t,r,j", op[0], op[1], BFD_RELOC_LO16); |
8fc2e39e | 12277 | break; |
252b5132 | 12278 | } |
c0ebe874 | 12279 | if (op[1] == 0) |
252b5132 | 12280 | { |
1661c76c | 12281 | as_warn (_("instruction %s: result is always false"), |
252b5132 | 12282 | ip->insn_mo->name); |
c0ebe874 | 12283 | move_register (op[0], 0); |
8fc2e39e | 12284 | break; |
252b5132 | 12285 | } |
dd3cbb7e NC |
12286 | if (CPU_HAS_SEQ (mips_opts.arch) |
12287 | && -512 <= imm_expr.X_add_number | |
12288 | && imm_expr.X_add_number < 512) | |
12289 | { | |
c0ebe874 | 12290 | macro_build (NULL, "seqi", "t,r,+Q", op[0], op[1], |
750bdd57 | 12291 | (int) imm_expr.X_add_number); |
dd3cbb7e NC |
12292 | break; |
12293 | } | |
b0e6f033 | 12294 | if (imm_expr.X_add_number >= 0 |
252b5132 | 12295 | && imm_expr.X_add_number < 0x10000) |
c0ebe874 | 12296 | macro_build (&imm_expr, "xori", "t,r,i", op[0], op[1], BFD_RELOC_LO16); |
b0e6f033 | 12297 | else if (imm_expr.X_add_number > -0x8000 |
252b5132 RH |
12298 | && imm_expr.X_add_number < 0) |
12299 | { | |
12300 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
bad1aba3 | 12301 | macro_build (&imm_expr, GPR_SIZE == 32 ? "addiu" : "daddiu", |
c0ebe874 | 12302 | "t,r,j", op[0], op[1], BFD_RELOC_LO16); |
252b5132 | 12303 | } |
dd3cbb7e NC |
12304 | else if (CPU_HAS_SEQ (mips_opts.arch)) |
12305 | { | |
12306 | used_at = 1; | |
bad1aba3 | 12307 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
c0ebe874 | 12308 | macro_build (NULL, "seq", "d,v,t", op[0], op[1], AT); |
dd3cbb7e NC |
12309 | break; |
12310 | } | |
252b5132 RH |
12311 | else |
12312 | { | |
bad1aba3 | 12313 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
c0ebe874 | 12314 | macro_build (NULL, "xor", "d,v,t", op[0], op[1], AT); |
252b5132 RH |
12315 | used_at = 1; |
12316 | } | |
c0ebe874 | 12317 | macro_build (&expr1, "sltiu", "t,r,j", op[0], op[0], BFD_RELOC_LO16); |
8fc2e39e | 12318 | break; |
252b5132 | 12319 | |
c0ebe874 | 12320 | case M_SGE: /* X >= Y <==> not (X < Y) */ |
252b5132 RH |
12321 | s = "slt"; |
12322 | goto sge; | |
12323 | case M_SGEU: | |
12324 | s = "sltu"; | |
12325 | sge: | |
c0ebe874 RS |
12326 | macro_build (NULL, s, "d,v,t", op[0], op[1], op[2]); |
12327 | macro_build (&expr1, "xori", "t,r,i", op[0], op[0], BFD_RELOC_LO16); | |
8fc2e39e | 12328 | break; |
252b5132 | 12329 | |
c0ebe874 | 12330 | case M_SGE_I: /* X >= I <==> not (X < I) */ |
252b5132 | 12331 | case M_SGEU_I: |
b0e6f033 | 12332 | if (imm_expr.X_add_number >= -0x8000 |
252b5132 | 12333 | && imm_expr.X_add_number < 0x8000) |
c0ebe874 RS |
12334 | macro_build (&imm_expr, mask == M_SGE_I ? "slti" : "sltiu", "t,r,j", |
12335 | op[0], op[1], BFD_RELOC_LO16); | |
252b5132 RH |
12336 | else |
12337 | { | |
bad1aba3 | 12338 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
67c0d1eb | 12339 | macro_build (NULL, mask == M_SGE_I ? "slt" : "sltu", "d,v,t", |
c0ebe874 | 12340 | op[0], op[1], AT); |
252b5132 RH |
12341 | used_at = 1; |
12342 | } | |
c0ebe874 | 12343 | macro_build (&expr1, "xori", "t,r,i", op[0], op[0], BFD_RELOC_LO16); |
8fc2e39e | 12344 | break; |
252b5132 | 12345 | |
c0ebe874 | 12346 | case M_SGT: /* X > Y <==> Y < X */ |
252b5132 RH |
12347 | s = "slt"; |
12348 | goto sgt; | |
12349 | case M_SGTU: | |
12350 | s = "sltu"; | |
12351 | sgt: | |
c0ebe874 | 12352 | macro_build (NULL, s, "d,v,t", op[0], op[2], op[1]); |
8fc2e39e | 12353 | break; |
252b5132 | 12354 | |
c0ebe874 | 12355 | case M_SGT_I: /* X > I <==> I < X */ |
252b5132 RH |
12356 | s = "slt"; |
12357 | goto sgti; | |
12358 | case M_SGTU_I: | |
12359 | s = "sltu"; | |
12360 | sgti: | |
8fc2e39e | 12361 | used_at = 1; |
bad1aba3 | 12362 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
c0ebe874 | 12363 | macro_build (NULL, s, "d,v,t", op[0], AT, op[1]); |
252b5132 RH |
12364 | break; |
12365 | ||
c0ebe874 | 12366 | case M_SLE: /* X <= Y <==> Y >= X <==> not (Y < X) */ |
252b5132 RH |
12367 | s = "slt"; |
12368 | goto sle; | |
12369 | case M_SLEU: | |
12370 | s = "sltu"; | |
12371 | sle: | |
c0ebe874 RS |
12372 | macro_build (NULL, s, "d,v,t", op[0], op[2], op[1]); |
12373 | macro_build (&expr1, "xori", "t,r,i", op[0], op[0], BFD_RELOC_LO16); | |
8fc2e39e | 12374 | break; |
252b5132 | 12375 | |
c0ebe874 | 12376 | case M_SLE_I: /* X <= I <==> I >= X <==> not (I < X) */ |
252b5132 RH |
12377 | s = "slt"; |
12378 | goto slei; | |
12379 | case M_SLEU_I: | |
12380 | s = "sltu"; | |
12381 | slei: | |
8fc2e39e | 12382 | used_at = 1; |
bad1aba3 | 12383 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
c0ebe874 RS |
12384 | macro_build (NULL, s, "d,v,t", op[0], AT, op[1]); |
12385 | macro_build (&expr1, "xori", "t,r,i", op[0], op[0], BFD_RELOC_LO16); | |
252b5132 RH |
12386 | break; |
12387 | ||
12388 | case M_SLT_I: | |
b0e6f033 | 12389 | if (imm_expr.X_add_number >= -0x8000 |
252b5132 RH |
12390 | && imm_expr.X_add_number < 0x8000) |
12391 | { | |
c0ebe874 RS |
12392 | macro_build (&imm_expr, "slti", "t,r,j", op[0], op[1], |
12393 | BFD_RELOC_LO16); | |
8fc2e39e | 12394 | break; |
252b5132 | 12395 | } |
8fc2e39e | 12396 | used_at = 1; |
bad1aba3 | 12397 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
c0ebe874 | 12398 | macro_build (NULL, "slt", "d,v,t", op[0], op[1], AT); |
252b5132 RH |
12399 | break; |
12400 | ||
12401 | case M_SLTU_I: | |
b0e6f033 | 12402 | if (imm_expr.X_add_number >= -0x8000 |
252b5132 RH |
12403 | && imm_expr.X_add_number < 0x8000) |
12404 | { | |
c0ebe874 | 12405 | macro_build (&imm_expr, "sltiu", "t,r,j", op[0], op[1], |
17a2f251 | 12406 | BFD_RELOC_LO16); |
8fc2e39e | 12407 | break; |
252b5132 | 12408 | } |
8fc2e39e | 12409 | used_at = 1; |
bad1aba3 | 12410 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
c0ebe874 | 12411 | macro_build (NULL, "sltu", "d,v,t", op[0], op[1], AT); |
252b5132 RH |
12412 | break; |
12413 | ||
12414 | case M_SNE: | |
c0ebe874 RS |
12415 | if (op[1] == 0) |
12416 | macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[2]); | |
12417 | else if (op[2] == 0) | |
12418 | macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[1]); | |
252b5132 RH |
12419 | else |
12420 | { | |
c0ebe874 RS |
12421 | macro_build (NULL, "xor", "d,v,t", op[0], op[1], op[2]); |
12422 | macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[0]); | |
252b5132 | 12423 | } |
8fc2e39e | 12424 | break; |
252b5132 RH |
12425 | |
12426 | case M_SNE_I: | |
b0e6f033 | 12427 | if (imm_expr.X_add_number == 0) |
252b5132 | 12428 | { |
c0ebe874 | 12429 | macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[1]); |
8fc2e39e | 12430 | break; |
252b5132 | 12431 | } |
c0ebe874 | 12432 | if (op[1] == 0) |
252b5132 | 12433 | { |
1661c76c | 12434 | as_warn (_("instruction %s: result is always true"), |
252b5132 | 12435 | ip->insn_mo->name); |
bad1aba3 | 12436 | macro_build (&expr1, GPR_SIZE == 32 ? "addiu" : "daddiu", "t,r,j", |
c0ebe874 | 12437 | op[0], 0, BFD_RELOC_LO16); |
8fc2e39e | 12438 | break; |
252b5132 | 12439 | } |
dd3cbb7e NC |
12440 | if (CPU_HAS_SEQ (mips_opts.arch) |
12441 | && -512 <= imm_expr.X_add_number | |
12442 | && imm_expr.X_add_number < 512) | |
12443 | { | |
c0ebe874 | 12444 | macro_build (NULL, "snei", "t,r,+Q", op[0], op[1], |
750bdd57 | 12445 | (int) imm_expr.X_add_number); |
dd3cbb7e NC |
12446 | break; |
12447 | } | |
b0e6f033 | 12448 | if (imm_expr.X_add_number >= 0 |
252b5132 RH |
12449 | && imm_expr.X_add_number < 0x10000) |
12450 | { | |
c0ebe874 RS |
12451 | macro_build (&imm_expr, "xori", "t,r,i", op[0], op[1], |
12452 | BFD_RELOC_LO16); | |
252b5132 | 12453 | } |
b0e6f033 | 12454 | else if (imm_expr.X_add_number > -0x8000 |
252b5132 RH |
12455 | && imm_expr.X_add_number < 0) |
12456 | { | |
12457 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
bad1aba3 | 12458 | macro_build (&imm_expr, GPR_SIZE == 32 ? "addiu" : "daddiu", |
c0ebe874 | 12459 | "t,r,j", op[0], op[1], BFD_RELOC_LO16); |
252b5132 | 12460 | } |
dd3cbb7e NC |
12461 | else if (CPU_HAS_SEQ (mips_opts.arch)) |
12462 | { | |
12463 | used_at = 1; | |
bad1aba3 | 12464 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
c0ebe874 | 12465 | macro_build (NULL, "sne", "d,v,t", op[0], op[1], AT); |
dd3cbb7e NC |
12466 | break; |
12467 | } | |
252b5132 RH |
12468 | else |
12469 | { | |
bad1aba3 | 12470 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
c0ebe874 | 12471 | macro_build (NULL, "xor", "d,v,t", op[0], op[1], AT); |
252b5132 RH |
12472 | used_at = 1; |
12473 | } | |
c0ebe874 | 12474 | macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[0]); |
8fc2e39e | 12475 | break; |
252b5132 | 12476 | |
df58fc94 RS |
12477 | case M_SUB_I: |
12478 | s = "addi"; | |
12479 | s2 = "sub"; | |
12480 | goto do_subi; | |
12481 | case M_SUBU_I: | |
12482 | s = "addiu"; | |
12483 | s2 = "subu"; | |
12484 | goto do_subi; | |
252b5132 RH |
12485 | case M_DSUB_I: |
12486 | dbl = 1; | |
df58fc94 RS |
12487 | s = "daddi"; |
12488 | s2 = "dsub"; | |
12489 | if (!mips_opts.micromips) | |
12490 | goto do_subi; | |
b0e6f033 | 12491 | if (imm_expr.X_add_number > -0x200 |
df58fc94 | 12492 | && imm_expr.X_add_number <= 0x200) |
252b5132 | 12493 | { |
b0e6f033 RS |
12494 | macro_build (NULL, s, "t,r,.", op[0], op[1], |
12495 | (int) -imm_expr.X_add_number); | |
8fc2e39e | 12496 | break; |
252b5132 | 12497 | } |
df58fc94 | 12498 | goto do_subi_i; |
252b5132 RH |
12499 | case M_DSUBU_I: |
12500 | dbl = 1; | |
df58fc94 RS |
12501 | s = "daddiu"; |
12502 | s2 = "dsubu"; | |
12503 | do_subi: | |
b0e6f033 | 12504 | if (imm_expr.X_add_number > -0x8000 |
252b5132 RH |
12505 | && imm_expr.X_add_number <= 0x8000) |
12506 | { | |
12507 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
c0ebe874 | 12508 | macro_build (&imm_expr, s, "t,r,j", op[0], op[1], BFD_RELOC_LO16); |
8fc2e39e | 12509 | break; |
252b5132 | 12510 | } |
df58fc94 | 12511 | do_subi_i: |
8fc2e39e | 12512 | used_at = 1; |
67c0d1eb | 12513 | load_register (AT, &imm_expr, dbl); |
c0ebe874 | 12514 | macro_build (NULL, s2, "d,v,t", op[0], op[1], AT); |
252b5132 RH |
12515 | break; |
12516 | ||
12517 | case M_TEQ_I: | |
12518 | s = "teq"; | |
12519 | goto trap; | |
12520 | case M_TGE_I: | |
12521 | s = "tge"; | |
12522 | goto trap; | |
12523 | case M_TGEU_I: | |
12524 | s = "tgeu"; | |
12525 | goto trap; | |
12526 | case M_TLT_I: | |
12527 | s = "tlt"; | |
12528 | goto trap; | |
12529 | case M_TLTU_I: | |
12530 | s = "tltu"; | |
12531 | goto trap; | |
12532 | case M_TNE_I: | |
12533 | s = "tne"; | |
12534 | trap: | |
8fc2e39e | 12535 | used_at = 1; |
bad1aba3 | 12536 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
c0ebe874 | 12537 | macro_build (NULL, s, "s,t", op[0], AT); |
252b5132 RH |
12538 | break; |
12539 | ||
252b5132 | 12540 | case M_TRUNCWS: |
43841e91 | 12541 | case M_TRUNCWD: |
df58fc94 | 12542 | gas_assert (!mips_opts.micromips); |
0aa27725 | 12543 | gas_assert (mips_opts.isa == ISA_MIPS1); |
8fc2e39e | 12544 | used_at = 1; |
252b5132 RH |
12545 | |
12546 | /* | |
12547 | * Is the double cfc1 instruction a bug in the mips assembler; | |
12548 | * or is there a reason for it? | |
12549 | */ | |
7d10b47d | 12550 | start_noreorder (); |
c0ebe874 RS |
12551 | macro_build (NULL, "cfc1", "t,G", op[2], RA); |
12552 | macro_build (NULL, "cfc1", "t,G", op[2], RA); | |
67c0d1eb | 12553 | macro_build (NULL, "nop", ""); |
252b5132 | 12554 | expr1.X_add_number = 3; |
c0ebe874 | 12555 | macro_build (&expr1, "ori", "t,r,i", AT, op[2], BFD_RELOC_LO16); |
252b5132 | 12556 | expr1.X_add_number = 2; |
67c0d1eb RS |
12557 | macro_build (&expr1, "xori", "t,r,i", AT, AT, BFD_RELOC_LO16); |
12558 | macro_build (NULL, "ctc1", "t,G", AT, RA); | |
12559 | macro_build (NULL, "nop", ""); | |
12560 | macro_build (NULL, mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S", | |
c0ebe874 RS |
12561 | op[0], op[1]); |
12562 | macro_build (NULL, "ctc1", "t,G", op[2], RA); | |
67c0d1eb | 12563 | macro_build (NULL, "nop", ""); |
7d10b47d | 12564 | end_noreorder (); |
252b5132 RH |
12565 | break; |
12566 | ||
f2ae14a1 | 12567 | case M_ULH_AB: |
252b5132 | 12568 | s = "lb"; |
df58fc94 RS |
12569 | s2 = "lbu"; |
12570 | off = 1; | |
12571 | goto uld_st; | |
f2ae14a1 | 12572 | case M_ULHU_AB: |
252b5132 | 12573 | s = "lbu"; |
df58fc94 RS |
12574 | s2 = "lbu"; |
12575 | off = 1; | |
12576 | goto uld_st; | |
f2ae14a1 | 12577 | case M_ULW_AB: |
df58fc94 RS |
12578 | s = "lwl"; |
12579 | s2 = "lwr"; | |
7f3c4072 | 12580 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 RS |
12581 | off = 3; |
12582 | goto uld_st; | |
f2ae14a1 | 12583 | case M_ULD_AB: |
252b5132 RH |
12584 | s = "ldl"; |
12585 | s2 = "ldr"; | |
7f3c4072 | 12586 | offbits = (mips_opts.micromips ? 12 : 16); |
252b5132 | 12587 | off = 7; |
df58fc94 | 12588 | goto uld_st; |
f2ae14a1 | 12589 | case M_USH_AB: |
df58fc94 RS |
12590 | s = "sb"; |
12591 | s2 = "sb"; | |
12592 | off = 1; | |
12593 | ust = 1; | |
12594 | goto uld_st; | |
f2ae14a1 | 12595 | case M_USW_AB: |
df58fc94 RS |
12596 | s = "swl"; |
12597 | s2 = "swr"; | |
7f3c4072 | 12598 | offbits = (mips_opts.micromips ? 12 : 16); |
252b5132 | 12599 | off = 3; |
df58fc94 RS |
12600 | ust = 1; |
12601 | goto uld_st; | |
f2ae14a1 | 12602 | case M_USD_AB: |
df58fc94 RS |
12603 | s = "sdl"; |
12604 | s2 = "sdr"; | |
7f3c4072 | 12605 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 RS |
12606 | off = 7; |
12607 | ust = 1; | |
12608 | ||
12609 | uld_st: | |
c0ebe874 | 12610 | breg = op[2]; |
f2ae14a1 | 12611 | large_offset = !small_offset_p (off, align, offbits); |
df58fc94 RS |
12612 | ep = &offset_expr; |
12613 | expr1.X_add_number = 0; | |
f2ae14a1 | 12614 | if (large_offset) |
df58fc94 RS |
12615 | { |
12616 | used_at = 1; | |
12617 | tempreg = AT; | |
f2ae14a1 RS |
12618 | if (small_offset_p (0, align, 16)) |
12619 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", tempreg, breg, -1, | |
12620 | offset_reloc[0], offset_reloc[1], offset_reloc[2]); | |
12621 | else | |
12622 | { | |
12623 | load_address (tempreg, ep, &used_at); | |
12624 | if (breg != 0) | |
12625 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
12626 | tempreg, tempreg, breg); | |
12627 | } | |
12628 | offset_reloc[0] = BFD_RELOC_LO16; | |
12629 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
12630 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
df58fc94 | 12631 | breg = tempreg; |
c0ebe874 | 12632 | tempreg = op[0]; |
df58fc94 RS |
12633 | ep = &expr1; |
12634 | } | |
c0ebe874 | 12635 | else if (!ust && op[0] == breg) |
8fc2e39e TS |
12636 | { |
12637 | used_at = 1; | |
12638 | tempreg = AT; | |
12639 | } | |
252b5132 | 12640 | else |
c0ebe874 | 12641 | tempreg = op[0]; |
af22f5b2 | 12642 | |
df58fc94 RS |
12643 | if (off == 1) |
12644 | goto ulh_sh; | |
252b5132 | 12645 | |
90ecf173 | 12646 | if (!target_big_endian) |
df58fc94 | 12647 | ep->X_add_number += off; |
f2ae14a1 | 12648 | if (offbits == 12) |
c8276761 | 12649 | macro_build (NULL, s, "t,~(b)", tempreg, (int) ep->X_add_number, breg); |
f2ae14a1 RS |
12650 | else |
12651 | macro_build (ep, s, "t,o(b)", tempreg, -1, | |
12652 | offset_reloc[0], offset_reloc[1], offset_reloc[2], breg); | |
df58fc94 | 12653 | |
90ecf173 | 12654 | if (!target_big_endian) |
df58fc94 | 12655 | ep->X_add_number -= off; |
252b5132 | 12656 | else |
df58fc94 | 12657 | ep->X_add_number += off; |
f2ae14a1 | 12658 | if (offbits == 12) |
df58fc94 | 12659 | macro_build (NULL, s2, "t,~(b)", |
c8276761 | 12660 | tempreg, (int) ep->X_add_number, breg); |
f2ae14a1 RS |
12661 | else |
12662 | macro_build (ep, s2, "t,o(b)", tempreg, -1, | |
12663 | offset_reloc[0], offset_reloc[1], offset_reloc[2], breg); | |
252b5132 | 12664 | |
df58fc94 | 12665 | /* If necessary, move the result in tempreg to the final destination. */ |
c0ebe874 | 12666 | if (!ust && op[0] != tempreg) |
df58fc94 RS |
12667 | { |
12668 | /* Protect second load's delay slot. */ | |
12669 | load_delay_nop (); | |
c0ebe874 | 12670 | move_register (op[0], tempreg); |
df58fc94 | 12671 | } |
8fc2e39e | 12672 | break; |
252b5132 | 12673 | |
df58fc94 | 12674 | ulh_sh: |
d6bc6245 | 12675 | used_at = 1; |
df58fc94 RS |
12676 | if (target_big_endian == ust) |
12677 | ep->X_add_number += off; | |
c0ebe874 | 12678 | tempreg = ust || large_offset ? op[0] : AT; |
f2ae14a1 RS |
12679 | macro_build (ep, s, "t,o(b)", tempreg, -1, |
12680 | offset_reloc[0], offset_reloc[1], offset_reloc[2], breg); | |
df58fc94 RS |
12681 | |
12682 | /* For halfword transfers we need a temporary register to shuffle | |
12683 | bytes. Unfortunately for M_USH_A we have none available before | |
12684 | the next store as AT holds the base address. We deal with this | |
12685 | case by clobbering TREG and then restoring it as with ULH. */ | |
c0ebe874 | 12686 | tempreg = ust == large_offset ? op[0] : AT; |
df58fc94 | 12687 | if (ust) |
c0ebe874 | 12688 | macro_build (NULL, "srl", SHFT_FMT, tempreg, op[0], 8); |
df58fc94 RS |
12689 | |
12690 | if (target_big_endian == ust) | |
12691 | ep->X_add_number -= off; | |
252b5132 | 12692 | else |
df58fc94 | 12693 | ep->X_add_number += off; |
f2ae14a1 RS |
12694 | macro_build (ep, s2, "t,o(b)", tempreg, -1, |
12695 | offset_reloc[0], offset_reloc[1], offset_reloc[2], breg); | |
252b5132 | 12696 | |
df58fc94 | 12697 | /* For M_USH_A re-retrieve the LSB. */ |
f2ae14a1 | 12698 | if (ust && large_offset) |
df58fc94 RS |
12699 | { |
12700 | if (target_big_endian) | |
12701 | ep->X_add_number += off; | |
12702 | else | |
12703 | ep->X_add_number -= off; | |
f2ae14a1 RS |
12704 | macro_build (&expr1, "lbu", "t,o(b)", AT, -1, |
12705 | offset_reloc[0], offset_reloc[1], offset_reloc[2], AT); | |
df58fc94 RS |
12706 | } |
12707 | /* For ULH and M_USH_A OR the LSB in. */ | |
f2ae14a1 | 12708 | if (!ust || large_offset) |
df58fc94 | 12709 | { |
c0ebe874 | 12710 | tempreg = !large_offset ? AT : op[0]; |
df58fc94 | 12711 | macro_build (NULL, "sll", SHFT_FMT, tempreg, tempreg, 8); |
c0ebe874 | 12712 | macro_build (NULL, "or", "d,v,t", op[0], op[0], AT); |
df58fc94 | 12713 | } |
252b5132 RH |
12714 | break; |
12715 | ||
12716 | default: | |
12717 | /* FIXME: Check if this is one of the itbl macros, since they | |
bdaaa2e1 | 12718 | are added dynamically. */ |
1661c76c | 12719 | as_bad (_("macro %s not implemented yet"), ip->insn_mo->name); |
252b5132 RH |
12720 | break; |
12721 | } | |
741fe287 | 12722 | if (!mips_opts.at && used_at) |
1661c76c | 12723 | as_bad (_("macro used $at after \".set noat\"")); |
252b5132 RH |
12724 | } |
12725 | ||
12726 | /* Implement macros in mips16 mode. */ | |
12727 | ||
12728 | static void | |
17a2f251 | 12729 | mips16_macro (struct mips_cl_insn *ip) |
252b5132 | 12730 | { |
c0ebe874 | 12731 | const struct mips_operand_array *operands; |
252b5132 | 12732 | int mask; |
c0ebe874 | 12733 | int tmp; |
252b5132 RH |
12734 | expressionS expr1; |
12735 | int dbl; | |
12736 | const char *s, *s2, *s3; | |
c0ebe874 RS |
12737 | unsigned int op[MAX_OPERANDS]; |
12738 | unsigned int i; | |
252b5132 RH |
12739 | |
12740 | mask = ip->insn_mo->mask; | |
12741 | ||
c0ebe874 RS |
12742 | operands = insn_operands (ip); |
12743 | for (i = 0; i < MAX_OPERANDS; i++) | |
12744 | if (operands->operand[i]) | |
12745 | op[i] = insn_extract_operand (ip, operands->operand[i]); | |
12746 | else | |
12747 | op[i] = -1; | |
252b5132 | 12748 | |
252b5132 RH |
12749 | expr1.X_op = O_constant; |
12750 | expr1.X_op_symbol = NULL; | |
12751 | expr1.X_add_symbol = NULL; | |
12752 | expr1.X_add_number = 1; | |
12753 | ||
12754 | dbl = 0; | |
12755 | ||
12756 | switch (mask) | |
12757 | { | |
12758 | default: | |
b37df7c4 | 12759 | abort (); |
252b5132 RH |
12760 | |
12761 | case M_DDIV_3: | |
12762 | dbl = 1; | |
12763 | case M_DIV_3: | |
12764 | s = "mflo"; | |
12765 | goto do_div3; | |
12766 | case M_DREM_3: | |
12767 | dbl = 1; | |
12768 | case M_REM_3: | |
12769 | s = "mfhi"; | |
12770 | do_div3: | |
7d10b47d | 12771 | start_noreorder (); |
c0ebe874 | 12772 | macro_build (NULL, dbl ? "ddiv" : "div", "0,x,y", op[1], op[2]); |
252b5132 | 12773 | expr1.X_add_number = 2; |
c0ebe874 | 12774 | macro_build (&expr1, "bnez", "x,p", op[2]); |
67c0d1eb | 12775 | macro_build (NULL, "break", "6", 7); |
bdaaa2e1 | 12776 | |
252b5132 RH |
12777 | /* FIXME: The normal code checks for of -1 / -0x80000000 here, |
12778 | since that causes an overflow. We should do that as well, | |
12779 | but I don't see how to do the comparisons without a temporary | |
12780 | register. */ | |
7d10b47d | 12781 | end_noreorder (); |
c0ebe874 | 12782 | macro_build (NULL, s, "x", op[0]); |
252b5132 RH |
12783 | break; |
12784 | ||
12785 | case M_DIVU_3: | |
12786 | s = "divu"; | |
12787 | s2 = "mflo"; | |
12788 | goto do_divu3; | |
12789 | case M_REMU_3: | |
12790 | s = "divu"; | |
12791 | s2 = "mfhi"; | |
12792 | goto do_divu3; | |
12793 | case M_DDIVU_3: | |
12794 | s = "ddivu"; | |
12795 | s2 = "mflo"; | |
12796 | goto do_divu3; | |
12797 | case M_DREMU_3: | |
12798 | s = "ddivu"; | |
12799 | s2 = "mfhi"; | |
12800 | do_divu3: | |
7d10b47d | 12801 | start_noreorder (); |
c0ebe874 | 12802 | macro_build (NULL, s, "0,x,y", op[1], op[2]); |
252b5132 | 12803 | expr1.X_add_number = 2; |
c0ebe874 | 12804 | macro_build (&expr1, "bnez", "x,p", op[2]); |
67c0d1eb | 12805 | macro_build (NULL, "break", "6", 7); |
7d10b47d | 12806 | end_noreorder (); |
c0ebe874 | 12807 | macro_build (NULL, s2, "x", op[0]); |
252b5132 RH |
12808 | break; |
12809 | ||
12810 | case M_DMUL: | |
12811 | dbl = 1; | |
12812 | case M_MUL: | |
c0ebe874 RS |
12813 | macro_build (NULL, dbl ? "dmultu" : "multu", "x,y", op[1], op[2]); |
12814 | macro_build (NULL, "mflo", "x", op[0]); | |
8fc2e39e | 12815 | break; |
252b5132 RH |
12816 | |
12817 | case M_DSUBU_I: | |
12818 | dbl = 1; | |
12819 | goto do_subu; | |
12820 | case M_SUBU_I: | |
12821 | do_subu: | |
252b5132 | 12822 | imm_expr.X_add_number = -imm_expr.X_add_number; |
c0ebe874 | 12823 | macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "y,x,4", op[0], op[1]); |
252b5132 RH |
12824 | break; |
12825 | ||
12826 | case M_SUBU_I_2: | |
252b5132 | 12827 | imm_expr.X_add_number = -imm_expr.X_add_number; |
c0ebe874 | 12828 | macro_build (&imm_expr, "addiu", "x,k", op[0]); |
252b5132 RH |
12829 | break; |
12830 | ||
12831 | case M_DSUBU_I_2: | |
252b5132 | 12832 | imm_expr.X_add_number = -imm_expr.X_add_number; |
c0ebe874 | 12833 | macro_build (&imm_expr, "daddiu", "y,j", op[0]); |
252b5132 RH |
12834 | break; |
12835 | ||
12836 | case M_BEQ: | |
12837 | s = "cmp"; | |
12838 | s2 = "bteqz"; | |
12839 | goto do_branch; | |
12840 | case M_BNE: | |
12841 | s = "cmp"; | |
12842 | s2 = "btnez"; | |
12843 | goto do_branch; | |
12844 | case M_BLT: | |
12845 | s = "slt"; | |
12846 | s2 = "btnez"; | |
12847 | goto do_branch; | |
12848 | case M_BLTU: | |
12849 | s = "sltu"; | |
12850 | s2 = "btnez"; | |
12851 | goto do_branch; | |
12852 | case M_BLE: | |
12853 | s = "slt"; | |
12854 | s2 = "bteqz"; | |
12855 | goto do_reverse_branch; | |
12856 | case M_BLEU: | |
12857 | s = "sltu"; | |
12858 | s2 = "bteqz"; | |
12859 | goto do_reverse_branch; | |
12860 | case M_BGE: | |
12861 | s = "slt"; | |
12862 | s2 = "bteqz"; | |
12863 | goto do_branch; | |
12864 | case M_BGEU: | |
12865 | s = "sltu"; | |
12866 | s2 = "bteqz"; | |
12867 | goto do_branch; | |
12868 | case M_BGT: | |
12869 | s = "slt"; | |
12870 | s2 = "btnez"; | |
12871 | goto do_reverse_branch; | |
12872 | case M_BGTU: | |
12873 | s = "sltu"; | |
12874 | s2 = "btnez"; | |
12875 | ||
12876 | do_reverse_branch: | |
c0ebe874 RS |
12877 | tmp = op[1]; |
12878 | op[1] = op[0]; | |
12879 | op[0] = tmp; | |
252b5132 RH |
12880 | |
12881 | do_branch: | |
c0ebe874 | 12882 | macro_build (NULL, s, "x,y", op[0], op[1]); |
67c0d1eb | 12883 | macro_build (&offset_expr, s2, "p"); |
252b5132 RH |
12884 | break; |
12885 | ||
12886 | case M_BEQ_I: | |
12887 | s = "cmpi"; | |
12888 | s2 = "bteqz"; | |
12889 | s3 = "x,U"; | |
12890 | goto do_branch_i; | |
12891 | case M_BNE_I: | |
12892 | s = "cmpi"; | |
12893 | s2 = "btnez"; | |
12894 | s3 = "x,U"; | |
12895 | goto do_branch_i; | |
12896 | case M_BLT_I: | |
12897 | s = "slti"; | |
12898 | s2 = "btnez"; | |
12899 | s3 = "x,8"; | |
12900 | goto do_branch_i; | |
12901 | case M_BLTU_I: | |
12902 | s = "sltiu"; | |
12903 | s2 = "btnez"; | |
12904 | s3 = "x,8"; | |
12905 | goto do_branch_i; | |
12906 | case M_BLE_I: | |
12907 | s = "slti"; | |
12908 | s2 = "btnez"; | |
12909 | s3 = "x,8"; | |
12910 | goto do_addone_branch_i; | |
12911 | case M_BLEU_I: | |
12912 | s = "sltiu"; | |
12913 | s2 = "btnez"; | |
12914 | s3 = "x,8"; | |
12915 | goto do_addone_branch_i; | |
12916 | case M_BGE_I: | |
12917 | s = "slti"; | |
12918 | s2 = "bteqz"; | |
12919 | s3 = "x,8"; | |
12920 | goto do_branch_i; | |
12921 | case M_BGEU_I: | |
12922 | s = "sltiu"; | |
12923 | s2 = "bteqz"; | |
12924 | s3 = "x,8"; | |
12925 | goto do_branch_i; | |
12926 | case M_BGT_I: | |
12927 | s = "slti"; | |
12928 | s2 = "bteqz"; | |
12929 | s3 = "x,8"; | |
12930 | goto do_addone_branch_i; | |
12931 | case M_BGTU_I: | |
12932 | s = "sltiu"; | |
12933 | s2 = "bteqz"; | |
12934 | s3 = "x,8"; | |
12935 | ||
12936 | do_addone_branch_i: | |
252b5132 RH |
12937 | ++imm_expr.X_add_number; |
12938 | ||
12939 | do_branch_i: | |
c0ebe874 | 12940 | macro_build (&imm_expr, s, s3, op[0]); |
67c0d1eb | 12941 | macro_build (&offset_expr, s2, "p"); |
252b5132 RH |
12942 | break; |
12943 | ||
12944 | case M_ABS: | |
12945 | expr1.X_add_number = 0; | |
c0ebe874 RS |
12946 | macro_build (&expr1, "slti", "x,8", op[1]); |
12947 | if (op[0] != op[1]) | |
12948 | macro_build (NULL, "move", "y,X", op[0], mips16_to_32_reg_map[op[1]]); | |
252b5132 | 12949 | expr1.X_add_number = 2; |
67c0d1eb | 12950 | macro_build (&expr1, "bteqz", "p"); |
c0ebe874 | 12951 | macro_build (NULL, "neg", "x,w", op[0], op[0]); |
0acfaea6 | 12952 | break; |
252b5132 RH |
12953 | } |
12954 | } | |
12955 | ||
14daeee3 RS |
12956 | /* Look up instruction [START, START + LENGTH) in HASH. Record any extra |
12957 | opcode bits in *OPCODE_EXTRA. */ | |
12958 | ||
12959 | static struct mips_opcode * | |
12960 | mips_lookup_insn (struct hash_control *hash, const char *start, | |
da8bca91 | 12961 | ssize_t length, unsigned int *opcode_extra) |
14daeee3 RS |
12962 | { |
12963 | char *name, *dot, *p; | |
12964 | unsigned int mask, suffix; | |
da8bca91 | 12965 | ssize_t opend; |
14daeee3 RS |
12966 | struct mips_opcode *insn; |
12967 | ||
12968 | /* Make a copy of the instruction so that we can fiddle with it. */ | |
12969 | name = alloca (length + 1); | |
12970 | memcpy (name, start, length); | |
12971 | name[length] = '\0'; | |
12972 | ||
12973 | /* Look up the instruction as-is. */ | |
12974 | insn = (struct mips_opcode *) hash_find (hash, name); | |
ee5734f0 | 12975 | if (insn) |
14daeee3 RS |
12976 | return insn; |
12977 | ||
12978 | dot = strchr (name, '.'); | |
12979 | if (dot && dot[1]) | |
12980 | { | |
12981 | /* Try to interpret the text after the dot as a VU0 channel suffix. */ | |
12982 | p = mips_parse_vu0_channels (dot + 1, &mask); | |
12983 | if (*p == 0 && mask != 0) | |
12984 | { | |
12985 | *dot = 0; | |
12986 | insn = (struct mips_opcode *) hash_find (hash, name); | |
12987 | *dot = '.'; | |
12988 | if (insn && (insn->pinfo2 & INSN2_VU0_CHANNEL_SUFFIX) != 0) | |
12989 | { | |
12990 | *opcode_extra |= mask << mips_vu0_channel_mask.lsb; | |
12991 | return insn; | |
12992 | } | |
12993 | } | |
12994 | } | |
12995 | ||
12996 | if (mips_opts.micromips) | |
12997 | { | |
12998 | /* See if there's an instruction size override suffix, | |
12999 | either `16' or `32', at the end of the mnemonic proper, | |
13000 | that defines the operation, i.e. before the first `.' | |
13001 | character if any. Strip it and retry. */ | |
13002 | opend = dot != NULL ? dot - name : length; | |
13003 | if (opend >= 3 && name[opend - 2] == '1' && name[opend - 1] == '6') | |
13004 | suffix = 2; | |
13005 | else if (name[opend - 2] == '3' && name[opend - 1] == '2') | |
13006 | suffix = 4; | |
13007 | else | |
13008 | suffix = 0; | |
13009 | if (suffix) | |
13010 | { | |
13011 | memcpy (name + opend - 2, name + opend, length - opend + 1); | |
13012 | insn = (struct mips_opcode *) hash_find (hash, name); | |
ee5734f0 | 13013 | if (insn) |
14daeee3 RS |
13014 | { |
13015 | forced_insn_length = suffix; | |
13016 | return insn; | |
13017 | } | |
13018 | } | |
13019 | } | |
13020 | ||
13021 | return NULL; | |
13022 | } | |
13023 | ||
77bd4346 | 13024 | /* Assemble an instruction into its binary format. If the instruction |
e423441d RS |
13025 | is a macro, set imm_expr and offset_expr to the values associated |
13026 | with "I" and "A" operands respectively. Otherwise store the value | |
13027 | of the relocatable field (if any) in offset_expr. In both cases | |
13028 | set offset_reloc to the relocation operators applied to offset_expr. */ | |
252b5132 RH |
13029 | |
13030 | static void | |
60f20e8b | 13031 | mips_ip (char *str, struct mips_cl_insn *insn) |
252b5132 | 13032 | { |
60f20e8b | 13033 | const struct mips_opcode *first, *past; |
df58fc94 | 13034 | struct hash_control *hash; |
a92713e6 | 13035 | char format; |
14daeee3 | 13036 | size_t end; |
a92713e6 | 13037 | struct mips_operand_token *tokens; |
14daeee3 | 13038 | unsigned int opcode_extra; |
252b5132 | 13039 | |
df58fc94 RS |
13040 | if (mips_opts.micromips) |
13041 | { | |
13042 | hash = micromips_op_hash; | |
13043 | past = µmips_opcodes[bfd_micromips_num_opcodes]; | |
13044 | } | |
13045 | else | |
13046 | { | |
13047 | hash = op_hash; | |
13048 | past = &mips_opcodes[NUMOPCODES]; | |
13049 | } | |
13050 | forced_insn_length = 0; | |
14daeee3 | 13051 | opcode_extra = 0; |
252b5132 | 13052 | |
df58fc94 | 13053 | /* We first try to match an instruction up to a space or to the end. */ |
a40bc9dd RS |
13054 | for (end = 0; str[end] != '\0' && !ISSPACE (str[end]); end++) |
13055 | continue; | |
bdaaa2e1 | 13056 | |
60f20e8b RS |
13057 | first = mips_lookup_insn (hash, str, end, &opcode_extra); |
13058 | if (first == NULL) | |
252b5132 | 13059 | { |
1661c76c | 13060 | set_insn_error (0, _("unrecognized opcode")); |
a40bc9dd | 13061 | return; |
252b5132 RH |
13062 | } |
13063 | ||
60f20e8b | 13064 | if (strcmp (first->name, "li.s") == 0) |
a92713e6 | 13065 | format = 'f'; |
60f20e8b | 13066 | else if (strcmp (first->name, "li.d") == 0) |
a92713e6 RS |
13067 | format = 'd'; |
13068 | else | |
13069 | format = 0; | |
13070 | tokens = mips_parse_arguments (str + end, format); | |
13071 | if (!tokens) | |
13072 | return; | |
13073 | ||
60f20e8b RS |
13074 | if (!match_insns (insn, first, past, tokens, opcode_extra, FALSE) |
13075 | && !match_insns (insn, first, past, tokens, opcode_extra, TRUE)) | |
1661c76c | 13076 | set_insn_error (0, _("invalid operands")); |
df58fc94 | 13077 | |
e3de51ce | 13078 | obstack_free (&mips_operand_tokens, tokens); |
252b5132 RH |
13079 | } |
13080 | ||
77bd4346 RS |
13081 | /* As for mips_ip, but used when assembling MIPS16 code. |
13082 | Also set forced_insn_length to the resulting instruction size in | |
13083 | bytes if the user explicitly requested a small or extended instruction. */ | |
252b5132 RH |
13084 | |
13085 | static void | |
60f20e8b | 13086 | mips16_ip (char *str, struct mips_cl_insn *insn) |
252b5132 | 13087 | { |
1a00e612 | 13088 | char *end, *s, c; |
60f20e8b | 13089 | struct mips_opcode *first; |
a92713e6 | 13090 | struct mips_operand_token *tokens; |
252b5132 | 13091 | |
df58fc94 | 13092 | forced_insn_length = 0; |
252b5132 | 13093 | |
3882b010 | 13094 | for (s = str; ISLOWER (*s); ++s) |
252b5132 | 13095 | ; |
1a00e612 RS |
13096 | end = s; |
13097 | c = *end; | |
13098 | switch (c) | |
252b5132 RH |
13099 | { |
13100 | case '\0': | |
13101 | break; | |
13102 | ||
13103 | case ' ': | |
1a00e612 | 13104 | s++; |
252b5132 RH |
13105 | break; |
13106 | ||
13107 | case '.': | |
13108 | if (s[1] == 't' && s[2] == ' ') | |
13109 | { | |
df58fc94 | 13110 | forced_insn_length = 2; |
252b5132 RH |
13111 | s += 3; |
13112 | break; | |
13113 | } | |
13114 | else if (s[1] == 'e' && s[2] == ' ') | |
13115 | { | |
df58fc94 | 13116 | forced_insn_length = 4; |
252b5132 RH |
13117 | s += 3; |
13118 | break; | |
13119 | } | |
13120 | /* Fall through. */ | |
13121 | default: | |
1661c76c | 13122 | set_insn_error (0, _("unrecognized opcode")); |
252b5132 RH |
13123 | return; |
13124 | } | |
13125 | ||
df58fc94 RS |
13126 | if (mips_opts.noautoextend && !forced_insn_length) |
13127 | forced_insn_length = 2; | |
252b5132 | 13128 | |
1a00e612 | 13129 | *end = 0; |
60f20e8b | 13130 | first = (struct mips_opcode *) hash_find (mips16_op_hash, str); |
1a00e612 RS |
13131 | *end = c; |
13132 | ||
60f20e8b | 13133 | if (!first) |
252b5132 | 13134 | { |
1661c76c | 13135 | set_insn_error (0, _("unrecognized opcode")); |
252b5132 RH |
13136 | return; |
13137 | } | |
13138 | ||
a92713e6 RS |
13139 | tokens = mips_parse_arguments (s, 0); |
13140 | if (!tokens) | |
13141 | return; | |
13142 | ||
60f20e8b | 13143 | if (!match_mips16_insns (insn, first, tokens)) |
1661c76c | 13144 | set_insn_error (0, _("invalid operands")); |
252b5132 | 13145 | |
e3de51ce | 13146 | obstack_free (&mips_operand_tokens, tokens); |
252b5132 RH |
13147 | } |
13148 | ||
b886a2ab RS |
13149 | /* Marshal immediate value VAL for an extended MIPS16 instruction. |
13150 | NBITS is the number of significant bits in VAL. */ | |
13151 | ||
13152 | static unsigned long | |
13153 | mips16_immed_extend (offsetT val, unsigned int nbits) | |
13154 | { | |
13155 | int extval; | |
13156 | if (nbits == 16) | |
13157 | { | |
13158 | extval = ((val >> 11) & 0x1f) | (val & 0x7e0); | |
13159 | val &= 0x1f; | |
13160 | } | |
13161 | else if (nbits == 15) | |
13162 | { | |
13163 | extval = ((val >> 11) & 0xf) | (val & 0x7f0); | |
13164 | val &= 0xf; | |
13165 | } | |
13166 | else | |
13167 | { | |
13168 | extval = ((val & 0x1f) << 6) | (val & 0x20); | |
13169 | val = 0; | |
13170 | } | |
13171 | return (extval << 16) | val; | |
13172 | } | |
13173 | ||
3ccad066 RS |
13174 | /* Like decode_mips16_operand, but require the operand to be defined and |
13175 | require it to be an integer. */ | |
13176 | ||
13177 | static const struct mips_int_operand * | |
13178 | mips16_immed_operand (int type, bfd_boolean extended_p) | |
13179 | { | |
13180 | const struct mips_operand *operand; | |
13181 | ||
13182 | operand = decode_mips16_operand (type, extended_p); | |
13183 | if (!operand || (operand->type != OP_INT && operand->type != OP_PCREL)) | |
13184 | abort (); | |
13185 | return (const struct mips_int_operand *) operand; | |
13186 | } | |
13187 | ||
13188 | /* Return true if SVAL fits OPERAND. RELOC is as for mips16_immed. */ | |
13189 | ||
13190 | static bfd_boolean | |
13191 | mips16_immed_in_range_p (const struct mips_int_operand *operand, | |
13192 | bfd_reloc_code_real_type reloc, offsetT sval) | |
13193 | { | |
13194 | int min_val, max_val; | |
13195 | ||
13196 | min_val = mips_int_operand_min (operand); | |
13197 | max_val = mips_int_operand_max (operand); | |
13198 | if (reloc != BFD_RELOC_UNUSED) | |
13199 | { | |
13200 | if (min_val < 0) | |
13201 | sval = SEXT_16BIT (sval); | |
13202 | else | |
13203 | sval &= 0xffff; | |
13204 | } | |
13205 | ||
13206 | return (sval >= min_val | |
13207 | && sval <= max_val | |
13208 | && (sval & ((1 << operand->shift) - 1)) == 0); | |
13209 | } | |
13210 | ||
5c04167a RS |
13211 | /* Install immediate value VAL into MIPS16 instruction *INSN, |
13212 | extending it if necessary. The instruction in *INSN may | |
13213 | already be extended. | |
13214 | ||
43c0598f RS |
13215 | RELOC is the relocation that produced VAL, or BFD_RELOC_UNUSED |
13216 | if none. In the former case, VAL is a 16-bit number with no | |
13217 | defined signedness. | |
13218 | ||
13219 | TYPE is the type of the immediate field. USER_INSN_LENGTH | |
13220 | is the length that the user requested, or 0 if none. */ | |
252b5132 RH |
13221 | |
13222 | static void | |
43c0598f RS |
13223 | mips16_immed (char *file, unsigned int line, int type, |
13224 | bfd_reloc_code_real_type reloc, offsetT val, | |
5c04167a | 13225 | unsigned int user_insn_length, unsigned long *insn) |
252b5132 | 13226 | { |
3ccad066 RS |
13227 | const struct mips_int_operand *operand; |
13228 | unsigned int uval, length; | |
252b5132 | 13229 | |
3ccad066 RS |
13230 | operand = mips16_immed_operand (type, FALSE); |
13231 | if (!mips16_immed_in_range_p (operand, reloc, val)) | |
5c04167a RS |
13232 | { |
13233 | /* We need an extended instruction. */ | |
13234 | if (user_insn_length == 2) | |
13235 | as_bad_where (file, line, _("invalid unextended operand value")); | |
13236 | else | |
13237 | *insn |= MIPS16_EXTEND; | |
13238 | } | |
13239 | else if (user_insn_length == 4) | |
13240 | { | |
13241 | /* The operand doesn't force an unextended instruction to be extended. | |
13242 | Warn if the user wanted an extended instruction anyway. */ | |
13243 | *insn |= MIPS16_EXTEND; | |
13244 | as_warn_where (file, line, | |
13245 | _("extended operand requested but not required")); | |
13246 | } | |
252b5132 | 13247 | |
3ccad066 RS |
13248 | length = mips16_opcode_length (*insn); |
13249 | if (length == 4) | |
252b5132 | 13250 | { |
3ccad066 RS |
13251 | operand = mips16_immed_operand (type, TRUE); |
13252 | if (!mips16_immed_in_range_p (operand, reloc, val)) | |
13253 | as_bad_where (file, line, | |
13254 | _("operand value out of range for instruction")); | |
252b5132 | 13255 | } |
3ccad066 RS |
13256 | uval = ((unsigned int) val >> operand->shift) - operand->bias; |
13257 | if (length == 2) | |
13258 | *insn = mips_insert_operand (&operand->root, *insn, uval); | |
252b5132 | 13259 | else |
3ccad066 | 13260 | *insn |= mips16_immed_extend (uval, operand->root.size); |
252b5132 RH |
13261 | } |
13262 | \f | |
d6f16593 | 13263 | struct percent_op_match |
ad8d3bb3 | 13264 | { |
5e0116d5 RS |
13265 | const char *str; |
13266 | bfd_reloc_code_real_type reloc; | |
d6f16593 MR |
13267 | }; |
13268 | ||
13269 | static const struct percent_op_match mips_percent_op[] = | |
ad8d3bb3 | 13270 | { |
5e0116d5 | 13271 | {"%lo", BFD_RELOC_LO16}, |
5e0116d5 RS |
13272 | {"%call_hi", BFD_RELOC_MIPS_CALL_HI16}, |
13273 | {"%call_lo", BFD_RELOC_MIPS_CALL_LO16}, | |
13274 | {"%call16", BFD_RELOC_MIPS_CALL16}, | |
13275 | {"%got_disp", BFD_RELOC_MIPS_GOT_DISP}, | |
13276 | {"%got_page", BFD_RELOC_MIPS_GOT_PAGE}, | |
13277 | {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST}, | |
13278 | {"%got_hi", BFD_RELOC_MIPS_GOT_HI16}, | |
13279 | {"%got_lo", BFD_RELOC_MIPS_GOT_LO16}, | |
13280 | {"%got", BFD_RELOC_MIPS_GOT16}, | |
13281 | {"%gp_rel", BFD_RELOC_GPREL16}, | |
13282 | {"%half", BFD_RELOC_16}, | |
13283 | {"%highest", BFD_RELOC_MIPS_HIGHEST}, | |
13284 | {"%higher", BFD_RELOC_MIPS_HIGHER}, | |
13285 | {"%neg", BFD_RELOC_MIPS_SUB}, | |
3f98094e DJ |
13286 | {"%tlsgd", BFD_RELOC_MIPS_TLS_GD}, |
13287 | {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM}, | |
13288 | {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16}, | |
13289 | {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16}, | |
13290 | {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16}, | |
13291 | {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16}, | |
13292 | {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL}, | |
5e0116d5 | 13293 | {"%hi", BFD_RELOC_HI16_S} |
ad8d3bb3 TS |
13294 | }; |
13295 | ||
d6f16593 MR |
13296 | static const struct percent_op_match mips16_percent_op[] = |
13297 | { | |
13298 | {"%lo", BFD_RELOC_MIPS16_LO16}, | |
13299 | {"%gprel", BFD_RELOC_MIPS16_GPREL}, | |
738e5348 RS |
13300 | {"%got", BFD_RELOC_MIPS16_GOT16}, |
13301 | {"%call16", BFD_RELOC_MIPS16_CALL16}, | |
d0f13682 CLT |
13302 | {"%hi", BFD_RELOC_MIPS16_HI16_S}, |
13303 | {"%tlsgd", BFD_RELOC_MIPS16_TLS_GD}, | |
13304 | {"%tlsldm", BFD_RELOC_MIPS16_TLS_LDM}, | |
13305 | {"%dtprel_hi", BFD_RELOC_MIPS16_TLS_DTPREL_HI16}, | |
13306 | {"%dtprel_lo", BFD_RELOC_MIPS16_TLS_DTPREL_LO16}, | |
13307 | {"%tprel_hi", BFD_RELOC_MIPS16_TLS_TPREL_HI16}, | |
13308 | {"%tprel_lo", BFD_RELOC_MIPS16_TLS_TPREL_LO16}, | |
13309 | {"%gottprel", BFD_RELOC_MIPS16_TLS_GOTTPREL} | |
d6f16593 MR |
13310 | }; |
13311 | ||
252b5132 | 13312 | |
5e0116d5 RS |
13313 | /* Return true if *STR points to a relocation operator. When returning true, |
13314 | move *STR over the operator and store its relocation code in *RELOC. | |
13315 | Leave both *STR and *RELOC alone when returning false. */ | |
13316 | ||
13317 | static bfd_boolean | |
17a2f251 | 13318 | parse_relocation (char **str, bfd_reloc_code_real_type *reloc) |
252b5132 | 13319 | { |
d6f16593 MR |
13320 | const struct percent_op_match *percent_op; |
13321 | size_t limit, i; | |
13322 | ||
13323 | if (mips_opts.mips16) | |
13324 | { | |
13325 | percent_op = mips16_percent_op; | |
13326 | limit = ARRAY_SIZE (mips16_percent_op); | |
13327 | } | |
13328 | else | |
13329 | { | |
13330 | percent_op = mips_percent_op; | |
13331 | limit = ARRAY_SIZE (mips_percent_op); | |
13332 | } | |
76b3015f | 13333 | |
d6f16593 | 13334 | for (i = 0; i < limit; i++) |
5e0116d5 | 13335 | if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0) |
394f9b3a | 13336 | { |
3f98094e DJ |
13337 | int len = strlen (percent_op[i].str); |
13338 | ||
13339 | if (!ISSPACE ((*str)[len]) && (*str)[len] != '(') | |
13340 | continue; | |
13341 | ||
5e0116d5 RS |
13342 | *str += strlen (percent_op[i].str); |
13343 | *reloc = percent_op[i].reloc; | |
394f9b3a | 13344 | |
5e0116d5 RS |
13345 | /* Check whether the output BFD supports this relocation. |
13346 | If not, issue an error and fall back on something safe. */ | |
13347 | if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc)) | |
394f9b3a | 13348 | { |
20203fb9 | 13349 | as_bad (_("relocation %s isn't supported by the current ABI"), |
5e0116d5 | 13350 | percent_op[i].str); |
01a3f561 | 13351 | *reloc = BFD_RELOC_UNUSED; |
394f9b3a | 13352 | } |
5e0116d5 | 13353 | return TRUE; |
394f9b3a | 13354 | } |
5e0116d5 | 13355 | return FALSE; |
394f9b3a | 13356 | } |
ad8d3bb3 | 13357 | |
ad8d3bb3 | 13358 | |
5e0116d5 RS |
13359 | /* Parse string STR as a 16-bit relocatable operand. Store the |
13360 | expression in *EP and the relocations in the array starting | |
13361 | at RELOC. Return the number of relocation operators used. | |
ad8d3bb3 | 13362 | |
01a3f561 | 13363 | On exit, EXPR_END points to the first character after the expression. */ |
ad8d3bb3 | 13364 | |
5e0116d5 | 13365 | static size_t |
17a2f251 TS |
13366 | my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc, |
13367 | char *str) | |
ad8d3bb3 | 13368 | { |
5e0116d5 RS |
13369 | bfd_reloc_code_real_type reversed_reloc[3]; |
13370 | size_t reloc_index, i; | |
09b8f35a RS |
13371 | int crux_depth, str_depth; |
13372 | char *crux; | |
5e0116d5 RS |
13373 | |
13374 | /* Search for the start of the main expression, recoding relocations | |
09b8f35a RS |
13375 | in REVERSED_RELOC. End the loop with CRUX pointing to the start |
13376 | of the main expression and with CRUX_DEPTH containing the number | |
13377 | of open brackets at that point. */ | |
13378 | reloc_index = -1; | |
13379 | str_depth = 0; | |
13380 | do | |
fb1b3232 | 13381 | { |
09b8f35a RS |
13382 | reloc_index++; |
13383 | crux = str; | |
13384 | crux_depth = str_depth; | |
13385 | ||
13386 | /* Skip over whitespace and brackets, keeping count of the number | |
13387 | of brackets. */ | |
13388 | while (*str == ' ' || *str == '\t' || *str == '(') | |
13389 | if (*str++ == '(') | |
13390 | str_depth++; | |
5e0116d5 | 13391 | } |
09b8f35a RS |
13392 | while (*str == '%' |
13393 | && reloc_index < (HAVE_NEWABI ? 3 : 1) | |
13394 | && parse_relocation (&str, &reversed_reloc[reloc_index])); | |
ad8d3bb3 | 13395 | |
09b8f35a | 13396 | my_getExpression (ep, crux); |
5e0116d5 | 13397 | str = expr_end; |
394f9b3a | 13398 | |
5e0116d5 | 13399 | /* Match every open bracket. */ |
09b8f35a | 13400 | while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t')) |
5e0116d5 | 13401 | if (*str++ == ')') |
09b8f35a | 13402 | crux_depth--; |
394f9b3a | 13403 | |
09b8f35a | 13404 | if (crux_depth > 0) |
20203fb9 | 13405 | as_bad (_("unclosed '('")); |
394f9b3a | 13406 | |
5e0116d5 | 13407 | expr_end = str; |
252b5132 | 13408 | |
01a3f561 | 13409 | if (reloc_index != 0) |
64bdfcaf RS |
13410 | { |
13411 | prev_reloc_op_frag = frag_now; | |
13412 | for (i = 0; i < reloc_index; i++) | |
13413 | reloc[i] = reversed_reloc[reloc_index - 1 - i]; | |
13414 | } | |
fb1b3232 | 13415 | |
5e0116d5 | 13416 | return reloc_index; |
252b5132 RH |
13417 | } |
13418 | ||
13419 | static void | |
17a2f251 | 13420 | my_getExpression (expressionS *ep, char *str) |
252b5132 RH |
13421 | { |
13422 | char *save_in; | |
13423 | ||
13424 | save_in = input_line_pointer; | |
13425 | input_line_pointer = str; | |
13426 | expression (ep); | |
13427 | expr_end = input_line_pointer; | |
13428 | input_line_pointer = save_in; | |
252b5132 RH |
13429 | } |
13430 | ||
252b5132 | 13431 | char * |
17a2f251 | 13432 | md_atof (int type, char *litP, int *sizeP) |
252b5132 | 13433 | { |
499ac353 | 13434 | return ieee_md_atof (type, litP, sizeP, target_big_endian); |
252b5132 RH |
13435 | } |
13436 | ||
13437 | void | |
17a2f251 | 13438 | md_number_to_chars (char *buf, valueT val, int n) |
252b5132 RH |
13439 | { |
13440 | if (target_big_endian) | |
13441 | number_to_chars_bigendian (buf, val, n); | |
13442 | else | |
13443 | number_to_chars_littleendian (buf, val, n); | |
13444 | } | |
13445 | \f | |
e013f690 TS |
13446 | static int support_64bit_objects(void) |
13447 | { | |
13448 | const char **list, **l; | |
aa3d8fdf | 13449 | int yes; |
e013f690 TS |
13450 | |
13451 | list = bfd_target_list (); | |
13452 | for (l = list; *l != NULL; l++) | |
aeffff67 RS |
13453 | if (strcmp (*l, ELF_TARGET ("elf64-", "big")) == 0 |
13454 | || strcmp (*l, ELF_TARGET ("elf64-", "little")) == 0) | |
e013f690 | 13455 | break; |
aa3d8fdf | 13456 | yes = (*l != NULL); |
e013f690 | 13457 | free (list); |
aa3d8fdf | 13458 | return yes; |
e013f690 TS |
13459 | } |
13460 | ||
316f5878 RS |
13461 | /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to |
13462 | NEW_VALUE. Warn if another value was already specified. Note: | |
13463 | we have to defer parsing the -march and -mtune arguments in order | |
13464 | to handle 'from-abi' correctly, since the ABI might be specified | |
13465 | in a later argument. */ | |
13466 | ||
13467 | static void | |
17a2f251 | 13468 | mips_set_option_string (const char **string_ptr, const char *new_value) |
316f5878 RS |
13469 | { |
13470 | if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0) | |
1661c76c | 13471 | as_warn (_("a different %s was already specified, is now %s"), |
316f5878 RS |
13472 | string_ptr == &mips_arch_string ? "-march" : "-mtune", |
13473 | new_value); | |
13474 | ||
13475 | *string_ptr = new_value; | |
13476 | } | |
13477 | ||
252b5132 | 13478 | int |
17a2f251 | 13479 | md_parse_option (int c, char *arg) |
252b5132 | 13480 | { |
c6278170 RS |
13481 | unsigned int i; |
13482 | ||
13483 | for (i = 0; i < ARRAY_SIZE (mips_ases); i++) | |
13484 | if (c == mips_ases[i].option_on || c == mips_ases[i].option_off) | |
13485 | { | |
13486 | file_ase_explicit |= mips_set_ase (&mips_ases[i], | |
13487 | c == mips_ases[i].option_on); | |
13488 | return 1; | |
13489 | } | |
13490 | ||
252b5132 RH |
13491 | switch (c) |
13492 | { | |
119d663a NC |
13493 | case OPTION_CONSTRUCT_FLOATS: |
13494 | mips_disable_float_construction = 0; | |
13495 | break; | |
bdaaa2e1 | 13496 | |
119d663a NC |
13497 | case OPTION_NO_CONSTRUCT_FLOATS: |
13498 | mips_disable_float_construction = 1; | |
13499 | break; | |
bdaaa2e1 | 13500 | |
252b5132 RH |
13501 | case OPTION_TRAP: |
13502 | mips_trap = 1; | |
13503 | break; | |
13504 | ||
13505 | case OPTION_BREAK: | |
13506 | mips_trap = 0; | |
13507 | break; | |
13508 | ||
13509 | case OPTION_EB: | |
13510 | target_big_endian = 1; | |
13511 | break; | |
13512 | ||
13513 | case OPTION_EL: | |
13514 | target_big_endian = 0; | |
13515 | break; | |
13516 | ||
13517 | case 'O': | |
4ffff32f TS |
13518 | if (arg == NULL) |
13519 | mips_optimize = 1; | |
13520 | else if (arg[0] == '0') | |
13521 | mips_optimize = 0; | |
13522 | else if (arg[0] == '1') | |
252b5132 RH |
13523 | mips_optimize = 1; |
13524 | else | |
13525 | mips_optimize = 2; | |
13526 | break; | |
13527 | ||
13528 | case 'g': | |
13529 | if (arg == NULL) | |
13530 | mips_debug = 2; | |
13531 | else | |
13532 | mips_debug = atoi (arg); | |
252b5132 RH |
13533 | break; |
13534 | ||
13535 | case OPTION_MIPS1: | |
0b35dfee | 13536 | file_mips_opts.isa = ISA_MIPS1; |
252b5132 RH |
13537 | break; |
13538 | ||
13539 | case OPTION_MIPS2: | |
0b35dfee | 13540 | file_mips_opts.isa = ISA_MIPS2; |
252b5132 RH |
13541 | break; |
13542 | ||
13543 | case OPTION_MIPS3: | |
0b35dfee | 13544 | file_mips_opts.isa = ISA_MIPS3; |
252b5132 RH |
13545 | break; |
13546 | ||
13547 | case OPTION_MIPS4: | |
0b35dfee | 13548 | file_mips_opts.isa = ISA_MIPS4; |
e7af610e NC |
13549 | break; |
13550 | ||
84ea6cf2 | 13551 | case OPTION_MIPS5: |
0b35dfee | 13552 | file_mips_opts.isa = ISA_MIPS5; |
84ea6cf2 NC |
13553 | break; |
13554 | ||
e7af610e | 13555 | case OPTION_MIPS32: |
0b35dfee | 13556 | file_mips_opts.isa = ISA_MIPS32; |
252b5132 RH |
13557 | break; |
13558 | ||
af7ee8bf | 13559 | case OPTION_MIPS32R2: |
0b35dfee | 13560 | file_mips_opts.isa = ISA_MIPS32R2; |
af7ee8bf CD |
13561 | break; |
13562 | ||
ae52f483 | 13563 | case OPTION_MIPS32R3: |
0ae19f05 | 13564 | file_mips_opts.isa = ISA_MIPS32R3; |
ae52f483 AB |
13565 | break; |
13566 | ||
13567 | case OPTION_MIPS32R5: | |
0ae19f05 | 13568 | file_mips_opts.isa = ISA_MIPS32R5; |
ae52f483 AB |
13569 | break; |
13570 | ||
5f74bc13 | 13571 | case OPTION_MIPS64R2: |
0b35dfee | 13572 | file_mips_opts.isa = ISA_MIPS64R2; |
5f74bc13 CD |
13573 | break; |
13574 | ||
ae52f483 | 13575 | case OPTION_MIPS64R3: |
0ae19f05 | 13576 | file_mips_opts.isa = ISA_MIPS64R3; |
ae52f483 AB |
13577 | break; |
13578 | ||
13579 | case OPTION_MIPS64R5: | |
0ae19f05 | 13580 | file_mips_opts.isa = ISA_MIPS64R5; |
ae52f483 AB |
13581 | break; |
13582 | ||
84ea6cf2 | 13583 | case OPTION_MIPS64: |
0b35dfee | 13584 | file_mips_opts.isa = ISA_MIPS64; |
84ea6cf2 NC |
13585 | break; |
13586 | ||
ec68c924 | 13587 | case OPTION_MTUNE: |
316f5878 RS |
13588 | mips_set_option_string (&mips_tune_string, arg); |
13589 | break; | |
ec68c924 | 13590 | |
316f5878 RS |
13591 | case OPTION_MARCH: |
13592 | mips_set_option_string (&mips_arch_string, arg); | |
252b5132 RH |
13593 | break; |
13594 | ||
13595 | case OPTION_M4650: | |
316f5878 RS |
13596 | mips_set_option_string (&mips_arch_string, "4650"); |
13597 | mips_set_option_string (&mips_tune_string, "4650"); | |
252b5132 RH |
13598 | break; |
13599 | ||
13600 | case OPTION_NO_M4650: | |
13601 | break; | |
13602 | ||
13603 | case OPTION_M4010: | |
316f5878 RS |
13604 | mips_set_option_string (&mips_arch_string, "4010"); |
13605 | mips_set_option_string (&mips_tune_string, "4010"); | |
252b5132 RH |
13606 | break; |
13607 | ||
13608 | case OPTION_NO_M4010: | |
13609 | break; | |
13610 | ||
13611 | case OPTION_M4100: | |
316f5878 RS |
13612 | mips_set_option_string (&mips_arch_string, "4100"); |
13613 | mips_set_option_string (&mips_tune_string, "4100"); | |
252b5132 RH |
13614 | break; |
13615 | ||
13616 | case OPTION_NO_M4100: | |
13617 | break; | |
13618 | ||
252b5132 | 13619 | case OPTION_M3900: |
316f5878 RS |
13620 | mips_set_option_string (&mips_arch_string, "3900"); |
13621 | mips_set_option_string (&mips_tune_string, "3900"); | |
252b5132 | 13622 | break; |
bdaaa2e1 | 13623 | |
252b5132 RH |
13624 | case OPTION_NO_M3900: |
13625 | break; | |
13626 | ||
df58fc94 RS |
13627 | case OPTION_MICROMIPS: |
13628 | if (mips_opts.mips16 == 1) | |
13629 | { | |
13630 | as_bad (_("-mmicromips cannot be used with -mips16")); | |
13631 | return 0; | |
13632 | } | |
13633 | mips_opts.micromips = 1; | |
13634 | mips_no_prev_insn (); | |
13635 | break; | |
13636 | ||
13637 | case OPTION_NO_MICROMIPS: | |
13638 | mips_opts.micromips = 0; | |
13639 | mips_no_prev_insn (); | |
13640 | break; | |
13641 | ||
252b5132 | 13642 | case OPTION_MIPS16: |
df58fc94 RS |
13643 | if (mips_opts.micromips == 1) |
13644 | { | |
13645 | as_bad (_("-mips16 cannot be used with -micromips")); | |
13646 | return 0; | |
13647 | } | |
252b5132 | 13648 | mips_opts.mips16 = 1; |
7d10b47d | 13649 | mips_no_prev_insn (); |
252b5132 RH |
13650 | break; |
13651 | ||
13652 | case OPTION_NO_MIPS16: | |
13653 | mips_opts.mips16 = 0; | |
7d10b47d | 13654 | mips_no_prev_insn (); |
252b5132 RH |
13655 | break; |
13656 | ||
6a32d874 CM |
13657 | case OPTION_FIX_24K: |
13658 | mips_fix_24k = 1; | |
13659 | break; | |
13660 | ||
13661 | case OPTION_NO_FIX_24K: | |
13662 | mips_fix_24k = 0; | |
13663 | break; | |
13664 | ||
a8d14a88 CM |
13665 | case OPTION_FIX_RM7000: |
13666 | mips_fix_rm7000 = 1; | |
13667 | break; | |
13668 | ||
13669 | case OPTION_NO_FIX_RM7000: | |
13670 | mips_fix_rm7000 = 0; | |
13671 | break; | |
13672 | ||
c67a084a NC |
13673 | case OPTION_FIX_LOONGSON2F_JUMP: |
13674 | mips_fix_loongson2f_jump = TRUE; | |
13675 | break; | |
13676 | ||
13677 | case OPTION_NO_FIX_LOONGSON2F_JUMP: | |
13678 | mips_fix_loongson2f_jump = FALSE; | |
13679 | break; | |
13680 | ||
13681 | case OPTION_FIX_LOONGSON2F_NOP: | |
13682 | mips_fix_loongson2f_nop = TRUE; | |
13683 | break; | |
13684 | ||
13685 | case OPTION_NO_FIX_LOONGSON2F_NOP: | |
13686 | mips_fix_loongson2f_nop = FALSE; | |
13687 | break; | |
13688 | ||
d766e8ec RS |
13689 | case OPTION_FIX_VR4120: |
13690 | mips_fix_vr4120 = 1; | |
60b63b72 RS |
13691 | break; |
13692 | ||
d766e8ec RS |
13693 | case OPTION_NO_FIX_VR4120: |
13694 | mips_fix_vr4120 = 0; | |
60b63b72 RS |
13695 | break; |
13696 | ||
7d8e00cf RS |
13697 | case OPTION_FIX_VR4130: |
13698 | mips_fix_vr4130 = 1; | |
13699 | break; | |
13700 | ||
13701 | case OPTION_NO_FIX_VR4130: | |
13702 | mips_fix_vr4130 = 0; | |
13703 | break; | |
13704 | ||
d954098f DD |
13705 | case OPTION_FIX_CN63XXP1: |
13706 | mips_fix_cn63xxp1 = TRUE; | |
13707 | break; | |
13708 | ||
13709 | case OPTION_NO_FIX_CN63XXP1: | |
13710 | mips_fix_cn63xxp1 = FALSE; | |
13711 | break; | |
13712 | ||
4a6a3df4 AO |
13713 | case OPTION_RELAX_BRANCH: |
13714 | mips_relax_branch = 1; | |
13715 | break; | |
13716 | ||
13717 | case OPTION_NO_RELAX_BRANCH: | |
13718 | mips_relax_branch = 0; | |
13719 | break; | |
13720 | ||
833794fc MR |
13721 | case OPTION_INSN32: |
13722 | mips_opts.insn32 = TRUE; | |
13723 | break; | |
13724 | ||
13725 | case OPTION_NO_INSN32: | |
13726 | mips_opts.insn32 = FALSE; | |
13727 | break; | |
13728 | ||
aa6975fb ILT |
13729 | case OPTION_MSHARED: |
13730 | mips_in_shared = TRUE; | |
13731 | break; | |
13732 | ||
13733 | case OPTION_MNO_SHARED: | |
13734 | mips_in_shared = FALSE; | |
13735 | break; | |
13736 | ||
aed1a261 RS |
13737 | case OPTION_MSYM32: |
13738 | mips_opts.sym32 = TRUE; | |
13739 | break; | |
13740 | ||
13741 | case OPTION_MNO_SYM32: | |
13742 | mips_opts.sym32 = FALSE; | |
13743 | break; | |
13744 | ||
252b5132 RH |
13745 | /* When generating ELF code, we permit -KPIC and -call_shared to |
13746 | select SVR4_PIC, and -non_shared to select no PIC. This is | |
13747 | intended to be compatible with Irix 5. */ | |
13748 | case OPTION_CALL_SHARED: | |
252b5132 | 13749 | mips_pic = SVR4_PIC; |
143d77c5 | 13750 | mips_abicalls = TRUE; |
252b5132 RH |
13751 | break; |
13752 | ||
861fb55a | 13753 | case OPTION_CALL_NONPIC: |
861fb55a DJ |
13754 | mips_pic = NO_PIC; |
13755 | mips_abicalls = TRUE; | |
13756 | break; | |
13757 | ||
252b5132 | 13758 | case OPTION_NON_SHARED: |
252b5132 | 13759 | mips_pic = NO_PIC; |
143d77c5 | 13760 | mips_abicalls = FALSE; |
252b5132 RH |
13761 | break; |
13762 | ||
44075ae2 TS |
13763 | /* The -xgot option tells the assembler to use 32 bit offsets |
13764 | when accessing the got in SVR4_PIC mode. It is for Irix | |
252b5132 RH |
13765 | compatibility. */ |
13766 | case OPTION_XGOT: | |
13767 | mips_big_got = 1; | |
13768 | break; | |
13769 | ||
13770 | case 'G': | |
6caf9ef4 TS |
13771 | g_switch_value = atoi (arg); |
13772 | g_switch_seen = 1; | |
252b5132 RH |
13773 | break; |
13774 | ||
34ba82a8 TS |
13775 | /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32 |
13776 | and -mabi=64. */ | |
252b5132 | 13777 | case OPTION_32: |
f3ded42a | 13778 | mips_abi = O32_ABI; |
252b5132 RH |
13779 | break; |
13780 | ||
e013f690 | 13781 | case OPTION_N32: |
316f5878 | 13782 | mips_abi = N32_ABI; |
e013f690 | 13783 | break; |
252b5132 | 13784 | |
e013f690 | 13785 | case OPTION_64: |
316f5878 | 13786 | mips_abi = N64_ABI; |
f43abd2b | 13787 | if (!support_64bit_objects()) |
1661c76c | 13788 | as_fatal (_("no compiled in support for 64 bit object file format")); |
252b5132 RH |
13789 | break; |
13790 | ||
c97ef257 | 13791 | case OPTION_GP32: |
bad1aba3 | 13792 | file_mips_opts.gp = 32; |
c97ef257 AH |
13793 | break; |
13794 | ||
13795 | case OPTION_GP64: | |
bad1aba3 | 13796 | file_mips_opts.gp = 64; |
c97ef257 | 13797 | break; |
252b5132 | 13798 | |
ca4e0257 | 13799 | case OPTION_FP32: |
0b35dfee | 13800 | file_mips_opts.fp = 32; |
316f5878 RS |
13801 | break; |
13802 | ||
13803 | case OPTION_FP64: | |
0b35dfee | 13804 | file_mips_opts.fp = 64; |
ca4e0257 RS |
13805 | break; |
13806 | ||
037b32b9 | 13807 | case OPTION_SINGLE_FLOAT: |
0b35dfee | 13808 | file_mips_opts.single_float = 1; |
037b32b9 AN |
13809 | break; |
13810 | ||
13811 | case OPTION_DOUBLE_FLOAT: | |
0b35dfee | 13812 | file_mips_opts.single_float = 0; |
037b32b9 AN |
13813 | break; |
13814 | ||
13815 | case OPTION_SOFT_FLOAT: | |
0b35dfee | 13816 | file_mips_opts.soft_float = 1; |
037b32b9 AN |
13817 | break; |
13818 | ||
13819 | case OPTION_HARD_FLOAT: | |
0b35dfee | 13820 | file_mips_opts.soft_float = 0; |
037b32b9 AN |
13821 | break; |
13822 | ||
252b5132 | 13823 | case OPTION_MABI: |
e013f690 | 13824 | if (strcmp (arg, "32") == 0) |
316f5878 | 13825 | mips_abi = O32_ABI; |
e013f690 | 13826 | else if (strcmp (arg, "o64") == 0) |
316f5878 | 13827 | mips_abi = O64_ABI; |
e013f690 | 13828 | else if (strcmp (arg, "n32") == 0) |
316f5878 | 13829 | mips_abi = N32_ABI; |
e013f690 TS |
13830 | else if (strcmp (arg, "64") == 0) |
13831 | { | |
316f5878 | 13832 | mips_abi = N64_ABI; |
e013f690 | 13833 | if (! support_64bit_objects()) |
1661c76c | 13834 | as_fatal (_("no compiled in support for 64 bit object file " |
e013f690 TS |
13835 | "format")); |
13836 | } | |
13837 | else if (strcmp (arg, "eabi") == 0) | |
316f5878 | 13838 | mips_abi = EABI_ABI; |
e013f690 | 13839 | else |
da0e507f TS |
13840 | { |
13841 | as_fatal (_("invalid abi -mabi=%s"), arg); | |
13842 | return 0; | |
13843 | } | |
252b5132 RH |
13844 | break; |
13845 | ||
6b76fefe | 13846 | case OPTION_M7000_HILO_FIX: |
b34976b6 | 13847 | mips_7000_hilo_fix = TRUE; |
6b76fefe CM |
13848 | break; |
13849 | ||
9ee72ff1 | 13850 | case OPTION_MNO_7000_HILO_FIX: |
b34976b6 | 13851 | mips_7000_hilo_fix = FALSE; |
6b76fefe CM |
13852 | break; |
13853 | ||
ecb4347a | 13854 | case OPTION_MDEBUG: |
b34976b6 | 13855 | mips_flag_mdebug = TRUE; |
ecb4347a DJ |
13856 | break; |
13857 | ||
13858 | case OPTION_NO_MDEBUG: | |
b34976b6 | 13859 | mips_flag_mdebug = FALSE; |
ecb4347a | 13860 | break; |
dcd410fe RO |
13861 | |
13862 | case OPTION_PDR: | |
13863 | mips_flag_pdr = TRUE; | |
13864 | break; | |
13865 | ||
13866 | case OPTION_NO_PDR: | |
13867 | mips_flag_pdr = FALSE; | |
13868 | break; | |
0a44bf69 RS |
13869 | |
13870 | case OPTION_MVXWORKS_PIC: | |
13871 | mips_pic = VXWORKS_PIC; | |
13872 | break; | |
ecb4347a | 13873 | |
ba92f887 MR |
13874 | case OPTION_NAN: |
13875 | if (strcmp (arg, "2008") == 0) | |
13876 | mips_flag_nan2008 = TRUE; | |
13877 | else if (strcmp (arg, "legacy") == 0) | |
13878 | mips_flag_nan2008 = FALSE; | |
13879 | else | |
13880 | { | |
1661c76c | 13881 | as_fatal (_("invalid NaN setting -mnan=%s"), arg); |
ba92f887 MR |
13882 | return 0; |
13883 | } | |
13884 | break; | |
13885 | ||
252b5132 RH |
13886 | default: |
13887 | return 0; | |
13888 | } | |
13889 | ||
c67a084a NC |
13890 | mips_fix_loongson2f = mips_fix_loongson2f_nop || mips_fix_loongson2f_jump; |
13891 | ||
252b5132 RH |
13892 | return 1; |
13893 | } | |
316f5878 RS |
13894 | \f |
13895 | /* Set up globals to generate code for the ISA or processor | |
13896 | described by INFO. */ | |
252b5132 | 13897 | |
252b5132 | 13898 | static void |
17a2f251 | 13899 | mips_set_architecture (const struct mips_cpu_info *info) |
252b5132 | 13900 | { |
316f5878 | 13901 | if (info != 0) |
252b5132 | 13902 | { |
0b35dfee | 13903 | file_mips_opts.arch = info->cpu; |
fef14a42 | 13904 | mips_opts.arch = info->cpu; |
316f5878 | 13905 | mips_opts.isa = info->isa; |
252b5132 | 13906 | } |
252b5132 RH |
13907 | } |
13908 | ||
252b5132 | 13909 | |
316f5878 | 13910 | /* Likewise for tuning. */ |
252b5132 | 13911 | |
316f5878 | 13912 | static void |
17a2f251 | 13913 | mips_set_tune (const struct mips_cpu_info *info) |
316f5878 RS |
13914 | { |
13915 | if (info != 0) | |
fef14a42 | 13916 | mips_tune = info->cpu; |
316f5878 | 13917 | } |
80cc45a5 | 13918 | |
34ba82a8 | 13919 | |
252b5132 | 13920 | void |
17a2f251 | 13921 | mips_after_parse_args (void) |
e9670677 | 13922 | { |
fef14a42 TS |
13923 | const struct mips_cpu_info *arch_info = 0; |
13924 | const struct mips_cpu_info *tune_info = 0; | |
13925 | ||
e9670677 | 13926 | /* GP relative stuff not working for PE */ |
6caf9ef4 | 13927 | if (strncmp (TARGET_OS, "pe", 2) == 0) |
e9670677 | 13928 | { |
6caf9ef4 | 13929 | if (g_switch_seen && g_switch_value != 0) |
1661c76c | 13930 | as_bad (_("-G not supported in this configuration")); |
e9670677 MR |
13931 | g_switch_value = 0; |
13932 | } | |
13933 | ||
cac012d6 AO |
13934 | if (mips_abi == NO_ABI) |
13935 | mips_abi = MIPS_DEFAULT_ABI; | |
13936 | ||
22923709 RS |
13937 | /* The following code determines the architecture and register size. |
13938 | Similar code was added to GCC 3.3 (see override_options() in | |
13939 | config/mips/mips.c). The GAS and GCC code should be kept in sync | |
13940 | as much as possible. */ | |
e9670677 | 13941 | |
316f5878 | 13942 | if (mips_arch_string != 0) |
fef14a42 | 13943 | arch_info = mips_parse_cpu ("-march", mips_arch_string); |
e9670677 | 13944 | |
0b35dfee | 13945 | if (file_mips_opts.isa != ISA_UNKNOWN) |
e9670677 | 13946 | { |
0b35dfee | 13947 | /* Handle -mipsN. At this point, file_mips_opts.isa contains the |
fef14a42 | 13948 | ISA level specified by -mipsN, while arch_info->isa contains |
316f5878 | 13949 | the -march selection (if any). */ |
fef14a42 | 13950 | if (arch_info != 0) |
e9670677 | 13951 | { |
316f5878 RS |
13952 | /* -march takes precedence over -mipsN, since it is more descriptive. |
13953 | There's no harm in specifying both as long as the ISA levels | |
13954 | are the same. */ | |
0b35dfee | 13955 | if (file_mips_opts.isa != arch_info->isa) |
1661c76c RS |
13956 | as_bad (_("-%s conflicts with the other architecture options," |
13957 | " which imply -%s"), | |
0b35dfee | 13958 | mips_cpu_info_from_isa (file_mips_opts.isa)->name, |
fef14a42 | 13959 | mips_cpu_info_from_isa (arch_info->isa)->name); |
e9670677 | 13960 | } |
316f5878 | 13961 | else |
0b35dfee | 13962 | arch_info = mips_cpu_info_from_isa (file_mips_opts.isa); |
e9670677 MR |
13963 | } |
13964 | ||
fef14a42 | 13965 | if (arch_info == 0) |
95bfe26e MF |
13966 | { |
13967 | arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT); | |
13968 | gas_assert (arch_info); | |
13969 | } | |
e9670677 | 13970 | |
fef14a42 | 13971 | if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa)) |
20203fb9 | 13972 | as_bad (_("-march=%s is not compatible with the selected ABI"), |
fef14a42 TS |
13973 | arch_info->name); |
13974 | ||
13975 | mips_set_architecture (arch_info); | |
13976 | ||
0b35dfee | 13977 | /* Optimize for file_mips_opts.arch, unless -mtune selects a different |
13978 | processor. */ | |
fef14a42 TS |
13979 | if (mips_tune_string != 0) |
13980 | tune_info = mips_parse_cpu ("-mtune", mips_tune_string); | |
e9670677 | 13981 | |
fef14a42 TS |
13982 | if (tune_info == 0) |
13983 | mips_set_tune (arch_info); | |
13984 | else | |
13985 | mips_set_tune (tune_info); | |
e9670677 | 13986 | |
bad1aba3 | 13987 | if (file_mips_opts.gp >= 0) |
e9670677 | 13988 | { |
316f5878 RS |
13989 | /* The user specified the size of the integer registers. Make sure |
13990 | it agrees with the ABI and ISA. */ | |
bad1aba3 | 13991 | if (file_mips_opts.gp == 64 && !ISA_HAS_64BIT_REGS (mips_opts.isa)) |
316f5878 | 13992 | as_bad (_("-mgp64 used with a 32-bit processor")); |
bad1aba3 | 13993 | else if (file_mips_opts.gp == 32 && ABI_NEEDS_64BIT_REGS (mips_abi)) |
316f5878 | 13994 | as_bad (_("-mgp32 used with a 64-bit ABI")); |
bad1aba3 | 13995 | else if (file_mips_opts.gp == 64 && ABI_NEEDS_32BIT_REGS (mips_abi)) |
316f5878 | 13996 | as_bad (_("-mgp64 used with a 32-bit ABI")); |
e9670677 MR |
13997 | } |
13998 | else | |
13999 | { | |
316f5878 RS |
14000 | /* Infer the integer register size from the ABI and processor. |
14001 | Restrict ourselves to 32-bit registers if that's all the | |
14002 | processor has, or if the ABI cannot handle 64-bit registers. */ | |
bad1aba3 | 14003 | file_mips_opts.gp = (ABI_NEEDS_32BIT_REGS (mips_abi) |
14004 | || !ISA_HAS_64BIT_REGS (mips_opts.isa)) | |
14005 | ? 32 : 64; | |
e9670677 MR |
14006 | } |
14007 | ||
0b35dfee | 14008 | switch (file_mips_opts.fp) |
ad3fea08 TS |
14009 | { |
14010 | default: | |
14011 | case -1: | |
14012 | /* No user specified float register size. | |
14013 | ??? GAS treats single-float processors as though they had 64-bit | |
14014 | float registers (although it complains when double-precision | |
14015 | instructions are used). As things stand, saying they have 32-bit | |
14016 | registers would lead to spurious "register must be even" messages. | |
14017 | So here we assume float registers are never smaller than the | |
14018 | integer ones. */ | |
bad1aba3 | 14019 | if (file_mips_opts.gp == 64) |
ad3fea08 | 14020 | /* 64-bit integer registers implies 64-bit float registers. */ |
0b35dfee | 14021 | file_mips_opts.fp = 64; |
c6278170 | 14022 | else if ((mips_opts.ase & FP64_ASES) |
ad3fea08 TS |
14023 | && ISA_HAS_64BIT_FPRS (mips_opts.isa)) |
14024 | /* -mips3d and -mdmx imply 64-bit float registers, if possible. */ | |
0b35dfee | 14025 | file_mips_opts.fp = 64; |
ad3fea08 TS |
14026 | else |
14027 | /* 32-bit float registers. */ | |
0b35dfee | 14028 | file_mips_opts.fp = 32; |
ad3fea08 TS |
14029 | break; |
14030 | ||
14031 | /* The user specified the size of the float registers. Check if it | |
14032 | agrees with the ABI and ISA. */ | |
0b35dfee | 14033 | case 64: |
ad3fea08 TS |
14034 | if (!ISA_HAS_64BIT_FPRS (mips_opts.isa)) |
14035 | as_bad (_("-mfp64 used with a 32-bit fpu")); | |
14036 | else if (ABI_NEEDS_32BIT_REGS (mips_abi) | |
14037 | && !ISA_HAS_MXHC1 (mips_opts.isa)) | |
14038 | as_warn (_("-mfp64 used with a 32-bit ABI")); | |
14039 | break; | |
0b35dfee | 14040 | case 32: |
ad3fea08 TS |
14041 | if (ABI_NEEDS_64BIT_REGS (mips_abi)) |
14042 | as_warn (_("-mfp32 used with a 64-bit ABI")); | |
14043 | break; | |
14044 | } | |
e9670677 | 14045 | |
316f5878 | 14046 | /* End of GCC-shared inference code. */ |
e9670677 | 14047 | |
17a2f251 TS |
14048 | /* This flag is set when we have a 64-bit capable CPU but use only |
14049 | 32-bit wide registers. Note that EABI does not use it. */ | |
14050 | if (ISA_HAS_64BIT_REGS (mips_opts.isa) | |
bad1aba3 | 14051 | && ((mips_abi == NO_ABI && file_mips_opts.gp == 32) |
17a2f251 | 14052 | || mips_abi == O32_ABI)) |
316f5878 | 14053 | mips_32bitmode = 1; |
e9670677 MR |
14054 | |
14055 | if (mips_opts.isa == ISA_MIPS1 && mips_trap) | |
14056 | as_bad (_("trap exception not supported at ISA 1")); | |
14057 | ||
e9670677 MR |
14058 | /* If the selected architecture includes support for ASEs, enable |
14059 | generation of code for them. */ | |
a4672219 | 14060 | if (mips_opts.mips16 == -1) |
0b35dfee | 14061 | mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_opts.arch)) ? 1 : 0; |
df58fc94 | 14062 | if (mips_opts.micromips == -1) |
0b35dfee | 14063 | mips_opts.micromips = (CPU_HAS_MICROMIPS (file_mips_opts.arch)) |
14064 | ? 1 : 0; | |
846ef2d0 RS |
14065 | |
14066 | /* MIPS3D and MDMX require 64-bit FPRs, so -mfp32 should stop those | |
14067 | ASEs from being selected implicitly. */ | |
0b35dfee | 14068 | if (file_mips_opts.fp != 64) |
846ef2d0 RS |
14069 | file_ase_explicit |= ASE_MIPS3D | ASE_MDMX; |
14070 | ||
14071 | /* If the user didn't explicitly select or deselect a particular ASE, | |
14072 | use the default setting for the CPU. */ | |
14073 | mips_opts.ase |= (arch_info->ase & ~file_ase_explicit); | |
14074 | ||
0b35dfee | 14075 | file_mips_opts.isa = mips_opts.isa; |
14076 | file_mips_opts.ase = mips_opts.ase; | |
bad1aba3 | 14077 | mips_opts.gp = file_mips_opts.gp; |
0b35dfee | 14078 | mips_opts.fp = file_mips_opts.fp; |
14079 | mips_opts.soft_float = file_mips_opts.soft_float; | |
14080 | mips_opts.single_float = file_mips_opts.single_float; | |
e9670677 | 14081 | |
c6278170 RS |
14082 | mips_check_isa_supports_ases (); |
14083 | ||
ecb4347a | 14084 | if (mips_flag_mdebug < 0) |
e8044f35 | 14085 | mips_flag_mdebug = 0; |
e9670677 MR |
14086 | } |
14087 | \f | |
14088 | void | |
17a2f251 | 14089 | mips_init_after_args (void) |
252b5132 RH |
14090 | { |
14091 | /* initialize opcodes */ | |
14092 | bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes; | |
beae10d5 | 14093 | mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes; |
252b5132 RH |
14094 | } |
14095 | ||
14096 | long | |
17a2f251 | 14097 | md_pcrel_from (fixS *fixP) |
252b5132 | 14098 | { |
a7ebbfdf TS |
14099 | valueT addr = fixP->fx_where + fixP->fx_frag->fr_address; |
14100 | switch (fixP->fx_r_type) | |
14101 | { | |
df58fc94 RS |
14102 | case BFD_RELOC_MICROMIPS_7_PCREL_S1: |
14103 | case BFD_RELOC_MICROMIPS_10_PCREL_S1: | |
14104 | /* Return the address of the delay slot. */ | |
14105 | return addr + 2; | |
14106 | ||
14107 | case BFD_RELOC_MICROMIPS_16_PCREL_S1: | |
14108 | case BFD_RELOC_MICROMIPS_JMP: | |
a7ebbfdf TS |
14109 | case BFD_RELOC_16_PCREL_S2: |
14110 | case BFD_RELOC_MIPS_JMP: | |
14111 | /* Return the address of the delay slot. */ | |
14112 | return addr + 4; | |
df58fc94 | 14113 | |
a7ebbfdf TS |
14114 | default: |
14115 | return addr; | |
14116 | } | |
252b5132 RH |
14117 | } |
14118 | ||
252b5132 RH |
14119 | /* This is called before the symbol table is processed. In order to |
14120 | work with gcc when using mips-tfile, we must keep all local labels. | |
14121 | However, in other cases, we want to discard them. If we were | |
14122 | called with -g, but we didn't see any debugging information, it may | |
14123 | mean that gcc is smuggling debugging information through to | |
14124 | mips-tfile, in which case we must generate all local labels. */ | |
14125 | ||
14126 | void | |
17a2f251 | 14127 | mips_frob_file_before_adjust (void) |
252b5132 RH |
14128 | { |
14129 | #ifndef NO_ECOFF_DEBUGGING | |
14130 | if (ECOFF_DEBUGGING | |
14131 | && mips_debug != 0 | |
14132 | && ! ecoff_debugging_seen) | |
14133 | flag_keep_locals = 1; | |
14134 | #endif | |
14135 | } | |
14136 | ||
3b91255e | 14137 | /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede |
55cf6793 | 14138 | the corresponding LO16 reloc. This is called before md_apply_fix and |
3b91255e RS |
14139 | tc_gen_reloc. Unmatched relocs can only be generated by use of explicit |
14140 | relocation operators. | |
14141 | ||
14142 | For our purposes, a %lo() expression matches a %got() or %hi() | |
14143 | expression if: | |
14144 | ||
14145 | (a) it refers to the same symbol; and | |
14146 | (b) the offset applied in the %lo() expression is no lower than | |
14147 | the offset applied in the %got() or %hi(). | |
14148 | ||
14149 | (b) allows us to cope with code like: | |
14150 | ||
14151 | lui $4,%hi(foo) | |
14152 | lh $4,%lo(foo+2)($4) | |
14153 | ||
14154 | ...which is legal on RELA targets, and has a well-defined behaviour | |
14155 | if the user knows that adding 2 to "foo" will not induce a carry to | |
14156 | the high 16 bits. | |
14157 | ||
14158 | When several %lo()s match a particular %got() or %hi(), we use the | |
14159 | following rules to distinguish them: | |
14160 | ||
14161 | (1) %lo()s with smaller offsets are a better match than %lo()s with | |
14162 | higher offsets. | |
14163 | ||
14164 | (2) %lo()s with no matching %got() or %hi() are better than those | |
14165 | that already have a matching %got() or %hi(). | |
14166 | ||
14167 | (3) later %lo()s are better than earlier %lo()s. | |
14168 | ||
14169 | These rules are applied in order. | |
14170 | ||
14171 | (1) means, among other things, that %lo()s with identical offsets are | |
14172 | chosen if they exist. | |
14173 | ||
14174 | (2) means that we won't associate several high-part relocations with | |
14175 | the same low-part relocation unless there's no alternative. Having | |
14176 | several high parts for the same low part is a GNU extension; this rule | |
14177 | allows careful users to avoid it. | |
14178 | ||
14179 | (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order, | |
14180 | with the last high-part relocation being at the front of the list. | |
14181 | It therefore makes sense to choose the last matching low-part | |
14182 | relocation, all other things being equal. It's also easier | |
14183 | to code that way. */ | |
252b5132 RH |
14184 | |
14185 | void | |
17a2f251 | 14186 | mips_frob_file (void) |
252b5132 RH |
14187 | { |
14188 | struct mips_hi_fixup *l; | |
35903be0 | 14189 | bfd_reloc_code_real_type looking_for_rtype = BFD_RELOC_UNUSED; |
252b5132 RH |
14190 | |
14191 | for (l = mips_hi_fixup_list; l != NULL; l = l->next) | |
14192 | { | |
14193 | segment_info_type *seginfo; | |
3b91255e RS |
14194 | bfd_boolean matched_lo_p; |
14195 | fixS **hi_pos, **lo_pos, **pos; | |
252b5132 | 14196 | |
9c2799c2 | 14197 | gas_assert (reloc_needs_lo_p (l->fixp->fx_r_type)); |
252b5132 | 14198 | |
5919d012 | 14199 | /* If a GOT16 relocation turns out to be against a global symbol, |
b886a2ab RS |
14200 | there isn't supposed to be a matching LO. Ignore %gots against |
14201 | constants; we'll report an error for those later. */ | |
738e5348 | 14202 | if (got16_reloc_p (l->fixp->fx_r_type) |
b886a2ab RS |
14203 | && !(l->fixp->fx_addsy |
14204 | && pic_need_relax (l->fixp->fx_addsy, l->seg))) | |
5919d012 RS |
14205 | continue; |
14206 | ||
14207 | /* Check quickly whether the next fixup happens to be a matching %lo. */ | |
14208 | if (fixup_has_matching_lo_p (l->fixp)) | |
252b5132 RH |
14209 | continue; |
14210 | ||
252b5132 | 14211 | seginfo = seg_info (l->seg); |
252b5132 | 14212 | |
3b91255e RS |
14213 | /* Set HI_POS to the position of this relocation in the chain. |
14214 | Set LO_POS to the position of the chosen low-part relocation. | |
14215 | MATCHED_LO_P is true on entry to the loop if *POS is a low-part | |
14216 | relocation that matches an immediately-preceding high-part | |
14217 | relocation. */ | |
14218 | hi_pos = NULL; | |
14219 | lo_pos = NULL; | |
14220 | matched_lo_p = FALSE; | |
738e5348 | 14221 | looking_for_rtype = matching_lo_reloc (l->fixp->fx_r_type); |
35903be0 | 14222 | |
3b91255e RS |
14223 | for (pos = &seginfo->fix_root; *pos != NULL; pos = &(*pos)->fx_next) |
14224 | { | |
14225 | if (*pos == l->fixp) | |
14226 | hi_pos = pos; | |
14227 | ||
35903be0 | 14228 | if ((*pos)->fx_r_type == looking_for_rtype |
30cfc97a | 14229 | && symbol_same_p ((*pos)->fx_addsy, l->fixp->fx_addsy) |
3b91255e RS |
14230 | && (*pos)->fx_offset >= l->fixp->fx_offset |
14231 | && (lo_pos == NULL | |
14232 | || (*pos)->fx_offset < (*lo_pos)->fx_offset | |
14233 | || (!matched_lo_p | |
14234 | && (*pos)->fx_offset == (*lo_pos)->fx_offset))) | |
14235 | lo_pos = pos; | |
14236 | ||
14237 | matched_lo_p = (reloc_needs_lo_p ((*pos)->fx_r_type) | |
14238 | && fixup_has_matching_lo_p (*pos)); | |
14239 | } | |
14240 | ||
14241 | /* If we found a match, remove the high-part relocation from its | |
14242 | current position and insert it before the low-part relocation. | |
14243 | Make the offsets match so that fixup_has_matching_lo_p() | |
14244 | will return true. | |
14245 | ||
14246 | We don't warn about unmatched high-part relocations since some | |
14247 | versions of gcc have been known to emit dead "lui ...%hi(...)" | |
14248 | instructions. */ | |
14249 | if (lo_pos != NULL) | |
14250 | { | |
14251 | l->fixp->fx_offset = (*lo_pos)->fx_offset; | |
14252 | if (l->fixp->fx_next != *lo_pos) | |
252b5132 | 14253 | { |
3b91255e RS |
14254 | *hi_pos = l->fixp->fx_next; |
14255 | l->fixp->fx_next = *lo_pos; | |
14256 | *lo_pos = l->fixp; | |
252b5132 | 14257 | } |
252b5132 RH |
14258 | } |
14259 | } | |
14260 | } | |
14261 | ||
252b5132 | 14262 | int |
17a2f251 | 14263 | mips_force_relocation (fixS *fixp) |
252b5132 | 14264 | { |
ae6063d4 | 14265 | if (generic_force_reloc (fixp)) |
252b5132 RH |
14266 | return 1; |
14267 | ||
df58fc94 RS |
14268 | /* We want to keep BFD_RELOC_MICROMIPS_*_PCREL_S1 relocation, |
14269 | so that the linker relaxation can update targets. */ | |
14270 | if (fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1 | |
14271 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1 | |
14272 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1) | |
14273 | return 1; | |
14274 | ||
3e722fb5 | 14275 | return 0; |
252b5132 RH |
14276 | } |
14277 | ||
b886a2ab RS |
14278 | /* Read the instruction associated with RELOC from BUF. */ |
14279 | ||
14280 | static unsigned int | |
14281 | read_reloc_insn (char *buf, bfd_reloc_code_real_type reloc) | |
14282 | { | |
14283 | if (mips16_reloc_p (reloc) || micromips_reloc_p (reloc)) | |
14284 | return read_compressed_insn (buf, 4); | |
14285 | else | |
14286 | return read_insn (buf); | |
14287 | } | |
14288 | ||
14289 | /* Write instruction INSN to BUF, given that it has been relocated | |
14290 | by RELOC. */ | |
14291 | ||
14292 | static void | |
14293 | write_reloc_insn (char *buf, bfd_reloc_code_real_type reloc, | |
14294 | unsigned long insn) | |
14295 | { | |
14296 | if (mips16_reloc_p (reloc) || micromips_reloc_p (reloc)) | |
14297 | write_compressed_insn (buf, insn, 4); | |
14298 | else | |
14299 | write_insn (buf, insn); | |
14300 | } | |
14301 | ||
252b5132 RH |
14302 | /* Apply a fixup to the object file. */ |
14303 | ||
94f592af | 14304 | void |
55cf6793 | 14305 | md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) |
252b5132 | 14306 | { |
4d68580a | 14307 | char *buf; |
b886a2ab | 14308 | unsigned long insn; |
a7ebbfdf | 14309 | reloc_howto_type *howto; |
252b5132 | 14310 | |
d56a8dda RS |
14311 | if (fixP->fx_pcrel) |
14312 | switch (fixP->fx_r_type) | |
14313 | { | |
14314 | case BFD_RELOC_16_PCREL_S2: | |
14315 | case BFD_RELOC_MICROMIPS_7_PCREL_S1: | |
14316 | case BFD_RELOC_MICROMIPS_10_PCREL_S1: | |
14317 | case BFD_RELOC_MICROMIPS_16_PCREL_S1: | |
14318 | case BFD_RELOC_32_PCREL: | |
14319 | break; | |
14320 | ||
14321 | case BFD_RELOC_32: | |
14322 | fixP->fx_r_type = BFD_RELOC_32_PCREL; | |
14323 | break; | |
14324 | ||
14325 | default: | |
14326 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
14327 | _("PC-relative reference to a different section")); | |
14328 | break; | |
14329 | } | |
14330 | ||
14331 | /* Handle BFD_RELOC_8, since it's easy. Punt on other bfd relocations | |
14332 | that have no MIPS ELF equivalent. */ | |
14333 | if (fixP->fx_r_type != BFD_RELOC_8) | |
14334 | { | |
14335 | howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type); | |
14336 | if (!howto) | |
14337 | return; | |
14338 | } | |
65551fa4 | 14339 | |
df58fc94 RS |
14340 | gas_assert (fixP->fx_size == 2 |
14341 | || fixP->fx_size == 4 | |
d56a8dda | 14342 | || fixP->fx_r_type == BFD_RELOC_8 |
90ecf173 MR |
14343 | || fixP->fx_r_type == BFD_RELOC_16 |
14344 | || fixP->fx_r_type == BFD_RELOC_64 | |
14345 | || fixP->fx_r_type == BFD_RELOC_CTOR | |
14346 | || fixP->fx_r_type == BFD_RELOC_MIPS_SUB | |
df58fc94 | 14347 | || fixP->fx_r_type == BFD_RELOC_MICROMIPS_SUB |
90ecf173 MR |
14348 | || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
14349 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY | |
14350 | || fixP->fx_r_type == BFD_RELOC_MIPS_TLS_DTPREL64); | |
252b5132 | 14351 | |
4d68580a | 14352 | buf = fixP->fx_frag->fr_literal + fixP->fx_where; |
252b5132 | 14353 | |
b1dca8ee RS |
14354 | /* Don't treat parts of a composite relocation as done. There are two |
14355 | reasons for this: | |
14356 | ||
14357 | (1) The second and third parts will be against 0 (RSS_UNDEF) but | |
14358 | should nevertheless be emitted if the first part is. | |
14359 | ||
14360 | (2) In normal usage, composite relocations are never assembly-time | |
14361 | constants. The easiest way of dealing with the pathological | |
14362 | exceptions is to generate a relocation against STN_UNDEF and | |
14363 | leave everything up to the linker. */ | |
3994f87e | 14364 | if (fixP->fx_addsy == NULL && !fixP->fx_pcrel && fixP->fx_tcbit == 0) |
252b5132 RH |
14365 | fixP->fx_done = 1; |
14366 | ||
14367 | switch (fixP->fx_r_type) | |
14368 | { | |
3f98094e DJ |
14369 | case BFD_RELOC_MIPS_TLS_GD: |
14370 | case BFD_RELOC_MIPS_TLS_LDM: | |
741d6ea8 JM |
14371 | case BFD_RELOC_MIPS_TLS_DTPREL32: |
14372 | case BFD_RELOC_MIPS_TLS_DTPREL64: | |
3f98094e DJ |
14373 | case BFD_RELOC_MIPS_TLS_DTPREL_HI16: |
14374 | case BFD_RELOC_MIPS_TLS_DTPREL_LO16: | |
14375 | case BFD_RELOC_MIPS_TLS_GOTTPREL: | |
d0f13682 CLT |
14376 | case BFD_RELOC_MIPS_TLS_TPREL32: |
14377 | case BFD_RELOC_MIPS_TLS_TPREL64: | |
3f98094e DJ |
14378 | case BFD_RELOC_MIPS_TLS_TPREL_HI16: |
14379 | case BFD_RELOC_MIPS_TLS_TPREL_LO16: | |
df58fc94 RS |
14380 | case BFD_RELOC_MICROMIPS_TLS_GD: |
14381 | case BFD_RELOC_MICROMIPS_TLS_LDM: | |
14382 | case BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16: | |
14383 | case BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16: | |
14384 | case BFD_RELOC_MICROMIPS_TLS_GOTTPREL: | |
14385 | case BFD_RELOC_MICROMIPS_TLS_TPREL_HI16: | |
14386 | case BFD_RELOC_MICROMIPS_TLS_TPREL_LO16: | |
d0f13682 CLT |
14387 | case BFD_RELOC_MIPS16_TLS_GD: |
14388 | case BFD_RELOC_MIPS16_TLS_LDM: | |
14389 | case BFD_RELOC_MIPS16_TLS_DTPREL_HI16: | |
14390 | case BFD_RELOC_MIPS16_TLS_DTPREL_LO16: | |
14391 | case BFD_RELOC_MIPS16_TLS_GOTTPREL: | |
14392 | case BFD_RELOC_MIPS16_TLS_TPREL_HI16: | |
14393 | case BFD_RELOC_MIPS16_TLS_TPREL_LO16: | |
b886a2ab RS |
14394 | if (!fixP->fx_addsy) |
14395 | { | |
14396 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
14397 | _("TLS relocation against a constant")); | |
14398 | break; | |
14399 | } | |
3f98094e DJ |
14400 | S_SET_THREAD_LOCAL (fixP->fx_addsy); |
14401 | /* fall through */ | |
14402 | ||
252b5132 | 14403 | case BFD_RELOC_MIPS_JMP: |
e369bcce TS |
14404 | case BFD_RELOC_MIPS_SHIFT5: |
14405 | case BFD_RELOC_MIPS_SHIFT6: | |
14406 | case BFD_RELOC_MIPS_GOT_DISP: | |
14407 | case BFD_RELOC_MIPS_GOT_PAGE: | |
14408 | case BFD_RELOC_MIPS_GOT_OFST: | |
14409 | case BFD_RELOC_MIPS_SUB: | |
14410 | case BFD_RELOC_MIPS_INSERT_A: | |
14411 | case BFD_RELOC_MIPS_INSERT_B: | |
14412 | case BFD_RELOC_MIPS_DELETE: | |
14413 | case BFD_RELOC_MIPS_HIGHEST: | |
14414 | case BFD_RELOC_MIPS_HIGHER: | |
14415 | case BFD_RELOC_MIPS_SCN_DISP: | |
14416 | case BFD_RELOC_MIPS_REL16: | |
14417 | case BFD_RELOC_MIPS_RELGOT: | |
14418 | case BFD_RELOC_MIPS_JALR: | |
252b5132 RH |
14419 | case BFD_RELOC_HI16: |
14420 | case BFD_RELOC_HI16_S: | |
b886a2ab | 14421 | case BFD_RELOC_LO16: |
cdf6fd85 | 14422 | case BFD_RELOC_GPREL16: |
252b5132 RH |
14423 | case BFD_RELOC_MIPS_LITERAL: |
14424 | case BFD_RELOC_MIPS_CALL16: | |
14425 | case BFD_RELOC_MIPS_GOT16: | |
cdf6fd85 | 14426 | case BFD_RELOC_GPREL32: |
252b5132 RH |
14427 | case BFD_RELOC_MIPS_GOT_HI16: |
14428 | case BFD_RELOC_MIPS_GOT_LO16: | |
14429 | case BFD_RELOC_MIPS_CALL_HI16: | |
14430 | case BFD_RELOC_MIPS_CALL_LO16: | |
14431 | case BFD_RELOC_MIPS16_GPREL: | |
738e5348 RS |
14432 | case BFD_RELOC_MIPS16_GOT16: |
14433 | case BFD_RELOC_MIPS16_CALL16: | |
d6f16593 MR |
14434 | case BFD_RELOC_MIPS16_HI16: |
14435 | case BFD_RELOC_MIPS16_HI16_S: | |
b886a2ab | 14436 | case BFD_RELOC_MIPS16_LO16: |
252b5132 | 14437 | case BFD_RELOC_MIPS16_JMP: |
df58fc94 RS |
14438 | case BFD_RELOC_MICROMIPS_JMP: |
14439 | case BFD_RELOC_MICROMIPS_GOT_DISP: | |
14440 | case BFD_RELOC_MICROMIPS_GOT_PAGE: | |
14441 | case BFD_RELOC_MICROMIPS_GOT_OFST: | |
14442 | case BFD_RELOC_MICROMIPS_SUB: | |
14443 | case BFD_RELOC_MICROMIPS_HIGHEST: | |
14444 | case BFD_RELOC_MICROMIPS_HIGHER: | |
14445 | case BFD_RELOC_MICROMIPS_SCN_DISP: | |
14446 | case BFD_RELOC_MICROMIPS_JALR: | |
14447 | case BFD_RELOC_MICROMIPS_HI16: | |
14448 | case BFD_RELOC_MICROMIPS_HI16_S: | |
b886a2ab | 14449 | case BFD_RELOC_MICROMIPS_LO16: |
df58fc94 RS |
14450 | case BFD_RELOC_MICROMIPS_GPREL16: |
14451 | case BFD_RELOC_MICROMIPS_LITERAL: | |
14452 | case BFD_RELOC_MICROMIPS_CALL16: | |
14453 | case BFD_RELOC_MICROMIPS_GOT16: | |
14454 | case BFD_RELOC_MICROMIPS_GOT_HI16: | |
14455 | case BFD_RELOC_MICROMIPS_GOT_LO16: | |
14456 | case BFD_RELOC_MICROMIPS_CALL_HI16: | |
14457 | case BFD_RELOC_MICROMIPS_CALL_LO16: | |
067ec077 | 14458 | case BFD_RELOC_MIPS_EH: |
b886a2ab RS |
14459 | if (fixP->fx_done) |
14460 | { | |
14461 | offsetT value; | |
14462 | ||
14463 | if (calculate_reloc (fixP->fx_r_type, *valP, &value)) | |
14464 | { | |
14465 | insn = read_reloc_insn (buf, fixP->fx_r_type); | |
14466 | if (mips16_reloc_p (fixP->fx_r_type)) | |
14467 | insn |= mips16_immed_extend (value, 16); | |
14468 | else | |
14469 | insn |= (value & 0xffff); | |
14470 | write_reloc_insn (buf, fixP->fx_r_type, insn); | |
14471 | } | |
14472 | else | |
14473 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
1661c76c | 14474 | _("unsupported constant in relocation")); |
b886a2ab | 14475 | } |
252b5132 RH |
14476 | break; |
14477 | ||
252b5132 RH |
14478 | case BFD_RELOC_64: |
14479 | /* This is handled like BFD_RELOC_32, but we output a sign | |
14480 | extended value if we are only 32 bits. */ | |
3e722fb5 | 14481 | if (fixP->fx_done) |
252b5132 RH |
14482 | { |
14483 | if (8 <= sizeof (valueT)) | |
4d68580a | 14484 | md_number_to_chars (buf, *valP, 8); |
252b5132 RH |
14485 | else |
14486 | { | |
a7ebbfdf | 14487 | valueT hiv; |
252b5132 | 14488 | |
a7ebbfdf | 14489 | if ((*valP & 0x80000000) != 0) |
252b5132 RH |
14490 | hiv = 0xffffffff; |
14491 | else | |
14492 | hiv = 0; | |
4d68580a RS |
14493 | md_number_to_chars (buf + (target_big_endian ? 4 : 0), *valP, 4); |
14494 | md_number_to_chars (buf + (target_big_endian ? 0 : 4), hiv, 4); | |
252b5132 RH |
14495 | } |
14496 | } | |
14497 | break; | |
14498 | ||
056350c6 | 14499 | case BFD_RELOC_RVA: |
252b5132 | 14500 | case BFD_RELOC_32: |
b47468a6 | 14501 | case BFD_RELOC_32_PCREL: |
252b5132 | 14502 | case BFD_RELOC_16: |
d56a8dda | 14503 | case BFD_RELOC_8: |
252b5132 | 14504 | /* If we are deleting this reloc entry, we must fill in the |
54f4ddb3 TS |
14505 | value now. This can happen if we have a .word which is not |
14506 | resolved when it appears but is later defined. */ | |
252b5132 | 14507 | if (fixP->fx_done) |
4d68580a | 14508 | md_number_to_chars (buf, *valP, fixP->fx_size); |
252b5132 RH |
14509 | break; |
14510 | ||
252b5132 | 14511 | case BFD_RELOC_16_PCREL_S2: |
a7ebbfdf | 14512 | if ((*valP & 0x3) != 0) |
cb56d3d3 | 14513 | as_bad_where (fixP->fx_file, fixP->fx_line, |
1661c76c | 14514 | _("branch to misaligned address (%lx)"), (long) *valP); |
cb56d3d3 | 14515 | |
54f4ddb3 TS |
14516 | /* We need to save the bits in the instruction since fixup_segment() |
14517 | might be deleting the relocation entry (i.e., a branch within | |
14518 | the current segment). */ | |
a7ebbfdf | 14519 | if (! fixP->fx_done) |
bb2d6cd7 | 14520 | break; |
252b5132 | 14521 | |
54f4ddb3 | 14522 | /* Update old instruction data. */ |
4d68580a | 14523 | insn = read_insn (buf); |
252b5132 | 14524 | |
a7ebbfdf TS |
14525 | if (*valP + 0x20000 <= 0x3ffff) |
14526 | { | |
14527 | insn |= (*valP >> 2) & 0xffff; | |
4d68580a | 14528 | write_insn (buf, insn); |
a7ebbfdf TS |
14529 | } |
14530 | else if (mips_pic == NO_PIC | |
14531 | && fixP->fx_done | |
14532 | && fixP->fx_frag->fr_address >= text_section->vma | |
14533 | && (fixP->fx_frag->fr_address | |
587aac4e | 14534 | < text_section->vma + bfd_get_section_size (text_section)) |
a7ebbfdf TS |
14535 | && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */ |
14536 | || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */ | |
14537 | || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */ | |
252b5132 RH |
14538 | { |
14539 | /* The branch offset is too large. If this is an | |
14540 | unconditional branch, and we are not generating PIC code, | |
14541 | we can convert it to an absolute jump instruction. */ | |
a7ebbfdf TS |
14542 | if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */ |
14543 | insn = 0x0c000000; /* jal */ | |
252b5132 | 14544 | else |
a7ebbfdf TS |
14545 | insn = 0x08000000; /* j */ |
14546 | fixP->fx_r_type = BFD_RELOC_MIPS_JMP; | |
14547 | fixP->fx_done = 0; | |
14548 | fixP->fx_addsy = section_symbol (text_section); | |
14549 | *valP += md_pcrel_from (fixP); | |
4d68580a | 14550 | write_insn (buf, insn); |
a7ebbfdf TS |
14551 | } |
14552 | else | |
14553 | { | |
14554 | /* If we got here, we have branch-relaxation disabled, | |
14555 | and there's nothing we can do to fix this instruction | |
14556 | without turning it into a longer sequence. */ | |
14557 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
1661c76c | 14558 | _("branch out of range")); |
252b5132 | 14559 | } |
252b5132 RH |
14560 | break; |
14561 | ||
df58fc94 RS |
14562 | case BFD_RELOC_MICROMIPS_7_PCREL_S1: |
14563 | case BFD_RELOC_MICROMIPS_10_PCREL_S1: | |
14564 | case BFD_RELOC_MICROMIPS_16_PCREL_S1: | |
14565 | /* We adjust the offset back to even. */ | |
14566 | if ((*valP & 0x1) != 0) | |
14567 | --(*valP); | |
14568 | ||
14569 | if (! fixP->fx_done) | |
14570 | break; | |
14571 | ||
14572 | /* Should never visit here, because we keep the relocation. */ | |
14573 | abort (); | |
14574 | break; | |
14575 | ||
252b5132 RH |
14576 | case BFD_RELOC_VTABLE_INHERIT: |
14577 | fixP->fx_done = 0; | |
14578 | if (fixP->fx_addsy | |
14579 | && !S_IS_DEFINED (fixP->fx_addsy) | |
14580 | && !S_IS_WEAK (fixP->fx_addsy)) | |
14581 | S_SET_WEAK (fixP->fx_addsy); | |
14582 | break; | |
14583 | ||
14584 | case BFD_RELOC_VTABLE_ENTRY: | |
14585 | fixP->fx_done = 0; | |
14586 | break; | |
14587 | ||
14588 | default: | |
b37df7c4 | 14589 | abort (); |
252b5132 | 14590 | } |
a7ebbfdf TS |
14591 | |
14592 | /* Remember value for tc_gen_reloc. */ | |
14593 | fixP->fx_addnumber = *valP; | |
252b5132 RH |
14594 | } |
14595 | ||
252b5132 | 14596 | static symbolS * |
17a2f251 | 14597 | get_symbol (void) |
252b5132 RH |
14598 | { |
14599 | int c; | |
14600 | char *name; | |
14601 | symbolS *p; | |
14602 | ||
14603 | name = input_line_pointer; | |
14604 | c = get_symbol_end (); | |
14605 | p = (symbolS *) symbol_find_or_make (name); | |
14606 | *input_line_pointer = c; | |
14607 | return p; | |
14608 | } | |
14609 | ||
742a56fe RS |
14610 | /* Align the current frag to a given power of two. If a particular |
14611 | fill byte should be used, FILL points to an integer that contains | |
14612 | that byte, otherwise FILL is null. | |
14613 | ||
462427c4 RS |
14614 | This function used to have the comment: |
14615 | ||
14616 | The MIPS assembler also automatically adjusts any preceding label. | |
14617 | ||
14618 | The implementation therefore applied the adjustment to a maximum of | |
14619 | one label. However, other label adjustments are applied to batches | |
14620 | of labels, and adjusting just one caused problems when new labels | |
14621 | were added for the sake of debugging or unwind information. | |
14622 | We therefore adjust all preceding labels (given as LABELS) instead. */ | |
252b5132 RH |
14623 | |
14624 | static void | |
462427c4 | 14625 | mips_align (int to, int *fill, struct insn_label_list *labels) |
252b5132 | 14626 | { |
7d10b47d | 14627 | mips_emit_delays (); |
df58fc94 | 14628 | mips_record_compressed_mode (); |
742a56fe RS |
14629 | if (fill == NULL && subseg_text_p (now_seg)) |
14630 | frag_align_code (to, 0); | |
14631 | else | |
14632 | frag_align (to, fill ? *fill : 0, 0); | |
252b5132 | 14633 | record_alignment (now_seg, to); |
462427c4 | 14634 | mips_move_labels (labels, FALSE); |
252b5132 RH |
14635 | } |
14636 | ||
14637 | /* Align to a given power of two. .align 0 turns off the automatic | |
14638 | alignment used by the data creating pseudo-ops. */ | |
14639 | ||
14640 | static void | |
17a2f251 | 14641 | s_align (int x ATTRIBUTE_UNUSED) |
252b5132 | 14642 | { |
742a56fe | 14643 | int temp, fill_value, *fill_ptr; |
49954fb4 | 14644 | long max_alignment = 28; |
252b5132 | 14645 | |
54f4ddb3 | 14646 | /* o Note that the assembler pulls down any immediately preceding label |
252b5132 | 14647 | to the aligned address. |
54f4ddb3 | 14648 | o It's not documented but auto alignment is reinstated by |
252b5132 | 14649 | a .align pseudo instruction. |
54f4ddb3 | 14650 | o Note also that after auto alignment is turned off the mips assembler |
252b5132 | 14651 | issues an error on attempt to assemble an improperly aligned data item. |
54f4ddb3 | 14652 | We don't. */ |
252b5132 RH |
14653 | |
14654 | temp = get_absolute_expression (); | |
14655 | if (temp > max_alignment) | |
1661c76c | 14656 | as_bad (_("alignment too large, %d assumed"), temp = max_alignment); |
252b5132 RH |
14657 | else if (temp < 0) |
14658 | { | |
1661c76c | 14659 | as_warn (_("alignment negative, 0 assumed")); |
252b5132 RH |
14660 | temp = 0; |
14661 | } | |
14662 | if (*input_line_pointer == ',') | |
14663 | { | |
f9419b05 | 14664 | ++input_line_pointer; |
742a56fe RS |
14665 | fill_value = get_absolute_expression (); |
14666 | fill_ptr = &fill_value; | |
252b5132 RH |
14667 | } |
14668 | else | |
742a56fe | 14669 | fill_ptr = 0; |
252b5132 RH |
14670 | if (temp) |
14671 | { | |
a8dbcb85 TS |
14672 | segment_info_type *si = seg_info (now_seg); |
14673 | struct insn_label_list *l = si->label_list; | |
54f4ddb3 | 14674 | /* Auto alignment should be switched on by next section change. */ |
252b5132 | 14675 | auto_align = 1; |
462427c4 | 14676 | mips_align (temp, fill_ptr, l); |
252b5132 RH |
14677 | } |
14678 | else | |
14679 | { | |
14680 | auto_align = 0; | |
14681 | } | |
14682 | ||
14683 | demand_empty_rest_of_line (); | |
14684 | } | |
14685 | ||
252b5132 | 14686 | static void |
17a2f251 | 14687 | s_change_sec (int sec) |
252b5132 RH |
14688 | { |
14689 | segT seg; | |
14690 | ||
252b5132 RH |
14691 | /* The ELF backend needs to know that we are changing sections, so |
14692 | that .previous works correctly. We could do something like check | |
b6ff326e | 14693 | for an obj_section_change_hook macro, but that might be confusing |
252b5132 RH |
14694 | as it would not be appropriate to use it in the section changing |
14695 | functions in read.c, since obj-elf.c intercepts those. FIXME: | |
14696 | This should be cleaner, somehow. */ | |
f3ded42a | 14697 | obj_elf_section_change_hook (); |
252b5132 | 14698 | |
7d10b47d | 14699 | mips_emit_delays (); |
6a32d874 | 14700 | |
252b5132 RH |
14701 | switch (sec) |
14702 | { | |
14703 | case 't': | |
14704 | s_text (0); | |
14705 | break; | |
14706 | case 'd': | |
14707 | s_data (0); | |
14708 | break; | |
14709 | case 'b': | |
14710 | subseg_set (bss_section, (subsegT) get_absolute_expression ()); | |
14711 | demand_empty_rest_of_line (); | |
14712 | break; | |
14713 | ||
14714 | case 'r': | |
4d0d148d TS |
14715 | seg = subseg_new (RDATA_SECTION_NAME, |
14716 | (subsegT) get_absolute_expression ()); | |
f3ded42a RS |
14717 | bfd_set_section_flags (stdoutput, seg, (SEC_ALLOC | SEC_LOAD |
14718 | | SEC_READONLY | SEC_RELOC | |
14719 | | SEC_DATA)); | |
14720 | if (strncmp (TARGET_OS, "elf", 3) != 0) | |
14721 | record_alignment (seg, 4); | |
4d0d148d | 14722 | demand_empty_rest_of_line (); |
252b5132 RH |
14723 | break; |
14724 | ||
14725 | case 's': | |
4d0d148d | 14726 | seg = subseg_new (".sdata", (subsegT) get_absolute_expression ()); |
f3ded42a RS |
14727 | bfd_set_section_flags (stdoutput, seg, |
14728 | SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA); | |
14729 | if (strncmp (TARGET_OS, "elf", 3) != 0) | |
14730 | record_alignment (seg, 4); | |
4d0d148d TS |
14731 | demand_empty_rest_of_line (); |
14732 | break; | |
998b3c36 MR |
14733 | |
14734 | case 'B': | |
14735 | seg = subseg_new (".sbss", (subsegT) get_absolute_expression ()); | |
f3ded42a RS |
14736 | bfd_set_section_flags (stdoutput, seg, SEC_ALLOC); |
14737 | if (strncmp (TARGET_OS, "elf", 3) != 0) | |
14738 | record_alignment (seg, 4); | |
998b3c36 MR |
14739 | demand_empty_rest_of_line (); |
14740 | break; | |
252b5132 RH |
14741 | } |
14742 | ||
14743 | auto_align = 1; | |
14744 | } | |
b34976b6 | 14745 | |
cca86cc8 | 14746 | void |
17a2f251 | 14747 | s_change_section (int ignore ATTRIBUTE_UNUSED) |
cca86cc8 | 14748 | { |
cca86cc8 SC |
14749 | char *section_name; |
14750 | char c; | |
684022ea | 14751 | char next_c = 0; |
cca86cc8 SC |
14752 | int section_type; |
14753 | int section_flag; | |
14754 | int section_entry_size; | |
14755 | int section_alignment; | |
b34976b6 | 14756 | |
cca86cc8 SC |
14757 | section_name = input_line_pointer; |
14758 | c = get_symbol_end (); | |
a816d1ed AO |
14759 | if (c) |
14760 | next_c = *(input_line_pointer + 1); | |
cca86cc8 | 14761 | |
4cf0dd0d TS |
14762 | /* Do we have .section Name<,"flags">? */ |
14763 | if (c != ',' || (c == ',' && next_c == '"')) | |
cca86cc8 | 14764 | { |
4cf0dd0d TS |
14765 | /* just after name is now '\0'. */ |
14766 | *input_line_pointer = c; | |
cca86cc8 SC |
14767 | input_line_pointer = section_name; |
14768 | obj_elf_section (ignore); | |
14769 | return; | |
14770 | } | |
14771 | input_line_pointer++; | |
14772 | ||
14773 | /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */ | |
14774 | if (c == ',') | |
14775 | section_type = get_absolute_expression (); | |
14776 | else | |
14777 | section_type = 0; | |
14778 | if (*input_line_pointer++ == ',') | |
14779 | section_flag = get_absolute_expression (); | |
14780 | else | |
14781 | section_flag = 0; | |
14782 | if (*input_line_pointer++ == ',') | |
14783 | section_entry_size = get_absolute_expression (); | |
14784 | else | |
14785 | section_entry_size = 0; | |
14786 | if (*input_line_pointer++ == ',') | |
14787 | section_alignment = get_absolute_expression (); | |
14788 | else | |
14789 | section_alignment = 0; | |
87975d2a AM |
14790 | /* FIXME: really ignore? */ |
14791 | (void) section_alignment; | |
cca86cc8 | 14792 | |
a816d1ed AO |
14793 | section_name = xstrdup (section_name); |
14794 | ||
8ab8a5c8 RS |
14795 | /* When using the generic form of .section (as implemented by obj-elf.c), |
14796 | there's no way to set the section type to SHT_MIPS_DWARF. Users have | |
14797 | traditionally had to fall back on the more common @progbits instead. | |
14798 | ||
14799 | There's nothing really harmful in this, since bfd will correct | |
14800 | SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it | |
708587a4 | 14801 | means that, for backwards compatibility, the special_section entries |
8ab8a5c8 RS |
14802 | for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF. |
14803 | ||
14804 | Even so, we shouldn't force users of the MIPS .section syntax to | |
14805 | incorrectly label the sections as SHT_PROGBITS. The best compromise | |
14806 | seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the | |
14807 | generic type-checking code. */ | |
14808 | if (section_type == SHT_MIPS_DWARF) | |
14809 | section_type = SHT_PROGBITS; | |
14810 | ||
cca86cc8 SC |
14811 | obj_elf_change_section (section_name, section_type, section_flag, |
14812 | section_entry_size, 0, 0, 0); | |
a816d1ed AO |
14813 | |
14814 | if (now_seg->name != section_name) | |
14815 | free (section_name); | |
cca86cc8 | 14816 | } |
252b5132 RH |
14817 | |
14818 | void | |
17a2f251 | 14819 | mips_enable_auto_align (void) |
252b5132 RH |
14820 | { |
14821 | auto_align = 1; | |
14822 | } | |
14823 | ||
14824 | static void | |
17a2f251 | 14825 | s_cons (int log_size) |
252b5132 | 14826 | { |
a8dbcb85 TS |
14827 | segment_info_type *si = seg_info (now_seg); |
14828 | struct insn_label_list *l = si->label_list; | |
252b5132 | 14829 | |
7d10b47d | 14830 | mips_emit_delays (); |
252b5132 | 14831 | if (log_size > 0 && auto_align) |
462427c4 | 14832 | mips_align (log_size, 0, l); |
252b5132 | 14833 | cons (1 << log_size); |
a1facbec | 14834 | mips_clear_insn_labels (); |
252b5132 RH |
14835 | } |
14836 | ||
14837 | static void | |
17a2f251 | 14838 | s_float_cons (int type) |
252b5132 | 14839 | { |
a8dbcb85 TS |
14840 | segment_info_type *si = seg_info (now_seg); |
14841 | struct insn_label_list *l = si->label_list; | |
252b5132 | 14842 | |
7d10b47d | 14843 | mips_emit_delays (); |
252b5132 RH |
14844 | |
14845 | if (auto_align) | |
49309057 ILT |
14846 | { |
14847 | if (type == 'd') | |
462427c4 | 14848 | mips_align (3, 0, l); |
49309057 | 14849 | else |
462427c4 | 14850 | mips_align (2, 0, l); |
49309057 | 14851 | } |
252b5132 | 14852 | |
252b5132 | 14853 | float_cons (type); |
a1facbec | 14854 | mips_clear_insn_labels (); |
252b5132 RH |
14855 | } |
14856 | ||
14857 | /* Handle .globl. We need to override it because on Irix 5 you are | |
14858 | permitted to say | |
14859 | .globl foo .text | |
14860 | where foo is an undefined symbol, to mean that foo should be | |
14861 | considered to be the address of a function. */ | |
14862 | ||
14863 | static void | |
17a2f251 | 14864 | s_mips_globl (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
14865 | { |
14866 | char *name; | |
14867 | int c; | |
14868 | symbolS *symbolP; | |
14869 | flagword flag; | |
14870 | ||
8a06b769 | 14871 | do |
252b5132 | 14872 | { |
8a06b769 | 14873 | name = input_line_pointer; |
252b5132 | 14874 | c = get_symbol_end (); |
8a06b769 TS |
14875 | symbolP = symbol_find_or_make (name); |
14876 | S_SET_EXTERNAL (symbolP); | |
14877 | ||
252b5132 | 14878 | *input_line_pointer = c; |
8a06b769 | 14879 | SKIP_WHITESPACE (); |
252b5132 | 14880 | |
8a06b769 TS |
14881 | /* On Irix 5, every global symbol that is not explicitly labelled as |
14882 | being a function is apparently labelled as being an object. */ | |
14883 | flag = BSF_OBJECT; | |
252b5132 | 14884 | |
8a06b769 TS |
14885 | if (!is_end_of_line[(unsigned char) *input_line_pointer] |
14886 | && (*input_line_pointer != ',')) | |
14887 | { | |
14888 | char *secname; | |
14889 | asection *sec; | |
14890 | ||
14891 | secname = input_line_pointer; | |
14892 | c = get_symbol_end (); | |
14893 | sec = bfd_get_section_by_name (stdoutput, secname); | |
14894 | if (sec == NULL) | |
14895 | as_bad (_("%s: no such section"), secname); | |
14896 | *input_line_pointer = c; | |
14897 | ||
14898 | if (sec != NULL && (sec->flags & SEC_CODE) != 0) | |
14899 | flag = BSF_FUNCTION; | |
14900 | } | |
14901 | ||
14902 | symbol_get_bfdsym (symbolP)->flags |= flag; | |
14903 | ||
14904 | c = *input_line_pointer; | |
14905 | if (c == ',') | |
14906 | { | |
14907 | input_line_pointer++; | |
14908 | SKIP_WHITESPACE (); | |
14909 | if (is_end_of_line[(unsigned char) *input_line_pointer]) | |
14910 | c = '\n'; | |
14911 | } | |
14912 | } | |
14913 | while (c == ','); | |
252b5132 | 14914 | |
252b5132 RH |
14915 | demand_empty_rest_of_line (); |
14916 | } | |
14917 | ||
14918 | static void | |
17a2f251 | 14919 | s_option (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
14920 | { |
14921 | char *opt; | |
14922 | char c; | |
14923 | ||
14924 | opt = input_line_pointer; | |
14925 | c = get_symbol_end (); | |
14926 | ||
14927 | if (*opt == 'O') | |
14928 | { | |
14929 | /* FIXME: What does this mean? */ | |
14930 | } | |
14931 | else if (strncmp (opt, "pic", 3) == 0) | |
14932 | { | |
14933 | int i; | |
14934 | ||
14935 | i = atoi (opt + 3); | |
14936 | if (i == 0) | |
14937 | mips_pic = NO_PIC; | |
14938 | else if (i == 2) | |
143d77c5 | 14939 | { |
8b828383 | 14940 | mips_pic = SVR4_PIC; |
143d77c5 EC |
14941 | mips_abicalls = TRUE; |
14942 | } | |
252b5132 RH |
14943 | else |
14944 | as_bad (_(".option pic%d not supported"), i); | |
14945 | ||
4d0d148d | 14946 | if (mips_pic == SVR4_PIC) |
252b5132 RH |
14947 | { |
14948 | if (g_switch_seen && g_switch_value != 0) | |
14949 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
14950 | g_switch_value = 0; | |
14951 | bfd_set_gp_size (stdoutput, 0); | |
14952 | } | |
14953 | } | |
14954 | else | |
1661c76c | 14955 | as_warn (_("unrecognized option \"%s\""), opt); |
252b5132 RH |
14956 | |
14957 | *input_line_pointer = c; | |
14958 | demand_empty_rest_of_line (); | |
14959 | } | |
14960 | ||
14961 | /* This structure is used to hold a stack of .set values. */ | |
14962 | ||
e972090a NC |
14963 | struct mips_option_stack |
14964 | { | |
252b5132 RH |
14965 | struct mips_option_stack *next; |
14966 | struct mips_set_options options; | |
14967 | }; | |
14968 | ||
14969 | static struct mips_option_stack *mips_opts_stack; | |
14970 | ||
14971 | /* Handle the .set pseudo-op. */ | |
14972 | ||
14973 | static void | |
17a2f251 | 14974 | s_mipsset (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
14975 | { |
14976 | char *name = input_line_pointer, ch; | |
c6278170 | 14977 | const struct mips_ase *ase; |
252b5132 RH |
14978 | |
14979 | while (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
f9419b05 | 14980 | ++input_line_pointer; |
252b5132 RH |
14981 | ch = *input_line_pointer; |
14982 | *input_line_pointer = '\0'; | |
14983 | ||
14984 | if (strcmp (name, "reorder") == 0) | |
14985 | { | |
7d10b47d RS |
14986 | if (mips_opts.noreorder) |
14987 | end_noreorder (); | |
252b5132 RH |
14988 | } |
14989 | else if (strcmp (name, "noreorder") == 0) | |
14990 | { | |
7d10b47d RS |
14991 | if (!mips_opts.noreorder) |
14992 | start_noreorder (); | |
252b5132 | 14993 | } |
741fe287 MR |
14994 | else if (strncmp (name, "at=", 3) == 0) |
14995 | { | |
14996 | char *s = name + 3; | |
14997 | ||
14998 | if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, &mips_opts.at)) | |
1661c76c | 14999 | as_bad (_("unrecognized register name `%s'"), s); |
741fe287 | 15000 | } |
252b5132 RH |
15001 | else if (strcmp (name, "at") == 0) |
15002 | { | |
741fe287 | 15003 | mips_opts.at = ATREG; |
252b5132 RH |
15004 | } |
15005 | else if (strcmp (name, "noat") == 0) | |
15006 | { | |
741fe287 | 15007 | mips_opts.at = ZERO; |
252b5132 RH |
15008 | } |
15009 | else if (strcmp (name, "macro") == 0) | |
15010 | { | |
15011 | mips_opts.warn_about_macros = 0; | |
15012 | } | |
15013 | else if (strcmp (name, "nomacro") == 0) | |
15014 | { | |
15015 | if (mips_opts.noreorder == 0) | |
15016 | as_bad (_("`noreorder' must be set before `nomacro'")); | |
15017 | mips_opts.warn_about_macros = 1; | |
15018 | } | |
15019 | else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0) | |
15020 | { | |
15021 | mips_opts.nomove = 0; | |
15022 | } | |
15023 | else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0) | |
15024 | { | |
15025 | mips_opts.nomove = 1; | |
15026 | } | |
15027 | else if (strcmp (name, "bopt") == 0) | |
15028 | { | |
15029 | mips_opts.nobopt = 0; | |
15030 | } | |
15031 | else if (strcmp (name, "nobopt") == 0) | |
15032 | { | |
15033 | mips_opts.nobopt = 1; | |
15034 | } | |
ad3fea08 | 15035 | else if (strcmp (name, "gp=default") == 0) |
bad1aba3 | 15036 | mips_opts.gp = file_mips_opts.gp; |
ad3fea08 | 15037 | else if (strcmp (name, "gp=32") == 0) |
bad1aba3 | 15038 | mips_opts.gp = 32; |
ad3fea08 TS |
15039 | else if (strcmp (name, "gp=64") == 0) |
15040 | { | |
15041 | if (!ISA_HAS_64BIT_REGS (mips_opts.isa)) | |
20203fb9 | 15042 | as_warn (_("%s isa does not support 64-bit registers"), |
ad3fea08 | 15043 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
bad1aba3 | 15044 | mips_opts.gp = 64; |
ad3fea08 TS |
15045 | } |
15046 | else if (strcmp (name, "fp=default") == 0) | |
0b35dfee | 15047 | mips_opts.fp = file_mips_opts.fp; |
ad3fea08 | 15048 | else if (strcmp (name, "fp=32") == 0) |
0b35dfee | 15049 | mips_opts.fp = 32; |
ad3fea08 TS |
15050 | else if (strcmp (name, "fp=64") == 0) |
15051 | { | |
15052 | if (!ISA_HAS_64BIT_FPRS (mips_opts.isa)) | |
20203fb9 | 15053 | as_warn (_("%s isa does not support 64-bit floating point registers"), |
ad3fea08 | 15054 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
0b35dfee | 15055 | mips_opts.fp = 64; |
ad3fea08 | 15056 | } |
037b32b9 AN |
15057 | else if (strcmp (name, "softfloat") == 0) |
15058 | mips_opts.soft_float = 1; | |
15059 | else if (strcmp (name, "hardfloat") == 0) | |
15060 | mips_opts.soft_float = 0; | |
15061 | else if (strcmp (name, "singlefloat") == 0) | |
15062 | mips_opts.single_float = 1; | |
15063 | else if (strcmp (name, "doublefloat") == 0) | |
15064 | mips_opts.single_float = 0; | |
252b5132 RH |
15065 | else if (strcmp (name, "mips16") == 0 |
15066 | || strcmp (name, "MIPS-16") == 0) | |
df58fc94 RS |
15067 | { |
15068 | if (mips_opts.micromips == 1) | |
15069 | as_fatal (_("`mips16' cannot be used with `micromips'")); | |
15070 | mips_opts.mips16 = 1; | |
15071 | } | |
252b5132 RH |
15072 | else if (strcmp (name, "nomips16") == 0 |
15073 | || strcmp (name, "noMIPS-16") == 0) | |
15074 | mips_opts.mips16 = 0; | |
df58fc94 RS |
15075 | else if (strcmp (name, "micromips") == 0) |
15076 | { | |
15077 | if (mips_opts.mips16 == 1) | |
15078 | as_fatal (_("`micromips' cannot be used with `mips16'")); | |
15079 | mips_opts.micromips = 1; | |
15080 | } | |
15081 | else if (strcmp (name, "nomicromips") == 0) | |
15082 | mips_opts.micromips = 0; | |
c6278170 RS |
15083 | else if (name[0] == 'n' |
15084 | && name[1] == 'o' | |
15085 | && (ase = mips_lookup_ase (name + 2))) | |
15086 | mips_set_ase (ase, FALSE); | |
15087 | else if ((ase = mips_lookup_ase (name))) | |
15088 | mips_set_ase (ase, TRUE); | |
1a2c1fad | 15089 | else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0) |
252b5132 | 15090 | { |
af7ee8bf | 15091 | int reset = 0; |
252b5132 | 15092 | |
1a2c1fad CD |
15093 | /* Permit the user to change the ISA and architecture on the fly. |
15094 | Needless to say, misuse can cause serious problems. */ | |
81a21e38 | 15095 | if (strcmp (name, "mips0") == 0 || strcmp (name, "arch=default") == 0) |
af7ee8bf CD |
15096 | { |
15097 | reset = 1; | |
0b35dfee | 15098 | mips_opts.isa = file_mips_opts.isa; |
15099 | mips_opts.arch = file_mips_opts.arch; | |
1a2c1fad CD |
15100 | } |
15101 | else if (strncmp (name, "arch=", 5) == 0) | |
15102 | { | |
15103 | const struct mips_cpu_info *p; | |
15104 | ||
15105 | p = mips_parse_cpu("internal use", name + 5); | |
15106 | if (!p) | |
15107 | as_bad (_("unknown architecture %s"), name + 5); | |
15108 | else | |
15109 | { | |
15110 | mips_opts.arch = p->cpu; | |
15111 | mips_opts.isa = p->isa; | |
15112 | } | |
15113 | } | |
81a21e38 TS |
15114 | else if (strncmp (name, "mips", 4) == 0) |
15115 | { | |
15116 | const struct mips_cpu_info *p; | |
15117 | ||
15118 | p = mips_parse_cpu("internal use", name); | |
15119 | if (!p) | |
15120 | as_bad (_("unknown ISA level %s"), name + 4); | |
15121 | else | |
15122 | { | |
15123 | mips_opts.arch = p->cpu; | |
15124 | mips_opts.isa = p->isa; | |
15125 | } | |
15126 | } | |
af7ee8bf | 15127 | else |
81a21e38 | 15128 | as_bad (_("unknown ISA or architecture %s"), name); |
af7ee8bf CD |
15129 | |
15130 | switch (mips_opts.isa) | |
98d3f06f KH |
15131 | { |
15132 | case 0: | |
98d3f06f | 15133 | break; |
af7ee8bf CD |
15134 | case ISA_MIPS1: |
15135 | case ISA_MIPS2: | |
15136 | case ISA_MIPS32: | |
15137 | case ISA_MIPS32R2: | |
ae52f483 AB |
15138 | case ISA_MIPS32R3: |
15139 | case ISA_MIPS32R5: | |
bad1aba3 | 15140 | mips_opts.gp = 32; |
0b35dfee | 15141 | mips_opts.fp = 32; |
98d3f06f | 15142 | break; |
af7ee8bf CD |
15143 | case ISA_MIPS3: |
15144 | case ISA_MIPS4: | |
15145 | case ISA_MIPS5: | |
15146 | case ISA_MIPS64: | |
5f74bc13 | 15147 | case ISA_MIPS64R2: |
ae52f483 AB |
15148 | case ISA_MIPS64R3: |
15149 | case ISA_MIPS64R5: | |
bad1aba3 | 15150 | mips_opts.gp = 64; |
e407c74b NC |
15151 | if (mips_opts.arch == CPU_R5900) |
15152 | { | |
0b35dfee | 15153 | mips_opts.fp = 32; |
e407c74b NC |
15154 | } |
15155 | else | |
15156 | { | |
0b35dfee | 15157 | mips_opts.fp = 64; |
e407c74b | 15158 | } |
98d3f06f KH |
15159 | break; |
15160 | default: | |
15161 | as_bad (_("unknown ISA level %s"), name + 4); | |
15162 | break; | |
15163 | } | |
af7ee8bf | 15164 | if (reset) |
98d3f06f | 15165 | { |
bad1aba3 | 15166 | mips_opts.gp = file_mips_opts.gp; |
0b35dfee | 15167 | mips_opts.fp = file_mips_opts.fp; |
98d3f06f | 15168 | } |
252b5132 RH |
15169 | } |
15170 | else if (strcmp (name, "autoextend") == 0) | |
15171 | mips_opts.noautoextend = 0; | |
15172 | else if (strcmp (name, "noautoextend") == 0) | |
15173 | mips_opts.noautoextend = 1; | |
833794fc MR |
15174 | else if (strcmp (name, "insn32") == 0) |
15175 | mips_opts.insn32 = TRUE; | |
15176 | else if (strcmp (name, "noinsn32") == 0) | |
15177 | mips_opts.insn32 = FALSE; | |
252b5132 RH |
15178 | else if (strcmp (name, "push") == 0) |
15179 | { | |
15180 | struct mips_option_stack *s; | |
15181 | ||
15182 | s = (struct mips_option_stack *) xmalloc (sizeof *s); | |
15183 | s->next = mips_opts_stack; | |
15184 | s->options = mips_opts; | |
15185 | mips_opts_stack = s; | |
15186 | } | |
15187 | else if (strcmp (name, "pop") == 0) | |
15188 | { | |
15189 | struct mips_option_stack *s; | |
15190 | ||
15191 | s = mips_opts_stack; | |
15192 | if (s == NULL) | |
15193 | as_bad (_(".set pop with no .set push")); | |
15194 | else | |
15195 | { | |
15196 | /* If we're changing the reorder mode we need to handle | |
15197 | delay slots correctly. */ | |
15198 | if (s->options.noreorder && ! mips_opts.noreorder) | |
7d10b47d | 15199 | start_noreorder (); |
252b5132 | 15200 | else if (! s->options.noreorder && mips_opts.noreorder) |
7d10b47d | 15201 | end_noreorder (); |
252b5132 RH |
15202 | |
15203 | mips_opts = s->options; | |
15204 | mips_opts_stack = s->next; | |
15205 | free (s); | |
15206 | } | |
15207 | } | |
aed1a261 RS |
15208 | else if (strcmp (name, "sym32") == 0) |
15209 | mips_opts.sym32 = TRUE; | |
15210 | else if (strcmp (name, "nosym32") == 0) | |
15211 | mips_opts.sym32 = FALSE; | |
e6559e01 JM |
15212 | else if (strchr (name, ',')) |
15213 | { | |
15214 | /* Generic ".set" directive; use the generic handler. */ | |
15215 | *input_line_pointer = ch; | |
15216 | input_line_pointer = name; | |
15217 | s_set (0); | |
15218 | return; | |
15219 | } | |
252b5132 RH |
15220 | else |
15221 | { | |
1661c76c | 15222 | as_warn (_("tried to set unrecognized symbol: %s\n"), name); |
252b5132 | 15223 | } |
c6278170 | 15224 | mips_check_isa_supports_ases (); |
252b5132 RH |
15225 | *input_line_pointer = ch; |
15226 | demand_empty_rest_of_line (); | |
15227 | } | |
15228 | ||
15229 | /* Handle the .abicalls pseudo-op. I believe this is equivalent to | |
15230 | .option pic2. It means to generate SVR4 PIC calls. */ | |
15231 | ||
15232 | static void | |
17a2f251 | 15233 | s_abicalls (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
15234 | { |
15235 | mips_pic = SVR4_PIC; | |
143d77c5 | 15236 | mips_abicalls = TRUE; |
4d0d148d TS |
15237 | |
15238 | if (g_switch_seen && g_switch_value != 0) | |
15239 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
15240 | g_switch_value = 0; | |
15241 | ||
252b5132 RH |
15242 | bfd_set_gp_size (stdoutput, 0); |
15243 | demand_empty_rest_of_line (); | |
15244 | } | |
15245 | ||
15246 | /* Handle the .cpload pseudo-op. This is used when generating SVR4 | |
15247 | PIC code. It sets the $gp register for the function based on the | |
15248 | function address, which is in the register named in the argument. | |
15249 | This uses a relocation against _gp_disp, which is handled specially | |
15250 | by the linker. The result is: | |
15251 | lui $gp,%hi(_gp_disp) | |
15252 | addiu $gp,$gp,%lo(_gp_disp) | |
15253 | addu $gp,$gp,.cpload argument | |
aa6975fb ILT |
15254 | The .cpload argument is normally $25 == $t9. |
15255 | ||
15256 | The -mno-shared option changes this to: | |
bbe506e8 TS |
15257 | lui $gp,%hi(__gnu_local_gp) |
15258 | addiu $gp,$gp,%lo(__gnu_local_gp) | |
aa6975fb ILT |
15259 | and the argument is ignored. This saves an instruction, but the |
15260 | resulting code is not position independent; it uses an absolute | |
bbe506e8 TS |
15261 | address for __gnu_local_gp. Thus code assembled with -mno-shared |
15262 | can go into an ordinary executable, but not into a shared library. */ | |
252b5132 RH |
15263 | |
15264 | static void | |
17a2f251 | 15265 | s_cpload (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
15266 | { |
15267 | expressionS ex; | |
aa6975fb ILT |
15268 | int reg; |
15269 | int in_shared; | |
252b5132 | 15270 | |
6478892d TS |
15271 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
15272 | .cpload is ignored. */ | |
15273 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) | |
252b5132 RH |
15274 | { |
15275 | s_ignore (0); | |
15276 | return; | |
15277 | } | |
15278 | ||
a276b80c MR |
15279 | if (mips_opts.mips16) |
15280 | { | |
15281 | as_bad (_("%s not supported in MIPS16 mode"), ".cpload"); | |
15282 | ignore_rest_of_line (); | |
15283 | return; | |
15284 | } | |
15285 | ||
d3ecfc59 | 15286 | /* .cpload should be in a .set noreorder section. */ |
252b5132 RH |
15287 | if (mips_opts.noreorder == 0) |
15288 | as_warn (_(".cpload not in noreorder section")); | |
15289 | ||
aa6975fb ILT |
15290 | reg = tc_get_register (0); |
15291 | ||
15292 | /* If we need to produce a 64-bit address, we are better off using | |
15293 | the default instruction sequence. */ | |
aed1a261 | 15294 | in_shared = mips_in_shared || HAVE_64BIT_SYMBOLS; |
aa6975fb | 15295 | |
252b5132 | 15296 | ex.X_op = O_symbol; |
bbe506e8 TS |
15297 | ex.X_add_symbol = symbol_find_or_make (in_shared ? "_gp_disp" : |
15298 | "__gnu_local_gp"); | |
252b5132 RH |
15299 | ex.X_op_symbol = NULL; |
15300 | ex.X_add_number = 0; | |
15301 | ||
15302 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ | |
49309057 | 15303 | symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; |
252b5132 | 15304 | |
8a75745d MR |
15305 | mips_mark_labels (); |
15306 | mips_assembling_insn = TRUE; | |
15307 | ||
584892a6 | 15308 | macro_start (); |
67c0d1eb RS |
15309 | macro_build_lui (&ex, mips_gp_register); |
15310 | macro_build (&ex, "addiu", "t,r,j", mips_gp_register, | |
17a2f251 | 15311 | mips_gp_register, BFD_RELOC_LO16); |
aa6975fb ILT |
15312 | if (in_shared) |
15313 | macro_build (NULL, "addu", "d,v,t", mips_gp_register, | |
15314 | mips_gp_register, reg); | |
584892a6 | 15315 | macro_end (); |
252b5132 | 15316 | |
8a75745d | 15317 | mips_assembling_insn = FALSE; |
252b5132 RH |
15318 | demand_empty_rest_of_line (); |
15319 | } | |
15320 | ||
6478892d TS |
15321 | /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is: |
15322 | .cpsetup $reg1, offset|$reg2, label | |
15323 | ||
15324 | If offset is given, this results in: | |
15325 | sd $gp, offset($sp) | |
956cd1d6 | 15326 | lui $gp, %hi(%neg(%gp_rel(label))) |
698b7d9d TS |
15327 | addiu $gp, $gp, %lo(%neg(%gp_rel(label))) |
15328 | daddu $gp, $gp, $reg1 | |
6478892d TS |
15329 | |
15330 | If $reg2 is given, this results in: | |
15331 | daddu $reg2, $gp, $0 | |
956cd1d6 | 15332 | lui $gp, %hi(%neg(%gp_rel(label))) |
698b7d9d TS |
15333 | addiu $gp, $gp, %lo(%neg(%gp_rel(label))) |
15334 | daddu $gp, $gp, $reg1 | |
aa6975fb ILT |
15335 | $reg1 is normally $25 == $t9. |
15336 | ||
15337 | The -mno-shared option replaces the last three instructions with | |
15338 | lui $gp,%hi(_gp) | |
54f4ddb3 | 15339 | addiu $gp,$gp,%lo(_gp) */ |
aa6975fb | 15340 | |
6478892d | 15341 | static void |
17a2f251 | 15342 | s_cpsetup (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
15343 | { |
15344 | expressionS ex_off; | |
15345 | expressionS ex_sym; | |
15346 | int reg1; | |
6478892d | 15347 | |
8586fc66 | 15348 | /* If we are not generating SVR4 PIC code, .cpsetup is ignored. |
6478892d TS |
15349 | We also need NewABI support. */ |
15350 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
15351 | { | |
15352 | s_ignore (0); | |
15353 | return; | |
15354 | } | |
15355 | ||
a276b80c MR |
15356 | if (mips_opts.mips16) |
15357 | { | |
15358 | as_bad (_("%s not supported in MIPS16 mode"), ".cpsetup"); | |
15359 | ignore_rest_of_line (); | |
15360 | return; | |
15361 | } | |
15362 | ||
6478892d TS |
15363 | reg1 = tc_get_register (0); |
15364 | SKIP_WHITESPACE (); | |
15365 | if (*input_line_pointer != ',') | |
15366 | { | |
15367 | as_bad (_("missing argument separator ',' for .cpsetup")); | |
15368 | return; | |
15369 | } | |
15370 | else | |
80245285 | 15371 | ++input_line_pointer; |
6478892d TS |
15372 | SKIP_WHITESPACE (); |
15373 | if (*input_line_pointer == '$') | |
80245285 TS |
15374 | { |
15375 | mips_cpreturn_register = tc_get_register (0); | |
15376 | mips_cpreturn_offset = -1; | |
15377 | } | |
6478892d | 15378 | else |
80245285 TS |
15379 | { |
15380 | mips_cpreturn_offset = get_absolute_expression (); | |
15381 | mips_cpreturn_register = -1; | |
15382 | } | |
6478892d TS |
15383 | SKIP_WHITESPACE (); |
15384 | if (*input_line_pointer != ',') | |
15385 | { | |
15386 | as_bad (_("missing argument separator ',' for .cpsetup")); | |
15387 | return; | |
15388 | } | |
15389 | else | |
f9419b05 | 15390 | ++input_line_pointer; |
6478892d | 15391 | SKIP_WHITESPACE (); |
f21f8242 | 15392 | expression (&ex_sym); |
6478892d | 15393 | |
8a75745d MR |
15394 | mips_mark_labels (); |
15395 | mips_assembling_insn = TRUE; | |
15396 | ||
584892a6 | 15397 | macro_start (); |
6478892d TS |
15398 | if (mips_cpreturn_register == -1) |
15399 | { | |
15400 | ex_off.X_op = O_constant; | |
15401 | ex_off.X_add_symbol = NULL; | |
15402 | ex_off.X_op_symbol = NULL; | |
15403 | ex_off.X_add_number = mips_cpreturn_offset; | |
15404 | ||
67c0d1eb | 15405 | macro_build (&ex_off, "sd", "t,o(b)", mips_gp_register, |
17a2f251 | 15406 | BFD_RELOC_LO16, SP); |
6478892d TS |
15407 | } |
15408 | else | |
67c0d1eb | 15409 | macro_build (NULL, "daddu", "d,v,t", mips_cpreturn_register, |
17a2f251 | 15410 | mips_gp_register, 0); |
6478892d | 15411 | |
aed1a261 | 15412 | if (mips_in_shared || HAVE_64BIT_SYMBOLS) |
aa6975fb | 15413 | { |
df58fc94 | 15414 | macro_build (&ex_sym, "lui", LUI_FMT, mips_gp_register, |
aa6975fb ILT |
15415 | -1, BFD_RELOC_GPREL16, BFD_RELOC_MIPS_SUB, |
15416 | BFD_RELOC_HI16_S); | |
15417 | ||
15418 | macro_build (&ex_sym, "addiu", "t,r,j", mips_gp_register, | |
15419 | mips_gp_register, -1, BFD_RELOC_GPREL16, | |
15420 | BFD_RELOC_MIPS_SUB, BFD_RELOC_LO16); | |
15421 | ||
15422 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register, | |
15423 | mips_gp_register, reg1); | |
15424 | } | |
15425 | else | |
15426 | { | |
15427 | expressionS ex; | |
15428 | ||
15429 | ex.X_op = O_symbol; | |
4184909a | 15430 | ex.X_add_symbol = symbol_find_or_make ("__gnu_local_gp"); |
aa6975fb ILT |
15431 | ex.X_op_symbol = NULL; |
15432 | ex.X_add_number = 0; | |
6e1304d8 | 15433 | |
aa6975fb ILT |
15434 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ |
15435 | symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; | |
15436 | ||
15437 | macro_build_lui (&ex, mips_gp_register); | |
15438 | macro_build (&ex, "addiu", "t,r,j", mips_gp_register, | |
15439 | mips_gp_register, BFD_RELOC_LO16); | |
15440 | } | |
f21f8242 | 15441 | |
584892a6 | 15442 | macro_end (); |
6478892d | 15443 | |
8a75745d | 15444 | mips_assembling_insn = FALSE; |
6478892d TS |
15445 | demand_empty_rest_of_line (); |
15446 | } | |
15447 | ||
15448 | static void | |
17a2f251 | 15449 | s_cplocal (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
15450 | { |
15451 | /* If we are not generating SVR4 PIC code, or if this is not NewABI code, | |
54f4ddb3 | 15452 | .cplocal is ignored. */ |
6478892d TS |
15453 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) |
15454 | { | |
15455 | s_ignore (0); | |
15456 | return; | |
15457 | } | |
15458 | ||
a276b80c MR |
15459 | if (mips_opts.mips16) |
15460 | { | |
15461 | as_bad (_("%s not supported in MIPS16 mode"), ".cplocal"); | |
15462 | ignore_rest_of_line (); | |
15463 | return; | |
15464 | } | |
15465 | ||
6478892d | 15466 | mips_gp_register = tc_get_register (0); |
85b51719 | 15467 | demand_empty_rest_of_line (); |
6478892d TS |
15468 | } |
15469 | ||
252b5132 RH |
15470 | /* Handle the .cprestore pseudo-op. This stores $gp into a given |
15471 | offset from $sp. The offset is remembered, and after making a PIC | |
15472 | call $gp is restored from that location. */ | |
15473 | ||
15474 | static void | |
17a2f251 | 15475 | s_cprestore (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
15476 | { |
15477 | expressionS ex; | |
252b5132 | 15478 | |
6478892d | 15479 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
c9914766 | 15480 | .cprestore is ignored. */ |
6478892d | 15481 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) |
252b5132 RH |
15482 | { |
15483 | s_ignore (0); | |
15484 | return; | |
15485 | } | |
15486 | ||
a276b80c MR |
15487 | if (mips_opts.mips16) |
15488 | { | |
15489 | as_bad (_("%s not supported in MIPS16 mode"), ".cprestore"); | |
15490 | ignore_rest_of_line (); | |
15491 | return; | |
15492 | } | |
15493 | ||
252b5132 | 15494 | mips_cprestore_offset = get_absolute_expression (); |
7a621144 | 15495 | mips_cprestore_valid = 1; |
252b5132 RH |
15496 | |
15497 | ex.X_op = O_constant; | |
15498 | ex.X_add_symbol = NULL; | |
15499 | ex.X_op_symbol = NULL; | |
15500 | ex.X_add_number = mips_cprestore_offset; | |
15501 | ||
8a75745d MR |
15502 | mips_mark_labels (); |
15503 | mips_assembling_insn = TRUE; | |
15504 | ||
584892a6 | 15505 | macro_start (); |
67c0d1eb RS |
15506 | macro_build_ldst_constoffset (&ex, ADDRESS_STORE_INSN, mips_gp_register, |
15507 | SP, HAVE_64BIT_ADDRESSES); | |
584892a6 | 15508 | macro_end (); |
252b5132 | 15509 | |
8a75745d | 15510 | mips_assembling_insn = FALSE; |
252b5132 RH |
15511 | demand_empty_rest_of_line (); |
15512 | } | |
15513 | ||
6478892d | 15514 | /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset |
67c1ffbe | 15515 | was given in the preceding .cpsetup, it results in: |
6478892d | 15516 | ld $gp, offset($sp) |
76b3015f | 15517 | |
6478892d | 15518 | If a register $reg2 was given there, it results in: |
54f4ddb3 TS |
15519 | daddu $gp, $reg2, $0 */ |
15520 | ||
6478892d | 15521 | static void |
17a2f251 | 15522 | s_cpreturn (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
15523 | { |
15524 | expressionS ex; | |
6478892d TS |
15525 | |
15526 | /* If we are not generating SVR4 PIC code, .cpreturn is ignored. | |
15527 | We also need NewABI support. */ | |
15528 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
15529 | { | |
15530 | s_ignore (0); | |
15531 | return; | |
15532 | } | |
15533 | ||
a276b80c MR |
15534 | if (mips_opts.mips16) |
15535 | { | |
15536 | as_bad (_("%s not supported in MIPS16 mode"), ".cpreturn"); | |
15537 | ignore_rest_of_line (); | |
15538 | return; | |
15539 | } | |
15540 | ||
8a75745d MR |
15541 | mips_mark_labels (); |
15542 | mips_assembling_insn = TRUE; | |
15543 | ||
584892a6 | 15544 | macro_start (); |
6478892d TS |
15545 | if (mips_cpreturn_register == -1) |
15546 | { | |
15547 | ex.X_op = O_constant; | |
15548 | ex.X_add_symbol = NULL; | |
15549 | ex.X_op_symbol = NULL; | |
15550 | ex.X_add_number = mips_cpreturn_offset; | |
15551 | ||
67c0d1eb | 15552 | macro_build (&ex, "ld", "t,o(b)", mips_gp_register, BFD_RELOC_LO16, SP); |
6478892d TS |
15553 | } |
15554 | else | |
67c0d1eb | 15555 | macro_build (NULL, "daddu", "d,v,t", mips_gp_register, |
17a2f251 | 15556 | mips_cpreturn_register, 0); |
584892a6 | 15557 | macro_end (); |
6478892d | 15558 | |
8a75745d | 15559 | mips_assembling_insn = FALSE; |
6478892d TS |
15560 | demand_empty_rest_of_line (); |
15561 | } | |
15562 | ||
d0f13682 CLT |
15563 | /* Handle a .dtprelword, .dtpreldword, .tprelword, or .tpreldword |
15564 | pseudo-op; DIRSTR says which. The pseudo-op generates a BYTES-size | |
15565 | DTP- or TP-relative relocation of type RTYPE, for use in either DWARF | |
15566 | debug information or MIPS16 TLS. */ | |
741d6ea8 JM |
15567 | |
15568 | static void | |
d0f13682 CLT |
15569 | s_tls_rel_directive (const size_t bytes, const char *dirstr, |
15570 | bfd_reloc_code_real_type rtype) | |
741d6ea8 JM |
15571 | { |
15572 | expressionS ex; | |
15573 | char *p; | |
15574 | ||
15575 | expression (&ex); | |
15576 | ||
15577 | if (ex.X_op != O_symbol) | |
15578 | { | |
1661c76c | 15579 | as_bad (_("unsupported use of %s"), dirstr); |
741d6ea8 JM |
15580 | ignore_rest_of_line (); |
15581 | } | |
15582 | ||
15583 | p = frag_more (bytes); | |
15584 | md_number_to_chars (p, 0, bytes); | |
d0f13682 | 15585 | fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, FALSE, rtype); |
741d6ea8 | 15586 | demand_empty_rest_of_line (); |
de64cffd | 15587 | mips_clear_insn_labels (); |
741d6ea8 JM |
15588 | } |
15589 | ||
15590 | /* Handle .dtprelword. */ | |
15591 | ||
15592 | static void | |
15593 | s_dtprelword (int ignore ATTRIBUTE_UNUSED) | |
15594 | { | |
d0f13682 | 15595 | s_tls_rel_directive (4, ".dtprelword", BFD_RELOC_MIPS_TLS_DTPREL32); |
741d6ea8 JM |
15596 | } |
15597 | ||
15598 | /* Handle .dtpreldword. */ | |
15599 | ||
15600 | static void | |
15601 | s_dtpreldword (int ignore ATTRIBUTE_UNUSED) | |
15602 | { | |
d0f13682 CLT |
15603 | s_tls_rel_directive (8, ".dtpreldword", BFD_RELOC_MIPS_TLS_DTPREL64); |
15604 | } | |
15605 | ||
15606 | /* Handle .tprelword. */ | |
15607 | ||
15608 | static void | |
15609 | s_tprelword (int ignore ATTRIBUTE_UNUSED) | |
15610 | { | |
15611 | s_tls_rel_directive (4, ".tprelword", BFD_RELOC_MIPS_TLS_TPREL32); | |
15612 | } | |
15613 | ||
15614 | /* Handle .tpreldword. */ | |
15615 | ||
15616 | static void | |
15617 | s_tpreldword (int ignore ATTRIBUTE_UNUSED) | |
15618 | { | |
15619 | s_tls_rel_directive (8, ".tpreldword", BFD_RELOC_MIPS_TLS_TPREL64); | |
741d6ea8 JM |
15620 | } |
15621 | ||
6478892d TS |
15622 | /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC |
15623 | code. It sets the offset to use in gp_rel relocations. */ | |
15624 | ||
15625 | static void | |
17a2f251 | 15626 | s_gpvalue (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
15627 | { |
15628 | /* If we are not generating SVR4 PIC code, .gpvalue is ignored. | |
15629 | We also need NewABI support. */ | |
15630 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
15631 | { | |
15632 | s_ignore (0); | |
15633 | return; | |
15634 | } | |
15635 | ||
def2e0dd | 15636 | mips_gprel_offset = get_absolute_expression (); |
6478892d TS |
15637 | |
15638 | demand_empty_rest_of_line (); | |
15639 | } | |
15640 | ||
252b5132 RH |
15641 | /* Handle the .gpword pseudo-op. This is used when generating PIC |
15642 | code. It generates a 32 bit GP relative reloc. */ | |
15643 | ||
15644 | static void | |
17a2f251 | 15645 | s_gpword (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 15646 | { |
a8dbcb85 TS |
15647 | segment_info_type *si; |
15648 | struct insn_label_list *l; | |
252b5132 RH |
15649 | expressionS ex; |
15650 | char *p; | |
15651 | ||
15652 | /* When not generating PIC code, this is treated as .word. */ | |
15653 | if (mips_pic != SVR4_PIC) | |
15654 | { | |
15655 | s_cons (2); | |
15656 | return; | |
15657 | } | |
15658 | ||
a8dbcb85 TS |
15659 | si = seg_info (now_seg); |
15660 | l = si->label_list; | |
7d10b47d | 15661 | mips_emit_delays (); |
252b5132 | 15662 | if (auto_align) |
462427c4 | 15663 | mips_align (2, 0, l); |
252b5132 RH |
15664 | |
15665 | expression (&ex); | |
a1facbec | 15666 | mips_clear_insn_labels (); |
252b5132 RH |
15667 | |
15668 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
15669 | { | |
1661c76c | 15670 | as_bad (_("unsupported use of .gpword")); |
252b5132 RH |
15671 | ignore_rest_of_line (); |
15672 | } | |
15673 | ||
15674 | p = frag_more (4); | |
17a2f251 | 15675 | md_number_to_chars (p, 0, 4); |
b34976b6 | 15676 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, |
cdf6fd85 | 15677 | BFD_RELOC_GPREL32); |
252b5132 RH |
15678 | |
15679 | demand_empty_rest_of_line (); | |
15680 | } | |
15681 | ||
10181a0d | 15682 | static void |
17a2f251 | 15683 | s_gpdword (int ignore ATTRIBUTE_UNUSED) |
10181a0d | 15684 | { |
a8dbcb85 TS |
15685 | segment_info_type *si; |
15686 | struct insn_label_list *l; | |
10181a0d AO |
15687 | expressionS ex; |
15688 | char *p; | |
15689 | ||
15690 | /* When not generating PIC code, this is treated as .dword. */ | |
15691 | if (mips_pic != SVR4_PIC) | |
15692 | { | |
15693 | s_cons (3); | |
15694 | return; | |
15695 | } | |
15696 | ||
a8dbcb85 TS |
15697 | si = seg_info (now_seg); |
15698 | l = si->label_list; | |
7d10b47d | 15699 | mips_emit_delays (); |
10181a0d | 15700 | if (auto_align) |
462427c4 | 15701 | mips_align (3, 0, l); |
10181a0d AO |
15702 | |
15703 | expression (&ex); | |
a1facbec | 15704 | mips_clear_insn_labels (); |
10181a0d AO |
15705 | |
15706 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
15707 | { | |
1661c76c | 15708 | as_bad (_("unsupported use of .gpdword")); |
10181a0d AO |
15709 | ignore_rest_of_line (); |
15710 | } | |
15711 | ||
15712 | p = frag_more (8); | |
17a2f251 | 15713 | md_number_to_chars (p, 0, 8); |
a105a300 | 15714 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, |
6e1304d8 | 15715 | BFD_RELOC_GPREL32)->fx_tcbit = 1; |
10181a0d AO |
15716 | |
15717 | /* GPREL32 composed with 64 gives a 64-bit GP offset. */ | |
6e1304d8 RS |
15718 | fix_new (frag_now, p - frag_now->fr_literal, 8, NULL, 0, |
15719 | FALSE, BFD_RELOC_64)->fx_tcbit = 1; | |
10181a0d AO |
15720 | |
15721 | demand_empty_rest_of_line (); | |
15722 | } | |
15723 | ||
a3f278e2 CM |
15724 | /* Handle the .ehword pseudo-op. This is used when generating unwinding |
15725 | tables. It generates a R_MIPS_EH reloc. */ | |
15726 | ||
15727 | static void | |
15728 | s_ehword (int ignore ATTRIBUTE_UNUSED) | |
15729 | { | |
15730 | expressionS ex; | |
15731 | char *p; | |
15732 | ||
15733 | mips_emit_delays (); | |
15734 | ||
15735 | expression (&ex); | |
15736 | mips_clear_insn_labels (); | |
15737 | ||
15738 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
15739 | { | |
1661c76c | 15740 | as_bad (_("unsupported use of .ehword")); |
a3f278e2 CM |
15741 | ignore_rest_of_line (); |
15742 | } | |
15743 | ||
15744 | p = frag_more (4); | |
15745 | md_number_to_chars (p, 0, 4); | |
15746 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, | |
15747 | BFD_RELOC_MIPS_EH); | |
15748 | ||
15749 | demand_empty_rest_of_line (); | |
15750 | } | |
15751 | ||
252b5132 RH |
15752 | /* Handle the .cpadd pseudo-op. This is used when dealing with switch |
15753 | tables in SVR4 PIC code. */ | |
15754 | ||
15755 | static void | |
17a2f251 | 15756 | s_cpadd (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 15757 | { |
252b5132 RH |
15758 | int reg; |
15759 | ||
10181a0d AO |
15760 | /* This is ignored when not generating SVR4 PIC code. */ |
15761 | if (mips_pic != SVR4_PIC) | |
252b5132 RH |
15762 | { |
15763 | s_ignore (0); | |
15764 | return; | |
15765 | } | |
15766 | ||
8a75745d MR |
15767 | mips_mark_labels (); |
15768 | mips_assembling_insn = TRUE; | |
15769 | ||
252b5132 | 15770 | /* Add $gp to the register named as an argument. */ |
584892a6 | 15771 | macro_start (); |
252b5132 | 15772 | reg = tc_get_register (0); |
67c0d1eb | 15773 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register); |
584892a6 | 15774 | macro_end (); |
252b5132 | 15775 | |
8a75745d | 15776 | mips_assembling_insn = FALSE; |
bdaaa2e1 | 15777 | demand_empty_rest_of_line (); |
252b5132 RH |
15778 | } |
15779 | ||
15780 | /* Handle the .insn pseudo-op. This marks instruction labels in | |
df58fc94 | 15781 | mips16/micromips mode. This permits the linker to handle them specially, |
252b5132 RH |
15782 | such as generating jalx instructions when needed. We also make |
15783 | them odd for the duration of the assembly, in order to generate the | |
15784 | right sort of code. We will make them even in the adjust_symtab | |
15785 | routine, while leaving them marked. This is convenient for the | |
15786 | debugger and the disassembler. The linker knows to make them odd | |
15787 | again. */ | |
15788 | ||
15789 | static void | |
17a2f251 | 15790 | s_insn (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 15791 | { |
df58fc94 | 15792 | mips_mark_labels (); |
252b5132 RH |
15793 | |
15794 | demand_empty_rest_of_line (); | |
15795 | } | |
15796 | ||
ba92f887 MR |
15797 | /* Handle the .nan pseudo-op. */ |
15798 | ||
15799 | static void | |
15800 | s_nan (int ignore ATTRIBUTE_UNUSED) | |
15801 | { | |
15802 | static const char str_legacy[] = "legacy"; | |
15803 | static const char str_2008[] = "2008"; | |
15804 | size_t i; | |
15805 | ||
15806 | for (i = 0; !is_end_of_line[(unsigned char) input_line_pointer[i]]; i++); | |
15807 | ||
15808 | if (i == sizeof (str_2008) - 1 | |
15809 | && memcmp (input_line_pointer, str_2008, i) == 0) | |
15810 | mips_flag_nan2008 = TRUE; | |
15811 | else if (i == sizeof (str_legacy) - 1 | |
15812 | && memcmp (input_line_pointer, str_legacy, i) == 0) | |
15813 | mips_flag_nan2008 = FALSE; | |
15814 | else | |
1661c76c | 15815 | as_bad (_("bad .nan directive")); |
ba92f887 MR |
15816 | |
15817 | input_line_pointer += i; | |
15818 | demand_empty_rest_of_line (); | |
15819 | } | |
15820 | ||
754e2bb9 RS |
15821 | /* Handle a .stab[snd] directive. Ideally these directives would be |
15822 | implemented in a transparent way, so that removing them would not | |
15823 | have any effect on the generated instructions. However, s_stab | |
15824 | internally changes the section, so in practice we need to decide | |
15825 | now whether the preceding label marks compressed code. We do not | |
15826 | support changing the compression mode of a label after a .stab* | |
15827 | directive, such as in: | |
15828 | ||
15829 | foo: | |
15830 | .stabs ... | |
15831 | .set mips16 | |
15832 | ||
15833 | so the current mode wins. */ | |
252b5132 RH |
15834 | |
15835 | static void | |
17a2f251 | 15836 | s_mips_stab (int type) |
252b5132 | 15837 | { |
754e2bb9 | 15838 | mips_mark_labels (); |
252b5132 RH |
15839 | s_stab (type); |
15840 | } | |
15841 | ||
54f4ddb3 | 15842 | /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */ |
252b5132 RH |
15843 | |
15844 | static void | |
17a2f251 | 15845 | s_mips_weakext (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
15846 | { |
15847 | char *name; | |
15848 | int c; | |
15849 | symbolS *symbolP; | |
15850 | expressionS exp; | |
15851 | ||
15852 | name = input_line_pointer; | |
15853 | c = get_symbol_end (); | |
15854 | symbolP = symbol_find_or_make (name); | |
15855 | S_SET_WEAK (symbolP); | |
15856 | *input_line_pointer = c; | |
15857 | ||
15858 | SKIP_WHITESPACE (); | |
15859 | ||
15860 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
15861 | { | |
15862 | if (S_IS_DEFINED (symbolP)) | |
15863 | { | |
20203fb9 | 15864 | as_bad (_("ignoring attempt to redefine symbol %s"), |
252b5132 RH |
15865 | S_GET_NAME (symbolP)); |
15866 | ignore_rest_of_line (); | |
15867 | return; | |
15868 | } | |
bdaaa2e1 | 15869 | |
252b5132 RH |
15870 | if (*input_line_pointer == ',') |
15871 | { | |
15872 | ++input_line_pointer; | |
15873 | SKIP_WHITESPACE (); | |
15874 | } | |
bdaaa2e1 | 15875 | |
252b5132 RH |
15876 | expression (&exp); |
15877 | if (exp.X_op != O_symbol) | |
15878 | { | |
20203fb9 | 15879 | as_bad (_("bad .weakext directive")); |
98d3f06f | 15880 | ignore_rest_of_line (); |
252b5132 RH |
15881 | return; |
15882 | } | |
49309057 | 15883 | symbol_set_value_expression (symbolP, &exp); |
252b5132 RH |
15884 | } |
15885 | ||
15886 | demand_empty_rest_of_line (); | |
15887 | } | |
15888 | ||
15889 | /* Parse a register string into a number. Called from the ECOFF code | |
15890 | to parse .frame. The argument is non-zero if this is the frame | |
15891 | register, so that we can record it in mips_frame_reg. */ | |
15892 | ||
15893 | int | |
17a2f251 | 15894 | tc_get_register (int frame) |
252b5132 | 15895 | { |
707bfff6 | 15896 | unsigned int reg; |
252b5132 RH |
15897 | |
15898 | SKIP_WHITESPACE (); | |
707bfff6 TS |
15899 | if (! reg_lookup (&input_line_pointer, RWARN | RTYPE_NUM | RTYPE_GP, ®)) |
15900 | reg = 0; | |
252b5132 | 15901 | if (frame) |
7a621144 DJ |
15902 | { |
15903 | mips_frame_reg = reg != 0 ? reg : SP; | |
15904 | mips_frame_reg_valid = 1; | |
15905 | mips_cprestore_valid = 0; | |
15906 | } | |
252b5132 RH |
15907 | return reg; |
15908 | } | |
15909 | ||
15910 | valueT | |
17a2f251 | 15911 | md_section_align (asection *seg, valueT addr) |
252b5132 RH |
15912 | { |
15913 | int align = bfd_get_section_alignment (stdoutput, seg); | |
15914 | ||
f3ded42a RS |
15915 | /* We don't need to align ELF sections to the full alignment. |
15916 | However, Irix 5 may prefer that we align them at least to a 16 | |
15917 | byte boundary. We don't bother to align the sections if we | |
15918 | are targeted for an embedded system. */ | |
15919 | if (strncmp (TARGET_OS, "elf", 3) == 0) | |
15920 | return addr; | |
15921 | if (align > 4) | |
15922 | align = 4; | |
252b5132 RH |
15923 | |
15924 | return ((addr + (1 << align) - 1) & (-1 << align)); | |
15925 | } | |
15926 | ||
15927 | /* Utility routine, called from above as well. If called while the | |
15928 | input file is still being read, it's only an approximation. (For | |
15929 | example, a symbol may later become defined which appeared to be | |
15930 | undefined earlier.) */ | |
15931 | ||
15932 | static int | |
17a2f251 | 15933 | nopic_need_relax (symbolS *sym, int before_relaxing) |
252b5132 RH |
15934 | { |
15935 | if (sym == 0) | |
15936 | return 0; | |
15937 | ||
4d0d148d | 15938 | if (g_switch_value > 0) |
252b5132 RH |
15939 | { |
15940 | const char *symname; | |
15941 | int change; | |
15942 | ||
c9914766 | 15943 | /* Find out whether this symbol can be referenced off the $gp |
252b5132 RH |
15944 | register. It can be if it is smaller than the -G size or if |
15945 | it is in the .sdata or .sbss section. Certain symbols can | |
c9914766 | 15946 | not be referenced off the $gp, although it appears as though |
252b5132 RH |
15947 | they can. */ |
15948 | symname = S_GET_NAME (sym); | |
15949 | if (symname != (const char *) NULL | |
15950 | && (strcmp (symname, "eprol") == 0 | |
15951 | || strcmp (symname, "etext") == 0 | |
15952 | || strcmp (symname, "_gp") == 0 | |
15953 | || strcmp (symname, "edata") == 0 | |
15954 | || strcmp (symname, "_fbss") == 0 | |
15955 | || strcmp (symname, "_fdata") == 0 | |
15956 | || strcmp (symname, "_ftext") == 0 | |
15957 | || strcmp (symname, "end") == 0 | |
15958 | || strcmp (symname, "_gp_disp") == 0)) | |
15959 | change = 1; | |
15960 | else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym)) | |
15961 | && (0 | |
15962 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 ILT |
15963 | || (symbol_get_obj (sym)->ecoff_extern_size != 0 |
15964 | && (symbol_get_obj (sym)->ecoff_extern_size | |
15965 | <= g_switch_value)) | |
252b5132 RH |
15966 | #endif |
15967 | /* We must defer this decision until after the whole | |
15968 | file has been read, since there might be a .extern | |
15969 | after the first use of this symbol. */ | |
15970 | || (before_relaxing | |
15971 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 | 15972 | && symbol_get_obj (sym)->ecoff_extern_size == 0 |
252b5132 RH |
15973 | #endif |
15974 | && S_GET_VALUE (sym) == 0) | |
15975 | || (S_GET_VALUE (sym) != 0 | |
15976 | && S_GET_VALUE (sym) <= g_switch_value))) | |
15977 | change = 0; | |
15978 | else | |
15979 | { | |
15980 | const char *segname; | |
15981 | ||
15982 | segname = segment_name (S_GET_SEGMENT (sym)); | |
9c2799c2 | 15983 | gas_assert (strcmp (segname, ".lit8") != 0 |
252b5132 RH |
15984 | && strcmp (segname, ".lit4") != 0); |
15985 | change = (strcmp (segname, ".sdata") != 0 | |
fba2b7f9 GK |
15986 | && strcmp (segname, ".sbss") != 0 |
15987 | && strncmp (segname, ".sdata.", 7) != 0 | |
d4dc2f22 TS |
15988 | && strncmp (segname, ".sbss.", 6) != 0 |
15989 | && strncmp (segname, ".gnu.linkonce.sb.", 17) != 0 | |
fba2b7f9 | 15990 | && strncmp (segname, ".gnu.linkonce.s.", 16) != 0); |
252b5132 RH |
15991 | } |
15992 | return change; | |
15993 | } | |
15994 | else | |
c9914766 | 15995 | /* We are not optimizing for the $gp register. */ |
252b5132 RH |
15996 | return 1; |
15997 | } | |
15998 | ||
5919d012 RS |
15999 | |
16000 | /* Return true if the given symbol should be considered local for SVR4 PIC. */ | |
16001 | ||
16002 | static bfd_boolean | |
17a2f251 | 16003 | pic_need_relax (symbolS *sym, asection *segtype) |
5919d012 RS |
16004 | { |
16005 | asection *symsec; | |
5919d012 RS |
16006 | |
16007 | /* Handle the case of a symbol equated to another symbol. */ | |
16008 | while (symbol_equated_reloc_p (sym)) | |
16009 | { | |
16010 | symbolS *n; | |
16011 | ||
5f0fe04b | 16012 | /* It's possible to get a loop here in a badly written program. */ |
5919d012 RS |
16013 | n = symbol_get_value_expression (sym)->X_add_symbol; |
16014 | if (n == sym) | |
16015 | break; | |
16016 | sym = n; | |
16017 | } | |
16018 | ||
df1f3cda DD |
16019 | if (symbol_section_p (sym)) |
16020 | return TRUE; | |
16021 | ||
5919d012 RS |
16022 | symsec = S_GET_SEGMENT (sym); |
16023 | ||
5919d012 | 16024 | /* This must duplicate the test in adjust_reloc_syms. */ |
45dfa85a AM |
16025 | return (!bfd_is_und_section (symsec) |
16026 | && !bfd_is_abs_section (symsec) | |
5f0fe04b TS |
16027 | && !bfd_is_com_section (symsec) |
16028 | && !s_is_linkonce (sym, segtype) | |
5919d012 | 16029 | /* A global or weak symbol is treated as external. */ |
f3ded42a | 16030 | && (!S_IS_WEAK (sym) && !S_IS_EXTERNAL (sym))); |
5919d012 RS |
16031 | } |
16032 | ||
16033 | ||
252b5132 RH |
16034 | /* Given a mips16 variant frag FRAGP, return non-zero if it needs an |
16035 | extended opcode. SEC is the section the frag is in. */ | |
16036 | ||
16037 | static int | |
17a2f251 | 16038 | mips16_extended_frag (fragS *fragp, asection *sec, long stretch) |
252b5132 RH |
16039 | { |
16040 | int type; | |
3ccad066 | 16041 | const struct mips_int_operand *operand; |
252b5132 | 16042 | offsetT val; |
252b5132 | 16043 | segT symsec; |
98aa84af | 16044 | fragS *sym_frag; |
252b5132 RH |
16045 | |
16046 | if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype)) | |
16047 | return 0; | |
16048 | if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype)) | |
16049 | return 1; | |
16050 | ||
16051 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
3ccad066 | 16052 | operand = mips16_immed_operand (type, FALSE); |
252b5132 | 16053 | |
98aa84af | 16054 | sym_frag = symbol_get_frag (fragp->fr_symbol); |
ac62c346 | 16055 | val = S_GET_VALUE (fragp->fr_symbol); |
98aa84af | 16056 | symsec = S_GET_SEGMENT (fragp->fr_symbol); |
252b5132 | 16057 | |
3ccad066 | 16058 | if (operand->root.type == OP_PCREL) |
252b5132 | 16059 | { |
3ccad066 | 16060 | const struct mips_pcrel_operand *pcrel_op; |
252b5132 | 16061 | addressT addr; |
3ccad066 | 16062 | offsetT maxtiny; |
252b5132 RH |
16063 | |
16064 | /* We won't have the section when we are called from | |
16065 | mips_relax_frag. However, we will always have been called | |
16066 | from md_estimate_size_before_relax first. If this is a | |
16067 | branch to a different section, we mark it as such. If SEC is | |
16068 | NULL, and the frag is not marked, then it must be a branch to | |
16069 | the same section. */ | |
3ccad066 | 16070 | pcrel_op = (const struct mips_pcrel_operand *) operand; |
252b5132 RH |
16071 | if (sec == NULL) |
16072 | { | |
16073 | if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype)) | |
16074 | return 1; | |
16075 | } | |
16076 | else | |
16077 | { | |
98aa84af | 16078 | /* Must have been called from md_estimate_size_before_relax. */ |
252b5132 RH |
16079 | if (symsec != sec) |
16080 | { | |
16081 | fragp->fr_subtype = | |
16082 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
16083 | ||
16084 | /* FIXME: We should support this, and let the linker | |
16085 | catch branches and loads that are out of range. */ | |
16086 | as_bad_where (fragp->fr_file, fragp->fr_line, | |
16087 | _("unsupported PC relative reference to different section")); | |
16088 | ||
16089 | return 1; | |
16090 | } | |
98aa84af AM |
16091 | if (fragp != sym_frag && sym_frag->fr_address == 0) |
16092 | /* Assume non-extended on the first relaxation pass. | |
16093 | The address we have calculated will be bogus if this is | |
16094 | a forward branch to another frag, as the forward frag | |
16095 | will have fr_address == 0. */ | |
16096 | return 0; | |
252b5132 RH |
16097 | } |
16098 | ||
16099 | /* In this case, we know for sure that the symbol fragment is in | |
98aa84af AM |
16100 | the same section. If the relax_marker of the symbol fragment |
16101 | differs from the relax_marker of this fragment, we have not | |
16102 | yet adjusted the symbol fragment fr_address. We want to add | |
252b5132 RH |
16103 | in STRETCH in order to get a better estimate of the address. |
16104 | This particularly matters because of the shift bits. */ | |
16105 | if (stretch != 0 | |
98aa84af | 16106 | && sym_frag->relax_marker != fragp->relax_marker) |
252b5132 RH |
16107 | { |
16108 | fragS *f; | |
16109 | ||
16110 | /* Adjust stretch for any alignment frag. Note that if have | |
16111 | been expanding the earlier code, the symbol may be | |
16112 | defined in what appears to be an earlier frag. FIXME: | |
16113 | This doesn't handle the fr_subtype field, which specifies | |
16114 | a maximum number of bytes to skip when doing an | |
16115 | alignment. */ | |
98aa84af | 16116 | for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next) |
252b5132 RH |
16117 | { |
16118 | if (f->fr_type == rs_align || f->fr_type == rs_align_code) | |
16119 | { | |
16120 | if (stretch < 0) | |
16121 | stretch = - ((- stretch) | |
16122 | & ~ ((1 << (int) f->fr_offset) - 1)); | |
16123 | else | |
16124 | stretch &= ~ ((1 << (int) f->fr_offset) - 1); | |
16125 | if (stretch == 0) | |
16126 | break; | |
16127 | } | |
16128 | } | |
16129 | if (f != NULL) | |
16130 | val += stretch; | |
16131 | } | |
16132 | ||
16133 | addr = fragp->fr_address + fragp->fr_fix; | |
16134 | ||
16135 | /* The base address rules are complicated. The base address of | |
16136 | a branch is the following instruction. The base address of a | |
16137 | PC relative load or add is the instruction itself, but if it | |
16138 | is in a delay slot (in which case it can not be extended) use | |
16139 | the address of the instruction whose delay slot it is in. */ | |
3ccad066 | 16140 | if (pcrel_op->include_isa_bit) |
252b5132 RH |
16141 | { |
16142 | addr += 2; | |
16143 | ||
16144 | /* If we are currently assuming that this frag should be | |
16145 | extended, then, the current address is two bytes | |
bdaaa2e1 | 16146 | higher. */ |
252b5132 RH |
16147 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) |
16148 | addr += 2; | |
16149 | ||
16150 | /* Ignore the low bit in the target, since it will be set | |
16151 | for a text label. */ | |
3ccad066 | 16152 | val &= -2; |
252b5132 RH |
16153 | } |
16154 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) | |
16155 | addr -= 4; | |
16156 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
16157 | addr -= 2; | |
16158 | ||
3ccad066 | 16159 | val -= addr & -(1 << pcrel_op->align_log2); |
252b5132 RH |
16160 | |
16161 | /* If any of the shifted bits are set, we must use an extended | |
16162 | opcode. If the address depends on the size of this | |
16163 | instruction, this can lead to a loop, so we arrange to always | |
16164 | use an extended opcode. We only check this when we are in | |
16165 | the main relaxation loop, when SEC is NULL. */ | |
3ccad066 | 16166 | if ((val & ((1 << operand->shift) - 1)) != 0 && sec == NULL) |
252b5132 RH |
16167 | { |
16168 | fragp->fr_subtype = | |
16169 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
16170 | return 1; | |
16171 | } | |
16172 | ||
16173 | /* If we are about to mark a frag as extended because the value | |
3ccad066 RS |
16174 | is precisely the next value above maxtiny, then there is a |
16175 | chance of an infinite loop as in the following code: | |
252b5132 RH |
16176 | la $4,foo |
16177 | .skip 1020 | |
16178 | .align 2 | |
16179 | foo: | |
16180 | In this case when the la is extended, foo is 0x3fc bytes | |
16181 | away, so the la can be shrunk, but then foo is 0x400 away, so | |
16182 | the la must be extended. To avoid this loop, we mark the | |
16183 | frag as extended if it was small, and is about to become | |
3ccad066 RS |
16184 | extended with the next value above maxtiny. */ |
16185 | maxtiny = mips_int_operand_max (operand); | |
16186 | if (val == maxtiny + (1 << operand->shift) | |
252b5132 RH |
16187 | && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype) |
16188 | && sec == NULL) | |
16189 | { | |
16190 | fragp->fr_subtype = | |
16191 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
16192 | return 1; | |
16193 | } | |
16194 | } | |
16195 | else if (symsec != absolute_section && sec != NULL) | |
16196 | as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation")); | |
16197 | ||
3ccad066 | 16198 | return !mips16_immed_in_range_p (operand, BFD_RELOC_UNUSED, val); |
252b5132 RH |
16199 | } |
16200 | ||
4a6a3df4 AO |
16201 | /* Compute the length of a branch sequence, and adjust the |
16202 | RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the | |
16203 | worst-case length is computed, with UPDATE being used to indicate | |
16204 | whether an unconditional (-1), branch-likely (+1) or regular (0) | |
16205 | branch is to be computed. */ | |
16206 | static int | |
17a2f251 | 16207 | relaxed_branch_length (fragS *fragp, asection *sec, int update) |
4a6a3df4 | 16208 | { |
b34976b6 | 16209 | bfd_boolean toofar; |
4a6a3df4 AO |
16210 | int length; |
16211 | ||
16212 | if (fragp | |
16213 | && S_IS_DEFINED (fragp->fr_symbol) | |
16214 | && sec == S_GET_SEGMENT (fragp->fr_symbol)) | |
16215 | { | |
16216 | addressT addr; | |
16217 | offsetT val; | |
16218 | ||
16219 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; | |
16220 | ||
16221 | addr = fragp->fr_address + fragp->fr_fix + 4; | |
16222 | ||
16223 | val -= addr; | |
16224 | ||
16225 | toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2); | |
16226 | } | |
16227 | else if (fragp) | |
16228 | /* If the symbol is not defined or it's in a different segment, | |
16229 | assume the user knows what's going on and emit a short | |
16230 | branch. */ | |
b34976b6 | 16231 | toofar = FALSE; |
4a6a3df4 | 16232 | else |
b34976b6 | 16233 | toofar = TRUE; |
4a6a3df4 AO |
16234 | |
16235 | if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) | |
16236 | fragp->fr_subtype | |
66b3e8da MR |
16237 | = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp->fr_subtype), |
16238 | RELAX_BRANCH_UNCOND (fragp->fr_subtype), | |
4a6a3df4 AO |
16239 | RELAX_BRANCH_LIKELY (fragp->fr_subtype), |
16240 | RELAX_BRANCH_LINK (fragp->fr_subtype), | |
16241 | toofar); | |
16242 | ||
16243 | length = 4; | |
16244 | if (toofar) | |
16245 | { | |
16246 | if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0)) | |
16247 | length += 8; | |
16248 | ||
16249 | if (mips_pic != NO_PIC) | |
16250 | { | |
16251 | /* Additional space for PIC loading of target address. */ | |
16252 | length += 8; | |
16253 | if (mips_opts.isa == ISA_MIPS1) | |
16254 | /* Additional space for $at-stabilizing nop. */ | |
16255 | length += 4; | |
16256 | } | |
16257 | ||
16258 | /* If branch is conditional. */ | |
16259 | if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0)) | |
16260 | length += 8; | |
16261 | } | |
b34976b6 | 16262 | |
4a6a3df4 AO |
16263 | return length; |
16264 | } | |
16265 | ||
df58fc94 RS |
16266 | /* Compute the length of a branch sequence, and adjust the |
16267 | RELAX_MICROMIPS_TOOFAR32 bit accordingly. If FRAGP is NULL, the | |
16268 | worst-case length is computed, with UPDATE being used to indicate | |
16269 | whether an unconditional (-1), or regular (0) branch is to be | |
16270 | computed. */ | |
16271 | ||
16272 | static int | |
16273 | relaxed_micromips_32bit_branch_length (fragS *fragp, asection *sec, int update) | |
16274 | { | |
16275 | bfd_boolean toofar; | |
16276 | int length; | |
16277 | ||
16278 | if (fragp | |
16279 | && S_IS_DEFINED (fragp->fr_symbol) | |
16280 | && sec == S_GET_SEGMENT (fragp->fr_symbol)) | |
16281 | { | |
16282 | addressT addr; | |
16283 | offsetT val; | |
16284 | ||
16285 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; | |
16286 | /* Ignore the low bit in the target, since it will be set | |
16287 | for a text label. */ | |
16288 | if ((val & 1) != 0) | |
16289 | --val; | |
16290 | ||
16291 | addr = fragp->fr_address + fragp->fr_fix + 4; | |
16292 | ||
16293 | val -= addr; | |
16294 | ||
16295 | toofar = val < - (0x8000 << 1) || val >= (0x8000 << 1); | |
16296 | } | |
16297 | else if (fragp) | |
16298 | /* If the symbol is not defined or it's in a different segment, | |
16299 | assume the user knows what's going on and emit a short | |
16300 | branch. */ | |
16301 | toofar = FALSE; | |
16302 | else | |
16303 | toofar = TRUE; | |
16304 | ||
16305 | if (fragp && update | |
16306 | && toofar != RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype)) | |
16307 | fragp->fr_subtype = (toofar | |
16308 | ? RELAX_MICROMIPS_MARK_TOOFAR32 (fragp->fr_subtype) | |
16309 | : RELAX_MICROMIPS_CLEAR_TOOFAR32 (fragp->fr_subtype)); | |
16310 | ||
16311 | length = 4; | |
16312 | if (toofar) | |
16313 | { | |
16314 | bfd_boolean compact_known = fragp != NULL; | |
16315 | bfd_boolean compact = FALSE; | |
16316 | bfd_boolean uncond; | |
16317 | ||
16318 | if (compact_known) | |
16319 | compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype); | |
16320 | if (fragp) | |
16321 | uncond = RELAX_MICROMIPS_UNCOND (fragp->fr_subtype); | |
16322 | else | |
16323 | uncond = update < 0; | |
16324 | ||
16325 | /* If label is out of range, we turn branch <br>: | |
16326 | ||
16327 | <br> label # 4 bytes | |
16328 | 0: | |
16329 | ||
16330 | into: | |
16331 | ||
16332 | j label # 4 bytes | |
16333 | nop # 2 bytes if compact && !PIC | |
16334 | 0: | |
16335 | */ | |
16336 | if (mips_pic == NO_PIC && (!compact_known || compact)) | |
16337 | length += 2; | |
16338 | ||
16339 | /* If assembling PIC code, we further turn: | |
16340 | ||
16341 | j label # 4 bytes | |
16342 | ||
16343 | into: | |
16344 | ||
16345 | lw/ld at, %got(label)(gp) # 4 bytes | |
16346 | d/addiu at, %lo(label) # 4 bytes | |
16347 | jr/c at # 2 bytes | |
16348 | */ | |
16349 | if (mips_pic != NO_PIC) | |
16350 | length += 6; | |
16351 | ||
16352 | /* If branch <br> is conditional, we prepend negated branch <brneg>: | |
16353 | ||
16354 | <brneg> 0f # 4 bytes | |
16355 | nop # 2 bytes if !compact | |
16356 | */ | |
16357 | if (!uncond) | |
16358 | length += (compact_known && compact) ? 4 : 6; | |
16359 | } | |
16360 | ||
16361 | return length; | |
16362 | } | |
16363 | ||
16364 | /* Compute the length of a branch, and adjust the RELAX_MICROMIPS_TOOFAR16 | |
16365 | bit accordingly. */ | |
16366 | ||
16367 | static int | |
16368 | relaxed_micromips_16bit_branch_length (fragS *fragp, asection *sec, int update) | |
16369 | { | |
16370 | bfd_boolean toofar; | |
16371 | ||
df58fc94 RS |
16372 | if (fragp |
16373 | && S_IS_DEFINED (fragp->fr_symbol) | |
16374 | && sec == S_GET_SEGMENT (fragp->fr_symbol)) | |
16375 | { | |
16376 | addressT addr; | |
16377 | offsetT val; | |
16378 | int type; | |
16379 | ||
16380 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; | |
16381 | /* Ignore the low bit in the target, since it will be set | |
16382 | for a text label. */ | |
16383 | if ((val & 1) != 0) | |
16384 | --val; | |
16385 | ||
16386 | /* Assume this is a 2-byte branch. */ | |
16387 | addr = fragp->fr_address + fragp->fr_fix + 2; | |
16388 | ||
16389 | /* We try to avoid the infinite loop by not adding 2 more bytes for | |
16390 | long branches. */ | |
16391 | ||
16392 | val -= addr; | |
16393 | ||
16394 | type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype); | |
16395 | if (type == 'D') | |
16396 | toofar = val < - (0x200 << 1) || val >= (0x200 << 1); | |
16397 | else if (type == 'E') | |
16398 | toofar = val < - (0x40 << 1) || val >= (0x40 << 1); | |
16399 | else | |
16400 | abort (); | |
16401 | } | |
16402 | else | |
16403 | /* If the symbol is not defined or it's in a different segment, | |
16404 | we emit a normal 32-bit branch. */ | |
16405 | toofar = TRUE; | |
16406 | ||
16407 | if (fragp && update | |
16408 | && toofar != RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype)) | |
16409 | fragp->fr_subtype | |
16410 | = toofar ? RELAX_MICROMIPS_MARK_TOOFAR16 (fragp->fr_subtype) | |
16411 | : RELAX_MICROMIPS_CLEAR_TOOFAR16 (fragp->fr_subtype); | |
16412 | ||
16413 | if (toofar) | |
16414 | return 4; | |
16415 | ||
16416 | return 2; | |
16417 | } | |
16418 | ||
252b5132 RH |
16419 | /* Estimate the size of a frag before relaxing. Unless this is the |
16420 | mips16, we are not really relaxing here, and the final size is | |
16421 | encoded in the subtype information. For the mips16, we have to | |
16422 | decide whether we are using an extended opcode or not. */ | |
16423 | ||
252b5132 | 16424 | int |
17a2f251 | 16425 | md_estimate_size_before_relax (fragS *fragp, asection *segtype) |
252b5132 | 16426 | { |
5919d012 | 16427 | int change; |
252b5132 | 16428 | |
4a6a3df4 AO |
16429 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
16430 | { | |
16431 | ||
b34976b6 AM |
16432 | fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE); |
16433 | ||
4a6a3df4 AO |
16434 | return fragp->fr_var; |
16435 | } | |
16436 | ||
252b5132 | 16437 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
177b4a6a AO |
16438 | /* We don't want to modify the EXTENDED bit here; it might get us |
16439 | into infinite loops. We change it only in mips_relax_frag(). */ | |
16440 | return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2); | |
252b5132 | 16441 | |
df58fc94 RS |
16442 | if (RELAX_MICROMIPS_P (fragp->fr_subtype)) |
16443 | { | |
16444 | int length = 4; | |
16445 | ||
16446 | if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0) | |
16447 | length = relaxed_micromips_16bit_branch_length (fragp, segtype, FALSE); | |
16448 | if (length == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)) | |
16449 | length = relaxed_micromips_32bit_branch_length (fragp, segtype, FALSE); | |
16450 | fragp->fr_var = length; | |
16451 | ||
16452 | return length; | |
16453 | } | |
16454 | ||
252b5132 | 16455 | if (mips_pic == NO_PIC) |
5919d012 | 16456 | change = nopic_need_relax (fragp->fr_symbol, 0); |
252b5132 | 16457 | else if (mips_pic == SVR4_PIC) |
5919d012 | 16458 | change = pic_need_relax (fragp->fr_symbol, segtype); |
0a44bf69 RS |
16459 | else if (mips_pic == VXWORKS_PIC) |
16460 | /* For vxworks, GOT16 relocations never have a corresponding LO16. */ | |
16461 | change = 0; | |
252b5132 RH |
16462 | else |
16463 | abort (); | |
16464 | ||
16465 | if (change) | |
16466 | { | |
4d7206a2 | 16467 | fragp->fr_subtype |= RELAX_USE_SECOND; |
4d7206a2 | 16468 | return -RELAX_FIRST (fragp->fr_subtype); |
252b5132 | 16469 | } |
4d7206a2 RS |
16470 | else |
16471 | return -RELAX_SECOND (fragp->fr_subtype); | |
252b5132 RH |
16472 | } |
16473 | ||
16474 | /* This is called to see whether a reloc against a defined symbol | |
de7e6852 | 16475 | should be converted into a reloc against a section. */ |
252b5132 RH |
16476 | |
16477 | int | |
17a2f251 | 16478 | mips_fix_adjustable (fixS *fixp) |
252b5132 | 16479 | { |
252b5132 RH |
16480 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
16481 | || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
16482 | return 0; | |
a161fe53 | 16483 | |
252b5132 RH |
16484 | if (fixp->fx_addsy == NULL) |
16485 | return 1; | |
a161fe53 | 16486 | |
de7e6852 RS |
16487 | /* If symbol SYM is in a mergeable section, relocations of the form |
16488 | SYM + 0 can usually be made section-relative. The mergeable data | |
16489 | is then identified by the section offset rather than by the symbol. | |
16490 | ||
16491 | However, if we're generating REL LO16 relocations, the offset is split | |
16492 | between the LO16 and parterning high part relocation. The linker will | |
16493 | need to recalculate the complete offset in order to correctly identify | |
16494 | the merge data. | |
16495 | ||
16496 | The linker has traditionally not looked for the parterning high part | |
16497 | relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be | |
16498 | placed anywhere. Rather than break backwards compatibility by changing | |
16499 | this, it seems better not to force the issue, and instead keep the | |
16500 | original symbol. This will work with either linker behavior. */ | |
738e5348 | 16501 | if ((lo16_reloc_p (fixp->fx_r_type) |
704803a9 | 16502 | || reloc_needs_lo_p (fixp->fx_r_type)) |
de7e6852 RS |
16503 | && HAVE_IN_PLACE_ADDENDS |
16504 | && (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_MERGE) != 0) | |
16505 | return 0; | |
16506 | ||
ce70d90a | 16507 | /* There is no place to store an in-place offset for JALR relocations. |
2de39019 CM |
16508 | Likewise an in-range offset of limited PC-relative relocations may |
16509 | overflow the in-place relocatable field if recalculated against the | |
16510 | start address of the symbol's containing section. */ | |
ce70d90a | 16511 | if (HAVE_IN_PLACE_ADDENDS |
2de39019 CM |
16512 | && (limited_pcrel_reloc_p (fixp->fx_r_type) |
16513 | || jalr_reloc_p (fixp->fx_r_type))) | |
1180b5a4 RS |
16514 | return 0; |
16515 | ||
b314ec0e RS |
16516 | /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve |
16517 | to a floating-point stub. The same is true for non-R_MIPS16_26 | |
16518 | relocations against MIPS16 functions; in this case, the stub becomes | |
16519 | the function's canonical address. | |
16520 | ||
16521 | Floating-point stubs are stored in unique .mips16.call.* or | |
16522 | .mips16.fn.* sections. If a stub T for function F is in section S, | |
16523 | the first relocation in section S must be against F; this is how the | |
16524 | linker determines the target function. All relocations that might | |
16525 | resolve to T must also be against F. We therefore have the following | |
16526 | restrictions, which are given in an intentionally-redundant way: | |
16527 | ||
16528 | 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16 | |
16529 | symbols. | |
16530 | ||
16531 | 2. We cannot reduce a stub's relocations against non-MIPS16 symbols | |
16532 | if that stub might be used. | |
16533 | ||
16534 | 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16 | |
16535 | symbols. | |
16536 | ||
16537 | 4. We cannot reduce a stub's relocations against MIPS16 symbols if | |
16538 | that stub might be used. | |
16539 | ||
16540 | There is a further restriction: | |
16541 | ||
df58fc94 RS |
16542 | 5. We cannot reduce jump relocations (R_MIPS_26, R_MIPS16_26 or |
16543 | R_MICROMIPS_26_S1) against MIPS16 or microMIPS symbols on | |
16544 | targets with in-place addends; the relocation field cannot | |
b314ec0e RS |
16545 | encode the low bit. |
16546 | ||
df58fc94 RS |
16547 | For simplicity, we deal with (3)-(4) by not reducing _any_ relocation |
16548 | against a MIPS16 symbol. We deal with (5) by by not reducing any | |
16549 | such relocations on REL targets. | |
b314ec0e RS |
16550 | |
16551 | We deal with (1)-(2) by saying that, if there's a R_MIPS16_26 | |
16552 | relocation against some symbol R, no relocation against R may be | |
16553 | reduced. (Note that this deals with (2) as well as (1) because | |
16554 | relocations against global symbols will never be reduced on ELF | |
16555 | targets.) This approach is a little simpler than trying to detect | |
16556 | stub sections, and gives the "all or nothing" per-symbol consistency | |
16557 | that we have for MIPS16 symbols. */ | |
f3ded42a | 16558 | if (fixp->fx_subsy == NULL |
30c09090 | 16559 | && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp->fx_addsy)) |
df58fc94 RS |
16560 | || *symbol_get_tc (fixp->fx_addsy) |
16561 | || (HAVE_IN_PLACE_ADDENDS | |
16562 | && ELF_ST_IS_MICROMIPS (S_GET_OTHER (fixp->fx_addsy)) | |
16563 | && jmp_reloc_p (fixp->fx_r_type)))) | |
252b5132 | 16564 | return 0; |
a161fe53 | 16565 | |
252b5132 RH |
16566 | return 1; |
16567 | } | |
16568 | ||
16569 | /* Translate internal representation of relocation info to BFD target | |
16570 | format. */ | |
16571 | ||
16572 | arelent ** | |
17a2f251 | 16573 | tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) |
252b5132 RH |
16574 | { |
16575 | static arelent *retval[4]; | |
16576 | arelent *reloc; | |
16577 | bfd_reloc_code_real_type code; | |
16578 | ||
4b0cff4e TS |
16579 | memset (retval, 0, sizeof(retval)); |
16580 | reloc = retval[0] = (arelent *) xcalloc (1, sizeof (arelent)); | |
49309057 ILT |
16581 | reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); |
16582 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
252b5132 RH |
16583 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; |
16584 | ||
bad36eac DJ |
16585 | if (fixp->fx_pcrel) |
16586 | { | |
df58fc94 RS |
16587 | gas_assert (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2 |
16588 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1 | |
16589 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1 | |
b47468a6 CM |
16590 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1 |
16591 | || fixp->fx_r_type == BFD_RELOC_32_PCREL); | |
bad36eac DJ |
16592 | |
16593 | /* At this point, fx_addnumber is "symbol offset - pcrel address". | |
16594 | Relocations want only the symbol offset. */ | |
16595 | reloc->addend = fixp->fx_addnumber + reloc->address; | |
bad36eac DJ |
16596 | } |
16597 | else | |
16598 | reloc->addend = fixp->fx_addnumber; | |
252b5132 | 16599 | |
438c16b8 TS |
16600 | /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable |
16601 | entry to be used in the relocation's section offset. */ | |
16602 | if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
252b5132 RH |
16603 | { |
16604 | reloc->address = reloc->addend; | |
16605 | reloc->addend = 0; | |
16606 | } | |
16607 | ||
252b5132 | 16608 | code = fixp->fx_r_type; |
252b5132 | 16609 | |
bad36eac | 16610 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); |
252b5132 RH |
16611 | if (reloc->howto == NULL) |
16612 | { | |
16613 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
1661c76c RS |
16614 | _("cannot represent %s relocation in this object file" |
16615 | " format"), | |
252b5132 RH |
16616 | bfd_get_reloc_code_name (code)); |
16617 | retval[0] = NULL; | |
16618 | } | |
16619 | ||
16620 | return retval; | |
16621 | } | |
16622 | ||
16623 | /* Relax a machine dependent frag. This returns the amount by which | |
16624 | the current size of the frag should change. */ | |
16625 | ||
16626 | int | |
17a2f251 | 16627 | mips_relax_frag (asection *sec, fragS *fragp, long stretch) |
252b5132 | 16628 | { |
4a6a3df4 AO |
16629 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
16630 | { | |
16631 | offsetT old_var = fragp->fr_var; | |
b34976b6 AM |
16632 | |
16633 | fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE); | |
4a6a3df4 AO |
16634 | |
16635 | return fragp->fr_var - old_var; | |
16636 | } | |
16637 | ||
df58fc94 RS |
16638 | if (RELAX_MICROMIPS_P (fragp->fr_subtype)) |
16639 | { | |
16640 | offsetT old_var = fragp->fr_var; | |
16641 | offsetT new_var = 4; | |
16642 | ||
16643 | if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0) | |
16644 | new_var = relaxed_micromips_16bit_branch_length (fragp, sec, TRUE); | |
16645 | if (new_var == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)) | |
16646 | new_var = relaxed_micromips_32bit_branch_length (fragp, sec, TRUE); | |
16647 | fragp->fr_var = new_var; | |
16648 | ||
16649 | return new_var - old_var; | |
16650 | } | |
16651 | ||
252b5132 RH |
16652 | if (! RELAX_MIPS16_P (fragp->fr_subtype)) |
16653 | return 0; | |
16654 | ||
c4e7957c | 16655 | if (mips16_extended_frag (fragp, NULL, stretch)) |
252b5132 RH |
16656 | { |
16657 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
16658 | return 0; | |
16659 | fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype); | |
16660 | return 2; | |
16661 | } | |
16662 | else | |
16663 | { | |
16664 | if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
16665 | return 0; | |
16666 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype); | |
16667 | return -2; | |
16668 | } | |
16669 | ||
16670 | return 0; | |
16671 | } | |
16672 | ||
16673 | /* Convert a machine dependent frag. */ | |
16674 | ||
16675 | void | |
17a2f251 | 16676 | md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp) |
252b5132 | 16677 | { |
4a6a3df4 AO |
16678 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
16679 | { | |
4d68580a | 16680 | char *buf; |
4a6a3df4 AO |
16681 | unsigned long insn; |
16682 | expressionS exp; | |
16683 | fixS *fixp; | |
b34976b6 | 16684 | |
4d68580a RS |
16685 | buf = fragp->fr_literal + fragp->fr_fix; |
16686 | insn = read_insn (buf); | |
b34976b6 | 16687 | |
4a6a3df4 AO |
16688 | if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) |
16689 | { | |
16690 | /* We generate a fixup instead of applying it right now | |
16691 | because, if there are linker relaxations, we're going to | |
16692 | need the relocations. */ | |
16693 | exp.X_op = O_symbol; | |
16694 | exp.X_add_symbol = fragp->fr_symbol; | |
16695 | exp.X_add_number = fragp->fr_offset; | |
16696 | ||
4d68580a RS |
16697 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, TRUE, |
16698 | BFD_RELOC_16_PCREL_S2); | |
4a6a3df4 AO |
16699 | fixp->fx_file = fragp->fr_file; |
16700 | fixp->fx_line = fragp->fr_line; | |
b34976b6 | 16701 | |
4d68580a | 16702 | buf = write_insn (buf, insn); |
4a6a3df4 AO |
16703 | } |
16704 | else | |
16705 | { | |
16706 | int i; | |
16707 | ||
16708 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
1661c76c | 16709 | _("relaxed out-of-range branch into a jump")); |
4a6a3df4 AO |
16710 | |
16711 | if (RELAX_BRANCH_UNCOND (fragp->fr_subtype)) | |
16712 | goto uncond; | |
16713 | ||
16714 | if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
16715 | { | |
16716 | /* Reverse the branch. */ | |
16717 | switch ((insn >> 28) & 0xf) | |
16718 | { | |
16719 | case 4: | |
56d438b1 CF |
16720 | if ((insn & 0xff000000) == 0x47000000 |
16721 | || (insn & 0xff600000) == 0x45600000) | |
16722 | { | |
16723 | /* BZ.df/BNZ.df, BZ.V/BNZ.V can have the condition | |
16724 | reversed by tweaking bit 23. */ | |
16725 | insn ^= 0x00800000; | |
16726 | } | |
16727 | else | |
16728 | { | |
16729 | /* bc[0-3][tf]l? instructions can have the condition | |
16730 | reversed by tweaking a single TF bit, and their | |
16731 | opcodes all have 0x4???????. */ | |
16732 | gas_assert ((insn & 0xf3e00000) == 0x41000000); | |
16733 | insn ^= 0x00010000; | |
16734 | } | |
4a6a3df4 AO |
16735 | break; |
16736 | ||
16737 | case 0: | |
16738 | /* bltz 0x04000000 bgez 0x04010000 | |
54f4ddb3 | 16739 | bltzal 0x04100000 bgezal 0x04110000 */ |
9c2799c2 | 16740 | gas_assert ((insn & 0xfc0e0000) == 0x04000000); |
4a6a3df4 AO |
16741 | insn ^= 0x00010000; |
16742 | break; | |
b34976b6 | 16743 | |
4a6a3df4 AO |
16744 | case 1: |
16745 | /* beq 0x10000000 bne 0x14000000 | |
54f4ddb3 | 16746 | blez 0x18000000 bgtz 0x1c000000 */ |
4a6a3df4 AO |
16747 | insn ^= 0x04000000; |
16748 | break; | |
16749 | ||
16750 | default: | |
16751 | abort (); | |
16752 | } | |
16753 | } | |
16754 | ||
16755 | if (RELAX_BRANCH_LINK (fragp->fr_subtype)) | |
16756 | { | |
16757 | /* Clear the and-link bit. */ | |
9c2799c2 | 16758 | gas_assert ((insn & 0xfc1c0000) == 0x04100000); |
4a6a3df4 | 16759 | |
54f4ddb3 TS |
16760 | /* bltzal 0x04100000 bgezal 0x04110000 |
16761 | bltzall 0x04120000 bgezall 0x04130000 */ | |
4a6a3df4 AO |
16762 | insn &= ~0x00100000; |
16763 | } | |
16764 | ||
16765 | /* Branch over the branch (if the branch was likely) or the | |
16766 | full jump (not likely case). Compute the offset from the | |
16767 | current instruction to branch to. */ | |
16768 | if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
16769 | i = 16; | |
16770 | else | |
16771 | { | |
16772 | /* How many bytes in instructions we've already emitted? */ | |
4d68580a | 16773 | i = buf - fragp->fr_literal - fragp->fr_fix; |
4a6a3df4 AO |
16774 | /* How many bytes in instructions from here to the end? */ |
16775 | i = fragp->fr_var - i; | |
16776 | } | |
16777 | /* Convert to instruction count. */ | |
16778 | i >>= 2; | |
16779 | /* Branch counts from the next instruction. */ | |
b34976b6 | 16780 | i--; |
4a6a3df4 AO |
16781 | insn |= i; |
16782 | /* Branch over the jump. */ | |
4d68580a | 16783 | buf = write_insn (buf, insn); |
4a6a3df4 | 16784 | |
54f4ddb3 | 16785 | /* nop */ |
4d68580a | 16786 | buf = write_insn (buf, 0); |
4a6a3df4 AO |
16787 | |
16788 | if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
16789 | { | |
16790 | /* beql $0, $0, 2f */ | |
16791 | insn = 0x50000000; | |
16792 | /* Compute the PC offset from the current instruction to | |
16793 | the end of the variable frag. */ | |
16794 | /* How many bytes in instructions we've already emitted? */ | |
4d68580a | 16795 | i = buf - fragp->fr_literal - fragp->fr_fix; |
4a6a3df4 AO |
16796 | /* How many bytes in instructions from here to the end? */ |
16797 | i = fragp->fr_var - i; | |
16798 | /* Convert to instruction count. */ | |
16799 | i >>= 2; | |
16800 | /* Don't decrement i, because we want to branch over the | |
16801 | delay slot. */ | |
4a6a3df4 | 16802 | insn |= i; |
4a6a3df4 | 16803 | |
4d68580a RS |
16804 | buf = write_insn (buf, insn); |
16805 | buf = write_insn (buf, 0); | |
4a6a3df4 AO |
16806 | } |
16807 | ||
16808 | uncond: | |
16809 | if (mips_pic == NO_PIC) | |
16810 | { | |
16811 | /* j or jal. */ | |
16812 | insn = (RELAX_BRANCH_LINK (fragp->fr_subtype) | |
16813 | ? 0x0c000000 : 0x08000000); | |
16814 | exp.X_op = O_symbol; | |
16815 | exp.X_add_symbol = fragp->fr_symbol; | |
16816 | exp.X_add_number = fragp->fr_offset; | |
16817 | ||
4d68580a RS |
16818 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, |
16819 | FALSE, BFD_RELOC_MIPS_JMP); | |
4a6a3df4 AO |
16820 | fixp->fx_file = fragp->fr_file; |
16821 | fixp->fx_line = fragp->fr_line; | |
16822 | ||
4d68580a | 16823 | buf = write_insn (buf, insn); |
4a6a3df4 AO |
16824 | } |
16825 | else | |
16826 | { | |
66b3e8da MR |
16827 | unsigned long at = RELAX_BRANCH_AT (fragp->fr_subtype); |
16828 | ||
4a6a3df4 | 16829 | /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */ |
66b3e8da MR |
16830 | insn = HAVE_64BIT_ADDRESSES ? 0xdf800000 : 0x8f800000; |
16831 | insn |= at << OP_SH_RT; | |
4a6a3df4 AO |
16832 | exp.X_op = O_symbol; |
16833 | exp.X_add_symbol = fragp->fr_symbol; | |
16834 | exp.X_add_number = fragp->fr_offset; | |
16835 | ||
16836 | if (fragp->fr_offset) | |
16837 | { | |
16838 | exp.X_add_symbol = make_expr_symbol (&exp); | |
16839 | exp.X_add_number = 0; | |
16840 | } | |
16841 | ||
4d68580a RS |
16842 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, |
16843 | FALSE, BFD_RELOC_MIPS_GOT16); | |
4a6a3df4 AO |
16844 | fixp->fx_file = fragp->fr_file; |
16845 | fixp->fx_line = fragp->fr_line; | |
16846 | ||
4d68580a | 16847 | buf = write_insn (buf, insn); |
b34976b6 | 16848 | |
4a6a3df4 | 16849 | if (mips_opts.isa == ISA_MIPS1) |
4d68580a RS |
16850 | /* nop */ |
16851 | buf = write_insn (buf, 0); | |
4a6a3df4 AO |
16852 | |
16853 | /* d/addiu $at, $at, <sym> R_MIPS_LO16 */ | |
66b3e8da MR |
16854 | insn = HAVE_64BIT_ADDRESSES ? 0x64000000 : 0x24000000; |
16855 | insn |= at << OP_SH_RS | at << OP_SH_RT; | |
4a6a3df4 | 16856 | |
4d68580a RS |
16857 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, |
16858 | FALSE, BFD_RELOC_LO16); | |
4a6a3df4 AO |
16859 | fixp->fx_file = fragp->fr_file; |
16860 | fixp->fx_line = fragp->fr_line; | |
b34976b6 | 16861 | |
4d68580a | 16862 | buf = write_insn (buf, insn); |
4a6a3df4 AO |
16863 | |
16864 | /* j(al)r $at. */ | |
16865 | if (RELAX_BRANCH_LINK (fragp->fr_subtype)) | |
66b3e8da | 16866 | insn = 0x0000f809; |
4a6a3df4 | 16867 | else |
66b3e8da MR |
16868 | insn = 0x00000008; |
16869 | insn |= at << OP_SH_RS; | |
4a6a3df4 | 16870 | |
4d68580a | 16871 | buf = write_insn (buf, insn); |
4a6a3df4 AO |
16872 | } |
16873 | } | |
16874 | ||
4a6a3df4 | 16875 | fragp->fr_fix += fragp->fr_var; |
4d68580a | 16876 | gas_assert (buf == fragp->fr_literal + fragp->fr_fix); |
4a6a3df4 AO |
16877 | return; |
16878 | } | |
16879 | ||
df58fc94 RS |
16880 | /* Relax microMIPS branches. */ |
16881 | if (RELAX_MICROMIPS_P (fragp->fr_subtype)) | |
16882 | { | |
4d68580a | 16883 | char *buf = fragp->fr_literal + fragp->fr_fix; |
df58fc94 RS |
16884 | bfd_boolean compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype); |
16885 | bfd_boolean al = RELAX_MICROMIPS_LINK (fragp->fr_subtype); | |
16886 | int type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype); | |
2309ddf2 | 16887 | bfd_boolean short_ds; |
df58fc94 RS |
16888 | unsigned long insn; |
16889 | expressionS exp; | |
16890 | fixS *fixp; | |
16891 | ||
16892 | exp.X_op = O_symbol; | |
16893 | exp.X_add_symbol = fragp->fr_symbol; | |
16894 | exp.X_add_number = fragp->fr_offset; | |
16895 | ||
16896 | fragp->fr_fix += fragp->fr_var; | |
16897 | ||
16898 | /* Handle 16-bit branches that fit or are forced to fit. */ | |
16899 | if (type != 0 && !RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype)) | |
16900 | { | |
16901 | /* We generate a fixup instead of applying it right now, | |
16902 | because if there is linker relaxation, we're going to | |
16903 | need the relocations. */ | |
16904 | if (type == 'D') | |
4d68580a | 16905 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 2, &exp, TRUE, |
df58fc94 RS |
16906 | BFD_RELOC_MICROMIPS_10_PCREL_S1); |
16907 | else if (type == 'E') | |
4d68580a | 16908 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 2, &exp, TRUE, |
df58fc94 RS |
16909 | BFD_RELOC_MICROMIPS_7_PCREL_S1); |
16910 | else | |
16911 | abort (); | |
16912 | ||
16913 | fixp->fx_file = fragp->fr_file; | |
16914 | fixp->fx_line = fragp->fr_line; | |
16915 | ||
16916 | /* These relocations can have an addend that won't fit in | |
16917 | 2 octets. */ | |
16918 | fixp->fx_no_overflow = 1; | |
16919 | ||
16920 | return; | |
16921 | } | |
16922 | ||
2309ddf2 | 16923 | /* Handle 32-bit branches that fit or are forced to fit. */ |
df58fc94 RS |
16924 | if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype) |
16925 | || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype)) | |
16926 | { | |
16927 | /* We generate a fixup instead of applying it right now, | |
16928 | because if there is linker relaxation, we're going to | |
16929 | need the relocations. */ | |
4d68580a RS |
16930 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, TRUE, |
16931 | BFD_RELOC_MICROMIPS_16_PCREL_S1); | |
df58fc94 RS |
16932 | fixp->fx_file = fragp->fr_file; |
16933 | fixp->fx_line = fragp->fr_line; | |
16934 | ||
16935 | if (type == 0) | |
16936 | return; | |
16937 | } | |
16938 | ||
16939 | /* Relax 16-bit branches to 32-bit branches. */ | |
16940 | if (type != 0) | |
16941 | { | |
4d68580a | 16942 | insn = read_compressed_insn (buf, 2); |
df58fc94 RS |
16943 | |
16944 | if ((insn & 0xfc00) == 0xcc00) /* b16 */ | |
16945 | insn = 0x94000000; /* beq */ | |
16946 | else if ((insn & 0xdc00) == 0x8c00) /* beqz16/bnez16 */ | |
16947 | { | |
16948 | unsigned long regno; | |
16949 | ||
16950 | regno = (insn >> MICROMIPSOP_SH_MD) & MICROMIPSOP_MASK_MD; | |
16951 | regno = micromips_to_32_reg_d_map [regno]; | |
16952 | insn = ((insn & 0x2000) << 16) | 0x94000000; /* beq/bne */ | |
16953 | insn |= regno << MICROMIPSOP_SH_RS; | |
16954 | } | |
16955 | else | |
16956 | abort (); | |
16957 | ||
16958 | /* Nothing else to do, just write it out. */ | |
16959 | if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype) | |
16960 | || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype)) | |
16961 | { | |
4d68580a RS |
16962 | buf = write_compressed_insn (buf, insn, 4); |
16963 | gas_assert (buf == fragp->fr_literal + fragp->fr_fix); | |
df58fc94 RS |
16964 | return; |
16965 | } | |
16966 | } | |
16967 | else | |
4d68580a | 16968 | insn = read_compressed_insn (buf, 4); |
df58fc94 RS |
16969 | |
16970 | /* Relax 32-bit branches to a sequence of instructions. */ | |
16971 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
1661c76c | 16972 | _("relaxed out-of-range branch into a jump")); |
df58fc94 | 16973 | |
2309ddf2 MR |
16974 | /* Set the short-delay-slot bit. */ |
16975 | short_ds = al && (insn & 0x02000000) != 0; | |
df58fc94 RS |
16976 | |
16977 | if (!RELAX_MICROMIPS_UNCOND (fragp->fr_subtype)) | |
16978 | { | |
16979 | symbolS *l; | |
16980 | ||
16981 | /* Reverse the branch. */ | |
16982 | if ((insn & 0xfc000000) == 0x94000000 /* beq */ | |
16983 | || (insn & 0xfc000000) == 0xb4000000) /* bne */ | |
16984 | insn ^= 0x20000000; | |
16985 | else if ((insn & 0xffe00000) == 0x40000000 /* bltz */ | |
16986 | || (insn & 0xffe00000) == 0x40400000 /* bgez */ | |
16987 | || (insn & 0xffe00000) == 0x40800000 /* blez */ | |
16988 | || (insn & 0xffe00000) == 0x40c00000 /* bgtz */ | |
16989 | || (insn & 0xffe00000) == 0x40a00000 /* bnezc */ | |
16990 | || (insn & 0xffe00000) == 0x40e00000 /* beqzc */ | |
16991 | || (insn & 0xffe00000) == 0x40200000 /* bltzal */ | |
16992 | || (insn & 0xffe00000) == 0x40600000 /* bgezal */ | |
16993 | || (insn & 0xffe00000) == 0x42200000 /* bltzals */ | |
16994 | || (insn & 0xffe00000) == 0x42600000) /* bgezals */ | |
16995 | insn ^= 0x00400000; | |
16996 | else if ((insn & 0xffe30000) == 0x43800000 /* bc1f */ | |
16997 | || (insn & 0xffe30000) == 0x43a00000 /* bc1t */ | |
16998 | || (insn & 0xffe30000) == 0x42800000 /* bc2f */ | |
16999 | || (insn & 0xffe30000) == 0x42a00000) /* bc2t */ | |
17000 | insn ^= 0x00200000; | |
56d438b1 CF |
17001 | else if ((insn & 0xff000000) == 0x83000000 /* BZ.df |
17002 | BNZ.df */ | |
17003 | || (insn & 0xff600000) == 0x81600000) /* BZ.V | |
17004 | BNZ.V */ | |
17005 | insn ^= 0x00800000; | |
df58fc94 RS |
17006 | else |
17007 | abort (); | |
17008 | ||
17009 | if (al) | |
17010 | { | |
17011 | /* Clear the and-link and short-delay-slot bits. */ | |
17012 | gas_assert ((insn & 0xfda00000) == 0x40200000); | |
17013 | ||
17014 | /* bltzal 0x40200000 bgezal 0x40600000 */ | |
17015 | /* bltzals 0x42200000 bgezals 0x42600000 */ | |
17016 | insn &= ~0x02200000; | |
17017 | } | |
17018 | ||
17019 | /* Make a label at the end for use with the branch. */ | |
17020 | l = symbol_new (micromips_label_name (), asec, fragp->fr_fix, fragp); | |
17021 | micromips_label_inc (); | |
f3ded42a | 17022 | S_SET_OTHER (l, ELF_ST_SET_MICROMIPS (S_GET_OTHER (l))); |
df58fc94 RS |
17023 | |
17024 | /* Refer to it. */ | |
4d68580a RS |
17025 | fixp = fix_new (fragp, buf - fragp->fr_literal, 4, l, 0, TRUE, |
17026 | BFD_RELOC_MICROMIPS_16_PCREL_S1); | |
df58fc94 RS |
17027 | fixp->fx_file = fragp->fr_file; |
17028 | fixp->fx_line = fragp->fr_line; | |
17029 | ||
17030 | /* Branch over the jump. */ | |
4d68580a | 17031 | buf = write_compressed_insn (buf, insn, 4); |
df58fc94 | 17032 | if (!compact) |
4d68580a RS |
17033 | /* nop */ |
17034 | buf = write_compressed_insn (buf, 0x0c00, 2); | |
df58fc94 RS |
17035 | } |
17036 | ||
17037 | if (mips_pic == NO_PIC) | |
17038 | { | |
2309ddf2 MR |
17039 | unsigned long jal = short_ds ? 0x74000000 : 0xf4000000; /* jal/s */ |
17040 | ||
df58fc94 RS |
17041 | /* j/jal/jals <sym> R_MICROMIPS_26_S1 */ |
17042 | insn = al ? jal : 0xd4000000; | |
17043 | ||
4d68580a RS |
17044 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE, |
17045 | BFD_RELOC_MICROMIPS_JMP); | |
df58fc94 RS |
17046 | fixp->fx_file = fragp->fr_file; |
17047 | fixp->fx_line = fragp->fr_line; | |
17048 | ||
4d68580a | 17049 | buf = write_compressed_insn (buf, insn, 4); |
df58fc94 | 17050 | if (compact) |
4d68580a RS |
17051 | /* nop */ |
17052 | buf = write_compressed_insn (buf, 0x0c00, 2); | |
df58fc94 RS |
17053 | } |
17054 | else | |
17055 | { | |
17056 | unsigned long at = RELAX_MICROMIPS_AT (fragp->fr_subtype); | |
2309ddf2 MR |
17057 | unsigned long jalr = short_ds ? 0x45e0 : 0x45c0; /* jalr/s */ |
17058 | unsigned long jr = compact ? 0x45a0 : 0x4580; /* jr/c */ | |
df58fc94 RS |
17059 | |
17060 | /* lw/ld $at, <sym>($gp) R_MICROMIPS_GOT16 */ | |
17061 | insn = HAVE_64BIT_ADDRESSES ? 0xdc1c0000 : 0xfc1c0000; | |
17062 | insn |= at << MICROMIPSOP_SH_RT; | |
17063 | ||
17064 | if (exp.X_add_number) | |
17065 | { | |
17066 | exp.X_add_symbol = make_expr_symbol (&exp); | |
17067 | exp.X_add_number = 0; | |
17068 | } | |
17069 | ||
4d68580a RS |
17070 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE, |
17071 | BFD_RELOC_MICROMIPS_GOT16); | |
df58fc94 RS |
17072 | fixp->fx_file = fragp->fr_file; |
17073 | fixp->fx_line = fragp->fr_line; | |
17074 | ||
4d68580a | 17075 | buf = write_compressed_insn (buf, insn, 4); |
df58fc94 RS |
17076 | |
17077 | /* d/addiu $at, $at, <sym> R_MICROMIPS_LO16 */ | |
17078 | insn = HAVE_64BIT_ADDRESSES ? 0x5c000000 : 0x30000000; | |
17079 | insn |= at << MICROMIPSOP_SH_RT | at << MICROMIPSOP_SH_RS; | |
17080 | ||
4d68580a RS |
17081 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE, |
17082 | BFD_RELOC_MICROMIPS_LO16); | |
df58fc94 RS |
17083 | fixp->fx_file = fragp->fr_file; |
17084 | fixp->fx_line = fragp->fr_line; | |
17085 | ||
4d68580a | 17086 | buf = write_compressed_insn (buf, insn, 4); |
df58fc94 RS |
17087 | |
17088 | /* jr/jrc/jalr/jalrs $at */ | |
17089 | insn = al ? jalr : jr; | |
17090 | insn |= at << MICROMIPSOP_SH_MJ; | |
17091 | ||
4d68580a | 17092 | buf = write_compressed_insn (buf, insn, 2); |
df58fc94 RS |
17093 | } |
17094 | ||
4d68580a | 17095 | gas_assert (buf == fragp->fr_literal + fragp->fr_fix); |
df58fc94 RS |
17096 | return; |
17097 | } | |
17098 | ||
252b5132 RH |
17099 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
17100 | { | |
17101 | int type; | |
3ccad066 | 17102 | const struct mips_int_operand *operand; |
252b5132 | 17103 | offsetT val; |
5c04167a RS |
17104 | char *buf; |
17105 | unsigned int user_length, length; | |
252b5132 | 17106 | unsigned long insn; |
5c04167a | 17107 | bfd_boolean ext; |
252b5132 RH |
17108 | |
17109 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
3ccad066 | 17110 | operand = mips16_immed_operand (type, FALSE); |
252b5132 | 17111 | |
5c04167a | 17112 | ext = RELAX_MIPS16_EXTENDED (fragp->fr_subtype); |
5f5f22c0 | 17113 | val = resolve_symbol_value (fragp->fr_symbol); |
3ccad066 | 17114 | if (operand->root.type == OP_PCREL) |
252b5132 | 17115 | { |
3ccad066 | 17116 | const struct mips_pcrel_operand *pcrel_op; |
252b5132 RH |
17117 | addressT addr; |
17118 | ||
3ccad066 | 17119 | pcrel_op = (const struct mips_pcrel_operand *) operand; |
252b5132 RH |
17120 | addr = fragp->fr_address + fragp->fr_fix; |
17121 | ||
17122 | /* The rules for the base address of a PC relative reloc are | |
17123 | complicated; see mips16_extended_frag. */ | |
3ccad066 | 17124 | if (pcrel_op->include_isa_bit) |
252b5132 RH |
17125 | { |
17126 | addr += 2; | |
17127 | if (ext) | |
17128 | addr += 2; | |
17129 | /* Ignore the low bit in the target, since it will be | |
17130 | set for a text label. */ | |
3ccad066 | 17131 | val &= -2; |
252b5132 RH |
17132 | } |
17133 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) | |
17134 | addr -= 4; | |
17135 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
17136 | addr -= 2; | |
17137 | ||
3ccad066 | 17138 | addr &= -(1 << pcrel_op->align_log2); |
252b5132 RH |
17139 | val -= addr; |
17140 | ||
17141 | /* Make sure the section winds up with the alignment we have | |
17142 | assumed. */ | |
3ccad066 RS |
17143 | if (operand->shift > 0) |
17144 | record_alignment (asec, operand->shift); | |
252b5132 RH |
17145 | } |
17146 | ||
17147 | if (ext | |
17148 | && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype) | |
17149 | || RELAX_MIPS16_DSLOT (fragp->fr_subtype))) | |
17150 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
17151 | _("extended instruction in delay slot")); | |
17152 | ||
5c04167a | 17153 | buf = fragp->fr_literal + fragp->fr_fix; |
252b5132 | 17154 | |
4d68580a | 17155 | insn = read_compressed_insn (buf, 2); |
5c04167a RS |
17156 | if (ext) |
17157 | insn |= MIPS16_EXTEND; | |
252b5132 | 17158 | |
5c04167a RS |
17159 | if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype)) |
17160 | user_length = 4; | |
17161 | else if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype)) | |
17162 | user_length = 2; | |
17163 | else | |
17164 | user_length = 0; | |
17165 | ||
43c0598f | 17166 | mips16_immed (fragp->fr_file, fragp->fr_line, type, |
c150d1d2 | 17167 | BFD_RELOC_UNUSED, val, user_length, &insn); |
252b5132 | 17168 | |
5c04167a RS |
17169 | length = (ext ? 4 : 2); |
17170 | gas_assert (mips16_opcode_length (insn) == length); | |
17171 | write_compressed_insn (buf, insn, length); | |
17172 | fragp->fr_fix += length; | |
252b5132 RH |
17173 | } |
17174 | else | |
17175 | { | |
df58fc94 RS |
17176 | relax_substateT subtype = fragp->fr_subtype; |
17177 | bfd_boolean second_longer = (subtype & RELAX_SECOND_LONGER) != 0; | |
17178 | bfd_boolean use_second = (subtype & RELAX_USE_SECOND) != 0; | |
4d7206a2 RS |
17179 | int first, second; |
17180 | fixS *fixp; | |
252b5132 | 17181 | |
df58fc94 RS |
17182 | first = RELAX_FIRST (subtype); |
17183 | second = RELAX_SECOND (subtype); | |
4d7206a2 | 17184 | fixp = (fixS *) fragp->fr_opcode; |
252b5132 | 17185 | |
df58fc94 RS |
17186 | /* If the delay slot chosen does not match the size of the instruction, |
17187 | then emit a warning. */ | |
17188 | if ((!use_second && (subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0) | |
17189 | || (use_second && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0)) | |
17190 | { | |
17191 | relax_substateT s; | |
17192 | const char *msg; | |
17193 | ||
17194 | s = subtype & (RELAX_DELAY_SLOT_16BIT | |
17195 | | RELAX_DELAY_SLOT_SIZE_FIRST | |
17196 | | RELAX_DELAY_SLOT_SIZE_SECOND); | |
17197 | msg = macro_warning (s); | |
17198 | if (msg != NULL) | |
db9b2be4 | 17199 | as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg); |
df58fc94 RS |
17200 | subtype &= ~s; |
17201 | } | |
17202 | ||
584892a6 | 17203 | /* Possibly emit a warning if we've chosen the longer option. */ |
df58fc94 | 17204 | if (use_second == second_longer) |
584892a6 | 17205 | { |
df58fc94 RS |
17206 | relax_substateT s; |
17207 | const char *msg; | |
17208 | ||
17209 | s = (subtype | |
17210 | & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT)); | |
17211 | msg = macro_warning (s); | |
17212 | if (msg != NULL) | |
db9b2be4 | 17213 | as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg); |
df58fc94 | 17214 | subtype &= ~s; |
584892a6 RS |
17215 | } |
17216 | ||
4d7206a2 RS |
17217 | /* Go through all the fixups for the first sequence. Disable them |
17218 | (by marking them as done) if we're going to use the second | |
17219 | sequence instead. */ | |
17220 | while (fixp | |
17221 | && fixp->fx_frag == fragp | |
17222 | && fixp->fx_where < fragp->fr_fix - second) | |
17223 | { | |
df58fc94 | 17224 | if (subtype & RELAX_USE_SECOND) |
4d7206a2 RS |
17225 | fixp->fx_done = 1; |
17226 | fixp = fixp->fx_next; | |
17227 | } | |
252b5132 | 17228 | |
4d7206a2 RS |
17229 | /* Go through the fixups for the second sequence. Disable them if |
17230 | we're going to use the first sequence, otherwise adjust their | |
17231 | addresses to account for the relaxation. */ | |
17232 | while (fixp && fixp->fx_frag == fragp) | |
17233 | { | |
df58fc94 | 17234 | if (subtype & RELAX_USE_SECOND) |
4d7206a2 RS |
17235 | fixp->fx_where -= first; |
17236 | else | |
17237 | fixp->fx_done = 1; | |
17238 | fixp = fixp->fx_next; | |
17239 | } | |
17240 | ||
17241 | /* Now modify the frag contents. */ | |
df58fc94 | 17242 | if (subtype & RELAX_USE_SECOND) |
4d7206a2 RS |
17243 | { |
17244 | char *start; | |
17245 | ||
17246 | start = fragp->fr_literal + fragp->fr_fix - first - second; | |
17247 | memmove (start, start + first, second); | |
17248 | fragp->fr_fix -= first; | |
17249 | } | |
17250 | else | |
17251 | fragp->fr_fix -= second; | |
252b5132 RH |
17252 | } |
17253 | } | |
17254 | ||
252b5132 RH |
17255 | /* This function is called after the relocs have been generated. |
17256 | We've been storing mips16 text labels as odd. Here we convert them | |
17257 | back to even for the convenience of the debugger. */ | |
17258 | ||
17259 | void | |
17a2f251 | 17260 | mips_frob_file_after_relocs (void) |
252b5132 RH |
17261 | { |
17262 | asymbol **syms; | |
17263 | unsigned int count, i; | |
17264 | ||
252b5132 RH |
17265 | syms = bfd_get_outsymbols (stdoutput); |
17266 | count = bfd_get_symcount (stdoutput); | |
17267 | for (i = 0; i < count; i++, syms++) | |
df58fc94 RS |
17268 | if (ELF_ST_IS_COMPRESSED (elf_symbol (*syms)->internal_elf_sym.st_other) |
17269 | && ((*syms)->value & 1) != 0) | |
17270 | { | |
17271 | (*syms)->value &= ~1; | |
17272 | /* If the symbol has an odd size, it was probably computed | |
17273 | incorrectly, so adjust that as well. */ | |
17274 | if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0) | |
17275 | ++elf_symbol (*syms)->internal_elf_sym.st_size; | |
17276 | } | |
252b5132 RH |
17277 | } |
17278 | ||
a1facbec MR |
17279 | /* This function is called whenever a label is defined, including fake |
17280 | labels instantiated off the dot special symbol. It is used when | |
17281 | handling branch delays; if a branch has a label, we assume we cannot | |
17282 | move it. This also bumps the value of the symbol by 1 in compressed | |
17283 | code. */ | |
252b5132 | 17284 | |
e1b47bd5 | 17285 | static void |
a1facbec | 17286 | mips_record_label (symbolS *sym) |
252b5132 | 17287 | { |
a8dbcb85 | 17288 | segment_info_type *si = seg_info (now_seg); |
252b5132 RH |
17289 | struct insn_label_list *l; |
17290 | ||
17291 | if (free_insn_labels == NULL) | |
17292 | l = (struct insn_label_list *) xmalloc (sizeof *l); | |
17293 | else | |
17294 | { | |
17295 | l = free_insn_labels; | |
17296 | free_insn_labels = l->next; | |
17297 | } | |
17298 | ||
17299 | l->label = sym; | |
a8dbcb85 TS |
17300 | l->next = si->label_list; |
17301 | si->label_list = l; | |
a1facbec | 17302 | } |
07a53e5c | 17303 | |
a1facbec MR |
17304 | /* This function is called as tc_frob_label() whenever a label is defined |
17305 | and adds a DWARF-2 record we only want for true labels. */ | |
17306 | ||
17307 | void | |
17308 | mips_define_label (symbolS *sym) | |
17309 | { | |
17310 | mips_record_label (sym); | |
07a53e5c | 17311 | dwarf2_emit_label (sym); |
252b5132 | 17312 | } |
e1b47bd5 RS |
17313 | |
17314 | /* This function is called by tc_new_dot_label whenever a new dot symbol | |
17315 | is defined. */ | |
17316 | ||
17317 | void | |
17318 | mips_add_dot_label (symbolS *sym) | |
17319 | { | |
17320 | mips_record_label (sym); | |
17321 | if (mips_assembling_insn && HAVE_CODE_COMPRESSION) | |
17322 | mips_compressed_mark_label (sym); | |
17323 | } | |
252b5132 | 17324 | \f |
252b5132 RH |
17325 | /* Some special processing for a MIPS ELF file. */ |
17326 | ||
17327 | void | |
17a2f251 | 17328 | mips_elf_final_processing (void) |
252b5132 RH |
17329 | { |
17330 | /* Write out the register information. */ | |
316f5878 | 17331 | if (mips_abi != N64_ABI) |
252b5132 RH |
17332 | { |
17333 | Elf32_RegInfo s; | |
17334 | ||
17335 | s.ri_gprmask = mips_gprmask; | |
17336 | s.ri_cprmask[0] = mips_cprmask[0]; | |
17337 | s.ri_cprmask[1] = mips_cprmask[1]; | |
17338 | s.ri_cprmask[2] = mips_cprmask[2]; | |
17339 | s.ri_cprmask[3] = mips_cprmask[3]; | |
17340 | /* The gp_value field is set by the MIPS ELF backend. */ | |
17341 | ||
17342 | bfd_mips_elf32_swap_reginfo_out (stdoutput, &s, | |
17343 | ((Elf32_External_RegInfo *) | |
17344 | mips_regmask_frag)); | |
17345 | } | |
17346 | else | |
17347 | { | |
17348 | Elf64_Internal_RegInfo s; | |
17349 | ||
17350 | s.ri_gprmask = mips_gprmask; | |
17351 | s.ri_pad = 0; | |
17352 | s.ri_cprmask[0] = mips_cprmask[0]; | |
17353 | s.ri_cprmask[1] = mips_cprmask[1]; | |
17354 | s.ri_cprmask[2] = mips_cprmask[2]; | |
17355 | s.ri_cprmask[3] = mips_cprmask[3]; | |
17356 | /* The gp_value field is set by the MIPS ELF backend. */ | |
17357 | ||
17358 | bfd_mips_elf64_swap_reginfo_out (stdoutput, &s, | |
17359 | ((Elf64_External_RegInfo *) | |
17360 | mips_regmask_frag)); | |
17361 | } | |
17362 | ||
17363 | /* Set the MIPS ELF flag bits. FIXME: There should probably be some | |
17364 | sort of BFD interface for this. */ | |
17365 | if (mips_any_noreorder) | |
17366 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER; | |
17367 | if (mips_pic != NO_PIC) | |
143d77c5 | 17368 | { |
8b828383 | 17369 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC; |
143d77c5 EC |
17370 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC; |
17371 | } | |
17372 | if (mips_abicalls) | |
17373 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC; | |
252b5132 | 17374 | |
b015e599 AP |
17375 | /* Set MIPS ELF flags for ASEs. Note that not all ASEs have flags |
17376 | defined at present; this might need to change in future. */ | |
a4672219 TS |
17377 | if (file_ase_mips16) |
17378 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16; | |
df58fc94 RS |
17379 | if (file_ase_micromips) |
17380 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MICROMIPS; | |
846ef2d0 | 17381 | if (file_ase & ASE_MDMX) |
deec1734 | 17382 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX; |
1f25f5d3 | 17383 | |
bdaaa2e1 | 17384 | /* Set the MIPS ELF ABI flags. */ |
316f5878 | 17385 | if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32) |
252b5132 | 17386 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32; |
316f5878 | 17387 | else if (mips_abi == O64_ABI) |
252b5132 | 17388 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64; |
316f5878 | 17389 | else if (mips_abi == EABI_ABI) |
252b5132 | 17390 | { |
bad1aba3 | 17391 | if (file_mips_opts.gp == 64) |
252b5132 RH |
17392 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64; |
17393 | else | |
17394 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32; | |
17395 | } | |
316f5878 | 17396 | else if (mips_abi == N32_ABI) |
be00bddd TS |
17397 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2; |
17398 | ||
c9914766 | 17399 | /* Nothing to do for N64_ABI. */ |
252b5132 RH |
17400 | |
17401 | if (mips_32bitmode) | |
17402 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE; | |
ad3fea08 | 17403 | |
ba92f887 MR |
17404 | if (mips_flag_nan2008) |
17405 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NAN2008; | |
17406 | ||
ad3fea08 | 17407 | /* 32 bit code with 64 bit FP registers. */ |
0b35dfee | 17408 | if (file_mips_opts.fp == 64 && ABI_NEEDS_32BIT_REGS (mips_abi)) |
f1c38003 | 17409 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_FP64; |
252b5132 | 17410 | } |
252b5132 | 17411 | \f |
beae10d5 | 17412 | typedef struct proc { |
9b2f1d35 EC |
17413 | symbolS *func_sym; |
17414 | symbolS *func_end_sym; | |
beae10d5 KH |
17415 | unsigned long reg_mask; |
17416 | unsigned long reg_offset; | |
17417 | unsigned long fpreg_mask; | |
17418 | unsigned long fpreg_offset; | |
17419 | unsigned long frame_offset; | |
17420 | unsigned long frame_reg; | |
17421 | unsigned long pc_reg; | |
17422 | } procS; | |
252b5132 RH |
17423 | |
17424 | static procS cur_proc; | |
17425 | static procS *cur_proc_ptr; | |
17426 | static int numprocs; | |
17427 | ||
df58fc94 RS |
17428 | /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1", a microMIPS nop |
17429 | as "2", and a normal nop as "0". */ | |
17430 | ||
17431 | #define NOP_OPCODE_MIPS 0 | |
17432 | #define NOP_OPCODE_MIPS16 1 | |
17433 | #define NOP_OPCODE_MICROMIPS 2 | |
742a56fe RS |
17434 | |
17435 | char | |
17436 | mips_nop_opcode (void) | |
17437 | { | |
df58fc94 RS |
17438 | if (seg_info (now_seg)->tc_segment_info_data.micromips) |
17439 | return NOP_OPCODE_MICROMIPS; | |
17440 | else if (seg_info (now_seg)->tc_segment_info_data.mips16) | |
17441 | return NOP_OPCODE_MIPS16; | |
17442 | else | |
17443 | return NOP_OPCODE_MIPS; | |
742a56fe RS |
17444 | } |
17445 | ||
df58fc94 RS |
17446 | /* Fill in an rs_align_code fragment. Unlike elsewhere we want to use |
17447 | 32-bit microMIPS NOPs here (if applicable). */ | |
a19d8eb0 | 17448 | |
0a9ef439 | 17449 | void |
17a2f251 | 17450 | mips_handle_align (fragS *fragp) |
a19d8eb0 | 17451 | { |
df58fc94 | 17452 | char nop_opcode; |
742a56fe | 17453 | char *p; |
c67a084a NC |
17454 | int bytes, size, excess; |
17455 | valueT opcode; | |
742a56fe | 17456 | |
0a9ef439 RH |
17457 | if (fragp->fr_type != rs_align_code) |
17458 | return; | |
17459 | ||
742a56fe | 17460 | p = fragp->fr_literal + fragp->fr_fix; |
df58fc94 RS |
17461 | nop_opcode = *p; |
17462 | switch (nop_opcode) | |
a19d8eb0 | 17463 | { |
df58fc94 RS |
17464 | case NOP_OPCODE_MICROMIPS: |
17465 | opcode = micromips_nop32_insn.insn_opcode; | |
17466 | size = 4; | |
17467 | break; | |
17468 | case NOP_OPCODE_MIPS16: | |
c67a084a NC |
17469 | opcode = mips16_nop_insn.insn_opcode; |
17470 | size = 2; | |
df58fc94 RS |
17471 | break; |
17472 | case NOP_OPCODE_MIPS: | |
17473 | default: | |
c67a084a NC |
17474 | opcode = nop_insn.insn_opcode; |
17475 | size = 4; | |
df58fc94 | 17476 | break; |
c67a084a | 17477 | } |
a19d8eb0 | 17478 | |
c67a084a NC |
17479 | bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix; |
17480 | excess = bytes % size; | |
df58fc94 RS |
17481 | |
17482 | /* Handle the leading part if we're not inserting a whole number of | |
17483 | instructions, and make it the end of the fixed part of the frag. | |
17484 | Try to fit in a short microMIPS NOP if applicable and possible, | |
17485 | and use zeroes otherwise. */ | |
17486 | gas_assert (excess < 4); | |
17487 | fragp->fr_fix += excess; | |
17488 | switch (excess) | |
c67a084a | 17489 | { |
df58fc94 RS |
17490 | case 3: |
17491 | *p++ = '\0'; | |
17492 | /* Fall through. */ | |
17493 | case 2: | |
833794fc | 17494 | if (nop_opcode == NOP_OPCODE_MICROMIPS && !mips_opts.insn32) |
df58fc94 | 17495 | { |
4d68580a | 17496 | p = write_compressed_insn (p, micromips_nop16_insn.insn_opcode, 2); |
df58fc94 RS |
17497 | break; |
17498 | } | |
17499 | *p++ = '\0'; | |
17500 | /* Fall through. */ | |
17501 | case 1: | |
17502 | *p++ = '\0'; | |
17503 | /* Fall through. */ | |
17504 | case 0: | |
17505 | break; | |
a19d8eb0 | 17506 | } |
c67a084a NC |
17507 | |
17508 | md_number_to_chars (p, opcode, size); | |
17509 | fragp->fr_var = size; | |
a19d8eb0 CP |
17510 | } |
17511 | ||
252b5132 | 17512 | static long |
17a2f251 | 17513 | get_number (void) |
252b5132 RH |
17514 | { |
17515 | int negative = 0; | |
17516 | long val = 0; | |
17517 | ||
17518 | if (*input_line_pointer == '-') | |
17519 | { | |
17520 | ++input_line_pointer; | |
17521 | negative = 1; | |
17522 | } | |
3882b010 | 17523 | if (!ISDIGIT (*input_line_pointer)) |
956cd1d6 | 17524 | as_bad (_("expected simple number")); |
252b5132 RH |
17525 | if (input_line_pointer[0] == '0') |
17526 | { | |
17527 | if (input_line_pointer[1] == 'x') | |
17528 | { | |
17529 | input_line_pointer += 2; | |
3882b010 | 17530 | while (ISXDIGIT (*input_line_pointer)) |
252b5132 RH |
17531 | { |
17532 | val <<= 4; | |
17533 | val |= hex_value (*input_line_pointer++); | |
17534 | } | |
17535 | return negative ? -val : val; | |
17536 | } | |
17537 | else | |
17538 | { | |
17539 | ++input_line_pointer; | |
3882b010 | 17540 | while (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
17541 | { |
17542 | val <<= 3; | |
17543 | val |= *input_line_pointer++ - '0'; | |
17544 | } | |
17545 | return negative ? -val : val; | |
17546 | } | |
17547 | } | |
3882b010 | 17548 | if (!ISDIGIT (*input_line_pointer)) |
252b5132 RH |
17549 | { |
17550 | printf (_(" *input_line_pointer == '%c' 0x%02x\n"), | |
17551 | *input_line_pointer, *input_line_pointer); | |
956cd1d6 | 17552 | as_warn (_("invalid number")); |
252b5132 RH |
17553 | return -1; |
17554 | } | |
3882b010 | 17555 | while (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
17556 | { |
17557 | val *= 10; | |
17558 | val += *input_line_pointer++ - '0'; | |
17559 | } | |
17560 | return negative ? -val : val; | |
17561 | } | |
17562 | ||
17563 | /* The .file directive; just like the usual .file directive, but there | |
c5dd6aab DJ |
17564 | is an initial number which is the ECOFF file index. In the non-ECOFF |
17565 | case .file implies DWARF-2. */ | |
17566 | ||
17567 | static void | |
17a2f251 | 17568 | s_mips_file (int x ATTRIBUTE_UNUSED) |
c5dd6aab | 17569 | { |
ecb4347a DJ |
17570 | static int first_file_directive = 0; |
17571 | ||
c5dd6aab DJ |
17572 | if (ECOFF_DEBUGGING) |
17573 | { | |
17574 | get_number (); | |
17575 | s_app_file (0); | |
17576 | } | |
17577 | else | |
ecb4347a DJ |
17578 | { |
17579 | char *filename; | |
17580 | ||
17581 | filename = dwarf2_directive_file (0); | |
17582 | ||
17583 | /* Versions of GCC up to 3.1 start files with a ".file" | |
17584 | directive even for stabs output. Make sure that this | |
17585 | ".file" is handled. Note that you need a version of GCC | |
17586 | after 3.1 in order to support DWARF-2 on MIPS. */ | |
17587 | if (filename != NULL && ! first_file_directive) | |
17588 | { | |
17589 | (void) new_logical_line (filename, -1); | |
c04f5787 | 17590 | s_app_file_string (filename, 0); |
ecb4347a DJ |
17591 | } |
17592 | first_file_directive = 1; | |
17593 | } | |
c5dd6aab DJ |
17594 | } |
17595 | ||
17596 | /* The .loc directive, implying DWARF-2. */ | |
252b5132 RH |
17597 | |
17598 | static void | |
17a2f251 | 17599 | s_mips_loc (int x ATTRIBUTE_UNUSED) |
252b5132 | 17600 | { |
c5dd6aab DJ |
17601 | if (!ECOFF_DEBUGGING) |
17602 | dwarf2_directive_loc (0); | |
252b5132 RH |
17603 | } |
17604 | ||
252b5132 RH |
17605 | /* The .end directive. */ |
17606 | ||
17607 | static void | |
17a2f251 | 17608 | s_mips_end (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
17609 | { |
17610 | symbolS *p; | |
252b5132 | 17611 | |
7a621144 DJ |
17612 | /* Following functions need their own .frame and .cprestore directives. */ |
17613 | mips_frame_reg_valid = 0; | |
17614 | mips_cprestore_valid = 0; | |
17615 | ||
252b5132 RH |
17616 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
17617 | { | |
17618 | p = get_symbol (); | |
17619 | demand_empty_rest_of_line (); | |
17620 | } | |
17621 | else | |
17622 | p = NULL; | |
17623 | ||
14949570 | 17624 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0) |
252b5132 RH |
17625 | as_warn (_(".end not in text section")); |
17626 | ||
17627 | if (!cur_proc_ptr) | |
17628 | { | |
1661c76c | 17629 | as_warn (_(".end directive without a preceding .ent directive")); |
252b5132 RH |
17630 | demand_empty_rest_of_line (); |
17631 | return; | |
17632 | } | |
17633 | ||
17634 | if (p != NULL) | |
17635 | { | |
9c2799c2 | 17636 | gas_assert (S_GET_NAME (p)); |
9b2f1d35 | 17637 | if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->func_sym))) |
1661c76c | 17638 | as_warn (_(".end symbol does not match .ent symbol")); |
ecb4347a DJ |
17639 | |
17640 | if (debug_type == DEBUG_STABS) | |
17641 | stabs_generate_asm_endfunc (S_GET_NAME (p), | |
17642 | S_GET_NAME (p)); | |
252b5132 RH |
17643 | } |
17644 | else | |
17645 | as_warn (_(".end directive missing or unknown symbol")); | |
17646 | ||
9b2f1d35 EC |
17647 | /* Create an expression to calculate the size of the function. */ |
17648 | if (p && cur_proc_ptr) | |
17649 | { | |
17650 | OBJ_SYMFIELD_TYPE *obj = symbol_get_obj (p); | |
17651 | expressionS *exp = xmalloc (sizeof (expressionS)); | |
17652 | ||
17653 | obj->size = exp; | |
17654 | exp->X_op = O_subtract; | |
17655 | exp->X_add_symbol = symbol_temp_new_now (); | |
17656 | exp->X_op_symbol = p; | |
17657 | exp->X_add_number = 0; | |
17658 | ||
17659 | cur_proc_ptr->func_end_sym = exp->X_add_symbol; | |
17660 | } | |
17661 | ||
ecb4347a | 17662 | /* Generate a .pdr section. */ |
f3ded42a | 17663 | if (!ECOFF_DEBUGGING && mips_flag_pdr) |
ecb4347a DJ |
17664 | { |
17665 | segT saved_seg = now_seg; | |
17666 | subsegT saved_subseg = now_subseg; | |
ecb4347a DJ |
17667 | expressionS exp; |
17668 | char *fragp; | |
252b5132 | 17669 | |
252b5132 | 17670 | #ifdef md_flush_pending_output |
ecb4347a | 17671 | md_flush_pending_output (); |
252b5132 RH |
17672 | #endif |
17673 | ||
9c2799c2 | 17674 | gas_assert (pdr_seg); |
ecb4347a | 17675 | subseg_set (pdr_seg, 0); |
252b5132 | 17676 | |
ecb4347a DJ |
17677 | /* Write the symbol. */ |
17678 | exp.X_op = O_symbol; | |
17679 | exp.X_add_symbol = p; | |
17680 | exp.X_add_number = 0; | |
17681 | emit_expr (&exp, 4); | |
252b5132 | 17682 | |
ecb4347a | 17683 | fragp = frag_more (7 * 4); |
252b5132 | 17684 | |
17a2f251 TS |
17685 | md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4); |
17686 | md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4); | |
17687 | md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4); | |
17688 | md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4); | |
17689 | md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4); | |
17690 | md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4); | |
17691 | md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4); | |
252b5132 | 17692 | |
ecb4347a DJ |
17693 | subseg_set (saved_seg, saved_subseg); |
17694 | } | |
252b5132 RH |
17695 | |
17696 | cur_proc_ptr = NULL; | |
17697 | } | |
17698 | ||
17699 | /* The .aent and .ent directives. */ | |
17700 | ||
17701 | static void | |
17a2f251 | 17702 | s_mips_ent (int aent) |
252b5132 | 17703 | { |
252b5132 | 17704 | symbolS *symbolP; |
252b5132 RH |
17705 | |
17706 | symbolP = get_symbol (); | |
17707 | if (*input_line_pointer == ',') | |
f9419b05 | 17708 | ++input_line_pointer; |
252b5132 | 17709 | SKIP_WHITESPACE (); |
3882b010 | 17710 | if (ISDIGIT (*input_line_pointer) |
d9a62219 | 17711 | || *input_line_pointer == '-') |
874e8986 | 17712 | get_number (); |
252b5132 | 17713 | |
14949570 | 17714 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0) |
1661c76c | 17715 | as_warn (_(".ent or .aent not in text section")); |
252b5132 RH |
17716 | |
17717 | if (!aent && cur_proc_ptr) | |
9a41af64 | 17718 | as_warn (_("missing .end")); |
252b5132 RH |
17719 | |
17720 | if (!aent) | |
17721 | { | |
7a621144 DJ |
17722 | /* This function needs its own .frame and .cprestore directives. */ |
17723 | mips_frame_reg_valid = 0; | |
17724 | mips_cprestore_valid = 0; | |
17725 | ||
252b5132 RH |
17726 | cur_proc_ptr = &cur_proc; |
17727 | memset (cur_proc_ptr, '\0', sizeof (procS)); | |
17728 | ||
9b2f1d35 | 17729 | cur_proc_ptr->func_sym = symbolP; |
252b5132 | 17730 | |
f9419b05 | 17731 | ++numprocs; |
ecb4347a DJ |
17732 | |
17733 | if (debug_type == DEBUG_STABS) | |
17734 | stabs_generate_asm_func (S_GET_NAME (symbolP), | |
17735 | S_GET_NAME (symbolP)); | |
252b5132 RH |
17736 | } |
17737 | ||
7c0fc524 MR |
17738 | symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION; |
17739 | ||
252b5132 RH |
17740 | demand_empty_rest_of_line (); |
17741 | } | |
17742 | ||
17743 | /* The .frame directive. If the mdebug section is present (IRIX 5 native) | |
bdaaa2e1 | 17744 | then ecoff.c (ecoff_directive_frame) is used. For embedded targets, |
252b5132 | 17745 | s_mips_frame is used so that we can set the PDR information correctly. |
bdaaa2e1 | 17746 | We can't use the ecoff routines because they make reference to the ecoff |
252b5132 RH |
17747 | symbol table (in the mdebug section). */ |
17748 | ||
17749 | static void | |
17a2f251 | 17750 | s_mips_frame (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 17751 | { |
f3ded42a RS |
17752 | if (ECOFF_DEBUGGING) |
17753 | s_ignore (ignore); | |
17754 | else | |
ecb4347a DJ |
17755 | { |
17756 | long val; | |
252b5132 | 17757 | |
ecb4347a DJ |
17758 | if (cur_proc_ptr == (procS *) NULL) |
17759 | { | |
17760 | as_warn (_(".frame outside of .ent")); | |
17761 | demand_empty_rest_of_line (); | |
17762 | return; | |
17763 | } | |
252b5132 | 17764 | |
ecb4347a DJ |
17765 | cur_proc_ptr->frame_reg = tc_get_register (1); |
17766 | ||
17767 | SKIP_WHITESPACE (); | |
17768 | if (*input_line_pointer++ != ',' | |
17769 | || get_absolute_expression_and_terminator (&val) != ',') | |
17770 | { | |
1661c76c | 17771 | as_warn (_("bad .frame directive")); |
ecb4347a DJ |
17772 | --input_line_pointer; |
17773 | demand_empty_rest_of_line (); | |
17774 | return; | |
17775 | } | |
252b5132 | 17776 | |
ecb4347a DJ |
17777 | cur_proc_ptr->frame_offset = val; |
17778 | cur_proc_ptr->pc_reg = tc_get_register (0); | |
252b5132 | 17779 | |
252b5132 | 17780 | demand_empty_rest_of_line (); |
252b5132 | 17781 | } |
252b5132 RH |
17782 | } |
17783 | ||
bdaaa2e1 KH |
17784 | /* The .fmask and .mask directives. If the mdebug section is present |
17785 | (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For | |
252b5132 | 17786 | embedded targets, s_mips_mask is used so that we can set the PDR |
bdaaa2e1 | 17787 | information correctly. We can't use the ecoff routines because they |
252b5132 RH |
17788 | make reference to the ecoff symbol table (in the mdebug section). */ |
17789 | ||
17790 | static void | |
17a2f251 | 17791 | s_mips_mask (int reg_type) |
252b5132 | 17792 | { |
f3ded42a RS |
17793 | if (ECOFF_DEBUGGING) |
17794 | s_ignore (reg_type); | |
17795 | else | |
252b5132 | 17796 | { |
ecb4347a | 17797 | long mask, off; |
252b5132 | 17798 | |
ecb4347a DJ |
17799 | if (cur_proc_ptr == (procS *) NULL) |
17800 | { | |
17801 | as_warn (_(".mask/.fmask outside of .ent")); | |
17802 | demand_empty_rest_of_line (); | |
17803 | return; | |
17804 | } | |
252b5132 | 17805 | |
ecb4347a DJ |
17806 | if (get_absolute_expression_and_terminator (&mask) != ',') |
17807 | { | |
1661c76c | 17808 | as_warn (_("bad .mask/.fmask directive")); |
ecb4347a DJ |
17809 | --input_line_pointer; |
17810 | demand_empty_rest_of_line (); | |
17811 | return; | |
17812 | } | |
252b5132 | 17813 | |
ecb4347a DJ |
17814 | off = get_absolute_expression (); |
17815 | ||
17816 | if (reg_type == 'F') | |
17817 | { | |
17818 | cur_proc_ptr->fpreg_mask = mask; | |
17819 | cur_proc_ptr->fpreg_offset = off; | |
17820 | } | |
17821 | else | |
17822 | { | |
17823 | cur_proc_ptr->reg_mask = mask; | |
17824 | cur_proc_ptr->reg_offset = off; | |
17825 | } | |
17826 | ||
17827 | demand_empty_rest_of_line (); | |
252b5132 | 17828 | } |
252b5132 RH |
17829 | } |
17830 | ||
316f5878 RS |
17831 | /* A table describing all the processors gas knows about. Names are |
17832 | matched in the order listed. | |
e7af610e | 17833 | |
316f5878 RS |
17834 | To ease comparison, please keep this table in the same order as |
17835 | gcc's mips_cpu_info_table[]. */ | |
e972090a NC |
17836 | static const struct mips_cpu_info mips_cpu_info_table[] = |
17837 | { | |
316f5878 | 17838 | /* Entries for generic ISAs */ |
d16afab6 RS |
17839 | { "mips1", MIPS_CPU_IS_ISA, 0, ISA_MIPS1, CPU_R3000 }, |
17840 | { "mips2", MIPS_CPU_IS_ISA, 0, ISA_MIPS2, CPU_R6000 }, | |
17841 | { "mips3", MIPS_CPU_IS_ISA, 0, ISA_MIPS3, CPU_R4000 }, | |
17842 | { "mips4", MIPS_CPU_IS_ISA, 0, ISA_MIPS4, CPU_R8000 }, | |
17843 | { "mips5", MIPS_CPU_IS_ISA, 0, ISA_MIPS5, CPU_MIPS5 }, | |
17844 | { "mips32", MIPS_CPU_IS_ISA, 0, ISA_MIPS32, CPU_MIPS32 }, | |
17845 | { "mips32r2", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
ae52f483 AB |
17846 | { "mips32r3", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R3, CPU_MIPS32R3 }, |
17847 | { "mips32r5", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R5, CPU_MIPS32R5 }, | |
d16afab6 RS |
17848 | { "mips64", MIPS_CPU_IS_ISA, 0, ISA_MIPS64, CPU_MIPS64 }, |
17849 | { "mips64r2", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R2, CPU_MIPS64R2 }, | |
ae52f483 AB |
17850 | { "mips64r3", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R3, CPU_MIPS64R3 }, |
17851 | { "mips64r5", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R5, CPU_MIPS64R5 }, | |
316f5878 RS |
17852 | |
17853 | /* MIPS I */ | |
d16afab6 RS |
17854 | { "r3000", 0, 0, ISA_MIPS1, CPU_R3000 }, |
17855 | { "r2000", 0, 0, ISA_MIPS1, CPU_R3000 }, | |
17856 | { "r3900", 0, 0, ISA_MIPS1, CPU_R3900 }, | |
316f5878 RS |
17857 | |
17858 | /* MIPS II */ | |
d16afab6 | 17859 | { "r6000", 0, 0, ISA_MIPS2, CPU_R6000 }, |
316f5878 RS |
17860 | |
17861 | /* MIPS III */ | |
d16afab6 RS |
17862 | { "r4000", 0, 0, ISA_MIPS3, CPU_R4000 }, |
17863 | { "r4010", 0, 0, ISA_MIPS2, CPU_R4010 }, | |
17864 | { "vr4100", 0, 0, ISA_MIPS3, CPU_VR4100 }, | |
17865 | { "vr4111", 0, 0, ISA_MIPS3, CPU_R4111 }, | |
17866 | { "vr4120", 0, 0, ISA_MIPS3, CPU_VR4120 }, | |
17867 | { "vr4130", 0, 0, ISA_MIPS3, CPU_VR4120 }, | |
17868 | { "vr4181", 0, 0, ISA_MIPS3, CPU_R4111 }, | |
17869 | { "vr4300", 0, 0, ISA_MIPS3, CPU_R4300 }, | |
17870 | { "r4400", 0, 0, ISA_MIPS3, CPU_R4400 }, | |
17871 | { "r4600", 0, 0, ISA_MIPS3, CPU_R4600 }, | |
17872 | { "orion", 0, 0, ISA_MIPS3, CPU_R4600 }, | |
17873 | { "r4650", 0, 0, ISA_MIPS3, CPU_R4650 }, | |
17874 | { "r5900", 0, 0, ISA_MIPS3, CPU_R5900 }, | |
b15591bb | 17875 | /* ST Microelectronics Loongson 2E and 2F cores */ |
d16afab6 RS |
17876 | { "loongson2e", 0, 0, ISA_MIPS3, CPU_LOONGSON_2E }, |
17877 | { "loongson2f", 0, 0, ISA_MIPS3, CPU_LOONGSON_2F }, | |
316f5878 RS |
17878 | |
17879 | /* MIPS IV */ | |
d16afab6 RS |
17880 | { "r8000", 0, 0, ISA_MIPS4, CPU_R8000 }, |
17881 | { "r10000", 0, 0, ISA_MIPS4, CPU_R10000 }, | |
17882 | { "r12000", 0, 0, ISA_MIPS4, CPU_R12000 }, | |
17883 | { "r14000", 0, 0, ISA_MIPS4, CPU_R14000 }, | |
17884 | { "r16000", 0, 0, ISA_MIPS4, CPU_R16000 }, | |
17885 | { "vr5000", 0, 0, ISA_MIPS4, CPU_R5000 }, | |
17886 | { "vr5400", 0, 0, ISA_MIPS4, CPU_VR5400 }, | |
17887 | { "vr5500", 0, 0, ISA_MIPS4, CPU_VR5500 }, | |
17888 | { "rm5200", 0, 0, ISA_MIPS4, CPU_R5000 }, | |
17889 | { "rm5230", 0, 0, ISA_MIPS4, CPU_R5000 }, | |
17890 | { "rm5231", 0, 0, ISA_MIPS4, CPU_R5000 }, | |
17891 | { "rm5261", 0, 0, ISA_MIPS4, CPU_R5000 }, | |
17892 | { "rm5721", 0, 0, ISA_MIPS4, CPU_R5000 }, | |
17893 | { "rm7000", 0, 0, ISA_MIPS4, CPU_RM7000 }, | |
17894 | { "rm9000", 0, 0, ISA_MIPS4, CPU_RM9000 }, | |
316f5878 RS |
17895 | |
17896 | /* MIPS 32 */ | |
d16afab6 RS |
17897 | { "4kc", 0, 0, ISA_MIPS32, CPU_MIPS32 }, |
17898 | { "4km", 0, 0, ISA_MIPS32, CPU_MIPS32 }, | |
17899 | { "4kp", 0, 0, ISA_MIPS32, CPU_MIPS32 }, | |
17900 | { "4ksc", 0, ASE_SMARTMIPS, ISA_MIPS32, CPU_MIPS32 }, | |
ad3fea08 TS |
17901 | |
17902 | /* MIPS 32 Release 2 */ | |
d16afab6 RS |
17903 | { "4kec", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
17904 | { "4kem", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
17905 | { "4kep", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
17906 | { "4ksd", 0, ASE_SMARTMIPS, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
17907 | { "m4k", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
17908 | { "m4kp", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
17909 | { "m14k", 0, ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
17910 | { "m14kc", 0, ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
17911 | { "m14ke", 0, ASE_DSP | ASE_DSPR2 | ASE_MCU, | |
17912 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
17913 | { "m14kec", 0, ASE_DSP | ASE_DSPR2 | ASE_MCU, | |
17914 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
17915 | { "24kc", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
17916 | { "24kf2_1", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
17917 | { "24kf", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
17918 | { "24kf1_1", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 | 17919 | /* Deprecated forms of the above. */ |
d16afab6 RS |
17920 | { "24kfx", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
17921 | { "24kx", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
01fd108f | 17922 | /* 24KE is a 24K with DSP ASE, other ASEs are optional. */ |
d16afab6 RS |
17923 | { "24kec", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
17924 | { "24kef2_1", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
17925 | { "24kef", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
17926 | { "24kef1_1", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 | 17927 | /* Deprecated forms of the above. */ |
d16afab6 RS |
17928 | { "24kefx", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
17929 | { "24kex", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
01fd108f | 17930 | /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */ |
d16afab6 RS |
17931 | { "34kc", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, |
17932 | { "34kf2_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
17933 | { "34kf", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
17934 | { "34kf1_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 | 17935 | /* Deprecated forms of the above. */ |
d16afab6 RS |
17936 | { "34kfx", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, |
17937 | { "34kx", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
711eefe4 | 17938 | /* 34Kn is a 34kc without DSP. */ |
d16afab6 | 17939 | { "34kn", 0, ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, |
01fd108f | 17940 | /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */ |
d16afab6 RS |
17941 | { "74kc", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, |
17942 | { "74kf2_1", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
17943 | { "74kf", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
17944 | { "74kf1_1", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
17945 | { "74kf3_2", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 | 17946 | /* Deprecated forms of the above. */ |
d16afab6 RS |
17947 | { "74kfx", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, |
17948 | { "74kx", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
30f8113a | 17949 | /* 1004K cores are multiprocessor versions of the 34K. */ |
d16afab6 RS |
17950 | { "1004kc", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, |
17951 | { "1004kf2_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
17952 | { "1004kf", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
17953 | { "1004kf1_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
bbaa46c0 | 17954 | /* P5600 with EVA and Virtualization ASEs, other ASEs are optional. */ |
ae52f483 | 17955 | { "p5600", 0, ASE_VIRT | ASE_EVA | ASE_XPA, ISA_MIPS32R5, CPU_MIPS32R5 }, |
32b26a03 | 17956 | |
316f5878 | 17957 | /* MIPS 64 */ |
d16afab6 RS |
17958 | { "5kc", 0, 0, ISA_MIPS64, CPU_MIPS64 }, |
17959 | { "5kf", 0, 0, ISA_MIPS64, CPU_MIPS64 }, | |
17960 | { "20kc", 0, ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 }, | |
17961 | { "25kf", 0, ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 }, | |
ad3fea08 | 17962 | |
c7a23324 | 17963 | /* Broadcom SB-1 CPU core */ |
d16afab6 | 17964 | { "sb1", 0, ASE_MIPS3D | ASE_MDMX, ISA_MIPS64, CPU_SB1 }, |
1e85aad8 | 17965 | /* Broadcom SB-1A CPU core */ |
d16afab6 | 17966 | { "sb1a", 0, ASE_MIPS3D | ASE_MDMX, ISA_MIPS64, CPU_SB1 }, |
d051516a | 17967 | |
4ba154f5 | 17968 | { "loongson3a", 0, 0, ISA_MIPS64R2, CPU_LOONGSON_3A }, |
e7af610e | 17969 | |
ed163775 MR |
17970 | /* MIPS 64 Release 2 */ |
17971 | ||
967344c6 | 17972 | /* Cavium Networks Octeon CPU core */ |
d16afab6 RS |
17973 | { "octeon", 0, 0, ISA_MIPS64R2, CPU_OCTEON }, |
17974 | { "octeon+", 0, 0, ISA_MIPS64R2, CPU_OCTEONP }, | |
17975 | { "octeon2", 0, 0, ISA_MIPS64R2, CPU_OCTEON2 }, | |
967344c6 | 17976 | |
52b6b6b9 | 17977 | /* RMI Xlr */ |
d16afab6 | 17978 | { "xlr", 0, 0, ISA_MIPS64, CPU_XLR }, |
52b6b6b9 | 17979 | |
55a36193 MK |
17980 | /* Broadcom XLP. |
17981 | XLP is mostly like XLR, with the prominent exception that it is | |
17982 | MIPS64R2 rather than MIPS64. */ | |
d16afab6 | 17983 | { "xlp", 0, 0, ISA_MIPS64R2, CPU_XLR }, |
55a36193 | 17984 | |
316f5878 | 17985 | /* End marker */ |
d16afab6 | 17986 | { NULL, 0, 0, 0, 0 } |
316f5878 | 17987 | }; |
e7af610e | 17988 | |
84ea6cf2 | 17989 | |
316f5878 RS |
17990 | /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL |
17991 | with a final "000" replaced by "k". Ignore case. | |
e7af610e | 17992 | |
316f5878 | 17993 | Note: this function is shared between GCC and GAS. */ |
c6c98b38 | 17994 | |
b34976b6 | 17995 | static bfd_boolean |
17a2f251 | 17996 | mips_strict_matching_cpu_name_p (const char *canonical, const char *given) |
316f5878 RS |
17997 | { |
17998 | while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical)) | |
17999 | given++, canonical++; | |
18000 | ||
18001 | return ((*given == 0 && *canonical == 0) | |
18002 | || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0)); | |
18003 | } | |
18004 | ||
18005 | ||
18006 | /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied | |
18007 | CPU name. We've traditionally allowed a lot of variation here. | |
18008 | ||
18009 | Note: this function is shared between GCC and GAS. */ | |
18010 | ||
b34976b6 | 18011 | static bfd_boolean |
17a2f251 | 18012 | mips_matching_cpu_name_p (const char *canonical, const char *given) |
316f5878 RS |
18013 | { |
18014 | /* First see if the name matches exactly, or with a final "000" | |
18015 | turned into "k". */ | |
18016 | if (mips_strict_matching_cpu_name_p (canonical, given)) | |
b34976b6 | 18017 | return TRUE; |
316f5878 RS |
18018 | |
18019 | /* If not, try comparing based on numerical designation alone. | |
18020 | See if GIVEN is an unadorned number, or 'r' followed by a number. */ | |
18021 | if (TOLOWER (*given) == 'r') | |
18022 | given++; | |
18023 | if (!ISDIGIT (*given)) | |
b34976b6 | 18024 | return FALSE; |
316f5878 RS |
18025 | |
18026 | /* Skip over some well-known prefixes in the canonical name, | |
18027 | hoping to find a number there too. */ | |
18028 | if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r') | |
18029 | canonical += 2; | |
18030 | else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm') | |
18031 | canonical += 2; | |
18032 | else if (TOLOWER (canonical[0]) == 'r') | |
18033 | canonical += 1; | |
18034 | ||
18035 | return mips_strict_matching_cpu_name_p (canonical, given); | |
18036 | } | |
18037 | ||
18038 | ||
18039 | /* Parse an option that takes the name of a processor as its argument. | |
18040 | OPTION is the name of the option and CPU_STRING is the argument. | |
18041 | Return the corresponding processor enumeration if the CPU_STRING is | |
18042 | recognized, otherwise report an error and return null. | |
18043 | ||
18044 | A similar function exists in GCC. */ | |
e7af610e NC |
18045 | |
18046 | static const struct mips_cpu_info * | |
17a2f251 | 18047 | mips_parse_cpu (const char *option, const char *cpu_string) |
e7af610e | 18048 | { |
316f5878 | 18049 | const struct mips_cpu_info *p; |
e7af610e | 18050 | |
316f5878 RS |
18051 | /* 'from-abi' selects the most compatible architecture for the given |
18052 | ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the | |
18053 | EABIs, we have to decide whether we're using the 32-bit or 64-bit | |
18054 | version. Look first at the -mgp options, if given, otherwise base | |
18055 | the choice on MIPS_DEFAULT_64BIT. | |
e7af610e | 18056 | |
316f5878 RS |
18057 | Treat NO_ABI like the EABIs. One reason to do this is that the |
18058 | plain 'mips' and 'mips64' configs have 'from-abi' as their default | |
18059 | architecture. This code picks MIPS I for 'mips' and MIPS III for | |
18060 | 'mips64', just as we did in the days before 'from-abi'. */ | |
18061 | if (strcasecmp (cpu_string, "from-abi") == 0) | |
18062 | { | |
18063 | if (ABI_NEEDS_32BIT_REGS (mips_abi)) | |
18064 | return mips_cpu_info_from_isa (ISA_MIPS1); | |
18065 | ||
18066 | if (ABI_NEEDS_64BIT_REGS (mips_abi)) | |
18067 | return mips_cpu_info_from_isa (ISA_MIPS3); | |
18068 | ||
bad1aba3 | 18069 | if (file_mips_opts.gp >= 0) |
18070 | return mips_cpu_info_from_isa (file_mips_opts.gp == 32 | |
0b35dfee | 18071 | ? ISA_MIPS1 : ISA_MIPS3); |
316f5878 RS |
18072 | |
18073 | return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT | |
18074 | ? ISA_MIPS3 | |
18075 | : ISA_MIPS1); | |
18076 | } | |
18077 | ||
18078 | /* 'default' has traditionally been a no-op. Probably not very useful. */ | |
18079 | if (strcasecmp (cpu_string, "default") == 0) | |
18080 | return 0; | |
18081 | ||
18082 | for (p = mips_cpu_info_table; p->name != 0; p++) | |
18083 | if (mips_matching_cpu_name_p (p->name, cpu_string)) | |
18084 | return p; | |
18085 | ||
1661c76c | 18086 | as_bad (_("bad value (%s) for %s"), cpu_string, option); |
316f5878 | 18087 | return 0; |
e7af610e NC |
18088 | } |
18089 | ||
316f5878 RS |
18090 | /* Return the canonical processor information for ISA (a member of the |
18091 | ISA_MIPS* enumeration). */ | |
18092 | ||
e7af610e | 18093 | static const struct mips_cpu_info * |
17a2f251 | 18094 | mips_cpu_info_from_isa (int isa) |
e7af610e NC |
18095 | { |
18096 | int i; | |
18097 | ||
18098 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
ad3fea08 | 18099 | if ((mips_cpu_info_table[i].flags & MIPS_CPU_IS_ISA) |
316f5878 | 18100 | && isa == mips_cpu_info_table[i].isa) |
e7af610e NC |
18101 | return (&mips_cpu_info_table[i]); |
18102 | ||
e972090a | 18103 | return NULL; |
e7af610e | 18104 | } |
fef14a42 TS |
18105 | |
18106 | static const struct mips_cpu_info * | |
17a2f251 | 18107 | mips_cpu_info_from_arch (int arch) |
fef14a42 TS |
18108 | { |
18109 | int i; | |
18110 | ||
18111 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
18112 | if (arch == mips_cpu_info_table[i].cpu) | |
18113 | return (&mips_cpu_info_table[i]); | |
18114 | ||
18115 | return NULL; | |
18116 | } | |
316f5878 RS |
18117 | \f |
18118 | static void | |
17a2f251 | 18119 | show (FILE *stream, const char *string, int *col_p, int *first_p) |
316f5878 RS |
18120 | { |
18121 | if (*first_p) | |
18122 | { | |
18123 | fprintf (stream, "%24s", ""); | |
18124 | *col_p = 24; | |
18125 | } | |
18126 | else | |
18127 | { | |
18128 | fprintf (stream, ", "); | |
18129 | *col_p += 2; | |
18130 | } | |
e7af610e | 18131 | |
316f5878 RS |
18132 | if (*col_p + strlen (string) > 72) |
18133 | { | |
18134 | fprintf (stream, "\n%24s", ""); | |
18135 | *col_p = 24; | |
18136 | } | |
18137 | ||
18138 | fprintf (stream, "%s", string); | |
18139 | *col_p += strlen (string); | |
18140 | ||
18141 | *first_p = 0; | |
18142 | } | |
18143 | ||
18144 | void | |
17a2f251 | 18145 | md_show_usage (FILE *stream) |
e7af610e | 18146 | { |
316f5878 RS |
18147 | int column, first; |
18148 | size_t i; | |
18149 | ||
18150 | fprintf (stream, _("\ | |
18151 | MIPS options:\n\ | |
316f5878 RS |
18152 | -EB generate big endian output\n\ |
18153 | -EL generate little endian output\n\ | |
18154 | -g, -g2 do not remove unneeded NOPs or swap branches\n\ | |
18155 | -G NUM allow referencing objects up to NUM bytes\n\ | |
18156 | implicitly with the gp register [default 8]\n")); | |
18157 | fprintf (stream, _("\ | |
18158 | -mips1 generate MIPS ISA I instructions\n\ | |
18159 | -mips2 generate MIPS ISA II instructions\n\ | |
18160 | -mips3 generate MIPS ISA III instructions\n\ | |
18161 | -mips4 generate MIPS ISA IV instructions\n\ | |
18162 | -mips5 generate MIPS ISA V instructions\n\ | |
18163 | -mips32 generate MIPS32 ISA instructions\n\ | |
af7ee8bf | 18164 | -mips32r2 generate MIPS32 release 2 ISA instructions\n\ |
ae52f483 AB |
18165 | -mips32r3 generate MIPS32 release 3 ISA instructions\n\ |
18166 | -mips32r5 generate MIPS32 release 5 ISA instructions\n\ | |
316f5878 | 18167 | -mips64 generate MIPS64 ISA instructions\n\ |
5f74bc13 | 18168 | -mips64r2 generate MIPS64 release 2 ISA instructions\n\ |
ae52f483 AB |
18169 | -mips64r3 generate MIPS64 release 3 ISA instructions\n\ |
18170 | -mips64r5 generate MIPS64 release 5 ISA instructions\n\ | |
316f5878 RS |
18171 | -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n")); |
18172 | ||
18173 | first = 1; | |
e7af610e NC |
18174 | |
18175 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
316f5878 RS |
18176 | show (stream, mips_cpu_info_table[i].name, &column, &first); |
18177 | show (stream, "from-abi", &column, &first); | |
18178 | fputc ('\n', stream); | |
e7af610e | 18179 | |
316f5878 RS |
18180 | fprintf (stream, _("\ |
18181 | -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\ | |
18182 | -no-mCPU don't generate code specific to CPU.\n\ | |
18183 | For -mCPU and -no-mCPU, CPU must be one of:\n")); | |
18184 | ||
18185 | first = 1; | |
18186 | ||
18187 | show (stream, "3900", &column, &first); | |
18188 | show (stream, "4010", &column, &first); | |
18189 | show (stream, "4100", &column, &first); | |
18190 | show (stream, "4650", &column, &first); | |
18191 | fputc ('\n', stream); | |
18192 | ||
18193 | fprintf (stream, _("\ | |
18194 | -mips16 generate mips16 instructions\n\ | |
18195 | -no-mips16 do not generate mips16 instructions\n")); | |
18196 | fprintf (stream, _("\ | |
df58fc94 RS |
18197 | -mmicromips generate microMIPS instructions\n\ |
18198 | -mno-micromips do not generate microMIPS instructions\n")); | |
18199 | fprintf (stream, _("\ | |
e16bfa71 TS |
18200 | -msmartmips generate smartmips instructions\n\ |
18201 | -mno-smartmips do not generate smartmips instructions\n")); | |
18202 | fprintf (stream, _("\ | |
74cd071d CF |
18203 | -mdsp generate DSP instructions\n\ |
18204 | -mno-dsp do not generate DSP instructions\n")); | |
18205 | fprintf (stream, _("\ | |
8b082fb1 TS |
18206 | -mdspr2 generate DSP R2 instructions\n\ |
18207 | -mno-dspr2 do not generate DSP R2 instructions\n")); | |
18208 | fprintf (stream, _("\ | |
ef2e4d86 CF |
18209 | -mmt generate MT instructions\n\ |
18210 | -mno-mt do not generate MT instructions\n")); | |
18211 | fprintf (stream, _("\ | |
dec0624d MR |
18212 | -mmcu generate MCU instructions\n\ |
18213 | -mno-mcu do not generate MCU instructions\n")); | |
18214 | fprintf (stream, _("\ | |
56d438b1 CF |
18215 | -mmsa generate MSA instructions\n\ |
18216 | -mno-msa do not generate MSA instructions\n")); | |
18217 | fprintf (stream, _("\ | |
7d64c587 AB |
18218 | -mxpa generate eXtended Physical Address (XPA) instructions\n\ |
18219 | -mno-xpa do not generate eXtended Physical Address (XPA) instructions\n")); | |
18220 | fprintf (stream, _("\ | |
b015e599 AP |
18221 | -mvirt generate Virtualization instructions\n\ |
18222 | -mno-virt do not generate Virtualization instructions\n")); | |
18223 | fprintf (stream, _("\ | |
833794fc MR |
18224 | -minsn32 only generate 32-bit microMIPS instructions\n\ |
18225 | -mno-insn32 generate all microMIPS instructions\n")); | |
18226 | fprintf (stream, _("\ | |
c67a084a NC |
18227 | -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\ |
18228 | -mfix-loongson2f-nop work around Loongson2F NOP errata\n\ | |
d766e8ec | 18229 | -mfix-vr4120 work around certain VR4120 errata\n\ |
7d8e00cf | 18230 | -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\ |
6a32d874 | 18231 | -mfix-24k insert a nop after ERET and DERET instructions\n\ |
d954098f | 18232 | -mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\ |
316f5878 RS |
18233 | -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\ |
18234 | -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\ | |
aed1a261 | 18235 | -msym32 assume all symbols have 32-bit values\n\ |
316f5878 RS |
18236 | -O0 remove unneeded NOPs, do not swap branches\n\ |
18237 | -O remove unneeded NOPs and swap branches\n\ | |
316f5878 RS |
18238 | --trap, --no-break trap exception on div by 0 and mult overflow\n\ |
18239 | --break, --no-trap break exception on div by 0 and mult overflow\n")); | |
037b32b9 AN |
18240 | fprintf (stream, _("\ |
18241 | -mhard-float allow floating-point instructions\n\ | |
18242 | -msoft-float do not allow floating-point instructions\n\ | |
18243 | -msingle-float only allow 32-bit floating-point operations\n\ | |
18244 | -mdouble-float allow 32-bit and 64-bit floating-point operations\n\ | |
3bf0dbfb | 18245 | --[no-]construct-floats [dis]allow floating point values to be constructed\n\ |
ba92f887 MR |
18246 | --[no-]relax-branch [dis]allow out-of-range branches to be relaxed\n\ |
18247 | -mnan=ENCODING select an IEEE 754 NaN encoding convention, either of:\n")); | |
18248 | ||
18249 | first = 1; | |
18250 | ||
18251 | show (stream, "legacy", &column, &first); | |
18252 | show (stream, "2008", &column, &first); | |
18253 | ||
18254 | fputc ('\n', stream); | |
18255 | ||
316f5878 RS |
18256 | fprintf (stream, _("\ |
18257 | -KPIC, -call_shared generate SVR4 position independent code\n\ | |
861fb55a | 18258 | -call_nonpic generate non-PIC code that can operate with DSOs\n\ |
0c000745 | 18259 | -mvxworks-pic generate VxWorks position independent code\n\ |
861fb55a | 18260 | -non_shared do not generate code that can operate with DSOs\n\ |
316f5878 | 18261 | -xgot assume a 32 bit GOT\n\ |
dcd410fe | 18262 | -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\ |
bbe506e8 | 18263 | -mshared, -mno-shared disable/enable .cpload optimization for\n\ |
d821e36b | 18264 | position dependent (non shared) code\n\ |
316f5878 RS |
18265 | -mabi=ABI create ABI conformant object file for:\n")); |
18266 | ||
18267 | first = 1; | |
18268 | ||
18269 | show (stream, "32", &column, &first); | |
18270 | show (stream, "o64", &column, &first); | |
18271 | show (stream, "n32", &column, &first); | |
18272 | show (stream, "64", &column, &first); | |
18273 | show (stream, "eabi", &column, &first); | |
18274 | ||
18275 | fputc ('\n', stream); | |
18276 | ||
18277 | fprintf (stream, _("\ | |
18278 | -32 create o32 ABI object file (default)\n\ | |
18279 | -n32 create n32 ABI object file\n\ | |
18280 | -64 create 64 ABI object file\n")); | |
e7af610e | 18281 | } |
14e777e0 | 18282 | |
1575952e | 18283 | #ifdef TE_IRIX |
14e777e0 | 18284 | enum dwarf2_format |
413a266c | 18285 | mips_dwarf2_format (asection *sec ATTRIBUTE_UNUSED) |
14e777e0 | 18286 | { |
369943fe | 18287 | if (HAVE_64BIT_SYMBOLS) |
1575952e | 18288 | return dwarf2_format_64bit_irix; |
14e777e0 KB |
18289 | else |
18290 | return dwarf2_format_32bit; | |
18291 | } | |
1575952e | 18292 | #endif |
73369e65 EC |
18293 | |
18294 | int | |
18295 | mips_dwarf2_addr_size (void) | |
18296 | { | |
6b6b3450 | 18297 | if (HAVE_64BIT_OBJECTS) |
73369e65 | 18298 | return 8; |
73369e65 EC |
18299 | else |
18300 | return 4; | |
18301 | } | |
5862107c EC |
18302 | |
18303 | /* Standard calling conventions leave the CFA at SP on entry. */ | |
18304 | void | |
18305 | mips_cfi_frame_initial_instructions (void) | |
18306 | { | |
18307 | cfi_add_CFA_def_cfa_register (SP); | |
18308 | } | |
18309 | ||
707bfff6 TS |
18310 | int |
18311 | tc_mips_regname_to_dw2regnum (char *regname) | |
18312 | { | |
18313 | unsigned int regnum = -1; | |
18314 | unsigned int reg; | |
18315 | ||
18316 | if (reg_lookup (®name, RTYPE_GP | RTYPE_NUM, ®)) | |
18317 | regnum = reg; | |
18318 | ||
18319 | return regnum; | |
18320 | } | |
263b2574 | 18321 | |
18322 | /* Implement CONVERT_SYMBOLIC_ATTRIBUTE. | |
18323 | Given a symbolic attribute NAME, return the proper integer value. | |
18324 | Returns -1 if the attribute is not known. */ | |
18325 | ||
18326 | int | |
18327 | mips_convert_symbolic_attribute (const char *name) | |
18328 | { | |
18329 | static const struct | |
18330 | { | |
18331 | const char * name; | |
18332 | const int tag; | |
18333 | } | |
18334 | attribute_table[] = | |
18335 | { | |
18336 | #define T(tag) {#tag, tag} | |
18337 | T (Tag_GNU_MIPS_ABI_FP), | |
18338 | T (Tag_GNU_MIPS_ABI_MSA), | |
18339 | #undef T | |
18340 | }; | |
18341 | unsigned int i; | |
18342 | ||
18343 | if (name == NULL) | |
18344 | return -1; | |
18345 | ||
18346 | for (i = 0; i < ARRAY_SIZE (attribute_table); i++) | |
18347 | if (streq (name, attribute_table[i].name)) | |
18348 | return attribute_table[i].tag; | |
18349 | ||
18350 | return -1; | |
18351 | } | |
fd5c94ab RS |
18352 | |
18353 | void | |
18354 | md_mips_end (void) | |
18355 | { | |
18356 | mips_emit_delays (); | |
18357 | if (cur_proc_ptr) | |
18358 | as_warn (_("missing .end at end of assembly")); | |
18359 | } |