Commit | Line | Data |
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252b5132 | 1 | /* tc-mips.c -- assemble code for a MIPS chip. |
81912461 | 2 | Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, |
e407c74b | 3 | 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012, 2013 |
c67a084a | 4 | Free Software Foundation, Inc. |
252b5132 RH |
5 | Contributed by the OSF and Ralph Campbell. |
6 | Written by Keith Knowles and Ralph Campbell, working independently. | |
7 | Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus | |
8 | Support. | |
9 | ||
10 | This file is part of GAS. | |
11 | ||
12 | GAS is free software; you can redistribute it and/or modify | |
13 | it under the terms of the GNU General Public License as published by | |
ec2655a6 | 14 | the Free Software Foundation; either version 3, or (at your option) |
252b5132 RH |
15 | any later version. |
16 | ||
17 | GAS is distributed in the hope that it will be useful, | |
18 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | GNU General Public License for more details. | |
21 | ||
22 | You should have received a copy of the GNU General Public License | |
23 | along with GAS; see the file COPYING. If not, write to the Free | |
4b4da160 NC |
24 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
25 | 02110-1301, USA. */ | |
252b5132 RH |
26 | |
27 | #include "as.h" | |
28 | #include "config.h" | |
29 | #include "subsegs.h" | |
3882b010 | 30 | #include "safe-ctype.h" |
252b5132 | 31 | |
252b5132 RH |
32 | #include "opcode/mips.h" |
33 | #include "itbl-ops.h" | |
c5dd6aab | 34 | #include "dwarf2dbg.h" |
5862107c | 35 | #include "dw2gencfi.h" |
252b5132 RH |
36 | |
37 | #ifdef DEBUG | |
38 | #define DBG(x) printf x | |
39 | #else | |
40 | #define DBG(x) | |
41 | #endif | |
42 | ||
252b5132 | 43 | /* Clean up namespace so we can include obj-elf.h too. */ |
17a2f251 TS |
44 | static int mips_output_flavor (void); |
45 | static int mips_output_flavor (void) { return OUTPUT_FLAVOR; } | |
252b5132 RH |
46 | #undef OBJ_PROCESS_STAB |
47 | #undef OUTPUT_FLAVOR | |
48 | #undef S_GET_ALIGN | |
49 | #undef S_GET_SIZE | |
50 | #undef S_SET_ALIGN | |
51 | #undef S_SET_SIZE | |
252b5132 RH |
52 | #undef obj_frob_file |
53 | #undef obj_frob_file_after_relocs | |
54 | #undef obj_frob_symbol | |
55 | #undef obj_pop_insert | |
56 | #undef obj_sec_sym_ok_for_reloc | |
57 | #undef OBJ_COPY_SYMBOL_ATTRIBUTES | |
58 | ||
59 | #include "obj-elf.h" | |
60 | /* Fix any of them that we actually care about. */ | |
61 | #undef OUTPUT_FLAVOR | |
62 | #define OUTPUT_FLAVOR mips_output_flavor() | |
252b5132 | 63 | |
252b5132 | 64 | #include "elf/mips.h" |
252b5132 RH |
65 | |
66 | #ifndef ECOFF_DEBUGGING | |
67 | #define NO_ECOFF_DEBUGGING | |
68 | #define ECOFF_DEBUGGING 0 | |
69 | #endif | |
70 | ||
ecb4347a DJ |
71 | int mips_flag_mdebug = -1; |
72 | ||
dcd410fe RO |
73 | /* Control generation of .pdr sections. Off by default on IRIX: the native |
74 | linker doesn't know about and discards them, but relocations against them | |
75 | remain, leading to rld crashes. */ | |
76 | #ifdef TE_IRIX | |
77 | int mips_flag_pdr = FALSE; | |
78 | #else | |
79 | int mips_flag_pdr = TRUE; | |
80 | #endif | |
81 | ||
252b5132 RH |
82 | #include "ecoff.h" |
83 | ||
252b5132 | 84 | static char *mips_regmask_frag; |
252b5132 | 85 | |
85b51719 | 86 | #define ZERO 0 |
741fe287 | 87 | #define ATREG 1 |
df58fc94 RS |
88 | #define S0 16 |
89 | #define S7 23 | |
252b5132 RH |
90 | #define TREG 24 |
91 | #define PIC_CALL_REG 25 | |
92 | #define KT0 26 | |
93 | #define KT1 27 | |
94 | #define GP 28 | |
95 | #define SP 29 | |
96 | #define FP 30 | |
97 | #define RA 31 | |
98 | ||
99 | #define ILLEGAL_REG (32) | |
100 | ||
741fe287 MR |
101 | #define AT mips_opts.at |
102 | ||
252b5132 RH |
103 | extern int target_big_endian; |
104 | ||
252b5132 | 105 | /* The name of the readonly data section. */ |
e8044f35 | 106 | #define RDATA_SECTION_NAME ".rodata" |
252b5132 | 107 | |
a4e06468 RS |
108 | /* Ways in which an instruction can be "appended" to the output. */ |
109 | enum append_method { | |
110 | /* Just add it normally. */ | |
111 | APPEND_ADD, | |
112 | ||
113 | /* Add it normally and then add a nop. */ | |
114 | APPEND_ADD_WITH_NOP, | |
115 | ||
116 | /* Turn an instruction with a delay slot into a "compact" version. */ | |
117 | APPEND_ADD_COMPACT, | |
118 | ||
119 | /* Insert the instruction before the last one. */ | |
120 | APPEND_SWAP | |
121 | }; | |
122 | ||
47e39b9d RS |
123 | /* Information about an instruction, including its format, operands |
124 | and fixups. */ | |
125 | struct mips_cl_insn | |
126 | { | |
127 | /* The opcode's entry in mips_opcodes or mips16_opcodes. */ | |
128 | const struct mips_opcode *insn_mo; | |
129 | ||
47e39b9d | 130 | /* The 16-bit or 32-bit bitstring of the instruction itself. This is |
5c04167a RS |
131 | a copy of INSN_MO->match with the operands filled in. If we have |
132 | decided to use an extended MIPS16 instruction, this includes the | |
133 | extension. */ | |
47e39b9d RS |
134 | unsigned long insn_opcode; |
135 | ||
136 | /* The frag that contains the instruction. */ | |
137 | struct frag *frag; | |
138 | ||
139 | /* The offset into FRAG of the first instruction byte. */ | |
140 | long where; | |
141 | ||
142 | /* The relocs associated with the instruction, if any. */ | |
143 | fixS *fixp[3]; | |
144 | ||
a38419a5 RS |
145 | /* True if this entry cannot be moved from its current position. */ |
146 | unsigned int fixed_p : 1; | |
47e39b9d | 147 | |
708587a4 | 148 | /* True if this instruction occurred in a .set noreorder block. */ |
47e39b9d RS |
149 | unsigned int noreorder_p : 1; |
150 | ||
2fa15973 RS |
151 | /* True for mips16 instructions that jump to an absolute address. */ |
152 | unsigned int mips16_absolute_jump_p : 1; | |
15be625d CM |
153 | |
154 | /* True if this instruction is complete. */ | |
155 | unsigned int complete_p : 1; | |
e407c74b NC |
156 | |
157 | /* True if this instruction is cleared from history by unconditional | |
158 | branch. */ | |
159 | unsigned int cleared_p : 1; | |
47e39b9d RS |
160 | }; |
161 | ||
a325df1d TS |
162 | /* The ABI to use. */ |
163 | enum mips_abi_level | |
164 | { | |
165 | NO_ABI = 0, | |
166 | O32_ABI, | |
167 | O64_ABI, | |
168 | N32_ABI, | |
169 | N64_ABI, | |
170 | EABI_ABI | |
171 | }; | |
172 | ||
173 | /* MIPS ABI we are using for this output file. */ | |
316f5878 | 174 | static enum mips_abi_level mips_abi = NO_ABI; |
a325df1d | 175 | |
143d77c5 EC |
176 | /* Whether or not we have code that can call pic code. */ |
177 | int mips_abicalls = FALSE; | |
178 | ||
aa6975fb ILT |
179 | /* Whether or not we have code which can be put into a shared |
180 | library. */ | |
181 | static bfd_boolean mips_in_shared = TRUE; | |
182 | ||
252b5132 RH |
183 | /* This is the set of options which may be modified by the .set |
184 | pseudo-op. We use a struct so that .set push and .set pop are more | |
185 | reliable. */ | |
186 | ||
e972090a NC |
187 | struct mips_set_options |
188 | { | |
252b5132 RH |
189 | /* MIPS ISA (Instruction Set Architecture) level. This is set to -1 |
190 | if it has not been initialized. Changed by `.set mipsN', and the | |
191 | -mipsN command line option, and the default CPU. */ | |
192 | int isa; | |
846ef2d0 RS |
193 | /* Enabled Application Specific Extensions (ASEs). Changed by `.set |
194 | <asename>', by command line options, and based on the default | |
195 | architecture. */ | |
196 | int ase; | |
252b5132 RH |
197 | /* Whether we are assembling for the mips16 processor. 0 if we are |
198 | not, 1 if we are, and -1 if the value has not been initialized. | |
199 | Changed by `.set mips16' and `.set nomips16', and the -mips16 and | |
200 | -nomips16 command line options, and the default CPU. */ | |
201 | int mips16; | |
df58fc94 RS |
202 | /* Whether we are assembling for the mipsMIPS ASE. 0 if we are not, |
203 | 1 if we are, and -1 if the value has not been initialized. Changed | |
204 | by `.set micromips' and `.set nomicromips', and the -mmicromips | |
205 | and -mno-micromips command line options, and the default CPU. */ | |
206 | int micromips; | |
252b5132 RH |
207 | /* Non-zero if we should not reorder instructions. Changed by `.set |
208 | reorder' and `.set noreorder'. */ | |
209 | int noreorder; | |
741fe287 MR |
210 | /* Non-zero if we should not permit the register designated "assembler |
211 | temporary" to be used in instructions. The value is the register | |
212 | number, normally $at ($1). Changed by `.set at=REG', `.set noat' | |
213 | (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */ | |
214 | unsigned int at; | |
252b5132 RH |
215 | /* Non-zero if we should warn when a macro instruction expands into |
216 | more than one machine instruction. Changed by `.set nomacro' and | |
217 | `.set macro'. */ | |
218 | int warn_about_macros; | |
219 | /* Non-zero if we should not move instructions. Changed by `.set | |
220 | move', `.set volatile', `.set nomove', and `.set novolatile'. */ | |
221 | int nomove; | |
222 | /* Non-zero if we should not optimize branches by moving the target | |
223 | of the branch into the delay slot. Actually, we don't perform | |
224 | this optimization anyhow. Changed by `.set bopt' and `.set | |
225 | nobopt'. */ | |
226 | int nobopt; | |
227 | /* Non-zero if we should not autoextend mips16 instructions. | |
228 | Changed by `.set autoextend' and `.set noautoextend'. */ | |
229 | int noautoextend; | |
a325df1d TS |
230 | /* Restrict general purpose registers and floating point registers |
231 | to 32 bit. This is initially determined when -mgp32 or -mfp32 | |
232 | is passed but can changed if the assembler code uses .set mipsN. */ | |
233 | int gp32; | |
234 | int fp32; | |
fef14a42 TS |
235 | /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march |
236 | command line option, and the default CPU. */ | |
237 | int arch; | |
aed1a261 RS |
238 | /* True if ".set sym32" is in effect. */ |
239 | bfd_boolean sym32; | |
037b32b9 AN |
240 | /* True if floating-point operations are not allowed. Changed by .set |
241 | softfloat or .set hardfloat, by command line options -msoft-float or | |
242 | -mhard-float. The default is false. */ | |
243 | bfd_boolean soft_float; | |
244 | ||
245 | /* True if only single-precision floating-point operations are allowed. | |
246 | Changed by .set singlefloat or .set doublefloat, command-line options | |
247 | -msingle-float or -mdouble-float. The default is false. */ | |
248 | bfd_boolean single_float; | |
252b5132 RH |
249 | }; |
250 | ||
037b32b9 AN |
251 | /* This is the struct we use to hold the current set of options. Note |
252 | that we must set the isa field to ISA_UNKNOWN and the ASE fields to | |
253 | -1 to indicate that they have not been initialized. */ | |
254 | ||
a325df1d | 255 | /* True if -mgp32 was passed. */ |
a8e8e863 | 256 | static int file_mips_gp32 = -1; |
a325df1d TS |
257 | |
258 | /* True if -mfp32 was passed. */ | |
a8e8e863 | 259 | static int file_mips_fp32 = -1; |
a325df1d | 260 | |
037b32b9 AN |
261 | /* 1 if -msoft-float, 0 if -mhard-float. The default is 0. */ |
262 | static int file_mips_soft_float = 0; | |
263 | ||
264 | /* 1 if -msingle-float, 0 if -mdouble-float. The default is 0. */ | |
265 | static int file_mips_single_float = 0; | |
252b5132 | 266 | |
e972090a NC |
267 | static struct mips_set_options mips_opts = |
268 | { | |
846ef2d0 | 269 | /* isa */ ISA_UNKNOWN, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1, |
b015e599 AP |
270 | /* noreorder */ 0, /* at */ ATREG, /* warn_about_macros */ 0, |
271 | /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* gp32 */ 0, | |
272 | /* fp32 */ 0, /* arch */ CPU_UNKNOWN, /* sym32 */ FALSE, | |
273 | /* soft_float */ FALSE, /* single_float */ FALSE | |
e7af610e | 274 | }; |
252b5132 | 275 | |
846ef2d0 RS |
276 | /* The set of ASEs that were selected on the command line, either |
277 | explicitly via ASE options or implicitly through things like -march. */ | |
278 | static unsigned int file_ase; | |
279 | ||
280 | /* Which bits of file_ase were explicitly set or cleared by ASE options. */ | |
281 | static unsigned int file_ase_explicit; | |
282 | ||
252b5132 RH |
283 | /* These variables are filled in with the masks of registers used. |
284 | The object format code reads them and puts them in the appropriate | |
285 | place. */ | |
286 | unsigned long mips_gprmask; | |
287 | unsigned long mips_cprmask[4]; | |
288 | ||
289 | /* MIPS ISA we are using for this output file. */ | |
e7af610e | 290 | static int file_mips_isa = ISA_UNKNOWN; |
252b5132 | 291 | |
738f4d98 | 292 | /* True if any MIPS16 code was produced. */ |
a4672219 TS |
293 | static int file_ase_mips16; |
294 | ||
3994f87e TS |
295 | #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \ |
296 | || mips_opts.isa == ISA_MIPS32R2 \ | |
297 | || mips_opts.isa == ISA_MIPS64 \ | |
298 | || mips_opts.isa == ISA_MIPS64R2) | |
299 | ||
df58fc94 RS |
300 | /* True if any microMIPS code was produced. */ |
301 | static int file_ase_micromips; | |
302 | ||
b12dd2e4 CF |
303 | /* True if we want to create R_MIPS_JALR for jalr $25. */ |
304 | #ifdef TE_IRIX | |
1180b5a4 | 305 | #define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI |
b12dd2e4 | 306 | #else |
1180b5a4 RS |
307 | /* As a GNU extension, we use R_MIPS_JALR for o32 too. However, |
308 | because there's no place for any addend, the only acceptable | |
309 | expression is a bare symbol. */ | |
310 | #define MIPS_JALR_HINT_P(EXPR) \ | |
311 | (!HAVE_IN_PLACE_ADDENDS \ | |
312 | || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0)) | |
b12dd2e4 CF |
313 | #endif |
314 | ||
ec68c924 | 315 | /* The argument of the -march= flag. The architecture we are assembling. */ |
fef14a42 | 316 | static int file_mips_arch = CPU_UNKNOWN; |
316f5878 | 317 | static const char *mips_arch_string; |
ec68c924 EC |
318 | |
319 | /* The argument of the -mtune= flag. The architecture for which we | |
320 | are optimizing. */ | |
321 | static int mips_tune = CPU_UNKNOWN; | |
316f5878 | 322 | static const char *mips_tune_string; |
ec68c924 | 323 | |
316f5878 | 324 | /* True when generating 32-bit code for a 64-bit processor. */ |
252b5132 RH |
325 | static int mips_32bitmode = 0; |
326 | ||
316f5878 RS |
327 | /* True if the given ABI requires 32-bit registers. */ |
328 | #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI) | |
329 | ||
330 | /* Likewise 64-bit registers. */ | |
707bfff6 TS |
331 | #define ABI_NEEDS_64BIT_REGS(ABI) \ |
332 | ((ABI) == N32_ABI \ | |
333 | || (ABI) == N64_ABI \ | |
316f5878 RS |
334 | || (ABI) == O64_ABI) |
335 | ||
ad3fea08 | 336 | /* Return true if ISA supports 64 bit wide gp registers. */ |
707bfff6 TS |
337 | #define ISA_HAS_64BIT_REGS(ISA) \ |
338 | ((ISA) == ISA_MIPS3 \ | |
339 | || (ISA) == ISA_MIPS4 \ | |
340 | || (ISA) == ISA_MIPS5 \ | |
341 | || (ISA) == ISA_MIPS64 \ | |
342 | || (ISA) == ISA_MIPS64R2) | |
9ce8a5dd | 343 | |
ad3fea08 TS |
344 | /* Return true if ISA supports 64 bit wide float registers. */ |
345 | #define ISA_HAS_64BIT_FPRS(ISA) \ | |
346 | ((ISA) == ISA_MIPS3 \ | |
347 | || (ISA) == ISA_MIPS4 \ | |
348 | || (ISA) == ISA_MIPS5 \ | |
349 | || (ISA) == ISA_MIPS32R2 \ | |
350 | || (ISA) == ISA_MIPS64 \ | |
351 | || (ISA) == ISA_MIPS64R2) | |
352 | ||
af7ee8bf CD |
353 | /* Return true if ISA supports 64-bit right rotate (dror et al.) |
354 | instructions. */ | |
707bfff6 | 355 | #define ISA_HAS_DROR(ISA) \ |
df58fc94 RS |
356 | ((ISA) == ISA_MIPS64R2 \ |
357 | || (mips_opts.micromips \ | |
358 | && ISA_HAS_64BIT_REGS (ISA)) \ | |
359 | ) | |
af7ee8bf CD |
360 | |
361 | /* Return true if ISA supports 32-bit right rotate (ror et al.) | |
362 | instructions. */ | |
707bfff6 TS |
363 | #define ISA_HAS_ROR(ISA) \ |
364 | ((ISA) == ISA_MIPS32R2 \ | |
365 | || (ISA) == ISA_MIPS64R2 \ | |
846ef2d0 | 366 | || (mips_opts.ase & ASE_SMARTMIPS) \ |
df58fc94 RS |
367 | || mips_opts.micromips \ |
368 | ) | |
707bfff6 | 369 | |
7455baf8 TS |
370 | /* Return true if ISA supports single-precision floats in odd registers. */ |
371 | #define ISA_HAS_ODD_SINGLE_FPR(ISA) \ | |
372 | ((ISA) == ISA_MIPS32 \ | |
373 | || (ISA) == ISA_MIPS32R2 \ | |
374 | || (ISA) == ISA_MIPS64 \ | |
375 | || (ISA) == ISA_MIPS64R2) | |
af7ee8bf | 376 | |
ad3fea08 TS |
377 | /* Return true if ISA supports move to/from high part of a 64-bit |
378 | floating-point register. */ | |
379 | #define ISA_HAS_MXHC1(ISA) \ | |
380 | ((ISA) == ISA_MIPS32R2 \ | |
381 | || (ISA) == ISA_MIPS64R2) | |
382 | ||
e013f690 | 383 | #define HAVE_32BIT_GPRS \ |
ad3fea08 | 384 | (mips_opts.gp32 || !ISA_HAS_64BIT_REGS (mips_opts.isa)) |
ca4e0257 | 385 | |
e013f690 | 386 | #define HAVE_32BIT_FPRS \ |
ad3fea08 | 387 | (mips_opts.fp32 || !ISA_HAS_64BIT_FPRS (mips_opts.isa)) |
ca4e0257 | 388 | |
ad3fea08 TS |
389 | #define HAVE_64BIT_GPRS (!HAVE_32BIT_GPRS) |
390 | #define HAVE_64BIT_FPRS (!HAVE_32BIT_FPRS) | |
ca4e0257 | 391 | |
316f5878 | 392 | #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI) |
e013f690 | 393 | |
316f5878 | 394 | #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI) |
e013f690 | 395 | |
3b91255e RS |
396 | /* True if relocations are stored in-place. */ |
397 | #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI) | |
398 | ||
aed1a261 RS |
399 | /* The ABI-derived address size. */ |
400 | #define HAVE_64BIT_ADDRESSES \ | |
401 | (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI)) | |
402 | #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES) | |
e013f690 | 403 | |
aed1a261 RS |
404 | /* The size of symbolic constants (i.e., expressions of the form |
405 | "SYMBOL" or "SYMBOL + OFFSET"). */ | |
406 | #define HAVE_32BIT_SYMBOLS \ | |
407 | (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32) | |
408 | #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS) | |
ca4e0257 | 409 | |
b7c7d6c1 TS |
410 | /* Addresses are loaded in different ways, depending on the address size |
411 | in use. The n32 ABI Documentation also mandates the use of additions | |
412 | with overflow checking, but existing implementations don't follow it. */ | |
f899b4b8 | 413 | #define ADDRESS_ADD_INSN \ |
b7c7d6c1 | 414 | (HAVE_32BIT_ADDRESSES ? "addu" : "daddu") |
f899b4b8 TS |
415 | |
416 | #define ADDRESS_ADDI_INSN \ | |
b7c7d6c1 | 417 | (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu") |
f899b4b8 TS |
418 | |
419 | #define ADDRESS_LOAD_INSN \ | |
420 | (HAVE_32BIT_ADDRESSES ? "lw" : "ld") | |
421 | ||
422 | #define ADDRESS_STORE_INSN \ | |
423 | (HAVE_32BIT_ADDRESSES ? "sw" : "sd") | |
424 | ||
a4672219 | 425 | /* Return true if the given CPU supports the MIPS16 ASE. */ |
3396de36 TS |
426 | #define CPU_HAS_MIPS16(cpu) \ |
427 | (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \ | |
428 | || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0) | |
a4672219 | 429 | |
2309ddf2 | 430 | /* Return true if the given CPU supports the microMIPS ASE. */ |
df58fc94 RS |
431 | #define CPU_HAS_MICROMIPS(cpu) 0 |
432 | ||
60b63b72 RS |
433 | /* True if CPU has a dror instruction. */ |
434 | #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500) | |
435 | ||
436 | /* True if CPU has a ror instruction. */ | |
437 | #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU) | |
438 | ||
dd6a37e7 | 439 | /* True if CPU is in the Octeon family */ |
432233b3 | 440 | #define CPU_IS_OCTEON(CPU) ((CPU) == CPU_OCTEON || (CPU) == CPU_OCTEONP || (CPU) == CPU_OCTEON2) |
dd6a37e7 | 441 | |
dd3cbb7e | 442 | /* True if CPU has seq/sne and seqi/snei instructions. */ |
dd6a37e7 | 443 | #define CPU_HAS_SEQ(CPU) (CPU_IS_OCTEON (CPU)) |
dd3cbb7e | 444 | |
0aa27725 RS |
445 | /* True, if CPU has support for ldc1 and sdc1. */ |
446 | #define CPU_HAS_LDC1_SDC1(CPU) \ | |
447 | ((mips_opts.isa != ISA_MIPS1) && ((CPU) != CPU_R5900)) | |
448 | ||
c8978940 CD |
449 | /* True if mflo and mfhi can be immediately followed by instructions |
450 | which write to the HI and LO registers. | |
451 | ||
452 | According to MIPS specifications, MIPS ISAs I, II, and III need | |
453 | (at least) two instructions between the reads of HI/LO and | |
454 | instructions which write them, and later ISAs do not. Contradicting | |
455 | the MIPS specifications, some MIPS IV processor user manuals (e.g. | |
456 | the UM for the NEC Vr5000) document needing the instructions between | |
457 | HI/LO reads and writes, as well. Therefore, we declare only MIPS32, | |
458 | MIPS64 and later ISAs to have the interlocks, plus any specific | |
459 | earlier-ISA CPUs for which CPU documentation declares that the | |
460 | instructions are really interlocked. */ | |
461 | #define hilo_interlocks \ | |
462 | (mips_opts.isa == ISA_MIPS32 \ | |
463 | || mips_opts.isa == ISA_MIPS32R2 \ | |
464 | || mips_opts.isa == ISA_MIPS64 \ | |
465 | || mips_opts.isa == ISA_MIPS64R2 \ | |
466 | || mips_opts.arch == CPU_R4010 \ | |
e407c74b | 467 | || mips_opts.arch == CPU_R5900 \ |
c8978940 CD |
468 | || mips_opts.arch == CPU_R10000 \ |
469 | || mips_opts.arch == CPU_R12000 \ | |
3aa3176b TS |
470 | || mips_opts.arch == CPU_R14000 \ |
471 | || mips_opts.arch == CPU_R16000 \ | |
c8978940 | 472 | || mips_opts.arch == CPU_RM7000 \ |
c8978940 | 473 | || mips_opts.arch == CPU_VR5500 \ |
df58fc94 | 474 | || mips_opts.micromips \ |
c8978940 | 475 | ) |
252b5132 RH |
476 | |
477 | /* Whether the processor uses hardware interlocks to protect reads | |
81912461 ILT |
478 | from the GPRs after they are loaded from memory, and thus does not |
479 | require nops to be inserted. This applies to instructions marked | |
480 | INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA | |
df58fc94 RS |
481 | level I and microMIPS mode instructions are always interlocked. */ |
482 | #define gpr_interlocks \ | |
483 | (mips_opts.isa != ISA_MIPS1 \ | |
484 | || mips_opts.arch == CPU_R3900 \ | |
e407c74b | 485 | || mips_opts.arch == CPU_R5900 \ |
df58fc94 RS |
486 | || mips_opts.micromips \ |
487 | ) | |
252b5132 | 488 | |
81912461 ILT |
489 | /* Whether the processor uses hardware interlocks to avoid delays |
490 | required by coprocessor instructions, and thus does not require | |
491 | nops to be inserted. This applies to instructions marked | |
492 | INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays | |
493 | between instructions marked INSN_WRITE_COND_CODE and ones marked | |
494 | INSN_READ_COND_CODE. These nops are only required at MIPS ISA | |
df58fc94 RS |
495 | levels I, II, and III and microMIPS mode instructions are always |
496 | interlocked. */ | |
bdaaa2e1 | 497 | /* Itbl support may require additional care here. */ |
81912461 ILT |
498 | #define cop_interlocks \ |
499 | ((mips_opts.isa != ISA_MIPS1 \ | |
500 | && mips_opts.isa != ISA_MIPS2 \ | |
501 | && mips_opts.isa != ISA_MIPS3) \ | |
502 | || mips_opts.arch == CPU_R4300 \ | |
df58fc94 | 503 | || mips_opts.micromips \ |
81912461 ILT |
504 | ) |
505 | ||
506 | /* Whether the processor uses hardware interlocks to protect reads | |
507 | from coprocessor registers after they are loaded from memory, and | |
508 | thus does not require nops to be inserted. This applies to | |
509 | instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only | |
df58fc94 RS |
510 | requires at MIPS ISA level I and microMIPS mode instructions are |
511 | always interlocked. */ | |
512 | #define cop_mem_interlocks \ | |
513 | (mips_opts.isa != ISA_MIPS1 \ | |
514 | || mips_opts.micromips \ | |
515 | ) | |
252b5132 | 516 | |
6b76fefe CM |
517 | /* Is this a mfhi or mflo instruction? */ |
518 | #define MF_HILO_INSN(PINFO) \ | |
b19e8a9b AN |
519 | ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO)) |
520 | ||
df58fc94 RS |
521 | /* Whether code compression (either of the MIPS16 or the microMIPS ASEs) |
522 | has been selected. This implies, in particular, that addresses of text | |
523 | labels have their LSB set. */ | |
524 | #define HAVE_CODE_COMPRESSION \ | |
525 | ((mips_opts.mips16 | mips_opts.micromips) != 0) | |
526 | ||
252b5132 RH |
527 | /* MIPS PIC level. */ |
528 | ||
a161fe53 | 529 | enum mips_pic_level mips_pic; |
252b5132 | 530 | |
c9914766 | 531 | /* 1 if we should generate 32 bit offsets from the $gp register in |
252b5132 | 532 | SVR4_PIC mode. Currently has no meaning in other modes. */ |
c9914766 | 533 | static int mips_big_got = 0; |
252b5132 RH |
534 | |
535 | /* 1 if trap instructions should used for overflow rather than break | |
536 | instructions. */ | |
c9914766 | 537 | static int mips_trap = 0; |
252b5132 | 538 | |
119d663a | 539 | /* 1 if double width floating point constants should not be constructed |
b6ff326e | 540 | by assembling two single width halves into two single width floating |
119d663a NC |
541 | point registers which just happen to alias the double width destination |
542 | register. On some architectures this aliasing can be disabled by a bit | |
d547a75e | 543 | in the status register, and the setting of this bit cannot be determined |
119d663a NC |
544 | automatically at assemble time. */ |
545 | static int mips_disable_float_construction; | |
546 | ||
252b5132 RH |
547 | /* Non-zero if any .set noreorder directives were used. */ |
548 | ||
549 | static int mips_any_noreorder; | |
550 | ||
6b76fefe CM |
551 | /* Non-zero if nops should be inserted when the register referenced in |
552 | an mfhi/mflo instruction is read in the next two instructions. */ | |
553 | static int mips_7000_hilo_fix; | |
554 | ||
02ffd3e4 | 555 | /* The size of objects in the small data section. */ |
156c2f8b | 556 | static unsigned int g_switch_value = 8; |
252b5132 RH |
557 | /* Whether the -G option was used. */ |
558 | static int g_switch_seen = 0; | |
559 | ||
560 | #define N_RMASK 0xc4 | |
561 | #define N_VFP 0xd4 | |
562 | ||
563 | /* If we can determine in advance that GP optimization won't be | |
564 | possible, we can skip the relaxation stuff that tries to produce | |
565 | GP-relative references. This makes delay slot optimization work | |
566 | better. | |
567 | ||
568 | This function can only provide a guess, but it seems to work for | |
fba2b7f9 GK |
569 | gcc output. It needs to guess right for gcc, otherwise gcc |
570 | will put what it thinks is a GP-relative instruction in a branch | |
571 | delay slot. | |
252b5132 RH |
572 | |
573 | I don't know if a fix is needed for the SVR4_PIC mode. I've only | |
574 | fixed it for the non-PIC mode. KR 95/04/07 */ | |
17a2f251 | 575 | static int nopic_need_relax (symbolS *, int); |
252b5132 RH |
576 | |
577 | /* handle of the OPCODE hash table */ | |
578 | static struct hash_control *op_hash = NULL; | |
579 | ||
580 | /* The opcode hash table we use for the mips16. */ | |
581 | static struct hash_control *mips16_op_hash = NULL; | |
582 | ||
df58fc94 RS |
583 | /* The opcode hash table we use for the microMIPS ASE. */ |
584 | static struct hash_control *micromips_op_hash = NULL; | |
585 | ||
252b5132 RH |
586 | /* This array holds the chars that always start a comment. If the |
587 | pre-processor is disabled, these aren't very useful */ | |
588 | const char comment_chars[] = "#"; | |
589 | ||
590 | /* This array holds the chars that only start a comment at the beginning of | |
591 | a line. If the line seems to have the form '# 123 filename' | |
592 | .line and .file directives will appear in the pre-processed output */ | |
593 | /* Note that input_file.c hand checks for '#' at the beginning of the | |
594 | first line of the input file. This is because the compiler outputs | |
bdaaa2e1 | 595 | #NO_APP at the beginning of its output. */ |
252b5132 RH |
596 | /* Also note that C style comments are always supported. */ |
597 | const char line_comment_chars[] = "#"; | |
598 | ||
bdaaa2e1 | 599 | /* This array holds machine specific line separator characters. */ |
63a0b638 | 600 | const char line_separator_chars[] = ";"; |
252b5132 RH |
601 | |
602 | /* Chars that can be used to separate mant from exp in floating point nums */ | |
603 | const char EXP_CHARS[] = "eE"; | |
604 | ||
605 | /* Chars that mean this number is a floating point constant */ | |
606 | /* As in 0f12.456 */ | |
607 | /* or 0d1.2345e12 */ | |
608 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; | |
609 | ||
610 | /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be | |
611 | changed in read.c . Ideally it shouldn't have to know about it at all, | |
612 | but nothing is ideal around here. | |
613 | */ | |
614 | ||
615 | static char *insn_error; | |
616 | ||
617 | static int auto_align = 1; | |
618 | ||
619 | /* When outputting SVR4 PIC code, the assembler needs to know the | |
620 | offset in the stack frame from which to restore the $gp register. | |
621 | This is set by the .cprestore pseudo-op, and saved in this | |
622 | variable. */ | |
623 | static offsetT mips_cprestore_offset = -1; | |
624 | ||
67c1ffbe | 625 | /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some |
6478892d | 626 | more optimizations, it can use a register value instead of a memory-saved |
956cd1d6 | 627 | offset and even an other register than $gp as global pointer. */ |
6478892d TS |
628 | static offsetT mips_cpreturn_offset = -1; |
629 | static int mips_cpreturn_register = -1; | |
630 | static int mips_gp_register = GP; | |
def2e0dd | 631 | static int mips_gprel_offset = 0; |
6478892d | 632 | |
7a621144 DJ |
633 | /* Whether mips_cprestore_offset has been set in the current function |
634 | (or whether it has already been warned about, if not). */ | |
635 | static int mips_cprestore_valid = 0; | |
636 | ||
252b5132 RH |
637 | /* This is the register which holds the stack frame, as set by the |
638 | .frame pseudo-op. This is needed to implement .cprestore. */ | |
639 | static int mips_frame_reg = SP; | |
640 | ||
7a621144 DJ |
641 | /* Whether mips_frame_reg has been set in the current function |
642 | (or whether it has already been warned about, if not). */ | |
643 | static int mips_frame_reg_valid = 0; | |
644 | ||
252b5132 RH |
645 | /* To output NOP instructions correctly, we need to keep information |
646 | about the previous two instructions. */ | |
647 | ||
648 | /* Whether we are optimizing. The default value of 2 means to remove | |
649 | unneeded NOPs and swap branch instructions when possible. A value | |
650 | of 1 means to not swap branches. A value of 0 means to always | |
651 | insert NOPs. */ | |
652 | static int mips_optimize = 2; | |
653 | ||
654 | /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is | |
655 | equivalent to seeing no -g option at all. */ | |
656 | static int mips_debug = 0; | |
657 | ||
7d8e00cf RS |
658 | /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */ |
659 | #define MAX_VR4130_NOPS 4 | |
660 | ||
661 | /* The maximum number of NOPs needed to fill delay slots. */ | |
662 | #define MAX_DELAY_NOPS 2 | |
663 | ||
664 | /* The maximum number of NOPs needed for any purpose. */ | |
665 | #define MAX_NOPS 4 | |
71400594 RS |
666 | |
667 | /* A list of previous instructions, with index 0 being the most recent. | |
668 | We need to look back MAX_NOPS instructions when filling delay slots | |
669 | or working around processor errata. We need to look back one | |
670 | instruction further if we're thinking about using history[0] to | |
671 | fill a branch delay slot. */ | |
672 | static struct mips_cl_insn history[1 + MAX_NOPS]; | |
252b5132 | 673 | |
1e915849 | 674 | /* Nop instructions used by emit_nop. */ |
df58fc94 RS |
675 | static struct mips_cl_insn nop_insn; |
676 | static struct mips_cl_insn mips16_nop_insn; | |
677 | static struct mips_cl_insn micromips_nop16_insn; | |
678 | static struct mips_cl_insn micromips_nop32_insn; | |
1e915849 RS |
679 | |
680 | /* The appropriate nop for the current mode. */ | |
df58fc94 RS |
681 | #define NOP_INSN (mips_opts.mips16 ? &mips16_nop_insn \ |
682 | : (mips_opts.micromips ? µmips_nop16_insn : &nop_insn)) | |
683 | ||
684 | /* The size of NOP_INSN in bytes. */ | |
685 | #define NOP_INSN_SIZE (HAVE_CODE_COMPRESSION ? 2 : 4) | |
252b5132 | 686 | |
252b5132 RH |
687 | /* If this is set, it points to a frag holding nop instructions which |
688 | were inserted before the start of a noreorder section. If those | |
689 | nops turn out to be unnecessary, the size of the frag can be | |
690 | decreased. */ | |
691 | static fragS *prev_nop_frag; | |
692 | ||
693 | /* The number of nop instructions we created in prev_nop_frag. */ | |
694 | static int prev_nop_frag_holds; | |
695 | ||
696 | /* The number of nop instructions that we know we need in | |
bdaaa2e1 | 697 | prev_nop_frag. */ |
252b5132 RH |
698 | static int prev_nop_frag_required; |
699 | ||
700 | /* The number of instructions we've seen since prev_nop_frag. */ | |
701 | static int prev_nop_frag_since; | |
702 | ||
e8044f35 RS |
703 | /* Relocations against symbols are sometimes done in two parts, with a HI |
704 | relocation and a LO relocation. Each relocation has only 16 bits of | |
705 | space to store an addend. This means that in order for the linker to | |
706 | handle carries correctly, it must be able to locate both the HI and | |
707 | the LO relocation. This means that the relocations must appear in | |
708 | order in the relocation table. | |
252b5132 RH |
709 | |
710 | In order to implement this, we keep track of each unmatched HI | |
711 | relocation. We then sort them so that they immediately precede the | |
bdaaa2e1 | 712 | corresponding LO relocation. */ |
252b5132 | 713 | |
e972090a NC |
714 | struct mips_hi_fixup |
715 | { | |
252b5132 RH |
716 | /* Next HI fixup. */ |
717 | struct mips_hi_fixup *next; | |
718 | /* This fixup. */ | |
719 | fixS *fixp; | |
720 | /* The section this fixup is in. */ | |
721 | segT seg; | |
722 | }; | |
723 | ||
724 | /* The list of unmatched HI relocs. */ | |
725 | ||
726 | static struct mips_hi_fixup *mips_hi_fixup_list; | |
727 | ||
64bdfcaf RS |
728 | /* The frag containing the last explicit relocation operator. |
729 | Null if explicit relocations have not been used. */ | |
730 | ||
731 | static fragS *prev_reloc_op_frag; | |
732 | ||
252b5132 RH |
733 | /* Map normal MIPS register numbers to mips16 register numbers. */ |
734 | ||
735 | #define X ILLEGAL_REG | |
e972090a NC |
736 | static const int mips32_to_16_reg_map[] = |
737 | { | |
252b5132 RH |
738 | X, X, 2, 3, 4, 5, 6, 7, |
739 | X, X, X, X, X, X, X, X, | |
740 | 0, 1, X, X, X, X, X, X, | |
741 | X, X, X, X, X, X, X, X | |
742 | }; | |
743 | #undef X | |
744 | ||
745 | /* Map mips16 register numbers to normal MIPS register numbers. */ | |
746 | ||
e972090a NC |
747 | static const unsigned int mips16_to_32_reg_map[] = |
748 | { | |
252b5132 RH |
749 | 16, 17, 2, 3, 4, 5, 6, 7 |
750 | }; | |
60b63b72 | 751 | |
df58fc94 RS |
752 | /* Map normal MIPS register numbers to microMIPS register numbers. */ |
753 | ||
754 | #define mips32_to_micromips_reg_b_map mips32_to_16_reg_map | |
755 | #define mips32_to_micromips_reg_c_map mips32_to_16_reg_map | |
756 | #define mips32_to_micromips_reg_d_map mips32_to_16_reg_map | |
757 | #define mips32_to_micromips_reg_e_map mips32_to_16_reg_map | |
758 | #define mips32_to_micromips_reg_f_map mips32_to_16_reg_map | |
759 | #define mips32_to_micromips_reg_g_map mips32_to_16_reg_map | |
760 | #define mips32_to_micromips_reg_l_map mips32_to_16_reg_map | |
761 | ||
762 | #define X ILLEGAL_REG | |
763 | /* reg type h: 4, 5, 6. */ | |
764 | static const int mips32_to_micromips_reg_h_map[] = | |
765 | { | |
766 | X, X, X, X, 4, 5, 6, X, | |
767 | X, X, X, X, X, X, X, X, | |
768 | X, X, X, X, X, X, X, X, | |
769 | X, X, X, X, X, X, X, X | |
770 | }; | |
771 | ||
772 | /* reg type m: 0, 17, 2, 3, 16, 18, 19, 20. */ | |
773 | static const int mips32_to_micromips_reg_m_map[] = | |
774 | { | |
775 | 0, X, 2, 3, X, X, X, X, | |
776 | X, X, X, X, X, X, X, X, | |
777 | 4, 1, 5, 6, 7, X, X, X, | |
778 | X, X, X, X, X, X, X, X | |
779 | }; | |
780 | ||
781 | /* reg type q: 0, 2-7. 17. */ | |
782 | static const int mips32_to_micromips_reg_q_map[] = | |
783 | { | |
784 | 0, X, 2, 3, 4, 5, 6, 7, | |
785 | X, X, X, X, X, X, X, X, | |
786 | X, 1, X, X, X, X, X, X, | |
787 | X, X, X, X, X, X, X, X | |
788 | }; | |
789 | ||
790 | #define mips32_to_micromips_reg_n_map mips32_to_micromips_reg_m_map | |
791 | #undef X | |
792 | ||
793 | /* Map microMIPS register numbers to normal MIPS register numbers. */ | |
794 | ||
795 | #define micromips_to_32_reg_b_map mips16_to_32_reg_map | |
796 | #define micromips_to_32_reg_c_map mips16_to_32_reg_map | |
797 | #define micromips_to_32_reg_d_map mips16_to_32_reg_map | |
798 | #define micromips_to_32_reg_e_map mips16_to_32_reg_map | |
799 | #define micromips_to_32_reg_f_map mips16_to_32_reg_map | |
800 | #define micromips_to_32_reg_g_map mips16_to_32_reg_map | |
801 | ||
802 | /* The microMIPS registers with type h. */ | |
803 | static const unsigned int micromips_to_32_reg_h_map[] = | |
804 | { | |
805 | 5, 5, 6, 4, 4, 4, 4, 4 | |
806 | }; | |
807 | ||
808 | /* The microMIPS registers with type i. */ | |
809 | static const unsigned int micromips_to_32_reg_i_map[] = | |
810 | { | |
811 | 6, 7, 7, 21, 22, 5, 6, 7 | |
812 | }; | |
813 | ||
814 | #define micromips_to_32_reg_l_map mips16_to_32_reg_map | |
815 | ||
816 | /* The microMIPS registers with type m. */ | |
817 | static const unsigned int micromips_to_32_reg_m_map[] = | |
818 | { | |
819 | 0, 17, 2, 3, 16, 18, 19, 20 | |
820 | }; | |
821 | ||
822 | #define micromips_to_32_reg_n_map micromips_to_32_reg_m_map | |
823 | ||
824 | /* The microMIPS registers with type q. */ | |
825 | static const unsigned int micromips_to_32_reg_q_map[] = | |
826 | { | |
827 | 0, 17, 2, 3, 4, 5, 6, 7 | |
828 | }; | |
829 | ||
830 | /* microMIPS imm type B. */ | |
831 | static const int micromips_imm_b_map[] = | |
832 | { | |
833 | 1, 4, 8, 12, 16, 20, 24, -1 | |
834 | }; | |
835 | ||
836 | /* microMIPS imm type C. */ | |
837 | static const int micromips_imm_c_map[] = | |
838 | { | |
839 | 128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64, 255, 32768, 65535 | |
840 | }; | |
841 | ||
71400594 RS |
842 | /* Classifies the kind of instructions we're interested in when |
843 | implementing -mfix-vr4120. */ | |
c67a084a NC |
844 | enum fix_vr4120_class |
845 | { | |
71400594 RS |
846 | FIX_VR4120_MACC, |
847 | FIX_VR4120_DMACC, | |
848 | FIX_VR4120_MULT, | |
849 | FIX_VR4120_DMULT, | |
850 | FIX_VR4120_DIV, | |
851 | FIX_VR4120_MTHILO, | |
852 | NUM_FIX_VR4120_CLASSES | |
853 | }; | |
854 | ||
c67a084a NC |
855 | /* ...likewise -mfix-loongson2f-jump. */ |
856 | static bfd_boolean mips_fix_loongson2f_jump; | |
857 | ||
858 | /* ...likewise -mfix-loongson2f-nop. */ | |
859 | static bfd_boolean mips_fix_loongson2f_nop; | |
860 | ||
861 | /* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */ | |
862 | static bfd_boolean mips_fix_loongson2f; | |
863 | ||
71400594 RS |
864 | /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if |
865 | there must be at least one other instruction between an instruction | |
866 | of type X and an instruction of type Y. */ | |
867 | static unsigned int vr4120_conflicts[NUM_FIX_VR4120_CLASSES]; | |
868 | ||
869 | /* True if -mfix-vr4120 is in force. */ | |
d766e8ec | 870 | static int mips_fix_vr4120; |
4a6a3df4 | 871 | |
7d8e00cf RS |
872 | /* ...likewise -mfix-vr4130. */ |
873 | static int mips_fix_vr4130; | |
874 | ||
6a32d874 CM |
875 | /* ...likewise -mfix-24k. */ |
876 | static int mips_fix_24k; | |
877 | ||
d954098f DD |
878 | /* ...likewise -mfix-cn63xxp1 */ |
879 | static bfd_boolean mips_fix_cn63xxp1; | |
880 | ||
4a6a3df4 AO |
881 | /* We don't relax branches by default, since this causes us to expand |
882 | `la .l2 - .l1' if there's a branch between .l1 and .l2, because we | |
883 | fail to compute the offset before expanding the macro to the most | |
884 | efficient expansion. */ | |
885 | ||
886 | static int mips_relax_branch; | |
252b5132 | 887 | \f |
4d7206a2 RS |
888 | /* The expansion of many macros depends on the type of symbol that |
889 | they refer to. For example, when generating position-dependent code, | |
890 | a macro that refers to a symbol may have two different expansions, | |
891 | one which uses GP-relative addresses and one which uses absolute | |
892 | addresses. When generating SVR4-style PIC, a macro may have | |
893 | different expansions for local and global symbols. | |
894 | ||
895 | We handle these situations by generating both sequences and putting | |
896 | them in variant frags. In position-dependent code, the first sequence | |
897 | will be the GP-relative one and the second sequence will be the | |
898 | absolute one. In SVR4 PIC, the first sequence will be for global | |
899 | symbols and the second will be for local symbols. | |
900 | ||
584892a6 RS |
901 | The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and |
902 | SECOND are the lengths of the two sequences in bytes. These fields | |
903 | can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition, | |
904 | the subtype has the following flags: | |
4d7206a2 | 905 | |
584892a6 RS |
906 | RELAX_USE_SECOND |
907 | Set if it has been decided that we should use the second | |
908 | sequence instead of the first. | |
909 | ||
910 | RELAX_SECOND_LONGER | |
911 | Set in the first variant frag if the macro's second implementation | |
912 | is longer than its first. This refers to the macro as a whole, | |
913 | not an individual relaxation. | |
914 | ||
915 | RELAX_NOMACRO | |
916 | Set in the first variant frag if the macro appeared in a .set nomacro | |
917 | block and if one alternative requires a warning but the other does not. | |
918 | ||
919 | RELAX_DELAY_SLOT | |
920 | Like RELAX_NOMACRO, but indicates that the macro appears in a branch | |
921 | delay slot. | |
4d7206a2 | 922 | |
df58fc94 RS |
923 | RELAX_DELAY_SLOT_16BIT |
924 | Like RELAX_DELAY_SLOT, but indicates that the delay slot requires a | |
925 | 16-bit instruction. | |
926 | ||
927 | RELAX_DELAY_SLOT_SIZE_FIRST | |
928 | Like RELAX_DELAY_SLOT, but indicates that the first implementation of | |
929 | the macro is of the wrong size for the branch delay slot. | |
930 | ||
931 | RELAX_DELAY_SLOT_SIZE_SECOND | |
932 | Like RELAX_DELAY_SLOT, but indicates that the second implementation of | |
933 | the macro is of the wrong size for the branch delay slot. | |
934 | ||
4d7206a2 RS |
935 | The frag's "opcode" points to the first fixup for relaxable code. |
936 | ||
937 | Relaxable macros are generated using a sequence such as: | |
938 | ||
939 | relax_start (SYMBOL); | |
940 | ... generate first expansion ... | |
941 | relax_switch (); | |
942 | ... generate second expansion ... | |
943 | relax_end (); | |
944 | ||
945 | The code and fixups for the unwanted alternative are discarded | |
946 | by md_convert_frag. */ | |
584892a6 | 947 | #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND)) |
4d7206a2 | 948 | |
584892a6 RS |
949 | #define RELAX_FIRST(X) (((X) >> 8) & 0xff) |
950 | #define RELAX_SECOND(X) ((X) & 0xff) | |
951 | #define RELAX_USE_SECOND 0x10000 | |
952 | #define RELAX_SECOND_LONGER 0x20000 | |
953 | #define RELAX_NOMACRO 0x40000 | |
954 | #define RELAX_DELAY_SLOT 0x80000 | |
df58fc94 RS |
955 | #define RELAX_DELAY_SLOT_16BIT 0x100000 |
956 | #define RELAX_DELAY_SLOT_SIZE_FIRST 0x200000 | |
957 | #define RELAX_DELAY_SLOT_SIZE_SECOND 0x400000 | |
252b5132 | 958 | |
4a6a3df4 AO |
959 | /* Branch without likely bit. If label is out of range, we turn: |
960 | ||
961 | beq reg1, reg2, label | |
962 | delay slot | |
963 | ||
964 | into | |
965 | ||
966 | bne reg1, reg2, 0f | |
967 | nop | |
968 | j label | |
969 | 0: delay slot | |
970 | ||
971 | with the following opcode replacements: | |
972 | ||
973 | beq <-> bne | |
974 | blez <-> bgtz | |
975 | bltz <-> bgez | |
976 | bc1f <-> bc1t | |
977 | ||
978 | bltzal <-> bgezal (with jal label instead of j label) | |
979 | ||
980 | Even though keeping the delay slot instruction in the delay slot of | |
981 | the branch would be more efficient, it would be very tricky to do | |
982 | correctly, because we'd have to introduce a variable frag *after* | |
983 | the delay slot instruction, and expand that instead. Let's do it | |
984 | the easy way for now, even if the branch-not-taken case now costs | |
985 | one additional instruction. Out-of-range branches are not supposed | |
986 | to be common, anyway. | |
987 | ||
988 | Branch likely. If label is out of range, we turn: | |
989 | ||
990 | beql reg1, reg2, label | |
991 | delay slot (annulled if branch not taken) | |
992 | ||
993 | into | |
994 | ||
995 | beql reg1, reg2, 1f | |
996 | nop | |
997 | beql $0, $0, 2f | |
998 | nop | |
999 | 1: j[al] label | |
1000 | delay slot (executed only if branch taken) | |
1001 | 2: | |
1002 | ||
1003 | It would be possible to generate a shorter sequence by losing the | |
1004 | likely bit, generating something like: | |
b34976b6 | 1005 | |
4a6a3df4 AO |
1006 | bne reg1, reg2, 0f |
1007 | nop | |
1008 | j[al] label | |
1009 | delay slot (executed only if branch taken) | |
1010 | 0: | |
1011 | ||
1012 | beql -> bne | |
1013 | bnel -> beq | |
1014 | blezl -> bgtz | |
1015 | bgtzl -> blez | |
1016 | bltzl -> bgez | |
1017 | bgezl -> bltz | |
1018 | bc1fl -> bc1t | |
1019 | bc1tl -> bc1f | |
1020 | ||
1021 | bltzall -> bgezal (with jal label instead of j label) | |
1022 | bgezall -> bltzal (ditto) | |
1023 | ||
1024 | ||
1025 | but it's not clear that it would actually improve performance. */ | |
66b3e8da MR |
1026 | #define RELAX_BRANCH_ENCODE(at, uncond, likely, link, toofar) \ |
1027 | ((relax_substateT) \ | |
1028 | (0xc0000000 \ | |
1029 | | ((at) & 0x1f) \ | |
1030 | | ((toofar) ? 0x20 : 0) \ | |
1031 | | ((link) ? 0x40 : 0) \ | |
1032 | | ((likely) ? 0x80 : 0) \ | |
1033 | | ((uncond) ? 0x100 : 0))) | |
4a6a3df4 | 1034 | #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000) |
66b3e8da MR |
1035 | #define RELAX_BRANCH_UNCOND(i) (((i) & 0x100) != 0) |
1036 | #define RELAX_BRANCH_LIKELY(i) (((i) & 0x80) != 0) | |
1037 | #define RELAX_BRANCH_LINK(i) (((i) & 0x40) != 0) | |
1038 | #define RELAX_BRANCH_TOOFAR(i) (((i) & 0x20) != 0) | |
1039 | #define RELAX_BRANCH_AT(i) ((i) & 0x1f) | |
4a6a3df4 | 1040 | |
252b5132 RH |
1041 | /* For mips16 code, we use an entirely different form of relaxation. |
1042 | mips16 supports two versions of most instructions which take | |
1043 | immediate values: a small one which takes some small value, and a | |
1044 | larger one which takes a 16 bit value. Since branches also follow | |
1045 | this pattern, relaxing these values is required. | |
1046 | ||
1047 | We can assemble both mips16 and normal MIPS code in a single | |
1048 | object. Therefore, we need to support this type of relaxation at | |
1049 | the same time that we support the relaxation described above. We | |
1050 | use the high bit of the subtype field to distinguish these cases. | |
1051 | ||
1052 | The information we store for this type of relaxation is the | |
1053 | argument code found in the opcode file for this relocation, whether | |
1054 | the user explicitly requested a small or extended form, and whether | |
1055 | the relocation is in a jump or jal delay slot. That tells us the | |
1056 | size of the value, and how it should be stored. We also store | |
1057 | whether the fragment is considered to be extended or not. We also | |
1058 | store whether this is known to be a branch to a different section, | |
1059 | whether we have tried to relax this frag yet, and whether we have | |
1060 | ever extended a PC relative fragment because of a shift count. */ | |
1061 | #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \ | |
1062 | (0x80000000 \ | |
1063 | | ((type) & 0xff) \ | |
1064 | | ((small) ? 0x100 : 0) \ | |
1065 | | ((ext) ? 0x200 : 0) \ | |
1066 | | ((dslot) ? 0x400 : 0) \ | |
1067 | | ((jal_dslot) ? 0x800 : 0)) | |
4a6a3df4 | 1068 | #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000) |
252b5132 RH |
1069 | #define RELAX_MIPS16_TYPE(i) ((i) & 0xff) |
1070 | #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0) | |
1071 | #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0) | |
1072 | #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0) | |
1073 | #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0) | |
1074 | #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0) | |
1075 | #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000) | |
1076 | #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000) | |
1077 | #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0) | |
1078 | #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000) | |
1079 | #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000) | |
885add95 | 1080 | |
df58fc94 RS |
1081 | /* For microMIPS code, we use relaxation similar to one we use for |
1082 | MIPS16 code. Some instructions that take immediate values support | |
1083 | two encodings: a small one which takes some small value, and a | |
1084 | larger one which takes a 16 bit value. As some branches also follow | |
1085 | this pattern, relaxing these values is required. | |
1086 | ||
1087 | We can assemble both microMIPS and normal MIPS code in a single | |
1088 | object. Therefore, we need to support this type of relaxation at | |
1089 | the same time that we support the relaxation described above. We | |
1090 | use one of the high bits of the subtype field to distinguish these | |
1091 | cases. | |
1092 | ||
1093 | The information we store for this type of relaxation is the argument | |
1094 | code found in the opcode file for this relocation, the register | |
40209cad MR |
1095 | selected as the assembler temporary, whether the branch is |
1096 | unconditional, whether it is compact, whether it stores the link | |
1097 | address implicitly in $ra, whether relaxation of out-of-range 32-bit | |
1098 | branches to a sequence of instructions is enabled, and whether the | |
1099 | displacement of a branch is too large to fit as an immediate argument | |
1100 | of a 16-bit and a 32-bit branch, respectively. */ | |
1101 | #define RELAX_MICROMIPS_ENCODE(type, at, uncond, compact, link, \ | |
1102 | relax32, toofar16, toofar32) \ | |
1103 | (0x40000000 \ | |
1104 | | ((type) & 0xff) \ | |
1105 | | (((at) & 0x1f) << 8) \ | |
1106 | | ((uncond) ? 0x2000 : 0) \ | |
1107 | | ((compact) ? 0x4000 : 0) \ | |
1108 | | ((link) ? 0x8000 : 0) \ | |
1109 | | ((relax32) ? 0x10000 : 0) \ | |
1110 | | ((toofar16) ? 0x20000 : 0) \ | |
1111 | | ((toofar32) ? 0x40000 : 0)) | |
df58fc94 RS |
1112 | #define RELAX_MICROMIPS_P(i) (((i) & 0xc0000000) == 0x40000000) |
1113 | #define RELAX_MICROMIPS_TYPE(i) ((i) & 0xff) | |
1114 | #define RELAX_MICROMIPS_AT(i) (((i) >> 8) & 0x1f) | |
40209cad MR |
1115 | #define RELAX_MICROMIPS_UNCOND(i) (((i) & 0x2000) != 0) |
1116 | #define RELAX_MICROMIPS_COMPACT(i) (((i) & 0x4000) != 0) | |
1117 | #define RELAX_MICROMIPS_LINK(i) (((i) & 0x8000) != 0) | |
1118 | #define RELAX_MICROMIPS_RELAX32(i) (((i) & 0x10000) != 0) | |
1119 | ||
1120 | #define RELAX_MICROMIPS_TOOFAR16(i) (((i) & 0x20000) != 0) | |
1121 | #define RELAX_MICROMIPS_MARK_TOOFAR16(i) ((i) | 0x20000) | |
1122 | #define RELAX_MICROMIPS_CLEAR_TOOFAR16(i) ((i) & ~0x20000) | |
1123 | #define RELAX_MICROMIPS_TOOFAR32(i) (((i) & 0x40000) != 0) | |
1124 | #define RELAX_MICROMIPS_MARK_TOOFAR32(i) ((i) | 0x40000) | |
1125 | #define RELAX_MICROMIPS_CLEAR_TOOFAR32(i) ((i) & ~0x40000) | |
df58fc94 | 1126 | |
43c0598f RS |
1127 | /* Sign-extend 16-bit value X. */ |
1128 | #define SEXT_16BIT(X) ((((X) + 0x8000) & 0xffff) - 0x8000) | |
1129 | ||
885add95 CD |
1130 | /* Is the given value a sign-extended 32-bit value? */ |
1131 | #define IS_SEXT_32BIT_NUM(x) \ | |
1132 | (((x) &~ (offsetT) 0x7fffffff) == 0 \ | |
1133 | || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff)) | |
1134 | ||
1135 | /* Is the given value a sign-extended 16-bit value? */ | |
1136 | #define IS_SEXT_16BIT_NUM(x) \ | |
1137 | (((x) &~ (offsetT) 0x7fff) == 0 \ | |
1138 | || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff)) | |
1139 | ||
df58fc94 RS |
1140 | /* Is the given value a sign-extended 12-bit value? */ |
1141 | #define IS_SEXT_12BIT_NUM(x) \ | |
1142 | (((((x) & 0xfff) ^ 0x800LL) - 0x800LL) == (x)) | |
1143 | ||
7f3c4072 CM |
1144 | /* Is the given value a sign-extended 9-bit value? */ |
1145 | #define IS_SEXT_9BIT_NUM(x) \ | |
1146 | (((((x) & 0x1ff) ^ 0x100LL) - 0x100LL) == (x)) | |
1147 | ||
2051e8c4 MR |
1148 | /* Is the given value a zero-extended 32-bit value? Or a negated one? */ |
1149 | #define IS_ZEXT_32BIT_NUM(x) \ | |
1150 | (((x) &~ (offsetT) 0xffffffff) == 0 \ | |
1151 | || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff)) | |
1152 | ||
bf12938e RS |
1153 | /* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in |
1154 | VALUE << SHIFT. VALUE is evaluated exactly once. */ | |
1155 | #define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \ | |
1156 | (STRUCT) = (((STRUCT) & ~((MASK) << (SHIFT))) \ | |
1157 | | (((VALUE) & (MASK)) << (SHIFT))) | |
1158 | ||
1159 | /* Extract bits MASK << SHIFT from STRUCT and shift them right | |
1160 | SHIFT places. */ | |
1161 | #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \ | |
1162 | (((STRUCT) >> (SHIFT)) & (MASK)) | |
1163 | ||
1164 | /* Change INSN's opcode so that the operand given by FIELD has value VALUE. | |
1165 | INSN is a mips_cl_insn structure and VALUE is evaluated exactly once. | |
1166 | ||
1167 | include/opcode/mips.h specifies operand fields using the macros | |
1168 | OP_MASK_<FIELD> and OP_SH_<FIELD>. The MIPS16 equivalents start | |
1169 | with "MIPS16OP" instead of "OP". */ | |
df58fc94 RS |
1170 | #define INSERT_OPERAND(MICROMIPS, FIELD, INSN, VALUE) \ |
1171 | do \ | |
1172 | if (!(MICROMIPS)) \ | |
1173 | INSERT_BITS ((INSN).insn_opcode, VALUE, \ | |
1174 | OP_MASK_##FIELD, OP_SH_##FIELD); \ | |
1175 | else \ | |
1176 | INSERT_BITS ((INSN).insn_opcode, VALUE, \ | |
1177 | MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD); \ | |
1178 | while (0) | |
bf12938e RS |
1179 | #define MIPS16_INSERT_OPERAND(FIELD, INSN, VALUE) \ |
1180 | INSERT_BITS ((INSN).insn_opcode, VALUE, \ | |
1181 | MIPS16OP_MASK_##FIELD, MIPS16OP_SH_##FIELD) | |
1182 | ||
1183 | /* Extract the operand given by FIELD from mips_cl_insn INSN. */ | |
df58fc94 RS |
1184 | #define EXTRACT_OPERAND(MICROMIPS, FIELD, INSN) \ |
1185 | (!(MICROMIPS) \ | |
1186 | ? EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) \ | |
1187 | : EXTRACT_BITS ((INSN).insn_opcode, \ | |
1188 | MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD)) | |
bf12938e RS |
1189 | #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \ |
1190 | EXTRACT_BITS ((INSN).insn_opcode, \ | |
1191 | MIPS16OP_MASK_##FIELD, \ | |
1192 | MIPS16OP_SH_##FIELD) | |
5c04167a RS |
1193 | |
1194 | /* The MIPS16 EXTEND opcode, shifted left 16 places. */ | |
1195 | #define MIPS16_EXTEND (0xf000U << 16) | |
4d7206a2 | 1196 | \f |
df58fc94 RS |
1197 | /* Whether or not we are emitting a branch-likely macro. */ |
1198 | static bfd_boolean emit_branch_likely_macro = FALSE; | |
1199 | ||
4d7206a2 RS |
1200 | /* Global variables used when generating relaxable macros. See the |
1201 | comment above RELAX_ENCODE for more details about how relaxation | |
1202 | is used. */ | |
1203 | static struct { | |
1204 | /* 0 if we're not emitting a relaxable macro. | |
1205 | 1 if we're emitting the first of the two relaxation alternatives. | |
1206 | 2 if we're emitting the second alternative. */ | |
1207 | int sequence; | |
1208 | ||
1209 | /* The first relaxable fixup in the current frag. (In other words, | |
1210 | the first fixup that refers to relaxable code.) */ | |
1211 | fixS *first_fixup; | |
1212 | ||
1213 | /* sizes[0] says how many bytes of the first alternative are stored in | |
1214 | the current frag. Likewise sizes[1] for the second alternative. */ | |
1215 | unsigned int sizes[2]; | |
1216 | ||
1217 | /* The symbol on which the choice of sequence depends. */ | |
1218 | symbolS *symbol; | |
1219 | } mips_relax; | |
252b5132 | 1220 | \f |
584892a6 RS |
1221 | /* Global variables used to decide whether a macro needs a warning. */ |
1222 | static struct { | |
1223 | /* True if the macro is in a branch delay slot. */ | |
1224 | bfd_boolean delay_slot_p; | |
1225 | ||
df58fc94 RS |
1226 | /* Set to the length in bytes required if the macro is in a delay slot |
1227 | that requires a specific length of instruction, otherwise zero. */ | |
1228 | unsigned int delay_slot_length; | |
1229 | ||
584892a6 RS |
1230 | /* For relaxable macros, sizes[0] is the length of the first alternative |
1231 | in bytes and sizes[1] is the length of the second alternative. | |
1232 | For non-relaxable macros, both elements give the length of the | |
1233 | macro in bytes. */ | |
1234 | unsigned int sizes[2]; | |
1235 | ||
df58fc94 RS |
1236 | /* For relaxable macros, first_insn_sizes[0] is the length of the first |
1237 | instruction of the first alternative in bytes and first_insn_sizes[1] | |
1238 | is the length of the first instruction of the second alternative. | |
1239 | For non-relaxable macros, both elements give the length of the first | |
1240 | instruction in bytes. | |
1241 | ||
1242 | Set to zero if we haven't yet seen the first instruction. */ | |
1243 | unsigned int first_insn_sizes[2]; | |
1244 | ||
1245 | /* For relaxable macros, insns[0] is the number of instructions for the | |
1246 | first alternative and insns[1] is the number of instructions for the | |
1247 | second alternative. | |
1248 | ||
1249 | For non-relaxable macros, both elements give the number of | |
1250 | instructions for the macro. */ | |
1251 | unsigned int insns[2]; | |
1252 | ||
584892a6 RS |
1253 | /* The first variant frag for this macro. */ |
1254 | fragS *first_frag; | |
1255 | } mips_macro_warning; | |
1256 | \f | |
252b5132 RH |
1257 | /* Prototypes for static functions. */ |
1258 | ||
252b5132 RH |
1259 | enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG }; |
1260 | ||
b34976b6 | 1261 | static void append_insn |
df58fc94 RS |
1262 | (struct mips_cl_insn *, expressionS *, bfd_reloc_code_real_type *, |
1263 | bfd_boolean expansionp); | |
7d10b47d | 1264 | static void mips_no_prev_insn (void); |
c67a084a | 1265 | static void macro_build (expressionS *, const char *, const char *, ...); |
b34976b6 | 1266 | static void mips16_macro_build |
03ea81db | 1267 | (expressionS *, const char *, const char *, va_list *); |
67c0d1eb | 1268 | static void load_register (int, expressionS *, int); |
584892a6 RS |
1269 | static void macro_start (void); |
1270 | static void macro_end (void); | |
17a2f251 TS |
1271 | static void macro (struct mips_cl_insn * ip); |
1272 | static void mips16_macro (struct mips_cl_insn * ip); | |
17a2f251 TS |
1273 | static void mips_ip (char *str, struct mips_cl_insn * ip); |
1274 | static void mips16_ip (char *str, struct mips_cl_insn * ip); | |
b34976b6 | 1275 | static void mips16_immed |
43c0598f RS |
1276 | (char *, unsigned int, int, bfd_reloc_code_real_type, offsetT, |
1277 | unsigned int, unsigned long *); | |
5e0116d5 | 1278 | static size_t my_getSmallExpression |
17a2f251 TS |
1279 | (expressionS *, bfd_reloc_code_real_type *, char *); |
1280 | static void my_getExpression (expressionS *, char *); | |
1281 | static void s_align (int); | |
1282 | static void s_change_sec (int); | |
1283 | static void s_change_section (int); | |
1284 | static void s_cons (int); | |
1285 | static void s_float_cons (int); | |
1286 | static void s_mips_globl (int); | |
1287 | static void s_option (int); | |
1288 | static void s_mipsset (int); | |
1289 | static void s_abicalls (int); | |
1290 | static void s_cpload (int); | |
1291 | static void s_cpsetup (int); | |
1292 | static void s_cplocal (int); | |
1293 | static void s_cprestore (int); | |
1294 | static void s_cpreturn (int); | |
741d6ea8 JM |
1295 | static void s_dtprelword (int); |
1296 | static void s_dtpreldword (int); | |
d0f13682 CLT |
1297 | static void s_tprelword (int); |
1298 | static void s_tpreldword (int); | |
17a2f251 TS |
1299 | static void s_gpvalue (int); |
1300 | static void s_gpword (int); | |
1301 | static void s_gpdword (int); | |
a3f278e2 | 1302 | static void s_ehword (int); |
17a2f251 TS |
1303 | static void s_cpadd (int); |
1304 | static void s_insn (int); | |
1305 | static void md_obj_begin (void); | |
1306 | static void md_obj_end (void); | |
1307 | static void s_mips_ent (int); | |
1308 | static void s_mips_end (int); | |
1309 | static void s_mips_frame (int); | |
1310 | static void s_mips_mask (int reg_type); | |
1311 | static void s_mips_stab (int); | |
1312 | static void s_mips_weakext (int); | |
1313 | static void s_mips_file (int); | |
1314 | static void s_mips_loc (int); | |
1315 | static bfd_boolean pic_need_relax (symbolS *, asection *); | |
4a6a3df4 | 1316 | static int relaxed_branch_length (fragS *, asection *, int); |
17a2f251 | 1317 | static int validate_mips_insn (const struct mips_opcode *); |
df58fc94 RS |
1318 | static int validate_micromips_insn (const struct mips_opcode *); |
1319 | static int relaxed_micromips_16bit_branch_length (fragS *, asection *, int); | |
1320 | static int relaxed_micromips_32bit_branch_length (fragS *, asection *, int); | |
e7af610e NC |
1321 | |
1322 | /* Table and functions used to map between CPU/ISA names, and | |
1323 | ISA levels, and CPU numbers. */ | |
1324 | ||
e972090a NC |
1325 | struct mips_cpu_info |
1326 | { | |
e7af610e | 1327 | const char *name; /* CPU or ISA name. */ |
d16afab6 RS |
1328 | int flags; /* MIPS_CPU_* flags. */ |
1329 | int ase; /* Set of ASEs implemented by the CPU. */ | |
e7af610e NC |
1330 | int isa; /* ISA level. */ |
1331 | int cpu; /* CPU number (default CPU if ISA). */ | |
1332 | }; | |
1333 | ||
ad3fea08 | 1334 | #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */ |
ad3fea08 | 1335 | |
17a2f251 TS |
1336 | static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *); |
1337 | static const struct mips_cpu_info *mips_cpu_info_from_isa (int); | |
1338 | static const struct mips_cpu_info *mips_cpu_info_from_arch (int); | |
252b5132 | 1339 | \f |
c31f3936 RS |
1340 | /* Command-line options. */ |
1341 | const char *md_shortopts = "O::g::G:"; | |
1342 | ||
1343 | enum options | |
1344 | { | |
1345 | OPTION_MARCH = OPTION_MD_BASE, | |
1346 | OPTION_MTUNE, | |
1347 | OPTION_MIPS1, | |
1348 | OPTION_MIPS2, | |
1349 | OPTION_MIPS3, | |
1350 | OPTION_MIPS4, | |
1351 | OPTION_MIPS5, | |
1352 | OPTION_MIPS32, | |
1353 | OPTION_MIPS64, | |
1354 | OPTION_MIPS32R2, | |
1355 | OPTION_MIPS64R2, | |
1356 | OPTION_MIPS16, | |
1357 | OPTION_NO_MIPS16, | |
1358 | OPTION_MIPS3D, | |
1359 | OPTION_NO_MIPS3D, | |
1360 | OPTION_MDMX, | |
1361 | OPTION_NO_MDMX, | |
1362 | OPTION_DSP, | |
1363 | OPTION_NO_DSP, | |
1364 | OPTION_MT, | |
1365 | OPTION_NO_MT, | |
1366 | OPTION_VIRT, | |
1367 | OPTION_NO_VIRT, | |
1368 | OPTION_SMARTMIPS, | |
1369 | OPTION_NO_SMARTMIPS, | |
1370 | OPTION_DSPR2, | |
1371 | OPTION_NO_DSPR2, | |
1372 | OPTION_EVA, | |
1373 | OPTION_NO_EVA, | |
1374 | OPTION_MICROMIPS, | |
1375 | OPTION_NO_MICROMIPS, | |
1376 | OPTION_MCU, | |
1377 | OPTION_NO_MCU, | |
1378 | OPTION_COMPAT_ARCH_BASE, | |
1379 | OPTION_M4650, | |
1380 | OPTION_NO_M4650, | |
1381 | OPTION_M4010, | |
1382 | OPTION_NO_M4010, | |
1383 | OPTION_M4100, | |
1384 | OPTION_NO_M4100, | |
1385 | OPTION_M3900, | |
1386 | OPTION_NO_M3900, | |
1387 | OPTION_M7000_HILO_FIX, | |
1388 | OPTION_MNO_7000_HILO_FIX, | |
1389 | OPTION_FIX_24K, | |
1390 | OPTION_NO_FIX_24K, | |
1391 | OPTION_FIX_LOONGSON2F_JUMP, | |
1392 | OPTION_NO_FIX_LOONGSON2F_JUMP, | |
1393 | OPTION_FIX_LOONGSON2F_NOP, | |
1394 | OPTION_NO_FIX_LOONGSON2F_NOP, | |
1395 | OPTION_FIX_VR4120, | |
1396 | OPTION_NO_FIX_VR4120, | |
1397 | OPTION_FIX_VR4130, | |
1398 | OPTION_NO_FIX_VR4130, | |
1399 | OPTION_FIX_CN63XXP1, | |
1400 | OPTION_NO_FIX_CN63XXP1, | |
1401 | OPTION_TRAP, | |
1402 | OPTION_BREAK, | |
1403 | OPTION_EB, | |
1404 | OPTION_EL, | |
1405 | OPTION_FP32, | |
1406 | OPTION_GP32, | |
1407 | OPTION_CONSTRUCT_FLOATS, | |
1408 | OPTION_NO_CONSTRUCT_FLOATS, | |
1409 | OPTION_FP64, | |
1410 | OPTION_GP64, | |
1411 | OPTION_RELAX_BRANCH, | |
1412 | OPTION_NO_RELAX_BRANCH, | |
1413 | OPTION_MSHARED, | |
1414 | OPTION_MNO_SHARED, | |
1415 | OPTION_MSYM32, | |
1416 | OPTION_MNO_SYM32, | |
1417 | OPTION_SOFT_FLOAT, | |
1418 | OPTION_HARD_FLOAT, | |
1419 | OPTION_SINGLE_FLOAT, | |
1420 | OPTION_DOUBLE_FLOAT, | |
1421 | OPTION_32, | |
c31f3936 RS |
1422 | OPTION_CALL_SHARED, |
1423 | OPTION_CALL_NONPIC, | |
1424 | OPTION_NON_SHARED, | |
1425 | OPTION_XGOT, | |
1426 | OPTION_MABI, | |
1427 | OPTION_N32, | |
1428 | OPTION_64, | |
1429 | OPTION_MDEBUG, | |
1430 | OPTION_NO_MDEBUG, | |
1431 | OPTION_PDR, | |
1432 | OPTION_NO_PDR, | |
1433 | OPTION_MVXWORKS_PIC, | |
c31f3936 RS |
1434 | OPTION_END_OF_ENUM |
1435 | }; | |
1436 | ||
1437 | struct option md_longopts[] = | |
1438 | { | |
1439 | /* Options which specify architecture. */ | |
1440 | {"march", required_argument, NULL, OPTION_MARCH}, | |
1441 | {"mtune", required_argument, NULL, OPTION_MTUNE}, | |
1442 | {"mips0", no_argument, NULL, OPTION_MIPS1}, | |
1443 | {"mips1", no_argument, NULL, OPTION_MIPS1}, | |
1444 | {"mips2", no_argument, NULL, OPTION_MIPS2}, | |
1445 | {"mips3", no_argument, NULL, OPTION_MIPS3}, | |
1446 | {"mips4", no_argument, NULL, OPTION_MIPS4}, | |
1447 | {"mips5", no_argument, NULL, OPTION_MIPS5}, | |
1448 | {"mips32", no_argument, NULL, OPTION_MIPS32}, | |
1449 | {"mips64", no_argument, NULL, OPTION_MIPS64}, | |
1450 | {"mips32r2", no_argument, NULL, OPTION_MIPS32R2}, | |
1451 | {"mips64r2", no_argument, NULL, OPTION_MIPS64R2}, | |
1452 | ||
1453 | /* Options which specify Application Specific Extensions (ASEs). */ | |
1454 | {"mips16", no_argument, NULL, OPTION_MIPS16}, | |
1455 | {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16}, | |
1456 | {"mips3d", no_argument, NULL, OPTION_MIPS3D}, | |
1457 | {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D}, | |
1458 | {"mdmx", no_argument, NULL, OPTION_MDMX}, | |
1459 | {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX}, | |
1460 | {"mdsp", no_argument, NULL, OPTION_DSP}, | |
1461 | {"mno-dsp", no_argument, NULL, OPTION_NO_DSP}, | |
1462 | {"mmt", no_argument, NULL, OPTION_MT}, | |
1463 | {"mno-mt", no_argument, NULL, OPTION_NO_MT}, | |
1464 | {"msmartmips", no_argument, NULL, OPTION_SMARTMIPS}, | |
1465 | {"mno-smartmips", no_argument, NULL, OPTION_NO_SMARTMIPS}, | |
1466 | {"mdspr2", no_argument, NULL, OPTION_DSPR2}, | |
1467 | {"mno-dspr2", no_argument, NULL, OPTION_NO_DSPR2}, | |
1468 | {"meva", no_argument, NULL, OPTION_EVA}, | |
1469 | {"mno-eva", no_argument, NULL, OPTION_NO_EVA}, | |
1470 | {"mmicromips", no_argument, NULL, OPTION_MICROMIPS}, | |
1471 | {"mno-micromips", no_argument, NULL, OPTION_NO_MICROMIPS}, | |
1472 | {"mmcu", no_argument, NULL, OPTION_MCU}, | |
1473 | {"mno-mcu", no_argument, NULL, OPTION_NO_MCU}, | |
1474 | {"mvirt", no_argument, NULL, OPTION_VIRT}, | |
1475 | {"mno-virt", no_argument, NULL, OPTION_NO_VIRT}, | |
1476 | ||
1477 | /* Old-style architecture options. Don't add more of these. */ | |
1478 | {"m4650", no_argument, NULL, OPTION_M4650}, | |
1479 | {"no-m4650", no_argument, NULL, OPTION_NO_M4650}, | |
1480 | {"m4010", no_argument, NULL, OPTION_M4010}, | |
1481 | {"no-m4010", no_argument, NULL, OPTION_NO_M4010}, | |
1482 | {"m4100", no_argument, NULL, OPTION_M4100}, | |
1483 | {"no-m4100", no_argument, NULL, OPTION_NO_M4100}, | |
1484 | {"m3900", no_argument, NULL, OPTION_M3900}, | |
1485 | {"no-m3900", no_argument, NULL, OPTION_NO_M3900}, | |
1486 | ||
1487 | /* Options which enable bug fixes. */ | |
1488 | {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX}, | |
1489 | {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, | |
1490 | {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, | |
1491 | {"mfix-loongson2f-jump", no_argument, NULL, OPTION_FIX_LOONGSON2F_JUMP}, | |
1492 | {"mno-fix-loongson2f-jump", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_JUMP}, | |
1493 | {"mfix-loongson2f-nop", no_argument, NULL, OPTION_FIX_LOONGSON2F_NOP}, | |
1494 | {"mno-fix-loongson2f-nop", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_NOP}, | |
1495 | {"mfix-vr4120", no_argument, NULL, OPTION_FIX_VR4120}, | |
1496 | {"mno-fix-vr4120", no_argument, NULL, OPTION_NO_FIX_VR4120}, | |
1497 | {"mfix-vr4130", no_argument, NULL, OPTION_FIX_VR4130}, | |
1498 | {"mno-fix-vr4130", no_argument, NULL, OPTION_NO_FIX_VR4130}, | |
1499 | {"mfix-24k", no_argument, NULL, OPTION_FIX_24K}, | |
1500 | {"mno-fix-24k", no_argument, NULL, OPTION_NO_FIX_24K}, | |
1501 | {"mfix-cn63xxp1", no_argument, NULL, OPTION_FIX_CN63XXP1}, | |
1502 | {"mno-fix-cn63xxp1", no_argument, NULL, OPTION_NO_FIX_CN63XXP1}, | |
1503 | ||
1504 | /* Miscellaneous options. */ | |
1505 | {"trap", no_argument, NULL, OPTION_TRAP}, | |
1506 | {"no-break", no_argument, NULL, OPTION_TRAP}, | |
1507 | {"break", no_argument, NULL, OPTION_BREAK}, | |
1508 | {"no-trap", no_argument, NULL, OPTION_BREAK}, | |
1509 | {"EB", no_argument, NULL, OPTION_EB}, | |
1510 | {"EL", no_argument, NULL, OPTION_EL}, | |
1511 | {"mfp32", no_argument, NULL, OPTION_FP32}, | |
1512 | {"mgp32", no_argument, NULL, OPTION_GP32}, | |
1513 | {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS}, | |
1514 | {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS}, | |
1515 | {"mfp64", no_argument, NULL, OPTION_FP64}, | |
1516 | {"mgp64", no_argument, NULL, OPTION_GP64}, | |
1517 | {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH}, | |
1518 | {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH}, | |
1519 | {"mshared", no_argument, NULL, OPTION_MSHARED}, | |
1520 | {"mno-shared", no_argument, NULL, OPTION_MNO_SHARED}, | |
1521 | {"msym32", no_argument, NULL, OPTION_MSYM32}, | |
1522 | {"mno-sym32", no_argument, NULL, OPTION_MNO_SYM32}, | |
1523 | {"msoft-float", no_argument, NULL, OPTION_SOFT_FLOAT}, | |
1524 | {"mhard-float", no_argument, NULL, OPTION_HARD_FLOAT}, | |
1525 | {"msingle-float", no_argument, NULL, OPTION_SINGLE_FLOAT}, | |
1526 | {"mdouble-float", no_argument, NULL, OPTION_DOUBLE_FLOAT}, | |
1527 | ||
1528 | /* Strictly speaking this next option is ELF specific, | |
1529 | but we allow it for other ports as well in order to | |
1530 | make testing easier. */ | |
1531 | {"32", no_argument, NULL, OPTION_32}, | |
1532 | ||
1533 | /* ELF-specific options. */ | |
c31f3936 RS |
1534 | {"KPIC", no_argument, NULL, OPTION_CALL_SHARED}, |
1535 | {"call_shared", no_argument, NULL, OPTION_CALL_SHARED}, | |
1536 | {"call_nonpic", no_argument, NULL, OPTION_CALL_NONPIC}, | |
1537 | {"non_shared", no_argument, NULL, OPTION_NON_SHARED}, | |
1538 | {"xgot", no_argument, NULL, OPTION_XGOT}, | |
1539 | {"mabi", required_argument, NULL, OPTION_MABI}, | |
1540 | {"n32", no_argument, NULL, OPTION_N32}, | |
1541 | {"64", no_argument, NULL, OPTION_64}, | |
1542 | {"mdebug", no_argument, NULL, OPTION_MDEBUG}, | |
1543 | {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG}, | |
1544 | {"mpdr", no_argument, NULL, OPTION_PDR}, | |
1545 | {"mno-pdr", no_argument, NULL, OPTION_NO_PDR}, | |
1546 | {"mvxworks-pic", no_argument, NULL, OPTION_MVXWORKS_PIC}, | |
c31f3936 RS |
1547 | |
1548 | {NULL, no_argument, NULL, 0} | |
1549 | }; | |
1550 | size_t md_longopts_size = sizeof (md_longopts); | |
1551 | \f | |
c6278170 RS |
1552 | /* Information about either an Application Specific Extension or an |
1553 | optional architecture feature that, for simplicity, we treat in the | |
1554 | same way as an ASE. */ | |
1555 | struct mips_ase | |
1556 | { | |
1557 | /* The name of the ASE, used in both the command-line and .set options. */ | |
1558 | const char *name; | |
1559 | ||
1560 | /* The associated ASE_* flags. If the ASE is available on both 32-bit | |
1561 | and 64-bit architectures, the flags here refer to the subset that | |
1562 | is available on both. */ | |
1563 | unsigned int flags; | |
1564 | ||
1565 | /* The ASE_* flag used for instructions that are available on 64-bit | |
1566 | architectures but that are not included in FLAGS. */ | |
1567 | unsigned int flags64; | |
1568 | ||
1569 | /* The command-line options that turn the ASE on and off. */ | |
1570 | int option_on; | |
1571 | int option_off; | |
1572 | ||
1573 | /* The minimum required architecture revisions for MIPS32, MIPS64, | |
1574 | microMIPS32 and microMIPS64, or -1 if the extension isn't supported. */ | |
1575 | int mips32_rev; | |
1576 | int mips64_rev; | |
1577 | int micromips32_rev; | |
1578 | int micromips64_rev; | |
1579 | }; | |
1580 | ||
1581 | /* A table of all supported ASEs. */ | |
1582 | static const struct mips_ase mips_ases[] = { | |
1583 | { "dsp", ASE_DSP, ASE_DSP64, | |
1584 | OPTION_DSP, OPTION_NO_DSP, | |
1585 | 2, 2, 2, 2 }, | |
1586 | ||
1587 | { "dspr2", ASE_DSP | ASE_DSPR2, 0, | |
1588 | OPTION_DSPR2, OPTION_NO_DSPR2, | |
1589 | 2, 2, 2, 2 }, | |
1590 | ||
1591 | { "eva", ASE_EVA, 0, | |
1592 | OPTION_EVA, OPTION_NO_EVA, | |
1593 | 2, 2, 2, 2 }, | |
1594 | ||
1595 | { "mcu", ASE_MCU, 0, | |
1596 | OPTION_MCU, OPTION_NO_MCU, | |
1597 | 2, 2, 2, 2 }, | |
1598 | ||
1599 | /* Deprecated in MIPS64r5, but we don't implement that yet. */ | |
1600 | { "mdmx", ASE_MDMX, 0, | |
1601 | OPTION_MDMX, OPTION_NO_MDMX, | |
1602 | -1, 1, -1, -1 }, | |
1603 | ||
1604 | /* Requires 64-bit FPRs, so the minimum MIPS32 revision is 2. */ | |
1605 | { "mips3d", ASE_MIPS3D, 0, | |
1606 | OPTION_MIPS3D, OPTION_NO_MIPS3D, | |
1607 | 2, 1, -1, -1 }, | |
1608 | ||
1609 | { "mt", ASE_MT, 0, | |
1610 | OPTION_MT, OPTION_NO_MT, | |
1611 | 2, 2, -1, -1 }, | |
1612 | ||
1613 | { "smartmips", ASE_SMARTMIPS, 0, | |
1614 | OPTION_SMARTMIPS, OPTION_NO_SMARTMIPS, | |
1615 | 1, -1, -1, -1 }, | |
1616 | ||
1617 | { "virt", ASE_VIRT, ASE_VIRT64, | |
1618 | OPTION_VIRT, OPTION_NO_VIRT, | |
1619 | 2, 2, 2, 2 } | |
1620 | }; | |
1621 | ||
1622 | /* The set of ASEs that require -mfp64. */ | |
1623 | #define FP64_ASES (ASE_MIPS3D | ASE_MDMX) | |
1624 | ||
1625 | /* Groups of ASE_* flags that represent different revisions of an ASE. */ | |
1626 | static const unsigned int mips_ase_groups[] = { | |
1627 | ASE_DSP | ASE_DSPR2 | |
1628 | }; | |
1629 | \f | |
252b5132 RH |
1630 | /* Pseudo-op table. |
1631 | ||
1632 | The following pseudo-ops from the Kane and Heinrich MIPS book | |
1633 | should be defined here, but are currently unsupported: .alias, | |
1634 | .galive, .gjaldef, .gjrlive, .livereg, .noalias. | |
1635 | ||
1636 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
1637 | specific to the type of debugging information being generated, and | |
1638 | should be defined by the object format: .aent, .begin, .bend, | |
1639 | .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp, | |
1640 | .vreg. | |
1641 | ||
1642 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
1643 | not MIPS CPU specific, but are also not specific to the object file | |
1644 | format. This file is probably the best place to define them, but | |
d84bcf09 | 1645 | they are not currently supported: .asm0, .endr, .lab, .struct. */ |
252b5132 | 1646 | |
e972090a NC |
1647 | static const pseudo_typeS mips_pseudo_table[] = |
1648 | { | |
beae10d5 | 1649 | /* MIPS specific pseudo-ops. */ |
252b5132 RH |
1650 | {"option", s_option, 0}, |
1651 | {"set", s_mipsset, 0}, | |
1652 | {"rdata", s_change_sec, 'r'}, | |
1653 | {"sdata", s_change_sec, 's'}, | |
1654 | {"livereg", s_ignore, 0}, | |
1655 | {"abicalls", s_abicalls, 0}, | |
1656 | {"cpload", s_cpload, 0}, | |
6478892d TS |
1657 | {"cpsetup", s_cpsetup, 0}, |
1658 | {"cplocal", s_cplocal, 0}, | |
252b5132 | 1659 | {"cprestore", s_cprestore, 0}, |
6478892d | 1660 | {"cpreturn", s_cpreturn, 0}, |
741d6ea8 JM |
1661 | {"dtprelword", s_dtprelword, 0}, |
1662 | {"dtpreldword", s_dtpreldword, 0}, | |
d0f13682 CLT |
1663 | {"tprelword", s_tprelword, 0}, |
1664 | {"tpreldword", s_tpreldword, 0}, | |
6478892d | 1665 | {"gpvalue", s_gpvalue, 0}, |
252b5132 | 1666 | {"gpword", s_gpword, 0}, |
10181a0d | 1667 | {"gpdword", s_gpdword, 0}, |
a3f278e2 | 1668 | {"ehword", s_ehword, 0}, |
252b5132 RH |
1669 | {"cpadd", s_cpadd, 0}, |
1670 | {"insn", s_insn, 0}, | |
1671 | ||
beae10d5 | 1672 | /* Relatively generic pseudo-ops that happen to be used on MIPS |
252b5132 | 1673 | chips. */ |
38a57ae7 | 1674 | {"asciiz", stringer, 8 + 1}, |
252b5132 RH |
1675 | {"bss", s_change_sec, 'b'}, |
1676 | {"err", s_err, 0}, | |
1677 | {"half", s_cons, 1}, | |
1678 | {"dword", s_cons, 3}, | |
1679 | {"weakext", s_mips_weakext, 0}, | |
7c752c2a TS |
1680 | {"origin", s_org, 0}, |
1681 | {"repeat", s_rept, 0}, | |
252b5132 | 1682 | |
998b3c36 MR |
1683 | /* For MIPS this is non-standard, but we define it for consistency. */ |
1684 | {"sbss", s_change_sec, 'B'}, | |
1685 | ||
beae10d5 | 1686 | /* These pseudo-ops are defined in read.c, but must be overridden |
252b5132 RH |
1687 | here for one reason or another. */ |
1688 | {"align", s_align, 0}, | |
1689 | {"byte", s_cons, 0}, | |
1690 | {"data", s_change_sec, 'd'}, | |
1691 | {"double", s_float_cons, 'd'}, | |
1692 | {"float", s_float_cons, 'f'}, | |
1693 | {"globl", s_mips_globl, 0}, | |
1694 | {"global", s_mips_globl, 0}, | |
1695 | {"hword", s_cons, 1}, | |
1696 | {"int", s_cons, 2}, | |
1697 | {"long", s_cons, 2}, | |
1698 | {"octa", s_cons, 4}, | |
1699 | {"quad", s_cons, 3}, | |
cca86cc8 | 1700 | {"section", s_change_section, 0}, |
252b5132 RH |
1701 | {"short", s_cons, 1}, |
1702 | {"single", s_float_cons, 'f'}, | |
754e2bb9 | 1703 | {"stabd", s_mips_stab, 'd'}, |
252b5132 | 1704 | {"stabn", s_mips_stab, 'n'}, |
754e2bb9 | 1705 | {"stabs", s_mips_stab, 's'}, |
252b5132 RH |
1706 | {"text", s_change_sec, 't'}, |
1707 | {"word", s_cons, 2}, | |
add56521 | 1708 | |
add56521 | 1709 | { "extern", ecoff_directive_extern, 0}, |
add56521 | 1710 | |
43841e91 | 1711 | { NULL, NULL, 0 }, |
252b5132 RH |
1712 | }; |
1713 | ||
e972090a NC |
1714 | static const pseudo_typeS mips_nonecoff_pseudo_table[] = |
1715 | { | |
beae10d5 KH |
1716 | /* These pseudo-ops should be defined by the object file format. |
1717 | However, a.out doesn't support them, so we have versions here. */ | |
252b5132 RH |
1718 | {"aent", s_mips_ent, 1}, |
1719 | {"bgnb", s_ignore, 0}, | |
1720 | {"end", s_mips_end, 0}, | |
1721 | {"endb", s_ignore, 0}, | |
1722 | {"ent", s_mips_ent, 0}, | |
c5dd6aab | 1723 | {"file", s_mips_file, 0}, |
252b5132 RH |
1724 | {"fmask", s_mips_mask, 'F'}, |
1725 | {"frame", s_mips_frame, 0}, | |
c5dd6aab | 1726 | {"loc", s_mips_loc, 0}, |
252b5132 RH |
1727 | {"mask", s_mips_mask, 'R'}, |
1728 | {"verstamp", s_ignore, 0}, | |
43841e91 | 1729 | { NULL, NULL, 0 }, |
252b5132 RH |
1730 | }; |
1731 | ||
3ae8dd8d MR |
1732 | /* Export the ABI address size for use by TC_ADDRESS_BYTES for the |
1733 | purpose of the `.dc.a' internal pseudo-op. */ | |
1734 | ||
1735 | int | |
1736 | mips_address_bytes (void) | |
1737 | { | |
1738 | return HAVE_64BIT_ADDRESSES ? 8 : 4; | |
1739 | } | |
1740 | ||
17a2f251 | 1741 | extern void pop_insert (const pseudo_typeS *); |
252b5132 RH |
1742 | |
1743 | void | |
17a2f251 | 1744 | mips_pop_insert (void) |
252b5132 RH |
1745 | { |
1746 | pop_insert (mips_pseudo_table); | |
1747 | if (! ECOFF_DEBUGGING) | |
1748 | pop_insert (mips_nonecoff_pseudo_table); | |
1749 | } | |
1750 | \f | |
1751 | /* Symbols labelling the current insn. */ | |
1752 | ||
e972090a NC |
1753 | struct insn_label_list |
1754 | { | |
252b5132 RH |
1755 | struct insn_label_list *next; |
1756 | symbolS *label; | |
1757 | }; | |
1758 | ||
252b5132 | 1759 | static struct insn_label_list *free_insn_labels; |
742a56fe | 1760 | #define label_list tc_segment_info_data.labels |
252b5132 | 1761 | |
17a2f251 | 1762 | static void mips_clear_insn_labels (void); |
df58fc94 RS |
1763 | static void mips_mark_labels (void); |
1764 | static void mips_compressed_mark_labels (void); | |
252b5132 RH |
1765 | |
1766 | static inline void | |
17a2f251 | 1767 | mips_clear_insn_labels (void) |
252b5132 RH |
1768 | { |
1769 | register struct insn_label_list **pl; | |
a8dbcb85 | 1770 | segment_info_type *si; |
252b5132 | 1771 | |
a8dbcb85 TS |
1772 | if (now_seg) |
1773 | { | |
1774 | for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next) | |
1775 | ; | |
1776 | ||
1777 | si = seg_info (now_seg); | |
1778 | *pl = si->label_list; | |
1779 | si->label_list = NULL; | |
1780 | } | |
252b5132 | 1781 | } |
a8dbcb85 | 1782 | |
df58fc94 RS |
1783 | /* Mark instruction labels in MIPS16/microMIPS mode. */ |
1784 | ||
1785 | static inline void | |
1786 | mips_mark_labels (void) | |
1787 | { | |
1788 | if (HAVE_CODE_COMPRESSION) | |
1789 | mips_compressed_mark_labels (); | |
1790 | } | |
252b5132 RH |
1791 | \f |
1792 | static char *expr_end; | |
1793 | ||
1794 | /* Expressions which appear in instructions. These are set by | |
1795 | mips_ip. */ | |
1796 | ||
1797 | static expressionS imm_expr; | |
5f74bc13 | 1798 | static expressionS imm2_expr; |
252b5132 RH |
1799 | static expressionS offset_expr; |
1800 | ||
1801 | /* Relocs associated with imm_expr and offset_expr. */ | |
1802 | ||
f6688943 TS |
1803 | static bfd_reloc_code_real_type imm_reloc[3] |
1804 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
1805 | static bfd_reloc_code_real_type offset_reloc[3] | |
1806 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 1807 | |
df58fc94 RS |
1808 | /* This is set to the resulting size of the instruction to be produced |
1809 | by mips16_ip if an explicit extension is used or by mips_ip if an | |
1810 | explicit size is supplied. */ | |
252b5132 | 1811 | |
df58fc94 | 1812 | static unsigned int forced_insn_length; |
252b5132 | 1813 | |
e1b47bd5 RS |
1814 | /* True if we are assembling an instruction. All dot symbols defined during |
1815 | this time should be treated as code labels. */ | |
1816 | ||
1817 | static bfd_boolean mips_assembling_insn; | |
1818 | ||
ecb4347a DJ |
1819 | /* The pdr segment for per procedure frame/regmask info. Not used for |
1820 | ECOFF debugging. */ | |
252b5132 RH |
1821 | |
1822 | static segT pdr_seg; | |
252b5132 | 1823 | |
e013f690 TS |
1824 | /* The default target format to use. */ |
1825 | ||
aeffff67 RS |
1826 | #if defined (TE_FreeBSD) |
1827 | #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd" | |
1828 | #elif defined (TE_TMIPS) | |
1829 | #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips" | |
1830 | #else | |
1831 | #define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips" | |
1832 | #endif | |
1833 | ||
e013f690 | 1834 | const char * |
17a2f251 | 1835 | mips_target_format (void) |
e013f690 TS |
1836 | { |
1837 | switch (OUTPUT_FLAVOR) | |
1838 | { | |
e013f690 | 1839 | case bfd_target_elf_flavour: |
0a44bf69 RS |
1840 | #ifdef TE_VXWORKS |
1841 | if (!HAVE_64BIT_OBJECTS && !HAVE_NEWABI) | |
1842 | return (target_big_endian | |
1843 | ? "elf32-bigmips-vxworks" | |
1844 | : "elf32-littlemips-vxworks"); | |
1845 | #endif | |
e013f690 | 1846 | return (target_big_endian |
cfe86eaa | 1847 | ? (HAVE_64BIT_OBJECTS |
aeffff67 | 1848 | ? ELF_TARGET ("elf64-", "big") |
cfe86eaa | 1849 | : (HAVE_NEWABI |
aeffff67 RS |
1850 | ? ELF_TARGET ("elf32-n", "big") |
1851 | : ELF_TARGET ("elf32-", "big"))) | |
cfe86eaa | 1852 | : (HAVE_64BIT_OBJECTS |
aeffff67 | 1853 | ? ELF_TARGET ("elf64-", "little") |
cfe86eaa | 1854 | : (HAVE_NEWABI |
aeffff67 RS |
1855 | ? ELF_TARGET ("elf32-n", "little") |
1856 | : ELF_TARGET ("elf32-", "little")))); | |
e013f690 TS |
1857 | default: |
1858 | abort (); | |
1859 | return NULL; | |
1860 | } | |
1861 | } | |
1862 | ||
c6278170 RS |
1863 | /* Return the ISA revision that is currently in use, or 0 if we are |
1864 | generating code for MIPS V or below. */ | |
1865 | ||
1866 | static int | |
1867 | mips_isa_rev (void) | |
1868 | { | |
1869 | if (mips_opts.isa == ISA_MIPS32R2 || mips_opts.isa == ISA_MIPS64R2) | |
1870 | return 2; | |
1871 | ||
1872 | /* microMIPS implies revision 2 or above. */ | |
1873 | if (mips_opts.micromips) | |
1874 | return 2; | |
1875 | ||
1876 | if (mips_opts.isa == ISA_MIPS32 || mips_opts.isa == ISA_MIPS64) | |
1877 | return 1; | |
1878 | ||
1879 | return 0; | |
1880 | } | |
1881 | ||
1882 | /* Return the mask of all ASEs that are revisions of those in FLAGS. */ | |
1883 | ||
1884 | static unsigned int | |
1885 | mips_ase_mask (unsigned int flags) | |
1886 | { | |
1887 | unsigned int i; | |
1888 | ||
1889 | for (i = 0; i < ARRAY_SIZE (mips_ase_groups); i++) | |
1890 | if (flags & mips_ase_groups[i]) | |
1891 | flags |= mips_ase_groups[i]; | |
1892 | return flags; | |
1893 | } | |
1894 | ||
1895 | /* Check whether the current ISA supports ASE. Issue a warning if | |
1896 | appropriate. */ | |
1897 | ||
1898 | static void | |
1899 | mips_check_isa_supports_ase (const struct mips_ase *ase) | |
1900 | { | |
1901 | const char *base; | |
1902 | int min_rev, size; | |
1903 | static unsigned int warned_isa; | |
1904 | static unsigned int warned_fp32; | |
1905 | ||
1906 | if (ISA_HAS_64BIT_REGS (mips_opts.isa)) | |
1907 | min_rev = mips_opts.micromips ? ase->micromips64_rev : ase->mips64_rev; | |
1908 | else | |
1909 | min_rev = mips_opts.micromips ? ase->micromips32_rev : ase->mips32_rev; | |
1910 | if ((min_rev < 0 || mips_isa_rev () < min_rev) | |
1911 | && (warned_isa & ase->flags) != ase->flags) | |
1912 | { | |
1913 | warned_isa |= ase->flags; | |
1914 | base = mips_opts.micromips ? "microMIPS" : "MIPS"; | |
1915 | size = ISA_HAS_64BIT_REGS (mips_opts.isa) ? 64 : 32; | |
1916 | if (min_rev < 0) | |
1917 | as_warn (_("The %d-bit %s architecture does not support the" | |
1918 | " `%s' extension"), size, base, ase->name); | |
1919 | else | |
1920 | as_warn (_("The `%s' extension requires %s%d revision %d or greater"), | |
1921 | ase->name, base, size, min_rev); | |
1922 | } | |
1923 | if ((ase->flags & FP64_ASES) | |
1924 | && mips_opts.fp32 | |
1925 | && (warned_fp32 & ase->flags) != ase->flags) | |
1926 | { | |
1927 | warned_fp32 |= ase->flags; | |
1928 | as_warn (_("The `%s' extension requires 64-bit FPRs"), ase->name); | |
1929 | } | |
1930 | } | |
1931 | ||
1932 | /* Check all enabled ASEs to see whether they are supported by the | |
1933 | chosen architecture. */ | |
1934 | ||
1935 | static void | |
1936 | mips_check_isa_supports_ases (void) | |
1937 | { | |
1938 | unsigned int i, mask; | |
1939 | ||
1940 | for (i = 0; i < ARRAY_SIZE (mips_ases); i++) | |
1941 | { | |
1942 | mask = mips_ase_mask (mips_ases[i].flags); | |
1943 | if ((mips_opts.ase & mask) == mips_ases[i].flags) | |
1944 | mips_check_isa_supports_ase (&mips_ases[i]); | |
1945 | } | |
1946 | } | |
1947 | ||
1948 | /* Set the state of ASE to ENABLED_P. Return the mask of ASE_* flags | |
1949 | that were affected. */ | |
1950 | ||
1951 | static unsigned int | |
1952 | mips_set_ase (const struct mips_ase *ase, bfd_boolean enabled_p) | |
1953 | { | |
1954 | unsigned int mask; | |
1955 | ||
1956 | mask = mips_ase_mask (ase->flags); | |
1957 | mips_opts.ase &= ~mask; | |
1958 | if (enabled_p) | |
1959 | mips_opts.ase |= ase->flags; | |
1960 | return mask; | |
1961 | } | |
1962 | ||
1963 | /* Return the ASE called NAME, or null if none. */ | |
1964 | ||
1965 | static const struct mips_ase * | |
1966 | mips_lookup_ase (const char *name) | |
1967 | { | |
1968 | unsigned int i; | |
1969 | ||
1970 | for (i = 0; i < ARRAY_SIZE (mips_ases); i++) | |
1971 | if (strcmp (name, mips_ases[i].name) == 0) | |
1972 | return &mips_ases[i]; | |
1973 | return NULL; | |
1974 | } | |
1975 | ||
df58fc94 RS |
1976 | /* Return the length of a microMIPS instruction in bytes. If bits of |
1977 | the mask beyond the low 16 are 0, then it is a 16-bit instruction. | |
1978 | Otherwise assume a 32-bit instruction; 48-bit instructions (0x1f | |
1979 | major opcode) will require further modifications to the opcode | |
1980 | table. */ | |
1981 | ||
1982 | static inline unsigned int | |
1983 | micromips_insn_length (const struct mips_opcode *mo) | |
1984 | { | |
1985 | return (mo->mask >> 16) == 0 ? 2 : 4; | |
1986 | } | |
1987 | ||
5c04167a RS |
1988 | /* Return the length of MIPS16 instruction OPCODE. */ |
1989 | ||
1990 | static inline unsigned int | |
1991 | mips16_opcode_length (unsigned long opcode) | |
1992 | { | |
1993 | return (opcode >> 16) == 0 ? 2 : 4; | |
1994 | } | |
1995 | ||
1e915849 RS |
1996 | /* Return the length of instruction INSN. */ |
1997 | ||
1998 | static inline unsigned int | |
1999 | insn_length (const struct mips_cl_insn *insn) | |
2000 | { | |
df58fc94 RS |
2001 | if (mips_opts.micromips) |
2002 | return micromips_insn_length (insn->insn_mo); | |
2003 | else if (mips_opts.mips16) | |
5c04167a | 2004 | return mips16_opcode_length (insn->insn_opcode); |
df58fc94 | 2005 | else |
1e915849 | 2006 | return 4; |
1e915849 RS |
2007 | } |
2008 | ||
2009 | /* Initialise INSN from opcode entry MO. Leave its position unspecified. */ | |
2010 | ||
2011 | static void | |
2012 | create_insn (struct mips_cl_insn *insn, const struct mips_opcode *mo) | |
2013 | { | |
2014 | size_t i; | |
2015 | ||
2016 | insn->insn_mo = mo; | |
1e915849 RS |
2017 | insn->insn_opcode = mo->match; |
2018 | insn->frag = NULL; | |
2019 | insn->where = 0; | |
2020 | for (i = 0; i < ARRAY_SIZE (insn->fixp); i++) | |
2021 | insn->fixp[i] = NULL; | |
2022 | insn->fixed_p = (mips_opts.noreorder > 0); | |
2023 | insn->noreorder_p = (mips_opts.noreorder > 0); | |
2024 | insn->mips16_absolute_jump_p = 0; | |
15be625d | 2025 | insn->complete_p = 0; |
e407c74b | 2026 | insn->cleared_p = 0; |
1e915849 RS |
2027 | } |
2028 | ||
df58fc94 | 2029 | /* Record the current MIPS16/microMIPS mode in now_seg. */ |
742a56fe RS |
2030 | |
2031 | static void | |
df58fc94 | 2032 | mips_record_compressed_mode (void) |
742a56fe RS |
2033 | { |
2034 | segment_info_type *si; | |
2035 | ||
2036 | si = seg_info (now_seg); | |
2037 | if (si->tc_segment_info_data.mips16 != mips_opts.mips16) | |
2038 | si->tc_segment_info_data.mips16 = mips_opts.mips16; | |
df58fc94 RS |
2039 | if (si->tc_segment_info_data.micromips != mips_opts.micromips) |
2040 | si->tc_segment_info_data.micromips = mips_opts.micromips; | |
742a56fe RS |
2041 | } |
2042 | ||
4d68580a RS |
2043 | /* Read a standard MIPS instruction from BUF. */ |
2044 | ||
2045 | static unsigned long | |
2046 | read_insn (char *buf) | |
2047 | { | |
2048 | if (target_big_endian) | |
2049 | return bfd_getb32 ((bfd_byte *) buf); | |
2050 | else | |
2051 | return bfd_getl32 ((bfd_byte *) buf); | |
2052 | } | |
2053 | ||
2054 | /* Write standard MIPS instruction INSN to BUF. Return a pointer to | |
2055 | the next byte. */ | |
2056 | ||
2057 | static char * | |
2058 | write_insn (char *buf, unsigned int insn) | |
2059 | { | |
2060 | md_number_to_chars (buf, insn, 4); | |
2061 | return buf + 4; | |
2062 | } | |
2063 | ||
2064 | /* Read a microMIPS or MIPS16 opcode from BUF, given that it | |
2065 | has length LENGTH. */ | |
2066 | ||
2067 | static unsigned long | |
2068 | read_compressed_insn (char *buf, unsigned int length) | |
2069 | { | |
2070 | unsigned long insn; | |
2071 | unsigned int i; | |
2072 | ||
2073 | insn = 0; | |
2074 | for (i = 0; i < length; i += 2) | |
2075 | { | |
2076 | insn <<= 16; | |
2077 | if (target_big_endian) | |
2078 | insn |= bfd_getb16 ((char *) buf); | |
2079 | else | |
2080 | insn |= bfd_getl16 ((char *) buf); | |
2081 | buf += 2; | |
2082 | } | |
2083 | return insn; | |
2084 | } | |
2085 | ||
5c04167a RS |
2086 | /* Write microMIPS or MIPS16 instruction INSN to BUF, given that the |
2087 | instruction is LENGTH bytes long. Return a pointer to the next byte. */ | |
2088 | ||
2089 | static char * | |
2090 | write_compressed_insn (char *buf, unsigned int insn, unsigned int length) | |
2091 | { | |
2092 | unsigned int i; | |
2093 | ||
2094 | for (i = 0; i < length; i += 2) | |
2095 | md_number_to_chars (buf + i, insn >> ((length - i - 2) * 8), 2); | |
2096 | return buf + length; | |
2097 | } | |
2098 | ||
1e915849 RS |
2099 | /* Install INSN at the location specified by its "frag" and "where" fields. */ |
2100 | ||
2101 | static void | |
2102 | install_insn (const struct mips_cl_insn *insn) | |
2103 | { | |
2104 | char *f = insn->frag->fr_literal + insn->where; | |
5c04167a RS |
2105 | if (HAVE_CODE_COMPRESSION) |
2106 | write_compressed_insn (f, insn->insn_opcode, insn_length (insn)); | |
1e915849 | 2107 | else |
4d68580a | 2108 | write_insn (f, insn->insn_opcode); |
df58fc94 | 2109 | mips_record_compressed_mode (); |
1e915849 RS |
2110 | } |
2111 | ||
2112 | /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly | |
2113 | and install the opcode in the new location. */ | |
2114 | ||
2115 | static void | |
2116 | move_insn (struct mips_cl_insn *insn, fragS *frag, long where) | |
2117 | { | |
2118 | size_t i; | |
2119 | ||
2120 | insn->frag = frag; | |
2121 | insn->where = where; | |
2122 | for (i = 0; i < ARRAY_SIZE (insn->fixp); i++) | |
2123 | if (insn->fixp[i] != NULL) | |
2124 | { | |
2125 | insn->fixp[i]->fx_frag = frag; | |
2126 | insn->fixp[i]->fx_where = where; | |
2127 | } | |
2128 | install_insn (insn); | |
2129 | } | |
2130 | ||
2131 | /* Add INSN to the end of the output. */ | |
2132 | ||
2133 | static void | |
2134 | add_fixed_insn (struct mips_cl_insn *insn) | |
2135 | { | |
2136 | char *f = frag_more (insn_length (insn)); | |
2137 | move_insn (insn, frag_now, f - frag_now->fr_literal); | |
2138 | } | |
2139 | ||
2140 | /* Start a variant frag and move INSN to the start of the variant part, | |
2141 | marking it as fixed. The other arguments are as for frag_var. */ | |
2142 | ||
2143 | static void | |
2144 | add_relaxed_insn (struct mips_cl_insn *insn, int max_chars, int var, | |
2145 | relax_substateT subtype, symbolS *symbol, offsetT offset) | |
2146 | { | |
2147 | frag_grow (max_chars); | |
2148 | move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal); | |
2149 | insn->fixed_p = 1; | |
2150 | frag_var (rs_machine_dependent, max_chars, var, | |
2151 | subtype, symbol, offset, NULL); | |
2152 | } | |
2153 | ||
2154 | /* Insert N copies of INSN into the history buffer, starting at | |
2155 | position FIRST. Neither FIRST nor N need to be clipped. */ | |
2156 | ||
2157 | static void | |
2158 | insert_into_history (unsigned int first, unsigned int n, | |
2159 | const struct mips_cl_insn *insn) | |
2160 | { | |
2161 | if (mips_relax.sequence != 2) | |
2162 | { | |
2163 | unsigned int i; | |
2164 | ||
2165 | for (i = ARRAY_SIZE (history); i-- > first;) | |
2166 | if (i >= first + n) | |
2167 | history[i] = history[i - n]; | |
2168 | else | |
2169 | history[i] = *insn; | |
2170 | } | |
2171 | } | |
2172 | ||
71400594 RS |
2173 | /* Initialize vr4120_conflicts. There is a bit of duplication here: |
2174 | the idea is to make it obvious at a glance that each errata is | |
2175 | included. */ | |
2176 | ||
2177 | static void | |
2178 | init_vr4120_conflicts (void) | |
2179 | { | |
2180 | #define CONFLICT(FIRST, SECOND) \ | |
2181 | vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND | |
2182 | ||
2183 | /* Errata 21 - [D]DIV[U] after [D]MACC */ | |
2184 | CONFLICT (MACC, DIV); | |
2185 | CONFLICT (DMACC, DIV); | |
2186 | ||
2187 | /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */ | |
2188 | CONFLICT (DMULT, DMULT); | |
2189 | CONFLICT (DMULT, DMACC); | |
2190 | CONFLICT (DMACC, DMULT); | |
2191 | CONFLICT (DMACC, DMACC); | |
2192 | ||
2193 | /* Errata 24 - MT{LO,HI} after [D]MACC */ | |
2194 | CONFLICT (MACC, MTHILO); | |
2195 | CONFLICT (DMACC, MTHILO); | |
2196 | ||
2197 | /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU | |
2198 | instruction is executed immediately after a MACC or DMACC | |
2199 | instruction, the result of [either instruction] is incorrect." */ | |
2200 | CONFLICT (MACC, MULT); | |
2201 | CONFLICT (MACC, DMULT); | |
2202 | CONFLICT (DMACC, MULT); | |
2203 | CONFLICT (DMACC, DMULT); | |
2204 | ||
2205 | /* VR4181A errata MD(4): "If a MACC or DMACC instruction is | |
2206 | executed immediately after a DMULT, DMULTU, DIV, DIVU, | |
2207 | DDIV or DDIVU instruction, the result of the MACC or | |
2208 | DMACC instruction is incorrect.". */ | |
2209 | CONFLICT (DMULT, MACC); | |
2210 | CONFLICT (DMULT, DMACC); | |
2211 | CONFLICT (DIV, MACC); | |
2212 | CONFLICT (DIV, DMACC); | |
2213 | ||
2214 | #undef CONFLICT | |
2215 | } | |
2216 | ||
707bfff6 TS |
2217 | struct regname { |
2218 | const char *name; | |
2219 | unsigned int num; | |
2220 | }; | |
2221 | ||
2222 | #define RTYPE_MASK 0x1ff00 | |
2223 | #define RTYPE_NUM 0x00100 | |
2224 | #define RTYPE_FPU 0x00200 | |
2225 | #define RTYPE_FCC 0x00400 | |
2226 | #define RTYPE_VEC 0x00800 | |
2227 | #define RTYPE_GP 0x01000 | |
2228 | #define RTYPE_CP0 0x02000 | |
2229 | #define RTYPE_PC 0x04000 | |
2230 | #define RTYPE_ACC 0x08000 | |
2231 | #define RTYPE_CCC 0x10000 | |
2232 | #define RNUM_MASK 0x000ff | |
2233 | #define RWARN 0x80000 | |
2234 | ||
2235 | #define GENERIC_REGISTER_NUMBERS \ | |
2236 | {"$0", RTYPE_NUM | 0}, \ | |
2237 | {"$1", RTYPE_NUM | 1}, \ | |
2238 | {"$2", RTYPE_NUM | 2}, \ | |
2239 | {"$3", RTYPE_NUM | 3}, \ | |
2240 | {"$4", RTYPE_NUM | 4}, \ | |
2241 | {"$5", RTYPE_NUM | 5}, \ | |
2242 | {"$6", RTYPE_NUM | 6}, \ | |
2243 | {"$7", RTYPE_NUM | 7}, \ | |
2244 | {"$8", RTYPE_NUM | 8}, \ | |
2245 | {"$9", RTYPE_NUM | 9}, \ | |
2246 | {"$10", RTYPE_NUM | 10}, \ | |
2247 | {"$11", RTYPE_NUM | 11}, \ | |
2248 | {"$12", RTYPE_NUM | 12}, \ | |
2249 | {"$13", RTYPE_NUM | 13}, \ | |
2250 | {"$14", RTYPE_NUM | 14}, \ | |
2251 | {"$15", RTYPE_NUM | 15}, \ | |
2252 | {"$16", RTYPE_NUM | 16}, \ | |
2253 | {"$17", RTYPE_NUM | 17}, \ | |
2254 | {"$18", RTYPE_NUM | 18}, \ | |
2255 | {"$19", RTYPE_NUM | 19}, \ | |
2256 | {"$20", RTYPE_NUM | 20}, \ | |
2257 | {"$21", RTYPE_NUM | 21}, \ | |
2258 | {"$22", RTYPE_NUM | 22}, \ | |
2259 | {"$23", RTYPE_NUM | 23}, \ | |
2260 | {"$24", RTYPE_NUM | 24}, \ | |
2261 | {"$25", RTYPE_NUM | 25}, \ | |
2262 | {"$26", RTYPE_NUM | 26}, \ | |
2263 | {"$27", RTYPE_NUM | 27}, \ | |
2264 | {"$28", RTYPE_NUM | 28}, \ | |
2265 | {"$29", RTYPE_NUM | 29}, \ | |
2266 | {"$30", RTYPE_NUM | 30}, \ | |
2267 | {"$31", RTYPE_NUM | 31} | |
2268 | ||
2269 | #define FPU_REGISTER_NAMES \ | |
2270 | {"$f0", RTYPE_FPU | 0}, \ | |
2271 | {"$f1", RTYPE_FPU | 1}, \ | |
2272 | {"$f2", RTYPE_FPU | 2}, \ | |
2273 | {"$f3", RTYPE_FPU | 3}, \ | |
2274 | {"$f4", RTYPE_FPU | 4}, \ | |
2275 | {"$f5", RTYPE_FPU | 5}, \ | |
2276 | {"$f6", RTYPE_FPU | 6}, \ | |
2277 | {"$f7", RTYPE_FPU | 7}, \ | |
2278 | {"$f8", RTYPE_FPU | 8}, \ | |
2279 | {"$f9", RTYPE_FPU | 9}, \ | |
2280 | {"$f10", RTYPE_FPU | 10}, \ | |
2281 | {"$f11", RTYPE_FPU | 11}, \ | |
2282 | {"$f12", RTYPE_FPU | 12}, \ | |
2283 | {"$f13", RTYPE_FPU | 13}, \ | |
2284 | {"$f14", RTYPE_FPU | 14}, \ | |
2285 | {"$f15", RTYPE_FPU | 15}, \ | |
2286 | {"$f16", RTYPE_FPU | 16}, \ | |
2287 | {"$f17", RTYPE_FPU | 17}, \ | |
2288 | {"$f18", RTYPE_FPU | 18}, \ | |
2289 | {"$f19", RTYPE_FPU | 19}, \ | |
2290 | {"$f20", RTYPE_FPU | 20}, \ | |
2291 | {"$f21", RTYPE_FPU | 21}, \ | |
2292 | {"$f22", RTYPE_FPU | 22}, \ | |
2293 | {"$f23", RTYPE_FPU | 23}, \ | |
2294 | {"$f24", RTYPE_FPU | 24}, \ | |
2295 | {"$f25", RTYPE_FPU | 25}, \ | |
2296 | {"$f26", RTYPE_FPU | 26}, \ | |
2297 | {"$f27", RTYPE_FPU | 27}, \ | |
2298 | {"$f28", RTYPE_FPU | 28}, \ | |
2299 | {"$f29", RTYPE_FPU | 29}, \ | |
2300 | {"$f30", RTYPE_FPU | 30}, \ | |
2301 | {"$f31", RTYPE_FPU | 31} | |
2302 | ||
2303 | #define FPU_CONDITION_CODE_NAMES \ | |
2304 | {"$fcc0", RTYPE_FCC | 0}, \ | |
2305 | {"$fcc1", RTYPE_FCC | 1}, \ | |
2306 | {"$fcc2", RTYPE_FCC | 2}, \ | |
2307 | {"$fcc3", RTYPE_FCC | 3}, \ | |
2308 | {"$fcc4", RTYPE_FCC | 4}, \ | |
2309 | {"$fcc5", RTYPE_FCC | 5}, \ | |
2310 | {"$fcc6", RTYPE_FCC | 6}, \ | |
2311 | {"$fcc7", RTYPE_FCC | 7} | |
2312 | ||
2313 | #define COPROC_CONDITION_CODE_NAMES \ | |
2314 | {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \ | |
2315 | {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \ | |
2316 | {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \ | |
2317 | {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \ | |
2318 | {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \ | |
2319 | {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \ | |
2320 | {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \ | |
2321 | {"$cc7", RTYPE_FCC | RTYPE_CCC | 7} | |
2322 | ||
2323 | #define N32N64_SYMBOLIC_REGISTER_NAMES \ | |
2324 | {"$a4", RTYPE_GP | 8}, \ | |
2325 | {"$a5", RTYPE_GP | 9}, \ | |
2326 | {"$a6", RTYPE_GP | 10}, \ | |
2327 | {"$a7", RTYPE_GP | 11}, \ | |
2328 | {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \ | |
2329 | {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \ | |
2330 | {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \ | |
2331 | {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \ | |
2332 | {"$t0", RTYPE_GP | 12}, \ | |
2333 | {"$t1", RTYPE_GP | 13}, \ | |
2334 | {"$t2", RTYPE_GP | 14}, \ | |
2335 | {"$t3", RTYPE_GP | 15} | |
2336 | ||
2337 | #define O32_SYMBOLIC_REGISTER_NAMES \ | |
2338 | {"$t0", RTYPE_GP | 8}, \ | |
2339 | {"$t1", RTYPE_GP | 9}, \ | |
2340 | {"$t2", RTYPE_GP | 10}, \ | |
2341 | {"$t3", RTYPE_GP | 11}, \ | |
2342 | {"$t4", RTYPE_GP | 12}, \ | |
2343 | {"$t5", RTYPE_GP | 13}, \ | |
2344 | {"$t6", RTYPE_GP | 14}, \ | |
2345 | {"$t7", RTYPE_GP | 15}, \ | |
2346 | {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \ | |
2347 | {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \ | |
2348 | {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \ | |
2349 | {"$ta3", RTYPE_GP | 15} /* alias for $t7 */ | |
2350 | ||
2351 | /* Remaining symbolic register names */ | |
2352 | #define SYMBOLIC_REGISTER_NAMES \ | |
2353 | {"$zero", RTYPE_GP | 0}, \ | |
2354 | {"$at", RTYPE_GP | 1}, \ | |
2355 | {"$AT", RTYPE_GP | 1}, \ | |
2356 | {"$v0", RTYPE_GP | 2}, \ | |
2357 | {"$v1", RTYPE_GP | 3}, \ | |
2358 | {"$a0", RTYPE_GP | 4}, \ | |
2359 | {"$a1", RTYPE_GP | 5}, \ | |
2360 | {"$a2", RTYPE_GP | 6}, \ | |
2361 | {"$a3", RTYPE_GP | 7}, \ | |
2362 | {"$s0", RTYPE_GP | 16}, \ | |
2363 | {"$s1", RTYPE_GP | 17}, \ | |
2364 | {"$s2", RTYPE_GP | 18}, \ | |
2365 | {"$s3", RTYPE_GP | 19}, \ | |
2366 | {"$s4", RTYPE_GP | 20}, \ | |
2367 | {"$s5", RTYPE_GP | 21}, \ | |
2368 | {"$s6", RTYPE_GP | 22}, \ | |
2369 | {"$s7", RTYPE_GP | 23}, \ | |
2370 | {"$t8", RTYPE_GP | 24}, \ | |
2371 | {"$t9", RTYPE_GP | 25}, \ | |
2372 | {"$k0", RTYPE_GP | 26}, \ | |
2373 | {"$kt0", RTYPE_GP | 26}, \ | |
2374 | {"$k1", RTYPE_GP | 27}, \ | |
2375 | {"$kt1", RTYPE_GP | 27}, \ | |
2376 | {"$gp", RTYPE_GP | 28}, \ | |
2377 | {"$sp", RTYPE_GP | 29}, \ | |
2378 | {"$s8", RTYPE_GP | 30}, \ | |
2379 | {"$fp", RTYPE_GP | 30}, \ | |
2380 | {"$ra", RTYPE_GP | 31} | |
2381 | ||
2382 | #define MIPS16_SPECIAL_REGISTER_NAMES \ | |
2383 | {"$pc", RTYPE_PC | 0} | |
2384 | ||
2385 | #define MDMX_VECTOR_REGISTER_NAMES \ | |
2386 | /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \ | |
2387 | /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \ | |
2388 | {"$v2", RTYPE_VEC | 2}, \ | |
2389 | {"$v3", RTYPE_VEC | 3}, \ | |
2390 | {"$v4", RTYPE_VEC | 4}, \ | |
2391 | {"$v5", RTYPE_VEC | 5}, \ | |
2392 | {"$v6", RTYPE_VEC | 6}, \ | |
2393 | {"$v7", RTYPE_VEC | 7}, \ | |
2394 | {"$v8", RTYPE_VEC | 8}, \ | |
2395 | {"$v9", RTYPE_VEC | 9}, \ | |
2396 | {"$v10", RTYPE_VEC | 10}, \ | |
2397 | {"$v11", RTYPE_VEC | 11}, \ | |
2398 | {"$v12", RTYPE_VEC | 12}, \ | |
2399 | {"$v13", RTYPE_VEC | 13}, \ | |
2400 | {"$v14", RTYPE_VEC | 14}, \ | |
2401 | {"$v15", RTYPE_VEC | 15}, \ | |
2402 | {"$v16", RTYPE_VEC | 16}, \ | |
2403 | {"$v17", RTYPE_VEC | 17}, \ | |
2404 | {"$v18", RTYPE_VEC | 18}, \ | |
2405 | {"$v19", RTYPE_VEC | 19}, \ | |
2406 | {"$v20", RTYPE_VEC | 20}, \ | |
2407 | {"$v21", RTYPE_VEC | 21}, \ | |
2408 | {"$v22", RTYPE_VEC | 22}, \ | |
2409 | {"$v23", RTYPE_VEC | 23}, \ | |
2410 | {"$v24", RTYPE_VEC | 24}, \ | |
2411 | {"$v25", RTYPE_VEC | 25}, \ | |
2412 | {"$v26", RTYPE_VEC | 26}, \ | |
2413 | {"$v27", RTYPE_VEC | 27}, \ | |
2414 | {"$v28", RTYPE_VEC | 28}, \ | |
2415 | {"$v29", RTYPE_VEC | 29}, \ | |
2416 | {"$v30", RTYPE_VEC | 30}, \ | |
2417 | {"$v31", RTYPE_VEC | 31} | |
2418 | ||
2419 | #define MIPS_DSP_ACCUMULATOR_NAMES \ | |
2420 | {"$ac0", RTYPE_ACC | 0}, \ | |
2421 | {"$ac1", RTYPE_ACC | 1}, \ | |
2422 | {"$ac2", RTYPE_ACC | 2}, \ | |
2423 | {"$ac3", RTYPE_ACC | 3} | |
2424 | ||
2425 | static const struct regname reg_names[] = { | |
2426 | GENERIC_REGISTER_NUMBERS, | |
2427 | FPU_REGISTER_NAMES, | |
2428 | FPU_CONDITION_CODE_NAMES, | |
2429 | COPROC_CONDITION_CODE_NAMES, | |
2430 | ||
2431 | /* The $txx registers depends on the abi, | |
2432 | these will be added later into the symbol table from | |
2433 | one of the tables below once mips_abi is set after | |
2434 | parsing of arguments from the command line. */ | |
2435 | SYMBOLIC_REGISTER_NAMES, | |
2436 | ||
2437 | MIPS16_SPECIAL_REGISTER_NAMES, | |
2438 | MDMX_VECTOR_REGISTER_NAMES, | |
2439 | MIPS_DSP_ACCUMULATOR_NAMES, | |
2440 | {0, 0} | |
2441 | }; | |
2442 | ||
2443 | static const struct regname reg_names_o32[] = { | |
2444 | O32_SYMBOLIC_REGISTER_NAMES, | |
2445 | {0, 0} | |
2446 | }; | |
2447 | ||
2448 | static const struct regname reg_names_n32n64[] = { | |
2449 | N32N64_SYMBOLIC_REGISTER_NAMES, | |
2450 | {0, 0} | |
2451 | }; | |
2452 | ||
df58fc94 RS |
2453 | /* Check if S points at a valid register specifier according to TYPES. |
2454 | If so, then return 1, advance S to consume the specifier and store | |
2455 | the register's number in REGNOP, otherwise return 0. */ | |
2456 | ||
707bfff6 TS |
2457 | static int |
2458 | reg_lookup (char **s, unsigned int types, unsigned int *regnop) | |
2459 | { | |
2460 | symbolS *symbolP; | |
2461 | char *e; | |
2462 | char save_c; | |
2463 | int reg = -1; | |
2464 | ||
2465 | /* Find end of name. */ | |
2466 | e = *s; | |
2467 | if (is_name_beginner (*e)) | |
2468 | ++e; | |
2469 | while (is_part_of_name (*e)) | |
2470 | ++e; | |
2471 | ||
2472 | /* Terminate name. */ | |
2473 | save_c = *e; | |
2474 | *e = '\0'; | |
2475 | ||
2476 | /* Look for a register symbol. */ | |
2477 | if ((symbolP = symbol_find (*s)) && S_GET_SEGMENT (symbolP) == reg_section) | |
2478 | { | |
2479 | int r = S_GET_VALUE (symbolP); | |
2480 | if (r & types) | |
2481 | reg = r & RNUM_MASK; | |
2482 | else if ((types & RTYPE_VEC) && (r & ~1) == (RTYPE_GP | 2)) | |
2483 | /* Convert GP reg $v0/1 to MDMX reg $v0/1! */ | |
2484 | reg = (r & RNUM_MASK) - 2; | |
2485 | } | |
2486 | /* Else see if this is a register defined in an itbl entry. */ | |
2487 | else if ((types & RTYPE_GP) && itbl_have_entries) | |
2488 | { | |
2489 | char *n = *s; | |
2490 | unsigned long r; | |
2491 | ||
2492 | if (*n == '$') | |
2493 | ++n; | |
2494 | if (itbl_get_reg_val (n, &r)) | |
2495 | reg = r & RNUM_MASK; | |
2496 | } | |
2497 | ||
2498 | /* Advance to next token if a register was recognised. */ | |
2499 | if (reg >= 0) | |
2500 | *s = e; | |
2501 | else if (types & RWARN) | |
20203fb9 | 2502 | as_warn (_("Unrecognized register name `%s'"), *s); |
707bfff6 TS |
2503 | |
2504 | *e = save_c; | |
2505 | if (regnop) | |
2506 | *regnop = reg; | |
2507 | return reg >= 0; | |
2508 | } | |
2509 | ||
df58fc94 RS |
2510 | /* Check if S points at a valid register list according to TYPES. |
2511 | If so, then return 1, advance S to consume the list and store | |
2512 | the registers present on the list as a bitmask of ones in REGLISTP, | |
2513 | otherwise return 0. A valid list comprises a comma-separated | |
2514 | enumeration of valid single registers and/or dash-separated | |
2515 | contiguous register ranges as determined by their numbers. | |
2516 | ||
2517 | As a special exception if one of s0-s7 registers is specified as | |
2518 | the range's lower delimiter and s8 (fp) is its upper one, then no | |
2519 | registers whose numbers place them between s7 and s8 (i.e. $24-$29) | |
2309ddf2 | 2520 | are selected; they have to be listed separately if needed. */ |
df58fc94 RS |
2521 | |
2522 | static int | |
2523 | reglist_lookup (char **s, unsigned int types, unsigned int *reglistp) | |
2524 | { | |
2525 | unsigned int reglist = 0; | |
2526 | unsigned int lastregno; | |
2527 | bfd_boolean ok = TRUE; | |
2528 | unsigned int regmask; | |
2309ddf2 | 2529 | char *s_endlist = *s; |
df58fc94 | 2530 | char *s_reset = *s; |
2309ddf2 | 2531 | unsigned int regno; |
df58fc94 RS |
2532 | |
2533 | while (reg_lookup (s, types, ®no)) | |
2534 | { | |
2535 | lastregno = regno; | |
2536 | if (**s == '-') | |
2537 | { | |
2538 | (*s)++; | |
2539 | ok = reg_lookup (s, types, &lastregno); | |
2540 | if (ok && lastregno < regno) | |
2541 | ok = FALSE; | |
2542 | if (!ok) | |
2543 | break; | |
2544 | } | |
2545 | ||
2546 | if (lastregno == FP && regno >= S0 && regno <= S7) | |
2547 | { | |
2548 | lastregno = S7; | |
2549 | reglist |= 1 << FP; | |
2550 | } | |
2551 | regmask = 1 << lastregno; | |
2552 | regmask = (regmask << 1) - 1; | |
2553 | regmask ^= (1 << regno) - 1; | |
2554 | reglist |= regmask; | |
2555 | ||
2309ddf2 | 2556 | s_endlist = *s; |
df58fc94 RS |
2557 | if (**s != ',') |
2558 | break; | |
2559 | (*s)++; | |
2560 | } | |
2561 | ||
2562 | if (ok) | |
2309ddf2 | 2563 | *s = s_endlist; |
df58fc94 RS |
2564 | else |
2565 | *s = s_reset; | |
2566 | if (reglistp) | |
2567 | *reglistp = reglist; | |
2568 | return ok && reglist != 0; | |
2569 | } | |
2570 | ||
d301a56b RS |
2571 | /* Return TRUE if opcode MO is valid on the currently selected ISA, ASE |
2572 | and architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */ | |
037b32b9 AN |
2573 | |
2574 | static bfd_boolean | |
f79e2745 | 2575 | is_opcode_valid (const struct mips_opcode *mo) |
037b32b9 AN |
2576 | { |
2577 | int isa = mips_opts.isa; | |
846ef2d0 | 2578 | int ase = mips_opts.ase; |
037b32b9 | 2579 | int fp_s, fp_d; |
c6278170 | 2580 | unsigned int i; |
037b32b9 | 2581 | |
c6278170 RS |
2582 | if (ISA_HAS_64BIT_REGS (mips_opts.isa)) |
2583 | for (i = 0; i < ARRAY_SIZE (mips_ases); i++) | |
2584 | if ((ase & mips_ases[i].flags) == mips_ases[i].flags) | |
2585 | ase |= mips_ases[i].flags64; | |
037b32b9 | 2586 | |
d301a56b | 2587 | if (!opcode_is_member (mo, isa, ase, mips_opts.arch)) |
037b32b9 AN |
2588 | return FALSE; |
2589 | ||
2590 | /* Check whether the instruction or macro requires single-precision or | |
2591 | double-precision floating-point support. Note that this information is | |
2592 | stored differently in the opcode table for insns and macros. */ | |
2593 | if (mo->pinfo == INSN_MACRO) | |
2594 | { | |
2595 | fp_s = mo->pinfo2 & INSN2_M_FP_S; | |
2596 | fp_d = mo->pinfo2 & INSN2_M_FP_D; | |
2597 | } | |
2598 | else | |
2599 | { | |
2600 | fp_s = mo->pinfo & FP_S; | |
2601 | fp_d = mo->pinfo & FP_D; | |
2602 | } | |
2603 | ||
2604 | if (fp_d && (mips_opts.soft_float || mips_opts.single_float)) | |
2605 | return FALSE; | |
2606 | ||
2607 | if (fp_s && mips_opts.soft_float) | |
2608 | return FALSE; | |
2609 | ||
2610 | return TRUE; | |
2611 | } | |
2612 | ||
2613 | /* Return TRUE if the MIPS16 opcode MO is valid on the currently | |
2614 | selected ISA and architecture. */ | |
2615 | ||
2616 | static bfd_boolean | |
2617 | is_opcode_valid_16 (const struct mips_opcode *mo) | |
2618 | { | |
d301a56b | 2619 | return opcode_is_member (mo, mips_opts.isa, 0, mips_opts.arch); |
037b32b9 AN |
2620 | } |
2621 | ||
df58fc94 RS |
2622 | /* Return TRUE if the size of the microMIPS opcode MO matches one |
2623 | explicitly requested. Always TRUE in the standard MIPS mode. */ | |
2624 | ||
2625 | static bfd_boolean | |
2626 | is_size_valid (const struct mips_opcode *mo) | |
2627 | { | |
2628 | if (!mips_opts.micromips) | |
2629 | return TRUE; | |
2630 | ||
2631 | if (!forced_insn_length) | |
2632 | return TRUE; | |
2633 | if (mo->pinfo == INSN_MACRO) | |
2634 | return FALSE; | |
2635 | return forced_insn_length == micromips_insn_length (mo); | |
2636 | } | |
2637 | ||
2638 | /* Return TRUE if the microMIPS opcode MO is valid for the delay slot | |
e64af278 MR |
2639 | of the preceding instruction. Always TRUE in the standard MIPS mode. |
2640 | ||
2641 | We don't accept macros in 16-bit delay slots to avoid a case where | |
2642 | a macro expansion fails because it relies on a preceding 32-bit real | |
2643 | instruction to have matched and does not handle the operands correctly. | |
2644 | The only macros that may expand to 16-bit instructions are JAL that | |
2645 | cannot be placed in a delay slot anyway, and corner cases of BALIGN | |
2646 | and BGT (that likewise cannot be placed in a delay slot) that decay to | |
2647 | a NOP. In all these cases the macros precede any corresponding real | |
2648 | instruction definitions in the opcode table, so they will match in the | |
2649 | second pass where the size of the delay slot is ignored and therefore | |
2650 | produce correct code. */ | |
df58fc94 RS |
2651 | |
2652 | static bfd_boolean | |
2653 | is_delay_slot_valid (const struct mips_opcode *mo) | |
2654 | { | |
2655 | if (!mips_opts.micromips) | |
2656 | return TRUE; | |
2657 | ||
2658 | if (mo->pinfo == INSN_MACRO) | |
c06dec14 | 2659 | return (history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) == 0; |
df58fc94 RS |
2660 | if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0 |
2661 | && micromips_insn_length (mo) != 4) | |
2662 | return FALSE; | |
2663 | if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 | |
2664 | && micromips_insn_length (mo) != 2) | |
2665 | return FALSE; | |
2666 | ||
2667 | return TRUE; | |
2668 | } | |
2669 | ||
707bfff6 TS |
2670 | /* This function is called once, at assembler startup time. It should set up |
2671 | all the tables, etc. that the MD part of the assembler will need. */ | |
156c2f8b | 2672 | |
252b5132 | 2673 | void |
17a2f251 | 2674 | md_begin (void) |
252b5132 | 2675 | { |
3994f87e | 2676 | const char *retval = NULL; |
156c2f8b | 2677 | int i = 0; |
252b5132 | 2678 | int broken = 0; |
1f25f5d3 | 2679 | |
0a44bf69 RS |
2680 | if (mips_pic != NO_PIC) |
2681 | { | |
2682 | if (g_switch_seen && g_switch_value != 0) | |
2683 | as_bad (_("-G may not be used in position-independent code")); | |
2684 | g_switch_value = 0; | |
2685 | } | |
2686 | ||
fef14a42 | 2687 | if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_arch)) |
252b5132 RH |
2688 | as_warn (_("Could not set architecture and machine")); |
2689 | ||
252b5132 RH |
2690 | op_hash = hash_new (); |
2691 | ||
2692 | for (i = 0; i < NUMOPCODES;) | |
2693 | { | |
2694 | const char *name = mips_opcodes[i].name; | |
2695 | ||
17a2f251 | 2696 | retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]); |
252b5132 RH |
2697 | if (retval != NULL) |
2698 | { | |
2699 | fprintf (stderr, _("internal error: can't hash `%s': %s\n"), | |
2700 | mips_opcodes[i].name, retval); | |
2701 | /* Probably a memory allocation problem? Give up now. */ | |
2702 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
2703 | } | |
2704 | do | |
2705 | { | |
2706 | if (mips_opcodes[i].pinfo != INSN_MACRO) | |
2707 | { | |
2708 | if (!validate_mips_insn (&mips_opcodes[i])) | |
2709 | broken = 1; | |
1e915849 RS |
2710 | if (nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0) |
2711 | { | |
2712 | create_insn (&nop_insn, mips_opcodes + i); | |
c67a084a NC |
2713 | if (mips_fix_loongson2f_nop) |
2714 | nop_insn.insn_opcode = LOONGSON2F_NOP_INSN; | |
1e915849 RS |
2715 | nop_insn.fixed_p = 1; |
2716 | } | |
252b5132 RH |
2717 | } |
2718 | ++i; | |
2719 | } | |
2720 | while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name)); | |
2721 | } | |
2722 | ||
2723 | mips16_op_hash = hash_new (); | |
2724 | ||
2725 | i = 0; | |
2726 | while (i < bfd_mips16_num_opcodes) | |
2727 | { | |
2728 | const char *name = mips16_opcodes[i].name; | |
2729 | ||
17a2f251 | 2730 | retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]); |
252b5132 RH |
2731 | if (retval != NULL) |
2732 | as_fatal (_("internal: can't hash `%s': %s"), | |
2733 | mips16_opcodes[i].name, retval); | |
2734 | do | |
2735 | { | |
2736 | if (mips16_opcodes[i].pinfo != INSN_MACRO | |
2737 | && ((mips16_opcodes[i].match & mips16_opcodes[i].mask) | |
2738 | != mips16_opcodes[i].match)) | |
2739 | { | |
2740 | fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"), | |
2741 | mips16_opcodes[i].name, mips16_opcodes[i].args); | |
2742 | broken = 1; | |
2743 | } | |
1e915849 RS |
2744 | if (mips16_nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0) |
2745 | { | |
2746 | create_insn (&mips16_nop_insn, mips16_opcodes + i); | |
2747 | mips16_nop_insn.fixed_p = 1; | |
2748 | } | |
252b5132 RH |
2749 | ++i; |
2750 | } | |
2751 | while (i < bfd_mips16_num_opcodes | |
2752 | && strcmp (mips16_opcodes[i].name, name) == 0); | |
2753 | } | |
2754 | ||
df58fc94 RS |
2755 | micromips_op_hash = hash_new (); |
2756 | ||
2757 | i = 0; | |
2758 | while (i < bfd_micromips_num_opcodes) | |
2759 | { | |
2760 | const char *name = micromips_opcodes[i].name; | |
2761 | ||
2762 | retval = hash_insert (micromips_op_hash, name, | |
2763 | (void *) µmips_opcodes[i]); | |
2764 | if (retval != NULL) | |
2765 | as_fatal (_("internal: can't hash `%s': %s"), | |
2766 | micromips_opcodes[i].name, retval); | |
2767 | do | |
2768 | if (micromips_opcodes[i].pinfo != INSN_MACRO) | |
2769 | { | |
2770 | struct mips_cl_insn *micromips_nop_insn; | |
2771 | ||
2772 | if (!validate_micromips_insn (µmips_opcodes[i])) | |
2773 | broken = 1; | |
2774 | ||
2775 | if (micromips_insn_length (micromips_opcodes + i) == 2) | |
2776 | micromips_nop_insn = µmips_nop16_insn; | |
2777 | else if (micromips_insn_length (micromips_opcodes + i) == 4) | |
2778 | micromips_nop_insn = µmips_nop32_insn; | |
2779 | else | |
2780 | continue; | |
2781 | ||
2782 | if (micromips_nop_insn->insn_mo == NULL | |
2783 | && strcmp (name, "nop") == 0) | |
2784 | { | |
2785 | create_insn (micromips_nop_insn, micromips_opcodes + i); | |
2786 | micromips_nop_insn->fixed_p = 1; | |
2787 | } | |
2788 | } | |
2789 | while (++i < bfd_micromips_num_opcodes | |
2790 | && strcmp (micromips_opcodes[i].name, name) == 0); | |
2791 | } | |
2792 | ||
252b5132 RH |
2793 | if (broken) |
2794 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
2795 | ||
2796 | /* We add all the general register names to the symbol table. This | |
2797 | helps us detect invalid uses of them. */ | |
707bfff6 TS |
2798 | for (i = 0; reg_names[i].name; i++) |
2799 | symbol_table_insert (symbol_new (reg_names[i].name, reg_section, | |
8fc4ee9b | 2800 | reg_names[i].num, /* & RNUM_MASK, */ |
707bfff6 TS |
2801 | &zero_address_frag)); |
2802 | if (HAVE_NEWABI) | |
2803 | for (i = 0; reg_names_n32n64[i].name; i++) | |
2804 | symbol_table_insert (symbol_new (reg_names_n32n64[i].name, reg_section, | |
8fc4ee9b | 2805 | reg_names_n32n64[i].num, /* & RNUM_MASK, */ |
252b5132 | 2806 | &zero_address_frag)); |
707bfff6 TS |
2807 | else |
2808 | for (i = 0; reg_names_o32[i].name; i++) | |
2809 | symbol_table_insert (symbol_new (reg_names_o32[i].name, reg_section, | |
8fc4ee9b | 2810 | reg_names_o32[i].num, /* & RNUM_MASK, */ |
6047c971 | 2811 | &zero_address_frag)); |
6047c971 | 2812 | |
7d10b47d | 2813 | mips_no_prev_insn (); |
252b5132 RH |
2814 | |
2815 | mips_gprmask = 0; | |
2816 | mips_cprmask[0] = 0; | |
2817 | mips_cprmask[1] = 0; | |
2818 | mips_cprmask[2] = 0; | |
2819 | mips_cprmask[3] = 0; | |
2820 | ||
2821 | /* set the default alignment for the text section (2**2) */ | |
2822 | record_alignment (text_section, 2); | |
2823 | ||
4d0d148d | 2824 | bfd_set_gp_size (stdoutput, g_switch_value); |
252b5132 | 2825 | |
f3ded42a RS |
2826 | /* On a native system other than VxWorks, sections must be aligned |
2827 | to 16 byte boundaries. When configured for an embedded ELF | |
2828 | target, we don't bother. */ | |
2829 | if (strncmp (TARGET_OS, "elf", 3) != 0 | |
2830 | && strncmp (TARGET_OS, "vxworks", 7) != 0) | |
252b5132 | 2831 | { |
f3ded42a RS |
2832 | (void) bfd_set_section_alignment (stdoutput, text_section, 4); |
2833 | (void) bfd_set_section_alignment (stdoutput, data_section, 4); | |
2834 | (void) bfd_set_section_alignment (stdoutput, bss_section, 4); | |
2835 | } | |
252b5132 | 2836 | |
f3ded42a RS |
2837 | /* Create a .reginfo section for register masks and a .mdebug |
2838 | section for debugging information. */ | |
2839 | { | |
2840 | segT seg; | |
2841 | subsegT subseg; | |
2842 | flagword flags; | |
2843 | segT sec; | |
2844 | ||
2845 | seg = now_seg; | |
2846 | subseg = now_subseg; | |
2847 | ||
2848 | /* The ABI says this section should be loaded so that the | |
2849 | running program can access it. However, we don't load it | |
2850 | if we are configured for an embedded target */ | |
2851 | flags = SEC_READONLY | SEC_DATA; | |
2852 | if (strncmp (TARGET_OS, "elf", 3) != 0) | |
2853 | flags |= SEC_ALLOC | SEC_LOAD; | |
2854 | ||
2855 | if (mips_abi != N64_ABI) | |
252b5132 | 2856 | { |
f3ded42a | 2857 | sec = subseg_new (".reginfo", (subsegT) 0); |
bdaaa2e1 | 2858 | |
f3ded42a RS |
2859 | bfd_set_section_flags (stdoutput, sec, flags); |
2860 | bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2); | |
252b5132 | 2861 | |
f3ded42a RS |
2862 | mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo)); |
2863 | } | |
2864 | else | |
2865 | { | |
2866 | /* The 64-bit ABI uses a .MIPS.options section rather than | |
2867 | .reginfo section. */ | |
2868 | sec = subseg_new (".MIPS.options", (subsegT) 0); | |
2869 | bfd_set_section_flags (stdoutput, sec, flags); | |
2870 | bfd_set_section_alignment (stdoutput, sec, 3); | |
252b5132 | 2871 | |
f3ded42a RS |
2872 | /* Set up the option header. */ |
2873 | { | |
2874 | Elf_Internal_Options opthdr; | |
2875 | char *f; | |
2876 | ||
2877 | opthdr.kind = ODK_REGINFO; | |
2878 | opthdr.size = (sizeof (Elf_External_Options) | |
2879 | + sizeof (Elf64_External_RegInfo)); | |
2880 | opthdr.section = 0; | |
2881 | opthdr.info = 0; | |
2882 | f = frag_more (sizeof (Elf_External_Options)); | |
2883 | bfd_mips_elf_swap_options_out (stdoutput, &opthdr, | |
2884 | (Elf_External_Options *) f); | |
2885 | ||
2886 | mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo)); | |
2887 | } | |
2888 | } | |
252b5132 | 2889 | |
f3ded42a RS |
2890 | if (ECOFF_DEBUGGING) |
2891 | { | |
2892 | sec = subseg_new (".mdebug", (subsegT) 0); | |
2893 | (void) bfd_set_section_flags (stdoutput, sec, | |
2894 | SEC_HAS_CONTENTS | SEC_READONLY); | |
2895 | (void) bfd_set_section_alignment (stdoutput, sec, 2); | |
252b5132 | 2896 | } |
f3ded42a RS |
2897 | else if (mips_flag_pdr) |
2898 | { | |
2899 | pdr_seg = subseg_new (".pdr", (subsegT) 0); | |
2900 | (void) bfd_set_section_flags (stdoutput, pdr_seg, | |
2901 | SEC_READONLY | SEC_RELOC | |
2902 | | SEC_DEBUGGING); | |
2903 | (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2); | |
2904 | } | |
2905 | ||
2906 | subseg_set (seg, subseg); | |
2907 | } | |
252b5132 RH |
2908 | |
2909 | if (! ECOFF_DEBUGGING) | |
2910 | md_obj_begin (); | |
71400594 RS |
2911 | |
2912 | if (mips_fix_vr4120) | |
2913 | init_vr4120_conflicts (); | |
252b5132 RH |
2914 | } |
2915 | ||
2916 | void | |
17a2f251 | 2917 | md_mips_end (void) |
252b5132 | 2918 | { |
02b1ab82 | 2919 | mips_emit_delays (); |
252b5132 RH |
2920 | if (! ECOFF_DEBUGGING) |
2921 | md_obj_end (); | |
2922 | } | |
2923 | ||
2924 | void | |
17a2f251 | 2925 | md_assemble (char *str) |
252b5132 RH |
2926 | { |
2927 | struct mips_cl_insn insn; | |
f6688943 TS |
2928 | bfd_reloc_code_real_type unused_reloc[3] |
2929 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 RH |
2930 | |
2931 | imm_expr.X_op = O_absent; | |
5f74bc13 | 2932 | imm2_expr.X_op = O_absent; |
252b5132 | 2933 | offset_expr.X_op = O_absent; |
f6688943 TS |
2934 | imm_reloc[0] = BFD_RELOC_UNUSED; |
2935 | imm_reloc[1] = BFD_RELOC_UNUSED; | |
2936 | imm_reloc[2] = BFD_RELOC_UNUSED; | |
2937 | offset_reloc[0] = BFD_RELOC_UNUSED; | |
2938 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
2939 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 | 2940 | |
e1b47bd5 RS |
2941 | mips_mark_labels (); |
2942 | mips_assembling_insn = TRUE; | |
2943 | ||
252b5132 RH |
2944 | if (mips_opts.mips16) |
2945 | mips16_ip (str, &insn); | |
2946 | else | |
2947 | { | |
2948 | mips_ip (str, &insn); | |
beae10d5 KH |
2949 | DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"), |
2950 | str, insn.insn_opcode)); | |
252b5132 RH |
2951 | } |
2952 | ||
2953 | if (insn_error) | |
e1b47bd5 RS |
2954 | as_bad ("%s `%s'", insn_error, str); |
2955 | else if (insn.insn_mo->pinfo == INSN_MACRO) | |
252b5132 | 2956 | { |
584892a6 | 2957 | macro_start (); |
252b5132 RH |
2958 | if (mips_opts.mips16) |
2959 | mips16_macro (&insn); | |
2960 | else | |
2961 | macro (&insn); | |
584892a6 | 2962 | macro_end (); |
252b5132 RH |
2963 | } |
2964 | else | |
2965 | { | |
2966 | if (imm_expr.X_op != O_absent) | |
df58fc94 | 2967 | append_insn (&insn, &imm_expr, imm_reloc, FALSE); |
252b5132 | 2968 | else if (offset_expr.X_op != O_absent) |
df58fc94 | 2969 | append_insn (&insn, &offset_expr, offset_reloc, FALSE); |
252b5132 | 2970 | else |
df58fc94 | 2971 | append_insn (&insn, NULL, unused_reloc, FALSE); |
252b5132 | 2972 | } |
e1b47bd5 RS |
2973 | |
2974 | mips_assembling_insn = FALSE; | |
252b5132 RH |
2975 | } |
2976 | ||
738e5348 RS |
2977 | /* Convenience functions for abstracting away the differences between |
2978 | MIPS16 and non-MIPS16 relocations. */ | |
2979 | ||
2980 | static inline bfd_boolean | |
2981 | mips16_reloc_p (bfd_reloc_code_real_type reloc) | |
2982 | { | |
2983 | switch (reloc) | |
2984 | { | |
2985 | case BFD_RELOC_MIPS16_JMP: | |
2986 | case BFD_RELOC_MIPS16_GPREL: | |
2987 | case BFD_RELOC_MIPS16_GOT16: | |
2988 | case BFD_RELOC_MIPS16_CALL16: | |
2989 | case BFD_RELOC_MIPS16_HI16_S: | |
2990 | case BFD_RELOC_MIPS16_HI16: | |
2991 | case BFD_RELOC_MIPS16_LO16: | |
2992 | return TRUE; | |
2993 | ||
2994 | default: | |
2995 | return FALSE; | |
2996 | } | |
2997 | } | |
2998 | ||
df58fc94 RS |
2999 | static inline bfd_boolean |
3000 | micromips_reloc_p (bfd_reloc_code_real_type reloc) | |
3001 | { | |
3002 | switch (reloc) | |
3003 | { | |
3004 | case BFD_RELOC_MICROMIPS_7_PCREL_S1: | |
3005 | case BFD_RELOC_MICROMIPS_10_PCREL_S1: | |
3006 | case BFD_RELOC_MICROMIPS_16_PCREL_S1: | |
3007 | case BFD_RELOC_MICROMIPS_GPREL16: | |
3008 | case BFD_RELOC_MICROMIPS_JMP: | |
3009 | case BFD_RELOC_MICROMIPS_HI16: | |
3010 | case BFD_RELOC_MICROMIPS_HI16_S: | |
3011 | case BFD_RELOC_MICROMIPS_LO16: | |
3012 | case BFD_RELOC_MICROMIPS_LITERAL: | |
3013 | case BFD_RELOC_MICROMIPS_GOT16: | |
3014 | case BFD_RELOC_MICROMIPS_CALL16: | |
3015 | case BFD_RELOC_MICROMIPS_GOT_HI16: | |
3016 | case BFD_RELOC_MICROMIPS_GOT_LO16: | |
3017 | case BFD_RELOC_MICROMIPS_CALL_HI16: | |
3018 | case BFD_RELOC_MICROMIPS_CALL_LO16: | |
3019 | case BFD_RELOC_MICROMIPS_SUB: | |
3020 | case BFD_RELOC_MICROMIPS_GOT_PAGE: | |
3021 | case BFD_RELOC_MICROMIPS_GOT_OFST: | |
3022 | case BFD_RELOC_MICROMIPS_GOT_DISP: | |
3023 | case BFD_RELOC_MICROMIPS_HIGHEST: | |
3024 | case BFD_RELOC_MICROMIPS_HIGHER: | |
3025 | case BFD_RELOC_MICROMIPS_SCN_DISP: | |
3026 | case BFD_RELOC_MICROMIPS_JALR: | |
3027 | return TRUE; | |
3028 | ||
3029 | default: | |
3030 | return FALSE; | |
3031 | } | |
3032 | } | |
3033 | ||
2309ddf2 MR |
3034 | static inline bfd_boolean |
3035 | jmp_reloc_p (bfd_reloc_code_real_type reloc) | |
3036 | { | |
3037 | return reloc == BFD_RELOC_MIPS_JMP || reloc == BFD_RELOC_MICROMIPS_JMP; | |
3038 | } | |
3039 | ||
738e5348 RS |
3040 | static inline bfd_boolean |
3041 | got16_reloc_p (bfd_reloc_code_real_type reloc) | |
3042 | { | |
2309ddf2 | 3043 | return (reloc == BFD_RELOC_MIPS_GOT16 || reloc == BFD_RELOC_MIPS16_GOT16 |
df58fc94 | 3044 | || reloc == BFD_RELOC_MICROMIPS_GOT16); |
738e5348 RS |
3045 | } |
3046 | ||
3047 | static inline bfd_boolean | |
3048 | hi16_reloc_p (bfd_reloc_code_real_type reloc) | |
3049 | { | |
2309ddf2 | 3050 | return (reloc == BFD_RELOC_HI16_S || reloc == BFD_RELOC_MIPS16_HI16_S |
df58fc94 | 3051 | || reloc == BFD_RELOC_MICROMIPS_HI16_S); |
738e5348 RS |
3052 | } |
3053 | ||
3054 | static inline bfd_boolean | |
3055 | lo16_reloc_p (bfd_reloc_code_real_type reloc) | |
3056 | { | |
2309ddf2 | 3057 | return (reloc == BFD_RELOC_LO16 || reloc == BFD_RELOC_MIPS16_LO16 |
df58fc94 RS |
3058 | || reloc == BFD_RELOC_MICROMIPS_LO16); |
3059 | } | |
3060 | ||
df58fc94 RS |
3061 | static inline bfd_boolean |
3062 | jalr_reloc_p (bfd_reloc_code_real_type reloc) | |
3063 | { | |
2309ddf2 | 3064 | return reloc == BFD_RELOC_MIPS_JALR || reloc == BFD_RELOC_MICROMIPS_JALR; |
738e5348 RS |
3065 | } |
3066 | ||
2de39019 CM |
3067 | /* Return true if RELOC is a PC-relative relocation that does not have |
3068 | full address range. */ | |
3069 | ||
3070 | static inline bfd_boolean | |
3071 | limited_pcrel_reloc_p (bfd_reloc_code_real_type reloc) | |
3072 | { | |
3073 | switch (reloc) | |
3074 | { | |
3075 | case BFD_RELOC_16_PCREL_S2: | |
3076 | case BFD_RELOC_MICROMIPS_7_PCREL_S1: | |
3077 | case BFD_RELOC_MICROMIPS_10_PCREL_S1: | |
3078 | case BFD_RELOC_MICROMIPS_16_PCREL_S1: | |
3079 | return TRUE; | |
3080 | ||
b47468a6 CM |
3081 | case BFD_RELOC_32_PCREL: |
3082 | return HAVE_64BIT_ADDRESSES; | |
3083 | ||
2de39019 CM |
3084 | default: |
3085 | return FALSE; | |
3086 | } | |
3087 | } | |
b47468a6 | 3088 | |
5919d012 | 3089 | /* Return true if the given relocation might need a matching %lo(). |
0a44bf69 RS |
3090 | This is only "might" because SVR4 R_MIPS_GOT16 relocations only |
3091 | need a matching %lo() when applied to local symbols. */ | |
5919d012 RS |
3092 | |
3093 | static inline bfd_boolean | |
17a2f251 | 3094 | reloc_needs_lo_p (bfd_reloc_code_real_type reloc) |
5919d012 | 3095 | { |
3b91255e | 3096 | return (HAVE_IN_PLACE_ADDENDS |
738e5348 | 3097 | && (hi16_reloc_p (reloc) |
0a44bf69 RS |
3098 | /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo(); |
3099 | all GOT16 relocations evaluate to "G". */ | |
738e5348 RS |
3100 | || (got16_reloc_p (reloc) && mips_pic != VXWORKS_PIC))); |
3101 | } | |
3102 | ||
3103 | /* Return the type of %lo() reloc needed by RELOC, given that | |
3104 | reloc_needs_lo_p. */ | |
3105 | ||
3106 | static inline bfd_reloc_code_real_type | |
3107 | matching_lo_reloc (bfd_reloc_code_real_type reloc) | |
3108 | { | |
df58fc94 RS |
3109 | return (mips16_reloc_p (reloc) ? BFD_RELOC_MIPS16_LO16 |
3110 | : (micromips_reloc_p (reloc) ? BFD_RELOC_MICROMIPS_LO16 | |
3111 | : BFD_RELOC_LO16)); | |
5919d012 RS |
3112 | } |
3113 | ||
3114 | /* Return true if the given fixup is followed by a matching R_MIPS_LO16 | |
3115 | relocation. */ | |
3116 | ||
3117 | static inline bfd_boolean | |
17a2f251 | 3118 | fixup_has_matching_lo_p (fixS *fixp) |
5919d012 RS |
3119 | { |
3120 | return (fixp->fx_next != NULL | |
738e5348 | 3121 | && fixp->fx_next->fx_r_type == matching_lo_reloc (fixp->fx_r_type) |
5919d012 RS |
3122 | && fixp->fx_addsy == fixp->fx_next->fx_addsy |
3123 | && fixp->fx_offset == fixp->fx_next->fx_offset); | |
3124 | } | |
3125 | ||
252b5132 RH |
3126 | /* This function returns true if modifying a register requires a |
3127 | delay. */ | |
3128 | ||
3129 | static int | |
17a2f251 | 3130 | reg_needs_delay (unsigned int reg) |
252b5132 RH |
3131 | { |
3132 | unsigned long prev_pinfo; | |
3133 | ||
47e39b9d | 3134 | prev_pinfo = history[0].insn_mo->pinfo; |
252b5132 | 3135 | if (! mips_opts.noreorder |
81912461 ILT |
3136 | && (((prev_pinfo & INSN_LOAD_MEMORY_DELAY) |
3137 | && ! gpr_interlocks) | |
3138 | || ((prev_pinfo & INSN_LOAD_COPROC_DELAY) | |
3139 | && ! cop_interlocks))) | |
252b5132 | 3140 | { |
81912461 ILT |
3141 | /* A load from a coprocessor or from memory. All load delays |
3142 | delay the use of general register rt for one instruction. */ | |
bdaaa2e1 | 3143 | /* Itbl support may require additional care here. */ |
252b5132 | 3144 | know (prev_pinfo & INSN_WRITE_GPR_T); |
df58fc94 | 3145 | if (reg == EXTRACT_OPERAND (mips_opts.micromips, RT, history[0])) |
252b5132 RH |
3146 | return 1; |
3147 | } | |
3148 | ||
3149 | return 0; | |
3150 | } | |
3151 | ||
462427c4 RS |
3152 | /* Move all labels in LABELS to the current insertion point. TEXT_P |
3153 | says whether the labels refer to text or data. */ | |
404a8071 RS |
3154 | |
3155 | static void | |
462427c4 | 3156 | mips_move_labels (struct insn_label_list *labels, bfd_boolean text_p) |
404a8071 RS |
3157 | { |
3158 | struct insn_label_list *l; | |
3159 | valueT val; | |
3160 | ||
462427c4 | 3161 | for (l = labels; l != NULL; l = l->next) |
404a8071 | 3162 | { |
9c2799c2 | 3163 | gas_assert (S_GET_SEGMENT (l->label) == now_seg); |
404a8071 RS |
3164 | symbol_set_frag (l->label, frag_now); |
3165 | val = (valueT) frag_now_fix (); | |
df58fc94 | 3166 | /* MIPS16/microMIPS text labels are stored as odd. */ |
462427c4 | 3167 | if (text_p && HAVE_CODE_COMPRESSION) |
404a8071 RS |
3168 | ++val; |
3169 | S_SET_VALUE (l->label, val); | |
3170 | } | |
3171 | } | |
3172 | ||
462427c4 RS |
3173 | /* Move all labels in insn_labels to the current insertion point |
3174 | and treat them as text labels. */ | |
3175 | ||
3176 | static void | |
3177 | mips_move_text_labels (void) | |
3178 | { | |
3179 | mips_move_labels (seg_info (now_seg)->label_list, TRUE); | |
3180 | } | |
3181 | ||
5f0fe04b TS |
3182 | static bfd_boolean |
3183 | s_is_linkonce (symbolS *sym, segT from_seg) | |
3184 | { | |
3185 | bfd_boolean linkonce = FALSE; | |
3186 | segT symseg = S_GET_SEGMENT (sym); | |
3187 | ||
3188 | if (symseg != from_seg && !S_IS_LOCAL (sym)) | |
3189 | { | |
3190 | if ((bfd_get_section_flags (stdoutput, symseg) & SEC_LINK_ONCE)) | |
3191 | linkonce = TRUE; | |
5f0fe04b TS |
3192 | /* The GNU toolchain uses an extension for ELF: a section |
3193 | beginning with the magic string .gnu.linkonce is a | |
3194 | linkonce section. */ | |
3195 | if (strncmp (segment_name (symseg), ".gnu.linkonce", | |
3196 | sizeof ".gnu.linkonce" - 1) == 0) | |
3197 | linkonce = TRUE; | |
5f0fe04b TS |
3198 | } |
3199 | return linkonce; | |
3200 | } | |
3201 | ||
e1b47bd5 | 3202 | /* Mark MIPS16 or microMIPS instruction label LABEL. This permits the |
df58fc94 RS |
3203 | linker to handle them specially, such as generating jalx instructions |
3204 | when needed. We also make them odd for the duration of the assembly, | |
3205 | in order to generate the right sort of code. We will make them even | |
252b5132 RH |
3206 | in the adjust_symtab routine, while leaving them marked. This is |
3207 | convenient for the debugger and the disassembler. The linker knows | |
3208 | to make them odd again. */ | |
3209 | ||
3210 | static void | |
e1b47bd5 | 3211 | mips_compressed_mark_label (symbolS *label) |
252b5132 | 3212 | { |
df58fc94 | 3213 | gas_assert (HAVE_CODE_COMPRESSION); |
a8dbcb85 | 3214 | |
f3ded42a RS |
3215 | if (mips_opts.mips16) |
3216 | S_SET_OTHER (label, ELF_ST_SET_MIPS16 (S_GET_OTHER (label))); | |
3217 | else | |
3218 | S_SET_OTHER (label, ELF_ST_SET_MICROMIPS (S_GET_OTHER (label))); | |
e1b47bd5 RS |
3219 | if ((S_GET_VALUE (label) & 1) == 0 |
3220 | /* Don't adjust the address if the label is global or weak, or | |
3221 | in a link-once section, since we'll be emitting symbol reloc | |
3222 | references to it which will be patched up by the linker, and | |
3223 | the final value of the symbol may or may not be MIPS16/microMIPS. */ | |
3224 | && !S_IS_WEAK (label) | |
3225 | && !S_IS_EXTERNAL (label) | |
3226 | && !s_is_linkonce (label, now_seg)) | |
3227 | S_SET_VALUE (label, S_GET_VALUE (label) | 1); | |
3228 | } | |
3229 | ||
3230 | /* Mark preceding MIPS16 or microMIPS instruction labels. */ | |
3231 | ||
3232 | static void | |
3233 | mips_compressed_mark_labels (void) | |
3234 | { | |
3235 | struct insn_label_list *l; | |
3236 | ||
3237 | for (l = seg_info (now_seg)->label_list; l != NULL; l = l->next) | |
3238 | mips_compressed_mark_label (l->label); | |
252b5132 RH |
3239 | } |
3240 | ||
4d7206a2 RS |
3241 | /* End the current frag. Make it a variant frag and record the |
3242 | relaxation info. */ | |
3243 | ||
3244 | static void | |
3245 | relax_close_frag (void) | |
3246 | { | |
584892a6 | 3247 | mips_macro_warning.first_frag = frag_now; |
4d7206a2 | 3248 | frag_var (rs_machine_dependent, 0, 0, |
584892a6 | 3249 | RELAX_ENCODE (mips_relax.sizes[0], mips_relax.sizes[1]), |
4d7206a2 RS |
3250 | mips_relax.symbol, 0, (char *) mips_relax.first_fixup); |
3251 | ||
3252 | memset (&mips_relax.sizes, 0, sizeof (mips_relax.sizes)); | |
3253 | mips_relax.first_fixup = 0; | |
3254 | } | |
3255 | ||
3256 | /* Start a new relaxation sequence whose expansion depends on SYMBOL. | |
3257 | See the comment above RELAX_ENCODE for more details. */ | |
3258 | ||
3259 | static void | |
3260 | relax_start (symbolS *symbol) | |
3261 | { | |
9c2799c2 | 3262 | gas_assert (mips_relax.sequence == 0); |
4d7206a2 RS |
3263 | mips_relax.sequence = 1; |
3264 | mips_relax.symbol = symbol; | |
3265 | } | |
3266 | ||
3267 | /* Start generating the second version of a relaxable sequence. | |
3268 | See the comment above RELAX_ENCODE for more details. */ | |
252b5132 RH |
3269 | |
3270 | static void | |
4d7206a2 RS |
3271 | relax_switch (void) |
3272 | { | |
9c2799c2 | 3273 | gas_assert (mips_relax.sequence == 1); |
4d7206a2 RS |
3274 | mips_relax.sequence = 2; |
3275 | } | |
3276 | ||
3277 | /* End the current relaxable sequence. */ | |
3278 | ||
3279 | static void | |
3280 | relax_end (void) | |
3281 | { | |
9c2799c2 | 3282 | gas_assert (mips_relax.sequence == 2); |
4d7206a2 RS |
3283 | relax_close_frag (); |
3284 | mips_relax.sequence = 0; | |
3285 | } | |
3286 | ||
11625dd8 RS |
3287 | /* Return true if IP is a delayed branch or jump. */ |
3288 | ||
3289 | static inline bfd_boolean | |
3290 | delayed_branch_p (const struct mips_cl_insn *ip) | |
3291 | { | |
3292 | return (ip->insn_mo->pinfo & (INSN_UNCOND_BRANCH_DELAY | |
3293 | | INSN_COND_BRANCH_DELAY | |
3294 | | INSN_COND_BRANCH_LIKELY)) != 0; | |
3295 | } | |
3296 | ||
3297 | /* Return true if IP is a compact branch or jump. */ | |
3298 | ||
3299 | static inline bfd_boolean | |
3300 | compact_branch_p (const struct mips_cl_insn *ip) | |
3301 | { | |
3302 | if (mips_opts.mips16) | |
3303 | return (ip->insn_mo->pinfo & (MIPS16_INSN_UNCOND_BRANCH | |
3304 | | MIPS16_INSN_COND_BRANCH)) != 0; | |
3305 | else | |
3306 | return (ip->insn_mo->pinfo2 & (INSN2_UNCOND_BRANCH | |
3307 | | INSN2_COND_BRANCH)) != 0; | |
3308 | } | |
3309 | ||
3310 | /* Return true if IP is an unconditional branch or jump. */ | |
3311 | ||
3312 | static inline bfd_boolean | |
3313 | uncond_branch_p (const struct mips_cl_insn *ip) | |
3314 | { | |
3315 | return ((ip->insn_mo->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0 | |
3316 | || (mips_opts.mips16 | |
3317 | ? (ip->insn_mo->pinfo & MIPS16_INSN_UNCOND_BRANCH) != 0 | |
3318 | : (ip->insn_mo->pinfo2 & INSN2_UNCOND_BRANCH) != 0)); | |
3319 | } | |
3320 | ||
3321 | /* Return true if IP is a branch-likely instruction. */ | |
3322 | ||
3323 | static inline bfd_boolean | |
3324 | branch_likely_p (const struct mips_cl_insn *ip) | |
3325 | { | |
3326 | return (ip->insn_mo->pinfo & INSN_COND_BRANCH_LIKELY) != 0; | |
3327 | } | |
3328 | ||
14fe068b RS |
3329 | /* Return the type of nop that should be used to fill the delay slot |
3330 | of delayed branch IP. */ | |
3331 | ||
3332 | static struct mips_cl_insn * | |
3333 | get_delay_slot_nop (const struct mips_cl_insn *ip) | |
3334 | { | |
3335 | if (mips_opts.micromips | |
3336 | && (ip->insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) | |
3337 | return µmips_nop32_insn; | |
3338 | return NOP_INSN; | |
3339 | } | |
3340 | ||
2309ddf2 | 3341 | /* Return the mask of core registers that IP reads or writes. */ |
df58fc94 RS |
3342 | |
3343 | static unsigned int | |
3344 | gpr_mod_mask (const struct mips_cl_insn *ip) | |
3345 | { | |
2309ddf2 | 3346 | unsigned long pinfo2; |
df58fc94 RS |
3347 | unsigned int mask; |
3348 | ||
3349 | mask = 0; | |
df58fc94 RS |
3350 | pinfo2 = ip->insn_mo->pinfo2; |
3351 | if (mips_opts.micromips) | |
3352 | { | |
df58fc94 RS |
3353 | if (pinfo2 & INSN2_MOD_GPR_MD) |
3354 | mask |= 1 << micromips_to_32_reg_d_map[EXTRACT_OPERAND (1, MD, *ip)]; | |
df58fc94 RS |
3355 | if (pinfo2 & INSN2_MOD_GPR_MF) |
3356 | mask |= 1 << micromips_to_32_reg_f_map[EXTRACT_OPERAND (1, MF, *ip)]; | |
df58fc94 RS |
3357 | if (pinfo2 & INSN2_MOD_SP) |
3358 | mask |= 1 << SP; | |
3359 | } | |
3360 | return mask; | |
3361 | } | |
3362 | ||
4c260379 RS |
3363 | /* Return the mask of core registers that IP reads. */ |
3364 | ||
3365 | static unsigned int | |
3366 | gpr_read_mask (const struct mips_cl_insn *ip) | |
3367 | { | |
3368 | unsigned long pinfo, pinfo2; | |
3369 | unsigned int mask; | |
3370 | ||
df58fc94 | 3371 | mask = gpr_mod_mask (ip); |
4c260379 RS |
3372 | pinfo = ip->insn_mo->pinfo; |
3373 | pinfo2 = ip->insn_mo->pinfo2; | |
3374 | if (mips_opts.mips16) | |
3375 | { | |
3376 | if (pinfo & MIPS16_INSN_READ_X) | |
3377 | mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, *ip)]; | |
3378 | if (pinfo & MIPS16_INSN_READ_Y) | |
3379 | mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RY, *ip)]; | |
3380 | if (pinfo & MIPS16_INSN_READ_T) | |
3381 | mask |= 1 << TREG; | |
3382 | if (pinfo & MIPS16_INSN_READ_SP) | |
3383 | mask |= 1 << SP; | |
3384 | if (pinfo & MIPS16_INSN_READ_31) | |
3385 | mask |= 1 << RA; | |
3386 | if (pinfo & MIPS16_INSN_READ_Z) | |
3387 | mask |= 1 << (mips16_to_32_reg_map | |
3388 | [MIPS16_EXTRACT_OPERAND (MOVE32Z, *ip)]); | |
3389 | if (pinfo & MIPS16_INSN_READ_GPR_X) | |
3390 | mask |= 1 << MIPS16_EXTRACT_OPERAND (REGR32, *ip); | |
3391 | } | |
3392 | else | |
3393 | { | |
3394 | if (pinfo2 & INSN2_READ_GPR_D) | |
2309ddf2 | 3395 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RD, *ip); |
4c260379 | 3396 | if (pinfo & INSN_READ_GPR_T) |
2309ddf2 | 3397 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RT, *ip); |
4c260379 | 3398 | if (pinfo & INSN_READ_GPR_S) |
2309ddf2 MR |
3399 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RS, *ip); |
3400 | if (pinfo2 & INSN2_READ_GP) | |
3401 | mask |= 1 << GP; | |
3402 | if (pinfo2 & INSN2_READ_GPR_31) | |
3403 | mask |= 1 << RA; | |
4c260379 | 3404 | if (pinfo2 & INSN2_READ_GPR_Z) |
2309ddf2 | 3405 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RZ, *ip); |
4c260379 | 3406 | } |
2b0c8b40 MR |
3407 | if (mips_opts.micromips) |
3408 | { | |
3409 | if (pinfo2 & INSN2_READ_GPR_MC) | |
3410 | mask |= 1 << micromips_to_32_reg_c_map[EXTRACT_OPERAND (1, MC, *ip)]; | |
3411 | if (pinfo2 & INSN2_READ_GPR_ME) | |
3412 | mask |= 1 << micromips_to_32_reg_e_map[EXTRACT_OPERAND (1, ME, *ip)]; | |
3413 | if (pinfo2 & INSN2_READ_GPR_MG) | |
3414 | mask |= 1 << micromips_to_32_reg_g_map[EXTRACT_OPERAND (1, MG, *ip)]; | |
3415 | if (pinfo2 & INSN2_READ_GPR_MJ) | |
3416 | mask |= 1 << EXTRACT_OPERAND (1, MJ, *ip); | |
3417 | if (pinfo2 & INSN2_READ_GPR_MMN) | |
3418 | { | |
3419 | mask |= 1 << micromips_to_32_reg_m_map[EXTRACT_OPERAND (1, MM, *ip)]; | |
3420 | mask |= 1 << micromips_to_32_reg_n_map[EXTRACT_OPERAND (1, MN, *ip)]; | |
3421 | } | |
3422 | if (pinfo2 & INSN2_READ_GPR_MP) | |
3423 | mask |= 1 << EXTRACT_OPERAND (1, MP, *ip); | |
3424 | if (pinfo2 & INSN2_READ_GPR_MQ) | |
3425 | mask |= 1 << micromips_to_32_reg_q_map[EXTRACT_OPERAND (1, MQ, *ip)]; | |
3426 | } | |
fe35f09f RS |
3427 | /* Don't include register 0. */ |
3428 | return mask & ~1; | |
4c260379 RS |
3429 | } |
3430 | ||
3431 | /* Return the mask of core registers that IP writes. */ | |
3432 | ||
3433 | static unsigned int | |
3434 | gpr_write_mask (const struct mips_cl_insn *ip) | |
3435 | { | |
3436 | unsigned long pinfo, pinfo2; | |
3437 | unsigned int mask; | |
3438 | ||
df58fc94 | 3439 | mask = gpr_mod_mask (ip); |
4c260379 RS |
3440 | pinfo = ip->insn_mo->pinfo; |
3441 | pinfo2 = ip->insn_mo->pinfo2; | |
3442 | if (mips_opts.mips16) | |
3443 | { | |
3444 | if (pinfo & MIPS16_INSN_WRITE_X) | |
3445 | mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, *ip)]; | |
3446 | if (pinfo & MIPS16_INSN_WRITE_Y) | |
3447 | mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RY, *ip)]; | |
3448 | if (pinfo & MIPS16_INSN_WRITE_Z) | |
3449 | mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RZ, *ip)]; | |
3450 | if (pinfo & MIPS16_INSN_WRITE_T) | |
3451 | mask |= 1 << TREG; | |
3452 | if (pinfo & MIPS16_INSN_WRITE_SP) | |
3453 | mask |= 1 << SP; | |
3454 | if (pinfo & MIPS16_INSN_WRITE_31) | |
3455 | mask |= 1 << RA; | |
3456 | if (pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
3457 | mask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode); | |
3458 | } | |
3459 | else | |
3460 | { | |
3461 | if (pinfo & INSN_WRITE_GPR_D) | |
df58fc94 | 3462 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RD, *ip); |
4c260379 | 3463 | if (pinfo & INSN_WRITE_GPR_T) |
df58fc94 | 3464 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RT, *ip); |
2b0c8b40 | 3465 | if (pinfo & INSN_WRITE_GPR_S) |
2309ddf2 | 3466 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RS, *ip); |
4c260379 RS |
3467 | if (pinfo & INSN_WRITE_GPR_31) |
3468 | mask |= 1 << RA; | |
3469 | if (pinfo2 & INSN2_WRITE_GPR_Z) | |
df58fc94 | 3470 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RZ, *ip); |
4c260379 | 3471 | } |
2b0c8b40 MR |
3472 | if (mips_opts.micromips) |
3473 | { | |
3474 | if (pinfo2 & INSN2_WRITE_GPR_MB) | |
3475 | mask |= 1 << micromips_to_32_reg_b_map[EXTRACT_OPERAND (1, MB, *ip)]; | |
3476 | if (pinfo2 & INSN2_WRITE_GPR_MHI) | |
3477 | { | |
3478 | mask |= 1 << micromips_to_32_reg_h_map[EXTRACT_OPERAND (1, MH, *ip)]; | |
3479 | mask |= 1 << micromips_to_32_reg_i_map[EXTRACT_OPERAND (1, MI, *ip)]; | |
3480 | } | |
3481 | if (pinfo2 & INSN2_WRITE_GPR_MJ) | |
3482 | mask |= 1 << EXTRACT_OPERAND (1, MJ, *ip); | |
3483 | if (pinfo2 & INSN2_WRITE_GPR_MP) | |
3484 | mask |= 1 << EXTRACT_OPERAND (1, MP, *ip); | |
3485 | } | |
fe35f09f RS |
3486 | /* Don't include register 0. */ |
3487 | return mask & ~1; | |
4c260379 RS |
3488 | } |
3489 | ||
3490 | /* Return the mask of floating-point registers that IP reads. */ | |
3491 | ||
3492 | static unsigned int | |
3493 | fpr_read_mask (const struct mips_cl_insn *ip) | |
3494 | { | |
3495 | unsigned long pinfo, pinfo2; | |
3496 | unsigned int mask; | |
3497 | ||
3498 | mask = 0; | |
3499 | pinfo = ip->insn_mo->pinfo; | |
3500 | pinfo2 = ip->insn_mo->pinfo2; | |
2309ddf2 | 3501 | if (!mips_opts.mips16) |
df58fc94 RS |
3502 | { |
3503 | if (pinfo2 & INSN2_READ_FPR_D) | |
2309ddf2 | 3504 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FD, *ip); |
4c260379 | 3505 | if (pinfo & INSN_READ_FPR_S) |
df58fc94 | 3506 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FS, *ip); |
4c260379 | 3507 | if (pinfo & INSN_READ_FPR_T) |
df58fc94 | 3508 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FT, *ip); |
4c260379 | 3509 | if (pinfo & INSN_READ_FPR_R) |
df58fc94 | 3510 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FR, *ip); |
4c260379 | 3511 | if (pinfo2 & INSN2_READ_FPR_Z) |
df58fc94 | 3512 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FZ, *ip); |
4c260379 RS |
3513 | } |
3514 | /* Conservatively treat all operands to an FP_D instruction are doubles. | |
3515 | (This is overly pessimistic for things like cvt.d.s.) */ | |
3516 | if (HAVE_32BIT_FPRS && (pinfo & FP_D)) | |
3517 | mask |= mask << 1; | |
3518 | return mask; | |
3519 | } | |
3520 | ||
3521 | /* Return the mask of floating-point registers that IP writes. */ | |
3522 | ||
3523 | static unsigned int | |
3524 | fpr_write_mask (const struct mips_cl_insn *ip) | |
3525 | { | |
3526 | unsigned long pinfo, pinfo2; | |
3527 | unsigned int mask; | |
3528 | ||
3529 | mask = 0; | |
3530 | pinfo = ip->insn_mo->pinfo; | |
3531 | pinfo2 = ip->insn_mo->pinfo2; | |
2309ddf2 | 3532 | if (!mips_opts.mips16) |
4c260379 RS |
3533 | { |
3534 | if (pinfo & INSN_WRITE_FPR_D) | |
df58fc94 | 3535 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FD, *ip); |
4c260379 | 3536 | if (pinfo & INSN_WRITE_FPR_S) |
df58fc94 | 3537 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FS, *ip); |
4c260379 | 3538 | if (pinfo & INSN_WRITE_FPR_T) |
df58fc94 | 3539 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FT, *ip); |
4c260379 | 3540 | if (pinfo2 & INSN2_WRITE_FPR_Z) |
df58fc94 | 3541 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FZ, *ip); |
4c260379 RS |
3542 | } |
3543 | /* Conservatively treat all operands to an FP_D instruction are doubles. | |
3544 | (This is overly pessimistic for things like cvt.s.d.) */ | |
3545 | if (HAVE_32BIT_FPRS && (pinfo & FP_D)) | |
3546 | mask |= mask << 1; | |
3547 | return mask; | |
3548 | } | |
3549 | ||
71400594 RS |
3550 | /* Classify an instruction according to the FIX_VR4120_* enumeration. |
3551 | Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected | |
3552 | by VR4120 errata. */ | |
4d7206a2 | 3553 | |
71400594 RS |
3554 | static unsigned int |
3555 | classify_vr4120_insn (const char *name) | |
252b5132 | 3556 | { |
71400594 RS |
3557 | if (strncmp (name, "macc", 4) == 0) |
3558 | return FIX_VR4120_MACC; | |
3559 | if (strncmp (name, "dmacc", 5) == 0) | |
3560 | return FIX_VR4120_DMACC; | |
3561 | if (strncmp (name, "mult", 4) == 0) | |
3562 | return FIX_VR4120_MULT; | |
3563 | if (strncmp (name, "dmult", 5) == 0) | |
3564 | return FIX_VR4120_DMULT; | |
3565 | if (strstr (name, "div")) | |
3566 | return FIX_VR4120_DIV; | |
3567 | if (strcmp (name, "mtlo") == 0 || strcmp (name, "mthi") == 0) | |
3568 | return FIX_VR4120_MTHILO; | |
3569 | return NUM_FIX_VR4120_CLASSES; | |
3570 | } | |
252b5132 | 3571 | |
ff239038 CM |
3572 | #define INSN_ERET 0x42000018 |
3573 | #define INSN_DERET 0x4200001f | |
3574 | ||
71400594 RS |
3575 | /* Return the number of instructions that must separate INSN1 and INSN2, |
3576 | where INSN1 is the earlier instruction. Return the worst-case value | |
3577 | for any INSN2 if INSN2 is null. */ | |
252b5132 | 3578 | |
71400594 RS |
3579 | static unsigned int |
3580 | insns_between (const struct mips_cl_insn *insn1, | |
3581 | const struct mips_cl_insn *insn2) | |
3582 | { | |
3583 | unsigned long pinfo1, pinfo2; | |
4c260379 | 3584 | unsigned int mask; |
71400594 RS |
3585 | |
3586 | /* This function needs to know which pinfo flags are set for INSN2 | |
3587 | and which registers INSN2 uses. The former is stored in PINFO2 and | |
4c260379 RS |
3588 | the latter is tested via INSN2_USES_GPR. If INSN2 is null, PINFO2 |
3589 | will have every flag set and INSN2_USES_GPR will always return true. */ | |
71400594 RS |
3590 | pinfo1 = insn1->insn_mo->pinfo; |
3591 | pinfo2 = insn2 ? insn2->insn_mo->pinfo : ~0U; | |
252b5132 | 3592 | |
4c260379 RS |
3593 | #define INSN2_USES_GPR(REG) \ |
3594 | (insn2 == NULL || (gpr_read_mask (insn2) & (1U << (REG))) != 0) | |
71400594 RS |
3595 | |
3596 | /* For most targets, write-after-read dependencies on the HI and LO | |
3597 | registers must be separated by at least two instructions. */ | |
3598 | if (!hilo_interlocks) | |
252b5132 | 3599 | { |
71400594 RS |
3600 | if ((pinfo1 & INSN_READ_LO) && (pinfo2 & INSN_WRITE_LO)) |
3601 | return 2; | |
3602 | if ((pinfo1 & INSN_READ_HI) && (pinfo2 & INSN_WRITE_HI)) | |
3603 | return 2; | |
3604 | } | |
3605 | ||
3606 | /* If we're working around r7000 errata, there must be two instructions | |
3607 | between an mfhi or mflo and any instruction that uses the result. */ | |
3608 | if (mips_7000_hilo_fix | |
df58fc94 | 3609 | && !mips_opts.micromips |
71400594 | 3610 | && MF_HILO_INSN (pinfo1) |
df58fc94 | 3611 | && INSN2_USES_GPR (EXTRACT_OPERAND (0, RD, *insn1))) |
71400594 RS |
3612 | return 2; |
3613 | ||
ff239038 CM |
3614 | /* If we're working around 24K errata, one instruction is required |
3615 | if an ERET or DERET is followed by a branch instruction. */ | |
df58fc94 | 3616 | if (mips_fix_24k && !mips_opts.micromips) |
ff239038 CM |
3617 | { |
3618 | if (insn1->insn_opcode == INSN_ERET | |
3619 | || insn1->insn_opcode == INSN_DERET) | |
3620 | { | |
3621 | if (insn2 == NULL | |
3622 | || insn2->insn_opcode == INSN_ERET | |
3623 | || insn2->insn_opcode == INSN_DERET | |
11625dd8 | 3624 | || delayed_branch_p (insn2)) |
ff239038 CM |
3625 | return 1; |
3626 | } | |
3627 | } | |
3628 | ||
71400594 RS |
3629 | /* If working around VR4120 errata, check for combinations that need |
3630 | a single intervening instruction. */ | |
df58fc94 | 3631 | if (mips_fix_vr4120 && !mips_opts.micromips) |
71400594 RS |
3632 | { |
3633 | unsigned int class1, class2; | |
252b5132 | 3634 | |
71400594 RS |
3635 | class1 = classify_vr4120_insn (insn1->insn_mo->name); |
3636 | if (class1 != NUM_FIX_VR4120_CLASSES && vr4120_conflicts[class1] != 0) | |
252b5132 | 3637 | { |
71400594 RS |
3638 | if (insn2 == NULL) |
3639 | return 1; | |
3640 | class2 = classify_vr4120_insn (insn2->insn_mo->name); | |
3641 | if (vr4120_conflicts[class1] & (1 << class2)) | |
3642 | return 1; | |
252b5132 | 3643 | } |
71400594 RS |
3644 | } |
3645 | ||
df58fc94 | 3646 | if (!HAVE_CODE_COMPRESSION) |
71400594 RS |
3647 | { |
3648 | /* Check for GPR or coprocessor load delays. All such delays | |
3649 | are on the RT register. */ | |
3650 | /* Itbl support may require additional care here. */ | |
3651 | if ((!gpr_interlocks && (pinfo1 & INSN_LOAD_MEMORY_DELAY)) | |
3652 | || (!cop_interlocks && (pinfo1 & INSN_LOAD_COPROC_DELAY))) | |
252b5132 | 3653 | { |
71400594 | 3654 | know (pinfo1 & INSN_WRITE_GPR_T); |
df58fc94 | 3655 | if (INSN2_USES_GPR (EXTRACT_OPERAND (0, RT, *insn1))) |
71400594 RS |
3656 | return 1; |
3657 | } | |
3658 | ||
3659 | /* Check for generic coprocessor hazards. | |
3660 | ||
3661 | This case is not handled very well. There is no special | |
3662 | knowledge of CP0 handling, and the coprocessors other than | |
3663 | the floating point unit are not distinguished at all. */ | |
3664 | /* Itbl support may require additional care here. FIXME! | |
3665 | Need to modify this to include knowledge about | |
3666 | user specified delays! */ | |
3667 | else if ((!cop_interlocks && (pinfo1 & INSN_COPROC_MOVE_DELAY)) | |
3668 | || (!cop_mem_interlocks && (pinfo1 & INSN_COPROC_MEMORY_DELAY))) | |
3669 | { | |
3670 | /* Handle cases where INSN1 writes to a known general coprocessor | |
3671 | register. There must be a one instruction delay before INSN2 | |
3672 | if INSN2 reads that register, otherwise no delay is needed. */ | |
4c260379 RS |
3673 | mask = fpr_write_mask (insn1); |
3674 | if (mask != 0) | |
252b5132 | 3675 | { |
4c260379 | 3676 | if (!insn2 || (mask & fpr_read_mask (insn2)) != 0) |
71400594 | 3677 | return 1; |
252b5132 RH |
3678 | } |
3679 | else | |
3680 | { | |
71400594 RS |
3681 | /* Read-after-write dependencies on the control registers |
3682 | require a two-instruction gap. */ | |
3683 | if ((pinfo1 & INSN_WRITE_COND_CODE) | |
3684 | && (pinfo2 & INSN_READ_COND_CODE)) | |
3685 | return 2; | |
3686 | ||
3687 | /* We don't know exactly what INSN1 does. If INSN2 is | |
3688 | also a coprocessor instruction, assume there must be | |
3689 | a one instruction gap. */ | |
3690 | if (pinfo2 & INSN_COP) | |
3691 | return 1; | |
252b5132 RH |
3692 | } |
3693 | } | |
6b76fefe | 3694 | |
71400594 RS |
3695 | /* Check for read-after-write dependencies on the coprocessor |
3696 | control registers in cases where INSN1 does not need a general | |
3697 | coprocessor delay. This means that INSN1 is a floating point | |
3698 | comparison instruction. */ | |
3699 | /* Itbl support may require additional care here. */ | |
3700 | else if (!cop_interlocks | |
3701 | && (pinfo1 & INSN_WRITE_COND_CODE) | |
3702 | && (pinfo2 & INSN_READ_COND_CODE)) | |
3703 | return 1; | |
3704 | } | |
6b76fefe | 3705 | |
4c260379 | 3706 | #undef INSN2_USES_GPR |
6b76fefe | 3707 | |
71400594 RS |
3708 | return 0; |
3709 | } | |
6b76fefe | 3710 | |
7d8e00cf RS |
3711 | /* Return the number of nops that would be needed to work around the |
3712 | VR4130 mflo/mfhi errata if instruction INSN immediately followed | |
932d1a1b RS |
3713 | the MAX_VR4130_NOPS instructions described by HIST. Ignore hazards |
3714 | that are contained within the first IGNORE instructions of HIST. */ | |
7d8e00cf RS |
3715 | |
3716 | static int | |
932d1a1b | 3717 | nops_for_vr4130 (int ignore, const struct mips_cl_insn *hist, |
7d8e00cf RS |
3718 | const struct mips_cl_insn *insn) |
3719 | { | |
4c260379 RS |
3720 | int i, j; |
3721 | unsigned int mask; | |
7d8e00cf RS |
3722 | |
3723 | /* Check if the instruction writes to HI or LO. MTHI and MTLO | |
3724 | are not affected by the errata. */ | |
3725 | if (insn != 0 | |
3726 | && ((insn->insn_mo->pinfo & (INSN_WRITE_HI | INSN_WRITE_LO)) == 0 | |
3727 | || strcmp (insn->insn_mo->name, "mtlo") == 0 | |
3728 | || strcmp (insn->insn_mo->name, "mthi") == 0)) | |
3729 | return 0; | |
3730 | ||
3731 | /* Search for the first MFLO or MFHI. */ | |
3732 | for (i = 0; i < MAX_VR4130_NOPS; i++) | |
91d6fa6a | 3733 | if (MF_HILO_INSN (hist[i].insn_mo->pinfo)) |
7d8e00cf RS |
3734 | { |
3735 | /* Extract the destination register. */ | |
4c260379 | 3736 | mask = gpr_write_mask (&hist[i]); |
7d8e00cf RS |
3737 | |
3738 | /* No nops are needed if INSN reads that register. */ | |
4c260379 | 3739 | if (insn != NULL && (gpr_read_mask (insn) & mask) != 0) |
7d8e00cf RS |
3740 | return 0; |
3741 | ||
3742 | /* ...or if any of the intervening instructions do. */ | |
3743 | for (j = 0; j < i; j++) | |
4c260379 | 3744 | if (gpr_read_mask (&hist[j]) & mask) |
7d8e00cf RS |
3745 | return 0; |
3746 | ||
932d1a1b RS |
3747 | if (i >= ignore) |
3748 | return MAX_VR4130_NOPS - i; | |
7d8e00cf RS |
3749 | } |
3750 | return 0; | |
3751 | } | |
3752 | ||
15be625d CM |
3753 | #define BASE_REG_EQ(INSN1, INSN2) \ |
3754 | ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \ | |
3755 | == (((INSN2) >> OP_SH_RS) & OP_MASK_RS)) | |
3756 | ||
3757 | /* Return the minimum alignment for this store instruction. */ | |
3758 | ||
3759 | static int | |
3760 | fix_24k_align_to (const struct mips_opcode *mo) | |
3761 | { | |
3762 | if (strcmp (mo->name, "sh") == 0) | |
3763 | return 2; | |
3764 | ||
3765 | if (strcmp (mo->name, "swc1") == 0 | |
3766 | || strcmp (mo->name, "swc2") == 0 | |
3767 | || strcmp (mo->name, "sw") == 0 | |
3768 | || strcmp (mo->name, "sc") == 0 | |
3769 | || strcmp (mo->name, "s.s") == 0) | |
3770 | return 4; | |
3771 | ||
3772 | if (strcmp (mo->name, "sdc1") == 0 | |
3773 | || strcmp (mo->name, "sdc2") == 0 | |
3774 | || strcmp (mo->name, "s.d") == 0) | |
3775 | return 8; | |
3776 | ||
3777 | /* sb, swl, swr */ | |
3778 | return 1; | |
3779 | } | |
3780 | ||
3781 | struct fix_24k_store_info | |
3782 | { | |
3783 | /* Immediate offset, if any, for this store instruction. */ | |
3784 | short off; | |
3785 | /* Alignment required by this store instruction. */ | |
3786 | int align_to; | |
3787 | /* True for register offsets. */ | |
3788 | int register_offset; | |
3789 | }; | |
3790 | ||
3791 | /* Comparison function used by qsort. */ | |
3792 | ||
3793 | static int | |
3794 | fix_24k_sort (const void *a, const void *b) | |
3795 | { | |
3796 | const struct fix_24k_store_info *pos1 = a; | |
3797 | const struct fix_24k_store_info *pos2 = b; | |
3798 | ||
3799 | return (pos1->off - pos2->off); | |
3800 | } | |
3801 | ||
3802 | /* INSN is a store instruction. Try to record the store information | |
3803 | in STINFO. Return false if the information isn't known. */ | |
3804 | ||
3805 | static bfd_boolean | |
3806 | fix_24k_record_store_info (struct fix_24k_store_info *stinfo, | |
ab9794cf | 3807 | const struct mips_cl_insn *insn) |
15be625d CM |
3808 | { |
3809 | /* The instruction must have a known offset. */ | |
3810 | if (!insn->complete_p || !strstr (insn->insn_mo->args, "o(")) | |
3811 | return FALSE; | |
3812 | ||
3813 | stinfo->off = (insn->insn_opcode >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE; | |
3814 | stinfo->align_to = fix_24k_align_to (insn->insn_mo); | |
3815 | return TRUE; | |
3816 | } | |
3817 | ||
932d1a1b RS |
3818 | /* Return the number of nops that would be needed to work around the 24k |
3819 | "lost data on stores during refill" errata if instruction INSN | |
3820 | immediately followed the 2 instructions described by HIST. | |
3821 | Ignore hazards that are contained within the first IGNORE | |
3822 | instructions of HIST. | |
3823 | ||
3824 | Problem: The FSB (fetch store buffer) acts as an intermediate buffer | |
3825 | for the data cache refills and store data. The following describes | |
3826 | the scenario where the store data could be lost. | |
3827 | ||
3828 | * A data cache miss, due to either a load or a store, causing fill | |
3829 | data to be supplied by the memory subsystem | |
3830 | * The first three doublewords of fill data are returned and written | |
3831 | into the cache | |
3832 | * A sequence of four stores occurs in consecutive cycles around the | |
3833 | final doubleword of the fill: | |
3834 | * Store A | |
3835 | * Store B | |
3836 | * Store C | |
3837 | * Zero, One or more instructions | |
3838 | * Store D | |
3839 | ||
3840 | The four stores A-D must be to different doublewords of the line that | |
3841 | is being filled. The fourth instruction in the sequence above permits | |
3842 | the fill of the final doubleword to be transferred from the FSB into | |
3843 | the cache. In the sequence above, the stores may be either integer | |
3844 | (sb, sh, sw, swr, swl, sc) or coprocessor (swc1/swc2, sdc1/sdc2, | |
3845 | swxc1, sdxc1, suxc1) stores, as long as the four stores are to | |
3846 | different doublewords on the line. If the floating point unit is | |
3847 | running in 1:2 mode, it is not possible to create the sequence above | |
3848 | using only floating point store instructions. | |
15be625d CM |
3849 | |
3850 | In this case, the cache line being filled is incorrectly marked | |
3851 | invalid, thereby losing the data from any store to the line that | |
3852 | occurs between the original miss and the completion of the five | |
3853 | cycle sequence shown above. | |
3854 | ||
932d1a1b | 3855 | The workarounds are: |
15be625d | 3856 | |
932d1a1b RS |
3857 | * Run the data cache in write-through mode. |
3858 | * Insert a non-store instruction between | |
3859 | Store A and Store B or Store B and Store C. */ | |
15be625d CM |
3860 | |
3861 | static int | |
932d1a1b | 3862 | nops_for_24k (int ignore, const struct mips_cl_insn *hist, |
15be625d CM |
3863 | const struct mips_cl_insn *insn) |
3864 | { | |
3865 | struct fix_24k_store_info pos[3]; | |
3866 | int align, i, base_offset; | |
3867 | ||
932d1a1b RS |
3868 | if (ignore >= 2) |
3869 | return 0; | |
3870 | ||
ab9794cf RS |
3871 | /* If the previous instruction wasn't a store, there's nothing to |
3872 | worry about. */ | |
15be625d CM |
3873 | if ((hist[0].insn_mo->pinfo & INSN_STORE_MEMORY) == 0) |
3874 | return 0; | |
3875 | ||
ab9794cf RS |
3876 | /* If the instructions after the previous one are unknown, we have |
3877 | to assume the worst. */ | |
3878 | if (!insn) | |
15be625d CM |
3879 | return 1; |
3880 | ||
ab9794cf RS |
3881 | /* Check whether we are dealing with three consecutive stores. */ |
3882 | if ((insn->insn_mo->pinfo & INSN_STORE_MEMORY) == 0 | |
3883 | || (hist[1].insn_mo->pinfo & INSN_STORE_MEMORY) == 0) | |
15be625d CM |
3884 | return 0; |
3885 | ||
3886 | /* If we don't know the relationship between the store addresses, | |
3887 | assume the worst. */ | |
ab9794cf | 3888 | if (!BASE_REG_EQ (insn->insn_opcode, hist[0].insn_opcode) |
15be625d CM |
3889 | || !BASE_REG_EQ (insn->insn_opcode, hist[1].insn_opcode)) |
3890 | return 1; | |
3891 | ||
3892 | if (!fix_24k_record_store_info (&pos[0], insn) | |
3893 | || !fix_24k_record_store_info (&pos[1], &hist[0]) | |
3894 | || !fix_24k_record_store_info (&pos[2], &hist[1])) | |
3895 | return 1; | |
3896 | ||
3897 | qsort (&pos, 3, sizeof (struct fix_24k_store_info), fix_24k_sort); | |
3898 | ||
3899 | /* Pick a value of ALIGN and X such that all offsets are adjusted by | |
3900 | X bytes and such that the base register + X is known to be aligned | |
3901 | to align bytes. */ | |
3902 | ||
3903 | if (((insn->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == SP) | |
3904 | align = 8; | |
3905 | else | |
3906 | { | |
3907 | align = pos[0].align_to; | |
3908 | base_offset = pos[0].off; | |
3909 | for (i = 1; i < 3; i++) | |
3910 | if (align < pos[i].align_to) | |
3911 | { | |
3912 | align = pos[i].align_to; | |
3913 | base_offset = pos[i].off; | |
3914 | } | |
3915 | for (i = 0; i < 3; i++) | |
3916 | pos[i].off -= base_offset; | |
3917 | } | |
3918 | ||
3919 | pos[0].off &= ~align + 1; | |
3920 | pos[1].off &= ~align + 1; | |
3921 | pos[2].off &= ~align + 1; | |
3922 | ||
3923 | /* If any two stores write to the same chunk, they also write to the | |
3924 | same doubleword. The offsets are still sorted at this point. */ | |
3925 | if (pos[0].off == pos[1].off || pos[1].off == pos[2].off) | |
3926 | return 0; | |
3927 | ||
3928 | /* A range of at least 9 bytes is needed for the stores to be in | |
3929 | non-overlapping doublewords. */ | |
3930 | if (pos[2].off - pos[0].off <= 8) | |
3931 | return 0; | |
3932 | ||
3933 | if (pos[2].off - pos[1].off >= 24 | |
3934 | || pos[1].off - pos[0].off >= 24 | |
3935 | || pos[2].off - pos[0].off >= 32) | |
3936 | return 0; | |
3937 | ||
3938 | return 1; | |
3939 | } | |
3940 | ||
71400594 | 3941 | /* Return the number of nops that would be needed if instruction INSN |
91d6fa6a | 3942 | immediately followed the MAX_NOPS instructions given by HIST, |
932d1a1b RS |
3943 | where HIST[0] is the most recent instruction. Ignore hazards |
3944 | between INSN and the first IGNORE instructions in HIST. | |
3945 | ||
3946 | If INSN is null, return the worse-case number of nops for any | |
3947 | instruction. */ | |
bdaaa2e1 | 3948 | |
71400594 | 3949 | static int |
932d1a1b | 3950 | nops_for_insn (int ignore, const struct mips_cl_insn *hist, |
71400594 RS |
3951 | const struct mips_cl_insn *insn) |
3952 | { | |
3953 | int i, nops, tmp_nops; | |
bdaaa2e1 | 3954 | |
71400594 | 3955 | nops = 0; |
932d1a1b | 3956 | for (i = ignore; i < MAX_DELAY_NOPS; i++) |
65b02341 | 3957 | { |
91d6fa6a | 3958 | tmp_nops = insns_between (hist + i, insn) - i; |
65b02341 RS |
3959 | if (tmp_nops > nops) |
3960 | nops = tmp_nops; | |
3961 | } | |
7d8e00cf | 3962 | |
df58fc94 | 3963 | if (mips_fix_vr4130 && !mips_opts.micromips) |
7d8e00cf | 3964 | { |
932d1a1b | 3965 | tmp_nops = nops_for_vr4130 (ignore, hist, insn); |
7d8e00cf RS |
3966 | if (tmp_nops > nops) |
3967 | nops = tmp_nops; | |
3968 | } | |
3969 | ||
df58fc94 | 3970 | if (mips_fix_24k && !mips_opts.micromips) |
15be625d | 3971 | { |
932d1a1b | 3972 | tmp_nops = nops_for_24k (ignore, hist, insn); |
15be625d CM |
3973 | if (tmp_nops > nops) |
3974 | nops = tmp_nops; | |
3975 | } | |
3976 | ||
71400594 RS |
3977 | return nops; |
3978 | } | |
252b5132 | 3979 | |
71400594 | 3980 | /* The variable arguments provide NUM_INSNS extra instructions that |
91d6fa6a | 3981 | might be added to HIST. Return the largest number of nops that |
932d1a1b RS |
3982 | would be needed after the extended sequence, ignoring hazards |
3983 | in the first IGNORE instructions. */ | |
252b5132 | 3984 | |
71400594 | 3985 | static int |
932d1a1b RS |
3986 | nops_for_sequence (int num_insns, int ignore, |
3987 | const struct mips_cl_insn *hist, ...) | |
71400594 RS |
3988 | { |
3989 | va_list args; | |
3990 | struct mips_cl_insn buffer[MAX_NOPS]; | |
3991 | struct mips_cl_insn *cursor; | |
3992 | int nops; | |
3993 | ||
91d6fa6a | 3994 | va_start (args, hist); |
71400594 | 3995 | cursor = buffer + num_insns; |
91d6fa6a | 3996 | memcpy (cursor, hist, (MAX_NOPS - num_insns) * sizeof (*cursor)); |
71400594 RS |
3997 | while (cursor > buffer) |
3998 | *--cursor = *va_arg (args, const struct mips_cl_insn *); | |
3999 | ||
932d1a1b | 4000 | nops = nops_for_insn (ignore, buffer, NULL); |
71400594 RS |
4001 | va_end (args); |
4002 | return nops; | |
4003 | } | |
252b5132 | 4004 | |
71400594 RS |
4005 | /* Like nops_for_insn, but if INSN is a branch, take into account the |
4006 | worst-case delay for the branch target. */ | |
252b5132 | 4007 | |
71400594 | 4008 | static int |
932d1a1b | 4009 | nops_for_insn_or_target (int ignore, const struct mips_cl_insn *hist, |
71400594 RS |
4010 | const struct mips_cl_insn *insn) |
4011 | { | |
4012 | int nops, tmp_nops; | |
60b63b72 | 4013 | |
932d1a1b | 4014 | nops = nops_for_insn (ignore, hist, insn); |
11625dd8 | 4015 | if (delayed_branch_p (insn)) |
71400594 | 4016 | { |
932d1a1b | 4017 | tmp_nops = nops_for_sequence (2, ignore ? ignore + 2 : 0, |
14fe068b | 4018 | hist, insn, get_delay_slot_nop (insn)); |
71400594 RS |
4019 | if (tmp_nops > nops) |
4020 | nops = tmp_nops; | |
4021 | } | |
11625dd8 | 4022 | else if (compact_branch_p (insn)) |
71400594 | 4023 | { |
932d1a1b | 4024 | tmp_nops = nops_for_sequence (1, ignore ? ignore + 1 : 0, hist, insn); |
71400594 RS |
4025 | if (tmp_nops > nops) |
4026 | nops = tmp_nops; | |
4027 | } | |
4028 | return nops; | |
4029 | } | |
4030 | ||
c67a084a NC |
4031 | /* Fix NOP issue: Replace nops by "or at,at,zero". */ |
4032 | ||
4033 | static void | |
4034 | fix_loongson2f_nop (struct mips_cl_insn * ip) | |
4035 | { | |
df58fc94 | 4036 | gas_assert (!HAVE_CODE_COMPRESSION); |
c67a084a NC |
4037 | if (strcmp (ip->insn_mo->name, "nop") == 0) |
4038 | ip->insn_opcode = LOONGSON2F_NOP_INSN; | |
4039 | } | |
4040 | ||
4041 | /* Fix Jump Issue: Eliminate instruction fetch from outside 256M region | |
4042 | jr target pc &= 'hffff_ffff_cfff_ffff. */ | |
4043 | ||
4044 | static void | |
4045 | fix_loongson2f_jump (struct mips_cl_insn * ip) | |
4046 | { | |
df58fc94 | 4047 | gas_assert (!HAVE_CODE_COMPRESSION); |
c67a084a NC |
4048 | if (strcmp (ip->insn_mo->name, "j") == 0 |
4049 | || strcmp (ip->insn_mo->name, "jr") == 0 | |
4050 | || strcmp (ip->insn_mo->name, "jalr") == 0) | |
4051 | { | |
4052 | int sreg; | |
4053 | expressionS ep; | |
4054 | ||
4055 | if (! mips_opts.at) | |
4056 | return; | |
4057 | ||
df58fc94 | 4058 | sreg = EXTRACT_OPERAND (0, RS, *ip); |
c67a084a NC |
4059 | if (sreg == ZERO || sreg == KT0 || sreg == KT1 || sreg == ATREG) |
4060 | return; | |
4061 | ||
4062 | ep.X_op = O_constant; | |
4063 | ep.X_add_number = 0xcfff0000; | |
4064 | macro_build (&ep, "lui", "t,u", ATREG, BFD_RELOC_HI16); | |
4065 | ep.X_add_number = 0xffff; | |
4066 | macro_build (&ep, "ori", "t,r,i", ATREG, ATREG, BFD_RELOC_LO16); | |
4067 | macro_build (NULL, "and", "d,v,t", sreg, sreg, ATREG); | |
4068 | } | |
4069 | } | |
4070 | ||
4071 | static void | |
4072 | fix_loongson2f (struct mips_cl_insn * ip) | |
4073 | { | |
4074 | if (mips_fix_loongson2f_nop) | |
4075 | fix_loongson2f_nop (ip); | |
4076 | ||
4077 | if (mips_fix_loongson2f_jump) | |
4078 | fix_loongson2f_jump (ip); | |
4079 | } | |
4080 | ||
a4e06468 RS |
4081 | /* IP is a branch that has a delay slot, and we need to fill it |
4082 | automatically. Return true if we can do that by swapping IP | |
e407c74b NC |
4083 | with the previous instruction. |
4084 | ADDRESS_EXPR is an operand of the instruction to be used with | |
4085 | RELOC_TYPE. */ | |
a4e06468 RS |
4086 | |
4087 | static bfd_boolean | |
e407c74b NC |
4088 | can_swap_branch_p (struct mips_cl_insn *ip, expressionS *address_expr, |
4089 | bfd_reloc_code_real_type *reloc_type) | |
a4e06468 | 4090 | { |
2b0c8b40 | 4091 | unsigned long pinfo, pinfo2, prev_pinfo, prev_pinfo2; |
a4e06468 RS |
4092 | unsigned int gpr_read, gpr_write, prev_gpr_read, prev_gpr_write; |
4093 | ||
4094 | /* -O2 and above is required for this optimization. */ | |
4095 | if (mips_optimize < 2) | |
4096 | return FALSE; | |
4097 | ||
4098 | /* If we have seen .set volatile or .set nomove, don't optimize. */ | |
4099 | if (mips_opts.nomove) | |
4100 | return FALSE; | |
4101 | ||
4102 | /* We can't swap if the previous instruction's position is fixed. */ | |
4103 | if (history[0].fixed_p) | |
4104 | return FALSE; | |
4105 | ||
4106 | /* If the previous previous insn was in a .set noreorder, we can't | |
4107 | swap. Actually, the MIPS assembler will swap in this situation. | |
4108 | However, gcc configured -with-gnu-as will generate code like | |
4109 | ||
4110 | .set noreorder | |
4111 | lw $4,XXX | |
4112 | .set reorder | |
4113 | INSN | |
4114 | bne $4,$0,foo | |
4115 | ||
4116 | in which we can not swap the bne and INSN. If gcc is not configured | |
4117 | -with-gnu-as, it does not output the .set pseudo-ops. */ | |
4118 | if (history[1].noreorder_p) | |
4119 | return FALSE; | |
4120 | ||
87333bb7 MR |
4121 | /* If the previous instruction had a fixup in mips16 mode, we can not swap. |
4122 | This means that the previous instruction was a 4-byte one anyhow. */ | |
a4e06468 RS |
4123 | if (mips_opts.mips16 && history[0].fixp[0]) |
4124 | return FALSE; | |
4125 | ||
4126 | /* If the branch is itself the target of a branch, we can not swap. | |
4127 | We cheat on this; all we check for is whether there is a label on | |
4128 | this instruction. If there are any branches to anything other than | |
4129 | a label, users must use .set noreorder. */ | |
4130 | if (seg_info (now_seg)->label_list) | |
4131 | return FALSE; | |
4132 | ||
4133 | /* If the previous instruction is in a variant frag other than this | |
2309ddf2 | 4134 | branch's one, we cannot do the swap. This does not apply to |
9301f9c3 MR |
4135 | MIPS16 code, which uses variant frags for different purposes. */ |
4136 | if (!mips_opts.mips16 | |
a4e06468 RS |
4137 | && history[0].frag |
4138 | && history[0].frag->fr_type == rs_machine_dependent) | |
4139 | return FALSE; | |
4140 | ||
bcd530a7 RS |
4141 | /* We do not swap with instructions that cannot architecturally |
4142 | be placed in a branch delay slot, such as SYNC or ERET. We | |
4143 | also refrain from swapping with a trap instruction, since it | |
4144 | complicates trap handlers to have the trap instruction be in | |
4145 | a delay slot. */ | |
a4e06468 | 4146 | prev_pinfo = history[0].insn_mo->pinfo; |
bcd530a7 | 4147 | if (prev_pinfo & INSN_NO_DELAY_SLOT) |
a4e06468 RS |
4148 | return FALSE; |
4149 | ||
4150 | /* Check for conflicts between the branch and the instructions | |
4151 | before the candidate delay slot. */ | |
4152 | if (nops_for_insn (0, history + 1, ip) > 0) | |
4153 | return FALSE; | |
4154 | ||
4155 | /* Check for conflicts between the swapped sequence and the | |
4156 | target of the branch. */ | |
4157 | if (nops_for_sequence (2, 0, history + 1, ip, history) > 0) | |
4158 | return FALSE; | |
4159 | ||
4160 | /* If the branch reads a register that the previous | |
4161 | instruction sets, we can not swap. */ | |
4162 | gpr_read = gpr_read_mask (ip); | |
4163 | prev_gpr_write = gpr_write_mask (&history[0]); | |
4164 | if (gpr_read & prev_gpr_write) | |
4165 | return FALSE; | |
4166 | ||
4167 | /* If the branch writes a register that the previous | |
4168 | instruction sets, we can not swap. */ | |
4169 | gpr_write = gpr_write_mask (ip); | |
4170 | if (gpr_write & prev_gpr_write) | |
4171 | return FALSE; | |
4172 | ||
4173 | /* If the branch writes a register that the previous | |
4174 | instruction reads, we can not swap. */ | |
4175 | prev_gpr_read = gpr_read_mask (&history[0]); | |
4176 | if (gpr_write & prev_gpr_read) | |
4177 | return FALSE; | |
4178 | ||
4179 | /* If one instruction sets a condition code and the | |
4180 | other one uses a condition code, we can not swap. */ | |
4181 | pinfo = ip->insn_mo->pinfo; | |
4182 | if ((pinfo & INSN_READ_COND_CODE) | |
4183 | && (prev_pinfo & INSN_WRITE_COND_CODE)) | |
4184 | return FALSE; | |
4185 | if ((pinfo & INSN_WRITE_COND_CODE) | |
4186 | && (prev_pinfo & INSN_READ_COND_CODE)) | |
4187 | return FALSE; | |
4188 | ||
4189 | /* If the previous instruction uses the PC, we can not swap. */ | |
2b0c8b40 | 4190 | prev_pinfo2 = history[0].insn_mo->pinfo2; |
a4e06468 RS |
4191 | if (mips_opts.mips16 && (prev_pinfo & MIPS16_INSN_READ_PC)) |
4192 | return FALSE; | |
2b0c8b40 MR |
4193 | if (mips_opts.micromips && (prev_pinfo2 & INSN2_READ_PC)) |
4194 | return FALSE; | |
a4e06468 | 4195 | |
df58fc94 RS |
4196 | /* If the previous instruction has an incorrect size for a fixed |
4197 | branch delay slot in microMIPS mode, we cannot swap. */ | |
2309ddf2 MR |
4198 | pinfo2 = ip->insn_mo->pinfo2; |
4199 | if (mips_opts.micromips | |
4200 | && (pinfo2 & INSN2_BRANCH_DELAY_16BIT) | |
4201 | && insn_length (history) != 2) | |
4202 | return FALSE; | |
4203 | if (mips_opts.micromips | |
4204 | && (pinfo2 & INSN2_BRANCH_DELAY_32BIT) | |
4205 | && insn_length (history) != 4) | |
4206 | return FALSE; | |
4207 | ||
e407c74b NC |
4208 | /* On R5900 short loops need to be fixed by inserting a nop in |
4209 | the branch delay slots. | |
4210 | A short loop can be terminated too early. */ | |
4211 | if (mips_opts.arch == CPU_R5900 | |
4212 | /* Check if instruction has a parameter, ignore "j $31". */ | |
4213 | && (address_expr != NULL) | |
4214 | /* Parameter must be 16 bit. */ | |
4215 | && (*reloc_type == BFD_RELOC_16_PCREL_S2) | |
4216 | /* Branch to same segment. */ | |
4217 | && (S_GET_SEGMENT(address_expr->X_add_symbol) == now_seg) | |
4218 | /* Branch to same code fragment. */ | |
4219 | && (symbol_get_frag(address_expr->X_add_symbol) == frag_now) | |
4220 | /* Can only calculate branch offset if value is known. */ | |
4221 | && symbol_constant_p(address_expr->X_add_symbol) | |
4222 | /* Check if branch is really conditional. */ | |
4223 | && !((ip->insn_opcode & 0xffff0000) == 0x10000000 /* beq $0,$0 */ | |
4224 | || (ip->insn_opcode & 0xffff0000) == 0x04010000 /* bgez $0 */ | |
4225 | || (ip->insn_opcode & 0xffff0000) == 0x04110000)) /* bgezal $0 */ | |
4226 | { | |
4227 | int distance; | |
4228 | /* Check if loop is shorter than 6 instructions including | |
4229 | branch and delay slot. */ | |
4230 | distance = frag_now_fix() - S_GET_VALUE(address_expr->X_add_symbol); | |
4231 | if (distance <= 20) | |
4232 | { | |
4233 | int i; | |
4234 | int rv; | |
4235 | ||
4236 | rv = FALSE; | |
4237 | /* When the loop includes branches or jumps, | |
4238 | it is not a short loop. */ | |
4239 | for (i = 0; i < (distance / 4); i++) | |
4240 | { | |
4241 | if ((history[i].cleared_p) | |
4242 | || delayed_branch_p(&history[i])) | |
4243 | { | |
4244 | rv = TRUE; | |
4245 | break; | |
4246 | } | |
4247 | } | |
4248 | if (rv == FALSE) | |
4249 | { | |
4250 | /* Insert nop after branch to fix short loop. */ | |
4251 | return FALSE; | |
4252 | } | |
4253 | } | |
4254 | } | |
4255 | ||
a4e06468 RS |
4256 | return TRUE; |
4257 | } | |
4258 | ||
e407c74b NC |
4259 | /* Decide how we should add IP to the instruction stream. |
4260 | ADDRESS_EXPR is an operand of the instruction to be used with | |
4261 | RELOC_TYPE. */ | |
a4e06468 RS |
4262 | |
4263 | static enum append_method | |
e407c74b NC |
4264 | get_append_method (struct mips_cl_insn *ip, expressionS *address_expr, |
4265 | bfd_reloc_code_real_type *reloc_type) | |
a4e06468 RS |
4266 | { |
4267 | unsigned long pinfo; | |
4268 | ||
4269 | /* The relaxed version of a macro sequence must be inherently | |
4270 | hazard-free. */ | |
4271 | if (mips_relax.sequence == 2) | |
4272 | return APPEND_ADD; | |
4273 | ||
4274 | /* We must not dabble with instructions in a ".set norerorder" block. */ | |
4275 | if (mips_opts.noreorder) | |
4276 | return APPEND_ADD; | |
4277 | ||
4278 | /* Otherwise, it's our responsibility to fill branch delay slots. */ | |
11625dd8 | 4279 | if (delayed_branch_p (ip)) |
a4e06468 | 4280 | { |
e407c74b NC |
4281 | if (!branch_likely_p (ip) |
4282 | && can_swap_branch_p (ip, address_expr, reloc_type)) | |
a4e06468 RS |
4283 | return APPEND_SWAP; |
4284 | ||
11625dd8 | 4285 | pinfo = ip->insn_mo->pinfo; |
a4e06468 RS |
4286 | if (mips_opts.mips16 |
4287 | && ISA_SUPPORTS_MIPS16E | |
a4e06468 RS |
4288 | && (pinfo & (MIPS16_INSN_READ_X | MIPS16_INSN_READ_31))) |
4289 | return APPEND_ADD_COMPACT; | |
4290 | ||
4291 | return APPEND_ADD_WITH_NOP; | |
4292 | } | |
4293 | ||
a4e06468 RS |
4294 | return APPEND_ADD; |
4295 | } | |
4296 | ||
ceb94aa5 RS |
4297 | /* IP is a MIPS16 instruction whose opcode we have just changed. |
4298 | Point IP->insn_mo to the new opcode's definition. */ | |
4299 | ||
4300 | static void | |
4301 | find_altered_mips16_opcode (struct mips_cl_insn *ip) | |
4302 | { | |
4303 | const struct mips_opcode *mo, *end; | |
4304 | ||
4305 | end = &mips16_opcodes[bfd_mips16_num_opcodes]; | |
4306 | for (mo = ip->insn_mo; mo < end; mo++) | |
4307 | if ((ip->insn_opcode & mo->mask) == mo->match) | |
4308 | { | |
4309 | ip->insn_mo = mo; | |
4310 | return; | |
4311 | } | |
4312 | abort (); | |
4313 | } | |
4314 | ||
df58fc94 RS |
4315 | /* For microMIPS macros, we need to generate a local number label |
4316 | as the target of branches. */ | |
4317 | #define MICROMIPS_LABEL_CHAR '\037' | |
4318 | static unsigned long micromips_target_label; | |
4319 | static char micromips_target_name[32]; | |
4320 | ||
4321 | static char * | |
4322 | micromips_label_name (void) | |
4323 | { | |
4324 | char *p = micromips_target_name; | |
4325 | char symbol_name_temporary[24]; | |
4326 | unsigned long l; | |
4327 | int i; | |
4328 | ||
4329 | if (*p) | |
4330 | return p; | |
4331 | ||
4332 | i = 0; | |
4333 | l = micromips_target_label; | |
4334 | #ifdef LOCAL_LABEL_PREFIX | |
4335 | *p++ = LOCAL_LABEL_PREFIX; | |
4336 | #endif | |
4337 | *p++ = 'L'; | |
4338 | *p++ = MICROMIPS_LABEL_CHAR; | |
4339 | do | |
4340 | { | |
4341 | symbol_name_temporary[i++] = l % 10 + '0'; | |
4342 | l /= 10; | |
4343 | } | |
4344 | while (l != 0); | |
4345 | while (i > 0) | |
4346 | *p++ = symbol_name_temporary[--i]; | |
4347 | *p = '\0'; | |
4348 | ||
4349 | return micromips_target_name; | |
4350 | } | |
4351 | ||
4352 | static void | |
4353 | micromips_label_expr (expressionS *label_expr) | |
4354 | { | |
4355 | label_expr->X_op = O_symbol; | |
4356 | label_expr->X_add_symbol = symbol_find_or_make (micromips_label_name ()); | |
4357 | label_expr->X_add_number = 0; | |
4358 | } | |
4359 | ||
4360 | static void | |
4361 | micromips_label_inc (void) | |
4362 | { | |
4363 | micromips_target_label++; | |
4364 | *micromips_target_name = '\0'; | |
4365 | } | |
4366 | ||
4367 | static void | |
4368 | micromips_add_label (void) | |
4369 | { | |
4370 | symbolS *s; | |
4371 | ||
4372 | s = colon (micromips_label_name ()); | |
4373 | micromips_label_inc (); | |
f3ded42a | 4374 | S_SET_OTHER (s, ELF_ST_SET_MICROMIPS (S_GET_OTHER (s))); |
df58fc94 RS |
4375 | } |
4376 | ||
4377 | /* If assembling microMIPS code, then return the microMIPS reloc | |
4378 | corresponding to the requested one if any. Otherwise return | |
4379 | the reloc unchanged. */ | |
4380 | ||
4381 | static bfd_reloc_code_real_type | |
4382 | micromips_map_reloc (bfd_reloc_code_real_type reloc) | |
4383 | { | |
4384 | static const bfd_reloc_code_real_type relocs[][2] = | |
4385 | { | |
4386 | /* Keep sorted incrementally by the left-hand key. */ | |
4387 | { BFD_RELOC_16_PCREL_S2, BFD_RELOC_MICROMIPS_16_PCREL_S1 }, | |
4388 | { BFD_RELOC_GPREL16, BFD_RELOC_MICROMIPS_GPREL16 }, | |
4389 | { BFD_RELOC_MIPS_JMP, BFD_RELOC_MICROMIPS_JMP }, | |
4390 | { BFD_RELOC_HI16, BFD_RELOC_MICROMIPS_HI16 }, | |
4391 | { BFD_RELOC_HI16_S, BFD_RELOC_MICROMIPS_HI16_S }, | |
4392 | { BFD_RELOC_LO16, BFD_RELOC_MICROMIPS_LO16 }, | |
4393 | { BFD_RELOC_MIPS_LITERAL, BFD_RELOC_MICROMIPS_LITERAL }, | |
4394 | { BFD_RELOC_MIPS_GOT16, BFD_RELOC_MICROMIPS_GOT16 }, | |
4395 | { BFD_RELOC_MIPS_CALL16, BFD_RELOC_MICROMIPS_CALL16 }, | |
4396 | { BFD_RELOC_MIPS_GOT_HI16, BFD_RELOC_MICROMIPS_GOT_HI16 }, | |
4397 | { BFD_RELOC_MIPS_GOT_LO16, BFD_RELOC_MICROMIPS_GOT_LO16 }, | |
4398 | { BFD_RELOC_MIPS_CALL_HI16, BFD_RELOC_MICROMIPS_CALL_HI16 }, | |
4399 | { BFD_RELOC_MIPS_CALL_LO16, BFD_RELOC_MICROMIPS_CALL_LO16 }, | |
4400 | { BFD_RELOC_MIPS_SUB, BFD_RELOC_MICROMIPS_SUB }, | |
4401 | { BFD_RELOC_MIPS_GOT_PAGE, BFD_RELOC_MICROMIPS_GOT_PAGE }, | |
4402 | { BFD_RELOC_MIPS_GOT_OFST, BFD_RELOC_MICROMIPS_GOT_OFST }, | |
4403 | { BFD_RELOC_MIPS_GOT_DISP, BFD_RELOC_MICROMIPS_GOT_DISP }, | |
4404 | { BFD_RELOC_MIPS_HIGHEST, BFD_RELOC_MICROMIPS_HIGHEST }, | |
4405 | { BFD_RELOC_MIPS_HIGHER, BFD_RELOC_MICROMIPS_HIGHER }, | |
4406 | { BFD_RELOC_MIPS_SCN_DISP, BFD_RELOC_MICROMIPS_SCN_DISP }, | |
4407 | { BFD_RELOC_MIPS_TLS_GD, BFD_RELOC_MICROMIPS_TLS_GD }, | |
4408 | { BFD_RELOC_MIPS_TLS_LDM, BFD_RELOC_MICROMIPS_TLS_LDM }, | |
4409 | { BFD_RELOC_MIPS_TLS_DTPREL_HI16, BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16 }, | |
4410 | { BFD_RELOC_MIPS_TLS_DTPREL_LO16, BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16 }, | |
4411 | { BFD_RELOC_MIPS_TLS_GOTTPREL, BFD_RELOC_MICROMIPS_TLS_GOTTPREL }, | |
4412 | { BFD_RELOC_MIPS_TLS_TPREL_HI16, BFD_RELOC_MICROMIPS_TLS_TPREL_HI16 }, | |
4413 | { BFD_RELOC_MIPS_TLS_TPREL_LO16, BFD_RELOC_MICROMIPS_TLS_TPREL_LO16 } | |
4414 | }; | |
4415 | bfd_reloc_code_real_type r; | |
4416 | size_t i; | |
4417 | ||
4418 | if (!mips_opts.micromips) | |
4419 | return reloc; | |
4420 | for (i = 0; i < ARRAY_SIZE (relocs); i++) | |
4421 | { | |
4422 | r = relocs[i][0]; | |
4423 | if (r > reloc) | |
4424 | return reloc; | |
4425 | if (r == reloc) | |
4426 | return relocs[i][1]; | |
4427 | } | |
4428 | return reloc; | |
4429 | } | |
4430 | ||
b886a2ab RS |
4431 | /* Try to resolve relocation RELOC against constant OPERAND at assembly time. |
4432 | Return true on success, storing the resolved value in RESULT. */ | |
4433 | ||
4434 | static bfd_boolean | |
4435 | calculate_reloc (bfd_reloc_code_real_type reloc, offsetT operand, | |
4436 | offsetT *result) | |
4437 | { | |
4438 | switch (reloc) | |
4439 | { | |
4440 | case BFD_RELOC_MIPS_HIGHEST: | |
4441 | case BFD_RELOC_MICROMIPS_HIGHEST: | |
4442 | *result = ((operand + 0x800080008000ull) >> 48) & 0xffff; | |
4443 | return TRUE; | |
4444 | ||
4445 | case BFD_RELOC_MIPS_HIGHER: | |
4446 | case BFD_RELOC_MICROMIPS_HIGHER: | |
4447 | *result = ((operand + 0x80008000ull) >> 32) & 0xffff; | |
4448 | return TRUE; | |
4449 | ||
4450 | case BFD_RELOC_HI16_S: | |
4451 | case BFD_RELOC_MICROMIPS_HI16_S: | |
4452 | case BFD_RELOC_MIPS16_HI16_S: | |
4453 | *result = ((operand + 0x8000) >> 16) & 0xffff; | |
4454 | return TRUE; | |
4455 | ||
4456 | case BFD_RELOC_HI16: | |
4457 | case BFD_RELOC_MICROMIPS_HI16: | |
4458 | case BFD_RELOC_MIPS16_HI16: | |
4459 | *result = (operand >> 16) & 0xffff; | |
4460 | return TRUE; | |
4461 | ||
4462 | case BFD_RELOC_LO16: | |
4463 | case BFD_RELOC_MICROMIPS_LO16: | |
4464 | case BFD_RELOC_MIPS16_LO16: | |
4465 | *result = operand & 0xffff; | |
4466 | return TRUE; | |
4467 | ||
4468 | case BFD_RELOC_UNUSED: | |
4469 | *result = operand; | |
4470 | return TRUE; | |
4471 | ||
4472 | default: | |
4473 | return FALSE; | |
4474 | } | |
4475 | } | |
4476 | ||
71400594 RS |
4477 | /* Output an instruction. IP is the instruction information. |
4478 | ADDRESS_EXPR is an operand of the instruction to be used with | |
df58fc94 RS |
4479 | RELOC_TYPE. EXPANSIONP is true if the instruction is part of |
4480 | a macro expansion. */ | |
71400594 RS |
4481 | |
4482 | static void | |
4483 | append_insn (struct mips_cl_insn *ip, expressionS *address_expr, | |
df58fc94 | 4484 | bfd_reloc_code_real_type *reloc_type, bfd_boolean expansionp) |
71400594 | 4485 | { |
14fe068b | 4486 | unsigned long prev_pinfo2, pinfo; |
71400594 | 4487 | bfd_boolean relaxed_branch = FALSE; |
a4e06468 | 4488 | enum append_method method; |
2309ddf2 | 4489 | bfd_boolean relax32; |
2b0c8b40 | 4490 | int branch_disp; |
71400594 | 4491 | |
2309ddf2 | 4492 | if (mips_fix_loongson2f && !HAVE_CODE_COMPRESSION) |
c67a084a NC |
4493 | fix_loongson2f (ip); |
4494 | ||
738f4d98 | 4495 | file_ase_mips16 |= mips_opts.mips16; |
df58fc94 | 4496 | file_ase_micromips |= mips_opts.micromips; |
738f4d98 | 4497 | |
df58fc94 | 4498 | prev_pinfo2 = history[0].insn_mo->pinfo2; |
71400594 | 4499 | pinfo = ip->insn_mo->pinfo; |
df58fc94 RS |
4500 | |
4501 | if (mips_opts.micromips | |
4502 | && !expansionp | |
4503 | && (((prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 | |
4504 | && micromips_insn_length (ip->insn_mo) != 2) | |
4505 | || ((prev_pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0 | |
4506 | && micromips_insn_length (ip->insn_mo) != 4))) | |
4507 | as_warn (_("Wrong size instruction in a %u-bit branch delay slot"), | |
4508 | (prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 ? 16 : 32); | |
71400594 | 4509 | |
15be625d CM |
4510 | if (address_expr == NULL) |
4511 | ip->complete_p = 1; | |
b886a2ab RS |
4512 | else if (reloc_type[0] <= BFD_RELOC_UNUSED |
4513 | && reloc_type[1] == BFD_RELOC_UNUSED | |
4514 | && reloc_type[2] == BFD_RELOC_UNUSED | |
15be625d CM |
4515 | && address_expr->X_op == O_constant) |
4516 | { | |
15be625d CM |
4517 | switch (*reloc_type) |
4518 | { | |
15be625d | 4519 | case BFD_RELOC_MIPS_JMP: |
df58fc94 RS |
4520 | { |
4521 | int shift; | |
4522 | ||
4523 | shift = mips_opts.micromips ? 1 : 2; | |
4524 | if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0) | |
4525 | as_bad (_("jump to misaligned address (0x%lx)"), | |
4526 | (unsigned long) address_expr->X_add_number); | |
4527 | ip->insn_opcode |= ((address_expr->X_add_number >> shift) | |
4528 | & 0x3ffffff); | |
335574df | 4529 | ip->complete_p = 1; |
df58fc94 | 4530 | } |
15be625d CM |
4531 | break; |
4532 | ||
4533 | case BFD_RELOC_MIPS16_JMP: | |
4534 | if ((address_expr->X_add_number & 3) != 0) | |
4535 | as_bad (_("jump to misaligned address (0x%lx)"), | |
4536 | (unsigned long) address_expr->X_add_number); | |
4537 | ip->insn_opcode |= | |
4538 | (((address_expr->X_add_number & 0x7c0000) << 3) | |
4539 | | ((address_expr->X_add_number & 0xf800000) >> 7) | |
4540 | | ((address_expr->X_add_number & 0x3fffc) >> 2)); | |
335574df | 4541 | ip->complete_p = 1; |
15be625d CM |
4542 | break; |
4543 | ||
4544 | case BFD_RELOC_16_PCREL_S2: | |
df58fc94 RS |
4545 | { |
4546 | int shift; | |
4547 | ||
4548 | shift = mips_opts.micromips ? 1 : 2; | |
4549 | if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0) | |
4550 | as_bad (_("branch to misaligned address (0x%lx)"), | |
4551 | (unsigned long) address_expr->X_add_number); | |
4552 | if (!mips_relax_branch) | |
4553 | { | |
4554 | if ((address_expr->X_add_number + (1 << (shift + 15))) | |
4555 | & ~((1 << (shift + 16)) - 1)) | |
4556 | as_bad (_("branch address range overflow (0x%lx)"), | |
4557 | (unsigned long) address_expr->X_add_number); | |
4558 | ip->insn_opcode |= ((address_expr->X_add_number >> shift) | |
4559 | & 0xffff); | |
4560 | } | |
df58fc94 | 4561 | } |
15be625d CM |
4562 | break; |
4563 | ||
4564 | default: | |
b886a2ab RS |
4565 | { |
4566 | offsetT value; | |
4567 | ||
4568 | if (calculate_reloc (*reloc_type, address_expr->X_add_number, | |
4569 | &value)) | |
4570 | { | |
4571 | ip->insn_opcode |= value & 0xffff; | |
4572 | ip->complete_p = 1; | |
4573 | } | |
4574 | } | |
4575 | break; | |
4576 | } | |
15be625d CM |
4577 | } |
4578 | ||
71400594 RS |
4579 | if (mips_relax.sequence != 2 && !mips_opts.noreorder) |
4580 | { | |
4581 | /* There are a lot of optimizations we could do that we don't. | |
4582 | In particular, we do not, in general, reorder instructions. | |
4583 | If you use gcc with optimization, it will reorder | |
4584 | instructions and generally do much more optimization then we | |
4585 | do here; repeating all that work in the assembler would only | |
4586 | benefit hand written assembly code, and does not seem worth | |
4587 | it. */ | |
4588 | int nops = (mips_optimize == 0 | |
932d1a1b RS |
4589 | ? nops_for_insn (0, history, NULL) |
4590 | : nops_for_insn_or_target (0, history, ip)); | |
71400594 | 4591 | if (nops > 0) |
252b5132 RH |
4592 | { |
4593 | fragS *old_frag; | |
4594 | unsigned long old_frag_offset; | |
4595 | int i; | |
252b5132 RH |
4596 | |
4597 | old_frag = frag_now; | |
4598 | old_frag_offset = frag_now_fix (); | |
4599 | ||
4600 | for (i = 0; i < nops; i++) | |
14fe068b RS |
4601 | add_fixed_insn (NOP_INSN); |
4602 | insert_into_history (0, nops, NOP_INSN); | |
252b5132 RH |
4603 | |
4604 | if (listing) | |
4605 | { | |
4606 | listing_prev_line (); | |
4607 | /* We may be at the start of a variant frag. In case we | |
4608 | are, make sure there is enough space for the frag | |
4609 | after the frags created by listing_prev_line. The | |
4610 | argument to frag_grow here must be at least as large | |
4611 | as the argument to all other calls to frag_grow in | |
4612 | this file. We don't have to worry about being in the | |
4613 | middle of a variant frag, because the variants insert | |
4614 | all needed nop instructions themselves. */ | |
4615 | frag_grow (40); | |
4616 | } | |
4617 | ||
462427c4 | 4618 | mips_move_text_labels (); |
252b5132 RH |
4619 | |
4620 | #ifndef NO_ECOFF_DEBUGGING | |
4621 | if (ECOFF_DEBUGGING) | |
4622 | ecoff_fix_loc (old_frag, old_frag_offset); | |
4623 | #endif | |
4624 | } | |
71400594 RS |
4625 | } |
4626 | else if (mips_relax.sequence != 2 && prev_nop_frag != NULL) | |
4627 | { | |
932d1a1b RS |
4628 | int nops; |
4629 | ||
4630 | /* Work out how many nops in prev_nop_frag are needed by IP, | |
4631 | ignoring hazards generated by the first prev_nop_frag_since | |
4632 | instructions. */ | |
4633 | nops = nops_for_insn_or_target (prev_nop_frag_since, history, ip); | |
9c2799c2 | 4634 | gas_assert (nops <= prev_nop_frag_holds); |
252b5132 | 4635 | |
71400594 RS |
4636 | /* Enforce NOPS as a minimum. */ |
4637 | if (nops > prev_nop_frag_required) | |
4638 | prev_nop_frag_required = nops; | |
252b5132 | 4639 | |
71400594 RS |
4640 | if (prev_nop_frag_holds == prev_nop_frag_required) |
4641 | { | |
4642 | /* Settle for the current number of nops. Update the history | |
4643 | accordingly (for the benefit of any future .set reorder code). */ | |
4644 | prev_nop_frag = NULL; | |
4645 | insert_into_history (prev_nop_frag_since, | |
4646 | prev_nop_frag_holds, NOP_INSN); | |
4647 | } | |
4648 | else | |
4649 | { | |
4650 | /* Allow this instruction to replace one of the nops that was | |
4651 | tentatively added to prev_nop_frag. */ | |
df58fc94 | 4652 | prev_nop_frag->fr_fix -= NOP_INSN_SIZE; |
71400594 RS |
4653 | prev_nop_frag_holds--; |
4654 | prev_nop_frag_since++; | |
252b5132 RH |
4655 | } |
4656 | } | |
4657 | ||
e407c74b | 4658 | method = get_append_method (ip, address_expr, reloc_type); |
2b0c8b40 | 4659 | branch_disp = method == APPEND_SWAP ? insn_length (history) : 0; |
a4e06468 | 4660 | |
e410add4 RS |
4661 | dwarf2_emit_insn (0); |
4662 | /* We want MIPS16 and microMIPS debug info to use ISA-encoded addresses, | |
4663 | so "move" the instruction address accordingly. | |
4664 | ||
4665 | Also, it doesn't seem appropriate for the assembler to reorder .loc | |
4666 | entries. If this instruction is a branch that we are going to swap | |
4667 | with the previous instruction, the two instructions should be | |
4668 | treated as a unit, and the debug information for both instructions | |
4669 | should refer to the start of the branch sequence. Using the | |
4670 | current position is certainly wrong when swapping a 32-bit branch | |
4671 | and a 16-bit delay slot, since the current position would then be | |
4672 | in the middle of a branch. */ | |
4673 | dwarf2_move_insn ((HAVE_CODE_COMPRESSION ? 1 : 0) - branch_disp); | |
58e2ea4d | 4674 | |
df58fc94 RS |
4675 | relax32 = (mips_relax_branch |
4676 | /* Don't try branch relaxation within .set nomacro, or within | |
4677 | .set noat if we use $at for PIC computations. If it turns | |
4678 | out that the branch was out-of-range, we'll get an error. */ | |
4679 | && !mips_opts.warn_about_macros | |
4680 | && (mips_opts.at || mips_pic == NO_PIC) | |
3bf0dbfb MR |
4681 | /* Don't relax BPOSGE32/64 or BC1ANY2T/F and BC1ANY4T/F |
4682 | as they have no complementing branches. */ | |
4683 | && !(ip->insn_mo->ase & (ASE_MIPS3D | ASE_DSP64 | ASE_DSP))); | |
df58fc94 RS |
4684 | |
4685 | if (!HAVE_CODE_COMPRESSION | |
4686 | && address_expr | |
4687 | && relax32 | |
0b25d3e6 | 4688 | && *reloc_type == BFD_RELOC_16_PCREL_S2 |
11625dd8 | 4689 | && delayed_branch_p (ip)) |
4a6a3df4 | 4690 | { |
895921c9 | 4691 | relaxed_branch = TRUE; |
1e915849 RS |
4692 | add_relaxed_insn (ip, (relaxed_branch_length |
4693 | (NULL, NULL, | |
11625dd8 RS |
4694 | uncond_branch_p (ip) ? -1 |
4695 | : branch_likely_p (ip) ? 1 | |
1e915849 RS |
4696 | : 0)), 4, |
4697 | RELAX_BRANCH_ENCODE | |
66b3e8da | 4698 | (AT, |
11625dd8 RS |
4699 | uncond_branch_p (ip), |
4700 | branch_likely_p (ip), | |
1e915849 RS |
4701 | pinfo & INSN_WRITE_GPR_31, |
4702 | 0), | |
4703 | address_expr->X_add_symbol, | |
4704 | address_expr->X_add_number); | |
4a6a3df4 AO |
4705 | *reloc_type = BFD_RELOC_UNUSED; |
4706 | } | |
df58fc94 RS |
4707 | else if (mips_opts.micromips |
4708 | && address_expr | |
4709 | && ((relax32 && *reloc_type == BFD_RELOC_16_PCREL_S2) | |
4710 | || *reloc_type > BFD_RELOC_UNUSED) | |
40209cad MR |
4711 | && (delayed_branch_p (ip) || compact_branch_p (ip)) |
4712 | /* Don't try branch relaxation when users specify | |
4713 | 16-bit/32-bit instructions. */ | |
4714 | && !forced_insn_length) | |
df58fc94 RS |
4715 | { |
4716 | bfd_boolean relax16 = *reloc_type > BFD_RELOC_UNUSED; | |
4717 | int type = relax16 ? *reloc_type - BFD_RELOC_UNUSED : 0; | |
11625dd8 RS |
4718 | int uncond = uncond_branch_p (ip) ? -1 : 0; |
4719 | int compact = compact_branch_p (ip); | |
df58fc94 RS |
4720 | int al = pinfo & INSN_WRITE_GPR_31; |
4721 | int length32; | |
4722 | ||
4723 | gas_assert (address_expr != NULL); | |
4724 | gas_assert (!mips_relax.sequence); | |
4725 | ||
2b0c8b40 | 4726 | relaxed_branch = TRUE; |
df58fc94 RS |
4727 | length32 = relaxed_micromips_32bit_branch_length (NULL, NULL, uncond); |
4728 | add_relaxed_insn (ip, relax32 ? length32 : 4, relax16 ? 2 : 4, | |
40209cad MR |
4729 | RELAX_MICROMIPS_ENCODE (type, AT, uncond, compact, al, |
4730 | relax32, 0, 0), | |
df58fc94 RS |
4731 | address_expr->X_add_symbol, |
4732 | address_expr->X_add_number); | |
4733 | *reloc_type = BFD_RELOC_UNUSED; | |
4734 | } | |
4735 | else if (mips_opts.mips16 && *reloc_type > BFD_RELOC_UNUSED) | |
252b5132 RH |
4736 | { |
4737 | /* We need to set up a variant frag. */ | |
df58fc94 | 4738 | gas_assert (address_expr != NULL); |
1e915849 RS |
4739 | add_relaxed_insn (ip, 4, 0, |
4740 | RELAX_MIPS16_ENCODE | |
4741 | (*reloc_type - BFD_RELOC_UNUSED, | |
df58fc94 | 4742 | forced_insn_length == 2, forced_insn_length == 4, |
11625dd8 | 4743 | delayed_branch_p (&history[0]), |
1e915849 RS |
4744 | history[0].mips16_absolute_jump_p), |
4745 | make_expr_symbol (address_expr), 0); | |
252b5132 | 4746 | } |
5c04167a | 4747 | else if (mips_opts.mips16 && insn_length (ip) == 2) |
9497f5ac | 4748 | { |
11625dd8 | 4749 | if (!delayed_branch_p (ip)) |
b8ee1a6e DU |
4750 | /* Make sure there is enough room to swap this instruction with |
4751 | a following jump instruction. */ | |
4752 | frag_grow (6); | |
1e915849 | 4753 | add_fixed_insn (ip); |
252b5132 RH |
4754 | } |
4755 | else | |
4756 | { | |
4757 | if (mips_opts.mips16 | |
4758 | && mips_opts.noreorder | |
11625dd8 | 4759 | && delayed_branch_p (&history[0])) |
252b5132 RH |
4760 | as_warn (_("extended instruction in delay slot")); |
4761 | ||
4d7206a2 RS |
4762 | if (mips_relax.sequence) |
4763 | { | |
4764 | /* If we've reached the end of this frag, turn it into a variant | |
4765 | frag and record the information for the instructions we've | |
4766 | written so far. */ | |
4767 | if (frag_room () < 4) | |
4768 | relax_close_frag (); | |
df58fc94 | 4769 | mips_relax.sizes[mips_relax.sequence - 1] += insn_length (ip); |
4d7206a2 RS |
4770 | } |
4771 | ||
584892a6 | 4772 | if (mips_relax.sequence != 2) |
df58fc94 RS |
4773 | { |
4774 | if (mips_macro_warning.first_insn_sizes[0] == 0) | |
4775 | mips_macro_warning.first_insn_sizes[0] = insn_length (ip); | |
4776 | mips_macro_warning.sizes[0] += insn_length (ip); | |
4777 | mips_macro_warning.insns[0]++; | |
4778 | } | |
584892a6 | 4779 | if (mips_relax.sequence != 1) |
df58fc94 RS |
4780 | { |
4781 | if (mips_macro_warning.first_insn_sizes[1] == 0) | |
4782 | mips_macro_warning.first_insn_sizes[1] = insn_length (ip); | |
4783 | mips_macro_warning.sizes[1] += insn_length (ip); | |
4784 | mips_macro_warning.insns[1]++; | |
4785 | } | |
584892a6 | 4786 | |
1e915849 RS |
4787 | if (mips_opts.mips16) |
4788 | { | |
4789 | ip->fixed_p = 1; | |
4790 | ip->mips16_absolute_jump_p = (*reloc_type == BFD_RELOC_MIPS16_JMP); | |
4791 | } | |
4792 | add_fixed_insn (ip); | |
252b5132 RH |
4793 | } |
4794 | ||
9fe77896 | 4795 | if (!ip->complete_p && *reloc_type < BFD_RELOC_UNUSED) |
252b5132 | 4796 | { |
df58fc94 | 4797 | bfd_reloc_code_real_type final_type[3]; |
2309ddf2 | 4798 | reloc_howto_type *howto0; |
9fe77896 RS |
4799 | reloc_howto_type *howto; |
4800 | int i; | |
34ce925e | 4801 | |
df58fc94 RS |
4802 | /* Perform any necessary conversion to microMIPS relocations |
4803 | and find out how many relocations there actually are. */ | |
4804 | for (i = 0; i < 3 && reloc_type[i] != BFD_RELOC_UNUSED; i++) | |
4805 | final_type[i] = micromips_map_reloc (reloc_type[i]); | |
4806 | ||
9fe77896 RS |
4807 | /* In a compound relocation, it is the final (outermost) |
4808 | operator that determines the relocated field. */ | |
2309ddf2 | 4809 | howto = howto0 = bfd_reloc_type_lookup (stdoutput, final_type[i - 1]); |
e8044f35 RS |
4810 | if (!howto) |
4811 | abort (); | |
2309ddf2 MR |
4812 | |
4813 | if (i > 1) | |
4814 | howto0 = bfd_reloc_type_lookup (stdoutput, final_type[0]); | |
9fe77896 RS |
4815 | ip->fixp[0] = fix_new_exp (ip->frag, ip->where, |
4816 | bfd_get_reloc_size (howto), | |
4817 | address_expr, | |
2309ddf2 MR |
4818 | howto0 && howto0->pc_relative, |
4819 | final_type[0]); | |
9fe77896 RS |
4820 | |
4821 | /* Tag symbols that have a R_MIPS16_26 relocation against them. */ | |
2309ddf2 | 4822 | if (final_type[0] == BFD_RELOC_MIPS16_JMP && ip->fixp[0]->fx_addsy) |
9fe77896 RS |
4823 | *symbol_get_tc (ip->fixp[0]->fx_addsy) = 1; |
4824 | ||
4825 | /* These relocations can have an addend that won't fit in | |
4826 | 4 octets for 64bit assembly. */ | |
4827 | if (HAVE_64BIT_GPRS | |
4828 | && ! howto->partial_inplace | |
4829 | && (reloc_type[0] == BFD_RELOC_16 | |
4830 | || reloc_type[0] == BFD_RELOC_32 | |
4831 | || reloc_type[0] == BFD_RELOC_MIPS_JMP | |
4832 | || reloc_type[0] == BFD_RELOC_GPREL16 | |
4833 | || reloc_type[0] == BFD_RELOC_MIPS_LITERAL | |
4834 | || reloc_type[0] == BFD_RELOC_GPREL32 | |
4835 | || reloc_type[0] == BFD_RELOC_64 | |
4836 | || reloc_type[0] == BFD_RELOC_CTOR | |
4837 | || reloc_type[0] == BFD_RELOC_MIPS_SUB | |
4838 | || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST | |
4839 | || reloc_type[0] == BFD_RELOC_MIPS_HIGHER | |
4840 | || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP | |
4841 | || reloc_type[0] == BFD_RELOC_MIPS_REL16 | |
4842 | || reloc_type[0] == BFD_RELOC_MIPS_RELGOT | |
4843 | || reloc_type[0] == BFD_RELOC_MIPS16_GPREL | |
4844 | || hi16_reloc_p (reloc_type[0]) | |
4845 | || lo16_reloc_p (reloc_type[0]))) | |
4846 | ip->fixp[0]->fx_no_overflow = 1; | |
4847 | ||
ddaf2c41 MR |
4848 | /* These relocations can have an addend that won't fit in 2 octets. */ |
4849 | if (reloc_type[0] == BFD_RELOC_MICROMIPS_7_PCREL_S1 | |
4850 | || reloc_type[0] == BFD_RELOC_MICROMIPS_10_PCREL_S1) | |
4851 | ip->fixp[0]->fx_no_overflow = 1; | |
4852 | ||
9fe77896 RS |
4853 | if (mips_relax.sequence) |
4854 | { | |
4855 | if (mips_relax.first_fixup == 0) | |
4856 | mips_relax.first_fixup = ip->fixp[0]; | |
4857 | } | |
4858 | else if (reloc_needs_lo_p (*reloc_type)) | |
4859 | { | |
4860 | struct mips_hi_fixup *hi_fixup; | |
4861 | ||
4862 | /* Reuse the last entry if it already has a matching %lo. */ | |
4863 | hi_fixup = mips_hi_fixup_list; | |
4864 | if (hi_fixup == 0 | |
4865 | || !fixup_has_matching_lo_p (hi_fixup->fixp)) | |
4d7206a2 | 4866 | { |
9fe77896 RS |
4867 | hi_fixup = ((struct mips_hi_fixup *) |
4868 | xmalloc (sizeof (struct mips_hi_fixup))); | |
4869 | hi_fixup->next = mips_hi_fixup_list; | |
4870 | mips_hi_fixup_list = hi_fixup; | |
4d7206a2 | 4871 | } |
9fe77896 RS |
4872 | hi_fixup->fixp = ip->fixp[0]; |
4873 | hi_fixup->seg = now_seg; | |
4874 | } | |
252b5132 | 4875 | |
9fe77896 RS |
4876 | /* Add fixups for the second and third relocations, if given. |
4877 | Note that the ABI allows the second relocation to be | |
4878 | against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the | |
4879 | moment we only use RSS_UNDEF, but we could add support | |
4880 | for the others if it ever becomes necessary. */ | |
4881 | for (i = 1; i < 3; i++) | |
4882 | if (reloc_type[i] != BFD_RELOC_UNUSED) | |
4883 | { | |
4884 | ip->fixp[i] = fix_new (ip->frag, ip->where, | |
4885 | ip->fixp[0]->fx_size, NULL, 0, | |
df58fc94 | 4886 | FALSE, final_type[i]); |
f6688943 | 4887 | |
9fe77896 RS |
4888 | /* Use fx_tcbit to mark compound relocs. */ |
4889 | ip->fixp[0]->fx_tcbit = 1; | |
4890 | ip->fixp[i]->fx_tcbit = 1; | |
4891 | } | |
252b5132 | 4892 | } |
1e915849 | 4893 | install_insn (ip); |
252b5132 RH |
4894 | |
4895 | /* Update the register mask information. */ | |
4c260379 RS |
4896 | mips_gprmask |= gpr_read_mask (ip) | gpr_write_mask (ip); |
4897 | mips_cprmask[1] |= fpr_read_mask (ip) | fpr_write_mask (ip); | |
252b5132 | 4898 | |
a4e06468 | 4899 | switch (method) |
252b5132 | 4900 | { |
a4e06468 RS |
4901 | case APPEND_ADD: |
4902 | insert_into_history (0, 1, ip); | |
4903 | break; | |
4904 | ||
4905 | case APPEND_ADD_WITH_NOP: | |
14fe068b RS |
4906 | { |
4907 | struct mips_cl_insn *nop; | |
4908 | ||
4909 | insert_into_history (0, 1, ip); | |
4910 | nop = get_delay_slot_nop (ip); | |
4911 | add_fixed_insn (nop); | |
4912 | insert_into_history (0, 1, nop); | |
4913 | if (mips_relax.sequence) | |
4914 | mips_relax.sizes[mips_relax.sequence - 1] += insn_length (nop); | |
4915 | } | |
a4e06468 RS |
4916 | break; |
4917 | ||
4918 | case APPEND_ADD_COMPACT: | |
4919 | /* Convert MIPS16 jr/jalr into a "compact" jump. */ | |
4920 | gas_assert (mips_opts.mips16); | |
4921 | ip->insn_opcode |= 0x0080; | |
4922 | find_altered_mips16_opcode (ip); | |
4923 | install_insn (ip); | |
4924 | insert_into_history (0, 1, ip); | |
4925 | break; | |
4926 | ||
4927 | case APPEND_SWAP: | |
4928 | { | |
4929 | struct mips_cl_insn delay = history[0]; | |
4930 | if (mips_opts.mips16) | |
4931 | { | |
4932 | know (delay.frag == ip->frag); | |
4933 | move_insn (ip, delay.frag, delay.where); | |
4934 | move_insn (&delay, ip->frag, ip->where + insn_length (ip)); | |
4935 | } | |
464ab0e5 | 4936 | else if (relaxed_branch || delay.frag != ip->frag) |
a4e06468 RS |
4937 | { |
4938 | /* Add the delay slot instruction to the end of the | |
4939 | current frag and shrink the fixed part of the | |
4940 | original frag. If the branch occupies the tail of | |
4941 | the latter, move it backwards to cover the gap. */ | |
2b0c8b40 | 4942 | delay.frag->fr_fix -= branch_disp; |
a4e06468 | 4943 | if (delay.frag == ip->frag) |
2b0c8b40 | 4944 | move_insn (ip, ip->frag, ip->where - branch_disp); |
a4e06468 RS |
4945 | add_fixed_insn (&delay); |
4946 | } | |
4947 | else | |
4948 | { | |
2b0c8b40 MR |
4949 | move_insn (&delay, ip->frag, |
4950 | ip->where - branch_disp + insn_length (ip)); | |
a4e06468 RS |
4951 | move_insn (ip, history[0].frag, history[0].where); |
4952 | } | |
4953 | history[0] = *ip; | |
4954 | delay.fixed_p = 1; | |
4955 | insert_into_history (0, 1, &delay); | |
4956 | } | |
4957 | break; | |
252b5132 RH |
4958 | } |
4959 | ||
13408f1e | 4960 | /* If we have just completed an unconditional branch, clear the history. */ |
11625dd8 RS |
4961 | if ((delayed_branch_p (&history[1]) && uncond_branch_p (&history[1])) |
4962 | || (compact_branch_p (&history[0]) && uncond_branch_p (&history[0]))) | |
e407c74b NC |
4963 | { |
4964 | unsigned int i; | |
4965 | ||
79850f26 | 4966 | mips_no_prev_insn (); |
13408f1e | 4967 | |
e407c74b | 4968 | for (i = 0; i < ARRAY_SIZE (history); i++) |
79850f26 | 4969 | history[i].cleared_p = 1; |
e407c74b NC |
4970 | } |
4971 | ||
df58fc94 RS |
4972 | /* We need to emit a label at the end of branch-likely macros. */ |
4973 | if (emit_branch_likely_macro) | |
4974 | { | |
4975 | emit_branch_likely_macro = FALSE; | |
4976 | micromips_add_label (); | |
4977 | } | |
4978 | ||
252b5132 RH |
4979 | /* We just output an insn, so the next one doesn't have a label. */ |
4980 | mips_clear_insn_labels (); | |
252b5132 RH |
4981 | } |
4982 | ||
e407c74b NC |
4983 | /* Forget that there was any previous instruction or label. |
4984 | When BRANCH is true, the branch history is also flushed. */ | |
252b5132 RH |
4985 | |
4986 | static void | |
7d10b47d | 4987 | mips_no_prev_insn (void) |
252b5132 | 4988 | { |
7d10b47d RS |
4989 | prev_nop_frag = NULL; |
4990 | insert_into_history (0, ARRAY_SIZE (history), NOP_INSN); | |
252b5132 RH |
4991 | mips_clear_insn_labels (); |
4992 | } | |
4993 | ||
7d10b47d RS |
4994 | /* This function must be called before we emit something other than |
4995 | instructions. It is like mips_no_prev_insn except that it inserts | |
4996 | any NOPS that might be needed by previous instructions. */ | |
252b5132 | 4997 | |
7d10b47d RS |
4998 | void |
4999 | mips_emit_delays (void) | |
252b5132 RH |
5000 | { |
5001 | if (! mips_opts.noreorder) | |
5002 | { | |
932d1a1b | 5003 | int nops = nops_for_insn (0, history, NULL); |
252b5132 RH |
5004 | if (nops > 0) |
5005 | { | |
7d10b47d RS |
5006 | while (nops-- > 0) |
5007 | add_fixed_insn (NOP_INSN); | |
462427c4 | 5008 | mips_move_text_labels (); |
7d10b47d RS |
5009 | } |
5010 | } | |
5011 | mips_no_prev_insn (); | |
5012 | } | |
5013 | ||
5014 | /* Start a (possibly nested) noreorder block. */ | |
5015 | ||
5016 | static void | |
5017 | start_noreorder (void) | |
5018 | { | |
5019 | if (mips_opts.noreorder == 0) | |
5020 | { | |
5021 | unsigned int i; | |
5022 | int nops; | |
5023 | ||
5024 | /* None of the instructions before the .set noreorder can be moved. */ | |
5025 | for (i = 0; i < ARRAY_SIZE (history); i++) | |
5026 | history[i].fixed_p = 1; | |
5027 | ||
5028 | /* Insert any nops that might be needed between the .set noreorder | |
5029 | block and the previous instructions. We will later remove any | |
5030 | nops that turn out not to be needed. */ | |
932d1a1b | 5031 | nops = nops_for_insn (0, history, NULL); |
7d10b47d RS |
5032 | if (nops > 0) |
5033 | { | |
5034 | if (mips_optimize != 0) | |
252b5132 RH |
5035 | { |
5036 | /* Record the frag which holds the nop instructions, so | |
5037 | that we can remove them if we don't need them. */ | |
df58fc94 | 5038 | frag_grow (nops * NOP_INSN_SIZE); |
252b5132 RH |
5039 | prev_nop_frag = frag_now; |
5040 | prev_nop_frag_holds = nops; | |
5041 | prev_nop_frag_required = 0; | |
5042 | prev_nop_frag_since = 0; | |
5043 | } | |
5044 | ||
5045 | for (; nops > 0; --nops) | |
1e915849 | 5046 | add_fixed_insn (NOP_INSN); |
252b5132 | 5047 | |
7d10b47d RS |
5048 | /* Move on to a new frag, so that it is safe to simply |
5049 | decrease the size of prev_nop_frag. */ | |
5050 | frag_wane (frag_now); | |
5051 | frag_new (0); | |
462427c4 | 5052 | mips_move_text_labels (); |
252b5132 | 5053 | } |
df58fc94 | 5054 | mips_mark_labels (); |
7d10b47d | 5055 | mips_clear_insn_labels (); |
252b5132 | 5056 | } |
7d10b47d RS |
5057 | mips_opts.noreorder++; |
5058 | mips_any_noreorder = 1; | |
5059 | } | |
252b5132 | 5060 | |
7d10b47d | 5061 | /* End a nested noreorder block. */ |
252b5132 | 5062 | |
7d10b47d RS |
5063 | static void |
5064 | end_noreorder (void) | |
5065 | { | |
5066 | mips_opts.noreorder--; | |
5067 | if (mips_opts.noreorder == 0 && prev_nop_frag != NULL) | |
5068 | { | |
5069 | /* Commit to inserting prev_nop_frag_required nops and go back to | |
5070 | handling nop insertion the .set reorder way. */ | |
5071 | prev_nop_frag->fr_fix -= ((prev_nop_frag_holds - prev_nop_frag_required) | |
df58fc94 | 5072 | * NOP_INSN_SIZE); |
7d10b47d RS |
5073 | insert_into_history (prev_nop_frag_since, |
5074 | prev_nop_frag_required, NOP_INSN); | |
5075 | prev_nop_frag = NULL; | |
5076 | } | |
252b5132 RH |
5077 | } |
5078 | ||
584892a6 RS |
5079 | /* Set up global variables for the start of a new macro. */ |
5080 | ||
5081 | static void | |
5082 | macro_start (void) | |
5083 | { | |
5084 | memset (&mips_macro_warning.sizes, 0, sizeof (mips_macro_warning.sizes)); | |
df58fc94 RS |
5085 | memset (&mips_macro_warning.first_insn_sizes, 0, |
5086 | sizeof (mips_macro_warning.first_insn_sizes)); | |
5087 | memset (&mips_macro_warning.insns, 0, sizeof (mips_macro_warning.insns)); | |
584892a6 | 5088 | mips_macro_warning.delay_slot_p = (mips_opts.noreorder |
11625dd8 | 5089 | && delayed_branch_p (&history[0])); |
df58fc94 RS |
5090 | switch (history[0].insn_mo->pinfo2 |
5091 | & (INSN2_BRANCH_DELAY_32BIT | INSN2_BRANCH_DELAY_16BIT)) | |
5092 | { | |
5093 | case INSN2_BRANCH_DELAY_32BIT: | |
5094 | mips_macro_warning.delay_slot_length = 4; | |
5095 | break; | |
5096 | case INSN2_BRANCH_DELAY_16BIT: | |
5097 | mips_macro_warning.delay_slot_length = 2; | |
5098 | break; | |
5099 | default: | |
5100 | mips_macro_warning.delay_slot_length = 0; | |
5101 | break; | |
5102 | } | |
5103 | mips_macro_warning.first_frag = NULL; | |
584892a6 RS |
5104 | } |
5105 | ||
df58fc94 RS |
5106 | /* Given that a macro is longer than one instruction or of the wrong size, |
5107 | return the appropriate warning for it. Return null if no warning is | |
5108 | needed. SUBTYPE is a bitmask of RELAX_DELAY_SLOT, RELAX_DELAY_SLOT_16BIT, | |
5109 | RELAX_DELAY_SLOT_SIZE_FIRST, RELAX_DELAY_SLOT_SIZE_SECOND, | |
5110 | and RELAX_NOMACRO. */ | |
584892a6 RS |
5111 | |
5112 | static const char * | |
5113 | macro_warning (relax_substateT subtype) | |
5114 | { | |
5115 | if (subtype & RELAX_DELAY_SLOT) | |
5116 | return _("Macro instruction expanded into multiple instructions" | |
5117 | " in a branch delay slot"); | |
5118 | else if (subtype & RELAX_NOMACRO) | |
5119 | return _("Macro instruction expanded into multiple instructions"); | |
df58fc94 RS |
5120 | else if (subtype & (RELAX_DELAY_SLOT_SIZE_FIRST |
5121 | | RELAX_DELAY_SLOT_SIZE_SECOND)) | |
5122 | return ((subtype & RELAX_DELAY_SLOT_16BIT) | |
5123 | ? _("Macro instruction expanded into a wrong size instruction" | |
5124 | " in a 16-bit branch delay slot") | |
5125 | : _("Macro instruction expanded into a wrong size instruction" | |
5126 | " in a 32-bit branch delay slot")); | |
584892a6 RS |
5127 | else |
5128 | return 0; | |
5129 | } | |
5130 | ||
5131 | /* Finish up a macro. Emit warnings as appropriate. */ | |
5132 | ||
5133 | static void | |
5134 | macro_end (void) | |
5135 | { | |
df58fc94 RS |
5136 | /* Relaxation warning flags. */ |
5137 | relax_substateT subtype = 0; | |
5138 | ||
5139 | /* Check delay slot size requirements. */ | |
5140 | if (mips_macro_warning.delay_slot_length == 2) | |
5141 | subtype |= RELAX_DELAY_SLOT_16BIT; | |
5142 | if (mips_macro_warning.delay_slot_length != 0) | |
584892a6 | 5143 | { |
df58fc94 RS |
5144 | if (mips_macro_warning.delay_slot_length |
5145 | != mips_macro_warning.first_insn_sizes[0]) | |
5146 | subtype |= RELAX_DELAY_SLOT_SIZE_FIRST; | |
5147 | if (mips_macro_warning.delay_slot_length | |
5148 | != mips_macro_warning.first_insn_sizes[1]) | |
5149 | subtype |= RELAX_DELAY_SLOT_SIZE_SECOND; | |
5150 | } | |
584892a6 | 5151 | |
df58fc94 RS |
5152 | /* Check instruction count requirements. */ |
5153 | if (mips_macro_warning.insns[0] > 1 || mips_macro_warning.insns[1] > 1) | |
5154 | { | |
5155 | if (mips_macro_warning.insns[1] > mips_macro_warning.insns[0]) | |
584892a6 RS |
5156 | subtype |= RELAX_SECOND_LONGER; |
5157 | if (mips_opts.warn_about_macros) | |
5158 | subtype |= RELAX_NOMACRO; | |
5159 | if (mips_macro_warning.delay_slot_p) | |
5160 | subtype |= RELAX_DELAY_SLOT; | |
df58fc94 | 5161 | } |
584892a6 | 5162 | |
df58fc94 RS |
5163 | /* If both alternatives fail to fill a delay slot correctly, |
5164 | emit the warning now. */ | |
5165 | if ((subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0 | |
5166 | && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0) | |
5167 | { | |
5168 | relax_substateT s; | |
5169 | const char *msg; | |
5170 | ||
5171 | s = subtype & (RELAX_DELAY_SLOT_16BIT | |
5172 | | RELAX_DELAY_SLOT_SIZE_FIRST | |
5173 | | RELAX_DELAY_SLOT_SIZE_SECOND); | |
5174 | msg = macro_warning (s); | |
5175 | if (msg != NULL) | |
5176 | as_warn ("%s", msg); | |
5177 | subtype &= ~s; | |
5178 | } | |
5179 | ||
5180 | /* If both implementations are longer than 1 instruction, then emit the | |
5181 | warning now. */ | |
5182 | if (mips_macro_warning.insns[0] > 1 && mips_macro_warning.insns[1] > 1) | |
5183 | { | |
5184 | relax_substateT s; | |
5185 | const char *msg; | |
5186 | ||
5187 | s = subtype & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT); | |
5188 | msg = macro_warning (s); | |
5189 | if (msg != NULL) | |
5190 | as_warn ("%s", msg); | |
5191 | subtype &= ~s; | |
584892a6 | 5192 | } |
df58fc94 RS |
5193 | |
5194 | /* If any flags still set, then one implementation might need a warning | |
5195 | and the other either will need one of a different kind or none at all. | |
5196 | Pass any remaining flags over to relaxation. */ | |
5197 | if (mips_macro_warning.first_frag != NULL) | |
5198 | mips_macro_warning.first_frag->fr_subtype |= subtype; | |
584892a6 RS |
5199 | } |
5200 | ||
df58fc94 RS |
5201 | /* Instruction operand formats used in macros that vary between |
5202 | standard MIPS and microMIPS code. */ | |
5203 | ||
5204 | static const char * const brk_fmt[2] = { "c", "mF" }; | |
5205 | static const char * const cop12_fmt[2] = { "E,o(b)", "E,~(b)" }; | |
5206 | static const char * const jalr_fmt[2] = { "d,s", "t,s" }; | |
5207 | static const char * const lui_fmt[2] = { "t,u", "s,u" }; | |
5208 | static const char * const mem12_fmt[2] = { "t,o(b)", "t,~(b)" }; | |
5209 | static const char * const mfhl_fmt[2] = { "d", "mj" }; | |
5210 | static const char * const shft_fmt[2] = { "d,w,<", "t,r,<" }; | |
5211 | static const char * const trap_fmt[2] = { "s,t,q", "s,t,|" }; | |
5212 | ||
5213 | #define BRK_FMT (brk_fmt[mips_opts.micromips]) | |
5214 | #define COP12_FMT (cop12_fmt[mips_opts.micromips]) | |
5215 | #define JALR_FMT (jalr_fmt[mips_opts.micromips]) | |
5216 | #define LUI_FMT (lui_fmt[mips_opts.micromips]) | |
5217 | #define MEM12_FMT (mem12_fmt[mips_opts.micromips]) | |
5218 | #define MFHL_FMT (mfhl_fmt[mips_opts.micromips]) | |
5219 | #define SHFT_FMT (shft_fmt[mips_opts.micromips]) | |
5220 | #define TRAP_FMT (trap_fmt[mips_opts.micromips]) | |
5221 | ||
6e1304d8 RS |
5222 | /* Read a macro's relocation codes from *ARGS and store them in *R. |
5223 | The first argument in *ARGS will be either the code for a single | |
5224 | relocation or -1 followed by the three codes that make up a | |
5225 | composite relocation. */ | |
5226 | ||
5227 | static void | |
5228 | macro_read_relocs (va_list *args, bfd_reloc_code_real_type *r) | |
5229 | { | |
5230 | int i, next; | |
5231 | ||
5232 | next = va_arg (*args, int); | |
5233 | if (next >= 0) | |
5234 | r[0] = (bfd_reloc_code_real_type) next; | |
5235 | else | |
5236 | for (i = 0; i < 3; i++) | |
5237 | r[i] = (bfd_reloc_code_real_type) va_arg (*args, int); | |
5238 | } | |
5239 | ||
252b5132 RH |
5240 | /* Build an instruction created by a macro expansion. This is passed |
5241 | a pointer to the count of instructions created so far, an | |
5242 | expression, the name of the instruction to build, an operand format | |
5243 | string, and corresponding arguments. */ | |
5244 | ||
252b5132 | 5245 | static void |
67c0d1eb | 5246 | macro_build (expressionS *ep, const char *name, const char *fmt, ...) |
252b5132 | 5247 | { |
df58fc94 | 5248 | const struct mips_opcode *mo = NULL; |
f6688943 | 5249 | bfd_reloc_code_real_type r[3]; |
df58fc94 RS |
5250 | const struct mips_opcode *amo; |
5251 | struct hash_control *hash; | |
5252 | struct mips_cl_insn insn; | |
252b5132 | 5253 | va_list args; |
252b5132 | 5254 | |
252b5132 | 5255 | va_start (args, fmt); |
252b5132 | 5256 | |
252b5132 RH |
5257 | if (mips_opts.mips16) |
5258 | { | |
03ea81db | 5259 | mips16_macro_build (ep, name, fmt, &args); |
252b5132 RH |
5260 | va_end (args); |
5261 | return; | |
5262 | } | |
5263 | ||
f6688943 TS |
5264 | r[0] = BFD_RELOC_UNUSED; |
5265 | r[1] = BFD_RELOC_UNUSED; | |
5266 | r[2] = BFD_RELOC_UNUSED; | |
df58fc94 RS |
5267 | hash = mips_opts.micromips ? micromips_op_hash : op_hash; |
5268 | amo = (struct mips_opcode *) hash_find (hash, name); | |
5269 | gas_assert (amo); | |
5270 | gas_assert (strcmp (name, amo->name) == 0); | |
1e915849 | 5271 | |
df58fc94 | 5272 | do |
8b082fb1 TS |
5273 | { |
5274 | /* Search until we get a match for NAME. It is assumed here that | |
df58fc94 RS |
5275 | macros will never generate MDMX, MIPS-3D, or MT instructions. |
5276 | We try to match an instruction that fulfils the branch delay | |
5277 | slot instruction length requirement (if any) of the previous | |
5278 | instruction. While doing this we record the first instruction | |
5279 | seen that matches all the other conditions and use it anyway | |
5280 | if the requirement cannot be met; we will issue an appropriate | |
5281 | warning later on. */ | |
5282 | if (strcmp (fmt, amo->args) == 0 | |
5283 | && amo->pinfo != INSN_MACRO | |
5284 | && is_opcode_valid (amo) | |
5285 | && is_size_valid (amo)) | |
5286 | { | |
5287 | if (is_delay_slot_valid (amo)) | |
5288 | { | |
5289 | mo = amo; | |
5290 | break; | |
5291 | } | |
5292 | else if (!mo) | |
5293 | mo = amo; | |
5294 | } | |
8b082fb1 | 5295 | |
df58fc94 RS |
5296 | ++amo; |
5297 | gas_assert (amo->name); | |
252b5132 | 5298 | } |
df58fc94 | 5299 | while (strcmp (name, amo->name) == 0); |
252b5132 | 5300 | |
df58fc94 | 5301 | gas_assert (mo); |
1e915849 | 5302 | create_insn (&insn, mo); |
252b5132 RH |
5303 | for (;;) |
5304 | { | |
5305 | switch (*fmt++) | |
5306 | { | |
5307 | case '\0': | |
5308 | break; | |
5309 | ||
5310 | case ',': | |
5311 | case '(': | |
5312 | case ')': | |
5313 | continue; | |
5314 | ||
5f74bc13 CD |
5315 | case '+': |
5316 | switch (*fmt++) | |
5317 | { | |
5318 | case 'A': | |
5319 | case 'E': | |
df58fc94 RS |
5320 | INSERT_OPERAND (mips_opts.micromips, |
5321 | EXTLSB, insn, va_arg (args, int)); | |
5f74bc13 CD |
5322 | continue; |
5323 | ||
5324 | case 'B': | |
5325 | case 'F': | |
5326 | /* Note that in the macro case, these arguments are already | |
5327 | in MSB form. (When handling the instruction in the | |
5328 | non-macro case, these arguments are sizes from which | |
5329 | MSB values must be calculated.) */ | |
df58fc94 RS |
5330 | INSERT_OPERAND (mips_opts.micromips, |
5331 | INSMSB, insn, va_arg (args, int)); | |
5f74bc13 CD |
5332 | continue; |
5333 | ||
b015e599 AP |
5334 | case 'J': |
5335 | gas_assert (!mips_opts.micromips); | |
5336 | INSERT_OPERAND (0, CODE10, insn, va_arg (args, int)); | |
5337 | continue; | |
5338 | ||
5f74bc13 CD |
5339 | case 'C': |
5340 | case 'G': | |
5341 | case 'H': | |
5342 | /* Note that in the macro case, these arguments are already | |
5343 | in MSBD form. (When handling the instruction in the | |
5344 | non-macro case, these arguments are sizes from which | |
5345 | MSBD values must be calculated.) */ | |
df58fc94 RS |
5346 | INSERT_OPERAND (mips_opts.micromips, |
5347 | EXTMSBD, insn, va_arg (args, int)); | |
5f74bc13 CD |
5348 | continue; |
5349 | ||
dd3cbb7e | 5350 | case 'Q': |
df58fc94 RS |
5351 | gas_assert (!mips_opts.micromips); |
5352 | INSERT_OPERAND (0, SEQI, insn, va_arg (args, int)); | |
dd3cbb7e NC |
5353 | continue; |
5354 | ||
7f3c4072 CM |
5355 | case 'j': |
5356 | INSERT_OPERAND (mips_opts.micromips, EVAOFFSET, insn, va_arg (args, int)); | |
5357 | continue; | |
5358 | ||
5f74bc13 | 5359 | default: |
b37df7c4 | 5360 | abort (); |
5f74bc13 CD |
5361 | } |
5362 | continue; | |
5363 | ||
8b082fb1 | 5364 | case '2': |
03f66e8a | 5365 | INSERT_OPERAND (mips_opts.micromips, BP, insn, va_arg (args, int)); |
8b082fb1 TS |
5366 | continue; |
5367 | ||
df58fc94 RS |
5368 | case 'n': |
5369 | gas_assert (mips_opts.micromips); | |
252b5132 RH |
5370 | case 't': |
5371 | case 'w': | |
5372 | case 'E': | |
df58fc94 | 5373 | INSERT_OPERAND (mips_opts.micromips, RT, insn, va_arg (args, int)); |
252b5132 RH |
5374 | continue; |
5375 | ||
5376 | case 'c': | |
df58fc94 RS |
5377 | gas_assert (!mips_opts.micromips); |
5378 | INSERT_OPERAND (0, CODE, insn, va_arg (args, int)); | |
38487616 TS |
5379 | continue; |
5380 | ||
252b5132 | 5381 | case 'W': |
df58fc94 RS |
5382 | gas_assert (!mips_opts.micromips); |
5383 | case 'T': | |
5384 | INSERT_OPERAND (mips_opts.micromips, FT, insn, va_arg (args, int)); | |
252b5132 RH |
5385 | continue; |
5386 | ||
252b5132 | 5387 | case 'G': |
df58fc94 RS |
5388 | if (mips_opts.micromips) |
5389 | INSERT_OPERAND (1, RS, insn, va_arg (args, int)); | |
5390 | else | |
5391 | INSERT_OPERAND (0, RD, insn, va_arg (args, int)); | |
5392 | continue; | |
5393 | ||
af7ee8bf | 5394 | case 'K': |
df58fc94 RS |
5395 | gas_assert (!mips_opts.micromips); |
5396 | case 'd': | |
5397 | INSERT_OPERAND (mips_opts.micromips, RD, insn, va_arg (args, int)); | |
252b5132 RH |
5398 | continue; |
5399 | ||
4372b673 | 5400 | case 'U': |
df58fc94 | 5401 | gas_assert (!mips_opts.micromips); |
4372b673 NC |
5402 | { |
5403 | int tmp = va_arg (args, int); | |
5404 | ||
df58fc94 RS |
5405 | INSERT_OPERAND (0, RT, insn, tmp); |
5406 | INSERT_OPERAND (0, RD, insn, tmp); | |
4372b673 | 5407 | } |
df58fc94 | 5408 | continue; |
4372b673 | 5409 | |
252b5132 RH |
5410 | case 'V': |
5411 | case 'S': | |
df58fc94 RS |
5412 | gas_assert (!mips_opts.micromips); |
5413 | INSERT_OPERAND (0, FS, insn, va_arg (args, int)); | |
252b5132 RH |
5414 | continue; |
5415 | ||
5416 | case 'z': | |
5417 | continue; | |
5418 | ||
5419 | case '<': | |
df58fc94 RS |
5420 | INSERT_OPERAND (mips_opts.micromips, |
5421 | SHAMT, insn, va_arg (args, int)); | |
252b5132 RH |
5422 | continue; |
5423 | ||
5424 | case 'D': | |
df58fc94 RS |
5425 | gas_assert (!mips_opts.micromips); |
5426 | INSERT_OPERAND (0, FD, insn, va_arg (args, int)); | |
252b5132 RH |
5427 | continue; |
5428 | ||
5429 | case 'B': | |
df58fc94 RS |
5430 | gas_assert (!mips_opts.micromips); |
5431 | INSERT_OPERAND (0, CODE20, insn, va_arg (args, int)); | |
252b5132 RH |
5432 | continue; |
5433 | ||
4372b673 | 5434 | case 'J': |
df58fc94 RS |
5435 | gas_assert (!mips_opts.micromips); |
5436 | INSERT_OPERAND (0, CODE19, insn, va_arg (args, int)); | |
4372b673 NC |
5437 | continue; |
5438 | ||
252b5132 | 5439 | case 'q': |
df58fc94 RS |
5440 | gas_assert (!mips_opts.micromips); |
5441 | INSERT_OPERAND (0, CODE2, insn, va_arg (args, int)); | |
252b5132 RH |
5442 | continue; |
5443 | ||
5444 | case 'b': | |
5445 | case 's': | |
5446 | case 'r': | |
5447 | case 'v': | |
df58fc94 | 5448 | INSERT_OPERAND (mips_opts.micromips, RS, insn, va_arg (args, int)); |
252b5132 RH |
5449 | continue; |
5450 | ||
5451 | case 'i': | |
5452 | case 'j': | |
6e1304d8 | 5453 | macro_read_relocs (&args, r); |
9c2799c2 | 5454 | gas_assert (*r == BFD_RELOC_GPREL16 |
e391c024 RS |
5455 | || *r == BFD_RELOC_MIPS_HIGHER |
5456 | || *r == BFD_RELOC_HI16_S | |
5457 | || *r == BFD_RELOC_LO16 | |
5458 | || *r == BFD_RELOC_MIPS_GOT_OFST); | |
5459 | continue; | |
5460 | ||
5461 | case 'o': | |
5462 | macro_read_relocs (&args, r); | |
252b5132 RH |
5463 | continue; |
5464 | ||
5465 | case 'u': | |
6e1304d8 | 5466 | macro_read_relocs (&args, r); |
9c2799c2 | 5467 | gas_assert (ep != NULL |
90ecf173 MR |
5468 | && (ep->X_op == O_constant |
5469 | || (ep->X_op == O_symbol | |
5470 | && (*r == BFD_RELOC_MIPS_HIGHEST | |
5471 | || *r == BFD_RELOC_HI16_S | |
5472 | || *r == BFD_RELOC_HI16 | |
5473 | || *r == BFD_RELOC_GPREL16 | |
5474 | || *r == BFD_RELOC_MIPS_GOT_HI16 | |
5475 | || *r == BFD_RELOC_MIPS_CALL_HI16)))); | |
252b5132 RH |
5476 | continue; |
5477 | ||
5478 | case 'p': | |
9c2799c2 | 5479 | gas_assert (ep != NULL); |
bad36eac | 5480 | |
252b5132 RH |
5481 | /* |
5482 | * This allows macro() to pass an immediate expression for | |
5483 | * creating short branches without creating a symbol. | |
bad36eac DJ |
5484 | * |
5485 | * We don't allow branch relaxation for these branches, as | |
5486 | * they should only appear in ".set nomacro" anyway. | |
252b5132 RH |
5487 | */ |
5488 | if (ep->X_op == O_constant) | |
5489 | { | |
df58fc94 RS |
5490 | /* For microMIPS we always use relocations for branches. |
5491 | So we should not resolve immediate values. */ | |
5492 | gas_assert (!mips_opts.micromips); | |
5493 | ||
bad36eac DJ |
5494 | if ((ep->X_add_number & 3) != 0) |
5495 | as_bad (_("branch to misaligned address (0x%lx)"), | |
5496 | (unsigned long) ep->X_add_number); | |
5497 | if ((ep->X_add_number + 0x20000) & ~0x3ffff) | |
5498 | as_bad (_("branch address range overflow (0x%lx)"), | |
5499 | (unsigned long) ep->X_add_number); | |
252b5132 RH |
5500 | insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff; |
5501 | ep = NULL; | |
5502 | } | |
5503 | else | |
0b25d3e6 | 5504 | *r = BFD_RELOC_16_PCREL_S2; |
252b5132 RH |
5505 | continue; |
5506 | ||
5507 | case 'a': | |
9c2799c2 | 5508 | gas_assert (ep != NULL); |
f6688943 | 5509 | *r = BFD_RELOC_MIPS_JMP; |
252b5132 RH |
5510 | continue; |
5511 | ||
5512 | case 'C': | |
df58fc94 RS |
5513 | gas_assert (!mips_opts.micromips); |
5514 | INSERT_OPERAND (0, COPZ, insn, va_arg (args, unsigned long)); | |
252b5132 RH |
5515 | continue; |
5516 | ||
d43b4baf | 5517 | case 'k': |
df58fc94 RS |
5518 | INSERT_OPERAND (mips_opts.micromips, |
5519 | CACHE, insn, va_arg (args, unsigned long)); | |
5520 | continue; | |
5521 | ||
5522 | case '|': | |
5523 | gas_assert (mips_opts.micromips); | |
5524 | INSERT_OPERAND (1, TRAP, insn, va_arg (args, int)); | |
5525 | continue; | |
5526 | ||
5527 | case '.': | |
5528 | gas_assert (mips_opts.micromips); | |
5529 | INSERT_OPERAND (1, OFFSET10, insn, va_arg (args, int)); | |
5530 | continue; | |
5531 | ||
dec0624d MR |
5532 | case '\\': |
5533 | INSERT_OPERAND (mips_opts.micromips, | |
5534 | 3BITPOS, insn, va_arg (args, unsigned int)); | |
5535 | continue; | |
5536 | ||
df58fc94 | 5537 | case '~': |
dec0624d MR |
5538 | INSERT_OPERAND (mips_opts.micromips, |
5539 | OFFSET12, insn, va_arg (args, unsigned long)); | |
df58fc94 RS |
5540 | continue; |
5541 | ||
5542 | case 'N': | |
5543 | gas_assert (mips_opts.micromips); | |
5544 | INSERT_OPERAND (1, BCC, insn, va_arg (args, int)); | |
5545 | continue; | |
5546 | ||
5547 | case 'm': /* Opcode extension character. */ | |
5548 | gas_assert (mips_opts.micromips); | |
5549 | switch (*fmt++) | |
5550 | { | |
5551 | case 'j': | |
5552 | INSERT_OPERAND (1, MJ, insn, va_arg (args, int)); | |
5553 | break; | |
5554 | ||
5555 | case 'p': | |
5556 | INSERT_OPERAND (1, MP, insn, va_arg (args, int)); | |
5557 | break; | |
5558 | ||
5559 | case 'F': | |
5560 | INSERT_OPERAND (1, IMMF, insn, va_arg (args, int)); | |
5561 | break; | |
5562 | ||
5563 | default: | |
b37df7c4 | 5564 | abort (); |
df58fc94 | 5565 | } |
d43b4baf TS |
5566 | continue; |
5567 | ||
252b5132 | 5568 | default: |
b37df7c4 | 5569 | abort (); |
252b5132 RH |
5570 | } |
5571 | break; | |
5572 | } | |
5573 | va_end (args); | |
9c2799c2 | 5574 | gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
252b5132 | 5575 | |
df58fc94 | 5576 | append_insn (&insn, ep, r, TRUE); |
252b5132 RH |
5577 | } |
5578 | ||
5579 | static void | |
67c0d1eb | 5580 | mips16_macro_build (expressionS *ep, const char *name, const char *fmt, |
03ea81db | 5581 | va_list *args) |
252b5132 | 5582 | { |
1e915849 | 5583 | struct mips_opcode *mo; |
252b5132 | 5584 | struct mips_cl_insn insn; |
f6688943 TS |
5585 | bfd_reloc_code_real_type r[3] |
5586 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 5587 | |
1e915849 | 5588 | mo = (struct mips_opcode *) hash_find (mips16_op_hash, name); |
9c2799c2 NC |
5589 | gas_assert (mo); |
5590 | gas_assert (strcmp (name, mo->name) == 0); | |
252b5132 | 5591 | |
1e915849 | 5592 | while (strcmp (fmt, mo->args) != 0 || mo->pinfo == INSN_MACRO) |
252b5132 | 5593 | { |
1e915849 | 5594 | ++mo; |
9c2799c2 NC |
5595 | gas_assert (mo->name); |
5596 | gas_assert (strcmp (name, mo->name) == 0); | |
252b5132 RH |
5597 | } |
5598 | ||
1e915849 | 5599 | create_insn (&insn, mo); |
252b5132 RH |
5600 | for (;;) |
5601 | { | |
5602 | int c; | |
5603 | ||
5604 | c = *fmt++; | |
5605 | switch (c) | |
5606 | { | |
5607 | case '\0': | |
5608 | break; | |
5609 | ||
5610 | case ',': | |
5611 | case '(': | |
5612 | case ')': | |
5613 | continue; | |
5614 | ||
5615 | case 'y': | |
5616 | case 'w': | |
03ea81db | 5617 | MIPS16_INSERT_OPERAND (RY, insn, va_arg (*args, int)); |
252b5132 RH |
5618 | continue; |
5619 | ||
5620 | case 'x': | |
5621 | case 'v': | |
03ea81db | 5622 | MIPS16_INSERT_OPERAND (RX, insn, va_arg (*args, int)); |
252b5132 RH |
5623 | continue; |
5624 | ||
5625 | case 'z': | |
03ea81db | 5626 | MIPS16_INSERT_OPERAND (RZ, insn, va_arg (*args, int)); |
252b5132 RH |
5627 | continue; |
5628 | ||
5629 | case 'Z': | |
03ea81db | 5630 | MIPS16_INSERT_OPERAND (MOVE32Z, insn, va_arg (*args, int)); |
252b5132 RH |
5631 | continue; |
5632 | ||
5633 | case '0': | |
5634 | case 'S': | |
5635 | case 'P': | |
5636 | case 'R': | |
5637 | continue; | |
5638 | ||
5639 | case 'X': | |
03ea81db | 5640 | MIPS16_INSERT_OPERAND (REGR32, insn, va_arg (*args, int)); |
252b5132 RH |
5641 | continue; |
5642 | ||
5643 | case 'Y': | |
5644 | { | |
5645 | int regno; | |
5646 | ||
03ea81db | 5647 | regno = va_arg (*args, int); |
252b5132 | 5648 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); |
a9e24354 | 5649 | MIPS16_INSERT_OPERAND (REG32R, insn, regno); |
252b5132 RH |
5650 | } |
5651 | continue; | |
5652 | ||
5653 | case '<': | |
5654 | case '>': | |
5655 | case '4': | |
5656 | case '5': | |
5657 | case 'H': | |
5658 | case 'W': | |
5659 | case 'D': | |
5660 | case 'j': | |
5661 | case '8': | |
5662 | case 'V': | |
5663 | case 'C': | |
5664 | case 'U': | |
5665 | case 'k': | |
5666 | case 'K': | |
5667 | case 'p': | |
5668 | case 'q': | |
5669 | { | |
b886a2ab RS |
5670 | offsetT value; |
5671 | ||
9c2799c2 | 5672 | gas_assert (ep != NULL); |
252b5132 RH |
5673 | |
5674 | if (ep->X_op != O_constant) | |
874e8986 | 5675 | *r = (int) BFD_RELOC_UNUSED + c; |
b886a2ab | 5676 | else if (calculate_reloc (*r, ep->X_add_number, &value)) |
252b5132 | 5677 | { |
b886a2ab | 5678 | mips16_immed (NULL, 0, c, *r, value, 0, &insn.insn_opcode); |
252b5132 | 5679 | ep = NULL; |
f6688943 | 5680 | *r = BFD_RELOC_UNUSED; |
252b5132 RH |
5681 | } |
5682 | } | |
5683 | continue; | |
5684 | ||
5685 | case '6': | |
03ea81db | 5686 | MIPS16_INSERT_OPERAND (IMM6, insn, va_arg (*args, int)); |
252b5132 RH |
5687 | continue; |
5688 | } | |
5689 | ||
5690 | break; | |
5691 | } | |
5692 | ||
9c2799c2 | 5693 | gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
252b5132 | 5694 | |
df58fc94 | 5695 | append_insn (&insn, ep, r, TRUE); |
252b5132 RH |
5696 | } |
5697 | ||
2051e8c4 MR |
5698 | /* |
5699 | * Sign-extend 32-bit mode constants that have bit 31 set and all | |
5700 | * higher bits unset. | |
5701 | */ | |
9f872bbe | 5702 | static void |
2051e8c4 MR |
5703 | normalize_constant_expr (expressionS *ex) |
5704 | { | |
9ee2a2d4 | 5705 | if (ex->X_op == O_constant |
2051e8c4 MR |
5706 | && IS_ZEXT_32BIT_NUM (ex->X_add_number)) |
5707 | ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000) | |
5708 | - 0x80000000); | |
5709 | } | |
5710 | ||
5711 | /* | |
5712 | * Sign-extend 32-bit mode address offsets that have bit 31 set and | |
5713 | * all higher bits unset. | |
5714 | */ | |
5715 | static void | |
5716 | normalize_address_expr (expressionS *ex) | |
5717 | { | |
5718 | if (((ex->X_op == O_constant && HAVE_32BIT_ADDRESSES) | |
5719 | || (ex->X_op == O_symbol && HAVE_32BIT_SYMBOLS)) | |
5720 | && IS_ZEXT_32BIT_NUM (ex->X_add_number)) | |
5721 | ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000) | |
5722 | - 0x80000000); | |
5723 | } | |
5724 | ||
438c16b8 TS |
5725 | /* |
5726 | * Generate a "jalr" instruction with a relocation hint to the called | |
5727 | * function. This occurs in NewABI PIC code. | |
5728 | */ | |
5729 | static void | |
df58fc94 | 5730 | macro_build_jalr (expressionS *ep, int cprestore) |
438c16b8 | 5731 | { |
df58fc94 RS |
5732 | static const bfd_reloc_code_real_type jalr_relocs[2] |
5733 | = { BFD_RELOC_MIPS_JALR, BFD_RELOC_MICROMIPS_JALR }; | |
5734 | bfd_reloc_code_real_type jalr_reloc = jalr_relocs[mips_opts.micromips]; | |
5735 | const char *jalr; | |
685736be | 5736 | char *f = NULL; |
b34976b6 | 5737 | |
1180b5a4 | 5738 | if (MIPS_JALR_HINT_P (ep)) |
f21f8242 | 5739 | { |
cc3d92a5 | 5740 | frag_grow (8); |
f21f8242 AO |
5741 | f = frag_more (0); |
5742 | } | |
2906b037 | 5743 | if (mips_opts.micromips) |
df58fc94 RS |
5744 | { |
5745 | jalr = mips_opts.noreorder && !cprestore ? "jalr" : "jalrs"; | |
e64af278 MR |
5746 | if (MIPS_JALR_HINT_P (ep) |
5747 | || (history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) | |
df58fc94 RS |
5748 | macro_build (NULL, jalr, "t,s", RA, PIC_CALL_REG); |
5749 | else | |
5750 | macro_build (NULL, jalr, "mj", PIC_CALL_REG); | |
5751 | } | |
2906b037 MR |
5752 | else |
5753 | macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG); | |
1180b5a4 | 5754 | if (MIPS_JALR_HINT_P (ep)) |
df58fc94 | 5755 | fix_new_exp (frag_now, f - frag_now->fr_literal, 4, ep, FALSE, jalr_reloc); |
438c16b8 TS |
5756 | } |
5757 | ||
252b5132 RH |
5758 | /* |
5759 | * Generate a "lui" instruction. | |
5760 | */ | |
5761 | static void | |
67c0d1eb | 5762 | macro_build_lui (expressionS *ep, int regnum) |
252b5132 | 5763 | { |
9c2799c2 | 5764 | gas_assert (! mips_opts.mips16); |
252b5132 | 5765 | |
df58fc94 | 5766 | if (ep->X_op != O_constant) |
252b5132 | 5767 | { |
9c2799c2 | 5768 | gas_assert (ep->X_op == O_symbol); |
bbe506e8 TS |
5769 | /* _gp_disp is a special case, used from s_cpload. |
5770 | __gnu_local_gp is used if mips_no_shared. */ | |
9c2799c2 | 5771 | gas_assert (mips_pic == NO_PIC |
78e1bb40 | 5772 | || (! HAVE_NEWABI |
aa6975fb ILT |
5773 | && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0) |
5774 | || (! mips_in_shared | |
bbe506e8 TS |
5775 | && strcmp (S_GET_NAME (ep->X_add_symbol), |
5776 | "__gnu_local_gp") == 0)); | |
252b5132 RH |
5777 | } |
5778 | ||
df58fc94 | 5779 | macro_build (ep, "lui", LUI_FMT, regnum, BFD_RELOC_HI16_S); |
252b5132 RH |
5780 | } |
5781 | ||
885add95 CD |
5782 | /* Generate a sequence of instructions to do a load or store from a constant |
5783 | offset off of a base register (breg) into/from a target register (treg), | |
5784 | using AT if necessary. */ | |
5785 | static void | |
67c0d1eb RS |
5786 | macro_build_ldst_constoffset (expressionS *ep, const char *op, |
5787 | int treg, int breg, int dbl) | |
885add95 | 5788 | { |
9c2799c2 | 5789 | gas_assert (ep->X_op == O_constant); |
885add95 | 5790 | |
256ab948 | 5791 | /* Sign-extending 32-bit constants makes their handling easier. */ |
2051e8c4 MR |
5792 | if (!dbl) |
5793 | normalize_constant_expr (ep); | |
256ab948 | 5794 | |
67c1ffbe | 5795 | /* Right now, this routine can only handle signed 32-bit constants. */ |
ecd13cd3 | 5796 | if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000)) |
885add95 CD |
5797 | as_warn (_("operand overflow")); |
5798 | ||
5799 | if (IS_SEXT_16BIT_NUM(ep->X_add_number)) | |
5800 | { | |
5801 | /* Signed 16-bit offset will fit in the op. Easy! */ | |
67c0d1eb | 5802 | macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
885add95 CD |
5803 | } |
5804 | else | |
5805 | { | |
5806 | /* 32-bit offset, need multiple instructions and AT, like: | |
5807 | lui $tempreg,const_hi (BFD_RELOC_HI16_S) | |
5808 | addu $tempreg,$tempreg,$breg | |
5809 | <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16) | |
5810 | to handle the complete offset. */ | |
67c0d1eb RS |
5811 | macro_build_lui (ep, AT); |
5812 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); | |
5813 | macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, AT); | |
885add95 | 5814 | |
741fe287 | 5815 | if (!mips_opts.at) |
8fc2e39e | 5816 | as_bad (_("Macro used $at after \".set noat\"")); |
885add95 CD |
5817 | } |
5818 | } | |
5819 | ||
252b5132 RH |
5820 | /* set_at() |
5821 | * Generates code to set the $at register to true (one) | |
5822 | * if reg is less than the immediate expression. | |
5823 | */ | |
5824 | static void | |
67c0d1eb | 5825 | set_at (int reg, int unsignedp) |
252b5132 RH |
5826 | { |
5827 | if (imm_expr.X_op == O_constant | |
5828 | && imm_expr.X_add_number >= -0x8000 | |
5829 | && imm_expr.X_add_number < 0x8000) | |
67c0d1eb RS |
5830 | macro_build (&imm_expr, unsignedp ? "sltiu" : "slti", "t,r,j", |
5831 | AT, reg, BFD_RELOC_LO16); | |
252b5132 RH |
5832 | else |
5833 | { | |
67c0d1eb RS |
5834 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
5835 | macro_build (NULL, unsignedp ? "sltu" : "slt", "d,v,t", AT, reg, AT); | |
252b5132 RH |
5836 | } |
5837 | } | |
5838 | ||
5839 | /* Warn if an expression is not a constant. */ | |
5840 | ||
5841 | static void | |
17a2f251 | 5842 | check_absolute_expr (struct mips_cl_insn *ip, expressionS *ex) |
252b5132 RH |
5843 | { |
5844 | if (ex->X_op == O_big) | |
5845 | as_bad (_("unsupported large constant")); | |
5846 | else if (ex->X_op != O_constant) | |
9ee2a2d4 MR |
5847 | as_bad (_("Instruction %s requires absolute expression"), |
5848 | ip->insn_mo->name); | |
13757d0c | 5849 | |
9ee2a2d4 MR |
5850 | if (HAVE_32BIT_GPRS) |
5851 | normalize_constant_expr (ex); | |
252b5132 RH |
5852 | } |
5853 | ||
5854 | /* Count the leading zeroes by performing a binary chop. This is a | |
5855 | bulky bit of source, but performance is a LOT better for the | |
5856 | majority of values than a simple loop to count the bits: | |
5857 | for (lcnt = 0; (lcnt < 32); lcnt++) | |
5858 | if ((v) & (1 << (31 - lcnt))) | |
5859 | break; | |
5860 | However it is not code size friendly, and the gain will drop a bit | |
5861 | on certain cached systems. | |
5862 | */ | |
5863 | #define COUNT_TOP_ZEROES(v) \ | |
5864 | (((v) & ~0xffff) == 0 \ | |
5865 | ? ((v) & ~0xff) == 0 \ | |
5866 | ? ((v) & ~0xf) == 0 \ | |
5867 | ? ((v) & ~0x3) == 0 \ | |
5868 | ? ((v) & ~0x1) == 0 \ | |
5869 | ? !(v) \ | |
5870 | ? 32 \ | |
5871 | : 31 \ | |
5872 | : 30 \ | |
5873 | : ((v) & ~0x7) == 0 \ | |
5874 | ? 29 \ | |
5875 | : 28 \ | |
5876 | : ((v) & ~0x3f) == 0 \ | |
5877 | ? ((v) & ~0x1f) == 0 \ | |
5878 | ? 27 \ | |
5879 | : 26 \ | |
5880 | : ((v) & ~0x7f) == 0 \ | |
5881 | ? 25 \ | |
5882 | : 24 \ | |
5883 | : ((v) & ~0xfff) == 0 \ | |
5884 | ? ((v) & ~0x3ff) == 0 \ | |
5885 | ? ((v) & ~0x1ff) == 0 \ | |
5886 | ? 23 \ | |
5887 | : 22 \ | |
5888 | : ((v) & ~0x7ff) == 0 \ | |
5889 | ? 21 \ | |
5890 | : 20 \ | |
5891 | : ((v) & ~0x3fff) == 0 \ | |
5892 | ? ((v) & ~0x1fff) == 0 \ | |
5893 | ? 19 \ | |
5894 | : 18 \ | |
5895 | : ((v) & ~0x7fff) == 0 \ | |
5896 | ? 17 \ | |
5897 | : 16 \ | |
5898 | : ((v) & ~0xffffff) == 0 \ | |
5899 | ? ((v) & ~0xfffff) == 0 \ | |
5900 | ? ((v) & ~0x3ffff) == 0 \ | |
5901 | ? ((v) & ~0x1ffff) == 0 \ | |
5902 | ? 15 \ | |
5903 | : 14 \ | |
5904 | : ((v) & ~0x7ffff) == 0 \ | |
5905 | ? 13 \ | |
5906 | : 12 \ | |
5907 | : ((v) & ~0x3fffff) == 0 \ | |
5908 | ? ((v) & ~0x1fffff) == 0 \ | |
5909 | ? 11 \ | |
5910 | : 10 \ | |
5911 | : ((v) & ~0x7fffff) == 0 \ | |
5912 | ? 9 \ | |
5913 | : 8 \ | |
5914 | : ((v) & ~0xfffffff) == 0 \ | |
5915 | ? ((v) & ~0x3ffffff) == 0 \ | |
5916 | ? ((v) & ~0x1ffffff) == 0 \ | |
5917 | ? 7 \ | |
5918 | : 6 \ | |
5919 | : ((v) & ~0x7ffffff) == 0 \ | |
5920 | ? 5 \ | |
5921 | : 4 \ | |
5922 | : ((v) & ~0x3fffffff) == 0 \ | |
5923 | ? ((v) & ~0x1fffffff) == 0 \ | |
5924 | ? 3 \ | |
5925 | : 2 \ | |
5926 | : ((v) & ~0x7fffffff) == 0 \ | |
5927 | ? 1 \ | |
5928 | : 0) | |
5929 | ||
5930 | /* load_register() | |
67c1ffbe | 5931 | * This routine generates the least number of instructions necessary to load |
252b5132 RH |
5932 | * an absolute expression value into a register. |
5933 | */ | |
5934 | static void | |
67c0d1eb | 5935 | load_register (int reg, expressionS *ep, int dbl) |
252b5132 RH |
5936 | { |
5937 | int freg; | |
5938 | expressionS hi32, lo32; | |
5939 | ||
5940 | if (ep->X_op != O_big) | |
5941 | { | |
9c2799c2 | 5942 | gas_assert (ep->X_op == O_constant); |
256ab948 TS |
5943 | |
5944 | /* Sign-extending 32-bit constants makes their handling easier. */ | |
2051e8c4 MR |
5945 | if (!dbl) |
5946 | normalize_constant_expr (ep); | |
256ab948 TS |
5947 | |
5948 | if (IS_SEXT_16BIT_NUM (ep->X_add_number)) | |
252b5132 RH |
5949 | { |
5950 | /* We can handle 16 bit signed values with an addiu to | |
5951 | $zero. No need to ever use daddiu here, since $zero and | |
5952 | the result are always correct in 32 bit mode. */ | |
67c0d1eb | 5953 | macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
5954 | return; |
5955 | } | |
5956 | else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000) | |
5957 | { | |
5958 | /* We can handle 16 bit unsigned values with an ori to | |
5959 | $zero. */ | |
67c0d1eb | 5960 | macro_build (ep, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
5961 | return; |
5962 | } | |
256ab948 | 5963 | else if ((IS_SEXT_32BIT_NUM (ep->X_add_number))) |
252b5132 RH |
5964 | { |
5965 | /* 32 bit values require an lui. */ | |
df58fc94 | 5966 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_HI16); |
252b5132 | 5967 | if ((ep->X_add_number & 0xffff) != 0) |
67c0d1eb | 5968 | macro_build (ep, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16); |
252b5132 RH |
5969 | return; |
5970 | } | |
5971 | } | |
5972 | ||
5973 | /* The value is larger than 32 bits. */ | |
5974 | ||
2051e8c4 | 5975 | if (!dbl || HAVE_32BIT_GPRS) |
252b5132 | 5976 | { |
55e08f71 NC |
5977 | char value[32]; |
5978 | ||
5979 | sprintf_vma (value, ep->X_add_number); | |
20e1fcfd | 5980 | as_bad (_("Number (0x%s) larger than 32 bits"), value); |
67c0d1eb | 5981 | macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
5982 | return; |
5983 | } | |
5984 | ||
5985 | if (ep->X_op != O_big) | |
5986 | { | |
5987 | hi32 = *ep; | |
5988 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
5989 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
5990 | hi32.X_add_number &= 0xffffffff; | |
5991 | lo32 = *ep; | |
5992 | lo32.X_add_number &= 0xffffffff; | |
5993 | } | |
5994 | else | |
5995 | { | |
9c2799c2 | 5996 | gas_assert (ep->X_add_number > 2); |
252b5132 RH |
5997 | if (ep->X_add_number == 3) |
5998 | generic_bignum[3] = 0; | |
5999 | else if (ep->X_add_number > 4) | |
6000 | as_bad (_("Number larger than 64 bits")); | |
6001 | lo32.X_op = O_constant; | |
6002 | lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16); | |
6003 | hi32.X_op = O_constant; | |
6004 | hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16); | |
6005 | } | |
6006 | ||
6007 | if (hi32.X_add_number == 0) | |
6008 | freg = 0; | |
6009 | else | |
6010 | { | |
6011 | int shift, bit; | |
6012 | unsigned long hi, lo; | |
6013 | ||
956cd1d6 | 6014 | if (hi32.X_add_number == (offsetT) 0xffffffff) |
beae10d5 KH |
6015 | { |
6016 | if ((lo32.X_add_number & 0xffff8000) == 0xffff8000) | |
6017 | { | |
67c0d1eb | 6018 | macro_build (&lo32, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
beae10d5 KH |
6019 | return; |
6020 | } | |
6021 | if (lo32.X_add_number & 0x80000000) | |
6022 | { | |
df58fc94 | 6023 | macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16); |
252b5132 | 6024 | if (lo32.X_add_number & 0xffff) |
67c0d1eb | 6025 | macro_build (&lo32, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16); |
beae10d5 KH |
6026 | return; |
6027 | } | |
6028 | } | |
252b5132 RH |
6029 | |
6030 | /* Check for 16bit shifted constant. We know that hi32 is | |
6031 | non-zero, so start the mask on the first bit of the hi32 | |
6032 | value. */ | |
6033 | shift = 17; | |
6034 | do | |
beae10d5 KH |
6035 | { |
6036 | unsigned long himask, lomask; | |
6037 | ||
6038 | if (shift < 32) | |
6039 | { | |
6040 | himask = 0xffff >> (32 - shift); | |
6041 | lomask = (0xffff << shift) & 0xffffffff; | |
6042 | } | |
6043 | else | |
6044 | { | |
6045 | himask = 0xffff << (shift - 32); | |
6046 | lomask = 0; | |
6047 | } | |
6048 | if ((hi32.X_add_number & ~(offsetT) himask) == 0 | |
6049 | && (lo32.X_add_number & ~(offsetT) lomask) == 0) | |
6050 | { | |
6051 | expressionS tmp; | |
6052 | ||
6053 | tmp.X_op = O_constant; | |
6054 | if (shift < 32) | |
6055 | tmp.X_add_number = ((hi32.X_add_number << (32 - shift)) | |
6056 | | (lo32.X_add_number >> shift)); | |
6057 | else | |
6058 | tmp.X_add_number = hi32.X_add_number >> (shift - 32); | |
67c0d1eb | 6059 | macro_build (&tmp, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16); |
df58fc94 | 6060 | macro_build (NULL, (shift >= 32) ? "dsll32" : "dsll", SHFT_FMT, |
67c0d1eb | 6061 | reg, reg, (shift >= 32) ? shift - 32 : shift); |
beae10d5 KH |
6062 | return; |
6063 | } | |
f9419b05 | 6064 | ++shift; |
beae10d5 KH |
6065 | } |
6066 | while (shift <= (64 - 16)); | |
252b5132 RH |
6067 | |
6068 | /* Find the bit number of the lowest one bit, and store the | |
6069 | shifted value in hi/lo. */ | |
6070 | hi = (unsigned long) (hi32.X_add_number & 0xffffffff); | |
6071 | lo = (unsigned long) (lo32.X_add_number & 0xffffffff); | |
6072 | if (lo != 0) | |
6073 | { | |
6074 | bit = 0; | |
6075 | while ((lo & 1) == 0) | |
6076 | { | |
6077 | lo >>= 1; | |
6078 | ++bit; | |
6079 | } | |
6080 | lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit); | |
6081 | hi >>= bit; | |
6082 | } | |
6083 | else | |
6084 | { | |
6085 | bit = 32; | |
6086 | while ((hi & 1) == 0) | |
6087 | { | |
6088 | hi >>= 1; | |
6089 | ++bit; | |
6090 | } | |
6091 | lo = hi; | |
6092 | hi = 0; | |
6093 | } | |
6094 | ||
6095 | /* Optimize if the shifted value is a (power of 2) - 1. */ | |
6096 | if ((hi == 0 && ((lo + 1) & lo) == 0) | |
6097 | || (lo == 0xffffffff && ((hi + 1) & hi) == 0)) | |
beae10d5 KH |
6098 | { |
6099 | shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number); | |
252b5132 | 6100 | if (shift != 0) |
beae10d5 | 6101 | { |
252b5132 RH |
6102 | expressionS tmp; |
6103 | ||
6104 | /* This instruction will set the register to be all | |
6105 | ones. */ | |
beae10d5 KH |
6106 | tmp.X_op = O_constant; |
6107 | tmp.X_add_number = (offsetT) -1; | |
67c0d1eb | 6108 | macro_build (&tmp, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
beae10d5 KH |
6109 | if (bit != 0) |
6110 | { | |
6111 | bit += shift; | |
df58fc94 | 6112 | macro_build (NULL, (bit >= 32) ? "dsll32" : "dsll", SHFT_FMT, |
67c0d1eb | 6113 | reg, reg, (bit >= 32) ? bit - 32 : bit); |
beae10d5 | 6114 | } |
df58fc94 | 6115 | macro_build (NULL, (shift >= 32) ? "dsrl32" : "dsrl", SHFT_FMT, |
67c0d1eb | 6116 | reg, reg, (shift >= 32) ? shift - 32 : shift); |
beae10d5 KH |
6117 | return; |
6118 | } | |
6119 | } | |
252b5132 RH |
6120 | |
6121 | /* Sign extend hi32 before calling load_register, because we can | |
6122 | generally get better code when we load a sign extended value. */ | |
6123 | if ((hi32.X_add_number & 0x80000000) != 0) | |
beae10d5 | 6124 | hi32.X_add_number |= ~(offsetT) 0xffffffff; |
67c0d1eb | 6125 | load_register (reg, &hi32, 0); |
252b5132 RH |
6126 | freg = reg; |
6127 | } | |
6128 | if ((lo32.X_add_number & 0xffff0000) == 0) | |
6129 | { | |
6130 | if (freg != 0) | |
6131 | { | |
df58fc94 | 6132 | macro_build (NULL, "dsll32", SHFT_FMT, reg, freg, 0); |
252b5132 RH |
6133 | freg = reg; |
6134 | } | |
6135 | } | |
6136 | else | |
6137 | { | |
6138 | expressionS mid16; | |
6139 | ||
956cd1d6 | 6140 | if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff)) |
beae10d5 | 6141 | { |
df58fc94 RS |
6142 | macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16); |
6143 | macro_build (NULL, "dsrl32", SHFT_FMT, reg, reg, 0); | |
beae10d5 KH |
6144 | return; |
6145 | } | |
252b5132 RH |
6146 | |
6147 | if (freg != 0) | |
6148 | { | |
df58fc94 | 6149 | macro_build (NULL, "dsll", SHFT_FMT, reg, freg, 16); |
252b5132 RH |
6150 | freg = reg; |
6151 | } | |
6152 | mid16 = lo32; | |
6153 | mid16.X_add_number >>= 16; | |
67c0d1eb | 6154 | macro_build (&mid16, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16); |
df58fc94 | 6155 | macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16); |
252b5132 RH |
6156 | freg = reg; |
6157 | } | |
6158 | if ((lo32.X_add_number & 0xffff) != 0) | |
67c0d1eb | 6159 | macro_build (&lo32, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16); |
252b5132 RH |
6160 | } |
6161 | ||
269137b2 TS |
6162 | static inline void |
6163 | load_delay_nop (void) | |
6164 | { | |
6165 | if (!gpr_interlocks) | |
6166 | macro_build (NULL, "nop", ""); | |
6167 | } | |
6168 | ||
252b5132 RH |
6169 | /* Load an address into a register. */ |
6170 | ||
6171 | static void | |
67c0d1eb | 6172 | load_address (int reg, expressionS *ep, int *used_at) |
252b5132 | 6173 | { |
252b5132 RH |
6174 | if (ep->X_op != O_constant |
6175 | && ep->X_op != O_symbol) | |
6176 | { | |
6177 | as_bad (_("expression too complex")); | |
6178 | ep->X_op = O_constant; | |
6179 | } | |
6180 | ||
6181 | if (ep->X_op == O_constant) | |
6182 | { | |
67c0d1eb | 6183 | load_register (reg, ep, HAVE_64BIT_ADDRESSES); |
252b5132 RH |
6184 | return; |
6185 | } | |
6186 | ||
6187 | if (mips_pic == NO_PIC) | |
6188 | { | |
6189 | /* If this is a reference to a GP relative symbol, we want | |
cdf6fd85 | 6190 | addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
6191 | Otherwise we want |
6192 | lui $reg,<sym> (BFD_RELOC_HI16_S) | |
6193 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
d6bc6245 | 6194 | If we have an addend, we always use the latter form. |
76b3015f | 6195 | |
d6bc6245 TS |
6196 | With 64bit address space and a usable $at we want |
6197 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
6198 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
6199 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
6200 | daddiu $at,<sym> (BFD_RELOC_LO16) | |
6201 | dsll32 $reg,0 | |
3a482fd5 | 6202 | daddu $reg,$reg,$at |
76b3015f | 6203 | |
c03099e6 | 6204 | If $at is already in use, we use a path which is suboptimal |
d6bc6245 TS |
6205 | on superscalar processors. |
6206 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
6207 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
6208 | dsll $reg,16 | |
6209 | daddiu $reg,<sym> (BFD_RELOC_HI16_S) | |
6210 | dsll $reg,16 | |
6211 | daddiu $reg,<sym> (BFD_RELOC_LO16) | |
6caf9ef4 TS |
6212 | |
6213 | For GP relative symbols in 64bit address space we can use | |
6214 | the same sequence as in 32bit address space. */ | |
aed1a261 | 6215 | if (HAVE_64BIT_SYMBOLS) |
d6bc6245 | 6216 | { |
6caf9ef4 TS |
6217 | if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET |
6218 | && !nopic_need_relax (ep->X_add_symbol, 1)) | |
6219 | { | |
6220 | relax_start (ep->X_add_symbol); | |
6221 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, | |
6222 | mips_gp_register, BFD_RELOC_GPREL16); | |
6223 | relax_switch (); | |
6224 | } | |
d6bc6245 | 6225 | |
741fe287 | 6226 | if (*used_at == 0 && mips_opts.at) |
d6bc6245 | 6227 | { |
df58fc94 RS |
6228 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST); |
6229 | macro_build (ep, "lui", LUI_FMT, AT, BFD_RELOC_HI16_S); | |
67c0d1eb RS |
6230 | macro_build (ep, "daddiu", "t,r,j", reg, reg, |
6231 | BFD_RELOC_MIPS_HIGHER); | |
6232 | macro_build (ep, "daddiu", "t,r,j", AT, AT, BFD_RELOC_LO16); | |
df58fc94 | 6233 | macro_build (NULL, "dsll32", SHFT_FMT, reg, reg, 0); |
67c0d1eb | 6234 | macro_build (NULL, "daddu", "d,v,t", reg, reg, AT); |
d6bc6245 TS |
6235 | *used_at = 1; |
6236 | } | |
6237 | else | |
6238 | { | |
df58fc94 | 6239 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST); |
67c0d1eb RS |
6240 | macro_build (ep, "daddiu", "t,r,j", reg, reg, |
6241 | BFD_RELOC_MIPS_HIGHER); | |
df58fc94 | 6242 | macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16); |
67c0d1eb | 6243 | macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_HI16_S); |
df58fc94 | 6244 | macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16); |
67c0d1eb | 6245 | macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_LO16); |
d6bc6245 | 6246 | } |
6caf9ef4 TS |
6247 | |
6248 | if (mips_relax.sequence) | |
6249 | relax_end (); | |
d6bc6245 | 6250 | } |
252b5132 RH |
6251 | else |
6252 | { | |
d6bc6245 | 6253 | if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 6254 | && !nopic_need_relax (ep->X_add_symbol, 1)) |
d6bc6245 | 6255 | { |
4d7206a2 | 6256 | relax_start (ep->X_add_symbol); |
67c0d1eb | 6257 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, |
17a2f251 | 6258 | mips_gp_register, BFD_RELOC_GPREL16); |
4d7206a2 | 6259 | relax_switch (); |
d6bc6245 | 6260 | } |
67c0d1eb RS |
6261 | macro_build_lui (ep, reg); |
6262 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", | |
6263 | reg, reg, BFD_RELOC_LO16); | |
4d7206a2 RS |
6264 | if (mips_relax.sequence) |
6265 | relax_end (); | |
d6bc6245 | 6266 | } |
252b5132 | 6267 | } |
0a44bf69 | 6268 | else if (!mips_big_got) |
252b5132 RH |
6269 | { |
6270 | expressionS ex; | |
6271 | ||
6272 | /* If this is a reference to an external symbol, we want | |
6273 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6274 | Otherwise we want | |
6275 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6276 | nop | |
6277 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
f5040a92 AO |
6278 | If there is a constant, it must be added in after. |
6279 | ||
ed6fb7bd | 6280 | If we have NewABI, we want |
f5040a92 AO |
6281 | lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP) |
6282 | unless we're referencing a global symbol with a non-zero | |
6283 | offset, in which case cst must be added separately. */ | |
ed6fb7bd SC |
6284 | if (HAVE_NEWABI) |
6285 | { | |
f5040a92 AO |
6286 | if (ep->X_add_number) |
6287 | { | |
4d7206a2 | 6288 | ex.X_add_number = ep->X_add_number; |
f5040a92 | 6289 | ep->X_add_number = 0; |
4d7206a2 | 6290 | relax_start (ep->X_add_symbol); |
67c0d1eb RS |
6291 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
6292 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
6293 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) |
6294 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
6295 | ex.X_op = O_constant; | |
67c0d1eb | 6296 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 6297 | reg, reg, BFD_RELOC_LO16); |
f5040a92 | 6298 | ep->X_add_number = ex.X_add_number; |
4d7206a2 | 6299 | relax_switch (); |
f5040a92 | 6300 | } |
67c0d1eb | 6301 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 6302 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); |
4d7206a2 RS |
6303 | if (mips_relax.sequence) |
6304 | relax_end (); | |
ed6fb7bd SC |
6305 | } |
6306 | else | |
6307 | { | |
f5040a92 AO |
6308 | ex.X_add_number = ep->X_add_number; |
6309 | ep->X_add_number = 0; | |
67c0d1eb RS |
6310 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
6311 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 6312 | load_delay_nop (); |
4d7206a2 RS |
6313 | relax_start (ep->X_add_symbol); |
6314 | relax_switch (); | |
67c0d1eb | 6315 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
17a2f251 | 6316 | BFD_RELOC_LO16); |
4d7206a2 | 6317 | relax_end (); |
ed6fb7bd | 6318 | |
f5040a92 AO |
6319 | if (ex.X_add_number != 0) |
6320 | { | |
6321 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
6322 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
6323 | ex.X_op = O_constant; | |
67c0d1eb | 6324 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 6325 | reg, reg, BFD_RELOC_LO16); |
f5040a92 | 6326 | } |
252b5132 RH |
6327 | } |
6328 | } | |
0a44bf69 | 6329 | else if (mips_big_got) |
252b5132 RH |
6330 | { |
6331 | expressionS ex; | |
252b5132 RH |
6332 | |
6333 | /* This is the large GOT case. If this is a reference to an | |
6334 | external symbol, we want | |
6335 | lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
6336 | addu $reg,$reg,$gp | |
6337 | lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16) | |
f5040a92 AO |
6338 | |
6339 | Otherwise, for a reference to a local symbol in old ABI, we want | |
252b5132 RH |
6340 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) |
6341 | nop | |
6342 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
684022ea | 6343 | If there is a constant, it must be added in after. |
f5040a92 AO |
6344 | |
6345 | In the NewABI, for local symbols, with or without offsets, we want: | |
438c16b8 TS |
6346 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) |
6347 | addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) | |
f5040a92 | 6348 | */ |
438c16b8 TS |
6349 | if (HAVE_NEWABI) |
6350 | { | |
4d7206a2 | 6351 | ex.X_add_number = ep->X_add_number; |
f5040a92 | 6352 | ep->X_add_number = 0; |
4d7206a2 | 6353 | relax_start (ep->X_add_symbol); |
df58fc94 | 6354 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
6355 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
6356 | reg, reg, mips_gp_register); | |
6357 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", | |
6358 | reg, BFD_RELOC_MIPS_GOT_LO16, reg); | |
f5040a92 AO |
6359 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) |
6360 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
6361 | else if (ex.X_add_number) | |
6362 | { | |
6363 | ex.X_op = O_constant; | |
67c0d1eb RS |
6364 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
6365 | BFD_RELOC_LO16); | |
f5040a92 AO |
6366 | } |
6367 | ||
6368 | ep->X_add_number = ex.X_add_number; | |
4d7206a2 | 6369 | relax_switch (); |
67c0d1eb | 6370 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 6371 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); |
67c0d1eb RS |
6372 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
6373 | BFD_RELOC_MIPS_GOT_OFST); | |
4d7206a2 | 6374 | relax_end (); |
438c16b8 | 6375 | } |
252b5132 | 6376 | else |
438c16b8 | 6377 | { |
f5040a92 AO |
6378 | ex.X_add_number = ep->X_add_number; |
6379 | ep->X_add_number = 0; | |
4d7206a2 | 6380 | relax_start (ep->X_add_symbol); |
df58fc94 | 6381 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
6382 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
6383 | reg, reg, mips_gp_register); | |
6384 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", | |
6385 | reg, BFD_RELOC_MIPS_GOT_LO16, reg); | |
4d7206a2 RS |
6386 | relax_switch (); |
6387 | if (reg_needs_delay (mips_gp_register)) | |
438c16b8 TS |
6388 | { |
6389 | /* We need a nop before loading from $gp. This special | |
6390 | check is required because the lui which starts the main | |
6391 | instruction stream does not refer to $gp, and so will not | |
6392 | insert the nop which may be required. */ | |
67c0d1eb | 6393 | macro_build (NULL, "nop", ""); |
438c16b8 | 6394 | } |
67c0d1eb | 6395 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 6396 | BFD_RELOC_MIPS_GOT16, mips_gp_register); |
269137b2 | 6397 | load_delay_nop (); |
67c0d1eb | 6398 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
17a2f251 | 6399 | BFD_RELOC_LO16); |
4d7206a2 | 6400 | relax_end (); |
438c16b8 | 6401 | |
f5040a92 AO |
6402 | if (ex.X_add_number != 0) |
6403 | { | |
6404 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
6405 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
6406 | ex.X_op = O_constant; | |
67c0d1eb RS |
6407 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
6408 | BFD_RELOC_LO16); | |
f5040a92 | 6409 | } |
252b5132 RH |
6410 | } |
6411 | } | |
252b5132 RH |
6412 | else |
6413 | abort (); | |
8fc2e39e | 6414 | |
741fe287 | 6415 | if (!mips_opts.at && *used_at == 1) |
8fc2e39e | 6416 | as_bad (_("Macro used $at after \".set noat\"")); |
252b5132 RH |
6417 | } |
6418 | ||
ea1fb5dc RS |
6419 | /* Move the contents of register SOURCE into register DEST. */ |
6420 | ||
6421 | static void | |
67c0d1eb | 6422 | move_register (int dest, int source) |
ea1fb5dc | 6423 | { |
df58fc94 RS |
6424 | /* Prefer to use a 16-bit microMIPS instruction unless the previous |
6425 | instruction specifically requires a 32-bit one. */ | |
6426 | if (mips_opts.micromips | |
6427 | && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) | |
7951ca42 | 6428 | macro_build (NULL, "move", "mp,mj", dest, source); |
df58fc94 RS |
6429 | else |
6430 | macro_build (NULL, HAVE_32BIT_GPRS ? "addu" : "daddu", "d,v,t", | |
6431 | dest, source, 0); | |
ea1fb5dc RS |
6432 | } |
6433 | ||
4d7206a2 | 6434 | /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where |
f6a22291 MR |
6435 | LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement. |
6436 | The two alternatives are: | |
4d7206a2 RS |
6437 | |
6438 | Global symbol Local sybmol | |
6439 | ------------- ------------ | |
6440 | lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET) | |
6441 | ... ... | |
6442 | addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET) | |
6443 | ||
6444 | load_got_offset emits the first instruction and add_got_offset | |
f6a22291 MR |
6445 | emits the second for a 16-bit offset or add_got_offset_hilo emits |
6446 | a sequence to add a 32-bit offset using a scratch register. */ | |
4d7206a2 RS |
6447 | |
6448 | static void | |
67c0d1eb | 6449 | load_got_offset (int dest, expressionS *local) |
4d7206a2 RS |
6450 | { |
6451 | expressionS global; | |
6452 | ||
6453 | global = *local; | |
6454 | global.X_add_number = 0; | |
6455 | ||
6456 | relax_start (local->X_add_symbol); | |
67c0d1eb RS |
6457 | macro_build (&global, ADDRESS_LOAD_INSN, "t,o(b)", dest, |
6458 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
4d7206a2 | 6459 | relax_switch (); |
67c0d1eb RS |
6460 | macro_build (local, ADDRESS_LOAD_INSN, "t,o(b)", dest, |
6461 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
4d7206a2 RS |
6462 | relax_end (); |
6463 | } | |
6464 | ||
6465 | static void | |
67c0d1eb | 6466 | add_got_offset (int dest, expressionS *local) |
4d7206a2 RS |
6467 | { |
6468 | expressionS global; | |
6469 | ||
6470 | global.X_op = O_constant; | |
6471 | global.X_op_symbol = NULL; | |
6472 | global.X_add_symbol = NULL; | |
6473 | global.X_add_number = local->X_add_number; | |
6474 | ||
6475 | relax_start (local->X_add_symbol); | |
67c0d1eb | 6476 | macro_build (&global, ADDRESS_ADDI_INSN, "t,r,j", |
4d7206a2 RS |
6477 | dest, dest, BFD_RELOC_LO16); |
6478 | relax_switch (); | |
67c0d1eb | 6479 | macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", dest, dest, BFD_RELOC_LO16); |
4d7206a2 RS |
6480 | relax_end (); |
6481 | } | |
6482 | ||
f6a22291 MR |
6483 | static void |
6484 | add_got_offset_hilo (int dest, expressionS *local, int tmp) | |
6485 | { | |
6486 | expressionS global; | |
6487 | int hold_mips_optimize; | |
6488 | ||
6489 | global.X_op = O_constant; | |
6490 | global.X_op_symbol = NULL; | |
6491 | global.X_add_symbol = NULL; | |
6492 | global.X_add_number = local->X_add_number; | |
6493 | ||
6494 | relax_start (local->X_add_symbol); | |
6495 | load_register (tmp, &global, HAVE_64BIT_ADDRESSES); | |
6496 | relax_switch (); | |
6497 | /* Set mips_optimize around the lui instruction to avoid | |
6498 | inserting an unnecessary nop after the lw. */ | |
6499 | hold_mips_optimize = mips_optimize; | |
6500 | mips_optimize = 2; | |
6501 | macro_build_lui (&global, tmp); | |
6502 | mips_optimize = hold_mips_optimize; | |
6503 | macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", tmp, tmp, BFD_RELOC_LO16); | |
6504 | relax_end (); | |
6505 | ||
6506 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dest, dest, tmp); | |
6507 | } | |
6508 | ||
df58fc94 RS |
6509 | /* Emit a sequence of instructions to emulate a branch likely operation. |
6510 | BR is an ordinary branch corresponding to one to be emulated. BRNEG | |
6511 | is its complementing branch with the original condition negated. | |
6512 | CALL is set if the original branch specified the link operation. | |
6513 | EP, FMT, SREG and TREG specify the usual macro_build() parameters. | |
6514 | ||
6515 | Code like this is produced in the noreorder mode: | |
6516 | ||
6517 | BRNEG <args>, 1f | |
6518 | nop | |
6519 | b <sym> | |
6520 | delay slot (executed only if branch taken) | |
6521 | 1: | |
6522 | ||
6523 | or, if CALL is set: | |
6524 | ||
6525 | BRNEG <args>, 1f | |
6526 | nop | |
6527 | bal <sym> | |
6528 | delay slot (executed only if branch taken) | |
6529 | 1: | |
6530 | ||
6531 | In the reorder mode the delay slot would be filled with a nop anyway, | |
6532 | so code produced is simply: | |
6533 | ||
6534 | BR <args>, <sym> | |
6535 | nop | |
6536 | ||
6537 | This function is used when producing code for the microMIPS ASE that | |
6538 | does not implement branch likely instructions in hardware. */ | |
6539 | ||
6540 | static void | |
6541 | macro_build_branch_likely (const char *br, const char *brneg, | |
6542 | int call, expressionS *ep, const char *fmt, | |
6543 | unsigned int sreg, unsigned int treg) | |
6544 | { | |
6545 | int noreorder = mips_opts.noreorder; | |
6546 | expressionS expr1; | |
6547 | ||
6548 | gas_assert (mips_opts.micromips); | |
6549 | start_noreorder (); | |
6550 | if (noreorder) | |
6551 | { | |
6552 | micromips_label_expr (&expr1); | |
6553 | macro_build (&expr1, brneg, fmt, sreg, treg); | |
6554 | macro_build (NULL, "nop", ""); | |
6555 | macro_build (ep, call ? "bal" : "b", "p"); | |
6556 | ||
6557 | /* Set to true so that append_insn adds a label. */ | |
6558 | emit_branch_likely_macro = TRUE; | |
6559 | } | |
6560 | else | |
6561 | { | |
6562 | macro_build (ep, br, fmt, sreg, treg); | |
6563 | macro_build (NULL, "nop", ""); | |
6564 | } | |
6565 | end_noreorder (); | |
6566 | } | |
6567 | ||
6568 | /* Emit a coprocessor branch-likely macro specified by TYPE, using CC as | |
6569 | the condition code tested. EP specifies the branch target. */ | |
6570 | ||
6571 | static void | |
6572 | macro_build_branch_ccl (int type, expressionS *ep, unsigned int cc) | |
6573 | { | |
6574 | const int call = 0; | |
6575 | const char *brneg; | |
6576 | const char *br; | |
6577 | ||
6578 | switch (type) | |
6579 | { | |
6580 | case M_BC1FL: | |
6581 | br = "bc1f"; | |
6582 | brneg = "bc1t"; | |
6583 | break; | |
6584 | case M_BC1TL: | |
6585 | br = "bc1t"; | |
6586 | brneg = "bc1f"; | |
6587 | break; | |
6588 | case M_BC2FL: | |
6589 | br = "bc2f"; | |
6590 | brneg = "bc2t"; | |
6591 | break; | |
6592 | case M_BC2TL: | |
6593 | br = "bc2t"; | |
6594 | brneg = "bc2f"; | |
6595 | break; | |
6596 | default: | |
6597 | abort (); | |
6598 | } | |
6599 | macro_build_branch_likely (br, brneg, call, ep, "N,p", cc, ZERO); | |
6600 | } | |
6601 | ||
6602 | /* Emit a two-argument branch macro specified by TYPE, using SREG as | |
6603 | the register tested. EP specifies the branch target. */ | |
6604 | ||
6605 | static void | |
6606 | macro_build_branch_rs (int type, expressionS *ep, unsigned int sreg) | |
6607 | { | |
6608 | const char *brneg = NULL; | |
6609 | const char *br; | |
6610 | int call = 0; | |
6611 | ||
6612 | switch (type) | |
6613 | { | |
6614 | case M_BGEZ: | |
6615 | br = "bgez"; | |
6616 | break; | |
6617 | case M_BGEZL: | |
6618 | br = mips_opts.micromips ? "bgez" : "bgezl"; | |
6619 | brneg = "bltz"; | |
6620 | break; | |
6621 | case M_BGEZALL: | |
6622 | gas_assert (mips_opts.micromips); | |
6623 | br = "bgezals"; | |
6624 | brneg = "bltz"; | |
6625 | call = 1; | |
6626 | break; | |
6627 | case M_BGTZ: | |
6628 | br = "bgtz"; | |
6629 | break; | |
6630 | case M_BGTZL: | |
6631 | br = mips_opts.micromips ? "bgtz" : "bgtzl"; | |
6632 | brneg = "blez"; | |
6633 | break; | |
6634 | case M_BLEZ: | |
6635 | br = "blez"; | |
6636 | break; | |
6637 | case M_BLEZL: | |
6638 | br = mips_opts.micromips ? "blez" : "blezl"; | |
6639 | brneg = "bgtz"; | |
6640 | break; | |
6641 | case M_BLTZ: | |
6642 | br = "bltz"; | |
6643 | break; | |
6644 | case M_BLTZL: | |
6645 | br = mips_opts.micromips ? "bltz" : "bltzl"; | |
6646 | brneg = "bgez"; | |
6647 | break; | |
6648 | case M_BLTZALL: | |
6649 | gas_assert (mips_opts.micromips); | |
6650 | br = "bltzals"; | |
6651 | brneg = "bgez"; | |
6652 | call = 1; | |
6653 | break; | |
6654 | default: | |
6655 | abort (); | |
6656 | } | |
6657 | if (mips_opts.micromips && brneg) | |
6658 | macro_build_branch_likely (br, brneg, call, ep, "s,p", sreg, ZERO); | |
6659 | else | |
6660 | macro_build (ep, br, "s,p", sreg); | |
6661 | } | |
6662 | ||
6663 | /* Emit a three-argument branch macro specified by TYPE, using SREG and | |
6664 | TREG as the registers tested. EP specifies the branch target. */ | |
6665 | ||
6666 | static void | |
6667 | macro_build_branch_rsrt (int type, expressionS *ep, | |
6668 | unsigned int sreg, unsigned int treg) | |
6669 | { | |
6670 | const char *brneg = NULL; | |
6671 | const int call = 0; | |
6672 | const char *br; | |
6673 | ||
6674 | switch (type) | |
6675 | { | |
6676 | case M_BEQ: | |
6677 | case M_BEQ_I: | |
6678 | br = "beq"; | |
6679 | break; | |
6680 | case M_BEQL: | |
6681 | case M_BEQL_I: | |
6682 | br = mips_opts.micromips ? "beq" : "beql"; | |
6683 | brneg = "bne"; | |
6684 | break; | |
6685 | case M_BNE: | |
6686 | case M_BNE_I: | |
6687 | br = "bne"; | |
6688 | break; | |
6689 | case M_BNEL: | |
6690 | case M_BNEL_I: | |
6691 | br = mips_opts.micromips ? "bne" : "bnel"; | |
6692 | brneg = "beq"; | |
6693 | break; | |
6694 | default: | |
6695 | abort (); | |
6696 | } | |
6697 | if (mips_opts.micromips && brneg) | |
6698 | macro_build_branch_likely (br, brneg, call, ep, "s,t,p", sreg, treg); | |
6699 | else | |
6700 | macro_build (ep, br, "s,t,p", sreg, treg); | |
6701 | } | |
6702 | ||
252b5132 RH |
6703 | /* |
6704 | * Build macros | |
6705 | * This routine implements the seemingly endless macro or synthesized | |
6706 | * instructions and addressing modes in the mips assembly language. Many | |
6707 | * of these macros are simple and are similar to each other. These could | |
67c1ffbe | 6708 | * probably be handled by some kind of table or grammar approach instead of |
252b5132 RH |
6709 | * this verbose method. Others are not simple macros but are more like |
6710 | * optimizing code generation. | |
6711 | * One interesting optimization is when several store macros appear | |
67c1ffbe | 6712 | * consecutively that would load AT with the upper half of the same address. |
252b5132 RH |
6713 | * The ensuing load upper instructions are ommited. This implies some kind |
6714 | * of global optimization. We currently only optimize within a single macro. | |
6715 | * For many of the load and store macros if the address is specified as a | |
6716 | * constant expression in the first 64k of memory (ie ld $2,0x4000c) we | |
6717 | * first load register 'at' with zero and use it as the base register. The | |
6718 | * mips assembler simply uses register $zero. Just one tiny optimization | |
6719 | * we're missing. | |
6720 | */ | |
6721 | static void | |
17a2f251 | 6722 | macro (struct mips_cl_insn *ip) |
252b5132 | 6723 | { |
741fe287 MR |
6724 | unsigned int treg, sreg, dreg, breg; |
6725 | unsigned int tempreg; | |
252b5132 | 6726 | int mask; |
43841e91 | 6727 | int used_at = 0; |
df58fc94 | 6728 | expressionS label_expr; |
252b5132 | 6729 | expressionS expr1; |
df58fc94 | 6730 | expressionS *ep; |
252b5132 RH |
6731 | const char *s; |
6732 | const char *s2; | |
6733 | const char *fmt; | |
6734 | int likely = 0; | |
252b5132 | 6735 | int coproc = 0; |
7f3c4072 | 6736 | int offbits = 16; |
1abe91b1 | 6737 | int call = 0; |
df58fc94 RS |
6738 | int jals = 0; |
6739 | int dbl = 0; | |
6740 | int imm = 0; | |
6741 | int ust = 0; | |
6742 | int lp = 0; | |
6743 | int ab = 0; | |
252b5132 | 6744 | int off; |
67c0d1eb | 6745 | offsetT maxnum; |
252b5132 | 6746 | bfd_reloc_code_real_type r; |
252b5132 RH |
6747 | int hold_mips_optimize; |
6748 | ||
9c2799c2 | 6749 | gas_assert (! mips_opts.mips16); |
252b5132 | 6750 | |
df58fc94 RS |
6751 | treg = EXTRACT_OPERAND (mips_opts.micromips, RT, *ip); |
6752 | dreg = EXTRACT_OPERAND (mips_opts.micromips, RD, *ip); | |
6753 | sreg = breg = EXTRACT_OPERAND (mips_opts.micromips, RS, *ip); | |
252b5132 RH |
6754 | mask = ip->insn_mo->mask; |
6755 | ||
df58fc94 RS |
6756 | label_expr.X_op = O_constant; |
6757 | label_expr.X_op_symbol = NULL; | |
6758 | label_expr.X_add_symbol = NULL; | |
6759 | label_expr.X_add_number = 0; | |
6760 | ||
252b5132 RH |
6761 | expr1.X_op = O_constant; |
6762 | expr1.X_op_symbol = NULL; | |
6763 | expr1.X_add_symbol = NULL; | |
6764 | expr1.X_add_number = 1; | |
6765 | ||
6766 | switch (mask) | |
6767 | { | |
6768 | case M_DABS: | |
6769 | dbl = 1; | |
6770 | case M_ABS: | |
df58fc94 RS |
6771 | /* bgez $a0,1f |
6772 | move v0,$a0 | |
6773 | sub v0,$zero,$a0 | |
6774 | 1: | |
6775 | */ | |
252b5132 | 6776 | |
7d10b47d | 6777 | start_noreorder (); |
252b5132 | 6778 | |
df58fc94 RS |
6779 | if (mips_opts.micromips) |
6780 | micromips_label_expr (&label_expr); | |
6781 | else | |
6782 | label_expr.X_add_number = 8; | |
6783 | macro_build (&label_expr, "bgez", "s,p", sreg); | |
252b5132 | 6784 | if (dreg == sreg) |
a605d2b3 | 6785 | macro_build (NULL, "nop", ""); |
252b5132 | 6786 | else |
67c0d1eb RS |
6787 | move_register (dreg, sreg); |
6788 | macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, 0, sreg); | |
df58fc94 RS |
6789 | if (mips_opts.micromips) |
6790 | micromips_add_label (); | |
252b5132 | 6791 | |
7d10b47d | 6792 | end_noreorder (); |
8fc2e39e | 6793 | break; |
252b5132 RH |
6794 | |
6795 | case M_ADD_I: | |
6796 | s = "addi"; | |
6797 | s2 = "add"; | |
6798 | goto do_addi; | |
6799 | case M_ADDU_I: | |
6800 | s = "addiu"; | |
6801 | s2 = "addu"; | |
6802 | goto do_addi; | |
6803 | case M_DADD_I: | |
6804 | dbl = 1; | |
6805 | s = "daddi"; | |
6806 | s2 = "dadd"; | |
df58fc94 RS |
6807 | if (!mips_opts.micromips) |
6808 | goto do_addi; | |
6809 | if (imm_expr.X_op == O_constant | |
6810 | && imm_expr.X_add_number >= -0x200 | |
6811 | && imm_expr.X_add_number < 0x200) | |
6812 | { | |
6813 | macro_build (NULL, s, "t,r,.", treg, sreg, imm_expr.X_add_number); | |
6814 | break; | |
6815 | } | |
6816 | goto do_addi_i; | |
252b5132 RH |
6817 | case M_DADDU_I: |
6818 | dbl = 1; | |
6819 | s = "daddiu"; | |
6820 | s2 = "daddu"; | |
6821 | do_addi: | |
6822 | if (imm_expr.X_op == O_constant | |
6823 | && imm_expr.X_add_number >= -0x8000 | |
6824 | && imm_expr.X_add_number < 0x8000) | |
6825 | { | |
67c0d1eb | 6826 | macro_build (&imm_expr, s, "t,r,j", treg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 6827 | break; |
252b5132 | 6828 | } |
df58fc94 | 6829 | do_addi_i: |
8fc2e39e | 6830 | used_at = 1; |
67c0d1eb RS |
6831 | load_register (AT, &imm_expr, dbl); |
6832 | macro_build (NULL, s2, "d,v,t", treg, sreg, AT); | |
252b5132 RH |
6833 | break; |
6834 | ||
6835 | case M_AND_I: | |
6836 | s = "andi"; | |
6837 | s2 = "and"; | |
6838 | goto do_bit; | |
6839 | case M_OR_I: | |
6840 | s = "ori"; | |
6841 | s2 = "or"; | |
6842 | goto do_bit; | |
6843 | case M_NOR_I: | |
6844 | s = ""; | |
6845 | s2 = "nor"; | |
6846 | goto do_bit; | |
6847 | case M_XOR_I: | |
6848 | s = "xori"; | |
6849 | s2 = "xor"; | |
6850 | do_bit: | |
6851 | if (imm_expr.X_op == O_constant | |
6852 | && imm_expr.X_add_number >= 0 | |
6853 | && imm_expr.X_add_number < 0x10000) | |
6854 | { | |
6855 | if (mask != M_NOR_I) | |
67c0d1eb | 6856 | macro_build (&imm_expr, s, "t,r,i", treg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
6857 | else |
6858 | { | |
67c0d1eb RS |
6859 | macro_build (&imm_expr, "ori", "t,r,i", |
6860 | treg, sreg, BFD_RELOC_LO16); | |
6861 | macro_build (NULL, "nor", "d,v,t", treg, treg, 0); | |
252b5132 | 6862 | } |
8fc2e39e | 6863 | break; |
252b5132 RH |
6864 | } |
6865 | ||
8fc2e39e | 6866 | used_at = 1; |
67c0d1eb RS |
6867 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
6868 | macro_build (NULL, s2, "d,v,t", treg, sreg, AT); | |
252b5132 RH |
6869 | break; |
6870 | ||
8b082fb1 TS |
6871 | case M_BALIGN: |
6872 | switch (imm_expr.X_add_number) | |
6873 | { | |
6874 | case 0: | |
6875 | macro_build (NULL, "nop", ""); | |
6876 | break; | |
6877 | case 2: | |
6878 | macro_build (NULL, "packrl.ph", "d,s,t", treg, treg, sreg); | |
6879 | break; | |
03f66e8a MR |
6880 | case 1: |
6881 | case 3: | |
8b082fb1 | 6882 | macro_build (NULL, "balign", "t,s,2", treg, sreg, |
90ecf173 | 6883 | (int) imm_expr.X_add_number); |
8b082fb1 | 6884 | break; |
03f66e8a MR |
6885 | default: |
6886 | as_bad (_("BALIGN immediate not 0, 1, 2 or 3 (%lu)"), | |
6887 | (unsigned long) imm_expr.X_add_number); | |
6888 | break; | |
8b082fb1 TS |
6889 | } |
6890 | break; | |
6891 | ||
df58fc94 RS |
6892 | case M_BC1FL: |
6893 | case M_BC1TL: | |
6894 | case M_BC2FL: | |
6895 | case M_BC2TL: | |
6896 | gas_assert (mips_opts.micromips); | |
6897 | macro_build_branch_ccl (mask, &offset_expr, | |
6898 | EXTRACT_OPERAND (1, BCC, *ip)); | |
6899 | break; | |
6900 | ||
252b5132 | 6901 | case M_BEQ_I: |
252b5132 | 6902 | case M_BEQL_I: |
252b5132 | 6903 | case M_BNE_I: |
252b5132 | 6904 | case M_BNEL_I: |
252b5132 | 6905 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) |
df58fc94 RS |
6906 | treg = 0; |
6907 | else | |
252b5132 | 6908 | { |
df58fc94 RS |
6909 | treg = AT; |
6910 | used_at = 1; | |
6911 | load_register (treg, &imm_expr, HAVE_64BIT_GPRS); | |
252b5132 | 6912 | } |
df58fc94 RS |
6913 | /* Fall through. */ |
6914 | case M_BEQL: | |
6915 | case M_BNEL: | |
6916 | macro_build_branch_rsrt (mask, &offset_expr, sreg, treg); | |
252b5132 RH |
6917 | break; |
6918 | ||
6919 | case M_BGEL: | |
6920 | likely = 1; | |
6921 | case M_BGE: | |
6922 | if (treg == 0) | |
df58fc94 RS |
6923 | macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, sreg); |
6924 | else if (sreg == 0) | |
6925 | macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, treg); | |
6926 | else | |
252b5132 | 6927 | { |
df58fc94 RS |
6928 | used_at = 1; |
6929 | macro_build (NULL, "slt", "d,v,t", AT, sreg, treg); | |
6930 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, | |
6931 | &offset_expr, AT, ZERO); | |
252b5132 | 6932 | } |
df58fc94 RS |
6933 | break; |
6934 | ||
6935 | case M_BGEZL: | |
6936 | case M_BGEZALL: | |
6937 | case M_BGTZL: | |
6938 | case M_BLEZL: | |
6939 | case M_BLTZL: | |
6940 | case M_BLTZALL: | |
6941 | macro_build_branch_rs (mask, &offset_expr, sreg); | |
252b5132 RH |
6942 | break; |
6943 | ||
6944 | case M_BGTL_I: | |
6945 | likely = 1; | |
6946 | case M_BGT_I: | |
90ecf173 | 6947 | /* Check for > max integer. */ |
252b5132 | 6948 | maxnum = 0x7fffffff; |
ca4e0257 | 6949 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
6950 | { |
6951 | maxnum <<= 16; | |
6952 | maxnum |= 0xffff; | |
6953 | maxnum <<= 16; | |
6954 | maxnum |= 0xffff; | |
6955 | } | |
6956 | if (imm_expr.X_op == O_constant | |
6957 | && imm_expr.X_add_number >= maxnum | |
ca4e0257 | 6958 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
6959 | { |
6960 | do_false: | |
90ecf173 | 6961 | /* Result is always false. */ |
252b5132 | 6962 | if (! likely) |
a605d2b3 | 6963 | macro_build (NULL, "nop", ""); |
252b5132 | 6964 | else |
df58fc94 | 6965 | macro_build_branch_rsrt (M_BNEL, &offset_expr, ZERO, ZERO); |
8fc2e39e | 6966 | break; |
252b5132 RH |
6967 | } |
6968 | if (imm_expr.X_op != O_constant) | |
6969 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 6970 | ++imm_expr.X_add_number; |
252b5132 RH |
6971 | /* FALLTHROUGH */ |
6972 | case M_BGE_I: | |
6973 | case M_BGEL_I: | |
6974 | if (mask == M_BGEL_I) | |
6975 | likely = 1; | |
6976 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
6977 | { | |
df58fc94 RS |
6978 | macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, |
6979 | &offset_expr, sreg); | |
8fc2e39e | 6980 | break; |
252b5132 RH |
6981 | } |
6982 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
6983 | { | |
df58fc94 RS |
6984 | macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, |
6985 | &offset_expr, sreg); | |
8fc2e39e | 6986 | break; |
252b5132 RH |
6987 | } |
6988 | maxnum = 0x7fffffff; | |
ca4e0257 | 6989 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
6990 | { |
6991 | maxnum <<= 16; | |
6992 | maxnum |= 0xffff; | |
6993 | maxnum <<= 16; | |
6994 | maxnum |= 0xffff; | |
6995 | } | |
6996 | maxnum = - maxnum - 1; | |
6997 | if (imm_expr.X_op == O_constant | |
6998 | && imm_expr.X_add_number <= maxnum | |
ca4e0257 | 6999 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
7000 | { |
7001 | do_true: | |
7002 | /* result is always true */ | |
7003 | as_warn (_("Branch %s is always true"), ip->insn_mo->name); | |
67c0d1eb | 7004 | macro_build (&offset_expr, "b", "p"); |
8fc2e39e | 7005 | break; |
252b5132 | 7006 | } |
8fc2e39e | 7007 | used_at = 1; |
67c0d1eb | 7008 | set_at (sreg, 0); |
df58fc94 RS |
7009 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, |
7010 | &offset_expr, AT, ZERO); | |
252b5132 RH |
7011 | break; |
7012 | ||
7013 | case M_BGEUL: | |
7014 | likely = 1; | |
7015 | case M_BGEU: | |
7016 | if (treg == 0) | |
7017 | goto do_true; | |
df58fc94 RS |
7018 | else if (sreg == 0) |
7019 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, | |
7020 | &offset_expr, ZERO, treg); | |
7021 | else | |
252b5132 | 7022 | { |
df58fc94 RS |
7023 | used_at = 1; |
7024 | macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg); | |
7025 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, | |
7026 | &offset_expr, AT, ZERO); | |
252b5132 | 7027 | } |
252b5132 RH |
7028 | break; |
7029 | ||
7030 | case M_BGTUL_I: | |
7031 | likely = 1; | |
7032 | case M_BGTU_I: | |
7033 | if (sreg == 0 | |
ca4e0257 | 7034 | || (HAVE_32BIT_GPRS |
252b5132 | 7035 | && imm_expr.X_op == O_constant |
f01dc953 | 7036 | && imm_expr.X_add_number == -1)) |
252b5132 RH |
7037 | goto do_false; |
7038 | if (imm_expr.X_op != O_constant) | |
7039 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 7040 | ++imm_expr.X_add_number; |
252b5132 RH |
7041 | /* FALLTHROUGH */ |
7042 | case M_BGEU_I: | |
7043 | case M_BGEUL_I: | |
7044 | if (mask == M_BGEUL_I) | |
7045 | likely = 1; | |
7046 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
7047 | goto do_true; | |
df58fc94 RS |
7048 | else if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) |
7049 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, | |
7050 | &offset_expr, sreg, ZERO); | |
7051 | else | |
252b5132 | 7052 | { |
df58fc94 RS |
7053 | used_at = 1; |
7054 | set_at (sreg, 1); | |
7055 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, | |
7056 | &offset_expr, AT, ZERO); | |
252b5132 | 7057 | } |
252b5132 RH |
7058 | break; |
7059 | ||
7060 | case M_BGTL: | |
7061 | likely = 1; | |
7062 | case M_BGT: | |
7063 | if (treg == 0) | |
df58fc94 RS |
7064 | macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, sreg); |
7065 | else if (sreg == 0) | |
7066 | macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, treg); | |
7067 | else | |
252b5132 | 7068 | { |
df58fc94 RS |
7069 | used_at = 1; |
7070 | macro_build (NULL, "slt", "d,v,t", AT, treg, sreg); | |
7071 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, | |
7072 | &offset_expr, AT, ZERO); | |
252b5132 | 7073 | } |
252b5132 RH |
7074 | break; |
7075 | ||
7076 | case M_BGTUL: | |
7077 | likely = 1; | |
7078 | case M_BGTU: | |
7079 | if (treg == 0) | |
df58fc94 RS |
7080 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, |
7081 | &offset_expr, sreg, ZERO); | |
7082 | else if (sreg == 0) | |
7083 | goto do_false; | |
7084 | else | |
252b5132 | 7085 | { |
df58fc94 RS |
7086 | used_at = 1; |
7087 | macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg); | |
7088 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, | |
7089 | &offset_expr, AT, ZERO); | |
252b5132 | 7090 | } |
252b5132 RH |
7091 | break; |
7092 | ||
7093 | case M_BLEL: | |
7094 | likely = 1; | |
7095 | case M_BLE: | |
7096 | if (treg == 0) | |
df58fc94 RS |
7097 | macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, sreg); |
7098 | else if (sreg == 0) | |
7099 | macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, treg); | |
7100 | else | |
252b5132 | 7101 | { |
df58fc94 RS |
7102 | used_at = 1; |
7103 | macro_build (NULL, "slt", "d,v,t", AT, treg, sreg); | |
7104 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, | |
7105 | &offset_expr, AT, ZERO); | |
252b5132 | 7106 | } |
252b5132 RH |
7107 | break; |
7108 | ||
7109 | case M_BLEL_I: | |
7110 | likely = 1; | |
7111 | case M_BLE_I: | |
7112 | maxnum = 0x7fffffff; | |
ca4e0257 | 7113 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
7114 | { |
7115 | maxnum <<= 16; | |
7116 | maxnum |= 0xffff; | |
7117 | maxnum <<= 16; | |
7118 | maxnum |= 0xffff; | |
7119 | } | |
7120 | if (imm_expr.X_op == O_constant | |
7121 | && imm_expr.X_add_number >= maxnum | |
ca4e0257 | 7122 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
7123 | goto do_true; |
7124 | if (imm_expr.X_op != O_constant) | |
7125 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 7126 | ++imm_expr.X_add_number; |
252b5132 RH |
7127 | /* FALLTHROUGH */ |
7128 | case M_BLT_I: | |
7129 | case M_BLTL_I: | |
7130 | if (mask == M_BLTL_I) | |
7131 | likely = 1; | |
7132 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
df58fc94 RS |
7133 | macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, sreg); |
7134 | else if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
7135 | macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, sreg); | |
7136 | else | |
252b5132 | 7137 | { |
df58fc94 RS |
7138 | used_at = 1; |
7139 | set_at (sreg, 0); | |
7140 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, | |
7141 | &offset_expr, AT, ZERO); | |
252b5132 | 7142 | } |
252b5132 RH |
7143 | break; |
7144 | ||
7145 | case M_BLEUL: | |
7146 | likely = 1; | |
7147 | case M_BLEU: | |
7148 | if (treg == 0) | |
df58fc94 RS |
7149 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, |
7150 | &offset_expr, sreg, ZERO); | |
7151 | else if (sreg == 0) | |
7152 | goto do_true; | |
7153 | else | |
252b5132 | 7154 | { |
df58fc94 RS |
7155 | used_at = 1; |
7156 | macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg); | |
7157 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, | |
7158 | &offset_expr, AT, ZERO); | |
252b5132 | 7159 | } |
252b5132 RH |
7160 | break; |
7161 | ||
7162 | case M_BLEUL_I: | |
7163 | likely = 1; | |
7164 | case M_BLEU_I: | |
7165 | if (sreg == 0 | |
ca4e0257 | 7166 | || (HAVE_32BIT_GPRS |
252b5132 | 7167 | && imm_expr.X_op == O_constant |
f01dc953 | 7168 | && imm_expr.X_add_number == -1)) |
252b5132 RH |
7169 | goto do_true; |
7170 | if (imm_expr.X_op != O_constant) | |
7171 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 7172 | ++imm_expr.X_add_number; |
252b5132 RH |
7173 | /* FALLTHROUGH */ |
7174 | case M_BLTU_I: | |
7175 | case M_BLTUL_I: | |
7176 | if (mask == M_BLTUL_I) | |
7177 | likely = 1; | |
7178 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
7179 | goto do_false; | |
df58fc94 RS |
7180 | else if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) |
7181 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, | |
7182 | &offset_expr, sreg, ZERO); | |
7183 | else | |
252b5132 | 7184 | { |
df58fc94 RS |
7185 | used_at = 1; |
7186 | set_at (sreg, 1); | |
7187 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, | |
7188 | &offset_expr, AT, ZERO); | |
252b5132 | 7189 | } |
252b5132 RH |
7190 | break; |
7191 | ||
7192 | case M_BLTL: | |
7193 | likely = 1; | |
7194 | case M_BLT: | |
7195 | if (treg == 0) | |
df58fc94 RS |
7196 | macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, sreg); |
7197 | else if (sreg == 0) | |
7198 | macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, treg); | |
7199 | else | |
252b5132 | 7200 | { |
df58fc94 RS |
7201 | used_at = 1; |
7202 | macro_build (NULL, "slt", "d,v,t", AT, sreg, treg); | |
7203 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, | |
7204 | &offset_expr, AT, ZERO); | |
252b5132 | 7205 | } |
252b5132 RH |
7206 | break; |
7207 | ||
7208 | case M_BLTUL: | |
7209 | likely = 1; | |
7210 | case M_BLTU: | |
7211 | if (treg == 0) | |
7212 | goto do_false; | |
df58fc94 RS |
7213 | else if (sreg == 0) |
7214 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, | |
7215 | &offset_expr, ZERO, treg); | |
7216 | else | |
252b5132 | 7217 | { |
df58fc94 RS |
7218 | used_at = 1; |
7219 | macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg); | |
7220 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, | |
7221 | &offset_expr, AT, ZERO); | |
252b5132 | 7222 | } |
252b5132 RH |
7223 | break; |
7224 | ||
5f74bc13 CD |
7225 | case M_DEXT: |
7226 | { | |
d5818fca MR |
7227 | /* Use unsigned arithmetic. */ |
7228 | addressT pos; | |
7229 | addressT size; | |
5f74bc13 | 7230 | |
90ecf173 | 7231 | if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant) |
5f74bc13 CD |
7232 | { |
7233 | as_bad (_("Unsupported large constant")); | |
7234 | pos = size = 1; | |
7235 | } | |
7236 | else | |
7237 | { | |
d5818fca MR |
7238 | pos = imm_expr.X_add_number; |
7239 | size = imm2_expr.X_add_number; | |
5f74bc13 CD |
7240 | } |
7241 | ||
7242 | if (pos > 63) | |
7243 | { | |
d5818fca | 7244 | as_bad (_("Improper position (%lu)"), (unsigned long) pos); |
5f74bc13 CD |
7245 | pos = 1; |
7246 | } | |
90ecf173 | 7247 | if (size == 0 || size > 64 || (pos + size - 1) > 63) |
5f74bc13 CD |
7248 | { |
7249 | as_bad (_("Improper extract size (%lu, position %lu)"), | |
d5818fca | 7250 | (unsigned long) size, (unsigned long) pos); |
5f74bc13 CD |
7251 | size = 1; |
7252 | } | |
7253 | ||
7254 | if (size <= 32 && pos < 32) | |
7255 | { | |
7256 | s = "dext"; | |
7257 | fmt = "t,r,+A,+C"; | |
7258 | } | |
7259 | else if (size <= 32) | |
7260 | { | |
7261 | s = "dextu"; | |
7262 | fmt = "t,r,+E,+H"; | |
7263 | } | |
7264 | else | |
7265 | { | |
7266 | s = "dextm"; | |
7267 | fmt = "t,r,+A,+G"; | |
7268 | } | |
d5818fca MR |
7269 | macro_build ((expressionS *) NULL, s, fmt, treg, sreg, (int) pos, |
7270 | (int) (size - 1)); | |
5f74bc13 | 7271 | } |
8fc2e39e | 7272 | break; |
5f74bc13 CD |
7273 | |
7274 | case M_DINS: | |
7275 | { | |
d5818fca MR |
7276 | /* Use unsigned arithmetic. */ |
7277 | addressT pos; | |
7278 | addressT size; | |
5f74bc13 | 7279 | |
90ecf173 | 7280 | if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant) |
5f74bc13 CD |
7281 | { |
7282 | as_bad (_("Unsupported large constant")); | |
7283 | pos = size = 1; | |
7284 | } | |
7285 | else | |
7286 | { | |
d5818fca MR |
7287 | pos = imm_expr.X_add_number; |
7288 | size = imm2_expr.X_add_number; | |
5f74bc13 CD |
7289 | } |
7290 | ||
7291 | if (pos > 63) | |
7292 | { | |
d5818fca | 7293 | as_bad (_("Improper position (%lu)"), (unsigned long) pos); |
5f74bc13 CD |
7294 | pos = 1; |
7295 | } | |
90ecf173 | 7296 | if (size == 0 || size > 64 || (pos + size - 1) > 63) |
5f74bc13 CD |
7297 | { |
7298 | as_bad (_("Improper insert size (%lu, position %lu)"), | |
d5818fca | 7299 | (unsigned long) size, (unsigned long) pos); |
5f74bc13 CD |
7300 | size = 1; |
7301 | } | |
7302 | ||
7303 | if (pos < 32 && (pos + size - 1) < 32) | |
7304 | { | |
7305 | s = "dins"; | |
7306 | fmt = "t,r,+A,+B"; | |
7307 | } | |
7308 | else if (pos >= 32) | |
7309 | { | |
7310 | s = "dinsu"; | |
7311 | fmt = "t,r,+E,+F"; | |
7312 | } | |
7313 | else | |
7314 | { | |
7315 | s = "dinsm"; | |
7316 | fmt = "t,r,+A,+F"; | |
7317 | } | |
750bdd57 AS |
7318 | macro_build ((expressionS *) NULL, s, fmt, treg, sreg, (int) pos, |
7319 | (int) (pos + size - 1)); | |
5f74bc13 | 7320 | } |
8fc2e39e | 7321 | break; |
5f74bc13 | 7322 | |
252b5132 RH |
7323 | case M_DDIV_3: |
7324 | dbl = 1; | |
7325 | case M_DIV_3: | |
7326 | s = "mflo"; | |
7327 | goto do_div3; | |
7328 | case M_DREM_3: | |
7329 | dbl = 1; | |
7330 | case M_REM_3: | |
7331 | s = "mfhi"; | |
7332 | do_div3: | |
7333 | if (treg == 0) | |
7334 | { | |
7335 | as_warn (_("Divide by zero.")); | |
7336 | if (mips_trap) | |
df58fc94 | 7337 | macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7); |
252b5132 | 7338 | else |
df58fc94 | 7339 | macro_build (NULL, "break", BRK_FMT, 7); |
8fc2e39e | 7340 | break; |
252b5132 RH |
7341 | } |
7342 | ||
7d10b47d | 7343 | start_noreorder (); |
252b5132 RH |
7344 | if (mips_trap) |
7345 | { | |
df58fc94 | 7346 | macro_build (NULL, "teq", TRAP_FMT, treg, ZERO, 7); |
67c0d1eb | 7347 | macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg); |
252b5132 RH |
7348 | } |
7349 | else | |
7350 | { | |
df58fc94 RS |
7351 | if (mips_opts.micromips) |
7352 | micromips_label_expr (&label_expr); | |
7353 | else | |
7354 | label_expr.X_add_number = 8; | |
7355 | macro_build (&label_expr, "bne", "s,t,p", treg, ZERO); | |
67c0d1eb | 7356 | macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg); |
df58fc94 RS |
7357 | macro_build (NULL, "break", BRK_FMT, 7); |
7358 | if (mips_opts.micromips) | |
7359 | micromips_add_label (); | |
252b5132 RH |
7360 | } |
7361 | expr1.X_add_number = -1; | |
8fc2e39e | 7362 | used_at = 1; |
f6a22291 | 7363 | load_register (AT, &expr1, dbl); |
df58fc94 RS |
7364 | if (mips_opts.micromips) |
7365 | micromips_label_expr (&label_expr); | |
7366 | else | |
7367 | label_expr.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16); | |
7368 | macro_build (&label_expr, "bne", "s,t,p", treg, AT); | |
252b5132 RH |
7369 | if (dbl) |
7370 | { | |
7371 | expr1.X_add_number = 1; | |
f6a22291 | 7372 | load_register (AT, &expr1, dbl); |
df58fc94 | 7373 | macro_build (NULL, "dsll32", SHFT_FMT, AT, AT, 31); |
252b5132 RH |
7374 | } |
7375 | else | |
7376 | { | |
7377 | expr1.X_add_number = 0x80000000; | |
df58fc94 | 7378 | macro_build (&expr1, "lui", LUI_FMT, AT, BFD_RELOC_HI16); |
252b5132 RH |
7379 | } |
7380 | if (mips_trap) | |
7381 | { | |
df58fc94 | 7382 | macro_build (NULL, "teq", TRAP_FMT, sreg, AT, 6); |
252b5132 RH |
7383 | /* We want to close the noreorder block as soon as possible, so |
7384 | that later insns are available for delay slot filling. */ | |
7d10b47d | 7385 | end_noreorder (); |
252b5132 RH |
7386 | } |
7387 | else | |
7388 | { | |
df58fc94 RS |
7389 | if (mips_opts.micromips) |
7390 | micromips_label_expr (&label_expr); | |
7391 | else | |
7392 | label_expr.X_add_number = 8; | |
7393 | macro_build (&label_expr, "bne", "s,t,p", sreg, AT); | |
a605d2b3 | 7394 | macro_build (NULL, "nop", ""); |
252b5132 RH |
7395 | |
7396 | /* We want to close the noreorder block as soon as possible, so | |
7397 | that later insns are available for delay slot filling. */ | |
7d10b47d | 7398 | end_noreorder (); |
252b5132 | 7399 | |
df58fc94 | 7400 | macro_build (NULL, "break", BRK_FMT, 6); |
252b5132 | 7401 | } |
df58fc94 RS |
7402 | if (mips_opts.micromips) |
7403 | micromips_add_label (); | |
7404 | macro_build (NULL, s, MFHL_FMT, dreg); | |
252b5132 RH |
7405 | break; |
7406 | ||
7407 | case M_DIV_3I: | |
7408 | s = "div"; | |
7409 | s2 = "mflo"; | |
7410 | goto do_divi; | |
7411 | case M_DIVU_3I: | |
7412 | s = "divu"; | |
7413 | s2 = "mflo"; | |
7414 | goto do_divi; | |
7415 | case M_REM_3I: | |
7416 | s = "div"; | |
7417 | s2 = "mfhi"; | |
7418 | goto do_divi; | |
7419 | case M_REMU_3I: | |
7420 | s = "divu"; | |
7421 | s2 = "mfhi"; | |
7422 | goto do_divi; | |
7423 | case M_DDIV_3I: | |
7424 | dbl = 1; | |
7425 | s = "ddiv"; | |
7426 | s2 = "mflo"; | |
7427 | goto do_divi; | |
7428 | case M_DDIVU_3I: | |
7429 | dbl = 1; | |
7430 | s = "ddivu"; | |
7431 | s2 = "mflo"; | |
7432 | goto do_divi; | |
7433 | case M_DREM_3I: | |
7434 | dbl = 1; | |
7435 | s = "ddiv"; | |
7436 | s2 = "mfhi"; | |
7437 | goto do_divi; | |
7438 | case M_DREMU_3I: | |
7439 | dbl = 1; | |
7440 | s = "ddivu"; | |
7441 | s2 = "mfhi"; | |
7442 | do_divi: | |
7443 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
7444 | { | |
7445 | as_warn (_("Divide by zero.")); | |
7446 | if (mips_trap) | |
df58fc94 | 7447 | macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7); |
252b5132 | 7448 | else |
df58fc94 | 7449 | macro_build (NULL, "break", BRK_FMT, 7); |
8fc2e39e | 7450 | break; |
252b5132 RH |
7451 | } |
7452 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
7453 | { | |
7454 | if (strcmp (s2, "mflo") == 0) | |
67c0d1eb | 7455 | move_register (dreg, sreg); |
252b5132 | 7456 | else |
c80c840e | 7457 | move_register (dreg, ZERO); |
8fc2e39e | 7458 | break; |
252b5132 RH |
7459 | } |
7460 | if (imm_expr.X_op == O_constant | |
7461 | && imm_expr.X_add_number == -1 | |
7462 | && s[strlen (s) - 1] != 'u') | |
7463 | { | |
7464 | if (strcmp (s2, "mflo") == 0) | |
7465 | { | |
67c0d1eb | 7466 | macro_build (NULL, dbl ? "dneg" : "neg", "d,w", dreg, sreg); |
252b5132 RH |
7467 | } |
7468 | else | |
c80c840e | 7469 | move_register (dreg, ZERO); |
8fc2e39e | 7470 | break; |
252b5132 RH |
7471 | } |
7472 | ||
8fc2e39e | 7473 | used_at = 1; |
67c0d1eb RS |
7474 | load_register (AT, &imm_expr, dbl); |
7475 | macro_build (NULL, s, "z,s,t", sreg, AT); | |
df58fc94 | 7476 | macro_build (NULL, s2, MFHL_FMT, dreg); |
252b5132 RH |
7477 | break; |
7478 | ||
7479 | case M_DIVU_3: | |
7480 | s = "divu"; | |
7481 | s2 = "mflo"; | |
7482 | goto do_divu3; | |
7483 | case M_REMU_3: | |
7484 | s = "divu"; | |
7485 | s2 = "mfhi"; | |
7486 | goto do_divu3; | |
7487 | case M_DDIVU_3: | |
7488 | s = "ddivu"; | |
7489 | s2 = "mflo"; | |
7490 | goto do_divu3; | |
7491 | case M_DREMU_3: | |
7492 | s = "ddivu"; | |
7493 | s2 = "mfhi"; | |
7494 | do_divu3: | |
7d10b47d | 7495 | start_noreorder (); |
252b5132 RH |
7496 | if (mips_trap) |
7497 | { | |
df58fc94 | 7498 | macro_build (NULL, "teq", TRAP_FMT, treg, ZERO, 7); |
67c0d1eb | 7499 | macro_build (NULL, s, "z,s,t", sreg, treg); |
252b5132 RH |
7500 | /* We want to close the noreorder block as soon as possible, so |
7501 | that later insns are available for delay slot filling. */ | |
7d10b47d | 7502 | end_noreorder (); |
252b5132 RH |
7503 | } |
7504 | else | |
7505 | { | |
df58fc94 RS |
7506 | if (mips_opts.micromips) |
7507 | micromips_label_expr (&label_expr); | |
7508 | else | |
7509 | label_expr.X_add_number = 8; | |
7510 | macro_build (&label_expr, "bne", "s,t,p", treg, ZERO); | |
67c0d1eb | 7511 | macro_build (NULL, s, "z,s,t", sreg, treg); |
252b5132 RH |
7512 | |
7513 | /* We want to close the noreorder block as soon as possible, so | |
7514 | that later insns are available for delay slot filling. */ | |
7d10b47d | 7515 | end_noreorder (); |
df58fc94 RS |
7516 | macro_build (NULL, "break", BRK_FMT, 7); |
7517 | if (mips_opts.micromips) | |
7518 | micromips_add_label (); | |
252b5132 | 7519 | } |
df58fc94 | 7520 | macro_build (NULL, s2, MFHL_FMT, dreg); |
8fc2e39e | 7521 | break; |
252b5132 | 7522 | |
1abe91b1 MR |
7523 | case M_DLCA_AB: |
7524 | dbl = 1; | |
7525 | case M_LCA_AB: | |
7526 | call = 1; | |
7527 | goto do_la; | |
252b5132 RH |
7528 | case M_DLA_AB: |
7529 | dbl = 1; | |
7530 | case M_LA_AB: | |
1abe91b1 | 7531 | do_la: |
252b5132 RH |
7532 | /* Load the address of a symbol into a register. If breg is not |
7533 | zero, we then add a base register to it. */ | |
7534 | ||
3bec30a8 TS |
7535 | if (dbl && HAVE_32BIT_GPRS) |
7536 | as_warn (_("dla used to load 32-bit register")); | |
7537 | ||
90ecf173 | 7538 | if (!dbl && HAVE_64BIT_OBJECTS) |
3bec30a8 TS |
7539 | as_warn (_("la used to load 64-bit address")); |
7540 | ||
0c11417f MR |
7541 | if (offset_expr.X_op == O_constant |
7542 | && offset_expr.X_add_number >= -0x8000 | |
7543 | && offset_expr.X_add_number < 0x8000) | |
7544 | { | |
aed1a261 | 7545 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, |
17a2f251 | 7546 | "t,r,j", treg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 7547 | break; |
0c11417f MR |
7548 | } |
7549 | ||
741fe287 | 7550 | if (mips_opts.at && (treg == breg)) |
afdbd6d0 CD |
7551 | { |
7552 | tempreg = AT; | |
7553 | used_at = 1; | |
7554 | } | |
7555 | else | |
7556 | { | |
7557 | tempreg = treg; | |
afdbd6d0 CD |
7558 | } |
7559 | ||
252b5132 RH |
7560 | if (offset_expr.X_op != O_symbol |
7561 | && offset_expr.X_op != O_constant) | |
7562 | { | |
f71d0d44 | 7563 | as_bad (_("Expression too complex")); |
252b5132 RH |
7564 | offset_expr.X_op = O_constant; |
7565 | } | |
7566 | ||
252b5132 | 7567 | if (offset_expr.X_op == O_constant) |
aed1a261 | 7568 | load_register (tempreg, &offset_expr, HAVE_64BIT_ADDRESSES); |
252b5132 RH |
7569 | else if (mips_pic == NO_PIC) |
7570 | { | |
d6bc6245 | 7571 | /* If this is a reference to a GP relative symbol, we want |
cdf6fd85 | 7572 | addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
7573 | Otherwise we want |
7574 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
7575 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
7576 | If we have a constant, we need two instructions anyhow, | |
d6bc6245 | 7577 | so we may as well always use the latter form. |
76b3015f | 7578 | |
6caf9ef4 TS |
7579 | With 64bit address space and a usable $at we want |
7580 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
7581 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
7582 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
7583 | daddiu $at,<sym> (BFD_RELOC_LO16) | |
7584 | dsll32 $tempreg,0 | |
7585 | daddu $tempreg,$tempreg,$at | |
7586 | ||
7587 | If $at is already in use, we use a path which is suboptimal | |
7588 | on superscalar processors. | |
7589 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
7590 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
7591 | dsll $tempreg,16 | |
7592 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
7593 | dsll $tempreg,16 | |
7594 | daddiu $tempreg,<sym> (BFD_RELOC_LO16) | |
7595 | ||
7596 | For GP relative symbols in 64bit address space we can use | |
7597 | the same sequence as in 32bit address space. */ | |
aed1a261 | 7598 | if (HAVE_64BIT_SYMBOLS) |
252b5132 | 7599 | { |
6caf9ef4 TS |
7600 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
7601 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) | |
7602 | { | |
7603 | relax_start (offset_expr.X_add_symbol); | |
7604 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
7605 | tempreg, mips_gp_register, BFD_RELOC_GPREL16); | |
7606 | relax_switch (); | |
7607 | } | |
d6bc6245 | 7608 | |
741fe287 | 7609 | if (used_at == 0 && mips_opts.at) |
98d3f06f | 7610 | { |
df58fc94 | 7611 | macro_build (&offset_expr, "lui", LUI_FMT, |
17a2f251 | 7612 | tempreg, BFD_RELOC_MIPS_HIGHEST); |
df58fc94 | 7613 | macro_build (&offset_expr, "lui", LUI_FMT, |
17a2f251 | 7614 | AT, BFD_RELOC_HI16_S); |
67c0d1eb | 7615 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 7616 | tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); |
67c0d1eb | 7617 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 7618 | AT, AT, BFD_RELOC_LO16); |
df58fc94 | 7619 | macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0); |
67c0d1eb | 7620 | macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT); |
98d3f06f KH |
7621 | used_at = 1; |
7622 | } | |
7623 | else | |
7624 | { | |
df58fc94 | 7625 | macro_build (&offset_expr, "lui", LUI_FMT, |
17a2f251 | 7626 | tempreg, BFD_RELOC_MIPS_HIGHEST); |
67c0d1eb | 7627 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 7628 | tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); |
df58fc94 | 7629 | macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16); |
67c0d1eb | 7630 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 7631 | tempreg, tempreg, BFD_RELOC_HI16_S); |
df58fc94 | 7632 | macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16); |
67c0d1eb | 7633 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 7634 | tempreg, tempreg, BFD_RELOC_LO16); |
98d3f06f | 7635 | } |
6caf9ef4 TS |
7636 | |
7637 | if (mips_relax.sequence) | |
7638 | relax_end (); | |
98d3f06f KH |
7639 | } |
7640 | else | |
7641 | { | |
7642 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET | |
6caf9ef4 | 7643 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
98d3f06f | 7644 | { |
4d7206a2 | 7645 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
7646 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
7647 | tempreg, mips_gp_register, BFD_RELOC_GPREL16); | |
4d7206a2 | 7648 | relax_switch (); |
98d3f06f | 7649 | } |
6943caf0 | 7650 | if (!IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) |
f71d0d44 | 7651 | as_bad (_("Offset too large")); |
67c0d1eb RS |
7652 | macro_build_lui (&offset_expr, tempreg); |
7653 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
7654 | tempreg, tempreg, BFD_RELOC_LO16); | |
4d7206a2 RS |
7655 | if (mips_relax.sequence) |
7656 | relax_end (); | |
98d3f06f | 7657 | } |
252b5132 | 7658 | } |
0a44bf69 | 7659 | else if (!mips_big_got && !HAVE_NEWABI) |
252b5132 | 7660 | { |
9117d219 NC |
7661 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
7662 | ||
252b5132 RH |
7663 | /* If this is a reference to an external symbol, and there |
7664 | is no constant, we want | |
7665 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
1abe91b1 | 7666 | or for lca or if tempreg is PIC_CALL_REG |
9117d219 | 7667 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
252b5132 RH |
7668 | For a local symbol, we want |
7669 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7670 | nop | |
7671 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
7672 | ||
7673 | If we have a small constant, and this is a reference to | |
7674 | an external symbol, we want | |
7675 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7676 | nop | |
7677 | addiu $tempreg,$tempreg,<constant> | |
7678 | For a local symbol, we want the same instruction | |
7679 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
7680 | addiu instruction. | |
7681 | ||
7682 | If we have a large constant, and this is a reference to | |
7683 | an external symbol, we want | |
7684 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7685 | lui $at,<hiconstant> | |
7686 | addiu $at,$at,<loconstant> | |
7687 | addu $tempreg,$tempreg,$at | |
7688 | For a local symbol, we want the same instruction | |
7689 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
ed6fb7bd | 7690 | addiu instruction. |
ed6fb7bd SC |
7691 | */ |
7692 | ||
4d7206a2 | 7693 | if (offset_expr.X_add_number == 0) |
252b5132 | 7694 | { |
0a44bf69 RS |
7695 | if (mips_pic == SVR4_PIC |
7696 | && breg == 0 | |
7697 | && (call || tempreg == PIC_CALL_REG)) | |
4d7206a2 RS |
7698 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16; |
7699 | ||
7700 | relax_start (offset_expr.X_add_symbol); | |
67c0d1eb RS |
7701 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
7702 | lw_reloc_type, mips_gp_register); | |
4d7206a2 | 7703 | if (breg != 0) |
252b5132 RH |
7704 | { |
7705 | /* We're going to put in an addu instruction using | |
7706 | tempreg, so we may as well insert the nop right | |
7707 | now. */ | |
269137b2 | 7708 | load_delay_nop (); |
252b5132 | 7709 | } |
4d7206a2 | 7710 | relax_switch (); |
67c0d1eb RS |
7711 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
7712 | tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 7713 | load_delay_nop (); |
67c0d1eb RS |
7714 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
7715 | tempreg, tempreg, BFD_RELOC_LO16); | |
4d7206a2 | 7716 | relax_end (); |
252b5132 RH |
7717 | /* FIXME: If breg == 0, and the next instruction uses |
7718 | $tempreg, then if this variant case is used an extra | |
7719 | nop will be generated. */ | |
7720 | } | |
4d7206a2 RS |
7721 | else if (offset_expr.X_add_number >= -0x8000 |
7722 | && offset_expr.X_add_number < 0x8000) | |
252b5132 | 7723 | { |
67c0d1eb | 7724 | load_got_offset (tempreg, &offset_expr); |
269137b2 | 7725 | load_delay_nop (); |
67c0d1eb | 7726 | add_got_offset (tempreg, &offset_expr); |
252b5132 RH |
7727 | } |
7728 | else | |
7729 | { | |
4d7206a2 RS |
7730 | expr1.X_add_number = offset_expr.X_add_number; |
7731 | offset_expr.X_add_number = | |
43c0598f | 7732 | SEXT_16BIT (offset_expr.X_add_number); |
67c0d1eb | 7733 | load_got_offset (tempreg, &offset_expr); |
f6a22291 | 7734 | offset_expr.X_add_number = expr1.X_add_number; |
252b5132 RH |
7735 | /* If we are going to add in a base register, and the |
7736 | target register and the base register are the same, | |
7737 | then we are using AT as a temporary register. Since | |
7738 | we want to load the constant into AT, we add our | |
7739 | current AT (from the global offset table) and the | |
7740 | register into the register now, and pretend we were | |
7741 | not using a base register. */ | |
67c0d1eb | 7742 | if (breg == treg) |
252b5132 | 7743 | { |
269137b2 | 7744 | load_delay_nop (); |
67c0d1eb | 7745 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7746 | treg, AT, breg); |
252b5132 RH |
7747 | breg = 0; |
7748 | tempreg = treg; | |
252b5132 | 7749 | } |
f6a22291 | 7750 | add_got_offset_hilo (tempreg, &offset_expr, AT); |
252b5132 RH |
7751 | used_at = 1; |
7752 | } | |
7753 | } | |
0a44bf69 | 7754 | else if (!mips_big_got && HAVE_NEWABI) |
f5040a92 | 7755 | { |
67c0d1eb | 7756 | int add_breg_early = 0; |
f5040a92 AO |
7757 | |
7758 | /* If this is a reference to an external, and there is no | |
7759 | constant, or local symbol (*), with or without a | |
7760 | constant, we want | |
7761 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
1abe91b1 | 7762 | or for lca or if tempreg is PIC_CALL_REG |
f5040a92 AO |
7763 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
7764 | ||
7765 | If we have a small constant, and this is a reference to | |
7766 | an external symbol, we want | |
7767 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
7768 | addiu $tempreg,$tempreg,<constant> | |
7769 | ||
7770 | If we have a large constant, and this is a reference to | |
7771 | an external symbol, we want | |
7772 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
7773 | lui $at,<hiconstant> | |
7774 | addiu $at,$at,<loconstant> | |
7775 | addu $tempreg,$tempreg,$at | |
7776 | ||
7777 | (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for | |
7778 | local symbols, even though it introduces an additional | |
7779 | instruction. */ | |
7780 | ||
f5040a92 AO |
7781 | if (offset_expr.X_add_number) |
7782 | { | |
4d7206a2 | 7783 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
7784 | offset_expr.X_add_number = 0; |
7785 | ||
4d7206a2 | 7786 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
7787 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
7788 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
7789 | |
7790 | if (expr1.X_add_number >= -0x8000 | |
7791 | && expr1.X_add_number < 0x8000) | |
7792 | { | |
67c0d1eb RS |
7793 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
7794 | tempreg, tempreg, BFD_RELOC_LO16); | |
f5040a92 | 7795 | } |
ecd13cd3 | 7796 | else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000)) |
f5040a92 | 7797 | { |
f5040a92 AO |
7798 | /* If we are going to add in a base register, and the |
7799 | target register and the base register are the same, | |
7800 | then we are using AT as a temporary register. Since | |
7801 | we want to load the constant into AT, we add our | |
7802 | current AT (from the global offset table) and the | |
7803 | register into the register now, and pretend we were | |
7804 | not using a base register. */ | |
7805 | if (breg != treg) | |
7806 | dreg = tempreg; | |
7807 | else | |
7808 | { | |
9c2799c2 | 7809 | gas_assert (tempreg == AT); |
67c0d1eb RS |
7810 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
7811 | treg, AT, breg); | |
f5040a92 | 7812 | dreg = treg; |
67c0d1eb | 7813 | add_breg_early = 1; |
f5040a92 AO |
7814 | } |
7815 | ||
f6a22291 | 7816 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 7817 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7818 | dreg, dreg, AT); |
f5040a92 | 7819 | |
f5040a92 AO |
7820 | used_at = 1; |
7821 | } | |
7822 | else | |
7823 | as_bad (_("PIC code offset overflow (max 32 signed bits)")); | |
7824 | ||
4d7206a2 | 7825 | relax_switch (); |
f5040a92 AO |
7826 | offset_expr.X_add_number = expr1.X_add_number; |
7827 | ||
67c0d1eb RS |
7828 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
7829 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
7830 | if (add_breg_early) | |
f5040a92 | 7831 | { |
67c0d1eb | 7832 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
f899b4b8 | 7833 | treg, tempreg, breg); |
f5040a92 AO |
7834 | breg = 0; |
7835 | tempreg = treg; | |
7836 | } | |
4d7206a2 | 7837 | relax_end (); |
f5040a92 | 7838 | } |
4d7206a2 | 7839 | else if (breg == 0 && (call || tempreg == PIC_CALL_REG)) |
f5040a92 | 7840 | { |
4d7206a2 | 7841 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
7842 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
7843 | BFD_RELOC_MIPS_CALL16, mips_gp_register); | |
4d7206a2 | 7844 | relax_switch (); |
67c0d1eb RS |
7845 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
7846 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
4d7206a2 | 7847 | relax_end (); |
f5040a92 | 7848 | } |
4d7206a2 | 7849 | else |
f5040a92 | 7850 | { |
67c0d1eb RS |
7851 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
7852 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
7853 | } |
7854 | } | |
0a44bf69 | 7855 | else if (mips_big_got && !HAVE_NEWABI) |
252b5132 | 7856 | { |
67c0d1eb | 7857 | int gpdelay; |
9117d219 NC |
7858 | int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; |
7859 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; | |
ed6fb7bd | 7860 | int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
252b5132 RH |
7861 | |
7862 | /* This is the large GOT case. If this is a reference to an | |
7863 | external symbol, and there is no constant, we want | |
7864 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
7865 | addu $tempreg,$tempreg,$gp | |
7866 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
1abe91b1 | 7867 | or for lca or if tempreg is PIC_CALL_REG |
9117d219 NC |
7868 | lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) |
7869 | addu $tempreg,$tempreg,$gp | |
7870 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) | |
252b5132 RH |
7871 | For a local symbol, we want |
7872 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7873 | nop | |
7874 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
7875 | ||
7876 | If we have a small constant, and this is a reference to | |
7877 | an external symbol, we want | |
7878 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
7879 | addu $tempreg,$tempreg,$gp | |
7880 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
7881 | nop | |
7882 | addiu $tempreg,$tempreg,<constant> | |
7883 | For a local symbol, we want | |
7884 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7885 | nop | |
7886 | addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16) | |
7887 | ||
7888 | If we have a large constant, and this is a reference to | |
7889 | an external symbol, we want | |
7890 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
7891 | addu $tempreg,$tempreg,$gp | |
7892 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
7893 | lui $at,<hiconstant> | |
7894 | addiu $at,$at,<loconstant> | |
7895 | addu $tempreg,$tempreg,$at | |
7896 | For a local symbol, we want | |
7897 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7898 | lui $at,<hiconstant> | |
7899 | addiu $at,$at,<loconstant> (BFD_RELOC_LO16) | |
7900 | addu $tempreg,$tempreg,$at | |
f5040a92 | 7901 | */ |
438c16b8 | 7902 | |
252b5132 RH |
7903 | expr1.X_add_number = offset_expr.X_add_number; |
7904 | offset_expr.X_add_number = 0; | |
4d7206a2 | 7905 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 7906 | gpdelay = reg_needs_delay (mips_gp_register); |
1abe91b1 MR |
7907 | if (expr1.X_add_number == 0 && breg == 0 |
7908 | && (call || tempreg == PIC_CALL_REG)) | |
9117d219 NC |
7909 | { |
7910 | lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; | |
7911 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; | |
7912 | } | |
df58fc94 | 7913 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type); |
67c0d1eb | 7914 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7915 | tempreg, tempreg, mips_gp_register); |
67c0d1eb | 7916 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
17a2f251 | 7917 | tempreg, lw_reloc_type, tempreg); |
252b5132 RH |
7918 | if (expr1.X_add_number == 0) |
7919 | { | |
67c0d1eb | 7920 | if (breg != 0) |
252b5132 RH |
7921 | { |
7922 | /* We're going to put in an addu instruction using | |
7923 | tempreg, so we may as well insert the nop right | |
7924 | now. */ | |
269137b2 | 7925 | load_delay_nop (); |
252b5132 | 7926 | } |
252b5132 RH |
7927 | } |
7928 | else if (expr1.X_add_number >= -0x8000 | |
7929 | && expr1.X_add_number < 0x8000) | |
7930 | { | |
269137b2 | 7931 | load_delay_nop (); |
67c0d1eb | 7932 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 7933 | tempreg, tempreg, BFD_RELOC_LO16); |
252b5132 RH |
7934 | } |
7935 | else | |
7936 | { | |
252b5132 RH |
7937 | /* If we are going to add in a base register, and the |
7938 | target register and the base register are the same, | |
7939 | then we are using AT as a temporary register. Since | |
7940 | we want to load the constant into AT, we add our | |
7941 | current AT (from the global offset table) and the | |
7942 | register into the register now, and pretend we were | |
7943 | not using a base register. */ | |
7944 | if (breg != treg) | |
67c0d1eb | 7945 | dreg = tempreg; |
252b5132 RH |
7946 | else |
7947 | { | |
9c2799c2 | 7948 | gas_assert (tempreg == AT); |
269137b2 | 7949 | load_delay_nop (); |
67c0d1eb | 7950 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7951 | treg, AT, breg); |
252b5132 | 7952 | dreg = treg; |
252b5132 RH |
7953 | } |
7954 | ||
f6a22291 | 7955 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 7956 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT); |
252b5132 | 7957 | |
252b5132 RH |
7958 | used_at = 1; |
7959 | } | |
43c0598f | 7960 | offset_expr.X_add_number = SEXT_16BIT (expr1.X_add_number); |
4d7206a2 | 7961 | relax_switch (); |
252b5132 | 7962 | |
67c0d1eb | 7963 | if (gpdelay) |
252b5132 RH |
7964 | { |
7965 | /* This is needed because this instruction uses $gp, but | |
f5040a92 | 7966 | the first instruction on the main stream does not. */ |
67c0d1eb | 7967 | macro_build (NULL, "nop", ""); |
252b5132 | 7968 | } |
ed6fb7bd | 7969 | |
67c0d1eb RS |
7970 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
7971 | local_reloc_type, mips_gp_register); | |
f5040a92 | 7972 | if (expr1.X_add_number >= -0x8000 |
252b5132 RH |
7973 | && expr1.X_add_number < 0x8000) |
7974 | { | |
269137b2 | 7975 | load_delay_nop (); |
67c0d1eb RS |
7976 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
7977 | tempreg, tempreg, BFD_RELOC_LO16); | |
252b5132 | 7978 | /* FIXME: If add_number is 0, and there was no base |
f5040a92 AO |
7979 | register, the external symbol case ended with a load, |
7980 | so if the symbol turns out to not be external, and | |
7981 | the next instruction uses tempreg, an unnecessary nop | |
7982 | will be inserted. */ | |
252b5132 RH |
7983 | } |
7984 | else | |
7985 | { | |
7986 | if (breg == treg) | |
7987 | { | |
7988 | /* We must add in the base register now, as in the | |
f5040a92 | 7989 | external symbol case. */ |
9c2799c2 | 7990 | gas_assert (tempreg == AT); |
269137b2 | 7991 | load_delay_nop (); |
67c0d1eb | 7992 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7993 | treg, AT, breg); |
252b5132 RH |
7994 | tempreg = treg; |
7995 | /* We set breg to 0 because we have arranged to add | |
f5040a92 | 7996 | it in in both cases. */ |
252b5132 RH |
7997 | breg = 0; |
7998 | } | |
7999 | ||
67c0d1eb RS |
8000 | macro_build_lui (&expr1, AT); |
8001 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
17a2f251 | 8002 | AT, AT, BFD_RELOC_LO16); |
67c0d1eb | 8003 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 8004 | tempreg, tempreg, AT); |
8fc2e39e | 8005 | used_at = 1; |
252b5132 | 8006 | } |
4d7206a2 | 8007 | relax_end (); |
252b5132 | 8008 | } |
0a44bf69 | 8009 | else if (mips_big_got && HAVE_NEWABI) |
f5040a92 | 8010 | { |
f5040a92 AO |
8011 | int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; |
8012 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; | |
67c0d1eb | 8013 | int add_breg_early = 0; |
f5040a92 AO |
8014 | |
8015 | /* This is the large GOT case. If this is a reference to an | |
8016 | external symbol, and there is no constant, we want | |
8017 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
8018 | add $tempreg,$tempreg,$gp | |
8019 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
1abe91b1 | 8020 | or for lca or if tempreg is PIC_CALL_REG |
f5040a92 AO |
8021 | lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) |
8022 | add $tempreg,$tempreg,$gp | |
8023 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) | |
8024 | ||
8025 | If we have a small constant, and this is a reference to | |
8026 | an external symbol, we want | |
8027 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
8028 | add $tempreg,$tempreg,$gp | |
8029 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
8030 | addi $tempreg,$tempreg,<constant> | |
8031 | ||
8032 | If we have a large constant, and this is a reference to | |
8033 | an external symbol, we want | |
8034 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
8035 | addu $tempreg,$tempreg,$gp | |
8036 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
8037 | lui $at,<hiconstant> | |
8038 | addi $at,$at,<loconstant> | |
8039 | add $tempreg,$tempreg,$at | |
8040 | ||
8041 | If we have NewABI, and we know it's a local symbol, we want | |
8042 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
8043 | addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) | |
8044 | otherwise we have to resort to GOT_HI16/GOT_LO16. */ | |
8045 | ||
4d7206a2 | 8046 | relax_start (offset_expr.X_add_symbol); |
f5040a92 | 8047 | |
4d7206a2 | 8048 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
8049 | offset_expr.X_add_number = 0; |
8050 | ||
1abe91b1 MR |
8051 | if (expr1.X_add_number == 0 && breg == 0 |
8052 | && (call || tempreg == PIC_CALL_REG)) | |
f5040a92 AO |
8053 | { |
8054 | lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; | |
8055 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; | |
8056 | } | |
df58fc94 | 8057 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type); |
67c0d1eb | 8058 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 8059 | tempreg, tempreg, mips_gp_register); |
67c0d1eb RS |
8060 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
8061 | tempreg, lw_reloc_type, tempreg); | |
f5040a92 AO |
8062 | |
8063 | if (expr1.X_add_number == 0) | |
4d7206a2 | 8064 | ; |
f5040a92 AO |
8065 | else if (expr1.X_add_number >= -0x8000 |
8066 | && expr1.X_add_number < 0x8000) | |
8067 | { | |
67c0d1eb | 8068 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 8069 | tempreg, tempreg, BFD_RELOC_LO16); |
f5040a92 | 8070 | } |
ecd13cd3 | 8071 | else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000)) |
f5040a92 | 8072 | { |
f5040a92 AO |
8073 | /* If we are going to add in a base register, and the |
8074 | target register and the base register are the same, | |
8075 | then we are using AT as a temporary register. Since | |
8076 | we want to load the constant into AT, we add our | |
8077 | current AT (from the global offset table) and the | |
8078 | register into the register now, and pretend we were | |
8079 | not using a base register. */ | |
8080 | if (breg != treg) | |
8081 | dreg = tempreg; | |
8082 | else | |
8083 | { | |
9c2799c2 | 8084 | gas_assert (tempreg == AT); |
67c0d1eb | 8085 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 8086 | treg, AT, breg); |
f5040a92 | 8087 | dreg = treg; |
67c0d1eb | 8088 | add_breg_early = 1; |
f5040a92 AO |
8089 | } |
8090 | ||
f6a22291 | 8091 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 8092 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT); |
f5040a92 | 8093 | |
f5040a92 AO |
8094 | used_at = 1; |
8095 | } | |
8096 | else | |
8097 | as_bad (_("PIC code offset overflow (max 32 signed bits)")); | |
8098 | ||
4d7206a2 | 8099 | relax_switch (); |
f5040a92 | 8100 | offset_expr.X_add_number = expr1.X_add_number; |
67c0d1eb RS |
8101 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
8102 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
8103 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, | |
8104 | tempreg, BFD_RELOC_MIPS_GOT_OFST); | |
8105 | if (add_breg_early) | |
f5040a92 | 8106 | { |
67c0d1eb | 8107 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 8108 | treg, tempreg, breg); |
f5040a92 AO |
8109 | breg = 0; |
8110 | tempreg = treg; | |
8111 | } | |
4d7206a2 | 8112 | relax_end (); |
f5040a92 | 8113 | } |
252b5132 RH |
8114 | else |
8115 | abort (); | |
8116 | ||
8117 | if (breg != 0) | |
aed1a261 | 8118 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", treg, tempreg, breg); |
252b5132 RH |
8119 | break; |
8120 | ||
52b6b6b9 | 8121 | case M_MSGSND: |
df58fc94 | 8122 | gas_assert (!mips_opts.micromips); |
52b6b6b9 JM |
8123 | { |
8124 | unsigned long temp = (treg << 16) | (0x01); | |
8125 | macro_build (NULL, "c2", "C", temp); | |
8126 | } | |
c7af4273 | 8127 | break; |
52b6b6b9 JM |
8128 | |
8129 | case M_MSGLD: | |
df58fc94 | 8130 | gas_assert (!mips_opts.micromips); |
52b6b6b9 JM |
8131 | { |
8132 | unsigned long temp = (0x02); | |
8133 | macro_build (NULL, "c2", "C", temp); | |
8134 | } | |
c7af4273 | 8135 | break; |
52b6b6b9 JM |
8136 | |
8137 | case M_MSGLD_T: | |
df58fc94 | 8138 | gas_assert (!mips_opts.micromips); |
52b6b6b9 JM |
8139 | { |
8140 | unsigned long temp = (treg << 16) | (0x02); | |
8141 | macro_build (NULL, "c2", "C", temp); | |
8142 | } | |
c7af4273 | 8143 | break; |
52b6b6b9 JM |
8144 | |
8145 | case M_MSGWAIT: | |
df58fc94 | 8146 | gas_assert (!mips_opts.micromips); |
52b6b6b9 | 8147 | macro_build (NULL, "c2", "C", 3); |
c7af4273 | 8148 | break; |
52b6b6b9 JM |
8149 | |
8150 | case M_MSGWAIT_T: | |
df58fc94 | 8151 | gas_assert (!mips_opts.micromips); |
52b6b6b9 JM |
8152 | { |
8153 | unsigned long temp = (treg << 16) | 0x03; | |
8154 | macro_build (NULL, "c2", "C", temp); | |
8155 | } | |
c7af4273 | 8156 | break; |
52b6b6b9 | 8157 | |
252b5132 RH |
8158 | case M_J_A: |
8159 | /* The j instruction may not be used in PIC code, since it | |
8160 | requires an absolute address. We convert it to a b | |
8161 | instruction. */ | |
8162 | if (mips_pic == NO_PIC) | |
67c0d1eb | 8163 | macro_build (&offset_expr, "j", "a"); |
252b5132 | 8164 | else |
67c0d1eb | 8165 | macro_build (&offset_expr, "b", "p"); |
8fc2e39e | 8166 | break; |
252b5132 RH |
8167 | |
8168 | /* The jal instructions must be handled as macros because when | |
8169 | generating PIC code they expand to multi-instruction | |
8170 | sequences. Normally they are simple instructions. */ | |
df58fc94 RS |
8171 | case M_JALS_1: |
8172 | dreg = RA; | |
8173 | /* Fall through. */ | |
8174 | case M_JALS_2: | |
8175 | gas_assert (mips_opts.micromips); | |
8176 | jals = 1; | |
8177 | goto jal; | |
252b5132 RH |
8178 | case M_JAL_1: |
8179 | dreg = RA; | |
8180 | /* Fall through. */ | |
8181 | case M_JAL_2: | |
df58fc94 | 8182 | jal: |
3e722fb5 | 8183 | if (mips_pic == NO_PIC) |
df58fc94 RS |
8184 | { |
8185 | s = jals ? "jalrs" : "jalr"; | |
e64af278 MR |
8186 | if (mips_opts.micromips |
8187 | && dreg == RA | |
8188 | && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) | |
df58fc94 RS |
8189 | macro_build (NULL, s, "mj", sreg); |
8190 | else | |
8191 | macro_build (NULL, s, JALR_FMT, dreg, sreg); | |
8192 | } | |
0a44bf69 | 8193 | else |
252b5132 | 8194 | { |
df58fc94 RS |
8195 | int cprestore = (mips_pic == SVR4_PIC && !HAVE_NEWABI |
8196 | && mips_cprestore_offset >= 0); | |
8197 | ||
252b5132 RH |
8198 | if (sreg != PIC_CALL_REG) |
8199 | as_warn (_("MIPS PIC call to register other than $25")); | |
bdaaa2e1 | 8200 | |
df58fc94 RS |
8201 | s = (mips_opts.micromips && (!mips_opts.noreorder || cprestore) |
8202 | ? "jalrs" : "jalr"); | |
e64af278 MR |
8203 | if (mips_opts.micromips |
8204 | && dreg == RA | |
8205 | && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) | |
df58fc94 RS |
8206 | macro_build (NULL, s, "mj", sreg); |
8207 | else | |
8208 | macro_build (NULL, s, JALR_FMT, dreg, sreg); | |
0a44bf69 | 8209 | if (mips_pic == SVR4_PIC && !HAVE_NEWABI) |
252b5132 | 8210 | { |
6478892d TS |
8211 | if (mips_cprestore_offset < 0) |
8212 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
8213 | else | |
8214 | { | |
90ecf173 | 8215 | if (!mips_frame_reg_valid) |
7a621144 DJ |
8216 | { |
8217 | as_warn (_("No .frame pseudo-op used in PIC code")); | |
8218 | /* Quiet this warning. */ | |
8219 | mips_frame_reg_valid = 1; | |
8220 | } | |
90ecf173 | 8221 | if (!mips_cprestore_valid) |
7a621144 DJ |
8222 | { |
8223 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
8224 | /* Quiet this warning. */ | |
8225 | mips_cprestore_valid = 1; | |
8226 | } | |
d3fca0b5 MR |
8227 | if (mips_opts.noreorder) |
8228 | macro_build (NULL, "nop", ""); | |
6478892d | 8229 | expr1.X_add_number = mips_cprestore_offset; |
67c0d1eb | 8230 | macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN, |
f899b4b8 | 8231 | mips_gp_register, |
256ab948 TS |
8232 | mips_frame_reg, |
8233 | HAVE_64BIT_ADDRESSES); | |
6478892d | 8234 | } |
252b5132 RH |
8235 | } |
8236 | } | |
252b5132 | 8237 | |
8fc2e39e | 8238 | break; |
252b5132 | 8239 | |
df58fc94 RS |
8240 | case M_JALS_A: |
8241 | gas_assert (mips_opts.micromips); | |
8242 | jals = 1; | |
8243 | /* Fall through. */ | |
252b5132 RH |
8244 | case M_JAL_A: |
8245 | if (mips_pic == NO_PIC) | |
df58fc94 | 8246 | macro_build (&offset_expr, jals ? "jals" : "jal", "a"); |
252b5132 RH |
8247 | else if (mips_pic == SVR4_PIC) |
8248 | { | |
8249 | /* If this is a reference to an external symbol, and we are | |
8250 | using a small GOT, we want | |
8251 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16) | |
8252 | nop | |
f9419b05 | 8253 | jalr $ra,$25 |
252b5132 RH |
8254 | nop |
8255 | lw $gp,cprestore($sp) | |
8256 | The cprestore value is set using the .cprestore | |
8257 | pseudo-op. If we are using a big GOT, we want | |
8258 | lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16) | |
8259 | addu $25,$25,$gp | |
8260 | lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16) | |
8261 | nop | |
f9419b05 | 8262 | jalr $ra,$25 |
252b5132 RH |
8263 | nop |
8264 | lw $gp,cprestore($sp) | |
8265 | If the symbol is not external, we want | |
8266 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
8267 | nop | |
8268 | addiu $25,$25,<sym> (BFD_RELOC_LO16) | |
f9419b05 | 8269 | jalr $ra,$25 |
252b5132 | 8270 | nop |
438c16b8 | 8271 | lw $gp,cprestore($sp) |
f5040a92 AO |
8272 | |
8273 | For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16 | |
8274 | sequences above, minus nops, unless the symbol is local, | |
8275 | which enables us to use GOT_PAGE/GOT_OFST (big got) or | |
8276 | GOT_DISP. */ | |
438c16b8 | 8277 | if (HAVE_NEWABI) |
252b5132 | 8278 | { |
90ecf173 | 8279 | if (!mips_big_got) |
f5040a92 | 8280 | { |
4d7206a2 | 8281 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
8282 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
8283 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL16, | |
f5040a92 | 8284 | mips_gp_register); |
4d7206a2 | 8285 | relax_switch (); |
67c0d1eb RS |
8286 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
8287 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT_DISP, | |
4d7206a2 RS |
8288 | mips_gp_register); |
8289 | relax_end (); | |
f5040a92 AO |
8290 | } |
8291 | else | |
8292 | { | |
4d7206a2 | 8293 | relax_start (offset_expr.X_add_symbol); |
df58fc94 | 8294 | macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG, |
67c0d1eb RS |
8295 | BFD_RELOC_MIPS_CALL_HI16); |
8296 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG, | |
8297 | PIC_CALL_REG, mips_gp_register); | |
8298 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", | |
8299 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16, | |
8300 | PIC_CALL_REG); | |
4d7206a2 | 8301 | relax_switch (); |
67c0d1eb RS |
8302 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
8303 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT_PAGE, | |
8304 | mips_gp_register); | |
8305 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
8306 | PIC_CALL_REG, PIC_CALL_REG, | |
17a2f251 | 8307 | BFD_RELOC_MIPS_GOT_OFST); |
4d7206a2 | 8308 | relax_end (); |
f5040a92 | 8309 | } |
684022ea | 8310 | |
df58fc94 | 8311 | macro_build_jalr (&offset_expr, 0); |
252b5132 RH |
8312 | } |
8313 | else | |
8314 | { | |
4d7206a2 | 8315 | relax_start (offset_expr.X_add_symbol); |
90ecf173 | 8316 | if (!mips_big_got) |
438c16b8 | 8317 | { |
67c0d1eb RS |
8318 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
8319 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL16, | |
17a2f251 | 8320 | mips_gp_register); |
269137b2 | 8321 | load_delay_nop (); |
4d7206a2 | 8322 | relax_switch (); |
438c16b8 | 8323 | } |
252b5132 | 8324 | else |
252b5132 | 8325 | { |
67c0d1eb RS |
8326 | int gpdelay; |
8327 | ||
8328 | gpdelay = reg_needs_delay (mips_gp_register); | |
df58fc94 | 8329 | macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG, |
67c0d1eb RS |
8330 | BFD_RELOC_MIPS_CALL_HI16); |
8331 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG, | |
8332 | PIC_CALL_REG, mips_gp_register); | |
8333 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", | |
8334 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16, | |
8335 | PIC_CALL_REG); | |
269137b2 | 8336 | load_delay_nop (); |
4d7206a2 | 8337 | relax_switch (); |
67c0d1eb RS |
8338 | if (gpdelay) |
8339 | macro_build (NULL, "nop", ""); | |
252b5132 | 8340 | } |
67c0d1eb RS |
8341 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
8342 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT16, | |
4d7206a2 | 8343 | mips_gp_register); |
269137b2 | 8344 | load_delay_nop (); |
67c0d1eb RS |
8345 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
8346 | PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16); | |
4d7206a2 | 8347 | relax_end (); |
df58fc94 | 8348 | macro_build_jalr (&offset_expr, mips_cprestore_offset >= 0); |
438c16b8 | 8349 | |
6478892d TS |
8350 | if (mips_cprestore_offset < 0) |
8351 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
8352 | else | |
8353 | { | |
90ecf173 | 8354 | if (!mips_frame_reg_valid) |
7a621144 DJ |
8355 | { |
8356 | as_warn (_("No .frame pseudo-op used in PIC code")); | |
8357 | /* Quiet this warning. */ | |
8358 | mips_frame_reg_valid = 1; | |
8359 | } | |
90ecf173 | 8360 | if (!mips_cprestore_valid) |
7a621144 DJ |
8361 | { |
8362 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
8363 | /* Quiet this warning. */ | |
8364 | mips_cprestore_valid = 1; | |
8365 | } | |
6478892d | 8366 | if (mips_opts.noreorder) |
67c0d1eb | 8367 | macro_build (NULL, "nop", ""); |
6478892d | 8368 | expr1.X_add_number = mips_cprestore_offset; |
67c0d1eb | 8369 | macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN, |
f899b4b8 | 8370 | mips_gp_register, |
256ab948 TS |
8371 | mips_frame_reg, |
8372 | HAVE_64BIT_ADDRESSES); | |
6478892d | 8373 | } |
252b5132 RH |
8374 | } |
8375 | } | |
0a44bf69 RS |
8376 | else if (mips_pic == VXWORKS_PIC) |
8377 | as_bad (_("Non-PIC jump used in PIC library")); | |
252b5132 RH |
8378 | else |
8379 | abort (); | |
8380 | ||
8fc2e39e | 8381 | break; |
252b5132 | 8382 | |
7f3c4072 CM |
8383 | case M_LBUE_AB: |
8384 | ab = 1; | |
8385 | case M_LBUE_OB: | |
8386 | s = "lbue"; | |
8387 | fmt = "t,+j(b)"; | |
8388 | offbits = 9; | |
8389 | goto ld_st; | |
8390 | case M_LHUE_AB: | |
8391 | ab = 1; | |
8392 | case M_LHUE_OB: | |
8393 | s = "lhue"; | |
8394 | fmt = "t,+j(b)"; | |
8395 | offbits = 9; | |
8396 | goto ld_st; | |
8397 | case M_LBE_AB: | |
8398 | ab = 1; | |
8399 | case M_LBE_OB: | |
8400 | s = "lbe"; | |
8401 | fmt = "t,+j(b)"; | |
8402 | offbits = 9; | |
8403 | goto ld_st; | |
8404 | case M_LHE_AB: | |
8405 | ab = 1; | |
8406 | case M_LHE_OB: | |
8407 | s = "lhe"; | |
8408 | fmt = "t,+j(b)"; | |
8409 | offbits = 9; | |
8410 | goto ld_st; | |
8411 | case M_LLE_AB: | |
8412 | ab = 1; | |
8413 | case M_LLE_OB: | |
8414 | s = "lle"; | |
8415 | fmt = "t,+j(b)"; | |
8416 | offbits = 9; | |
8417 | goto ld_st; | |
8418 | case M_LWE_AB: | |
8419 | ab = 1; | |
8420 | case M_LWE_OB: | |
8421 | s = "lwe"; | |
8422 | fmt = "t,+j(b)"; | |
8423 | offbits = 9; | |
8424 | goto ld_st; | |
8425 | case M_LWLE_AB: | |
8426 | ab = 1; | |
8427 | case M_LWLE_OB: | |
8428 | s = "lwle"; | |
8429 | fmt = "t,+j(b)"; | |
8430 | offbits = 9; | |
8431 | goto ld_st; | |
8432 | case M_LWRE_AB: | |
8433 | ab = 1; | |
8434 | case M_LWRE_OB: | |
8435 | s = "lwre"; | |
8436 | fmt = "t,+j(b)"; | |
8437 | offbits = 9; | |
8438 | goto ld_st; | |
8439 | case M_SBE_AB: | |
8440 | ab = 1; | |
8441 | case M_SBE_OB: | |
8442 | s = "sbe"; | |
8443 | fmt = "t,+j(b)"; | |
8444 | offbits = 9; | |
8445 | goto ld_st; | |
8446 | case M_SCE_AB: | |
8447 | ab = 1; | |
8448 | case M_SCE_OB: | |
8449 | s = "sce"; | |
8450 | fmt = "t,+j(b)"; | |
8451 | offbits = 9; | |
8452 | goto ld_st; | |
8453 | case M_SHE_AB: | |
8454 | ab = 1; | |
8455 | case M_SHE_OB: | |
8456 | s = "she"; | |
8457 | fmt = "t,+j(b)"; | |
8458 | offbits = 9; | |
8459 | goto ld_st; | |
8460 | case M_SWE_AB: | |
8461 | ab = 1; | |
8462 | case M_SWE_OB: | |
8463 | s = "swe"; | |
8464 | fmt = "t,+j(b)"; | |
8465 | offbits = 9; | |
8466 | goto ld_st; | |
8467 | case M_SWLE_AB: | |
8468 | ab = 1; | |
8469 | case M_SWLE_OB: | |
8470 | s = "swle"; | |
8471 | fmt = "t,+j(b)"; | |
8472 | offbits = 9; | |
8473 | goto ld_st; | |
8474 | case M_SWRE_AB: | |
8475 | ab = 1; | |
8476 | case M_SWRE_OB: | |
8477 | s = "swre"; | |
8478 | fmt = "t,+j(b)"; | |
8479 | offbits = 9; | |
8480 | goto ld_st; | |
dec0624d MR |
8481 | case M_ACLR_AB: |
8482 | ab = 1; | |
8483 | case M_ACLR_OB: | |
8484 | s = "aclr"; | |
8485 | treg = EXTRACT_OPERAND (mips_opts.micromips, 3BITPOS, *ip); | |
8486 | fmt = "\\,~(b)"; | |
7f3c4072 | 8487 | offbits = 12; |
dec0624d MR |
8488 | goto ld_st; |
8489 | case M_ASET_AB: | |
8490 | ab = 1; | |
8491 | case M_ASET_OB: | |
8492 | s = "aset"; | |
8493 | treg = EXTRACT_OPERAND (mips_opts.micromips, 3BITPOS, *ip); | |
8494 | fmt = "\\,~(b)"; | |
7f3c4072 | 8495 | offbits = 12; |
dec0624d | 8496 | goto ld_st; |
252b5132 | 8497 | case M_LB_AB: |
df58fc94 | 8498 | ab = 1; |
252b5132 | 8499 | s = "lb"; |
df58fc94 | 8500 | fmt = "t,o(b)"; |
252b5132 RH |
8501 | goto ld; |
8502 | case M_LBU_AB: | |
df58fc94 | 8503 | ab = 1; |
252b5132 | 8504 | s = "lbu"; |
df58fc94 | 8505 | fmt = "t,o(b)"; |
252b5132 RH |
8506 | goto ld; |
8507 | case M_LH_AB: | |
df58fc94 | 8508 | ab = 1; |
252b5132 | 8509 | s = "lh"; |
df58fc94 | 8510 | fmt = "t,o(b)"; |
252b5132 RH |
8511 | goto ld; |
8512 | case M_LHU_AB: | |
df58fc94 | 8513 | ab = 1; |
252b5132 | 8514 | s = "lhu"; |
df58fc94 | 8515 | fmt = "t,o(b)"; |
252b5132 RH |
8516 | goto ld; |
8517 | case M_LW_AB: | |
df58fc94 | 8518 | ab = 1; |
252b5132 | 8519 | s = "lw"; |
df58fc94 | 8520 | fmt = "t,o(b)"; |
252b5132 RH |
8521 | goto ld; |
8522 | case M_LWC0_AB: | |
df58fc94 RS |
8523 | ab = 1; |
8524 | gas_assert (!mips_opts.micromips); | |
252b5132 | 8525 | s = "lwc0"; |
df58fc94 | 8526 | fmt = "E,o(b)"; |
bdaaa2e1 | 8527 | /* Itbl support may require additional care here. */ |
252b5132 | 8528 | coproc = 1; |
df58fc94 | 8529 | goto ld_st; |
252b5132 | 8530 | case M_LWC1_AB: |
df58fc94 | 8531 | ab = 1; |
252b5132 | 8532 | s = "lwc1"; |
df58fc94 | 8533 | fmt = "T,o(b)"; |
bdaaa2e1 | 8534 | /* Itbl support may require additional care here. */ |
252b5132 | 8535 | coproc = 1; |
df58fc94 | 8536 | goto ld_st; |
252b5132 | 8537 | case M_LWC2_AB: |
df58fc94 RS |
8538 | ab = 1; |
8539 | case M_LWC2_OB: | |
252b5132 | 8540 | s = "lwc2"; |
df58fc94 | 8541 | fmt = COP12_FMT; |
7f3c4072 | 8542 | offbits = (mips_opts.micromips ? 12 : 16); |
bdaaa2e1 | 8543 | /* Itbl support may require additional care here. */ |
252b5132 | 8544 | coproc = 1; |
df58fc94 | 8545 | goto ld_st; |
252b5132 | 8546 | case M_LWC3_AB: |
df58fc94 RS |
8547 | ab = 1; |
8548 | gas_assert (!mips_opts.micromips); | |
252b5132 | 8549 | s = "lwc3"; |
df58fc94 | 8550 | fmt = "E,o(b)"; |
bdaaa2e1 | 8551 | /* Itbl support may require additional care here. */ |
252b5132 | 8552 | coproc = 1; |
df58fc94 | 8553 | goto ld_st; |
252b5132 | 8554 | case M_LWL_AB: |
df58fc94 RS |
8555 | ab = 1; |
8556 | case M_LWL_OB: | |
252b5132 | 8557 | s = "lwl"; |
df58fc94 | 8558 | fmt = MEM12_FMT; |
7f3c4072 | 8559 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 | 8560 | goto ld_st; |
252b5132 | 8561 | case M_LWR_AB: |
df58fc94 RS |
8562 | ab = 1; |
8563 | case M_LWR_OB: | |
252b5132 | 8564 | s = "lwr"; |
df58fc94 | 8565 | fmt = MEM12_FMT; |
7f3c4072 | 8566 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 | 8567 | goto ld_st; |
252b5132 | 8568 | case M_LDC1_AB: |
df58fc94 | 8569 | ab = 1; |
252b5132 | 8570 | s = "ldc1"; |
df58fc94 | 8571 | fmt = "T,o(b)"; |
bdaaa2e1 | 8572 | /* Itbl support may require additional care here. */ |
252b5132 | 8573 | coproc = 1; |
df58fc94 | 8574 | goto ld_st; |
252b5132 | 8575 | case M_LDC2_AB: |
df58fc94 RS |
8576 | ab = 1; |
8577 | case M_LDC2_OB: | |
252b5132 | 8578 | s = "ldc2"; |
df58fc94 | 8579 | fmt = COP12_FMT; |
7f3c4072 | 8580 | offbits = (mips_opts.micromips ? 12 : 16); |
bdaaa2e1 | 8581 | /* Itbl support may require additional care here. */ |
252b5132 | 8582 | coproc = 1; |
df58fc94 | 8583 | goto ld_st; |
c77c0862 RS |
8584 | case M_LQC2_AB: |
8585 | ab = 1; | |
8586 | s = "lqc2"; | |
8587 | fmt = "E,o(b)"; | |
8588 | /* Itbl support may require additional care here. */ | |
8589 | coproc = 1; | |
8590 | goto ld_st; | |
252b5132 | 8591 | case M_LDC3_AB: |
df58fc94 | 8592 | ab = 1; |
252b5132 | 8593 | s = "ldc3"; |
df58fc94 | 8594 | fmt = "E,o(b)"; |
bdaaa2e1 | 8595 | /* Itbl support may require additional care here. */ |
252b5132 | 8596 | coproc = 1; |
df58fc94 | 8597 | goto ld_st; |
252b5132 | 8598 | case M_LDL_AB: |
df58fc94 RS |
8599 | ab = 1; |
8600 | case M_LDL_OB: | |
252b5132 | 8601 | s = "ldl"; |
df58fc94 | 8602 | fmt = MEM12_FMT; |
7f3c4072 | 8603 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 | 8604 | goto ld_st; |
252b5132 | 8605 | case M_LDR_AB: |
df58fc94 RS |
8606 | ab = 1; |
8607 | case M_LDR_OB: | |
252b5132 | 8608 | s = "ldr"; |
df58fc94 | 8609 | fmt = MEM12_FMT; |
7f3c4072 | 8610 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 | 8611 | goto ld_st; |
252b5132 | 8612 | case M_LL_AB: |
df58fc94 RS |
8613 | ab = 1; |
8614 | case M_LL_OB: | |
252b5132 | 8615 | s = "ll"; |
df58fc94 | 8616 | fmt = MEM12_FMT; |
7f3c4072 | 8617 | offbits = (mips_opts.micromips ? 12 : 16); |
252b5132 RH |
8618 | goto ld; |
8619 | case M_LLD_AB: | |
df58fc94 RS |
8620 | ab = 1; |
8621 | case M_LLD_OB: | |
252b5132 | 8622 | s = "lld"; |
df58fc94 | 8623 | fmt = MEM12_FMT; |
7f3c4072 | 8624 | offbits = (mips_opts.micromips ? 12 : 16); |
252b5132 RH |
8625 | goto ld; |
8626 | case M_LWU_AB: | |
df58fc94 RS |
8627 | ab = 1; |
8628 | case M_LWU_OB: | |
252b5132 | 8629 | s = "lwu"; |
df58fc94 | 8630 | fmt = MEM12_FMT; |
7f3c4072 | 8631 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 RS |
8632 | goto ld; |
8633 | case M_LWP_AB: | |
8634 | ab = 1; | |
8635 | case M_LWP_OB: | |
8636 | gas_assert (mips_opts.micromips); | |
8637 | s = "lwp"; | |
8638 | fmt = "t,~(b)"; | |
7f3c4072 | 8639 | offbits = 12; |
df58fc94 RS |
8640 | lp = 1; |
8641 | goto ld; | |
8642 | case M_LDP_AB: | |
8643 | ab = 1; | |
8644 | case M_LDP_OB: | |
8645 | gas_assert (mips_opts.micromips); | |
8646 | s = "ldp"; | |
8647 | fmt = "t,~(b)"; | |
7f3c4072 | 8648 | offbits = 12; |
df58fc94 RS |
8649 | lp = 1; |
8650 | goto ld; | |
8651 | case M_LWM_AB: | |
8652 | ab = 1; | |
8653 | case M_LWM_OB: | |
8654 | gas_assert (mips_opts.micromips); | |
8655 | s = "lwm"; | |
8656 | fmt = "n,~(b)"; | |
7f3c4072 | 8657 | offbits = 12; |
df58fc94 RS |
8658 | goto ld_st; |
8659 | case M_LDM_AB: | |
8660 | ab = 1; | |
8661 | case M_LDM_OB: | |
8662 | gas_assert (mips_opts.micromips); | |
8663 | s = "ldm"; | |
8664 | fmt = "n,~(b)"; | |
7f3c4072 | 8665 | offbits = 12; |
df58fc94 RS |
8666 | goto ld_st; |
8667 | ||
252b5132 | 8668 | ld: |
f19ccbda MR |
8669 | /* We don't want to use $0 as tempreg. */ |
8670 | if (breg == treg + lp || treg + lp == ZERO) | |
df58fc94 | 8671 | goto ld_st; |
252b5132 | 8672 | else |
df58fc94 RS |
8673 | tempreg = treg + lp; |
8674 | goto ld_noat; | |
8675 | ||
252b5132 | 8676 | case M_SB_AB: |
df58fc94 | 8677 | ab = 1; |
252b5132 | 8678 | s = "sb"; |
df58fc94 RS |
8679 | fmt = "t,o(b)"; |
8680 | goto ld_st; | |
252b5132 | 8681 | case M_SH_AB: |
df58fc94 | 8682 | ab = 1; |
252b5132 | 8683 | s = "sh"; |
df58fc94 RS |
8684 | fmt = "t,o(b)"; |
8685 | goto ld_st; | |
252b5132 | 8686 | case M_SW_AB: |
df58fc94 | 8687 | ab = 1; |
252b5132 | 8688 | s = "sw"; |
df58fc94 RS |
8689 | fmt = "t,o(b)"; |
8690 | goto ld_st; | |
252b5132 | 8691 | case M_SWC0_AB: |
df58fc94 RS |
8692 | ab = 1; |
8693 | gas_assert (!mips_opts.micromips); | |
252b5132 | 8694 | s = "swc0"; |
df58fc94 | 8695 | fmt = "E,o(b)"; |
bdaaa2e1 | 8696 | /* Itbl support may require additional care here. */ |
252b5132 | 8697 | coproc = 1; |
df58fc94 | 8698 | goto ld_st; |
252b5132 | 8699 | case M_SWC1_AB: |
df58fc94 | 8700 | ab = 1; |
252b5132 | 8701 | s = "swc1"; |
df58fc94 | 8702 | fmt = "T,o(b)"; |
bdaaa2e1 | 8703 | /* Itbl support may require additional care here. */ |
252b5132 | 8704 | coproc = 1; |
df58fc94 | 8705 | goto ld_st; |
252b5132 | 8706 | case M_SWC2_AB: |
df58fc94 RS |
8707 | ab = 1; |
8708 | case M_SWC2_OB: | |
252b5132 | 8709 | s = "swc2"; |
df58fc94 | 8710 | fmt = COP12_FMT; |
7f3c4072 | 8711 | offbits = (mips_opts.micromips ? 12 : 16); |
bdaaa2e1 | 8712 | /* Itbl support may require additional care here. */ |
252b5132 | 8713 | coproc = 1; |
df58fc94 | 8714 | goto ld_st; |
252b5132 | 8715 | case M_SWC3_AB: |
df58fc94 RS |
8716 | ab = 1; |
8717 | gas_assert (!mips_opts.micromips); | |
252b5132 | 8718 | s = "swc3"; |
df58fc94 | 8719 | fmt = "E,o(b)"; |
bdaaa2e1 | 8720 | /* Itbl support may require additional care here. */ |
252b5132 | 8721 | coproc = 1; |
df58fc94 | 8722 | goto ld_st; |
252b5132 | 8723 | case M_SWL_AB: |
df58fc94 RS |
8724 | ab = 1; |
8725 | case M_SWL_OB: | |
252b5132 | 8726 | s = "swl"; |
df58fc94 | 8727 | fmt = MEM12_FMT; |
7f3c4072 | 8728 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 | 8729 | goto ld_st; |
252b5132 | 8730 | case M_SWR_AB: |
df58fc94 RS |
8731 | ab = 1; |
8732 | case M_SWR_OB: | |
252b5132 | 8733 | s = "swr"; |
df58fc94 | 8734 | fmt = MEM12_FMT; |
7f3c4072 | 8735 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 | 8736 | goto ld_st; |
252b5132 | 8737 | case M_SC_AB: |
df58fc94 RS |
8738 | ab = 1; |
8739 | case M_SC_OB: | |
252b5132 | 8740 | s = "sc"; |
df58fc94 | 8741 | fmt = MEM12_FMT; |
7f3c4072 | 8742 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 | 8743 | goto ld_st; |
252b5132 | 8744 | case M_SCD_AB: |
df58fc94 RS |
8745 | ab = 1; |
8746 | case M_SCD_OB: | |
252b5132 | 8747 | s = "scd"; |
df58fc94 | 8748 | fmt = MEM12_FMT; |
7f3c4072 | 8749 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 | 8750 | goto ld_st; |
d43b4baf | 8751 | case M_CACHE_AB: |
df58fc94 RS |
8752 | ab = 1; |
8753 | case M_CACHE_OB: | |
d43b4baf | 8754 | s = "cache"; |
df58fc94 | 8755 | fmt = mips_opts.micromips ? "k,~(b)" : "k,o(b)"; |
7f3c4072 CM |
8756 | offbits = (mips_opts.micromips ? 12 : 16); |
8757 | goto ld_st; | |
8758 | case M_CACHEE_AB: | |
8759 | ab = 1; | |
8760 | case M_CACHEE_OB: | |
8761 | s = "cachee"; | |
8762 | fmt = "k,+j(b)"; | |
8763 | offbits = 9; | |
df58fc94 | 8764 | goto ld_st; |
3eebd5eb | 8765 | case M_PREF_AB: |
df58fc94 RS |
8766 | ab = 1; |
8767 | case M_PREF_OB: | |
3eebd5eb | 8768 | s = "pref"; |
df58fc94 | 8769 | fmt = !mips_opts.micromips ? "k,o(b)" : "k,~(b)"; |
7f3c4072 CM |
8770 | offbits = (mips_opts.micromips ? 12 : 16); |
8771 | goto ld_st; | |
8772 | case M_PREFE_AB: | |
8773 | ab = 1; | |
8774 | case M_PREFE_OB: | |
8775 | s = "prefe"; | |
8776 | fmt = "k,+j(b)"; | |
8777 | offbits = 9; | |
df58fc94 | 8778 | goto ld_st; |
252b5132 | 8779 | case M_SDC1_AB: |
df58fc94 | 8780 | ab = 1; |
252b5132 | 8781 | s = "sdc1"; |
df58fc94 | 8782 | fmt = "T,o(b)"; |
252b5132 | 8783 | coproc = 1; |
bdaaa2e1 | 8784 | /* Itbl support may require additional care here. */ |
df58fc94 | 8785 | goto ld_st; |
252b5132 | 8786 | case M_SDC2_AB: |
df58fc94 RS |
8787 | ab = 1; |
8788 | case M_SDC2_OB: | |
252b5132 | 8789 | s = "sdc2"; |
df58fc94 | 8790 | fmt = COP12_FMT; |
7f3c4072 | 8791 | offbits = (mips_opts.micromips ? 12 : 16); |
c77c0862 RS |
8792 | /* Itbl support may require additional care here. */ |
8793 | coproc = 1; | |
8794 | goto ld_st; | |
8795 | case M_SQC2_AB: | |
8796 | ab = 1; | |
8797 | s = "sqc2"; | |
8798 | fmt = "E,o(b)"; | |
bdaaa2e1 | 8799 | /* Itbl support may require additional care here. */ |
252b5132 | 8800 | coproc = 1; |
df58fc94 | 8801 | goto ld_st; |
252b5132 | 8802 | case M_SDC3_AB: |
df58fc94 RS |
8803 | ab = 1; |
8804 | gas_assert (!mips_opts.micromips); | |
252b5132 | 8805 | s = "sdc3"; |
df58fc94 | 8806 | fmt = "E,o(b)"; |
bdaaa2e1 | 8807 | /* Itbl support may require additional care here. */ |
252b5132 | 8808 | coproc = 1; |
df58fc94 | 8809 | goto ld_st; |
252b5132 | 8810 | case M_SDL_AB: |
df58fc94 RS |
8811 | ab = 1; |
8812 | case M_SDL_OB: | |
252b5132 | 8813 | s = "sdl"; |
df58fc94 | 8814 | fmt = MEM12_FMT; |
7f3c4072 | 8815 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 | 8816 | goto ld_st; |
252b5132 | 8817 | case M_SDR_AB: |
df58fc94 RS |
8818 | ab = 1; |
8819 | case M_SDR_OB: | |
252b5132 | 8820 | s = "sdr"; |
df58fc94 | 8821 | fmt = MEM12_FMT; |
7f3c4072 | 8822 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 RS |
8823 | goto ld_st; |
8824 | case M_SWP_AB: | |
8825 | ab = 1; | |
8826 | case M_SWP_OB: | |
8827 | gas_assert (mips_opts.micromips); | |
8828 | s = "swp"; | |
8829 | fmt = "t,~(b)"; | |
7f3c4072 | 8830 | offbits = 12; |
df58fc94 RS |
8831 | goto ld_st; |
8832 | case M_SDP_AB: | |
8833 | ab = 1; | |
8834 | case M_SDP_OB: | |
8835 | gas_assert (mips_opts.micromips); | |
8836 | s = "sdp"; | |
8837 | fmt = "t,~(b)"; | |
7f3c4072 | 8838 | offbits = 12; |
df58fc94 RS |
8839 | goto ld_st; |
8840 | case M_SWM_AB: | |
8841 | ab = 1; | |
8842 | case M_SWM_OB: | |
8843 | gas_assert (mips_opts.micromips); | |
8844 | s = "swm"; | |
8845 | fmt = "n,~(b)"; | |
7f3c4072 | 8846 | offbits = 12; |
df58fc94 RS |
8847 | goto ld_st; |
8848 | case M_SDM_AB: | |
8849 | ab = 1; | |
8850 | case M_SDM_OB: | |
8851 | gas_assert (mips_opts.micromips); | |
8852 | s = "sdm"; | |
8853 | fmt = "n,~(b)"; | |
7f3c4072 | 8854 | offbits = 12; |
df58fc94 RS |
8855 | |
8856 | ld_st: | |
8fc2e39e TS |
8857 | tempreg = AT; |
8858 | used_at = 1; | |
df58fc94 | 8859 | ld_noat: |
252b5132 RH |
8860 | if (offset_expr.X_op != O_constant |
8861 | && offset_expr.X_op != O_symbol) | |
8862 | { | |
f71d0d44 | 8863 | as_bad (_("Expression too complex")); |
252b5132 RH |
8864 | offset_expr.X_op = O_constant; |
8865 | } | |
8866 | ||
2051e8c4 MR |
8867 | if (HAVE_32BIT_ADDRESSES |
8868 | && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) | |
55e08f71 NC |
8869 | { |
8870 | char value [32]; | |
8871 | ||
8872 | sprintf_vma (value, offset_expr.X_add_number); | |
20e1fcfd | 8873 | as_bad (_("Number (0x%s) larger than 32 bits"), value); |
55e08f71 | 8874 | } |
2051e8c4 | 8875 | |
252b5132 RH |
8876 | /* A constant expression in PIC code can be handled just as it |
8877 | is in non PIC code. */ | |
aed1a261 RS |
8878 | if (offset_expr.X_op == O_constant) |
8879 | { | |
df58fc94 RS |
8880 | int hipart = 0; |
8881 | ||
842f8b2a | 8882 | expr1.X_add_number = offset_expr.X_add_number; |
2051e8c4 | 8883 | normalize_address_expr (&expr1); |
7f3c4072 CM |
8884 | if ((offbits == 0 || offbits == 16) |
8885 | && !IS_SEXT_16BIT_NUM (expr1.X_add_number)) | |
842f8b2a MR |
8886 | { |
8887 | expr1.X_add_number = ((expr1.X_add_number + 0x8000) | |
8888 | & ~(bfd_vma) 0xffff); | |
df58fc94 RS |
8889 | hipart = 1; |
8890 | } | |
7f3c4072 | 8891 | else if (offbits == 12 && !IS_SEXT_12BIT_NUM (expr1.X_add_number)) |
df58fc94 RS |
8892 | { |
8893 | expr1.X_add_number = ((expr1.X_add_number + 0x800) | |
8894 | & ~(bfd_vma) 0xfff); | |
8895 | hipart = 1; | |
8896 | } | |
7f3c4072 CM |
8897 | else if (offbits == 9 && !IS_SEXT_9BIT_NUM (expr1.X_add_number)) |
8898 | { | |
8899 | expr1.X_add_number = ((expr1.X_add_number + 0x100) | |
8900 | & ~(bfd_vma) 0x1ff); | |
8901 | hipart = 1; | |
8902 | } | |
df58fc94 RS |
8903 | if (hipart) |
8904 | { | |
842f8b2a MR |
8905 | load_register (tempreg, &expr1, HAVE_64BIT_ADDRESSES); |
8906 | if (breg != 0) | |
8907 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
8908 | tempreg, tempreg, breg); | |
8909 | breg = tempreg; | |
8910 | } | |
7f3c4072 | 8911 | if (offbits == 0) |
dd6a37e7 AP |
8912 | { |
8913 | if (offset_expr.X_add_number == 0) | |
8914 | tempreg = breg; | |
8915 | else | |
8916 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, | |
8917 | "t,r,j", tempreg, breg, BFD_RELOC_LO16); | |
8918 | macro_build (NULL, s, fmt, treg, tempreg); | |
8919 | } | |
7f3c4072 | 8920 | else if (offbits == 16) |
df58fc94 RS |
8921 | macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, breg); |
8922 | else | |
8923 | macro_build (NULL, s, fmt, | |
8924 | treg, (unsigned long) offset_expr.X_add_number, breg); | |
8925 | } | |
7f3c4072 | 8926 | else if (offbits != 16) |
df58fc94 | 8927 | { |
7f3c4072 CM |
8928 | /* The offset field is too narrow to be used for a low-part |
8929 | relocation, so load the whole address into the auxillary | |
8930 | register. In the case of "A(b)" addresses, we first load | |
8931 | absolute address "A" into the register and then add base | |
8932 | register "b". In the case of "o(b)" addresses, we simply | |
8933 | need to add 16-bit offset "o" to base register "b", and | |
df58fc94 RS |
8934 | offset_reloc already contains the relocations associated |
8935 | with "o". */ | |
8936 | if (ab) | |
8937 | { | |
8938 | load_address (tempreg, &offset_expr, &used_at); | |
8939 | if (breg != 0) | |
8940 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
8941 | tempreg, tempreg, breg); | |
8942 | } | |
8943 | else | |
8944 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
8945 | tempreg, breg, -1, | |
8946 | offset_reloc[0], offset_reloc[1], offset_reloc[2]); | |
8947 | expr1.X_add_number = 0; | |
7f3c4072 | 8948 | if (offbits == 0) |
dd6a37e7 AP |
8949 | macro_build (NULL, s, fmt, treg, tempreg); |
8950 | else | |
8951 | macro_build (NULL, s, fmt, | |
8952 | treg, (unsigned long) expr1.X_add_number, tempreg); | |
aed1a261 RS |
8953 | } |
8954 | else if (mips_pic == NO_PIC) | |
252b5132 RH |
8955 | { |
8956 | /* If this is a reference to a GP relative symbol, and there | |
8957 | is no base register, we want | |
cdf6fd85 | 8958 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
252b5132 RH |
8959 | Otherwise, if there is no base register, we want |
8960 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
8961 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
8962 | If we have a constant, we need two instructions anyhow, | |
8963 | so we always use the latter form. | |
8964 | ||
8965 | If we have a base register, and this is a reference to a | |
8966 | GP relative symbol, we want | |
8967 | addu $tempreg,$breg,$gp | |
cdf6fd85 | 8968 | <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16) |
252b5132 RH |
8969 | Otherwise we want |
8970 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
8971 | addu $tempreg,$tempreg,$breg | |
8972 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
d6bc6245 | 8973 | With a constant we always use the latter case. |
76b3015f | 8974 | |
d6bc6245 TS |
8975 | With 64bit address space and no base register and $at usable, |
8976 | we want | |
8977 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
8978 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
8979 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
8980 | dsll32 $tempreg,0 | |
8981 | daddu $tempreg,$at | |
8982 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
8983 | If we have a base register, we want | |
8984 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
8985 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
8986 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
8987 | daddu $at,$breg | |
8988 | dsll32 $tempreg,0 | |
8989 | daddu $tempreg,$at | |
8990 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
8991 | ||
8992 | Without $at we can't generate the optimal path for superscalar | |
8993 | processors here since this would require two temporary registers. | |
8994 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
8995 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
8996 | dsll $tempreg,16 | |
8997 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
8998 | dsll $tempreg,16 | |
8999 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
9000 | If we have a base register, we want | |
9001 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
9002 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
9003 | dsll $tempreg,16 | |
9004 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
9005 | dsll $tempreg,16 | |
9006 | daddu $tempreg,$tempreg,$breg | |
9007 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
6373ee54 | 9008 | |
6caf9ef4 | 9009 | For GP relative symbols in 64bit address space we can use |
aed1a261 RS |
9010 | the same sequence as in 32bit address space. */ |
9011 | if (HAVE_64BIT_SYMBOLS) | |
d6bc6245 | 9012 | { |
aed1a261 | 9013 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 TS |
9014 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
9015 | { | |
9016 | relax_start (offset_expr.X_add_symbol); | |
9017 | if (breg == 0) | |
9018 | { | |
9019 | macro_build (&offset_expr, s, fmt, treg, | |
9020 | BFD_RELOC_GPREL16, mips_gp_register); | |
9021 | } | |
9022 | else | |
9023 | { | |
9024 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
9025 | tempreg, breg, mips_gp_register); | |
9026 | macro_build (&offset_expr, s, fmt, treg, | |
9027 | BFD_RELOC_GPREL16, tempreg); | |
9028 | } | |
9029 | relax_switch (); | |
9030 | } | |
d6bc6245 | 9031 | |
741fe287 | 9032 | if (used_at == 0 && mips_opts.at) |
d6bc6245 | 9033 | { |
df58fc94 | 9034 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, |
67c0d1eb | 9035 | BFD_RELOC_MIPS_HIGHEST); |
df58fc94 | 9036 | macro_build (&offset_expr, "lui", LUI_FMT, AT, |
67c0d1eb RS |
9037 | BFD_RELOC_HI16_S); |
9038 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
9039 | tempreg, BFD_RELOC_MIPS_HIGHER); | |
d6bc6245 | 9040 | if (breg != 0) |
67c0d1eb | 9041 | macro_build (NULL, "daddu", "d,v,t", AT, AT, breg); |
df58fc94 | 9042 | macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0); |
67c0d1eb RS |
9043 | macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT); |
9044 | macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, | |
9045 | tempreg); | |
d6bc6245 TS |
9046 | used_at = 1; |
9047 | } | |
9048 | else | |
9049 | { | |
df58fc94 | 9050 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, |
67c0d1eb RS |
9051 | BFD_RELOC_MIPS_HIGHEST); |
9052 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
9053 | tempreg, BFD_RELOC_MIPS_HIGHER); | |
df58fc94 | 9054 | macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16); |
67c0d1eb RS |
9055 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, |
9056 | tempreg, BFD_RELOC_HI16_S); | |
df58fc94 | 9057 | macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16); |
d6bc6245 | 9058 | if (breg != 0) |
67c0d1eb | 9059 | macro_build (NULL, "daddu", "d,v,t", |
17a2f251 | 9060 | tempreg, tempreg, breg); |
67c0d1eb | 9061 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 9062 | BFD_RELOC_LO16, tempreg); |
d6bc6245 | 9063 | } |
6caf9ef4 TS |
9064 | |
9065 | if (mips_relax.sequence) | |
9066 | relax_end (); | |
8fc2e39e | 9067 | break; |
d6bc6245 | 9068 | } |
256ab948 | 9069 | |
252b5132 RH |
9070 | if (breg == 0) |
9071 | { | |
67c0d1eb | 9072 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 9073 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 9074 | { |
4d7206a2 | 9075 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
9076 | macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_GPREL16, |
9077 | mips_gp_register); | |
4d7206a2 | 9078 | relax_switch (); |
252b5132 | 9079 | } |
67c0d1eb RS |
9080 | macro_build_lui (&offset_expr, tempreg); |
9081 | macro_build (&offset_expr, s, fmt, treg, | |
17a2f251 | 9082 | BFD_RELOC_LO16, tempreg); |
4d7206a2 RS |
9083 | if (mips_relax.sequence) |
9084 | relax_end (); | |
252b5132 RH |
9085 | } |
9086 | else | |
9087 | { | |
67c0d1eb | 9088 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 9089 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 9090 | { |
4d7206a2 | 9091 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 9092 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 9093 | tempreg, breg, mips_gp_register); |
67c0d1eb | 9094 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 9095 | BFD_RELOC_GPREL16, tempreg); |
4d7206a2 | 9096 | relax_switch (); |
252b5132 | 9097 | } |
67c0d1eb RS |
9098 | macro_build_lui (&offset_expr, tempreg); |
9099 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 9100 | tempreg, tempreg, breg); |
67c0d1eb | 9101 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 9102 | BFD_RELOC_LO16, tempreg); |
4d7206a2 RS |
9103 | if (mips_relax.sequence) |
9104 | relax_end (); | |
252b5132 RH |
9105 | } |
9106 | } | |
0a44bf69 | 9107 | else if (!mips_big_got) |
252b5132 | 9108 | { |
ed6fb7bd | 9109 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
f9419b05 | 9110 | |
252b5132 RH |
9111 | /* If this is a reference to an external symbol, we want |
9112 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
9113 | nop | |
9114 | <op> $treg,0($tempreg) | |
9115 | Otherwise we want | |
9116 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
9117 | nop | |
9118 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
9119 | <op> $treg,0($tempreg) | |
f5040a92 AO |
9120 | |
9121 | For NewABI, we want | |
9122 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
9123 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) | |
9124 | ||
252b5132 RH |
9125 | If there is a base register, we add it to $tempreg before |
9126 | the <op>. If there is a constant, we stick it in the | |
9127 | <op> instruction. We don't handle constants larger than | |
9128 | 16 bits, because we have no way to load the upper 16 bits | |
9129 | (actually, we could handle them for the subset of cases | |
9130 | in which we are not using $at). */ | |
9c2799c2 | 9131 | gas_assert (offset_expr.X_op == O_symbol); |
f5040a92 AO |
9132 | if (HAVE_NEWABI) |
9133 | { | |
67c0d1eb RS |
9134 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
9135 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
f5040a92 | 9136 | if (breg != 0) |
67c0d1eb | 9137 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 9138 | tempreg, tempreg, breg); |
67c0d1eb | 9139 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 9140 | BFD_RELOC_MIPS_GOT_OFST, tempreg); |
f5040a92 AO |
9141 | break; |
9142 | } | |
252b5132 RH |
9143 | expr1.X_add_number = offset_expr.X_add_number; |
9144 | offset_expr.X_add_number = 0; | |
9145 | if (expr1.X_add_number < -0x8000 | |
9146 | || expr1.X_add_number >= 0x8000) | |
9147 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb RS |
9148 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
9149 | lw_reloc_type, mips_gp_register); | |
269137b2 | 9150 | load_delay_nop (); |
4d7206a2 RS |
9151 | relax_start (offset_expr.X_add_symbol); |
9152 | relax_switch (); | |
67c0d1eb RS |
9153 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, |
9154 | tempreg, BFD_RELOC_LO16); | |
4d7206a2 | 9155 | relax_end (); |
252b5132 | 9156 | if (breg != 0) |
67c0d1eb | 9157 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 9158 | tempreg, tempreg, breg); |
67c0d1eb | 9159 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
252b5132 | 9160 | } |
0a44bf69 | 9161 | else if (mips_big_got && !HAVE_NEWABI) |
252b5132 | 9162 | { |
67c0d1eb | 9163 | int gpdelay; |
252b5132 RH |
9164 | |
9165 | /* If this is a reference to an external symbol, we want | |
9166 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
9167 | addu $tempreg,$tempreg,$gp | |
9168 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
9169 | <op> $treg,0($tempreg) | |
9170 | Otherwise we want | |
9171 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
9172 | nop | |
9173 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
9174 | <op> $treg,0($tempreg) | |
9175 | If there is a base register, we add it to $tempreg before | |
9176 | the <op>. If there is a constant, we stick it in the | |
9177 | <op> instruction. We don't handle constants larger than | |
9178 | 16 bits, because we have no way to load the upper 16 bits | |
9179 | (actually, we could handle them for the subset of cases | |
f5040a92 | 9180 | in which we are not using $at). */ |
9c2799c2 | 9181 | gas_assert (offset_expr.X_op == O_symbol); |
252b5132 RH |
9182 | expr1.X_add_number = offset_expr.X_add_number; |
9183 | offset_expr.X_add_number = 0; | |
9184 | if (expr1.X_add_number < -0x8000 | |
9185 | || expr1.X_add_number >= 0x8000) | |
9186 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 9187 | gpdelay = reg_needs_delay (mips_gp_register); |
4d7206a2 | 9188 | relax_start (offset_expr.X_add_symbol); |
df58fc94 | 9189 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, |
17a2f251 | 9190 | BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
9191 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, |
9192 | mips_gp_register); | |
9193 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
9194 | BFD_RELOC_MIPS_GOT_LO16, tempreg); | |
4d7206a2 | 9195 | relax_switch (); |
67c0d1eb RS |
9196 | if (gpdelay) |
9197 | macro_build (NULL, "nop", ""); | |
9198 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
9199 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 9200 | load_delay_nop (); |
67c0d1eb RS |
9201 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, |
9202 | tempreg, BFD_RELOC_LO16); | |
4d7206a2 RS |
9203 | relax_end (); |
9204 | ||
252b5132 | 9205 | if (breg != 0) |
67c0d1eb | 9206 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 9207 | tempreg, tempreg, breg); |
67c0d1eb | 9208 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
252b5132 | 9209 | } |
0a44bf69 | 9210 | else if (mips_big_got && HAVE_NEWABI) |
f5040a92 | 9211 | { |
f5040a92 AO |
9212 | /* If this is a reference to an external symbol, we want |
9213 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
9214 | add $tempreg,$tempreg,$gp | |
9215 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
9216 | <op> $treg,<ofst>($tempreg) | |
9217 | Otherwise, for local symbols, we want: | |
9218 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
9219 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */ | |
9c2799c2 | 9220 | gas_assert (offset_expr.X_op == O_symbol); |
4d7206a2 | 9221 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
9222 | offset_expr.X_add_number = 0; |
9223 | if (expr1.X_add_number < -0x8000 | |
9224 | || expr1.X_add_number >= 0x8000) | |
9225 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4d7206a2 | 9226 | relax_start (offset_expr.X_add_symbol); |
df58fc94 | 9227 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, |
17a2f251 | 9228 | BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
9229 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, |
9230 | mips_gp_register); | |
9231 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
9232 | BFD_RELOC_MIPS_GOT_LO16, tempreg); | |
f5040a92 | 9233 | if (breg != 0) |
67c0d1eb | 9234 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 9235 | tempreg, tempreg, breg); |
67c0d1eb | 9236 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
684022ea | 9237 | |
4d7206a2 | 9238 | relax_switch (); |
f5040a92 | 9239 | offset_expr.X_add_number = expr1.X_add_number; |
67c0d1eb RS |
9240 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
9241 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
f5040a92 | 9242 | if (breg != 0) |
67c0d1eb | 9243 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 9244 | tempreg, tempreg, breg); |
67c0d1eb | 9245 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 9246 | BFD_RELOC_MIPS_GOT_OFST, tempreg); |
4d7206a2 | 9247 | relax_end (); |
f5040a92 | 9248 | } |
252b5132 RH |
9249 | else |
9250 | abort (); | |
9251 | ||
252b5132 RH |
9252 | break; |
9253 | ||
9254 | case M_LI: | |
9255 | case M_LI_S: | |
67c0d1eb | 9256 | load_register (treg, &imm_expr, 0); |
8fc2e39e | 9257 | break; |
252b5132 RH |
9258 | |
9259 | case M_DLI: | |
67c0d1eb | 9260 | load_register (treg, &imm_expr, 1); |
8fc2e39e | 9261 | break; |
252b5132 RH |
9262 | |
9263 | case M_LI_SS: | |
9264 | if (imm_expr.X_op == O_constant) | |
9265 | { | |
8fc2e39e | 9266 | used_at = 1; |
67c0d1eb RS |
9267 | load_register (AT, &imm_expr, 0); |
9268 | macro_build (NULL, "mtc1", "t,G", AT, treg); | |
252b5132 RH |
9269 | break; |
9270 | } | |
9271 | else | |
9272 | { | |
9c2799c2 | 9273 | gas_assert (offset_expr.X_op == O_symbol |
90ecf173 MR |
9274 | && strcmp (segment_name (S_GET_SEGMENT |
9275 | (offset_expr.X_add_symbol)), | |
9276 | ".lit4") == 0 | |
9277 | && offset_expr.X_add_number == 0); | |
67c0d1eb | 9278 | macro_build (&offset_expr, "lwc1", "T,o(b)", treg, |
17a2f251 | 9279 | BFD_RELOC_MIPS_LITERAL, mips_gp_register); |
8fc2e39e | 9280 | break; |
252b5132 RH |
9281 | } |
9282 | ||
9283 | case M_LI_D: | |
ca4e0257 RS |
9284 | /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits |
9285 | wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high | |
9286 | order 32 bits of the value and the low order 32 bits are either | |
9287 | zero or in OFFSET_EXPR. */ | |
252b5132 RH |
9288 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) |
9289 | { | |
ca4e0257 | 9290 | if (HAVE_64BIT_GPRS) |
67c0d1eb | 9291 | load_register (treg, &imm_expr, 1); |
252b5132 RH |
9292 | else |
9293 | { | |
9294 | int hreg, lreg; | |
9295 | ||
9296 | if (target_big_endian) | |
9297 | { | |
9298 | hreg = treg; | |
9299 | lreg = treg + 1; | |
9300 | } | |
9301 | else | |
9302 | { | |
9303 | hreg = treg + 1; | |
9304 | lreg = treg; | |
9305 | } | |
9306 | ||
9307 | if (hreg <= 31) | |
67c0d1eb | 9308 | load_register (hreg, &imm_expr, 0); |
252b5132 RH |
9309 | if (lreg <= 31) |
9310 | { | |
9311 | if (offset_expr.X_op == O_absent) | |
67c0d1eb | 9312 | move_register (lreg, 0); |
252b5132 RH |
9313 | else |
9314 | { | |
9c2799c2 | 9315 | gas_assert (offset_expr.X_op == O_constant); |
67c0d1eb | 9316 | load_register (lreg, &offset_expr, 0); |
252b5132 RH |
9317 | } |
9318 | } | |
9319 | } | |
8fc2e39e | 9320 | break; |
252b5132 RH |
9321 | } |
9322 | ||
9323 | /* We know that sym is in the .rdata section. First we get the | |
9324 | upper 16 bits of the address. */ | |
9325 | if (mips_pic == NO_PIC) | |
9326 | { | |
67c0d1eb | 9327 | macro_build_lui (&offset_expr, AT); |
8fc2e39e | 9328 | used_at = 1; |
252b5132 | 9329 | } |
0a44bf69 | 9330 | else |
252b5132 | 9331 | { |
67c0d1eb RS |
9332 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, |
9333 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
8fc2e39e | 9334 | used_at = 1; |
252b5132 | 9335 | } |
bdaaa2e1 | 9336 | |
252b5132 | 9337 | /* Now we load the register(s). */ |
ca4e0257 | 9338 | if (HAVE_64BIT_GPRS) |
8fc2e39e TS |
9339 | { |
9340 | used_at = 1; | |
9341 | macro_build (&offset_expr, "ld", "t,o(b)", treg, BFD_RELOC_LO16, AT); | |
9342 | } | |
252b5132 RH |
9343 | else |
9344 | { | |
8fc2e39e | 9345 | used_at = 1; |
67c0d1eb | 9346 | macro_build (&offset_expr, "lw", "t,o(b)", treg, BFD_RELOC_LO16, AT); |
f9419b05 | 9347 | if (treg != RA) |
252b5132 RH |
9348 | { |
9349 | /* FIXME: How in the world do we deal with the possible | |
9350 | overflow here? */ | |
9351 | offset_expr.X_add_number += 4; | |
67c0d1eb | 9352 | macro_build (&offset_expr, "lw", "t,o(b)", |
17a2f251 | 9353 | treg + 1, BFD_RELOC_LO16, AT); |
252b5132 RH |
9354 | } |
9355 | } | |
252b5132 RH |
9356 | break; |
9357 | ||
9358 | case M_LI_DD: | |
ca4e0257 RS |
9359 | /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits |
9360 | wide, IMM_EXPR is the entire value and the GPRs are known to be 64 | |
9361 | bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of | |
9362 | the value and the low order 32 bits are either zero or in | |
9363 | OFFSET_EXPR. */ | |
252b5132 RH |
9364 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) |
9365 | { | |
8fc2e39e | 9366 | used_at = 1; |
67c0d1eb | 9367 | load_register (AT, &imm_expr, HAVE_64BIT_FPRS); |
ca4e0257 RS |
9368 | if (HAVE_64BIT_FPRS) |
9369 | { | |
9c2799c2 | 9370 | gas_assert (HAVE_64BIT_GPRS); |
67c0d1eb | 9371 | macro_build (NULL, "dmtc1", "t,S", AT, treg); |
ca4e0257 | 9372 | } |
252b5132 RH |
9373 | else |
9374 | { | |
67c0d1eb | 9375 | macro_build (NULL, "mtc1", "t,G", AT, treg + 1); |
252b5132 | 9376 | if (offset_expr.X_op == O_absent) |
67c0d1eb | 9377 | macro_build (NULL, "mtc1", "t,G", 0, treg); |
252b5132 RH |
9378 | else |
9379 | { | |
9c2799c2 | 9380 | gas_assert (offset_expr.X_op == O_constant); |
67c0d1eb RS |
9381 | load_register (AT, &offset_expr, 0); |
9382 | macro_build (NULL, "mtc1", "t,G", AT, treg); | |
252b5132 RH |
9383 | } |
9384 | } | |
9385 | break; | |
9386 | } | |
9387 | ||
9c2799c2 | 9388 | gas_assert (offset_expr.X_op == O_symbol |
90ecf173 | 9389 | && offset_expr.X_add_number == 0); |
252b5132 RH |
9390 | s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol)); |
9391 | if (strcmp (s, ".lit8") == 0) | |
9392 | { | |
0aa27725 | 9393 | if (CPU_HAS_LDC1_SDC1 (mips_opts.arch) || mips_opts.micromips) |
252b5132 | 9394 | { |
67c0d1eb | 9395 | macro_build (&offset_expr, "ldc1", "T,o(b)", treg, |
17a2f251 | 9396 | BFD_RELOC_MIPS_LITERAL, mips_gp_register); |
8fc2e39e | 9397 | break; |
252b5132 | 9398 | } |
c9914766 | 9399 | breg = mips_gp_register; |
252b5132 RH |
9400 | r = BFD_RELOC_MIPS_LITERAL; |
9401 | goto dob; | |
9402 | } | |
9403 | else | |
9404 | { | |
9c2799c2 | 9405 | gas_assert (strcmp (s, RDATA_SECTION_NAME) == 0); |
8fc2e39e | 9406 | used_at = 1; |
0a44bf69 | 9407 | if (mips_pic != NO_PIC) |
67c0d1eb RS |
9408 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, |
9409 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
252b5132 RH |
9410 | else |
9411 | { | |
9412 | /* FIXME: This won't work for a 64 bit address. */ | |
67c0d1eb | 9413 | macro_build_lui (&offset_expr, AT); |
252b5132 | 9414 | } |
bdaaa2e1 | 9415 | |
0aa27725 | 9416 | if (CPU_HAS_LDC1_SDC1 (mips_opts.arch) || mips_opts.micromips) |
252b5132 | 9417 | { |
67c0d1eb RS |
9418 | macro_build (&offset_expr, "ldc1", "T,o(b)", |
9419 | treg, BFD_RELOC_LO16, AT); | |
252b5132 RH |
9420 | break; |
9421 | } | |
9422 | breg = AT; | |
9423 | r = BFD_RELOC_LO16; | |
9424 | goto dob; | |
9425 | } | |
9426 | ||
9427 | case M_L_DOB: | |
252b5132 RH |
9428 | /* Even on a big endian machine $fn comes before $fn+1. We have |
9429 | to adjust when loading from memory. */ | |
9430 | r = BFD_RELOC_LO16; | |
9431 | dob: | |
df58fc94 | 9432 | gas_assert (!mips_opts.micromips); |
0aa27725 | 9433 | gas_assert (!CPU_HAS_LDC1_SDC1 (mips_opts.arch)); |
67c0d1eb | 9434 | macro_build (&offset_expr, "lwc1", "T,o(b)", |
17a2f251 | 9435 | target_big_endian ? treg + 1 : treg, r, breg); |
252b5132 RH |
9436 | /* FIXME: A possible overflow which I don't know how to deal |
9437 | with. */ | |
9438 | offset_expr.X_add_number += 4; | |
67c0d1eb | 9439 | macro_build (&offset_expr, "lwc1", "T,o(b)", |
17a2f251 | 9440 | target_big_endian ? treg : treg + 1, r, breg); |
252b5132 RH |
9441 | break; |
9442 | ||
c4a68bea | 9443 | case M_S_DOB: |
df58fc94 | 9444 | gas_assert (!mips_opts.micromips); |
0aa27725 | 9445 | gas_assert (!CPU_HAS_LDC1_SDC1 (mips_opts.arch)); |
c4a68bea MR |
9446 | /* Even on a big endian machine $fn comes before $fn+1. We have |
9447 | to adjust when storing to memory. */ | |
9448 | macro_build (&offset_expr, "swc1", "T,o(b)", | |
9449 | target_big_endian ? treg + 1 : treg, BFD_RELOC_LO16, breg); | |
9450 | offset_expr.X_add_number += 4; | |
9451 | macro_build (&offset_expr, "swc1", "T,o(b)", | |
9452 | target_big_endian ? treg : treg + 1, BFD_RELOC_LO16, breg); | |
9453 | break; | |
9454 | ||
252b5132 | 9455 | case M_L_DAB: |
df58fc94 | 9456 | gas_assert (!mips_opts.micromips); |
252b5132 RH |
9457 | /* |
9458 | * The MIPS assembler seems to check for X_add_number not | |
9459 | * being double aligned and generating: | |
9460 | * lui at,%hi(foo+1) | |
9461 | * addu at,at,v1 | |
9462 | * addiu at,at,%lo(foo+1) | |
9463 | * lwc1 f2,0(at) | |
9464 | * lwc1 f3,4(at) | |
9465 | * But, the resulting address is the same after relocation so why | |
9466 | * generate the extra instruction? | |
9467 | */ | |
bdaaa2e1 | 9468 | /* Itbl support may require additional care here. */ |
252b5132 | 9469 | coproc = 1; |
df58fc94 | 9470 | fmt = "T,o(b)"; |
0aa27725 | 9471 | if (CPU_HAS_LDC1_SDC1 (mips_opts.arch)) |
252b5132 RH |
9472 | { |
9473 | s = "ldc1"; | |
df58fc94 | 9474 | goto ld_st; |
252b5132 | 9475 | } |
252b5132 | 9476 | s = "lwc1"; |
252b5132 RH |
9477 | goto ldd_std; |
9478 | ||
9479 | case M_S_DAB: | |
df58fc94 RS |
9480 | gas_assert (!mips_opts.micromips); |
9481 | /* Itbl support may require additional care here. */ | |
9482 | coproc = 1; | |
9483 | fmt = "T,o(b)"; | |
0aa27725 | 9484 | if (CPU_HAS_LDC1_SDC1 (mips_opts.arch)) |
252b5132 RH |
9485 | { |
9486 | s = "sdc1"; | |
df58fc94 | 9487 | goto ld_st; |
252b5132 | 9488 | } |
252b5132 | 9489 | s = "swc1"; |
252b5132 RH |
9490 | goto ldd_std; |
9491 | ||
e407c74b NC |
9492 | case M_LQ_AB: |
9493 | fmt = "t,o(b)"; | |
9494 | s = "lq"; | |
9495 | goto ld; | |
9496 | ||
9497 | case M_SQ_AB: | |
9498 | fmt = "t,o(b)"; | |
9499 | s = "sq"; | |
9500 | goto ld_st; | |
9501 | ||
252b5132 | 9502 | case M_LD_AB: |
df58fc94 | 9503 | fmt = "t,o(b)"; |
ca4e0257 | 9504 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
9505 | { |
9506 | s = "ld"; | |
9507 | goto ld; | |
9508 | } | |
252b5132 | 9509 | s = "lw"; |
252b5132 RH |
9510 | goto ldd_std; |
9511 | ||
9512 | case M_SD_AB: | |
df58fc94 | 9513 | fmt = "t,o(b)"; |
ca4e0257 | 9514 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
9515 | { |
9516 | s = "sd"; | |
df58fc94 | 9517 | goto ld_st; |
252b5132 | 9518 | } |
252b5132 | 9519 | s = "sw"; |
252b5132 RH |
9520 | |
9521 | ldd_std: | |
9522 | if (offset_expr.X_op != O_symbol | |
9523 | && offset_expr.X_op != O_constant) | |
9524 | { | |
f71d0d44 | 9525 | as_bad (_("Expression too complex")); |
252b5132 RH |
9526 | offset_expr.X_op = O_constant; |
9527 | } | |
9528 | ||
2051e8c4 MR |
9529 | if (HAVE_32BIT_ADDRESSES |
9530 | && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) | |
55e08f71 NC |
9531 | { |
9532 | char value [32]; | |
9533 | ||
9534 | sprintf_vma (value, offset_expr.X_add_number); | |
20e1fcfd | 9535 | as_bad (_("Number (0x%s) larger than 32 bits"), value); |
55e08f71 | 9536 | } |
2051e8c4 | 9537 | |
252b5132 RH |
9538 | /* Even on a big endian machine $fn comes before $fn+1. We have |
9539 | to adjust when loading from memory. We set coproc if we must | |
9540 | load $fn+1 first. */ | |
bdaaa2e1 | 9541 | /* Itbl support may require additional care here. */ |
90ecf173 | 9542 | if (!target_big_endian) |
252b5132 RH |
9543 | coproc = 0; |
9544 | ||
90ecf173 | 9545 | if (mips_pic == NO_PIC || offset_expr.X_op == O_constant) |
252b5132 RH |
9546 | { |
9547 | /* If this is a reference to a GP relative symbol, we want | |
cdf6fd85 TS |
9548 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
9549 | <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16) | |
252b5132 RH |
9550 | If we have a base register, we use this |
9551 | addu $at,$breg,$gp | |
cdf6fd85 TS |
9552 | <op> $treg,<sym>($at) (BFD_RELOC_GPREL16) |
9553 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16) | |
252b5132 RH |
9554 | If this is not a GP relative symbol, we want |
9555 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
9556 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
9557 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
9558 | If there is a base register, we add it to $at after the | |
9559 | lui instruction. If there is a constant, we always use | |
9560 | the last case. */ | |
39a59cf8 MR |
9561 | if (offset_expr.X_op == O_symbol |
9562 | && (valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET | |
6caf9ef4 | 9563 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 9564 | { |
4d7206a2 | 9565 | relax_start (offset_expr.X_add_symbol); |
252b5132 RH |
9566 | if (breg == 0) |
9567 | { | |
c9914766 | 9568 | tempreg = mips_gp_register; |
252b5132 RH |
9569 | } |
9570 | else | |
9571 | { | |
67c0d1eb | 9572 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 9573 | AT, breg, mips_gp_register); |
252b5132 | 9574 | tempreg = AT; |
252b5132 RH |
9575 | used_at = 1; |
9576 | } | |
9577 | ||
beae10d5 | 9578 | /* Itbl support may require additional care here. */ |
67c0d1eb | 9579 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 9580 | BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
9581 | offset_expr.X_add_number += 4; |
9582 | ||
9583 | /* Set mips_optimize to 2 to avoid inserting an | |
9584 | undesired nop. */ | |
9585 | hold_mips_optimize = mips_optimize; | |
9586 | mips_optimize = 2; | |
beae10d5 | 9587 | /* Itbl support may require additional care here. */ |
67c0d1eb | 9588 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 9589 | BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
9590 | mips_optimize = hold_mips_optimize; |
9591 | ||
4d7206a2 | 9592 | relax_switch (); |
252b5132 | 9593 | |
0970e49e | 9594 | offset_expr.X_add_number -= 4; |
252b5132 | 9595 | } |
8fc2e39e | 9596 | used_at = 1; |
67c0d1eb | 9597 | macro_build_lui (&offset_expr, AT); |
252b5132 | 9598 | if (breg != 0) |
67c0d1eb | 9599 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 9600 | /* Itbl support may require additional care here. */ |
67c0d1eb | 9601 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 9602 | BFD_RELOC_LO16, AT); |
252b5132 RH |
9603 | /* FIXME: How do we handle overflow here? */ |
9604 | offset_expr.X_add_number += 4; | |
beae10d5 | 9605 | /* Itbl support may require additional care here. */ |
67c0d1eb | 9606 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 9607 | BFD_RELOC_LO16, AT); |
4d7206a2 RS |
9608 | if (mips_relax.sequence) |
9609 | relax_end (); | |
bdaaa2e1 | 9610 | } |
0a44bf69 | 9611 | else if (!mips_big_got) |
252b5132 | 9612 | { |
252b5132 RH |
9613 | /* If this is a reference to an external symbol, we want |
9614 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
9615 | nop | |
9616 | <op> $treg,0($at) | |
9617 | <op> $treg+1,4($at) | |
9618 | Otherwise we want | |
9619 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
9620 | nop | |
9621 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
9622 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
9623 | If there is a base register we add it to $at before the | |
9624 | lwc1 instructions. If there is a constant we include it | |
9625 | in the lwc1 instructions. */ | |
9626 | used_at = 1; | |
9627 | expr1.X_add_number = offset_expr.X_add_number; | |
252b5132 RH |
9628 | if (expr1.X_add_number < -0x8000 |
9629 | || expr1.X_add_number >= 0x8000 - 4) | |
9630 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 9631 | load_got_offset (AT, &offset_expr); |
269137b2 | 9632 | load_delay_nop (); |
252b5132 | 9633 | if (breg != 0) |
67c0d1eb | 9634 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
252b5132 RH |
9635 | |
9636 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
9637 | nop. */ | |
9638 | hold_mips_optimize = mips_optimize; | |
9639 | mips_optimize = 2; | |
4d7206a2 | 9640 | |
beae10d5 | 9641 | /* Itbl support may require additional care here. */ |
4d7206a2 | 9642 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
9643 | macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg, |
9644 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 9645 | expr1.X_add_number += 4; |
67c0d1eb RS |
9646 | macro_build (&expr1, s, fmt, coproc ? treg : treg + 1, |
9647 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 9648 | relax_switch (); |
67c0d1eb RS |
9649 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
9650 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 9651 | offset_expr.X_add_number += 4; |
67c0d1eb RS |
9652 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
9653 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 9654 | relax_end (); |
252b5132 | 9655 | |
4d7206a2 | 9656 | mips_optimize = hold_mips_optimize; |
252b5132 | 9657 | } |
0a44bf69 | 9658 | else if (mips_big_got) |
252b5132 | 9659 | { |
67c0d1eb | 9660 | int gpdelay; |
252b5132 RH |
9661 | |
9662 | /* If this is a reference to an external symbol, we want | |
9663 | lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
9664 | addu $at,$at,$gp | |
9665 | lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16) | |
9666 | nop | |
9667 | <op> $treg,0($at) | |
9668 | <op> $treg+1,4($at) | |
9669 | Otherwise we want | |
9670 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
9671 | nop | |
9672 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
9673 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
9674 | If there is a base register we add it to $at before the | |
9675 | lwc1 instructions. If there is a constant we include it | |
9676 | in the lwc1 instructions. */ | |
9677 | used_at = 1; | |
9678 | expr1.X_add_number = offset_expr.X_add_number; | |
9679 | offset_expr.X_add_number = 0; | |
9680 | if (expr1.X_add_number < -0x8000 | |
9681 | || expr1.X_add_number >= 0x8000 - 4) | |
9682 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 9683 | gpdelay = reg_needs_delay (mips_gp_register); |
4d7206a2 | 9684 | relax_start (offset_expr.X_add_symbol); |
df58fc94 | 9685 | macro_build (&offset_expr, "lui", LUI_FMT, |
67c0d1eb RS |
9686 | AT, BFD_RELOC_MIPS_GOT_HI16); |
9687 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 9688 | AT, AT, mips_gp_register); |
67c0d1eb | 9689 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
17a2f251 | 9690 | AT, BFD_RELOC_MIPS_GOT_LO16, AT); |
269137b2 | 9691 | load_delay_nop (); |
252b5132 | 9692 | if (breg != 0) |
67c0d1eb | 9693 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 9694 | /* Itbl support may require additional care here. */ |
67c0d1eb | 9695 | macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 9696 | BFD_RELOC_LO16, AT); |
252b5132 RH |
9697 | expr1.X_add_number += 4; |
9698 | ||
9699 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
9700 | nop. */ | |
9701 | hold_mips_optimize = mips_optimize; | |
9702 | mips_optimize = 2; | |
beae10d5 | 9703 | /* Itbl support may require additional care here. */ |
67c0d1eb | 9704 | macro_build (&expr1, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 9705 | BFD_RELOC_LO16, AT); |
252b5132 RH |
9706 | mips_optimize = hold_mips_optimize; |
9707 | expr1.X_add_number -= 4; | |
9708 | ||
4d7206a2 RS |
9709 | relax_switch (); |
9710 | offset_expr.X_add_number = expr1.X_add_number; | |
67c0d1eb RS |
9711 | if (gpdelay) |
9712 | macro_build (NULL, "nop", ""); | |
9713 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, | |
9714 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 9715 | load_delay_nop (); |
252b5132 | 9716 | if (breg != 0) |
67c0d1eb | 9717 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 9718 | /* Itbl support may require additional care here. */ |
67c0d1eb RS |
9719 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
9720 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 9721 | offset_expr.X_add_number += 4; |
252b5132 RH |
9722 | |
9723 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
9724 | nop. */ | |
9725 | hold_mips_optimize = mips_optimize; | |
9726 | mips_optimize = 2; | |
beae10d5 | 9727 | /* Itbl support may require additional care here. */ |
67c0d1eb RS |
9728 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
9729 | BFD_RELOC_LO16, AT); | |
252b5132 | 9730 | mips_optimize = hold_mips_optimize; |
4d7206a2 | 9731 | relax_end (); |
252b5132 | 9732 | } |
252b5132 RH |
9733 | else |
9734 | abort (); | |
9735 | ||
252b5132 RH |
9736 | break; |
9737 | ||
9738 | case M_LD_OB: | |
704897fb | 9739 | s = HAVE_64BIT_GPRS ? "ld" : "lw"; |
252b5132 RH |
9740 | goto sd_ob; |
9741 | case M_SD_OB: | |
704897fb | 9742 | s = HAVE_64BIT_GPRS ? "sd" : "sw"; |
252b5132 | 9743 | sd_ob: |
4614d845 MR |
9744 | macro_build (&offset_expr, s, "t,o(b)", treg, |
9745 | -1, offset_reloc[0], offset_reloc[1], offset_reloc[2], | |
9746 | breg); | |
704897fb MR |
9747 | if (!HAVE_64BIT_GPRS) |
9748 | { | |
9749 | offset_expr.X_add_number += 4; | |
9750 | macro_build (&offset_expr, s, "t,o(b)", treg + 1, | |
4614d845 MR |
9751 | -1, offset_reloc[0], offset_reloc[1], offset_reloc[2], |
9752 | breg); | |
704897fb | 9753 | } |
8fc2e39e | 9754 | break; |
252b5132 | 9755 | |
dd6a37e7 AP |
9756 | |
9757 | case M_SAA_AB: | |
9758 | ab = 1; | |
9759 | case M_SAA_OB: | |
9760 | s = "saa"; | |
7f3c4072 | 9761 | offbits = 0; |
dd6a37e7 AP |
9762 | fmt = "t,(b)"; |
9763 | goto ld_st; | |
9764 | case M_SAAD_AB: | |
9765 | ab = 1; | |
9766 | case M_SAAD_OB: | |
9767 | s = "saad"; | |
7f3c4072 | 9768 | offbits = 0; |
dd6a37e7 AP |
9769 | fmt = "t,(b)"; |
9770 | goto ld_st; | |
9771 | ||
252b5132 RH |
9772 | /* New code added to support COPZ instructions. |
9773 | This code builds table entries out of the macros in mip_opcodes. | |
9774 | R4000 uses interlocks to handle coproc delays. | |
9775 | Other chips (like the R3000) require nops to be inserted for delays. | |
9776 | ||
f72c8c98 | 9777 | FIXME: Currently, we require that the user handle delays. |
252b5132 RH |
9778 | In order to fill delay slots for non-interlocked chips, |
9779 | we must have a way to specify delays based on the coprocessor. | |
9780 | Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc. | |
9781 | What are the side-effects of the cop instruction? | |
9782 | What cache support might we have and what are its effects? | |
9783 | Both coprocessor & memory require delays. how long??? | |
bdaaa2e1 | 9784 | What registers are read/set/modified? |
252b5132 RH |
9785 | |
9786 | If an itbl is provided to interpret cop instructions, | |
bdaaa2e1 | 9787 | this knowledge can be encoded in the itbl spec. */ |
252b5132 RH |
9788 | |
9789 | case M_COP0: | |
9790 | s = "c0"; | |
9791 | goto copz; | |
9792 | case M_COP1: | |
9793 | s = "c1"; | |
9794 | goto copz; | |
9795 | case M_COP2: | |
9796 | s = "c2"; | |
9797 | goto copz; | |
9798 | case M_COP3: | |
9799 | s = "c3"; | |
9800 | copz: | |
df58fc94 | 9801 | gas_assert (!mips_opts.micromips); |
252b5132 RH |
9802 | /* For now we just do C (same as Cz). The parameter will be |
9803 | stored in insn_opcode by mips_ip. */ | |
67c0d1eb | 9804 | macro_build (NULL, s, "C", ip->insn_opcode); |
8fc2e39e | 9805 | break; |
252b5132 | 9806 | |
ea1fb5dc | 9807 | case M_MOVE: |
67c0d1eb | 9808 | move_register (dreg, sreg); |
8fc2e39e | 9809 | break; |
ea1fb5dc | 9810 | |
252b5132 RH |
9811 | case M_DMUL: |
9812 | dbl = 1; | |
9813 | case M_MUL: | |
e407c74b NC |
9814 | if (mips_opts.arch == CPU_R5900) |
9815 | { | |
9816 | macro_build (NULL, dbl ? "dmultu" : "multu", "d,s,t", dreg, sreg, treg); | |
9817 | } | |
9818 | else | |
9819 | { | |
67c0d1eb | 9820 | macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", sreg, treg); |
df58fc94 | 9821 | macro_build (NULL, "mflo", MFHL_FMT, dreg); |
e407c74b | 9822 | } |
8fc2e39e | 9823 | break; |
252b5132 RH |
9824 | |
9825 | case M_DMUL_I: | |
9826 | dbl = 1; | |
9827 | case M_MUL_I: | |
9828 | /* The MIPS assembler some times generates shifts and adds. I'm | |
9829 | not trying to be that fancy. GCC should do this for us | |
9830 | anyway. */ | |
8fc2e39e | 9831 | used_at = 1; |
67c0d1eb RS |
9832 | load_register (AT, &imm_expr, dbl); |
9833 | macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, AT); | |
df58fc94 | 9834 | macro_build (NULL, "mflo", MFHL_FMT, dreg); |
252b5132 RH |
9835 | break; |
9836 | ||
9837 | case M_DMULO_I: | |
9838 | dbl = 1; | |
9839 | case M_MULO_I: | |
9840 | imm = 1; | |
9841 | goto do_mulo; | |
9842 | ||
9843 | case M_DMULO: | |
9844 | dbl = 1; | |
9845 | case M_MULO: | |
9846 | do_mulo: | |
7d10b47d | 9847 | start_noreorder (); |
8fc2e39e | 9848 | used_at = 1; |
252b5132 | 9849 | if (imm) |
67c0d1eb RS |
9850 | load_register (AT, &imm_expr, dbl); |
9851 | macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, imm ? AT : treg); | |
df58fc94 RS |
9852 | macro_build (NULL, "mflo", MFHL_FMT, dreg); |
9853 | macro_build (NULL, dbl ? "dsra32" : "sra", SHFT_FMT, dreg, dreg, RA); | |
9854 | macro_build (NULL, "mfhi", MFHL_FMT, AT); | |
252b5132 | 9855 | if (mips_trap) |
df58fc94 | 9856 | macro_build (NULL, "tne", TRAP_FMT, dreg, AT, 6); |
252b5132 RH |
9857 | else |
9858 | { | |
df58fc94 RS |
9859 | if (mips_opts.micromips) |
9860 | micromips_label_expr (&label_expr); | |
9861 | else | |
9862 | label_expr.X_add_number = 8; | |
9863 | macro_build (&label_expr, "beq", "s,t,p", dreg, AT); | |
a605d2b3 | 9864 | macro_build (NULL, "nop", ""); |
df58fc94 RS |
9865 | macro_build (NULL, "break", BRK_FMT, 6); |
9866 | if (mips_opts.micromips) | |
9867 | micromips_add_label (); | |
252b5132 | 9868 | } |
7d10b47d | 9869 | end_noreorder (); |
df58fc94 | 9870 | macro_build (NULL, "mflo", MFHL_FMT, dreg); |
252b5132 RH |
9871 | break; |
9872 | ||
9873 | case M_DMULOU_I: | |
9874 | dbl = 1; | |
9875 | case M_MULOU_I: | |
9876 | imm = 1; | |
9877 | goto do_mulou; | |
9878 | ||
9879 | case M_DMULOU: | |
9880 | dbl = 1; | |
9881 | case M_MULOU: | |
9882 | do_mulou: | |
7d10b47d | 9883 | start_noreorder (); |
8fc2e39e | 9884 | used_at = 1; |
252b5132 | 9885 | if (imm) |
67c0d1eb RS |
9886 | load_register (AT, &imm_expr, dbl); |
9887 | macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", | |
17a2f251 | 9888 | sreg, imm ? AT : treg); |
df58fc94 RS |
9889 | macro_build (NULL, "mfhi", MFHL_FMT, AT); |
9890 | macro_build (NULL, "mflo", MFHL_FMT, dreg); | |
252b5132 | 9891 | if (mips_trap) |
df58fc94 | 9892 | macro_build (NULL, "tne", TRAP_FMT, AT, ZERO, 6); |
252b5132 RH |
9893 | else |
9894 | { | |
df58fc94 RS |
9895 | if (mips_opts.micromips) |
9896 | micromips_label_expr (&label_expr); | |
9897 | else | |
9898 | label_expr.X_add_number = 8; | |
9899 | macro_build (&label_expr, "beq", "s,t,p", AT, ZERO); | |
a605d2b3 | 9900 | macro_build (NULL, "nop", ""); |
df58fc94 RS |
9901 | macro_build (NULL, "break", BRK_FMT, 6); |
9902 | if (mips_opts.micromips) | |
9903 | micromips_add_label (); | |
252b5132 | 9904 | } |
7d10b47d | 9905 | end_noreorder (); |
252b5132 RH |
9906 | break; |
9907 | ||
771c7ce4 | 9908 | case M_DROL: |
fef14a42 | 9909 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 CD |
9910 | { |
9911 | if (dreg == sreg) | |
9912 | { | |
9913 | tempreg = AT; | |
9914 | used_at = 1; | |
9915 | } | |
9916 | else | |
9917 | { | |
9918 | tempreg = dreg; | |
82dd0097 | 9919 | } |
67c0d1eb RS |
9920 | macro_build (NULL, "dnegu", "d,w", tempreg, treg); |
9921 | macro_build (NULL, "drorv", "d,t,s", dreg, sreg, tempreg); | |
8fc2e39e | 9922 | break; |
82dd0097 | 9923 | } |
8fc2e39e | 9924 | used_at = 1; |
c80c840e | 9925 | macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, treg); |
67c0d1eb RS |
9926 | macro_build (NULL, "dsrlv", "d,t,s", AT, sreg, AT); |
9927 | macro_build (NULL, "dsllv", "d,t,s", dreg, sreg, treg); | |
9928 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
9929 | break; |
9930 | ||
252b5132 | 9931 | case M_ROL: |
fef14a42 | 9932 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 CD |
9933 | { |
9934 | if (dreg == sreg) | |
9935 | { | |
9936 | tempreg = AT; | |
9937 | used_at = 1; | |
9938 | } | |
9939 | else | |
9940 | { | |
9941 | tempreg = dreg; | |
82dd0097 | 9942 | } |
67c0d1eb RS |
9943 | macro_build (NULL, "negu", "d,w", tempreg, treg); |
9944 | macro_build (NULL, "rorv", "d,t,s", dreg, sreg, tempreg); | |
8fc2e39e | 9945 | break; |
82dd0097 | 9946 | } |
8fc2e39e | 9947 | used_at = 1; |
c80c840e | 9948 | macro_build (NULL, "subu", "d,v,t", AT, ZERO, treg); |
67c0d1eb RS |
9949 | macro_build (NULL, "srlv", "d,t,s", AT, sreg, AT); |
9950 | macro_build (NULL, "sllv", "d,t,s", dreg, sreg, treg); | |
9951 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
9952 | break; |
9953 | ||
771c7ce4 TS |
9954 | case M_DROL_I: |
9955 | { | |
9956 | unsigned int rot; | |
91d6fa6a NC |
9957 | char *l; |
9958 | char *rr; | |
771c7ce4 TS |
9959 | |
9960 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 9961 | as_bad (_("Improper rotate count")); |
771c7ce4 | 9962 | rot = imm_expr.X_add_number & 0x3f; |
fef14a42 | 9963 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
60b63b72 RS |
9964 | { |
9965 | rot = (64 - rot) & 0x3f; | |
9966 | if (rot >= 32) | |
df58fc94 | 9967 | macro_build (NULL, "dror32", SHFT_FMT, dreg, sreg, rot - 32); |
60b63b72 | 9968 | else |
df58fc94 | 9969 | macro_build (NULL, "dror", SHFT_FMT, dreg, sreg, rot); |
8fc2e39e | 9970 | break; |
60b63b72 | 9971 | } |
483fc7cd | 9972 | if (rot == 0) |
483fc7cd | 9973 | { |
df58fc94 | 9974 | macro_build (NULL, "dsrl", SHFT_FMT, dreg, sreg, 0); |
8fc2e39e | 9975 | break; |
483fc7cd | 9976 | } |
82dd0097 | 9977 | l = (rot < 0x20) ? "dsll" : "dsll32"; |
91d6fa6a | 9978 | rr = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32"; |
82dd0097 | 9979 | rot &= 0x1f; |
8fc2e39e | 9980 | used_at = 1; |
df58fc94 RS |
9981 | macro_build (NULL, l, SHFT_FMT, AT, sreg, rot); |
9982 | macro_build (NULL, rr, SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f); | |
67c0d1eb | 9983 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); |
771c7ce4 TS |
9984 | } |
9985 | break; | |
9986 | ||
252b5132 | 9987 | case M_ROL_I: |
771c7ce4 TS |
9988 | { |
9989 | unsigned int rot; | |
9990 | ||
9991 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 9992 | as_bad (_("Improper rotate count")); |
771c7ce4 | 9993 | rot = imm_expr.X_add_number & 0x1f; |
fef14a42 | 9994 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
60b63b72 | 9995 | { |
df58fc94 | 9996 | macro_build (NULL, "ror", SHFT_FMT, dreg, sreg, (32 - rot) & 0x1f); |
8fc2e39e | 9997 | break; |
60b63b72 | 9998 | } |
483fc7cd | 9999 | if (rot == 0) |
483fc7cd | 10000 | { |
df58fc94 | 10001 | macro_build (NULL, "srl", SHFT_FMT, dreg, sreg, 0); |
8fc2e39e | 10002 | break; |
483fc7cd | 10003 | } |
8fc2e39e | 10004 | used_at = 1; |
df58fc94 RS |
10005 | macro_build (NULL, "sll", SHFT_FMT, AT, sreg, rot); |
10006 | macro_build (NULL, "srl", SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f); | |
67c0d1eb | 10007 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); |
771c7ce4 TS |
10008 | } |
10009 | break; | |
10010 | ||
10011 | case M_DROR: | |
fef14a42 | 10012 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 | 10013 | { |
67c0d1eb | 10014 | macro_build (NULL, "drorv", "d,t,s", dreg, sreg, treg); |
8fc2e39e | 10015 | break; |
82dd0097 | 10016 | } |
8fc2e39e | 10017 | used_at = 1; |
c80c840e | 10018 | macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, treg); |
67c0d1eb RS |
10019 | macro_build (NULL, "dsllv", "d,t,s", AT, sreg, AT); |
10020 | macro_build (NULL, "dsrlv", "d,t,s", dreg, sreg, treg); | |
10021 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
10022 | break; |
10023 | ||
10024 | case M_ROR: | |
fef14a42 | 10025 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 | 10026 | { |
67c0d1eb | 10027 | macro_build (NULL, "rorv", "d,t,s", dreg, sreg, treg); |
8fc2e39e | 10028 | break; |
82dd0097 | 10029 | } |
8fc2e39e | 10030 | used_at = 1; |
c80c840e | 10031 | macro_build (NULL, "subu", "d,v,t", AT, ZERO, treg); |
67c0d1eb RS |
10032 | macro_build (NULL, "sllv", "d,t,s", AT, sreg, AT); |
10033 | macro_build (NULL, "srlv", "d,t,s", dreg, sreg, treg); | |
10034 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
10035 | break; |
10036 | ||
771c7ce4 TS |
10037 | case M_DROR_I: |
10038 | { | |
10039 | unsigned int rot; | |
91d6fa6a NC |
10040 | char *l; |
10041 | char *rr; | |
771c7ce4 TS |
10042 | |
10043 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 10044 | as_bad (_("Improper rotate count")); |
771c7ce4 | 10045 | rot = imm_expr.X_add_number & 0x3f; |
fef14a42 | 10046 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 CD |
10047 | { |
10048 | if (rot >= 32) | |
df58fc94 | 10049 | macro_build (NULL, "dror32", SHFT_FMT, dreg, sreg, rot - 32); |
82dd0097 | 10050 | else |
df58fc94 | 10051 | macro_build (NULL, "dror", SHFT_FMT, dreg, sreg, rot); |
8fc2e39e | 10052 | break; |
82dd0097 | 10053 | } |
483fc7cd | 10054 | if (rot == 0) |
483fc7cd | 10055 | { |
df58fc94 | 10056 | macro_build (NULL, "dsrl", SHFT_FMT, dreg, sreg, 0); |
8fc2e39e | 10057 | break; |
483fc7cd | 10058 | } |
91d6fa6a | 10059 | rr = (rot < 0x20) ? "dsrl" : "dsrl32"; |
82dd0097 CD |
10060 | l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32"; |
10061 | rot &= 0x1f; | |
8fc2e39e | 10062 | used_at = 1; |
df58fc94 RS |
10063 | macro_build (NULL, rr, SHFT_FMT, AT, sreg, rot); |
10064 | macro_build (NULL, l, SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f); | |
67c0d1eb | 10065 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); |
771c7ce4 TS |
10066 | } |
10067 | break; | |
10068 | ||
252b5132 | 10069 | case M_ROR_I: |
771c7ce4 TS |
10070 | { |
10071 | unsigned int rot; | |
10072 | ||
10073 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 10074 | as_bad (_("Improper rotate count")); |
771c7ce4 | 10075 | rot = imm_expr.X_add_number & 0x1f; |
fef14a42 | 10076 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 | 10077 | { |
df58fc94 | 10078 | macro_build (NULL, "ror", SHFT_FMT, dreg, sreg, rot); |
8fc2e39e | 10079 | break; |
82dd0097 | 10080 | } |
483fc7cd | 10081 | if (rot == 0) |
483fc7cd | 10082 | { |
df58fc94 | 10083 | macro_build (NULL, "srl", SHFT_FMT, dreg, sreg, 0); |
8fc2e39e | 10084 | break; |
483fc7cd | 10085 | } |
8fc2e39e | 10086 | used_at = 1; |
df58fc94 RS |
10087 | macro_build (NULL, "srl", SHFT_FMT, AT, sreg, rot); |
10088 | macro_build (NULL, "sll", SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f); | |
67c0d1eb | 10089 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); |
771c7ce4 | 10090 | } |
252b5132 RH |
10091 | break; |
10092 | ||
252b5132 RH |
10093 | case M_SEQ: |
10094 | if (sreg == 0) | |
67c0d1eb | 10095 | macro_build (&expr1, "sltiu", "t,r,j", dreg, treg, BFD_RELOC_LO16); |
252b5132 | 10096 | else if (treg == 0) |
67c0d1eb | 10097 | macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
10098 | else |
10099 | { | |
67c0d1eb RS |
10100 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg); |
10101 | macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16); | |
252b5132 | 10102 | } |
8fc2e39e | 10103 | break; |
252b5132 RH |
10104 | |
10105 | case M_SEQ_I: | |
10106 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
10107 | { | |
67c0d1eb | 10108 | macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 10109 | break; |
252b5132 RH |
10110 | } |
10111 | if (sreg == 0) | |
10112 | { | |
10113 | as_warn (_("Instruction %s: result is always false"), | |
10114 | ip->insn_mo->name); | |
67c0d1eb | 10115 | move_register (dreg, 0); |
8fc2e39e | 10116 | break; |
252b5132 | 10117 | } |
dd3cbb7e NC |
10118 | if (CPU_HAS_SEQ (mips_opts.arch) |
10119 | && -512 <= imm_expr.X_add_number | |
10120 | && imm_expr.X_add_number < 512) | |
10121 | { | |
10122 | macro_build (NULL, "seqi", "t,r,+Q", dreg, sreg, | |
750bdd57 | 10123 | (int) imm_expr.X_add_number); |
dd3cbb7e NC |
10124 | break; |
10125 | } | |
252b5132 RH |
10126 | if (imm_expr.X_op == O_constant |
10127 | && imm_expr.X_add_number >= 0 | |
10128 | && imm_expr.X_add_number < 0x10000) | |
10129 | { | |
67c0d1eb | 10130 | macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
10131 | } |
10132 | else if (imm_expr.X_op == O_constant | |
10133 | && imm_expr.X_add_number > -0x8000 | |
10134 | && imm_expr.X_add_number < 0) | |
10135 | { | |
10136 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 10137 | macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu", |
17a2f251 | 10138 | "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 | 10139 | } |
dd3cbb7e NC |
10140 | else if (CPU_HAS_SEQ (mips_opts.arch)) |
10141 | { | |
10142 | used_at = 1; | |
10143 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); | |
10144 | macro_build (NULL, "seq", "d,v,t", dreg, sreg, AT); | |
10145 | break; | |
10146 | } | |
252b5132 RH |
10147 | else |
10148 | { | |
67c0d1eb RS |
10149 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
10150 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
10151 | used_at = 1; |
10152 | } | |
67c0d1eb | 10153 | macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16); |
8fc2e39e | 10154 | break; |
252b5132 RH |
10155 | |
10156 | case M_SGE: /* sreg >= treg <==> not (sreg < treg) */ | |
10157 | s = "slt"; | |
10158 | goto sge; | |
10159 | case M_SGEU: | |
10160 | s = "sltu"; | |
10161 | sge: | |
67c0d1eb RS |
10162 | macro_build (NULL, s, "d,v,t", dreg, sreg, treg); |
10163 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
8fc2e39e | 10164 | break; |
252b5132 RH |
10165 | |
10166 | case M_SGE_I: /* sreg >= I <==> not (sreg < I) */ | |
10167 | case M_SGEU_I: | |
10168 | if (imm_expr.X_op == O_constant | |
10169 | && imm_expr.X_add_number >= -0x8000 | |
10170 | && imm_expr.X_add_number < 0x8000) | |
10171 | { | |
67c0d1eb RS |
10172 | macro_build (&imm_expr, mask == M_SGE_I ? "slti" : "sltiu", "t,r,j", |
10173 | dreg, sreg, BFD_RELOC_LO16); | |
252b5132 RH |
10174 | } |
10175 | else | |
10176 | { | |
67c0d1eb RS |
10177 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
10178 | macro_build (NULL, mask == M_SGE_I ? "slt" : "sltu", "d,v,t", | |
10179 | dreg, sreg, AT); | |
252b5132 RH |
10180 | used_at = 1; |
10181 | } | |
67c0d1eb | 10182 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); |
8fc2e39e | 10183 | break; |
252b5132 RH |
10184 | |
10185 | case M_SGT: /* sreg > treg <==> treg < sreg */ | |
10186 | s = "slt"; | |
10187 | goto sgt; | |
10188 | case M_SGTU: | |
10189 | s = "sltu"; | |
10190 | sgt: | |
67c0d1eb | 10191 | macro_build (NULL, s, "d,v,t", dreg, treg, sreg); |
8fc2e39e | 10192 | break; |
252b5132 RH |
10193 | |
10194 | case M_SGT_I: /* sreg > I <==> I < sreg */ | |
10195 | s = "slt"; | |
10196 | goto sgti; | |
10197 | case M_SGTU_I: | |
10198 | s = "sltu"; | |
10199 | sgti: | |
8fc2e39e | 10200 | used_at = 1; |
67c0d1eb RS |
10201 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
10202 | macro_build (NULL, s, "d,v,t", dreg, AT, sreg); | |
252b5132 RH |
10203 | break; |
10204 | ||
2396cfb9 | 10205 | case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */ |
252b5132 RH |
10206 | s = "slt"; |
10207 | goto sle; | |
10208 | case M_SLEU: | |
10209 | s = "sltu"; | |
10210 | sle: | |
67c0d1eb RS |
10211 | macro_build (NULL, s, "d,v,t", dreg, treg, sreg); |
10212 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
8fc2e39e | 10213 | break; |
252b5132 | 10214 | |
2396cfb9 | 10215 | case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */ |
252b5132 RH |
10216 | s = "slt"; |
10217 | goto slei; | |
10218 | case M_SLEU_I: | |
10219 | s = "sltu"; | |
10220 | slei: | |
8fc2e39e | 10221 | used_at = 1; |
67c0d1eb RS |
10222 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
10223 | macro_build (NULL, s, "d,v,t", dreg, AT, sreg); | |
10224 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
252b5132 RH |
10225 | break; |
10226 | ||
10227 | case M_SLT_I: | |
10228 | if (imm_expr.X_op == O_constant | |
10229 | && imm_expr.X_add_number >= -0x8000 | |
10230 | && imm_expr.X_add_number < 0x8000) | |
10231 | { | |
67c0d1eb | 10232 | macro_build (&imm_expr, "slti", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 10233 | break; |
252b5132 | 10234 | } |
8fc2e39e | 10235 | used_at = 1; |
67c0d1eb RS |
10236 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
10237 | macro_build (NULL, "slt", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
10238 | break; |
10239 | ||
10240 | case M_SLTU_I: | |
10241 | if (imm_expr.X_op == O_constant | |
10242 | && imm_expr.X_add_number >= -0x8000 | |
10243 | && imm_expr.X_add_number < 0x8000) | |
10244 | { | |
67c0d1eb | 10245 | macro_build (&imm_expr, "sltiu", "t,r,j", dreg, sreg, |
17a2f251 | 10246 | BFD_RELOC_LO16); |
8fc2e39e | 10247 | break; |
252b5132 | 10248 | } |
8fc2e39e | 10249 | used_at = 1; |
67c0d1eb RS |
10250 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
10251 | macro_build (NULL, "sltu", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
10252 | break; |
10253 | ||
10254 | case M_SNE: | |
10255 | if (sreg == 0) | |
67c0d1eb | 10256 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, treg); |
252b5132 | 10257 | else if (treg == 0) |
67c0d1eb | 10258 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg); |
252b5132 RH |
10259 | else |
10260 | { | |
67c0d1eb RS |
10261 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg); |
10262 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg); | |
252b5132 | 10263 | } |
8fc2e39e | 10264 | break; |
252b5132 RH |
10265 | |
10266 | case M_SNE_I: | |
10267 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
10268 | { | |
67c0d1eb | 10269 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg); |
8fc2e39e | 10270 | break; |
252b5132 RH |
10271 | } |
10272 | if (sreg == 0) | |
10273 | { | |
10274 | as_warn (_("Instruction %s: result is always true"), | |
10275 | ip->insn_mo->name); | |
67c0d1eb RS |
10276 | macro_build (&expr1, HAVE_32BIT_GPRS ? "addiu" : "daddiu", "t,r,j", |
10277 | dreg, 0, BFD_RELOC_LO16); | |
8fc2e39e | 10278 | break; |
252b5132 | 10279 | } |
dd3cbb7e NC |
10280 | if (CPU_HAS_SEQ (mips_opts.arch) |
10281 | && -512 <= imm_expr.X_add_number | |
10282 | && imm_expr.X_add_number < 512) | |
10283 | { | |
10284 | macro_build (NULL, "snei", "t,r,+Q", dreg, sreg, | |
750bdd57 | 10285 | (int) imm_expr.X_add_number); |
dd3cbb7e NC |
10286 | break; |
10287 | } | |
252b5132 RH |
10288 | if (imm_expr.X_op == O_constant |
10289 | && imm_expr.X_add_number >= 0 | |
10290 | && imm_expr.X_add_number < 0x10000) | |
10291 | { | |
67c0d1eb | 10292 | macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
10293 | } |
10294 | else if (imm_expr.X_op == O_constant | |
10295 | && imm_expr.X_add_number > -0x8000 | |
10296 | && imm_expr.X_add_number < 0) | |
10297 | { | |
10298 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 10299 | macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu", |
17a2f251 | 10300 | "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 | 10301 | } |
dd3cbb7e NC |
10302 | else if (CPU_HAS_SEQ (mips_opts.arch)) |
10303 | { | |
10304 | used_at = 1; | |
10305 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); | |
10306 | macro_build (NULL, "sne", "d,v,t", dreg, sreg, AT); | |
10307 | break; | |
10308 | } | |
252b5132 RH |
10309 | else |
10310 | { | |
67c0d1eb RS |
10311 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
10312 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
10313 | used_at = 1; |
10314 | } | |
67c0d1eb | 10315 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg); |
8fc2e39e | 10316 | break; |
252b5132 | 10317 | |
df58fc94 RS |
10318 | case M_SUB_I: |
10319 | s = "addi"; | |
10320 | s2 = "sub"; | |
10321 | goto do_subi; | |
10322 | case M_SUBU_I: | |
10323 | s = "addiu"; | |
10324 | s2 = "subu"; | |
10325 | goto do_subi; | |
252b5132 RH |
10326 | case M_DSUB_I: |
10327 | dbl = 1; | |
df58fc94 RS |
10328 | s = "daddi"; |
10329 | s2 = "dsub"; | |
10330 | if (!mips_opts.micromips) | |
10331 | goto do_subi; | |
252b5132 | 10332 | if (imm_expr.X_op == O_constant |
df58fc94 RS |
10333 | && imm_expr.X_add_number > -0x200 |
10334 | && imm_expr.X_add_number <= 0x200) | |
252b5132 | 10335 | { |
df58fc94 | 10336 | macro_build (NULL, s, "t,r,.", dreg, sreg, -imm_expr.X_add_number); |
8fc2e39e | 10337 | break; |
252b5132 | 10338 | } |
df58fc94 | 10339 | goto do_subi_i; |
252b5132 RH |
10340 | case M_DSUBU_I: |
10341 | dbl = 1; | |
df58fc94 RS |
10342 | s = "daddiu"; |
10343 | s2 = "dsubu"; | |
10344 | do_subi: | |
252b5132 RH |
10345 | if (imm_expr.X_op == O_constant |
10346 | && imm_expr.X_add_number > -0x8000 | |
10347 | && imm_expr.X_add_number <= 0x8000) | |
10348 | { | |
10349 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
df58fc94 | 10350 | macro_build (&imm_expr, s, "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 10351 | break; |
252b5132 | 10352 | } |
df58fc94 | 10353 | do_subi_i: |
8fc2e39e | 10354 | used_at = 1; |
67c0d1eb | 10355 | load_register (AT, &imm_expr, dbl); |
df58fc94 | 10356 | macro_build (NULL, s2, "d,v,t", dreg, sreg, AT); |
252b5132 RH |
10357 | break; |
10358 | ||
10359 | case M_TEQ_I: | |
10360 | s = "teq"; | |
10361 | goto trap; | |
10362 | case M_TGE_I: | |
10363 | s = "tge"; | |
10364 | goto trap; | |
10365 | case M_TGEU_I: | |
10366 | s = "tgeu"; | |
10367 | goto trap; | |
10368 | case M_TLT_I: | |
10369 | s = "tlt"; | |
10370 | goto trap; | |
10371 | case M_TLTU_I: | |
10372 | s = "tltu"; | |
10373 | goto trap; | |
10374 | case M_TNE_I: | |
10375 | s = "tne"; | |
10376 | trap: | |
8fc2e39e | 10377 | used_at = 1; |
67c0d1eb RS |
10378 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
10379 | macro_build (NULL, s, "s,t", sreg, AT); | |
252b5132 RH |
10380 | break; |
10381 | ||
252b5132 | 10382 | case M_TRUNCWS: |
43841e91 | 10383 | case M_TRUNCWD: |
df58fc94 | 10384 | gas_assert (!mips_opts.micromips); |
0aa27725 | 10385 | gas_assert (mips_opts.isa == ISA_MIPS1); |
8fc2e39e | 10386 | used_at = 1; |
252b5132 RH |
10387 | sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */ |
10388 | dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */ | |
10389 | ||
10390 | /* | |
10391 | * Is the double cfc1 instruction a bug in the mips assembler; | |
10392 | * or is there a reason for it? | |
10393 | */ | |
7d10b47d | 10394 | start_noreorder (); |
67c0d1eb RS |
10395 | macro_build (NULL, "cfc1", "t,G", treg, RA); |
10396 | macro_build (NULL, "cfc1", "t,G", treg, RA); | |
10397 | macro_build (NULL, "nop", ""); | |
252b5132 | 10398 | expr1.X_add_number = 3; |
67c0d1eb | 10399 | macro_build (&expr1, "ori", "t,r,i", AT, treg, BFD_RELOC_LO16); |
252b5132 | 10400 | expr1.X_add_number = 2; |
67c0d1eb RS |
10401 | macro_build (&expr1, "xori", "t,r,i", AT, AT, BFD_RELOC_LO16); |
10402 | macro_build (NULL, "ctc1", "t,G", AT, RA); | |
10403 | macro_build (NULL, "nop", ""); | |
10404 | macro_build (NULL, mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S", | |
10405 | dreg, sreg); | |
10406 | macro_build (NULL, "ctc1", "t,G", treg, RA); | |
10407 | macro_build (NULL, "nop", ""); | |
7d10b47d | 10408 | end_noreorder (); |
252b5132 RH |
10409 | break; |
10410 | ||
df58fc94 RS |
10411 | case M_ULH_A: |
10412 | ab = 1; | |
252b5132 RH |
10413 | case M_ULH: |
10414 | s = "lb"; | |
df58fc94 RS |
10415 | s2 = "lbu"; |
10416 | off = 1; | |
10417 | goto uld_st; | |
10418 | case M_ULHU_A: | |
10419 | ab = 1; | |
252b5132 RH |
10420 | case M_ULHU: |
10421 | s = "lbu"; | |
df58fc94 RS |
10422 | s2 = "lbu"; |
10423 | off = 1; | |
10424 | goto uld_st; | |
10425 | case M_ULW_A: | |
10426 | ab = 1; | |
10427 | case M_ULW: | |
10428 | s = "lwl"; | |
10429 | s2 = "lwr"; | |
7f3c4072 | 10430 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 RS |
10431 | off = 3; |
10432 | goto uld_st; | |
10433 | case M_ULD_A: | |
10434 | ab = 1; | |
252b5132 RH |
10435 | case M_ULD: |
10436 | s = "ldl"; | |
10437 | s2 = "ldr"; | |
7f3c4072 | 10438 | offbits = (mips_opts.micromips ? 12 : 16); |
252b5132 | 10439 | off = 7; |
df58fc94 RS |
10440 | goto uld_st; |
10441 | case M_USH_A: | |
10442 | ab = 1; | |
10443 | case M_USH: | |
10444 | s = "sb"; | |
10445 | s2 = "sb"; | |
10446 | off = 1; | |
10447 | ust = 1; | |
10448 | goto uld_st; | |
10449 | case M_USW_A: | |
10450 | ab = 1; | |
10451 | case M_USW: | |
10452 | s = "swl"; | |
10453 | s2 = "swr"; | |
7f3c4072 | 10454 | offbits = (mips_opts.micromips ? 12 : 16); |
252b5132 | 10455 | off = 3; |
df58fc94 RS |
10456 | ust = 1; |
10457 | goto uld_st; | |
10458 | case M_USD_A: | |
10459 | ab = 1; | |
10460 | case M_USD: | |
10461 | s = "sdl"; | |
10462 | s2 = "sdr"; | |
7f3c4072 | 10463 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 RS |
10464 | off = 7; |
10465 | ust = 1; | |
10466 | ||
10467 | uld_st: | |
10468 | if (!ab && offset_expr.X_add_number >= 0x8000 - off) | |
f71d0d44 | 10469 | as_bad (_("Operand overflow")); |
df58fc94 RS |
10470 | |
10471 | ep = &offset_expr; | |
10472 | expr1.X_add_number = 0; | |
10473 | if (ab) | |
10474 | { | |
10475 | used_at = 1; | |
10476 | tempreg = AT; | |
10477 | load_address (tempreg, ep, &used_at); | |
10478 | if (breg != 0) | |
10479 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
10480 | tempreg, tempreg, breg); | |
10481 | breg = tempreg; | |
10482 | tempreg = treg; | |
10483 | ep = &expr1; | |
10484 | } | |
7f3c4072 | 10485 | else if (offbits == 12 |
df58fc94 RS |
10486 | && (offset_expr.X_op != O_constant |
10487 | || !IS_SEXT_12BIT_NUM (offset_expr.X_add_number) | |
10488 | || !IS_SEXT_12BIT_NUM (offset_expr.X_add_number + off))) | |
10489 | { | |
10490 | used_at = 1; | |
10491 | tempreg = AT; | |
10492 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", tempreg, breg, | |
10493 | -1, offset_reloc[0], offset_reloc[1], offset_reloc[2]); | |
10494 | breg = tempreg; | |
10495 | tempreg = treg; | |
10496 | ep = &expr1; | |
10497 | } | |
10498 | else if (!ust && treg == breg) | |
8fc2e39e TS |
10499 | { |
10500 | used_at = 1; | |
10501 | tempreg = AT; | |
10502 | } | |
252b5132 | 10503 | else |
df58fc94 | 10504 | tempreg = treg; |
af22f5b2 | 10505 | |
df58fc94 RS |
10506 | if (off == 1) |
10507 | goto ulh_sh; | |
252b5132 | 10508 | |
90ecf173 | 10509 | if (!target_big_endian) |
df58fc94 | 10510 | ep->X_add_number += off; |
7f3c4072 | 10511 | if (offbits != 12) |
df58fc94 | 10512 | macro_build (ep, s, "t,o(b)", tempreg, BFD_RELOC_LO16, breg); |
252b5132 | 10513 | else |
df58fc94 RS |
10514 | macro_build (NULL, s, "t,~(b)", |
10515 | tempreg, (unsigned long) ep->X_add_number, breg); | |
10516 | ||
90ecf173 | 10517 | if (!target_big_endian) |
df58fc94 | 10518 | ep->X_add_number -= off; |
252b5132 | 10519 | else |
df58fc94 | 10520 | ep->X_add_number += off; |
7f3c4072 | 10521 | if (offbits != 12) |
df58fc94 RS |
10522 | macro_build (ep, s2, "t,o(b)", tempreg, BFD_RELOC_LO16, breg); |
10523 | else | |
10524 | macro_build (NULL, s2, "t,~(b)", | |
10525 | tempreg, (unsigned long) ep->X_add_number, breg); | |
252b5132 | 10526 | |
df58fc94 RS |
10527 | /* If necessary, move the result in tempreg to the final destination. */ |
10528 | if (!ust && treg != tempreg) | |
10529 | { | |
10530 | /* Protect second load's delay slot. */ | |
10531 | load_delay_nop (); | |
10532 | move_register (treg, tempreg); | |
10533 | } | |
8fc2e39e | 10534 | break; |
252b5132 | 10535 | |
df58fc94 | 10536 | ulh_sh: |
d6bc6245 | 10537 | used_at = 1; |
df58fc94 RS |
10538 | if (target_big_endian == ust) |
10539 | ep->X_add_number += off; | |
10540 | tempreg = ust || ab ? treg : AT; | |
10541 | macro_build (ep, s, "t,o(b)", tempreg, BFD_RELOC_LO16, breg); | |
10542 | ||
10543 | /* For halfword transfers we need a temporary register to shuffle | |
10544 | bytes. Unfortunately for M_USH_A we have none available before | |
10545 | the next store as AT holds the base address. We deal with this | |
10546 | case by clobbering TREG and then restoring it as with ULH. */ | |
10547 | tempreg = ust == ab ? treg : AT; | |
10548 | if (ust) | |
10549 | macro_build (NULL, "srl", SHFT_FMT, tempreg, treg, 8); | |
10550 | ||
10551 | if (target_big_endian == ust) | |
10552 | ep->X_add_number -= off; | |
252b5132 | 10553 | else |
df58fc94 RS |
10554 | ep->X_add_number += off; |
10555 | macro_build (ep, s2, "t,o(b)", tempreg, BFD_RELOC_LO16, breg); | |
252b5132 | 10556 | |
df58fc94 RS |
10557 | /* For M_USH_A re-retrieve the LSB. */ |
10558 | if (ust && ab) | |
10559 | { | |
10560 | if (target_big_endian) | |
10561 | ep->X_add_number += off; | |
10562 | else | |
10563 | ep->X_add_number -= off; | |
10564 | macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT); | |
10565 | } | |
10566 | /* For ULH and M_USH_A OR the LSB in. */ | |
10567 | if (!ust || ab) | |
10568 | { | |
10569 | tempreg = !ab ? AT : treg; | |
10570 | macro_build (NULL, "sll", SHFT_FMT, tempreg, tempreg, 8); | |
10571 | macro_build (NULL, "or", "d,v,t", treg, treg, AT); | |
10572 | } | |
252b5132 RH |
10573 | break; |
10574 | ||
10575 | default: | |
10576 | /* FIXME: Check if this is one of the itbl macros, since they | |
bdaaa2e1 | 10577 | are added dynamically. */ |
252b5132 RH |
10578 | as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name); |
10579 | break; | |
10580 | } | |
741fe287 | 10581 | if (!mips_opts.at && used_at) |
8fc2e39e | 10582 | as_bad (_("Macro used $at after \".set noat\"")); |
252b5132 RH |
10583 | } |
10584 | ||
10585 | /* Implement macros in mips16 mode. */ | |
10586 | ||
10587 | static void | |
17a2f251 | 10588 | mips16_macro (struct mips_cl_insn *ip) |
252b5132 RH |
10589 | { |
10590 | int mask; | |
10591 | int xreg, yreg, zreg, tmp; | |
252b5132 RH |
10592 | expressionS expr1; |
10593 | int dbl; | |
10594 | const char *s, *s2, *s3; | |
10595 | ||
10596 | mask = ip->insn_mo->mask; | |
10597 | ||
bf12938e RS |
10598 | xreg = MIPS16_EXTRACT_OPERAND (RX, *ip); |
10599 | yreg = MIPS16_EXTRACT_OPERAND (RY, *ip); | |
10600 | zreg = MIPS16_EXTRACT_OPERAND (RZ, *ip); | |
252b5132 | 10601 | |
252b5132 RH |
10602 | expr1.X_op = O_constant; |
10603 | expr1.X_op_symbol = NULL; | |
10604 | expr1.X_add_symbol = NULL; | |
10605 | expr1.X_add_number = 1; | |
10606 | ||
10607 | dbl = 0; | |
10608 | ||
10609 | switch (mask) | |
10610 | { | |
10611 | default: | |
b37df7c4 | 10612 | abort (); |
252b5132 RH |
10613 | |
10614 | case M_DDIV_3: | |
10615 | dbl = 1; | |
10616 | case M_DIV_3: | |
10617 | s = "mflo"; | |
10618 | goto do_div3; | |
10619 | case M_DREM_3: | |
10620 | dbl = 1; | |
10621 | case M_REM_3: | |
10622 | s = "mfhi"; | |
10623 | do_div3: | |
7d10b47d | 10624 | start_noreorder (); |
67c0d1eb | 10625 | macro_build (NULL, dbl ? "ddiv" : "div", "0,x,y", xreg, yreg); |
252b5132 | 10626 | expr1.X_add_number = 2; |
67c0d1eb RS |
10627 | macro_build (&expr1, "bnez", "x,p", yreg); |
10628 | macro_build (NULL, "break", "6", 7); | |
bdaaa2e1 | 10629 | |
252b5132 RH |
10630 | /* FIXME: The normal code checks for of -1 / -0x80000000 here, |
10631 | since that causes an overflow. We should do that as well, | |
10632 | but I don't see how to do the comparisons without a temporary | |
10633 | register. */ | |
7d10b47d | 10634 | end_noreorder (); |
67c0d1eb | 10635 | macro_build (NULL, s, "x", zreg); |
252b5132 RH |
10636 | break; |
10637 | ||
10638 | case M_DIVU_3: | |
10639 | s = "divu"; | |
10640 | s2 = "mflo"; | |
10641 | goto do_divu3; | |
10642 | case M_REMU_3: | |
10643 | s = "divu"; | |
10644 | s2 = "mfhi"; | |
10645 | goto do_divu3; | |
10646 | case M_DDIVU_3: | |
10647 | s = "ddivu"; | |
10648 | s2 = "mflo"; | |
10649 | goto do_divu3; | |
10650 | case M_DREMU_3: | |
10651 | s = "ddivu"; | |
10652 | s2 = "mfhi"; | |
10653 | do_divu3: | |
7d10b47d | 10654 | start_noreorder (); |
67c0d1eb | 10655 | macro_build (NULL, s, "0,x,y", xreg, yreg); |
252b5132 | 10656 | expr1.X_add_number = 2; |
67c0d1eb RS |
10657 | macro_build (&expr1, "bnez", "x,p", yreg); |
10658 | macro_build (NULL, "break", "6", 7); | |
7d10b47d | 10659 | end_noreorder (); |
67c0d1eb | 10660 | macro_build (NULL, s2, "x", zreg); |
252b5132 RH |
10661 | break; |
10662 | ||
10663 | case M_DMUL: | |
10664 | dbl = 1; | |
10665 | case M_MUL: | |
67c0d1eb RS |
10666 | macro_build (NULL, dbl ? "dmultu" : "multu", "x,y", xreg, yreg); |
10667 | macro_build (NULL, "mflo", "x", zreg); | |
8fc2e39e | 10668 | break; |
252b5132 RH |
10669 | |
10670 | case M_DSUBU_I: | |
10671 | dbl = 1; | |
10672 | goto do_subu; | |
10673 | case M_SUBU_I: | |
10674 | do_subu: | |
10675 | if (imm_expr.X_op != O_constant) | |
10676 | as_bad (_("Unsupported large constant")); | |
10677 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 10678 | macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "y,x,4", yreg, xreg); |
252b5132 RH |
10679 | break; |
10680 | ||
10681 | case M_SUBU_I_2: | |
10682 | if (imm_expr.X_op != O_constant) | |
10683 | as_bad (_("Unsupported large constant")); | |
10684 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 10685 | macro_build (&imm_expr, "addiu", "x,k", xreg); |
252b5132 RH |
10686 | break; |
10687 | ||
10688 | case M_DSUBU_I_2: | |
10689 | if (imm_expr.X_op != O_constant) | |
10690 | as_bad (_("Unsupported large constant")); | |
10691 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 10692 | macro_build (&imm_expr, "daddiu", "y,j", yreg); |
252b5132 RH |
10693 | break; |
10694 | ||
10695 | case M_BEQ: | |
10696 | s = "cmp"; | |
10697 | s2 = "bteqz"; | |
10698 | goto do_branch; | |
10699 | case M_BNE: | |
10700 | s = "cmp"; | |
10701 | s2 = "btnez"; | |
10702 | goto do_branch; | |
10703 | case M_BLT: | |
10704 | s = "slt"; | |
10705 | s2 = "btnez"; | |
10706 | goto do_branch; | |
10707 | case M_BLTU: | |
10708 | s = "sltu"; | |
10709 | s2 = "btnez"; | |
10710 | goto do_branch; | |
10711 | case M_BLE: | |
10712 | s = "slt"; | |
10713 | s2 = "bteqz"; | |
10714 | goto do_reverse_branch; | |
10715 | case M_BLEU: | |
10716 | s = "sltu"; | |
10717 | s2 = "bteqz"; | |
10718 | goto do_reverse_branch; | |
10719 | case M_BGE: | |
10720 | s = "slt"; | |
10721 | s2 = "bteqz"; | |
10722 | goto do_branch; | |
10723 | case M_BGEU: | |
10724 | s = "sltu"; | |
10725 | s2 = "bteqz"; | |
10726 | goto do_branch; | |
10727 | case M_BGT: | |
10728 | s = "slt"; | |
10729 | s2 = "btnez"; | |
10730 | goto do_reverse_branch; | |
10731 | case M_BGTU: | |
10732 | s = "sltu"; | |
10733 | s2 = "btnez"; | |
10734 | ||
10735 | do_reverse_branch: | |
10736 | tmp = xreg; | |
10737 | xreg = yreg; | |
10738 | yreg = tmp; | |
10739 | ||
10740 | do_branch: | |
67c0d1eb RS |
10741 | macro_build (NULL, s, "x,y", xreg, yreg); |
10742 | macro_build (&offset_expr, s2, "p"); | |
252b5132 RH |
10743 | break; |
10744 | ||
10745 | case M_BEQ_I: | |
10746 | s = "cmpi"; | |
10747 | s2 = "bteqz"; | |
10748 | s3 = "x,U"; | |
10749 | goto do_branch_i; | |
10750 | case M_BNE_I: | |
10751 | s = "cmpi"; | |
10752 | s2 = "btnez"; | |
10753 | s3 = "x,U"; | |
10754 | goto do_branch_i; | |
10755 | case M_BLT_I: | |
10756 | s = "slti"; | |
10757 | s2 = "btnez"; | |
10758 | s3 = "x,8"; | |
10759 | goto do_branch_i; | |
10760 | case M_BLTU_I: | |
10761 | s = "sltiu"; | |
10762 | s2 = "btnez"; | |
10763 | s3 = "x,8"; | |
10764 | goto do_branch_i; | |
10765 | case M_BLE_I: | |
10766 | s = "slti"; | |
10767 | s2 = "btnez"; | |
10768 | s3 = "x,8"; | |
10769 | goto do_addone_branch_i; | |
10770 | case M_BLEU_I: | |
10771 | s = "sltiu"; | |
10772 | s2 = "btnez"; | |
10773 | s3 = "x,8"; | |
10774 | goto do_addone_branch_i; | |
10775 | case M_BGE_I: | |
10776 | s = "slti"; | |
10777 | s2 = "bteqz"; | |
10778 | s3 = "x,8"; | |
10779 | goto do_branch_i; | |
10780 | case M_BGEU_I: | |
10781 | s = "sltiu"; | |
10782 | s2 = "bteqz"; | |
10783 | s3 = "x,8"; | |
10784 | goto do_branch_i; | |
10785 | case M_BGT_I: | |
10786 | s = "slti"; | |
10787 | s2 = "bteqz"; | |
10788 | s3 = "x,8"; | |
10789 | goto do_addone_branch_i; | |
10790 | case M_BGTU_I: | |
10791 | s = "sltiu"; | |
10792 | s2 = "bteqz"; | |
10793 | s3 = "x,8"; | |
10794 | ||
10795 | do_addone_branch_i: | |
10796 | if (imm_expr.X_op != O_constant) | |
10797 | as_bad (_("Unsupported large constant")); | |
10798 | ++imm_expr.X_add_number; | |
10799 | ||
10800 | do_branch_i: | |
67c0d1eb RS |
10801 | macro_build (&imm_expr, s, s3, xreg); |
10802 | macro_build (&offset_expr, s2, "p"); | |
252b5132 RH |
10803 | break; |
10804 | ||
10805 | case M_ABS: | |
10806 | expr1.X_add_number = 0; | |
67c0d1eb | 10807 | macro_build (&expr1, "slti", "x,8", yreg); |
252b5132 | 10808 | if (xreg != yreg) |
67c0d1eb | 10809 | move_register (xreg, yreg); |
252b5132 | 10810 | expr1.X_add_number = 2; |
67c0d1eb RS |
10811 | macro_build (&expr1, "bteqz", "p"); |
10812 | macro_build (NULL, "neg", "x,w", xreg, xreg); | |
252b5132 RH |
10813 | } |
10814 | } | |
10815 | ||
10816 | /* For consistency checking, verify that all bits are specified either | |
10817 | by the match/mask part of the instruction definition, or by the | |
10818 | operand list. */ | |
10819 | static int | |
17a2f251 | 10820 | validate_mips_insn (const struct mips_opcode *opc) |
252b5132 RH |
10821 | { |
10822 | const char *p = opc->args; | |
10823 | char c; | |
10824 | unsigned long used_bits = opc->mask; | |
10825 | ||
10826 | if ((used_bits & opc->match) != opc->match) | |
10827 | { | |
10828 | as_bad (_("internal: bad mips opcode (mask error): %s %s"), | |
10829 | opc->name, opc->args); | |
10830 | return 0; | |
10831 | } | |
10832 | #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift))) | |
10833 | while (*p) | |
10834 | switch (c = *p++) | |
10835 | { | |
10836 | case ',': break; | |
10837 | case '(': break; | |
10838 | case ')': break; | |
af7ee8bf CD |
10839 | case '+': |
10840 | switch (c = *p++) | |
10841 | { | |
9bcd4f99 TS |
10842 | case '1': USE_BITS (OP_MASK_UDI1, OP_SH_UDI1); break; |
10843 | case '2': USE_BITS (OP_MASK_UDI2, OP_SH_UDI2); break; | |
10844 | case '3': USE_BITS (OP_MASK_UDI3, OP_SH_UDI3); break; | |
10845 | case '4': USE_BITS (OP_MASK_UDI4, OP_SH_UDI4); break; | |
af7ee8bf CD |
10846 | case 'A': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
10847 | case 'B': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break; | |
10848 | case 'C': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
bbcc0807 CD |
10849 | case 'D': USE_BITS (OP_MASK_RD, OP_SH_RD); |
10850 | USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; | |
5f74bc13 CD |
10851 | case 'E': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
10852 | case 'F': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break; | |
10853 | case 'G': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
10854 | case 'H': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
10855 | case 'I': break; | |
b015e599 | 10856 | case 'J': USE_BITS (OP_MASK_CODE10, OP_SH_CODE10); break; |
ef2e4d86 CF |
10857 | case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break; |
10858 | case 'T': USE_BITS (OP_MASK_RT, OP_SH_RT); | |
10859 | USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; | |
bb35fb24 NC |
10860 | case 'x': USE_BITS (OP_MASK_BBITIND, OP_SH_BBITIND); break; |
10861 | case 'X': USE_BITS (OP_MASK_BBITIND, OP_SH_BBITIND); break; | |
10862 | case 'p': USE_BITS (OP_MASK_CINSPOS, OP_SH_CINSPOS); break; | |
10863 | case 'P': USE_BITS (OP_MASK_CINSPOS, OP_SH_CINSPOS); break; | |
dd3cbb7e | 10864 | case 'Q': USE_BITS (OP_MASK_SEQI, OP_SH_SEQI); break; |
bb35fb24 NC |
10865 | case 's': USE_BITS (OP_MASK_CINSLM1, OP_SH_CINSLM1); break; |
10866 | case 'S': USE_BITS (OP_MASK_CINSLM1, OP_SH_CINSLM1); break; | |
98675402 RS |
10867 | case 'z': USE_BITS (OP_MASK_RZ, OP_SH_RZ); break; |
10868 | case 'Z': USE_BITS (OP_MASK_FZ, OP_SH_FZ); break; | |
10869 | case 'a': USE_BITS (OP_MASK_OFFSET_A, OP_SH_OFFSET_A); break; | |
10870 | case 'b': USE_BITS (OP_MASK_OFFSET_B, OP_SH_OFFSET_B); break; | |
10871 | case 'c': USE_BITS (OP_MASK_OFFSET_C, OP_SH_OFFSET_C); break; | |
7f3c4072 | 10872 | case 'j': USE_BITS (OP_MASK_EVAOFFSET, OP_SH_EVAOFFSET); break; |
bb35fb24 | 10873 | |
af7ee8bf CD |
10874 | default: |
10875 | as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"), | |
10876 | c, opc->name, opc->args); | |
10877 | return 0; | |
10878 | } | |
10879 | break; | |
252b5132 RH |
10880 | case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
10881 | case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; | |
10882 | case 'A': break; | |
4372b673 | 10883 | case 'B': USE_BITS (OP_MASK_CODE20, OP_SH_CODE20); break; |
252b5132 RH |
10884 | case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break; |
10885 | case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break; | |
10886 | case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
10887 | case 'F': break; | |
10888 | case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
156c2f8b | 10889 | case 'H': USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; |
252b5132 | 10890 | case 'I': break; |
e972090a | 10891 | case 'J': USE_BITS (OP_MASK_CODE19, OP_SH_CODE19); break; |
af7ee8bf | 10892 | case 'K': USE_BITS (OP_MASK_RD, OP_SH_RD); break; |
252b5132 RH |
10893 | case 'L': break; |
10894 | case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break; | |
10895 | case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break; | |
deec1734 CD |
10896 | case 'O': USE_BITS (OP_MASK_ALN, OP_SH_ALN); break; |
10897 | case 'Q': USE_BITS (OP_MASK_VSEL, OP_SH_VSEL); | |
10898 | USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
252b5132 RH |
10899 | case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break; |
10900 | case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
10901 | case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
10902 | case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
10903 | case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
deec1734 CD |
10904 | case 'X': USE_BITS (OP_MASK_FD, OP_SH_FD); break; |
10905 | case 'Y': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
10906 | case 'Z': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
252b5132 RH |
10907 | case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break; |
10908 | case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
10909 | case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break; | |
10910 | case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
10911 | case 'f': break; | |
10912 | case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break; | |
10913 | case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; | |
10914 | case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
10915 | case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break; | |
10916 | case 'l': break; | |
10917 | case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
10918 | case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
10919 | case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break; | |
10920 | case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
10921 | case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
10922 | case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
10923 | case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; | |
10924 | case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
10925 | case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
10926 | case 'x': break; | |
10927 | case 'z': break; | |
10928 | case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break; | |
4372b673 NC |
10929 | case 'U': USE_BITS (OP_MASK_RD, OP_SH_RD); |
10930 | USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
60b63b72 RS |
10931 | case 'e': USE_BITS (OP_MASK_VECBYTE, OP_SH_VECBYTE); break; |
10932 | case '%': USE_BITS (OP_MASK_VECALIGN, OP_SH_VECALIGN); break; | |
10933 | case '[': break; | |
10934 | case ']': break; | |
620edafd | 10935 | case '1': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
8b082fb1 | 10936 | case '2': USE_BITS (OP_MASK_BP, OP_SH_BP); break; |
74cd071d CF |
10937 | case '3': USE_BITS (OP_MASK_SA3, OP_SH_SA3); break; |
10938 | case '4': USE_BITS (OP_MASK_SA4, OP_SH_SA4); break; | |
10939 | case '5': USE_BITS (OP_MASK_IMM8, OP_SH_IMM8); break; | |
10940 | case '6': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
10941 | case '7': USE_BITS (OP_MASK_DSPACC, OP_SH_DSPACC); break; | |
10942 | case '8': USE_BITS (OP_MASK_WRDSP, OP_SH_WRDSP); break; | |
10943 | case '9': USE_BITS (OP_MASK_DSPACC_S, OP_SH_DSPACC_S);break; | |
10944 | case '0': USE_BITS (OP_MASK_DSPSFT, OP_SH_DSPSFT); break; | |
10945 | case '\'': USE_BITS (OP_MASK_RDDSP, OP_SH_RDDSP); break; | |
10946 | case ':': USE_BITS (OP_MASK_DSPSFT_7, OP_SH_DSPSFT_7);break; | |
10947 | case '@': USE_BITS (OP_MASK_IMM10, OP_SH_IMM10); break; | |
ef2e4d86 CF |
10948 | case '!': USE_BITS (OP_MASK_MT_U, OP_SH_MT_U); break; |
10949 | case '$': USE_BITS (OP_MASK_MT_H, OP_SH_MT_H); break; | |
10950 | case '*': USE_BITS (OP_MASK_MTACC_T, OP_SH_MTACC_T); break; | |
10951 | case '&': USE_BITS (OP_MASK_MTACC_D, OP_SH_MTACC_D); break; | |
dec0624d MR |
10952 | case '\\': USE_BITS (OP_MASK_3BITPOS, OP_SH_3BITPOS); break; |
10953 | case '~': USE_BITS (OP_MASK_OFFSET12, OP_SH_OFFSET12); break; | |
ef2e4d86 | 10954 | case 'g': USE_BITS (OP_MASK_RD, OP_SH_RD); break; |
252b5132 RH |
10955 | default: |
10956 | as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"), | |
10957 | c, opc->name, opc->args); | |
10958 | return 0; | |
10959 | } | |
10960 | #undef USE_BITS | |
10961 | if (used_bits != 0xffffffff) | |
10962 | { | |
10963 | as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"), | |
10964 | ~used_bits & 0xffffffff, opc->name, opc->args); | |
10965 | return 0; | |
10966 | } | |
10967 | return 1; | |
10968 | } | |
10969 | ||
df58fc94 RS |
10970 | /* For consistency checking, verify that the length implied matches the |
10971 | major opcode and that all bits are specified either by the match/mask | |
10972 | part of the instruction definition, or by the operand list. */ | |
10973 | ||
10974 | static int | |
10975 | validate_micromips_insn (const struct mips_opcode *opc) | |
10976 | { | |
10977 | unsigned long match = opc->match; | |
10978 | unsigned long mask = opc->mask; | |
10979 | const char *p = opc->args; | |
10980 | unsigned long insn_bits; | |
10981 | unsigned long used_bits; | |
10982 | unsigned long major; | |
10983 | unsigned int length; | |
10984 | char e; | |
10985 | char c; | |
10986 | ||
10987 | if ((mask & match) != match) | |
10988 | { | |
10989 | as_bad (_("Internal error: bad microMIPS opcode (mask error): %s %s"), | |
10990 | opc->name, opc->args); | |
10991 | return 0; | |
10992 | } | |
10993 | length = micromips_insn_length (opc); | |
10994 | if (length != 2 && length != 4) | |
10995 | { | |
10996 | as_bad (_("Internal error: bad microMIPS opcode (incorrect length: %u): " | |
10997 | "%s %s"), length, opc->name, opc->args); | |
10998 | return 0; | |
10999 | } | |
11000 | major = match >> (10 + 8 * (length - 2)); | |
11001 | if ((length == 2 && (major & 7) != 1 && (major & 6) != 2) | |
11002 | || (length == 4 && (major & 7) != 0 && (major & 4) != 4)) | |
11003 | { | |
11004 | as_bad (_("Internal error: bad microMIPS opcode " | |
11005 | "(opcode/length mismatch): %s %s"), opc->name, opc->args); | |
11006 | return 0; | |
11007 | } | |
11008 | ||
11009 | /* Shift piecewise to avoid an overflow where unsigned long is 32-bit. */ | |
11010 | insn_bits = 1 << 4 * length; | |
11011 | insn_bits <<= 4 * length; | |
11012 | insn_bits -= 1; | |
11013 | used_bits = mask; | |
11014 | #define USE_BITS(field) \ | |
11015 | (used_bits |= MICROMIPSOP_MASK_##field << MICROMIPSOP_SH_##field) | |
11016 | while (*p) | |
11017 | switch (c = *p++) | |
11018 | { | |
11019 | case ',': break; | |
11020 | case '(': break; | |
11021 | case ')': break; | |
11022 | case '+': | |
11023 | e = c; | |
11024 | switch (c = *p++) | |
11025 | { | |
11026 | case 'A': USE_BITS (EXTLSB); break; | |
11027 | case 'B': USE_BITS (INSMSB); break; | |
11028 | case 'C': USE_BITS (EXTMSBD); break; | |
11029 | case 'D': USE_BITS (RS); USE_BITS (SEL); break; | |
11030 | case 'E': USE_BITS (EXTLSB); break; | |
11031 | case 'F': USE_BITS (INSMSB); break; | |
11032 | case 'G': USE_BITS (EXTMSBD); break; | |
11033 | case 'H': USE_BITS (EXTMSBD); break; | |
7f3c4072 | 11034 | case 'j': USE_BITS (EVAOFFSET); break; |
df58fc94 RS |
11035 | default: |
11036 | as_bad (_("Internal error: bad mips opcode " | |
11037 | "(unknown extension operand type `%c%c'): %s %s"), | |
11038 | e, c, opc->name, opc->args); | |
11039 | return 0; | |
11040 | } | |
11041 | break; | |
11042 | case 'm': | |
11043 | e = c; | |
11044 | switch (c = *p++) | |
11045 | { | |
11046 | case 'A': USE_BITS (IMMA); break; | |
11047 | case 'B': USE_BITS (IMMB); break; | |
11048 | case 'C': USE_BITS (IMMC); break; | |
11049 | case 'D': USE_BITS (IMMD); break; | |
11050 | case 'E': USE_BITS (IMME); break; | |
11051 | case 'F': USE_BITS (IMMF); break; | |
11052 | case 'G': USE_BITS (IMMG); break; | |
11053 | case 'H': USE_BITS (IMMH); break; | |
11054 | case 'I': USE_BITS (IMMI); break; | |
11055 | case 'J': USE_BITS (IMMJ); break; | |
11056 | case 'L': USE_BITS (IMML); break; | |
11057 | case 'M': USE_BITS (IMMM); break; | |
11058 | case 'N': USE_BITS (IMMN); break; | |
11059 | case 'O': USE_BITS (IMMO); break; | |
11060 | case 'P': USE_BITS (IMMP); break; | |
11061 | case 'Q': USE_BITS (IMMQ); break; | |
11062 | case 'U': USE_BITS (IMMU); break; | |
11063 | case 'W': USE_BITS (IMMW); break; | |
11064 | case 'X': USE_BITS (IMMX); break; | |
11065 | case 'Y': USE_BITS (IMMY); break; | |
11066 | case 'Z': break; | |
11067 | case 'a': break; | |
11068 | case 'b': USE_BITS (MB); break; | |
11069 | case 'c': USE_BITS (MC); break; | |
11070 | case 'd': USE_BITS (MD); break; | |
11071 | case 'e': USE_BITS (ME); break; | |
11072 | case 'f': USE_BITS (MF); break; | |
11073 | case 'g': USE_BITS (MG); break; | |
11074 | case 'h': USE_BITS (MH); break; | |
11075 | case 'i': USE_BITS (MI); break; | |
11076 | case 'j': USE_BITS (MJ); break; | |
11077 | case 'l': USE_BITS (ML); break; | |
11078 | case 'm': USE_BITS (MM); break; | |
11079 | case 'n': USE_BITS (MN); break; | |
11080 | case 'p': USE_BITS (MP); break; | |
11081 | case 'q': USE_BITS (MQ); break; | |
11082 | case 'r': break; | |
11083 | case 's': break; | |
11084 | case 't': break; | |
11085 | case 'x': break; | |
11086 | case 'y': break; | |
11087 | case 'z': break; | |
11088 | default: | |
11089 | as_bad (_("Internal error: bad mips opcode " | |
11090 | "(unknown extension operand type `%c%c'): %s %s"), | |
11091 | e, c, opc->name, opc->args); | |
11092 | return 0; | |
11093 | } | |
11094 | break; | |
11095 | case '.': USE_BITS (OFFSET10); break; | |
11096 | case '1': USE_BITS (STYPE); break; | |
03f66e8a MR |
11097 | case '2': USE_BITS (BP); break; |
11098 | case '3': USE_BITS (SA3); break; | |
11099 | case '4': USE_BITS (SA4); break; | |
11100 | case '5': USE_BITS (IMM8); break; | |
11101 | case '6': USE_BITS (RS); break; | |
11102 | case '7': USE_BITS (DSPACC); break; | |
11103 | case '8': USE_BITS (WRDSP); break; | |
11104 | case '0': USE_BITS (DSPSFT); break; | |
df58fc94 RS |
11105 | case '<': USE_BITS (SHAMT); break; |
11106 | case '>': USE_BITS (SHAMT); break; | |
03f66e8a | 11107 | case '@': USE_BITS (IMM10); break; |
df58fc94 RS |
11108 | case 'B': USE_BITS (CODE10); break; |
11109 | case 'C': USE_BITS (COPZ); break; | |
11110 | case 'D': USE_BITS (FD); break; | |
11111 | case 'E': USE_BITS (RT); break; | |
11112 | case 'G': USE_BITS (RS); break; | |
444d75be | 11113 | case 'H': USE_BITS (SEL); break; |
df58fc94 RS |
11114 | case 'K': USE_BITS (RS); break; |
11115 | case 'M': USE_BITS (CCC); break; | |
11116 | case 'N': USE_BITS (BCC); break; | |
11117 | case 'R': USE_BITS (FR); break; | |
11118 | case 'S': USE_BITS (FS); break; | |
11119 | case 'T': USE_BITS (FT); break; | |
11120 | case 'V': USE_BITS (FS); break; | |
dec0624d | 11121 | case '\\': USE_BITS (3BITPOS); break; |
03f66e8a | 11122 | case '^': USE_BITS (RD); break; |
df58fc94 RS |
11123 | case 'a': USE_BITS (TARGET); break; |
11124 | case 'b': USE_BITS (RS); break; | |
11125 | case 'c': USE_BITS (CODE); break; | |
11126 | case 'd': USE_BITS (RD); break; | |
11127 | case 'h': USE_BITS (PREFX); break; | |
11128 | case 'i': USE_BITS (IMMEDIATE); break; | |
11129 | case 'j': USE_BITS (DELTA); break; | |
11130 | case 'k': USE_BITS (CACHE); break; | |
11131 | case 'n': USE_BITS (RT); break; | |
11132 | case 'o': USE_BITS (DELTA); break; | |
11133 | case 'p': USE_BITS (DELTA); break; | |
11134 | case 'q': USE_BITS (CODE2); break; | |
11135 | case 'r': USE_BITS (RS); break; | |
11136 | case 's': USE_BITS (RS); break; | |
11137 | case 't': USE_BITS (RT); break; | |
11138 | case 'u': USE_BITS (IMMEDIATE); break; | |
11139 | case 'v': USE_BITS (RS); break; | |
11140 | case 'w': USE_BITS (RT); break; | |
11141 | case 'y': USE_BITS (RS3); break; | |
11142 | case 'z': break; | |
11143 | case '|': USE_BITS (TRAP); break; | |
11144 | case '~': USE_BITS (OFFSET12); break; | |
11145 | default: | |
11146 | as_bad (_("Internal error: bad microMIPS opcode " | |
11147 | "(unknown operand type `%c'): %s %s"), | |
11148 | c, opc->name, opc->args); | |
11149 | return 0; | |
11150 | } | |
11151 | #undef USE_BITS | |
11152 | if (used_bits != insn_bits) | |
11153 | { | |
11154 | if (~used_bits & insn_bits) | |
11155 | as_bad (_("Internal error: bad microMIPS opcode " | |
11156 | "(bits 0x%lx undefined): %s %s"), | |
11157 | ~used_bits & insn_bits, opc->name, opc->args); | |
11158 | if (used_bits & ~insn_bits) | |
11159 | as_bad (_("Internal error: bad microMIPS opcode " | |
11160 | "(bits 0x%lx defined): %s %s"), | |
11161 | used_bits & ~insn_bits, opc->name, opc->args); | |
11162 | return 0; | |
11163 | } | |
11164 | return 1; | |
11165 | } | |
11166 | ||
9bcd4f99 TS |
11167 | /* UDI immediates. */ |
11168 | struct mips_immed { | |
11169 | char type; | |
11170 | unsigned int shift; | |
11171 | unsigned long mask; | |
11172 | const char * desc; | |
11173 | }; | |
11174 | ||
11175 | static const struct mips_immed mips_immed[] = { | |
11176 | { '1', OP_SH_UDI1, OP_MASK_UDI1, 0}, | |
11177 | { '2', OP_SH_UDI2, OP_MASK_UDI2, 0}, | |
11178 | { '3', OP_SH_UDI3, OP_MASK_UDI3, 0}, | |
11179 | { '4', OP_SH_UDI4, OP_MASK_UDI4, 0}, | |
11180 | { 0,0,0,0 } | |
11181 | }; | |
11182 | ||
7455baf8 TS |
11183 | /* Check whether an odd floating-point register is allowed. */ |
11184 | static int | |
11185 | mips_oddfpreg_ok (const struct mips_opcode *insn, int argnum) | |
11186 | { | |
11187 | const char *s = insn->name; | |
11188 | ||
11189 | if (insn->pinfo == INSN_MACRO) | |
11190 | /* Let a macro pass, we'll catch it later when it is expanded. */ | |
11191 | return 1; | |
11192 | ||
e407c74b | 11193 | if (ISA_HAS_ODD_SINGLE_FPR (mips_opts.isa) || (mips_opts.arch == CPU_R5900)) |
7455baf8 TS |
11194 | { |
11195 | /* Allow odd registers for single-precision ops. */ | |
11196 | switch (insn->pinfo & (FP_S | FP_D)) | |
11197 | { | |
11198 | case FP_S: | |
11199 | case 0: | |
11200 | return 1; /* both single precision - ok */ | |
11201 | case FP_D: | |
11202 | return 0; /* both double precision - fail */ | |
11203 | default: | |
11204 | break; | |
11205 | } | |
11206 | ||
11207 | /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */ | |
11208 | s = strchr (insn->name, '.'); | |
11209 | if (argnum == 2) | |
11210 | s = s != NULL ? strchr (s + 1, '.') : NULL; | |
11211 | return (s != NULL && (s[1] == 'w' || s[1] == 's')); | |
11212 | } | |
11213 | ||
11214 | /* Single-precision coprocessor loads and moves are OK too. */ | |
11215 | if ((insn->pinfo & FP_S) | |
11216 | && (insn->pinfo & (INSN_COPROC_MEMORY_DELAY | INSN_STORE_MEMORY | |
11217 | | INSN_LOAD_COPROC_DELAY | INSN_COPROC_MOVE_DELAY))) | |
11218 | return 1; | |
11219 | ||
11220 | return 0; | |
11221 | } | |
11222 | ||
df58fc94 RS |
11223 | /* Check if EXPR is a constant between MIN (inclusive) and MAX (exclusive) |
11224 | taking bits from BIT up. */ | |
11225 | static int | |
11226 | expr_const_in_range (expressionS *ep, offsetT min, offsetT max, int bit) | |
11227 | { | |
11228 | return (ep->X_op == O_constant | |
11229 | && (ep->X_add_number & ((1 << bit) - 1)) == 0 | |
11230 | && ep->X_add_number >= min << bit | |
11231 | && ep->X_add_number < max << bit); | |
11232 | } | |
11233 | ||
252b5132 RH |
11234 | /* This routine assembles an instruction into its binary format. As a |
11235 | side effect, it sets one of the global variables imm_reloc or | |
11236 | offset_reloc to the type of relocation to do if one of the operands | |
11237 | is an address expression. */ | |
11238 | ||
11239 | static void | |
17a2f251 | 11240 | mips_ip (char *str, struct mips_cl_insn *ip) |
252b5132 | 11241 | { |
df58fc94 RS |
11242 | bfd_boolean wrong_delay_slot_insns = FALSE; |
11243 | bfd_boolean need_delay_slot_ok = TRUE; | |
11244 | struct mips_opcode *firstinsn = NULL; | |
11245 | const struct mips_opcode *past; | |
11246 | struct hash_control *hash; | |
252b5132 RH |
11247 | char *s; |
11248 | const char *args; | |
43841e91 | 11249 | char c = 0; |
252b5132 RH |
11250 | struct mips_opcode *insn; |
11251 | char *argsStart; | |
11252 | unsigned int regno; | |
34224acf | 11253 | unsigned int lastregno; |
df58fc94 | 11254 | unsigned int destregno = 0; |
af7ee8bf | 11255 | unsigned int lastpos = 0; |
071742cf | 11256 | unsigned int limlo, limhi; |
f02d8318 | 11257 | int sizelo; |
252b5132 | 11258 | char *s_reset; |
74cd071d | 11259 | offsetT min_range, max_range; |
df58fc94 | 11260 | long opend; |
a40bc9dd | 11261 | char *name; |
707bfff6 TS |
11262 | int argnum; |
11263 | unsigned int rtype; | |
df58fc94 | 11264 | char *dot; |
a40bc9dd | 11265 | long end; |
252b5132 RH |
11266 | |
11267 | insn_error = NULL; | |
11268 | ||
df58fc94 RS |
11269 | if (mips_opts.micromips) |
11270 | { | |
11271 | hash = micromips_op_hash; | |
11272 | past = µmips_opcodes[bfd_micromips_num_opcodes]; | |
11273 | } | |
11274 | else | |
11275 | { | |
11276 | hash = op_hash; | |
11277 | past = &mips_opcodes[NUMOPCODES]; | |
11278 | } | |
11279 | forced_insn_length = 0; | |
252b5132 | 11280 | insn = NULL; |
252b5132 | 11281 | |
df58fc94 | 11282 | /* We first try to match an instruction up to a space or to the end. */ |
a40bc9dd RS |
11283 | for (end = 0; str[end] != '\0' && !ISSPACE (str[end]); end++) |
11284 | continue; | |
bdaaa2e1 | 11285 | |
a40bc9dd RS |
11286 | /* Make a copy of the instruction so that we can fiddle with it. */ |
11287 | name = alloca (end + 1); | |
11288 | memcpy (name, str, end); | |
11289 | name[end] = '\0'; | |
252b5132 | 11290 | |
df58fc94 RS |
11291 | for (;;) |
11292 | { | |
11293 | insn = (struct mips_opcode *) hash_find (hash, name); | |
11294 | ||
11295 | if (insn != NULL || !mips_opts.micromips) | |
11296 | break; | |
11297 | if (forced_insn_length) | |
11298 | break; | |
11299 | ||
11300 | /* See if there's an instruction size override suffix, | |
11301 | either `16' or `32', at the end of the mnemonic proper, | |
11302 | that defines the operation, i.e. before the first `.' | |
11303 | character if any. Strip it and retry. */ | |
11304 | dot = strchr (name, '.'); | |
11305 | opend = dot != NULL ? dot - name : end; | |
11306 | if (opend < 3) | |
11307 | break; | |
11308 | if (name[opend - 2] == '1' && name[opend - 1] == '6') | |
11309 | forced_insn_length = 2; | |
11310 | else if (name[opend - 2] == '3' && name[opend - 1] == '2') | |
11311 | forced_insn_length = 4; | |
11312 | else | |
11313 | break; | |
11314 | memcpy (name + opend - 2, name + opend, end - opend + 1); | |
11315 | } | |
252b5132 RH |
11316 | if (insn == NULL) |
11317 | { | |
a40bc9dd RS |
11318 | insn_error = _("Unrecognized opcode"); |
11319 | return; | |
252b5132 RH |
11320 | } |
11321 | ||
df58fc94 RS |
11322 | /* For microMIPS instructions placed in a fixed-length branch delay slot |
11323 | we make up to two passes over the relevant fragment of the opcode | |
11324 | table. First we try instructions that meet the delay slot's length | |
11325 | requirement. If none matched, then we retry with the remaining ones | |
11326 | and if one matches, then we use it and then issue an appropriate | |
11327 | warning later on. */ | |
a40bc9dd | 11328 | argsStart = s = str + end; |
252b5132 RH |
11329 | for (;;) |
11330 | { | |
df58fc94 RS |
11331 | bfd_boolean delay_slot_ok; |
11332 | bfd_boolean size_ok; | |
b34976b6 | 11333 | bfd_boolean ok; |
252b5132 | 11334 | |
a40bc9dd | 11335 | gas_assert (strcmp (insn->name, name) == 0); |
252b5132 | 11336 | |
f79e2745 | 11337 | ok = is_opcode_valid (insn); |
df58fc94 RS |
11338 | size_ok = is_size_valid (insn); |
11339 | delay_slot_ok = is_delay_slot_valid (insn); | |
11340 | if (!delay_slot_ok && !wrong_delay_slot_insns) | |
252b5132 | 11341 | { |
df58fc94 RS |
11342 | firstinsn = insn; |
11343 | wrong_delay_slot_insns = TRUE; | |
11344 | } | |
11345 | if (!ok || !size_ok || delay_slot_ok != need_delay_slot_ok) | |
11346 | { | |
11347 | static char buf[256]; | |
11348 | ||
11349 | if (insn + 1 < past && strcmp (insn->name, insn[1].name) == 0) | |
252b5132 RH |
11350 | { |
11351 | ++insn; | |
11352 | continue; | |
11353 | } | |
df58fc94 | 11354 | if (wrong_delay_slot_insns && need_delay_slot_ok) |
beae10d5 | 11355 | { |
df58fc94 RS |
11356 | gas_assert (firstinsn); |
11357 | need_delay_slot_ok = FALSE; | |
11358 | past = insn + 1; | |
11359 | insn = firstinsn; | |
11360 | continue; | |
252b5132 | 11361 | } |
df58fc94 RS |
11362 | |
11363 | if (insn_error) | |
11364 | return; | |
11365 | ||
11366 | if (!ok) | |
7bd942df | 11367 | sprintf (buf, _("Opcode not supported on this processor: %s (%s)"), |
df58fc94 RS |
11368 | mips_cpu_info_from_arch (mips_opts.arch)->name, |
11369 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
11370 | else | |
11371 | sprintf (buf, _("Unrecognized %u-bit version of microMIPS opcode"), | |
11372 | 8 * forced_insn_length); | |
11373 | insn_error = buf; | |
11374 | ||
11375 | return; | |
252b5132 RH |
11376 | } |
11377 | ||
1e915849 | 11378 | create_insn (ip, insn); |
268f6bed | 11379 | insn_error = NULL; |
707bfff6 | 11380 | argnum = 1; |
24864476 | 11381 | lastregno = 0xffffffff; |
252b5132 RH |
11382 | for (args = insn->args;; ++args) |
11383 | { | |
deec1734 CD |
11384 | int is_mdmx; |
11385 | ||
ad8d3bb3 | 11386 | s += strspn (s, " \t"); |
deec1734 | 11387 | is_mdmx = 0; |
252b5132 RH |
11388 | switch (*args) |
11389 | { | |
11390 | case '\0': /* end of args */ | |
11391 | if (*s == '\0') | |
11392 | return; | |
11393 | break; | |
11394 | ||
03f66e8a MR |
11395 | case '2': |
11396 | /* DSP 2-bit unsigned immediate in bit 11 (for standard MIPS | |
11397 | code) or 14 (for microMIPS code). */ | |
8b082fb1 TS |
11398 | my_getExpression (&imm_expr, s); |
11399 | check_absolute_expr (ip, &imm_expr); | |
11400 | if ((unsigned long) imm_expr.X_add_number != 1 | |
11401 | && (unsigned long) imm_expr.X_add_number != 3) | |
11402 | { | |
11403 | as_bad (_("BALIGN immediate not 1 or 3 (%lu)"), | |
11404 | (unsigned long) imm_expr.X_add_number); | |
11405 | } | |
03f66e8a MR |
11406 | INSERT_OPERAND (mips_opts.micromips, |
11407 | BP, *ip, imm_expr.X_add_number); | |
8b082fb1 TS |
11408 | imm_expr.X_op = O_absent; |
11409 | s = expr_end; | |
11410 | continue; | |
11411 | ||
03f66e8a MR |
11412 | case '3': |
11413 | /* DSP 3-bit unsigned immediate in bit 13 (for standard MIPS | |
11414 | code) or 21 (for microMIPS code). */ | |
11415 | { | |
11416 | unsigned long mask = (mips_opts.micromips | |
11417 | ? MICROMIPSOP_MASK_SA3 : OP_MASK_SA3); | |
11418 | ||
11419 | my_getExpression (&imm_expr, s); | |
11420 | check_absolute_expr (ip, &imm_expr); | |
11421 | if ((unsigned long) imm_expr.X_add_number > mask) | |
11422 | as_bad (_("DSP immediate not in range 0..%lu (%lu)"), | |
11423 | mask, (unsigned long) imm_expr.X_add_number); | |
11424 | INSERT_OPERAND (mips_opts.micromips, | |
11425 | SA3, *ip, imm_expr.X_add_number); | |
11426 | imm_expr.X_op = O_absent; | |
11427 | s = expr_end; | |
11428 | } | |
74cd071d CF |
11429 | continue; |
11430 | ||
03f66e8a MR |
11431 | case '4': |
11432 | /* DSP 4-bit unsigned immediate in bit 12 (for standard MIPS | |
11433 | code) or 21 (for microMIPS code). */ | |
11434 | { | |
11435 | unsigned long mask = (mips_opts.micromips | |
11436 | ? MICROMIPSOP_MASK_SA4 : OP_MASK_SA4); | |
11437 | ||
11438 | my_getExpression (&imm_expr, s); | |
11439 | check_absolute_expr (ip, &imm_expr); | |
11440 | if ((unsigned long) imm_expr.X_add_number > mask) | |
11441 | as_bad (_("DSP immediate not in range 0..%lu (%lu)"), | |
11442 | mask, (unsigned long) imm_expr.X_add_number); | |
11443 | INSERT_OPERAND (mips_opts.micromips, | |
11444 | SA4, *ip, imm_expr.X_add_number); | |
11445 | imm_expr.X_op = O_absent; | |
11446 | s = expr_end; | |
11447 | } | |
74cd071d CF |
11448 | continue; |
11449 | ||
03f66e8a MR |
11450 | case '5': |
11451 | /* DSP 8-bit unsigned immediate in bit 13 (for standard MIPS | |
11452 | code) or 16 (for microMIPS code). */ | |
11453 | { | |
11454 | unsigned long mask = (mips_opts.micromips | |
11455 | ? MICROMIPSOP_MASK_IMM8 : OP_MASK_IMM8); | |
11456 | ||
11457 | my_getExpression (&imm_expr, s); | |
11458 | check_absolute_expr (ip, &imm_expr); | |
11459 | if ((unsigned long) imm_expr.X_add_number > mask) | |
11460 | as_bad (_("DSP immediate not in range 0..%lu (%lu)"), | |
11461 | mask, (unsigned long) imm_expr.X_add_number); | |
11462 | INSERT_OPERAND (mips_opts.micromips, | |
11463 | IMM8, *ip, imm_expr.X_add_number); | |
11464 | imm_expr.X_op = O_absent; | |
11465 | s = expr_end; | |
11466 | } | |
74cd071d CF |
11467 | continue; |
11468 | ||
03f66e8a MR |
11469 | case '6': |
11470 | /* DSP 5-bit unsigned immediate in bit 16 (for standard MIPS | |
11471 | code) or 21 (for microMIPS code). */ | |
11472 | { | |
11473 | unsigned long mask = (mips_opts.micromips | |
11474 | ? MICROMIPSOP_MASK_RS : OP_MASK_RS); | |
11475 | ||
11476 | my_getExpression (&imm_expr, s); | |
11477 | check_absolute_expr (ip, &imm_expr); | |
11478 | if ((unsigned long) imm_expr.X_add_number > mask) | |
11479 | as_bad (_("DSP immediate not in range 0..%lu (%lu)"), | |
11480 | mask, (unsigned long) imm_expr.X_add_number); | |
11481 | INSERT_OPERAND (mips_opts.micromips, | |
11482 | RS, *ip, imm_expr.X_add_number); | |
11483 | imm_expr.X_op = O_absent; | |
11484 | s = expr_end; | |
11485 | } | |
74cd071d CF |
11486 | continue; |
11487 | ||
90ecf173 | 11488 | case '7': /* Four DSP accumulators in bits 11,12. */ |
03f66e8a MR |
11489 | if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' |
11490 | && s[3] >= '0' && s[3] <= '3') | |
74cd071d CF |
11491 | { |
11492 | regno = s[3] - '0'; | |
11493 | s += 4; | |
03f66e8a | 11494 | INSERT_OPERAND (mips_opts.micromips, DSPACC, *ip, regno); |
74cd071d CF |
11495 | continue; |
11496 | } | |
11497 | else | |
11498 | as_bad (_("Invalid dsp acc register")); | |
11499 | break; | |
11500 | ||
03f66e8a MR |
11501 | case '8': |
11502 | /* DSP 6-bit unsigned immediate in bit 11 (for standard MIPS | |
11503 | code) or 14 (for microMIPS code). */ | |
11504 | { | |
11505 | unsigned long mask = (mips_opts.micromips | |
11506 | ? MICROMIPSOP_MASK_WRDSP | |
11507 | : OP_MASK_WRDSP); | |
11508 | ||
11509 | my_getExpression (&imm_expr, s); | |
11510 | check_absolute_expr (ip, &imm_expr); | |
11511 | if ((unsigned long) imm_expr.X_add_number > mask) | |
11512 | as_bad (_("DSP immediate not in range 0..%lu (%lu)"), | |
11513 | mask, (unsigned long) imm_expr.X_add_number); | |
11514 | INSERT_OPERAND (mips_opts.micromips, | |
11515 | WRDSP, *ip, imm_expr.X_add_number); | |
11516 | imm_expr.X_op = O_absent; | |
11517 | s = expr_end; | |
11518 | } | |
74cd071d CF |
11519 | continue; |
11520 | ||
90ecf173 | 11521 | case '9': /* Four DSP accumulators in bits 21,22. */ |
df58fc94 | 11522 | gas_assert (!mips_opts.micromips); |
03f66e8a MR |
11523 | if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' |
11524 | && s[3] >= '0' && s[3] <= '3') | |
74cd071d CF |
11525 | { |
11526 | regno = s[3] - '0'; | |
11527 | s += 4; | |
df58fc94 | 11528 | INSERT_OPERAND (0, DSPACC_S, *ip, regno); |
74cd071d CF |
11529 | continue; |
11530 | } | |
11531 | else | |
11532 | as_bad (_("Invalid dsp acc register")); | |
11533 | break; | |
11534 | ||
03f66e8a MR |
11535 | case '0': |
11536 | /* DSP 6-bit signed immediate in bit 16 (for standard MIPS | |
11537 | code) or 20 (for microMIPS code). */ | |
11538 | { | |
11539 | long mask = (mips_opts.micromips | |
11540 | ? MICROMIPSOP_MASK_DSPSFT : OP_MASK_DSPSFT); | |
11541 | ||
11542 | my_getExpression (&imm_expr, s); | |
11543 | check_absolute_expr (ip, &imm_expr); | |
11544 | min_range = -((mask + 1) >> 1); | |
11545 | max_range = ((mask + 1) >> 1) - 1; | |
11546 | if (imm_expr.X_add_number < min_range | |
11547 | || imm_expr.X_add_number > max_range) | |
a9e24354 TS |
11548 | as_bad (_("DSP immediate not in range %ld..%ld (%ld)"), |
11549 | (long) min_range, (long) max_range, | |
11550 | (long) imm_expr.X_add_number); | |
03f66e8a MR |
11551 | INSERT_OPERAND (mips_opts.micromips, |
11552 | DSPSFT, *ip, imm_expr.X_add_number); | |
11553 | imm_expr.X_op = O_absent; | |
11554 | s = expr_end; | |
11555 | } | |
74cd071d CF |
11556 | continue; |
11557 | ||
90ecf173 | 11558 | case '\'': /* DSP 6-bit unsigned immediate in bit 16. */ |
df58fc94 | 11559 | gas_assert (!mips_opts.micromips); |
74cd071d CF |
11560 | my_getExpression (&imm_expr, s); |
11561 | check_absolute_expr (ip, &imm_expr); | |
11562 | if (imm_expr.X_add_number & ~OP_MASK_RDDSP) | |
11563 | { | |
a9e24354 TS |
11564 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), |
11565 | OP_MASK_RDDSP, | |
11566 | (unsigned long) imm_expr.X_add_number); | |
74cd071d | 11567 | } |
df58fc94 | 11568 | INSERT_OPERAND (0, RDDSP, *ip, imm_expr.X_add_number); |
74cd071d CF |
11569 | imm_expr.X_op = O_absent; |
11570 | s = expr_end; | |
11571 | continue; | |
11572 | ||
90ecf173 | 11573 | case ':': /* DSP 7-bit signed immediate in bit 19. */ |
df58fc94 | 11574 | gas_assert (!mips_opts.micromips); |
74cd071d CF |
11575 | my_getExpression (&imm_expr, s); |
11576 | check_absolute_expr (ip, &imm_expr); | |
11577 | min_range = -((OP_MASK_DSPSFT_7 + 1) >> 1); | |
11578 | max_range = ((OP_MASK_DSPSFT_7 + 1) >> 1) - 1; | |
11579 | if (imm_expr.X_add_number < min_range || | |
11580 | imm_expr.X_add_number > max_range) | |
11581 | { | |
a9e24354 TS |
11582 | as_bad (_("DSP immediate not in range %ld..%ld (%ld)"), |
11583 | (long) min_range, (long) max_range, | |
11584 | (long) imm_expr.X_add_number); | |
74cd071d | 11585 | } |
df58fc94 | 11586 | INSERT_OPERAND (0, DSPSFT_7, *ip, imm_expr.X_add_number); |
74cd071d CF |
11587 | imm_expr.X_op = O_absent; |
11588 | s = expr_end; | |
11589 | continue; | |
11590 | ||
90ecf173 | 11591 | case '@': /* DSP 10-bit signed immediate in bit 16. */ |
03f66e8a MR |
11592 | { |
11593 | long mask = (mips_opts.micromips | |
11594 | ? MICROMIPSOP_MASK_IMM10 : OP_MASK_IMM10); | |
11595 | ||
11596 | my_getExpression (&imm_expr, s); | |
11597 | check_absolute_expr (ip, &imm_expr); | |
11598 | min_range = -((mask + 1) >> 1); | |
11599 | max_range = ((mask + 1) >> 1) - 1; | |
11600 | if (imm_expr.X_add_number < min_range | |
11601 | || imm_expr.X_add_number > max_range) | |
a9e24354 TS |
11602 | as_bad (_("DSP immediate not in range %ld..%ld (%ld)"), |
11603 | (long) min_range, (long) max_range, | |
11604 | (long) imm_expr.X_add_number); | |
03f66e8a MR |
11605 | INSERT_OPERAND (mips_opts.micromips, |
11606 | IMM10, *ip, imm_expr.X_add_number); | |
11607 | imm_expr.X_op = O_absent; | |
11608 | s = expr_end; | |
11609 | } | |
11610 | continue; | |
11611 | ||
11612 | case '^': /* DSP 5-bit unsigned immediate in bit 11. */ | |
11613 | gas_assert (mips_opts.micromips); | |
11614 | my_getExpression (&imm_expr, s); | |
11615 | check_absolute_expr (ip, &imm_expr); | |
11616 | if (imm_expr.X_add_number & ~MICROMIPSOP_MASK_RD) | |
11617 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), | |
11618 | MICROMIPSOP_MASK_RD, | |
11619 | (unsigned long) imm_expr.X_add_number); | |
11620 | INSERT_OPERAND (1, RD, *ip, imm_expr.X_add_number); | |
74cd071d CF |
11621 | imm_expr.X_op = O_absent; |
11622 | s = expr_end; | |
11623 | continue; | |
11624 | ||
a9e24354 | 11625 | case '!': /* MT usermode flag bit. */ |
df58fc94 | 11626 | gas_assert (!mips_opts.micromips); |
ef2e4d86 CF |
11627 | my_getExpression (&imm_expr, s); |
11628 | check_absolute_expr (ip, &imm_expr); | |
11629 | if (imm_expr.X_add_number & ~OP_MASK_MT_U) | |
a9e24354 TS |
11630 | as_bad (_("MT usermode bit not 0 or 1 (%lu)"), |
11631 | (unsigned long) imm_expr.X_add_number); | |
df58fc94 | 11632 | INSERT_OPERAND (0, MT_U, *ip, imm_expr.X_add_number); |
ef2e4d86 CF |
11633 | imm_expr.X_op = O_absent; |
11634 | s = expr_end; | |
11635 | continue; | |
11636 | ||
a9e24354 | 11637 | case '$': /* MT load high flag bit. */ |
df58fc94 | 11638 | gas_assert (!mips_opts.micromips); |
ef2e4d86 CF |
11639 | my_getExpression (&imm_expr, s); |
11640 | check_absolute_expr (ip, &imm_expr); | |
11641 | if (imm_expr.X_add_number & ~OP_MASK_MT_H) | |
a9e24354 TS |
11642 | as_bad (_("MT load high bit not 0 or 1 (%lu)"), |
11643 | (unsigned long) imm_expr.X_add_number); | |
df58fc94 | 11644 | INSERT_OPERAND (0, MT_H, *ip, imm_expr.X_add_number); |
ef2e4d86 CF |
11645 | imm_expr.X_op = O_absent; |
11646 | s = expr_end; | |
11647 | continue; | |
11648 | ||
90ecf173 | 11649 | case '*': /* Four DSP accumulators in bits 18,19. */ |
df58fc94 | 11650 | gas_assert (!mips_opts.micromips); |
ef2e4d86 CF |
11651 | if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' && |
11652 | s[3] >= '0' && s[3] <= '3') | |
11653 | { | |
11654 | regno = s[3] - '0'; | |
11655 | s += 4; | |
df58fc94 | 11656 | INSERT_OPERAND (0, MTACC_T, *ip, regno); |
ef2e4d86 CF |
11657 | continue; |
11658 | } | |
11659 | else | |
11660 | as_bad (_("Invalid dsp/smartmips acc register")); | |
11661 | break; | |
11662 | ||
90ecf173 | 11663 | case '&': /* Four DSP accumulators in bits 13,14. */ |
df58fc94 | 11664 | gas_assert (!mips_opts.micromips); |
ef2e4d86 CF |
11665 | if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' && |
11666 | s[3] >= '0' && s[3] <= '3') | |
11667 | { | |
11668 | regno = s[3] - '0'; | |
11669 | s += 4; | |
df58fc94 | 11670 | INSERT_OPERAND (0, MTACC_D, *ip, regno); |
ef2e4d86 CF |
11671 | continue; |
11672 | } | |
11673 | else | |
11674 | as_bad (_("Invalid dsp/smartmips acc register")); | |
11675 | break; | |
11676 | ||
dec0624d MR |
11677 | case '\\': /* 3-bit bit position. */ |
11678 | { | |
2906b037 MR |
11679 | unsigned long mask = (mips_opts.micromips |
11680 | ? MICROMIPSOP_MASK_3BITPOS | |
11681 | : OP_MASK_3BITPOS); | |
dec0624d MR |
11682 | |
11683 | my_getExpression (&imm_expr, s); | |
11684 | check_absolute_expr (ip, &imm_expr); | |
11685 | if ((unsigned long) imm_expr.X_add_number > mask) | |
11686 | as_warn (_("Bit position for %s not in range 0..%lu (%lu)"), | |
11687 | ip->insn_mo->name, | |
11688 | mask, (unsigned long) imm_expr.X_add_number); | |
11689 | INSERT_OPERAND (mips_opts.micromips, | |
11690 | 3BITPOS, *ip, imm_expr.X_add_number); | |
11691 | imm_expr.X_op = O_absent; | |
11692 | s = expr_end; | |
11693 | } | |
11694 | continue; | |
11695 | ||
252b5132 | 11696 | case ',': |
a339155f | 11697 | ++argnum; |
252b5132 RH |
11698 | if (*s++ == *args) |
11699 | continue; | |
11700 | s--; | |
11701 | switch (*++args) | |
11702 | { | |
11703 | case 'r': | |
11704 | case 'v': | |
df58fc94 | 11705 | INSERT_OPERAND (mips_opts.micromips, RS, *ip, lastregno); |
252b5132 RH |
11706 | continue; |
11707 | ||
11708 | case 'w': | |
df58fc94 | 11709 | INSERT_OPERAND (mips_opts.micromips, RT, *ip, lastregno); |
38487616 TS |
11710 | continue; |
11711 | ||
252b5132 | 11712 | case 'W': |
df58fc94 RS |
11713 | gas_assert (!mips_opts.micromips); |
11714 | INSERT_OPERAND (0, FT, *ip, lastregno); | |
252b5132 RH |
11715 | continue; |
11716 | ||
11717 | case 'V': | |
df58fc94 | 11718 | INSERT_OPERAND (mips_opts.micromips, FS, *ip, lastregno); |
252b5132 RH |
11719 | continue; |
11720 | } | |
11721 | break; | |
11722 | ||
11723 | case '(': | |
11724 | /* Handle optional base register. | |
11725 | Either the base register is omitted or | |
bdaaa2e1 | 11726 | we must have a left paren. */ |
252b5132 RH |
11727 | /* This is dependent on the next operand specifier |
11728 | is a base register specification. */ | |
df58fc94 RS |
11729 | gas_assert (args[1] == 'b' |
11730 | || (mips_opts.micromips | |
11731 | && args[1] == 'm' | |
11732 | && (args[2] == 'l' || args[2] == 'n' | |
11733 | || args[2] == 's' || args[2] == 'a'))); | |
11734 | if (*s == '\0' && args[1] == 'b') | |
252b5132 | 11735 | return; |
df58fc94 | 11736 | /* Fall through. */ |
252b5132 | 11737 | |
90ecf173 | 11738 | case ')': /* These must match exactly. */ |
df58fc94 RS |
11739 | if (*s++ == *args) |
11740 | continue; | |
11741 | break; | |
11742 | ||
11743 | case '[': /* These must match exactly. */ | |
60b63b72 | 11744 | case ']': |
df58fc94 | 11745 | gas_assert (!mips_opts.micromips); |
252b5132 RH |
11746 | if (*s++ == *args) |
11747 | continue; | |
11748 | break; | |
11749 | ||
af7ee8bf CD |
11750 | case '+': /* Opcode extension character. */ |
11751 | switch (*++args) | |
11752 | { | |
9bcd4f99 TS |
11753 | case '1': /* UDI immediates. */ |
11754 | case '2': | |
11755 | case '3': | |
11756 | case '4': | |
df58fc94 | 11757 | gas_assert (!mips_opts.micromips); |
9bcd4f99 TS |
11758 | { |
11759 | const struct mips_immed *imm = mips_immed; | |
11760 | ||
11761 | while (imm->type && imm->type != *args) | |
11762 | ++imm; | |
11763 | if (! imm->type) | |
b37df7c4 | 11764 | abort (); |
9bcd4f99 TS |
11765 | my_getExpression (&imm_expr, s); |
11766 | check_absolute_expr (ip, &imm_expr); | |
11767 | if ((unsigned long) imm_expr.X_add_number & ~imm->mask) | |
11768 | { | |
11769 | as_warn (_("Illegal %s number (%lu, 0x%lx)"), | |
11770 | imm->desc ? imm->desc : ip->insn_mo->name, | |
11771 | (unsigned long) imm_expr.X_add_number, | |
11772 | (unsigned long) imm_expr.X_add_number); | |
90ecf173 | 11773 | imm_expr.X_add_number &= imm->mask; |
9bcd4f99 TS |
11774 | } |
11775 | ip->insn_opcode |= ((unsigned long) imm_expr.X_add_number | |
11776 | << imm->shift); | |
11777 | imm_expr.X_op = O_absent; | |
11778 | s = expr_end; | |
11779 | } | |
11780 | continue; | |
90ecf173 | 11781 | |
b015e599 AP |
11782 | case 'J': /* 10-bit hypcall code. */ |
11783 | gas_assert (!mips_opts.micromips); | |
11784 | { | |
11785 | unsigned long mask = OP_MASK_CODE10; | |
11786 | ||
11787 | my_getExpression (&imm_expr, s); | |
11788 | check_absolute_expr (ip, &imm_expr); | |
11789 | if ((unsigned long) imm_expr.X_add_number > mask) | |
11790 | as_warn (_("Code for %s not in range 0..%lu (%lu)"), | |
11791 | ip->insn_mo->name, | |
11792 | mask, (unsigned long) imm_expr.X_add_number); | |
11793 | INSERT_OPERAND (0, CODE10, *ip, imm_expr.X_add_number); | |
11794 | imm_expr.X_op = O_absent; | |
11795 | s = expr_end; | |
11796 | } | |
11797 | continue; | |
11798 | ||
071742cf CD |
11799 | case 'A': /* ins/ext position, becomes LSB. */ |
11800 | limlo = 0; | |
11801 | limhi = 31; | |
5f74bc13 CD |
11802 | goto do_lsb; |
11803 | case 'E': | |
11804 | limlo = 32; | |
11805 | limhi = 63; | |
11806 | goto do_lsb; | |
90ecf173 | 11807 | do_lsb: |
071742cf CD |
11808 | my_getExpression (&imm_expr, s); |
11809 | check_absolute_expr (ip, &imm_expr); | |
11810 | if ((unsigned long) imm_expr.X_add_number < limlo | |
11811 | || (unsigned long) imm_expr.X_add_number > limhi) | |
11812 | { | |
11813 | as_bad (_("Improper position (%lu)"), | |
11814 | (unsigned long) imm_expr.X_add_number); | |
11815 | imm_expr.X_add_number = limlo; | |
11816 | } | |
11817 | lastpos = imm_expr.X_add_number; | |
df58fc94 RS |
11818 | INSERT_OPERAND (mips_opts.micromips, |
11819 | EXTLSB, *ip, imm_expr.X_add_number); | |
071742cf CD |
11820 | imm_expr.X_op = O_absent; |
11821 | s = expr_end; | |
11822 | continue; | |
11823 | ||
11824 | case 'B': /* ins size, becomes MSB. */ | |
11825 | limlo = 1; | |
11826 | limhi = 32; | |
5f74bc13 CD |
11827 | goto do_msb; |
11828 | case 'F': | |
11829 | limlo = 33; | |
11830 | limhi = 64; | |
11831 | goto do_msb; | |
90ecf173 | 11832 | do_msb: |
071742cf CD |
11833 | my_getExpression (&imm_expr, s); |
11834 | check_absolute_expr (ip, &imm_expr); | |
11835 | /* Check for negative input so that small negative numbers | |
11836 | will not succeed incorrectly. The checks against | |
11837 | (pos+size) transitively check "size" itself, | |
11838 | assuming that "pos" is reasonable. */ | |
11839 | if ((long) imm_expr.X_add_number < 0 | |
11840 | || ((unsigned long) imm_expr.X_add_number | |
11841 | + lastpos) < limlo | |
11842 | || ((unsigned long) imm_expr.X_add_number | |
11843 | + lastpos) > limhi) | |
11844 | { | |
11845 | as_bad (_("Improper insert size (%lu, position %lu)"), | |
11846 | (unsigned long) imm_expr.X_add_number, | |
11847 | (unsigned long) lastpos); | |
11848 | imm_expr.X_add_number = limlo - lastpos; | |
11849 | } | |
df58fc94 RS |
11850 | INSERT_OPERAND (mips_opts.micromips, INSMSB, *ip, |
11851 | lastpos + imm_expr.X_add_number - 1); | |
071742cf CD |
11852 | imm_expr.X_op = O_absent; |
11853 | s = expr_end; | |
11854 | continue; | |
11855 | ||
11856 | case 'C': /* ext size, becomes MSBD. */ | |
11857 | limlo = 1; | |
11858 | limhi = 32; | |
f02d8318 | 11859 | sizelo = 1; |
5f74bc13 CD |
11860 | goto do_msbd; |
11861 | case 'G': | |
11862 | limlo = 33; | |
11863 | limhi = 64; | |
f02d8318 | 11864 | sizelo = 33; |
5f74bc13 CD |
11865 | goto do_msbd; |
11866 | case 'H': | |
11867 | limlo = 33; | |
11868 | limhi = 64; | |
f02d8318 | 11869 | sizelo = 1; |
5f74bc13 | 11870 | goto do_msbd; |
90ecf173 | 11871 | do_msbd: |
071742cf CD |
11872 | my_getExpression (&imm_expr, s); |
11873 | check_absolute_expr (ip, &imm_expr); | |
f02d8318 CF |
11874 | /* The checks against (pos+size) don't transitively check |
11875 | "size" itself, assuming that "pos" is reasonable. | |
11876 | We also need to check the lower bound of "size". */ | |
11877 | if ((long) imm_expr.X_add_number < sizelo | |
071742cf CD |
11878 | || ((unsigned long) imm_expr.X_add_number |
11879 | + lastpos) < limlo | |
11880 | || ((unsigned long) imm_expr.X_add_number | |
11881 | + lastpos) > limhi) | |
11882 | { | |
11883 | as_bad (_("Improper extract size (%lu, position %lu)"), | |
11884 | (unsigned long) imm_expr.X_add_number, | |
11885 | (unsigned long) lastpos); | |
11886 | imm_expr.X_add_number = limlo - lastpos; | |
11887 | } | |
df58fc94 RS |
11888 | INSERT_OPERAND (mips_opts.micromips, |
11889 | EXTMSBD, *ip, imm_expr.X_add_number - 1); | |
071742cf CD |
11890 | imm_expr.X_op = O_absent; |
11891 | s = expr_end; | |
11892 | continue; | |
af7ee8bf | 11893 | |
bbcc0807 CD |
11894 | case 'D': |
11895 | /* +D is for disassembly only; never match. */ | |
11896 | break; | |
11897 | ||
5f74bc13 CD |
11898 | case 'I': |
11899 | /* "+I" is like "I", except that imm2_expr is used. */ | |
11900 | my_getExpression (&imm2_expr, s); | |
11901 | if (imm2_expr.X_op != O_big | |
11902 | && imm2_expr.X_op != O_constant) | |
11903 | insn_error = _("absolute expression required"); | |
9ee2a2d4 MR |
11904 | if (HAVE_32BIT_GPRS) |
11905 | normalize_constant_expr (&imm2_expr); | |
5f74bc13 CD |
11906 | s = expr_end; |
11907 | continue; | |
11908 | ||
707bfff6 | 11909 | case 'T': /* Coprocessor register. */ |
df58fc94 | 11910 | gas_assert (!mips_opts.micromips); |
ef2e4d86 CF |
11911 | /* +T is for disassembly only; never match. */ |
11912 | break; | |
11913 | ||
707bfff6 | 11914 | case 't': /* Coprocessor register number. */ |
df58fc94 | 11915 | gas_assert (!mips_opts.micromips); |
ef2e4d86 CF |
11916 | if (s[0] == '$' && ISDIGIT (s[1])) |
11917 | { | |
11918 | ++s; | |
11919 | regno = 0; | |
11920 | do | |
11921 | { | |
11922 | regno *= 10; | |
11923 | regno += *s - '0'; | |
11924 | ++s; | |
11925 | } | |
11926 | while (ISDIGIT (*s)); | |
11927 | if (regno > 31) | |
11928 | as_bad (_("Invalid register number (%d)"), regno); | |
11929 | else | |
11930 | { | |
df58fc94 | 11931 | INSERT_OPERAND (0, RT, *ip, regno); |
ef2e4d86 CF |
11932 | continue; |
11933 | } | |
11934 | } | |
11935 | else | |
11936 | as_bad (_("Invalid coprocessor 0 register number")); | |
11937 | break; | |
11938 | ||
bb35fb24 NC |
11939 | case 'x': |
11940 | /* bbit[01] and bbit[01]32 bit index. Give error if index | |
11941 | is not in the valid range. */ | |
df58fc94 | 11942 | gas_assert (!mips_opts.micromips); |
bb35fb24 NC |
11943 | my_getExpression (&imm_expr, s); |
11944 | check_absolute_expr (ip, &imm_expr); | |
11945 | if ((unsigned) imm_expr.X_add_number > 31) | |
11946 | { | |
11947 | as_bad (_("Improper bit index (%lu)"), | |
11948 | (unsigned long) imm_expr.X_add_number); | |
11949 | imm_expr.X_add_number = 0; | |
11950 | } | |
df58fc94 | 11951 | INSERT_OPERAND (0, BBITIND, *ip, imm_expr.X_add_number); |
bb35fb24 NC |
11952 | imm_expr.X_op = O_absent; |
11953 | s = expr_end; | |
11954 | continue; | |
11955 | ||
11956 | case 'X': | |
11957 | /* bbit[01] bit index when bbit is used but we generate | |
11958 | bbit[01]32 because the index is over 32. Move to the | |
11959 | next candidate if index is not in the valid range. */ | |
df58fc94 | 11960 | gas_assert (!mips_opts.micromips); |
bb35fb24 NC |
11961 | my_getExpression (&imm_expr, s); |
11962 | check_absolute_expr (ip, &imm_expr); | |
11963 | if ((unsigned) imm_expr.X_add_number < 32 | |
11964 | || (unsigned) imm_expr.X_add_number > 63) | |
11965 | break; | |
df58fc94 | 11966 | INSERT_OPERAND (0, BBITIND, *ip, imm_expr.X_add_number - 32); |
bb35fb24 NC |
11967 | imm_expr.X_op = O_absent; |
11968 | s = expr_end; | |
11969 | continue; | |
11970 | ||
11971 | case 'p': | |
11972 | /* cins, cins32, exts and exts32 position field. Give error | |
11973 | if it's not in the valid range. */ | |
df58fc94 | 11974 | gas_assert (!mips_opts.micromips); |
bb35fb24 NC |
11975 | my_getExpression (&imm_expr, s); |
11976 | check_absolute_expr (ip, &imm_expr); | |
11977 | if ((unsigned) imm_expr.X_add_number > 31) | |
11978 | { | |
11979 | as_bad (_("Improper position (%lu)"), | |
11980 | (unsigned long) imm_expr.X_add_number); | |
11981 | imm_expr.X_add_number = 0; | |
11982 | } | |
11983 | /* Make the pos explicit to simplify +S. */ | |
11984 | lastpos = imm_expr.X_add_number + 32; | |
df58fc94 | 11985 | INSERT_OPERAND (0, CINSPOS, *ip, imm_expr.X_add_number); |
bb35fb24 NC |
11986 | imm_expr.X_op = O_absent; |
11987 | s = expr_end; | |
11988 | continue; | |
11989 | ||
11990 | case 'P': | |
11991 | /* cins, cins32, exts and exts32 position field. Move to | |
11992 | the next candidate if it's not in the valid range. */ | |
df58fc94 | 11993 | gas_assert (!mips_opts.micromips); |
bb35fb24 NC |
11994 | my_getExpression (&imm_expr, s); |
11995 | check_absolute_expr (ip, &imm_expr); | |
11996 | if ((unsigned) imm_expr.X_add_number < 32 | |
11997 | || (unsigned) imm_expr.X_add_number > 63) | |
11998 | break; | |
11999 | lastpos = imm_expr.X_add_number; | |
df58fc94 | 12000 | INSERT_OPERAND (0, CINSPOS, *ip, imm_expr.X_add_number - 32); |
bb35fb24 NC |
12001 | imm_expr.X_op = O_absent; |
12002 | s = expr_end; | |
12003 | continue; | |
12004 | ||
12005 | case 's': | |
12006 | /* cins and exts length-minus-one field. */ | |
df58fc94 | 12007 | gas_assert (!mips_opts.micromips); |
bb35fb24 NC |
12008 | my_getExpression (&imm_expr, s); |
12009 | check_absolute_expr (ip, &imm_expr); | |
12010 | if ((unsigned long) imm_expr.X_add_number > 31) | |
12011 | { | |
12012 | as_bad (_("Improper size (%lu)"), | |
12013 | (unsigned long) imm_expr.X_add_number); | |
12014 | imm_expr.X_add_number = 0; | |
12015 | } | |
df58fc94 | 12016 | INSERT_OPERAND (0, CINSLM1, *ip, imm_expr.X_add_number); |
bb35fb24 NC |
12017 | imm_expr.X_op = O_absent; |
12018 | s = expr_end; | |
12019 | continue; | |
12020 | ||
12021 | case 'S': | |
12022 | /* cins32/exts32 and cins/exts aliasing cint32/exts32 | |
12023 | length-minus-one field. */ | |
df58fc94 | 12024 | gas_assert (!mips_opts.micromips); |
bb35fb24 NC |
12025 | my_getExpression (&imm_expr, s); |
12026 | check_absolute_expr (ip, &imm_expr); | |
12027 | if ((long) imm_expr.X_add_number < 0 | |
12028 | || (unsigned long) imm_expr.X_add_number + lastpos > 63) | |
12029 | { | |
12030 | as_bad (_("Improper size (%lu)"), | |
12031 | (unsigned long) imm_expr.X_add_number); | |
12032 | imm_expr.X_add_number = 0; | |
12033 | } | |
df58fc94 | 12034 | INSERT_OPERAND (0, CINSLM1, *ip, imm_expr.X_add_number); |
bb35fb24 NC |
12035 | imm_expr.X_op = O_absent; |
12036 | s = expr_end; | |
12037 | continue; | |
12038 | ||
dd3cbb7e NC |
12039 | case 'Q': |
12040 | /* seqi/snei immediate field. */ | |
df58fc94 | 12041 | gas_assert (!mips_opts.micromips); |
dd3cbb7e NC |
12042 | my_getExpression (&imm_expr, s); |
12043 | check_absolute_expr (ip, &imm_expr); | |
12044 | if ((long) imm_expr.X_add_number < -512 | |
12045 | || (long) imm_expr.X_add_number >= 512) | |
12046 | { | |
12047 | as_bad (_("Improper immediate (%ld)"), | |
12048 | (long) imm_expr.X_add_number); | |
12049 | imm_expr.X_add_number = 0; | |
12050 | } | |
df58fc94 | 12051 | INSERT_OPERAND (0, SEQI, *ip, imm_expr.X_add_number); |
dd3cbb7e NC |
12052 | imm_expr.X_op = O_absent; |
12053 | s = expr_end; | |
12054 | continue; | |
12055 | ||
98675402 | 12056 | case 'a': /* 8-bit signed offset in bit 6 */ |
df58fc94 | 12057 | gas_assert (!mips_opts.micromips); |
98675402 RS |
12058 | my_getExpression (&imm_expr, s); |
12059 | check_absolute_expr (ip, &imm_expr); | |
12060 | min_range = -((OP_MASK_OFFSET_A + 1) >> 1); | |
12061 | max_range = ((OP_MASK_OFFSET_A + 1) >> 1) - 1; | |
12062 | if (imm_expr.X_add_number < min_range | |
12063 | || imm_expr.X_add_number > max_range) | |
12064 | { | |
c95354ed | 12065 | as_bad (_("Offset not in range %ld..%ld (%ld)"), |
98675402 RS |
12066 | (long) min_range, (long) max_range, |
12067 | (long) imm_expr.X_add_number); | |
12068 | } | |
df58fc94 | 12069 | INSERT_OPERAND (0, OFFSET_A, *ip, imm_expr.X_add_number); |
98675402 RS |
12070 | imm_expr.X_op = O_absent; |
12071 | s = expr_end; | |
12072 | continue; | |
12073 | ||
12074 | case 'b': /* 8-bit signed offset in bit 3 */ | |
df58fc94 | 12075 | gas_assert (!mips_opts.micromips); |
98675402 RS |
12076 | my_getExpression (&imm_expr, s); |
12077 | check_absolute_expr (ip, &imm_expr); | |
12078 | min_range = -((OP_MASK_OFFSET_B + 1) >> 1); | |
12079 | max_range = ((OP_MASK_OFFSET_B + 1) >> 1) - 1; | |
12080 | if (imm_expr.X_add_number < min_range | |
12081 | || imm_expr.X_add_number > max_range) | |
12082 | { | |
c95354ed | 12083 | as_bad (_("Offset not in range %ld..%ld (%ld)"), |
98675402 RS |
12084 | (long) min_range, (long) max_range, |
12085 | (long) imm_expr.X_add_number); | |
12086 | } | |
df58fc94 | 12087 | INSERT_OPERAND (0, OFFSET_B, *ip, imm_expr.X_add_number); |
98675402 RS |
12088 | imm_expr.X_op = O_absent; |
12089 | s = expr_end; | |
12090 | continue; | |
12091 | ||
12092 | case 'c': /* 9-bit signed offset in bit 6 */ | |
df58fc94 | 12093 | gas_assert (!mips_opts.micromips); |
98675402 RS |
12094 | my_getExpression (&imm_expr, s); |
12095 | check_absolute_expr (ip, &imm_expr); | |
12096 | min_range = -((OP_MASK_OFFSET_C + 1) >> 1); | |
12097 | max_range = ((OP_MASK_OFFSET_C + 1) >> 1) - 1; | |
c95354ed MX |
12098 | /* We check the offset range before adjusted. */ |
12099 | min_range <<= 4; | |
12100 | max_range <<= 4; | |
98675402 RS |
12101 | if (imm_expr.X_add_number < min_range |
12102 | || imm_expr.X_add_number > max_range) | |
12103 | { | |
c95354ed | 12104 | as_bad (_("Offset not in range %ld..%ld (%ld)"), |
98675402 RS |
12105 | (long) min_range, (long) max_range, |
12106 | (long) imm_expr.X_add_number); | |
12107 | } | |
c95354ed MX |
12108 | if (imm_expr.X_add_number & 0xf) |
12109 | { | |
12110 | as_bad (_("Offset not 16 bytes alignment (%ld)"), | |
12111 | (long) imm_expr.X_add_number); | |
12112 | } | |
12113 | /* Right shift 4 bits to adjust the offset operand. */ | |
df58fc94 RS |
12114 | INSERT_OPERAND (0, OFFSET_C, *ip, |
12115 | imm_expr.X_add_number >> 4); | |
98675402 RS |
12116 | imm_expr.X_op = O_absent; |
12117 | s = expr_end; | |
12118 | continue; | |
12119 | ||
12120 | case 'z': | |
df58fc94 | 12121 | gas_assert (!mips_opts.micromips); |
98675402 RS |
12122 | if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no)) |
12123 | break; | |
12124 | if (regno == AT && mips_opts.at) | |
12125 | { | |
12126 | if (mips_opts.at == ATREG) | |
12127 | as_warn (_("used $at without \".set noat\"")); | |
12128 | else | |
12129 | as_warn (_("used $%u with \".set at=$%u\""), | |
12130 | regno, mips_opts.at); | |
12131 | } | |
df58fc94 | 12132 | INSERT_OPERAND (0, RZ, *ip, regno); |
98675402 RS |
12133 | continue; |
12134 | ||
12135 | case 'Z': | |
df58fc94 | 12136 | gas_assert (!mips_opts.micromips); |
98675402 RS |
12137 | if (!reg_lookup (&s, RTYPE_FPU, ®no)) |
12138 | break; | |
df58fc94 | 12139 | INSERT_OPERAND (0, FZ, *ip, regno); |
98675402 RS |
12140 | continue; |
12141 | ||
7f3c4072 CM |
12142 | case 'j': |
12143 | { | |
12144 | int shift = 8; | |
12145 | size_t i; | |
12146 | /* Check whether there is only a single bracketed expression | |
12147 | left. If so, it must be the base register and the | |
12148 | constant must be zero. */ | |
12149 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
12150 | continue; | |
12151 | ||
12152 | /* If this value won't fit into the offset, then go find | |
12153 | a macro that will generate a 16- or 32-bit offset code | |
12154 | pattern. */ | |
12155 | i = my_getSmallExpression (&imm_expr, imm_reloc, s); | |
12156 | if ((i == 0 && (imm_expr.X_op != O_constant | |
12157 | || imm_expr.X_add_number >= 1 << shift | |
12158 | || imm_expr.X_add_number < -1 << shift)) | |
12159 | || i > 0) | |
12160 | { | |
12161 | imm_expr.X_op = O_absent; | |
12162 | break; | |
12163 | } | |
12164 | INSERT_OPERAND (mips_opts.micromips, EVAOFFSET, *ip, | |
12165 | imm_expr.X_add_number); | |
12166 | imm_expr.X_op = O_absent; | |
12167 | s = expr_end; | |
12168 | } | |
12169 | continue; | |
12170 | ||
af7ee8bf | 12171 | default: |
df58fc94 | 12172 | as_bad (_("Internal error: bad %s opcode " |
90ecf173 | 12173 | "(unknown extension operand type `+%c'): %s %s"), |
df58fc94 | 12174 | mips_opts.micromips ? "microMIPS" : "MIPS", |
90ecf173 | 12175 | *args, insn->name, insn->args); |
af7ee8bf CD |
12176 | /* Further processing is fruitless. */ |
12177 | return; | |
12178 | } | |
12179 | break; | |
12180 | ||
df58fc94 | 12181 | case '.': /* 10-bit offset. */ |
df58fc94 | 12182 | gas_assert (mips_opts.micromips); |
dec0624d | 12183 | case '~': /* 12-bit offset. */ |
df58fc94 RS |
12184 | { |
12185 | int shift = *args == '.' ? 9 : 11; | |
12186 | size_t i; | |
12187 | ||
12188 | /* Check whether there is only a single bracketed expression | |
12189 | left. If so, it must be the base register and the | |
12190 | constant must be zero. */ | |
12191 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
12192 | continue; | |
12193 | ||
12194 | /* If this value won't fit into the offset, then go find | |
12195 | a macro that will generate a 16- or 32-bit offset code | |
12196 | pattern. */ | |
12197 | i = my_getSmallExpression (&imm_expr, imm_reloc, s); | |
12198 | if ((i == 0 && (imm_expr.X_op != O_constant | |
12199 | || imm_expr.X_add_number >= 1 << shift | |
12200 | || imm_expr.X_add_number < -1 << shift)) | |
12201 | || i > 0) | |
12202 | { | |
12203 | imm_expr.X_op = O_absent; | |
12204 | break; | |
12205 | } | |
12206 | if (shift == 9) | |
12207 | INSERT_OPERAND (1, OFFSET10, *ip, imm_expr.X_add_number); | |
12208 | else | |
dec0624d MR |
12209 | INSERT_OPERAND (mips_opts.micromips, |
12210 | OFFSET12, *ip, imm_expr.X_add_number); | |
df58fc94 RS |
12211 | imm_expr.X_op = O_absent; |
12212 | s = expr_end; | |
12213 | } | |
12214 | continue; | |
12215 | ||
252b5132 RH |
12216 | case '<': /* must be at least one digit */ |
12217 | /* | |
12218 | * According to the manual, if the shift amount is greater | |
b6ff326e KH |
12219 | * than 31 or less than 0, then the shift amount should be |
12220 | * mod 32. In reality the mips assembler issues an error. | |
252b5132 RH |
12221 | * We issue a warning and mask out all but the low 5 bits. |
12222 | */ | |
12223 | my_getExpression (&imm_expr, s); | |
12224 | check_absolute_expr (ip, &imm_expr); | |
12225 | if ((unsigned long) imm_expr.X_add_number > 31) | |
bf12938e RS |
12226 | as_warn (_("Improper shift amount (%lu)"), |
12227 | (unsigned long) imm_expr.X_add_number); | |
df58fc94 RS |
12228 | INSERT_OPERAND (mips_opts.micromips, |
12229 | SHAMT, *ip, imm_expr.X_add_number); | |
252b5132 RH |
12230 | imm_expr.X_op = O_absent; |
12231 | s = expr_end; | |
12232 | continue; | |
12233 | ||
12234 | case '>': /* shift amount minus 32 */ | |
12235 | my_getExpression (&imm_expr, s); | |
12236 | check_absolute_expr (ip, &imm_expr); | |
12237 | if ((unsigned long) imm_expr.X_add_number < 32 | |
12238 | || (unsigned long) imm_expr.X_add_number > 63) | |
12239 | break; | |
df58fc94 RS |
12240 | INSERT_OPERAND (mips_opts.micromips, |
12241 | SHAMT, *ip, imm_expr.X_add_number - 32); | |
252b5132 RH |
12242 | imm_expr.X_op = O_absent; |
12243 | s = expr_end; | |
12244 | continue; | |
12245 | ||
90ecf173 MR |
12246 | case 'k': /* CACHE code. */ |
12247 | case 'h': /* PREFX code. */ | |
12248 | case '1': /* SYNC type. */ | |
252b5132 RH |
12249 | my_getExpression (&imm_expr, s); |
12250 | check_absolute_expr (ip, &imm_expr); | |
12251 | if ((unsigned long) imm_expr.X_add_number > 31) | |
bf12938e RS |
12252 | as_warn (_("Invalid value for `%s' (%lu)"), |
12253 | ip->insn_mo->name, | |
12254 | (unsigned long) imm_expr.X_add_number); | |
df58fc94 | 12255 | switch (*args) |
d954098f | 12256 | { |
df58fc94 RS |
12257 | case 'k': |
12258 | if (mips_fix_cn63xxp1 | |
12259 | && !mips_opts.micromips | |
12260 | && strcmp ("pref", insn->name) == 0) | |
d954098f DD |
12261 | switch (imm_expr.X_add_number) |
12262 | { | |
12263 | case 5: | |
12264 | case 25: | |
12265 | case 26: | |
12266 | case 27: | |
12267 | case 28: | |
12268 | case 29: | |
12269 | case 30: | |
12270 | case 31: /* These are ok. */ | |
12271 | break; | |
12272 | ||
12273 | default: /* The rest must be changed to 28. */ | |
12274 | imm_expr.X_add_number = 28; | |
12275 | break; | |
12276 | } | |
df58fc94 RS |
12277 | INSERT_OPERAND (mips_opts.micromips, |
12278 | CACHE, *ip, imm_expr.X_add_number); | |
12279 | break; | |
12280 | case 'h': | |
12281 | INSERT_OPERAND (mips_opts.micromips, | |
12282 | PREFX, *ip, imm_expr.X_add_number); | |
12283 | break; | |
12284 | case '1': | |
12285 | INSERT_OPERAND (mips_opts.micromips, | |
12286 | STYPE, *ip, imm_expr.X_add_number); | |
12287 | break; | |
d954098f | 12288 | } |
252b5132 RH |
12289 | imm_expr.X_op = O_absent; |
12290 | s = expr_end; | |
12291 | continue; | |
12292 | ||
90ecf173 | 12293 | case 'c': /* BREAK code. */ |
df58fc94 RS |
12294 | { |
12295 | unsigned long mask = (mips_opts.micromips | |
12296 | ? MICROMIPSOP_MASK_CODE | |
12297 | : OP_MASK_CODE); | |
12298 | ||
12299 | my_getExpression (&imm_expr, s); | |
12300 | check_absolute_expr (ip, &imm_expr); | |
12301 | if ((unsigned long) imm_expr.X_add_number > mask) | |
12302 | as_warn (_("Code for %s not in range 0..%lu (%lu)"), | |
12303 | ip->insn_mo->name, | |
12304 | mask, (unsigned long) imm_expr.X_add_number); | |
12305 | INSERT_OPERAND (mips_opts.micromips, | |
12306 | CODE, *ip, imm_expr.X_add_number); | |
12307 | imm_expr.X_op = O_absent; | |
12308 | s = expr_end; | |
12309 | } | |
252b5132 RH |
12310 | continue; |
12311 | ||
90ecf173 | 12312 | case 'q': /* Lower BREAK code. */ |
df58fc94 RS |
12313 | { |
12314 | unsigned long mask = (mips_opts.micromips | |
12315 | ? MICROMIPSOP_MASK_CODE2 | |
12316 | : OP_MASK_CODE2); | |
12317 | ||
12318 | my_getExpression (&imm_expr, s); | |
12319 | check_absolute_expr (ip, &imm_expr); | |
12320 | if ((unsigned long) imm_expr.X_add_number > mask) | |
12321 | as_warn (_("Lower code for %s not in range 0..%lu (%lu)"), | |
12322 | ip->insn_mo->name, | |
12323 | mask, (unsigned long) imm_expr.X_add_number); | |
12324 | INSERT_OPERAND (mips_opts.micromips, | |
12325 | CODE2, *ip, imm_expr.X_add_number); | |
12326 | imm_expr.X_op = O_absent; | |
12327 | s = expr_end; | |
12328 | } | |
252b5132 RH |
12329 | continue; |
12330 | ||
df58fc94 RS |
12331 | case 'B': /* 20- or 10-bit syscall/break/wait code. */ |
12332 | { | |
12333 | unsigned long mask = (mips_opts.micromips | |
12334 | ? MICROMIPSOP_MASK_CODE10 | |
12335 | : OP_MASK_CODE20); | |
12336 | ||
12337 | my_getExpression (&imm_expr, s); | |
12338 | check_absolute_expr (ip, &imm_expr); | |
12339 | if ((unsigned long) imm_expr.X_add_number > mask) | |
12340 | as_warn (_("Code for %s not in range 0..%lu (%lu)"), | |
12341 | ip->insn_mo->name, | |
12342 | mask, (unsigned long) imm_expr.X_add_number); | |
12343 | if (mips_opts.micromips) | |
12344 | INSERT_OPERAND (1, CODE10, *ip, imm_expr.X_add_number); | |
12345 | else | |
12346 | INSERT_OPERAND (0, CODE20, *ip, imm_expr.X_add_number); | |
12347 | imm_expr.X_op = O_absent; | |
12348 | s = expr_end; | |
12349 | } | |
252b5132 RH |
12350 | continue; |
12351 | ||
df58fc94 RS |
12352 | case 'C': /* 25- or 23-bit coprocessor code. */ |
12353 | { | |
12354 | unsigned long mask = (mips_opts.micromips | |
12355 | ? MICROMIPSOP_MASK_COPZ | |
12356 | : OP_MASK_COPZ); | |
12357 | ||
12358 | my_getExpression (&imm_expr, s); | |
12359 | check_absolute_expr (ip, &imm_expr); | |
12360 | if ((unsigned long) imm_expr.X_add_number > mask) | |
12361 | as_warn (_("Coproccesor code > %u bits (%lu)"), | |
12362 | mips_opts.micromips ? 23U : 25U, | |
793b27f4 | 12363 | (unsigned long) imm_expr.X_add_number); |
df58fc94 RS |
12364 | INSERT_OPERAND (mips_opts.micromips, |
12365 | COPZ, *ip, imm_expr.X_add_number); | |
12366 | imm_expr.X_op = O_absent; | |
12367 | s = expr_end; | |
12368 | } | |
beae10d5 | 12369 | continue; |
252b5132 | 12370 | |
df58fc94 RS |
12371 | case 'J': /* 19-bit WAIT code. */ |
12372 | gas_assert (!mips_opts.micromips); | |
4372b673 NC |
12373 | my_getExpression (&imm_expr, s); |
12374 | check_absolute_expr (ip, &imm_expr); | |
793b27f4 | 12375 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE19) |
df58fc94 RS |
12376 | { |
12377 | as_warn (_("Illegal 19-bit code (%lu)"), | |
a9e24354 | 12378 | (unsigned long) imm_expr.X_add_number); |
df58fc94 RS |
12379 | imm_expr.X_add_number &= OP_MASK_CODE19; |
12380 | } | |
12381 | INSERT_OPERAND (0, CODE19, *ip, imm_expr.X_add_number); | |
4372b673 NC |
12382 | imm_expr.X_op = O_absent; |
12383 | s = expr_end; | |
12384 | continue; | |
12385 | ||
707bfff6 | 12386 | case 'P': /* Performance register. */ |
df58fc94 | 12387 | gas_assert (!mips_opts.micromips); |
beae10d5 | 12388 | my_getExpression (&imm_expr, s); |
252b5132 | 12389 | check_absolute_expr (ip, &imm_expr); |
beae10d5 | 12390 | if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1) |
bf12938e RS |
12391 | as_warn (_("Invalid performance register (%lu)"), |
12392 | (unsigned long) imm_expr.X_add_number); | |
e407c74b NC |
12393 | if (imm_expr.X_add_number != 0 && mips_opts.arch == CPU_R5900 |
12394 | && (!strcmp(insn->name,"mfps") || !strcmp(insn->name,"mtps"))) | |
12395 | as_warn (_("Invalid performance register (%lu)"), | |
12396 | (unsigned long) imm_expr.X_add_number); | |
df58fc94 | 12397 | INSERT_OPERAND (0, PERFREG, *ip, imm_expr.X_add_number); |
beae10d5 KH |
12398 | imm_expr.X_op = O_absent; |
12399 | s = expr_end; | |
12400 | continue; | |
252b5132 | 12401 | |
707bfff6 | 12402 | case 'G': /* Coprocessor destination register. */ |
df58fc94 RS |
12403 | { |
12404 | unsigned long opcode = ip->insn_opcode; | |
12405 | unsigned long mask; | |
12406 | unsigned int types; | |
12407 | int cop0; | |
12408 | ||
12409 | if (mips_opts.micromips) | |
12410 | { | |
12411 | mask = ~((MICROMIPSOP_MASK_RT << MICROMIPSOP_SH_RT) | |
12412 | | (MICROMIPSOP_MASK_RS << MICROMIPSOP_SH_RS) | |
12413 | | (MICROMIPSOP_MASK_SEL << MICROMIPSOP_SH_SEL)); | |
12414 | opcode &= mask; | |
12415 | switch (opcode) | |
12416 | { | |
12417 | case 0x000000fc: /* mfc0 */ | |
12418 | case 0x000002fc: /* mtc0 */ | |
12419 | case 0x580000fc: /* dmfc0 */ | |
12420 | case 0x580002fc: /* dmtc0 */ | |
12421 | cop0 = 1; | |
12422 | break; | |
12423 | default: | |
12424 | cop0 = 0; | |
12425 | break; | |
12426 | } | |
12427 | } | |
12428 | else | |
12429 | { | |
12430 | opcode = (opcode >> OP_SH_OP) & OP_MASK_OP; | |
12431 | cop0 = opcode == OP_OP_COP0; | |
12432 | } | |
12433 | types = RTYPE_NUM | (cop0 ? RTYPE_CP0 : RTYPE_GP); | |
12434 | ok = reg_lookup (&s, types, ®no); | |
12435 | if (mips_opts.micromips) | |
12436 | INSERT_OPERAND (1, RS, *ip, regno); | |
12437 | else | |
12438 | INSERT_OPERAND (0, RD, *ip, regno); | |
12439 | if (ok) | |
12440 | { | |
12441 | lastregno = regno; | |
12442 | continue; | |
12443 | } | |
12444 | } | |
12445 | break; | |
707bfff6 | 12446 | |
df58fc94 RS |
12447 | case 'y': /* ALNV.PS source register. */ |
12448 | gas_assert (mips_opts.micromips); | |
12449 | goto do_reg; | |
12450 | case 'x': /* Ignore register name. */ | |
12451 | case 'U': /* Destination register (CLO/CLZ). */ | |
12452 | case 'g': /* Coprocessor destination register. */ | |
12453 | gas_assert (!mips_opts.micromips); | |
90ecf173 MR |
12454 | case 'b': /* Base register. */ |
12455 | case 'd': /* Destination register. */ | |
12456 | case 's': /* Source register. */ | |
12457 | case 't': /* Target register. */ | |
12458 | case 'r': /* Both target and source. */ | |
12459 | case 'v': /* Both dest and source. */ | |
12460 | case 'w': /* Both dest and target. */ | |
12461 | case 'E': /* Coprocessor target register. */ | |
12462 | case 'K': /* RDHWR destination register. */ | |
90ecf173 | 12463 | case 'z': /* Must be zero register. */ |
df58fc94 | 12464 | do_reg: |
90ecf173 | 12465 | s_reset = s; |
707bfff6 TS |
12466 | if (*args == 'E' || *args == 'K') |
12467 | ok = reg_lookup (&s, RTYPE_NUM, ®no); | |
12468 | else | |
12469 | { | |
12470 | ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no); | |
741fe287 MR |
12471 | if (regno == AT && mips_opts.at) |
12472 | { | |
12473 | if (mips_opts.at == ATREG) | |
f71d0d44 | 12474 | as_warn (_("Used $at without \".set noat\"")); |
741fe287 | 12475 | else |
f71d0d44 | 12476 | as_warn (_("Used $%u with \".set at=$%u\""), |
741fe287 MR |
12477 | regno, mips_opts.at); |
12478 | } | |
707bfff6 TS |
12479 | } |
12480 | if (ok) | |
252b5132 | 12481 | { |
252b5132 RH |
12482 | c = *args; |
12483 | if (*s == ' ') | |
f9419b05 | 12484 | ++s; |
252b5132 RH |
12485 | if (args[1] != *s) |
12486 | { | |
12487 | if (c == 'r' || c == 'v' || c == 'w') | |
12488 | { | |
12489 | regno = lastregno; | |
12490 | s = s_reset; | |
f9419b05 | 12491 | ++args; |
252b5132 RH |
12492 | } |
12493 | } | |
12494 | /* 'z' only matches $0. */ | |
12495 | if (c == 'z' && regno != 0) | |
12496 | break; | |
12497 | ||
24864476 | 12498 | if (c == 's' && !strncmp (ip->insn_mo->name, "jalr", 4)) |
e7c604dd CM |
12499 | { |
12500 | if (regno == lastregno) | |
90ecf173 MR |
12501 | { |
12502 | insn_error | |
f71d0d44 | 12503 | = _("Source and destination must be different"); |
e7c604dd | 12504 | continue; |
90ecf173 | 12505 | } |
24864476 | 12506 | if (regno == 31 && lastregno == 0xffffffff) |
90ecf173 MR |
12507 | { |
12508 | insn_error | |
f71d0d44 | 12509 | = _("A destination register must be supplied"); |
e7c604dd | 12510 | continue; |
90ecf173 | 12511 | } |
e7c604dd | 12512 | } |
90ecf173 MR |
12513 | /* Now that we have assembled one operand, we use the args |
12514 | string to figure out where it goes in the instruction. */ | |
252b5132 RH |
12515 | switch (c) |
12516 | { | |
12517 | case 'r': | |
12518 | case 's': | |
12519 | case 'v': | |
12520 | case 'b': | |
df58fc94 | 12521 | INSERT_OPERAND (mips_opts.micromips, RS, *ip, regno); |
252b5132 | 12522 | break; |
df58fc94 | 12523 | |
af7ee8bf | 12524 | case 'K': |
df58fc94 RS |
12525 | if (mips_opts.micromips) |
12526 | INSERT_OPERAND (1, RS, *ip, regno); | |
12527 | else | |
12528 | INSERT_OPERAND (0, RD, *ip, regno); | |
12529 | break; | |
12530 | ||
12531 | case 'd': | |
ef2e4d86 | 12532 | case 'g': |
df58fc94 | 12533 | INSERT_OPERAND (mips_opts.micromips, RD, *ip, regno); |
252b5132 | 12534 | break; |
df58fc94 | 12535 | |
4372b673 | 12536 | case 'U': |
df58fc94 RS |
12537 | gas_assert (!mips_opts.micromips); |
12538 | INSERT_OPERAND (0, RD, *ip, regno); | |
12539 | INSERT_OPERAND (0, RT, *ip, regno); | |
4372b673 | 12540 | break; |
df58fc94 | 12541 | |
252b5132 RH |
12542 | case 'w': |
12543 | case 't': | |
12544 | case 'E': | |
df58fc94 RS |
12545 | INSERT_OPERAND (mips_opts.micromips, RT, *ip, regno); |
12546 | break; | |
12547 | ||
12548 | case 'y': | |
12549 | gas_assert (mips_opts.micromips); | |
12550 | INSERT_OPERAND (1, RS3, *ip, regno); | |
252b5132 | 12551 | break; |
df58fc94 | 12552 | |
252b5132 RH |
12553 | case 'x': |
12554 | /* This case exists because on the r3000 trunc | |
12555 | expands into a macro which requires a gp | |
12556 | register. On the r6000 or r4000 it is | |
12557 | assembled into a single instruction which | |
12558 | ignores the register. Thus the insn version | |
12559 | is MIPS_ISA2 and uses 'x', and the macro | |
12560 | version is MIPS_ISA1 and uses 't'. */ | |
12561 | break; | |
df58fc94 | 12562 | |
252b5132 RH |
12563 | case 'z': |
12564 | /* This case is for the div instruction, which | |
12565 | acts differently if the destination argument | |
12566 | is $0. This only matches $0, and is checked | |
12567 | outside the switch. */ | |
12568 | break; | |
252b5132 RH |
12569 | } |
12570 | lastregno = regno; | |
12571 | continue; | |
12572 | } | |
252b5132 RH |
12573 | switch (*args++) |
12574 | { | |
12575 | case 'r': | |
12576 | case 'v': | |
df58fc94 | 12577 | INSERT_OPERAND (mips_opts.micromips, RS, *ip, lastregno); |
252b5132 | 12578 | continue; |
df58fc94 | 12579 | |
252b5132 | 12580 | case 'w': |
df58fc94 | 12581 | INSERT_OPERAND (mips_opts.micromips, RT, *ip, lastregno); |
252b5132 RH |
12582 | continue; |
12583 | } | |
12584 | break; | |
12585 | ||
deec1734 | 12586 | case 'O': /* MDMX alignment immediate constant. */ |
df58fc94 | 12587 | gas_assert (!mips_opts.micromips); |
deec1734 CD |
12588 | my_getExpression (&imm_expr, s); |
12589 | check_absolute_expr (ip, &imm_expr); | |
12590 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_ALN) | |
20203fb9 | 12591 | as_warn (_("Improper align amount (%ld), using low bits"), |
bf12938e | 12592 | (long) imm_expr.X_add_number); |
df58fc94 | 12593 | INSERT_OPERAND (0, ALN, *ip, imm_expr.X_add_number); |
deec1734 CD |
12594 | imm_expr.X_op = O_absent; |
12595 | s = expr_end; | |
12596 | continue; | |
12597 | ||
12598 | case 'Q': /* MDMX vector, element sel, or const. */ | |
12599 | if (s[0] != '$') | |
12600 | { | |
12601 | /* MDMX Immediate. */ | |
df58fc94 | 12602 | gas_assert (!mips_opts.micromips); |
deec1734 CD |
12603 | my_getExpression (&imm_expr, s); |
12604 | check_absolute_expr (ip, &imm_expr); | |
12605 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_FT) | |
bf12938e RS |
12606 | as_warn (_("Invalid MDMX Immediate (%ld)"), |
12607 | (long) imm_expr.X_add_number); | |
df58fc94 | 12608 | INSERT_OPERAND (0, FT, *ip, imm_expr.X_add_number); |
deec1734 CD |
12609 | if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL)) |
12610 | ip->insn_opcode |= MDMX_FMTSEL_IMM_QH << OP_SH_VSEL; | |
12611 | else | |
12612 | ip->insn_opcode |= MDMX_FMTSEL_IMM_OB << OP_SH_VSEL; | |
deec1734 CD |
12613 | imm_expr.X_op = O_absent; |
12614 | s = expr_end; | |
12615 | continue; | |
12616 | } | |
12617 | /* Not MDMX Immediate. Fall through. */ | |
12618 | case 'X': /* MDMX destination register. */ | |
12619 | case 'Y': /* MDMX source register. */ | |
12620 | case 'Z': /* MDMX target register. */ | |
12621 | is_mdmx = 1; | |
df58fc94 RS |
12622 | case 'W': |
12623 | gas_assert (!mips_opts.micromips); | |
90ecf173 MR |
12624 | case 'D': /* Floating point destination register. */ |
12625 | case 'S': /* Floating point source register. */ | |
12626 | case 'T': /* Floating point target register. */ | |
12627 | case 'R': /* Floating point source register. */ | |
252b5132 | 12628 | case 'V': |
707bfff6 TS |
12629 | rtype = RTYPE_FPU; |
12630 | if (is_mdmx | |
846ef2d0 | 12631 | || ((mips_opts.ase & ASE_MDMX) |
707bfff6 TS |
12632 | && (ip->insn_mo->pinfo & FP_D) |
12633 | && (ip->insn_mo->pinfo & (INSN_COPROC_MOVE_DELAY | |
12634 | | INSN_COPROC_MEMORY_DELAY | |
12635 | | INSN_LOAD_COPROC_DELAY | |
12636 | | INSN_LOAD_MEMORY_DELAY | |
12637 | | INSN_STORE_MEMORY)))) | |
12638 | rtype |= RTYPE_VEC; | |
252b5132 | 12639 | s_reset = s; |
707bfff6 | 12640 | if (reg_lookup (&s, rtype, ®no)) |
252b5132 | 12641 | { |
252b5132 | 12642 | if ((regno & 1) != 0 |
ca4e0257 | 12643 | && HAVE_32BIT_FPRS |
90ecf173 | 12644 | && !mips_oddfpreg_ok (ip->insn_mo, argnum)) |
252b5132 RH |
12645 | as_warn (_("Float register should be even, was %d"), |
12646 | regno); | |
12647 | ||
12648 | c = *args; | |
12649 | if (*s == ' ') | |
f9419b05 | 12650 | ++s; |
252b5132 RH |
12651 | if (args[1] != *s) |
12652 | { | |
12653 | if (c == 'V' || c == 'W') | |
12654 | { | |
12655 | regno = lastregno; | |
12656 | s = s_reset; | |
f9419b05 | 12657 | ++args; |
252b5132 RH |
12658 | } |
12659 | } | |
12660 | switch (c) | |
12661 | { | |
12662 | case 'D': | |
deec1734 | 12663 | case 'X': |
df58fc94 | 12664 | INSERT_OPERAND (mips_opts.micromips, FD, *ip, regno); |
252b5132 | 12665 | break; |
df58fc94 | 12666 | |
252b5132 RH |
12667 | case 'V': |
12668 | case 'S': | |
deec1734 | 12669 | case 'Y': |
df58fc94 | 12670 | INSERT_OPERAND (mips_opts.micromips, FS, *ip, regno); |
252b5132 | 12671 | break; |
df58fc94 | 12672 | |
deec1734 CD |
12673 | case 'Q': |
12674 | /* This is like 'Z', but also needs to fix the MDMX | |
12675 | vector/scalar select bits. Note that the | |
12676 | scalar immediate case is handled above. */ | |
12677 | if (*s == '[') | |
12678 | { | |
12679 | int is_qh = (ip->insn_opcode & (1 << OP_SH_VSEL)); | |
12680 | int max_el = (is_qh ? 3 : 7); | |
12681 | s++; | |
12682 | my_getExpression(&imm_expr, s); | |
12683 | check_absolute_expr (ip, &imm_expr); | |
12684 | s = expr_end; | |
12685 | if (imm_expr.X_add_number > max_el) | |
20203fb9 NC |
12686 | as_bad (_("Bad element selector %ld"), |
12687 | (long) imm_expr.X_add_number); | |
deec1734 CD |
12688 | imm_expr.X_add_number &= max_el; |
12689 | ip->insn_opcode |= (imm_expr.X_add_number | |
12690 | << (OP_SH_VSEL + | |
12691 | (is_qh ? 2 : 1))); | |
01a3f561 | 12692 | imm_expr.X_op = O_absent; |
deec1734 | 12693 | if (*s != ']') |
20203fb9 | 12694 | as_warn (_("Expecting ']' found '%s'"), s); |
deec1734 CD |
12695 | else |
12696 | s++; | |
12697 | } | |
12698 | else | |
12699 | { | |
12700 | if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL)) | |
12701 | ip->insn_opcode |= (MDMX_FMTSEL_VEC_QH | |
12702 | << OP_SH_VSEL); | |
12703 | else | |
12704 | ip->insn_opcode |= (MDMX_FMTSEL_VEC_OB << | |
12705 | OP_SH_VSEL); | |
12706 | } | |
90ecf173 | 12707 | /* Fall through. */ |
252b5132 RH |
12708 | case 'W': |
12709 | case 'T': | |
deec1734 | 12710 | case 'Z': |
df58fc94 | 12711 | INSERT_OPERAND (mips_opts.micromips, FT, *ip, regno); |
252b5132 | 12712 | break; |
df58fc94 | 12713 | |
252b5132 | 12714 | case 'R': |
df58fc94 | 12715 | INSERT_OPERAND (mips_opts.micromips, FR, *ip, regno); |
252b5132 RH |
12716 | break; |
12717 | } | |
12718 | lastregno = regno; | |
12719 | continue; | |
12720 | } | |
12721 | ||
252b5132 RH |
12722 | switch (*args++) |
12723 | { | |
12724 | case 'V': | |
df58fc94 | 12725 | INSERT_OPERAND (mips_opts.micromips, FS, *ip, lastregno); |
252b5132 | 12726 | continue; |
df58fc94 | 12727 | |
252b5132 | 12728 | case 'W': |
df58fc94 | 12729 | INSERT_OPERAND (mips_opts.micromips, FT, *ip, lastregno); |
252b5132 RH |
12730 | continue; |
12731 | } | |
12732 | break; | |
12733 | ||
12734 | case 'I': | |
12735 | my_getExpression (&imm_expr, s); | |
12736 | if (imm_expr.X_op != O_big | |
12737 | && imm_expr.X_op != O_constant) | |
12738 | insn_error = _("absolute expression required"); | |
9ee2a2d4 MR |
12739 | if (HAVE_32BIT_GPRS) |
12740 | normalize_constant_expr (&imm_expr); | |
252b5132 RH |
12741 | s = expr_end; |
12742 | continue; | |
12743 | ||
12744 | case 'A': | |
12745 | my_getExpression (&offset_expr, s); | |
2051e8c4 | 12746 | normalize_address_expr (&offset_expr); |
f6688943 | 12747 | *imm_reloc = BFD_RELOC_32; |
252b5132 RH |
12748 | s = expr_end; |
12749 | continue; | |
12750 | ||
12751 | case 'F': | |
12752 | case 'L': | |
12753 | case 'f': | |
12754 | case 'l': | |
12755 | { | |
12756 | int f64; | |
ca4e0257 | 12757 | int using_gprs; |
252b5132 RH |
12758 | char *save_in; |
12759 | char *err; | |
12760 | unsigned char temp[8]; | |
12761 | int len; | |
12762 | unsigned int length; | |
12763 | segT seg; | |
12764 | subsegT subseg; | |
12765 | char *p; | |
12766 | ||
12767 | /* These only appear as the last operand in an | |
12768 | instruction, and every instruction that accepts | |
12769 | them in any variant accepts them in all variants. | |
12770 | This means we don't have to worry about backing out | |
12771 | any changes if the instruction does not match. | |
12772 | ||
12773 | The difference between them is the size of the | |
12774 | floating point constant and where it goes. For 'F' | |
12775 | and 'L' the constant is 64 bits; for 'f' and 'l' it | |
12776 | is 32 bits. Where the constant is placed is based | |
12777 | on how the MIPS assembler does things: | |
12778 | F -- .rdata | |
12779 | L -- .lit8 | |
12780 | f -- immediate value | |
12781 | l -- .lit4 | |
12782 | ||
12783 | The .lit4 and .lit8 sections are only used if | |
12784 | permitted by the -G argument. | |
12785 | ||
ca4e0257 RS |
12786 | The code below needs to know whether the target register |
12787 | is 32 or 64 bits wide. It relies on the fact 'f' and | |
12788 | 'F' are used with GPR-based instructions and 'l' and | |
12789 | 'L' are used with FPR-based instructions. */ | |
252b5132 RH |
12790 | |
12791 | f64 = *args == 'F' || *args == 'L'; | |
ca4e0257 | 12792 | using_gprs = *args == 'F' || *args == 'f'; |
252b5132 RH |
12793 | |
12794 | save_in = input_line_pointer; | |
12795 | input_line_pointer = s; | |
12796 | err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len); | |
12797 | length = len; | |
12798 | s = input_line_pointer; | |
12799 | input_line_pointer = save_in; | |
12800 | if (err != NULL && *err != '\0') | |
12801 | { | |
12802 | as_bad (_("Bad floating point constant: %s"), err); | |
12803 | memset (temp, '\0', sizeof temp); | |
12804 | length = f64 ? 8 : 4; | |
12805 | } | |
12806 | ||
9c2799c2 | 12807 | gas_assert (length == (unsigned) (f64 ? 8 : 4)); |
252b5132 RH |
12808 | |
12809 | if (*args == 'f' | |
12810 | || (*args == 'l' | |
3e722fb5 | 12811 | && (g_switch_value < 4 |
252b5132 RH |
12812 | || (temp[0] == 0 && temp[1] == 0) |
12813 | || (temp[2] == 0 && temp[3] == 0)))) | |
12814 | { | |
12815 | imm_expr.X_op = O_constant; | |
90ecf173 | 12816 | if (!target_big_endian) |
252b5132 RH |
12817 | imm_expr.X_add_number = bfd_getl32 (temp); |
12818 | else | |
12819 | imm_expr.X_add_number = bfd_getb32 (temp); | |
12820 | } | |
12821 | else if (length > 4 | |
90ecf173 | 12822 | && !mips_disable_float_construction |
ca4e0257 RS |
12823 | /* Constants can only be constructed in GPRs and |
12824 | copied to FPRs if the GPRs are at least as wide | |
12825 | as the FPRs. Force the constant into memory if | |
12826 | we are using 64-bit FPRs but the GPRs are only | |
12827 | 32 bits wide. */ | |
12828 | && (using_gprs | |
90ecf173 | 12829 | || !(HAVE_64BIT_FPRS && HAVE_32BIT_GPRS)) |
252b5132 RH |
12830 | && ((temp[0] == 0 && temp[1] == 0) |
12831 | || (temp[2] == 0 && temp[3] == 0)) | |
12832 | && ((temp[4] == 0 && temp[5] == 0) | |
12833 | || (temp[6] == 0 && temp[7] == 0))) | |
12834 | { | |
ca4e0257 | 12835 | /* The value is simple enough to load with a couple of |
90ecf173 MR |
12836 | instructions. If using 32-bit registers, set |
12837 | imm_expr to the high order 32 bits and offset_expr to | |
12838 | the low order 32 bits. Otherwise, set imm_expr to | |
12839 | the entire 64 bit constant. */ | |
ca4e0257 | 12840 | if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS) |
252b5132 RH |
12841 | { |
12842 | imm_expr.X_op = O_constant; | |
12843 | offset_expr.X_op = O_constant; | |
90ecf173 | 12844 | if (!target_big_endian) |
252b5132 RH |
12845 | { |
12846 | imm_expr.X_add_number = bfd_getl32 (temp + 4); | |
12847 | offset_expr.X_add_number = bfd_getl32 (temp); | |
12848 | } | |
12849 | else | |
12850 | { | |
12851 | imm_expr.X_add_number = bfd_getb32 (temp); | |
12852 | offset_expr.X_add_number = bfd_getb32 (temp + 4); | |
12853 | } | |
12854 | if (offset_expr.X_add_number == 0) | |
12855 | offset_expr.X_op = O_absent; | |
12856 | } | |
12857 | else if (sizeof (imm_expr.X_add_number) > 4) | |
12858 | { | |
12859 | imm_expr.X_op = O_constant; | |
90ecf173 | 12860 | if (!target_big_endian) |
252b5132 RH |
12861 | imm_expr.X_add_number = bfd_getl64 (temp); |
12862 | else | |
12863 | imm_expr.X_add_number = bfd_getb64 (temp); | |
12864 | } | |
12865 | else | |
12866 | { | |
12867 | imm_expr.X_op = O_big; | |
12868 | imm_expr.X_add_number = 4; | |
90ecf173 | 12869 | if (!target_big_endian) |
252b5132 RH |
12870 | { |
12871 | generic_bignum[0] = bfd_getl16 (temp); | |
12872 | generic_bignum[1] = bfd_getl16 (temp + 2); | |
12873 | generic_bignum[2] = bfd_getl16 (temp + 4); | |
12874 | generic_bignum[3] = bfd_getl16 (temp + 6); | |
12875 | } | |
12876 | else | |
12877 | { | |
12878 | generic_bignum[0] = bfd_getb16 (temp + 6); | |
12879 | generic_bignum[1] = bfd_getb16 (temp + 4); | |
12880 | generic_bignum[2] = bfd_getb16 (temp + 2); | |
12881 | generic_bignum[3] = bfd_getb16 (temp); | |
12882 | } | |
12883 | } | |
12884 | } | |
12885 | else | |
12886 | { | |
12887 | const char *newname; | |
12888 | segT new_seg; | |
12889 | ||
12890 | /* Switch to the right section. */ | |
12891 | seg = now_seg; | |
12892 | subseg = now_subseg; | |
12893 | switch (*args) | |
12894 | { | |
12895 | default: /* unused default case avoids warnings. */ | |
12896 | case 'L': | |
12897 | newname = RDATA_SECTION_NAME; | |
3e722fb5 | 12898 | if (g_switch_value >= 8) |
252b5132 RH |
12899 | newname = ".lit8"; |
12900 | break; | |
12901 | case 'F': | |
3e722fb5 | 12902 | newname = RDATA_SECTION_NAME; |
252b5132 RH |
12903 | break; |
12904 | case 'l': | |
9c2799c2 | 12905 | gas_assert (g_switch_value >= 4); |
252b5132 RH |
12906 | newname = ".lit4"; |
12907 | break; | |
12908 | } | |
12909 | new_seg = subseg_new (newname, (subsegT) 0); | |
f3ded42a RS |
12910 | bfd_set_section_flags (stdoutput, new_seg, |
12911 | (SEC_ALLOC | |
12912 | | SEC_LOAD | |
12913 | | SEC_READONLY | |
12914 | | SEC_DATA)); | |
252b5132 | 12915 | frag_align (*args == 'l' ? 2 : 3, 0, 0); |
f3ded42a | 12916 | if (strncmp (TARGET_OS, "elf", 3) != 0) |
252b5132 RH |
12917 | record_alignment (new_seg, 4); |
12918 | else | |
12919 | record_alignment (new_seg, *args == 'l' ? 2 : 3); | |
12920 | if (seg == now_seg) | |
12921 | as_bad (_("Can't use floating point insn in this section")); | |
12922 | ||
df58fc94 RS |
12923 | /* Set the argument to the current address in the |
12924 | section. */ | |
12925 | offset_expr.X_op = O_symbol; | |
12926 | offset_expr.X_add_symbol = symbol_temp_new_now (); | |
12927 | offset_expr.X_add_number = 0; | |
12928 | ||
12929 | /* Put the floating point number into the section. */ | |
12930 | p = frag_more ((int) length); | |
12931 | memcpy (p, temp, length); | |
12932 | ||
12933 | /* Switch back to the original section. */ | |
12934 | subseg_set (seg, subseg); | |
12935 | } | |
12936 | } | |
12937 | continue; | |
12938 | ||
12939 | case 'i': /* 16-bit unsigned immediate. */ | |
12940 | case 'j': /* 16-bit signed immediate. */ | |
12941 | *imm_reloc = BFD_RELOC_LO16; | |
12942 | if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0) | |
12943 | { | |
12944 | int more; | |
12945 | offsetT minval, maxval; | |
12946 | ||
12947 | more = (insn + 1 < past | |
12948 | && strcmp (insn->name, insn[1].name) == 0); | |
12949 | ||
12950 | /* If the expression was written as an unsigned number, | |
12951 | only treat it as signed if there are no more | |
12952 | alternatives. */ | |
12953 | if (more | |
12954 | && *args == 'j' | |
12955 | && sizeof (imm_expr.X_add_number) <= 4 | |
12956 | && imm_expr.X_op == O_constant | |
12957 | && imm_expr.X_add_number < 0 | |
12958 | && imm_expr.X_unsigned | |
12959 | && HAVE_64BIT_GPRS) | |
12960 | break; | |
12961 | ||
12962 | /* For compatibility with older assemblers, we accept | |
12963 | 0x8000-0xffff as signed 16-bit numbers when only | |
12964 | signed numbers are allowed. */ | |
12965 | if (*args == 'i') | |
12966 | minval = 0, maxval = 0xffff; | |
12967 | else if (more) | |
12968 | minval = -0x8000, maxval = 0x7fff; | |
12969 | else | |
12970 | minval = -0x8000, maxval = 0xffff; | |
12971 | ||
12972 | if (imm_expr.X_op != O_constant | |
12973 | || imm_expr.X_add_number < minval | |
12974 | || imm_expr.X_add_number > maxval) | |
12975 | { | |
12976 | if (more) | |
12977 | break; | |
12978 | if (imm_expr.X_op == O_constant | |
12979 | || imm_expr.X_op == O_big) | |
12980 | as_bad (_("Expression out of range")); | |
12981 | } | |
12982 | } | |
12983 | s = expr_end; | |
12984 | continue; | |
12985 | ||
12986 | case 'o': /* 16-bit offset. */ | |
12987 | offset_reloc[0] = BFD_RELOC_LO16; | |
12988 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
12989 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
12990 | ||
12991 | /* Check whether there is only a single bracketed expression | |
12992 | left. If so, it must be the base register and the | |
12993 | constant must be zero. */ | |
12994 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
12995 | { | |
12996 | offset_expr.X_op = O_constant; | |
12997 | offset_expr.X_add_number = 0; | |
12998 | continue; | |
12999 | } | |
13000 | ||
13001 | /* If this value won't fit into a 16 bit offset, then go | |
13002 | find a macro that will generate the 32 bit offset | |
13003 | code pattern. */ | |
13004 | if (my_getSmallExpression (&offset_expr, offset_reloc, s) == 0 | |
13005 | && (offset_expr.X_op != O_constant | |
13006 | || offset_expr.X_add_number >= 0x8000 | |
13007 | || offset_expr.X_add_number < -0x8000)) | |
13008 | break; | |
13009 | ||
13010 | s = expr_end; | |
13011 | continue; | |
13012 | ||
13013 | case 'p': /* PC-relative offset. */ | |
13014 | *offset_reloc = BFD_RELOC_16_PCREL_S2; | |
13015 | my_getExpression (&offset_expr, s); | |
13016 | s = expr_end; | |
13017 | continue; | |
13018 | ||
13019 | case 'u': /* Upper 16 bits. */ | |
5821951c | 13020 | *imm_reloc = BFD_RELOC_LO16; |
df58fc94 RS |
13021 | if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0 |
13022 | && imm_expr.X_op == O_constant | |
13023 | && (imm_expr.X_add_number < 0 | |
13024 | || imm_expr.X_add_number >= 0x10000)) | |
13025 | as_bad (_("lui expression (%lu) not in range 0..65535"), | |
13026 | (unsigned long) imm_expr.X_add_number); | |
13027 | s = expr_end; | |
13028 | continue; | |
13029 | ||
13030 | case 'a': /* 26-bit address. */ | |
13031 | *offset_reloc = BFD_RELOC_MIPS_JMP; | |
13032 | my_getExpression (&offset_expr, s); | |
13033 | s = expr_end; | |
13034 | continue; | |
13035 | ||
13036 | case 'N': /* 3-bit branch condition code. */ | |
13037 | case 'M': /* 3-bit compare condition code. */ | |
13038 | rtype = RTYPE_CCC; | |
13039 | if (ip->insn_mo->pinfo & (FP_D | FP_S)) | |
13040 | rtype |= RTYPE_FCC; | |
13041 | if (!reg_lookup (&s, rtype, ®no)) | |
13042 | break; | |
13043 | if ((strcmp (str + strlen (str) - 3, ".ps") == 0 | |
13044 | || strcmp (str + strlen (str) - 5, "any2f") == 0 | |
13045 | || strcmp (str + strlen (str) - 5, "any2t") == 0) | |
13046 | && (regno & 1) != 0) | |
13047 | as_warn (_("Condition code register should be even for %s, " | |
13048 | "was %d"), | |
13049 | str, regno); | |
13050 | if ((strcmp (str + strlen (str) - 5, "any4f") == 0 | |
13051 | || strcmp (str + strlen (str) - 5, "any4t") == 0) | |
13052 | && (regno & 3) != 0) | |
13053 | as_warn (_("Condition code register should be 0 or 4 for %s, " | |
13054 | "was %d"), | |
13055 | str, regno); | |
13056 | if (*args == 'N') | |
13057 | INSERT_OPERAND (mips_opts.micromips, BCC, *ip, regno); | |
13058 | else | |
13059 | INSERT_OPERAND (mips_opts.micromips, CCC, *ip, regno); | |
13060 | continue; | |
13061 | ||
13062 | case 'H': | |
13063 | if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X')) | |
13064 | s += 2; | |
13065 | if (ISDIGIT (*s)) | |
13066 | { | |
13067 | c = 0; | |
13068 | do | |
13069 | { | |
13070 | c *= 10; | |
13071 | c += *s - '0'; | |
13072 | ++s; | |
13073 | } | |
13074 | while (ISDIGIT (*s)); | |
13075 | } | |
13076 | else | |
13077 | c = 8; /* Invalid sel value. */ | |
13078 | ||
13079 | if (c > 7) | |
13080 | as_bad (_("Invalid coprocessor sub-selection value (0-7)")); | |
13081 | INSERT_OPERAND (mips_opts.micromips, SEL, *ip, c); | |
13082 | continue; | |
13083 | ||
13084 | case 'e': | |
13085 | gas_assert (!mips_opts.micromips); | |
13086 | /* Must be at least one digit. */ | |
13087 | my_getExpression (&imm_expr, s); | |
13088 | check_absolute_expr (ip, &imm_expr); | |
13089 | ||
13090 | if ((unsigned long) imm_expr.X_add_number | |
13091 | > (unsigned long) OP_MASK_VECBYTE) | |
13092 | { | |
13093 | as_bad (_("bad byte vector index (%ld)"), | |
13094 | (long) imm_expr.X_add_number); | |
13095 | imm_expr.X_add_number = 0; | |
13096 | } | |
13097 | ||
13098 | INSERT_OPERAND (0, VECBYTE, *ip, imm_expr.X_add_number); | |
13099 | imm_expr.X_op = O_absent; | |
13100 | s = expr_end; | |
13101 | continue; | |
13102 | ||
13103 | case '%': | |
13104 | gas_assert (!mips_opts.micromips); | |
13105 | my_getExpression (&imm_expr, s); | |
13106 | check_absolute_expr (ip, &imm_expr); | |
13107 | ||
13108 | if ((unsigned long) imm_expr.X_add_number | |
13109 | > (unsigned long) OP_MASK_VECALIGN) | |
13110 | { | |
13111 | as_bad (_("bad byte vector index (%ld)"), | |
13112 | (long) imm_expr.X_add_number); | |
13113 | imm_expr.X_add_number = 0; | |
13114 | } | |
13115 | ||
13116 | INSERT_OPERAND (0, VECALIGN, *ip, imm_expr.X_add_number); | |
13117 | imm_expr.X_op = O_absent; | |
13118 | s = expr_end; | |
13119 | continue; | |
13120 | ||
13121 | case 'm': /* Opcode extension character. */ | |
13122 | gas_assert (mips_opts.micromips); | |
13123 | c = *++args; | |
13124 | switch (c) | |
13125 | { | |
13126 | case 'r': | |
13127 | if (strncmp (s, "$pc", 3) == 0) | |
13128 | { | |
13129 | s += 3; | |
13130 | continue; | |
13131 | } | |
13132 | break; | |
13133 | ||
13134 | case 'a': | |
13135 | case 'b': | |
13136 | case 'c': | |
13137 | case 'd': | |
13138 | case 'e': | |
13139 | case 'f': | |
13140 | case 'g': | |
13141 | case 'h': | |
13142 | case 'i': | |
13143 | case 'j': | |
13144 | case 'l': | |
13145 | case 'm': | |
13146 | case 'n': | |
13147 | case 'p': | |
13148 | case 'q': | |
13149 | case 's': | |
13150 | case 't': | |
13151 | case 'x': | |
13152 | case 'y': | |
13153 | case 'z': | |
13154 | s_reset = s; | |
13155 | ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no); | |
13156 | if (regno == AT && mips_opts.at) | |
13157 | { | |
13158 | if (mips_opts.at == ATREG) | |
13159 | as_warn (_("Used $at without \".set noat\"")); | |
13160 | else | |
13161 | as_warn (_("Used $%u with \".set at=$%u\""), | |
13162 | regno, mips_opts.at); | |
13163 | } | |
13164 | if (!ok) | |
13165 | { | |
13166 | if (c == 'c') | |
13167 | { | |
13168 | gas_assert (args[1] == ','); | |
13169 | regno = lastregno; | |
13170 | ++args; | |
13171 | } | |
13172 | else if (c == 't') | |
13173 | { | |
13174 | gas_assert (args[1] == ','); | |
13175 | ++args; | |
13176 | continue; /* Nothing to do. */ | |
13177 | } | |
13178 | else | |
13179 | break; | |
13180 | } | |
13181 | ||
13182 | if (c == 'j' && !strncmp (ip->insn_mo->name, "jalr", 4)) | |
13183 | { | |
13184 | if (regno == lastregno) | |
13185 | { | |
13186 | insn_error | |
13187 | = _("Source and destination must be different"); | |
13188 | continue; | |
13189 | } | |
13190 | if (regno == 31 && lastregno == 0xffffffff) | |
13191 | { | |
13192 | insn_error | |
13193 | = _("A destination register must be supplied"); | |
13194 | continue; | |
13195 | } | |
13196 | } | |
13197 | ||
13198 | if (*s == ' ') | |
13199 | ++s; | |
13200 | if (args[1] != *s) | |
13201 | { | |
13202 | if (c == 'e') | |
13203 | { | |
13204 | gas_assert (args[1] == ','); | |
13205 | regno = lastregno; | |
13206 | s = s_reset; | |
13207 | ++args; | |
13208 | } | |
13209 | else if (c == 't') | |
13210 | { | |
13211 | gas_assert (args[1] == ','); | |
13212 | s = s_reset; | |
13213 | ++args; | |
13214 | continue; /* Nothing to do. */ | |
13215 | } | |
13216 | } | |
13217 | ||
13218 | /* Make sure regno is the same as lastregno. */ | |
13219 | if (c == 't' && regno != lastregno) | |
13220 | break; | |
13221 | ||
13222 | /* Make sure regno is the same as destregno. */ | |
13223 | if (c == 'x' && regno != destregno) | |
13224 | break; | |
13225 | ||
13226 | /* We need to save regno, before regno maps to the | |
13227 | microMIPS register encoding. */ | |
13228 | lastregno = regno; | |
13229 | ||
13230 | if (c == 'f') | |
13231 | destregno = regno; | |
13232 | ||
13233 | switch (c) | |
13234 | { | |
13235 | case 'a': | |
13236 | if (regno != GP) | |
13237 | regno = ILLEGAL_REG; | |
13238 | break; | |
13239 | ||
13240 | case 'b': | |
13241 | regno = mips32_to_micromips_reg_b_map[regno]; | |
13242 | break; | |
13243 | ||
13244 | case 'c': | |
13245 | regno = mips32_to_micromips_reg_c_map[regno]; | |
13246 | break; | |
13247 | ||
13248 | case 'd': | |
13249 | regno = mips32_to_micromips_reg_d_map[regno]; | |
13250 | break; | |
13251 | ||
13252 | case 'e': | |
13253 | regno = mips32_to_micromips_reg_e_map[regno]; | |
13254 | break; | |
13255 | ||
13256 | case 'f': | |
13257 | regno = mips32_to_micromips_reg_f_map[regno]; | |
13258 | break; | |
13259 | ||
13260 | case 'g': | |
13261 | regno = mips32_to_micromips_reg_g_map[regno]; | |
13262 | break; | |
13263 | ||
13264 | case 'h': | |
13265 | regno = mips32_to_micromips_reg_h_map[regno]; | |
13266 | break; | |
13267 | ||
13268 | case 'i': | |
13269 | switch (EXTRACT_OPERAND (1, MI, *ip)) | |
13270 | { | |
13271 | case 4: | |
13272 | if (regno == 21) | |
13273 | regno = 3; | |
13274 | else if (regno == 22) | |
13275 | regno = 4; | |
13276 | else if (regno == 5) | |
13277 | regno = 5; | |
13278 | else if (regno == 6) | |
13279 | regno = 6; | |
13280 | else if (regno == 7) | |
13281 | regno = 7; | |
13282 | else | |
13283 | regno = ILLEGAL_REG; | |
13284 | break; | |
13285 | ||
13286 | case 5: | |
13287 | if (regno == 6) | |
13288 | regno = 0; | |
13289 | else if (regno == 7) | |
13290 | regno = 1; | |
13291 | else | |
13292 | regno = ILLEGAL_REG; | |
13293 | break; | |
13294 | ||
13295 | case 6: | |
13296 | if (regno == 7) | |
13297 | regno = 2; | |
13298 | else | |
13299 | regno = ILLEGAL_REG; | |
13300 | break; | |
13301 | ||
13302 | default: | |
13303 | regno = ILLEGAL_REG; | |
13304 | break; | |
13305 | } | |
13306 | break; | |
13307 | ||
13308 | case 'l': | |
13309 | regno = mips32_to_micromips_reg_l_map[regno]; | |
13310 | break; | |
13311 | ||
13312 | case 'm': | |
13313 | regno = mips32_to_micromips_reg_m_map[regno]; | |
13314 | break; | |
13315 | ||
13316 | case 'n': | |
13317 | regno = mips32_to_micromips_reg_n_map[regno]; | |
13318 | break; | |
13319 | ||
13320 | case 'q': | |
13321 | regno = mips32_to_micromips_reg_q_map[regno]; | |
13322 | break; | |
13323 | ||
13324 | case 's': | |
13325 | if (regno != SP) | |
13326 | regno = ILLEGAL_REG; | |
13327 | break; | |
13328 | ||
13329 | case 'y': | |
13330 | if (regno != 31) | |
13331 | regno = ILLEGAL_REG; | |
13332 | break; | |
13333 | ||
13334 | case 'z': | |
13335 | if (regno != ZERO) | |
13336 | regno = ILLEGAL_REG; | |
13337 | break; | |
13338 | ||
13339 | case 'j': /* Do nothing. */ | |
13340 | case 'p': | |
13341 | case 't': | |
13342 | case 'x': | |
13343 | break; | |
13344 | ||
13345 | default: | |
b37df7c4 | 13346 | abort (); |
df58fc94 RS |
13347 | } |
13348 | ||
13349 | if (regno == ILLEGAL_REG) | |
13350 | break; | |
13351 | ||
13352 | switch (c) | |
13353 | { | |
13354 | case 'b': | |
13355 | INSERT_OPERAND (1, MB, *ip, regno); | |
13356 | break; | |
13357 | ||
13358 | case 'c': | |
13359 | INSERT_OPERAND (1, MC, *ip, regno); | |
13360 | break; | |
13361 | ||
13362 | case 'd': | |
13363 | INSERT_OPERAND (1, MD, *ip, regno); | |
13364 | break; | |
13365 | ||
13366 | case 'e': | |
13367 | INSERT_OPERAND (1, ME, *ip, regno); | |
13368 | break; | |
13369 | ||
13370 | case 'f': | |
13371 | INSERT_OPERAND (1, MF, *ip, regno); | |
13372 | break; | |
13373 | ||
13374 | case 'g': | |
13375 | INSERT_OPERAND (1, MG, *ip, regno); | |
13376 | break; | |
13377 | ||
13378 | case 'h': | |
13379 | INSERT_OPERAND (1, MH, *ip, regno); | |
13380 | break; | |
13381 | ||
13382 | case 'i': | |
13383 | INSERT_OPERAND (1, MI, *ip, regno); | |
13384 | break; | |
13385 | ||
13386 | case 'j': | |
13387 | INSERT_OPERAND (1, MJ, *ip, regno); | |
13388 | break; | |
13389 | ||
13390 | case 'l': | |
13391 | INSERT_OPERAND (1, ML, *ip, regno); | |
13392 | break; | |
13393 | ||
13394 | case 'm': | |
13395 | INSERT_OPERAND (1, MM, *ip, regno); | |
13396 | break; | |
13397 | ||
13398 | case 'n': | |
13399 | INSERT_OPERAND (1, MN, *ip, regno); | |
13400 | break; | |
13401 | ||
13402 | case 'p': | |
13403 | INSERT_OPERAND (1, MP, *ip, regno); | |
13404 | break; | |
13405 | ||
13406 | case 'q': | |
13407 | INSERT_OPERAND (1, MQ, *ip, regno); | |
13408 | break; | |
13409 | ||
13410 | case 'a': /* Do nothing. */ | |
13411 | case 's': /* Do nothing. */ | |
13412 | case 't': /* Do nothing. */ | |
13413 | case 'x': /* Do nothing. */ | |
13414 | case 'y': /* Do nothing. */ | |
13415 | case 'z': /* Do nothing. */ | |
13416 | break; | |
13417 | ||
13418 | default: | |
b37df7c4 | 13419 | abort (); |
df58fc94 RS |
13420 | } |
13421 | continue; | |
13422 | ||
13423 | case 'A': | |
13424 | { | |
13425 | bfd_reloc_code_real_type r[3]; | |
13426 | expressionS ep; | |
13427 | int imm; | |
13428 | ||
13429 | /* Check whether there is only a single bracketed | |
13430 | expression left. If so, it must be the base register | |
13431 | and the constant must be zero. */ | |
13432 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
13433 | { | |
13434 | INSERT_OPERAND (1, IMMA, *ip, 0); | |
13435 | continue; | |
13436 | } | |
13437 | ||
13438 | if (my_getSmallExpression (&ep, r, s) > 0 | |
13439 | || !expr_const_in_range (&ep, -64, 64, 2)) | |
13440 | break; | |
13441 | ||
13442 | imm = ep.X_add_number >> 2; | |
13443 | INSERT_OPERAND (1, IMMA, *ip, imm); | |
13444 | } | |
13445 | s = expr_end; | |
13446 | continue; | |
13447 | ||
13448 | case 'B': | |
13449 | { | |
13450 | bfd_reloc_code_real_type r[3]; | |
13451 | expressionS ep; | |
13452 | int imm; | |
13453 | ||
13454 | if (my_getSmallExpression (&ep, r, s) > 0 | |
13455 | || ep.X_op != O_constant) | |
13456 | break; | |
13457 | ||
13458 | for (imm = 0; imm < 8; imm++) | |
13459 | if (micromips_imm_b_map[imm] == ep.X_add_number) | |
13460 | break; | |
13461 | if (imm >= 8) | |
13462 | break; | |
13463 | ||
13464 | INSERT_OPERAND (1, IMMB, *ip, imm); | |
13465 | } | |
13466 | s = expr_end; | |
13467 | continue; | |
13468 | ||
13469 | case 'C': | |
13470 | { | |
13471 | bfd_reloc_code_real_type r[3]; | |
13472 | expressionS ep; | |
13473 | int imm; | |
13474 | ||
13475 | if (my_getSmallExpression (&ep, r, s) > 0 | |
13476 | || ep.X_op != O_constant) | |
13477 | break; | |
13478 | ||
13479 | for (imm = 0; imm < 16; imm++) | |
13480 | if (micromips_imm_c_map[imm] == ep.X_add_number) | |
13481 | break; | |
13482 | if (imm >= 16) | |
13483 | break; | |
13484 | ||
13485 | INSERT_OPERAND (1, IMMC, *ip, imm); | |
13486 | } | |
13487 | s = expr_end; | |
13488 | continue; | |
13489 | ||
13490 | case 'D': /* pc relative offset */ | |
13491 | case 'E': /* pc relative offset */ | |
13492 | my_getExpression (&offset_expr, s); | |
13493 | if (offset_expr.X_op == O_register) | |
13494 | break; | |
13495 | ||
40209cad MR |
13496 | if (!forced_insn_length) |
13497 | *offset_reloc = (int) BFD_RELOC_UNUSED + c; | |
13498 | else if (c == 'D') | |
13499 | *offset_reloc = BFD_RELOC_MICROMIPS_10_PCREL_S1; | |
13500 | else | |
13501 | *offset_reloc = BFD_RELOC_MICROMIPS_7_PCREL_S1; | |
df58fc94 RS |
13502 | s = expr_end; |
13503 | continue; | |
13504 | ||
13505 | case 'F': | |
13506 | { | |
13507 | bfd_reloc_code_real_type r[3]; | |
13508 | expressionS ep; | |
13509 | int imm; | |
13510 | ||
13511 | if (my_getSmallExpression (&ep, r, s) > 0 | |
13512 | || !expr_const_in_range (&ep, 0, 16, 0)) | |
13513 | break; | |
13514 | ||
13515 | imm = ep.X_add_number; | |
13516 | INSERT_OPERAND (1, IMMF, *ip, imm); | |
13517 | } | |
13518 | s = expr_end; | |
13519 | continue; | |
13520 | ||
13521 | case 'G': | |
13522 | { | |
13523 | bfd_reloc_code_real_type r[3]; | |
13524 | expressionS ep; | |
13525 | int imm; | |
13526 | ||
13527 | /* Check whether there is only a single bracketed | |
13528 | expression left. If so, it must be the base register | |
13529 | and the constant must be zero. */ | |
13530 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
13531 | { | |
13532 | INSERT_OPERAND (1, IMMG, *ip, 0); | |
13533 | continue; | |
13534 | } | |
13535 | ||
13536 | if (my_getSmallExpression (&ep, r, s) > 0 | |
13537 | || !expr_const_in_range (&ep, -1, 15, 0)) | |
13538 | break; | |
13539 | ||
13540 | imm = ep.X_add_number & 15; | |
13541 | INSERT_OPERAND (1, IMMG, *ip, imm); | |
13542 | } | |
13543 | s = expr_end; | |
13544 | continue; | |
13545 | ||
13546 | case 'H': | |
13547 | { | |
13548 | bfd_reloc_code_real_type r[3]; | |
13549 | expressionS ep; | |
13550 | int imm; | |
13551 | ||
13552 | /* Check whether there is only a single bracketed | |
13553 | expression left. If so, it must be the base register | |
13554 | and the constant must be zero. */ | |
13555 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
13556 | { | |
13557 | INSERT_OPERAND (1, IMMH, *ip, 0); | |
13558 | continue; | |
13559 | } | |
13560 | ||
13561 | if (my_getSmallExpression (&ep, r, s) > 0 | |
13562 | || !expr_const_in_range (&ep, 0, 16, 1)) | |
13563 | break; | |
13564 | ||
13565 | imm = ep.X_add_number >> 1; | |
13566 | INSERT_OPERAND (1, IMMH, *ip, imm); | |
13567 | } | |
13568 | s = expr_end; | |
13569 | continue; | |
13570 | ||
13571 | case 'I': | |
13572 | { | |
13573 | bfd_reloc_code_real_type r[3]; | |
13574 | expressionS ep; | |
13575 | int imm; | |
13576 | ||
13577 | if (my_getSmallExpression (&ep, r, s) > 0 | |
13578 | || !expr_const_in_range (&ep, -1, 127, 0)) | |
13579 | break; | |
13580 | ||
13581 | imm = ep.X_add_number & 127; | |
13582 | INSERT_OPERAND (1, IMMI, *ip, imm); | |
13583 | } | |
13584 | s = expr_end; | |
13585 | continue; | |
13586 | ||
13587 | case 'J': | |
13588 | { | |
13589 | bfd_reloc_code_real_type r[3]; | |
13590 | expressionS ep; | |
13591 | int imm; | |
13592 | ||
13593 | /* Check whether there is only a single bracketed | |
13594 | expression left. If so, it must be the base register | |
13595 | and the constant must be zero. */ | |
13596 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
13597 | { | |
13598 | INSERT_OPERAND (1, IMMJ, *ip, 0); | |
13599 | continue; | |
13600 | } | |
13601 | ||
13602 | if (my_getSmallExpression (&ep, r, s) > 0 | |
13603 | || !expr_const_in_range (&ep, 0, 16, 2)) | |
13604 | break; | |
13605 | ||
13606 | imm = ep.X_add_number >> 2; | |
13607 | INSERT_OPERAND (1, IMMJ, *ip, imm); | |
13608 | } | |
13609 | s = expr_end; | |
13610 | continue; | |
13611 | ||
13612 | case 'L': | |
13613 | { | |
13614 | bfd_reloc_code_real_type r[3]; | |
13615 | expressionS ep; | |
13616 | int imm; | |
13617 | ||
13618 | /* Check whether there is only a single bracketed | |
13619 | expression left. If so, it must be the base register | |
13620 | and the constant must be zero. */ | |
13621 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
13622 | { | |
13623 | INSERT_OPERAND (1, IMML, *ip, 0); | |
13624 | continue; | |
13625 | } | |
13626 | ||
13627 | if (my_getSmallExpression (&ep, r, s) > 0 | |
13628 | || !expr_const_in_range (&ep, 0, 16, 0)) | |
13629 | break; | |
13630 | ||
13631 | imm = ep.X_add_number; | |
13632 | INSERT_OPERAND (1, IMML, *ip, imm); | |
13633 | } | |
13634 | s = expr_end; | |
13635 | continue; | |
13636 | ||
13637 | case 'M': | |
13638 | { | |
13639 | bfd_reloc_code_real_type r[3]; | |
13640 | expressionS ep; | |
13641 | int imm; | |
13642 | ||
13643 | if (my_getSmallExpression (&ep, r, s) > 0 | |
13644 | || !expr_const_in_range (&ep, 1, 9, 0)) | |
13645 | break; | |
13646 | ||
13647 | imm = ep.X_add_number & 7; | |
13648 | INSERT_OPERAND (1, IMMM, *ip, imm); | |
13649 | } | |
13650 | s = expr_end; | |
13651 | continue; | |
13652 | ||
13653 | case 'N': /* Register list for lwm and swm. */ | |
13654 | { | |
13655 | /* A comma-separated list of registers and/or | |
13656 | dash-separated contiguous ranges including | |
13657 | both ra and a set of one or more registers | |
13658 | starting at s0 up to s3 which have to be | |
13659 | consecutive, e.g.: | |
13660 | ||
13661 | s0, ra | |
13662 | s0, s1, ra, s2, s3 | |
13663 | s0-s2, ra | |
13664 | ||
13665 | and any permutations of these. */ | |
13666 | unsigned int reglist; | |
13667 | int imm; | |
13668 | ||
13669 | if (!reglist_lookup (&s, RTYPE_NUM | RTYPE_GP, ®list)) | |
13670 | break; | |
13671 | ||
13672 | if ((reglist & 0xfff1ffff) != 0x80010000) | |
13673 | break; | |
13674 | ||
13675 | reglist = (reglist >> 17) & 7; | |
13676 | reglist += 1; | |
13677 | if ((reglist & -reglist) != reglist) | |
13678 | break; | |
252b5132 | 13679 | |
df58fc94 RS |
13680 | imm = ffs (reglist) - 1; |
13681 | INSERT_OPERAND (1, IMMN, *ip, imm); | |
13682 | } | |
13683 | continue; | |
252b5132 | 13684 | |
df58fc94 RS |
13685 | case 'O': /* sdbbp 4-bit code. */ |
13686 | { | |
13687 | bfd_reloc_code_real_type r[3]; | |
13688 | expressionS ep; | |
13689 | int imm; | |
13690 | ||
13691 | if (my_getSmallExpression (&ep, r, s) > 0 | |
13692 | || !expr_const_in_range (&ep, 0, 16, 0)) | |
13693 | break; | |
13694 | ||
13695 | imm = ep.X_add_number; | |
13696 | INSERT_OPERAND (1, IMMO, *ip, imm); | |
252b5132 | 13697 | } |
df58fc94 RS |
13698 | s = expr_end; |
13699 | continue; | |
252b5132 | 13700 | |
df58fc94 RS |
13701 | case 'P': |
13702 | { | |
13703 | bfd_reloc_code_real_type r[3]; | |
13704 | expressionS ep; | |
13705 | int imm; | |
5e0116d5 | 13706 | |
df58fc94 RS |
13707 | if (my_getSmallExpression (&ep, r, s) > 0 |
13708 | || !expr_const_in_range (&ep, 0, 32, 2)) | |
13709 | break; | |
5e0116d5 | 13710 | |
df58fc94 RS |
13711 | imm = ep.X_add_number >> 2; |
13712 | INSERT_OPERAND (1, IMMP, *ip, imm); | |
13713 | } | |
13714 | s = expr_end; | |
13715 | continue; | |
5e0116d5 | 13716 | |
df58fc94 RS |
13717 | case 'Q': |
13718 | { | |
13719 | bfd_reloc_code_real_type r[3]; | |
13720 | expressionS ep; | |
13721 | int imm; | |
5e0116d5 | 13722 | |
df58fc94 RS |
13723 | if (my_getSmallExpression (&ep, r, s) > 0 |
13724 | || !expr_const_in_range (&ep, -0x400000, 0x400000, 2)) | |
13725 | break; | |
252b5132 | 13726 | |
df58fc94 RS |
13727 | imm = ep.X_add_number >> 2; |
13728 | INSERT_OPERAND (1, IMMQ, *ip, imm); | |
13729 | } | |
13730 | s = expr_end; | |
13731 | continue; | |
4614d845 | 13732 | |
df58fc94 RS |
13733 | case 'U': |
13734 | { | |
13735 | bfd_reloc_code_real_type r[3]; | |
13736 | expressionS ep; | |
13737 | int imm; | |
13738 | ||
13739 | /* Check whether there is only a single bracketed | |
13740 | expression left. If so, it must be the base register | |
13741 | and the constant must be zero. */ | |
13742 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
13743 | { | |
13744 | INSERT_OPERAND (1, IMMU, *ip, 0); | |
13745 | continue; | |
13746 | } | |
13747 | ||
13748 | if (my_getSmallExpression (&ep, r, s) > 0 | |
13749 | || !expr_const_in_range (&ep, 0, 32, 2)) | |
13750 | break; | |
13751 | ||
13752 | imm = ep.X_add_number >> 2; | |
13753 | INSERT_OPERAND (1, IMMU, *ip, imm); | |
13754 | } | |
13755 | s = expr_end; | |
5e0116d5 | 13756 | continue; |
252b5132 | 13757 | |
df58fc94 RS |
13758 | case 'W': |
13759 | { | |
13760 | bfd_reloc_code_real_type r[3]; | |
13761 | expressionS ep; | |
13762 | int imm; | |
252b5132 | 13763 | |
df58fc94 RS |
13764 | if (my_getSmallExpression (&ep, r, s) > 0 |
13765 | || !expr_const_in_range (&ep, 0, 64, 2)) | |
13766 | break; | |
252b5132 | 13767 | |
df58fc94 RS |
13768 | imm = ep.X_add_number >> 2; |
13769 | INSERT_OPERAND (1, IMMW, *ip, imm); | |
13770 | } | |
13771 | s = expr_end; | |
13772 | continue; | |
252b5132 | 13773 | |
df58fc94 RS |
13774 | case 'X': |
13775 | { | |
13776 | bfd_reloc_code_real_type r[3]; | |
13777 | expressionS ep; | |
13778 | int imm; | |
252b5132 | 13779 | |
df58fc94 RS |
13780 | if (my_getSmallExpression (&ep, r, s) > 0 |
13781 | || !expr_const_in_range (&ep, -8, 8, 0)) | |
13782 | break; | |
252b5132 | 13783 | |
df58fc94 RS |
13784 | imm = ep.X_add_number; |
13785 | INSERT_OPERAND (1, IMMX, *ip, imm); | |
13786 | } | |
13787 | s = expr_end; | |
13788 | continue; | |
252b5132 | 13789 | |
df58fc94 RS |
13790 | case 'Y': |
13791 | { | |
13792 | bfd_reloc_code_real_type r[3]; | |
13793 | expressionS ep; | |
13794 | int imm; | |
156c2f8b | 13795 | |
df58fc94 RS |
13796 | if (my_getSmallExpression (&ep, r, s) > 0 |
13797 | || expr_const_in_range (&ep, -2, 2, 2) | |
13798 | || !expr_const_in_range (&ep, -258, 258, 2)) | |
13799 | break; | |
156c2f8b | 13800 | |
df58fc94 RS |
13801 | imm = ep.X_add_number >> 2; |
13802 | imm = ((imm >> 1) & ~0xff) | (imm & 0xff); | |
13803 | INSERT_OPERAND (1, IMMY, *ip, imm); | |
13804 | } | |
13805 | s = expr_end; | |
13806 | continue; | |
60b63b72 | 13807 | |
df58fc94 RS |
13808 | case 'Z': |
13809 | { | |
13810 | bfd_reloc_code_real_type r[3]; | |
13811 | expressionS ep; | |
13812 | ||
13813 | if (my_getSmallExpression (&ep, r, s) > 0 | |
13814 | || !expr_const_in_range (&ep, 0, 1, 0)) | |
13815 | break; | |
13816 | } | |
13817 | s = expr_end; | |
13818 | continue; | |
13819 | ||
13820 | default: | |
13821 | as_bad (_("Internal error: bad microMIPS opcode " | |
13822 | "(unknown extension operand type `m%c'): %s %s"), | |
13823 | *args, insn->name, insn->args); | |
13824 | /* Further processing is fruitless. */ | |
13825 | return; | |
60b63b72 | 13826 | } |
df58fc94 | 13827 | break; |
60b63b72 | 13828 | |
df58fc94 RS |
13829 | case 'n': /* Register list for 32-bit lwm and swm. */ |
13830 | gas_assert (mips_opts.micromips); | |
13831 | { | |
13832 | /* A comma-separated list of registers and/or | |
13833 | dash-separated contiguous ranges including | |
13834 | at least one of ra and a set of one or more | |
13835 | registers starting at s0 up to s7 and then | |
13836 | s8 which have to be consecutive, e.g.: | |
13837 | ||
13838 | ra | |
13839 | s0 | |
13840 | ra, s0, s1, s2 | |
13841 | s0-s8 | |
13842 | s0-s5, ra | |
13843 | ||
13844 | and any permutations of these. */ | |
13845 | unsigned int reglist; | |
13846 | int imm; | |
13847 | int ra; | |
13848 | ||
13849 | if (!reglist_lookup (&s, RTYPE_NUM | RTYPE_GP, ®list)) | |
13850 | break; | |
13851 | ||
13852 | if ((reglist & 0x3f00ffff) != 0) | |
13853 | break; | |
13854 | ||
13855 | ra = (reglist >> 27) & 0x10; | |
13856 | reglist = ((reglist >> 22) & 0x100) | ((reglist >> 16) & 0xff); | |
13857 | reglist += 1; | |
13858 | if ((reglist & -reglist) != reglist) | |
13859 | break; | |
13860 | ||
13861 | imm = (ffs (reglist) - 1) | ra; | |
13862 | INSERT_OPERAND (1, RT, *ip, imm); | |
13863 | imm_expr.X_op = O_absent; | |
13864 | } | |
60b63b72 RS |
13865 | continue; |
13866 | ||
df58fc94 RS |
13867 | case '|': /* 4-bit trap code. */ |
13868 | gas_assert (mips_opts.micromips); | |
60b63b72 RS |
13869 | my_getExpression (&imm_expr, s); |
13870 | check_absolute_expr (ip, &imm_expr); | |
60b63b72 | 13871 | if ((unsigned long) imm_expr.X_add_number |
df58fc94 RS |
13872 | > MICROMIPSOP_MASK_TRAP) |
13873 | as_bad (_("Trap code (%lu) for %s not in 0..15 range"), | |
13874 | (unsigned long) imm_expr.X_add_number, | |
13875 | ip->insn_mo->name); | |
13876 | INSERT_OPERAND (1, TRAP, *ip, imm_expr.X_add_number); | |
60b63b72 RS |
13877 | imm_expr.X_op = O_absent; |
13878 | s = expr_end; | |
13879 | continue; | |
13880 | ||
252b5132 | 13881 | default: |
f71d0d44 | 13882 | as_bad (_("Bad char = '%c'\n"), *args); |
b37df7c4 | 13883 | abort (); |
252b5132 RH |
13884 | } |
13885 | break; | |
13886 | } | |
13887 | /* Args don't match. */ | |
df58fc94 RS |
13888 | s = argsStart; |
13889 | insn_error = _("Illegal operands"); | |
13890 | if (insn + 1 < past && !strcmp (insn->name, insn[1].name)) | |
252b5132 RH |
13891 | { |
13892 | ++insn; | |
252b5132 RH |
13893 | continue; |
13894 | } | |
df58fc94 RS |
13895 | else if (wrong_delay_slot_insns && need_delay_slot_ok) |
13896 | { | |
13897 | gas_assert (firstinsn); | |
13898 | need_delay_slot_ok = FALSE; | |
13899 | past = insn + 1; | |
13900 | insn = firstinsn; | |
13901 | continue; | |
13902 | } | |
252b5132 RH |
13903 | return; |
13904 | } | |
13905 | } | |
13906 | ||
0499d65b TS |
13907 | #define SKIP_SPACE_TABS(S) { while (*(S) == ' ' || *(S) == '\t') ++(S); } |
13908 | ||
252b5132 RH |
13909 | /* This routine assembles an instruction into its binary format when |
13910 | assembling for the mips16. As a side effect, it sets one of the | |
df58fc94 RS |
13911 | global variables imm_reloc or offset_reloc to the type of relocation |
13912 | to do if one of the operands is an address expression. It also sets | |
13913 | forced_insn_length to the resulting instruction size in bytes if the | |
13914 | user explicitly requested a small or extended instruction. */ | |
252b5132 RH |
13915 | |
13916 | static void | |
17a2f251 | 13917 | mips16_ip (char *str, struct mips_cl_insn *ip) |
252b5132 RH |
13918 | { |
13919 | char *s; | |
13920 | const char *args; | |
13921 | struct mips_opcode *insn; | |
13922 | char *argsstart; | |
13923 | unsigned int regno; | |
13924 | unsigned int lastregno = 0; | |
13925 | char *s_reset; | |
d6f16593 | 13926 | size_t i; |
252b5132 RH |
13927 | |
13928 | insn_error = NULL; | |
13929 | ||
df58fc94 | 13930 | forced_insn_length = 0; |
252b5132 | 13931 | |
3882b010 | 13932 | for (s = str; ISLOWER (*s); ++s) |
252b5132 RH |
13933 | ; |
13934 | switch (*s) | |
13935 | { | |
13936 | case '\0': | |
13937 | break; | |
13938 | ||
13939 | case ' ': | |
13940 | *s++ = '\0'; | |
13941 | break; | |
13942 | ||
13943 | case '.': | |
13944 | if (s[1] == 't' && s[2] == ' ') | |
13945 | { | |
13946 | *s = '\0'; | |
df58fc94 | 13947 | forced_insn_length = 2; |
252b5132 RH |
13948 | s += 3; |
13949 | break; | |
13950 | } | |
13951 | else if (s[1] == 'e' && s[2] == ' ') | |
13952 | { | |
13953 | *s = '\0'; | |
df58fc94 | 13954 | forced_insn_length = 4; |
252b5132 RH |
13955 | s += 3; |
13956 | break; | |
13957 | } | |
13958 | /* Fall through. */ | |
13959 | default: | |
13960 | insn_error = _("unknown opcode"); | |
13961 | return; | |
13962 | } | |
13963 | ||
df58fc94 RS |
13964 | if (mips_opts.noautoextend && !forced_insn_length) |
13965 | forced_insn_length = 2; | |
252b5132 RH |
13966 | |
13967 | if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL) | |
13968 | { | |
13969 | insn_error = _("unrecognized opcode"); | |
13970 | return; | |
13971 | } | |
13972 | ||
13973 | argsstart = s; | |
13974 | for (;;) | |
13975 | { | |
9b3f89ee TS |
13976 | bfd_boolean ok; |
13977 | ||
9c2799c2 | 13978 | gas_assert (strcmp (insn->name, str) == 0); |
252b5132 | 13979 | |
037b32b9 | 13980 | ok = is_opcode_valid_16 (insn); |
9b3f89ee TS |
13981 | if (! ok) |
13982 | { | |
13983 | if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] | |
13984 | && strcmp (insn->name, insn[1].name) == 0) | |
13985 | { | |
13986 | ++insn; | |
13987 | continue; | |
13988 | } | |
13989 | else | |
13990 | { | |
13991 | if (!insn_error) | |
13992 | { | |
13993 | static char buf[100]; | |
13994 | sprintf (buf, | |
7bd942df | 13995 | _("Opcode not supported on this processor: %s (%s)"), |
9b3f89ee TS |
13996 | mips_cpu_info_from_arch (mips_opts.arch)->name, |
13997 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
13998 | insn_error = buf; | |
13999 | } | |
14000 | return; | |
14001 | } | |
14002 | } | |
14003 | ||
1e915849 | 14004 | create_insn (ip, insn); |
252b5132 | 14005 | imm_expr.X_op = O_absent; |
f6688943 TS |
14006 | imm_reloc[0] = BFD_RELOC_UNUSED; |
14007 | imm_reloc[1] = BFD_RELOC_UNUSED; | |
14008 | imm_reloc[2] = BFD_RELOC_UNUSED; | |
5f74bc13 | 14009 | imm2_expr.X_op = O_absent; |
252b5132 | 14010 | offset_expr.X_op = O_absent; |
f6688943 TS |
14011 | offset_reloc[0] = BFD_RELOC_UNUSED; |
14012 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
14013 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
14014 | for (args = insn->args; 1; ++args) |
14015 | { | |
14016 | int c; | |
14017 | ||
14018 | if (*s == ' ') | |
14019 | ++s; | |
14020 | ||
14021 | /* In this switch statement we call break if we did not find | |
14022 | a match, continue if we did find a match, or return if we | |
14023 | are done. */ | |
14024 | ||
14025 | c = *args; | |
14026 | switch (c) | |
14027 | { | |
14028 | case '\0': | |
14029 | if (*s == '\0') | |
14030 | { | |
b886a2ab RS |
14031 | offsetT value; |
14032 | ||
252b5132 RH |
14033 | /* Stuff the immediate value in now, if we can. */ |
14034 | if (imm_expr.X_op == O_constant | |
f6688943 | 14035 | && *imm_reloc > BFD_RELOC_UNUSED |
b886a2ab RS |
14036 | && insn->pinfo != INSN_MACRO |
14037 | && calculate_reloc (*offset_reloc, | |
14038 | imm_expr.X_add_number, &value)) | |
252b5132 | 14039 | { |
c4e7957c | 14040 | mips16_immed (NULL, 0, *imm_reloc - BFD_RELOC_UNUSED, |
b886a2ab | 14041 | *offset_reloc, value, forced_insn_length, |
43c0598f | 14042 | &ip->insn_opcode); |
252b5132 | 14043 | imm_expr.X_op = O_absent; |
f6688943 | 14044 | *imm_reloc = BFD_RELOC_UNUSED; |
43c0598f | 14045 | *offset_reloc = BFD_RELOC_UNUSED; |
252b5132 RH |
14046 | } |
14047 | ||
14048 | return; | |
14049 | } | |
14050 | break; | |
14051 | ||
14052 | case ',': | |
14053 | if (*s++ == c) | |
14054 | continue; | |
14055 | s--; | |
14056 | switch (*++args) | |
14057 | { | |
14058 | case 'v': | |
bf12938e | 14059 | MIPS16_INSERT_OPERAND (RX, *ip, lastregno); |
252b5132 RH |
14060 | continue; |
14061 | case 'w': | |
bf12938e | 14062 | MIPS16_INSERT_OPERAND (RY, *ip, lastregno); |
252b5132 RH |
14063 | continue; |
14064 | } | |
14065 | break; | |
14066 | ||
14067 | case '(': | |
14068 | case ')': | |
14069 | if (*s++ == c) | |
14070 | continue; | |
14071 | break; | |
14072 | ||
14073 | case 'v': | |
14074 | case 'w': | |
14075 | if (s[0] != '$') | |
14076 | { | |
14077 | if (c == 'v') | |
bf12938e | 14078 | MIPS16_INSERT_OPERAND (RX, *ip, lastregno); |
252b5132 | 14079 | else |
bf12938e | 14080 | MIPS16_INSERT_OPERAND (RY, *ip, lastregno); |
252b5132 RH |
14081 | ++args; |
14082 | continue; | |
14083 | } | |
14084 | /* Fall through. */ | |
14085 | case 'x': | |
14086 | case 'y': | |
14087 | case 'z': | |
14088 | case 'Z': | |
14089 | case '0': | |
14090 | case 'S': | |
14091 | case 'R': | |
14092 | case 'X': | |
14093 | case 'Y': | |
707bfff6 TS |
14094 | s_reset = s; |
14095 | if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no)) | |
252b5132 | 14096 | { |
707bfff6 | 14097 | if (c == 'v' || c == 'w') |
85b51719 | 14098 | { |
707bfff6 | 14099 | if (c == 'v') |
a9e24354 | 14100 | MIPS16_INSERT_OPERAND (RX, *ip, lastregno); |
707bfff6 | 14101 | else |
a9e24354 | 14102 | MIPS16_INSERT_OPERAND (RY, *ip, lastregno); |
707bfff6 TS |
14103 | ++args; |
14104 | continue; | |
85b51719 | 14105 | } |
707bfff6 | 14106 | break; |
252b5132 RH |
14107 | } |
14108 | ||
14109 | if (*s == ' ') | |
14110 | ++s; | |
14111 | if (args[1] != *s) | |
14112 | { | |
14113 | if (c == 'v' || c == 'w') | |
14114 | { | |
14115 | regno = mips16_to_32_reg_map[lastregno]; | |
14116 | s = s_reset; | |
f9419b05 | 14117 | ++args; |
252b5132 RH |
14118 | } |
14119 | } | |
14120 | ||
14121 | switch (c) | |
14122 | { | |
14123 | case 'x': | |
14124 | case 'y': | |
14125 | case 'z': | |
14126 | case 'v': | |
14127 | case 'w': | |
14128 | case 'Z': | |
14129 | regno = mips32_to_16_reg_map[regno]; | |
14130 | break; | |
14131 | ||
14132 | case '0': | |
14133 | if (regno != 0) | |
14134 | regno = ILLEGAL_REG; | |
14135 | break; | |
14136 | ||
14137 | case 'S': | |
14138 | if (regno != SP) | |
14139 | regno = ILLEGAL_REG; | |
14140 | break; | |
14141 | ||
14142 | case 'R': | |
14143 | if (regno != RA) | |
14144 | regno = ILLEGAL_REG; | |
14145 | break; | |
14146 | ||
14147 | case 'X': | |
14148 | case 'Y': | |
741fe287 MR |
14149 | if (regno == AT && mips_opts.at) |
14150 | { | |
14151 | if (mips_opts.at == ATREG) | |
14152 | as_warn (_("used $at without \".set noat\"")); | |
14153 | else | |
14154 | as_warn (_("used $%u with \".set at=$%u\""), | |
14155 | regno, mips_opts.at); | |
14156 | } | |
252b5132 RH |
14157 | break; |
14158 | ||
14159 | default: | |
b37df7c4 | 14160 | abort (); |
252b5132 RH |
14161 | } |
14162 | ||
14163 | if (regno == ILLEGAL_REG) | |
14164 | break; | |
14165 | ||
14166 | switch (c) | |
14167 | { | |
14168 | case 'x': | |
14169 | case 'v': | |
bf12938e | 14170 | MIPS16_INSERT_OPERAND (RX, *ip, regno); |
252b5132 RH |
14171 | break; |
14172 | case 'y': | |
14173 | case 'w': | |
bf12938e | 14174 | MIPS16_INSERT_OPERAND (RY, *ip, regno); |
252b5132 RH |
14175 | break; |
14176 | case 'z': | |
bf12938e | 14177 | MIPS16_INSERT_OPERAND (RZ, *ip, regno); |
252b5132 RH |
14178 | break; |
14179 | case 'Z': | |
bf12938e | 14180 | MIPS16_INSERT_OPERAND (MOVE32Z, *ip, regno); |
252b5132 RH |
14181 | case '0': |
14182 | case 'S': | |
14183 | case 'R': | |
14184 | break; | |
14185 | case 'X': | |
bf12938e | 14186 | MIPS16_INSERT_OPERAND (REGR32, *ip, regno); |
252b5132 RH |
14187 | break; |
14188 | case 'Y': | |
14189 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); | |
bf12938e | 14190 | MIPS16_INSERT_OPERAND (REG32R, *ip, regno); |
252b5132 RH |
14191 | break; |
14192 | default: | |
b37df7c4 | 14193 | abort (); |
252b5132 RH |
14194 | } |
14195 | ||
14196 | lastregno = regno; | |
14197 | continue; | |
14198 | ||
14199 | case 'P': | |
14200 | if (strncmp (s, "$pc", 3) == 0) | |
14201 | { | |
14202 | s += 3; | |
14203 | continue; | |
14204 | } | |
14205 | break; | |
14206 | ||
252b5132 RH |
14207 | case '5': |
14208 | case 'H': | |
14209 | case 'W': | |
14210 | case 'D': | |
14211 | case 'j': | |
252b5132 RH |
14212 | case 'V': |
14213 | case 'C': | |
14214 | case 'U': | |
14215 | case 'k': | |
14216 | case 'K': | |
d6f16593 MR |
14217 | i = my_getSmallExpression (&imm_expr, imm_reloc, s); |
14218 | if (i > 0) | |
252b5132 | 14219 | { |
d6f16593 | 14220 | if (imm_expr.X_op != O_constant) |
252b5132 | 14221 | { |
df58fc94 | 14222 | forced_insn_length = 4; |
5c04167a | 14223 | ip->insn_opcode |= MIPS16_EXTEND; |
252b5132 | 14224 | } |
d6f16593 MR |
14225 | else |
14226 | { | |
14227 | /* We need to relax this instruction. */ | |
14228 | *offset_reloc = *imm_reloc; | |
14229 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; | |
14230 | } | |
14231 | s = expr_end; | |
14232 | continue; | |
252b5132 | 14233 | } |
d6f16593 MR |
14234 | *imm_reloc = BFD_RELOC_UNUSED; |
14235 | /* Fall through. */ | |
14236 | case '<': | |
14237 | case '>': | |
14238 | case '[': | |
14239 | case ']': | |
14240 | case '4': | |
14241 | case '8': | |
14242 | my_getExpression (&imm_expr, s); | |
252b5132 RH |
14243 | if (imm_expr.X_op == O_register) |
14244 | { | |
14245 | /* What we thought was an expression turned out to | |
14246 | be a register. */ | |
14247 | ||
14248 | if (s[0] == '(' && args[1] == '(') | |
14249 | { | |
14250 | /* It looks like the expression was omitted | |
14251 | before a register indirection, which means | |
14252 | that the expression is implicitly zero. We | |
14253 | still set up imm_expr, so that we handle | |
14254 | explicit extensions correctly. */ | |
14255 | imm_expr.X_op = O_constant; | |
14256 | imm_expr.X_add_number = 0; | |
f6688943 | 14257 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
14258 | continue; |
14259 | } | |
14260 | ||
14261 | break; | |
14262 | } | |
14263 | ||
14264 | /* We need to relax this instruction. */ | |
f6688943 | 14265 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
14266 | s = expr_end; |
14267 | continue; | |
14268 | ||
14269 | case 'p': | |
14270 | case 'q': | |
14271 | case 'A': | |
14272 | case 'B': | |
14273 | case 'E': | |
14274 | /* We use offset_reloc rather than imm_reloc for the PC | |
14275 | relative operands. This lets macros with both | |
14276 | immediate and address operands work correctly. */ | |
14277 | my_getExpression (&offset_expr, s); | |
14278 | ||
14279 | if (offset_expr.X_op == O_register) | |
14280 | break; | |
14281 | ||
14282 | /* We need to relax this instruction. */ | |
f6688943 | 14283 | *offset_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
14284 | s = expr_end; |
14285 | continue; | |
14286 | ||
14287 | case '6': /* break code */ | |
14288 | my_getExpression (&imm_expr, s); | |
14289 | check_absolute_expr (ip, &imm_expr); | |
14290 | if ((unsigned long) imm_expr.X_add_number > 63) | |
bf12938e RS |
14291 | as_warn (_("Invalid value for `%s' (%lu)"), |
14292 | ip->insn_mo->name, | |
14293 | (unsigned long) imm_expr.X_add_number); | |
14294 | MIPS16_INSERT_OPERAND (IMM6, *ip, imm_expr.X_add_number); | |
252b5132 RH |
14295 | imm_expr.X_op = O_absent; |
14296 | s = expr_end; | |
14297 | continue; | |
14298 | ||
14299 | case 'a': /* 26 bit address */ | |
14300 | my_getExpression (&offset_expr, s); | |
14301 | s = expr_end; | |
f6688943 | 14302 | *offset_reloc = BFD_RELOC_MIPS16_JMP; |
252b5132 RH |
14303 | ip->insn_opcode <<= 16; |
14304 | continue; | |
14305 | ||
14306 | case 'l': /* register list for entry macro */ | |
14307 | case 'L': /* register list for exit macro */ | |
14308 | { | |
14309 | int mask; | |
14310 | ||
14311 | if (c == 'l') | |
14312 | mask = 0; | |
14313 | else | |
14314 | mask = 7 << 3; | |
14315 | while (*s != '\0') | |
14316 | { | |
707bfff6 | 14317 | unsigned int freg, reg1, reg2; |
252b5132 RH |
14318 | |
14319 | while (*s == ' ' || *s == ',') | |
14320 | ++s; | |
707bfff6 | 14321 | if (reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®1)) |
252b5132 | 14322 | freg = 0; |
707bfff6 TS |
14323 | else if (reg_lookup (&s, RTYPE_FPU, ®1)) |
14324 | freg = 1; | |
252b5132 RH |
14325 | else |
14326 | { | |
707bfff6 TS |
14327 | as_bad (_("can't parse register list")); |
14328 | break; | |
252b5132 RH |
14329 | } |
14330 | if (*s == ' ') | |
14331 | ++s; | |
14332 | if (*s != '-') | |
14333 | reg2 = reg1; | |
14334 | else | |
14335 | { | |
14336 | ++s; | |
707bfff6 TS |
14337 | if (!reg_lookup (&s, freg ? RTYPE_FPU |
14338 | : (RTYPE_GP | RTYPE_NUM), ®2)) | |
252b5132 | 14339 | { |
707bfff6 TS |
14340 | as_bad (_("invalid register list")); |
14341 | break; | |
252b5132 RH |
14342 | } |
14343 | } | |
14344 | if (freg && reg1 == 0 && reg2 == 0 && c == 'L') | |
14345 | { | |
14346 | mask &= ~ (7 << 3); | |
14347 | mask |= 5 << 3; | |
14348 | } | |
14349 | else if (freg && reg1 == 0 && reg2 == 1 && c == 'L') | |
14350 | { | |
14351 | mask &= ~ (7 << 3); | |
14352 | mask |= 6 << 3; | |
14353 | } | |
14354 | else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L') | |
14355 | mask |= (reg2 - 3) << 3; | |
14356 | else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17) | |
14357 | mask |= (reg2 - 15) << 1; | |
f9419b05 | 14358 | else if (reg1 == RA && reg2 == RA) |
252b5132 RH |
14359 | mask |= 1; |
14360 | else | |
14361 | { | |
14362 | as_bad (_("invalid register list")); | |
14363 | break; | |
14364 | } | |
14365 | } | |
14366 | /* The mask is filled in in the opcode table for the | |
14367 | benefit of the disassembler. We remove it before | |
14368 | applying the actual mask. */ | |
14369 | ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6); | |
14370 | ip->insn_opcode |= mask << MIPS16OP_SH_IMM6; | |
14371 | } | |
14372 | continue; | |
14373 | ||
0499d65b TS |
14374 | case 'm': /* Register list for save insn. */ |
14375 | case 'M': /* Register list for restore insn. */ | |
14376 | { | |
5c04167a | 14377 | int opcode = ip->insn_opcode; |
0499d65b | 14378 | int framesz = 0, seen_framesz = 0; |
91d6fa6a | 14379 | int nargs = 0, statics = 0, sregs = 0; |
0499d65b TS |
14380 | |
14381 | while (*s != '\0') | |
14382 | { | |
14383 | unsigned int reg1, reg2; | |
14384 | ||
14385 | SKIP_SPACE_TABS (s); | |
14386 | while (*s == ',') | |
14387 | ++s; | |
14388 | SKIP_SPACE_TABS (s); | |
14389 | ||
14390 | my_getExpression (&imm_expr, s); | |
14391 | if (imm_expr.X_op == O_constant) | |
14392 | { | |
14393 | /* Handle the frame size. */ | |
14394 | if (seen_framesz) | |
14395 | { | |
14396 | as_bad (_("more than one frame size in list")); | |
14397 | break; | |
14398 | } | |
14399 | seen_framesz = 1; | |
14400 | framesz = imm_expr.X_add_number; | |
14401 | imm_expr.X_op = O_absent; | |
14402 | s = expr_end; | |
14403 | continue; | |
14404 | } | |
14405 | ||
707bfff6 | 14406 | if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®1)) |
0499d65b TS |
14407 | { |
14408 | as_bad (_("can't parse register list")); | |
14409 | break; | |
14410 | } | |
0499d65b | 14411 | |
707bfff6 TS |
14412 | while (*s == ' ') |
14413 | ++s; | |
14414 | ||
0499d65b TS |
14415 | if (*s != '-') |
14416 | reg2 = reg1; | |
14417 | else | |
14418 | { | |
14419 | ++s; | |
707bfff6 TS |
14420 | if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®2) |
14421 | || reg2 < reg1) | |
0499d65b TS |
14422 | { |
14423 | as_bad (_("can't parse register list")); | |
14424 | break; | |
14425 | } | |
0499d65b TS |
14426 | } |
14427 | ||
14428 | while (reg1 <= reg2) | |
14429 | { | |
14430 | if (reg1 >= 4 && reg1 <= 7) | |
14431 | { | |
3a93f742 | 14432 | if (!seen_framesz) |
0499d65b | 14433 | /* args $a0-$a3 */ |
91d6fa6a | 14434 | nargs |= 1 << (reg1 - 4); |
0499d65b TS |
14435 | else |
14436 | /* statics $a0-$a3 */ | |
14437 | statics |= 1 << (reg1 - 4); | |
14438 | } | |
14439 | else if ((reg1 >= 16 && reg1 <= 23) || reg1 == 30) | |
14440 | { | |
14441 | /* $s0-$s8 */ | |
14442 | sregs |= 1 << ((reg1 == 30) ? 8 : (reg1 - 16)); | |
14443 | } | |
14444 | else if (reg1 == 31) | |
14445 | { | |
14446 | /* Add $ra to insn. */ | |
14447 | opcode |= 0x40; | |
14448 | } | |
14449 | else | |
14450 | { | |
14451 | as_bad (_("unexpected register in list")); | |
14452 | break; | |
14453 | } | |
14454 | if (++reg1 == 24) | |
14455 | reg1 = 30; | |
14456 | } | |
14457 | } | |
14458 | ||
14459 | /* Encode args/statics combination. */ | |
91d6fa6a | 14460 | if (nargs & statics) |
0499d65b | 14461 | as_bad (_("arg/static registers overlap")); |
91d6fa6a | 14462 | else if (nargs == 0xf) |
0499d65b TS |
14463 | /* All $a0-$a3 are args. */ |
14464 | opcode |= MIPS16_ALL_ARGS << 16; | |
14465 | else if (statics == 0xf) | |
14466 | /* All $a0-$a3 are statics. */ | |
14467 | opcode |= MIPS16_ALL_STATICS << 16; | |
14468 | else | |
14469 | { | |
14470 | int narg = 0, nstat = 0; | |
14471 | ||
14472 | /* Count arg registers. */ | |
91d6fa6a | 14473 | while (nargs & 0x1) |
0499d65b | 14474 | { |
91d6fa6a | 14475 | nargs >>= 1; |
0499d65b TS |
14476 | narg++; |
14477 | } | |
91d6fa6a | 14478 | if (nargs != 0) |
0499d65b TS |
14479 | as_bad (_("invalid arg register list")); |
14480 | ||
14481 | /* Count static registers. */ | |
14482 | while (statics & 0x8) | |
14483 | { | |
14484 | statics = (statics << 1) & 0xf; | |
14485 | nstat++; | |
14486 | } | |
14487 | if (statics != 0) | |
14488 | as_bad (_("invalid static register list")); | |
14489 | ||
14490 | /* Encode args/statics. */ | |
14491 | opcode |= ((narg << 2) | nstat) << 16; | |
14492 | } | |
14493 | ||
14494 | /* Encode $s0/$s1. */ | |
14495 | if (sregs & (1 << 0)) /* $s0 */ | |
14496 | opcode |= 0x20; | |
14497 | if (sregs & (1 << 1)) /* $s1 */ | |
14498 | opcode |= 0x10; | |
14499 | sregs >>= 2; | |
14500 | ||
14501 | if (sregs != 0) | |
14502 | { | |
14503 | /* Count regs $s2-$s8. */ | |
14504 | int nsreg = 0; | |
14505 | while (sregs & 1) | |
14506 | { | |
14507 | sregs >>= 1; | |
14508 | nsreg++; | |
14509 | } | |
14510 | if (sregs != 0) | |
14511 | as_bad (_("invalid static register list")); | |
14512 | /* Encode $s2-$s8. */ | |
14513 | opcode |= nsreg << 24; | |
14514 | } | |
14515 | ||
14516 | /* Encode frame size. */ | |
14517 | if (!seen_framesz) | |
14518 | as_bad (_("missing frame size")); | |
14519 | else if ((framesz & 7) != 0 || framesz < 0 | |
14520 | || framesz > 0xff * 8) | |
14521 | as_bad (_("invalid frame size")); | |
14522 | else if (framesz != 128 || (opcode >> 16) != 0) | |
14523 | { | |
14524 | framesz /= 8; | |
14525 | opcode |= (((framesz & 0xf0) << 16) | |
14526 | | (framesz & 0x0f)); | |
14527 | } | |
14528 | ||
14529 | /* Finally build the instruction. */ | |
14530 | if ((opcode >> 16) != 0 || framesz == 0) | |
5c04167a RS |
14531 | opcode |= MIPS16_EXTEND; |
14532 | ip->insn_opcode = opcode; | |
0499d65b TS |
14533 | } |
14534 | continue; | |
14535 | ||
252b5132 RH |
14536 | case 'e': /* extend code */ |
14537 | my_getExpression (&imm_expr, s); | |
14538 | check_absolute_expr (ip, &imm_expr); | |
14539 | if ((unsigned long) imm_expr.X_add_number > 0x7ff) | |
14540 | { | |
14541 | as_warn (_("Invalid value for `%s' (%lu)"), | |
14542 | ip->insn_mo->name, | |
14543 | (unsigned long) imm_expr.X_add_number); | |
14544 | imm_expr.X_add_number &= 0x7ff; | |
14545 | } | |
14546 | ip->insn_opcode |= imm_expr.X_add_number; | |
14547 | imm_expr.X_op = O_absent; | |
14548 | s = expr_end; | |
14549 | continue; | |
14550 | ||
14551 | default: | |
b37df7c4 | 14552 | abort (); |
252b5132 RH |
14553 | } |
14554 | break; | |
14555 | } | |
14556 | ||
14557 | /* Args don't match. */ | |
14558 | if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] && | |
14559 | strcmp (insn->name, insn[1].name) == 0) | |
14560 | { | |
14561 | ++insn; | |
14562 | s = argsstart; | |
14563 | continue; | |
14564 | } | |
14565 | ||
14566 | insn_error = _("illegal operands"); | |
14567 | ||
14568 | return; | |
14569 | } | |
14570 | } | |
14571 | ||
14572 | /* This structure holds information we know about a mips16 immediate | |
14573 | argument type. */ | |
14574 | ||
e972090a NC |
14575 | struct mips16_immed_operand |
14576 | { | |
252b5132 RH |
14577 | /* The type code used in the argument string in the opcode table. */ |
14578 | int type; | |
14579 | /* The number of bits in the short form of the opcode. */ | |
14580 | int nbits; | |
14581 | /* The number of bits in the extended form of the opcode. */ | |
14582 | int extbits; | |
14583 | /* The amount by which the short form is shifted when it is used; | |
14584 | for example, the sw instruction has a shift count of 2. */ | |
14585 | int shift; | |
14586 | /* The amount by which the short form is shifted when it is stored | |
14587 | into the instruction code. */ | |
14588 | int op_shift; | |
14589 | /* Non-zero if the short form is unsigned. */ | |
14590 | int unsp; | |
14591 | /* Non-zero if the extended form is unsigned. */ | |
14592 | int extu; | |
14593 | /* Non-zero if the value is PC relative. */ | |
14594 | int pcrel; | |
14595 | }; | |
14596 | ||
14597 | /* The mips16 immediate operand types. */ | |
14598 | ||
14599 | static const struct mips16_immed_operand mips16_immed_operands[] = | |
14600 | { | |
14601 | { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
14602 | { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
14603 | { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
14604 | { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
14605 | { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 }, | |
14606 | { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
14607 | { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
14608 | { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
14609 | { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
14610 | { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 }, | |
14611 | { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
14612 | { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
14613 | { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
14614 | { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 }, | |
14615 | { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
14616 | { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
14617 | { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
14618 | { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
14619 | { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 }, | |
14620 | { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 }, | |
14621 | { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 } | |
14622 | }; | |
14623 | ||
14624 | #define MIPS16_NUM_IMMED \ | |
14625 | (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0]) | |
14626 | ||
b886a2ab RS |
14627 | /* Marshal immediate value VAL for an extended MIPS16 instruction. |
14628 | NBITS is the number of significant bits in VAL. */ | |
14629 | ||
14630 | static unsigned long | |
14631 | mips16_immed_extend (offsetT val, unsigned int nbits) | |
14632 | { | |
14633 | int extval; | |
14634 | if (nbits == 16) | |
14635 | { | |
14636 | extval = ((val >> 11) & 0x1f) | (val & 0x7e0); | |
14637 | val &= 0x1f; | |
14638 | } | |
14639 | else if (nbits == 15) | |
14640 | { | |
14641 | extval = ((val >> 11) & 0xf) | (val & 0x7f0); | |
14642 | val &= 0xf; | |
14643 | } | |
14644 | else | |
14645 | { | |
14646 | extval = ((val & 0x1f) << 6) | (val & 0x20); | |
14647 | val = 0; | |
14648 | } | |
14649 | return (extval << 16) | val; | |
14650 | } | |
14651 | ||
5c04167a RS |
14652 | /* Install immediate value VAL into MIPS16 instruction *INSN, |
14653 | extending it if necessary. The instruction in *INSN may | |
14654 | already be extended. | |
14655 | ||
43c0598f RS |
14656 | RELOC is the relocation that produced VAL, or BFD_RELOC_UNUSED |
14657 | if none. In the former case, VAL is a 16-bit number with no | |
14658 | defined signedness. | |
14659 | ||
14660 | TYPE is the type of the immediate field. USER_INSN_LENGTH | |
14661 | is the length that the user requested, or 0 if none. */ | |
252b5132 RH |
14662 | |
14663 | static void | |
43c0598f RS |
14664 | mips16_immed (char *file, unsigned int line, int type, |
14665 | bfd_reloc_code_real_type reloc, offsetT val, | |
5c04167a | 14666 | unsigned int user_insn_length, unsigned long *insn) |
252b5132 | 14667 | { |
3994f87e | 14668 | const struct mips16_immed_operand *op; |
252b5132 | 14669 | int mintiny, maxtiny; |
252b5132 RH |
14670 | |
14671 | op = mips16_immed_operands; | |
14672 | while (op->type != type) | |
14673 | { | |
14674 | ++op; | |
9c2799c2 | 14675 | gas_assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); |
252b5132 RH |
14676 | } |
14677 | ||
14678 | if (op->unsp) | |
14679 | { | |
14680 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
14681 | { | |
14682 | mintiny = 1; | |
14683 | maxtiny = 1 << op->nbits; | |
14684 | } | |
14685 | else | |
14686 | { | |
14687 | mintiny = 0; | |
14688 | maxtiny = (1 << op->nbits) - 1; | |
14689 | } | |
43c0598f RS |
14690 | if (reloc != BFD_RELOC_UNUSED) |
14691 | val &= 0xffff; | |
252b5132 RH |
14692 | } |
14693 | else | |
14694 | { | |
14695 | mintiny = - (1 << (op->nbits - 1)); | |
14696 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
43c0598f RS |
14697 | if (reloc != BFD_RELOC_UNUSED) |
14698 | val = SEXT_16BIT (val); | |
252b5132 RH |
14699 | } |
14700 | ||
14701 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
14702 | if (type == 'p' || type == 'q') | |
14703 | val /= 2; | |
14704 | ||
14705 | if ((val & ((1 << op->shift) - 1)) != 0 | |
14706 | || val < (mintiny << op->shift) | |
14707 | || val > (maxtiny << op->shift)) | |
5c04167a RS |
14708 | { |
14709 | /* We need an extended instruction. */ | |
14710 | if (user_insn_length == 2) | |
14711 | as_bad_where (file, line, _("invalid unextended operand value")); | |
14712 | else | |
14713 | *insn |= MIPS16_EXTEND; | |
14714 | } | |
14715 | else if (user_insn_length == 4) | |
14716 | { | |
14717 | /* The operand doesn't force an unextended instruction to be extended. | |
14718 | Warn if the user wanted an extended instruction anyway. */ | |
14719 | *insn |= MIPS16_EXTEND; | |
14720 | as_warn_where (file, line, | |
14721 | _("extended operand requested but not required")); | |
14722 | } | |
252b5132 | 14723 | |
5c04167a | 14724 | if (mips16_opcode_length (*insn) == 2) |
252b5132 RH |
14725 | { |
14726 | int insnval; | |
14727 | ||
252b5132 RH |
14728 | insnval = ((val >> op->shift) & ((1 << op->nbits) - 1)); |
14729 | insnval <<= op->op_shift; | |
14730 | *insn |= insnval; | |
14731 | } | |
14732 | else | |
14733 | { | |
14734 | long minext, maxext; | |
252b5132 | 14735 | |
43c0598f | 14736 | if (reloc == BFD_RELOC_UNUSED) |
252b5132 | 14737 | { |
43c0598f RS |
14738 | if (op->extu) |
14739 | { | |
14740 | minext = 0; | |
14741 | maxext = (1 << op->extbits) - 1; | |
14742 | } | |
14743 | else | |
14744 | { | |
14745 | minext = - (1 << (op->extbits - 1)); | |
14746 | maxext = (1 << (op->extbits - 1)) - 1; | |
14747 | } | |
14748 | if (val < minext || val > maxext) | |
14749 | as_bad_where (file, line, | |
14750 | _("operand value out of range for instruction")); | |
252b5132 | 14751 | } |
252b5132 | 14752 | |
b886a2ab | 14753 | *insn |= mips16_immed_extend (val, op->extbits); |
252b5132 RH |
14754 | } |
14755 | } | |
14756 | \f | |
d6f16593 | 14757 | struct percent_op_match |
ad8d3bb3 | 14758 | { |
5e0116d5 RS |
14759 | const char *str; |
14760 | bfd_reloc_code_real_type reloc; | |
d6f16593 MR |
14761 | }; |
14762 | ||
14763 | static const struct percent_op_match mips_percent_op[] = | |
ad8d3bb3 | 14764 | { |
5e0116d5 | 14765 | {"%lo", BFD_RELOC_LO16}, |
5e0116d5 RS |
14766 | {"%call_hi", BFD_RELOC_MIPS_CALL_HI16}, |
14767 | {"%call_lo", BFD_RELOC_MIPS_CALL_LO16}, | |
14768 | {"%call16", BFD_RELOC_MIPS_CALL16}, | |
14769 | {"%got_disp", BFD_RELOC_MIPS_GOT_DISP}, | |
14770 | {"%got_page", BFD_RELOC_MIPS_GOT_PAGE}, | |
14771 | {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST}, | |
14772 | {"%got_hi", BFD_RELOC_MIPS_GOT_HI16}, | |
14773 | {"%got_lo", BFD_RELOC_MIPS_GOT_LO16}, | |
14774 | {"%got", BFD_RELOC_MIPS_GOT16}, | |
14775 | {"%gp_rel", BFD_RELOC_GPREL16}, | |
14776 | {"%half", BFD_RELOC_16}, | |
14777 | {"%highest", BFD_RELOC_MIPS_HIGHEST}, | |
14778 | {"%higher", BFD_RELOC_MIPS_HIGHER}, | |
14779 | {"%neg", BFD_RELOC_MIPS_SUB}, | |
3f98094e DJ |
14780 | {"%tlsgd", BFD_RELOC_MIPS_TLS_GD}, |
14781 | {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM}, | |
14782 | {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16}, | |
14783 | {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16}, | |
14784 | {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16}, | |
14785 | {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16}, | |
14786 | {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL}, | |
5e0116d5 | 14787 | {"%hi", BFD_RELOC_HI16_S} |
ad8d3bb3 TS |
14788 | }; |
14789 | ||
d6f16593 MR |
14790 | static const struct percent_op_match mips16_percent_op[] = |
14791 | { | |
14792 | {"%lo", BFD_RELOC_MIPS16_LO16}, | |
14793 | {"%gprel", BFD_RELOC_MIPS16_GPREL}, | |
738e5348 RS |
14794 | {"%got", BFD_RELOC_MIPS16_GOT16}, |
14795 | {"%call16", BFD_RELOC_MIPS16_CALL16}, | |
d0f13682 CLT |
14796 | {"%hi", BFD_RELOC_MIPS16_HI16_S}, |
14797 | {"%tlsgd", BFD_RELOC_MIPS16_TLS_GD}, | |
14798 | {"%tlsldm", BFD_RELOC_MIPS16_TLS_LDM}, | |
14799 | {"%dtprel_hi", BFD_RELOC_MIPS16_TLS_DTPREL_HI16}, | |
14800 | {"%dtprel_lo", BFD_RELOC_MIPS16_TLS_DTPREL_LO16}, | |
14801 | {"%tprel_hi", BFD_RELOC_MIPS16_TLS_TPREL_HI16}, | |
14802 | {"%tprel_lo", BFD_RELOC_MIPS16_TLS_TPREL_LO16}, | |
14803 | {"%gottprel", BFD_RELOC_MIPS16_TLS_GOTTPREL} | |
d6f16593 MR |
14804 | }; |
14805 | ||
252b5132 | 14806 | |
5e0116d5 RS |
14807 | /* Return true if *STR points to a relocation operator. When returning true, |
14808 | move *STR over the operator and store its relocation code in *RELOC. | |
14809 | Leave both *STR and *RELOC alone when returning false. */ | |
14810 | ||
14811 | static bfd_boolean | |
17a2f251 | 14812 | parse_relocation (char **str, bfd_reloc_code_real_type *reloc) |
252b5132 | 14813 | { |
d6f16593 MR |
14814 | const struct percent_op_match *percent_op; |
14815 | size_t limit, i; | |
14816 | ||
14817 | if (mips_opts.mips16) | |
14818 | { | |
14819 | percent_op = mips16_percent_op; | |
14820 | limit = ARRAY_SIZE (mips16_percent_op); | |
14821 | } | |
14822 | else | |
14823 | { | |
14824 | percent_op = mips_percent_op; | |
14825 | limit = ARRAY_SIZE (mips_percent_op); | |
14826 | } | |
76b3015f | 14827 | |
d6f16593 | 14828 | for (i = 0; i < limit; i++) |
5e0116d5 | 14829 | if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0) |
394f9b3a | 14830 | { |
3f98094e DJ |
14831 | int len = strlen (percent_op[i].str); |
14832 | ||
14833 | if (!ISSPACE ((*str)[len]) && (*str)[len] != '(') | |
14834 | continue; | |
14835 | ||
5e0116d5 RS |
14836 | *str += strlen (percent_op[i].str); |
14837 | *reloc = percent_op[i].reloc; | |
394f9b3a | 14838 | |
5e0116d5 RS |
14839 | /* Check whether the output BFD supports this relocation. |
14840 | If not, issue an error and fall back on something safe. */ | |
14841 | if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc)) | |
394f9b3a | 14842 | { |
20203fb9 | 14843 | as_bad (_("relocation %s isn't supported by the current ABI"), |
5e0116d5 | 14844 | percent_op[i].str); |
01a3f561 | 14845 | *reloc = BFD_RELOC_UNUSED; |
394f9b3a | 14846 | } |
5e0116d5 | 14847 | return TRUE; |
394f9b3a | 14848 | } |
5e0116d5 | 14849 | return FALSE; |
394f9b3a | 14850 | } |
ad8d3bb3 | 14851 | |
ad8d3bb3 | 14852 | |
5e0116d5 RS |
14853 | /* Parse string STR as a 16-bit relocatable operand. Store the |
14854 | expression in *EP and the relocations in the array starting | |
14855 | at RELOC. Return the number of relocation operators used. | |
ad8d3bb3 | 14856 | |
01a3f561 | 14857 | On exit, EXPR_END points to the first character after the expression. */ |
ad8d3bb3 | 14858 | |
5e0116d5 | 14859 | static size_t |
17a2f251 TS |
14860 | my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc, |
14861 | char *str) | |
ad8d3bb3 | 14862 | { |
5e0116d5 RS |
14863 | bfd_reloc_code_real_type reversed_reloc[3]; |
14864 | size_t reloc_index, i; | |
09b8f35a RS |
14865 | int crux_depth, str_depth; |
14866 | char *crux; | |
5e0116d5 RS |
14867 | |
14868 | /* Search for the start of the main expression, recoding relocations | |
09b8f35a RS |
14869 | in REVERSED_RELOC. End the loop with CRUX pointing to the start |
14870 | of the main expression and with CRUX_DEPTH containing the number | |
14871 | of open brackets at that point. */ | |
14872 | reloc_index = -1; | |
14873 | str_depth = 0; | |
14874 | do | |
fb1b3232 | 14875 | { |
09b8f35a RS |
14876 | reloc_index++; |
14877 | crux = str; | |
14878 | crux_depth = str_depth; | |
14879 | ||
14880 | /* Skip over whitespace and brackets, keeping count of the number | |
14881 | of brackets. */ | |
14882 | while (*str == ' ' || *str == '\t' || *str == '(') | |
14883 | if (*str++ == '(') | |
14884 | str_depth++; | |
5e0116d5 | 14885 | } |
09b8f35a RS |
14886 | while (*str == '%' |
14887 | && reloc_index < (HAVE_NEWABI ? 3 : 1) | |
14888 | && parse_relocation (&str, &reversed_reloc[reloc_index])); | |
ad8d3bb3 | 14889 | |
09b8f35a | 14890 | my_getExpression (ep, crux); |
5e0116d5 | 14891 | str = expr_end; |
394f9b3a | 14892 | |
5e0116d5 | 14893 | /* Match every open bracket. */ |
09b8f35a | 14894 | while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t')) |
5e0116d5 | 14895 | if (*str++ == ')') |
09b8f35a | 14896 | crux_depth--; |
394f9b3a | 14897 | |
09b8f35a | 14898 | if (crux_depth > 0) |
20203fb9 | 14899 | as_bad (_("unclosed '('")); |
394f9b3a | 14900 | |
5e0116d5 | 14901 | expr_end = str; |
252b5132 | 14902 | |
01a3f561 | 14903 | if (reloc_index != 0) |
64bdfcaf RS |
14904 | { |
14905 | prev_reloc_op_frag = frag_now; | |
14906 | for (i = 0; i < reloc_index; i++) | |
14907 | reloc[i] = reversed_reloc[reloc_index - 1 - i]; | |
14908 | } | |
fb1b3232 | 14909 | |
5e0116d5 | 14910 | return reloc_index; |
252b5132 RH |
14911 | } |
14912 | ||
14913 | static void | |
17a2f251 | 14914 | my_getExpression (expressionS *ep, char *str) |
252b5132 RH |
14915 | { |
14916 | char *save_in; | |
14917 | ||
14918 | save_in = input_line_pointer; | |
14919 | input_line_pointer = str; | |
14920 | expression (ep); | |
14921 | expr_end = input_line_pointer; | |
14922 | input_line_pointer = save_in; | |
252b5132 RH |
14923 | } |
14924 | ||
252b5132 | 14925 | char * |
17a2f251 | 14926 | md_atof (int type, char *litP, int *sizeP) |
252b5132 | 14927 | { |
499ac353 | 14928 | return ieee_md_atof (type, litP, sizeP, target_big_endian); |
252b5132 RH |
14929 | } |
14930 | ||
14931 | void | |
17a2f251 | 14932 | md_number_to_chars (char *buf, valueT val, int n) |
252b5132 RH |
14933 | { |
14934 | if (target_big_endian) | |
14935 | number_to_chars_bigendian (buf, val, n); | |
14936 | else | |
14937 | number_to_chars_littleendian (buf, val, n); | |
14938 | } | |
14939 | \f | |
e013f690 TS |
14940 | static int support_64bit_objects(void) |
14941 | { | |
14942 | const char **list, **l; | |
aa3d8fdf | 14943 | int yes; |
e013f690 TS |
14944 | |
14945 | list = bfd_target_list (); | |
14946 | for (l = list; *l != NULL; l++) | |
aeffff67 RS |
14947 | if (strcmp (*l, ELF_TARGET ("elf64-", "big")) == 0 |
14948 | || strcmp (*l, ELF_TARGET ("elf64-", "little")) == 0) | |
e013f690 | 14949 | break; |
aa3d8fdf | 14950 | yes = (*l != NULL); |
e013f690 | 14951 | free (list); |
aa3d8fdf | 14952 | return yes; |
e013f690 TS |
14953 | } |
14954 | ||
316f5878 RS |
14955 | /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to |
14956 | NEW_VALUE. Warn if another value was already specified. Note: | |
14957 | we have to defer parsing the -march and -mtune arguments in order | |
14958 | to handle 'from-abi' correctly, since the ABI might be specified | |
14959 | in a later argument. */ | |
14960 | ||
14961 | static void | |
17a2f251 | 14962 | mips_set_option_string (const char **string_ptr, const char *new_value) |
316f5878 RS |
14963 | { |
14964 | if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0) | |
14965 | as_warn (_("A different %s was already specified, is now %s"), | |
14966 | string_ptr == &mips_arch_string ? "-march" : "-mtune", | |
14967 | new_value); | |
14968 | ||
14969 | *string_ptr = new_value; | |
14970 | } | |
14971 | ||
252b5132 | 14972 | int |
17a2f251 | 14973 | md_parse_option (int c, char *arg) |
252b5132 | 14974 | { |
c6278170 RS |
14975 | unsigned int i; |
14976 | ||
14977 | for (i = 0; i < ARRAY_SIZE (mips_ases); i++) | |
14978 | if (c == mips_ases[i].option_on || c == mips_ases[i].option_off) | |
14979 | { | |
14980 | file_ase_explicit |= mips_set_ase (&mips_ases[i], | |
14981 | c == mips_ases[i].option_on); | |
14982 | return 1; | |
14983 | } | |
14984 | ||
252b5132 RH |
14985 | switch (c) |
14986 | { | |
119d663a NC |
14987 | case OPTION_CONSTRUCT_FLOATS: |
14988 | mips_disable_float_construction = 0; | |
14989 | break; | |
bdaaa2e1 | 14990 | |
119d663a NC |
14991 | case OPTION_NO_CONSTRUCT_FLOATS: |
14992 | mips_disable_float_construction = 1; | |
14993 | break; | |
bdaaa2e1 | 14994 | |
252b5132 RH |
14995 | case OPTION_TRAP: |
14996 | mips_trap = 1; | |
14997 | break; | |
14998 | ||
14999 | case OPTION_BREAK: | |
15000 | mips_trap = 0; | |
15001 | break; | |
15002 | ||
15003 | case OPTION_EB: | |
15004 | target_big_endian = 1; | |
15005 | break; | |
15006 | ||
15007 | case OPTION_EL: | |
15008 | target_big_endian = 0; | |
15009 | break; | |
15010 | ||
15011 | case 'O': | |
4ffff32f TS |
15012 | if (arg == NULL) |
15013 | mips_optimize = 1; | |
15014 | else if (arg[0] == '0') | |
15015 | mips_optimize = 0; | |
15016 | else if (arg[0] == '1') | |
252b5132 RH |
15017 | mips_optimize = 1; |
15018 | else | |
15019 | mips_optimize = 2; | |
15020 | break; | |
15021 | ||
15022 | case 'g': | |
15023 | if (arg == NULL) | |
15024 | mips_debug = 2; | |
15025 | else | |
15026 | mips_debug = atoi (arg); | |
252b5132 RH |
15027 | break; |
15028 | ||
15029 | case OPTION_MIPS1: | |
316f5878 | 15030 | file_mips_isa = ISA_MIPS1; |
252b5132 RH |
15031 | break; |
15032 | ||
15033 | case OPTION_MIPS2: | |
316f5878 | 15034 | file_mips_isa = ISA_MIPS2; |
252b5132 RH |
15035 | break; |
15036 | ||
15037 | case OPTION_MIPS3: | |
316f5878 | 15038 | file_mips_isa = ISA_MIPS3; |
252b5132 RH |
15039 | break; |
15040 | ||
15041 | case OPTION_MIPS4: | |
316f5878 | 15042 | file_mips_isa = ISA_MIPS4; |
e7af610e NC |
15043 | break; |
15044 | ||
84ea6cf2 | 15045 | case OPTION_MIPS5: |
316f5878 | 15046 | file_mips_isa = ISA_MIPS5; |
84ea6cf2 NC |
15047 | break; |
15048 | ||
e7af610e | 15049 | case OPTION_MIPS32: |
316f5878 | 15050 | file_mips_isa = ISA_MIPS32; |
252b5132 RH |
15051 | break; |
15052 | ||
af7ee8bf CD |
15053 | case OPTION_MIPS32R2: |
15054 | file_mips_isa = ISA_MIPS32R2; | |
15055 | break; | |
15056 | ||
5f74bc13 CD |
15057 | case OPTION_MIPS64R2: |
15058 | file_mips_isa = ISA_MIPS64R2; | |
15059 | break; | |
15060 | ||
84ea6cf2 | 15061 | case OPTION_MIPS64: |
316f5878 | 15062 | file_mips_isa = ISA_MIPS64; |
84ea6cf2 NC |
15063 | break; |
15064 | ||
ec68c924 | 15065 | case OPTION_MTUNE: |
316f5878 RS |
15066 | mips_set_option_string (&mips_tune_string, arg); |
15067 | break; | |
ec68c924 | 15068 | |
316f5878 RS |
15069 | case OPTION_MARCH: |
15070 | mips_set_option_string (&mips_arch_string, arg); | |
252b5132 RH |
15071 | break; |
15072 | ||
15073 | case OPTION_M4650: | |
316f5878 RS |
15074 | mips_set_option_string (&mips_arch_string, "4650"); |
15075 | mips_set_option_string (&mips_tune_string, "4650"); | |
252b5132 RH |
15076 | break; |
15077 | ||
15078 | case OPTION_NO_M4650: | |
15079 | break; | |
15080 | ||
15081 | case OPTION_M4010: | |
316f5878 RS |
15082 | mips_set_option_string (&mips_arch_string, "4010"); |
15083 | mips_set_option_string (&mips_tune_string, "4010"); | |
252b5132 RH |
15084 | break; |
15085 | ||
15086 | case OPTION_NO_M4010: | |
15087 | break; | |
15088 | ||
15089 | case OPTION_M4100: | |
316f5878 RS |
15090 | mips_set_option_string (&mips_arch_string, "4100"); |
15091 | mips_set_option_string (&mips_tune_string, "4100"); | |
252b5132 RH |
15092 | break; |
15093 | ||
15094 | case OPTION_NO_M4100: | |
15095 | break; | |
15096 | ||
252b5132 | 15097 | case OPTION_M3900: |
316f5878 RS |
15098 | mips_set_option_string (&mips_arch_string, "3900"); |
15099 | mips_set_option_string (&mips_tune_string, "3900"); | |
252b5132 | 15100 | break; |
bdaaa2e1 | 15101 | |
252b5132 RH |
15102 | case OPTION_NO_M3900: |
15103 | break; | |
15104 | ||
df58fc94 RS |
15105 | case OPTION_MICROMIPS: |
15106 | if (mips_opts.mips16 == 1) | |
15107 | { | |
15108 | as_bad (_("-mmicromips cannot be used with -mips16")); | |
15109 | return 0; | |
15110 | } | |
15111 | mips_opts.micromips = 1; | |
15112 | mips_no_prev_insn (); | |
15113 | break; | |
15114 | ||
15115 | case OPTION_NO_MICROMIPS: | |
15116 | mips_opts.micromips = 0; | |
15117 | mips_no_prev_insn (); | |
15118 | break; | |
15119 | ||
252b5132 | 15120 | case OPTION_MIPS16: |
df58fc94 RS |
15121 | if (mips_opts.micromips == 1) |
15122 | { | |
15123 | as_bad (_("-mips16 cannot be used with -micromips")); | |
15124 | return 0; | |
15125 | } | |
252b5132 | 15126 | mips_opts.mips16 = 1; |
7d10b47d | 15127 | mips_no_prev_insn (); |
252b5132 RH |
15128 | break; |
15129 | ||
15130 | case OPTION_NO_MIPS16: | |
15131 | mips_opts.mips16 = 0; | |
7d10b47d | 15132 | mips_no_prev_insn (); |
252b5132 RH |
15133 | break; |
15134 | ||
6a32d874 CM |
15135 | case OPTION_FIX_24K: |
15136 | mips_fix_24k = 1; | |
15137 | break; | |
15138 | ||
15139 | case OPTION_NO_FIX_24K: | |
15140 | mips_fix_24k = 0; | |
15141 | break; | |
15142 | ||
c67a084a NC |
15143 | case OPTION_FIX_LOONGSON2F_JUMP: |
15144 | mips_fix_loongson2f_jump = TRUE; | |
15145 | break; | |
15146 | ||
15147 | case OPTION_NO_FIX_LOONGSON2F_JUMP: | |
15148 | mips_fix_loongson2f_jump = FALSE; | |
15149 | break; | |
15150 | ||
15151 | case OPTION_FIX_LOONGSON2F_NOP: | |
15152 | mips_fix_loongson2f_nop = TRUE; | |
15153 | break; | |
15154 | ||
15155 | case OPTION_NO_FIX_LOONGSON2F_NOP: | |
15156 | mips_fix_loongson2f_nop = FALSE; | |
15157 | break; | |
15158 | ||
d766e8ec RS |
15159 | case OPTION_FIX_VR4120: |
15160 | mips_fix_vr4120 = 1; | |
60b63b72 RS |
15161 | break; |
15162 | ||
d766e8ec RS |
15163 | case OPTION_NO_FIX_VR4120: |
15164 | mips_fix_vr4120 = 0; | |
60b63b72 RS |
15165 | break; |
15166 | ||
7d8e00cf RS |
15167 | case OPTION_FIX_VR4130: |
15168 | mips_fix_vr4130 = 1; | |
15169 | break; | |
15170 | ||
15171 | case OPTION_NO_FIX_VR4130: | |
15172 | mips_fix_vr4130 = 0; | |
15173 | break; | |
15174 | ||
d954098f DD |
15175 | case OPTION_FIX_CN63XXP1: |
15176 | mips_fix_cn63xxp1 = TRUE; | |
15177 | break; | |
15178 | ||
15179 | case OPTION_NO_FIX_CN63XXP1: | |
15180 | mips_fix_cn63xxp1 = FALSE; | |
15181 | break; | |
15182 | ||
4a6a3df4 AO |
15183 | case OPTION_RELAX_BRANCH: |
15184 | mips_relax_branch = 1; | |
15185 | break; | |
15186 | ||
15187 | case OPTION_NO_RELAX_BRANCH: | |
15188 | mips_relax_branch = 0; | |
15189 | break; | |
15190 | ||
aa6975fb ILT |
15191 | case OPTION_MSHARED: |
15192 | mips_in_shared = TRUE; | |
15193 | break; | |
15194 | ||
15195 | case OPTION_MNO_SHARED: | |
15196 | mips_in_shared = FALSE; | |
15197 | break; | |
15198 | ||
aed1a261 RS |
15199 | case OPTION_MSYM32: |
15200 | mips_opts.sym32 = TRUE; | |
15201 | break; | |
15202 | ||
15203 | case OPTION_MNO_SYM32: | |
15204 | mips_opts.sym32 = FALSE; | |
15205 | break; | |
15206 | ||
252b5132 RH |
15207 | /* When generating ELF code, we permit -KPIC and -call_shared to |
15208 | select SVR4_PIC, and -non_shared to select no PIC. This is | |
15209 | intended to be compatible with Irix 5. */ | |
15210 | case OPTION_CALL_SHARED: | |
252b5132 | 15211 | mips_pic = SVR4_PIC; |
143d77c5 | 15212 | mips_abicalls = TRUE; |
252b5132 RH |
15213 | break; |
15214 | ||
861fb55a | 15215 | case OPTION_CALL_NONPIC: |
861fb55a DJ |
15216 | mips_pic = NO_PIC; |
15217 | mips_abicalls = TRUE; | |
15218 | break; | |
15219 | ||
252b5132 | 15220 | case OPTION_NON_SHARED: |
252b5132 | 15221 | mips_pic = NO_PIC; |
143d77c5 | 15222 | mips_abicalls = FALSE; |
252b5132 RH |
15223 | break; |
15224 | ||
44075ae2 TS |
15225 | /* The -xgot option tells the assembler to use 32 bit offsets |
15226 | when accessing the got in SVR4_PIC mode. It is for Irix | |
252b5132 RH |
15227 | compatibility. */ |
15228 | case OPTION_XGOT: | |
15229 | mips_big_got = 1; | |
15230 | break; | |
15231 | ||
15232 | case 'G': | |
6caf9ef4 TS |
15233 | g_switch_value = atoi (arg); |
15234 | g_switch_seen = 1; | |
252b5132 RH |
15235 | break; |
15236 | ||
34ba82a8 TS |
15237 | /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32 |
15238 | and -mabi=64. */ | |
252b5132 | 15239 | case OPTION_32: |
f3ded42a | 15240 | mips_abi = O32_ABI; |
252b5132 RH |
15241 | break; |
15242 | ||
e013f690 | 15243 | case OPTION_N32: |
316f5878 | 15244 | mips_abi = N32_ABI; |
e013f690 | 15245 | break; |
252b5132 | 15246 | |
e013f690 | 15247 | case OPTION_64: |
316f5878 | 15248 | mips_abi = N64_ABI; |
f43abd2b | 15249 | if (!support_64bit_objects()) |
e013f690 | 15250 | as_fatal (_("No compiled in support for 64 bit object file format")); |
252b5132 RH |
15251 | break; |
15252 | ||
c97ef257 | 15253 | case OPTION_GP32: |
a325df1d | 15254 | file_mips_gp32 = 1; |
c97ef257 AH |
15255 | break; |
15256 | ||
15257 | case OPTION_GP64: | |
a325df1d | 15258 | file_mips_gp32 = 0; |
c97ef257 | 15259 | break; |
252b5132 | 15260 | |
ca4e0257 | 15261 | case OPTION_FP32: |
a325df1d | 15262 | file_mips_fp32 = 1; |
316f5878 RS |
15263 | break; |
15264 | ||
15265 | case OPTION_FP64: | |
15266 | file_mips_fp32 = 0; | |
ca4e0257 RS |
15267 | break; |
15268 | ||
037b32b9 AN |
15269 | case OPTION_SINGLE_FLOAT: |
15270 | file_mips_single_float = 1; | |
15271 | break; | |
15272 | ||
15273 | case OPTION_DOUBLE_FLOAT: | |
15274 | file_mips_single_float = 0; | |
15275 | break; | |
15276 | ||
15277 | case OPTION_SOFT_FLOAT: | |
15278 | file_mips_soft_float = 1; | |
15279 | break; | |
15280 | ||
15281 | case OPTION_HARD_FLOAT: | |
15282 | file_mips_soft_float = 0; | |
15283 | break; | |
15284 | ||
252b5132 | 15285 | case OPTION_MABI: |
e013f690 | 15286 | if (strcmp (arg, "32") == 0) |
316f5878 | 15287 | mips_abi = O32_ABI; |
e013f690 | 15288 | else if (strcmp (arg, "o64") == 0) |
316f5878 | 15289 | mips_abi = O64_ABI; |
e013f690 | 15290 | else if (strcmp (arg, "n32") == 0) |
316f5878 | 15291 | mips_abi = N32_ABI; |
e013f690 TS |
15292 | else if (strcmp (arg, "64") == 0) |
15293 | { | |
316f5878 | 15294 | mips_abi = N64_ABI; |
e013f690 TS |
15295 | if (! support_64bit_objects()) |
15296 | as_fatal (_("No compiled in support for 64 bit object file " | |
15297 | "format")); | |
15298 | } | |
15299 | else if (strcmp (arg, "eabi") == 0) | |
316f5878 | 15300 | mips_abi = EABI_ABI; |
e013f690 | 15301 | else |
da0e507f TS |
15302 | { |
15303 | as_fatal (_("invalid abi -mabi=%s"), arg); | |
15304 | return 0; | |
15305 | } | |
252b5132 RH |
15306 | break; |
15307 | ||
6b76fefe | 15308 | case OPTION_M7000_HILO_FIX: |
b34976b6 | 15309 | mips_7000_hilo_fix = TRUE; |
6b76fefe CM |
15310 | break; |
15311 | ||
9ee72ff1 | 15312 | case OPTION_MNO_7000_HILO_FIX: |
b34976b6 | 15313 | mips_7000_hilo_fix = FALSE; |
6b76fefe CM |
15314 | break; |
15315 | ||
ecb4347a | 15316 | case OPTION_MDEBUG: |
b34976b6 | 15317 | mips_flag_mdebug = TRUE; |
ecb4347a DJ |
15318 | break; |
15319 | ||
15320 | case OPTION_NO_MDEBUG: | |
b34976b6 | 15321 | mips_flag_mdebug = FALSE; |
ecb4347a | 15322 | break; |
dcd410fe RO |
15323 | |
15324 | case OPTION_PDR: | |
15325 | mips_flag_pdr = TRUE; | |
15326 | break; | |
15327 | ||
15328 | case OPTION_NO_PDR: | |
15329 | mips_flag_pdr = FALSE; | |
15330 | break; | |
0a44bf69 RS |
15331 | |
15332 | case OPTION_MVXWORKS_PIC: | |
15333 | mips_pic = VXWORKS_PIC; | |
15334 | break; | |
ecb4347a | 15335 | |
252b5132 RH |
15336 | default: |
15337 | return 0; | |
15338 | } | |
15339 | ||
c67a084a NC |
15340 | mips_fix_loongson2f = mips_fix_loongson2f_nop || mips_fix_loongson2f_jump; |
15341 | ||
252b5132 RH |
15342 | return 1; |
15343 | } | |
316f5878 RS |
15344 | \f |
15345 | /* Set up globals to generate code for the ISA or processor | |
15346 | described by INFO. */ | |
252b5132 | 15347 | |
252b5132 | 15348 | static void |
17a2f251 | 15349 | mips_set_architecture (const struct mips_cpu_info *info) |
252b5132 | 15350 | { |
316f5878 | 15351 | if (info != 0) |
252b5132 | 15352 | { |
fef14a42 TS |
15353 | file_mips_arch = info->cpu; |
15354 | mips_opts.arch = info->cpu; | |
316f5878 | 15355 | mips_opts.isa = info->isa; |
252b5132 | 15356 | } |
252b5132 RH |
15357 | } |
15358 | ||
252b5132 | 15359 | |
316f5878 | 15360 | /* Likewise for tuning. */ |
252b5132 | 15361 | |
316f5878 | 15362 | static void |
17a2f251 | 15363 | mips_set_tune (const struct mips_cpu_info *info) |
316f5878 RS |
15364 | { |
15365 | if (info != 0) | |
fef14a42 | 15366 | mips_tune = info->cpu; |
316f5878 | 15367 | } |
80cc45a5 | 15368 | |
34ba82a8 | 15369 | |
252b5132 | 15370 | void |
17a2f251 | 15371 | mips_after_parse_args (void) |
e9670677 | 15372 | { |
fef14a42 TS |
15373 | const struct mips_cpu_info *arch_info = 0; |
15374 | const struct mips_cpu_info *tune_info = 0; | |
15375 | ||
e9670677 | 15376 | /* GP relative stuff not working for PE */ |
6caf9ef4 | 15377 | if (strncmp (TARGET_OS, "pe", 2) == 0) |
e9670677 | 15378 | { |
6caf9ef4 | 15379 | if (g_switch_seen && g_switch_value != 0) |
e9670677 MR |
15380 | as_bad (_("-G not supported in this configuration.")); |
15381 | g_switch_value = 0; | |
15382 | } | |
15383 | ||
cac012d6 AO |
15384 | if (mips_abi == NO_ABI) |
15385 | mips_abi = MIPS_DEFAULT_ABI; | |
15386 | ||
22923709 RS |
15387 | /* The following code determines the architecture and register size. |
15388 | Similar code was added to GCC 3.3 (see override_options() in | |
15389 | config/mips/mips.c). The GAS and GCC code should be kept in sync | |
15390 | as much as possible. */ | |
e9670677 | 15391 | |
316f5878 | 15392 | if (mips_arch_string != 0) |
fef14a42 | 15393 | arch_info = mips_parse_cpu ("-march", mips_arch_string); |
e9670677 | 15394 | |
316f5878 | 15395 | if (file_mips_isa != ISA_UNKNOWN) |
e9670677 | 15396 | { |
316f5878 | 15397 | /* Handle -mipsN. At this point, file_mips_isa contains the |
fef14a42 | 15398 | ISA level specified by -mipsN, while arch_info->isa contains |
316f5878 | 15399 | the -march selection (if any). */ |
fef14a42 | 15400 | if (arch_info != 0) |
e9670677 | 15401 | { |
316f5878 RS |
15402 | /* -march takes precedence over -mipsN, since it is more descriptive. |
15403 | There's no harm in specifying both as long as the ISA levels | |
15404 | are the same. */ | |
fef14a42 | 15405 | if (file_mips_isa != arch_info->isa) |
316f5878 RS |
15406 | as_bad (_("-%s conflicts with the other architecture options, which imply -%s"), |
15407 | mips_cpu_info_from_isa (file_mips_isa)->name, | |
fef14a42 | 15408 | mips_cpu_info_from_isa (arch_info->isa)->name); |
e9670677 | 15409 | } |
316f5878 | 15410 | else |
fef14a42 | 15411 | arch_info = mips_cpu_info_from_isa (file_mips_isa); |
e9670677 MR |
15412 | } |
15413 | ||
fef14a42 | 15414 | if (arch_info == 0) |
95bfe26e MF |
15415 | { |
15416 | arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT); | |
15417 | gas_assert (arch_info); | |
15418 | } | |
e9670677 | 15419 | |
fef14a42 | 15420 | if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa)) |
20203fb9 | 15421 | as_bad (_("-march=%s is not compatible with the selected ABI"), |
fef14a42 TS |
15422 | arch_info->name); |
15423 | ||
15424 | mips_set_architecture (arch_info); | |
15425 | ||
15426 | /* Optimize for file_mips_arch, unless -mtune selects a different processor. */ | |
15427 | if (mips_tune_string != 0) | |
15428 | tune_info = mips_parse_cpu ("-mtune", mips_tune_string); | |
e9670677 | 15429 | |
fef14a42 TS |
15430 | if (tune_info == 0) |
15431 | mips_set_tune (arch_info); | |
15432 | else | |
15433 | mips_set_tune (tune_info); | |
e9670677 | 15434 | |
316f5878 | 15435 | if (file_mips_gp32 >= 0) |
e9670677 | 15436 | { |
316f5878 RS |
15437 | /* The user specified the size of the integer registers. Make sure |
15438 | it agrees with the ABI and ISA. */ | |
15439 | if (file_mips_gp32 == 0 && !ISA_HAS_64BIT_REGS (mips_opts.isa)) | |
15440 | as_bad (_("-mgp64 used with a 32-bit processor")); | |
15441 | else if (file_mips_gp32 == 1 && ABI_NEEDS_64BIT_REGS (mips_abi)) | |
15442 | as_bad (_("-mgp32 used with a 64-bit ABI")); | |
15443 | else if (file_mips_gp32 == 0 && ABI_NEEDS_32BIT_REGS (mips_abi)) | |
15444 | as_bad (_("-mgp64 used with a 32-bit ABI")); | |
e9670677 MR |
15445 | } |
15446 | else | |
15447 | { | |
316f5878 RS |
15448 | /* Infer the integer register size from the ABI and processor. |
15449 | Restrict ourselves to 32-bit registers if that's all the | |
15450 | processor has, or if the ABI cannot handle 64-bit registers. */ | |
15451 | file_mips_gp32 = (ABI_NEEDS_32BIT_REGS (mips_abi) | |
15452 | || !ISA_HAS_64BIT_REGS (mips_opts.isa)); | |
e9670677 MR |
15453 | } |
15454 | ||
ad3fea08 TS |
15455 | switch (file_mips_fp32) |
15456 | { | |
15457 | default: | |
15458 | case -1: | |
15459 | /* No user specified float register size. | |
15460 | ??? GAS treats single-float processors as though they had 64-bit | |
15461 | float registers (although it complains when double-precision | |
15462 | instructions are used). As things stand, saying they have 32-bit | |
15463 | registers would lead to spurious "register must be even" messages. | |
15464 | So here we assume float registers are never smaller than the | |
15465 | integer ones. */ | |
15466 | if (file_mips_gp32 == 0) | |
15467 | /* 64-bit integer registers implies 64-bit float registers. */ | |
15468 | file_mips_fp32 = 0; | |
c6278170 | 15469 | else if ((mips_opts.ase & FP64_ASES) |
ad3fea08 TS |
15470 | && ISA_HAS_64BIT_FPRS (mips_opts.isa)) |
15471 | /* -mips3d and -mdmx imply 64-bit float registers, if possible. */ | |
15472 | file_mips_fp32 = 0; | |
15473 | else | |
15474 | /* 32-bit float registers. */ | |
15475 | file_mips_fp32 = 1; | |
15476 | break; | |
15477 | ||
15478 | /* The user specified the size of the float registers. Check if it | |
15479 | agrees with the ABI and ISA. */ | |
15480 | case 0: | |
15481 | if (!ISA_HAS_64BIT_FPRS (mips_opts.isa)) | |
15482 | as_bad (_("-mfp64 used with a 32-bit fpu")); | |
15483 | else if (ABI_NEEDS_32BIT_REGS (mips_abi) | |
15484 | && !ISA_HAS_MXHC1 (mips_opts.isa)) | |
15485 | as_warn (_("-mfp64 used with a 32-bit ABI")); | |
15486 | break; | |
15487 | case 1: | |
15488 | if (ABI_NEEDS_64BIT_REGS (mips_abi)) | |
15489 | as_warn (_("-mfp32 used with a 64-bit ABI")); | |
15490 | break; | |
15491 | } | |
e9670677 | 15492 | |
316f5878 | 15493 | /* End of GCC-shared inference code. */ |
e9670677 | 15494 | |
17a2f251 TS |
15495 | /* This flag is set when we have a 64-bit capable CPU but use only |
15496 | 32-bit wide registers. Note that EABI does not use it. */ | |
15497 | if (ISA_HAS_64BIT_REGS (mips_opts.isa) | |
15498 | && ((mips_abi == NO_ABI && file_mips_gp32 == 1) | |
15499 | || mips_abi == O32_ABI)) | |
316f5878 | 15500 | mips_32bitmode = 1; |
e9670677 MR |
15501 | |
15502 | if (mips_opts.isa == ISA_MIPS1 && mips_trap) | |
15503 | as_bad (_("trap exception not supported at ISA 1")); | |
15504 | ||
e9670677 MR |
15505 | /* If the selected architecture includes support for ASEs, enable |
15506 | generation of code for them. */ | |
a4672219 | 15507 | if (mips_opts.mips16 == -1) |
fef14a42 | 15508 | mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_arch)) ? 1 : 0; |
df58fc94 RS |
15509 | if (mips_opts.micromips == -1) |
15510 | mips_opts.micromips = (CPU_HAS_MICROMIPS (file_mips_arch)) ? 1 : 0; | |
846ef2d0 RS |
15511 | |
15512 | /* MIPS3D and MDMX require 64-bit FPRs, so -mfp32 should stop those | |
15513 | ASEs from being selected implicitly. */ | |
15514 | if (file_mips_fp32 == 1) | |
15515 | file_ase_explicit |= ASE_MIPS3D | ASE_MDMX; | |
15516 | ||
15517 | /* If the user didn't explicitly select or deselect a particular ASE, | |
15518 | use the default setting for the CPU. */ | |
15519 | mips_opts.ase |= (arch_info->ase & ~file_ase_explicit); | |
15520 | ||
e9670677 | 15521 | file_mips_isa = mips_opts.isa; |
846ef2d0 | 15522 | file_ase = mips_opts.ase; |
e9670677 MR |
15523 | mips_opts.gp32 = file_mips_gp32; |
15524 | mips_opts.fp32 = file_mips_fp32; | |
037b32b9 AN |
15525 | mips_opts.soft_float = file_mips_soft_float; |
15526 | mips_opts.single_float = file_mips_single_float; | |
e9670677 | 15527 | |
c6278170 RS |
15528 | mips_check_isa_supports_ases (); |
15529 | ||
ecb4347a | 15530 | if (mips_flag_mdebug < 0) |
e8044f35 | 15531 | mips_flag_mdebug = 0; |
e9670677 MR |
15532 | } |
15533 | \f | |
15534 | void | |
17a2f251 | 15535 | mips_init_after_args (void) |
252b5132 RH |
15536 | { |
15537 | /* initialize opcodes */ | |
15538 | bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes; | |
beae10d5 | 15539 | mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes; |
252b5132 RH |
15540 | } |
15541 | ||
15542 | long | |
17a2f251 | 15543 | md_pcrel_from (fixS *fixP) |
252b5132 | 15544 | { |
a7ebbfdf TS |
15545 | valueT addr = fixP->fx_where + fixP->fx_frag->fr_address; |
15546 | switch (fixP->fx_r_type) | |
15547 | { | |
df58fc94 RS |
15548 | case BFD_RELOC_MICROMIPS_7_PCREL_S1: |
15549 | case BFD_RELOC_MICROMIPS_10_PCREL_S1: | |
15550 | /* Return the address of the delay slot. */ | |
15551 | return addr + 2; | |
15552 | ||
15553 | case BFD_RELOC_MICROMIPS_16_PCREL_S1: | |
15554 | case BFD_RELOC_MICROMIPS_JMP: | |
a7ebbfdf TS |
15555 | case BFD_RELOC_16_PCREL_S2: |
15556 | case BFD_RELOC_MIPS_JMP: | |
15557 | /* Return the address of the delay slot. */ | |
15558 | return addr + 4; | |
df58fc94 | 15559 | |
b47468a6 CM |
15560 | case BFD_RELOC_32_PCREL: |
15561 | return addr; | |
15562 | ||
a7ebbfdf | 15563 | default: |
58ea3d6a | 15564 | /* We have no relocation type for PC relative MIPS16 instructions. */ |
64817874 TS |
15565 | if (fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != now_seg) |
15566 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15567 | _("PC relative MIPS16 instruction references a different section")); | |
a7ebbfdf TS |
15568 | return addr; |
15569 | } | |
252b5132 RH |
15570 | } |
15571 | ||
252b5132 RH |
15572 | /* This is called before the symbol table is processed. In order to |
15573 | work with gcc when using mips-tfile, we must keep all local labels. | |
15574 | However, in other cases, we want to discard them. If we were | |
15575 | called with -g, but we didn't see any debugging information, it may | |
15576 | mean that gcc is smuggling debugging information through to | |
15577 | mips-tfile, in which case we must generate all local labels. */ | |
15578 | ||
15579 | void | |
17a2f251 | 15580 | mips_frob_file_before_adjust (void) |
252b5132 RH |
15581 | { |
15582 | #ifndef NO_ECOFF_DEBUGGING | |
15583 | if (ECOFF_DEBUGGING | |
15584 | && mips_debug != 0 | |
15585 | && ! ecoff_debugging_seen) | |
15586 | flag_keep_locals = 1; | |
15587 | #endif | |
15588 | } | |
15589 | ||
3b91255e | 15590 | /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede |
55cf6793 | 15591 | the corresponding LO16 reloc. This is called before md_apply_fix and |
3b91255e RS |
15592 | tc_gen_reloc. Unmatched relocs can only be generated by use of explicit |
15593 | relocation operators. | |
15594 | ||
15595 | For our purposes, a %lo() expression matches a %got() or %hi() | |
15596 | expression if: | |
15597 | ||
15598 | (a) it refers to the same symbol; and | |
15599 | (b) the offset applied in the %lo() expression is no lower than | |
15600 | the offset applied in the %got() or %hi(). | |
15601 | ||
15602 | (b) allows us to cope with code like: | |
15603 | ||
15604 | lui $4,%hi(foo) | |
15605 | lh $4,%lo(foo+2)($4) | |
15606 | ||
15607 | ...which is legal on RELA targets, and has a well-defined behaviour | |
15608 | if the user knows that adding 2 to "foo" will not induce a carry to | |
15609 | the high 16 bits. | |
15610 | ||
15611 | When several %lo()s match a particular %got() or %hi(), we use the | |
15612 | following rules to distinguish them: | |
15613 | ||
15614 | (1) %lo()s with smaller offsets are a better match than %lo()s with | |
15615 | higher offsets. | |
15616 | ||
15617 | (2) %lo()s with no matching %got() or %hi() are better than those | |
15618 | that already have a matching %got() or %hi(). | |
15619 | ||
15620 | (3) later %lo()s are better than earlier %lo()s. | |
15621 | ||
15622 | These rules are applied in order. | |
15623 | ||
15624 | (1) means, among other things, that %lo()s with identical offsets are | |
15625 | chosen if they exist. | |
15626 | ||
15627 | (2) means that we won't associate several high-part relocations with | |
15628 | the same low-part relocation unless there's no alternative. Having | |
15629 | several high parts for the same low part is a GNU extension; this rule | |
15630 | allows careful users to avoid it. | |
15631 | ||
15632 | (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order, | |
15633 | with the last high-part relocation being at the front of the list. | |
15634 | It therefore makes sense to choose the last matching low-part | |
15635 | relocation, all other things being equal. It's also easier | |
15636 | to code that way. */ | |
252b5132 RH |
15637 | |
15638 | void | |
17a2f251 | 15639 | mips_frob_file (void) |
252b5132 RH |
15640 | { |
15641 | struct mips_hi_fixup *l; | |
35903be0 | 15642 | bfd_reloc_code_real_type looking_for_rtype = BFD_RELOC_UNUSED; |
252b5132 RH |
15643 | |
15644 | for (l = mips_hi_fixup_list; l != NULL; l = l->next) | |
15645 | { | |
15646 | segment_info_type *seginfo; | |
3b91255e RS |
15647 | bfd_boolean matched_lo_p; |
15648 | fixS **hi_pos, **lo_pos, **pos; | |
252b5132 | 15649 | |
9c2799c2 | 15650 | gas_assert (reloc_needs_lo_p (l->fixp->fx_r_type)); |
252b5132 | 15651 | |
5919d012 | 15652 | /* If a GOT16 relocation turns out to be against a global symbol, |
b886a2ab RS |
15653 | there isn't supposed to be a matching LO. Ignore %gots against |
15654 | constants; we'll report an error for those later. */ | |
738e5348 | 15655 | if (got16_reloc_p (l->fixp->fx_r_type) |
b886a2ab RS |
15656 | && !(l->fixp->fx_addsy |
15657 | && pic_need_relax (l->fixp->fx_addsy, l->seg))) | |
5919d012 RS |
15658 | continue; |
15659 | ||
15660 | /* Check quickly whether the next fixup happens to be a matching %lo. */ | |
15661 | if (fixup_has_matching_lo_p (l->fixp)) | |
252b5132 RH |
15662 | continue; |
15663 | ||
252b5132 | 15664 | seginfo = seg_info (l->seg); |
252b5132 | 15665 | |
3b91255e RS |
15666 | /* Set HI_POS to the position of this relocation in the chain. |
15667 | Set LO_POS to the position of the chosen low-part relocation. | |
15668 | MATCHED_LO_P is true on entry to the loop if *POS is a low-part | |
15669 | relocation that matches an immediately-preceding high-part | |
15670 | relocation. */ | |
15671 | hi_pos = NULL; | |
15672 | lo_pos = NULL; | |
15673 | matched_lo_p = FALSE; | |
738e5348 | 15674 | looking_for_rtype = matching_lo_reloc (l->fixp->fx_r_type); |
35903be0 | 15675 | |
3b91255e RS |
15676 | for (pos = &seginfo->fix_root; *pos != NULL; pos = &(*pos)->fx_next) |
15677 | { | |
15678 | if (*pos == l->fixp) | |
15679 | hi_pos = pos; | |
15680 | ||
35903be0 | 15681 | if ((*pos)->fx_r_type == looking_for_rtype |
30cfc97a | 15682 | && symbol_same_p ((*pos)->fx_addsy, l->fixp->fx_addsy) |
3b91255e RS |
15683 | && (*pos)->fx_offset >= l->fixp->fx_offset |
15684 | && (lo_pos == NULL | |
15685 | || (*pos)->fx_offset < (*lo_pos)->fx_offset | |
15686 | || (!matched_lo_p | |
15687 | && (*pos)->fx_offset == (*lo_pos)->fx_offset))) | |
15688 | lo_pos = pos; | |
15689 | ||
15690 | matched_lo_p = (reloc_needs_lo_p ((*pos)->fx_r_type) | |
15691 | && fixup_has_matching_lo_p (*pos)); | |
15692 | } | |
15693 | ||
15694 | /* If we found a match, remove the high-part relocation from its | |
15695 | current position and insert it before the low-part relocation. | |
15696 | Make the offsets match so that fixup_has_matching_lo_p() | |
15697 | will return true. | |
15698 | ||
15699 | We don't warn about unmatched high-part relocations since some | |
15700 | versions of gcc have been known to emit dead "lui ...%hi(...)" | |
15701 | instructions. */ | |
15702 | if (lo_pos != NULL) | |
15703 | { | |
15704 | l->fixp->fx_offset = (*lo_pos)->fx_offset; | |
15705 | if (l->fixp->fx_next != *lo_pos) | |
252b5132 | 15706 | { |
3b91255e RS |
15707 | *hi_pos = l->fixp->fx_next; |
15708 | l->fixp->fx_next = *lo_pos; | |
15709 | *lo_pos = l->fixp; | |
252b5132 | 15710 | } |
252b5132 RH |
15711 | } |
15712 | } | |
15713 | } | |
15714 | ||
252b5132 | 15715 | int |
17a2f251 | 15716 | mips_force_relocation (fixS *fixp) |
252b5132 | 15717 | { |
ae6063d4 | 15718 | if (generic_force_reloc (fixp)) |
252b5132 RH |
15719 | return 1; |
15720 | ||
df58fc94 RS |
15721 | /* We want to keep BFD_RELOC_MICROMIPS_*_PCREL_S1 relocation, |
15722 | so that the linker relaxation can update targets. */ | |
15723 | if (fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1 | |
15724 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1 | |
15725 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1) | |
15726 | return 1; | |
15727 | ||
3e722fb5 | 15728 | return 0; |
252b5132 RH |
15729 | } |
15730 | ||
b886a2ab RS |
15731 | /* Read the instruction associated with RELOC from BUF. */ |
15732 | ||
15733 | static unsigned int | |
15734 | read_reloc_insn (char *buf, bfd_reloc_code_real_type reloc) | |
15735 | { | |
15736 | if (mips16_reloc_p (reloc) || micromips_reloc_p (reloc)) | |
15737 | return read_compressed_insn (buf, 4); | |
15738 | else | |
15739 | return read_insn (buf); | |
15740 | } | |
15741 | ||
15742 | /* Write instruction INSN to BUF, given that it has been relocated | |
15743 | by RELOC. */ | |
15744 | ||
15745 | static void | |
15746 | write_reloc_insn (char *buf, bfd_reloc_code_real_type reloc, | |
15747 | unsigned long insn) | |
15748 | { | |
15749 | if (mips16_reloc_p (reloc) || micromips_reloc_p (reloc)) | |
15750 | write_compressed_insn (buf, insn, 4); | |
15751 | else | |
15752 | write_insn (buf, insn); | |
15753 | } | |
15754 | ||
252b5132 RH |
15755 | /* Apply a fixup to the object file. */ |
15756 | ||
94f592af | 15757 | void |
55cf6793 | 15758 | md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) |
252b5132 | 15759 | { |
4d68580a | 15760 | char *buf; |
b886a2ab | 15761 | unsigned long insn; |
a7ebbfdf | 15762 | reloc_howto_type *howto; |
252b5132 | 15763 | |
a7ebbfdf TS |
15764 | /* We ignore generic BFD relocations we don't know about. */ |
15765 | howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type); | |
15766 | if (! howto) | |
15767 | return; | |
65551fa4 | 15768 | |
df58fc94 RS |
15769 | gas_assert (fixP->fx_size == 2 |
15770 | || fixP->fx_size == 4 | |
90ecf173 MR |
15771 | || fixP->fx_r_type == BFD_RELOC_16 |
15772 | || fixP->fx_r_type == BFD_RELOC_64 | |
15773 | || fixP->fx_r_type == BFD_RELOC_CTOR | |
15774 | || fixP->fx_r_type == BFD_RELOC_MIPS_SUB | |
df58fc94 | 15775 | || fixP->fx_r_type == BFD_RELOC_MICROMIPS_SUB |
90ecf173 MR |
15776 | || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
15777 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY | |
15778 | || fixP->fx_r_type == BFD_RELOC_MIPS_TLS_DTPREL64); | |
252b5132 | 15779 | |
4d68580a | 15780 | buf = fixP->fx_frag->fr_literal + fixP->fx_where; |
252b5132 | 15781 | |
df58fc94 RS |
15782 | gas_assert (!fixP->fx_pcrel || fixP->fx_r_type == BFD_RELOC_16_PCREL_S2 |
15783 | || fixP->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1 | |
15784 | || fixP->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1 | |
b47468a6 CM |
15785 | || fixP->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1 |
15786 | || fixP->fx_r_type == BFD_RELOC_32_PCREL); | |
b1dca8ee RS |
15787 | |
15788 | /* Don't treat parts of a composite relocation as done. There are two | |
15789 | reasons for this: | |
15790 | ||
15791 | (1) The second and third parts will be against 0 (RSS_UNDEF) but | |
15792 | should nevertheless be emitted if the first part is. | |
15793 | ||
15794 | (2) In normal usage, composite relocations are never assembly-time | |
15795 | constants. The easiest way of dealing with the pathological | |
15796 | exceptions is to generate a relocation against STN_UNDEF and | |
15797 | leave everything up to the linker. */ | |
3994f87e | 15798 | if (fixP->fx_addsy == NULL && !fixP->fx_pcrel && fixP->fx_tcbit == 0) |
252b5132 RH |
15799 | fixP->fx_done = 1; |
15800 | ||
15801 | switch (fixP->fx_r_type) | |
15802 | { | |
3f98094e DJ |
15803 | case BFD_RELOC_MIPS_TLS_GD: |
15804 | case BFD_RELOC_MIPS_TLS_LDM: | |
741d6ea8 JM |
15805 | case BFD_RELOC_MIPS_TLS_DTPREL32: |
15806 | case BFD_RELOC_MIPS_TLS_DTPREL64: | |
3f98094e DJ |
15807 | case BFD_RELOC_MIPS_TLS_DTPREL_HI16: |
15808 | case BFD_RELOC_MIPS_TLS_DTPREL_LO16: | |
15809 | case BFD_RELOC_MIPS_TLS_GOTTPREL: | |
d0f13682 CLT |
15810 | case BFD_RELOC_MIPS_TLS_TPREL32: |
15811 | case BFD_RELOC_MIPS_TLS_TPREL64: | |
3f98094e DJ |
15812 | case BFD_RELOC_MIPS_TLS_TPREL_HI16: |
15813 | case BFD_RELOC_MIPS_TLS_TPREL_LO16: | |
df58fc94 RS |
15814 | case BFD_RELOC_MICROMIPS_TLS_GD: |
15815 | case BFD_RELOC_MICROMIPS_TLS_LDM: | |
15816 | case BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16: | |
15817 | case BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16: | |
15818 | case BFD_RELOC_MICROMIPS_TLS_GOTTPREL: | |
15819 | case BFD_RELOC_MICROMIPS_TLS_TPREL_HI16: | |
15820 | case BFD_RELOC_MICROMIPS_TLS_TPREL_LO16: | |
d0f13682 CLT |
15821 | case BFD_RELOC_MIPS16_TLS_GD: |
15822 | case BFD_RELOC_MIPS16_TLS_LDM: | |
15823 | case BFD_RELOC_MIPS16_TLS_DTPREL_HI16: | |
15824 | case BFD_RELOC_MIPS16_TLS_DTPREL_LO16: | |
15825 | case BFD_RELOC_MIPS16_TLS_GOTTPREL: | |
15826 | case BFD_RELOC_MIPS16_TLS_TPREL_HI16: | |
15827 | case BFD_RELOC_MIPS16_TLS_TPREL_LO16: | |
b886a2ab RS |
15828 | if (!fixP->fx_addsy) |
15829 | { | |
15830 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15831 | _("TLS relocation against a constant")); | |
15832 | break; | |
15833 | } | |
3f98094e DJ |
15834 | S_SET_THREAD_LOCAL (fixP->fx_addsy); |
15835 | /* fall through */ | |
15836 | ||
252b5132 | 15837 | case BFD_RELOC_MIPS_JMP: |
e369bcce TS |
15838 | case BFD_RELOC_MIPS_SHIFT5: |
15839 | case BFD_RELOC_MIPS_SHIFT6: | |
15840 | case BFD_RELOC_MIPS_GOT_DISP: | |
15841 | case BFD_RELOC_MIPS_GOT_PAGE: | |
15842 | case BFD_RELOC_MIPS_GOT_OFST: | |
15843 | case BFD_RELOC_MIPS_SUB: | |
15844 | case BFD_RELOC_MIPS_INSERT_A: | |
15845 | case BFD_RELOC_MIPS_INSERT_B: | |
15846 | case BFD_RELOC_MIPS_DELETE: | |
15847 | case BFD_RELOC_MIPS_HIGHEST: | |
15848 | case BFD_RELOC_MIPS_HIGHER: | |
15849 | case BFD_RELOC_MIPS_SCN_DISP: | |
15850 | case BFD_RELOC_MIPS_REL16: | |
15851 | case BFD_RELOC_MIPS_RELGOT: | |
15852 | case BFD_RELOC_MIPS_JALR: | |
252b5132 RH |
15853 | case BFD_RELOC_HI16: |
15854 | case BFD_RELOC_HI16_S: | |
b886a2ab | 15855 | case BFD_RELOC_LO16: |
cdf6fd85 | 15856 | case BFD_RELOC_GPREL16: |
252b5132 RH |
15857 | case BFD_RELOC_MIPS_LITERAL: |
15858 | case BFD_RELOC_MIPS_CALL16: | |
15859 | case BFD_RELOC_MIPS_GOT16: | |
cdf6fd85 | 15860 | case BFD_RELOC_GPREL32: |
252b5132 RH |
15861 | case BFD_RELOC_MIPS_GOT_HI16: |
15862 | case BFD_RELOC_MIPS_GOT_LO16: | |
15863 | case BFD_RELOC_MIPS_CALL_HI16: | |
15864 | case BFD_RELOC_MIPS_CALL_LO16: | |
15865 | case BFD_RELOC_MIPS16_GPREL: | |
738e5348 RS |
15866 | case BFD_RELOC_MIPS16_GOT16: |
15867 | case BFD_RELOC_MIPS16_CALL16: | |
d6f16593 MR |
15868 | case BFD_RELOC_MIPS16_HI16: |
15869 | case BFD_RELOC_MIPS16_HI16_S: | |
b886a2ab | 15870 | case BFD_RELOC_MIPS16_LO16: |
252b5132 | 15871 | case BFD_RELOC_MIPS16_JMP: |
df58fc94 RS |
15872 | case BFD_RELOC_MICROMIPS_JMP: |
15873 | case BFD_RELOC_MICROMIPS_GOT_DISP: | |
15874 | case BFD_RELOC_MICROMIPS_GOT_PAGE: | |
15875 | case BFD_RELOC_MICROMIPS_GOT_OFST: | |
15876 | case BFD_RELOC_MICROMIPS_SUB: | |
15877 | case BFD_RELOC_MICROMIPS_HIGHEST: | |
15878 | case BFD_RELOC_MICROMIPS_HIGHER: | |
15879 | case BFD_RELOC_MICROMIPS_SCN_DISP: | |
15880 | case BFD_RELOC_MICROMIPS_JALR: | |
15881 | case BFD_RELOC_MICROMIPS_HI16: | |
15882 | case BFD_RELOC_MICROMIPS_HI16_S: | |
b886a2ab | 15883 | case BFD_RELOC_MICROMIPS_LO16: |
df58fc94 RS |
15884 | case BFD_RELOC_MICROMIPS_GPREL16: |
15885 | case BFD_RELOC_MICROMIPS_LITERAL: | |
15886 | case BFD_RELOC_MICROMIPS_CALL16: | |
15887 | case BFD_RELOC_MICROMIPS_GOT16: | |
15888 | case BFD_RELOC_MICROMIPS_GOT_HI16: | |
15889 | case BFD_RELOC_MICROMIPS_GOT_LO16: | |
15890 | case BFD_RELOC_MICROMIPS_CALL_HI16: | |
15891 | case BFD_RELOC_MICROMIPS_CALL_LO16: | |
067ec077 | 15892 | case BFD_RELOC_MIPS_EH: |
b886a2ab RS |
15893 | if (fixP->fx_done) |
15894 | { | |
15895 | offsetT value; | |
15896 | ||
15897 | if (calculate_reloc (fixP->fx_r_type, *valP, &value)) | |
15898 | { | |
15899 | insn = read_reloc_insn (buf, fixP->fx_r_type); | |
15900 | if (mips16_reloc_p (fixP->fx_r_type)) | |
15901 | insn |= mips16_immed_extend (value, 16); | |
15902 | else | |
15903 | insn |= (value & 0xffff); | |
15904 | write_reloc_insn (buf, fixP->fx_r_type, insn); | |
15905 | } | |
15906 | else | |
15907 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15908 | _("Unsupported constant in relocation")); | |
15909 | } | |
252b5132 RH |
15910 | break; |
15911 | ||
252b5132 RH |
15912 | case BFD_RELOC_64: |
15913 | /* This is handled like BFD_RELOC_32, but we output a sign | |
15914 | extended value if we are only 32 bits. */ | |
3e722fb5 | 15915 | if (fixP->fx_done) |
252b5132 RH |
15916 | { |
15917 | if (8 <= sizeof (valueT)) | |
4d68580a | 15918 | md_number_to_chars (buf, *valP, 8); |
252b5132 RH |
15919 | else |
15920 | { | |
a7ebbfdf | 15921 | valueT hiv; |
252b5132 | 15922 | |
a7ebbfdf | 15923 | if ((*valP & 0x80000000) != 0) |
252b5132 RH |
15924 | hiv = 0xffffffff; |
15925 | else | |
15926 | hiv = 0; | |
4d68580a RS |
15927 | md_number_to_chars (buf + (target_big_endian ? 4 : 0), *valP, 4); |
15928 | md_number_to_chars (buf + (target_big_endian ? 0 : 4), hiv, 4); | |
252b5132 RH |
15929 | } |
15930 | } | |
15931 | break; | |
15932 | ||
056350c6 | 15933 | case BFD_RELOC_RVA: |
252b5132 | 15934 | case BFD_RELOC_32: |
b47468a6 | 15935 | case BFD_RELOC_32_PCREL: |
252b5132 RH |
15936 | case BFD_RELOC_16: |
15937 | /* If we are deleting this reloc entry, we must fill in the | |
54f4ddb3 TS |
15938 | value now. This can happen if we have a .word which is not |
15939 | resolved when it appears but is later defined. */ | |
252b5132 | 15940 | if (fixP->fx_done) |
4d68580a | 15941 | md_number_to_chars (buf, *valP, fixP->fx_size); |
252b5132 RH |
15942 | break; |
15943 | ||
252b5132 | 15944 | case BFD_RELOC_16_PCREL_S2: |
a7ebbfdf | 15945 | if ((*valP & 0x3) != 0) |
cb56d3d3 | 15946 | as_bad_where (fixP->fx_file, fixP->fx_line, |
bad36eac | 15947 | _("Branch to misaligned address (%lx)"), (long) *valP); |
cb56d3d3 | 15948 | |
54f4ddb3 TS |
15949 | /* We need to save the bits in the instruction since fixup_segment() |
15950 | might be deleting the relocation entry (i.e., a branch within | |
15951 | the current segment). */ | |
a7ebbfdf | 15952 | if (! fixP->fx_done) |
bb2d6cd7 | 15953 | break; |
252b5132 | 15954 | |
54f4ddb3 | 15955 | /* Update old instruction data. */ |
4d68580a | 15956 | insn = read_insn (buf); |
252b5132 | 15957 | |
a7ebbfdf TS |
15958 | if (*valP + 0x20000 <= 0x3ffff) |
15959 | { | |
15960 | insn |= (*valP >> 2) & 0xffff; | |
4d68580a | 15961 | write_insn (buf, insn); |
a7ebbfdf TS |
15962 | } |
15963 | else if (mips_pic == NO_PIC | |
15964 | && fixP->fx_done | |
15965 | && fixP->fx_frag->fr_address >= text_section->vma | |
15966 | && (fixP->fx_frag->fr_address | |
587aac4e | 15967 | < text_section->vma + bfd_get_section_size (text_section)) |
a7ebbfdf TS |
15968 | && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */ |
15969 | || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */ | |
15970 | || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */ | |
252b5132 RH |
15971 | { |
15972 | /* The branch offset is too large. If this is an | |
15973 | unconditional branch, and we are not generating PIC code, | |
15974 | we can convert it to an absolute jump instruction. */ | |
a7ebbfdf TS |
15975 | if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */ |
15976 | insn = 0x0c000000; /* jal */ | |
252b5132 | 15977 | else |
a7ebbfdf TS |
15978 | insn = 0x08000000; /* j */ |
15979 | fixP->fx_r_type = BFD_RELOC_MIPS_JMP; | |
15980 | fixP->fx_done = 0; | |
15981 | fixP->fx_addsy = section_symbol (text_section); | |
15982 | *valP += md_pcrel_from (fixP); | |
4d68580a | 15983 | write_insn (buf, insn); |
a7ebbfdf TS |
15984 | } |
15985 | else | |
15986 | { | |
15987 | /* If we got here, we have branch-relaxation disabled, | |
15988 | and there's nothing we can do to fix this instruction | |
15989 | without turning it into a longer sequence. */ | |
15990 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15991 | _("Branch out of range")); | |
252b5132 | 15992 | } |
252b5132 RH |
15993 | break; |
15994 | ||
df58fc94 RS |
15995 | case BFD_RELOC_MICROMIPS_7_PCREL_S1: |
15996 | case BFD_RELOC_MICROMIPS_10_PCREL_S1: | |
15997 | case BFD_RELOC_MICROMIPS_16_PCREL_S1: | |
15998 | /* We adjust the offset back to even. */ | |
15999 | if ((*valP & 0x1) != 0) | |
16000 | --(*valP); | |
16001 | ||
16002 | if (! fixP->fx_done) | |
16003 | break; | |
16004 | ||
16005 | /* Should never visit here, because we keep the relocation. */ | |
16006 | abort (); | |
16007 | break; | |
16008 | ||
252b5132 RH |
16009 | case BFD_RELOC_VTABLE_INHERIT: |
16010 | fixP->fx_done = 0; | |
16011 | if (fixP->fx_addsy | |
16012 | && !S_IS_DEFINED (fixP->fx_addsy) | |
16013 | && !S_IS_WEAK (fixP->fx_addsy)) | |
16014 | S_SET_WEAK (fixP->fx_addsy); | |
16015 | break; | |
16016 | ||
16017 | case BFD_RELOC_VTABLE_ENTRY: | |
16018 | fixP->fx_done = 0; | |
16019 | break; | |
16020 | ||
16021 | default: | |
b37df7c4 | 16022 | abort (); |
252b5132 | 16023 | } |
a7ebbfdf TS |
16024 | |
16025 | /* Remember value for tc_gen_reloc. */ | |
16026 | fixP->fx_addnumber = *valP; | |
252b5132 RH |
16027 | } |
16028 | ||
252b5132 | 16029 | static symbolS * |
17a2f251 | 16030 | get_symbol (void) |
252b5132 RH |
16031 | { |
16032 | int c; | |
16033 | char *name; | |
16034 | symbolS *p; | |
16035 | ||
16036 | name = input_line_pointer; | |
16037 | c = get_symbol_end (); | |
16038 | p = (symbolS *) symbol_find_or_make (name); | |
16039 | *input_line_pointer = c; | |
16040 | return p; | |
16041 | } | |
16042 | ||
742a56fe RS |
16043 | /* Align the current frag to a given power of two. If a particular |
16044 | fill byte should be used, FILL points to an integer that contains | |
16045 | that byte, otherwise FILL is null. | |
16046 | ||
462427c4 RS |
16047 | This function used to have the comment: |
16048 | ||
16049 | The MIPS assembler also automatically adjusts any preceding label. | |
16050 | ||
16051 | The implementation therefore applied the adjustment to a maximum of | |
16052 | one label. However, other label adjustments are applied to batches | |
16053 | of labels, and adjusting just one caused problems when new labels | |
16054 | were added for the sake of debugging or unwind information. | |
16055 | We therefore adjust all preceding labels (given as LABELS) instead. */ | |
252b5132 RH |
16056 | |
16057 | static void | |
462427c4 | 16058 | mips_align (int to, int *fill, struct insn_label_list *labels) |
252b5132 | 16059 | { |
7d10b47d | 16060 | mips_emit_delays (); |
df58fc94 | 16061 | mips_record_compressed_mode (); |
742a56fe RS |
16062 | if (fill == NULL && subseg_text_p (now_seg)) |
16063 | frag_align_code (to, 0); | |
16064 | else | |
16065 | frag_align (to, fill ? *fill : 0, 0); | |
252b5132 | 16066 | record_alignment (now_seg, to); |
462427c4 | 16067 | mips_move_labels (labels, FALSE); |
252b5132 RH |
16068 | } |
16069 | ||
16070 | /* Align to a given power of two. .align 0 turns off the automatic | |
16071 | alignment used by the data creating pseudo-ops. */ | |
16072 | ||
16073 | static void | |
17a2f251 | 16074 | s_align (int x ATTRIBUTE_UNUSED) |
252b5132 | 16075 | { |
742a56fe | 16076 | int temp, fill_value, *fill_ptr; |
49954fb4 | 16077 | long max_alignment = 28; |
252b5132 | 16078 | |
54f4ddb3 | 16079 | /* o Note that the assembler pulls down any immediately preceding label |
252b5132 | 16080 | to the aligned address. |
54f4ddb3 | 16081 | o It's not documented but auto alignment is reinstated by |
252b5132 | 16082 | a .align pseudo instruction. |
54f4ddb3 | 16083 | o Note also that after auto alignment is turned off the mips assembler |
252b5132 | 16084 | issues an error on attempt to assemble an improperly aligned data item. |
54f4ddb3 | 16085 | We don't. */ |
252b5132 RH |
16086 | |
16087 | temp = get_absolute_expression (); | |
16088 | if (temp > max_alignment) | |
16089 | as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment); | |
16090 | else if (temp < 0) | |
16091 | { | |
16092 | as_warn (_("Alignment negative: 0 assumed.")); | |
16093 | temp = 0; | |
16094 | } | |
16095 | if (*input_line_pointer == ',') | |
16096 | { | |
f9419b05 | 16097 | ++input_line_pointer; |
742a56fe RS |
16098 | fill_value = get_absolute_expression (); |
16099 | fill_ptr = &fill_value; | |
252b5132 RH |
16100 | } |
16101 | else | |
742a56fe | 16102 | fill_ptr = 0; |
252b5132 RH |
16103 | if (temp) |
16104 | { | |
a8dbcb85 TS |
16105 | segment_info_type *si = seg_info (now_seg); |
16106 | struct insn_label_list *l = si->label_list; | |
54f4ddb3 | 16107 | /* Auto alignment should be switched on by next section change. */ |
252b5132 | 16108 | auto_align = 1; |
462427c4 | 16109 | mips_align (temp, fill_ptr, l); |
252b5132 RH |
16110 | } |
16111 | else | |
16112 | { | |
16113 | auto_align = 0; | |
16114 | } | |
16115 | ||
16116 | demand_empty_rest_of_line (); | |
16117 | } | |
16118 | ||
252b5132 | 16119 | static void |
17a2f251 | 16120 | s_change_sec (int sec) |
252b5132 RH |
16121 | { |
16122 | segT seg; | |
16123 | ||
252b5132 RH |
16124 | /* The ELF backend needs to know that we are changing sections, so |
16125 | that .previous works correctly. We could do something like check | |
b6ff326e | 16126 | for an obj_section_change_hook macro, but that might be confusing |
252b5132 RH |
16127 | as it would not be appropriate to use it in the section changing |
16128 | functions in read.c, since obj-elf.c intercepts those. FIXME: | |
16129 | This should be cleaner, somehow. */ | |
f3ded42a | 16130 | obj_elf_section_change_hook (); |
252b5132 | 16131 | |
7d10b47d | 16132 | mips_emit_delays (); |
6a32d874 | 16133 | |
252b5132 RH |
16134 | switch (sec) |
16135 | { | |
16136 | case 't': | |
16137 | s_text (0); | |
16138 | break; | |
16139 | case 'd': | |
16140 | s_data (0); | |
16141 | break; | |
16142 | case 'b': | |
16143 | subseg_set (bss_section, (subsegT) get_absolute_expression ()); | |
16144 | demand_empty_rest_of_line (); | |
16145 | break; | |
16146 | ||
16147 | case 'r': | |
4d0d148d TS |
16148 | seg = subseg_new (RDATA_SECTION_NAME, |
16149 | (subsegT) get_absolute_expression ()); | |
f3ded42a RS |
16150 | bfd_set_section_flags (stdoutput, seg, (SEC_ALLOC | SEC_LOAD |
16151 | | SEC_READONLY | SEC_RELOC | |
16152 | | SEC_DATA)); | |
16153 | if (strncmp (TARGET_OS, "elf", 3) != 0) | |
16154 | record_alignment (seg, 4); | |
4d0d148d | 16155 | demand_empty_rest_of_line (); |
252b5132 RH |
16156 | break; |
16157 | ||
16158 | case 's': | |
4d0d148d | 16159 | seg = subseg_new (".sdata", (subsegT) get_absolute_expression ()); |
f3ded42a RS |
16160 | bfd_set_section_flags (stdoutput, seg, |
16161 | SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA); | |
16162 | if (strncmp (TARGET_OS, "elf", 3) != 0) | |
16163 | record_alignment (seg, 4); | |
4d0d148d TS |
16164 | demand_empty_rest_of_line (); |
16165 | break; | |
998b3c36 MR |
16166 | |
16167 | case 'B': | |
16168 | seg = subseg_new (".sbss", (subsegT) get_absolute_expression ()); | |
f3ded42a RS |
16169 | bfd_set_section_flags (stdoutput, seg, SEC_ALLOC); |
16170 | if (strncmp (TARGET_OS, "elf", 3) != 0) | |
16171 | record_alignment (seg, 4); | |
998b3c36 MR |
16172 | demand_empty_rest_of_line (); |
16173 | break; | |
252b5132 RH |
16174 | } |
16175 | ||
16176 | auto_align = 1; | |
16177 | } | |
b34976b6 | 16178 | |
cca86cc8 | 16179 | void |
17a2f251 | 16180 | s_change_section (int ignore ATTRIBUTE_UNUSED) |
cca86cc8 | 16181 | { |
cca86cc8 SC |
16182 | char *section_name; |
16183 | char c; | |
684022ea | 16184 | char next_c = 0; |
cca86cc8 SC |
16185 | int section_type; |
16186 | int section_flag; | |
16187 | int section_entry_size; | |
16188 | int section_alignment; | |
b34976b6 | 16189 | |
cca86cc8 SC |
16190 | section_name = input_line_pointer; |
16191 | c = get_symbol_end (); | |
a816d1ed AO |
16192 | if (c) |
16193 | next_c = *(input_line_pointer + 1); | |
cca86cc8 | 16194 | |
4cf0dd0d TS |
16195 | /* Do we have .section Name<,"flags">? */ |
16196 | if (c != ',' || (c == ',' && next_c == '"')) | |
cca86cc8 | 16197 | { |
4cf0dd0d TS |
16198 | /* just after name is now '\0'. */ |
16199 | *input_line_pointer = c; | |
cca86cc8 SC |
16200 | input_line_pointer = section_name; |
16201 | obj_elf_section (ignore); | |
16202 | return; | |
16203 | } | |
16204 | input_line_pointer++; | |
16205 | ||
16206 | /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */ | |
16207 | if (c == ',') | |
16208 | section_type = get_absolute_expression (); | |
16209 | else | |
16210 | section_type = 0; | |
16211 | if (*input_line_pointer++ == ',') | |
16212 | section_flag = get_absolute_expression (); | |
16213 | else | |
16214 | section_flag = 0; | |
16215 | if (*input_line_pointer++ == ',') | |
16216 | section_entry_size = get_absolute_expression (); | |
16217 | else | |
16218 | section_entry_size = 0; | |
16219 | if (*input_line_pointer++ == ',') | |
16220 | section_alignment = get_absolute_expression (); | |
16221 | else | |
16222 | section_alignment = 0; | |
87975d2a AM |
16223 | /* FIXME: really ignore? */ |
16224 | (void) section_alignment; | |
cca86cc8 | 16225 | |
a816d1ed AO |
16226 | section_name = xstrdup (section_name); |
16227 | ||
8ab8a5c8 RS |
16228 | /* When using the generic form of .section (as implemented by obj-elf.c), |
16229 | there's no way to set the section type to SHT_MIPS_DWARF. Users have | |
16230 | traditionally had to fall back on the more common @progbits instead. | |
16231 | ||
16232 | There's nothing really harmful in this, since bfd will correct | |
16233 | SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it | |
708587a4 | 16234 | means that, for backwards compatibility, the special_section entries |
8ab8a5c8 RS |
16235 | for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF. |
16236 | ||
16237 | Even so, we shouldn't force users of the MIPS .section syntax to | |
16238 | incorrectly label the sections as SHT_PROGBITS. The best compromise | |
16239 | seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the | |
16240 | generic type-checking code. */ | |
16241 | if (section_type == SHT_MIPS_DWARF) | |
16242 | section_type = SHT_PROGBITS; | |
16243 | ||
cca86cc8 SC |
16244 | obj_elf_change_section (section_name, section_type, section_flag, |
16245 | section_entry_size, 0, 0, 0); | |
a816d1ed AO |
16246 | |
16247 | if (now_seg->name != section_name) | |
16248 | free (section_name); | |
cca86cc8 | 16249 | } |
252b5132 RH |
16250 | |
16251 | void | |
17a2f251 | 16252 | mips_enable_auto_align (void) |
252b5132 RH |
16253 | { |
16254 | auto_align = 1; | |
16255 | } | |
16256 | ||
16257 | static void | |
17a2f251 | 16258 | s_cons (int log_size) |
252b5132 | 16259 | { |
a8dbcb85 TS |
16260 | segment_info_type *si = seg_info (now_seg); |
16261 | struct insn_label_list *l = si->label_list; | |
252b5132 | 16262 | |
7d10b47d | 16263 | mips_emit_delays (); |
252b5132 | 16264 | if (log_size > 0 && auto_align) |
462427c4 | 16265 | mips_align (log_size, 0, l); |
252b5132 | 16266 | cons (1 << log_size); |
a1facbec | 16267 | mips_clear_insn_labels (); |
252b5132 RH |
16268 | } |
16269 | ||
16270 | static void | |
17a2f251 | 16271 | s_float_cons (int type) |
252b5132 | 16272 | { |
a8dbcb85 TS |
16273 | segment_info_type *si = seg_info (now_seg); |
16274 | struct insn_label_list *l = si->label_list; | |
252b5132 | 16275 | |
7d10b47d | 16276 | mips_emit_delays (); |
252b5132 RH |
16277 | |
16278 | if (auto_align) | |
49309057 ILT |
16279 | { |
16280 | if (type == 'd') | |
462427c4 | 16281 | mips_align (3, 0, l); |
49309057 | 16282 | else |
462427c4 | 16283 | mips_align (2, 0, l); |
49309057 | 16284 | } |
252b5132 | 16285 | |
252b5132 | 16286 | float_cons (type); |
a1facbec | 16287 | mips_clear_insn_labels (); |
252b5132 RH |
16288 | } |
16289 | ||
16290 | /* Handle .globl. We need to override it because on Irix 5 you are | |
16291 | permitted to say | |
16292 | .globl foo .text | |
16293 | where foo is an undefined symbol, to mean that foo should be | |
16294 | considered to be the address of a function. */ | |
16295 | ||
16296 | static void | |
17a2f251 | 16297 | s_mips_globl (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
16298 | { |
16299 | char *name; | |
16300 | int c; | |
16301 | symbolS *symbolP; | |
16302 | flagword flag; | |
16303 | ||
8a06b769 | 16304 | do |
252b5132 | 16305 | { |
8a06b769 | 16306 | name = input_line_pointer; |
252b5132 | 16307 | c = get_symbol_end (); |
8a06b769 TS |
16308 | symbolP = symbol_find_or_make (name); |
16309 | S_SET_EXTERNAL (symbolP); | |
16310 | ||
252b5132 | 16311 | *input_line_pointer = c; |
8a06b769 | 16312 | SKIP_WHITESPACE (); |
252b5132 | 16313 | |
8a06b769 TS |
16314 | /* On Irix 5, every global symbol that is not explicitly labelled as |
16315 | being a function is apparently labelled as being an object. */ | |
16316 | flag = BSF_OBJECT; | |
252b5132 | 16317 | |
8a06b769 TS |
16318 | if (!is_end_of_line[(unsigned char) *input_line_pointer] |
16319 | && (*input_line_pointer != ',')) | |
16320 | { | |
16321 | char *secname; | |
16322 | asection *sec; | |
16323 | ||
16324 | secname = input_line_pointer; | |
16325 | c = get_symbol_end (); | |
16326 | sec = bfd_get_section_by_name (stdoutput, secname); | |
16327 | if (sec == NULL) | |
16328 | as_bad (_("%s: no such section"), secname); | |
16329 | *input_line_pointer = c; | |
16330 | ||
16331 | if (sec != NULL && (sec->flags & SEC_CODE) != 0) | |
16332 | flag = BSF_FUNCTION; | |
16333 | } | |
16334 | ||
16335 | symbol_get_bfdsym (symbolP)->flags |= flag; | |
16336 | ||
16337 | c = *input_line_pointer; | |
16338 | if (c == ',') | |
16339 | { | |
16340 | input_line_pointer++; | |
16341 | SKIP_WHITESPACE (); | |
16342 | if (is_end_of_line[(unsigned char) *input_line_pointer]) | |
16343 | c = '\n'; | |
16344 | } | |
16345 | } | |
16346 | while (c == ','); | |
252b5132 | 16347 | |
252b5132 RH |
16348 | demand_empty_rest_of_line (); |
16349 | } | |
16350 | ||
16351 | static void | |
17a2f251 | 16352 | s_option (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
16353 | { |
16354 | char *opt; | |
16355 | char c; | |
16356 | ||
16357 | opt = input_line_pointer; | |
16358 | c = get_symbol_end (); | |
16359 | ||
16360 | if (*opt == 'O') | |
16361 | { | |
16362 | /* FIXME: What does this mean? */ | |
16363 | } | |
16364 | else if (strncmp (opt, "pic", 3) == 0) | |
16365 | { | |
16366 | int i; | |
16367 | ||
16368 | i = atoi (opt + 3); | |
16369 | if (i == 0) | |
16370 | mips_pic = NO_PIC; | |
16371 | else if (i == 2) | |
143d77c5 | 16372 | { |
8b828383 | 16373 | mips_pic = SVR4_PIC; |
143d77c5 EC |
16374 | mips_abicalls = TRUE; |
16375 | } | |
252b5132 RH |
16376 | else |
16377 | as_bad (_(".option pic%d not supported"), i); | |
16378 | ||
4d0d148d | 16379 | if (mips_pic == SVR4_PIC) |
252b5132 RH |
16380 | { |
16381 | if (g_switch_seen && g_switch_value != 0) | |
16382 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
16383 | g_switch_value = 0; | |
16384 | bfd_set_gp_size (stdoutput, 0); | |
16385 | } | |
16386 | } | |
16387 | else | |
16388 | as_warn (_("Unrecognized option \"%s\""), opt); | |
16389 | ||
16390 | *input_line_pointer = c; | |
16391 | demand_empty_rest_of_line (); | |
16392 | } | |
16393 | ||
16394 | /* This structure is used to hold a stack of .set values. */ | |
16395 | ||
e972090a NC |
16396 | struct mips_option_stack |
16397 | { | |
252b5132 RH |
16398 | struct mips_option_stack *next; |
16399 | struct mips_set_options options; | |
16400 | }; | |
16401 | ||
16402 | static struct mips_option_stack *mips_opts_stack; | |
16403 | ||
16404 | /* Handle the .set pseudo-op. */ | |
16405 | ||
16406 | static void | |
17a2f251 | 16407 | s_mipsset (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
16408 | { |
16409 | char *name = input_line_pointer, ch; | |
c6278170 | 16410 | const struct mips_ase *ase; |
252b5132 RH |
16411 | |
16412 | while (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
f9419b05 | 16413 | ++input_line_pointer; |
252b5132 RH |
16414 | ch = *input_line_pointer; |
16415 | *input_line_pointer = '\0'; | |
16416 | ||
16417 | if (strcmp (name, "reorder") == 0) | |
16418 | { | |
7d10b47d RS |
16419 | if (mips_opts.noreorder) |
16420 | end_noreorder (); | |
252b5132 RH |
16421 | } |
16422 | else if (strcmp (name, "noreorder") == 0) | |
16423 | { | |
7d10b47d RS |
16424 | if (!mips_opts.noreorder) |
16425 | start_noreorder (); | |
252b5132 | 16426 | } |
741fe287 MR |
16427 | else if (strncmp (name, "at=", 3) == 0) |
16428 | { | |
16429 | char *s = name + 3; | |
16430 | ||
16431 | if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, &mips_opts.at)) | |
16432 | as_bad (_("Unrecognized register name `%s'"), s); | |
16433 | } | |
252b5132 RH |
16434 | else if (strcmp (name, "at") == 0) |
16435 | { | |
741fe287 | 16436 | mips_opts.at = ATREG; |
252b5132 RH |
16437 | } |
16438 | else if (strcmp (name, "noat") == 0) | |
16439 | { | |
741fe287 | 16440 | mips_opts.at = ZERO; |
252b5132 RH |
16441 | } |
16442 | else if (strcmp (name, "macro") == 0) | |
16443 | { | |
16444 | mips_opts.warn_about_macros = 0; | |
16445 | } | |
16446 | else if (strcmp (name, "nomacro") == 0) | |
16447 | { | |
16448 | if (mips_opts.noreorder == 0) | |
16449 | as_bad (_("`noreorder' must be set before `nomacro'")); | |
16450 | mips_opts.warn_about_macros = 1; | |
16451 | } | |
16452 | else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0) | |
16453 | { | |
16454 | mips_opts.nomove = 0; | |
16455 | } | |
16456 | else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0) | |
16457 | { | |
16458 | mips_opts.nomove = 1; | |
16459 | } | |
16460 | else if (strcmp (name, "bopt") == 0) | |
16461 | { | |
16462 | mips_opts.nobopt = 0; | |
16463 | } | |
16464 | else if (strcmp (name, "nobopt") == 0) | |
16465 | { | |
16466 | mips_opts.nobopt = 1; | |
16467 | } | |
ad3fea08 TS |
16468 | else if (strcmp (name, "gp=default") == 0) |
16469 | mips_opts.gp32 = file_mips_gp32; | |
16470 | else if (strcmp (name, "gp=32") == 0) | |
16471 | mips_opts.gp32 = 1; | |
16472 | else if (strcmp (name, "gp=64") == 0) | |
16473 | { | |
16474 | if (!ISA_HAS_64BIT_REGS (mips_opts.isa)) | |
20203fb9 | 16475 | as_warn (_("%s isa does not support 64-bit registers"), |
ad3fea08 TS |
16476 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
16477 | mips_opts.gp32 = 0; | |
16478 | } | |
16479 | else if (strcmp (name, "fp=default") == 0) | |
16480 | mips_opts.fp32 = file_mips_fp32; | |
16481 | else if (strcmp (name, "fp=32") == 0) | |
16482 | mips_opts.fp32 = 1; | |
16483 | else if (strcmp (name, "fp=64") == 0) | |
16484 | { | |
16485 | if (!ISA_HAS_64BIT_FPRS (mips_opts.isa)) | |
20203fb9 | 16486 | as_warn (_("%s isa does not support 64-bit floating point registers"), |
ad3fea08 TS |
16487 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
16488 | mips_opts.fp32 = 0; | |
16489 | } | |
037b32b9 AN |
16490 | else if (strcmp (name, "softfloat") == 0) |
16491 | mips_opts.soft_float = 1; | |
16492 | else if (strcmp (name, "hardfloat") == 0) | |
16493 | mips_opts.soft_float = 0; | |
16494 | else if (strcmp (name, "singlefloat") == 0) | |
16495 | mips_opts.single_float = 1; | |
16496 | else if (strcmp (name, "doublefloat") == 0) | |
16497 | mips_opts.single_float = 0; | |
252b5132 RH |
16498 | else if (strcmp (name, "mips16") == 0 |
16499 | || strcmp (name, "MIPS-16") == 0) | |
df58fc94 RS |
16500 | { |
16501 | if (mips_opts.micromips == 1) | |
16502 | as_fatal (_("`mips16' cannot be used with `micromips'")); | |
16503 | mips_opts.mips16 = 1; | |
16504 | } | |
252b5132 RH |
16505 | else if (strcmp (name, "nomips16") == 0 |
16506 | || strcmp (name, "noMIPS-16") == 0) | |
16507 | mips_opts.mips16 = 0; | |
df58fc94 RS |
16508 | else if (strcmp (name, "micromips") == 0) |
16509 | { | |
16510 | if (mips_opts.mips16 == 1) | |
16511 | as_fatal (_("`micromips' cannot be used with `mips16'")); | |
16512 | mips_opts.micromips = 1; | |
16513 | } | |
16514 | else if (strcmp (name, "nomicromips") == 0) | |
16515 | mips_opts.micromips = 0; | |
c6278170 RS |
16516 | else if (name[0] == 'n' |
16517 | && name[1] == 'o' | |
16518 | && (ase = mips_lookup_ase (name + 2))) | |
16519 | mips_set_ase (ase, FALSE); | |
16520 | else if ((ase = mips_lookup_ase (name))) | |
16521 | mips_set_ase (ase, TRUE); | |
1a2c1fad | 16522 | else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0) |
252b5132 | 16523 | { |
af7ee8bf | 16524 | int reset = 0; |
252b5132 | 16525 | |
1a2c1fad CD |
16526 | /* Permit the user to change the ISA and architecture on the fly. |
16527 | Needless to say, misuse can cause serious problems. */ | |
81a21e38 | 16528 | if (strcmp (name, "mips0") == 0 || strcmp (name, "arch=default") == 0) |
af7ee8bf CD |
16529 | { |
16530 | reset = 1; | |
16531 | mips_opts.isa = file_mips_isa; | |
1a2c1fad | 16532 | mips_opts.arch = file_mips_arch; |
1a2c1fad CD |
16533 | } |
16534 | else if (strncmp (name, "arch=", 5) == 0) | |
16535 | { | |
16536 | const struct mips_cpu_info *p; | |
16537 | ||
16538 | p = mips_parse_cpu("internal use", name + 5); | |
16539 | if (!p) | |
16540 | as_bad (_("unknown architecture %s"), name + 5); | |
16541 | else | |
16542 | { | |
16543 | mips_opts.arch = p->cpu; | |
16544 | mips_opts.isa = p->isa; | |
16545 | } | |
16546 | } | |
81a21e38 TS |
16547 | else if (strncmp (name, "mips", 4) == 0) |
16548 | { | |
16549 | const struct mips_cpu_info *p; | |
16550 | ||
16551 | p = mips_parse_cpu("internal use", name); | |
16552 | if (!p) | |
16553 | as_bad (_("unknown ISA level %s"), name + 4); | |
16554 | else | |
16555 | { | |
16556 | mips_opts.arch = p->cpu; | |
16557 | mips_opts.isa = p->isa; | |
16558 | } | |
16559 | } | |
af7ee8bf | 16560 | else |
81a21e38 | 16561 | as_bad (_("unknown ISA or architecture %s"), name); |
af7ee8bf CD |
16562 | |
16563 | switch (mips_opts.isa) | |
98d3f06f KH |
16564 | { |
16565 | case 0: | |
98d3f06f | 16566 | break; |
af7ee8bf CD |
16567 | case ISA_MIPS1: |
16568 | case ISA_MIPS2: | |
16569 | case ISA_MIPS32: | |
16570 | case ISA_MIPS32R2: | |
98d3f06f KH |
16571 | mips_opts.gp32 = 1; |
16572 | mips_opts.fp32 = 1; | |
16573 | break; | |
af7ee8bf CD |
16574 | case ISA_MIPS3: |
16575 | case ISA_MIPS4: | |
16576 | case ISA_MIPS5: | |
16577 | case ISA_MIPS64: | |
5f74bc13 | 16578 | case ISA_MIPS64R2: |
98d3f06f | 16579 | mips_opts.gp32 = 0; |
e407c74b NC |
16580 | if (mips_opts.arch == CPU_R5900) |
16581 | { | |
16582 | mips_opts.fp32 = 1; | |
16583 | } | |
16584 | else | |
16585 | { | |
98d3f06f | 16586 | mips_opts.fp32 = 0; |
e407c74b | 16587 | } |
98d3f06f KH |
16588 | break; |
16589 | default: | |
16590 | as_bad (_("unknown ISA level %s"), name + 4); | |
16591 | break; | |
16592 | } | |
af7ee8bf | 16593 | if (reset) |
98d3f06f | 16594 | { |
af7ee8bf CD |
16595 | mips_opts.gp32 = file_mips_gp32; |
16596 | mips_opts.fp32 = file_mips_fp32; | |
98d3f06f | 16597 | } |
252b5132 RH |
16598 | } |
16599 | else if (strcmp (name, "autoextend") == 0) | |
16600 | mips_opts.noautoextend = 0; | |
16601 | else if (strcmp (name, "noautoextend") == 0) | |
16602 | mips_opts.noautoextend = 1; | |
16603 | else if (strcmp (name, "push") == 0) | |
16604 | { | |
16605 | struct mips_option_stack *s; | |
16606 | ||
16607 | s = (struct mips_option_stack *) xmalloc (sizeof *s); | |
16608 | s->next = mips_opts_stack; | |
16609 | s->options = mips_opts; | |
16610 | mips_opts_stack = s; | |
16611 | } | |
16612 | else if (strcmp (name, "pop") == 0) | |
16613 | { | |
16614 | struct mips_option_stack *s; | |
16615 | ||
16616 | s = mips_opts_stack; | |
16617 | if (s == NULL) | |
16618 | as_bad (_(".set pop with no .set push")); | |
16619 | else | |
16620 | { | |
16621 | /* If we're changing the reorder mode we need to handle | |
16622 | delay slots correctly. */ | |
16623 | if (s->options.noreorder && ! mips_opts.noreorder) | |
7d10b47d | 16624 | start_noreorder (); |
252b5132 | 16625 | else if (! s->options.noreorder && mips_opts.noreorder) |
7d10b47d | 16626 | end_noreorder (); |
252b5132 RH |
16627 | |
16628 | mips_opts = s->options; | |
16629 | mips_opts_stack = s->next; | |
16630 | free (s); | |
16631 | } | |
16632 | } | |
aed1a261 RS |
16633 | else if (strcmp (name, "sym32") == 0) |
16634 | mips_opts.sym32 = TRUE; | |
16635 | else if (strcmp (name, "nosym32") == 0) | |
16636 | mips_opts.sym32 = FALSE; | |
e6559e01 JM |
16637 | else if (strchr (name, ',')) |
16638 | { | |
16639 | /* Generic ".set" directive; use the generic handler. */ | |
16640 | *input_line_pointer = ch; | |
16641 | input_line_pointer = name; | |
16642 | s_set (0); | |
16643 | return; | |
16644 | } | |
252b5132 RH |
16645 | else |
16646 | { | |
16647 | as_warn (_("Tried to set unrecognized symbol: %s\n"), name); | |
16648 | } | |
c6278170 | 16649 | mips_check_isa_supports_ases (); |
252b5132 RH |
16650 | *input_line_pointer = ch; |
16651 | demand_empty_rest_of_line (); | |
16652 | } | |
16653 | ||
16654 | /* Handle the .abicalls pseudo-op. I believe this is equivalent to | |
16655 | .option pic2. It means to generate SVR4 PIC calls. */ | |
16656 | ||
16657 | static void | |
17a2f251 | 16658 | s_abicalls (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
16659 | { |
16660 | mips_pic = SVR4_PIC; | |
143d77c5 | 16661 | mips_abicalls = TRUE; |
4d0d148d TS |
16662 | |
16663 | if (g_switch_seen && g_switch_value != 0) | |
16664 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
16665 | g_switch_value = 0; | |
16666 | ||
252b5132 RH |
16667 | bfd_set_gp_size (stdoutput, 0); |
16668 | demand_empty_rest_of_line (); | |
16669 | } | |
16670 | ||
16671 | /* Handle the .cpload pseudo-op. This is used when generating SVR4 | |
16672 | PIC code. It sets the $gp register for the function based on the | |
16673 | function address, which is in the register named in the argument. | |
16674 | This uses a relocation against _gp_disp, which is handled specially | |
16675 | by the linker. The result is: | |
16676 | lui $gp,%hi(_gp_disp) | |
16677 | addiu $gp,$gp,%lo(_gp_disp) | |
16678 | addu $gp,$gp,.cpload argument | |
aa6975fb ILT |
16679 | The .cpload argument is normally $25 == $t9. |
16680 | ||
16681 | The -mno-shared option changes this to: | |
bbe506e8 TS |
16682 | lui $gp,%hi(__gnu_local_gp) |
16683 | addiu $gp,$gp,%lo(__gnu_local_gp) | |
aa6975fb ILT |
16684 | and the argument is ignored. This saves an instruction, but the |
16685 | resulting code is not position independent; it uses an absolute | |
bbe506e8 TS |
16686 | address for __gnu_local_gp. Thus code assembled with -mno-shared |
16687 | can go into an ordinary executable, but not into a shared library. */ | |
252b5132 RH |
16688 | |
16689 | static void | |
17a2f251 | 16690 | s_cpload (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
16691 | { |
16692 | expressionS ex; | |
aa6975fb ILT |
16693 | int reg; |
16694 | int in_shared; | |
252b5132 | 16695 | |
6478892d TS |
16696 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
16697 | .cpload is ignored. */ | |
16698 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) | |
252b5132 RH |
16699 | { |
16700 | s_ignore (0); | |
16701 | return; | |
16702 | } | |
16703 | ||
a276b80c MR |
16704 | if (mips_opts.mips16) |
16705 | { | |
16706 | as_bad (_("%s not supported in MIPS16 mode"), ".cpload"); | |
16707 | ignore_rest_of_line (); | |
16708 | return; | |
16709 | } | |
16710 | ||
d3ecfc59 | 16711 | /* .cpload should be in a .set noreorder section. */ |
252b5132 RH |
16712 | if (mips_opts.noreorder == 0) |
16713 | as_warn (_(".cpload not in noreorder section")); | |
16714 | ||
aa6975fb ILT |
16715 | reg = tc_get_register (0); |
16716 | ||
16717 | /* If we need to produce a 64-bit address, we are better off using | |
16718 | the default instruction sequence. */ | |
aed1a261 | 16719 | in_shared = mips_in_shared || HAVE_64BIT_SYMBOLS; |
aa6975fb | 16720 | |
252b5132 | 16721 | ex.X_op = O_symbol; |
bbe506e8 TS |
16722 | ex.X_add_symbol = symbol_find_or_make (in_shared ? "_gp_disp" : |
16723 | "__gnu_local_gp"); | |
252b5132 RH |
16724 | ex.X_op_symbol = NULL; |
16725 | ex.X_add_number = 0; | |
16726 | ||
16727 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ | |
49309057 | 16728 | symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; |
252b5132 | 16729 | |
8a75745d MR |
16730 | mips_mark_labels (); |
16731 | mips_assembling_insn = TRUE; | |
16732 | ||
584892a6 | 16733 | macro_start (); |
67c0d1eb RS |
16734 | macro_build_lui (&ex, mips_gp_register); |
16735 | macro_build (&ex, "addiu", "t,r,j", mips_gp_register, | |
17a2f251 | 16736 | mips_gp_register, BFD_RELOC_LO16); |
aa6975fb ILT |
16737 | if (in_shared) |
16738 | macro_build (NULL, "addu", "d,v,t", mips_gp_register, | |
16739 | mips_gp_register, reg); | |
584892a6 | 16740 | macro_end (); |
252b5132 | 16741 | |
8a75745d | 16742 | mips_assembling_insn = FALSE; |
252b5132 RH |
16743 | demand_empty_rest_of_line (); |
16744 | } | |
16745 | ||
6478892d TS |
16746 | /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is: |
16747 | .cpsetup $reg1, offset|$reg2, label | |
16748 | ||
16749 | If offset is given, this results in: | |
16750 | sd $gp, offset($sp) | |
956cd1d6 | 16751 | lui $gp, %hi(%neg(%gp_rel(label))) |
698b7d9d TS |
16752 | addiu $gp, $gp, %lo(%neg(%gp_rel(label))) |
16753 | daddu $gp, $gp, $reg1 | |
6478892d TS |
16754 | |
16755 | If $reg2 is given, this results in: | |
16756 | daddu $reg2, $gp, $0 | |
956cd1d6 | 16757 | lui $gp, %hi(%neg(%gp_rel(label))) |
698b7d9d TS |
16758 | addiu $gp, $gp, %lo(%neg(%gp_rel(label))) |
16759 | daddu $gp, $gp, $reg1 | |
aa6975fb ILT |
16760 | $reg1 is normally $25 == $t9. |
16761 | ||
16762 | The -mno-shared option replaces the last three instructions with | |
16763 | lui $gp,%hi(_gp) | |
54f4ddb3 | 16764 | addiu $gp,$gp,%lo(_gp) */ |
aa6975fb | 16765 | |
6478892d | 16766 | static void |
17a2f251 | 16767 | s_cpsetup (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
16768 | { |
16769 | expressionS ex_off; | |
16770 | expressionS ex_sym; | |
16771 | int reg1; | |
6478892d | 16772 | |
8586fc66 | 16773 | /* If we are not generating SVR4 PIC code, .cpsetup is ignored. |
6478892d TS |
16774 | We also need NewABI support. */ |
16775 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
16776 | { | |
16777 | s_ignore (0); | |
16778 | return; | |
16779 | } | |
16780 | ||
a276b80c MR |
16781 | if (mips_opts.mips16) |
16782 | { | |
16783 | as_bad (_("%s not supported in MIPS16 mode"), ".cpsetup"); | |
16784 | ignore_rest_of_line (); | |
16785 | return; | |
16786 | } | |
16787 | ||
6478892d TS |
16788 | reg1 = tc_get_register (0); |
16789 | SKIP_WHITESPACE (); | |
16790 | if (*input_line_pointer != ',') | |
16791 | { | |
16792 | as_bad (_("missing argument separator ',' for .cpsetup")); | |
16793 | return; | |
16794 | } | |
16795 | else | |
80245285 | 16796 | ++input_line_pointer; |
6478892d TS |
16797 | SKIP_WHITESPACE (); |
16798 | if (*input_line_pointer == '$') | |
80245285 TS |
16799 | { |
16800 | mips_cpreturn_register = tc_get_register (0); | |
16801 | mips_cpreturn_offset = -1; | |
16802 | } | |
6478892d | 16803 | else |
80245285 TS |
16804 | { |
16805 | mips_cpreturn_offset = get_absolute_expression (); | |
16806 | mips_cpreturn_register = -1; | |
16807 | } | |
6478892d TS |
16808 | SKIP_WHITESPACE (); |
16809 | if (*input_line_pointer != ',') | |
16810 | { | |
16811 | as_bad (_("missing argument separator ',' for .cpsetup")); | |
16812 | return; | |
16813 | } | |
16814 | else | |
f9419b05 | 16815 | ++input_line_pointer; |
6478892d | 16816 | SKIP_WHITESPACE (); |
f21f8242 | 16817 | expression (&ex_sym); |
6478892d | 16818 | |
8a75745d MR |
16819 | mips_mark_labels (); |
16820 | mips_assembling_insn = TRUE; | |
16821 | ||
584892a6 | 16822 | macro_start (); |
6478892d TS |
16823 | if (mips_cpreturn_register == -1) |
16824 | { | |
16825 | ex_off.X_op = O_constant; | |
16826 | ex_off.X_add_symbol = NULL; | |
16827 | ex_off.X_op_symbol = NULL; | |
16828 | ex_off.X_add_number = mips_cpreturn_offset; | |
16829 | ||
67c0d1eb | 16830 | macro_build (&ex_off, "sd", "t,o(b)", mips_gp_register, |
17a2f251 | 16831 | BFD_RELOC_LO16, SP); |
6478892d TS |
16832 | } |
16833 | else | |
67c0d1eb | 16834 | macro_build (NULL, "daddu", "d,v,t", mips_cpreturn_register, |
17a2f251 | 16835 | mips_gp_register, 0); |
6478892d | 16836 | |
aed1a261 | 16837 | if (mips_in_shared || HAVE_64BIT_SYMBOLS) |
aa6975fb | 16838 | { |
df58fc94 | 16839 | macro_build (&ex_sym, "lui", LUI_FMT, mips_gp_register, |
aa6975fb ILT |
16840 | -1, BFD_RELOC_GPREL16, BFD_RELOC_MIPS_SUB, |
16841 | BFD_RELOC_HI16_S); | |
16842 | ||
16843 | macro_build (&ex_sym, "addiu", "t,r,j", mips_gp_register, | |
16844 | mips_gp_register, -1, BFD_RELOC_GPREL16, | |
16845 | BFD_RELOC_MIPS_SUB, BFD_RELOC_LO16); | |
16846 | ||
16847 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register, | |
16848 | mips_gp_register, reg1); | |
16849 | } | |
16850 | else | |
16851 | { | |
16852 | expressionS ex; | |
16853 | ||
16854 | ex.X_op = O_symbol; | |
4184909a | 16855 | ex.X_add_symbol = symbol_find_or_make ("__gnu_local_gp"); |
aa6975fb ILT |
16856 | ex.X_op_symbol = NULL; |
16857 | ex.X_add_number = 0; | |
6e1304d8 | 16858 | |
aa6975fb ILT |
16859 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ |
16860 | symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; | |
16861 | ||
16862 | macro_build_lui (&ex, mips_gp_register); | |
16863 | macro_build (&ex, "addiu", "t,r,j", mips_gp_register, | |
16864 | mips_gp_register, BFD_RELOC_LO16); | |
16865 | } | |
f21f8242 | 16866 | |
584892a6 | 16867 | macro_end (); |
6478892d | 16868 | |
8a75745d | 16869 | mips_assembling_insn = FALSE; |
6478892d TS |
16870 | demand_empty_rest_of_line (); |
16871 | } | |
16872 | ||
16873 | static void | |
17a2f251 | 16874 | s_cplocal (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
16875 | { |
16876 | /* If we are not generating SVR4 PIC code, or if this is not NewABI code, | |
54f4ddb3 | 16877 | .cplocal is ignored. */ |
6478892d TS |
16878 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) |
16879 | { | |
16880 | s_ignore (0); | |
16881 | return; | |
16882 | } | |
16883 | ||
a276b80c MR |
16884 | if (mips_opts.mips16) |
16885 | { | |
16886 | as_bad (_("%s not supported in MIPS16 mode"), ".cplocal"); | |
16887 | ignore_rest_of_line (); | |
16888 | return; | |
16889 | } | |
16890 | ||
6478892d | 16891 | mips_gp_register = tc_get_register (0); |
85b51719 | 16892 | demand_empty_rest_of_line (); |
6478892d TS |
16893 | } |
16894 | ||
252b5132 RH |
16895 | /* Handle the .cprestore pseudo-op. This stores $gp into a given |
16896 | offset from $sp. The offset is remembered, and after making a PIC | |
16897 | call $gp is restored from that location. */ | |
16898 | ||
16899 | static void | |
17a2f251 | 16900 | s_cprestore (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
16901 | { |
16902 | expressionS ex; | |
252b5132 | 16903 | |
6478892d | 16904 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
c9914766 | 16905 | .cprestore is ignored. */ |
6478892d | 16906 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) |
252b5132 RH |
16907 | { |
16908 | s_ignore (0); | |
16909 | return; | |
16910 | } | |
16911 | ||
a276b80c MR |
16912 | if (mips_opts.mips16) |
16913 | { | |
16914 | as_bad (_("%s not supported in MIPS16 mode"), ".cprestore"); | |
16915 | ignore_rest_of_line (); | |
16916 | return; | |
16917 | } | |
16918 | ||
252b5132 | 16919 | mips_cprestore_offset = get_absolute_expression (); |
7a621144 | 16920 | mips_cprestore_valid = 1; |
252b5132 RH |
16921 | |
16922 | ex.X_op = O_constant; | |
16923 | ex.X_add_symbol = NULL; | |
16924 | ex.X_op_symbol = NULL; | |
16925 | ex.X_add_number = mips_cprestore_offset; | |
16926 | ||
8a75745d MR |
16927 | mips_mark_labels (); |
16928 | mips_assembling_insn = TRUE; | |
16929 | ||
584892a6 | 16930 | macro_start (); |
67c0d1eb RS |
16931 | macro_build_ldst_constoffset (&ex, ADDRESS_STORE_INSN, mips_gp_register, |
16932 | SP, HAVE_64BIT_ADDRESSES); | |
584892a6 | 16933 | macro_end (); |
252b5132 | 16934 | |
8a75745d | 16935 | mips_assembling_insn = FALSE; |
252b5132 RH |
16936 | demand_empty_rest_of_line (); |
16937 | } | |
16938 | ||
6478892d | 16939 | /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset |
67c1ffbe | 16940 | was given in the preceding .cpsetup, it results in: |
6478892d | 16941 | ld $gp, offset($sp) |
76b3015f | 16942 | |
6478892d | 16943 | If a register $reg2 was given there, it results in: |
54f4ddb3 TS |
16944 | daddu $gp, $reg2, $0 */ |
16945 | ||
6478892d | 16946 | static void |
17a2f251 | 16947 | s_cpreturn (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
16948 | { |
16949 | expressionS ex; | |
6478892d TS |
16950 | |
16951 | /* If we are not generating SVR4 PIC code, .cpreturn is ignored. | |
16952 | We also need NewABI support. */ | |
16953 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
16954 | { | |
16955 | s_ignore (0); | |
16956 | return; | |
16957 | } | |
16958 | ||
a276b80c MR |
16959 | if (mips_opts.mips16) |
16960 | { | |
16961 | as_bad (_("%s not supported in MIPS16 mode"), ".cpreturn"); | |
16962 | ignore_rest_of_line (); | |
16963 | return; | |
16964 | } | |
16965 | ||
8a75745d MR |
16966 | mips_mark_labels (); |
16967 | mips_assembling_insn = TRUE; | |
16968 | ||
584892a6 | 16969 | macro_start (); |
6478892d TS |
16970 | if (mips_cpreturn_register == -1) |
16971 | { | |
16972 | ex.X_op = O_constant; | |
16973 | ex.X_add_symbol = NULL; | |
16974 | ex.X_op_symbol = NULL; | |
16975 | ex.X_add_number = mips_cpreturn_offset; | |
16976 | ||
67c0d1eb | 16977 | macro_build (&ex, "ld", "t,o(b)", mips_gp_register, BFD_RELOC_LO16, SP); |
6478892d TS |
16978 | } |
16979 | else | |
67c0d1eb | 16980 | macro_build (NULL, "daddu", "d,v,t", mips_gp_register, |
17a2f251 | 16981 | mips_cpreturn_register, 0); |
584892a6 | 16982 | macro_end (); |
6478892d | 16983 | |
8a75745d | 16984 | mips_assembling_insn = FALSE; |
6478892d TS |
16985 | demand_empty_rest_of_line (); |
16986 | } | |
16987 | ||
d0f13682 CLT |
16988 | /* Handle a .dtprelword, .dtpreldword, .tprelword, or .tpreldword |
16989 | pseudo-op; DIRSTR says which. The pseudo-op generates a BYTES-size | |
16990 | DTP- or TP-relative relocation of type RTYPE, for use in either DWARF | |
16991 | debug information or MIPS16 TLS. */ | |
741d6ea8 JM |
16992 | |
16993 | static void | |
d0f13682 CLT |
16994 | s_tls_rel_directive (const size_t bytes, const char *dirstr, |
16995 | bfd_reloc_code_real_type rtype) | |
741d6ea8 JM |
16996 | { |
16997 | expressionS ex; | |
16998 | char *p; | |
16999 | ||
17000 | expression (&ex); | |
17001 | ||
17002 | if (ex.X_op != O_symbol) | |
17003 | { | |
d0f13682 | 17004 | as_bad (_("Unsupported use of %s"), dirstr); |
741d6ea8 JM |
17005 | ignore_rest_of_line (); |
17006 | } | |
17007 | ||
17008 | p = frag_more (bytes); | |
17009 | md_number_to_chars (p, 0, bytes); | |
d0f13682 | 17010 | fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, FALSE, rtype); |
741d6ea8 | 17011 | demand_empty_rest_of_line (); |
de64cffd | 17012 | mips_clear_insn_labels (); |
741d6ea8 JM |
17013 | } |
17014 | ||
17015 | /* Handle .dtprelword. */ | |
17016 | ||
17017 | static void | |
17018 | s_dtprelword (int ignore ATTRIBUTE_UNUSED) | |
17019 | { | |
d0f13682 | 17020 | s_tls_rel_directive (4, ".dtprelword", BFD_RELOC_MIPS_TLS_DTPREL32); |
741d6ea8 JM |
17021 | } |
17022 | ||
17023 | /* Handle .dtpreldword. */ | |
17024 | ||
17025 | static void | |
17026 | s_dtpreldword (int ignore ATTRIBUTE_UNUSED) | |
17027 | { | |
d0f13682 CLT |
17028 | s_tls_rel_directive (8, ".dtpreldword", BFD_RELOC_MIPS_TLS_DTPREL64); |
17029 | } | |
17030 | ||
17031 | /* Handle .tprelword. */ | |
17032 | ||
17033 | static void | |
17034 | s_tprelword (int ignore ATTRIBUTE_UNUSED) | |
17035 | { | |
17036 | s_tls_rel_directive (4, ".tprelword", BFD_RELOC_MIPS_TLS_TPREL32); | |
17037 | } | |
17038 | ||
17039 | /* Handle .tpreldword. */ | |
17040 | ||
17041 | static void | |
17042 | s_tpreldword (int ignore ATTRIBUTE_UNUSED) | |
17043 | { | |
17044 | s_tls_rel_directive (8, ".tpreldword", BFD_RELOC_MIPS_TLS_TPREL64); | |
741d6ea8 JM |
17045 | } |
17046 | ||
6478892d TS |
17047 | /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC |
17048 | code. It sets the offset to use in gp_rel relocations. */ | |
17049 | ||
17050 | static void | |
17a2f251 | 17051 | s_gpvalue (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
17052 | { |
17053 | /* If we are not generating SVR4 PIC code, .gpvalue is ignored. | |
17054 | We also need NewABI support. */ | |
17055 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
17056 | { | |
17057 | s_ignore (0); | |
17058 | return; | |
17059 | } | |
17060 | ||
def2e0dd | 17061 | mips_gprel_offset = get_absolute_expression (); |
6478892d TS |
17062 | |
17063 | demand_empty_rest_of_line (); | |
17064 | } | |
17065 | ||
252b5132 RH |
17066 | /* Handle the .gpword pseudo-op. This is used when generating PIC |
17067 | code. It generates a 32 bit GP relative reloc. */ | |
17068 | ||
17069 | static void | |
17a2f251 | 17070 | s_gpword (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 17071 | { |
a8dbcb85 TS |
17072 | segment_info_type *si; |
17073 | struct insn_label_list *l; | |
252b5132 RH |
17074 | expressionS ex; |
17075 | char *p; | |
17076 | ||
17077 | /* When not generating PIC code, this is treated as .word. */ | |
17078 | if (mips_pic != SVR4_PIC) | |
17079 | { | |
17080 | s_cons (2); | |
17081 | return; | |
17082 | } | |
17083 | ||
a8dbcb85 TS |
17084 | si = seg_info (now_seg); |
17085 | l = si->label_list; | |
7d10b47d | 17086 | mips_emit_delays (); |
252b5132 | 17087 | if (auto_align) |
462427c4 | 17088 | mips_align (2, 0, l); |
252b5132 RH |
17089 | |
17090 | expression (&ex); | |
a1facbec | 17091 | mips_clear_insn_labels (); |
252b5132 RH |
17092 | |
17093 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
17094 | { | |
17095 | as_bad (_("Unsupported use of .gpword")); | |
17096 | ignore_rest_of_line (); | |
17097 | } | |
17098 | ||
17099 | p = frag_more (4); | |
17a2f251 | 17100 | md_number_to_chars (p, 0, 4); |
b34976b6 | 17101 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, |
cdf6fd85 | 17102 | BFD_RELOC_GPREL32); |
252b5132 RH |
17103 | |
17104 | demand_empty_rest_of_line (); | |
17105 | } | |
17106 | ||
10181a0d | 17107 | static void |
17a2f251 | 17108 | s_gpdword (int ignore ATTRIBUTE_UNUSED) |
10181a0d | 17109 | { |
a8dbcb85 TS |
17110 | segment_info_type *si; |
17111 | struct insn_label_list *l; | |
10181a0d AO |
17112 | expressionS ex; |
17113 | char *p; | |
17114 | ||
17115 | /* When not generating PIC code, this is treated as .dword. */ | |
17116 | if (mips_pic != SVR4_PIC) | |
17117 | { | |
17118 | s_cons (3); | |
17119 | return; | |
17120 | } | |
17121 | ||
a8dbcb85 TS |
17122 | si = seg_info (now_seg); |
17123 | l = si->label_list; | |
7d10b47d | 17124 | mips_emit_delays (); |
10181a0d | 17125 | if (auto_align) |
462427c4 | 17126 | mips_align (3, 0, l); |
10181a0d AO |
17127 | |
17128 | expression (&ex); | |
a1facbec | 17129 | mips_clear_insn_labels (); |
10181a0d AO |
17130 | |
17131 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
17132 | { | |
17133 | as_bad (_("Unsupported use of .gpdword")); | |
17134 | ignore_rest_of_line (); | |
17135 | } | |
17136 | ||
17137 | p = frag_more (8); | |
17a2f251 | 17138 | md_number_to_chars (p, 0, 8); |
a105a300 | 17139 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, |
6e1304d8 | 17140 | BFD_RELOC_GPREL32)->fx_tcbit = 1; |
10181a0d AO |
17141 | |
17142 | /* GPREL32 composed with 64 gives a 64-bit GP offset. */ | |
6e1304d8 RS |
17143 | fix_new (frag_now, p - frag_now->fr_literal, 8, NULL, 0, |
17144 | FALSE, BFD_RELOC_64)->fx_tcbit = 1; | |
10181a0d AO |
17145 | |
17146 | demand_empty_rest_of_line (); | |
17147 | } | |
17148 | ||
a3f278e2 CM |
17149 | /* Handle the .ehword pseudo-op. This is used when generating unwinding |
17150 | tables. It generates a R_MIPS_EH reloc. */ | |
17151 | ||
17152 | static void | |
17153 | s_ehword (int ignore ATTRIBUTE_UNUSED) | |
17154 | { | |
17155 | expressionS ex; | |
17156 | char *p; | |
17157 | ||
17158 | mips_emit_delays (); | |
17159 | ||
17160 | expression (&ex); | |
17161 | mips_clear_insn_labels (); | |
17162 | ||
17163 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
17164 | { | |
17165 | as_bad (_("Unsupported use of .ehword")); | |
17166 | ignore_rest_of_line (); | |
17167 | } | |
17168 | ||
17169 | p = frag_more (4); | |
17170 | md_number_to_chars (p, 0, 4); | |
17171 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, | |
17172 | BFD_RELOC_MIPS_EH); | |
17173 | ||
17174 | demand_empty_rest_of_line (); | |
17175 | } | |
17176 | ||
252b5132 RH |
17177 | /* Handle the .cpadd pseudo-op. This is used when dealing with switch |
17178 | tables in SVR4 PIC code. */ | |
17179 | ||
17180 | static void | |
17a2f251 | 17181 | s_cpadd (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 17182 | { |
252b5132 RH |
17183 | int reg; |
17184 | ||
10181a0d AO |
17185 | /* This is ignored when not generating SVR4 PIC code. */ |
17186 | if (mips_pic != SVR4_PIC) | |
252b5132 RH |
17187 | { |
17188 | s_ignore (0); | |
17189 | return; | |
17190 | } | |
17191 | ||
8a75745d MR |
17192 | mips_mark_labels (); |
17193 | mips_assembling_insn = TRUE; | |
17194 | ||
252b5132 | 17195 | /* Add $gp to the register named as an argument. */ |
584892a6 | 17196 | macro_start (); |
252b5132 | 17197 | reg = tc_get_register (0); |
67c0d1eb | 17198 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register); |
584892a6 | 17199 | macro_end (); |
252b5132 | 17200 | |
8a75745d | 17201 | mips_assembling_insn = FALSE; |
bdaaa2e1 | 17202 | demand_empty_rest_of_line (); |
252b5132 RH |
17203 | } |
17204 | ||
17205 | /* Handle the .insn pseudo-op. This marks instruction labels in | |
df58fc94 | 17206 | mips16/micromips mode. This permits the linker to handle them specially, |
252b5132 RH |
17207 | such as generating jalx instructions when needed. We also make |
17208 | them odd for the duration of the assembly, in order to generate the | |
17209 | right sort of code. We will make them even in the adjust_symtab | |
17210 | routine, while leaving them marked. This is convenient for the | |
17211 | debugger and the disassembler. The linker knows to make them odd | |
17212 | again. */ | |
17213 | ||
17214 | static void | |
17a2f251 | 17215 | s_insn (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 17216 | { |
df58fc94 | 17217 | mips_mark_labels (); |
252b5132 RH |
17218 | |
17219 | demand_empty_rest_of_line (); | |
17220 | } | |
17221 | ||
754e2bb9 RS |
17222 | /* Handle a .stab[snd] directive. Ideally these directives would be |
17223 | implemented in a transparent way, so that removing them would not | |
17224 | have any effect on the generated instructions. However, s_stab | |
17225 | internally changes the section, so in practice we need to decide | |
17226 | now whether the preceding label marks compressed code. We do not | |
17227 | support changing the compression mode of a label after a .stab* | |
17228 | directive, such as in: | |
17229 | ||
17230 | foo: | |
17231 | .stabs ... | |
17232 | .set mips16 | |
17233 | ||
17234 | so the current mode wins. */ | |
252b5132 RH |
17235 | |
17236 | static void | |
17a2f251 | 17237 | s_mips_stab (int type) |
252b5132 | 17238 | { |
754e2bb9 | 17239 | mips_mark_labels (); |
252b5132 RH |
17240 | s_stab (type); |
17241 | } | |
17242 | ||
54f4ddb3 | 17243 | /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */ |
252b5132 RH |
17244 | |
17245 | static void | |
17a2f251 | 17246 | s_mips_weakext (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
17247 | { |
17248 | char *name; | |
17249 | int c; | |
17250 | symbolS *symbolP; | |
17251 | expressionS exp; | |
17252 | ||
17253 | name = input_line_pointer; | |
17254 | c = get_symbol_end (); | |
17255 | symbolP = symbol_find_or_make (name); | |
17256 | S_SET_WEAK (symbolP); | |
17257 | *input_line_pointer = c; | |
17258 | ||
17259 | SKIP_WHITESPACE (); | |
17260 | ||
17261 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
17262 | { | |
17263 | if (S_IS_DEFINED (symbolP)) | |
17264 | { | |
20203fb9 | 17265 | as_bad (_("ignoring attempt to redefine symbol %s"), |
252b5132 RH |
17266 | S_GET_NAME (symbolP)); |
17267 | ignore_rest_of_line (); | |
17268 | return; | |
17269 | } | |
bdaaa2e1 | 17270 | |
252b5132 RH |
17271 | if (*input_line_pointer == ',') |
17272 | { | |
17273 | ++input_line_pointer; | |
17274 | SKIP_WHITESPACE (); | |
17275 | } | |
bdaaa2e1 | 17276 | |
252b5132 RH |
17277 | expression (&exp); |
17278 | if (exp.X_op != O_symbol) | |
17279 | { | |
20203fb9 | 17280 | as_bad (_("bad .weakext directive")); |
98d3f06f | 17281 | ignore_rest_of_line (); |
252b5132 RH |
17282 | return; |
17283 | } | |
49309057 | 17284 | symbol_set_value_expression (symbolP, &exp); |
252b5132 RH |
17285 | } |
17286 | ||
17287 | demand_empty_rest_of_line (); | |
17288 | } | |
17289 | ||
17290 | /* Parse a register string into a number. Called from the ECOFF code | |
17291 | to parse .frame. The argument is non-zero if this is the frame | |
17292 | register, so that we can record it in mips_frame_reg. */ | |
17293 | ||
17294 | int | |
17a2f251 | 17295 | tc_get_register (int frame) |
252b5132 | 17296 | { |
707bfff6 | 17297 | unsigned int reg; |
252b5132 RH |
17298 | |
17299 | SKIP_WHITESPACE (); | |
707bfff6 TS |
17300 | if (! reg_lookup (&input_line_pointer, RWARN | RTYPE_NUM | RTYPE_GP, ®)) |
17301 | reg = 0; | |
252b5132 | 17302 | if (frame) |
7a621144 DJ |
17303 | { |
17304 | mips_frame_reg = reg != 0 ? reg : SP; | |
17305 | mips_frame_reg_valid = 1; | |
17306 | mips_cprestore_valid = 0; | |
17307 | } | |
252b5132 RH |
17308 | return reg; |
17309 | } | |
17310 | ||
17311 | valueT | |
17a2f251 | 17312 | md_section_align (asection *seg, valueT addr) |
252b5132 RH |
17313 | { |
17314 | int align = bfd_get_section_alignment (stdoutput, seg); | |
17315 | ||
f3ded42a RS |
17316 | /* We don't need to align ELF sections to the full alignment. |
17317 | However, Irix 5 may prefer that we align them at least to a 16 | |
17318 | byte boundary. We don't bother to align the sections if we | |
17319 | are targeted for an embedded system. */ | |
17320 | if (strncmp (TARGET_OS, "elf", 3) == 0) | |
17321 | return addr; | |
17322 | if (align > 4) | |
17323 | align = 4; | |
252b5132 RH |
17324 | |
17325 | return ((addr + (1 << align) - 1) & (-1 << align)); | |
17326 | } | |
17327 | ||
17328 | /* Utility routine, called from above as well. If called while the | |
17329 | input file is still being read, it's only an approximation. (For | |
17330 | example, a symbol may later become defined which appeared to be | |
17331 | undefined earlier.) */ | |
17332 | ||
17333 | static int | |
17a2f251 | 17334 | nopic_need_relax (symbolS *sym, int before_relaxing) |
252b5132 RH |
17335 | { |
17336 | if (sym == 0) | |
17337 | return 0; | |
17338 | ||
4d0d148d | 17339 | if (g_switch_value > 0) |
252b5132 RH |
17340 | { |
17341 | const char *symname; | |
17342 | int change; | |
17343 | ||
c9914766 | 17344 | /* Find out whether this symbol can be referenced off the $gp |
252b5132 RH |
17345 | register. It can be if it is smaller than the -G size or if |
17346 | it is in the .sdata or .sbss section. Certain symbols can | |
c9914766 | 17347 | not be referenced off the $gp, although it appears as though |
252b5132 RH |
17348 | they can. */ |
17349 | symname = S_GET_NAME (sym); | |
17350 | if (symname != (const char *) NULL | |
17351 | && (strcmp (symname, "eprol") == 0 | |
17352 | || strcmp (symname, "etext") == 0 | |
17353 | || strcmp (symname, "_gp") == 0 | |
17354 | || strcmp (symname, "edata") == 0 | |
17355 | || strcmp (symname, "_fbss") == 0 | |
17356 | || strcmp (symname, "_fdata") == 0 | |
17357 | || strcmp (symname, "_ftext") == 0 | |
17358 | || strcmp (symname, "end") == 0 | |
17359 | || strcmp (symname, "_gp_disp") == 0)) | |
17360 | change = 1; | |
17361 | else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym)) | |
17362 | && (0 | |
17363 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 ILT |
17364 | || (symbol_get_obj (sym)->ecoff_extern_size != 0 |
17365 | && (symbol_get_obj (sym)->ecoff_extern_size | |
17366 | <= g_switch_value)) | |
252b5132 RH |
17367 | #endif |
17368 | /* We must defer this decision until after the whole | |
17369 | file has been read, since there might be a .extern | |
17370 | after the first use of this symbol. */ | |
17371 | || (before_relaxing | |
17372 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 | 17373 | && symbol_get_obj (sym)->ecoff_extern_size == 0 |
252b5132 RH |
17374 | #endif |
17375 | && S_GET_VALUE (sym) == 0) | |
17376 | || (S_GET_VALUE (sym) != 0 | |
17377 | && S_GET_VALUE (sym) <= g_switch_value))) | |
17378 | change = 0; | |
17379 | else | |
17380 | { | |
17381 | const char *segname; | |
17382 | ||
17383 | segname = segment_name (S_GET_SEGMENT (sym)); | |
9c2799c2 | 17384 | gas_assert (strcmp (segname, ".lit8") != 0 |
252b5132 RH |
17385 | && strcmp (segname, ".lit4") != 0); |
17386 | change = (strcmp (segname, ".sdata") != 0 | |
fba2b7f9 GK |
17387 | && strcmp (segname, ".sbss") != 0 |
17388 | && strncmp (segname, ".sdata.", 7) != 0 | |
d4dc2f22 TS |
17389 | && strncmp (segname, ".sbss.", 6) != 0 |
17390 | && strncmp (segname, ".gnu.linkonce.sb.", 17) != 0 | |
fba2b7f9 | 17391 | && strncmp (segname, ".gnu.linkonce.s.", 16) != 0); |
252b5132 RH |
17392 | } |
17393 | return change; | |
17394 | } | |
17395 | else | |
c9914766 | 17396 | /* We are not optimizing for the $gp register. */ |
252b5132 RH |
17397 | return 1; |
17398 | } | |
17399 | ||
5919d012 RS |
17400 | |
17401 | /* Return true if the given symbol should be considered local for SVR4 PIC. */ | |
17402 | ||
17403 | static bfd_boolean | |
17a2f251 | 17404 | pic_need_relax (symbolS *sym, asection *segtype) |
5919d012 RS |
17405 | { |
17406 | asection *symsec; | |
5919d012 RS |
17407 | |
17408 | /* Handle the case of a symbol equated to another symbol. */ | |
17409 | while (symbol_equated_reloc_p (sym)) | |
17410 | { | |
17411 | symbolS *n; | |
17412 | ||
5f0fe04b | 17413 | /* It's possible to get a loop here in a badly written program. */ |
5919d012 RS |
17414 | n = symbol_get_value_expression (sym)->X_add_symbol; |
17415 | if (n == sym) | |
17416 | break; | |
17417 | sym = n; | |
17418 | } | |
17419 | ||
df1f3cda DD |
17420 | if (symbol_section_p (sym)) |
17421 | return TRUE; | |
17422 | ||
5919d012 RS |
17423 | symsec = S_GET_SEGMENT (sym); |
17424 | ||
5919d012 | 17425 | /* This must duplicate the test in adjust_reloc_syms. */ |
45dfa85a AM |
17426 | return (!bfd_is_und_section (symsec) |
17427 | && !bfd_is_abs_section (symsec) | |
5f0fe04b TS |
17428 | && !bfd_is_com_section (symsec) |
17429 | && !s_is_linkonce (sym, segtype) | |
5919d012 | 17430 | /* A global or weak symbol is treated as external. */ |
f3ded42a | 17431 | && (!S_IS_WEAK (sym) && !S_IS_EXTERNAL (sym))); |
5919d012 RS |
17432 | } |
17433 | ||
17434 | ||
252b5132 RH |
17435 | /* Given a mips16 variant frag FRAGP, return non-zero if it needs an |
17436 | extended opcode. SEC is the section the frag is in. */ | |
17437 | ||
17438 | static int | |
17a2f251 | 17439 | mips16_extended_frag (fragS *fragp, asection *sec, long stretch) |
252b5132 RH |
17440 | { |
17441 | int type; | |
3994f87e | 17442 | const struct mips16_immed_operand *op; |
252b5132 RH |
17443 | offsetT val; |
17444 | int mintiny, maxtiny; | |
17445 | segT symsec; | |
98aa84af | 17446 | fragS *sym_frag; |
252b5132 RH |
17447 | |
17448 | if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype)) | |
17449 | return 0; | |
17450 | if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype)) | |
17451 | return 1; | |
17452 | ||
17453 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
17454 | op = mips16_immed_operands; | |
17455 | while (op->type != type) | |
17456 | { | |
17457 | ++op; | |
9c2799c2 | 17458 | gas_assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); |
252b5132 RH |
17459 | } |
17460 | ||
17461 | if (op->unsp) | |
17462 | { | |
17463 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
17464 | { | |
17465 | mintiny = 1; | |
17466 | maxtiny = 1 << op->nbits; | |
17467 | } | |
17468 | else | |
17469 | { | |
17470 | mintiny = 0; | |
17471 | maxtiny = (1 << op->nbits) - 1; | |
17472 | } | |
17473 | } | |
17474 | else | |
17475 | { | |
17476 | mintiny = - (1 << (op->nbits - 1)); | |
17477 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
17478 | } | |
17479 | ||
98aa84af | 17480 | sym_frag = symbol_get_frag (fragp->fr_symbol); |
ac62c346 | 17481 | val = S_GET_VALUE (fragp->fr_symbol); |
98aa84af | 17482 | symsec = S_GET_SEGMENT (fragp->fr_symbol); |
252b5132 RH |
17483 | |
17484 | if (op->pcrel) | |
17485 | { | |
17486 | addressT addr; | |
17487 | ||
17488 | /* We won't have the section when we are called from | |
17489 | mips_relax_frag. However, we will always have been called | |
17490 | from md_estimate_size_before_relax first. If this is a | |
17491 | branch to a different section, we mark it as such. If SEC is | |
17492 | NULL, and the frag is not marked, then it must be a branch to | |
17493 | the same section. */ | |
17494 | if (sec == NULL) | |
17495 | { | |
17496 | if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype)) | |
17497 | return 1; | |
17498 | } | |
17499 | else | |
17500 | { | |
98aa84af | 17501 | /* Must have been called from md_estimate_size_before_relax. */ |
252b5132 RH |
17502 | if (symsec != sec) |
17503 | { | |
17504 | fragp->fr_subtype = | |
17505 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
17506 | ||
17507 | /* FIXME: We should support this, and let the linker | |
17508 | catch branches and loads that are out of range. */ | |
17509 | as_bad_where (fragp->fr_file, fragp->fr_line, | |
17510 | _("unsupported PC relative reference to different section")); | |
17511 | ||
17512 | return 1; | |
17513 | } | |
98aa84af AM |
17514 | if (fragp != sym_frag && sym_frag->fr_address == 0) |
17515 | /* Assume non-extended on the first relaxation pass. | |
17516 | The address we have calculated will be bogus if this is | |
17517 | a forward branch to another frag, as the forward frag | |
17518 | will have fr_address == 0. */ | |
17519 | return 0; | |
252b5132 RH |
17520 | } |
17521 | ||
17522 | /* In this case, we know for sure that the symbol fragment is in | |
98aa84af AM |
17523 | the same section. If the relax_marker of the symbol fragment |
17524 | differs from the relax_marker of this fragment, we have not | |
17525 | yet adjusted the symbol fragment fr_address. We want to add | |
252b5132 RH |
17526 | in STRETCH in order to get a better estimate of the address. |
17527 | This particularly matters because of the shift bits. */ | |
17528 | if (stretch != 0 | |
98aa84af | 17529 | && sym_frag->relax_marker != fragp->relax_marker) |
252b5132 RH |
17530 | { |
17531 | fragS *f; | |
17532 | ||
17533 | /* Adjust stretch for any alignment frag. Note that if have | |
17534 | been expanding the earlier code, the symbol may be | |
17535 | defined in what appears to be an earlier frag. FIXME: | |
17536 | This doesn't handle the fr_subtype field, which specifies | |
17537 | a maximum number of bytes to skip when doing an | |
17538 | alignment. */ | |
98aa84af | 17539 | for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next) |
252b5132 RH |
17540 | { |
17541 | if (f->fr_type == rs_align || f->fr_type == rs_align_code) | |
17542 | { | |
17543 | if (stretch < 0) | |
17544 | stretch = - ((- stretch) | |
17545 | & ~ ((1 << (int) f->fr_offset) - 1)); | |
17546 | else | |
17547 | stretch &= ~ ((1 << (int) f->fr_offset) - 1); | |
17548 | if (stretch == 0) | |
17549 | break; | |
17550 | } | |
17551 | } | |
17552 | if (f != NULL) | |
17553 | val += stretch; | |
17554 | } | |
17555 | ||
17556 | addr = fragp->fr_address + fragp->fr_fix; | |
17557 | ||
17558 | /* The base address rules are complicated. The base address of | |
17559 | a branch is the following instruction. The base address of a | |
17560 | PC relative load or add is the instruction itself, but if it | |
17561 | is in a delay slot (in which case it can not be extended) use | |
17562 | the address of the instruction whose delay slot it is in. */ | |
17563 | if (type == 'p' || type == 'q') | |
17564 | { | |
17565 | addr += 2; | |
17566 | ||
17567 | /* If we are currently assuming that this frag should be | |
17568 | extended, then, the current address is two bytes | |
bdaaa2e1 | 17569 | higher. */ |
252b5132 RH |
17570 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) |
17571 | addr += 2; | |
17572 | ||
17573 | /* Ignore the low bit in the target, since it will be set | |
17574 | for a text label. */ | |
17575 | if ((val & 1) != 0) | |
17576 | --val; | |
17577 | } | |
17578 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) | |
17579 | addr -= 4; | |
17580 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
17581 | addr -= 2; | |
17582 | ||
17583 | val -= addr & ~ ((1 << op->shift) - 1); | |
17584 | ||
17585 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
17586 | if (type == 'p' || type == 'q') | |
17587 | val /= 2; | |
17588 | ||
17589 | /* If any of the shifted bits are set, we must use an extended | |
17590 | opcode. If the address depends on the size of this | |
17591 | instruction, this can lead to a loop, so we arrange to always | |
17592 | use an extended opcode. We only check this when we are in | |
17593 | the main relaxation loop, when SEC is NULL. */ | |
17594 | if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL) | |
17595 | { | |
17596 | fragp->fr_subtype = | |
17597 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
17598 | return 1; | |
17599 | } | |
17600 | ||
17601 | /* If we are about to mark a frag as extended because the value | |
17602 | is precisely maxtiny + 1, then there is a chance of an | |
17603 | infinite loop as in the following code: | |
17604 | la $4,foo | |
17605 | .skip 1020 | |
17606 | .align 2 | |
17607 | foo: | |
17608 | In this case when the la is extended, foo is 0x3fc bytes | |
17609 | away, so the la can be shrunk, but then foo is 0x400 away, so | |
17610 | the la must be extended. To avoid this loop, we mark the | |
17611 | frag as extended if it was small, and is about to become | |
17612 | extended with a value of maxtiny + 1. */ | |
17613 | if (val == ((maxtiny + 1) << op->shift) | |
17614 | && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype) | |
17615 | && sec == NULL) | |
17616 | { | |
17617 | fragp->fr_subtype = | |
17618 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
17619 | return 1; | |
17620 | } | |
17621 | } | |
17622 | else if (symsec != absolute_section && sec != NULL) | |
17623 | as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation")); | |
17624 | ||
17625 | if ((val & ((1 << op->shift) - 1)) != 0 | |
17626 | || val < (mintiny << op->shift) | |
17627 | || val > (maxtiny << op->shift)) | |
17628 | return 1; | |
17629 | else | |
17630 | return 0; | |
17631 | } | |
17632 | ||
4a6a3df4 AO |
17633 | /* Compute the length of a branch sequence, and adjust the |
17634 | RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the | |
17635 | worst-case length is computed, with UPDATE being used to indicate | |
17636 | whether an unconditional (-1), branch-likely (+1) or regular (0) | |
17637 | branch is to be computed. */ | |
17638 | static int | |
17a2f251 | 17639 | relaxed_branch_length (fragS *fragp, asection *sec, int update) |
4a6a3df4 | 17640 | { |
b34976b6 | 17641 | bfd_boolean toofar; |
4a6a3df4 AO |
17642 | int length; |
17643 | ||
17644 | if (fragp | |
17645 | && S_IS_DEFINED (fragp->fr_symbol) | |
17646 | && sec == S_GET_SEGMENT (fragp->fr_symbol)) | |
17647 | { | |
17648 | addressT addr; | |
17649 | offsetT val; | |
17650 | ||
17651 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; | |
17652 | ||
17653 | addr = fragp->fr_address + fragp->fr_fix + 4; | |
17654 | ||
17655 | val -= addr; | |
17656 | ||
17657 | toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2); | |
17658 | } | |
17659 | else if (fragp) | |
17660 | /* If the symbol is not defined or it's in a different segment, | |
17661 | assume the user knows what's going on and emit a short | |
17662 | branch. */ | |
b34976b6 | 17663 | toofar = FALSE; |
4a6a3df4 | 17664 | else |
b34976b6 | 17665 | toofar = TRUE; |
4a6a3df4 AO |
17666 | |
17667 | if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) | |
17668 | fragp->fr_subtype | |
66b3e8da MR |
17669 | = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp->fr_subtype), |
17670 | RELAX_BRANCH_UNCOND (fragp->fr_subtype), | |
4a6a3df4 AO |
17671 | RELAX_BRANCH_LIKELY (fragp->fr_subtype), |
17672 | RELAX_BRANCH_LINK (fragp->fr_subtype), | |
17673 | toofar); | |
17674 | ||
17675 | length = 4; | |
17676 | if (toofar) | |
17677 | { | |
17678 | if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0)) | |
17679 | length += 8; | |
17680 | ||
17681 | if (mips_pic != NO_PIC) | |
17682 | { | |
17683 | /* Additional space for PIC loading of target address. */ | |
17684 | length += 8; | |
17685 | if (mips_opts.isa == ISA_MIPS1) | |
17686 | /* Additional space for $at-stabilizing nop. */ | |
17687 | length += 4; | |
17688 | } | |
17689 | ||
17690 | /* If branch is conditional. */ | |
17691 | if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0)) | |
17692 | length += 8; | |
17693 | } | |
b34976b6 | 17694 | |
4a6a3df4 AO |
17695 | return length; |
17696 | } | |
17697 | ||
df58fc94 RS |
17698 | /* Compute the length of a branch sequence, and adjust the |
17699 | RELAX_MICROMIPS_TOOFAR32 bit accordingly. If FRAGP is NULL, the | |
17700 | worst-case length is computed, with UPDATE being used to indicate | |
17701 | whether an unconditional (-1), or regular (0) branch is to be | |
17702 | computed. */ | |
17703 | ||
17704 | static int | |
17705 | relaxed_micromips_32bit_branch_length (fragS *fragp, asection *sec, int update) | |
17706 | { | |
17707 | bfd_boolean toofar; | |
17708 | int length; | |
17709 | ||
17710 | if (fragp | |
17711 | && S_IS_DEFINED (fragp->fr_symbol) | |
17712 | && sec == S_GET_SEGMENT (fragp->fr_symbol)) | |
17713 | { | |
17714 | addressT addr; | |
17715 | offsetT val; | |
17716 | ||
17717 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; | |
17718 | /* Ignore the low bit in the target, since it will be set | |
17719 | for a text label. */ | |
17720 | if ((val & 1) != 0) | |
17721 | --val; | |
17722 | ||
17723 | addr = fragp->fr_address + fragp->fr_fix + 4; | |
17724 | ||
17725 | val -= addr; | |
17726 | ||
17727 | toofar = val < - (0x8000 << 1) || val >= (0x8000 << 1); | |
17728 | } | |
17729 | else if (fragp) | |
17730 | /* If the symbol is not defined or it's in a different segment, | |
17731 | assume the user knows what's going on and emit a short | |
17732 | branch. */ | |
17733 | toofar = FALSE; | |
17734 | else | |
17735 | toofar = TRUE; | |
17736 | ||
17737 | if (fragp && update | |
17738 | && toofar != RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype)) | |
17739 | fragp->fr_subtype = (toofar | |
17740 | ? RELAX_MICROMIPS_MARK_TOOFAR32 (fragp->fr_subtype) | |
17741 | : RELAX_MICROMIPS_CLEAR_TOOFAR32 (fragp->fr_subtype)); | |
17742 | ||
17743 | length = 4; | |
17744 | if (toofar) | |
17745 | { | |
17746 | bfd_boolean compact_known = fragp != NULL; | |
17747 | bfd_boolean compact = FALSE; | |
17748 | bfd_boolean uncond; | |
17749 | ||
17750 | if (compact_known) | |
17751 | compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype); | |
17752 | if (fragp) | |
17753 | uncond = RELAX_MICROMIPS_UNCOND (fragp->fr_subtype); | |
17754 | else | |
17755 | uncond = update < 0; | |
17756 | ||
17757 | /* If label is out of range, we turn branch <br>: | |
17758 | ||
17759 | <br> label # 4 bytes | |
17760 | 0: | |
17761 | ||
17762 | into: | |
17763 | ||
17764 | j label # 4 bytes | |
17765 | nop # 2 bytes if compact && !PIC | |
17766 | 0: | |
17767 | */ | |
17768 | if (mips_pic == NO_PIC && (!compact_known || compact)) | |
17769 | length += 2; | |
17770 | ||
17771 | /* If assembling PIC code, we further turn: | |
17772 | ||
17773 | j label # 4 bytes | |
17774 | ||
17775 | into: | |
17776 | ||
17777 | lw/ld at, %got(label)(gp) # 4 bytes | |
17778 | d/addiu at, %lo(label) # 4 bytes | |
17779 | jr/c at # 2 bytes | |
17780 | */ | |
17781 | if (mips_pic != NO_PIC) | |
17782 | length += 6; | |
17783 | ||
17784 | /* If branch <br> is conditional, we prepend negated branch <brneg>: | |
17785 | ||
17786 | <brneg> 0f # 4 bytes | |
17787 | nop # 2 bytes if !compact | |
17788 | */ | |
17789 | if (!uncond) | |
17790 | length += (compact_known && compact) ? 4 : 6; | |
17791 | } | |
17792 | ||
17793 | return length; | |
17794 | } | |
17795 | ||
17796 | /* Compute the length of a branch, and adjust the RELAX_MICROMIPS_TOOFAR16 | |
17797 | bit accordingly. */ | |
17798 | ||
17799 | static int | |
17800 | relaxed_micromips_16bit_branch_length (fragS *fragp, asection *sec, int update) | |
17801 | { | |
17802 | bfd_boolean toofar; | |
17803 | ||
df58fc94 RS |
17804 | if (fragp |
17805 | && S_IS_DEFINED (fragp->fr_symbol) | |
17806 | && sec == S_GET_SEGMENT (fragp->fr_symbol)) | |
17807 | { | |
17808 | addressT addr; | |
17809 | offsetT val; | |
17810 | int type; | |
17811 | ||
17812 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; | |
17813 | /* Ignore the low bit in the target, since it will be set | |
17814 | for a text label. */ | |
17815 | if ((val & 1) != 0) | |
17816 | --val; | |
17817 | ||
17818 | /* Assume this is a 2-byte branch. */ | |
17819 | addr = fragp->fr_address + fragp->fr_fix + 2; | |
17820 | ||
17821 | /* We try to avoid the infinite loop by not adding 2 more bytes for | |
17822 | long branches. */ | |
17823 | ||
17824 | val -= addr; | |
17825 | ||
17826 | type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype); | |
17827 | if (type == 'D') | |
17828 | toofar = val < - (0x200 << 1) || val >= (0x200 << 1); | |
17829 | else if (type == 'E') | |
17830 | toofar = val < - (0x40 << 1) || val >= (0x40 << 1); | |
17831 | else | |
17832 | abort (); | |
17833 | } | |
17834 | else | |
17835 | /* If the symbol is not defined or it's in a different segment, | |
17836 | we emit a normal 32-bit branch. */ | |
17837 | toofar = TRUE; | |
17838 | ||
17839 | if (fragp && update | |
17840 | && toofar != RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype)) | |
17841 | fragp->fr_subtype | |
17842 | = toofar ? RELAX_MICROMIPS_MARK_TOOFAR16 (fragp->fr_subtype) | |
17843 | : RELAX_MICROMIPS_CLEAR_TOOFAR16 (fragp->fr_subtype); | |
17844 | ||
17845 | if (toofar) | |
17846 | return 4; | |
17847 | ||
17848 | return 2; | |
17849 | } | |
17850 | ||
252b5132 RH |
17851 | /* Estimate the size of a frag before relaxing. Unless this is the |
17852 | mips16, we are not really relaxing here, and the final size is | |
17853 | encoded in the subtype information. For the mips16, we have to | |
17854 | decide whether we are using an extended opcode or not. */ | |
17855 | ||
252b5132 | 17856 | int |
17a2f251 | 17857 | md_estimate_size_before_relax (fragS *fragp, asection *segtype) |
252b5132 | 17858 | { |
5919d012 | 17859 | int change; |
252b5132 | 17860 | |
4a6a3df4 AO |
17861 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
17862 | { | |
17863 | ||
b34976b6 AM |
17864 | fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE); |
17865 | ||
4a6a3df4 AO |
17866 | return fragp->fr_var; |
17867 | } | |
17868 | ||
252b5132 | 17869 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
177b4a6a AO |
17870 | /* We don't want to modify the EXTENDED bit here; it might get us |
17871 | into infinite loops. We change it only in mips_relax_frag(). */ | |
17872 | return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2); | |
252b5132 | 17873 | |
df58fc94 RS |
17874 | if (RELAX_MICROMIPS_P (fragp->fr_subtype)) |
17875 | { | |
17876 | int length = 4; | |
17877 | ||
17878 | if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0) | |
17879 | length = relaxed_micromips_16bit_branch_length (fragp, segtype, FALSE); | |
17880 | if (length == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)) | |
17881 | length = relaxed_micromips_32bit_branch_length (fragp, segtype, FALSE); | |
17882 | fragp->fr_var = length; | |
17883 | ||
17884 | return length; | |
17885 | } | |
17886 | ||
252b5132 | 17887 | if (mips_pic == NO_PIC) |
5919d012 | 17888 | change = nopic_need_relax (fragp->fr_symbol, 0); |
252b5132 | 17889 | else if (mips_pic == SVR4_PIC) |
5919d012 | 17890 | change = pic_need_relax (fragp->fr_symbol, segtype); |
0a44bf69 RS |
17891 | else if (mips_pic == VXWORKS_PIC) |
17892 | /* For vxworks, GOT16 relocations never have a corresponding LO16. */ | |
17893 | change = 0; | |
252b5132 RH |
17894 | else |
17895 | abort (); | |
17896 | ||
17897 | if (change) | |
17898 | { | |
4d7206a2 | 17899 | fragp->fr_subtype |= RELAX_USE_SECOND; |
4d7206a2 | 17900 | return -RELAX_FIRST (fragp->fr_subtype); |
252b5132 | 17901 | } |
4d7206a2 RS |
17902 | else |
17903 | return -RELAX_SECOND (fragp->fr_subtype); | |
252b5132 RH |
17904 | } |
17905 | ||
17906 | /* This is called to see whether a reloc against a defined symbol | |
de7e6852 | 17907 | should be converted into a reloc against a section. */ |
252b5132 RH |
17908 | |
17909 | int | |
17a2f251 | 17910 | mips_fix_adjustable (fixS *fixp) |
252b5132 | 17911 | { |
252b5132 RH |
17912 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
17913 | || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
17914 | return 0; | |
a161fe53 | 17915 | |
252b5132 RH |
17916 | if (fixp->fx_addsy == NULL) |
17917 | return 1; | |
a161fe53 | 17918 | |
de7e6852 RS |
17919 | /* If symbol SYM is in a mergeable section, relocations of the form |
17920 | SYM + 0 can usually be made section-relative. The mergeable data | |
17921 | is then identified by the section offset rather than by the symbol. | |
17922 | ||
17923 | However, if we're generating REL LO16 relocations, the offset is split | |
17924 | between the LO16 and parterning high part relocation. The linker will | |
17925 | need to recalculate the complete offset in order to correctly identify | |
17926 | the merge data. | |
17927 | ||
17928 | The linker has traditionally not looked for the parterning high part | |
17929 | relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be | |
17930 | placed anywhere. Rather than break backwards compatibility by changing | |
17931 | this, it seems better not to force the issue, and instead keep the | |
17932 | original symbol. This will work with either linker behavior. */ | |
738e5348 | 17933 | if ((lo16_reloc_p (fixp->fx_r_type) |
704803a9 | 17934 | || reloc_needs_lo_p (fixp->fx_r_type)) |
de7e6852 RS |
17935 | && HAVE_IN_PLACE_ADDENDS |
17936 | && (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_MERGE) != 0) | |
17937 | return 0; | |
17938 | ||
ce70d90a | 17939 | /* There is no place to store an in-place offset for JALR relocations. |
2de39019 CM |
17940 | Likewise an in-range offset of limited PC-relative relocations may |
17941 | overflow the in-place relocatable field if recalculated against the | |
17942 | start address of the symbol's containing section. */ | |
ce70d90a | 17943 | if (HAVE_IN_PLACE_ADDENDS |
2de39019 CM |
17944 | && (limited_pcrel_reloc_p (fixp->fx_r_type) |
17945 | || jalr_reloc_p (fixp->fx_r_type))) | |
1180b5a4 RS |
17946 | return 0; |
17947 | ||
b314ec0e RS |
17948 | /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve |
17949 | to a floating-point stub. The same is true for non-R_MIPS16_26 | |
17950 | relocations against MIPS16 functions; in this case, the stub becomes | |
17951 | the function's canonical address. | |
17952 | ||
17953 | Floating-point stubs are stored in unique .mips16.call.* or | |
17954 | .mips16.fn.* sections. If a stub T for function F is in section S, | |
17955 | the first relocation in section S must be against F; this is how the | |
17956 | linker determines the target function. All relocations that might | |
17957 | resolve to T must also be against F. We therefore have the following | |
17958 | restrictions, which are given in an intentionally-redundant way: | |
17959 | ||
17960 | 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16 | |
17961 | symbols. | |
17962 | ||
17963 | 2. We cannot reduce a stub's relocations against non-MIPS16 symbols | |
17964 | if that stub might be used. | |
17965 | ||
17966 | 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16 | |
17967 | symbols. | |
17968 | ||
17969 | 4. We cannot reduce a stub's relocations against MIPS16 symbols if | |
17970 | that stub might be used. | |
17971 | ||
17972 | There is a further restriction: | |
17973 | ||
df58fc94 RS |
17974 | 5. We cannot reduce jump relocations (R_MIPS_26, R_MIPS16_26 or |
17975 | R_MICROMIPS_26_S1) against MIPS16 or microMIPS symbols on | |
17976 | targets with in-place addends; the relocation field cannot | |
b314ec0e RS |
17977 | encode the low bit. |
17978 | ||
df58fc94 RS |
17979 | For simplicity, we deal with (3)-(4) by not reducing _any_ relocation |
17980 | against a MIPS16 symbol. We deal with (5) by by not reducing any | |
17981 | such relocations on REL targets. | |
b314ec0e RS |
17982 | |
17983 | We deal with (1)-(2) by saying that, if there's a R_MIPS16_26 | |
17984 | relocation against some symbol R, no relocation against R may be | |
17985 | reduced. (Note that this deals with (2) as well as (1) because | |
17986 | relocations against global symbols will never be reduced on ELF | |
17987 | targets.) This approach is a little simpler than trying to detect | |
17988 | stub sections, and gives the "all or nothing" per-symbol consistency | |
17989 | that we have for MIPS16 symbols. */ | |
f3ded42a | 17990 | if (fixp->fx_subsy == NULL |
30c09090 | 17991 | && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp->fx_addsy)) |
df58fc94 RS |
17992 | || *symbol_get_tc (fixp->fx_addsy) |
17993 | || (HAVE_IN_PLACE_ADDENDS | |
17994 | && ELF_ST_IS_MICROMIPS (S_GET_OTHER (fixp->fx_addsy)) | |
17995 | && jmp_reloc_p (fixp->fx_r_type)))) | |
252b5132 | 17996 | return 0; |
a161fe53 | 17997 | |
252b5132 RH |
17998 | return 1; |
17999 | } | |
18000 | ||
18001 | /* Translate internal representation of relocation info to BFD target | |
18002 | format. */ | |
18003 | ||
18004 | arelent ** | |
17a2f251 | 18005 | tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) |
252b5132 RH |
18006 | { |
18007 | static arelent *retval[4]; | |
18008 | arelent *reloc; | |
18009 | bfd_reloc_code_real_type code; | |
18010 | ||
4b0cff4e TS |
18011 | memset (retval, 0, sizeof(retval)); |
18012 | reloc = retval[0] = (arelent *) xcalloc (1, sizeof (arelent)); | |
49309057 ILT |
18013 | reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); |
18014 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
252b5132 RH |
18015 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; |
18016 | ||
bad36eac DJ |
18017 | if (fixp->fx_pcrel) |
18018 | { | |
df58fc94 RS |
18019 | gas_assert (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2 |
18020 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1 | |
18021 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1 | |
b47468a6 CM |
18022 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1 |
18023 | || fixp->fx_r_type == BFD_RELOC_32_PCREL); | |
bad36eac DJ |
18024 | |
18025 | /* At this point, fx_addnumber is "symbol offset - pcrel address". | |
18026 | Relocations want only the symbol offset. */ | |
18027 | reloc->addend = fixp->fx_addnumber + reloc->address; | |
bad36eac DJ |
18028 | } |
18029 | else | |
18030 | reloc->addend = fixp->fx_addnumber; | |
252b5132 | 18031 | |
438c16b8 TS |
18032 | /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable |
18033 | entry to be used in the relocation's section offset. */ | |
18034 | if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
252b5132 RH |
18035 | { |
18036 | reloc->address = reloc->addend; | |
18037 | reloc->addend = 0; | |
18038 | } | |
18039 | ||
252b5132 | 18040 | code = fixp->fx_r_type; |
252b5132 | 18041 | |
bad36eac | 18042 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); |
252b5132 RH |
18043 | if (reloc->howto == NULL) |
18044 | { | |
18045 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
18046 | _("Can not represent %s relocation in this object file format"), | |
18047 | bfd_get_reloc_code_name (code)); | |
18048 | retval[0] = NULL; | |
18049 | } | |
18050 | ||
18051 | return retval; | |
18052 | } | |
18053 | ||
18054 | /* Relax a machine dependent frag. This returns the amount by which | |
18055 | the current size of the frag should change. */ | |
18056 | ||
18057 | int | |
17a2f251 | 18058 | mips_relax_frag (asection *sec, fragS *fragp, long stretch) |
252b5132 | 18059 | { |
4a6a3df4 AO |
18060 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
18061 | { | |
18062 | offsetT old_var = fragp->fr_var; | |
b34976b6 AM |
18063 | |
18064 | fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE); | |
4a6a3df4 AO |
18065 | |
18066 | return fragp->fr_var - old_var; | |
18067 | } | |
18068 | ||
df58fc94 RS |
18069 | if (RELAX_MICROMIPS_P (fragp->fr_subtype)) |
18070 | { | |
18071 | offsetT old_var = fragp->fr_var; | |
18072 | offsetT new_var = 4; | |
18073 | ||
18074 | if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0) | |
18075 | new_var = relaxed_micromips_16bit_branch_length (fragp, sec, TRUE); | |
18076 | if (new_var == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)) | |
18077 | new_var = relaxed_micromips_32bit_branch_length (fragp, sec, TRUE); | |
18078 | fragp->fr_var = new_var; | |
18079 | ||
18080 | return new_var - old_var; | |
18081 | } | |
18082 | ||
252b5132 RH |
18083 | if (! RELAX_MIPS16_P (fragp->fr_subtype)) |
18084 | return 0; | |
18085 | ||
c4e7957c | 18086 | if (mips16_extended_frag (fragp, NULL, stretch)) |
252b5132 RH |
18087 | { |
18088 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
18089 | return 0; | |
18090 | fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype); | |
18091 | return 2; | |
18092 | } | |
18093 | else | |
18094 | { | |
18095 | if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
18096 | return 0; | |
18097 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype); | |
18098 | return -2; | |
18099 | } | |
18100 | ||
18101 | return 0; | |
18102 | } | |
18103 | ||
18104 | /* Convert a machine dependent frag. */ | |
18105 | ||
18106 | void | |
17a2f251 | 18107 | md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp) |
252b5132 | 18108 | { |
4a6a3df4 AO |
18109 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
18110 | { | |
4d68580a | 18111 | char *buf; |
4a6a3df4 AO |
18112 | unsigned long insn; |
18113 | expressionS exp; | |
18114 | fixS *fixp; | |
b34976b6 | 18115 | |
4d68580a RS |
18116 | buf = fragp->fr_literal + fragp->fr_fix; |
18117 | insn = read_insn (buf); | |
b34976b6 | 18118 | |
4a6a3df4 AO |
18119 | if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) |
18120 | { | |
18121 | /* We generate a fixup instead of applying it right now | |
18122 | because, if there are linker relaxations, we're going to | |
18123 | need the relocations. */ | |
18124 | exp.X_op = O_symbol; | |
18125 | exp.X_add_symbol = fragp->fr_symbol; | |
18126 | exp.X_add_number = fragp->fr_offset; | |
18127 | ||
4d68580a RS |
18128 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, TRUE, |
18129 | BFD_RELOC_16_PCREL_S2); | |
4a6a3df4 AO |
18130 | fixp->fx_file = fragp->fr_file; |
18131 | fixp->fx_line = fragp->fr_line; | |
b34976b6 | 18132 | |
4d68580a | 18133 | buf = write_insn (buf, insn); |
4a6a3df4 AO |
18134 | } |
18135 | else | |
18136 | { | |
18137 | int i; | |
18138 | ||
18139 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
5c4f07ba | 18140 | _("Relaxed out-of-range branch into a jump")); |
4a6a3df4 AO |
18141 | |
18142 | if (RELAX_BRANCH_UNCOND (fragp->fr_subtype)) | |
18143 | goto uncond; | |
18144 | ||
18145 | if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
18146 | { | |
18147 | /* Reverse the branch. */ | |
18148 | switch ((insn >> 28) & 0xf) | |
18149 | { | |
18150 | case 4: | |
3bf0dbfb MR |
18151 | /* bc[0-3][tf]l? instructions can have the condition |
18152 | reversed by tweaking a single TF bit, and their | |
18153 | opcodes all have 0x4???????. */ | |
18154 | gas_assert ((insn & 0xf3e00000) == 0x41000000); | |
4a6a3df4 AO |
18155 | insn ^= 0x00010000; |
18156 | break; | |
18157 | ||
18158 | case 0: | |
18159 | /* bltz 0x04000000 bgez 0x04010000 | |
54f4ddb3 | 18160 | bltzal 0x04100000 bgezal 0x04110000 */ |
9c2799c2 | 18161 | gas_assert ((insn & 0xfc0e0000) == 0x04000000); |
4a6a3df4 AO |
18162 | insn ^= 0x00010000; |
18163 | break; | |
b34976b6 | 18164 | |
4a6a3df4 AO |
18165 | case 1: |
18166 | /* beq 0x10000000 bne 0x14000000 | |
54f4ddb3 | 18167 | blez 0x18000000 bgtz 0x1c000000 */ |
4a6a3df4 AO |
18168 | insn ^= 0x04000000; |
18169 | break; | |
18170 | ||
18171 | default: | |
18172 | abort (); | |
18173 | } | |
18174 | } | |
18175 | ||
18176 | if (RELAX_BRANCH_LINK (fragp->fr_subtype)) | |
18177 | { | |
18178 | /* Clear the and-link bit. */ | |
9c2799c2 | 18179 | gas_assert ((insn & 0xfc1c0000) == 0x04100000); |
4a6a3df4 | 18180 | |
54f4ddb3 TS |
18181 | /* bltzal 0x04100000 bgezal 0x04110000 |
18182 | bltzall 0x04120000 bgezall 0x04130000 */ | |
4a6a3df4 AO |
18183 | insn &= ~0x00100000; |
18184 | } | |
18185 | ||
18186 | /* Branch over the branch (if the branch was likely) or the | |
18187 | full jump (not likely case). Compute the offset from the | |
18188 | current instruction to branch to. */ | |
18189 | if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
18190 | i = 16; | |
18191 | else | |
18192 | { | |
18193 | /* How many bytes in instructions we've already emitted? */ | |
4d68580a | 18194 | i = buf - fragp->fr_literal - fragp->fr_fix; |
4a6a3df4 AO |
18195 | /* How many bytes in instructions from here to the end? */ |
18196 | i = fragp->fr_var - i; | |
18197 | } | |
18198 | /* Convert to instruction count. */ | |
18199 | i >>= 2; | |
18200 | /* Branch counts from the next instruction. */ | |
b34976b6 | 18201 | i--; |
4a6a3df4 AO |
18202 | insn |= i; |
18203 | /* Branch over the jump. */ | |
4d68580a | 18204 | buf = write_insn (buf, insn); |
4a6a3df4 | 18205 | |
54f4ddb3 | 18206 | /* nop */ |
4d68580a | 18207 | buf = write_insn (buf, 0); |
4a6a3df4 AO |
18208 | |
18209 | if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
18210 | { | |
18211 | /* beql $0, $0, 2f */ | |
18212 | insn = 0x50000000; | |
18213 | /* Compute the PC offset from the current instruction to | |
18214 | the end of the variable frag. */ | |
18215 | /* How many bytes in instructions we've already emitted? */ | |
4d68580a | 18216 | i = buf - fragp->fr_literal - fragp->fr_fix; |
4a6a3df4 AO |
18217 | /* How many bytes in instructions from here to the end? */ |
18218 | i = fragp->fr_var - i; | |
18219 | /* Convert to instruction count. */ | |
18220 | i >>= 2; | |
18221 | /* Don't decrement i, because we want to branch over the | |
18222 | delay slot. */ | |
4a6a3df4 | 18223 | insn |= i; |
4a6a3df4 | 18224 | |
4d68580a RS |
18225 | buf = write_insn (buf, insn); |
18226 | buf = write_insn (buf, 0); | |
4a6a3df4 AO |
18227 | } |
18228 | ||
18229 | uncond: | |
18230 | if (mips_pic == NO_PIC) | |
18231 | { | |
18232 | /* j or jal. */ | |
18233 | insn = (RELAX_BRANCH_LINK (fragp->fr_subtype) | |
18234 | ? 0x0c000000 : 0x08000000); | |
18235 | exp.X_op = O_symbol; | |
18236 | exp.X_add_symbol = fragp->fr_symbol; | |
18237 | exp.X_add_number = fragp->fr_offset; | |
18238 | ||
4d68580a RS |
18239 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, |
18240 | FALSE, BFD_RELOC_MIPS_JMP); | |
4a6a3df4 AO |
18241 | fixp->fx_file = fragp->fr_file; |
18242 | fixp->fx_line = fragp->fr_line; | |
18243 | ||
4d68580a | 18244 | buf = write_insn (buf, insn); |
4a6a3df4 AO |
18245 | } |
18246 | else | |
18247 | { | |
66b3e8da MR |
18248 | unsigned long at = RELAX_BRANCH_AT (fragp->fr_subtype); |
18249 | ||
4a6a3df4 | 18250 | /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */ |
66b3e8da MR |
18251 | insn = HAVE_64BIT_ADDRESSES ? 0xdf800000 : 0x8f800000; |
18252 | insn |= at << OP_SH_RT; | |
4a6a3df4 AO |
18253 | exp.X_op = O_symbol; |
18254 | exp.X_add_symbol = fragp->fr_symbol; | |
18255 | exp.X_add_number = fragp->fr_offset; | |
18256 | ||
18257 | if (fragp->fr_offset) | |
18258 | { | |
18259 | exp.X_add_symbol = make_expr_symbol (&exp); | |
18260 | exp.X_add_number = 0; | |
18261 | } | |
18262 | ||
4d68580a RS |
18263 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, |
18264 | FALSE, BFD_RELOC_MIPS_GOT16); | |
4a6a3df4 AO |
18265 | fixp->fx_file = fragp->fr_file; |
18266 | fixp->fx_line = fragp->fr_line; | |
18267 | ||
4d68580a | 18268 | buf = write_insn (buf, insn); |
b34976b6 | 18269 | |
4a6a3df4 | 18270 | if (mips_opts.isa == ISA_MIPS1) |
4d68580a RS |
18271 | /* nop */ |
18272 | buf = write_insn (buf, 0); | |
4a6a3df4 AO |
18273 | |
18274 | /* d/addiu $at, $at, <sym> R_MIPS_LO16 */ | |
66b3e8da MR |
18275 | insn = HAVE_64BIT_ADDRESSES ? 0x64000000 : 0x24000000; |
18276 | insn |= at << OP_SH_RS | at << OP_SH_RT; | |
4a6a3df4 | 18277 | |
4d68580a RS |
18278 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, |
18279 | FALSE, BFD_RELOC_LO16); | |
4a6a3df4 AO |
18280 | fixp->fx_file = fragp->fr_file; |
18281 | fixp->fx_line = fragp->fr_line; | |
b34976b6 | 18282 | |
4d68580a | 18283 | buf = write_insn (buf, insn); |
4a6a3df4 AO |
18284 | |
18285 | /* j(al)r $at. */ | |
18286 | if (RELAX_BRANCH_LINK (fragp->fr_subtype)) | |
66b3e8da | 18287 | insn = 0x0000f809; |
4a6a3df4 | 18288 | else |
66b3e8da MR |
18289 | insn = 0x00000008; |
18290 | insn |= at << OP_SH_RS; | |
4a6a3df4 | 18291 | |
4d68580a | 18292 | buf = write_insn (buf, insn); |
4a6a3df4 AO |
18293 | } |
18294 | } | |
18295 | ||
4a6a3df4 | 18296 | fragp->fr_fix += fragp->fr_var; |
4d68580a | 18297 | gas_assert (buf == fragp->fr_literal + fragp->fr_fix); |
4a6a3df4 AO |
18298 | return; |
18299 | } | |
18300 | ||
df58fc94 RS |
18301 | /* Relax microMIPS branches. */ |
18302 | if (RELAX_MICROMIPS_P (fragp->fr_subtype)) | |
18303 | { | |
4d68580a | 18304 | char *buf = fragp->fr_literal + fragp->fr_fix; |
df58fc94 RS |
18305 | bfd_boolean compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype); |
18306 | bfd_boolean al = RELAX_MICROMIPS_LINK (fragp->fr_subtype); | |
18307 | int type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype); | |
2309ddf2 | 18308 | bfd_boolean short_ds; |
df58fc94 RS |
18309 | unsigned long insn; |
18310 | expressionS exp; | |
18311 | fixS *fixp; | |
18312 | ||
18313 | exp.X_op = O_symbol; | |
18314 | exp.X_add_symbol = fragp->fr_symbol; | |
18315 | exp.X_add_number = fragp->fr_offset; | |
18316 | ||
18317 | fragp->fr_fix += fragp->fr_var; | |
18318 | ||
18319 | /* Handle 16-bit branches that fit or are forced to fit. */ | |
18320 | if (type != 0 && !RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype)) | |
18321 | { | |
18322 | /* We generate a fixup instead of applying it right now, | |
18323 | because if there is linker relaxation, we're going to | |
18324 | need the relocations. */ | |
18325 | if (type == 'D') | |
4d68580a | 18326 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 2, &exp, TRUE, |
df58fc94 RS |
18327 | BFD_RELOC_MICROMIPS_10_PCREL_S1); |
18328 | else if (type == 'E') | |
4d68580a | 18329 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 2, &exp, TRUE, |
df58fc94 RS |
18330 | BFD_RELOC_MICROMIPS_7_PCREL_S1); |
18331 | else | |
18332 | abort (); | |
18333 | ||
18334 | fixp->fx_file = fragp->fr_file; | |
18335 | fixp->fx_line = fragp->fr_line; | |
18336 | ||
18337 | /* These relocations can have an addend that won't fit in | |
18338 | 2 octets. */ | |
18339 | fixp->fx_no_overflow = 1; | |
18340 | ||
18341 | return; | |
18342 | } | |
18343 | ||
2309ddf2 | 18344 | /* Handle 32-bit branches that fit or are forced to fit. */ |
df58fc94 RS |
18345 | if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype) |
18346 | || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype)) | |
18347 | { | |
18348 | /* We generate a fixup instead of applying it right now, | |
18349 | because if there is linker relaxation, we're going to | |
18350 | need the relocations. */ | |
4d68580a RS |
18351 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, TRUE, |
18352 | BFD_RELOC_MICROMIPS_16_PCREL_S1); | |
df58fc94 RS |
18353 | fixp->fx_file = fragp->fr_file; |
18354 | fixp->fx_line = fragp->fr_line; | |
18355 | ||
18356 | if (type == 0) | |
18357 | return; | |
18358 | } | |
18359 | ||
18360 | /* Relax 16-bit branches to 32-bit branches. */ | |
18361 | if (type != 0) | |
18362 | { | |
4d68580a | 18363 | insn = read_compressed_insn (buf, 2); |
df58fc94 RS |
18364 | |
18365 | if ((insn & 0xfc00) == 0xcc00) /* b16 */ | |
18366 | insn = 0x94000000; /* beq */ | |
18367 | else if ((insn & 0xdc00) == 0x8c00) /* beqz16/bnez16 */ | |
18368 | { | |
18369 | unsigned long regno; | |
18370 | ||
18371 | regno = (insn >> MICROMIPSOP_SH_MD) & MICROMIPSOP_MASK_MD; | |
18372 | regno = micromips_to_32_reg_d_map [regno]; | |
18373 | insn = ((insn & 0x2000) << 16) | 0x94000000; /* beq/bne */ | |
18374 | insn |= regno << MICROMIPSOP_SH_RS; | |
18375 | } | |
18376 | else | |
18377 | abort (); | |
18378 | ||
18379 | /* Nothing else to do, just write it out. */ | |
18380 | if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype) | |
18381 | || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype)) | |
18382 | { | |
4d68580a RS |
18383 | buf = write_compressed_insn (buf, insn, 4); |
18384 | gas_assert (buf == fragp->fr_literal + fragp->fr_fix); | |
df58fc94 RS |
18385 | return; |
18386 | } | |
18387 | } | |
18388 | else | |
4d68580a | 18389 | insn = read_compressed_insn (buf, 4); |
df58fc94 RS |
18390 | |
18391 | /* Relax 32-bit branches to a sequence of instructions. */ | |
18392 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
18393 | _("Relaxed out-of-range branch into a jump")); | |
18394 | ||
2309ddf2 MR |
18395 | /* Set the short-delay-slot bit. */ |
18396 | short_ds = al && (insn & 0x02000000) != 0; | |
df58fc94 RS |
18397 | |
18398 | if (!RELAX_MICROMIPS_UNCOND (fragp->fr_subtype)) | |
18399 | { | |
18400 | symbolS *l; | |
18401 | ||
18402 | /* Reverse the branch. */ | |
18403 | if ((insn & 0xfc000000) == 0x94000000 /* beq */ | |
18404 | || (insn & 0xfc000000) == 0xb4000000) /* bne */ | |
18405 | insn ^= 0x20000000; | |
18406 | else if ((insn & 0xffe00000) == 0x40000000 /* bltz */ | |
18407 | || (insn & 0xffe00000) == 0x40400000 /* bgez */ | |
18408 | || (insn & 0xffe00000) == 0x40800000 /* blez */ | |
18409 | || (insn & 0xffe00000) == 0x40c00000 /* bgtz */ | |
18410 | || (insn & 0xffe00000) == 0x40a00000 /* bnezc */ | |
18411 | || (insn & 0xffe00000) == 0x40e00000 /* beqzc */ | |
18412 | || (insn & 0xffe00000) == 0x40200000 /* bltzal */ | |
18413 | || (insn & 0xffe00000) == 0x40600000 /* bgezal */ | |
18414 | || (insn & 0xffe00000) == 0x42200000 /* bltzals */ | |
18415 | || (insn & 0xffe00000) == 0x42600000) /* bgezals */ | |
18416 | insn ^= 0x00400000; | |
18417 | else if ((insn & 0xffe30000) == 0x43800000 /* bc1f */ | |
18418 | || (insn & 0xffe30000) == 0x43a00000 /* bc1t */ | |
18419 | || (insn & 0xffe30000) == 0x42800000 /* bc2f */ | |
18420 | || (insn & 0xffe30000) == 0x42a00000) /* bc2t */ | |
18421 | insn ^= 0x00200000; | |
18422 | else | |
18423 | abort (); | |
18424 | ||
18425 | if (al) | |
18426 | { | |
18427 | /* Clear the and-link and short-delay-slot bits. */ | |
18428 | gas_assert ((insn & 0xfda00000) == 0x40200000); | |
18429 | ||
18430 | /* bltzal 0x40200000 bgezal 0x40600000 */ | |
18431 | /* bltzals 0x42200000 bgezals 0x42600000 */ | |
18432 | insn &= ~0x02200000; | |
18433 | } | |
18434 | ||
18435 | /* Make a label at the end for use with the branch. */ | |
18436 | l = symbol_new (micromips_label_name (), asec, fragp->fr_fix, fragp); | |
18437 | micromips_label_inc (); | |
f3ded42a | 18438 | S_SET_OTHER (l, ELF_ST_SET_MICROMIPS (S_GET_OTHER (l))); |
df58fc94 RS |
18439 | |
18440 | /* Refer to it. */ | |
4d68580a RS |
18441 | fixp = fix_new (fragp, buf - fragp->fr_literal, 4, l, 0, TRUE, |
18442 | BFD_RELOC_MICROMIPS_16_PCREL_S1); | |
df58fc94 RS |
18443 | fixp->fx_file = fragp->fr_file; |
18444 | fixp->fx_line = fragp->fr_line; | |
18445 | ||
18446 | /* Branch over the jump. */ | |
4d68580a | 18447 | buf = write_compressed_insn (buf, insn, 4); |
df58fc94 | 18448 | if (!compact) |
4d68580a RS |
18449 | /* nop */ |
18450 | buf = write_compressed_insn (buf, 0x0c00, 2); | |
df58fc94 RS |
18451 | } |
18452 | ||
18453 | if (mips_pic == NO_PIC) | |
18454 | { | |
2309ddf2 MR |
18455 | unsigned long jal = short_ds ? 0x74000000 : 0xf4000000; /* jal/s */ |
18456 | ||
df58fc94 RS |
18457 | /* j/jal/jals <sym> R_MICROMIPS_26_S1 */ |
18458 | insn = al ? jal : 0xd4000000; | |
18459 | ||
4d68580a RS |
18460 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE, |
18461 | BFD_RELOC_MICROMIPS_JMP); | |
df58fc94 RS |
18462 | fixp->fx_file = fragp->fr_file; |
18463 | fixp->fx_line = fragp->fr_line; | |
18464 | ||
4d68580a | 18465 | buf = write_compressed_insn (buf, insn, 4); |
df58fc94 | 18466 | if (compact) |
4d68580a RS |
18467 | /* nop */ |
18468 | buf = write_compressed_insn (buf, 0x0c00, 2); | |
df58fc94 RS |
18469 | } |
18470 | else | |
18471 | { | |
18472 | unsigned long at = RELAX_MICROMIPS_AT (fragp->fr_subtype); | |
2309ddf2 MR |
18473 | unsigned long jalr = short_ds ? 0x45e0 : 0x45c0; /* jalr/s */ |
18474 | unsigned long jr = compact ? 0x45a0 : 0x4580; /* jr/c */ | |
df58fc94 RS |
18475 | |
18476 | /* lw/ld $at, <sym>($gp) R_MICROMIPS_GOT16 */ | |
18477 | insn = HAVE_64BIT_ADDRESSES ? 0xdc1c0000 : 0xfc1c0000; | |
18478 | insn |= at << MICROMIPSOP_SH_RT; | |
18479 | ||
18480 | if (exp.X_add_number) | |
18481 | { | |
18482 | exp.X_add_symbol = make_expr_symbol (&exp); | |
18483 | exp.X_add_number = 0; | |
18484 | } | |
18485 | ||
4d68580a RS |
18486 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE, |
18487 | BFD_RELOC_MICROMIPS_GOT16); | |
df58fc94 RS |
18488 | fixp->fx_file = fragp->fr_file; |
18489 | fixp->fx_line = fragp->fr_line; | |
18490 | ||
4d68580a | 18491 | buf = write_compressed_insn (buf, insn, 4); |
df58fc94 RS |
18492 | |
18493 | /* d/addiu $at, $at, <sym> R_MICROMIPS_LO16 */ | |
18494 | insn = HAVE_64BIT_ADDRESSES ? 0x5c000000 : 0x30000000; | |
18495 | insn |= at << MICROMIPSOP_SH_RT | at << MICROMIPSOP_SH_RS; | |
18496 | ||
4d68580a RS |
18497 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE, |
18498 | BFD_RELOC_MICROMIPS_LO16); | |
df58fc94 RS |
18499 | fixp->fx_file = fragp->fr_file; |
18500 | fixp->fx_line = fragp->fr_line; | |
18501 | ||
4d68580a | 18502 | buf = write_compressed_insn (buf, insn, 4); |
df58fc94 RS |
18503 | |
18504 | /* jr/jrc/jalr/jalrs $at */ | |
18505 | insn = al ? jalr : jr; | |
18506 | insn |= at << MICROMIPSOP_SH_MJ; | |
18507 | ||
4d68580a | 18508 | buf = write_compressed_insn (buf, insn, 2); |
df58fc94 RS |
18509 | } |
18510 | ||
4d68580a | 18511 | gas_assert (buf == fragp->fr_literal + fragp->fr_fix); |
df58fc94 RS |
18512 | return; |
18513 | } | |
18514 | ||
252b5132 RH |
18515 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
18516 | { | |
18517 | int type; | |
3994f87e | 18518 | const struct mips16_immed_operand *op; |
252b5132 | 18519 | offsetT val; |
5c04167a RS |
18520 | char *buf; |
18521 | unsigned int user_length, length; | |
252b5132 | 18522 | unsigned long insn; |
5c04167a | 18523 | bfd_boolean ext; |
252b5132 RH |
18524 | |
18525 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
18526 | op = mips16_immed_operands; | |
18527 | while (op->type != type) | |
18528 | ++op; | |
18529 | ||
5c04167a | 18530 | ext = RELAX_MIPS16_EXTENDED (fragp->fr_subtype); |
5f5f22c0 | 18531 | val = resolve_symbol_value (fragp->fr_symbol); |
252b5132 RH |
18532 | if (op->pcrel) |
18533 | { | |
18534 | addressT addr; | |
18535 | ||
18536 | addr = fragp->fr_address + fragp->fr_fix; | |
18537 | ||
18538 | /* The rules for the base address of a PC relative reloc are | |
18539 | complicated; see mips16_extended_frag. */ | |
18540 | if (type == 'p' || type == 'q') | |
18541 | { | |
18542 | addr += 2; | |
18543 | if (ext) | |
18544 | addr += 2; | |
18545 | /* Ignore the low bit in the target, since it will be | |
18546 | set for a text label. */ | |
18547 | if ((val & 1) != 0) | |
18548 | --val; | |
18549 | } | |
18550 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) | |
18551 | addr -= 4; | |
18552 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
18553 | addr -= 2; | |
18554 | ||
18555 | addr &= ~ (addressT) ((1 << op->shift) - 1); | |
18556 | val -= addr; | |
18557 | ||
18558 | /* Make sure the section winds up with the alignment we have | |
18559 | assumed. */ | |
18560 | if (op->shift > 0) | |
18561 | record_alignment (asec, op->shift); | |
18562 | } | |
18563 | ||
18564 | if (ext | |
18565 | && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype) | |
18566 | || RELAX_MIPS16_DSLOT (fragp->fr_subtype))) | |
18567 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
18568 | _("extended instruction in delay slot")); | |
18569 | ||
5c04167a | 18570 | buf = fragp->fr_literal + fragp->fr_fix; |
252b5132 | 18571 | |
4d68580a | 18572 | insn = read_compressed_insn (buf, 2); |
5c04167a RS |
18573 | if (ext) |
18574 | insn |= MIPS16_EXTEND; | |
252b5132 | 18575 | |
5c04167a RS |
18576 | if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype)) |
18577 | user_length = 4; | |
18578 | else if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype)) | |
18579 | user_length = 2; | |
18580 | else | |
18581 | user_length = 0; | |
18582 | ||
43c0598f | 18583 | mips16_immed (fragp->fr_file, fragp->fr_line, type, |
c150d1d2 | 18584 | BFD_RELOC_UNUSED, val, user_length, &insn); |
252b5132 | 18585 | |
5c04167a RS |
18586 | length = (ext ? 4 : 2); |
18587 | gas_assert (mips16_opcode_length (insn) == length); | |
18588 | write_compressed_insn (buf, insn, length); | |
18589 | fragp->fr_fix += length; | |
252b5132 RH |
18590 | } |
18591 | else | |
18592 | { | |
df58fc94 RS |
18593 | relax_substateT subtype = fragp->fr_subtype; |
18594 | bfd_boolean second_longer = (subtype & RELAX_SECOND_LONGER) != 0; | |
18595 | bfd_boolean use_second = (subtype & RELAX_USE_SECOND) != 0; | |
4d7206a2 RS |
18596 | int first, second; |
18597 | fixS *fixp; | |
252b5132 | 18598 | |
df58fc94 RS |
18599 | first = RELAX_FIRST (subtype); |
18600 | second = RELAX_SECOND (subtype); | |
4d7206a2 | 18601 | fixp = (fixS *) fragp->fr_opcode; |
252b5132 | 18602 | |
df58fc94 RS |
18603 | /* If the delay slot chosen does not match the size of the instruction, |
18604 | then emit a warning. */ | |
18605 | if ((!use_second && (subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0) | |
18606 | || (use_second && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0)) | |
18607 | { | |
18608 | relax_substateT s; | |
18609 | const char *msg; | |
18610 | ||
18611 | s = subtype & (RELAX_DELAY_SLOT_16BIT | |
18612 | | RELAX_DELAY_SLOT_SIZE_FIRST | |
18613 | | RELAX_DELAY_SLOT_SIZE_SECOND); | |
18614 | msg = macro_warning (s); | |
18615 | if (msg != NULL) | |
db9b2be4 | 18616 | as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg); |
df58fc94 RS |
18617 | subtype &= ~s; |
18618 | } | |
18619 | ||
584892a6 | 18620 | /* Possibly emit a warning if we've chosen the longer option. */ |
df58fc94 | 18621 | if (use_second == second_longer) |
584892a6 | 18622 | { |
df58fc94 RS |
18623 | relax_substateT s; |
18624 | const char *msg; | |
18625 | ||
18626 | s = (subtype | |
18627 | & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT)); | |
18628 | msg = macro_warning (s); | |
18629 | if (msg != NULL) | |
db9b2be4 | 18630 | as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg); |
df58fc94 | 18631 | subtype &= ~s; |
584892a6 RS |
18632 | } |
18633 | ||
4d7206a2 RS |
18634 | /* Go through all the fixups for the first sequence. Disable them |
18635 | (by marking them as done) if we're going to use the second | |
18636 | sequence instead. */ | |
18637 | while (fixp | |
18638 | && fixp->fx_frag == fragp | |
18639 | && fixp->fx_where < fragp->fr_fix - second) | |
18640 | { | |
df58fc94 | 18641 | if (subtype & RELAX_USE_SECOND) |
4d7206a2 RS |
18642 | fixp->fx_done = 1; |
18643 | fixp = fixp->fx_next; | |
18644 | } | |
252b5132 | 18645 | |
4d7206a2 RS |
18646 | /* Go through the fixups for the second sequence. Disable them if |
18647 | we're going to use the first sequence, otherwise adjust their | |
18648 | addresses to account for the relaxation. */ | |
18649 | while (fixp && fixp->fx_frag == fragp) | |
18650 | { | |
df58fc94 | 18651 | if (subtype & RELAX_USE_SECOND) |
4d7206a2 RS |
18652 | fixp->fx_where -= first; |
18653 | else | |
18654 | fixp->fx_done = 1; | |
18655 | fixp = fixp->fx_next; | |
18656 | } | |
18657 | ||
18658 | /* Now modify the frag contents. */ | |
df58fc94 | 18659 | if (subtype & RELAX_USE_SECOND) |
4d7206a2 RS |
18660 | { |
18661 | char *start; | |
18662 | ||
18663 | start = fragp->fr_literal + fragp->fr_fix - first - second; | |
18664 | memmove (start, start + first, second); | |
18665 | fragp->fr_fix -= first; | |
18666 | } | |
18667 | else | |
18668 | fragp->fr_fix -= second; | |
252b5132 RH |
18669 | } |
18670 | } | |
18671 | ||
252b5132 RH |
18672 | /* This function is called after the relocs have been generated. |
18673 | We've been storing mips16 text labels as odd. Here we convert them | |
18674 | back to even for the convenience of the debugger. */ | |
18675 | ||
18676 | void | |
17a2f251 | 18677 | mips_frob_file_after_relocs (void) |
252b5132 RH |
18678 | { |
18679 | asymbol **syms; | |
18680 | unsigned int count, i; | |
18681 | ||
252b5132 RH |
18682 | syms = bfd_get_outsymbols (stdoutput); |
18683 | count = bfd_get_symcount (stdoutput); | |
18684 | for (i = 0; i < count; i++, syms++) | |
df58fc94 RS |
18685 | if (ELF_ST_IS_COMPRESSED (elf_symbol (*syms)->internal_elf_sym.st_other) |
18686 | && ((*syms)->value & 1) != 0) | |
18687 | { | |
18688 | (*syms)->value &= ~1; | |
18689 | /* If the symbol has an odd size, it was probably computed | |
18690 | incorrectly, so adjust that as well. */ | |
18691 | if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0) | |
18692 | ++elf_symbol (*syms)->internal_elf_sym.st_size; | |
18693 | } | |
252b5132 RH |
18694 | } |
18695 | ||
a1facbec MR |
18696 | /* This function is called whenever a label is defined, including fake |
18697 | labels instantiated off the dot special symbol. It is used when | |
18698 | handling branch delays; if a branch has a label, we assume we cannot | |
18699 | move it. This also bumps the value of the symbol by 1 in compressed | |
18700 | code. */ | |
252b5132 | 18701 | |
e1b47bd5 | 18702 | static void |
a1facbec | 18703 | mips_record_label (symbolS *sym) |
252b5132 | 18704 | { |
a8dbcb85 | 18705 | segment_info_type *si = seg_info (now_seg); |
252b5132 RH |
18706 | struct insn_label_list *l; |
18707 | ||
18708 | if (free_insn_labels == NULL) | |
18709 | l = (struct insn_label_list *) xmalloc (sizeof *l); | |
18710 | else | |
18711 | { | |
18712 | l = free_insn_labels; | |
18713 | free_insn_labels = l->next; | |
18714 | } | |
18715 | ||
18716 | l->label = sym; | |
a8dbcb85 TS |
18717 | l->next = si->label_list; |
18718 | si->label_list = l; | |
a1facbec | 18719 | } |
07a53e5c | 18720 | |
a1facbec MR |
18721 | /* This function is called as tc_frob_label() whenever a label is defined |
18722 | and adds a DWARF-2 record we only want for true labels. */ | |
18723 | ||
18724 | void | |
18725 | mips_define_label (symbolS *sym) | |
18726 | { | |
18727 | mips_record_label (sym); | |
07a53e5c | 18728 | dwarf2_emit_label (sym); |
252b5132 | 18729 | } |
e1b47bd5 RS |
18730 | |
18731 | /* This function is called by tc_new_dot_label whenever a new dot symbol | |
18732 | is defined. */ | |
18733 | ||
18734 | void | |
18735 | mips_add_dot_label (symbolS *sym) | |
18736 | { | |
18737 | mips_record_label (sym); | |
18738 | if (mips_assembling_insn && HAVE_CODE_COMPRESSION) | |
18739 | mips_compressed_mark_label (sym); | |
18740 | } | |
252b5132 | 18741 | \f |
252b5132 RH |
18742 | /* Some special processing for a MIPS ELF file. */ |
18743 | ||
18744 | void | |
17a2f251 | 18745 | mips_elf_final_processing (void) |
252b5132 RH |
18746 | { |
18747 | /* Write out the register information. */ | |
316f5878 | 18748 | if (mips_abi != N64_ABI) |
252b5132 RH |
18749 | { |
18750 | Elf32_RegInfo s; | |
18751 | ||
18752 | s.ri_gprmask = mips_gprmask; | |
18753 | s.ri_cprmask[0] = mips_cprmask[0]; | |
18754 | s.ri_cprmask[1] = mips_cprmask[1]; | |
18755 | s.ri_cprmask[2] = mips_cprmask[2]; | |
18756 | s.ri_cprmask[3] = mips_cprmask[3]; | |
18757 | /* The gp_value field is set by the MIPS ELF backend. */ | |
18758 | ||
18759 | bfd_mips_elf32_swap_reginfo_out (stdoutput, &s, | |
18760 | ((Elf32_External_RegInfo *) | |
18761 | mips_regmask_frag)); | |
18762 | } | |
18763 | else | |
18764 | { | |
18765 | Elf64_Internal_RegInfo s; | |
18766 | ||
18767 | s.ri_gprmask = mips_gprmask; | |
18768 | s.ri_pad = 0; | |
18769 | s.ri_cprmask[0] = mips_cprmask[0]; | |
18770 | s.ri_cprmask[1] = mips_cprmask[1]; | |
18771 | s.ri_cprmask[2] = mips_cprmask[2]; | |
18772 | s.ri_cprmask[3] = mips_cprmask[3]; | |
18773 | /* The gp_value field is set by the MIPS ELF backend. */ | |
18774 | ||
18775 | bfd_mips_elf64_swap_reginfo_out (stdoutput, &s, | |
18776 | ((Elf64_External_RegInfo *) | |
18777 | mips_regmask_frag)); | |
18778 | } | |
18779 | ||
18780 | /* Set the MIPS ELF flag bits. FIXME: There should probably be some | |
18781 | sort of BFD interface for this. */ | |
18782 | if (mips_any_noreorder) | |
18783 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER; | |
18784 | if (mips_pic != NO_PIC) | |
143d77c5 | 18785 | { |
8b828383 | 18786 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC; |
143d77c5 EC |
18787 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC; |
18788 | } | |
18789 | if (mips_abicalls) | |
18790 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC; | |
252b5132 | 18791 | |
b015e599 AP |
18792 | /* Set MIPS ELF flags for ASEs. Note that not all ASEs have flags |
18793 | defined at present; this might need to change in future. */ | |
a4672219 TS |
18794 | if (file_ase_mips16) |
18795 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16; | |
df58fc94 RS |
18796 | if (file_ase_micromips) |
18797 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MICROMIPS; | |
846ef2d0 | 18798 | if (file_ase & ASE_MDMX) |
deec1734 | 18799 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX; |
1f25f5d3 | 18800 | |
bdaaa2e1 | 18801 | /* Set the MIPS ELF ABI flags. */ |
316f5878 | 18802 | if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32) |
252b5132 | 18803 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32; |
316f5878 | 18804 | else if (mips_abi == O64_ABI) |
252b5132 | 18805 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64; |
316f5878 | 18806 | else if (mips_abi == EABI_ABI) |
252b5132 | 18807 | { |
316f5878 | 18808 | if (!file_mips_gp32) |
252b5132 RH |
18809 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64; |
18810 | else | |
18811 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32; | |
18812 | } | |
316f5878 | 18813 | else if (mips_abi == N32_ABI) |
be00bddd TS |
18814 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2; |
18815 | ||
c9914766 | 18816 | /* Nothing to do for N64_ABI. */ |
252b5132 RH |
18817 | |
18818 | if (mips_32bitmode) | |
18819 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE; | |
ad3fea08 TS |
18820 | |
18821 | #if 0 /* XXX FIXME */ | |
18822 | /* 32 bit code with 64 bit FP registers. */ | |
18823 | if (!file_mips_fp32 && ABI_NEEDS_32BIT_REGS (mips_abi)) | |
18824 | elf_elfheader (stdoutput)->e_flags |= ???; | |
18825 | #endif | |
252b5132 | 18826 | } |
252b5132 | 18827 | \f |
beae10d5 | 18828 | typedef struct proc { |
9b2f1d35 EC |
18829 | symbolS *func_sym; |
18830 | symbolS *func_end_sym; | |
beae10d5 KH |
18831 | unsigned long reg_mask; |
18832 | unsigned long reg_offset; | |
18833 | unsigned long fpreg_mask; | |
18834 | unsigned long fpreg_offset; | |
18835 | unsigned long frame_offset; | |
18836 | unsigned long frame_reg; | |
18837 | unsigned long pc_reg; | |
18838 | } procS; | |
252b5132 RH |
18839 | |
18840 | static procS cur_proc; | |
18841 | static procS *cur_proc_ptr; | |
18842 | static int numprocs; | |
18843 | ||
df58fc94 RS |
18844 | /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1", a microMIPS nop |
18845 | as "2", and a normal nop as "0". */ | |
18846 | ||
18847 | #define NOP_OPCODE_MIPS 0 | |
18848 | #define NOP_OPCODE_MIPS16 1 | |
18849 | #define NOP_OPCODE_MICROMIPS 2 | |
742a56fe RS |
18850 | |
18851 | char | |
18852 | mips_nop_opcode (void) | |
18853 | { | |
df58fc94 RS |
18854 | if (seg_info (now_seg)->tc_segment_info_data.micromips) |
18855 | return NOP_OPCODE_MICROMIPS; | |
18856 | else if (seg_info (now_seg)->tc_segment_info_data.mips16) | |
18857 | return NOP_OPCODE_MIPS16; | |
18858 | else | |
18859 | return NOP_OPCODE_MIPS; | |
742a56fe RS |
18860 | } |
18861 | ||
df58fc94 RS |
18862 | /* Fill in an rs_align_code fragment. Unlike elsewhere we want to use |
18863 | 32-bit microMIPS NOPs here (if applicable). */ | |
a19d8eb0 | 18864 | |
0a9ef439 | 18865 | void |
17a2f251 | 18866 | mips_handle_align (fragS *fragp) |
a19d8eb0 | 18867 | { |
df58fc94 | 18868 | char nop_opcode; |
742a56fe | 18869 | char *p; |
c67a084a NC |
18870 | int bytes, size, excess; |
18871 | valueT opcode; | |
742a56fe | 18872 | |
0a9ef439 RH |
18873 | if (fragp->fr_type != rs_align_code) |
18874 | return; | |
18875 | ||
742a56fe | 18876 | p = fragp->fr_literal + fragp->fr_fix; |
df58fc94 RS |
18877 | nop_opcode = *p; |
18878 | switch (nop_opcode) | |
a19d8eb0 | 18879 | { |
df58fc94 RS |
18880 | case NOP_OPCODE_MICROMIPS: |
18881 | opcode = micromips_nop32_insn.insn_opcode; | |
18882 | size = 4; | |
18883 | break; | |
18884 | case NOP_OPCODE_MIPS16: | |
c67a084a NC |
18885 | opcode = mips16_nop_insn.insn_opcode; |
18886 | size = 2; | |
df58fc94 RS |
18887 | break; |
18888 | case NOP_OPCODE_MIPS: | |
18889 | default: | |
c67a084a NC |
18890 | opcode = nop_insn.insn_opcode; |
18891 | size = 4; | |
df58fc94 | 18892 | break; |
c67a084a | 18893 | } |
a19d8eb0 | 18894 | |
c67a084a NC |
18895 | bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix; |
18896 | excess = bytes % size; | |
df58fc94 RS |
18897 | |
18898 | /* Handle the leading part if we're not inserting a whole number of | |
18899 | instructions, and make it the end of the fixed part of the frag. | |
18900 | Try to fit in a short microMIPS NOP if applicable and possible, | |
18901 | and use zeroes otherwise. */ | |
18902 | gas_assert (excess < 4); | |
18903 | fragp->fr_fix += excess; | |
18904 | switch (excess) | |
c67a084a | 18905 | { |
df58fc94 RS |
18906 | case 3: |
18907 | *p++ = '\0'; | |
18908 | /* Fall through. */ | |
18909 | case 2: | |
18910 | if (nop_opcode == NOP_OPCODE_MICROMIPS) | |
18911 | { | |
4d68580a | 18912 | p = write_compressed_insn (p, micromips_nop16_insn.insn_opcode, 2); |
df58fc94 RS |
18913 | break; |
18914 | } | |
18915 | *p++ = '\0'; | |
18916 | /* Fall through. */ | |
18917 | case 1: | |
18918 | *p++ = '\0'; | |
18919 | /* Fall through. */ | |
18920 | case 0: | |
18921 | break; | |
a19d8eb0 | 18922 | } |
c67a084a NC |
18923 | |
18924 | md_number_to_chars (p, opcode, size); | |
18925 | fragp->fr_var = size; | |
a19d8eb0 CP |
18926 | } |
18927 | ||
252b5132 | 18928 | static void |
17a2f251 | 18929 | md_obj_begin (void) |
252b5132 RH |
18930 | { |
18931 | } | |
18932 | ||
18933 | static void | |
17a2f251 | 18934 | md_obj_end (void) |
252b5132 | 18935 | { |
54f4ddb3 | 18936 | /* Check for premature end, nesting errors, etc. */ |
252b5132 | 18937 | if (cur_proc_ptr) |
9a41af64 | 18938 | as_warn (_("missing .end at end of assembly")); |
252b5132 RH |
18939 | } |
18940 | ||
18941 | static long | |
17a2f251 | 18942 | get_number (void) |
252b5132 RH |
18943 | { |
18944 | int negative = 0; | |
18945 | long val = 0; | |
18946 | ||
18947 | if (*input_line_pointer == '-') | |
18948 | { | |
18949 | ++input_line_pointer; | |
18950 | negative = 1; | |
18951 | } | |
3882b010 | 18952 | if (!ISDIGIT (*input_line_pointer)) |
956cd1d6 | 18953 | as_bad (_("expected simple number")); |
252b5132 RH |
18954 | if (input_line_pointer[0] == '0') |
18955 | { | |
18956 | if (input_line_pointer[1] == 'x') | |
18957 | { | |
18958 | input_line_pointer += 2; | |
3882b010 | 18959 | while (ISXDIGIT (*input_line_pointer)) |
252b5132 RH |
18960 | { |
18961 | val <<= 4; | |
18962 | val |= hex_value (*input_line_pointer++); | |
18963 | } | |
18964 | return negative ? -val : val; | |
18965 | } | |
18966 | else | |
18967 | { | |
18968 | ++input_line_pointer; | |
3882b010 | 18969 | while (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
18970 | { |
18971 | val <<= 3; | |
18972 | val |= *input_line_pointer++ - '0'; | |
18973 | } | |
18974 | return negative ? -val : val; | |
18975 | } | |
18976 | } | |
3882b010 | 18977 | if (!ISDIGIT (*input_line_pointer)) |
252b5132 RH |
18978 | { |
18979 | printf (_(" *input_line_pointer == '%c' 0x%02x\n"), | |
18980 | *input_line_pointer, *input_line_pointer); | |
956cd1d6 | 18981 | as_warn (_("invalid number")); |
252b5132 RH |
18982 | return -1; |
18983 | } | |
3882b010 | 18984 | while (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
18985 | { |
18986 | val *= 10; | |
18987 | val += *input_line_pointer++ - '0'; | |
18988 | } | |
18989 | return negative ? -val : val; | |
18990 | } | |
18991 | ||
18992 | /* The .file directive; just like the usual .file directive, but there | |
c5dd6aab DJ |
18993 | is an initial number which is the ECOFF file index. In the non-ECOFF |
18994 | case .file implies DWARF-2. */ | |
18995 | ||
18996 | static void | |
17a2f251 | 18997 | s_mips_file (int x ATTRIBUTE_UNUSED) |
c5dd6aab | 18998 | { |
ecb4347a DJ |
18999 | static int first_file_directive = 0; |
19000 | ||
c5dd6aab DJ |
19001 | if (ECOFF_DEBUGGING) |
19002 | { | |
19003 | get_number (); | |
19004 | s_app_file (0); | |
19005 | } | |
19006 | else | |
ecb4347a DJ |
19007 | { |
19008 | char *filename; | |
19009 | ||
19010 | filename = dwarf2_directive_file (0); | |
19011 | ||
19012 | /* Versions of GCC up to 3.1 start files with a ".file" | |
19013 | directive even for stabs output. Make sure that this | |
19014 | ".file" is handled. Note that you need a version of GCC | |
19015 | after 3.1 in order to support DWARF-2 on MIPS. */ | |
19016 | if (filename != NULL && ! first_file_directive) | |
19017 | { | |
19018 | (void) new_logical_line (filename, -1); | |
c04f5787 | 19019 | s_app_file_string (filename, 0); |
ecb4347a DJ |
19020 | } |
19021 | first_file_directive = 1; | |
19022 | } | |
c5dd6aab DJ |
19023 | } |
19024 | ||
19025 | /* The .loc directive, implying DWARF-2. */ | |
252b5132 RH |
19026 | |
19027 | static void | |
17a2f251 | 19028 | s_mips_loc (int x ATTRIBUTE_UNUSED) |
252b5132 | 19029 | { |
c5dd6aab DJ |
19030 | if (!ECOFF_DEBUGGING) |
19031 | dwarf2_directive_loc (0); | |
252b5132 RH |
19032 | } |
19033 | ||
252b5132 RH |
19034 | /* The .end directive. */ |
19035 | ||
19036 | static void | |
17a2f251 | 19037 | s_mips_end (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
19038 | { |
19039 | symbolS *p; | |
252b5132 | 19040 | |
7a621144 DJ |
19041 | /* Following functions need their own .frame and .cprestore directives. */ |
19042 | mips_frame_reg_valid = 0; | |
19043 | mips_cprestore_valid = 0; | |
19044 | ||
252b5132 RH |
19045 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
19046 | { | |
19047 | p = get_symbol (); | |
19048 | demand_empty_rest_of_line (); | |
19049 | } | |
19050 | else | |
19051 | p = NULL; | |
19052 | ||
14949570 | 19053 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0) |
252b5132 RH |
19054 | as_warn (_(".end not in text section")); |
19055 | ||
19056 | if (!cur_proc_ptr) | |
19057 | { | |
19058 | as_warn (_(".end directive without a preceding .ent directive.")); | |
19059 | demand_empty_rest_of_line (); | |
19060 | return; | |
19061 | } | |
19062 | ||
19063 | if (p != NULL) | |
19064 | { | |
9c2799c2 | 19065 | gas_assert (S_GET_NAME (p)); |
9b2f1d35 | 19066 | if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->func_sym))) |
252b5132 | 19067 | as_warn (_(".end symbol does not match .ent symbol.")); |
ecb4347a DJ |
19068 | |
19069 | if (debug_type == DEBUG_STABS) | |
19070 | stabs_generate_asm_endfunc (S_GET_NAME (p), | |
19071 | S_GET_NAME (p)); | |
252b5132 RH |
19072 | } |
19073 | else | |
19074 | as_warn (_(".end directive missing or unknown symbol")); | |
19075 | ||
9b2f1d35 EC |
19076 | /* Create an expression to calculate the size of the function. */ |
19077 | if (p && cur_proc_ptr) | |
19078 | { | |
19079 | OBJ_SYMFIELD_TYPE *obj = symbol_get_obj (p); | |
19080 | expressionS *exp = xmalloc (sizeof (expressionS)); | |
19081 | ||
19082 | obj->size = exp; | |
19083 | exp->X_op = O_subtract; | |
19084 | exp->X_add_symbol = symbol_temp_new_now (); | |
19085 | exp->X_op_symbol = p; | |
19086 | exp->X_add_number = 0; | |
19087 | ||
19088 | cur_proc_ptr->func_end_sym = exp->X_add_symbol; | |
19089 | } | |
19090 | ||
ecb4347a | 19091 | /* Generate a .pdr section. */ |
f3ded42a | 19092 | if (!ECOFF_DEBUGGING && mips_flag_pdr) |
ecb4347a DJ |
19093 | { |
19094 | segT saved_seg = now_seg; | |
19095 | subsegT saved_subseg = now_subseg; | |
ecb4347a DJ |
19096 | expressionS exp; |
19097 | char *fragp; | |
252b5132 | 19098 | |
252b5132 | 19099 | #ifdef md_flush_pending_output |
ecb4347a | 19100 | md_flush_pending_output (); |
252b5132 RH |
19101 | #endif |
19102 | ||
9c2799c2 | 19103 | gas_assert (pdr_seg); |
ecb4347a | 19104 | subseg_set (pdr_seg, 0); |
252b5132 | 19105 | |
ecb4347a DJ |
19106 | /* Write the symbol. */ |
19107 | exp.X_op = O_symbol; | |
19108 | exp.X_add_symbol = p; | |
19109 | exp.X_add_number = 0; | |
19110 | emit_expr (&exp, 4); | |
252b5132 | 19111 | |
ecb4347a | 19112 | fragp = frag_more (7 * 4); |
252b5132 | 19113 | |
17a2f251 TS |
19114 | md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4); |
19115 | md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4); | |
19116 | md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4); | |
19117 | md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4); | |
19118 | md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4); | |
19119 | md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4); | |
19120 | md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4); | |
252b5132 | 19121 | |
ecb4347a DJ |
19122 | subseg_set (saved_seg, saved_subseg); |
19123 | } | |
252b5132 RH |
19124 | |
19125 | cur_proc_ptr = NULL; | |
19126 | } | |
19127 | ||
19128 | /* The .aent and .ent directives. */ | |
19129 | ||
19130 | static void | |
17a2f251 | 19131 | s_mips_ent (int aent) |
252b5132 | 19132 | { |
252b5132 | 19133 | symbolS *symbolP; |
252b5132 RH |
19134 | |
19135 | symbolP = get_symbol (); | |
19136 | if (*input_line_pointer == ',') | |
f9419b05 | 19137 | ++input_line_pointer; |
252b5132 | 19138 | SKIP_WHITESPACE (); |
3882b010 | 19139 | if (ISDIGIT (*input_line_pointer) |
d9a62219 | 19140 | || *input_line_pointer == '-') |
874e8986 | 19141 | get_number (); |
252b5132 | 19142 | |
14949570 | 19143 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0) |
252b5132 RH |
19144 | as_warn (_(".ent or .aent not in text section.")); |
19145 | ||
19146 | if (!aent && cur_proc_ptr) | |
9a41af64 | 19147 | as_warn (_("missing .end")); |
252b5132 RH |
19148 | |
19149 | if (!aent) | |
19150 | { | |
7a621144 DJ |
19151 | /* This function needs its own .frame and .cprestore directives. */ |
19152 | mips_frame_reg_valid = 0; | |
19153 | mips_cprestore_valid = 0; | |
19154 | ||
252b5132 RH |
19155 | cur_proc_ptr = &cur_proc; |
19156 | memset (cur_proc_ptr, '\0', sizeof (procS)); | |
19157 | ||
9b2f1d35 | 19158 | cur_proc_ptr->func_sym = symbolP; |
252b5132 | 19159 | |
f9419b05 | 19160 | ++numprocs; |
ecb4347a DJ |
19161 | |
19162 | if (debug_type == DEBUG_STABS) | |
19163 | stabs_generate_asm_func (S_GET_NAME (symbolP), | |
19164 | S_GET_NAME (symbolP)); | |
252b5132 RH |
19165 | } |
19166 | ||
7c0fc524 MR |
19167 | symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION; |
19168 | ||
252b5132 RH |
19169 | demand_empty_rest_of_line (); |
19170 | } | |
19171 | ||
19172 | /* The .frame directive. If the mdebug section is present (IRIX 5 native) | |
bdaaa2e1 | 19173 | then ecoff.c (ecoff_directive_frame) is used. For embedded targets, |
252b5132 | 19174 | s_mips_frame is used so that we can set the PDR information correctly. |
bdaaa2e1 | 19175 | We can't use the ecoff routines because they make reference to the ecoff |
252b5132 RH |
19176 | symbol table (in the mdebug section). */ |
19177 | ||
19178 | static void | |
17a2f251 | 19179 | s_mips_frame (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 19180 | { |
f3ded42a RS |
19181 | if (ECOFF_DEBUGGING) |
19182 | s_ignore (ignore); | |
19183 | else | |
ecb4347a DJ |
19184 | { |
19185 | long val; | |
252b5132 | 19186 | |
ecb4347a DJ |
19187 | if (cur_proc_ptr == (procS *) NULL) |
19188 | { | |
19189 | as_warn (_(".frame outside of .ent")); | |
19190 | demand_empty_rest_of_line (); | |
19191 | return; | |
19192 | } | |
252b5132 | 19193 | |
ecb4347a DJ |
19194 | cur_proc_ptr->frame_reg = tc_get_register (1); |
19195 | ||
19196 | SKIP_WHITESPACE (); | |
19197 | if (*input_line_pointer++ != ',' | |
19198 | || get_absolute_expression_and_terminator (&val) != ',') | |
19199 | { | |
19200 | as_warn (_("Bad .frame directive")); | |
19201 | --input_line_pointer; | |
19202 | demand_empty_rest_of_line (); | |
19203 | return; | |
19204 | } | |
252b5132 | 19205 | |
ecb4347a DJ |
19206 | cur_proc_ptr->frame_offset = val; |
19207 | cur_proc_ptr->pc_reg = tc_get_register (0); | |
252b5132 | 19208 | |
252b5132 | 19209 | demand_empty_rest_of_line (); |
252b5132 | 19210 | } |
252b5132 RH |
19211 | } |
19212 | ||
bdaaa2e1 KH |
19213 | /* The .fmask and .mask directives. If the mdebug section is present |
19214 | (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For | |
252b5132 | 19215 | embedded targets, s_mips_mask is used so that we can set the PDR |
bdaaa2e1 | 19216 | information correctly. We can't use the ecoff routines because they |
252b5132 RH |
19217 | make reference to the ecoff symbol table (in the mdebug section). */ |
19218 | ||
19219 | static void | |
17a2f251 | 19220 | s_mips_mask (int reg_type) |
252b5132 | 19221 | { |
f3ded42a RS |
19222 | if (ECOFF_DEBUGGING) |
19223 | s_ignore (reg_type); | |
19224 | else | |
252b5132 | 19225 | { |
ecb4347a | 19226 | long mask, off; |
252b5132 | 19227 | |
ecb4347a DJ |
19228 | if (cur_proc_ptr == (procS *) NULL) |
19229 | { | |
19230 | as_warn (_(".mask/.fmask outside of .ent")); | |
19231 | demand_empty_rest_of_line (); | |
19232 | return; | |
19233 | } | |
252b5132 | 19234 | |
ecb4347a DJ |
19235 | if (get_absolute_expression_and_terminator (&mask) != ',') |
19236 | { | |
19237 | as_warn (_("Bad .mask/.fmask directive")); | |
19238 | --input_line_pointer; | |
19239 | demand_empty_rest_of_line (); | |
19240 | return; | |
19241 | } | |
252b5132 | 19242 | |
ecb4347a DJ |
19243 | off = get_absolute_expression (); |
19244 | ||
19245 | if (reg_type == 'F') | |
19246 | { | |
19247 | cur_proc_ptr->fpreg_mask = mask; | |
19248 | cur_proc_ptr->fpreg_offset = off; | |
19249 | } | |
19250 | else | |
19251 | { | |
19252 | cur_proc_ptr->reg_mask = mask; | |
19253 | cur_proc_ptr->reg_offset = off; | |
19254 | } | |
19255 | ||
19256 | demand_empty_rest_of_line (); | |
252b5132 | 19257 | } |
252b5132 RH |
19258 | } |
19259 | ||
316f5878 RS |
19260 | /* A table describing all the processors gas knows about. Names are |
19261 | matched in the order listed. | |
e7af610e | 19262 | |
316f5878 RS |
19263 | To ease comparison, please keep this table in the same order as |
19264 | gcc's mips_cpu_info_table[]. */ | |
e972090a NC |
19265 | static const struct mips_cpu_info mips_cpu_info_table[] = |
19266 | { | |
316f5878 | 19267 | /* Entries for generic ISAs */ |
d16afab6 RS |
19268 | { "mips1", MIPS_CPU_IS_ISA, 0, ISA_MIPS1, CPU_R3000 }, |
19269 | { "mips2", MIPS_CPU_IS_ISA, 0, ISA_MIPS2, CPU_R6000 }, | |
19270 | { "mips3", MIPS_CPU_IS_ISA, 0, ISA_MIPS3, CPU_R4000 }, | |
19271 | { "mips4", MIPS_CPU_IS_ISA, 0, ISA_MIPS4, CPU_R8000 }, | |
19272 | { "mips5", MIPS_CPU_IS_ISA, 0, ISA_MIPS5, CPU_MIPS5 }, | |
19273 | { "mips32", MIPS_CPU_IS_ISA, 0, ISA_MIPS32, CPU_MIPS32 }, | |
19274 | { "mips32r2", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19275 | { "mips64", MIPS_CPU_IS_ISA, 0, ISA_MIPS64, CPU_MIPS64 }, | |
19276 | { "mips64r2", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R2, CPU_MIPS64R2 }, | |
316f5878 RS |
19277 | |
19278 | /* MIPS I */ | |
d16afab6 RS |
19279 | { "r3000", 0, 0, ISA_MIPS1, CPU_R3000 }, |
19280 | { "r2000", 0, 0, ISA_MIPS1, CPU_R3000 }, | |
19281 | { "r3900", 0, 0, ISA_MIPS1, CPU_R3900 }, | |
316f5878 RS |
19282 | |
19283 | /* MIPS II */ | |
d16afab6 | 19284 | { "r6000", 0, 0, ISA_MIPS2, CPU_R6000 }, |
316f5878 RS |
19285 | |
19286 | /* MIPS III */ | |
d16afab6 RS |
19287 | { "r4000", 0, 0, ISA_MIPS3, CPU_R4000 }, |
19288 | { "r4010", 0, 0, ISA_MIPS2, CPU_R4010 }, | |
19289 | { "vr4100", 0, 0, ISA_MIPS3, CPU_VR4100 }, | |
19290 | { "vr4111", 0, 0, ISA_MIPS3, CPU_R4111 }, | |
19291 | { "vr4120", 0, 0, ISA_MIPS3, CPU_VR4120 }, | |
19292 | { "vr4130", 0, 0, ISA_MIPS3, CPU_VR4120 }, | |
19293 | { "vr4181", 0, 0, ISA_MIPS3, CPU_R4111 }, | |
19294 | { "vr4300", 0, 0, ISA_MIPS3, CPU_R4300 }, | |
19295 | { "r4400", 0, 0, ISA_MIPS3, CPU_R4400 }, | |
19296 | { "r4600", 0, 0, ISA_MIPS3, CPU_R4600 }, | |
19297 | { "orion", 0, 0, ISA_MIPS3, CPU_R4600 }, | |
19298 | { "r4650", 0, 0, ISA_MIPS3, CPU_R4650 }, | |
19299 | { "r5900", 0, 0, ISA_MIPS3, CPU_R5900 }, | |
b15591bb | 19300 | /* ST Microelectronics Loongson 2E and 2F cores */ |
d16afab6 RS |
19301 | { "loongson2e", 0, 0, ISA_MIPS3, CPU_LOONGSON_2E }, |
19302 | { "loongson2f", 0, 0, ISA_MIPS3, CPU_LOONGSON_2F }, | |
316f5878 RS |
19303 | |
19304 | /* MIPS IV */ | |
d16afab6 RS |
19305 | { "r8000", 0, 0, ISA_MIPS4, CPU_R8000 }, |
19306 | { "r10000", 0, 0, ISA_MIPS4, CPU_R10000 }, | |
19307 | { "r12000", 0, 0, ISA_MIPS4, CPU_R12000 }, | |
19308 | { "r14000", 0, 0, ISA_MIPS4, CPU_R14000 }, | |
19309 | { "r16000", 0, 0, ISA_MIPS4, CPU_R16000 }, | |
19310 | { "vr5000", 0, 0, ISA_MIPS4, CPU_R5000 }, | |
19311 | { "vr5400", 0, 0, ISA_MIPS4, CPU_VR5400 }, | |
19312 | { "vr5500", 0, 0, ISA_MIPS4, CPU_VR5500 }, | |
19313 | { "rm5200", 0, 0, ISA_MIPS4, CPU_R5000 }, | |
19314 | { "rm5230", 0, 0, ISA_MIPS4, CPU_R5000 }, | |
19315 | { "rm5231", 0, 0, ISA_MIPS4, CPU_R5000 }, | |
19316 | { "rm5261", 0, 0, ISA_MIPS4, CPU_R5000 }, | |
19317 | { "rm5721", 0, 0, ISA_MIPS4, CPU_R5000 }, | |
19318 | { "rm7000", 0, 0, ISA_MIPS4, CPU_RM7000 }, | |
19319 | { "rm9000", 0, 0, ISA_MIPS4, CPU_RM9000 }, | |
316f5878 RS |
19320 | |
19321 | /* MIPS 32 */ | |
d16afab6 RS |
19322 | { "4kc", 0, 0, ISA_MIPS32, CPU_MIPS32 }, |
19323 | { "4km", 0, 0, ISA_MIPS32, CPU_MIPS32 }, | |
19324 | { "4kp", 0, 0, ISA_MIPS32, CPU_MIPS32 }, | |
19325 | { "4ksc", 0, ASE_SMARTMIPS, ISA_MIPS32, CPU_MIPS32 }, | |
ad3fea08 TS |
19326 | |
19327 | /* MIPS 32 Release 2 */ | |
d16afab6 RS |
19328 | { "4kec", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
19329 | { "4kem", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19330 | { "4kep", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19331 | { "4ksd", 0, ASE_SMARTMIPS, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19332 | { "m4k", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19333 | { "m4kp", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19334 | { "m14k", 0, ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19335 | { "m14kc", 0, ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19336 | { "m14ke", 0, ASE_DSP | ASE_DSPR2 | ASE_MCU, | |
19337 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19338 | { "m14kec", 0, ASE_DSP | ASE_DSPR2 | ASE_MCU, | |
19339 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19340 | { "24kc", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19341 | { "24kf2_1", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19342 | { "24kf", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19343 | { "24kf1_1", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 | 19344 | /* Deprecated forms of the above. */ |
d16afab6 RS |
19345 | { "24kfx", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
19346 | { "24kx", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
01fd108f | 19347 | /* 24KE is a 24K with DSP ASE, other ASEs are optional. */ |
d16afab6 RS |
19348 | { "24kec", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
19349 | { "24kef2_1", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19350 | { "24kef", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19351 | { "24kef1_1", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 | 19352 | /* Deprecated forms of the above. */ |
d16afab6 RS |
19353 | { "24kefx", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
19354 | { "24kex", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
01fd108f | 19355 | /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */ |
d16afab6 RS |
19356 | { "34kc", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, |
19357 | { "34kf2_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19358 | { "34kf", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19359 | { "34kf1_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 | 19360 | /* Deprecated forms of the above. */ |
d16afab6 RS |
19361 | { "34kfx", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, |
19362 | { "34kx", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
711eefe4 | 19363 | /* 34Kn is a 34kc without DSP. */ |
d16afab6 | 19364 | { "34kn", 0, ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, |
01fd108f | 19365 | /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */ |
d16afab6 RS |
19366 | { "74kc", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, |
19367 | { "74kf2_1", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19368 | { "74kf", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19369 | { "74kf1_1", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19370 | { "74kf3_2", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 | 19371 | /* Deprecated forms of the above. */ |
d16afab6 RS |
19372 | { "74kfx", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, |
19373 | { "74kx", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
30f8113a | 19374 | /* 1004K cores are multiprocessor versions of the 34K. */ |
d16afab6 RS |
19375 | { "1004kc", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, |
19376 | { "1004kf2_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19377 | { "1004kf", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19378 | { "1004kf1_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
32b26a03 | 19379 | |
316f5878 | 19380 | /* MIPS 64 */ |
d16afab6 RS |
19381 | { "5kc", 0, 0, ISA_MIPS64, CPU_MIPS64 }, |
19382 | { "5kf", 0, 0, ISA_MIPS64, CPU_MIPS64 }, | |
19383 | { "20kc", 0, ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 }, | |
19384 | { "25kf", 0, ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 }, | |
ad3fea08 | 19385 | |
c7a23324 | 19386 | /* Broadcom SB-1 CPU core */ |
d16afab6 | 19387 | { "sb1", 0, ASE_MIPS3D | ASE_MDMX, ISA_MIPS64, CPU_SB1 }, |
1e85aad8 | 19388 | /* Broadcom SB-1A CPU core */ |
d16afab6 | 19389 | { "sb1a", 0, ASE_MIPS3D | ASE_MDMX, ISA_MIPS64, CPU_SB1 }, |
d051516a | 19390 | |
d16afab6 | 19391 | { "loongson3a", 0, 0, ISA_MIPS64, CPU_LOONGSON_3A }, |
e7af610e | 19392 | |
ed163775 MR |
19393 | /* MIPS 64 Release 2 */ |
19394 | ||
967344c6 | 19395 | /* Cavium Networks Octeon CPU core */ |
d16afab6 RS |
19396 | { "octeon", 0, 0, ISA_MIPS64R2, CPU_OCTEON }, |
19397 | { "octeon+", 0, 0, ISA_MIPS64R2, CPU_OCTEONP }, | |
19398 | { "octeon2", 0, 0, ISA_MIPS64R2, CPU_OCTEON2 }, | |
967344c6 | 19399 | |
52b6b6b9 | 19400 | /* RMI Xlr */ |
d16afab6 | 19401 | { "xlr", 0, 0, ISA_MIPS64, CPU_XLR }, |
52b6b6b9 | 19402 | |
55a36193 MK |
19403 | /* Broadcom XLP. |
19404 | XLP is mostly like XLR, with the prominent exception that it is | |
19405 | MIPS64R2 rather than MIPS64. */ | |
d16afab6 | 19406 | { "xlp", 0, 0, ISA_MIPS64R2, CPU_XLR }, |
55a36193 | 19407 | |
316f5878 | 19408 | /* End marker */ |
d16afab6 | 19409 | { NULL, 0, 0, 0, 0 } |
316f5878 | 19410 | }; |
e7af610e | 19411 | |
84ea6cf2 | 19412 | |
316f5878 RS |
19413 | /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL |
19414 | with a final "000" replaced by "k". Ignore case. | |
e7af610e | 19415 | |
316f5878 | 19416 | Note: this function is shared between GCC and GAS. */ |
c6c98b38 | 19417 | |
b34976b6 | 19418 | static bfd_boolean |
17a2f251 | 19419 | mips_strict_matching_cpu_name_p (const char *canonical, const char *given) |
316f5878 RS |
19420 | { |
19421 | while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical)) | |
19422 | given++, canonical++; | |
19423 | ||
19424 | return ((*given == 0 && *canonical == 0) | |
19425 | || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0)); | |
19426 | } | |
19427 | ||
19428 | ||
19429 | /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied | |
19430 | CPU name. We've traditionally allowed a lot of variation here. | |
19431 | ||
19432 | Note: this function is shared between GCC and GAS. */ | |
19433 | ||
b34976b6 | 19434 | static bfd_boolean |
17a2f251 | 19435 | mips_matching_cpu_name_p (const char *canonical, const char *given) |
316f5878 RS |
19436 | { |
19437 | /* First see if the name matches exactly, or with a final "000" | |
19438 | turned into "k". */ | |
19439 | if (mips_strict_matching_cpu_name_p (canonical, given)) | |
b34976b6 | 19440 | return TRUE; |
316f5878 RS |
19441 | |
19442 | /* If not, try comparing based on numerical designation alone. | |
19443 | See if GIVEN is an unadorned number, or 'r' followed by a number. */ | |
19444 | if (TOLOWER (*given) == 'r') | |
19445 | given++; | |
19446 | if (!ISDIGIT (*given)) | |
b34976b6 | 19447 | return FALSE; |
316f5878 RS |
19448 | |
19449 | /* Skip over some well-known prefixes in the canonical name, | |
19450 | hoping to find a number there too. */ | |
19451 | if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r') | |
19452 | canonical += 2; | |
19453 | else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm') | |
19454 | canonical += 2; | |
19455 | else if (TOLOWER (canonical[0]) == 'r') | |
19456 | canonical += 1; | |
19457 | ||
19458 | return mips_strict_matching_cpu_name_p (canonical, given); | |
19459 | } | |
19460 | ||
19461 | ||
19462 | /* Parse an option that takes the name of a processor as its argument. | |
19463 | OPTION is the name of the option and CPU_STRING is the argument. | |
19464 | Return the corresponding processor enumeration if the CPU_STRING is | |
19465 | recognized, otherwise report an error and return null. | |
19466 | ||
19467 | A similar function exists in GCC. */ | |
e7af610e NC |
19468 | |
19469 | static const struct mips_cpu_info * | |
17a2f251 | 19470 | mips_parse_cpu (const char *option, const char *cpu_string) |
e7af610e | 19471 | { |
316f5878 | 19472 | const struct mips_cpu_info *p; |
e7af610e | 19473 | |
316f5878 RS |
19474 | /* 'from-abi' selects the most compatible architecture for the given |
19475 | ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the | |
19476 | EABIs, we have to decide whether we're using the 32-bit or 64-bit | |
19477 | version. Look first at the -mgp options, if given, otherwise base | |
19478 | the choice on MIPS_DEFAULT_64BIT. | |
e7af610e | 19479 | |
316f5878 RS |
19480 | Treat NO_ABI like the EABIs. One reason to do this is that the |
19481 | plain 'mips' and 'mips64' configs have 'from-abi' as their default | |
19482 | architecture. This code picks MIPS I for 'mips' and MIPS III for | |
19483 | 'mips64', just as we did in the days before 'from-abi'. */ | |
19484 | if (strcasecmp (cpu_string, "from-abi") == 0) | |
19485 | { | |
19486 | if (ABI_NEEDS_32BIT_REGS (mips_abi)) | |
19487 | return mips_cpu_info_from_isa (ISA_MIPS1); | |
19488 | ||
19489 | if (ABI_NEEDS_64BIT_REGS (mips_abi)) | |
19490 | return mips_cpu_info_from_isa (ISA_MIPS3); | |
19491 | ||
19492 | if (file_mips_gp32 >= 0) | |
19493 | return mips_cpu_info_from_isa (file_mips_gp32 ? ISA_MIPS1 : ISA_MIPS3); | |
19494 | ||
19495 | return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT | |
19496 | ? ISA_MIPS3 | |
19497 | : ISA_MIPS1); | |
19498 | } | |
19499 | ||
19500 | /* 'default' has traditionally been a no-op. Probably not very useful. */ | |
19501 | if (strcasecmp (cpu_string, "default") == 0) | |
19502 | return 0; | |
19503 | ||
19504 | for (p = mips_cpu_info_table; p->name != 0; p++) | |
19505 | if (mips_matching_cpu_name_p (p->name, cpu_string)) | |
19506 | return p; | |
19507 | ||
20203fb9 | 19508 | as_bad (_("Bad value (%s) for %s"), cpu_string, option); |
316f5878 | 19509 | return 0; |
e7af610e NC |
19510 | } |
19511 | ||
316f5878 RS |
19512 | /* Return the canonical processor information for ISA (a member of the |
19513 | ISA_MIPS* enumeration). */ | |
19514 | ||
e7af610e | 19515 | static const struct mips_cpu_info * |
17a2f251 | 19516 | mips_cpu_info_from_isa (int isa) |
e7af610e NC |
19517 | { |
19518 | int i; | |
19519 | ||
19520 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
ad3fea08 | 19521 | if ((mips_cpu_info_table[i].flags & MIPS_CPU_IS_ISA) |
316f5878 | 19522 | && isa == mips_cpu_info_table[i].isa) |
e7af610e NC |
19523 | return (&mips_cpu_info_table[i]); |
19524 | ||
e972090a | 19525 | return NULL; |
e7af610e | 19526 | } |
fef14a42 TS |
19527 | |
19528 | static const struct mips_cpu_info * | |
17a2f251 | 19529 | mips_cpu_info_from_arch (int arch) |
fef14a42 TS |
19530 | { |
19531 | int i; | |
19532 | ||
19533 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
19534 | if (arch == mips_cpu_info_table[i].cpu) | |
19535 | return (&mips_cpu_info_table[i]); | |
19536 | ||
19537 | return NULL; | |
19538 | } | |
316f5878 RS |
19539 | \f |
19540 | static void | |
17a2f251 | 19541 | show (FILE *stream, const char *string, int *col_p, int *first_p) |
316f5878 RS |
19542 | { |
19543 | if (*first_p) | |
19544 | { | |
19545 | fprintf (stream, "%24s", ""); | |
19546 | *col_p = 24; | |
19547 | } | |
19548 | else | |
19549 | { | |
19550 | fprintf (stream, ", "); | |
19551 | *col_p += 2; | |
19552 | } | |
e7af610e | 19553 | |
316f5878 RS |
19554 | if (*col_p + strlen (string) > 72) |
19555 | { | |
19556 | fprintf (stream, "\n%24s", ""); | |
19557 | *col_p = 24; | |
19558 | } | |
19559 | ||
19560 | fprintf (stream, "%s", string); | |
19561 | *col_p += strlen (string); | |
19562 | ||
19563 | *first_p = 0; | |
19564 | } | |
19565 | ||
19566 | void | |
17a2f251 | 19567 | md_show_usage (FILE *stream) |
e7af610e | 19568 | { |
316f5878 RS |
19569 | int column, first; |
19570 | size_t i; | |
19571 | ||
19572 | fprintf (stream, _("\ | |
19573 | MIPS options:\n\ | |
316f5878 RS |
19574 | -EB generate big endian output\n\ |
19575 | -EL generate little endian output\n\ | |
19576 | -g, -g2 do not remove unneeded NOPs or swap branches\n\ | |
19577 | -G NUM allow referencing objects up to NUM bytes\n\ | |
19578 | implicitly with the gp register [default 8]\n")); | |
19579 | fprintf (stream, _("\ | |
19580 | -mips1 generate MIPS ISA I instructions\n\ | |
19581 | -mips2 generate MIPS ISA II instructions\n\ | |
19582 | -mips3 generate MIPS ISA III instructions\n\ | |
19583 | -mips4 generate MIPS ISA IV instructions\n\ | |
19584 | -mips5 generate MIPS ISA V instructions\n\ | |
19585 | -mips32 generate MIPS32 ISA instructions\n\ | |
af7ee8bf | 19586 | -mips32r2 generate MIPS32 release 2 ISA instructions\n\ |
316f5878 | 19587 | -mips64 generate MIPS64 ISA instructions\n\ |
5f74bc13 | 19588 | -mips64r2 generate MIPS64 release 2 ISA instructions\n\ |
316f5878 RS |
19589 | -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n")); |
19590 | ||
19591 | first = 1; | |
e7af610e NC |
19592 | |
19593 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
316f5878 RS |
19594 | show (stream, mips_cpu_info_table[i].name, &column, &first); |
19595 | show (stream, "from-abi", &column, &first); | |
19596 | fputc ('\n', stream); | |
e7af610e | 19597 | |
316f5878 RS |
19598 | fprintf (stream, _("\ |
19599 | -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\ | |
19600 | -no-mCPU don't generate code specific to CPU.\n\ | |
19601 | For -mCPU and -no-mCPU, CPU must be one of:\n")); | |
19602 | ||
19603 | first = 1; | |
19604 | ||
19605 | show (stream, "3900", &column, &first); | |
19606 | show (stream, "4010", &column, &first); | |
19607 | show (stream, "4100", &column, &first); | |
19608 | show (stream, "4650", &column, &first); | |
19609 | fputc ('\n', stream); | |
19610 | ||
19611 | fprintf (stream, _("\ | |
19612 | -mips16 generate mips16 instructions\n\ | |
19613 | -no-mips16 do not generate mips16 instructions\n")); | |
19614 | fprintf (stream, _("\ | |
df58fc94 RS |
19615 | -mmicromips generate microMIPS instructions\n\ |
19616 | -mno-micromips do not generate microMIPS instructions\n")); | |
19617 | fprintf (stream, _("\ | |
e16bfa71 TS |
19618 | -msmartmips generate smartmips instructions\n\ |
19619 | -mno-smartmips do not generate smartmips instructions\n")); | |
19620 | fprintf (stream, _("\ | |
74cd071d CF |
19621 | -mdsp generate DSP instructions\n\ |
19622 | -mno-dsp do not generate DSP instructions\n")); | |
19623 | fprintf (stream, _("\ | |
8b082fb1 TS |
19624 | -mdspr2 generate DSP R2 instructions\n\ |
19625 | -mno-dspr2 do not generate DSP R2 instructions\n")); | |
19626 | fprintf (stream, _("\ | |
ef2e4d86 CF |
19627 | -mmt generate MT instructions\n\ |
19628 | -mno-mt do not generate MT instructions\n")); | |
19629 | fprintf (stream, _("\ | |
dec0624d MR |
19630 | -mmcu generate MCU instructions\n\ |
19631 | -mno-mcu do not generate MCU instructions\n")); | |
19632 | fprintf (stream, _("\ | |
b015e599 AP |
19633 | -mvirt generate Virtualization instructions\n\ |
19634 | -mno-virt do not generate Virtualization instructions\n")); | |
19635 | fprintf (stream, _("\ | |
c67a084a NC |
19636 | -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\ |
19637 | -mfix-loongson2f-nop work around Loongson2F NOP errata\n\ | |
d766e8ec | 19638 | -mfix-vr4120 work around certain VR4120 errata\n\ |
7d8e00cf | 19639 | -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\ |
6a32d874 | 19640 | -mfix-24k insert a nop after ERET and DERET instructions\n\ |
d954098f | 19641 | -mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\ |
316f5878 RS |
19642 | -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\ |
19643 | -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\ | |
aed1a261 | 19644 | -msym32 assume all symbols have 32-bit values\n\ |
316f5878 RS |
19645 | -O0 remove unneeded NOPs, do not swap branches\n\ |
19646 | -O remove unneeded NOPs and swap branches\n\ | |
316f5878 RS |
19647 | --trap, --no-break trap exception on div by 0 and mult overflow\n\ |
19648 | --break, --no-trap break exception on div by 0 and mult overflow\n")); | |
037b32b9 AN |
19649 | fprintf (stream, _("\ |
19650 | -mhard-float allow floating-point instructions\n\ | |
19651 | -msoft-float do not allow floating-point instructions\n\ | |
19652 | -msingle-float only allow 32-bit floating-point operations\n\ | |
19653 | -mdouble-float allow 32-bit and 64-bit floating-point operations\n\ | |
3bf0dbfb MR |
19654 | --[no-]construct-floats [dis]allow floating point values to be constructed\n\ |
19655 | --[no-]relax-branch [dis]allow out-of-range branches to be relaxed\n" | |
037b32b9 | 19656 | )); |
316f5878 RS |
19657 | fprintf (stream, _("\ |
19658 | -KPIC, -call_shared generate SVR4 position independent code\n\ | |
861fb55a | 19659 | -call_nonpic generate non-PIC code that can operate with DSOs\n\ |
0c000745 | 19660 | -mvxworks-pic generate VxWorks position independent code\n\ |
861fb55a | 19661 | -non_shared do not generate code that can operate with DSOs\n\ |
316f5878 | 19662 | -xgot assume a 32 bit GOT\n\ |
dcd410fe | 19663 | -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\ |
bbe506e8 | 19664 | -mshared, -mno-shared disable/enable .cpload optimization for\n\ |
d821e36b | 19665 | position dependent (non shared) code\n\ |
316f5878 RS |
19666 | -mabi=ABI create ABI conformant object file for:\n")); |
19667 | ||
19668 | first = 1; | |
19669 | ||
19670 | show (stream, "32", &column, &first); | |
19671 | show (stream, "o64", &column, &first); | |
19672 | show (stream, "n32", &column, &first); | |
19673 | show (stream, "64", &column, &first); | |
19674 | show (stream, "eabi", &column, &first); | |
19675 | ||
19676 | fputc ('\n', stream); | |
19677 | ||
19678 | fprintf (stream, _("\ | |
19679 | -32 create o32 ABI object file (default)\n\ | |
19680 | -n32 create n32 ABI object file\n\ | |
19681 | -64 create 64 ABI object file\n")); | |
e7af610e | 19682 | } |
14e777e0 | 19683 | |
1575952e | 19684 | #ifdef TE_IRIX |
14e777e0 | 19685 | enum dwarf2_format |
413a266c | 19686 | mips_dwarf2_format (asection *sec ATTRIBUTE_UNUSED) |
14e777e0 | 19687 | { |
369943fe | 19688 | if (HAVE_64BIT_SYMBOLS) |
1575952e | 19689 | return dwarf2_format_64bit_irix; |
14e777e0 KB |
19690 | else |
19691 | return dwarf2_format_32bit; | |
19692 | } | |
1575952e | 19693 | #endif |
73369e65 EC |
19694 | |
19695 | int | |
19696 | mips_dwarf2_addr_size (void) | |
19697 | { | |
6b6b3450 | 19698 | if (HAVE_64BIT_OBJECTS) |
73369e65 | 19699 | return 8; |
73369e65 EC |
19700 | else |
19701 | return 4; | |
19702 | } | |
5862107c EC |
19703 | |
19704 | /* Standard calling conventions leave the CFA at SP on entry. */ | |
19705 | void | |
19706 | mips_cfi_frame_initial_instructions (void) | |
19707 | { | |
19708 | cfi_add_CFA_def_cfa_register (SP); | |
19709 | } | |
19710 | ||
707bfff6 TS |
19711 | int |
19712 | tc_mips_regname_to_dw2regnum (char *regname) | |
19713 | { | |
19714 | unsigned int regnum = -1; | |
19715 | unsigned int reg; | |
19716 | ||
19717 | if (reg_lookup (®name, RTYPE_GP | RTYPE_NUM, ®)) | |
19718 | regnum = reg; | |
19719 | ||
19720 | return regnum; | |
19721 | } |