Commit | Line | Data |
---|---|---|
252b5132 | 1 | /* tc-mips.c -- assemble code for a MIPS chip. |
071742cf | 2 | Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 |
82efde3a | 3 | Free Software Foundation, Inc. |
252b5132 RH |
4 | Contributed by the OSF and Ralph Campbell. |
5 | Written by Keith Knowles and Ralph Campbell, working independently. | |
6 | Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus | |
7 | Support. | |
8 | ||
9 | This file is part of GAS. | |
10 | ||
11 | GAS is free software; you can redistribute it and/or modify | |
12 | it under the terms of the GNU General Public License as published by | |
13 | the Free Software Foundation; either version 2, or (at your option) | |
14 | any later version. | |
15 | ||
16 | GAS is distributed in the hope that it will be useful, | |
17 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | GNU General Public License for more details. | |
20 | ||
21 | You should have received a copy of the GNU General Public License | |
22 | along with GAS; see the file COPYING. If not, write to the Free | |
23 | Software Foundation, 59 Temple Place - Suite 330, Boston, MA | |
24 | 02111-1307, USA. */ | |
25 | ||
26 | #include "as.h" | |
27 | #include "config.h" | |
28 | #include "subsegs.h" | |
3882b010 | 29 | #include "safe-ctype.h" |
252b5132 RH |
30 | |
31 | #ifdef USE_STDARG | |
32 | #include <stdarg.h> | |
33 | #endif | |
34 | #ifdef USE_VARARGS | |
35 | #include <varargs.h> | |
36 | #endif | |
37 | ||
38 | #include "opcode/mips.h" | |
39 | #include "itbl-ops.h" | |
c5dd6aab | 40 | #include "dwarf2dbg.h" |
252b5132 RH |
41 | |
42 | #ifdef DEBUG | |
43 | #define DBG(x) printf x | |
44 | #else | |
45 | #define DBG(x) | |
46 | #endif | |
47 | ||
48 | #ifdef OBJ_MAYBE_ELF | |
49 | /* Clean up namespace so we can include obj-elf.h too. */ | |
50 | static int mips_output_flavor PARAMS ((void)); | |
51 | static int mips_output_flavor () { return OUTPUT_FLAVOR; } | |
52 | #undef OBJ_PROCESS_STAB | |
53 | #undef OUTPUT_FLAVOR | |
54 | #undef S_GET_ALIGN | |
55 | #undef S_GET_SIZE | |
56 | #undef S_SET_ALIGN | |
57 | #undef S_SET_SIZE | |
252b5132 RH |
58 | #undef obj_frob_file |
59 | #undef obj_frob_file_after_relocs | |
60 | #undef obj_frob_symbol | |
61 | #undef obj_pop_insert | |
62 | #undef obj_sec_sym_ok_for_reloc | |
63 | #undef OBJ_COPY_SYMBOL_ATTRIBUTES | |
64 | ||
65 | #include "obj-elf.h" | |
66 | /* Fix any of them that we actually care about. */ | |
67 | #undef OUTPUT_FLAVOR | |
68 | #define OUTPUT_FLAVOR mips_output_flavor() | |
69 | #endif | |
70 | ||
71 | #if defined (OBJ_ELF) | |
72 | #include "elf/mips.h" | |
73 | #endif | |
74 | ||
75 | #ifndef ECOFF_DEBUGGING | |
76 | #define NO_ECOFF_DEBUGGING | |
77 | #define ECOFF_DEBUGGING 0 | |
78 | #endif | |
79 | ||
ecb4347a DJ |
80 | int mips_flag_mdebug = -1; |
81 | ||
252b5132 RH |
82 | #include "ecoff.h" |
83 | ||
84 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
85 | static char *mips_regmask_frag; | |
86 | #endif | |
87 | ||
85b51719 | 88 | #define ZERO 0 |
252b5132 RH |
89 | #define AT 1 |
90 | #define TREG 24 | |
91 | #define PIC_CALL_REG 25 | |
92 | #define KT0 26 | |
93 | #define KT1 27 | |
94 | #define GP 28 | |
95 | #define SP 29 | |
96 | #define FP 30 | |
97 | #define RA 31 | |
98 | ||
99 | #define ILLEGAL_REG (32) | |
100 | ||
101 | /* Allow override of standard little-endian ECOFF format. */ | |
102 | ||
103 | #ifndef ECOFF_LITTLE_FORMAT | |
104 | #define ECOFF_LITTLE_FORMAT "ecoff-littlemips" | |
105 | #endif | |
106 | ||
107 | extern int target_big_endian; | |
108 | ||
252b5132 RH |
109 | /* The name of the readonly data section. */ |
110 | #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \ | |
111 | ? ".data" \ | |
112 | : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \ | |
113 | ? ".rdata" \ | |
056350c6 NC |
114 | : OUTPUT_FLAVOR == bfd_target_coff_flavour \ |
115 | ? ".rdata" \ | |
252b5132 RH |
116 | : OUTPUT_FLAVOR == bfd_target_elf_flavour \ |
117 | ? ".rodata" \ | |
118 | : (abort (), "")) | |
119 | ||
a325df1d TS |
120 | /* The ABI to use. */ |
121 | enum mips_abi_level | |
122 | { | |
123 | NO_ABI = 0, | |
124 | O32_ABI, | |
125 | O64_ABI, | |
126 | N32_ABI, | |
127 | N64_ABI, | |
128 | EABI_ABI | |
129 | }; | |
130 | ||
131 | /* MIPS ABI we are using for this output file. */ | |
316f5878 | 132 | static enum mips_abi_level mips_abi = NO_ABI; |
a325df1d | 133 | |
252b5132 RH |
134 | /* This is the set of options which may be modified by the .set |
135 | pseudo-op. We use a struct so that .set push and .set pop are more | |
136 | reliable. */ | |
137 | ||
e972090a NC |
138 | struct mips_set_options |
139 | { | |
252b5132 RH |
140 | /* MIPS ISA (Instruction Set Architecture) level. This is set to -1 |
141 | if it has not been initialized. Changed by `.set mipsN', and the | |
142 | -mipsN command line option, and the default CPU. */ | |
143 | int isa; | |
1f25f5d3 CD |
144 | /* Enabled Application Specific Extensions (ASEs). These are set to -1 |
145 | if they have not been initialized. Changed by `.set <asename>', by | |
146 | command line options, and based on the default architecture. */ | |
147 | int ase_mips3d; | |
deec1734 | 148 | int ase_mdmx; |
252b5132 RH |
149 | /* Whether we are assembling for the mips16 processor. 0 if we are |
150 | not, 1 if we are, and -1 if the value has not been initialized. | |
151 | Changed by `.set mips16' and `.set nomips16', and the -mips16 and | |
152 | -nomips16 command line options, and the default CPU. */ | |
153 | int mips16; | |
154 | /* Non-zero if we should not reorder instructions. Changed by `.set | |
155 | reorder' and `.set noreorder'. */ | |
156 | int noreorder; | |
157 | /* Non-zero if we should not permit the $at ($1) register to be used | |
158 | in instructions. Changed by `.set at' and `.set noat'. */ | |
159 | int noat; | |
160 | /* Non-zero if we should warn when a macro instruction expands into | |
161 | more than one machine instruction. Changed by `.set nomacro' and | |
162 | `.set macro'. */ | |
163 | int warn_about_macros; | |
164 | /* Non-zero if we should not move instructions. Changed by `.set | |
165 | move', `.set volatile', `.set nomove', and `.set novolatile'. */ | |
166 | int nomove; | |
167 | /* Non-zero if we should not optimize branches by moving the target | |
168 | of the branch into the delay slot. Actually, we don't perform | |
169 | this optimization anyhow. Changed by `.set bopt' and `.set | |
170 | nobopt'. */ | |
171 | int nobopt; | |
172 | /* Non-zero if we should not autoextend mips16 instructions. | |
173 | Changed by `.set autoextend' and `.set noautoextend'. */ | |
174 | int noautoextend; | |
a325df1d TS |
175 | /* Restrict general purpose registers and floating point registers |
176 | to 32 bit. This is initially determined when -mgp32 or -mfp32 | |
177 | is passed but can changed if the assembler code uses .set mipsN. */ | |
178 | int gp32; | |
179 | int fp32; | |
252b5132 RH |
180 | }; |
181 | ||
a325df1d | 182 | /* True if -mgp32 was passed. */ |
a8e8e863 | 183 | static int file_mips_gp32 = -1; |
a325df1d TS |
184 | |
185 | /* True if -mfp32 was passed. */ | |
a8e8e863 | 186 | static int file_mips_fp32 = -1; |
a325df1d | 187 | |
252b5132 | 188 | /* This is the struct we use to hold the current set of options. Note |
a4672219 | 189 | that we must set the isa field to ISA_UNKNOWN and the ASE fields to |
e7af610e | 190 | -1 to indicate that they have not been initialized. */ |
252b5132 | 191 | |
e972090a NC |
192 | static struct mips_set_options mips_opts = |
193 | { | |
316f5878 | 194 | ISA_UNKNOWN, -1, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0 |
e7af610e | 195 | }; |
252b5132 RH |
196 | |
197 | /* These variables are filled in with the masks of registers used. | |
198 | The object format code reads them and puts them in the appropriate | |
199 | place. */ | |
200 | unsigned long mips_gprmask; | |
201 | unsigned long mips_cprmask[4]; | |
202 | ||
203 | /* MIPS ISA we are using for this output file. */ | |
e7af610e | 204 | static int file_mips_isa = ISA_UNKNOWN; |
252b5132 | 205 | |
a4672219 TS |
206 | /* True if -mips16 was passed or implied by arguments passed on the |
207 | command line (e.g., by -march). */ | |
208 | static int file_ase_mips16; | |
209 | ||
1f25f5d3 CD |
210 | /* True if -mips3d was passed or implied by arguments passed on the |
211 | command line (e.g., by -march). */ | |
212 | static int file_ase_mips3d; | |
213 | ||
deec1734 CD |
214 | /* True if -mdmx was passed or implied by arguments passed on the |
215 | command line (e.g., by -march). */ | |
216 | static int file_ase_mdmx; | |
217 | ||
ec68c924 EC |
218 | /* The argument of the -march= flag. The architecture we are assembling. */ |
219 | static int mips_arch = CPU_UNKNOWN; | |
316f5878 RS |
220 | static const char *mips_arch_string; |
221 | static const struct mips_cpu_info *mips_arch_info; | |
ec68c924 EC |
222 | |
223 | /* The argument of the -mtune= flag. The architecture for which we | |
224 | are optimizing. */ | |
225 | static int mips_tune = CPU_UNKNOWN; | |
316f5878 RS |
226 | static const char *mips_tune_string; |
227 | static const struct mips_cpu_info *mips_tune_info; | |
ec68c924 | 228 | |
316f5878 | 229 | /* True when generating 32-bit code for a 64-bit processor. */ |
252b5132 RH |
230 | static int mips_32bitmode = 0; |
231 | ||
9ce8a5dd GRK |
232 | /* Some ISA's have delay slots for instructions which read or write |
233 | from a coprocessor (eg. mips1-mips3); some don't (eg mips4). | |
bdaaa2e1 | 234 | Return true if instructions marked INSN_LOAD_COPROC_DELAY, |
9ce8a5dd GRK |
235 | INSN_COPROC_MOVE_DELAY, or INSN_WRITE_COND_CODE actually have a |
236 | delay slot in this ISA. The uses of this macro assume that any | |
237 | ISA that has delay slots for one of these, has them for all. They | |
238 | also assume that ISAs which don't have delays for these insns, don't | |
bdaaa2e1 | 239 | have delays for the INSN_LOAD_MEMORY_DELAY instructions either. */ |
9ce8a5dd | 240 | #define ISA_HAS_COPROC_DELAYS(ISA) ( \ |
e7af610e NC |
241 | (ISA) == ISA_MIPS1 \ |
242 | || (ISA) == ISA_MIPS2 \ | |
243 | || (ISA) == ISA_MIPS3 \ | |
9ce8a5dd GRK |
244 | ) |
245 | ||
316f5878 RS |
246 | /* True if the given ABI requires 32-bit registers. */ |
247 | #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI) | |
248 | ||
249 | /* Likewise 64-bit registers. */ | |
250 | #define ABI_NEEDS_64BIT_REGS(ABI) \ | |
251 | ((ABI) == N32_ABI \ | |
252 | || (ABI) == N64_ABI \ | |
253 | || (ABI) == O64_ABI) | |
254 | ||
bdaaa2e1 | 255 | /* Return true if ISA supports 64 bit gp register instructions. */ |
9ce8a5dd | 256 | #define ISA_HAS_64BIT_REGS(ISA) ( \ |
e7af610e NC |
257 | (ISA) == ISA_MIPS3 \ |
258 | || (ISA) == ISA_MIPS4 \ | |
84ea6cf2 | 259 | || (ISA) == ISA_MIPS5 \ |
d1cf510e | 260 | || (ISA) == ISA_MIPS64 \ |
9ce8a5dd GRK |
261 | ) |
262 | ||
af7ee8bf CD |
263 | /* Return true if ISA supports 64-bit right rotate (dror et al.) |
264 | instructions. */ | |
265 | #define ISA_HAS_DROR(ISA) ( \ | |
266 | 0 \ | |
267 | ) | |
268 | ||
269 | /* Return true if ISA supports 32-bit right rotate (ror et al.) | |
270 | instructions. */ | |
271 | #define ISA_HAS_ROR(ISA) ( \ | |
272 | (ISA) == ISA_MIPS32R2 \ | |
273 | ) | |
274 | ||
e013f690 | 275 | #define HAVE_32BIT_GPRS \ |
316f5878 | 276 | (mips_opts.gp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
ca4e0257 | 277 | |
e013f690 | 278 | #define HAVE_32BIT_FPRS \ |
316f5878 | 279 | (mips_opts.fp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
ca4e0257 RS |
280 | |
281 | #define HAVE_64BIT_GPRS (! HAVE_32BIT_GPRS) | |
282 | #define HAVE_64BIT_FPRS (! HAVE_32BIT_FPRS) | |
283 | ||
316f5878 | 284 | #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI) |
e013f690 | 285 | |
316f5878 | 286 | #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI) |
e013f690 TS |
287 | |
288 | /* We can only have 64bit addresses if the object file format | |
289 | supports it. */ | |
afdbd6d0 CD |
290 | #define HAVE_32BIT_ADDRESSES \ |
291 | (HAVE_32BIT_GPRS \ | |
292 | || ((bfd_arch_bits_per_address (stdoutput) == 32 \ | |
293 | || ! HAVE_64BIT_OBJECTS) \ | |
294 | && mips_pic != EMBEDDED_PIC)) | |
e013f690 TS |
295 | |
296 | #define HAVE_64BIT_ADDRESSES (! HAVE_32BIT_ADDRESSES) | |
ca4e0257 | 297 | |
a4672219 | 298 | /* Return true if the given CPU supports the MIPS16 ASE. */ |
3396de36 TS |
299 | #define CPU_HAS_MIPS16(cpu) \ |
300 | (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \ | |
301 | || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0) | |
a4672219 | 302 | |
1f25f5d3 CD |
303 | /* Return true if the given CPU supports the MIPS3D ASE. */ |
304 | #define CPU_HAS_MIPS3D(cpu) ((cpu) == CPU_SB1 \ | |
305 | ) | |
306 | ||
deec1734 | 307 | /* Return true if the given CPU supports the MDMX ASE. */ |
b34976b6 | 308 | #define CPU_HAS_MDMX(cpu) (FALSE \ |
deec1734 CD |
309 | ) |
310 | ||
60b63b72 RS |
311 | /* True if CPU has a dror instruction. */ |
312 | #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500) | |
313 | ||
314 | /* True if CPU has a ror instruction. */ | |
315 | #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU) | |
316 | ||
bdaaa2e1 | 317 | /* Whether the processor uses hardware interlocks to protect |
252b5132 | 318 | reads from the HI and LO registers, and thus does not |
ec68c924 | 319 | require nops to be inserted. */ |
252b5132 | 320 | |
ec68c924 | 321 | #define hilo_interlocks (mips_arch == CPU_R4010 \ |
60b63b72 | 322 | || mips_arch == CPU_VR5500 \ |
0a758a12 | 323 | || mips_arch == CPU_SB1 \ |
252b5132 RH |
324 | ) |
325 | ||
326 | /* Whether the processor uses hardware interlocks to protect reads | |
327 | from the GPRs, and thus does not require nops to be inserted. */ | |
328 | #define gpr_interlocks \ | |
e7af610e | 329 | (mips_opts.isa != ISA_MIPS1 \ |
60b63b72 RS |
330 | || mips_arch == CPU_VR5400 \ |
331 | || mips_arch == CPU_VR5500 \ | |
ec68c924 | 332 | || mips_arch == CPU_R3900) |
252b5132 RH |
333 | |
334 | /* As with other "interlocks" this is used by hardware that has FP | |
335 | (co-processor) interlocks. */ | |
bdaaa2e1 | 336 | /* Itbl support may require additional care here. */ |
ec68c924 | 337 | #define cop_interlocks (mips_arch == CPU_R4300 \ |
60b63b72 RS |
338 | || mips_arch == CPU_VR5400 \ |
339 | || mips_arch == CPU_VR5500 \ | |
0a758a12 | 340 | || mips_arch == CPU_SB1 \ |
252b5132 RH |
341 | ) |
342 | ||
6b76fefe CM |
343 | /* Is this a mfhi or mflo instruction? */ |
344 | #define MF_HILO_INSN(PINFO) \ | |
345 | ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO)) | |
346 | ||
252b5132 RH |
347 | /* MIPS PIC level. */ |
348 | ||
a161fe53 | 349 | enum mips_pic_level mips_pic; |
252b5132 | 350 | |
39c0a331 L |
351 | /* Warn about all NOPS that the assembler generates. */ |
352 | static int warn_nops = 0; | |
353 | ||
c9914766 | 354 | /* 1 if we should generate 32 bit offsets from the $gp register in |
252b5132 | 355 | SVR4_PIC mode. Currently has no meaning in other modes. */ |
c9914766 | 356 | static int mips_big_got = 0; |
252b5132 RH |
357 | |
358 | /* 1 if trap instructions should used for overflow rather than break | |
359 | instructions. */ | |
c9914766 | 360 | static int mips_trap = 0; |
252b5132 | 361 | |
119d663a | 362 | /* 1 if double width floating point constants should not be constructed |
b6ff326e | 363 | by assembling two single width halves into two single width floating |
119d663a NC |
364 | point registers which just happen to alias the double width destination |
365 | register. On some architectures this aliasing can be disabled by a bit | |
d547a75e | 366 | in the status register, and the setting of this bit cannot be determined |
119d663a NC |
367 | automatically at assemble time. */ |
368 | static int mips_disable_float_construction; | |
369 | ||
252b5132 RH |
370 | /* Non-zero if any .set noreorder directives were used. */ |
371 | ||
372 | static int mips_any_noreorder; | |
373 | ||
6b76fefe CM |
374 | /* Non-zero if nops should be inserted when the register referenced in |
375 | an mfhi/mflo instruction is read in the next two instructions. */ | |
376 | static int mips_7000_hilo_fix; | |
377 | ||
252b5132 | 378 | /* The size of the small data section. */ |
156c2f8b | 379 | static unsigned int g_switch_value = 8; |
252b5132 RH |
380 | /* Whether the -G option was used. */ |
381 | static int g_switch_seen = 0; | |
382 | ||
383 | #define N_RMASK 0xc4 | |
384 | #define N_VFP 0xd4 | |
385 | ||
386 | /* If we can determine in advance that GP optimization won't be | |
387 | possible, we can skip the relaxation stuff that tries to produce | |
388 | GP-relative references. This makes delay slot optimization work | |
389 | better. | |
390 | ||
391 | This function can only provide a guess, but it seems to work for | |
fba2b7f9 GK |
392 | gcc output. It needs to guess right for gcc, otherwise gcc |
393 | will put what it thinks is a GP-relative instruction in a branch | |
394 | delay slot. | |
252b5132 RH |
395 | |
396 | I don't know if a fix is needed for the SVR4_PIC mode. I've only | |
397 | fixed it for the non-PIC mode. KR 95/04/07 */ | |
398 | static int nopic_need_relax PARAMS ((symbolS *, int)); | |
399 | ||
400 | /* handle of the OPCODE hash table */ | |
401 | static struct hash_control *op_hash = NULL; | |
402 | ||
403 | /* The opcode hash table we use for the mips16. */ | |
404 | static struct hash_control *mips16_op_hash = NULL; | |
405 | ||
406 | /* This array holds the chars that always start a comment. If the | |
407 | pre-processor is disabled, these aren't very useful */ | |
408 | const char comment_chars[] = "#"; | |
409 | ||
410 | /* This array holds the chars that only start a comment at the beginning of | |
411 | a line. If the line seems to have the form '# 123 filename' | |
412 | .line and .file directives will appear in the pre-processed output */ | |
413 | /* Note that input_file.c hand checks for '#' at the beginning of the | |
414 | first line of the input file. This is because the compiler outputs | |
bdaaa2e1 | 415 | #NO_APP at the beginning of its output. */ |
252b5132 RH |
416 | /* Also note that C style comments are always supported. */ |
417 | const char line_comment_chars[] = "#"; | |
418 | ||
bdaaa2e1 | 419 | /* This array holds machine specific line separator characters. */ |
63a0b638 | 420 | const char line_separator_chars[] = ";"; |
252b5132 RH |
421 | |
422 | /* Chars that can be used to separate mant from exp in floating point nums */ | |
423 | const char EXP_CHARS[] = "eE"; | |
424 | ||
425 | /* Chars that mean this number is a floating point constant */ | |
426 | /* As in 0f12.456 */ | |
427 | /* or 0d1.2345e12 */ | |
428 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; | |
429 | ||
430 | /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be | |
431 | changed in read.c . Ideally it shouldn't have to know about it at all, | |
432 | but nothing is ideal around here. | |
433 | */ | |
434 | ||
435 | static char *insn_error; | |
436 | ||
437 | static int auto_align = 1; | |
438 | ||
439 | /* When outputting SVR4 PIC code, the assembler needs to know the | |
440 | offset in the stack frame from which to restore the $gp register. | |
441 | This is set by the .cprestore pseudo-op, and saved in this | |
442 | variable. */ | |
443 | static offsetT mips_cprestore_offset = -1; | |
444 | ||
6478892d TS |
445 | /* Similiar for NewABI PIC code, where $gp is callee-saved. NewABI has some |
446 | more optimizations, it can use a register value instead of a memory-saved | |
956cd1d6 | 447 | offset and even an other register than $gp as global pointer. */ |
6478892d TS |
448 | static offsetT mips_cpreturn_offset = -1; |
449 | static int mips_cpreturn_register = -1; | |
450 | static int mips_gp_register = GP; | |
def2e0dd | 451 | static int mips_gprel_offset = 0; |
6478892d | 452 | |
7a621144 DJ |
453 | /* Whether mips_cprestore_offset has been set in the current function |
454 | (or whether it has already been warned about, if not). */ | |
455 | static int mips_cprestore_valid = 0; | |
456 | ||
252b5132 RH |
457 | /* This is the register which holds the stack frame, as set by the |
458 | .frame pseudo-op. This is needed to implement .cprestore. */ | |
459 | static int mips_frame_reg = SP; | |
460 | ||
7a621144 DJ |
461 | /* Whether mips_frame_reg has been set in the current function |
462 | (or whether it has already been warned about, if not). */ | |
463 | static int mips_frame_reg_valid = 0; | |
464 | ||
252b5132 RH |
465 | /* To output NOP instructions correctly, we need to keep information |
466 | about the previous two instructions. */ | |
467 | ||
468 | /* Whether we are optimizing. The default value of 2 means to remove | |
469 | unneeded NOPs and swap branch instructions when possible. A value | |
470 | of 1 means to not swap branches. A value of 0 means to always | |
471 | insert NOPs. */ | |
472 | static int mips_optimize = 2; | |
473 | ||
474 | /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is | |
475 | equivalent to seeing no -g option at all. */ | |
476 | static int mips_debug = 0; | |
477 | ||
478 | /* The previous instruction. */ | |
479 | static struct mips_cl_insn prev_insn; | |
480 | ||
481 | /* The instruction before prev_insn. */ | |
482 | static struct mips_cl_insn prev_prev_insn; | |
483 | ||
484 | /* If we don't want information for prev_insn or prev_prev_insn, we | |
485 | point the insn_mo field at this dummy integer. */ | |
43841e91 | 486 | static const struct mips_opcode dummy_opcode = { NULL, NULL, 0, 0, 0, 0 }; |
252b5132 RH |
487 | |
488 | /* Non-zero if prev_insn is valid. */ | |
489 | static int prev_insn_valid; | |
490 | ||
491 | /* The frag for the previous instruction. */ | |
492 | static struct frag *prev_insn_frag; | |
493 | ||
494 | /* The offset into prev_insn_frag for the previous instruction. */ | |
495 | static long prev_insn_where; | |
496 | ||
497 | /* The reloc type for the previous instruction, if any. */ | |
f6688943 | 498 | static bfd_reloc_code_real_type prev_insn_reloc_type[3]; |
252b5132 RH |
499 | |
500 | /* The reloc for the previous instruction, if any. */ | |
f6688943 | 501 | static fixS *prev_insn_fixp[3]; |
252b5132 RH |
502 | |
503 | /* Non-zero if the previous instruction was in a delay slot. */ | |
504 | static int prev_insn_is_delay_slot; | |
505 | ||
506 | /* Non-zero if the previous instruction was in a .set noreorder. */ | |
507 | static int prev_insn_unreordered; | |
508 | ||
509 | /* Non-zero if the previous instruction uses an extend opcode (if | |
510 | mips16). */ | |
511 | static int prev_insn_extended; | |
512 | ||
513 | /* Non-zero if the previous previous instruction was in a .set | |
514 | noreorder. */ | |
515 | static int prev_prev_insn_unreordered; | |
516 | ||
517 | /* If this is set, it points to a frag holding nop instructions which | |
518 | were inserted before the start of a noreorder section. If those | |
519 | nops turn out to be unnecessary, the size of the frag can be | |
520 | decreased. */ | |
521 | static fragS *prev_nop_frag; | |
522 | ||
523 | /* The number of nop instructions we created in prev_nop_frag. */ | |
524 | static int prev_nop_frag_holds; | |
525 | ||
526 | /* The number of nop instructions that we know we need in | |
bdaaa2e1 | 527 | prev_nop_frag. */ |
252b5132 RH |
528 | static int prev_nop_frag_required; |
529 | ||
530 | /* The number of instructions we've seen since prev_nop_frag. */ | |
531 | static int prev_nop_frag_since; | |
532 | ||
533 | /* For ECOFF and ELF, relocations against symbols are done in two | |
534 | parts, with a HI relocation and a LO relocation. Each relocation | |
535 | has only 16 bits of space to store an addend. This means that in | |
536 | order for the linker to handle carries correctly, it must be able | |
537 | to locate both the HI and the LO relocation. This means that the | |
538 | relocations must appear in order in the relocation table. | |
539 | ||
540 | In order to implement this, we keep track of each unmatched HI | |
541 | relocation. We then sort them so that they immediately precede the | |
bdaaa2e1 | 542 | corresponding LO relocation. */ |
252b5132 | 543 | |
e972090a NC |
544 | struct mips_hi_fixup |
545 | { | |
252b5132 RH |
546 | /* Next HI fixup. */ |
547 | struct mips_hi_fixup *next; | |
548 | /* This fixup. */ | |
549 | fixS *fixp; | |
550 | /* The section this fixup is in. */ | |
551 | segT seg; | |
552 | }; | |
553 | ||
554 | /* The list of unmatched HI relocs. */ | |
555 | ||
556 | static struct mips_hi_fixup *mips_hi_fixup_list; | |
557 | ||
64bdfcaf RS |
558 | /* The frag containing the last explicit relocation operator. |
559 | Null if explicit relocations have not been used. */ | |
560 | ||
561 | static fragS *prev_reloc_op_frag; | |
562 | ||
252b5132 RH |
563 | /* Map normal MIPS register numbers to mips16 register numbers. */ |
564 | ||
565 | #define X ILLEGAL_REG | |
e972090a NC |
566 | static const int mips32_to_16_reg_map[] = |
567 | { | |
252b5132 RH |
568 | X, X, 2, 3, 4, 5, 6, 7, |
569 | X, X, X, X, X, X, X, X, | |
570 | 0, 1, X, X, X, X, X, X, | |
571 | X, X, X, X, X, X, X, X | |
572 | }; | |
573 | #undef X | |
574 | ||
575 | /* Map mips16 register numbers to normal MIPS register numbers. */ | |
576 | ||
e972090a NC |
577 | static const unsigned int mips16_to_32_reg_map[] = |
578 | { | |
252b5132 RH |
579 | 16, 17, 2, 3, 4, 5, 6, 7 |
580 | }; | |
60b63b72 RS |
581 | |
582 | static int mips_fix_4122_bugs; | |
4a6a3df4 AO |
583 | |
584 | /* We don't relax branches by default, since this causes us to expand | |
585 | `la .l2 - .l1' if there's a branch between .l1 and .l2, because we | |
586 | fail to compute the offset before expanding the macro to the most | |
587 | efficient expansion. */ | |
588 | ||
589 | static int mips_relax_branch; | |
252b5132 RH |
590 | \f |
591 | /* Since the MIPS does not have multiple forms of PC relative | |
592 | instructions, we do not have to do relaxing as is done on other | |
593 | platforms. However, we do have to handle GP relative addressing | |
594 | correctly, which turns out to be a similar problem. | |
595 | ||
596 | Every macro that refers to a symbol can occur in (at least) two | |
597 | forms, one with GP relative addressing and one without. For | |
598 | example, loading a global variable into a register generally uses | |
599 | a macro instruction like this: | |
600 | lw $4,i | |
601 | If i can be addressed off the GP register (this is true if it is in | |
602 | the .sbss or .sdata section, or if it is known to be smaller than | |
603 | the -G argument) this will generate the following instruction: | |
604 | lw $4,i($gp) | |
605 | This instruction will use a GPREL reloc. If i can not be addressed | |
606 | off the GP register, the following instruction sequence will be used: | |
607 | lui $at,i | |
608 | lw $4,i($at) | |
609 | In this case the first instruction will have a HI16 reloc, and the | |
610 | second reloc will have a LO16 reloc. Both relocs will be against | |
611 | the symbol i. | |
612 | ||
613 | The issue here is that we may not know whether i is GP addressable | |
614 | until after we see the instruction that uses it. Therefore, we | |
615 | want to be able to choose the final instruction sequence only at | |
616 | the end of the assembly. This is similar to the way other | |
617 | platforms choose the size of a PC relative instruction only at the | |
618 | end of assembly. | |
619 | ||
620 | When generating position independent code we do not use GP | |
621 | addressing in quite the same way, but the issue still arises as | |
622 | external symbols and local symbols must be handled differently. | |
623 | ||
624 | We handle these issues by actually generating both possible | |
625 | instruction sequences. The longer one is put in a frag_var with | |
626 | type rs_machine_dependent. We encode what to do with the frag in | |
627 | the subtype field. We encode (1) the number of existing bytes to | |
628 | replace, (2) the number of new bytes to use, (3) the offset from | |
629 | the start of the existing bytes to the first reloc we must generate | |
630 | (that is, the offset is applied from the start of the existing | |
631 | bytes after they are replaced by the new bytes, if any), (4) the | |
632 | offset from the start of the existing bytes to the second reloc, | |
633 | (5) whether a third reloc is needed (the third reloc is always four | |
634 | bytes after the second reloc), and (6) whether to warn if this | |
635 | variant is used (this is sometimes needed if .set nomacro or .set | |
636 | noat is in effect). All these numbers are reasonably small. | |
637 | ||
638 | Generating two instruction sequences must be handled carefully to | |
639 | ensure that delay slots are handled correctly. Fortunately, there | |
640 | are a limited number of cases. When the second instruction | |
641 | sequence is generated, append_insn is directed to maintain the | |
642 | existing delay slot information, so it continues to apply to any | |
643 | code after the second instruction sequence. This means that the | |
644 | second instruction sequence must not impose any requirements not | |
645 | required by the first instruction sequence. | |
646 | ||
647 | These variant frags are then handled in functions called by the | |
648 | machine independent code. md_estimate_size_before_relax returns | |
649 | the final size of the frag. md_convert_frag sets up the final form | |
650 | of the frag. tc_gen_reloc adjust the first reloc and adds a second | |
651 | one if needed. */ | |
652 | #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \ | |
653 | ((relax_substateT) \ | |
654 | (((old) << 23) \ | |
655 | | ((new) << 16) \ | |
656 | | (((reloc1) + 64) << 9) \ | |
657 | | (((reloc2) + 64) << 2) \ | |
658 | | ((reloc3) ? (1 << 1) : 0) \ | |
659 | | ((warn) ? 1 : 0))) | |
660 | #define RELAX_OLD(i) (((i) >> 23) & 0x7f) | |
661 | #define RELAX_NEW(i) (((i) >> 16) & 0x7f) | |
9a41af64 TS |
662 | #define RELAX_RELOC1(i) ((valueT) (((i) >> 9) & 0x7f) - 64) |
663 | #define RELAX_RELOC2(i) ((valueT) (((i) >> 2) & 0x7f) - 64) | |
252b5132 RH |
664 | #define RELAX_RELOC3(i) (((i) >> 1) & 1) |
665 | #define RELAX_WARN(i) ((i) & 1) | |
666 | ||
4a6a3df4 AO |
667 | /* Branch without likely bit. If label is out of range, we turn: |
668 | ||
669 | beq reg1, reg2, label | |
670 | delay slot | |
671 | ||
672 | into | |
673 | ||
674 | bne reg1, reg2, 0f | |
675 | nop | |
676 | j label | |
677 | 0: delay slot | |
678 | ||
679 | with the following opcode replacements: | |
680 | ||
681 | beq <-> bne | |
682 | blez <-> bgtz | |
683 | bltz <-> bgez | |
684 | bc1f <-> bc1t | |
685 | ||
686 | bltzal <-> bgezal (with jal label instead of j label) | |
687 | ||
688 | Even though keeping the delay slot instruction in the delay slot of | |
689 | the branch would be more efficient, it would be very tricky to do | |
690 | correctly, because we'd have to introduce a variable frag *after* | |
691 | the delay slot instruction, and expand that instead. Let's do it | |
692 | the easy way for now, even if the branch-not-taken case now costs | |
693 | one additional instruction. Out-of-range branches are not supposed | |
694 | to be common, anyway. | |
695 | ||
696 | Branch likely. If label is out of range, we turn: | |
697 | ||
698 | beql reg1, reg2, label | |
699 | delay slot (annulled if branch not taken) | |
700 | ||
701 | into | |
702 | ||
703 | beql reg1, reg2, 1f | |
704 | nop | |
705 | beql $0, $0, 2f | |
706 | nop | |
707 | 1: j[al] label | |
708 | delay slot (executed only if branch taken) | |
709 | 2: | |
710 | ||
711 | It would be possible to generate a shorter sequence by losing the | |
712 | likely bit, generating something like: | |
b34976b6 | 713 | |
4a6a3df4 AO |
714 | bne reg1, reg2, 0f |
715 | nop | |
716 | j[al] label | |
717 | delay slot (executed only if branch taken) | |
718 | 0: | |
719 | ||
720 | beql -> bne | |
721 | bnel -> beq | |
722 | blezl -> bgtz | |
723 | bgtzl -> blez | |
724 | bltzl -> bgez | |
725 | bgezl -> bltz | |
726 | bc1fl -> bc1t | |
727 | bc1tl -> bc1f | |
728 | ||
729 | bltzall -> bgezal (with jal label instead of j label) | |
730 | bgezall -> bltzal (ditto) | |
731 | ||
732 | ||
733 | but it's not clear that it would actually improve performance. */ | |
af6ae2ad | 734 | #define RELAX_BRANCH_ENCODE(uncond, likely, link, toofar) \ |
4a6a3df4 AO |
735 | ((relax_substateT) \ |
736 | (0xc0000000 \ | |
737 | | ((toofar) ? 1 : 0) \ | |
738 | | ((link) ? 2 : 0) \ | |
739 | | ((likely) ? 4 : 0) \ | |
af6ae2ad | 740 | | ((uncond) ? 8 : 0))) |
4a6a3df4 | 741 | #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000) |
4a6a3df4 AO |
742 | #define RELAX_BRANCH_UNCOND(i) (((i) & 8) != 0) |
743 | #define RELAX_BRANCH_LIKELY(i) (((i) & 4) != 0) | |
744 | #define RELAX_BRANCH_LINK(i) (((i) & 2) != 0) | |
ae6063d4 | 745 | #define RELAX_BRANCH_TOOFAR(i) (((i) & 1) != 0) |
4a6a3df4 | 746 | |
252b5132 RH |
747 | /* For mips16 code, we use an entirely different form of relaxation. |
748 | mips16 supports two versions of most instructions which take | |
749 | immediate values: a small one which takes some small value, and a | |
750 | larger one which takes a 16 bit value. Since branches also follow | |
751 | this pattern, relaxing these values is required. | |
752 | ||
753 | We can assemble both mips16 and normal MIPS code in a single | |
754 | object. Therefore, we need to support this type of relaxation at | |
755 | the same time that we support the relaxation described above. We | |
756 | use the high bit of the subtype field to distinguish these cases. | |
757 | ||
758 | The information we store for this type of relaxation is the | |
759 | argument code found in the opcode file for this relocation, whether | |
760 | the user explicitly requested a small or extended form, and whether | |
761 | the relocation is in a jump or jal delay slot. That tells us the | |
762 | size of the value, and how it should be stored. We also store | |
763 | whether the fragment is considered to be extended or not. We also | |
764 | store whether this is known to be a branch to a different section, | |
765 | whether we have tried to relax this frag yet, and whether we have | |
766 | ever extended a PC relative fragment because of a shift count. */ | |
767 | #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \ | |
768 | (0x80000000 \ | |
769 | | ((type) & 0xff) \ | |
770 | | ((small) ? 0x100 : 0) \ | |
771 | | ((ext) ? 0x200 : 0) \ | |
772 | | ((dslot) ? 0x400 : 0) \ | |
773 | | ((jal_dslot) ? 0x800 : 0)) | |
4a6a3df4 | 774 | #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000) |
252b5132 RH |
775 | #define RELAX_MIPS16_TYPE(i) ((i) & 0xff) |
776 | #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0) | |
777 | #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0) | |
778 | #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0) | |
779 | #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0) | |
780 | #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0) | |
781 | #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000) | |
782 | #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000) | |
783 | #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0) | |
784 | #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000) | |
785 | #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000) | |
885add95 CD |
786 | |
787 | /* Is the given value a sign-extended 32-bit value? */ | |
788 | #define IS_SEXT_32BIT_NUM(x) \ | |
789 | (((x) &~ (offsetT) 0x7fffffff) == 0 \ | |
790 | || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff)) | |
791 | ||
792 | /* Is the given value a sign-extended 16-bit value? */ | |
793 | #define IS_SEXT_16BIT_NUM(x) \ | |
794 | (((x) &~ (offsetT) 0x7fff) == 0 \ | |
795 | || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff)) | |
796 | ||
252b5132 RH |
797 | \f |
798 | /* Prototypes for static functions. */ | |
799 | ||
800 | #ifdef __STDC__ | |
801 | #define internalError() \ | |
802 | as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__) | |
803 | #else | |
804 | #define internalError() as_fatal (_("MIPS internal Error")); | |
805 | #endif | |
806 | ||
807 | enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG }; | |
808 | ||
5919d012 RS |
809 | static inline bfd_boolean reloc_needs_lo_p |
810 | PARAMS ((bfd_reloc_code_real_type)); | |
811 | static inline bfd_boolean fixup_has_matching_lo_p | |
812 | PARAMS ((fixS *)); | |
b34976b6 AM |
813 | static int insn_uses_reg |
814 | PARAMS ((struct mips_cl_insn *ip, unsigned int reg, | |
815 | enum mips_regclass class)); | |
816 | static int reg_needs_delay | |
817 | PARAMS ((unsigned int)); | |
818 | static void mips16_mark_labels | |
819 | PARAMS ((void)); | |
820 | static void append_insn | |
821 | PARAMS ((char *place, struct mips_cl_insn * ip, expressionS * p, | |
5e0116d5 | 822 | bfd_reloc_code_real_type *r)); |
b34976b6 AM |
823 | static void mips_no_prev_insn |
824 | PARAMS ((int)); | |
825 | static void mips_emit_delays | |
826 | PARAMS ((bfd_boolean)); | |
252b5132 | 827 | #ifdef USE_STDARG |
b34976b6 AM |
828 | static void macro_build |
829 | PARAMS ((char *place, int *counter, expressionS * ep, const char *name, | |
830 | const char *fmt, ...)); | |
252b5132 RH |
831 | #else |
832 | static void macro_build (); | |
833 | #endif | |
b34976b6 AM |
834 | static void mips16_macro_build |
835 | PARAMS ((char *, int *, expressionS *, const char *, const char *, va_list)); | |
836 | static void macro_build_jalr | |
837 | PARAMS ((int, expressionS *)); | |
838 | static void macro_build_lui | |
839 | PARAMS ((char *place, int *counter, expressionS * ep, int regnum)); | |
840 | static void macro_build_ldst_constoffset | |
841 | PARAMS ((char *place, int *counter, expressionS * ep, const char *op, | |
842 | int valreg, int breg)); | |
843 | static void set_at | |
844 | PARAMS ((int *counter, int reg, int unsignedp)); | |
845 | static void check_absolute_expr | |
846 | PARAMS ((struct mips_cl_insn * ip, expressionS *)); | |
847 | static void load_register | |
848 | PARAMS ((int *, int, expressionS *, int)); | |
849 | static void load_address | |
850 | PARAMS ((int *, int, expressionS *, int *)); | |
851 | static void move_register | |
852 | PARAMS ((int *, int, int)); | |
853 | static void macro | |
854 | PARAMS ((struct mips_cl_insn * ip)); | |
855 | static void mips16_macro | |
856 | PARAMS ((struct mips_cl_insn * ip)); | |
252b5132 | 857 | #ifdef LOSING_COMPILER |
b34976b6 AM |
858 | static void macro2 |
859 | PARAMS ((struct mips_cl_insn * ip)); | |
252b5132 | 860 | #endif |
b34976b6 AM |
861 | static void mips_ip |
862 | PARAMS ((char *str, struct mips_cl_insn * ip)); | |
863 | static void mips16_ip | |
864 | PARAMS ((char *str, struct mips_cl_insn * ip)); | |
865 | static void mips16_immed | |
866 | PARAMS ((char *, unsigned int, int, offsetT, bfd_boolean, bfd_boolean, | |
867 | bfd_boolean, unsigned long *, bfd_boolean *, unsigned short *)); | |
5e0116d5 RS |
868 | static bfd_boolean parse_relocation |
869 | PARAMS ((char **, bfd_reloc_code_real_type *)); | |
870 | static size_t my_getSmallExpression | |
871 | PARAMS ((expressionS *, bfd_reloc_code_real_type *, char *)); | |
b34976b6 AM |
872 | static void my_getExpression |
873 | PARAMS ((expressionS *, char *)); | |
ae948b86 | 874 | #ifdef OBJ_ELF |
b34976b6 AM |
875 | static int support_64bit_objects |
876 | PARAMS((void)); | |
ae948b86 | 877 | #endif |
b34976b6 AM |
878 | static void mips_set_option_string |
879 | PARAMS ((const char **, const char *)); | |
880 | static symbolS *get_symbol | |
881 | PARAMS ((void)); | |
882 | static void mips_align | |
883 | PARAMS ((int to, int fill, symbolS *label)); | |
884 | static void s_align | |
885 | PARAMS ((int)); | |
886 | static void s_change_sec | |
887 | PARAMS ((int)); | |
888 | static void s_change_section | |
889 | PARAMS ((int)); | |
890 | static void s_cons | |
891 | PARAMS ((int)); | |
892 | static void s_float_cons | |
893 | PARAMS ((int)); | |
894 | static void s_mips_globl | |
895 | PARAMS ((int)); | |
896 | static void s_option | |
897 | PARAMS ((int)); | |
898 | static void s_mipsset | |
899 | PARAMS ((int)); | |
900 | static void s_abicalls | |
901 | PARAMS ((int)); | |
902 | static void s_cpload | |
903 | PARAMS ((int)); | |
904 | static void s_cpsetup | |
905 | PARAMS ((int)); | |
906 | static void s_cplocal | |
907 | PARAMS ((int)); | |
908 | static void s_cprestore | |
909 | PARAMS ((int)); | |
910 | static void s_cpreturn | |
911 | PARAMS ((int)); | |
912 | static void s_gpvalue | |
913 | PARAMS ((int)); | |
914 | static void s_gpword | |
915 | PARAMS ((int)); | |
916 | static void s_gpdword | |
917 | PARAMS ((int)); | |
918 | static void s_cpadd | |
919 | PARAMS ((int)); | |
920 | static void s_insn | |
921 | PARAMS ((int)); | |
922 | static void md_obj_begin | |
923 | PARAMS ((void)); | |
924 | static void md_obj_end | |
925 | PARAMS ((void)); | |
926 | static long get_number | |
927 | PARAMS ((void)); | |
928 | static void s_mips_ent | |
929 | PARAMS ((int)); | |
930 | static void s_mips_end | |
931 | PARAMS ((int)); | |
932 | static void s_mips_frame | |
933 | PARAMS ((int)); | |
934 | static void s_mips_mask | |
935 | PARAMS ((int)); | |
936 | static void s_mips_stab | |
937 | PARAMS ((int)); | |
938 | static void s_mips_weakext | |
939 | PARAMS ((int)); | |
940 | static void s_mips_file | |
941 | PARAMS ((int)); | |
942 | static void s_mips_loc | |
943 | PARAMS ((int)); | |
5919d012 RS |
944 | static bfd_boolean pic_need_relax |
945 | PARAMS ((symbolS *, asection *)); | |
b34976b6 AM |
946 | static int mips16_extended_frag |
947 | PARAMS ((fragS *, asection *, long)); | |
4a6a3df4 | 948 | static int relaxed_branch_length (fragS *, asection *, int); |
b34976b6 AM |
949 | static int validate_mips_insn |
950 | PARAMS ((const struct mips_opcode *)); | |
951 | static void show | |
952 | PARAMS ((FILE *, const char *, int *, int *)); | |
add55e1f | 953 | #ifdef OBJ_ELF |
b34976b6 AM |
954 | static int mips_need_elf_addend_fixup |
955 | PARAMS ((fixS *)); | |
add55e1f | 956 | #endif |
e7af610e NC |
957 | |
958 | /* Table and functions used to map between CPU/ISA names, and | |
959 | ISA levels, and CPU numbers. */ | |
960 | ||
e972090a NC |
961 | struct mips_cpu_info |
962 | { | |
e7af610e NC |
963 | const char *name; /* CPU or ISA name. */ |
964 | int is_isa; /* Is this an ISA? (If 0, a CPU.) */ | |
965 | int isa; /* ISA level. */ | |
966 | int cpu; /* CPU number (default CPU if ISA). */ | |
967 | }; | |
968 | ||
b34976b6 AM |
969 | static void mips_set_architecture |
970 | PARAMS ((const struct mips_cpu_info *)); | |
971 | static void mips_set_tune | |
972 | PARAMS ((const struct mips_cpu_info *)); | |
973 | static bfd_boolean mips_strict_matching_cpu_name_p | |
974 | PARAMS ((const char *, const char *)); | |
975 | static bfd_boolean mips_matching_cpu_name_p | |
976 | PARAMS ((const char *, const char *)); | |
977 | static const struct mips_cpu_info *mips_parse_cpu | |
978 | PARAMS ((const char *, const char *)); | |
979 | static const struct mips_cpu_info *mips_cpu_info_from_isa | |
980 | PARAMS ((int)); | |
252b5132 RH |
981 | \f |
982 | /* Pseudo-op table. | |
983 | ||
984 | The following pseudo-ops from the Kane and Heinrich MIPS book | |
985 | should be defined here, but are currently unsupported: .alias, | |
986 | .galive, .gjaldef, .gjrlive, .livereg, .noalias. | |
987 | ||
988 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
989 | specific to the type of debugging information being generated, and | |
990 | should be defined by the object format: .aent, .begin, .bend, | |
991 | .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp, | |
992 | .vreg. | |
993 | ||
994 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
995 | not MIPS CPU specific, but are also not specific to the object file | |
996 | format. This file is probably the best place to define them, but | |
997 | they are not currently supported: .asm0, .endr, .lab, .repeat, | |
998 | .struct. */ | |
999 | ||
e972090a NC |
1000 | static const pseudo_typeS mips_pseudo_table[] = |
1001 | { | |
beae10d5 | 1002 | /* MIPS specific pseudo-ops. */ |
252b5132 RH |
1003 | {"option", s_option, 0}, |
1004 | {"set", s_mipsset, 0}, | |
1005 | {"rdata", s_change_sec, 'r'}, | |
1006 | {"sdata", s_change_sec, 's'}, | |
1007 | {"livereg", s_ignore, 0}, | |
1008 | {"abicalls", s_abicalls, 0}, | |
1009 | {"cpload", s_cpload, 0}, | |
6478892d TS |
1010 | {"cpsetup", s_cpsetup, 0}, |
1011 | {"cplocal", s_cplocal, 0}, | |
252b5132 | 1012 | {"cprestore", s_cprestore, 0}, |
6478892d TS |
1013 | {"cpreturn", s_cpreturn, 0}, |
1014 | {"gpvalue", s_gpvalue, 0}, | |
252b5132 | 1015 | {"gpword", s_gpword, 0}, |
10181a0d | 1016 | {"gpdword", s_gpdword, 0}, |
252b5132 RH |
1017 | {"cpadd", s_cpadd, 0}, |
1018 | {"insn", s_insn, 0}, | |
1019 | ||
beae10d5 | 1020 | /* Relatively generic pseudo-ops that happen to be used on MIPS |
252b5132 RH |
1021 | chips. */ |
1022 | {"asciiz", stringer, 1}, | |
1023 | {"bss", s_change_sec, 'b'}, | |
1024 | {"err", s_err, 0}, | |
1025 | {"half", s_cons, 1}, | |
1026 | {"dword", s_cons, 3}, | |
1027 | {"weakext", s_mips_weakext, 0}, | |
1028 | ||
beae10d5 | 1029 | /* These pseudo-ops are defined in read.c, but must be overridden |
252b5132 RH |
1030 | here for one reason or another. */ |
1031 | {"align", s_align, 0}, | |
1032 | {"byte", s_cons, 0}, | |
1033 | {"data", s_change_sec, 'd'}, | |
1034 | {"double", s_float_cons, 'd'}, | |
1035 | {"float", s_float_cons, 'f'}, | |
1036 | {"globl", s_mips_globl, 0}, | |
1037 | {"global", s_mips_globl, 0}, | |
1038 | {"hword", s_cons, 1}, | |
1039 | {"int", s_cons, 2}, | |
1040 | {"long", s_cons, 2}, | |
1041 | {"octa", s_cons, 4}, | |
1042 | {"quad", s_cons, 3}, | |
cca86cc8 | 1043 | {"section", s_change_section, 0}, |
252b5132 RH |
1044 | {"short", s_cons, 1}, |
1045 | {"single", s_float_cons, 'f'}, | |
1046 | {"stabn", s_mips_stab, 'n'}, | |
1047 | {"text", s_change_sec, 't'}, | |
1048 | {"word", s_cons, 2}, | |
add56521 | 1049 | |
add56521 | 1050 | { "extern", ecoff_directive_extern, 0}, |
add56521 | 1051 | |
43841e91 | 1052 | { NULL, NULL, 0 }, |
252b5132 RH |
1053 | }; |
1054 | ||
e972090a NC |
1055 | static const pseudo_typeS mips_nonecoff_pseudo_table[] = |
1056 | { | |
beae10d5 KH |
1057 | /* These pseudo-ops should be defined by the object file format. |
1058 | However, a.out doesn't support them, so we have versions here. */ | |
252b5132 RH |
1059 | {"aent", s_mips_ent, 1}, |
1060 | {"bgnb", s_ignore, 0}, | |
1061 | {"end", s_mips_end, 0}, | |
1062 | {"endb", s_ignore, 0}, | |
1063 | {"ent", s_mips_ent, 0}, | |
c5dd6aab | 1064 | {"file", s_mips_file, 0}, |
252b5132 RH |
1065 | {"fmask", s_mips_mask, 'F'}, |
1066 | {"frame", s_mips_frame, 0}, | |
c5dd6aab | 1067 | {"loc", s_mips_loc, 0}, |
252b5132 RH |
1068 | {"mask", s_mips_mask, 'R'}, |
1069 | {"verstamp", s_ignore, 0}, | |
43841e91 | 1070 | { NULL, NULL, 0 }, |
252b5132 RH |
1071 | }; |
1072 | ||
1073 | extern void pop_insert PARAMS ((const pseudo_typeS *)); | |
1074 | ||
1075 | void | |
1076 | mips_pop_insert () | |
1077 | { | |
1078 | pop_insert (mips_pseudo_table); | |
1079 | if (! ECOFF_DEBUGGING) | |
1080 | pop_insert (mips_nonecoff_pseudo_table); | |
1081 | } | |
1082 | \f | |
1083 | /* Symbols labelling the current insn. */ | |
1084 | ||
e972090a NC |
1085 | struct insn_label_list |
1086 | { | |
252b5132 RH |
1087 | struct insn_label_list *next; |
1088 | symbolS *label; | |
1089 | }; | |
1090 | ||
1091 | static struct insn_label_list *insn_labels; | |
1092 | static struct insn_label_list *free_insn_labels; | |
1093 | ||
1094 | static void mips_clear_insn_labels PARAMS ((void)); | |
1095 | ||
1096 | static inline void | |
1097 | mips_clear_insn_labels () | |
1098 | { | |
1099 | register struct insn_label_list **pl; | |
1100 | ||
1101 | for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next) | |
1102 | ; | |
1103 | *pl = insn_labels; | |
1104 | insn_labels = NULL; | |
1105 | } | |
1106 | \f | |
1107 | static char *expr_end; | |
1108 | ||
1109 | /* Expressions which appear in instructions. These are set by | |
1110 | mips_ip. */ | |
1111 | ||
1112 | static expressionS imm_expr; | |
1113 | static expressionS offset_expr; | |
1114 | ||
1115 | /* Relocs associated with imm_expr and offset_expr. */ | |
1116 | ||
f6688943 TS |
1117 | static bfd_reloc_code_real_type imm_reloc[3] |
1118 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
1119 | static bfd_reloc_code_real_type offset_reloc[3] | |
1120 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 1121 | |
252b5132 RH |
1122 | /* These are set by mips16_ip if an explicit extension is used. */ |
1123 | ||
b34976b6 | 1124 | static bfd_boolean mips16_small, mips16_ext; |
252b5132 | 1125 | |
7ed4a06a | 1126 | #ifdef OBJ_ELF |
ecb4347a DJ |
1127 | /* The pdr segment for per procedure frame/regmask info. Not used for |
1128 | ECOFF debugging. */ | |
252b5132 RH |
1129 | |
1130 | static segT pdr_seg; | |
7ed4a06a | 1131 | #endif |
252b5132 | 1132 | |
e013f690 TS |
1133 | /* The default target format to use. */ |
1134 | ||
1135 | const char * | |
1136 | mips_target_format () | |
1137 | { | |
1138 | switch (OUTPUT_FLAVOR) | |
1139 | { | |
1140 | case bfd_target_aout_flavour: | |
1141 | return target_big_endian ? "a.out-mips-big" : "a.out-mips-little"; | |
1142 | case bfd_target_ecoff_flavour: | |
1143 | return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT; | |
1144 | case bfd_target_coff_flavour: | |
1145 | return "pe-mips"; | |
1146 | case bfd_target_elf_flavour: | |
1147 | #ifdef TE_TMIPS | |
cfe86eaa | 1148 | /* This is traditional mips. */ |
e013f690 | 1149 | return (target_big_endian |
cfe86eaa TS |
1150 | ? (HAVE_64BIT_OBJECTS |
1151 | ? "elf64-tradbigmips" | |
1152 | : (HAVE_NEWABI | |
1153 | ? "elf32-ntradbigmips" : "elf32-tradbigmips")) | |
1154 | : (HAVE_64BIT_OBJECTS | |
1155 | ? "elf64-tradlittlemips" | |
1156 | : (HAVE_NEWABI | |
1157 | ? "elf32-ntradlittlemips" : "elf32-tradlittlemips"))); | |
e013f690 TS |
1158 | #else |
1159 | return (target_big_endian | |
cfe86eaa TS |
1160 | ? (HAVE_64BIT_OBJECTS |
1161 | ? "elf64-bigmips" | |
1162 | : (HAVE_NEWABI | |
1163 | ? "elf32-nbigmips" : "elf32-bigmips")) | |
1164 | : (HAVE_64BIT_OBJECTS | |
1165 | ? "elf64-littlemips" | |
1166 | : (HAVE_NEWABI | |
1167 | ? "elf32-nlittlemips" : "elf32-littlemips"))); | |
e013f690 TS |
1168 | #endif |
1169 | default: | |
1170 | abort (); | |
1171 | return NULL; | |
1172 | } | |
1173 | } | |
1174 | ||
156c2f8b NC |
1175 | /* This function is called once, at assembler startup time. It should |
1176 | set up all the tables, etc. that the MD part of the assembler will need. */ | |
1177 | ||
252b5132 RH |
1178 | void |
1179 | md_begin () | |
1180 | { | |
252b5132 | 1181 | register const char *retval = NULL; |
156c2f8b | 1182 | int i = 0; |
252b5132 | 1183 | int broken = 0; |
1f25f5d3 | 1184 | |
ec68c924 | 1185 | if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, mips_arch)) |
252b5132 RH |
1186 | as_warn (_("Could not set architecture and machine")); |
1187 | ||
252b5132 RH |
1188 | op_hash = hash_new (); |
1189 | ||
1190 | for (i = 0; i < NUMOPCODES;) | |
1191 | { | |
1192 | const char *name = mips_opcodes[i].name; | |
1193 | ||
1194 | retval = hash_insert (op_hash, name, (PTR) &mips_opcodes[i]); | |
1195 | if (retval != NULL) | |
1196 | { | |
1197 | fprintf (stderr, _("internal error: can't hash `%s': %s\n"), | |
1198 | mips_opcodes[i].name, retval); | |
1199 | /* Probably a memory allocation problem? Give up now. */ | |
1200 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
1201 | } | |
1202 | do | |
1203 | { | |
1204 | if (mips_opcodes[i].pinfo != INSN_MACRO) | |
1205 | { | |
1206 | if (!validate_mips_insn (&mips_opcodes[i])) | |
1207 | broken = 1; | |
1208 | } | |
1209 | ++i; | |
1210 | } | |
1211 | while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name)); | |
1212 | } | |
1213 | ||
1214 | mips16_op_hash = hash_new (); | |
1215 | ||
1216 | i = 0; | |
1217 | while (i < bfd_mips16_num_opcodes) | |
1218 | { | |
1219 | const char *name = mips16_opcodes[i].name; | |
1220 | ||
1221 | retval = hash_insert (mips16_op_hash, name, (PTR) &mips16_opcodes[i]); | |
1222 | if (retval != NULL) | |
1223 | as_fatal (_("internal: can't hash `%s': %s"), | |
1224 | mips16_opcodes[i].name, retval); | |
1225 | do | |
1226 | { | |
1227 | if (mips16_opcodes[i].pinfo != INSN_MACRO | |
1228 | && ((mips16_opcodes[i].match & mips16_opcodes[i].mask) | |
1229 | != mips16_opcodes[i].match)) | |
1230 | { | |
1231 | fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"), | |
1232 | mips16_opcodes[i].name, mips16_opcodes[i].args); | |
1233 | broken = 1; | |
1234 | } | |
1235 | ++i; | |
1236 | } | |
1237 | while (i < bfd_mips16_num_opcodes | |
1238 | && strcmp (mips16_opcodes[i].name, name) == 0); | |
1239 | } | |
1240 | ||
1241 | if (broken) | |
1242 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
1243 | ||
1244 | /* We add all the general register names to the symbol table. This | |
1245 | helps us detect invalid uses of them. */ | |
1246 | for (i = 0; i < 32; i++) | |
1247 | { | |
1248 | char buf[5]; | |
1249 | ||
1250 | sprintf (buf, "$%d", i); | |
1251 | symbol_table_insert (symbol_new (buf, reg_section, i, | |
1252 | &zero_address_frag)); | |
1253 | } | |
76db943d TS |
1254 | symbol_table_insert (symbol_new ("$ra", reg_section, RA, |
1255 | &zero_address_frag)); | |
252b5132 RH |
1256 | symbol_table_insert (symbol_new ("$fp", reg_section, FP, |
1257 | &zero_address_frag)); | |
1258 | symbol_table_insert (symbol_new ("$sp", reg_section, SP, | |
1259 | &zero_address_frag)); | |
1260 | symbol_table_insert (symbol_new ("$gp", reg_section, GP, | |
1261 | &zero_address_frag)); | |
1262 | symbol_table_insert (symbol_new ("$at", reg_section, AT, | |
1263 | &zero_address_frag)); | |
1264 | symbol_table_insert (symbol_new ("$kt0", reg_section, KT0, | |
1265 | &zero_address_frag)); | |
1266 | symbol_table_insert (symbol_new ("$kt1", reg_section, KT1, | |
1267 | &zero_address_frag)); | |
85b51719 TS |
1268 | symbol_table_insert (symbol_new ("$zero", reg_section, ZERO, |
1269 | &zero_address_frag)); | |
252b5132 RH |
1270 | symbol_table_insert (symbol_new ("$pc", reg_section, -1, |
1271 | &zero_address_frag)); | |
1272 | ||
6047c971 AO |
1273 | /* If we don't add these register names to the symbol table, they |
1274 | may end up being added as regular symbols by operand(), and then | |
1275 | make it to the object file as undefined in case they're not | |
1276 | regarded as local symbols. They're local in o32, since `$' is a | |
1277 | local symbol prefix, but not in n32 or n64. */ | |
1278 | for (i = 0; i < 8; i++) | |
1279 | { | |
1280 | char buf[6]; | |
1281 | ||
1282 | sprintf (buf, "$fcc%i", i); | |
1283 | symbol_table_insert (symbol_new (buf, reg_section, -1, | |
1284 | &zero_address_frag)); | |
1285 | } | |
1286 | ||
b34976b6 | 1287 | mips_no_prev_insn (FALSE); |
252b5132 RH |
1288 | |
1289 | mips_gprmask = 0; | |
1290 | mips_cprmask[0] = 0; | |
1291 | mips_cprmask[1] = 0; | |
1292 | mips_cprmask[2] = 0; | |
1293 | mips_cprmask[3] = 0; | |
1294 | ||
1295 | /* set the default alignment for the text section (2**2) */ | |
1296 | record_alignment (text_section, 2); | |
1297 | ||
1298 | if (USE_GLOBAL_POINTER_OPT) | |
1299 | bfd_set_gp_size (stdoutput, g_switch_value); | |
1300 | ||
1301 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
1302 | { | |
1303 | /* On a native system, sections must be aligned to 16 byte | |
1304 | boundaries. When configured for an embedded ELF target, we | |
1305 | don't bother. */ | |
1306 | if (strcmp (TARGET_OS, "elf") != 0) | |
1307 | { | |
1308 | (void) bfd_set_section_alignment (stdoutput, text_section, 4); | |
1309 | (void) bfd_set_section_alignment (stdoutput, data_section, 4); | |
1310 | (void) bfd_set_section_alignment (stdoutput, bss_section, 4); | |
1311 | } | |
1312 | ||
1313 | /* Create a .reginfo section for register masks and a .mdebug | |
1314 | section for debugging information. */ | |
1315 | { | |
1316 | segT seg; | |
1317 | subsegT subseg; | |
1318 | flagword flags; | |
1319 | segT sec; | |
1320 | ||
1321 | seg = now_seg; | |
1322 | subseg = now_subseg; | |
1323 | ||
1324 | /* The ABI says this section should be loaded so that the | |
1325 | running program can access it. However, we don't load it | |
1326 | if we are configured for an embedded target */ | |
1327 | flags = SEC_READONLY | SEC_DATA; | |
1328 | if (strcmp (TARGET_OS, "elf") != 0) | |
1329 | flags |= SEC_ALLOC | SEC_LOAD; | |
1330 | ||
316f5878 | 1331 | if (mips_abi != N64_ABI) |
252b5132 RH |
1332 | { |
1333 | sec = subseg_new (".reginfo", (subsegT) 0); | |
1334 | ||
195325d2 TS |
1335 | bfd_set_section_flags (stdoutput, sec, flags); |
1336 | bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2); | |
bdaaa2e1 | 1337 | |
252b5132 RH |
1338 | #ifdef OBJ_ELF |
1339 | mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo)); | |
1340 | #endif | |
1341 | } | |
1342 | else | |
1343 | { | |
1344 | /* The 64-bit ABI uses a .MIPS.options section rather than | |
1345 | .reginfo section. */ | |
1346 | sec = subseg_new (".MIPS.options", (subsegT) 0); | |
195325d2 TS |
1347 | bfd_set_section_flags (stdoutput, sec, flags); |
1348 | bfd_set_section_alignment (stdoutput, sec, 3); | |
252b5132 RH |
1349 | |
1350 | #ifdef OBJ_ELF | |
1351 | /* Set up the option header. */ | |
1352 | { | |
1353 | Elf_Internal_Options opthdr; | |
1354 | char *f; | |
1355 | ||
1356 | opthdr.kind = ODK_REGINFO; | |
1357 | opthdr.size = (sizeof (Elf_External_Options) | |
1358 | + sizeof (Elf64_External_RegInfo)); | |
1359 | opthdr.section = 0; | |
1360 | opthdr.info = 0; | |
1361 | f = frag_more (sizeof (Elf_External_Options)); | |
1362 | bfd_mips_elf_swap_options_out (stdoutput, &opthdr, | |
1363 | (Elf_External_Options *) f); | |
1364 | ||
1365 | mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo)); | |
1366 | } | |
1367 | #endif | |
1368 | } | |
1369 | ||
1370 | if (ECOFF_DEBUGGING) | |
1371 | { | |
1372 | sec = subseg_new (".mdebug", (subsegT) 0); | |
1373 | (void) bfd_set_section_flags (stdoutput, sec, | |
1374 | SEC_HAS_CONTENTS | SEC_READONLY); | |
1375 | (void) bfd_set_section_alignment (stdoutput, sec, 2); | |
1376 | } | |
ecb4347a DJ |
1377 | #ifdef OBJ_ELF |
1378 | else if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
1379 | { | |
1380 | pdr_seg = subseg_new (".pdr", (subsegT) 0); | |
1381 | (void) bfd_set_section_flags (stdoutput, pdr_seg, | |
1382 | SEC_READONLY | SEC_RELOC | |
1383 | | SEC_DEBUGGING); | |
1384 | (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2); | |
1385 | } | |
252b5132 RH |
1386 | #endif |
1387 | ||
1388 | subseg_set (seg, subseg); | |
1389 | } | |
1390 | } | |
1391 | ||
1392 | if (! ECOFF_DEBUGGING) | |
1393 | md_obj_begin (); | |
1394 | } | |
1395 | ||
1396 | void | |
1397 | md_mips_end () | |
1398 | { | |
1399 | if (! ECOFF_DEBUGGING) | |
1400 | md_obj_end (); | |
1401 | } | |
1402 | ||
1403 | void | |
1404 | md_assemble (str) | |
1405 | char *str; | |
1406 | { | |
1407 | struct mips_cl_insn insn; | |
f6688943 TS |
1408 | bfd_reloc_code_real_type unused_reloc[3] |
1409 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 RH |
1410 | |
1411 | imm_expr.X_op = O_absent; | |
252b5132 | 1412 | offset_expr.X_op = O_absent; |
f6688943 TS |
1413 | imm_reloc[0] = BFD_RELOC_UNUSED; |
1414 | imm_reloc[1] = BFD_RELOC_UNUSED; | |
1415 | imm_reloc[2] = BFD_RELOC_UNUSED; | |
1416 | offset_reloc[0] = BFD_RELOC_UNUSED; | |
1417 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
1418 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
1419 | |
1420 | if (mips_opts.mips16) | |
1421 | mips16_ip (str, &insn); | |
1422 | else | |
1423 | { | |
1424 | mips_ip (str, &insn); | |
beae10d5 KH |
1425 | DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"), |
1426 | str, insn.insn_opcode)); | |
252b5132 RH |
1427 | } |
1428 | ||
1429 | if (insn_error) | |
1430 | { | |
1431 | as_bad ("%s `%s'", insn_error, str); | |
1432 | return; | |
1433 | } | |
1434 | ||
1435 | if (insn.insn_mo->pinfo == INSN_MACRO) | |
1436 | { | |
1437 | if (mips_opts.mips16) | |
1438 | mips16_macro (&insn); | |
1439 | else | |
1440 | macro (&insn); | |
1441 | } | |
1442 | else | |
1443 | { | |
1444 | if (imm_expr.X_op != O_absent) | |
5e0116d5 | 1445 | append_insn (NULL, &insn, &imm_expr, imm_reloc); |
252b5132 | 1446 | else if (offset_expr.X_op != O_absent) |
5e0116d5 | 1447 | append_insn (NULL, &insn, &offset_expr, offset_reloc); |
252b5132 | 1448 | else |
5e0116d5 | 1449 | append_insn (NULL, &insn, NULL, unused_reloc); |
252b5132 RH |
1450 | } |
1451 | } | |
1452 | ||
5919d012 RS |
1453 | /* Return true if the given relocation might need a matching %lo(). |
1454 | Note that R_MIPS_GOT16 relocations only need a matching %lo() when | |
1455 | applied to local symbols. */ | |
1456 | ||
1457 | static inline bfd_boolean | |
1458 | reloc_needs_lo_p (reloc) | |
1459 | bfd_reloc_code_real_type reloc; | |
1460 | { | |
1461 | return (reloc == BFD_RELOC_HI16_S | |
1462 | || reloc == BFD_RELOC_MIPS_GOT16); | |
1463 | } | |
1464 | ||
1465 | /* Return true if the given fixup is followed by a matching R_MIPS_LO16 | |
1466 | relocation. */ | |
1467 | ||
1468 | static inline bfd_boolean | |
1469 | fixup_has_matching_lo_p (fixp) | |
1470 | fixS *fixp; | |
1471 | { | |
1472 | return (fixp->fx_next != NULL | |
1473 | && fixp->fx_next->fx_r_type == BFD_RELOC_LO16 | |
1474 | && fixp->fx_addsy == fixp->fx_next->fx_addsy | |
1475 | && fixp->fx_offset == fixp->fx_next->fx_offset); | |
1476 | } | |
1477 | ||
252b5132 RH |
1478 | /* See whether instruction IP reads register REG. CLASS is the type |
1479 | of register. */ | |
1480 | ||
1481 | static int | |
1482 | insn_uses_reg (ip, reg, class) | |
1483 | struct mips_cl_insn *ip; | |
1484 | unsigned int reg; | |
1485 | enum mips_regclass class; | |
1486 | { | |
1487 | if (class == MIPS16_REG) | |
1488 | { | |
1489 | assert (mips_opts.mips16); | |
1490 | reg = mips16_to_32_reg_map[reg]; | |
1491 | class = MIPS_GR_REG; | |
1492 | } | |
1493 | ||
85b51719 TS |
1494 | /* Don't report on general register ZERO, since it never changes. */ |
1495 | if (class == MIPS_GR_REG && reg == ZERO) | |
252b5132 RH |
1496 | return 0; |
1497 | ||
1498 | if (class == MIPS_FP_REG) | |
1499 | { | |
1500 | assert (! mips_opts.mips16); | |
1501 | /* If we are called with either $f0 or $f1, we must check $f0. | |
1502 | This is not optimal, because it will introduce an unnecessary | |
1503 | NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would | |
1504 | need to distinguish reading both $f0 and $f1 or just one of | |
1505 | them. Note that we don't have to check the other way, | |
1506 | because there is no instruction that sets both $f0 and $f1 | |
1507 | and requires a delay. */ | |
1508 | if ((ip->insn_mo->pinfo & INSN_READ_FPR_S) | |
1509 | && ((((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS) &~(unsigned)1) | |
1510 | == (reg &~ (unsigned) 1))) | |
1511 | return 1; | |
1512 | if ((ip->insn_mo->pinfo & INSN_READ_FPR_T) | |
1513 | && ((((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT) &~(unsigned)1) | |
1514 | == (reg &~ (unsigned) 1))) | |
1515 | return 1; | |
1516 | } | |
1517 | else if (! mips_opts.mips16) | |
1518 | { | |
1519 | if ((ip->insn_mo->pinfo & INSN_READ_GPR_S) | |
1520 | && ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == reg) | |
1521 | return 1; | |
1522 | if ((ip->insn_mo->pinfo & INSN_READ_GPR_T) | |
1523 | && ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT) == reg) | |
1524 | return 1; | |
1525 | } | |
1526 | else | |
1527 | { | |
1528 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_X) | |
1529 | && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_RX) | |
1530 | & MIPS16OP_MASK_RX)] | |
1531 | == reg)) | |
1532 | return 1; | |
1533 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Y) | |
1534 | && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_RY) | |
1535 | & MIPS16OP_MASK_RY)] | |
1536 | == reg)) | |
1537 | return 1; | |
1538 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Z) | |
1539 | && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z) | |
1540 | & MIPS16OP_MASK_MOVE32Z)] | |
1541 | == reg)) | |
1542 | return 1; | |
1543 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_T) && reg == TREG) | |
1544 | return 1; | |
1545 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_SP) && reg == SP) | |
1546 | return 1; | |
1547 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_31) && reg == RA) | |
1548 | return 1; | |
1549 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_GPR_X) | |
1550 | && ((ip->insn_opcode >> MIPS16OP_SH_REGR32) | |
1551 | & MIPS16OP_MASK_REGR32) == reg) | |
1552 | return 1; | |
1553 | } | |
1554 | ||
1555 | return 0; | |
1556 | } | |
1557 | ||
1558 | /* This function returns true if modifying a register requires a | |
1559 | delay. */ | |
1560 | ||
1561 | static int | |
1562 | reg_needs_delay (reg) | |
156c2f8b | 1563 | unsigned int reg; |
252b5132 RH |
1564 | { |
1565 | unsigned long prev_pinfo; | |
1566 | ||
1567 | prev_pinfo = prev_insn.insn_mo->pinfo; | |
1568 | if (! mips_opts.noreorder | |
9ce8a5dd | 1569 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 RH |
1570 | && ((prev_pinfo & INSN_LOAD_COPROC_DELAY) |
1571 | || (! gpr_interlocks | |
1572 | && (prev_pinfo & INSN_LOAD_MEMORY_DELAY)))) | |
1573 | { | |
1574 | /* A load from a coprocessor or from memory. All load | |
1575 | delays delay the use of general register rt for one | |
1576 | instruction on the r3000. The r6000 and r4000 use | |
1577 | interlocks. */ | |
bdaaa2e1 | 1578 | /* Itbl support may require additional care here. */ |
252b5132 RH |
1579 | know (prev_pinfo & INSN_WRITE_GPR_T); |
1580 | if (reg == ((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT)) | |
1581 | return 1; | |
1582 | } | |
1583 | ||
1584 | return 0; | |
1585 | } | |
1586 | ||
1587 | /* Mark instruction labels in mips16 mode. This permits the linker to | |
1588 | handle them specially, such as generating jalx instructions when | |
1589 | needed. We also make them odd for the duration of the assembly, in | |
1590 | order to generate the right sort of code. We will make them even | |
1591 | in the adjust_symtab routine, while leaving them marked. This is | |
1592 | convenient for the debugger and the disassembler. The linker knows | |
1593 | to make them odd again. */ | |
1594 | ||
1595 | static void | |
1596 | mips16_mark_labels () | |
1597 | { | |
1598 | if (mips_opts.mips16) | |
1599 | { | |
1600 | struct insn_label_list *l; | |
98aa84af | 1601 | valueT val; |
252b5132 RH |
1602 | |
1603 | for (l = insn_labels; l != NULL; l = l->next) | |
1604 | { | |
1605 | #ifdef OBJ_ELF | |
1606 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
1607 | S_SET_OTHER (l->label, STO_MIPS16); | |
1608 | #endif | |
98aa84af AM |
1609 | val = S_GET_VALUE (l->label); |
1610 | if ((val & 1) == 0) | |
1611 | S_SET_VALUE (l->label, val + 1); | |
252b5132 RH |
1612 | } |
1613 | } | |
1614 | } | |
1615 | ||
1616 | /* Output an instruction. PLACE is where to put the instruction; if | |
1617 | it is NULL, this uses frag_more to get room. IP is the instruction | |
1618 | information. ADDRESS_EXPR is an operand of the instruction to be | |
1619 | used with RELOC_TYPE. */ | |
1620 | ||
1621 | static void | |
5e0116d5 | 1622 | append_insn (place, ip, address_expr, reloc_type) |
252b5132 RH |
1623 | char *place; |
1624 | struct mips_cl_insn *ip; | |
1625 | expressionS *address_expr; | |
f6688943 | 1626 | bfd_reloc_code_real_type *reloc_type; |
252b5132 RH |
1627 | { |
1628 | register unsigned long prev_pinfo, pinfo; | |
1629 | char *f; | |
f6688943 | 1630 | fixS *fixp[3]; |
252b5132 RH |
1631 | int nops = 0; |
1632 | ||
1633 | /* Mark instruction labels in mips16 mode. */ | |
f9419b05 | 1634 | mips16_mark_labels (); |
252b5132 RH |
1635 | |
1636 | prev_pinfo = prev_insn.insn_mo->pinfo; | |
1637 | pinfo = ip->insn_mo->pinfo; | |
1638 | ||
1639 | if (place == NULL && (! mips_opts.noreorder || prev_nop_frag != NULL)) | |
1640 | { | |
1641 | int prev_prev_nop; | |
1642 | ||
1643 | /* If the previous insn required any delay slots, see if we need | |
1644 | to insert a NOP or two. There are eight kinds of possible | |
1645 | hazards, of which an instruction can have at most one type. | |
1646 | (1) a load from memory delay | |
1647 | (2) a load from a coprocessor delay | |
1648 | (3) an unconditional branch delay | |
1649 | (4) a conditional branch delay | |
1650 | (5) a move to coprocessor register delay | |
1651 | (6) a load coprocessor register from memory delay | |
1652 | (7) a coprocessor condition code delay | |
1653 | (8) a HI/LO special register delay | |
1654 | ||
1655 | There are a lot of optimizations we could do that we don't. | |
1656 | In particular, we do not, in general, reorder instructions. | |
1657 | If you use gcc with optimization, it will reorder | |
1658 | instructions and generally do much more optimization then we | |
1659 | do here; repeating all that work in the assembler would only | |
1660 | benefit hand written assembly code, and does not seem worth | |
1661 | it. */ | |
1662 | ||
1663 | /* This is how a NOP is emitted. */ | |
1664 | #define emit_nop() \ | |
1665 | (mips_opts.mips16 \ | |
1666 | ? md_number_to_chars (frag_more (2), 0x6500, 2) \ | |
1667 | : md_number_to_chars (frag_more (4), 0, 4)) | |
1668 | ||
1669 | /* The previous insn might require a delay slot, depending upon | |
1670 | the contents of the current insn. */ | |
1671 | if (! mips_opts.mips16 | |
9ce8a5dd | 1672 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 RH |
1673 | && (((prev_pinfo & INSN_LOAD_COPROC_DELAY) |
1674 | && ! cop_interlocks) | |
1675 | || (! gpr_interlocks | |
1676 | && (prev_pinfo & INSN_LOAD_MEMORY_DELAY)))) | |
1677 | { | |
1678 | /* A load from a coprocessor or from memory. All load | |
1679 | delays delay the use of general register rt for one | |
1680 | instruction on the r3000. The r6000 and r4000 use | |
1681 | interlocks. */ | |
beae10d5 | 1682 | /* Itbl support may require additional care here. */ |
252b5132 RH |
1683 | know (prev_pinfo & INSN_WRITE_GPR_T); |
1684 | if (mips_optimize == 0 | |
1685 | || insn_uses_reg (ip, | |
1686 | ((prev_insn.insn_opcode >> OP_SH_RT) | |
1687 | & OP_MASK_RT), | |
1688 | MIPS_GR_REG)) | |
1689 | ++nops; | |
1690 | } | |
1691 | else if (! mips_opts.mips16 | |
9ce8a5dd | 1692 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 | 1693 | && (((prev_pinfo & INSN_COPROC_MOVE_DELAY) |
beae10d5 | 1694 | && ! cop_interlocks) |
e7af610e | 1695 | || (mips_opts.isa == ISA_MIPS1 |
252b5132 RH |
1696 | && (prev_pinfo & INSN_COPROC_MEMORY_DELAY)))) |
1697 | { | |
1698 | /* A generic coprocessor delay. The previous instruction | |
1699 | modified a coprocessor general or control register. If | |
1700 | it modified a control register, we need to avoid any | |
1701 | coprocessor instruction (this is probably not always | |
1702 | required, but it sometimes is). If it modified a general | |
1703 | register, we avoid using that register. | |
1704 | ||
1705 | On the r6000 and r4000 loading a coprocessor register | |
1706 | from memory is interlocked, and does not require a delay. | |
1707 | ||
1708 | This case is not handled very well. There is no special | |
1709 | knowledge of CP0 handling, and the coprocessors other | |
1710 | than the floating point unit are not distinguished at | |
1711 | all. */ | |
1712 | /* Itbl support may require additional care here. FIXME! | |
bdaaa2e1 | 1713 | Need to modify this to include knowledge about |
252b5132 RH |
1714 | user specified delays! */ |
1715 | if (prev_pinfo & INSN_WRITE_FPR_T) | |
1716 | { | |
1717 | if (mips_optimize == 0 | |
1718 | || insn_uses_reg (ip, | |
1719 | ((prev_insn.insn_opcode >> OP_SH_FT) | |
1720 | & OP_MASK_FT), | |
1721 | MIPS_FP_REG)) | |
1722 | ++nops; | |
1723 | } | |
1724 | else if (prev_pinfo & INSN_WRITE_FPR_S) | |
1725 | { | |
1726 | if (mips_optimize == 0 | |
1727 | || insn_uses_reg (ip, | |
1728 | ((prev_insn.insn_opcode >> OP_SH_FS) | |
1729 | & OP_MASK_FS), | |
1730 | MIPS_FP_REG)) | |
1731 | ++nops; | |
1732 | } | |
1733 | else | |
1734 | { | |
1735 | /* We don't know exactly what the previous instruction | |
1736 | does. If the current instruction uses a coprocessor | |
1737 | register, we must insert a NOP. If previous | |
1738 | instruction may set the condition codes, and the | |
1739 | current instruction uses them, we must insert two | |
1740 | NOPS. */ | |
bdaaa2e1 | 1741 | /* Itbl support may require additional care here. */ |
252b5132 RH |
1742 | if (mips_optimize == 0 |
1743 | || ((prev_pinfo & INSN_WRITE_COND_CODE) | |
1744 | && (pinfo & INSN_READ_COND_CODE))) | |
1745 | nops += 2; | |
1746 | else if (pinfo & INSN_COP) | |
1747 | ++nops; | |
1748 | } | |
1749 | } | |
1750 | else if (! mips_opts.mips16 | |
9ce8a5dd | 1751 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 RH |
1752 | && (prev_pinfo & INSN_WRITE_COND_CODE) |
1753 | && ! cop_interlocks) | |
1754 | { | |
1755 | /* The previous instruction sets the coprocessor condition | |
1756 | codes, but does not require a general coprocessor delay | |
1757 | (this means it is a floating point comparison | |
1758 | instruction). If this instruction uses the condition | |
1759 | codes, we need to insert a single NOP. */ | |
beae10d5 | 1760 | /* Itbl support may require additional care here. */ |
252b5132 RH |
1761 | if (mips_optimize == 0 |
1762 | || (pinfo & INSN_READ_COND_CODE)) | |
1763 | ++nops; | |
1764 | } | |
6b76fefe CM |
1765 | |
1766 | /* If we're fixing up mfhi/mflo for the r7000 and the | |
1767 | previous insn was an mfhi/mflo and the current insn | |
1768 | reads the register that the mfhi/mflo wrote to, then | |
1769 | insert two nops. */ | |
1770 | ||
1771 | else if (mips_7000_hilo_fix | |
1772 | && MF_HILO_INSN (prev_pinfo) | |
1773 | && insn_uses_reg (ip, ((prev_insn.insn_opcode >> OP_SH_RD) | |
beae10d5 KH |
1774 | & OP_MASK_RD), |
1775 | MIPS_GR_REG)) | |
6b76fefe CM |
1776 | { |
1777 | nops += 2; | |
1778 | } | |
1779 | ||
1780 | /* If we're fixing up mfhi/mflo for the r7000 and the | |
1781 | 2nd previous insn was an mfhi/mflo and the current insn | |
1782 | reads the register that the mfhi/mflo wrote to, then | |
1783 | insert one nop. */ | |
1784 | ||
1785 | else if (mips_7000_hilo_fix | |
1786 | && MF_HILO_INSN (prev_prev_insn.insn_opcode) | |
1787 | && insn_uses_reg (ip, ((prev_prev_insn.insn_opcode >> OP_SH_RD) | |
1788 | & OP_MASK_RD), | |
1789 | MIPS_GR_REG)) | |
bdaaa2e1 | 1790 | |
6b76fefe | 1791 | { |
f9419b05 | 1792 | ++nops; |
6b76fefe | 1793 | } |
bdaaa2e1 | 1794 | |
252b5132 RH |
1795 | else if (prev_pinfo & INSN_READ_LO) |
1796 | { | |
1797 | /* The previous instruction reads the LO register; if the | |
1798 | current instruction writes to the LO register, we must | |
bdaaa2e1 KH |
1799 | insert two NOPS. Some newer processors have interlocks. |
1800 | Also the tx39's multiply instructions can be exectuted | |
252b5132 | 1801 | immediatly after a read from HI/LO (without the delay), |
bdaaa2e1 KH |
1802 | though the tx39's divide insns still do require the |
1803 | delay. */ | |
252b5132 | 1804 | if (! (hilo_interlocks |
ec68c924 | 1805 | || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT))) |
252b5132 RH |
1806 | && (mips_optimize == 0 |
1807 | || (pinfo & INSN_WRITE_LO))) | |
1808 | nops += 2; | |
1809 | /* Most mips16 branch insns don't have a delay slot. | |
1810 | If a read from LO is immediately followed by a branch | |
1811 | to a write to LO we have a read followed by a write | |
1812 | less than 2 insns away. We assume the target of | |
1813 | a branch might be a write to LO, and insert a nop | |
bdaaa2e1 | 1814 | between a read and an immediately following branch. */ |
252b5132 RH |
1815 | else if (mips_opts.mips16 |
1816 | && (mips_optimize == 0 | |
1817 | || (pinfo & MIPS16_INSN_BRANCH))) | |
f9419b05 | 1818 | ++nops; |
252b5132 RH |
1819 | } |
1820 | else if (prev_insn.insn_mo->pinfo & INSN_READ_HI) | |
1821 | { | |
1822 | /* The previous instruction reads the HI register; if the | |
1823 | current instruction writes to the HI register, we must | |
1824 | insert a NOP. Some newer processors have interlocks. | |
bdaaa2e1 | 1825 | Also the note tx39's multiply above. */ |
252b5132 | 1826 | if (! (hilo_interlocks |
ec68c924 | 1827 | || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT))) |
252b5132 RH |
1828 | && (mips_optimize == 0 |
1829 | || (pinfo & INSN_WRITE_HI))) | |
1830 | nops += 2; | |
1831 | /* Most mips16 branch insns don't have a delay slot. | |
1832 | If a read from HI is immediately followed by a branch | |
1833 | to a write to HI we have a read followed by a write | |
1834 | less than 2 insns away. We assume the target of | |
1835 | a branch might be a write to HI, and insert a nop | |
bdaaa2e1 | 1836 | between a read and an immediately following branch. */ |
252b5132 RH |
1837 | else if (mips_opts.mips16 |
1838 | && (mips_optimize == 0 | |
1839 | || (pinfo & MIPS16_INSN_BRANCH))) | |
f9419b05 | 1840 | ++nops; |
252b5132 RH |
1841 | } |
1842 | ||
1843 | /* If the previous instruction was in a noreorder section, then | |
1844 | we don't want to insert the nop after all. */ | |
bdaaa2e1 | 1845 | /* Itbl support may require additional care here. */ |
252b5132 RH |
1846 | if (prev_insn_unreordered) |
1847 | nops = 0; | |
1848 | ||
1849 | /* There are two cases which require two intervening | |
1850 | instructions: 1) setting the condition codes using a move to | |
1851 | coprocessor instruction which requires a general coprocessor | |
1852 | delay and then reading the condition codes 2) reading the HI | |
1853 | or LO register and then writing to it (except on processors | |
1854 | which have interlocks). If we are not already emitting a NOP | |
1855 | instruction, we must check for these cases compared to the | |
1856 | instruction previous to the previous instruction. */ | |
1857 | if ((! mips_opts.mips16 | |
9ce8a5dd | 1858 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 RH |
1859 | && (prev_prev_insn.insn_mo->pinfo & INSN_COPROC_MOVE_DELAY) |
1860 | && (prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE) | |
1861 | && (pinfo & INSN_READ_COND_CODE) | |
1862 | && ! cop_interlocks) | |
1863 | || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_LO) | |
1864 | && (pinfo & INSN_WRITE_LO) | |
1865 | && ! (hilo_interlocks | |
ec68c924 | 1866 | || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT)))) |
252b5132 RH |
1867 | || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI) |
1868 | && (pinfo & INSN_WRITE_HI) | |
1869 | && ! (hilo_interlocks | |
ec68c924 | 1870 | || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT))))) |
252b5132 RH |
1871 | prev_prev_nop = 1; |
1872 | else | |
1873 | prev_prev_nop = 0; | |
1874 | ||
1875 | if (prev_prev_insn_unreordered) | |
1876 | prev_prev_nop = 0; | |
1877 | ||
1878 | if (prev_prev_nop && nops == 0) | |
1879 | ++nops; | |
1880 | ||
60b63b72 RS |
1881 | if (mips_fix_4122_bugs && prev_insn.insn_mo->name) |
1882 | { | |
1883 | /* We're out of bits in pinfo, so we must resort to string | |
1884 | ops here. Shortcuts are selected based on opcodes being | |
1885 | limited to the VR4122 instruction set. */ | |
1886 | int min_nops = 0; | |
1887 | const char *pn = prev_insn.insn_mo->name; | |
1888 | const char *tn = ip->insn_mo->name; | |
1889 | if (strncmp(pn, "macc", 4) == 0 | |
1890 | || strncmp(pn, "dmacc", 5) == 0) | |
1891 | { | |
1892 | /* Errata 21 - [D]DIV[U] after [D]MACC */ | |
1893 | if (strstr (tn, "div")) | |
1894 | { | |
1895 | min_nops = 1; | |
1896 | } | |
1897 | ||
1898 | /* Errata 23 - Continuous DMULT[U]/DMACC instructions */ | |
1899 | if (pn[0] == 'd' /* dmacc */ | |
1900 | && (strncmp(tn, "dmult", 5) == 0 | |
1901 | || strncmp(tn, "dmacc", 5) == 0)) | |
1902 | { | |
1903 | min_nops = 1; | |
1904 | } | |
1905 | ||
1906 | /* Errata 24 - MT{LO,HI} after [D]MACC */ | |
1907 | if (strcmp (tn, "mtlo") == 0 | |
1908 | || strcmp (tn, "mthi") == 0) | |
1909 | { | |
1910 | min_nops = 1; | |
1911 | } | |
1912 | ||
1913 | } | |
1914 | else if (strncmp(pn, "dmult", 5) == 0 | |
1915 | && (strncmp(tn, "dmult", 5) == 0 | |
1916 | || strncmp(tn, "dmacc", 5) == 0)) | |
1917 | { | |
1918 | /* Here is the rest of errata 23. */ | |
1919 | min_nops = 1; | |
1920 | } | |
1921 | if (nops < min_nops) | |
1922 | nops = min_nops; | |
1923 | } | |
1924 | ||
252b5132 RH |
1925 | /* If we are being given a nop instruction, don't bother with |
1926 | one of the nops we would otherwise output. This will only | |
1927 | happen when a nop instruction is used with mips_optimize set | |
1928 | to 0. */ | |
1929 | if (nops > 0 | |
1930 | && ! mips_opts.noreorder | |
156c2f8b | 1931 | && ip->insn_opcode == (unsigned) (mips_opts.mips16 ? 0x6500 : 0)) |
252b5132 RH |
1932 | --nops; |
1933 | ||
1934 | /* Now emit the right number of NOP instructions. */ | |
1935 | if (nops > 0 && ! mips_opts.noreorder) | |
1936 | { | |
1937 | fragS *old_frag; | |
1938 | unsigned long old_frag_offset; | |
1939 | int i; | |
1940 | struct insn_label_list *l; | |
1941 | ||
1942 | old_frag = frag_now; | |
1943 | old_frag_offset = frag_now_fix (); | |
1944 | ||
1945 | for (i = 0; i < nops; i++) | |
1946 | emit_nop (); | |
1947 | ||
1948 | if (listing) | |
1949 | { | |
1950 | listing_prev_line (); | |
1951 | /* We may be at the start of a variant frag. In case we | |
1952 | are, make sure there is enough space for the frag | |
1953 | after the frags created by listing_prev_line. The | |
1954 | argument to frag_grow here must be at least as large | |
1955 | as the argument to all other calls to frag_grow in | |
1956 | this file. We don't have to worry about being in the | |
1957 | middle of a variant frag, because the variants insert | |
1958 | all needed nop instructions themselves. */ | |
1959 | frag_grow (40); | |
1960 | } | |
1961 | ||
1962 | for (l = insn_labels; l != NULL; l = l->next) | |
1963 | { | |
98aa84af AM |
1964 | valueT val; |
1965 | ||
252b5132 | 1966 | assert (S_GET_SEGMENT (l->label) == now_seg); |
49309057 | 1967 | symbol_set_frag (l->label, frag_now); |
98aa84af | 1968 | val = (valueT) frag_now_fix (); |
252b5132 RH |
1969 | /* mips16 text labels are stored as odd. */ |
1970 | if (mips_opts.mips16) | |
f9419b05 | 1971 | ++val; |
98aa84af | 1972 | S_SET_VALUE (l->label, val); |
252b5132 RH |
1973 | } |
1974 | ||
1975 | #ifndef NO_ECOFF_DEBUGGING | |
1976 | if (ECOFF_DEBUGGING) | |
1977 | ecoff_fix_loc (old_frag, old_frag_offset); | |
1978 | #endif | |
1979 | } | |
1980 | else if (prev_nop_frag != NULL) | |
1981 | { | |
1982 | /* We have a frag holding nops we may be able to remove. If | |
1983 | we don't need any nops, we can decrease the size of | |
1984 | prev_nop_frag by the size of one instruction. If we do | |
bdaaa2e1 | 1985 | need some nops, we count them in prev_nops_required. */ |
252b5132 RH |
1986 | if (prev_nop_frag_since == 0) |
1987 | { | |
1988 | if (nops == 0) | |
1989 | { | |
1990 | prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4; | |
1991 | --prev_nop_frag_holds; | |
1992 | } | |
1993 | else | |
1994 | prev_nop_frag_required += nops; | |
1995 | } | |
1996 | else | |
1997 | { | |
1998 | if (prev_prev_nop == 0) | |
1999 | { | |
2000 | prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4; | |
2001 | --prev_nop_frag_holds; | |
2002 | } | |
2003 | else | |
2004 | ++prev_nop_frag_required; | |
2005 | } | |
2006 | ||
2007 | if (prev_nop_frag_holds <= prev_nop_frag_required) | |
2008 | prev_nop_frag = NULL; | |
2009 | ||
2010 | ++prev_nop_frag_since; | |
2011 | ||
2012 | /* Sanity check: by the time we reach the second instruction | |
2013 | after prev_nop_frag, we should have used up all the nops | |
2014 | one way or another. */ | |
2015 | assert (prev_nop_frag_since <= 1 || prev_nop_frag == NULL); | |
2016 | } | |
2017 | } | |
2018 | ||
4a6a3df4 AO |
2019 | if (place == NULL |
2020 | && address_expr | |
0b25d3e6 | 2021 | && *reloc_type == BFD_RELOC_16_PCREL_S2 |
4a6a3df4 AO |
2022 | && (pinfo & INSN_UNCOND_BRANCH_DELAY || pinfo & INSN_COND_BRANCH_DELAY |
2023 | || pinfo & INSN_COND_BRANCH_LIKELY) | |
2024 | && mips_relax_branch | |
2025 | /* Don't try branch relaxation within .set nomacro, or within | |
2026 | .set noat if we use $at for PIC computations. If it turns | |
2027 | out that the branch was out-of-range, we'll get an error. */ | |
2028 | && !mips_opts.warn_about_macros | |
2029 | && !(mips_opts.noat && mips_pic != NO_PIC) | |
2030 | && !mips_opts.mips16) | |
2031 | { | |
2032 | f = frag_var (rs_machine_dependent, | |
2033 | relaxed_branch_length | |
2034 | (NULL, NULL, | |
2035 | (pinfo & INSN_UNCOND_BRANCH_DELAY) ? -1 | |
2036 | : (pinfo & INSN_COND_BRANCH_LIKELY) ? 1 : 0), 4, | |
2037 | RELAX_BRANCH_ENCODE | |
af6ae2ad | 2038 | (pinfo & INSN_UNCOND_BRANCH_DELAY, |
4a6a3df4 AO |
2039 | pinfo & INSN_COND_BRANCH_LIKELY, |
2040 | pinfo & INSN_WRITE_GPR_31, | |
2041 | 0), | |
2042 | address_expr->X_add_symbol, | |
2043 | address_expr->X_add_number, | |
2044 | 0); | |
2045 | *reloc_type = BFD_RELOC_UNUSED; | |
2046 | } | |
2047 | else if (*reloc_type > BFD_RELOC_UNUSED) | |
252b5132 RH |
2048 | { |
2049 | /* We need to set up a variant frag. */ | |
2050 | assert (mips_opts.mips16 && address_expr != NULL); | |
2051 | f = frag_var (rs_machine_dependent, 4, 0, | |
f6688943 | 2052 | RELAX_MIPS16_ENCODE (*reloc_type - BFD_RELOC_UNUSED, |
252b5132 RH |
2053 | mips16_small, mips16_ext, |
2054 | (prev_pinfo | |
2055 | & INSN_UNCOND_BRANCH_DELAY), | |
f6688943 | 2056 | (*prev_insn_reloc_type |
252b5132 | 2057 | == BFD_RELOC_MIPS16_JMP)), |
c4e7957c | 2058 | make_expr_symbol (address_expr), 0, NULL); |
252b5132 RH |
2059 | } |
2060 | else if (place != NULL) | |
2061 | f = place; | |
2062 | else if (mips_opts.mips16 | |
2063 | && ! ip->use_extend | |
f6688943 | 2064 | && *reloc_type != BFD_RELOC_MIPS16_JMP) |
252b5132 RH |
2065 | { |
2066 | /* Make sure there is enough room to swap this instruction with | |
2067 | a following jump instruction. */ | |
2068 | frag_grow (6); | |
2069 | f = frag_more (2); | |
2070 | } | |
2071 | else | |
2072 | { | |
2073 | if (mips_opts.mips16 | |
2074 | && mips_opts.noreorder | |
2075 | && (prev_pinfo & INSN_UNCOND_BRANCH_DELAY) != 0) | |
2076 | as_warn (_("extended instruction in delay slot")); | |
2077 | ||
2078 | f = frag_more (4); | |
2079 | } | |
2080 | ||
f6688943 TS |
2081 | fixp[0] = fixp[1] = fixp[2] = NULL; |
2082 | if (address_expr != NULL && *reloc_type < BFD_RELOC_UNUSED) | |
252b5132 RH |
2083 | { |
2084 | if (address_expr->X_op == O_constant) | |
2085 | { | |
4db1a35d | 2086 | valueT tmp; |
f6688943 TS |
2087 | |
2088 | switch (*reloc_type) | |
252b5132 RH |
2089 | { |
2090 | case BFD_RELOC_32: | |
2091 | ip->insn_opcode |= address_expr->X_add_number; | |
2092 | break; | |
2093 | ||
f6688943 TS |
2094 | case BFD_RELOC_MIPS_HIGHEST: |
2095 | tmp = (address_expr->X_add_number + 0x800080008000) >> 16; | |
2096 | tmp >>= 16; | |
2097 | ip->insn_opcode |= (tmp >> 16) & 0xffff; | |
2098 | break; | |
2099 | ||
2100 | case BFD_RELOC_MIPS_HIGHER: | |
2101 | tmp = (address_expr->X_add_number + 0x80008000) >> 16; | |
2102 | ip->insn_opcode |= (tmp >> 16) & 0xffff; | |
2103 | break; | |
2104 | ||
2105 | case BFD_RELOC_HI16_S: | |
2106 | ip->insn_opcode |= ((address_expr->X_add_number + 0x8000) | |
2107 | >> 16) & 0xffff; | |
2108 | break; | |
2109 | ||
2110 | case BFD_RELOC_HI16: | |
2111 | ip->insn_opcode |= (address_expr->X_add_number >> 16) & 0xffff; | |
2112 | break; | |
2113 | ||
252b5132 | 2114 | case BFD_RELOC_LO16: |
ed6fb7bd | 2115 | case BFD_RELOC_MIPS_GOT_DISP: |
252b5132 RH |
2116 | ip->insn_opcode |= address_expr->X_add_number & 0xffff; |
2117 | break; | |
2118 | ||
2119 | case BFD_RELOC_MIPS_JMP: | |
2120 | if ((address_expr->X_add_number & 3) != 0) | |
2121 | as_bad (_("jump to misaligned address (0x%lx)"), | |
2122 | (unsigned long) address_expr->X_add_number); | |
f3c0ec86 | 2123 | if (address_expr->X_add_number & ~0xfffffff) |
7496292d TS |
2124 | as_bad (_("jump address range overflow (0x%lx)"), |
2125 | (unsigned long) address_expr->X_add_number); | |
252b5132 RH |
2126 | ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0x3ffffff; |
2127 | break; | |
2128 | ||
2129 | case BFD_RELOC_MIPS16_JMP: | |
2130 | if ((address_expr->X_add_number & 3) != 0) | |
2131 | as_bad (_("jump to misaligned address (0x%lx)"), | |
2132 | (unsigned long) address_expr->X_add_number); | |
f3c0ec86 | 2133 | if (address_expr->X_add_number & ~0xfffffff) |
7496292d TS |
2134 | as_bad (_("jump address range overflow (0x%lx)"), |
2135 | (unsigned long) address_expr->X_add_number); | |
252b5132 RH |
2136 | ip->insn_opcode |= |
2137 | (((address_expr->X_add_number & 0x7c0000) << 3) | |
2138 | | ((address_expr->X_add_number & 0xf800000) >> 7) | |
2139 | | ((address_expr->X_add_number & 0x3fffc) >> 2)); | |
2140 | break; | |
2141 | ||
252b5132 RH |
2142 | case BFD_RELOC_16_PCREL_S2: |
2143 | goto need_reloc; | |
2144 | ||
2145 | default: | |
2146 | internalError (); | |
2147 | } | |
2148 | } | |
2149 | else | |
2150 | { | |
2151 | need_reloc: | |
f6688943 | 2152 | /* Don't generate a reloc if we are writing into a variant frag. */ |
252b5132 RH |
2153 | if (place == NULL) |
2154 | { | |
f6688943 TS |
2155 | fixp[0] = fix_new_exp (frag_now, f - frag_now->fr_literal, 4, |
2156 | address_expr, | |
0b25d3e6 | 2157 | *reloc_type == BFD_RELOC_16_PCREL_S2, |
f6688943 TS |
2158 | reloc_type[0]); |
2159 | ||
b6ff326e | 2160 | /* These relocations can have an addend that won't fit in |
f6688943 TS |
2161 | 4 octets for 64bit assembly. */ |
2162 | if (HAVE_64BIT_GPRS && | |
2163 | (*reloc_type == BFD_RELOC_16 | |
98d3f06f KH |
2164 | || *reloc_type == BFD_RELOC_32 |
2165 | || *reloc_type == BFD_RELOC_MIPS_JMP | |
2166 | || *reloc_type == BFD_RELOC_HI16_S | |
2167 | || *reloc_type == BFD_RELOC_LO16 | |
2168 | || *reloc_type == BFD_RELOC_GPREL16 | |
2169 | || *reloc_type == BFD_RELOC_MIPS_LITERAL | |
2170 | || *reloc_type == BFD_RELOC_GPREL32 | |
2171 | || *reloc_type == BFD_RELOC_64 | |
2172 | || *reloc_type == BFD_RELOC_CTOR | |
2173 | || *reloc_type == BFD_RELOC_MIPS_SUB | |
2174 | || *reloc_type == BFD_RELOC_MIPS_HIGHEST | |
2175 | || *reloc_type == BFD_RELOC_MIPS_HIGHER | |
2176 | || *reloc_type == BFD_RELOC_MIPS_SCN_DISP | |
2177 | || *reloc_type == BFD_RELOC_MIPS_REL16 | |
2178 | || *reloc_type == BFD_RELOC_MIPS_RELGOT)) | |
f6688943 TS |
2179 | fixp[0]->fx_no_overflow = 1; |
2180 | ||
5919d012 | 2181 | if (reloc_needs_lo_p (*reloc_type)) |
252b5132 RH |
2182 | { |
2183 | struct mips_hi_fixup *hi_fixup; | |
2184 | ||
5919d012 RS |
2185 | /* Reuse the last entry if it already has a matching %lo. */ |
2186 | hi_fixup = mips_hi_fixup_list; | |
2187 | if (hi_fixup == 0 | |
2188 | || !fixup_has_matching_lo_p (hi_fixup->fixp)) | |
2189 | { | |
2190 | hi_fixup = ((struct mips_hi_fixup *) | |
2191 | xmalloc (sizeof (struct mips_hi_fixup))); | |
2192 | hi_fixup->next = mips_hi_fixup_list; | |
2193 | mips_hi_fixup_list = hi_fixup; | |
2194 | } | |
f6688943 | 2195 | hi_fixup->fixp = fixp[0]; |
252b5132 | 2196 | hi_fixup->seg = now_seg; |
252b5132 | 2197 | } |
f6688943 TS |
2198 | |
2199 | if (reloc_type[1] != BFD_RELOC_UNUSED) | |
2200 | { | |
2201 | /* FIXME: This symbol can be one of | |
2202 | RSS_UNDEF, RSS_GP, RSS_GP0, RSS_LOC. */ | |
2203 | address_expr->X_op = O_absent; | |
2204 | address_expr->X_add_symbol = 0; | |
2205 | address_expr->X_add_number = 0; | |
2206 | ||
2207 | fixp[1] = fix_new_exp (frag_now, f - frag_now->fr_literal, | |
b34976b6 | 2208 | 4, address_expr, FALSE, |
f6688943 TS |
2209 | reloc_type[1]); |
2210 | ||
b6ff326e | 2211 | /* These relocations can have an addend that won't fit in |
f6688943 TS |
2212 | 4 octets for 64bit assembly. */ |
2213 | if (HAVE_64BIT_GPRS && | |
2214 | (*reloc_type == BFD_RELOC_16 | |
2215 | || *reloc_type == BFD_RELOC_32 | |
2216 | || *reloc_type == BFD_RELOC_MIPS_JMP | |
2217 | || *reloc_type == BFD_RELOC_HI16_S | |
2218 | || *reloc_type == BFD_RELOC_LO16 | |
2219 | || *reloc_type == BFD_RELOC_GPREL16 | |
2220 | || *reloc_type == BFD_RELOC_MIPS_LITERAL | |
2221 | || *reloc_type == BFD_RELOC_GPREL32 | |
2222 | || *reloc_type == BFD_RELOC_64 | |
2223 | || *reloc_type == BFD_RELOC_CTOR | |
2224 | || *reloc_type == BFD_RELOC_MIPS_SUB | |
2225 | || *reloc_type == BFD_RELOC_MIPS_HIGHEST | |
2226 | || *reloc_type == BFD_RELOC_MIPS_HIGHER | |
2227 | || *reloc_type == BFD_RELOC_MIPS_SCN_DISP | |
2228 | || *reloc_type == BFD_RELOC_MIPS_REL16 | |
2229 | || *reloc_type == BFD_RELOC_MIPS_RELGOT)) | |
98d3f06f | 2230 | fixp[1]->fx_no_overflow = 1; |
f6688943 TS |
2231 | |
2232 | if (reloc_type[2] != BFD_RELOC_UNUSED) | |
2233 | { | |
2234 | address_expr->X_op = O_absent; | |
2235 | address_expr->X_add_symbol = 0; | |
2236 | address_expr->X_add_number = 0; | |
2237 | ||
2238 | fixp[2] = fix_new_exp (frag_now, | |
2239 | f - frag_now->fr_literal, 4, | |
b34976b6 | 2240 | address_expr, FALSE, |
f6688943 TS |
2241 | reloc_type[2]); |
2242 | ||
b6ff326e | 2243 | /* These relocations can have an addend that won't fit in |
f6688943 TS |
2244 | 4 octets for 64bit assembly. */ |
2245 | if (HAVE_64BIT_GPRS && | |
2246 | (*reloc_type == BFD_RELOC_16 | |
2247 | || *reloc_type == BFD_RELOC_32 | |
2248 | || *reloc_type == BFD_RELOC_MIPS_JMP | |
2249 | || *reloc_type == BFD_RELOC_HI16_S | |
2250 | || *reloc_type == BFD_RELOC_LO16 | |
2251 | || *reloc_type == BFD_RELOC_GPREL16 | |
2252 | || *reloc_type == BFD_RELOC_MIPS_LITERAL | |
2253 | || *reloc_type == BFD_RELOC_GPREL32 | |
2254 | || *reloc_type == BFD_RELOC_64 | |
2255 | || *reloc_type == BFD_RELOC_CTOR | |
2256 | || *reloc_type == BFD_RELOC_MIPS_SUB | |
2257 | || *reloc_type == BFD_RELOC_MIPS_HIGHEST | |
2258 | || *reloc_type == BFD_RELOC_MIPS_HIGHER | |
2259 | || *reloc_type == BFD_RELOC_MIPS_SCN_DISP | |
2260 | || *reloc_type == BFD_RELOC_MIPS_REL16 | |
2261 | || *reloc_type == BFD_RELOC_MIPS_RELGOT)) | |
98d3f06f | 2262 | fixp[2]->fx_no_overflow = 1; |
f6688943 TS |
2263 | } |
2264 | } | |
252b5132 RH |
2265 | } |
2266 | } | |
2267 | } | |
2268 | ||
2269 | if (! mips_opts.mips16) | |
c5dd6aab DJ |
2270 | { |
2271 | md_number_to_chars (f, ip->insn_opcode, 4); | |
2272 | #ifdef OBJ_ELF | |
2273 | dwarf2_emit_insn (4); | |
2274 | #endif | |
2275 | } | |
f6688943 | 2276 | else if (*reloc_type == BFD_RELOC_MIPS16_JMP) |
252b5132 RH |
2277 | { |
2278 | md_number_to_chars (f, ip->insn_opcode >> 16, 2); | |
2279 | md_number_to_chars (f + 2, ip->insn_opcode & 0xffff, 2); | |
c5dd6aab DJ |
2280 | #ifdef OBJ_ELF |
2281 | dwarf2_emit_insn (4); | |
2282 | #endif | |
252b5132 RH |
2283 | } |
2284 | else | |
2285 | { | |
2286 | if (ip->use_extend) | |
2287 | { | |
2288 | md_number_to_chars (f, 0xf000 | ip->extend, 2); | |
2289 | f += 2; | |
2290 | } | |
2291 | md_number_to_chars (f, ip->insn_opcode, 2); | |
c5dd6aab DJ |
2292 | #ifdef OBJ_ELF |
2293 | dwarf2_emit_insn (ip->use_extend ? 4 : 2); | |
2294 | #endif | |
252b5132 RH |
2295 | } |
2296 | ||
2297 | /* Update the register mask information. */ | |
2298 | if (! mips_opts.mips16) | |
2299 | { | |
2300 | if (pinfo & INSN_WRITE_GPR_D) | |
2301 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD); | |
2302 | if ((pinfo & (INSN_WRITE_GPR_T | INSN_READ_GPR_T)) != 0) | |
2303 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT); | |
2304 | if (pinfo & INSN_READ_GPR_S) | |
2305 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS); | |
2306 | if (pinfo & INSN_WRITE_GPR_31) | |
f9419b05 | 2307 | mips_gprmask |= 1 << RA; |
252b5132 RH |
2308 | if (pinfo & INSN_WRITE_FPR_D) |
2309 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FD) & OP_MASK_FD); | |
2310 | if ((pinfo & (INSN_WRITE_FPR_S | INSN_READ_FPR_S)) != 0) | |
2311 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS); | |
2312 | if ((pinfo & (INSN_WRITE_FPR_T | INSN_READ_FPR_T)) != 0) | |
2313 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT); | |
2314 | if ((pinfo & INSN_READ_FPR_R) != 0) | |
2315 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FR) & OP_MASK_FR); | |
2316 | if (pinfo & INSN_COP) | |
2317 | { | |
bdaaa2e1 KH |
2318 | /* We don't keep enough information to sort these cases out. |
2319 | The itbl support does keep this information however, although | |
2320 | we currently don't support itbl fprmats as part of the cop | |
2321 | instruction. May want to add this support in the future. */ | |
252b5132 RH |
2322 | } |
2323 | /* Never set the bit for $0, which is always zero. */ | |
beae10d5 | 2324 | mips_gprmask &= ~1 << 0; |
252b5132 RH |
2325 | } |
2326 | else | |
2327 | { | |
2328 | if (pinfo & (MIPS16_INSN_WRITE_X | MIPS16_INSN_READ_X)) | |
2329 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RX) | |
2330 | & MIPS16OP_MASK_RX); | |
2331 | if (pinfo & (MIPS16_INSN_WRITE_Y | MIPS16_INSN_READ_Y)) | |
2332 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RY) | |
2333 | & MIPS16OP_MASK_RY); | |
2334 | if (pinfo & MIPS16_INSN_WRITE_Z) | |
2335 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RZ) | |
2336 | & MIPS16OP_MASK_RZ); | |
2337 | if (pinfo & (MIPS16_INSN_WRITE_T | MIPS16_INSN_READ_T)) | |
2338 | mips_gprmask |= 1 << TREG; | |
2339 | if (pinfo & (MIPS16_INSN_WRITE_SP | MIPS16_INSN_READ_SP)) | |
2340 | mips_gprmask |= 1 << SP; | |
2341 | if (pinfo & (MIPS16_INSN_WRITE_31 | MIPS16_INSN_READ_31)) | |
2342 | mips_gprmask |= 1 << RA; | |
2343 | if (pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
2344 | mips_gprmask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode); | |
2345 | if (pinfo & MIPS16_INSN_READ_Z) | |
2346 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z) | |
2347 | & MIPS16OP_MASK_MOVE32Z); | |
2348 | if (pinfo & MIPS16_INSN_READ_GPR_X) | |
2349 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_REGR32) | |
2350 | & MIPS16OP_MASK_REGR32); | |
2351 | } | |
2352 | ||
2353 | if (place == NULL && ! mips_opts.noreorder) | |
2354 | { | |
2355 | /* Filling the branch delay slot is more complex. We try to | |
2356 | switch the branch with the previous instruction, which we can | |
2357 | do if the previous instruction does not set up a condition | |
2358 | that the branch tests and if the branch is not itself the | |
2359 | target of any branch. */ | |
2360 | if ((pinfo & INSN_UNCOND_BRANCH_DELAY) | |
2361 | || (pinfo & INSN_COND_BRANCH_DELAY)) | |
2362 | { | |
2363 | if (mips_optimize < 2 | |
2364 | /* If we have seen .set volatile or .set nomove, don't | |
2365 | optimize. */ | |
2366 | || mips_opts.nomove != 0 | |
2367 | /* If we had to emit any NOP instructions, then we | |
2368 | already know we can not swap. */ | |
2369 | || nops != 0 | |
2370 | /* If we don't even know the previous insn, we can not | |
bdaaa2e1 | 2371 | swap. */ |
252b5132 RH |
2372 | || ! prev_insn_valid |
2373 | /* If the previous insn is already in a branch delay | |
2374 | slot, then we can not swap. */ | |
2375 | || prev_insn_is_delay_slot | |
2376 | /* If the previous previous insn was in a .set | |
2377 | noreorder, we can't swap. Actually, the MIPS | |
2378 | assembler will swap in this situation. However, gcc | |
2379 | configured -with-gnu-as will generate code like | |
2380 | .set noreorder | |
2381 | lw $4,XXX | |
2382 | .set reorder | |
2383 | INSN | |
2384 | bne $4,$0,foo | |
2385 | in which we can not swap the bne and INSN. If gcc is | |
2386 | not configured -with-gnu-as, it does not output the | |
2387 | .set pseudo-ops. We don't have to check | |
2388 | prev_insn_unreordered, because prev_insn_valid will | |
2389 | be 0 in that case. We don't want to use | |
2390 | prev_prev_insn_valid, because we do want to be able | |
2391 | to swap at the start of a function. */ | |
2392 | || prev_prev_insn_unreordered | |
2393 | /* If the branch is itself the target of a branch, we | |
2394 | can not swap. We cheat on this; all we check for is | |
2395 | whether there is a label on this instruction. If | |
2396 | there are any branches to anything other than a | |
2397 | label, users must use .set noreorder. */ | |
2398 | || insn_labels != NULL | |
2399 | /* If the previous instruction is in a variant frag, we | |
2400 | can not do the swap. This does not apply to the | |
2401 | mips16, which uses variant frags for different | |
2402 | purposes. */ | |
2403 | || (! mips_opts.mips16 | |
2404 | && prev_insn_frag->fr_type == rs_machine_dependent) | |
2405 | /* If the branch reads the condition codes, we don't | |
2406 | even try to swap, because in the sequence | |
2407 | ctc1 $X,$31 | |
2408 | INSN | |
2409 | INSN | |
2410 | bc1t LABEL | |
2411 | we can not swap, and I don't feel like handling that | |
2412 | case. */ | |
2413 | || (! mips_opts.mips16 | |
9ce8a5dd | 2414 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 RH |
2415 | && (pinfo & INSN_READ_COND_CODE)) |
2416 | /* We can not swap with an instruction that requires a | |
2417 | delay slot, becase the target of the branch might | |
2418 | interfere with that instruction. */ | |
2419 | || (! mips_opts.mips16 | |
9ce8a5dd | 2420 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 | 2421 | && (prev_pinfo |
bdaaa2e1 | 2422 | /* Itbl support may require additional care here. */ |
252b5132 RH |
2423 | & (INSN_LOAD_COPROC_DELAY |
2424 | | INSN_COPROC_MOVE_DELAY | |
2425 | | INSN_WRITE_COND_CODE))) | |
2426 | || (! (hilo_interlocks | |
ec68c924 | 2427 | || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT))) |
252b5132 RH |
2428 | && (prev_pinfo |
2429 | & (INSN_READ_LO | |
2430 | | INSN_READ_HI))) | |
2431 | || (! mips_opts.mips16 | |
2432 | && ! gpr_interlocks | |
2433 | && (prev_pinfo & INSN_LOAD_MEMORY_DELAY)) | |
2434 | || (! mips_opts.mips16 | |
e7af610e | 2435 | && mips_opts.isa == ISA_MIPS1 |
bdaaa2e1 | 2436 | /* Itbl support may require additional care here. */ |
252b5132 RH |
2437 | && (prev_pinfo & INSN_COPROC_MEMORY_DELAY)) |
2438 | /* We can not swap with a branch instruction. */ | |
2439 | || (prev_pinfo | |
2440 | & (INSN_UNCOND_BRANCH_DELAY | |
2441 | | INSN_COND_BRANCH_DELAY | |
2442 | | INSN_COND_BRANCH_LIKELY)) | |
2443 | /* We do not swap with a trap instruction, since it | |
2444 | complicates trap handlers to have the trap | |
2445 | instruction be in a delay slot. */ | |
2446 | || (prev_pinfo & INSN_TRAP) | |
2447 | /* If the branch reads a register that the previous | |
2448 | instruction sets, we can not swap. */ | |
2449 | || (! mips_opts.mips16 | |
2450 | && (prev_pinfo & INSN_WRITE_GPR_T) | |
2451 | && insn_uses_reg (ip, | |
2452 | ((prev_insn.insn_opcode >> OP_SH_RT) | |
2453 | & OP_MASK_RT), | |
2454 | MIPS_GR_REG)) | |
2455 | || (! mips_opts.mips16 | |
2456 | && (prev_pinfo & INSN_WRITE_GPR_D) | |
2457 | && insn_uses_reg (ip, | |
2458 | ((prev_insn.insn_opcode >> OP_SH_RD) | |
2459 | & OP_MASK_RD), | |
2460 | MIPS_GR_REG)) | |
2461 | || (mips_opts.mips16 | |
2462 | && (((prev_pinfo & MIPS16_INSN_WRITE_X) | |
2463 | && insn_uses_reg (ip, | |
2464 | ((prev_insn.insn_opcode | |
2465 | >> MIPS16OP_SH_RX) | |
2466 | & MIPS16OP_MASK_RX), | |
2467 | MIPS16_REG)) | |
2468 | || ((prev_pinfo & MIPS16_INSN_WRITE_Y) | |
2469 | && insn_uses_reg (ip, | |
2470 | ((prev_insn.insn_opcode | |
2471 | >> MIPS16OP_SH_RY) | |
2472 | & MIPS16OP_MASK_RY), | |
2473 | MIPS16_REG)) | |
2474 | || ((prev_pinfo & MIPS16_INSN_WRITE_Z) | |
2475 | && insn_uses_reg (ip, | |
2476 | ((prev_insn.insn_opcode | |
2477 | >> MIPS16OP_SH_RZ) | |
2478 | & MIPS16OP_MASK_RZ), | |
2479 | MIPS16_REG)) | |
2480 | || ((prev_pinfo & MIPS16_INSN_WRITE_T) | |
2481 | && insn_uses_reg (ip, TREG, MIPS_GR_REG)) | |
2482 | || ((prev_pinfo & MIPS16_INSN_WRITE_31) | |
2483 | && insn_uses_reg (ip, RA, MIPS_GR_REG)) | |
2484 | || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
2485 | && insn_uses_reg (ip, | |
2486 | MIPS16OP_EXTRACT_REG32R (prev_insn. | |
2487 | insn_opcode), | |
2488 | MIPS_GR_REG)))) | |
2489 | /* If the branch writes a register that the previous | |
2490 | instruction sets, we can not swap (we know that | |
2491 | branches write only to RD or to $31). */ | |
2492 | || (! mips_opts.mips16 | |
2493 | && (prev_pinfo & INSN_WRITE_GPR_T) | |
2494 | && (((pinfo & INSN_WRITE_GPR_D) | |
2495 | && (((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT) | |
2496 | == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD))) | |
2497 | || ((pinfo & INSN_WRITE_GPR_31) | |
2498 | && (((prev_insn.insn_opcode >> OP_SH_RT) | |
2499 | & OP_MASK_RT) | |
f9419b05 | 2500 | == RA)))) |
252b5132 RH |
2501 | || (! mips_opts.mips16 |
2502 | && (prev_pinfo & INSN_WRITE_GPR_D) | |
2503 | && (((pinfo & INSN_WRITE_GPR_D) | |
2504 | && (((prev_insn.insn_opcode >> OP_SH_RD) & OP_MASK_RD) | |
2505 | == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD))) | |
2506 | || ((pinfo & INSN_WRITE_GPR_31) | |
2507 | && (((prev_insn.insn_opcode >> OP_SH_RD) | |
2508 | & OP_MASK_RD) | |
f9419b05 | 2509 | == RA)))) |
252b5132 RH |
2510 | || (mips_opts.mips16 |
2511 | && (pinfo & MIPS16_INSN_WRITE_31) | |
2512 | && ((prev_pinfo & MIPS16_INSN_WRITE_31) | |
2513 | || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
2514 | && (MIPS16OP_EXTRACT_REG32R (prev_insn.insn_opcode) | |
2515 | == RA)))) | |
2516 | /* If the branch writes a register that the previous | |
2517 | instruction reads, we can not swap (we know that | |
2518 | branches only write to RD or to $31). */ | |
2519 | || (! mips_opts.mips16 | |
2520 | && (pinfo & INSN_WRITE_GPR_D) | |
2521 | && insn_uses_reg (&prev_insn, | |
2522 | ((ip->insn_opcode >> OP_SH_RD) | |
2523 | & OP_MASK_RD), | |
2524 | MIPS_GR_REG)) | |
2525 | || (! mips_opts.mips16 | |
2526 | && (pinfo & INSN_WRITE_GPR_31) | |
f9419b05 | 2527 | && insn_uses_reg (&prev_insn, RA, MIPS_GR_REG)) |
252b5132 RH |
2528 | || (mips_opts.mips16 |
2529 | && (pinfo & MIPS16_INSN_WRITE_31) | |
2530 | && insn_uses_reg (&prev_insn, RA, MIPS_GR_REG)) | |
2531 | /* If we are generating embedded PIC code, the branch | |
2532 | might be expanded into a sequence which uses $at, so | |
2533 | we can't swap with an instruction which reads it. */ | |
2534 | || (mips_pic == EMBEDDED_PIC | |
2535 | && insn_uses_reg (&prev_insn, AT, MIPS_GR_REG)) | |
2536 | /* If the previous previous instruction has a load | |
2537 | delay, and sets a register that the branch reads, we | |
2538 | can not swap. */ | |
2539 | || (! mips_opts.mips16 | |
9ce8a5dd | 2540 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
bdaaa2e1 | 2541 | /* Itbl support may require additional care here. */ |
252b5132 RH |
2542 | && ((prev_prev_insn.insn_mo->pinfo & INSN_LOAD_COPROC_DELAY) |
2543 | || (! gpr_interlocks | |
2544 | && (prev_prev_insn.insn_mo->pinfo | |
2545 | & INSN_LOAD_MEMORY_DELAY))) | |
2546 | && insn_uses_reg (ip, | |
2547 | ((prev_prev_insn.insn_opcode >> OP_SH_RT) | |
2548 | & OP_MASK_RT), | |
2549 | MIPS_GR_REG)) | |
2550 | /* If one instruction sets a condition code and the | |
2551 | other one uses a condition code, we can not swap. */ | |
2552 | || ((pinfo & INSN_READ_COND_CODE) | |
2553 | && (prev_pinfo & INSN_WRITE_COND_CODE)) | |
2554 | || ((pinfo & INSN_WRITE_COND_CODE) | |
2555 | && (prev_pinfo & INSN_READ_COND_CODE)) | |
2556 | /* If the previous instruction uses the PC, we can not | |
2557 | swap. */ | |
2558 | || (mips_opts.mips16 | |
2559 | && (prev_pinfo & MIPS16_INSN_READ_PC)) | |
2560 | /* If the previous instruction was extended, we can not | |
2561 | swap. */ | |
2562 | || (mips_opts.mips16 && prev_insn_extended) | |
2563 | /* If the previous instruction had a fixup in mips16 | |
2564 | mode, we can not swap. This normally means that the | |
2565 | previous instruction was a 4 byte branch anyhow. */ | |
f6688943 | 2566 | || (mips_opts.mips16 && prev_insn_fixp[0]) |
bdaaa2e1 KH |
2567 | /* If the previous instruction is a sync, sync.l, or |
2568 | sync.p, we can not swap. */ | |
f173e82e | 2569 | || (prev_pinfo & INSN_SYNC)) |
252b5132 RH |
2570 | { |
2571 | /* We could do even better for unconditional branches to | |
2572 | portions of this object file; we could pick up the | |
2573 | instruction at the destination, put it in the delay | |
2574 | slot, and bump the destination address. */ | |
2575 | emit_nop (); | |
2576 | /* Update the previous insn information. */ | |
2577 | prev_prev_insn = *ip; | |
2578 | prev_insn.insn_mo = &dummy_opcode; | |
2579 | } | |
2580 | else | |
2581 | { | |
2582 | /* It looks like we can actually do the swap. */ | |
2583 | if (! mips_opts.mips16) | |
2584 | { | |
2585 | char *prev_f; | |
2586 | char temp[4]; | |
2587 | ||
2588 | prev_f = prev_insn_frag->fr_literal + prev_insn_where; | |
2589 | memcpy (temp, prev_f, 4); | |
2590 | memcpy (prev_f, f, 4); | |
2591 | memcpy (f, temp, 4); | |
f6688943 TS |
2592 | if (prev_insn_fixp[0]) |
2593 | { | |
2594 | prev_insn_fixp[0]->fx_frag = frag_now; | |
2595 | prev_insn_fixp[0]->fx_where = f - frag_now->fr_literal; | |
2596 | } | |
2597 | if (prev_insn_fixp[1]) | |
2598 | { | |
2599 | prev_insn_fixp[1]->fx_frag = frag_now; | |
2600 | prev_insn_fixp[1]->fx_where = f - frag_now->fr_literal; | |
2601 | } | |
2602 | if (prev_insn_fixp[2]) | |
252b5132 | 2603 | { |
f6688943 TS |
2604 | prev_insn_fixp[2]->fx_frag = frag_now; |
2605 | prev_insn_fixp[2]->fx_where = f - frag_now->fr_literal; | |
252b5132 | 2606 | } |
f6688943 | 2607 | if (fixp[0]) |
252b5132 | 2608 | { |
f6688943 TS |
2609 | fixp[0]->fx_frag = prev_insn_frag; |
2610 | fixp[0]->fx_where = prev_insn_where; | |
2611 | } | |
2612 | if (fixp[1]) | |
2613 | { | |
2614 | fixp[1]->fx_frag = prev_insn_frag; | |
2615 | fixp[1]->fx_where = prev_insn_where; | |
2616 | } | |
2617 | if (fixp[2]) | |
2618 | { | |
2619 | fixp[2]->fx_frag = prev_insn_frag; | |
2620 | fixp[2]->fx_where = prev_insn_where; | |
252b5132 RH |
2621 | } |
2622 | } | |
2623 | else | |
2624 | { | |
2625 | char *prev_f; | |
2626 | char temp[2]; | |
2627 | ||
f6688943 TS |
2628 | assert (prev_insn_fixp[0] == NULL); |
2629 | assert (prev_insn_fixp[1] == NULL); | |
2630 | assert (prev_insn_fixp[2] == NULL); | |
252b5132 RH |
2631 | prev_f = prev_insn_frag->fr_literal + prev_insn_where; |
2632 | memcpy (temp, prev_f, 2); | |
2633 | memcpy (prev_f, f, 2); | |
f6688943 | 2634 | if (*reloc_type != BFD_RELOC_MIPS16_JMP) |
252b5132 | 2635 | { |
f6688943 | 2636 | assert (*reloc_type == BFD_RELOC_UNUSED); |
252b5132 RH |
2637 | memcpy (f, temp, 2); |
2638 | } | |
2639 | else | |
2640 | { | |
2641 | memcpy (f, f + 2, 2); | |
2642 | memcpy (f + 2, temp, 2); | |
2643 | } | |
f6688943 TS |
2644 | if (fixp[0]) |
2645 | { | |
2646 | fixp[0]->fx_frag = prev_insn_frag; | |
2647 | fixp[0]->fx_where = prev_insn_where; | |
2648 | } | |
2649 | if (fixp[1]) | |
2650 | { | |
2651 | fixp[1]->fx_frag = prev_insn_frag; | |
2652 | fixp[1]->fx_where = prev_insn_where; | |
2653 | } | |
2654 | if (fixp[2]) | |
252b5132 | 2655 | { |
f6688943 TS |
2656 | fixp[2]->fx_frag = prev_insn_frag; |
2657 | fixp[2]->fx_where = prev_insn_where; | |
252b5132 RH |
2658 | } |
2659 | } | |
2660 | ||
2661 | /* Update the previous insn information; leave prev_insn | |
2662 | unchanged. */ | |
2663 | prev_prev_insn = *ip; | |
2664 | } | |
2665 | prev_insn_is_delay_slot = 1; | |
2666 | ||
2667 | /* If that was an unconditional branch, forget the previous | |
2668 | insn information. */ | |
2669 | if (pinfo & INSN_UNCOND_BRANCH_DELAY) | |
2670 | { | |
2671 | prev_prev_insn.insn_mo = &dummy_opcode; | |
2672 | prev_insn.insn_mo = &dummy_opcode; | |
2673 | } | |
2674 | ||
f6688943 TS |
2675 | prev_insn_fixp[0] = NULL; |
2676 | prev_insn_fixp[1] = NULL; | |
2677 | prev_insn_fixp[2] = NULL; | |
2678 | prev_insn_reloc_type[0] = BFD_RELOC_UNUSED; | |
2679 | prev_insn_reloc_type[1] = BFD_RELOC_UNUSED; | |
2680 | prev_insn_reloc_type[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
2681 | prev_insn_extended = 0; |
2682 | } | |
2683 | else if (pinfo & INSN_COND_BRANCH_LIKELY) | |
2684 | { | |
2685 | /* We don't yet optimize a branch likely. What we should do | |
2686 | is look at the target, copy the instruction found there | |
2687 | into the delay slot, and increment the branch to jump to | |
2688 | the next instruction. */ | |
2689 | emit_nop (); | |
2690 | /* Update the previous insn information. */ | |
2691 | prev_prev_insn = *ip; | |
2692 | prev_insn.insn_mo = &dummy_opcode; | |
f6688943 TS |
2693 | prev_insn_fixp[0] = NULL; |
2694 | prev_insn_fixp[1] = NULL; | |
2695 | prev_insn_fixp[2] = NULL; | |
2696 | prev_insn_reloc_type[0] = BFD_RELOC_UNUSED; | |
2697 | prev_insn_reloc_type[1] = BFD_RELOC_UNUSED; | |
2698 | prev_insn_reloc_type[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
2699 | prev_insn_extended = 0; |
2700 | } | |
2701 | else | |
2702 | { | |
2703 | /* Update the previous insn information. */ | |
2704 | if (nops > 0) | |
2705 | prev_prev_insn.insn_mo = &dummy_opcode; | |
2706 | else | |
2707 | prev_prev_insn = prev_insn; | |
2708 | prev_insn = *ip; | |
2709 | ||
2710 | /* Any time we see a branch, we always fill the delay slot | |
2711 | immediately; since this insn is not a branch, we know it | |
2712 | is not in a delay slot. */ | |
2713 | prev_insn_is_delay_slot = 0; | |
2714 | ||
f6688943 TS |
2715 | prev_insn_fixp[0] = fixp[0]; |
2716 | prev_insn_fixp[1] = fixp[1]; | |
2717 | prev_insn_fixp[2] = fixp[2]; | |
2718 | prev_insn_reloc_type[0] = reloc_type[0]; | |
2719 | prev_insn_reloc_type[1] = reloc_type[1]; | |
2720 | prev_insn_reloc_type[2] = reloc_type[2]; | |
252b5132 RH |
2721 | if (mips_opts.mips16) |
2722 | prev_insn_extended = (ip->use_extend | |
f6688943 | 2723 | || *reloc_type > BFD_RELOC_UNUSED); |
252b5132 RH |
2724 | } |
2725 | ||
2726 | prev_prev_insn_unreordered = prev_insn_unreordered; | |
2727 | prev_insn_unreordered = 0; | |
2728 | prev_insn_frag = frag_now; | |
2729 | prev_insn_where = f - frag_now->fr_literal; | |
2730 | prev_insn_valid = 1; | |
2731 | } | |
2732 | else if (place == NULL) | |
2733 | { | |
2734 | /* We need to record a bit of information even when we are not | |
2735 | reordering, in order to determine the base address for mips16 | |
2736 | PC relative relocs. */ | |
2737 | prev_prev_insn = prev_insn; | |
2738 | prev_insn = *ip; | |
f6688943 TS |
2739 | prev_insn_reloc_type[0] = reloc_type[0]; |
2740 | prev_insn_reloc_type[1] = reloc_type[1]; | |
2741 | prev_insn_reloc_type[2] = reloc_type[2]; | |
252b5132 RH |
2742 | prev_prev_insn_unreordered = prev_insn_unreordered; |
2743 | prev_insn_unreordered = 1; | |
2744 | } | |
2745 | ||
2746 | /* We just output an insn, so the next one doesn't have a label. */ | |
2747 | mips_clear_insn_labels (); | |
252b5132 RH |
2748 | } |
2749 | ||
2750 | /* This function forgets that there was any previous instruction or | |
2751 | label. If PRESERVE is non-zero, it remembers enough information to | |
bdaaa2e1 | 2752 | know whether nops are needed before a noreorder section. */ |
252b5132 RH |
2753 | |
2754 | static void | |
2755 | mips_no_prev_insn (preserve) | |
2756 | int preserve; | |
2757 | { | |
2758 | if (! preserve) | |
2759 | { | |
2760 | prev_insn.insn_mo = &dummy_opcode; | |
2761 | prev_prev_insn.insn_mo = &dummy_opcode; | |
2762 | prev_nop_frag = NULL; | |
2763 | prev_nop_frag_holds = 0; | |
2764 | prev_nop_frag_required = 0; | |
2765 | prev_nop_frag_since = 0; | |
2766 | } | |
2767 | prev_insn_valid = 0; | |
2768 | prev_insn_is_delay_slot = 0; | |
2769 | prev_insn_unreordered = 0; | |
2770 | prev_insn_extended = 0; | |
f6688943 TS |
2771 | prev_insn_reloc_type[0] = BFD_RELOC_UNUSED; |
2772 | prev_insn_reloc_type[1] = BFD_RELOC_UNUSED; | |
2773 | prev_insn_reloc_type[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
2774 | prev_prev_insn_unreordered = 0; |
2775 | mips_clear_insn_labels (); | |
2776 | } | |
2777 | ||
2778 | /* This function must be called whenever we turn on noreorder or emit | |
2779 | something other than instructions. It inserts any NOPS which might | |
2780 | be needed by the previous instruction, and clears the information | |
2781 | kept for the previous instructions. The INSNS parameter is true if | |
bdaaa2e1 | 2782 | instructions are to follow. */ |
252b5132 RH |
2783 | |
2784 | static void | |
2785 | mips_emit_delays (insns) | |
b34976b6 | 2786 | bfd_boolean insns; |
252b5132 RH |
2787 | { |
2788 | if (! mips_opts.noreorder) | |
2789 | { | |
2790 | int nops; | |
2791 | ||
2792 | nops = 0; | |
2793 | if ((! mips_opts.mips16 | |
9ce8a5dd | 2794 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 RH |
2795 | && (! cop_interlocks |
2796 | && (prev_insn.insn_mo->pinfo | |
2797 | & (INSN_LOAD_COPROC_DELAY | |
2798 | | INSN_COPROC_MOVE_DELAY | |
2799 | | INSN_WRITE_COND_CODE)))) | |
2800 | || (! hilo_interlocks | |
2801 | && (prev_insn.insn_mo->pinfo | |
2802 | & (INSN_READ_LO | |
2803 | | INSN_READ_HI))) | |
2804 | || (! mips_opts.mips16 | |
2805 | && ! gpr_interlocks | |
bdaaa2e1 | 2806 | && (prev_insn.insn_mo->pinfo |
252b5132 RH |
2807 | & INSN_LOAD_MEMORY_DELAY)) |
2808 | || (! mips_opts.mips16 | |
e7af610e | 2809 | && mips_opts.isa == ISA_MIPS1 |
252b5132 RH |
2810 | && (prev_insn.insn_mo->pinfo |
2811 | & INSN_COPROC_MEMORY_DELAY))) | |
2812 | { | |
beae10d5 | 2813 | /* Itbl support may require additional care here. */ |
252b5132 RH |
2814 | ++nops; |
2815 | if ((! mips_opts.mips16 | |
9ce8a5dd | 2816 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 RH |
2817 | && (! cop_interlocks |
2818 | && prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)) | |
2819 | || (! hilo_interlocks | |
2820 | && ((prev_insn.insn_mo->pinfo & INSN_READ_HI) | |
2821 | || (prev_insn.insn_mo->pinfo & INSN_READ_LO)))) | |
2822 | ++nops; | |
2823 | ||
2824 | if (prev_insn_unreordered) | |
2825 | nops = 0; | |
2826 | } | |
2827 | else if ((! mips_opts.mips16 | |
9ce8a5dd | 2828 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 RH |
2829 | && (! cop_interlocks |
2830 | && prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)) | |
2831 | || (! hilo_interlocks | |
2832 | && ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI) | |
2833 | || (prev_prev_insn.insn_mo->pinfo & INSN_READ_LO)))) | |
2834 | { | |
beae10d5 | 2835 | /* Itbl support may require additional care here. */ |
252b5132 RH |
2836 | if (! prev_prev_insn_unreordered) |
2837 | ++nops; | |
2838 | } | |
2839 | ||
60b63b72 RS |
2840 | if (mips_fix_4122_bugs && prev_insn.insn_mo->name) |
2841 | { | |
2842 | int min_nops = 0; | |
2843 | const char *pn = prev_insn.insn_mo->name; | |
2844 | if (strncmp(pn, "macc", 4) == 0 | |
2845 | || strncmp(pn, "dmacc", 5) == 0 | |
2846 | || strncmp(pn, "dmult", 5) == 0) | |
2847 | { | |
2848 | min_nops = 1; | |
2849 | } | |
2850 | if (nops < min_nops) | |
2851 | nops = min_nops; | |
2852 | } | |
2853 | ||
252b5132 RH |
2854 | if (nops > 0) |
2855 | { | |
2856 | struct insn_label_list *l; | |
2857 | ||
2858 | if (insns) | |
2859 | { | |
2860 | /* Record the frag which holds the nop instructions, so | |
2861 | that we can remove them if we don't need them. */ | |
2862 | frag_grow (mips_opts.mips16 ? nops * 2 : nops * 4); | |
2863 | prev_nop_frag = frag_now; | |
2864 | prev_nop_frag_holds = nops; | |
2865 | prev_nop_frag_required = 0; | |
2866 | prev_nop_frag_since = 0; | |
2867 | } | |
2868 | ||
2869 | for (; nops > 0; --nops) | |
2870 | emit_nop (); | |
2871 | ||
2872 | if (insns) | |
2873 | { | |
2874 | /* Move on to a new frag, so that it is safe to simply | |
bdaaa2e1 | 2875 | decrease the size of prev_nop_frag. */ |
252b5132 RH |
2876 | frag_wane (frag_now); |
2877 | frag_new (0); | |
2878 | } | |
2879 | ||
2880 | for (l = insn_labels; l != NULL; l = l->next) | |
2881 | { | |
98aa84af AM |
2882 | valueT val; |
2883 | ||
252b5132 | 2884 | assert (S_GET_SEGMENT (l->label) == now_seg); |
49309057 | 2885 | symbol_set_frag (l->label, frag_now); |
98aa84af | 2886 | val = (valueT) frag_now_fix (); |
252b5132 RH |
2887 | /* mips16 text labels are stored as odd. */ |
2888 | if (mips_opts.mips16) | |
f9419b05 | 2889 | ++val; |
98aa84af | 2890 | S_SET_VALUE (l->label, val); |
252b5132 RH |
2891 | } |
2892 | } | |
2893 | } | |
2894 | ||
2895 | /* Mark instruction labels in mips16 mode. */ | |
f9419b05 | 2896 | if (insns) |
252b5132 RH |
2897 | mips16_mark_labels (); |
2898 | ||
2899 | mips_no_prev_insn (insns); | |
2900 | } | |
2901 | ||
2902 | /* Build an instruction created by a macro expansion. This is passed | |
2903 | a pointer to the count of instructions created so far, an | |
2904 | expression, the name of the instruction to build, an operand format | |
2905 | string, and corresponding arguments. */ | |
2906 | ||
2907 | #ifdef USE_STDARG | |
2908 | static void | |
2909 | macro_build (char *place, | |
2910 | int *counter, | |
2911 | expressionS * ep, | |
2912 | const char *name, | |
2913 | const char *fmt, | |
2914 | ...) | |
2915 | #else | |
2916 | static void | |
2917 | macro_build (place, counter, ep, name, fmt, va_alist) | |
2918 | char *place; | |
2919 | int *counter; | |
2920 | expressionS *ep; | |
2921 | const char *name; | |
2922 | const char *fmt; | |
2923 | va_dcl | |
2924 | #endif | |
2925 | { | |
2926 | struct mips_cl_insn insn; | |
f6688943 | 2927 | bfd_reloc_code_real_type r[3]; |
252b5132 | 2928 | va_list args; |
252b5132 RH |
2929 | |
2930 | #ifdef USE_STDARG | |
2931 | va_start (args, fmt); | |
2932 | #else | |
2933 | va_start (args); | |
2934 | #endif | |
2935 | ||
2936 | /* | |
2937 | * If the macro is about to expand into a second instruction, | |
2938 | * print a warning if needed. We need to pass ip as a parameter | |
2939 | * to generate a better warning message here... | |
2940 | */ | |
2941 | if (mips_opts.warn_about_macros && place == NULL && *counter == 1) | |
2942 | as_warn (_("Macro instruction expanded into multiple instructions")); | |
2943 | ||
80cc45a5 EC |
2944 | /* |
2945 | * If the macro is about to expand into a second instruction, | |
2946 | * and it is in a delay slot, print a warning. | |
2947 | */ | |
2948 | if (place == NULL | |
2949 | && *counter == 1 | |
2950 | && mips_opts.noreorder | |
2951 | && (prev_prev_insn.insn_mo->pinfo | |
2952 | & (INSN_UNCOND_BRANCH_DELAY | INSN_COND_BRANCH_DELAY | |
2b2e39bf | 2953 | | INSN_COND_BRANCH_LIKELY)) != 0) |
80cc45a5 EC |
2954 | as_warn (_("Macro instruction expanded into multiple instructions in a branch delay slot")); |
2955 | ||
252b5132 | 2956 | if (place == NULL) |
f9419b05 | 2957 | ++*counter; /* bump instruction counter */ |
252b5132 RH |
2958 | |
2959 | if (mips_opts.mips16) | |
2960 | { | |
2961 | mips16_macro_build (place, counter, ep, name, fmt, args); | |
2962 | va_end (args); | |
2963 | return; | |
2964 | } | |
2965 | ||
f6688943 TS |
2966 | r[0] = BFD_RELOC_UNUSED; |
2967 | r[1] = BFD_RELOC_UNUSED; | |
2968 | r[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
2969 | insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name); |
2970 | assert (insn.insn_mo); | |
2971 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
2972 | ||
2973 | /* Search until we get a match for NAME. */ | |
2974 | while (1) | |
2975 | { | |
b34976b6 | 2976 | /* It is assumed here that macros will never generate |
deec1734 | 2977 | MDMX or MIPS-3D instructions. */ |
252b5132 RH |
2978 | if (strcmp (fmt, insn.insn_mo->args) == 0 |
2979 | && insn.insn_mo->pinfo != INSN_MACRO | |
aec421e0 TS |
2980 | && OPCODE_IS_MEMBER (insn.insn_mo, |
2981 | (mips_opts.isa | |
3396de36 | 2982 | | (file_ase_mips16 ? INSN_MIPS16 : 0)), |
aec421e0 | 2983 | mips_arch) |
ec68c924 | 2984 | && (mips_arch != CPU_R4650 || (insn.insn_mo->pinfo & FP_D) == 0)) |
252b5132 RH |
2985 | break; |
2986 | ||
2987 | ++insn.insn_mo; | |
2988 | assert (insn.insn_mo->name); | |
2989 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
2990 | } | |
2991 | ||
2992 | insn.insn_opcode = insn.insn_mo->match; | |
2993 | for (;;) | |
2994 | { | |
2995 | switch (*fmt++) | |
2996 | { | |
2997 | case '\0': | |
2998 | break; | |
2999 | ||
3000 | case ',': | |
3001 | case '(': | |
3002 | case ')': | |
3003 | continue; | |
3004 | ||
3005 | case 't': | |
3006 | case 'w': | |
3007 | case 'E': | |
38487616 | 3008 | insn.insn_opcode |= va_arg (args, int) << OP_SH_RT; |
252b5132 RH |
3009 | continue; |
3010 | ||
3011 | case 'c': | |
38487616 TS |
3012 | insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE; |
3013 | continue; | |
3014 | ||
252b5132 RH |
3015 | case 'T': |
3016 | case 'W': | |
38487616 | 3017 | insn.insn_opcode |= va_arg (args, int) << OP_SH_FT; |
252b5132 RH |
3018 | continue; |
3019 | ||
3020 | case 'd': | |
3021 | case 'G': | |
af7ee8bf | 3022 | case 'K': |
38487616 | 3023 | insn.insn_opcode |= va_arg (args, int) << OP_SH_RD; |
252b5132 RH |
3024 | continue; |
3025 | ||
4372b673 NC |
3026 | case 'U': |
3027 | { | |
3028 | int tmp = va_arg (args, int); | |
3029 | ||
38487616 TS |
3030 | insn.insn_opcode |= tmp << OP_SH_RT; |
3031 | insn.insn_opcode |= tmp << OP_SH_RD; | |
beae10d5 | 3032 | continue; |
4372b673 NC |
3033 | } |
3034 | ||
252b5132 RH |
3035 | case 'V': |
3036 | case 'S': | |
38487616 | 3037 | insn.insn_opcode |= va_arg (args, int) << OP_SH_FS; |
252b5132 RH |
3038 | continue; |
3039 | ||
3040 | case 'z': | |
3041 | continue; | |
3042 | ||
3043 | case '<': | |
38487616 | 3044 | insn.insn_opcode |= va_arg (args, int) << OP_SH_SHAMT; |
252b5132 RH |
3045 | continue; |
3046 | ||
3047 | case 'D': | |
38487616 | 3048 | insn.insn_opcode |= va_arg (args, int) << OP_SH_FD; |
252b5132 RH |
3049 | continue; |
3050 | ||
3051 | case 'B': | |
38487616 | 3052 | insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE20; |
252b5132 RH |
3053 | continue; |
3054 | ||
4372b673 | 3055 | case 'J': |
38487616 | 3056 | insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE19; |
4372b673 NC |
3057 | continue; |
3058 | ||
252b5132 | 3059 | case 'q': |
38487616 | 3060 | insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE2; |
252b5132 RH |
3061 | continue; |
3062 | ||
3063 | case 'b': | |
3064 | case 's': | |
3065 | case 'r': | |
3066 | case 'v': | |
38487616 | 3067 | insn.insn_opcode |= va_arg (args, int) << OP_SH_RS; |
252b5132 RH |
3068 | continue; |
3069 | ||
3070 | case 'i': | |
3071 | case 'j': | |
3072 | case 'o': | |
f6688943 | 3073 | *r = (bfd_reloc_code_real_type) va_arg (args, int); |
cdf6fd85 | 3074 | assert (*r == BFD_RELOC_GPREL16 |
f6688943 TS |
3075 | || *r == BFD_RELOC_MIPS_LITERAL |
3076 | || *r == BFD_RELOC_MIPS_HIGHER | |
3077 | || *r == BFD_RELOC_HI16_S | |
3078 | || *r == BFD_RELOC_LO16 | |
3079 | || *r == BFD_RELOC_MIPS_GOT16 | |
3080 | || *r == BFD_RELOC_MIPS_CALL16 | |
438c16b8 TS |
3081 | || *r == BFD_RELOC_MIPS_GOT_DISP |
3082 | || *r == BFD_RELOC_MIPS_GOT_PAGE | |
3083 | || *r == BFD_RELOC_MIPS_GOT_OFST | |
f6688943 TS |
3084 | || *r == BFD_RELOC_MIPS_GOT_LO16 |
3085 | || *r == BFD_RELOC_MIPS_CALL_LO16 | |
252b5132 | 3086 | || (ep->X_op == O_subtract |
f6688943 | 3087 | && *r == BFD_RELOC_PCREL_LO16)); |
252b5132 RH |
3088 | continue; |
3089 | ||
3090 | case 'u': | |
f6688943 | 3091 | *r = (bfd_reloc_code_real_type) va_arg (args, int); |
252b5132 RH |
3092 | assert (ep != NULL |
3093 | && (ep->X_op == O_constant | |
3094 | || (ep->X_op == O_symbol | |
f6688943 TS |
3095 | && (*r == BFD_RELOC_MIPS_HIGHEST |
3096 | || *r == BFD_RELOC_HI16_S | |
3097 | || *r == BFD_RELOC_HI16 | |
3098 | || *r == BFD_RELOC_GPREL16 | |
3099 | || *r == BFD_RELOC_MIPS_GOT_HI16 | |
3100 | || *r == BFD_RELOC_MIPS_CALL_HI16)) | |
252b5132 | 3101 | || (ep->X_op == O_subtract |
f6688943 | 3102 | && *r == BFD_RELOC_PCREL_HI16_S))); |
252b5132 RH |
3103 | continue; |
3104 | ||
3105 | case 'p': | |
3106 | assert (ep != NULL); | |
3107 | /* | |
3108 | * This allows macro() to pass an immediate expression for | |
3109 | * creating short branches without creating a symbol. | |
0b25d3e6 AO |
3110 | * Note that the expression still might come from the assembly |
3111 | * input, in which case the value is not checked for range nor | |
3112 | * is a relocation entry generated (yuck). | |
252b5132 RH |
3113 | */ |
3114 | if (ep->X_op == O_constant) | |
3115 | { | |
3116 | insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff; | |
3117 | ep = NULL; | |
3118 | } | |
3119 | else | |
0b25d3e6 | 3120 | *r = BFD_RELOC_16_PCREL_S2; |
252b5132 RH |
3121 | continue; |
3122 | ||
3123 | case 'a': | |
3124 | assert (ep != NULL); | |
f6688943 | 3125 | *r = BFD_RELOC_MIPS_JMP; |
252b5132 RH |
3126 | continue; |
3127 | ||
3128 | case 'C': | |
3129 | insn.insn_opcode |= va_arg (args, unsigned long); | |
3130 | continue; | |
3131 | ||
3132 | default: | |
3133 | internalError (); | |
3134 | } | |
3135 | break; | |
3136 | } | |
3137 | va_end (args); | |
f6688943 | 3138 | assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
252b5132 | 3139 | |
5e0116d5 | 3140 | append_insn (place, &insn, ep, r); |
252b5132 RH |
3141 | } |
3142 | ||
3143 | static void | |
3144 | mips16_macro_build (place, counter, ep, name, fmt, args) | |
3145 | char *place; | |
43841e91 | 3146 | int *counter ATTRIBUTE_UNUSED; |
252b5132 RH |
3147 | expressionS *ep; |
3148 | const char *name; | |
3149 | const char *fmt; | |
3150 | va_list args; | |
3151 | { | |
3152 | struct mips_cl_insn insn; | |
f6688943 TS |
3153 | bfd_reloc_code_real_type r[3] |
3154 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 3155 | |
252b5132 RH |
3156 | insn.insn_mo = (struct mips_opcode *) hash_find (mips16_op_hash, name); |
3157 | assert (insn.insn_mo); | |
3158 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
3159 | ||
3160 | while (strcmp (fmt, insn.insn_mo->args) != 0 | |
3161 | || insn.insn_mo->pinfo == INSN_MACRO) | |
3162 | { | |
3163 | ++insn.insn_mo; | |
3164 | assert (insn.insn_mo->name); | |
3165 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
3166 | } | |
3167 | ||
3168 | insn.insn_opcode = insn.insn_mo->match; | |
b34976b6 | 3169 | insn.use_extend = FALSE; |
252b5132 RH |
3170 | |
3171 | for (;;) | |
3172 | { | |
3173 | int c; | |
3174 | ||
3175 | c = *fmt++; | |
3176 | switch (c) | |
3177 | { | |
3178 | case '\0': | |
3179 | break; | |
3180 | ||
3181 | case ',': | |
3182 | case '(': | |
3183 | case ')': | |
3184 | continue; | |
3185 | ||
3186 | case 'y': | |
3187 | case 'w': | |
3188 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RY; | |
3189 | continue; | |
3190 | ||
3191 | case 'x': | |
3192 | case 'v': | |
3193 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RX; | |
3194 | continue; | |
3195 | ||
3196 | case 'z': | |
3197 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RZ; | |
3198 | continue; | |
3199 | ||
3200 | case 'Z': | |
3201 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_MOVE32Z; | |
3202 | continue; | |
3203 | ||
3204 | case '0': | |
3205 | case 'S': | |
3206 | case 'P': | |
3207 | case 'R': | |
3208 | continue; | |
3209 | ||
3210 | case 'X': | |
3211 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_REGR32; | |
3212 | continue; | |
3213 | ||
3214 | case 'Y': | |
3215 | { | |
3216 | int regno; | |
3217 | ||
3218 | regno = va_arg (args, int); | |
3219 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); | |
3220 | insn.insn_opcode |= regno << MIPS16OP_SH_REG32R; | |
3221 | } | |
3222 | continue; | |
3223 | ||
3224 | case '<': | |
3225 | case '>': | |
3226 | case '4': | |
3227 | case '5': | |
3228 | case 'H': | |
3229 | case 'W': | |
3230 | case 'D': | |
3231 | case 'j': | |
3232 | case '8': | |
3233 | case 'V': | |
3234 | case 'C': | |
3235 | case 'U': | |
3236 | case 'k': | |
3237 | case 'K': | |
3238 | case 'p': | |
3239 | case 'q': | |
3240 | { | |
3241 | assert (ep != NULL); | |
3242 | ||
3243 | if (ep->X_op != O_constant) | |
874e8986 | 3244 | *r = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
3245 | else |
3246 | { | |
b34976b6 AM |
3247 | mips16_immed (NULL, 0, c, ep->X_add_number, FALSE, FALSE, |
3248 | FALSE, &insn.insn_opcode, &insn.use_extend, | |
c4e7957c | 3249 | &insn.extend); |
252b5132 | 3250 | ep = NULL; |
f6688943 | 3251 | *r = BFD_RELOC_UNUSED; |
252b5132 RH |
3252 | } |
3253 | } | |
3254 | continue; | |
3255 | ||
3256 | case '6': | |
3257 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_IMM6; | |
3258 | continue; | |
3259 | } | |
3260 | ||
3261 | break; | |
3262 | } | |
3263 | ||
f6688943 | 3264 | assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
252b5132 | 3265 | |
5e0116d5 | 3266 | append_insn (place, &insn, ep, r); |
252b5132 RH |
3267 | } |
3268 | ||
438c16b8 TS |
3269 | /* |
3270 | * Generate a "jalr" instruction with a relocation hint to the called | |
3271 | * function. This occurs in NewABI PIC code. | |
3272 | */ | |
3273 | static void | |
3274 | macro_build_jalr (icnt, ep) | |
3275 | int icnt; | |
3276 | expressionS *ep; | |
3277 | { | |
f21f8242 | 3278 | char *f; |
b34976b6 | 3279 | |
438c16b8 | 3280 | if (HAVE_NEWABI) |
f21f8242 AO |
3281 | { |
3282 | frag_grow (4); | |
3283 | f = frag_more (0); | |
3284 | } | |
438c16b8 TS |
3285 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "jalr", "d,s", |
3286 | RA, PIC_CALL_REG); | |
3287 | if (HAVE_NEWABI) | |
f21f8242 | 3288 | fix_new_exp (frag_now, f - frag_now->fr_literal, |
b34976b6 | 3289 | 0, ep, FALSE, BFD_RELOC_MIPS_JALR); |
438c16b8 TS |
3290 | } |
3291 | ||
252b5132 RH |
3292 | /* |
3293 | * Generate a "lui" instruction. | |
3294 | */ | |
3295 | static void | |
3296 | macro_build_lui (place, counter, ep, regnum) | |
3297 | char *place; | |
3298 | int *counter; | |
3299 | expressionS *ep; | |
3300 | int regnum; | |
3301 | { | |
3302 | expressionS high_expr; | |
3303 | struct mips_cl_insn insn; | |
f6688943 TS |
3304 | bfd_reloc_code_real_type r[3] |
3305 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
5a38dc70 AM |
3306 | const char *name = "lui"; |
3307 | const char *fmt = "t,u"; | |
252b5132 RH |
3308 | |
3309 | assert (! mips_opts.mips16); | |
3310 | ||
3311 | if (place == NULL) | |
3312 | high_expr = *ep; | |
3313 | else | |
3314 | { | |
3315 | high_expr.X_op = O_constant; | |
3316 | high_expr.X_add_number = ep->X_add_number; | |
3317 | } | |
3318 | ||
3319 | if (high_expr.X_op == O_constant) | |
3320 | { | |
3321 | /* we can compute the instruction now without a relocation entry */ | |
e7d556df TS |
3322 | high_expr.X_add_number = ((high_expr.X_add_number + 0x8000) |
3323 | >> 16) & 0xffff; | |
f6688943 | 3324 | *r = BFD_RELOC_UNUSED; |
252b5132 | 3325 | } |
78e1bb40 | 3326 | else |
252b5132 RH |
3327 | { |
3328 | assert (ep->X_op == O_symbol); | |
3329 | /* _gp_disp is a special case, used from s_cpload. */ | |
3330 | assert (mips_pic == NO_PIC | |
78e1bb40 AO |
3331 | || (! HAVE_NEWABI |
3332 | && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0)); | |
f6688943 | 3333 | *r = BFD_RELOC_HI16_S; |
252b5132 RH |
3334 | } |
3335 | ||
3336 | /* | |
3337 | * If the macro is about to expand into a second instruction, | |
3338 | * print a warning if needed. We need to pass ip as a parameter | |
3339 | * to generate a better warning message here... | |
3340 | */ | |
3341 | if (mips_opts.warn_about_macros && place == NULL && *counter == 1) | |
3342 | as_warn (_("Macro instruction expanded into multiple instructions")); | |
3343 | ||
3344 | if (place == NULL) | |
f9419b05 | 3345 | ++*counter; /* bump instruction counter */ |
252b5132 RH |
3346 | |
3347 | insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name); | |
3348 | assert (insn.insn_mo); | |
3349 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
3350 | assert (strcmp (fmt, insn.insn_mo->args) == 0); | |
3351 | ||
3352 | insn.insn_opcode = insn.insn_mo->match | (regnum << OP_SH_RT); | |
f6688943 | 3353 | if (*r == BFD_RELOC_UNUSED) |
252b5132 RH |
3354 | { |
3355 | insn.insn_opcode |= high_expr.X_add_number; | |
5e0116d5 | 3356 | append_insn (place, &insn, NULL, r); |
252b5132 RH |
3357 | } |
3358 | else | |
5e0116d5 | 3359 | append_insn (place, &insn, &high_expr, r); |
252b5132 RH |
3360 | } |
3361 | ||
885add95 CD |
3362 | /* Generate a sequence of instructions to do a load or store from a constant |
3363 | offset off of a base register (breg) into/from a target register (treg), | |
3364 | using AT if necessary. */ | |
3365 | static void | |
3366 | macro_build_ldst_constoffset (place, counter, ep, op, treg, breg) | |
3367 | char *place; | |
3368 | int *counter; | |
3369 | expressionS *ep; | |
3370 | const char *op; | |
3371 | int treg, breg; | |
3372 | { | |
3373 | assert (ep->X_op == O_constant); | |
3374 | ||
3375 | /* Right now, this routine can only handle signed 32-bit contants. */ | |
3376 | if (! IS_SEXT_32BIT_NUM(ep->X_add_number)) | |
3377 | as_warn (_("operand overflow")); | |
3378 | ||
3379 | if (IS_SEXT_16BIT_NUM(ep->X_add_number)) | |
3380 | { | |
3381 | /* Signed 16-bit offset will fit in the op. Easy! */ | |
3382 | macro_build (place, counter, ep, op, "t,o(b)", treg, | |
3383 | (int) BFD_RELOC_LO16, breg); | |
3384 | } | |
3385 | else | |
3386 | { | |
3387 | /* 32-bit offset, need multiple instructions and AT, like: | |
3388 | lui $tempreg,const_hi (BFD_RELOC_HI16_S) | |
3389 | addu $tempreg,$tempreg,$breg | |
3390 | <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16) | |
3391 | to handle the complete offset. */ | |
3392 | macro_build_lui (place, counter, ep, AT); | |
3393 | if (place != NULL) | |
3394 | place += 4; | |
3395 | macro_build (place, counter, (expressionS *) NULL, | |
3396 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", | |
3397 | "d,v,t", AT, AT, breg); | |
3398 | if (place != NULL) | |
3399 | place += 4; | |
3400 | macro_build (place, counter, ep, op, "t,o(b)", treg, | |
3401 | (int) BFD_RELOC_LO16, AT); | |
3402 | ||
3403 | if (mips_opts.noat) | |
3404 | as_warn (_("Macro used $at after \".set noat\"")); | |
3405 | } | |
3406 | } | |
3407 | ||
252b5132 RH |
3408 | /* set_at() |
3409 | * Generates code to set the $at register to true (one) | |
3410 | * if reg is less than the immediate expression. | |
3411 | */ | |
3412 | static void | |
3413 | set_at (counter, reg, unsignedp) | |
3414 | int *counter; | |
3415 | int reg; | |
3416 | int unsignedp; | |
3417 | { | |
3418 | if (imm_expr.X_op == O_constant | |
3419 | && imm_expr.X_add_number >= -0x8000 | |
3420 | && imm_expr.X_add_number < 0x8000) | |
3421 | macro_build ((char *) NULL, counter, &imm_expr, | |
3422 | unsignedp ? "sltiu" : "slti", | |
3423 | "t,r,j", AT, reg, (int) BFD_RELOC_LO16); | |
3424 | else | |
3425 | { | |
4d34fb5f | 3426 | load_register (counter, AT, &imm_expr, HAVE_64BIT_GPRS); |
2396cfb9 | 3427 | macro_build ((char *) NULL, counter, (expressionS *) NULL, |
252b5132 RH |
3428 | unsignedp ? "sltu" : "slt", |
3429 | "d,v,t", AT, reg, AT); | |
3430 | } | |
3431 | } | |
3432 | ||
3433 | /* Warn if an expression is not a constant. */ | |
3434 | ||
3435 | static void | |
3436 | check_absolute_expr (ip, ex) | |
3437 | struct mips_cl_insn *ip; | |
3438 | expressionS *ex; | |
3439 | { | |
3440 | if (ex->X_op == O_big) | |
3441 | as_bad (_("unsupported large constant")); | |
3442 | else if (ex->X_op != O_constant) | |
3443 | as_bad (_("Instruction %s requires absolute expression"), ip->insn_mo->name); | |
3444 | } | |
3445 | ||
3446 | /* Count the leading zeroes by performing a binary chop. This is a | |
3447 | bulky bit of source, but performance is a LOT better for the | |
3448 | majority of values than a simple loop to count the bits: | |
3449 | for (lcnt = 0; (lcnt < 32); lcnt++) | |
3450 | if ((v) & (1 << (31 - lcnt))) | |
3451 | break; | |
3452 | However it is not code size friendly, and the gain will drop a bit | |
3453 | on certain cached systems. | |
3454 | */ | |
3455 | #define COUNT_TOP_ZEROES(v) \ | |
3456 | (((v) & ~0xffff) == 0 \ | |
3457 | ? ((v) & ~0xff) == 0 \ | |
3458 | ? ((v) & ~0xf) == 0 \ | |
3459 | ? ((v) & ~0x3) == 0 \ | |
3460 | ? ((v) & ~0x1) == 0 \ | |
3461 | ? !(v) \ | |
3462 | ? 32 \ | |
3463 | : 31 \ | |
3464 | : 30 \ | |
3465 | : ((v) & ~0x7) == 0 \ | |
3466 | ? 29 \ | |
3467 | : 28 \ | |
3468 | : ((v) & ~0x3f) == 0 \ | |
3469 | ? ((v) & ~0x1f) == 0 \ | |
3470 | ? 27 \ | |
3471 | : 26 \ | |
3472 | : ((v) & ~0x7f) == 0 \ | |
3473 | ? 25 \ | |
3474 | : 24 \ | |
3475 | : ((v) & ~0xfff) == 0 \ | |
3476 | ? ((v) & ~0x3ff) == 0 \ | |
3477 | ? ((v) & ~0x1ff) == 0 \ | |
3478 | ? 23 \ | |
3479 | : 22 \ | |
3480 | : ((v) & ~0x7ff) == 0 \ | |
3481 | ? 21 \ | |
3482 | : 20 \ | |
3483 | : ((v) & ~0x3fff) == 0 \ | |
3484 | ? ((v) & ~0x1fff) == 0 \ | |
3485 | ? 19 \ | |
3486 | : 18 \ | |
3487 | : ((v) & ~0x7fff) == 0 \ | |
3488 | ? 17 \ | |
3489 | : 16 \ | |
3490 | : ((v) & ~0xffffff) == 0 \ | |
3491 | ? ((v) & ~0xfffff) == 0 \ | |
3492 | ? ((v) & ~0x3ffff) == 0 \ | |
3493 | ? ((v) & ~0x1ffff) == 0 \ | |
3494 | ? 15 \ | |
3495 | : 14 \ | |
3496 | : ((v) & ~0x7ffff) == 0 \ | |
3497 | ? 13 \ | |
3498 | : 12 \ | |
3499 | : ((v) & ~0x3fffff) == 0 \ | |
3500 | ? ((v) & ~0x1fffff) == 0 \ | |
3501 | ? 11 \ | |
3502 | : 10 \ | |
3503 | : ((v) & ~0x7fffff) == 0 \ | |
3504 | ? 9 \ | |
3505 | : 8 \ | |
3506 | : ((v) & ~0xfffffff) == 0 \ | |
3507 | ? ((v) & ~0x3ffffff) == 0 \ | |
3508 | ? ((v) & ~0x1ffffff) == 0 \ | |
3509 | ? 7 \ | |
3510 | : 6 \ | |
3511 | : ((v) & ~0x7ffffff) == 0 \ | |
3512 | ? 5 \ | |
3513 | : 4 \ | |
3514 | : ((v) & ~0x3fffffff) == 0 \ | |
3515 | ? ((v) & ~0x1fffffff) == 0 \ | |
3516 | ? 3 \ | |
3517 | : 2 \ | |
3518 | : ((v) & ~0x7fffffff) == 0 \ | |
3519 | ? 1 \ | |
3520 | : 0) | |
3521 | ||
3522 | /* load_register() | |
3523 | * This routine generates the least number of instructions neccessary to load | |
3524 | * an absolute expression value into a register. | |
3525 | */ | |
3526 | static void | |
3527 | load_register (counter, reg, ep, dbl) | |
3528 | int *counter; | |
3529 | int reg; | |
3530 | expressionS *ep; | |
3531 | int dbl; | |
3532 | { | |
3533 | int freg; | |
3534 | expressionS hi32, lo32; | |
3535 | ||
3536 | if (ep->X_op != O_big) | |
3537 | { | |
3538 | assert (ep->X_op == O_constant); | |
3539 | if (ep->X_add_number < 0x8000 | |
3540 | && (ep->X_add_number >= 0 | |
3541 | || (ep->X_add_number >= -0x8000 | |
3542 | && (! dbl | |
3543 | || ! ep->X_unsigned | |
3544 | || sizeof (ep->X_add_number) > 4)))) | |
3545 | { | |
3546 | /* We can handle 16 bit signed values with an addiu to | |
3547 | $zero. No need to ever use daddiu here, since $zero and | |
3548 | the result are always correct in 32 bit mode. */ | |
3549 | macro_build ((char *) NULL, counter, ep, "addiu", "t,r,j", reg, 0, | |
3550 | (int) BFD_RELOC_LO16); | |
3551 | return; | |
3552 | } | |
3553 | else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000) | |
3554 | { | |
3555 | /* We can handle 16 bit unsigned values with an ori to | |
3556 | $zero. */ | |
3557 | macro_build ((char *) NULL, counter, ep, "ori", "t,r,i", reg, 0, | |
3558 | (int) BFD_RELOC_LO16); | |
3559 | return; | |
3560 | } | |
6373ee54 | 3561 | else if ((IS_SEXT_32BIT_NUM (ep->X_add_number) |
252b5132 RH |
3562 | && (! dbl |
3563 | || ! ep->X_unsigned | |
3564 | || sizeof (ep->X_add_number) > 4 | |
3565 | || (ep->X_add_number & 0x80000000) == 0)) | |
ca4e0257 | 3566 | || ((HAVE_32BIT_GPRS || ! dbl) |
252b5132 | 3567 | && (ep->X_add_number &~ (offsetT) 0xffffffff) == 0) |
ca4e0257 | 3568 | || (HAVE_32BIT_GPRS |
252b5132 RH |
3569 | && ! dbl |
3570 | && ((ep->X_add_number &~ (offsetT) 0xffffffff) | |
3571 | == ~ (offsetT) 0xffffffff))) | |
3572 | { | |
3573 | /* 32 bit values require an lui. */ | |
3574 | macro_build ((char *) NULL, counter, ep, "lui", "t,u", reg, | |
3575 | (int) BFD_RELOC_HI16); | |
3576 | if ((ep->X_add_number & 0xffff) != 0) | |
3577 | macro_build ((char *) NULL, counter, ep, "ori", "t,r,i", reg, reg, | |
3578 | (int) BFD_RELOC_LO16); | |
3579 | return; | |
3580 | } | |
3581 | } | |
3582 | ||
3583 | /* The value is larger than 32 bits. */ | |
3584 | ||
ca4e0257 | 3585 | if (HAVE_32BIT_GPRS) |
252b5132 | 3586 | { |
956cd1d6 TS |
3587 | as_bad (_("Number (0x%lx) larger than 32 bits"), |
3588 | (unsigned long) ep->X_add_number); | |
252b5132 RH |
3589 | macro_build ((char *) NULL, counter, ep, "addiu", "t,r,j", reg, 0, |
3590 | (int) BFD_RELOC_LO16); | |
3591 | return; | |
3592 | } | |
3593 | ||
3594 | if (ep->X_op != O_big) | |
3595 | { | |
3596 | hi32 = *ep; | |
3597 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
3598 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
3599 | hi32.X_add_number &= 0xffffffff; | |
3600 | lo32 = *ep; | |
3601 | lo32.X_add_number &= 0xffffffff; | |
3602 | } | |
3603 | else | |
3604 | { | |
3605 | assert (ep->X_add_number > 2); | |
3606 | if (ep->X_add_number == 3) | |
3607 | generic_bignum[3] = 0; | |
3608 | else if (ep->X_add_number > 4) | |
3609 | as_bad (_("Number larger than 64 bits")); | |
3610 | lo32.X_op = O_constant; | |
3611 | lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16); | |
3612 | hi32.X_op = O_constant; | |
3613 | hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16); | |
3614 | } | |
3615 | ||
3616 | if (hi32.X_add_number == 0) | |
3617 | freg = 0; | |
3618 | else | |
3619 | { | |
3620 | int shift, bit; | |
3621 | unsigned long hi, lo; | |
3622 | ||
956cd1d6 | 3623 | if (hi32.X_add_number == (offsetT) 0xffffffff) |
beae10d5 KH |
3624 | { |
3625 | if ((lo32.X_add_number & 0xffff8000) == 0xffff8000) | |
3626 | { | |
3627 | macro_build ((char *) NULL, counter, &lo32, "addiu", "t,r,j", | |
252b5132 | 3628 | reg, 0, (int) BFD_RELOC_LO16); |
beae10d5 KH |
3629 | return; |
3630 | } | |
3631 | if (lo32.X_add_number & 0x80000000) | |
3632 | { | |
3633 | macro_build ((char *) NULL, counter, &lo32, "lui", "t,u", reg, | |
3634 | (int) BFD_RELOC_HI16); | |
252b5132 RH |
3635 | if (lo32.X_add_number & 0xffff) |
3636 | macro_build ((char *) NULL, counter, &lo32, "ori", "t,r,i", | |
3637 | reg, reg, (int) BFD_RELOC_LO16); | |
beae10d5 KH |
3638 | return; |
3639 | } | |
3640 | } | |
252b5132 RH |
3641 | |
3642 | /* Check for 16bit shifted constant. We know that hi32 is | |
3643 | non-zero, so start the mask on the first bit of the hi32 | |
3644 | value. */ | |
3645 | shift = 17; | |
3646 | do | |
beae10d5 KH |
3647 | { |
3648 | unsigned long himask, lomask; | |
3649 | ||
3650 | if (shift < 32) | |
3651 | { | |
3652 | himask = 0xffff >> (32 - shift); | |
3653 | lomask = (0xffff << shift) & 0xffffffff; | |
3654 | } | |
3655 | else | |
3656 | { | |
3657 | himask = 0xffff << (shift - 32); | |
3658 | lomask = 0; | |
3659 | } | |
3660 | if ((hi32.X_add_number & ~(offsetT) himask) == 0 | |
3661 | && (lo32.X_add_number & ~(offsetT) lomask) == 0) | |
3662 | { | |
3663 | expressionS tmp; | |
3664 | ||
3665 | tmp.X_op = O_constant; | |
3666 | if (shift < 32) | |
3667 | tmp.X_add_number = ((hi32.X_add_number << (32 - shift)) | |
3668 | | (lo32.X_add_number >> shift)); | |
3669 | else | |
3670 | tmp.X_add_number = hi32.X_add_number >> (shift - 32); | |
3671 | macro_build ((char *) NULL, counter, &tmp, | |
3672 | "ori", "t,r,i", reg, 0, | |
3673 | (int) BFD_RELOC_LO16); | |
2396cfb9 | 3674 | macro_build ((char *) NULL, counter, (expressionS *) NULL, |
beae10d5 KH |
3675 | (shift >= 32) ? "dsll32" : "dsll", |
3676 | "d,w,<", reg, reg, | |
3677 | (shift >= 32) ? shift - 32 : shift); | |
3678 | return; | |
3679 | } | |
f9419b05 | 3680 | ++shift; |
beae10d5 KH |
3681 | } |
3682 | while (shift <= (64 - 16)); | |
252b5132 RH |
3683 | |
3684 | /* Find the bit number of the lowest one bit, and store the | |
3685 | shifted value in hi/lo. */ | |
3686 | hi = (unsigned long) (hi32.X_add_number & 0xffffffff); | |
3687 | lo = (unsigned long) (lo32.X_add_number & 0xffffffff); | |
3688 | if (lo != 0) | |
3689 | { | |
3690 | bit = 0; | |
3691 | while ((lo & 1) == 0) | |
3692 | { | |
3693 | lo >>= 1; | |
3694 | ++bit; | |
3695 | } | |
3696 | lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit); | |
3697 | hi >>= bit; | |
3698 | } | |
3699 | else | |
3700 | { | |
3701 | bit = 32; | |
3702 | while ((hi & 1) == 0) | |
3703 | { | |
3704 | hi >>= 1; | |
3705 | ++bit; | |
3706 | } | |
3707 | lo = hi; | |
3708 | hi = 0; | |
3709 | } | |
3710 | ||
3711 | /* Optimize if the shifted value is a (power of 2) - 1. */ | |
3712 | if ((hi == 0 && ((lo + 1) & lo) == 0) | |
3713 | || (lo == 0xffffffff && ((hi + 1) & hi) == 0)) | |
beae10d5 KH |
3714 | { |
3715 | shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number); | |
252b5132 | 3716 | if (shift != 0) |
beae10d5 | 3717 | { |
252b5132 RH |
3718 | expressionS tmp; |
3719 | ||
3720 | /* This instruction will set the register to be all | |
3721 | ones. */ | |
beae10d5 KH |
3722 | tmp.X_op = O_constant; |
3723 | tmp.X_add_number = (offsetT) -1; | |
3724 | macro_build ((char *) NULL, counter, &tmp, "addiu", "t,r,j", | |
252b5132 | 3725 | reg, 0, (int) BFD_RELOC_LO16); |
beae10d5 KH |
3726 | if (bit != 0) |
3727 | { | |
3728 | bit += shift; | |
2396cfb9 | 3729 | macro_build ((char *) NULL, counter, (expressionS *) NULL, |
beae10d5 KH |
3730 | (bit >= 32) ? "dsll32" : "dsll", |
3731 | "d,w,<", reg, reg, | |
3732 | (bit >= 32) ? bit - 32 : bit); | |
3733 | } | |
2396cfb9 | 3734 | macro_build ((char *) NULL, counter, (expressionS *) NULL, |
252b5132 | 3735 | (shift >= 32) ? "dsrl32" : "dsrl", |
beae10d5 | 3736 | "d,w,<", reg, reg, |
252b5132 | 3737 | (shift >= 32) ? shift - 32 : shift); |
beae10d5 KH |
3738 | return; |
3739 | } | |
3740 | } | |
252b5132 RH |
3741 | |
3742 | /* Sign extend hi32 before calling load_register, because we can | |
3743 | generally get better code when we load a sign extended value. */ | |
3744 | if ((hi32.X_add_number & 0x80000000) != 0) | |
beae10d5 | 3745 | hi32.X_add_number |= ~(offsetT) 0xffffffff; |
252b5132 RH |
3746 | load_register (counter, reg, &hi32, 0); |
3747 | freg = reg; | |
3748 | } | |
3749 | if ((lo32.X_add_number & 0xffff0000) == 0) | |
3750 | { | |
3751 | if (freg != 0) | |
3752 | { | |
2396cfb9 TS |
3753 | macro_build ((char *) NULL, counter, (expressionS *) NULL, |
3754 | "dsll32", "d,w,<", reg, freg, 0); | |
252b5132 RH |
3755 | freg = reg; |
3756 | } | |
3757 | } | |
3758 | else | |
3759 | { | |
3760 | expressionS mid16; | |
3761 | ||
956cd1d6 | 3762 | if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff)) |
beae10d5 | 3763 | { |
252b5132 RH |
3764 | macro_build ((char *) NULL, counter, &lo32, "lui", "t,u", reg, |
3765 | (int) BFD_RELOC_HI16); | |
956cd1d6 TS |
3766 | macro_build ((char *) NULL, counter, (expressionS *) NULL, |
3767 | "dsrl32", "d,w,<", reg, reg, 0); | |
beae10d5 KH |
3768 | return; |
3769 | } | |
252b5132 RH |
3770 | |
3771 | if (freg != 0) | |
3772 | { | |
956cd1d6 TS |
3773 | macro_build ((char *) NULL, counter, (expressionS *) NULL, "dsll", |
3774 | "d,w,<", reg, freg, 16); | |
252b5132 RH |
3775 | freg = reg; |
3776 | } | |
3777 | mid16 = lo32; | |
3778 | mid16.X_add_number >>= 16; | |
3779 | macro_build ((char *) NULL, counter, &mid16, "ori", "t,r,i", reg, | |
3780 | freg, (int) BFD_RELOC_LO16); | |
956cd1d6 TS |
3781 | macro_build ((char *) NULL, counter, (expressionS *) NULL, "dsll", |
3782 | "d,w,<", reg, reg, 16); | |
252b5132 RH |
3783 | freg = reg; |
3784 | } | |
3785 | if ((lo32.X_add_number & 0xffff) != 0) | |
3786 | macro_build ((char *) NULL, counter, &lo32, "ori", "t,r,i", reg, freg, | |
3787 | (int) BFD_RELOC_LO16); | |
3788 | } | |
3789 | ||
3790 | /* Load an address into a register. */ | |
3791 | ||
3792 | static void | |
c9914766 | 3793 | load_address (counter, reg, ep, used_at) |
252b5132 RH |
3794 | int *counter; |
3795 | int reg; | |
3796 | expressionS *ep; | |
d6bc6245 | 3797 | int *used_at; |
252b5132 | 3798 | { |
f9419b05 | 3799 | char *p = NULL; |
252b5132 RH |
3800 | |
3801 | if (ep->X_op != O_constant | |
3802 | && ep->X_op != O_symbol) | |
3803 | { | |
3804 | as_bad (_("expression too complex")); | |
3805 | ep->X_op = O_constant; | |
3806 | } | |
3807 | ||
3808 | if (ep->X_op == O_constant) | |
3809 | { | |
c9914766 | 3810 | load_register (counter, reg, ep, HAVE_64BIT_ADDRESSES); |
252b5132 RH |
3811 | return; |
3812 | } | |
3813 | ||
3814 | if (mips_pic == NO_PIC) | |
3815 | { | |
3816 | /* If this is a reference to a GP relative symbol, we want | |
cdf6fd85 | 3817 | addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
3818 | Otherwise we want |
3819 | lui $reg,<sym> (BFD_RELOC_HI16_S) | |
3820 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
d6bc6245 | 3821 | If we have an addend, we always use the latter form. |
76b3015f | 3822 | |
d6bc6245 TS |
3823 | With 64bit address space and a usable $at we want |
3824 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
3825 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
3826 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
3827 | daddiu $at,<sym> (BFD_RELOC_LO16) | |
3828 | dsll32 $reg,0 | |
3a482fd5 | 3829 | daddu $reg,$reg,$at |
76b3015f | 3830 | |
c03099e6 | 3831 | If $at is already in use, we use a path which is suboptimal |
d6bc6245 TS |
3832 | on superscalar processors. |
3833 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
3834 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
3835 | dsll $reg,16 | |
3836 | daddiu $reg,<sym> (BFD_RELOC_HI16_S) | |
3837 | dsll $reg,16 | |
3838 | daddiu $reg,<sym> (BFD_RELOC_LO16) | |
3839 | */ | |
c9914766 | 3840 | if (HAVE_64BIT_ADDRESSES) |
d6bc6245 | 3841 | { |
d6bc6245 TS |
3842 | /* We don't do GP optimization for now because RELAX_ENCODE can't |
3843 | hold the data for such large chunks. */ | |
3844 | ||
460597ba | 3845 | if (*used_at == 0 && ! mips_opts.noat) |
d6bc6245 TS |
3846 | { |
3847 | macro_build (p, counter, ep, "lui", "t,u", | |
3848 | reg, (int) BFD_RELOC_MIPS_HIGHEST); | |
3849 | macro_build (p, counter, ep, "lui", "t,u", | |
3850 | AT, (int) BFD_RELOC_HI16_S); | |
3851 | macro_build (p, counter, ep, "daddiu", "t,r,j", | |
3852 | reg, reg, (int) BFD_RELOC_MIPS_HIGHER); | |
3853 | macro_build (p, counter, ep, "daddiu", "t,r,j", | |
3854 | AT, AT, (int) BFD_RELOC_LO16); | |
2396cfb9 TS |
3855 | macro_build (p, counter, (expressionS *) NULL, "dsll32", |
3856 | "d,w,<", reg, reg, 0); | |
3a482fd5 | 3857 | macro_build (p, counter, (expressionS *) NULL, "daddu", |
2396cfb9 | 3858 | "d,v,t", reg, reg, AT); |
d6bc6245 TS |
3859 | *used_at = 1; |
3860 | } | |
3861 | else | |
3862 | { | |
3863 | macro_build (p, counter, ep, "lui", "t,u", | |
3864 | reg, (int) BFD_RELOC_MIPS_HIGHEST); | |
3865 | macro_build (p, counter, ep, "daddiu", "t,r,j", | |
3866 | reg, reg, (int) BFD_RELOC_MIPS_HIGHER); | |
2396cfb9 TS |
3867 | macro_build (p, counter, (expressionS *) NULL, "dsll", |
3868 | "d,w,<", reg, reg, 16); | |
d6bc6245 TS |
3869 | macro_build (p, counter, ep, "daddiu", "t,r,j", |
3870 | reg, reg, (int) BFD_RELOC_HI16_S); | |
2396cfb9 TS |
3871 | macro_build (p, counter, (expressionS *) NULL, "dsll", |
3872 | "d,w,<", reg, reg, 16); | |
d6bc6245 TS |
3873 | macro_build (p, counter, ep, "daddiu", "t,r,j", |
3874 | reg, reg, (int) BFD_RELOC_LO16); | |
3875 | } | |
3876 | } | |
252b5132 RH |
3877 | else |
3878 | { | |
d6bc6245 TS |
3879 | if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET |
3880 | && ! nopic_need_relax (ep->X_add_symbol, 1)) | |
3881 | { | |
3882 | frag_grow (20); | |
3883 | macro_build ((char *) NULL, counter, ep, | |
c9914766 TS |
3884 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", "t,r,j", |
3885 | reg, mips_gp_register, (int) BFD_RELOC_GPREL16); | |
d6bc6245 TS |
3886 | p = frag_var (rs_machine_dependent, 8, 0, |
3887 | RELAX_ENCODE (4, 8, 0, 4, 0, | |
3888 | mips_opts.warn_about_macros), | |
956cd1d6 | 3889 | ep->X_add_symbol, 0, NULL); |
d6bc6245 TS |
3890 | } |
3891 | macro_build_lui (p, counter, ep, reg); | |
3892 | if (p != NULL) | |
3893 | p += 4; | |
c9914766 TS |
3894 | macro_build (p, counter, ep, |
3895 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", | |
d6bc6245 TS |
3896 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); |
3897 | } | |
252b5132 RH |
3898 | } |
3899 | else if (mips_pic == SVR4_PIC && ! mips_big_got) | |
3900 | { | |
3901 | expressionS ex; | |
3902 | ||
3903 | /* If this is a reference to an external symbol, we want | |
3904 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3905 | Otherwise we want | |
3906 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3907 | nop | |
3908 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
ed6fb7bd SC |
3909 | If we have NewABI, we want |
3910 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
252b5132 RH |
3911 | If there is a constant, it must be added in after. */ |
3912 | ex.X_add_number = ep->X_add_number; | |
3913 | ep->X_add_number = 0; | |
3914 | frag_grow (20); | |
ed6fb7bd SC |
3915 | if (HAVE_NEWABI) |
3916 | { | |
3917 | macro_build ((char *) NULL, counter, ep, | |
3918 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", "t,o(b)", reg, | |
3919 | (int) BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
3920 | } | |
3921 | else | |
3922 | { | |
3923 | macro_build ((char *) NULL, counter, ep, | |
3924 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", "t,o(b)", | |
3925 | reg, (int) BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
3926 | macro_build ((char *) NULL, counter, (expressionS *) NULL, "nop", ""); | |
3927 | p = frag_var (rs_machine_dependent, 4, 0, | |
3928 | RELAX_ENCODE (0, 4, -8, 0, 0, mips_opts.warn_about_macros), | |
3929 | ep->X_add_symbol, (offsetT) 0, (char *) NULL); | |
3930 | macro_build (p, counter, ep, | |
3931 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", | |
3932 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); | |
3933 | } | |
3934 | ||
252b5132 RH |
3935 | if (ex.X_add_number != 0) |
3936 | { | |
3937 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
3938 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
3939 | ex.X_op = O_constant; | |
3940 | macro_build ((char *) NULL, counter, &ex, | |
ca4e0257 | 3941 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
252b5132 RH |
3942 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); |
3943 | } | |
3944 | } | |
3945 | else if (mips_pic == SVR4_PIC) | |
3946 | { | |
3947 | expressionS ex; | |
3948 | int off; | |
3949 | ||
3950 | /* This is the large GOT case. If this is a reference to an | |
3951 | external symbol, we want | |
3952 | lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
3953 | addu $reg,$reg,$gp | |
3954 | lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16) | |
3955 | Otherwise, for a reference to a local symbol, we want | |
3956 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3957 | nop | |
3958 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
438c16b8 TS |
3959 | If we have NewABI, we want |
3960 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
3961 | addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) | |
252b5132 RH |
3962 | If there is a constant, it must be added in after. */ |
3963 | ex.X_add_number = ep->X_add_number; | |
3964 | ep->X_add_number = 0; | |
438c16b8 TS |
3965 | if (HAVE_NEWABI) |
3966 | { | |
3967 | macro_build ((char *) NULL, counter, ep, | |
3968 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", "t,o(b)", reg, | |
3969 | (int) BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
3970 | macro_build (p, counter, ep, | |
3971 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", "t,r,j", | |
3972 | reg, reg, (int) BFD_RELOC_MIPS_GOT_OFST); | |
3973 | } | |
252b5132 | 3974 | else |
438c16b8 TS |
3975 | { |
3976 | if (reg_needs_delay (mips_gp_register)) | |
3977 | off = 4; | |
3978 | else | |
3979 | off = 0; | |
3980 | frag_grow (32); | |
3981 | macro_build ((char *) NULL, counter, ep, "lui", "t,u", reg, | |
3982 | (int) BFD_RELOC_MIPS_GOT_HI16); | |
3983 | macro_build ((char *) NULL, counter, (expressionS *) NULL, | |
3984 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", "d,v,t", reg, | |
3985 | reg, mips_gp_register); | |
3986 | macro_build ((char *) NULL, counter, ep, | |
3987 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", | |
3988 | "t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT_LO16, reg); | |
3989 | p = frag_var (rs_machine_dependent, 12 + off, 0, | |
3990 | RELAX_ENCODE (12, 12 + off, off, 8 + off, 0, | |
3991 | mips_opts.warn_about_macros), | |
3992 | ep->X_add_symbol, 0, NULL); | |
3993 | if (off > 0) | |
3994 | { | |
3995 | /* We need a nop before loading from $gp. This special | |
3996 | check is required because the lui which starts the main | |
3997 | instruction stream does not refer to $gp, and so will not | |
3998 | insert the nop which may be required. */ | |
3999 | macro_build (p, counter, (expressionS *) NULL, "nop", ""); | |
4000 | p += 4; | |
4001 | } | |
4002 | macro_build (p, counter, ep, | |
4003 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", "t,o(b)", reg, | |
4004 | (int) BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
4005 | p += 4; | |
252b5132 RH |
4006 | macro_build (p, counter, (expressionS *) NULL, "nop", ""); |
4007 | p += 4; | |
438c16b8 TS |
4008 | macro_build (p, counter, ep, |
4009 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", | |
4010 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); | |
252b5132 | 4011 | } |
438c16b8 | 4012 | |
252b5132 RH |
4013 | if (ex.X_add_number != 0) |
4014 | { | |
4015 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
4016 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4017 | ex.X_op = O_constant; | |
f7ea7ef2 TS |
4018 | macro_build ((char *) NULL, counter, &ex, |
4019 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", | |
252b5132 RH |
4020 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); |
4021 | } | |
4022 | } | |
4023 | else if (mips_pic == EMBEDDED_PIC) | |
4024 | { | |
4025 | /* We always do | |
cdf6fd85 | 4026 | addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16) |
c9914766 TS |
4027 | */ |
4028 | macro_build ((char *) NULL, counter, ep, | |
4029 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", | |
4030 | "t,r,j", reg, mips_gp_register, (int) BFD_RELOC_GPREL16); | |
252b5132 RH |
4031 | } |
4032 | else | |
4033 | abort (); | |
4034 | } | |
4035 | ||
ea1fb5dc RS |
4036 | /* Move the contents of register SOURCE into register DEST. */ |
4037 | ||
4038 | static void | |
4039 | move_register (counter, dest, source) | |
4040 | int *counter; | |
4041 | int dest; | |
4042 | int source; | |
4043 | { | |
4044 | macro_build ((char *) NULL, counter, (expressionS *) NULL, | |
4045 | HAVE_32BIT_GPRS ? "addu" : "daddu", | |
4046 | "d,v,t", dest, source, 0); | |
4047 | } | |
4048 | ||
252b5132 RH |
4049 | /* |
4050 | * Build macros | |
4051 | * This routine implements the seemingly endless macro or synthesized | |
4052 | * instructions and addressing modes in the mips assembly language. Many | |
4053 | * of these macros are simple and are similar to each other. These could | |
4054 | * probably be handled by some kind of table or grammer aproach instead of | |
4055 | * this verbose method. Others are not simple macros but are more like | |
4056 | * optimizing code generation. | |
4057 | * One interesting optimization is when several store macros appear | |
4058 | * consecutivly that would load AT with the upper half of the same address. | |
4059 | * The ensuing load upper instructions are ommited. This implies some kind | |
4060 | * of global optimization. We currently only optimize within a single macro. | |
4061 | * For many of the load and store macros if the address is specified as a | |
4062 | * constant expression in the first 64k of memory (ie ld $2,0x4000c) we | |
4063 | * first load register 'at' with zero and use it as the base register. The | |
4064 | * mips assembler simply uses register $zero. Just one tiny optimization | |
4065 | * we're missing. | |
4066 | */ | |
4067 | static void | |
4068 | macro (ip) | |
4069 | struct mips_cl_insn *ip; | |
4070 | { | |
4071 | register int treg, sreg, dreg, breg; | |
4072 | int tempreg; | |
4073 | int mask; | |
4074 | int icnt = 0; | |
43841e91 | 4075 | int used_at = 0; |
252b5132 RH |
4076 | expressionS expr1; |
4077 | const char *s; | |
4078 | const char *s2; | |
4079 | const char *fmt; | |
4080 | int likely = 0; | |
4081 | int dbl = 0; | |
4082 | int coproc = 0; | |
4083 | int lr = 0; | |
4084 | int imm = 0; | |
4085 | offsetT maxnum; | |
4086 | int off; | |
4087 | bfd_reloc_code_real_type r; | |
252b5132 RH |
4088 | int hold_mips_optimize; |
4089 | ||
4090 | assert (! mips_opts.mips16); | |
4091 | ||
4092 | treg = (ip->insn_opcode >> 16) & 0x1f; | |
4093 | dreg = (ip->insn_opcode >> 11) & 0x1f; | |
4094 | sreg = breg = (ip->insn_opcode >> 21) & 0x1f; | |
4095 | mask = ip->insn_mo->mask; | |
4096 | ||
4097 | expr1.X_op = O_constant; | |
4098 | expr1.X_op_symbol = NULL; | |
4099 | expr1.X_add_symbol = NULL; | |
4100 | expr1.X_add_number = 1; | |
4101 | ||
5919d012 RS |
4102 | /* Umatched fixups should not be put in the same frag as a relaxable |
4103 | macro. For example, suppose we have: | |
4104 | ||
4105 | lui $4,%hi(l1) # 1 | |
4106 | la $5,l2 # 2 | |
4107 | addiu $4,$4,%lo(l1) # 3 | |
4108 | ||
4109 | If instructions 1 and 2 were put in the same frag, md_frob_file would | |
4110 | move the fixup for #1 after the fixups for the "unrelaxed" version of | |
4111 | #2. This would confuse tc_gen_reloc, which expects the relocations | |
4112 | for #2 to be the last for that frag. | |
4113 | ||
64bdfcaf RS |
4114 | Also, if tc_gen_reloc sees certain relocations in a variant frag, |
4115 | it assumes that they belong to a relaxable macro. We mustn't put | |
4116 | other uses of such relocations into a variant frag. | |
4117 | ||
4118 | To avoid both problems, finish the current frag it contains a | |
4119 | %reloc() operator. The macro then goes into a new frag. */ | |
4120 | if (prev_reloc_op_frag == frag_now) | |
5919d012 RS |
4121 | { |
4122 | frag_wane (frag_now); | |
4123 | frag_new (0); | |
4124 | } | |
4125 | ||
252b5132 RH |
4126 | switch (mask) |
4127 | { | |
4128 | case M_DABS: | |
4129 | dbl = 1; | |
4130 | case M_ABS: | |
4131 | /* bgez $a0,.+12 | |
4132 | move v0,$a0 | |
4133 | sub v0,$zero,$a0 | |
4134 | */ | |
4135 | ||
b34976b6 | 4136 | mips_emit_delays (TRUE); |
252b5132 RH |
4137 | ++mips_opts.noreorder; |
4138 | mips_any_noreorder = 1; | |
4139 | ||
4140 | expr1.X_add_number = 8; | |
4141 | macro_build ((char *) NULL, &icnt, &expr1, "bgez", "s,p", sreg); | |
4142 | if (dreg == sreg) | |
2396cfb9 TS |
4143 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "", |
4144 | 0); | |
252b5132 | 4145 | else |
ea1fb5dc | 4146 | move_register (&icnt, dreg, sreg); |
2396cfb9 | 4147 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
9a41af64 | 4148 | dbl ? "dsub" : "sub", "d,v,t", dreg, 0, sreg); |
252b5132 RH |
4149 | |
4150 | --mips_opts.noreorder; | |
4151 | return; | |
4152 | ||
4153 | case M_ADD_I: | |
4154 | s = "addi"; | |
4155 | s2 = "add"; | |
4156 | goto do_addi; | |
4157 | case M_ADDU_I: | |
4158 | s = "addiu"; | |
4159 | s2 = "addu"; | |
4160 | goto do_addi; | |
4161 | case M_DADD_I: | |
4162 | dbl = 1; | |
4163 | s = "daddi"; | |
4164 | s2 = "dadd"; | |
4165 | goto do_addi; | |
4166 | case M_DADDU_I: | |
4167 | dbl = 1; | |
4168 | s = "daddiu"; | |
4169 | s2 = "daddu"; | |
4170 | do_addi: | |
4171 | if (imm_expr.X_op == O_constant | |
4172 | && imm_expr.X_add_number >= -0x8000 | |
4173 | && imm_expr.X_add_number < 0x8000) | |
4174 | { | |
4175 | macro_build ((char *) NULL, &icnt, &imm_expr, s, "t,r,j", treg, sreg, | |
4176 | (int) BFD_RELOC_LO16); | |
4177 | return; | |
4178 | } | |
4179 | load_register (&icnt, AT, &imm_expr, dbl); | |
2396cfb9 TS |
4180 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s2, "d,v,t", |
4181 | treg, sreg, AT); | |
252b5132 RH |
4182 | break; |
4183 | ||
4184 | case M_AND_I: | |
4185 | s = "andi"; | |
4186 | s2 = "and"; | |
4187 | goto do_bit; | |
4188 | case M_OR_I: | |
4189 | s = "ori"; | |
4190 | s2 = "or"; | |
4191 | goto do_bit; | |
4192 | case M_NOR_I: | |
4193 | s = ""; | |
4194 | s2 = "nor"; | |
4195 | goto do_bit; | |
4196 | case M_XOR_I: | |
4197 | s = "xori"; | |
4198 | s2 = "xor"; | |
4199 | do_bit: | |
4200 | if (imm_expr.X_op == O_constant | |
4201 | && imm_expr.X_add_number >= 0 | |
4202 | && imm_expr.X_add_number < 0x10000) | |
4203 | { | |
4204 | if (mask != M_NOR_I) | |
4205 | macro_build ((char *) NULL, &icnt, &imm_expr, s, "t,r,i", treg, | |
4206 | sreg, (int) BFD_RELOC_LO16); | |
4207 | else | |
4208 | { | |
4209 | macro_build ((char *) NULL, &icnt, &imm_expr, "ori", "t,r,i", | |
4210 | treg, sreg, (int) BFD_RELOC_LO16); | |
2396cfb9 TS |
4211 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nor", |
4212 | "d,v,t", treg, treg, 0); | |
252b5132 RH |
4213 | } |
4214 | return; | |
4215 | } | |
4216 | ||
d6bc6245 | 4217 | load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS); |
2396cfb9 TS |
4218 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s2, "d,v,t", |
4219 | treg, sreg, AT); | |
252b5132 RH |
4220 | break; |
4221 | ||
4222 | case M_BEQ_I: | |
4223 | s = "beq"; | |
4224 | goto beq_i; | |
4225 | case M_BEQL_I: | |
4226 | s = "beql"; | |
4227 | likely = 1; | |
4228 | goto beq_i; | |
4229 | case M_BNE_I: | |
4230 | s = "bne"; | |
4231 | goto beq_i; | |
4232 | case M_BNEL_I: | |
4233 | s = "bnel"; | |
4234 | likely = 1; | |
4235 | beq_i: | |
4236 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4237 | { | |
4238 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "s,t,p", sreg, | |
4239 | 0); | |
4240 | return; | |
4241 | } | |
4d34fb5f | 4242 | load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS); |
252b5132 RH |
4243 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "s,t,p", sreg, AT); |
4244 | break; | |
4245 | ||
4246 | case M_BGEL: | |
4247 | likely = 1; | |
4248 | case M_BGE: | |
4249 | if (treg == 0) | |
4250 | { | |
4251 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
2396cfb9 | 4252 | likely ? "bgezl" : "bgez", "s,p", sreg); |
252b5132 RH |
4253 | return; |
4254 | } | |
4255 | if (sreg == 0) | |
4256 | { | |
4257 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
2396cfb9 | 4258 | likely ? "blezl" : "blez", "s,p", treg); |
252b5132 RH |
4259 | return; |
4260 | } | |
2396cfb9 TS |
4261 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "slt", "d,v,t", |
4262 | AT, sreg, treg); | |
252b5132 | 4263 | macro_build ((char *) NULL, &icnt, &offset_expr, |
9a41af64 | 4264 | likely ? "beql" : "beq", "s,t,p", AT, 0); |
252b5132 RH |
4265 | break; |
4266 | ||
4267 | case M_BGTL_I: | |
4268 | likely = 1; | |
4269 | case M_BGT_I: | |
4270 | /* check for > max integer */ | |
4271 | maxnum = 0x7fffffff; | |
ca4e0257 | 4272 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
4273 | { |
4274 | maxnum <<= 16; | |
4275 | maxnum |= 0xffff; | |
4276 | maxnum <<= 16; | |
4277 | maxnum |= 0xffff; | |
4278 | } | |
4279 | if (imm_expr.X_op == O_constant | |
4280 | && imm_expr.X_add_number >= maxnum | |
ca4e0257 | 4281 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
4282 | { |
4283 | do_false: | |
4284 | /* result is always false */ | |
4285 | if (! likely) | |
4286 | { | |
39c0a331 L |
4287 | if (warn_nops) |
4288 | as_warn (_("Branch %s is always false (nop)"), | |
4289 | ip->insn_mo->name); | |
2396cfb9 TS |
4290 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", |
4291 | "", 0); | |
252b5132 RH |
4292 | } |
4293 | else | |
4294 | { | |
39c0a331 L |
4295 | if (warn_nops) |
4296 | as_warn (_("Branch likely %s is always false"), | |
4297 | ip->insn_mo->name); | |
252b5132 RH |
4298 | macro_build ((char *) NULL, &icnt, &offset_expr, "bnel", |
4299 | "s,t,p", 0, 0); | |
4300 | } | |
4301 | return; | |
4302 | } | |
4303 | if (imm_expr.X_op != O_constant) | |
4304 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 4305 | ++imm_expr.X_add_number; |
252b5132 RH |
4306 | /* FALLTHROUGH */ |
4307 | case M_BGE_I: | |
4308 | case M_BGEL_I: | |
4309 | if (mask == M_BGEL_I) | |
4310 | likely = 1; | |
4311 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4312 | { | |
4313 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4314 | likely ? "bgezl" : "bgez", "s,p", sreg); |
252b5132 RH |
4315 | return; |
4316 | } | |
4317 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4318 | { | |
4319 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4320 | likely ? "bgtzl" : "bgtz", "s,p", sreg); |
252b5132 RH |
4321 | return; |
4322 | } | |
4323 | maxnum = 0x7fffffff; | |
ca4e0257 | 4324 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
4325 | { |
4326 | maxnum <<= 16; | |
4327 | maxnum |= 0xffff; | |
4328 | maxnum <<= 16; | |
4329 | maxnum |= 0xffff; | |
4330 | } | |
4331 | maxnum = - maxnum - 1; | |
4332 | if (imm_expr.X_op == O_constant | |
4333 | && imm_expr.X_add_number <= maxnum | |
ca4e0257 | 4334 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
4335 | { |
4336 | do_true: | |
4337 | /* result is always true */ | |
4338 | as_warn (_("Branch %s is always true"), ip->insn_mo->name); | |
4339 | macro_build ((char *) NULL, &icnt, &offset_expr, "b", "p"); | |
4340 | return; | |
4341 | } | |
4342 | set_at (&icnt, sreg, 0); | |
4343 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4344 | likely ? "beql" : "beq", "s,t,p", AT, 0); |
252b5132 RH |
4345 | break; |
4346 | ||
4347 | case M_BGEUL: | |
4348 | likely = 1; | |
4349 | case M_BGEU: | |
4350 | if (treg == 0) | |
4351 | goto do_true; | |
4352 | if (sreg == 0) | |
4353 | { | |
4354 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4355 | likely ? "beql" : "beq", "s,t,p", 0, treg); |
252b5132 RH |
4356 | return; |
4357 | } | |
2396cfb9 TS |
4358 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu", |
4359 | "d,v,t", AT, sreg, treg); | |
252b5132 | 4360 | macro_build ((char *) NULL, &icnt, &offset_expr, |
9a41af64 | 4361 | likely ? "beql" : "beq", "s,t,p", AT, 0); |
252b5132 RH |
4362 | break; |
4363 | ||
4364 | case M_BGTUL_I: | |
4365 | likely = 1; | |
4366 | case M_BGTU_I: | |
4367 | if (sreg == 0 | |
ca4e0257 | 4368 | || (HAVE_32BIT_GPRS |
252b5132 | 4369 | && imm_expr.X_op == O_constant |
956cd1d6 | 4370 | && imm_expr.X_add_number == (offsetT) 0xffffffff)) |
252b5132 RH |
4371 | goto do_false; |
4372 | if (imm_expr.X_op != O_constant) | |
4373 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 4374 | ++imm_expr.X_add_number; |
252b5132 RH |
4375 | /* FALLTHROUGH */ |
4376 | case M_BGEU_I: | |
4377 | case M_BGEUL_I: | |
4378 | if (mask == M_BGEUL_I) | |
4379 | likely = 1; | |
4380 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4381 | goto do_true; | |
4382 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4383 | { | |
4384 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4385 | likely ? "bnel" : "bne", "s,t,p", sreg, 0); |
252b5132 RH |
4386 | return; |
4387 | } | |
4388 | set_at (&icnt, sreg, 1); | |
4389 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4390 | likely ? "beql" : "beq", "s,t,p", AT, 0); |
252b5132 RH |
4391 | break; |
4392 | ||
4393 | case M_BGTL: | |
4394 | likely = 1; | |
4395 | case M_BGT: | |
4396 | if (treg == 0) | |
4397 | { | |
4398 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4399 | likely ? "bgtzl" : "bgtz", "s,p", sreg); |
252b5132 RH |
4400 | return; |
4401 | } | |
4402 | if (sreg == 0) | |
4403 | { | |
4404 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4405 | likely ? "bltzl" : "bltz", "s,p", treg); |
252b5132 RH |
4406 | return; |
4407 | } | |
2396cfb9 TS |
4408 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "slt", "d,v,t", |
4409 | AT, treg, sreg); | |
252b5132 | 4410 | macro_build ((char *) NULL, &icnt, &offset_expr, |
9a41af64 | 4411 | likely ? "bnel" : "bne", "s,t,p", AT, 0); |
252b5132 RH |
4412 | break; |
4413 | ||
4414 | case M_BGTUL: | |
4415 | likely = 1; | |
4416 | case M_BGTU: | |
4417 | if (treg == 0) | |
4418 | { | |
4419 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4420 | likely ? "bnel" : "bne", "s,t,p", sreg, 0); |
252b5132 RH |
4421 | return; |
4422 | } | |
4423 | if (sreg == 0) | |
4424 | goto do_false; | |
2396cfb9 TS |
4425 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu", |
4426 | "d,v,t", AT, treg, sreg); | |
252b5132 | 4427 | macro_build ((char *) NULL, &icnt, &offset_expr, |
9a41af64 | 4428 | likely ? "bnel" : "bne", "s,t,p", AT, 0); |
252b5132 RH |
4429 | break; |
4430 | ||
4431 | case M_BLEL: | |
4432 | likely = 1; | |
4433 | case M_BLE: | |
4434 | if (treg == 0) | |
4435 | { | |
4436 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4437 | likely ? "blezl" : "blez", "s,p", sreg); |
252b5132 RH |
4438 | return; |
4439 | } | |
4440 | if (sreg == 0) | |
4441 | { | |
4442 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4443 | likely ? "bgezl" : "bgez", "s,p", treg); |
252b5132 RH |
4444 | return; |
4445 | } | |
2396cfb9 TS |
4446 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "slt", "d,v,t", |
4447 | AT, treg, sreg); | |
252b5132 | 4448 | macro_build ((char *) NULL, &icnt, &offset_expr, |
9a41af64 | 4449 | likely ? "beql" : "beq", "s,t,p", AT, 0); |
252b5132 RH |
4450 | break; |
4451 | ||
4452 | case M_BLEL_I: | |
4453 | likely = 1; | |
4454 | case M_BLE_I: | |
4455 | maxnum = 0x7fffffff; | |
ca4e0257 | 4456 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
4457 | { |
4458 | maxnum <<= 16; | |
4459 | maxnum |= 0xffff; | |
4460 | maxnum <<= 16; | |
4461 | maxnum |= 0xffff; | |
4462 | } | |
4463 | if (imm_expr.X_op == O_constant | |
4464 | && imm_expr.X_add_number >= maxnum | |
ca4e0257 | 4465 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
4466 | goto do_true; |
4467 | if (imm_expr.X_op != O_constant) | |
4468 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 4469 | ++imm_expr.X_add_number; |
252b5132 RH |
4470 | /* FALLTHROUGH */ |
4471 | case M_BLT_I: | |
4472 | case M_BLTL_I: | |
4473 | if (mask == M_BLTL_I) | |
4474 | likely = 1; | |
4475 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4476 | { | |
4477 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4478 | likely ? "bltzl" : "bltz", "s,p", sreg); |
252b5132 RH |
4479 | return; |
4480 | } | |
4481 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4482 | { | |
4483 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4484 | likely ? "blezl" : "blez", "s,p", sreg); |
252b5132 RH |
4485 | return; |
4486 | } | |
4487 | set_at (&icnt, sreg, 0); | |
4488 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4489 | likely ? "bnel" : "bne", "s,t,p", AT, 0); |
252b5132 RH |
4490 | break; |
4491 | ||
4492 | case M_BLEUL: | |
4493 | likely = 1; | |
4494 | case M_BLEU: | |
4495 | if (treg == 0) | |
4496 | { | |
4497 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4498 | likely ? "beql" : "beq", "s,t,p", sreg, 0); |
252b5132 RH |
4499 | return; |
4500 | } | |
4501 | if (sreg == 0) | |
4502 | goto do_true; | |
2396cfb9 TS |
4503 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu", |
4504 | "d,v,t", AT, treg, sreg); | |
252b5132 | 4505 | macro_build ((char *) NULL, &icnt, &offset_expr, |
9a41af64 | 4506 | likely ? "beql" : "beq", "s,t,p", AT, 0); |
252b5132 RH |
4507 | break; |
4508 | ||
4509 | case M_BLEUL_I: | |
4510 | likely = 1; | |
4511 | case M_BLEU_I: | |
4512 | if (sreg == 0 | |
ca4e0257 | 4513 | || (HAVE_32BIT_GPRS |
252b5132 | 4514 | && imm_expr.X_op == O_constant |
956cd1d6 | 4515 | && imm_expr.X_add_number == (offsetT) 0xffffffff)) |
252b5132 RH |
4516 | goto do_true; |
4517 | if (imm_expr.X_op != O_constant) | |
4518 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 4519 | ++imm_expr.X_add_number; |
252b5132 RH |
4520 | /* FALLTHROUGH */ |
4521 | case M_BLTU_I: | |
4522 | case M_BLTUL_I: | |
4523 | if (mask == M_BLTUL_I) | |
4524 | likely = 1; | |
4525 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4526 | goto do_false; | |
4527 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4528 | { | |
4529 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
4530 | likely ? "beql" : "beq", | |
4531 | "s,t,p", sreg, 0); | |
4532 | return; | |
4533 | } | |
4534 | set_at (&icnt, sreg, 1); | |
4535 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4536 | likely ? "bnel" : "bne", "s,t,p", AT, 0); |
252b5132 RH |
4537 | break; |
4538 | ||
4539 | case M_BLTL: | |
4540 | likely = 1; | |
4541 | case M_BLT: | |
4542 | if (treg == 0) | |
4543 | { | |
4544 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4545 | likely ? "bltzl" : "bltz", "s,p", sreg); |
252b5132 RH |
4546 | return; |
4547 | } | |
4548 | if (sreg == 0) | |
4549 | { | |
4550 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4551 | likely ? "bgtzl" : "bgtz", "s,p", treg); |
252b5132 RH |
4552 | return; |
4553 | } | |
2396cfb9 TS |
4554 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "slt", "d,v,t", |
4555 | AT, sreg, treg); | |
252b5132 | 4556 | macro_build ((char *) NULL, &icnt, &offset_expr, |
9a41af64 | 4557 | likely ? "bnel" : "bne", "s,t,p", AT, 0); |
252b5132 RH |
4558 | break; |
4559 | ||
4560 | case M_BLTUL: | |
4561 | likely = 1; | |
4562 | case M_BLTU: | |
4563 | if (treg == 0) | |
4564 | goto do_false; | |
4565 | if (sreg == 0) | |
4566 | { | |
4567 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4568 | likely ? "bnel" : "bne", "s,t,p", 0, treg); |
252b5132 RH |
4569 | return; |
4570 | } | |
2396cfb9 TS |
4571 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu", |
4572 | "d,v,t", AT, sreg, | |
252b5132 RH |
4573 | treg); |
4574 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4575 | likely ? "bnel" : "bne", "s,t,p", AT, 0); |
252b5132 RH |
4576 | break; |
4577 | ||
4578 | case M_DDIV_3: | |
4579 | dbl = 1; | |
4580 | case M_DIV_3: | |
4581 | s = "mflo"; | |
4582 | goto do_div3; | |
4583 | case M_DREM_3: | |
4584 | dbl = 1; | |
4585 | case M_REM_3: | |
4586 | s = "mfhi"; | |
4587 | do_div3: | |
4588 | if (treg == 0) | |
4589 | { | |
4590 | as_warn (_("Divide by zero.")); | |
4591 | if (mips_trap) | |
2396cfb9 | 4592 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "teq", |
9bd7d936 | 4593 | "s,t,q", 0, 0, 7); |
252b5132 | 4594 | else |
2396cfb9 TS |
4595 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break", |
4596 | "c", 7); | |
252b5132 RH |
4597 | return; |
4598 | } | |
4599 | ||
b34976b6 | 4600 | mips_emit_delays (TRUE); |
252b5132 RH |
4601 | ++mips_opts.noreorder; |
4602 | mips_any_noreorder = 1; | |
4603 | if (mips_trap) | |
4604 | { | |
2396cfb9 | 4605 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "teq", |
9bd7d936 | 4606 | "s,t,q", treg, 0, 7); |
2396cfb9 | 4607 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
9a41af64 | 4608 | dbl ? "ddiv" : "div", "z,s,t", sreg, treg); |
252b5132 RH |
4609 | } |
4610 | else | |
4611 | { | |
4612 | expr1.X_add_number = 8; | |
4613 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, 0); | |
2396cfb9 | 4614 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
9a41af64 | 4615 | dbl ? "ddiv" : "div", "z,s,t", sreg, treg); |
2396cfb9 TS |
4616 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break", |
4617 | "c", 7); | |
252b5132 RH |
4618 | } |
4619 | expr1.X_add_number = -1; | |
4620 | macro_build ((char *) NULL, &icnt, &expr1, | |
4621 | dbl ? "daddiu" : "addiu", | |
4622 | "t,r,j", AT, 0, (int) BFD_RELOC_LO16); | |
4623 | expr1.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16); | |
4624 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, AT); | |
4625 | if (dbl) | |
4626 | { | |
4627 | expr1.X_add_number = 1; | |
4628 | macro_build ((char *) NULL, &icnt, &expr1, "daddiu", "t,r,j", AT, 0, | |
4629 | (int) BFD_RELOC_LO16); | |
2396cfb9 TS |
4630 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsll32", |
4631 | "d,w,<", AT, AT, 31); | |
252b5132 RH |
4632 | } |
4633 | else | |
4634 | { | |
4635 | expr1.X_add_number = 0x80000000; | |
4636 | macro_build ((char *) NULL, &icnt, &expr1, "lui", "t,u", AT, | |
4637 | (int) BFD_RELOC_HI16); | |
4638 | } | |
4639 | if (mips_trap) | |
4640 | { | |
2396cfb9 | 4641 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "teq", |
9bd7d936 | 4642 | "s,t,q", sreg, AT, 6); |
252b5132 RH |
4643 | /* We want to close the noreorder block as soon as possible, so |
4644 | that later insns are available for delay slot filling. */ | |
4645 | --mips_opts.noreorder; | |
4646 | } | |
4647 | else | |
4648 | { | |
4649 | expr1.X_add_number = 8; | |
4650 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", sreg, AT); | |
2396cfb9 TS |
4651 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "", |
4652 | 0); | |
252b5132 RH |
4653 | |
4654 | /* We want to close the noreorder block as soon as possible, so | |
4655 | that later insns are available for delay slot filling. */ | |
4656 | --mips_opts.noreorder; | |
4657 | ||
2396cfb9 TS |
4658 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break", |
4659 | "c", 6); | |
252b5132 | 4660 | } |
2396cfb9 | 4661 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "d", dreg); |
252b5132 RH |
4662 | break; |
4663 | ||
4664 | case M_DIV_3I: | |
4665 | s = "div"; | |
4666 | s2 = "mflo"; | |
4667 | goto do_divi; | |
4668 | case M_DIVU_3I: | |
4669 | s = "divu"; | |
4670 | s2 = "mflo"; | |
4671 | goto do_divi; | |
4672 | case M_REM_3I: | |
4673 | s = "div"; | |
4674 | s2 = "mfhi"; | |
4675 | goto do_divi; | |
4676 | case M_REMU_3I: | |
4677 | s = "divu"; | |
4678 | s2 = "mfhi"; | |
4679 | goto do_divi; | |
4680 | case M_DDIV_3I: | |
4681 | dbl = 1; | |
4682 | s = "ddiv"; | |
4683 | s2 = "mflo"; | |
4684 | goto do_divi; | |
4685 | case M_DDIVU_3I: | |
4686 | dbl = 1; | |
4687 | s = "ddivu"; | |
4688 | s2 = "mflo"; | |
4689 | goto do_divi; | |
4690 | case M_DREM_3I: | |
4691 | dbl = 1; | |
4692 | s = "ddiv"; | |
4693 | s2 = "mfhi"; | |
4694 | goto do_divi; | |
4695 | case M_DREMU_3I: | |
4696 | dbl = 1; | |
4697 | s = "ddivu"; | |
4698 | s2 = "mfhi"; | |
4699 | do_divi: | |
4700 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4701 | { | |
4702 | as_warn (_("Divide by zero.")); | |
4703 | if (mips_trap) | |
2396cfb9 | 4704 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "teq", |
9bd7d936 | 4705 | "s,t,q", 0, 0, 7); |
252b5132 | 4706 | else |
2396cfb9 TS |
4707 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break", |
4708 | "c", 7); | |
252b5132 RH |
4709 | return; |
4710 | } | |
4711 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4712 | { | |
4713 | if (strcmp (s2, "mflo") == 0) | |
ea1fb5dc | 4714 | move_register (&icnt, dreg, sreg); |
252b5132 | 4715 | else |
ea1fb5dc | 4716 | move_register (&icnt, dreg, 0); |
252b5132 RH |
4717 | return; |
4718 | } | |
4719 | if (imm_expr.X_op == O_constant | |
4720 | && imm_expr.X_add_number == -1 | |
4721 | && s[strlen (s) - 1] != 'u') | |
4722 | { | |
4723 | if (strcmp (s2, "mflo") == 0) | |
4724 | { | |
2396cfb9 TS |
4725 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
4726 | dbl ? "dneg" : "neg", "d,w", dreg, sreg); | |
252b5132 RH |
4727 | } |
4728 | else | |
ea1fb5dc | 4729 | move_register (&icnt, dreg, 0); |
252b5132 RH |
4730 | return; |
4731 | } | |
4732 | ||
4733 | load_register (&icnt, AT, &imm_expr, dbl); | |
2396cfb9 TS |
4734 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "z,s,t", |
4735 | sreg, AT); | |
4736 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s2, "d", dreg); | |
252b5132 RH |
4737 | break; |
4738 | ||
4739 | case M_DIVU_3: | |
4740 | s = "divu"; | |
4741 | s2 = "mflo"; | |
4742 | goto do_divu3; | |
4743 | case M_REMU_3: | |
4744 | s = "divu"; | |
4745 | s2 = "mfhi"; | |
4746 | goto do_divu3; | |
4747 | case M_DDIVU_3: | |
4748 | s = "ddivu"; | |
4749 | s2 = "mflo"; | |
4750 | goto do_divu3; | |
4751 | case M_DREMU_3: | |
4752 | s = "ddivu"; | |
4753 | s2 = "mfhi"; | |
4754 | do_divu3: | |
b34976b6 | 4755 | mips_emit_delays (TRUE); |
252b5132 RH |
4756 | ++mips_opts.noreorder; |
4757 | mips_any_noreorder = 1; | |
4758 | if (mips_trap) | |
4759 | { | |
2396cfb9 | 4760 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "teq", |
9bd7d936 | 4761 | "s,t,q", treg, 0, 7); |
2396cfb9 TS |
4762 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "z,s,t", |
4763 | sreg, treg); | |
252b5132 RH |
4764 | /* We want to close the noreorder block as soon as possible, so |
4765 | that later insns are available for delay slot filling. */ | |
4766 | --mips_opts.noreorder; | |
4767 | } | |
4768 | else | |
4769 | { | |
4770 | expr1.X_add_number = 8; | |
4771 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, 0); | |
2396cfb9 TS |
4772 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "z,s,t", |
4773 | sreg, treg); | |
252b5132 RH |
4774 | |
4775 | /* We want to close the noreorder block as soon as possible, so | |
4776 | that later insns are available for delay slot filling. */ | |
4777 | --mips_opts.noreorder; | |
2396cfb9 TS |
4778 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break", |
4779 | "c", 7); | |
252b5132 | 4780 | } |
2396cfb9 | 4781 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s2, "d", dreg); |
252b5132 RH |
4782 | return; |
4783 | ||
4784 | case M_DLA_AB: | |
4785 | dbl = 1; | |
4786 | case M_LA_AB: | |
4787 | /* Load the address of a symbol into a register. If breg is not | |
4788 | zero, we then add a base register to it. */ | |
4789 | ||
3bec30a8 TS |
4790 | if (dbl && HAVE_32BIT_GPRS) |
4791 | as_warn (_("dla used to load 32-bit register")); | |
4792 | ||
c90bbe5b | 4793 | if (! dbl && HAVE_64BIT_OBJECTS) |
3bec30a8 TS |
4794 | as_warn (_("la used to load 64-bit address")); |
4795 | ||
0c11417f MR |
4796 | if (offset_expr.X_op == O_constant |
4797 | && offset_expr.X_add_number >= -0x8000 | |
4798 | && offset_expr.X_add_number < 0x8000) | |
4799 | { | |
4800 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
4801 | (dbl || HAVE_64BIT_ADDRESSES) ? "daddiu" : "addiu", | |
4802 | "t,r,j", treg, sreg, (int) BFD_RELOC_LO16); | |
4803 | return; | |
4804 | } | |
4805 | ||
afdbd6d0 CD |
4806 | if (treg == breg) |
4807 | { | |
4808 | tempreg = AT; | |
4809 | used_at = 1; | |
4810 | } | |
4811 | else | |
4812 | { | |
4813 | tempreg = treg; | |
4814 | used_at = 0; | |
4815 | } | |
4816 | ||
252b5132 RH |
4817 | /* When generating embedded PIC code, we permit expressions of |
4818 | the form | |
afdbd6d0 CD |
4819 | la $treg,foo-bar |
4820 | la $treg,foo-bar($breg) | |
bb2d6cd7 | 4821 | where bar is an address in the current section. These are used |
252b5132 RH |
4822 | when getting the addresses of functions. We don't permit |
4823 | X_add_number to be non-zero, because if the symbol is | |
4824 | external the relaxing code needs to know that any addend is | |
4825 | purely the offset to X_op_symbol. */ | |
4826 | if (mips_pic == EMBEDDED_PIC | |
4827 | && offset_expr.X_op == O_subtract | |
49309057 | 4828 | && (symbol_constant_p (offset_expr.X_op_symbol) |
bb2d6cd7 | 4829 | ? S_GET_SEGMENT (offset_expr.X_op_symbol) == now_seg |
49309057 ILT |
4830 | : (symbol_equated_p (offset_expr.X_op_symbol) |
4831 | && (S_GET_SEGMENT | |
4832 | (symbol_get_value_expression (offset_expr.X_op_symbol) | |
4833 | ->X_add_symbol) | |
bb2d6cd7 | 4834 | == now_seg))) |
bb2d6cd7 GK |
4835 | && (offset_expr.X_add_number == 0 |
4836 | || OUTPUT_FLAVOR == bfd_target_elf_flavour)) | |
252b5132 | 4837 | { |
afdbd6d0 CD |
4838 | if (breg == 0) |
4839 | { | |
4840 | tempreg = treg; | |
4841 | used_at = 0; | |
4842 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
4843 | tempreg, (int) BFD_RELOC_PCREL_HI16_S); | |
4844 | } | |
4845 | else | |
4846 | { | |
4847 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
4848 | tempreg, (int) BFD_RELOC_PCREL_HI16_S); | |
4849 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4d34fb5f | 4850 | (dbl || HAVE_64BIT_ADDRESSES) ? "daddu" : "addu", |
afdbd6d0 CD |
4851 | "d,v,t", tempreg, tempreg, breg); |
4852 | } | |
252b5132 | 4853 | macro_build ((char *) NULL, &icnt, &offset_expr, |
4d34fb5f | 4854 | (dbl || HAVE_64BIT_ADDRESSES) ? "daddiu" : "addiu", |
afdbd6d0 CD |
4855 | "t,r,j", treg, tempreg, (int) BFD_RELOC_PCREL_LO16); |
4856 | if (! used_at) | |
4857 | return; | |
4858 | break; | |
252b5132 RH |
4859 | } |
4860 | ||
4861 | if (offset_expr.X_op != O_symbol | |
4862 | && offset_expr.X_op != O_constant) | |
4863 | { | |
4864 | as_bad (_("expression too complex")); | |
4865 | offset_expr.X_op = O_constant; | |
4866 | } | |
4867 | ||
252b5132 | 4868 | if (offset_expr.X_op == O_constant) |
4d34fb5f TS |
4869 | load_register (&icnt, tempreg, &offset_expr, |
4870 | ((mips_pic == EMBEDDED_PIC || mips_pic == NO_PIC) | |
4871 | ? (dbl || HAVE_64BIT_ADDRESSES) | |
4872 | : HAVE_64BIT_ADDRESSES)); | |
252b5132 RH |
4873 | else if (mips_pic == NO_PIC) |
4874 | { | |
d6bc6245 | 4875 | /* If this is a reference to a GP relative symbol, we want |
cdf6fd85 | 4876 | addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
4877 | Otherwise we want |
4878 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
4879 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
4880 | If we have a constant, we need two instructions anyhow, | |
d6bc6245 | 4881 | so we may as well always use the latter form. |
76b3015f | 4882 | |
d6bc6245 TS |
4883 | With 64bit address space and a usable $at we want |
4884 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
4885 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
4886 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
4887 | daddiu $at,<sym> (BFD_RELOC_LO16) | |
4888 | dsll32 $tempreg,0 | |
3a482fd5 | 4889 | daddu $tempreg,$tempreg,$at |
76b3015f | 4890 | |
c03099e6 | 4891 | If $at is already in use, we use a path which is suboptimal |
d6bc6245 TS |
4892 | on superscalar processors. |
4893 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
4894 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
4895 | dsll $tempreg,16 | |
4896 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
4897 | dsll $tempreg,16 | |
4898 | daddiu $tempreg,<sym> (BFD_RELOC_LO16) | |
4899 | */ | |
f9419b05 | 4900 | char *p = NULL; |
d6bc6245 | 4901 | if (HAVE_64BIT_ADDRESSES) |
252b5132 | 4902 | { |
d6bc6245 TS |
4903 | /* We don't do GP optimization for now because RELAX_ENCODE can't |
4904 | hold the data for such large chunks. */ | |
4905 | ||
460597ba | 4906 | if (used_at == 0 && ! mips_opts.noat) |
98d3f06f KH |
4907 | { |
4908 | macro_build (p, &icnt, &offset_expr, "lui", "t,u", | |
4909 | tempreg, (int) BFD_RELOC_MIPS_HIGHEST); | |
4910 | macro_build (p, &icnt, &offset_expr, "lui", "t,u", | |
4911 | AT, (int) BFD_RELOC_HI16_S); | |
4912 | macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j", | |
4913 | tempreg, tempreg, (int) BFD_RELOC_MIPS_HIGHER); | |
4914 | macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j", | |
4915 | AT, AT, (int) BFD_RELOC_LO16); | |
4916 | macro_build (p, &icnt, (expressionS *) NULL, "dsll32", | |
4917 | "d,w,<", tempreg, tempreg, 0); | |
3a482fd5 MR |
4918 | macro_build (p, &icnt, (expressionS *) NULL, "daddu", |
4919 | "d,v,t", tempreg, tempreg, AT); | |
98d3f06f KH |
4920 | used_at = 1; |
4921 | } | |
4922 | else | |
4923 | { | |
4924 | macro_build (p, &icnt, &offset_expr, "lui", "t,u", | |
4925 | tempreg, (int) BFD_RELOC_MIPS_HIGHEST); | |
4926 | macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j", | |
4927 | tempreg, tempreg, (int) BFD_RELOC_MIPS_HIGHER); | |
4928 | macro_build (p, &icnt, (expressionS *) NULL, "dsll", "d,w,<", | |
4929 | tempreg, tempreg, 16); | |
4930 | macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j", | |
4931 | tempreg, tempreg, (int) BFD_RELOC_HI16_S); | |
4932 | macro_build (p, &icnt, (expressionS *) NULL, "dsll", "d,w,<", | |
4933 | tempreg, tempreg, 16); | |
4934 | macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j", | |
4935 | tempreg, tempreg, (int) BFD_RELOC_LO16); | |
4936 | } | |
4937 | } | |
4938 | else | |
4939 | { | |
4940 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET | |
4941 | && ! nopic_need_relax (offset_expr.X_add_symbol, 1)) | |
4942 | { | |
4943 | frag_grow (20); | |
4944 | macro_build ((char *) NULL, &icnt, &offset_expr, "addiu", | |
c9914766 TS |
4945 | "t,r,j", tempreg, mips_gp_register, |
4946 | (int) BFD_RELOC_GPREL16); | |
98d3f06f KH |
4947 | p = frag_var (rs_machine_dependent, 8, 0, |
4948 | RELAX_ENCODE (4, 8, 0, 4, 0, | |
4949 | mips_opts.warn_about_macros), | |
4950 | offset_expr.X_add_symbol, 0, NULL); | |
4951 | } | |
4952 | macro_build_lui (p, &icnt, &offset_expr, tempreg); | |
4953 | if (p != NULL) | |
4954 | p += 4; | |
4955 | macro_build (p, &icnt, &offset_expr, "addiu", | |
4956 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); | |
4957 | } | |
252b5132 RH |
4958 | } |
4959 | else if (mips_pic == SVR4_PIC && ! mips_big_got) | |
4960 | { | |
9117d219 NC |
4961 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
4962 | ||
252b5132 RH |
4963 | /* If this is a reference to an external symbol, and there |
4964 | is no constant, we want | |
4965 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
9117d219 NC |
4966 | or if tempreg is PIC_CALL_REG |
4967 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) | |
252b5132 RH |
4968 | For a local symbol, we want |
4969 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4970 | nop | |
4971 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
4972 | ||
4973 | If we have a small constant, and this is a reference to | |
4974 | an external symbol, we want | |
4975 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4976 | nop | |
4977 | addiu $tempreg,$tempreg,<constant> | |
4978 | For a local symbol, we want the same instruction | |
4979 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
4980 | addiu instruction. | |
4981 | ||
4982 | If we have a large constant, and this is a reference to | |
4983 | an external symbol, we want | |
4984 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4985 | lui $at,<hiconstant> | |
4986 | addiu $at,$at,<loconstant> | |
4987 | addu $tempreg,$tempreg,$at | |
4988 | For a local symbol, we want the same instruction | |
4989 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
ed6fb7bd SC |
4990 | addiu instruction. |
4991 | ||
4992 | For NewABI, we want for local or external data addresses | |
4993 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
4994 | For a local function symbol, we want | |
4995 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
4996 | nop | |
4997 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_MIPS_GOT_OFST) | |
4998 | */ | |
4999 | ||
252b5132 RH |
5000 | expr1.X_add_number = offset_expr.X_add_number; |
5001 | offset_expr.X_add_number = 0; | |
5002 | frag_grow (32); | |
9117d219 NC |
5003 | if (expr1.X_add_number == 0 && tempreg == PIC_CALL_REG) |
5004 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16; | |
ed6fb7bd SC |
5005 | else if (HAVE_NEWABI) |
5006 | lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_DISP; | |
4d34fb5f TS |
5007 | macro_build ((char *) NULL, &icnt, &offset_expr, |
5008 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", | |
c9914766 | 5009 | "t,o(b)", tempreg, lw_reloc_type, mips_gp_register); |
252b5132 RH |
5010 | if (expr1.X_add_number == 0) |
5011 | { | |
5012 | int off; | |
f9419b05 | 5013 | char *p; |
252b5132 RH |
5014 | |
5015 | if (breg == 0) | |
5016 | off = 0; | |
5017 | else | |
5018 | { | |
5019 | /* We're going to put in an addu instruction using | |
5020 | tempreg, so we may as well insert the nop right | |
5021 | now. */ | |
5022 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5023 | "nop", ""); | |
5024 | off = 4; | |
5025 | } | |
5026 | p = frag_var (rs_machine_dependent, 8 - off, 0, | |
5027 | RELAX_ENCODE (0, 8 - off, -4 - off, 4 - off, 0, | |
5028 | (breg == 0 | |
5029 | ? mips_opts.warn_about_macros | |
5030 | : 0)), | |
c4e7957c | 5031 | offset_expr.X_add_symbol, 0, NULL); |
252b5132 RH |
5032 | if (breg == 0) |
5033 | { | |
5034 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
5035 | p += 4; | |
5036 | } | |
5037 | macro_build (p, &icnt, &expr1, | |
ca4e0257 | 5038 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
252b5132 RH |
5039 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
5040 | /* FIXME: If breg == 0, and the next instruction uses | |
5041 | $tempreg, then if this variant case is used an extra | |
5042 | nop will be generated. */ | |
5043 | } | |
5044 | else if (expr1.X_add_number >= -0x8000 | |
5045 | && expr1.X_add_number < 0x8000) | |
5046 | { | |
5047 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5048 | "nop", ""); | |
5049 | macro_build ((char *) NULL, &icnt, &expr1, | |
ca4e0257 | 5050 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
252b5132 | 5051 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
c4e7957c TS |
5052 | frag_var (rs_machine_dependent, 0, 0, |
5053 | RELAX_ENCODE (0, 0, -12, -4, 0, 0), | |
5054 | offset_expr.X_add_symbol, 0, NULL); | |
252b5132 RH |
5055 | } |
5056 | else | |
5057 | { | |
5058 | int off1; | |
5059 | ||
5060 | /* If we are going to add in a base register, and the | |
5061 | target register and the base register are the same, | |
5062 | then we are using AT as a temporary register. Since | |
5063 | we want to load the constant into AT, we add our | |
5064 | current AT (from the global offset table) and the | |
5065 | register into the register now, and pretend we were | |
5066 | not using a base register. */ | |
5067 | if (breg != treg) | |
5068 | off1 = 0; | |
5069 | else | |
5070 | { | |
5071 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5072 | "nop", ""); | |
5073 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 5074 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
5075 | "d,v,t", treg, AT, breg); |
5076 | breg = 0; | |
5077 | tempreg = treg; | |
5078 | off1 = -8; | |
5079 | } | |
5080 | ||
5081 | /* Set mips_optimize around the lui instruction to avoid | |
5082 | inserting an unnecessary nop after the lw. */ | |
5083 | hold_mips_optimize = mips_optimize; | |
5084 | mips_optimize = 2; | |
c4e7957c | 5085 | macro_build_lui (NULL, &icnt, &expr1, AT); |
252b5132 RH |
5086 | mips_optimize = hold_mips_optimize; |
5087 | ||
5088 | macro_build ((char *) NULL, &icnt, &expr1, | |
ca4e0257 | 5089 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
252b5132 RH |
5090 | "t,r,j", AT, AT, (int) BFD_RELOC_LO16); |
5091 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 5092 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 | 5093 | "d,v,t", tempreg, tempreg, AT); |
c4e7957c TS |
5094 | frag_var (rs_machine_dependent, 0, 0, |
5095 | RELAX_ENCODE (0, 0, -16 + off1, -8, 0, 0), | |
5096 | offset_expr.X_add_symbol, 0, NULL); | |
252b5132 RH |
5097 | used_at = 1; |
5098 | } | |
5099 | } | |
5100 | else if (mips_pic == SVR4_PIC) | |
5101 | { | |
5102 | int gpdel; | |
f9419b05 | 5103 | char *p; |
9117d219 NC |
5104 | int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; |
5105 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; | |
ed6fb7bd | 5106 | int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
252b5132 RH |
5107 | |
5108 | /* This is the large GOT case. If this is a reference to an | |
5109 | external symbol, and there is no constant, we want | |
5110 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5111 | addu $tempreg,$tempreg,$gp | |
5112 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
9117d219 NC |
5113 | or if tempreg is PIC_CALL_REG |
5114 | lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) | |
5115 | addu $tempreg,$tempreg,$gp | |
5116 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) | |
252b5132 RH |
5117 | For a local symbol, we want |
5118 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5119 | nop | |
5120 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
5121 | ||
5122 | If we have a small constant, and this is a reference to | |
5123 | an external symbol, we want | |
5124 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5125 | addu $tempreg,$tempreg,$gp | |
5126 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5127 | nop | |
5128 | addiu $tempreg,$tempreg,<constant> | |
5129 | For a local symbol, we want | |
5130 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5131 | nop | |
5132 | addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16) | |
5133 | ||
5134 | If we have a large constant, and this is a reference to | |
5135 | an external symbol, we want | |
5136 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5137 | addu $tempreg,$tempreg,$gp | |
5138 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5139 | lui $at,<hiconstant> | |
5140 | addiu $at,$at,<loconstant> | |
5141 | addu $tempreg,$tempreg,$at | |
5142 | For a local symbol, we want | |
5143 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5144 | lui $at,<hiconstant> | |
5145 | addiu $at,$at,<loconstant> (BFD_RELOC_LO16) | |
5146 | addu $tempreg,$tempreg,$at | |
438c16b8 | 5147 | |
ed6fb7bd SC |
5148 | For NewABI, we want for local data addresses |
5149 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
438c16b8 | 5150 | */ |
438c16b8 | 5151 | |
252b5132 RH |
5152 | expr1.X_add_number = offset_expr.X_add_number; |
5153 | offset_expr.X_add_number = 0; | |
5154 | frag_grow (52); | |
f7ea7ef2 | 5155 | if (reg_needs_delay (mips_gp_register)) |
252b5132 RH |
5156 | gpdel = 4; |
5157 | else | |
5158 | gpdel = 0; | |
9117d219 NC |
5159 | if (expr1.X_add_number == 0 && tempreg == PIC_CALL_REG) |
5160 | { | |
5161 | lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; | |
5162 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; | |
5163 | } | |
252b5132 | 5164 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", |
9117d219 | 5165 | tempreg, lui_reloc_type); |
252b5132 | 5166 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
ca4e0257 | 5167 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
c9914766 | 5168 | "d,v,t", tempreg, tempreg, mips_gp_register); |
252b5132 | 5169 | macro_build ((char *) NULL, &icnt, &offset_expr, |
4d34fb5f | 5170 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", |
9117d219 | 5171 | "t,o(b)", tempreg, lw_reloc_type, tempreg); |
252b5132 RH |
5172 | if (expr1.X_add_number == 0) |
5173 | { | |
5174 | int off; | |
5175 | ||
5176 | if (breg == 0) | |
5177 | off = 0; | |
5178 | else | |
5179 | { | |
5180 | /* We're going to put in an addu instruction using | |
5181 | tempreg, so we may as well insert the nop right | |
5182 | now. */ | |
5183 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5184 | "nop", ""); | |
5185 | off = 4; | |
5186 | } | |
5187 | ||
5188 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, | |
5189 | RELAX_ENCODE (12 + off, 12 + gpdel, gpdel, | |
5190 | 8 + gpdel, 0, | |
5191 | (breg == 0 | |
5192 | ? mips_opts.warn_about_macros | |
5193 | : 0)), | |
c4e7957c | 5194 | offset_expr.X_add_symbol, 0, NULL); |
252b5132 RH |
5195 | } |
5196 | else if (expr1.X_add_number >= -0x8000 | |
5197 | && expr1.X_add_number < 0x8000) | |
5198 | { | |
5199 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5200 | "nop", ""); | |
5201 | macro_build ((char *) NULL, &icnt, &expr1, | |
ca4e0257 | 5202 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
252b5132 RH |
5203 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
5204 | ||
5205 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, | |
5206 | RELAX_ENCODE (20, 12 + gpdel, gpdel, 8 + gpdel, 0, | |
5207 | (breg == 0 | |
5208 | ? mips_opts.warn_about_macros | |
5209 | : 0)), | |
c4e7957c | 5210 | offset_expr.X_add_symbol, 0, NULL); |
252b5132 RH |
5211 | } |
5212 | else | |
5213 | { | |
5214 | int adj, dreg; | |
5215 | ||
5216 | /* If we are going to add in a base register, and the | |
5217 | target register and the base register are the same, | |
5218 | then we are using AT as a temporary register. Since | |
5219 | we want to load the constant into AT, we add our | |
5220 | current AT (from the global offset table) and the | |
5221 | register into the register now, and pretend we were | |
5222 | not using a base register. */ | |
5223 | if (breg != treg) | |
5224 | { | |
5225 | adj = 0; | |
5226 | dreg = tempreg; | |
5227 | } | |
5228 | else | |
5229 | { | |
5230 | assert (tempreg == AT); | |
5231 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5232 | "nop", ""); | |
5233 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 5234 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
5235 | "d,v,t", treg, AT, breg); |
5236 | dreg = treg; | |
5237 | adj = 8; | |
5238 | } | |
5239 | ||
5240 | /* Set mips_optimize around the lui instruction to avoid | |
5241 | inserting an unnecessary nop after the lw. */ | |
5242 | hold_mips_optimize = mips_optimize; | |
5243 | mips_optimize = 2; | |
c4e7957c | 5244 | macro_build_lui (NULL, &icnt, &expr1, AT); |
252b5132 RH |
5245 | mips_optimize = hold_mips_optimize; |
5246 | ||
5247 | macro_build ((char *) NULL, &icnt, &expr1, | |
ca4e0257 | 5248 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
252b5132 RH |
5249 | "t,r,j", AT, AT, (int) BFD_RELOC_LO16); |
5250 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 5251 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
5252 | "d,v,t", dreg, dreg, AT); |
5253 | ||
5254 | p = frag_var (rs_machine_dependent, 16 + gpdel + adj, 0, | |
5255 | RELAX_ENCODE (24 + adj, 16 + gpdel + adj, gpdel, | |
5256 | 8 + gpdel, 0, | |
5257 | (breg == 0 | |
5258 | ? mips_opts.warn_about_macros | |
5259 | : 0)), | |
c4e7957c | 5260 | offset_expr.X_add_symbol, 0, NULL); |
252b5132 RH |
5261 | |
5262 | used_at = 1; | |
5263 | } | |
5264 | ||
5265 | if (gpdel > 0) | |
5266 | { | |
5267 | /* This is needed because this instruction uses $gp, but | |
5268 | the first instruction on the main stream does not. */ | |
5269 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
5270 | p += 4; | |
5271 | } | |
ed6fb7bd SC |
5272 | |
5273 | if (HAVE_NEWABI) | |
5274 | local_reloc_type = (int) BFD_RELOC_MIPS_GOT_DISP; | |
252b5132 | 5275 | macro_build (p, &icnt, &offset_expr, |
4d34fb5f | 5276 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", |
ed6fb7bd SC |
5277 | "t,o(b)", tempreg, |
5278 | local_reloc_type, | |
c9914766 | 5279 | mips_gp_register); |
252b5132 | 5280 | p += 4; |
ed6fb7bd SC |
5281 | if (expr1.X_add_number == 0 && HAVE_NEWABI) |
5282 | { | |
5283 | /* BFD_RELOC_MIPS_GOT_DISP is sufficient for newabi */ | |
5284 | } | |
5285 | else | |
5286 | if (expr1.X_add_number >= -0x8000 | |
252b5132 RH |
5287 | && expr1.X_add_number < 0x8000) |
5288 | { | |
5289 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
5290 | p += 4; | |
5291 | macro_build (p, &icnt, &expr1, | |
ca4e0257 | 5292 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
252b5132 RH |
5293 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
5294 | /* FIXME: If add_number is 0, and there was no base | |
5295 | register, the external symbol case ended with a load, | |
5296 | so if the symbol turns out to not be external, and | |
5297 | the next instruction uses tempreg, an unnecessary nop | |
5298 | will be inserted. */ | |
5299 | } | |
5300 | else | |
5301 | { | |
5302 | if (breg == treg) | |
5303 | { | |
5304 | /* We must add in the base register now, as in the | |
5305 | external symbol case. */ | |
5306 | assert (tempreg == AT); | |
5307 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
5308 | p += 4; | |
5309 | macro_build (p, &icnt, (expressionS *) NULL, | |
ca4e0257 | 5310 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
5311 | "d,v,t", treg, AT, breg); |
5312 | p += 4; | |
5313 | tempreg = treg; | |
5314 | /* We set breg to 0 because we have arranged to add | |
5315 | it in in both cases. */ | |
5316 | breg = 0; | |
5317 | } | |
5318 | ||
5319 | macro_build_lui (p, &icnt, &expr1, AT); | |
5320 | p += 4; | |
5321 | macro_build (p, &icnt, &expr1, | |
ca4e0257 | 5322 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
252b5132 RH |
5323 | "t,r,j", AT, AT, (int) BFD_RELOC_LO16); |
5324 | p += 4; | |
5325 | macro_build (p, &icnt, (expressionS *) NULL, | |
ca4e0257 | 5326 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
5327 | "d,v,t", tempreg, tempreg, AT); |
5328 | p += 4; | |
5329 | } | |
5330 | } | |
5331 | else if (mips_pic == EMBEDDED_PIC) | |
5332 | { | |
5333 | /* We use | |
cdf6fd85 | 5334 | addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
5335 | */ |
5336 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
c9914766 TS |
5337 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", "t,r,j", |
5338 | tempreg, mips_gp_register, (int) BFD_RELOC_GPREL16); | |
252b5132 RH |
5339 | } |
5340 | else | |
5341 | abort (); | |
5342 | ||
5343 | if (breg != 0) | |
4d34fb5f TS |
5344 | { |
5345 | char *s; | |
5346 | ||
5347 | if (mips_pic == EMBEDDED_PIC || mips_pic == NO_PIC) | |
5348 | s = (dbl || HAVE_64BIT_ADDRESSES) ? "daddu" : "addu"; | |
5349 | else | |
5350 | s = HAVE_64BIT_ADDRESSES ? "daddu" : "addu"; | |
5351 | ||
5352 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, | |
5353 | "d,v,t", treg, tempreg, breg); | |
5354 | } | |
252b5132 RH |
5355 | |
5356 | if (! used_at) | |
5357 | return; | |
5358 | ||
5359 | break; | |
5360 | ||
5361 | case M_J_A: | |
5362 | /* The j instruction may not be used in PIC code, since it | |
5363 | requires an absolute address. We convert it to a b | |
5364 | instruction. */ | |
5365 | if (mips_pic == NO_PIC) | |
5366 | macro_build ((char *) NULL, &icnt, &offset_expr, "j", "a"); | |
5367 | else | |
5368 | macro_build ((char *) NULL, &icnt, &offset_expr, "b", "p"); | |
5369 | return; | |
5370 | ||
5371 | /* The jal instructions must be handled as macros because when | |
5372 | generating PIC code they expand to multi-instruction | |
5373 | sequences. Normally they are simple instructions. */ | |
5374 | case M_JAL_1: | |
5375 | dreg = RA; | |
5376 | /* Fall through. */ | |
5377 | case M_JAL_2: | |
5378 | if (mips_pic == NO_PIC | |
5379 | || mips_pic == EMBEDDED_PIC) | |
5380 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "jalr", | |
5381 | "d,s", dreg, sreg); | |
5382 | else if (mips_pic == SVR4_PIC) | |
5383 | { | |
5384 | if (sreg != PIC_CALL_REG) | |
5385 | as_warn (_("MIPS PIC call to register other than $25")); | |
bdaaa2e1 | 5386 | |
252b5132 RH |
5387 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "jalr", |
5388 | "d,s", dreg, sreg); | |
6478892d | 5389 | if (! HAVE_NEWABI) |
252b5132 | 5390 | { |
6478892d TS |
5391 | if (mips_cprestore_offset < 0) |
5392 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
5393 | else | |
5394 | { | |
7a621144 DJ |
5395 | if (! mips_frame_reg_valid) |
5396 | { | |
5397 | as_warn (_("No .frame pseudo-op used in PIC code")); | |
5398 | /* Quiet this warning. */ | |
5399 | mips_frame_reg_valid = 1; | |
5400 | } | |
5401 | if (! mips_cprestore_valid) | |
5402 | { | |
5403 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
5404 | /* Quiet this warning. */ | |
5405 | mips_cprestore_valid = 1; | |
5406 | } | |
6478892d | 5407 | expr1.X_add_number = mips_cprestore_offset; |
885add95 CD |
5408 | macro_build_ldst_constoffset ((char *) NULL, &icnt, &expr1, |
5409 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", | |
5410 | mips_gp_register, mips_frame_reg); | |
6478892d | 5411 | } |
252b5132 RH |
5412 | } |
5413 | } | |
5414 | else | |
5415 | abort (); | |
5416 | ||
5417 | return; | |
5418 | ||
5419 | case M_JAL_A: | |
5420 | if (mips_pic == NO_PIC) | |
5421 | macro_build ((char *) NULL, &icnt, &offset_expr, "jal", "a"); | |
5422 | else if (mips_pic == SVR4_PIC) | |
5423 | { | |
f9419b05 TS |
5424 | char *p; |
5425 | ||
252b5132 RH |
5426 | /* If this is a reference to an external symbol, and we are |
5427 | using a small GOT, we want | |
5428 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16) | |
5429 | nop | |
f9419b05 | 5430 | jalr $ra,$25 |
252b5132 RH |
5431 | nop |
5432 | lw $gp,cprestore($sp) | |
5433 | The cprestore value is set using the .cprestore | |
5434 | pseudo-op. If we are using a big GOT, we want | |
5435 | lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16) | |
5436 | addu $25,$25,$gp | |
5437 | lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16) | |
5438 | nop | |
f9419b05 | 5439 | jalr $ra,$25 |
252b5132 RH |
5440 | nop |
5441 | lw $gp,cprestore($sp) | |
5442 | If the symbol is not external, we want | |
5443 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5444 | nop | |
5445 | addiu $25,$25,<sym> (BFD_RELOC_LO16) | |
f9419b05 | 5446 | jalr $ra,$25 |
252b5132 | 5447 | nop |
438c16b8 TS |
5448 | lw $gp,cprestore($sp) |
5449 | For NewABI, we want | |
5450 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
5451 | jalr $ra,$25 (BFD_RELOC_MIPS_JALR) | |
5452 | */ | |
5453 | if (HAVE_NEWABI) | |
252b5132 RH |
5454 | { |
5455 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
ca4e0257 | 5456 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", |
252b5132 | 5457 | "t,o(b)", PIC_CALL_REG, |
438c16b8 TS |
5458 | (int) BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); |
5459 | macro_build_jalr (icnt, &offset_expr); | |
252b5132 RH |
5460 | } |
5461 | else | |
5462 | { | |
438c16b8 TS |
5463 | frag_grow (40); |
5464 | if (! mips_big_got) | |
5465 | { | |
5466 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
5467 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", | |
5468 | "t,o(b)", PIC_CALL_REG, | |
5469 | (int) BFD_RELOC_MIPS_CALL16, mips_gp_register); | |
5470 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5471 | "nop", ""); | |
5472 | p = frag_var (rs_machine_dependent, 4, 0, | |
5473 | RELAX_ENCODE (0, 4, -8, 0, 0, 0), | |
5474 | offset_expr.X_add_symbol, 0, NULL); | |
5475 | } | |
252b5132 | 5476 | else |
252b5132 | 5477 | { |
438c16b8 TS |
5478 | int gpdel; |
5479 | ||
5480 | if (reg_needs_delay (mips_gp_register)) | |
5481 | gpdel = 4; | |
5482 | else | |
5483 | gpdel = 0; | |
5484 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", | |
5485 | "t,u", PIC_CALL_REG, | |
5486 | (int) BFD_RELOC_MIPS_CALL_HI16); | |
5487 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5488 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", | |
5489 | "d,v,t", PIC_CALL_REG, PIC_CALL_REG, | |
5490 | mips_gp_register); | |
5491 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
5492 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", | |
5493 | "t,o(b)", PIC_CALL_REG, | |
5494 | (int) BFD_RELOC_MIPS_CALL_LO16, PIC_CALL_REG); | |
5495 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5496 | "nop", ""); | |
5497 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, | |
5498 | RELAX_ENCODE (16, 12 + gpdel, gpdel, | |
5499 | 8 + gpdel, 0, 0), | |
5500 | offset_expr.X_add_symbol, 0, NULL); | |
5501 | if (gpdel > 0) | |
5502 | { | |
5503 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
5504 | p += 4; | |
5505 | } | |
5506 | macro_build (p, &icnt, &offset_expr, | |
5507 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", | |
5508 | "t,o(b)", PIC_CALL_REG, | |
5509 | (int) BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
5510 | p += 4; | |
252b5132 RH |
5511 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); |
5512 | p += 4; | |
5513 | } | |
5514 | macro_build (p, &icnt, &offset_expr, | |
438c16b8 TS |
5515 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
5516 | "t,r,j", PIC_CALL_REG, PIC_CALL_REG, | |
5517 | (int) BFD_RELOC_LO16); | |
5518 | macro_build_jalr (icnt, &offset_expr); | |
5519 | ||
6478892d TS |
5520 | if (mips_cprestore_offset < 0) |
5521 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
5522 | else | |
5523 | { | |
7a621144 DJ |
5524 | if (! mips_frame_reg_valid) |
5525 | { | |
5526 | as_warn (_("No .frame pseudo-op used in PIC code")); | |
5527 | /* Quiet this warning. */ | |
5528 | mips_frame_reg_valid = 1; | |
5529 | } | |
5530 | if (! mips_cprestore_valid) | |
5531 | { | |
5532 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
5533 | /* Quiet this warning. */ | |
5534 | mips_cprestore_valid = 1; | |
5535 | } | |
6478892d TS |
5536 | if (mips_opts.noreorder) |
5537 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
98d3f06f | 5538 | "nop", ""); |
6478892d | 5539 | expr1.X_add_number = mips_cprestore_offset; |
885add95 CD |
5540 | macro_build_ldst_constoffset ((char *) NULL, &icnt, &expr1, |
5541 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", | |
5542 | mips_gp_register, mips_frame_reg); | |
6478892d | 5543 | } |
252b5132 RH |
5544 | } |
5545 | } | |
5546 | else if (mips_pic == EMBEDDED_PIC) | |
5547 | { | |
5548 | macro_build ((char *) NULL, &icnt, &offset_expr, "bal", "p"); | |
5549 | /* The linker may expand the call to a longer sequence which | |
5550 | uses $at, so we must break rather than return. */ | |
5551 | break; | |
5552 | } | |
5553 | else | |
5554 | abort (); | |
5555 | ||
5556 | return; | |
5557 | ||
5558 | case M_LB_AB: | |
5559 | s = "lb"; | |
5560 | goto ld; | |
5561 | case M_LBU_AB: | |
5562 | s = "lbu"; | |
5563 | goto ld; | |
5564 | case M_LH_AB: | |
5565 | s = "lh"; | |
5566 | goto ld; | |
5567 | case M_LHU_AB: | |
5568 | s = "lhu"; | |
5569 | goto ld; | |
5570 | case M_LW_AB: | |
5571 | s = "lw"; | |
5572 | goto ld; | |
5573 | case M_LWC0_AB: | |
5574 | s = "lwc0"; | |
bdaaa2e1 | 5575 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5576 | coproc = 1; |
5577 | goto ld; | |
5578 | case M_LWC1_AB: | |
5579 | s = "lwc1"; | |
bdaaa2e1 | 5580 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5581 | coproc = 1; |
5582 | goto ld; | |
5583 | case M_LWC2_AB: | |
5584 | s = "lwc2"; | |
bdaaa2e1 | 5585 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5586 | coproc = 1; |
5587 | goto ld; | |
5588 | case M_LWC3_AB: | |
5589 | s = "lwc3"; | |
bdaaa2e1 | 5590 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5591 | coproc = 1; |
5592 | goto ld; | |
5593 | case M_LWL_AB: | |
5594 | s = "lwl"; | |
5595 | lr = 1; | |
5596 | goto ld; | |
5597 | case M_LWR_AB: | |
5598 | s = "lwr"; | |
5599 | lr = 1; | |
5600 | goto ld; | |
5601 | case M_LDC1_AB: | |
ec68c924 | 5602 | if (mips_arch == CPU_R4650) |
252b5132 RH |
5603 | { |
5604 | as_bad (_("opcode not supported on this processor")); | |
5605 | return; | |
5606 | } | |
5607 | s = "ldc1"; | |
bdaaa2e1 | 5608 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5609 | coproc = 1; |
5610 | goto ld; | |
5611 | case M_LDC2_AB: | |
5612 | s = "ldc2"; | |
bdaaa2e1 | 5613 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5614 | coproc = 1; |
5615 | goto ld; | |
5616 | case M_LDC3_AB: | |
5617 | s = "ldc3"; | |
bdaaa2e1 | 5618 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5619 | coproc = 1; |
5620 | goto ld; | |
5621 | case M_LDL_AB: | |
5622 | s = "ldl"; | |
5623 | lr = 1; | |
5624 | goto ld; | |
5625 | case M_LDR_AB: | |
5626 | s = "ldr"; | |
5627 | lr = 1; | |
5628 | goto ld; | |
5629 | case M_LL_AB: | |
5630 | s = "ll"; | |
5631 | goto ld; | |
5632 | case M_LLD_AB: | |
5633 | s = "lld"; | |
5634 | goto ld; | |
5635 | case M_LWU_AB: | |
5636 | s = "lwu"; | |
5637 | ld: | |
5638 | if (breg == treg || coproc || lr) | |
5639 | { | |
5640 | tempreg = AT; | |
5641 | used_at = 1; | |
5642 | } | |
5643 | else | |
5644 | { | |
5645 | tempreg = treg; | |
5646 | used_at = 0; | |
5647 | } | |
5648 | goto ld_st; | |
5649 | case M_SB_AB: | |
5650 | s = "sb"; | |
5651 | goto st; | |
5652 | case M_SH_AB: | |
5653 | s = "sh"; | |
5654 | goto st; | |
5655 | case M_SW_AB: | |
5656 | s = "sw"; | |
5657 | goto st; | |
5658 | case M_SWC0_AB: | |
5659 | s = "swc0"; | |
bdaaa2e1 | 5660 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5661 | coproc = 1; |
5662 | goto st; | |
5663 | case M_SWC1_AB: | |
5664 | s = "swc1"; | |
bdaaa2e1 | 5665 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5666 | coproc = 1; |
5667 | goto st; | |
5668 | case M_SWC2_AB: | |
5669 | s = "swc2"; | |
bdaaa2e1 | 5670 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5671 | coproc = 1; |
5672 | goto st; | |
5673 | case M_SWC3_AB: | |
5674 | s = "swc3"; | |
bdaaa2e1 | 5675 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5676 | coproc = 1; |
5677 | goto st; | |
5678 | case M_SWL_AB: | |
5679 | s = "swl"; | |
5680 | goto st; | |
5681 | case M_SWR_AB: | |
5682 | s = "swr"; | |
5683 | goto st; | |
5684 | case M_SC_AB: | |
5685 | s = "sc"; | |
5686 | goto st; | |
5687 | case M_SCD_AB: | |
5688 | s = "scd"; | |
5689 | goto st; | |
5690 | case M_SDC1_AB: | |
ec68c924 | 5691 | if (mips_arch == CPU_R4650) |
252b5132 RH |
5692 | { |
5693 | as_bad (_("opcode not supported on this processor")); | |
5694 | return; | |
5695 | } | |
5696 | s = "sdc1"; | |
5697 | coproc = 1; | |
bdaaa2e1 | 5698 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5699 | goto st; |
5700 | case M_SDC2_AB: | |
5701 | s = "sdc2"; | |
bdaaa2e1 | 5702 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5703 | coproc = 1; |
5704 | goto st; | |
5705 | case M_SDC3_AB: | |
5706 | s = "sdc3"; | |
bdaaa2e1 | 5707 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5708 | coproc = 1; |
5709 | goto st; | |
5710 | case M_SDL_AB: | |
5711 | s = "sdl"; | |
5712 | goto st; | |
5713 | case M_SDR_AB: | |
5714 | s = "sdr"; | |
5715 | st: | |
5716 | tempreg = AT; | |
5717 | used_at = 1; | |
5718 | ld_st: | |
bdaaa2e1 | 5719 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5720 | if (mask == M_LWC1_AB |
5721 | || mask == M_SWC1_AB | |
5722 | || mask == M_LDC1_AB | |
5723 | || mask == M_SDC1_AB | |
5724 | || mask == M_L_DAB | |
5725 | || mask == M_S_DAB) | |
5726 | fmt = "T,o(b)"; | |
5727 | else if (coproc) | |
5728 | fmt = "E,o(b)"; | |
5729 | else | |
5730 | fmt = "t,o(b)"; | |
5731 | ||
afdbd6d0 CD |
5732 | /* For embedded PIC, we allow loads where the offset is calculated |
5733 | by subtracting a symbol in the current segment from an unknown | |
5734 | symbol, relative to a base register, e.g.: | |
5735 | <op> $treg, <sym>-<localsym>($breg) | |
5736 | This is used by the compiler for switch statements. */ | |
76b3015f | 5737 | if (mips_pic == EMBEDDED_PIC |
afdbd6d0 CD |
5738 | && offset_expr.X_op == O_subtract |
5739 | && (symbol_constant_p (offset_expr.X_op_symbol) | |
5740 | ? S_GET_SEGMENT (offset_expr.X_op_symbol) == now_seg | |
5741 | : (symbol_equated_p (offset_expr.X_op_symbol) | |
5742 | && (S_GET_SEGMENT | |
5743 | (symbol_get_value_expression (offset_expr.X_op_symbol) | |
5744 | ->X_add_symbol) | |
5745 | == now_seg))) | |
5746 | && breg != 0 | |
5747 | && (offset_expr.X_add_number == 0 | |
5748 | || OUTPUT_FLAVOR == bfd_target_elf_flavour)) | |
5749 | { | |
5750 | /* For this case, we output the instructions: | |
5751 | lui $tempreg,<sym> (BFD_RELOC_PCREL_HI16_S) | |
5752 | addiu $tempreg,$tempreg,$breg | |
5753 | <op> $treg,<sym>($tempreg) (BFD_RELOC_PCREL_LO16) | |
5754 | If the relocation would fit entirely in 16 bits, it would be | |
5755 | nice to emit: | |
5756 | <op> $treg,<sym>($breg) (BFD_RELOC_PCREL_LO16) | |
5757 | instead, but that seems quite difficult. */ | |
5758 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
5759 | tempreg, (int) BFD_RELOC_PCREL_HI16_S); | |
5760 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5761 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
5762 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) | |
5763 | ? "addu" : "daddu"), | |
5764 | "d,v,t", tempreg, tempreg, breg); | |
5765 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, treg, | |
5766 | (int) BFD_RELOC_PCREL_LO16, tempreg); | |
5767 | if (! used_at) | |
5768 | return; | |
5769 | break; | |
5770 | } | |
5771 | ||
252b5132 RH |
5772 | if (offset_expr.X_op != O_constant |
5773 | && offset_expr.X_op != O_symbol) | |
5774 | { | |
5775 | as_bad (_("expression too complex")); | |
5776 | offset_expr.X_op = O_constant; | |
5777 | } | |
5778 | ||
5779 | /* A constant expression in PIC code can be handled just as it | |
5780 | is in non PIC code. */ | |
5781 | if (mips_pic == NO_PIC | |
5782 | || offset_expr.X_op == O_constant) | |
5783 | { | |
f9419b05 TS |
5784 | char *p; |
5785 | ||
252b5132 RH |
5786 | /* If this is a reference to a GP relative symbol, and there |
5787 | is no base register, we want | |
cdf6fd85 | 5788 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
252b5132 RH |
5789 | Otherwise, if there is no base register, we want |
5790 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
5791 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
5792 | If we have a constant, we need two instructions anyhow, | |
5793 | so we always use the latter form. | |
5794 | ||
5795 | If we have a base register, and this is a reference to a | |
5796 | GP relative symbol, we want | |
5797 | addu $tempreg,$breg,$gp | |
cdf6fd85 | 5798 | <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16) |
252b5132 RH |
5799 | Otherwise we want |
5800 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
5801 | addu $tempreg,$tempreg,$breg | |
5802 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
d6bc6245 | 5803 | With a constant we always use the latter case. |
76b3015f | 5804 | |
d6bc6245 TS |
5805 | With 64bit address space and no base register and $at usable, |
5806 | we want | |
5807 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5808 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
5809 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5810 | dsll32 $tempreg,0 | |
5811 | daddu $tempreg,$at | |
5812 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
5813 | If we have a base register, we want | |
5814 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5815 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
5816 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5817 | daddu $at,$breg | |
5818 | dsll32 $tempreg,0 | |
5819 | daddu $tempreg,$at | |
5820 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
5821 | ||
5822 | Without $at we can't generate the optimal path for superscalar | |
5823 | processors here since this would require two temporary registers. | |
5824 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5825 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5826 | dsll $tempreg,16 | |
5827 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
5828 | dsll $tempreg,16 | |
5829 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
5830 | If we have a base register, we want | |
5831 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5832 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5833 | dsll $tempreg,16 | |
5834 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
5835 | dsll $tempreg,16 | |
5836 | daddu $tempreg,$tempreg,$breg | |
5837 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
6373ee54 CD |
5838 | |
5839 | If we have 64-bit addresses, as an optimization, for | |
5840 | addresses which are 32-bit constants (e.g. kseg0/kseg1 | |
5841 | addresses) we fall back to the 32-bit address generation | |
78d32a17 MR |
5842 | mechanism since it is more efficient. Note that due to |
5843 | the signed offset used by memory operations, the 32-bit | |
5844 | range is shifted down by 32768 here. This code should | |
6373ee54 CD |
5845 | probably attempt to generate 64-bit constants more |
5846 | efficiently in general. | |
d6bc6245 | 5847 | */ |
6373ee54 CD |
5848 | if (HAVE_64BIT_ADDRESSES |
5849 | && !(offset_expr.X_op == O_constant | |
78d32a17 | 5850 | && IS_SEXT_32BIT_NUM (offset_expr.X_add_number + 0x8000))) |
d6bc6245 TS |
5851 | { |
5852 | p = NULL; | |
5853 | ||
5854 | /* We don't do GP optimization for now because RELAX_ENCODE can't | |
5855 | hold the data for such large chunks. */ | |
5856 | ||
460597ba | 5857 | if (used_at == 0 && ! mips_opts.noat) |
d6bc6245 TS |
5858 | { |
5859 | macro_build (p, &icnt, &offset_expr, "lui", "t,u", | |
5860 | tempreg, (int) BFD_RELOC_MIPS_HIGHEST); | |
5861 | macro_build (p, &icnt, &offset_expr, "lui", "t,u", | |
5862 | AT, (int) BFD_RELOC_HI16_S); | |
5863 | macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j", | |
5864 | tempreg, tempreg, (int) BFD_RELOC_MIPS_HIGHER); | |
5865 | if (breg != 0) | |
2396cfb9 TS |
5866 | macro_build (p, &icnt, (expressionS *) NULL, "daddu", |
5867 | "d,v,t", AT, AT, breg); | |
5868 | macro_build (p, &icnt, (expressionS *) NULL, "dsll32", | |
5869 | "d,w,<", tempreg, tempreg, 0); | |
5870 | macro_build (p, &icnt, (expressionS *) NULL, "daddu", | |
5871 | "d,v,t", tempreg, tempreg, AT); | |
d6bc6245 TS |
5872 | macro_build (p, &icnt, &offset_expr, s, |
5873 | fmt, treg, (int) BFD_RELOC_LO16, tempreg); | |
5874 | used_at = 1; | |
5875 | } | |
5876 | else | |
5877 | { | |
5878 | macro_build (p, &icnt, &offset_expr, "lui", "t,u", | |
5879 | tempreg, (int) BFD_RELOC_MIPS_HIGHEST); | |
5880 | macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j", | |
5881 | tempreg, tempreg, (int) BFD_RELOC_MIPS_HIGHER); | |
2396cfb9 TS |
5882 | macro_build (p, &icnt, (expressionS *) NULL, "dsll", |
5883 | "d,w,<", tempreg, tempreg, 16); | |
d6bc6245 TS |
5884 | macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j", |
5885 | tempreg, tempreg, (int) BFD_RELOC_HI16_S); | |
2396cfb9 TS |
5886 | macro_build (p, &icnt, (expressionS *) NULL, "dsll", |
5887 | "d,w,<", tempreg, tempreg, 16); | |
d6bc6245 | 5888 | if (breg != 0) |
2396cfb9 TS |
5889 | macro_build (p, &icnt, (expressionS *) NULL, "daddu", |
5890 | "d,v,t", tempreg, tempreg, breg); | |
d6bc6245 TS |
5891 | macro_build (p, &icnt, &offset_expr, s, |
5892 | fmt, treg, (int) BFD_RELOC_LO16, tempreg); | |
5893 | } | |
5894 | ||
5895 | return; | |
5896 | } | |
76b3015f | 5897 | |
252b5132 RH |
5898 | if (breg == 0) |
5899 | { | |
e7d556df | 5900 | if ((valueT) offset_expr.X_add_number > MAX_GPREL_OFFSET |
252b5132 RH |
5901 | || nopic_need_relax (offset_expr.X_add_symbol, 1)) |
5902 | p = NULL; | |
5903 | else | |
5904 | { | |
5905 | frag_grow (20); | |
5906 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
c9914766 TS |
5907 | treg, (int) BFD_RELOC_GPREL16, |
5908 | mips_gp_register); | |
252b5132 RH |
5909 | p = frag_var (rs_machine_dependent, 8, 0, |
5910 | RELAX_ENCODE (4, 8, 0, 4, 0, | |
5911 | (mips_opts.warn_about_macros | |
5912 | || (used_at | |
5913 | && mips_opts.noat))), | |
956cd1d6 | 5914 | offset_expr.X_add_symbol, 0, NULL); |
252b5132 RH |
5915 | used_at = 0; |
5916 | } | |
5917 | macro_build_lui (p, &icnt, &offset_expr, tempreg); | |
5918 | if (p != NULL) | |
5919 | p += 4; | |
5920 | macro_build (p, &icnt, &offset_expr, s, fmt, treg, | |
5921 | (int) BFD_RELOC_LO16, tempreg); | |
5922 | } | |
5923 | else | |
5924 | { | |
e7d556df | 5925 | if ((valueT) offset_expr.X_add_number > MAX_GPREL_OFFSET |
252b5132 RH |
5926 | || nopic_need_relax (offset_expr.X_add_symbol, 1)) |
5927 | p = NULL; | |
5928 | else | |
5929 | { | |
5930 | frag_grow (28); | |
5931 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 5932 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
c9914766 | 5933 | "d,v,t", tempreg, breg, mips_gp_register); |
252b5132 | 5934 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
cdf6fd85 | 5935 | treg, (int) BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
5936 | p = frag_var (rs_machine_dependent, 12, 0, |
5937 | RELAX_ENCODE (8, 12, 0, 8, 0, 0), | |
956cd1d6 | 5938 | offset_expr.X_add_symbol, 0, NULL); |
252b5132 RH |
5939 | } |
5940 | macro_build_lui (p, &icnt, &offset_expr, tempreg); | |
5941 | if (p != NULL) | |
5942 | p += 4; | |
5943 | macro_build (p, &icnt, (expressionS *) NULL, | |
ca4e0257 | 5944 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
5945 | "d,v,t", tempreg, tempreg, breg); |
5946 | if (p != NULL) | |
5947 | p += 4; | |
5948 | macro_build (p, &icnt, &offset_expr, s, fmt, treg, | |
5949 | (int) BFD_RELOC_LO16, tempreg); | |
5950 | } | |
5951 | } | |
5952 | else if (mips_pic == SVR4_PIC && ! mips_big_got) | |
5953 | { | |
f9419b05 | 5954 | char *p; |
ed6fb7bd | 5955 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
f9419b05 | 5956 | |
252b5132 RH |
5957 | /* If this is a reference to an external symbol, we want |
5958 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5959 | nop | |
5960 | <op> $treg,0($tempreg) | |
5961 | Otherwise we want | |
5962 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5963 | nop | |
5964 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
5965 | <op> $treg,0($tempreg) | |
ed6fb7bd SC |
5966 | If we have NewABI, we want |
5967 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
252b5132 RH |
5968 | If there is a base register, we add it to $tempreg before |
5969 | the <op>. If there is a constant, we stick it in the | |
5970 | <op> instruction. We don't handle constants larger than | |
5971 | 16 bits, because we have no way to load the upper 16 bits | |
5972 | (actually, we could handle them for the subset of cases | |
5973 | in which we are not using $at). */ | |
5974 | assert (offset_expr.X_op == O_symbol); | |
5975 | expr1.X_add_number = offset_expr.X_add_number; | |
5976 | offset_expr.X_add_number = 0; | |
ed6fb7bd SC |
5977 | if (HAVE_NEWABI) |
5978 | lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_DISP; | |
252b5132 RH |
5979 | if (expr1.X_add_number < -0x8000 |
5980 | || expr1.X_add_number >= 0x8000) | |
5981 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
5982 | frag_grow (20); | |
5983 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
c9914766 | 5984 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", "t,o(b)", tempreg, |
ed6fb7bd | 5985 | (int) lw_reloc_type, mips_gp_register); |
252b5132 | 5986 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); |
bdaaa2e1 | 5987 | p = frag_var (rs_machine_dependent, 4, 0, |
252b5132 | 5988 | RELAX_ENCODE (0, 4, -8, 0, 0, 0), |
c4e7957c | 5989 | offset_expr.X_add_symbol, 0, NULL); |
252b5132 | 5990 | macro_build (p, &icnt, &offset_expr, |
ca4e0257 | 5991 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
252b5132 RH |
5992 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
5993 | if (breg != 0) | |
5994 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 5995 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
5996 | "d,v,t", tempreg, tempreg, breg); |
5997 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, treg, | |
5998 | (int) BFD_RELOC_LO16, tempreg); | |
5999 | } | |
6000 | else if (mips_pic == SVR4_PIC) | |
6001 | { | |
6002 | int gpdel; | |
f9419b05 | 6003 | char *p; |
252b5132 RH |
6004 | |
6005 | /* If this is a reference to an external symbol, we want | |
6006 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
6007 | addu $tempreg,$tempreg,$gp | |
6008 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
6009 | <op> $treg,0($tempreg) | |
6010 | Otherwise we want | |
6011 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6012 | nop | |
6013 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
6014 | <op> $treg,0($tempreg) | |
6015 | If there is a base register, we add it to $tempreg before | |
6016 | the <op>. If there is a constant, we stick it in the | |
6017 | <op> instruction. We don't handle constants larger than | |
6018 | 16 bits, because we have no way to load the upper 16 bits | |
6019 | (actually, we could handle them for the subset of cases | |
438c16b8 TS |
6020 | in which we are not using $at). |
6021 | ||
6022 | For NewABI, we want | |
6023 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
6024 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_MIPS_GOT_OFST) | |
6025 | <op> $treg,0($tempreg) | |
6026 | */ | |
252b5132 RH |
6027 | assert (offset_expr.X_op == O_symbol); |
6028 | expr1.X_add_number = offset_expr.X_add_number; | |
6029 | offset_expr.X_add_number = 0; | |
6030 | if (expr1.X_add_number < -0x8000 | |
6031 | || expr1.X_add_number >= 0x8000) | |
6032 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
438c16b8 TS |
6033 | if (HAVE_NEWABI) |
6034 | { | |
6035 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
6036 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", | |
6037 | "t,o(b)", tempreg, BFD_RELOC_MIPS_GOT_PAGE, | |
6038 | mips_gp_register); | |
6039 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
6040 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", | |
6041 | "t,r,j", tempreg, tempreg, | |
6042 | BFD_RELOC_MIPS_GOT_OFST); | |
6043 | if (breg != 0) | |
6044 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
6045 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", | |
6046 | "d,v,t", tempreg, tempreg, breg); | |
6047 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, treg, | |
6048 | (int) BFD_RELOC_LO16, tempreg); | |
6049 | ||
6050 | if (! used_at) | |
6051 | return; | |
6052 | ||
6053 | break; | |
6054 | } | |
f7ea7ef2 | 6055 | if (reg_needs_delay (mips_gp_register)) |
252b5132 RH |
6056 | gpdel = 4; |
6057 | else | |
6058 | gpdel = 0; | |
6059 | frag_grow (36); | |
6060 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
6061 | tempreg, (int) BFD_RELOC_MIPS_GOT_HI16); | |
6062 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 6063 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
c9914766 | 6064 | "d,v,t", tempreg, tempreg, mips_gp_register); |
252b5132 | 6065 | macro_build ((char *) NULL, &icnt, &offset_expr, |
ca4e0257 | 6066 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", |
252b5132 RH |
6067 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT_LO16, |
6068 | tempreg); | |
6069 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, | |
6070 | RELAX_ENCODE (12, 12 + gpdel, gpdel, 8 + gpdel, 0, 0), | |
c4e7957c | 6071 | offset_expr.X_add_symbol, 0, NULL); |
252b5132 RH |
6072 | if (gpdel > 0) |
6073 | { | |
6074 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
6075 | p += 4; | |
6076 | } | |
6077 | macro_build (p, &icnt, &offset_expr, | |
ca4e0257 | 6078 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", |
c9914766 TS |
6079 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, |
6080 | mips_gp_register); | |
252b5132 RH |
6081 | p += 4; |
6082 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
6083 | p += 4; | |
6084 | macro_build (p, &icnt, &offset_expr, | |
ca4e0257 | 6085 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
252b5132 RH |
6086 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
6087 | if (breg != 0) | |
6088 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 6089 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
6090 | "d,v,t", tempreg, tempreg, breg); |
6091 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, treg, | |
6092 | (int) BFD_RELOC_LO16, tempreg); | |
6093 | } | |
6094 | else if (mips_pic == EMBEDDED_PIC) | |
6095 | { | |
6096 | /* If there is no base register, we want | |
cdf6fd85 | 6097 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
252b5132 RH |
6098 | If there is a base register, we want |
6099 | addu $tempreg,$breg,$gp | |
cdf6fd85 | 6100 | <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16) |
252b5132 RH |
6101 | */ |
6102 | assert (offset_expr.X_op == O_symbol); | |
6103 | if (breg == 0) | |
6104 | { | |
6105 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
c9914766 | 6106 | treg, (int) BFD_RELOC_GPREL16, mips_gp_register); |
252b5132 RH |
6107 | used_at = 0; |
6108 | } | |
6109 | else | |
6110 | { | |
6111 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 6112 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
c9914766 | 6113 | "d,v,t", tempreg, breg, mips_gp_register); |
252b5132 | 6114 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
cdf6fd85 | 6115 | treg, (int) BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
6116 | } |
6117 | } | |
6118 | else | |
6119 | abort (); | |
6120 | ||
6121 | if (! used_at) | |
6122 | return; | |
6123 | ||
6124 | break; | |
6125 | ||
6126 | case M_LI: | |
6127 | case M_LI_S: | |
6128 | load_register (&icnt, treg, &imm_expr, 0); | |
6129 | return; | |
6130 | ||
6131 | case M_DLI: | |
6132 | load_register (&icnt, treg, &imm_expr, 1); | |
6133 | return; | |
6134 | ||
6135 | case M_LI_SS: | |
6136 | if (imm_expr.X_op == O_constant) | |
6137 | { | |
6138 | load_register (&icnt, AT, &imm_expr, 0); | |
6139 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
6140 | "mtc1", "t,G", AT, treg); | |
6141 | break; | |
6142 | } | |
6143 | else | |
6144 | { | |
6145 | assert (offset_expr.X_op == O_symbol | |
6146 | && strcmp (segment_name (S_GET_SEGMENT | |
6147 | (offset_expr.X_add_symbol)), | |
6148 | ".lit4") == 0 | |
6149 | && offset_expr.X_add_number == 0); | |
6150 | macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)", | |
c9914766 | 6151 | treg, (int) BFD_RELOC_MIPS_LITERAL, mips_gp_register); |
252b5132 RH |
6152 | return; |
6153 | } | |
6154 | ||
6155 | case M_LI_D: | |
ca4e0257 RS |
6156 | /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits |
6157 | wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high | |
6158 | order 32 bits of the value and the low order 32 bits are either | |
6159 | zero or in OFFSET_EXPR. */ | |
252b5132 RH |
6160 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) |
6161 | { | |
ca4e0257 | 6162 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
6163 | load_register (&icnt, treg, &imm_expr, 1); |
6164 | else | |
6165 | { | |
6166 | int hreg, lreg; | |
6167 | ||
6168 | if (target_big_endian) | |
6169 | { | |
6170 | hreg = treg; | |
6171 | lreg = treg + 1; | |
6172 | } | |
6173 | else | |
6174 | { | |
6175 | hreg = treg + 1; | |
6176 | lreg = treg; | |
6177 | } | |
6178 | ||
6179 | if (hreg <= 31) | |
6180 | load_register (&icnt, hreg, &imm_expr, 0); | |
6181 | if (lreg <= 31) | |
6182 | { | |
6183 | if (offset_expr.X_op == O_absent) | |
ea1fb5dc | 6184 | move_register (&icnt, lreg, 0); |
252b5132 RH |
6185 | else |
6186 | { | |
6187 | assert (offset_expr.X_op == O_constant); | |
6188 | load_register (&icnt, lreg, &offset_expr, 0); | |
6189 | } | |
6190 | } | |
6191 | } | |
6192 | return; | |
6193 | } | |
6194 | ||
6195 | /* We know that sym is in the .rdata section. First we get the | |
6196 | upper 16 bits of the address. */ | |
6197 | if (mips_pic == NO_PIC) | |
6198 | { | |
956cd1d6 | 6199 | macro_build_lui (NULL, &icnt, &offset_expr, AT); |
252b5132 RH |
6200 | } |
6201 | else if (mips_pic == SVR4_PIC) | |
6202 | { | |
6203 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
ca4e0257 | 6204 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", |
c9914766 TS |
6205 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, |
6206 | mips_gp_register); | |
252b5132 RH |
6207 | } |
6208 | else if (mips_pic == EMBEDDED_PIC) | |
6209 | { | |
6210 | /* For embedded PIC we pick up the entire address off $gp in | |
6211 | a single instruction. */ | |
6212 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
c9914766 TS |
6213 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", "t,r,j", AT, |
6214 | mips_gp_register, (int) BFD_RELOC_GPREL16); | |
252b5132 RH |
6215 | offset_expr.X_op = O_constant; |
6216 | offset_expr.X_add_number = 0; | |
6217 | } | |
6218 | else | |
6219 | abort (); | |
bdaaa2e1 | 6220 | |
252b5132 | 6221 | /* Now we load the register(s). */ |
ca4e0257 | 6222 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
6223 | macro_build ((char *) NULL, &icnt, &offset_expr, "ld", "t,o(b)", |
6224 | treg, (int) BFD_RELOC_LO16, AT); | |
6225 | else | |
6226 | { | |
6227 | macro_build ((char *) NULL, &icnt, &offset_expr, "lw", "t,o(b)", | |
6228 | treg, (int) BFD_RELOC_LO16, AT); | |
f9419b05 | 6229 | if (treg != RA) |
252b5132 RH |
6230 | { |
6231 | /* FIXME: How in the world do we deal with the possible | |
6232 | overflow here? */ | |
6233 | offset_expr.X_add_number += 4; | |
6234 | macro_build ((char *) NULL, &icnt, &offset_expr, "lw", "t,o(b)", | |
6235 | treg + 1, (int) BFD_RELOC_LO16, AT); | |
6236 | } | |
6237 | } | |
6238 | ||
6239 | /* To avoid confusion in tc_gen_reloc, we must ensure that this | |
6240 | does not become a variant frag. */ | |
6241 | frag_wane (frag_now); | |
6242 | frag_new (0); | |
6243 | ||
6244 | break; | |
6245 | ||
6246 | case M_LI_DD: | |
ca4e0257 RS |
6247 | /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits |
6248 | wide, IMM_EXPR is the entire value and the GPRs are known to be 64 | |
6249 | bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of | |
6250 | the value and the low order 32 bits are either zero or in | |
6251 | OFFSET_EXPR. */ | |
252b5132 RH |
6252 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) |
6253 | { | |
ca4e0257 RS |
6254 | load_register (&icnt, AT, &imm_expr, HAVE_64BIT_FPRS); |
6255 | if (HAVE_64BIT_FPRS) | |
6256 | { | |
6257 | assert (HAVE_64BIT_GPRS); | |
6258 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
6259 | "dmtc1", "t,S", AT, treg); | |
6260 | } | |
252b5132 RH |
6261 | else |
6262 | { | |
6263 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
6264 | "mtc1", "t,G", AT, treg + 1); | |
6265 | if (offset_expr.X_op == O_absent) | |
6266 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
6267 | "mtc1", "t,G", 0, treg); | |
6268 | else | |
6269 | { | |
6270 | assert (offset_expr.X_op == O_constant); | |
6271 | load_register (&icnt, AT, &offset_expr, 0); | |
6272 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
6273 | "mtc1", "t,G", AT, treg); | |
6274 | } | |
6275 | } | |
6276 | break; | |
6277 | } | |
6278 | ||
6279 | assert (offset_expr.X_op == O_symbol | |
6280 | && offset_expr.X_add_number == 0); | |
6281 | s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol)); | |
6282 | if (strcmp (s, ".lit8") == 0) | |
6283 | { | |
e7af610e | 6284 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 RH |
6285 | { |
6286 | macro_build ((char *) NULL, &icnt, &offset_expr, "ldc1", | |
c9914766 TS |
6287 | "T,o(b)", treg, (int) BFD_RELOC_MIPS_LITERAL, |
6288 | mips_gp_register); | |
252b5132 RH |
6289 | return; |
6290 | } | |
c9914766 | 6291 | breg = mips_gp_register; |
252b5132 RH |
6292 | r = BFD_RELOC_MIPS_LITERAL; |
6293 | goto dob; | |
6294 | } | |
6295 | else | |
6296 | { | |
6297 | assert (strcmp (s, RDATA_SECTION_NAME) == 0); | |
6298 | if (mips_pic == SVR4_PIC) | |
6299 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
ca4e0257 | 6300 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", |
c9914766 TS |
6301 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, |
6302 | mips_gp_register); | |
252b5132 RH |
6303 | else |
6304 | { | |
6305 | /* FIXME: This won't work for a 64 bit address. */ | |
956cd1d6 | 6306 | macro_build_lui (NULL, &icnt, &offset_expr, AT); |
252b5132 | 6307 | } |
bdaaa2e1 | 6308 | |
e7af610e | 6309 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 RH |
6310 | { |
6311 | macro_build ((char *) NULL, &icnt, &offset_expr, "ldc1", | |
6312 | "T,o(b)", treg, (int) BFD_RELOC_LO16, AT); | |
6313 | ||
6314 | /* To avoid confusion in tc_gen_reloc, we must ensure | |
6315 | that this does not become a variant frag. */ | |
6316 | frag_wane (frag_now); | |
6317 | frag_new (0); | |
6318 | ||
6319 | break; | |
6320 | } | |
6321 | breg = AT; | |
6322 | r = BFD_RELOC_LO16; | |
6323 | goto dob; | |
6324 | } | |
6325 | ||
6326 | case M_L_DOB: | |
ec68c924 | 6327 | if (mips_arch == CPU_R4650) |
252b5132 RH |
6328 | { |
6329 | as_bad (_("opcode not supported on this processor")); | |
6330 | return; | |
6331 | } | |
6332 | /* Even on a big endian machine $fn comes before $fn+1. We have | |
6333 | to adjust when loading from memory. */ | |
6334 | r = BFD_RELOC_LO16; | |
6335 | dob: | |
e7af610e | 6336 | assert (mips_opts.isa == ISA_MIPS1); |
252b5132 RH |
6337 | macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)", |
6338 | target_big_endian ? treg + 1 : treg, | |
6339 | (int) r, breg); | |
6340 | /* FIXME: A possible overflow which I don't know how to deal | |
6341 | with. */ | |
6342 | offset_expr.X_add_number += 4; | |
6343 | macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)", | |
6344 | target_big_endian ? treg : treg + 1, | |
6345 | (int) r, breg); | |
6346 | ||
6347 | /* To avoid confusion in tc_gen_reloc, we must ensure that this | |
6348 | does not become a variant frag. */ | |
6349 | frag_wane (frag_now); | |
6350 | frag_new (0); | |
6351 | ||
6352 | if (breg != AT) | |
6353 | return; | |
6354 | break; | |
6355 | ||
6356 | case M_L_DAB: | |
6357 | /* | |
6358 | * The MIPS assembler seems to check for X_add_number not | |
6359 | * being double aligned and generating: | |
6360 | * lui at,%hi(foo+1) | |
6361 | * addu at,at,v1 | |
6362 | * addiu at,at,%lo(foo+1) | |
6363 | * lwc1 f2,0(at) | |
6364 | * lwc1 f3,4(at) | |
6365 | * But, the resulting address is the same after relocation so why | |
6366 | * generate the extra instruction? | |
6367 | */ | |
ec68c924 | 6368 | if (mips_arch == CPU_R4650) |
252b5132 RH |
6369 | { |
6370 | as_bad (_("opcode not supported on this processor")); | |
6371 | return; | |
6372 | } | |
bdaaa2e1 | 6373 | /* Itbl support may require additional care here. */ |
252b5132 | 6374 | coproc = 1; |
e7af610e | 6375 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 RH |
6376 | { |
6377 | s = "ldc1"; | |
6378 | goto ld; | |
6379 | } | |
6380 | ||
6381 | s = "lwc1"; | |
6382 | fmt = "T,o(b)"; | |
6383 | goto ldd_std; | |
6384 | ||
6385 | case M_S_DAB: | |
ec68c924 | 6386 | if (mips_arch == CPU_R4650) |
252b5132 RH |
6387 | { |
6388 | as_bad (_("opcode not supported on this processor")); | |
6389 | return; | |
6390 | } | |
6391 | ||
e7af610e | 6392 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 RH |
6393 | { |
6394 | s = "sdc1"; | |
6395 | goto st; | |
6396 | } | |
6397 | ||
6398 | s = "swc1"; | |
6399 | fmt = "T,o(b)"; | |
bdaaa2e1 | 6400 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6401 | coproc = 1; |
6402 | goto ldd_std; | |
6403 | ||
6404 | case M_LD_AB: | |
ca4e0257 | 6405 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
6406 | { |
6407 | s = "ld"; | |
6408 | goto ld; | |
6409 | } | |
6410 | ||
6411 | s = "lw"; | |
6412 | fmt = "t,o(b)"; | |
6413 | goto ldd_std; | |
6414 | ||
6415 | case M_SD_AB: | |
ca4e0257 | 6416 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
6417 | { |
6418 | s = "sd"; | |
6419 | goto st; | |
6420 | } | |
6421 | ||
6422 | s = "sw"; | |
6423 | fmt = "t,o(b)"; | |
6424 | ||
6425 | ldd_std: | |
afdbd6d0 CD |
6426 | /* We do _not_ bother to allow embedded PIC (symbol-local_symbol) |
6427 | loads for the case of doing a pair of loads to simulate an 'ld'. | |
6428 | This is not currently done by the compiler, and assembly coders | |
6429 | writing embedded-pic code can cope. */ | |
6430 | ||
252b5132 RH |
6431 | if (offset_expr.X_op != O_symbol |
6432 | && offset_expr.X_op != O_constant) | |
6433 | { | |
6434 | as_bad (_("expression too complex")); | |
6435 | offset_expr.X_op = O_constant; | |
6436 | } | |
6437 | ||
6438 | /* Even on a big endian machine $fn comes before $fn+1. We have | |
6439 | to adjust when loading from memory. We set coproc if we must | |
6440 | load $fn+1 first. */ | |
bdaaa2e1 | 6441 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6442 | if (! target_big_endian) |
6443 | coproc = 0; | |
6444 | ||
6445 | if (mips_pic == NO_PIC | |
6446 | || offset_expr.X_op == O_constant) | |
6447 | { | |
f9419b05 TS |
6448 | char *p; |
6449 | ||
252b5132 | 6450 | /* If this is a reference to a GP relative symbol, we want |
cdf6fd85 TS |
6451 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
6452 | <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16) | |
252b5132 RH |
6453 | If we have a base register, we use this |
6454 | addu $at,$breg,$gp | |
cdf6fd85 TS |
6455 | <op> $treg,<sym>($at) (BFD_RELOC_GPREL16) |
6456 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16) | |
252b5132 RH |
6457 | If this is not a GP relative symbol, we want |
6458 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
6459 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
6460 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
6461 | If there is a base register, we add it to $at after the | |
6462 | lui instruction. If there is a constant, we always use | |
6463 | the last case. */ | |
e7d556df | 6464 | if ((valueT) offset_expr.X_add_number > MAX_GPREL_OFFSET |
252b5132 RH |
6465 | || nopic_need_relax (offset_expr.X_add_symbol, 1)) |
6466 | { | |
6467 | p = NULL; | |
6468 | used_at = 1; | |
6469 | } | |
6470 | else | |
6471 | { | |
6472 | int off; | |
6473 | ||
6474 | if (breg == 0) | |
6475 | { | |
6476 | frag_grow (28); | |
c9914766 | 6477 | tempreg = mips_gp_register; |
252b5132 RH |
6478 | off = 0; |
6479 | used_at = 0; | |
6480 | } | |
6481 | else | |
6482 | { | |
6483 | frag_grow (36); | |
6484 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 6485 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
c9914766 | 6486 | "d,v,t", AT, breg, mips_gp_register); |
252b5132 RH |
6487 | tempreg = AT; |
6488 | off = 4; | |
6489 | used_at = 1; | |
6490 | } | |
6491 | ||
beae10d5 | 6492 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6493 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
6494 | coproc ? treg + 1 : treg, | |
cdf6fd85 | 6495 | (int) BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
6496 | offset_expr.X_add_number += 4; |
6497 | ||
6498 | /* Set mips_optimize to 2 to avoid inserting an | |
6499 | undesired nop. */ | |
6500 | hold_mips_optimize = mips_optimize; | |
6501 | mips_optimize = 2; | |
beae10d5 | 6502 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6503 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
6504 | coproc ? treg : treg + 1, | |
cdf6fd85 | 6505 | (int) BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
6506 | mips_optimize = hold_mips_optimize; |
6507 | ||
6508 | p = frag_var (rs_machine_dependent, 12 + off, 0, | |
6509 | RELAX_ENCODE (8 + off, 12 + off, 0, 4 + off, 1, | |
6510 | used_at && mips_opts.noat), | |
956cd1d6 | 6511 | offset_expr.X_add_symbol, 0, NULL); |
252b5132 RH |
6512 | |
6513 | /* We just generated two relocs. When tc_gen_reloc | |
6514 | handles this case, it will skip the first reloc and | |
6515 | handle the second. The second reloc already has an | |
6516 | extra addend of 4, which we added above. We must | |
6517 | subtract it out, and then subtract another 4 to make | |
6518 | the first reloc come out right. The second reloc | |
6519 | will come out right because we are going to add 4 to | |
6520 | offset_expr when we build its instruction below. | |
6521 | ||
6522 | If we have a symbol, then we don't want to include | |
6523 | the offset, because it will wind up being included | |
6524 | when we generate the reloc. */ | |
6525 | ||
6526 | if (offset_expr.X_op == O_constant) | |
6527 | offset_expr.X_add_number -= 8; | |
6528 | else | |
6529 | { | |
6530 | offset_expr.X_add_number = -4; | |
6531 | offset_expr.X_op = O_constant; | |
6532 | } | |
6533 | } | |
6534 | macro_build_lui (p, &icnt, &offset_expr, AT); | |
6535 | if (p != NULL) | |
6536 | p += 4; | |
6537 | if (breg != 0) | |
6538 | { | |
6539 | macro_build (p, &icnt, (expressionS *) NULL, | |
ca4e0257 | 6540 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
6541 | "d,v,t", AT, breg, AT); |
6542 | if (p != NULL) | |
6543 | p += 4; | |
6544 | } | |
beae10d5 | 6545 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6546 | macro_build (p, &icnt, &offset_expr, s, fmt, |
6547 | coproc ? treg + 1 : treg, | |
6548 | (int) BFD_RELOC_LO16, AT); | |
6549 | if (p != NULL) | |
6550 | p += 4; | |
6551 | /* FIXME: How do we handle overflow here? */ | |
6552 | offset_expr.X_add_number += 4; | |
beae10d5 | 6553 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6554 | macro_build (p, &icnt, &offset_expr, s, fmt, |
6555 | coproc ? treg : treg + 1, | |
6556 | (int) BFD_RELOC_LO16, AT); | |
bdaaa2e1 | 6557 | } |
252b5132 RH |
6558 | else if (mips_pic == SVR4_PIC && ! mips_big_got) |
6559 | { | |
6560 | int off; | |
6561 | ||
6562 | /* If this is a reference to an external symbol, we want | |
6563 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6564 | nop | |
6565 | <op> $treg,0($at) | |
6566 | <op> $treg+1,4($at) | |
6567 | Otherwise we want | |
6568 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6569 | nop | |
6570 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
6571 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
6572 | If there is a base register we add it to $at before the | |
6573 | lwc1 instructions. If there is a constant we include it | |
6574 | in the lwc1 instructions. */ | |
6575 | used_at = 1; | |
6576 | expr1.X_add_number = offset_expr.X_add_number; | |
6577 | offset_expr.X_add_number = 0; | |
6578 | if (expr1.X_add_number < -0x8000 | |
6579 | || expr1.X_add_number >= 0x8000 - 4) | |
6580 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
6581 | if (breg == 0) | |
6582 | off = 0; | |
6583 | else | |
6584 | off = 4; | |
6585 | frag_grow (24 + off); | |
6586 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
c9914766 TS |
6587 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", "t,o(b)", AT, |
6588 | (int) BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
252b5132 RH |
6589 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); |
6590 | if (breg != 0) | |
6591 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 6592 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 | 6593 | "d,v,t", AT, breg, AT); |
beae10d5 | 6594 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6595 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, |
6596 | coproc ? treg + 1 : treg, | |
6597 | (int) BFD_RELOC_LO16, AT); | |
6598 | expr1.X_add_number += 4; | |
6599 | ||
6600 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
6601 | nop. */ | |
6602 | hold_mips_optimize = mips_optimize; | |
6603 | mips_optimize = 2; | |
beae10d5 | 6604 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6605 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, |
6606 | coproc ? treg : treg + 1, | |
6607 | (int) BFD_RELOC_LO16, AT); | |
6608 | mips_optimize = hold_mips_optimize; | |
6609 | ||
6610 | (void) frag_var (rs_machine_dependent, 0, 0, | |
6611 | RELAX_ENCODE (0, 0, -16 - off, -8, 1, 0), | |
c4e7957c | 6612 | offset_expr.X_add_symbol, 0, NULL); |
252b5132 RH |
6613 | } |
6614 | else if (mips_pic == SVR4_PIC) | |
6615 | { | |
6616 | int gpdel, off; | |
f9419b05 | 6617 | char *p; |
252b5132 RH |
6618 | |
6619 | /* If this is a reference to an external symbol, we want | |
6620 | lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
6621 | addu $at,$at,$gp | |
6622 | lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16) | |
6623 | nop | |
6624 | <op> $treg,0($at) | |
6625 | <op> $treg+1,4($at) | |
6626 | Otherwise we want | |
6627 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6628 | nop | |
6629 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
6630 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
6631 | If there is a base register we add it to $at before the | |
6632 | lwc1 instructions. If there is a constant we include it | |
6633 | in the lwc1 instructions. */ | |
6634 | used_at = 1; | |
6635 | expr1.X_add_number = offset_expr.X_add_number; | |
6636 | offset_expr.X_add_number = 0; | |
6637 | if (expr1.X_add_number < -0x8000 | |
6638 | || expr1.X_add_number >= 0x8000 - 4) | |
6639 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
c9914766 | 6640 | if (reg_needs_delay (mips_gp_register)) |
252b5132 RH |
6641 | gpdel = 4; |
6642 | else | |
6643 | gpdel = 0; | |
6644 | if (breg == 0) | |
6645 | off = 0; | |
6646 | else | |
6647 | off = 4; | |
6648 | frag_grow (56); | |
6649 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
6650 | AT, (int) BFD_RELOC_MIPS_GOT_HI16); | |
6651 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 6652 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
c9914766 | 6653 | "d,v,t", AT, AT, mips_gp_register); |
252b5132 | 6654 | macro_build ((char *) NULL, &icnt, &offset_expr, |
ca4e0257 | 6655 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", |
252b5132 RH |
6656 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT_LO16, AT); |
6657 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); | |
6658 | if (breg != 0) | |
6659 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 6660 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 | 6661 | "d,v,t", AT, breg, AT); |
beae10d5 | 6662 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6663 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, |
6664 | coproc ? treg + 1 : treg, | |
6665 | (int) BFD_RELOC_LO16, AT); | |
6666 | expr1.X_add_number += 4; | |
6667 | ||
6668 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
6669 | nop. */ | |
6670 | hold_mips_optimize = mips_optimize; | |
6671 | mips_optimize = 2; | |
beae10d5 | 6672 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6673 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, |
6674 | coproc ? treg : treg + 1, | |
6675 | (int) BFD_RELOC_LO16, AT); | |
6676 | mips_optimize = hold_mips_optimize; | |
6677 | expr1.X_add_number -= 4; | |
6678 | ||
6679 | p = frag_var (rs_machine_dependent, 16 + gpdel + off, 0, | |
6680 | RELAX_ENCODE (24 + off, 16 + gpdel + off, gpdel, | |
6681 | 8 + gpdel + off, 1, 0), | |
c4e7957c | 6682 | offset_expr.X_add_symbol, 0, NULL); |
252b5132 RH |
6683 | if (gpdel > 0) |
6684 | { | |
6685 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
6686 | p += 4; | |
6687 | } | |
6688 | macro_build (p, &icnt, &offset_expr, | |
ca4e0257 | 6689 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", |
c9914766 TS |
6690 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, |
6691 | mips_gp_register); | |
252b5132 RH |
6692 | p += 4; |
6693 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
6694 | p += 4; | |
6695 | if (breg != 0) | |
6696 | { | |
6697 | macro_build (p, &icnt, (expressionS *) NULL, | |
ca4e0257 | 6698 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
6699 | "d,v,t", AT, breg, AT); |
6700 | p += 4; | |
6701 | } | |
beae10d5 | 6702 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6703 | macro_build (p, &icnt, &expr1, s, fmt, |
6704 | coproc ? treg + 1 : treg, | |
6705 | (int) BFD_RELOC_LO16, AT); | |
6706 | p += 4; | |
6707 | expr1.X_add_number += 4; | |
6708 | ||
6709 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
6710 | nop. */ | |
6711 | hold_mips_optimize = mips_optimize; | |
6712 | mips_optimize = 2; | |
beae10d5 | 6713 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6714 | macro_build (p, &icnt, &expr1, s, fmt, |
6715 | coproc ? treg : treg + 1, | |
6716 | (int) BFD_RELOC_LO16, AT); | |
6717 | mips_optimize = hold_mips_optimize; | |
6718 | } | |
6719 | else if (mips_pic == EMBEDDED_PIC) | |
6720 | { | |
6721 | /* If there is no base register, we use | |
cdf6fd85 TS |
6722 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
6723 | <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16) | |
252b5132 RH |
6724 | If we have a base register, we use |
6725 | addu $at,$breg,$gp | |
cdf6fd85 TS |
6726 | <op> $treg,<sym>($at) (BFD_RELOC_GPREL16) |
6727 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16) | |
252b5132 RH |
6728 | */ |
6729 | if (breg == 0) | |
6730 | { | |
c9914766 | 6731 | tempreg = mips_gp_register; |
252b5132 RH |
6732 | used_at = 0; |
6733 | } | |
6734 | else | |
6735 | { | |
6736 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 6737 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
c9914766 | 6738 | "d,v,t", AT, breg, mips_gp_register); |
252b5132 RH |
6739 | tempreg = AT; |
6740 | used_at = 1; | |
6741 | } | |
6742 | ||
beae10d5 | 6743 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6744 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
6745 | coproc ? treg + 1 : treg, | |
cdf6fd85 | 6746 | (int) BFD_RELOC_GPREL16, tempreg); |
252b5132 | 6747 | offset_expr.X_add_number += 4; |
beae10d5 | 6748 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6749 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
6750 | coproc ? treg : treg + 1, | |
cdf6fd85 | 6751 | (int) BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
6752 | } |
6753 | else | |
6754 | abort (); | |
6755 | ||
6756 | if (! used_at) | |
6757 | return; | |
6758 | ||
6759 | break; | |
6760 | ||
6761 | case M_LD_OB: | |
6762 | s = "lw"; | |
6763 | goto sd_ob; | |
6764 | case M_SD_OB: | |
6765 | s = "sw"; | |
6766 | sd_ob: | |
ca4e0257 | 6767 | assert (HAVE_32BIT_ADDRESSES); |
252b5132 RH |
6768 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, |
6769 | (int) BFD_RELOC_LO16, breg); | |
6770 | offset_expr.X_add_number += 4; | |
6771 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg + 1, | |
6772 | (int) BFD_RELOC_LO16, breg); | |
6773 | return; | |
6774 | ||
6775 | /* New code added to support COPZ instructions. | |
6776 | This code builds table entries out of the macros in mip_opcodes. | |
6777 | R4000 uses interlocks to handle coproc delays. | |
6778 | Other chips (like the R3000) require nops to be inserted for delays. | |
6779 | ||
f72c8c98 | 6780 | FIXME: Currently, we require that the user handle delays. |
252b5132 RH |
6781 | In order to fill delay slots for non-interlocked chips, |
6782 | we must have a way to specify delays based on the coprocessor. | |
6783 | Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc. | |
6784 | What are the side-effects of the cop instruction? | |
6785 | What cache support might we have and what are its effects? | |
6786 | Both coprocessor & memory require delays. how long??? | |
bdaaa2e1 | 6787 | What registers are read/set/modified? |
252b5132 RH |
6788 | |
6789 | If an itbl is provided to interpret cop instructions, | |
bdaaa2e1 | 6790 | this knowledge can be encoded in the itbl spec. */ |
252b5132 RH |
6791 | |
6792 | case M_COP0: | |
6793 | s = "c0"; | |
6794 | goto copz; | |
6795 | case M_COP1: | |
6796 | s = "c1"; | |
6797 | goto copz; | |
6798 | case M_COP2: | |
6799 | s = "c2"; | |
6800 | goto copz; | |
6801 | case M_COP3: | |
6802 | s = "c3"; | |
6803 | copz: | |
6804 | /* For now we just do C (same as Cz). The parameter will be | |
6805 | stored in insn_opcode by mips_ip. */ | |
6806 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "C", | |
6807 | ip->insn_opcode); | |
6808 | return; | |
6809 | ||
ea1fb5dc RS |
6810 | case M_MOVE: |
6811 | move_register (&icnt, dreg, sreg); | |
6812 | return; | |
6813 | ||
252b5132 RH |
6814 | #ifdef LOSING_COMPILER |
6815 | default: | |
6816 | /* Try and see if this is a new itbl instruction. | |
6817 | This code builds table entries out of the macros in mip_opcodes. | |
6818 | FIXME: For now we just assemble the expression and pass it's | |
6819 | value along as a 32-bit immediate. | |
bdaaa2e1 | 6820 | We may want to have the assembler assemble this value, |
252b5132 RH |
6821 | so that we gain the assembler's knowledge of delay slots, |
6822 | symbols, etc. | |
6823 | Would it be more efficient to use mask (id) here? */ | |
bdaaa2e1 | 6824 | if (itbl_have_entries |
252b5132 | 6825 | && (immed_expr = itbl_assemble (ip->insn_mo->name, ""))) |
beae10d5 | 6826 | { |
252b5132 RH |
6827 | s = ip->insn_mo->name; |
6828 | s2 = "cop3"; | |
6829 | coproc = ITBL_DECODE_PNUM (immed_expr);; | |
6830 | macro_build ((char *) NULL, &icnt, &immed_expr, s, "C"); | |
6831 | return; | |
beae10d5 | 6832 | } |
252b5132 RH |
6833 | macro2 (ip); |
6834 | return; | |
6835 | } | |
6836 | if (mips_opts.noat) | |
6837 | as_warn (_("Macro used $at after \".set noat\"")); | |
6838 | } | |
bdaaa2e1 | 6839 | |
252b5132 RH |
6840 | static void |
6841 | macro2 (ip) | |
6842 | struct mips_cl_insn *ip; | |
6843 | { | |
6844 | register int treg, sreg, dreg, breg; | |
6845 | int tempreg; | |
6846 | int mask; | |
6847 | int icnt = 0; | |
6848 | int used_at; | |
6849 | expressionS expr1; | |
6850 | const char *s; | |
6851 | const char *s2; | |
6852 | const char *fmt; | |
6853 | int likely = 0; | |
6854 | int dbl = 0; | |
6855 | int coproc = 0; | |
6856 | int lr = 0; | |
6857 | int imm = 0; | |
6858 | int off; | |
6859 | offsetT maxnum; | |
6860 | bfd_reloc_code_real_type r; | |
6861 | char *p; | |
bdaaa2e1 | 6862 | |
252b5132 RH |
6863 | treg = (ip->insn_opcode >> 16) & 0x1f; |
6864 | dreg = (ip->insn_opcode >> 11) & 0x1f; | |
6865 | sreg = breg = (ip->insn_opcode >> 21) & 0x1f; | |
6866 | mask = ip->insn_mo->mask; | |
bdaaa2e1 | 6867 | |
252b5132 RH |
6868 | expr1.X_op = O_constant; |
6869 | expr1.X_op_symbol = NULL; | |
6870 | expr1.X_add_symbol = NULL; | |
6871 | expr1.X_add_number = 1; | |
bdaaa2e1 | 6872 | |
252b5132 RH |
6873 | switch (mask) |
6874 | { | |
6875 | #endif /* LOSING_COMPILER */ | |
6876 | ||
6877 | case M_DMUL: | |
6878 | dbl = 1; | |
6879 | case M_MUL: | |
2396cfb9 TS |
6880 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
6881 | dbl ? "dmultu" : "multu", "s,t", sreg, treg); | |
6882 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mflo", "d", | |
6883 | dreg); | |
252b5132 RH |
6884 | return; |
6885 | ||
6886 | case M_DMUL_I: | |
6887 | dbl = 1; | |
6888 | case M_MUL_I: | |
6889 | /* The MIPS assembler some times generates shifts and adds. I'm | |
6890 | not trying to be that fancy. GCC should do this for us | |
6891 | anyway. */ | |
6892 | load_register (&icnt, AT, &imm_expr, dbl); | |
2396cfb9 | 6893 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
9a41af64 | 6894 | dbl ? "dmult" : "mult", "s,t", sreg, AT); |
2396cfb9 TS |
6895 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mflo", "d", |
6896 | dreg); | |
252b5132 RH |
6897 | break; |
6898 | ||
6899 | case M_DMULO_I: | |
6900 | dbl = 1; | |
6901 | case M_MULO_I: | |
6902 | imm = 1; | |
6903 | goto do_mulo; | |
6904 | ||
6905 | case M_DMULO: | |
6906 | dbl = 1; | |
6907 | case M_MULO: | |
6908 | do_mulo: | |
b34976b6 | 6909 | mips_emit_delays (TRUE); |
252b5132 RH |
6910 | ++mips_opts.noreorder; |
6911 | mips_any_noreorder = 1; | |
6912 | if (imm) | |
6913 | load_register (&icnt, AT, &imm_expr, dbl); | |
2396cfb9 | 6914 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
9a41af64 | 6915 | dbl ? "dmult" : "mult", "s,t", sreg, imm ? AT : treg); |
2396cfb9 TS |
6916 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mflo", "d", |
6917 | dreg); | |
6918 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
f9419b05 | 6919 | dbl ? "dsra32" : "sra", "d,w,<", dreg, dreg, RA); |
2396cfb9 TS |
6920 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mfhi", "d", |
6921 | AT); | |
252b5132 | 6922 | if (mips_trap) |
9bd7d936 MR |
6923 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "tne", |
6924 | "s,t,q", dreg, AT, 6); | |
252b5132 RH |
6925 | else |
6926 | { | |
6927 | expr1.X_add_number = 8; | |
2396cfb9 TS |
6928 | macro_build ((char *) NULL, &icnt, &expr1, "beq", "s,t,p", dreg, |
6929 | AT); | |
6930 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "", | |
6931 | 0); | |
6932 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break", | |
6933 | "c", 6); | |
252b5132 RH |
6934 | } |
6935 | --mips_opts.noreorder; | |
2396cfb9 | 6936 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mflo", "d", dreg); |
252b5132 RH |
6937 | break; |
6938 | ||
6939 | case M_DMULOU_I: | |
6940 | dbl = 1; | |
6941 | case M_MULOU_I: | |
6942 | imm = 1; | |
6943 | goto do_mulou; | |
6944 | ||
6945 | case M_DMULOU: | |
6946 | dbl = 1; | |
6947 | case M_MULOU: | |
6948 | do_mulou: | |
b34976b6 | 6949 | mips_emit_delays (TRUE); |
252b5132 RH |
6950 | ++mips_opts.noreorder; |
6951 | mips_any_noreorder = 1; | |
6952 | if (imm) | |
6953 | load_register (&icnt, AT, &imm_expr, dbl); | |
2396cfb9 | 6954 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
252b5132 RH |
6955 | dbl ? "dmultu" : "multu", |
6956 | "s,t", sreg, imm ? AT : treg); | |
2396cfb9 TS |
6957 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mfhi", "d", |
6958 | AT); | |
6959 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mflo", "d", | |
6960 | dreg); | |
252b5132 | 6961 | if (mips_trap) |
9bd7d936 MR |
6962 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "tne", |
6963 | "s,t,q", AT, 0, 6); | |
252b5132 RH |
6964 | else |
6965 | { | |
6966 | expr1.X_add_number = 8; | |
6967 | macro_build ((char *) NULL, &icnt, &expr1, "beq", "s,t,p", AT, 0); | |
2396cfb9 TS |
6968 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "", |
6969 | 0); | |
6970 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break", | |
6971 | "c", 6); | |
252b5132 RH |
6972 | } |
6973 | --mips_opts.noreorder; | |
6974 | break; | |
6975 | ||
771c7ce4 | 6976 | case M_DROL: |
af7ee8bf | 6977 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_arch)) |
82dd0097 CD |
6978 | { |
6979 | if (dreg == sreg) | |
6980 | { | |
6981 | tempreg = AT; | |
6982 | used_at = 1; | |
6983 | } | |
6984 | else | |
6985 | { | |
6986 | tempreg = dreg; | |
6987 | used_at = 0; | |
6988 | } | |
6989 | macro_build ((char *) NULL, &icnt, NULL, "dnegu", | |
6990 | "d,w", tempreg, treg); | |
6991 | macro_build ((char *) NULL, &icnt, NULL, "drorv", | |
6992 | "d,t,s", dreg, sreg, tempreg); | |
6993 | if (used_at) | |
6994 | break; | |
6995 | return; | |
6996 | } | |
771c7ce4 TS |
6997 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsubu", |
6998 | "d,v,t", AT, 0, treg); | |
6999 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsrlv", | |
7000 | "d,t,s", AT, sreg, AT); | |
7001 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsllv", | |
7002 | "d,t,s", dreg, sreg, treg); | |
7003 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", | |
7004 | "d,v,t", dreg, dreg, AT); | |
7005 | break; | |
7006 | ||
252b5132 | 7007 | case M_ROL: |
af7ee8bf | 7008 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_arch)) |
82dd0097 CD |
7009 | { |
7010 | if (dreg == sreg) | |
7011 | { | |
7012 | tempreg = AT; | |
7013 | used_at = 1; | |
7014 | } | |
7015 | else | |
7016 | { | |
7017 | tempreg = dreg; | |
7018 | used_at = 0; | |
7019 | } | |
7020 | macro_build ((char *) NULL, &icnt, NULL, "negu", | |
7021 | "d,w", tempreg, treg); | |
7022 | macro_build ((char *) NULL, &icnt, NULL, "rorv", | |
7023 | "d,t,s", dreg, sreg, tempreg); | |
7024 | if (used_at) | |
7025 | break; | |
7026 | return; | |
7027 | } | |
2396cfb9 TS |
7028 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "subu", |
7029 | "d,v,t", AT, 0, treg); | |
7030 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srlv", | |
7031 | "d,t,s", AT, sreg, AT); | |
7032 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sllv", | |
7033 | "d,t,s", dreg, sreg, treg); | |
7034 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", | |
7035 | "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
7036 | break; |
7037 | ||
771c7ce4 TS |
7038 | case M_DROL_I: |
7039 | { | |
7040 | unsigned int rot; | |
82dd0097 | 7041 | char *l, *r; |
771c7ce4 TS |
7042 | |
7043 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 7044 | as_bad (_("Improper rotate count")); |
771c7ce4 | 7045 | rot = imm_expr.X_add_number & 0x3f; |
af7ee8bf | 7046 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_arch)) |
60b63b72 RS |
7047 | { |
7048 | rot = (64 - rot) & 0x3f; | |
7049 | if (rot >= 32) | |
7050 | macro_build ((char *) NULL, &icnt, NULL, "dror32", | |
7051 | "d,w,<", dreg, sreg, rot - 32); | |
7052 | else | |
7053 | macro_build ((char *) NULL, &icnt, NULL, "dror", | |
7054 | "d,w,<", dreg, sreg, rot); | |
82dd0097 | 7055 | return; |
60b63b72 | 7056 | } |
483fc7cd | 7057 | if (rot == 0) |
483fc7cd | 7058 | { |
82dd0097 CD |
7059 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsrl", |
7060 | "d,w,<", dreg, sreg, 0); | |
7061 | return; | |
483fc7cd | 7062 | } |
82dd0097 CD |
7063 | l = (rot < 0x20) ? "dsll" : "dsll32"; |
7064 | r = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32"; | |
7065 | rot &= 0x1f; | |
7066 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, l, | |
7067 | "d,w,<", AT, sreg, rot); | |
7068 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, r, | |
7069 | "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); | |
7070 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", | |
7071 | "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
7072 | } |
7073 | break; | |
7074 | ||
252b5132 | 7075 | case M_ROL_I: |
771c7ce4 TS |
7076 | { |
7077 | unsigned int rot; | |
7078 | ||
7079 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 7080 | as_bad (_("Improper rotate count")); |
771c7ce4 | 7081 | rot = imm_expr.X_add_number & 0x1f; |
af7ee8bf | 7082 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_arch)) |
60b63b72 RS |
7083 | { |
7084 | macro_build ((char *) NULL, &icnt, NULL, "ror", | |
7085 | "d,w,<", dreg, sreg, (32 - rot) & 0x1f); | |
82dd0097 | 7086 | return; |
60b63b72 | 7087 | } |
483fc7cd | 7088 | if (rot == 0) |
483fc7cd | 7089 | { |
483fc7cd | 7090 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl", |
82dd0097 CD |
7091 | "d,w,<", dreg, sreg, 0); |
7092 | return; | |
483fc7cd | 7093 | } |
82dd0097 CD |
7094 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll", |
7095 | "d,w,<", AT, sreg, rot); | |
7096 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl", | |
7097 | "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); | |
7098 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", | |
7099 | "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
7100 | } |
7101 | break; | |
7102 | ||
7103 | case M_DROR: | |
af7ee8bf | 7104 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_arch)) |
82dd0097 CD |
7105 | { |
7106 | macro_build ((char *) NULL, &icnt, NULL, "drorv", | |
7107 | "d,t,s", dreg, sreg, treg); | |
7108 | return; | |
7109 | } | |
771c7ce4 TS |
7110 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsubu", |
7111 | "d,v,t", AT, 0, treg); | |
7112 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsllv", | |
7113 | "d,t,s", AT, sreg, AT); | |
7114 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsrlv", | |
7115 | "d,t,s", dreg, sreg, treg); | |
7116 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", | |
7117 | "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
7118 | break; |
7119 | ||
7120 | case M_ROR: | |
af7ee8bf | 7121 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_arch)) |
82dd0097 CD |
7122 | { |
7123 | macro_build ((char *) NULL, &icnt, NULL, "rorv", | |
7124 | "d,t,s", dreg, sreg, treg); | |
7125 | return; | |
7126 | } | |
2396cfb9 TS |
7127 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "subu", |
7128 | "d,v,t", AT, 0, treg); | |
7129 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sllv", | |
7130 | "d,t,s", AT, sreg, AT); | |
7131 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srlv", | |
7132 | "d,t,s", dreg, sreg, treg); | |
7133 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", | |
7134 | "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
7135 | break; |
7136 | ||
771c7ce4 TS |
7137 | case M_DROR_I: |
7138 | { | |
7139 | unsigned int rot; | |
82dd0097 | 7140 | char *l, *r; |
771c7ce4 TS |
7141 | |
7142 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 7143 | as_bad (_("Improper rotate count")); |
771c7ce4 | 7144 | rot = imm_expr.X_add_number & 0x3f; |
af7ee8bf | 7145 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_arch)) |
82dd0097 CD |
7146 | { |
7147 | if (rot >= 32) | |
7148 | macro_build ((char *) NULL, &icnt, NULL, "dror32", | |
7149 | "d,w,<", dreg, sreg, rot - 32); | |
7150 | else | |
7151 | macro_build ((char *) NULL, &icnt, NULL, "dror", | |
7152 | "d,w,<", dreg, sreg, rot); | |
7153 | return; | |
7154 | } | |
483fc7cd | 7155 | if (rot == 0) |
483fc7cd | 7156 | { |
82dd0097 CD |
7157 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsrl", |
7158 | "d,w,<", dreg, sreg, 0); | |
7159 | return; | |
483fc7cd | 7160 | } |
82dd0097 CD |
7161 | r = (rot < 0x20) ? "dsrl" : "dsrl32"; |
7162 | l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32"; | |
7163 | rot &= 0x1f; | |
7164 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, r, | |
7165 | "d,w,<", AT, sreg, rot); | |
7166 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, l, | |
7167 | "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); | |
7168 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", | |
7169 | "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
7170 | } |
7171 | break; | |
7172 | ||
252b5132 | 7173 | case M_ROR_I: |
771c7ce4 TS |
7174 | { |
7175 | unsigned int rot; | |
7176 | ||
7177 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 7178 | as_bad (_("Improper rotate count")); |
771c7ce4 | 7179 | rot = imm_expr.X_add_number & 0x1f; |
af7ee8bf | 7180 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_arch)) |
82dd0097 CD |
7181 | { |
7182 | macro_build ((char *) NULL, &icnt, NULL, "ror", | |
7183 | "d,w,<", dreg, sreg, rot); | |
7184 | return; | |
7185 | } | |
483fc7cd | 7186 | if (rot == 0) |
483fc7cd RS |
7187 | { |
7188 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl", | |
82dd0097 CD |
7189 | "d,w,<", dreg, sreg, 0); |
7190 | return; | |
483fc7cd | 7191 | } |
82dd0097 CD |
7192 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl", |
7193 | "d,w,<", AT, sreg, rot); | |
7194 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll", | |
7195 | "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); | |
7196 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", | |
7197 | "d,v,t", dreg, dreg, AT); | |
771c7ce4 | 7198 | } |
252b5132 RH |
7199 | break; |
7200 | ||
7201 | case M_S_DOB: | |
ec68c924 | 7202 | if (mips_arch == CPU_R4650) |
252b5132 RH |
7203 | { |
7204 | as_bad (_("opcode not supported on this processor")); | |
7205 | return; | |
7206 | } | |
e7af610e | 7207 | assert (mips_opts.isa == ISA_MIPS1); |
252b5132 RH |
7208 | /* Even on a big endian machine $fn comes before $fn+1. We have |
7209 | to adjust when storing to memory. */ | |
7210 | macro_build ((char *) NULL, &icnt, &offset_expr, "swc1", "T,o(b)", | |
7211 | target_big_endian ? treg + 1 : treg, | |
7212 | (int) BFD_RELOC_LO16, breg); | |
7213 | offset_expr.X_add_number += 4; | |
7214 | macro_build ((char *) NULL, &icnt, &offset_expr, "swc1", "T,o(b)", | |
7215 | target_big_endian ? treg : treg + 1, | |
7216 | (int) BFD_RELOC_LO16, breg); | |
7217 | return; | |
7218 | ||
7219 | case M_SEQ: | |
7220 | if (sreg == 0) | |
7221 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, | |
7222 | treg, (int) BFD_RELOC_LO16); | |
7223 | else if (treg == 0) | |
7224 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, | |
7225 | sreg, (int) BFD_RELOC_LO16); | |
7226 | else | |
7227 | { | |
2396cfb9 TS |
7228 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "xor", |
7229 | "d,v,t", dreg, sreg, treg); | |
252b5132 RH |
7230 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, |
7231 | dreg, (int) BFD_RELOC_LO16); | |
7232 | } | |
7233 | return; | |
7234 | ||
7235 | case M_SEQ_I: | |
7236 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
7237 | { | |
7238 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, | |
7239 | sreg, (int) BFD_RELOC_LO16); | |
7240 | return; | |
7241 | } | |
7242 | if (sreg == 0) | |
7243 | { | |
7244 | as_warn (_("Instruction %s: result is always false"), | |
7245 | ip->insn_mo->name); | |
ea1fb5dc | 7246 | move_register (&icnt, dreg, 0); |
252b5132 RH |
7247 | return; |
7248 | } | |
7249 | if (imm_expr.X_op == O_constant | |
7250 | && imm_expr.X_add_number >= 0 | |
7251 | && imm_expr.X_add_number < 0x10000) | |
7252 | { | |
7253 | macro_build ((char *) NULL, &icnt, &imm_expr, "xori", "t,r,i", dreg, | |
7254 | sreg, (int) BFD_RELOC_LO16); | |
7255 | used_at = 0; | |
7256 | } | |
7257 | else if (imm_expr.X_op == O_constant | |
7258 | && imm_expr.X_add_number > -0x8000 | |
7259 | && imm_expr.X_add_number < 0) | |
7260 | { | |
7261 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
7262 | macro_build ((char *) NULL, &icnt, &imm_expr, | |
ca4e0257 | 7263 | HAVE_32BIT_GPRS ? "addiu" : "daddiu", |
252b5132 RH |
7264 | "t,r,j", dreg, sreg, |
7265 | (int) BFD_RELOC_LO16); | |
7266 | used_at = 0; | |
7267 | } | |
7268 | else | |
7269 | { | |
4d34fb5f | 7270 | load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS); |
2396cfb9 TS |
7271 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "xor", |
7272 | "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7273 | used_at = 1; |
7274 | } | |
7275 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, dreg, | |
7276 | (int) BFD_RELOC_LO16); | |
7277 | if (used_at) | |
7278 | break; | |
7279 | return; | |
7280 | ||
7281 | case M_SGE: /* sreg >= treg <==> not (sreg < treg) */ | |
7282 | s = "slt"; | |
7283 | goto sge; | |
7284 | case M_SGEU: | |
7285 | s = "sltu"; | |
7286 | sge: | |
2396cfb9 TS |
7287 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "d,v,t", |
7288 | dreg, sreg, treg); | |
252b5132 RH |
7289 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, |
7290 | (int) BFD_RELOC_LO16); | |
7291 | return; | |
7292 | ||
7293 | case M_SGE_I: /* sreg >= I <==> not (sreg < I) */ | |
7294 | case M_SGEU_I: | |
7295 | if (imm_expr.X_op == O_constant | |
7296 | && imm_expr.X_add_number >= -0x8000 | |
7297 | && imm_expr.X_add_number < 0x8000) | |
7298 | { | |
7299 | macro_build ((char *) NULL, &icnt, &imm_expr, | |
7300 | mask == M_SGE_I ? "slti" : "sltiu", | |
7301 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); | |
7302 | used_at = 0; | |
7303 | } | |
7304 | else | |
7305 | { | |
4d34fb5f | 7306 | load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS); |
2396cfb9 TS |
7307 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
7308 | mask == M_SGE_I ? "slt" : "sltu", "d,v,t", dreg, sreg, | |
7309 | AT); | |
252b5132 RH |
7310 | used_at = 1; |
7311 | } | |
7312 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, | |
7313 | (int) BFD_RELOC_LO16); | |
7314 | if (used_at) | |
7315 | break; | |
7316 | return; | |
7317 | ||
7318 | case M_SGT: /* sreg > treg <==> treg < sreg */ | |
7319 | s = "slt"; | |
7320 | goto sgt; | |
7321 | case M_SGTU: | |
7322 | s = "sltu"; | |
7323 | sgt: | |
2396cfb9 TS |
7324 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "d,v,t", |
7325 | dreg, treg, sreg); | |
252b5132 RH |
7326 | return; |
7327 | ||
7328 | case M_SGT_I: /* sreg > I <==> I < sreg */ | |
7329 | s = "slt"; | |
7330 | goto sgti; | |
7331 | case M_SGTU_I: | |
7332 | s = "sltu"; | |
7333 | sgti: | |
4d34fb5f | 7334 | load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS); |
2396cfb9 TS |
7335 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "d,v,t", |
7336 | dreg, AT, sreg); | |
252b5132 RH |
7337 | break; |
7338 | ||
2396cfb9 | 7339 | case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */ |
252b5132 RH |
7340 | s = "slt"; |
7341 | goto sle; | |
7342 | case M_SLEU: | |
7343 | s = "sltu"; | |
7344 | sle: | |
2396cfb9 TS |
7345 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "d,v,t", |
7346 | dreg, treg, sreg); | |
252b5132 RH |
7347 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, |
7348 | (int) BFD_RELOC_LO16); | |
7349 | return; | |
7350 | ||
2396cfb9 | 7351 | case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */ |
252b5132 RH |
7352 | s = "slt"; |
7353 | goto slei; | |
7354 | case M_SLEU_I: | |
7355 | s = "sltu"; | |
7356 | slei: | |
4d34fb5f | 7357 | load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS); |
2396cfb9 TS |
7358 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "d,v,t", |
7359 | dreg, AT, sreg); | |
252b5132 RH |
7360 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, |
7361 | (int) BFD_RELOC_LO16); | |
7362 | break; | |
7363 | ||
7364 | case M_SLT_I: | |
7365 | if (imm_expr.X_op == O_constant | |
7366 | && imm_expr.X_add_number >= -0x8000 | |
7367 | && imm_expr.X_add_number < 0x8000) | |
7368 | { | |
7369 | macro_build ((char *) NULL, &icnt, &imm_expr, "slti", "t,r,j", | |
7370 | dreg, sreg, (int) BFD_RELOC_LO16); | |
7371 | return; | |
7372 | } | |
4d34fb5f | 7373 | load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS); |
2396cfb9 TS |
7374 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "slt", "d,v,t", |
7375 | dreg, sreg, AT); | |
252b5132 RH |
7376 | break; |
7377 | ||
7378 | case M_SLTU_I: | |
7379 | if (imm_expr.X_op == O_constant | |
7380 | && imm_expr.X_add_number >= -0x8000 | |
7381 | && imm_expr.X_add_number < 0x8000) | |
7382 | { | |
7383 | macro_build ((char *) NULL, &icnt, &imm_expr, "sltiu", "t,r,j", | |
7384 | dreg, sreg, (int) BFD_RELOC_LO16); | |
7385 | return; | |
7386 | } | |
4d34fb5f | 7387 | load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS); |
2396cfb9 TS |
7388 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu", |
7389 | "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7390 | break; |
7391 | ||
7392 | case M_SNE: | |
7393 | if (sreg == 0) | |
2396cfb9 TS |
7394 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu", |
7395 | "d,v,t", dreg, 0, treg); | |
252b5132 | 7396 | else if (treg == 0) |
2396cfb9 TS |
7397 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu", |
7398 | "d,v,t", dreg, 0, sreg); | |
252b5132 RH |
7399 | else |
7400 | { | |
2396cfb9 TS |
7401 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "xor", |
7402 | "d,v,t", dreg, sreg, treg); | |
7403 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu", | |
7404 | "d,v,t", dreg, 0, dreg); | |
252b5132 RH |
7405 | } |
7406 | return; | |
7407 | ||
7408 | case M_SNE_I: | |
7409 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
7410 | { | |
2396cfb9 TS |
7411 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu", |
7412 | "d,v,t", dreg, 0, sreg); | |
252b5132 RH |
7413 | return; |
7414 | } | |
7415 | if (sreg == 0) | |
7416 | { | |
7417 | as_warn (_("Instruction %s: result is always true"), | |
7418 | ip->insn_mo->name); | |
7419 | macro_build ((char *) NULL, &icnt, &expr1, | |
ca4e0257 | 7420 | HAVE_32BIT_GPRS ? "addiu" : "daddiu", |
252b5132 RH |
7421 | "t,r,j", dreg, 0, (int) BFD_RELOC_LO16); |
7422 | return; | |
7423 | } | |
7424 | if (imm_expr.X_op == O_constant | |
7425 | && imm_expr.X_add_number >= 0 | |
7426 | && imm_expr.X_add_number < 0x10000) | |
7427 | { | |
7428 | macro_build ((char *) NULL, &icnt, &imm_expr, "xori", "t,r,i", | |
7429 | dreg, sreg, (int) BFD_RELOC_LO16); | |
7430 | used_at = 0; | |
7431 | } | |
7432 | else if (imm_expr.X_op == O_constant | |
7433 | && imm_expr.X_add_number > -0x8000 | |
7434 | && imm_expr.X_add_number < 0) | |
7435 | { | |
7436 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
7437 | macro_build ((char *) NULL, &icnt, &imm_expr, | |
ca4e0257 | 7438 | HAVE_32BIT_GPRS ? "addiu" : "daddiu", |
252b5132 RH |
7439 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); |
7440 | used_at = 0; | |
7441 | } | |
7442 | else | |
7443 | { | |
4d34fb5f | 7444 | load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS); |
2396cfb9 TS |
7445 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "xor", |
7446 | "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7447 | used_at = 1; |
7448 | } | |
2396cfb9 TS |
7449 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu", |
7450 | "d,v,t", dreg, 0, dreg); | |
252b5132 RH |
7451 | if (used_at) |
7452 | break; | |
7453 | return; | |
7454 | ||
7455 | case M_DSUB_I: | |
7456 | dbl = 1; | |
7457 | case M_SUB_I: | |
7458 | if (imm_expr.X_op == O_constant | |
7459 | && imm_expr.X_add_number > -0x8000 | |
7460 | && imm_expr.X_add_number <= 0x8000) | |
7461 | { | |
7462 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
7463 | macro_build ((char *) NULL, &icnt, &imm_expr, | |
7464 | dbl ? "daddi" : "addi", | |
7465 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); | |
7466 | return; | |
7467 | } | |
7468 | load_register (&icnt, AT, &imm_expr, dbl); | |
2396cfb9 | 7469 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
9a41af64 | 7470 | dbl ? "dsub" : "sub", "d,v,t", dreg, sreg, AT); |
252b5132 RH |
7471 | break; |
7472 | ||
7473 | case M_DSUBU_I: | |
7474 | dbl = 1; | |
7475 | case M_SUBU_I: | |
7476 | if (imm_expr.X_op == O_constant | |
7477 | && imm_expr.X_add_number > -0x8000 | |
7478 | && imm_expr.X_add_number <= 0x8000) | |
7479 | { | |
7480 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
7481 | macro_build ((char *) NULL, &icnt, &imm_expr, | |
7482 | dbl ? "daddiu" : "addiu", | |
7483 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); | |
7484 | return; | |
7485 | } | |
7486 | load_register (&icnt, AT, &imm_expr, dbl); | |
2396cfb9 | 7487 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
9a41af64 | 7488 | dbl ? "dsubu" : "subu", "d,v,t", dreg, sreg, AT); |
252b5132 RH |
7489 | break; |
7490 | ||
7491 | case M_TEQ_I: | |
7492 | s = "teq"; | |
7493 | goto trap; | |
7494 | case M_TGE_I: | |
7495 | s = "tge"; | |
7496 | goto trap; | |
7497 | case M_TGEU_I: | |
7498 | s = "tgeu"; | |
7499 | goto trap; | |
7500 | case M_TLT_I: | |
7501 | s = "tlt"; | |
7502 | goto trap; | |
7503 | case M_TLTU_I: | |
7504 | s = "tltu"; | |
7505 | goto trap; | |
7506 | case M_TNE_I: | |
7507 | s = "tne"; | |
7508 | trap: | |
4d34fb5f | 7509 | load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS); |
2396cfb9 TS |
7510 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "s,t", sreg, |
7511 | AT); | |
252b5132 RH |
7512 | break; |
7513 | ||
252b5132 | 7514 | case M_TRUNCWS: |
43841e91 | 7515 | case M_TRUNCWD: |
e7af610e | 7516 | assert (mips_opts.isa == ISA_MIPS1); |
252b5132 RH |
7517 | sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */ |
7518 | dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */ | |
7519 | ||
7520 | /* | |
7521 | * Is the double cfc1 instruction a bug in the mips assembler; | |
7522 | * or is there a reason for it? | |
7523 | */ | |
b34976b6 | 7524 | mips_emit_delays (TRUE); |
252b5132 RH |
7525 | ++mips_opts.noreorder; |
7526 | mips_any_noreorder = 1; | |
2396cfb9 | 7527 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "cfc1", "t,G", |
f9419b05 | 7528 | treg, RA); |
2396cfb9 | 7529 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "cfc1", "t,G", |
f9419b05 | 7530 | treg, RA); |
2396cfb9 | 7531 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); |
252b5132 RH |
7532 | expr1.X_add_number = 3; |
7533 | macro_build ((char *) NULL, &icnt, &expr1, "ori", "t,r,i", AT, treg, | |
7534 | (int) BFD_RELOC_LO16); | |
7535 | expr1.X_add_number = 2; | |
7536 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", AT, AT, | |
7537 | (int) BFD_RELOC_LO16); | |
2396cfb9 | 7538 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "ctc1", "t,G", |
f9419b05 | 7539 | AT, RA); |
2396cfb9 TS |
7540 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); |
7541 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
252b5132 | 7542 | mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S", dreg, sreg); |
2396cfb9 | 7543 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "ctc1", "t,G", |
f9419b05 | 7544 | treg, RA); |
2396cfb9 | 7545 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); |
252b5132 RH |
7546 | --mips_opts.noreorder; |
7547 | break; | |
7548 | ||
7549 | case M_ULH: | |
7550 | s = "lb"; | |
7551 | goto ulh; | |
7552 | case M_ULHU: | |
7553 | s = "lbu"; | |
7554 | ulh: | |
7555 | if (offset_expr.X_add_number >= 0x7fff) | |
7556 | as_bad (_("operand overflow")); | |
7557 | /* avoid load delay */ | |
7558 | if (! target_big_endian) | |
f9419b05 | 7559 | ++offset_expr.X_add_number; |
252b5132 RH |
7560 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, |
7561 | (int) BFD_RELOC_LO16, breg); | |
7562 | if (! target_big_endian) | |
f9419b05 | 7563 | --offset_expr.X_add_number; |
252b5132 | 7564 | else |
f9419b05 | 7565 | ++offset_expr.X_add_number; |
252b5132 RH |
7566 | macro_build ((char *) NULL, &icnt, &offset_expr, "lbu", "t,o(b)", AT, |
7567 | (int) BFD_RELOC_LO16, breg); | |
2396cfb9 TS |
7568 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll", "d,w,<", |
7569 | treg, treg, 8); | |
7570 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", "d,v,t", | |
7571 | treg, treg, AT); | |
252b5132 RH |
7572 | break; |
7573 | ||
7574 | case M_ULD: | |
7575 | s = "ldl"; | |
7576 | s2 = "ldr"; | |
7577 | off = 7; | |
7578 | goto ulw; | |
7579 | case M_ULW: | |
7580 | s = "lwl"; | |
7581 | s2 = "lwr"; | |
7582 | off = 3; | |
7583 | ulw: | |
7584 | if (offset_expr.X_add_number >= 0x8000 - off) | |
7585 | as_bad (_("operand overflow")); | |
7586 | if (! target_big_endian) | |
7587 | offset_expr.X_add_number += off; | |
7588 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, | |
7589 | (int) BFD_RELOC_LO16, breg); | |
7590 | if (! target_big_endian) | |
7591 | offset_expr.X_add_number -= off; | |
7592 | else | |
7593 | offset_expr.X_add_number += off; | |
7594 | macro_build ((char *) NULL, &icnt, &offset_expr, s2, "t,o(b)", treg, | |
7595 | (int) BFD_RELOC_LO16, breg); | |
7596 | return; | |
7597 | ||
7598 | case M_ULD_A: | |
7599 | s = "ldl"; | |
7600 | s2 = "ldr"; | |
7601 | off = 7; | |
7602 | goto ulwa; | |
7603 | case M_ULW_A: | |
7604 | s = "lwl"; | |
7605 | s2 = "lwr"; | |
7606 | off = 3; | |
7607 | ulwa: | |
d6bc6245 | 7608 | used_at = 1; |
c9914766 | 7609 | load_address (&icnt, AT, &offset_expr, &used_at); |
252b5132 RH |
7610 | if (breg != 0) |
7611 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 7612 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
7613 | "d,v,t", AT, AT, breg); |
7614 | if (! target_big_endian) | |
7615 | expr1.X_add_number = off; | |
7616 | else | |
7617 | expr1.X_add_number = 0; | |
7618 | macro_build ((char *) NULL, &icnt, &expr1, s, "t,o(b)", treg, | |
7619 | (int) BFD_RELOC_LO16, AT); | |
7620 | if (! target_big_endian) | |
7621 | expr1.X_add_number = 0; | |
7622 | else | |
7623 | expr1.X_add_number = off; | |
7624 | macro_build ((char *) NULL, &icnt, &expr1, s2, "t,o(b)", treg, | |
7625 | (int) BFD_RELOC_LO16, AT); | |
7626 | break; | |
7627 | ||
7628 | case M_ULH_A: | |
7629 | case M_ULHU_A: | |
d6bc6245 | 7630 | used_at = 1; |
c9914766 | 7631 | load_address (&icnt, AT, &offset_expr, &used_at); |
252b5132 RH |
7632 | if (breg != 0) |
7633 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 7634 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
7635 | "d,v,t", AT, AT, breg); |
7636 | if (target_big_endian) | |
7637 | expr1.X_add_number = 0; | |
7638 | macro_build ((char *) NULL, &icnt, &expr1, | |
7639 | mask == M_ULH_A ? "lb" : "lbu", "t,o(b)", treg, | |
7640 | (int) BFD_RELOC_LO16, AT); | |
7641 | if (target_big_endian) | |
7642 | expr1.X_add_number = 1; | |
7643 | else | |
7644 | expr1.X_add_number = 0; | |
7645 | macro_build ((char *) NULL, &icnt, &expr1, "lbu", "t,o(b)", AT, | |
7646 | (int) BFD_RELOC_LO16, AT); | |
2396cfb9 TS |
7647 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll", "d,w,<", |
7648 | treg, treg, 8); | |
7649 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", "d,v,t", | |
7650 | treg, treg, AT); | |
252b5132 RH |
7651 | break; |
7652 | ||
7653 | case M_USH: | |
7654 | if (offset_expr.X_add_number >= 0x7fff) | |
7655 | as_bad (_("operand overflow")); | |
7656 | if (target_big_endian) | |
f9419b05 | 7657 | ++offset_expr.X_add_number; |
252b5132 RH |
7658 | macro_build ((char *) NULL, &icnt, &offset_expr, "sb", "t,o(b)", treg, |
7659 | (int) BFD_RELOC_LO16, breg); | |
2396cfb9 TS |
7660 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl", "d,w,<", |
7661 | AT, treg, 8); | |
252b5132 | 7662 | if (target_big_endian) |
f9419b05 | 7663 | --offset_expr.X_add_number; |
252b5132 | 7664 | else |
f9419b05 | 7665 | ++offset_expr.X_add_number; |
252b5132 RH |
7666 | macro_build ((char *) NULL, &icnt, &offset_expr, "sb", "t,o(b)", AT, |
7667 | (int) BFD_RELOC_LO16, breg); | |
7668 | break; | |
7669 | ||
7670 | case M_USD: | |
7671 | s = "sdl"; | |
7672 | s2 = "sdr"; | |
7673 | off = 7; | |
7674 | goto usw; | |
7675 | case M_USW: | |
7676 | s = "swl"; | |
7677 | s2 = "swr"; | |
7678 | off = 3; | |
7679 | usw: | |
7680 | if (offset_expr.X_add_number >= 0x8000 - off) | |
7681 | as_bad (_("operand overflow")); | |
7682 | if (! target_big_endian) | |
7683 | offset_expr.X_add_number += off; | |
7684 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, | |
7685 | (int) BFD_RELOC_LO16, breg); | |
7686 | if (! target_big_endian) | |
7687 | offset_expr.X_add_number -= off; | |
7688 | else | |
7689 | offset_expr.X_add_number += off; | |
7690 | macro_build ((char *) NULL, &icnt, &offset_expr, s2, "t,o(b)", treg, | |
7691 | (int) BFD_RELOC_LO16, breg); | |
7692 | return; | |
7693 | ||
7694 | case M_USD_A: | |
7695 | s = "sdl"; | |
7696 | s2 = "sdr"; | |
7697 | off = 7; | |
7698 | goto uswa; | |
7699 | case M_USW_A: | |
7700 | s = "swl"; | |
7701 | s2 = "swr"; | |
7702 | off = 3; | |
7703 | uswa: | |
d6bc6245 | 7704 | used_at = 1; |
c9914766 | 7705 | load_address (&icnt, AT, &offset_expr, &used_at); |
252b5132 RH |
7706 | if (breg != 0) |
7707 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 7708 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
7709 | "d,v,t", AT, AT, breg); |
7710 | if (! target_big_endian) | |
7711 | expr1.X_add_number = off; | |
7712 | else | |
7713 | expr1.X_add_number = 0; | |
7714 | macro_build ((char *) NULL, &icnt, &expr1, s, "t,o(b)", treg, | |
7715 | (int) BFD_RELOC_LO16, AT); | |
7716 | if (! target_big_endian) | |
7717 | expr1.X_add_number = 0; | |
7718 | else | |
7719 | expr1.X_add_number = off; | |
7720 | macro_build ((char *) NULL, &icnt, &expr1, s2, "t,o(b)", treg, | |
7721 | (int) BFD_RELOC_LO16, AT); | |
7722 | break; | |
7723 | ||
7724 | case M_USH_A: | |
d6bc6245 | 7725 | used_at = 1; |
c9914766 | 7726 | load_address (&icnt, AT, &offset_expr, &used_at); |
252b5132 RH |
7727 | if (breg != 0) |
7728 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 7729 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
7730 | "d,v,t", AT, AT, breg); |
7731 | if (! target_big_endian) | |
7732 | expr1.X_add_number = 0; | |
7733 | macro_build ((char *) NULL, &icnt, &expr1, "sb", "t,o(b)", treg, | |
7734 | (int) BFD_RELOC_LO16, AT); | |
2396cfb9 TS |
7735 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl", "d,w,<", |
7736 | treg, treg, 8); | |
252b5132 RH |
7737 | if (! target_big_endian) |
7738 | expr1.X_add_number = 1; | |
7739 | else | |
7740 | expr1.X_add_number = 0; | |
7741 | macro_build ((char *) NULL, &icnt, &expr1, "sb", "t,o(b)", treg, | |
7742 | (int) BFD_RELOC_LO16, AT); | |
7743 | if (! target_big_endian) | |
7744 | expr1.X_add_number = 0; | |
7745 | else | |
7746 | expr1.X_add_number = 1; | |
7747 | macro_build ((char *) NULL, &icnt, &expr1, "lbu", "t,o(b)", AT, | |
7748 | (int) BFD_RELOC_LO16, AT); | |
2396cfb9 TS |
7749 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll", "d,w,<", |
7750 | treg, treg, 8); | |
7751 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", "d,v,t", | |
7752 | treg, treg, AT); | |
252b5132 RH |
7753 | break; |
7754 | ||
7755 | default: | |
7756 | /* FIXME: Check if this is one of the itbl macros, since they | |
bdaaa2e1 | 7757 | are added dynamically. */ |
252b5132 RH |
7758 | as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name); |
7759 | break; | |
7760 | } | |
7761 | if (mips_opts.noat) | |
7762 | as_warn (_("Macro used $at after \".set noat\"")); | |
7763 | } | |
7764 | ||
7765 | /* Implement macros in mips16 mode. */ | |
7766 | ||
7767 | static void | |
7768 | mips16_macro (ip) | |
7769 | struct mips_cl_insn *ip; | |
7770 | { | |
7771 | int mask; | |
7772 | int xreg, yreg, zreg, tmp; | |
7773 | int icnt; | |
7774 | expressionS expr1; | |
7775 | int dbl; | |
7776 | const char *s, *s2, *s3; | |
7777 | ||
7778 | mask = ip->insn_mo->mask; | |
7779 | ||
7780 | xreg = (ip->insn_opcode >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX; | |
7781 | yreg = (ip->insn_opcode >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY; | |
7782 | zreg = (ip->insn_opcode >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ; | |
7783 | ||
7784 | icnt = 0; | |
7785 | ||
7786 | expr1.X_op = O_constant; | |
7787 | expr1.X_op_symbol = NULL; | |
7788 | expr1.X_add_symbol = NULL; | |
7789 | expr1.X_add_number = 1; | |
7790 | ||
7791 | dbl = 0; | |
7792 | ||
7793 | switch (mask) | |
7794 | { | |
7795 | default: | |
7796 | internalError (); | |
7797 | ||
7798 | case M_DDIV_3: | |
7799 | dbl = 1; | |
7800 | case M_DIV_3: | |
7801 | s = "mflo"; | |
7802 | goto do_div3; | |
7803 | case M_DREM_3: | |
7804 | dbl = 1; | |
7805 | case M_REM_3: | |
7806 | s = "mfhi"; | |
7807 | do_div3: | |
b34976b6 | 7808 | mips_emit_delays (TRUE); |
252b5132 RH |
7809 | ++mips_opts.noreorder; |
7810 | mips_any_noreorder = 1; | |
2396cfb9 | 7811 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
252b5132 RH |
7812 | dbl ? "ddiv" : "div", |
7813 | "0,x,y", xreg, yreg); | |
7814 | expr1.X_add_number = 2; | |
7815 | macro_build ((char *) NULL, &icnt, &expr1, "bnez", "x,p", yreg); | |
2396cfb9 TS |
7816 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break", "6", |
7817 | 7); | |
bdaaa2e1 | 7818 | |
252b5132 RH |
7819 | /* FIXME: The normal code checks for of -1 / -0x80000000 here, |
7820 | since that causes an overflow. We should do that as well, | |
7821 | but I don't see how to do the comparisons without a temporary | |
7822 | register. */ | |
7823 | --mips_opts.noreorder; | |
2396cfb9 | 7824 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "x", zreg); |
252b5132 RH |
7825 | break; |
7826 | ||
7827 | case M_DIVU_3: | |
7828 | s = "divu"; | |
7829 | s2 = "mflo"; | |
7830 | goto do_divu3; | |
7831 | case M_REMU_3: | |
7832 | s = "divu"; | |
7833 | s2 = "mfhi"; | |
7834 | goto do_divu3; | |
7835 | case M_DDIVU_3: | |
7836 | s = "ddivu"; | |
7837 | s2 = "mflo"; | |
7838 | goto do_divu3; | |
7839 | case M_DREMU_3: | |
7840 | s = "ddivu"; | |
7841 | s2 = "mfhi"; | |
7842 | do_divu3: | |
b34976b6 | 7843 | mips_emit_delays (TRUE); |
252b5132 RH |
7844 | ++mips_opts.noreorder; |
7845 | mips_any_noreorder = 1; | |
2396cfb9 TS |
7846 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "0,x,y", |
7847 | xreg, yreg); | |
252b5132 RH |
7848 | expr1.X_add_number = 2; |
7849 | macro_build ((char *) NULL, &icnt, &expr1, "bnez", "x,p", yreg); | |
98d3f06f KH |
7850 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break", |
7851 | "6", 7); | |
252b5132 | 7852 | --mips_opts.noreorder; |
2396cfb9 | 7853 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s2, "x", zreg); |
252b5132 RH |
7854 | break; |
7855 | ||
7856 | case M_DMUL: | |
7857 | dbl = 1; | |
7858 | case M_MUL: | |
2396cfb9 | 7859 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
9a41af64 | 7860 | dbl ? "dmultu" : "multu", "x,y", xreg, yreg); |
2396cfb9 TS |
7861 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mflo", "x", |
7862 | zreg); | |
252b5132 RH |
7863 | return; |
7864 | ||
7865 | case M_DSUBU_I: | |
7866 | dbl = 1; | |
7867 | goto do_subu; | |
7868 | case M_SUBU_I: | |
7869 | do_subu: | |
7870 | if (imm_expr.X_op != O_constant) | |
7871 | as_bad (_("Unsupported large constant")); | |
7872 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
7873 | macro_build ((char *) NULL, &icnt, &imm_expr, | |
9a41af64 | 7874 | dbl ? "daddiu" : "addiu", "y,x,4", yreg, xreg); |
252b5132 RH |
7875 | break; |
7876 | ||
7877 | case M_SUBU_I_2: | |
7878 | if (imm_expr.X_op != O_constant) | |
7879 | as_bad (_("Unsupported large constant")); | |
7880 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
7881 | macro_build ((char *) NULL, &icnt, &imm_expr, "addiu", | |
7882 | "x,k", xreg); | |
7883 | break; | |
7884 | ||
7885 | case M_DSUBU_I_2: | |
7886 | if (imm_expr.X_op != O_constant) | |
7887 | as_bad (_("Unsupported large constant")); | |
7888 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
7889 | macro_build ((char *) NULL, &icnt, &imm_expr, "daddiu", | |
7890 | "y,j", yreg); | |
7891 | break; | |
7892 | ||
7893 | case M_BEQ: | |
7894 | s = "cmp"; | |
7895 | s2 = "bteqz"; | |
7896 | goto do_branch; | |
7897 | case M_BNE: | |
7898 | s = "cmp"; | |
7899 | s2 = "btnez"; | |
7900 | goto do_branch; | |
7901 | case M_BLT: | |
7902 | s = "slt"; | |
7903 | s2 = "btnez"; | |
7904 | goto do_branch; | |
7905 | case M_BLTU: | |
7906 | s = "sltu"; | |
7907 | s2 = "btnez"; | |
7908 | goto do_branch; | |
7909 | case M_BLE: | |
7910 | s = "slt"; | |
7911 | s2 = "bteqz"; | |
7912 | goto do_reverse_branch; | |
7913 | case M_BLEU: | |
7914 | s = "sltu"; | |
7915 | s2 = "bteqz"; | |
7916 | goto do_reverse_branch; | |
7917 | case M_BGE: | |
7918 | s = "slt"; | |
7919 | s2 = "bteqz"; | |
7920 | goto do_branch; | |
7921 | case M_BGEU: | |
7922 | s = "sltu"; | |
7923 | s2 = "bteqz"; | |
7924 | goto do_branch; | |
7925 | case M_BGT: | |
7926 | s = "slt"; | |
7927 | s2 = "btnez"; | |
7928 | goto do_reverse_branch; | |
7929 | case M_BGTU: | |
7930 | s = "sltu"; | |
7931 | s2 = "btnez"; | |
7932 | ||
7933 | do_reverse_branch: | |
7934 | tmp = xreg; | |
7935 | xreg = yreg; | |
7936 | yreg = tmp; | |
7937 | ||
7938 | do_branch: | |
7939 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "x,y", | |
7940 | xreg, yreg); | |
7941 | macro_build ((char *) NULL, &icnt, &offset_expr, s2, "p"); | |
7942 | break; | |
7943 | ||
7944 | case M_BEQ_I: | |
7945 | s = "cmpi"; | |
7946 | s2 = "bteqz"; | |
7947 | s3 = "x,U"; | |
7948 | goto do_branch_i; | |
7949 | case M_BNE_I: | |
7950 | s = "cmpi"; | |
7951 | s2 = "btnez"; | |
7952 | s3 = "x,U"; | |
7953 | goto do_branch_i; | |
7954 | case M_BLT_I: | |
7955 | s = "slti"; | |
7956 | s2 = "btnez"; | |
7957 | s3 = "x,8"; | |
7958 | goto do_branch_i; | |
7959 | case M_BLTU_I: | |
7960 | s = "sltiu"; | |
7961 | s2 = "btnez"; | |
7962 | s3 = "x,8"; | |
7963 | goto do_branch_i; | |
7964 | case M_BLE_I: | |
7965 | s = "slti"; | |
7966 | s2 = "btnez"; | |
7967 | s3 = "x,8"; | |
7968 | goto do_addone_branch_i; | |
7969 | case M_BLEU_I: | |
7970 | s = "sltiu"; | |
7971 | s2 = "btnez"; | |
7972 | s3 = "x,8"; | |
7973 | goto do_addone_branch_i; | |
7974 | case M_BGE_I: | |
7975 | s = "slti"; | |
7976 | s2 = "bteqz"; | |
7977 | s3 = "x,8"; | |
7978 | goto do_branch_i; | |
7979 | case M_BGEU_I: | |
7980 | s = "sltiu"; | |
7981 | s2 = "bteqz"; | |
7982 | s3 = "x,8"; | |
7983 | goto do_branch_i; | |
7984 | case M_BGT_I: | |
7985 | s = "slti"; | |
7986 | s2 = "bteqz"; | |
7987 | s3 = "x,8"; | |
7988 | goto do_addone_branch_i; | |
7989 | case M_BGTU_I: | |
7990 | s = "sltiu"; | |
7991 | s2 = "bteqz"; | |
7992 | s3 = "x,8"; | |
7993 | ||
7994 | do_addone_branch_i: | |
7995 | if (imm_expr.X_op != O_constant) | |
7996 | as_bad (_("Unsupported large constant")); | |
7997 | ++imm_expr.X_add_number; | |
7998 | ||
7999 | do_branch_i: | |
8000 | macro_build ((char *) NULL, &icnt, &imm_expr, s, s3, xreg); | |
8001 | macro_build ((char *) NULL, &icnt, &offset_expr, s2, "p"); | |
8002 | break; | |
8003 | ||
8004 | case M_ABS: | |
8005 | expr1.X_add_number = 0; | |
98d3f06f | 8006 | macro_build ((char *) NULL, &icnt, &expr1, "slti", "x,8", yreg); |
252b5132 | 8007 | if (xreg != yreg) |
ea1fb5dc | 8008 | move_register (&icnt, xreg, yreg); |
252b5132 RH |
8009 | expr1.X_add_number = 2; |
8010 | macro_build ((char *) NULL, &icnt, &expr1, "bteqz", "p"); | |
8011 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
8012 | "neg", "x,w", xreg, xreg); | |
8013 | } | |
8014 | } | |
8015 | ||
8016 | /* For consistency checking, verify that all bits are specified either | |
8017 | by the match/mask part of the instruction definition, or by the | |
8018 | operand list. */ | |
8019 | static int | |
8020 | validate_mips_insn (opc) | |
8021 | const struct mips_opcode *opc; | |
8022 | { | |
8023 | const char *p = opc->args; | |
8024 | char c; | |
8025 | unsigned long used_bits = opc->mask; | |
8026 | ||
8027 | if ((used_bits & opc->match) != opc->match) | |
8028 | { | |
8029 | as_bad (_("internal: bad mips opcode (mask error): %s %s"), | |
8030 | opc->name, opc->args); | |
8031 | return 0; | |
8032 | } | |
8033 | #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift))) | |
8034 | while (*p) | |
8035 | switch (c = *p++) | |
8036 | { | |
8037 | case ',': break; | |
8038 | case '(': break; | |
8039 | case ')': break; | |
af7ee8bf CD |
8040 | case '+': |
8041 | switch (c = *p++) | |
8042 | { | |
8043 | case 'A': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; | |
8044 | case 'B': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break; | |
8045 | case 'C': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
bbcc0807 CD |
8046 | case 'D': USE_BITS (OP_MASK_RD, OP_SH_RD); |
8047 | USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; | |
af7ee8bf CD |
8048 | default: |
8049 | as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"), | |
8050 | c, opc->name, opc->args); | |
8051 | return 0; | |
8052 | } | |
8053 | break; | |
252b5132 RH |
8054 | case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
8055 | case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; | |
8056 | case 'A': break; | |
4372b673 | 8057 | case 'B': USE_BITS (OP_MASK_CODE20, OP_SH_CODE20); break; |
252b5132 RH |
8058 | case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break; |
8059 | case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break; | |
8060 | case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
8061 | case 'F': break; | |
8062 | case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
156c2f8b | 8063 | case 'H': USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; |
252b5132 | 8064 | case 'I': break; |
e972090a | 8065 | case 'J': USE_BITS (OP_MASK_CODE19, OP_SH_CODE19); break; |
af7ee8bf | 8066 | case 'K': USE_BITS (OP_MASK_RD, OP_SH_RD); break; |
252b5132 RH |
8067 | case 'L': break; |
8068 | case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break; | |
8069 | case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break; | |
deec1734 CD |
8070 | case 'O': USE_BITS (OP_MASK_ALN, OP_SH_ALN); break; |
8071 | case 'Q': USE_BITS (OP_MASK_VSEL, OP_SH_VSEL); | |
8072 | USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
252b5132 RH |
8073 | case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break; |
8074 | case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
8075 | case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
8076 | case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
8077 | case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
deec1734 CD |
8078 | case 'X': USE_BITS (OP_MASK_FD, OP_SH_FD); break; |
8079 | case 'Y': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
8080 | case 'Z': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
252b5132 RH |
8081 | case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break; |
8082 | case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
8083 | case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break; | |
8084 | case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
8085 | case 'f': break; | |
8086 | case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break; | |
8087 | case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; | |
8088 | case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
8089 | case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break; | |
8090 | case 'l': break; | |
8091 | case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
8092 | case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
8093 | case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break; | |
8094 | case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
8095 | case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
8096 | case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
8097 | case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; | |
8098 | case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
8099 | case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
8100 | case 'x': break; | |
8101 | case 'z': break; | |
8102 | case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break; | |
4372b673 NC |
8103 | case 'U': USE_BITS (OP_MASK_RD, OP_SH_RD); |
8104 | USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
60b63b72 RS |
8105 | case 'e': USE_BITS (OP_MASK_VECBYTE, OP_SH_VECBYTE); break; |
8106 | case '%': USE_BITS (OP_MASK_VECALIGN, OP_SH_VECALIGN); break; | |
8107 | case '[': break; | |
8108 | case ']': break; | |
252b5132 RH |
8109 | default: |
8110 | as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"), | |
8111 | c, opc->name, opc->args); | |
8112 | return 0; | |
8113 | } | |
8114 | #undef USE_BITS | |
8115 | if (used_bits != 0xffffffff) | |
8116 | { | |
8117 | as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"), | |
8118 | ~used_bits & 0xffffffff, opc->name, opc->args); | |
8119 | return 0; | |
8120 | } | |
8121 | return 1; | |
8122 | } | |
8123 | ||
8124 | /* This routine assembles an instruction into its binary format. As a | |
8125 | side effect, it sets one of the global variables imm_reloc or | |
8126 | offset_reloc to the type of relocation to do if one of the operands | |
8127 | is an address expression. */ | |
8128 | ||
8129 | static void | |
8130 | mips_ip (str, ip) | |
8131 | char *str; | |
8132 | struct mips_cl_insn *ip; | |
8133 | { | |
8134 | char *s; | |
8135 | const char *args; | |
43841e91 | 8136 | char c = 0; |
252b5132 RH |
8137 | struct mips_opcode *insn; |
8138 | char *argsStart; | |
8139 | unsigned int regno; | |
8140 | unsigned int lastregno = 0; | |
af7ee8bf | 8141 | unsigned int lastpos = 0; |
071742cf | 8142 | unsigned int limlo, limhi; |
252b5132 RH |
8143 | char *s_reset; |
8144 | char save_c = 0; | |
252b5132 RH |
8145 | |
8146 | insn_error = NULL; | |
8147 | ||
8148 | /* If the instruction contains a '.', we first try to match an instruction | |
8149 | including the '.'. Then we try again without the '.'. */ | |
8150 | insn = NULL; | |
3882b010 | 8151 | for (s = str; *s != '\0' && !ISSPACE (*s); ++s) |
252b5132 RH |
8152 | continue; |
8153 | ||
8154 | /* If we stopped on whitespace, then replace the whitespace with null for | |
8155 | the call to hash_find. Save the character we replaced just in case we | |
8156 | have to re-parse the instruction. */ | |
3882b010 | 8157 | if (ISSPACE (*s)) |
252b5132 RH |
8158 | { |
8159 | save_c = *s; | |
8160 | *s++ = '\0'; | |
8161 | } | |
bdaaa2e1 | 8162 | |
252b5132 RH |
8163 | insn = (struct mips_opcode *) hash_find (op_hash, str); |
8164 | ||
8165 | /* If we didn't find the instruction in the opcode table, try again, but | |
8166 | this time with just the instruction up to, but not including the | |
8167 | first '.'. */ | |
8168 | if (insn == NULL) | |
8169 | { | |
bdaaa2e1 | 8170 | /* Restore the character we overwrite above (if any). */ |
252b5132 RH |
8171 | if (save_c) |
8172 | *(--s) = save_c; | |
8173 | ||
8174 | /* Scan up to the first '.' or whitespace. */ | |
3882b010 L |
8175 | for (s = str; |
8176 | *s != '\0' && *s != '.' && !ISSPACE (*s); | |
8177 | ++s) | |
252b5132 RH |
8178 | continue; |
8179 | ||
8180 | /* If we did not find a '.', then we can quit now. */ | |
8181 | if (*s != '.') | |
8182 | { | |
8183 | insn_error = "unrecognized opcode"; | |
8184 | return; | |
8185 | } | |
8186 | ||
8187 | /* Lookup the instruction in the hash table. */ | |
8188 | *s++ = '\0'; | |
8189 | if ((insn = (struct mips_opcode *) hash_find (op_hash, str)) == NULL) | |
8190 | { | |
8191 | insn_error = "unrecognized opcode"; | |
8192 | return; | |
8193 | } | |
252b5132 RH |
8194 | } |
8195 | ||
8196 | argsStart = s; | |
8197 | for (;;) | |
8198 | { | |
b34976b6 | 8199 | bfd_boolean ok; |
252b5132 RH |
8200 | |
8201 | assert (strcmp (insn->name, str) == 0); | |
8202 | ||
1f25f5d3 CD |
8203 | if (OPCODE_IS_MEMBER (insn, |
8204 | (mips_opts.isa | |
3396de36 | 8205 | | (file_ase_mips16 ? INSN_MIPS16 : 0) |
deec1734 | 8206 | | (mips_opts.ase_mdmx ? INSN_MDMX : 0) |
98d3f06f | 8207 | | (mips_opts.ase_mips3d ? INSN_MIPS3D : 0)), |
1f25f5d3 | 8208 | mips_arch)) |
b34976b6 | 8209 | ok = TRUE; |
bdaaa2e1 | 8210 | else |
b34976b6 | 8211 | ok = FALSE; |
bdaaa2e1 | 8212 | |
252b5132 RH |
8213 | if (insn->pinfo != INSN_MACRO) |
8214 | { | |
ec68c924 | 8215 | if (mips_arch == CPU_R4650 && (insn->pinfo & FP_D) != 0) |
b34976b6 | 8216 | ok = FALSE; |
252b5132 RH |
8217 | } |
8218 | ||
8219 | if (! ok) | |
8220 | { | |
8221 | if (insn + 1 < &mips_opcodes[NUMOPCODES] | |
8222 | && strcmp (insn->name, insn[1].name) == 0) | |
8223 | { | |
8224 | ++insn; | |
8225 | continue; | |
8226 | } | |
252b5132 | 8227 | else |
beae10d5 | 8228 | { |
268f6bed L |
8229 | if (!insn_error) |
8230 | { | |
8231 | static char buf[100]; | |
316f5878 RS |
8232 | if (mips_arch_info->is_isa) |
8233 | sprintf (buf, | |
8234 | _("opcode not supported at this ISA level (%s)"), | |
8235 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
8236 | else | |
8237 | sprintf (buf, | |
8238 | _("opcode not supported on this processor: %s (%s)"), | |
8239 | mips_arch_info->name, | |
8240 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
268f6bed L |
8241 | insn_error = buf; |
8242 | } | |
8243 | if (save_c) | |
8244 | *(--s) = save_c; | |
2bd7f1f3 | 8245 | return; |
252b5132 | 8246 | } |
252b5132 RH |
8247 | } |
8248 | ||
8249 | ip->insn_mo = insn; | |
8250 | ip->insn_opcode = insn->match; | |
268f6bed | 8251 | insn_error = NULL; |
252b5132 RH |
8252 | for (args = insn->args;; ++args) |
8253 | { | |
deec1734 CD |
8254 | int is_mdmx; |
8255 | ||
ad8d3bb3 | 8256 | s += strspn (s, " \t"); |
deec1734 | 8257 | is_mdmx = 0; |
252b5132 RH |
8258 | switch (*args) |
8259 | { | |
8260 | case '\0': /* end of args */ | |
8261 | if (*s == '\0') | |
8262 | return; | |
8263 | break; | |
8264 | ||
8265 | case ',': | |
8266 | if (*s++ == *args) | |
8267 | continue; | |
8268 | s--; | |
8269 | switch (*++args) | |
8270 | { | |
8271 | case 'r': | |
8272 | case 'v': | |
38487616 | 8273 | ip->insn_opcode |= lastregno << OP_SH_RS; |
252b5132 RH |
8274 | continue; |
8275 | ||
8276 | case 'w': | |
38487616 TS |
8277 | ip->insn_opcode |= lastregno << OP_SH_RT; |
8278 | continue; | |
8279 | ||
252b5132 | 8280 | case 'W': |
38487616 | 8281 | ip->insn_opcode |= lastregno << OP_SH_FT; |
252b5132 RH |
8282 | continue; |
8283 | ||
8284 | case 'V': | |
38487616 | 8285 | ip->insn_opcode |= lastregno << OP_SH_FS; |
252b5132 RH |
8286 | continue; |
8287 | } | |
8288 | break; | |
8289 | ||
8290 | case '(': | |
8291 | /* Handle optional base register. | |
8292 | Either the base register is omitted or | |
bdaaa2e1 | 8293 | we must have a left paren. */ |
252b5132 RH |
8294 | /* This is dependent on the next operand specifier |
8295 | is a base register specification. */ | |
8296 | assert (args[1] == 'b' || args[1] == '5' | |
8297 | || args[1] == '-' || args[1] == '4'); | |
8298 | if (*s == '\0') | |
8299 | return; | |
8300 | ||
8301 | case ')': /* these must match exactly */ | |
60b63b72 RS |
8302 | case '[': |
8303 | case ']': | |
252b5132 RH |
8304 | if (*s++ == *args) |
8305 | continue; | |
8306 | break; | |
8307 | ||
af7ee8bf CD |
8308 | case '+': /* Opcode extension character. */ |
8309 | switch (*++args) | |
8310 | { | |
071742cf CD |
8311 | case 'A': /* ins/ext position, becomes LSB. */ |
8312 | limlo = 0; | |
8313 | limhi = 31; | |
8314 | my_getExpression (&imm_expr, s); | |
8315 | check_absolute_expr (ip, &imm_expr); | |
8316 | if ((unsigned long) imm_expr.X_add_number < limlo | |
8317 | || (unsigned long) imm_expr.X_add_number > limhi) | |
8318 | { | |
8319 | as_bad (_("Improper position (%lu)"), | |
8320 | (unsigned long) imm_expr.X_add_number); | |
8321 | imm_expr.X_add_number = limlo; | |
8322 | } | |
8323 | lastpos = imm_expr.X_add_number; | |
8324 | ip->insn_opcode |= (imm_expr.X_add_number | |
8325 | & OP_MASK_SHAMT) << OP_SH_SHAMT; | |
8326 | imm_expr.X_op = O_absent; | |
8327 | s = expr_end; | |
8328 | continue; | |
8329 | ||
8330 | case 'B': /* ins size, becomes MSB. */ | |
8331 | limlo = 1; | |
8332 | limhi = 32; | |
8333 | my_getExpression (&imm_expr, s); | |
8334 | check_absolute_expr (ip, &imm_expr); | |
8335 | /* Check for negative input so that small negative numbers | |
8336 | will not succeed incorrectly. The checks against | |
8337 | (pos+size) transitively check "size" itself, | |
8338 | assuming that "pos" is reasonable. */ | |
8339 | if ((long) imm_expr.X_add_number < 0 | |
8340 | || ((unsigned long) imm_expr.X_add_number | |
8341 | + lastpos) < limlo | |
8342 | || ((unsigned long) imm_expr.X_add_number | |
8343 | + lastpos) > limhi) | |
8344 | { | |
8345 | as_bad (_("Improper insert size (%lu, position %lu)"), | |
8346 | (unsigned long) imm_expr.X_add_number, | |
8347 | (unsigned long) lastpos); | |
8348 | imm_expr.X_add_number = limlo - lastpos; | |
8349 | } | |
8350 | ip->insn_opcode |= ((lastpos + imm_expr.X_add_number - 1) | |
8351 | & OP_MASK_INSMSB) << OP_SH_INSMSB; | |
8352 | imm_expr.X_op = O_absent; | |
8353 | s = expr_end; | |
8354 | continue; | |
8355 | ||
8356 | case 'C': /* ext size, becomes MSBD. */ | |
8357 | limlo = 1; | |
8358 | limhi = 32; | |
8359 | my_getExpression (&imm_expr, s); | |
8360 | check_absolute_expr (ip, &imm_expr); | |
8361 | /* Check for negative input so that small negative numbers | |
8362 | will not succeed incorrectly. The checks against | |
8363 | (pos+size) transitively check "size" itself, | |
8364 | assuming that "pos" is reasonable. */ | |
8365 | if ((long) imm_expr.X_add_number < 0 | |
8366 | || ((unsigned long) imm_expr.X_add_number | |
8367 | + lastpos) < limlo | |
8368 | || ((unsigned long) imm_expr.X_add_number | |
8369 | + lastpos) > limhi) | |
8370 | { | |
8371 | as_bad (_("Improper extract size (%lu, position %lu)"), | |
8372 | (unsigned long) imm_expr.X_add_number, | |
8373 | (unsigned long) lastpos); | |
8374 | imm_expr.X_add_number = limlo - lastpos; | |
8375 | } | |
8376 | ip->insn_opcode |= ((imm_expr.X_add_number - 1) | |
8377 | & OP_MASK_EXTMSBD) << OP_SH_EXTMSBD; | |
8378 | imm_expr.X_op = O_absent; | |
8379 | s = expr_end; | |
8380 | continue; | |
af7ee8bf | 8381 | |
bbcc0807 CD |
8382 | case 'D': |
8383 | /* +D is for disassembly only; never match. */ | |
8384 | break; | |
8385 | ||
af7ee8bf CD |
8386 | default: |
8387 | as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"), | |
8388 | *args, insn->name, insn->args); | |
8389 | /* Further processing is fruitless. */ | |
8390 | return; | |
8391 | } | |
8392 | break; | |
8393 | ||
252b5132 RH |
8394 | case '<': /* must be at least one digit */ |
8395 | /* | |
8396 | * According to the manual, if the shift amount is greater | |
b6ff326e KH |
8397 | * than 31 or less than 0, then the shift amount should be |
8398 | * mod 32. In reality the mips assembler issues an error. | |
252b5132 RH |
8399 | * We issue a warning and mask out all but the low 5 bits. |
8400 | */ | |
8401 | my_getExpression (&imm_expr, s); | |
8402 | check_absolute_expr (ip, &imm_expr); | |
8403 | if ((unsigned long) imm_expr.X_add_number > 31) | |
8404 | { | |
793b27f4 TS |
8405 | as_warn (_("Improper shift amount (%lu)"), |
8406 | (unsigned long) imm_expr.X_add_number); | |
38487616 | 8407 | imm_expr.X_add_number &= OP_MASK_SHAMT; |
252b5132 | 8408 | } |
38487616 | 8409 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_SHAMT; |
252b5132 RH |
8410 | imm_expr.X_op = O_absent; |
8411 | s = expr_end; | |
8412 | continue; | |
8413 | ||
8414 | case '>': /* shift amount minus 32 */ | |
8415 | my_getExpression (&imm_expr, s); | |
8416 | check_absolute_expr (ip, &imm_expr); | |
8417 | if ((unsigned long) imm_expr.X_add_number < 32 | |
8418 | || (unsigned long) imm_expr.X_add_number > 63) | |
8419 | break; | |
38487616 | 8420 | ip->insn_opcode |= (imm_expr.X_add_number - 32) << OP_SH_SHAMT; |
252b5132 RH |
8421 | imm_expr.X_op = O_absent; |
8422 | s = expr_end; | |
8423 | continue; | |
8424 | ||
252b5132 RH |
8425 | case 'k': /* cache code */ |
8426 | case 'h': /* prefx code */ | |
8427 | my_getExpression (&imm_expr, s); | |
8428 | check_absolute_expr (ip, &imm_expr); | |
8429 | if ((unsigned long) imm_expr.X_add_number > 31) | |
8430 | { | |
8431 | as_warn (_("Invalid value for `%s' (%lu)"), | |
8432 | ip->insn_mo->name, | |
8433 | (unsigned long) imm_expr.X_add_number); | |
8434 | imm_expr.X_add_number &= 0x1f; | |
8435 | } | |
8436 | if (*args == 'k') | |
8437 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CACHE; | |
8438 | else | |
8439 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_PREFX; | |
8440 | imm_expr.X_op = O_absent; | |
8441 | s = expr_end; | |
8442 | continue; | |
8443 | ||
8444 | case 'c': /* break code */ | |
8445 | my_getExpression (&imm_expr, s); | |
8446 | check_absolute_expr (ip, &imm_expr); | |
793b27f4 | 8447 | if ((unsigned long) imm_expr.X_add_number > 1023) |
252b5132 | 8448 | { |
793b27f4 TS |
8449 | as_warn (_("Illegal break code (%lu)"), |
8450 | (unsigned long) imm_expr.X_add_number); | |
38487616 | 8451 | imm_expr.X_add_number &= OP_MASK_CODE; |
252b5132 | 8452 | } |
38487616 | 8453 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE; |
252b5132 RH |
8454 | imm_expr.X_op = O_absent; |
8455 | s = expr_end; | |
8456 | continue; | |
8457 | ||
8458 | case 'q': /* lower break code */ | |
8459 | my_getExpression (&imm_expr, s); | |
8460 | check_absolute_expr (ip, &imm_expr); | |
793b27f4 | 8461 | if ((unsigned long) imm_expr.X_add_number > 1023) |
252b5132 | 8462 | { |
793b27f4 TS |
8463 | as_warn (_("Illegal lower break code (%lu)"), |
8464 | (unsigned long) imm_expr.X_add_number); | |
38487616 | 8465 | imm_expr.X_add_number &= OP_MASK_CODE2; |
252b5132 | 8466 | } |
38487616 | 8467 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE2; |
252b5132 RH |
8468 | imm_expr.X_op = O_absent; |
8469 | s = expr_end; | |
8470 | continue; | |
8471 | ||
4372b673 | 8472 | case 'B': /* 20-bit syscall/break code. */ |
156c2f8b | 8473 | my_getExpression (&imm_expr, s); |
156c2f8b | 8474 | check_absolute_expr (ip, &imm_expr); |
793b27f4 TS |
8475 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE20) |
8476 | as_warn (_("Illegal 20-bit code (%lu)"), | |
8477 | (unsigned long) imm_expr.X_add_number); | |
38487616 | 8478 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE20; |
252b5132 RH |
8479 | imm_expr.X_op = O_absent; |
8480 | s = expr_end; | |
8481 | continue; | |
8482 | ||
98d3f06f | 8483 | case 'C': /* Coprocessor code */ |
beae10d5 | 8484 | my_getExpression (&imm_expr, s); |
252b5132 | 8485 | check_absolute_expr (ip, &imm_expr); |
98d3f06f | 8486 | if ((unsigned long) imm_expr.X_add_number >= (1 << 25)) |
252b5132 | 8487 | { |
793b27f4 TS |
8488 | as_warn (_("Coproccesor code > 25 bits (%lu)"), |
8489 | (unsigned long) imm_expr.X_add_number); | |
98d3f06f | 8490 | imm_expr.X_add_number &= ((1 << 25) - 1); |
252b5132 | 8491 | } |
beae10d5 KH |
8492 | ip->insn_opcode |= imm_expr.X_add_number; |
8493 | imm_expr.X_op = O_absent; | |
8494 | s = expr_end; | |
8495 | continue; | |
252b5132 | 8496 | |
4372b673 NC |
8497 | case 'J': /* 19-bit wait code. */ |
8498 | my_getExpression (&imm_expr, s); | |
8499 | check_absolute_expr (ip, &imm_expr); | |
793b27f4 TS |
8500 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE19) |
8501 | as_warn (_("Illegal 19-bit code (%lu)"), | |
8502 | (unsigned long) imm_expr.X_add_number); | |
38487616 | 8503 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE19; |
4372b673 NC |
8504 | imm_expr.X_op = O_absent; |
8505 | s = expr_end; | |
8506 | continue; | |
8507 | ||
252b5132 | 8508 | case 'P': /* Performance register */ |
beae10d5 | 8509 | my_getExpression (&imm_expr, s); |
252b5132 | 8510 | check_absolute_expr (ip, &imm_expr); |
beae10d5 | 8511 | if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1) |
252b5132 | 8512 | { |
793b27f4 TS |
8513 | as_warn (_("Invalid performance register (%lu)"), |
8514 | (unsigned long) imm_expr.X_add_number); | |
38487616 | 8515 | imm_expr.X_add_number &= OP_MASK_PERFREG; |
252b5132 | 8516 | } |
38487616 | 8517 | ip->insn_opcode |= (imm_expr.X_add_number << OP_SH_PERFREG); |
beae10d5 KH |
8518 | imm_expr.X_op = O_absent; |
8519 | s = expr_end; | |
8520 | continue; | |
252b5132 RH |
8521 | |
8522 | case 'b': /* base register */ | |
8523 | case 'd': /* destination register */ | |
8524 | case 's': /* source register */ | |
8525 | case 't': /* target register */ | |
8526 | case 'r': /* both target and source */ | |
8527 | case 'v': /* both dest and source */ | |
8528 | case 'w': /* both dest and target */ | |
8529 | case 'E': /* coprocessor target register */ | |
8530 | case 'G': /* coprocessor destination register */ | |
af7ee8bf | 8531 | case 'K': /* 'rdhwr' destination register */ |
252b5132 RH |
8532 | case 'x': /* ignore register name */ |
8533 | case 'z': /* must be zero register */ | |
4372b673 | 8534 | case 'U': /* destination register (clo/clz). */ |
252b5132 RH |
8535 | s_reset = s; |
8536 | if (s[0] == '$') | |
8537 | { | |
8538 | ||
3882b010 | 8539 | if (ISDIGIT (s[1])) |
252b5132 RH |
8540 | { |
8541 | ++s; | |
8542 | regno = 0; | |
8543 | do | |
8544 | { | |
8545 | regno *= 10; | |
8546 | regno += *s - '0'; | |
8547 | ++s; | |
8548 | } | |
3882b010 | 8549 | while (ISDIGIT (*s)); |
252b5132 RH |
8550 | if (regno > 31) |
8551 | as_bad (_("Invalid register number (%d)"), regno); | |
8552 | } | |
af7ee8bf | 8553 | else if (*args == 'E' || *args == 'G' || *args == 'K') |
252b5132 RH |
8554 | goto notreg; |
8555 | else | |
8556 | { | |
76db943d TS |
8557 | if (s[1] == 'r' && s[2] == 'a') |
8558 | { | |
8559 | s += 3; | |
8560 | regno = RA; | |
8561 | } | |
8562 | else if (s[1] == 'f' && s[2] == 'p') | |
252b5132 RH |
8563 | { |
8564 | s += 3; | |
8565 | regno = FP; | |
8566 | } | |
8567 | else if (s[1] == 's' && s[2] == 'p') | |
8568 | { | |
8569 | s += 3; | |
8570 | regno = SP; | |
8571 | } | |
8572 | else if (s[1] == 'g' && s[2] == 'p') | |
8573 | { | |
8574 | s += 3; | |
8575 | regno = GP; | |
8576 | } | |
8577 | else if (s[1] == 'a' && s[2] == 't') | |
8578 | { | |
8579 | s += 3; | |
8580 | regno = AT; | |
8581 | } | |
8582 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '0') | |
8583 | { | |
8584 | s += 4; | |
8585 | regno = KT0; | |
8586 | } | |
8587 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '1') | |
8588 | { | |
8589 | s += 4; | |
8590 | regno = KT1; | |
8591 | } | |
85b51719 TS |
8592 | else if (s[1] == 'z' && s[2] == 'e' && s[3] == 'r' && s[4] == 'o') |
8593 | { | |
8594 | s += 5; | |
8595 | regno = ZERO; | |
8596 | } | |
252b5132 RH |
8597 | else if (itbl_have_entries) |
8598 | { | |
8599 | char *p, *n; | |
d7ba4a77 | 8600 | unsigned long r; |
252b5132 | 8601 | |
d7ba4a77 | 8602 | p = s + 1; /* advance past '$' */ |
252b5132 RH |
8603 | n = itbl_get_field (&p); /* n is name */ |
8604 | ||
d7ba4a77 ILT |
8605 | /* See if this is a register defined in an |
8606 | itbl entry. */ | |
8607 | if (itbl_get_reg_val (n, &r)) | |
252b5132 RH |
8608 | { |
8609 | /* Get_field advances to the start of | |
8610 | the next field, so we need to back | |
d7ba4a77 | 8611 | rack to the end of the last field. */ |
bdaaa2e1 | 8612 | if (p) |
252b5132 | 8613 | s = p - 1; |
bdaaa2e1 | 8614 | else |
d7ba4a77 | 8615 | s = strchr (s, '\0'); |
252b5132 RH |
8616 | regno = r; |
8617 | } | |
8618 | else | |
8619 | goto notreg; | |
beae10d5 | 8620 | } |
252b5132 RH |
8621 | else |
8622 | goto notreg; | |
8623 | } | |
8624 | if (regno == AT | |
8625 | && ! mips_opts.noat | |
8626 | && *args != 'E' | |
af7ee8bf CD |
8627 | && *args != 'G' |
8628 | && *args != 'K') | |
252b5132 RH |
8629 | as_warn (_("Used $at without \".set noat\"")); |
8630 | c = *args; | |
8631 | if (*s == ' ') | |
f9419b05 | 8632 | ++s; |
252b5132 RH |
8633 | if (args[1] != *s) |
8634 | { | |
8635 | if (c == 'r' || c == 'v' || c == 'w') | |
8636 | { | |
8637 | regno = lastregno; | |
8638 | s = s_reset; | |
f9419b05 | 8639 | ++args; |
252b5132 RH |
8640 | } |
8641 | } | |
8642 | /* 'z' only matches $0. */ | |
8643 | if (c == 'z' && regno != 0) | |
8644 | break; | |
8645 | ||
bdaaa2e1 KH |
8646 | /* Now that we have assembled one operand, we use the args string |
8647 | * to figure out where it goes in the instruction. */ | |
252b5132 RH |
8648 | switch (c) |
8649 | { | |
8650 | case 'r': | |
8651 | case 's': | |
8652 | case 'v': | |
8653 | case 'b': | |
38487616 | 8654 | ip->insn_opcode |= regno << OP_SH_RS; |
252b5132 RH |
8655 | break; |
8656 | case 'd': | |
8657 | case 'G': | |
af7ee8bf | 8658 | case 'K': |
38487616 | 8659 | ip->insn_opcode |= regno << OP_SH_RD; |
252b5132 | 8660 | break; |
4372b673 | 8661 | case 'U': |
38487616 TS |
8662 | ip->insn_opcode |= regno << OP_SH_RD; |
8663 | ip->insn_opcode |= regno << OP_SH_RT; | |
4372b673 | 8664 | break; |
252b5132 RH |
8665 | case 'w': |
8666 | case 't': | |
8667 | case 'E': | |
38487616 | 8668 | ip->insn_opcode |= regno << OP_SH_RT; |
252b5132 RH |
8669 | break; |
8670 | case 'x': | |
8671 | /* This case exists because on the r3000 trunc | |
8672 | expands into a macro which requires a gp | |
8673 | register. On the r6000 or r4000 it is | |
8674 | assembled into a single instruction which | |
8675 | ignores the register. Thus the insn version | |
8676 | is MIPS_ISA2 and uses 'x', and the macro | |
8677 | version is MIPS_ISA1 and uses 't'. */ | |
8678 | break; | |
8679 | case 'z': | |
8680 | /* This case is for the div instruction, which | |
8681 | acts differently if the destination argument | |
8682 | is $0. This only matches $0, and is checked | |
8683 | outside the switch. */ | |
8684 | break; | |
8685 | case 'D': | |
8686 | /* Itbl operand; not yet implemented. FIXME ?? */ | |
8687 | break; | |
8688 | /* What about all other operands like 'i', which | |
8689 | can be specified in the opcode table? */ | |
8690 | } | |
8691 | lastregno = regno; | |
8692 | continue; | |
8693 | } | |
8694 | notreg: | |
8695 | switch (*args++) | |
8696 | { | |
8697 | case 'r': | |
8698 | case 'v': | |
38487616 | 8699 | ip->insn_opcode |= lastregno << OP_SH_RS; |
252b5132 RH |
8700 | continue; |
8701 | case 'w': | |
38487616 | 8702 | ip->insn_opcode |= lastregno << OP_SH_RT; |
252b5132 RH |
8703 | continue; |
8704 | } | |
8705 | break; | |
8706 | ||
deec1734 CD |
8707 | case 'O': /* MDMX alignment immediate constant. */ |
8708 | my_getExpression (&imm_expr, s); | |
8709 | check_absolute_expr (ip, &imm_expr); | |
8710 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_ALN) | |
8711 | { | |
8712 | as_warn ("Improper align amount (%ld), using low bits", | |
8713 | (long) imm_expr.X_add_number); | |
8714 | imm_expr.X_add_number &= OP_MASK_ALN; | |
8715 | } | |
8716 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_ALN; | |
8717 | imm_expr.X_op = O_absent; | |
8718 | s = expr_end; | |
8719 | continue; | |
8720 | ||
8721 | case 'Q': /* MDMX vector, element sel, or const. */ | |
8722 | if (s[0] != '$') | |
8723 | { | |
8724 | /* MDMX Immediate. */ | |
8725 | my_getExpression (&imm_expr, s); | |
8726 | check_absolute_expr (ip, &imm_expr); | |
8727 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_FT) | |
8728 | { | |
8729 | as_warn (_("Invalid MDMX Immediate (%ld)"), | |
8730 | (long) imm_expr.X_add_number); | |
8731 | imm_expr.X_add_number &= OP_MASK_FT; | |
8732 | } | |
8733 | imm_expr.X_add_number &= OP_MASK_FT; | |
8734 | if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL)) | |
8735 | ip->insn_opcode |= MDMX_FMTSEL_IMM_QH << OP_SH_VSEL; | |
8736 | else | |
8737 | ip->insn_opcode |= MDMX_FMTSEL_IMM_OB << OP_SH_VSEL; | |
8738 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_FT; | |
8739 | imm_expr.X_op = O_absent; | |
8740 | s = expr_end; | |
8741 | continue; | |
8742 | } | |
8743 | /* Not MDMX Immediate. Fall through. */ | |
8744 | case 'X': /* MDMX destination register. */ | |
8745 | case 'Y': /* MDMX source register. */ | |
8746 | case 'Z': /* MDMX target register. */ | |
8747 | is_mdmx = 1; | |
252b5132 RH |
8748 | case 'D': /* floating point destination register */ |
8749 | case 'S': /* floating point source register */ | |
8750 | case 'T': /* floating point target register */ | |
8751 | case 'R': /* floating point source register */ | |
8752 | case 'V': | |
8753 | case 'W': | |
8754 | s_reset = s; | |
deec1734 CD |
8755 | /* Accept $fN for FP and MDMX register numbers, and in |
8756 | addition accept $vN for MDMX register numbers. */ | |
8757 | if ((s[0] == '$' && s[1] == 'f' && ISDIGIT (s[2])) | |
8758 | || (is_mdmx != 0 && s[0] == '$' && s[1] == 'v' | |
8759 | && ISDIGIT (s[2]))) | |
252b5132 RH |
8760 | { |
8761 | s += 2; | |
8762 | regno = 0; | |
8763 | do | |
8764 | { | |
8765 | regno *= 10; | |
8766 | regno += *s - '0'; | |
8767 | ++s; | |
8768 | } | |
3882b010 | 8769 | while (ISDIGIT (*s)); |
252b5132 RH |
8770 | |
8771 | if (regno > 31) | |
8772 | as_bad (_("Invalid float register number (%d)"), regno); | |
8773 | ||
8774 | if ((regno & 1) != 0 | |
ca4e0257 | 8775 | && HAVE_32BIT_FPRS |
252b5132 RH |
8776 | && ! (strcmp (str, "mtc1") == 0 |
8777 | || strcmp (str, "mfc1") == 0 | |
8778 | || strcmp (str, "lwc1") == 0 | |
8779 | || strcmp (str, "swc1") == 0 | |
8780 | || strcmp (str, "l.s") == 0 | |
8781 | || strcmp (str, "s.s") == 0)) | |
8782 | as_warn (_("Float register should be even, was %d"), | |
8783 | regno); | |
8784 | ||
8785 | c = *args; | |
8786 | if (*s == ' ') | |
f9419b05 | 8787 | ++s; |
252b5132 RH |
8788 | if (args[1] != *s) |
8789 | { | |
8790 | if (c == 'V' || c == 'W') | |
8791 | { | |
8792 | regno = lastregno; | |
8793 | s = s_reset; | |
f9419b05 | 8794 | ++args; |
252b5132 RH |
8795 | } |
8796 | } | |
8797 | switch (c) | |
8798 | { | |
8799 | case 'D': | |
deec1734 | 8800 | case 'X': |
38487616 | 8801 | ip->insn_opcode |= regno << OP_SH_FD; |
252b5132 RH |
8802 | break; |
8803 | case 'V': | |
8804 | case 'S': | |
deec1734 | 8805 | case 'Y': |
38487616 | 8806 | ip->insn_opcode |= regno << OP_SH_FS; |
252b5132 | 8807 | break; |
deec1734 CD |
8808 | case 'Q': |
8809 | /* This is like 'Z', but also needs to fix the MDMX | |
8810 | vector/scalar select bits. Note that the | |
8811 | scalar immediate case is handled above. */ | |
8812 | if (*s == '[') | |
8813 | { | |
8814 | int is_qh = (ip->insn_opcode & (1 << OP_SH_VSEL)); | |
8815 | int max_el = (is_qh ? 3 : 7); | |
8816 | s++; | |
8817 | my_getExpression(&imm_expr, s); | |
8818 | check_absolute_expr (ip, &imm_expr); | |
8819 | s = expr_end; | |
8820 | if (imm_expr.X_add_number > max_el) | |
8821 | as_bad(_("Bad element selector %ld"), | |
8822 | (long) imm_expr.X_add_number); | |
8823 | imm_expr.X_add_number &= max_el; | |
8824 | ip->insn_opcode |= (imm_expr.X_add_number | |
8825 | << (OP_SH_VSEL + | |
8826 | (is_qh ? 2 : 1))); | |
8827 | if (*s != ']') | |
8828 | as_warn(_("Expecting ']' found '%s'"), s); | |
8829 | else | |
8830 | s++; | |
8831 | } | |
8832 | else | |
8833 | { | |
8834 | if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL)) | |
8835 | ip->insn_opcode |= (MDMX_FMTSEL_VEC_QH | |
8836 | << OP_SH_VSEL); | |
8837 | else | |
8838 | ip->insn_opcode |= (MDMX_FMTSEL_VEC_OB << | |
8839 | OP_SH_VSEL); | |
8840 | } | |
8841 | /* Fall through */ | |
252b5132 RH |
8842 | case 'W': |
8843 | case 'T': | |
deec1734 | 8844 | case 'Z': |
38487616 | 8845 | ip->insn_opcode |= regno << OP_SH_FT; |
252b5132 RH |
8846 | break; |
8847 | case 'R': | |
38487616 | 8848 | ip->insn_opcode |= regno << OP_SH_FR; |
252b5132 RH |
8849 | break; |
8850 | } | |
8851 | lastregno = regno; | |
8852 | continue; | |
8853 | } | |
8854 | ||
252b5132 RH |
8855 | switch (*args++) |
8856 | { | |
8857 | case 'V': | |
38487616 | 8858 | ip->insn_opcode |= lastregno << OP_SH_FS; |
252b5132 RH |
8859 | continue; |
8860 | case 'W': | |
38487616 | 8861 | ip->insn_opcode |= lastregno << OP_SH_FT; |
252b5132 RH |
8862 | continue; |
8863 | } | |
8864 | break; | |
8865 | ||
8866 | case 'I': | |
8867 | my_getExpression (&imm_expr, s); | |
8868 | if (imm_expr.X_op != O_big | |
8869 | && imm_expr.X_op != O_constant) | |
8870 | insn_error = _("absolute expression required"); | |
8871 | s = expr_end; | |
8872 | continue; | |
8873 | ||
8874 | case 'A': | |
8875 | my_getExpression (&offset_expr, s); | |
f6688943 | 8876 | *imm_reloc = BFD_RELOC_32; |
252b5132 RH |
8877 | s = expr_end; |
8878 | continue; | |
8879 | ||
8880 | case 'F': | |
8881 | case 'L': | |
8882 | case 'f': | |
8883 | case 'l': | |
8884 | { | |
8885 | int f64; | |
ca4e0257 | 8886 | int using_gprs; |
252b5132 RH |
8887 | char *save_in; |
8888 | char *err; | |
8889 | unsigned char temp[8]; | |
8890 | int len; | |
8891 | unsigned int length; | |
8892 | segT seg; | |
8893 | subsegT subseg; | |
8894 | char *p; | |
8895 | ||
8896 | /* These only appear as the last operand in an | |
8897 | instruction, and every instruction that accepts | |
8898 | them in any variant accepts them in all variants. | |
8899 | This means we don't have to worry about backing out | |
8900 | any changes if the instruction does not match. | |
8901 | ||
8902 | The difference between them is the size of the | |
8903 | floating point constant and where it goes. For 'F' | |
8904 | and 'L' the constant is 64 bits; for 'f' and 'l' it | |
8905 | is 32 bits. Where the constant is placed is based | |
8906 | on how the MIPS assembler does things: | |
8907 | F -- .rdata | |
8908 | L -- .lit8 | |
8909 | f -- immediate value | |
8910 | l -- .lit4 | |
8911 | ||
8912 | The .lit4 and .lit8 sections are only used if | |
8913 | permitted by the -G argument. | |
8914 | ||
8915 | When generating embedded PIC code, we use the | |
8916 | .lit8 section but not the .lit4 section (we can do | |
8917 | .lit4 inline easily; we need to put .lit8 | |
8918 | somewhere in the data segment, and using .lit8 | |
8919 | permits the linker to eventually combine identical | |
ca4e0257 RS |
8920 | .lit8 entries). |
8921 | ||
8922 | The code below needs to know whether the target register | |
8923 | is 32 or 64 bits wide. It relies on the fact 'f' and | |
8924 | 'F' are used with GPR-based instructions and 'l' and | |
8925 | 'L' are used with FPR-based instructions. */ | |
252b5132 RH |
8926 | |
8927 | f64 = *args == 'F' || *args == 'L'; | |
ca4e0257 | 8928 | using_gprs = *args == 'F' || *args == 'f'; |
252b5132 RH |
8929 | |
8930 | save_in = input_line_pointer; | |
8931 | input_line_pointer = s; | |
8932 | err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len); | |
8933 | length = len; | |
8934 | s = input_line_pointer; | |
8935 | input_line_pointer = save_in; | |
8936 | if (err != NULL && *err != '\0') | |
8937 | { | |
8938 | as_bad (_("Bad floating point constant: %s"), err); | |
8939 | memset (temp, '\0', sizeof temp); | |
8940 | length = f64 ? 8 : 4; | |
8941 | } | |
8942 | ||
156c2f8b | 8943 | assert (length == (unsigned) (f64 ? 8 : 4)); |
252b5132 RH |
8944 | |
8945 | if (*args == 'f' | |
8946 | || (*args == 'l' | |
8947 | && (! USE_GLOBAL_POINTER_OPT | |
8948 | || mips_pic == EMBEDDED_PIC | |
8949 | || g_switch_value < 4 | |
8950 | || (temp[0] == 0 && temp[1] == 0) | |
8951 | || (temp[2] == 0 && temp[3] == 0)))) | |
8952 | { | |
8953 | imm_expr.X_op = O_constant; | |
8954 | if (! target_big_endian) | |
8955 | imm_expr.X_add_number = bfd_getl32 (temp); | |
8956 | else | |
8957 | imm_expr.X_add_number = bfd_getb32 (temp); | |
8958 | } | |
8959 | else if (length > 4 | |
119d663a | 8960 | && ! mips_disable_float_construction |
ca4e0257 RS |
8961 | /* Constants can only be constructed in GPRs and |
8962 | copied to FPRs if the GPRs are at least as wide | |
8963 | as the FPRs. Force the constant into memory if | |
8964 | we are using 64-bit FPRs but the GPRs are only | |
8965 | 32 bits wide. */ | |
8966 | && (using_gprs | |
8967 | || ! (HAVE_64BIT_FPRS && HAVE_32BIT_GPRS)) | |
252b5132 RH |
8968 | && ((temp[0] == 0 && temp[1] == 0) |
8969 | || (temp[2] == 0 && temp[3] == 0)) | |
8970 | && ((temp[4] == 0 && temp[5] == 0) | |
8971 | || (temp[6] == 0 && temp[7] == 0))) | |
8972 | { | |
ca4e0257 RS |
8973 | /* The value is simple enough to load with a couple of |
8974 | instructions. If using 32-bit registers, set | |
8975 | imm_expr to the high order 32 bits and offset_expr to | |
8976 | the low order 32 bits. Otherwise, set imm_expr to | |
8977 | the entire 64 bit constant. */ | |
8978 | if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS) | |
252b5132 RH |
8979 | { |
8980 | imm_expr.X_op = O_constant; | |
8981 | offset_expr.X_op = O_constant; | |
8982 | if (! target_big_endian) | |
8983 | { | |
8984 | imm_expr.X_add_number = bfd_getl32 (temp + 4); | |
8985 | offset_expr.X_add_number = bfd_getl32 (temp); | |
8986 | } | |
8987 | else | |
8988 | { | |
8989 | imm_expr.X_add_number = bfd_getb32 (temp); | |
8990 | offset_expr.X_add_number = bfd_getb32 (temp + 4); | |
8991 | } | |
8992 | if (offset_expr.X_add_number == 0) | |
8993 | offset_expr.X_op = O_absent; | |
8994 | } | |
8995 | else if (sizeof (imm_expr.X_add_number) > 4) | |
8996 | { | |
8997 | imm_expr.X_op = O_constant; | |
8998 | if (! target_big_endian) | |
8999 | imm_expr.X_add_number = bfd_getl64 (temp); | |
9000 | else | |
9001 | imm_expr.X_add_number = bfd_getb64 (temp); | |
9002 | } | |
9003 | else | |
9004 | { | |
9005 | imm_expr.X_op = O_big; | |
9006 | imm_expr.X_add_number = 4; | |
9007 | if (! target_big_endian) | |
9008 | { | |
9009 | generic_bignum[0] = bfd_getl16 (temp); | |
9010 | generic_bignum[1] = bfd_getl16 (temp + 2); | |
9011 | generic_bignum[2] = bfd_getl16 (temp + 4); | |
9012 | generic_bignum[3] = bfd_getl16 (temp + 6); | |
9013 | } | |
9014 | else | |
9015 | { | |
9016 | generic_bignum[0] = bfd_getb16 (temp + 6); | |
9017 | generic_bignum[1] = bfd_getb16 (temp + 4); | |
9018 | generic_bignum[2] = bfd_getb16 (temp + 2); | |
9019 | generic_bignum[3] = bfd_getb16 (temp); | |
9020 | } | |
9021 | } | |
9022 | } | |
9023 | else | |
9024 | { | |
9025 | const char *newname; | |
9026 | segT new_seg; | |
9027 | ||
9028 | /* Switch to the right section. */ | |
9029 | seg = now_seg; | |
9030 | subseg = now_subseg; | |
9031 | switch (*args) | |
9032 | { | |
9033 | default: /* unused default case avoids warnings. */ | |
9034 | case 'L': | |
9035 | newname = RDATA_SECTION_NAME; | |
bb2d6cd7 GK |
9036 | if ((USE_GLOBAL_POINTER_OPT && g_switch_value >= 8) |
9037 | || mips_pic == EMBEDDED_PIC) | |
252b5132 RH |
9038 | newname = ".lit8"; |
9039 | break; | |
9040 | case 'F': | |
bb2d6cd7 GK |
9041 | if (mips_pic == EMBEDDED_PIC) |
9042 | newname = ".lit8"; | |
9043 | else | |
9044 | newname = RDATA_SECTION_NAME; | |
252b5132 RH |
9045 | break; |
9046 | case 'l': | |
9047 | assert (!USE_GLOBAL_POINTER_OPT | |
9048 | || g_switch_value >= 4); | |
9049 | newname = ".lit4"; | |
9050 | break; | |
9051 | } | |
9052 | new_seg = subseg_new (newname, (subsegT) 0); | |
9053 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
9054 | bfd_set_section_flags (stdoutput, new_seg, | |
9055 | (SEC_ALLOC | |
9056 | | SEC_LOAD | |
9057 | | SEC_READONLY | |
9058 | | SEC_DATA)); | |
9059 | frag_align (*args == 'l' ? 2 : 3, 0, 0); | |
9060 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour | |
9061 | && strcmp (TARGET_OS, "elf") != 0) | |
9062 | record_alignment (new_seg, 4); | |
9063 | else | |
9064 | record_alignment (new_seg, *args == 'l' ? 2 : 3); | |
9065 | if (seg == now_seg) | |
9066 | as_bad (_("Can't use floating point insn in this section")); | |
9067 | ||
9068 | /* Set the argument to the current address in the | |
9069 | section. */ | |
9070 | offset_expr.X_op = O_symbol; | |
9071 | offset_expr.X_add_symbol = | |
9072 | symbol_new ("L0\001", now_seg, | |
9073 | (valueT) frag_now_fix (), frag_now); | |
9074 | offset_expr.X_add_number = 0; | |
9075 | ||
9076 | /* Put the floating point number into the section. */ | |
9077 | p = frag_more ((int) length); | |
9078 | memcpy (p, temp, length); | |
9079 | ||
9080 | /* Switch back to the original section. */ | |
9081 | subseg_set (seg, subseg); | |
9082 | } | |
9083 | } | |
9084 | continue; | |
9085 | ||
9086 | case 'i': /* 16 bit unsigned immediate */ | |
9087 | case 'j': /* 16 bit signed immediate */ | |
f6688943 | 9088 | *imm_reloc = BFD_RELOC_LO16; |
5e0116d5 | 9089 | if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0) |
252b5132 RH |
9090 | { |
9091 | int more; | |
5e0116d5 RS |
9092 | offsetT minval, maxval; |
9093 | ||
9094 | more = (insn + 1 < &mips_opcodes[NUMOPCODES] | |
9095 | && strcmp (insn->name, insn[1].name) == 0); | |
9096 | ||
9097 | /* If the expression was written as an unsigned number, | |
9098 | only treat it as signed if there are no more | |
9099 | alternatives. */ | |
9100 | if (more | |
9101 | && *args == 'j' | |
9102 | && sizeof (imm_expr.X_add_number) <= 4 | |
9103 | && imm_expr.X_op == O_constant | |
9104 | && imm_expr.X_add_number < 0 | |
9105 | && imm_expr.X_unsigned | |
9106 | && HAVE_64BIT_GPRS) | |
9107 | break; | |
9108 | ||
9109 | /* For compatibility with older assemblers, we accept | |
9110 | 0x8000-0xffff as signed 16-bit numbers when only | |
9111 | signed numbers are allowed. */ | |
9112 | if (*args == 'i') | |
9113 | minval = 0, maxval = 0xffff; | |
9114 | else if (more) | |
9115 | minval = -0x8000, maxval = 0x7fff; | |
252b5132 | 9116 | else |
5e0116d5 RS |
9117 | minval = -0x8000, maxval = 0xffff; |
9118 | ||
9119 | if (imm_expr.X_op != O_constant | |
9120 | || imm_expr.X_add_number < minval | |
9121 | || imm_expr.X_add_number > maxval) | |
252b5132 RH |
9122 | { |
9123 | if (more) | |
9124 | break; | |
2ae7e77b AH |
9125 | if (imm_expr.X_op == O_constant |
9126 | || imm_expr.X_op == O_big) | |
5e0116d5 | 9127 | as_bad (_("expression out of range")); |
252b5132 RH |
9128 | } |
9129 | } | |
9130 | s = expr_end; | |
9131 | continue; | |
9132 | ||
9133 | case 'o': /* 16 bit offset */ | |
5e0116d5 RS |
9134 | /* Check whether there is only a single bracketed expression |
9135 | left. If so, it must be the base register and the | |
9136 | constant must be zero. */ | |
9137 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
9138 | { | |
9139 | offset_expr.X_op = O_constant; | |
9140 | offset_expr.X_add_number = 0; | |
9141 | continue; | |
9142 | } | |
252b5132 RH |
9143 | |
9144 | /* If this value won't fit into a 16 bit offset, then go | |
9145 | find a macro that will generate the 32 bit offset | |
afdbd6d0 | 9146 | code pattern. */ |
5e0116d5 | 9147 | if (my_getSmallExpression (&offset_expr, offset_reloc, s) == 0 |
252b5132 RH |
9148 | && (offset_expr.X_op != O_constant |
9149 | || offset_expr.X_add_number >= 0x8000 | |
afdbd6d0 | 9150 | || offset_expr.X_add_number < -0x8000)) |
252b5132 RH |
9151 | break; |
9152 | ||
252b5132 RH |
9153 | s = expr_end; |
9154 | continue; | |
9155 | ||
9156 | case 'p': /* pc relative offset */ | |
0b25d3e6 | 9157 | *offset_reloc = BFD_RELOC_16_PCREL_S2; |
252b5132 RH |
9158 | my_getExpression (&offset_expr, s); |
9159 | s = expr_end; | |
9160 | continue; | |
9161 | ||
9162 | case 'u': /* upper 16 bits */ | |
5e0116d5 RS |
9163 | if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0 |
9164 | && imm_expr.X_op == O_constant | |
9165 | && (imm_expr.X_add_number < 0 | |
9166 | || imm_expr.X_add_number >= 0x10000)) | |
252b5132 RH |
9167 | as_bad (_("lui expression not in range 0..65535")); |
9168 | s = expr_end; | |
9169 | continue; | |
9170 | ||
9171 | case 'a': /* 26 bit address */ | |
9172 | my_getExpression (&offset_expr, s); | |
9173 | s = expr_end; | |
f6688943 | 9174 | *offset_reloc = BFD_RELOC_MIPS_JMP; |
252b5132 RH |
9175 | continue; |
9176 | ||
9177 | case 'N': /* 3 bit branch condition code */ | |
9178 | case 'M': /* 3 bit compare condition code */ | |
9179 | if (strncmp (s, "$fcc", 4) != 0) | |
9180 | break; | |
9181 | s += 4; | |
9182 | regno = 0; | |
9183 | do | |
9184 | { | |
9185 | regno *= 10; | |
9186 | regno += *s - '0'; | |
9187 | ++s; | |
9188 | } | |
3882b010 | 9189 | while (ISDIGIT (*s)); |
252b5132 RH |
9190 | if (regno > 7) |
9191 | as_bad (_("invalid condition code register $fcc%d"), regno); | |
9192 | if (*args == 'N') | |
9193 | ip->insn_opcode |= regno << OP_SH_BCC; | |
9194 | else | |
9195 | ip->insn_opcode |= regno << OP_SH_CCC; | |
beae10d5 | 9196 | continue; |
252b5132 | 9197 | |
156c2f8b NC |
9198 | case 'H': |
9199 | if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X')) | |
9200 | s += 2; | |
3882b010 | 9201 | if (ISDIGIT (*s)) |
156c2f8b NC |
9202 | { |
9203 | c = 0; | |
9204 | do | |
9205 | { | |
9206 | c *= 10; | |
9207 | c += *s - '0'; | |
9208 | ++s; | |
9209 | } | |
3882b010 | 9210 | while (ISDIGIT (*s)); |
156c2f8b NC |
9211 | } |
9212 | else | |
9213 | c = 8; /* Invalid sel value. */ | |
9214 | ||
9215 | if (c > 7) | |
9216 | as_bad (_("invalid coprocessor sub-selection value (0-7)")); | |
9217 | ip->insn_opcode |= c; | |
9218 | continue; | |
9219 | ||
60b63b72 RS |
9220 | case 'e': |
9221 | /* Must be at least one digit. */ | |
9222 | my_getExpression (&imm_expr, s); | |
9223 | check_absolute_expr (ip, &imm_expr); | |
9224 | ||
9225 | if ((unsigned long) imm_expr.X_add_number | |
9226 | > (unsigned long) OP_MASK_VECBYTE) | |
9227 | { | |
9228 | as_bad (_("bad byte vector index (%ld)"), | |
9229 | (long) imm_expr.X_add_number); | |
9230 | imm_expr.X_add_number = 0; | |
9231 | } | |
9232 | ||
9233 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_VECBYTE; | |
9234 | imm_expr.X_op = O_absent; | |
9235 | s = expr_end; | |
9236 | continue; | |
9237 | ||
9238 | case '%': | |
9239 | my_getExpression (&imm_expr, s); | |
9240 | check_absolute_expr (ip, &imm_expr); | |
9241 | ||
9242 | if ((unsigned long) imm_expr.X_add_number | |
9243 | > (unsigned long) OP_MASK_VECALIGN) | |
9244 | { | |
9245 | as_bad (_("bad byte vector index (%ld)"), | |
9246 | (long) imm_expr.X_add_number); | |
9247 | imm_expr.X_add_number = 0; | |
9248 | } | |
9249 | ||
9250 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_VECALIGN; | |
9251 | imm_expr.X_op = O_absent; | |
9252 | s = expr_end; | |
9253 | continue; | |
9254 | ||
252b5132 RH |
9255 | default: |
9256 | as_bad (_("bad char = '%c'\n"), *args); | |
9257 | internalError (); | |
9258 | } | |
9259 | break; | |
9260 | } | |
9261 | /* Args don't match. */ | |
9262 | if (insn + 1 < &mips_opcodes[NUMOPCODES] && | |
9263 | !strcmp (insn->name, insn[1].name)) | |
9264 | { | |
9265 | ++insn; | |
9266 | s = argsStart; | |
268f6bed | 9267 | insn_error = _("illegal operands"); |
252b5132 RH |
9268 | continue; |
9269 | } | |
268f6bed L |
9270 | if (save_c) |
9271 | *(--s) = save_c; | |
252b5132 RH |
9272 | insn_error = _("illegal operands"); |
9273 | return; | |
9274 | } | |
9275 | } | |
9276 | ||
9277 | /* This routine assembles an instruction into its binary format when | |
9278 | assembling for the mips16. As a side effect, it sets one of the | |
9279 | global variables imm_reloc or offset_reloc to the type of | |
9280 | relocation to do if one of the operands is an address expression. | |
9281 | It also sets mips16_small and mips16_ext if the user explicitly | |
9282 | requested a small or extended instruction. */ | |
9283 | ||
9284 | static void | |
9285 | mips16_ip (str, ip) | |
9286 | char *str; | |
9287 | struct mips_cl_insn *ip; | |
9288 | { | |
9289 | char *s; | |
9290 | const char *args; | |
9291 | struct mips_opcode *insn; | |
9292 | char *argsstart; | |
9293 | unsigned int regno; | |
9294 | unsigned int lastregno = 0; | |
9295 | char *s_reset; | |
9296 | ||
9297 | insn_error = NULL; | |
9298 | ||
b34976b6 AM |
9299 | mips16_small = FALSE; |
9300 | mips16_ext = FALSE; | |
252b5132 | 9301 | |
3882b010 | 9302 | for (s = str; ISLOWER (*s); ++s) |
252b5132 RH |
9303 | ; |
9304 | switch (*s) | |
9305 | { | |
9306 | case '\0': | |
9307 | break; | |
9308 | ||
9309 | case ' ': | |
9310 | *s++ = '\0'; | |
9311 | break; | |
9312 | ||
9313 | case '.': | |
9314 | if (s[1] == 't' && s[2] == ' ') | |
9315 | { | |
9316 | *s = '\0'; | |
b34976b6 | 9317 | mips16_small = TRUE; |
252b5132 RH |
9318 | s += 3; |
9319 | break; | |
9320 | } | |
9321 | else if (s[1] == 'e' && s[2] == ' ') | |
9322 | { | |
9323 | *s = '\0'; | |
b34976b6 | 9324 | mips16_ext = TRUE; |
252b5132 RH |
9325 | s += 3; |
9326 | break; | |
9327 | } | |
9328 | /* Fall through. */ | |
9329 | default: | |
9330 | insn_error = _("unknown opcode"); | |
9331 | return; | |
9332 | } | |
9333 | ||
9334 | if (mips_opts.noautoextend && ! mips16_ext) | |
b34976b6 | 9335 | mips16_small = TRUE; |
252b5132 RH |
9336 | |
9337 | if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL) | |
9338 | { | |
9339 | insn_error = _("unrecognized opcode"); | |
9340 | return; | |
9341 | } | |
9342 | ||
9343 | argsstart = s; | |
9344 | for (;;) | |
9345 | { | |
9346 | assert (strcmp (insn->name, str) == 0); | |
9347 | ||
9348 | ip->insn_mo = insn; | |
9349 | ip->insn_opcode = insn->match; | |
b34976b6 | 9350 | ip->use_extend = FALSE; |
252b5132 | 9351 | imm_expr.X_op = O_absent; |
f6688943 TS |
9352 | imm_reloc[0] = BFD_RELOC_UNUSED; |
9353 | imm_reloc[1] = BFD_RELOC_UNUSED; | |
9354 | imm_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 | 9355 | offset_expr.X_op = O_absent; |
f6688943 TS |
9356 | offset_reloc[0] = BFD_RELOC_UNUSED; |
9357 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
9358 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
9359 | for (args = insn->args; 1; ++args) |
9360 | { | |
9361 | int c; | |
9362 | ||
9363 | if (*s == ' ') | |
9364 | ++s; | |
9365 | ||
9366 | /* In this switch statement we call break if we did not find | |
9367 | a match, continue if we did find a match, or return if we | |
9368 | are done. */ | |
9369 | ||
9370 | c = *args; | |
9371 | switch (c) | |
9372 | { | |
9373 | case '\0': | |
9374 | if (*s == '\0') | |
9375 | { | |
9376 | /* Stuff the immediate value in now, if we can. */ | |
9377 | if (imm_expr.X_op == O_constant | |
f6688943 | 9378 | && *imm_reloc > BFD_RELOC_UNUSED |
252b5132 RH |
9379 | && insn->pinfo != INSN_MACRO) |
9380 | { | |
c4e7957c | 9381 | mips16_immed (NULL, 0, *imm_reloc - BFD_RELOC_UNUSED, |
b34976b6 | 9382 | imm_expr.X_add_number, TRUE, mips16_small, |
252b5132 RH |
9383 | mips16_ext, &ip->insn_opcode, |
9384 | &ip->use_extend, &ip->extend); | |
9385 | imm_expr.X_op = O_absent; | |
f6688943 | 9386 | *imm_reloc = BFD_RELOC_UNUSED; |
252b5132 RH |
9387 | } |
9388 | ||
9389 | return; | |
9390 | } | |
9391 | break; | |
9392 | ||
9393 | case ',': | |
9394 | if (*s++ == c) | |
9395 | continue; | |
9396 | s--; | |
9397 | switch (*++args) | |
9398 | { | |
9399 | case 'v': | |
9400 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RX; | |
9401 | continue; | |
9402 | case 'w': | |
9403 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RY; | |
9404 | continue; | |
9405 | } | |
9406 | break; | |
9407 | ||
9408 | case '(': | |
9409 | case ')': | |
9410 | if (*s++ == c) | |
9411 | continue; | |
9412 | break; | |
9413 | ||
9414 | case 'v': | |
9415 | case 'w': | |
9416 | if (s[0] != '$') | |
9417 | { | |
9418 | if (c == 'v') | |
9419 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RX; | |
9420 | else | |
9421 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RY; | |
9422 | ++args; | |
9423 | continue; | |
9424 | } | |
9425 | /* Fall through. */ | |
9426 | case 'x': | |
9427 | case 'y': | |
9428 | case 'z': | |
9429 | case 'Z': | |
9430 | case '0': | |
9431 | case 'S': | |
9432 | case 'R': | |
9433 | case 'X': | |
9434 | case 'Y': | |
9435 | if (s[0] != '$') | |
9436 | break; | |
9437 | s_reset = s; | |
3882b010 | 9438 | if (ISDIGIT (s[1])) |
252b5132 RH |
9439 | { |
9440 | ++s; | |
9441 | regno = 0; | |
9442 | do | |
9443 | { | |
9444 | regno *= 10; | |
9445 | regno += *s - '0'; | |
9446 | ++s; | |
9447 | } | |
3882b010 | 9448 | while (ISDIGIT (*s)); |
252b5132 RH |
9449 | if (regno > 31) |
9450 | { | |
9451 | as_bad (_("invalid register number (%d)"), regno); | |
9452 | regno = 2; | |
9453 | } | |
9454 | } | |
9455 | else | |
9456 | { | |
76db943d TS |
9457 | if (s[1] == 'r' && s[2] == 'a') |
9458 | { | |
9459 | s += 3; | |
9460 | regno = RA; | |
9461 | } | |
9462 | else if (s[1] == 'f' && s[2] == 'p') | |
252b5132 RH |
9463 | { |
9464 | s += 3; | |
9465 | regno = FP; | |
9466 | } | |
9467 | else if (s[1] == 's' && s[2] == 'p') | |
9468 | { | |
9469 | s += 3; | |
9470 | regno = SP; | |
9471 | } | |
9472 | else if (s[1] == 'g' && s[2] == 'p') | |
9473 | { | |
9474 | s += 3; | |
9475 | regno = GP; | |
9476 | } | |
9477 | else if (s[1] == 'a' && s[2] == 't') | |
9478 | { | |
9479 | s += 3; | |
9480 | regno = AT; | |
9481 | } | |
9482 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '0') | |
9483 | { | |
9484 | s += 4; | |
9485 | regno = KT0; | |
9486 | } | |
9487 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '1') | |
9488 | { | |
9489 | s += 4; | |
9490 | regno = KT1; | |
9491 | } | |
85b51719 TS |
9492 | else if (s[1] == 'z' && s[2] == 'e' && s[3] == 'r' && s[4] == 'o') |
9493 | { | |
9494 | s += 5; | |
9495 | regno = ZERO; | |
9496 | } | |
252b5132 RH |
9497 | else |
9498 | break; | |
9499 | } | |
9500 | ||
9501 | if (*s == ' ') | |
9502 | ++s; | |
9503 | if (args[1] != *s) | |
9504 | { | |
9505 | if (c == 'v' || c == 'w') | |
9506 | { | |
9507 | regno = mips16_to_32_reg_map[lastregno]; | |
9508 | s = s_reset; | |
f9419b05 | 9509 | ++args; |
252b5132 RH |
9510 | } |
9511 | } | |
9512 | ||
9513 | switch (c) | |
9514 | { | |
9515 | case 'x': | |
9516 | case 'y': | |
9517 | case 'z': | |
9518 | case 'v': | |
9519 | case 'w': | |
9520 | case 'Z': | |
9521 | regno = mips32_to_16_reg_map[regno]; | |
9522 | break; | |
9523 | ||
9524 | case '0': | |
9525 | if (regno != 0) | |
9526 | regno = ILLEGAL_REG; | |
9527 | break; | |
9528 | ||
9529 | case 'S': | |
9530 | if (regno != SP) | |
9531 | regno = ILLEGAL_REG; | |
9532 | break; | |
9533 | ||
9534 | case 'R': | |
9535 | if (regno != RA) | |
9536 | regno = ILLEGAL_REG; | |
9537 | break; | |
9538 | ||
9539 | case 'X': | |
9540 | case 'Y': | |
9541 | if (regno == AT && ! mips_opts.noat) | |
9542 | as_warn (_("used $at without \".set noat\"")); | |
9543 | break; | |
9544 | ||
9545 | default: | |
9546 | internalError (); | |
9547 | } | |
9548 | ||
9549 | if (regno == ILLEGAL_REG) | |
9550 | break; | |
9551 | ||
9552 | switch (c) | |
9553 | { | |
9554 | case 'x': | |
9555 | case 'v': | |
9556 | ip->insn_opcode |= regno << MIPS16OP_SH_RX; | |
9557 | break; | |
9558 | case 'y': | |
9559 | case 'w': | |
9560 | ip->insn_opcode |= regno << MIPS16OP_SH_RY; | |
9561 | break; | |
9562 | case 'z': | |
9563 | ip->insn_opcode |= regno << MIPS16OP_SH_RZ; | |
9564 | break; | |
9565 | case 'Z': | |
9566 | ip->insn_opcode |= regno << MIPS16OP_SH_MOVE32Z; | |
9567 | case '0': | |
9568 | case 'S': | |
9569 | case 'R': | |
9570 | break; | |
9571 | case 'X': | |
9572 | ip->insn_opcode |= regno << MIPS16OP_SH_REGR32; | |
9573 | break; | |
9574 | case 'Y': | |
9575 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); | |
9576 | ip->insn_opcode |= regno << MIPS16OP_SH_REG32R; | |
9577 | break; | |
9578 | default: | |
9579 | internalError (); | |
9580 | } | |
9581 | ||
9582 | lastregno = regno; | |
9583 | continue; | |
9584 | ||
9585 | case 'P': | |
9586 | if (strncmp (s, "$pc", 3) == 0) | |
9587 | { | |
9588 | s += 3; | |
9589 | continue; | |
9590 | } | |
9591 | break; | |
9592 | ||
9593 | case '<': | |
9594 | case '>': | |
9595 | case '[': | |
9596 | case ']': | |
9597 | case '4': | |
9598 | case '5': | |
9599 | case 'H': | |
9600 | case 'W': | |
9601 | case 'D': | |
9602 | case 'j': | |
9603 | case '8': | |
9604 | case 'V': | |
9605 | case 'C': | |
9606 | case 'U': | |
9607 | case 'k': | |
9608 | case 'K': | |
9609 | if (s[0] == '%' | |
9610 | && strncmp (s + 1, "gprel(", sizeof "gprel(" - 1) == 0) | |
9611 | { | |
9612 | /* This is %gprel(SYMBOL). We need to read SYMBOL, | |
9613 | and generate the appropriate reloc. If the text | |
9614 | inside %gprel is not a symbol name with an | |
9615 | optional offset, then we generate a normal reloc | |
9616 | and will probably fail later. */ | |
9617 | my_getExpression (&imm_expr, s + sizeof "%gprel" - 1); | |
9618 | if (imm_expr.X_op == O_symbol) | |
9619 | { | |
b34976b6 | 9620 | mips16_ext = TRUE; |
f6688943 | 9621 | *imm_reloc = BFD_RELOC_MIPS16_GPREL; |
252b5132 | 9622 | s = expr_end; |
b34976b6 | 9623 | ip->use_extend = TRUE; |
252b5132 RH |
9624 | ip->extend = 0; |
9625 | continue; | |
9626 | } | |
9627 | } | |
9628 | else | |
9629 | { | |
9630 | /* Just pick up a normal expression. */ | |
9631 | my_getExpression (&imm_expr, s); | |
9632 | } | |
9633 | ||
9634 | if (imm_expr.X_op == O_register) | |
9635 | { | |
9636 | /* What we thought was an expression turned out to | |
9637 | be a register. */ | |
9638 | ||
9639 | if (s[0] == '(' && args[1] == '(') | |
9640 | { | |
9641 | /* It looks like the expression was omitted | |
9642 | before a register indirection, which means | |
9643 | that the expression is implicitly zero. We | |
9644 | still set up imm_expr, so that we handle | |
9645 | explicit extensions correctly. */ | |
9646 | imm_expr.X_op = O_constant; | |
9647 | imm_expr.X_add_number = 0; | |
f6688943 | 9648 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
9649 | continue; |
9650 | } | |
9651 | ||
9652 | break; | |
9653 | } | |
9654 | ||
9655 | /* We need to relax this instruction. */ | |
f6688943 | 9656 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
9657 | s = expr_end; |
9658 | continue; | |
9659 | ||
9660 | case 'p': | |
9661 | case 'q': | |
9662 | case 'A': | |
9663 | case 'B': | |
9664 | case 'E': | |
9665 | /* We use offset_reloc rather than imm_reloc for the PC | |
9666 | relative operands. This lets macros with both | |
9667 | immediate and address operands work correctly. */ | |
9668 | my_getExpression (&offset_expr, s); | |
9669 | ||
9670 | if (offset_expr.X_op == O_register) | |
9671 | break; | |
9672 | ||
9673 | /* We need to relax this instruction. */ | |
f6688943 | 9674 | *offset_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
9675 | s = expr_end; |
9676 | continue; | |
9677 | ||
9678 | case '6': /* break code */ | |
9679 | my_getExpression (&imm_expr, s); | |
9680 | check_absolute_expr (ip, &imm_expr); | |
9681 | if ((unsigned long) imm_expr.X_add_number > 63) | |
9682 | { | |
9683 | as_warn (_("Invalid value for `%s' (%lu)"), | |
9684 | ip->insn_mo->name, | |
9685 | (unsigned long) imm_expr.X_add_number); | |
9686 | imm_expr.X_add_number &= 0x3f; | |
9687 | } | |
9688 | ip->insn_opcode |= imm_expr.X_add_number << MIPS16OP_SH_IMM6; | |
9689 | imm_expr.X_op = O_absent; | |
9690 | s = expr_end; | |
9691 | continue; | |
9692 | ||
9693 | case 'a': /* 26 bit address */ | |
9694 | my_getExpression (&offset_expr, s); | |
9695 | s = expr_end; | |
f6688943 | 9696 | *offset_reloc = BFD_RELOC_MIPS16_JMP; |
252b5132 RH |
9697 | ip->insn_opcode <<= 16; |
9698 | continue; | |
9699 | ||
9700 | case 'l': /* register list for entry macro */ | |
9701 | case 'L': /* register list for exit macro */ | |
9702 | { | |
9703 | int mask; | |
9704 | ||
9705 | if (c == 'l') | |
9706 | mask = 0; | |
9707 | else | |
9708 | mask = 7 << 3; | |
9709 | while (*s != '\0') | |
9710 | { | |
9711 | int freg, reg1, reg2; | |
9712 | ||
9713 | while (*s == ' ' || *s == ',') | |
9714 | ++s; | |
9715 | if (*s != '$') | |
9716 | { | |
9717 | as_bad (_("can't parse register list")); | |
9718 | break; | |
9719 | } | |
9720 | ++s; | |
9721 | if (*s != 'f') | |
9722 | freg = 0; | |
9723 | else | |
9724 | { | |
9725 | freg = 1; | |
9726 | ++s; | |
9727 | } | |
9728 | reg1 = 0; | |
3882b010 | 9729 | while (ISDIGIT (*s)) |
252b5132 RH |
9730 | { |
9731 | reg1 *= 10; | |
9732 | reg1 += *s - '0'; | |
9733 | ++s; | |
9734 | } | |
9735 | if (*s == ' ') | |
9736 | ++s; | |
9737 | if (*s != '-') | |
9738 | reg2 = reg1; | |
9739 | else | |
9740 | { | |
9741 | ++s; | |
9742 | if (*s != '$') | |
9743 | break; | |
9744 | ++s; | |
9745 | if (freg) | |
9746 | { | |
9747 | if (*s == 'f') | |
9748 | ++s; | |
9749 | else | |
9750 | { | |
9751 | as_bad (_("invalid register list")); | |
9752 | break; | |
9753 | } | |
9754 | } | |
9755 | reg2 = 0; | |
3882b010 | 9756 | while (ISDIGIT (*s)) |
252b5132 RH |
9757 | { |
9758 | reg2 *= 10; | |
9759 | reg2 += *s - '0'; | |
9760 | ++s; | |
9761 | } | |
9762 | } | |
9763 | if (freg && reg1 == 0 && reg2 == 0 && c == 'L') | |
9764 | { | |
9765 | mask &= ~ (7 << 3); | |
9766 | mask |= 5 << 3; | |
9767 | } | |
9768 | else if (freg && reg1 == 0 && reg2 == 1 && c == 'L') | |
9769 | { | |
9770 | mask &= ~ (7 << 3); | |
9771 | mask |= 6 << 3; | |
9772 | } | |
9773 | else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L') | |
9774 | mask |= (reg2 - 3) << 3; | |
9775 | else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17) | |
9776 | mask |= (reg2 - 15) << 1; | |
f9419b05 | 9777 | else if (reg1 == RA && reg2 == RA) |
252b5132 RH |
9778 | mask |= 1; |
9779 | else | |
9780 | { | |
9781 | as_bad (_("invalid register list")); | |
9782 | break; | |
9783 | } | |
9784 | } | |
9785 | /* The mask is filled in in the opcode table for the | |
9786 | benefit of the disassembler. We remove it before | |
9787 | applying the actual mask. */ | |
9788 | ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6); | |
9789 | ip->insn_opcode |= mask << MIPS16OP_SH_IMM6; | |
9790 | } | |
9791 | continue; | |
9792 | ||
9793 | case 'e': /* extend code */ | |
9794 | my_getExpression (&imm_expr, s); | |
9795 | check_absolute_expr (ip, &imm_expr); | |
9796 | if ((unsigned long) imm_expr.X_add_number > 0x7ff) | |
9797 | { | |
9798 | as_warn (_("Invalid value for `%s' (%lu)"), | |
9799 | ip->insn_mo->name, | |
9800 | (unsigned long) imm_expr.X_add_number); | |
9801 | imm_expr.X_add_number &= 0x7ff; | |
9802 | } | |
9803 | ip->insn_opcode |= imm_expr.X_add_number; | |
9804 | imm_expr.X_op = O_absent; | |
9805 | s = expr_end; | |
9806 | continue; | |
9807 | ||
9808 | default: | |
9809 | internalError (); | |
9810 | } | |
9811 | break; | |
9812 | } | |
9813 | ||
9814 | /* Args don't match. */ | |
9815 | if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] && | |
9816 | strcmp (insn->name, insn[1].name) == 0) | |
9817 | { | |
9818 | ++insn; | |
9819 | s = argsstart; | |
9820 | continue; | |
9821 | } | |
9822 | ||
9823 | insn_error = _("illegal operands"); | |
9824 | ||
9825 | return; | |
9826 | } | |
9827 | } | |
9828 | ||
9829 | /* This structure holds information we know about a mips16 immediate | |
9830 | argument type. */ | |
9831 | ||
e972090a NC |
9832 | struct mips16_immed_operand |
9833 | { | |
252b5132 RH |
9834 | /* The type code used in the argument string in the opcode table. */ |
9835 | int type; | |
9836 | /* The number of bits in the short form of the opcode. */ | |
9837 | int nbits; | |
9838 | /* The number of bits in the extended form of the opcode. */ | |
9839 | int extbits; | |
9840 | /* The amount by which the short form is shifted when it is used; | |
9841 | for example, the sw instruction has a shift count of 2. */ | |
9842 | int shift; | |
9843 | /* The amount by which the short form is shifted when it is stored | |
9844 | into the instruction code. */ | |
9845 | int op_shift; | |
9846 | /* Non-zero if the short form is unsigned. */ | |
9847 | int unsp; | |
9848 | /* Non-zero if the extended form is unsigned. */ | |
9849 | int extu; | |
9850 | /* Non-zero if the value is PC relative. */ | |
9851 | int pcrel; | |
9852 | }; | |
9853 | ||
9854 | /* The mips16 immediate operand types. */ | |
9855 | ||
9856 | static const struct mips16_immed_operand mips16_immed_operands[] = | |
9857 | { | |
9858 | { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
9859 | { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
9860 | { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
9861 | { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
9862 | { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 }, | |
9863 | { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
9864 | { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
9865 | { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
9866 | { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
9867 | { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 }, | |
9868 | { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
9869 | { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
9870 | { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
9871 | { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 }, | |
9872 | { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
9873 | { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
9874 | { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
9875 | { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
9876 | { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 }, | |
9877 | { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 }, | |
9878 | { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 } | |
9879 | }; | |
9880 | ||
9881 | #define MIPS16_NUM_IMMED \ | |
9882 | (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0]) | |
9883 | ||
9884 | /* Handle a mips16 instruction with an immediate value. This or's the | |
9885 | small immediate value into *INSN. It sets *USE_EXTEND to indicate | |
9886 | whether an extended value is needed; if one is needed, it sets | |
9887 | *EXTEND to the value. The argument type is TYPE. The value is VAL. | |
9888 | If SMALL is true, an unextended opcode was explicitly requested. | |
9889 | If EXT is true, an extended opcode was explicitly requested. If | |
9890 | WARN is true, warn if EXT does not match reality. */ | |
9891 | ||
9892 | static void | |
9893 | mips16_immed (file, line, type, val, warn, small, ext, insn, use_extend, | |
9894 | extend) | |
9895 | char *file; | |
9896 | unsigned int line; | |
9897 | int type; | |
9898 | offsetT val; | |
b34976b6 AM |
9899 | bfd_boolean warn; |
9900 | bfd_boolean small; | |
9901 | bfd_boolean ext; | |
252b5132 | 9902 | unsigned long *insn; |
b34976b6 | 9903 | bfd_boolean *use_extend; |
252b5132 RH |
9904 | unsigned short *extend; |
9905 | { | |
9906 | register const struct mips16_immed_operand *op; | |
9907 | int mintiny, maxtiny; | |
b34976b6 | 9908 | bfd_boolean needext; |
252b5132 RH |
9909 | |
9910 | op = mips16_immed_operands; | |
9911 | while (op->type != type) | |
9912 | { | |
9913 | ++op; | |
9914 | assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); | |
9915 | } | |
9916 | ||
9917 | if (op->unsp) | |
9918 | { | |
9919 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
9920 | { | |
9921 | mintiny = 1; | |
9922 | maxtiny = 1 << op->nbits; | |
9923 | } | |
9924 | else | |
9925 | { | |
9926 | mintiny = 0; | |
9927 | maxtiny = (1 << op->nbits) - 1; | |
9928 | } | |
9929 | } | |
9930 | else | |
9931 | { | |
9932 | mintiny = - (1 << (op->nbits - 1)); | |
9933 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
9934 | } | |
9935 | ||
9936 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
9937 | if (type == 'p' || type == 'q') | |
9938 | val /= 2; | |
9939 | ||
9940 | if ((val & ((1 << op->shift) - 1)) != 0 | |
9941 | || val < (mintiny << op->shift) | |
9942 | || val > (maxtiny << op->shift)) | |
b34976b6 | 9943 | needext = TRUE; |
252b5132 | 9944 | else |
b34976b6 | 9945 | needext = FALSE; |
252b5132 RH |
9946 | |
9947 | if (warn && ext && ! needext) | |
beae10d5 KH |
9948 | as_warn_where (file, line, |
9949 | _("extended operand requested but not required")); | |
252b5132 RH |
9950 | if (small && needext) |
9951 | as_bad_where (file, line, _("invalid unextended operand value")); | |
9952 | ||
9953 | if (small || (! ext && ! needext)) | |
9954 | { | |
9955 | int insnval; | |
9956 | ||
b34976b6 | 9957 | *use_extend = FALSE; |
252b5132 RH |
9958 | insnval = ((val >> op->shift) & ((1 << op->nbits) - 1)); |
9959 | insnval <<= op->op_shift; | |
9960 | *insn |= insnval; | |
9961 | } | |
9962 | else | |
9963 | { | |
9964 | long minext, maxext; | |
9965 | int extval; | |
9966 | ||
9967 | if (op->extu) | |
9968 | { | |
9969 | minext = 0; | |
9970 | maxext = (1 << op->extbits) - 1; | |
9971 | } | |
9972 | else | |
9973 | { | |
9974 | minext = - (1 << (op->extbits - 1)); | |
9975 | maxext = (1 << (op->extbits - 1)) - 1; | |
9976 | } | |
9977 | if (val < minext || val > maxext) | |
9978 | as_bad_where (file, line, | |
9979 | _("operand value out of range for instruction")); | |
9980 | ||
b34976b6 | 9981 | *use_extend = TRUE; |
252b5132 RH |
9982 | if (op->extbits == 16) |
9983 | { | |
9984 | extval = ((val >> 11) & 0x1f) | (val & 0x7e0); | |
9985 | val &= 0x1f; | |
9986 | } | |
9987 | else if (op->extbits == 15) | |
9988 | { | |
9989 | extval = ((val >> 11) & 0xf) | (val & 0x7f0); | |
9990 | val &= 0xf; | |
9991 | } | |
9992 | else | |
9993 | { | |
9994 | extval = ((val & 0x1f) << 6) | (val & 0x20); | |
9995 | val = 0; | |
9996 | } | |
9997 | ||
9998 | *extend = (unsigned short) extval; | |
9999 | *insn |= val; | |
10000 | } | |
10001 | } | |
10002 | \f | |
5e0116d5 | 10003 | static const struct percent_op_match |
ad8d3bb3 | 10004 | { |
5e0116d5 RS |
10005 | const char *str; |
10006 | bfd_reloc_code_real_type reloc; | |
ad8d3bb3 TS |
10007 | } percent_op[] = |
10008 | { | |
5e0116d5 | 10009 | {"%lo", BFD_RELOC_LO16}, |
ad8d3bb3 | 10010 | #ifdef OBJ_ELF |
5e0116d5 RS |
10011 | {"%call_hi", BFD_RELOC_MIPS_CALL_HI16}, |
10012 | {"%call_lo", BFD_RELOC_MIPS_CALL_LO16}, | |
10013 | {"%call16", BFD_RELOC_MIPS_CALL16}, | |
10014 | {"%got_disp", BFD_RELOC_MIPS_GOT_DISP}, | |
10015 | {"%got_page", BFD_RELOC_MIPS_GOT_PAGE}, | |
10016 | {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST}, | |
10017 | {"%got_hi", BFD_RELOC_MIPS_GOT_HI16}, | |
10018 | {"%got_lo", BFD_RELOC_MIPS_GOT_LO16}, | |
10019 | {"%got", BFD_RELOC_MIPS_GOT16}, | |
10020 | {"%gp_rel", BFD_RELOC_GPREL16}, | |
10021 | {"%half", BFD_RELOC_16}, | |
10022 | {"%highest", BFD_RELOC_MIPS_HIGHEST}, | |
10023 | {"%higher", BFD_RELOC_MIPS_HIGHER}, | |
10024 | {"%neg", BFD_RELOC_MIPS_SUB}, | |
ad8d3bb3 | 10025 | #endif |
5e0116d5 | 10026 | {"%hi", BFD_RELOC_HI16_S} |
ad8d3bb3 TS |
10027 | }; |
10028 | ||
252b5132 | 10029 | |
5e0116d5 RS |
10030 | /* Return true if *STR points to a relocation operator. When returning true, |
10031 | move *STR over the operator and store its relocation code in *RELOC. | |
10032 | Leave both *STR and *RELOC alone when returning false. */ | |
10033 | ||
10034 | static bfd_boolean | |
10035 | parse_relocation (str, reloc) | |
ad8d3bb3 | 10036 | char **str; |
5e0116d5 | 10037 | bfd_reloc_code_real_type *reloc; |
252b5132 | 10038 | { |
5e0116d5 | 10039 | size_t i; |
76b3015f | 10040 | |
5e0116d5 RS |
10041 | for (i = 0; i < ARRAY_SIZE (percent_op); i++) |
10042 | if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0) | |
394f9b3a | 10043 | { |
5e0116d5 RS |
10044 | *str += strlen (percent_op[i].str); |
10045 | *reloc = percent_op[i].reloc; | |
394f9b3a | 10046 | |
5e0116d5 RS |
10047 | /* Check whether the output BFD supports this relocation. |
10048 | If not, issue an error and fall back on something safe. */ | |
10049 | if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc)) | |
394f9b3a | 10050 | { |
5e0116d5 RS |
10051 | as_bad ("relocation %s isn't supported by the current ABI", |
10052 | percent_op[i].str); | |
10053 | *reloc = BFD_RELOC_LO16; | |
394f9b3a | 10054 | } |
5e0116d5 | 10055 | return TRUE; |
394f9b3a | 10056 | } |
5e0116d5 | 10057 | return FALSE; |
394f9b3a | 10058 | } |
ad8d3bb3 | 10059 | |
ad8d3bb3 | 10060 | |
5e0116d5 RS |
10061 | /* Parse string STR as a 16-bit relocatable operand. Store the |
10062 | expression in *EP and the relocations in the array starting | |
10063 | at RELOC. Return the number of relocation operators used. | |
ad8d3bb3 | 10064 | |
5e0116d5 RS |
10065 | On exit, EXPR_END points to the first character after the expression. |
10066 | If no relocation operators are used, RELOC[0] is set to BFD_RELOC_LO16. */ | |
ad8d3bb3 | 10067 | |
5e0116d5 RS |
10068 | static size_t |
10069 | my_getSmallExpression (ep, reloc, str) | |
ad8d3bb3 | 10070 | expressionS *ep; |
5e0116d5 | 10071 | bfd_reloc_code_real_type *reloc; |
ad8d3bb3 TS |
10072 | char *str; |
10073 | { | |
5e0116d5 RS |
10074 | bfd_reloc_code_real_type reversed_reloc[3]; |
10075 | size_t reloc_index, i; | |
09b8f35a RS |
10076 | int crux_depth, str_depth; |
10077 | char *crux; | |
5e0116d5 RS |
10078 | |
10079 | /* Search for the start of the main expression, recoding relocations | |
09b8f35a RS |
10080 | in REVERSED_RELOC. End the loop with CRUX pointing to the start |
10081 | of the main expression and with CRUX_DEPTH containing the number | |
10082 | of open brackets at that point. */ | |
10083 | reloc_index = -1; | |
10084 | str_depth = 0; | |
10085 | do | |
fb1b3232 | 10086 | { |
09b8f35a RS |
10087 | reloc_index++; |
10088 | crux = str; | |
10089 | crux_depth = str_depth; | |
10090 | ||
10091 | /* Skip over whitespace and brackets, keeping count of the number | |
10092 | of brackets. */ | |
10093 | while (*str == ' ' || *str == '\t' || *str == '(') | |
10094 | if (*str++ == '(') | |
10095 | str_depth++; | |
5e0116d5 | 10096 | } |
09b8f35a RS |
10097 | while (*str == '%' |
10098 | && reloc_index < (HAVE_NEWABI ? 3 : 1) | |
10099 | && parse_relocation (&str, &reversed_reloc[reloc_index])); | |
ad8d3bb3 | 10100 | |
09b8f35a | 10101 | my_getExpression (ep, crux); |
5e0116d5 | 10102 | str = expr_end; |
394f9b3a | 10103 | |
5e0116d5 | 10104 | /* Match every open bracket. */ |
09b8f35a | 10105 | while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t')) |
5e0116d5 | 10106 | if (*str++ == ')') |
09b8f35a | 10107 | crux_depth--; |
394f9b3a | 10108 | |
09b8f35a | 10109 | if (crux_depth > 0) |
5e0116d5 | 10110 | as_bad ("unclosed '('"); |
394f9b3a | 10111 | |
5e0116d5 | 10112 | expr_end = str; |
252b5132 | 10113 | |
64bdfcaf RS |
10114 | if (reloc_index == 0) |
10115 | reloc[0] = BFD_RELOC_LO16; | |
10116 | else | |
10117 | { | |
10118 | prev_reloc_op_frag = frag_now; | |
10119 | for (i = 0; i < reloc_index; i++) | |
10120 | reloc[i] = reversed_reloc[reloc_index - 1 - i]; | |
10121 | } | |
fb1b3232 | 10122 | |
5e0116d5 | 10123 | return reloc_index; |
252b5132 RH |
10124 | } |
10125 | ||
10126 | static void | |
10127 | my_getExpression (ep, str) | |
10128 | expressionS *ep; | |
10129 | char *str; | |
10130 | { | |
10131 | char *save_in; | |
98aa84af | 10132 | valueT val; |
252b5132 RH |
10133 | |
10134 | save_in = input_line_pointer; | |
10135 | input_line_pointer = str; | |
10136 | expression (ep); | |
10137 | expr_end = input_line_pointer; | |
10138 | input_line_pointer = save_in; | |
10139 | ||
10140 | /* If we are in mips16 mode, and this is an expression based on `.', | |
10141 | then we bump the value of the symbol by 1 since that is how other | |
10142 | text symbols are handled. We don't bother to handle complex | |
10143 | expressions, just `.' plus or minus a constant. */ | |
10144 | if (mips_opts.mips16 | |
10145 | && ep->X_op == O_symbol | |
10146 | && strcmp (S_GET_NAME (ep->X_add_symbol), FAKE_LABEL_NAME) == 0 | |
10147 | && S_GET_SEGMENT (ep->X_add_symbol) == now_seg | |
49309057 ILT |
10148 | && symbol_get_frag (ep->X_add_symbol) == frag_now |
10149 | && symbol_constant_p (ep->X_add_symbol) | |
98aa84af AM |
10150 | && (val = S_GET_VALUE (ep->X_add_symbol)) == frag_now_fix ()) |
10151 | S_SET_VALUE (ep->X_add_symbol, val + 1); | |
252b5132 RH |
10152 | } |
10153 | ||
10154 | /* Turn a string in input_line_pointer into a floating point constant | |
bc0d738a NC |
10155 | of type TYPE, and store the appropriate bytes in *LITP. The number |
10156 | of LITTLENUMS emitted is stored in *SIZEP. An error message is | |
252b5132 RH |
10157 | returned, or NULL on OK. */ |
10158 | ||
10159 | char * | |
10160 | md_atof (type, litP, sizeP) | |
10161 | int type; | |
10162 | char *litP; | |
10163 | int *sizeP; | |
10164 | { | |
10165 | int prec; | |
10166 | LITTLENUM_TYPE words[4]; | |
10167 | char *t; | |
10168 | int i; | |
10169 | ||
10170 | switch (type) | |
10171 | { | |
10172 | case 'f': | |
10173 | prec = 2; | |
10174 | break; | |
10175 | ||
10176 | case 'd': | |
10177 | prec = 4; | |
10178 | break; | |
10179 | ||
10180 | default: | |
10181 | *sizeP = 0; | |
10182 | return _("bad call to md_atof"); | |
10183 | } | |
10184 | ||
10185 | t = atof_ieee (input_line_pointer, type, words); | |
10186 | if (t) | |
10187 | input_line_pointer = t; | |
10188 | ||
10189 | *sizeP = prec * 2; | |
10190 | ||
10191 | if (! target_big_endian) | |
10192 | { | |
10193 | for (i = prec - 1; i >= 0; i--) | |
10194 | { | |
10195 | md_number_to_chars (litP, (valueT) words[i], 2); | |
10196 | litP += 2; | |
10197 | } | |
10198 | } | |
10199 | else | |
10200 | { | |
10201 | for (i = 0; i < prec; i++) | |
10202 | { | |
10203 | md_number_to_chars (litP, (valueT) words[i], 2); | |
10204 | litP += 2; | |
10205 | } | |
10206 | } | |
bdaaa2e1 | 10207 | |
252b5132 RH |
10208 | return NULL; |
10209 | } | |
10210 | ||
10211 | void | |
10212 | md_number_to_chars (buf, val, n) | |
10213 | char *buf; | |
10214 | valueT val; | |
10215 | int n; | |
10216 | { | |
10217 | if (target_big_endian) | |
10218 | number_to_chars_bigendian (buf, val, n); | |
10219 | else | |
10220 | number_to_chars_littleendian (buf, val, n); | |
10221 | } | |
10222 | \f | |
ae948b86 | 10223 | #ifdef OBJ_ELF |
e013f690 TS |
10224 | static int support_64bit_objects(void) |
10225 | { | |
10226 | const char **list, **l; | |
aa3d8fdf | 10227 | int yes; |
e013f690 TS |
10228 | |
10229 | list = bfd_target_list (); | |
10230 | for (l = list; *l != NULL; l++) | |
10231 | #ifdef TE_TMIPS | |
10232 | /* This is traditional mips */ | |
10233 | if (strcmp (*l, "elf64-tradbigmips") == 0 | |
10234 | || strcmp (*l, "elf64-tradlittlemips") == 0) | |
10235 | #else | |
10236 | if (strcmp (*l, "elf64-bigmips") == 0 | |
10237 | || strcmp (*l, "elf64-littlemips") == 0) | |
10238 | #endif | |
10239 | break; | |
aa3d8fdf | 10240 | yes = (*l != NULL); |
e013f690 | 10241 | free (list); |
aa3d8fdf | 10242 | return yes; |
e013f690 | 10243 | } |
ae948b86 | 10244 | #endif /* OBJ_ELF */ |
e013f690 | 10245 | |
5a38dc70 | 10246 | const char *md_shortopts = "nO::g::G:"; |
252b5132 | 10247 | |
e972090a NC |
10248 | struct option md_longopts[] = |
10249 | { | |
252b5132 RH |
10250 | #define OPTION_MIPS1 (OPTION_MD_BASE + 1) |
10251 | {"mips0", no_argument, NULL, OPTION_MIPS1}, | |
10252 | {"mips1", no_argument, NULL, OPTION_MIPS1}, | |
10253 | #define OPTION_MIPS2 (OPTION_MD_BASE + 2) | |
10254 | {"mips2", no_argument, NULL, OPTION_MIPS2}, | |
10255 | #define OPTION_MIPS3 (OPTION_MD_BASE + 3) | |
10256 | {"mips3", no_argument, NULL, OPTION_MIPS3}, | |
10257 | #define OPTION_MIPS4 (OPTION_MD_BASE + 4) | |
10258 | {"mips4", no_argument, NULL, OPTION_MIPS4}, | |
ae948b86 TS |
10259 | #define OPTION_MIPS5 (OPTION_MD_BASE + 5) |
10260 | {"mips5", no_argument, NULL, OPTION_MIPS5}, | |
10261 | #define OPTION_MIPS32 (OPTION_MD_BASE + 6) | |
10262 | {"mips32", no_argument, NULL, OPTION_MIPS32}, | |
10263 | #define OPTION_MIPS64 (OPTION_MD_BASE + 7) | |
10264 | {"mips64", no_argument, NULL, OPTION_MIPS64}, | |
10265 | #define OPTION_MEMBEDDED_PIC (OPTION_MD_BASE + 8) | |
252b5132 | 10266 | {"membedded-pic", no_argument, NULL, OPTION_MEMBEDDED_PIC}, |
ae948b86 | 10267 | #define OPTION_TRAP (OPTION_MD_BASE + 9) |
252b5132 RH |
10268 | {"trap", no_argument, NULL, OPTION_TRAP}, |
10269 | {"no-break", no_argument, NULL, OPTION_TRAP}, | |
ae948b86 | 10270 | #define OPTION_BREAK (OPTION_MD_BASE + 10) |
252b5132 RH |
10271 | {"break", no_argument, NULL, OPTION_BREAK}, |
10272 | {"no-trap", no_argument, NULL, OPTION_BREAK}, | |
ae948b86 | 10273 | #define OPTION_EB (OPTION_MD_BASE + 11) |
252b5132 | 10274 | {"EB", no_argument, NULL, OPTION_EB}, |
ae948b86 | 10275 | #define OPTION_EL (OPTION_MD_BASE + 12) |
252b5132 | 10276 | {"EL", no_argument, NULL, OPTION_EL}, |
ae948b86 | 10277 | #define OPTION_MIPS16 (OPTION_MD_BASE + 13) |
252b5132 | 10278 | {"mips16", no_argument, NULL, OPTION_MIPS16}, |
ae948b86 | 10279 | #define OPTION_NO_MIPS16 (OPTION_MD_BASE + 14) |
252b5132 | 10280 | {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16}, |
ae948b86 | 10281 | #define OPTION_M7000_HILO_FIX (OPTION_MD_BASE + 15) |
6b76fefe | 10282 | {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX}, |
9ee72ff1 TS |
10283 | #define OPTION_MNO_7000_HILO_FIX (OPTION_MD_BASE + 16) |
10284 | {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, | |
10285 | {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, | |
ae948b86 TS |
10286 | #define OPTION_FP32 (OPTION_MD_BASE + 17) |
10287 | {"mfp32", no_argument, NULL, OPTION_FP32}, | |
10288 | #define OPTION_GP32 (OPTION_MD_BASE + 18) | |
c97ef257 | 10289 | {"mgp32", no_argument, NULL, OPTION_GP32}, |
ae948b86 | 10290 | #define OPTION_CONSTRUCT_FLOATS (OPTION_MD_BASE + 19) |
119d663a | 10291 | {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS}, |
ae948b86 | 10292 | #define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MD_BASE + 20) |
119d663a | 10293 | {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS}, |
ae948b86 | 10294 | #define OPTION_MARCH (OPTION_MD_BASE + 21) |
ec68c924 | 10295 | {"march", required_argument, NULL, OPTION_MARCH}, |
ae948b86 | 10296 | #define OPTION_MTUNE (OPTION_MD_BASE + 22) |
ec68c924 | 10297 | {"mtune", required_argument, NULL, OPTION_MTUNE}, |
316f5878 RS |
10298 | #define OPTION_FP64 (OPTION_MD_BASE + 23) |
10299 | {"mfp64", no_argument, NULL, OPTION_FP64}, | |
ae948b86 TS |
10300 | #define OPTION_M4650 (OPTION_MD_BASE + 24) |
10301 | {"m4650", no_argument, NULL, OPTION_M4650}, | |
10302 | #define OPTION_NO_M4650 (OPTION_MD_BASE + 25) | |
10303 | {"no-m4650", no_argument, NULL, OPTION_NO_M4650}, | |
10304 | #define OPTION_M4010 (OPTION_MD_BASE + 26) | |
10305 | {"m4010", no_argument, NULL, OPTION_M4010}, | |
10306 | #define OPTION_NO_M4010 (OPTION_MD_BASE + 27) | |
10307 | {"no-m4010", no_argument, NULL, OPTION_NO_M4010}, | |
10308 | #define OPTION_M4100 (OPTION_MD_BASE + 28) | |
10309 | {"m4100", no_argument, NULL, OPTION_M4100}, | |
10310 | #define OPTION_NO_M4100 (OPTION_MD_BASE + 29) | |
10311 | {"no-m4100", no_argument, NULL, OPTION_NO_M4100}, | |
10312 | #define OPTION_M3900 (OPTION_MD_BASE + 30) | |
10313 | {"m3900", no_argument, NULL, OPTION_M3900}, | |
10314 | #define OPTION_NO_M3900 (OPTION_MD_BASE + 31) | |
10315 | {"no-m3900", no_argument, NULL, OPTION_NO_M3900}, | |
10316 | #define OPTION_GP64 (OPTION_MD_BASE + 32) | |
10317 | {"mgp64", no_argument, NULL, OPTION_GP64}, | |
1f25f5d3 CD |
10318 | #define OPTION_MIPS3D (OPTION_MD_BASE + 33) |
10319 | {"mips3d", no_argument, NULL, OPTION_MIPS3D}, | |
10320 | #define OPTION_NO_MIPS3D (OPTION_MD_BASE + 34) | |
10321 | {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D}, | |
deec1734 CD |
10322 | #define OPTION_MDMX (OPTION_MD_BASE + 35) |
10323 | {"mdmx", no_argument, NULL, OPTION_MDMX}, | |
10324 | #define OPTION_NO_MDMX (OPTION_MD_BASE + 36) | |
10325 | {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX}, | |
60b63b72 RS |
10326 | #define OPTION_FIX_VR4122 (OPTION_MD_BASE + 37) |
10327 | #define OPTION_NO_FIX_VR4122 (OPTION_MD_BASE + 38) | |
10328 | {"mfix-vr4122-bugs", no_argument, NULL, OPTION_FIX_VR4122}, | |
10329 | {"no-mfix-vr4122-bugs", no_argument, NULL, OPTION_NO_FIX_VR4122}, | |
4a6a3df4 AO |
10330 | #define OPTION_RELAX_BRANCH (OPTION_MD_BASE + 39) |
10331 | #define OPTION_NO_RELAX_BRANCH (OPTION_MD_BASE + 40) | |
10332 | {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH}, | |
10333 | {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH}, | |
af7ee8bf CD |
10334 | #define OPTION_MIPS32R2 (OPTION_MD_BASE + 41) |
10335 | {"mips32r2", no_argument, NULL, OPTION_MIPS32R2}, | |
156c2f8b | 10336 | #ifdef OBJ_ELF |
af7ee8bf | 10337 | #define OPTION_ELF_BASE (OPTION_MD_BASE + 42) |
156c2f8b | 10338 | #define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0) |
156c2f8b NC |
10339 | {"KPIC", no_argument, NULL, OPTION_CALL_SHARED}, |
10340 | {"call_shared", no_argument, NULL, OPTION_CALL_SHARED}, | |
ae948b86 | 10341 | #define OPTION_NON_SHARED (OPTION_ELF_BASE + 1) |
156c2f8b | 10342 | {"non_shared", no_argument, NULL, OPTION_NON_SHARED}, |
ae948b86 | 10343 | #define OPTION_XGOT (OPTION_ELF_BASE + 2) |
156c2f8b | 10344 | {"xgot", no_argument, NULL, OPTION_XGOT}, |
ae948b86 TS |
10345 | #define OPTION_MABI (OPTION_ELF_BASE + 3) |
10346 | {"mabi", required_argument, NULL, OPTION_MABI}, | |
10347 | #define OPTION_32 (OPTION_ELF_BASE + 4) | |
156c2f8b | 10348 | {"32", no_argument, NULL, OPTION_32}, |
ae948b86 | 10349 | #define OPTION_N32 (OPTION_ELF_BASE + 5) |
e013f690 | 10350 | {"n32", no_argument, NULL, OPTION_N32}, |
ae948b86 | 10351 | #define OPTION_64 (OPTION_ELF_BASE + 6) |
156c2f8b | 10352 | {"64", no_argument, NULL, OPTION_64}, |
ecb4347a DJ |
10353 | #define OPTION_MDEBUG (OPTION_ELF_BASE + 7) |
10354 | {"mdebug", no_argument, NULL, OPTION_MDEBUG}, | |
10355 | #define OPTION_NO_MDEBUG (OPTION_ELF_BASE + 8) | |
10356 | {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG}, | |
ae948b86 | 10357 | #endif /* OBJ_ELF */ |
252b5132 RH |
10358 | {NULL, no_argument, NULL, 0} |
10359 | }; | |
156c2f8b | 10360 | size_t md_longopts_size = sizeof (md_longopts); |
252b5132 | 10361 | |
316f5878 RS |
10362 | /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to |
10363 | NEW_VALUE. Warn if another value was already specified. Note: | |
10364 | we have to defer parsing the -march and -mtune arguments in order | |
10365 | to handle 'from-abi' correctly, since the ABI might be specified | |
10366 | in a later argument. */ | |
10367 | ||
10368 | static void | |
10369 | mips_set_option_string (string_ptr, new_value) | |
10370 | const char **string_ptr, *new_value; | |
10371 | { | |
10372 | if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0) | |
10373 | as_warn (_("A different %s was already specified, is now %s"), | |
10374 | string_ptr == &mips_arch_string ? "-march" : "-mtune", | |
10375 | new_value); | |
10376 | ||
10377 | *string_ptr = new_value; | |
10378 | } | |
10379 | ||
252b5132 RH |
10380 | int |
10381 | md_parse_option (c, arg) | |
10382 | int c; | |
10383 | char *arg; | |
10384 | { | |
10385 | switch (c) | |
10386 | { | |
119d663a NC |
10387 | case OPTION_CONSTRUCT_FLOATS: |
10388 | mips_disable_float_construction = 0; | |
10389 | break; | |
bdaaa2e1 | 10390 | |
119d663a NC |
10391 | case OPTION_NO_CONSTRUCT_FLOATS: |
10392 | mips_disable_float_construction = 1; | |
10393 | break; | |
bdaaa2e1 | 10394 | |
252b5132 RH |
10395 | case OPTION_TRAP: |
10396 | mips_trap = 1; | |
10397 | break; | |
10398 | ||
10399 | case OPTION_BREAK: | |
10400 | mips_trap = 0; | |
10401 | break; | |
10402 | ||
10403 | case OPTION_EB: | |
10404 | target_big_endian = 1; | |
10405 | break; | |
10406 | ||
10407 | case OPTION_EL: | |
10408 | target_big_endian = 0; | |
10409 | break; | |
10410 | ||
39c0a331 L |
10411 | case 'n': |
10412 | warn_nops = 1; | |
10413 | break; | |
10414 | ||
252b5132 RH |
10415 | case 'O': |
10416 | if (arg && arg[1] == '0') | |
10417 | mips_optimize = 1; | |
10418 | else | |
10419 | mips_optimize = 2; | |
10420 | break; | |
10421 | ||
10422 | case 'g': | |
10423 | if (arg == NULL) | |
10424 | mips_debug = 2; | |
10425 | else | |
10426 | mips_debug = atoi (arg); | |
10427 | /* When the MIPS assembler sees -g or -g2, it does not do | |
10428 | optimizations which limit full symbolic debugging. We take | |
10429 | that to be equivalent to -O0. */ | |
10430 | if (mips_debug == 2) | |
10431 | mips_optimize = 1; | |
10432 | break; | |
10433 | ||
10434 | case OPTION_MIPS1: | |
316f5878 | 10435 | file_mips_isa = ISA_MIPS1; |
252b5132 RH |
10436 | break; |
10437 | ||
10438 | case OPTION_MIPS2: | |
316f5878 | 10439 | file_mips_isa = ISA_MIPS2; |
252b5132 RH |
10440 | break; |
10441 | ||
10442 | case OPTION_MIPS3: | |
316f5878 | 10443 | file_mips_isa = ISA_MIPS3; |
252b5132 RH |
10444 | break; |
10445 | ||
10446 | case OPTION_MIPS4: | |
316f5878 | 10447 | file_mips_isa = ISA_MIPS4; |
e7af610e NC |
10448 | break; |
10449 | ||
84ea6cf2 | 10450 | case OPTION_MIPS5: |
316f5878 | 10451 | file_mips_isa = ISA_MIPS5; |
84ea6cf2 NC |
10452 | break; |
10453 | ||
e7af610e | 10454 | case OPTION_MIPS32: |
316f5878 | 10455 | file_mips_isa = ISA_MIPS32; |
252b5132 RH |
10456 | break; |
10457 | ||
af7ee8bf CD |
10458 | case OPTION_MIPS32R2: |
10459 | file_mips_isa = ISA_MIPS32R2; | |
10460 | break; | |
10461 | ||
84ea6cf2 | 10462 | case OPTION_MIPS64: |
316f5878 | 10463 | file_mips_isa = ISA_MIPS64; |
84ea6cf2 NC |
10464 | break; |
10465 | ||
ec68c924 | 10466 | case OPTION_MTUNE: |
316f5878 RS |
10467 | mips_set_option_string (&mips_tune_string, arg); |
10468 | break; | |
ec68c924 | 10469 | |
316f5878 RS |
10470 | case OPTION_MARCH: |
10471 | mips_set_option_string (&mips_arch_string, arg); | |
252b5132 RH |
10472 | break; |
10473 | ||
10474 | case OPTION_M4650: | |
316f5878 RS |
10475 | mips_set_option_string (&mips_arch_string, "4650"); |
10476 | mips_set_option_string (&mips_tune_string, "4650"); | |
252b5132 RH |
10477 | break; |
10478 | ||
10479 | case OPTION_NO_M4650: | |
10480 | break; | |
10481 | ||
10482 | case OPTION_M4010: | |
316f5878 RS |
10483 | mips_set_option_string (&mips_arch_string, "4010"); |
10484 | mips_set_option_string (&mips_tune_string, "4010"); | |
252b5132 RH |
10485 | break; |
10486 | ||
10487 | case OPTION_NO_M4010: | |
10488 | break; | |
10489 | ||
10490 | case OPTION_M4100: | |
316f5878 RS |
10491 | mips_set_option_string (&mips_arch_string, "4100"); |
10492 | mips_set_option_string (&mips_tune_string, "4100"); | |
252b5132 RH |
10493 | break; |
10494 | ||
10495 | case OPTION_NO_M4100: | |
10496 | break; | |
10497 | ||
252b5132 | 10498 | case OPTION_M3900: |
316f5878 RS |
10499 | mips_set_option_string (&mips_arch_string, "3900"); |
10500 | mips_set_option_string (&mips_tune_string, "3900"); | |
252b5132 | 10501 | break; |
bdaaa2e1 | 10502 | |
252b5132 RH |
10503 | case OPTION_NO_M3900: |
10504 | break; | |
10505 | ||
deec1734 CD |
10506 | case OPTION_MDMX: |
10507 | mips_opts.ase_mdmx = 1; | |
10508 | break; | |
10509 | ||
10510 | case OPTION_NO_MDMX: | |
10511 | mips_opts.ase_mdmx = 0; | |
10512 | break; | |
10513 | ||
252b5132 RH |
10514 | case OPTION_MIPS16: |
10515 | mips_opts.mips16 = 1; | |
b34976b6 | 10516 | mips_no_prev_insn (FALSE); |
252b5132 RH |
10517 | break; |
10518 | ||
10519 | case OPTION_NO_MIPS16: | |
10520 | mips_opts.mips16 = 0; | |
b34976b6 | 10521 | mips_no_prev_insn (FALSE); |
252b5132 RH |
10522 | break; |
10523 | ||
1f25f5d3 CD |
10524 | case OPTION_MIPS3D: |
10525 | mips_opts.ase_mips3d = 1; | |
10526 | break; | |
10527 | ||
10528 | case OPTION_NO_MIPS3D: | |
10529 | mips_opts.ase_mips3d = 0; | |
10530 | break; | |
10531 | ||
252b5132 RH |
10532 | case OPTION_MEMBEDDED_PIC: |
10533 | mips_pic = EMBEDDED_PIC; | |
10534 | if (USE_GLOBAL_POINTER_OPT && g_switch_seen) | |
10535 | { | |
10536 | as_bad (_("-G may not be used with embedded PIC code")); | |
10537 | return 0; | |
10538 | } | |
10539 | g_switch_value = 0x7fffffff; | |
10540 | break; | |
10541 | ||
60b63b72 RS |
10542 | case OPTION_FIX_VR4122: |
10543 | mips_fix_4122_bugs = 1; | |
10544 | break; | |
10545 | ||
10546 | case OPTION_NO_FIX_VR4122: | |
10547 | mips_fix_4122_bugs = 0; | |
10548 | break; | |
10549 | ||
4a6a3df4 AO |
10550 | case OPTION_RELAX_BRANCH: |
10551 | mips_relax_branch = 1; | |
10552 | break; | |
10553 | ||
10554 | case OPTION_NO_RELAX_BRANCH: | |
10555 | mips_relax_branch = 0; | |
10556 | break; | |
10557 | ||
0f074f60 | 10558 | #ifdef OBJ_ELF |
252b5132 RH |
10559 | /* When generating ELF code, we permit -KPIC and -call_shared to |
10560 | select SVR4_PIC, and -non_shared to select no PIC. This is | |
10561 | intended to be compatible with Irix 5. */ | |
10562 | case OPTION_CALL_SHARED: | |
10563 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
10564 | { | |
10565 | as_bad (_("-call_shared is supported only for ELF format")); | |
10566 | return 0; | |
10567 | } | |
10568 | mips_pic = SVR4_PIC; | |
10569 | if (g_switch_seen && g_switch_value != 0) | |
10570 | { | |
10571 | as_bad (_("-G may not be used with SVR4 PIC code")); | |
10572 | return 0; | |
10573 | } | |
10574 | g_switch_value = 0; | |
10575 | break; | |
10576 | ||
10577 | case OPTION_NON_SHARED: | |
10578 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
10579 | { | |
10580 | as_bad (_("-non_shared is supported only for ELF format")); | |
10581 | return 0; | |
10582 | } | |
10583 | mips_pic = NO_PIC; | |
10584 | break; | |
10585 | ||
10586 | /* The -xgot option tells the assembler to use 32 offsets when | |
10587 | accessing the got in SVR4_PIC mode. It is for Irix | |
10588 | compatibility. */ | |
10589 | case OPTION_XGOT: | |
10590 | mips_big_got = 1; | |
10591 | break; | |
0f074f60 | 10592 | #endif /* OBJ_ELF */ |
252b5132 RH |
10593 | |
10594 | case 'G': | |
10595 | if (! USE_GLOBAL_POINTER_OPT) | |
10596 | { | |
10597 | as_bad (_("-G is not supported for this configuration")); | |
10598 | return 0; | |
10599 | } | |
10600 | else if (mips_pic == SVR4_PIC || mips_pic == EMBEDDED_PIC) | |
10601 | { | |
10602 | as_bad (_("-G may not be used with SVR4 or embedded PIC code")); | |
10603 | return 0; | |
10604 | } | |
10605 | else | |
10606 | g_switch_value = atoi (arg); | |
10607 | g_switch_seen = 1; | |
10608 | break; | |
10609 | ||
0f074f60 | 10610 | #ifdef OBJ_ELF |
34ba82a8 TS |
10611 | /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32 |
10612 | and -mabi=64. */ | |
252b5132 | 10613 | case OPTION_32: |
34ba82a8 TS |
10614 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
10615 | { | |
10616 | as_bad (_("-32 is supported for ELF format only")); | |
10617 | return 0; | |
10618 | } | |
316f5878 | 10619 | mips_abi = O32_ABI; |
252b5132 RH |
10620 | break; |
10621 | ||
e013f690 | 10622 | case OPTION_N32: |
34ba82a8 TS |
10623 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
10624 | { | |
10625 | as_bad (_("-n32 is supported for ELF format only")); | |
10626 | return 0; | |
10627 | } | |
316f5878 | 10628 | mips_abi = N32_ABI; |
e013f690 | 10629 | break; |
252b5132 | 10630 | |
e013f690 | 10631 | case OPTION_64: |
34ba82a8 TS |
10632 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
10633 | { | |
10634 | as_bad (_("-64 is supported for ELF format only")); | |
10635 | return 0; | |
10636 | } | |
316f5878 | 10637 | mips_abi = N64_ABI; |
e013f690 TS |
10638 | if (! support_64bit_objects()) |
10639 | as_fatal (_("No compiled in support for 64 bit object file format")); | |
252b5132 | 10640 | break; |
ae948b86 | 10641 | #endif /* OBJ_ELF */ |
252b5132 | 10642 | |
c97ef257 | 10643 | case OPTION_GP32: |
a325df1d | 10644 | file_mips_gp32 = 1; |
c97ef257 AH |
10645 | break; |
10646 | ||
10647 | case OPTION_GP64: | |
a325df1d | 10648 | file_mips_gp32 = 0; |
c97ef257 | 10649 | break; |
252b5132 | 10650 | |
ca4e0257 | 10651 | case OPTION_FP32: |
a325df1d | 10652 | file_mips_fp32 = 1; |
316f5878 RS |
10653 | break; |
10654 | ||
10655 | case OPTION_FP64: | |
10656 | file_mips_fp32 = 0; | |
ca4e0257 RS |
10657 | break; |
10658 | ||
ae948b86 | 10659 | #ifdef OBJ_ELF |
252b5132 | 10660 | case OPTION_MABI: |
34ba82a8 TS |
10661 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
10662 | { | |
10663 | as_bad (_("-mabi is supported for ELF format only")); | |
10664 | return 0; | |
10665 | } | |
e013f690 | 10666 | if (strcmp (arg, "32") == 0) |
316f5878 | 10667 | mips_abi = O32_ABI; |
e013f690 | 10668 | else if (strcmp (arg, "o64") == 0) |
316f5878 | 10669 | mips_abi = O64_ABI; |
e013f690 | 10670 | else if (strcmp (arg, "n32") == 0) |
316f5878 | 10671 | mips_abi = N32_ABI; |
e013f690 TS |
10672 | else if (strcmp (arg, "64") == 0) |
10673 | { | |
316f5878 | 10674 | mips_abi = N64_ABI; |
e013f690 TS |
10675 | if (! support_64bit_objects()) |
10676 | as_fatal (_("No compiled in support for 64 bit object file " | |
10677 | "format")); | |
10678 | } | |
10679 | else if (strcmp (arg, "eabi") == 0) | |
316f5878 | 10680 | mips_abi = EABI_ABI; |
e013f690 | 10681 | else |
da0e507f TS |
10682 | { |
10683 | as_fatal (_("invalid abi -mabi=%s"), arg); | |
10684 | return 0; | |
10685 | } | |
252b5132 | 10686 | break; |
e013f690 | 10687 | #endif /* OBJ_ELF */ |
252b5132 | 10688 | |
6b76fefe | 10689 | case OPTION_M7000_HILO_FIX: |
b34976b6 | 10690 | mips_7000_hilo_fix = TRUE; |
6b76fefe CM |
10691 | break; |
10692 | ||
9ee72ff1 | 10693 | case OPTION_MNO_7000_HILO_FIX: |
b34976b6 | 10694 | mips_7000_hilo_fix = FALSE; |
6b76fefe CM |
10695 | break; |
10696 | ||
ecb4347a DJ |
10697 | #ifdef OBJ_ELF |
10698 | case OPTION_MDEBUG: | |
b34976b6 | 10699 | mips_flag_mdebug = TRUE; |
ecb4347a DJ |
10700 | break; |
10701 | ||
10702 | case OPTION_NO_MDEBUG: | |
b34976b6 | 10703 | mips_flag_mdebug = FALSE; |
ecb4347a DJ |
10704 | break; |
10705 | #endif /* OBJ_ELF */ | |
10706 | ||
252b5132 RH |
10707 | default: |
10708 | return 0; | |
10709 | } | |
10710 | ||
10711 | return 1; | |
10712 | } | |
316f5878 RS |
10713 | \f |
10714 | /* Set up globals to generate code for the ISA or processor | |
10715 | described by INFO. */ | |
252b5132 | 10716 | |
252b5132 | 10717 | static void |
316f5878 RS |
10718 | mips_set_architecture (info) |
10719 | const struct mips_cpu_info *info; | |
252b5132 | 10720 | { |
316f5878 | 10721 | if (info != 0) |
252b5132 | 10722 | { |
316f5878 RS |
10723 | mips_arch_info = info; |
10724 | mips_arch = info->cpu; | |
10725 | mips_opts.isa = info->isa; | |
252b5132 | 10726 | } |
252b5132 RH |
10727 | } |
10728 | ||
252b5132 | 10729 | |
316f5878 | 10730 | /* Likewise for tuning. */ |
252b5132 | 10731 | |
316f5878 RS |
10732 | static void |
10733 | mips_set_tune (info) | |
10734 | const struct mips_cpu_info *info; | |
10735 | { | |
10736 | if (info != 0) | |
10737 | { | |
10738 | mips_tune_info = info; | |
10739 | mips_tune = info->cpu; | |
10740 | } | |
10741 | } | |
80cc45a5 | 10742 | |
34ba82a8 | 10743 | |
252b5132 | 10744 | void |
e9670677 MR |
10745 | mips_after_parse_args () |
10746 | { | |
e9670677 MR |
10747 | /* GP relative stuff not working for PE */ |
10748 | if (strncmp (TARGET_OS, "pe", 2) == 0 | |
10749 | && g_switch_value != 0) | |
10750 | { | |
10751 | if (g_switch_seen) | |
10752 | as_bad (_("-G not supported in this configuration.")); | |
10753 | g_switch_value = 0; | |
10754 | } | |
10755 | ||
22923709 RS |
10756 | /* The following code determines the architecture and register size. |
10757 | Similar code was added to GCC 3.3 (see override_options() in | |
10758 | config/mips/mips.c). The GAS and GCC code should be kept in sync | |
10759 | as much as possible. */ | |
e9670677 | 10760 | |
316f5878 RS |
10761 | if (mips_arch_string != 0) |
10762 | mips_set_architecture (mips_parse_cpu ("-march", mips_arch_string)); | |
e9670677 | 10763 | |
316f5878 RS |
10764 | if (mips_tune_string != 0) |
10765 | mips_set_tune (mips_parse_cpu ("-mtune", mips_tune_string)); | |
e9670677 | 10766 | |
316f5878 | 10767 | if (file_mips_isa != ISA_UNKNOWN) |
e9670677 | 10768 | { |
316f5878 RS |
10769 | /* Handle -mipsN. At this point, file_mips_isa contains the |
10770 | ISA level specified by -mipsN, while mips_opts.isa contains | |
10771 | the -march selection (if any). */ | |
10772 | if (mips_arch_info != 0) | |
e9670677 | 10773 | { |
316f5878 RS |
10774 | /* -march takes precedence over -mipsN, since it is more descriptive. |
10775 | There's no harm in specifying both as long as the ISA levels | |
10776 | are the same. */ | |
10777 | if (file_mips_isa != mips_opts.isa) | |
10778 | as_bad (_("-%s conflicts with the other architecture options, which imply -%s"), | |
10779 | mips_cpu_info_from_isa (file_mips_isa)->name, | |
10780 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
e9670677 | 10781 | } |
316f5878 RS |
10782 | else |
10783 | mips_set_architecture (mips_cpu_info_from_isa (file_mips_isa)); | |
e9670677 MR |
10784 | } |
10785 | ||
316f5878 RS |
10786 | if (mips_arch_info == 0) |
10787 | mips_set_architecture (mips_parse_cpu ("default CPU", | |
10788 | MIPS_CPU_STRING_DEFAULT)); | |
e9670677 | 10789 | |
316f5878 RS |
10790 | if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (mips_opts.isa)) |
10791 | as_bad ("-march=%s is not compatible with the selected ABI", | |
10792 | mips_arch_info->name); | |
e9670677 | 10793 | |
316f5878 RS |
10794 | /* Optimize for mips_arch, unless -mtune selects a different processor. */ |
10795 | if (mips_tune_info == 0) | |
10796 | mips_set_tune (mips_arch_info); | |
e9670677 | 10797 | |
316f5878 | 10798 | if (file_mips_gp32 >= 0) |
e9670677 | 10799 | { |
316f5878 RS |
10800 | /* The user specified the size of the integer registers. Make sure |
10801 | it agrees with the ABI and ISA. */ | |
10802 | if (file_mips_gp32 == 0 && !ISA_HAS_64BIT_REGS (mips_opts.isa)) | |
10803 | as_bad (_("-mgp64 used with a 32-bit processor")); | |
10804 | else if (file_mips_gp32 == 1 && ABI_NEEDS_64BIT_REGS (mips_abi)) | |
10805 | as_bad (_("-mgp32 used with a 64-bit ABI")); | |
10806 | else if (file_mips_gp32 == 0 && ABI_NEEDS_32BIT_REGS (mips_abi)) | |
10807 | as_bad (_("-mgp64 used with a 32-bit ABI")); | |
e9670677 MR |
10808 | } |
10809 | else | |
10810 | { | |
316f5878 RS |
10811 | /* Infer the integer register size from the ABI and processor. |
10812 | Restrict ourselves to 32-bit registers if that's all the | |
10813 | processor has, or if the ABI cannot handle 64-bit registers. */ | |
10814 | file_mips_gp32 = (ABI_NEEDS_32BIT_REGS (mips_abi) | |
10815 | || !ISA_HAS_64BIT_REGS (mips_opts.isa)); | |
e9670677 MR |
10816 | } |
10817 | ||
316f5878 RS |
10818 | /* ??? GAS treats single-float processors as though they had 64-bit |
10819 | float registers (although it complains when double-precision | |
10820 | instructions are used). As things stand, saying they have 32-bit | |
10821 | registers would lead to spurious "register must be even" messages. | |
10822 | So here we assume float registers are always the same size as | |
10823 | integer ones, unless the user says otherwise. */ | |
10824 | if (file_mips_fp32 < 0) | |
10825 | file_mips_fp32 = file_mips_gp32; | |
e9670677 | 10826 | |
316f5878 | 10827 | /* End of GCC-shared inference code. */ |
e9670677 | 10828 | |
316f5878 RS |
10829 | /* ??? When do we want this flag to be set? Who uses it? */ |
10830 | if (file_mips_gp32 == 1 | |
10831 | && mips_abi == NO_ABI | |
10832 | && ISA_HAS_64BIT_REGS (mips_opts.isa)) | |
10833 | mips_32bitmode = 1; | |
e9670677 MR |
10834 | |
10835 | if (mips_opts.isa == ISA_MIPS1 && mips_trap) | |
10836 | as_bad (_("trap exception not supported at ISA 1")); | |
10837 | ||
e9670677 MR |
10838 | /* If the selected architecture includes support for ASEs, enable |
10839 | generation of code for them. */ | |
a4672219 TS |
10840 | if (mips_opts.mips16 == -1) |
10841 | mips_opts.mips16 = (CPU_HAS_MIPS16 (mips_arch)) ? 1 : 0; | |
ffdefa66 | 10842 | if (mips_opts.ase_mips3d == -1) |
a4672219 | 10843 | mips_opts.ase_mips3d = (CPU_HAS_MIPS3D (mips_arch)) ? 1 : 0; |
ffdefa66 | 10844 | if (mips_opts.ase_mdmx == -1) |
a4672219 | 10845 | mips_opts.ase_mdmx = (CPU_HAS_MDMX (mips_arch)) ? 1 : 0; |
e9670677 | 10846 | |
e9670677 | 10847 | file_mips_isa = mips_opts.isa; |
a4672219 | 10848 | file_ase_mips16 = mips_opts.mips16; |
e9670677 MR |
10849 | file_ase_mips3d = mips_opts.ase_mips3d; |
10850 | file_ase_mdmx = mips_opts.ase_mdmx; | |
10851 | mips_opts.gp32 = file_mips_gp32; | |
10852 | mips_opts.fp32 = file_mips_fp32; | |
10853 | ||
ecb4347a DJ |
10854 | if (mips_flag_mdebug < 0) |
10855 | { | |
10856 | #ifdef OBJ_MAYBE_ECOFF | |
10857 | if (OUTPUT_FLAVOR == bfd_target_ecoff_flavour) | |
10858 | mips_flag_mdebug = 1; | |
10859 | else | |
10860 | #endif /* OBJ_MAYBE_ECOFF */ | |
10861 | mips_flag_mdebug = 0; | |
10862 | } | |
e9670677 MR |
10863 | } |
10864 | \f | |
10865 | void | |
252b5132 RH |
10866 | mips_init_after_args () |
10867 | { | |
10868 | /* initialize opcodes */ | |
10869 | bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes; | |
beae10d5 | 10870 | mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes; |
252b5132 RH |
10871 | } |
10872 | ||
10873 | long | |
10874 | md_pcrel_from (fixP) | |
10875 | fixS *fixP; | |
10876 | { | |
10877 | if (OUTPUT_FLAVOR != bfd_target_aout_flavour | |
10878 | && fixP->fx_addsy != (symbolS *) NULL | |
10879 | && ! S_IS_DEFINED (fixP->fx_addsy)) | |
af6ae2ad | 10880 | return 4; |
252b5132 | 10881 | |
c9914766 | 10882 | /* Return the address of the delay slot. */ |
252b5132 RH |
10883 | return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address; |
10884 | } | |
10885 | ||
252b5132 RH |
10886 | /* This is called before the symbol table is processed. In order to |
10887 | work with gcc when using mips-tfile, we must keep all local labels. | |
10888 | However, in other cases, we want to discard them. If we were | |
10889 | called with -g, but we didn't see any debugging information, it may | |
10890 | mean that gcc is smuggling debugging information through to | |
10891 | mips-tfile, in which case we must generate all local labels. */ | |
10892 | ||
10893 | void | |
10894 | mips_frob_file_before_adjust () | |
10895 | { | |
10896 | #ifndef NO_ECOFF_DEBUGGING | |
10897 | if (ECOFF_DEBUGGING | |
10898 | && mips_debug != 0 | |
10899 | && ! ecoff_debugging_seen) | |
10900 | flag_keep_locals = 1; | |
10901 | #endif | |
10902 | } | |
10903 | ||
10904 | /* Sort any unmatched HI16_S relocs so that they immediately precede | |
94f592af | 10905 | the corresponding LO reloc. This is called before md_apply_fix3 and |
252b5132 RH |
10906 | tc_gen_reloc. Unmatched HI16_S relocs can only be generated by |
10907 | explicit use of the %hi modifier. */ | |
10908 | ||
10909 | void | |
10910 | mips_frob_file () | |
10911 | { | |
10912 | struct mips_hi_fixup *l; | |
10913 | ||
10914 | for (l = mips_hi_fixup_list; l != NULL; l = l->next) | |
10915 | { | |
10916 | segment_info_type *seginfo; | |
10917 | int pass; | |
10918 | ||
5919d012 | 10919 | assert (reloc_needs_lo_p (l->fixp->fx_r_type)); |
252b5132 | 10920 | |
5919d012 RS |
10921 | /* If a GOT16 relocation turns out to be against a global symbol, |
10922 | there isn't supposed to be a matching LO. */ | |
10923 | if (l->fixp->fx_r_type == BFD_RELOC_MIPS_GOT16 | |
10924 | && !pic_need_relax (l->fixp->fx_addsy, l->seg)) | |
10925 | continue; | |
10926 | ||
10927 | /* Check quickly whether the next fixup happens to be a matching %lo. */ | |
10928 | if (fixup_has_matching_lo_p (l->fixp)) | |
252b5132 RH |
10929 | continue; |
10930 | ||
10931 | /* Look through the fixups for this segment for a matching %lo. | |
10932 | When we find one, move the %hi just in front of it. We do | |
10933 | this in two passes. In the first pass, we try to find a | |
10934 | unique %lo. In the second pass, we permit multiple %hi | |
10935 | relocs for a single %lo (this is a GNU extension). */ | |
10936 | seginfo = seg_info (l->seg); | |
10937 | for (pass = 0; pass < 2; pass++) | |
10938 | { | |
10939 | fixS *f, *prev; | |
10940 | ||
10941 | prev = NULL; | |
10942 | for (f = seginfo->fix_root; f != NULL; f = f->fx_next) | |
10943 | { | |
10944 | /* Check whether this is a %lo fixup which matches l->fixp. */ | |
10945 | if (f->fx_r_type == BFD_RELOC_LO16 | |
10946 | && f->fx_addsy == l->fixp->fx_addsy | |
10947 | && f->fx_offset == l->fixp->fx_offset | |
10948 | && (pass == 1 | |
10949 | || prev == NULL | |
5919d012 RS |
10950 | || !reloc_needs_lo_p (prev->fx_r_type) |
10951 | || !fixup_has_matching_lo_p (prev))) | |
252b5132 RH |
10952 | { |
10953 | fixS **pf; | |
10954 | ||
10955 | /* Move l->fixp before f. */ | |
10956 | for (pf = &seginfo->fix_root; | |
10957 | *pf != l->fixp; | |
10958 | pf = &(*pf)->fx_next) | |
10959 | assert (*pf != NULL); | |
10960 | ||
10961 | *pf = l->fixp->fx_next; | |
10962 | ||
10963 | l->fixp->fx_next = f; | |
10964 | if (prev == NULL) | |
10965 | seginfo->fix_root = l->fixp; | |
10966 | else | |
10967 | prev->fx_next = l->fixp; | |
10968 | ||
10969 | break; | |
10970 | } | |
10971 | ||
10972 | prev = f; | |
10973 | } | |
10974 | ||
10975 | if (f != NULL) | |
10976 | break; | |
10977 | ||
10978 | #if 0 /* GCC code motion plus incomplete dead code elimination | |
10979 | can leave a %hi without a %lo. */ | |
10980 | if (pass == 1) | |
10981 | as_warn_where (l->fixp->fx_file, l->fixp->fx_line, | |
10982 | _("Unmatched %%hi reloc")); | |
10983 | #endif | |
10984 | } | |
10985 | } | |
10986 | } | |
10987 | ||
10988 | /* When generating embedded PIC code we need to use a special | |
10989 | relocation to represent the difference of two symbols in the .text | |
10990 | section (switch tables use a difference of this sort). See | |
10991 | include/coff/mips.h for details. This macro checks whether this | |
10992 | fixup requires the special reloc. */ | |
10993 | #define SWITCH_TABLE(fixp) \ | |
10994 | ((fixp)->fx_r_type == BFD_RELOC_32 \ | |
bb2d6cd7 | 10995 | && OUTPUT_FLAVOR != bfd_target_elf_flavour \ |
252b5132 RH |
10996 | && (fixp)->fx_addsy != NULL \ |
10997 | && (fixp)->fx_subsy != NULL \ | |
10998 | && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \ | |
10999 | && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section) | |
11000 | ||
11001 | /* When generating embedded PIC code we must keep all PC relative | |
11002 | relocations, in case the linker has to relax a call. We also need | |
f6688943 TS |
11003 | to keep relocations for switch table entries. |
11004 | ||
11005 | We may have combined relocations without symbols in the N32/N64 ABI. | |
11006 | We have to prevent gas from dropping them. */ | |
252b5132 | 11007 | |
252b5132 RH |
11008 | int |
11009 | mips_force_relocation (fixp) | |
11010 | fixS *fixp; | |
11011 | { | |
ae6063d4 | 11012 | if (generic_force_reloc (fixp)) |
252b5132 RH |
11013 | return 1; |
11014 | ||
f6688943 TS |
11015 | if (HAVE_NEWABI |
11016 | && S_GET_SEGMENT (fixp->fx_addsy) == bfd_abs_section_ptr | |
11017 | && (fixp->fx_r_type == BFD_RELOC_MIPS_SUB | |
11018 | || fixp->fx_r_type == BFD_RELOC_HI16_S | |
11019 | || fixp->fx_r_type == BFD_RELOC_LO16)) | |
11020 | return 1; | |
11021 | ||
252b5132 RH |
11022 | return (mips_pic == EMBEDDED_PIC |
11023 | && (fixp->fx_pcrel | |
11024 | || SWITCH_TABLE (fixp) | |
11025 | || fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S | |
11026 | || fixp->fx_r_type == BFD_RELOC_PCREL_LO16)); | |
11027 | } | |
11028 | ||
45f8dfe8 AO |
11029 | /* This hook is called before a fix is simplified. We don't really |
11030 | decide whether to skip a fix here. Rather, we turn global symbols | |
11031 | used as branch targets into local symbols, such that they undergo | |
11032 | simplification. We can only do this if the symbol is defined and | |
11033 | it is in the same section as the branch. If this doesn't hold, we | |
11034 | emit a better error message than just saying the relocation is not | |
11035 | valid for the selected object format. | |
11036 | ||
11037 | FIXP is the fix-up we're going to try to simplify, SEG is the | |
11038 | segment in which the fix up occurs. The return value should be | |
11039 | non-zero to indicate the fix-up is valid for further | |
11040 | simplifications. */ | |
11041 | ||
11042 | int | |
11043 | mips_validate_fix (fixP, seg) | |
11044 | struct fix *fixP; | |
11045 | asection *seg; | |
11046 | { | |
11047 | /* There's a lot of discussion on whether it should be possible to | |
11048 | use R_MIPS_PC16 to represent branch relocations. The outcome | |
11049 | seems to be that it can, but gas/bfd are very broken in creating | |
11050 | RELA relocations for this, so for now we only accept branches to | |
11051 | symbols in the same section. Anything else is of dubious value, | |
11052 | since there's no guarantee that at link time the symbol would be | |
11053 | in range. Even for branches to local symbols this is arguably | |
11054 | wrong, since it we assume the symbol is not going to be | |
11055 | overridden, which should be possible per ELF library semantics, | |
11056 | but then, there isn't a dynamic relocation that could be used to | |
11057 | this effect, and the target would likely be out of range as well. | |
11058 | ||
11059 | Unfortunately, it seems that there is too much code out there | |
11060 | that relies on branches to symbols that are global to be resolved | |
11061 | as if they were local, like the IRIX tools do, so we do it as | |
11062 | well, but with a warning so that people are reminded to fix their | |
11063 | code. If we ever get back to using R_MIPS_PC16 for branch | |
11064 | targets, this entire block should go away (and probably the | |
11065 | whole function). */ | |
11066 | ||
11067 | if (fixP->fx_r_type == BFD_RELOC_16_PCREL_S2 | |
11068 | && (((OUTPUT_FLAVOR == bfd_target_ecoff_flavour | |
11069 | || OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
11070 | && mips_pic != EMBEDDED_PIC) | |
11071 | || bfd_reloc_type_lookup (stdoutput, BFD_RELOC_16_PCREL_S2) == NULL) | |
11072 | && fixP->fx_addsy) | |
11073 | { | |
11074 | if (! S_IS_DEFINED (fixP->fx_addsy)) | |
11075 | { | |
11076 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11077 | _("Cannot branch to undefined symbol.")); | |
11078 | /* Avoid any further errors about this fixup. */ | |
11079 | fixP->fx_done = 1; | |
11080 | } | |
11081 | else if (S_GET_SEGMENT (fixP->fx_addsy) != seg) | |
11082 | { | |
11083 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11084 | _("Cannot branch to symbol in another section.")); | |
11085 | fixP->fx_done = 1; | |
11086 | } | |
11087 | else if (S_IS_EXTERNAL (fixP->fx_addsy)) | |
11088 | { | |
11089 | symbolS *sym = fixP->fx_addsy; | |
11090 | ||
11091 | as_warn_where (fixP->fx_file, fixP->fx_line, | |
11092 | _("Pretending global symbol used as branch target is local.")); | |
11093 | ||
11094 | fixP->fx_addsy = symbol_create (S_GET_NAME (sym), | |
11095 | S_GET_SEGMENT (sym), | |
11096 | S_GET_VALUE (sym), | |
11097 | symbol_get_frag (sym)); | |
11098 | copy_symbol_attributes (fixP->fx_addsy, sym); | |
11099 | S_CLEAR_EXTERNAL (fixP->fx_addsy); | |
11100 | assert (symbol_resolved_p (sym)); | |
11101 | symbol_mark_resolved (fixP->fx_addsy); | |
11102 | } | |
11103 | } | |
11104 | ||
11105 | return 1; | |
11106 | } | |
11107 | ||
add55e1f RS |
11108 | #ifdef OBJ_ELF |
11109 | static int | |
11110 | mips_need_elf_addend_fixup (fixP) | |
11111 | fixS *fixP; | |
11112 | { | |
2d2bf3e0 CD |
11113 | if (S_GET_OTHER (fixP->fx_addsy) == STO_MIPS16) |
11114 | return 1; | |
b25a253c CD |
11115 | if (mips_pic == EMBEDDED_PIC |
11116 | && S_IS_WEAK (fixP->fx_addsy)) | |
11117 | return 1; | |
11118 | if (mips_pic != EMBEDDED_PIC | |
11119 | && (S_IS_WEAK (fixP->fx_addsy) | |
bad9ca53 | 11120 | || S_IS_EXTERNAL (fixP->fx_addsy)) |
2d2bf3e0 CD |
11121 | && !S_IS_COMMON (fixP->fx_addsy)) |
11122 | return 1; | |
11123 | if (symbol_used_in_reloc_p (fixP->fx_addsy) | |
11124 | && (((bfd_get_section_flags (stdoutput, | |
11125 | S_GET_SEGMENT (fixP->fx_addsy)) | |
631cb423 | 11126 | & (SEC_LINK_ONCE | SEC_MERGE)) != 0) |
2d2bf3e0 CD |
11127 | || !strncmp (segment_name (S_GET_SEGMENT (fixP->fx_addsy)), |
11128 | ".gnu.linkonce", | |
11129 | sizeof (".gnu.linkonce") - 1))) | |
11130 | return 1; | |
11131 | return 0; | |
add55e1f RS |
11132 | } |
11133 | #endif | |
11134 | ||
252b5132 RH |
11135 | /* Apply a fixup to the object file. */ |
11136 | ||
94f592af NC |
11137 | void |
11138 | md_apply_fix3 (fixP, valP, seg) | |
252b5132 | 11139 | fixS *fixP; |
98d3f06f | 11140 | valueT *valP; |
94f592af | 11141 | segT seg ATTRIBUTE_UNUSED; |
252b5132 | 11142 | { |
874e8986 | 11143 | bfd_byte *buf; |
98aa84af AM |
11144 | long insn; |
11145 | valueT value; | |
ed6fb7bd | 11146 | static int previous_fx_r_type = 0; |
252b5132 | 11147 | |
65551fa4 CD |
11148 | /* FIXME: Maybe just return for all reloc types not listed below? |
11149 | Eric Christopher says: "This is stupid, please rewrite md_apply_fix3. */ | |
11150 | if (fixP->fx_r_type == BFD_RELOC_8) | |
11151 | return; | |
11152 | ||
252b5132 RH |
11153 | assert (fixP->fx_size == 4 |
11154 | || fixP->fx_r_type == BFD_RELOC_16 | |
f6688943 TS |
11155 | || fixP->fx_r_type == BFD_RELOC_32 |
11156 | || fixP->fx_r_type == BFD_RELOC_MIPS_JMP | |
11157 | || fixP->fx_r_type == BFD_RELOC_HI16_S | |
11158 | || fixP->fx_r_type == BFD_RELOC_LO16 | |
11159 | || fixP->fx_r_type == BFD_RELOC_GPREL16 | |
76b3015f | 11160 | || fixP->fx_r_type == BFD_RELOC_MIPS_LITERAL |
f6688943 | 11161 | || fixP->fx_r_type == BFD_RELOC_GPREL32 |
252b5132 | 11162 | || fixP->fx_r_type == BFD_RELOC_64 |
f6688943 TS |
11163 | || fixP->fx_r_type == BFD_RELOC_CTOR |
11164 | || fixP->fx_r_type == BFD_RELOC_MIPS_SUB | |
11165 | || fixP->fx_r_type == BFD_RELOC_MIPS_HIGHEST | |
11166 | || fixP->fx_r_type == BFD_RELOC_MIPS_HIGHER | |
11167 | || fixP->fx_r_type == BFD_RELOC_MIPS_SCN_DISP | |
11168 | || fixP->fx_r_type == BFD_RELOC_MIPS_REL16 | |
11169 | || fixP->fx_r_type == BFD_RELOC_MIPS_RELGOT | |
252b5132 | 11170 | || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
438c16b8 TS |
11171 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY |
11172 | || fixP->fx_r_type == BFD_RELOC_MIPS_JALR); | |
252b5132 | 11173 | |
98d3f06f | 11174 | value = *valP; |
252b5132 RH |
11175 | |
11176 | /* If we aren't adjusting this fixup to be against the section | |
11177 | symbol, we need to adjust the value. */ | |
11178 | #ifdef OBJ_ELF | |
11179 | if (fixP->fx_addsy != NULL && OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
bb2d6cd7 | 11180 | { |
add55e1f | 11181 | if (mips_need_elf_addend_fixup (fixP)) |
98aa84af | 11182 | { |
d6e9d61a | 11183 | reloc_howto_type *howto; |
98aa84af | 11184 | valueT symval = S_GET_VALUE (fixP->fx_addsy); |
94f592af | 11185 | |
98aa84af | 11186 | value -= symval; |
d6e9d61a MR |
11187 | |
11188 | howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type); | |
af6ae2ad | 11189 | if (value != 0 && howto && howto->partial_inplace |
7a49a8c2 | 11190 | && (! fixP->fx_pcrel || howto->pcrel_offset)) |
98aa84af AM |
11191 | { |
11192 | /* In this case, the bfd_install_relocation routine will | |
11193 | incorrectly add the symbol value back in. We just want | |
7a49a8c2 | 11194 | the addend to appear in the object file. |
b34976b6 | 11195 | |
7a49a8c2 L |
11196 | howto->pcrel_offset is added for R_MIPS_PC16, which is |
11197 | generated for code like | |
b34976b6 | 11198 | |
7a49a8c2 L |
11199 | globl g1 .text |
11200 | .text | |
11201 | .space 20 | |
11202 | g1: | |
11203 | x: | |
11204 | bal g1 | |
11205 | */ | |
98aa84af | 11206 | value -= symval; |
7461da6e RS |
11207 | |
11208 | /* Make sure the addend is still non-zero. If it became zero | |
11209 | after the last operation, set it to a spurious value and | |
11210 | subtract the same value from the object file's contents. */ | |
11211 | if (value == 0) | |
11212 | { | |
11213 | value = 8; | |
11214 | ||
11215 | /* The in-place addends for LO16 relocations are signed; | |
11216 | leave the matching HI16 in-place addends as zero. */ | |
11217 | if (fixP->fx_r_type != BFD_RELOC_HI16_S) | |
11218 | { | |
7461da6e RS |
11219 | bfd_vma contents, mask, field; |
11220 | ||
7461da6e RS |
11221 | contents = bfd_get_bits (fixP->fx_frag->fr_literal |
11222 | + fixP->fx_where, | |
11223 | fixP->fx_size * 8, | |
11224 | target_big_endian); | |
11225 | ||
11226 | /* MASK has bits set where the relocation should go. | |
11227 | FIELD is -value, shifted into the appropriate place | |
11228 | for this relocation. */ | |
11229 | mask = 1 << (howto->bitsize - 1); | |
11230 | mask = (((mask - 1) << 1) | 1) << howto->bitpos; | |
11231 | field = (-value >> howto->rightshift) << howto->bitpos; | |
11232 | ||
11233 | bfd_put_bits ((field & mask) | (contents & ~mask), | |
11234 | fixP->fx_frag->fr_literal + fixP->fx_where, | |
11235 | fixP->fx_size * 8, | |
11236 | target_big_endian); | |
11237 | } | |
11238 | } | |
98aa84af AM |
11239 | } |
11240 | } | |
252b5132 | 11241 | |
bb2d6cd7 GK |
11242 | /* This code was generated using trial and error and so is |
11243 | fragile and not trustworthy. If you change it, you should | |
11244 | rerun the elf-rel, elf-rel2, and empic testcases and ensure | |
11245 | they still pass. */ | |
11246 | if (fixP->fx_pcrel || fixP->fx_subsy != NULL) | |
11247 | { | |
11248 | value += fixP->fx_frag->fr_address + fixP->fx_where; | |
11249 | ||
11250 | /* BFD's REL handling, for MIPS, is _very_ weird. | |
11251 | This gives the right results, but it can't possibly | |
11252 | be the way things are supposed to work. */ | |
0b25d3e6 | 11253 | if (fixP->fx_r_type != BFD_RELOC_16_PCREL_S2 |
bb2d6cd7 GK |
11254 | || S_GET_SEGMENT (fixP->fx_addsy) != undefined_section) |
11255 | value += fixP->fx_frag->fr_address + fixP->fx_where; | |
11256 | } | |
11257 | } | |
11258 | #endif | |
252b5132 | 11259 | |
94f592af | 11260 | fixP->fx_addnumber = value; /* Remember value for tc_gen_reloc. */ |
252b5132 | 11261 | |
ed6fb7bd SC |
11262 | /* We are not done if this is a composite relocation to set up gp. */ |
11263 | if (fixP->fx_addsy == NULL && ! fixP->fx_pcrel | |
11264 | && !(fixP->fx_r_type == BFD_RELOC_MIPS_SUB | |
10181a0d AO |
11265 | || (fixP->fx_r_type == BFD_RELOC_64 |
11266 | && (previous_fx_r_type == BFD_RELOC_GPREL32 | |
11267 | || previous_fx_r_type == BFD_RELOC_GPREL16)) | |
ed6fb7bd SC |
11268 | || (previous_fx_r_type == BFD_RELOC_MIPS_SUB |
11269 | && (fixP->fx_r_type == BFD_RELOC_HI16_S | |
11270 | || fixP->fx_r_type == BFD_RELOC_LO16)))) | |
252b5132 | 11271 | fixP->fx_done = 1; |
ed6fb7bd | 11272 | previous_fx_r_type = fixP->fx_r_type; |
252b5132 RH |
11273 | |
11274 | switch (fixP->fx_r_type) | |
11275 | { | |
11276 | case BFD_RELOC_MIPS_JMP: | |
e369bcce TS |
11277 | case BFD_RELOC_MIPS_SHIFT5: |
11278 | case BFD_RELOC_MIPS_SHIFT6: | |
11279 | case BFD_RELOC_MIPS_GOT_DISP: | |
11280 | case BFD_RELOC_MIPS_GOT_PAGE: | |
11281 | case BFD_RELOC_MIPS_GOT_OFST: | |
11282 | case BFD_RELOC_MIPS_SUB: | |
11283 | case BFD_RELOC_MIPS_INSERT_A: | |
11284 | case BFD_RELOC_MIPS_INSERT_B: | |
11285 | case BFD_RELOC_MIPS_DELETE: | |
11286 | case BFD_RELOC_MIPS_HIGHEST: | |
11287 | case BFD_RELOC_MIPS_HIGHER: | |
11288 | case BFD_RELOC_MIPS_SCN_DISP: | |
11289 | case BFD_RELOC_MIPS_REL16: | |
11290 | case BFD_RELOC_MIPS_RELGOT: | |
11291 | case BFD_RELOC_MIPS_JALR: | |
252b5132 RH |
11292 | case BFD_RELOC_HI16: |
11293 | case BFD_RELOC_HI16_S: | |
cdf6fd85 | 11294 | case BFD_RELOC_GPREL16: |
252b5132 RH |
11295 | case BFD_RELOC_MIPS_LITERAL: |
11296 | case BFD_RELOC_MIPS_CALL16: | |
11297 | case BFD_RELOC_MIPS_GOT16: | |
cdf6fd85 | 11298 | case BFD_RELOC_GPREL32: |
252b5132 RH |
11299 | case BFD_RELOC_MIPS_GOT_HI16: |
11300 | case BFD_RELOC_MIPS_GOT_LO16: | |
11301 | case BFD_RELOC_MIPS_CALL_HI16: | |
11302 | case BFD_RELOC_MIPS_CALL_LO16: | |
11303 | case BFD_RELOC_MIPS16_GPREL: | |
11304 | if (fixP->fx_pcrel) | |
11305 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11306 | _("Invalid PC relative reloc")); | |
11307 | /* Nothing needed to do. The value comes from the reloc entry */ | |
11308 | break; | |
11309 | ||
11310 | case BFD_RELOC_MIPS16_JMP: | |
11311 | /* We currently always generate a reloc against a symbol, which | |
11312 | means that we don't want an addend even if the symbol is | |
11313 | defined. */ | |
11314 | fixP->fx_addnumber = 0; | |
11315 | break; | |
11316 | ||
11317 | case BFD_RELOC_PCREL_HI16_S: | |
11318 | /* The addend for this is tricky if it is internal, so we just | |
11319 | do everything here rather than in bfd_install_relocation. */ | |
bdaaa2e1 | 11320 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour |
bb2d6cd7 GK |
11321 | && !fixP->fx_done |
11322 | && value != 0) | |
11323 | break; | |
11324 | if (fixP->fx_addsy | |
11325 | && (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_SECTION_SYM) == 0) | |
252b5132 RH |
11326 | { |
11327 | /* For an external symbol adjust by the address to make it | |
11328 | pcrel_offset. We use the address of the RELLO reloc | |
11329 | which follows this one. */ | |
11330 | value += (fixP->fx_next->fx_frag->fr_address | |
11331 | + fixP->fx_next->fx_where); | |
11332 | } | |
e7d556df | 11333 | value = ((value + 0x8000) >> 16) & 0xffff; |
874e8986 | 11334 | buf = (bfd_byte *) fixP->fx_frag->fr_literal + fixP->fx_where; |
252b5132 RH |
11335 | if (target_big_endian) |
11336 | buf += 2; | |
874e8986 | 11337 | md_number_to_chars ((char *) buf, value, 2); |
252b5132 RH |
11338 | break; |
11339 | ||
11340 | case BFD_RELOC_PCREL_LO16: | |
11341 | /* The addend for this is tricky if it is internal, so we just | |
11342 | do everything here rather than in bfd_install_relocation. */ | |
bdaaa2e1 | 11343 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour |
bb2d6cd7 GK |
11344 | && !fixP->fx_done |
11345 | && value != 0) | |
11346 | break; | |
11347 | if (fixP->fx_addsy | |
11348 | && (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_SECTION_SYM) == 0) | |
252b5132 | 11349 | value += fixP->fx_frag->fr_address + fixP->fx_where; |
874e8986 | 11350 | buf = (bfd_byte *) fixP->fx_frag->fr_literal + fixP->fx_where; |
252b5132 RH |
11351 | if (target_big_endian) |
11352 | buf += 2; | |
874e8986 | 11353 | md_number_to_chars ((char *) buf, value, 2); |
252b5132 RH |
11354 | break; |
11355 | ||
11356 | case BFD_RELOC_64: | |
11357 | /* This is handled like BFD_RELOC_32, but we output a sign | |
11358 | extended value if we are only 32 bits. */ | |
11359 | if (fixP->fx_done | |
11360 | || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP))) | |
11361 | { | |
11362 | if (8 <= sizeof (valueT)) | |
11363 | md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where, | |
11364 | value, 8); | |
11365 | else | |
11366 | { | |
11367 | long w1, w2; | |
11368 | long hiv; | |
11369 | ||
11370 | w1 = w2 = fixP->fx_where; | |
11371 | if (target_big_endian) | |
11372 | w1 += 4; | |
11373 | else | |
11374 | w2 += 4; | |
11375 | md_number_to_chars (fixP->fx_frag->fr_literal + w1, value, 4); | |
11376 | if ((value & 0x80000000) != 0) | |
11377 | hiv = 0xffffffff; | |
11378 | else | |
11379 | hiv = 0; | |
11380 | md_number_to_chars (fixP->fx_frag->fr_literal + w2, hiv, 4); | |
11381 | } | |
11382 | } | |
11383 | break; | |
11384 | ||
056350c6 | 11385 | case BFD_RELOC_RVA: |
252b5132 RH |
11386 | case BFD_RELOC_32: |
11387 | /* If we are deleting this reloc entry, we must fill in the | |
11388 | value now. This can happen if we have a .word which is not | |
11389 | resolved when it appears but is later defined. We also need | |
11390 | to fill in the value if this is an embedded PIC switch table | |
11391 | entry. */ | |
11392 | if (fixP->fx_done | |
11393 | || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP))) | |
11394 | md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where, | |
11395 | value, 4); | |
11396 | break; | |
11397 | ||
11398 | case BFD_RELOC_16: | |
11399 | /* If we are deleting this reloc entry, we must fill in the | |
11400 | value now. */ | |
11401 | assert (fixP->fx_size == 2); | |
11402 | if (fixP->fx_done) | |
11403 | md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where, | |
11404 | value, 2); | |
11405 | break; | |
11406 | ||
11407 | case BFD_RELOC_LO16: | |
11408 | /* When handling an embedded PIC switch statement, we can wind | |
11409 | up deleting a LO16 reloc. See the 'o' case in mips_ip. */ | |
11410 | if (fixP->fx_done) | |
11411 | { | |
98aa84af | 11412 | if (value + 0x8000 > 0xffff) |
252b5132 RH |
11413 | as_bad_where (fixP->fx_file, fixP->fx_line, |
11414 | _("relocation overflow")); | |
874e8986 | 11415 | buf = (bfd_byte *) fixP->fx_frag->fr_literal + fixP->fx_where; |
252b5132 RH |
11416 | if (target_big_endian) |
11417 | buf += 2; | |
874e8986 | 11418 | md_number_to_chars ((char *) buf, value, 2); |
252b5132 RH |
11419 | } |
11420 | break; | |
11421 | ||
11422 | case BFD_RELOC_16_PCREL_S2: | |
cb56d3d3 TS |
11423 | if ((value & 0x3) != 0) |
11424 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
0b25d3e6 | 11425 | _("Branch to odd address (%lx)"), (long) value); |
cb56d3d3 | 11426 | |
252b5132 RH |
11427 | /* |
11428 | * We need to save the bits in the instruction since fixup_segment() | |
11429 | * might be deleting the relocation entry (i.e., a branch within | |
11430 | * the current segment). | |
11431 | */ | |
af6ae2ad | 11432 | if (!fixP->fx_done && (value != 0 || HAVE_NEWABI)) |
bb2d6cd7 GK |
11433 | break; |
11434 | /* If 'value' is zero, the remaining reloc code won't actually | |
11435 | do the store, so it must be done here. This is probably | |
11436 | a bug somewhere. */ | |
b25a253c | 11437 | if (!fixP->fx_done |
0b25d3e6 AO |
11438 | && (fixP->fx_r_type != BFD_RELOC_16_PCREL_S2 |
11439 | || fixP->fx_addsy == NULL /* ??? */ | |
b25a253c | 11440 | || ! S_IS_DEFINED (fixP->fx_addsy))) |
bb2d6cd7 | 11441 | value -= fixP->fx_frag->fr_address + fixP->fx_where; |
bdaaa2e1 | 11442 | |
98aa84af | 11443 | value = (offsetT) value >> 2; |
252b5132 RH |
11444 | |
11445 | /* update old instruction data */ | |
874e8986 | 11446 | buf = (bfd_byte *) (fixP->fx_where + fixP->fx_frag->fr_literal); |
252b5132 RH |
11447 | if (target_big_endian) |
11448 | insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3]; | |
11449 | else | |
11450 | insn = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0]; | |
11451 | ||
98aa84af | 11452 | if (value + 0x8000 <= 0xffff) |
252b5132 RH |
11453 | insn |= value & 0xffff; |
11454 | else | |
11455 | { | |
11456 | /* The branch offset is too large. If this is an | |
11457 | unconditional branch, and we are not generating PIC code, | |
11458 | we can convert it to an absolute jump instruction. */ | |
11459 | if (mips_pic == NO_PIC | |
11460 | && fixP->fx_done | |
11461 | && fixP->fx_frag->fr_address >= text_section->vma | |
11462 | && (fixP->fx_frag->fr_address | |
11463 | < text_section->vma + text_section->_raw_size) | |
11464 | && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */ | |
11465 | || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */ | |
11466 | || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */ | |
11467 | { | |
11468 | if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */ | |
11469 | insn = 0x0c000000; /* jal */ | |
11470 | else | |
11471 | insn = 0x08000000; /* j */ | |
11472 | fixP->fx_r_type = BFD_RELOC_MIPS_JMP; | |
11473 | fixP->fx_done = 0; | |
11474 | fixP->fx_addsy = section_symbol (text_section); | |
11475 | fixP->fx_addnumber = (value << 2) + md_pcrel_from (fixP); | |
11476 | } | |
11477 | else | |
11478 | { | |
4a6a3df4 AO |
11479 | /* If we got here, we have branch-relaxation disabled, |
11480 | and there's nothing we can do to fix this instruction | |
11481 | without turning it into a longer sequence. */ | |
252b5132 RH |
11482 | as_bad_where (fixP->fx_file, fixP->fx_line, |
11483 | _("Branch out of range")); | |
11484 | } | |
11485 | } | |
11486 | ||
11487 | md_number_to_chars ((char *) buf, (valueT) insn, 4); | |
11488 | break; | |
11489 | ||
11490 | case BFD_RELOC_VTABLE_INHERIT: | |
11491 | fixP->fx_done = 0; | |
11492 | if (fixP->fx_addsy | |
11493 | && !S_IS_DEFINED (fixP->fx_addsy) | |
11494 | && !S_IS_WEAK (fixP->fx_addsy)) | |
11495 | S_SET_WEAK (fixP->fx_addsy); | |
11496 | break; | |
11497 | ||
11498 | case BFD_RELOC_VTABLE_ENTRY: | |
11499 | fixP->fx_done = 0; | |
11500 | break; | |
11501 | ||
11502 | default: | |
11503 | internalError (); | |
11504 | } | |
252b5132 RH |
11505 | } |
11506 | ||
11507 | #if 0 | |
11508 | void | |
11509 | printInsn (oc) | |
11510 | unsigned long oc; | |
11511 | { | |
11512 | const struct mips_opcode *p; | |
11513 | int treg, sreg, dreg, shamt; | |
11514 | short imm; | |
11515 | const char *args; | |
11516 | int i; | |
11517 | ||
11518 | for (i = 0; i < NUMOPCODES; ++i) | |
11519 | { | |
11520 | p = &mips_opcodes[i]; | |
11521 | if (((oc & p->mask) == p->match) && (p->pinfo != INSN_MACRO)) | |
11522 | { | |
11523 | printf ("%08lx %s\t", oc, p->name); | |
11524 | treg = (oc >> 16) & 0x1f; | |
11525 | sreg = (oc >> 21) & 0x1f; | |
11526 | dreg = (oc >> 11) & 0x1f; | |
11527 | shamt = (oc >> 6) & 0x1f; | |
11528 | imm = oc; | |
11529 | for (args = p->args;; ++args) | |
11530 | { | |
11531 | switch (*args) | |
11532 | { | |
11533 | case '\0': | |
11534 | printf ("\n"); | |
11535 | break; | |
11536 | ||
11537 | case ',': | |
11538 | case '(': | |
11539 | case ')': | |
11540 | printf ("%c", *args); | |
11541 | continue; | |
11542 | ||
11543 | case 'r': | |
11544 | assert (treg == sreg); | |
11545 | printf ("$%d,$%d", treg, sreg); | |
11546 | continue; | |
11547 | ||
11548 | case 'd': | |
11549 | case 'G': | |
11550 | printf ("$%d", dreg); | |
11551 | continue; | |
11552 | ||
11553 | case 't': | |
11554 | case 'E': | |
11555 | printf ("$%d", treg); | |
11556 | continue; | |
11557 | ||
11558 | case 'k': | |
11559 | printf ("0x%x", treg); | |
11560 | continue; | |
11561 | ||
11562 | case 'b': | |
11563 | case 's': | |
11564 | printf ("$%d", sreg); | |
11565 | continue; | |
11566 | ||
11567 | case 'a': | |
11568 | printf ("0x%08lx", oc & 0x1ffffff); | |
11569 | continue; | |
11570 | ||
11571 | case 'i': | |
11572 | case 'j': | |
11573 | case 'o': | |
11574 | case 'u': | |
11575 | printf ("%d", imm); | |
11576 | continue; | |
11577 | ||
11578 | case '<': | |
11579 | case '>': | |
11580 | printf ("$%d", shamt); | |
11581 | continue; | |
11582 | ||
11583 | default: | |
11584 | internalError (); | |
11585 | } | |
11586 | break; | |
11587 | } | |
11588 | return; | |
11589 | } | |
11590 | } | |
11591 | printf (_("%08lx UNDEFINED\n"), oc); | |
11592 | } | |
11593 | #endif | |
11594 | ||
11595 | static symbolS * | |
11596 | get_symbol () | |
11597 | { | |
11598 | int c; | |
11599 | char *name; | |
11600 | symbolS *p; | |
11601 | ||
11602 | name = input_line_pointer; | |
11603 | c = get_symbol_end (); | |
11604 | p = (symbolS *) symbol_find_or_make (name); | |
11605 | *input_line_pointer = c; | |
11606 | return p; | |
11607 | } | |
11608 | ||
11609 | /* Align the current frag to a given power of two. The MIPS assembler | |
11610 | also automatically adjusts any preceding label. */ | |
11611 | ||
11612 | static void | |
11613 | mips_align (to, fill, label) | |
11614 | int to; | |
11615 | int fill; | |
11616 | symbolS *label; | |
11617 | { | |
b34976b6 | 11618 | mips_emit_delays (FALSE); |
252b5132 RH |
11619 | frag_align (to, fill, 0); |
11620 | record_alignment (now_seg, to); | |
11621 | if (label != NULL) | |
11622 | { | |
11623 | assert (S_GET_SEGMENT (label) == now_seg); | |
49309057 | 11624 | symbol_set_frag (label, frag_now); |
252b5132 RH |
11625 | S_SET_VALUE (label, (valueT) frag_now_fix ()); |
11626 | } | |
11627 | } | |
11628 | ||
11629 | /* Align to a given power of two. .align 0 turns off the automatic | |
11630 | alignment used by the data creating pseudo-ops. */ | |
11631 | ||
11632 | static void | |
11633 | s_align (x) | |
43841e91 | 11634 | int x ATTRIBUTE_UNUSED; |
252b5132 RH |
11635 | { |
11636 | register int temp; | |
11637 | register long temp_fill; | |
11638 | long max_alignment = 15; | |
11639 | ||
11640 | /* | |
11641 | ||
11642 | o Note that the assembler pulls down any immediately preceeding label | |
11643 | to the aligned address. | |
11644 | o It's not documented but auto alignment is reinstated by | |
11645 | a .align pseudo instruction. | |
11646 | o Note also that after auto alignment is turned off the mips assembler | |
11647 | issues an error on attempt to assemble an improperly aligned data item. | |
11648 | We don't. | |
11649 | ||
11650 | */ | |
11651 | ||
11652 | temp = get_absolute_expression (); | |
11653 | if (temp > max_alignment) | |
11654 | as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment); | |
11655 | else if (temp < 0) | |
11656 | { | |
11657 | as_warn (_("Alignment negative: 0 assumed.")); | |
11658 | temp = 0; | |
11659 | } | |
11660 | if (*input_line_pointer == ',') | |
11661 | { | |
f9419b05 | 11662 | ++input_line_pointer; |
252b5132 RH |
11663 | temp_fill = get_absolute_expression (); |
11664 | } | |
11665 | else | |
11666 | temp_fill = 0; | |
11667 | if (temp) | |
11668 | { | |
11669 | auto_align = 1; | |
11670 | mips_align (temp, (int) temp_fill, | |
11671 | insn_labels != NULL ? insn_labels->label : NULL); | |
11672 | } | |
11673 | else | |
11674 | { | |
11675 | auto_align = 0; | |
11676 | } | |
11677 | ||
11678 | demand_empty_rest_of_line (); | |
11679 | } | |
11680 | ||
11681 | void | |
11682 | mips_flush_pending_output () | |
11683 | { | |
b34976b6 | 11684 | mips_emit_delays (FALSE); |
252b5132 RH |
11685 | mips_clear_insn_labels (); |
11686 | } | |
11687 | ||
11688 | static void | |
11689 | s_change_sec (sec) | |
11690 | int sec; | |
11691 | { | |
11692 | segT seg; | |
11693 | ||
11694 | /* When generating embedded PIC code, we only use the .text, .lit8, | |
11695 | .sdata and .sbss sections. We change the .data and .rdata | |
11696 | pseudo-ops to use .sdata. */ | |
11697 | if (mips_pic == EMBEDDED_PIC | |
11698 | && (sec == 'd' || sec == 'r')) | |
11699 | sec = 's'; | |
11700 | ||
11701 | #ifdef OBJ_ELF | |
11702 | /* The ELF backend needs to know that we are changing sections, so | |
11703 | that .previous works correctly. We could do something like check | |
b6ff326e | 11704 | for an obj_section_change_hook macro, but that might be confusing |
252b5132 RH |
11705 | as it would not be appropriate to use it in the section changing |
11706 | functions in read.c, since obj-elf.c intercepts those. FIXME: | |
11707 | This should be cleaner, somehow. */ | |
11708 | obj_elf_section_change_hook (); | |
11709 | #endif | |
11710 | ||
b34976b6 | 11711 | mips_emit_delays (FALSE); |
252b5132 RH |
11712 | switch (sec) |
11713 | { | |
11714 | case 't': | |
11715 | s_text (0); | |
11716 | break; | |
11717 | case 'd': | |
11718 | s_data (0); | |
11719 | break; | |
11720 | case 'b': | |
11721 | subseg_set (bss_section, (subsegT) get_absolute_expression ()); | |
11722 | demand_empty_rest_of_line (); | |
11723 | break; | |
11724 | ||
11725 | case 'r': | |
11726 | if (USE_GLOBAL_POINTER_OPT) | |
11727 | { | |
11728 | seg = subseg_new (RDATA_SECTION_NAME, | |
11729 | (subsegT) get_absolute_expression ()); | |
11730 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
11731 | { | |
11732 | bfd_set_section_flags (stdoutput, seg, | |
11733 | (SEC_ALLOC | |
11734 | | SEC_LOAD | |
11735 | | SEC_READONLY | |
11736 | | SEC_RELOC | |
11737 | | SEC_DATA)); | |
11738 | if (strcmp (TARGET_OS, "elf") != 0) | |
e799a695 | 11739 | record_alignment (seg, 4); |
252b5132 RH |
11740 | } |
11741 | demand_empty_rest_of_line (); | |
11742 | } | |
11743 | else | |
11744 | { | |
11745 | as_bad (_("No read only data section in this object file format")); | |
11746 | demand_empty_rest_of_line (); | |
11747 | return; | |
11748 | } | |
11749 | break; | |
11750 | ||
11751 | case 's': | |
11752 | if (USE_GLOBAL_POINTER_OPT) | |
11753 | { | |
11754 | seg = subseg_new (".sdata", (subsegT) get_absolute_expression ()); | |
11755 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
11756 | { | |
11757 | bfd_set_section_flags (stdoutput, seg, | |
11758 | SEC_ALLOC | SEC_LOAD | SEC_RELOC | |
11759 | | SEC_DATA); | |
11760 | if (strcmp (TARGET_OS, "elf") != 0) | |
e799a695 | 11761 | record_alignment (seg, 4); |
252b5132 RH |
11762 | } |
11763 | demand_empty_rest_of_line (); | |
11764 | break; | |
11765 | } | |
11766 | else | |
11767 | { | |
11768 | as_bad (_("Global pointers not supported; recompile -G 0")); | |
11769 | demand_empty_rest_of_line (); | |
11770 | return; | |
11771 | } | |
11772 | } | |
11773 | ||
11774 | auto_align = 1; | |
11775 | } | |
b34976b6 | 11776 | |
cca86cc8 SC |
11777 | void |
11778 | s_change_section (ignore) | |
11779 | int ignore ATTRIBUTE_UNUSED; | |
11780 | { | |
7ed4a06a | 11781 | #ifdef OBJ_ELF |
cca86cc8 SC |
11782 | char *section_name; |
11783 | char c; | |
4cf0dd0d | 11784 | char next_c; |
cca86cc8 SC |
11785 | int section_type; |
11786 | int section_flag; | |
11787 | int section_entry_size; | |
11788 | int section_alignment; | |
b34976b6 | 11789 | |
7ed4a06a TS |
11790 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
11791 | return; | |
11792 | ||
cca86cc8 SC |
11793 | section_name = input_line_pointer; |
11794 | c = get_symbol_end (); | |
a816d1ed AO |
11795 | if (c) |
11796 | next_c = *(input_line_pointer + 1); | |
cca86cc8 | 11797 | |
4cf0dd0d TS |
11798 | /* Do we have .section Name<,"flags">? */ |
11799 | if (c != ',' || (c == ',' && next_c == '"')) | |
cca86cc8 | 11800 | { |
4cf0dd0d TS |
11801 | /* just after name is now '\0'. */ |
11802 | *input_line_pointer = c; | |
cca86cc8 SC |
11803 | input_line_pointer = section_name; |
11804 | obj_elf_section (ignore); | |
11805 | return; | |
11806 | } | |
11807 | input_line_pointer++; | |
11808 | ||
11809 | /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */ | |
11810 | if (c == ',') | |
11811 | section_type = get_absolute_expression (); | |
11812 | else | |
11813 | section_type = 0; | |
11814 | if (*input_line_pointer++ == ',') | |
11815 | section_flag = get_absolute_expression (); | |
11816 | else | |
11817 | section_flag = 0; | |
11818 | if (*input_line_pointer++ == ',') | |
11819 | section_entry_size = get_absolute_expression (); | |
11820 | else | |
11821 | section_entry_size = 0; | |
11822 | if (*input_line_pointer++ == ',') | |
11823 | section_alignment = get_absolute_expression (); | |
11824 | else | |
11825 | section_alignment = 0; | |
11826 | ||
a816d1ed AO |
11827 | section_name = xstrdup (section_name); |
11828 | ||
cca86cc8 SC |
11829 | obj_elf_change_section (section_name, section_type, section_flag, |
11830 | section_entry_size, 0, 0, 0); | |
a816d1ed AO |
11831 | |
11832 | if (now_seg->name != section_name) | |
11833 | free (section_name); | |
7ed4a06a | 11834 | #endif /* OBJ_ELF */ |
cca86cc8 | 11835 | } |
252b5132 RH |
11836 | |
11837 | void | |
11838 | mips_enable_auto_align () | |
11839 | { | |
11840 | auto_align = 1; | |
11841 | } | |
11842 | ||
11843 | static void | |
11844 | s_cons (log_size) | |
11845 | int log_size; | |
11846 | { | |
11847 | symbolS *label; | |
11848 | ||
11849 | label = insn_labels != NULL ? insn_labels->label : NULL; | |
b34976b6 | 11850 | mips_emit_delays (FALSE); |
252b5132 RH |
11851 | if (log_size > 0 && auto_align) |
11852 | mips_align (log_size, 0, label); | |
11853 | mips_clear_insn_labels (); | |
11854 | cons (1 << log_size); | |
11855 | } | |
11856 | ||
11857 | static void | |
11858 | s_float_cons (type) | |
11859 | int type; | |
11860 | { | |
11861 | symbolS *label; | |
11862 | ||
11863 | label = insn_labels != NULL ? insn_labels->label : NULL; | |
11864 | ||
b34976b6 | 11865 | mips_emit_delays (FALSE); |
252b5132 RH |
11866 | |
11867 | if (auto_align) | |
49309057 ILT |
11868 | { |
11869 | if (type == 'd') | |
11870 | mips_align (3, 0, label); | |
11871 | else | |
11872 | mips_align (2, 0, label); | |
11873 | } | |
252b5132 RH |
11874 | |
11875 | mips_clear_insn_labels (); | |
11876 | ||
11877 | float_cons (type); | |
11878 | } | |
11879 | ||
11880 | /* Handle .globl. We need to override it because on Irix 5 you are | |
11881 | permitted to say | |
11882 | .globl foo .text | |
11883 | where foo is an undefined symbol, to mean that foo should be | |
11884 | considered to be the address of a function. */ | |
11885 | ||
11886 | static void | |
11887 | s_mips_globl (x) | |
43841e91 | 11888 | int x ATTRIBUTE_UNUSED; |
252b5132 RH |
11889 | { |
11890 | char *name; | |
11891 | int c; | |
11892 | symbolS *symbolP; | |
11893 | flagword flag; | |
11894 | ||
11895 | name = input_line_pointer; | |
11896 | c = get_symbol_end (); | |
11897 | symbolP = symbol_find_or_make (name); | |
11898 | *input_line_pointer = c; | |
11899 | SKIP_WHITESPACE (); | |
11900 | ||
11901 | /* On Irix 5, every global symbol that is not explicitly labelled as | |
11902 | being a function is apparently labelled as being an object. */ | |
11903 | flag = BSF_OBJECT; | |
11904 | ||
11905 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
11906 | { | |
11907 | char *secname; | |
11908 | asection *sec; | |
11909 | ||
11910 | secname = input_line_pointer; | |
11911 | c = get_symbol_end (); | |
11912 | sec = bfd_get_section_by_name (stdoutput, secname); | |
11913 | if (sec == NULL) | |
11914 | as_bad (_("%s: no such section"), secname); | |
11915 | *input_line_pointer = c; | |
11916 | ||
11917 | if (sec != NULL && (sec->flags & SEC_CODE) != 0) | |
11918 | flag = BSF_FUNCTION; | |
11919 | } | |
11920 | ||
49309057 | 11921 | symbol_get_bfdsym (symbolP)->flags |= flag; |
252b5132 RH |
11922 | |
11923 | S_SET_EXTERNAL (symbolP); | |
11924 | demand_empty_rest_of_line (); | |
11925 | } | |
11926 | ||
11927 | static void | |
11928 | s_option (x) | |
43841e91 | 11929 | int x ATTRIBUTE_UNUSED; |
252b5132 RH |
11930 | { |
11931 | char *opt; | |
11932 | char c; | |
11933 | ||
11934 | opt = input_line_pointer; | |
11935 | c = get_symbol_end (); | |
11936 | ||
11937 | if (*opt == 'O') | |
11938 | { | |
11939 | /* FIXME: What does this mean? */ | |
11940 | } | |
11941 | else if (strncmp (opt, "pic", 3) == 0) | |
11942 | { | |
11943 | int i; | |
11944 | ||
11945 | i = atoi (opt + 3); | |
11946 | if (i == 0) | |
11947 | mips_pic = NO_PIC; | |
11948 | else if (i == 2) | |
11949 | mips_pic = SVR4_PIC; | |
11950 | else | |
11951 | as_bad (_(".option pic%d not supported"), i); | |
11952 | ||
11953 | if (USE_GLOBAL_POINTER_OPT && mips_pic == SVR4_PIC) | |
11954 | { | |
11955 | if (g_switch_seen && g_switch_value != 0) | |
11956 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
11957 | g_switch_value = 0; | |
11958 | bfd_set_gp_size (stdoutput, 0); | |
11959 | } | |
11960 | } | |
11961 | else | |
11962 | as_warn (_("Unrecognized option \"%s\""), opt); | |
11963 | ||
11964 | *input_line_pointer = c; | |
11965 | demand_empty_rest_of_line (); | |
11966 | } | |
11967 | ||
11968 | /* This structure is used to hold a stack of .set values. */ | |
11969 | ||
e972090a NC |
11970 | struct mips_option_stack |
11971 | { | |
252b5132 RH |
11972 | struct mips_option_stack *next; |
11973 | struct mips_set_options options; | |
11974 | }; | |
11975 | ||
11976 | static struct mips_option_stack *mips_opts_stack; | |
11977 | ||
11978 | /* Handle the .set pseudo-op. */ | |
11979 | ||
11980 | static void | |
11981 | s_mipsset (x) | |
43841e91 | 11982 | int x ATTRIBUTE_UNUSED; |
252b5132 RH |
11983 | { |
11984 | char *name = input_line_pointer, ch; | |
11985 | ||
11986 | while (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
f9419b05 | 11987 | ++input_line_pointer; |
252b5132 RH |
11988 | ch = *input_line_pointer; |
11989 | *input_line_pointer = '\0'; | |
11990 | ||
11991 | if (strcmp (name, "reorder") == 0) | |
11992 | { | |
11993 | if (mips_opts.noreorder && prev_nop_frag != NULL) | |
11994 | { | |
11995 | /* If we still have pending nops, we can discard them. The | |
11996 | usual nop handling will insert any that are still | |
bdaaa2e1 | 11997 | needed. */ |
252b5132 RH |
11998 | prev_nop_frag->fr_fix -= (prev_nop_frag_holds |
11999 | * (mips_opts.mips16 ? 2 : 4)); | |
12000 | prev_nop_frag = NULL; | |
12001 | } | |
12002 | mips_opts.noreorder = 0; | |
12003 | } | |
12004 | else if (strcmp (name, "noreorder") == 0) | |
12005 | { | |
b34976b6 | 12006 | mips_emit_delays (TRUE); |
252b5132 RH |
12007 | mips_opts.noreorder = 1; |
12008 | mips_any_noreorder = 1; | |
12009 | } | |
12010 | else if (strcmp (name, "at") == 0) | |
12011 | { | |
12012 | mips_opts.noat = 0; | |
12013 | } | |
12014 | else if (strcmp (name, "noat") == 0) | |
12015 | { | |
12016 | mips_opts.noat = 1; | |
12017 | } | |
12018 | else if (strcmp (name, "macro") == 0) | |
12019 | { | |
12020 | mips_opts.warn_about_macros = 0; | |
12021 | } | |
12022 | else if (strcmp (name, "nomacro") == 0) | |
12023 | { | |
12024 | if (mips_opts.noreorder == 0) | |
12025 | as_bad (_("`noreorder' must be set before `nomacro'")); | |
12026 | mips_opts.warn_about_macros = 1; | |
12027 | } | |
12028 | else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0) | |
12029 | { | |
12030 | mips_opts.nomove = 0; | |
12031 | } | |
12032 | else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0) | |
12033 | { | |
12034 | mips_opts.nomove = 1; | |
12035 | } | |
12036 | else if (strcmp (name, "bopt") == 0) | |
12037 | { | |
12038 | mips_opts.nobopt = 0; | |
12039 | } | |
12040 | else if (strcmp (name, "nobopt") == 0) | |
12041 | { | |
12042 | mips_opts.nobopt = 1; | |
12043 | } | |
12044 | else if (strcmp (name, "mips16") == 0 | |
12045 | || strcmp (name, "MIPS-16") == 0) | |
12046 | mips_opts.mips16 = 1; | |
12047 | else if (strcmp (name, "nomips16") == 0 | |
12048 | || strcmp (name, "noMIPS-16") == 0) | |
12049 | mips_opts.mips16 = 0; | |
1f25f5d3 CD |
12050 | else if (strcmp (name, "mips3d") == 0) |
12051 | mips_opts.ase_mips3d = 1; | |
12052 | else if (strcmp (name, "nomips3d") == 0) | |
12053 | mips_opts.ase_mips3d = 0; | |
a4672219 TS |
12054 | else if (strcmp (name, "mdmx") == 0) |
12055 | mips_opts.ase_mdmx = 1; | |
12056 | else if (strcmp (name, "nomdmx") == 0) | |
12057 | mips_opts.ase_mdmx = 0; | |
252b5132 RH |
12058 | else if (strncmp (name, "mips", 4) == 0) |
12059 | { | |
af7ee8bf | 12060 | int reset = 0; |
252b5132 RH |
12061 | |
12062 | /* Permit the user to change the ISA on the fly. Needless to | |
12063 | say, misuse can cause serious problems. */ | |
af7ee8bf CD |
12064 | if (strcmp (name, "mips0") == 0) |
12065 | { | |
12066 | reset = 1; | |
12067 | mips_opts.isa = file_mips_isa; | |
12068 | } | |
12069 | else if (strcmp (name, "mips1") == 0) | |
12070 | mips_opts.isa = ISA_MIPS1; | |
12071 | else if (strcmp (name, "mips2") == 0) | |
12072 | mips_opts.isa = ISA_MIPS2; | |
12073 | else if (strcmp (name, "mips3") == 0) | |
12074 | mips_opts.isa = ISA_MIPS3; | |
12075 | else if (strcmp (name, "mips4") == 0) | |
12076 | mips_opts.isa = ISA_MIPS4; | |
12077 | else if (strcmp (name, "mips5") == 0) | |
12078 | mips_opts.isa = ISA_MIPS5; | |
12079 | else if (strcmp (name, "mips32") == 0) | |
12080 | mips_opts.isa = ISA_MIPS32; | |
12081 | else if (strcmp (name, "mips32r2") == 0) | |
12082 | mips_opts.isa = ISA_MIPS32R2; | |
12083 | else if (strcmp (name, "mips64") == 0) | |
12084 | mips_opts.isa = ISA_MIPS64; | |
12085 | else | |
12086 | as_bad (_("unknown ISA level %s"), name + 4); | |
12087 | ||
12088 | switch (mips_opts.isa) | |
98d3f06f KH |
12089 | { |
12090 | case 0: | |
98d3f06f | 12091 | break; |
af7ee8bf CD |
12092 | case ISA_MIPS1: |
12093 | case ISA_MIPS2: | |
12094 | case ISA_MIPS32: | |
12095 | case ISA_MIPS32R2: | |
98d3f06f KH |
12096 | mips_opts.gp32 = 1; |
12097 | mips_opts.fp32 = 1; | |
12098 | break; | |
af7ee8bf CD |
12099 | case ISA_MIPS3: |
12100 | case ISA_MIPS4: | |
12101 | case ISA_MIPS5: | |
12102 | case ISA_MIPS64: | |
98d3f06f KH |
12103 | mips_opts.gp32 = 0; |
12104 | mips_opts.fp32 = 0; | |
12105 | break; | |
12106 | default: | |
12107 | as_bad (_("unknown ISA level %s"), name + 4); | |
12108 | break; | |
12109 | } | |
af7ee8bf | 12110 | if (reset) |
98d3f06f | 12111 | { |
af7ee8bf CD |
12112 | mips_opts.gp32 = file_mips_gp32; |
12113 | mips_opts.fp32 = file_mips_fp32; | |
98d3f06f | 12114 | } |
252b5132 RH |
12115 | } |
12116 | else if (strcmp (name, "autoextend") == 0) | |
12117 | mips_opts.noautoextend = 0; | |
12118 | else if (strcmp (name, "noautoextend") == 0) | |
12119 | mips_opts.noautoextend = 1; | |
12120 | else if (strcmp (name, "push") == 0) | |
12121 | { | |
12122 | struct mips_option_stack *s; | |
12123 | ||
12124 | s = (struct mips_option_stack *) xmalloc (sizeof *s); | |
12125 | s->next = mips_opts_stack; | |
12126 | s->options = mips_opts; | |
12127 | mips_opts_stack = s; | |
12128 | } | |
12129 | else if (strcmp (name, "pop") == 0) | |
12130 | { | |
12131 | struct mips_option_stack *s; | |
12132 | ||
12133 | s = mips_opts_stack; | |
12134 | if (s == NULL) | |
12135 | as_bad (_(".set pop with no .set push")); | |
12136 | else | |
12137 | { | |
12138 | /* If we're changing the reorder mode we need to handle | |
12139 | delay slots correctly. */ | |
12140 | if (s->options.noreorder && ! mips_opts.noreorder) | |
b34976b6 | 12141 | mips_emit_delays (TRUE); |
252b5132 RH |
12142 | else if (! s->options.noreorder && mips_opts.noreorder) |
12143 | { | |
12144 | if (prev_nop_frag != NULL) | |
12145 | { | |
12146 | prev_nop_frag->fr_fix -= (prev_nop_frag_holds | |
12147 | * (mips_opts.mips16 ? 2 : 4)); | |
12148 | prev_nop_frag = NULL; | |
12149 | } | |
12150 | } | |
12151 | ||
12152 | mips_opts = s->options; | |
12153 | mips_opts_stack = s->next; | |
12154 | free (s); | |
12155 | } | |
12156 | } | |
12157 | else | |
12158 | { | |
12159 | as_warn (_("Tried to set unrecognized symbol: %s\n"), name); | |
12160 | } | |
12161 | *input_line_pointer = ch; | |
12162 | demand_empty_rest_of_line (); | |
12163 | } | |
12164 | ||
12165 | /* Handle the .abicalls pseudo-op. I believe this is equivalent to | |
12166 | .option pic2. It means to generate SVR4 PIC calls. */ | |
12167 | ||
12168 | static void | |
12169 | s_abicalls (ignore) | |
43841e91 | 12170 | int ignore ATTRIBUTE_UNUSED; |
252b5132 RH |
12171 | { |
12172 | mips_pic = SVR4_PIC; | |
12173 | if (USE_GLOBAL_POINTER_OPT) | |
12174 | { | |
12175 | if (g_switch_seen && g_switch_value != 0) | |
12176 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
12177 | g_switch_value = 0; | |
12178 | } | |
12179 | bfd_set_gp_size (stdoutput, 0); | |
12180 | demand_empty_rest_of_line (); | |
12181 | } | |
12182 | ||
12183 | /* Handle the .cpload pseudo-op. This is used when generating SVR4 | |
12184 | PIC code. It sets the $gp register for the function based on the | |
12185 | function address, which is in the register named in the argument. | |
12186 | This uses a relocation against _gp_disp, which is handled specially | |
12187 | by the linker. The result is: | |
12188 | lui $gp,%hi(_gp_disp) | |
12189 | addiu $gp,$gp,%lo(_gp_disp) | |
12190 | addu $gp,$gp,.cpload argument | |
12191 | The .cpload argument is normally $25 == $t9. */ | |
12192 | ||
12193 | static void | |
12194 | s_cpload (ignore) | |
43841e91 | 12195 | int ignore ATTRIBUTE_UNUSED; |
252b5132 RH |
12196 | { |
12197 | expressionS ex; | |
12198 | int icnt = 0; | |
12199 | ||
6478892d TS |
12200 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
12201 | .cpload is ignored. */ | |
12202 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) | |
252b5132 RH |
12203 | { |
12204 | s_ignore (0); | |
12205 | return; | |
12206 | } | |
12207 | ||
d3ecfc59 | 12208 | /* .cpload should be in a .set noreorder section. */ |
252b5132 RH |
12209 | if (mips_opts.noreorder == 0) |
12210 | as_warn (_(".cpload not in noreorder section")); | |
12211 | ||
12212 | ex.X_op = O_symbol; | |
12213 | ex.X_add_symbol = symbol_find_or_make ("_gp_disp"); | |
12214 | ex.X_op_symbol = NULL; | |
12215 | ex.X_add_number = 0; | |
12216 | ||
12217 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ | |
49309057 | 12218 | symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; |
252b5132 | 12219 | |
c9914766 TS |
12220 | macro_build_lui (NULL, &icnt, &ex, mips_gp_register); |
12221 | macro_build ((char *) NULL, &icnt, &ex, "addiu", "t,r,j", | |
12222 | mips_gp_register, mips_gp_register, (int) BFD_RELOC_LO16); | |
252b5132 RH |
12223 | |
12224 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "addu", "d,v,t", | |
c9914766 | 12225 | mips_gp_register, mips_gp_register, tc_get_register (0)); |
252b5132 RH |
12226 | |
12227 | demand_empty_rest_of_line (); | |
12228 | } | |
12229 | ||
6478892d TS |
12230 | /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is: |
12231 | .cpsetup $reg1, offset|$reg2, label | |
12232 | ||
12233 | If offset is given, this results in: | |
12234 | sd $gp, offset($sp) | |
956cd1d6 | 12235 | lui $gp, %hi(%neg(%gp_rel(label))) |
698b7d9d TS |
12236 | addiu $gp, $gp, %lo(%neg(%gp_rel(label))) |
12237 | daddu $gp, $gp, $reg1 | |
6478892d TS |
12238 | |
12239 | If $reg2 is given, this results in: | |
12240 | daddu $reg2, $gp, $0 | |
956cd1d6 | 12241 | lui $gp, %hi(%neg(%gp_rel(label))) |
698b7d9d TS |
12242 | addiu $gp, $gp, %lo(%neg(%gp_rel(label))) |
12243 | daddu $gp, $gp, $reg1 | |
12244 | $reg1 is normally $25 == $t9. */ | |
6478892d TS |
12245 | static void |
12246 | s_cpsetup (ignore) | |
12247 | int ignore ATTRIBUTE_UNUSED; | |
12248 | { | |
12249 | expressionS ex_off; | |
12250 | expressionS ex_sym; | |
12251 | int reg1; | |
12252 | int icnt = 0; | |
f21f8242 | 12253 | char *f; |
6478892d | 12254 | |
8586fc66 | 12255 | /* If we are not generating SVR4 PIC code, .cpsetup is ignored. |
6478892d TS |
12256 | We also need NewABI support. */ |
12257 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
12258 | { | |
12259 | s_ignore (0); | |
12260 | return; | |
12261 | } | |
12262 | ||
12263 | reg1 = tc_get_register (0); | |
12264 | SKIP_WHITESPACE (); | |
12265 | if (*input_line_pointer != ',') | |
12266 | { | |
12267 | as_bad (_("missing argument separator ',' for .cpsetup")); | |
12268 | return; | |
12269 | } | |
12270 | else | |
80245285 | 12271 | ++input_line_pointer; |
6478892d TS |
12272 | SKIP_WHITESPACE (); |
12273 | if (*input_line_pointer == '$') | |
80245285 TS |
12274 | { |
12275 | mips_cpreturn_register = tc_get_register (0); | |
12276 | mips_cpreturn_offset = -1; | |
12277 | } | |
6478892d | 12278 | else |
80245285 TS |
12279 | { |
12280 | mips_cpreturn_offset = get_absolute_expression (); | |
12281 | mips_cpreturn_register = -1; | |
12282 | } | |
6478892d TS |
12283 | SKIP_WHITESPACE (); |
12284 | if (*input_line_pointer != ',') | |
12285 | { | |
12286 | as_bad (_("missing argument separator ',' for .cpsetup")); | |
12287 | return; | |
12288 | } | |
12289 | else | |
f9419b05 | 12290 | ++input_line_pointer; |
6478892d | 12291 | SKIP_WHITESPACE (); |
f21f8242 | 12292 | expression (&ex_sym); |
6478892d TS |
12293 | |
12294 | if (mips_cpreturn_register == -1) | |
12295 | { | |
12296 | ex_off.X_op = O_constant; | |
12297 | ex_off.X_add_symbol = NULL; | |
12298 | ex_off.X_op_symbol = NULL; | |
12299 | ex_off.X_add_number = mips_cpreturn_offset; | |
12300 | ||
12301 | macro_build ((char *) NULL, &icnt, &ex_off, "sd", "t,o(b)", | |
12302 | mips_gp_register, (int) BFD_RELOC_LO16, SP); | |
12303 | } | |
12304 | else | |
12305 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "daddu", | |
12306 | "d,v,t", mips_cpreturn_register, mips_gp_register, 0); | |
12307 | ||
f21f8242 AO |
12308 | /* Ensure there's room for the next two instructions, so that `f' |
12309 | doesn't end up with an address in the wrong frag. */ | |
12310 | frag_grow (8); | |
12311 | f = frag_more (0); | |
6478892d TS |
12312 | macro_build ((char *) NULL, &icnt, &ex_sym, "lui", "t,u", mips_gp_register, |
12313 | (int) BFD_RELOC_GPREL16); | |
f21f8242 AO |
12314 | fix_new (frag_now, f - frag_now->fr_literal, |
12315 | 0, NULL, 0, 0, BFD_RELOC_MIPS_SUB); | |
12316 | fix_new (frag_now, f - frag_now->fr_literal, | |
12317 | 0, NULL, 0, 0, BFD_RELOC_HI16_S); | |
12318 | ||
12319 | f = frag_more (0); | |
6478892d TS |
12320 | macro_build ((char *) NULL, &icnt, &ex_sym, "addiu", "t,r,j", |
12321 | mips_gp_register, mips_gp_register, (int) BFD_RELOC_GPREL16); | |
f21f8242 AO |
12322 | fix_new (frag_now, f - frag_now->fr_literal, |
12323 | 0, NULL, 0, 0, BFD_RELOC_MIPS_SUB); | |
12324 | fix_new (frag_now, f - frag_now->fr_literal, | |
12325 | 0, NULL, 0, 0, BFD_RELOC_LO16); | |
12326 | ||
8586fc66 TS |
12327 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
12328 | HAVE_64BIT_ADDRESSES ? "daddu" : "addu", "d,v,t", | |
12329 | mips_gp_register, mips_gp_register, reg1); | |
6478892d TS |
12330 | |
12331 | demand_empty_rest_of_line (); | |
12332 | } | |
12333 | ||
12334 | static void | |
12335 | s_cplocal (ignore) | |
12336 | int ignore ATTRIBUTE_UNUSED; | |
12337 | { | |
12338 | /* If we are not generating SVR4 PIC code, or if this is not NewABI code, | |
12339 | .cplocal is ignored. */ | |
12340 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
12341 | { | |
12342 | s_ignore (0); | |
12343 | return; | |
12344 | } | |
12345 | ||
12346 | mips_gp_register = tc_get_register (0); | |
85b51719 | 12347 | demand_empty_rest_of_line (); |
6478892d TS |
12348 | } |
12349 | ||
252b5132 RH |
12350 | /* Handle the .cprestore pseudo-op. This stores $gp into a given |
12351 | offset from $sp. The offset is remembered, and after making a PIC | |
12352 | call $gp is restored from that location. */ | |
12353 | ||
12354 | static void | |
12355 | s_cprestore (ignore) | |
43841e91 | 12356 | int ignore ATTRIBUTE_UNUSED; |
252b5132 RH |
12357 | { |
12358 | expressionS ex; | |
12359 | int icnt = 0; | |
12360 | ||
6478892d | 12361 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
c9914766 | 12362 | .cprestore is ignored. */ |
6478892d | 12363 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) |
252b5132 RH |
12364 | { |
12365 | s_ignore (0); | |
12366 | return; | |
12367 | } | |
12368 | ||
12369 | mips_cprestore_offset = get_absolute_expression (); | |
7a621144 | 12370 | mips_cprestore_valid = 1; |
252b5132 RH |
12371 | |
12372 | ex.X_op = O_constant; | |
12373 | ex.X_add_symbol = NULL; | |
12374 | ex.X_op_symbol = NULL; | |
12375 | ex.X_add_number = mips_cprestore_offset; | |
12376 | ||
885add95 CD |
12377 | macro_build_ldst_constoffset ((char *) NULL, &icnt, &ex, |
12378 | HAVE_32BIT_ADDRESSES ? "sw" : "sd", | |
12379 | mips_gp_register, SP); | |
252b5132 RH |
12380 | |
12381 | demand_empty_rest_of_line (); | |
12382 | } | |
12383 | ||
6478892d TS |
12384 | /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset |
12385 | was given in the preceeding .gpsetup, it results in: | |
12386 | ld $gp, offset($sp) | |
76b3015f | 12387 | |
6478892d TS |
12388 | If a register $reg2 was given there, it results in: |
12389 | daddiu $gp, $gp, $reg2 | |
12390 | */ | |
12391 | static void | |
12392 | s_cpreturn (ignore) | |
12393 | int ignore ATTRIBUTE_UNUSED; | |
12394 | { | |
12395 | expressionS ex; | |
12396 | int icnt = 0; | |
12397 | ||
12398 | /* If we are not generating SVR4 PIC code, .cpreturn is ignored. | |
12399 | We also need NewABI support. */ | |
12400 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
12401 | { | |
12402 | s_ignore (0); | |
12403 | return; | |
12404 | } | |
12405 | ||
12406 | if (mips_cpreturn_register == -1) | |
12407 | { | |
12408 | ex.X_op = O_constant; | |
12409 | ex.X_add_symbol = NULL; | |
12410 | ex.X_op_symbol = NULL; | |
12411 | ex.X_add_number = mips_cpreturn_offset; | |
12412 | ||
12413 | macro_build ((char *) NULL, &icnt, &ex, "ld", "t,o(b)", | |
12414 | mips_gp_register, (int) BFD_RELOC_LO16, SP); | |
12415 | } | |
12416 | else | |
12417 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "daddu", | |
12418 | "d,v,t", mips_gp_register, mips_cpreturn_register, 0); | |
12419 | ||
12420 | demand_empty_rest_of_line (); | |
12421 | } | |
12422 | ||
12423 | /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC | |
12424 | code. It sets the offset to use in gp_rel relocations. */ | |
12425 | ||
12426 | static void | |
12427 | s_gpvalue (ignore) | |
12428 | int ignore ATTRIBUTE_UNUSED; | |
12429 | { | |
12430 | /* If we are not generating SVR4 PIC code, .gpvalue is ignored. | |
12431 | We also need NewABI support. */ | |
12432 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
12433 | { | |
12434 | s_ignore (0); | |
12435 | return; | |
12436 | } | |
12437 | ||
def2e0dd | 12438 | mips_gprel_offset = get_absolute_expression (); |
6478892d TS |
12439 | |
12440 | demand_empty_rest_of_line (); | |
12441 | } | |
12442 | ||
252b5132 RH |
12443 | /* Handle the .gpword pseudo-op. This is used when generating PIC |
12444 | code. It generates a 32 bit GP relative reloc. */ | |
12445 | ||
12446 | static void | |
12447 | s_gpword (ignore) | |
43841e91 | 12448 | int ignore ATTRIBUTE_UNUSED; |
252b5132 RH |
12449 | { |
12450 | symbolS *label; | |
12451 | expressionS ex; | |
12452 | char *p; | |
12453 | ||
12454 | /* When not generating PIC code, this is treated as .word. */ | |
12455 | if (mips_pic != SVR4_PIC) | |
12456 | { | |
12457 | s_cons (2); | |
12458 | return; | |
12459 | } | |
12460 | ||
12461 | label = insn_labels != NULL ? insn_labels->label : NULL; | |
b34976b6 | 12462 | mips_emit_delays (TRUE); |
252b5132 RH |
12463 | if (auto_align) |
12464 | mips_align (2, 0, label); | |
12465 | mips_clear_insn_labels (); | |
12466 | ||
12467 | expression (&ex); | |
12468 | ||
12469 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
12470 | { | |
12471 | as_bad (_("Unsupported use of .gpword")); | |
12472 | ignore_rest_of_line (); | |
12473 | } | |
12474 | ||
12475 | p = frag_more (4); | |
12476 | md_number_to_chars (p, (valueT) 0, 4); | |
b34976b6 | 12477 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, |
cdf6fd85 | 12478 | BFD_RELOC_GPREL32); |
252b5132 RH |
12479 | |
12480 | demand_empty_rest_of_line (); | |
12481 | } | |
12482 | ||
10181a0d AO |
12483 | static void |
12484 | s_gpdword (ignore) | |
12485 | int ignore ATTRIBUTE_UNUSED; | |
12486 | { | |
12487 | symbolS *label; | |
12488 | expressionS ex; | |
12489 | char *p; | |
12490 | ||
12491 | /* When not generating PIC code, this is treated as .dword. */ | |
12492 | if (mips_pic != SVR4_PIC) | |
12493 | { | |
12494 | s_cons (3); | |
12495 | return; | |
12496 | } | |
12497 | ||
12498 | label = insn_labels != NULL ? insn_labels->label : NULL; | |
b34976b6 | 12499 | mips_emit_delays (TRUE); |
10181a0d AO |
12500 | if (auto_align) |
12501 | mips_align (3, 0, label); | |
12502 | mips_clear_insn_labels (); | |
12503 | ||
12504 | expression (&ex); | |
12505 | ||
12506 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
12507 | { | |
12508 | as_bad (_("Unsupported use of .gpdword")); | |
12509 | ignore_rest_of_line (); | |
12510 | } | |
12511 | ||
12512 | p = frag_more (8); | |
12513 | md_number_to_chars (p, (valueT) 0, 8); | |
b34976b6 | 12514 | fix_new_exp (frag_now, p - frag_now->fr_literal, 8, &ex, FALSE, |
10181a0d AO |
12515 | BFD_RELOC_GPREL32); |
12516 | ||
12517 | /* GPREL32 composed with 64 gives a 64-bit GP offset. */ | |
12518 | ex.X_op = O_absent; | |
12519 | ex.X_add_symbol = 0; | |
12520 | ex.X_add_number = 0; | |
b34976b6 | 12521 | fix_new_exp (frag_now, p - frag_now->fr_literal, 8, &ex, FALSE, |
10181a0d AO |
12522 | BFD_RELOC_64); |
12523 | ||
12524 | demand_empty_rest_of_line (); | |
12525 | } | |
12526 | ||
252b5132 RH |
12527 | /* Handle the .cpadd pseudo-op. This is used when dealing with switch |
12528 | tables in SVR4 PIC code. */ | |
12529 | ||
12530 | static void | |
12531 | s_cpadd (ignore) | |
43841e91 | 12532 | int ignore ATTRIBUTE_UNUSED; |
252b5132 RH |
12533 | { |
12534 | int icnt = 0; | |
12535 | int reg; | |
12536 | ||
10181a0d AO |
12537 | /* This is ignored when not generating SVR4 PIC code. */ |
12538 | if (mips_pic != SVR4_PIC) | |
252b5132 RH |
12539 | { |
12540 | s_ignore (0); | |
12541 | return; | |
12542 | } | |
12543 | ||
12544 | /* Add $gp to the register named as an argument. */ | |
12545 | reg = tc_get_register (0); | |
12546 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 12547 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
c9914766 | 12548 | "d,v,t", reg, reg, mips_gp_register); |
252b5132 | 12549 | |
bdaaa2e1 | 12550 | demand_empty_rest_of_line (); |
252b5132 RH |
12551 | } |
12552 | ||
12553 | /* Handle the .insn pseudo-op. This marks instruction labels in | |
12554 | mips16 mode. This permits the linker to handle them specially, | |
12555 | such as generating jalx instructions when needed. We also make | |
12556 | them odd for the duration of the assembly, in order to generate the | |
12557 | right sort of code. We will make them even in the adjust_symtab | |
12558 | routine, while leaving them marked. This is convenient for the | |
12559 | debugger and the disassembler. The linker knows to make them odd | |
12560 | again. */ | |
12561 | ||
12562 | static void | |
12563 | s_insn (ignore) | |
43841e91 | 12564 | int ignore ATTRIBUTE_UNUSED; |
252b5132 | 12565 | { |
f9419b05 | 12566 | mips16_mark_labels (); |
252b5132 RH |
12567 | |
12568 | demand_empty_rest_of_line (); | |
12569 | } | |
12570 | ||
12571 | /* Handle a .stabn directive. We need these in order to mark a label | |
12572 | as being a mips16 text label correctly. Sometimes the compiler | |
12573 | will emit a label, followed by a .stabn, and then switch sections. | |
12574 | If the label and .stabn are in mips16 mode, then the label is | |
12575 | really a mips16 text label. */ | |
12576 | ||
12577 | static void | |
12578 | s_mips_stab (type) | |
12579 | int type; | |
12580 | { | |
f9419b05 | 12581 | if (type == 'n') |
252b5132 RH |
12582 | mips16_mark_labels (); |
12583 | ||
12584 | s_stab (type); | |
12585 | } | |
12586 | ||
12587 | /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. | |
12588 | */ | |
12589 | ||
12590 | static void | |
12591 | s_mips_weakext (ignore) | |
43841e91 | 12592 | int ignore ATTRIBUTE_UNUSED; |
252b5132 RH |
12593 | { |
12594 | char *name; | |
12595 | int c; | |
12596 | symbolS *symbolP; | |
12597 | expressionS exp; | |
12598 | ||
12599 | name = input_line_pointer; | |
12600 | c = get_symbol_end (); | |
12601 | symbolP = symbol_find_or_make (name); | |
12602 | S_SET_WEAK (symbolP); | |
12603 | *input_line_pointer = c; | |
12604 | ||
12605 | SKIP_WHITESPACE (); | |
12606 | ||
12607 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
12608 | { | |
12609 | if (S_IS_DEFINED (symbolP)) | |
12610 | { | |
956cd1d6 | 12611 | as_bad ("ignoring attempt to redefine symbol %s", |
252b5132 RH |
12612 | S_GET_NAME (symbolP)); |
12613 | ignore_rest_of_line (); | |
12614 | return; | |
12615 | } | |
bdaaa2e1 | 12616 | |
252b5132 RH |
12617 | if (*input_line_pointer == ',') |
12618 | { | |
12619 | ++input_line_pointer; | |
12620 | SKIP_WHITESPACE (); | |
12621 | } | |
bdaaa2e1 | 12622 | |
252b5132 RH |
12623 | expression (&exp); |
12624 | if (exp.X_op != O_symbol) | |
12625 | { | |
12626 | as_bad ("bad .weakext directive"); | |
98d3f06f | 12627 | ignore_rest_of_line (); |
252b5132 RH |
12628 | return; |
12629 | } | |
49309057 | 12630 | symbol_set_value_expression (symbolP, &exp); |
252b5132 RH |
12631 | } |
12632 | ||
12633 | demand_empty_rest_of_line (); | |
12634 | } | |
12635 | ||
12636 | /* Parse a register string into a number. Called from the ECOFF code | |
12637 | to parse .frame. The argument is non-zero if this is the frame | |
12638 | register, so that we can record it in mips_frame_reg. */ | |
12639 | ||
12640 | int | |
12641 | tc_get_register (frame) | |
12642 | int frame; | |
12643 | { | |
12644 | int reg; | |
12645 | ||
12646 | SKIP_WHITESPACE (); | |
12647 | if (*input_line_pointer++ != '$') | |
12648 | { | |
12649 | as_warn (_("expected `$'")); | |
85b51719 | 12650 | reg = ZERO; |
252b5132 | 12651 | } |
3882b010 | 12652 | else if (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
12653 | { |
12654 | reg = get_absolute_expression (); | |
12655 | if (reg < 0 || reg >= 32) | |
12656 | { | |
12657 | as_warn (_("Bad register number")); | |
85b51719 | 12658 | reg = ZERO; |
252b5132 RH |
12659 | } |
12660 | } | |
12661 | else | |
12662 | { | |
76db943d | 12663 | if (strncmp (input_line_pointer, "ra", 2) == 0) |
85b51719 TS |
12664 | { |
12665 | reg = RA; | |
12666 | input_line_pointer += 2; | |
12667 | } | |
76db943d | 12668 | else if (strncmp (input_line_pointer, "fp", 2) == 0) |
85b51719 TS |
12669 | { |
12670 | reg = FP; | |
12671 | input_line_pointer += 2; | |
12672 | } | |
252b5132 | 12673 | else if (strncmp (input_line_pointer, "sp", 2) == 0) |
85b51719 TS |
12674 | { |
12675 | reg = SP; | |
12676 | input_line_pointer += 2; | |
12677 | } | |
252b5132 | 12678 | else if (strncmp (input_line_pointer, "gp", 2) == 0) |
85b51719 TS |
12679 | { |
12680 | reg = GP; | |
12681 | input_line_pointer += 2; | |
12682 | } | |
252b5132 | 12683 | else if (strncmp (input_line_pointer, "at", 2) == 0) |
85b51719 TS |
12684 | { |
12685 | reg = AT; | |
12686 | input_line_pointer += 2; | |
12687 | } | |
12688 | else if (strncmp (input_line_pointer, "kt0", 3) == 0) | |
12689 | { | |
12690 | reg = KT0; | |
12691 | input_line_pointer += 3; | |
12692 | } | |
12693 | else if (strncmp (input_line_pointer, "kt1", 3) == 0) | |
12694 | { | |
12695 | reg = KT1; | |
12696 | input_line_pointer += 3; | |
12697 | } | |
12698 | else if (strncmp (input_line_pointer, "zero", 4) == 0) | |
12699 | { | |
12700 | reg = ZERO; | |
12701 | input_line_pointer += 4; | |
12702 | } | |
252b5132 RH |
12703 | else |
12704 | { | |
12705 | as_warn (_("Unrecognized register name")); | |
85b51719 TS |
12706 | reg = ZERO; |
12707 | while (ISALNUM(*input_line_pointer)) | |
12708 | input_line_pointer++; | |
252b5132 | 12709 | } |
252b5132 RH |
12710 | } |
12711 | if (frame) | |
7a621144 DJ |
12712 | { |
12713 | mips_frame_reg = reg != 0 ? reg : SP; | |
12714 | mips_frame_reg_valid = 1; | |
12715 | mips_cprestore_valid = 0; | |
12716 | } | |
252b5132 RH |
12717 | return reg; |
12718 | } | |
12719 | ||
12720 | valueT | |
12721 | md_section_align (seg, addr) | |
12722 | asection *seg; | |
12723 | valueT addr; | |
12724 | { | |
12725 | int align = bfd_get_section_alignment (stdoutput, seg); | |
12726 | ||
12727 | #ifdef OBJ_ELF | |
12728 | /* We don't need to align ELF sections to the full alignment. | |
12729 | However, Irix 5 may prefer that we align them at least to a 16 | |
12730 | byte boundary. We don't bother to align the sections if we are | |
12731 | targeted for an embedded system. */ | |
12732 | if (strcmp (TARGET_OS, "elf") == 0) | |
12733 | return addr; | |
12734 | if (align > 4) | |
12735 | align = 4; | |
12736 | #endif | |
12737 | ||
12738 | return ((addr + (1 << align) - 1) & (-1 << align)); | |
12739 | } | |
12740 | ||
12741 | /* Utility routine, called from above as well. If called while the | |
12742 | input file is still being read, it's only an approximation. (For | |
12743 | example, a symbol may later become defined which appeared to be | |
12744 | undefined earlier.) */ | |
12745 | ||
12746 | static int | |
12747 | nopic_need_relax (sym, before_relaxing) | |
12748 | symbolS *sym; | |
12749 | int before_relaxing; | |
12750 | { | |
12751 | if (sym == 0) | |
12752 | return 0; | |
12753 | ||
6478892d | 12754 | if (USE_GLOBAL_POINTER_OPT && g_switch_value > 0) |
252b5132 RH |
12755 | { |
12756 | const char *symname; | |
12757 | int change; | |
12758 | ||
c9914766 | 12759 | /* Find out whether this symbol can be referenced off the $gp |
252b5132 RH |
12760 | register. It can be if it is smaller than the -G size or if |
12761 | it is in the .sdata or .sbss section. Certain symbols can | |
c9914766 | 12762 | not be referenced off the $gp, although it appears as though |
252b5132 RH |
12763 | they can. */ |
12764 | symname = S_GET_NAME (sym); | |
12765 | if (symname != (const char *) NULL | |
12766 | && (strcmp (symname, "eprol") == 0 | |
12767 | || strcmp (symname, "etext") == 0 | |
12768 | || strcmp (symname, "_gp") == 0 | |
12769 | || strcmp (symname, "edata") == 0 | |
12770 | || strcmp (symname, "_fbss") == 0 | |
12771 | || strcmp (symname, "_fdata") == 0 | |
12772 | || strcmp (symname, "_ftext") == 0 | |
12773 | || strcmp (symname, "end") == 0 | |
12774 | || strcmp (symname, "_gp_disp") == 0)) | |
12775 | change = 1; | |
12776 | else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym)) | |
97bbfa38 | 12777 | && !S_IS_EXTERN (sym) |
252b5132 RH |
12778 | && (0 |
12779 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 ILT |
12780 | || (symbol_get_obj (sym)->ecoff_extern_size != 0 |
12781 | && (symbol_get_obj (sym)->ecoff_extern_size | |
12782 | <= g_switch_value)) | |
252b5132 RH |
12783 | #endif |
12784 | /* We must defer this decision until after the whole | |
12785 | file has been read, since there might be a .extern | |
12786 | after the first use of this symbol. */ | |
12787 | || (before_relaxing | |
12788 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 | 12789 | && symbol_get_obj (sym)->ecoff_extern_size == 0 |
252b5132 RH |
12790 | #endif |
12791 | && S_GET_VALUE (sym) == 0) | |
12792 | || (S_GET_VALUE (sym) != 0 | |
12793 | && S_GET_VALUE (sym) <= g_switch_value))) | |
12794 | change = 0; | |
12795 | else | |
12796 | { | |
12797 | const char *segname; | |
12798 | ||
12799 | segname = segment_name (S_GET_SEGMENT (sym)); | |
12800 | assert (strcmp (segname, ".lit8") != 0 | |
12801 | && strcmp (segname, ".lit4") != 0); | |
12802 | change = (strcmp (segname, ".sdata") != 0 | |
fba2b7f9 GK |
12803 | && strcmp (segname, ".sbss") != 0 |
12804 | && strncmp (segname, ".sdata.", 7) != 0 | |
12805 | && strncmp (segname, ".gnu.linkonce.s.", 16) != 0); | |
252b5132 RH |
12806 | } |
12807 | return change; | |
12808 | } | |
12809 | else | |
c9914766 | 12810 | /* We are not optimizing for the $gp register. */ |
252b5132 RH |
12811 | return 1; |
12812 | } | |
12813 | ||
5919d012 RS |
12814 | |
12815 | /* Return true if the given symbol should be considered local for SVR4 PIC. */ | |
12816 | ||
12817 | static bfd_boolean | |
12818 | pic_need_relax (sym, segtype) | |
12819 | symbolS *sym; | |
12820 | asection *segtype; | |
12821 | { | |
12822 | asection *symsec; | |
12823 | bfd_boolean linkonce; | |
12824 | ||
12825 | /* Handle the case of a symbol equated to another symbol. */ | |
12826 | while (symbol_equated_reloc_p (sym)) | |
12827 | { | |
12828 | symbolS *n; | |
12829 | ||
12830 | /* It's possible to get a loop here in a badly written | |
12831 | program. */ | |
12832 | n = symbol_get_value_expression (sym)->X_add_symbol; | |
12833 | if (n == sym) | |
12834 | break; | |
12835 | sym = n; | |
12836 | } | |
12837 | ||
12838 | symsec = S_GET_SEGMENT (sym); | |
12839 | ||
12840 | /* duplicate the test for LINK_ONCE sections as in adjust_reloc_syms */ | |
12841 | linkonce = FALSE; | |
12842 | if (symsec != segtype && ! S_IS_LOCAL (sym)) | |
12843 | { | |
12844 | if ((bfd_get_section_flags (stdoutput, symsec) & SEC_LINK_ONCE) | |
12845 | != 0) | |
12846 | linkonce = TRUE; | |
12847 | ||
12848 | /* The GNU toolchain uses an extension for ELF: a section | |
12849 | beginning with the magic string .gnu.linkonce is a linkonce | |
12850 | section. */ | |
12851 | if (strncmp (segment_name (symsec), ".gnu.linkonce", | |
12852 | sizeof ".gnu.linkonce" - 1) == 0) | |
12853 | linkonce = TRUE; | |
12854 | } | |
12855 | ||
12856 | /* This must duplicate the test in adjust_reloc_syms. */ | |
12857 | return (symsec != &bfd_und_section | |
12858 | && symsec != &bfd_abs_section | |
12859 | && ! bfd_is_com_section (symsec) | |
12860 | && !linkonce | |
12861 | #ifdef OBJ_ELF | |
12862 | /* A global or weak symbol is treated as external. */ | |
12863 | && (OUTPUT_FLAVOR != bfd_target_elf_flavour | |
12864 | || (! S_IS_WEAK (sym) | |
12865 | && (! S_IS_EXTERNAL (sym) | |
12866 | || mips_pic == EMBEDDED_PIC))) | |
12867 | #endif | |
12868 | ); | |
12869 | } | |
12870 | ||
12871 | ||
252b5132 RH |
12872 | /* Given a mips16 variant frag FRAGP, return non-zero if it needs an |
12873 | extended opcode. SEC is the section the frag is in. */ | |
12874 | ||
12875 | static int | |
12876 | mips16_extended_frag (fragp, sec, stretch) | |
12877 | fragS *fragp; | |
12878 | asection *sec; | |
12879 | long stretch; | |
12880 | { | |
12881 | int type; | |
12882 | register const struct mips16_immed_operand *op; | |
12883 | offsetT val; | |
12884 | int mintiny, maxtiny; | |
12885 | segT symsec; | |
98aa84af | 12886 | fragS *sym_frag; |
252b5132 RH |
12887 | |
12888 | if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype)) | |
12889 | return 0; | |
12890 | if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype)) | |
12891 | return 1; | |
12892 | ||
12893 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
12894 | op = mips16_immed_operands; | |
12895 | while (op->type != type) | |
12896 | { | |
12897 | ++op; | |
12898 | assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); | |
12899 | } | |
12900 | ||
12901 | if (op->unsp) | |
12902 | { | |
12903 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
12904 | { | |
12905 | mintiny = 1; | |
12906 | maxtiny = 1 << op->nbits; | |
12907 | } | |
12908 | else | |
12909 | { | |
12910 | mintiny = 0; | |
12911 | maxtiny = (1 << op->nbits) - 1; | |
12912 | } | |
12913 | } | |
12914 | else | |
12915 | { | |
12916 | mintiny = - (1 << (op->nbits - 1)); | |
12917 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
12918 | } | |
12919 | ||
98aa84af | 12920 | sym_frag = symbol_get_frag (fragp->fr_symbol); |
ac62c346 | 12921 | val = S_GET_VALUE (fragp->fr_symbol); |
98aa84af | 12922 | symsec = S_GET_SEGMENT (fragp->fr_symbol); |
252b5132 RH |
12923 | |
12924 | if (op->pcrel) | |
12925 | { | |
12926 | addressT addr; | |
12927 | ||
12928 | /* We won't have the section when we are called from | |
12929 | mips_relax_frag. However, we will always have been called | |
12930 | from md_estimate_size_before_relax first. If this is a | |
12931 | branch to a different section, we mark it as such. If SEC is | |
12932 | NULL, and the frag is not marked, then it must be a branch to | |
12933 | the same section. */ | |
12934 | if (sec == NULL) | |
12935 | { | |
12936 | if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype)) | |
12937 | return 1; | |
12938 | } | |
12939 | else | |
12940 | { | |
98aa84af | 12941 | /* Must have been called from md_estimate_size_before_relax. */ |
252b5132 RH |
12942 | if (symsec != sec) |
12943 | { | |
12944 | fragp->fr_subtype = | |
12945 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
12946 | ||
12947 | /* FIXME: We should support this, and let the linker | |
12948 | catch branches and loads that are out of range. */ | |
12949 | as_bad_where (fragp->fr_file, fragp->fr_line, | |
12950 | _("unsupported PC relative reference to different section")); | |
12951 | ||
12952 | return 1; | |
12953 | } | |
98aa84af AM |
12954 | if (fragp != sym_frag && sym_frag->fr_address == 0) |
12955 | /* Assume non-extended on the first relaxation pass. | |
12956 | The address we have calculated will be bogus if this is | |
12957 | a forward branch to another frag, as the forward frag | |
12958 | will have fr_address == 0. */ | |
12959 | return 0; | |
252b5132 RH |
12960 | } |
12961 | ||
12962 | /* In this case, we know for sure that the symbol fragment is in | |
98aa84af AM |
12963 | the same section. If the relax_marker of the symbol fragment |
12964 | differs from the relax_marker of this fragment, we have not | |
12965 | yet adjusted the symbol fragment fr_address. We want to add | |
252b5132 RH |
12966 | in STRETCH in order to get a better estimate of the address. |
12967 | This particularly matters because of the shift bits. */ | |
12968 | if (stretch != 0 | |
98aa84af | 12969 | && sym_frag->relax_marker != fragp->relax_marker) |
252b5132 RH |
12970 | { |
12971 | fragS *f; | |
12972 | ||
12973 | /* Adjust stretch for any alignment frag. Note that if have | |
12974 | been expanding the earlier code, the symbol may be | |
12975 | defined in what appears to be an earlier frag. FIXME: | |
12976 | This doesn't handle the fr_subtype field, which specifies | |
12977 | a maximum number of bytes to skip when doing an | |
12978 | alignment. */ | |
98aa84af | 12979 | for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next) |
252b5132 RH |
12980 | { |
12981 | if (f->fr_type == rs_align || f->fr_type == rs_align_code) | |
12982 | { | |
12983 | if (stretch < 0) | |
12984 | stretch = - ((- stretch) | |
12985 | & ~ ((1 << (int) f->fr_offset) - 1)); | |
12986 | else | |
12987 | stretch &= ~ ((1 << (int) f->fr_offset) - 1); | |
12988 | if (stretch == 0) | |
12989 | break; | |
12990 | } | |
12991 | } | |
12992 | if (f != NULL) | |
12993 | val += stretch; | |
12994 | } | |
12995 | ||
12996 | addr = fragp->fr_address + fragp->fr_fix; | |
12997 | ||
12998 | /* The base address rules are complicated. The base address of | |
12999 | a branch is the following instruction. The base address of a | |
13000 | PC relative load or add is the instruction itself, but if it | |
13001 | is in a delay slot (in which case it can not be extended) use | |
13002 | the address of the instruction whose delay slot it is in. */ | |
13003 | if (type == 'p' || type == 'q') | |
13004 | { | |
13005 | addr += 2; | |
13006 | ||
13007 | /* If we are currently assuming that this frag should be | |
13008 | extended, then, the current address is two bytes | |
bdaaa2e1 | 13009 | higher. */ |
252b5132 RH |
13010 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) |
13011 | addr += 2; | |
13012 | ||
13013 | /* Ignore the low bit in the target, since it will be set | |
13014 | for a text label. */ | |
13015 | if ((val & 1) != 0) | |
13016 | --val; | |
13017 | } | |
13018 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) | |
13019 | addr -= 4; | |
13020 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
13021 | addr -= 2; | |
13022 | ||
13023 | val -= addr & ~ ((1 << op->shift) - 1); | |
13024 | ||
13025 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
13026 | if (type == 'p' || type == 'q') | |
13027 | val /= 2; | |
13028 | ||
13029 | /* If any of the shifted bits are set, we must use an extended | |
13030 | opcode. If the address depends on the size of this | |
13031 | instruction, this can lead to a loop, so we arrange to always | |
13032 | use an extended opcode. We only check this when we are in | |
13033 | the main relaxation loop, when SEC is NULL. */ | |
13034 | if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL) | |
13035 | { | |
13036 | fragp->fr_subtype = | |
13037 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
13038 | return 1; | |
13039 | } | |
13040 | ||
13041 | /* If we are about to mark a frag as extended because the value | |
13042 | is precisely maxtiny + 1, then there is a chance of an | |
13043 | infinite loop as in the following code: | |
13044 | la $4,foo | |
13045 | .skip 1020 | |
13046 | .align 2 | |
13047 | foo: | |
13048 | In this case when the la is extended, foo is 0x3fc bytes | |
13049 | away, so the la can be shrunk, but then foo is 0x400 away, so | |
13050 | the la must be extended. To avoid this loop, we mark the | |
13051 | frag as extended if it was small, and is about to become | |
13052 | extended with a value of maxtiny + 1. */ | |
13053 | if (val == ((maxtiny + 1) << op->shift) | |
13054 | && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype) | |
13055 | && sec == NULL) | |
13056 | { | |
13057 | fragp->fr_subtype = | |
13058 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
13059 | return 1; | |
13060 | } | |
13061 | } | |
13062 | else if (symsec != absolute_section && sec != NULL) | |
13063 | as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation")); | |
13064 | ||
13065 | if ((val & ((1 << op->shift) - 1)) != 0 | |
13066 | || val < (mintiny << op->shift) | |
13067 | || val > (maxtiny << op->shift)) | |
13068 | return 1; | |
13069 | else | |
13070 | return 0; | |
13071 | } | |
13072 | ||
4a6a3df4 AO |
13073 | /* Compute the length of a branch sequence, and adjust the |
13074 | RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the | |
13075 | worst-case length is computed, with UPDATE being used to indicate | |
13076 | whether an unconditional (-1), branch-likely (+1) or regular (0) | |
13077 | branch is to be computed. */ | |
13078 | static int | |
13079 | relaxed_branch_length (fragp, sec, update) | |
13080 | fragS *fragp; | |
13081 | asection *sec; | |
13082 | int update; | |
13083 | { | |
b34976b6 | 13084 | bfd_boolean toofar; |
4a6a3df4 AO |
13085 | int length; |
13086 | ||
13087 | if (fragp | |
13088 | && S_IS_DEFINED (fragp->fr_symbol) | |
13089 | && sec == S_GET_SEGMENT (fragp->fr_symbol)) | |
13090 | { | |
13091 | addressT addr; | |
13092 | offsetT val; | |
13093 | ||
13094 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; | |
13095 | ||
13096 | addr = fragp->fr_address + fragp->fr_fix + 4; | |
13097 | ||
13098 | val -= addr; | |
13099 | ||
13100 | toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2); | |
13101 | } | |
13102 | else if (fragp) | |
13103 | /* If the symbol is not defined or it's in a different segment, | |
13104 | assume the user knows what's going on and emit a short | |
13105 | branch. */ | |
b34976b6 | 13106 | toofar = FALSE; |
4a6a3df4 | 13107 | else |
b34976b6 | 13108 | toofar = TRUE; |
4a6a3df4 AO |
13109 | |
13110 | if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) | |
13111 | fragp->fr_subtype | |
af6ae2ad | 13112 | = RELAX_BRANCH_ENCODE (RELAX_BRANCH_UNCOND (fragp->fr_subtype), |
4a6a3df4 AO |
13113 | RELAX_BRANCH_LIKELY (fragp->fr_subtype), |
13114 | RELAX_BRANCH_LINK (fragp->fr_subtype), | |
13115 | toofar); | |
13116 | ||
13117 | length = 4; | |
13118 | if (toofar) | |
13119 | { | |
13120 | if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0)) | |
13121 | length += 8; | |
13122 | ||
13123 | if (mips_pic != NO_PIC) | |
13124 | { | |
13125 | /* Additional space for PIC loading of target address. */ | |
13126 | length += 8; | |
13127 | if (mips_opts.isa == ISA_MIPS1) | |
13128 | /* Additional space for $at-stabilizing nop. */ | |
13129 | length += 4; | |
13130 | } | |
13131 | ||
13132 | /* If branch is conditional. */ | |
13133 | if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0)) | |
13134 | length += 8; | |
13135 | } | |
b34976b6 | 13136 | |
4a6a3df4 AO |
13137 | return length; |
13138 | } | |
13139 | ||
252b5132 RH |
13140 | /* Estimate the size of a frag before relaxing. Unless this is the |
13141 | mips16, we are not really relaxing here, and the final size is | |
13142 | encoded in the subtype information. For the mips16, we have to | |
13143 | decide whether we are using an extended opcode or not. */ | |
13144 | ||
252b5132 RH |
13145 | int |
13146 | md_estimate_size_before_relax (fragp, segtype) | |
13147 | fragS *fragp; | |
13148 | asection *segtype; | |
13149 | { | |
5919d012 | 13150 | int change; |
252b5132 | 13151 | |
4a6a3df4 AO |
13152 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
13153 | { | |
13154 | ||
b34976b6 AM |
13155 | fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE); |
13156 | ||
4a6a3df4 AO |
13157 | return fragp->fr_var; |
13158 | } | |
13159 | ||
252b5132 | 13160 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
177b4a6a AO |
13161 | /* We don't want to modify the EXTENDED bit here; it might get us |
13162 | into infinite loops. We change it only in mips_relax_frag(). */ | |
13163 | return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2); | |
252b5132 RH |
13164 | |
13165 | if (mips_pic == NO_PIC) | |
5919d012 | 13166 | change = nopic_need_relax (fragp->fr_symbol, 0); |
252b5132 | 13167 | else if (mips_pic == SVR4_PIC) |
5919d012 | 13168 | change = pic_need_relax (fragp->fr_symbol, segtype); |
252b5132 RH |
13169 | else |
13170 | abort (); | |
13171 | ||
13172 | if (change) | |
13173 | { | |
13174 | /* Record the offset to the first reloc in the fr_opcode field. | |
13175 | This lets md_convert_frag and tc_gen_reloc know that the code | |
13176 | must be expanded. */ | |
13177 | fragp->fr_opcode = (fragp->fr_literal | |
13178 | + fragp->fr_fix | |
13179 | - RELAX_OLD (fragp->fr_subtype) | |
13180 | + RELAX_RELOC1 (fragp->fr_subtype)); | |
13181 | /* FIXME: This really needs as_warn_where. */ | |
13182 | if (RELAX_WARN (fragp->fr_subtype)) | |
9a41af64 TS |
13183 | as_warn (_("AT used after \".set noat\" or macro used after " |
13184 | "\".set nomacro\"")); | |
13185 | ||
13186 | return RELAX_NEW (fragp->fr_subtype) - RELAX_OLD (fragp->fr_subtype); | |
252b5132 RH |
13187 | } |
13188 | ||
9a41af64 | 13189 | return 0; |
252b5132 RH |
13190 | } |
13191 | ||
13192 | /* This is called to see whether a reloc against a defined symbol | |
13193 | should be converted into a reloc against a section. Don't adjust | |
13194 | MIPS16 jump relocations, so we don't have to worry about the format | |
13195 | of the offset in the .o file. Don't adjust relocations against | |
13196 | mips16 symbols, so that the linker can find them if it needs to set | |
13197 | up a stub. */ | |
13198 | ||
13199 | int | |
13200 | mips_fix_adjustable (fixp) | |
13201 | fixS *fixp; | |
13202 | { | |
13203 | if (fixp->fx_r_type == BFD_RELOC_MIPS16_JMP) | |
13204 | return 0; | |
a161fe53 | 13205 | |
252b5132 RH |
13206 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
13207 | || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
13208 | return 0; | |
a161fe53 | 13209 | |
252b5132 RH |
13210 | if (fixp->fx_addsy == NULL) |
13211 | return 1; | |
a161fe53 | 13212 | |
252b5132 RH |
13213 | #ifdef OBJ_ELF |
13214 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour | |
13215 | && S_GET_OTHER (fixp->fx_addsy) == STO_MIPS16 | |
13216 | && fixp->fx_subsy == NULL) | |
13217 | return 0; | |
13218 | #endif | |
a161fe53 | 13219 | |
252b5132 RH |
13220 | return 1; |
13221 | } | |
13222 | ||
13223 | /* Translate internal representation of relocation info to BFD target | |
13224 | format. */ | |
13225 | ||
13226 | arelent ** | |
13227 | tc_gen_reloc (section, fixp) | |
43841e91 | 13228 | asection *section ATTRIBUTE_UNUSED; |
252b5132 RH |
13229 | fixS *fixp; |
13230 | { | |
13231 | static arelent *retval[4]; | |
13232 | arelent *reloc; | |
13233 | bfd_reloc_code_real_type code; | |
13234 | ||
13235 | reloc = retval[0] = (arelent *) xmalloc (sizeof (arelent)); | |
13236 | retval[1] = NULL; | |
13237 | ||
49309057 ILT |
13238 | reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); |
13239 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
252b5132 RH |
13240 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; |
13241 | ||
13242 | if (mips_pic == EMBEDDED_PIC | |
13243 | && SWITCH_TABLE (fixp)) | |
13244 | { | |
13245 | /* For a switch table entry we use a special reloc. The addend | |
13246 | is actually the difference between the reloc address and the | |
13247 | subtrahend. */ | |
13248 | reloc->addend = reloc->address - S_GET_VALUE (fixp->fx_subsy); | |
13249 | if (OUTPUT_FLAVOR != bfd_target_ecoff_flavour) | |
13250 | as_fatal (_("Double check fx_r_type in tc-mips.c:tc_gen_reloc")); | |
13251 | fixp->fx_r_type = BFD_RELOC_GPREL32; | |
13252 | } | |
13253 | else if (fixp->fx_r_type == BFD_RELOC_PCREL_LO16) | |
13254 | { | |
4514d474 CD |
13255 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) |
13256 | reloc->addend = fixp->fx_addnumber; | |
252b5132 | 13257 | else |
4514d474 CD |
13258 | { |
13259 | /* We use a special addend for an internal RELLO reloc. */ | |
13260 | if (symbol_section_p (fixp->fx_addsy)) | |
13261 | reloc->addend = reloc->address - S_GET_VALUE (fixp->fx_subsy); | |
13262 | else | |
13263 | reloc->addend = fixp->fx_addnumber + reloc->address; | |
13264 | } | |
252b5132 RH |
13265 | } |
13266 | else if (fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S) | |
13267 | { | |
13268 | assert (fixp->fx_next != NULL | |
13269 | && fixp->fx_next->fx_r_type == BFD_RELOC_PCREL_LO16); | |
4514d474 CD |
13270 | |
13271 | /* The reloc is relative to the RELLO; adjust the addend | |
252b5132 | 13272 | accordingly. */ |
4514d474 CD |
13273 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) |
13274 | reloc->addend = fixp->fx_next->fx_addnumber; | |
252b5132 | 13275 | else |
4514d474 CD |
13276 | { |
13277 | /* We use a special addend for an internal RELHI reloc. */ | |
13278 | if (symbol_section_p (fixp->fx_addsy)) | |
13279 | reloc->addend = (fixp->fx_next->fx_frag->fr_address | |
13280 | + fixp->fx_next->fx_where | |
13281 | - S_GET_VALUE (fixp->fx_subsy)); | |
13282 | else | |
13283 | reloc->addend = (fixp->fx_addnumber | |
13284 | + fixp->fx_next->fx_frag->fr_address | |
13285 | + fixp->fx_next->fx_where); | |
13286 | } | |
252b5132 | 13287 | } |
4514d474 CD |
13288 | else if (fixp->fx_pcrel == 0 || OUTPUT_FLAVOR == bfd_target_elf_flavour) |
13289 | reloc->addend = fixp->fx_addnumber; | |
252b5132 RH |
13290 | else |
13291 | { | |
13292 | if (OUTPUT_FLAVOR != bfd_target_aout_flavour) | |
13293 | /* A gruesome hack which is a result of the gruesome gas reloc | |
13294 | handling. */ | |
13295 | reloc->addend = reloc->address; | |
13296 | else | |
13297 | reloc->addend = -reloc->address; | |
13298 | } | |
13299 | ||
13300 | /* If this is a variant frag, we may need to adjust the existing | |
13301 | reloc and generate a new one. */ | |
13302 | if (fixp->fx_frag->fr_opcode != NULL | |
ed6fb7bd SC |
13303 | && ((fixp->fx_r_type == BFD_RELOC_GPREL16 |
13304 | && ! HAVE_NEWABI) | |
252b5132 RH |
13305 | || fixp->fx_r_type == BFD_RELOC_MIPS_GOT16 |
13306 | || fixp->fx_r_type == BFD_RELOC_MIPS_CALL16 | |
13307 | || fixp->fx_r_type == BFD_RELOC_MIPS_GOT_HI16 | |
13308 | || fixp->fx_r_type == BFD_RELOC_MIPS_GOT_LO16 | |
13309 | || fixp->fx_r_type == BFD_RELOC_MIPS_CALL_HI16 | |
6478892d | 13310 | || fixp->fx_r_type == BFD_RELOC_MIPS_CALL_LO16) |
ed6fb7bd | 13311 | ) |
252b5132 RH |
13312 | { |
13313 | arelent *reloc2; | |
13314 | ||
13315 | assert (! RELAX_MIPS16_P (fixp->fx_frag->fr_subtype)); | |
13316 | ||
13317 | /* If this is not the last reloc in this frag, then we have two | |
13318 | GPREL relocs, or a GOT_HI16/GOT_LO16 pair, or a | |
13319 | CALL_HI16/CALL_LO16, both of which are being replaced. Let | |
13320 | the second one handle all of them. */ | |
13321 | if (fixp->fx_next != NULL | |
13322 | && fixp->fx_frag == fixp->fx_next->fx_frag) | |
13323 | { | |
cdf6fd85 TS |
13324 | assert ((fixp->fx_r_type == BFD_RELOC_GPREL16 |
13325 | && fixp->fx_next->fx_r_type == BFD_RELOC_GPREL16) | |
252b5132 RH |
13326 | || (fixp->fx_r_type == BFD_RELOC_MIPS_GOT_HI16 |
13327 | && (fixp->fx_next->fx_r_type | |
13328 | == BFD_RELOC_MIPS_GOT_LO16)) | |
13329 | || (fixp->fx_r_type == BFD_RELOC_MIPS_CALL_HI16 | |
13330 | && (fixp->fx_next->fx_r_type | |
13331 | == BFD_RELOC_MIPS_CALL_LO16))); | |
13332 | retval[0] = NULL; | |
13333 | return retval; | |
13334 | } | |
13335 | ||
13336 | fixp->fx_where = fixp->fx_frag->fr_opcode - fixp->fx_frag->fr_literal; | |
13337 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
13338 | reloc2 = retval[1] = (arelent *) xmalloc (sizeof (arelent)); | |
13339 | retval[2] = NULL; | |
49309057 ILT |
13340 | reloc2->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); |
13341 | *reloc2->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
252b5132 RH |
13342 | reloc2->address = (reloc->address |
13343 | + (RELAX_RELOC2 (fixp->fx_frag->fr_subtype) | |
13344 | - RELAX_RELOC1 (fixp->fx_frag->fr_subtype))); | |
13345 | reloc2->addend = fixp->fx_addnumber; | |
13346 | reloc2->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_LO16); | |
13347 | assert (reloc2->howto != NULL); | |
13348 | ||
13349 | if (RELAX_RELOC3 (fixp->fx_frag->fr_subtype)) | |
13350 | { | |
13351 | arelent *reloc3; | |
13352 | ||
13353 | reloc3 = retval[2] = (arelent *) xmalloc (sizeof (arelent)); | |
13354 | retval[3] = NULL; | |
13355 | *reloc3 = *reloc2; | |
13356 | reloc3->address += 4; | |
13357 | } | |
13358 | ||
13359 | if (mips_pic == NO_PIC) | |
13360 | { | |
cdf6fd85 | 13361 | assert (fixp->fx_r_type == BFD_RELOC_GPREL16); |
252b5132 RH |
13362 | fixp->fx_r_type = BFD_RELOC_HI16_S; |
13363 | } | |
13364 | else if (mips_pic == SVR4_PIC) | |
13365 | { | |
13366 | switch (fixp->fx_r_type) | |
13367 | { | |
13368 | default: | |
13369 | abort (); | |
13370 | case BFD_RELOC_MIPS_GOT16: | |
13371 | break; | |
252b5132 RH |
13372 | case BFD_RELOC_MIPS_GOT_LO16: |
13373 | case BFD_RELOC_MIPS_CALL_LO16: | |
13374 | fixp->fx_r_type = BFD_RELOC_MIPS_GOT16; | |
13375 | break; | |
ed6fb7bd SC |
13376 | case BFD_RELOC_MIPS_CALL16: |
13377 | if (HAVE_NEWABI) | |
13378 | { | |
13379 | /* BFD_RELOC_MIPS_GOT16;*/ | |
13380 | fixp->fx_r_type = BFD_RELOC_MIPS_GOT_PAGE; | |
13381 | reloc2->howto = bfd_reloc_type_lookup | |
13382 | (stdoutput, BFD_RELOC_MIPS_GOT_OFST); | |
13383 | } | |
13384 | else | |
13385 | fixp->fx_r_type = BFD_RELOC_MIPS_GOT16; | |
13386 | break; | |
252b5132 RH |
13387 | } |
13388 | } | |
13389 | else | |
13390 | abort (); | |
ed6fb7bd SC |
13391 | |
13392 | /* newabi uses R_MIPS_GOT_DISP for local symbols */ | |
6b70243f | 13393 | if (HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_MIPS_GOT_LO16) |
ed6fb7bd SC |
13394 | { |
13395 | fixp->fx_r_type = BFD_RELOC_MIPS_GOT_DISP; | |
13396 | retval[1] = NULL; | |
13397 | } | |
252b5132 RH |
13398 | } |
13399 | ||
438c16b8 TS |
13400 | /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable |
13401 | entry to be used in the relocation's section offset. */ | |
13402 | if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
252b5132 RH |
13403 | { |
13404 | reloc->address = reloc->addend; | |
13405 | reloc->addend = 0; | |
13406 | } | |
13407 | ||
13408 | /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that | |
13409 | fixup_segment converted a non-PC relative reloc into a PC | |
13410 | relative reloc. In such a case, we need to convert the reloc | |
13411 | code. */ | |
13412 | code = fixp->fx_r_type; | |
13413 | if (fixp->fx_pcrel) | |
13414 | { | |
13415 | switch (code) | |
13416 | { | |
13417 | case BFD_RELOC_8: | |
13418 | code = BFD_RELOC_8_PCREL; | |
13419 | break; | |
13420 | case BFD_RELOC_16: | |
13421 | code = BFD_RELOC_16_PCREL; | |
13422 | break; | |
13423 | case BFD_RELOC_32: | |
13424 | code = BFD_RELOC_32_PCREL; | |
13425 | break; | |
13426 | case BFD_RELOC_64: | |
13427 | code = BFD_RELOC_64_PCREL; | |
13428 | break; | |
13429 | case BFD_RELOC_8_PCREL: | |
13430 | case BFD_RELOC_16_PCREL: | |
13431 | case BFD_RELOC_32_PCREL: | |
13432 | case BFD_RELOC_64_PCREL: | |
13433 | case BFD_RELOC_16_PCREL_S2: | |
13434 | case BFD_RELOC_PCREL_HI16_S: | |
13435 | case BFD_RELOC_PCREL_LO16: | |
13436 | break; | |
13437 | default: | |
13438 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
13439 | _("Cannot make %s relocation PC relative"), | |
13440 | bfd_get_reloc_code_name (code)); | |
13441 | } | |
13442 | } | |
13443 | ||
add55e1f RS |
13444 | #ifdef OBJ_ELF |
13445 | /* md_apply_fix3 has a double-subtraction hack to get | |
13446 | bfd_install_relocation to behave nicely. GPREL relocations are | |
13447 | handled correctly without this hack, so undo it here. We can't | |
13448 | stop md_apply_fix3 from subtracting twice in the first place since | |
13449 | the fake addend is required for variant frags above. */ | |
13450 | if (fixp->fx_addsy != NULL && OUTPUT_FLAVOR == bfd_target_elf_flavour | |
98605598 | 13451 | && (code == BFD_RELOC_GPREL16 || code == BFD_RELOC_MIPS16_GPREL) |
add55e1f RS |
13452 | && reloc->addend != 0 |
13453 | && mips_need_elf_addend_fixup (fixp)) | |
13454 | reloc->addend += S_GET_VALUE (fixp->fx_addsy); | |
13455 | #endif | |
13456 | ||
0b25d3e6 AO |
13457 | /* To support a PC relative reloc when generating embedded PIC code |
13458 | for ECOFF, we use a Cygnus extension. We check for that here to | |
13459 | make sure that we don't let such a reloc escape normally. */ | |
13460 | if ((OUTPUT_FLAVOR == bfd_target_ecoff_flavour | |
13461 | || OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
13462 | && code == BFD_RELOC_16_PCREL_S2 | |
13463 | && mips_pic != EMBEDDED_PIC) | |
13464 | reloc->howto = NULL; | |
13465 | else | |
13466 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); | |
13467 | ||
252b5132 RH |
13468 | if (reloc->howto == NULL) |
13469 | { | |
13470 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
13471 | _("Can not represent %s relocation in this object file format"), | |
13472 | bfd_get_reloc_code_name (code)); | |
13473 | retval[0] = NULL; | |
13474 | } | |
13475 | ||
13476 | return retval; | |
13477 | } | |
13478 | ||
13479 | /* Relax a machine dependent frag. This returns the amount by which | |
13480 | the current size of the frag should change. */ | |
13481 | ||
13482 | int | |
4a6a3df4 AO |
13483 | mips_relax_frag (sec, fragp, stretch) |
13484 | asection *sec; | |
252b5132 RH |
13485 | fragS *fragp; |
13486 | long stretch; | |
13487 | { | |
4a6a3df4 AO |
13488 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
13489 | { | |
13490 | offsetT old_var = fragp->fr_var; | |
b34976b6 AM |
13491 | |
13492 | fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE); | |
4a6a3df4 AO |
13493 | |
13494 | return fragp->fr_var - old_var; | |
13495 | } | |
13496 | ||
252b5132 RH |
13497 | if (! RELAX_MIPS16_P (fragp->fr_subtype)) |
13498 | return 0; | |
13499 | ||
c4e7957c | 13500 | if (mips16_extended_frag (fragp, NULL, stretch)) |
252b5132 RH |
13501 | { |
13502 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
13503 | return 0; | |
13504 | fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype); | |
13505 | return 2; | |
13506 | } | |
13507 | else | |
13508 | { | |
13509 | if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
13510 | return 0; | |
13511 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype); | |
13512 | return -2; | |
13513 | } | |
13514 | ||
13515 | return 0; | |
13516 | } | |
13517 | ||
13518 | /* Convert a machine dependent frag. */ | |
13519 | ||
13520 | void | |
13521 | md_convert_frag (abfd, asec, fragp) | |
43841e91 | 13522 | bfd *abfd ATTRIBUTE_UNUSED; |
252b5132 RH |
13523 | segT asec; |
13524 | fragS *fragp; | |
13525 | { | |
13526 | int old, new; | |
13527 | char *fixptr; | |
13528 | ||
4a6a3df4 AO |
13529 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
13530 | { | |
13531 | bfd_byte *buf; | |
13532 | unsigned long insn; | |
13533 | expressionS exp; | |
13534 | fixS *fixp; | |
b34976b6 | 13535 | |
4a6a3df4 AO |
13536 | buf = (bfd_byte *)fragp->fr_literal + fragp->fr_fix; |
13537 | ||
13538 | if (target_big_endian) | |
13539 | insn = bfd_getb32 (buf); | |
13540 | else | |
13541 | insn = bfd_getl32 (buf); | |
b34976b6 | 13542 | |
4a6a3df4 AO |
13543 | if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) |
13544 | { | |
13545 | /* We generate a fixup instead of applying it right now | |
13546 | because, if there are linker relaxations, we're going to | |
13547 | need the relocations. */ | |
13548 | exp.X_op = O_symbol; | |
13549 | exp.X_add_symbol = fragp->fr_symbol; | |
13550 | exp.X_add_number = fragp->fr_offset; | |
13551 | ||
13552 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
0b25d3e6 AO |
13553 | 4, &exp, 1, |
13554 | BFD_RELOC_16_PCREL_S2); | |
4a6a3df4 AO |
13555 | fixp->fx_file = fragp->fr_file; |
13556 | fixp->fx_line = fragp->fr_line; | |
b34976b6 | 13557 | |
4a6a3df4 AO |
13558 | md_number_to_chars ((char *)buf, insn, 4); |
13559 | buf += 4; | |
13560 | } | |
13561 | else | |
13562 | { | |
13563 | int i; | |
13564 | ||
13565 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
13566 | _("relaxed out-of-range branch into a jump")); | |
13567 | ||
13568 | if (RELAX_BRANCH_UNCOND (fragp->fr_subtype)) | |
13569 | goto uncond; | |
13570 | ||
13571 | if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
13572 | { | |
13573 | /* Reverse the branch. */ | |
13574 | switch ((insn >> 28) & 0xf) | |
13575 | { | |
13576 | case 4: | |
13577 | /* bc[0-3][tf]l? and bc1any[24][ft] instructions can | |
13578 | have the condition reversed by tweaking a single | |
13579 | bit, and their opcodes all have 0x4???????. */ | |
13580 | assert ((insn & 0xf1000000) == 0x41000000); | |
13581 | insn ^= 0x00010000; | |
13582 | break; | |
13583 | ||
13584 | case 0: | |
13585 | /* bltz 0x04000000 bgez 0x04010000 | |
13586 | bltzal 0x04100000 bgezal 0x04110000 */ | |
13587 | assert ((insn & 0xfc0e0000) == 0x04000000); | |
13588 | insn ^= 0x00010000; | |
13589 | break; | |
b34976b6 | 13590 | |
4a6a3df4 AO |
13591 | case 1: |
13592 | /* beq 0x10000000 bne 0x14000000 | |
13593 | blez 0x18000000 bgtz 0x1c000000 */ | |
13594 | insn ^= 0x04000000; | |
13595 | break; | |
13596 | ||
13597 | default: | |
13598 | abort (); | |
13599 | } | |
13600 | } | |
13601 | ||
13602 | if (RELAX_BRANCH_LINK (fragp->fr_subtype)) | |
13603 | { | |
13604 | /* Clear the and-link bit. */ | |
13605 | assert ((insn & 0xfc1c0000) == 0x04100000); | |
13606 | ||
13607 | /* bltzal 0x04100000 bgezal 0x04110000 | |
13608 | bltzall 0x04120000 bgezall 0x04130000 */ | |
13609 | insn &= ~0x00100000; | |
13610 | } | |
13611 | ||
13612 | /* Branch over the branch (if the branch was likely) or the | |
13613 | full jump (not likely case). Compute the offset from the | |
13614 | current instruction to branch to. */ | |
13615 | if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
13616 | i = 16; | |
13617 | else | |
13618 | { | |
13619 | /* How many bytes in instructions we've already emitted? */ | |
13620 | i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix; | |
13621 | /* How many bytes in instructions from here to the end? */ | |
13622 | i = fragp->fr_var - i; | |
13623 | } | |
13624 | /* Convert to instruction count. */ | |
13625 | i >>= 2; | |
13626 | /* Branch counts from the next instruction. */ | |
b34976b6 | 13627 | i--; |
4a6a3df4 AO |
13628 | insn |= i; |
13629 | /* Branch over the jump. */ | |
13630 | md_number_to_chars ((char *)buf, insn, 4); | |
13631 | buf += 4; | |
13632 | ||
13633 | /* Nop */ | |
13634 | md_number_to_chars ((char*)buf, 0, 4); | |
13635 | buf += 4; | |
13636 | ||
13637 | if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
13638 | { | |
13639 | /* beql $0, $0, 2f */ | |
13640 | insn = 0x50000000; | |
13641 | /* Compute the PC offset from the current instruction to | |
13642 | the end of the variable frag. */ | |
13643 | /* How many bytes in instructions we've already emitted? */ | |
13644 | i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix; | |
13645 | /* How many bytes in instructions from here to the end? */ | |
13646 | i = fragp->fr_var - i; | |
13647 | /* Convert to instruction count. */ | |
13648 | i >>= 2; | |
13649 | /* Don't decrement i, because we want to branch over the | |
13650 | delay slot. */ | |
13651 | ||
13652 | insn |= i; | |
13653 | md_number_to_chars ((char *)buf, insn, 4); | |
13654 | buf += 4; | |
13655 | ||
13656 | md_number_to_chars ((char *)buf, 0, 4); | |
13657 | buf += 4; | |
13658 | } | |
13659 | ||
13660 | uncond: | |
13661 | if (mips_pic == NO_PIC) | |
13662 | { | |
13663 | /* j or jal. */ | |
13664 | insn = (RELAX_BRANCH_LINK (fragp->fr_subtype) | |
13665 | ? 0x0c000000 : 0x08000000); | |
13666 | exp.X_op = O_symbol; | |
13667 | exp.X_add_symbol = fragp->fr_symbol; | |
13668 | exp.X_add_number = fragp->fr_offset; | |
13669 | ||
13670 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
13671 | 4, &exp, 0, BFD_RELOC_MIPS_JMP); | |
13672 | fixp->fx_file = fragp->fr_file; | |
13673 | fixp->fx_line = fragp->fr_line; | |
13674 | ||
13675 | md_number_to_chars ((char*)buf, insn, 4); | |
13676 | buf += 4; | |
13677 | } | |
13678 | else | |
13679 | { | |
13680 | /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */ | |
13681 | insn = HAVE_64BIT_ADDRESSES ? 0xdf810000 : 0x8f810000; | |
13682 | exp.X_op = O_symbol; | |
13683 | exp.X_add_symbol = fragp->fr_symbol; | |
13684 | exp.X_add_number = fragp->fr_offset; | |
13685 | ||
13686 | if (fragp->fr_offset) | |
13687 | { | |
13688 | exp.X_add_symbol = make_expr_symbol (&exp); | |
13689 | exp.X_add_number = 0; | |
13690 | } | |
13691 | ||
13692 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
13693 | 4, &exp, 0, BFD_RELOC_MIPS_GOT16); | |
13694 | fixp->fx_file = fragp->fr_file; | |
13695 | fixp->fx_line = fragp->fr_line; | |
13696 | ||
13697 | md_number_to_chars ((char*)buf, insn, 4); | |
13698 | buf += 4; | |
b34976b6 | 13699 | |
4a6a3df4 AO |
13700 | if (mips_opts.isa == ISA_MIPS1) |
13701 | { | |
13702 | /* nop */ | |
13703 | md_number_to_chars ((char*)buf, 0, 4); | |
13704 | buf += 4; | |
13705 | } | |
13706 | ||
13707 | /* d/addiu $at, $at, <sym> R_MIPS_LO16 */ | |
13708 | insn = HAVE_64BIT_ADDRESSES ? 0x64210000 : 0x24210000; | |
13709 | ||
13710 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
13711 | 4, &exp, 0, BFD_RELOC_LO16); | |
13712 | fixp->fx_file = fragp->fr_file; | |
13713 | fixp->fx_line = fragp->fr_line; | |
b34976b6 | 13714 | |
4a6a3df4 AO |
13715 | md_number_to_chars ((char*)buf, insn, 4); |
13716 | buf += 4; | |
13717 | ||
13718 | /* j(al)r $at. */ | |
13719 | if (RELAX_BRANCH_LINK (fragp->fr_subtype)) | |
13720 | insn = 0x0020f809; | |
13721 | else | |
13722 | insn = 0x00200008; | |
13723 | ||
13724 | md_number_to_chars ((char*)buf, insn, 4); | |
13725 | buf += 4; | |
13726 | } | |
13727 | } | |
13728 | ||
13729 | assert (buf == (bfd_byte *)fragp->fr_literal | |
13730 | + fragp->fr_fix + fragp->fr_var); | |
13731 | ||
13732 | fragp->fr_fix += fragp->fr_var; | |
13733 | ||
13734 | return; | |
13735 | } | |
13736 | ||
252b5132 RH |
13737 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
13738 | { | |
13739 | int type; | |
13740 | register const struct mips16_immed_operand *op; | |
b34976b6 | 13741 | bfd_boolean small, ext; |
252b5132 RH |
13742 | offsetT val; |
13743 | bfd_byte *buf; | |
13744 | unsigned long insn; | |
b34976b6 | 13745 | bfd_boolean use_extend; |
252b5132 RH |
13746 | unsigned short extend; |
13747 | ||
13748 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
13749 | op = mips16_immed_operands; | |
13750 | while (op->type != type) | |
13751 | ++op; | |
13752 | ||
13753 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
13754 | { | |
b34976b6 AM |
13755 | small = FALSE; |
13756 | ext = TRUE; | |
252b5132 RH |
13757 | } |
13758 | else | |
13759 | { | |
b34976b6 AM |
13760 | small = TRUE; |
13761 | ext = FALSE; | |
252b5132 RH |
13762 | } |
13763 | ||
6386f3a7 | 13764 | resolve_symbol_value (fragp->fr_symbol); |
252b5132 RH |
13765 | val = S_GET_VALUE (fragp->fr_symbol); |
13766 | if (op->pcrel) | |
13767 | { | |
13768 | addressT addr; | |
13769 | ||
13770 | addr = fragp->fr_address + fragp->fr_fix; | |
13771 | ||
13772 | /* The rules for the base address of a PC relative reloc are | |
13773 | complicated; see mips16_extended_frag. */ | |
13774 | if (type == 'p' || type == 'q') | |
13775 | { | |
13776 | addr += 2; | |
13777 | if (ext) | |
13778 | addr += 2; | |
13779 | /* Ignore the low bit in the target, since it will be | |
13780 | set for a text label. */ | |
13781 | if ((val & 1) != 0) | |
13782 | --val; | |
13783 | } | |
13784 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) | |
13785 | addr -= 4; | |
13786 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
13787 | addr -= 2; | |
13788 | ||
13789 | addr &= ~ (addressT) ((1 << op->shift) - 1); | |
13790 | val -= addr; | |
13791 | ||
13792 | /* Make sure the section winds up with the alignment we have | |
13793 | assumed. */ | |
13794 | if (op->shift > 0) | |
13795 | record_alignment (asec, op->shift); | |
13796 | } | |
13797 | ||
13798 | if (ext | |
13799 | && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype) | |
13800 | || RELAX_MIPS16_DSLOT (fragp->fr_subtype))) | |
13801 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
13802 | _("extended instruction in delay slot")); | |
13803 | ||
13804 | buf = (bfd_byte *) (fragp->fr_literal + fragp->fr_fix); | |
13805 | ||
13806 | if (target_big_endian) | |
13807 | insn = bfd_getb16 (buf); | |
13808 | else | |
13809 | insn = bfd_getl16 (buf); | |
13810 | ||
13811 | mips16_immed (fragp->fr_file, fragp->fr_line, type, val, | |
13812 | RELAX_MIPS16_USER_EXT (fragp->fr_subtype), | |
13813 | small, ext, &insn, &use_extend, &extend); | |
13814 | ||
13815 | if (use_extend) | |
13816 | { | |
874e8986 | 13817 | md_number_to_chars ((char *) buf, 0xf000 | extend, 2); |
252b5132 RH |
13818 | fragp->fr_fix += 2; |
13819 | buf += 2; | |
13820 | } | |
13821 | ||
874e8986 | 13822 | md_number_to_chars ((char *) buf, insn, 2); |
252b5132 RH |
13823 | fragp->fr_fix += 2; |
13824 | buf += 2; | |
13825 | } | |
13826 | else | |
13827 | { | |
13828 | if (fragp->fr_opcode == NULL) | |
13829 | return; | |
13830 | ||
13831 | old = RELAX_OLD (fragp->fr_subtype); | |
13832 | new = RELAX_NEW (fragp->fr_subtype); | |
13833 | fixptr = fragp->fr_literal + fragp->fr_fix; | |
13834 | ||
13835 | if (new > 0) | |
13836 | memcpy (fixptr - old, fixptr, new); | |
13837 | ||
13838 | fragp->fr_fix += new - old; | |
13839 | } | |
13840 | } | |
13841 | ||
13842 | #ifdef OBJ_ELF | |
13843 | ||
13844 | /* This function is called after the relocs have been generated. | |
13845 | We've been storing mips16 text labels as odd. Here we convert them | |
13846 | back to even for the convenience of the debugger. */ | |
13847 | ||
13848 | void | |
13849 | mips_frob_file_after_relocs () | |
13850 | { | |
13851 | asymbol **syms; | |
13852 | unsigned int count, i; | |
13853 | ||
13854 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
13855 | return; | |
13856 | ||
13857 | syms = bfd_get_outsymbols (stdoutput); | |
13858 | count = bfd_get_symcount (stdoutput); | |
13859 | for (i = 0; i < count; i++, syms++) | |
13860 | { | |
13861 | if (elf_symbol (*syms)->internal_elf_sym.st_other == STO_MIPS16 | |
13862 | && ((*syms)->value & 1) != 0) | |
13863 | { | |
13864 | (*syms)->value &= ~1; | |
13865 | /* If the symbol has an odd size, it was probably computed | |
13866 | incorrectly, so adjust that as well. */ | |
13867 | if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0) | |
13868 | ++elf_symbol (*syms)->internal_elf_sym.st_size; | |
13869 | } | |
13870 | } | |
13871 | } | |
13872 | ||
13873 | #endif | |
13874 | ||
13875 | /* This function is called whenever a label is defined. It is used | |
13876 | when handling branch delays; if a branch has a label, we assume we | |
13877 | can not move it. */ | |
13878 | ||
13879 | void | |
13880 | mips_define_label (sym) | |
13881 | symbolS *sym; | |
13882 | { | |
13883 | struct insn_label_list *l; | |
13884 | ||
13885 | if (free_insn_labels == NULL) | |
13886 | l = (struct insn_label_list *) xmalloc (sizeof *l); | |
13887 | else | |
13888 | { | |
13889 | l = free_insn_labels; | |
13890 | free_insn_labels = l->next; | |
13891 | } | |
13892 | ||
13893 | l->label = sym; | |
13894 | l->next = insn_labels; | |
13895 | insn_labels = l; | |
13896 | } | |
13897 | \f | |
13898 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
13899 | ||
13900 | /* Some special processing for a MIPS ELF file. */ | |
13901 | ||
13902 | void | |
13903 | mips_elf_final_processing () | |
13904 | { | |
13905 | /* Write out the register information. */ | |
316f5878 | 13906 | if (mips_abi != N64_ABI) |
252b5132 RH |
13907 | { |
13908 | Elf32_RegInfo s; | |
13909 | ||
13910 | s.ri_gprmask = mips_gprmask; | |
13911 | s.ri_cprmask[0] = mips_cprmask[0]; | |
13912 | s.ri_cprmask[1] = mips_cprmask[1]; | |
13913 | s.ri_cprmask[2] = mips_cprmask[2]; | |
13914 | s.ri_cprmask[3] = mips_cprmask[3]; | |
13915 | /* The gp_value field is set by the MIPS ELF backend. */ | |
13916 | ||
13917 | bfd_mips_elf32_swap_reginfo_out (stdoutput, &s, | |
13918 | ((Elf32_External_RegInfo *) | |
13919 | mips_regmask_frag)); | |
13920 | } | |
13921 | else | |
13922 | { | |
13923 | Elf64_Internal_RegInfo s; | |
13924 | ||
13925 | s.ri_gprmask = mips_gprmask; | |
13926 | s.ri_pad = 0; | |
13927 | s.ri_cprmask[0] = mips_cprmask[0]; | |
13928 | s.ri_cprmask[1] = mips_cprmask[1]; | |
13929 | s.ri_cprmask[2] = mips_cprmask[2]; | |
13930 | s.ri_cprmask[3] = mips_cprmask[3]; | |
13931 | /* The gp_value field is set by the MIPS ELF backend. */ | |
13932 | ||
13933 | bfd_mips_elf64_swap_reginfo_out (stdoutput, &s, | |
13934 | ((Elf64_External_RegInfo *) | |
13935 | mips_regmask_frag)); | |
13936 | } | |
13937 | ||
13938 | /* Set the MIPS ELF flag bits. FIXME: There should probably be some | |
13939 | sort of BFD interface for this. */ | |
13940 | if (mips_any_noreorder) | |
13941 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER; | |
13942 | if (mips_pic != NO_PIC) | |
13943 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC; | |
13944 | ||
98d3f06f | 13945 | /* Set MIPS ELF flags for ASEs. */ |
a4672219 TS |
13946 | if (file_ase_mips16) |
13947 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16; | |
1f25f5d3 CD |
13948 | #if 0 /* XXX FIXME */ |
13949 | if (file_ase_mips3d) | |
13950 | elf_elfheader (stdoutput)->e_flags |= ???; | |
13951 | #endif | |
deec1734 CD |
13952 | if (file_ase_mdmx) |
13953 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX; | |
1f25f5d3 | 13954 | |
bdaaa2e1 | 13955 | /* Set the MIPS ELF ABI flags. */ |
316f5878 | 13956 | if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32) |
252b5132 | 13957 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32; |
316f5878 | 13958 | else if (mips_abi == O64_ABI) |
252b5132 | 13959 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64; |
316f5878 | 13960 | else if (mips_abi == EABI_ABI) |
252b5132 | 13961 | { |
316f5878 | 13962 | if (!file_mips_gp32) |
252b5132 RH |
13963 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64; |
13964 | else | |
13965 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32; | |
13966 | } | |
316f5878 | 13967 | else if (mips_abi == N32_ABI) |
be00bddd TS |
13968 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2; |
13969 | ||
c9914766 | 13970 | /* Nothing to do for N64_ABI. */ |
252b5132 RH |
13971 | |
13972 | if (mips_32bitmode) | |
13973 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE; | |
13974 | } | |
13975 | ||
13976 | #endif /* OBJ_ELF || OBJ_MAYBE_ELF */ | |
13977 | \f | |
beae10d5 KH |
13978 | typedef struct proc { |
13979 | symbolS *isym; | |
13980 | unsigned long reg_mask; | |
13981 | unsigned long reg_offset; | |
13982 | unsigned long fpreg_mask; | |
13983 | unsigned long fpreg_offset; | |
13984 | unsigned long frame_offset; | |
13985 | unsigned long frame_reg; | |
13986 | unsigned long pc_reg; | |
13987 | } procS; | |
252b5132 RH |
13988 | |
13989 | static procS cur_proc; | |
13990 | static procS *cur_proc_ptr; | |
13991 | static int numprocs; | |
13992 | ||
0a9ef439 | 13993 | /* Fill in an rs_align_code fragment. */ |
a19d8eb0 | 13994 | |
0a9ef439 RH |
13995 | void |
13996 | mips_handle_align (fragp) | |
13997 | fragS *fragp; | |
a19d8eb0 | 13998 | { |
0a9ef439 RH |
13999 | if (fragp->fr_type != rs_align_code) |
14000 | return; | |
14001 | ||
14002 | if (mips_opts.mips16) | |
a19d8eb0 CP |
14003 | { |
14004 | static const unsigned char be_nop[] = { 0x65, 0x00 }; | |
14005 | static const unsigned char le_nop[] = { 0x00, 0x65 }; | |
14006 | ||
0a9ef439 RH |
14007 | int bytes; |
14008 | char *p; | |
a19d8eb0 | 14009 | |
0a9ef439 RH |
14010 | bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix; |
14011 | p = fragp->fr_literal + fragp->fr_fix; | |
14012 | ||
14013 | if (bytes & 1) | |
14014 | { | |
14015 | *p++ = 0; | |
f9419b05 | 14016 | fragp->fr_fix++; |
0a9ef439 RH |
14017 | } |
14018 | ||
14019 | memcpy (p, (target_big_endian ? be_nop : le_nop), 2); | |
14020 | fragp->fr_var = 2; | |
a19d8eb0 CP |
14021 | } |
14022 | ||
0a9ef439 | 14023 | /* For mips32, a nop is a zero, which we trivially get by doing nothing. */ |
a19d8eb0 CP |
14024 | } |
14025 | ||
252b5132 RH |
14026 | static void |
14027 | md_obj_begin () | |
14028 | { | |
14029 | } | |
14030 | ||
14031 | static void | |
14032 | md_obj_end () | |
14033 | { | |
14034 | /* check for premature end, nesting errors, etc */ | |
14035 | if (cur_proc_ptr) | |
9a41af64 | 14036 | as_warn (_("missing .end at end of assembly")); |
252b5132 RH |
14037 | } |
14038 | ||
14039 | static long | |
14040 | get_number () | |
14041 | { | |
14042 | int negative = 0; | |
14043 | long val = 0; | |
14044 | ||
14045 | if (*input_line_pointer == '-') | |
14046 | { | |
14047 | ++input_line_pointer; | |
14048 | negative = 1; | |
14049 | } | |
3882b010 | 14050 | if (!ISDIGIT (*input_line_pointer)) |
956cd1d6 | 14051 | as_bad (_("expected simple number")); |
252b5132 RH |
14052 | if (input_line_pointer[0] == '0') |
14053 | { | |
14054 | if (input_line_pointer[1] == 'x') | |
14055 | { | |
14056 | input_line_pointer += 2; | |
3882b010 | 14057 | while (ISXDIGIT (*input_line_pointer)) |
252b5132 RH |
14058 | { |
14059 | val <<= 4; | |
14060 | val |= hex_value (*input_line_pointer++); | |
14061 | } | |
14062 | return negative ? -val : val; | |
14063 | } | |
14064 | else | |
14065 | { | |
14066 | ++input_line_pointer; | |
3882b010 | 14067 | while (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
14068 | { |
14069 | val <<= 3; | |
14070 | val |= *input_line_pointer++ - '0'; | |
14071 | } | |
14072 | return negative ? -val : val; | |
14073 | } | |
14074 | } | |
3882b010 | 14075 | if (!ISDIGIT (*input_line_pointer)) |
252b5132 RH |
14076 | { |
14077 | printf (_(" *input_line_pointer == '%c' 0x%02x\n"), | |
14078 | *input_line_pointer, *input_line_pointer); | |
956cd1d6 | 14079 | as_warn (_("invalid number")); |
252b5132 RH |
14080 | return -1; |
14081 | } | |
3882b010 | 14082 | while (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
14083 | { |
14084 | val *= 10; | |
14085 | val += *input_line_pointer++ - '0'; | |
14086 | } | |
14087 | return negative ? -val : val; | |
14088 | } | |
14089 | ||
14090 | /* The .file directive; just like the usual .file directive, but there | |
c5dd6aab DJ |
14091 | is an initial number which is the ECOFF file index. In the non-ECOFF |
14092 | case .file implies DWARF-2. */ | |
14093 | ||
14094 | static void | |
14095 | s_mips_file (x) | |
14096 | int x ATTRIBUTE_UNUSED; | |
14097 | { | |
ecb4347a DJ |
14098 | static int first_file_directive = 0; |
14099 | ||
c5dd6aab DJ |
14100 | if (ECOFF_DEBUGGING) |
14101 | { | |
14102 | get_number (); | |
14103 | s_app_file (0); | |
14104 | } | |
14105 | else | |
ecb4347a DJ |
14106 | { |
14107 | char *filename; | |
14108 | ||
14109 | filename = dwarf2_directive_file (0); | |
14110 | ||
14111 | /* Versions of GCC up to 3.1 start files with a ".file" | |
14112 | directive even for stabs output. Make sure that this | |
14113 | ".file" is handled. Note that you need a version of GCC | |
14114 | after 3.1 in order to support DWARF-2 on MIPS. */ | |
14115 | if (filename != NULL && ! first_file_directive) | |
14116 | { | |
14117 | (void) new_logical_line (filename, -1); | |
14118 | s_app_file_string (filename); | |
14119 | } | |
14120 | first_file_directive = 1; | |
14121 | } | |
c5dd6aab DJ |
14122 | } |
14123 | ||
14124 | /* The .loc directive, implying DWARF-2. */ | |
252b5132 RH |
14125 | |
14126 | static void | |
c5dd6aab | 14127 | s_mips_loc (x) |
43841e91 | 14128 | int x ATTRIBUTE_UNUSED; |
252b5132 | 14129 | { |
c5dd6aab DJ |
14130 | if (!ECOFF_DEBUGGING) |
14131 | dwarf2_directive_loc (0); | |
252b5132 RH |
14132 | } |
14133 | ||
252b5132 RH |
14134 | /* The .end directive. */ |
14135 | ||
14136 | static void | |
14137 | s_mips_end (x) | |
43841e91 | 14138 | int x ATTRIBUTE_UNUSED; |
252b5132 RH |
14139 | { |
14140 | symbolS *p; | |
252b5132 | 14141 | |
7a621144 DJ |
14142 | /* Following functions need their own .frame and .cprestore directives. */ |
14143 | mips_frame_reg_valid = 0; | |
14144 | mips_cprestore_valid = 0; | |
14145 | ||
252b5132 RH |
14146 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
14147 | { | |
14148 | p = get_symbol (); | |
14149 | demand_empty_rest_of_line (); | |
14150 | } | |
14151 | else | |
14152 | p = NULL; | |
14153 | ||
14949570 | 14154 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0) |
252b5132 RH |
14155 | as_warn (_(".end not in text section")); |
14156 | ||
14157 | if (!cur_proc_ptr) | |
14158 | { | |
14159 | as_warn (_(".end directive without a preceding .ent directive.")); | |
14160 | demand_empty_rest_of_line (); | |
14161 | return; | |
14162 | } | |
14163 | ||
14164 | if (p != NULL) | |
14165 | { | |
14166 | assert (S_GET_NAME (p)); | |
14167 | if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->isym))) | |
14168 | as_warn (_(".end symbol does not match .ent symbol.")); | |
ecb4347a DJ |
14169 | |
14170 | if (debug_type == DEBUG_STABS) | |
14171 | stabs_generate_asm_endfunc (S_GET_NAME (p), | |
14172 | S_GET_NAME (p)); | |
252b5132 RH |
14173 | } |
14174 | else | |
14175 | as_warn (_(".end directive missing or unknown symbol")); | |
14176 | ||
ecb4347a DJ |
14177 | #ifdef OBJ_ELF |
14178 | /* Generate a .pdr section. */ | |
14179 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING) | |
14180 | { | |
14181 | segT saved_seg = now_seg; | |
14182 | subsegT saved_subseg = now_subseg; | |
14183 | valueT dot; | |
14184 | expressionS exp; | |
14185 | char *fragp; | |
252b5132 | 14186 | |
ecb4347a | 14187 | dot = frag_now_fix (); |
252b5132 RH |
14188 | |
14189 | #ifdef md_flush_pending_output | |
ecb4347a | 14190 | md_flush_pending_output (); |
252b5132 RH |
14191 | #endif |
14192 | ||
ecb4347a DJ |
14193 | assert (pdr_seg); |
14194 | subseg_set (pdr_seg, 0); | |
252b5132 | 14195 | |
ecb4347a DJ |
14196 | /* Write the symbol. */ |
14197 | exp.X_op = O_symbol; | |
14198 | exp.X_add_symbol = p; | |
14199 | exp.X_add_number = 0; | |
14200 | emit_expr (&exp, 4); | |
252b5132 | 14201 | |
ecb4347a | 14202 | fragp = frag_more (7 * 4); |
252b5132 | 14203 | |
ecb4347a DJ |
14204 | md_number_to_chars (fragp, (valueT) cur_proc_ptr->reg_mask, 4); |
14205 | md_number_to_chars (fragp + 4, (valueT) cur_proc_ptr->reg_offset, 4); | |
14206 | md_number_to_chars (fragp + 8, (valueT) cur_proc_ptr->fpreg_mask, 4); | |
14207 | md_number_to_chars (fragp + 12, (valueT) cur_proc_ptr->fpreg_offset, 4); | |
14208 | md_number_to_chars (fragp + 16, (valueT) cur_proc_ptr->frame_offset, 4); | |
14209 | md_number_to_chars (fragp + 20, (valueT) cur_proc_ptr->frame_reg, 4); | |
14210 | md_number_to_chars (fragp + 24, (valueT) cur_proc_ptr->pc_reg, 4); | |
252b5132 | 14211 | |
ecb4347a DJ |
14212 | subseg_set (saved_seg, saved_subseg); |
14213 | } | |
14214 | #endif /* OBJ_ELF */ | |
252b5132 RH |
14215 | |
14216 | cur_proc_ptr = NULL; | |
14217 | } | |
14218 | ||
14219 | /* The .aent and .ent directives. */ | |
14220 | ||
14221 | static void | |
14222 | s_mips_ent (aent) | |
14223 | int aent; | |
14224 | { | |
252b5132 | 14225 | symbolS *symbolP; |
252b5132 RH |
14226 | |
14227 | symbolP = get_symbol (); | |
14228 | if (*input_line_pointer == ',') | |
f9419b05 | 14229 | ++input_line_pointer; |
252b5132 | 14230 | SKIP_WHITESPACE (); |
3882b010 | 14231 | if (ISDIGIT (*input_line_pointer) |
d9a62219 | 14232 | || *input_line_pointer == '-') |
874e8986 | 14233 | get_number (); |
252b5132 | 14234 | |
14949570 | 14235 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0) |
252b5132 RH |
14236 | as_warn (_(".ent or .aent not in text section.")); |
14237 | ||
14238 | if (!aent && cur_proc_ptr) | |
9a41af64 | 14239 | as_warn (_("missing .end")); |
252b5132 RH |
14240 | |
14241 | if (!aent) | |
14242 | { | |
7a621144 DJ |
14243 | /* This function needs its own .frame and .cprestore directives. */ |
14244 | mips_frame_reg_valid = 0; | |
14245 | mips_cprestore_valid = 0; | |
14246 | ||
252b5132 RH |
14247 | cur_proc_ptr = &cur_proc; |
14248 | memset (cur_proc_ptr, '\0', sizeof (procS)); | |
14249 | ||
14250 | cur_proc_ptr->isym = symbolP; | |
14251 | ||
49309057 | 14252 | symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION; |
252b5132 | 14253 | |
f9419b05 | 14254 | ++numprocs; |
ecb4347a DJ |
14255 | |
14256 | if (debug_type == DEBUG_STABS) | |
14257 | stabs_generate_asm_func (S_GET_NAME (symbolP), | |
14258 | S_GET_NAME (symbolP)); | |
252b5132 RH |
14259 | } |
14260 | ||
14261 | demand_empty_rest_of_line (); | |
14262 | } | |
14263 | ||
14264 | /* The .frame directive. If the mdebug section is present (IRIX 5 native) | |
bdaaa2e1 | 14265 | then ecoff.c (ecoff_directive_frame) is used. For embedded targets, |
252b5132 | 14266 | s_mips_frame is used so that we can set the PDR information correctly. |
bdaaa2e1 | 14267 | We can't use the ecoff routines because they make reference to the ecoff |
252b5132 RH |
14268 | symbol table (in the mdebug section). */ |
14269 | ||
14270 | static void | |
14271 | s_mips_frame (ignore) | |
2b3c5a5d | 14272 | int ignore ATTRIBUTE_UNUSED; |
252b5132 | 14273 | { |
ecb4347a DJ |
14274 | #ifdef OBJ_ELF |
14275 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING) | |
14276 | { | |
14277 | long val; | |
252b5132 | 14278 | |
ecb4347a DJ |
14279 | if (cur_proc_ptr == (procS *) NULL) |
14280 | { | |
14281 | as_warn (_(".frame outside of .ent")); | |
14282 | demand_empty_rest_of_line (); | |
14283 | return; | |
14284 | } | |
252b5132 | 14285 | |
ecb4347a DJ |
14286 | cur_proc_ptr->frame_reg = tc_get_register (1); |
14287 | ||
14288 | SKIP_WHITESPACE (); | |
14289 | if (*input_line_pointer++ != ',' | |
14290 | || get_absolute_expression_and_terminator (&val) != ',') | |
14291 | { | |
14292 | as_warn (_("Bad .frame directive")); | |
14293 | --input_line_pointer; | |
14294 | demand_empty_rest_of_line (); | |
14295 | return; | |
14296 | } | |
252b5132 | 14297 | |
ecb4347a DJ |
14298 | cur_proc_ptr->frame_offset = val; |
14299 | cur_proc_ptr->pc_reg = tc_get_register (0); | |
252b5132 | 14300 | |
252b5132 | 14301 | demand_empty_rest_of_line (); |
252b5132 | 14302 | } |
ecb4347a DJ |
14303 | else |
14304 | #endif /* OBJ_ELF */ | |
14305 | s_ignore (ignore); | |
252b5132 RH |
14306 | } |
14307 | ||
bdaaa2e1 KH |
14308 | /* The .fmask and .mask directives. If the mdebug section is present |
14309 | (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For | |
252b5132 | 14310 | embedded targets, s_mips_mask is used so that we can set the PDR |
bdaaa2e1 | 14311 | information correctly. We can't use the ecoff routines because they |
252b5132 RH |
14312 | make reference to the ecoff symbol table (in the mdebug section). */ |
14313 | ||
14314 | static void | |
14315 | s_mips_mask (reg_type) | |
14316 | char reg_type; | |
14317 | { | |
ecb4347a DJ |
14318 | #ifdef OBJ_ELF |
14319 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING) | |
252b5132 | 14320 | { |
ecb4347a | 14321 | long mask, off; |
252b5132 | 14322 | |
ecb4347a DJ |
14323 | if (cur_proc_ptr == (procS *) NULL) |
14324 | { | |
14325 | as_warn (_(".mask/.fmask outside of .ent")); | |
14326 | demand_empty_rest_of_line (); | |
14327 | return; | |
14328 | } | |
252b5132 | 14329 | |
ecb4347a DJ |
14330 | if (get_absolute_expression_and_terminator (&mask) != ',') |
14331 | { | |
14332 | as_warn (_("Bad .mask/.fmask directive")); | |
14333 | --input_line_pointer; | |
14334 | demand_empty_rest_of_line (); | |
14335 | return; | |
14336 | } | |
252b5132 | 14337 | |
ecb4347a DJ |
14338 | off = get_absolute_expression (); |
14339 | ||
14340 | if (reg_type == 'F') | |
14341 | { | |
14342 | cur_proc_ptr->fpreg_mask = mask; | |
14343 | cur_proc_ptr->fpreg_offset = off; | |
14344 | } | |
14345 | else | |
14346 | { | |
14347 | cur_proc_ptr->reg_mask = mask; | |
14348 | cur_proc_ptr->reg_offset = off; | |
14349 | } | |
14350 | ||
14351 | demand_empty_rest_of_line (); | |
252b5132 RH |
14352 | } |
14353 | else | |
ecb4347a DJ |
14354 | #endif /* OBJ_ELF */ |
14355 | s_ignore (reg_type); | |
252b5132 RH |
14356 | } |
14357 | ||
14358 | /* The .loc directive. */ | |
14359 | ||
14360 | #if 0 | |
14361 | static void | |
14362 | s_loc (x) | |
14363 | int x; | |
14364 | { | |
14365 | symbolS *symbolP; | |
14366 | int lineno; | |
14367 | int addroff; | |
14368 | ||
14369 | assert (now_seg == text_section); | |
14370 | ||
14371 | lineno = get_number (); | |
14372 | addroff = frag_now_fix (); | |
14373 | ||
14374 | symbolP = symbol_new ("", N_SLINE, addroff, frag_now); | |
14375 | S_SET_TYPE (symbolP, N_SLINE); | |
14376 | S_SET_OTHER (symbolP, 0); | |
14377 | S_SET_DESC (symbolP, lineno); | |
14378 | symbolP->sy_segment = now_seg; | |
14379 | } | |
14380 | #endif | |
e7af610e | 14381 | |
316f5878 RS |
14382 | /* A table describing all the processors gas knows about. Names are |
14383 | matched in the order listed. | |
e7af610e | 14384 | |
316f5878 RS |
14385 | To ease comparison, please keep this table in the same order as |
14386 | gcc's mips_cpu_info_table[]. */ | |
e972090a NC |
14387 | static const struct mips_cpu_info mips_cpu_info_table[] = |
14388 | { | |
316f5878 RS |
14389 | /* Entries for generic ISAs */ |
14390 | { "mips1", 1, ISA_MIPS1, CPU_R3000 }, | |
14391 | { "mips2", 1, ISA_MIPS2, CPU_R6000 }, | |
14392 | { "mips3", 1, ISA_MIPS3, CPU_R4000 }, | |
14393 | { "mips4", 1, ISA_MIPS4, CPU_R8000 }, | |
14394 | { "mips5", 1, ISA_MIPS5, CPU_MIPS5 }, | |
14395 | { "mips32", 1, ISA_MIPS32, CPU_MIPS32 }, | |
af7ee8bf | 14396 | { "mips32r2", 1, ISA_MIPS32R2, CPU_MIPS32R2 }, |
316f5878 RS |
14397 | { "mips64", 1, ISA_MIPS64, CPU_MIPS64 }, |
14398 | ||
14399 | /* MIPS I */ | |
14400 | { "r3000", 0, ISA_MIPS1, CPU_R3000 }, | |
14401 | { "r2000", 0, ISA_MIPS1, CPU_R3000 }, | |
14402 | { "r3900", 0, ISA_MIPS1, CPU_R3900 }, | |
14403 | ||
14404 | /* MIPS II */ | |
14405 | { "r6000", 0, ISA_MIPS2, CPU_R6000 }, | |
14406 | ||
14407 | /* MIPS III */ | |
14408 | { "r4000", 0, ISA_MIPS3, CPU_R4000 }, | |
14409 | { "r4010", 0, ISA_MIPS2, CPU_R4010 }, | |
14410 | { "vr4100", 0, ISA_MIPS3, CPU_VR4100 }, | |
14411 | { "vr4111", 0, ISA_MIPS3, CPU_R4111 }, | |
60b63b72 RS |
14412 | { "vr4120", 0, ISA_MIPS3, CPU_VR4120 }, |
14413 | { "vr4130", 0, ISA_MIPS3, CPU_VR4120 }, | |
14414 | { "vr4181", 0, ISA_MIPS3, CPU_R4111 }, | |
316f5878 RS |
14415 | { "vr4300", 0, ISA_MIPS3, CPU_R4300 }, |
14416 | { "r4400", 0, ISA_MIPS3, CPU_R4400 }, | |
14417 | { "r4600", 0, ISA_MIPS3, CPU_R4600 }, | |
14418 | { "orion", 0, ISA_MIPS3, CPU_R4600 }, | |
14419 | { "r4650", 0, ISA_MIPS3, CPU_R4650 }, | |
14420 | ||
14421 | /* MIPS IV */ | |
14422 | { "r8000", 0, ISA_MIPS4, CPU_R8000 }, | |
14423 | { "r10000", 0, ISA_MIPS4, CPU_R10000 }, | |
14424 | { "r12000", 0, ISA_MIPS4, CPU_R12000 }, | |
14425 | { "vr5000", 0, ISA_MIPS4, CPU_R5000 }, | |
60b63b72 RS |
14426 | { "vr5400", 0, ISA_MIPS4, CPU_VR5400 }, |
14427 | { "vr5500", 0, ISA_MIPS4, CPU_VR5500 }, | |
316f5878 RS |
14428 | { "rm5200", 0, ISA_MIPS4, CPU_R5000 }, |
14429 | { "rm5230", 0, ISA_MIPS4, CPU_R5000 }, | |
14430 | { "rm5231", 0, ISA_MIPS4, CPU_R5000 }, | |
14431 | { "rm5261", 0, ISA_MIPS4, CPU_R5000 }, | |
14432 | { "rm5721", 0, ISA_MIPS4, CPU_R5000 }, | |
14433 | { "r7000", 0, ISA_MIPS4, CPU_R5000 }, | |
14434 | ||
14435 | /* MIPS 32 */ | |
14436 | { "4kc", 0, ISA_MIPS32, CPU_MIPS32, }, | |
14437 | { "4km", 0, ISA_MIPS32, CPU_MIPS32 }, | |
14438 | { "4kp", 0, ISA_MIPS32, CPU_MIPS32 }, | |
e7af610e | 14439 | |
316f5878 RS |
14440 | /* MIPS 64 */ |
14441 | { "5kc", 0, ISA_MIPS64, CPU_MIPS64 }, | |
14442 | { "20kc", 0, ISA_MIPS64, CPU_MIPS64 }, | |
e7af610e | 14443 | |
c7a23324 | 14444 | /* Broadcom SB-1 CPU core */ |
316f5878 | 14445 | { "sb1", 0, ISA_MIPS64, CPU_SB1 }, |
e7af610e | 14446 | |
316f5878 RS |
14447 | /* End marker */ |
14448 | { NULL, 0, 0, 0 } | |
14449 | }; | |
e7af610e | 14450 | |
84ea6cf2 | 14451 | |
316f5878 RS |
14452 | /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL |
14453 | with a final "000" replaced by "k". Ignore case. | |
e7af610e | 14454 | |
316f5878 | 14455 | Note: this function is shared between GCC and GAS. */ |
c6c98b38 | 14456 | |
b34976b6 | 14457 | static bfd_boolean |
316f5878 RS |
14458 | mips_strict_matching_cpu_name_p (canonical, given) |
14459 | const char *canonical, *given; | |
14460 | { | |
14461 | while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical)) | |
14462 | given++, canonical++; | |
14463 | ||
14464 | return ((*given == 0 && *canonical == 0) | |
14465 | || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0)); | |
14466 | } | |
14467 | ||
14468 | ||
14469 | /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied | |
14470 | CPU name. We've traditionally allowed a lot of variation here. | |
14471 | ||
14472 | Note: this function is shared between GCC and GAS. */ | |
14473 | ||
b34976b6 | 14474 | static bfd_boolean |
316f5878 RS |
14475 | mips_matching_cpu_name_p (canonical, given) |
14476 | const char *canonical, *given; | |
14477 | { | |
14478 | /* First see if the name matches exactly, or with a final "000" | |
14479 | turned into "k". */ | |
14480 | if (mips_strict_matching_cpu_name_p (canonical, given)) | |
b34976b6 | 14481 | return TRUE; |
316f5878 RS |
14482 | |
14483 | /* If not, try comparing based on numerical designation alone. | |
14484 | See if GIVEN is an unadorned number, or 'r' followed by a number. */ | |
14485 | if (TOLOWER (*given) == 'r') | |
14486 | given++; | |
14487 | if (!ISDIGIT (*given)) | |
b34976b6 | 14488 | return FALSE; |
316f5878 RS |
14489 | |
14490 | /* Skip over some well-known prefixes in the canonical name, | |
14491 | hoping to find a number there too. */ | |
14492 | if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r') | |
14493 | canonical += 2; | |
14494 | else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm') | |
14495 | canonical += 2; | |
14496 | else if (TOLOWER (canonical[0]) == 'r') | |
14497 | canonical += 1; | |
14498 | ||
14499 | return mips_strict_matching_cpu_name_p (canonical, given); | |
14500 | } | |
14501 | ||
14502 | ||
14503 | /* Parse an option that takes the name of a processor as its argument. | |
14504 | OPTION is the name of the option and CPU_STRING is the argument. | |
14505 | Return the corresponding processor enumeration if the CPU_STRING is | |
14506 | recognized, otherwise report an error and return null. | |
14507 | ||
14508 | A similar function exists in GCC. */ | |
e7af610e NC |
14509 | |
14510 | static const struct mips_cpu_info * | |
316f5878 RS |
14511 | mips_parse_cpu (option, cpu_string) |
14512 | const char *option, *cpu_string; | |
e7af610e | 14513 | { |
316f5878 | 14514 | const struct mips_cpu_info *p; |
e7af610e | 14515 | |
316f5878 RS |
14516 | /* 'from-abi' selects the most compatible architecture for the given |
14517 | ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the | |
14518 | EABIs, we have to decide whether we're using the 32-bit or 64-bit | |
14519 | version. Look first at the -mgp options, if given, otherwise base | |
14520 | the choice on MIPS_DEFAULT_64BIT. | |
e7af610e | 14521 | |
316f5878 RS |
14522 | Treat NO_ABI like the EABIs. One reason to do this is that the |
14523 | plain 'mips' and 'mips64' configs have 'from-abi' as their default | |
14524 | architecture. This code picks MIPS I for 'mips' and MIPS III for | |
14525 | 'mips64', just as we did in the days before 'from-abi'. */ | |
14526 | if (strcasecmp (cpu_string, "from-abi") == 0) | |
14527 | { | |
14528 | if (ABI_NEEDS_32BIT_REGS (mips_abi)) | |
14529 | return mips_cpu_info_from_isa (ISA_MIPS1); | |
14530 | ||
14531 | if (ABI_NEEDS_64BIT_REGS (mips_abi)) | |
14532 | return mips_cpu_info_from_isa (ISA_MIPS3); | |
14533 | ||
14534 | if (file_mips_gp32 >= 0) | |
14535 | return mips_cpu_info_from_isa (file_mips_gp32 ? ISA_MIPS1 : ISA_MIPS3); | |
14536 | ||
14537 | return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT | |
14538 | ? ISA_MIPS3 | |
14539 | : ISA_MIPS1); | |
14540 | } | |
14541 | ||
14542 | /* 'default' has traditionally been a no-op. Probably not very useful. */ | |
14543 | if (strcasecmp (cpu_string, "default") == 0) | |
14544 | return 0; | |
14545 | ||
14546 | for (p = mips_cpu_info_table; p->name != 0; p++) | |
14547 | if (mips_matching_cpu_name_p (p->name, cpu_string)) | |
14548 | return p; | |
14549 | ||
14550 | as_bad ("Bad value (%s) for %s", cpu_string, option); | |
14551 | return 0; | |
e7af610e NC |
14552 | } |
14553 | ||
316f5878 RS |
14554 | /* Return the canonical processor information for ISA (a member of the |
14555 | ISA_MIPS* enumeration). */ | |
14556 | ||
e7af610e NC |
14557 | static const struct mips_cpu_info * |
14558 | mips_cpu_info_from_isa (isa) | |
14559 | int isa; | |
14560 | { | |
14561 | int i; | |
14562 | ||
14563 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
14564 | if (mips_cpu_info_table[i].is_isa | |
316f5878 | 14565 | && isa == mips_cpu_info_table[i].isa) |
e7af610e NC |
14566 | return (&mips_cpu_info_table[i]); |
14567 | ||
e972090a | 14568 | return NULL; |
e7af610e | 14569 | } |
316f5878 RS |
14570 | \f |
14571 | static void | |
14572 | show (stream, string, col_p, first_p) | |
14573 | FILE *stream; | |
14574 | const char *string; | |
14575 | int *col_p; | |
14576 | int *first_p; | |
14577 | { | |
14578 | if (*first_p) | |
14579 | { | |
14580 | fprintf (stream, "%24s", ""); | |
14581 | *col_p = 24; | |
14582 | } | |
14583 | else | |
14584 | { | |
14585 | fprintf (stream, ", "); | |
14586 | *col_p += 2; | |
14587 | } | |
e7af610e | 14588 | |
316f5878 RS |
14589 | if (*col_p + strlen (string) > 72) |
14590 | { | |
14591 | fprintf (stream, "\n%24s", ""); | |
14592 | *col_p = 24; | |
14593 | } | |
14594 | ||
14595 | fprintf (stream, "%s", string); | |
14596 | *col_p += strlen (string); | |
14597 | ||
14598 | *first_p = 0; | |
14599 | } | |
14600 | ||
14601 | void | |
14602 | md_show_usage (stream) | |
14603 | FILE *stream; | |
e7af610e | 14604 | { |
316f5878 RS |
14605 | int column, first; |
14606 | size_t i; | |
14607 | ||
14608 | fprintf (stream, _("\ | |
14609 | MIPS options:\n\ | |
14610 | -membedded-pic generate embedded position independent code\n\ | |
14611 | -EB generate big endian output\n\ | |
14612 | -EL generate little endian output\n\ | |
14613 | -g, -g2 do not remove unneeded NOPs or swap branches\n\ | |
14614 | -G NUM allow referencing objects up to NUM bytes\n\ | |
14615 | implicitly with the gp register [default 8]\n")); | |
14616 | fprintf (stream, _("\ | |
14617 | -mips1 generate MIPS ISA I instructions\n\ | |
14618 | -mips2 generate MIPS ISA II instructions\n\ | |
14619 | -mips3 generate MIPS ISA III instructions\n\ | |
14620 | -mips4 generate MIPS ISA IV instructions\n\ | |
14621 | -mips5 generate MIPS ISA V instructions\n\ | |
14622 | -mips32 generate MIPS32 ISA instructions\n\ | |
af7ee8bf | 14623 | -mips32r2 generate MIPS32 release 2 ISA instructions\n\ |
316f5878 RS |
14624 | -mips64 generate MIPS64 ISA instructions\n\ |
14625 | -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n")); | |
14626 | ||
14627 | first = 1; | |
e7af610e NC |
14628 | |
14629 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
316f5878 RS |
14630 | show (stream, mips_cpu_info_table[i].name, &column, &first); |
14631 | show (stream, "from-abi", &column, &first); | |
14632 | fputc ('\n', stream); | |
e7af610e | 14633 | |
316f5878 RS |
14634 | fprintf (stream, _("\ |
14635 | -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\ | |
14636 | -no-mCPU don't generate code specific to CPU.\n\ | |
14637 | For -mCPU and -no-mCPU, CPU must be one of:\n")); | |
14638 | ||
14639 | first = 1; | |
14640 | ||
14641 | show (stream, "3900", &column, &first); | |
14642 | show (stream, "4010", &column, &first); | |
14643 | show (stream, "4100", &column, &first); | |
14644 | show (stream, "4650", &column, &first); | |
14645 | fputc ('\n', stream); | |
14646 | ||
14647 | fprintf (stream, _("\ | |
14648 | -mips16 generate mips16 instructions\n\ | |
14649 | -no-mips16 do not generate mips16 instructions\n")); | |
14650 | fprintf (stream, _("\ | |
14651 | -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\ | |
14652 | -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\ | |
14653 | -O0 remove unneeded NOPs, do not swap branches\n\ | |
14654 | -O remove unneeded NOPs and swap branches\n\ | |
14655 | -n warn about NOPs generated from macros\n\ | |
14656 | --[no-]construct-floats [dis]allow floating point values to be constructed\n\ | |
14657 | --trap, --no-break trap exception on div by 0 and mult overflow\n\ | |
14658 | --break, --no-trap break exception on div by 0 and mult overflow\n")); | |
14659 | #ifdef OBJ_ELF | |
14660 | fprintf (stream, _("\ | |
14661 | -KPIC, -call_shared generate SVR4 position independent code\n\ | |
14662 | -non_shared do not generate position independent code\n\ | |
14663 | -xgot assume a 32 bit GOT\n\ | |
14664 | -mabi=ABI create ABI conformant object file for:\n")); | |
14665 | ||
14666 | first = 1; | |
14667 | ||
14668 | show (stream, "32", &column, &first); | |
14669 | show (stream, "o64", &column, &first); | |
14670 | show (stream, "n32", &column, &first); | |
14671 | show (stream, "64", &column, &first); | |
14672 | show (stream, "eabi", &column, &first); | |
14673 | ||
14674 | fputc ('\n', stream); | |
14675 | ||
14676 | fprintf (stream, _("\ | |
14677 | -32 create o32 ABI object file (default)\n\ | |
14678 | -n32 create n32 ABI object file\n\ | |
14679 | -64 create 64 ABI object file\n")); | |
14680 | #endif | |
e7af610e | 14681 | } |
14e777e0 KB |
14682 | |
14683 | enum dwarf2_format | |
14684 | mips_dwarf2_format () | |
14685 | { | |
14686 | if (mips_abi == N64_ABI) | |
1de5b6a1 AO |
14687 | { |
14688 | #ifdef TE_IRIX | |
14689 | return dwarf2_format_64bit_irix; | |
14690 | #else | |
14691 | return dwarf2_format_64bit; | |
14692 | #endif | |
14693 | } | |
14e777e0 KB |
14694 | else |
14695 | return dwarf2_format_32bit; | |
14696 | } |