Fixes a problem generating relocs for thumb function calls to local symbols defined...
[deliverable/binutils-gdb.git] / gas / config / tc-mips.c
CommitLineData
252b5132 1/* tc-mips.c -- assemble code for a MIPS chip.
b90efa5b 2 Copyright (C) 1993-2015 Free Software Foundation, Inc.
252b5132
RH
3 Contributed by the OSF and Ralph Campbell.
4 Written by Keith Knowles and Ralph Campbell, working independently.
5 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
6 Support.
7
8 This file is part of GAS.
9
10 GAS is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
ec2655a6 12 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH
13 any later version.
14
15 GAS is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
19
20 You should have received a copy of the GNU General Public License
21 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC
22 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
23 02110-1301, USA. */
252b5132
RH
24
25#include "as.h"
26#include "config.h"
27#include "subsegs.h"
3882b010 28#include "safe-ctype.h"
252b5132 29
252b5132
RH
30#include "opcode/mips.h"
31#include "itbl-ops.h"
c5dd6aab 32#include "dwarf2dbg.h"
5862107c 33#include "dw2gencfi.h"
252b5132 34
42429eac
RS
35/* Check assumptions made in this file. */
36typedef char static_assert1[sizeof (offsetT) < 8 ? -1 : 1];
37typedef char static_assert2[sizeof (valueT) < 8 ? -1 : 1];
38
252b5132
RH
39#ifdef DEBUG
40#define DBG(x) printf x
41#else
42#define DBG(x)
43#endif
44
263b2574 45#define streq(a, b) (strcmp (a, b) == 0)
46
9e12b7a2
RS
47#define SKIP_SPACE_TABS(S) \
48 do { while (*(S) == ' ' || *(S) == '\t') ++(S); } while (0)
49
252b5132 50/* Clean up namespace so we can include obj-elf.h too. */
17a2f251
TS
51static int mips_output_flavor (void);
52static int mips_output_flavor (void) { return OUTPUT_FLAVOR; }
252b5132
RH
53#undef OBJ_PROCESS_STAB
54#undef OUTPUT_FLAVOR
55#undef S_GET_ALIGN
56#undef S_GET_SIZE
57#undef S_SET_ALIGN
58#undef S_SET_SIZE
252b5132
RH
59#undef obj_frob_file
60#undef obj_frob_file_after_relocs
61#undef obj_frob_symbol
62#undef obj_pop_insert
63#undef obj_sec_sym_ok_for_reloc
64#undef OBJ_COPY_SYMBOL_ATTRIBUTES
65
66#include "obj-elf.h"
67/* Fix any of them that we actually care about. */
68#undef OUTPUT_FLAVOR
69#define OUTPUT_FLAVOR mips_output_flavor()
252b5132 70
252b5132 71#include "elf/mips.h"
252b5132
RH
72
73#ifndef ECOFF_DEBUGGING
74#define NO_ECOFF_DEBUGGING
75#define ECOFF_DEBUGGING 0
76#endif
77
ecb4347a
DJ
78int mips_flag_mdebug = -1;
79
dcd410fe
RO
80/* Control generation of .pdr sections. Off by default on IRIX: the native
81 linker doesn't know about and discards them, but relocations against them
82 remain, leading to rld crashes. */
83#ifdef TE_IRIX
84int mips_flag_pdr = FALSE;
85#else
86int mips_flag_pdr = TRUE;
87#endif
88
252b5132
RH
89#include "ecoff.h"
90
252b5132 91static char *mips_regmask_frag;
351cdf24 92static char *mips_flags_frag;
252b5132 93
85b51719 94#define ZERO 0
741fe287 95#define ATREG 1
df58fc94
RS
96#define S0 16
97#define S7 23
252b5132
RH
98#define TREG 24
99#define PIC_CALL_REG 25
100#define KT0 26
101#define KT1 27
102#define GP 28
103#define SP 29
104#define FP 30
105#define RA 31
106
107#define ILLEGAL_REG (32)
108
741fe287
MR
109#define AT mips_opts.at
110
252b5132
RH
111extern int target_big_endian;
112
252b5132 113/* The name of the readonly data section. */
e8044f35 114#define RDATA_SECTION_NAME ".rodata"
252b5132 115
a4e06468
RS
116/* Ways in which an instruction can be "appended" to the output. */
117enum append_method {
118 /* Just add it normally. */
119 APPEND_ADD,
120
121 /* Add it normally and then add a nop. */
122 APPEND_ADD_WITH_NOP,
123
124 /* Turn an instruction with a delay slot into a "compact" version. */
125 APPEND_ADD_COMPACT,
126
127 /* Insert the instruction before the last one. */
128 APPEND_SWAP
129};
130
47e39b9d
RS
131/* Information about an instruction, including its format, operands
132 and fixups. */
133struct mips_cl_insn
134{
135 /* The opcode's entry in mips_opcodes or mips16_opcodes. */
136 const struct mips_opcode *insn_mo;
137
47e39b9d 138 /* The 16-bit or 32-bit bitstring of the instruction itself. This is
5c04167a
RS
139 a copy of INSN_MO->match with the operands filled in. If we have
140 decided to use an extended MIPS16 instruction, this includes the
141 extension. */
47e39b9d
RS
142 unsigned long insn_opcode;
143
144 /* The frag that contains the instruction. */
145 struct frag *frag;
146
147 /* The offset into FRAG of the first instruction byte. */
148 long where;
149
150 /* The relocs associated with the instruction, if any. */
151 fixS *fixp[3];
152
a38419a5
RS
153 /* True if this entry cannot be moved from its current position. */
154 unsigned int fixed_p : 1;
47e39b9d 155
708587a4 156 /* True if this instruction occurred in a .set noreorder block. */
47e39b9d
RS
157 unsigned int noreorder_p : 1;
158
2fa15973
RS
159 /* True for mips16 instructions that jump to an absolute address. */
160 unsigned int mips16_absolute_jump_p : 1;
15be625d
CM
161
162 /* True if this instruction is complete. */
163 unsigned int complete_p : 1;
e407c74b
NC
164
165 /* True if this instruction is cleared from history by unconditional
166 branch. */
167 unsigned int cleared_p : 1;
47e39b9d
RS
168};
169
a325df1d
TS
170/* The ABI to use. */
171enum mips_abi_level
172{
173 NO_ABI = 0,
174 O32_ABI,
175 O64_ABI,
176 N32_ABI,
177 N64_ABI,
178 EABI_ABI
179};
180
181/* MIPS ABI we are using for this output file. */
316f5878 182static enum mips_abi_level mips_abi = NO_ABI;
a325df1d 183
143d77c5
EC
184/* Whether or not we have code that can call pic code. */
185int mips_abicalls = FALSE;
186
aa6975fb
ILT
187/* Whether or not we have code which can be put into a shared
188 library. */
189static bfd_boolean mips_in_shared = TRUE;
190
252b5132
RH
191/* This is the set of options which may be modified by the .set
192 pseudo-op. We use a struct so that .set push and .set pop are more
193 reliable. */
194
e972090a
NC
195struct mips_set_options
196{
252b5132
RH
197 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
198 if it has not been initialized. Changed by `.set mipsN', and the
199 -mipsN command line option, and the default CPU. */
200 int isa;
846ef2d0
RS
201 /* Enabled Application Specific Extensions (ASEs). Changed by `.set
202 <asename>', by command line options, and based on the default
203 architecture. */
204 int ase;
252b5132
RH
205 /* Whether we are assembling for the mips16 processor. 0 if we are
206 not, 1 if we are, and -1 if the value has not been initialized.
207 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
208 -nomips16 command line options, and the default CPU. */
209 int mips16;
df58fc94
RS
210 /* Whether we are assembling for the mipsMIPS ASE. 0 if we are not,
211 1 if we are, and -1 if the value has not been initialized. Changed
212 by `.set micromips' and `.set nomicromips', and the -mmicromips
213 and -mno-micromips command line options, and the default CPU. */
214 int micromips;
252b5132
RH
215 /* Non-zero if we should not reorder instructions. Changed by `.set
216 reorder' and `.set noreorder'. */
217 int noreorder;
741fe287
MR
218 /* Non-zero if we should not permit the register designated "assembler
219 temporary" to be used in instructions. The value is the register
220 number, normally $at ($1). Changed by `.set at=REG', `.set noat'
221 (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */
222 unsigned int at;
252b5132
RH
223 /* Non-zero if we should warn when a macro instruction expands into
224 more than one machine instruction. Changed by `.set nomacro' and
225 `.set macro'. */
226 int warn_about_macros;
227 /* Non-zero if we should not move instructions. Changed by `.set
228 move', `.set volatile', `.set nomove', and `.set novolatile'. */
229 int nomove;
230 /* Non-zero if we should not optimize branches by moving the target
231 of the branch into the delay slot. Actually, we don't perform
232 this optimization anyhow. Changed by `.set bopt' and `.set
233 nobopt'. */
234 int nobopt;
235 /* Non-zero if we should not autoextend mips16 instructions.
236 Changed by `.set autoextend' and `.set noautoextend'. */
237 int noautoextend;
833794fc
MR
238 /* True if we should only emit 32-bit microMIPS instructions.
239 Changed by `.set insn32' and `.set noinsn32', and the -minsn32
240 and -mno-insn32 command line options. */
241 bfd_boolean insn32;
a325df1d
TS
242 /* Restrict general purpose registers and floating point registers
243 to 32 bit. This is initially determined when -mgp32 or -mfp32
244 is passed but can changed if the assembler code uses .set mipsN. */
bad1aba3 245 int gp;
0b35dfee 246 int fp;
fef14a42
TS
247 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
248 command line option, and the default CPU. */
249 int arch;
aed1a261
RS
250 /* True if ".set sym32" is in effect. */
251 bfd_boolean sym32;
037b32b9
AN
252 /* True if floating-point operations are not allowed. Changed by .set
253 softfloat or .set hardfloat, by command line options -msoft-float or
254 -mhard-float. The default is false. */
255 bfd_boolean soft_float;
256
257 /* True if only single-precision floating-point operations are allowed.
258 Changed by .set singlefloat or .set doublefloat, command-line options
259 -msingle-float or -mdouble-float. The default is false. */
260 bfd_boolean single_float;
351cdf24
MF
261
262 /* 1 if single-precision operations on odd-numbered registers are
263 allowed. */
264 int oddspreg;
252b5132
RH
265};
266
919731af 267/* Specifies whether module level options have been checked yet. */
268static bfd_boolean file_mips_opts_checked = FALSE;
269
7361da2c
AB
270/* Do we support nan2008? 0 if we don't, 1 if we do, and -1 if the
271 value has not been initialized. Changed by `.nan legacy' and
272 `.nan 2008', and the -mnan=legacy and -mnan=2008 command line
273 options, and the default CPU. */
274static int mips_nan2008 = -1;
a325df1d 275
0b35dfee 276/* This is the struct we use to hold the module level set of options.
bad1aba3 277 Note that we must set the isa field to ISA_UNKNOWN and the ASE, gp and
0b35dfee 278 fp fields to -1 to indicate that they have not been initialized. */
037b32b9 279
0b35dfee 280static struct mips_set_options file_mips_opts =
281{
282 /* isa */ ISA_UNKNOWN, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1,
283 /* noreorder */ 0, /* at */ ATREG, /* warn_about_macros */ 0,
284 /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE,
bad1aba3 285 /* gp */ -1, /* fp */ -1, /* arch */ CPU_UNKNOWN, /* sym32 */ FALSE,
351cdf24 286 /* soft_float */ FALSE, /* single_float */ FALSE, /* oddspreg */ -1
0b35dfee 287};
252b5132 288
0b35dfee 289/* This is similar to file_mips_opts, but for the current set of options. */
ba92f887 290
e972090a
NC
291static struct mips_set_options mips_opts =
292{
846ef2d0 293 /* isa */ ISA_UNKNOWN, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1,
b015e599 294 /* noreorder */ 0, /* at */ ATREG, /* warn_about_macros */ 0,
833794fc 295 /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE,
bad1aba3 296 /* gp */ -1, /* fp */ -1, /* arch */ CPU_UNKNOWN, /* sym32 */ FALSE,
351cdf24 297 /* soft_float */ FALSE, /* single_float */ FALSE, /* oddspreg */ -1
e7af610e 298};
252b5132 299
846ef2d0
RS
300/* Which bits of file_ase were explicitly set or cleared by ASE options. */
301static unsigned int file_ase_explicit;
302
252b5132
RH
303/* These variables are filled in with the masks of registers used.
304 The object format code reads them and puts them in the appropriate
305 place. */
306unsigned long mips_gprmask;
307unsigned long mips_cprmask[4];
308
738f4d98 309/* True if any MIPS16 code was produced. */
a4672219
TS
310static int file_ase_mips16;
311
3994f87e
TS
312#define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \
313 || mips_opts.isa == ISA_MIPS32R2 \
ae52f483
AB
314 || mips_opts.isa == ISA_MIPS32R3 \
315 || mips_opts.isa == ISA_MIPS32R5 \
3994f87e 316 || mips_opts.isa == ISA_MIPS64 \
ae52f483
AB
317 || mips_opts.isa == ISA_MIPS64R2 \
318 || mips_opts.isa == ISA_MIPS64R3 \
319 || mips_opts.isa == ISA_MIPS64R5)
3994f87e 320
df58fc94
RS
321/* True if any microMIPS code was produced. */
322static int file_ase_micromips;
323
b12dd2e4
CF
324/* True if we want to create R_MIPS_JALR for jalr $25. */
325#ifdef TE_IRIX
1180b5a4 326#define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI
b12dd2e4 327#else
1180b5a4
RS
328/* As a GNU extension, we use R_MIPS_JALR for o32 too. However,
329 because there's no place for any addend, the only acceptable
330 expression is a bare symbol. */
331#define MIPS_JALR_HINT_P(EXPR) \
332 (!HAVE_IN_PLACE_ADDENDS \
333 || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0))
b12dd2e4
CF
334#endif
335
ec68c924 336/* The argument of the -march= flag. The architecture we are assembling. */
316f5878 337static const char *mips_arch_string;
ec68c924
EC
338
339/* The argument of the -mtune= flag. The architecture for which we
340 are optimizing. */
341static int mips_tune = CPU_UNKNOWN;
316f5878 342static const char *mips_tune_string;
ec68c924 343
316f5878 344/* True when generating 32-bit code for a 64-bit processor. */
252b5132
RH
345static int mips_32bitmode = 0;
346
316f5878
RS
347/* True if the given ABI requires 32-bit registers. */
348#define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
349
350/* Likewise 64-bit registers. */
707bfff6
TS
351#define ABI_NEEDS_64BIT_REGS(ABI) \
352 ((ABI) == N32_ABI \
353 || (ABI) == N64_ABI \
316f5878
RS
354 || (ABI) == O64_ABI)
355
7361da2c
AB
356#define ISA_IS_R6(ISA) \
357 ((ISA) == ISA_MIPS32R6 \
358 || (ISA) == ISA_MIPS64R6)
359
ad3fea08 360/* Return true if ISA supports 64 bit wide gp registers. */
707bfff6
TS
361#define ISA_HAS_64BIT_REGS(ISA) \
362 ((ISA) == ISA_MIPS3 \
363 || (ISA) == ISA_MIPS4 \
364 || (ISA) == ISA_MIPS5 \
365 || (ISA) == ISA_MIPS64 \
ae52f483
AB
366 || (ISA) == ISA_MIPS64R2 \
367 || (ISA) == ISA_MIPS64R3 \
7361da2c
AB
368 || (ISA) == ISA_MIPS64R5 \
369 || (ISA) == ISA_MIPS64R6)
9ce8a5dd 370
ad3fea08
TS
371/* Return true if ISA supports 64 bit wide float registers. */
372#define ISA_HAS_64BIT_FPRS(ISA) \
373 ((ISA) == ISA_MIPS3 \
374 || (ISA) == ISA_MIPS4 \
375 || (ISA) == ISA_MIPS5 \
376 || (ISA) == ISA_MIPS32R2 \
ae52f483
AB
377 || (ISA) == ISA_MIPS32R3 \
378 || (ISA) == ISA_MIPS32R5 \
7361da2c 379 || (ISA) == ISA_MIPS32R6 \
ad3fea08 380 || (ISA) == ISA_MIPS64 \
ae52f483
AB
381 || (ISA) == ISA_MIPS64R2 \
382 || (ISA) == ISA_MIPS64R3 \
7361da2c
AB
383 || (ISA) == ISA_MIPS64R5 \
384 || (ISA) == ISA_MIPS64R6)
ad3fea08 385
af7ee8bf
CD
386/* Return true if ISA supports 64-bit right rotate (dror et al.)
387 instructions. */
707bfff6 388#define ISA_HAS_DROR(ISA) \
df58fc94 389 ((ISA) == ISA_MIPS64R2 \
ae52f483
AB
390 || (ISA) == ISA_MIPS64R3 \
391 || (ISA) == ISA_MIPS64R5 \
7361da2c 392 || (ISA) == ISA_MIPS64R6 \
df58fc94
RS
393 || (mips_opts.micromips \
394 && ISA_HAS_64BIT_REGS (ISA)) \
395 )
af7ee8bf
CD
396
397/* Return true if ISA supports 32-bit right rotate (ror et al.)
398 instructions. */
707bfff6
TS
399#define ISA_HAS_ROR(ISA) \
400 ((ISA) == ISA_MIPS32R2 \
ae52f483
AB
401 || (ISA) == ISA_MIPS32R3 \
402 || (ISA) == ISA_MIPS32R5 \
7361da2c 403 || (ISA) == ISA_MIPS32R6 \
707bfff6 404 || (ISA) == ISA_MIPS64R2 \
ae52f483
AB
405 || (ISA) == ISA_MIPS64R3 \
406 || (ISA) == ISA_MIPS64R5 \
7361da2c 407 || (ISA) == ISA_MIPS64R6 \
846ef2d0 408 || (mips_opts.ase & ASE_SMARTMIPS) \
df58fc94
RS
409 || mips_opts.micromips \
410 )
707bfff6 411
7455baf8 412/* Return true if ISA supports single-precision floats in odd registers. */
351cdf24
MF
413#define ISA_HAS_ODD_SINGLE_FPR(ISA, CPU)\
414 (((ISA) == ISA_MIPS32 \
415 || (ISA) == ISA_MIPS32R2 \
416 || (ISA) == ISA_MIPS32R3 \
417 || (ISA) == ISA_MIPS32R5 \
7361da2c 418 || (ISA) == ISA_MIPS32R6 \
351cdf24
MF
419 || (ISA) == ISA_MIPS64 \
420 || (ISA) == ISA_MIPS64R2 \
421 || (ISA) == ISA_MIPS64R3 \
422 || (ISA) == ISA_MIPS64R5 \
7361da2c 423 || (ISA) == ISA_MIPS64R6 \
351cdf24
MF
424 || (CPU) == CPU_R5900) \
425 && (CPU) != CPU_LOONGSON_3A)
af7ee8bf 426
ad3fea08
TS
427/* Return true if ISA supports move to/from high part of a 64-bit
428 floating-point register. */
429#define ISA_HAS_MXHC1(ISA) \
430 ((ISA) == ISA_MIPS32R2 \
ae52f483
AB
431 || (ISA) == ISA_MIPS32R3 \
432 || (ISA) == ISA_MIPS32R5 \
7361da2c
AB
433 || (ISA) == ISA_MIPS32R6 \
434 || (ISA) == ISA_MIPS64R2 \
435 || (ISA) == ISA_MIPS64R3 \
436 || (ISA) == ISA_MIPS64R5 \
437 || (ISA) == ISA_MIPS64R6)
438
439/* Return true if ISA supports legacy NAN. */
440#define ISA_HAS_LEGACY_NAN(ISA) \
441 ((ISA) == ISA_MIPS1 \
442 || (ISA) == ISA_MIPS2 \
443 || (ISA) == ISA_MIPS3 \
444 || (ISA) == ISA_MIPS4 \
445 || (ISA) == ISA_MIPS5 \
446 || (ISA) == ISA_MIPS32 \
447 || (ISA) == ISA_MIPS32R2 \
448 || (ISA) == ISA_MIPS32R3 \
449 || (ISA) == ISA_MIPS32R5 \
450 || (ISA) == ISA_MIPS64 \
ae52f483
AB
451 || (ISA) == ISA_MIPS64R2 \
452 || (ISA) == ISA_MIPS64R3 \
453 || (ISA) == ISA_MIPS64R5)
ad3fea08 454
bad1aba3 455#define GPR_SIZE \
456 (mips_opts.gp == 64 && !ISA_HAS_64BIT_REGS (mips_opts.isa) \
457 ? 32 \
458 : mips_opts.gp)
ca4e0257 459
bad1aba3 460#define FPR_SIZE \
461 (mips_opts.fp == 64 && !ISA_HAS_64BIT_FPRS (mips_opts.isa) \
462 ? 32 \
463 : mips_opts.fp)
ca4e0257 464
316f5878 465#define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
e013f690 466
316f5878 467#define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
e013f690 468
3b91255e
RS
469/* True if relocations are stored in-place. */
470#define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
471
aed1a261
RS
472/* The ABI-derived address size. */
473#define HAVE_64BIT_ADDRESSES \
bad1aba3 474 (GPR_SIZE == 64 && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
aed1a261 475#define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
e013f690 476
aed1a261
RS
477/* The size of symbolic constants (i.e., expressions of the form
478 "SYMBOL" or "SYMBOL + OFFSET"). */
479#define HAVE_32BIT_SYMBOLS \
480 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
481#define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
ca4e0257 482
b7c7d6c1
TS
483/* Addresses are loaded in different ways, depending on the address size
484 in use. The n32 ABI Documentation also mandates the use of additions
485 with overflow checking, but existing implementations don't follow it. */
f899b4b8 486#define ADDRESS_ADD_INSN \
b7c7d6c1 487 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
f899b4b8
TS
488
489#define ADDRESS_ADDI_INSN \
b7c7d6c1 490 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
f899b4b8
TS
491
492#define ADDRESS_LOAD_INSN \
493 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
494
495#define ADDRESS_STORE_INSN \
496 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
497
a4672219 498/* Return true if the given CPU supports the MIPS16 ASE. */
3396de36
TS
499#define CPU_HAS_MIPS16(cpu) \
500 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
501 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
a4672219 502
2309ddf2 503/* Return true if the given CPU supports the microMIPS ASE. */
df58fc94
RS
504#define CPU_HAS_MICROMIPS(cpu) 0
505
60b63b72
RS
506/* True if CPU has a dror instruction. */
507#define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
508
509/* True if CPU has a ror instruction. */
510#define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
511
dd6a37e7 512/* True if CPU is in the Octeon family */
2c629856
N
513#define CPU_IS_OCTEON(CPU) ((CPU) == CPU_OCTEON || (CPU) == CPU_OCTEONP \
514 || (CPU) == CPU_OCTEON2 || (CPU) == CPU_OCTEON3)
dd6a37e7 515
dd3cbb7e 516/* True if CPU has seq/sne and seqi/snei instructions. */
dd6a37e7 517#define CPU_HAS_SEQ(CPU) (CPU_IS_OCTEON (CPU))
dd3cbb7e 518
0aa27725
RS
519/* True, if CPU has support for ldc1 and sdc1. */
520#define CPU_HAS_LDC1_SDC1(CPU) \
521 ((mips_opts.isa != ISA_MIPS1) && ((CPU) != CPU_R5900))
522
c8978940
CD
523/* True if mflo and mfhi can be immediately followed by instructions
524 which write to the HI and LO registers.
525
526 According to MIPS specifications, MIPS ISAs I, II, and III need
527 (at least) two instructions between the reads of HI/LO and
528 instructions which write them, and later ISAs do not. Contradicting
529 the MIPS specifications, some MIPS IV processor user manuals (e.g.
530 the UM for the NEC Vr5000) document needing the instructions between
531 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
532 MIPS64 and later ISAs to have the interlocks, plus any specific
533 earlier-ISA CPUs for which CPU documentation declares that the
534 instructions are really interlocked. */
535#define hilo_interlocks \
536 (mips_opts.isa == ISA_MIPS32 \
537 || mips_opts.isa == ISA_MIPS32R2 \
ae52f483
AB
538 || mips_opts.isa == ISA_MIPS32R3 \
539 || mips_opts.isa == ISA_MIPS32R5 \
7361da2c 540 || mips_opts.isa == ISA_MIPS32R6 \
c8978940
CD
541 || mips_opts.isa == ISA_MIPS64 \
542 || mips_opts.isa == ISA_MIPS64R2 \
ae52f483
AB
543 || mips_opts.isa == ISA_MIPS64R3 \
544 || mips_opts.isa == ISA_MIPS64R5 \
7361da2c 545 || mips_opts.isa == ISA_MIPS64R6 \
c8978940 546 || mips_opts.arch == CPU_R4010 \
e407c74b 547 || mips_opts.arch == CPU_R5900 \
c8978940
CD
548 || mips_opts.arch == CPU_R10000 \
549 || mips_opts.arch == CPU_R12000 \
3aa3176b
TS
550 || mips_opts.arch == CPU_R14000 \
551 || mips_opts.arch == CPU_R16000 \
c8978940 552 || mips_opts.arch == CPU_RM7000 \
c8978940 553 || mips_opts.arch == CPU_VR5500 \
df58fc94 554 || mips_opts.micromips \
c8978940 555 )
252b5132
RH
556
557/* Whether the processor uses hardware interlocks to protect reads
81912461
ILT
558 from the GPRs after they are loaded from memory, and thus does not
559 require nops to be inserted. This applies to instructions marked
67dc82bc 560 INSN_LOAD_MEMORY. These nops are only required at MIPS ISA
df58fc94
RS
561 level I and microMIPS mode instructions are always interlocked. */
562#define gpr_interlocks \
563 (mips_opts.isa != ISA_MIPS1 \
564 || mips_opts.arch == CPU_R3900 \
e407c74b 565 || mips_opts.arch == CPU_R5900 \
df58fc94
RS
566 || mips_opts.micromips \
567 )
252b5132 568
81912461
ILT
569/* Whether the processor uses hardware interlocks to avoid delays
570 required by coprocessor instructions, and thus does not require
571 nops to be inserted. This applies to instructions marked
43885403
MF
572 INSN_LOAD_COPROC, INSN_COPROC_MOVE, and to delays between
573 instructions marked INSN_WRITE_COND_CODE and ones marked
81912461 574 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
df58fc94
RS
575 levels I, II, and III and microMIPS mode instructions are always
576 interlocked. */
bdaaa2e1 577/* Itbl support may require additional care here. */
81912461
ILT
578#define cop_interlocks \
579 ((mips_opts.isa != ISA_MIPS1 \
580 && mips_opts.isa != ISA_MIPS2 \
581 && mips_opts.isa != ISA_MIPS3) \
582 || mips_opts.arch == CPU_R4300 \
df58fc94 583 || mips_opts.micromips \
81912461
ILT
584 )
585
586/* Whether the processor uses hardware interlocks to protect reads
587 from coprocessor registers after they are loaded from memory, and
588 thus does not require nops to be inserted. This applies to
589 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
df58fc94
RS
590 requires at MIPS ISA level I and microMIPS mode instructions are
591 always interlocked. */
592#define cop_mem_interlocks \
593 (mips_opts.isa != ISA_MIPS1 \
594 || mips_opts.micromips \
595 )
252b5132 596
6b76fefe
CM
597/* Is this a mfhi or mflo instruction? */
598#define MF_HILO_INSN(PINFO) \
b19e8a9b
AN
599 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
600
df58fc94
RS
601/* Whether code compression (either of the MIPS16 or the microMIPS ASEs)
602 has been selected. This implies, in particular, that addresses of text
603 labels have their LSB set. */
604#define HAVE_CODE_COMPRESSION \
605 ((mips_opts.mips16 | mips_opts.micromips) != 0)
606
42429eac 607/* The minimum and maximum signed values that can be stored in a GPR. */
bad1aba3 608#define GPR_SMAX ((offsetT) (((valueT) 1 << (GPR_SIZE - 1)) - 1))
42429eac
RS
609#define GPR_SMIN (-GPR_SMAX - 1)
610
252b5132
RH
611/* MIPS PIC level. */
612
a161fe53 613enum mips_pic_level mips_pic;
252b5132 614
c9914766 615/* 1 if we should generate 32 bit offsets from the $gp register in
252b5132 616 SVR4_PIC mode. Currently has no meaning in other modes. */
c9914766 617static int mips_big_got = 0;
252b5132
RH
618
619/* 1 if trap instructions should used for overflow rather than break
620 instructions. */
c9914766 621static int mips_trap = 0;
252b5132 622
119d663a 623/* 1 if double width floating point constants should not be constructed
b6ff326e 624 by assembling two single width halves into two single width floating
119d663a
NC
625 point registers which just happen to alias the double width destination
626 register. On some architectures this aliasing can be disabled by a bit
d547a75e 627 in the status register, and the setting of this bit cannot be determined
119d663a
NC
628 automatically at assemble time. */
629static int mips_disable_float_construction;
630
252b5132
RH
631/* Non-zero if any .set noreorder directives were used. */
632
633static int mips_any_noreorder;
634
6b76fefe
CM
635/* Non-zero if nops should be inserted when the register referenced in
636 an mfhi/mflo instruction is read in the next two instructions. */
637static int mips_7000_hilo_fix;
638
02ffd3e4 639/* The size of objects in the small data section. */
156c2f8b 640static unsigned int g_switch_value = 8;
252b5132
RH
641/* Whether the -G option was used. */
642static int g_switch_seen = 0;
643
644#define N_RMASK 0xc4
645#define N_VFP 0xd4
646
647/* If we can determine in advance that GP optimization won't be
648 possible, we can skip the relaxation stuff that tries to produce
649 GP-relative references. This makes delay slot optimization work
650 better.
651
652 This function can only provide a guess, but it seems to work for
fba2b7f9
GK
653 gcc output. It needs to guess right for gcc, otherwise gcc
654 will put what it thinks is a GP-relative instruction in a branch
655 delay slot.
252b5132
RH
656
657 I don't know if a fix is needed for the SVR4_PIC mode. I've only
658 fixed it for the non-PIC mode. KR 95/04/07 */
17a2f251 659static int nopic_need_relax (symbolS *, int);
252b5132
RH
660
661/* handle of the OPCODE hash table */
662static struct hash_control *op_hash = NULL;
663
664/* The opcode hash table we use for the mips16. */
665static struct hash_control *mips16_op_hash = NULL;
666
df58fc94
RS
667/* The opcode hash table we use for the microMIPS ASE. */
668static struct hash_control *micromips_op_hash = NULL;
669
252b5132
RH
670/* This array holds the chars that always start a comment. If the
671 pre-processor is disabled, these aren't very useful */
672const char comment_chars[] = "#";
673
674/* This array holds the chars that only start a comment at the beginning of
675 a line. If the line seems to have the form '# 123 filename'
676 .line and .file directives will appear in the pre-processed output */
677/* Note that input_file.c hand checks for '#' at the beginning of the
678 first line of the input file. This is because the compiler outputs
bdaaa2e1 679 #NO_APP at the beginning of its output. */
252b5132
RH
680/* Also note that C style comments are always supported. */
681const char line_comment_chars[] = "#";
682
bdaaa2e1 683/* This array holds machine specific line separator characters. */
63a0b638 684const char line_separator_chars[] = ";";
252b5132
RH
685
686/* Chars that can be used to separate mant from exp in floating point nums */
687const char EXP_CHARS[] = "eE";
688
689/* Chars that mean this number is a floating point constant */
690/* As in 0f12.456 */
691/* or 0d1.2345e12 */
692const char FLT_CHARS[] = "rRsSfFdDxXpP";
693
694/* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
695 changed in read.c . Ideally it shouldn't have to know about it at all,
696 but nothing is ideal around here.
697 */
698
e3de51ce
RS
699/* Types of printf format used for instruction-related error messages.
700 "I" means int ("%d") and "S" means string ("%s"). */
701enum mips_insn_error_format {
702 ERR_FMT_PLAIN,
703 ERR_FMT_I,
704 ERR_FMT_SS,
705};
706
707/* Information about an error that was found while assembling the current
708 instruction. */
709struct mips_insn_error {
710 /* We sometimes need to match an instruction against more than one
711 opcode table entry. Errors found during this matching are reported
712 against a particular syntactic argument rather than against the
713 instruction as a whole. We grade these messages so that errors
714 against argument N have a greater priority than an error against
715 any argument < N, since the former implies that arguments up to N
716 were acceptable and that the opcode entry was therefore a closer match.
717 If several matches report an error against the same argument,
718 we only use that error if it is the same in all cases.
719
720 min_argnum is the minimum argument number for which an error message
721 should be accepted. It is 0 if MSG is against the instruction as
722 a whole. */
723 int min_argnum;
724
725 /* The printf()-style message, including its format and arguments. */
726 enum mips_insn_error_format format;
727 const char *msg;
728 union {
729 int i;
730 const char *ss[2];
731 } u;
732};
733
734/* The error that should be reported for the current instruction. */
735static struct mips_insn_error insn_error;
252b5132
RH
736
737static int auto_align = 1;
738
739/* When outputting SVR4 PIC code, the assembler needs to know the
740 offset in the stack frame from which to restore the $gp register.
741 This is set by the .cprestore pseudo-op, and saved in this
742 variable. */
743static offsetT mips_cprestore_offset = -1;
744
67c1ffbe 745/* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
6478892d 746 more optimizations, it can use a register value instead of a memory-saved
956cd1d6 747 offset and even an other register than $gp as global pointer. */
6478892d
TS
748static offsetT mips_cpreturn_offset = -1;
749static int mips_cpreturn_register = -1;
750static int mips_gp_register = GP;
def2e0dd 751static int mips_gprel_offset = 0;
6478892d 752
7a621144
DJ
753/* Whether mips_cprestore_offset has been set in the current function
754 (or whether it has already been warned about, if not). */
755static int mips_cprestore_valid = 0;
756
252b5132
RH
757/* This is the register which holds the stack frame, as set by the
758 .frame pseudo-op. This is needed to implement .cprestore. */
759static int mips_frame_reg = SP;
760
7a621144
DJ
761/* Whether mips_frame_reg has been set in the current function
762 (or whether it has already been warned about, if not). */
763static int mips_frame_reg_valid = 0;
764
252b5132
RH
765/* To output NOP instructions correctly, we need to keep information
766 about the previous two instructions. */
767
768/* Whether we are optimizing. The default value of 2 means to remove
769 unneeded NOPs and swap branch instructions when possible. A value
770 of 1 means to not swap branches. A value of 0 means to always
771 insert NOPs. */
772static int mips_optimize = 2;
773
774/* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
775 equivalent to seeing no -g option at all. */
776static int mips_debug = 0;
777
7d8e00cf
RS
778/* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */
779#define MAX_VR4130_NOPS 4
780
781/* The maximum number of NOPs needed to fill delay slots. */
782#define MAX_DELAY_NOPS 2
783
784/* The maximum number of NOPs needed for any purpose. */
785#define MAX_NOPS 4
71400594
RS
786
787/* A list of previous instructions, with index 0 being the most recent.
788 We need to look back MAX_NOPS instructions when filling delay slots
789 or working around processor errata. We need to look back one
790 instruction further if we're thinking about using history[0] to
791 fill a branch delay slot. */
792static struct mips_cl_insn history[1 + MAX_NOPS];
252b5132 793
fc76e730 794/* Arrays of operands for each instruction. */
14daeee3 795#define MAX_OPERANDS 6
fc76e730
RS
796struct mips_operand_array {
797 const struct mips_operand *operand[MAX_OPERANDS];
798};
799static struct mips_operand_array *mips_operands;
800static struct mips_operand_array *mips16_operands;
801static struct mips_operand_array *micromips_operands;
802
1e915849 803/* Nop instructions used by emit_nop. */
df58fc94
RS
804static struct mips_cl_insn nop_insn;
805static struct mips_cl_insn mips16_nop_insn;
806static struct mips_cl_insn micromips_nop16_insn;
807static struct mips_cl_insn micromips_nop32_insn;
1e915849
RS
808
809/* The appropriate nop for the current mode. */
833794fc
MR
810#define NOP_INSN (mips_opts.mips16 \
811 ? &mips16_nop_insn \
812 : (mips_opts.micromips \
813 ? (mips_opts.insn32 \
814 ? &micromips_nop32_insn \
815 : &micromips_nop16_insn) \
816 : &nop_insn))
df58fc94
RS
817
818/* The size of NOP_INSN in bytes. */
833794fc
MR
819#define NOP_INSN_SIZE ((mips_opts.mips16 \
820 || (mips_opts.micromips && !mips_opts.insn32)) \
821 ? 2 : 4)
252b5132 822
252b5132
RH
823/* If this is set, it points to a frag holding nop instructions which
824 were inserted before the start of a noreorder section. If those
825 nops turn out to be unnecessary, the size of the frag can be
826 decreased. */
827static fragS *prev_nop_frag;
828
829/* The number of nop instructions we created in prev_nop_frag. */
830static int prev_nop_frag_holds;
831
832/* The number of nop instructions that we know we need in
bdaaa2e1 833 prev_nop_frag. */
252b5132
RH
834static int prev_nop_frag_required;
835
836/* The number of instructions we've seen since prev_nop_frag. */
837static int prev_nop_frag_since;
838
e8044f35
RS
839/* Relocations against symbols are sometimes done in two parts, with a HI
840 relocation and a LO relocation. Each relocation has only 16 bits of
841 space to store an addend. This means that in order for the linker to
842 handle carries correctly, it must be able to locate both the HI and
843 the LO relocation. This means that the relocations must appear in
844 order in the relocation table.
252b5132
RH
845
846 In order to implement this, we keep track of each unmatched HI
847 relocation. We then sort them so that they immediately precede the
bdaaa2e1 848 corresponding LO relocation. */
252b5132 849
e972090a
NC
850struct mips_hi_fixup
851{
252b5132
RH
852 /* Next HI fixup. */
853 struct mips_hi_fixup *next;
854 /* This fixup. */
855 fixS *fixp;
856 /* The section this fixup is in. */
857 segT seg;
858};
859
860/* The list of unmatched HI relocs. */
861
862static struct mips_hi_fixup *mips_hi_fixup_list;
863
64bdfcaf
RS
864/* The frag containing the last explicit relocation operator.
865 Null if explicit relocations have not been used. */
866
867static fragS *prev_reloc_op_frag;
868
252b5132
RH
869/* Map mips16 register numbers to normal MIPS register numbers. */
870
e972090a
NC
871static const unsigned int mips16_to_32_reg_map[] =
872{
252b5132
RH
873 16, 17, 2, 3, 4, 5, 6, 7
874};
60b63b72 875
df58fc94
RS
876/* Map microMIPS register numbers to normal MIPS register numbers. */
877
df58fc94 878#define micromips_to_32_reg_d_map mips16_to_32_reg_map
df58fc94
RS
879
880/* The microMIPS registers with type h. */
e76ff5ab 881static const unsigned int micromips_to_32_reg_h_map1[] =
df58fc94
RS
882{
883 5, 5, 6, 4, 4, 4, 4, 4
884};
e76ff5ab 885static const unsigned int micromips_to_32_reg_h_map2[] =
df58fc94
RS
886{
887 6, 7, 7, 21, 22, 5, 6, 7
888};
889
df58fc94
RS
890/* The microMIPS registers with type m. */
891static const unsigned int micromips_to_32_reg_m_map[] =
892{
893 0, 17, 2, 3, 16, 18, 19, 20
894};
895
896#define micromips_to_32_reg_n_map micromips_to_32_reg_m_map
897
71400594
RS
898/* Classifies the kind of instructions we're interested in when
899 implementing -mfix-vr4120. */
c67a084a
NC
900enum fix_vr4120_class
901{
71400594
RS
902 FIX_VR4120_MACC,
903 FIX_VR4120_DMACC,
904 FIX_VR4120_MULT,
905 FIX_VR4120_DMULT,
906 FIX_VR4120_DIV,
907 FIX_VR4120_MTHILO,
908 NUM_FIX_VR4120_CLASSES
909};
910
c67a084a
NC
911/* ...likewise -mfix-loongson2f-jump. */
912static bfd_boolean mips_fix_loongson2f_jump;
913
914/* ...likewise -mfix-loongson2f-nop. */
915static bfd_boolean mips_fix_loongson2f_nop;
916
917/* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */
918static bfd_boolean mips_fix_loongson2f;
919
71400594
RS
920/* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if
921 there must be at least one other instruction between an instruction
922 of type X and an instruction of type Y. */
923static unsigned int vr4120_conflicts[NUM_FIX_VR4120_CLASSES];
924
925/* True if -mfix-vr4120 is in force. */
d766e8ec 926static int mips_fix_vr4120;
4a6a3df4 927
7d8e00cf
RS
928/* ...likewise -mfix-vr4130. */
929static int mips_fix_vr4130;
930
6a32d874
CM
931/* ...likewise -mfix-24k. */
932static int mips_fix_24k;
933
a8d14a88
CM
934/* ...likewise -mfix-rm7000 */
935static int mips_fix_rm7000;
936
d954098f
DD
937/* ...likewise -mfix-cn63xxp1 */
938static bfd_boolean mips_fix_cn63xxp1;
939
4a6a3df4
AO
940/* We don't relax branches by default, since this causes us to expand
941 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
942 fail to compute the offset before expanding the macro to the most
943 efficient expansion. */
944
945static int mips_relax_branch;
252b5132 946\f
4d7206a2
RS
947/* The expansion of many macros depends on the type of symbol that
948 they refer to. For example, when generating position-dependent code,
949 a macro that refers to a symbol may have two different expansions,
950 one which uses GP-relative addresses and one which uses absolute
951 addresses. When generating SVR4-style PIC, a macro may have
952 different expansions for local and global symbols.
953
954 We handle these situations by generating both sequences and putting
955 them in variant frags. In position-dependent code, the first sequence
956 will be the GP-relative one and the second sequence will be the
957 absolute one. In SVR4 PIC, the first sequence will be for global
958 symbols and the second will be for local symbols.
959
584892a6
RS
960 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
961 SECOND are the lengths of the two sequences in bytes. These fields
962 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
963 the subtype has the following flags:
4d7206a2 964
584892a6
RS
965 RELAX_USE_SECOND
966 Set if it has been decided that we should use the second
967 sequence instead of the first.
968
969 RELAX_SECOND_LONGER
970 Set in the first variant frag if the macro's second implementation
971 is longer than its first. This refers to the macro as a whole,
972 not an individual relaxation.
973
974 RELAX_NOMACRO
975 Set in the first variant frag if the macro appeared in a .set nomacro
976 block and if one alternative requires a warning but the other does not.
977
978 RELAX_DELAY_SLOT
979 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
980 delay slot.
4d7206a2 981
df58fc94
RS
982 RELAX_DELAY_SLOT_16BIT
983 Like RELAX_DELAY_SLOT, but indicates that the delay slot requires a
984 16-bit instruction.
985
986 RELAX_DELAY_SLOT_SIZE_FIRST
987 Like RELAX_DELAY_SLOT, but indicates that the first implementation of
988 the macro is of the wrong size for the branch delay slot.
989
990 RELAX_DELAY_SLOT_SIZE_SECOND
991 Like RELAX_DELAY_SLOT, but indicates that the second implementation of
992 the macro is of the wrong size for the branch delay slot.
993
4d7206a2
RS
994 The frag's "opcode" points to the first fixup for relaxable code.
995
996 Relaxable macros are generated using a sequence such as:
997
998 relax_start (SYMBOL);
999 ... generate first expansion ...
1000 relax_switch ();
1001 ... generate second expansion ...
1002 relax_end ();
1003
1004 The code and fixups for the unwanted alternative are discarded
1005 by md_convert_frag. */
584892a6 1006#define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND))
4d7206a2 1007
584892a6
RS
1008#define RELAX_FIRST(X) (((X) >> 8) & 0xff)
1009#define RELAX_SECOND(X) ((X) & 0xff)
1010#define RELAX_USE_SECOND 0x10000
1011#define RELAX_SECOND_LONGER 0x20000
1012#define RELAX_NOMACRO 0x40000
1013#define RELAX_DELAY_SLOT 0x80000
df58fc94
RS
1014#define RELAX_DELAY_SLOT_16BIT 0x100000
1015#define RELAX_DELAY_SLOT_SIZE_FIRST 0x200000
1016#define RELAX_DELAY_SLOT_SIZE_SECOND 0x400000
252b5132 1017
4a6a3df4
AO
1018/* Branch without likely bit. If label is out of range, we turn:
1019
1020 beq reg1, reg2, label
1021 delay slot
1022
1023 into
1024
1025 bne reg1, reg2, 0f
1026 nop
1027 j label
1028 0: delay slot
1029
1030 with the following opcode replacements:
1031
1032 beq <-> bne
1033 blez <-> bgtz
1034 bltz <-> bgez
1035 bc1f <-> bc1t
1036
1037 bltzal <-> bgezal (with jal label instead of j label)
1038
1039 Even though keeping the delay slot instruction in the delay slot of
1040 the branch would be more efficient, it would be very tricky to do
1041 correctly, because we'd have to introduce a variable frag *after*
1042 the delay slot instruction, and expand that instead. Let's do it
1043 the easy way for now, even if the branch-not-taken case now costs
1044 one additional instruction. Out-of-range branches are not supposed
1045 to be common, anyway.
1046
1047 Branch likely. If label is out of range, we turn:
1048
1049 beql reg1, reg2, label
1050 delay slot (annulled if branch not taken)
1051
1052 into
1053
1054 beql reg1, reg2, 1f
1055 nop
1056 beql $0, $0, 2f
1057 nop
1058 1: j[al] label
1059 delay slot (executed only if branch taken)
1060 2:
1061
1062 It would be possible to generate a shorter sequence by losing the
1063 likely bit, generating something like:
b34976b6 1064
4a6a3df4
AO
1065 bne reg1, reg2, 0f
1066 nop
1067 j[al] label
1068 delay slot (executed only if branch taken)
1069 0:
1070
1071 beql -> bne
1072 bnel -> beq
1073 blezl -> bgtz
1074 bgtzl -> blez
1075 bltzl -> bgez
1076 bgezl -> bltz
1077 bc1fl -> bc1t
1078 bc1tl -> bc1f
1079
1080 bltzall -> bgezal (with jal label instead of j label)
1081 bgezall -> bltzal (ditto)
1082
1083
1084 but it's not clear that it would actually improve performance. */
66b3e8da
MR
1085#define RELAX_BRANCH_ENCODE(at, uncond, likely, link, toofar) \
1086 ((relax_substateT) \
1087 (0xc0000000 \
1088 | ((at) & 0x1f) \
1089 | ((toofar) ? 0x20 : 0) \
1090 | ((link) ? 0x40 : 0) \
1091 | ((likely) ? 0x80 : 0) \
1092 | ((uncond) ? 0x100 : 0)))
4a6a3df4 1093#define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
66b3e8da
MR
1094#define RELAX_BRANCH_UNCOND(i) (((i) & 0x100) != 0)
1095#define RELAX_BRANCH_LIKELY(i) (((i) & 0x80) != 0)
1096#define RELAX_BRANCH_LINK(i) (((i) & 0x40) != 0)
1097#define RELAX_BRANCH_TOOFAR(i) (((i) & 0x20) != 0)
1098#define RELAX_BRANCH_AT(i) ((i) & 0x1f)
4a6a3df4 1099
252b5132
RH
1100/* For mips16 code, we use an entirely different form of relaxation.
1101 mips16 supports two versions of most instructions which take
1102 immediate values: a small one which takes some small value, and a
1103 larger one which takes a 16 bit value. Since branches also follow
1104 this pattern, relaxing these values is required.
1105
1106 We can assemble both mips16 and normal MIPS code in a single
1107 object. Therefore, we need to support this type of relaxation at
1108 the same time that we support the relaxation described above. We
1109 use the high bit of the subtype field to distinguish these cases.
1110
1111 The information we store for this type of relaxation is the
1112 argument code found in the opcode file for this relocation, whether
1113 the user explicitly requested a small or extended form, and whether
1114 the relocation is in a jump or jal delay slot. That tells us the
1115 size of the value, and how it should be stored. We also store
1116 whether the fragment is considered to be extended or not. We also
1117 store whether this is known to be a branch to a different section,
1118 whether we have tried to relax this frag yet, and whether we have
1119 ever extended a PC relative fragment because of a shift count. */
1120#define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
1121 (0x80000000 \
1122 | ((type) & 0xff) \
1123 | ((small) ? 0x100 : 0) \
1124 | ((ext) ? 0x200 : 0) \
1125 | ((dslot) ? 0x400 : 0) \
1126 | ((jal_dslot) ? 0x800 : 0))
4a6a3df4 1127#define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
252b5132
RH
1128#define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
1129#define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
1130#define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
1131#define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
1132#define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
1133#define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
1134#define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
1135#define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
1136#define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
1137#define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
1138#define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
885add95 1139
df58fc94
RS
1140/* For microMIPS code, we use relaxation similar to one we use for
1141 MIPS16 code. Some instructions that take immediate values support
1142 two encodings: a small one which takes some small value, and a
1143 larger one which takes a 16 bit value. As some branches also follow
1144 this pattern, relaxing these values is required.
1145
1146 We can assemble both microMIPS and normal MIPS code in a single
1147 object. Therefore, we need to support this type of relaxation at
1148 the same time that we support the relaxation described above. We
1149 use one of the high bits of the subtype field to distinguish these
1150 cases.
1151
1152 The information we store for this type of relaxation is the argument
1153 code found in the opcode file for this relocation, the register
40209cad
MR
1154 selected as the assembler temporary, whether the branch is
1155 unconditional, whether it is compact, whether it stores the link
1156 address implicitly in $ra, whether relaxation of out-of-range 32-bit
1157 branches to a sequence of instructions is enabled, and whether the
1158 displacement of a branch is too large to fit as an immediate argument
1159 of a 16-bit and a 32-bit branch, respectively. */
1160#define RELAX_MICROMIPS_ENCODE(type, at, uncond, compact, link, \
1161 relax32, toofar16, toofar32) \
1162 (0x40000000 \
1163 | ((type) & 0xff) \
1164 | (((at) & 0x1f) << 8) \
1165 | ((uncond) ? 0x2000 : 0) \
1166 | ((compact) ? 0x4000 : 0) \
1167 | ((link) ? 0x8000 : 0) \
1168 | ((relax32) ? 0x10000 : 0) \
1169 | ((toofar16) ? 0x20000 : 0) \
1170 | ((toofar32) ? 0x40000 : 0))
df58fc94
RS
1171#define RELAX_MICROMIPS_P(i) (((i) & 0xc0000000) == 0x40000000)
1172#define RELAX_MICROMIPS_TYPE(i) ((i) & 0xff)
1173#define RELAX_MICROMIPS_AT(i) (((i) >> 8) & 0x1f)
40209cad
MR
1174#define RELAX_MICROMIPS_UNCOND(i) (((i) & 0x2000) != 0)
1175#define RELAX_MICROMIPS_COMPACT(i) (((i) & 0x4000) != 0)
1176#define RELAX_MICROMIPS_LINK(i) (((i) & 0x8000) != 0)
1177#define RELAX_MICROMIPS_RELAX32(i) (((i) & 0x10000) != 0)
1178
1179#define RELAX_MICROMIPS_TOOFAR16(i) (((i) & 0x20000) != 0)
1180#define RELAX_MICROMIPS_MARK_TOOFAR16(i) ((i) | 0x20000)
1181#define RELAX_MICROMIPS_CLEAR_TOOFAR16(i) ((i) & ~0x20000)
1182#define RELAX_MICROMIPS_TOOFAR32(i) (((i) & 0x40000) != 0)
1183#define RELAX_MICROMIPS_MARK_TOOFAR32(i) ((i) | 0x40000)
1184#define RELAX_MICROMIPS_CLEAR_TOOFAR32(i) ((i) & ~0x40000)
df58fc94 1185
43c0598f
RS
1186/* Sign-extend 16-bit value X. */
1187#define SEXT_16BIT(X) ((((X) + 0x8000) & 0xffff) - 0x8000)
1188
885add95
CD
1189/* Is the given value a sign-extended 32-bit value? */
1190#define IS_SEXT_32BIT_NUM(x) \
1191 (((x) &~ (offsetT) 0x7fffffff) == 0 \
1192 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
1193
1194/* Is the given value a sign-extended 16-bit value? */
1195#define IS_SEXT_16BIT_NUM(x) \
1196 (((x) &~ (offsetT) 0x7fff) == 0 \
1197 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
1198
df58fc94
RS
1199/* Is the given value a sign-extended 12-bit value? */
1200#define IS_SEXT_12BIT_NUM(x) \
1201 (((((x) & 0xfff) ^ 0x800LL) - 0x800LL) == (x))
1202
7f3c4072
CM
1203/* Is the given value a sign-extended 9-bit value? */
1204#define IS_SEXT_9BIT_NUM(x) \
1205 (((((x) & 0x1ff) ^ 0x100LL) - 0x100LL) == (x))
1206
2051e8c4
MR
1207/* Is the given value a zero-extended 32-bit value? Or a negated one? */
1208#define IS_ZEXT_32BIT_NUM(x) \
1209 (((x) &~ (offsetT) 0xffffffff) == 0 \
1210 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
1211
bf12938e
RS
1212/* Extract bits MASK << SHIFT from STRUCT and shift them right
1213 SHIFT places. */
1214#define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
1215 (((STRUCT) >> (SHIFT)) & (MASK))
1216
bf12938e 1217/* Extract the operand given by FIELD from mips_cl_insn INSN. */
df58fc94
RS
1218#define EXTRACT_OPERAND(MICROMIPS, FIELD, INSN) \
1219 (!(MICROMIPS) \
1220 ? EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) \
1221 : EXTRACT_BITS ((INSN).insn_opcode, \
1222 MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD))
bf12938e
RS
1223#define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \
1224 EXTRACT_BITS ((INSN).insn_opcode, \
1225 MIPS16OP_MASK_##FIELD, \
1226 MIPS16OP_SH_##FIELD)
5c04167a
RS
1227
1228/* The MIPS16 EXTEND opcode, shifted left 16 places. */
1229#define MIPS16_EXTEND (0xf000U << 16)
4d7206a2 1230\f
df58fc94
RS
1231/* Whether or not we are emitting a branch-likely macro. */
1232static bfd_boolean emit_branch_likely_macro = FALSE;
1233
4d7206a2
RS
1234/* Global variables used when generating relaxable macros. See the
1235 comment above RELAX_ENCODE for more details about how relaxation
1236 is used. */
1237static struct {
1238 /* 0 if we're not emitting a relaxable macro.
1239 1 if we're emitting the first of the two relaxation alternatives.
1240 2 if we're emitting the second alternative. */
1241 int sequence;
1242
1243 /* The first relaxable fixup in the current frag. (In other words,
1244 the first fixup that refers to relaxable code.) */
1245 fixS *first_fixup;
1246
1247 /* sizes[0] says how many bytes of the first alternative are stored in
1248 the current frag. Likewise sizes[1] for the second alternative. */
1249 unsigned int sizes[2];
1250
1251 /* The symbol on which the choice of sequence depends. */
1252 symbolS *symbol;
1253} mips_relax;
252b5132 1254\f
584892a6
RS
1255/* Global variables used to decide whether a macro needs a warning. */
1256static struct {
1257 /* True if the macro is in a branch delay slot. */
1258 bfd_boolean delay_slot_p;
1259
df58fc94
RS
1260 /* Set to the length in bytes required if the macro is in a delay slot
1261 that requires a specific length of instruction, otherwise zero. */
1262 unsigned int delay_slot_length;
1263
584892a6
RS
1264 /* For relaxable macros, sizes[0] is the length of the first alternative
1265 in bytes and sizes[1] is the length of the second alternative.
1266 For non-relaxable macros, both elements give the length of the
1267 macro in bytes. */
1268 unsigned int sizes[2];
1269
df58fc94
RS
1270 /* For relaxable macros, first_insn_sizes[0] is the length of the first
1271 instruction of the first alternative in bytes and first_insn_sizes[1]
1272 is the length of the first instruction of the second alternative.
1273 For non-relaxable macros, both elements give the length of the first
1274 instruction in bytes.
1275
1276 Set to zero if we haven't yet seen the first instruction. */
1277 unsigned int first_insn_sizes[2];
1278
1279 /* For relaxable macros, insns[0] is the number of instructions for the
1280 first alternative and insns[1] is the number of instructions for the
1281 second alternative.
1282
1283 For non-relaxable macros, both elements give the number of
1284 instructions for the macro. */
1285 unsigned int insns[2];
1286
584892a6
RS
1287 /* The first variant frag for this macro. */
1288 fragS *first_frag;
1289} mips_macro_warning;
1290\f
252b5132
RH
1291/* Prototypes for static functions. */
1292
252b5132
RH
1293enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG };
1294
b34976b6 1295static void append_insn
df58fc94
RS
1296 (struct mips_cl_insn *, expressionS *, bfd_reloc_code_real_type *,
1297 bfd_boolean expansionp);
7d10b47d 1298static void mips_no_prev_insn (void);
c67a084a 1299static void macro_build (expressionS *, const char *, const char *, ...);
b34976b6 1300static void mips16_macro_build
03ea81db 1301 (expressionS *, const char *, const char *, va_list *);
67c0d1eb 1302static void load_register (int, expressionS *, int);
584892a6
RS
1303static void macro_start (void);
1304static void macro_end (void);
833794fc 1305static void macro (struct mips_cl_insn *ip, char *str);
17a2f251 1306static void mips16_macro (struct mips_cl_insn * ip);
17a2f251
TS
1307static void mips_ip (char *str, struct mips_cl_insn * ip);
1308static void mips16_ip (char *str, struct mips_cl_insn * ip);
b34976b6 1309static void mips16_immed
43c0598f
RS
1310 (char *, unsigned int, int, bfd_reloc_code_real_type, offsetT,
1311 unsigned int, unsigned long *);
5e0116d5 1312static size_t my_getSmallExpression
17a2f251
TS
1313 (expressionS *, bfd_reloc_code_real_type *, char *);
1314static void my_getExpression (expressionS *, char *);
1315static void s_align (int);
1316static void s_change_sec (int);
1317static void s_change_section (int);
1318static void s_cons (int);
1319static void s_float_cons (int);
1320static void s_mips_globl (int);
1321static void s_option (int);
1322static void s_mipsset (int);
1323static void s_abicalls (int);
1324static void s_cpload (int);
1325static void s_cpsetup (int);
1326static void s_cplocal (int);
1327static void s_cprestore (int);
1328static void s_cpreturn (int);
741d6ea8
JM
1329static void s_dtprelword (int);
1330static void s_dtpreldword (int);
d0f13682
CLT
1331static void s_tprelword (int);
1332static void s_tpreldword (int);
17a2f251
TS
1333static void s_gpvalue (int);
1334static void s_gpword (int);
1335static void s_gpdword (int);
a3f278e2 1336static void s_ehword (int);
17a2f251
TS
1337static void s_cpadd (int);
1338static void s_insn (int);
ba92f887 1339static void s_nan (int);
919731af 1340static void s_module (int);
17a2f251
TS
1341static void s_mips_ent (int);
1342static void s_mips_end (int);
1343static void s_mips_frame (int);
1344static void s_mips_mask (int reg_type);
1345static void s_mips_stab (int);
1346static void s_mips_weakext (int);
1347static void s_mips_file (int);
1348static void s_mips_loc (int);
1349static bfd_boolean pic_need_relax (symbolS *, asection *);
4a6a3df4 1350static int relaxed_branch_length (fragS *, asection *, int);
df58fc94
RS
1351static int relaxed_micromips_16bit_branch_length (fragS *, asection *, int);
1352static int relaxed_micromips_32bit_branch_length (fragS *, asection *, int);
919731af 1353static void file_mips_check_options (void);
e7af610e
NC
1354
1355/* Table and functions used to map between CPU/ISA names, and
1356 ISA levels, and CPU numbers. */
1357
e972090a
NC
1358struct mips_cpu_info
1359{
e7af610e 1360 const char *name; /* CPU or ISA name. */
d16afab6
RS
1361 int flags; /* MIPS_CPU_* flags. */
1362 int ase; /* Set of ASEs implemented by the CPU. */
e7af610e
NC
1363 int isa; /* ISA level. */
1364 int cpu; /* CPU number (default CPU if ISA). */
1365};
1366
ad3fea08 1367#define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */
ad3fea08 1368
17a2f251
TS
1369static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *);
1370static const struct mips_cpu_info *mips_cpu_info_from_isa (int);
1371static const struct mips_cpu_info *mips_cpu_info_from_arch (int);
252b5132 1372\f
c31f3936
RS
1373/* Command-line options. */
1374const char *md_shortopts = "O::g::G:";
1375
1376enum options
1377 {
1378 OPTION_MARCH = OPTION_MD_BASE,
1379 OPTION_MTUNE,
1380 OPTION_MIPS1,
1381 OPTION_MIPS2,
1382 OPTION_MIPS3,
1383 OPTION_MIPS4,
1384 OPTION_MIPS5,
1385 OPTION_MIPS32,
1386 OPTION_MIPS64,
1387 OPTION_MIPS32R2,
ae52f483
AB
1388 OPTION_MIPS32R3,
1389 OPTION_MIPS32R5,
7361da2c 1390 OPTION_MIPS32R6,
c31f3936 1391 OPTION_MIPS64R2,
ae52f483
AB
1392 OPTION_MIPS64R3,
1393 OPTION_MIPS64R5,
7361da2c 1394 OPTION_MIPS64R6,
c31f3936
RS
1395 OPTION_MIPS16,
1396 OPTION_NO_MIPS16,
1397 OPTION_MIPS3D,
1398 OPTION_NO_MIPS3D,
1399 OPTION_MDMX,
1400 OPTION_NO_MDMX,
1401 OPTION_DSP,
1402 OPTION_NO_DSP,
1403 OPTION_MT,
1404 OPTION_NO_MT,
1405 OPTION_VIRT,
1406 OPTION_NO_VIRT,
56d438b1
CF
1407 OPTION_MSA,
1408 OPTION_NO_MSA,
c31f3936
RS
1409 OPTION_SMARTMIPS,
1410 OPTION_NO_SMARTMIPS,
1411 OPTION_DSPR2,
1412 OPTION_NO_DSPR2,
1413 OPTION_EVA,
1414 OPTION_NO_EVA,
7d64c587
AB
1415 OPTION_XPA,
1416 OPTION_NO_XPA,
c31f3936
RS
1417 OPTION_MICROMIPS,
1418 OPTION_NO_MICROMIPS,
1419 OPTION_MCU,
1420 OPTION_NO_MCU,
1421 OPTION_COMPAT_ARCH_BASE,
1422 OPTION_M4650,
1423 OPTION_NO_M4650,
1424 OPTION_M4010,
1425 OPTION_NO_M4010,
1426 OPTION_M4100,
1427 OPTION_NO_M4100,
1428 OPTION_M3900,
1429 OPTION_NO_M3900,
1430 OPTION_M7000_HILO_FIX,
1431 OPTION_MNO_7000_HILO_FIX,
1432 OPTION_FIX_24K,
1433 OPTION_NO_FIX_24K,
a8d14a88
CM
1434 OPTION_FIX_RM7000,
1435 OPTION_NO_FIX_RM7000,
c31f3936
RS
1436 OPTION_FIX_LOONGSON2F_JUMP,
1437 OPTION_NO_FIX_LOONGSON2F_JUMP,
1438 OPTION_FIX_LOONGSON2F_NOP,
1439 OPTION_NO_FIX_LOONGSON2F_NOP,
1440 OPTION_FIX_VR4120,
1441 OPTION_NO_FIX_VR4120,
1442 OPTION_FIX_VR4130,
1443 OPTION_NO_FIX_VR4130,
1444 OPTION_FIX_CN63XXP1,
1445 OPTION_NO_FIX_CN63XXP1,
1446 OPTION_TRAP,
1447 OPTION_BREAK,
1448 OPTION_EB,
1449 OPTION_EL,
1450 OPTION_FP32,
1451 OPTION_GP32,
1452 OPTION_CONSTRUCT_FLOATS,
1453 OPTION_NO_CONSTRUCT_FLOATS,
1454 OPTION_FP64,
351cdf24 1455 OPTION_FPXX,
c31f3936
RS
1456 OPTION_GP64,
1457 OPTION_RELAX_BRANCH,
1458 OPTION_NO_RELAX_BRANCH,
833794fc
MR
1459 OPTION_INSN32,
1460 OPTION_NO_INSN32,
c31f3936
RS
1461 OPTION_MSHARED,
1462 OPTION_MNO_SHARED,
1463 OPTION_MSYM32,
1464 OPTION_MNO_SYM32,
1465 OPTION_SOFT_FLOAT,
1466 OPTION_HARD_FLOAT,
1467 OPTION_SINGLE_FLOAT,
1468 OPTION_DOUBLE_FLOAT,
1469 OPTION_32,
c31f3936
RS
1470 OPTION_CALL_SHARED,
1471 OPTION_CALL_NONPIC,
1472 OPTION_NON_SHARED,
1473 OPTION_XGOT,
1474 OPTION_MABI,
1475 OPTION_N32,
1476 OPTION_64,
1477 OPTION_MDEBUG,
1478 OPTION_NO_MDEBUG,
1479 OPTION_PDR,
1480 OPTION_NO_PDR,
1481 OPTION_MVXWORKS_PIC,
ba92f887 1482 OPTION_NAN,
351cdf24
MF
1483 OPTION_ODD_SPREG,
1484 OPTION_NO_ODD_SPREG,
c31f3936
RS
1485 OPTION_END_OF_ENUM
1486 };
1487
1488struct option md_longopts[] =
1489{
1490 /* Options which specify architecture. */
1491 {"march", required_argument, NULL, OPTION_MARCH},
1492 {"mtune", required_argument, NULL, OPTION_MTUNE},
1493 {"mips0", no_argument, NULL, OPTION_MIPS1},
1494 {"mips1", no_argument, NULL, OPTION_MIPS1},
1495 {"mips2", no_argument, NULL, OPTION_MIPS2},
1496 {"mips3", no_argument, NULL, OPTION_MIPS3},
1497 {"mips4", no_argument, NULL, OPTION_MIPS4},
1498 {"mips5", no_argument, NULL, OPTION_MIPS5},
1499 {"mips32", no_argument, NULL, OPTION_MIPS32},
1500 {"mips64", no_argument, NULL, OPTION_MIPS64},
1501 {"mips32r2", no_argument, NULL, OPTION_MIPS32R2},
ae52f483
AB
1502 {"mips32r3", no_argument, NULL, OPTION_MIPS32R3},
1503 {"mips32r5", no_argument, NULL, OPTION_MIPS32R5},
7361da2c 1504 {"mips32r6", no_argument, NULL, OPTION_MIPS32R6},
c31f3936 1505 {"mips64r2", no_argument, NULL, OPTION_MIPS64R2},
ae52f483
AB
1506 {"mips64r3", no_argument, NULL, OPTION_MIPS64R3},
1507 {"mips64r5", no_argument, NULL, OPTION_MIPS64R5},
7361da2c 1508 {"mips64r6", no_argument, NULL, OPTION_MIPS64R6},
c31f3936
RS
1509
1510 /* Options which specify Application Specific Extensions (ASEs). */
1511 {"mips16", no_argument, NULL, OPTION_MIPS16},
1512 {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16},
1513 {"mips3d", no_argument, NULL, OPTION_MIPS3D},
1514 {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D},
1515 {"mdmx", no_argument, NULL, OPTION_MDMX},
1516 {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX},
1517 {"mdsp", no_argument, NULL, OPTION_DSP},
1518 {"mno-dsp", no_argument, NULL, OPTION_NO_DSP},
1519 {"mmt", no_argument, NULL, OPTION_MT},
1520 {"mno-mt", no_argument, NULL, OPTION_NO_MT},
1521 {"msmartmips", no_argument, NULL, OPTION_SMARTMIPS},
1522 {"mno-smartmips", no_argument, NULL, OPTION_NO_SMARTMIPS},
1523 {"mdspr2", no_argument, NULL, OPTION_DSPR2},
1524 {"mno-dspr2", no_argument, NULL, OPTION_NO_DSPR2},
1525 {"meva", no_argument, NULL, OPTION_EVA},
1526 {"mno-eva", no_argument, NULL, OPTION_NO_EVA},
1527 {"mmicromips", no_argument, NULL, OPTION_MICROMIPS},
1528 {"mno-micromips", no_argument, NULL, OPTION_NO_MICROMIPS},
1529 {"mmcu", no_argument, NULL, OPTION_MCU},
1530 {"mno-mcu", no_argument, NULL, OPTION_NO_MCU},
1531 {"mvirt", no_argument, NULL, OPTION_VIRT},
1532 {"mno-virt", no_argument, NULL, OPTION_NO_VIRT},
56d438b1
CF
1533 {"mmsa", no_argument, NULL, OPTION_MSA},
1534 {"mno-msa", no_argument, NULL, OPTION_NO_MSA},
7d64c587
AB
1535 {"mxpa", no_argument, NULL, OPTION_XPA},
1536 {"mno-xpa", no_argument, NULL, OPTION_NO_XPA},
c31f3936
RS
1537
1538 /* Old-style architecture options. Don't add more of these. */
1539 {"m4650", no_argument, NULL, OPTION_M4650},
1540 {"no-m4650", no_argument, NULL, OPTION_NO_M4650},
1541 {"m4010", no_argument, NULL, OPTION_M4010},
1542 {"no-m4010", no_argument, NULL, OPTION_NO_M4010},
1543 {"m4100", no_argument, NULL, OPTION_M4100},
1544 {"no-m4100", no_argument, NULL, OPTION_NO_M4100},
1545 {"m3900", no_argument, NULL, OPTION_M3900},
1546 {"no-m3900", no_argument, NULL, OPTION_NO_M3900},
1547
1548 /* Options which enable bug fixes. */
1549 {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX},
1550 {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
1551 {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
1552 {"mfix-loongson2f-jump", no_argument, NULL, OPTION_FIX_LOONGSON2F_JUMP},
1553 {"mno-fix-loongson2f-jump", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_JUMP},
1554 {"mfix-loongson2f-nop", no_argument, NULL, OPTION_FIX_LOONGSON2F_NOP},
1555 {"mno-fix-loongson2f-nop", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_NOP},
1556 {"mfix-vr4120", no_argument, NULL, OPTION_FIX_VR4120},
1557 {"mno-fix-vr4120", no_argument, NULL, OPTION_NO_FIX_VR4120},
1558 {"mfix-vr4130", no_argument, NULL, OPTION_FIX_VR4130},
1559 {"mno-fix-vr4130", no_argument, NULL, OPTION_NO_FIX_VR4130},
1560 {"mfix-24k", no_argument, NULL, OPTION_FIX_24K},
1561 {"mno-fix-24k", no_argument, NULL, OPTION_NO_FIX_24K},
a8d14a88
CM
1562 {"mfix-rm7000", no_argument, NULL, OPTION_FIX_RM7000},
1563 {"mno-fix-rm7000", no_argument, NULL, OPTION_NO_FIX_RM7000},
c31f3936
RS
1564 {"mfix-cn63xxp1", no_argument, NULL, OPTION_FIX_CN63XXP1},
1565 {"mno-fix-cn63xxp1", no_argument, NULL, OPTION_NO_FIX_CN63XXP1},
1566
1567 /* Miscellaneous options. */
1568 {"trap", no_argument, NULL, OPTION_TRAP},
1569 {"no-break", no_argument, NULL, OPTION_TRAP},
1570 {"break", no_argument, NULL, OPTION_BREAK},
1571 {"no-trap", no_argument, NULL, OPTION_BREAK},
1572 {"EB", no_argument, NULL, OPTION_EB},
1573 {"EL", no_argument, NULL, OPTION_EL},
1574 {"mfp32", no_argument, NULL, OPTION_FP32},
1575 {"mgp32", no_argument, NULL, OPTION_GP32},
1576 {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS},
1577 {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS},
1578 {"mfp64", no_argument, NULL, OPTION_FP64},
351cdf24 1579 {"mfpxx", no_argument, NULL, OPTION_FPXX},
c31f3936
RS
1580 {"mgp64", no_argument, NULL, OPTION_GP64},
1581 {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH},
1582 {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH},
833794fc
MR
1583 {"minsn32", no_argument, NULL, OPTION_INSN32},
1584 {"mno-insn32", no_argument, NULL, OPTION_NO_INSN32},
c31f3936
RS
1585 {"mshared", no_argument, NULL, OPTION_MSHARED},
1586 {"mno-shared", no_argument, NULL, OPTION_MNO_SHARED},
1587 {"msym32", no_argument, NULL, OPTION_MSYM32},
1588 {"mno-sym32", no_argument, NULL, OPTION_MNO_SYM32},
1589 {"msoft-float", no_argument, NULL, OPTION_SOFT_FLOAT},
1590 {"mhard-float", no_argument, NULL, OPTION_HARD_FLOAT},
1591 {"msingle-float", no_argument, NULL, OPTION_SINGLE_FLOAT},
1592 {"mdouble-float", no_argument, NULL, OPTION_DOUBLE_FLOAT},
351cdf24
MF
1593 {"modd-spreg", no_argument, NULL, OPTION_ODD_SPREG},
1594 {"mno-odd-spreg", no_argument, NULL, OPTION_NO_ODD_SPREG},
c31f3936
RS
1595
1596 /* Strictly speaking this next option is ELF specific,
1597 but we allow it for other ports as well in order to
1598 make testing easier. */
1599 {"32", no_argument, NULL, OPTION_32},
1600
1601 /* ELF-specific options. */
c31f3936
RS
1602 {"KPIC", no_argument, NULL, OPTION_CALL_SHARED},
1603 {"call_shared", no_argument, NULL, OPTION_CALL_SHARED},
1604 {"call_nonpic", no_argument, NULL, OPTION_CALL_NONPIC},
1605 {"non_shared", no_argument, NULL, OPTION_NON_SHARED},
1606 {"xgot", no_argument, NULL, OPTION_XGOT},
1607 {"mabi", required_argument, NULL, OPTION_MABI},
1608 {"n32", no_argument, NULL, OPTION_N32},
1609 {"64", no_argument, NULL, OPTION_64},
1610 {"mdebug", no_argument, NULL, OPTION_MDEBUG},
1611 {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG},
1612 {"mpdr", no_argument, NULL, OPTION_PDR},
1613 {"mno-pdr", no_argument, NULL, OPTION_NO_PDR},
1614 {"mvxworks-pic", no_argument, NULL, OPTION_MVXWORKS_PIC},
ba92f887 1615 {"mnan", required_argument, NULL, OPTION_NAN},
c31f3936
RS
1616
1617 {NULL, no_argument, NULL, 0}
1618};
1619size_t md_longopts_size = sizeof (md_longopts);
1620\f
c6278170
RS
1621/* Information about either an Application Specific Extension or an
1622 optional architecture feature that, for simplicity, we treat in the
1623 same way as an ASE. */
1624struct mips_ase
1625{
1626 /* The name of the ASE, used in both the command-line and .set options. */
1627 const char *name;
1628
1629 /* The associated ASE_* flags. If the ASE is available on both 32-bit
1630 and 64-bit architectures, the flags here refer to the subset that
1631 is available on both. */
1632 unsigned int flags;
1633
1634 /* The ASE_* flag used for instructions that are available on 64-bit
1635 architectures but that are not included in FLAGS. */
1636 unsigned int flags64;
1637
1638 /* The command-line options that turn the ASE on and off. */
1639 int option_on;
1640 int option_off;
1641
1642 /* The minimum required architecture revisions for MIPS32, MIPS64,
1643 microMIPS32 and microMIPS64, or -1 if the extension isn't supported. */
1644 int mips32_rev;
1645 int mips64_rev;
1646 int micromips32_rev;
1647 int micromips64_rev;
7361da2c
AB
1648
1649 /* The architecture where the ASE was removed or -1 if the extension has not
1650 been removed. */
1651 int rem_rev;
c6278170
RS
1652};
1653
1654/* A table of all supported ASEs. */
1655static const struct mips_ase mips_ases[] = {
1656 { "dsp", ASE_DSP, ASE_DSP64,
1657 OPTION_DSP, OPTION_NO_DSP,
7361da2c
AB
1658 2, 2, 2, 2,
1659 -1 },
c6278170
RS
1660
1661 { "dspr2", ASE_DSP | ASE_DSPR2, 0,
1662 OPTION_DSPR2, OPTION_NO_DSPR2,
7361da2c
AB
1663 2, 2, 2, 2,
1664 -1 },
c6278170
RS
1665
1666 { "eva", ASE_EVA, 0,
1667 OPTION_EVA, OPTION_NO_EVA,
7361da2c
AB
1668 2, 2, 2, 2,
1669 -1 },
c6278170
RS
1670
1671 { "mcu", ASE_MCU, 0,
1672 OPTION_MCU, OPTION_NO_MCU,
7361da2c
AB
1673 2, 2, 2, 2,
1674 -1 },
c6278170
RS
1675
1676 /* Deprecated in MIPS64r5, but we don't implement that yet. */
1677 { "mdmx", ASE_MDMX, 0,
1678 OPTION_MDMX, OPTION_NO_MDMX,
7361da2c
AB
1679 -1, 1, -1, -1,
1680 6 },
c6278170
RS
1681
1682 /* Requires 64-bit FPRs, so the minimum MIPS32 revision is 2. */
1683 { "mips3d", ASE_MIPS3D, 0,
1684 OPTION_MIPS3D, OPTION_NO_MIPS3D,
7361da2c
AB
1685 2, 1, -1, -1,
1686 6 },
c6278170
RS
1687
1688 { "mt", ASE_MT, 0,
1689 OPTION_MT, OPTION_NO_MT,
7361da2c
AB
1690 2, 2, -1, -1,
1691 -1 },
c6278170
RS
1692
1693 { "smartmips", ASE_SMARTMIPS, 0,
1694 OPTION_SMARTMIPS, OPTION_NO_SMARTMIPS,
7361da2c
AB
1695 1, -1, -1, -1,
1696 6 },
c6278170
RS
1697
1698 { "virt", ASE_VIRT, ASE_VIRT64,
1699 OPTION_VIRT, OPTION_NO_VIRT,
7361da2c
AB
1700 2, 2, 2, 2,
1701 -1 },
56d438b1
CF
1702
1703 { "msa", ASE_MSA, ASE_MSA64,
1704 OPTION_MSA, OPTION_NO_MSA,
7361da2c
AB
1705 2, 2, 2, 2,
1706 -1 },
7d64c587
AB
1707
1708 { "xpa", ASE_XPA, 0,
1709 OPTION_XPA, OPTION_NO_XPA,
7361da2c
AB
1710 2, 2, -1, -1,
1711 -1 },
c6278170
RS
1712};
1713
1714/* The set of ASEs that require -mfp64. */
82bda27b 1715#define FP64_ASES (ASE_MIPS3D | ASE_MDMX | ASE_MSA)
c6278170
RS
1716
1717/* Groups of ASE_* flags that represent different revisions of an ASE. */
1718static const unsigned int mips_ase_groups[] = {
1719 ASE_DSP | ASE_DSPR2
1720};
1721\f
252b5132
RH
1722/* Pseudo-op table.
1723
1724 The following pseudo-ops from the Kane and Heinrich MIPS book
1725 should be defined here, but are currently unsupported: .alias,
1726 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
1727
1728 The following pseudo-ops from the Kane and Heinrich MIPS book are
1729 specific to the type of debugging information being generated, and
1730 should be defined by the object format: .aent, .begin, .bend,
1731 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
1732 .vreg.
1733
1734 The following pseudo-ops from the Kane and Heinrich MIPS book are
1735 not MIPS CPU specific, but are also not specific to the object file
1736 format. This file is probably the best place to define them, but
d84bcf09 1737 they are not currently supported: .asm0, .endr, .lab, .struct. */
252b5132 1738
e972090a
NC
1739static const pseudo_typeS mips_pseudo_table[] =
1740{
beae10d5 1741 /* MIPS specific pseudo-ops. */
252b5132
RH
1742 {"option", s_option, 0},
1743 {"set", s_mipsset, 0},
1744 {"rdata", s_change_sec, 'r'},
1745 {"sdata", s_change_sec, 's'},
1746 {"livereg", s_ignore, 0},
1747 {"abicalls", s_abicalls, 0},
1748 {"cpload", s_cpload, 0},
6478892d
TS
1749 {"cpsetup", s_cpsetup, 0},
1750 {"cplocal", s_cplocal, 0},
252b5132 1751 {"cprestore", s_cprestore, 0},
6478892d 1752 {"cpreturn", s_cpreturn, 0},
741d6ea8
JM
1753 {"dtprelword", s_dtprelword, 0},
1754 {"dtpreldword", s_dtpreldword, 0},
d0f13682
CLT
1755 {"tprelword", s_tprelword, 0},
1756 {"tpreldword", s_tpreldword, 0},
6478892d 1757 {"gpvalue", s_gpvalue, 0},
252b5132 1758 {"gpword", s_gpword, 0},
10181a0d 1759 {"gpdword", s_gpdword, 0},
a3f278e2 1760 {"ehword", s_ehword, 0},
252b5132
RH
1761 {"cpadd", s_cpadd, 0},
1762 {"insn", s_insn, 0},
ba92f887 1763 {"nan", s_nan, 0},
919731af 1764 {"module", s_module, 0},
252b5132 1765
beae10d5 1766 /* Relatively generic pseudo-ops that happen to be used on MIPS
252b5132 1767 chips. */
38a57ae7 1768 {"asciiz", stringer, 8 + 1},
252b5132
RH
1769 {"bss", s_change_sec, 'b'},
1770 {"err", s_err, 0},
1771 {"half", s_cons, 1},
1772 {"dword", s_cons, 3},
1773 {"weakext", s_mips_weakext, 0},
7c752c2a
TS
1774 {"origin", s_org, 0},
1775 {"repeat", s_rept, 0},
252b5132 1776
998b3c36
MR
1777 /* For MIPS this is non-standard, but we define it for consistency. */
1778 {"sbss", s_change_sec, 'B'},
1779
beae10d5 1780 /* These pseudo-ops are defined in read.c, but must be overridden
252b5132
RH
1781 here for one reason or another. */
1782 {"align", s_align, 0},
1783 {"byte", s_cons, 0},
1784 {"data", s_change_sec, 'd'},
1785 {"double", s_float_cons, 'd'},
1786 {"float", s_float_cons, 'f'},
1787 {"globl", s_mips_globl, 0},
1788 {"global", s_mips_globl, 0},
1789 {"hword", s_cons, 1},
1790 {"int", s_cons, 2},
1791 {"long", s_cons, 2},
1792 {"octa", s_cons, 4},
1793 {"quad", s_cons, 3},
cca86cc8 1794 {"section", s_change_section, 0},
252b5132
RH
1795 {"short", s_cons, 1},
1796 {"single", s_float_cons, 'f'},
754e2bb9 1797 {"stabd", s_mips_stab, 'd'},
252b5132 1798 {"stabn", s_mips_stab, 'n'},
754e2bb9 1799 {"stabs", s_mips_stab, 's'},
252b5132
RH
1800 {"text", s_change_sec, 't'},
1801 {"word", s_cons, 2},
add56521 1802
add56521 1803 { "extern", ecoff_directive_extern, 0},
add56521 1804
43841e91 1805 { NULL, NULL, 0 },
252b5132
RH
1806};
1807
e972090a
NC
1808static const pseudo_typeS mips_nonecoff_pseudo_table[] =
1809{
beae10d5
KH
1810 /* These pseudo-ops should be defined by the object file format.
1811 However, a.out doesn't support them, so we have versions here. */
252b5132
RH
1812 {"aent", s_mips_ent, 1},
1813 {"bgnb", s_ignore, 0},
1814 {"end", s_mips_end, 0},
1815 {"endb", s_ignore, 0},
1816 {"ent", s_mips_ent, 0},
c5dd6aab 1817 {"file", s_mips_file, 0},
252b5132
RH
1818 {"fmask", s_mips_mask, 'F'},
1819 {"frame", s_mips_frame, 0},
c5dd6aab 1820 {"loc", s_mips_loc, 0},
252b5132
RH
1821 {"mask", s_mips_mask, 'R'},
1822 {"verstamp", s_ignore, 0},
43841e91 1823 { NULL, NULL, 0 },
252b5132
RH
1824};
1825
3ae8dd8d
MR
1826/* Export the ABI address size for use by TC_ADDRESS_BYTES for the
1827 purpose of the `.dc.a' internal pseudo-op. */
1828
1829int
1830mips_address_bytes (void)
1831{
919731af 1832 file_mips_check_options ();
3ae8dd8d
MR
1833 return HAVE_64BIT_ADDRESSES ? 8 : 4;
1834}
1835
17a2f251 1836extern void pop_insert (const pseudo_typeS *);
252b5132
RH
1837
1838void
17a2f251 1839mips_pop_insert (void)
252b5132
RH
1840{
1841 pop_insert (mips_pseudo_table);
1842 if (! ECOFF_DEBUGGING)
1843 pop_insert (mips_nonecoff_pseudo_table);
1844}
1845\f
1846/* Symbols labelling the current insn. */
1847
e972090a
NC
1848struct insn_label_list
1849{
252b5132
RH
1850 struct insn_label_list *next;
1851 symbolS *label;
1852};
1853
252b5132 1854static struct insn_label_list *free_insn_labels;
742a56fe 1855#define label_list tc_segment_info_data.labels
252b5132 1856
17a2f251 1857static void mips_clear_insn_labels (void);
df58fc94
RS
1858static void mips_mark_labels (void);
1859static void mips_compressed_mark_labels (void);
252b5132
RH
1860
1861static inline void
17a2f251 1862mips_clear_insn_labels (void)
252b5132 1863{
ed9e98c2 1864 struct insn_label_list **pl;
a8dbcb85 1865 segment_info_type *si;
252b5132 1866
a8dbcb85
TS
1867 if (now_seg)
1868 {
1869 for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next)
1870 ;
1871
1872 si = seg_info (now_seg);
1873 *pl = si->label_list;
1874 si->label_list = NULL;
1875 }
252b5132 1876}
a8dbcb85 1877
df58fc94
RS
1878/* Mark instruction labels in MIPS16/microMIPS mode. */
1879
1880static inline void
1881mips_mark_labels (void)
1882{
1883 if (HAVE_CODE_COMPRESSION)
1884 mips_compressed_mark_labels ();
1885}
252b5132
RH
1886\f
1887static char *expr_end;
1888
e423441d 1889/* An expression in a macro instruction. This is set by mips_ip and
b0e6f033 1890 mips16_ip and when populated is always an O_constant. */
252b5132
RH
1891
1892static expressionS imm_expr;
252b5132 1893
77bd4346
RS
1894/* The relocatable field in an instruction and the relocs associated
1895 with it. These variables are used for instructions like LUI and
1896 JAL as well as true offsets. They are also used for address
1897 operands in macros. */
252b5132 1898
77bd4346 1899static expressionS offset_expr;
f6688943
TS
1900static bfd_reloc_code_real_type offset_reloc[3]
1901 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
252b5132 1902
df58fc94
RS
1903/* This is set to the resulting size of the instruction to be produced
1904 by mips16_ip if an explicit extension is used or by mips_ip if an
1905 explicit size is supplied. */
252b5132 1906
df58fc94 1907static unsigned int forced_insn_length;
252b5132 1908
e1b47bd5
RS
1909/* True if we are assembling an instruction. All dot symbols defined during
1910 this time should be treated as code labels. */
1911
1912static bfd_boolean mips_assembling_insn;
1913
ecb4347a
DJ
1914/* The pdr segment for per procedure frame/regmask info. Not used for
1915 ECOFF debugging. */
252b5132
RH
1916
1917static segT pdr_seg;
252b5132 1918
e013f690
TS
1919/* The default target format to use. */
1920
aeffff67
RS
1921#if defined (TE_FreeBSD)
1922#define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd"
1923#elif defined (TE_TMIPS)
1924#define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips"
1925#else
1926#define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips"
1927#endif
1928
e013f690 1929const char *
17a2f251 1930mips_target_format (void)
e013f690
TS
1931{
1932 switch (OUTPUT_FLAVOR)
1933 {
e013f690 1934 case bfd_target_elf_flavour:
0a44bf69
RS
1935#ifdef TE_VXWORKS
1936 if (!HAVE_64BIT_OBJECTS && !HAVE_NEWABI)
1937 return (target_big_endian
1938 ? "elf32-bigmips-vxworks"
1939 : "elf32-littlemips-vxworks");
1940#endif
e013f690 1941 return (target_big_endian
cfe86eaa 1942 ? (HAVE_64BIT_OBJECTS
aeffff67 1943 ? ELF_TARGET ("elf64-", "big")
cfe86eaa 1944 : (HAVE_NEWABI
aeffff67
RS
1945 ? ELF_TARGET ("elf32-n", "big")
1946 : ELF_TARGET ("elf32-", "big")))
cfe86eaa 1947 : (HAVE_64BIT_OBJECTS
aeffff67 1948 ? ELF_TARGET ("elf64-", "little")
cfe86eaa 1949 : (HAVE_NEWABI
aeffff67
RS
1950 ? ELF_TARGET ("elf32-n", "little")
1951 : ELF_TARGET ("elf32-", "little"))));
e013f690
TS
1952 default:
1953 abort ();
1954 return NULL;
1955 }
1956}
1957
c6278170
RS
1958/* Return the ISA revision that is currently in use, or 0 if we are
1959 generating code for MIPS V or below. */
1960
1961static int
1962mips_isa_rev (void)
1963{
1964 if (mips_opts.isa == ISA_MIPS32R2 || mips_opts.isa == ISA_MIPS64R2)
1965 return 2;
1966
ae52f483
AB
1967 if (mips_opts.isa == ISA_MIPS32R3 || mips_opts.isa == ISA_MIPS64R3)
1968 return 3;
1969
1970 if (mips_opts.isa == ISA_MIPS32R5 || mips_opts.isa == ISA_MIPS64R5)
1971 return 5;
1972
7361da2c
AB
1973 if (mips_opts.isa == ISA_MIPS32R6 || mips_opts.isa == ISA_MIPS64R6)
1974 return 6;
1975
c6278170
RS
1976 /* microMIPS implies revision 2 or above. */
1977 if (mips_opts.micromips)
1978 return 2;
1979
1980 if (mips_opts.isa == ISA_MIPS32 || mips_opts.isa == ISA_MIPS64)
1981 return 1;
1982
1983 return 0;
1984}
1985
1986/* Return the mask of all ASEs that are revisions of those in FLAGS. */
1987
1988static unsigned int
1989mips_ase_mask (unsigned int flags)
1990{
1991 unsigned int i;
1992
1993 for (i = 0; i < ARRAY_SIZE (mips_ase_groups); i++)
1994 if (flags & mips_ase_groups[i])
1995 flags |= mips_ase_groups[i];
1996 return flags;
1997}
1998
1999/* Check whether the current ISA supports ASE. Issue a warning if
2000 appropriate. */
2001
2002static void
2003mips_check_isa_supports_ase (const struct mips_ase *ase)
2004{
2005 const char *base;
2006 int min_rev, size;
2007 static unsigned int warned_isa;
2008 static unsigned int warned_fp32;
2009
2010 if (ISA_HAS_64BIT_REGS (mips_opts.isa))
2011 min_rev = mips_opts.micromips ? ase->micromips64_rev : ase->mips64_rev;
2012 else
2013 min_rev = mips_opts.micromips ? ase->micromips32_rev : ase->mips32_rev;
2014 if ((min_rev < 0 || mips_isa_rev () < min_rev)
2015 && (warned_isa & ase->flags) != ase->flags)
2016 {
2017 warned_isa |= ase->flags;
2018 base = mips_opts.micromips ? "microMIPS" : "MIPS";
2019 size = ISA_HAS_64BIT_REGS (mips_opts.isa) ? 64 : 32;
2020 if (min_rev < 0)
1661c76c 2021 as_warn (_("the %d-bit %s architecture does not support the"
c6278170
RS
2022 " `%s' extension"), size, base, ase->name);
2023 else
1661c76c 2024 as_warn (_("the `%s' extension requires %s%d revision %d or greater"),
c6278170
RS
2025 ase->name, base, size, min_rev);
2026 }
7361da2c
AB
2027 else if ((ase->rem_rev > 0 && mips_isa_rev () >= ase->rem_rev)
2028 && (warned_isa & ase->flags) != ase->flags)
2029 {
2030 warned_isa |= ase->flags;
2031 base = mips_opts.micromips ? "microMIPS" : "MIPS";
2032 size = ISA_HAS_64BIT_REGS (mips_opts.isa) ? 64 : 32;
2033 as_warn (_("the `%s' extension was removed in %s%d revision %d"),
2034 ase->name, base, size, ase->rem_rev);
2035 }
2036
c6278170 2037 if ((ase->flags & FP64_ASES)
0b35dfee 2038 && mips_opts.fp != 64
c6278170
RS
2039 && (warned_fp32 & ase->flags) != ase->flags)
2040 {
2041 warned_fp32 |= ase->flags;
1661c76c 2042 as_warn (_("the `%s' extension requires 64-bit FPRs"), ase->name);
c6278170
RS
2043 }
2044}
2045
2046/* Check all enabled ASEs to see whether they are supported by the
2047 chosen architecture. */
2048
2049static void
2050mips_check_isa_supports_ases (void)
2051{
2052 unsigned int i, mask;
2053
2054 for (i = 0; i < ARRAY_SIZE (mips_ases); i++)
2055 {
2056 mask = mips_ase_mask (mips_ases[i].flags);
2057 if ((mips_opts.ase & mask) == mips_ases[i].flags)
2058 mips_check_isa_supports_ase (&mips_ases[i]);
2059 }
2060}
2061
2062/* Set the state of ASE to ENABLED_P. Return the mask of ASE_* flags
2063 that were affected. */
2064
2065static unsigned int
919731af 2066mips_set_ase (const struct mips_ase *ase, struct mips_set_options *opts,
2067 bfd_boolean enabled_p)
c6278170
RS
2068{
2069 unsigned int mask;
2070
2071 mask = mips_ase_mask (ase->flags);
919731af 2072 opts->ase &= ~mask;
c6278170 2073 if (enabled_p)
919731af 2074 opts->ase |= ase->flags;
c6278170
RS
2075 return mask;
2076}
2077
2078/* Return the ASE called NAME, or null if none. */
2079
2080static const struct mips_ase *
2081mips_lookup_ase (const char *name)
2082{
2083 unsigned int i;
2084
2085 for (i = 0; i < ARRAY_SIZE (mips_ases); i++)
2086 if (strcmp (name, mips_ases[i].name) == 0)
2087 return &mips_ases[i];
2088 return NULL;
2089}
2090
df58fc94
RS
2091/* Return the length of a microMIPS instruction in bytes. If bits of
2092 the mask beyond the low 16 are 0, then it is a 16-bit instruction.
2093 Otherwise assume a 32-bit instruction; 48-bit instructions (0x1f
2094 major opcode) will require further modifications to the opcode
2095 table. */
2096
2097static inline unsigned int
2098micromips_insn_length (const struct mips_opcode *mo)
2099{
2100 return (mo->mask >> 16) == 0 ? 2 : 4;
2101}
2102
5c04167a
RS
2103/* Return the length of MIPS16 instruction OPCODE. */
2104
2105static inline unsigned int
2106mips16_opcode_length (unsigned long opcode)
2107{
2108 return (opcode >> 16) == 0 ? 2 : 4;
2109}
2110
1e915849
RS
2111/* Return the length of instruction INSN. */
2112
2113static inline unsigned int
2114insn_length (const struct mips_cl_insn *insn)
2115{
df58fc94
RS
2116 if (mips_opts.micromips)
2117 return micromips_insn_length (insn->insn_mo);
2118 else if (mips_opts.mips16)
5c04167a 2119 return mips16_opcode_length (insn->insn_opcode);
df58fc94 2120 else
1e915849 2121 return 4;
1e915849
RS
2122}
2123
2124/* Initialise INSN from opcode entry MO. Leave its position unspecified. */
2125
2126static void
2127create_insn (struct mips_cl_insn *insn, const struct mips_opcode *mo)
2128{
2129 size_t i;
2130
2131 insn->insn_mo = mo;
1e915849
RS
2132 insn->insn_opcode = mo->match;
2133 insn->frag = NULL;
2134 insn->where = 0;
2135 for (i = 0; i < ARRAY_SIZE (insn->fixp); i++)
2136 insn->fixp[i] = NULL;
2137 insn->fixed_p = (mips_opts.noreorder > 0);
2138 insn->noreorder_p = (mips_opts.noreorder > 0);
2139 insn->mips16_absolute_jump_p = 0;
15be625d 2140 insn->complete_p = 0;
e407c74b 2141 insn->cleared_p = 0;
1e915849
RS
2142}
2143
fc76e730
RS
2144/* Get a list of all the operands in INSN. */
2145
2146static const struct mips_operand_array *
2147insn_operands (const struct mips_cl_insn *insn)
2148{
2149 if (insn->insn_mo >= &mips_opcodes[0]
2150 && insn->insn_mo < &mips_opcodes[NUMOPCODES])
2151 return &mips_operands[insn->insn_mo - &mips_opcodes[0]];
2152
2153 if (insn->insn_mo >= &mips16_opcodes[0]
2154 && insn->insn_mo < &mips16_opcodes[bfd_mips16_num_opcodes])
2155 return &mips16_operands[insn->insn_mo - &mips16_opcodes[0]];
2156
2157 if (insn->insn_mo >= &micromips_opcodes[0]
2158 && insn->insn_mo < &micromips_opcodes[bfd_micromips_num_opcodes])
2159 return &micromips_operands[insn->insn_mo - &micromips_opcodes[0]];
2160
2161 abort ();
2162}
2163
2164/* Get a description of operand OPNO of INSN. */
2165
2166static const struct mips_operand *
2167insn_opno (const struct mips_cl_insn *insn, unsigned opno)
2168{
2169 const struct mips_operand_array *operands;
2170
2171 operands = insn_operands (insn);
2172 if (opno >= MAX_OPERANDS || !operands->operand[opno])
2173 abort ();
2174 return operands->operand[opno];
2175}
2176
e077a1c8
RS
2177/* Install UVAL as the value of OPERAND in INSN. */
2178
2179static inline void
2180insn_insert_operand (struct mips_cl_insn *insn,
2181 const struct mips_operand *operand, unsigned int uval)
2182{
2183 insn->insn_opcode = mips_insert_operand (operand, insn->insn_opcode, uval);
2184}
2185
fc76e730
RS
2186/* Extract the value of OPERAND from INSN. */
2187
2188static inline unsigned
2189insn_extract_operand (const struct mips_cl_insn *insn,
2190 const struct mips_operand *operand)
2191{
2192 return mips_extract_operand (operand, insn->insn_opcode);
2193}
2194
df58fc94 2195/* Record the current MIPS16/microMIPS mode in now_seg. */
742a56fe
RS
2196
2197static void
df58fc94 2198mips_record_compressed_mode (void)
742a56fe
RS
2199{
2200 segment_info_type *si;
2201
2202 si = seg_info (now_seg);
2203 if (si->tc_segment_info_data.mips16 != mips_opts.mips16)
2204 si->tc_segment_info_data.mips16 = mips_opts.mips16;
df58fc94
RS
2205 if (si->tc_segment_info_data.micromips != mips_opts.micromips)
2206 si->tc_segment_info_data.micromips = mips_opts.micromips;
742a56fe
RS
2207}
2208
4d68580a
RS
2209/* Read a standard MIPS instruction from BUF. */
2210
2211static unsigned long
2212read_insn (char *buf)
2213{
2214 if (target_big_endian)
2215 return bfd_getb32 ((bfd_byte *) buf);
2216 else
2217 return bfd_getl32 ((bfd_byte *) buf);
2218}
2219
2220/* Write standard MIPS instruction INSN to BUF. Return a pointer to
2221 the next byte. */
2222
2223static char *
2224write_insn (char *buf, unsigned int insn)
2225{
2226 md_number_to_chars (buf, insn, 4);
2227 return buf + 4;
2228}
2229
2230/* Read a microMIPS or MIPS16 opcode from BUF, given that it
2231 has length LENGTH. */
2232
2233static unsigned long
2234read_compressed_insn (char *buf, unsigned int length)
2235{
2236 unsigned long insn;
2237 unsigned int i;
2238
2239 insn = 0;
2240 for (i = 0; i < length; i += 2)
2241 {
2242 insn <<= 16;
2243 if (target_big_endian)
2244 insn |= bfd_getb16 ((char *) buf);
2245 else
2246 insn |= bfd_getl16 ((char *) buf);
2247 buf += 2;
2248 }
2249 return insn;
2250}
2251
5c04167a
RS
2252/* Write microMIPS or MIPS16 instruction INSN to BUF, given that the
2253 instruction is LENGTH bytes long. Return a pointer to the next byte. */
2254
2255static char *
2256write_compressed_insn (char *buf, unsigned int insn, unsigned int length)
2257{
2258 unsigned int i;
2259
2260 for (i = 0; i < length; i += 2)
2261 md_number_to_chars (buf + i, insn >> ((length - i - 2) * 8), 2);
2262 return buf + length;
2263}
2264
1e915849
RS
2265/* Install INSN at the location specified by its "frag" and "where" fields. */
2266
2267static void
2268install_insn (const struct mips_cl_insn *insn)
2269{
2270 char *f = insn->frag->fr_literal + insn->where;
5c04167a
RS
2271 if (HAVE_CODE_COMPRESSION)
2272 write_compressed_insn (f, insn->insn_opcode, insn_length (insn));
1e915849 2273 else
4d68580a 2274 write_insn (f, insn->insn_opcode);
df58fc94 2275 mips_record_compressed_mode ();
1e915849
RS
2276}
2277
2278/* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
2279 and install the opcode in the new location. */
2280
2281static void
2282move_insn (struct mips_cl_insn *insn, fragS *frag, long where)
2283{
2284 size_t i;
2285
2286 insn->frag = frag;
2287 insn->where = where;
2288 for (i = 0; i < ARRAY_SIZE (insn->fixp); i++)
2289 if (insn->fixp[i] != NULL)
2290 {
2291 insn->fixp[i]->fx_frag = frag;
2292 insn->fixp[i]->fx_where = where;
2293 }
2294 install_insn (insn);
2295}
2296
2297/* Add INSN to the end of the output. */
2298
2299static void
2300add_fixed_insn (struct mips_cl_insn *insn)
2301{
2302 char *f = frag_more (insn_length (insn));
2303 move_insn (insn, frag_now, f - frag_now->fr_literal);
2304}
2305
2306/* Start a variant frag and move INSN to the start of the variant part,
2307 marking it as fixed. The other arguments are as for frag_var. */
2308
2309static void
2310add_relaxed_insn (struct mips_cl_insn *insn, int max_chars, int var,
2311 relax_substateT subtype, symbolS *symbol, offsetT offset)
2312{
2313 frag_grow (max_chars);
2314 move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal);
2315 insn->fixed_p = 1;
2316 frag_var (rs_machine_dependent, max_chars, var,
2317 subtype, symbol, offset, NULL);
2318}
2319
2320/* Insert N copies of INSN into the history buffer, starting at
2321 position FIRST. Neither FIRST nor N need to be clipped. */
2322
2323static void
2324insert_into_history (unsigned int first, unsigned int n,
2325 const struct mips_cl_insn *insn)
2326{
2327 if (mips_relax.sequence != 2)
2328 {
2329 unsigned int i;
2330
2331 for (i = ARRAY_SIZE (history); i-- > first;)
2332 if (i >= first + n)
2333 history[i] = history[i - n];
2334 else
2335 history[i] = *insn;
2336 }
2337}
2338
e3de51ce
RS
2339/* Clear the error in insn_error. */
2340
2341static void
2342clear_insn_error (void)
2343{
2344 memset (&insn_error, 0, sizeof (insn_error));
2345}
2346
2347/* Possibly record error message MSG for the current instruction.
2348 If the error is about a particular argument, ARGNUM is the 1-based
2349 number of that argument, otherwise it is 0. FORMAT is the format
2350 of MSG. Return true if MSG was used, false if the current message
2351 was kept. */
2352
2353static bfd_boolean
2354set_insn_error_format (int argnum, enum mips_insn_error_format format,
2355 const char *msg)
2356{
2357 if (argnum == 0)
2358 {
2359 /* Give priority to errors against specific arguments, and to
2360 the first whole-instruction message. */
2361 if (insn_error.msg)
2362 return FALSE;
2363 }
2364 else
2365 {
2366 /* Keep insn_error if it is against a later argument. */
2367 if (argnum < insn_error.min_argnum)
2368 return FALSE;
2369
2370 /* If both errors are against the same argument but are different,
2371 give up on reporting a specific error for this argument.
2372 See the comment about mips_insn_error for details. */
2373 if (argnum == insn_error.min_argnum
2374 && insn_error.msg
2375 && strcmp (insn_error.msg, msg) != 0)
2376 {
2377 insn_error.msg = 0;
2378 insn_error.min_argnum += 1;
2379 return FALSE;
2380 }
2381 }
2382 insn_error.min_argnum = argnum;
2383 insn_error.format = format;
2384 insn_error.msg = msg;
2385 return TRUE;
2386}
2387
2388/* Record an instruction error with no % format fields. ARGNUM and MSG are
2389 as for set_insn_error_format. */
2390
2391static void
2392set_insn_error (int argnum, const char *msg)
2393{
2394 set_insn_error_format (argnum, ERR_FMT_PLAIN, msg);
2395}
2396
2397/* Record an instruction error with one %d field I. ARGNUM and MSG are
2398 as for set_insn_error_format. */
2399
2400static void
2401set_insn_error_i (int argnum, const char *msg, int i)
2402{
2403 if (set_insn_error_format (argnum, ERR_FMT_I, msg))
2404 insn_error.u.i = i;
2405}
2406
2407/* Record an instruction error with two %s fields S1 and S2. ARGNUM and MSG
2408 are as for set_insn_error_format. */
2409
2410static void
2411set_insn_error_ss (int argnum, const char *msg, const char *s1, const char *s2)
2412{
2413 if (set_insn_error_format (argnum, ERR_FMT_SS, msg))
2414 {
2415 insn_error.u.ss[0] = s1;
2416 insn_error.u.ss[1] = s2;
2417 }
2418}
2419
2420/* Report the error in insn_error, which is against assembly code STR. */
2421
2422static void
2423report_insn_error (const char *str)
2424{
2425 const char *msg;
2426
2427 msg = ACONCAT ((insn_error.msg, " `%s'", NULL));
2428 switch (insn_error.format)
2429 {
2430 case ERR_FMT_PLAIN:
2431 as_bad (msg, str);
2432 break;
2433
2434 case ERR_FMT_I:
2435 as_bad (msg, insn_error.u.i, str);
2436 break;
2437
2438 case ERR_FMT_SS:
2439 as_bad (msg, insn_error.u.ss[0], insn_error.u.ss[1], str);
2440 break;
2441 }
2442}
2443
71400594
RS
2444/* Initialize vr4120_conflicts. There is a bit of duplication here:
2445 the idea is to make it obvious at a glance that each errata is
2446 included. */
2447
2448static void
2449init_vr4120_conflicts (void)
2450{
2451#define CONFLICT(FIRST, SECOND) \
2452 vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND
2453
2454 /* Errata 21 - [D]DIV[U] after [D]MACC */
2455 CONFLICT (MACC, DIV);
2456 CONFLICT (DMACC, DIV);
2457
2458 /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */
2459 CONFLICT (DMULT, DMULT);
2460 CONFLICT (DMULT, DMACC);
2461 CONFLICT (DMACC, DMULT);
2462 CONFLICT (DMACC, DMACC);
2463
2464 /* Errata 24 - MT{LO,HI} after [D]MACC */
2465 CONFLICT (MACC, MTHILO);
2466 CONFLICT (DMACC, MTHILO);
2467
2468 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
2469 instruction is executed immediately after a MACC or DMACC
2470 instruction, the result of [either instruction] is incorrect." */
2471 CONFLICT (MACC, MULT);
2472 CONFLICT (MACC, DMULT);
2473 CONFLICT (DMACC, MULT);
2474 CONFLICT (DMACC, DMULT);
2475
2476 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
2477 executed immediately after a DMULT, DMULTU, DIV, DIVU,
2478 DDIV or DDIVU instruction, the result of the MACC or
2479 DMACC instruction is incorrect.". */
2480 CONFLICT (DMULT, MACC);
2481 CONFLICT (DMULT, DMACC);
2482 CONFLICT (DIV, MACC);
2483 CONFLICT (DIV, DMACC);
2484
2485#undef CONFLICT
2486}
2487
707bfff6
TS
2488struct regname {
2489 const char *name;
2490 unsigned int num;
2491};
2492
14daeee3 2493#define RNUM_MASK 0x00000ff
56d438b1 2494#define RTYPE_MASK 0x0ffff00
14daeee3
RS
2495#define RTYPE_NUM 0x0000100
2496#define RTYPE_FPU 0x0000200
2497#define RTYPE_FCC 0x0000400
2498#define RTYPE_VEC 0x0000800
2499#define RTYPE_GP 0x0001000
2500#define RTYPE_CP0 0x0002000
2501#define RTYPE_PC 0x0004000
2502#define RTYPE_ACC 0x0008000
2503#define RTYPE_CCC 0x0010000
2504#define RTYPE_VI 0x0020000
2505#define RTYPE_VF 0x0040000
2506#define RTYPE_R5900_I 0x0080000
2507#define RTYPE_R5900_Q 0x0100000
2508#define RTYPE_R5900_R 0x0200000
2509#define RTYPE_R5900_ACC 0x0400000
56d438b1 2510#define RTYPE_MSA 0x0800000
14daeee3 2511#define RWARN 0x8000000
707bfff6
TS
2512
2513#define GENERIC_REGISTER_NUMBERS \
2514 {"$0", RTYPE_NUM | 0}, \
2515 {"$1", RTYPE_NUM | 1}, \
2516 {"$2", RTYPE_NUM | 2}, \
2517 {"$3", RTYPE_NUM | 3}, \
2518 {"$4", RTYPE_NUM | 4}, \
2519 {"$5", RTYPE_NUM | 5}, \
2520 {"$6", RTYPE_NUM | 6}, \
2521 {"$7", RTYPE_NUM | 7}, \
2522 {"$8", RTYPE_NUM | 8}, \
2523 {"$9", RTYPE_NUM | 9}, \
2524 {"$10", RTYPE_NUM | 10}, \
2525 {"$11", RTYPE_NUM | 11}, \
2526 {"$12", RTYPE_NUM | 12}, \
2527 {"$13", RTYPE_NUM | 13}, \
2528 {"$14", RTYPE_NUM | 14}, \
2529 {"$15", RTYPE_NUM | 15}, \
2530 {"$16", RTYPE_NUM | 16}, \
2531 {"$17", RTYPE_NUM | 17}, \
2532 {"$18", RTYPE_NUM | 18}, \
2533 {"$19", RTYPE_NUM | 19}, \
2534 {"$20", RTYPE_NUM | 20}, \
2535 {"$21", RTYPE_NUM | 21}, \
2536 {"$22", RTYPE_NUM | 22}, \
2537 {"$23", RTYPE_NUM | 23}, \
2538 {"$24", RTYPE_NUM | 24}, \
2539 {"$25", RTYPE_NUM | 25}, \
2540 {"$26", RTYPE_NUM | 26}, \
2541 {"$27", RTYPE_NUM | 27}, \
2542 {"$28", RTYPE_NUM | 28}, \
2543 {"$29", RTYPE_NUM | 29}, \
2544 {"$30", RTYPE_NUM | 30}, \
2545 {"$31", RTYPE_NUM | 31}
2546
2547#define FPU_REGISTER_NAMES \
2548 {"$f0", RTYPE_FPU | 0}, \
2549 {"$f1", RTYPE_FPU | 1}, \
2550 {"$f2", RTYPE_FPU | 2}, \
2551 {"$f3", RTYPE_FPU | 3}, \
2552 {"$f4", RTYPE_FPU | 4}, \
2553 {"$f5", RTYPE_FPU | 5}, \
2554 {"$f6", RTYPE_FPU | 6}, \
2555 {"$f7", RTYPE_FPU | 7}, \
2556 {"$f8", RTYPE_FPU | 8}, \
2557 {"$f9", RTYPE_FPU | 9}, \
2558 {"$f10", RTYPE_FPU | 10}, \
2559 {"$f11", RTYPE_FPU | 11}, \
2560 {"$f12", RTYPE_FPU | 12}, \
2561 {"$f13", RTYPE_FPU | 13}, \
2562 {"$f14", RTYPE_FPU | 14}, \
2563 {"$f15", RTYPE_FPU | 15}, \
2564 {"$f16", RTYPE_FPU | 16}, \
2565 {"$f17", RTYPE_FPU | 17}, \
2566 {"$f18", RTYPE_FPU | 18}, \
2567 {"$f19", RTYPE_FPU | 19}, \
2568 {"$f20", RTYPE_FPU | 20}, \
2569 {"$f21", RTYPE_FPU | 21}, \
2570 {"$f22", RTYPE_FPU | 22}, \
2571 {"$f23", RTYPE_FPU | 23}, \
2572 {"$f24", RTYPE_FPU | 24}, \
2573 {"$f25", RTYPE_FPU | 25}, \
2574 {"$f26", RTYPE_FPU | 26}, \
2575 {"$f27", RTYPE_FPU | 27}, \
2576 {"$f28", RTYPE_FPU | 28}, \
2577 {"$f29", RTYPE_FPU | 29}, \
2578 {"$f30", RTYPE_FPU | 30}, \
2579 {"$f31", RTYPE_FPU | 31}
2580
2581#define FPU_CONDITION_CODE_NAMES \
2582 {"$fcc0", RTYPE_FCC | 0}, \
2583 {"$fcc1", RTYPE_FCC | 1}, \
2584 {"$fcc2", RTYPE_FCC | 2}, \
2585 {"$fcc3", RTYPE_FCC | 3}, \
2586 {"$fcc4", RTYPE_FCC | 4}, \
2587 {"$fcc5", RTYPE_FCC | 5}, \
2588 {"$fcc6", RTYPE_FCC | 6}, \
2589 {"$fcc7", RTYPE_FCC | 7}
2590
2591#define COPROC_CONDITION_CODE_NAMES \
2592 {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \
2593 {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \
2594 {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \
2595 {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \
2596 {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \
2597 {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \
2598 {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \
2599 {"$cc7", RTYPE_FCC | RTYPE_CCC | 7}
2600
2601#define N32N64_SYMBOLIC_REGISTER_NAMES \
2602 {"$a4", RTYPE_GP | 8}, \
2603 {"$a5", RTYPE_GP | 9}, \
2604 {"$a6", RTYPE_GP | 10}, \
2605 {"$a7", RTYPE_GP | 11}, \
2606 {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \
2607 {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \
2608 {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \
2609 {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \
2610 {"$t0", RTYPE_GP | 12}, \
2611 {"$t1", RTYPE_GP | 13}, \
2612 {"$t2", RTYPE_GP | 14}, \
2613 {"$t3", RTYPE_GP | 15}
2614
2615#define O32_SYMBOLIC_REGISTER_NAMES \
2616 {"$t0", RTYPE_GP | 8}, \
2617 {"$t1", RTYPE_GP | 9}, \
2618 {"$t2", RTYPE_GP | 10}, \
2619 {"$t3", RTYPE_GP | 11}, \
2620 {"$t4", RTYPE_GP | 12}, \
2621 {"$t5", RTYPE_GP | 13}, \
2622 {"$t6", RTYPE_GP | 14}, \
2623 {"$t7", RTYPE_GP | 15}, \
2624 {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \
2625 {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \
2626 {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \
2627 {"$ta3", RTYPE_GP | 15} /* alias for $t7 */
2628
2629/* Remaining symbolic register names */
2630#define SYMBOLIC_REGISTER_NAMES \
2631 {"$zero", RTYPE_GP | 0}, \
2632 {"$at", RTYPE_GP | 1}, \
2633 {"$AT", RTYPE_GP | 1}, \
2634 {"$v0", RTYPE_GP | 2}, \
2635 {"$v1", RTYPE_GP | 3}, \
2636 {"$a0", RTYPE_GP | 4}, \
2637 {"$a1", RTYPE_GP | 5}, \
2638 {"$a2", RTYPE_GP | 6}, \
2639 {"$a3", RTYPE_GP | 7}, \
2640 {"$s0", RTYPE_GP | 16}, \
2641 {"$s1", RTYPE_GP | 17}, \
2642 {"$s2", RTYPE_GP | 18}, \
2643 {"$s3", RTYPE_GP | 19}, \
2644 {"$s4", RTYPE_GP | 20}, \
2645 {"$s5", RTYPE_GP | 21}, \
2646 {"$s6", RTYPE_GP | 22}, \
2647 {"$s7", RTYPE_GP | 23}, \
2648 {"$t8", RTYPE_GP | 24}, \
2649 {"$t9", RTYPE_GP | 25}, \
2650 {"$k0", RTYPE_GP | 26}, \
2651 {"$kt0", RTYPE_GP | 26}, \
2652 {"$k1", RTYPE_GP | 27}, \
2653 {"$kt1", RTYPE_GP | 27}, \
2654 {"$gp", RTYPE_GP | 28}, \
2655 {"$sp", RTYPE_GP | 29}, \
2656 {"$s8", RTYPE_GP | 30}, \
2657 {"$fp", RTYPE_GP | 30}, \
2658 {"$ra", RTYPE_GP | 31}
2659
2660#define MIPS16_SPECIAL_REGISTER_NAMES \
2661 {"$pc", RTYPE_PC | 0}
2662
2663#define MDMX_VECTOR_REGISTER_NAMES \
2664 /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \
2665 /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \
2666 {"$v2", RTYPE_VEC | 2}, \
2667 {"$v3", RTYPE_VEC | 3}, \
2668 {"$v4", RTYPE_VEC | 4}, \
2669 {"$v5", RTYPE_VEC | 5}, \
2670 {"$v6", RTYPE_VEC | 6}, \
2671 {"$v7", RTYPE_VEC | 7}, \
2672 {"$v8", RTYPE_VEC | 8}, \
2673 {"$v9", RTYPE_VEC | 9}, \
2674 {"$v10", RTYPE_VEC | 10}, \
2675 {"$v11", RTYPE_VEC | 11}, \
2676 {"$v12", RTYPE_VEC | 12}, \
2677 {"$v13", RTYPE_VEC | 13}, \
2678 {"$v14", RTYPE_VEC | 14}, \
2679 {"$v15", RTYPE_VEC | 15}, \
2680 {"$v16", RTYPE_VEC | 16}, \
2681 {"$v17", RTYPE_VEC | 17}, \
2682 {"$v18", RTYPE_VEC | 18}, \
2683 {"$v19", RTYPE_VEC | 19}, \
2684 {"$v20", RTYPE_VEC | 20}, \
2685 {"$v21", RTYPE_VEC | 21}, \
2686 {"$v22", RTYPE_VEC | 22}, \
2687 {"$v23", RTYPE_VEC | 23}, \
2688 {"$v24", RTYPE_VEC | 24}, \
2689 {"$v25", RTYPE_VEC | 25}, \
2690 {"$v26", RTYPE_VEC | 26}, \
2691 {"$v27", RTYPE_VEC | 27}, \
2692 {"$v28", RTYPE_VEC | 28}, \
2693 {"$v29", RTYPE_VEC | 29}, \
2694 {"$v30", RTYPE_VEC | 30}, \
2695 {"$v31", RTYPE_VEC | 31}
2696
14daeee3
RS
2697#define R5900_I_NAMES \
2698 {"$I", RTYPE_R5900_I | 0}
2699
2700#define R5900_Q_NAMES \
2701 {"$Q", RTYPE_R5900_Q | 0}
2702
2703#define R5900_R_NAMES \
2704 {"$R", RTYPE_R5900_R | 0}
2705
2706#define R5900_ACC_NAMES \
2707 {"$ACC", RTYPE_R5900_ACC | 0 }
2708
707bfff6
TS
2709#define MIPS_DSP_ACCUMULATOR_NAMES \
2710 {"$ac0", RTYPE_ACC | 0}, \
2711 {"$ac1", RTYPE_ACC | 1}, \
2712 {"$ac2", RTYPE_ACC | 2}, \
2713 {"$ac3", RTYPE_ACC | 3}
2714
2715static const struct regname reg_names[] = {
2716 GENERIC_REGISTER_NUMBERS,
2717 FPU_REGISTER_NAMES,
2718 FPU_CONDITION_CODE_NAMES,
2719 COPROC_CONDITION_CODE_NAMES,
2720
2721 /* The $txx registers depends on the abi,
2722 these will be added later into the symbol table from
2723 one of the tables below once mips_abi is set after
2724 parsing of arguments from the command line. */
2725 SYMBOLIC_REGISTER_NAMES,
2726
2727 MIPS16_SPECIAL_REGISTER_NAMES,
2728 MDMX_VECTOR_REGISTER_NAMES,
14daeee3
RS
2729 R5900_I_NAMES,
2730 R5900_Q_NAMES,
2731 R5900_R_NAMES,
2732 R5900_ACC_NAMES,
707bfff6
TS
2733 MIPS_DSP_ACCUMULATOR_NAMES,
2734 {0, 0}
2735};
2736
2737static const struct regname reg_names_o32[] = {
2738 O32_SYMBOLIC_REGISTER_NAMES,
2739 {0, 0}
2740};
2741
2742static const struct regname reg_names_n32n64[] = {
2743 N32N64_SYMBOLIC_REGISTER_NAMES,
2744 {0, 0}
2745};
2746
a92713e6
RS
2747/* Register symbols $v0 and $v1 map to GPRs 2 and 3, but they can also be
2748 interpreted as vector registers 0 and 1. If SYMVAL is the value of one
2749 of these register symbols, return the associated vector register,
2750 otherwise return SYMVAL itself. */
df58fc94 2751
a92713e6
RS
2752static unsigned int
2753mips_prefer_vec_regno (unsigned int symval)
707bfff6 2754{
a92713e6
RS
2755 if ((symval & -2) == (RTYPE_GP | 2))
2756 return RTYPE_VEC | (symval & 1);
2757 return symval;
2758}
2759
14daeee3
RS
2760/* Return true if string [S, E) is a valid register name, storing its
2761 symbol value in *SYMVAL_PTR if so. */
a92713e6
RS
2762
2763static bfd_boolean
14daeee3 2764mips_parse_register_1 (char *s, char *e, unsigned int *symval_ptr)
a92713e6 2765{
707bfff6 2766 char save_c;
14daeee3 2767 symbolS *symbol;
707bfff6
TS
2768
2769 /* Terminate name. */
2770 save_c = *e;
2771 *e = '\0';
2772
a92713e6
RS
2773 /* Look up the name. */
2774 symbol = symbol_find (s);
2775 *e = save_c;
2776
2777 if (!symbol || S_GET_SEGMENT (symbol) != reg_section)
2778 return FALSE;
2779
14daeee3
RS
2780 *symval_ptr = S_GET_VALUE (symbol);
2781 return TRUE;
2782}
2783
2784/* Return true if the string at *SPTR is a valid register name. Allow it
2785 to have a VU0-style channel suffix of the form x?y?z?w? if CHANNELS_PTR
2786 is nonnull.
2787
2788 When returning true, move *SPTR past the register, store the
2789 register's symbol value in *SYMVAL_PTR and the channel mask in
2790 *CHANNELS_PTR (if nonnull). The symbol value includes the register
2791 number (RNUM_MASK) and register type (RTYPE_MASK). The channel mask
2792 is a 4-bit value of the form XYZW and is 0 if no suffix was given. */
2793
2794static bfd_boolean
2795mips_parse_register (char **sptr, unsigned int *symval_ptr,
2796 unsigned int *channels_ptr)
2797{
2798 char *s, *e, *m;
2799 const char *q;
2800 unsigned int channels, symval, bit;
2801
2802 /* Find end of name. */
2803 s = e = *sptr;
2804 if (is_name_beginner (*e))
2805 ++e;
2806 while (is_part_of_name (*e))
2807 ++e;
2808
2809 channels = 0;
2810 if (!mips_parse_register_1 (s, e, &symval))
2811 {
2812 if (!channels_ptr)
2813 return FALSE;
2814
2815 /* Eat characters from the end of the string that are valid
2816 channel suffixes. The preceding register must be $ACC or
2817 end with a digit, so there is no ambiguity. */
2818 bit = 1;
2819 m = e;
2820 for (q = "wzyx"; *q; q++, bit <<= 1)
2821 if (m > s && m[-1] == *q)
2822 {
2823 --m;
2824 channels |= bit;
2825 }
2826
2827 if (channels == 0
2828 || !mips_parse_register_1 (s, m, &symval)
2829 || (symval & (RTYPE_VI | RTYPE_VF | RTYPE_R5900_ACC)) == 0)
2830 return FALSE;
2831 }
2832
a92713e6 2833 *sptr = e;
14daeee3
RS
2834 *symval_ptr = symval;
2835 if (channels_ptr)
2836 *channels_ptr = channels;
a92713e6
RS
2837 return TRUE;
2838}
2839
2840/* Check if SPTR points at a valid register specifier according to TYPES.
2841 If so, then return 1, advance S to consume the specifier and store
2842 the register's number in REGNOP, otherwise return 0. */
2843
2844static int
2845reg_lookup (char **s, unsigned int types, unsigned int *regnop)
2846{
2847 unsigned int regno;
2848
14daeee3 2849 if (mips_parse_register (s, &regno, NULL))
707bfff6 2850 {
a92713e6
RS
2851 if (types & RTYPE_VEC)
2852 regno = mips_prefer_vec_regno (regno);
2853 if (regno & types)
2854 regno &= RNUM_MASK;
2855 else
2856 regno = ~0;
707bfff6 2857 }
a92713e6 2858 else
707bfff6 2859 {
a92713e6 2860 if (types & RWARN)
1661c76c 2861 as_warn (_("unrecognized register name `%s'"), *s);
a92713e6 2862 regno = ~0;
707bfff6 2863 }
707bfff6 2864 if (regnop)
a92713e6
RS
2865 *regnop = regno;
2866 return regno <= RNUM_MASK;
707bfff6
TS
2867}
2868
14daeee3
RS
2869/* Parse a VU0 "x?y?z?w?" channel mask at S and store the associated
2870 mask in *CHANNELS. Return a pointer to the first unconsumed character. */
2871
2872static char *
2873mips_parse_vu0_channels (char *s, unsigned int *channels)
2874{
2875 unsigned int i;
2876
2877 *channels = 0;
2878 for (i = 0; i < 4; i++)
2879 if (*s == "xyzw"[i])
2880 {
2881 *channels |= 1 << (3 - i);
2882 ++s;
2883 }
2884 return s;
2885}
2886
a92713e6
RS
2887/* Token types for parsed operand lists. */
2888enum mips_operand_token_type {
2889 /* A plain register, e.g. $f2. */
2890 OT_REG,
df58fc94 2891
14daeee3
RS
2892 /* A 4-bit XYZW channel mask. */
2893 OT_CHANNELS,
2894
56d438b1
CF
2895 /* A constant vector index, e.g. [1]. */
2896 OT_INTEGER_INDEX,
2897
2898 /* A register vector index, e.g. [$2]. */
2899 OT_REG_INDEX,
df58fc94 2900
a92713e6
RS
2901 /* A continuous range of registers, e.g. $s0-$s4. */
2902 OT_REG_RANGE,
2903
2904 /* A (possibly relocated) expression. */
2905 OT_INTEGER,
2906
2907 /* A floating-point value. */
2908 OT_FLOAT,
2909
2910 /* A single character. This can be '(', ')' or ',', but '(' only appears
2911 before OT_REGs. */
2912 OT_CHAR,
2913
14daeee3
RS
2914 /* A doubled character, either "--" or "++". */
2915 OT_DOUBLE_CHAR,
2916
a92713e6
RS
2917 /* The end of the operand list. */
2918 OT_END
2919};
2920
2921/* A parsed operand token. */
2922struct mips_operand_token
2923{
2924 /* The type of token. */
2925 enum mips_operand_token_type type;
2926 union
2927 {
56d438b1 2928 /* The register symbol value for an OT_REG or OT_REG_INDEX. */
a92713e6
RS
2929 unsigned int regno;
2930
14daeee3
RS
2931 /* The 4-bit channel mask for an OT_CHANNEL_SUFFIX. */
2932 unsigned int channels;
2933
56d438b1
CF
2934 /* The integer value of an OT_INTEGER_INDEX. */
2935 addressT index;
a92713e6
RS
2936
2937 /* The two register symbol values involved in an OT_REG_RANGE. */
2938 struct {
2939 unsigned int regno1;
2940 unsigned int regno2;
2941 } reg_range;
2942
2943 /* The value of an OT_INTEGER. The value is represented as an
2944 expression and the relocation operators that were applied to
2945 that expression. The reloc entries are BFD_RELOC_UNUSED if no
2946 relocation operators were used. */
2947 struct {
2948 expressionS value;
2949 bfd_reloc_code_real_type relocs[3];
2950 } integer;
2951
2952 /* The binary data for an OT_FLOAT constant, and the number of bytes
2953 in the constant. */
2954 struct {
2955 unsigned char data[8];
2956 int length;
2957 } flt;
2958
14daeee3 2959 /* The character represented by an OT_CHAR or OT_DOUBLE_CHAR. */
a92713e6
RS
2960 char ch;
2961 } u;
2962};
2963
2964/* An obstack used to construct lists of mips_operand_tokens. */
2965static struct obstack mips_operand_tokens;
2966
2967/* Give TOKEN type TYPE and add it to mips_operand_tokens. */
2968
2969static void
2970mips_add_token (struct mips_operand_token *token,
2971 enum mips_operand_token_type type)
2972{
2973 token->type = type;
2974 obstack_grow (&mips_operand_tokens, token, sizeof (*token));
2975}
2976
2977/* Check whether S is '(' followed by a register name. Add OT_CHAR
2978 and OT_REG tokens for them if so, and return a pointer to the first
2979 unconsumed character. Return null otherwise. */
2980
2981static char *
2982mips_parse_base_start (char *s)
2983{
2984 struct mips_operand_token token;
14daeee3
RS
2985 unsigned int regno, channels;
2986 bfd_boolean decrement_p;
df58fc94 2987
a92713e6
RS
2988 if (*s != '(')
2989 return 0;
2990
2991 ++s;
2992 SKIP_SPACE_TABS (s);
14daeee3
RS
2993
2994 /* Only match "--" as part of a base expression. In other contexts "--X"
2995 is a double negative. */
2996 decrement_p = (s[0] == '-' && s[1] == '-');
2997 if (decrement_p)
2998 {
2999 s += 2;
3000 SKIP_SPACE_TABS (s);
3001 }
3002
3003 /* Allow a channel specifier because that leads to better error messages
3004 than treating something like "$vf0x++" as an expression. */
3005 if (!mips_parse_register (&s, &regno, &channels))
a92713e6
RS
3006 return 0;
3007
3008 token.u.ch = '(';
3009 mips_add_token (&token, OT_CHAR);
3010
14daeee3
RS
3011 if (decrement_p)
3012 {
3013 token.u.ch = '-';
3014 mips_add_token (&token, OT_DOUBLE_CHAR);
3015 }
3016
a92713e6
RS
3017 token.u.regno = regno;
3018 mips_add_token (&token, OT_REG);
3019
14daeee3
RS
3020 if (channels)
3021 {
3022 token.u.channels = channels;
3023 mips_add_token (&token, OT_CHANNELS);
3024 }
3025
3026 /* For consistency, only match "++" as part of base expressions too. */
3027 SKIP_SPACE_TABS (s);
3028 if (s[0] == '+' && s[1] == '+')
3029 {
3030 s += 2;
3031 token.u.ch = '+';
3032 mips_add_token (&token, OT_DOUBLE_CHAR);
3033 }
3034
a92713e6
RS
3035 return s;
3036}
3037
3038/* Parse one or more tokens from S. Return a pointer to the first
3039 unconsumed character on success. Return null if an error was found
3040 and store the error text in insn_error. FLOAT_FORMAT is as for
3041 mips_parse_arguments. */
3042
3043static char *
3044mips_parse_argument_token (char *s, char float_format)
3045{
3046 char *end, *save_in, *err;
14daeee3 3047 unsigned int regno1, regno2, channels;
a92713e6
RS
3048 struct mips_operand_token token;
3049
3050 /* First look for "($reg", since we want to treat that as an
3051 OT_CHAR and OT_REG rather than an expression. */
3052 end = mips_parse_base_start (s);
3053 if (end)
3054 return end;
3055
3056 /* Handle other characters that end up as OT_CHARs. */
3057 if (*s == ')' || *s == ',')
3058 {
3059 token.u.ch = *s;
3060 mips_add_token (&token, OT_CHAR);
3061 ++s;
3062 return s;
3063 }
3064
3065 /* Handle tokens that start with a register. */
14daeee3 3066 if (mips_parse_register (&s, &regno1, &channels))
df58fc94 3067 {
14daeee3
RS
3068 if (channels)
3069 {
3070 /* A register and a VU0 channel suffix. */
3071 token.u.regno = regno1;
3072 mips_add_token (&token, OT_REG);
3073
3074 token.u.channels = channels;
3075 mips_add_token (&token, OT_CHANNELS);
3076 return s;
3077 }
3078
a92713e6
RS
3079 SKIP_SPACE_TABS (s);
3080 if (*s == '-')
df58fc94 3081 {
a92713e6
RS
3082 /* A register range. */
3083 ++s;
3084 SKIP_SPACE_TABS (s);
14daeee3 3085 if (!mips_parse_register (&s, &regno2, NULL))
a92713e6 3086 {
1661c76c 3087 set_insn_error (0, _("invalid register range"));
a92713e6
RS
3088 return 0;
3089 }
df58fc94 3090
a92713e6
RS
3091 token.u.reg_range.regno1 = regno1;
3092 token.u.reg_range.regno2 = regno2;
3093 mips_add_token (&token, OT_REG_RANGE);
3094 return s;
3095 }
a92713e6 3096
56d438b1
CF
3097 /* Add the register itself. */
3098 token.u.regno = regno1;
3099 mips_add_token (&token, OT_REG);
3100
3101 /* Check for a vector index. */
3102 if (*s == '[')
3103 {
a92713e6
RS
3104 ++s;
3105 SKIP_SPACE_TABS (s);
56d438b1
CF
3106 if (mips_parse_register (&s, &token.u.regno, NULL))
3107 mips_add_token (&token, OT_REG_INDEX);
3108 else
a92713e6 3109 {
56d438b1
CF
3110 expressionS element;
3111
3112 my_getExpression (&element, s);
3113 if (element.X_op != O_constant)
3114 {
3115 set_insn_error (0, _("vector element must be constant"));
3116 return 0;
3117 }
3118 s = expr_end;
3119 token.u.index = element.X_add_number;
3120 mips_add_token (&token, OT_INTEGER_INDEX);
a92713e6 3121 }
a92713e6
RS
3122 SKIP_SPACE_TABS (s);
3123 if (*s != ']')
3124 {
1661c76c 3125 set_insn_error (0, _("missing `]'"));
a92713e6
RS
3126 return 0;
3127 }
3128 ++s;
df58fc94 3129 }
a92713e6 3130 return s;
df58fc94
RS
3131 }
3132
a92713e6
RS
3133 if (float_format)
3134 {
3135 /* First try to treat expressions as floats. */
3136 save_in = input_line_pointer;
3137 input_line_pointer = s;
3138 err = md_atof (float_format, (char *) token.u.flt.data,
3139 &token.u.flt.length);
3140 end = input_line_pointer;
3141 input_line_pointer = save_in;
3142 if (err && *err)
3143 {
e3de51ce 3144 set_insn_error (0, err);
a92713e6
RS
3145 return 0;
3146 }
3147 if (s != end)
3148 {
3149 mips_add_token (&token, OT_FLOAT);
3150 return end;
3151 }
3152 }
3153
3154 /* Treat everything else as an integer expression. */
3155 token.u.integer.relocs[0] = BFD_RELOC_UNUSED;
3156 token.u.integer.relocs[1] = BFD_RELOC_UNUSED;
3157 token.u.integer.relocs[2] = BFD_RELOC_UNUSED;
3158 my_getSmallExpression (&token.u.integer.value, token.u.integer.relocs, s);
3159 s = expr_end;
3160 mips_add_token (&token, OT_INTEGER);
3161 return s;
3162}
3163
3164/* S points to the operand list for an instruction. FLOAT_FORMAT is 'f'
3165 if expressions should be treated as 32-bit floating-point constants,
3166 'd' if they should be treated as 64-bit floating-point constants,
3167 or 0 if they should be treated as integer expressions (the usual case).
3168
3169 Return a list of tokens on success, otherwise return 0. The caller
3170 must obstack_free the list after use. */
3171
3172static struct mips_operand_token *
3173mips_parse_arguments (char *s, char float_format)
3174{
3175 struct mips_operand_token token;
3176
3177 SKIP_SPACE_TABS (s);
3178 while (*s)
3179 {
3180 s = mips_parse_argument_token (s, float_format);
3181 if (!s)
3182 {
3183 obstack_free (&mips_operand_tokens,
3184 obstack_finish (&mips_operand_tokens));
3185 return 0;
3186 }
3187 SKIP_SPACE_TABS (s);
3188 }
3189 mips_add_token (&token, OT_END);
3190 return (struct mips_operand_token *) obstack_finish (&mips_operand_tokens);
df58fc94
RS
3191}
3192
d301a56b
RS
3193/* Return TRUE if opcode MO is valid on the currently selected ISA, ASE
3194 and architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */
037b32b9
AN
3195
3196static bfd_boolean
f79e2745 3197is_opcode_valid (const struct mips_opcode *mo)
037b32b9
AN
3198{
3199 int isa = mips_opts.isa;
846ef2d0 3200 int ase = mips_opts.ase;
037b32b9 3201 int fp_s, fp_d;
c6278170 3202 unsigned int i;
037b32b9 3203
c6278170
RS
3204 if (ISA_HAS_64BIT_REGS (mips_opts.isa))
3205 for (i = 0; i < ARRAY_SIZE (mips_ases); i++)
3206 if ((ase & mips_ases[i].flags) == mips_ases[i].flags)
3207 ase |= mips_ases[i].flags64;
037b32b9 3208
d301a56b 3209 if (!opcode_is_member (mo, isa, ase, mips_opts.arch))
037b32b9
AN
3210 return FALSE;
3211
3212 /* Check whether the instruction or macro requires single-precision or
3213 double-precision floating-point support. Note that this information is
3214 stored differently in the opcode table for insns and macros. */
3215 if (mo->pinfo == INSN_MACRO)
3216 {
3217 fp_s = mo->pinfo2 & INSN2_M_FP_S;
3218 fp_d = mo->pinfo2 & INSN2_M_FP_D;
3219 }
3220 else
3221 {
3222 fp_s = mo->pinfo & FP_S;
3223 fp_d = mo->pinfo & FP_D;
3224 }
3225
3226 if (fp_d && (mips_opts.soft_float || mips_opts.single_float))
3227 return FALSE;
3228
3229 if (fp_s && mips_opts.soft_float)
3230 return FALSE;
3231
3232 return TRUE;
3233}
3234
3235/* Return TRUE if the MIPS16 opcode MO is valid on the currently
3236 selected ISA and architecture. */
3237
3238static bfd_boolean
3239is_opcode_valid_16 (const struct mips_opcode *mo)
3240{
d301a56b 3241 return opcode_is_member (mo, mips_opts.isa, 0, mips_opts.arch);
037b32b9
AN
3242}
3243
df58fc94
RS
3244/* Return TRUE if the size of the microMIPS opcode MO matches one
3245 explicitly requested. Always TRUE in the standard MIPS mode. */
3246
3247static bfd_boolean
3248is_size_valid (const struct mips_opcode *mo)
3249{
3250 if (!mips_opts.micromips)
3251 return TRUE;
3252
833794fc
MR
3253 if (mips_opts.insn32)
3254 {
3255 if (mo->pinfo != INSN_MACRO && micromips_insn_length (mo) != 4)
3256 return FALSE;
3257 if ((mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0)
3258 return FALSE;
3259 }
df58fc94
RS
3260 if (!forced_insn_length)
3261 return TRUE;
3262 if (mo->pinfo == INSN_MACRO)
3263 return FALSE;
3264 return forced_insn_length == micromips_insn_length (mo);
3265}
3266
3267/* Return TRUE if the microMIPS opcode MO is valid for the delay slot
e64af278
MR
3268 of the preceding instruction. Always TRUE in the standard MIPS mode.
3269
3270 We don't accept macros in 16-bit delay slots to avoid a case where
3271 a macro expansion fails because it relies on a preceding 32-bit real
3272 instruction to have matched and does not handle the operands correctly.
3273 The only macros that may expand to 16-bit instructions are JAL that
3274 cannot be placed in a delay slot anyway, and corner cases of BALIGN
3275 and BGT (that likewise cannot be placed in a delay slot) that decay to
3276 a NOP. In all these cases the macros precede any corresponding real
3277 instruction definitions in the opcode table, so they will match in the
3278 second pass where the size of the delay slot is ignored and therefore
3279 produce correct code. */
df58fc94
RS
3280
3281static bfd_boolean
3282is_delay_slot_valid (const struct mips_opcode *mo)
3283{
3284 if (!mips_opts.micromips)
3285 return TRUE;
3286
3287 if (mo->pinfo == INSN_MACRO)
c06dec14 3288 return (history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) == 0;
df58fc94
RS
3289 if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0
3290 && micromips_insn_length (mo) != 4)
3291 return FALSE;
3292 if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0
3293 && micromips_insn_length (mo) != 2)
3294 return FALSE;
3295
3296 return TRUE;
3297}
3298
fc76e730
RS
3299/* For consistency checking, verify that all bits of OPCODE are specified
3300 either by the match/mask part of the instruction definition, or by the
3301 operand list. Also build up a list of operands in OPERANDS.
3302
3303 INSN_BITS says which bits of the instruction are significant.
3304 If OPCODE is a standard or microMIPS instruction, DECODE_OPERAND
3305 provides the mips_operand description of each operand. DECODE_OPERAND
3306 is null for MIPS16 instructions. */
ab902481
RS
3307
3308static int
3309validate_mips_insn (const struct mips_opcode *opcode,
3310 unsigned long insn_bits,
fc76e730
RS
3311 const struct mips_operand *(*decode_operand) (const char *),
3312 struct mips_operand_array *operands)
ab902481
RS
3313{
3314 const char *s;
fc76e730 3315 unsigned long used_bits, doubled, undefined, opno, mask;
ab902481
RS
3316 const struct mips_operand *operand;
3317
fc76e730
RS
3318 mask = (opcode->pinfo == INSN_MACRO ? 0 : opcode->mask);
3319 if ((mask & opcode->match) != opcode->match)
ab902481
RS
3320 {
3321 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
3322 opcode->name, opcode->args);
3323 return 0;
3324 }
3325 used_bits = 0;
fc76e730 3326 opno = 0;
14daeee3
RS
3327 if (opcode->pinfo2 & INSN2_VU0_CHANNEL_SUFFIX)
3328 used_bits = mips_insert_operand (&mips_vu0_channel_mask, used_bits, -1);
ab902481
RS
3329 for (s = opcode->args; *s; ++s)
3330 switch (*s)
3331 {
3332 case ',':
3333 case '(':
3334 case ')':
3335 break;
3336
14daeee3
RS
3337 case '#':
3338 s++;
3339 break;
3340
ab902481 3341 default:
fc76e730
RS
3342 if (!decode_operand)
3343 operand = decode_mips16_operand (*s, FALSE);
3344 else
3345 operand = decode_operand (s);
3346 if (!operand && opcode->pinfo != INSN_MACRO)
ab902481
RS
3347 {
3348 as_bad (_("internal: unknown operand type: %s %s"),
3349 opcode->name, opcode->args);
3350 return 0;
3351 }
fc76e730
RS
3352 gas_assert (opno < MAX_OPERANDS);
3353 operands->operand[opno] = operand;
14daeee3 3354 if (operand && operand->type != OP_VU0_MATCH_SUFFIX)
fc76e730 3355 {
14daeee3 3356 used_bits = mips_insert_operand (operand, used_bits, -1);
fc76e730
RS
3357 if (operand->type == OP_MDMX_IMM_REG)
3358 /* Bit 5 is the format selector (OB vs QH). The opcode table
3359 has separate entries for each format. */
3360 used_bits &= ~(1 << (operand->lsb + 5));
3361 if (operand->type == OP_ENTRY_EXIT_LIST)
3362 used_bits &= ~(mask & 0x700);
3363 }
ab902481 3364 /* Skip prefix characters. */
7361da2c 3365 if (decode_operand && (*s == '+' || *s == 'm' || *s == '-'))
ab902481 3366 ++s;
fc76e730 3367 opno += 1;
ab902481
RS
3368 break;
3369 }
fc76e730 3370 doubled = used_bits & mask & insn_bits;
ab902481
RS
3371 if (doubled)
3372 {
3373 as_bad (_("internal: bad mips opcode (bits 0x%08lx doubly defined):"
3374 " %s %s"), doubled, opcode->name, opcode->args);
3375 return 0;
3376 }
fc76e730 3377 used_bits |= mask;
ab902481 3378 undefined = ~used_bits & insn_bits;
fc76e730 3379 if (opcode->pinfo != INSN_MACRO && undefined)
ab902481
RS
3380 {
3381 as_bad (_("internal: bad mips opcode (bits 0x%08lx undefined): %s %s"),
3382 undefined, opcode->name, opcode->args);
3383 return 0;
3384 }
3385 used_bits &= ~insn_bits;
3386 if (used_bits)
3387 {
3388 as_bad (_("internal: bad mips opcode (bits 0x%08lx defined): %s %s"),
3389 used_bits, opcode->name, opcode->args);
3390 return 0;
3391 }
3392 return 1;
3393}
3394
fc76e730
RS
3395/* The MIPS16 version of validate_mips_insn. */
3396
3397static int
3398validate_mips16_insn (const struct mips_opcode *opcode,
3399 struct mips_operand_array *operands)
3400{
3401 if (opcode->args[0] == 'a' || opcode->args[0] == 'i')
3402 {
3403 /* In this case OPCODE defines the first 16 bits in a 32-bit jump
3404 instruction. Use TMP to describe the full instruction. */
3405 struct mips_opcode tmp;
3406
3407 tmp = *opcode;
3408 tmp.match <<= 16;
3409 tmp.mask <<= 16;
3410 return validate_mips_insn (&tmp, 0xffffffff, 0, operands);
3411 }
3412 return validate_mips_insn (opcode, 0xffff, 0, operands);
3413}
3414
ab902481
RS
3415/* The microMIPS version of validate_mips_insn. */
3416
3417static int
fc76e730
RS
3418validate_micromips_insn (const struct mips_opcode *opc,
3419 struct mips_operand_array *operands)
ab902481
RS
3420{
3421 unsigned long insn_bits;
3422 unsigned long major;
3423 unsigned int length;
3424
fc76e730
RS
3425 if (opc->pinfo == INSN_MACRO)
3426 return validate_mips_insn (opc, 0xffffffff, decode_micromips_operand,
3427 operands);
3428
ab902481
RS
3429 length = micromips_insn_length (opc);
3430 if (length != 2 && length != 4)
3431 {
1661c76c 3432 as_bad (_("internal error: bad microMIPS opcode (incorrect length: %u): "
ab902481
RS
3433 "%s %s"), length, opc->name, opc->args);
3434 return 0;
3435 }
3436 major = opc->match >> (10 + 8 * (length - 2));
3437 if ((length == 2 && (major & 7) != 1 && (major & 6) != 2)
3438 || (length == 4 && (major & 7) != 0 && (major & 4) != 4))
3439 {
1661c76c 3440 as_bad (_("internal error: bad microMIPS opcode "
ab902481
RS
3441 "(opcode/length mismatch): %s %s"), opc->name, opc->args);
3442 return 0;
3443 }
3444
3445 /* Shift piecewise to avoid an overflow where unsigned long is 32-bit. */
3446 insn_bits = 1 << 4 * length;
3447 insn_bits <<= 4 * length;
3448 insn_bits -= 1;
fc76e730
RS
3449 return validate_mips_insn (opc, insn_bits, decode_micromips_operand,
3450 operands);
ab902481
RS
3451}
3452
707bfff6
TS
3453/* This function is called once, at assembler startup time. It should set up
3454 all the tables, etc. that the MD part of the assembler will need. */
156c2f8b 3455
252b5132 3456void
17a2f251 3457md_begin (void)
252b5132 3458{
3994f87e 3459 const char *retval = NULL;
156c2f8b 3460 int i = 0;
252b5132 3461 int broken = 0;
1f25f5d3 3462
0a44bf69
RS
3463 if (mips_pic != NO_PIC)
3464 {
3465 if (g_switch_seen && g_switch_value != 0)
3466 as_bad (_("-G may not be used in position-independent code"));
3467 g_switch_value = 0;
3468 }
3469
0b35dfee 3470 if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_opts.arch))
1661c76c 3471 as_warn (_("could not set architecture and machine"));
252b5132 3472
252b5132
RH
3473 op_hash = hash_new ();
3474
fc76e730 3475 mips_operands = XCNEWVEC (struct mips_operand_array, NUMOPCODES);
252b5132
RH
3476 for (i = 0; i < NUMOPCODES;)
3477 {
3478 const char *name = mips_opcodes[i].name;
3479
17a2f251 3480 retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]);
252b5132
RH
3481 if (retval != NULL)
3482 {
3483 fprintf (stderr, _("internal error: can't hash `%s': %s\n"),
3484 mips_opcodes[i].name, retval);
3485 /* Probably a memory allocation problem? Give up now. */
1661c76c 3486 as_fatal (_("broken assembler, no assembly attempted"));
252b5132
RH
3487 }
3488 do
3489 {
fc76e730
RS
3490 if (!validate_mips_insn (&mips_opcodes[i], 0xffffffff,
3491 decode_mips_operand, &mips_operands[i]))
3492 broken = 1;
3493 if (nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0)
252b5132 3494 {
fc76e730
RS
3495 create_insn (&nop_insn, mips_opcodes + i);
3496 if (mips_fix_loongson2f_nop)
3497 nop_insn.insn_opcode = LOONGSON2F_NOP_INSN;
3498 nop_insn.fixed_p = 1;
252b5132
RH
3499 }
3500 ++i;
3501 }
3502 while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name));
3503 }
3504
3505 mips16_op_hash = hash_new ();
fc76e730
RS
3506 mips16_operands = XCNEWVEC (struct mips_operand_array,
3507 bfd_mips16_num_opcodes);
252b5132
RH
3508
3509 i = 0;
3510 while (i < bfd_mips16_num_opcodes)
3511 {
3512 const char *name = mips16_opcodes[i].name;
3513
17a2f251 3514 retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]);
252b5132
RH
3515 if (retval != NULL)
3516 as_fatal (_("internal: can't hash `%s': %s"),
3517 mips16_opcodes[i].name, retval);
3518 do
3519 {
fc76e730
RS
3520 if (!validate_mips16_insn (&mips16_opcodes[i], &mips16_operands[i]))
3521 broken = 1;
1e915849
RS
3522 if (mips16_nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0)
3523 {
3524 create_insn (&mips16_nop_insn, mips16_opcodes + i);
3525 mips16_nop_insn.fixed_p = 1;
3526 }
252b5132
RH
3527 ++i;
3528 }
3529 while (i < bfd_mips16_num_opcodes
3530 && strcmp (mips16_opcodes[i].name, name) == 0);
3531 }
3532
df58fc94 3533 micromips_op_hash = hash_new ();
fc76e730
RS
3534 micromips_operands = XCNEWVEC (struct mips_operand_array,
3535 bfd_micromips_num_opcodes);
df58fc94
RS
3536
3537 i = 0;
3538 while (i < bfd_micromips_num_opcodes)
3539 {
3540 const char *name = micromips_opcodes[i].name;
3541
3542 retval = hash_insert (micromips_op_hash, name,
3543 (void *) &micromips_opcodes[i]);
3544 if (retval != NULL)
3545 as_fatal (_("internal: can't hash `%s': %s"),
3546 micromips_opcodes[i].name, retval);
3547 do
fc76e730
RS
3548 {
3549 struct mips_cl_insn *micromips_nop_insn;
3550
3551 if (!validate_micromips_insn (&micromips_opcodes[i],
3552 &micromips_operands[i]))
3553 broken = 1;
3554
3555 if (micromips_opcodes[i].pinfo != INSN_MACRO)
3556 {
3557 if (micromips_insn_length (micromips_opcodes + i) == 2)
3558 micromips_nop_insn = &micromips_nop16_insn;
3559 else if (micromips_insn_length (micromips_opcodes + i) == 4)
3560 micromips_nop_insn = &micromips_nop32_insn;
3561 else
3562 continue;
3563
3564 if (micromips_nop_insn->insn_mo == NULL
3565 && strcmp (name, "nop") == 0)
3566 {
3567 create_insn (micromips_nop_insn, micromips_opcodes + i);
3568 micromips_nop_insn->fixed_p = 1;
3569 }
3570 }
3571 }
df58fc94
RS
3572 while (++i < bfd_micromips_num_opcodes
3573 && strcmp (micromips_opcodes[i].name, name) == 0);
3574 }
3575
252b5132 3576 if (broken)
1661c76c 3577 as_fatal (_("broken assembler, no assembly attempted"));
252b5132
RH
3578
3579 /* We add all the general register names to the symbol table. This
3580 helps us detect invalid uses of them. */
707bfff6
TS
3581 for (i = 0; reg_names[i].name; i++)
3582 symbol_table_insert (symbol_new (reg_names[i].name, reg_section,
8fc4ee9b 3583 reg_names[i].num, /* & RNUM_MASK, */
707bfff6
TS
3584 &zero_address_frag));
3585 if (HAVE_NEWABI)
3586 for (i = 0; reg_names_n32n64[i].name; i++)
3587 symbol_table_insert (symbol_new (reg_names_n32n64[i].name, reg_section,
8fc4ee9b 3588 reg_names_n32n64[i].num, /* & RNUM_MASK, */
252b5132 3589 &zero_address_frag));
707bfff6
TS
3590 else
3591 for (i = 0; reg_names_o32[i].name; i++)
3592 symbol_table_insert (symbol_new (reg_names_o32[i].name, reg_section,
8fc4ee9b 3593 reg_names_o32[i].num, /* & RNUM_MASK, */
6047c971 3594 &zero_address_frag));
6047c971 3595
14daeee3
RS
3596 for (i = 0; i < 32; i++)
3597 {
3598 char regname[7];
3599
3600 /* R5900 VU0 floating-point register. */
3601 regname[sizeof (rename) - 1] = 0;
3602 snprintf (regname, sizeof (regname) - 1, "$vf%d", i);
3603 symbol_table_insert (symbol_new (regname, reg_section,
3604 RTYPE_VF | i, &zero_address_frag));
3605
3606 /* R5900 VU0 integer register. */
3607 snprintf (regname, sizeof (regname) - 1, "$vi%d", i);
3608 symbol_table_insert (symbol_new (regname, reg_section,
3609 RTYPE_VI | i, &zero_address_frag));
3610
56d438b1
CF
3611 /* MSA register. */
3612 snprintf (regname, sizeof (regname) - 1, "$w%d", i);
3613 symbol_table_insert (symbol_new (regname, reg_section,
3614 RTYPE_MSA | i, &zero_address_frag));
14daeee3
RS
3615 }
3616
a92713e6
RS
3617 obstack_init (&mips_operand_tokens);
3618
7d10b47d 3619 mips_no_prev_insn ();
252b5132
RH
3620
3621 mips_gprmask = 0;
3622 mips_cprmask[0] = 0;
3623 mips_cprmask[1] = 0;
3624 mips_cprmask[2] = 0;
3625 mips_cprmask[3] = 0;
3626
3627 /* set the default alignment for the text section (2**2) */
3628 record_alignment (text_section, 2);
3629
4d0d148d 3630 bfd_set_gp_size (stdoutput, g_switch_value);
252b5132 3631
f3ded42a
RS
3632 /* On a native system other than VxWorks, sections must be aligned
3633 to 16 byte boundaries. When configured for an embedded ELF
3634 target, we don't bother. */
3635 if (strncmp (TARGET_OS, "elf", 3) != 0
3636 && strncmp (TARGET_OS, "vxworks", 7) != 0)
252b5132 3637 {
f3ded42a
RS
3638 (void) bfd_set_section_alignment (stdoutput, text_section, 4);
3639 (void) bfd_set_section_alignment (stdoutput, data_section, 4);
3640 (void) bfd_set_section_alignment (stdoutput, bss_section, 4);
3641 }
252b5132 3642
f3ded42a
RS
3643 /* Create a .reginfo section for register masks and a .mdebug
3644 section for debugging information. */
3645 {
3646 segT seg;
3647 subsegT subseg;
3648 flagword flags;
3649 segT sec;
3650
3651 seg = now_seg;
3652 subseg = now_subseg;
3653
3654 /* The ABI says this section should be loaded so that the
3655 running program can access it. However, we don't load it
3656 if we are configured for an embedded target */
3657 flags = SEC_READONLY | SEC_DATA;
3658 if (strncmp (TARGET_OS, "elf", 3) != 0)
3659 flags |= SEC_ALLOC | SEC_LOAD;
3660
3661 if (mips_abi != N64_ABI)
252b5132 3662 {
f3ded42a 3663 sec = subseg_new (".reginfo", (subsegT) 0);
bdaaa2e1 3664
f3ded42a
RS
3665 bfd_set_section_flags (stdoutput, sec, flags);
3666 bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2);
252b5132 3667
f3ded42a
RS
3668 mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo));
3669 }
3670 else
3671 {
3672 /* The 64-bit ABI uses a .MIPS.options section rather than
3673 .reginfo section. */
3674 sec = subseg_new (".MIPS.options", (subsegT) 0);
3675 bfd_set_section_flags (stdoutput, sec, flags);
3676 bfd_set_section_alignment (stdoutput, sec, 3);
252b5132 3677
f3ded42a
RS
3678 /* Set up the option header. */
3679 {
3680 Elf_Internal_Options opthdr;
3681 char *f;
3682
3683 opthdr.kind = ODK_REGINFO;
3684 opthdr.size = (sizeof (Elf_External_Options)
3685 + sizeof (Elf64_External_RegInfo));
3686 opthdr.section = 0;
3687 opthdr.info = 0;
3688 f = frag_more (sizeof (Elf_External_Options));
3689 bfd_mips_elf_swap_options_out (stdoutput, &opthdr,
3690 (Elf_External_Options *) f);
3691
3692 mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo));
3693 }
3694 }
252b5132 3695
351cdf24
MF
3696 sec = subseg_new (".MIPS.abiflags", (subsegT) 0);
3697 bfd_set_section_flags (stdoutput, sec,
3698 SEC_READONLY | SEC_DATA | SEC_ALLOC | SEC_LOAD);
3699 bfd_set_section_alignment (stdoutput, sec, 3);
3700 mips_flags_frag = frag_more (sizeof (Elf_External_ABIFlags_v0));
3701
f3ded42a
RS
3702 if (ECOFF_DEBUGGING)
3703 {
3704 sec = subseg_new (".mdebug", (subsegT) 0);
3705 (void) bfd_set_section_flags (stdoutput, sec,
3706 SEC_HAS_CONTENTS | SEC_READONLY);
3707 (void) bfd_set_section_alignment (stdoutput, sec, 2);
252b5132 3708 }
f3ded42a
RS
3709 else if (mips_flag_pdr)
3710 {
3711 pdr_seg = subseg_new (".pdr", (subsegT) 0);
3712 (void) bfd_set_section_flags (stdoutput, pdr_seg,
3713 SEC_READONLY | SEC_RELOC
3714 | SEC_DEBUGGING);
3715 (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2);
3716 }
3717
3718 subseg_set (seg, subseg);
3719 }
252b5132 3720
71400594
RS
3721 if (mips_fix_vr4120)
3722 init_vr4120_conflicts ();
252b5132
RH
3723}
3724
351cdf24
MF
3725static inline void
3726fpabi_incompatible_with (int fpabi, const char *what)
3727{
3728 as_warn (_(".gnu_attribute %d,%d is incompatible with `%s'"),
3729 Tag_GNU_MIPS_ABI_FP, fpabi, what);
3730}
3731
3732static inline void
3733fpabi_requires (int fpabi, const char *what)
3734{
3735 as_warn (_(".gnu_attribute %d,%d requires `%s'"),
3736 Tag_GNU_MIPS_ABI_FP, fpabi, what);
3737}
3738
3739/* Check -mabi and register sizes against the specified FP ABI. */
3740static void
3741check_fpabi (int fpabi)
3742{
351cdf24
MF
3743 switch (fpabi)
3744 {
3745 case Val_GNU_MIPS_ABI_FP_DOUBLE:
ea79f94a
MF
3746 if (file_mips_opts.soft_float)
3747 fpabi_incompatible_with (fpabi, "softfloat");
3748 else if (file_mips_opts.single_float)
3749 fpabi_incompatible_with (fpabi, "singlefloat");
351cdf24
MF
3750 if (file_mips_opts.gp == 64 && file_mips_opts.fp == 32)
3751 fpabi_incompatible_with (fpabi, "gp=64 fp=32");
3752 else if (file_mips_opts.gp == 32 && file_mips_opts.fp == 64)
3753 fpabi_incompatible_with (fpabi, "gp=32 fp=64");
351cdf24
MF
3754 break;
3755
3756 case Val_GNU_MIPS_ABI_FP_XX:
3757 if (mips_abi != O32_ABI)
3758 fpabi_requires (fpabi, "-mabi=32");
ea79f94a
MF
3759 else if (file_mips_opts.soft_float)
3760 fpabi_incompatible_with (fpabi, "softfloat");
3761 else if (file_mips_opts.single_float)
3762 fpabi_incompatible_with (fpabi, "singlefloat");
351cdf24
MF
3763 else if (file_mips_opts.fp != 0)
3764 fpabi_requires (fpabi, "fp=xx");
351cdf24
MF
3765 break;
3766
3767 case Val_GNU_MIPS_ABI_FP_64A:
3768 case Val_GNU_MIPS_ABI_FP_64:
3769 if (mips_abi != O32_ABI)
3770 fpabi_requires (fpabi, "-mabi=32");
ea79f94a
MF
3771 else if (file_mips_opts.soft_float)
3772 fpabi_incompatible_with (fpabi, "softfloat");
3773 else if (file_mips_opts.single_float)
3774 fpabi_incompatible_with (fpabi, "singlefloat");
351cdf24
MF
3775 else if (file_mips_opts.fp != 64)
3776 fpabi_requires (fpabi, "fp=64");
3777 else if (fpabi == Val_GNU_MIPS_ABI_FP_64 && !file_mips_opts.oddspreg)
3778 fpabi_incompatible_with (fpabi, "nooddspreg");
3779 else if (fpabi == Val_GNU_MIPS_ABI_FP_64A && file_mips_opts.oddspreg)
3780 fpabi_requires (fpabi, "nooddspreg");
351cdf24
MF
3781 break;
3782
3783 case Val_GNU_MIPS_ABI_FP_SINGLE:
3784 if (file_mips_opts.soft_float)
3785 fpabi_incompatible_with (fpabi, "softfloat");
3786 else if (!file_mips_opts.single_float)
3787 fpabi_requires (fpabi, "singlefloat");
3788 break;
3789
3790 case Val_GNU_MIPS_ABI_FP_SOFT:
3791 if (!file_mips_opts.soft_float)
3792 fpabi_requires (fpabi, "softfloat");
3793 break;
3794
3795 case Val_GNU_MIPS_ABI_FP_OLD_64:
3796 as_warn (_(".gnu_attribute %d,%d is no longer supported"),
3797 Tag_GNU_MIPS_ABI_FP, fpabi);
3798 break;
3799
3800 default:
3801 as_warn (_(".gnu_attribute %d,%d is not a recognized"
3802 " floating-point ABI"), Tag_GNU_MIPS_ABI_FP, fpabi);
3803 break;
3804 }
351cdf24
MF
3805}
3806
919731af 3807/* Perform consistency checks on the current options. */
3808
3809static void
3810mips_check_options (struct mips_set_options *opts, bfd_boolean abi_checks)
3811{
3812 /* Check the size of integer registers agrees with the ABI and ISA. */
3813 if (opts->gp == 64 && !ISA_HAS_64BIT_REGS (opts->isa))
3814 as_bad (_("`gp=64' used with a 32-bit processor"));
3815 else if (abi_checks
3816 && opts->gp == 32 && ABI_NEEDS_64BIT_REGS (mips_abi))
3817 as_bad (_("`gp=32' used with a 64-bit ABI"));
3818 else if (abi_checks
3819 && opts->gp == 64 && ABI_NEEDS_32BIT_REGS (mips_abi))
3820 as_bad (_("`gp=64' used with a 32-bit ABI"));
3821
3822 /* Check the size of the float registers agrees with the ABI and ISA. */
3823 switch (opts->fp)
3824 {
351cdf24
MF
3825 case 0:
3826 if (!CPU_HAS_LDC1_SDC1 (opts->arch))
3827 as_bad (_("`fp=xx' used with a cpu lacking ldc1/sdc1 instructions"));
3828 else if (opts->single_float == 1)
3829 as_bad (_("`fp=xx' cannot be used with `singlefloat'"));
3830 break;
919731af 3831 case 64:
3832 if (!ISA_HAS_64BIT_FPRS (opts->isa))
3833 as_bad (_("`fp=64' used with a 32-bit fpu"));
3834 else if (abi_checks
3835 && ABI_NEEDS_32BIT_REGS (mips_abi)
3836 && !ISA_HAS_MXHC1 (opts->isa))
3837 as_warn (_("`fp=64' used with a 32-bit ABI"));
3838 break;
3839 case 32:
3840 if (abi_checks
3841 && ABI_NEEDS_64BIT_REGS (mips_abi))
3842 as_warn (_("`fp=32' used with a 64-bit ABI"));
7361da2c
AB
3843 if (ISA_IS_R6 (mips_opts.isa) && opts->single_float == 0)
3844 as_bad (_("`fp=32' used with a MIPS R6 cpu"));
919731af 3845 break;
3846 default:
3847 as_bad (_("Unknown size of floating point registers"));
3848 break;
3849 }
3850
351cdf24
MF
3851 if (ABI_NEEDS_64BIT_REGS (mips_abi) && !opts->oddspreg)
3852 as_bad (_("`nooddspreg` cannot be used with a 64-bit ABI"));
3853
919731af 3854 if (opts->micromips == 1 && opts->mips16 == 1)
3855 as_bad (_("`mips16' cannot be used with `micromips'"));
7361da2c
AB
3856 else if (ISA_IS_R6 (mips_opts.isa)
3857 && (opts->micromips == 1
3858 || opts->mips16 == 1))
3859 as_fatal (_("`%s' can not be used with `%s'"),
3860 opts->micromips ? "micromips" : "mips16",
3861 mips_cpu_info_from_isa (mips_opts.isa)->name);
3862
3863 if (ISA_IS_R6 (opts->isa) && mips_relax_branch)
3864 as_fatal (_("branch relaxation is not supported in `%s'"),
3865 mips_cpu_info_from_isa (opts->isa)->name);
919731af 3866}
3867
3868/* Perform consistency checks on the module level options exactly once.
3869 This is a deferred check that happens:
3870 at the first .set directive
3871 or, at the first pseudo op that generates code (inc .dc.a)
3872 or, at the first instruction
3873 or, at the end. */
3874
3875static void
3876file_mips_check_options (void)
3877{
3878 const struct mips_cpu_info *arch_info = 0;
3879
3880 if (file_mips_opts_checked)
3881 return;
3882
3883 /* The following code determines the register size.
3884 Similar code was added to GCC 3.3 (see override_options() in
3885 config/mips/mips.c). The GAS and GCC code should be kept in sync
3886 as much as possible. */
3887
3888 if (file_mips_opts.gp < 0)
3889 {
3890 /* Infer the integer register size from the ABI and processor.
3891 Restrict ourselves to 32-bit registers if that's all the
3892 processor has, or if the ABI cannot handle 64-bit registers. */
3893 file_mips_opts.gp = (ABI_NEEDS_32BIT_REGS (mips_abi)
3894 || !ISA_HAS_64BIT_REGS (file_mips_opts.isa))
3895 ? 32 : 64;
3896 }
3897
3898 if (file_mips_opts.fp < 0)
3899 {
3900 /* No user specified float register size.
3901 ??? GAS treats single-float processors as though they had 64-bit
3902 float registers (although it complains when double-precision
3903 instructions are used). As things stand, saying they have 32-bit
3904 registers would lead to spurious "register must be even" messages.
3905 So here we assume float registers are never smaller than the
3906 integer ones. */
3907 if (file_mips_opts.gp == 64)
3908 /* 64-bit integer registers implies 64-bit float registers. */
3909 file_mips_opts.fp = 64;
3910 else if ((file_mips_opts.ase & FP64_ASES)
3911 && ISA_HAS_64BIT_FPRS (file_mips_opts.isa))
3912 /* Handle ASEs that require 64-bit float registers, if possible. */
3913 file_mips_opts.fp = 64;
7361da2c
AB
3914 else if (ISA_IS_R6 (mips_opts.isa))
3915 /* R6 implies 64-bit float registers. */
3916 file_mips_opts.fp = 64;
919731af 3917 else
3918 /* 32-bit float registers. */
3919 file_mips_opts.fp = 32;
3920 }
3921
3922 arch_info = mips_cpu_info_from_arch (file_mips_opts.arch);
3923
351cdf24
MF
3924 /* Disable operations on odd-numbered floating-point registers by default
3925 when using the FPXX ABI. */
3926 if (file_mips_opts.oddspreg < 0)
3927 {
3928 if (file_mips_opts.fp == 0)
3929 file_mips_opts.oddspreg = 0;
3930 else
3931 file_mips_opts.oddspreg = 1;
3932 }
3933
919731af 3934 /* End of GCC-shared inference code. */
3935
3936 /* This flag is set when we have a 64-bit capable CPU but use only
3937 32-bit wide registers. Note that EABI does not use it. */
3938 if (ISA_HAS_64BIT_REGS (file_mips_opts.isa)
3939 && ((mips_abi == NO_ABI && file_mips_opts.gp == 32)
3940 || mips_abi == O32_ABI))
3941 mips_32bitmode = 1;
3942
3943 if (file_mips_opts.isa == ISA_MIPS1 && mips_trap)
3944 as_bad (_("trap exception not supported at ISA 1"));
3945
3946 /* If the selected architecture includes support for ASEs, enable
3947 generation of code for them. */
3948 if (file_mips_opts.mips16 == -1)
3949 file_mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_opts.arch)) ? 1 : 0;
3950 if (file_mips_opts.micromips == -1)
3951 file_mips_opts.micromips = (CPU_HAS_MICROMIPS (file_mips_opts.arch))
3952 ? 1 : 0;
3953
7361da2c
AB
3954 if (mips_nan2008 == -1)
3955 mips_nan2008 = (ISA_HAS_LEGACY_NAN (file_mips_opts.isa)) ? 0 : 1;
3956 else if (!ISA_HAS_LEGACY_NAN (file_mips_opts.isa) && mips_nan2008 == 0)
3957 as_fatal (_("`%s' does not support legacy NaN"),
3958 mips_cpu_info_from_arch (file_mips_opts.arch)->name);
3959
919731af 3960 /* Some ASEs require 64-bit FPRs, so -mfp32 should stop those ASEs from
3961 being selected implicitly. */
3962 if (file_mips_opts.fp != 64)
3963 file_ase_explicit |= ASE_MIPS3D | ASE_MDMX | ASE_MSA;
3964
3965 /* If the user didn't explicitly select or deselect a particular ASE,
3966 use the default setting for the CPU. */
3967 file_mips_opts.ase |= (arch_info->ase & ~file_ase_explicit);
3968
3969 /* Set up the current options. These may change throughout assembly. */
3970 mips_opts = file_mips_opts;
3971
3972 mips_check_isa_supports_ases ();
3973 mips_check_options (&file_mips_opts, TRUE);
3974 file_mips_opts_checked = TRUE;
3975
3976 if (!bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_opts.arch))
3977 as_warn (_("could not set architecture and machine"));
3978}
3979
252b5132 3980void
17a2f251 3981md_assemble (char *str)
252b5132
RH
3982{
3983 struct mips_cl_insn insn;
f6688943
TS
3984 bfd_reloc_code_real_type unused_reloc[3]
3985 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
252b5132 3986
919731af 3987 file_mips_check_options ();
3988
252b5132 3989 imm_expr.X_op = O_absent;
252b5132 3990 offset_expr.X_op = O_absent;
f6688943
TS
3991 offset_reloc[0] = BFD_RELOC_UNUSED;
3992 offset_reloc[1] = BFD_RELOC_UNUSED;
3993 offset_reloc[2] = BFD_RELOC_UNUSED;
252b5132 3994
e1b47bd5
RS
3995 mips_mark_labels ();
3996 mips_assembling_insn = TRUE;
e3de51ce 3997 clear_insn_error ();
e1b47bd5 3998
252b5132
RH
3999 if (mips_opts.mips16)
4000 mips16_ip (str, &insn);
4001 else
4002 {
4003 mips_ip (str, &insn);
beae10d5
KH
4004 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
4005 str, insn.insn_opcode));
252b5132
RH
4006 }
4007
e3de51ce
RS
4008 if (insn_error.msg)
4009 report_insn_error (str);
e1b47bd5 4010 else if (insn.insn_mo->pinfo == INSN_MACRO)
252b5132 4011 {
584892a6 4012 macro_start ();
252b5132
RH
4013 if (mips_opts.mips16)
4014 mips16_macro (&insn);
4015 else
833794fc 4016 macro (&insn, str);
584892a6 4017 macro_end ();
252b5132
RH
4018 }
4019 else
4020 {
77bd4346 4021 if (offset_expr.X_op != O_absent)
df58fc94 4022 append_insn (&insn, &offset_expr, offset_reloc, FALSE);
252b5132 4023 else
df58fc94 4024 append_insn (&insn, NULL, unused_reloc, FALSE);
252b5132 4025 }
e1b47bd5
RS
4026
4027 mips_assembling_insn = FALSE;
252b5132
RH
4028}
4029
738e5348
RS
4030/* Convenience functions for abstracting away the differences between
4031 MIPS16 and non-MIPS16 relocations. */
4032
4033static inline bfd_boolean
4034mips16_reloc_p (bfd_reloc_code_real_type reloc)
4035{
4036 switch (reloc)
4037 {
4038 case BFD_RELOC_MIPS16_JMP:
4039 case BFD_RELOC_MIPS16_GPREL:
4040 case BFD_RELOC_MIPS16_GOT16:
4041 case BFD_RELOC_MIPS16_CALL16:
4042 case BFD_RELOC_MIPS16_HI16_S:
4043 case BFD_RELOC_MIPS16_HI16:
4044 case BFD_RELOC_MIPS16_LO16:
4045 return TRUE;
4046
4047 default:
4048 return FALSE;
4049 }
4050}
4051
df58fc94
RS
4052static inline bfd_boolean
4053micromips_reloc_p (bfd_reloc_code_real_type reloc)
4054{
4055 switch (reloc)
4056 {
4057 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
4058 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
4059 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
4060 case BFD_RELOC_MICROMIPS_GPREL16:
4061 case BFD_RELOC_MICROMIPS_JMP:
4062 case BFD_RELOC_MICROMIPS_HI16:
4063 case BFD_RELOC_MICROMIPS_HI16_S:
4064 case BFD_RELOC_MICROMIPS_LO16:
4065 case BFD_RELOC_MICROMIPS_LITERAL:
4066 case BFD_RELOC_MICROMIPS_GOT16:
4067 case BFD_RELOC_MICROMIPS_CALL16:
4068 case BFD_RELOC_MICROMIPS_GOT_HI16:
4069 case BFD_RELOC_MICROMIPS_GOT_LO16:
4070 case BFD_RELOC_MICROMIPS_CALL_HI16:
4071 case BFD_RELOC_MICROMIPS_CALL_LO16:
4072 case BFD_RELOC_MICROMIPS_SUB:
4073 case BFD_RELOC_MICROMIPS_GOT_PAGE:
4074 case BFD_RELOC_MICROMIPS_GOT_OFST:
4075 case BFD_RELOC_MICROMIPS_GOT_DISP:
4076 case BFD_RELOC_MICROMIPS_HIGHEST:
4077 case BFD_RELOC_MICROMIPS_HIGHER:
4078 case BFD_RELOC_MICROMIPS_SCN_DISP:
4079 case BFD_RELOC_MICROMIPS_JALR:
4080 return TRUE;
4081
4082 default:
4083 return FALSE;
4084 }
4085}
4086
2309ddf2
MR
4087static inline bfd_boolean
4088jmp_reloc_p (bfd_reloc_code_real_type reloc)
4089{
4090 return reloc == BFD_RELOC_MIPS_JMP || reloc == BFD_RELOC_MICROMIPS_JMP;
4091}
4092
738e5348
RS
4093static inline bfd_boolean
4094got16_reloc_p (bfd_reloc_code_real_type reloc)
4095{
2309ddf2 4096 return (reloc == BFD_RELOC_MIPS_GOT16 || reloc == BFD_RELOC_MIPS16_GOT16
df58fc94 4097 || reloc == BFD_RELOC_MICROMIPS_GOT16);
738e5348
RS
4098}
4099
4100static inline bfd_boolean
4101hi16_reloc_p (bfd_reloc_code_real_type reloc)
4102{
2309ddf2 4103 return (reloc == BFD_RELOC_HI16_S || reloc == BFD_RELOC_MIPS16_HI16_S
df58fc94 4104 || reloc == BFD_RELOC_MICROMIPS_HI16_S);
738e5348
RS
4105}
4106
4107static inline bfd_boolean
4108lo16_reloc_p (bfd_reloc_code_real_type reloc)
4109{
2309ddf2 4110 return (reloc == BFD_RELOC_LO16 || reloc == BFD_RELOC_MIPS16_LO16
df58fc94
RS
4111 || reloc == BFD_RELOC_MICROMIPS_LO16);
4112}
4113
df58fc94
RS
4114static inline bfd_boolean
4115jalr_reloc_p (bfd_reloc_code_real_type reloc)
4116{
2309ddf2 4117 return reloc == BFD_RELOC_MIPS_JALR || reloc == BFD_RELOC_MICROMIPS_JALR;
738e5348
RS
4118}
4119
f2ae14a1
RS
4120static inline bfd_boolean
4121gprel16_reloc_p (bfd_reloc_code_real_type reloc)
4122{
4123 return (reloc == BFD_RELOC_GPREL16 || reloc == BFD_RELOC_MIPS16_GPREL
4124 || reloc == BFD_RELOC_MICROMIPS_GPREL16);
4125}
4126
2de39019
CM
4127/* Return true if RELOC is a PC-relative relocation that does not have
4128 full address range. */
4129
4130static inline bfd_boolean
4131limited_pcrel_reloc_p (bfd_reloc_code_real_type reloc)
4132{
4133 switch (reloc)
4134 {
4135 case BFD_RELOC_16_PCREL_S2:
4136 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
4137 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
4138 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
7361da2c
AB
4139 case BFD_RELOC_MIPS_21_PCREL_S2:
4140 case BFD_RELOC_MIPS_26_PCREL_S2:
4141 case BFD_RELOC_MIPS_18_PCREL_S3:
4142 case BFD_RELOC_MIPS_19_PCREL_S2:
2de39019
CM
4143 return TRUE;
4144
b47468a6 4145 case BFD_RELOC_32_PCREL:
7361da2c
AB
4146 case BFD_RELOC_HI16_S_PCREL:
4147 case BFD_RELOC_LO16_PCREL:
b47468a6
CM
4148 return HAVE_64BIT_ADDRESSES;
4149
2de39019
CM
4150 default:
4151 return FALSE;
4152 }
4153}
b47468a6 4154
5919d012 4155/* Return true if the given relocation might need a matching %lo().
0a44bf69
RS
4156 This is only "might" because SVR4 R_MIPS_GOT16 relocations only
4157 need a matching %lo() when applied to local symbols. */
5919d012
RS
4158
4159static inline bfd_boolean
17a2f251 4160reloc_needs_lo_p (bfd_reloc_code_real_type reloc)
5919d012 4161{
3b91255e 4162 return (HAVE_IN_PLACE_ADDENDS
738e5348 4163 && (hi16_reloc_p (reloc)
0a44bf69
RS
4164 /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo();
4165 all GOT16 relocations evaluate to "G". */
738e5348
RS
4166 || (got16_reloc_p (reloc) && mips_pic != VXWORKS_PIC)));
4167}
4168
4169/* Return the type of %lo() reloc needed by RELOC, given that
4170 reloc_needs_lo_p. */
4171
4172static inline bfd_reloc_code_real_type
4173matching_lo_reloc (bfd_reloc_code_real_type reloc)
4174{
df58fc94
RS
4175 return (mips16_reloc_p (reloc) ? BFD_RELOC_MIPS16_LO16
4176 : (micromips_reloc_p (reloc) ? BFD_RELOC_MICROMIPS_LO16
4177 : BFD_RELOC_LO16));
5919d012
RS
4178}
4179
4180/* Return true if the given fixup is followed by a matching R_MIPS_LO16
4181 relocation. */
4182
4183static inline bfd_boolean
17a2f251 4184fixup_has_matching_lo_p (fixS *fixp)
5919d012
RS
4185{
4186 return (fixp->fx_next != NULL
738e5348 4187 && fixp->fx_next->fx_r_type == matching_lo_reloc (fixp->fx_r_type)
5919d012
RS
4188 && fixp->fx_addsy == fixp->fx_next->fx_addsy
4189 && fixp->fx_offset == fixp->fx_next->fx_offset);
4190}
4191
462427c4
RS
4192/* Move all labels in LABELS to the current insertion point. TEXT_P
4193 says whether the labels refer to text or data. */
404a8071
RS
4194
4195static void
462427c4 4196mips_move_labels (struct insn_label_list *labels, bfd_boolean text_p)
404a8071
RS
4197{
4198 struct insn_label_list *l;
4199 valueT val;
4200
462427c4 4201 for (l = labels; l != NULL; l = l->next)
404a8071 4202 {
9c2799c2 4203 gas_assert (S_GET_SEGMENT (l->label) == now_seg);
404a8071
RS
4204 symbol_set_frag (l->label, frag_now);
4205 val = (valueT) frag_now_fix ();
df58fc94 4206 /* MIPS16/microMIPS text labels are stored as odd. */
462427c4 4207 if (text_p && HAVE_CODE_COMPRESSION)
404a8071
RS
4208 ++val;
4209 S_SET_VALUE (l->label, val);
4210 }
4211}
4212
462427c4
RS
4213/* Move all labels in insn_labels to the current insertion point
4214 and treat them as text labels. */
4215
4216static void
4217mips_move_text_labels (void)
4218{
4219 mips_move_labels (seg_info (now_seg)->label_list, TRUE);
4220}
4221
5f0fe04b
TS
4222static bfd_boolean
4223s_is_linkonce (symbolS *sym, segT from_seg)
4224{
4225 bfd_boolean linkonce = FALSE;
4226 segT symseg = S_GET_SEGMENT (sym);
4227
4228 if (symseg != from_seg && !S_IS_LOCAL (sym))
4229 {
4230 if ((bfd_get_section_flags (stdoutput, symseg) & SEC_LINK_ONCE))
4231 linkonce = TRUE;
5f0fe04b
TS
4232 /* The GNU toolchain uses an extension for ELF: a section
4233 beginning with the magic string .gnu.linkonce is a
4234 linkonce section. */
4235 if (strncmp (segment_name (symseg), ".gnu.linkonce",
4236 sizeof ".gnu.linkonce" - 1) == 0)
4237 linkonce = TRUE;
5f0fe04b
TS
4238 }
4239 return linkonce;
4240}
4241
e1b47bd5 4242/* Mark MIPS16 or microMIPS instruction label LABEL. This permits the
df58fc94
RS
4243 linker to handle them specially, such as generating jalx instructions
4244 when needed. We also make them odd for the duration of the assembly,
4245 in order to generate the right sort of code. We will make them even
252b5132
RH
4246 in the adjust_symtab routine, while leaving them marked. This is
4247 convenient for the debugger and the disassembler. The linker knows
4248 to make them odd again. */
4249
4250static void
e1b47bd5 4251mips_compressed_mark_label (symbolS *label)
252b5132 4252{
df58fc94 4253 gas_assert (HAVE_CODE_COMPRESSION);
a8dbcb85 4254
f3ded42a
RS
4255 if (mips_opts.mips16)
4256 S_SET_OTHER (label, ELF_ST_SET_MIPS16 (S_GET_OTHER (label)));
4257 else
4258 S_SET_OTHER (label, ELF_ST_SET_MICROMIPS (S_GET_OTHER (label)));
e1b47bd5
RS
4259 if ((S_GET_VALUE (label) & 1) == 0
4260 /* Don't adjust the address if the label is global or weak, or
4261 in a link-once section, since we'll be emitting symbol reloc
4262 references to it which will be patched up by the linker, and
4263 the final value of the symbol may or may not be MIPS16/microMIPS. */
4264 && !S_IS_WEAK (label)
4265 && !S_IS_EXTERNAL (label)
4266 && !s_is_linkonce (label, now_seg))
4267 S_SET_VALUE (label, S_GET_VALUE (label) | 1);
4268}
4269
4270/* Mark preceding MIPS16 or microMIPS instruction labels. */
4271
4272static void
4273mips_compressed_mark_labels (void)
4274{
4275 struct insn_label_list *l;
4276
4277 for (l = seg_info (now_seg)->label_list; l != NULL; l = l->next)
4278 mips_compressed_mark_label (l->label);
252b5132
RH
4279}
4280
4d7206a2
RS
4281/* End the current frag. Make it a variant frag and record the
4282 relaxation info. */
4283
4284static void
4285relax_close_frag (void)
4286{
584892a6 4287 mips_macro_warning.first_frag = frag_now;
4d7206a2 4288 frag_var (rs_machine_dependent, 0, 0,
584892a6 4289 RELAX_ENCODE (mips_relax.sizes[0], mips_relax.sizes[1]),
4d7206a2
RS
4290 mips_relax.symbol, 0, (char *) mips_relax.first_fixup);
4291
4292 memset (&mips_relax.sizes, 0, sizeof (mips_relax.sizes));
4293 mips_relax.first_fixup = 0;
4294}
4295
4296/* Start a new relaxation sequence whose expansion depends on SYMBOL.
4297 See the comment above RELAX_ENCODE for more details. */
4298
4299static void
4300relax_start (symbolS *symbol)
4301{
9c2799c2 4302 gas_assert (mips_relax.sequence == 0);
4d7206a2
RS
4303 mips_relax.sequence = 1;
4304 mips_relax.symbol = symbol;
4305}
4306
4307/* Start generating the second version of a relaxable sequence.
4308 See the comment above RELAX_ENCODE for more details. */
252b5132
RH
4309
4310static void
4d7206a2
RS
4311relax_switch (void)
4312{
9c2799c2 4313 gas_assert (mips_relax.sequence == 1);
4d7206a2
RS
4314 mips_relax.sequence = 2;
4315}
4316
4317/* End the current relaxable sequence. */
4318
4319static void
4320relax_end (void)
4321{
9c2799c2 4322 gas_assert (mips_relax.sequence == 2);
4d7206a2
RS
4323 relax_close_frag ();
4324 mips_relax.sequence = 0;
4325}
4326
11625dd8
RS
4327/* Return true if IP is a delayed branch or jump. */
4328
4329static inline bfd_boolean
4330delayed_branch_p (const struct mips_cl_insn *ip)
4331{
4332 return (ip->insn_mo->pinfo & (INSN_UNCOND_BRANCH_DELAY
4333 | INSN_COND_BRANCH_DELAY
4334 | INSN_COND_BRANCH_LIKELY)) != 0;
4335}
4336
4337/* Return true if IP is a compact branch or jump. */
4338
4339static inline bfd_boolean
4340compact_branch_p (const struct mips_cl_insn *ip)
4341{
26545944
RS
4342 return (ip->insn_mo->pinfo2 & (INSN2_UNCOND_BRANCH
4343 | INSN2_COND_BRANCH)) != 0;
11625dd8
RS
4344}
4345
4346/* Return true if IP is an unconditional branch or jump. */
4347
4348static inline bfd_boolean
4349uncond_branch_p (const struct mips_cl_insn *ip)
4350{
4351 return ((ip->insn_mo->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0
26545944 4352 || (ip->insn_mo->pinfo2 & INSN2_UNCOND_BRANCH) != 0);
11625dd8
RS
4353}
4354
4355/* Return true if IP is a branch-likely instruction. */
4356
4357static inline bfd_boolean
4358branch_likely_p (const struct mips_cl_insn *ip)
4359{
4360 return (ip->insn_mo->pinfo & INSN_COND_BRANCH_LIKELY) != 0;
4361}
4362
14fe068b
RS
4363/* Return the type of nop that should be used to fill the delay slot
4364 of delayed branch IP. */
4365
4366static struct mips_cl_insn *
4367get_delay_slot_nop (const struct mips_cl_insn *ip)
4368{
4369 if (mips_opts.micromips
4370 && (ip->insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
4371 return &micromips_nop32_insn;
4372 return NOP_INSN;
4373}
4374
fc76e730
RS
4375/* Return a mask that has bit N set if OPCODE reads the register(s)
4376 in operand N. */
df58fc94
RS
4377
4378static unsigned int
fc76e730 4379insn_read_mask (const struct mips_opcode *opcode)
df58fc94 4380{
fc76e730
RS
4381 return (opcode->pinfo & INSN_READ_ALL) >> INSN_READ_SHIFT;
4382}
df58fc94 4383
fc76e730
RS
4384/* Return a mask that has bit N set if OPCODE writes to the register(s)
4385 in operand N. */
4386
4387static unsigned int
4388insn_write_mask (const struct mips_opcode *opcode)
4389{
4390 return (opcode->pinfo & INSN_WRITE_ALL) >> INSN_WRITE_SHIFT;
4391}
4392
4393/* Return a mask of the registers specified by operand OPERAND of INSN.
4394 Ignore registers of type OP_REG_<t> unless bit OP_REG_<t> of TYPE_MASK
4395 is set. */
4396
4397static unsigned int
4398operand_reg_mask (const struct mips_cl_insn *insn,
4399 const struct mips_operand *operand,
4400 unsigned int type_mask)
4401{
4402 unsigned int uval, vsel;
4403
4404 switch (operand->type)
df58fc94 4405 {
fc76e730
RS
4406 case OP_INT:
4407 case OP_MAPPED_INT:
4408 case OP_MSB:
4409 case OP_PCREL:
4410 case OP_PERF_REG:
4411 case OP_ADDIUSP_INT:
4412 case OP_ENTRY_EXIT_LIST:
4413 case OP_REPEAT_DEST_REG:
4414 case OP_REPEAT_PREV_REG:
4415 case OP_PC:
14daeee3
RS
4416 case OP_VU0_SUFFIX:
4417 case OP_VU0_MATCH_SUFFIX:
56d438b1 4418 case OP_IMM_INDEX:
fc76e730
RS
4419 abort ();
4420
4421 case OP_REG:
0f35dbc4 4422 case OP_OPTIONAL_REG:
fc76e730
RS
4423 {
4424 const struct mips_reg_operand *reg_op;
4425
4426 reg_op = (const struct mips_reg_operand *) operand;
4427 if (!(type_mask & (1 << reg_op->reg_type)))
4428 return 0;
4429 uval = insn_extract_operand (insn, operand);
4430 return 1 << mips_decode_reg_operand (reg_op, uval);
4431 }
4432
4433 case OP_REG_PAIR:
4434 {
4435 const struct mips_reg_pair_operand *pair_op;
4436
4437 pair_op = (const struct mips_reg_pair_operand *) operand;
4438 if (!(type_mask & (1 << pair_op->reg_type)))
4439 return 0;
4440 uval = insn_extract_operand (insn, operand);
4441 return (1 << pair_op->reg1_map[uval]) | (1 << pair_op->reg2_map[uval]);
4442 }
4443
4444 case OP_CLO_CLZ_DEST:
4445 if (!(type_mask & (1 << OP_REG_GP)))
4446 return 0;
4447 uval = insn_extract_operand (insn, operand);
4448 return (1 << (uval & 31)) | (1 << (uval >> 5));
4449
7361da2c
AB
4450 case OP_SAME_RS_RT:
4451 if (!(type_mask & (1 << OP_REG_GP)))
4452 return 0;
4453 uval = insn_extract_operand (insn, operand);
4454 gas_assert ((uval & 31) == (uval >> 5));
4455 return 1 << (uval & 31);
4456
4457 case OP_CHECK_PREV:
4458 case OP_NON_ZERO_REG:
4459 if (!(type_mask & (1 << OP_REG_GP)))
4460 return 0;
4461 uval = insn_extract_operand (insn, operand);
4462 return 1 << (uval & 31);
4463
fc76e730
RS
4464 case OP_LWM_SWM_LIST:
4465 abort ();
4466
4467 case OP_SAVE_RESTORE_LIST:
4468 abort ();
4469
4470 case OP_MDMX_IMM_REG:
4471 if (!(type_mask & (1 << OP_REG_VEC)))
4472 return 0;
4473 uval = insn_extract_operand (insn, operand);
4474 vsel = uval >> 5;
4475 if ((vsel & 0x18) == 0x18)
4476 return 0;
4477 return 1 << (uval & 31);
56d438b1
CF
4478
4479 case OP_REG_INDEX:
4480 if (!(type_mask & (1 << OP_REG_GP)))
4481 return 0;
4482 return 1 << insn_extract_operand (insn, operand);
df58fc94 4483 }
fc76e730
RS
4484 abort ();
4485}
4486
4487/* Return a mask of the registers specified by operands OPNO_MASK of INSN,
4488 where bit N of OPNO_MASK is set if operand N should be included.
4489 Ignore registers of type OP_REG_<t> unless bit OP_REG_<t> of TYPE_MASK
4490 is set. */
4491
4492static unsigned int
4493insn_reg_mask (const struct mips_cl_insn *insn,
4494 unsigned int type_mask, unsigned int opno_mask)
4495{
4496 unsigned int opno, reg_mask;
4497
4498 opno = 0;
4499 reg_mask = 0;
4500 while (opno_mask != 0)
4501 {
4502 if (opno_mask & 1)
4503 reg_mask |= operand_reg_mask (insn, insn_opno (insn, opno), type_mask);
4504 opno_mask >>= 1;
4505 opno += 1;
4506 }
4507 return reg_mask;
df58fc94
RS
4508}
4509
4c260379
RS
4510/* Return the mask of core registers that IP reads. */
4511
4512static unsigned int
4513gpr_read_mask (const struct mips_cl_insn *ip)
4514{
4515 unsigned long pinfo, pinfo2;
4516 unsigned int mask;
4517
fc76e730 4518 mask = insn_reg_mask (ip, 1 << OP_REG_GP, insn_read_mask (ip->insn_mo));
4c260379
RS
4519 pinfo = ip->insn_mo->pinfo;
4520 pinfo2 = ip->insn_mo->pinfo2;
fc76e730 4521 if (pinfo & INSN_UDI)
4c260379 4522 {
fc76e730
RS
4523 /* UDI instructions have traditionally been assumed to read RS
4524 and RT. */
4525 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RT, *ip);
4526 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RS, *ip);
4c260379 4527 }
fc76e730
RS
4528 if (pinfo & INSN_READ_GPR_24)
4529 mask |= 1 << 24;
4530 if (pinfo2 & INSN2_READ_GPR_16)
4531 mask |= 1 << 16;
4532 if (pinfo2 & INSN2_READ_SP)
4533 mask |= 1 << SP;
26545944 4534 if (pinfo2 & INSN2_READ_GPR_31)
fc76e730 4535 mask |= 1 << 31;
fe35f09f
RS
4536 /* Don't include register 0. */
4537 return mask & ~1;
4c260379
RS
4538}
4539
4540/* Return the mask of core registers that IP writes. */
4541
4542static unsigned int
4543gpr_write_mask (const struct mips_cl_insn *ip)
4544{
4545 unsigned long pinfo, pinfo2;
4546 unsigned int mask;
4547
fc76e730 4548 mask = insn_reg_mask (ip, 1 << OP_REG_GP, insn_write_mask (ip->insn_mo));
4c260379
RS
4549 pinfo = ip->insn_mo->pinfo;
4550 pinfo2 = ip->insn_mo->pinfo2;
fc76e730
RS
4551 if (pinfo & INSN_WRITE_GPR_24)
4552 mask |= 1 << 24;
4553 if (pinfo & INSN_WRITE_GPR_31)
4554 mask |= 1 << 31;
4555 if (pinfo & INSN_UDI)
4556 /* UDI instructions have traditionally been assumed to write to RD. */
4557 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RD, *ip);
4558 if (pinfo2 & INSN2_WRITE_SP)
4559 mask |= 1 << SP;
fe35f09f
RS
4560 /* Don't include register 0. */
4561 return mask & ~1;
4c260379
RS
4562}
4563
4564/* Return the mask of floating-point registers that IP reads. */
4565
4566static unsigned int
4567fpr_read_mask (const struct mips_cl_insn *ip)
4568{
fc76e730 4569 unsigned long pinfo;
4c260379
RS
4570 unsigned int mask;
4571
9d5de888
CF
4572 mask = insn_reg_mask (ip, ((1 << OP_REG_FP) | (1 << OP_REG_VEC)
4573 | (1 << OP_REG_MSA)),
fc76e730 4574 insn_read_mask (ip->insn_mo));
4c260379 4575 pinfo = ip->insn_mo->pinfo;
4c260379
RS
4576 /* Conservatively treat all operands to an FP_D instruction are doubles.
4577 (This is overly pessimistic for things like cvt.d.s.) */
bad1aba3 4578 if (FPR_SIZE != 64 && (pinfo & FP_D))
4c260379
RS
4579 mask |= mask << 1;
4580 return mask;
4581}
4582
4583/* Return the mask of floating-point registers that IP writes. */
4584
4585static unsigned int
4586fpr_write_mask (const struct mips_cl_insn *ip)
4587{
fc76e730 4588 unsigned long pinfo;
4c260379
RS
4589 unsigned int mask;
4590
9d5de888
CF
4591 mask = insn_reg_mask (ip, ((1 << OP_REG_FP) | (1 << OP_REG_VEC)
4592 | (1 << OP_REG_MSA)),
fc76e730 4593 insn_write_mask (ip->insn_mo));
4c260379 4594 pinfo = ip->insn_mo->pinfo;
4c260379
RS
4595 /* Conservatively treat all operands to an FP_D instruction are doubles.
4596 (This is overly pessimistic for things like cvt.s.d.) */
bad1aba3 4597 if (FPR_SIZE != 64 && (pinfo & FP_D))
4c260379
RS
4598 mask |= mask << 1;
4599 return mask;
4600}
4601
a1d78564
RS
4602/* Operand OPNUM of INSN is an odd-numbered floating-point register.
4603 Check whether that is allowed. */
4604
4605static bfd_boolean
4606mips_oddfpreg_ok (const struct mips_opcode *insn, int opnum)
4607{
4608 const char *s = insn->name;
351cdf24
MF
4609 bfd_boolean oddspreg = (ISA_HAS_ODD_SINGLE_FPR (mips_opts.isa, mips_opts.arch)
4610 || FPR_SIZE == 64)
4611 && mips_opts.oddspreg;
a1d78564
RS
4612
4613 if (insn->pinfo == INSN_MACRO)
4614 /* Let a macro pass, we'll catch it later when it is expanded. */
4615 return TRUE;
4616
351cdf24
MF
4617 /* Single-precision coprocessor loads and moves are OK for 32-bit registers,
4618 otherwise it depends on oddspreg. */
4619 if ((insn->pinfo & FP_S)
4620 && (insn->pinfo & (INSN_LOAD_MEMORY | INSN_STORE_MEMORY
43885403 4621 | INSN_LOAD_COPROC | INSN_COPROC_MOVE)))
351cdf24 4622 return FPR_SIZE == 32 || oddspreg;
a1d78564 4623
351cdf24
MF
4624 /* Allow odd registers for single-precision ops and double-precision if the
4625 floating-point registers are 64-bit wide. */
4626 switch (insn->pinfo & (FP_S | FP_D))
4627 {
4628 case FP_S:
4629 case 0:
4630 return oddspreg;
4631 case FP_D:
4632 return FPR_SIZE == 64;
4633 default:
4634 break;
a1d78564
RS
4635 }
4636
351cdf24
MF
4637 /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */
4638 s = strchr (insn->name, '.');
4639 if (s != NULL && opnum == 2)
4640 s = strchr (s + 1, '.');
4641 if (s != NULL && (s[1] == 'w' || s[1] == 's'))
4642 return oddspreg;
a1d78564 4643
351cdf24 4644 return FPR_SIZE == 64;
a1d78564
RS
4645}
4646
a1d78564
RS
4647/* Information about an instruction argument that we're trying to match. */
4648struct mips_arg_info
4649{
4650 /* The instruction so far. */
4651 struct mips_cl_insn *insn;
4652
a92713e6
RS
4653 /* The first unconsumed operand token. */
4654 struct mips_operand_token *token;
4655
a1d78564
RS
4656 /* The 1-based operand number, in terms of insn->insn_mo->args. */
4657 int opnum;
4658
4659 /* The 1-based argument number, for error reporting. This does not
4660 count elided optional registers, etc.. */
4661 int argnum;
4662
4663 /* The last OP_REG operand seen, or ILLEGAL_REG if none. */
4664 unsigned int last_regno;
4665
4666 /* If the first operand was an OP_REG, this is the register that it
4667 specified, otherwise it is ILLEGAL_REG. */
4668 unsigned int dest_regno;
4669
4670 /* The value of the last OP_INT operand. Only used for OP_MSB,
4671 where it gives the lsb position. */
4672 unsigned int last_op_int;
4673
60f20e8b
RS
4674 /* If true, match routines should assume that no later instruction
4675 alternative matches and should therefore be as accomodating as
4676 possible. Match routines should not report errors if something
4677 is only invalid for !LAX_MATCH. */
4678 bfd_boolean lax_match;
a1d78564 4679
a1d78564
RS
4680 /* True if a reference to the current AT register was seen. */
4681 bfd_boolean seen_at;
4682};
4683
1a00e612
RS
4684/* Record that the argument is out of range. */
4685
4686static void
4687match_out_of_range (struct mips_arg_info *arg)
4688{
4689 set_insn_error_i (arg->argnum, _("operand %d out of range"), arg->argnum);
4690}
4691
4692/* Record that the argument isn't constant but needs to be. */
4693
4694static void
4695match_not_constant (struct mips_arg_info *arg)
4696{
4697 set_insn_error_i (arg->argnum, _("operand %d must be constant"),
4698 arg->argnum);
4699}
4700
a92713e6
RS
4701/* Try to match an OT_CHAR token for character CH. Consume the token
4702 and return true on success, otherwise return false. */
a1d78564 4703
a92713e6
RS
4704static bfd_boolean
4705match_char (struct mips_arg_info *arg, char ch)
a1d78564 4706{
a92713e6
RS
4707 if (arg->token->type == OT_CHAR && arg->token->u.ch == ch)
4708 {
4709 ++arg->token;
4710 if (ch == ',')
4711 arg->argnum += 1;
4712 return TRUE;
4713 }
4714 return FALSE;
4715}
a1d78564 4716
a92713e6
RS
4717/* Try to get an expression from the next tokens in ARG. Consume the
4718 tokens and return true on success, storing the expression value in
4719 VALUE and relocation types in R. */
4720
4721static bfd_boolean
4722match_expression (struct mips_arg_info *arg, expressionS *value,
4723 bfd_reloc_code_real_type *r)
4724{
d436c1c2
RS
4725 /* If the next token is a '(' that was parsed as being part of a base
4726 expression, assume we have an elided offset. The later match will fail
4727 if this turns out to be wrong. */
4728 if (arg->token->type == OT_CHAR && arg->token->u.ch == '(')
a1d78564 4729 {
d436c1c2
RS
4730 value->X_op = O_constant;
4731 value->X_add_number = 0;
4732 r[0] = r[1] = r[2] = BFD_RELOC_UNUSED;
a92713e6
RS
4733 return TRUE;
4734 }
4735
d436c1c2
RS
4736 /* Reject register-based expressions such as "0+$2" and "(($2))".
4737 For plain registers the default error seems more appropriate. */
4738 if (arg->token->type == OT_INTEGER
4739 && arg->token->u.integer.value.X_op == O_register)
a92713e6 4740 {
d436c1c2
RS
4741 set_insn_error (arg->argnum, _("register value used as expression"));
4742 return FALSE;
a1d78564 4743 }
d436c1c2
RS
4744
4745 if (arg->token->type == OT_INTEGER)
a92713e6 4746 {
d436c1c2
RS
4747 *value = arg->token->u.integer.value;
4748 memcpy (r, arg->token->u.integer.relocs, 3 * sizeof (*r));
4749 ++arg->token;
4750 return TRUE;
a92713e6 4751 }
a92713e6 4752
d436c1c2
RS
4753 set_insn_error_i
4754 (arg->argnum, _("operand %d must be an immediate expression"),
4755 arg->argnum);
4756 return FALSE;
a92713e6
RS
4757}
4758
4759/* Try to get a constant expression from the next tokens in ARG. Consume
4760 the tokens and return return true on success, storing the constant value
4761 in *VALUE. Use FALLBACK as the value if the match succeeded with an
4762 error. */
4763
4764static bfd_boolean
1a00e612 4765match_const_int (struct mips_arg_info *arg, offsetT *value)
a92713e6
RS
4766{
4767 expressionS ex;
4768 bfd_reloc_code_real_type r[3];
a1d78564 4769
a92713e6
RS
4770 if (!match_expression (arg, &ex, r))
4771 return FALSE;
4772
4773 if (r[0] == BFD_RELOC_UNUSED && ex.X_op == O_constant)
a1d78564
RS
4774 *value = ex.X_add_number;
4775 else
4776 {
1a00e612
RS
4777 match_not_constant (arg);
4778 return FALSE;
a1d78564 4779 }
a92713e6 4780 return TRUE;
a1d78564
RS
4781}
4782
4783/* Return the RTYPE_* flags for a register operand of type TYPE that
4784 appears in instruction OPCODE. */
4785
4786static unsigned int
4787convert_reg_type (const struct mips_opcode *opcode,
4788 enum mips_reg_operand_type type)
4789{
4790 switch (type)
4791 {
4792 case OP_REG_GP:
4793 return RTYPE_NUM | RTYPE_GP;
4794
4795 case OP_REG_FP:
4796 /* Allow vector register names for MDMX if the instruction is a 64-bit
4797 FPR load, store or move (including moves to and from GPRs). */
4798 if ((mips_opts.ase & ASE_MDMX)
4799 && (opcode->pinfo & FP_D)
43885403 4800 && (opcode->pinfo & (INSN_COPROC_MOVE
a1d78564 4801 | INSN_COPROC_MEMORY_DELAY
43885403 4802 | INSN_LOAD_COPROC
67dc82bc 4803 | INSN_LOAD_MEMORY
a1d78564
RS
4804 | INSN_STORE_MEMORY)))
4805 return RTYPE_FPU | RTYPE_VEC;
4806 return RTYPE_FPU;
4807
4808 case OP_REG_CCC:
4809 if (opcode->pinfo & (FP_D | FP_S))
4810 return RTYPE_CCC | RTYPE_FCC;
4811 return RTYPE_CCC;
4812
4813 case OP_REG_VEC:
4814 if (opcode->membership & INSN_5400)
4815 return RTYPE_FPU;
4816 return RTYPE_FPU | RTYPE_VEC;
4817
4818 case OP_REG_ACC:
4819 return RTYPE_ACC;
4820
4821 case OP_REG_COPRO:
4822 if (opcode->name[strlen (opcode->name) - 1] == '0')
4823 return RTYPE_NUM | RTYPE_CP0;
4824 return RTYPE_NUM;
4825
4826 case OP_REG_HW:
4827 return RTYPE_NUM;
14daeee3
RS
4828
4829 case OP_REG_VI:
4830 return RTYPE_NUM | RTYPE_VI;
4831
4832 case OP_REG_VF:
4833 return RTYPE_NUM | RTYPE_VF;
4834
4835 case OP_REG_R5900_I:
4836 return RTYPE_R5900_I;
4837
4838 case OP_REG_R5900_Q:
4839 return RTYPE_R5900_Q;
4840
4841 case OP_REG_R5900_R:
4842 return RTYPE_R5900_R;
4843
4844 case OP_REG_R5900_ACC:
4845 return RTYPE_R5900_ACC;
56d438b1
CF
4846
4847 case OP_REG_MSA:
4848 return RTYPE_MSA;
4849
4850 case OP_REG_MSA_CTRL:
4851 return RTYPE_NUM;
a1d78564
RS
4852 }
4853 abort ();
4854}
4855
4856/* ARG is register REGNO, of type TYPE. Warn about any dubious registers. */
4857
4858static void
4859check_regno (struct mips_arg_info *arg,
4860 enum mips_reg_operand_type type, unsigned int regno)
4861{
4862 if (AT && type == OP_REG_GP && regno == AT)
4863 arg->seen_at = TRUE;
4864
4865 if (type == OP_REG_FP
4866 && (regno & 1) != 0
a1d78564 4867 && !mips_oddfpreg_ok (arg->insn->insn_mo, arg->opnum))
351cdf24
MF
4868 {
4869 /* This was a warning prior to introducing O32 FPXX and FP64 support
4870 so maintain a warning for FP32 but raise an error for the new
4871 cases. */
4872 if (FPR_SIZE == 32)
4873 as_warn (_("float register should be even, was %d"), regno);
4874 else
4875 as_bad (_("float register should be even, was %d"), regno);
4876 }
a1d78564
RS
4877
4878 if (type == OP_REG_CCC)
4879 {
4880 const char *name;
4881 size_t length;
4882
4883 name = arg->insn->insn_mo->name;
4884 length = strlen (name);
4885 if ((regno & 1) != 0
4886 && ((length >= 3 && strcmp (name + length - 3, ".ps") == 0)
4887 || (length >= 5 && strncmp (name + length - 5, "any2", 4) == 0)))
1661c76c 4888 as_warn (_("condition code register should be even for %s, was %d"),
a1d78564
RS
4889 name, regno);
4890
4891 if ((regno & 3) != 0
4892 && (length >= 5 && strncmp (name + length - 5, "any4", 4) == 0))
1661c76c 4893 as_warn (_("condition code register should be 0 or 4 for %s, was %d"),
a1d78564
RS
4894 name, regno);
4895 }
4896}
4897
a92713e6
RS
4898/* ARG is a register with symbol value SYMVAL. Try to interpret it as
4899 a register of type TYPE. Return true on success, storing the register
4900 number in *REGNO and warning about any dubious uses. */
4901
4902static bfd_boolean
4903match_regno (struct mips_arg_info *arg, enum mips_reg_operand_type type,
4904 unsigned int symval, unsigned int *regno)
4905{
4906 if (type == OP_REG_VEC)
4907 symval = mips_prefer_vec_regno (symval);
4908 if (!(symval & convert_reg_type (arg->insn->insn_mo, type)))
4909 return FALSE;
4910
4911 *regno = symval & RNUM_MASK;
4912 check_regno (arg, type, *regno);
4913 return TRUE;
4914}
4915
4916/* Try to interpret the next token in ARG as a register of type TYPE.
4917 Consume the token and return true on success, storing the register
4918 number in *REGNO. Return false on failure. */
4919
4920static bfd_boolean
4921match_reg (struct mips_arg_info *arg, enum mips_reg_operand_type type,
4922 unsigned int *regno)
4923{
4924 if (arg->token->type == OT_REG
4925 && match_regno (arg, type, arg->token->u.regno, regno))
4926 {
4927 ++arg->token;
4928 return TRUE;
4929 }
4930 return FALSE;
4931}
4932
4933/* Try to interpret the next token in ARG as a range of registers of type TYPE.
4934 Consume the token and return true on success, storing the register numbers
4935 in *REGNO1 and *REGNO2. Return false on failure. */
4936
4937static bfd_boolean
4938match_reg_range (struct mips_arg_info *arg, enum mips_reg_operand_type type,
4939 unsigned int *regno1, unsigned int *regno2)
4940{
4941 if (match_reg (arg, type, regno1))
4942 {
4943 *regno2 = *regno1;
4944 return TRUE;
4945 }
4946 if (arg->token->type == OT_REG_RANGE
4947 && match_regno (arg, type, arg->token->u.reg_range.regno1, regno1)
4948 && match_regno (arg, type, arg->token->u.reg_range.regno2, regno2)
4949 && *regno1 <= *regno2)
4950 {
4951 ++arg->token;
4952 return TRUE;
4953 }
4954 return FALSE;
4955}
4956
a1d78564
RS
4957/* OP_INT matcher. */
4958
a92713e6 4959static bfd_boolean
a1d78564 4960match_int_operand (struct mips_arg_info *arg,
a92713e6 4961 const struct mips_operand *operand_base)
a1d78564
RS
4962{
4963 const struct mips_int_operand *operand;
3ccad066 4964 unsigned int uval;
a1d78564
RS
4965 int min_val, max_val, factor;
4966 offsetT sval;
a1d78564
RS
4967
4968 operand = (const struct mips_int_operand *) operand_base;
4969 factor = 1 << operand->shift;
3ccad066
RS
4970 min_val = mips_int_operand_min (operand);
4971 max_val = mips_int_operand_max (operand);
a1d78564 4972
d436c1c2
RS
4973 if (operand_base->lsb == 0
4974 && operand_base->size == 16
4975 && operand->shift == 0
4976 && operand->bias == 0
4977 && (operand->max_val == 32767 || operand->max_val == 65535))
a1d78564
RS
4978 {
4979 /* The operand can be relocated. */
a92713e6
RS
4980 if (!match_expression (arg, &offset_expr, offset_reloc))
4981 return FALSE;
4982
4983 if (offset_reloc[0] != BFD_RELOC_UNUSED)
a1d78564
RS
4984 /* Relocation operators were used. Accept the arguent and
4985 leave the relocation value in offset_expr and offset_relocs
4986 for the caller to process. */
a92713e6
RS
4987 return TRUE;
4988
4989 if (offset_expr.X_op != O_constant)
a1d78564 4990 {
60f20e8b
RS
4991 /* Accept non-constant operands if no later alternative matches,
4992 leaving it for the caller to process. */
4993 if (!arg->lax_match)
4994 return FALSE;
a92713e6
RS
4995 offset_reloc[0] = BFD_RELOC_LO16;
4996 return TRUE;
a1d78564 4997 }
a92713e6 4998
a1d78564
RS
4999 /* Clear the global state; we're going to install the operand
5000 ourselves. */
a92713e6 5001 sval = offset_expr.X_add_number;
a1d78564 5002 offset_expr.X_op = O_absent;
60f20e8b
RS
5003
5004 /* For compatibility with older assemblers, we accept
5005 0x8000-0xffff as signed 16-bit numbers when only
5006 signed numbers are allowed. */
5007 if (sval > max_val)
5008 {
5009 max_val = ((1 << operand_base->size) - 1) << operand->shift;
5010 if (!arg->lax_match && sval <= max_val)
5011 return FALSE;
5012 }
a1d78564
RS
5013 }
5014 else
5015 {
1a00e612 5016 if (!match_const_int (arg, &sval))
a92713e6 5017 return FALSE;
a1d78564
RS
5018 }
5019
5020 arg->last_op_int = sval;
5021
1a00e612 5022 if (sval < min_val || sval > max_val || sval % factor)
a1d78564 5023 {
1a00e612
RS
5024 match_out_of_range (arg);
5025 return FALSE;
a1d78564
RS
5026 }
5027
5028 uval = (unsigned int) sval >> operand->shift;
5029 uval -= operand->bias;
5030
5031 /* Handle -mfix-cn63xxp1. */
5032 if (arg->opnum == 1
5033 && mips_fix_cn63xxp1
5034 && !mips_opts.micromips
5035 && strcmp ("pref", arg->insn->insn_mo->name) == 0)
5036 switch (uval)
5037 {
5038 case 5:
5039 case 25:
5040 case 26:
5041 case 27:
5042 case 28:
5043 case 29:
5044 case 30:
5045 case 31:
5046 /* These are ok. */
5047 break;
5048
5049 default:
5050 /* The rest must be changed to 28. */
5051 uval = 28;
5052 break;
5053 }
5054
5055 insn_insert_operand (arg->insn, operand_base, uval);
a92713e6 5056 return TRUE;
a1d78564
RS
5057}
5058
5059/* OP_MAPPED_INT matcher. */
5060
a92713e6 5061static bfd_boolean
a1d78564 5062match_mapped_int_operand (struct mips_arg_info *arg,
a92713e6 5063 const struct mips_operand *operand_base)
a1d78564
RS
5064{
5065 const struct mips_mapped_int_operand *operand;
5066 unsigned int uval, num_vals;
5067 offsetT sval;
5068
5069 operand = (const struct mips_mapped_int_operand *) operand_base;
1a00e612 5070 if (!match_const_int (arg, &sval))
a92713e6 5071 return FALSE;
a1d78564
RS
5072
5073 num_vals = 1 << operand_base->size;
5074 for (uval = 0; uval < num_vals; uval++)
5075 if (operand->int_map[uval] == sval)
5076 break;
5077 if (uval == num_vals)
1a00e612
RS
5078 {
5079 match_out_of_range (arg);
5080 return FALSE;
5081 }
a1d78564
RS
5082
5083 insn_insert_operand (arg->insn, operand_base, uval);
a92713e6 5084 return TRUE;
a1d78564
RS
5085}
5086
5087/* OP_MSB matcher. */
5088
a92713e6 5089static bfd_boolean
a1d78564 5090match_msb_operand (struct mips_arg_info *arg,
a92713e6 5091 const struct mips_operand *operand_base)
a1d78564
RS
5092{
5093 const struct mips_msb_operand *operand;
5094 int min_val, max_val, max_high;
5095 offsetT size, sval, high;
5096
5097 operand = (const struct mips_msb_operand *) operand_base;
5098 min_val = operand->bias;
5099 max_val = min_val + (1 << operand_base->size) - 1;
5100 max_high = operand->opsize;
5101
1a00e612 5102 if (!match_const_int (arg, &size))
a92713e6 5103 return FALSE;
a1d78564
RS
5104
5105 high = size + arg->last_op_int;
5106 sval = operand->add_lsb ? high : size;
5107
5108 if (size < 0 || high > max_high || sval < min_val || sval > max_val)
5109 {
1a00e612
RS
5110 match_out_of_range (arg);
5111 return FALSE;
a1d78564
RS
5112 }
5113 insn_insert_operand (arg->insn, operand_base, sval - min_val);
a92713e6 5114 return TRUE;
a1d78564
RS
5115}
5116
5117/* OP_REG matcher. */
5118
a92713e6 5119static bfd_boolean
a1d78564 5120match_reg_operand (struct mips_arg_info *arg,
a92713e6 5121 const struct mips_operand *operand_base)
a1d78564
RS
5122{
5123 const struct mips_reg_operand *operand;
a92713e6 5124 unsigned int regno, uval, num_vals;
a1d78564
RS
5125
5126 operand = (const struct mips_reg_operand *) operand_base;
a92713e6
RS
5127 if (!match_reg (arg, operand->reg_type, &regno))
5128 return FALSE;
a1d78564
RS
5129
5130 if (operand->reg_map)
5131 {
5132 num_vals = 1 << operand->root.size;
5133 for (uval = 0; uval < num_vals; uval++)
5134 if (operand->reg_map[uval] == regno)
5135 break;
5136 if (num_vals == uval)
a92713e6 5137 return FALSE;
a1d78564
RS
5138 }
5139 else
5140 uval = regno;
5141
a1d78564
RS
5142 arg->last_regno = regno;
5143 if (arg->opnum == 1)
5144 arg->dest_regno = regno;
5145 insn_insert_operand (arg->insn, operand_base, uval);
a92713e6 5146 return TRUE;
a1d78564
RS
5147}
5148
5149/* OP_REG_PAIR matcher. */
5150
a92713e6 5151static bfd_boolean
a1d78564 5152match_reg_pair_operand (struct mips_arg_info *arg,
a92713e6 5153 const struct mips_operand *operand_base)
a1d78564
RS
5154{
5155 const struct mips_reg_pair_operand *operand;
a92713e6 5156 unsigned int regno1, regno2, uval, num_vals;
a1d78564
RS
5157
5158 operand = (const struct mips_reg_pair_operand *) operand_base;
a92713e6
RS
5159 if (!match_reg (arg, operand->reg_type, &regno1)
5160 || !match_char (arg, ',')
5161 || !match_reg (arg, operand->reg_type, &regno2))
5162 return FALSE;
a1d78564
RS
5163
5164 num_vals = 1 << operand_base->size;
5165 for (uval = 0; uval < num_vals; uval++)
5166 if (operand->reg1_map[uval] == regno1 && operand->reg2_map[uval] == regno2)
5167 break;
5168 if (uval == num_vals)
a92713e6 5169 return FALSE;
a1d78564 5170
a1d78564 5171 insn_insert_operand (arg->insn, operand_base, uval);
a92713e6 5172 return TRUE;
a1d78564
RS
5173}
5174
5175/* OP_PCREL matcher. The caller chooses the relocation type. */
5176
a92713e6
RS
5177static bfd_boolean
5178match_pcrel_operand (struct mips_arg_info *arg)
a1d78564 5179{
a92713e6
RS
5180 bfd_reloc_code_real_type r[3];
5181
5182 return match_expression (arg, &offset_expr, r) && r[0] == BFD_RELOC_UNUSED;
a1d78564
RS
5183}
5184
5185/* OP_PERF_REG matcher. */
5186
a92713e6 5187static bfd_boolean
a1d78564 5188match_perf_reg_operand (struct mips_arg_info *arg,
a92713e6 5189 const struct mips_operand *operand)
a1d78564
RS
5190{
5191 offsetT sval;
5192
1a00e612 5193 if (!match_const_int (arg, &sval))
a92713e6 5194 return FALSE;
a1d78564
RS
5195
5196 if (sval != 0
5197 && (sval != 1
5198 || (mips_opts.arch == CPU_R5900
5199 && (strcmp (arg->insn->insn_mo->name, "mfps") == 0
5200 || strcmp (arg->insn->insn_mo->name, "mtps") == 0))))
5201 {
1a00e612
RS
5202 set_insn_error (arg->argnum, _("invalid performance register"));
5203 return FALSE;
a1d78564
RS
5204 }
5205
5206 insn_insert_operand (arg->insn, operand, sval);
a92713e6 5207 return TRUE;
a1d78564
RS
5208}
5209
5210/* OP_ADDIUSP matcher. */
5211
a92713e6 5212static bfd_boolean
a1d78564 5213match_addiusp_operand (struct mips_arg_info *arg,
a92713e6 5214 const struct mips_operand *operand)
a1d78564
RS
5215{
5216 offsetT sval;
5217 unsigned int uval;
5218
1a00e612 5219 if (!match_const_int (arg, &sval))
a92713e6 5220 return FALSE;
a1d78564
RS
5221
5222 if (sval % 4)
1a00e612
RS
5223 {
5224 match_out_of_range (arg);
5225 return FALSE;
5226 }
a1d78564
RS
5227
5228 sval /= 4;
5229 if (!(sval >= -258 && sval <= 257) || (sval >= -2 && sval <= 1))
1a00e612
RS
5230 {
5231 match_out_of_range (arg);
5232 return FALSE;
5233 }
a1d78564
RS
5234
5235 uval = (unsigned int) sval;
5236 uval = ((uval >> 1) & ~0xff) | (uval & 0xff);
5237 insn_insert_operand (arg->insn, operand, uval);
a92713e6 5238 return TRUE;
a1d78564
RS
5239}
5240
5241/* OP_CLO_CLZ_DEST matcher. */
5242
a92713e6 5243static bfd_boolean
a1d78564 5244match_clo_clz_dest_operand (struct mips_arg_info *arg,
a92713e6 5245 const struct mips_operand *operand)
a1d78564
RS
5246{
5247 unsigned int regno;
5248
a92713e6
RS
5249 if (!match_reg (arg, OP_REG_GP, &regno))
5250 return FALSE;
a1d78564 5251
a1d78564 5252 insn_insert_operand (arg->insn, operand, regno | (regno << 5));
a92713e6 5253 return TRUE;
a1d78564
RS
5254}
5255
7361da2c
AB
5256/* OP_CHECK_PREV matcher. */
5257
5258static bfd_boolean
5259match_check_prev_operand (struct mips_arg_info *arg,
5260 const struct mips_operand *operand_base)
5261{
5262 const struct mips_check_prev_operand *operand;
5263 unsigned int regno;
5264
5265 operand = (const struct mips_check_prev_operand *) operand_base;
5266
5267 if (!match_reg (arg, OP_REG_GP, &regno))
5268 return FALSE;
5269
5270 if (!operand->zero_ok && regno == 0)
5271 return FALSE;
5272
5273 if ((operand->less_than_ok && regno < arg->last_regno)
5274 || (operand->greater_than_ok && regno > arg->last_regno)
5275 || (operand->equal_ok && regno == arg->last_regno))
5276 {
5277 arg->last_regno = regno;
5278 insn_insert_operand (arg->insn, operand_base, regno);
5279 return TRUE;
5280 }
5281
5282 return FALSE;
5283}
5284
5285/* OP_SAME_RS_RT matcher. */
5286
5287static bfd_boolean
5288match_same_rs_rt_operand (struct mips_arg_info *arg,
5289 const struct mips_operand *operand)
5290{
5291 unsigned int regno;
5292
5293 if (!match_reg (arg, OP_REG_GP, &regno))
5294 return FALSE;
5295
5296 if (regno == 0)
5297 {
5298 set_insn_error (arg->argnum, _("the source register must not be $0"));
5299 return FALSE;
5300 }
5301
5302 arg->last_regno = regno;
5303
5304 insn_insert_operand (arg->insn, operand, regno | (regno << 5));
5305 return TRUE;
5306}
5307
a1d78564
RS
5308/* OP_LWM_SWM_LIST matcher. */
5309
a92713e6 5310static bfd_boolean
a1d78564 5311match_lwm_swm_list_operand (struct mips_arg_info *arg,
a92713e6 5312 const struct mips_operand *operand)
a1d78564 5313{
a92713e6
RS
5314 unsigned int reglist, sregs, ra, regno1, regno2;
5315 struct mips_arg_info reset;
a1d78564 5316
a92713e6
RS
5317 reglist = 0;
5318 if (!match_reg_range (arg, OP_REG_GP, &regno1, &regno2))
5319 return FALSE;
5320 do
5321 {
5322 if (regno2 == FP && regno1 >= S0 && regno1 <= S7)
5323 {
5324 reglist |= 1 << FP;
5325 regno2 = S7;
5326 }
5327 reglist |= ((1U << regno2 << 1) - 1) & -(1U << regno1);
5328 reset = *arg;
5329 }
5330 while (match_char (arg, ',')
5331 && match_reg_range (arg, OP_REG_GP, &regno1, &regno2));
5332 *arg = reset;
a1d78564
RS
5333
5334 if (operand->size == 2)
5335 {
5336 /* The list must include both ra and s0-sN, for 0 <= N <= 3. E.g.:
5337
5338 s0, ra
5339 s0, s1, ra, s2, s3
5340 s0-s2, ra
5341
5342 and any permutations of these. */
5343 if ((reglist & 0xfff1ffff) != 0x80010000)
a92713e6 5344 return FALSE;
a1d78564
RS
5345
5346 sregs = (reglist >> 17) & 7;
5347 ra = 0;
5348 }
5349 else
5350 {
5351 /* The list must include at least one of ra and s0-sN,
5352 for 0 <= N <= 8. (Note that there is a gap between s7 and s8,
5353 which are $23 and $30 respectively.) E.g.:
5354
5355 ra
5356 s0
5357 ra, s0, s1, s2
5358 s0-s8
5359 s0-s5, ra
5360
5361 and any permutations of these. */
5362 if ((reglist & 0x3f00ffff) != 0)
a92713e6 5363 return FALSE;
a1d78564
RS
5364
5365 ra = (reglist >> 27) & 0x10;
5366 sregs = ((reglist >> 22) & 0x100) | ((reglist >> 16) & 0xff);
5367 }
5368 sregs += 1;
5369 if ((sregs & -sregs) != sregs)
a92713e6 5370 return FALSE;
a1d78564
RS
5371
5372 insn_insert_operand (arg->insn, operand, (ffs (sregs) - 1) | ra);
a92713e6 5373 return TRUE;
a1d78564
RS
5374}
5375
364215c8
RS
5376/* OP_ENTRY_EXIT_LIST matcher. */
5377
a92713e6 5378static unsigned int
364215c8 5379match_entry_exit_operand (struct mips_arg_info *arg,
a92713e6 5380 const struct mips_operand *operand)
364215c8
RS
5381{
5382 unsigned int mask;
5383 bfd_boolean is_exit;
5384
5385 /* The format is the same for both ENTRY and EXIT, but the constraints
5386 are different. */
5387 is_exit = strcmp (arg->insn->insn_mo->name, "exit") == 0;
5388 mask = (is_exit ? 7 << 3 : 0);
a92713e6 5389 do
364215c8
RS
5390 {
5391 unsigned int regno1, regno2;
5392 bfd_boolean is_freg;
5393
a92713e6 5394 if (match_reg_range (arg, OP_REG_GP, &regno1, &regno2))
364215c8 5395 is_freg = FALSE;
a92713e6 5396 else if (match_reg_range (arg, OP_REG_FP, &regno1, &regno2))
364215c8
RS
5397 is_freg = TRUE;
5398 else
a92713e6 5399 return FALSE;
364215c8
RS
5400
5401 if (is_exit && is_freg && regno1 == 0 && regno2 < 2)
5402 {
5403 mask &= ~(7 << 3);
5404 mask |= (5 + regno2) << 3;
5405 }
5406 else if (!is_exit && regno1 == 4 && regno2 >= 4 && regno2 <= 7)
5407 mask |= (regno2 - 3) << 3;
5408 else if (regno1 == 16 && regno2 >= 16 && regno2 <= 17)
5409 mask |= (regno2 - 15) << 1;
5410 else if (regno1 == RA && regno2 == RA)
5411 mask |= 1;
5412 else
a92713e6 5413 return FALSE;
364215c8 5414 }
a92713e6
RS
5415 while (match_char (arg, ','));
5416
364215c8 5417 insn_insert_operand (arg->insn, operand, mask);
a92713e6 5418 return TRUE;
364215c8
RS
5419}
5420
5421/* OP_SAVE_RESTORE_LIST matcher. */
5422
a92713e6
RS
5423static bfd_boolean
5424match_save_restore_list_operand (struct mips_arg_info *arg)
364215c8
RS
5425{
5426 unsigned int opcode, args, statics, sregs;
5427 unsigned int num_frame_sizes, num_args, num_statics, num_sregs;
364215c8 5428 offsetT frame_size;
364215c8 5429
364215c8
RS
5430 opcode = arg->insn->insn_opcode;
5431 frame_size = 0;
5432 num_frame_sizes = 0;
5433 args = 0;
5434 statics = 0;
5435 sregs = 0;
a92713e6 5436 do
364215c8
RS
5437 {
5438 unsigned int regno1, regno2;
5439
a92713e6 5440 if (arg->token->type == OT_INTEGER)
364215c8
RS
5441 {
5442 /* Handle the frame size. */
1a00e612 5443 if (!match_const_int (arg, &frame_size))
a92713e6 5444 return FALSE;
364215c8 5445 num_frame_sizes += 1;
364215c8
RS
5446 }
5447 else
5448 {
a92713e6
RS
5449 if (!match_reg_range (arg, OP_REG_GP, &regno1, &regno2))
5450 return FALSE;
364215c8
RS
5451
5452 while (regno1 <= regno2)
5453 {
5454 if (regno1 >= 4 && regno1 <= 7)
5455 {
5456 if (num_frame_sizes == 0)
5457 /* args $a0-$a3 */
5458 args |= 1 << (regno1 - 4);
5459 else
5460 /* statics $a0-$a3 */
5461 statics |= 1 << (regno1 - 4);
5462 }
5463 else if (regno1 >= 16 && regno1 <= 23)
5464 /* $s0-$s7 */
5465 sregs |= 1 << (regno1 - 16);
5466 else if (regno1 == 30)
5467 /* $s8 */
5468 sregs |= 1 << 8;
5469 else if (regno1 == 31)
5470 /* Add $ra to insn. */
5471 opcode |= 0x40;
5472 else
a92713e6 5473 return FALSE;
364215c8
RS
5474 regno1 += 1;
5475 if (regno1 == 24)
5476 regno1 = 30;
5477 }
5478 }
364215c8 5479 }
a92713e6 5480 while (match_char (arg, ','));
364215c8
RS
5481
5482 /* Encode args/statics combination. */
5483 if (args & statics)
a92713e6 5484 return FALSE;
364215c8
RS
5485 else if (args == 0xf)
5486 /* All $a0-$a3 are args. */
5487 opcode |= MIPS16_ALL_ARGS << 16;
5488 else if (statics == 0xf)
5489 /* All $a0-$a3 are statics. */
5490 opcode |= MIPS16_ALL_STATICS << 16;
5491 else
5492 {
5493 /* Count arg registers. */
5494 num_args = 0;
5495 while (args & 0x1)
5496 {
5497 args >>= 1;
5498 num_args += 1;
5499 }
5500 if (args != 0)
a92713e6 5501 return FALSE;
364215c8
RS
5502
5503 /* Count static registers. */
5504 num_statics = 0;
5505 while (statics & 0x8)
5506 {
5507 statics = (statics << 1) & 0xf;
5508 num_statics += 1;
5509 }
5510 if (statics != 0)
a92713e6 5511 return FALSE;
364215c8
RS
5512
5513 /* Encode args/statics. */
5514 opcode |= ((num_args << 2) | num_statics) << 16;
5515 }
5516
5517 /* Encode $s0/$s1. */
5518 if (sregs & (1 << 0)) /* $s0 */
5519 opcode |= 0x20;
5520 if (sregs & (1 << 1)) /* $s1 */
5521 opcode |= 0x10;
5522 sregs >>= 2;
5523
5524 /* Encode $s2-$s8. */
5525 num_sregs = 0;
5526 while (sregs & 1)
5527 {
5528 sregs >>= 1;
5529 num_sregs += 1;
5530 }
5531 if (sregs != 0)
a92713e6 5532 return FALSE;
364215c8
RS
5533 opcode |= num_sregs << 24;
5534
5535 /* Encode frame size. */
5536 if (num_frame_sizes == 0)
1a00e612
RS
5537 {
5538 set_insn_error (arg->argnum, _("missing frame size"));
5539 return FALSE;
5540 }
5541 if (num_frame_sizes > 1)
5542 {
5543 set_insn_error (arg->argnum, _("frame size specified twice"));
5544 return FALSE;
5545 }
5546 if ((frame_size & 7) != 0 || frame_size < 0 || frame_size > 0xff * 8)
5547 {
5548 set_insn_error (arg->argnum, _("invalid frame size"));
5549 return FALSE;
5550 }
5551 if (frame_size != 128 || (opcode >> 16) != 0)
364215c8
RS
5552 {
5553 frame_size /= 8;
5554 opcode |= (((frame_size & 0xf0) << 16)
5555 | (frame_size & 0x0f));
5556 }
5557
364215c8
RS
5558 /* Finally build the instruction. */
5559 if ((opcode >> 16) != 0 || frame_size == 0)
5560 opcode |= MIPS16_EXTEND;
5561 arg->insn->insn_opcode = opcode;
a92713e6 5562 return TRUE;
364215c8
RS
5563}
5564
a1d78564
RS
5565/* OP_MDMX_IMM_REG matcher. */
5566
a92713e6 5567static bfd_boolean
a1d78564 5568match_mdmx_imm_reg_operand (struct mips_arg_info *arg,
a92713e6 5569 const struct mips_operand *operand)
a1d78564 5570{
a92713e6 5571 unsigned int regno, uval;
a1d78564
RS
5572 bfd_boolean is_qh;
5573 const struct mips_opcode *opcode;
5574
5575 /* The mips_opcode records whether this is an octobyte or quadhalf
5576 instruction. Start out with that bit in place. */
5577 opcode = arg->insn->insn_mo;
5578 uval = mips_extract_operand (operand, opcode->match);
5579 is_qh = (uval != 0);
5580
56d438b1 5581 if (arg->token->type == OT_REG)
a1d78564
RS
5582 {
5583 if ((opcode->membership & INSN_5400)
5584 && strcmp (opcode->name, "rzu.ob") == 0)
5585 {
1a00e612
RS
5586 set_insn_error_i (arg->argnum, _("operand %d must be an immediate"),
5587 arg->argnum);
5588 return FALSE;
a1d78564
RS
5589 }
5590
56d438b1
CF
5591 if (!match_regno (arg, OP_REG_VEC, arg->token->u.regno, &regno))
5592 return FALSE;
5593 ++arg->token;
5594
a1d78564
RS
5595 /* Check whether this is a vector register or a broadcast of
5596 a single element. */
56d438b1 5597 if (arg->token->type == OT_INTEGER_INDEX)
a1d78564 5598 {
56d438b1 5599 if (arg->token->u.index > (is_qh ? 3 : 7))
a1d78564 5600 {
1a00e612
RS
5601 set_insn_error (arg->argnum, _("invalid element selector"));
5602 return FALSE;
a1d78564 5603 }
56d438b1
CF
5604 uval |= arg->token->u.index << (is_qh ? 2 : 1) << 5;
5605 ++arg->token;
a1d78564
RS
5606 }
5607 else
5608 {
5609 /* A full vector. */
5610 if ((opcode->membership & INSN_5400)
5611 && (strcmp (opcode->name, "sll.ob") == 0
5612 || strcmp (opcode->name, "srl.ob") == 0))
5613 {
1a00e612
RS
5614 set_insn_error_i (arg->argnum, _("operand %d must be scalar"),
5615 arg->argnum);
5616 return FALSE;
a1d78564
RS
5617 }
5618
5619 if (is_qh)
5620 uval |= MDMX_FMTSEL_VEC_QH << 5;
5621 else
5622 uval |= MDMX_FMTSEL_VEC_OB << 5;
5623 }
a1d78564
RS
5624 uval |= regno;
5625 }
5626 else
5627 {
5628 offsetT sval;
5629
1a00e612 5630 if (!match_const_int (arg, &sval))
a92713e6 5631 return FALSE;
a1d78564
RS
5632 if (sval < 0 || sval > 31)
5633 {
1a00e612
RS
5634 match_out_of_range (arg);
5635 return FALSE;
a1d78564
RS
5636 }
5637 uval |= (sval & 31);
5638 if (is_qh)
5639 uval |= MDMX_FMTSEL_IMM_QH << 5;
5640 else
5641 uval |= MDMX_FMTSEL_IMM_OB << 5;
5642 }
5643 insn_insert_operand (arg->insn, operand, uval);
a92713e6 5644 return TRUE;
a1d78564
RS
5645}
5646
56d438b1
CF
5647/* OP_IMM_INDEX matcher. */
5648
5649static bfd_boolean
5650match_imm_index_operand (struct mips_arg_info *arg,
5651 const struct mips_operand *operand)
5652{
5653 unsigned int max_val;
5654
5655 if (arg->token->type != OT_INTEGER_INDEX)
5656 return FALSE;
5657
5658 max_val = (1 << operand->size) - 1;
5659 if (arg->token->u.index > max_val)
5660 {
5661 match_out_of_range (arg);
5662 return FALSE;
5663 }
5664 insn_insert_operand (arg->insn, operand, arg->token->u.index);
5665 ++arg->token;
5666 return TRUE;
5667}
5668
5669/* OP_REG_INDEX matcher. */
5670
5671static bfd_boolean
5672match_reg_index_operand (struct mips_arg_info *arg,
5673 const struct mips_operand *operand)
5674{
5675 unsigned int regno;
5676
5677 if (arg->token->type != OT_REG_INDEX)
5678 return FALSE;
5679
5680 if (!match_regno (arg, OP_REG_GP, arg->token->u.regno, &regno))
5681 return FALSE;
5682
5683 insn_insert_operand (arg->insn, operand, regno);
5684 ++arg->token;
5685 return TRUE;
5686}
5687
a1d78564
RS
5688/* OP_PC matcher. */
5689
a92713e6
RS
5690static bfd_boolean
5691match_pc_operand (struct mips_arg_info *arg)
a1d78564 5692{
a92713e6
RS
5693 if (arg->token->type == OT_REG && (arg->token->u.regno & RTYPE_PC))
5694 {
5695 ++arg->token;
5696 return TRUE;
5697 }
5698 return FALSE;
a1d78564
RS
5699}
5700
7361da2c
AB
5701/* OP_NON_ZERO_REG matcher. */
5702
5703static bfd_boolean
5704match_non_zero_reg_operand (struct mips_arg_info *arg,
5705 const struct mips_operand *operand)
5706{
5707 unsigned int regno;
5708
5709 if (!match_reg (arg, OP_REG_GP, &regno))
5710 return FALSE;
5711
5712 if (regno == 0)
5713 return FALSE;
5714
5715 arg->last_regno = regno;
5716 insn_insert_operand (arg->insn, operand, regno);
5717 return TRUE;
5718}
5719
a1d78564
RS
5720/* OP_REPEAT_DEST_REG and OP_REPEAT_PREV_REG matcher. OTHER_REGNO is the
5721 register that we need to match. */
5722
a92713e6
RS
5723static bfd_boolean
5724match_tied_reg_operand (struct mips_arg_info *arg, unsigned int other_regno)
a1d78564
RS
5725{
5726 unsigned int regno;
5727
a92713e6 5728 return match_reg (arg, OP_REG_GP, &regno) && regno == other_regno;
a1d78564
RS
5729}
5730
89565f1b
RS
5731/* Read a floating-point constant from S for LI.S or LI.D. LENGTH is
5732 the length of the value in bytes (4 for float, 8 for double) and
5733 USING_GPRS says whether the destination is a GPR rather than an FPR.
5734
5735 Return the constant in IMM and OFFSET as follows:
5736
5737 - If the constant should be loaded via memory, set IMM to O_absent and
5738 OFFSET to the memory address.
5739
5740 - Otherwise, if the constant should be loaded into two 32-bit registers,
5741 set IMM to the O_constant to load into the high register and OFFSET
5742 to the corresponding value for the low register.
5743
5744 - Otherwise, set IMM to the full O_constant and set OFFSET to O_absent.
5745
5746 These constants only appear as the last operand in an instruction,
5747 and every instruction that accepts them in any variant accepts them
5748 in all variants. This means we don't have to worry about backing out
5749 any changes if the instruction does not match. We just match
5750 unconditionally and report an error if the constant is invalid. */
5751
a92713e6
RS
5752static bfd_boolean
5753match_float_constant (struct mips_arg_info *arg, expressionS *imm,
5754 expressionS *offset, int length, bfd_boolean using_gprs)
89565f1b 5755{
a92713e6 5756 char *p;
89565f1b
RS
5757 segT seg, new_seg;
5758 subsegT subseg;
5759 const char *newname;
a92713e6 5760 unsigned char *data;
89565f1b
RS
5761
5762 /* Where the constant is placed is based on how the MIPS assembler
5763 does things:
5764
5765 length == 4 && using_gprs -- immediate value only
5766 length == 8 && using_gprs -- .rdata or immediate value
5767 length == 4 && !using_gprs -- .lit4 or immediate value
5768 length == 8 && !using_gprs -- .lit8 or immediate value
5769
5770 The .lit4 and .lit8 sections are only used if permitted by the
5771 -G argument. */
a92713e6 5772 if (arg->token->type != OT_FLOAT)
1a00e612
RS
5773 {
5774 set_insn_error (arg->argnum, _("floating-point expression required"));
5775 return FALSE;
5776 }
a92713e6
RS
5777
5778 gas_assert (arg->token->u.flt.length == length);
5779 data = arg->token->u.flt.data;
5780 ++arg->token;
89565f1b
RS
5781
5782 /* Handle 32-bit constants for which an immediate value is best. */
5783 if (length == 4
5784 && (using_gprs
5785 || g_switch_value < 4
5786 || (data[0] == 0 && data[1] == 0)
5787 || (data[2] == 0 && data[3] == 0)))
5788 {
5789 imm->X_op = O_constant;
5790 if (!target_big_endian)
5791 imm->X_add_number = bfd_getl32 (data);
5792 else
5793 imm->X_add_number = bfd_getb32 (data);
5794 offset->X_op = O_absent;
a92713e6 5795 return TRUE;
89565f1b
RS
5796 }
5797
5798 /* Handle 64-bit constants for which an immediate value is best. */
5799 if (length == 8
5800 && !mips_disable_float_construction
351cdf24
MF
5801 /* Constants can only be constructed in GPRs and copied to FPRs if the
5802 GPRs are at least as wide as the FPRs or MTHC1 is available.
5803 Unlike most tests for 32-bit floating-point registers this check
5804 specifically looks for GPR_SIZE == 32 as the FPXX ABI does not
5805 permit 64-bit moves without MXHC1.
5806 Force the constant into memory otherwise. */
5807 && (using_gprs
5808 || GPR_SIZE == 64
5809 || ISA_HAS_MXHC1 (mips_opts.isa)
5810 || FPR_SIZE == 32)
89565f1b
RS
5811 && ((data[0] == 0 && data[1] == 0)
5812 || (data[2] == 0 && data[3] == 0))
5813 && ((data[4] == 0 && data[5] == 0)
5814 || (data[6] == 0 && data[7] == 0)))
5815 {
5816 /* The value is simple enough to load with a couple of instructions.
5817 If using 32-bit registers, set IMM to the high order 32 bits and
5818 OFFSET to the low order 32 bits. Otherwise, set IMM to the entire
5819 64 bit constant. */
351cdf24 5820 if (GPR_SIZE == 32 || (!using_gprs && FPR_SIZE != 64))
89565f1b
RS
5821 {
5822 imm->X_op = O_constant;
5823 offset->X_op = O_constant;
5824 if (!target_big_endian)
5825 {
5826 imm->X_add_number = bfd_getl32 (data + 4);
5827 offset->X_add_number = bfd_getl32 (data);
5828 }
5829 else
5830 {
5831 imm->X_add_number = bfd_getb32 (data);
5832 offset->X_add_number = bfd_getb32 (data + 4);
5833 }
5834 if (offset->X_add_number == 0)
5835 offset->X_op = O_absent;
5836 }
5837 else
5838 {
5839 imm->X_op = O_constant;
5840 if (!target_big_endian)
5841 imm->X_add_number = bfd_getl64 (data);
5842 else
5843 imm->X_add_number = bfd_getb64 (data);
5844 offset->X_op = O_absent;
5845 }
a92713e6 5846 return TRUE;
89565f1b
RS
5847 }
5848
5849 /* Switch to the right section. */
5850 seg = now_seg;
5851 subseg = now_subseg;
5852 if (length == 4)
5853 {
5854 gas_assert (!using_gprs && g_switch_value >= 4);
5855 newname = ".lit4";
5856 }
5857 else
5858 {
5859 if (using_gprs || g_switch_value < 8)
5860 newname = RDATA_SECTION_NAME;
5861 else
5862 newname = ".lit8";
5863 }
5864
5865 new_seg = subseg_new (newname, (subsegT) 0);
5866 bfd_set_section_flags (stdoutput, new_seg,
5867 SEC_ALLOC | SEC_LOAD | SEC_READONLY | SEC_DATA);
5868 frag_align (length == 4 ? 2 : 3, 0, 0);
5869 if (strncmp (TARGET_OS, "elf", 3) != 0)
5870 record_alignment (new_seg, 4);
5871 else
5872 record_alignment (new_seg, length == 4 ? 2 : 3);
5873 if (seg == now_seg)
1661c76c 5874 as_bad (_("cannot use `%s' in this section"), arg->insn->insn_mo->name);
89565f1b
RS
5875
5876 /* Set the argument to the current address in the section. */
5877 imm->X_op = O_absent;
5878 offset->X_op = O_symbol;
5879 offset->X_add_symbol = symbol_temp_new_now ();
5880 offset->X_add_number = 0;
5881
5882 /* Put the floating point number into the section. */
5883 p = frag_more (length);
5884 memcpy (p, data, length);
5885
5886 /* Switch back to the original section. */
5887 subseg_set (seg, subseg);
a92713e6 5888 return TRUE;
89565f1b
RS
5889}
5890
14daeee3
RS
5891/* OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX matcher; MATCH_P selects between
5892 them. */
5893
5894static bfd_boolean
5895match_vu0_suffix_operand (struct mips_arg_info *arg,
5896 const struct mips_operand *operand,
5897 bfd_boolean match_p)
5898{
5899 unsigned int uval;
5900
5901 /* The operand can be an XYZW mask or a single 2-bit channel index
5902 (with X being 0). */
5903 gas_assert (operand->size == 2 || operand->size == 4);
5904
ee5734f0 5905 /* The suffix can be omitted when it is already part of the opcode. */
14daeee3 5906 if (arg->token->type != OT_CHANNELS)
ee5734f0 5907 return match_p;
14daeee3
RS
5908
5909 uval = arg->token->u.channels;
5910 if (operand->size == 2)
5911 {
5912 /* Check that a single bit is set and convert it into a 2-bit index. */
5913 if ((uval & -uval) != uval)
5914 return FALSE;
5915 uval = 4 - ffs (uval);
5916 }
5917
5918 if (match_p && insn_extract_operand (arg->insn, operand) != uval)
5919 return FALSE;
5920
5921 ++arg->token;
5922 if (!match_p)
5923 insn_insert_operand (arg->insn, operand, uval);
5924 return TRUE;
5925}
5926
a1d78564
RS
5927/* S is the text seen for ARG. Match it against OPERAND. Return the end
5928 of the argument text if the match is successful, otherwise return null. */
5929
a92713e6 5930static bfd_boolean
a1d78564 5931match_operand (struct mips_arg_info *arg,
a92713e6 5932 const struct mips_operand *operand)
a1d78564
RS
5933{
5934 switch (operand->type)
5935 {
5936 case OP_INT:
a92713e6 5937 return match_int_operand (arg, operand);
a1d78564
RS
5938
5939 case OP_MAPPED_INT:
a92713e6 5940 return match_mapped_int_operand (arg, operand);
a1d78564
RS
5941
5942 case OP_MSB:
a92713e6 5943 return match_msb_operand (arg, operand);
a1d78564
RS
5944
5945 case OP_REG:
0f35dbc4 5946 case OP_OPTIONAL_REG:
a92713e6 5947 return match_reg_operand (arg, operand);
a1d78564
RS
5948
5949 case OP_REG_PAIR:
a92713e6 5950 return match_reg_pair_operand (arg, operand);
a1d78564
RS
5951
5952 case OP_PCREL:
a92713e6 5953 return match_pcrel_operand (arg);
a1d78564
RS
5954
5955 case OP_PERF_REG:
a92713e6 5956 return match_perf_reg_operand (arg, operand);
a1d78564
RS
5957
5958 case OP_ADDIUSP_INT:
a92713e6 5959 return match_addiusp_operand (arg, operand);
a1d78564
RS
5960
5961 case OP_CLO_CLZ_DEST:
a92713e6 5962 return match_clo_clz_dest_operand (arg, operand);
a1d78564
RS
5963
5964 case OP_LWM_SWM_LIST:
a92713e6 5965 return match_lwm_swm_list_operand (arg, operand);
a1d78564
RS
5966
5967 case OP_ENTRY_EXIT_LIST:
a92713e6 5968 return match_entry_exit_operand (arg, operand);
364215c8 5969
a1d78564 5970 case OP_SAVE_RESTORE_LIST:
a92713e6 5971 return match_save_restore_list_operand (arg);
a1d78564
RS
5972
5973 case OP_MDMX_IMM_REG:
a92713e6 5974 return match_mdmx_imm_reg_operand (arg, operand);
a1d78564
RS
5975
5976 case OP_REPEAT_DEST_REG:
a92713e6 5977 return match_tied_reg_operand (arg, arg->dest_regno);
a1d78564
RS
5978
5979 case OP_REPEAT_PREV_REG:
a92713e6 5980 return match_tied_reg_operand (arg, arg->last_regno);
a1d78564
RS
5981
5982 case OP_PC:
a92713e6 5983 return match_pc_operand (arg);
14daeee3
RS
5984
5985 case OP_VU0_SUFFIX:
5986 return match_vu0_suffix_operand (arg, operand, FALSE);
5987
5988 case OP_VU0_MATCH_SUFFIX:
5989 return match_vu0_suffix_operand (arg, operand, TRUE);
56d438b1
CF
5990
5991 case OP_IMM_INDEX:
5992 return match_imm_index_operand (arg, operand);
5993
5994 case OP_REG_INDEX:
5995 return match_reg_index_operand (arg, operand);
7361da2c
AB
5996
5997 case OP_SAME_RS_RT:
5998 return match_same_rs_rt_operand (arg, operand);
5999
6000 case OP_CHECK_PREV:
6001 return match_check_prev_operand (arg, operand);
6002
6003 case OP_NON_ZERO_REG:
6004 return match_non_zero_reg_operand (arg, operand);
a1d78564
RS
6005 }
6006 abort ();
6007}
6008
6009/* ARG is the state after successfully matching an instruction.
6010 Issue any queued-up warnings. */
6011
6012static void
6013check_completed_insn (struct mips_arg_info *arg)
6014{
6015 if (arg->seen_at)
6016 {
6017 if (AT == ATREG)
1661c76c 6018 as_warn (_("used $at without \".set noat\""));
a1d78564 6019 else
1661c76c 6020 as_warn (_("used $%u with \".set at=$%u\""), AT, AT);
a1d78564
RS
6021 }
6022}
a1d78564 6023
85fcb30f
RS
6024/* Return true if modifying general-purpose register REG needs a delay. */
6025
6026static bfd_boolean
6027reg_needs_delay (unsigned int reg)
6028{
6029 unsigned long prev_pinfo;
6030
6031 prev_pinfo = history[0].insn_mo->pinfo;
6032 if (!mips_opts.noreorder
67dc82bc 6033 && (((prev_pinfo & INSN_LOAD_MEMORY) && !gpr_interlocks)
43885403 6034 || ((prev_pinfo & INSN_LOAD_COPROC) && !cop_interlocks))
85fcb30f
RS
6035 && (gpr_write_mask (&history[0]) & (1 << reg)))
6036 return TRUE;
6037
6038 return FALSE;
6039}
6040
71400594
RS
6041/* Classify an instruction according to the FIX_VR4120_* enumeration.
6042 Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected
6043 by VR4120 errata. */
4d7206a2 6044
71400594
RS
6045static unsigned int
6046classify_vr4120_insn (const char *name)
252b5132 6047{
71400594
RS
6048 if (strncmp (name, "macc", 4) == 0)
6049 return FIX_VR4120_MACC;
6050 if (strncmp (name, "dmacc", 5) == 0)
6051 return FIX_VR4120_DMACC;
6052 if (strncmp (name, "mult", 4) == 0)
6053 return FIX_VR4120_MULT;
6054 if (strncmp (name, "dmult", 5) == 0)
6055 return FIX_VR4120_DMULT;
6056 if (strstr (name, "div"))
6057 return FIX_VR4120_DIV;
6058 if (strcmp (name, "mtlo") == 0 || strcmp (name, "mthi") == 0)
6059 return FIX_VR4120_MTHILO;
6060 return NUM_FIX_VR4120_CLASSES;
6061}
252b5132 6062
a8d14a88
CM
6063#define INSN_ERET 0x42000018
6064#define INSN_DERET 0x4200001f
6065#define INSN_DMULT 0x1c
6066#define INSN_DMULTU 0x1d
ff239038 6067
71400594
RS
6068/* Return the number of instructions that must separate INSN1 and INSN2,
6069 where INSN1 is the earlier instruction. Return the worst-case value
6070 for any INSN2 if INSN2 is null. */
252b5132 6071
71400594
RS
6072static unsigned int
6073insns_between (const struct mips_cl_insn *insn1,
6074 const struct mips_cl_insn *insn2)
6075{
6076 unsigned long pinfo1, pinfo2;
4c260379 6077 unsigned int mask;
71400594 6078
85fcb30f
RS
6079 /* If INFO2 is null, pessimistically assume that all flags are set for
6080 the second instruction. */
71400594
RS
6081 pinfo1 = insn1->insn_mo->pinfo;
6082 pinfo2 = insn2 ? insn2->insn_mo->pinfo : ~0U;
252b5132 6083
71400594
RS
6084 /* For most targets, write-after-read dependencies on the HI and LO
6085 registers must be separated by at least two instructions. */
6086 if (!hilo_interlocks)
252b5132 6087 {
71400594
RS
6088 if ((pinfo1 & INSN_READ_LO) && (pinfo2 & INSN_WRITE_LO))
6089 return 2;
6090 if ((pinfo1 & INSN_READ_HI) && (pinfo2 & INSN_WRITE_HI))
6091 return 2;
6092 }
6093
6094 /* If we're working around r7000 errata, there must be two instructions
6095 between an mfhi or mflo and any instruction that uses the result. */
6096 if (mips_7000_hilo_fix
df58fc94 6097 && !mips_opts.micromips
71400594 6098 && MF_HILO_INSN (pinfo1)
85fcb30f 6099 && (insn2 == NULL || (gpr_read_mask (insn2) & gpr_write_mask (insn1))))
71400594
RS
6100 return 2;
6101
ff239038
CM
6102 /* If we're working around 24K errata, one instruction is required
6103 if an ERET or DERET is followed by a branch instruction. */
df58fc94 6104 if (mips_fix_24k && !mips_opts.micromips)
ff239038
CM
6105 {
6106 if (insn1->insn_opcode == INSN_ERET
6107 || insn1->insn_opcode == INSN_DERET)
6108 {
6109 if (insn2 == NULL
6110 || insn2->insn_opcode == INSN_ERET
6111 || insn2->insn_opcode == INSN_DERET
11625dd8 6112 || delayed_branch_p (insn2))
ff239038
CM
6113 return 1;
6114 }
6115 }
6116
a8d14a88
CM
6117 /* If we're working around PMC RM7000 errata, there must be three
6118 nops between a dmult and a load instruction. */
6119 if (mips_fix_rm7000 && !mips_opts.micromips)
6120 {
6121 if ((insn1->insn_opcode & insn1->insn_mo->mask) == INSN_DMULT
6122 || (insn1->insn_opcode & insn1->insn_mo->mask) == INSN_DMULTU)
6123 {
6124 if (pinfo2 & INSN_LOAD_MEMORY)
6125 return 3;
6126 }
6127 }
6128
71400594
RS
6129 /* If working around VR4120 errata, check for combinations that need
6130 a single intervening instruction. */
df58fc94 6131 if (mips_fix_vr4120 && !mips_opts.micromips)
71400594
RS
6132 {
6133 unsigned int class1, class2;
252b5132 6134
71400594
RS
6135 class1 = classify_vr4120_insn (insn1->insn_mo->name);
6136 if (class1 != NUM_FIX_VR4120_CLASSES && vr4120_conflicts[class1] != 0)
252b5132 6137 {
71400594
RS
6138 if (insn2 == NULL)
6139 return 1;
6140 class2 = classify_vr4120_insn (insn2->insn_mo->name);
6141 if (vr4120_conflicts[class1] & (1 << class2))
6142 return 1;
252b5132 6143 }
71400594
RS
6144 }
6145
df58fc94 6146 if (!HAVE_CODE_COMPRESSION)
71400594
RS
6147 {
6148 /* Check for GPR or coprocessor load delays. All such delays
6149 are on the RT register. */
6150 /* Itbl support may require additional care here. */
67dc82bc 6151 if ((!gpr_interlocks && (pinfo1 & INSN_LOAD_MEMORY))
43885403 6152 || (!cop_interlocks && (pinfo1 & INSN_LOAD_COPROC)))
252b5132 6153 {
85fcb30f 6154 if (insn2 == NULL || (gpr_read_mask (insn2) & gpr_write_mask (insn1)))
71400594
RS
6155 return 1;
6156 }
6157
6158 /* Check for generic coprocessor hazards.
6159
6160 This case is not handled very well. There is no special
6161 knowledge of CP0 handling, and the coprocessors other than
6162 the floating point unit are not distinguished at all. */
6163 /* Itbl support may require additional care here. FIXME!
6164 Need to modify this to include knowledge about
6165 user specified delays! */
43885403 6166 else if ((!cop_interlocks && (pinfo1 & INSN_COPROC_MOVE))
71400594
RS
6167 || (!cop_mem_interlocks && (pinfo1 & INSN_COPROC_MEMORY_DELAY)))
6168 {
6169 /* Handle cases where INSN1 writes to a known general coprocessor
6170 register. There must be a one instruction delay before INSN2
6171 if INSN2 reads that register, otherwise no delay is needed. */
4c260379
RS
6172 mask = fpr_write_mask (insn1);
6173 if (mask != 0)
252b5132 6174 {
4c260379 6175 if (!insn2 || (mask & fpr_read_mask (insn2)) != 0)
71400594 6176 return 1;
252b5132
RH
6177 }
6178 else
6179 {
71400594
RS
6180 /* Read-after-write dependencies on the control registers
6181 require a two-instruction gap. */
6182 if ((pinfo1 & INSN_WRITE_COND_CODE)
6183 && (pinfo2 & INSN_READ_COND_CODE))
6184 return 2;
6185
6186 /* We don't know exactly what INSN1 does. If INSN2 is
6187 also a coprocessor instruction, assume there must be
6188 a one instruction gap. */
6189 if (pinfo2 & INSN_COP)
6190 return 1;
252b5132
RH
6191 }
6192 }
6b76fefe 6193
71400594
RS
6194 /* Check for read-after-write dependencies on the coprocessor
6195 control registers in cases where INSN1 does not need a general
6196 coprocessor delay. This means that INSN1 is a floating point
6197 comparison instruction. */
6198 /* Itbl support may require additional care here. */
6199 else if (!cop_interlocks
6200 && (pinfo1 & INSN_WRITE_COND_CODE)
6201 && (pinfo2 & INSN_READ_COND_CODE))
6202 return 1;
6203 }
6b76fefe 6204
7361da2c
AB
6205 /* Forbidden slots can not contain Control Transfer Instructions (CTIs)
6206 CTIs include all branches and jumps, nal, eret, eretnc, deret, wait
6207 and pause. */
6208 if ((insn1->insn_mo->pinfo2 & INSN2_FORBIDDEN_SLOT)
6209 && ((pinfo2 & INSN_NO_DELAY_SLOT)
6210 || (insn2 && delayed_branch_p (insn2))))
6211 return 1;
6212
71400594
RS
6213 return 0;
6214}
6b76fefe 6215
7d8e00cf
RS
6216/* Return the number of nops that would be needed to work around the
6217 VR4130 mflo/mfhi errata if instruction INSN immediately followed
932d1a1b
RS
6218 the MAX_VR4130_NOPS instructions described by HIST. Ignore hazards
6219 that are contained within the first IGNORE instructions of HIST. */
7d8e00cf
RS
6220
6221static int
932d1a1b 6222nops_for_vr4130 (int ignore, const struct mips_cl_insn *hist,
7d8e00cf
RS
6223 const struct mips_cl_insn *insn)
6224{
4c260379
RS
6225 int i, j;
6226 unsigned int mask;
7d8e00cf
RS
6227
6228 /* Check if the instruction writes to HI or LO. MTHI and MTLO
6229 are not affected by the errata. */
6230 if (insn != 0
6231 && ((insn->insn_mo->pinfo & (INSN_WRITE_HI | INSN_WRITE_LO)) == 0
6232 || strcmp (insn->insn_mo->name, "mtlo") == 0
6233 || strcmp (insn->insn_mo->name, "mthi") == 0))
6234 return 0;
6235
6236 /* Search for the first MFLO or MFHI. */
6237 for (i = 0; i < MAX_VR4130_NOPS; i++)
91d6fa6a 6238 if (MF_HILO_INSN (hist[i].insn_mo->pinfo))
7d8e00cf
RS
6239 {
6240 /* Extract the destination register. */
4c260379 6241 mask = gpr_write_mask (&hist[i]);
7d8e00cf
RS
6242
6243 /* No nops are needed if INSN reads that register. */
4c260379 6244 if (insn != NULL && (gpr_read_mask (insn) & mask) != 0)
7d8e00cf
RS
6245 return 0;
6246
6247 /* ...or if any of the intervening instructions do. */
6248 for (j = 0; j < i; j++)
4c260379 6249 if (gpr_read_mask (&hist[j]) & mask)
7d8e00cf
RS
6250 return 0;
6251
932d1a1b
RS
6252 if (i >= ignore)
6253 return MAX_VR4130_NOPS - i;
7d8e00cf
RS
6254 }
6255 return 0;
6256}
6257
15be625d
CM
6258#define BASE_REG_EQ(INSN1, INSN2) \
6259 ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \
6260 == (((INSN2) >> OP_SH_RS) & OP_MASK_RS))
6261
6262/* Return the minimum alignment for this store instruction. */
6263
6264static int
6265fix_24k_align_to (const struct mips_opcode *mo)
6266{
6267 if (strcmp (mo->name, "sh") == 0)
6268 return 2;
6269
6270 if (strcmp (mo->name, "swc1") == 0
6271 || strcmp (mo->name, "swc2") == 0
6272 || strcmp (mo->name, "sw") == 0
6273 || strcmp (mo->name, "sc") == 0
6274 || strcmp (mo->name, "s.s") == 0)
6275 return 4;
6276
6277 if (strcmp (mo->name, "sdc1") == 0
6278 || strcmp (mo->name, "sdc2") == 0
6279 || strcmp (mo->name, "s.d") == 0)
6280 return 8;
6281
6282 /* sb, swl, swr */
6283 return 1;
6284}
6285
6286struct fix_24k_store_info
6287 {
6288 /* Immediate offset, if any, for this store instruction. */
6289 short off;
6290 /* Alignment required by this store instruction. */
6291 int align_to;
6292 /* True for register offsets. */
6293 int register_offset;
6294 };
6295
6296/* Comparison function used by qsort. */
6297
6298static int
6299fix_24k_sort (const void *a, const void *b)
6300{
6301 const struct fix_24k_store_info *pos1 = a;
6302 const struct fix_24k_store_info *pos2 = b;
6303
6304 return (pos1->off - pos2->off);
6305}
6306
6307/* INSN is a store instruction. Try to record the store information
6308 in STINFO. Return false if the information isn't known. */
6309
6310static bfd_boolean
6311fix_24k_record_store_info (struct fix_24k_store_info *stinfo,
ab9794cf 6312 const struct mips_cl_insn *insn)
15be625d
CM
6313{
6314 /* The instruction must have a known offset. */
6315 if (!insn->complete_p || !strstr (insn->insn_mo->args, "o("))
6316 return FALSE;
6317
6318 stinfo->off = (insn->insn_opcode >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE;
6319 stinfo->align_to = fix_24k_align_to (insn->insn_mo);
6320 return TRUE;
6321}
6322
932d1a1b
RS
6323/* Return the number of nops that would be needed to work around the 24k
6324 "lost data on stores during refill" errata if instruction INSN
6325 immediately followed the 2 instructions described by HIST.
6326 Ignore hazards that are contained within the first IGNORE
6327 instructions of HIST.
6328
6329 Problem: The FSB (fetch store buffer) acts as an intermediate buffer
6330 for the data cache refills and store data. The following describes
6331 the scenario where the store data could be lost.
6332
6333 * A data cache miss, due to either a load or a store, causing fill
6334 data to be supplied by the memory subsystem
6335 * The first three doublewords of fill data are returned and written
6336 into the cache
6337 * A sequence of four stores occurs in consecutive cycles around the
6338 final doubleword of the fill:
6339 * Store A
6340 * Store B
6341 * Store C
6342 * Zero, One or more instructions
6343 * Store D
6344
6345 The four stores A-D must be to different doublewords of the line that
6346 is being filled. The fourth instruction in the sequence above permits
6347 the fill of the final doubleword to be transferred from the FSB into
6348 the cache. In the sequence above, the stores may be either integer
6349 (sb, sh, sw, swr, swl, sc) or coprocessor (swc1/swc2, sdc1/sdc2,
6350 swxc1, sdxc1, suxc1) stores, as long as the four stores are to
6351 different doublewords on the line. If the floating point unit is
6352 running in 1:2 mode, it is not possible to create the sequence above
6353 using only floating point store instructions.
15be625d
CM
6354
6355 In this case, the cache line being filled is incorrectly marked
6356 invalid, thereby losing the data from any store to the line that
6357 occurs between the original miss and the completion of the five
6358 cycle sequence shown above.
6359
932d1a1b 6360 The workarounds are:
15be625d 6361
932d1a1b
RS
6362 * Run the data cache in write-through mode.
6363 * Insert a non-store instruction between
6364 Store A and Store B or Store B and Store C. */
15be625d
CM
6365
6366static int
932d1a1b 6367nops_for_24k (int ignore, const struct mips_cl_insn *hist,
15be625d
CM
6368 const struct mips_cl_insn *insn)
6369{
6370 struct fix_24k_store_info pos[3];
6371 int align, i, base_offset;
6372
932d1a1b
RS
6373 if (ignore >= 2)
6374 return 0;
6375
ab9794cf
RS
6376 /* If the previous instruction wasn't a store, there's nothing to
6377 worry about. */
15be625d
CM
6378 if ((hist[0].insn_mo->pinfo & INSN_STORE_MEMORY) == 0)
6379 return 0;
6380
ab9794cf
RS
6381 /* If the instructions after the previous one are unknown, we have
6382 to assume the worst. */
6383 if (!insn)
15be625d
CM
6384 return 1;
6385
ab9794cf
RS
6386 /* Check whether we are dealing with three consecutive stores. */
6387 if ((insn->insn_mo->pinfo & INSN_STORE_MEMORY) == 0
6388 || (hist[1].insn_mo->pinfo & INSN_STORE_MEMORY) == 0)
15be625d
CM
6389 return 0;
6390
6391 /* If we don't know the relationship between the store addresses,
6392 assume the worst. */
ab9794cf 6393 if (!BASE_REG_EQ (insn->insn_opcode, hist[0].insn_opcode)
15be625d
CM
6394 || !BASE_REG_EQ (insn->insn_opcode, hist[1].insn_opcode))
6395 return 1;
6396
6397 if (!fix_24k_record_store_info (&pos[0], insn)
6398 || !fix_24k_record_store_info (&pos[1], &hist[0])
6399 || !fix_24k_record_store_info (&pos[2], &hist[1]))
6400 return 1;
6401
6402 qsort (&pos, 3, sizeof (struct fix_24k_store_info), fix_24k_sort);
6403
6404 /* Pick a value of ALIGN and X such that all offsets are adjusted by
6405 X bytes and such that the base register + X is known to be aligned
6406 to align bytes. */
6407
6408 if (((insn->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == SP)
6409 align = 8;
6410 else
6411 {
6412 align = pos[0].align_to;
6413 base_offset = pos[0].off;
6414 for (i = 1; i < 3; i++)
6415 if (align < pos[i].align_to)
6416 {
6417 align = pos[i].align_to;
6418 base_offset = pos[i].off;
6419 }
6420 for (i = 0; i < 3; i++)
6421 pos[i].off -= base_offset;
6422 }
6423
6424 pos[0].off &= ~align + 1;
6425 pos[1].off &= ~align + 1;
6426 pos[2].off &= ~align + 1;
6427
6428 /* If any two stores write to the same chunk, they also write to the
6429 same doubleword. The offsets are still sorted at this point. */
6430 if (pos[0].off == pos[1].off || pos[1].off == pos[2].off)
6431 return 0;
6432
6433 /* A range of at least 9 bytes is needed for the stores to be in
6434 non-overlapping doublewords. */
6435 if (pos[2].off - pos[0].off <= 8)
6436 return 0;
6437
6438 if (pos[2].off - pos[1].off >= 24
6439 || pos[1].off - pos[0].off >= 24
6440 || pos[2].off - pos[0].off >= 32)
6441 return 0;
6442
6443 return 1;
6444}
6445
71400594 6446/* Return the number of nops that would be needed if instruction INSN
91d6fa6a 6447 immediately followed the MAX_NOPS instructions given by HIST,
932d1a1b
RS
6448 where HIST[0] is the most recent instruction. Ignore hazards
6449 between INSN and the first IGNORE instructions in HIST.
6450
6451 If INSN is null, return the worse-case number of nops for any
6452 instruction. */
bdaaa2e1 6453
71400594 6454static int
932d1a1b 6455nops_for_insn (int ignore, const struct mips_cl_insn *hist,
71400594
RS
6456 const struct mips_cl_insn *insn)
6457{
6458 int i, nops, tmp_nops;
bdaaa2e1 6459
71400594 6460 nops = 0;
932d1a1b 6461 for (i = ignore; i < MAX_DELAY_NOPS; i++)
65b02341 6462 {
91d6fa6a 6463 tmp_nops = insns_between (hist + i, insn) - i;
65b02341
RS
6464 if (tmp_nops > nops)
6465 nops = tmp_nops;
6466 }
7d8e00cf 6467
df58fc94 6468 if (mips_fix_vr4130 && !mips_opts.micromips)
7d8e00cf 6469 {
932d1a1b 6470 tmp_nops = nops_for_vr4130 (ignore, hist, insn);
7d8e00cf
RS
6471 if (tmp_nops > nops)
6472 nops = tmp_nops;
6473 }
6474
df58fc94 6475 if (mips_fix_24k && !mips_opts.micromips)
15be625d 6476 {
932d1a1b 6477 tmp_nops = nops_for_24k (ignore, hist, insn);
15be625d
CM
6478 if (tmp_nops > nops)
6479 nops = tmp_nops;
6480 }
6481
71400594
RS
6482 return nops;
6483}
252b5132 6484
71400594 6485/* The variable arguments provide NUM_INSNS extra instructions that
91d6fa6a 6486 might be added to HIST. Return the largest number of nops that
932d1a1b
RS
6487 would be needed after the extended sequence, ignoring hazards
6488 in the first IGNORE instructions. */
252b5132 6489
71400594 6490static int
932d1a1b
RS
6491nops_for_sequence (int num_insns, int ignore,
6492 const struct mips_cl_insn *hist, ...)
71400594
RS
6493{
6494 va_list args;
6495 struct mips_cl_insn buffer[MAX_NOPS];
6496 struct mips_cl_insn *cursor;
6497 int nops;
6498
91d6fa6a 6499 va_start (args, hist);
71400594 6500 cursor = buffer + num_insns;
91d6fa6a 6501 memcpy (cursor, hist, (MAX_NOPS - num_insns) * sizeof (*cursor));
71400594
RS
6502 while (cursor > buffer)
6503 *--cursor = *va_arg (args, const struct mips_cl_insn *);
6504
932d1a1b 6505 nops = nops_for_insn (ignore, buffer, NULL);
71400594
RS
6506 va_end (args);
6507 return nops;
6508}
252b5132 6509
71400594
RS
6510/* Like nops_for_insn, but if INSN is a branch, take into account the
6511 worst-case delay for the branch target. */
252b5132 6512
71400594 6513static int
932d1a1b 6514nops_for_insn_or_target (int ignore, const struct mips_cl_insn *hist,
71400594
RS
6515 const struct mips_cl_insn *insn)
6516{
6517 int nops, tmp_nops;
60b63b72 6518
932d1a1b 6519 nops = nops_for_insn (ignore, hist, insn);
11625dd8 6520 if (delayed_branch_p (insn))
71400594 6521 {
932d1a1b 6522 tmp_nops = nops_for_sequence (2, ignore ? ignore + 2 : 0,
14fe068b 6523 hist, insn, get_delay_slot_nop (insn));
71400594
RS
6524 if (tmp_nops > nops)
6525 nops = tmp_nops;
6526 }
11625dd8 6527 else if (compact_branch_p (insn))
71400594 6528 {
932d1a1b 6529 tmp_nops = nops_for_sequence (1, ignore ? ignore + 1 : 0, hist, insn);
71400594
RS
6530 if (tmp_nops > nops)
6531 nops = tmp_nops;
6532 }
6533 return nops;
6534}
6535
c67a084a
NC
6536/* Fix NOP issue: Replace nops by "or at,at,zero". */
6537
6538static void
6539fix_loongson2f_nop (struct mips_cl_insn * ip)
6540{
df58fc94 6541 gas_assert (!HAVE_CODE_COMPRESSION);
c67a084a
NC
6542 if (strcmp (ip->insn_mo->name, "nop") == 0)
6543 ip->insn_opcode = LOONGSON2F_NOP_INSN;
6544}
6545
6546/* Fix Jump Issue: Eliminate instruction fetch from outside 256M region
6547 jr target pc &= 'hffff_ffff_cfff_ffff. */
6548
6549static void
6550fix_loongson2f_jump (struct mips_cl_insn * ip)
6551{
df58fc94 6552 gas_assert (!HAVE_CODE_COMPRESSION);
c67a084a
NC
6553 if (strcmp (ip->insn_mo->name, "j") == 0
6554 || strcmp (ip->insn_mo->name, "jr") == 0
6555 || strcmp (ip->insn_mo->name, "jalr") == 0)
6556 {
6557 int sreg;
6558 expressionS ep;
6559
6560 if (! mips_opts.at)
6561 return;
6562
df58fc94 6563 sreg = EXTRACT_OPERAND (0, RS, *ip);
c67a084a
NC
6564 if (sreg == ZERO || sreg == KT0 || sreg == KT1 || sreg == ATREG)
6565 return;
6566
6567 ep.X_op = O_constant;
6568 ep.X_add_number = 0xcfff0000;
6569 macro_build (&ep, "lui", "t,u", ATREG, BFD_RELOC_HI16);
6570 ep.X_add_number = 0xffff;
6571 macro_build (&ep, "ori", "t,r,i", ATREG, ATREG, BFD_RELOC_LO16);
6572 macro_build (NULL, "and", "d,v,t", sreg, sreg, ATREG);
6573 }
6574}
6575
6576static void
6577fix_loongson2f (struct mips_cl_insn * ip)
6578{
6579 if (mips_fix_loongson2f_nop)
6580 fix_loongson2f_nop (ip);
6581
6582 if (mips_fix_loongson2f_jump)
6583 fix_loongson2f_jump (ip);
6584}
6585
a4e06468
RS
6586/* IP is a branch that has a delay slot, and we need to fill it
6587 automatically. Return true if we can do that by swapping IP
e407c74b
NC
6588 with the previous instruction.
6589 ADDRESS_EXPR is an operand of the instruction to be used with
6590 RELOC_TYPE. */
a4e06468
RS
6591
6592static bfd_boolean
e407c74b 6593can_swap_branch_p (struct mips_cl_insn *ip, expressionS *address_expr,
26545944 6594 bfd_reloc_code_real_type *reloc_type)
a4e06468 6595{
2b0c8b40 6596 unsigned long pinfo, pinfo2, prev_pinfo, prev_pinfo2;
a4e06468 6597 unsigned int gpr_read, gpr_write, prev_gpr_read, prev_gpr_write;
9d5de888 6598 unsigned int fpr_read, prev_fpr_write;
a4e06468
RS
6599
6600 /* -O2 and above is required for this optimization. */
6601 if (mips_optimize < 2)
6602 return FALSE;
6603
6604 /* If we have seen .set volatile or .set nomove, don't optimize. */
6605 if (mips_opts.nomove)
6606 return FALSE;
6607
6608 /* We can't swap if the previous instruction's position is fixed. */
6609 if (history[0].fixed_p)
6610 return FALSE;
6611
6612 /* If the previous previous insn was in a .set noreorder, we can't
6613 swap. Actually, the MIPS assembler will swap in this situation.
6614 However, gcc configured -with-gnu-as will generate code like
6615
6616 .set noreorder
6617 lw $4,XXX
6618 .set reorder
6619 INSN
6620 bne $4,$0,foo
6621
6622 in which we can not swap the bne and INSN. If gcc is not configured
6623 -with-gnu-as, it does not output the .set pseudo-ops. */
6624 if (history[1].noreorder_p)
6625 return FALSE;
6626
87333bb7
MR
6627 /* If the previous instruction had a fixup in mips16 mode, we can not swap.
6628 This means that the previous instruction was a 4-byte one anyhow. */
a4e06468
RS
6629 if (mips_opts.mips16 && history[0].fixp[0])
6630 return FALSE;
6631
6632 /* If the branch is itself the target of a branch, we can not swap.
6633 We cheat on this; all we check for is whether there is a label on
6634 this instruction. If there are any branches to anything other than
6635 a label, users must use .set noreorder. */
6636 if (seg_info (now_seg)->label_list)
6637 return FALSE;
6638
6639 /* If the previous instruction is in a variant frag other than this
2309ddf2 6640 branch's one, we cannot do the swap. This does not apply to
9301f9c3
MR
6641 MIPS16 code, which uses variant frags for different purposes. */
6642 if (!mips_opts.mips16
a4e06468
RS
6643 && history[0].frag
6644 && history[0].frag->fr_type == rs_machine_dependent)
6645 return FALSE;
6646
bcd530a7
RS
6647 /* We do not swap with instructions that cannot architecturally
6648 be placed in a branch delay slot, such as SYNC or ERET. We
6649 also refrain from swapping with a trap instruction, since it
6650 complicates trap handlers to have the trap instruction be in
6651 a delay slot. */
a4e06468 6652 prev_pinfo = history[0].insn_mo->pinfo;
bcd530a7 6653 if (prev_pinfo & INSN_NO_DELAY_SLOT)
a4e06468
RS
6654 return FALSE;
6655
6656 /* Check for conflicts between the branch and the instructions
6657 before the candidate delay slot. */
6658 if (nops_for_insn (0, history + 1, ip) > 0)
6659 return FALSE;
6660
6661 /* Check for conflicts between the swapped sequence and the
6662 target of the branch. */
6663 if (nops_for_sequence (2, 0, history + 1, ip, history) > 0)
6664 return FALSE;
6665
6666 /* If the branch reads a register that the previous
6667 instruction sets, we can not swap. */
6668 gpr_read = gpr_read_mask (ip);
6669 prev_gpr_write = gpr_write_mask (&history[0]);
6670 if (gpr_read & prev_gpr_write)
6671 return FALSE;
6672
9d5de888
CF
6673 fpr_read = fpr_read_mask (ip);
6674 prev_fpr_write = fpr_write_mask (&history[0]);
6675 if (fpr_read & prev_fpr_write)
6676 return FALSE;
6677
a4e06468
RS
6678 /* If the branch writes a register that the previous
6679 instruction sets, we can not swap. */
6680 gpr_write = gpr_write_mask (ip);
6681 if (gpr_write & prev_gpr_write)
6682 return FALSE;
6683
6684 /* If the branch writes a register that the previous
6685 instruction reads, we can not swap. */
6686 prev_gpr_read = gpr_read_mask (&history[0]);
6687 if (gpr_write & prev_gpr_read)
6688 return FALSE;
6689
6690 /* If one instruction sets a condition code and the
6691 other one uses a condition code, we can not swap. */
6692 pinfo = ip->insn_mo->pinfo;
6693 if ((pinfo & INSN_READ_COND_CODE)
6694 && (prev_pinfo & INSN_WRITE_COND_CODE))
6695 return FALSE;
6696 if ((pinfo & INSN_WRITE_COND_CODE)
6697 && (prev_pinfo & INSN_READ_COND_CODE))
6698 return FALSE;
6699
6700 /* If the previous instruction uses the PC, we can not swap. */
2b0c8b40 6701 prev_pinfo2 = history[0].insn_mo->pinfo2;
26545944 6702 if (prev_pinfo2 & INSN2_READ_PC)
2b0c8b40 6703 return FALSE;
a4e06468 6704
df58fc94
RS
6705 /* If the previous instruction has an incorrect size for a fixed
6706 branch delay slot in microMIPS mode, we cannot swap. */
2309ddf2
MR
6707 pinfo2 = ip->insn_mo->pinfo2;
6708 if (mips_opts.micromips
6709 && (pinfo2 & INSN2_BRANCH_DELAY_16BIT)
6710 && insn_length (history) != 2)
6711 return FALSE;
6712 if (mips_opts.micromips
6713 && (pinfo2 & INSN2_BRANCH_DELAY_32BIT)
6714 && insn_length (history) != 4)
6715 return FALSE;
6716
e407c74b
NC
6717 /* On R5900 short loops need to be fixed by inserting a nop in
6718 the branch delay slots.
6719 A short loop can be terminated too early. */
6720 if (mips_opts.arch == CPU_R5900
6721 /* Check if instruction has a parameter, ignore "j $31". */
6722 && (address_expr != NULL)
6723 /* Parameter must be 16 bit. */
6724 && (*reloc_type == BFD_RELOC_16_PCREL_S2)
6725 /* Branch to same segment. */
6726 && (S_GET_SEGMENT(address_expr->X_add_symbol) == now_seg)
6727 /* Branch to same code fragment. */
6728 && (symbol_get_frag(address_expr->X_add_symbol) == frag_now)
6729 /* Can only calculate branch offset if value is known. */
6730 && symbol_constant_p(address_expr->X_add_symbol)
6731 /* Check if branch is really conditional. */
6732 && !((ip->insn_opcode & 0xffff0000) == 0x10000000 /* beq $0,$0 */
6733 || (ip->insn_opcode & 0xffff0000) == 0x04010000 /* bgez $0 */
6734 || (ip->insn_opcode & 0xffff0000) == 0x04110000)) /* bgezal $0 */
6735 {
6736 int distance;
6737 /* Check if loop is shorter than 6 instructions including
6738 branch and delay slot. */
6739 distance = frag_now_fix() - S_GET_VALUE(address_expr->X_add_symbol);
6740 if (distance <= 20)
6741 {
6742 int i;
6743 int rv;
6744
6745 rv = FALSE;
6746 /* When the loop includes branches or jumps,
6747 it is not a short loop. */
6748 for (i = 0; i < (distance / 4); i++)
6749 {
6750 if ((history[i].cleared_p)
6751 || delayed_branch_p(&history[i]))
6752 {
6753 rv = TRUE;
6754 break;
6755 }
6756 }
6757 if (rv == FALSE)
6758 {
6759 /* Insert nop after branch to fix short loop. */
6760 return FALSE;
6761 }
6762 }
6763 }
6764
a4e06468
RS
6765 return TRUE;
6766}
6767
e407c74b
NC
6768/* Decide how we should add IP to the instruction stream.
6769 ADDRESS_EXPR is an operand of the instruction to be used with
6770 RELOC_TYPE. */
a4e06468
RS
6771
6772static enum append_method
e407c74b 6773get_append_method (struct mips_cl_insn *ip, expressionS *address_expr,
26545944 6774 bfd_reloc_code_real_type *reloc_type)
a4e06468 6775{
a4e06468
RS
6776 /* The relaxed version of a macro sequence must be inherently
6777 hazard-free. */
6778 if (mips_relax.sequence == 2)
6779 return APPEND_ADD;
6780
6781 /* We must not dabble with instructions in a ".set norerorder" block. */
6782 if (mips_opts.noreorder)
6783 return APPEND_ADD;
6784
6785 /* Otherwise, it's our responsibility to fill branch delay slots. */
11625dd8 6786 if (delayed_branch_p (ip))
a4e06468 6787 {
e407c74b
NC
6788 if (!branch_likely_p (ip)
6789 && can_swap_branch_p (ip, address_expr, reloc_type))
a4e06468
RS
6790 return APPEND_SWAP;
6791
6792 if (mips_opts.mips16
6793 && ISA_SUPPORTS_MIPS16E
fc76e730 6794 && gpr_read_mask (ip) != 0)
a4e06468
RS
6795 return APPEND_ADD_COMPACT;
6796
6797 return APPEND_ADD_WITH_NOP;
6798 }
6799
a4e06468
RS
6800 return APPEND_ADD;
6801}
6802
ceb94aa5
RS
6803/* IP is a MIPS16 instruction whose opcode we have just changed.
6804 Point IP->insn_mo to the new opcode's definition. */
6805
6806static void
6807find_altered_mips16_opcode (struct mips_cl_insn *ip)
6808{
6809 const struct mips_opcode *mo, *end;
6810
6811 end = &mips16_opcodes[bfd_mips16_num_opcodes];
6812 for (mo = ip->insn_mo; mo < end; mo++)
6813 if ((ip->insn_opcode & mo->mask) == mo->match)
6814 {
6815 ip->insn_mo = mo;
6816 return;
6817 }
6818 abort ();
6819}
6820
df58fc94
RS
6821/* For microMIPS macros, we need to generate a local number label
6822 as the target of branches. */
6823#define MICROMIPS_LABEL_CHAR '\037'
6824static unsigned long micromips_target_label;
6825static char micromips_target_name[32];
6826
6827static char *
6828micromips_label_name (void)
6829{
6830 char *p = micromips_target_name;
6831 char symbol_name_temporary[24];
6832 unsigned long l;
6833 int i;
6834
6835 if (*p)
6836 return p;
6837
6838 i = 0;
6839 l = micromips_target_label;
6840#ifdef LOCAL_LABEL_PREFIX
6841 *p++ = LOCAL_LABEL_PREFIX;
6842#endif
6843 *p++ = 'L';
6844 *p++ = MICROMIPS_LABEL_CHAR;
6845 do
6846 {
6847 symbol_name_temporary[i++] = l % 10 + '0';
6848 l /= 10;
6849 }
6850 while (l != 0);
6851 while (i > 0)
6852 *p++ = symbol_name_temporary[--i];
6853 *p = '\0';
6854
6855 return micromips_target_name;
6856}
6857
6858static void
6859micromips_label_expr (expressionS *label_expr)
6860{
6861 label_expr->X_op = O_symbol;
6862 label_expr->X_add_symbol = symbol_find_or_make (micromips_label_name ());
6863 label_expr->X_add_number = 0;
6864}
6865
6866static void
6867micromips_label_inc (void)
6868{
6869 micromips_target_label++;
6870 *micromips_target_name = '\0';
6871}
6872
6873static void
6874micromips_add_label (void)
6875{
6876 symbolS *s;
6877
6878 s = colon (micromips_label_name ());
6879 micromips_label_inc ();
f3ded42a 6880 S_SET_OTHER (s, ELF_ST_SET_MICROMIPS (S_GET_OTHER (s)));
df58fc94
RS
6881}
6882
6883/* If assembling microMIPS code, then return the microMIPS reloc
6884 corresponding to the requested one if any. Otherwise return
6885 the reloc unchanged. */
6886
6887static bfd_reloc_code_real_type
6888micromips_map_reloc (bfd_reloc_code_real_type reloc)
6889{
6890 static const bfd_reloc_code_real_type relocs[][2] =
6891 {
6892 /* Keep sorted incrementally by the left-hand key. */
6893 { BFD_RELOC_16_PCREL_S2, BFD_RELOC_MICROMIPS_16_PCREL_S1 },
6894 { BFD_RELOC_GPREL16, BFD_RELOC_MICROMIPS_GPREL16 },
6895 { BFD_RELOC_MIPS_JMP, BFD_RELOC_MICROMIPS_JMP },
6896 { BFD_RELOC_HI16, BFD_RELOC_MICROMIPS_HI16 },
6897 { BFD_RELOC_HI16_S, BFD_RELOC_MICROMIPS_HI16_S },
6898 { BFD_RELOC_LO16, BFD_RELOC_MICROMIPS_LO16 },
6899 { BFD_RELOC_MIPS_LITERAL, BFD_RELOC_MICROMIPS_LITERAL },
6900 { BFD_RELOC_MIPS_GOT16, BFD_RELOC_MICROMIPS_GOT16 },
6901 { BFD_RELOC_MIPS_CALL16, BFD_RELOC_MICROMIPS_CALL16 },
6902 { BFD_RELOC_MIPS_GOT_HI16, BFD_RELOC_MICROMIPS_GOT_HI16 },
6903 { BFD_RELOC_MIPS_GOT_LO16, BFD_RELOC_MICROMIPS_GOT_LO16 },
6904 { BFD_RELOC_MIPS_CALL_HI16, BFD_RELOC_MICROMIPS_CALL_HI16 },
6905 { BFD_RELOC_MIPS_CALL_LO16, BFD_RELOC_MICROMIPS_CALL_LO16 },
6906 { BFD_RELOC_MIPS_SUB, BFD_RELOC_MICROMIPS_SUB },
6907 { BFD_RELOC_MIPS_GOT_PAGE, BFD_RELOC_MICROMIPS_GOT_PAGE },
6908 { BFD_RELOC_MIPS_GOT_OFST, BFD_RELOC_MICROMIPS_GOT_OFST },
6909 { BFD_RELOC_MIPS_GOT_DISP, BFD_RELOC_MICROMIPS_GOT_DISP },
6910 { BFD_RELOC_MIPS_HIGHEST, BFD_RELOC_MICROMIPS_HIGHEST },
6911 { BFD_RELOC_MIPS_HIGHER, BFD_RELOC_MICROMIPS_HIGHER },
6912 { BFD_RELOC_MIPS_SCN_DISP, BFD_RELOC_MICROMIPS_SCN_DISP },
6913 { BFD_RELOC_MIPS_TLS_GD, BFD_RELOC_MICROMIPS_TLS_GD },
6914 { BFD_RELOC_MIPS_TLS_LDM, BFD_RELOC_MICROMIPS_TLS_LDM },
6915 { BFD_RELOC_MIPS_TLS_DTPREL_HI16, BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16 },
6916 { BFD_RELOC_MIPS_TLS_DTPREL_LO16, BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16 },
6917 { BFD_RELOC_MIPS_TLS_GOTTPREL, BFD_RELOC_MICROMIPS_TLS_GOTTPREL },
6918 { BFD_RELOC_MIPS_TLS_TPREL_HI16, BFD_RELOC_MICROMIPS_TLS_TPREL_HI16 },
6919 { BFD_RELOC_MIPS_TLS_TPREL_LO16, BFD_RELOC_MICROMIPS_TLS_TPREL_LO16 }
6920 };
6921 bfd_reloc_code_real_type r;
6922 size_t i;
6923
6924 if (!mips_opts.micromips)
6925 return reloc;
6926 for (i = 0; i < ARRAY_SIZE (relocs); i++)
6927 {
6928 r = relocs[i][0];
6929 if (r > reloc)
6930 return reloc;
6931 if (r == reloc)
6932 return relocs[i][1];
6933 }
6934 return reloc;
6935}
6936
b886a2ab
RS
6937/* Try to resolve relocation RELOC against constant OPERAND at assembly time.
6938 Return true on success, storing the resolved value in RESULT. */
6939
6940static bfd_boolean
6941calculate_reloc (bfd_reloc_code_real_type reloc, offsetT operand,
6942 offsetT *result)
6943{
6944 switch (reloc)
6945 {
6946 case BFD_RELOC_MIPS_HIGHEST:
6947 case BFD_RELOC_MICROMIPS_HIGHEST:
6948 *result = ((operand + 0x800080008000ull) >> 48) & 0xffff;
6949 return TRUE;
6950
6951 case BFD_RELOC_MIPS_HIGHER:
6952 case BFD_RELOC_MICROMIPS_HIGHER:
6953 *result = ((operand + 0x80008000ull) >> 32) & 0xffff;
6954 return TRUE;
6955
6956 case BFD_RELOC_HI16_S:
6957 case BFD_RELOC_MICROMIPS_HI16_S:
6958 case BFD_RELOC_MIPS16_HI16_S:
6959 *result = ((operand + 0x8000) >> 16) & 0xffff;
6960 return TRUE;
6961
6962 case BFD_RELOC_HI16:
6963 case BFD_RELOC_MICROMIPS_HI16:
6964 case BFD_RELOC_MIPS16_HI16:
6965 *result = (operand >> 16) & 0xffff;
6966 return TRUE;
6967
6968 case BFD_RELOC_LO16:
6969 case BFD_RELOC_MICROMIPS_LO16:
6970 case BFD_RELOC_MIPS16_LO16:
6971 *result = operand & 0xffff;
6972 return TRUE;
6973
6974 case BFD_RELOC_UNUSED:
6975 *result = operand;
6976 return TRUE;
6977
6978 default:
6979 return FALSE;
6980 }
6981}
6982
71400594
RS
6983/* Output an instruction. IP is the instruction information.
6984 ADDRESS_EXPR is an operand of the instruction to be used with
df58fc94
RS
6985 RELOC_TYPE. EXPANSIONP is true if the instruction is part of
6986 a macro expansion. */
71400594
RS
6987
6988static void
6989append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
df58fc94 6990 bfd_reloc_code_real_type *reloc_type, bfd_boolean expansionp)
71400594 6991{
14fe068b 6992 unsigned long prev_pinfo2, pinfo;
71400594 6993 bfd_boolean relaxed_branch = FALSE;
a4e06468 6994 enum append_method method;
2309ddf2 6995 bfd_boolean relax32;
2b0c8b40 6996 int branch_disp;
71400594 6997
2309ddf2 6998 if (mips_fix_loongson2f && !HAVE_CODE_COMPRESSION)
c67a084a
NC
6999 fix_loongson2f (ip);
7000
738f4d98 7001 file_ase_mips16 |= mips_opts.mips16;
df58fc94 7002 file_ase_micromips |= mips_opts.micromips;
738f4d98 7003
df58fc94 7004 prev_pinfo2 = history[0].insn_mo->pinfo2;
71400594 7005 pinfo = ip->insn_mo->pinfo;
df58fc94
RS
7006
7007 if (mips_opts.micromips
7008 && !expansionp
7009 && (((prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0
7010 && micromips_insn_length (ip->insn_mo) != 2)
7011 || ((prev_pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0
7012 && micromips_insn_length (ip->insn_mo) != 4)))
1661c76c 7013 as_warn (_("wrong size instruction in a %u-bit branch delay slot"),
df58fc94 7014 (prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 ? 16 : 32);
71400594 7015
15be625d
CM
7016 if (address_expr == NULL)
7017 ip->complete_p = 1;
b886a2ab
RS
7018 else if (reloc_type[0] <= BFD_RELOC_UNUSED
7019 && reloc_type[1] == BFD_RELOC_UNUSED
7020 && reloc_type[2] == BFD_RELOC_UNUSED
15be625d
CM
7021 && address_expr->X_op == O_constant)
7022 {
15be625d
CM
7023 switch (*reloc_type)
7024 {
15be625d 7025 case BFD_RELOC_MIPS_JMP:
df58fc94
RS
7026 {
7027 int shift;
7028
7029 shift = mips_opts.micromips ? 1 : 2;
7030 if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0)
7031 as_bad (_("jump to misaligned address (0x%lx)"),
7032 (unsigned long) address_expr->X_add_number);
7033 ip->insn_opcode |= ((address_expr->X_add_number >> shift)
7034 & 0x3ffffff);
335574df 7035 ip->complete_p = 1;
df58fc94 7036 }
15be625d
CM
7037 break;
7038
7039 case BFD_RELOC_MIPS16_JMP:
7040 if ((address_expr->X_add_number & 3) != 0)
7041 as_bad (_("jump to misaligned address (0x%lx)"),
7042 (unsigned long) address_expr->X_add_number);
7043 ip->insn_opcode |=
7044 (((address_expr->X_add_number & 0x7c0000) << 3)
7045 | ((address_expr->X_add_number & 0xf800000) >> 7)
7046 | ((address_expr->X_add_number & 0x3fffc) >> 2));
335574df 7047 ip->complete_p = 1;
15be625d
CM
7048 break;
7049
7050 case BFD_RELOC_16_PCREL_S2:
df58fc94
RS
7051 {
7052 int shift;
7053
7054 shift = mips_opts.micromips ? 1 : 2;
7055 if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0)
7056 as_bad (_("branch to misaligned address (0x%lx)"),
7057 (unsigned long) address_expr->X_add_number);
7058 if (!mips_relax_branch)
7059 {
7060 if ((address_expr->X_add_number + (1 << (shift + 15)))
7061 & ~((1 << (shift + 16)) - 1))
7062 as_bad (_("branch address range overflow (0x%lx)"),
7063 (unsigned long) address_expr->X_add_number);
7064 ip->insn_opcode |= ((address_expr->X_add_number >> shift)
7065 & 0xffff);
7066 }
df58fc94 7067 }
15be625d
CM
7068 break;
7069
7361da2c
AB
7070 case BFD_RELOC_MIPS_21_PCREL_S2:
7071 {
7072 int shift;
7073
7074 shift = 2;
7075 if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0)
7076 as_bad (_("branch to misaligned address (0x%lx)"),
7077 (unsigned long) address_expr->X_add_number);
7078 if ((address_expr->X_add_number + (1 << (shift + 20)))
7079 & ~((1 << (shift + 21)) - 1))
7080 as_bad (_("branch address range overflow (0x%lx)"),
7081 (unsigned long) address_expr->X_add_number);
7082 ip->insn_opcode |= ((address_expr->X_add_number >> shift)
7083 & 0x1fffff);
7084 }
7085 break;
7086
7087 case BFD_RELOC_MIPS_26_PCREL_S2:
7088 {
7089 int shift;
7090
7091 shift = 2;
7092 if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0)
7093 as_bad (_("branch to misaligned address (0x%lx)"),
7094 (unsigned long) address_expr->X_add_number);
7095 if ((address_expr->X_add_number + (1 << (shift + 25)))
7096 & ~((1 << (shift + 26)) - 1))
7097 as_bad (_("branch address range overflow (0x%lx)"),
7098 (unsigned long) address_expr->X_add_number);
7099 ip->insn_opcode |= ((address_expr->X_add_number >> shift)
7100 & 0x3ffffff);
7101 }
7102 break;
7103
15be625d 7104 default:
b886a2ab
RS
7105 {
7106 offsetT value;
7107
7108 if (calculate_reloc (*reloc_type, address_expr->X_add_number,
7109 &value))
7110 {
7111 ip->insn_opcode |= value & 0xffff;
7112 ip->complete_p = 1;
7113 }
7114 }
7115 break;
7116 }
15be625d
CM
7117 }
7118
71400594
RS
7119 if (mips_relax.sequence != 2 && !mips_opts.noreorder)
7120 {
7121 /* There are a lot of optimizations we could do that we don't.
7122 In particular, we do not, in general, reorder instructions.
7123 If you use gcc with optimization, it will reorder
7124 instructions and generally do much more optimization then we
7125 do here; repeating all that work in the assembler would only
7126 benefit hand written assembly code, and does not seem worth
7127 it. */
7128 int nops = (mips_optimize == 0
932d1a1b
RS
7129 ? nops_for_insn (0, history, NULL)
7130 : nops_for_insn_or_target (0, history, ip));
71400594 7131 if (nops > 0)
252b5132
RH
7132 {
7133 fragS *old_frag;
7134 unsigned long old_frag_offset;
7135 int i;
252b5132
RH
7136
7137 old_frag = frag_now;
7138 old_frag_offset = frag_now_fix ();
7139
7140 for (i = 0; i < nops; i++)
14fe068b
RS
7141 add_fixed_insn (NOP_INSN);
7142 insert_into_history (0, nops, NOP_INSN);
252b5132
RH
7143
7144 if (listing)
7145 {
7146 listing_prev_line ();
7147 /* We may be at the start of a variant frag. In case we
7148 are, make sure there is enough space for the frag
7149 after the frags created by listing_prev_line. The
7150 argument to frag_grow here must be at least as large
7151 as the argument to all other calls to frag_grow in
7152 this file. We don't have to worry about being in the
7153 middle of a variant frag, because the variants insert
7154 all needed nop instructions themselves. */
7155 frag_grow (40);
7156 }
7157
462427c4 7158 mips_move_text_labels ();
252b5132
RH
7159
7160#ifndef NO_ECOFF_DEBUGGING
7161 if (ECOFF_DEBUGGING)
7162 ecoff_fix_loc (old_frag, old_frag_offset);
7163#endif
7164 }
71400594
RS
7165 }
7166 else if (mips_relax.sequence != 2 && prev_nop_frag != NULL)
7167 {
932d1a1b
RS
7168 int nops;
7169
7170 /* Work out how many nops in prev_nop_frag are needed by IP,
7171 ignoring hazards generated by the first prev_nop_frag_since
7172 instructions. */
7173 nops = nops_for_insn_or_target (prev_nop_frag_since, history, ip);
9c2799c2 7174 gas_assert (nops <= prev_nop_frag_holds);
252b5132 7175
71400594
RS
7176 /* Enforce NOPS as a minimum. */
7177 if (nops > prev_nop_frag_required)
7178 prev_nop_frag_required = nops;
252b5132 7179
71400594
RS
7180 if (prev_nop_frag_holds == prev_nop_frag_required)
7181 {
7182 /* Settle for the current number of nops. Update the history
7183 accordingly (for the benefit of any future .set reorder code). */
7184 prev_nop_frag = NULL;
7185 insert_into_history (prev_nop_frag_since,
7186 prev_nop_frag_holds, NOP_INSN);
7187 }
7188 else
7189 {
7190 /* Allow this instruction to replace one of the nops that was
7191 tentatively added to prev_nop_frag. */
df58fc94 7192 prev_nop_frag->fr_fix -= NOP_INSN_SIZE;
71400594
RS
7193 prev_nop_frag_holds--;
7194 prev_nop_frag_since++;
252b5132
RH
7195 }
7196 }
7197
e407c74b 7198 method = get_append_method (ip, address_expr, reloc_type);
2b0c8b40 7199 branch_disp = method == APPEND_SWAP ? insn_length (history) : 0;
a4e06468 7200
e410add4
RS
7201 dwarf2_emit_insn (0);
7202 /* We want MIPS16 and microMIPS debug info to use ISA-encoded addresses,
7203 so "move" the instruction address accordingly.
7204
7205 Also, it doesn't seem appropriate for the assembler to reorder .loc
7206 entries. If this instruction is a branch that we are going to swap
7207 with the previous instruction, the two instructions should be
7208 treated as a unit, and the debug information for both instructions
7209 should refer to the start of the branch sequence. Using the
7210 current position is certainly wrong when swapping a 32-bit branch
7211 and a 16-bit delay slot, since the current position would then be
7212 in the middle of a branch. */
7213 dwarf2_move_insn ((HAVE_CODE_COMPRESSION ? 1 : 0) - branch_disp);
58e2ea4d 7214
df58fc94
RS
7215 relax32 = (mips_relax_branch
7216 /* Don't try branch relaxation within .set nomacro, or within
7217 .set noat if we use $at for PIC computations. If it turns
7218 out that the branch was out-of-range, we'll get an error. */
7219 && !mips_opts.warn_about_macros
7220 && (mips_opts.at || mips_pic == NO_PIC)
3bf0dbfb
MR
7221 /* Don't relax BPOSGE32/64 or BC1ANY2T/F and BC1ANY4T/F
7222 as they have no complementing branches. */
7223 && !(ip->insn_mo->ase & (ASE_MIPS3D | ASE_DSP64 | ASE_DSP)));
df58fc94
RS
7224
7225 if (!HAVE_CODE_COMPRESSION
7226 && address_expr
7227 && relax32
0b25d3e6 7228 && *reloc_type == BFD_RELOC_16_PCREL_S2
11625dd8 7229 && delayed_branch_p (ip))
4a6a3df4 7230 {
895921c9 7231 relaxed_branch = TRUE;
1e915849
RS
7232 add_relaxed_insn (ip, (relaxed_branch_length
7233 (NULL, NULL,
11625dd8
RS
7234 uncond_branch_p (ip) ? -1
7235 : branch_likely_p (ip) ? 1
1e915849
RS
7236 : 0)), 4,
7237 RELAX_BRANCH_ENCODE
66b3e8da 7238 (AT,
11625dd8
RS
7239 uncond_branch_p (ip),
7240 branch_likely_p (ip),
1e915849
RS
7241 pinfo & INSN_WRITE_GPR_31,
7242 0),
7243 address_expr->X_add_symbol,
7244 address_expr->X_add_number);
4a6a3df4
AO
7245 *reloc_type = BFD_RELOC_UNUSED;
7246 }
df58fc94
RS
7247 else if (mips_opts.micromips
7248 && address_expr
7249 && ((relax32 && *reloc_type == BFD_RELOC_16_PCREL_S2)
7250 || *reloc_type > BFD_RELOC_UNUSED)
40209cad
MR
7251 && (delayed_branch_p (ip) || compact_branch_p (ip))
7252 /* Don't try branch relaxation when users specify
7253 16-bit/32-bit instructions. */
7254 && !forced_insn_length)
df58fc94
RS
7255 {
7256 bfd_boolean relax16 = *reloc_type > BFD_RELOC_UNUSED;
7257 int type = relax16 ? *reloc_type - BFD_RELOC_UNUSED : 0;
11625dd8
RS
7258 int uncond = uncond_branch_p (ip) ? -1 : 0;
7259 int compact = compact_branch_p (ip);
df58fc94
RS
7260 int al = pinfo & INSN_WRITE_GPR_31;
7261 int length32;
7262
7263 gas_assert (address_expr != NULL);
7264 gas_assert (!mips_relax.sequence);
7265
2b0c8b40 7266 relaxed_branch = TRUE;
df58fc94
RS
7267 length32 = relaxed_micromips_32bit_branch_length (NULL, NULL, uncond);
7268 add_relaxed_insn (ip, relax32 ? length32 : 4, relax16 ? 2 : 4,
40209cad
MR
7269 RELAX_MICROMIPS_ENCODE (type, AT, uncond, compact, al,
7270 relax32, 0, 0),
df58fc94
RS
7271 address_expr->X_add_symbol,
7272 address_expr->X_add_number);
7273 *reloc_type = BFD_RELOC_UNUSED;
7274 }
7275 else if (mips_opts.mips16 && *reloc_type > BFD_RELOC_UNUSED)
252b5132
RH
7276 {
7277 /* We need to set up a variant frag. */
df58fc94 7278 gas_assert (address_expr != NULL);
1e915849
RS
7279 add_relaxed_insn (ip, 4, 0,
7280 RELAX_MIPS16_ENCODE
7281 (*reloc_type - BFD_RELOC_UNUSED,
df58fc94 7282 forced_insn_length == 2, forced_insn_length == 4,
11625dd8 7283 delayed_branch_p (&history[0]),
1e915849
RS
7284 history[0].mips16_absolute_jump_p),
7285 make_expr_symbol (address_expr), 0);
252b5132 7286 }
5c04167a 7287 else if (mips_opts.mips16 && insn_length (ip) == 2)
9497f5ac 7288 {
11625dd8 7289 if (!delayed_branch_p (ip))
b8ee1a6e
DU
7290 /* Make sure there is enough room to swap this instruction with
7291 a following jump instruction. */
7292 frag_grow (6);
1e915849 7293 add_fixed_insn (ip);
252b5132
RH
7294 }
7295 else
7296 {
7297 if (mips_opts.mips16
7298 && mips_opts.noreorder
11625dd8 7299 && delayed_branch_p (&history[0]))
252b5132
RH
7300 as_warn (_("extended instruction in delay slot"));
7301
4d7206a2
RS
7302 if (mips_relax.sequence)
7303 {
7304 /* If we've reached the end of this frag, turn it into a variant
7305 frag and record the information for the instructions we've
7306 written so far. */
7307 if (frag_room () < 4)
7308 relax_close_frag ();
df58fc94 7309 mips_relax.sizes[mips_relax.sequence - 1] += insn_length (ip);
4d7206a2
RS
7310 }
7311
584892a6 7312 if (mips_relax.sequence != 2)
df58fc94
RS
7313 {
7314 if (mips_macro_warning.first_insn_sizes[0] == 0)
7315 mips_macro_warning.first_insn_sizes[0] = insn_length (ip);
7316 mips_macro_warning.sizes[0] += insn_length (ip);
7317 mips_macro_warning.insns[0]++;
7318 }
584892a6 7319 if (mips_relax.sequence != 1)
df58fc94
RS
7320 {
7321 if (mips_macro_warning.first_insn_sizes[1] == 0)
7322 mips_macro_warning.first_insn_sizes[1] = insn_length (ip);
7323 mips_macro_warning.sizes[1] += insn_length (ip);
7324 mips_macro_warning.insns[1]++;
7325 }
584892a6 7326
1e915849
RS
7327 if (mips_opts.mips16)
7328 {
7329 ip->fixed_p = 1;
7330 ip->mips16_absolute_jump_p = (*reloc_type == BFD_RELOC_MIPS16_JMP);
7331 }
7332 add_fixed_insn (ip);
252b5132
RH
7333 }
7334
9fe77896 7335 if (!ip->complete_p && *reloc_type < BFD_RELOC_UNUSED)
252b5132 7336 {
df58fc94 7337 bfd_reloc_code_real_type final_type[3];
2309ddf2 7338 reloc_howto_type *howto0;
9fe77896
RS
7339 reloc_howto_type *howto;
7340 int i;
34ce925e 7341
df58fc94
RS
7342 /* Perform any necessary conversion to microMIPS relocations
7343 and find out how many relocations there actually are. */
7344 for (i = 0; i < 3 && reloc_type[i] != BFD_RELOC_UNUSED; i++)
7345 final_type[i] = micromips_map_reloc (reloc_type[i]);
7346
9fe77896
RS
7347 /* In a compound relocation, it is the final (outermost)
7348 operator that determines the relocated field. */
2309ddf2 7349 howto = howto0 = bfd_reloc_type_lookup (stdoutput, final_type[i - 1]);
e8044f35
RS
7350 if (!howto)
7351 abort ();
2309ddf2
MR
7352
7353 if (i > 1)
7354 howto0 = bfd_reloc_type_lookup (stdoutput, final_type[0]);
9fe77896
RS
7355 ip->fixp[0] = fix_new_exp (ip->frag, ip->where,
7356 bfd_get_reloc_size (howto),
7357 address_expr,
2309ddf2
MR
7358 howto0 && howto0->pc_relative,
7359 final_type[0]);
9fe77896
RS
7360
7361 /* Tag symbols that have a R_MIPS16_26 relocation against them. */
2309ddf2 7362 if (final_type[0] == BFD_RELOC_MIPS16_JMP && ip->fixp[0]->fx_addsy)
9fe77896
RS
7363 *symbol_get_tc (ip->fixp[0]->fx_addsy) = 1;
7364
7365 /* These relocations can have an addend that won't fit in
7366 4 octets for 64bit assembly. */
bad1aba3 7367 if (GPR_SIZE == 64
9fe77896
RS
7368 && ! howto->partial_inplace
7369 && (reloc_type[0] == BFD_RELOC_16
7370 || reloc_type[0] == BFD_RELOC_32
7371 || reloc_type[0] == BFD_RELOC_MIPS_JMP
7372 || reloc_type[0] == BFD_RELOC_GPREL16
7373 || reloc_type[0] == BFD_RELOC_MIPS_LITERAL
7374 || reloc_type[0] == BFD_RELOC_GPREL32
7375 || reloc_type[0] == BFD_RELOC_64
7376 || reloc_type[0] == BFD_RELOC_CTOR
7377 || reloc_type[0] == BFD_RELOC_MIPS_SUB
7378 || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST
7379 || reloc_type[0] == BFD_RELOC_MIPS_HIGHER
7380 || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP
7381 || reloc_type[0] == BFD_RELOC_MIPS_REL16
7382 || reloc_type[0] == BFD_RELOC_MIPS_RELGOT
7383 || reloc_type[0] == BFD_RELOC_MIPS16_GPREL
7384 || hi16_reloc_p (reloc_type[0])
7385 || lo16_reloc_p (reloc_type[0])))
7386 ip->fixp[0]->fx_no_overflow = 1;
7387
ddaf2c41
MR
7388 /* These relocations can have an addend that won't fit in 2 octets. */
7389 if (reloc_type[0] == BFD_RELOC_MICROMIPS_7_PCREL_S1
7390 || reloc_type[0] == BFD_RELOC_MICROMIPS_10_PCREL_S1)
7391 ip->fixp[0]->fx_no_overflow = 1;
7392
9fe77896
RS
7393 if (mips_relax.sequence)
7394 {
7395 if (mips_relax.first_fixup == 0)
7396 mips_relax.first_fixup = ip->fixp[0];
7397 }
7398 else if (reloc_needs_lo_p (*reloc_type))
7399 {
7400 struct mips_hi_fixup *hi_fixup;
7401
7402 /* Reuse the last entry if it already has a matching %lo. */
7403 hi_fixup = mips_hi_fixup_list;
7404 if (hi_fixup == 0
7405 || !fixup_has_matching_lo_p (hi_fixup->fixp))
4d7206a2 7406 {
9fe77896
RS
7407 hi_fixup = ((struct mips_hi_fixup *)
7408 xmalloc (sizeof (struct mips_hi_fixup)));
7409 hi_fixup->next = mips_hi_fixup_list;
7410 mips_hi_fixup_list = hi_fixup;
4d7206a2 7411 }
9fe77896
RS
7412 hi_fixup->fixp = ip->fixp[0];
7413 hi_fixup->seg = now_seg;
7414 }
252b5132 7415
9fe77896
RS
7416 /* Add fixups for the second and third relocations, if given.
7417 Note that the ABI allows the second relocation to be
7418 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
7419 moment we only use RSS_UNDEF, but we could add support
7420 for the others if it ever becomes necessary. */
7421 for (i = 1; i < 3; i++)
7422 if (reloc_type[i] != BFD_RELOC_UNUSED)
7423 {
7424 ip->fixp[i] = fix_new (ip->frag, ip->where,
7425 ip->fixp[0]->fx_size, NULL, 0,
df58fc94 7426 FALSE, final_type[i]);
f6688943 7427
9fe77896
RS
7428 /* Use fx_tcbit to mark compound relocs. */
7429 ip->fixp[0]->fx_tcbit = 1;
7430 ip->fixp[i]->fx_tcbit = 1;
7431 }
252b5132 7432 }
1e915849 7433 install_insn (ip);
252b5132
RH
7434
7435 /* Update the register mask information. */
4c260379
RS
7436 mips_gprmask |= gpr_read_mask (ip) | gpr_write_mask (ip);
7437 mips_cprmask[1] |= fpr_read_mask (ip) | fpr_write_mask (ip);
252b5132 7438
a4e06468 7439 switch (method)
252b5132 7440 {
a4e06468
RS
7441 case APPEND_ADD:
7442 insert_into_history (0, 1, ip);
7443 break;
7444
7445 case APPEND_ADD_WITH_NOP:
14fe068b
RS
7446 {
7447 struct mips_cl_insn *nop;
7448
7449 insert_into_history (0, 1, ip);
7450 nop = get_delay_slot_nop (ip);
7451 add_fixed_insn (nop);
7452 insert_into_history (0, 1, nop);
7453 if (mips_relax.sequence)
7454 mips_relax.sizes[mips_relax.sequence - 1] += insn_length (nop);
7455 }
a4e06468
RS
7456 break;
7457
7458 case APPEND_ADD_COMPACT:
7459 /* Convert MIPS16 jr/jalr into a "compact" jump. */
7460 gas_assert (mips_opts.mips16);
7461 ip->insn_opcode |= 0x0080;
7462 find_altered_mips16_opcode (ip);
7463 install_insn (ip);
7464 insert_into_history (0, 1, ip);
7465 break;
7466
7467 case APPEND_SWAP:
7468 {
7469 struct mips_cl_insn delay = history[0];
7470 if (mips_opts.mips16)
7471 {
7472 know (delay.frag == ip->frag);
7473 move_insn (ip, delay.frag, delay.where);
7474 move_insn (&delay, ip->frag, ip->where + insn_length (ip));
7475 }
464ab0e5 7476 else if (relaxed_branch || delay.frag != ip->frag)
a4e06468
RS
7477 {
7478 /* Add the delay slot instruction to the end of the
7479 current frag and shrink the fixed part of the
7480 original frag. If the branch occupies the tail of
7481 the latter, move it backwards to cover the gap. */
2b0c8b40 7482 delay.frag->fr_fix -= branch_disp;
a4e06468 7483 if (delay.frag == ip->frag)
2b0c8b40 7484 move_insn (ip, ip->frag, ip->where - branch_disp);
a4e06468
RS
7485 add_fixed_insn (&delay);
7486 }
7487 else
7488 {
2b0c8b40
MR
7489 move_insn (&delay, ip->frag,
7490 ip->where - branch_disp + insn_length (ip));
a4e06468
RS
7491 move_insn (ip, history[0].frag, history[0].where);
7492 }
7493 history[0] = *ip;
7494 delay.fixed_p = 1;
7495 insert_into_history (0, 1, &delay);
7496 }
7497 break;
252b5132
RH
7498 }
7499
13408f1e 7500 /* If we have just completed an unconditional branch, clear the history. */
11625dd8
RS
7501 if ((delayed_branch_p (&history[1]) && uncond_branch_p (&history[1]))
7502 || (compact_branch_p (&history[0]) && uncond_branch_p (&history[0])))
e407c74b
NC
7503 {
7504 unsigned int i;
7505
79850f26 7506 mips_no_prev_insn ();
13408f1e 7507
e407c74b 7508 for (i = 0; i < ARRAY_SIZE (history); i++)
79850f26 7509 history[i].cleared_p = 1;
e407c74b
NC
7510 }
7511
df58fc94
RS
7512 /* We need to emit a label at the end of branch-likely macros. */
7513 if (emit_branch_likely_macro)
7514 {
7515 emit_branch_likely_macro = FALSE;
7516 micromips_add_label ();
7517 }
7518
252b5132
RH
7519 /* We just output an insn, so the next one doesn't have a label. */
7520 mips_clear_insn_labels ();
252b5132
RH
7521}
7522
e407c74b
NC
7523/* Forget that there was any previous instruction or label.
7524 When BRANCH is true, the branch history is also flushed. */
252b5132
RH
7525
7526static void
7d10b47d 7527mips_no_prev_insn (void)
252b5132 7528{
7d10b47d
RS
7529 prev_nop_frag = NULL;
7530 insert_into_history (0, ARRAY_SIZE (history), NOP_INSN);
252b5132
RH
7531 mips_clear_insn_labels ();
7532}
7533
7d10b47d
RS
7534/* This function must be called before we emit something other than
7535 instructions. It is like mips_no_prev_insn except that it inserts
7536 any NOPS that might be needed by previous instructions. */
252b5132 7537
7d10b47d
RS
7538void
7539mips_emit_delays (void)
252b5132
RH
7540{
7541 if (! mips_opts.noreorder)
7542 {
932d1a1b 7543 int nops = nops_for_insn (0, history, NULL);
252b5132
RH
7544 if (nops > 0)
7545 {
7d10b47d
RS
7546 while (nops-- > 0)
7547 add_fixed_insn (NOP_INSN);
462427c4 7548 mips_move_text_labels ();
7d10b47d
RS
7549 }
7550 }
7551 mips_no_prev_insn ();
7552}
7553
7554/* Start a (possibly nested) noreorder block. */
7555
7556static void
7557start_noreorder (void)
7558{
7559 if (mips_opts.noreorder == 0)
7560 {
7561 unsigned int i;
7562 int nops;
7563
7564 /* None of the instructions before the .set noreorder can be moved. */
7565 for (i = 0; i < ARRAY_SIZE (history); i++)
7566 history[i].fixed_p = 1;
7567
7568 /* Insert any nops that might be needed between the .set noreorder
7569 block and the previous instructions. We will later remove any
7570 nops that turn out not to be needed. */
932d1a1b 7571 nops = nops_for_insn (0, history, NULL);
7d10b47d
RS
7572 if (nops > 0)
7573 {
7574 if (mips_optimize != 0)
252b5132
RH
7575 {
7576 /* Record the frag which holds the nop instructions, so
7577 that we can remove them if we don't need them. */
df58fc94 7578 frag_grow (nops * NOP_INSN_SIZE);
252b5132
RH
7579 prev_nop_frag = frag_now;
7580 prev_nop_frag_holds = nops;
7581 prev_nop_frag_required = 0;
7582 prev_nop_frag_since = 0;
7583 }
7584
7585 for (; nops > 0; --nops)
1e915849 7586 add_fixed_insn (NOP_INSN);
252b5132 7587
7d10b47d
RS
7588 /* Move on to a new frag, so that it is safe to simply
7589 decrease the size of prev_nop_frag. */
7590 frag_wane (frag_now);
7591 frag_new (0);
462427c4 7592 mips_move_text_labels ();
252b5132 7593 }
df58fc94 7594 mips_mark_labels ();
7d10b47d 7595 mips_clear_insn_labels ();
252b5132 7596 }
7d10b47d
RS
7597 mips_opts.noreorder++;
7598 mips_any_noreorder = 1;
7599}
252b5132 7600
7d10b47d 7601/* End a nested noreorder block. */
252b5132 7602
7d10b47d
RS
7603static void
7604end_noreorder (void)
7605{
7606 mips_opts.noreorder--;
7607 if (mips_opts.noreorder == 0 && prev_nop_frag != NULL)
7608 {
7609 /* Commit to inserting prev_nop_frag_required nops and go back to
7610 handling nop insertion the .set reorder way. */
7611 prev_nop_frag->fr_fix -= ((prev_nop_frag_holds - prev_nop_frag_required)
df58fc94 7612 * NOP_INSN_SIZE);
7d10b47d
RS
7613 insert_into_history (prev_nop_frag_since,
7614 prev_nop_frag_required, NOP_INSN);
7615 prev_nop_frag = NULL;
7616 }
252b5132
RH
7617}
7618
97d87491
RS
7619/* Sign-extend 32-bit mode constants that have bit 31 set and all
7620 higher bits unset. */
7621
7622static void
7623normalize_constant_expr (expressionS *ex)
7624{
7625 if (ex->X_op == O_constant
7626 && IS_ZEXT_32BIT_NUM (ex->X_add_number))
7627 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
7628 - 0x80000000);
7629}
7630
7631/* Sign-extend 32-bit mode address offsets that have bit 31 set and
7632 all higher bits unset. */
7633
7634static void
7635normalize_address_expr (expressionS *ex)
7636{
7637 if (((ex->X_op == O_constant && HAVE_32BIT_ADDRESSES)
7638 || (ex->X_op == O_symbol && HAVE_32BIT_SYMBOLS))
7639 && IS_ZEXT_32BIT_NUM (ex->X_add_number))
7640 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
7641 - 0x80000000);
7642}
7643
7644/* Try to match TOKENS against OPCODE, storing the result in INSN.
7645 Return true if the match was successful.
7646
7647 OPCODE_EXTRA is a value that should be ORed into the opcode
7648 (used for VU0 channel suffixes, etc.). MORE_ALTS is true if
7649 there are more alternatives after OPCODE and SOFT_MATCH is
7650 as for mips_arg_info. */
7651
7652static bfd_boolean
7653match_insn (struct mips_cl_insn *insn, const struct mips_opcode *opcode,
7654 struct mips_operand_token *tokens, unsigned int opcode_extra,
60f20e8b 7655 bfd_boolean lax_match, bfd_boolean complete_p)
97d87491
RS
7656{
7657 const char *args;
7658 struct mips_arg_info arg;
7659 const struct mips_operand *operand;
7660 char c;
7661
7662 imm_expr.X_op = O_absent;
97d87491
RS
7663 offset_expr.X_op = O_absent;
7664 offset_reloc[0] = BFD_RELOC_UNUSED;
7665 offset_reloc[1] = BFD_RELOC_UNUSED;
7666 offset_reloc[2] = BFD_RELOC_UNUSED;
7667
7668 create_insn (insn, opcode);
60f20e8b
RS
7669 /* When no opcode suffix is specified, assume ".xyzw". */
7670 if ((opcode->pinfo2 & INSN2_VU0_CHANNEL_SUFFIX) != 0 && opcode_extra == 0)
7671 insn->insn_opcode |= 0xf << mips_vu0_channel_mask.lsb;
7672 else
7673 insn->insn_opcode |= opcode_extra;
97d87491
RS
7674 memset (&arg, 0, sizeof (arg));
7675 arg.insn = insn;
7676 arg.token = tokens;
7677 arg.argnum = 1;
7678 arg.last_regno = ILLEGAL_REG;
7679 arg.dest_regno = ILLEGAL_REG;
60f20e8b 7680 arg.lax_match = lax_match;
97d87491
RS
7681 for (args = opcode->args;; ++args)
7682 {
7683 if (arg.token->type == OT_END)
7684 {
7685 /* Handle unary instructions in which only one operand is given.
7686 The source is then the same as the destination. */
7687 if (arg.opnum == 1 && *args == ',')
7688 {
7689 operand = (mips_opts.micromips
7690 ? decode_micromips_operand (args + 1)
7691 : decode_mips_operand (args + 1));
7692 if (operand && mips_optional_operand_p (operand))
7693 {
7694 arg.token = tokens;
7695 arg.argnum = 1;
7696 continue;
7697 }
7698 }
7699
7700 /* Treat elided base registers as $0. */
7701 if (strcmp (args, "(b)") == 0)
7702 args += 3;
7703
7704 if (args[0] == '+')
7705 switch (args[1])
7706 {
7707 case 'K':
7708 case 'N':
7709 /* The register suffix is optional. */
7710 args += 2;
7711 break;
7712 }
7713
7714 /* Fail the match if there were too few operands. */
7715 if (*args)
7716 return FALSE;
7717
7718 /* Successful match. */
60f20e8b
RS
7719 if (!complete_p)
7720 return TRUE;
e3de51ce 7721 clear_insn_error ();
97d87491
RS
7722 if (arg.dest_regno == arg.last_regno
7723 && strncmp (insn->insn_mo->name, "jalr", 4) == 0)
7724 {
7725 if (arg.opnum == 2)
e3de51ce 7726 set_insn_error
1661c76c 7727 (0, _("source and destination must be different"));
97d87491 7728 else if (arg.last_regno == 31)
e3de51ce 7729 set_insn_error
1661c76c 7730 (0, _("a destination register must be supplied"));
97d87491 7731 }
173d3447
CF
7732 else if (arg.last_regno == 31
7733 && (strncmp (insn->insn_mo->name, "bltzal", 6) == 0
7734 || strncmp (insn->insn_mo->name, "bgezal", 6) == 0))
7735 set_insn_error (0, _("the source register must not be $31"));
97d87491
RS
7736 check_completed_insn (&arg);
7737 return TRUE;
7738 }
7739
7740 /* Fail the match if the line has too many operands. */
7741 if (*args == 0)
7742 return FALSE;
7743
7744 /* Handle characters that need to match exactly. */
7745 if (*args == '(' || *args == ')' || *args == ',')
7746 {
7747 if (match_char (&arg, *args))
7748 continue;
7749 return FALSE;
7750 }
7751 if (*args == '#')
7752 {
7753 ++args;
7754 if (arg.token->type == OT_DOUBLE_CHAR
7755 && arg.token->u.ch == *args)
7756 {
7757 ++arg.token;
7758 continue;
7759 }
7760 return FALSE;
7761 }
7762
7763 /* Handle special macro operands. Work out the properties of
7764 other operands. */
7765 arg.opnum += 1;
97d87491
RS
7766 switch (*args)
7767 {
7361da2c
AB
7768 case '-':
7769 switch (args[1])
7770 {
7771 case 'A':
7772 *offset_reloc = BFD_RELOC_MIPS_19_PCREL_S2;
7773 break;
7774
7775 case 'B':
7776 *offset_reloc = BFD_RELOC_MIPS_18_PCREL_S3;
7777 break;
7778 }
7779 break;
7780
97d87491
RS
7781 case '+':
7782 switch (args[1])
7783 {
97d87491
RS
7784 case 'i':
7785 *offset_reloc = BFD_RELOC_MIPS_JMP;
7786 break;
7361da2c
AB
7787
7788 case '\'':
7789 *offset_reloc = BFD_RELOC_MIPS_26_PCREL_S2;
7790 break;
7791
7792 case '\"':
7793 *offset_reloc = BFD_RELOC_MIPS_21_PCREL_S2;
7794 break;
97d87491
RS
7795 }
7796 break;
7797
97d87491 7798 case 'I':
1a00e612
RS
7799 if (!match_const_int (&arg, &imm_expr.X_add_number))
7800 return FALSE;
7801 imm_expr.X_op = O_constant;
bad1aba3 7802 if (GPR_SIZE == 32)
97d87491
RS
7803 normalize_constant_expr (&imm_expr);
7804 continue;
7805
7806 case 'A':
7807 if (arg.token->type == OT_CHAR && arg.token->u.ch == '(')
7808 {
7809 /* Assume that the offset has been elided and that what
7810 we saw was a base register. The match will fail later
7811 if that assumption turns out to be wrong. */
7812 offset_expr.X_op = O_constant;
7813 offset_expr.X_add_number = 0;
7814 }
97d87491 7815 else
1a00e612
RS
7816 {
7817 if (!match_expression (&arg, &offset_expr, offset_reloc))
7818 return FALSE;
7819 normalize_address_expr (&offset_expr);
7820 }
97d87491
RS
7821 continue;
7822
7823 case 'F':
7824 if (!match_float_constant (&arg, &imm_expr, &offset_expr,
7825 8, TRUE))
1a00e612 7826 return FALSE;
97d87491
RS
7827 continue;
7828
7829 case 'L':
7830 if (!match_float_constant (&arg, &imm_expr, &offset_expr,
7831 8, FALSE))
1a00e612 7832 return FALSE;
97d87491
RS
7833 continue;
7834
7835 case 'f':
7836 if (!match_float_constant (&arg, &imm_expr, &offset_expr,
7837 4, TRUE))
1a00e612 7838 return FALSE;
97d87491
RS
7839 continue;
7840
7841 case 'l':
7842 if (!match_float_constant (&arg, &imm_expr, &offset_expr,
7843 4, FALSE))
1a00e612 7844 return FALSE;
97d87491
RS
7845 continue;
7846
97d87491
RS
7847 case 'p':
7848 *offset_reloc = BFD_RELOC_16_PCREL_S2;
7849 break;
7850
7851 case 'a':
7852 *offset_reloc = BFD_RELOC_MIPS_JMP;
7853 break;
7854
7855 case 'm':
7856 gas_assert (mips_opts.micromips);
7857 c = args[1];
7858 switch (c)
7859 {
7860 case 'D':
7861 case 'E':
7862 if (!forced_insn_length)
7863 *offset_reloc = (int) BFD_RELOC_UNUSED + c;
7864 else if (c == 'D')
7865 *offset_reloc = BFD_RELOC_MICROMIPS_10_PCREL_S1;
7866 else
7867 *offset_reloc = BFD_RELOC_MICROMIPS_7_PCREL_S1;
7868 break;
7869 }
7870 break;
7871 }
7872
7873 operand = (mips_opts.micromips
7874 ? decode_micromips_operand (args)
7875 : decode_mips_operand (args));
7876 if (!operand)
7877 abort ();
7878
7879 /* Skip prefixes. */
7361da2c 7880 if (*args == '+' || *args == 'm' || *args == '-')
97d87491
RS
7881 args++;
7882
7883 if (mips_optional_operand_p (operand)
7884 && args[1] == ','
7885 && (arg.token[0].type != OT_REG
7886 || arg.token[1].type == OT_END))
7887 {
7888 /* Assume that the register has been elided and is the
7889 same as the first operand. */
7890 arg.token = tokens;
7891 arg.argnum = 1;
7892 }
7893
7894 if (!match_operand (&arg, operand))
7895 return FALSE;
7896 }
7897}
7898
7899/* Like match_insn, but for MIPS16. */
7900
7901static bfd_boolean
7902match_mips16_insn (struct mips_cl_insn *insn, const struct mips_opcode *opcode,
1a00e612 7903 struct mips_operand_token *tokens)
97d87491
RS
7904{
7905 const char *args;
7906 const struct mips_operand *operand;
7907 const struct mips_operand *ext_operand;
7908 struct mips_arg_info arg;
7909 int relax_char;
7910
7911 create_insn (insn, opcode);
7912 imm_expr.X_op = O_absent;
97d87491
RS
7913 offset_expr.X_op = O_absent;
7914 offset_reloc[0] = BFD_RELOC_UNUSED;
7915 offset_reloc[1] = BFD_RELOC_UNUSED;
7916 offset_reloc[2] = BFD_RELOC_UNUSED;
7917 relax_char = 0;
7918
7919 memset (&arg, 0, sizeof (arg));
7920 arg.insn = insn;
7921 arg.token = tokens;
7922 arg.argnum = 1;
7923 arg.last_regno = ILLEGAL_REG;
7924 arg.dest_regno = ILLEGAL_REG;
97d87491
RS
7925 relax_char = 0;
7926 for (args = opcode->args;; ++args)
7927 {
7928 int c;
7929
7930 if (arg.token->type == OT_END)
7931 {
7932 offsetT value;
7933
7934 /* Handle unary instructions in which only one operand is given.
7935 The source is then the same as the destination. */
7936 if (arg.opnum == 1 && *args == ',')
7937 {
7938 operand = decode_mips16_operand (args[1], FALSE);
7939 if (operand && mips_optional_operand_p (operand))
7940 {
7941 arg.token = tokens;
7942 arg.argnum = 1;
7943 continue;
7944 }
7945 }
7946
7947 /* Fail the match if there were too few operands. */
7948 if (*args)
7949 return FALSE;
7950
7951 /* Successful match. Stuff the immediate value in now, if
7952 we can. */
e3de51ce 7953 clear_insn_error ();
97d87491
RS
7954 if (opcode->pinfo == INSN_MACRO)
7955 {
7956 gas_assert (relax_char == 0 || relax_char == 'p');
7957 gas_assert (*offset_reloc == BFD_RELOC_UNUSED);
7958 }
7959 else if (relax_char
7960 && offset_expr.X_op == O_constant
7961 && calculate_reloc (*offset_reloc,
7962 offset_expr.X_add_number,
7963 &value))
7964 {
7965 mips16_immed (NULL, 0, relax_char, *offset_reloc, value,
7966 forced_insn_length, &insn->insn_opcode);
7967 offset_expr.X_op = O_absent;
7968 *offset_reloc = BFD_RELOC_UNUSED;
7969 }
7970 else if (relax_char && *offset_reloc != BFD_RELOC_UNUSED)
7971 {
7972 if (forced_insn_length == 2)
e3de51ce 7973 set_insn_error (0, _("invalid unextended operand value"));
97d87491
RS
7974 forced_insn_length = 4;
7975 insn->insn_opcode |= MIPS16_EXTEND;
7976 }
7977 else if (relax_char)
7978 *offset_reloc = (int) BFD_RELOC_UNUSED + relax_char;
7979
7980 check_completed_insn (&arg);
7981 return TRUE;
7982 }
7983
7984 /* Fail the match if the line has too many operands. */
7985 if (*args == 0)
7986 return FALSE;
7987
7988 /* Handle characters that need to match exactly. */
7989 if (*args == '(' || *args == ')' || *args == ',')
7990 {
7991 if (match_char (&arg, *args))
7992 continue;
7993 return FALSE;
7994 }
7995
7996 arg.opnum += 1;
7997 c = *args;
7998 switch (c)
7999 {
8000 case 'p':
8001 case 'q':
8002 case 'A':
8003 case 'B':
8004 case 'E':
8005 relax_char = c;
8006 break;
8007
8008 case 'I':
1a00e612
RS
8009 if (!match_const_int (&arg, &imm_expr.X_add_number))
8010 return FALSE;
8011 imm_expr.X_op = O_constant;
bad1aba3 8012 if (GPR_SIZE == 32)
97d87491
RS
8013 normalize_constant_expr (&imm_expr);
8014 continue;
8015
8016 case 'a':
8017 case 'i':
8018 *offset_reloc = BFD_RELOC_MIPS16_JMP;
8019 insn->insn_opcode <<= 16;
8020 break;
8021 }
8022
8023 operand = decode_mips16_operand (c, FALSE);
8024 if (!operand)
8025 abort ();
8026
8027 /* '6' is a special case. It is used for BREAK and SDBBP,
8028 whose operands are only meaningful to the software that decodes
8029 them. This means that there is no architectural reason why
8030 they cannot be prefixed by EXTEND, but in practice,
8031 exception handlers will only look at the instruction
8032 itself. We therefore allow '6' to be extended when
8033 disassembling but not when assembling. */
8034 if (operand->type != OP_PCREL && c != '6')
8035 {
8036 ext_operand = decode_mips16_operand (c, TRUE);
8037 if (operand != ext_operand)
8038 {
8039 if (arg.token->type == OT_CHAR && arg.token->u.ch == '(')
8040 {
8041 offset_expr.X_op = O_constant;
8042 offset_expr.X_add_number = 0;
8043 relax_char = c;
8044 continue;
8045 }
8046
8047 /* We need the OT_INTEGER check because some MIPS16
8048 immediate variants are listed before the register ones. */
8049 if (arg.token->type != OT_INTEGER
8050 || !match_expression (&arg, &offset_expr, offset_reloc))
8051 return FALSE;
8052
8053 /* '8' is used for SLTI(U) and has traditionally not
8054 been allowed to take relocation operators. */
8055 if (offset_reloc[0] != BFD_RELOC_UNUSED
8056 && (ext_operand->size != 16 || c == '8'))
8057 return FALSE;
8058
8059 relax_char = c;
8060 continue;
8061 }
8062 }
8063
8064 if (mips_optional_operand_p (operand)
8065 && args[1] == ','
8066 && (arg.token[0].type != OT_REG
8067 || arg.token[1].type == OT_END))
8068 {
8069 /* Assume that the register has been elided and is the
8070 same as the first operand. */
8071 arg.token = tokens;
8072 arg.argnum = 1;
8073 }
8074
8075 if (!match_operand (&arg, operand))
8076 return FALSE;
8077 }
8078}
8079
60f20e8b
RS
8080/* Record that the current instruction is invalid for the current ISA. */
8081
8082static void
8083match_invalid_for_isa (void)
8084{
8085 set_insn_error_ss
1661c76c 8086 (0, _("opcode not supported on this processor: %s (%s)"),
60f20e8b
RS
8087 mips_cpu_info_from_arch (mips_opts.arch)->name,
8088 mips_cpu_info_from_isa (mips_opts.isa)->name);
8089}
8090
8091/* Try to match TOKENS against a series of opcode entries, starting at FIRST.
8092 Return true if a definite match or failure was found, storing any match
8093 in INSN. OPCODE_EXTRA is a value that should be ORed into the opcode
8094 (to handle things like VU0 suffixes). LAX_MATCH is true if we have already
8095 tried and failed to match under normal conditions and now want to try a
8096 more relaxed match. */
8097
8098static bfd_boolean
8099match_insns (struct mips_cl_insn *insn, const struct mips_opcode *first,
8100 const struct mips_opcode *past, struct mips_operand_token *tokens,
8101 int opcode_extra, bfd_boolean lax_match)
8102{
8103 const struct mips_opcode *opcode;
8104 const struct mips_opcode *invalid_delay_slot;
8105 bfd_boolean seen_valid_for_isa, seen_valid_for_size;
8106
8107 /* Search for a match, ignoring alternatives that don't satisfy the
8108 current ISA or forced_length. */
8109 invalid_delay_slot = 0;
8110 seen_valid_for_isa = FALSE;
8111 seen_valid_for_size = FALSE;
8112 opcode = first;
8113 do
8114 {
8115 gas_assert (strcmp (opcode->name, first->name) == 0);
8116 if (is_opcode_valid (opcode))
8117 {
8118 seen_valid_for_isa = TRUE;
8119 if (is_size_valid (opcode))
8120 {
8121 bfd_boolean delay_slot_ok;
8122
8123 seen_valid_for_size = TRUE;
8124 delay_slot_ok = is_delay_slot_valid (opcode);
8125 if (match_insn (insn, opcode, tokens, opcode_extra,
8126 lax_match, delay_slot_ok))
8127 {
8128 if (!delay_slot_ok)
8129 {
8130 if (!invalid_delay_slot)
8131 invalid_delay_slot = opcode;
8132 }
8133 else
8134 return TRUE;
8135 }
8136 }
8137 }
8138 ++opcode;
8139 }
8140 while (opcode < past && strcmp (opcode->name, first->name) == 0);
8141
8142 /* If the only matches we found had the wrong length for the delay slot,
8143 pick the first such match. We'll issue an appropriate warning later. */
8144 if (invalid_delay_slot)
8145 {
8146 if (match_insn (insn, invalid_delay_slot, tokens, opcode_extra,
8147 lax_match, TRUE))
8148 return TRUE;
8149 abort ();
8150 }
8151
8152 /* Handle the case where we didn't try to match an instruction because
8153 all the alternatives were incompatible with the current ISA. */
8154 if (!seen_valid_for_isa)
8155 {
8156 match_invalid_for_isa ();
8157 return TRUE;
8158 }
8159
8160 /* Handle the case where we didn't try to match an instruction because
8161 all the alternatives were of the wrong size. */
8162 if (!seen_valid_for_size)
8163 {
8164 if (mips_opts.insn32)
1661c76c 8165 set_insn_error (0, _("opcode not supported in the `insn32' mode"));
60f20e8b
RS
8166 else
8167 set_insn_error_i
1661c76c 8168 (0, _("unrecognized %d-bit version of microMIPS opcode"),
60f20e8b
RS
8169 8 * forced_insn_length);
8170 return TRUE;
8171 }
8172
8173 return FALSE;
8174}
8175
8176/* Like match_insns, but for MIPS16. */
8177
8178static bfd_boolean
8179match_mips16_insns (struct mips_cl_insn *insn, const struct mips_opcode *first,
8180 struct mips_operand_token *tokens)
8181{
8182 const struct mips_opcode *opcode;
8183 bfd_boolean seen_valid_for_isa;
8184
8185 /* Search for a match, ignoring alternatives that don't satisfy the
8186 current ISA. There are no separate entries for extended forms so
8187 we deal with forced_length later. */
8188 seen_valid_for_isa = FALSE;
8189 opcode = first;
8190 do
8191 {
8192 gas_assert (strcmp (opcode->name, first->name) == 0);
8193 if (is_opcode_valid_16 (opcode))
8194 {
8195 seen_valid_for_isa = TRUE;
8196 if (match_mips16_insn (insn, opcode, tokens))
8197 return TRUE;
8198 }
8199 ++opcode;
8200 }
8201 while (opcode < &mips16_opcodes[bfd_mips16_num_opcodes]
8202 && strcmp (opcode->name, first->name) == 0);
8203
8204 /* Handle the case where we didn't try to match an instruction because
8205 all the alternatives were incompatible with the current ISA. */
8206 if (!seen_valid_for_isa)
8207 {
8208 match_invalid_for_isa ();
8209 return TRUE;
8210 }
8211
8212 return FALSE;
8213}
8214
584892a6
RS
8215/* Set up global variables for the start of a new macro. */
8216
8217static void
8218macro_start (void)
8219{
8220 memset (&mips_macro_warning.sizes, 0, sizeof (mips_macro_warning.sizes));
df58fc94
RS
8221 memset (&mips_macro_warning.first_insn_sizes, 0,
8222 sizeof (mips_macro_warning.first_insn_sizes));
8223 memset (&mips_macro_warning.insns, 0, sizeof (mips_macro_warning.insns));
584892a6 8224 mips_macro_warning.delay_slot_p = (mips_opts.noreorder
11625dd8 8225 && delayed_branch_p (&history[0]));
df58fc94
RS
8226 switch (history[0].insn_mo->pinfo2
8227 & (INSN2_BRANCH_DELAY_32BIT | INSN2_BRANCH_DELAY_16BIT))
8228 {
8229 case INSN2_BRANCH_DELAY_32BIT:
8230 mips_macro_warning.delay_slot_length = 4;
8231 break;
8232 case INSN2_BRANCH_DELAY_16BIT:
8233 mips_macro_warning.delay_slot_length = 2;
8234 break;
8235 default:
8236 mips_macro_warning.delay_slot_length = 0;
8237 break;
8238 }
8239 mips_macro_warning.first_frag = NULL;
584892a6
RS
8240}
8241
df58fc94
RS
8242/* Given that a macro is longer than one instruction or of the wrong size,
8243 return the appropriate warning for it. Return null if no warning is
8244 needed. SUBTYPE is a bitmask of RELAX_DELAY_SLOT, RELAX_DELAY_SLOT_16BIT,
8245 RELAX_DELAY_SLOT_SIZE_FIRST, RELAX_DELAY_SLOT_SIZE_SECOND,
8246 and RELAX_NOMACRO. */
584892a6
RS
8247
8248static const char *
8249macro_warning (relax_substateT subtype)
8250{
8251 if (subtype & RELAX_DELAY_SLOT)
1661c76c 8252 return _("macro instruction expanded into multiple instructions"
584892a6
RS
8253 " in a branch delay slot");
8254 else if (subtype & RELAX_NOMACRO)
1661c76c 8255 return _("macro instruction expanded into multiple instructions");
df58fc94
RS
8256 else if (subtype & (RELAX_DELAY_SLOT_SIZE_FIRST
8257 | RELAX_DELAY_SLOT_SIZE_SECOND))
8258 return ((subtype & RELAX_DELAY_SLOT_16BIT)
1661c76c 8259 ? _("macro instruction expanded into a wrong size instruction"
df58fc94 8260 " in a 16-bit branch delay slot")
1661c76c 8261 : _("macro instruction expanded into a wrong size instruction"
df58fc94 8262 " in a 32-bit branch delay slot"));
584892a6
RS
8263 else
8264 return 0;
8265}
8266
8267/* Finish up a macro. Emit warnings as appropriate. */
8268
8269static void
8270macro_end (void)
8271{
df58fc94
RS
8272 /* Relaxation warning flags. */
8273 relax_substateT subtype = 0;
8274
8275 /* Check delay slot size requirements. */
8276 if (mips_macro_warning.delay_slot_length == 2)
8277 subtype |= RELAX_DELAY_SLOT_16BIT;
8278 if (mips_macro_warning.delay_slot_length != 0)
584892a6 8279 {
df58fc94
RS
8280 if (mips_macro_warning.delay_slot_length
8281 != mips_macro_warning.first_insn_sizes[0])
8282 subtype |= RELAX_DELAY_SLOT_SIZE_FIRST;
8283 if (mips_macro_warning.delay_slot_length
8284 != mips_macro_warning.first_insn_sizes[1])
8285 subtype |= RELAX_DELAY_SLOT_SIZE_SECOND;
8286 }
584892a6 8287
df58fc94
RS
8288 /* Check instruction count requirements. */
8289 if (mips_macro_warning.insns[0] > 1 || mips_macro_warning.insns[1] > 1)
8290 {
8291 if (mips_macro_warning.insns[1] > mips_macro_warning.insns[0])
584892a6
RS
8292 subtype |= RELAX_SECOND_LONGER;
8293 if (mips_opts.warn_about_macros)
8294 subtype |= RELAX_NOMACRO;
8295 if (mips_macro_warning.delay_slot_p)
8296 subtype |= RELAX_DELAY_SLOT;
df58fc94 8297 }
584892a6 8298
df58fc94
RS
8299 /* If both alternatives fail to fill a delay slot correctly,
8300 emit the warning now. */
8301 if ((subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0
8302 && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0)
8303 {
8304 relax_substateT s;
8305 const char *msg;
8306
8307 s = subtype & (RELAX_DELAY_SLOT_16BIT
8308 | RELAX_DELAY_SLOT_SIZE_FIRST
8309 | RELAX_DELAY_SLOT_SIZE_SECOND);
8310 msg = macro_warning (s);
8311 if (msg != NULL)
8312 as_warn ("%s", msg);
8313 subtype &= ~s;
8314 }
8315
8316 /* If both implementations are longer than 1 instruction, then emit the
8317 warning now. */
8318 if (mips_macro_warning.insns[0] > 1 && mips_macro_warning.insns[1] > 1)
8319 {
8320 relax_substateT s;
8321 const char *msg;
8322
8323 s = subtype & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT);
8324 msg = macro_warning (s);
8325 if (msg != NULL)
8326 as_warn ("%s", msg);
8327 subtype &= ~s;
584892a6 8328 }
df58fc94
RS
8329
8330 /* If any flags still set, then one implementation might need a warning
8331 and the other either will need one of a different kind or none at all.
8332 Pass any remaining flags over to relaxation. */
8333 if (mips_macro_warning.first_frag != NULL)
8334 mips_macro_warning.first_frag->fr_subtype |= subtype;
584892a6
RS
8335}
8336
df58fc94
RS
8337/* Instruction operand formats used in macros that vary between
8338 standard MIPS and microMIPS code. */
8339
833794fc 8340static const char * const brk_fmt[2][2] = { { "c", "c" }, { "mF", "c" } };
df58fc94
RS
8341static const char * const cop12_fmt[2] = { "E,o(b)", "E,~(b)" };
8342static const char * const jalr_fmt[2] = { "d,s", "t,s" };
8343static const char * const lui_fmt[2] = { "t,u", "s,u" };
8344static const char * const mem12_fmt[2] = { "t,o(b)", "t,~(b)" };
833794fc 8345static const char * const mfhl_fmt[2][2] = { { "d", "d" }, { "mj", "s" } };
df58fc94
RS
8346static const char * const shft_fmt[2] = { "d,w,<", "t,r,<" };
8347static const char * const trap_fmt[2] = { "s,t,q", "s,t,|" };
8348
833794fc 8349#define BRK_FMT (brk_fmt[mips_opts.micromips][mips_opts.insn32])
7361da2c
AB
8350#define COP12_FMT (ISA_IS_R6 (mips_opts.isa) ? "E,+:(d)" \
8351 : cop12_fmt[mips_opts.micromips])
df58fc94
RS
8352#define JALR_FMT (jalr_fmt[mips_opts.micromips])
8353#define LUI_FMT (lui_fmt[mips_opts.micromips])
8354#define MEM12_FMT (mem12_fmt[mips_opts.micromips])
7361da2c
AB
8355#define LL_SC_FMT (ISA_IS_R6 (mips_opts.isa) ? "t,+j(b)" \
8356 : mem12_fmt[mips_opts.micromips])
833794fc 8357#define MFHL_FMT (mfhl_fmt[mips_opts.micromips][mips_opts.insn32])
df58fc94
RS
8358#define SHFT_FMT (shft_fmt[mips_opts.micromips])
8359#define TRAP_FMT (trap_fmt[mips_opts.micromips])
8360
6e1304d8
RS
8361/* Read a macro's relocation codes from *ARGS and store them in *R.
8362 The first argument in *ARGS will be either the code for a single
8363 relocation or -1 followed by the three codes that make up a
8364 composite relocation. */
8365
8366static void
8367macro_read_relocs (va_list *args, bfd_reloc_code_real_type *r)
8368{
8369 int i, next;
8370
8371 next = va_arg (*args, int);
8372 if (next >= 0)
8373 r[0] = (bfd_reloc_code_real_type) next;
8374 else
f2ae14a1
RS
8375 {
8376 for (i = 0; i < 3; i++)
8377 r[i] = (bfd_reloc_code_real_type) va_arg (*args, int);
8378 /* This function is only used for 16-bit relocation fields.
8379 To make the macro code simpler, treat an unrelocated value
8380 in the same way as BFD_RELOC_LO16. */
8381 if (r[0] == BFD_RELOC_UNUSED)
8382 r[0] = BFD_RELOC_LO16;
8383 }
6e1304d8
RS
8384}
8385
252b5132
RH
8386/* Build an instruction created by a macro expansion. This is passed
8387 a pointer to the count of instructions created so far, an
8388 expression, the name of the instruction to build, an operand format
8389 string, and corresponding arguments. */
8390
252b5132 8391static void
67c0d1eb 8392macro_build (expressionS *ep, const char *name, const char *fmt, ...)
252b5132 8393{
df58fc94 8394 const struct mips_opcode *mo = NULL;
f6688943 8395 bfd_reloc_code_real_type r[3];
df58fc94 8396 const struct mips_opcode *amo;
e077a1c8 8397 const struct mips_operand *operand;
df58fc94
RS
8398 struct hash_control *hash;
8399 struct mips_cl_insn insn;
252b5132 8400 va_list args;
e077a1c8 8401 unsigned int uval;
252b5132 8402
252b5132 8403 va_start (args, fmt);
252b5132 8404
252b5132
RH
8405 if (mips_opts.mips16)
8406 {
03ea81db 8407 mips16_macro_build (ep, name, fmt, &args);
252b5132
RH
8408 va_end (args);
8409 return;
8410 }
8411
f6688943
TS
8412 r[0] = BFD_RELOC_UNUSED;
8413 r[1] = BFD_RELOC_UNUSED;
8414 r[2] = BFD_RELOC_UNUSED;
df58fc94
RS
8415 hash = mips_opts.micromips ? micromips_op_hash : op_hash;
8416 amo = (struct mips_opcode *) hash_find (hash, name);
8417 gas_assert (amo);
8418 gas_assert (strcmp (name, amo->name) == 0);
1e915849 8419
df58fc94 8420 do
8b082fb1
TS
8421 {
8422 /* Search until we get a match for NAME. It is assumed here that
df58fc94
RS
8423 macros will never generate MDMX, MIPS-3D, or MT instructions.
8424 We try to match an instruction that fulfils the branch delay
8425 slot instruction length requirement (if any) of the previous
8426 instruction. While doing this we record the first instruction
8427 seen that matches all the other conditions and use it anyway
8428 if the requirement cannot be met; we will issue an appropriate
8429 warning later on. */
8430 if (strcmp (fmt, amo->args) == 0
8431 && amo->pinfo != INSN_MACRO
8432 && is_opcode_valid (amo)
8433 && is_size_valid (amo))
8434 {
8435 if (is_delay_slot_valid (amo))
8436 {
8437 mo = amo;
8438 break;
8439 }
8440 else if (!mo)
8441 mo = amo;
8442 }
8b082fb1 8443
df58fc94
RS
8444 ++amo;
8445 gas_assert (amo->name);
252b5132 8446 }
df58fc94 8447 while (strcmp (name, amo->name) == 0);
252b5132 8448
df58fc94 8449 gas_assert (mo);
1e915849 8450 create_insn (&insn, mo);
e077a1c8 8451 for (; *fmt; ++fmt)
252b5132 8452 {
e077a1c8 8453 switch (*fmt)
252b5132 8454 {
252b5132
RH
8455 case ',':
8456 case '(':
8457 case ')':
252b5132 8458 case 'z':
e077a1c8 8459 break;
252b5132
RH
8460
8461 case 'i':
8462 case 'j':
6e1304d8 8463 macro_read_relocs (&args, r);
9c2799c2 8464 gas_assert (*r == BFD_RELOC_GPREL16
e391c024
RS
8465 || *r == BFD_RELOC_MIPS_HIGHER
8466 || *r == BFD_RELOC_HI16_S
8467 || *r == BFD_RELOC_LO16
8468 || *r == BFD_RELOC_MIPS_GOT_OFST);
e077a1c8 8469 break;
e391c024
RS
8470
8471 case 'o':
8472 macro_read_relocs (&args, r);
e077a1c8 8473 break;
252b5132
RH
8474
8475 case 'u':
6e1304d8 8476 macro_read_relocs (&args, r);
9c2799c2 8477 gas_assert (ep != NULL
90ecf173
MR
8478 && (ep->X_op == O_constant
8479 || (ep->X_op == O_symbol
8480 && (*r == BFD_RELOC_MIPS_HIGHEST
8481 || *r == BFD_RELOC_HI16_S
8482 || *r == BFD_RELOC_HI16
8483 || *r == BFD_RELOC_GPREL16
8484 || *r == BFD_RELOC_MIPS_GOT_HI16
8485 || *r == BFD_RELOC_MIPS_CALL_HI16))));
e077a1c8 8486 break;
252b5132
RH
8487
8488 case 'p':
9c2799c2 8489 gas_assert (ep != NULL);
bad36eac 8490
252b5132
RH
8491 /*
8492 * This allows macro() to pass an immediate expression for
8493 * creating short branches without creating a symbol.
bad36eac
DJ
8494 *
8495 * We don't allow branch relaxation for these branches, as
8496 * they should only appear in ".set nomacro" anyway.
252b5132
RH
8497 */
8498 if (ep->X_op == O_constant)
8499 {
df58fc94
RS
8500 /* For microMIPS we always use relocations for branches.
8501 So we should not resolve immediate values. */
8502 gas_assert (!mips_opts.micromips);
8503
bad36eac
DJ
8504 if ((ep->X_add_number & 3) != 0)
8505 as_bad (_("branch to misaligned address (0x%lx)"),
8506 (unsigned long) ep->X_add_number);
8507 if ((ep->X_add_number + 0x20000) & ~0x3ffff)
8508 as_bad (_("branch address range overflow (0x%lx)"),
8509 (unsigned long) ep->X_add_number);
252b5132
RH
8510 insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff;
8511 ep = NULL;
8512 }
8513 else
0b25d3e6 8514 *r = BFD_RELOC_16_PCREL_S2;
e077a1c8 8515 break;
252b5132
RH
8516
8517 case 'a':
9c2799c2 8518 gas_assert (ep != NULL);
f6688943 8519 *r = BFD_RELOC_MIPS_JMP;
e077a1c8 8520 break;
d43b4baf 8521
252b5132 8522 default:
e077a1c8
RS
8523 operand = (mips_opts.micromips
8524 ? decode_micromips_operand (fmt)
8525 : decode_mips_operand (fmt));
8526 if (!operand)
8527 abort ();
8528
8529 uval = va_arg (args, int);
8530 if (operand->type == OP_CLO_CLZ_DEST)
8531 uval |= (uval << 5);
8532 insn_insert_operand (&insn, operand, uval);
8533
7361da2c 8534 if (*fmt == '+' || *fmt == 'm' || *fmt == '-')
e077a1c8
RS
8535 ++fmt;
8536 break;
252b5132 8537 }
252b5132
RH
8538 }
8539 va_end (args);
9c2799c2 8540 gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
252b5132 8541
df58fc94 8542 append_insn (&insn, ep, r, TRUE);
252b5132
RH
8543}
8544
8545static void
67c0d1eb 8546mips16_macro_build (expressionS *ep, const char *name, const char *fmt,
03ea81db 8547 va_list *args)
252b5132 8548{
1e915849 8549 struct mips_opcode *mo;
252b5132 8550 struct mips_cl_insn insn;
e077a1c8 8551 const struct mips_operand *operand;
f6688943
TS
8552 bfd_reloc_code_real_type r[3]
8553 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
252b5132 8554
1e915849 8555 mo = (struct mips_opcode *) hash_find (mips16_op_hash, name);
9c2799c2
NC
8556 gas_assert (mo);
8557 gas_assert (strcmp (name, mo->name) == 0);
252b5132 8558
1e915849 8559 while (strcmp (fmt, mo->args) != 0 || mo->pinfo == INSN_MACRO)
252b5132 8560 {
1e915849 8561 ++mo;
9c2799c2
NC
8562 gas_assert (mo->name);
8563 gas_assert (strcmp (name, mo->name) == 0);
252b5132
RH
8564 }
8565
1e915849 8566 create_insn (&insn, mo);
e077a1c8 8567 for (; *fmt; ++fmt)
252b5132
RH
8568 {
8569 int c;
8570
e077a1c8 8571 c = *fmt;
252b5132
RH
8572 switch (c)
8573 {
252b5132
RH
8574 case ',':
8575 case '(':
8576 case ')':
e077a1c8 8577 break;
252b5132
RH
8578
8579 case '0':
8580 case 'S':
8581 case 'P':
8582 case 'R':
e077a1c8 8583 break;
252b5132
RH
8584
8585 case '<':
8586 case '>':
8587 case '4':
8588 case '5':
8589 case 'H':
8590 case 'W':
8591 case 'D':
8592 case 'j':
8593 case '8':
8594 case 'V':
8595 case 'C':
8596 case 'U':
8597 case 'k':
8598 case 'K':
8599 case 'p':
8600 case 'q':
8601 {
b886a2ab
RS
8602 offsetT value;
8603
9c2799c2 8604 gas_assert (ep != NULL);
252b5132
RH
8605
8606 if (ep->X_op != O_constant)
874e8986 8607 *r = (int) BFD_RELOC_UNUSED + c;
b886a2ab 8608 else if (calculate_reloc (*r, ep->X_add_number, &value))
252b5132 8609 {
b886a2ab 8610 mips16_immed (NULL, 0, c, *r, value, 0, &insn.insn_opcode);
252b5132 8611 ep = NULL;
f6688943 8612 *r = BFD_RELOC_UNUSED;
252b5132
RH
8613 }
8614 }
e077a1c8 8615 break;
252b5132 8616
e077a1c8
RS
8617 default:
8618 operand = decode_mips16_operand (c, FALSE);
8619 if (!operand)
8620 abort ();
252b5132 8621
4a06e5a2 8622 insn_insert_operand (&insn, operand, va_arg (*args, int));
e077a1c8
RS
8623 break;
8624 }
252b5132
RH
8625 }
8626
9c2799c2 8627 gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
252b5132 8628
df58fc94 8629 append_insn (&insn, ep, r, TRUE);
252b5132
RH
8630}
8631
438c16b8
TS
8632/*
8633 * Generate a "jalr" instruction with a relocation hint to the called
8634 * function. This occurs in NewABI PIC code.
8635 */
8636static void
df58fc94 8637macro_build_jalr (expressionS *ep, int cprestore)
438c16b8 8638{
df58fc94
RS
8639 static const bfd_reloc_code_real_type jalr_relocs[2]
8640 = { BFD_RELOC_MIPS_JALR, BFD_RELOC_MICROMIPS_JALR };
8641 bfd_reloc_code_real_type jalr_reloc = jalr_relocs[mips_opts.micromips];
8642 const char *jalr;
685736be 8643 char *f = NULL;
b34976b6 8644
1180b5a4 8645 if (MIPS_JALR_HINT_P (ep))
f21f8242 8646 {
cc3d92a5 8647 frag_grow (8);
f21f8242
AO
8648 f = frag_more (0);
8649 }
2906b037 8650 if (mips_opts.micromips)
df58fc94 8651 {
833794fc
MR
8652 jalr = ((mips_opts.noreorder && !cprestore) || mips_opts.insn32
8653 ? "jalr" : "jalrs");
e64af278 8654 if (MIPS_JALR_HINT_P (ep)
833794fc 8655 || mips_opts.insn32
e64af278 8656 || (history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
df58fc94
RS
8657 macro_build (NULL, jalr, "t,s", RA, PIC_CALL_REG);
8658 else
8659 macro_build (NULL, jalr, "mj", PIC_CALL_REG);
8660 }
2906b037
MR
8661 else
8662 macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG);
1180b5a4 8663 if (MIPS_JALR_HINT_P (ep))
df58fc94 8664 fix_new_exp (frag_now, f - frag_now->fr_literal, 4, ep, FALSE, jalr_reloc);
438c16b8
TS
8665}
8666
252b5132
RH
8667/*
8668 * Generate a "lui" instruction.
8669 */
8670static void
67c0d1eb 8671macro_build_lui (expressionS *ep, int regnum)
252b5132 8672{
9c2799c2 8673 gas_assert (! mips_opts.mips16);
252b5132 8674
df58fc94 8675 if (ep->X_op != O_constant)
252b5132 8676 {
9c2799c2 8677 gas_assert (ep->X_op == O_symbol);
bbe506e8
TS
8678 /* _gp_disp is a special case, used from s_cpload.
8679 __gnu_local_gp is used if mips_no_shared. */
9c2799c2 8680 gas_assert (mips_pic == NO_PIC
78e1bb40 8681 || (! HAVE_NEWABI
aa6975fb
ILT
8682 && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0)
8683 || (! mips_in_shared
bbe506e8
TS
8684 && strcmp (S_GET_NAME (ep->X_add_symbol),
8685 "__gnu_local_gp") == 0));
252b5132
RH
8686 }
8687
df58fc94 8688 macro_build (ep, "lui", LUI_FMT, regnum, BFD_RELOC_HI16_S);
252b5132
RH
8689}
8690
885add95
CD
8691/* Generate a sequence of instructions to do a load or store from a constant
8692 offset off of a base register (breg) into/from a target register (treg),
8693 using AT if necessary. */
8694static void
67c0d1eb
RS
8695macro_build_ldst_constoffset (expressionS *ep, const char *op,
8696 int treg, int breg, int dbl)
885add95 8697{
9c2799c2 8698 gas_assert (ep->X_op == O_constant);
885add95 8699
256ab948 8700 /* Sign-extending 32-bit constants makes their handling easier. */
2051e8c4
MR
8701 if (!dbl)
8702 normalize_constant_expr (ep);
256ab948 8703
67c1ffbe 8704 /* Right now, this routine can only handle signed 32-bit constants. */
ecd13cd3 8705 if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000))
885add95
CD
8706 as_warn (_("operand overflow"));
8707
8708 if (IS_SEXT_16BIT_NUM(ep->X_add_number))
8709 {
8710 /* Signed 16-bit offset will fit in the op. Easy! */
67c0d1eb 8711 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, breg);
885add95
CD
8712 }
8713 else
8714 {
8715 /* 32-bit offset, need multiple instructions and AT, like:
8716 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
8717 addu $tempreg,$tempreg,$breg
8718 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
8719 to handle the complete offset. */
67c0d1eb
RS
8720 macro_build_lui (ep, AT);
8721 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
8722 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, AT);
885add95 8723
741fe287 8724 if (!mips_opts.at)
1661c76c 8725 as_bad (_("macro used $at after \".set noat\""));
885add95
CD
8726 }
8727}
8728
252b5132
RH
8729/* set_at()
8730 * Generates code to set the $at register to true (one)
8731 * if reg is less than the immediate expression.
8732 */
8733static void
67c0d1eb 8734set_at (int reg, int unsignedp)
252b5132 8735{
b0e6f033 8736 if (imm_expr.X_add_number >= -0x8000
252b5132 8737 && imm_expr.X_add_number < 0x8000)
67c0d1eb
RS
8738 macro_build (&imm_expr, unsignedp ? "sltiu" : "slti", "t,r,j",
8739 AT, reg, BFD_RELOC_LO16);
252b5132
RH
8740 else
8741 {
bad1aba3 8742 load_register (AT, &imm_expr, GPR_SIZE == 64);
67c0d1eb 8743 macro_build (NULL, unsignedp ? "sltu" : "slt", "d,v,t", AT, reg, AT);
252b5132
RH
8744 }
8745}
8746
252b5132
RH
8747/* Count the leading zeroes by performing a binary chop. This is a
8748 bulky bit of source, but performance is a LOT better for the
8749 majority of values than a simple loop to count the bits:
8750 for (lcnt = 0; (lcnt < 32); lcnt++)
8751 if ((v) & (1 << (31 - lcnt)))
8752 break;
8753 However it is not code size friendly, and the gain will drop a bit
8754 on certain cached systems.
8755*/
8756#define COUNT_TOP_ZEROES(v) \
8757 (((v) & ~0xffff) == 0 \
8758 ? ((v) & ~0xff) == 0 \
8759 ? ((v) & ~0xf) == 0 \
8760 ? ((v) & ~0x3) == 0 \
8761 ? ((v) & ~0x1) == 0 \
8762 ? !(v) \
8763 ? 32 \
8764 : 31 \
8765 : 30 \
8766 : ((v) & ~0x7) == 0 \
8767 ? 29 \
8768 : 28 \
8769 : ((v) & ~0x3f) == 0 \
8770 ? ((v) & ~0x1f) == 0 \
8771 ? 27 \
8772 : 26 \
8773 : ((v) & ~0x7f) == 0 \
8774 ? 25 \
8775 : 24 \
8776 : ((v) & ~0xfff) == 0 \
8777 ? ((v) & ~0x3ff) == 0 \
8778 ? ((v) & ~0x1ff) == 0 \
8779 ? 23 \
8780 : 22 \
8781 : ((v) & ~0x7ff) == 0 \
8782 ? 21 \
8783 : 20 \
8784 : ((v) & ~0x3fff) == 0 \
8785 ? ((v) & ~0x1fff) == 0 \
8786 ? 19 \
8787 : 18 \
8788 : ((v) & ~0x7fff) == 0 \
8789 ? 17 \
8790 : 16 \
8791 : ((v) & ~0xffffff) == 0 \
8792 ? ((v) & ~0xfffff) == 0 \
8793 ? ((v) & ~0x3ffff) == 0 \
8794 ? ((v) & ~0x1ffff) == 0 \
8795 ? 15 \
8796 : 14 \
8797 : ((v) & ~0x7ffff) == 0 \
8798 ? 13 \
8799 : 12 \
8800 : ((v) & ~0x3fffff) == 0 \
8801 ? ((v) & ~0x1fffff) == 0 \
8802 ? 11 \
8803 : 10 \
8804 : ((v) & ~0x7fffff) == 0 \
8805 ? 9 \
8806 : 8 \
8807 : ((v) & ~0xfffffff) == 0 \
8808 ? ((v) & ~0x3ffffff) == 0 \
8809 ? ((v) & ~0x1ffffff) == 0 \
8810 ? 7 \
8811 : 6 \
8812 : ((v) & ~0x7ffffff) == 0 \
8813 ? 5 \
8814 : 4 \
8815 : ((v) & ~0x3fffffff) == 0 \
8816 ? ((v) & ~0x1fffffff) == 0 \
8817 ? 3 \
8818 : 2 \
8819 : ((v) & ~0x7fffffff) == 0 \
8820 ? 1 \
8821 : 0)
8822
8823/* load_register()
67c1ffbe 8824 * This routine generates the least number of instructions necessary to load
252b5132
RH
8825 * an absolute expression value into a register.
8826 */
8827static void
67c0d1eb 8828load_register (int reg, expressionS *ep, int dbl)
252b5132
RH
8829{
8830 int freg;
8831 expressionS hi32, lo32;
8832
8833 if (ep->X_op != O_big)
8834 {
9c2799c2 8835 gas_assert (ep->X_op == O_constant);
256ab948
TS
8836
8837 /* Sign-extending 32-bit constants makes their handling easier. */
2051e8c4
MR
8838 if (!dbl)
8839 normalize_constant_expr (ep);
256ab948
TS
8840
8841 if (IS_SEXT_16BIT_NUM (ep->X_add_number))
252b5132
RH
8842 {
8843 /* We can handle 16 bit signed values with an addiu to
8844 $zero. No need to ever use daddiu here, since $zero and
8845 the result are always correct in 32 bit mode. */
67c0d1eb 8846 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
252b5132
RH
8847 return;
8848 }
8849 else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000)
8850 {
8851 /* We can handle 16 bit unsigned values with an ori to
8852 $zero. */
67c0d1eb 8853 macro_build (ep, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16);
252b5132
RH
8854 return;
8855 }
256ab948 8856 else if ((IS_SEXT_32BIT_NUM (ep->X_add_number)))
252b5132
RH
8857 {
8858 /* 32 bit values require an lui. */
df58fc94 8859 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_HI16);
252b5132 8860 if ((ep->X_add_number & 0xffff) != 0)
67c0d1eb 8861 macro_build (ep, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
252b5132
RH
8862 return;
8863 }
8864 }
8865
8866 /* The value is larger than 32 bits. */
8867
bad1aba3 8868 if (!dbl || GPR_SIZE == 32)
252b5132 8869 {
55e08f71
NC
8870 char value[32];
8871
8872 sprintf_vma (value, ep->X_add_number);
1661c76c 8873 as_bad (_("number (0x%s) larger than 32 bits"), value);
67c0d1eb 8874 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
252b5132
RH
8875 return;
8876 }
8877
8878 if (ep->X_op != O_big)
8879 {
8880 hi32 = *ep;
8881 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
8882 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
8883 hi32.X_add_number &= 0xffffffff;
8884 lo32 = *ep;
8885 lo32.X_add_number &= 0xffffffff;
8886 }
8887 else
8888 {
9c2799c2 8889 gas_assert (ep->X_add_number > 2);
252b5132
RH
8890 if (ep->X_add_number == 3)
8891 generic_bignum[3] = 0;
8892 else if (ep->X_add_number > 4)
1661c76c 8893 as_bad (_("number larger than 64 bits"));
252b5132
RH
8894 lo32.X_op = O_constant;
8895 lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16);
8896 hi32.X_op = O_constant;
8897 hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16);
8898 }
8899
8900 if (hi32.X_add_number == 0)
8901 freg = 0;
8902 else
8903 {
8904 int shift, bit;
8905 unsigned long hi, lo;
8906
956cd1d6 8907 if (hi32.X_add_number == (offsetT) 0xffffffff)
beae10d5
KH
8908 {
8909 if ((lo32.X_add_number & 0xffff8000) == 0xffff8000)
8910 {
67c0d1eb 8911 macro_build (&lo32, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
beae10d5
KH
8912 return;
8913 }
8914 if (lo32.X_add_number & 0x80000000)
8915 {
df58fc94 8916 macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16);
252b5132 8917 if (lo32.X_add_number & 0xffff)
67c0d1eb 8918 macro_build (&lo32, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
beae10d5
KH
8919 return;
8920 }
8921 }
252b5132
RH
8922
8923 /* Check for 16bit shifted constant. We know that hi32 is
8924 non-zero, so start the mask on the first bit of the hi32
8925 value. */
8926 shift = 17;
8927 do
beae10d5
KH
8928 {
8929 unsigned long himask, lomask;
8930
8931 if (shift < 32)
8932 {
8933 himask = 0xffff >> (32 - shift);
8934 lomask = (0xffff << shift) & 0xffffffff;
8935 }
8936 else
8937 {
8938 himask = 0xffff << (shift - 32);
8939 lomask = 0;
8940 }
8941 if ((hi32.X_add_number & ~(offsetT) himask) == 0
8942 && (lo32.X_add_number & ~(offsetT) lomask) == 0)
8943 {
8944 expressionS tmp;
8945
8946 tmp.X_op = O_constant;
8947 if (shift < 32)
8948 tmp.X_add_number = ((hi32.X_add_number << (32 - shift))
8949 | (lo32.X_add_number >> shift));
8950 else
8951 tmp.X_add_number = hi32.X_add_number >> (shift - 32);
67c0d1eb 8952 macro_build (&tmp, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16);
df58fc94 8953 macro_build (NULL, (shift >= 32) ? "dsll32" : "dsll", SHFT_FMT,
67c0d1eb 8954 reg, reg, (shift >= 32) ? shift - 32 : shift);
beae10d5
KH
8955 return;
8956 }
f9419b05 8957 ++shift;
beae10d5
KH
8958 }
8959 while (shift <= (64 - 16));
252b5132
RH
8960
8961 /* Find the bit number of the lowest one bit, and store the
8962 shifted value in hi/lo. */
8963 hi = (unsigned long) (hi32.X_add_number & 0xffffffff);
8964 lo = (unsigned long) (lo32.X_add_number & 0xffffffff);
8965 if (lo != 0)
8966 {
8967 bit = 0;
8968 while ((lo & 1) == 0)
8969 {
8970 lo >>= 1;
8971 ++bit;
8972 }
8973 lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit);
8974 hi >>= bit;
8975 }
8976 else
8977 {
8978 bit = 32;
8979 while ((hi & 1) == 0)
8980 {
8981 hi >>= 1;
8982 ++bit;
8983 }
8984 lo = hi;
8985 hi = 0;
8986 }
8987
8988 /* Optimize if the shifted value is a (power of 2) - 1. */
8989 if ((hi == 0 && ((lo + 1) & lo) == 0)
8990 || (lo == 0xffffffff && ((hi + 1) & hi) == 0))
beae10d5
KH
8991 {
8992 shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number);
252b5132 8993 if (shift != 0)
beae10d5 8994 {
252b5132
RH
8995 expressionS tmp;
8996
8997 /* This instruction will set the register to be all
8998 ones. */
beae10d5
KH
8999 tmp.X_op = O_constant;
9000 tmp.X_add_number = (offsetT) -1;
67c0d1eb 9001 macro_build (&tmp, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
beae10d5
KH
9002 if (bit != 0)
9003 {
9004 bit += shift;
df58fc94 9005 macro_build (NULL, (bit >= 32) ? "dsll32" : "dsll", SHFT_FMT,
67c0d1eb 9006 reg, reg, (bit >= 32) ? bit - 32 : bit);
beae10d5 9007 }
df58fc94 9008 macro_build (NULL, (shift >= 32) ? "dsrl32" : "dsrl", SHFT_FMT,
67c0d1eb 9009 reg, reg, (shift >= 32) ? shift - 32 : shift);
beae10d5
KH
9010 return;
9011 }
9012 }
252b5132
RH
9013
9014 /* Sign extend hi32 before calling load_register, because we can
9015 generally get better code when we load a sign extended value. */
9016 if ((hi32.X_add_number & 0x80000000) != 0)
beae10d5 9017 hi32.X_add_number |= ~(offsetT) 0xffffffff;
67c0d1eb 9018 load_register (reg, &hi32, 0);
252b5132
RH
9019 freg = reg;
9020 }
9021 if ((lo32.X_add_number & 0xffff0000) == 0)
9022 {
9023 if (freg != 0)
9024 {
df58fc94 9025 macro_build (NULL, "dsll32", SHFT_FMT, reg, freg, 0);
252b5132
RH
9026 freg = reg;
9027 }
9028 }
9029 else
9030 {
9031 expressionS mid16;
9032
956cd1d6 9033 if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff))
beae10d5 9034 {
df58fc94
RS
9035 macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16);
9036 macro_build (NULL, "dsrl32", SHFT_FMT, reg, reg, 0);
beae10d5
KH
9037 return;
9038 }
252b5132
RH
9039
9040 if (freg != 0)
9041 {
df58fc94 9042 macro_build (NULL, "dsll", SHFT_FMT, reg, freg, 16);
252b5132
RH
9043 freg = reg;
9044 }
9045 mid16 = lo32;
9046 mid16.X_add_number >>= 16;
67c0d1eb 9047 macro_build (&mid16, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
df58fc94 9048 macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16);
252b5132
RH
9049 freg = reg;
9050 }
9051 if ((lo32.X_add_number & 0xffff) != 0)
67c0d1eb 9052 macro_build (&lo32, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
252b5132
RH
9053}
9054
269137b2
TS
9055static inline void
9056load_delay_nop (void)
9057{
9058 if (!gpr_interlocks)
9059 macro_build (NULL, "nop", "");
9060}
9061
252b5132
RH
9062/* Load an address into a register. */
9063
9064static void
67c0d1eb 9065load_address (int reg, expressionS *ep, int *used_at)
252b5132 9066{
252b5132
RH
9067 if (ep->X_op != O_constant
9068 && ep->X_op != O_symbol)
9069 {
9070 as_bad (_("expression too complex"));
9071 ep->X_op = O_constant;
9072 }
9073
9074 if (ep->X_op == O_constant)
9075 {
67c0d1eb 9076 load_register (reg, ep, HAVE_64BIT_ADDRESSES);
252b5132
RH
9077 return;
9078 }
9079
9080 if (mips_pic == NO_PIC)
9081 {
9082 /* If this is a reference to a GP relative symbol, we want
cdf6fd85 9083 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
252b5132
RH
9084 Otherwise we want
9085 lui $reg,<sym> (BFD_RELOC_HI16_S)
9086 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
d6bc6245 9087 If we have an addend, we always use the latter form.
76b3015f 9088
d6bc6245
TS
9089 With 64bit address space and a usable $at we want
9090 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
9091 lui $at,<sym> (BFD_RELOC_HI16_S)
9092 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
9093 daddiu $at,<sym> (BFD_RELOC_LO16)
9094 dsll32 $reg,0
3a482fd5 9095 daddu $reg,$reg,$at
76b3015f 9096
c03099e6 9097 If $at is already in use, we use a path which is suboptimal
d6bc6245
TS
9098 on superscalar processors.
9099 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
9100 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
9101 dsll $reg,16
9102 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
9103 dsll $reg,16
9104 daddiu $reg,<sym> (BFD_RELOC_LO16)
6caf9ef4
TS
9105
9106 For GP relative symbols in 64bit address space we can use
9107 the same sequence as in 32bit address space. */
aed1a261 9108 if (HAVE_64BIT_SYMBOLS)
d6bc6245 9109 {
6caf9ef4
TS
9110 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
9111 && !nopic_need_relax (ep->X_add_symbol, 1))
9112 {
9113 relax_start (ep->X_add_symbol);
9114 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
9115 mips_gp_register, BFD_RELOC_GPREL16);
9116 relax_switch ();
9117 }
d6bc6245 9118
741fe287 9119 if (*used_at == 0 && mips_opts.at)
d6bc6245 9120 {
df58fc94
RS
9121 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST);
9122 macro_build (ep, "lui", LUI_FMT, AT, BFD_RELOC_HI16_S);
67c0d1eb
RS
9123 macro_build (ep, "daddiu", "t,r,j", reg, reg,
9124 BFD_RELOC_MIPS_HIGHER);
9125 macro_build (ep, "daddiu", "t,r,j", AT, AT, BFD_RELOC_LO16);
df58fc94 9126 macro_build (NULL, "dsll32", SHFT_FMT, reg, reg, 0);
67c0d1eb 9127 macro_build (NULL, "daddu", "d,v,t", reg, reg, AT);
d6bc6245
TS
9128 *used_at = 1;
9129 }
9130 else
9131 {
df58fc94 9132 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST);
67c0d1eb
RS
9133 macro_build (ep, "daddiu", "t,r,j", reg, reg,
9134 BFD_RELOC_MIPS_HIGHER);
df58fc94 9135 macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16);
67c0d1eb 9136 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_HI16_S);
df58fc94 9137 macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16);
67c0d1eb 9138 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_LO16);
d6bc6245 9139 }
6caf9ef4
TS
9140
9141 if (mips_relax.sequence)
9142 relax_end ();
d6bc6245 9143 }
252b5132
RH
9144 else
9145 {
d6bc6245 9146 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
6caf9ef4 9147 && !nopic_need_relax (ep->X_add_symbol, 1))
d6bc6245 9148 {
4d7206a2 9149 relax_start (ep->X_add_symbol);
67c0d1eb 9150 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
17a2f251 9151 mips_gp_register, BFD_RELOC_GPREL16);
4d7206a2 9152 relax_switch ();
d6bc6245 9153 }
67c0d1eb
RS
9154 macro_build_lui (ep, reg);
9155 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j",
9156 reg, reg, BFD_RELOC_LO16);
4d7206a2
RS
9157 if (mips_relax.sequence)
9158 relax_end ();
d6bc6245 9159 }
252b5132 9160 }
0a44bf69 9161 else if (!mips_big_got)
252b5132
RH
9162 {
9163 expressionS ex;
9164
9165 /* If this is a reference to an external symbol, we want
9166 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9167 Otherwise we want
9168 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9169 nop
9170 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
f5040a92
AO
9171 If there is a constant, it must be added in after.
9172
ed6fb7bd 9173 If we have NewABI, we want
f5040a92
AO
9174 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
9175 unless we're referencing a global symbol with a non-zero
9176 offset, in which case cst must be added separately. */
ed6fb7bd
SC
9177 if (HAVE_NEWABI)
9178 {
f5040a92
AO
9179 if (ep->X_add_number)
9180 {
4d7206a2 9181 ex.X_add_number = ep->X_add_number;
f5040a92 9182 ep->X_add_number = 0;
4d7206a2 9183 relax_start (ep->X_add_symbol);
67c0d1eb
RS
9184 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
9185 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
f5040a92
AO
9186 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
9187 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9188 ex.X_op = O_constant;
67c0d1eb 9189 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j",
17a2f251 9190 reg, reg, BFD_RELOC_LO16);
f5040a92 9191 ep->X_add_number = ex.X_add_number;
4d7206a2 9192 relax_switch ();
f5040a92 9193 }
67c0d1eb 9194 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
17a2f251 9195 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
4d7206a2
RS
9196 if (mips_relax.sequence)
9197 relax_end ();
ed6fb7bd
SC
9198 }
9199 else
9200 {
f5040a92
AO
9201 ex.X_add_number = ep->X_add_number;
9202 ep->X_add_number = 0;
67c0d1eb
RS
9203 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
9204 BFD_RELOC_MIPS_GOT16, mips_gp_register);
269137b2 9205 load_delay_nop ();
4d7206a2
RS
9206 relax_start (ep->X_add_symbol);
9207 relax_switch ();
67c0d1eb 9208 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
17a2f251 9209 BFD_RELOC_LO16);
4d7206a2 9210 relax_end ();
ed6fb7bd 9211
f5040a92
AO
9212 if (ex.X_add_number != 0)
9213 {
9214 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
9215 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9216 ex.X_op = O_constant;
67c0d1eb 9217 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j",
17a2f251 9218 reg, reg, BFD_RELOC_LO16);
f5040a92 9219 }
252b5132
RH
9220 }
9221 }
0a44bf69 9222 else if (mips_big_got)
252b5132
RH
9223 {
9224 expressionS ex;
252b5132
RH
9225
9226 /* This is the large GOT case. If this is a reference to an
9227 external symbol, we want
9228 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
9229 addu $reg,$reg,$gp
9230 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
f5040a92
AO
9231
9232 Otherwise, for a reference to a local symbol in old ABI, we want
252b5132
RH
9233 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9234 nop
9235 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
684022ea 9236 If there is a constant, it must be added in after.
f5040a92
AO
9237
9238 In the NewABI, for local symbols, with or without offsets, we want:
438c16b8
TS
9239 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
9240 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
f5040a92 9241 */
438c16b8
TS
9242 if (HAVE_NEWABI)
9243 {
4d7206a2 9244 ex.X_add_number = ep->X_add_number;
f5040a92 9245 ep->X_add_number = 0;
4d7206a2 9246 relax_start (ep->X_add_symbol);
df58fc94 9247 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16);
67c0d1eb
RS
9248 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9249 reg, reg, mips_gp_register);
9250 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)",
9251 reg, BFD_RELOC_MIPS_GOT_LO16, reg);
f5040a92
AO
9252 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
9253 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9254 else if (ex.X_add_number)
9255 {
9256 ex.X_op = O_constant;
67c0d1eb
RS
9257 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
9258 BFD_RELOC_LO16);
f5040a92
AO
9259 }
9260
9261 ep->X_add_number = ex.X_add_number;
4d7206a2 9262 relax_switch ();
67c0d1eb 9263 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
17a2f251 9264 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
67c0d1eb
RS
9265 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
9266 BFD_RELOC_MIPS_GOT_OFST);
4d7206a2 9267 relax_end ();
438c16b8 9268 }
252b5132 9269 else
438c16b8 9270 {
f5040a92
AO
9271 ex.X_add_number = ep->X_add_number;
9272 ep->X_add_number = 0;
4d7206a2 9273 relax_start (ep->X_add_symbol);
df58fc94 9274 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16);
67c0d1eb
RS
9275 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9276 reg, reg, mips_gp_register);
9277 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)",
9278 reg, BFD_RELOC_MIPS_GOT_LO16, reg);
4d7206a2
RS
9279 relax_switch ();
9280 if (reg_needs_delay (mips_gp_register))
438c16b8
TS
9281 {
9282 /* We need a nop before loading from $gp. This special
9283 check is required because the lui which starts the main
9284 instruction stream does not refer to $gp, and so will not
9285 insert the nop which may be required. */
67c0d1eb 9286 macro_build (NULL, "nop", "");
438c16b8 9287 }
67c0d1eb 9288 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
17a2f251 9289 BFD_RELOC_MIPS_GOT16, mips_gp_register);
269137b2 9290 load_delay_nop ();
67c0d1eb 9291 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
17a2f251 9292 BFD_RELOC_LO16);
4d7206a2 9293 relax_end ();
438c16b8 9294
f5040a92
AO
9295 if (ex.X_add_number != 0)
9296 {
9297 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
9298 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9299 ex.X_op = O_constant;
67c0d1eb
RS
9300 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
9301 BFD_RELOC_LO16);
f5040a92 9302 }
252b5132
RH
9303 }
9304 }
252b5132
RH
9305 else
9306 abort ();
8fc2e39e 9307
741fe287 9308 if (!mips_opts.at && *used_at == 1)
1661c76c 9309 as_bad (_("macro used $at after \".set noat\""));
252b5132
RH
9310}
9311
ea1fb5dc
RS
9312/* Move the contents of register SOURCE into register DEST. */
9313
9314static void
67c0d1eb 9315move_register (int dest, int source)
ea1fb5dc 9316{
df58fc94
RS
9317 /* Prefer to use a 16-bit microMIPS instruction unless the previous
9318 instruction specifically requires a 32-bit one. */
9319 if (mips_opts.micromips
833794fc 9320 && !mips_opts.insn32
df58fc94 9321 && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
7951ca42 9322 macro_build (NULL, "move", "mp,mj", dest, source);
df58fc94 9323 else
bad1aba3 9324 macro_build (NULL, GPR_SIZE == 32 ? "addu" : "daddu", "d,v,t",
df58fc94 9325 dest, source, 0);
ea1fb5dc
RS
9326}
9327
4d7206a2 9328/* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
f6a22291
MR
9329 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
9330 The two alternatives are:
4d7206a2
RS
9331
9332 Global symbol Local sybmol
9333 ------------- ------------
9334 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
9335 ... ...
9336 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
9337
9338 load_got_offset emits the first instruction and add_got_offset
f6a22291
MR
9339 emits the second for a 16-bit offset or add_got_offset_hilo emits
9340 a sequence to add a 32-bit offset using a scratch register. */
4d7206a2
RS
9341
9342static void
67c0d1eb 9343load_got_offset (int dest, expressionS *local)
4d7206a2
RS
9344{
9345 expressionS global;
9346
9347 global = *local;
9348 global.X_add_number = 0;
9349
9350 relax_start (local->X_add_symbol);
67c0d1eb
RS
9351 macro_build (&global, ADDRESS_LOAD_INSN, "t,o(b)", dest,
9352 BFD_RELOC_MIPS_GOT16, mips_gp_register);
4d7206a2 9353 relax_switch ();
67c0d1eb
RS
9354 macro_build (local, ADDRESS_LOAD_INSN, "t,o(b)", dest,
9355 BFD_RELOC_MIPS_GOT16, mips_gp_register);
4d7206a2
RS
9356 relax_end ();
9357}
9358
9359static void
67c0d1eb 9360add_got_offset (int dest, expressionS *local)
4d7206a2
RS
9361{
9362 expressionS global;
9363
9364 global.X_op = O_constant;
9365 global.X_op_symbol = NULL;
9366 global.X_add_symbol = NULL;
9367 global.X_add_number = local->X_add_number;
9368
9369 relax_start (local->X_add_symbol);
67c0d1eb 9370 macro_build (&global, ADDRESS_ADDI_INSN, "t,r,j",
4d7206a2
RS
9371 dest, dest, BFD_RELOC_LO16);
9372 relax_switch ();
67c0d1eb 9373 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", dest, dest, BFD_RELOC_LO16);
4d7206a2
RS
9374 relax_end ();
9375}
9376
f6a22291
MR
9377static void
9378add_got_offset_hilo (int dest, expressionS *local, int tmp)
9379{
9380 expressionS global;
9381 int hold_mips_optimize;
9382
9383 global.X_op = O_constant;
9384 global.X_op_symbol = NULL;
9385 global.X_add_symbol = NULL;
9386 global.X_add_number = local->X_add_number;
9387
9388 relax_start (local->X_add_symbol);
9389 load_register (tmp, &global, HAVE_64BIT_ADDRESSES);
9390 relax_switch ();
9391 /* Set mips_optimize around the lui instruction to avoid
9392 inserting an unnecessary nop after the lw. */
9393 hold_mips_optimize = mips_optimize;
9394 mips_optimize = 2;
9395 macro_build_lui (&global, tmp);
9396 mips_optimize = hold_mips_optimize;
9397 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", tmp, tmp, BFD_RELOC_LO16);
9398 relax_end ();
9399
9400 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dest, dest, tmp);
9401}
9402
df58fc94
RS
9403/* Emit a sequence of instructions to emulate a branch likely operation.
9404 BR is an ordinary branch corresponding to one to be emulated. BRNEG
9405 is its complementing branch with the original condition negated.
9406 CALL is set if the original branch specified the link operation.
9407 EP, FMT, SREG and TREG specify the usual macro_build() parameters.
9408
9409 Code like this is produced in the noreorder mode:
9410
9411 BRNEG <args>, 1f
9412 nop
9413 b <sym>
9414 delay slot (executed only if branch taken)
9415 1:
9416
9417 or, if CALL is set:
9418
9419 BRNEG <args>, 1f
9420 nop
9421 bal <sym>
9422 delay slot (executed only if branch taken)
9423 1:
9424
9425 In the reorder mode the delay slot would be filled with a nop anyway,
9426 so code produced is simply:
9427
9428 BR <args>, <sym>
9429 nop
9430
9431 This function is used when producing code for the microMIPS ASE that
9432 does not implement branch likely instructions in hardware. */
9433
9434static void
9435macro_build_branch_likely (const char *br, const char *brneg,
9436 int call, expressionS *ep, const char *fmt,
9437 unsigned int sreg, unsigned int treg)
9438{
9439 int noreorder = mips_opts.noreorder;
9440 expressionS expr1;
9441
9442 gas_assert (mips_opts.micromips);
9443 start_noreorder ();
9444 if (noreorder)
9445 {
9446 micromips_label_expr (&expr1);
9447 macro_build (&expr1, brneg, fmt, sreg, treg);
9448 macro_build (NULL, "nop", "");
9449 macro_build (ep, call ? "bal" : "b", "p");
9450
9451 /* Set to true so that append_insn adds a label. */
9452 emit_branch_likely_macro = TRUE;
9453 }
9454 else
9455 {
9456 macro_build (ep, br, fmt, sreg, treg);
9457 macro_build (NULL, "nop", "");
9458 }
9459 end_noreorder ();
9460}
9461
9462/* Emit a coprocessor branch-likely macro specified by TYPE, using CC as
9463 the condition code tested. EP specifies the branch target. */
9464
9465static void
9466macro_build_branch_ccl (int type, expressionS *ep, unsigned int cc)
9467{
9468 const int call = 0;
9469 const char *brneg;
9470 const char *br;
9471
9472 switch (type)
9473 {
9474 case M_BC1FL:
9475 br = "bc1f";
9476 brneg = "bc1t";
9477 break;
9478 case M_BC1TL:
9479 br = "bc1t";
9480 brneg = "bc1f";
9481 break;
9482 case M_BC2FL:
9483 br = "bc2f";
9484 brneg = "bc2t";
9485 break;
9486 case M_BC2TL:
9487 br = "bc2t";
9488 brneg = "bc2f";
9489 break;
9490 default:
9491 abort ();
9492 }
9493 macro_build_branch_likely (br, brneg, call, ep, "N,p", cc, ZERO);
9494}
9495
9496/* Emit a two-argument branch macro specified by TYPE, using SREG as
9497 the register tested. EP specifies the branch target. */
9498
9499static void
9500macro_build_branch_rs (int type, expressionS *ep, unsigned int sreg)
9501{
9502 const char *brneg = NULL;
9503 const char *br;
9504 int call = 0;
9505
9506 switch (type)
9507 {
9508 case M_BGEZ:
9509 br = "bgez";
9510 break;
9511 case M_BGEZL:
9512 br = mips_opts.micromips ? "bgez" : "bgezl";
9513 brneg = "bltz";
9514 break;
9515 case M_BGEZALL:
9516 gas_assert (mips_opts.micromips);
833794fc 9517 br = mips_opts.insn32 ? "bgezal" : "bgezals";
df58fc94
RS
9518 brneg = "bltz";
9519 call = 1;
9520 break;
9521 case M_BGTZ:
9522 br = "bgtz";
9523 break;
9524 case M_BGTZL:
9525 br = mips_opts.micromips ? "bgtz" : "bgtzl";
9526 brneg = "blez";
9527 break;
9528 case M_BLEZ:
9529 br = "blez";
9530 break;
9531 case M_BLEZL:
9532 br = mips_opts.micromips ? "blez" : "blezl";
9533 brneg = "bgtz";
9534 break;
9535 case M_BLTZ:
9536 br = "bltz";
9537 break;
9538 case M_BLTZL:
9539 br = mips_opts.micromips ? "bltz" : "bltzl";
9540 brneg = "bgez";
9541 break;
9542 case M_BLTZALL:
9543 gas_assert (mips_opts.micromips);
833794fc 9544 br = mips_opts.insn32 ? "bltzal" : "bltzals";
df58fc94
RS
9545 brneg = "bgez";
9546 call = 1;
9547 break;
9548 default:
9549 abort ();
9550 }
9551 if (mips_opts.micromips && brneg)
9552 macro_build_branch_likely (br, brneg, call, ep, "s,p", sreg, ZERO);
9553 else
9554 macro_build (ep, br, "s,p", sreg);
9555}
9556
9557/* Emit a three-argument branch macro specified by TYPE, using SREG and
9558 TREG as the registers tested. EP specifies the branch target. */
9559
9560static void
9561macro_build_branch_rsrt (int type, expressionS *ep,
9562 unsigned int sreg, unsigned int treg)
9563{
9564 const char *brneg = NULL;
9565 const int call = 0;
9566 const char *br;
9567
9568 switch (type)
9569 {
9570 case M_BEQ:
9571 case M_BEQ_I:
9572 br = "beq";
9573 break;
9574 case M_BEQL:
9575 case M_BEQL_I:
9576 br = mips_opts.micromips ? "beq" : "beql";
9577 brneg = "bne";
9578 break;
9579 case M_BNE:
9580 case M_BNE_I:
9581 br = "bne";
9582 break;
9583 case M_BNEL:
9584 case M_BNEL_I:
9585 br = mips_opts.micromips ? "bne" : "bnel";
9586 brneg = "beq";
9587 break;
9588 default:
9589 abort ();
9590 }
9591 if (mips_opts.micromips && brneg)
9592 macro_build_branch_likely (br, brneg, call, ep, "s,t,p", sreg, treg);
9593 else
9594 macro_build (ep, br, "s,t,p", sreg, treg);
9595}
9596
f2ae14a1
RS
9597/* Return the high part that should be loaded in order to make the low
9598 part of VALUE accessible using an offset of OFFBITS bits. */
9599
9600static offsetT
9601offset_high_part (offsetT value, unsigned int offbits)
9602{
9603 offsetT bias;
9604 addressT low_mask;
9605
9606 if (offbits == 0)
9607 return value;
9608 bias = 1 << (offbits - 1);
9609 low_mask = bias * 2 - 1;
9610 return (value + bias) & ~low_mask;
9611}
9612
9613/* Return true if the value stored in offset_expr and offset_reloc
9614 fits into a signed offset of OFFBITS bits. RANGE is the maximum
9615 amount that the caller wants to add without inducing overflow
9616 and ALIGN is the known alignment of the value in bytes. */
9617
9618static bfd_boolean
9619small_offset_p (unsigned int range, unsigned int align, unsigned int offbits)
9620{
9621 if (offbits == 16)
9622 {
9623 /* Accept any relocation operator if overflow isn't a concern. */
9624 if (range < align && *offset_reloc != BFD_RELOC_UNUSED)
9625 return TRUE;
9626
9627 /* These relocations are guaranteed not to overflow in correct links. */
9628 if (*offset_reloc == BFD_RELOC_MIPS_LITERAL
9629 || gprel16_reloc_p (*offset_reloc))
9630 return TRUE;
9631 }
9632 if (offset_expr.X_op == O_constant
9633 && offset_high_part (offset_expr.X_add_number, offbits) == 0
9634 && offset_high_part (offset_expr.X_add_number + range, offbits) == 0)
9635 return TRUE;
9636 return FALSE;
9637}
9638
252b5132
RH
9639/*
9640 * Build macros
9641 * This routine implements the seemingly endless macro or synthesized
9642 * instructions and addressing modes in the mips assembly language. Many
9643 * of these macros are simple and are similar to each other. These could
67c1ffbe 9644 * probably be handled by some kind of table or grammar approach instead of
252b5132
RH
9645 * this verbose method. Others are not simple macros but are more like
9646 * optimizing code generation.
9647 * One interesting optimization is when several store macros appear
67c1ffbe 9648 * consecutively that would load AT with the upper half of the same address.
252b5132
RH
9649 * The ensuing load upper instructions are ommited. This implies some kind
9650 * of global optimization. We currently only optimize within a single macro.
9651 * For many of the load and store macros if the address is specified as a
9652 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
9653 * first load register 'at' with zero and use it as the base register. The
9654 * mips assembler simply uses register $zero. Just one tiny optimization
9655 * we're missing.
9656 */
9657static void
833794fc 9658macro (struct mips_cl_insn *ip, char *str)
252b5132 9659{
c0ebe874
RS
9660 const struct mips_operand_array *operands;
9661 unsigned int breg, i;
741fe287 9662 unsigned int tempreg;
252b5132 9663 int mask;
43841e91 9664 int used_at = 0;
df58fc94 9665 expressionS label_expr;
252b5132 9666 expressionS expr1;
df58fc94 9667 expressionS *ep;
252b5132
RH
9668 const char *s;
9669 const char *s2;
9670 const char *fmt;
9671 int likely = 0;
252b5132 9672 int coproc = 0;
7f3c4072 9673 int offbits = 16;
1abe91b1 9674 int call = 0;
df58fc94
RS
9675 int jals = 0;
9676 int dbl = 0;
9677 int imm = 0;
9678 int ust = 0;
9679 int lp = 0;
f2ae14a1 9680 bfd_boolean large_offset;
252b5132 9681 int off;
252b5132 9682 int hold_mips_optimize;
f2ae14a1 9683 unsigned int align;
c0ebe874 9684 unsigned int op[MAX_OPERANDS];
252b5132 9685
9c2799c2 9686 gas_assert (! mips_opts.mips16);
252b5132 9687
c0ebe874
RS
9688 operands = insn_operands (ip);
9689 for (i = 0; i < MAX_OPERANDS; i++)
9690 if (operands->operand[i])
9691 op[i] = insn_extract_operand (ip, operands->operand[i]);
9692 else
9693 op[i] = -1;
9694
252b5132
RH
9695 mask = ip->insn_mo->mask;
9696
df58fc94
RS
9697 label_expr.X_op = O_constant;
9698 label_expr.X_op_symbol = NULL;
9699 label_expr.X_add_symbol = NULL;
9700 label_expr.X_add_number = 0;
9701
252b5132
RH
9702 expr1.X_op = O_constant;
9703 expr1.X_op_symbol = NULL;
9704 expr1.X_add_symbol = NULL;
9705 expr1.X_add_number = 1;
f2ae14a1 9706 align = 1;
252b5132
RH
9707
9708 switch (mask)
9709 {
9710 case M_DABS:
9711 dbl = 1;
9712 case M_ABS:
df58fc94
RS
9713 /* bgez $a0,1f
9714 move v0,$a0
9715 sub v0,$zero,$a0
9716 1:
9717 */
252b5132 9718
7d10b47d 9719 start_noreorder ();
252b5132 9720
df58fc94
RS
9721 if (mips_opts.micromips)
9722 micromips_label_expr (&label_expr);
9723 else
9724 label_expr.X_add_number = 8;
c0ebe874
RS
9725 macro_build (&label_expr, "bgez", "s,p", op[1]);
9726 if (op[0] == op[1])
a605d2b3 9727 macro_build (NULL, "nop", "");
252b5132 9728 else
c0ebe874
RS
9729 move_register (op[0], op[1]);
9730 macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", op[0], 0, op[1]);
df58fc94
RS
9731 if (mips_opts.micromips)
9732 micromips_add_label ();
252b5132 9733
7d10b47d 9734 end_noreorder ();
8fc2e39e 9735 break;
252b5132
RH
9736
9737 case M_ADD_I:
9738 s = "addi";
9739 s2 = "add";
9740 goto do_addi;
9741 case M_ADDU_I:
9742 s = "addiu";
9743 s2 = "addu";
9744 goto do_addi;
9745 case M_DADD_I:
9746 dbl = 1;
9747 s = "daddi";
9748 s2 = "dadd";
df58fc94
RS
9749 if (!mips_opts.micromips)
9750 goto do_addi;
b0e6f033 9751 if (imm_expr.X_add_number >= -0x200
df58fc94
RS
9752 && imm_expr.X_add_number < 0x200)
9753 {
b0e6f033
RS
9754 macro_build (NULL, s, "t,r,.", op[0], op[1],
9755 (int) imm_expr.X_add_number);
df58fc94
RS
9756 break;
9757 }
9758 goto do_addi_i;
252b5132
RH
9759 case M_DADDU_I:
9760 dbl = 1;
9761 s = "daddiu";
9762 s2 = "daddu";
9763 do_addi:
b0e6f033 9764 if (imm_expr.X_add_number >= -0x8000
252b5132
RH
9765 && imm_expr.X_add_number < 0x8000)
9766 {
c0ebe874 9767 macro_build (&imm_expr, s, "t,r,j", op[0], op[1], BFD_RELOC_LO16);
8fc2e39e 9768 break;
252b5132 9769 }
df58fc94 9770 do_addi_i:
8fc2e39e 9771 used_at = 1;
67c0d1eb 9772 load_register (AT, &imm_expr, dbl);
c0ebe874 9773 macro_build (NULL, s2, "d,v,t", op[0], op[1], AT);
252b5132
RH
9774 break;
9775
9776 case M_AND_I:
9777 s = "andi";
9778 s2 = "and";
9779 goto do_bit;
9780 case M_OR_I:
9781 s = "ori";
9782 s2 = "or";
9783 goto do_bit;
9784 case M_NOR_I:
9785 s = "";
9786 s2 = "nor";
9787 goto do_bit;
9788 case M_XOR_I:
9789 s = "xori";
9790 s2 = "xor";
9791 do_bit:
b0e6f033 9792 if (imm_expr.X_add_number >= 0
252b5132
RH
9793 && imm_expr.X_add_number < 0x10000)
9794 {
9795 if (mask != M_NOR_I)
c0ebe874 9796 macro_build (&imm_expr, s, "t,r,i", op[0], op[1], BFD_RELOC_LO16);
252b5132
RH
9797 else
9798 {
67c0d1eb 9799 macro_build (&imm_expr, "ori", "t,r,i",
c0ebe874
RS
9800 op[0], op[1], BFD_RELOC_LO16);
9801 macro_build (NULL, "nor", "d,v,t", op[0], op[0], 0);
252b5132 9802 }
8fc2e39e 9803 break;
252b5132
RH
9804 }
9805
8fc2e39e 9806 used_at = 1;
bad1aba3 9807 load_register (AT, &imm_expr, GPR_SIZE == 64);
c0ebe874 9808 macro_build (NULL, s2, "d,v,t", op[0], op[1], AT);
252b5132
RH
9809 break;
9810
8b082fb1
TS
9811 case M_BALIGN:
9812 switch (imm_expr.X_add_number)
9813 {
9814 case 0:
9815 macro_build (NULL, "nop", "");
9816 break;
9817 case 2:
c0ebe874 9818 macro_build (NULL, "packrl.ph", "d,s,t", op[0], op[0], op[1]);
8b082fb1 9819 break;
03f66e8a
MR
9820 case 1:
9821 case 3:
c0ebe874 9822 macro_build (NULL, "balign", "t,s,2", op[0], op[1],
90ecf173 9823 (int) imm_expr.X_add_number);
8b082fb1 9824 break;
03f66e8a
MR
9825 default:
9826 as_bad (_("BALIGN immediate not 0, 1, 2 or 3 (%lu)"),
9827 (unsigned long) imm_expr.X_add_number);
9828 break;
8b082fb1
TS
9829 }
9830 break;
9831
df58fc94
RS
9832 case M_BC1FL:
9833 case M_BC1TL:
9834 case M_BC2FL:
9835 case M_BC2TL:
9836 gas_assert (mips_opts.micromips);
9837 macro_build_branch_ccl (mask, &offset_expr,
9838 EXTRACT_OPERAND (1, BCC, *ip));
9839 break;
9840
252b5132 9841 case M_BEQ_I:
252b5132 9842 case M_BEQL_I:
252b5132 9843 case M_BNE_I:
252b5132 9844 case M_BNEL_I:
b0e6f033 9845 if (imm_expr.X_add_number == 0)
c0ebe874 9846 op[1] = 0;
df58fc94 9847 else
252b5132 9848 {
c0ebe874 9849 op[1] = AT;
df58fc94 9850 used_at = 1;
bad1aba3 9851 load_register (op[1], &imm_expr, GPR_SIZE == 64);
252b5132 9852 }
df58fc94
RS
9853 /* Fall through. */
9854 case M_BEQL:
9855 case M_BNEL:
c0ebe874 9856 macro_build_branch_rsrt (mask, &offset_expr, op[0], op[1]);
252b5132
RH
9857 break;
9858
9859 case M_BGEL:
9860 likely = 1;
9861 case M_BGE:
c0ebe874
RS
9862 if (op[1] == 0)
9863 macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, op[0]);
9864 else if (op[0] == 0)
9865 macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, op[1]);
df58fc94 9866 else
252b5132 9867 {
df58fc94 9868 used_at = 1;
c0ebe874 9869 macro_build (NULL, "slt", "d,v,t", AT, op[0], op[1]);
df58fc94
RS
9870 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
9871 &offset_expr, AT, ZERO);
252b5132 9872 }
df58fc94
RS
9873 break;
9874
9875 case M_BGEZL:
9876 case M_BGEZALL:
9877 case M_BGTZL:
9878 case M_BLEZL:
9879 case M_BLTZL:
9880 case M_BLTZALL:
c0ebe874 9881 macro_build_branch_rs (mask, &offset_expr, op[0]);
252b5132
RH
9882 break;
9883
9884 case M_BGTL_I:
9885 likely = 1;
9886 case M_BGT_I:
90ecf173 9887 /* Check for > max integer. */
b0e6f033 9888 if (imm_expr.X_add_number >= GPR_SMAX)
252b5132
RH
9889 {
9890 do_false:
90ecf173 9891 /* Result is always false. */
252b5132 9892 if (! likely)
a605d2b3 9893 macro_build (NULL, "nop", "");
252b5132 9894 else
df58fc94 9895 macro_build_branch_rsrt (M_BNEL, &offset_expr, ZERO, ZERO);
8fc2e39e 9896 break;
252b5132 9897 }
f9419b05 9898 ++imm_expr.X_add_number;
252b5132
RH
9899 /* FALLTHROUGH */
9900 case M_BGE_I:
9901 case M_BGEL_I:
9902 if (mask == M_BGEL_I)
9903 likely = 1;
b0e6f033 9904 if (imm_expr.X_add_number == 0)
252b5132 9905 {
df58fc94 9906 macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ,
c0ebe874 9907 &offset_expr, op[0]);
8fc2e39e 9908 break;
252b5132 9909 }
b0e6f033 9910 if (imm_expr.X_add_number == 1)
252b5132 9911 {
df58fc94 9912 macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ,
c0ebe874 9913 &offset_expr, op[0]);
8fc2e39e 9914 break;
252b5132 9915 }
b0e6f033 9916 if (imm_expr.X_add_number <= GPR_SMIN)
252b5132
RH
9917 {
9918 do_true:
9919 /* result is always true */
1661c76c 9920 as_warn (_("branch %s is always true"), ip->insn_mo->name);
67c0d1eb 9921 macro_build (&offset_expr, "b", "p");
8fc2e39e 9922 break;
252b5132 9923 }
8fc2e39e 9924 used_at = 1;
c0ebe874 9925 set_at (op[0], 0);
df58fc94
RS
9926 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
9927 &offset_expr, AT, ZERO);
252b5132
RH
9928 break;
9929
9930 case M_BGEUL:
9931 likely = 1;
9932 case M_BGEU:
c0ebe874 9933 if (op[1] == 0)
252b5132 9934 goto do_true;
c0ebe874 9935 else if (op[0] == 0)
df58fc94 9936 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
c0ebe874 9937 &offset_expr, ZERO, op[1]);
df58fc94 9938 else
252b5132 9939 {
df58fc94 9940 used_at = 1;
c0ebe874 9941 macro_build (NULL, "sltu", "d,v,t", AT, op[0], op[1]);
df58fc94
RS
9942 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
9943 &offset_expr, AT, ZERO);
252b5132 9944 }
252b5132
RH
9945 break;
9946
9947 case M_BGTUL_I:
9948 likely = 1;
9949 case M_BGTU_I:
c0ebe874 9950 if (op[0] == 0
bad1aba3 9951 || (GPR_SIZE == 32
f01dc953 9952 && imm_expr.X_add_number == -1))
252b5132 9953 goto do_false;
f9419b05 9954 ++imm_expr.X_add_number;
252b5132
RH
9955 /* FALLTHROUGH */
9956 case M_BGEU_I:
9957 case M_BGEUL_I:
9958 if (mask == M_BGEUL_I)
9959 likely = 1;
b0e6f033 9960 if (imm_expr.X_add_number == 0)
252b5132 9961 goto do_true;
b0e6f033 9962 else if (imm_expr.X_add_number == 1)
df58fc94 9963 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
c0ebe874 9964 &offset_expr, op[0], ZERO);
df58fc94 9965 else
252b5132 9966 {
df58fc94 9967 used_at = 1;
c0ebe874 9968 set_at (op[0], 1);
df58fc94
RS
9969 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
9970 &offset_expr, AT, ZERO);
252b5132 9971 }
252b5132
RH
9972 break;
9973
9974 case M_BGTL:
9975 likely = 1;
9976 case M_BGT:
c0ebe874
RS
9977 if (op[1] == 0)
9978 macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, op[0]);
9979 else if (op[0] == 0)
9980 macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, op[1]);
df58fc94 9981 else
252b5132 9982 {
df58fc94 9983 used_at = 1;
c0ebe874 9984 macro_build (NULL, "slt", "d,v,t", AT, op[1], op[0]);
df58fc94
RS
9985 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
9986 &offset_expr, AT, ZERO);
252b5132 9987 }
252b5132
RH
9988 break;
9989
9990 case M_BGTUL:
9991 likely = 1;
9992 case M_BGTU:
c0ebe874 9993 if (op[1] == 0)
df58fc94 9994 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
c0ebe874
RS
9995 &offset_expr, op[0], ZERO);
9996 else if (op[0] == 0)
df58fc94
RS
9997 goto do_false;
9998 else
252b5132 9999 {
df58fc94 10000 used_at = 1;
c0ebe874 10001 macro_build (NULL, "sltu", "d,v,t", AT, op[1], op[0]);
df58fc94
RS
10002 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
10003 &offset_expr, AT, ZERO);
252b5132 10004 }
252b5132
RH
10005 break;
10006
10007 case M_BLEL:
10008 likely = 1;
10009 case M_BLE:
c0ebe874
RS
10010 if (op[1] == 0)
10011 macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, op[0]);
10012 else if (op[0] == 0)
10013 macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, op[1]);
df58fc94 10014 else
252b5132 10015 {
df58fc94 10016 used_at = 1;
c0ebe874 10017 macro_build (NULL, "slt", "d,v,t", AT, op[1], op[0]);
df58fc94
RS
10018 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
10019 &offset_expr, AT, ZERO);
252b5132 10020 }
252b5132
RH
10021 break;
10022
10023 case M_BLEL_I:
10024 likely = 1;
10025 case M_BLE_I:
b0e6f033 10026 if (imm_expr.X_add_number >= GPR_SMAX)
252b5132 10027 goto do_true;
f9419b05 10028 ++imm_expr.X_add_number;
252b5132
RH
10029 /* FALLTHROUGH */
10030 case M_BLT_I:
10031 case M_BLTL_I:
10032 if (mask == M_BLTL_I)
10033 likely = 1;
b0e6f033 10034 if (imm_expr.X_add_number == 0)
c0ebe874 10035 macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, op[0]);
b0e6f033 10036 else if (imm_expr.X_add_number == 1)
c0ebe874 10037 macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, op[0]);
df58fc94 10038 else
252b5132 10039 {
df58fc94 10040 used_at = 1;
c0ebe874 10041 set_at (op[0], 0);
df58fc94
RS
10042 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
10043 &offset_expr, AT, ZERO);
252b5132 10044 }
252b5132
RH
10045 break;
10046
10047 case M_BLEUL:
10048 likely = 1;
10049 case M_BLEU:
c0ebe874 10050 if (op[1] == 0)
df58fc94 10051 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
c0ebe874
RS
10052 &offset_expr, op[0], ZERO);
10053 else if (op[0] == 0)
df58fc94
RS
10054 goto do_true;
10055 else
252b5132 10056 {
df58fc94 10057 used_at = 1;
c0ebe874 10058 macro_build (NULL, "sltu", "d,v,t", AT, op[1], op[0]);
df58fc94
RS
10059 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
10060 &offset_expr, AT, ZERO);
252b5132 10061 }
252b5132
RH
10062 break;
10063
10064 case M_BLEUL_I:
10065 likely = 1;
10066 case M_BLEU_I:
c0ebe874 10067 if (op[0] == 0
bad1aba3 10068 || (GPR_SIZE == 32
f01dc953 10069 && imm_expr.X_add_number == -1))
252b5132 10070 goto do_true;
f9419b05 10071 ++imm_expr.X_add_number;
252b5132
RH
10072 /* FALLTHROUGH */
10073 case M_BLTU_I:
10074 case M_BLTUL_I:
10075 if (mask == M_BLTUL_I)
10076 likely = 1;
b0e6f033 10077 if (imm_expr.X_add_number == 0)
252b5132 10078 goto do_false;
b0e6f033 10079 else if (imm_expr.X_add_number == 1)
df58fc94 10080 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
c0ebe874 10081 &offset_expr, op[0], ZERO);
df58fc94 10082 else
252b5132 10083 {
df58fc94 10084 used_at = 1;
c0ebe874 10085 set_at (op[0], 1);
df58fc94
RS
10086 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
10087 &offset_expr, AT, ZERO);
252b5132 10088 }
252b5132
RH
10089 break;
10090
10091 case M_BLTL:
10092 likely = 1;
10093 case M_BLT:
c0ebe874
RS
10094 if (op[1] == 0)
10095 macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, op[0]);
10096 else if (op[0] == 0)
10097 macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, op[1]);
df58fc94 10098 else
252b5132 10099 {
df58fc94 10100 used_at = 1;
c0ebe874 10101 macro_build (NULL, "slt", "d,v,t", AT, op[0], op[1]);
df58fc94
RS
10102 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
10103 &offset_expr, AT, ZERO);
252b5132 10104 }
252b5132
RH
10105 break;
10106
10107 case M_BLTUL:
10108 likely = 1;
10109 case M_BLTU:
c0ebe874 10110 if (op[1] == 0)
252b5132 10111 goto do_false;
c0ebe874 10112 else if (op[0] == 0)
df58fc94 10113 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
c0ebe874 10114 &offset_expr, ZERO, op[1]);
df58fc94 10115 else
252b5132 10116 {
df58fc94 10117 used_at = 1;
c0ebe874 10118 macro_build (NULL, "sltu", "d,v,t", AT, op[0], op[1]);
df58fc94
RS
10119 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
10120 &offset_expr, AT, ZERO);
252b5132 10121 }
252b5132
RH
10122 break;
10123
10124 case M_DDIV_3:
10125 dbl = 1;
10126 case M_DIV_3:
10127 s = "mflo";
10128 goto do_div3;
10129 case M_DREM_3:
10130 dbl = 1;
10131 case M_REM_3:
10132 s = "mfhi";
10133 do_div3:
c0ebe874 10134 if (op[2] == 0)
252b5132 10135 {
1661c76c 10136 as_warn (_("divide by zero"));
252b5132 10137 if (mips_trap)
df58fc94 10138 macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7);
252b5132 10139 else
df58fc94 10140 macro_build (NULL, "break", BRK_FMT, 7);
8fc2e39e 10141 break;
252b5132
RH
10142 }
10143
7d10b47d 10144 start_noreorder ();
252b5132
RH
10145 if (mips_trap)
10146 {
c0ebe874
RS
10147 macro_build (NULL, "teq", TRAP_FMT, op[2], ZERO, 7);
10148 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", op[1], op[2]);
252b5132
RH
10149 }
10150 else
10151 {
df58fc94
RS
10152 if (mips_opts.micromips)
10153 micromips_label_expr (&label_expr);
10154 else
10155 label_expr.X_add_number = 8;
c0ebe874
RS
10156 macro_build (&label_expr, "bne", "s,t,p", op[2], ZERO);
10157 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", op[1], op[2]);
df58fc94
RS
10158 macro_build (NULL, "break", BRK_FMT, 7);
10159 if (mips_opts.micromips)
10160 micromips_add_label ();
252b5132
RH
10161 }
10162 expr1.X_add_number = -1;
8fc2e39e 10163 used_at = 1;
f6a22291 10164 load_register (AT, &expr1, dbl);
df58fc94
RS
10165 if (mips_opts.micromips)
10166 micromips_label_expr (&label_expr);
10167 else
10168 label_expr.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16);
c0ebe874 10169 macro_build (&label_expr, "bne", "s,t,p", op[2], AT);
252b5132
RH
10170 if (dbl)
10171 {
10172 expr1.X_add_number = 1;
f6a22291 10173 load_register (AT, &expr1, dbl);
df58fc94 10174 macro_build (NULL, "dsll32", SHFT_FMT, AT, AT, 31);
252b5132
RH
10175 }
10176 else
10177 {
10178 expr1.X_add_number = 0x80000000;
df58fc94 10179 macro_build (&expr1, "lui", LUI_FMT, AT, BFD_RELOC_HI16);
252b5132
RH
10180 }
10181 if (mips_trap)
10182 {
c0ebe874 10183 macro_build (NULL, "teq", TRAP_FMT, op[1], AT, 6);
252b5132
RH
10184 /* We want to close the noreorder block as soon as possible, so
10185 that later insns are available for delay slot filling. */
7d10b47d 10186 end_noreorder ();
252b5132
RH
10187 }
10188 else
10189 {
df58fc94
RS
10190 if (mips_opts.micromips)
10191 micromips_label_expr (&label_expr);
10192 else
10193 label_expr.X_add_number = 8;
c0ebe874 10194 macro_build (&label_expr, "bne", "s,t,p", op[1], AT);
a605d2b3 10195 macro_build (NULL, "nop", "");
252b5132
RH
10196
10197 /* We want to close the noreorder block as soon as possible, so
10198 that later insns are available for delay slot filling. */
7d10b47d 10199 end_noreorder ();
252b5132 10200
df58fc94 10201 macro_build (NULL, "break", BRK_FMT, 6);
252b5132 10202 }
df58fc94
RS
10203 if (mips_opts.micromips)
10204 micromips_add_label ();
c0ebe874 10205 macro_build (NULL, s, MFHL_FMT, op[0]);
252b5132
RH
10206 break;
10207
10208 case M_DIV_3I:
10209 s = "div";
10210 s2 = "mflo";
10211 goto do_divi;
10212 case M_DIVU_3I:
10213 s = "divu";
10214 s2 = "mflo";
10215 goto do_divi;
10216 case M_REM_3I:
10217 s = "div";
10218 s2 = "mfhi";
10219 goto do_divi;
10220 case M_REMU_3I:
10221 s = "divu";
10222 s2 = "mfhi";
10223 goto do_divi;
10224 case M_DDIV_3I:
10225 dbl = 1;
10226 s = "ddiv";
10227 s2 = "mflo";
10228 goto do_divi;
10229 case M_DDIVU_3I:
10230 dbl = 1;
10231 s = "ddivu";
10232 s2 = "mflo";
10233 goto do_divi;
10234 case M_DREM_3I:
10235 dbl = 1;
10236 s = "ddiv";
10237 s2 = "mfhi";
10238 goto do_divi;
10239 case M_DREMU_3I:
10240 dbl = 1;
10241 s = "ddivu";
10242 s2 = "mfhi";
10243 do_divi:
b0e6f033 10244 if (imm_expr.X_add_number == 0)
252b5132 10245 {
1661c76c 10246 as_warn (_("divide by zero"));
252b5132 10247 if (mips_trap)
df58fc94 10248 macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7);
252b5132 10249 else
df58fc94 10250 macro_build (NULL, "break", BRK_FMT, 7);
8fc2e39e 10251 break;
252b5132 10252 }
b0e6f033 10253 if (imm_expr.X_add_number == 1)
252b5132
RH
10254 {
10255 if (strcmp (s2, "mflo") == 0)
c0ebe874 10256 move_register (op[0], op[1]);
252b5132 10257 else
c0ebe874 10258 move_register (op[0], ZERO);
8fc2e39e 10259 break;
252b5132 10260 }
b0e6f033 10261 if (imm_expr.X_add_number == -1 && s[strlen (s) - 1] != 'u')
252b5132
RH
10262 {
10263 if (strcmp (s2, "mflo") == 0)
c0ebe874 10264 macro_build (NULL, dbl ? "dneg" : "neg", "d,w", op[0], op[1]);
252b5132 10265 else
c0ebe874 10266 move_register (op[0], ZERO);
8fc2e39e 10267 break;
252b5132
RH
10268 }
10269
8fc2e39e 10270 used_at = 1;
67c0d1eb 10271 load_register (AT, &imm_expr, dbl);
c0ebe874
RS
10272 macro_build (NULL, s, "z,s,t", op[1], AT);
10273 macro_build (NULL, s2, MFHL_FMT, op[0]);
252b5132
RH
10274 break;
10275
10276 case M_DIVU_3:
10277 s = "divu";
10278 s2 = "mflo";
10279 goto do_divu3;
10280 case M_REMU_3:
10281 s = "divu";
10282 s2 = "mfhi";
10283 goto do_divu3;
10284 case M_DDIVU_3:
10285 s = "ddivu";
10286 s2 = "mflo";
10287 goto do_divu3;
10288 case M_DREMU_3:
10289 s = "ddivu";
10290 s2 = "mfhi";
10291 do_divu3:
7d10b47d 10292 start_noreorder ();
252b5132
RH
10293 if (mips_trap)
10294 {
c0ebe874
RS
10295 macro_build (NULL, "teq", TRAP_FMT, op[2], ZERO, 7);
10296 macro_build (NULL, s, "z,s,t", op[1], op[2]);
252b5132
RH
10297 /* We want to close the noreorder block as soon as possible, so
10298 that later insns are available for delay slot filling. */
7d10b47d 10299 end_noreorder ();
252b5132
RH
10300 }
10301 else
10302 {
df58fc94
RS
10303 if (mips_opts.micromips)
10304 micromips_label_expr (&label_expr);
10305 else
10306 label_expr.X_add_number = 8;
c0ebe874
RS
10307 macro_build (&label_expr, "bne", "s,t,p", op[2], ZERO);
10308 macro_build (NULL, s, "z,s,t", op[1], op[2]);
252b5132
RH
10309
10310 /* We want to close the noreorder block as soon as possible, so
10311 that later insns are available for delay slot filling. */
7d10b47d 10312 end_noreorder ();
df58fc94
RS
10313 macro_build (NULL, "break", BRK_FMT, 7);
10314 if (mips_opts.micromips)
10315 micromips_add_label ();
252b5132 10316 }
c0ebe874 10317 macro_build (NULL, s2, MFHL_FMT, op[0]);
8fc2e39e 10318 break;
252b5132 10319
1abe91b1
MR
10320 case M_DLCA_AB:
10321 dbl = 1;
10322 case M_LCA_AB:
10323 call = 1;
10324 goto do_la;
252b5132
RH
10325 case M_DLA_AB:
10326 dbl = 1;
10327 case M_LA_AB:
1abe91b1 10328 do_la:
252b5132
RH
10329 /* Load the address of a symbol into a register. If breg is not
10330 zero, we then add a base register to it. */
10331
c0ebe874 10332 breg = op[2];
bad1aba3 10333 if (dbl && GPR_SIZE == 32)
3bec30a8
TS
10334 as_warn (_("dla used to load 32-bit register"));
10335
90ecf173 10336 if (!dbl && HAVE_64BIT_OBJECTS)
3bec30a8
TS
10337 as_warn (_("la used to load 64-bit address"));
10338
f2ae14a1 10339 if (small_offset_p (0, align, 16))
0c11417f 10340 {
c0ebe874 10341 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", op[0], breg,
f2ae14a1 10342 -1, offset_reloc[0], offset_reloc[1], offset_reloc[2]);
8fc2e39e 10343 break;
0c11417f
MR
10344 }
10345
c0ebe874 10346 if (mips_opts.at && (op[0] == breg))
afdbd6d0
CD
10347 {
10348 tempreg = AT;
10349 used_at = 1;
10350 }
10351 else
c0ebe874 10352 tempreg = op[0];
afdbd6d0 10353
252b5132
RH
10354 if (offset_expr.X_op != O_symbol
10355 && offset_expr.X_op != O_constant)
10356 {
1661c76c 10357 as_bad (_("expression too complex"));
252b5132
RH
10358 offset_expr.X_op = O_constant;
10359 }
10360
252b5132 10361 if (offset_expr.X_op == O_constant)
aed1a261 10362 load_register (tempreg, &offset_expr, HAVE_64BIT_ADDRESSES);
252b5132
RH
10363 else if (mips_pic == NO_PIC)
10364 {
d6bc6245 10365 /* If this is a reference to a GP relative symbol, we want
cdf6fd85 10366 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
252b5132
RH
10367 Otherwise we want
10368 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
10369 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
10370 If we have a constant, we need two instructions anyhow,
d6bc6245 10371 so we may as well always use the latter form.
76b3015f 10372
6caf9ef4
TS
10373 With 64bit address space and a usable $at we want
10374 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
10375 lui $at,<sym> (BFD_RELOC_HI16_S)
10376 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
10377 daddiu $at,<sym> (BFD_RELOC_LO16)
10378 dsll32 $tempreg,0
10379 daddu $tempreg,$tempreg,$at
10380
10381 If $at is already in use, we use a path which is suboptimal
10382 on superscalar processors.
10383 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
10384 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
10385 dsll $tempreg,16
10386 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
10387 dsll $tempreg,16
10388 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
10389
10390 For GP relative symbols in 64bit address space we can use
10391 the same sequence as in 32bit address space. */
aed1a261 10392 if (HAVE_64BIT_SYMBOLS)
252b5132 10393 {
6caf9ef4
TS
10394 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
10395 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
10396 {
10397 relax_start (offset_expr.X_add_symbol);
10398 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
10399 tempreg, mips_gp_register, BFD_RELOC_GPREL16);
10400 relax_switch ();
10401 }
d6bc6245 10402
741fe287 10403 if (used_at == 0 && mips_opts.at)
98d3f06f 10404 {
df58fc94 10405 macro_build (&offset_expr, "lui", LUI_FMT,
17a2f251 10406 tempreg, BFD_RELOC_MIPS_HIGHEST);
df58fc94 10407 macro_build (&offset_expr, "lui", LUI_FMT,
17a2f251 10408 AT, BFD_RELOC_HI16_S);
67c0d1eb 10409 macro_build (&offset_expr, "daddiu", "t,r,j",
17a2f251 10410 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
67c0d1eb 10411 macro_build (&offset_expr, "daddiu", "t,r,j",
17a2f251 10412 AT, AT, BFD_RELOC_LO16);
df58fc94 10413 macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0);
67c0d1eb 10414 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT);
98d3f06f
KH
10415 used_at = 1;
10416 }
10417 else
10418 {
df58fc94 10419 macro_build (&offset_expr, "lui", LUI_FMT,
17a2f251 10420 tempreg, BFD_RELOC_MIPS_HIGHEST);
67c0d1eb 10421 macro_build (&offset_expr, "daddiu", "t,r,j",
17a2f251 10422 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
df58fc94 10423 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
67c0d1eb 10424 macro_build (&offset_expr, "daddiu", "t,r,j",
17a2f251 10425 tempreg, tempreg, BFD_RELOC_HI16_S);
df58fc94 10426 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
67c0d1eb 10427 macro_build (&offset_expr, "daddiu", "t,r,j",
17a2f251 10428 tempreg, tempreg, BFD_RELOC_LO16);
98d3f06f 10429 }
6caf9ef4
TS
10430
10431 if (mips_relax.sequence)
10432 relax_end ();
98d3f06f
KH
10433 }
10434 else
10435 {
10436 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
6caf9ef4 10437 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
98d3f06f 10438 {
4d7206a2 10439 relax_start (offset_expr.X_add_symbol);
67c0d1eb
RS
10440 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
10441 tempreg, mips_gp_register, BFD_RELOC_GPREL16);
4d7206a2 10442 relax_switch ();
98d3f06f 10443 }
6943caf0 10444 if (!IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
1661c76c 10445 as_bad (_("offset too large"));
67c0d1eb
RS
10446 macro_build_lui (&offset_expr, tempreg);
10447 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
10448 tempreg, tempreg, BFD_RELOC_LO16);
4d7206a2
RS
10449 if (mips_relax.sequence)
10450 relax_end ();
98d3f06f 10451 }
252b5132 10452 }
0a44bf69 10453 else if (!mips_big_got && !HAVE_NEWABI)
252b5132 10454 {
9117d219
NC
10455 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
10456
252b5132
RH
10457 /* If this is a reference to an external symbol, and there
10458 is no constant, we want
10459 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
1abe91b1 10460 or for lca or if tempreg is PIC_CALL_REG
9117d219 10461 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
252b5132
RH
10462 For a local symbol, we want
10463 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10464 nop
10465 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
10466
10467 If we have a small constant, and this is a reference to
10468 an external symbol, we want
10469 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10470 nop
10471 addiu $tempreg,$tempreg,<constant>
10472 For a local symbol, we want the same instruction
10473 sequence, but we output a BFD_RELOC_LO16 reloc on the
10474 addiu instruction.
10475
10476 If we have a large constant, and this is a reference to
10477 an external symbol, we want
10478 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10479 lui $at,<hiconstant>
10480 addiu $at,$at,<loconstant>
10481 addu $tempreg,$tempreg,$at
10482 For a local symbol, we want the same instruction
10483 sequence, but we output a BFD_RELOC_LO16 reloc on the
ed6fb7bd 10484 addiu instruction.
ed6fb7bd
SC
10485 */
10486
4d7206a2 10487 if (offset_expr.X_add_number == 0)
252b5132 10488 {
0a44bf69
RS
10489 if (mips_pic == SVR4_PIC
10490 && breg == 0
10491 && (call || tempreg == PIC_CALL_REG))
4d7206a2
RS
10492 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16;
10493
10494 relax_start (offset_expr.X_add_symbol);
67c0d1eb
RS
10495 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
10496 lw_reloc_type, mips_gp_register);
4d7206a2 10497 if (breg != 0)
252b5132
RH
10498 {
10499 /* We're going to put in an addu instruction using
10500 tempreg, so we may as well insert the nop right
10501 now. */
269137b2 10502 load_delay_nop ();
252b5132 10503 }
4d7206a2 10504 relax_switch ();
67c0d1eb
RS
10505 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
10506 tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register);
269137b2 10507 load_delay_nop ();
67c0d1eb
RS
10508 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
10509 tempreg, tempreg, BFD_RELOC_LO16);
4d7206a2 10510 relax_end ();
252b5132
RH
10511 /* FIXME: If breg == 0, and the next instruction uses
10512 $tempreg, then if this variant case is used an extra
10513 nop will be generated. */
10514 }
4d7206a2
RS
10515 else if (offset_expr.X_add_number >= -0x8000
10516 && offset_expr.X_add_number < 0x8000)
252b5132 10517 {
67c0d1eb 10518 load_got_offset (tempreg, &offset_expr);
269137b2 10519 load_delay_nop ();
67c0d1eb 10520 add_got_offset (tempreg, &offset_expr);
252b5132
RH
10521 }
10522 else
10523 {
4d7206a2
RS
10524 expr1.X_add_number = offset_expr.X_add_number;
10525 offset_expr.X_add_number =
43c0598f 10526 SEXT_16BIT (offset_expr.X_add_number);
67c0d1eb 10527 load_got_offset (tempreg, &offset_expr);
f6a22291 10528 offset_expr.X_add_number = expr1.X_add_number;
252b5132
RH
10529 /* If we are going to add in a base register, and the
10530 target register and the base register are the same,
10531 then we are using AT as a temporary register. Since
10532 we want to load the constant into AT, we add our
10533 current AT (from the global offset table) and the
10534 register into the register now, and pretend we were
10535 not using a base register. */
c0ebe874 10536 if (breg == op[0])
252b5132 10537 {
269137b2 10538 load_delay_nop ();
67c0d1eb 10539 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
c0ebe874 10540 op[0], AT, breg);
252b5132 10541 breg = 0;
c0ebe874 10542 tempreg = op[0];
252b5132 10543 }
f6a22291 10544 add_got_offset_hilo (tempreg, &offset_expr, AT);
252b5132
RH
10545 used_at = 1;
10546 }
10547 }
0a44bf69 10548 else if (!mips_big_got && HAVE_NEWABI)
f5040a92 10549 {
67c0d1eb 10550 int add_breg_early = 0;
f5040a92
AO
10551
10552 /* If this is a reference to an external, and there is no
10553 constant, or local symbol (*), with or without a
10554 constant, we want
10555 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
1abe91b1 10556 or for lca or if tempreg is PIC_CALL_REG
f5040a92
AO
10557 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
10558
10559 If we have a small constant, and this is a reference to
10560 an external symbol, we want
10561 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
10562 addiu $tempreg,$tempreg,<constant>
10563
10564 If we have a large constant, and this is a reference to
10565 an external symbol, we want
10566 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
10567 lui $at,<hiconstant>
10568 addiu $at,$at,<loconstant>
10569 addu $tempreg,$tempreg,$at
10570
10571 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
10572 local symbols, even though it introduces an additional
10573 instruction. */
10574
f5040a92
AO
10575 if (offset_expr.X_add_number)
10576 {
4d7206a2 10577 expr1.X_add_number = offset_expr.X_add_number;
f5040a92
AO
10578 offset_expr.X_add_number = 0;
10579
4d7206a2 10580 relax_start (offset_expr.X_add_symbol);
67c0d1eb
RS
10581 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
10582 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
f5040a92
AO
10583
10584 if (expr1.X_add_number >= -0x8000
10585 && expr1.X_add_number < 0x8000)
10586 {
67c0d1eb
RS
10587 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
10588 tempreg, tempreg, BFD_RELOC_LO16);
f5040a92 10589 }
ecd13cd3 10590 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
f5040a92 10591 {
c0ebe874
RS
10592 unsigned int dreg;
10593
f5040a92
AO
10594 /* If we are going to add in a base register, and the
10595 target register and the base register are the same,
10596 then we are using AT as a temporary register. Since
10597 we want to load the constant into AT, we add our
10598 current AT (from the global offset table) and the
10599 register into the register now, and pretend we were
10600 not using a base register. */
c0ebe874 10601 if (breg != op[0])
f5040a92
AO
10602 dreg = tempreg;
10603 else
10604 {
9c2799c2 10605 gas_assert (tempreg == AT);
67c0d1eb 10606 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
c0ebe874
RS
10607 op[0], AT, breg);
10608 dreg = op[0];
67c0d1eb 10609 add_breg_early = 1;
f5040a92
AO
10610 }
10611
f6a22291 10612 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
67c0d1eb 10613 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
17a2f251 10614 dreg, dreg, AT);
f5040a92 10615
f5040a92
AO
10616 used_at = 1;
10617 }
10618 else
10619 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
10620
4d7206a2 10621 relax_switch ();
f5040a92
AO
10622 offset_expr.X_add_number = expr1.X_add_number;
10623
67c0d1eb
RS
10624 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
10625 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
10626 if (add_breg_early)
f5040a92 10627 {
67c0d1eb 10628 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
c0ebe874 10629 op[0], tempreg, breg);
f5040a92 10630 breg = 0;
c0ebe874 10631 tempreg = op[0];
f5040a92 10632 }
4d7206a2 10633 relax_end ();
f5040a92 10634 }
4d7206a2 10635 else if (breg == 0 && (call || tempreg == PIC_CALL_REG))
f5040a92 10636 {
4d7206a2 10637 relax_start (offset_expr.X_add_symbol);
67c0d1eb
RS
10638 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
10639 BFD_RELOC_MIPS_CALL16, mips_gp_register);
4d7206a2 10640 relax_switch ();
67c0d1eb
RS
10641 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
10642 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
4d7206a2 10643 relax_end ();
f5040a92 10644 }
4d7206a2 10645 else
f5040a92 10646 {
67c0d1eb
RS
10647 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
10648 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
f5040a92
AO
10649 }
10650 }
0a44bf69 10651 else if (mips_big_got && !HAVE_NEWABI)
252b5132 10652 {
67c0d1eb 10653 int gpdelay;
9117d219
NC
10654 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
10655 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
ed6fb7bd 10656 int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
252b5132
RH
10657
10658 /* This is the large GOT case. If this is a reference to an
10659 external symbol, and there is no constant, we want
10660 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10661 addu $tempreg,$tempreg,$gp
10662 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
1abe91b1 10663 or for lca or if tempreg is PIC_CALL_REG
9117d219
NC
10664 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
10665 addu $tempreg,$tempreg,$gp
10666 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
252b5132
RH
10667 For a local symbol, we want
10668 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10669 nop
10670 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
10671
10672 If we have a small constant, and this is a reference to
10673 an external symbol, we want
10674 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10675 addu $tempreg,$tempreg,$gp
10676 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10677 nop
10678 addiu $tempreg,$tempreg,<constant>
10679 For a local symbol, we want
10680 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10681 nop
10682 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
10683
10684 If we have a large constant, and this is a reference to
10685 an external symbol, we want
10686 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10687 addu $tempreg,$tempreg,$gp
10688 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10689 lui $at,<hiconstant>
10690 addiu $at,$at,<loconstant>
10691 addu $tempreg,$tempreg,$at
10692 For a local symbol, we want
10693 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10694 lui $at,<hiconstant>
10695 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
10696 addu $tempreg,$tempreg,$at
f5040a92 10697 */
438c16b8 10698
252b5132
RH
10699 expr1.X_add_number = offset_expr.X_add_number;
10700 offset_expr.X_add_number = 0;
4d7206a2 10701 relax_start (offset_expr.X_add_symbol);
67c0d1eb 10702 gpdelay = reg_needs_delay (mips_gp_register);
1abe91b1
MR
10703 if (expr1.X_add_number == 0 && breg == 0
10704 && (call || tempreg == PIC_CALL_REG))
9117d219
NC
10705 {
10706 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
10707 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
10708 }
df58fc94 10709 macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type);
67c0d1eb 10710 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
17a2f251 10711 tempreg, tempreg, mips_gp_register);
67c0d1eb 10712 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
17a2f251 10713 tempreg, lw_reloc_type, tempreg);
252b5132
RH
10714 if (expr1.X_add_number == 0)
10715 {
67c0d1eb 10716 if (breg != 0)
252b5132
RH
10717 {
10718 /* We're going to put in an addu instruction using
10719 tempreg, so we may as well insert the nop right
10720 now. */
269137b2 10721 load_delay_nop ();
252b5132 10722 }
252b5132
RH
10723 }
10724 else if (expr1.X_add_number >= -0x8000
10725 && expr1.X_add_number < 0x8000)
10726 {
269137b2 10727 load_delay_nop ();
67c0d1eb 10728 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
17a2f251 10729 tempreg, tempreg, BFD_RELOC_LO16);
252b5132
RH
10730 }
10731 else
10732 {
c0ebe874
RS
10733 unsigned int dreg;
10734
252b5132
RH
10735 /* If we are going to add in a base register, and the
10736 target register and the base register are the same,
10737 then we are using AT as a temporary register. Since
10738 we want to load the constant into AT, we add our
10739 current AT (from the global offset table) and the
10740 register into the register now, and pretend we were
10741 not using a base register. */
c0ebe874 10742 if (breg != op[0])
67c0d1eb 10743 dreg = tempreg;
252b5132
RH
10744 else
10745 {
9c2799c2 10746 gas_assert (tempreg == AT);
269137b2 10747 load_delay_nop ();
67c0d1eb 10748 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
c0ebe874
RS
10749 op[0], AT, breg);
10750 dreg = op[0];
252b5132
RH
10751 }
10752
f6a22291 10753 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
67c0d1eb 10754 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
252b5132 10755
252b5132
RH
10756 used_at = 1;
10757 }
43c0598f 10758 offset_expr.X_add_number = SEXT_16BIT (expr1.X_add_number);
4d7206a2 10759 relax_switch ();
252b5132 10760
67c0d1eb 10761 if (gpdelay)
252b5132
RH
10762 {
10763 /* This is needed because this instruction uses $gp, but
f5040a92 10764 the first instruction on the main stream does not. */
67c0d1eb 10765 macro_build (NULL, "nop", "");
252b5132 10766 }
ed6fb7bd 10767
67c0d1eb
RS
10768 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
10769 local_reloc_type, mips_gp_register);
f5040a92 10770 if (expr1.X_add_number >= -0x8000
252b5132
RH
10771 && expr1.X_add_number < 0x8000)
10772 {
269137b2 10773 load_delay_nop ();
67c0d1eb
RS
10774 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
10775 tempreg, tempreg, BFD_RELOC_LO16);
252b5132 10776 /* FIXME: If add_number is 0, and there was no base
f5040a92
AO
10777 register, the external symbol case ended with a load,
10778 so if the symbol turns out to not be external, and
10779 the next instruction uses tempreg, an unnecessary nop
10780 will be inserted. */
252b5132
RH
10781 }
10782 else
10783 {
c0ebe874 10784 if (breg == op[0])
252b5132
RH
10785 {
10786 /* We must add in the base register now, as in the
f5040a92 10787 external symbol case. */
9c2799c2 10788 gas_assert (tempreg == AT);
269137b2 10789 load_delay_nop ();
67c0d1eb 10790 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
c0ebe874
RS
10791 op[0], AT, breg);
10792 tempreg = op[0];
252b5132 10793 /* We set breg to 0 because we have arranged to add
f5040a92 10794 it in in both cases. */
252b5132
RH
10795 breg = 0;
10796 }
10797
67c0d1eb
RS
10798 macro_build_lui (&expr1, AT);
10799 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
17a2f251 10800 AT, AT, BFD_RELOC_LO16);
67c0d1eb 10801 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
17a2f251 10802 tempreg, tempreg, AT);
8fc2e39e 10803 used_at = 1;
252b5132 10804 }
4d7206a2 10805 relax_end ();
252b5132 10806 }
0a44bf69 10807 else if (mips_big_got && HAVE_NEWABI)
f5040a92 10808 {
f5040a92
AO
10809 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
10810 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
67c0d1eb 10811 int add_breg_early = 0;
f5040a92
AO
10812
10813 /* This is the large GOT case. If this is a reference to an
10814 external symbol, and there is no constant, we want
10815 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10816 add $tempreg,$tempreg,$gp
10817 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
1abe91b1 10818 or for lca or if tempreg is PIC_CALL_REG
f5040a92
AO
10819 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
10820 add $tempreg,$tempreg,$gp
10821 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
10822
10823 If we have a small constant, and this is a reference to
10824 an external symbol, we want
10825 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10826 add $tempreg,$tempreg,$gp
10827 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10828 addi $tempreg,$tempreg,<constant>
10829
10830 If we have a large constant, and this is a reference to
10831 an external symbol, we want
10832 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10833 addu $tempreg,$tempreg,$gp
10834 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10835 lui $at,<hiconstant>
10836 addi $at,$at,<loconstant>
10837 add $tempreg,$tempreg,$at
10838
10839 If we have NewABI, and we know it's a local symbol, we want
10840 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
10841 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
10842 otherwise we have to resort to GOT_HI16/GOT_LO16. */
10843
4d7206a2 10844 relax_start (offset_expr.X_add_symbol);
f5040a92 10845
4d7206a2 10846 expr1.X_add_number = offset_expr.X_add_number;
f5040a92
AO
10847 offset_expr.X_add_number = 0;
10848
1abe91b1
MR
10849 if (expr1.X_add_number == 0 && breg == 0
10850 && (call || tempreg == PIC_CALL_REG))
f5040a92
AO
10851 {
10852 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
10853 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
10854 }
df58fc94 10855 macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type);
67c0d1eb 10856 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
17a2f251 10857 tempreg, tempreg, mips_gp_register);
67c0d1eb
RS
10858 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
10859 tempreg, lw_reloc_type, tempreg);
f5040a92
AO
10860
10861 if (expr1.X_add_number == 0)
4d7206a2 10862 ;
f5040a92
AO
10863 else if (expr1.X_add_number >= -0x8000
10864 && expr1.X_add_number < 0x8000)
10865 {
67c0d1eb 10866 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
17a2f251 10867 tempreg, tempreg, BFD_RELOC_LO16);
f5040a92 10868 }
ecd13cd3 10869 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
f5040a92 10870 {
c0ebe874
RS
10871 unsigned int dreg;
10872
f5040a92
AO
10873 /* If we are going to add in a base register, and the
10874 target register and the base register are the same,
10875 then we are using AT as a temporary register. Since
10876 we want to load the constant into AT, we add our
10877 current AT (from the global offset table) and the
10878 register into the register now, and pretend we were
10879 not using a base register. */
c0ebe874 10880 if (breg != op[0])
f5040a92
AO
10881 dreg = tempreg;
10882 else
10883 {
9c2799c2 10884 gas_assert (tempreg == AT);
67c0d1eb 10885 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
c0ebe874
RS
10886 op[0], AT, breg);
10887 dreg = op[0];
67c0d1eb 10888 add_breg_early = 1;
f5040a92
AO
10889 }
10890
f6a22291 10891 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
67c0d1eb 10892 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
f5040a92 10893
f5040a92
AO
10894 used_at = 1;
10895 }
10896 else
10897 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
10898
4d7206a2 10899 relax_switch ();
f5040a92 10900 offset_expr.X_add_number = expr1.X_add_number;
67c0d1eb
RS
10901 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
10902 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
10903 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
10904 tempreg, BFD_RELOC_MIPS_GOT_OFST);
10905 if (add_breg_early)
f5040a92 10906 {
67c0d1eb 10907 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
c0ebe874 10908 op[0], tempreg, breg);
f5040a92 10909 breg = 0;
c0ebe874 10910 tempreg = op[0];
f5040a92 10911 }
4d7206a2 10912 relax_end ();
f5040a92 10913 }
252b5132
RH
10914 else
10915 abort ();
10916
10917 if (breg != 0)
c0ebe874 10918 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", op[0], tempreg, breg);
252b5132
RH
10919 break;
10920
52b6b6b9 10921 case M_MSGSND:
df58fc94 10922 gas_assert (!mips_opts.micromips);
c0ebe874 10923 macro_build (NULL, "c2", "C", (op[0] << 16) | 0x01);
c7af4273 10924 break;
52b6b6b9
JM
10925
10926 case M_MSGLD:
df58fc94 10927 gas_assert (!mips_opts.micromips);
c8276761 10928 macro_build (NULL, "c2", "C", 0x02);
c7af4273 10929 break;
52b6b6b9
JM
10930
10931 case M_MSGLD_T:
df58fc94 10932 gas_assert (!mips_opts.micromips);
c0ebe874 10933 macro_build (NULL, "c2", "C", (op[0] << 16) | 0x02);
c7af4273 10934 break;
52b6b6b9
JM
10935
10936 case M_MSGWAIT:
df58fc94 10937 gas_assert (!mips_opts.micromips);
52b6b6b9 10938 macro_build (NULL, "c2", "C", 3);
c7af4273 10939 break;
52b6b6b9
JM
10940
10941 case M_MSGWAIT_T:
df58fc94 10942 gas_assert (!mips_opts.micromips);
c0ebe874 10943 macro_build (NULL, "c2", "C", (op[0] << 16) | 0x03);
c7af4273 10944 break;
52b6b6b9 10945
252b5132
RH
10946 case M_J_A:
10947 /* The j instruction may not be used in PIC code, since it
10948 requires an absolute address. We convert it to a b
10949 instruction. */
10950 if (mips_pic == NO_PIC)
67c0d1eb 10951 macro_build (&offset_expr, "j", "a");
252b5132 10952 else
67c0d1eb 10953 macro_build (&offset_expr, "b", "p");
8fc2e39e 10954 break;
252b5132
RH
10955
10956 /* The jal instructions must be handled as macros because when
10957 generating PIC code they expand to multi-instruction
10958 sequences. Normally they are simple instructions. */
df58fc94 10959 case M_JALS_1:
c0ebe874
RS
10960 op[1] = op[0];
10961 op[0] = RA;
df58fc94
RS
10962 /* Fall through. */
10963 case M_JALS_2:
10964 gas_assert (mips_opts.micromips);
833794fc
MR
10965 if (mips_opts.insn32)
10966 {
1661c76c 10967 as_bad (_("opcode not supported in the `insn32' mode `%s'"), str);
833794fc
MR
10968 break;
10969 }
df58fc94
RS
10970 jals = 1;
10971 goto jal;
252b5132 10972 case M_JAL_1:
c0ebe874
RS
10973 op[1] = op[0];
10974 op[0] = RA;
252b5132
RH
10975 /* Fall through. */
10976 case M_JAL_2:
df58fc94 10977 jal:
3e722fb5 10978 if (mips_pic == NO_PIC)
df58fc94
RS
10979 {
10980 s = jals ? "jalrs" : "jalr";
e64af278 10981 if (mips_opts.micromips
833794fc 10982 && !mips_opts.insn32
c0ebe874 10983 && op[0] == RA
e64af278 10984 && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
c0ebe874 10985 macro_build (NULL, s, "mj", op[1]);
df58fc94 10986 else
c0ebe874 10987 macro_build (NULL, s, JALR_FMT, op[0], op[1]);
df58fc94 10988 }
0a44bf69 10989 else
252b5132 10990 {
df58fc94
RS
10991 int cprestore = (mips_pic == SVR4_PIC && !HAVE_NEWABI
10992 && mips_cprestore_offset >= 0);
10993
c0ebe874 10994 if (op[1] != PIC_CALL_REG)
252b5132 10995 as_warn (_("MIPS PIC call to register other than $25"));
bdaaa2e1 10996
833794fc
MR
10997 s = ((mips_opts.micromips
10998 && !mips_opts.insn32
10999 && (!mips_opts.noreorder || cprestore))
df58fc94 11000 ? "jalrs" : "jalr");
e64af278 11001 if (mips_opts.micromips
833794fc 11002 && !mips_opts.insn32
c0ebe874 11003 && op[0] == RA
e64af278 11004 && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
c0ebe874 11005 macro_build (NULL, s, "mj", op[1]);
df58fc94 11006 else
c0ebe874 11007 macro_build (NULL, s, JALR_FMT, op[0], op[1]);
0a44bf69 11008 if (mips_pic == SVR4_PIC && !HAVE_NEWABI)
252b5132 11009 {
6478892d 11010 if (mips_cprestore_offset < 0)
1661c76c 11011 as_warn (_("no .cprestore pseudo-op used in PIC code"));
6478892d
TS
11012 else
11013 {
90ecf173 11014 if (!mips_frame_reg_valid)
7a621144 11015 {
1661c76c 11016 as_warn (_("no .frame pseudo-op used in PIC code"));
7a621144
DJ
11017 /* Quiet this warning. */
11018 mips_frame_reg_valid = 1;
11019 }
90ecf173 11020 if (!mips_cprestore_valid)
7a621144 11021 {
1661c76c 11022 as_warn (_("no .cprestore pseudo-op used in PIC code"));
7a621144
DJ
11023 /* Quiet this warning. */
11024 mips_cprestore_valid = 1;
11025 }
d3fca0b5
MR
11026 if (mips_opts.noreorder)
11027 macro_build (NULL, "nop", "");
6478892d 11028 expr1.X_add_number = mips_cprestore_offset;
67c0d1eb 11029 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
f899b4b8 11030 mips_gp_register,
256ab948
TS
11031 mips_frame_reg,
11032 HAVE_64BIT_ADDRESSES);
6478892d 11033 }
252b5132
RH
11034 }
11035 }
252b5132 11036
8fc2e39e 11037 break;
252b5132 11038
df58fc94
RS
11039 case M_JALS_A:
11040 gas_assert (mips_opts.micromips);
833794fc
MR
11041 if (mips_opts.insn32)
11042 {
1661c76c 11043 as_bad (_("opcode not supported in the `insn32' mode `%s'"), str);
833794fc
MR
11044 break;
11045 }
df58fc94
RS
11046 jals = 1;
11047 /* Fall through. */
252b5132
RH
11048 case M_JAL_A:
11049 if (mips_pic == NO_PIC)
df58fc94 11050 macro_build (&offset_expr, jals ? "jals" : "jal", "a");
252b5132
RH
11051 else if (mips_pic == SVR4_PIC)
11052 {
11053 /* If this is a reference to an external symbol, and we are
11054 using a small GOT, we want
11055 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
11056 nop
f9419b05 11057 jalr $ra,$25
252b5132
RH
11058 nop
11059 lw $gp,cprestore($sp)
11060 The cprestore value is set using the .cprestore
11061 pseudo-op. If we are using a big GOT, we want
11062 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
11063 addu $25,$25,$gp
11064 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
11065 nop
f9419b05 11066 jalr $ra,$25
252b5132
RH
11067 nop
11068 lw $gp,cprestore($sp)
11069 If the symbol is not external, we want
11070 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11071 nop
11072 addiu $25,$25,<sym> (BFD_RELOC_LO16)
f9419b05 11073 jalr $ra,$25
252b5132 11074 nop
438c16b8 11075 lw $gp,cprestore($sp)
f5040a92
AO
11076
11077 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
11078 sequences above, minus nops, unless the symbol is local,
11079 which enables us to use GOT_PAGE/GOT_OFST (big got) or
11080 GOT_DISP. */
438c16b8 11081 if (HAVE_NEWABI)
252b5132 11082 {
90ecf173 11083 if (!mips_big_got)
f5040a92 11084 {
4d7206a2 11085 relax_start (offset_expr.X_add_symbol);
67c0d1eb
RS
11086 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
11087 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
f5040a92 11088 mips_gp_register);
4d7206a2 11089 relax_switch ();
67c0d1eb
RS
11090 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
11091 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_DISP,
4d7206a2
RS
11092 mips_gp_register);
11093 relax_end ();
f5040a92
AO
11094 }
11095 else
11096 {
4d7206a2 11097 relax_start (offset_expr.X_add_symbol);
df58fc94 11098 macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG,
67c0d1eb
RS
11099 BFD_RELOC_MIPS_CALL_HI16);
11100 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
11101 PIC_CALL_REG, mips_gp_register);
11102 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
11103 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
11104 PIC_CALL_REG);
4d7206a2 11105 relax_switch ();
67c0d1eb
RS
11106 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
11107 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_PAGE,
11108 mips_gp_register);
11109 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
11110 PIC_CALL_REG, PIC_CALL_REG,
17a2f251 11111 BFD_RELOC_MIPS_GOT_OFST);
4d7206a2 11112 relax_end ();
f5040a92 11113 }
684022ea 11114
df58fc94 11115 macro_build_jalr (&offset_expr, 0);
252b5132
RH
11116 }
11117 else
11118 {
4d7206a2 11119 relax_start (offset_expr.X_add_symbol);
90ecf173 11120 if (!mips_big_got)
438c16b8 11121 {
67c0d1eb
RS
11122 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
11123 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
17a2f251 11124 mips_gp_register);
269137b2 11125 load_delay_nop ();
4d7206a2 11126 relax_switch ();
438c16b8 11127 }
252b5132 11128 else
252b5132 11129 {
67c0d1eb
RS
11130 int gpdelay;
11131
11132 gpdelay = reg_needs_delay (mips_gp_register);
df58fc94 11133 macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG,
67c0d1eb
RS
11134 BFD_RELOC_MIPS_CALL_HI16);
11135 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
11136 PIC_CALL_REG, mips_gp_register);
11137 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
11138 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
11139 PIC_CALL_REG);
269137b2 11140 load_delay_nop ();
4d7206a2 11141 relax_switch ();
67c0d1eb
RS
11142 if (gpdelay)
11143 macro_build (NULL, "nop", "");
252b5132 11144 }
67c0d1eb
RS
11145 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
11146 PIC_CALL_REG, BFD_RELOC_MIPS_GOT16,
4d7206a2 11147 mips_gp_register);
269137b2 11148 load_delay_nop ();
67c0d1eb
RS
11149 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
11150 PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16);
4d7206a2 11151 relax_end ();
df58fc94 11152 macro_build_jalr (&offset_expr, mips_cprestore_offset >= 0);
438c16b8 11153
6478892d 11154 if (mips_cprestore_offset < 0)
1661c76c 11155 as_warn (_("no .cprestore pseudo-op used in PIC code"));
6478892d
TS
11156 else
11157 {
90ecf173 11158 if (!mips_frame_reg_valid)
7a621144 11159 {
1661c76c 11160 as_warn (_("no .frame pseudo-op used in PIC code"));
7a621144
DJ
11161 /* Quiet this warning. */
11162 mips_frame_reg_valid = 1;
11163 }
90ecf173 11164 if (!mips_cprestore_valid)
7a621144 11165 {
1661c76c 11166 as_warn (_("no .cprestore pseudo-op used in PIC code"));
7a621144
DJ
11167 /* Quiet this warning. */
11168 mips_cprestore_valid = 1;
11169 }
6478892d 11170 if (mips_opts.noreorder)
67c0d1eb 11171 macro_build (NULL, "nop", "");
6478892d 11172 expr1.X_add_number = mips_cprestore_offset;
67c0d1eb 11173 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
f899b4b8 11174 mips_gp_register,
256ab948
TS
11175 mips_frame_reg,
11176 HAVE_64BIT_ADDRESSES);
6478892d 11177 }
252b5132
RH
11178 }
11179 }
0a44bf69 11180 else if (mips_pic == VXWORKS_PIC)
1661c76c 11181 as_bad (_("non-PIC jump used in PIC library"));
252b5132
RH
11182 else
11183 abort ();
11184
8fc2e39e 11185 break;
252b5132 11186
7f3c4072 11187 case M_LBUE_AB:
7f3c4072
CM
11188 s = "lbue";
11189 fmt = "t,+j(b)";
11190 offbits = 9;
11191 goto ld_st;
11192 case M_LHUE_AB:
7f3c4072
CM
11193 s = "lhue";
11194 fmt = "t,+j(b)";
11195 offbits = 9;
11196 goto ld_st;
11197 case M_LBE_AB:
7f3c4072
CM
11198 s = "lbe";
11199 fmt = "t,+j(b)";
11200 offbits = 9;
11201 goto ld_st;
11202 case M_LHE_AB:
7f3c4072
CM
11203 s = "lhe";
11204 fmt = "t,+j(b)";
11205 offbits = 9;
11206 goto ld_st;
11207 case M_LLE_AB:
7f3c4072
CM
11208 s = "lle";
11209 fmt = "t,+j(b)";
11210 offbits = 9;
11211 goto ld_st;
11212 case M_LWE_AB:
7f3c4072
CM
11213 s = "lwe";
11214 fmt = "t,+j(b)";
11215 offbits = 9;
11216 goto ld_st;
11217 case M_LWLE_AB:
7f3c4072
CM
11218 s = "lwle";
11219 fmt = "t,+j(b)";
11220 offbits = 9;
11221 goto ld_st;
11222 case M_LWRE_AB:
7f3c4072
CM
11223 s = "lwre";
11224 fmt = "t,+j(b)";
11225 offbits = 9;
11226 goto ld_st;
11227 case M_SBE_AB:
7f3c4072
CM
11228 s = "sbe";
11229 fmt = "t,+j(b)";
11230 offbits = 9;
11231 goto ld_st;
11232 case M_SCE_AB:
7f3c4072
CM
11233 s = "sce";
11234 fmt = "t,+j(b)";
11235 offbits = 9;
11236 goto ld_st;
11237 case M_SHE_AB:
7f3c4072
CM
11238 s = "she";
11239 fmt = "t,+j(b)";
11240 offbits = 9;
11241 goto ld_st;
11242 case M_SWE_AB:
7f3c4072
CM
11243 s = "swe";
11244 fmt = "t,+j(b)";
11245 offbits = 9;
11246 goto ld_st;
11247 case M_SWLE_AB:
7f3c4072
CM
11248 s = "swle";
11249 fmt = "t,+j(b)";
11250 offbits = 9;
11251 goto ld_st;
11252 case M_SWRE_AB:
7f3c4072
CM
11253 s = "swre";
11254 fmt = "t,+j(b)";
11255 offbits = 9;
11256 goto ld_st;
dec0624d 11257 case M_ACLR_AB:
dec0624d 11258 s = "aclr";
dec0624d 11259 fmt = "\\,~(b)";
7f3c4072 11260 offbits = 12;
dec0624d
MR
11261 goto ld_st;
11262 case M_ASET_AB:
dec0624d 11263 s = "aset";
dec0624d 11264 fmt = "\\,~(b)";
7f3c4072 11265 offbits = 12;
dec0624d 11266 goto ld_st;
252b5132
RH
11267 case M_LB_AB:
11268 s = "lb";
df58fc94 11269 fmt = "t,o(b)";
252b5132
RH
11270 goto ld;
11271 case M_LBU_AB:
11272 s = "lbu";
df58fc94 11273 fmt = "t,o(b)";
252b5132
RH
11274 goto ld;
11275 case M_LH_AB:
11276 s = "lh";
df58fc94 11277 fmt = "t,o(b)";
252b5132
RH
11278 goto ld;
11279 case M_LHU_AB:
11280 s = "lhu";
df58fc94 11281 fmt = "t,o(b)";
252b5132
RH
11282 goto ld;
11283 case M_LW_AB:
11284 s = "lw";
df58fc94 11285 fmt = "t,o(b)";
252b5132
RH
11286 goto ld;
11287 case M_LWC0_AB:
df58fc94 11288 gas_assert (!mips_opts.micromips);
252b5132 11289 s = "lwc0";
df58fc94 11290 fmt = "E,o(b)";
bdaaa2e1 11291 /* Itbl support may require additional care here. */
252b5132 11292 coproc = 1;
df58fc94 11293 goto ld_st;
252b5132
RH
11294 case M_LWC1_AB:
11295 s = "lwc1";
df58fc94 11296 fmt = "T,o(b)";
bdaaa2e1 11297 /* Itbl support may require additional care here. */
252b5132 11298 coproc = 1;
df58fc94 11299 goto ld_st;
252b5132
RH
11300 case M_LWC2_AB:
11301 s = "lwc2";
df58fc94 11302 fmt = COP12_FMT;
7361da2c
AB
11303 offbits = (mips_opts.micromips ? 12
11304 : ISA_IS_R6 (mips_opts.isa) ? 11
11305 : 16);
bdaaa2e1 11306 /* Itbl support may require additional care here. */
252b5132 11307 coproc = 1;
df58fc94 11308 goto ld_st;
252b5132 11309 case M_LWC3_AB:
df58fc94 11310 gas_assert (!mips_opts.micromips);
252b5132 11311 s = "lwc3";
df58fc94 11312 fmt = "E,o(b)";
bdaaa2e1 11313 /* Itbl support may require additional care here. */
252b5132 11314 coproc = 1;
df58fc94 11315 goto ld_st;
252b5132
RH
11316 case M_LWL_AB:
11317 s = "lwl";
df58fc94 11318 fmt = MEM12_FMT;
7f3c4072 11319 offbits = (mips_opts.micromips ? 12 : 16);
df58fc94 11320 goto ld_st;
252b5132
RH
11321 case M_LWR_AB:
11322 s = "lwr";
df58fc94 11323 fmt = MEM12_FMT;
7f3c4072 11324 offbits = (mips_opts.micromips ? 12 : 16);
df58fc94 11325 goto ld_st;
252b5132 11326 case M_LDC1_AB:
252b5132 11327 s = "ldc1";
df58fc94 11328 fmt = "T,o(b)";
bdaaa2e1 11329 /* Itbl support may require additional care here. */
252b5132 11330 coproc = 1;
df58fc94 11331 goto ld_st;
252b5132
RH
11332 case M_LDC2_AB:
11333 s = "ldc2";
df58fc94 11334 fmt = COP12_FMT;
7361da2c
AB
11335 offbits = (mips_opts.micromips ? 12
11336 : ISA_IS_R6 (mips_opts.isa) ? 11
11337 : 16);
bdaaa2e1 11338 /* Itbl support may require additional care here. */
252b5132 11339 coproc = 1;
df58fc94 11340 goto ld_st;
c77c0862 11341 case M_LQC2_AB:
c77c0862 11342 s = "lqc2";
14daeee3 11343 fmt = "+7,o(b)";
c77c0862
RS
11344 /* Itbl support may require additional care here. */
11345 coproc = 1;
11346 goto ld_st;
252b5132
RH
11347 case M_LDC3_AB:
11348 s = "ldc3";
df58fc94 11349 fmt = "E,o(b)";
bdaaa2e1 11350 /* Itbl support may require additional care here. */
252b5132 11351 coproc = 1;
df58fc94 11352 goto ld_st;
252b5132
RH
11353 case M_LDL_AB:
11354 s = "ldl";
df58fc94 11355 fmt = MEM12_FMT;
7f3c4072 11356 offbits = (mips_opts.micromips ? 12 : 16);
df58fc94 11357 goto ld_st;
252b5132
RH
11358 case M_LDR_AB:
11359 s = "ldr";
df58fc94 11360 fmt = MEM12_FMT;
7f3c4072 11361 offbits = (mips_opts.micromips ? 12 : 16);
df58fc94 11362 goto ld_st;
252b5132
RH
11363 case M_LL_AB:
11364 s = "ll";
7361da2c
AB
11365 fmt = LL_SC_FMT;
11366 offbits = (mips_opts.micromips ? 12
11367 : ISA_IS_R6 (mips_opts.isa) ? 9
11368 : 16);
252b5132
RH
11369 goto ld;
11370 case M_LLD_AB:
11371 s = "lld";
7361da2c
AB
11372 fmt = LL_SC_FMT;
11373 offbits = (mips_opts.micromips ? 12
11374 : ISA_IS_R6 (mips_opts.isa) ? 9
11375 : 16);
252b5132
RH
11376 goto ld;
11377 case M_LWU_AB:
11378 s = "lwu";
df58fc94 11379 fmt = MEM12_FMT;
7f3c4072 11380 offbits = (mips_opts.micromips ? 12 : 16);
df58fc94
RS
11381 goto ld;
11382 case M_LWP_AB:
df58fc94
RS
11383 gas_assert (mips_opts.micromips);
11384 s = "lwp";
11385 fmt = "t,~(b)";
7f3c4072 11386 offbits = 12;
df58fc94
RS
11387 lp = 1;
11388 goto ld;
11389 case M_LDP_AB:
df58fc94
RS
11390 gas_assert (mips_opts.micromips);
11391 s = "ldp";
11392 fmt = "t,~(b)";
7f3c4072 11393 offbits = 12;
df58fc94
RS
11394 lp = 1;
11395 goto ld;
11396 case M_LWM_AB:
df58fc94
RS
11397 gas_assert (mips_opts.micromips);
11398 s = "lwm";
11399 fmt = "n,~(b)";
7f3c4072 11400 offbits = 12;
df58fc94
RS
11401 goto ld_st;
11402 case M_LDM_AB:
df58fc94
RS
11403 gas_assert (mips_opts.micromips);
11404 s = "ldm";
11405 fmt = "n,~(b)";
7f3c4072 11406 offbits = 12;
df58fc94
RS
11407 goto ld_st;
11408
252b5132 11409 ld:
f19ccbda 11410 /* We don't want to use $0 as tempreg. */
c0ebe874 11411 if (op[2] == op[0] + lp || op[0] + lp == ZERO)
df58fc94 11412 goto ld_st;
252b5132 11413 else
c0ebe874 11414 tempreg = op[0] + lp;
df58fc94
RS
11415 goto ld_noat;
11416
252b5132
RH
11417 case M_SB_AB:
11418 s = "sb";
df58fc94
RS
11419 fmt = "t,o(b)";
11420 goto ld_st;
252b5132
RH
11421 case M_SH_AB:
11422 s = "sh";
df58fc94
RS
11423 fmt = "t,o(b)";
11424 goto ld_st;
252b5132
RH
11425 case M_SW_AB:
11426 s = "sw";
df58fc94
RS
11427 fmt = "t,o(b)";
11428 goto ld_st;
252b5132 11429 case M_SWC0_AB:
df58fc94 11430 gas_assert (!mips_opts.micromips);
252b5132 11431 s = "swc0";
df58fc94 11432 fmt = "E,o(b)";
bdaaa2e1 11433 /* Itbl support may require additional care here. */
252b5132 11434 coproc = 1;
df58fc94 11435 goto ld_st;
252b5132
RH
11436 case M_SWC1_AB:
11437 s = "swc1";
df58fc94 11438 fmt = "T,o(b)";
bdaaa2e1 11439 /* Itbl support may require additional care here. */
252b5132 11440 coproc = 1;
df58fc94 11441 goto ld_st;
252b5132
RH
11442 case M_SWC2_AB:
11443 s = "swc2";
df58fc94 11444 fmt = COP12_FMT;
7361da2c
AB
11445 offbits = (mips_opts.micromips ? 12
11446 : ISA_IS_R6 (mips_opts.isa) ? 11
11447 : 16);
bdaaa2e1 11448 /* Itbl support may require additional care here. */
252b5132 11449 coproc = 1;
df58fc94 11450 goto ld_st;
252b5132 11451 case M_SWC3_AB:
df58fc94 11452 gas_assert (!mips_opts.micromips);
252b5132 11453 s = "swc3";
df58fc94 11454 fmt = "E,o(b)";
bdaaa2e1 11455 /* Itbl support may require additional care here. */
252b5132 11456 coproc = 1;
df58fc94 11457 goto ld_st;
252b5132
RH
11458 case M_SWL_AB:
11459 s = "swl";
df58fc94 11460 fmt = MEM12_FMT;
7f3c4072 11461 offbits = (mips_opts.micromips ? 12 : 16);
df58fc94 11462 goto ld_st;
252b5132
RH
11463 case M_SWR_AB:
11464 s = "swr";
df58fc94 11465 fmt = MEM12_FMT;
7f3c4072 11466 offbits = (mips_opts.micromips ? 12 : 16);
df58fc94 11467 goto ld_st;
252b5132
RH
11468 case M_SC_AB:
11469 s = "sc";
7361da2c
AB
11470 fmt = LL_SC_FMT;
11471 offbits = (mips_opts.micromips ? 12
11472 : ISA_IS_R6 (mips_opts.isa) ? 9
11473 : 16);
df58fc94 11474 goto ld_st;
252b5132
RH
11475 case M_SCD_AB:
11476 s = "scd";
7361da2c
AB
11477 fmt = LL_SC_FMT;
11478 offbits = (mips_opts.micromips ? 12
11479 : ISA_IS_R6 (mips_opts.isa) ? 9
11480 : 16);
df58fc94 11481 goto ld_st;
d43b4baf
TS
11482 case M_CACHE_AB:
11483 s = "cache";
7361da2c
AB
11484 fmt = (mips_opts.micromips ? "k,~(b)"
11485 : ISA_IS_R6 (mips_opts.isa) ? "k,+j(b)"
11486 : "k,o(b)");
11487 offbits = (mips_opts.micromips ? 12
11488 : ISA_IS_R6 (mips_opts.isa) ? 9
11489 : 16);
7f3c4072
CM
11490 goto ld_st;
11491 case M_CACHEE_AB:
7f3c4072
CM
11492 s = "cachee";
11493 fmt = "k,+j(b)";
11494 offbits = 9;
df58fc94 11495 goto ld_st;
3eebd5eb
MR
11496 case M_PREF_AB:
11497 s = "pref";
7361da2c
AB
11498 fmt = (mips_opts.micromips ? "k,~(b)"
11499 : ISA_IS_R6 (mips_opts.isa) ? "k,+j(b)"
11500 : "k,o(b)");
11501 offbits = (mips_opts.micromips ? 12
11502 : ISA_IS_R6 (mips_opts.isa) ? 9
11503 : 16);
7f3c4072
CM
11504 goto ld_st;
11505 case M_PREFE_AB:
7f3c4072
CM
11506 s = "prefe";
11507 fmt = "k,+j(b)";
11508 offbits = 9;
df58fc94 11509 goto ld_st;
252b5132 11510 case M_SDC1_AB:
252b5132 11511 s = "sdc1";
df58fc94 11512 fmt = "T,o(b)";
252b5132 11513 coproc = 1;
bdaaa2e1 11514 /* Itbl support may require additional care here. */
df58fc94 11515 goto ld_st;
252b5132
RH
11516 case M_SDC2_AB:
11517 s = "sdc2";
df58fc94 11518 fmt = COP12_FMT;
7361da2c
AB
11519 offbits = (mips_opts.micromips ? 12
11520 : ISA_IS_R6 (mips_opts.isa) ? 11
11521 : 16);
c77c0862
RS
11522 /* Itbl support may require additional care here. */
11523 coproc = 1;
11524 goto ld_st;
11525 case M_SQC2_AB:
c77c0862 11526 s = "sqc2";
14daeee3 11527 fmt = "+7,o(b)";
bdaaa2e1 11528 /* Itbl support may require additional care here. */
252b5132 11529 coproc = 1;
df58fc94 11530 goto ld_st;
252b5132 11531 case M_SDC3_AB:
df58fc94 11532 gas_assert (!mips_opts.micromips);
252b5132 11533 s = "sdc3";
df58fc94 11534 fmt = "E,o(b)";
bdaaa2e1 11535 /* Itbl support may require additional care here. */
252b5132 11536 coproc = 1;
df58fc94 11537 goto ld_st;
252b5132
RH
11538 case M_SDL_AB:
11539 s = "sdl";
df58fc94 11540 fmt = MEM12_FMT;
7f3c4072 11541 offbits = (mips_opts.micromips ? 12 : 16);
df58fc94 11542 goto ld_st;
252b5132
RH
11543 case M_SDR_AB:
11544 s = "sdr";
df58fc94 11545 fmt = MEM12_FMT;
7f3c4072 11546 offbits = (mips_opts.micromips ? 12 : 16);
df58fc94
RS
11547 goto ld_st;
11548 case M_SWP_AB:
df58fc94
RS
11549 gas_assert (mips_opts.micromips);
11550 s = "swp";
11551 fmt = "t,~(b)";
7f3c4072 11552 offbits = 12;
df58fc94
RS
11553 goto ld_st;
11554 case M_SDP_AB:
df58fc94
RS
11555 gas_assert (mips_opts.micromips);
11556 s = "sdp";
11557 fmt = "t,~(b)";
7f3c4072 11558 offbits = 12;
df58fc94
RS
11559 goto ld_st;
11560 case M_SWM_AB:
df58fc94
RS
11561 gas_assert (mips_opts.micromips);
11562 s = "swm";
11563 fmt = "n,~(b)";
7f3c4072 11564 offbits = 12;
df58fc94
RS
11565 goto ld_st;
11566 case M_SDM_AB:
df58fc94
RS
11567 gas_assert (mips_opts.micromips);
11568 s = "sdm";
11569 fmt = "n,~(b)";
7f3c4072 11570 offbits = 12;
df58fc94
RS
11571
11572 ld_st:
8fc2e39e 11573 tempreg = AT;
df58fc94 11574 ld_noat:
c0ebe874 11575 breg = op[2];
f2ae14a1
RS
11576 if (small_offset_p (0, align, 16))
11577 {
11578 /* The first case exists for M_LD_AB and M_SD_AB, which are
11579 macros for o32 but which should act like normal instructions
11580 otherwise. */
11581 if (offbits == 16)
c0ebe874 11582 macro_build (&offset_expr, s, fmt, op[0], -1, offset_reloc[0],
f2ae14a1
RS
11583 offset_reloc[1], offset_reloc[2], breg);
11584 else if (small_offset_p (0, align, offbits))
11585 {
11586 if (offbits == 0)
c0ebe874 11587 macro_build (NULL, s, fmt, op[0], breg);
f2ae14a1 11588 else
c0ebe874 11589 macro_build (NULL, s, fmt, op[0],
c8276761 11590 (int) offset_expr.X_add_number, breg);
f2ae14a1
RS
11591 }
11592 else
11593 {
11594 if (tempreg == AT)
11595 used_at = 1;
11596 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
11597 tempreg, breg, -1, offset_reloc[0],
11598 offset_reloc[1], offset_reloc[2]);
11599 if (offbits == 0)
c0ebe874 11600 macro_build (NULL, s, fmt, op[0], tempreg);
f2ae14a1 11601 else
c0ebe874 11602 macro_build (NULL, s, fmt, op[0], 0, tempreg);
f2ae14a1
RS
11603 }
11604 break;
11605 }
11606
11607 if (tempreg == AT)
11608 used_at = 1;
11609
252b5132
RH
11610 if (offset_expr.X_op != O_constant
11611 && offset_expr.X_op != O_symbol)
11612 {
1661c76c 11613 as_bad (_("expression too complex"));
252b5132
RH
11614 offset_expr.X_op = O_constant;
11615 }
11616
2051e8c4
MR
11617 if (HAVE_32BIT_ADDRESSES
11618 && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
55e08f71
NC
11619 {
11620 char value [32];
11621
11622 sprintf_vma (value, offset_expr.X_add_number);
1661c76c 11623 as_bad (_("number (0x%s) larger than 32 bits"), value);
55e08f71 11624 }
2051e8c4 11625
252b5132
RH
11626 /* A constant expression in PIC code can be handled just as it
11627 is in non PIC code. */
aed1a261
RS
11628 if (offset_expr.X_op == O_constant)
11629 {
f2ae14a1
RS
11630 expr1.X_add_number = offset_high_part (offset_expr.X_add_number,
11631 offbits == 0 ? 16 : offbits);
11632 offset_expr.X_add_number -= expr1.X_add_number;
df58fc94 11633
f2ae14a1
RS
11634 load_register (tempreg, &expr1, HAVE_64BIT_ADDRESSES);
11635 if (breg != 0)
11636 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11637 tempreg, tempreg, breg);
7f3c4072 11638 if (offbits == 0)
dd6a37e7 11639 {
f2ae14a1 11640 if (offset_expr.X_add_number != 0)
dd6a37e7 11641 macro_build (&offset_expr, ADDRESS_ADDI_INSN,
f2ae14a1 11642 "t,r,j", tempreg, tempreg, BFD_RELOC_LO16);
c0ebe874 11643 macro_build (NULL, s, fmt, op[0], tempreg);
dd6a37e7 11644 }
7f3c4072 11645 else if (offbits == 16)
c0ebe874 11646 macro_build (&offset_expr, s, fmt, op[0], BFD_RELOC_LO16, tempreg);
df58fc94 11647 else
c0ebe874 11648 macro_build (NULL, s, fmt, op[0],
c8276761 11649 (int) offset_expr.X_add_number, tempreg);
df58fc94 11650 }
7f3c4072 11651 else if (offbits != 16)
df58fc94 11652 {
7f3c4072
CM
11653 /* The offset field is too narrow to be used for a low-part
11654 relocation, so load the whole address into the auxillary
f2ae14a1
RS
11655 register. */
11656 load_address (tempreg, &offset_expr, &used_at);
11657 if (breg != 0)
11658 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11659 tempreg, tempreg, breg);
7f3c4072 11660 if (offbits == 0)
c0ebe874 11661 macro_build (NULL, s, fmt, op[0], tempreg);
dd6a37e7 11662 else
c0ebe874 11663 macro_build (NULL, s, fmt, op[0], 0, tempreg);
aed1a261
RS
11664 }
11665 else if (mips_pic == NO_PIC)
252b5132
RH
11666 {
11667 /* If this is a reference to a GP relative symbol, and there
11668 is no base register, we want
c0ebe874 11669 <op> op[0],<sym>($gp) (BFD_RELOC_GPREL16)
252b5132
RH
11670 Otherwise, if there is no base register, we want
11671 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
c0ebe874 11672 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
252b5132
RH
11673 If we have a constant, we need two instructions anyhow,
11674 so we always use the latter form.
11675
11676 If we have a base register, and this is a reference to a
11677 GP relative symbol, we want
11678 addu $tempreg,$breg,$gp
c0ebe874 11679 <op> op[0],<sym>($tempreg) (BFD_RELOC_GPREL16)
252b5132
RH
11680 Otherwise we want
11681 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
11682 addu $tempreg,$tempreg,$breg
c0ebe874 11683 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
d6bc6245 11684 With a constant we always use the latter case.
76b3015f 11685
d6bc6245
TS
11686 With 64bit address space and no base register and $at usable,
11687 we want
11688 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
11689 lui $at,<sym> (BFD_RELOC_HI16_S)
11690 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
11691 dsll32 $tempreg,0
11692 daddu $tempreg,$at
c0ebe874 11693 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
d6bc6245
TS
11694 If we have a base register, we want
11695 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
11696 lui $at,<sym> (BFD_RELOC_HI16_S)
11697 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
11698 daddu $at,$breg
11699 dsll32 $tempreg,0
11700 daddu $tempreg,$at
c0ebe874 11701 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
d6bc6245
TS
11702
11703 Without $at we can't generate the optimal path for superscalar
11704 processors here since this would require two temporary registers.
11705 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
11706 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
11707 dsll $tempreg,16
11708 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
11709 dsll $tempreg,16
c0ebe874 11710 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
d6bc6245
TS
11711 If we have a base register, we want
11712 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
11713 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
11714 dsll $tempreg,16
11715 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
11716 dsll $tempreg,16
11717 daddu $tempreg,$tempreg,$breg
c0ebe874 11718 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
6373ee54 11719
6caf9ef4 11720 For GP relative symbols in 64bit address space we can use
aed1a261
RS
11721 the same sequence as in 32bit address space. */
11722 if (HAVE_64BIT_SYMBOLS)
d6bc6245 11723 {
aed1a261 11724 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
6caf9ef4
TS
11725 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
11726 {
11727 relax_start (offset_expr.X_add_symbol);
11728 if (breg == 0)
11729 {
c0ebe874 11730 macro_build (&offset_expr, s, fmt, op[0],
6caf9ef4
TS
11731 BFD_RELOC_GPREL16, mips_gp_register);
11732 }
11733 else
11734 {
11735 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11736 tempreg, breg, mips_gp_register);
c0ebe874 11737 macro_build (&offset_expr, s, fmt, op[0],
6caf9ef4
TS
11738 BFD_RELOC_GPREL16, tempreg);
11739 }
11740 relax_switch ();
11741 }
d6bc6245 11742
741fe287 11743 if (used_at == 0 && mips_opts.at)
d6bc6245 11744 {
df58fc94 11745 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
67c0d1eb 11746 BFD_RELOC_MIPS_HIGHEST);
df58fc94 11747 macro_build (&offset_expr, "lui", LUI_FMT, AT,
67c0d1eb
RS
11748 BFD_RELOC_HI16_S);
11749 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
11750 tempreg, BFD_RELOC_MIPS_HIGHER);
d6bc6245 11751 if (breg != 0)
67c0d1eb 11752 macro_build (NULL, "daddu", "d,v,t", AT, AT, breg);
df58fc94 11753 macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0);
67c0d1eb 11754 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT);
c0ebe874 11755 macro_build (&offset_expr, s, fmt, op[0], BFD_RELOC_LO16,
67c0d1eb 11756 tempreg);
d6bc6245
TS
11757 used_at = 1;
11758 }
11759 else
11760 {
df58fc94 11761 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
67c0d1eb
RS
11762 BFD_RELOC_MIPS_HIGHEST);
11763 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
11764 tempreg, BFD_RELOC_MIPS_HIGHER);
df58fc94 11765 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
67c0d1eb
RS
11766 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
11767 tempreg, BFD_RELOC_HI16_S);
df58fc94 11768 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
d6bc6245 11769 if (breg != 0)
67c0d1eb 11770 macro_build (NULL, "daddu", "d,v,t",
17a2f251 11771 tempreg, tempreg, breg);
c0ebe874 11772 macro_build (&offset_expr, s, fmt, op[0],
17a2f251 11773 BFD_RELOC_LO16, tempreg);
d6bc6245 11774 }
6caf9ef4
TS
11775
11776 if (mips_relax.sequence)
11777 relax_end ();
8fc2e39e 11778 break;
d6bc6245 11779 }
256ab948 11780
252b5132
RH
11781 if (breg == 0)
11782 {
67c0d1eb 11783 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
6caf9ef4 11784 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
252b5132 11785 {
4d7206a2 11786 relax_start (offset_expr.X_add_symbol);
c0ebe874 11787 macro_build (&offset_expr, s, fmt, op[0], BFD_RELOC_GPREL16,
67c0d1eb 11788 mips_gp_register);
4d7206a2 11789 relax_switch ();
252b5132 11790 }
67c0d1eb 11791 macro_build_lui (&offset_expr, tempreg);
c0ebe874 11792 macro_build (&offset_expr, s, fmt, op[0],
17a2f251 11793 BFD_RELOC_LO16, tempreg);
4d7206a2
RS
11794 if (mips_relax.sequence)
11795 relax_end ();
252b5132
RH
11796 }
11797 else
11798 {
67c0d1eb 11799 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
6caf9ef4 11800 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
252b5132 11801 {
4d7206a2 11802 relax_start (offset_expr.X_add_symbol);
67c0d1eb 11803 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
17a2f251 11804 tempreg, breg, mips_gp_register);
c0ebe874 11805 macro_build (&offset_expr, s, fmt, op[0],
17a2f251 11806 BFD_RELOC_GPREL16, tempreg);
4d7206a2 11807 relax_switch ();
252b5132 11808 }
67c0d1eb
RS
11809 macro_build_lui (&offset_expr, tempreg);
11810 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
17a2f251 11811 tempreg, tempreg, breg);
c0ebe874 11812 macro_build (&offset_expr, s, fmt, op[0],
17a2f251 11813 BFD_RELOC_LO16, tempreg);
4d7206a2
RS
11814 if (mips_relax.sequence)
11815 relax_end ();
252b5132
RH
11816 }
11817 }
0a44bf69 11818 else if (!mips_big_got)
252b5132 11819 {
ed6fb7bd 11820 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
f9419b05 11821
252b5132
RH
11822 /* If this is a reference to an external symbol, we want
11823 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11824 nop
c0ebe874 11825 <op> op[0],0($tempreg)
252b5132
RH
11826 Otherwise we want
11827 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11828 nop
11829 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
c0ebe874 11830 <op> op[0],0($tempreg)
f5040a92
AO
11831
11832 For NewABI, we want
11833 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
c0ebe874 11834 <op> op[0],<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
f5040a92 11835
252b5132
RH
11836 If there is a base register, we add it to $tempreg before
11837 the <op>. If there is a constant, we stick it in the
11838 <op> instruction. We don't handle constants larger than
11839 16 bits, because we have no way to load the upper 16 bits
11840 (actually, we could handle them for the subset of cases
11841 in which we are not using $at). */
9c2799c2 11842 gas_assert (offset_expr.X_op == O_symbol);
f5040a92
AO
11843 if (HAVE_NEWABI)
11844 {
67c0d1eb
RS
11845 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
11846 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
f5040a92 11847 if (breg != 0)
67c0d1eb 11848 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
17a2f251 11849 tempreg, tempreg, breg);
c0ebe874 11850 macro_build (&offset_expr, s, fmt, op[0],
17a2f251 11851 BFD_RELOC_MIPS_GOT_OFST, tempreg);
f5040a92
AO
11852 break;
11853 }
252b5132
RH
11854 expr1.X_add_number = offset_expr.X_add_number;
11855 offset_expr.X_add_number = 0;
11856 if (expr1.X_add_number < -0x8000
11857 || expr1.X_add_number >= 0x8000)
11858 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
67c0d1eb
RS
11859 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
11860 lw_reloc_type, mips_gp_register);
269137b2 11861 load_delay_nop ();
4d7206a2
RS
11862 relax_start (offset_expr.X_add_symbol);
11863 relax_switch ();
67c0d1eb
RS
11864 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
11865 tempreg, BFD_RELOC_LO16);
4d7206a2 11866 relax_end ();
252b5132 11867 if (breg != 0)
67c0d1eb 11868 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
17a2f251 11869 tempreg, tempreg, breg);
c0ebe874 11870 macro_build (&expr1, s, fmt, op[0], BFD_RELOC_LO16, tempreg);
252b5132 11871 }
0a44bf69 11872 else if (mips_big_got && !HAVE_NEWABI)
252b5132 11873 {
67c0d1eb 11874 int gpdelay;
252b5132
RH
11875
11876 /* If this is a reference to an external symbol, we want
11877 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11878 addu $tempreg,$tempreg,$gp
11879 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
c0ebe874 11880 <op> op[0],0($tempreg)
252b5132
RH
11881 Otherwise we want
11882 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11883 nop
11884 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
c0ebe874 11885 <op> op[0],0($tempreg)
252b5132
RH
11886 If there is a base register, we add it to $tempreg before
11887 the <op>. If there is a constant, we stick it in the
11888 <op> instruction. We don't handle constants larger than
11889 16 bits, because we have no way to load the upper 16 bits
11890 (actually, we could handle them for the subset of cases
f5040a92 11891 in which we are not using $at). */
9c2799c2 11892 gas_assert (offset_expr.X_op == O_symbol);
252b5132
RH
11893 expr1.X_add_number = offset_expr.X_add_number;
11894 offset_expr.X_add_number = 0;
11895 if (expr1.X_add_number < -0x8000
11896 || expr1.X_add_number >= 0x8000)
11897 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
67c0d1eb 11898 gpdelay = reg_needs_delay (mips_gp_register);
4d7206a2 11899 relax_start (offset_expr.X_add_symbol);
df58fc94 11900 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
17a2f251 11901 BFD_RELOC_MIPS_GOT_HI16);
67c0d1eb
RS
11902 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
11903 mips_gp_register);
11904 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
11905 BFD_RELOC_MIPS_GOT_LO16, tempreg);
4d7206a2 11906 relax_switch ();
67c0d1eb
RS
11907 if (gpdelay)
11908 macro_build (NULL, "nop", "");
11909 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
11910 BFD_RELOC_MIPS_GOT16, mips_gp_register);
269137b2 11911 load_delay_nop ();
67c0d1eb
RS
11912 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
11913 tempreg, BFD_RELOC_LO16);
4d7206a2
RS
11914 relax_end ();
11915
252b5132 11916 if (breg != 0)
67c0d1eb 11917 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
17a2f251 11918 tempreg, tempreg, breg);
c0ebe874 11919 macro_build (&expr1, s, fmt, op[0], BFD_RELOC_LO16, tempreg);
252b5132 11920 }
0a44bf69 11921 else if (mips_big_got && HAVE_NEWABI)
f5040a92 11922 {
f5040a92
AO
11923 /* If this is a reference to an external symbol, we want
11924 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11925 add $tempreg,$tempreg,$gp
11926 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
c0ebe874 11927 <op> op[0],<ofst>($tempreg)
f5040a92
AO
11928 Otherwise, for local symbols, we want:
11929 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
c0ebe874 11930 <op> op[0],<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
9c2799c2 11931 gas_assert (offset_expr.X_op == O_symbol);
4d7206a2 11932 expr1.X_add_number = offset_expr.X_add_number;
f5040a92
AO
11933 offset_expr.X_add_number = 0;
11934 if (expr1.X_add_number < -0x8000
11935 || expr1.X_add_number >= 0x8000)
11936 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4d7206a2 11937 relax_start (offset_expr.X_add_symbol);
df58fc94 11938 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
17a2f251 11939 BFD_RELOC_MIPS_GOT_HI16);
67c0d1eb
RS
11940 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
11941 mips_gp_register);
11942 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
11943 BFD_RELOC_MIPS_GOT_LO16, tempreg);
f5040a92 11944 if (breg != 0)
67c0d1eb 11945 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
17a2f251 11946 tempreg, tempreg, breg);
c0ebe874 11947 macro_build (&expr1, s, fmt, op[0], BFD_RELOC_LO16, tempreg);
684022ea 11948
4d7206a2 11949 relax_switch ();
f5040a92 11950 offset_expr.X_add_number = expr1.X_add_number;
67c0d1eb
RS
11951 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
11952 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
f5040a92 11953 if (breg != 0)
67c0d1eb 11954 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
17a2f251 11955 tempreg, tempreg, breg);
c0ebe874 11956 macro_build (&offset_expr, s, fmt, op[0],
17a2f251 11957 BFD_RELOC_MIPS_GOT_OFST, tempreg);
4d7206a2 11958 relax_end ();
f5040a92 11959 }
252b5132
RH
11960 else
11961 abort ();
11962
252b5132
RH
11963 break;
11964
833794fc
MR
11965 case M_JRADDIUSP:
11966 gas_assert (mips_opts.micromips);
11967 gas_assert (mips_opts.insn32);
11968 start_noreorder ();
11969 macro_build (NULL, "jr", "s", RA);
c0ebe874 11970 expr1.X_add_number = op[0] << 2;
833794fc
MR
11971 macro_build (&expr1, "addiu", "t,r,j", SP, SP, BFD_RELOC_LO16);
11972 end_noreorder ();
11973 break;
11974
11975 case M_JRC:
11976 gas_assert (mips_opts.micromips);
11977 gas_assert (mips_opts.insn32);
c0ebe874 11978 macro_build (NULL, "jr", "s", op[0]);
833794fc
MR
11979 if (mips_opts.noreorder)
11980 macro_build (NULL, "nop", "");
11981 break;
11982
252b5132
RH
11983 case M_LI:
11984 case M_LI_S:
c0ebe874 11985 load_register (op[0], &imm_expr, 0);
8fc2e39e 11986 break;
252b5132
RH
11987
11988 case M_DLI:
c0ebe874 11989 load_register (op[0], &imm_expr, 1);
8fc2e39e 11990 break;
252b5132
RH
11991
11992 case M_LI_SS:
11993 if (imm_expr.X_op == O_constant)
11994 {
8fc2e39e 11995 used_at = 1;
67c0d1eb 11996 load_register (AT, &imm_expr, 0);
c0ebe874 11997 macro_build (NULL, "mtc1", "t,G", AT, op[0]);
252b5132
RH
11998 break;
11999 }
12000 else
12001 {
b0e6f033
RS
12002 gas_assert (imm_expr.X_op == O_absent
12003 && offset_expr.X_op == O_symbol
90ecf173
MR
12004 && strcmp (segment_name (S_GET_SEGMENT
12005 (offset_expr.X_add_symbol)),
12006 ".lit4") == 0
12007 && offset_expr.X_add_number == 0);
c0ebe874 12008 macro_build (&offset_expr, "lwc1", "T,o(b)", op[0],
17a2f251 12009 BFD_RELOC_MIPS_LITERAL, mips_gp_register);
8fc2e39e 12010 break;
252b5132
RH
12011 }
12012
12013 case M_LI_D:
ca4e0257
RS
12014 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
12015 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
12016 order 32 bits of the value and the low order 32 bits are either
12017 zero or in OFFSET_EXPR. */
b0e6f033 12018 if (imm_expr.X_op == O_constant)
252b5132 12019 {
bad1aba3 12020 if (GPR_SIZE == 64)
c0ebe874 12021 load_register (op[0], &imm_expr, 1);
252b5132
RH
12022 else
12023 {
12024 int hreg, lreg;
12025
12026 if (target_big_endian)
12027 {
c0ebe874
RS
12028 hreg = op[0];
12029 lreg = op[0] + 1;
252b5132
RH
12030 }
12031 else
12032 {
c0ebe874
RS
12033 hreg = op[0] + 1;
12034 lreg = op[0];
252b5132
RH
12035 }
12036
12037 if (hreg <= 31)
67c0d1eb 12038 load_register (hreg, &imm_expr, 0);
252b5132
RH
12039 if (lreg <= 31)
12040 {
12041 if (offset_expr.X_op == O_absent)
67c0d1eb 12042 move_register (lreg, 0);
252b5132
RH
12043 else
12044 {
9c2799c2 12045 gas_assert (offset_expr.X_op == O_constant);
67c0d1eb 12046 load_register (lreg, &offset_expr, 0);
252b5132
RH
12047 }
12048 }
12049 }
8fc2e39e 12050 break;
252b5132 12051 }
b0e6f033 12052 gas_assert (imm_expr.X_op == O_absent);
252b5132
RH
12053
12054 /* We know that sym is in the .rdata section. First we get the
12055 upper 16 bits of the address. */
12056 if (mips_pic == NO_PIC)
12057 {
67c0d1eb 12058 macro_build_lui (&offset_expr, AT);
8fc2e39e 12059 used_at = 1;
252b5132 12060 }
0a44bf69 12061 else
252b5132 12062 {
67c0d1eb
RS
12063 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
12064 BFD_RELOC_MIPS_GOT16, mips_gp_register);
8fc2e39e 12065 used_at = 1;
252b5132 12066 }
bdaaa2e1 12067
252b5132 12068 /* Now we load the register(s). */
bad1aba3 12069 if (GPR_SIZE == 64)
8fc2e39e
TS
12070 {
12071 used_at = 1;
c0ebe874
RS
12072 macro_build (&offset_expr, "ld", "t,o(b)", op[0],
12073 BFD_RELOC_LO16, AT);
8fc2e39e 12074 }
252b5132
RH
12075 else
12076 {
8fc2e39e 12077 used_at = 1;
c0ebe874
RS
12078 macro_build (&offset_expr, "lw", "t,o(b)", op[0],
12079 BFD_RELOC_LO16, AT);
12080 if (op[0] != RA)
252b5132
RH
12081 {
12082 /* FIXME: How in the world do we deal with the possible
12083 overflow here? */
12084 offset_expr.X_add_number += 4;
67c0d1eb 12085 macro_build (&offset_expr, "lw", "t,o(b)",
c0ebe874 12086 op[0] + 1, BFD_RELOC_LO16, AT);
252b5132
RH
12087 }
12088 }
252b5132
RH
12089 break;
12090
12091 case M_LI_DD:
ca4e0257
RS
12092 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
12093 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
12094 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
12095 the value and the low order 32 bits are either zero or in
12096 OFFSET_EXPR. */
b0e6f033 12097 if (imm_expr.X_op == O_constant)
252b5132 12098 {
8fc2e39e 12099 used_at = 1;
bad1aba3 12100 load_register (AT, &imm_expr, FPR_SIZE == 64);
351cdf24
MF
12101 if (FPR_SIZE == 64 && GPR_SIZE == 64)
12102 macro_build (NULL, "dmtc1", "t,S", AT, op[0]);
252b5132
RH
12103 else
12104 {
351cdf24
MF
12105 if (ISA_HAS_MXHC1 (mips_opts.isa))
12106 macro_build (NULL, "mthc1", "t,G", AT, op[0]);
12107 else if (FPR_SIZE != 32)
12108 as_bad (_("Unable to generate `%s' compliant code "
12109 "without mthc1"),
12110 (FPR_SIZE == 64) ? "fp64" : "fpxx");
12111 else
12112 macro_build (NULL, "mtc1", "t,G", AT, op[0] + 1);
252b5132 12113 if (offset_expr.X_op == O_absent)
c0ebe874 12114 macro_build (NULL, "mtc1", "t,G", 0, op[0]);
252b5132
RH
12115 else
12116 {
9c2799c2 12117 gas_assert (offset_expr.X_op == O_constant);
67c0d1eb 12118 load_register (AT, &offset_expr, 0);
c0ebe874 12119 macro_build (NULL, "mtc1", "t,G", AT, op[0]);
252b5132
RH
12120 }
12121 }
12122 break;
12123 }
12124
b0e6f033
RS
12125 gas_assert (imm_expr.X_op == O_absent
12126 && offset_expr.X_op == O_symbol
90ecf173 12127 && offset_expr.X_add_number == 0);
252b5132
RH
12128 s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol));
12129 if (strcmp (s, ".lit8") == 0)
f2ae14a1 12130 {
c0ebe874 12131 op[2] = mips_gp_register;
f2ae14a1
RS
12132 offset_reloc[0] = BFD_RELOC_MIPS_LITERAL;
12133 offset_reloc[1] = BFD_RELOC_UNUSED;
12134 offset_reloc[2] = BFD_RELOC_UNUSED;
252b5132
RH
12135 }
12136 else
12137 {
9c2799c2 12138 gas_assert (strcmp (s, RDATA_SECTION_NAME) == 0);
8fc2e39e 12139 used_at = 1;
0a44bf69 12140 if (mips_pic != NO_PIC)
67c0d1eb
RS
12141 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
12142 BFD_RELOC_MIPS_GOT16, mips_gp_register);
252b5132
RH
12143 else
12144 {
12145 /* FIXME: This won't work for a 64 bit address. */
67c0d1eb 12146 macro_build_lui (&offset_expr, AT);
252b5132 12147 }
bdaaa2e1 12148
c0ebe874 12149 op[2] = AT;
f2ae14a1
RS
12150 offset_reloc[0] = BFD_RELOC_LO16;
12151 offset_reloc[1] = BFD_RELOC_UNUSED;
12152 offset_reloc[2] = BFD_RELOC_UNUSED;
12153 }
12154 align = 8;
12155 /* Fall through */
c4a68bea 12156
252b5132
RH
12157 case M_L_DAB:
12158 /*
12159 * The MIPS assembler seems to check for X_add_number not
12160 * being double aligned and generating:
12161 * lui at,%hi(foo+1)
12162 * addu at,at,v1
12163 * addiu at,at,%lo(foo+1)
12164 * lwc1 f2,0(at)
12165 * lwc1 f3,4(at)
12166 * But, the resulting address is the same after relocation so why
12167 * generate the extra instruction?
12168 */
bdaaa2e1 12169 /* Itbl support may require additional care here. */
252b5132 12170 coproc = 1;
df58fc94 12171 fmt = "T,o(b)";
0aa27725 12172 if (CPU_HAS_LDC1_SDC1 (mips_opts.arch))
252b5132
RH
12173 {
12174 s = "ldc1";
df58fc94 12175 goto ld_st;
252b5132 12176 }
252b5132 12177 s = "lwc1";
252b5132
RH
12178 goto ldd_std;
12179
12180 case M_S_DAB:
df58fc94
RS
12181 gas_assert (!mips_opts.micromips);
12182 /* Itbl support may require additional care here. */
12183 coproc = 1;
12184 fmt = "T,o(b)";
0aa27725 12185 if (CPU_HAS_LDC1_SDC1 (mips_opts.arch))
252b5132
RH
12186 {
12187 s = "sdc1";
df58fc94 12188 goto ld_st;
252b5132 12189 }
252b5132 12190 s = "swc1";
252b5132
RH
12191 goto ldd_std;
12192
e407c74b
NC
12193 case M_LQ_AB:
12194 fmt = "t,o(b)";
12195 s = "lq";
12196 goto ld;
12197
12198 case M_SQ_AB:
12199 fmt = "t,o(b)";
12200 s = "sq";
12201 goto ld_st;
12202
252b5132 12203 case M_LD_AB:
df58fc94 12204 fmt = "t,o(b)";
bad1aba3 12205 if (GPR_SIZE == 64)
252b5132
RH
12206 {
12207 s = "ld";
12208 goto ld;
12209 }
252b5132 12210 s = "lw";
252b5132
RH
12211 goto ldd_std;
12212
12213 case M_SD_AB:
df58fc94 12214 fmt = "t,o(b)";
bad1aba3 12215 if (GPR_SIZE == 64)
252b5132
RH
12216 {
12217 s = "sd";
df58fc94 12218 goto ld_st;
252b5132 12219 }
252b5132 12220 s = "sw";
252b5132
RH
12221
12222 ldd_std:
f2ae14a1
RS
12223 /* Even on a big endian machine $fn comes before $fn+1. We have
12224 to adjust when loading from memory. We set coproc if we must
12225 load $fn+1 first. */
12226 /* Itbl support may require additional care here. */
12227 if (!target_big_endian)
12228 coproc = 0;
12229
c0ebe874 12230 breg = op[2];
f2ae14a1
RS
12231 if (small_offset_p (0, align, 16))
12232 {
12233 ep = &offset_expr;
12234 if (!small_offset_p (4, align, 16))
12235 {
12236 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", AT, breg,
12237 -1, offset_reloc[0], offset_reloc[1],
12238 offset_reloc[2]);
12239 expr1.X_add_number = 0;
12240 ep = &expr1;
12241 breg = AT;
12242 used_at = 1;
12243 offset_reloc[0] = BFD_RELOC_LO16;
12244 offset_reloc[1] = BFD_RELOC_UNUSED;
12245 offset_reloc[2] = BFD_RELOC_UNUSED;
12246 }
c0ebe874 12247 if (strcmp (s, "lw") == 0 && op[0] == breg)
f2ae14a1
RS
12248 {
12249 ep->X_add_number += 4;
c0ebe874 12250 macro_build (ep, s, fmt, op[0] + 1, -1, offset_reloc[0],
f2ae14a1
RS
12251 offset_reloc[1], offset_reloc[2], breg);
12252 ep->X_add_number -= 4;
c0ebe874 12253 macro_build (ep, s, fmt, op[0], -1, offset_reloc[0],
f2ae14a1
RS
12254 offset_reloc[1], offset_reloc[2], breg);
12255 }
12256 else
12257 {
c0ebe874 12258 macro_build (ep, s, fmt, coproc ? op[0] + 1 : op[0], -1,
f2ae14a1
RS
12259 offset_reloc[0], offset_reloc[1], offset_reloc[2],
12260 breg);
12261 ep->X_add_number += 4;
c0ebe874 12262 macro_build (ep, s, fmt, coproc ? op[0] : op[0] + 1, -1,
f2ae14a1
RS
12263 offset_reloc[0], offset_reloc[1], offset_reloc[2],
12264 breg);
12265 }
12266 break;
12267 }
12268
252b5132
RH
12269 if (offset_expr.X_op != O_symbol
12270 && offset_expr.X_op != O_constant)
12271 {
1661c76c 12272 as_bad (_("expression too complex"));
252b5132
RH
12273 offset_expr.X_op = O_constant;
12274 }
12275
2051e8c4
MR
12276 if (HAVE_32BIT_ADDRESSES
12277 && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
55e08f71
NC
12278 {
12279 char value [32];
12280
12281 sprintf_vma (value, offset_expr.X_add_number);
1661c76c 12282 as_bad (_("number (0x%s) larger than 32 bits"), value);
55e08f71 12283 }
2051e8c4 12284
90ecf173 12285 if (mips_pic == NO_PIC || offset_expr.X_op == O_constant)
252b5132
RH
12286 {
12287 /* If this is a reference to a GP relative symbol, we want
c0ebe874
RS
12288 <op> op[0],<sym>($gp) (BFD_RELOC_GPREL16)
12289 <op> op[0]+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
252b5132
RH
12290 If we have a base register, we use this
12291 addu $at,$breg,$gp
c0ebe874
RS
12292 <op> op[0],<sym>($at) (BFD_RELOC_GPREL16)
12293 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_GPREL16)
252b5132
RH
12294 If this is not a GP relative symbol, we want
12295 lui $at,<sym> (BFD_RELOC_HI16_S)
c0ebe874
RS
12296 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
12297 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
252b5132
RH
12298 If there is a base register, we add it to $at after the
12299 lui instruction. If there is a constant, we always use
12300 the last case. */
39a59cf8
MR
12301 if (offset_expr.X_op == O_symbol
12302 && (valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
6caf9ef4 12303 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
252b5132 12304 {
4d7206a2 12305 relax_start (offset_expr.X_add_symbol);
252b5132
RH
12306 if (breg == 0)
12307 {
c9914766 12308 tempreg = mips_gp_register;
252b5132
RH
12309 }
12310 else
12311 {
67c0d1eb 12312 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
17a2f251 12313 AT, breg, mips_gp_register);
252b5132 12314 tempreg = AT;
252b5132
RH
12315 used_at = 1;
12316 }
12317
beae10d5 12318 /* Itbl support may require additional care here. */
c0ebe874 12319 macro_build (&offset_expr, s, fmt, coproc ? op[0] + 1 : op[0],
17a2f251 12320 BFD_RELOC_GPREL16, tempreg);
252b5132
RH
12321 offset_expr.X_add_number += 4;
12322
12323 /* Set mips_optimize to 2 to avoid inserting an
12324 undesired nop. */
12325 hold_mips_optimize = mips_optimize;
12326 mips_optimize = 2;
beae10d5 12327 /* Itbl support may require additional care here. */
c0ebe874 12328 macro_build (&offset_expr, s, fmt, coproc ? op[0] : op[0] + 1,
17a2f251 12329 BFD_RELOC_GPREL16, tempreg);
252b5132
RH
12330 mips_optimize = hold_mips_optimize;
12331
4d7206a2 12332 relax_switch ();
252b5132 12333
0970e49e 12334 offset_expr.X_add_number -= 4;
252b5132 12335 }
8fc2e39e 12336 used_at = 1;
f2ae14a1
RS
12337 if (offset_high_part (offset_expr.X_add_number, 16)
12338 != offset_high_part (offset_expr.X_add_number + 4, 16))
12339 {
12340 load_address (AT, &offset_expr, &used_at);
12341 offset_expr.X_op = O_constant;
12342 offset_expr.X_add_number = 0;
12343 }
12344 else
12345 macro_build_lui (&offset_expr, AT);
252b5132 12346 if (breg != 0)
67c0d1eb 12347 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
beae10d5 12348 /* Itbl support may require additional care here. */
c0ebe874 12349 macro_build (&offset_expr, s, fmt, coproc ? op[0] + 1 : op[0],
17a2f251 12350 BFD_RELOC_LO16, AT);
252b5132
RH
12351 /* FIXME: How do we handle overflow here? */
12352 offset_expr.X_add_number += 4;
beae10d5 12353 /* Itbl support may require additional care here. */
c0ebe874 12354 macro_build (&offset_expr, s, fmt, coproc ? op[0] : op[0] + 1,
17a2f251 12355 BFD_RELOC_LO16, AT);
4d7206a2
RS
12356 if (mips_relax.sequence)
12357 relax_end ();
bdaaa2e1 12358 }
0a44bf69 12359 else if (!mips_big_got)
252b5132 12360 {
252b5132
RH
12361 /* If this is a reference to an external symbol, we want
12362 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12363 nop
c0ebe874
RS
12364 <op> op[0],0($at)
12365 <op> op[0]+1,4($at)
252b5132
RH
12366 Otherwise we want
12367 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12368 nop
c0ebe874
RS
12369 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
12370 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
252b5132
RH
12371 If there is a base register we add it to $at before the
12372 lwc1 instructions. If there is a constant we include it
12373 in the lwc1 instructions. */
12374 used_at = 1;
12375 expr1.X_add_number = offset_expr.X_add_number;
252b5132
RH
12376 if (expr1.X_add_number < -0x8000
12377 || expr1.X_add_number >= 0x8000 - 4)
12378 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
67c0d1eb 12379 load_got_offset (AT, &offset_expr);
269137b2 12380 load_delay_nop ();
252b5132 12381 if (breg != 0)
67c0d1eb 12382 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
252b5132
RH
12383
12384 /* Set mips_optimize to 2 to avoid inserting an undesired
12385 nop. */
12386 hold_mips_optimize = mips_optimize;
12387 mips_optimize = 2;
4d7206a2 12388
beae10d5 12389 /* Itbl support may require additional care here. */
4d7206a2 12390 relax_start (offset_expr.X_add_symbol);
c0ebe874 12391 macro_build (&expr1, s, fmt, coproc ? op[0] + 1 : op[0],
67c0d1eb 12392 BFD_RELOC_LO16, AT);
4d7206a2 12393 expr1.X_add_number += 4;
c0ebe874 12394 macro_build (&expr1, s, fmt, coproc ? op[0] : op[0] + 1,
67c0d1eb 12395 BFD_RELOC_LO16, AT);
4d7206a2 12396 relax_switch ();
c0ebe874 12397 macro_build (&offset_expr, s, fmt, coproc ? op[0] + 1 : op[0],
67c0d1eb 12398 BFD_RELOC_LO16, AT);
4d7206a2 12399 offset_expr.X_add_number += 4;
c0ebe874 12400 macro_build (&offset_expr, s, fmt, coproc ? op[0] : op[0] + 1,
67c0d1eb 12401 BFD_RELOC_LO16, AT);
4d7206a2 12402 relax_end ();
252b5132 12403
4d7206a2 12404 mips_optimize = hold_mips_optimize;
252b5132 12405 }
0a44bf69 12406 else if (mips_big_got)
252b5132 12407 {
67c0d1eb 12408 int gpdelay;
252b5132
RH
12409
12410 /* If this is a reference to an external symbol, we want
12411 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
12412 addu $at,$at,$gp
12413 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
12414 nop
c0ebe874
RS
12415 <op> op[0],0($at)
12416 <op> op[0]+1,4($at)
252b5132
RH
12417 Otherwise we want
12418 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12419 nop
c0ebe874
RS
12420 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
12421 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
252b5132
RH
12422 If there is a base register we add it to $at before the
12423 lwc1 instructions. If there is a constant we include it
12424 in the lwc1 instructions. */
12425 used_at = 1;
12426 expr1.X_add_number = offset_expr.X_add_number;
12427 offset_expr.X_add_number = 0;
12428 if (expr1.X_add_number < -0x8000
12429 || expr1.X_add_number >= 0x8000 - 4)
12430 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
67c0d1eb 12431 gpdelay = reg_needs_delay (mips_gp_register);
4d7206a2 12432 relax_start (offset_expr.X_add_symbol);
df58fc94 12433 macro_build (&offset_expr, "lui", LUI_FMT,
67c0d1eb
RS
12434 AT, BFD_RELOC_MIPS_GOT_HI16);
12435 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
17a2f251 12436 AT, AT, mips_gp_register);
67c0d1eb 12437 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
17a2f251 12438 AT, BFD_RELOC_MIPS_GOT_LO16, AT);
269137b2 12439 load_delay_nop ();
252b5132 12440 if (breg != 0)
67c0d1eb 12441 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
beae10d5 12442 /* Itbl support may require additional care here. */
c0ebe874 12443 macro_build (&expr1, s, fmt, coproc ? op[0] + 1 : op[0],
17a2f251 12444 BFD_RELOC_LO16, AT);
252b5132
RH
12445 expr1.X_add_number += 4;
12446
12447 /* Set mips_optimize to 2 to avoid inserting an undesired
12448 nop. */
12449 hold_mips_optimize = mips_optimize;
12450 mips_optimize = 2;
beae10d5 12451 /* Itbl support may require additional care here. */
c0ebe874 12452 macro_build (&expr1, s, fmt, coproc ? op[0] : op[0] + 1,
17a2f251 12453 BFD_RELOC_LO16, AT);
252b5132
RH
12454 mips_optimize = hold_mips_optimize;
12455 expr1.X_add_number -= 4;
12456
4d7206a2
RS
12457 relax_switch ();
12458 offset_expr.X_add_number = expr1.X_add_number;
67c0d1eb
RS
12459 if (gpdelay)
12460 macro_build (NULL, "nop", "");
12461 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
12462 BFD_RELOC_MIPS_GOT16, mips_gp_register);
269137b2 12463 load_delay_nop ();
252b5132 12464 if (breg != 0)
67c0d1eb 12465 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
beae10d5 12466 /* Itbl support may require additional care here. */
c0ebe874 12467 macro_build (&offset_expr, s, fmt, coproc ? op[0] + 1 : op[0],
67c0d1eb 12468 BFD_RELOC_LO16, AT);
4d7206a2 12469 offset_expr.X_add_number += 4;
252b5132
RH
12470
12471 /* Set mips_optimize to 2 to avoid inserting an undesired
12472 nop. */
12473 hold_mips_optimize = mips_optimize;
12474 mips_optimize = 2;
beae10d5 12475 /* Itbl support may require additional care here. */
c0ebe874 12476 macro_build (&offset_expr, s, fmt, coproc ? op[0] : op[0] + 1,
67c0d1eb 12477 BFD_RELOC_LO16, AT);
252b5132 12478 mips_optimize = hold_mips_optimize;
4d7206a2 12479 relax_end ();
252b5132 12480 }
252b5132
RH
12481 else
12482 abort ();
12483
252b5132 12484 break;
dd6a37e7
AP
12485
12486 case M_SAA_AB:
dd6a37e7 12487 s = "saa";
0db377d0 12488 goto saa_saad;
dd6a37e7 12489 case M_SAAD_AB:
dd6a37e7 12490 s = "saad";
0db377d0
MR
12491 saa_saad:
12492 gas_assert (!mips_opts.micromips);
7f3c4072 12493 offbits = 0;
dd6a37e7
AP
12494 fmt = "t,(b)";
12495 goto ld_st;
12496
252b5132
RH
12497 /* New code added to support COPZ instructions.
12498 This code builds table entries out of the macros in mip_opcodes.
12499 R4000 uses interlocks to handle coproc delays.
12500 Other chips (like the R3000) require nops to be inserted for delays.
12501
f72c8c98 12502 FIXME: Currently, we require that the user handle delays.
252b5132
RH
12503 In order to fill delay slots for non-interlocked chips,
12504 we must have a way to specify delays based on the coprocessor.
12505 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
12506 What are the side-effects of the cop instruction?
12507 What cache support might we have and what are its effects?
12508 Both coprocessor & memory require delays. how long???
bdaaa2e1 12509 What registers are read/set/modified?
252b5132
RH
12510
12511 If an itbl is provided to interpret cop instructions,
bdaaa2e1 12512 this knowledge can be encoded in the itbl spec. */
252b5132
RH
12513
12514 case M_COP0:
12515 s = "c0";
12516 goto copz;
12517 case M_COP1:
12518 s = "c1";
12519 goto copz;
12520 case M_COP2:
12521 s = "c2";
12522 goto copz;
12523 case M_COP3:
12524 s = "c3";
12525 copz:
df58fc94 12526 gas_assert (!mips_opts.micromips);
252b5132
RH
12527 /* For now we just do C (same as Cz). The parameter will be
12528 stored in insn_opcode by mips_ip. */
c8276761 12529 macro_build (NULL, s, "C", (int) ip->insn_opcode);
8fc2e39e 12530 break;
252b5132 12531
ea1fb5dc 12532 case M_MOVE:
c0ebe874 12533 move_register (op[0], op[1]);
8fc2e39e 12534 break;
ea1fb5dc 12535
833794fc
MR
12536 case M_MOVEP:
12537 gas_assert (mips_opts.micromips);
12538 gas_assert (mips_opts.insn32);
c0ebe874
RS
12539 move_register (micromips_to_32_reg_h_map1[op[0]],
12540 micromips_to_32_reg_m_map[op[1]]);
12541 move_register (micromips_to_32_reg_h_map2[op[0]],
12542 micromips_to_32_reg_n_map[op[2]]);
833794fc
MR
12543 break;
12544
252b5132
RH
12545 case M_DMUL:
12546 dbl = 1;
12547 case M_MUL:
e407c74b 12548 if (mips_opts.arch == CPU_R5900)
c0ebe874
RS
12549 macro_build (NULL, dbl ? "dmultu" : "multu", "d,s,t", op[0], op[1],
12550 op[2]);
e407c74b
NC
12551 else
12552 {
c0ebe874
RS
12553 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", op[1], op[2]);
12554 macro_build (NULL, "mflo", MFHL_FMT, op[0]);
e407c74b 12555 }
8fc2e39e 12556 break;
252b5132
RH
12557
12558 case M_DMUL_I:
12559 dbl = 1;
12560 case M_MUL_I:
12561 /* The MIPS assembler some times generates shifts and adds. I'm
12562 not trying to be that fancy. GCC should do this for us
12563 anyway. */
8fc2e39e 12564 used_at = 1;
67c0d1eb 12565 load_register (AT, &imm_expr, dbl);
c0ebe874
RS
12566 macro_build (NULL, dbl ? "dmult" : "mult", "s,t", op[1], AT);
12567 macro_build (NULL, "mflo", MFHL_FMT, op[0]);
252b5132
RH
12568 break;
12569
12570 case M_DMULO_I:
12571 dbl = 1;
12572 case M_MULO_I:
12573 imm = 1;
12574 goto do_mulo;
12575
12576 case M_DMULO:
12577 dbl = 1;
12578 case M_MULO:
12579 do_mulo:
7d10b47d 12580 start_noreorder ();
8fc2e39e 12581 used_at = 1;
252b5132 12582 if (imm)
67c0d1eb 12583 load_register (AT, &imm_expr, dbl);
c0ebe874
RS
12584 macro_build (NULL, dbl ? "dmult" : "mult", "s,t",
12585 op[1], imm ? AT : op[2]);
12586 macro_build (NULL, "mflo", MFHL_FMT, op[0]);
12587 macro_build (NULL, dbl ? "dsra32" : "sra", SHFT_FMT, op[0], op[0], 31);
df58fc94 12588 macro_build (NULL, "mfhi", MFHL_FMT, AT);
252b5132 12589 if (mips_trap)
c0ebe874 12590 macro_build (NULL, "tne", TRAP_FMT, op[0], AT, 6);
252b5132
RH
12591 else
12592 {
df58fc94
RS
12593 if (mips_opts.micromips)
12594 micromips_label_expr (&label_expr);
12595 else
12596 label_expr.X_add_number = 8;
c0ebe874 12597 macro_build (&label_expr, "beq", "s,t,p", op[0], AT);
a605d2b3 12598 macro_build (NULL, "nop", "");
df58fc94
RS
12599 macro_build (NULL, "break", BRK_FMT, 6);
12600 if (mips_opts.micromips)
12601 micromips_add_label ();
252b5132 12602 }
7d10b47d 12603 end_noreorder ();
c0ebe874 12604 macro_build (NULL, "mflo", MFHL_FMT, op[0]);
252b5132
RH
12605 break;
12606
12607 case M_DMULOU_I:
12608 dbl = 1;
12609 case M_MULOU_I:
12610 imm = 1;
12611 goto do_mulou;
12612
12613 case M_DMULOU:
12614 dbl = 1;
12615 case M_MULOU:
12616 do_mulou:
7d10b47d 12617 start_noreorder ();
8fc2e39e 12618 used_at = 1;
252b5132 12619 if (imm)
67c0d1eb
RS
12620 load_register (AT, &imm_expr, dbl);
12621 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t",
c0ebe874 12622 op[1], imm ? AT : op[2]);
df58fc94 12623 macro_build (NULL, "mfhi", MFHL_FMT, AT);
c0ebe874 12624 macro_build (NULL, "mflo", MFHL_FMT, op[0]);
252b5132 12625 if (mips_trap)
df58fc94 12626 macro_build (NULL, "tne", TRAP_FMT, AT, ZERO, 6);
252b5132
RH
12627 else
12628 {
df58fc94
RS
12629 if (mips_opts.micromips)
12630 micromips_label_expr (&label_expr);
12631 else
12632 label_expr.X_add_number = 8;
12633 macro_build (&label_expr, "beq", "s,t,p", AT, ZERO);
a605d2b3 12634 macro_build (NULL, "nop", "");
df58fc94
RS
12635 macro_build (NULL, "break", BRK_FMT, 6);
12636 if (mips_opts.micromips)
12637 micromips_add_label ();
252b5132 12638 }
7d10b47d 12639 end_noreorder ();
252b5132
RH
12640 break;
12641
771c7ce4 12642 case M_DROL:
fef14a42 12643 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
82dd0097 12644 {
c0ebe874 12645 if (op[0] == op[1])
82dd0097
CD
12646 {
12647 tempreg = AT;
12648 used_at = 1;
12649 }
12650 else
c0ebe874
RS
12651 tempreg = op[0];
12652 macro_build (NULL, "dnegu", "d,w", tempreg, op[2]);
12653 macro_build (NULL, "drorv", "d,t,s", op[0], op[1], tempreg);
8fc2e39e 12654 break;
82dd0097 12655 }
8fc2e39e 12656 used_at = 1;
c0ebe874
RS
12657 macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, op[2]);
12658 macro_build (NULL, "dsrlv", "d,t,s", AT, op[1], AT);
12659 macro_build (NULL, "dsllv", "d,t,s", op[0], op[1], op[2]);
12660 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
771c7ce4
TS
12661 break;
12662
252b5132 12663 case M_ROL:
fef14a42 12664 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
82dd0097 12665 {
c0ebe874 12666 if (op[0] == op[1])
82dd0097
CD
12667 {
12668 tempreg = AT;
12669 used_at = 1;
12670 }
12671 else
c0ebe874
RS
12672 tempreg = op[0];
12673 macro_build (NULL, "negu", "d,w", tempreg, op[2]);
12674 macro_build (NULL, "rorv", "d,t,s", op[0], op[1], tempreg);
8fc2e39e 12675 break;
82dd0097 12676 }
8fc2e39e 12677 used_at = 1;
c0ebe874
RS
12678 macro_build (NULL, "subu", "d,v,t", AT, ZERO, op[2]);
12679 macro_build (NULL, "srlv", "d,t,s", AT, op[1], AT);
12680 macro_build (NULL, "sllv", "d,t,s", op[0], op[1], op[2]);
12681 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
252b5132
RH
12682 break;
12683
771c7ce4
TS
12684 case M_DROL_I:
12685 {
12686 unsigned int rot;
91d6fa6a
NC
12687 char *l;
12688 char *rr;
771c7ce4 12689
771c7ce4 12690 rot = imm_expr.X_add_number & 0x3f;
fef14a42 12691 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
60b63b72
RS
12692 {
12693 rot = (64 - rot) & 0x3f;
12694 if (rot >= 32)
c0ebe874 12695 macro_build (NULL, "dror32", SHFT_FMT, op[0], op[1], rot - 32);
60b63b72 12696 else
c0ebe874 12697 macro_build (NULL, "dror", SHFT_FMT, op[0], op[1], rot);
8fc2e39e 12698 break;
60b63b72 12699 }
483fc7cd 12700 if (rot == 0)
483fc7cd 12701 {
c0ebe874 12702 macro_build (NULL, "dsrl", SHFT_FMT, op[0], op[1], 0);
8fc2e39e 12703 break;
483fc7cd 12704 }
82dd0097 12705 l = (rot < 0x20) ? "dsll" : "dsll32";
91d6fa6a 12706 rr = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32";
82dd0097 12707 rot &= 0x1f;
8fc2e39e 12708 used_at = 1;
c0ebe874
RS
12709 macro_build (NULL, l, SHFT_FMT, AT, op[1], rot);
12710 macro_build (NULL, rr, SHFT_FMT, op[0], op[1], (0x20 - rot) & 0x1f);
12711 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
771c7ce4
TS
12712 }
12713 break;
12714
252b5132 12715 case M_ROL_I:
771c7ce4
TS
12716 {
12717 unsigned int rot;
12718
771c7ce4 12719 rot = imm_expr.X_add_number & 0x1f;
fef14a42 12720 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
60b63b72 12721 {
c0ebe874
RS
12722 macro_build (NULL, "ror", SHFT_FMT, op[0], op[1],
12723 (32 - rot) & 0x1f);
8fc2e39e 12724 break;
60b63b72 12725 }
483fc7cd 12726 if (rot == 0)
483fc7cd 12727 {
c0ebe874 12728 macro_build (NULL, "srl", SHFT_FMT, op[0], op[1], 0);
8fc2e39e 12729 break;
483fc7cd 12730 }
8fc2e39e 12731 used_at = 1;
c0ebe874
RS
12732 macro_build (NULL, "sll", SHFT_FMT, AT, op[1], rot);
12733 macro_build (NULL, "srl", SHFT_FMT, op[0], op[1], (0x20 - rot) & 0x1f);
12734 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
771c7ce4
TS
12735 }
12736 break;
12737
12738 case M_DROR:
fef14a42 12739 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
82dd0097 12740 {
c0ebe874 12741 macro_build (NULL, "drorv", "d,t,s", op[0], op[1], op[2]);
8fc2e39e 12742 break;
82dd0097 12743 }
8fc2e39e 12744 used_at = 1;
c0ebe874
RS
12745 macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, op[2]);
12746 macro_build (NULL, "dsllv", "d,t,s", AT, op[1], AT);
12747 macro_build (NULL, "dsrlv", "d,t,s", op[0], op[1], op[2]);
12748 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
252b5132
RH
12749 break;
12750
12751 case M_ROR:
fef14a42 12752 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
82dd0097 12753 {
c0ebe874 12754 macro_build (NULL, "rorv", "d,t,s", op[0], op[1], op[2]);
8fc2e39e 12755 break;
82dd0097 12756 }
8fc2e39e 12757 used_at = 1;
c0ebe874
RS
12758 macro_build (NULL, "subu", "d,v,t", AT, ZERO, op[2]);
12759 macro_build (NULL, "sllv", "d,t,s", AT, op[1], AT);
12760 macro_build (NULL, "srlv", "d,t,s", op[0], op[1], op[2]);
12761 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
252b5132
RH
12762 break;
12763
771c7ce4
TS
12764 case M_DROR_I:
12765 {
12766 unsigned int rot;
91d6fa6a
NC
12767 char *l;
12768 char *rr;
771c7ce4 12769
771c7ce4 12770 rot = imm_expr.X_add_number & 0x3f;
fef14a42 12771 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
82dd0097
CD
12772 {
12773 if (rot >= 32)
c0ebe874 12774 macro_build (NULL, "dror32", SHFT_FMT, op[0], op[1], rot - 32);
82dd0097 12775 else
c0ebe874 12776 macro_build (NULL, "dror", SHFT_FMT, op[0], op[1], rot);
8fc2e39e 12777 break;
82dd0097 12778 }
483fc7cd 12779 if (rot == 0)
483fc7cd 12780 {
c0ebe874 12781 macro_build (NULL, "dsrl", SHFT_FMT, op[0], op[1], 0);
8fc2e39e 12782 break;
483fc7cd 12783 }
91d6fa6a 12784 rr = (rot < 0x20) ? "dsrl" : "dsrl32";
82dd0097
CD
12785 l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32";
12786 rot &= 0x1f;
8fc2e39e 12787 used_at = 1;
c0ebe874
RS
12788 macro_build (NULL, rr, SHFT_FMT, AT, op[1], rot);
12789 macro_build (NULL, l, SHFT_FMT, op[0], op[1], (0x20 - rot) & 0x1f);
12790 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
771c7ce4
TS
12791 }
12792 break;
12793
252b5132 12794 case M_ROR_I:
771c7ce4
TS
12795 {
12796 unsigned int rot;
12797
771c7ce4 12798 rot = imm_expr.X_add_number & 0x1f;
fef14a42 12799 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
82dd0097 12800 {
c0ebe874 12801 macro_build (NULL, "ror", SHFT_FMT, op[0], op[1], rot);
8fc2e39e 12802 break;
82dd0097 12803 }
483fc7cd 12804 if (rot == 0)
483fc7cd 12805 {
c0ebe874 12806 macro_build (NULL, "srl", SHFT_FMT, op[0], op[1], 0);
8fc2e39e 12807 break;
483fc7cd 12808 }
8fc2e39e 12809 used_at = 1;
c0ebe874
RS
12810 macro_build (NULL, "srl", SHFT_FMT, AT, op[1], rot);
12811 macro_build (NULL, "sll", SHFT_FMT, op[0], op[1], (0x20 - rot) & 0x1f);
12812 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
771c7ce4 12813 }
252b5132
RH
12814 break;
12815
252b5132 12816 case M_SEQ:
c0ebe874
RS
12817 if (op[1] == 0)
12818 macro_build (&expr1, "sltiu", "t,r,j", op[0], op[2], BFD_RELOC_LO16);
12819 else if (op[2] == 0)
12820 macro_build (&expr1, "sltiu", "t,r,j", op[0], op[1], BFD_RELOC_LO16);
252b5132
RH
12821 else
12822 {
c0ebe874
RS
12823 macro_build (NULL, "xor", "d,v,t", op[0], op[1], op[2]);
12824 macro_build (&expr1, "sltiu", "t,r,j", op[0], op[0], BFD_RELOC_LO16);
252b5132 12825 }
8fc2e39e 12826 break;
252b5132
RH
12827
12828 case M_SEQ_I:
b0e6f033 12829 if (imm_expr.X_add_number == 0)
252b5132 12830 {
c0ebe874 12831 macro_build (&expr1, "sltiu", "t,r,j", op[0], op[1], BFD_RELOC_LO16);
8fc2e39e 12832 break;
252b5132 12833 }
c0ebe874 12834 if (op[1] == 0)
252b5132 12835 {
1661c76c 12836 as_warn (_("instruction %s: result is always false"),
252b5132 12837 ip->insn_mo->name);
c0ebe874 12838 move_register (op[0], 0);
8fc2e39e 12839 break;
252b5132 12840 }
dd3cbb7e
NC
12841 if (CPU_HAS_SEQ (mips_opts.arch)
12842 && -512 <= imm_expr.X_add_number
12843 && imm_expr.X_add_number < 512)
12844 {
c0ebe874 12845 macro_build (NULL, "seqi", "t,r,+Q", op[0], op[1],
750bdd57 12846 (int) imm_expr.X_add_number);
dd3cbb7e
NC
12847 break;
12848 }
b0e6f033 12849 if (imm_expr.X_add_number >= 0
252b5132 12850 && imm_expr.X_add_number < 0x10000)
c0ebe874 12851 macro_build (&imm_expr, "xori", "t,r,i", op[0], op[1], BFD_RELOC_LO16);
b0e6f033 12852 else if (imm_expr.X_add_number > -0x8000
252b5132
RH
12853 && imm_expr.X_add_number < 0)
12854 {
12855 imm_expr.X_add_number = -imm_expr.X_add_number;
bad1aba3 12856 macro_build (&imm_expr, GPR_SIZE == 32 ? "addiu" : "daddiu",
c0ebe874 12857 "t,r,j", op[0], op[1], BFD_RELOC_LO16);
252b5132 12858 }
dd3cbb7e
NC
12859 else if (CPU_HAS_SEQ (mips_opts.arch))
12860 {
12861 used_at = 1;
bad1aba3 12862 load_register (AT, &imm_expr, GPR_SIZE == 64);
c0ebe874 12863 macro_build (NULL, "seq", "d,v,t", op[0], op[1], AT);
dd3cbb7e
NC
12864 break;
12865 }
252b5132
RH
12866 else
12867 {
bad1aba3 12868 load_register (AT, &imm_expr, GPR_SIZE == 64);
c0ebe874 12869 macro_build (NULL, "xor", "d,v,t", op[0], op[1], AT);
252b5132
RH
12870 used_at = 1;
12871 }
c0ebe874 12872 macro_build (&expr1, "sltiu", "t,r,j", op[0], op[0], BFD_RELOC_LO16);
8fc2e39e 12873 break;
252b5132 12874
c0ebe874 12875 case M_SGE: /* X >= Y <==> not (X < Y) */
252b5132
RH
12876 s = "slt";
12877 goto sge;
12878 case M_SGEU:
12879 s = "sltu";
12880 sge:
c0ebe874
RS
12881 macro_build (NULL, s, "d,v,t", op[0], op[1], op[2]);
12882 macro_build (&expr1, "xori", "t,r,i", op[0], op[0], BFD_RELOC_LO16);
8fc2e39e 12883 break;
252b5132 12884
c0ebe874 12885 case M_SGE_I: /* X >= I <==> not (X < I) */
252b5132 12886 case M_SGEU_I:
b0e6f033 12887 if (imm_expr.X_add_number >= -0x8000
252b5132 12888 && imm_expr.X_add_number < 0x8000)
c0ebe874
RS
12889 macro_build (&imm_expr, mask == M_SGE_I ? "slti" : "sltiu", "t,r,j",
12890 op[0], op[1], BFD_RELOC_LO16);
252b5132
RH
12891 else
12892 {
bad1aba3 12893 load_register (AT, &imm_expr, GPR_SIZE == 64);
67c0d1eb 12894 macro_build (NULL, mask == M_SGE_I ? "slt" : "sltu", "d,v,t",
c0ebe874 12895 op[0], op[1], AT);
252b5132
RH
12896 used_at = 1;
12897 }
c0ebe874 12898 macro_build (&expr1, "xori", "t,r,i", op[0], op[0], BFD_RELOC_LO16);
8fc2e39e 12899 break;
252b5132 12900
c0ebe874 12901 case M_SGT: /* X > Y <==> Y < X */
252b5132
RH
12902 s = "slt";
12903 goto sgt;
12904 case M_SGTU:
12905 s = "sltu";
12906 sgt:
c0ebe874 12907 macro_build (NULL, s, "d,v,t", op[0], op[2], op[1]);
8fc2e39e 12908 break;
252b5132 12909
c0ebe874 12910 case M_SGT_I: /* X > I <==> I < X */
252b5132
RH
12911 s = "slt";
12912 goto sgti;
12913 case M_SGTU_I:
12914 s = "sltu";
12915 sgti:
8fc2e39e 12916 used_at = 1;
bad1aba3 12917 load_register (AT, &imm_expr, GPR_SIZE == 64);
c0ebe874 12918 macro_build (NULL, s, "d,v,t", op[0], AT, op[1]);
252b5132
RH
12919 break;
12920
c0ebe874 12921 case M_SLE: /* X <= Y <==> Y >= X <==> not (Y < X) */
252b5132
RH
12922 s = "slt";
12923 goto sle;
12924 case M_SLEU:
12925 s = "sltu";
12926 sle:
c0ebe874
RS
12927 macro_build (NULL, s, "d,v,t", op[0], op[2], op[1]);
12928 macro_build (&expr1, "xori", "t,r,i", op[0], op[0], BFD_RELOC_LO16);
8fc2e39e 12929 break;
252b5132 12930
c0ebe874 12931 case M_SLE_I: /* X <= I <==> I >= X <==> not (I < X) */
252b5132
RH
12932 s = "slt";
12933 goto slei;
12934 case M_SLEU_I:
12935 s = "sltu";
12936 slei:
8fc2e39e 12937 used_at = 1;
bad1aba3 12938 load_register (AT, &imm_expr, GPR_SIZE == 64);
c0ebe874
RS
12939 macro_build (NULL, s, "d,v,t", op[0], AT, op[1]);
12940 macro_build (&expr1, "xori", "t,r,i", op[0], op[0], BFD_RELOC_LO16);
252b5132
RH
12941 break;
12942
12943 case M_SLT_I:
b0e6f033 12944 if (imm_expr.X_add_number >= -0x8000
252b5132
RH
12945 && imm_expr.X_add_number < 0x8000)
12946 {
c0ebe874
RS
12947 macro_build (&imm_expr, "slti", "t,r,j", op[0], op[1],
12948 BFD_RELOC_LO16);
8fc2e39e 12949 break;
252b5132 12950 }
8fc2e39e 12951 used_at = 1;
bad1aba3 12952 load_register (AT, &imm_expr, GPR_SIZE == 64);
c0ebe874 12953 macro_build (NULL, "slt", "d,v,t", op[0], op[1], AT);
252b5132
RH
12954 break;
12955
12956 case M_SLTU_I:
b0e6f033 12957 if (imm_expr.X_add_number >= -0x8000
252b5132
RH
12958 && imm_expr.X_add_number < 0x8000)
12959 {
c0ebe874 12960 macro_build (&imm_expr, "sltiu", "t,r,j", op[0], op[1],
17a2f251 12961 BFD_RELOC_LO16);
8fc2e39e 12962 break;
252b5132 12963 }
8fc2e39e 12964 used_at = 1;
bad1aba3 12965 load_register (AT, &imm_expr, GPR_SIZE == 64);
c0ebe874 12966 macro_build (NULL, "sltu", "d,v,t", op[0], op[1], AT);
252b5132
RH
12967 break;
12968
12969 case M_SNE:
c0ebe874
RS
12970 if (op[1] == 0)
12971 macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[2]);
12972 else if (op[2] == 0)
12973 macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[1]);
252b5132
RH
12974 else
12975 {
c0ebe874
RS
12976 macro_build (NULL, "xor", "d,v,t", op[0], op[1], op[2]);
12977 macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[0]);
252b5132 12978 }
8fc2e39e 12979 break;
252b5132
RH
12980
12981 case M_SNE_I:
b0e6f033 12982 if (imm_expr.X_add_number == 0)
252b5132 12983 {
c0ebe874 12984 macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[1]);
8fc2e39e 12985 break;
252b5132 12986 }
c0ebe874 12987 if (op[1] == 0)
252b5132 12988 {
1661c76c 12989 as_warn (_("instruction %s: result is always true"),
252b5132 12990 ip->insn_mo->name);
bad1aba3 12991 macro_build (&expr1, GPR_SIZE == 32 ? "addiu" : "daddiu", "t,r,j",
c0ebe874 12992 op[0], 0, BFD_RELOC_LO16);
8fc2e39e 12993 break;
252b5132 12994 }
dd3cbb7e
NC
12995 if (CPU_HAS_SEQ (mips_opts.arch)
12996 && -512 <= imm_expr.X_add_number
12997 && imm_expr.X_add_number < 512)
12998 {
c0ebe874 12999 macro_build (NULL, "snei", "t,r,+Q", op[0], op[1],
750bdd57 13000 (int) imm_expr.X_add_number);
dd3cbb7e
NC
13001 break;
13002 }
b0e6f033 13003 if (imm_expr.X_add_number >= 0
252b5132
RH
13004 && imm_expr.X_add_number < 0x10000)
13005 {
c0ebe874
RS
13006 macro_build (&imm_expr, "xori", "t,r,i", op[0], op[1],
13007 BFD_RELOC_LO16);
252b5132 13008 }
b0e6f033 13009 else if (imm_expr.X_add_number > -0x8000
252b5132
RH
13010 && imm_expr.X_add_number < 0)
13011 {
13012 imm_expr.X_add_number = -imm_expr.X_add_number;
bad1aba3 13013 macro_build (&imm_expr, GPR_SIZE == 32 ? "addiu" : "daddiu",
c0ebe874 13014 "t,r,j", op[0], op[1], BFD_RELOC_LO16);
252b5132 13015 }
dd3cbb7e
NC
13016 else if (CPU_HAS_SEQ (mips_opts.arch))
13017 {
13018 used_at = 1;
bad1aba3 13019 load_register (AT, &imm_expr, GPR_SIZE == 64);
c0ebe874 13020 macro_build (NULL, "sne", "d,v,t", op[0], op[1], AT);
dd3cbb7e
NC
13021 break;
13022 }
252b5132
RH
13023 else
13024 {
bad1aba3 13025 load_register (AT, &imm_expr, GPR_SIZE == 64);
c0ebe874 13026 macro_build (NULL, "xor", "d,v,t", op[0], op[1], AT);
252b5132
RH
13027 used_at = 1;
13028 }
c0ebe874 13029 macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[0]);
8fc2e39e 13030 break;
252b5132 13031
df58fc94
RS
13032 case M_SUB_I:
13033 s = "addi";
13034 s2 = "sub";
13035 goto do_subi;
13036 case M_SUBU_I:
13037 s = "addiu";
13038 s2 = "subu";
13039 goto do_subi;
252b5132
RH
13040 case M_DSUB_I:
13041 dbl = 1;
df58fc94
RS
13042 s = "daddi";
13043 s2 = "dsub";
13044 if (!mips_opts.micromips)
13045 goto do_subi;
b0e6f033 13046 if (imm_expr.X_add_number > -0x200
df58fc94 13047 && imm_expr.X_add_number <= 0x200)
252b5132 13048 {
b0e6f033
RS
13049 macro_build (NULL, s, "t,r,.", op[0], op[1],
13050 (int) -imm_expr.X_add_number);
8fc2e39e 13051 break;
252b5132 13052 }
df58fc94 13053 goto do_subi_i;
252b5132
RH
13054 case M_DSUBU_I:
13055 dbl = 1;
df58fc94
RS
13056 s = "daddiu";
13057 s2 = "dsubu";
13058 do_subi:
b0e6f033 13059 if (imm_expr.X_add_number > -0x8000
252b5132
RH
13060 && imm_expr.X_add_number <= 0x8000)
13061 {
13062 imm_expr.X_add_number = -imm_expr.X_add_number;
c0ebe874 13063 macro_build (&imm_expr, s, "t,r,j", op[0], op[1], BFD_RELOC_LO16);
8fc2e39e 13064 break;
252b5132 13065 }
df58fc94 13066 do_subi_i:
8fc2e39e 13067 used_at = 1;
67c0d1eb 13068 load_register (AT, &imm_expr, dbl);
c0ebe874 13069 macro_build (NULL, s2, "d,v,t", op[0], op[1], AT);
252b5132
RH
13070 break;
13071
13072 case M_TEQ_I:
13073 s = "teq";
13074 goto trap;
13075 case M_TGE_I:
13076 s = "tge";
13077 goto trap;
13078 case M_TGEU_I:
13079 s = "tgeu";
13080 goto trap;
13081 case M_TLT_I:
13082 s = "tlt";
13083 goto trap;
13084 case M_TLTU_I:
13085 s = "tltu";
13086 goto trap;
13087 case M_TNE_I:
13088 s = "tne";
13089 trap:
8fc2e39e 13090 used_at = 1;
bad1aba3 13091 load_register (AT, &imm_expr, GPR_SIZE == 64);
c0ebe874 13092 macro_build (NULL, s, "s,t", op[0], AT);
252b5132
RH
13093 break;
13094
252b5132 13095 case M_TRUNCWS:
43841e91 13096 case M_TRUNCWD:
df58fc94 13097 gas_assert (!mips_opts.micromips);
0aa27725 13098 gas_assert (mips_opts.isa == ISA_MIPS1);
8fc2e39e 13099 used_at = 1;
252b5132
RH
13100
13101 /*
13102 * Is the double cfc1 instruction a bug in the mips assembler;
13103 * or is there a reason for it?
13104 */
7d10b47d 13105 start_noreorder ();
c0ebe874
RS
13106 macro_build (NULL, "cfc1", "t,G", op[2], RA);
13107 macro_build (NULL, "cfc1", "t,G", op[2], RA);
67c0d1eb 13108 macro_build (NULL, "nop", "");
252b5132 13109 expr1.X_add_number = 3;
c0ebe874 13110 macro_build (&expr1, "ori", "t,r,i", AT, op[2], BFD_RELOC_LO16);
252b5132 13111 expr1.X_add_number = 2;
67c0d1eb
RS
13112 macro_build (&expr1, "xori", "t,r,i", AT, AT, BFD_RELOC_LO16);
13113 macro_build (NULL, "ctc1", "t,G", AT, RA);
13114 macro_build (NULL, "nop", "");
13115 macro_build (NULL, mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S",
c0ebe874
RS
13116 op[0], op[1]);
13117 macro_build (NULL, "ctc1", "t,G", op[2], RA);
67c0d1eb 13118 macro_build (NULL, "nop", "");
7d10b47d 13119 end_noreorder ();
252b5132
RH
13120 break;
13121
f2ae14a1 13122 case M_ULH_AB:
252b5132 13123 s = "lb";
df58fc94
RS
13124 s2 = "lbu";
13125 off = 1;
13126 goto uld_st;
f2ae14a1 13127 case M_ULHU_AB:
252b5132 13128 s = "lbu";
df58fc94
RS
13129 s2 = "lbu";
13130 off = 1;
13131 goto uld_st;
f2ae14a1 13132 case M_ULW_AB:
df58fc94
RS
13133 s = "lwl";
13134 s2 = "lwr";
7f3c4072 13135 offbits = (mips_opts.micromips ? 12 : 16);
df58fc94
RS
13136 off = 3;
13137 goto uld_st;
f2ae14a1 13138 case M_ULD_AB:
252b5132
RH
13139 s = "ldl";
13140 s2 = "ldr";
7f3c4072 13141 offbits = (mips_opts.micromips ? 12 : 16);
252b5132 13142 off = 7;
df58fc94 13143 goto uld_st;
f2ae14a1 13144 case M_USH_AB:
df58fc94
RS
13145 s = "sb";
13146 s2 = "sb";
13147 off = 1;
13148 ust = 1;
13149 goto uld_st;
f2ae14a1 13150 case M_USW_AB:
df58fc94
RS
13151 s = "swl";
13152 s2 = "swr";
7f3c4072 13153 offbits = (mips_opts.micromips ? 12 : 16);
252b5132 13154 off = 3;
df58fc94
RS
13155 ust = 1;
13156 goto uld_st;
f2ae14a1 13157 case M_USD_AB:
df58fc94
RS
13158 s = "sdl";
13159 s2 = "sdr";
7f3c4072 13160 offbits = (mips_opts.micromips ? 12 : 16);
df58fc94
RS
13161 off = 7;
13162 ust = 1;
13163
13164 uld_st:
c0ebe874 13165 breg = op[2];
f2ae14a1 13166 large_offset = !small_offset_p (off, align, offbits);
df58fc94
RS
13167 ep = &offset_expr;
13168 expr1.X_add_number = 0;
f2ae14a1 13169 if (large_offset)
df58fc94
RS
13170 {
13171 used_at = 1;
13172 tempreg = AT;
f2ae14a1
RS
13173 if (small_offset_p (0, align, 16))
13174 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", tempreg, breg, -1,
13175 offset_reloc[0], offset_reloc[1], offset_reloc[2]);
13176 else
13177 {
13178 load_address (tempreg, ep, &used_at);
13179 if (breg != 0)
13180 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
13181 tempreg, tempreg, breg);
13182 }
13183 offset_reloc[0] = BFD_RELOC_LO16;
13184 offset_reloc[1] = BFD_RELOC_UNUSED;
13185 offset_reloc[2] = BFD_RELOC_UNUSED;
df58fc94 13186 breg = tempreg;
c0ebe874 13187 tempreg = op[0];
df58fc94
RS
13188 ep = &expr1;
13189 }
c0ebe874 13190 else if (!ust && op[0] == breg)
8fc2e39e
TS
13191 {
13192 used_at = 1;
13193 tempreg = AT;
13194 }
252b5132 13195 else
c0ebe874 13196 tempreg = op[0];
af22f5b2 13197
df58fc94
RS
13198 if (off == 1)
13199 goto ulh_sh;
252b5132 13200
90ecf173 13201 if (!target_big_endian)
df58fc94 13202 ep->X_add_number += off;
f2ae14a1 13203 if (offbits == 12)
c8276761 13204 macro_build (NULL, s, "t,~(b)", tempreg, (int) ep->X_add_number, breg);
f2ae14a1
RS
13205 else
13206 macro_build (ep, s, "t,o(b)", tempreg, -1,
13207 offset_reloc[0], offset_reloc[1], offset_reloc[2], breg);
df58fc94 13208
90ecf173 13209 if (!target_big_endian)
df58fc94 13210 ep->X_add_number -= off;
252b5132 13211 else
df58fc94 13212 ep->X_add_number += off;
f2ae14a1 13213 if (offbits == 12)
df58fc94 13214 macro_build (NULL, s2, "t,~(b)",
c8276761 13215 tempreg, (int) ep->X_add_number, breg);
f2ae14a1
RS
13216 else
13217 macro_build (ep, s2, "t,o(b)", tempreg, -1,
13218 offset_reloc[0], offset_reloc[1], offset_reloc[2], breg);
252b5132 13219
df58fc94 13220 /* If necessary, move the result in tempreg to the final destination. */
c0ebe874 13221 if (!ust && op[0] != tempreg)
df58fc94
RS
13222 {
13223 /* Protect second load's delay slot. */
13224 load_delay_nop ();
c0ebe874 13225 move_register (op[0], tempreg);
df58fc94 13226 }
8fc2e39e 13227 break;
252b5132 13228
df58fc94 13229 ulh_sh:
d6bc6245 13230 used_at = 1;
df58fc94
RS
13231 if (target_big_endian == ust)
13232 ep->X_add_number += off;
c0ebe874 13233 tempreg = ust || large_offset ? op[0] : AT;
f2ae14a1
RS
13234 macro_build (ep, s, "t,o(b)", tempreg, -1,
13235 offset_reloc[0], offset_reloc[1], offset_reloc[2], breg);
df58fc94
RS
13236
13237 /* For halfword transfers we need a temporary register to shuffle
13238 bytes. Unfortunately for M_USH_A we have none available before
13239 the next store as AT holds the base address. We deal with this
13240 case by clobbering TREG and then restoring it as with ULH. */
c0ebe874 13241 tempreg = ust == large_offset ? op[0] : AT;
df58fc94 13242 if (ust)
c0ebe874 13243 macro_build (NULL, "srl", SHFT_FMT, tempreg, op[0], 8);
df58fc94
RS
13244
13245 if (target_big_endian == ust)
13246 ep->X_add_number -= off;
252b5132 13247 else
df58fc94 13248 ep->X_add_number += off;
f2ae14a1
RS
13249 macro_build (ep, s2, "t,o(b)", tempreg, -1,
13250 offset_reloc[0], offset_reloc[1], offset_reloc[2], breg);
252b5132 13251
df58fc94 13252 /* For M_USH_A re-retrieve the LSB. */
f2ae14a1 13253 if (ust && large_offset)
df58fc94
RS
13254 {
13255 if (target_big_endian)
13256 ep->X_add_number += off;
13257 else
13258 ep->X_add_number -= off;
f2ae14a1
RS
13259 macro_build (&expr1, "lbu", "t,o(b)", AT, -1,
13260 offset_reloc[0], offset_reloc[1], offset_reloc[2], AT);
df58fc94
RS
13261 }
13262 /* For ULH and M_USH_A OR the LSB in. */
f2ae14a1 13263 if (!ust || large_offset)
df58fc94 13264 {
c0ebe874 13265 tempreg = !large_offset ? AT : op[0];
df58fc94 13266 macro_build (NULL, "sll", SHFT_FMT, tempreg, tempreg, 8);
c0ebe874 13267 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
df58fc94 13268 }
252b5132
RH
13269 break;
13270
13271 default:
13272 /* FIXME: Check if this is one of the itbl macros, since they
bdaaa2e1 13273 are added dynamically. */
1661c76c 13274 as_bad (_("macro %s not implemented yet"), ip->insn_mo->name);
252b5132
RH
13275 break;
13276 }
741fe287 13277 if (!mips_opts.at && used_at)
1661c76c 13278 as_bad (_("macro used $at after \".set noat\""));
252b5132
RH
13279}
13280
13281/* Implement macros in mips16 mode. */
13282
13283static void
17a2f251 13284mips16_macro (struct mips_cl_insn *ip)
252b5132 13285{
c0ebe874 13286 const struct mips_operand_array *operands;
252b5132 13287 int mask;
c0ebe874 13288 int tmp;
252b5132
RH
13289 expressionS expr1;
13290 int dbl;
13291 const char *s, *s2, *s3;
c0ebe874
RS
13292 unsigned int op[MAX_OPERANDS];
13293 unsigned int i;
252b5132
RH
13294
13295 mask = ip->insn_mo->mask;
13296
c0ebe874
RS
13297 operands = insn_operands (ip);
13298 for (i = 0; i < MAX_OPERANDS; i++)
13299 if (operands->operand[i])
13300 op[i] = insn_extract_operand (ip, operands->operand[i]);
13301 else
13302 op[i] = -1;
252b5132 13303
252b5132
RH
13304 expr1.X_op = O_constant;
13305 expr1.X_op_symbol = NULL;
13306 expr1.X_add_symbol = NULL;
13307 expr1.X_add_number = 1;
13308
13309 dbl = 0;
13310
13311 switch (mask)
13312 {
13313 default:
b37df7c4 13314 abort ();
252b5132
RH
13315
13316 case M_DDIV_3:
13317 dbl = 1;
13318 case M_DIV_3:
13319 s = "mflo";
13320 goto do_div3;
13321 case M_DREM_3:
13322 dbl = 1;
13323 case M_REM_3:
13324 s = "mfhi";
13325 do_div3:
7d10b47d 13326 start_noreorder ();
c0ebe874 13327 macro_build (NULL, dbl ? "ddiv" : "div", "0,x,y", op[1], op[2]);
252b5132 13328 expr1.X_add_number = 2;
c0ebe874 13329 macro_build (&expr1, "bnez", "x,p", op[2]);
67c0d1eb 13330 macro_build (NULL, "break", "6", 7);
bdaaa2e1 13331
252b5132
RH
13332 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
13333 since that causes an overflow. We should do that as well,
13334 but I don't see how to do the comparisons without a temporary
13335 register. */
7d10b47d 13336 end_noreorder ();
c0ebe874 13337 macro_build (NULL, s, "x", op[0]);
252b5132
RH
13338 break;
13339
13340 case M_DIVU_3:
13341 s = "divu";
13342 s2 = "mflo";
13343 goto do_divu3;
13344 case M_REMU_3:
13345 s = "divu";
13346 s2 = "mfhi";
13347 goto do_divu3;
13348 case M_DDIVU_3:
13349 s = "ddivu";
13350 s2 = "mflo";
13351 goto do_divu3;
13352 case M_DREMU_3:
13353 s = "ddivu";
13354 s2 = "mfhi";
13355 do_divu3:
7d10b47d 13356 start_noreorder ();
c0ebe874 13357 macro_build (NULL, s, "0,x,y", op[1], op[2]);
252b5132 13358 expr1.X_add_number = 2;
c0ebe874 13359 macro_build (&expr1, "bnez", "x,p", op[2]);
67c0d1eb 13360 macro_build (NULL, "break", "6", 7);
7d10b47d 13361 end_noreorder ();
c0ebe874 13362 macro_build (NULL, s2, "x", op[0]);
252b5132
RH
13363 break;
13364
13365 case M_DMUL:
13366 dbl = 1;
13367 case M_MUL:
c0ebe874
RS
13368 macro_build (NULL, dbl ? "dmultu" : "multu", "x,y", op[1], op[2]);
13369 macro_build (NULL, "mflo", "x", op[0]);
8fc2e39e 13370 break;
252b5132
RH
13371
13372 case M_DSUBU_I:
13373 dbl = 1;
13374 goto do_subu;
13375 case M_SUBU_I:
13376 do_subu:
252b5132 13377 imm_expr.X_add_number = -imm_expr.X_add_number;
c0ebe874 13378 macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "y,x,4", op[0], op[1]);
252b5132
RH
13379 break;
13380
13381 case M_SUBU_I_2:
252b5132 13382 imm_expr.X_add_number = -imm_expr.X_add_number;
c0ebe874 13383 macro_build (&imm_expr, "addiu", "x,k", op[0]);
252b5132
RH
13384 break;
13385
13386 case M_DSUBU_I_2:
252b5132 13387 imm_expr.X_add_number = -imm_expr.X_add_number;
c0ebe874 13388 macro_build (&imm_expr, "daddiu", "y,j", op[0]);
252b5132
RH
13389 break;
13390
13391 case M_BEQ:
13392 s = "cmp";
13393 s2 = "bteqz";
13394 goto do_branch;
13395 case M_BNE:
13396 s = "cmp";
13397 s2 = "btnez";
13398 goto do_branch;
13399 case M_BLT:
13400 s = "slt";
13401 s2 = "btnez";
13402 goto do_branch;
13403 case M_BLTU:
13404 s = "sltu";
13405 s2 = "btnez";
13406 goto do_branch;
13407 case M_BLE:
13408 s = "slt";
13409 s2 = "bteqz";
13410 goto do_reverse_branch;
13411 case M_BLEU:
13412 s = "sltu";
13413 s2 = "bteqz";
13414 goto do_reverse_branch;
13415 case M_BGE:
13416 s = "slt";
13417 s2 = "bteqz";
13418 goto do_branch;
13419 case M_BGEU:
13420 s = "sltu";
13421 s2 = "bteqz";
13422 goto do_branch;
13423 case M_BGT:
13424 s = "slt";
13425 s2 = "btnez";
13426 goto do_reverse_branch;
13427 case M_BGTU:
13428 s = "sltu";
13429 s2 = "btnez";
13430
13431 do_reverse_branch:
c0ebe874
RS
13432 tmp = op[1];
13433 op[1] = op[0];
13434 op[0] = tmp;
252b5132
RH
13435
13436 do_branch:
c0ebe874 13437 macro_build (NULL, s, "x,y", op[0], op[1]);
67c0d1eb 13438 macro_build (&offset_expr, s2, "p");
252b5132
RH
13439 break;
13440
13441 case M_BEQ_I:
13442 s = "cmpi";
13443 s2 = "bteqz";
13444 s3 = "x,U";
13445 goto do_branch_i;
13446 case M_BNE_I:
13447 s = "cmpi";
13448 s2 = "btnez";
13449 s3 = "x,U";
13450 goto do_branch_i;
13451 case M_BLT_I:
13452 s = "slti";
13453 s2 = "btnez";
13454 s3 = "x,8";
13455 goto do_branch_i;
13456 case M_BLTU_I:
13457 s = "sltiu";
13458 s2 = "btnez";
13459 s3 = "x,8";
13460 goto do_branch_i;
13461 case M_BLE_I:
13462 s = "slti";
13463 s2 = "btnez";
13464 s3 = "x,8";
13465 goto do_addone_branch_i;
13466 case M_BLEU_I:
13467 s = "sltiu";
13468 s2 = "btnez";
13469 s3 = "x,8";
13470 goto do_addone_branch_i;
13471 case M_BGE_I:
13472 s = "slti";
13473 s2 = "bteqz";
13474 s3 = "x,8";
13475 goto do_branch_i;
13476 case M_BGEU_I:
13477 s = "sltiu";
13478 s2 = "bteqz";
13479 s3 = "x,8";
13480 goto do_branch_i;
13481 case M_BGT_I:
13482 s = "slti";
13483 s2 = "bteqz";
13484 s3 = "x,8";
13485 goto do_addone_branch_i;
13486 case M_BGTU_I:
13487 s = "sltiu";
13488 s2 = "bteqz";
13489 s3 = "x,8";
13490
13491 do_addone_branch_i:
252b5132
RH
13492 ++imm_expr.X_add_number;
13493
13494 do_branch_i:
c0ebe874 13495 macro_build (&imm_expr, s, s3, op[0]);
67c0d1eb 13496 macro_build (&offset_expr, s2, "p");
252b5132
RH
13497 break;
13498
13499 case M_ABS:
13500 expr1.X_add_number = 0;
c0ebe874
RS
13501 macro_build (&expr1, "slti", "x,8", op[1]);
13502 if (op[0] != op[1])
13503 macro_build (NULL, "move", "y,X", op[0], mips16_to_32_reg_map[op[1]]);
252b5132 13504 expr1.X_add_number = 2;
67c0d1eb 13505 macro_build (&expr1, "bteqz", "p");
c0ebe874 13506 macro_build (NULL, "neg", "x,w", op[0], op[0]);
0acfaea6 13507 break;
252b5132
RH
13508 }
13509}
13510
14daeee3
RS
13511/* Look up instruction [START, START + LENGTH) in HASH. Record any extra
13512 opcode bits in *OPCODE_EXTRA. */
13513
13514static struct mips_opcode *
13515mips_lookup_insn (struct hash_control *hash, const char *start,
da8bca91 13516 ssize_t length, unsigned int *opcode_extra)
14daeee3
RS
13517{
13518 char *name, *dot, *p;
13519 unsigned int mask, suffix;
da8bca91 13520 ssize_t opend;
14daeee3
RS
13521 struct mips_opcode *insn;
13522
13523 /* Make a copy of the instruction so that we can fiddle with it. */
13524 name = alloca (length + 1);
13525 memcpy (name, start, length);
13526 name[length] = '\0';
13527
13528 /* Look up the instruction as-is. */
13529 insn = (struct mips_opcode *) hash_find (hash, name);
ee5734f0 13530 if (insn)
14daeee3
RS
13531 return insn;
13532
13533 dot = strchr (name, '.');
13534 if (dot && dot[1])
13535 {
13536 /* Try to interpret the text after the dot as a VU0 channel suffix. */
13537 p = mips_parse_vu0_channels (dot + 1, &mask);
13538 if (*p == 0 && mask != 0)
13539 {
13540 *dot = 0;
13541 insn = (struct mips_opcode *) hash_find (hash, name);
13542 *dot = '.';
13543 if (insn && (insn->pinfo2 & INSN2_VU0_CHANNEL_SUFFIX) != 0)
13544 {
13545 *opcode_extra |= mask << mips_vu0_channel_mask.lsb;
13546 return insn;
13547 }
13548 }
13549 }
13550
13551 if (mips_opts.micromips)
13552 {
13553 /* See if there's an instruction size override suffix,
13554 either `16' or `32', at the end of the mnemonic proper,
13555 that defines the operation, i.e. before the first `.'
13556 character if any. Strip it and retry. */
13557 opend = dot != NULL ? dot - name : length;
13558 if (opend >= 3 && name[opend - 2] == '1' && name[opend - 1] == '6')
13559 suffix = 2;
13560 else if (name[opend - 2] == '3' && name[opend - 1] == '2')
13561 suffix = 4;
13562 else
13563 suffix = 0;
13564 if (suffix)
13565 {
13566 memcpy (name + opend - 2, name + opend, length - opend + 1);
13567 insn = (struct mips_opcode *) hash_find (hash, name);
ee5734f0 13568 if (insn)
14daeee3
RS
13569 {
13570 forced_insn_length = suffix;
13571 return insn;
13572 }
13573 }
13574 }
13575
13576 return NULL;
13577}
13578
77bd4346 13579/* Assemble an instruction into its binary format. If the instruction
e423441d
RS
13580 is a macro, set imm_expr and offset_expr to the values associated
13581 with "I" and "A" operands respectively. Otherwise store the value
13582 of the relocatable field (if any) in offset_expr. In both cases
13583 set offset_reloc to the relocation operators applied to offset_expr. */
252b5132
RH
13584
13585static void
60f20e8b 13586mips_ip (char *str, struct mips_cl_insn *insn)
252b5132 13587{
60f20e8b 13588 const struct mips_opcode *first, *past;
df58fc94 13589 struct hash_control *hash;
a92713e6 13590 char format;
14daeee3 13591 size_t end;
a92713e6 13592 struct mips_operand_token *tokens;
14daeee3 13593 unsigned int opcode_extra;
252b5132 13594
df58fc94
RS
13595 if (mips_opts.micromips)
13596 {
13597 hash = micromips_op_hash;
13598 past = &micromips_opcodes[bfd_micromips_num_opcodes];
13599 }
13600 else
13601 {
13602 hash = op_hash;
13603 past = &mips_opcodes[NUMOPCODES];
13604 }
13605 forced_insn_length = 0;
14daeee3 13606 opcode_extra = 0;
252b5132 13607
df58fc94 13608 /* We first try to match an instruction up to a space or to the end. */
a40bc9dd
RS
13609 for (end = 0; str[end] != '\0' && !ISSPACE (str[end]); end++)
13610 continue;
bdaaa2e1 13611
60f20e8b
RS
13612 first = mips_lookup_insn (hash, str, end, &opcode_extra);
13613 if (first == NULL)
252b5132 13614 {
1661c76c 13615 set_insn_error (0, _("unrecognized opcode"));
a40bc9dd 13616 return;
252b5132
RH
13617 }
13618
60f20e8b 13619 if (strcmp (first->name, "li.s") == 0)
a92713e6 13620 format = 'f';
60f20e8b 13621 else if (strcmp (first->name, "li.d") == 0)
a92713e6
RS
13622 format = 'd';
13623 else
13624 format = 0;
13625 tokens = mips_parse_arguments (str + end, format);
13626 if (!tokens)
13627 return;
13628
60f20e8b
RS
13629 if (!match_insns (insn, first, past, tokens, opcode_extra, FALSE)
13630 && !match_insns (insn, first, past, tokens, opcode_extra, TRUE))
1661c76c 13631 set_insn_error (0, _("invalid operands"));
df58fc94 13632
e3de51ce 13633 obstack_free (&mips_operand_tokens, tokens);
252b5132
RH
13634}
13635
77bd4346
RS
13636/* As for mips_ip, but used when assembling MIPS16 code.
13637 Also set forced_insn_length to the resulting instruction size in
13638 bytes if the user explicitly requested a small or extended instruction. */
252b5132
RH
13639
13640static void
60f20e8b 13641mips16_ip (char *str, struct mips_cl_insn *insn)
252b5132 13642{
1a00e612 13643 char *end, *s, c;
60f20e8b 13644 struct mips_opcode *first;
a92713e6 13645 struct mips_operand_token *tokens;
252b5132 13646
df58fc94 13647 forced_insn_length = 0;
252b5132 13648
3882b010 13649 for (s = str; ISLOWER (*s); ++s)
252b5132 13650 ;
1a00e612
RS
13651 end = s;
13652 c = *end;
13653 switch (c)
252b5132
RH
13654 {
13655 case '\0':
13656 break;
13657
13658 case ' ':
1a00e612 13659 s++;
252b5132
RH
13660 break;
13661
13662 case '.':
13663 if (s[1] == 't' && s[2] == ' ')
13664 {
df58fc94 13665 forced_insn_length = 2;
252b5132
RH
13666 s += 3;
13667 break;
13668 }
13669 else if (s[1] == 'e' && s[2] == ' ')
13670 {
df58fc94 13671 forced_insn_length = 4;
252b5132
RH
13672 s += 3;
13673 break;
13674 }
13675 /* Fall through. */
13676 default:
1661c76c 13677 set_insn_error (0, _("unrecognized opcode"));
252b5132
RH
13678 return;
13679 }
13680
df58fc94
RS
13681 if (mips_opts.noautoextend && !forced_insn_length)
13682 forced_insn_length = 2;
252b5132 13683
1a00e612 13684 *end = 0;
60f20e8b 13685 first = (struct mips_opcode *) hash_find (mips16_op_hash, str);
1a00e612
RS
13686 *end = c;
13687
60f20e8b 13688 if (!first)
252b5132 13689 {
1661c76c 13690 set_insn_error (0, _("unrecognized opcode"));
252b5132
RH
13691 return;
13692 }
13693
a92713e6
RS
13694 tokens = mips_parse_arguments (s, 0);
13695 if (!tokens)
13696 return;
13697
60f20e8b 13698 if (!match_mips16_insns (insn, first, tokens))
1661c76c 13699 set_insn_error (0, _("invalid operands"));
252b5132 13700
e3de51ce 13701 obstack_free (&mips_operand_tokens, tokens);
252b5132
RH
13702}
13703
b886a2ab
RS
13704/* Marshal immediate value VAL for an extended MIPS16 instruction.
13705 NBITS is the number of significant bits in VAL. */
13706
13707static unsigned long
13708mips16_immed_extend (offsetT val, unsigned int nbits)
13709{
13710 int extval;
13711 if (nbits == 16)
13712 {
13713 extval = ((val >> 11) & 0x1f) | (val & 0x7e0);
13714 val &= 0x1f;
13715 }
13716 else if (nbits == 15)
13717 {
13718 extval = ((val >> 11) & 0xf) | (val & 0x7f0);
13719 val &= 0xf;
13720 }
13721 else
13722 {
13723 extval = ((val & 0x1f) << 6) | (val & 0x20);
13724 val = 0;
13725 }
13726 return (extval << 16) | val;
13727}
13728
3ccad066
RS
13729/* Like decode_mips16_operand, but require the operand to be defined and
13730 require it to be an integer. */
13731
13732static const struct mips_int_operand *
13733mips16_immed_operand (int type, bfd_boolean extended_p)
13734{
13735 const struct mips_operand *operand;
13736
13737 operand = decode_mips16_operand (type, extended_p);
13738 if (!operand || (operand->type != OP_INT && operand->type != OP_PCREL))
13739 abort ();
13740 return (const struct mips_int_operand *) operand;
13741}
13742
13743/* Return true if SVAL fits OPERAND. RELOC is as for mips16_immed. */
13744
13745static bfd_boolean
13746mips16_immed_in_range_p (const struct mips_int_operand *operand,
13747 bfd_reloc_code_real_type reloc, offsetT sval)
13748{
13749 int min_val, max_val;
13750
13751 min_val = mips_int_operand_min (operand);
13752 max_val = mips_int_operand_max (operand);
13753 if (reloc != BFD_RELOC_UNUSED)
13754 {
13755 if (min_val < 0)
13756 sval = SEXT_16BIT (sval);
13757 else
13758 sval &= 0xffff;
13759 }
13760
13761 return (sval >= min_val
13762 && sval <= max_val
13763 && (sval & ((1 << operand->shift) - 1)) == 0);
13764}
13765
5c04167a
RS
13766/* Install immediate value VAL into MIPS16 instruction *INSN,
13767 extending it if necessary. The instruction in *INSN may
13768 already be extended.
13769
43c0598f
RS
13770 RELOC is the relocation that produced VAL, or BFD_RELOC_UNUSED
13771 if none. In the former case, VAL is a 16-bit number with no
13772 defined signedness.
13773
13774 TYPE is the type of the immediate field. USER_INSN_LENGTH
13775 is the length that the user requested, or 0 if none. */
252b5132
RH
13776
13777static void
43c0598f
RS
13778mips16_immed (char *file, unsigned int line, int type,
13779 bfd_reloc_code_real_type reloc, offsetT val,
5c04167a 13780 unsigned int user_insn_length, unsigned long *insn)
252b5132 13781{
3ccad066
RS
13782 const struct mips_int_operand *operand;
13783 unsigned int uval, length;
252b5132 13784
3ccad066
RS
13785 operand = mips16_immed_operand (type, FALSE);
13786 if (!mips16_immed_in_range_p (operand, reloc, val))
5c04167a
RS
13787 {
13788 /* We need an extended instruction. */
13789 if (user_insn_length == 2)
13790 as_bad_where (file, line, _("invalid unextended operand value"));
13791 else
13792 *insn |= MIPS16_EXTEND;
13793 }
13794 else if (user_insn_length == 4)
13795 {
13796 /* The operand doesn't force an unextended instruction to be extended.
13797 Warn if the user wanted an extended instruction anyway. */
13798 *insn |= MIPS16_EXTEND;
13799 as_warn_where (file, line,
13800 _("extended operand requested but not required"));
13801 }
252b5132 13802
3ccad066
RS
13803 length = mips16_opcode_length (*insn);
13804 if (length == 4)
252b5132 13805 {
3ccad066
RS
13806 operand = mips16_immed_operand (type, TRUE);
13807 if (!mips16_immed_in_range_p (operand, reloc, val))
13808 as_bad_where (file, line,
13809 _("operand value out of range for instruction"));
252b5132 13810 }
3ccad066
RS
13811 uval = ((unsigned int) val >> operand->shift) - operand->bias;
13812 if (length == 2)
13813 *insn = mips_insert_operand (&operand->root, *insn, uval);
252b5132 13814 else
3ccad066 13815 *insn |= mips16_immed_extend (uval, operand->root.size);
252b5132
RH
13816}
13817\f
d6f16593 13818struct percent_op_match
ad8d3bb3 13819{
5e0116d5
RS
13820 const char *str;
13821 bfd_reloc_code_real_type reloc;
d6f16593
MR
13822};
13823
13824static const struct percent_op_match mips_percent_op[] =
ad8d3bb3 13825{
5e0116d5 13826 {"%lo", BFD_RELOC_LO16},
5e0116d5
RS
13827 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16},
13828 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16},
13829 {"%call16", BFD_RELOC_MIPS_CALL16},
13830 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP},
13831 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE},
13832 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST},
13833 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16},
13834 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16},
13835 {"%got", BFD_RELOC_MIPS_GOT16},
13836 {"%gp_rel", BFD_RELOC_GPREL16},
13837 {"%half", BFD_RELOC_16},
13838 {"%highest", BFD_RELOC_MIPS_HIGHEST},
13839 {"%higher", BFD_RELOC_MIPS_HIGHER},
13840 {"%neg", BFD_RELOC_MIPS_SUB},
3f98094e
DJ
13841 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD},
13842 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM},
13843 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16},
13844 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16},
13845 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16},
13846 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16},
13847 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL},
7361da2c
AB
13848 {"%hi", BFD_RELOC_HI16_S},
13849 {"%pcrel_hi", BFD_RELOC_HI16_S_PCREL},
13850 {"%pcrel_lo", BFD_RELOC_LO16_PCREL}
ad8d3bb3
TS
13851};
13852
d6f16593
MR
13853static const struct percent_op_match mips16_percent_op[] =
13854{
13855 {"%lo", BFD_RELOC_MIPS16_LO16},
13856 {"%gprel", BFD_RELOC_MIPS16_GPREL},
738e5348
RS
13857 {"%got", BFD_RELOC_MIPS16_GOT16},
13858 {"%call16", BFD_RELOC_MIPS16_CALL16},
d0f13682
CLT
13859 {"%hi", BFD_RELOC_MIPS16_HI16_S},
13860 {"%tlsgd", BFD_RELOC_MIPS16_TLS_GD},
13861 {"%tlsldm", BFD_RELOC_MIPS16_TLS_LDM},
13862 {"%dtprel_hi", BFD_RELOC_MIPS16_TLS_DTPREL_HI16},
13863 {"%dtprel_lo", BFD_RELOC_MIPS16_TLS_DTPREL_LO16},
13864 {"%tprel_hi", BFD_RELOC_MIPS16_TLS_TPREL_HI16},
13865 {"%tprel_lo", BFD_RELOC_MIPS16_TLS_TPREL_LO16},
13866 {"%gottprel", BFD_RELOC_MIPS16_TLS_GOTTPREL}
d6f16593
MR
13867};
13868
252b5132 13869
5e0116d5
RS
13870/* Return true if *STR points to a relocation operator. When returning true,
13871 move *STR over the operator and store its relocation code in *RELOC.
13872 Leave both *STR and *RELOC alone when returning false. */
13873
13874static bfd_boolean
17a2f251 13875parse_relocation (char **str, bfd_reloc_code_real_type *reloc)
252b5132 13876{
d6f16593
MR
13877 const struct percent_op_match *percent_op;
13878 size_t limit, i;
13879
13880 if (mips_opts.mips16)
13881 {
13882 percent_op = mips16_percent_op;
13883 limit = ARRAY_SIZE (mips16_percent_op);
13884 }
13885 else
13886 {
13887 percent_op = mips_percent_op;
13888 limit = ARRAY_SIZE (mips_percent_op);
13889 }
76b3015f 13890
d6f16593 13891 for (i = 0; i < limit; i++)
5e0116d5 13892 if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0)
394f9b3a 13893 {
3f98094e
DJ
13894 int len = strlen (percent_op[i].str);
13895
13896 if (!ISSPACE ((*str)[len]) && (*str)[len] != '(')
13897 continue;
13898
5e0116d5
RS
13899 *str += strlen (percent_op[i].str);
13900 *reloc = percent_op[i].reloc;
394f9b3a 13901
5e0116d5
RS
13902 /* Check whether the output BFD supports this relocation.
13903 If not, issue an error and fall back on something safe. */
13904 if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc))
394f9b3a 13905 {
20203fb9 13906 as_bad (_("relocation %s isn't supported by the current ABI"),
5e0116d5 13907 percent_op[i].str);
01a3f561 13908 *reloc = BFD_RELOC_UNUSED;
394f9b3a 13909 }
5e0116d5 13910 return TRUE;
394f9b3a 13911 }
5e0116d5 13912 return FALSE;
394f9b3a 13913}
ad8d3bb3 13914
ad8d3bb3 13915
5e0116d5
RS
13916/* Parse string STR as a 16-bit relocatable operand. Store the
13917 expression in *EP and the relocations in the array starting
13918 at RELOC. Return the number of relocation operators used.
ad8d3bb3 13919
01a3f561 13920 On exit, EXPR_END points to the first character after the expression. */
ad8d3bb3 13921
5e0116d5 13922static size_t
17a2f251
TS
13923my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc,
13924 char *str)
ad8d3bb3 13925{
5e0116d5
RS
13926 bfd_reloc_code_real_type reversed_reloc[3];
13927 size_t reloc_index, i;
09b8f35a
RS
13928 int crux_depth, str_depth;
13929 char *crux;
5e0116d5
RS
13930
13931 /* Search for the start of the main expression, recoding relocations
09b8f35a
RS
13932 in REVERSED_RELOC. End the loop with CRUX pointing to the start
13933 of the main expression and with CRUX_DEPTH containing the number
13934 of open brackets at that point. */
13935 reloc_index = -1;
13936 str_depth = 0;
13937 do
fb1b3232 13938 {
09b8f35a
RS
13939 reloc_index++;
13940 crux = str;
13941 crux_depth = str_depth;
13942
13943 /* Skip over whitespace and brackets, keeping count of the number
13944 of brackets. */
13945 while (*str == ' ' || *str == '\t' || *str == '(')
13946 if (*str++ == '(')
13947 str_depth++;
5e0116d5 13948 }
09b8f35a
RS
13949 while (*str == '%'
13950 && reloc_index < (HAVE_NEWABI ? 3 : 1)
13951 && parse_relocation (&str, &reversed_reloc[reloc_index]));
ad8d3bb3 13952
09b8f35a 13953 my_getExpression (ep, crux);
5e0116d5 13954 str = expr_end;
394f9b3a 13955
5e0116d5 13956 /* Match every open bracket. */
09b8f35a 13957 while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t'))
5e0116d5 13958 if (*str++ == ')')
09b8f35a 13959 crux_depth--;
394f9b3a 13960
09b8f35a 13961 if (crux_depth > 0)
20203fb9 13962 as_bad (_("unclosed '('"));
394f9b3a 13963
5e0116d5 13964 expr_end = str;
252b5132 13965
01a3f561 13966 if (reloc_index != 0)
64bdfcaf
RS
13967 {
13968 prev_reloc_op_frag = frag_now;
13969 for (i = 0; i < reloc_index; i++)
13970 reloc[i] = reversed_reloc[reloc_index - 1 - i];
13971 }
fb1b3232 13972
5e0116d5 13973 return reloc_index;
252b5132
RH
13974}
13975
13976static void
17a2f251 13977my_getExpression (expressionS *ep, char *str)
252b5132
RH
13978{
13979 char *save_in;
13980
13981 save_in = input_line_pointer;
13982 input_line_pointer = str;
13983 expression (ep);
13984 expr_end = input_line_pointer;
13985 input_line_pointer = save_in;
252b5132
RH
13986}
13987
252b5132 13988char *
17a2f251 13989md_atof (int type, char *litP, int *sizeP)
252b5132 13990{
499ac353 13991 return ieee_md_atof (type, litP, sizeP, target_big_endian);
252b5132
RH
13992}
13993
13994void
17a2f251 13995md_number_to_chars (char *buf, valueT val, int n)
252b5132
RH
13996{
13997 if (target_big_endian)
13998 number_to_chars_bigendian (buf, val, n);
13999 else
14000 number_to_chars_littleendian (buf, val, n);
14001}
14002\f
e013f690
TS
14003static int support_64bit_objects(void)
14004{
14005 const char **list, **l;
aa3d8fdf 14006 int yes;
e013f690
TS
14007
14008 list = bfd_target_list ();
14009 for (l = list; *l != NULL; l++)
aeffff67
RS
14010 if (strcmp (*l, ELF_TARGET ("elf64-", "big")) == 0
14011 || strcmp (*l, ELF_TARGET ("elf64-", "little")) == 0)
e013f690 14012 break;
aa3d8fdf 14013 yes = (*l != NULL);
e013f690 14014 free (list);
aa3d8fdf 14015 return yes;
e013f690
TS
14016}
14017
316f5878
RS
14018/* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
14019 NEW_VALUE. Warn if another value was already specified. Note:
14020 we have to defer parsing the -march and -mtune arguments in order
14021 to handle 'from-abi' correctly, since the ABI might be specified
14022 in a later argument. */
14023
14024static void
17a2f251 14025mips_set_option_string (const char **string_ptr, const char *new_value)
316f5878
RS
14026{
14027 if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0)
1661c76c 14028 as_warn (_("a different %s was already specified, is now %s"),
316f5878
RS
14029 string_ptr == &mips_arch_string ? "-march" : "-mtune",
14030 new_value);
14031
14032 *string_ptr = new_value;
14033}
14034
252b5132 14035int
17a2f251 14036md_parse_option (int c, char *arg)
252b5132 14037{
c6278170
RS
14038 unsigned int i;
14039
14040 for (i = 0; i < ARRAY_SIZE (mips_ases); i++)
14041 if (c == mips_ases[i].option_on || c == mips_ases[i].option_off)
14042 {
919731af 14043 file_ase_explicit |= mips_set_ase (&mips_ases[i], &file_mips_opts,
c6278170
RS
14044 c == mips_ases[i].option_on);
14045 return 1;
14046 }
14047
252b5132
RH
14048 switch (c)
14049 {
119d663a
NC
14050 case OPTION_CONSTRUCT_FLOATS:
14051 mips_disable_float_construction = 0;
14052 break;
bdaaa2e1 14053
119d663a
NC
14054 case OPTION_NO_CONSTRUCT_FLOATS:
14055 mips_disable_float_construction = 1;
14056 break;
bdaaa2e1 14057
252b5132
RH
14058 case OPTION_TRAP:
14059 mips_trap = 1;
14060 break;
14061
14062 case OPTION_BREAK:
14063 mips_trap = 0;
14064 break;
14065
14066 case OPTION_EB:
14067 target_big_endian = 1;
14068 break;
14069
14070 case OPTION_EL:
14071 target_big_endian = 0;
14072 break;
14073
14074 case 'O':
4ffff32f
TS
14075 if (arg == NULL)
14076 mips_optimize = 1;
14077 else if (arg[0] == '0')
14078 mips_optimize = 0;
14079 else if (arg[0] == '1')
252b5132
RH
14080 mips_optimize = 1;
14081 else
14082 mips_optimize = 2;
14083 break;
14084
14085 case 'g':
14086 if (arg == NULL)
14087 mips_debug = 2;
14088 else
14089 mips_debug = atoi (arg);
252b5132
RH
14090 break;
14091
14092 case OPTION_MIPS1:
0b35dfee 14093 file_mips_opts.isa = ISA_MIPS1;
252b5132
RH
14094 break;
14095
14096 case OPTION_MIPS2:
0b35dfee 14097 file_mips_opts.isa = ISA_MIPS2;
252b5132
RH
14098 break;
14099
14100 case OPTION_MIPS3:
0b35dfee 14101 file_mips_opts.isa = ISA_MIPS3;
252b5132
RH
14102 break;
14103
14104 case OPTION_MIPS4:
0b35dfee 14105 file_mips_opts.isa = ISA_MIPS4;
e7af610e
NC
14106 break;
14107
84ea6cf2 14108 case OPTION_MIPS5:
0b35dfee 14109 file_mips_opts.isa = ISA_MIPS5;
84ea6cf2
NC
14110 break;
14111
e7af610e 14112 case OPTION_MIPS32:
0b35dfee 14113 file_mips_opts.isa = ISA_MIPS32;
252b5132
RH
14114 break;
14115
af7ee8bf 14116 case OPTION_MIPS32R2:
0b35dfee 14117 file_mips_opts.isa = ISA_MIPS32R2;
af7ee8bf
CD
14118 break;
14119
ae52f483 14120 case OPTION_MIPS32R3:
0ae19f05 14121 file_mips_opts.isa = ISA_MIPS32R3;
ae52f483
AB
14122 break;
14123
14124 case OPTION_MIPS32R5:
0ae19f05 14125 file_mips_opts.isa = ISA_MIPS32R5;
ae52f483
AB
14126 break;
14127
7361da2c
AB
14128 case OPTION_MIPS32R6:
14129 file_mips_opts.isa = ISA_MIPS32R6;
14130 break;
14131
5f74bc13 14132 case OPTION_MIPS64R2:
0b35dfee 14133 file_mips_opts.isa = ISA_MIPS64R2;
5f74bc13
CD
14134 break;
14135
ae52f483 14136 case OPTION_MIPS64R3:
0ae19f05 14137 file_mips_opts.isa = ISA_MIPS64R3;
ae52f483
AB
14138 break;
14139
14140 case OPTION_MIPS64R5:
0ae19f05 14141 file_mips_opts.isa = ISA_MIPS64R5;
ae52f483
AB
14142 break;
14143
7361da2c
AB
14144 case OPTION_MIPS64R6:
14145 file_mips_opts.isa = ISA_MIPS64R6;
14146 break;
14147
84ea6cf2 14148 case OPTION_MIPS64:
0b35dfee 14149 file_mips_opts.isa = ISA_MIPS64;
84ea6cf2
NC
14150 break;
14151
ec68c924 14152 case OPTION_MTUNE:
316f5878
RS
14153 mips_set_option_string (&mips_tune_string, arg);
14154 break;
ec68c924 14155
316f5878
RS
14156 case OPTION_MARCH:
14157 mips_set_option_string (&mips_arch_string, arg);
252b5132
RH
14158 break;
14159
14160 case OPTION_M4650:
316f5878
RS
14161 mips_set_option_string (&mips_arch_string, "4650");
14162 mips_set_option_string (&mips_tune_string, "4650");
252b5132
RH
14163 break;
14164
14165 case OPTION_NO_M4650:
14166 break;
14167
14168 case OPTION_M4010:
316f5878
RS
14169 mips_set_option_string (&mips_arch_string, "4010");
14170 mips_set_option_string (&mips_tune_string, "4010");
252b5132
RH
14171 break;
14172
14173 case OPTION_NO_M4010:
14174 break;
14175
14176 case OPTION_M4100:
316f5878
RS
14177 mips_set_option_string (&mips_arch_string, "4100");
14178 mips_set_option_string (&mips_tune_string, "4100");
252b5132
RH
14179 break;
14180
14181 case OPTION_NO_M4100:
14182 break;
14183
252b5132 14184 case OPTION_M3900:
316f5878
RS
14185 mips_set_option_string (&mips_arch_string, "3900");
14186 mips_set_option_string (&mips_tune_string, "3900");
252b5132 14187 break;
bdaaa2e1 14188
252b5132
RH
14189 case OPTION_NO_M3900:
14190 break;
14191
df58fc94 14192 case OPTION_MICROMIPS:
919731af 14193 if (file_mips_opts.mips16 == 1)
df58fc94
RS
14194 {
14195 as_bad (_("-mmicromips cannot be used with -mips16"));
14196 return 0;
14197 }
919731af 14198 file_mips_opts.micromips = 1;
df58fc94
RS
14199 mips_no_prev_insn ();
14200 break;
14201
14202 case OPTION_NO_MICROMIPS:
919731af 14203 file_mips_opts.micromips = 0;
df58fc94
RS
14204 mips_no_prev_insn ();
14205 break;
14206
252b5132 14207 case OPTION_MIPS16:
919731af 14208 if (file_mips_opts.micromips == 1)
df58fc94
RS
14209 {
14210 as_bad (_("-mips16 cannot be used with -micromips"));
14211 return 0;
14212 }
919731af 14213 file_mips_opts.mips16 = 1;
7d10b47d 14214 mips_no_prev_insn ();
252b5132
RH
14215 break;
14216
14217 case OPTION_NO_MIPS16:
919731af 14218 file_mips_opts.mips16 = 0;
7d10b47d 14219 mips_no_prev_insn ();
252b5132
RH
14220 break;
14221
6a32d874
CM
14222 case OPTION_FIX_24K:
14223 mips_fix_24k = 1;
14224 break;
14225
14226 case OPTION_NO_FIX_24K:
14227 mips_fix_24k = 0;
14228 break;
14229
a8d14a88
CM
14230 case OPTION_FIX_RM7000:
14231 mips_fix_rm7000 = 1;
14232 break;
14233
14234 case OPTION_NO_FIX_RM7000:
14235 mips_fix_rm7000 = 0;
14236 break;
14237
c67a084a
NC
14238 case OPTION_FIX_LOONGSON2F_JUMP:
14239 mips_fix_loongson2f_jump = TRUE;
14240 break;
14241
14242 case OPTION_NO_FIX_LOONGSON2F_JUMP:
14243 mips_fix_loongson2f_jump = FALSE;
14244 break;
14245
14246 case OPTION_FIX_LOONGSON2F_NOP:
14247 mips_fix_loongson2f_nop = TRUE;
14248 break;
14249
14250 case OPTION_NO_FIX_LOONGSON2F_NOP:
14251 mips_fix_loongson2f_nop = FALSE;
14252 break;
14253
d766e8ec
RS
14254 case OPTION_FIX_VR4120:
14255 mips_fix_vr4120 = 1;
60b63b72
RS
14256 break;
14257
d766e8ec
RS
14258 case OPTION_NO_FIX_VR4120:
14259 mips_fix_vr4120 = 0;
60b63b72
RS
14260 break;
14261
7d8e00cf
RS
14262 case OPTION_FIX_VR4130:
14263 mips_fix_vr4130 = 1;
14264 break;
14265
14266 case OPTION_NO_FIX_VR4130:
14267 mips_fix_vr4130 = 0;
14268 break;
14269
d954098f
DD
14270 case OPTION_FIX_CN63XXP1:
14271 mips_fix_cn63xxp1 = TRUE;
14272 break;
14273
14274 case OPTION_NO_FIX_CN63XXP1:
14275 mips_fix_cn63xxp1 = FALSE;
14276 break;
14277
4a6a3df4
AO
14278 case OPTION_RELAX_BRANCH:
14279 mips_relax_branch = 1;
14280 break;
14281
14282 case OPTION_NO_RELAX_BRANCH:
14283 mips_relax_branch = 0;
14284 break;
14285
833794fc 14286 case OPTION_INSN32:
919731af 14287 file_mips_opts.insn32 = TRUE;
833794fc
MR
14288 break;
14289
14290 case OPTION_NO_INSN32:
919731af 14291 file_mips_opts.insn32 = FALSE;
833794fc
MR
14292 break;
14293
aa6975fb
ILT
14294 case OPTION_MSHARED:
14295 mips_in_shared = TRUE;
14296 break;
14297
14298 case OPTION_MNO_SHARED:
14299 mips_in_shared = FALSE;
14300 break;
14301
aed1a261 14302 case OPTION_MSYM32:
919731af 14303 file_mips_opts.sym32 = TRUE;
aed1a261
RS
14304 break;
14305
14306 case OPTION_MNO_SYM32:
919731af 14307 file_mips_opts.sym32 = FALSE;
aed1a261
RS
14308 break;
14309
252b5132
RH
14310 /* When generating ELF code, we permit -KPIC and -call_shared to
14311 select SVR4_PIC, and -non_shared to select no PIC. This is
14312 intended to be compatible with Irix 5. */
14313 case OPTION_CALL_SHARED:
252b5132 14314 mips_pic = SVR4_PIC;
143d77c5 14315 mips_abicalls = TRUE;
252b5132
RH
14316 break;
14317
861fb55a 14318 case OPTION_CALL_NONPIC:
861fb55a
DJ
14319 mips_pic = NO_PIC;
14320 mips_abicalls = TRUE;
14321 break;
14322
252b5132 14323 case OPTION_NON_SHARED:
252b5132 14324 mips_pic = NO_PIC;
143d77c5 14325 mips_abicalls = FALSE;
252b5132
RH
14326 break;
14327
44075ae2
TS
14328 /* The -xgot option tells the assembler to use 32 bit offsets
14329 when accessing the got in SVR4_PIC mode. It is for Irix
252b5132
RH
14330 compatibility. */
14331 case OPTION_XGOT:
14332 mips_big_got = 1;
14333 break;
14334
14335 case 'G':
6caf9ef4
TS
14336 g_switch_value = atoi (arg);
14337 g_switch_seen = 1;
252b5132
RH
14338 break;
14339
34ba82a8
TS
14340 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
14341 and -mabi=64. */
252b5132 14342 case OPTION_32:
f3ded42a 14343 mips_abi = O32_ABI;
252b5132
RH
14344 break;
14345
e013f690 14346 case OPTION_N32:
316f5878 14347 mips_abi = N32_ABI;
e013f690 14348 break;
252b5132 14349
e013f690 14350 case OPTION_64:
316f5878 14351 mips_abi = N64_ABI;
f43abd2b 14352 if (!support_64bit_objects())
1661c76c 14353 as_fatal (_("no compiled in support for 64 bit object file format"));
252b5132
RH
14354 break;
14355
c97ef257 14356 case OPTION_GP32:
bad1aba3 14357 file_mips_opts.gp = 32;
c97ef257
AH
14358 break;
14359
14360 case OPTION_GP64:
bad1aba3 14361 file_mips_opts.gp = 64;
c97ef257 14362 break;
252b5132 14363
ca4e0257 14364 case OPTION_FP32:
0b35dfee 14365 file_mips_opts.fp = 32;
316f5878
RS
14366 break;
14367
351cdf24
MF
14368 case OPTION_FPXX:
14369 file_mips_opts.fp = 0;
14370 break;
14371
316f5878 14372 case OPTION_FP64:
0b35dfee 14373 file_mips_opts.fp = 64;
ca4e0257
RS
14374 break;
14375
351cdf24
MF
14376 case OPTION_ODD_SPREG:
14377 file_mips_opts.oddspreg = 1;
14378 break;
14379
14380 case OPTION_NO_ODD_SPREG:
14381 file_mips_opts.oddspreg = 0;
14382 break;
14383
037b32b9 14384 case OPTION_SINGLE_FLOAT:
0b35dfee 14385 file_mips_opts.single_float = 1;
037b32b9
AN
14386 break;
14387
14388 case OPTION_DOUBLE_FLOAT:
0b35dfee 14389 file_mips_opts.single_float = 0;
037b32b9
AN
14390 break;
14391
14392 case OPTION_SOFT_FLOAT:
0b35dfee 14393 file_mips_opts.soft_float = 1;
037b32b9
AN
14394 break;
14395
14396 case OPTION_HARD_FLOAT:
0b35dfee 14397 file_mips_opts.soft_float = 0;
037b32b9
AN
14398 break;
14399
252b5132 14400 case OPTION_MABI:
e013f690 14401 if (strcmp (arg, "32") == 0)
316f5878 14402 mips_abi = O32_ABI;
e013f690 14403 else if (strcmp (arg, "o64") == 0)
316f5878 14404 mips_abi = O64_ABI;
e013f690 14405 else if (strcmp (arg, "n32") == 0)
316f5878 14406 mips_abi = N32_ABI;
e013f690
TS
14407 else if (strcmp (arg, "64") == 0)
14408 {
316f5878 14409 mips_abi = N64_ABI;
e013f690 14410 if (! support_64bit_objects())
1661c76c 14411 as_fatal (_("no compiled in support for 64 bit object file "
e013f690
TS
14412 "format"));
14413 }
14414 else if (strcmp (arg, "eabi") == 0)
316f5878 14415 mips_abi = EABI_ABI;
e013f690 14416 else
da0e507f
TS
14417 {
14418 as_fatal (_("invalid abi -mabi=%s"), arg);
14419 return 0;
14420 }
252b5132
RH
14421 break;
14422
6b76fefe 14423 case OPTION_M7000_HILO_FIX:
b34976b6 14424 mips_7000_hilo_fix = TRUE;
6b76fefe
CM
14425 break;
14426
9ee72ff1 14427 case OPTION_MNO_7000_HILO_FIX:
b34976b6 14428 mips_7000_hilo_fix = FALSE;
6b76fefe
CM
14429 break;
14430
ecb4347a 14431 case OPTION_MDEBUG:
b34976b6 14432 mips_flag_mdebug = TRUE;
ecb4347a
DJ
14433 break;
14434
14435 case OPTION_NO_MDEBUG:
b34976b6 14436 mips_flag_mdebug = FALSE;
ecb4347a 14437 break;
dcd410fe
RO
14438
14439 case OPTION_PDR:
14440 mips_flag_pdr = TRUE;
14441 break;
14442
14443 case OPTION_NO_PDR:
14444 mips_flag_pdr = FALSE;
14445 break;
0a44bf69
RS
14446
14447 case OPTION_MVXWORKS_PIC:
14448 mips_pic = VXWORKS_PIC;
14449 break;
ecb4347a 14450
ba92f887
MR
14451 case OPTION_NAN:
14452 if (strcmp (arg, "2008") == 0)
7361da2c 14453 mips_nan2008 = 1;
ba92f887 14454 else if (strcmp (arg, "legacy") == 0)
7361da2c 14455 mips_nan2008 = 0;
ba92f887
MR
14456 else
14457 {
1661c76c 14458 as_fatal (_("invalid NaN setting -mnan=%s"), arg);
ba92f887
MR
14459 return 0;
14460 }
14461 break;
14462
252b5132
RH
14463 default:
14464 return 0;
14465 }
14466
c67a084a
NC
14467 mips_fix_loongson2f = mips_fix_loongson2f_nop || mips_fix_loongson2f_jump;
14468
252b5132
RH
14469 return 1;
14470}
316f5878 14471\f
919731af 14472/* Set up globals to tune for the ISA or processor described by INFO. */
252b5132 14473
316f5878 14474static void
17a2f251 14475mips_set_tune (const struct mips_cpu_info *info)
316f5878
RS
14476{
14477 if (info != 0)
fef14a42 14478 mips_tune = info->cpu;
316f5878 14479}
80cc45a5 14480
34ba82a8 14481
252b5132 14482void
17a2f251 14483mips_after_parse_args (void)
e9670677 14484{
fef14a42
TS
14485 const struct mips_cpu_info *arch_info = 0;
14486 const struct mips_cpu_info *tune_info = 0;
14487
e9670677 14488 /* GP relative stuff not working for PE */
6caf9ef4 14489 if (strncmp (TARGET_OS, "pe", 2) == 0)
e9670677 14490 {
6caf9ef4 14491 if (g_switch_seen && g_switch_value != 0)
1661c76c 14492 as_bad (_("-G not supported in this configuration"));
e9670677
MR
14493 g_switch_value = 0;
14494 }
14495
cac012d6
AO
14496 if (mips_abi == NO_ABI)
14497 mips_abi = MIPS_DEFAULT_ABI;
14498
919731af 14499 /* The following code determines the architecture.
22923709
RS
14500 Similar code was added to GCC 3.3 (see override_options() in
14501 config/mips/mips.c). The GAS and GCC code should be kept in sync
14502 as much as possible. */
e9670677 14503
316f5878 14504 if (mips_arch_string != 0)
fef14a42 14505 arch_info = mips_parse_cpu ("-march", mips_arch_string);
e9670677 14506
0b35dfee 14507 if (file_mips_opts.isa != ISA_UNKNOWN)
e9670677 14508 {
0b35dfee 14509 /* Handle -mipsN. At this point, file_mips_opts.isa contains the
fef14a42 14510 ISA level specified by -mipsN, while arch_info->isa contains
316f5878 14511 the -march selection (if any). */
fef14a42 14512 if (arch_info != 0)
e9670677 14513 {
316f5878
RS
14514 /* -march takes precedence over -mipsN, since it is more descriptive.
14515 There's no harm in specifying both as long as the ISA levels
14516 are the same. */
0b35dfee 14517 if (file_mips_opts.isa != arch_info->isa)
1661c76c
RS
14518 as_bad (_("-%s conflicts with the other architecture options,"
14519 " which imply -%s"),
0b35dfee 14520 mips_cpu_info_from_isa (file_mips_opts.isa)->name,
fef14a42 14521 mips_cpu_info_from_isa (arch_info->isa)->name);
e9670677 14522 }
316f5878 14523 else
0b35dfee 14524 arch_info = mips_cpu_info_from_isa (file_mips_opts.isa);
e9670677
MR
14525 }
14526
fef14a42 14527 if (arch_info == 0)
95bfe26e
MF
14528 {
14529 arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT);
14530 gas_assert (arch_info);
14531 }
e9670677 14532
fef14a42 14533 if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa))
20203fb9 14534 as_bad (_("-march=%s is not compatible with the selected ABI"),
fef14a42
TS
14535 arch_info->name);
14536
919731af 14537 file_mips_opts.arch = arch_info->cpu;
14538 file_mips_opts.isa = arch_info->isa;
14539
14540 /* Set up initial mips_opts state. */
14541 mips_opts = file_mips_opts;
14542
14543 /* The register size inference code is now placed in
14544 file_mips_check_options. */
fef14a42 14545
0b35dfee 14546 /* Optimize for file_mips_opts.arch, unless -mtune selects a different
14547 processor. */
fef14a42
TS
14548 if (mips_tune_string != 0)
14549 tune_info = mips_parse_cpu ("-mtune", mips_tune_string);
e9670677 14550
fef14a42
TS
14551 if (tune_info == 0)
14552 mips_set_tune (arch_info);
14553 else
14554 mips_set_tune (tune_info);
e9670677 14555
ecb4347a 14556 if (mips_flag_mdebug < 0)
e8044f35 14557 mips_flag_mdebug = 0;
e9670677
MR
14558}
14559\f
14560void
17a2f251 14561mips_init_after_args (void)
252b5132
RH
14562{
14563 /* initialize opcodes */
14564 bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes;
beae10d5 14565 mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes;
252b5132
RH
14566}
14567
14568long
17a2f251 14569md_pcrel_from (fixS *fixP)
252b5132 14570{
a7ebbfdf
TS
14571 valueT addr = fixP->fx_where + fixP->fx_frag->fr_address;
14572 switch (fixP->fx_r_type)
14573 {
df58fc94
RS
14574 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
14575 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
14576 /* Return the address of the delay slot. */
14577 return addr + 2;
14578
14579 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
14580 case BFD_RELOC_MICROMIPS_JMP:
a7ebbfdf 14581 case BFD_RELOC_16_PCREL_S2:
7361da2c
AB
14582 case BFD_RELOC_MIPS_21_PCREL_S2:
14583 case BFD_RELOC_MIPS_26_PCREL_S2:
a7ebbfdf
TS
14584 case BFD_RELOC_MIPS_JMP:
14585 /* Return the address of the delay slot. */
14586 return addr + 4;
df58fc94 14587
a7ebbfdf
TS
14588 default:
14589 return addr;
14590 }
252b5132
RH
14591}
14592
252b5132
RH
14593/* This is called before the symbol table is processed. In order to
14594 work with gcc when using mips-tfile, we must keep all local labels.
14595 However, in other cases, we want to discard them. If we were
14596 called with -g, but we didn't see any debugging information, it may
14597 mean that gcc is smuggling debugging information through to
14598 mips-tfile, in which case we must generate all local labels. */
14599
14600void
17a2f251 14601mips_frob_file_before_adjust (void)
252b5132
RH
14602{
14603#ifndef NO_ECOFF_DEBUGGING
14604 if (ECOFF_DEBUGGING
14605 && mips_debug != 0
14606 && ! ecoff_debugging_seen)
14607 flag_keep_locals = 1;
14608#endif
14609}
14610
3b91255e 14611/* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
55cf6793 14612 the corresponding LO16 reloc. This is called before md_apply_fix and
3b91255e
RS
14613 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
14614 relocation operators.
14615
14616 For our purposes, a %lo() expression matches a %got() or %hi()
14617 expression if:
14618
14619 (a) it refers to the same symbol; and
14620 (b) the offset applied in the %lo() expression is no lower than
14621 the offset applied in the %got() or %hi().
14622
14623 (b) allows us to cope with code like:
14624
14625 lui $4,%hi(foo)
14626 lh $4,%lo(foo+2)($4)
14627
14628 ...which is legal on RELA targets, and has a well-defined behaviour
14629 if the user knows that adding 2 to "foo" will not induce a carry to
14630 the high 16 bits.
14631
14632 When several %lo()s match a particular %got() or %hi(), we use the
14633 following rules to distinguish them:
14634
14635 (1) %lo()s with smaller offsets are a better match than %lo()s with
14636 higher offsets.
14637
14638 (2) %lo()s with no matching %got() or %hi() are better than those
14639 that already have a matching %got() or %hi().
14640
14641 (3) later %lo()s are better than earlier %lo()s.
14642
14643 These rules are applied in order.
14644
14645 (1) means, among other things, that %lo()s with identical offsets are
14646 chosen if they exist.
14647
14648 (2) means that we won't associate several high-part relocations with
14649 the same low-part relocation unless there's no alternative. Having
14650 several high parts for the same low part is a GNU extension; this rule
14651 allows careful users to avoid it.
14652
14653 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
14654 with the last high-part relocation being at the front of the list.
14655 It therefore makes sense to choose the last matching low-part
14656 relocation, all other things being equal. It's also easier
14657 to code that way. */
252b5132
RH
14658
14659void
17a2f251 14660mips_frob_file (void)
252b5132
RH
14661{
14662 struct mips_hi_fixup *l;
35903be0 14663 bfd_reloc_code_real_type looking_for_rtype = BFD_RELOC_UNUSED;
252b5132
RH
14664
14665 for (l = mips_hi_fixup_list; l != NULL; l = l->next)
14666 {
14667 segment_info_type *seginfo;
3b91255e
RS
14668 bfd_boolean matched_lo_p;
14669 fixS **hi_pos, **lo_pos, **pos;
252b5132 14670
9c2799c2 14671 gas_assert (reloc_needs_lo_p (l->fixp->fx_r_type));
252b5132 14672
5919d012 14673 /* If a GOT16 relocation turns out to be against a global symbol,
b886a2ab
RS
14674 there isn't supposed to be a matching LO. Ignore %gots against
14675 constants; we'll report an error for those later. */
738e5348 14676 if (got16_reloc_p (l->fixp->fx_r_type)
b886a2ab
RS
14677 && !(l->fixp->fx_addsy
14678 && pic_need_relax (l->fixp->fx_addsy, l->seg)))
5919d012
RS
14679 continue;
14680
14681 /* Check quickly whether the next fixup happens to be a matching %lo. */
14682 if (fixup_has_matching_lo_p (l->fixp))
252b5132
RH
14683 continue;
14684
252b5132 14685 seginfo = seg_info (l->seg);
252b5132 14686
3b91255e
RS
14687 /* Set HI_POS to the position of this relocation in the chain.
14688 Set LO_POS to the position of the chosen low-part relocation.
14689 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
14690 relocation that matches an immediately-preceding high-part
14691 relocation. */
14692 hi_pos = NULL;
14693 lo_pos = NULL;
14694 matched_lo_p = FALSE;
738e5348 14695 looking_for_rtype = matching_lo_reloc (l->fixp->fx_r_type);
35903be0 14696
3b91255e
RS
14697 for (pos = &seginfo->fix_root; *pos != NULL; pos = &(*pos)->fx_next)
14698 {
14699 if (*pos == l->fixp)
14700 hi_pos = pos;
14701
35903be0 14702 if ((*pos)->fx_r_type == looking_for_rtype
30cfc97a 14703 && symbol_same_p ((*pos)->fx_addsy, l->fixp->fx_addsy)
3b91255e
RS
14704 && (*pos)->fx_offset >= l->fixp->fx_offset
14705 && (lo_pos == NULL
14706 || (*pos)->fx_offset < (*lo_pos)->fx_offset
14707 || (!matched_lo_p
14708 && (*pos)->fx_offset == (*lo_pos)->fx_offset)))
14709 lo_pos = pos;
14710
14711 matched_lo_p = (reloc_needs_lo_p ((*pos)->fx_r_type)
14712 && fixup_has_matching_lo_p (*pos));
14713 }
14714
14715 /* If we found a match, remove the high-part relocation from its
14716 current position and insert it before the low-part relocation.
14717 Make the offsets match so that fixup_has_matching_lo_p()
14718 will return true.
14719
14720 We don't warn about unmatched high-part relocations since some
14721 versions of gcc have been known to emit dead "lui ...%hi(...)"
14722 instructions. */
14723 if (lo_pos != NULL)
14724 {
14725 l->fixp->fx_offset = (*lo_pos)->fx_offset;
14726 if (l->fixp->fx_next != *lo_pos)
252b5132 14727 {
3b91255e
RS
14728 *hi_pos = l->fixp->fx_next;
14729 l->fixp->fx_next = *lo_pos;
14730 *lo_pos = l->fixp;
252b5132 14731 }
252b5132
RH
14732 }
14733 }
14734}
14735
252b5132 14736int
17a2f251 14737mips_force_relocation (fixS *fixp)
252b5132 14738{
ae6063d4 14739 if (generic_force_reloc (fixp))
252b5132
RH
14740 return 1;
14741
df58fc94
RS
14742 /* We want to keep BFD_RELOC_MICROMIPS_*_PCREL_S1 relocation,
14743 so that the linker relaxation can update targets. */
14744 if (fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1
14745 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1
14746 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1)
14747 return 1;
14748
7361da2c
AB
14749 /* We want all PC-relative relocations to be kept for R6 relaxation. */
14750 if (ISA_IS_R6 (mips_opts.isa)
14751 && (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2
14752 || fixp->fx_r_type == BFD_RELOC_MIPS_21_PCREL_S2
14753 || fixp->fx_r_type == BFD_RELOC_MIPS_26_PCREL_S2
14754 || fixp->fx_r_type == BFD_RELOC_MIPS_18_PCREL_S3
14755 || fixp->fx_r_type == BFD_RELOC_MIPS_19_PCREL_S2
14756 || fixp->fx_r_type == BFD_RELOC_HI16_S_PCREL
14757 || fixp->fx_r_type == BFD_RELOC_LO16_PCREL))
14758 return 1;
14759
3e722fb5 14760 return 0;
252b5132
RH
14761}
14762
b886a2ab
RS
14763/* Read the instruction associated with RELOC from BUF. */
14764
14765static unsigned int
14766read_reloc_insn (char *buf, bfd_reloc_code_real_type reloc)
14767{
14768 if (mips16_reloc_p (reloc) || micromips_reloc_p (reloc))
14769 return read_compressed_insn (buf, 4);
14770 else
14771 return read_insn (buf);
14772}
14773
14774/* Write instruction INSN to BUF, given that it has been relocated
14775 by RELOC. */
14776
14777static void
14778write_reloc_insn (char *buf, bfd_reloc_code_real_type reloc,
14779 unsigned long insn)
14780{
14781 if (mips16_reloc_p (reloc) || micromips_reloc_p (reloc))
14782 write_compressed_insn (buf, insn, 4);
14783 else
14784 write_insn (buf, insn);
14785}
14786
252b5132
RH
14787/* Apply a fixup to the object file. */
14788
94f592af 14789void
55cf6793 14790md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
252b5132 14791{
4d68580a 14792 char *buf;
b886a2ab 14793 unsigned long insn;
a7ebbfdf 14794 reloc_howto_type *howto;
252b5132 14795
d56a8dda
RS
14796 if (fixP->fx_pcrel)
14797 switch (fixP->fx_r_type)
14798 {
14799 case BFD_RELOC_16_PCREL_S2:
14800 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
14801 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
14802 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
14803 case BFD_RELOC_32_PCREL:
7361da2c
AB
14804 case BFD_RELOC_MIPS_21_PCREL_S2:
14805 case BFD_RELOC_MIPS_26_PCREL_S2:
14806 case BFD_RELOC_MIPS_18_PCREL_S3:
14807 case BFD_RELOC_MIPS_19_PCREL_S2:
14808 case BFD_RELOC_HI16_S_PCREL:
14809 case BFD_RELOC_LO16_PCREL:
d56a8dda
RS
14810 break;
14811
14812 case BFD_RELOC_32:
14813 fixP->fx_r_type = BFD_RELOC_32_PCREL;
14814 break;
14815
14816 default:
14817 as_bad_where (fixP->fx_file, fixP->fx_line,
14818 _("PC-relative reference to a different section"));
14819 break;
14820 }
14821
14822 /* Handle BFD_RELOC_8, since it's easy. Punt on other bfd relocations
14823 that have no MIPS ELF equivalent. */
14824 if (fixP->fx_r_type != BFD_RELOC_8)
14825 {
14826 howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type);
14827 if (!howto)
14828 return;
14829 }
65551fa4 14830
df58fc94
RS
14831 gas_assert (fixP->fx_size == 2
14832 || fixP->fx_size == 4
d56a8dda 14833 || fixP->fx_r_type == BFD_RELOC_8
90ecf173
MR
14834 || fixP->fx_r_type == BFD_RELOC_16
14835 || fixP->fx_r_type == BFD_RELOC_64
14836 || fixP->fx_r_type == BFD_RELOC_CTOR
14837 || fixP->fx_r_type == BFD_RELOC_MIPS_SUB
df58fc94 14838 || fixP->fx_r_type == BFD_RELOC_MICROMIPS_SUB
90ecf173
MR
14839 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
14840 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY
14841 || fixP->fx_r_type == BFD_RELOC_MIPS_TLS_DTPREL64);
252b5132 14842
4d68580a 14843 buf = fixP->fx_frag->fr_literal + fixP->fx_where;
252b5132 14844
b1dca8ee
RS
14845 /* Don't treat parts of a composite relocation as done. There are two
14846 reasons for this:
14847
14848 (1) The second and third parts will be against 0 (RSS_UNDEF) but
14849 should nevertheless be emitted if the first part is.
14850
14851 (2) In normal usage, composite relocations are never assembly-time
14852 constants. The easiest way of dealing with the pathological
14853 exceptions is to generate a relocation against STN_UNDEF and
14854 leave everything up to the linker. */
3994f87e 14855 if (fixP->fx_addsy == NULL && !fixP->fx_pcrel && fixP->fx_tcbit == 0)
252b5132
RH
14856 fixP->fx_done = 1;
14857
14858 switch (fixP->fx_r_type)
14859 {
3f98094e
DJ
14860 case BFD_RELOC_MIPS_TLS_GD:
14861 case BFD_RELOC_MIPS_TLS_LDM:
741d6ea8
JM
14862 case BFD_RELOC_MIPS_TLS_DTPREL32:
14863 case BFD_RELOC_MIPS_TLS_DTPREL64:
3f98094e
DJ
14864 case BFD_RELOC_MIPS_TLS_DTPREL_HI16:
14865 case BFD_RELOC_MIPS_TLS_DTPREL_LO16:
14866 case BFD_RELOC_MIPS_TLS_GOTTPREL:
d0f13682
CLT
14867 case BFD_RELOC_MIPS_TLS_TPREL32:
14868 case BFD_RELOC_MIPS_TLS_TPREL64:
3f98094e
DJ
14869 case BFD_RELOC_MIPS_TLS_TPREL_HI16:
14870 case BFD_RELOC_MIPS_TLS_TPREL_LO16:
df58fc94
RS
14871 case BFD_RELOC_MICROMIPS_TLS_GD:
14872 case BFD_RELOC_MICROMIPS_TLS_LDM:
14873 case BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16:
14874 case BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16:
14875 case BFD_RELOC_MICROMIPS_TLS_GOTTPREL:
14876 case BFD_RELOC_MICROMIPS_TLS_TPREL_HI16:
14877 case BFD_RELOC_MICROMIPS_TLS_TPREL_LO16:
d0f13682
CLT
14878 case BFD_RELOC_MIPS16_TLS_GD:
14879 case BFD_RELOC_MIPS16_TLS_LDM:
14880 case BFD_RELOC_MIPS16_TLS_DTPREL_HI16:
14881 case BFD_RELOC_MIPS16_TLS_DTPREL_LO16:
14882 case BFD_RELOC_MIPS16_TLS_GOTTPREL:
14883 case BFD_RELOC_MIPS16_TLS_TPREL_HI16:
14884 case BFD_RELOC_MIPS16_TLS_TPREL_LO16:
b886a2ab
RS
14885 if (!fixP->fx_addsy)
14886 {
14887 as_bad_where (fixP->fx_file, fixP->fx_line,
14888 _("TLS relocation against a constant"));
14889 break;
14890 }
3f98094e
DJ
14891 S_SET_THREAD_LOCAL (fixP->fx_addsy);
14892 /* fall through */
14893
252b5132 14894 case BFD_RELOC_MIPS_JMP:
e369bcce
TS
14895 case BFD_RELOC_MIPS_SHIFT5:
14896 case BFD_RELOC_MIPS_SHIFT6:
14897 case BFD_RELOC_MIPS_GOT_DISP:
14898 case BFD_RELOC_MIPS_GOT_PAGE:
14899 case BFD_RELOC_MIPS_GOT_OFST:
14900 case BFD_RELOC_MIPS_SUB:
14901 case BFD_RELOC_MIPS_INSERT_A:
14902 case BFD_RELOC_MIPS_INSERT_B:
14903 case BFD_RELOC_MIPS_DELETE:
14904 case BFD_RELOC_MIPS_HIGHEST:
14905 case BFD_RELOC_MIPS_HIGHER:
14906 case BFD_RELOC_MIPS_SCN_DISP:
14907 case BFD_RELOC_MIPS_REL16:
14908 case BFD_RELOC_MIPS_RELGOT:
14909 case BFD_RELOC_MIPS_JALR:
252b5132
RH
14910 case BFD_RELOC_HI16:
14911 case BFD_RELOC_HI16_S:
b886a2ab 14912 case BFD_RELOC_LO16:
cdf6fd85 14913 case BFD_RELOC_GPREL16:
252b5132
RH
14914 case BFD_RELOC_MIPS_LITERAL:
14915 case BFD_RELOC_MIPS_CALL16:
14916 case BFD_RELOC_MIPS_GOT16:
cdf6fd85 14917 case BFD_RELOC_GPREL32:
252b5132
RH
14918 case BFD_RELOC_MIPS_GOT_HI16:
14919 case BFD_RELOC_MIPS_GOT_LO16:
14920 case BFD_RELOC_MIPS_CALL_HI16:
14921 case BFD_RELOC_MIPS_CALL_LO16:
14922 case BFD_RELOC_MIPS16_GPREL:
738e5348
RS
14923 case BFD_RELOC_MIPS16_GOT16:
14924 case BFD_RELOC_MIPS16_CALL16:
d6f16593
MR
14925 case BFD_RELOC_MIPS16_HI16:
14926 case BFD_RELOC_MIPS16_HI16_S:
b886a2ab 14927 case BFD_RELOC_MIPS16_LO16:
252b5132 14928 case BFD_RELOC_MIPS16_JMP:
df58fc94
RS
14929 case BFD_RELOC_MICROMIPS_JMP:
14930 case BFD_RELOC_MICROMIPS_GOT_DISP:
14931 case BFD_RELOC_MICROMIPS_GOT_PAGE:
14932 case BFD_RELOC_MICROMIPS_GOT_OFST:
14933 case BFD_RELOC_MICROMIPS_SUB:
14934 case BFD_RELOC_MICROMIPS_HIGHEST:
14935 case BFD_RELOC_MICROMIPS_HIGHER:
14936 case BFD_RELOC_MICROMIPS_SCN_DISP:
14937 case BFD_RELOC_MICROMIPS_JALR:
14938 case BFD_RELOC_MICROMIPS_HI16:
14939 case BFD_RELOC_MICROMIPS_HI16_S:
b886a2ab 14940 case BFD_RELOC_MICROMIPS_LO16:
df58fc94
RS
14941 case BFD_RELOC_MICROMIPS_GPREL16:
14942 case BFD_RELOC_MICROMIPS_LITERAL:
14943 case BFD_RELOC_MICROMIPS_CALL16:
14944 case BFD_RELOC_MICROMIPS_GOT16:
14945 case BFD_RELOC_MICROMIPS_GOT_HI16:
14946 case BFD_RELOC_MICROMIPS_GOT_LO16:
14947 case BFD_RELOC_MICROMIPS_CALL_HI16:
14948 case BFD_RELOC_MICROMIPS_CALL_LO16:
067ec077 14949 case BFD_RELOC_MIPS_EH:
b886a2ab
RS
14950 if (fixP->fx_done)
14951 {
14952 offsetT value;
14953
14954 if (calculate_reloc (fixP->fx_r_type, *valP, &value))
14955 {
14956 insn = read_reloc_insn (buf, fixP->fx_r_type);
14957 if (mips16_reloc_p (fixP->fx_r_type))
14958 insn |= mips16_immed_extend (value, 16);
14959 else
14960 insn |= (value & 0xffff);
14961 write_reloc_insn (buf, fixP->fx_r_type, insn);
14962 }
14963 else
14964 as_bad_where (fixP->fx_file, fixP->fx_line,
1661c76c 14965 _("unsupported constant in relocation"));
b886a2ab 14966 }
252b5132
RH
14967 break;
14968
252b5132
RH
14969 case BFD_RELOC_64:
14970 /* This is handled like BFD_RELOC_32, but we output a sign
14971 extended value if we are only 32 bits. */
3e722fb5 14972 if (fixP->fx_done)
252b5132
RH
14973 {
14974 if (8 <= sizeof (valueT))
4d68580a 14975 md_number_to_chars (buf, *valP, 8);
252b5132
RH
14976 else
14977 {
a7ebbfdf 14978 valueT hiv;
252b5132 14979
a7ebbfdf 14980 if ((*valP & 0x80000000) != 0)
252b5132
RH
14981 hiv = 0xffffffff;
14982 else
14983 hiv = 0;
4d68580a
RS
14984 md_number_to_chars (buf + (target_big_endian ? 4 : 0), *valP, 4);
14985 md_number_to_chars (buf + (target_big_endian ? 0 : 4), hiv, 4);
252b5132
RH
14986 }
14987 }
14988 break;
14989
056350c6 14990 case BFD_RELOC_RVA:
252b5132 14991 case BFD_RELOC_32:
b47468a6 14992 case BFD_RELOC_32_PCREL:
252b5132 14993 case BFD_RELOC_16:
d56a8dda 14994 case BFD_RELOC_8:
252b5132 14995 /* If we are deleting this reloc entry, we must fill in the
54f4ddb3
TS
14996 value now. This can happen if we have a .word which is not
14997 resolved when it appears but is later defined. */
252b5132 14998 if (fixP->fx_done)
4d68580a 14999 md_number_to_chars (buf, *valP, fixP->fx_size);
252b5132
RH
15000 break;
15001
7361da2c
AB
15002 case BFD_RELOC_MIPS_21_PCREL_S2:
15003 case BFD_RELOC_MIPS_26_PCREL_S2:
15004 if ((*valP & 0x3) != 0)
15005 as_bad_where (fixP->fx_file, fixP->fx_line,
15006 _("branch to misaligned address (%lx)"), (long) *valP);
15007
15008 gas_assert (!fixP->fx_done);
15009 break;
15010
15011 case BFD_RELOC_MIPS_18_PCREL_S3:
0866e94c 15012 if ((S_GET_VALUE (fixP->fx_addsy) & 0x7) != 0)
7361da2c 15013 as_bad_where (fixP->fx_file, fixP->fx_line,
0866e94c
MF
15014 _("PC-relative access using misaligned symbol (%lx)"),
15015 (long) S_GET_VALUE (fixP->fx_addsy));
15016 if ((fixP->fx_offset & 0x7) != 0)
15017 as_bad_where (fixP->fx_file, fixP->fx_line,
15018 _("PC-relative access using misaligned offset (%lx)"),
15019 (long) fixP->fx_offset);
7361da2c
AB
15020
15021 gas_assert (!fixP->fx_done);
15022 break;
15023
15024 case BFD_RELOC_MIPS_19_PCREL_S2:
15025 if ((*valP & 0x3) != 0)
15026 as_bad_where (fixP->fx_file, fixP->fx_line,
15027 _("PC-relative access to misaligned address (%lx)"),
0866e94c 15028 (long) (S_GET_VALUE (fixP->fx_addsy) + fixP->fx_offset));
7361da2c
AB
15029
15030 gas_assert (!fixP->fx_done);
15031 break;
15032
15033 case BFD_RELOC_HI16_S_PCREL:
15034 case BFD_RELOC_LO16_PCREL:
15035 gas_assert (!fixP->fx_done);
15036 break;
15037
252b5132 15038 case BFD_RELOC_16_PCREL_S2:
a7ebbfdf 15039 if ((*valP & 0x3) != 0)
cb56d3d3 15040 as_bad_where (fixP->fx_file, fixP->fx_line,
1661c76c 15041 _("branch to misaligned address (%lx)"), (long) *valP);
cb56d3d3 15042
54f4ddb3
TS
15043 /* We need to save the bits in the instruction since fixup_segment()
15044 might be deleting the relocation entry (i.e., a branch within
15045 the current segment). */
a7ebbfdf 15046 if (! fixP->fx_done)
bb2d6cd7 15047 break;
252b5132 15048
54f4ddb3 15049 /* Update old instruction data. */
4d68580a 15050 insn = read_insn (buf);
252b5132 15051
a7ebbfdf
TS
15052 if (*valP + 0x20000 <= 0x3ffff)
15053 {
15054 insn |= (*valP >> 2) & 0xffff;
4d68580a 15055 write_insn (buf, insn);
a7ebbfdf
TS
15056 }
15057 else if (mips_pic == NO_PIC
15058 && fixP->fx_done
15059 && fixP->fx_frag->fr_address >= text_section->vma
15060 && (fixP->fx_frag->fr_address
587aac4e 15061 < text_section->vma + bfd_get_section_size (text_section))
a7ebbfdf
TS
15062 && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */
15063 || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */
15064 || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */
252b5132
RH
15065 {
15066 /* The branch offset is too large. If this is an
15067 unconditional branch, and we are not generating PIC code,
15068 we can convert it to an absolute jump instruction. */
a7ebbfdf
TS
15069 if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */
15070 insn = 0x0c000000; /* jal */
252b5132 15071 else
a7ebbfdf
TS
15072 insn = 0x08000000; /* j */
15073 fixP->fx_r_type = BFD_RELOC_MIPS_JMP;
15074 fixP->fx_done = 0;
15075 fixP->fx_addsy = section_symbol (text_section);
15076 *valP += md_pcrel_from (fixP);
4d68580a 15077 write_insn (buf, insn);
a7ebbfdf
TS
15078 }
15079 else
15080 {
15081 /* If we got here, we have branch-relaxation disabled,
15082 and there's nothing we can do to fix this instruction
15083 without turning it into a longer sequence. */
15084 as_bad_where (fixP->fx_file, fixP->fx_line,
1661c76c 15085 _("branch out of range"));
252b5132 15086 }
252b5132
RH
15087 break;
15088
df58fc94
RS
15089 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
15090 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
15091 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
15092 /* We adjust the offset back to even. */
15093 if ((*valP & 0x1) != 0)
15094 --(*valP);
15095
15096 if (! fixP->fx_done)
15097 break;
15098
15099 /* Should never visit here, because we keep the relocation. */
15100 abort ();
15101 break;
15102
252b5132
RH
15103 case BFD_RELOC_VTABLE_INHERIT:
15104 fixP->fx_done = 0;
15105 if (fixP->fx_addsy
15106 && !S_IS_DEFINED (fixP->fx_addsy)
15107 && !S_IS_WEAK (fixP->fx_addsy))
15108 S_SET_WEAK (fixP->fx_addsy);
15109 break;
15110
15111 case BFD_RELOC_VTABLE_ENTRY:
15112 fixP->fx_done = 0;
15113 break;
15114
15115 default:
b37df7c4 15116 abort ();
252b5132 15117 }
a7ebbfdf
TS
15118
15119 /* Remember value for tc_gen_reloc. */
15120 fixP->fx_addnumber = *valP;
252b5132
RH
15121}
15122
252b5132 15123static symbolS *
17a2f251 15124get_symbol (void)
252b5132
RH
15125{
15126 int c;
15127 char *name;
15128 symbolS *p;
15129
15130 name = input_line_pointer;
15131 c = get_symbol_end ();
15132 p = (symbolS *) symbol_find_or_make (name);
15133 *input_line_pointer = c;
15134 return p;
15135}
15136
742a56fe
RS
15137/* Align the current frag to a given power of two. If a particular
15138 fill byte should be used, FILL points to an integer that contains
15139 that byte, otherwise FILL is null.
15140
462427c4
RS
15141 This function used to have the comment:
15142
15143 The MIPS assembler also automatically adjusts any preceding label.
15144
15145 The implementation therefore applied the adjustment to a maximum of
15146 one label. However, other label adjustments are applied to batches
15147 of labels, and adjusting just one caused problems when new labels
15148 were added for the sake of debugging or unwind information.
15149 We therefore adjust all preceding labels (given as LABELS) instead. */
252b5132
RH
15150
15151static void
462427c4 15152mips_align (int to, int *fill, struct insn_label_list *labels)
252b5132 15153{
7d10b47d 15154 mips_emit_delays ();
df58fc94 15155 mips_record_compressed_mode ();
742a56fe
RS
15156 if (fill == NULL && subseg_text_p (now_seg))
15157 frag_align_code (to, 0);
15158 else
15159 frag_align (to, fill ? *fill : 0, 0);
252b5132 15160 record_alignment (now_seg, to);
462427c4 15161 mips_move_labels (labels, FALSE);
252b5132
RH
15162}
15163
15164/* Align to a given power of two. .align 0 turns off the automatic
15165 alignment used by the data creating pseudo-ops. */
15166
15167static void
17a2f251 15168s_align (int x ATTRIBUTE_UNUSED)
252b5132 15169{
742a56fe 15170 int temp, fill_value, *fill_ptr;
49954fb4 15171 long max_alignment = 28;
252b5132 15172
54f4ddb3 15173 /* o Note that the assembler pulls down any immediately preceding label
252b5132 15174 to the aligned address.
54f4ddb3 15175 o It's not documented but auto alignment is reinstated by
252b5132 15176 a .align pseudo instruction.
54f4ddb3 15177 o Note also that after auto alignment is turned off the mips assembler
252b5132 15178 issues an error on attempt to assemble an improperly aligned data item.
54f4ddb3 15179 We don't. */
252b5132
RH
15180
15181 temp = get_absolute_expression ();
15182 if (temp > max_alignment)
1661c76c 15183 as_bad (_("alignment too large, %d assumed"), temp = max_alignment);
252b5132
RH
15184 else if (temp < 0)
15185 {
1661c76c 15186 as_warn (_("alignment negative, 0 assumed"));
252b5132
RH
15187 temp = 0;
15188 }
15189 if (*input_line_pointer == ',')
15190 {
f9419b05 15191 ++input_line_pointer;
742a56fe
RS
15192 fill_value = get_absolute_expression ();
15193 fill_ptr = &fill_value;
252b5132
RH
15194 }
15195 else
742a56fe 15196 fill_ptr = 0;
252b5132
RH
15197 if (temp)
15198 {
a8dbcb85
TS
15199 segment_info_type *si = seg_info (now_seg);
15200 struct insn_label_list *l = si->label_list;
54f4ddb3 15201 /* Auto alignment should be switched on by next section change. */
252b5132 15202 auto_align = 1;
462427c4 15203 mips_align (temp, fill_ptr, l);
252b5132
RH
15204 }
15205 else
15206 {
15207 auto_align = 0;
15208 }
15209
15210 demand_empty_rest_of_line ();
15211}
15212
252b5132 15213static void
17a2f251 15214s_change_sec (int sec)
252b5132
RH
15215{
15216 segT seg;
15217
252b5132
RH
15218 /* The ELF backend needs to know that we are changing sections, so
15219 that .previous works correctly. We could do something like check
b6ff326e 15220 for an obj_section_change_hook macro, but that might be confusing
252b5132
RH
15221 as it would not be appropriate to use it in the section changing
15222 functions in read.c, since obj-elf.c intercepts those. FIXME:
15223 This should be cleaner, somehow. */
f3ded42a 15224 obj_elf_section_change_hook ();
252b5132 15225
7d10b47d 15226 mips_emit_delays ();
6a32d874 15227
252b5132
RH
15228 switch (sec)
15229 {
15230 case 't':
15231 s_text (0);
15232 break;
15233 case 'd':
15234 s_data (0);
15235 break;
15236 case 'b':
15237 subseg_set (bss_section, (subsegT) get_absolute_expression ());
15238 demand_empty_rest_of_line ();
15239 break;
15240
15241 case 'r':
4d0d148d
TS
15242 seg = subseg_new (RDATA_SECTION_NAME,
15243 (subsegT) get_absolute_expression ());
f3ded42a
RS
15244 bfd_set_section_flags (stdoutput, seg, (SEC_ALLOC | SEC_LOAD
15245 | SEC_READONLY | SEC_RELOC
15246 | SEC_DATA));
15247 if (strncmp (TARGET_OS, "elf", 3) != 0)
15248 record_alignment (seg, 4);
4d0d148d 15249 demand_empty_rest_of_line ();
252b5132
RH
15250 break;
15251
15252 case 's':
4d0d148d 15253 seg = subseg_new (".sdata", (subsegT) get_absolute_expression ());
f3ded42a
RS
15254 bfd_set_section_flags (stdoutput, seg,
15255 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA);
15256 if (strncmp (TARGET_OS, "elf", 3) != 0)
15257 record_alignment (seg, 4);
4d0d148d
TS
15258 demand_empty_rest_of_line ();
15259 break;
998b3c36
MR
15260
15261 case 'B':
15262 seg = subseg_new (".sbss", (subsegT) get_absolute_expression ());
f3ded42a
RS
15263 bfd_set_section_flags (stdoutput, seg, SEC_ALLOC);
15264 if (strncmp (TARGET_OS, "elf", 3) != 0)
15265 record_alignment (seg, 4);
998b3c36
MR
15266 demand_empty_rest_of_line ();
15267 break;
252b5132
RH
15268 }
15269
15270 auto_align = 1;
15271}
b34976b6 15272
cca86cc8 15273void
17a2f251 15274s_change_section (int ignore ATTRIBUTE_UNUSED)
cca86cc8 15275{
cca86cc8
SC
15276 char *section_name;
15277 char c;
684022ea 15278 char next_c = 0;
cca86cc8
SC
15279 int section_type;
15280 int section_flag;
15281 int section_entry_size;
15282 int section_alignment;
b34976b6 15283
cca86cc8
SC
15284 section_name = input_line_pointer;
15285 c = get_symbol_end ();
a816d1ed
AO
15286 if (c)
15287 next_c = *(input_line_pointer + 1);
cca86cc8 15288
4cf0dd0d
TS
15289 /* Do we have .section Name<,"flags">? */
15290 if (c != ',' || (c == ',' && next_c == '"'))
cca86cc8 15291 {
4cf0dd0d
TS
15292 /* just after name is now '\0'. */
15293 *input_line_pointer = c;
cca86cc8
SC
15294 input_line_pointer = section_name;
15295 obj_elf_section (ignore);
15296 return;
15297 }
15298 input_line_pointer++;
15299
15300 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
15301 if (c == ',')
15302 section_type = get_absolute_expression ();
15303 else
15304 section_type = 0;
15305 if (*input_line_pointer++ == ',')
15306 section_flag = get_absolute_expression ();
15307 else
15308 section_flag = 0;
15309 if (*input_line_pointer++ == ',')
15310 section_entry_size = get_absolute_expression ();
15311 else
15312 section_entry_size = 0;
15313 if (*input_line_pointer++ == ',')
15314 section_alignment = get_absolute_expression ();
15315 else
15316 section_alignment = 0;
87975d2a
AM
15317 /* FIXME: really ignore? */
15318 (void) section_alignment;
cca86cc8 15319
a816d1ed
AO
15320 section_name = xstrdup (section_name);
15321
8ab8a5c8
RS
15322 /* When using the generic form of .section (as implemented by obj-elf.c),
15323 there's no way to set the section type to SHT_MIPS_DWARF. Users have
15324 traditionally had to fall back on the more common @progbits instead.
15325
15326 There's nothing really harmful in this, since bfd will correct
15327 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
708587a4 15328 means that, for backwards compatibility, the special_section entries
8ab8a5c8
RS
15329 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
15330
15331 Even so, we shouldn't force users of the MIPS .section syntax to
15332 incorrectly label the sections as SHT_PROGBITS. The best compromise
15333 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
15334 generic type-checking code. */
15335 if (section_type == SHT_MIPS_DWARF)
15336 section_type = SHT_PROGBITS;
15337
cca86cc8
SC
15338 obj_elf_change_section (section_name, section_type, section_flag,
15339 section_entry_size, 0, 0, 0);
a816d1ed
AO
15340
15341 if (now_seg->name != section_name)
15342 free (section_name);
cca86cc8 15343}
252b5132
RH
15344
15345void
17a2f251 15346mips_enable_auto_align (void)
252b5132
RH
15347{
15348 auto_align = 1;
15349}
15350
15351static void
17a2f251 15352s_cons (int log_size)
252b5132 15353{
a8dbcb85
TS
15354 segment_info_type *si = seg_info (now_seg);
15355 struct insn_label_list *l = si->label_list;
252b5132 15356
7d10b47d 15357 mips_emit_delays ();
252b5132 15358 if (log_size > 0 && auto_align)
462427c4 15359 mips_align (log_size, 0, l);
252b5132 15360 cons (1 << log_size);
a1facbec 15361 mips_clear_insn_labels ();
252b5132
RH
15362}
15363
15364static void
17a2f251 15365s_float_cons (int type)
252b5132 15366{
a8dbcb85
TS
15367 segment_info_type *si = seg_info (now_seg);
15368 struct insn_label_list *l = si->label_list;
252b5132 15369
7d10b47d 15370 mips_emit_delays ();
252b5132
RH
15371
15372 if (auto_align)
49309057
ILT
15373 {
15374 if (type == 'd')
462427c4 15375 mips_align (3, 0, l);
49309057 15376 else
462427c4 15377 mips_align (2, 0, l);
49309057 15378 }
252b5132 15379
252b5132 15380 float_cons (type);
a1facbec 15381 mips_clear_insn_labels ();
252b5132
RH
15382}
15383
15384/* Handle .globl. We need to override it because on Irix 5 you are
15385 permitted to say
15386 .globl foo .text
15387 where foo is an undefined symbol, to mean that foo should be
15388 considered to be the address of a function. */
15389
15390static void
17a2f251 15391s_mips_globl (int x ATTRIBUTE_UNUSED)
252b5132
RH
15392{
15393 char *name;
15394 int c;
15395 symbolS *symbolP;
15396 flagword flag;
15397
8a06b769 15398 do
252b5132 15399 {
8a06b769 15400 name = input_line_pointer;
252b5132 15401 c = get_symbol_end ();
8a06b769
TS
15402 symbolP = symbol_find_or_make (name);
15403 S_SET_EXTERNAL (symbolP);
15404
252b5132 15405 *input_line_pointer = c;
8a06b769 15406 SKIP_WHITESPACE ();
252b5132 15407
8a06b769
TS
15408 /* On Irix 5, every global symbol that is not explicitly labelled as
15409 being a function is apparently labelled as being an object. */
15410 flag = BSF_OBJECT;
252b5132 15411
8a06b769
TS
15412 if (!is_end_of_line[(unsigned char) *input_line_pointer]
15413 && (*input_line_pointer != ','))
15414 {
15415 char *secname;
15416 asection *sec;
15417
15418 secname = input_line_pointer;
15419 c = get_symbol_end ();
15420 sec = bfd_get_section_by_name (stdoutput, secname);
15421 if (sec == NULL)
15422 as_bad (_("%s: no such section"), secname);
15423 *input_line_pointer = c;
15424
15425 if (sec != NULL && (sec->flags & SEC_CODE) != 0)
15426 flag = BSF_FUNCTION;
15427 }
15428
15429 symbol_get_bfdsym (symbolP)->flags |= flag;
15430
15431 c = *input_line_pointer;
15432 if (c == ',')
15433 {
15434 input_line_pointer++;
15435 SKIP_WHITESPACE ();
15436 if (is_end_of_line[(unsigned char) *input_line_pointer])
15437 c = '\n';
15438 }
15439 }
15440 while (c == ',');
252b5132 15441
252b5132
RH
15442 demand_empty_rest_of_line ();
15443}
15444
15445static void
17a2f251 15446s_option (int x ATTRIBUTE_UNUSED)
252b5132
RH
15447{
15448 char *opt;
15449 char c;
15450
15451 opt = input_line_pointer;
15452 c = get_symbol_end ();
15453
15454 if (*opt == 'O')
15455 {
15456 /* FIXME: What does this mean? */
15457 }
15458 else if (strncmp (opt, "pic", 3) == 0)
15459 {
15460 int i;
15461
15462 i = atoi (opt + 3);
15463 if (i == 0)
15464 mips_pic = NO_PIC;
15465 else if (i == 2)
143d77c5 15466 {
8b828383 15467 mips_pic = SVR4_PIC;
143d77c5
EC
15468 mips_abicalls = TRUE;
15469 }
252b5132
RH
15470 else
15471 as_bad (_(".option pic%d not supported"), i);
15472
4d0d148d 15473 if (mips_pic == SVR4_PIC)
252b5132
RH
15474 {
15475 if (g_switch_seen && g_switch_value != 0)
15476 as_warn (_("-G may not be used with SVR4 PIC code"));
15477 g_switch_value = 0;
15478 bfd_set_gp_size (stdoutput, 0);
15479 }
15480 }
15481 else
1661c76c 15482 as_warn (_("unrecognized option \"%s\""), opt);
252b5132
RH
15483
15484 *input_line_pointer = c;
15485 demand_empty_rest_of_line ();
15486}
15487
15488/* This structure is used to hold a stack of .set values. */
15489
e972090a
NC
15490struct mips_option_stack
15491{
252b5132
RH
15492 struct mips_option_stack *next;
15493 struct mips_set_options options;
15494};
15495
15496static struct mips_option_stack *mips_opts_stack;
15497
919731af 15498static bfd_boolean
15499parse_code_option (char * name)
252b5132 15500{
c6278170 15501 const struct mips_ase *ase;
919731af 15502 if (strncmp (name, "at=", 3) == 0)
741fe287
MR
15503 {
15504 char *s = name + 3;
15505
15506 if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, &mips_opts.at))
1661c76c 15507 as_bad (_("unrecognized register name `%s'"), s);
741fe287 15508 }
252b5132 15509 else if (strcmp (name, "at") == 0)
919731af 15510 mips_opts.at = ATREG;
252b5132 15511 else if (strcmp (name, "noat") == 0)
919731af 15512 mips_opts.at = ZERO;
252b5132 15513 else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0)
919731af 15514 mips_opts.nomove = 0;
252b5132 15515 else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0)
919731af 15516 mips_opts.nomove = 1;
252b5132 15517 else if (strcmp (name, "bopt") == 0)
919731af 15518 mips_opts.nobopt = 0;
252b5132 15519 else if (strcmp (name, "nobopt") == 0)
919731af 15520 mips_opts.nobopt = 1;
ad3fea08 15521 else if (strcmp (name, "gp=32") == 0)
bad1aba3 15522 mips_opts.gp = 32;
ad3fea08 15523 else if (strcmp (name, "gp=64") == 0)
919731af 15524 mips_opts.gp = 64;
ad3fea08 15525 else if (strcmp (name, "fp=32") == 0)
0b35dfee 15526 mips_opts.fp = 32;
351cdf24
MF
15527 else if (strcmp (name, "fp=xx") == 0)
15528 mips_opts.fp = 0;
ad3fea08 15529 else if (strcmp (name, "fp=64") == 0)
919731af 15530 mips_opts.fp = 64;
037b32b9
AN
15531 else if (strcmp (name, "softfloat") == 0)
15532 mips_opts.soft_float = 1;
15533 else if (strcmp (name, "hardfloat") == 0)
15534 mips_opts.soft_float = 0;
15535 else if (strcmp (name, "singlefloat") == 0)
15536 mips_opts.single_float = 1;
15537 else if (strcmp (name, "doublefloat") == 0)
15538 mips_opts.single_float = 0;
351cdf24
MF
15539 else if (strcmp (name, "nooddspreg") == 0)
15540 mips_opts.oddspreg = 0;
15541 else if (strcmp (name, "oddspreg") == 0)
15542 mips_opts.oddspreg = 1;
252b5132
RH
15543 else if (strcmp (name, "mips16") == 0
15544 || strcmp (name, "MIPS-16") == 0)
919731af 15545 mips_opts.mips16 = 1;
252b5132
RH
15546 else if (strcmp (name, "nomips16") == 0
15547 || strcmp (name, "noMIPS-16") == 0)
15548 mips_opts.mips16 = 0;
df58fc94 15549 else if (strcmp (name, "micromips") == 0)
919731af 15550 mips_opts.micromips = 1;
df58fc94
RS
15551 else if (strcmp (name, "nomicromips") == 0)
15552 mips_opts.micromips = 0;
c6278170
RS
15553 else if (name[0] == 'n'
15554 && name[1] == 'o'
15555 && (ase = mips_lookup_ase (name + 2)))
919731af 15556 mips_set_ase (ase, &mips_opts, FALSE);
c6278170 15557 else if ((ase = mips_lookup_ase (name)))
919731af 15558 mips_set_ase (ase, &mips_opts, TRUE);
1a2c1fad 15559 else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0)
252b5132 15560 {
1a2c1fad
CD
15561 /* Permit the user to change the ISA and architecture on the fly.
15562 Needless to say, misuse can cause serious problems. */
919731af 15563 if (strncmp (name, "arch=", 5) == 0)
1a2c1fad
CD
15564 {
15565 const struct mips_cpu_info *p;
15566
919731af 15567 p = mips_parse_cpu ("internal use", name + 5);
1a2c1fad
CD
15568 if (!p)
15569 as_bad (_("unknown architecture %s"), name + 5);
15570 else
15571 {
15572 mips_opts.arch = p->cpu;
15573 mips_opts.isa = p->isa;
15574 }
15575 }
81a21e38
TS
15576 else if (strncmp (name, "mips", 4) == 0)
15577 {
15578 const struct mips_cpu_info *p;
15579
919731af 15580 p = mips_parse_cpu ("internal use", name);
81a21e38
TS
15581 if (!p)
15582 as_bad (_("unknown ISA level %s"), name + 4);
15583 else
15584 {
15585 mips_opts.arch = p->cpu;
15586 mips_opts.isa = p->isa;
15587 }
15588 }
af7ee8bf 15589 else
81a21e38 15590 as_bad (_("unknown ISA or architecture %s"), name);
252b5132
RH
15591 }
15592 else if (strcmp (name, "autoextend") == 0)
15593 mips_opts.noautoextend = 0;
15594 else if (strcmp (name, "noautoextend") == 0)
15595 mips_opts.noautoextend = 1;
833794fc
MR
15596 else if (strcmp (name, "insn32") == 0)
15597 mips_opts.insn32 = TRUE;
15598 else if (strcmp (name, "noinsn32") == 0)
15599 mips_opts.insn32 = FALSE;
919731af 15600 else if (strcmp (name, "sym32") == 0)
15601 mips_opts.sym32 = TRUE;
15602 else if (strcmp (name, "nosym32") == 0)
15603 mips_opts.sym32 = FALSE;
15604 else
15605 return FALSE;
15606 return TRUE;
15607}
15608
15609/* Handle the .set pseudo-op. */
15610
15611static void
15612s_mipsset (int x ATTRIBUTE_UNUSED)
15613{
15614 char *name = input_line_pointer, ch;
15615 int prev_isa = mips_opts.isa;
15616
15617 file_mips_check_options ();
15618
15619 while (!is_end_of_line[(unsigned char) *input_line_pointer])
15620 ++input_line_pointer;
15621 ch = *input_line_pointer;
15622 *input_line_pointer = '\0';
15623
15624 if (strchr (name, ','))
15625 {
15626 /* Generic ".set" directive; use the generic handler. */
15627 *input_line_pointer = ch;
15628 input_line_pointer = name;
15629 s_set (0);
15630 return;
15631 }
15632
15633 if (strcmp (name, "reorder") == 0)
15634 {
15635 if (mips_opts.noreorder)
15636 end_noreorder ();
15637 }
15638 else if (strcmp (name, "noreorder") == 0)
15639 {
15640 if (!mips_opts.noreorder)
15641 start_noreorder ();
15642 }
15643 else if (strcmp (name, "macro") == 0)
15644 mips_opts.warn_about_macros = 0;
15645 else if (strcmp (name, "nomacro") == 0)
15646 {
15647 if (mips_opts.noreorder == 0)
15648 as_bad (_("`noreorder' must be set before `nomacro'"));
15649 mips_opts.warn_about_macros = 1;
15650 }
15651 else if (strcmp (name, "gp=default") == 0)
15652 mips_opts.gp = file_mips_opts.gp;
15653 else if (strcmp (name, "fp=default") == 0)
15654 mips_opts.fp = file_mips_opts.fp;
15655 else if (strcmp (name, "mips0") == 0 || strcmp (name, "arch=default") == 0)
15656 {
15657 mips_opts.isa = file_mips_opts.isa;
15658 mips_opts.arch = file_mips_opts.arch;
15659 mips_opts.gp = file_mips_opts.gp;
15660 mips_opts.fp = file_mips_opts.fp;
15661 }
252b5132
RH
15662 else if (strcmp (name, "push") == 0)
15663 {
15664 struct mips_option_stack *s;
15665
15666 s = (struct mips_option_stack *) xmalloc (sizeof *s);
15667 s->next = mips_opts_stack;
15668 s->options = mips_opts;
15669 mips_opts_stack = s;
15670 }
15671 else if (strcmp (name, "pop") == 0)
15672 {
15673 struct mips_option_stack *s;
15674
15675 s = mips_opts_stack;
15676 if (s == NULL)
15677 as_bad (_(".set pop with no .set push"));
15678 else
15679 {
15680 /* If we're changing the reorder mode we need to handle
15681 delay slots correctly. */
15682 if (s->options.noreorder && ! mips_opts.noreorder)
7d10b47d 15683 start_noreorder ();
252b5132 15684 else if (! s->options.noreorder && mips_opts.noreorder)
7d10b47d 15685 end_noreorder ();
252b5132
RH
15686
15687 mips_opts = s->options;
15688 mips_opts_stack = s->next;
15689 free (s);
15690 }
15691 }
919731af 15692 else if (!parse_code_option (name))
15693 as_warn (_("tried to set unrecognized symbol: %s\n"), name);
15694
15695 /* The use of .set [arch|cpu]= historically 'fixes' the width of gp and fp
15696 registers based on what is supported by the arch/cpu. */
15697 if (mips_opts.isa != prev_isa)
e6559e01 15698 {
919731af 15699 switch (mips_opts.isa)
15700 {
15701 case 0:
15702 break;
15703 case ISA_MIPS1:
351cdf24
MF
15704 /* MIPS I cannot support FPXX. */
15705 mips_opts.fp = 32;
15706 /* fall-through. */
919731af 15707 case ISA_MIPS2:
15708 case ISA_MIPS32:
15709 case ISA_MIPS32R2:
15710 case ISA_MIPS32R3:
15711 case ISA_MIPS32R5:
15712 mips_opts.gp = 32;
351cdf24
MF
15713 if (mips_opts.fp != 0)
15714 mips_opts.fp = 32;
919731af 15715 break;
7361da2c
AB
15716 case ISA_MIPS32R6:
15717 mips_opts.gp = 32;
15718 mips_opts.fp = 64;
15719 break;
919731af 15720 case ISA_MIPS3:
15721 case ISA_MIPS4:
15722 case ISA_MIPS5:
15723 case ISA_MIPS64:
15724 case ISA_MIPS64R2:
15725 case ISA_MIPS64R3:
15726 case ISA_MIPS64R5:
7361da2c 15727 case ISA_MIPS64R6:
919731af 15728 mips_opts.gp = 64;
351cdf24
MF
15729 if (mips_opts.fp != 0)
15730 {
15731 if (mips_opts.arch == CPU_R5900)
15732 mips_opts.fp = 32;
15733 else
15734 mips_opts.fp = 64;
15735 }
919731af 15736 break;
15737 default:
15738 as_bad (_("unknown ISA level %s"), name + 4);
15739 break;
15740 }
e6559e01 15741 }
919731af 15742
15743 mips_check_options (&mips_opts, FALSE);
15744
15745 mips_check_isa_supports_ases ();
15746 *input_line_pointer = ch;
15747 demand_empty_rest_of_line ();
15748}
15749
15750/* Handle the .module pseudo-op. */
15751
15752static void
15753s_module (int ignore ATTRIBUTE_UNUSED)
15754{
15755 char *name = input_line_pointer, ch;
15756
15757 while (!is_end_of_line[(unsigned char) *input_line_pointer])
15758 ++input_line_pointer;
15759 ch = *input_line_pointer;
15760 *input_line_pointer = '\0';
15761
15762 if (!file_mips_opts_checked)
252b5132 15763 {
919731af 15764 if (!parse_code_option (name))
15765 as_bad (_(".module used with unrecognized symbol: %s\n"), name);
15766
15767 /* Update module level settings from mips_opts. */
15768 file_mips_opts = mips_opts;
252b5132 15769 }
919731af 15770 else
15771 as_bad (_(".module is not permitted after generating code"));
15772
252b5132
RH
15773 *input_line_pointer = ch;
15774 demand_empty_rest_of_line ();
15775}
15776
15777/* Handle the .abicalls pseudo-op. I believe this is equivalent to
15778 .option pic2. It means to generate SVR4 PIC calls. */
15779
15780static void
17a2f251 15781s_abicalls (int ignore ATTRIBUTE_UNUSED)
252b5132
RH
15782{
15783 mips_pic = SVR4_PIC;
143d77c5 15784 mips_abicalls = TRUE;
4d0d148d
TS
15785
15786 if (g_switch_seen && g_switch_value != 0)
15787 as_warn (_("-G may not be used with SVR4 PIC code"));
15788 g_switch_value = 0;
15789
252b5132
RH
15790 bfd_set_gp_size (stdoutput, 0);
15791 demand_empty_rest_of_line ();
15792}
15793
15794/* Handle the .cpload pseudo-op. This is used when generating SVR4
15795 PIC code. It sets the $gp register for the function based on the
15796 function address, which is in the register named in the argument.
15797 This uses a relocation against _gp_disp, which is handled specially
15798 by the linker. The result is:
15799 lui $gp,%hi(_gp_disp)
15800 addiu $gp,$gp,%lo(_gp_disp)
15801 addu $gp,$gp,.cpload argument
aa6975fb
ILT
15802 The .cpload argument is normally $25 == $t9.
15803
15804 The -mno-shared option changes this to:
bbe506e8
TS
15805 lui $gp,%hi(__gnu_local_gp)
15806 addiu $gp,$gp,%lo(__gnu_local_gp)
aa6975fb
ILT
15807 and the argument is ignored. This saves an instruction, but the
15808 resulting code is not position independent; it uses an absolute
bbe506e8
TS
15809 address for __gnu_local_gp. Thus code assembled with -mno-shared
15810 can go into an ordinary executable, but not into a shared library. */
252b5132
RH
15811
15812static void
17a2f251 15813s_cpload (int ignore ATTRIBUTE_UNUSED)
252b5132
RH
15814{
15815 expressionS ex;
aa6975fb
ILT
15816 int reg;
15817 int in_shared;
252b5132 15818
919731af 15819 file_mips_check_options ();
15820
6478892d
TS
15821 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
15822 .cpload is ignored. */
15823 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
252b5132
RH
15824 {
15825 s_ignore (0);
15826 return;
15827 }
15828
a276b80c
MR
15829 if (mips_opts.mips16)
15830 {
15831 as_bad (_("%s not supported in MIPS16 mode"), ".cpload");
15832 ignore_rest_of_line ();
15833 return;
15834 }
15835
d3ecfc59 15836 /* .cpload should be in a .set noreorder section. */
252b5132
RH
15837 if (mips_opts.noreorder == 0)
15838 as_warn (_(".cpload not in noreorder section"));
15839
aa6975fb
ILT
15840 reg = tc_get_register (0);
15841
15842 /* If we need to produce a 64-bit address, we are better off using
15843 the default instruction sequence. */
aed1a261 15844 in_shared = mips_in_shared || HAVE_64BIT_SYMBOLS;
aa6975fb 15845
252b5132 15846 ex.X_op = O_symbol;
bbe506e8
TS
15847 ex.X_add_symbol = symbol_find_or_make (in_shared ? "_gp_disp" :
15848 "__gnu_local_gp");
252b5132
RH
15849 ex.X_op_symbol = NULL;
15850 ex.X_add_number = 0;
15851
15852 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
49309057 15853 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
252b5132 15854
8a75745d
MR
15855 mips_mark_labels ();
15856 mips_assembling_insn = TRUE;
15857
584892a6 15858 macro_start ();
67c0d1eb
RS
15859 macro_build_lui (&ex, mips_gp_register);
15860 macro_build (&ex, "addiu", "t,r,j", mips_gp_register,
17a2f251 15861 mips_gp_register, BFD_RELOC_LO16);
aa6975fb
ILT
15862 if (in_shared)
15863 macro_build (NULL, "addu", "d,v,t", mips_gp_register,
15864 mips_gp_register, reg);
584892a6 15865 macro_end ();
252b5132 15866
8a75745d 15867 mips_assembling_insn = FALSE;
252b5132
RH
15868 demand_empty_rest_of_line ();
15869}
15870
6478892d
TS
15871/* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
15872 .cpsetup $reg1, offset|$reg2, label
15873
15874 If offset is given, this results in:
15875 sd $gp, offset($sp)
956cd1d6 15876 lui $gp, %hi(%neg(%gp_rel(label)))
698b7d9d
TS
15877 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
15878 daddu $gp, $gp, $reg1
6478892d
TS
15879
15880 If $reg2 is given, this results in:
15881 daddu $reg2, $gp, $0
956cd1d6 15882 lui $gp, %hi(%neg(%gp_rel(label)))
698b7d9d
TS
15883 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
15884 daddu $gp, $gp, $reg1
aa6975fb
ILT
15885 $reg1 is normally $25 == $t9.
15886
15887 The -mno-shared option replaces the last three instructions with
15888 lui $gp,%hi(_gp)
54f4ddb3 15889 addiu $gp,$gp,%lo(_gp) */
aa6975fb 15890
6478892d 15891static void
17a2f251 15892s_cpsetup (int ignore ATTRIBUTE_UNUSED)
6478892d
TS
15893{
15894 expressionS ex_off;
15895 expressionS ex_sym;
15896 int reg1;
6478892d 15897
919731af 15898 file_mips_check_options ();
15899
8586fc66 15900 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
6478892d
TS
15901 We also need NewABI support. */
15902 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
15903 {
15904 s_ignore (0);
15905 return;
15906 }
15907
a276b80c
MR
15908 if (mips_opts.mips16)
15909 {
15910 as_bad (_("%s not supported in MIPS16 mode"), ".cpsetup");
15911 ignore_rest_of_line ();
15912 return;
15913 }
15914
6478892d
TS
15915 reg1 = tc_get_register (0);
15916 SKIP_WHITESPACE ();
15917 if (*input_line_pointer != ',')
15918 {
15919 as_bad (_("missing argument separator ',' for .cpsetup"));
15920 return;
15921 }
15922 else
80245285 15923 ++input_line_pointer;
6478892d
TS
15924 SKIP_WHITESPACE ();
15925 if (*input_line_pointer == '$')
80245285
TS
15926 {
15927 mips_cpreturn_register = tc_get_register (0);
15928 mips_cpreturn_offset = -1;
15929 }
6478892d 15930 else
80245285
TS
15931 {
15932 mips_cpreturn_offset = get_absolute_expression ();
15933 mips_cpreturn_register = -1;
15934 }
6478892d
TS
15935 SKIP_WHITESPACE ();
15936 if (*input_line_pointer != ',')
15937 {
15938 as_bad (_("missing argument separator ',' for .cpsetup"));
15939 return;
15940 }
15941 else
f9419b05 15942 ++input_line_pointer;
6478892d 15943 SKIP_WHITESPACE ();
f21f8242 15944 expression (&ex_sym);
6478892d 15945
8a75745d
MR
15946 mips_mark_labels ();
15947 mips_assembling_insn = TRUE;
15948
584892a6 15949 macro_start ();
6478892d
TS
15950 if (mips_cpreturn_register == -1)
15951 {
15952 ex_off.X_op = O_constant;
15953 ex_off.X_add_symbol = NULL;
15954 ex_off.X_op_symbol = NULL;
15955 ex_off.X_add_number = mips_cpreturn_offset;
15956
67c0d1eb 15957 macro_build (&ex_off, "sd", "t,o(b)", mips_gp_register,
17a2f251 15958 BFD_RELOC_LO16, SP);
6478892d
TS
15959 }
15960 else
67c0d1eb 15961 macro_build (NULL, "daddu", "d,v,t", mips_cpreturn_register,
17a2f251 15962 mips_gp_register, 0);
6478892d 15963
aed1a261 15964 if (mips_in_shared || HAVE_64BIT_SYMBOLS)
aa6975fb 15965 {
df58fc94 15966 macro_build (&ex_sym, "lui", LUI_FMT, mips_gp_register,
aa6975fb
ILT
15967 -1, BFD_RELOC_GPREL16, BFD_RELOC_MIPS_SUB,
15968 BFD_RELOC_HI16_S);
15969
15970 macro_build (&ex_sym, "addiu", "t,r,j", mips_gp_register,
15971 mips_gp_register, -1, BFD_RELOC_GPREL16,
15972 BFD_RELOC_MIPS_SUB, BFD_RELOC_LO16);
15973
15974 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register,
15975 mips_gp_register, reg1);
15976 }
15977 else
15978 {
15979 expressionS ex;
15980
15981 ex.X_op = O_symbol;
4184909a 15982 ex.X_add_symbol = symbol_find_or_make ("__gnu_local_gp");
aa6975fb
ILT
15983 ex.X_op_symbol = NULL;
15984 ex.X_add_number = 0;
6e1304d8 15985
aa6975fb
ILT
15986 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
15987 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
15988
15989 macro_build_lui (&ex, mips_gp_register);
15990 macro_build (&ex, "addiu", "t,r,j", mips_gp_register,
15991 mips_gp_register, BFD_RELOC_LO16);
15992 }
f21f8242 15993
584892a6 15994 macro_end ();
6478892d 15995
8a75745d 15996 mips_assembling_insn = FALSE;
6478892d
TS
15997 demand_empty_rest_of_line ();
15998}
15999
16000static void
17a2f251 16001s_cplocal (int ignore ATTRIBUTE_UNUSED)
6478892d 16002{
919731af 16003 file_mips_check_options ();
16004
6478892d 16005 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
54f4ddb3 16006 .cplocal is ignored. */
6478892d
TS
16007 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
16008 {
16009 s_ignore (0);
16010 return;
16011 }
16012
a276b80c
MR
16013 if (mips_opts.mips16)
16014 {
16015 as_bad (_("%s not supported in MIPS16 mode"), ".cplocal");
16016 ignore_rest_of_line ();
16017 return;
16018 }
16019
6478892d 16020 mips_gp_register = tc_get_register (0);
85b51719 16021 demand_empty_rest_of_line ();
6478892d
TS
16022}
16023
252b5132
RH
16024/* Handle the .cprestore pseudo-op. This stores $gp into a given
16025 offset from $sp. The offset is remembered, and after making a PIC
16026 call $gp is restored from that location. */
16027
16028static void
17a2f251 16029s_cprestore (int ignore ATTRIBUTE_UNUSED)
252b5132
RH
16030{
16031 expressionS ex;
252b5132 16032
919731af 16033 file_mips_check_options ();
16034
6478892d 16035 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
c9914766 16036 .cprestore is ignored. */
6478892d 16037 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
252b5132
RH
16038 {
16039 s_ignore (0);
16040 return;
16041 }
16042
a276b80c
MR
16043 if (mips_opts.mips16)
16044 {
16045 as_bad (_("%s not supported in MIPS16 mode"), ".cprestore");
16046 ignore_rest_of_line ();
16047 return;
16048 }
16049
252b5132 16050 mips_cprestore_offset = get_absolute_expression ();
7a621144 16051 mips_cprestore_valid = 1;
252b5132
RH
16052
16053 ex.X_op = O_constant;
16054 ex.X_add_symbol = NULL;
16055 ex.X_op_symbol = NULL;
16056 ex.X_add_number = mips_cprestore_offset;
16057
8a75745d
MR
16058 mips_mark_labels ();
16059 mips_assembling_insn = TRUE;
16060
584892a6 16061 macro_start ();
67c0d1eb
RS
16062 macro_build_ldst_constoffset (&ex, ADDRESS_STORE_INSN, mips_gp_register,
16063 SP, HAVE_64BIT_ADDRESSES);
584892a6 16064 macro_end ();
252b5132 16065
8a75745d 16066 mips_assembling_insn = FALSE;
252b5132
RH
16067 demand_empty_rest_of_line ();
16068}
16069
6478892d 16070/* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
67c1ffbe 16071 was given in the preceding .cpsetup, it results in:
6478892d 16072 ld $gp, offset($sp)
76b3015f 16073
6478892d 16074 If a register $reg2 was given there, it results in:
54f4ddb3
TS
16075 daddu $gp, $reg2, $0 */
16076
6478892d 16077static void
17a2f251 16078s_cpreturn (int ignore ATTRIBUTE_UNUSED)
6478892d
TS
16079{
16080 expressionS ex;
6478892d 16081
919731af 16082 file_mips_check_options ();
16083
6478892d
TS
16084 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
16085 We also need NewABI support. */
16086 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
16087 {
16088 s_ignore (0);
16089 return;
16090 }
16091
a276b80c
MR
16092 if (mips_opts.mips16)
16093 {
16094 as_bad (_("%s not supported in MIPS16 mode"), ".cpreturn");
16095 ignore_rest_of_line ();
16096 return;
16097 }
16098
8a75745d
MR
16099 mips_mark_labels ();
16100 mips_assembling_insn = TRUE;
16101
584892a6 16102 macro_start ();
6478892d
TS
16103 if (mips_cpreturn_register == -1)
16104 {
16105 ex.X_op = O_constant;
16106 ex.X_add_symbol = NULL;
16107 ex.X_op_symbol = NULL;
16108 ex.X_add_number = mips_cpreturn_offset;
16109
67c0d1eb 16110 macro_build (&ex, "ld", "t,o(b)", mips_gp_register, BFD_RELOC_LO16, SP);
6478892d
TS
16111 }
16112 else
67c0d1eb 16113 macro_build (NULL, "daddu", "d,v,t", mips_gp_register,
17a2f251 16114 mips_cpreturn_register, 0);
584892a6 16115 macro_end ();
6478892d 16116
8a75745d 16117 mips_assembling_insn = FALSE;
6478892d
TS
16118 demand_empty_rest_of_line ();
16119}
16120
d0f13682
CLT
16121/* Handle a .dtprelword, .dtpreldword, .tprelword, or .tpreldword
16122 pseudo-op; DIRSTR says which. The pseudo-op generates a BYTES-size
16123 DTP- or TP-relative relocation of type RTYPE, for use in either DWARF
16124 debug information or MIPS16 TLS. */
741d6ea8
JM
16125
16126static void
d0f13682
CLT
16127s_tls_rel_directive (const size_t bytes, const char *dirstr,
16128 bfd_reloc_code_real_type rtype)
741d6ea8
JM
16129{
16130 expressionS ex;
16131 char *p;
16132
16133 expression (&ex);
16134
16135 if (ex.X_op != O_symbol)
16136 {
1661c76c 16137 as_bad (_("unsupported use of %s"), dirstr);
741d6ea8
JM
16138 ignore_rest_of_line ();
16139 }
16140
16141 p = frag_more (bytes);
16142 md_number_to_chars (p, 0, bytes);
d0f13682 16143 fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, FALSE, rtype);
741d6ea8 16144 demand_empty_rest_of_line ();
de64cffd 16145 mips_clear_insn_labels ();
741d6ea8
JM
16146}
16147
16148/* Handle .dtprelword. */
16149
16150static void
16151s_dtprelword (int ignore ATTRIBUTE_UNUSED)
16152{
d0f13682 16153 s_tls_rel_directive (4, ".dtprelword", BFD_RELOC_MIPS_TLS_DTPREL32);
741d6ea8
JM
16154}
16155
16156/* Handle .dtpreldword. */
16157
16158static void
16159s_dtpreldword (int ignore ATTRIBUTE_UNUSED)
16160{
d0f13682
CLT
16161 s_tls_rel_directive (8, ".dtpreldword", BFD_RELOC_MIPS_TLS_DTPREL64);
16162}
16163
16164/* Handle .tprelword. */
16165
16166static void
16167s_tprelword (int ignore ATTRIBUTE_UNUSED)
16168{
16169 s_tls_rel_directive (4, ".tprelword", BFD_RELOC_MIPS_TLS_TPREL32);
16170}
16171
16172/* Handle .tpreldword. */
16173
16174static void
16175s_tpreldword (int ignore ATTRIBUTE_UNUSED)
16176{
16177 s_tls_rel_directive (8, ".tpreldword", BFD_RELOC_MIPS_TLS_TPREL64);
741d6ea8
JM
16178}
16179
6478892d
TS
16180/* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
16181 code. It sets the offset to use in gp_rel relocations. */
16182
16183static void
17a2f251 16184s_gpvalue (int ignore ATTRIBUTE_UNUSED)
6478892d
TS
16185{
16186 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
16187 We also need NewABI support. */
16188 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
16189 {
16190 s_ignore (0);
16191 return;
16192 }
16193
def2e0dd 16194 mips_gprel_offset = get_absolute_expression ();
6478892d
TS
16195
16196 demand_empty_rest_of_line ();
16197}
16198
252b5132
RH
16199/* Handle the .gpword pseudo-op. This is used when generating PIC
16200 code. It generates a 32 bit GP relative reloc. */
16201
16202static void
17a2f251 16203s_gpword (int ignore ATTRIBUTE_UNUSED)
252b5132 16204{
a8dbcb85
TS
16205 segment_info_type *si;
16206 struct insn_label_list *l;
252b5132
RH
16207 expressionS ex;
16208 char *p;
16209
16210 /* When not generating PIC code, this is treated as .word. */
16211 if (mips_pic != SVR4_PIC)
16212 {
16213 s_cons (2);
16214 return;
16215 }
16216
a8dbcb85
TS
16217 si = seg_info (now_seg);
16218 l = si->label_list;
7d10b47d 16219 mips_emit_delays ();
252b5132 16220 if (auto_align)
462427c4 16221 mips_align (2, 0, l);
252b5132
RH
16222
16223 expression (&ex);
a1facbec 16224 mips_clear_insn_labels ();
252b5132
RH
16225
16226 if (ex.X_op != O_symbol || ex.X_add_number != 0)
16227 {
1661c76c 16228 as_bad (_("unsupported use of .gpword"));
252b5132
RH
16229 ignore_rest_of_line ();
16230 }
16231
16232 p = frag_more (4);
17a2f251 16233 md_number_to_chars (p, 0, 4);
b34976b6 16234 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
cdf6fd85 16235 BFD_RELOC_GPREL32);
252b5132
RH
16236
16237 demand_empty_rest_of_line ();
16238}
16239
10181a0d 16240static void
17a2f251 16241s_gpdword (int ignore ATTRIBUTE_UNUSED)
10181a0d 16242{
a8dbcb85
TS
16243 segment_info_type *si;
16244 struct insn_label_list *l;
10181a0d
AO
16245 expressionS ex;
16246 char *p;
16247
16248 /* When not generating PIC code, this is treated as .dword. */
16249 if (mips_pic != SVR4_PIC)
16250 {
16251 s_cons (3);
16252 return;
16253 }
16254
a8dbcb85
TS
16255 si = seg_info (now_seg);
16256 l = si->label_list;
7d10b47d 16257 mips_emit_delays ();
10181a0d 16258 if (auto_align)
462427c4 16259 mips_align (3, 0, l);
10181a0d
AO
16260
16261 expression (&ex);
a1facbec 16262 mips_clear_insn_labels ();
10181a0d
AO
16263
16264 if (ex.X_op != O_symbol || ex.X_add_number != 0)
16265 {
1661c76c 16266 as_bad (_("unsupported use of .gpdword"));
10181a0d
AO
16267 ignore_rest_of_line ();
16268 }
16269
16270 p = frag_more (8);
17a2f251 16271 md_number_to_chars (p, 0, 8);
a105a300 16272 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
6e1304d8 16273 BFD_RELOC_GPREL32)->fx_tcbit = 1;
10181a0d
AO
16274
16275 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
6e1304d8
RS
16276 fix_new (frag_now, p - frag_now->fr_literal, 8, NULL, 0,
16277 FALSE, BFD_RELOC_64)->fx_tcbit = 1;
10181a0d
AO
16278
16279 demand_empty_rest_of_line ();
16280}
16281
a3f278e2
CM
16282/* Handle the .ehword pseudo-op. This is used when generating unwinding
16283 tables. It generates a R_MIPS_EH reloc. */
16284
16285static void
16286s_ehword (int ignore ATTRIBUTE_UNUSED)
16287{
16288 expressionS ex;
16289 char *p;
16290
16291 mips_emit_delays ();
16292
16293 expression (&ex);
16294 mips_clear_insn_labels ();
16295
16296 if (ex.X_op != O_symbol || ex.X_add_number != 0)
16297 {
1661c76c 16298 as_bad (_("unsupported use of .ehword"));
a3f278e2
CM
16299 ignore_rest_of_line ();
16300 }
16301
16302 p = frag_more (4);
16303 md_number_to_chars (p, 0, 4);
16304 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
16305 BFD_RELOC_MIPS_EH);
16306
16307 demand_empty_rest_of_line ();
16308}
16309
252b5132
RH
16310/* Handle the .cpadd pseudo-op. This is used when dealing with switch
16311 tables in SVR4 PIC code. */
16312
16313static void
17a2f251 16314s_cpadd (int ignore ATTRIBUTE_UNUSED)
252b5132 16315{
252b5132
RH
16316 int reg;
16317
919731af 16318 file_mips_check_options ();
16319
10181a0d
AO
16320 /* This is ignored when not generating SVR4 PIC code. */
16321 if (mips_pic != SVR4_PIC)
252b5132
RH
16322 {
16323 s_ignore (0);
16324 return;
16325 }
16326
8a75745d
MR
16327 mips_mark_labels ();
16328 mips_assembling_insn = TRUE;
16329
252b5132 16330 /* Add $gp to the register named as an argument. */
584892a6 16331 macro_start ();
252b5132 16332 reg = tc_get_register (0);
67c0d1eb 16333 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register);
584892a6 16334 macro_end ();
252b5132 16335
8a75745d 16336 mips_assembling_insn = FALSE;
bdaaa2e1 16337 demand_empty_rest_of_line ();
252b5132
RH
16338}
16339
16340/* Handle the .insn pseudo-op. This marks instruction labels in
df58fc94 16341 mips16/micromips mode. This permits the linker to handle them specially,
252b5132
RH
16342 such as generating jalx instructions when needed. We also make
16343 them odd for the duration of the assembly, in order to generate the
16344 right sort of code. We will make them even in the adjust_symtab
16345 routine, while leaving them marked. This is convenient for the
16346 debugger and the disassembler. The linker knows to make them odd
16347 again. */
16348
16349static void
17a2f251 16350s_insn (int ignore ATTRIBUTE_UNUSED)
252b5132 16351{
7bb01e2d
MR
16352 file_mips_check_options ();
16353 file_ase_mips16 |= mips_opts.mips16;
16354 file_ase_micromips |= mips_opts.micromips;
16355
df58fc94 16356 mips_mark_labels ();
252b5132
RH
16357
16358 demand_empty_rest_of_line ();
16359}
16360
ba92f887
MR
16361/* Handle the .nan pseudo-op. */
16362
16363static void
16364s_nan (int ignore ATTRIBUTE_UNUSED)
16365{
16366 static const char str_legacy[] = "legacy";
16367 static const char str_2008[] = "2008";
16368 size_t i;
16369
16370 for (i = 0; !is_end_of_line[(unsigned char) input_line_pointer[i]]; i++);
16371
16372 if (i == sizeof (str_2008) - 1
16373 && memcmp (input_line_pointer, str_2008, i) == 0)
7361da2c 16374 mips_nan2008 = 1;
ba92f887
MR
16375 else if (i == sizeof (str_legacy) - 1
16376 && memcmp (input_line_pointer, str_legacy, i) == 0)
7361da2c
AB
16377 {
16378 if (ISA_HAS_LEGACY_NAN (file_mips_opts.isa))
16379 mips_nan2008 = 0;
16380 else
16381 as_bad (_("`%s' does not support legacy NaN"),
16382 mips_cpu_info_from_isa (file_mips_opts.isa)->name);
16383 }
ba92f887 16384 else
1661c76c 16385 as_bad (_("bad .nan directive"));
ba92f887
MR
16386
16387 input_line_pointer += i;
16388 demand_empty_rest_of_line ();
16389}
16390
754e2bb9
RS
16391/* Handle a .stab[snd] directive. Ideally these directives would be
16392 implemented in a transparent way, so that removing them would not
16393 have any effect on the generated instructions. However, s_stab
16394 internally changes the section, so in practice we need to decide
16395 now whether the preceding label marks compressed code. We do not
16396 support changing the compression mode of a label after a .stab*
16397 directive, such as in:
16398
16399 foo:
16400 .stabs ...
16401 .set mips16
16402
16403 so the current mode wins. */
252b5132
RH
16404
16405static void
17a2f251 16406s_mips_stab (int type)
252b5132 16407{
754e2bb9 16408 mips_mark_labels ();
252b5132
RH
16409 s_stab (type);
16410}
16411
54f4ddb3 16412/* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */
252b5132
RH
16413
16414static void
17a2f251 16415s_mips_weakext (int ignore ATTRIBUTE_UNUSED)
252b5132
RH
16416{
16417 char *name;
16418 int c;
16419 symbolS *symbolP;
16420 expressionS exp;
16421
16422 name = input_line_pointer;
16423 c = get_symbol_end ();
16424 symbolP = symbol_find_or_make (name);
16425 S_SET_WEAK (symbolP);
16426 *input_line_pointer = c;
16427
16428 SKIP_WHITESPACE ();
16429
16430 if (! is_end_of_line[(unsigned char) *input_line_pointer])
16431 {
16432 if (S_IS_DEFINED (symbolP))
16433 {
20203fb9 16434 as_bad (_("ignoring attempt to redefine symbol %s"),
252b5132
RH
16435 S_GET_NAME (symbolP));
16436 ignore_rest_of_line ();
16437 return;
16438 }
bdaaa2e1 16439
252b5132
RH
16440 if (*input_line_pointer == ',')
16441 {
16442 ++input_line_pointer;
16443 SKIP_WHITESPACE ();
16444 }
bdaaa2e1 16445
252b5132
RH
16446 expression (&exp);
16447 if (exp.X_op != O_symbol)
16448 {
20203fb9 16449 as_bad (_("bad .weakext directive"));
98d3f06f 16450 ignore_rest_of_line ();
252b5132
RH
16451 return;
16452 }
49309057 16453 symbol_set_value_expression (symbolP, &exp);
252b5132
RH
16454 }
16455
16456 demand_empty_rest_of_line ();
16457}
16458
16459/* Parse a register string into a number. Called from the ECOFF code
16460 to parse .frame. The argument is non-zero if this is the frame
16461 register, so that we can record it in mips_frame_reg. */
16462
16463int
17a2f251 16464tc_get_register (int frame)
252b5132 16465{
707bfff6 16466 unsigned int reg;
252b5132
RH
16467
16468 SKIP_WHITESPACE ();
707bfff6
TS
16469 if (! reg_lookup (&input_line_pointer, RWARN | RTYPE_NUM | RTYPE_GP, &reg))
16470 reg = 0;
252b5132 16471 if (frame)
7a621144
DJ
16472 {
16473 mips_frame_reg = reg != 0 ? reg : SP;
16474 mips_frame_reg_valid = 1;
16475 mips_cprestore_valid = 0;
16476 }
252b5132
RH
16477 return reg;
16478}
16479
16480valueT
17a2f251 16481md_section_align (asection *seg, valueT addr)
252b5132
RH
16482{
16483 int align = bfd_get_section_alignment (stdoutput, seg);
16484
f3ded42a
RS
16485 /* We don't need to align ELF sections to the full alignment.
16486 However, Irix 5 may prefer that we align them at least to a 16
16487 byte boundary. We don't bother to align the sections if we
16488 are targeted for an embedded system. */
16489 if (strncmp (TARGET_OS, "elf", 3) == 0)
16490 return addr;
16491 if (align > 4)
16492 align = 4;
252b5132
RH
16493
16494 return ((addr + (1 << align) - 1) & (-1 << align));
16495}
16496
16497/* Utility routine, called from above as well. If called while the
16498 input file is still being read, it's only an approximation. (For
16499 example, a symbol may later become defined which appeared to be
16500 undefined earlier.) */
16501
16502static int
17a2f251 16503nopic_need_relax (symbolS *sym, int before_relaxing)
252b5132
RH
16504{
16505 if (sym == 0)
16506 return 0;
16507
4d0d148d 16508 if (g_switch_value > 0)
252b5132
RH
16509 {
16510 const char *symname;
16511 int change;
16512
c9914766 16513 /* Find out whether this symbol can be referenced off the $gp
252b5132
RH
16514 register. It can be if it is smaller than the -G size or if
16515 it is in the .sdata or .sbss section. Certain symbols can
c9914766 16516 not be referenced off the $gp, although it appears as though
252b5132
RH
16517 they can. */
16518 symname = S_GET_NAME (sym);
16519 if (symname != (const char *) NULL
16520 && (strcmp (symname, "eprol") == 0
16521 || strcmp (symname, "etext") == 0
16522 || strcmp (symname, "_gp") == 0
16523 || strcmp (symname, "edata") == 0
16524 || strcmp (symname, "_fbss") == 0
16525 || strcmp (symname, "_fdata") == 0
16526 || strcmp (symname, "_ftext") == 0
16527 || strcmp (symname, "end") == 0
16528 || strcmp (symname, "_gp_disp") == 0))
16529 change = 1;
16530 else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym))
16531 && (0
16532#ifndef NO_ECOFF_DEBUGGING
49309057
ILT
16533 || (symbol_get_obj (sym)->ecoff_extern_size != 0
16534 && (symbol_get_obj (sym)->ecoff_extern_size
16535 <= g_switch_value))
252b5132
RH
16536#endif
16537 /* We must defer this decision until after the whole
16538 file has been read, since there might be a .extern
16539 after the first use of this symbol. */
16540 || (before_relaxing
16541#ifndef NO_ECOFF_DEBUGGING
49309057 16542 && symbol_get_obj (sym)->ecoff_extern_size == 0
252b5132
RH
16543#endif
16544 && S_GET_VALUE (sym) == 0)
16545 || (S_GET_VALUE (sym) != 0
16546 && S_GET_VALUE (sym) <= g_switch_value)))
16547 change = 0;
16548 else
16549 {
16550 const char *segname;
16551
16552 segname = segment_name (S_GET_SEGMENT (sym));
9c2799c2 16553 gas_assert (strcmp (segname, ".lit8") != 0
252b5132
RH
16554 && strcmp (segname, ".lit4") != 0);
16555 change = (strcmp (segname, ".sdata") != 0
fba2b7f9
GK
16556 && strcmp (segname, ".sbss") != 0
16557 && strncmp (segname, ".sdata.", 7) != 0
d4dc2f22
TS
16558 && strncmp (segname, ".sbss.", 6) != 0
16559 && strncmp (segname, ".gnu.linkonce.sb.", 17) != 0
fba2b7f9 16560 && strncmp (segname, ".gnu.linkonce.s.", 16) != 0);
252b5132
RH
16561 }
16562 return change;
16563 }
16564 else
c9914766 16565 /* We are not optimizing for the $gp register. */
252b5132
RH
16566 return 1;
16567}
16568
5919d012
RS
16569
16570/* Return true if the given symbol should be considered local for SVR4 PIC. */
16571
16572static bfd_boolean
17a2f251 16573pic_need_relax (symbolS *sym, asection *segtype)
5919d012
RS
16574{
16575 asection *symsec;
5919d012
RS
16576
16577 /* Handle the case of a symbol equated to another symbol. */
16578 while (symbol_equated_reloc_p (sym))
16579 {
16580 symbolS *n;
16581
5f0fe04b 16582 /* It's possible to get a loop here in a badly written program. */
5919d012
RS
16583 n = symbol_get_value_expression (sym)->X_add_symbol;
16584 if (n == sym)
16585 break;
16586 sym = n;
16587 }
16588
df1f3cda
DD
16589 if (symbol_section_p (sym))
16590 return TRUE;
16591
5919d012
RS
16592 symsec = S_GET_SEGMENT (sym);
16593
5919d012 16594 /* This must duplicate the test in adjust_reloc_syms. */
45dfa85a
AM
16595 return (!bfd_is_und_section (symsec)
16596 && !bfd_is_abs_section (symsec)
5f0fe04b
TS
16597 && !bfd_is_com_section (symsec)
16598 && !s_is_linkonce (sym, segtype)
5919d012 16599 /* A global or weak symbol is treated as external. */
f3ded42a 16600 && (!S_IS_WEAK (sym) && !S_IS_EXTERNAL (sym)));
5919d012
RS
16601}
16602
16603
252b5132
RH
16604/* Given a mips16 variant frag FRAGP, return non-zero if it needs an
16605 extended opcode. SEC is the section the frag is in. */
16606
16607static int
17a2f251 16608mips16_extended_frag (fragS *fragp, asection *sec, long stretch)
252b5132
RH
16609{
16610 int type;
3ccad066 16611 const struct mips_int_operand *operand;
252b5132 16612 offsetT val;
252b5132 16613 segT symsec;
98aa84af 16614 fragS *sym_frag;
252b5132
RH
16615
16616 if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype))
16617 return 0;
16618 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype))
16619 return 1;
16620
16621 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
3ccad066 16622 operand = mips16_immed_operand (type, FALSE);
252b5132 16623
98aa84af 16624 sym_frag = symbol_get_frag (fragp->fr_symbol);
ac62c346 16625 val = S_GET_VALUE (fragp->fr_symbol);
98aa84af 16626 symsec = S_GET_SEGMENT (fragp->fr_symbol);
252b5132 16627
3ccad066 16628 if (operand->root.type == OP_PCREL)
252b5132 16629 {
3ccad066 16630 const struct mips_pcrel_operand *pcrel_op;
252b5132 16631 addressT addr;
3ccad066 16632 offsetT maxtiny;
252b5132
RH
16633
16634 /* We won't have the section when we are called from
16635 mips_relax_frag. However, we will always have been called
16636 from md_estimate_size_before_relax first. If this is a
16637 branch to a different section, we mark it as such. If SEC is
16638 NULL, and the frag is not marked, then it must be a branch to
16639 the same section. */
3ccad066 16640 pcrel_op = (const struct mips_pcrel_operand *) operand;
252b5132
RH
16641 if (sec == NULL)
16642 {
16643 if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype))
16644 return 1;
16645 }
16646 else
16647 {
98aa84af 16648 /* Must have been called from md_estimate_size_before_relax. */
252b5132
RH
16649 if (symsec != sec)
16650 {
16651 fragp->fr_subtype =
16652 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
16653
16654 /* FIXME: We should support this, and let the linker
16655 catch branches and loads that are out of range. */
16656 as_bad_where (fragp->fr_file, fragp->fr_line,
16657 _("unsupported PC relative reference to different section"));
16658
16659 return 1;
16660 }
98aa84af
AM
16661 if (fragp != sym_frag && sym_frag->fr_address == 0)
16662 /* Assume non-extended on the first relaxation pass.
16663 The address we have calculated will be bogus if this is
16664 a forward branch to another frag, as the forward frag
16665 will have fr_address == 0. */
16666 return 0;
252b5132
RH
16667 }
16668
16669 /* In this case, we know for sure that the symbol fragment is in
98aa84af
AM
16670 the same section. If the relax_marker of the symbol fragment
16671 differs from the relax_marker of this fragment, we have not
16672 yet adjusted the symbol fragment fr_address. We want to add
252b5132
RH
16673 in STRETCH in order to get a better estimate of the address.
16674 This particularly matters because of the shift bits. */
16675 if (stretch != 0
98aa84af 16676 && sym_frag->relax_marker != fragp->relax_marker)
252b5132
RH
16677 {
16678 fragS *f;
16679
16680 /* Adjust stretch for any alignment frag. Note that if have
16681 been expanding the earlier code, the symbol may be
16682 defined in what appears to be an earlier frag. FIXME:
16683 This doesn't handle the fr_subtype field, which specifies
16684 a maximum number of bytes to skip when doing an
16685 alignment. */
98aa84af 16686 for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next)
252b5132
RH
16687 {
16688 if (f->fr_type == rs_align || f->fr_type == rs_align_code)
16689 {
16690 if (stretch < 0)
16691 stretch = - ((- stretch)
16692 & ~ ((1 << (int) f->fr_offset) - 1));
16693 else
16694 stretch &= ~ ((1 << (int) f->fr_offset) - 1);
16695 if (stretch == 0)
16696 break;
16697 }
16698 }
16699 if (f != NULL)
16700 val += stretch;
16701 }
16702
16703 addr = fragp->fr_address + fragp->fr_fix;
16704
16705 /* The base address rules are complicated. The base address of
16706 a branch is the following instruction. The base address of a
16707 PC relative load or add is the instruction itself, but if it
16708 is in a delay slot (in which case it can not be extended) use
16709 the address of the instruction whose delay slot it is in. */
3ccad066 16710 if (pcrel_op->include_isa_bit)
252b5132
RH
16711 {
16712 addr += 2;
16713
16714 /* If we are currently assuming that this frag should be
16715 extended, then, the current address is two bytes
bdaaa2e1 16716 higher. */
252b5132
RH
16717 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
16718 addr += 2;
16719
16720 /* Ignore the low bit in the target, since it will be set
16721 for a text label. */
3ccad066 16722 val &= -2;
252b5132
RH
16723 }
16724 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
16725 addr -= 4;
16726 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
16727 addr -= 2;
16728
3ccad066 16729 val -= addr & -(1 << pcrel_op->align_log2);
252b5132
RH
16730
16731 /* If any of the shifted bits are set, we must use an extended
16732 opcode. If the address depends on the size of this
16733 instruction, this can lead to a loop, so we arrange to always
16734 use an extended opcode. We only check this when we are in
16735 the main relaxation loop, when SEC is NULL. */
3ccad066 16736 if ((val & ((1 << operand->shift) - 1)) != 0 && sec == NULL)
252b5132
RH
16737 {
16738 fragp->fr_subtype =
16739 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
16740 return 1;
16741 }
16742
16743 /* If we are about to mark a frag as extended because the value
3ccad066
RS
16744 is precisely the next value above maxtiny, then there is a
16745 chance of an infinite loop as in the following code:
252b5132
RH
16746 la $4,foo
16747 .skip 1020
16748 .align 2
16749 foo:
16750 In this case when the la is extended, foo is 0x3fc bytes
16751 away, so the la can be shrunk, but then foo is 0x400 away, so
16752 the la must be extended. To avoid this loop, we mark the
16753 frag as extended if it was small, and is about to become
3ccad066
RS
16754 extended with the next value above maxtiny. */
16755 maxtiny = mips_int_operand_max (operand);
16756 if (val == maxtiny + (1 << operand->shift)
252b5132
RH
16757 && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)
16758 && sec == NULL)
16759 {
16760 fragp->fr_subtype =
16761 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
16762 return 1;
16763 }
16764 }
16765 else if (symsec != absolute_section && sec != NULL)
16766 as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation"));
16767
3ccad066 16768 return !mips16_immed_in_range_p (operand, BFD_RELOC_UNUSED, val);
252b5132
RH
16769}
16770
4a6a3df4
AO
16771/* Compute the length of a branch sequence, and adjust the
16772 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
16773 worst-case length is computed, with UPDATE being used to indicate
16774 whether an unconditional (-1), branch-likely (+1) or regular (0)
16775 branch is to be computed. */
16776static int
17a2f251 16777relaxed_branch_length (fragS *fragp, asection *sec, int update)
4a6a3df4 16778{
b34976b6 16779 bfd_boolean toofar;
4a6a3df4
AO
16780 int length;
16781
16782 if (fragp
16783 && S_IS_DEFINED (fragp->fr_symbol)
16784 && sec == S_GET_SEGMENT (fragp->fr_symbol))
16785 {
16786 addressT addr;
16787 offsetT val;
16788
16789 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
16790
16791 addr = fragp->fr_address + fragp->fr_fix + 4;
16792
16793 val -= addr;
16794
16795 toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2);
16796 }
16797 else if (fragp)
16798 /* If the symbol is not defined or it's in a different segment,
16799 assume the user knows what's going on and emit a short
16800 branch. */
b34976b6 16801 toofar = FALSE;
4a6a3df4 16802 else
b34976b6 16803 toofar = TRUE;
4a6a3df4
AO
16804
16805 if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
16806 fragp->fr_subtype
66b3e8da
MR
16807 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp->fr_subtype),
16808 RELAX_BRANCH_UNCOND (fragp->fr_subtype),
4a6a3df4
AO
16809 RELAX_BRANCH_LIKELY (fragp->fr_subtype),
16810 RELAX_BRANCH_LINK (fragp->fr_subtype),
16811 toofar);
16812
16813 length = 4;
16814 if (toofar)
16815 {
16816 if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0))
16817 length += 8;
16818
16819 if (mips_pic != NO_PIC)
16820 {
16821 /* Additional space for PIC loading of target address. */
16822 length += 8;
16823 if (mips_opts.isa == ISA_MIPS1)
16824 /* Additional space for $at-stabilizing nop. */
16825 length += 4;
16826 }
16827
16828 /* If branch is conditional. */
16829 if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0))
16830 length += 8;
16831 }
b34976b6 16832
4a6a3df4
AO
16833 return length;
16834}
16835
df58fc94
RS
16836/* Compute the length of a branch sequence, and adjust the
16837 RELAX_MICROMIPS_TOOFAR32 bit accordingly. If FRAGP is NULL, the
16838 worst-case length is computed, with UPDATE being used to indicate
16839 whether an unconditional (-1), or regular (0) branch is to be
16840 computed. */
16841
16842static int
16843relaxed_micromips_32bit_branch_length (fragS *fragp, asection *sec, int update)
16844{
16845 bfd_boolean toofar;
16846 int length;
16847
16848 if (fragp
16849 && S_IS_DEFINED (fragp->fr_symbol)
16850 && sec == S_GET_SEGMENT (fragp->fr_symbol))
16851 {
16852 addressT addr;
16853 offsetT val;
16854
16855 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
16856 /* Ignore the low bit in the target, since it will be set
16857 for a text label. */
16858 if ((val & 1) != 0)
16859 --val;
16860
16861 addr = fragp->fr_address + fragp->fr_fix + 4;
16862
16863 val -= addr;
16864
16865 toofar = val < - (0x8000 << 1) || val >= (0x8000 << 1);
16866 }
16867 else if (fragp)
16868 /* If the symbol is not defined or it's in a different segment,
16869 assume the user knows what's going on and emit a short
16870 branch. */
16871 toofar = FALSE;
16872 else
16873 toofar = TRUE;
16874
16875 if (fragp && update
16876 && toofar != RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype))
16877 fragp->fr_subtype = (toofar
16878 ? RELAX_MICROMIPS_MARK_TOOFAR32 (fragp->fr_subtype)
16879 : RELAX_MICROMIPS_CLEAR_TOOFAR32 (fragp->fr_subtype));
16880
16881 length = 4;
16882 if (toofar)
16883 {
16884 bfd_boolean compact_known = fragp != NULL;
16885 bfd_boolean compact = FALSE;
16886 bfd_boolean uncond;
16887
16888 if (compact_known)
16889 compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype);
16890 if (fragp)
16891 uncond = RELAX_MICROMIPS_UNCOND (fragp->fr_subtype);
16892 else
16893 uncond = update < 0;
16894
16895 /* If label is out of range, we turn branch <br>:
16896
16897 <br> label # 4 bytes
16898 0:
16899
16900 into:
16901
16902 j label # 4 bytes
16903 nop # 2 bytes if compact && !PIC
16904 0:
16905 */
16906 if (mips_pic == NO_PIC && (!compact_known || compact))
16907 length += 2;
16908
16909 /* If assembling PIC code, we further turn:
16910
16911 j label # 4 bytes
16912
16913 into:
16914
16915 lw/ld at, %got(label)(gp) # 4 bytes
16916 d/addiu at, %lo(label) # 4 bytes
16917 jr/c at # 2 bytes
16918 */
16919 if (mips_pic != NO_PIC)
16920 length += 6;
16921
16922 /* If branch <br> is conditional, we prepend negated branch <brneg>:
16923
16924 <brneg> 0f # 4 bytes
16925 nop # 2 bytes if !compact
16926 */
16927 if (!uncond)
16928 length += (compact_known && compact) ? 4 : 6;
16929 }
16930
16931 return length;
16932}
16933
16934/* Compute the length of a branch, and adjust the RELAX_MICROMIPS_TOOFAR16
16935 bit accordingly. */
16936
16937static int
16938relaxed_micromips_16bit_branch_length (fragS *fragp, asection *sec, int update)
16939{
16940 bfd_boolean toofar;
16941
df58fc94
RS
16942 if (fragp
16943 && S_IS_DEFINED (fragp->fr_symbol)
16944 && sec == S_GET_SEGMENT (fragp->fr_symbol))
16945 {
16946 addressT addr;
16947 offsetT val;
16948 int type;
16949
16950 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
16951 /* Ignore the low bit in the target, since it will be set
16952 for a text label. */
16953 if ((val & 1) != 0)
16954 --val;
16955
16956 /* Assume this is a 2-byte branch. */
16957 addr = fragp->fr_address + fragp->fr_fix + 2;
16958
16959 /* We try to avoid the infinite loop by not adding 2 more bytes for
16960 long branches. */
16961
16962 val -= addr;
16963
16964 type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype);
16965 if (type == 'D')
16966 toofar = val < - (0x200 << 1) || val >= (0x200 << 1);
16967 else if (type == 'E')
16968 toofar = val < - (0x40 << 1) || val >= (0x40 << 1);
16969 else
16970 abort ();
16971 }
16972 else
16973 /* If the symbol is not defined or it's in a different segment,
16974 we emit a normal 32-bit branch. */
16975 toofar = TRUE;
16976
16977 if (fragp && update
16978 && toofar != RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype))
16979 fragp->fr_subtype
16980 = toofar ? RELAX_MICROMIPS_MARK_TOOFAR16 (fragp->fr_subtype)
16981 : RELAX_MICROMIPS_CLEAR_TOOFAR16 (fragp->fr_subtype);
16982
16983 if (toofar)
16984 return 4;
16985
16986 return 2;
16987}
16988
252b5132
RH
16989/* Estimate the size of a frag before relaxing. Unless this is the
16990 mips16, we are not really relaxing here, and the final size is
16991 encoded in the subtype information. For the mips16, we have to
16992 decide whether we are using an extended opcode or not. */
16993
252b5132 16994int
17a2f251 16995md_estimate_size_before_relax (fragS *fragp, asection *segtype)
252b5132 16996{
5919d012 16997 int change;
252b5132 16998
4a6a3df4
AO
16999 if (RELAX_BRANCH_P (fragp->fr_subtype))
17000 {
17001
b34976b6
AM
17002 fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE);
17003
4a6a3df4
AO
17004 return fragp->fr_var;
17005 }
17006
252b5132 17007 if (RELAX_MIPS16_P (fragp->fr_subtype))
177b4a6a
AO
17008 /* We don't want to modify the EXTENDED bit here; it might get us
17009 into infinite loops. We change it only in mips_relax_frag(). */
17010 return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2);
252b5132 17011
df58fc94
RS
17012 if (RELAX_MICROMIPS_P (fragp->fr_subtype))
17013 {
17014 int length = 4;
17015
17016 if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0)
17017 length = relaxed_micromips_16bit_branch_length (fragp, segtype, FALSE);
17018 if (length == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype))
17019 length = relaxed_micromips_32bit_branch_length (fragp, segtype, FALSE);
17020 fragp->fr_var = length;
17021
17022 return length;
17023 }
17024
252b5132 17025 if (mips_pic == NO_PIC)
5919d012 17026 change = nopic_need_relax (fragp->fr_symbol, 0);
252b5132 17027 else if (mips_pic == SVR4_PIC)
5919d012 17028 change = pic_need_relax (fragp->fr_symbol, segtype);
0a44bf69
RS
17029 else if (mips_pic == VXWORKS_PIC)
17030 /* For vxworks, GOT16 relocations never have a corresponding LO16. */
17031 change = 0;
252b5132
RH
17032 else
17033 abort ();
17034
17035 if (change)
17036 {
4d7206a2 17037 fragp->fr_subtype |= RELAX_USE_SECOND;
4d7206a2 17038 return -RELAX_FIRST (fragp->fr_subtype);
252b5132 17039 }
4d7206a2
RS
17040 else
17041 return -RELAX_SECOND (fragp->fr_subtype);
252b5132
RH
17042}
17043
17044/* This is called to see whether a reloc against a defined symbol
de7e6852 17045 should be converted into a reloc against a section. */
252b5132
RH
17046
17047int
17a2f251 17048mips_fix_adjustable (fixS *fixp)
252b5132 17049{
252b5132
RH
17050 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
17051 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
17052 return 0;
a161fe53 17053
252b5132
RH
17054 if (fixp->fx_addsy == NULL)
17055 return 1;
a161fe53 17056
de7e6852
RS
17057 /* If symbol SYM is in a mergeable section, relocations of the form
17058 SYM + 0 can usually be made section-relative. The mergeable data
17059 is then identified by the section offset rather than by the symbol.
17060
17061 However, if we're generating REL LO16 relocations, the offset is split
17062 between the LO16 and parterning high part relocation. The linker will
17063 need to recalculate the complete offset in order to correctly identify
17064 the merge data.
17065
17066 The linker has traditionally not looked for the parterning high part
17067 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
17068 placed anywhere. Rather than break backwards compatibility by changing
17069 this, it seems better not to force the issue, and instead keep the
17070 original symbol. This will work with either linker behavior. */
738e5348 17071 if ((lo16_reloc_p (fixp->fx_r_type)
704803a9 17072 || reloc_needs_lo_p (fixp->fx_r_type))
de7e6852
RS
17073 && HAVE_IN_PLACE_ADDENDS
17074 && (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_MERGE) != 0)
17075 return 0;
17076
ce70d90a 17077 /* There is no place to store an in-place offset for JALR relocations.
2de39019
CM
17078 Likewise an in-range offset of limited PC-relative relocations may
17079 overflow the in-place relocatable field if recalculated against the
7361da2c
AB
17080 start address of the symbol's containing section.
17081
17082 Also, PC relative relocations for MIPS R6 need to be symbol rather than
17083 section relative to allow linker relaxations to be performed later on. */
17084 if ((HAVE_IN_PLACE_ADDENDS || ISA_IS_R6 (mips_opts.isa))
2de39019
CM
17085 && (limited_pcrel_reloc_p (fixp->fx_r_type)
17086 || jalr_reloc_p (fixp->fx_r_type)))
1180b5a4
RS
17087 return 0;
17088
b314ec0e
RS
17089 /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve
17090 to a floating-point stub. The same is true for non-R_MIPS16_26
17091 relocations against MIPS16 functions; in this case, the stub becomes
17092 the function's canonical address.
17093
17094 Floating-point stubs are stored in unique .mips16.call.* or
17095 .mips16.fn.* sections. If a stub T for function F is in section S,
17096 the first relocation in section S must be against F; this is how the
17097 linker determines the target function. All relocations that might
17098 resolve to T must also be against F. We therefore have the following
17099 restrictions, which are given in an intentionally-redundant way:
17100
17101 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16
17102 symbols.
17103
17104 2. We cannot reduce a stub's relocations against non-MIPS16 symbols
17105 if that stub might be used.
17106
17107 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16
17108 symbols.
17109
17110 4. We cannot reduce a stub's relocations against MIPS16 symbols if
17111 that stub might be used.
17112
17113 There is a further restriction:
17114
df58fc94
RS
17115 5. We cannot reduce jump relocations (R_MIPS_26, R_MIPS16_26 or
17116 R_MICROMIPS_26_S1) against MIPS16 or microMIPS symbols on
17117 targets with in-place addends; the relocation field cannot
b314ec0e
RS
17118 encode the low bit.
17119
df58fc94
RS
17120 For simplicity, we deal with (3)-(4) by not reducing _any_ relocation
17121 against a MIPS16 symbol. We deal with (5) by by not reducing any
17122 such relocations on REL targets.
b314ec0e
RS
17123
17124 We deal with (1)-(2) by saying that, if there's a R_MIPS16_26
17125 relocation against some symbol R, no relocation against R may be
17126 reduced. (Note that this deals with (2) as well as (1) because
17127 relocations against global symbols will never be reduced on ELF
17128 targets.) This approach is a little simpler than trying to detect
17129 stub sections, and gives the "all or nothing" per-symbol consistency
17130 that we have for MIPS16 symbols. */
f3ded42a 17131 if (fixp->fx_subsy == NULL
30c09090 17132 && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp->fx_addsy))
df58fc94
RS
17133 || *symbol_get_tc (fixp->fx_addsy)
17134 || (HAVE_IN_PLACE_ADDENDS
17135 && ELF_ST_IS_MICROMIPS (S_GET_OTHER (fixp->fx_addsy))
17136 && jmp_reloc_p (fixp->fx_r_type))))
252b5132 17137 return 0;
a161fe53 17138
252b5132
RH
17139 return 1;
17140}
17141
17142/* Translate internal representation of relocation info to BFD target
17143 format. */
17144
17145arelent **
17a2f251 17146tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
252b5132
RH
17147{
17148 static arelent *retval[4];
17149 arelent *reloc;
17150 bfd_reloc_code_real_type code;
17151
4b0cff4e
TS
17152 memset (retval, 0, sizeof(retval));
17153 reloc = retval[0] = (arelent *) xcalloc (1, sizeof (arelent));
49309057
ILT
17154 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
17155 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH
17156 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
17157
bad36eac
DJ
17158 if (fixp->fx_pcrel)
17159 {
df58fc94
RS
17160 gas_assert (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2
17161 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1
17162 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1
b47468a6 17163 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1
7361da2c
AB
17164 || fixp->fx_r_type == BFD_RELOC_32_PCREL
17165 || fixp->fx_r_type == BFD_RELOC_MIPS_21_PCREL_S2
17166 || fixp->fx_r_type == BFD_RELOC_MIPS_26_PCREL_S2
17167 || fixp->fx_r_type == BFD_RELOC_MIPS_18_PCREL_S3
17168 || fixp->fx_r_type == BFD_RELOC_MIPS_19_PCREL_S2
17169 || fixp->fx_r_type == BFD_RELOC_HI16_S_PCREL
17170 || fixp->fx_r_type == BFD_RELOC_LO16_PCREL);
bad36eac
DJ
17171
17172 /* At this point, fx_addnumber is "symbol offset - pcrel address".
17173 Relocations want only the symbol offset. */
17174 reloc->addend = fixp->fx_addnumber + reloc->address;
bad36eac
DJ
17175 }
17176 else
17177 reloc->addend = fixp->fx_addnumber;
252b5132 17178
438c16b8
TS
17179 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
17180 entry to be used in the relocation's section offset. */
17181 if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
252b5132
RH
17182 {
17183 reloc->address = reloc->addend;
17184 reloc->addend = 0;
17185 }
17186
252b5132 17187 code = fixp->fx_r_type;
252b5132 17188
bad36eac 17189 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
252b5132
RH
17190 if (reloc->howto == NULL)
17191 {
17192 as_bad_where (fixp->fx_file, fixp->fx_line,
1661c76c
RS
17193 _("cannot represent %s relocation in this object file"
17194 " format"),
252b5132
RH
17195 bfd_get_reloc_code_name (code));
17196 retval[0] = NULL;
17197 }
17198
17199 return retval;
17200}
17201
17202/* Relax a machine dependent frag. This returns the amount by which
17203 the current size of the frag should change. */
17204
17205int
17a2f251 17206mips_relax_frag (asection *sec, fragS *fragp, long stretch)
252b5132 17207{
4a6a3df4
AO
17208 if (RELAX_BRANCH_P (fragp->fr_subtype))
17209 {
17210 offsetT old_var = fragp->fr_var;
b34976b6
AM
17211
17212 fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE);
4a6a3df4
AO
17213
17214 return fragp->fr_var - old_var;
17215 }
17216
df58fc94
RS
17217 if (RELAX_MICROMIPS_P (fragp->fr_subtype))
17218 {
17219 offsetT old_var = fragp->fr_var;
17220 offsetT new_var = 4;
17221
17222 if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0)
17223 new_var = relaxed_micromips_16bit_branch_length (fragp, sec, TRUE);
17224 if (new_var == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype))
17225 new_var = relaxed_micromips_32bit_branch_length (fragp, sec, TRUE);
17226 fragp->fr_var = new_var;
17227
17228 return new_var - old_var;
17229 }
17230
252b5132
RH
17231 if (! RELAX_MIPS16_P (fragp->fr_subtype))
17232 return 0;
17233
c4e7957c 17234 if (mips16_extended_frag (fragp, NULL, stretch))
252b5132
RH
17235 {
17236 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
17237 return 0;
17238 fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype);
17239 return 2;
17240 }
17241 else
17242 {
17243 if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
17244 return 0;
17245 fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype);
17246 return -2;
17247 }
17248
17249 return 0;
17250}
17251
17252/* Convert a machine dependent frag. */
17253
17254void
17a2f251 17255md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp)
252b5132 17256{
4a6a3df4
AO
17257 if (RELAX_BRANCH_P (fragp->fr_subtype))
17258 {
4d68580a 17259 char *buf;
4a6a3df4
AO
17260 unsigned long insn;
17261 expressionS exp;
17262 fixS *fixp;
b34976b6 17263
4d68580a
RS
17264 buf = fragp->fr_literal + fragp->fr_fix;
17265 insn = read_insn (buf);
b34976b6 17266
4a6a3df4
AO
17267 if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
17268 {
17269 /* We generate a fixup instead of applying it right now
17270 because, if there are linker relaxations, we're going to
17271 need the relocations. */
17272 exp.X_op = O_symbol;
17273 exp.X_add_symbol = fragp->fr_symbol;
17274 exp.X_add_number = fragp->fr_offset;
17275
4d68580a
RS
17276 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, TRUE,
17277 BFD_RELOC_16_PCREL_S2);
4a6a3df4
AO
17278 fixp->fx_file = fragp->fr_file;
17279 fixp->fx_line = fragp->fr_line;
b34976b6 17280
4d68580a 17281 buf = write_insn (buf, insn);
4a6a3df4
AO
17282 }
17283 else
17284 {
17285 int i;
17286
17287 as_warn_where (fragp->fr_file, fragp->fr_line,
1661c76c 17288 _("relaxed out-of-range branch into a jump"));
4a6a3df4
AO
17289
17290 if (RELAX_BRANCH_UNCOND (fragp->fr_subtype))
17291 goto uncond;
17292
17293 if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype))
17294 {
17295 /* Reverse the branch. */
17296 switch ((insn >> 28) & 0xf)
17297 {
17298 case 4:
56d438b1
CF
17299 if ((insn & 0xff000000) == 0x47000000
17300 || (insn & 0xff600000) == 0x45600000)
17301 {
17302 /* BZ.df/BNZ.df, BZ.V/BNZ.V can have the condition
17303 reversed by tweaking bit 23. */
17304 insn ^= 0x00800000;
17305 }
17306 else
17307 {
17308 /* bc[0-3][tf]l? instructions can have the condition
17309 reversed by tweaking a single TF bit, and their
17310 opcodes all have 0x4???????. */
17311 gas_assert ((insn & 0xf3e00000) == 0x41000000);
17312 insn ^= 0x00010000;
17313 }
4a6a3df4
AO
17314 break;
17315
17316 case 0:
17317 /* bltz 0x04000000 bgez 0x04010000
54f4ddb3 17318 bltzal 0x04100000 bgezal 0x04110000 */
9c2799c2 17319 gas_assert ((insn & 0xfc0e0000) == 0x04000000);
4a6a3df4
AO
17320 insn ^= 0x00010000;
17321 break;
b34976b6 17322
4a6a3df4
AO
17323 case 1:
17324 /* beq 0x10000000 bne 0x14000000
54f4ddb3 17325 blez 0x18000000 bgtz 0x1c000000 */
4a6a3df4
AO
17326 insn ^= 0x04000000;
17327 break;
17328
17329 default:
17330 abort ();
17331 }
17332 }
17333
17334 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
17335 {
17336 /* Clear the and-link bit. */
9c2799c2 17337 gas_assert ((insn & 0xfc1c0000) == 0x04100000);
4a6a3df4 17338
54f4ddb3
TS
17339 /* bltzal 0x04100000 bgezal 0x04110000
17340 bltzall 0x04120000 bgezall 0x04130000 */
4a6a3df4
AO
17341 insn &= ~0x00100000;
17342 }
17343
17344 /* Branch over the branch (if the branch was likely) or the
17345 full jump (not likely case). Compute the offset from the
17346 current instruction to branch to. */
17347 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
17348 i = 16;
17349 else
17350 {
17351 /* How many bytes in instructions we've already emitted? */
4d68580a 17352 i = buf - fragp->fr_literal - fragp->fr_fix;
4a6a3df4
AO
17353 /* How many bytes in instructions from here to the end? */
17354 i = fragp->fr_var - i;
17355 }
17356 /* Convert to instruction count. */
17357 i >>= 2;
17358 /* Branch counts from the next instruction. */
b34976b6 17359 i--;
4a6a3df4
AO
17360 insn |= i;
17361 /* Branch over the jump. */
4d68580a 17362 buf = write_insn (buf, insn);
4a6a3df4 17363
54f4ddb3 17364 /* nop */
4d68580a 17365 buf = write_insn (buf, 0);
4a6a3df4
AO
17366
17367 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
17368 {
17369 /* beql $0, $0, 2f */
17370 insn = 0x50000000;
17371 /* Compute the PC offset from the current instruction to
17372 the end of the variable frag. */
17373 /* How many bytes in instructions we've already emitted? */
4d68580a 17374 i = buf - fragp->fr_literal - fragp->fr_fix;
4a6a3df4
AO
17375 /* How many bytes in instructions from here to the end? */
17376 i = fragp->fr_var - i;
17377 /* Convert to instruction count. */
17378 i >>= 2;
17379 /* Don't decrement i, because we want to branch over the
17380 delay slot. */
4a6a3df4 17381 insn |= i;
4a6a3df4 17382
4d68580a
RS
17383 buf = write_insn (buf, insn);
17384 buf = write_insn (buf, 0);
4a6a3df4
AO
17385 }
17386
17387 uncond:
17388 if (mips_pic == NO_PIC)
17389 {
17390 /* j or jal. */
17391 insn = (RELAX_BRANCH_LINK (fragp->fr_subtype)
17392 ? 0x0c000000 : 0x08000000);
17393 exp.X_op = O_symbol;
17394 exp.X_add_symbol = fragp->fr_symbol;
17395 exp.X_add_number = fragp->fr_offset;
17396
4d68580a
RS
17397 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp,
17398 FALSE, BFD_RELOC_MIPS_JMP);
4a6a3df4
AO
17399 fixp->fx_file = fragp->fr_file;
17400 fixp->fx_line = fragp->fr_line;
17401
4d68580a 17402 buf = write_insn (buf, insn);
4a6a3df4
AO
17403 }
17404 else
17405 {
66b3e8da
MR
17406 unsigned long at = RELAX_BRANCH_AT (fragp->fr_subtype);
17407
4a6a3df4 17408 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
66b3e8da
MR
17409 insn = HAVE_64BIT_ADDRESSES ? 0xdf800000 : 0x8f800000;
17410 insn |= at << OP_SH_RT;
4a6a3df4
AO
17411 exp.X_op = O_symbol;
17412 exp.X_add_symbol = fragp->fr_symbol;
17413 exp.X_add_number = fragp->fr_offset;
17414
17415 if (fragp->fr_offset)
17416 {
17417 exp.X_add_symbol = make_expr_symbol (&exp);
17418 exp.X_add_number = 0;
17419 }
17420
4d68580a
RS
17421 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp,
17422 FALSE, BFD_RELOC_MIPS_GOT16);
4a6a3df4
AO
17423 fixp->fx_file = fragp->fr_file;
17424 fixp->fx_line = fragp->fr_line;
17425
4d68580a 17426 buf = write_insn (buf, insn);
b34976b6 17427
4a6a3df4 17428 if (mips_opts.isa == ISA_MIPS1)
4d68580a
RS
17429 /* nop */
17430 buf = write_insn (buf, 0);
4a6a3df4
AO
17431
17432 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
66b3e8da
MR
17433 insn = HAVE_64BIT_ADDRESSES ? 0x64000000 : 0x24000000;
17434 insn |= at << OP_SH_RS | at << OP_SH_RT;
4a6a3df4 17435
4d68580a
RS
17436 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp,
17437 FALSE, BFD_RELOC_LO16);
4a6a3df4
AO
17438 fixp->fx_file = fragp->fr_file;
17439 fixp->fx_line = fragp->fr_line;
b34976b6 17440
4d68580a 17441 buf = write_insn (buf, insn);
4a6a3df4
AO
17442
17443 /* j(al)r $at. */
17444 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
66b3e8da 17445 insn = 0x0000f809;
4a6a3df4 17446 else
66b3e8da
MR
17447 insn = 0x00000008;
17448 insn |= at << OP_SH_RS;
4a6a3df4 17449
4d68580a 17450 buf = write_insn (buf, insn);
4a6a3df4
AO
17451 }
17452 }
17453
4a6a3df4 17454 fragp->fr_fix += fragp->fr_var;
4d68580a 17455 gas_assert (buf == fragp->fr_literal + fragp->fr_fix);
4a6a3df4
AO
17456 return;
17457 }
17458
df58fc94
RS
17459 /* Relax microMIPS branches. */
17460 if (RELAX_MICROMIPS_P (fragp->fr_subtype))
17461 {
4d68580a 17462 char *buf = fragp->fr_literal + fragp->fr_fix;
df58fc94
RS
17463 bfd_boolean compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype);
17464 bfd_boolean al = RELAX_MICROMIPS_LINK (fragp->fr_subtype);
17465 int type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype);
2309ddf2 17466 bfd_boolean short_ds;
df58fc94
RS
17467 unsigned long insn;
17468 expressionS exp;
17469 fixS *fixp;
17470
17471 exp.X_op = O_symbol;
17472 exp.X_add_symbol = fragp->fr_symbol;
17473 exp.X_add_number = fragp->fr_offset;
17474
17475 fragp->fr_fix += fragp->fr_var;
17476
17477 /* Handle 16-bit branches that fit or are forced to fit. */
17478 if (type != 0 && !RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype))
17479 {
17480 /* We generate a fixup instead of applying it right now,
17481 because if there is linker relaxation, we're going to
17482 need the relocations. */
17483 if (type == 'D')
4d68580a 17484 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 2, &exp, TRUE,
df58fc94
RS
17485 BFD_RELOC_MICROMIPS_10_PCREL_S1);
17486 else if (type == 'E')
4d68580a 17487 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 2, &exp, TRUE,
df58fc94
RS
17488 BFD_RELOC_MICROMIPS_7_PCREL_S1);
17489 else
17490 abort ();
17491
17492 fixp->fx_file = fragp->fr_file;
17493 fixp->fx_line = fragp->fr_line;
17494
17495 /* These relocations can have an addend that won't fit in
17496 2 octets. */
17497 fixp->fx_no_overflow = 1;
17498
17499 return;
17500 }
17501
2309ddf2 17502 /* Handle 32-bit branches that fit or are forced to fit. */
df58fc94
RS
17503 if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)
17504 || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype))
17505 {
17506 /* We generate a fixup instead of applying it right now,
17507 because if there is linker relaxation, we're going to
17508 need the relocations. */
4d68580a
RS
17509 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, TRUE,
17510 BFD_RELOC_MICROMIPS_16_PCREL_S1);
df58fc94
RS
17511 fixp->fx_file = fragp->fr_file;
17512 fixp->fx_line = fragp->fr_line;
17513
17514 if (type == 0)
17515 return;
17516 }
17517
17518 /* Relax 16-bit branches to 32-bit branches. */
17519 if (type != 0)
17520 {
4d68580a 17521 insn = read_compressed_insn (buf, 2);
df58fc94
RS
17522
17523 if ((insn & 0xfc00) == 0xcc00) /* b16 */
17524 insn = 0x94000000; /* beq */
17525 else if ((insn & 0xdc00) == 0x8c00) /* beqz16/bnez16 */
17526 {
17527 unsigned long regno;
17528
17529 regno = (insn >> MICROMIPSOP_SH_MD) & MICROMIPSOP_MASK_MD;
17530 regno = micromips_to_32_reg_d_map [regno];
17531 insn = ((insn & 0x2000) << 16) | 0x94000000; /* beq/bne */
17532 insn |= regno << MICROMIPSOP_SH_RS;
17533 }
17534 else
17535 abort ();
17536
17537 /* Nothing else to do, just write it out. */
17538 if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)
17539 || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype))
17540 {
4d68580a
RS
17541 buf = write_compressed_insn (buf, insn, 4);
17542 gas_assert (buf == fragp->fr_literal + fragp->fr_fix);
df58fc94
RS
17543 return;
17544 }
17545 }
17546 else
4d68580a 17547 insn = read_compressed_insn (buf, 4);
df58fc94
RS
17548
17549 /* Relax 32-bit branches to a sequence of instructions. */
17550 as_warn_where (fragp->fr_file, fragp->fr_line,
1661c76c 17551 _("relaxed out-of-range branch into a jump"));
df58fc94 17552
2309ddf2
MR
17553 /* Set the short-delay-slot bit. */
17554 short_ds = al && (insn & 0x02000000) != 0;
df58fc94
RS
17555
17556 if (!RELAX_MICROMIPS_UNCOND (fragp->fr_subtype))
17557 {
17558 symbolS *l;
17559
17560 /* Reverse the branch. */
17561 if ((insn & 0xfc000000) == 0x94000000 /* beq */
17562 || (insn & 0xfc000000) == 0xb4000000) /* bne */
17563 insn ^= 0x20000000;
17564 else if ((insn & 0xffe00000) == 0x40000000 /* bltz */
17565 || (insn & 0xffe00000) == 0x40400000 /* bgez */
17566 || (insn & 0xffe00000) == 0x40800000 /* blez */
17567 || (insn & 0xffe00000) == 0x40c00000 /* bgtz */
17568 || (insn & 0xffe00000) == 0x40a00000 /* bnezc */
17569 || (insn & 0xffe00000) == 0x40e00000 /* beqzc */
17570 || (insn & 0xffe00000) == 0x40200000 /* bltzal */
17571 || (insn & 0xffe00000) == 0x40600000 /* bgezal */
17572 || (insn & 0xffe00000) == 0x42200000 /* bltzals */
17573 || (insn & 0xffe00000) == 0x42600000) /* bgezals */
17574 insn ^= 0x00400000;
17575 else if ((insn & 0xffe30000) == 0x43800000 /* bc1f */
17576 || (insn & 0xffe30000) == 0x43a00000 /* bc1t */
17577 || (insn & 0xffe30000) == 0x42800000 /* bc2f */
17578 || (insn & 0xffe30000) == 0x42a00000) /* bc2t */
17579 insn ^= 0x00200000;
56d438b1
CF
17580 else if ((insn & 0xff000000) == 0x83000000 /* BZ.df
17581 BNZ.df */
17582 || (insn & 0xff600000) == 0x81600000) /* BZ.V
17583 BNZ.V */
17584 insn ^= 0x00800000;
df58fc94
RS
17585 else
17586 abort ();
17587
17588 if (al)
17589 {
17590 /* Clear the and-link and short-delay-slot bits. */
17591 gas_assert ((insn & 0xfda00000) == 0x40200000);
17592
17593 /* bltzal 0x40200000 bgezal 0x40600000 */
17594 /* bltzals 0x42200000 bgezals 0x42600000 */
17595 insn &= ~0x02200000;
17596 }
17597
17598 /* Make a label at the end for use with the branch. */
17599 l = symbol_new (micromips_label_name (), asec, fragp->fr_fix, fragp);
17600 micromips_label_inc ();
f3ded42a 17601 S_SET_OTHER (l, ELF_ST_SET_MICROMIPS (S_GET_OTHER (l)));
df58fc94
RS
17602
17603 /* Refer to it. */
4d68580a
RS
17604 fixp = fix_new (fragp, buf - fragp->fr_literal, 4, l, 0, TRUE,
17605 BFD_RELOC_MICROMIPS_16_PCREL_S1);
df58fc94
RS
17606 fixp->fx_file = fragp->fr_file;
17607 fixp->fx_line = fragp->fr_line;
17608
17609 /* Branch over the jump. */
4d68580a 17610 buf = write_compressed_insn (buf, insn, 4);
df58fc94 17611 if (!compact)
4d68580a
RS
17612 /* nop */
17613 buf = write_compressed_insn (buf, 0x0c00, 2);
df58fc94
RS
17614 }
17615
17616 if (mips_pic == NO_PIC)
17617 {
2309ddf2
MR
17618 unsigned long jal = short_ds ? 0x74000000 : 0xf4000000; /* jal/s */
17619
df58fc94
RS
17620 /* j/jal/jals <sym> R_MICROMIPS_26_S1 */
17621 insn = al ? jal : 0xd4000000;
17622
4d68580a
RS
17623 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE,
17624 BFD_RELOC_MICROMIPS_JMP);
df58fc94
RS
17625 fixp->fx_file = fragp->fr_file;
17626 fixp->fx_line = fragp->fr_line;
17627
4d68580a 17628 buf = write_compressed_insn (buf, insn, 4);
df58fc94 17629 if (compact)
4d68580a
RS
17630 /* nop */
17631 buf = write_compressed_insn (buf, 0x0c00, 2);
df58fc94
RS
17632 }
17633 else
17634 {
17635 unsigned long at = RELAX_MICROMIPS_AT (fragp->fr_subtype);
2309ddf2
MR
17636 unsigned long jalr = short_ds ? 0x45e0 : 0x45c0; /* jalr/s */
17637 unsigned long jr = compact ? 0x45a0 : 0x4580; /* jr/c */
df58fc94
RS
17638
17639 /* lw/ld $at, <sym>($gp) R_MICROMIPS_GOT16 */
17640 insn = HAVE_64BIT_ADDRESSES ? 0xdc1c0000 : 0xfc1c0000;
17641 insn |= at << MICROMIPSOP_SH_RT;
17642
17643 if (exp.X_add_number)
17644 {
17645 exp.X_add_symbol = make_expr_symbol (&exp);
17646 exp.X_add_number = 0;
17647 }
17648
4d68580a
RS
17649 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE,
17650 BFD_RELOC_MICROMIPS_GOT16);
df58fc94
RS
17651 fixp->fx_file = fragp->fr_file;
17652 fixp->fx_line = fragp->fr_line;
17653
4d68580a 17654 buf = write_compressed_insn (buf, insn, 4);
df58fc94
RS
17655
17656 /* d/addiu $at, $at, <sym> R_MICROMIPS_LO16 */
17657 insn = HAVE_64BIT_ADDRESSES ? 0x5c000000 : 0x30000000;
17658 insn |= at << MICROMIPSOP_SH_RT | at << MICROMIPSOP_SH_RS;
17659
4d68580a
RS
17660 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE,
17661 BFD_RELOC_MICROMIPS_LO16);
df58fc94
RS
17662 fixp->fx_file = fragp->fr_file;
17663 fixp->fx_line = fragp->fr_line;
17664
4d68580a 17665 buf = write_compressed_insn (buf, insn, 4);
df58fc94
RS
17666
17667 /* jr/jrc/jalr/jalrs $at */
17668 insn = al ? jalr : jr;
17669 insn |= at << MICROMIPSOP_SH_MJ;
17670
4d68580a 17671 buf = write_compressed_insn (buf, insn, 2);
df58fc94
RS
17672 }
17673
4d68580a 17674 gas_assert (buf == fragp->fr_literal + fragp->fr_fix);
df58fc94
RS
17675 return;
17676 }
17677
252b5132
RH
17678 if (RELAX_MIPS16_P (fragp->fr_subtype))
17679 {
17680 int type;
3ccad066 17681 const struct mips_int_operand *operand;
252b5132 17682 offsetT val;
5c04167a
RS
17683 char *buf;
17684 unsigned int user_length, length;
252b5132 17685 unsigned long insn;
5c04167a 17686 bfd_boolean ext;
252b5132
RH
17687
17688 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
3ccad066 17689 operand = mips16_immed_operand (type, FALSE);
252b5132 17690
5c04167a 17691 ext = RELAX_MIPS16_EXTENDED (fragp->fr_subtype);
5f5f22c0 17692 val = resolve_symbol_value (fragp->fr_symbol);
3ccad066 17693 if (operand->root.type == OP_PCREL)
252b5132 17694 {
3ccad066 17695 const struct mips_pcrel_operand *pcrel_op;
252b5132
RH
17696 addressT addr;
17697
3ccad066 17698 pcrel_op = (const struct mips_pcrel_operand *) operand;
252b5132
RH
17699 addr = fragp->fr_address + fragp->fr_fix;
17700
17701 /* The rules for the base address of a PC relative reloc are
17702 complicated; see mips16_extended_frag. */
3ccad066 17703 if (pcrel_op->include_isa_bit)
252b5132
RH
17704 {
17705 addr += 2;
17706 if (ext)
17707 addr += 2;
17708 /* Ignore the low bit in the target, since it will be
17709 set for a text label. */
3ccad066 17710 val &= -2;
252b5132
RH
17711 }
17712 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
17713 addr -= 4;
17714 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
17715 addr -= 2;
17716
3ccad066 17717 addr &= -(1 << pcrel_op->align_log2);
252b5132
RH
17718 val -= addr;
17719
17720 /* Make sure the section winds up with the alignment we have
17721 assumed. */
3ccad066
RS
17722 if (operand->shift > 0)
17723 record_alignment (asec, operand->shift);
252b5132
RH
17724 }
17725
17726 if (ext
17727 && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)
17728 || RELAX_MIPS16_DSLOT (fragp->fr_subtype)))
17729 as_warn_where (fragp->fr_file, fragp->fr_line,
17730 _("extended instruction in delay slot"));
17731
5c04167a 17732 buf = fragp->fr_literal + fragp->fr_fix;
252b5132 17733
4d68580a 17734 insn = read_compressed_insn (buf, 2);
5c04167a
RS
17735 if (ext)
17736 insn |= MIPS16_EXTEND;
252b5132 17737
5c04167a
RS
17738 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype))
17739 user_length = 4;
17740 else if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype))
17741 user_length = 2;
17742 else
17743 user_length = 0;
17744
43c0598f 17745 mips16_immed (fragp->fr_file, fragp->fr_line, type,
c150d1d2 17746 BFD_RELOC_UNUSED, val, user_length, &insn);
252b5132 17747
5c04167a
RS
17748 length = (ext ? 4 : 2);
17749 gas_assert (mips16_opcode_length (insn) == length);
17750 write_compressed_insn (buf, insn, length);
17751 fragp->fr_fix += length;
252b5132
RH
17752 }
17753 else
17754 {
df58fc94
RS
17755 relax_substateT subtype = fragp->fr_subtype;
17756 bfd_boolean second_longer = (subtype & RELAX_SECOND_LONGER) != 0;
17757 bfd_boolean use_second = (subtype & RELAX_USE_SECOND) != 0;
4d7206a2
RS
17758 int first, second;
17759 fixS *fixp;
252b5132 17760
df58fc94
RS
17761 first = RELAX_FIRST (subtype);
17762 second = RELAX_SECOND (subtype);
4d7206a2 17763 fixp = (fixS *) fragp->fr_opcode;
252b5132 17764
df58fc94
RS
17765 /* If the delay slot chosen does not match the size of the instruction,
17766 then emit a warning. */
17767 if ((!use_second && (subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0)
17768 || (use_second && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0))
17769 {
17770 relax_substateT s;
17771 const char *msg;
17772
17773 s = subtype & (RELAX_DELAY_SLOT_16BIT
17774 | RELAX_DELAY_SLOT_SIZE_FIRST
17775 | RELAX_DELAY_SLOT_SIZE_SECOND);
17776 msg = macro_warning (s);
17777 if (msg != NULL)
db9b2be4 17778 as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg);
df58fc94
RS
17779 subtype &= ~s;
17780 }
17781
584892a6 17782 /* Possibly emit a warning if we've chosen the longer option. */
df58fc94 17783 if (use_second == second_longer)
584892a6 17784 {
df58fc94
RS
17785 relax_substateT s;
17786 const char *msg;
17787
17788 s = (subtype
17789 & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT));
17790 msg = macro_warning (s);
17791 if (msg != NULL)
db9b2be4 17792 as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg);
df58fc94 17793 subtype &= ~s;
584892a6
RS
17794 }
17795
4d7206a2
RS
17796 /* Go through all the fixups for the first sequence. Disable them
17797 (by marking them as done) if we're going to use the second
17798 sequence instead. */
17799 while (fixp
17800 && fixp->fx_frag == fragp
17801 && fixp->fx_where < fragp->fr_fix - second)
17802 {
df58fc94 17803 if (subtype & RELAX_USE_SECOND)
4d7206a2
RS
17804 fixp->fx_done = 1;
17805 fixp = fixp->fx_next;
17806 }
252b5132 17807
4d7206a2
RS
17808 /* Go through the fixups for the second sequence. Disable them if
17809 we're going to use the first sequence, otherwise adjust their
17810 addresses to account for the relaxation. */
17811 while (fixp && fixp->fx_frag == fragp)
17812 {
df58fc94 17813 if (subtype & RELAX_USE_SECOND)
4d7206a2
RS
17814 fixp->fx_where -= first;
17815 else
17816 fixp->fx_done = 1;
17817 fixp = fixp->fx_next;
17818 }
17819
17820 /* Now modify the frag contents. */
df58fc94 17821 if (subtype & RELAX_USE_SECOND)
4d7206a2
RS
17822 {
17823 char *start;
17824
17825 start = fragp->fr_literal + fragp->fr_fix - first - second;
17826 memmove (start, start + first, second);
17827 fragp->fr_fix -= first;
17828 }
17829 else
17830 fragp->fr_fix -= second;
252b5132
RH
17831 }
17832}
17833
252b5132
RH
17834/* This function is called after the relocs have been generated.
17835 We've been storing mips16 text labels as odd. Here we convert them
17836 back to even for the convenience of the debugger. */
17837
17838void
17a2f251 17839mips_frob_file_after_relocs (void)
252b5132
RH
17840{
17841 asymbol **syms;
17842 unsigned int count, i;
17843
252b5132
RH
17844 syms = bfd_get_outsymbols (stdoutput);
17845 count = bfd_get_symcount (stdoutput);
17846 for (i = 0; i < count; i++, syms++)
df58fc94
RS
17847 if (ELF_ST_IS_COMPRESSED (elf_symbol (*syms)->internal_elf_sym.st_other)
17848 && ((*syms)->value & 1) != 0)
17849 {
17850 (*syms)->value &= ~1;
17851 /* If the symbol has an odd size, it was probably computed
17852 incorrectly, so adjust that as well. */
17853 if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0)
17854 ++elf_symbol (*syms)->internal_elf_sym.st_size;
17855 }
252b5132
RH
17856}
17857
a1facbec
MR
17858/* This function is called whenever a label is defined, including fake
17859 labels instantiated off the dot special symbol. It is used when
17860 handling branch delays; if a branch has a label, we assume we cannot
17861 move it. This also bumps the value of the symbol by 1 in compressed
17862 code. */
252b5132 17863
e1b47bd5 17864static void
a1facbec 17865mips_record_label (symbolS *sym)
252b5132 17866{
a8dbcb85 17867 segment_info_type *si = seg_info (now_seg);
252b5132
RH
17868 struct insn_label_list *l;
17869
17870 if (free_insn_labels == NULL)
17871 l = (struct insn_label_list *) xmalloc (sizeof *l);
17872 else
17873 {
17874 l = free_insn_labels;
17875 free_insn_labels = l->next;
17876 }
17877
17878 l->label = sym;
a8dbcb85
TS
17879 l->next = si->label_list;
17880 si->label_list = l;
a1facbec 17881}
07a53e5c 17882
a1facbec
MR
17883/* This function is called as tc_frob_label() whenever a label is defined
17884 and adds a DWARF-2 record we only want for true labels. */
17885
17886void
17887mips_define_label (symbolS *sym)
17888{
17889 mips_record_label (sym);
07a53e5c 17890 dwarf2_emit_label (sym);
252b5132 17891}
e1b47bd5
RS
17892
17893/* This function is called by tc_new_dot_label whenever a new dot symbol
17894 is defined. */
17895
17896void
17897mips_add_dot_label (symbolS *sym)
17898{
17899 mips_record_label (sym);
17900 if (mips_assembling_insn && HAVE_CODE_COMPRESSION)
17901 mips_compressed_mark_label (sym);
17902}
252b5132 17903\f
351cdf24
MF
17904/* Converting ASE flags from internal to .MIPS.abiflags values. */
17905static unsigned int
17906mips_convert_ase_flags (int ase)
17907{
17908 unsigned int ext_ases = 0;
17909
17910 if (ase & ASE_DSP)
17911 ext_ases |= AFL_ASE_DSP;
17912 if (ase & ASE_DSPR2)
17913 ext_ases |= AFL_ASE_DSPR2;
17914 if (ase & ASE_EVA)
17915 ext_ases |= AFL_ASE_EVA;
17916 if (ase & ASE_MCU)
17917 ext_ases |= AFL_ASE_MCU;
17918 if (ase & ASE_MDMX)
17919 ext_ases |= AFL_ASE_MDMX;
17920 if (ase & ASE_MIPS3D)
17921 ext_ases |= AFL_ASE_MIPS3D;
17922 if (ase & ASE_MT)
17923 ext_ases |= AFL_ASE_MT;
17924 if (ase & ASE_SMARTMIPS)
17925 ext_ases |= AFL_ASE_SMARTMIPS;
17926 if (ase & ASE_VIRT)
17927 ext_ases |= AFL_ASE_VIRT;
17928 if (ase & ASE_MSA)
17929 ext_ases |= AFL_ASE_MSA;
17930 if (ase & ASE_XPA)
17931 ext_ases |= AFL_ASE_XPA;
17932
17933 return ext_ases;
17934}
252b5132
RH
17935/* Some special processing for a MIPS ELF file. */
17936
17937void
17a2f251 17938mips_elf_final_processing (void)
252b5132 17939{
351cdf24
MF
17940 int fpabi;
17941 Elf_Internal_ABIFlags_v0 flags;
17942
17943 flags.version = 0;
17944 flags.isa_rev = 0;
17945 switch (file_mips_opts.isa)
17946 {
17947 case INSN_ISA1:
17948 flags.isa_level = 1;
17949 break;
17950 case INSN_ISA2:
17951 flags.isa_level = 2;
17952 break;
17953 case INSN_ISA3:
17954 flags.isa_level = 3;
17955 break;
17956 case INSN_ISA4:
17957 flags.isa_level = 4;
17958 break;
17959 case INSN_ISA5:
17960 flags.isa_level = 5;
17961 break;
17962 case INSN_ISA32:
17963 flags.isa_level = 32;
17964 flags.isa_rev = 1;
17965 break;
17966 case INSN_ISA32R2:
17967 flags.isa_level = 32;
17968 flags.isa_rev = 2;
17969 break;
17970 case INSN_ISA32R3:
17971 flags.isa_level = 32;
17972 flags.isa_rev = 3;
17973 break;
17974 case INSN_ISA32R5:
17975 flags.isa_level = 32;
17976 flags.isa_rev = 5;
17977 break;
09c14161
MF
17978 case INSN_ISA32R6:
17979 flags.isa_level = 32;
17980 flags.isa_rev = 6;
17981 break;
351cdf24
MF
17982 case INSN_ISA64:
17983 flags.isa_level = 64;
17984 flags.isa_rev = 1;
17985 break;
17986 case INSN_ISA64R2:
17987 flags.isa_level = 64;
17988 flags.isa_rev = 2;
17989 break;
17990 case INSN_ISA64R3:
17991 flags.isa_level = 64;
17992 flags.isa_rev = 3;
17993 break;
17994 case INSN_ISA64R5:
17995 flags.isa_level = 64;
17996 flags.isa_rev = 5;
17997 break;
09c14161
MF
17998 case INSN_ISA64R6:
17999 flags.isa_level = 64;
18000 flags.isa_rev = 6;
18001 break;
351cdf24
MF
18002 }
18003
18004 flags.gpr_size = file_mips_opts.gp == 32 ? AFL_REG_32 : AFL_REG_64;
18005 flags.cpr1_size = file_mips_opts.soft_float ? AFL_REG_NONE
18006 : (file_mips_opts.ase & ASE_MSA) ? AFL_REG_128
18007 : (file_mips_opts.fp == 64) ? AFL_REG_64
18008 : AFL_REG_32;
18009 flags.cpr2_size = AFL_REG_NONE;
18010 flags.fp_abi = bfd_elf_get_obj_attr_int (stdoutput, OBJ_ATTR_GNU,
18011 Tag_GNU_MIPS_ABI_FP);
18012 flags.isa_ext = bfd_mips_isa_ext (stdoutput);
18013 flags.ases = mips_convert_ase_flags (file_mips_opts.ase);
18014 if (file_ase_mips16)
18015 flags.ases |= AFL_ASE_MIPS16;
18016 if (file_ase_micromips)
18017 flags.ases |= AFL_ASE_MICROMIPS;
18018 flags.flags1 = 0;
18019 if ((ISA_HAS_ODD_SINGLE_FPR (file_mips_opts.isa, file_mips_opts.arch)
18020 || file_mips_opts.fp == 64)
18021 && file_mips_opts.oddspreg)
18022 flags.flags1 |= AFL_FLAGS1_ODDSPREG;
18023 flags.flags2 = 0;
18024
18025 bfd_mips_elf_swap_abiflags_v0_out (stdoutput, &flags,
18026 ((Elf_External_ABIFlags_v0 *)
18027 mips_flags_frag));
18028
252b5132 18029 /* Write out the register information. */
316f5878 18030 if (mips_abi != N64_ABI)
252b5132
RH
18031 {
18032 Elf32_RegInfo s;
18033
18034 s.ri_gprmask = mips_gprmask;
18035 s.ri_cprmask[0] = mips_cprmask[0];
18036 s.ri_cprmask[1] = mips_cprmask[1];
18037 s.ri_cprmask[2] = mips_cprmask[2];
18038 s.ri_cprmask[3] = mips_cprmask[3];
18039 /* The gp_value field is set by the MIPS ELF backend. */
18040
18041 bfd_mips_elf32_swap_reginfo_out (stdoutput, &s,
18042 ((Elf32_External_RegInfo *)
18043 mips_regmask_frag));
18044 }
18045 else
18046 {
18047 Elf64_Internal_RegInfo s;
18048
18049 s.ri_gprmask = mips_gprmask;
18050 s.ri_pad = 0;
18051 s.ri_cprmask[0] = mips_cprmask[0];
18052 s.ri_cprmask[1] = mips_cprmask[1];
18053 s.ri_cprmask[2] = mips_cprmask[2];
18054 s.ri_cprmask[3] = mips_cprmask[3];
18055 /* The gp_value field is set by the MIPS ELF backend. */
18056
18057 bfd_mips_elf64_swap_reginfo_out (stdoutput, &s,
18058 ((Elf64_External_RegInfo *)
18059 mips_regmask_frag));
18060 }
18061
18062 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
18063 sort of BFD interface for this. */
18064 if (mips_any_noreorder)
18065 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER;
18066 if (mips_pic != NO_PIC)
143d77c5 18067 {
8b828383 18068 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC;
143d77c5
EC
18069 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
18070 }
18071 if (mips_abicalls)
18072 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
252b5132 18073
b015e599
AP
18074 /* Set MIPS ELF flags for ASEs. Note that not all ASEs have flags
18075 defined at present; this might need to change in future. */
a4672219
TS
18076 if (file_ase_mips16)
18077 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16;
df58fc94
RS
18078 if (file_ase_micromips)
18079 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MICROMIPS;
919731af 18080 if (file_mips_opts.ase & ASE_MDMX)
deec1734 18081 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX;
1f25f5d3 18082
bdaaa2e1 18083 /* Set the MIPS ELF ABI flags. */
316f5878 18084 if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32)
252b5132 18085 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32;
316f5878 18086 else if (mips_abi == O64_ABI)
252b5132 18087 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64;
316f5878 18088 else if (mips_abi == EABI_ABI)
252b5132 18089 {
bad1aba3 18090 if (file_mips_opts.gp == 64)
252b5132
RH
18091 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64;
18092 else
18093 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32;
18094 }
316f5878 18095 else if (mips_abi == N32_ABI)
be00bddd
TS
18096 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2;
18097
c9914766 18098 /* Nothing to do for N64_ABI. */
252b5132
RH
18099
18100 if (mips_32bitmode)
18101 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE;
ad3fea08 18102
7361da2c 18103 if (mips_nan2008 == 1)
ba92f887
MR
18104 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NAN2008;
18105
ad3fea08 18106 /* 32 bit code with 64 bit FP registers. */
351cdf24
MF
18107 fpabi = bfd_elf_get_obj_attr_int (stdoutput, OBJ_ATTR_GNU,
18108 Tag_GNU_MIPS_ABI_FP);
18109 if (fpabi == Val_GNU_MIPS_ABI_FP_OLD_64)
f1c38003 18110 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_FP64;
252b5132 18111}
252b5132 18112\f
beae10d5 18113typedef struct proc {
9b2f1d35
EC
18114 symbolS *func_sym;
18115 symbolS *func_end_sym;
beae10d5
KH
18116 unsigned long reg_mask;
18117 unsigned long reg_offset;
18118 unsigned long fpreg_mask;
18119 unsigned long fpreg_offset;
18120 unsigned long frame_offset;
18121 unsigned long frame_reg;
18122 unsigned long pc_reg;
18123} procS;
252b5132
RH
18124
18125static procS cur_proc;
18126static procS *cur_proc_ptr;
18127static int numprocs;
18128
df58fc94
RS
18129/* Implement NOP_OPCODE. We encode a MIPS16 nop as "1", a microMIPS nop
18130 as "2", and a normal nop as "0". */
18131
18132#define NOP_OPCODE_MIPS 0
18133#define NOP_OPCODE_MIPS16 1
18134#define NOP_OPCODE_MICROMIPS 2
742a56fe
RS
18135
18136char
18137mips_nop_opcode (void)
18138{
df58fc94
RS
18139 if (seg_info (now_seg)->tc_segment_info_data.micromips)
18140 return NOP_OPCODE_MICROMIPS;
18141 else if (seg_info (now_seg)->tc_segment_info_data.mips16)
18142 return NOP_OPCODE_MIPS16;
18143 else
18144 return NOP_OPCODE_MIPS;
742a56fe
RS
18145}
18146
df58fc94
RS
18147/* Fill in an rs_align_code fragment. Unlike elsewhere we want to use
18148 32-bit microMIPS NOPs here (if applicable). */
a19d8eb0 18149
0a9ef439 18150void
17a2f251 18151mips_handle_align (fragS *fragp)
a19d8eb0 18152{
df58fc94 18153 char nop_opcode;
742a56fe 18154 char *p;
c67a084a
NC
18155 int bytes, size, excess;
18156 valueT opcode;
742a56fe 18157
0a9ef439
RH
18158 if (fragp->fr_type != rs_align_code)
18159 return;
18160
742a56fe 18161 p = fragp->fr_literal + fragp->fr_fix;
df58fc94
RS
18162 nop_opcode = *p;
18163 switch (nop_opcode)
a19d8eb0 18164 {
df58fc94
RS
18165 case NOP_OPCODE_MICROMIPS:
18166 opcode = micromips_nop32_insn.insn_opcode;
18167 size = 4;
18168 break;
18169 case NOP_OPCODE_MIPS16:
c67a084a
NC
18170 opcode = mips16_nop_insn.insn_opcode;
18171 size = 2;
df58fc94
RS
18172 break;
18173 case NOP_OPCODE_MIPS:
18174 default:
c67a084a
NC
18175 opcode = nop_insn.insn_opcode;
18176 size = 4;
df58fc94 18177 break;
c67a084a 18178 }
a19d8eb0 18179
c67a084a
NC
18180 bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
18181 excess = bytes % size;
df58fc94
RS
18182
18183 /* Handle the leading part if we're not inserting a whole number of
18184 instructions, and make it the end of the fixed part of the frag.
18185 Try to fit in a short microMIPS NOP if applicable and possible,
18186 and use zeroes otherwise. */
18187 gas_assert (excess < 4);
18188 fragp->fr_fix += excess;
18189 switch (excess)
c67a084a 18190 {
df58fc94
RS
18191 case 3:
18192 *p++ = '\0';
18193 /* Fall through. */
18194 case 2:
833794fc 18195 if (nop_opcode == NOP_OPCODE_MICROMIPS && !mips_opts.insn32)
df58fc94 18196 {
4d68580a 18197 p = write_compressed_insn (p, micromips_nop16_insn.insn_opcode, 2);
df58fc94
RS
18198 break;
18199 }
18200 *p++ = '\0';
18201 /* Fall through. */
18202 case 1:
18203 *p++ = '\0';
18204 /* Fall through. */
18205 case 0:
18206 break;
a19d8eb0 18207 }
c67a084a
NC
18208
18209 md_number_to_chars (p, opcode, size);
18210 fragp->fr_var = size;
a19d8eb0
CP
18211}
18212
252b5132 18213static long
17a2f251 18214get_number (void)
252b5132
RH
18215{
18216 int negative = 0;
18217 long val = 0;
18218
18219 if (*input_line_pointer == '-')
18220 {
18221 ++input_line_pointer;
18222 negative = 1;
18223 }
3882b010 18224 if (!ISDIGIT (*input_line_pointer))
956cd1d6 18225 as_bad (_("expected simple number"));
252b5132
RH
18226 if (input_line_pointer[0] == '0')
18227 {
18228 if (input_line_pointer[1] == 'x')
18229 {
18230 input_line_pointer += 2;
3882b010 18231 while (ISXDIGIT (*input_line_pointer))
252b5132
RH
18232 {
18233 val <<= 4;
18234 val |= hex_value (*input_line_pointer++);
18235 }
18236 return negative ? -val : val;
18237 }
18238 else
18239 {
18240 ++input_line_pointer;
3882b010 18241 while (ISDIGIT (*input_line_pointer))
252b5132
RH
18242 {
18243 val <<= 3;
18244 val |= *input_line_pointer++ - '0';
18245 }
18246 return negative ? -val : val;
18247 }
18248 }
3882b010 18249 if (!ISDIGIT (*input_line_pointer))
252b5132
RH
18250 {
18251 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
18252 *input_line_pointer, *input_line_pointer);
956cd1d6 18253 as_warn (_("invalid number"));
252b5132
RH
18254 return -1;
18255 }
3882b010 18256 while (ISDIGIT (*input_line_pointer))
252b5132
RH
18257 {
18258 val *= 10;
18259 val += *input_line_pointer++ - '0';
18260 }
18261 return negative ? -val : val;
18262}
18263
18264/* The .file directive; just like the usual .file directive, but there
c5dd6aab
DJ
18265 is an initial number which is the ECOFF file index. In the non-ECOFF
18266 case .file implies DWARF-2. */
18267
18268static void
17a2f251 18269s_mips_file (int x ATTRIBUTE_UNUSED)
c5dd6aab 18270{
ecb4347a
DJ
18271 static int first_file_directive = 0;
18272
c5dd6aab
DJ
18273 if (ECOFF_DEBUGGING)
18274 {
18275 get_number ();
18276 s_app_file (0);
18277 }
18278 else
ecb4347a
DJ
18279 {
18280 char *filename;
18281
18282 filename = dwarf2_directive_file (0);
18283
18284 /* Versions of GCC up to 3.1 start files with a ".file"
18285 directive even for stabs output. Make sure that this
18286 ".file" is handled. Note that you need a version of GCC
18287 after 3.1 in order to support DWARF-2 on MIPS. */
18288 if (filename != NULL && ! first_file_directive)
18289 {
18290 (void) new_logical_line (filename, -1);
c04f5787 18291 s_app_file_string (filename, 0);
ecb4347a
DJ
18292 }
18293 first_file_directive = 1;
18294 }
c5dd6aab
DJ
18295}
18296
18297/* The .loc directive, implying DWARF-2. */
252b5132
RH
18298
18299static void
17a2f251 18300s_mips_loc (int x ATTRIBUTE_UNUSED)
252b5132 18301{
c5dd6aab
DJ
18302 if (!ECOFF_DEBUGGING)
18303 dwarf2_directive_loc (0);
252b5132
RH
18304}
18305
252b5132
RH
18306/* The .end directive. */
18307
18308static void
17a2f251 18309s_mips_end (int x ATTRIBUTE_UNUSED)
252b5132
RH
18310{
18311 symbolS *p;
252b5132 18312
7a621144
DJ
18313 /* Following functions need their own .frame and .cprestore directives. */
18314 mips_frame_reg_valid = 0;
18315 mips_cprestore_valid = 0;
18316
252b5132
RH
18317 if (!is_end_of_line[(unsigned char) *input_line_pointer])
18318 {
18319 p = get_symbol ();
18320 demand_empty_rest_of_line ();
18321 }
18322 else
18323 p = NULL;
18324
14949570 18325 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
252b5132
RH
18326 as_warn (_(".end not in text section"));
18327
18328 if (!cur_proc_ptr)
18329 {
1661c76c 18330 as_warn (_(".end directive without a preceding .ent directive"));
252b5132
RH
18331 demand_empty_rest_of_line ();
18332 return;
18333 }
18334
18335 if (p != NULL)
18336 {
9c2799c2 18337 gas_assert (S_GET_NAME (p));
9b2f1d35 18338 if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->func_sym)))
1661c76c 18339 as_warn (_(".end symbol does not match .ent symbol"));
ecb4347a
DJ
18340
18341 if (debug_type == DEBUG_STABS)
18342 stabs_generate_asm_endfunc (S_GET_NAME (p),
18343 S_GET_NAME (p));
252b5132
RH
18344 }
18345 else
18346 as_warn (_(".end directive missing or unknown symbol"));
18347
9b2f1d35
EC
18348 /* Create an expression to calculate the size of the function. */
18349 if (p && cur_proc_ptr)
18350 {
18351 OBJ_SYMFIELD_TYPE *obj = symbol_get_obj (p);
18352 expressionS *exp = xmalloc (sizeof (expressionS));
18353
18354 obj->size = exp;
18355 exp->X_op = O_subtract;
18356 exp->X_add_symbol = symbol_temp_new_now ();
18357 exp->X_op_symbol = p;
18358 exp->X_add_number = 0;
18359
18360 cur_proc_ptr->func_end_sym = exp->X_add_symbol;
18361 }
18362
ecb4347a 18363 /* Generate a .pdr section. */
f3ded42a 18364 if (!ECOFF_DEBUGGING && mips_flag_pdr)
ecb4347a
DJ
18365 {
18366 segT saved_seg = now_seg;
18367 subsegT saved_subseg = now_subseg;
ecb4347a
DJ
18368 expressionS exp;
18369 char *fragp;
252b5132 18370
252b5132 18371#ifdef md_flush_pending_output
ecb4347a 18372 md_flush_pending_output ();
252b5132
RH
18373#endif
18374
9c2799c2 18375 gas_assert (pdr_seg);
ecb4347a 18376 subseg_set (pdr_seg, 0);
252b5132 18377
ecb4347a
DJ
18378 /* Write the symbol. */
18379 exp.X_op = O_symbol;
18380 exp.X_add_symbol = p;
18381 exp.X_add_number = 0;
18382 emit_expr (&exp, 4);
252b5132 18383
ecb4347a 18384 fragp = frag_more (7 * 4);
252b5132 18385
17a2f251
TS
18386 md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4);
18387 md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4);
18388 md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4);
18389 md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4);
18390 md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4);
18391 md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4);
18392 md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4);
252b5132 18393
ecb4347a
DJ
18394 subseg_set (saved_seg, saved_subseg);
18395 }
252b5132
RH
18396
18397 cur_proc_ptr = NULL;
18398}
18399
18400/* The .aent and .ent directives. */
18401
18402static void
17a2f251 18403s_mips_ent (int aent)
252b5132 18404{
252b5132 18405 symbolS *symbolP;
252b5132
RH
18406
18407 symbolP = get_symbol ();
18408 if (*input_line_pointer == ',')
f9419b05 18409 ++input_line_pointer;
252b5132 18410 SKIP_WHITESPACE ();
3882b010 18411 if (ISDIGIT (*input_line_pointer)
d9a62219 18412 || *input_line_pointer == '-')
874e8986 18413 get_number ();
252b5132 18414
14949570 18415 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
1661c76c 18416 as_warn (_(".ent or .aent not in text section"));
252b5132
RH
18417
18418 if (!aent && cur_proc_ptr)
9a41af64 18419 as_warn (_("missing .end"));
252b5132
RH
18420
18421 if (!aent)
18422 {
7a621144
DJ
18423 /* This function needs its own .frame and .cprestore directives. */
18424 mips_frame_reg_valid = 0;
18425 mips_cprestore_valid = 0;
18426
252b5132
RH
18427 cur_proc_ptr = &cur_proc;
18428 memset (cur_proc_ptr, '\0', sizeof (procS));
18429
9b2f1d35 18430 cur_proc_ptr->func_sym = symbolP;
252b5132 18431
f9419b05 18432 ++numprocs;
ecb4347a
DJ
18433
18434 if (debug_type == DEBUG_STABS)
18435 stabs_generate_asm_func (S_GET_NAME (symbolP),
18436 S_GET_NAME (symbolP));
252b5132
RH
18437 }
18438
7c0fc524
MR
18439 symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION;
18440
252b5132
RH
18441 demand_empty_rest_of_line ();
18442}
18443
18444/* The .frame directive. If the mdebug section is present (IRIX 5 native)
bdaaa2e1 18445 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
252b5132 18446 s_mips_frame is used so that we can set the PDR information correctly.
bdaaa2e1 18447 We can't use the ecoff routines because they make reference to the ecoff
252b5132
RH
18448 symbol table (in the mdebug section). */
18449
18450static void
17a2f251 18451s_mips_frame (int ignore ATTRIBUTE_UNUSED)
252b5132 18452{
f3ded42a
RS
18453 if (ECOFF_DEBUGGING)
18454 s_ignore (ignore);
18455 else
ecb4347a
DJ
18456 {
18457 long val;
252b5132 18458
ecb4347a
DJ
18459 if (cur_proc_ptr == (procS *) NULL)
18460 {
18461 as_warn (_(".frame outside of .ent"));
18462 demand_empty_rest_of_line ();
18463 return;
18464 }
252b5132 18465
ecb4347a
DJ
18466 cur_proc_ptr->frame_reg = tc_get_register (1);
18467
18468 SKIP_WHITESPACE ();
18469 if (*input_line_pointer++ != ','
18470 || get_absolute_expression_and_terminator (&val) != ',')
18471 {
1661c76c 18472 as_warn (_("bad .frame directive"));
ecb4347a
DJ
18473 --input_line_pointer;
18474 demand_empty_rest_of_line ();
18475 return;
18476 }
252b5132 18477
ecb4347a
DJ
18478 cur_proc_ptr->frame_offset = val;
18479 cur_proc_ptr->pc_reg = tc_get_register (0);
252b5132 18480
252b5132 18481 demand_empty_rest_of_line ();
252b5132 18482 }
252b5132
RH
18483}
18484
bdaaa2e1
KH
18485/* The .fmask and .mask directives. If the mdebug section is present
18486 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
252b5132 18487 embedded targets, s_mips_mask is used so that we can set the PDR
bdaaa2e1 18488 information correctly. We can't use the ecoff routines because they
252b5132
RH
18489 make reference to the ecoff symbol table (in the mdebug section). */
18490
18491static void
17a2f251 18492s_mips_mask (int reg_type)
252b5132 18493{
f3ded42a
RS
18494 if (ECOFF_DEBUGGING)
18495 s_ignore (reg_type);
18496 else
252b5132 18497 {
ecb4347a 18498 long mask, off;
252b5132 18499
ecb4347a
DJ
18500 if (cur_proc_ptr == (procS *) NULL)
18501 {
18502 as_warn (_(".mask/.fmask outside of .ent"));
18503 demand_empty_rest_of_line ();
18504 return;
18505 }
252b5132 18506
ecb4347a
DJ
18507 if (get_absolute_expression_and_terminator (&mask) != ',')
18508 {
1661c76c 18509 as_warn (_("bad .mask/.fmask directive"));
ecb4347a
DJ
18510 --input_line_pointer;
18511 demand_empty_rest_of_line ();
18512 return;
18513 }
252b5132 18514
ecb4347a
DJ
18515 off = get_absolute_expression ();
18516
18517 if (reg_type == 'F')
18518 {
18519 cur_proc_ptr->fpreg_mask = mask;
18520 cur_proc_ptr->fpreg_offset = off;
18521 }
18522 else
18523 {
18524 cur_proc_ptr->reg_mask = mask;
18525 cur_proc_ptr->reg_offset = off;
18526 }
18527
18528 demand_empty_rest_of_line ();
252b5132 18529 }
252b5132
RH
18530}
18531
316f5878
RS
18532/* A table describing all the processors gas knows about. Names are
18533 matched in the order listed.
e7af610e 18534
316f5878
RS
18535 To ease comparison, please keep this table in the same order as
18536 gcc's mips_cpu_info_table[]. */
e972090a
NC
18537static const struct mips_cpu_info mips_cpu_info_table[] =
18538{
316f5878 18539 /* Entries for generic ISAs */
d16afab6
RS
18540 { "mips1", MIPS_CPU_IS_ISA, 0, ISA_MIPS1, CPU_R3000 },
18541 { "mips2", MIPS_CPU_IS_ISA, 0, ISA_MIPS2, CPU_R6000 },
18542 { "mips3", MIPS_CPU_IS_ISA, 0, ISA_MIPS3, CPU_R4000 },
18543 { "mips4", MIPS_CPU_IS_ISA, 0, ISA_MIPS4, CPU_R8000 },
18544 { "mips5", MIPS_CPU_IS_ISA, 0, ISA_MIPS5, CPU_MIPS5 },
18545 { "mips32", MIPS_CPU_IS_ISA, 0, ISA_MIPS32, CPU_MIPS32 },
18546 { "mips32r2", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
ae52f483
AB
18547 { "mips32r3", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R3, CPU_MIPS32R3 },
18548 { "mips32r5", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R5, CPU_MIPS32R5 },
7361da2c 18549 { "mips32r6", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R6, CPU_MIPS32R6 },
d16afab6
RS
18550 { "mips64", MIPS_CPU_IS_ISA, 0, ISA_MIPS64, CPU_MIPS64 },
18551 { "mips64r2", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R2, CPU_MIPS64R2 },
ae52f483
AB
18552 { "mips64r3", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R3, CPU_MIPS64R3 },
18553 { "mips64r5", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R5, CPU_MIPS64R5 },
7361da2c 18554 { "mips64r6", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R6, CPU_MIPS64R6 },
316f5878
RS
18555
18556 /* MIPS I */
d16afab6
RS
18557 { "r3000", 0, 0, ISA_MIPS1, CPU_R3000 },
18558 { "r2000", 0, 0, ISA_MIPS1, CPU_R3000 },
18559 { "r3900", 0, 0, ISA_MIPS1, CPU_R3900 },
316f5878
RS
18560
18561 /* MIPS II */
d16afab6 18562 { "r6000", 0, 0, ISA_MIPS2, CPU_R6000 },
316f5878
RS
18563
18564 /* MIPS III */
d16afab6
RS
18565 { "r4000", 0, 0, ISA_MIPS3, CPU_R4000 },
18566 { "r4010", 0, 0, ISA_MIPS2, CPU_R4010 },
18567 { "vr4100", 0, 0, ISA_MIPS3, CPU_VR4100 },
18568 { "vr4111", 0, 0, ISA_MIPS3, CPU_R4111 },
18569 { "vr4120", 0, 0, ISA_MIPS3, CPU_VR4120 },
18570 { "vr4130", 0, 0, ISA_MIPS3, CPU_VR4120 },
18571 { "vr4181", 0, 0, ISA_MIPS3, CPU_R4111 },
18572 { "vr4300", 0, 0, ISA_MIPS3, CPU_R4300 },
18573 { "r4400", 0, 0, ISA_MIPS3, CPU_R4400 },
18574 { "r4600", 0, 0, ISA_MIPS3, CPU_R4600 },
18575 { "orion", 0, 0, ISA_MIPS3, CPU_R4600 },
18576 { "r4650", 0, 0, ISA_MIPS3, CPU_R4650 },
18577 { "r5900", 0, 0, ISA_MIPS3, CPU_R5900 },
b15591bb 18578 /* ST Microelectronics Loongson 2E and 2F cores */
d16afab6
RS
18579 { "loongson2e", 0, 0, ISA_MIPS3, CPU_LOONGSON_2E },
18580 { "loongson2f", 0, 0, ISA_MIPS3, CPU_LOONGSON_2F },
316f5878
RS
18581
18582 /* MIPS IV */
d16afab6
RS
18583 { "r8000", 0, 0, ISA_MIPS4, CPU_R8000 },
18584 { "r10000", 0, 0, ISA_MIPS4, CPU_R10000 },
18585 { "r12000", 0, 0, ISA_MIPS4, CPU_R12000 },
18586 { "r14000", 0, 0, ISA_MIPS4, CPU_R14000 },
18587 { "r16000", 0, 0, ISA_MIPS4, CPU_R16000 },
18588 { "vr5000", 0, 0, ISA_MIPS4, CPU_R5000 },
18589 { "vr5400", 0, 0, ISA_MIPS4, CPU_VR5400 },
18590 { "vr5500", 0, 0, ISA_MIPS4, CPU_VR5500 },
18591 { "rm5200", 0, 0, ISA_MIPS4, CPU_R5000 },
18592 { "rm5230", 0, 0, ISA_MIPS4, CPU_R5000 },
18593 { "rm5231", 0, 0, ISA_MIPS4, CPU_R5000 },
18594 { "rm5261", 0, 0, ISA_MIPS4, CPU_R5000 },
18595 { "rm5721", 0, 0, ISA_MIPS4, CPU_R5000 },
18596 { "rm7000", 0, 0, ISA_MIPS4, CPU_RM7000 },
18597 { "rm9000", 0, 0, ISA_MIPS4, CPU_RM9000 },
316f5878
RS
18598
18599 /* MIPS 32 */
d16afab6
RS
18600 { "4kc", 0, 0, ISA_MIPS32, CPU_MIPS32 },
18601 { "4km", 0, 0, ISA_MIPS32, CPU_MIPS32 },
18602 { "4kp", 0, 0, ISA_MIPS32, CPU_MIPS32 },
18603 { "4ksc", 0, ASE_SMARTMIPS, ISA_MIPS32, CPU_MIPS32 },
ad3fea08
TS
18604
18605 /* MIPS 32 Release 2 */
d16afab6
RS
18606 { "4kec", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
18607 { "4kem", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
18608 { "4kep", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
18609 { "4ksd", 0, ASE_SMARTMIPS, ISA_MIPS32R2, CPU_MIPS32R2 },
18610 { "m4k", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
18611 { "m4kp", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
18612 { "m14k", 0, ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 },
18613 { "m14kc", 0, ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 },
18614 { "m14ke", 0, ASE_DSP | ASE_DSPR2 | ASE_MCU,
18615 ISA_MIPS32R2, CPU_MIPS32R2 },
18616 { "m14kec", 0, ASE_DSP | ASE_DSPR2 | ASE_MCU,
18617 ISA_MIPS32R2, CPU_MIPS32R2 },
18618 { "24kc", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
18619 { "24kf2_1", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
18620 { "24kf", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
18621 { "24kf1_1", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
0fdf1951 18622 /* Deprecated forms of the above. */
d16afab6
RS
18623 { "24kfx", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
18624 { "24kx", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
01fd108f 18625 /* 24KE is a 24K with DSP ASE, other ASEs are optional. */
d16afab6
RS
18626 { "24kec", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
18627 { "24kef2_1", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
18628 { "24kef", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
18629 { "24kef1_1", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
0fdf1951 18630 /* Deprecated forms of the above. */
d16afab6
RS
18631 { "24kefx", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
18632 { "24kex", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
01fd108f 18633 /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */
d16afab6
RS
18634 { "34kc", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
18635 { "34kf2_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
18636 { "34kf", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
18637 { "34kf1_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
0fdf1951 18638 /* Deprecated forms of the above. */
d16afab6
RS
18639 { "34kfx", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
18640 { "34kx", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
711eefe4 18641 /* 34Kn is a 34kc without DSP. */
d16afab6 18642 { "34kn", 0, ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
01fd108f 18643 /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */
d16afab6
RS
18644 { "74kc", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
18645 { "74kf2_1", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
18646 { "74kf", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
18647 { "74kf1_1", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
18648 { "74kf3_2", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
0fdf1951 18649 /* Deprecated forms of the above. */
d16afab6
RS
18650 { "74kfx", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
18651 { "74kx", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
30f8113a 18652 /* 1004K cores are multiprocessor versions of the 34K. */
d16afab6
RS
18653 { "1004kc", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
18654 { "1004kf2_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
18655 { "1004kf", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
18656 { "1004kf1_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
bbaa46c0 18657 /* P5600 with EVA and Virtualization ASEs, other ASEs are optional. */
ae52f483 18658 { "p5600", 0, ASE_VIRT | ASE_EVA | ASE_XPA, ISA_MIPS32R5, CPU_MIPS32R5 },
32b26a03 18659
316f5878 18660 /* MIPS 64 */
d16afab6
RS
18661 { "5kc", 0, 0, ISA_MIPS64, CPU_MIPS64 },
18662 { "5kf", 0, 0, ISA_MIPS64, CPU_MIPS64 },
18663 { "20kc", 0, ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 },
18664 { "25kf", 0, ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 },
ad3fea08 18665
c7a23324 18666 /* Broadcom SB-1 CPU core */
d16afab6 18667 { "sb1", 0, ASE_MIPS3D | ASE_MDMX, ISA_MIPS64, CPU_SB1 },
1e85aad8 18668 /* Broadcom SB-1A CPU core */
d16afab6 18669 { "sb1a", 0, ASE_MIPS3D | ASE_MDMX, ISA_MIPS64, CPU_SB1 },
d051516a 18670
4ba154f5 18671 { "loongson3a", 0, 0, ISA_MIPS64R2, CPU_LOONGSON_3A },
e7af610e 18672
ed163775
MR
18673 /* MIPS 64 Release 2 */
18674
967344c6 18675 /* Cavium Networks Octeon CPU core */
d16afab6
RS
18676 { "octeon", 0, 0, ISA_MIPS64R2, CPU_OCTEON },
18677 { "octeon+", 0, 0, ISA_MIPS64R2, CPU_OCTEONP },
18678 { "octeon2", 0, 0, ISA_MIPS64R2, CPU_OCTEON2 },
2c629856 18679 { "octeon3", 0, ASE_VIRT | ASE_VIRT64, ISA_MIPS64R5, CPU_OCTEON3 },
967344c6 18680
52b6b6b9 18681 /* RMI Xlr */
d16afab6 18682 { "xlr", 0, 0, ISA_MIPS64, CPU_XLR },
52b6b6b9 18683
55a36193
MK
18684 /* Broadcom XLP.
18685 XLP is mostly like XLR, with the prominent exception that it is
18686 MIPS64R2 rather than MIPS64. */
d16afab6 18687 { "xlp", 0, 0, ISA_MIPS64R2, CPU_XLR },
55a36193 18688
316f5878 18689 /* End marker */
d16afab6 18690 { NULL, 0, 0, 0, 0 }
316f5878 18691};
e7af610e 18692
84ea6cf2 18693
316f5878
RS
18694/* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
18695 with a final "000" replaced by "k". Ignore case.
e7af610e 18696
316f5878 18697 Note: this function is shared between GCC and GAS. */
c6c98b38 18698
b34976b6 18699static bfd_boolean
17a2f251 18700mips_strict_matching_cpu_name_p (const char *canonical, const char *given)
316f5878
RS
18701{
18702 while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical))
18703 given++, canonical++;
18704
18705 return ((*given == 0 && *canonical == 0)
18706 || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0));
18707}
18708
18709
18710/* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
18711 CPU name. We've traditionally allowed a lot of variation here.
18712
18713 Note: this function is shared between GCC and GAS. */
18714
b34976b6 18715static bfd_boolean
17a2f251 18716mips_matching_cpu_name_p (const char *canonical, const char *given)
316f5878
RS
18717{
18718 /* First see if the name matches exactly, or with a final "000"
18719 turned into "k". */
18720 if (mips_strict_matching_cpu_name_p (canonical, given))
b34976b6 18721 return TRUE;
316f5878
RS
18722
18723 /* If not, try comparing based on numerical designation alone.
18724 See if GIVEN is an unadorned number, or 'r' followed by a number. */
18725 if (TOLOWER (*given) == 'r')
18726 given++;
18727 if (!ISDIGIT (*given))
b34976b6 18728 return FALSE;
316f5878
RS
18729
18730 /* Skip over some well-known prefixes in the canonical name,
18731 hoping to find a number there too. */
18732 if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r')
18733 canonical += 2;
18734 else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm')
18735 canonical += 2;
18736 else if (TOLOWER (canonical[0]) == 'r')
18737 canonical += 1;
18738
18739 return mips_strict_matching_cpu_name_p (canonical, given);
18740}
18741
18742
18743/* Parse an option that takes the name of a processor as its argument.
18744 OPTION is the name of the option and CPU_STRING is the argument.
18745 Return the corresponding processor enumeration if the CPU_STRING is
18746 recognized, otherwise report an error and return null.
18747
18748 A similar function exists in GCC. */
e7af610e
NC
18749
18750static const struct mips_cpu_info *
17a2f251 18751mips_parse_cpu (const char *option, const char *cpu_string)
e7af610e 18752{
316f5878 18753 const struct mips_cpu_info *p;
e7af610e 18754
316f5878
RS
18755 /* 'from-abi' selects the most compatible architecture for the given
18756 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
18757 EABIs, we have to decide whether we're using the 32-bit or 64-bit
18758 version. Look first at the -mgp options, if given, otherwise base
18759 the choice on MIPS_DEFAULT_64BIT.
e7af610e 18760
316f5878
RS
18761 Treat NO_ABI like the EABIs. One reason to do this is that the
18762 plain 'mips' and 'mips64' configs have 'from-abi' as their default
18763 architecture. This code picks MIPS I for 'mips' and MIPS III for
18764 'mips64', just as we did in the days before 'from-abi'. */
18765 if (strcasecmp (cpu_string, "from-abi") == 0)
18766 {
18767 if (ABI_NEEDS_32BIT_REGS (mips_abi))
18768 return mips_cpu_info_from_isa (ISA_MIPS1);
18769
18770 if (ABI_NEEDS_64BIT_REGS (mips_abi))
18771 return mips_cpu_info_from_isa (ISA_MIPS3);
18772
bad1aba3 18773 if (file_mips_opts.gp >= 0)
18774 return mips_cpu_info_from_isa (file_mips_opts.gp == 32
0b35dfee 18775 ? ISA_MIPS1 : ISA_MIPS3);
316f5878
RS
18776
18777 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
18778 ? ISA_MIPS3
18779 : ISA_MIPS1);
18780 }
18781
18782 /* 'default' has traditionally been a no-op. Probably not very useful. */
18783 if (strcasecmp (cpu_string, "default") == 0)
18784 return 0;
18785
18786 for (p = mips_cpu_info_table; p->name != 0; p++)
18787 if (mips_matching_cpu_name_p (p->name, cpu_string))
18788 return p;
18789
1661c76c 18790 as_bad (_("bad value (%s) for %s"), cpu_string, option);
316f5878 18791 return 0;
e7af610e
NC
18792}
18793
316f5878
RS
18794/* Return the canonical processor information for ISA (a member of the
18795 ISA_MIPS* enumeration). */
18796
e7af610e 18797static const struct mips_cpu_info *
17a2f251 18798mips_cpu_info_from_isa (int isa)
e7af610e
NC
18799{
18800 int i;
18801
18802 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
ad3fea08 18803 if ((mips_cpu_info_table[i].flags & MIPS_CPU_IS_ISA)
316f5878 18804 && isa == mips_cpu_info_table[i].isa)
e7af610e
NC
18805 return (&mips_cpu_info_table[i]);
18806
e972090a 18807 return NULL;
e7af610e 18808}
fef14a42
TS
18809
18810static const struct mips_cpu_info *
17a2f251 18811mips_cpu_info_from_arch (int arch)
fef14a42
TS
18812{
18813 int i;
18814
18815 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
18816 if (arch == mips_cpu_info_table[i].cpu)
18817 return (&mips_cpu_info_table[i]);
18818
18819 return NULL;
18820}
316f5878
RS
18821\f
18822static void
17a2f251 18823show (FILE *stream, const char *string, int *col_p, int *first_p)
316f5878
RS
18824{
18825 if (*first_p)
18826 {
18827 fprintf (stream, "%24s", "");
18828 *col_p = 24;
18829 }
18830 else
18831 {
18832 fprintf (stream, ", ");
18833 *col_p += 2;
18834 }
e7af610e 18835
316f5878
RS
18836 if (*col_p + strlen (string) > 72)
18837 {
18838 fprintf (stream, "\n%24s", "");
18839 *col_p = 24;
18840 }
18841
18842 fprintf (stream, "%s", string);
18843 *col_p += strlen (string);
18844
18845 *first_p = 0;
18846}
18847
18848void
17a2f251 18849md_show_usage (FILE *stream)
e7af610e 18850{
316f5878
RS
18851 int column, first;
18852 size_t i;
18853
18854 fprintf (stream, _("\
18855MIPS options:\n\
316f5878
RS
18856-EB generate big endian output\n\
18857-EL generate little endian output\n\
18858-g, -g2 do not remove unneeded NOPs or swap branches\n\
18859-G NUM allow referencing objects up to NUM bytes\n\
18860 implicitly with the gp register [default 8]\n"));
18861 fprintf (stream, _("\
18862-mips1 generate MIPS ISA I instructions\n\
18863-mips2 generate MIPS ISA II instructions\n\
18864-mips3 generate MIPS ISA III instructions\n\
18865-mips4 generate MIPS ISA IV instructions\n\
18866-mips5 generate MIPS ISA V instructions\n\
18867-mips32 generate MIPS32 ISA instructions\n\
af7ee8bf 18868-mips32r2 generate MIPS32 release 2 ISA instructions\n\
ae52f483
AB
18869-mips32r3 generate MIPS32 release 3 ISA instructions\n\
18870-mips32r5 generate MIPS32 release 5 ISA instructions\n\
7361da2c 18871-mips32r6 generate MIPS32 release 6 ISA instructions\n\
316f5878 18872-mips64 generate MIPS64 ISA instructions\n\
5f74bc13 18873-mips64r2 generate MIPS64 release 2 ISA instructions\n\
ae52f483
AB
18874-mips64r3 generate MIPS64 release 3 ISA instructions\n\
18875-mips64r5 generate MIPS64 release 5 ISA instructions\n\
7361da2c 18876-mips64r6 generate MIPS64 release 6 ISA instructions\n\
316f5878
RS
18877-march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
18878
18879 first = 1;
e7af610e
NC
18880
18881 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
316f5878
RS
18882 show (stream, mips_cpu_info_table[i].name, &column, &first);
18883 show (stream, "from-abi", &column, &first);
18884 fputc ('\n', stream);
e7af610e 18885
316f5878
RS
18886 fprintf (stream, _("\
18887-mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
18888-no-mCPU don't generate code specific to CPU.\n\
18889 For -mCPU and -no-mCPU, CPU must be one of:\n"));
18890
18891 first = 1;
18892
18893 show (stream, "3900", &column, &first);
18894 show (stream, "4010", &column, &first);
18895 show (stream, "4100", &column, &first);
18896 show (stream, "4650", &column, &first);
18897 fputc ('\n', stream);
18898
18899 fprintf (stream, _("\
18900-mips16 generate mips16 instructions\n\
18901-no-mips16 do not generate mips16 instructions\n"));
18902 fprintf (stream, _("\
df58fc94
RS
18903-mmicromips generate microMIPS instructions\n\
18904-mno-micromips do not generate microMIPS instructions\n"));
18905 fprintf (stream, _("\
e16bfa71
TS
18906-msmartmips generate smartmips instructions\n\
18907-mno-smartmips do not generate smartmips instructions\n"));
18908 fprintf (stream, _("\
74cd071d
CF
18909-mdsp generate DSP instructions\n\
18910-mno-dsp do not generate DSP instructions\n"));
18911 fprintf (stream, _("\
8b082fb1
TS
18912-mdspr2 generate DSP R2 instructions\n\
18913-mno-dspr2 do not generate DSP R2 instructions\n"));
18914 fprintf (stream, _("\
ef2e4d86
CF
18915-mmt generate MT instructions\n\
18916-mno-mt do not generate MT instructions\n"));
18917 fprintf (stream, _("\
dec0624d
MR
18918-mmcu generate MCU instructions\n\
18919-mno-mcu do not generate MCU instructions\n"));
18920 fprintf (stream, _("\
56d438b1
CF
18921-mmsa generate MSA instructions\n\
18922-mno-msa do not generate MSA instructions\n"));
18923 fprintf (stream, _("\
7d64c587
AB
18924-mxpa generate eXtended Physical Address (XPA) instructions\n\
18925-mno-xpa do not generate eXtended Physical Address (XPA) instructions\n"));
18926 fprintf (stream, _("\
b015e599
AP
18927-mvirt generate Virtualization instructions\n\
18928-mno-virt do not generate Virtualization instructions\n"));
18929 fprintf (stream, _("\
833794fc
MR
18930-minsn32 only generate 32-bit microMIPS instructions\n\
18931-mno-insn32 generate all microMIPS instructions\n"));
18932 fprintf (stream, _("\
c67a084a
NC
18933-mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\
18934-mfix-loongson2f-nop work around Loongson2F NOP errata\n\
d766e8ec 18935-mfix-vr4120 work around certain VR4120 errata\n\
7d8e00cf 18936-mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
6a32d874 18937-mfix-24k insert a nop after ERET and DERET instructions\n\
d954098f 18938-mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\
316f5878
RS
18939-mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
18940-mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
aed1a261 18941-msym32 assume all symbols have 32-bit values\n\
316f5878
RS
18942-O0 remove unneeded NOPs, do not swap branches\n\
18943-O remove unneeded NOPs and swap branches\n\
316f5878
RS
18944--trap, --no-break trap exception on div by 0 and mult overflow\n\
18945--break, --no-trap break exception on div by 0 and mult overflow\n"));
037b32b9
AN
18946 fprintf (stream, _("\
18947-mhard-float allow floating-point instructions\n\
18948-msoft-float do not allow floating-point instructions\n\
18949-msingle-float only allow 32-bit floating-point operations\n\
18950-mdouble-float allow 32-bit and 64-bit floating-point operations\n\
3bf0dbfb 18951--[no-]construct-floats [dis]allow floating point values to be constructed\n\
ba92f887
MR
18952--[no-]relax-branch [dis]allow out-of-range branches to be relaxed\n\
18953-mnan=ENCODING select an IEEE 754 NaN encoding convention, either of:\n"));
18954
18955 first = 1;
18956
18957 show (stream, "legacy", &column, &first);
18958 show (stream, "2008", &column, &first);
18959
18960 fputc ('\n', stream);
18961
316f5878
RS
18962 fprintf (stream, _("\
18963-KPIC, -call_shared generate SVR4 position independent code\n\
861fb55a 18964-call_nonpic generate non-PIC code that can operate with DSOs\n\
0c000745 18965-mvxworks-pic generate VxWorks position independent code\n\
861fb55a 18966-non_shared do not generate code that can operate with DSOs\n\
316f5878 18967-xgot assume a 32 bit GOT\n\
dcd410fe 18968-mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
bbe506e8 18969-mshared, -mno-shared disable/enable .cpload optimization for\n\
d821e36b 18970 position dependent (non shared) code\n\
316f5878
RS
18971-mabi=ABI create ABI conformant object file for:\n"));
18972
18973 first = 1;
18974
18975 show (stream, "32", &column, &first);
18976 show (stream, "o64", &column, &first);
18977 show (stream, "n32", &column, &first);
18978 show (stream, "64", &column, &first);
18979 show (stream, "eabi", &column, &first);
18980
18981 fputc ('\n', stream);
18982
18983 fprintf (stream, _("\
18984-32 create o32 ABI object file (default)\n\
18985-n32 create n32 ABI object file\n\
18986-64 create 64 ABI object file\n"));
e7af610e 18987}
14e777e0 18988
1575952e 18989#ifdef TE_IRIX
14e777e0 18990enum dwarf2_format
413a266c 18991mips_dwarf2_format (asection *sec ATTRIBUTE_UNUSED)
14e777e0 18992{
369943fe 18993 if (HAVE_64BIT_SYMBOLS)
1575952e 18994 return dwarf2_format_64bit_irix;
14e777e0
KB
18995 else
18996 return dwarf2_format_32bit;
18997}
1575952e 18998#endif
73369e65
EC
18999
19000int
19001mips_dwarf2_addr_size (void)
19002{
6b6b3450 19003 if (HAVE_64BIT_OBJECTS)
73369e65 19004 return 8;
73369e65
EC
19005 else
19006 return 4;
19007}
5862107c
EC
19008
19009/* Standard calling conventions leave the CFA at SP on entry. */
19010void
19011mips_cfi_frame_initial_instructions (void)
19012{
19013 cfi_add_CFA_def_cfa_register (SP);
19014}
19015
707bfff6
TS
19016int
19017tc_mips_regname_to_dw2regnum (char *regname)
19018{
19019 unsigned int regnum = -1;
19020 unsigned int reg;
19021
19022 if (reg_lookup (&regname, RTYPE_GP | RTYPE_NUM, &reg))
19023 regnum = reg;
19024
19025 return regnum;
19026}
263b2574 19027
19028/* Implement CONVERT_SYMBOLIC_ATTRIBUTE.
19029 Given a symbolic attribute NAME, return the proper integer value.
19030 Returns -1 if the attribute is not known. */
19031
19032int
19033mips_convert_symbolic_attribute (const char *name)
19034{
19035 static const struct
19036 {
19037 const char * name;
19038 const int tag;
19039 }
19040 attribute_table[] =
19041 {
19042#define T(tag) {#tag, tag}
19043 T (Tag_GNU_MIPS_ABI_FP),
19044 T (Tag_GNU_MIPS_ABI_MSA),
19045#undef T
19046 };
19047 unsigned int i;
19048
19049 if (name == NULL)
19050 return -1;
19051
19052 for (i = 0; i < ARRAY_SIZE (attribute_table); i++)
19053 if (streq (name, attribute_table[i].name))
19054 return attribute_table[i].tag;
19055
19056 return -1;
19057}
fd5c94ab
RS
19058
19059void
19060md_mips_end (void)
19061{
351cdf24
MF
19062 int fpabi = Val_GNU_MIPS_ABI_FP_ANY;
19063
fd5c94ab
RS
19064 mips_emit_delays ();
19065 if (cur_proc_ptr)
19066 as_warn (_("missing .end at end of assembly"));
919731af 19067
19068 /* Just in case no code was emitted, do the consistency check. */
19069 file_mips_check_options ();
351cdf24
MF
19070
19071 /* Set a floating-point ABI if the user did not. */
19072 if (obj_elf_seen_attribute (OBJ_ATTR_GNU, Tag_GNU_MIPS_ABI_FP))
19073 {
19074 /* Perform consistency checks on the floating-point ABI. */
19075 fpabi = bfd_elf_get_obj_attr_int (stdoutput, OBJ_ATTR_GNU,
19076 Tag_GNU_MIPS_ABI_FP);
19077 if (fpabi != Val_GNU_MIPS_ABI_FP_ANY)
19078 check_fpabi (fpabi);
19079 }
19080 else
19081 {
19082 /* Soft-float gets precedence over single-float, the two options should
19083 not be used together so this should not matter. */
19084 if (file_mips_opts.soft_float == 1)
19085 fpabi = Val_GNU_MIPS_ABI_FP_SOFT;
19086 /* Single-float gets precedence over all double_float cases. */
19087 else if (file_mips_opts.single_float == 1)
19088 fpabi = Val_GNU_MIPS_ABI_FP_SINGLE;
19089 else
19090 {
19091 switch (file_mips_opts.fp)
19092 {
19093 case 32:
19094 if (file_mips_opts.gp == 32)
19095 fpabi = Val_GNU_MIPS_ABI_FP_DOUBLE;
19096 break;
19097 case 0:
19098 fpabi = Val_GNU_MIPS_ABI_FP_XX;
19099 break;
19100 case 64:
19101 if (file_mips_opts.gp == 32 && !file_mips_opts.oddspreg)
19102 fpabi = Val_GNU_MIPS_ABI_FP_64A;
19103 else if (file_mips_opts.gp == 32)
19104 fpabi = Val_GNU_MIPS_ABI_FP_64;
19105 else
19106 fpabi = Val_GNU_MIPS_ABI_FP_DOUBLE;
19107 break;
19108 }
19109 }
19110
19111 bfd_elf_add_obj_attr_int (stdoutput, OBJ_ATTR_GNU,
19112 Tag_GNU_MIPS_ABI_FP, fpabi);
19113 }
fd5c94ab 19114}
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