Commit | Line | Data |
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252b5132 | 1 | /* tc-mips.c -- assemble code for a MIPS chip. |
f7e42eb4 | 2 | Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001 |
82efde3a | 3 | Free Software Foundation, Inc. |
252b5132 RH |
4 | Contributed by the OSF and Ralph Campbell. |
5 | Written by Keith Knowles and Ralph Campbell, working independently. | |
6 | Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus | |
7 | Support. | |
8 | ||
9 | This file is part of GAS. | |
10 | ||
11 | GAS is free software; you can redistribute it and/or modify | |
12 | it under the terms of the GNU General Public License as published by | |
13 | the Free Software Foundation; either version 2, or (at your option) | |
14 | any later version. | |
15 | ||
16 | GAS is distributed in the hope that it will be useful, | |
17 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | GNU General Public License for more details. | |
20 | ||
21 | You should have received a copy of the GNU General Public License | |
22 | along with GAS; see the file COPYING. If not, write to the Free | |
23 | Software Foundation, 59 Temple Place - Suite 330, Boston, MA | |
24 | 02111-1307, USA. */ | |
25 | ||
26 | #include "as.h" | |
27 | #include "config.h" | |
28 | #include "subsegs.h" | |
29 | ||
30 | #include <ctype.h> | |
31 | ||
32 | #ifdef USE_STDARG | |
33 | #include <stdarg.h> | |
34 | #endif | |
35 | #ifdef USE_VARARGS | |
36 | #include <varargs.h> | |
37 | #endif | |
38 | ||
39 | #include "opcode/mips.h" | |
40 | #include "itbl-ops.h" | |
41 | ||
42 | #ifdef DEBUG | |
43 | #define DBG(x) printf x | |
44 | #else | |
45 | #define DBG(x) | |
46 | #endif | |
47 | ||
48 | #ifdef OBJ_MAYBE_ELF | |
49 | /* Clean up namespace so we can include obj-elf.h too. */ | |
50 | static int mips_output_flavor PARAMS ((void)); | |
51 | static int mips_output_flavor () { return OUTPUT_FLAVOR; } | |
52 | #undef OBJ_PROCESS_STAB | |
53 | #undef OUTPUT_FLAVOR | |
54 | #undef S_GET_ALIGN | |
55 | #undef S_GET_SIZE | |
56 | #undef S_SET_ALIGN | |
57 | #undef S_SET_SIZE | |
252b5132 RH |
58 | #undef obj_frob_file |
59 | #undef obj_frob_file_after_relocs | |
60 | #undef obj_frob_symbol | |
61 | #undef obj_pop_insert | |
62 | #undef obj_sec_sym_ok_for_reloc | |
63 | #undef OBJ_COPY_SYMBOL_ATTRIBUTES | |
64 | ||
65 | #include "obj-elf.h" | |
66 | /* Fix any of them that we actually care about. */ | |
67 | #undef OUTPUT_FLAVOR | |
68 | #define OUTPUT_FLAVOR mips_output_flavor() | |
69 | #endif | |
70 | ||
71 | #if defined (OBJ_ELF) | |
72 | #include "elf/mips.h" | |
73 | #endif | |
74 | ||
75 | #ifndef ECOFF_DEBUGGING | |
76 | #define NO_ECOFF_DEBUGGING | |
77 | #define ECOFF_DEBUGGING 0 | |
78 | #endif | |
79 | ||
80 | #include "ecoff.h" | |
81 | ||
82 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
83 | static char *mips_regmask_frag; | |
84 | #endif | |
85 | ||
86 | #define AT 1 | |
87 | #define TREG 24 | |
88 | #define PIC_CALL_REG 25 | |
89 | #define KT0 26 | |
90 | #define KT1 27 | |
91 | #define GP 28 | |
92 | #define SP 29 | |
93 | #define FP 30 | |
94 | #define RA 31 | |
95 | ||
96 | #define ILLEGAL_REG (32) | |
97 | ||
98 | /* Allow override of standard little-endian ECOFF format. */ | |
99 | ||
100 | #ifndef ECOFF_LITTLE_FORMAT | |
101 | #define ECOFF_LITTLE_FORMAT "ecoff-littlemips" | |
102 | #endif | |
103 | ||
104 | extern int target_big_endian; | |
105 | ||
106 | /* 1 is we should use the 64 bit MIPS ELF ABI, 0 if we should use the | |
107 | 32 bit ABI. This has no meaning for ECOFF. | |
108 | Note that the default is always 32 bit, even if "configured" for | |
109 | 64 bit [e.g. --target=mips64-elf]. */ | |
110 | static int mips_64; | |
111 | ||
112 | /* The default target format to use. */ | |
beae10d5 | 113 | |
252b5132 RH |
114 | const char * |
115 | mips_target_format () | |
116 | { | |
117 | switch (OUTPUT_FLAVOR) | |
118 | { | |
119 | case bfd_target_aout_flavour: | |
120 | return target_big_endian ? "a.out-mips-big" : "a.out-mips-little"; | |
121 | case bfd_target_ecoff_flavour: | |
122 | return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT; | |
056350c6 NC |
123 | case bfd_target_coff_flavour: |
124 | return "pe-mips"; | |
252b5132 | 125 | case bfd_target_elf_flavour: |
8614eeee UC |
126 | #ifdef TE_TMIPS |
127 | /* This is traditional mips */ | |
128 | return (target_big_endian | |
af9539e4 L |
129 | ? (mips_64 ? "elf64-tradbigmips" : "elf32-tradbigmips") |
130 | : (mips_64 ? "elf64-tradlittlemips" : "elf32-tradlittlemips")); | |
8614eeee | 131 | #else |
252b5132 RH |
132 | return (target_big_endian |
133 | ? (mips_64 ? "elf64-bigmips" : "elf32-bigmips") | |
134 | : (mips_64 ? "elf64-littlemips" : "elf32-littlemips")); | |
8614eeee | 135 | #endif |
252b5132 RH |
136 | default: |
137 | abort (); | |
138 | return NULL; | |
139 | } | |
140 | } | |
141 | ||
142 | /* The name of the readonly data section. */ | |
143 | #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \ | |
144 | ? ".data" \ | |
145 | : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \ | |
146 | ? ".rdata" \ | |
056350c6 NC |
147 | : OUTPUT_FLAVOR == bfd_target_coff_flavour \ |
148 | ? ".rdata" \ | |
252b5132 RH |
149 | : OUTPUT_FLAVOR == bfd_target_elf_flavour \ |
150 | ? ".rodata" \ | |
151 | : (abort (), "")) | |
152 | ||
153 | /* This is the set of options which may be modified by the .set | |
154 | pseudo-op. We use a struct so that .set push and .set pop are more | |
155 | reliable. */ | |
156 | ||
e972090a NC |
157 | struct mips_set_options |
158 | { | |
252b5132 RH |
159 | /* MIPS ISA (Instruction Set Architecture) level. This is set to -1 |
160 | if it has not been initialized. Changed by `.set mipsN', and the | |
161 | -mipsN command line option, and the default CPU. */ | |
162 | int isa; | |
163 | /* Whether we are assembling for the mips16 processor. 0 if we are | |
164 | not, 1 if we are, and -1 if the value has not been initialized. | |
165 | Changed by `.set mips16' and `.set nomips16', and the -mips16 and | |
166 | -nomips16 command line options, and the default CPU. */ | |
167 | int mips16; | |
168 | /* Non-zero if we should not reorder instructions. Changed by `.set | |
169 | reorder' and `.set noreorder'. */ | |
170 | int noreorder; | |
171 | /* Non-zero if we should not permit the $at ($1) register to be used | |
172 | in instructions. Changed by `.set at' and `.set noat'. */ | |
173 | int noat; | |
174 | /* Non-zero if we should warn when a macro instruction expands into | |
175 | more than one machine instruction. Changed by `.set nomacro' and | |
176 | `.set macro'. */ | |
177 | int warn_about_macros; | |
178 | /* Non-zero if we should not move instructions. Changed by `.set | |
179 | move', `.set volatile', `.set nomove', and `.set novolatile'. */ | |
180 | int nomove; | |
181 | /* Non-zero if we should not optimize branches by moving the target | |
182 | of the branch into the delay slot. Actually, we don't perform | |
183 | this optimization anyhow. Changed by `.set bopt' and `.set | |
184 | nobopt'. */ | |
185 | int nobopt; | |
186 | /* Non-zero if we should not autoextend mips16 instructions. | |
187 | Changed by `.set autoextend' and `.set noautoextend'. */ | |
188 | int noautoextend; | |
189 | }; | |
190 | ||
191 | /* This is the struct we use to hold the current set of options. Note | |
e7af610e NC |
192 | that we must set the isa field to ISA_UNKNOWN and the mips16 field to |
193 | -1 to indicate that they have not been initialized. */ | |
252b5132 | 194 | |
e972090a NC |
195 | static struct mips_set_options mips_opts = |
196 | { | |
e7af610e NC |
197 | ISA_UNKNOWN, -1, 0, 0, 0, 0, 0, 0 |
198 | }; | |
252b5132 RH |
199 | |
200 | /* These variables are filled in with the masks of registers used. | |
201 | The object format code reads them and puts them in the appropriate | |
202 | place. */ | |
203 | unsigned long mips_gprmask; | |
204 | unsigned long mips_cprmask[4]; | |
205 | ||
206 | /* MIPS ISA we are using for this output file. */ | |
e7af610e | 207 | static int file_mips_isa = ISA_UNKNOWN; |
252b5132 | 208 | |
ec68c924 | 209 | /* The argument of the -mcpu= flag. Historical for code generation. */ |
e7af610e | 210 | static int mips_cpu = CPU_UNKNOWN; |
252b5132 | 211 | |
ec68c924 EC |
212 | /* The argument of the -march= flag. The architecture we are assembling. */ |
213 | static int mips_arch = CPU_UNKNOWN; | |
214 | ||
215 | /* The argument of the -mtune= flag. The architecture for which we | |
216 | are optimizing. */ | |
217 | static int mips_tune = CPU_UNKNOWN; | |
218 | ||
bdaaa2e1 | 219 | /* The argument of the -mabi= flag. */ |
9a41af64 | 220 | static char * mips_abi_string = NULL; |
252b5132 | 221 | |
2f4dcb11 | 222 | /* Whether we should mark the file EABI64 or EABI32. */ |
252b5132 RH |
223 | static int mips_eabi64 = 0; |
224 | ||
225 | /* If they asked for mips1 or mips2 and a cpu that is | |
bdaaa2e1 | 226 | mips3 or greater, then mark the object file 32BITMODE. */ |
252b5132 RH |
227 | static int mips_32bitmode = 0; |
228 | ||
bdaaa2e1 | 229 | /* True if -mgp32 was passed. */ |
c97ef257 AH |
230 | static int mips_gp32 = 0; |
231 | ||
ca4e0257 RS |
232 | /* True if -mfp32 was passed. */ |
233 | static int mips_fp32 = 0; | |
234 | ||
235 | /* True if the selected ABI is defined for 32-bit registers only. */ | |
236 | static int mips_32bit_abi = 0; | |
237 | ||
9ce8a5dd GRK |
238 | /* Some ISA's have delay slots for instructions which read or write |
239 | from a coprocessor (eg. mips1-mips3); some don't (eg mips4). | |
bdaaa2e1 | 240 | Return true if instructions marked INSN_LOAD_COPROC_DELAY, |
9ce8a5dd GRK |
241 | INSN_COPROC_MOVE_DELAY, or INSN_WRITE_COND_CODE actually have a |
242 | delay slot in this ISA. The uses of this macro assume that any | |
243 | ISA that has delay slots for one of these, has them for all. They | |
244 | also assume that ISAs which don't have delays for these insns, don't | |
bdaaa2e1 | 245 | have delays for the INSN_LOAD_MEMORY_DELAY instructions either. */ |
9ce8a5dd | 246 | #define ISA_HAS_COPROC_DELAYS(ISA) ( \ |
e7af610e NC |
247 | (ISA) == ISA_MIPS1 \ |
248 | || (ISA) == ISA_MIPS2 \ | |
249 | || (ISA) == ISA_MIPS3 \ | |
9ce8a5dd GRK |
250 | ) |
251 | ||
bdaaa2e1 | 252 | /* Return true if ISA supports 64 bit gp register instructions. */ |
9ce8a5dd | 253 | #define ISA_HAS_64BIT_REGS(ISA) ( \ |
e7af610e NC |
254 | (ISA) == ISA_MIPS3 \ |
255 | || (ISA) == ISA_MIPS4 \ | |
84ea6cf2 | 256 | || (ISA) == ISA_MIPS5 \ |
d1cf510e | 257 | || (ISA) == ISA_MIPS64 \ |
9ce8a5dd GRK |
258 | ) |
259 | ||
ca4e0257 RS |
260 | #define HAVE_32BIT_GPRS \ |
261 | (mips_gp32 \ | |
262 | || mips_32bit_abi \ | |
263 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) | |
264 | ||
265 | #define HAVE_32BIT_FPRS \ | |
266 | (mips_fp32 \ | |
267 | || mips_32bit_abi \ | |
268 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) | |
269 | ||
270 | #define HAVE_64BIT_GPRS (! HAVE_32BIT_GPRS) | |
271 | #define HAVE_64BIT_FPRS (! HAVE_32BIT_FPRS) | |
272 | ||
273 | #define HAVE_32BIT_ADDRESSES \ | |
274 | (HAVE_32BIT_GPRS \ | |
275 | || bfd_arch_bits_per_address (stdoutput) == 32) | |
276 | ||
bdaaa2e1 | 277 | /* Whether the processor uses hardware interlocks to protect |
252b5132 | 278 | reads from the HI and LO registers, and thus does not |
ec68c924 | 279 | require nops to be inserted. */ |
252b5132 | 280 | |
ec68c924 | 281 | #define hilo_interlocks (mips_arch == CPU_R4010 \ |
252b5132 RH |
282 | ) |
283 | ||
284 | /* Whether the processor uses hardware interlocks to protect reads | |
285 | from the GPRs, and thus does not require nops to be inserted. */ | |
286 | #define gpr_interlocks \ | |
e7af610e | 287 | (mips_opts.isa != ISA_MIPS1 \ |
ec68c924 | 288 | || mips_arch == CPU_R3900) |
252b5132 RH |
289 | |
290 | /* As with other "interlocks" this is used by hardware that has FP | |
291 | (co-processor) interlocks. */ | |
bdaaa2e1 | 292 | /* Itbl support may require additional care here. */ |
ec68c924 | 293 | #define cop_interlocks (mips_arch == CPU_R4300 \ |
252b5132 RH |
294 | ) |
295 | ||
6b76fefe CM |
296 | /* Is this a mfhi or mflo instruction? */ |
297 | #define MF_HILO_INSN(PINFO) \ | |
298 | ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO)) | |
299 | ||
252b5132 RH |
300 | /* MIPS PIC level. */ |
301 | ||
e972090a NC |
302 | enum mips_pic_level |
303 | { | |
252b5132 RH |
304 | /* Do not generate PIC code. */ |
305 | NO_PIC, | |
306 | ||
307 | /* Generate PIC code as in Irix 4. This is not implemented, and I'm | |
308 | not sure what it is supposed to do. */ | |
309 | IRIX4_PIC, | |
310 | ||
311 | /* Generate PIC code as in the SVR4 MIPS ABI. */ | |
312 | SVR4_PIC, | |
313 | ||
314 | /* Generate PIC code without using a global offset table: the data | |
315 | segment has a maximum size of 64K, all data references are off | |
316 | the $gp register, and all text references are PC relative. This | |
317 | is used on some embedded systems. */ | |
318 | EMBEDDED_PIC | |
319 | }; | |
320 | ||
321 | static enum mips_pic_level mips_pic; | |
322 | ||
39c0a331 L |
323 | /* Warn about all NOPS that the assembler generates. */ |
324 | static int warn_nops = 0; | |
325 | ||
252b5132 RH |
326 | /* 1 if we should generate 32 bit offsets from the GP register in |
327 | SVR4_PIC mode. Currently has no meaning in other modes. */ | |
328 | static int mips_big_got; | |
329 | ||
330 | /* 1 if trap instructions should used for overflow rather than break | |
331 | instructions. */ | |
332 | static int mips_trap; | |
333 | ||
119d663a NC |
334 | /* 1 if double width floating point constants should not be constructed |
335 | by a assembling two single width halves into two single width floating | |
336 | point registers which just happen to alias the double width destination | |
337 | register. On some architectures this aliasing can be disabled by a bit | |
d547a75e | 338 | in the status register, and the setting of this bit cannot be determined |
119d663a NC |
339 | automatically at assemble time. */ |
340 | static int mips_disable_float_construction; | |
341 | ||
252b5132 RH |
342 | /* Non-zero if any .set noreorder directives were used. */ |
343 | ||
344 | static int mips_any_noreorder; | |
345 | ||
6b76fefe CM |
346 | /* Non-zero if nops should be inserted when the register referenced in |
347 | an mfhi/mflo instruction is read in the next two instructions. */ | |
348 | static int mips_7000_hilo_fix; | |
349 | ||
252b5132 | 350 | /* The size of the small data section. */ |
156c2f8b | 351 | static unsigned int g_switch_value = 8; |
252b5132 RH |
352 | /* Whether the -G option was used. */ |
353 | static int g_switch_seen = 0; | |
354 | ||
355 | #define N_RMASK 0xc4 | |
356 | #define N_VFP 0xd4 | |
357 | ||
358 | /* If we can determine in advance that GP optimization won't be | |
359 | possible, we can skip the relaxation stuff that tries to produce | |
360 | GP-relative references. This makes delay slot optimization work | |
361 | better. | |
362 | ||
363 | This function can only provide a guess, but it seems to work for | |
fba2b7f9 GK |
364 | gcc output. It needs to guess right for gcc, otherwise gcc |
365 | will put what it thinks is a GP-relative instruction in a branch | |
366 | delay slot. | |
252b5132 RH |
367 | |
368 | I don't know if a fix is needed for the SVR4_PIC mode. I've only | |
369 | fixed it for the non-PIC mode. KR 95/04/07 */ | |
370 | static int nopic_need_relax PARAMS ((symbolS *, int)); | |
371 | ||
372 | /* handle of the OPCODE hash table */ | |
373 | static struct hash_control *op_hash = NULL; | |
374 | ||
375 | /* The opcode hash table we use for the mips16. */ | |
376 | static struct hash_control *mips16_op_hash = NULL; | |
377 | ||
378 | /* This array holds the chars that always start a comment. If the | |
379 | pre-processor is disabled, these aren't very useful */ | |
380 | const char comment_chars[] = "#"; | |
381 | ||
382 | /* This array holds the chars that only start a comment at the beginning of | |
383 | a line. If the line seems to have the form '# 123 filename' | |
384 | .line and .file directives will appear in the pre-processed output */ | |
385 | /* Note that input_file.c hand checks for '#' at the beginning of the | |
386 | first line of the input file. This is because the compiler outputs | |
bdaaa2e1 | 387 | #NO_APP at the beginning of its output. */ |
252b5132 RH |
388 | /* Also note that C style comments are always supported. */ |
389 | const char line_comment_chars[] = "#"; | |
390 | ||
bdaaa2e1 | 391 | /* This array holds machine specific line separator characters. */ |
63a0b638 | 392 | const char line_separator_chars[] = ";"; |
252b5132 RH |
393 | |
394 | /* Chars that can be used to separate mant from exp in floating point nums */ | |
395 | const char EXP_CHARS[] = "eE"; | |
396 | ||
397 | /* Chars that mean this number is a floating point constant */ | |
398 | /* As in 0f12.456 */ | |
399 | /* or 0d1.2345e12 */ | |
400 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; | |
401 | ||
402 | /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be | |
403 | changed in read.c . Ideally it shouldn't have to know about it at all, | |
404 | but nothing is ideal around here. | |
405 | */ | |
406 | ||
407 | static char *insn_error; | |
408 | ||
409 | static int auto_align = 1; | |
410 | ||
411 | /* When outputting SVR4 PIC code, the assembler needs to know the | |
412 | offset in the stack frame from which to restore the $gp register. | |
413 | This is set by the .cprestore pseudo-op, and saved in this | |
414 | variable. */ | |
415 | static offsetT mips_cprestore_offset = -1; | |
416 | ||
417 | /* This is the register which holds the stack frame, as set by the | |
418 | .frame pseudo-op. This is needed to implement .cprestore. */ | |
419 | static int mips_frame_reg = SP; | |
420 | ||
421 | /* To output NOP instructions correctly, we need to keep information | |
422 | about the previous two instructions. */ | |
423 | ||
424 | /* Whether we are optimizing. The default value of 2 means to remove | |
425 | unneeded NOPs and swap branch instructions when possible. A value | |
426 | of 1 means to not swap branches. A value of 0 means to always | |
427 | insert NOPs. */ | |
428 | static int mips_optimize = 2; | |
429 | ||
430 | /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is | |
431 | equivalent to seeing no -g option at all. */ | |
432 | static int mips_debug = 0; | |
433 | ||
434 | /* The previous instruction. */ | |
435 | static struct mips_cl_insn prev_insn; | |
436 | ||
437 | /* The instruction before prev_insn. */ | |
438 | static struct mips_cl_insn prev_prev_insn; | |
439 | ||
440 | /* If we don't want information for prev_insn or prev_prev_insn, we | |
441 | point the insn_mo field at this dummy integer. */ | |
43841e91 | 442 | static const struct mips_opcode dummy_opcode = { NULL, NULL, 0, 0, 0, 0 }; |
252b5132 RH |
443 | |
444 | /* Non-zero if prev_insn is valid. */ | |
445 | static int prev_insn_valid; | |
446 | ||
447 | /* The frag for the previous instruction. */ | |
448 | static struct frag *prev_insn_frag; | |
449 | ||
450 | /* The offset into prev_insn_frag for the previous instruction. */ | |
451 | static long prev_insn_where; | |
452 | ||
453 | /* The reloc type for the previous instruction, if any. */ | |
454 | static bfd_reloc_code_real_type prev_insn_reloc_type; | |
455 | ||
456 | /* The reloc for the previous instruction, if any. */ | |
457 | static fixS *prev_insn_fixp; | |
458 | ||
459 | /* Non-zero if the previous instruction was in a delay slot. */ | |
460 | static int prev_insn_is_delay_slot; | |
461 | ||
462 | /* Non-zero if the previous instruction was in a .set noreorder. */ | |
463 | static int prev_insn_unreordered; | |
464 | ||
465 | /* Non-zero if the previous instruction uses an extend opcode (if | |
466 | mips16). */ | |
467 | static int prev_insn_extended; | |
468 | ||
469 | /* Non-zero if the previous previous instruction was in a .set | |
470 | noreorder. */ | |
471 | static int prev_prev_insn_unreordered; | |
472 | ||
473 | /* If this is set, it points to a frag holding nop instructions which | |
474 | were inserted before the start of a noreorder section. If those | |
475 | nops turn out to be unnecessary, the size of the frag can be | |
476 | decreased. */ | |
477 | static fragS *prev_nop_frag; | |
478 | ||
479 | /* The number of nop instructions we created in prev_nop_frag. */ | |
480 | static int prev_nop_frag_holds; | |
481 | ||
482 | /* The number of nop instructions that we know we need in | |
bdaaa2e1 | 483 | prev_nop_frag. */ |
252b5132 RH |
484 | static int prev_nop_frag_required; |
485 | ||
486 | /* The number of instructions we've seen since prev_nop_frag. */ | |
487 | static int prev_nop_frag_since; | |
488 | ||
489 | /* For ECOFF and ELF, relocations against symbols are done in two | |
490 | parts, with a HI relocation and a LO relocation. Each relocation | |
491 | has only 16 bits of space to store an addend. This means that in | |
492 | order for the linker to handle carries correctly, it must be able | |
493 | to locate both the HI and the LO relocation. This means that the | |
494 | relocations must appear in order in the relocation table. | |
495 | ||
496 | In order to implement this, we keep track of each unmatched HI | |
497 | relocation. We then sort them so that they immediately precede the | |
bdaaa2e1 | 498 | corresponding LO relocation. */ |
252b5132 | 499 | |
e972090a NC |
500 | struct mips_hi_fixup |
501 | { | |
252b5132 RH |
502 | /* Next HI fixup. */ |
503 | struct mips_hi_fixup *next; | |
504 | /* This fixup. */ | |
505 | fixS *fixp; | |
506 | /* The section this fixup is in. */ | |
507 | segT seg; | |
508 | }; | |
509 | ||
510 | /* The list of unmatched HI relocs. */ | |
511 | ||
512 | static struct mips_hi_fixup *mips_hi_fixup_list; | |
513 | ||
514 | /* Map normal MIPS register numbers to mips16 register numbers. */ | |
515 | ||
516 | #define X ILLEGAL_REG | |
e972090a NC |
517 | static const int mips32_to_16_reg_map[] = |
518 | { | |
252b5132 RH |
519 | X, X, 2, 3, 4, 5, 6, 7, |
520 | X, X, X, X, X, X, X, X, | |
521 | 0, 1, X, X, X, X, X, X, | |
522 | X, X, X, X, X, X, X, X | |
523 | }; | |
524 | #undef X | |
525 | ||
526 | /* Map mips16 register numbers to normal MIPS register numbers. */ | |
527 | ||
e972090a NC |
528 | static const unsigned int mips16_to_32_reg_map[] = |
529 | { | |
252b5132 RH |
530 | 16, 17, 2, 3, 4, 5, 6, 7 |
531 | }; | |
532 | \f | |
533 | /* Since the MIPS does not have multiple forms of PC relative | |
534 | instructions, we do not have to do relaxing as is done on other | |
535 | platforms. However, we do have to handle GP relative addressing | |
536 | correctly, which turns out to be a similar problem. | |
537 | ||
538 | Every macro that refers to a symbol can occur in (at least) two | |
539 | forms, one with GP relative addressing and one without. For | |
540 | example, loading a global variable into a register generally uses | |
541 | a macro instruction like this: | |
542 | lw $4,i | |
543 | If i can be addressed off the GP register (this is true if it is in | |
544 | the .sbss or .sdata section, or if it is known to be smaller than | |
545 | the -G argument) this will generate the following instruction: | |
546 | lw $4,i($gp) | |
547 | This instruction will use a GPREL reloc. If i can not be addressed | |
548 | off the GP register, the following instruction sequence will be used: | |
549 | lui $at,i | |
550 | lw $4,i($at) | |
551 | In this case the first instruction will have a HI16 reloc, and the | |
552 | second reloc will have a LO16 reloc. Both relocs will be against | |
553 | the symbol i. | |
554 | ||
555 | The issue here is that we may not know whether i is GP addressable | |
556 | until after we see the instruction that uses it. Therefore, we | |
557 | want to be able to choose the final instruction sequence only at | |
558 | the end of the assembly. This is similar to the way other | |
559 | platforms choose the size of a PC relative instruction only at the | |
560 | end of assembly. | |
561 | ||
562 | When generating position independent code we do not use GP | |
563 | addressing in quite the same way, but the issue still arises as | |
564 | external symbols and local symbols must be handled differently. | |
565 | ||
566 | We handle these issues by actually generating both possible | |
567 | instruction sequences. The longer one is put in a frag_var with | |
568 | type rs_machine_dependent. We encode what to do with the frag in | |
569 | the subtype field. We encode (1) the number of existing bytes to | |
570 | replace, (2) the number of new bytes to use, (3) the offset from | |
571 | the start of the existing bytes to the first reloc we must generate | |
572 | (that is, the offset is applied from the start of the existing | |
573 | bytes after they are replaced by the new bytes, if any), (4) the | |
574 | offset from the start of the existing bytes to the second reloc, | |
575 | (5) whether a third reloc is needed (the third reloc is always four | |
576 | bytes after the second reloc), and (6) whether to warn if this | |
577 | variant is used (this is sometimes needed if .set nomacro or .set | |
578 | noat is in effect). All these numbers are reasonably small. | |
579 | ||
580 | Generating two instruction sequences must be handled carefully to | |
581 | ensure that delay slots are handled correctly. Fortunately, there | |
582 | are a limited number of cases. When the second instruction | |
583 | sequence is generated, append_insn is directed to maintain the | |
584 | existing delay slot information, so it continues to apply to any | |
585 | code after the second instruction sequence. This means that the | |
586 | second instruction sequence must not impose any requirements not | |
587 | required by the first instruction sequence. | |
588 | ||
589 | These variant frags are then handled in functions called by the | |
590 | machine independent code. md_estimate_size_before_relax returns | |
591 | the final size of the frag. md_convert_frag sets up the final form | |
592 | of the frag. tc_gen_reloc adjust the first reloc and adds a second | |
593 | one if needed. */ | |
594 | #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \ | |
595 | ((relax_substateT) \ | |
596 | (((old) << 23) \ | |
597 | | ((new) << 16) \ | |
598 | | (((reloc1) + 64) << 9) \ | |
599 | | (((reloc2) + 64) << 2) \ | |
600 | | ((reloc3) ? (1 << 1) : 0) \ | |
601 | | ((warn) ? 1 : 0))) | |
602 | #define RELAX_OLD(i) (((i) >> 23) & 0x7f) | |
603 | #define RELAX_NEW(i) (((i) >> 16) & 0x7f) | |
9a41af64 TS |
604 | #define RELAX_RELOC1(i) ((valueT) (((i) >> 9) & 0x7f) - 64) |
605 | #define RELAX_RELOC2(i) ((valueT) (((i) >> 2) & 0x7f) - 64) | |
252b5132 RH |
606 | #define RELAX_RELOC3(i) (((i) >> 1) & 1) |
607 | #define RELAX_WARN(i) ((i) & 1) | |
608 | ||
609 | /* For mips16 code, we use an entirely different form of relaxation. | |
610 | mips16 supports two versions of most instructions which take | |
611 | immediate values: a small one which takes some small value, and a | |
612 | larger one which takes a 16 bit value. Since branches also follow | |
613 | this pattern, relaxing these values is required. | |
614 | ||
615 | We can assemble both mips16 and normal MIPS code in a single | |
616 | object. Therefore, we need to support this type of relaxation at | |
617 | the same time that we support the relaxation described above. We | |
618 | use the high bit of the subtype field to distinguish these cases. | |
619 | ||
620 | The information we store for this type of relaxation is the | |
621 | argument code found in the opcode file for this relocation, whether | |
622 | the user explicitly requested a small or extended form, and whether | |
623 | the relocation is in a jump or jal delay slot. That tells us the | |
624 | size of the value, and how it should be stored. We also store | |
625 | whether the fragment is considered to be extended or not. We also | |
626 | store whether this is known to be a branch to a different section, | |
627 | whether we have tried to relax this frag yet, and whether we have | |
628 | ever extended a PC relative fragment because of a shift count. */ | |
629 | #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \ | |
630 | (0x80000000 \ | |
631 | | ((type) & 0xff) \ | |
632 | | ((small) ? 0x100 : 0) \ | |
633 | | ((ext) ? 0x200 : 0) \ | |
634 | | ((dslot) ? 0x400 : 0) \ | |
635 | | ((jal_dslot) ? 0x800 : 0)) | |
636 | #define RELAX_MIPS16_P(i) (((i) & 0x80000000) != 0) | |
637 | #define RELAX_MIPS16_TYPE(i) ((i) & 0xff) | |
638 | #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0) | |
639 | #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0) | |
640 | #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0) | |
641 | #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0) | |
642 | #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0) | |
643 | #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000) | |
644 | #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000) | |
645 | #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0) | |
646 | #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000) | |
647 | #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000) | |
648 | \f | |
649 | /* Prototypes for static functions. */ | |
650 | ||
651 | #ifdef __STDC__ | |
652 | #define internalError() \ | |
653 | as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__) | |
654 | #else | |
655 | #define internalError() as_fatal (_("MIPS internal Error")); | |
656 | #endif | |
657 | ||
658 | enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG }; | |
659 | ||
660 | static int insn_uses_reg PARAMS ((struct mips_cl_insn *ip, | |
661 | unsigned int reg, enum mips_regclass class)); | |
156c2f8b | 662 | static int reg_needs_delay PARAMS ((unsigned int)); |
252b5132 RH |
663 | static void mips16_mark_labels PARAMS ((void)); |
664 | static void append_insn PARAMS ((char *place, | |
665 | struct mips_cl_insn * ip, | |
666 | expressionS * p, | |
667 | bfd_reloc_code_real_type r, | |
668 | boolean)); | |
669 | static void mips_no_prev_insn PARAMS ((int)); | |
670 | static void mips_emit_delays PARAMS ((boolean)); | |
671 | #ifdef USE_STDARG | |
672 | static void macro_build PARAMS ((char *place, int *counter, expressionS * ep, | |
673 | const char *name, const char *fmt, | |
674 | ...)); | |
675 | #else | |
676 | static void macro_build (); | |
677 | #endif | |
678 | static void mips16_macro_build PARAMS ((char *, int *, expressionS *, | |
679 | const char *, const char *, | |
680 | va_list)); | |
681 | static void macro_build_lui PARAMS ((char *place, int *counter, | |
682 | expressionS * ep, int regnum)); | |
683 | static void set_at PARAMS ((int *counter, int reg, int unsignedp)); | |
684 | static void check_absolute_expr PARAMS ((struct mips_cl_insn * ip, | |
685 | expressionS *)); | |
686 | static void load_register PARAMS ((int *, int, expressionS *, int)); | |
687 | static void load_address PARAMS ((int *counter, int reg, expressionS *ep)); | |
ea1fb5dc | 688 | static void move_register PARAMS ((int *, int, int)); |
252b5132 RH |
689 | static void macro PARAMS ((struct mips_cl_insn * ip)); |
690 | static void mips16_macro PARAMS ((struct mips_cl_insn * ip)); | |
691 | #ifdef LOSING_COMPILER | |
692 | static void macro2 PARAMS ((struct mips_cl_insn * ip)); | |
693 | #endif | |
694 | static void mips_ip PARAMS ((char *str, struct mips_cl_insn * ip)); | |
695 | static void mips16_ip PARAMS ((char *str, struct mips_cl_insn * ip)); | |
696 | static void mips16_immed PARAMS ((char *, unsigned int, int, offsetT, boolean, | |
697 | boolean, boolean, unsigned long *, | |
698 | boolean *, unsigned short *)); | |
699 | static int my_getSmallExpression PARAMS ((expressionS * ep, char *str)); | |
700 | static void my_getExpression PARAMS ((expressionS * ep, char *str)); | |
701 | static symbolS *get_symbol PARAMS ((void)); | |
702 | static void mips_align PARAMS ((int to, int fill, symbolS *label)); | |
703 | static void s_align PARAMS ((int)); | |
704 | static void s_change_sec PARAMS ((int)); | |
705 | static void s_cons PARAMS ((int)); | |
706 | static void s_float_cons PARAMS ((int)); | |
707 | static void s_mips_globl PARAMS ((int)); | |
708 | static void s_option PARAMS ((int)); | |
709 | static void s_mipsset PARAMS ((int)); | |
710 | static void s_abicalls PARAMS ((int)); | |
711 | static void s_cpload PARAMS ((int)); | |
712 | static void s_cprestore PARAMS ((int)); | |
713 | static void s_gpword PARAMS ((int)); | |
714 | static void s_cpadd PARAMS ((int)); | |
715 | static void s_insn PARAMS ((int)); | |
716 | static void md_obj_begin PARAMS ((void)); | |
717 | static void md_obj_end PARAMS ((void)); | |
718 | static long get_number PARAMS ((void)); | |
719 | static void s_mips_ent PARAMS ((int)); | |
720 | static void s_mips_end PARAMS ((int)); | |
721 | static void s_mips_frame PARAMS ((int)); | |
722 | static void s_mips_mask PARAMS ((int)); | |
723 | static void s_mips_stab PARAMS ((int)); | |
724 | static void s_mips_weakext PARAMS ((int)); | |
725 | static void s_file PARAMS ((int)); | |
726 | static int mips16_extended_frag PARAMS ((fragS *, asection *, long)); | |
e7af610e NC |
727 | static const char *mips_isa_to_str PARAMS ((int)); |
728 | static const char *mips_cpu_to_str PARAMS ((int)); | |
252b5132 | 729 | static int validate_mips_insn PARAMS ((const struct mips_opcode *)); |
e7af610e NC |
730 | |
731 | /* Table and functions used to map between CPU/ISA names, and | |
732 | ISA levels, and CPU numbers. */ | |
733 | ||
e972090a NC |
734 | struct mips_cpu_info |
735 | { | |
e7af610e NC |
736 | const char *name; /* CPU or ISA name. */ |
737 | int is_isa; /* Is this an ISA? (If 0, a CPU.) */ | |
738 | int isa; /* ISA level. */ | |
739 | int cpu; /* CPU number (default CPU if ISA). */ | |
740 | }; | |
741 | ||
742 | static const struct mips_cpu_info *mips_cpu_info_from_name PARAMS ((const char *)); | |
743 | static const struct mips_cpu_info *mips_cpu_info_from_isa PARAMS ((int)); | |
744 | static const struct mips_cpu_info *mips_cpu_info_from_cpu PARAMS ((int)); | |
252b5132 RH |
745 | \f |
746 | /* Pseudo-op table. | |
747 | ||
748 | The following pseudo-ops from the Kane and Heinrich MIPS book | |
749 | should be defined here, but are currently unsupported: .alias, | |
750 | .galive, .gjaldef, .gjrlive, .livereg, .noalias. | |
751 | ||
752 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
753 | specific to the type of debugging information being generated, and | |
754 | should be defined by the object format: .aent, .begin, .bend, | |
755 | .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp, | |
756 | .vreg. | |
757 | ||
758 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
759 | not MIPS CPU specific, but are also not specific to the object file | |
760 | format. This file is probably the best place to define them, but | |
761 | they are not currently supported: .asm0, .endr, .lab, .repeat, | |
762 | .struct. */ | |
763 | ||
e972090a NC |
764 | static const pseudo_typeS mips_pseudo_table[] = |
765 | { | |
beae10d5 | 766 | /* MIPS specific pseudo-ops. */ |
252b5132 RH |
767 | {"option", s_option, 0}, |
768 | {"set", s_mipsset, 0}, | |
769 | {"rdata", s_change_sec, 'r'}, | |
770 | {"sdata", s_change_sec, 's'}, | |
771 | {"livereg", s_ignore, 0}, | |
772 | {"abicalls", s_abicalls, 0}, | |
773 | {"cpload", s_cpload, 0}, | |
774 | {"cprestore", s_cprestore, 0}, | |
775 | {"gpword", s_gpword, 0}, | |
776 | {"cpadd", s_cpadd, 0}, | |
777 | {"insn", s_insn, 0}, | |
778 | ||
beae10d5 | 779 | /* Relatively generic pseudo-ops that happen to be used on MIPS |
252b5132 RH |
780 | chips. */ |
781 | {"asciiz", stringer, 1}, | |
782 | {"bss", s_change_sec, 'b'}, | |
783 | {"err", s_err, 0}, | |
784 | {"half", s_cons, 1}, | |
785 | {"dword", s_cons, 3}, | |
786 | {"weakext", s_mips_weakext, 0}, | |
787 | ||
beae10d5 | 788 | /* These pseudo-ops are defined in read.c, but must be overridden |
252b5132 RH |
789 | here for one reason or another. */ |
790 | {"align", s_align, 0}, | |
791 | {"byte", s_cons, 0}, | |
792 | {"data", s_change_sec, 'd'}, | |
793 | {"double", s_float_cons, 'd'}, | |
794 | {"float", s_float_cons, 'f'}, | |
795 | {"globl", s_mips_globl, 0}, | |
796 | {"global", s_mips_globl, 0}, | |
797 | {"hword", s_cons, 1}, | |
798 | {"int", s_cons, 2}, | |
799 | {"long", s_cons, 2}, | |
800 | {"octa", s_cons, 4}, | |
801 | {"quad", s_cons, 3}, | |
802 | {"short", s_cons, 1}, | |
803 | {"single", s_float_cons, 'f'}, | |
804 | {"stabn", s_mips_stab, 'n'}, | |
805 | {"text", s_change_sec, 't'}, | |
806 | {"word", s_cons, 2}, | |
add56521 L |
807 | |
808 | #ifdef MIPS_STABS_ELF | |
809 | { "extern", ecoff_directive_extern, 0}, | |
810 | #endif | |
811 | ||
43841e91 | 812 | { NULL, NULL, 0 }, |
252b5132 RH |
813 | }; |
814 | ||
e972090a NC |
815 | static const pseudo_typeS mips_nonecoff_pseudo_table[] = |
816 | { | |
beae10d5 KH |
817 | /* These pseudo-ops should be defined by the object file format. |
818 | However, a.out doesn't support them, so we have versions here. */ | |
252b5132 RH |
819 | {"aent", s_mips_ent, 1}, |
820 | {"bgnb", s_ignore, 0}, | |
821 | {"end", s_mips_end, 0}, | |
822 | {"endb", s_ignore, 0}, | |
823 | {"ent", s_mips_ent, 0}, | |
824 | {"file", s_file, 0}, | |
825 | {"fmask", s_mips_mask, 'F'}, | |
826 | {"frame", s_mips_frame, 0}, | |
827 | {"loc", s_ignore, 0}, | |
828 | {"mask", s_mips_mask, 'R'}, | |
829 | {"verstamp", s_ignore, 0}, | |
43841e91 | 830 | { NULL, NULL, 0 }, |
252b5132 RH |
831 | }; |
832 | ||
833 | extern void pop_insert PARAMS ((const pseudo_typeS *)); | |
834 | ||
835 | void | |
836 | mips_pop_insert () | |
837 | { | |
838 | pop_insert (mips_pseudo_table); | |
839 | if (! ECOFF_DEBUGGING) | |
840 | pop_insert (mips_nonecoff_pseudo_table); | |
841 | } | |
842 | \f | |
843 | /* Symbols labelling the current insn. */ | |
844 | ||
e972090a NC |
845 | struct insn_label_list |
846 | { | |
252b5132 RH |
847 | struct insn_label_list *next; |
848 | symbolS *label; | |
849 | }; | |
850 | ||
851 | static struct insn_label_list *insn_labels; | |
852 | static struct insn_label_list *free_insn_labels; | |
853 | ||
854 | static void mips_clear_insn_labels PARAMS ((void)); | |
855 | ||
856 | static inline void | |
857 | mips_clear_insn_labels () | |
858 | { | |
859 | register struct insn_label_list **pl; | |
860 | ||
861 | for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next) | |
862 | ; | |
863 | *pl = insn_labels; | |
864 | insn_labels = NULL; | |
865 | } | |
866 | \f | |
867 | static char *expr_end; | |
868 | ||
869 | /* Expressions which appear in instructions. These are set by | |
870 | mips_ip. */ | |
871 | ||
872 | static expressionS imm_expr; | |
873 | static expressionS offset_expr; | |
874 | ||
875 | /* Relocs associated with imm_expr and offset_expr. */ | |
876 | ||
877 | static bfd_reloc_code_real_type imm_reloc; | |
878 | static bfd_reloc_code_real_type offset_reloc; | |
879 | ||
880 | /* This is set by mips_ip if imm_reloc is an unmatched HI16_S reloc. */ | |
881 | ||
882 | static boolean imm_unmatched_hi; | |
883 | ||
884 | /* These are set by mips16_ip if an explicit extension is used. */ | |
885 | ||
886 | static boolean mips16_small, mips16_ext; | |
887 | ||
888 | #ifdef MIPS_STABS_ELF | |
889 | /* The pdr segment for per procedure frame/regmask info */ | |
890 | ||
891 | static segT pdr_seg; | |
892 | #endif | |
893 | ||
e7af610e NC |
894 | static const char * |
895 | mips_isa_to_str (isa) | |
896 | int isa; | |
897 | { | |
898 | const struct mips_cpu_info *ci; | |
899 | static char s[20]; | |
900 | ||
901 | ci = mips_cpu_info_from_isa (isa); | |
902 | if (ci != NULL) | |
903 | return (ci->name); | |
904 | ||
905 | sprintf (s, "ISA#%d", isa); | |
906 | return s; | |
907 | } | |
908 | ||
909 | static const char * | |
156c2f8b NC |
910 | mips_cpu_to_str (cpu) |
911 | int cpu; | |
912 | { | |
e7af610e | 913 | const struct mips_cpu_info *ci; |
156c2f8b | 914 | static char s[16]; |
e7af610e NC |
915 | |
916 | ci = mips_cpu_info_from_cpu (cpu); | |
917 | if (ci != NULL) | |
918 | return (ci->name); | |
919 | ||
920 | sprintf (s, "CPU#%d", cpu); | |
921 | return s; | |
156c2f8b NC |
922 | } |
923 | ||
924 | /* This function is called once, at assembler startup time. It should | |
925 | set up all the tables, etc. that the MD part of the assembler will need. */ | |
926 | ||
252b5132 RH |
927 | void |
928 | md_begin () | |
929 | { | |
252b5132 | 930 | register const char *retval = NULL; |
156c2f8b | 931 | int i = 0; |
252b5132 RH |
932 | const char *cpu; |
933 | char *a = NULL; | |
934 | int broken = 0; | |
935 | int mips_isa_from_cpu; | |
e7af610e NC |
936 | int target_cpu_had_mips16 = 0; |
937 | const struct mips_cpu_info *ci; | |
252b5132 | 938 | |
056350c6 NC |
939 | /* GP relative stuff not working for PE */ |
940 | if (strncmp (TARGET_OS, "pe", 2) == 0 | |
941 | && g_switch_value != 0) | |
942 | { | |
943 | if (g_switch_seen) | |
944 | as_bad (_("-G not supported in this configuration.")); | |
945 | g_switch_value = 0; | |
946 | } | |
947 | ||
252b5132 RH |
948 | cpu = TARGET_CPU; |
949 | if (strcmp (cpu + (sizeof TARGET_CPU) - 3, "el") == 0) | |
950 | { | |
951 | a = xmalloc (sizeof TARGET_CPU); | |
952 | strcpy (a, TARGET_CPU); | |
953 | a[(sizeof TARGET_CPU) - 3] = '\0'; | |
954 | cpu = a; | |
955 | } | |
956 | ||
e7af610e | 957 | if (strncmp (cpu, "mips16", sizeof "mips16" - 1) == 0) |
252b5132 | 958 | { |
e7af610e NC |
959 | target_cpu_had_mips16 = 1; |
960 | cpu += sizeof "mips16" - 1; | |
252b5132 RH |
961 | } |
962 | ||
e7af610e NC |
963 | if (mips_opts.mips16 < 0) |
964 | mips_opts.mips16 = target_cpu_had_mips16; | |
252b5132 | 965 | |
6dce9e24 TS |
966 | /* Backward compatibility for historic -mcpu= option. Check for |
967 | incompatible options, warn if -mcpu is used. */ | |
968 | if (mips_cpu != CPU_UNKNOWN | |
969 | && mips_arch != CPU_UNKNOWN | |
970 | && mips_cpu != mips_arch) | |
971 | { | |
972 | as_fatal (_("The -mcpu option can't be used together with -march. " | |
973 | "Use -mtune instead of -mcpu.")); | |
974 | } | |
975 | ||
976 | if (mips_cpu != CPU_UNKNOWN | |
977 | && mips_tune != CPU_UNKNOWN | |
978 | && mips_cpu != mips_tune) | |
979 | { | |
980 | as_fatal (_("The -mcpu option can't be used together with -mtune. " | |
981 | "Use -march instead of -mcpu.")); | |
982 | } | |
983 | ||
984 | if (mips_arch == CPU_UNKNOWN && mips_cpu != CPU_UNKNOWN) | |
985 | { | |
986 | ci = mips_cpu_info_from_cpu (mips_cpu); | |
987 | assert (ci != NULL); | |
988 | mips_arch = ci->cpu; | |
989 | as_warn (_("The -mcpu option is deprecated. Please use -march and " | |
990 | "-mtune instead.")); | |
991 | } | |
992 | ||
ec68c924 | 993 | /* At this point, mips_arch will either be CPU_UNKNOWN if no ARCH was |
e7af610e NC |
994 | specified on the command line, or some other value if one was. |
995 | Similarly, mips_opts.isa will be ISA_UNKNOWN if not specified on | |
996 | the command line, or will be set otherwise if one was. */ | |
ec68c924 | 997 | if (mips_arch != CPU_UNKNOWN && mips_opts.isa != ISA_UNKNOWN) |
252b5132 | 998 | { |
e7af610e | 999 | /* We have it all. There's nothing to do. */ |
252b5132 | 1000 | } |
ec68c924 | 1001 | else if (mips_arch != CPU_UNKNOWN && mips_opts.isa == ISA_UNKNOWN) |
252b5132 | 1002 | { |
ec68c924 EC |
1003 | /* We have ARCH, we need ISA. */ |
1004 | ci = mips_cpu_info_from_cpu (mips_arch); | |
e7af610e NC |
1005 | assert (ci != NULL); |
1006 | mips_opts.isa = ci->isa; | |
1007 | } | |
ec68c924 | 1008 | else if (mips_arch == CPU_UNKNOWN && mips_opts.isa != ISA_UNKNOWN) |
e7af610e | 1009 | { |
ec68c924 | 1010 | /* We have ISA, we need default ARCH. */ |
e7af610e NC |
1011 | ci = mips_cpu_info_from_isa (mips_opts.isa); |
1012 | assert (ci != NULL); | |
ec68c924 EC |
1013 | mips_arch = ci->cpu; |
1014 | } | |
e7af610e NC |
1015 | else |
1016 | { | |
ec68c924 | 1017 | /* We need to set both ISA and ARCH from target cpu. */ |
e7af610e NC |
1018 | ci = mips_cpu_info_from_name (cpu); |
1019 | if (ci == NULL) | |
beae10d5 | 1020 | ci = mips_cpu_info_from_cpu (CPU_R3000); |
e7af610e NC |
1021 | assert (ci != NULL); |
1022 | mips_opts.isa = ci->isa; | |
ec68c924 | 1023 | mips_arch = ci->cpu; |
252b5132 RH |
1024 | } |
1025 | ||
ec68c924 EC |
1026 | if (mips_tune == CPU_UNKNOWN) |
1027 | mips_tune = mips_arch; | |
1028 | ||
1029 | ci = mips_cpu_info_from_cpu (mips_arch); | |
e7af610e NC |
1030 | assert (ci != NULL); |
1031 | mips_isa_from_cpu = ci->isa; | |
1032 | ||
252b5132 | 1033 | /* End of TARGET_CPU processing, get rid of malloced memory |
bdaaa2e1 | 1034 | if necessary. */ |
252b5132 RH |
1035 | cpu = NULL; |
1036 | if (a != NULL) | |
1037 | { | |
156c2f8b NC |
1038 | free (a); |
1039 | a = NULL; | |
252b5132 RH |
1040 | } |
1041 | ||
e7af610e | 1042 | if (mips_opts.isa == ISA_MIPS1 && mips_trap) |
252b5132 RH |
1043 | as_bad (_("trap exception not supported at ISA 1")); |
1044 | ||
1045 | /* Set the EABI kind based on the ISA before the user gets | |
1046 | to change the ISA with directives. This isn't really | |
bdaaa2e1 | 1047 | the best, but then neither is basing the abi on the isa. */ |
9ce8a5dd | 1048 | if (ISA_HAS_64BIT_REGS (mips_opts.isa) |
252b5132 | 1049 | && mips_abi_string |
beae10d5 | 1050 | && 0 == strcmp (mips_abi_string, "eabi")) |
252b5132 RH |
1051 | mips_eabi64 = 1; |
1052 | ||
e7af610e NC |
1053 | /* If they asked for mips1 or mips2 and a cpu that is |
1054 | mips3 or greater, then mark the object file 32BITMODE. */ | |
1055 | if (mips_isa_from_cpu != ISA_UNKNOWN | |
1056 | && ! ISA_HAS_64BIT_REGS (mips_opts.isa) | |
1057 | && ISA_HAS_64BIT_REGS (mips_isa_from_cpu)) | |
1058 | mips_32bitmode = 1; | |
252b5132 | 1059 | |
ec68c924 | 1060 | if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, mips_arch)) |
252b5132 RH |
1061 | as_warn (_("Could not set architecture and machine")); |
1062 | ||
1063 | file_mips_isa = mips_opts.isa; | |
1064 | ||
1065 | op_hash = hash_new (); | |
1066 | ||
1067 | for (i = 0; i < NUMOPCODES;) | |
1068 | { | |
1069 | const char *name = mips_opcodes[i].name; | |
1070 | ||
1071 | retval = hash_insert (op_hash, name, (PTR) &mips_opcodes[i]); | |
1072 | if (retval != NULL) | |
1073 | { | |
1074 | fprintf (stderr, _("internal error: can't hash `%s': %s\n"), | |
1075 | mips_opcodes[i].name, retval); | |
1076 | /* Probably a memory allocation problem? Give up now. */ | |
1077 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
1078 | } | |
1079 | do | |
1080 | { | |
1081 | if (mips_opcodes[i].pinfo != INSN_MACRO) | |
1082 | { | |
1083 | if (!validate_mips_insn (&mips_opcodes[i])) | |
1084 | broken = 1; | |
1085 | } | |
1086 | ++i; | |
1087 | } | |
1088 | while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name)); | |
1089 | } | |
1090 | ||
1091 | mips16_op_hash = hash_new (); | |
1092 | ||
1093 | i = 0; | |
1094 | while (i < bfd_mips16_num_opcodes) | |
1095 | { | |
1096 | const char *name = mips16_opcodes[i].name; | |
1097 | ||
1098 | retval = hash_insert (mips16_op_hash, name, (PTR) &mips16_opcodes[i]); | |
1099 | if (retval != NULL) | |
1100 | as_fatal (_("internal: can't hash `%s': %s"), | |
1101 | mips16_opcodes[i].name, retval); | |
1102 | do | |
1103 | { | |
1104 | if (mips16_opcodes[i].pinfo != INSN_MACRO | |
1105 | && ((mips16_opcodes[i].match & mips16_opcodes[i].mask) | |
1106 | != mips16_opcodes[i].match)) | |
1107 | { | |
1108 | fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"), | |
1109 | mips16_opcodes[i].name, mips16_opcodes[i].args); | |
1110 | broken = 1; | |
1111 | } | |
1112 | ++i; | |
1113 | } | |
1114 | while (i < bfd_mips16_num_opcodes | |
1115 | && strcmp (mips16_opcodes[i].name, name) == 0); | |
1116 | } | |
1117 | ||
1118 | if (broken) | |
1119 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
1120 | ||
1121 | /* We add all the general register names to the symbol table. This | |
1122 | helps us detect invalid uses of them. */ | |
1123 | for (i = 0; i < 32; i++) | |
1124 | { | |
1125 | char buf[5]; | |
1126 | ||
1127 | sprintf (buf, "$%d", i); | |
1128 | symbol_table_insert (symbol_new (buf, reg_section, i, | |
1129 | &zero_address_frag)); | |
1130 | } | |
1131 | symbol_table_insert (symbol_new ("$fp", reg_section, FP, | |
1132 | &zero_address_frag)); | |
1133 | symbol_table_insert (symbol_new ("$sp", reg_section, SP, | |
1134 | &zero_address_frag)); | |
1135 | symbol_table_insert (symbol_new ("$gp", reg_section, GP, | |
1136 | &zero_address_frag)); | |
1137 | symbol_table_insert (symbol_new ("$at", reg_section, AT, | |
1138 | &zero_address_frag)); | |
1139 | symbol_table_insert (symbol_new ("$kt0", reg_section, KT0, | |
1140 | &zero_address_frag)); | |
1141 | symbol_table_insert (symbol_new ("$kt1", reg_section, KT1, | |
1142 | &zero_address_frag)); | |
1143 | symbol_table_insert (symbol_new ("$pc", reg_section, -1, | |
1144 | &zero_address_frag)); | |
1145 | ||
1146 | mips_no_prev_insn (false); | |
1147 | ||
1148 | mips_gprmask = 0; | |
1149 | mips_cprmask[0] = 0; | |
1150 | mips_cprmask[1] = 0; | |
1151 | mips_cprmask[2] = 0; | |
1152 | mips_cprmask[3] = 0; | |
1153 | ||
1154 | /* set the default alignment for the text section (2**2) */ | |
1155 | record_alignment (text_section, 2); | |
1156 | ||
1157 | if (USE_GLOBAL_POINTER_OPT) | |
1158 | bfd_set_gp_size (stdoutput, g_switch_value); | |
1159 | ||
1160 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
1161 | { | |
1162 | /* On a native system, sections must be aligned to 16 byte | |
1163 | boundaries. When configured for an embedded ELF target, we | |
1164 | don't bother. */ | |
1165 | if (strcmp (TARGET_OS, "elf") != 0) | |
1166 | { | |
1167 | (void) bfd_set_section_alignment (stdoutput, text_section, 4); | |
1168 | (void) bfd_set_section_alignment (stdoutput, data_section, 4); | |
1169 | (void) bfd_set_section_alignment (stdoutput, bss_section, 4); | |
1170 | } | |
1171 | ||
1172 | /* Create a .reginfo section for register masks and a .mdebug | |
1173 | section for debugging information. */ | |
1174 | { | |
1175 | segT seg; | |
1176 | subsegT subseg; | |
1177 | flagword flags; | |
1178 | segT sec; | |
1179 | ||
1180 | seg = now_seg; | |
1181 | subseg = now_subseg; | |
1182 | ||
1183 | /* The ABI says this section should be loaded so that the | |
1184 | running program can access it. However, we don't load it | |
1185 | if we are configured for an embedded target */ | |
1186 | flags = SEC_READONLY | SEC_DATA; | |
1187 | if (strcmp (TARGET_OS, "elf") != 0) | |
1188 | flags |= SEC_ALLOC | SEC_LOAD; | |
1189 | ||
1190 | if (! mips_64) | |
1191 | { | |
1192 | sec = subseg_new (".reginfo", (subsegT) 0); | |
1193 | ||
252b5132 RH |
1194 | (void) bfd_set_section_flags (stdoutput, sec, flags); |
1195 | (void) bfd_set_section_alignment (stdoutput, sec, 2); | |
bdaaa2e1 | 1196 | |
252b5132 RH |
1197 | #ifdef OBJ_ELF |
1198 | mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo)); | |
1199 | #endif | |
1200 | } | |
1201 | else | |
1202 | { | |
1203 | /* The 64-bit ABI uses a .MIPS.options section rather than | |
1204 | .reginfo section. */ | |
1205 | sec = subseg_new (".MIPS.options", (subsegT) 0); | |
1206 | (void) bfd_set_section_flags (stdoutput, sec, flags); | |
1207 | (void) bfd_set_section_alignment (stdoutput, sec, 3); | |
1208 | ||
1209 | #ifdef OBJ_ELF | |
1210 | /* Set up the option header. */ | |
1211 | { | |
1212 | Elf_Internal_Options opthdr; | |
1213 | char *f; | |
1214 | ||
1215 | opthdr.kind = ODK_REGINFO; | |
1216 | opthdr.size = (sizeof (Elf_External_Options) | |
1217 | + sizeof (Elf64_External_RegInfo)); | |
1218 | opthdr.section = 0; | |
1219 | opthdr.info = 0; | |
1220 | f = frag_more (sizeof (Elf_External_Options)); | |
1221 | bfd_mips_elf_swap_options_out (stdoutput, &opthdr, | |
1222 | (Elf_External_Options *) f); | |
1223 | ||
1224 | mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo)); | |
1225 | } | |
1226 | #endif | |
1227 | } | |
1228 | ||
1229 | if (ECOFF_DEBUGGING) | |
1230 | { | |
1231 | sec = subseg_new (".mdebug", (subsegT) 0); | |
1232 | (void) bfd_set_section_flags (stdoutput, sec, | |
1233 | SEC_HAS_CONTENTS | SEC_READONLY); | |
1234 | (void) bfd_set_section_alignment (stdoutput, sec, 2); | |
1235 | } | |
1236 | ||
1237 | #ifdef MIPS_STABS_ELF | |
1238 | pdr_seg = subseg_new (".pdr", (subsegT) 0); | |
1239 | (void) bfd_set_section_flags (stdoutput, pdr_seg, | |
1240 | SEC_READONLY | SEC_RELOC | SEC_DEBUGGING); | |
1241 | (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2); | |
1242 | #endif | |
1243 | ||
1244 | subseg_set (seg, subseg); | |
1245 | } | |
1246 | } | |
1247 | ||
1248 | if (! ECOFF_DEBUGGING) | |
1249 | md_obj_begin (); | |
1250 | } | |
1251 | ||
1252 | void | |
1253 | md_mips_end () | |
1254 | { | |
1255 | if (! ECOFF_DEBUGGING) | |
1256 | md_obj_end (); | |
1257 | } | |
1258 | ||
1259 | void | |
1260 | md_assemble (str) | |
1261 | char *str; | |
1262 | { | |
1263 | struct mips_cl_insn insn; | |
1264 | ||
1265 | imm_expr.X_op = O_absent; | |
1266 | imm_reloc = BFD_RELOC_UNUSED; | |
1267 | imm_unmatched_hi = false; | |
1268 | offset_expr.X_op = O_absent; | |
1269 | offset_reloc = BFD_RELOC_UNUSED; | |
1270 | ||
1271 | if (mips_opts.mips16) | |
1272 | mips16_ip (str, &insn); | |
1273 | else | |
1274 | { | |
1275 | mips_ip (str, &insn); | |
beae10d5 KH |
1276 | DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"), |
1277 | str, insn.insn_opcode)); | |
252b5132 RH |
1278 | } |
1279 | ||
1280 | if (insn_error) | |
1281 | { | |
1282 | as_bad ("%s `%s'", insn_error, str); | |
1283 | return; | |
1284 | } | |
1285 | ||
1286 | if (insn.insn_mo->pinfo == INSN_MACRO) | |
1287 | { | |
1288 | if (mips_opts.mips16) | |
1289 | mips16_macro (&insn); | |
1290 | else | |
1291 | macro (&insn); | |
1292 | } | |
1293 | else | |
1294 | { | |
1295 | if (imm_expr.X_op != O_absent) | |
1296 | append_insn ((char *) NULL, &insn, &imm_expr, imm_reloc, | |
1297 | imm_unmatched_hi); | |
1298 | else if (offset_expr.X_op != O_absent) | |
1299 | append_insn ((char *) NULL, &insn, &offset_expr, offset_reloc, false); | |
1300 | else | |
1301 | append_insn ((char *) NULL, &insn, NULL, BFD_RELOC_UNUSED, false); | |
1302 | } | |
1303 | } | |
1304 | ||
1305 | /* See whether instruction IP reads register REG. CLASS is the type | |
1306 | of register. */ | |
1307 | ||
1308 | static int | |
1309 | insn_uses_reg (ip, reg, class) | |
1310 | struct mips_cl_insn *ip; | |
1311 | unsigned int reg; | |
1312 | enum mips_regclass class; | |
1313 | { | |
1314 | if (class == MIPS16_REG) | |
1315 | { | |
1316 | assert (mips_opts.mips16); | |
1317 | reg = mips16_to_32_reg_map[reg]; | |
1318 | class = MIPS_GR_REG; | |
1319 | } | |
1320 | ||
1321 | /* Don't report on general register 0, since it never changes. */ | |
1322 | if (class == MIPS_GR_REG && reg == 0) | |
1323 | return 0; | |
1324 | ||
1325 | if (class == MIPS_FP_REG) | |
1326 | { | |
1327 | assert (! mips_opts.mips16); | |
1328 | /* If we are called with either $f0 or $f1, we must check $f0. | |
1329 | This is not optimal, because it will introduce an unnecessary | |
1330 | NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would | |
1331 | need to distinguish reading both $f0 and $f1 or just one of | |
1332 | them. Note that we don't have to check the other way, | |
1333 | because there is no instruction that sets both $f0 and $f1 | |
1334 | and requires a delay. */ | |
1335 | if ((ip->insn_mo->pinfo & INSN_READ_FPR_S) | |
1336 | && ((((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS) &~(unsigned)1) | |
1337 | == (reg &~ (unsigned) 1))) | |
1338 | return 1; | |
1339 | if ((ip->insn_mo->pinfo & INSN_READ_FPR_T) | |
1340 | && ((((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT) &~(unsigned)1) | |
1341 | == (reg &~ (unsigned) 1))) | |
1342 | return 1; | |
1343 | } | |
1344 | else if (! mips_opts.mips16) | |
1345 | { | |
1346 | if ((ip->insn_mo->pinfo & INSN_READ_GPR_S) | |
1347 | && ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == reg) | |
1348 | return 1; | |
1349 | if ((ip->insn_mo->pinfo & INSN_READ_GPR_T) | |
1350 | && ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT) == reg) | |
1351 | return 1; | |
1352 | } | |
1353 | else | |
1354 | { | |
1355 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_X) | |
1356 | && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_RX) | |
1357 | & MIPS16OP_MASK_RX)] | |
1358 | == reg)) | |
1359 | return 1; | |
1360 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Y) | |
1361 | && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_RY) | |
1362 | & MIPS16OP_MASK_RY)] | |
1363 | == reg)) | |
1364 | return 1; | |
1365 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Z) | |
1366 | && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z) | |
1367 | & MIPS16OP_MASK_MOVE32Z)] | |
1368 | == reg)) | |
1369 | return 1; | |
1370 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_T) && reg == TREG) | |
1371 | return 1; | |
1372 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_SP) && reg == SP) | |
1373 | return 1; | |
1374 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_31) && reg == RA) | |
1375 | return 1; | |
1376 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_GPR_X) | |
1377 | && ((ip->insn_opcode >> MIPS16OP_SH_REGR32) | |
1378 | & MIPS16OP_MASK_REGR32) == reg) | |
1379 | return 1; | |
1380 | } | |
1381 | ||
1382 | return 0; | |
1383 | } | |
1384 | ||
1385 | /* This function returns true if modifying a register requires a | |
1386 | delay. */ | |
1387 | ||
1388 | static int | |
1389 | reg_needs_delay (reg) | |
156c2f8b | 1390 | unsigned int reg; |
252b5132 RH |
1391 | { |
1392 | unsigned long prev_pinfo; | |
1393 | ||
1394 | prev_pinfo = prev_insn.insn_mo->pinfo; | |
1395 | if (! mips_opts.noreorder | |
9ce8a5dd | 1396 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 RH |
1397 | && ((prev_pinfo & INSN_LOAD_COPROC_DELAY) |
1398 | || (! gpr_interlocks | |
1399 | && (prev_pinfo & INSN_LOAD_MEMORY_DELAY)))) | |
1400 | { | |
1401 | /* A load from a coprocessor or from memory. All load | |
1402 | delays delay the use of general register rt for one | |
1403 | instruction on the r3000. The r6000 and r4000 use | |
1404 | interlocks. */ | |
bdaaa2e1 | 1405 | /* Itbl support may require additional care here. */ |
252b5132 RH |
1406 | know (prev_pinfo & INSN_WRITE_GPR_T); |
1407 | if (reg == ((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT)) | |
1408 | return 1; | |
1409 | } | |
1410 | ||
1411 | return 0; | |
1412 | } | |
1413 | ||
1414 | /* Mark instruction labels in mips16 mode. This permits the linker to | |
1415 | handle them specially, such as generating jalx instructions when | |
1416 | needed. We also make them odd for the duration of the assembly, in | |
1417 | order to generate the right sort of code. We will make them even | |
1418 | in the adjust_symtab routine, while leaving them marked. This is | |
1419 | convenient for the debugger and the disassembler. The linker knows | |
1420 | to make them odd again. */ | |
1421 | ||
1422 | static void | |
1423 | mips16_mark_labels () | |
1424 | { | |
1425 | if (mips_opts.mips16) | |
1426 | { | |
1427 | struct insn_label_list *l; | |
98aa84af | 1428 | valueT val; |
252b5132 RH |
1429 | |
1430 | for (l = insn_labels; l != NULL; l = l->next) | |
1431 | { | |
1432 | #ifdef OBJ_ELF | |
1433 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
1434 | S_SET_OTHER (l->label, STO_MIPS16); | |
1435 | #endif | |
98aa84af AM |
1436 | val = S_GET_VALUE (l->label); |
1437 | if ((val & 1) == 0) | |
1438 | S_SET_VALUE (l->label, val + 1); | |
252b5132 RH |
1439 | } |
1440 | } | |
1441 | } | |
1442 | ||
1443 | /* Output an instruction. PLACE is where to put the instruction; if | |
1444 | it is NULL, this uses frag_more to get room. IP is the instruction | |
1445 | information. ADDRESS_EXPR is an operand of the instruction to be | |
1446 | used with RELOC_TYPE. */ | |
1447 | ||
1448 | static void | |
1449 | append_insn (place, ip, address_expr, reloc_type, unmatched_hi) | |
1450 | char *place; | |
1451 | struct mips_cl_insn *ip; | |
1452 | expressionS *address_expr; | |
1453 | bfd_reloc_code_real_type reloc_type; | |
1454 | boolean unmatched_hi; | |
1455 | { | |
1456 | register unsigned long prev_pinfo, pinfo; | |
1457 | char *f; | |
1458 | fixS *fixp; | |
1459 | int nops = 0; | |
1460 | ||
1461 | /* Mark instruction labels in mips16 mode. */ | |
1462 | if (mips_opts.mips16) | |
1463 | mips16_mark_labels (); | |
1464 | ||
1465 | prev_pinfo = prev_insn.insn_mo->pinfo; | |
1466 | pinfo = ip->insn_mo->pinfo; | |
1467 | ||
1468 | if (place == NULL && (! mips_opts.noreorder || prev_nop_frag != NULL)) | |
1469 | { | |
1470 | int prev_prev_nop; | |
1471 | ||
1472 | /* If the previous insn required any delay slots, see if we need | |
1473 | to insert a NOP or two. There are eight kinds of possible | |
1474 | hazards, of which an instruction can have at most one type. | |
1475 | (1) a load from memory delay | |
1476 | (2) a load from a coprocessor delay | |
1477 | (3) an unconditional branch delay | |
1478 | (4) a conditional branch delay | |
1479 | (5) a move to coprocessor register delay | |
1480 | (6) a load coprocessor register from memory delay | |
1481 | (7) a coprocessor condition code delay | |
1482 | (8) a HI/LO special register delay | |
1483 | ||
1484 | There are a lot of optimizations we could do that we don't. | |
1485 | In particular, we do not, in general, reorder instructions. | |
1486 | If you use gcc with optimization, it will reorder | |
1487 | instructions and generally do much more optimization then we | |
1488 | do here; repeating all that work in the assembler would only | |
1489 | benefit hand written assembly code, and does not seem worth | |
1490 | it. */ | |
1491 | ||
1492 | /* This is how a NOP is emitted. */ | |
1493 | #define emit_nop() \ | |
1494 | (mips_opts.mips16 \ | |
1495 | ? md_number_to_chars (frag_more (2), 0x6500, 2) \ | |
1496 | : md_number_to_chars (frag_more (4), 0, 4)) | |
1497 | ||
1498 | /* The previous insn might require a delay slot, depending upon | |
1499 | the contents of the current insn. */ | |
1500 | if (! mips_opts.mips16 | |
9ce8a5dd | 1501 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 RH |
1502 | && (((prev_pinfo & INSN_LOAD_COPROC_DELAY) |
1503 | && ! cop_interlocks) | |
1504 | || (! gpr_interlocks | |
1505 | && (prev_pinfo & INSN_LOAD_MEMORY_DELAY)))) | |
1506 | { | |
1507 | /* A load from a coprocessor or from memory. All load | |
1508 | delays delay the use of general register rt for one | |
1509 | instruction on the r3000. The r6000 and r4000 use | |
1510 | interlocks. */ | |
beae10d5 | 1511 | /* Itbl support may require additional care here. */ |
252b5132 RH |
1512 | know (prev_pinfo & INSN_WRITE_GPR_T); |
1513 | if (mips_optimize == 0 | |
1514 | || insn_uses_reg (ip, | |
1515 | ((prev_insn.insn_opcode >> OP_SH_RT) | |
1516 | & OP_MASK_RT), | |
1517 | MIPS_GR_REG)) | |
1518 | ++nops; | |
1519 | } | |
1520 | else if (! mips_opts.mips16 | |
9ce8a5dd | 1521 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 | 1522 | && (((prev_pinfo & INSN_COPROC_MOVE_DELAY) |
beae10d5 | 1523 | && ! cop_interlocks) |
e7af610e | 1524 | || (mips_opts.isa == ISA_MIPS1 |
252b5132 RH |
1525 | && (prev_pinfo & INSN_COPROC_MEMORY_DELAY)))) |
1526 | { | |
1527 | /* A generic coprocessor delay. The previous instruction | |
1528 | modified a coprocessor general or control register. If | |
1529 | it modified a control register, we need to avoid any | |
1530 | coprocessor instruction (this is probably not always | |
1531 | required, but it sometimes is). If it modified a general | |
1532 | register, we avoid using that register. | |
1533 | ||
1534 | On the r6000 and r4000 loading a coprocessor register | |
1535 | from memory is interlocked, and does not require a delay. | |
1536 | ||
1537 | This case is not handled very well. There is no special | |
1538 | knowledge of CP0 handling, and the coprocessors other | |
1539 | than the floating point unit are not distinguished at | |
1540 | all. */ | |
1541 | /* Itbl support may require additional care here. FIXME! | |
bdaaa2e1 | 1542 | Need to modify this to include knowledge about |
252b5132 RH |
1543 | user specified delays! */ |
1544 | if (prev_pinfo & INSN_WRITE_FPR_T) | |
1545 | { | |
1546 | if (mips_optimize == 0 | |
1547 | || insn_uses_reg (ip, | |
1548 | ((prev_insn.insn_opcode >> OP_SH_FT) | |
1549 | & OP_MASK_FT), | |
1550 | MIPS_FP_REG)) | |
1551 | ++nops; | |
1552 | } | |
1553 | else if (prev_pinfo & INSN_WRITE_FPR_S) | |
1554 | { | |
1555 | if (mips_optimize == 0 | |
1556 | || insn_uses_reg (ip, | |
1557 | ((prev_insn.insn_opcode >> OP_SH_FS) | |
1558 | & OP_MASK_FS), | |
1559 | MIPS_FP_REG)) | |
1560 | ++nops; | |
1561 | } | |
1562 | else | |
1563 | { | |
1564 | /* We don't know exactly what the previous instruction | |
1565 | does. If the current instruction uses a coprocessor | |
1566 | register, we must insert a NOP. If previous | |
1567 | instruction may set the condition codes, and the | |
1568 | current instruction uses them, we must insert two | |
1569 | NOPS. */ | |
bdaaa2e1 | 1570 | /* Itbl support may require additional care here. */ |
252b5132 RH |
1571 | if (mips_optimize == 0 |
1572 | || ((prev_pinfo & INSN_WRITE_COND_CODE) | |
1573 | && (pinfo & INSN_READ_COND_CODE))) | |
1574 | nops += 2; | |
1575 | else if (pinfo & INSN_COP) | |
1576 | ++nops; | |
1577 | } | |
1578 | } | |
1579 | else if (! mips_opts.mips16 | |
9ce8a5dd | 1580 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 RH |
1581 | && (prev_pinfo & INSN_WRITE_COND_CODE) |
1582 | && ! cop_interlocks) | |
1583 | { | |
1584 | /* The previous instruction sets the coprocessor condition | |
1585 | codes, but does not require a general coprocessor delay | |
1586 | (this means it is a floating point comparison | |
1587 | instruction). If this instruction uses the condition | |
1588 | codes, we need to insert a single NOP. */ | |
beae10d5 | 1589 | /* Itbl support may require additional care here. */ |
252b5132 RH |
1590 | if (mips_optimize == 0 |
1591 | || (pinfo & INSN_READ_COND_CODE)) | |
1592 | ++nops; | |
1593 | } | |
6b76fefe CM |
1594 | |
1595 | /* If we're fixing up mfhi/mflo for the r7000 and the | |
1596 | previous insn was an mfhi/mflo and the current insn | |
1597 | reads the register that the mfhi/mflo wrote to, then | |
1598 | insert two nops. */ | |
1599 | ||
1600 | else if (mips_7000_hilo_fix | |
1601 | && MF_HILO_INSN (prev_pinfo) | |
1602 | && insn_uses_reg (ip, ((prev_insn.insn_opcode >> OP_SH_RD) | |
beae10d5 KH |
1603 | & OP_MASK_RD), |
1604 | MIPS_GR_REG)) | |
6b76fefe CM |
1605 | { |
1606 | nops += 2; | |
1607 | } | |
1608 | ||
1609 | /* If we're fixing up mfhi/mflo for the r7000 and the | |
1610 | 2nd previous insn was an mfhi/mflo and the current insn | |
1611 | reads the register that the mfhi/mflo wrote to, then | |
1612 | insert one nop. */ | |
1613 | ||
1614 | else if (mips_7000_hilo_fix | |
1615 | && MF_HILO_INSN (prev_prev_insn.insn_opcode) | |
1616 | && insn_uses_reg (ip, ((prev_prev_insn.insn_opcode >> OP_SH_RD) | |
1617 | & OP_MASK_RD), | |
1618 | MIPS_GR_REG)) | |
bdaaa2e1 | 1619 | |
6b76fefe CM |
1620 | { |
1621 | nops += 1; | |
1622 | } | |
bdaaa2e1 | 1623 | |
252b5132 RH |
1624 | else if (prev_pinfo & INSN_READ_LO) |
1625 | { | |
1626 | /* The previous instruction reads the LO register; if the | |
1627 | current instruction writes to the LO register, we must | |
bdaaa2e1 KH |
1628 | insert two NOPS. Some newer processors have interlocks. |
1629 | Also the tx39's multiply instructions can be exectuted | |
252b5132 | 1630 | immediatly after a read from HI/LO (without the delay), |
bdaaa2e1 KH |
1631 | though the tx39's divide insns still do require the |
1632 | delay. */ | |
252b5132 | 1633 | if (! (hilo_interlocks |
ec68c924 | 1634 | || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT))) |
252b5132 RH |
1635 | && (mips_optimize == 0 |
1636 | || (pinfo & INSN_WRITE_LO))) | |
1637 | nops += 2; | |
1638 | /* Most mips16 branch insns don't have a delay slot. | |
1639 | If a read from LO is immediately followed by a branch | |
1640 | to a write to LO we have a read followed by a write | |
1641 | less than 2 insns away. We assume the target of | |
1642 | a branch might be a write to LO, and insert a nop | |
bdaaa2e1 | 1643 | between a read and an immediately following branch. */ |
252b5132 RH |
1644 | else if (mips_opts.mips16 |
1645 | && (mips_optimize == 0 | |
1646 | || (pinfo & MIPS16_INSN_BRANCH))) | |
1647 | nops += 1; | |
1648 | } | |
1649 | else if (prev_insn.insn_mo->pinfo & INSN_READ_HI) | |
1650 | { | |
1651 | /* The previous instruction reads the HI register; if the | |
1652 | current instruction writes to the HI register, we must | |
1653 | insert a NOP. Some newer processors have interlocks. | |
bdaaa2e1 | 1654 | Also the note tx39's multiply above. */ |
252b5132 | 1655 | if (! (hilo_interlocks |
ec68c924 | 1656 | || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT))) |
252b5132 RH |
1657 | && (mips_optimize == 0 |
1658 | || (pinfo & INSN_WRITE_HI))) | |
1659 | nops += 2; | |
1660 | /* Most mips16 branch insns don't have a delay slot. | |
1661 | If a read from HI is immediately followed by a branch | |
1662 | to a write to HI we have a read followed by a write | |
1663 | less than 2 insns away. We assume the target of | |
1664 | a branch might be a write to HI, and insert a nop | |
bdaaa2e1 | 1665 | between a read and an immediately following branch. */ |
252b5132 RH |
1666 | else if (mips_opts.mips16 |
1667 | && (mips_optimize == 0 | |
1668 | || (pinfo & MIPS16_INSN_BRANCH))) | |
1669 | nops += 1; | |
1670 | } | |
1671 | ||
1672 | /* If the previous instruction was in a noreorder section, then | |
1673 | we don't want to insert the nop after all. */ | |
bdaaa2e1 | 1674 | /* Itbl support may require additional care here. */ |
252b5132 RH |
1675 | if (prev_insn_unreordered) |
1676 | nops = 0; | |
1677 | ||
1678 | /* There are two cases which require two intervening | |
1679 | instructions: 1) setting the condition codes using a move to | |
1680 | coprocessor instruction which requires a general coprocessor | |
1681 | delay and then reading the condition codes 2) reading the HI | |
1682 | or LO register and then writing to it (except on processors | |
1683 | which have interlocks). If we are not already emitting a NOP | |
1684 | instruction, we must check for these cases compared to the | |
1685 | instruction previous to the previous instruction. */ | |
1686 | if ((! mips_opts.mips16 | |
9ce8a5dd | 1687 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 RH |
1688 | && (prev_prev_insn.insn_mo->pinfo & INSN_COPROC_MOVE_DELAY) |
1689 | && (prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE) | |
1690 | && (pinfo & INSN_READ_COND_CODE) | |
1691 | && ! cop_interlocks) | |
1692 | || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_LO) | |
1693 | && (pinfo & INSN_WRITE_LO) | |
1694 | && ! (hilo_interlocks | |
ec68c924 | 1695 | || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT)))) |
252b5132 RH |
1696 | || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI) |
1697 | && (pinfo & INSN_WRITE_HI) | |
1698 | && ! (hilo_interlocks | |
ec68c924 | 1699 | || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT))))) |
252b5132 RH |
1700 | prev_prev_nop = 1; |
1701 | else | |
1702 | prev_prev_nop = 0; | |
1703 | ||
1704 | if (prev_prev_insn_unreordered) | |
1705 | prev_prev_nop = 0; | |
1706 | ||
1707 | if (prev_prev_nop && nops == 0) | |
1708 | ++nops; | |
1709 | ||
1710 | /* If we are being given a nop instruction, don't bother with | |
1711 | one of the nops we would otherwise output. This will only | |
1712 | happen when a nop instruction is used with mips_optimize set | |
1713 | to 0. */ | |
1714 | if (nops > 0 | |
1715 | && ! mips_opts.noreorder | |
156c2f8b | 1716 | && ip->insn_opcode == (unsigned) (mips_opts.mips16 ? 0x6500 : 0)) |
252b5132 RH |
1717 | --nops; |
1718 | ||
1719 | /* Now emit the right number of NOP instructions. */ | |
1720 | if (nops > 0 && ! mips_opts.noreorder) | |
1721 | { | |
1722 | fragS *old_frag; | |
1723 | unsigned long old_frag_offset; | |
1724 | int i; | |
1725 | struct insn_label_list *l; | |
1726 | ||
1727 | old_frag = frag_now; | |
1728 | old_frag_offset = frag_now_fix (); | |
1729 | ||
1730 | for (i = 0; i < nops; i++) | |
1731 | emit_nop (); | |
1732 | ||
1733 | if (listing) | |
1734 | { | |
1735 | listing_prev_line (); | |
1736 | /* We may be at the start of a variant frag. In case we | |
1737 | are, make sure there is enough space for the frag | |
1738 | after the frags created by listing_prev_line. The | |
1739 | argument to frag_grow here must be at least as large | |
1740 | as the argument to all other calls to frag_grow in | |
1741 | this file. We don't have to worry about being in the | |
1742 | middle of a variant frag, because the variants insert | |
1743 | all needed nop instructions themselves. */ | |
1744 | frag_grow (40); | |
1745 | } | |
1746 | ||
1747 | for (l = insn_labels; l != NULL; l = l->next) | |
1748 | { | |
98aa84af AM |
1749 | valueT val; |
1750 | ||
252b5132 | 1751 | assert (S_GET_SEGMENT (l->label) == now_seg); |
49309057 | 1752 | symbol_set_frag (l->label, frag_now); |
98aa84af | 1753 | val = (valueT) frag_now_fix (); |
252b5132 RH |
1754 | /* mips16 text labels are stored as odd. */ |
1755 | if (mips_opts.mips16) | |
98aa84af AM |
1756 | val += 1; |
1757 | S_SET_VALUE (l->label, val); | |
252b5132 RH |
1758 | } |
1759 | ||
1760 | #ifndef NO_ECOFF_DEBUGGING | |
1761 | if (ECOFF_DEBUGGING) | |
1762 | ecoff_fix_loc (old_frag, old_frag_offset); | |
1763 | #endif | |
1764 | } | |
1765 | else if (prev_nop_frag != NULL) | |
1766 | { | |
1767 | /* We have a frag holding nops we may be able to remove. If | |
1768 | we don't need any nops, we can decrease the size of | |
1769 | prev_nop_frag by the size of one instruction. If we do | |
bdaaa2e1 | 1770 | need some nops, we count them in prev_nops_required. */ |
252b5132 RH |
1771 | if (prev_nop_frag_since == 0) |
1772 | { | |
1773 | if (nops == 0) | |
1774 | { | |
1775 | prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4; | |
1776 | --prev_nop_frag_holds; | |
1777 | } | |
1778 | else | |
1779 | prev_nop_frag_required += nops; | |
1780 | } | |
1781 | else | |
1782 | { | |
1783 | if (prev_prev_nop == 0) | |
1784 | { | |
1785 | prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4; | |
1786 | --prev_nop_frag_holds; | |
1787 | } | |
1788 | else | |
1789 | ++prev_nop_frag_required; | |
1790 | } | |
1791 | ||
1792 | if (prev_nop_frag_holds <= prev_nop_frag_required) | |
1793 | prev_nop_frag = NULL; | |
1794 | ||
1795 | ++prev_nop_frag_since; | |
1796 | ||
1797 | /* Sanity check: by the time we reach the second instruction | |
1798 | after prev_nop_frag, we should have used up all the nops | |
1799 | one way or another. */ | |
1800 | assert (prev_nop_frag_since <= 1 || prev_nop_frag == NULL); | |
1801 | } | |
1802 | } | |
1803 | ||
1804 | if (reloc_type > BFD_RELOC_UNUSED) | |
1805 | { | |
1806 | /* We need to set up a variant frag. */ | |
1807 | assert (mips_opts.mips16 && address_expr != NULL); | |
1808 | f = frag_var (rs_machine_dependent, 4, 0, | |
1809 | RELAX_MIPS16_ENCODE (reloc_type - BFD_RELOC_UNUSED, | |
1810 | mips16_small, mips16_ext, | |
1811 | (prev_pinfo | |
1812 | & INSN_UNCOND_BRANCH_DELAY), | |
1813 | (prev_insn_reloc_type | |
1814 | == BFD_RELOC_MIPS16_JMP)), | |
1815 | make_expr_symbol (address_expr), (offsetT) 0, | |
1816 | (char *) NULL); | |
1817 | } | |
1818 | else if (place != NULL) | |
1819 | f = place; | |
1820 | else if (mips_opts.mips16 | |
1821 | && ! ip->use_extend | |
1822 | && reloc_type != BFD_RELOC_MIPS16_JMP) | |
1823 | { | |
1824 | /* Make sure there is enough room to swap this instruction with | |
1825 | a following jump instruction. */ | |
1826 | frag_grow (6); | |
1827 | f = frag_more (2); | |
1828 | } | |
1829 | else | |
1830 | { | |
1831 | if (mips_opts.mips16 | |
1832 | && mips_opts.noreorder | |
1833 | && (prev_pinfo & INSN_UNCOND_BRANCH_DELAY) != 0) | |
1834 | as_warn (_("extended instruction in delay slot")); | |
1835 | ||
1836 | f = frag_more (4); | |
1837 | } | |
1838 | ||
1839 | fixp = NULL; | |
1840 | if (address_expr != NULL && reloc_type < BFD_RELOC_UNUSED) | |
1841 | { | |
1842 | if (address_expr->X_op == O_constant) | |
1843 | { | |
1844 | switch (reloc_type) | |
1845 | { | |
1846 | case BFD_RELOC_32: | |
1847 | ip->insn_opcode |= address_expr->X_add_number; | |
1848 | break; | |
1849 | ||
1850 | case BFD_RELOC_LO16: | |
1851 | ip->insn_opcode |= address_expr->X_add_number & 0xffff; | |
1852 | break; | |
1853 | ||
1854 | case BFD_RELOC_MIPS_JMP: | |
1855 | if ((address_expr->X_add_number & 3) != 0) | |
1856 | as_bad (_("jump to misaligned address (0x%lx)"), | |
1857 | (unsigned long) address_expr->X_add_number); | |
1858 | ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0x3ffffff; | |
1859 | break; | |
1860 | ||
1861 | case BFD_RELOC_MIPS16_JMP: | |
1862 | if ((address_expr->X_add_number & 3) != 0) | |
1863 | as_bad (_("jump to misaligned address (0x%lx)"), | |
1864 | (unsigned long) address_expr->X_add_number); | |
1865 | ip->insn_opcode |= | |
1866 | (((address_expr->X_add_number & 0x7c0000) << 3) | |
1867 | | ((address_expr->X_add_number & 0xf800000) >> 7) | |
1868 | | ((address_expr->X_add_number & 0x3fffc) >> 2)); | |
1869 | break; | |
1870 | ||
252b5132 RH |
1871 | case BFD_RELOC_16_PCREL_S2: |
1872 | goto need_reloc; | |
1873 | ||
1874 | default: | |
1875 | internalError (); | |
1876 | } | |
1877 | } | |
1878 | else | |
1879 | { | |
1880 | need_reloc: | |
1881 | /* Don't generate a reloc if we are writing into a variant | |
1882 | frag. */ | |
1883 | if (place == NULL) | |
1884 | { | |
1885 | fixp = fix_new_exp (frag_now, f - frag_now->fr_literal, 4, | |
1886 | address_expr, | |
1887 | reloc_type == BFD_RELOC_16_PCREL_S2, | |
1888 | reloc_type); | |
1889 | if (unmatched_hi) | |
1890 | { | |
1891 | struct mips_hi_fixup *hi_fixup; | |
1892 | ||
1893 | assert (reloc_type == BFD_RELOC_HI16_S); | |
1894 | hi_fixup = ((struct mips_hi_fixup *) | |
1895 | xmalloc (sizeof (struct mips_hi_fixup))); | |
1896 | hi_fixup->fixp = fixp; | |
1897 | hi_fixup->seg = now_seg; | |
1898 | hi_fixup->next = mips_hi_fixup_list; | |
1899 | mips_hi_fixup_list = hi_fixup; | |
1900 | } | |
1901 | } | |
1902 | } | |
1903 | } | |
1904 | ||
1905 | if (! mips_opts.mips16) | |
1906 | md_number_to_chars (f, ip->insn_opcode, 4); | |
1907 | else if (reloc_type == BFD_RELOC_MIPS16_JMP) | |
1908 | { | |
1909 | md_number_to_chars (f, ip->insn_opcode >> 16, 2); | |
1910 | md_number_to_chars (f + 2, ip->insn_opcode & 0xffff, 2); | |
1911 | } | |
1912 | else | |
1913 | { | |
1914 | if (ip->use_extend) | |
1915 | { | |
1916 | md_number_to_chars (f, 0xf000 | ip->extend, 2); | |
1917 | f += 2; | |
1918 | } | |
1919 | md_number_to_chars (f, ip->insn_opcode, 2); | |
1920 | } | |
1921 | ||
1922 | /* Update the register mask information. */ | |
1923 | if (! mips_opts.mips16) | |
1924 | { | |
1925 | if (pinfo & INSN_WRITE_GPR_D) | |
1926 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD); | |
1927 | if ((pinfo & (INSN_WRITE_GPR_T | INSN_READ_GPR_T)) != 0) | |
1928 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT); | |
1929 | if (pinfo & INSN_READ_GPR_S) | |
1930 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS); | |
1931 | if (pinfo & INSN_WRITE_GPR_31) | |
1932 | mips_gprmask |= 1 << 31; | |
1933 | if (pinfo & INSN_WRITE_FPR_D) | |
1934 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FD) & OP_MASK_FD); | |
1935 | if ((pinfo & (INSN_WRITE_FPR_S | INSN_READ_FPR_S)) != 0) | |
1936 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS); | |
1937 | if ((pinfo & (INSN_WRITE_FPR_T | INSN_READ_FPR_T)) != 0) | |
1938 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT); | |
1939 | if ((pinfo & INSN_READ_FPR_R) != 0) | |
1940 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FR) & OP_MASK_FR); | |
1941 | if (pinfo & INSN_COP) | |
1942 | { | |
bdaaa2e1 KH |
1943 | /* We don't keep enough information to sort these cases out. |
1944 | The itbl support does keep this information however, although | |
1945 | we currently don't support itbl fprmats as part of the cop | |
1946 | instruction. May want to add this support in the future. */ | |
252b5132 RH |
1947 | } |
1948 | /* Never set the bit for $0, which is always zero. */ | |
beae10d5 | 1949 | mips_gprmask &= ~1 << 0; |
252b5132 RH |
1950 | } |
1951 | else | |
1952 | { | |
1953 | if (pinfo & (MIPS16_INSN_WRITE_X | MIPS16_INSN_READ_X)) | |
1954 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RX) | |
1955 | & MIPS16OP_MASK_RX); | |
1956 | if (pinfo & (MIPS16_INSN_WRITE_Y | MIPS16_INSN_READ_Y)) | |
1957 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RY) | |
1958 | & MIPS16OP_MASK_RY); | |
1959 | if (pinfo & MIPS16_INSN_WRITE_Z) | |
1960 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RZ) | |
1961 | & MIPS16OP_MASK_RZ); | |
1962 | if (pinfo & (MIPS16_INSN_WRITE_T | MIPS16_INSN_READ_T)) | |
1963 | mips_gprmask |= 1 << TREG; | |
1964 | if (pinfo & (MIPS16_INSN_WRITE_SP | MIPS16_INSN_READ_SP)) | |
1965 | mips_gprmask |= 1 << SP; | |
1966 | if (pinfo & (MIPS16_INSN_WRITE_31 | MIPS16_INSN_READ_31)) | |
1967 | mips_gprmask |= 1 << RA; | |
1968 | if (pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
1969 | mips_gprmask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode); | |
1970 | if (pinfo & MIPS16_INSN_READ_Z) | |
1971 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z) | |
1972 | & MIPS16OP_MASK_MOVE32Z); | |
1973 | if (pinfo & MIPS16_INSN_READ_GPR_X) | |
1974 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_REGR32) | |
1975 | & MIPS16OP_MASK_REGR32); | |
1976 | } | |
1977 | ||
1978 | if (place == NULL && ! mips_opts.noreorder) | |
1979 | { | |
1980 | /* Filling the branch delay slot is more complex. We try to | |
1981 | switch the branch with the previous instruction, which we can | |
1982 | do if the previous instruction does not set up a condition | |
1983 | that the branch tests and if the branch is not itself the | |
1984 | target of any branch. */ | |
1985 | if ((pinfo & INSN_UNCOND_BRANCH_DELAY) | |
1986 | || (pinfo & INSN_COND_BRANCH_DELAY)) | |
1987 | { | |
1988 | if (mips_optimize < 2 | |
1989 | /* If we have seen .set volatile or .set nomove, don't | |
1990 | optimize. */ | |
1991 | || mips_opts.nomove != 0 | |
1992 | /* If we had to emit any NOP instructions, then we | |
1993 | already know we can not swap. */ | |
1994 | || nops != 0 | |
1995 | /* If we don't even know the previous insn, we can not | |
bdaaa2e1 | 1996 | swap. */ |
252b5132 RH |
1997 | || ! prev_insn_valid |
1998 | /* If the previous insn is already in a branch delay | |
1999 | slot, then we can not swap. */ | |
2000 | || prev_insn_is_delay_slot | |
2001 | /* If the previous previous insn was in a .set | |
2002 | noreorder, we can't swap. Actually, the MIPS | |
2003 | assembler will swap in this situation. However, gcc | |
2004 | configured -with-gnu-as will generate code like | |
2005 | .set noreorder | |
2006 | lw $4,XXX | |
2007 | .set reorder | |
2008 | INSN | |
2009 | bne $4,$0,foo | |
2010 | in which we can not swap the bne and INSN. If gcc is | |
2011 | not configured -with-gnu-as, it does not output the | |
2012 | .set pseudo-ops. We don't have to check | |
2013 | prev_insn_unreordered, because prev_insn_valid will | |
2014 | be 0 in that case. We don't want to use | |
2015 | prev_prev_insn_valid, because we do want to be able | |
2016 | to swap at the start of a function. */ | |
2017 | || prev_prev_insn_unreordered | |
2018 | /* If the branch is itself the target of a branch, we | |
2019 | can not swap. We cheat on this; all we check for is | |
2020 | whether there is a label on this instruction. If | |
2021 | there are any branches to anything other than a | |
2022 | label, users must use .set noreorder. */ | |
2023 | || insn_labels != NULL | |
2024 | /* If the previous instruction is in a variant frag, we | |
2025 | can not do the swap. This does not apply to the | |
2026 | mips16, which uses variant frags for different | |
2027 | purposes. */ | |
2028 | || (! mips_opts.mips16 | |
2029 | && prev_insn_frag->fr_type == rs_machine_dependent) | |
2030 | /* If the branch reads the condition codes, we don't | |
2031 | even try to swap, because in the sequence | |
2032 | ctc1 $X,$31 | |
2033 | INSN | |
2034 | INSN | |
2035 | bc1t LABEL | |
2036 | we can not swap, and I don't feel like handling that | |
2037 | case. */ | |
2038 | || (! mips_opts.mips16 | |
9ce8a5dd | 2039 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 RH |
2040 | && (pinfo & INSN_READ_COND_CODE)) |
2041 | /* We can not swap with an instruction that requires a | |
2042 | delay slot, becase the target of the branch might | |
2043 | interfere with that instruction. */ | |
2044 | || (! mips_opts.mips16 | |
9ce8a5dd | 2045 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 | 2046 | && (prev_pinfo |
bdaaa2e1 | 2047 | /* Itbl support may require additional care here. */ |
252b5132 RH |
2048 | & (INSN_LOAD_COPROC_DELAY |
2049 | | INSN_COPROC_MOVE_DELAY | |
2050 | | INSN_WRITE_COND_CODE))) | |
2051 | || (! (hilo_interlocks | |
ec68c924 | 2052 | || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT))) |
252b5132 RH |
2053 | && (prev_pinfo |
2054 | & (INSN_READ_LO | |
2055 | | INSN_READ_HI))) | |
2056 | || (! mips_opts.mips16 | |
2057 | && ! gpr_interlocks | |
2058 | && (prev_pinfo & INSN_LOAD_MEMORY_DELAY)) | |
2059 | || (! mips_opts.mips16 | |
e7af610e | 2060 | && mips_opts.isa == ISA_MIPS1 |
bdaaa2e1 | 2061 | /* Itbl support may require additional care here. */ |
252b5132 RH |
2062 | && (prev_pinfo & INSN_COPROC_MEMORY_DELAY)) |
2063 | /* We can not swap with a branch instruction. */ | |
2064 | || (prev_pinfo | |
2065 | & (INSN_UNCOND_BRANCH_DELAY | |
2066 | | INSN_COND_BRANCH_DELAY | |
2067 | | INSN_COND_BRANCH_LIKELY)) | |
2068 | /* We do not swap with a trap instruction, since it | |
2069 | complicates trap handlers to have the trap | |
2070 | instruction be in a delay slot. */ | |
2071 | || (prev_pinfo & INSN_TRAP) | |
2072 | /* If the branch reads a register that the previous | |
2073 | instruction sets, we can not swap. */ | |
2074 | || (! mips_opts.mips16 | |
2075 | && (prev_pinfo & INSN_WRITE_GPR_T) | |
2076 | && insn_uses_reg (ip, | |
2077 | ((prev_insn.insn_opcode >> OP_SH_RT) | |
2078 | & OP_MASK_RT), | |
2079 | MIPS_GR_REG)) | |
2080 | || (! mips_opts.mips16 | |
2081 | && (prev_pinfo & INSN_WRITE_GPR_D) | |
2082 | && insn_uses_reg (ip, | |
2083 | ((prev_insn.insn_opcode >> OP_SH_RD) | |
2084 | & OP_MASK_RD), | |
2085 | MIPS_GR_REG)) | |
2086 | || (mips_opts.mips16 | |
2087 | && (((prev_pinfo & MIPS16_INSN_WRITE_X) | |
2088 | && insn_uses_reg (ip, | |
2089 | ((prev_insn.insn_opcode | |
2090 | >> MIPS16OP_SH_RX) | |
2091 | & MIPS16OP_MASK_RX), | |
2092 | MIPS16_REG)) | |
2093 | || ((prev_pinfo & MIPS16_INSN_WRITE_Y) | |
2094 | && insn_uses_reg (ip, | |
2095 | ((prev_insn.insn_opcode | |
2096 | >> MIPS16OP_SH_RY) | |
2097 | & MIPS16OP_MASK_RY), | |
2098 | MIPS16_REG)) | |
2099 | || ((prev_pinfo & MIPS16_INSN_WRITE_Z) | |
2100 | && insn_uses_reg (ip, | |
2101 | ((prev_insn.insn_opcode | |
2102 | >> MIPS16OP_SH_RZ) | |
2103 | & MIPS16OP_MASK_RZ), | |
2104 | MIPS16_REG)) | |
2105 | || ((prev_pinfo & MIPS16_INSN_WRITE_T) | |
2106 | && insn_uses_reg (ip, TREG, MIPS_GR_REG)) | |
2107 | || ((prev_pinfo & MIPS16_INSN_WRITE_31) | |
2108 | && insn_uses_reg (ip, RA, MIPS_GR_REG)) | |
2109 | || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
2110 | && insn_uses_reg (ip, | |
2111 | MIPS16OP_EXTRACT_REG32R (prev_insn. | |
2112 | insn_opcode), | |
2113 | MIPS_GR_REG)))) | |
2114 | /* If the branch writes a register that the previous | |
2115 | instruction sets, we can not swap (we know that | |
2116 | branches write only to RD or to $31). */ | |
2117 | || (! mips_opts.mips16 | |
2118 | && (prev_pinfo & INSN_WRITE_GPR_T) | |
2119 | && (((pinfo & INSN_WRITE_GPR_D) | |
2120 | && (((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT) | |
2121 | == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD))) | |
2122 | || ((pinfo & INSN_WRITE_GPR_31) | |
2123 | && (((prev_insn.insn_opcode >> OP_SH_RT) | |
2124 | & OP_MASK_RT) | |
2125 | == 31)))) | |
2126 | || (! mips_opts.mips16 | |
2127 | && (prev_pinfo & INSN_WRITE_GPR_D) | |
2128 | && (((pinfo & INSN_WRITE_GPR_D) | |
2129 | && (((prev_insn.insn_opcode >> OP_SH_RD) & OP_MASK_RD) | |
2130 | == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD))) | |
2131 | || ((pinfo & INSN_WRITE_GPR_31) | |
2132 | && (((prev_insn.insn_opcode >> OP_SH_RD) | |
2133 | & OP_MASK_RD) | |
2134 | == 31)))) | |
2135 | || (mips_opts.mips16 | |
2136 | && (pinfo & MIPS16_INSN_WRITE_31) | |
2137 | && ((prev_pinfo & MIPS16_INSN_WRITE_31) | |
2138 | || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
2139 | && (MIPS16OP_EXTRACT_REG32R (prev_insn.insn_opcode) | |
2140 | == RA)))) | |
2141 | /* If the branch writes a register that the previous | |
2142 | instruction reads, we can not swap (we know that | |
2143 | branches only write to RD or to $31). */ | |
2144 | || (! mips_opts.mips16 | |
2145 | && (pinfo & INSN_WRITE_GPR_D) | |
2146 | && insn_uses_reg (&prev_insn, | |
2147 | ((ip->insn_opcode >> OP_SH_RD) | |
2148 | & OP_MASK_RD), | |
2149 | MIPS_GR_REG)) | |
2150 | || (! mips_opts.mips16 | |
2151 | && (pinfo & INSN_WRITE_GPR_31) | |
2152 | && insn_uses_reg (&prev_insn, 31, MIPS_GR_REG)) | |
2153 | || (mips_opts.mips16 | |
2154 | && (pinfo & MIPS16_INSN_WRITE_31) | |
2155 | && insn_uses_reg (&prev_insn, RA, MIPS_GR_REG)) | |
2156 | /* If we are generating embedded PIC code, the branch | |
2157 | might be expanded into a sequence which uses $at, so | |
2158 | we can't swap with an instruction which reads it. */ | |
2159 | || (mips_pic == EMBEDDED_PIC | |
2160 | && insn_uses_reg (&prev_insn, AT, MIPS_GR_REG)) | |
2161 | /* If the previous previous instruction has a load | |
2162 | delay, and sets a register that the branch reads, we | |
2163 | can not swap. */ | |
2164 | || (! mips_opts.mips16 | |
9ce8a5dd | 2165 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
bdaaa2e1 | 2166 | /* Itbl support may require additional care here. */ |
252b5132 RH |
2167 | && ((prev_prev_insn.insn_mo->pinfo & INSN_LOAD_COPROC_DELAY) |
2168 | || (! gpr_interlocks | |
2169 | && (prev_prev_insn.insn_mo->pinfo | |
2170 | & INSN_LOAD_MEMORY_DELAY))) | |
2171 | && insn_uses_reg (ip, | |
2172 | ((prev_prev_insn.insn_opcode >> OP_SH_RT) | |
2173 | & OP_MASK_RT), | |
2174 | MIPS_GR_REG)) | |
2175 | /* If one instruction sets a condition code and the | |
2176 | other one uses a condition code, we can not swap. */ | |
2177 | || ((pinfo & INSN_READ_COND_CODE) | |
2178 | && (prev_pinfo & INSN_WRITE_COND_CODE)) | |
2179 | || ((pinfo & INSN_WRITE_COND_CODE) | |
2180 | && (prev_pinfo & INSN_READ_COND_CODE)) | |
2181 | /* If the previous instruction uses the PC, we can not | |
2182 | swap. */ | |
2183 | || (mips_opts.mips16 | |
2184 | && (prev_pinfo & MIPS16_INSN_READ_PC)) | |
2185 | /* If the previous instruction was extended, we can not | |
2186 | swap. */ | |
2187 | || (mips_opts.mips16 && prev_insn_extended) | |
2188 | /* If the previous instruction had a fixup in mips16 | |
2189 | mode, we can not swap. This normally means that the | |
2190 | previous instruction was a 4 byte branch anyhow. */ | |
2191 | || (mips_opts.mips16 && prev_insn_fixp) | |
bdaaa2e1 KH |
2192 | /* If the previous instruction is a sync, sync.l, or |
2193 | sync.p, we can not swap. */ | |
f173e82e | 2194 | || (prev_pinfo & INSN_SYNC)) |
252b5132 RH |
2195 | { |
2196 | /* We could do even better for unconditional branches to | |
2197 | portions of this object file; we could pick up the | |
2198 | instruction at the destination, put it in the delay | |
2199 | slot, and bump the destination address. */ | |
2200 | emit_nop (); | |
2201 | /* Update the previous insn information. */ | |
2202 | prev_prev_insn = *ip; | |
2203 | prev_insn.insn_mo = &dummy_opcode; | |
2204 | } | |
2205 | else | |
2206 | { | |
2207 | /* It looks like we can actually do the swap. */ | |
2208 | if (! mips_opts.mips16) | |
2209 | { | |
2210 | char *prev_f; | |
2211 | char temp[4]; | |
2212 | ||
2213 | prev_f = prev_insn_frag->fr_literal + prev_insn_where; | |
2214 | memcpy (temp, prev_f, 4); | |
2215 | memcpy (prev_f, f, 4); | |
2216 | memcpy (f, temp, 4); | |
2217 | if (prev_insn_fixp) | |
2218 | { | |
2219 | prev_insn_fixp->fx_frag = frag_now; | |
2220 | prev_insn_fixp->fx_where = f - frag_now->fr_literal; | |
2221 | } | |
2222 | if (fixp) | |
2223 | { | |
2224 | fixp->fx_frag = prev_insn_frag; | |
2225 | fixp->fx_where = prev_insn_where; | |
2226 | } | |
2227 | } | |
2228 | else | |
2229 | { | |
2230 | char *prev_f; | |
2231 | char temp[2]; | |
2232 | ||
2233 | assert (prev_insn_fixp == NULL); | |
2234 | prev_f = prev_insn_frag->fr_literal + prev_insn_where; | |
2235 | memcpy (temp, prev_f, 2); | |
2236 | memcpy (prev_f, f, 2); | |
2237 | if (reloc_type != BFD_RELOC_MIPS16_JMP) | |
2238 | { | |
2239 | assert (reloc_type == BFD_RELOC_UNUSED); | |
2240 | memcpy (f, temp, 2); | |
2241 | } | |
2242 | else | |
2243 | { | |
2244 | memcpy (f, f + 2, 2); | |
2245 | memcpy (f + 2, temp, 2); | |
2246 | } | |
2247 | if (fixp) | |
2248 | { | |
2249 | fixp->fx_frag = prev_insn_frag; | |
2250 | fixp->fx_where = prev_insn_where; | |
2251 | } | |
2252 | } | |
2253 | ||
2254 | /* Update the previous insn information; leave prev_insn | |
2255 | unchanged. */ | |
2256 | prev_prev_insn = *ip; | |
2257 | } | |
2258 | prev_insn_is_delay_slot = 1; | |
2259 | ||
2260 | /* If that was an unconditional branch, forget the previous | |
2261 | insn information. */ | |
2262 | if (pinfo & INSN_UNCOND_BRANCH_DELAY) | |
2263 | { | |
2264 | prev_prev_insn.insn_mo = &dummy_opcode; | |
2265 | prev_insn.insn_mo = &dummy_opcode; | |
2266 | } | |
2267 | ||
2268 | prev_insn_fixp = NULL; | |
2269 | prev_insn_reloc_type = BFD_RELOC_UNUSED; | |
2270 | prev_insn_extended = 0; | |
2271 | } | |
2272 | else if (pinfo & INSN_COND_BRANCH_LIKELY) | |
2273 | { | |
2274 | /* We don't yet optimize a branch likely. What we should do | |
2275 | is look at the target, copy the instruction found there | |
2276 | into the delay slot, and increment the branch to jump to | |
2277 | the next instruction. */ | |
2278 | emit_nop (); | |
2279 | /* Update the previous insn information. */ | |
2280 | prev_prev_insn = *ip; | |
2281 | prev_insn.insn_mo = &dummy_opcode; | |
2282 | prev_insn_fixp = NULL; | |
2283 | prev_insn_reloc_type = BFD_RELOC_UNUSED; | |
2284 | prev_insn_extended = 0; | |
2285 | } | |
2286 | else | |
2287 | { | |
2288 | /* Update the previous insn information. */ | |
2289 | if (nops > 0) | |
2290 | prev_prev_insn.insn_mo = &dummy_opcode; | |
2291 | else | |
2292 | prev_prev_insn = prev_insn; | |
2293 | prev_insn = *ip; | |
2294 | ||
2295 | /* Any time we see a branch, we always fill the delay slot | |
2296 | immediately; since this insn is not a branch, we know it | |
2297 | is not in a delay slot. */ | |
2298 | prev_insn_is_delay_slot = 0; | |
2299 | ||
2300 | prev_insn_fixp = fixp; | |
2301 | prev_insn_reloc_type = reloc_type; | |
2302 | if (mips_opts.mips16) | |
2303 | prev_insn_extended = (ip->use_extend | |
2304 | || reloc_type > BFD_RELOC_UNUSED); | |
2305 | } | |
2306 | ||
2307 | prev_prev_insn_unreordered = prev_insn_unreordered; | |
2308 | prev_insn_unreordered = 0; | |
2309 | prev_insn_frag = frag_now; | |
2310 | prev_insn_where = f - frag_now->fr_literal; | |
2311 | prev_insn_valid = 1; | |
2312 | } | |
2313 | else if (place == NULL) | |
2314 | { | |
2315 | /* We need to record a bit of information even when we are not | |
2316 | reordering, in order to determine the base address for mips16 | |
2317 | PC relative relocs. */ | |
2318 | prev_prev_insn = prev_insn; | |
2319 | prev_insn = *ip; | |
2320 | prev_insn_reloc_type = reloc_type; | |
2321 | prev_prev_insn_unreordered = prev_insn_unreordered; | |
2322 | prev_insn_unreordered = 1; | |
2323 | } | |
2324 | ||
2325 | /* We just output an insn, so the next one doesn't have a label. */ | |
2326 | mips_clear_insn_labels (); | |
2327 | ||
2328 | /* We must ensure that a fixup associated with an unmatched %hi | |
2329 | reloc does not become a variant frag. Otherwise, the | |
2330 | rearrangement of %hi relocs in frob_file may confuse | |
2331 | tc_gen_reloc. */ | |
2332 | if (unmatched_hi) | |
2333 | { | |
2334 | frag_wane (frag_now); | |
2335 | frag_new (0); | |
2336 | } | |
2337 | } | |
2338 | ||
2339 | /* This function forgets that there was any previous instruction or | |
2340 | label. If PRESERVE is non-zero, it remembers enough information to | |
bdaaa2e1 | 2341 | know whether nops are needed before a noreorder section. */ |
252b5132 RH |
2342 | |
2343 | static void | |
2344 | mips_no_prev_insn (preserve) | |
2345 | int preserve; | |
2346 | { | |
2347 | if (! preserve) | |
2348 | { | |
2349 | prev_insn.insn_mo = &dummy_opcode; | |
2350 | prev_prev_insn.insn_mo = &dummy_opcode; | |
2351 | prev_nop_frag = NULL; | |
2352 | prev_nop_frag_holds = 0; | |
2353 | prev_nop_frag_required = 0; | |
2354 | prev_nop_frag_since = 0; | |
2355 | } | |
2356 | prev_insn_valid = 0; | |
2357 | prev_insn_is_delay_slot = 0; | |
2358 | prev_insn_unreordered = 0; | |
2359 | prev_insn_extended = 0; | |
2360 | prev_insn_reloc_type = BFD_RELOC_UNUSED; | |
2361 | prev_prev_insn_unreordered = 0; | |
2362 | mips_clear_insn_labels (); | |
2363 | } | |
2364 | ||
2365 | /* This function must be called whenever we turn on noreorder or emit | |
2366 | something other than instructions. It inserts any NOPS which might | |
2367 | be needed by the previous instruction, and clears the information | |
2368 | kept for the previous instructions. The INSNS parameter is true if | |
bdaaa2e1 | 2369 | instructions are to follow. */ |
252b5132 RH |
2370 | |
2371 | static void | |
2372 | mips_emit_delays (insns) | |
2373 | boolean insns; | |
2374 | { | |
2375 | if (! mips_opts.noreorder) | |
2376 | { | |
2377 | int nops; | |
2378 | ||
2379 | nops = 0; | |
2380 | if ((! mips_opts.mips16 | |
9ce8a5dd | 2381 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 RH |
2382 | && (! cop_interlocks |
2383 | && (prev_insn.insn_mo->pinfo | |
2384 | & (INSN_LOAD_COPROC_DELAY | |
2385 | | INSN_COPROC_MOVE_DELAY | |
2386 | | INSN_WRITE_COND_CODE)))) | |
2387 | || (! hilo_interlocks | |
2388 | && (prev_insn.insn_mo->pinfo | |
2389 | & (INSN_READ_LO | |
2390 | | INSN_READ_HI))) | |
2391 | || (! mips_opts.mips16 | |
2392 | && ! gpr_interlocks | |
bdaaa2e1 | 2393 | && (prev_insn.insn_mo->pinfo |
252b5132 RH |
2394 | & INSN_LOAD_MEMORY_DELAY)) |
2395 | || (! mips_opts.mips16 | |
e7af610e | 2396 | && mips_opts.isa == ISA_MIPS1 |
252b5132 RH |
2397 | && (prev_insn.insn_mo->pinfo |
2398 | & INSN_COPROC_MEMORY_DELAY))) | |
2399 | { | |
beae10d5 | 2400 | /* Itbl support may require additional care here. */ |
252b5132 RH |
2401 | ++nops; |
2402 | if ((! mips_opts.mips16 | |
9ce8a5dd | 2403 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 RH |
2404 | && (! cop_interlocks |
2405 | && prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)) | |
2406 | || (! hilo_interlocks | |
2407 | && ((prev_insn.insn_mo->pinfo & INSN_READ_HI) | |
2408 | || (prev_insn.insn_mo->pinfo & INSN_READ_LO)))) | |
2409 | ++nops; | |
2410 | ||
2411 | if (prev_insn_unreordered) | |
2412 | nops = 0; | |
2413 | } | |
2414 | else if ((! mips_opts.mips16 | |
9ce8a5dd | 2415 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 RH |
2416 | && (! cop_interlocks |
2417 | && prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)) | |
2418 | || (! hilo_interlocks | |
2419 | && ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI) | |
2420 | || (prev_prev_insn.insn_mo->pinfo & INSN_READ_LO)))) | |
2421 | { | |
beae10d5 | 2422 | /* Itbl support may require additional care here. */ |
252b5132 RH |
2423 | if (! prev_prev_insn_unreordered) |
2424 | ++nops; | |
2425 | } | |
2426 | ||
2427 | if (nops > 0) | |
2428 | { | |
2429 | struct insn_label_list *l; | |
2430 | ||
2431 | if (insns) | |
2432 | { | |
2433 | /* Record the frag which holds the nop instructions, so | |
2434 | that we can remove them if we don't need them. */ | |
2435 | frag_grow (mips_opts.mips16 ? nops * 2 : nops * 4); | |
2436 | prev_nop_frag = frag_now; | |
2437 | prev_nop_frag_holds = nops; | |
2438 | prev_nop_frag_required = 0; | |
2439 | prev_nop_frag_since = 0; | |
2440 | } | |
2441 | ||
2442 | for (; nops > 0; --nops) | |
2443 | emit_nop (); | |
2444 | ||
2445 | if (insns) | |
2446 | { | |
2447 | /* Move on to a new frag, so that it is safe to simply | |
bdaaa2e1 | 2448 | decrease the size of prev_nop_frag. */ |
252b5132 RH |
2449 | frag_wane (frag_now); |
2450 | frag_new (0); | |
2451 | } | |
2452 | ||
2453 | for (l = insn_labels; l != NULL; l = l->next) | |
2454 | { | |
98aa84af AM |
2455 | valueT val; |
2456 | ||
252b5132 | 2457 | assert (S_GET_SEGMENT (l->label) == now_seg); |
49309057 | 2458 | symbol_set_frag (l->label, frag_now); |
98aa84af | 2459 | val = (valueT) frag_now_fix (); |
252b5132 RH |
2460 | /* mips16 text labels are stored as odd. */ |
2461 | if (mips_opts.mips16) | |
98aa84af AM |
2462 | val += 1; |
2463 | S_SET_VALUE (l->label, val); | |
252b5132 RH |
2464 | } |
2465 | } | |
2466 | } | |
2467 | ||
2468 | /* Mark instruction labels in mips16 mode. */ | |
2469 | if (mips_opts.mips16 && insns) | |
2470 | mips16_mark_labels (); | |
2471 | ||
2472 | mips_no_prev_insn (insns); | |
2473 | } | |
2474 | ||
2475 | /* Build an instruction created by a macro expansion. This is passed | |
2476 | a pointer to the count of instructions created so far, an | |
2477 | expression, the name of the instruction to build, an operand format | |
2478 | string, and corresponding arguments. */ | |
2479 | ||
2480 | #ifdef USE_STDARG | |
2481 | static void | |
2482 | macro_build (char *place, | |
2483 | int *counter, | |
2484 | expressionS * ep, | |
2485 | const char *name, | |
2486 | const char *fmt, | |
2487 | ...) | |
2488 | #else | |
2489 | static void | |
2490 | macro_build (place, counter, ep, name, fmt, va_alist) | |
2491 | char *place; | |
2492 | int *counter; | |
2493 | expressionS *ep; | |
2494 | const char *name; | |
2495 | const char *fmt; | |
2496 | va_dcl | |
2497 | #endif | |
2498 | { | |
2499 | struct mips_cl_insn insn; | |
2500 | bfd_reloc_code_real_type r; | |
2501 | va_list args; | |
252b5132 RH |
2502 | |
2503 | #ifdef USE_STDARG | |
2504 | va_start (args, fmt); | |
2505 | #else | |
2506 | va_start (args); | |
2507 | #endif | |
2508 | ||
2509 | /* | |
2510 | * If the macro is about to expand into a second instruction, | |
2511 | * print a warning if needed. We need to pass ip as a parameter | |
2512 | * to generate a better warning message here... | |
2513 | */ | |
2514 | if (mips_opts.warn_about_macros && place == NULL && *counter == 1) | |
2515 | as_warn (_("Macro instruction expanded into multiple instructions")); | |
2516 | ||
2517 | if (place == NULL) | |
2518 | *counter += 1; /* bump instruction counter */ | |
2519 | ||
2520 | if (mips_opts.mips16) | |
2521 | { | |
2522 | mips16_macro_build (place, counter, ep, name, fmt, args); | |
2523 | va_end (args); | |
2524 | return; | |
2525 | } | |
2526 | ||
2527 | r = BFD_RELOC_UNUSED; | |
2528 | insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name); | |
2529 | assert (insn.insn_mo); | |
2530 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
2531 | ||
2532 | /* Search until we get a match for NAME. */ | |
2533 | while (1) | |
2534 | { | |
252b5132 RH |
2535 | if (strcmp (fmt, insn.insn_mo->args) == 0 |
2536 | && insn.insn_mo->pinfo != INSN_MACRO | |
ea1fb5dc | 2537 | && OPCODE_IS_MEMBER (insn.insn_mo, mips_opts.isa, mips_arch) |
ec68c924 | 2538 | && (mips_arch != CPU_R4650 || (insn.insn_mo->pinfo & FP_D) == 0)) |
252b5132 RH |
2539 | break; |
2540 | ||
2541 | ++insn.insn_mo; | |
2542 | assert (insn.insn_mo->name); | |
2543 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
2544 | } | |
2545 | ||
2546 | insn.insn_opcode = insn.insn_mo->match; | |
2547 | for (;;) | |
2548 | { | |
2549 | switch (*fmt++) | |
2550 | { | |
2551 | case '\0': | |
2552 | break; | |
2553 | ||
2554 | case ',': | |
2555 | case '(': | |
2556 | case ')': | |
2557 | continue; | |
2558 | ||
2559 | case 't': | |
2560 | case 'w': | |
2561 | case 'E': | |
38487616 | 2562 | insn.insn_opcode |= va_arg (args, int) << OP_SH_RT; |
252b5132 RH |
2563 | continue; |
2564 | ||
2565 | case 'c': | |
38487616 TS |
2566 | insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE; |
2567 | continue; | |
2568 | ||
252b5132 RH |
2569 | case 'T': |
2570 | case 'W': | |
38487616 | 2571 | insn.insn_opcode |= va_arg (args, int) << OP_SH_FT; |
252b5132 RH |
2572 | continue; |
2573 | ||
2574 | case 'd': | |
2575 | case 'G': | |
38487616 | 2576 | insn.insn_opcode |= va_arg (args, int) << OP_SH_RD; |
252b5132 RH |
2577 | continue; |
2578 | ||
4372b673 NC |
2579 | case 'U': |
2580 | { | |
2581 | int tmp = va_arg (args, int); | |
2582 | ||
38487616 TS |
2583 | insn.insn_opcode |= tmp << OP_SH_RT; |
2584 | insn.insn_opcode |= tmp << OP_SH_RD; | |
beae10d5 | 2585 | continue; |
4372b673 NC |
2586 | } |
2587 | ||
252b5132 RH |
2588 | case 'V': |
2589 | case 'S': | |
38487616 | 2590 | insn.insn_opcode |= va_arg (args, int) << OP_SH_FS; |
252b5132 RH |
2591 | continue; |
2592 | ||
2593 | case 'z': | |
2594 | continue; | |
2595 | ||
2596 | case '<': | |
38487616 | 2597 | insn.insn_opcode |= va_arg (args, int) << OP_SH_SHAMT; |
252b5132 RH |
2598 | continue; |
2599 | ||
2600 | case 'D': | |
38487616 | 2601 | insn.insn_opcode |= va_arg (args, int) << OP_SH_FD; |
252b5132 RH |
2602 | continue; |
2603 | ||
2604 | case 'B': | |
38487616 | 2605 | insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE20; |
252b5132 RH |
2606 | continue; |
2607 | ||
4372b673 | 2608 | case 'J': |
38487616 | 2609 | insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE19; |
4372b673 NC |
2610 | continue; |
2611 | ||
252b5132 | 2612 | case 'q': |
38487616 | 2613 | insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE2; |
252b5132 RH |
2614 | continue; |
2615 | ||
2616 | case 'b': | |
2617 | case 's': | |
2618 | case 'r': | |
2619 | case 'v': | |
38487616 | 2620 | insn.insn_opcode |= va_arg (args, int) << OP_SH_RS; |
252b5132 RH |
2621 | continue; |
2622 | ||
2623 | case 'i': | |
2624 | case 'j': | |
2625 | case 'o': | |
2626 | r = (bfd_reloc_code_real_type) va_arg (args, int); | |
2627 | assert (r == BFD_RELOC_MIPS_GPREL | |
2628 | || r == BFD_RELOC_MIPS_LITERAL | |
2629 | || r == BFD_RELOC_LO16 | |
2630 | || r == BFD_RELOC_MIPS_GOT16 | |
2631 | || r == BFD_RELOC_MIPS_CALL16 | |
2632 | || r == BFD_RELOC_MIPS_GOT_LO16 | |
2633 | || r == BFD_RELOC_MIPS_CALL_LO16 | |
2634 | || (ep->X_op == O_subtract | |
252b5132 RH |
2635 | && r == BFD_RELOC_PCREL_LO16)); |
2636 | continue; | |
2637 | ||
2638 | case 'u': | |
2639 | r = (bfd_reloc_code_real_type) va_arg (args, int); | |
2640 | assert (ep != NULL | |
2641 | && (ep->X_op == O_constant | |
2642 | || (ep->X_op == O_symbol | |
2643 | && (r == BFD_RELOC_HI16_S | |
2644 | || r == BFD_RELOC_HI16 | |
2645 | || r == BFD_RELOC_MIPS_GOT_HI16 | |
2646 | || r == BFD_RELOC_MIPS_CALL_HI16)) | |
2647 | || (ep->X_op == O_subtract | |
252b5132 RH |
2648 | && r == BFD_RELOC_PCREL_HI16_S))); |
2649 | if (ep->X_op == O_constant) | |
2650 | { | |
2651 | insn.insn_opcode |= (ep->X_add_number >> 16) & 0xffff; | |
2652 | ep = NULL; | |
2653 | r = BFD_RELOC_UNUSED; | |
2654 | } | |
2655 | continue; | |
2656 | ||
2657 | case 'p': | |
2658 | assert (ep != NULL); | |
2659 | /* | |
2660 | * This allows macro() to pass an immediate expression for | |
2661 | * creating short branches without creating a symbol. | |
2662 | * Note that the expression still might come from the assembly | |
2663 | * input, in which case the value is not checked for range nor | |
2664 | * is a relocation entry generated (yuck). | |
2665 | */ | |
2666 | if (ep->X_op == O_constant) | |
2667 | { | |
2668 | insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff; | |
2669 | ep = NULL; | |
2670 | } | |
2671 | else | |
2672 | r = BFD_RELOC_16_PCREL_S2; | |
2673 | continue; | |
2674 | ||
2675 | case 'a': | |
2676 | assert (ep != NULL); | |
2677 | r = BFD_RELOC_MIPS_JMP; | |
2678 | continue; | |
2679 | ||
2680 | case 'C': | |
2681 | insn.insn_opcode |= va_arg (args, unsigned long); | |
2682 | continue; | |
2683 | ||
2684 | default: | |
2685 | internalError (); | |
2686 | } | |
2687 | break; | |
2688 | } | |
2689 | va_end (args); | |
2690 | assert (r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); | |
2691 | ||
2692 | append_insn (place, &insn, ep, r, false); | |
2693 | } | |
2694 | ||
2695 | static void | |
2696 | mips16_macro_build (place, counter, ep, name, fmt, args) | |
2697 | char *place; | |
43841e91 | 2698 | int *counter ATTRIBUTE_UNUSED; |
252b5132 RH |
2699 | expressionS *ep; |
2700 | const char *name; | |
2701 | const char *fmt; | |
2702 | va_list args; | |
2703 | { | |
2704 | struct mips_cl_insn insn; | |
2705 | bfd_reloc_code_real_type r; | |
2706 | ||
2707 | r = BFD_RELOC_UNUSED; | |
2708 | insn.insn_mo = (struct mips_opcode *) hash_find (mips16_op_hash, name); | |
2709 | assert (insn.insn_mo); | |
2710 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
2711 | ||
2712 | while (strcmp (fmt, insn.insn_mo->args) != 0 | |
2713 | || insn.insn_mo->pinfo == INSN_MACRO) | |
2714 | { | |
2715 | ++insn.insn_mo; | |
2716 | assert (insn.insn_mo->name); | |
2717 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
2718 | } | |
2719 | ||
2720 | insn.insn_opcode = insn.insn_mo->match; | |
2721 | insn.use_extend = false; | |
2722 | ||
2723 | for (;;) | |
2724 | { | |
2725 | int c; | |
2726 | ||
2727 | c = *fmt++; | |
2728 | switch (c) | |
2729 | { | |
2730 | case '\0': | |
2731 | break; | |
2732 | ||
2733 | case ',': | |
2734 | case '(': | |
2735 | case ')': | |
2736 | continue; | |
2737 | ||
2738 | case 'y': | |
2739 | case 'w': | |
2740 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RY; | |
2741 | continue; | |
2742 | ||
2743 | case 'x': | |
2744 | case 'v': | |
2745 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RX; | |
2746 | continue; | |
2747 | ||
2748 | case 'z': | |
2749 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RZ; | |
2750 | continue; | |
2751 | ||
2752 | case 'Z': | |
2753 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_MOVE32Z; | |
2754 | continue; | |
2755 | ||
2756 | case '0': | |
2757 | case 'S': | |
2758 | case 'P': | |
2759 | case 'R': | |
2760 | continue; | |
2761 | ||
2762 | case 'X': | |
2763 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_REGR32; | |
2764 | continue; | |
2765 | ||
2766 | case 'Y': | |
2767 | { | |
2768 | int regno; | |
2769 | ||
2770 | regno = va_arg (args, int); | |
2771 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); | |
2772 | insn.insn_opcode |= regno << MIPS16OP_SH_REG32R; | |
2773 | } | |
2774 | continue; | |
2775 | ||
2776 | case '<': | |
2777 | case '>': | |
2778 | case '4': | |
2779 | case '5': | |
2780 | case 'H': | |
2781 | case 'W': | |
2782 | case 'D': | |
2783 | case 'j': | |
2784 | case '8': | |
2785 | case 'V': | |
2786 | case 'C': | |
2787 | case 'U': | |
2788 | case 'k': | |
2789 | case 'K': | |
2790 | case 'p': | |
2791 | case 'q': | |
2792 | { | |
2793 | assert (ep != NULL); | |
2794 | ||
2795 | if (ep->X_op != O_constant) | |
2796 | r = BFD_RELOC_UNUSED + c; | |
2797 | else | |
2798 | { | |
2799 | mips16_immed ((char *) NULL, 0, c, ep->X_add_number, false, | |
2800 | false, false, &insn.insn_opcode, | |
2801 | &insn.use_extend, &insn.extend); | |
2802 | ep = NULL; | |
2803 | r = BFD_RELOC_UNUSED; | |
2804 | } | |
2805 | } | |
2806 | continue; | |
2807 | ||
2808 | case '6': | |
2809 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_IMM6; | |
2810 | continue; | |
2811 | } | |
2812 | ||
2813 | break; | |
2814 | } | |
2815 | ||
2816 | assert (r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); | |
2817 | ||
2818 | append_insn (place, &insn, ep, r, false); | |
2819 | } | |
2820 | ||
2821 | /* | |
2822 | * Generate a "lui" instruction. | |
2823 | */ | |
2824 | static void | |
2825 | macro_build_lui (place, counter, ep, regnum) | |
2826 | char *place; | |
2827 | int *counter; | |
2828 | expressionS *ep; | |
2829 | int regnum; | |
2830 | { | |
2831 | expressionS high_expr; | |
2832 | struct mips_cl_insn insn; | |
2833 | bfd_reloc_code_real_type r; | |
2834 | CONST char *name = "lui"; | |
2835 | CONST char *fmt = "t,u"; | |
2836 | ||
2837 | assert (! mips_opts.mips16); | |
2838 | ||
2839 | if (place == NULL) | |
2840 | high_expr = *ep; | |
2841 | else | |
2842 | { | |
2843 | high_expr.X_op = O_constant; | |
2844 | high_expr.X_add_number = ep->X_add_number; | |
2845 | } | |
2846 | ||
2847 | if (high_expr.X_op == O_constant) | |
2848 | { | |
2849 | /* we can compute the instruction now without a relocation entry */ | |
2850 | if (high_expr.X_add_number & 0x8000) | |
2851 | high_expr.X_add_number += 0x10000; | |
2852 | high_expr.X_add_number = | |
2853 | ((unsigned long) high_expr.X_add_number >> 16) & 0xffff; | |
2854 | r = BFD_RELOC_UNUSED; | |
2855 | } | |
2856 | else | |
2857 | { | |
2858 | assert (ep->X_op == O_symbol); | |
2859 | /* _gp_disp is a special case, used from s_cpload. */ | |
2860 | assert (mips_pic == NO_PIC | |
2861 | || strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0); | |
2862 | r = BFD_RELOC_HI16_S; | |
2863 | } | |
2864 | ||
2865 | /* | |
2866 | * If the macro is about to expand into a second instruction, | |
2867 | * print a warning if needed. We need to pass ip as a parameter | |
2868 | * to generate a better warning message here... | |
2869 | */ | |
2870 | if (mips_opts.warn_about_macros && place == NULL && *counter == 1) | |
2871 | as_warn (_("Macro instruction expanded into multiple instructions")); | |
2872 | ||
2873 | if (place == NULL) | |
2874 | *counter += 1; /* bump instruction counter */ | |
2875 | ||
2876 | insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name); | |
2877 | assert (insn.insn_mo); | |
2878 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
2879 | assert (strcmp (fmt, insn.insn_mo->args) == 0); | |
2880 | ||
2881 | insn.insn_opcode = insn.insn_mo->match | (regnum << OP_SH_RT); | |
2882 | if (r == BFD_RELOC_UNUSED) | |
2883 | { | |
2884 | insn.insn_opcode |= high_expr.X_add_number; | |
2885 | append_insn (place, &insn, NULL, r, false); | |
2886 | } | |
2887 | else | |
2888 | append_insn (place, &insn, &high_expr, r, false); | |
2889 | } | |
2890 | ||
2891 | /* set_at() | |
2892 | * Generates code to set the $at register to true (one) | |
2893 | * if reg is less than the immediate expression. | |
2894 | */ | |
2895 | static void | |
2896 | set_at (counter, reg, unsignedp) | |
2897 | int *counter; | |
2898 | int reg; | |
2899 | int unsignedp; | |
2900 | { | |
2901 | if (imm_expr.X_op == O_constant | |
2902 | && imm_expr.X_add_number >= -0x8000 | |
2903 | && imm_expr.X_add_number < 0x8000) | |
2904 | macro_build ((char *) NULL, counter, &imm_expr, | |
2905 | unsignedp ? "sltiu" : "slti", | |
2906 | "t,r,j", AT, reg, (int) BFD_RELOC_LO16); | |
2907 | else | |
2908 | { | |
2909 | load_register (counter, AT, &imm_expr, 0); | |
2910 | macro_build ((char *) NULL, counter, NULL, | |
2911 | unsignedp ? "sltu" : "slt", | |
2912 | "d,v,t", AT, reg, AT); | |
2913 | } | |
2914 | } | |
2915 | ||
2916 | /* Warn if an expression is not a constant. */ | |
2917 | ||
2918 | static void | |
2919 | check_absolute_expr (ip, ex) | |
2920 | struct mips_cl_insn *ip; | |
2921 | expressionS *ex; | |
2922 | { | |
2923 | if (ex->X_op == O_big) | |
2924 | as_bad (_("unsupported large constant")); | |
2925 | else if (ex->X_op != O_constant) | |
2926 | as_bad (_("Instruction %s requires absolute expression"), ip->insn_mo->name); | |
2927 | } | |
2928 | ||
2929 | /* Count the leading zeroes by performing a binary chop. This is a | |
2930 | bulky bit of source, but performance is a LOT better for the | |
2931 | majority of values than a simple loop to count the bits: | |
2932 | for (lcnt = 0; (lcnt < 32); lcnt++) | |
2933 | if ((v) & (1 << (31 - lcnt))) | |
2934 | break; | |
2935 | However it is not code size friendly, and the gain will drop a bit | |
2936 | on certain cached systems. | |
2937 | */ | |
2938 | #define COUNT_TOP_ZEROES(v) \ | |
2939 | (((v) & ~0xffff) == 0 \ | |
2940 | ? ((v) & ~0xff) == 0 \ | |
2941 | ? ((v) & ~0xf) == 0 \ | |
2942 | ? ((v) & ~0x3) == 0 \ | |
2943 | ? ((v) & ~0x1) == 0 \ | |
2944 | ? !(v) \ | |
2945 | ? 32 \ | |
2946 | : 31 \ | |
2947 | : 30 \ | |
2948 | : ((v) & ~0x7) == 0 \ | |
2949 | ? 29 \ | |
2950 | : 28 \ | |
2951 | : ((v) & ~0x3f) == 0 \ | |
2952 | ? ((v) & ~0x1f) == 0 \ | |
2953 | ? 27 \ | |
2954 | : 26 \ | |
2955 | : ((v) & ~0x7f) == 0 \ | |
2956 | ? 25 \ | |
2957 | : 24 \ | |
2958 | : ((v) & ~0xfff) == 0 \ | |
2959 | ? ((v) & ~0x3ff) == 0 \ | |
2960 | ? ((v) & ~0x1ff) == 0 \ | |
2961 | ? 23 \ | |
2962 | : 22 \ | |
2963 | : ((v) & ~0x7ff) == 0 \ | |
2964 | ? 21 \ | |
2965 | : 20 \ | |
2966 | : ((v) & ~0x3fff) == 0 \ | |
2967 | ? ((v) & ~0x1fff) == 0 \ | |
2968 | ? 19 \ | |
2969 | : 18 \ | |
2970 | : ((v) & ~0x7fff) == 0 \ | |
2971 | ? 17 \ | |
2972 | : 16 \ | |
2973 | : ((v) & ~0xffffff) == 0 \ | |
2974 | ? ((v) & ~0xfffff) == 0 \ | |
2975 | ? ((v) & ~0x3ffff) == 0 \ | |
2976 | ? ((v) & ~0x1ffff) == 0 \ | |
2977 | ? 15 \ | |
2978 | : 14 \ | |
2979 | : ((v) & ~0x7ffff) == 0 \ | |
2980 | ? 13 \ | |
2981 | : 12 \ | |
2982 | : ((v) & ~0x3fffff) == 0 \ | |
2983 | ? ((v) & ~0x1fffff) == 0 \ | |
2984 | ? 11 \ | |
2985 | : 10 \ | |
2986 | : ((v) & ~0x7fffff) == 0 \ | |
2987 | ? 9 \ | |
2988 | : 8 \ | |
2989 | : ((v) & ~0xfffffff) == 0 \ | |
2990 | ? ((v) & ~0x3ffffff) == 0 \ | |
2991 | ? ((v) & ~0x1ffffff) == 0 \ | |
2992 | ? 7 \ | |
2993 | : 6 \ | |
2994 | : ((v) & ~0x7ffffff) == 0 \ | |
2995 | ? 5 \ | |
2996 | : 4 \ | |
2997 | : ((v) & ~0x3fffffff) == 0 \ | |
2998 | ? ((v) & ~0x1fffffff) == 0 \ | |
2999 | ? 3 \ | |
3000 | : 2 \ | |
3001 | : ((v) & ~0x7fffffff) == 0 \ | |
3002 | ? 1 \ | |
3003 | : 0) | |
3004 | ||
3005 | /* load_register() | |
3006 | * This routine generates the least number of instructions neccessary to load | |
3007 | * an absolute expression value into a register. | |
3008 | */ | |
3009 | static void | |
3010 | load_register (counter, reg, ep, dbl) | |
3011 | int *counter; | |
3012 | int reg; | |
3013 | expressionS *ep; | |
3014 | int dbl; | |
3015 | { | |
3016 | int freg; | |
3017 | expressionS hi32, lo32; | |
3018 | ||
3019 | if (ep->X_op != O_big) | |
3020 | { | |
3021 | assert (ep->X_op == O_constant); | |
3022 | if (ep->X_add_number < 0x8000 | |
3023 | && (ep->X_add_number >= 0 | |
3024 | || (ep->X_add_number >= -0x8000 | |
3025 | && (! dbl | |
3026 | || ! ep->X_unsigned | |
3027 | || sizeof (ep->X_add_number) > 4)))) | |
3028 | { | |
3029 | /* We can handle 16 bit signed values with an addiu to | |
3030 | $zero. No need to ever use daddiu here, since $zero and | |
3031 | the result are always correct in 32 bit mode. */ | |
3032 | macro_build ((char *) NULL, counter, ep, "addiu", "t,r,j", reg, 0, | |
3033 | (int) BFD_RELOC_LO16); | |
3034 | return; | |
3035 | } | |
3036 | else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000) | |
3037 | { | |
3038 | /* We can handle 16 bit unsigned values with an ori to | |
3039 | $zero. */ | |
3040 | macro_build ((char *) NULL, counter, ep, "ori", "t,r,i", reg, 0, | |
3041 | (int) BFD_RELOC_LO16); | |
3042 | return; | |
3043 | } | |
3044 | else if ((((ep->X_add_number &~ (offsetT) 0x7fffffff) == 0 | |
3045 | || ((ep->X_add_number &~ (offsetT) 0x7fffffff) | |
3046 | == ~ (offsetT) 0x7fffffff)) | |
3047 | && (! dbl | |
3048 | || ! ep->X_unsigned | |
3049 | || sizeof (ep->X_add_number) > 4 | |
3050 | || (ep->X_add_number & 0x80000000) == 0)) | |
ca4e0257 | 3051 | || ((HAVE_32BIT_GPRS || ! dbl) |
252b5132 | 3052 | && (ep->X_add_number &~ (offsetT) 0xffffffff) == 0) |
ca4e0257 | 3053 | || (HAVE_32BIT_GPRS |
252b5132 RH |
3054 | && ! dbl |
3055 | && ((ep->X_add_number &~ (offsetT) 0xffffffff) | |
3056 | == ~ (offsetT) 0xffffffff))) | |
3057 | { | |
3058 | /* 32 bit values require an lui. */ | |
3059 | macro_build ((char *) NULL, counter, ep, "lui", "t,u", reg, | |
3060 | (int) BFD_RELOC_HI16); | |
3061 | if ((ep->X_add_number & 0xffff) != 0) | |
3062 | macro_build ((char *) NULL, counter, ep, "ori", "t,r,i", reg, reg, | |
3063 | (int) BFD_RELOC_LO16); | |
3064 | return; | |
3065 | } | |
3066 | } | |
3067 | ||
3068 | /* The value is larger than 32 bits. */ | |
3069 | ||
ca4e0257 | 3070 | if (HAVE_32BIT_GPRS) |
252b5132 RH |
3071 | { |
3072 | as_bad (_("Number larger than 32 bits")); | |
3073 | macro_build ((char *) NULL, counter, ep, "addiu", "t,r,j", reg, 0, | |
3074 | (int) BFD_RELOC_LO16); | |
3075 | return; | |
3076 | } | |
3077 | ||
3078 | if (ep->X_op != O_big) | |
3079 | { | |
3080 | hi32 = *ep; | |
3081 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
3082 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
3083 | hi32.X_add_number &= 0xffffffff; | |
3084 | lo32 = *ep; | |
3085 | lo32.X_add_number &= 0xffffffff; | |
3086 | } | |
3087 | else | |
3088 | { | |
3089 | assert (ep->X_add_number > 2); | |
3090 | if (ep->X_add_number == 3) | |
3091 | generic_bignum[3] = 0; | |
3092 | else if (ep->X_add_number > 4) | |
3093 | as_bad (_("Number larger than 64 bits")); | |
3094 | lo32.X_op = O_constant; | |
3095 | lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16); | |
3096 | hi32.X_op = O_constant; | |
3097 | hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16); | |
3098 | } | |
3099 | ||
3100 | if (hi32.X_add_number == 0) | |
3101 | freg = 0; | |
3102 | else | |
3103 | { | |
3104 | int shift, bit; | |
3105 | unsigned long hi, lo; | |
3106 | ||
3107 | if (hi32.X_add_number == 0xffffffff) | |
beae10d5 KH |
3108 | { |
3109 | if ((lo32.X_add_number & 0xffff8000) == 0xffff8000) | |
3110 | { | |
3111 | macro_build ((char *) NULL, counter, &lo32, "addiu", "t,r,j", | |
252b5132 | 3112 | reg, 0, (int) BFD_RELOC_LO16); |
beae10d5 KH |
3113 | return; |
3114 | } | |
3115 | if (lo32.X_add_number & 0x80000000) | |
3116 | { | |
3117 | macro_build ((char *) NULL, counter, &lo32, "lui", "t,u", reg, | |
3118 | (int) BFD_RELOC_HI16); | |
252b5132 RH |
3119 | if (lo32.X_add_number & 0xffff) |
3120 | macro_build ((char *) NULL, counter, &lo32, "ori", "t,r,i", | |
3121 | reg, reg, (int) BFD_RELOC_LO16); | |
beae10d5 KH |
3122 | return; |
3123 | } | |
3124 | } | |
252b5132 RH |
3125 | |
3126 | /* Check for 16bit shifted constant. We know that hi32 is | |
3127 | non-zero, so start the mask on the first bit of the hi32 | |
3128 | value. */ | |
3129 | shift = 17; | |
3130 | do | |
beae10d5 KH |
3131 | { |
3132 | unsigned long himask, lomask; | |
3133 | ||
3134 | if (shift < 32) | |
3135 | { | |
3136 | himask = 0xffff >> (32 - shift); | |
3137 | lomask = (0xffff << shift) & 0xffffffff; | |
3138 | } | |
3139 | else | |
3140 | { | |
3141 | himask = 0xffff << (shift - 32); | |
3142 | lomask = 0; | |
3143 | } | |
3144 | if ((hi32.X_add_number & ~(offsetT) himask) == 0 | |
3145 | && (lo32.X_add_number & ~(offsetT) lomask) == 0) | |
3146 | { | |
3147 | expressionS tmp; | |
3148 | ||
3149 | tmp.X_op = O_constant; | |
3150 | if (shift < 32) | |
3151 | tmp.X_add_number = ((hi32.X_add_number << (32 - shift)) | |
3152 | | (lo32.X_add_number >> shift)); | |
3153 | else | |
3154 | tmp.X_add_number = hi32.X_add_number >> (shift - 32); | |
3155 | macro_build ((char *) NULL, counter, &tmp, | |
3156 | "ori", "t,r,i", reg, 0, | |
3157 | (int) BFD_RELOC_LO16); | |
3158 | macro_build ((char *) NULL, counter, NULL, | |
3159 | (shift >= 32) ? "dsll32" : "dsll", | |
3160 | "d,w,<", reg, reg, | |
3161 | (shift >= 32) ? shift - 32 : shift); | |
3162 | return; | |
3163 | } | |
3164 | shift++; | |
3165 | } | |
3166 | while (shift <= (64 - 16)); | |
252b5132 RH |
3167 | |
3168 | /* Find the bit number of the lowest one bit, and store the | |
3169 | shifted value in hi/lo. */ | |
3170 | hi = (unsigned long) (hi32.X_add_number & 0xffffffff); | |
3171 | lo = (unsigned long) (lo32.X_add_number & 0xffffffff); | |
3172 | if (lo != 0) | |
3173 | { | |
3174 | bit = 0; | |
3175 | while ((lo & 1) == 0) | |
3176 | { | |
3177 | lo >>= 1; | |
3178 | ++bit; | |
3179 | } | |
3180 | lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit); | |
3181 | hi >>= bit; | |
3182 | } | |
3183 | else | |
3184 | { | |
3185 | bit = 32; | |
3186 | while ((hi & 1) == 0) | |
3187 | { | |
3188 | hi >>= 1; | |
3189 | ++bit; | |
3190 | } | |
3191 | lo = hi; | |
3192 | hi = 0; | |
3193 | } | |
3194 | ||
3195 | /* Optimize if the shifted value is a (power of 2) - 1. */ | |
3196 | if ((hi == 0 && ((lo + 1) & lo) == 0) | |
3197 | || (lo == 0xffffffff && ((hi + 1) & hi) == 0)) | |
beae10d5 KH |
3198 | { |
3199 | shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number); | |
252b5132 | 3200 | if (shift != 0) |
beae10d5 | 3201 | { |
252b5132 RH |
3202 | expressionS tmp; |
3203 | ||
3204 | /* This instruction will set the register to be all | |
3205 | ones. */ | |
beae10d5 KH |
3206 | tmp.X_op = O_constant; |
3207 | tmp.X_add_number = (offsetT) -1; | |
3208 | macro_build ((char *) NULL, counter, &tmp, "addiu", "t,r,j", | |
252b5132 | 3209 | reg, 0, (int) BFD_RELOC_LO16); |
beae10d5 KH |
3210 | if (bit != 0) |
3211 | { | |
3212 | bit += shift; | |
3213 | macro_build ((char *) NULL, counter, NULL, | |
3214 | (bit >= 32) ? "dsll32" : "dsll", | |
3215 | "d,w,<", reg, reg, | |
3216 | (bit >= 32) ? bit - 32 : bit); | |
3217 | } | |
3218 | macro_build ((char *) NULL, counter, NULL, | |
252b5132 | 3219 | (shift >= 32) ? "dsrl32" : "dsrl", |
beae10d5 | 3220 | "d,w,<", reg, reg, |
252b5132 | 3221 | (shift >= 32) ? shift - 32 : shift); |
beae10d5 KH |
3222 | return; |
3223 | } | |
3224 | } | |
252b5132 RH |
3225 | |
3226 | /* Sign extend hi32 before calling load_register, because we can | |
3227 | generally get better code when we load a sign extended value. */ | |
3228 | if ((hi32.X_add_number & 0x80000000) != 0) | |
beae10d5 | 3229 | hi32.X_add_number |= ~(offsetT) 0xffffffff; |
252b5132 RH |
3230 | load_register (counter, reg, &hi32, 0); |
3231 | freg = reg; | |
3232 | } | |
3233 | if ((lo32.X_add_number & 0xffff0000) == 0) | |
3234 | { | |
3235 | if (freg != 0) | |
3236 | { | |
3237 | macro_build ((char *) NULL, counter, NULL, "dsll32", "d,w,<", reg, | |
3238 | freg, 0); | |
3239 | freg = reg; | |
3240 | } | |
3241 | } | |
3242 | else | |
3243 | { | |
3244 | expressionS mid16; | |
3245 | ||
3246 | if ((freg == 0) && (lo32.X_add_number == 0xffffffff)) | |
beae10d5 | 3247 | { |
252b5132 RH |
3248 | macro_build ((char *) NULL, counter, &lo32, "lui", "t,u", reg, |
3249 | (int) BFD_RELOC_HI16); | |
beae10d5 KH |
3250 | macro_build ((char *) NULL, counter, NULL, "dsrl32", "d,w,<", reg, |
3251 | reg, 0); | |
3252 | return; | |
3253 | } | |
252b5132 RH |
3254 | |
3255 | if (freg != 0) | |
3256 | { | |
3257 | macro_build ((char *) NULL, counter, NULL, "dsll", "d,w,<", reg, | |
3258 | freg, 16); | |
3259 | freg = reg; | |
3260 | } | |
3261 | mid16 = lo32; | |
3262 | mid16.X_add_number >>= 16; | |
3263 | macro_build ((char *) NULL, counter, &mid16, "ori", "t,r,i", reg, | |
3264 | freg, (int) BFD_RELOC_LO16); | |
3265 | macro_build ((char *) NULL, counter, NULL, "dsll", "d,w,<", reg, | |
3266 | reg, 16); | |
3267 | freg = reg; | |
3268 | } | |
3269 | if ((lo32.X_add_number & 0xffff) != 0) | |
3270 | macro_build ((char *) NULL, counter, &lo32, "ori", "t,r,i", reg, freg, | |
3271 | (int) BFD_RELOC_LO16); | |
3272 | } | |
3273 | ||
3274 | /* Load an address into a register. */ | |
3275 | ||
3276 | static void | |
3277 | load_address (counter, reg, ep) | |
3278 | int *counter; | |
3279 | int reg; | |
3280 | expressionS *ep; | |
3281 | { | |
3282 | char *p; | |
3283 | ||
3284 | if (ep->X_op != O_constant | |
3285 | && ep->X_op != O_symbol) | |
3286 | { | |
3287 | as_bad (_("expression too complex")); | |
3288 | ep->X_op = O_constant; | |
3289 | } | |
3290 | ||
3291 | if (ep->X_op == O_constant) | |
3292 | { | |
3293 | load_register (counter, reg, ep, 0); | |
3294 | return; | |
3295 | } | |
3296 | ||
3297 | if (mips_pic == NO_PIC) | |
3298 | { | |
3299 | /* If this is a reference to a GP relative symbol, we want | |
3300 | addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL) | |
3301 | Otherwise we want | |
3302 | lui $reg,<sym> (BFD_RELOC_HI16_S) | |
3303 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
3304 | If we have an addend, we always use the latter form. */ | |
3305 | if ((valueT) ep->X_add_number >= MAX_GPREL_OFFSET | |
beae10d5 | 3306 | || nopic_need_relax (ep->X_add_symbol, 1)) |
252b5132 RH |
3307 | p = NULL; |
3308 | else | |
3309 | { | |
3310 | frag_grow (20); | |
3311 | macro_build ((char *) NULL, counter, ep, | |
ca4e0257 | 3312 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
252b5132 RH |
3313 | "t,r,j", reg, GP, (int) BFD_RELOC_MIPS_GPREL); |
3314 | p = frag_var (rs_machine_dependent, 8, 0, | |
3315 | RELAX_ENCODE (4, 8, 0, 4, 0, | |
3316 | mips_opts.warn_about_macros), | |
3317 | ep->X_add_symbol, (offsetT) 0, (char *) NULL); | |
3318 | } | |
3319 | macro_build_lui (p, counter, ep, reg); | |
3320 | if (p != NULL) | |
3321 | p += 4; | |
3322 | macro_build (p, counter, ep, | |
ca4e0257 | 3323 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
252b5132 RH |
3324 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); |
3325 | } | |
3326 | else if (mips_pic == SVR4_PIC && ! mips_big_got) | |
3327 | { | |
3328 | expressionS ex; | |
3329 | ||
3330 | /* If this is a reference to an external symbol, we want | |
3331 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3332 | Otherwise we want | |
3333 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3334 | nop | |
3335 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
3336 | If there is a constant, it must be added in after. */ | |
3337 | ex.X_add_number = ep->X_add_number; | |
3338 | ep->X_add_number = 0; | |
3339 | frag_grow (20); | |
3340 | macro_build ((char *) NULL, counter, ep, | |
ca4e0257 | 3341 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", |
252b5132 RH |
3342 | "t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT16, GP); |
3343 | macro_build ((char *) NULL, counter, (expressionS *) NULL, "nop", ""); | |
3344 | p = frag_var (rs_machine_dependent, 4, 0, | |
3345 | RELAX_ENCODE (0, 4, -8, 0, 0, mips_opts.warn_about_macros), | |
3346 | ep->X_add_symbol, (offsetT) 0, (char *) NULL); | |
3347 | macro_build (p, counter, ep, | |
ca4e0257 | 3348 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
252b5132 RH |
3349 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); |
3350 | if (ex.X_add_number != 0) | |
3351 | { | |
3352 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
3353 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
3354 | ex.X_op = O_constant; | |
3355 | macro_build ((char *) NULL, counter, &ex, | |
ca4e0257 | 3356 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
252b5132 RH |
3357 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); |
3358 | } | |
3359 | } | |
3360 | else if (mips_pic == SVR4_PIC) | |
3361 | { | |
3362 | expressionS ex; | |
3363 | int off; | |
3364 | ||
3365 | /* This is the large GOT case. If this is a reference to an | |
3366 | external symbol, we want | |
3367 | lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
3368 | addu $reg,$reg,$gp | |
3369 | lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16) | |
3370 | Otherwise, for a reference to a local symbol, we want | |
3371 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3372 | nop | |
3373 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
3374 | If there is a constant, it must be added in after. */ | |
3375 | ex.X_add_number = ep->X_add_number; | |
3376 | ep->X_add_number = 0; | |
3377 | if (reg_needs_delay (GP)) | |
3378 | off = 4; | |
3379 | else | |
3380 | off = 0; | |
3381 | frag_grow (32); | |
3382 | macro_build ((char *) NULL, counter, ep, "lui", "t,u", reg, | |
3383 | (int) BFD_RELOC_MIPS_GOT_HI16); | |
3384 | macro_build ((char *) NULL, counter, (expressionS *) NULL, | |
ca4e0257 | 3385 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
3386 | "d,v,t", reg, reg, GP); |
3387 | macro_build ((char *) NULL, counter, ep, | |
ca4e0257 | 3388 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", |
252b5132 RH |
3389 | "t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT_LO16, reg); |
3390 | p = frag_var (rs_machine_dependent, 12 + off, 0, | |
3391 | RELAX_ENCODE (12, 12 + off, off, 8 + off, 0, | |
3392 | mips_opts.warn_about_macros), | |
3393 | ep->X_add_symbol, (offsetT) 0, (char *) NULL); | |
3394 | if (off > 0) | |
3395 | { | |
3396 | /* We need a nop before loading from $gp. This special | |
3397 | check is required because the lui which starts the main | |
3398 | instruction stream does not refer to $gp, and so will not | |
3399 | insert the nop which may be required. */ | |
3400 | macro_build (p, counter, (expressionS *) NULL, "nop", ""); | |
3401 | p += 4; | |
3402 | } | |
9a41af64 | 3403 | macro_build (p, counter, ep, HAVE_32BIT_ADDRESSES ? "lw" : "ld", |
252b5132 RH |
3404 | "t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT16, GP); |
3405 | p += 4; | |
3406 | macro_build (p, counter, (expressionS *) NULL, "nop", ""); | |
3407 | p += 4; | |
9a41af64 | 3408 | macro_build (p, counter, ep, HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
252b5132 RH |
3409 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); |
3410 | if (ex.X_add_number != 0) | |
3411 | { | |
3412 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
3413 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
3414 | ex.X_op = O_constant; | |
3415 | macro_build ((char *) NULL, counter, &ex, | |
ca4e0257 | 3416 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
252b5132 RH |
3417 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); |
3418 | } | |
3419 | } | |
3420 | else if (mips_pic == EMBEDDED_PIC) | |
3421 | { | |
3422 | /* We always do | |
3423 | addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL) | |
3424 | */ | |
3425 | macro_build ((char *) NULL, counter, ep, | |
ca4e0257 | 3426 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
252b5132 RH |
3427 | "t,r,j", reg, GP, (int) BFD_RELOC_MIPS_GPREL); |
3428 | } | |
3429 | else | |
3430 | abort (); | |
3431 | } | |
3432 | ||
ea1fb5dc RS |
3433 | /* Move the contents of register SOURCE into register DEST. */ |
3434 | ||
3435 | static void | |
3436 | move_register (counter, dest, source) | |
3437 | int *counter; | |
3438 | int dest; | |
3439 | int source; | |
3440 | { | |
3441 | macro_build ((char *) NULL, counter, (expressionS *) NULL, | |
3442 | HAVE_32BIT_GPRS ? "addu" : "daddu", | |
3443 | "d,v,t", dest, source, 0); | |
3444 | } | |
3445 | ||
252b5132 RH |
3446 | /* |
3447 | * Build macros | |
3448 | * This routine implements the seemingly endless macro or synthesized | |
3449 | * instructions and addressing modes in the mips assembly language. Many | |
3450 | * of these macros are simple and are similar to each other. These could | |
3451 | * probably be handled by some kind of table or grammer aproach instead of | |
3452 | * this verbose method. Others are not simple macros but are more like | |
3453 | * optimizing code generation. | |
3454 | * One interesting optimization is when several store macros appear | |
3455 | * consecutivly that would load AT with the upper half of the same address. | |
3456 | * The ensuing load upper instructions are ommited. This implies some kind | |
3457 | * of global optimization. We currently only optimize within a single macro. | |
3458 | * For many of the load and store macros if the address is specified as a | |
3459 | * constant expression in the first 64k of memory (ie ld $2,0x4000c) we | |
3460 | * first load register 'at' with zero and use it as the base register. The | |
3461 | * mips assembler simply uses register $zero. Just one tiny optimization | |
3462 | * we're missing. | |
3463 | */ | |
3464 | static void | |
3465 | macro (ip) | |
3466 | struct mips_cl_insn *ip; | |
3467 | { | |
3468 | register int treg, sreg, dreg, breg; | |
3469 | int tempreg; | |
3470 | int mask; | |
3471 | int icnt = 0; | |
43841e91 | 3472 | int used_at = 0; |
252b5132 RH |
3473 | expressionS expr1; |
3474 | const char *s; | |
3475 | const char *s2; | |
3476 | const char *fmt; | |
3477 | int likely = 0; | |
3478 | int dbl = 0; | |
3479 | int coproc = 0; | |
3480 | int lr = 0; | |
3481 | int imm = 0; | |
3482 | offsetT maxnum; | |
3483 | int off; | |
3484 | bfd_reloc_code_real_type r; | |
3485 | char *p; | |
3486 | int hold_mips_optimize; | |
3487 | ||
3488 | assert (! mips_opts.mips16); | |
3489 | ||
3490 | treg = (ip->insn_opcode >> 16) & 0x1f; | |
3491 | dreg = (ip->insn_opcode >> 11) & 0x1f; | |
3492 | sreg = breg = (ip->insn_opcode >> 21) & 0x1f; | |
3493 | mask = ip->insn_mo->mask; | |
3494 | ||
3495 | expr1.X_op = O_constant; | |
3496 | expr1.X_op_symbol = NULL; | |
3497 | expr1.X_add_symbol = NULL; | |
3498 | expr1.X_add_number = 1; | |
3499 | ||
3500 | switch (mask) | |
3501 | { | |
3502 | case M_DABS: | |
3503 | dbl = 1; | |
3504 | case M_ABS: | |
3505 | /* bgez $a0,.+12 | |
3506 | move v0,$a0 | |
3507 | sub v0,$zero,$a0 | |
3508 | */ | |
3509 | ||
3510 | mips_emit_delays (true); | |
3511 | ++mips_opts.noreorder; | |
3512 | mips_any_noreorder = 1; | |
3513 | ||
3514 | expr1.X_add_number = 8; | |
3515 | macro_build ((char *) NULL, &icnt, &expr1, "bgez", "s,p", sreg); | |
3516 | if (dreg == sreg) | |
3517 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); | |
3518 | else | |
ea1fb5dc | 3519 | move_register (&icnt, dreg, sreg); |
252b5132 | 3520 | macro_build ((char *) NULL, &icnt, NULL, |
9a41af64 | 3521 | dbl ? "dsub" : "sub", "d,v,t", dreg, 0, sreg); |
252b5132 RH |
3522 | |
3523 | --mips_opts.noreorder; | |
3524 | return; | |
3525 | ||
3526 | case M_ADD_I: | |
3527 | s = "addi"; | |
3528 | s2 = "add"; | |
3529 | goto do_addi; | |
3530 | case M_ADDU_I: | |
3531 | s = "addiu"; | |
3532 | s2 = "addu"; | |
3533 | goto do_addi; | |
3534 | case M_DADD_I: | |
3535 | dbl = 1; | |
3536 | s = "daddi"; | |
3537 | s2 = "dadd"; | |
3538 | goto do_addi; | |
3539 | case M_DADDU_I: | |
3540 | dbl = 1; | |
3541 | s = "daddiu"; | |
3542 | s2 = "daddu"; | |
3543 | do_addi: | |
3544 | if (imm_expr.X_op == O_constant | |
3545 | && imm_expr.X_add_number >= -0x8000 | |
3546 | && imm_expr.X_add_number < 0x8000) | |
3547 | { | |
3548 | macro_build ((char *) NULL, &icnt, &imm_expr, s, "t,r,j", treg, sreg, | |
3549 | (int) BFD_RELOC_LO16); | |
3550 | return; | |
3551 | } | |
3552 | load_register (&icnt, AT, &imm_expr, dbl); | |
3553 | macro_build ((char *) NULL, &icnt, NULL, s2, "d,v,t", treg, sreg, AT); | |
3554 | break; | |
3555 | ||
3556 | case M_AND_I: | |
3557 | s = "andi"; | |
3558 | s2 = "and"; | |
3559 | goto do_bit; | |
3560 | case M_OR_I: | |
3561 | s = "ori"; | |
3562 | s2 = "or"; | |
3563 | goto do_bit; | |
3564 | case M_NOR_I: | |
3565 | s = ""; | |
3566 | s2 = "nor"; | |
3567 | goto do_bit; | |
3568 | case M_XOR_I: | |
3569 | s = "xori"; | |
3570 | s2 = "xor"; | |
3571 | do_bit: | |
3572 | if (imm_expr.X_op == O_constant | |
3573 | && imm_expr.X_add_number >= 0 | |
3574 | && imm_expr.X_add_number < 0x10000) | |
3575 | { | |
3576 | if (mask != M_NOR_I) | |
3577 | macro_build ((char *) NULL, &icnt, &imm_expr, s, "t,r,i", treg, | |
3578 | sreg, (int) BFD_RELOC_LO16); | |
3579 | else | |
3580 | { | |
3581 | macro_build ((char *) NULL, &icnt, &imm_expr, "ori", "t,r,i", | |
3582 | treg, sreg, (int) BFD_RELOC_LO16); | |
3583 | macro_build ((char *) NULL, &icnt, NULL, "nor", "d,v,t", | |
3584 | treg, treg, 0); | |
3585 | } | |
3586 | return; | |
3587 | } | |
3588 | ||
3589 | load_register (&icnt, AT, &imm_expr, 0); | |
3590 | macro_build ((char *) NULL, &icnt, NULL, s2, "d,v,t", treg, sreg, AT); | |
3591 | break; | |
3592 | ||
3593 | case M_BEQ_I: | |
3594 | s = "beq"; | |
3595 | goto beq_i; | |
3596 | case M_BEQL_I: | |
3597 | s = "beql"; | |
3598 | likely = 1; | |
3599 | goto beq_i; | |
3600 | case M_BNE_I: | |
3601 | s = "bne"; | |
3602 | goto beq_i; | |
3603 | case M_BNEL_I: | |
3604 | s = "bnel"; | |
3605 | likely = 1; | |
3606 | beq_i: | |
3607 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
3608 | { | |
3609 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "s,t,p", sreg, | |
3610 | 0); | |
3611 | return; | |
3612 | } | |
3613 | load_register (&icnt, AT, &imm_expr, 0); | |
3614 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "s,t,p", sreg, AT); | |
3615 | break; | |
3616 | ||
3617 | case M_BGEL: | |
3618 | likely = 1; | |
3619 | case M_BGE: | |
3620 | if (treg == 0) | |
3621 | { | |
3622 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3623 | likely ? "bgezl" : "bgez", | |
3624 | "s,p", sreg); | |
3625 | return; | |
3626 | } | |
3627 | if (sreg == 0) | |
3628 | { | |
3629 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3630 | likely ? "blezl" : "blez", | |
3631 | "s,p", treg); | |
3632 | return; | |
3633 | } | |
3634 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", AT, sreg, treg); | |
3635 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 3636 | likely ? "beql" : "beq", "s,t,p", AT, 0); |
252b5132 RH |
3637 | break; |
3638 | ||
3639 | case M_BGTL_I: | |
3640 | likely = 1; | |
3641 | case M_BGT_I: | |
3642 | /* check for > max integer */ | |
3643 | maxnum = 0x7fffffff; | |
ca4e0257 | 3644 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
3645 | { |
3646 | maxnum <<= 16; | |
3647 | maxnum |= 0xffff; | |
3648 | maxnum <<= 16; | |
3649 | maxnum |= 0xffff; | |
3650 | } | |
3651 | if (imm_expr.X_op == O_constant | |
3652 | && imm_expr.X_add_number >= maxnum | |
ca4e0257 | 3653 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
3654 | { |
3655 | do_false: | |
3656 | /* result is always false */ | |
3657 | if (! likely) | |
3658 | { | |
39c0a331 L |
3659 | if (warn_nops) |
3660 | as_warn (_("Branch %s is always false (nop)"), | |
3661 | ip->insn_mo->name); | |
252b5132 RH |
3662 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); |
3663 | } | |
3664 | else | |
3665 | { | |
39c0a331 L |
3666 | if (warn_nops) |
3667 | as_warn (_("Branch likely %s is always false"), | |
3668 | ip->insn_mo->name); | |
252b5132 RH |
3669 | macro_build ((char *) NULL, &icnt, &offset_expr, "bnel", |
3670 | "s,t,p", 0, 0); | |
3671 | } | |
3672 | return; | |
3673 | } | |
3674 | if (imm_expr.X_op != O_constant) | |
3675 | as_bad (_("Unsupported large constant")); | |
3676 | imm_expr.X_add_number++; | |
3677 | /* FALLTHROUGH */ | |
3678 | case M_BGE_I: | |
3679 | case M_BGEL_I: | |
3680 | if (mask == M_BGEL_I) | |
3681 | likely = 1; | |
3682 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
3683 | { | |
3684 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 3685 | likely ? "bgezl" : "bgez", "s,p", sreg); |
252b5132 RH |
3686 | return; |
3687 | } | |
3688 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
3689 | { | |
3690 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 3691 | likely ? "bgtzl" : "bgtz", "s,p", sreg); |
252b5132 RH |
3692 | return; |
3693 | } | |
3694 | maxnum = 0x7fffffff; | |
ca4e0257 | 3695 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
3696 | { |
3697 | maxnum <<= 16; | |
3698 | maxnum |= 0xffff; | |
3699 | maxnum <<= 16; | |
3700 | maxnum |= 0xffff; | |
3701 | } | |
3702 | maxnum = - maxnum - 1; | |
3703 | if (imm_expr.X_op == O_constant | |
3704 | && imm_expr.X_add_number <= maxnum | |
ca4e0257 | 3705 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
3706 | { |
3707 | do_true: | |
3708 | /* result is always true */ | |
3709 | as_warn (_("Branch %s is always true"), ip->insn_mo->name); | |
3710 | macro_build ((char *) NULL, &icnt, &offset_expr, "b", "p"); | |
3711 | return; | |
3712 | } | |
3713 | set_at (&icnt, sreg, 0); | |
3714 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 3715 | likely ? "beql" : "beq", "s,t,p", AT, 0); |
252b5132 RH |
3716 | break; |
3717 | ||
3718 | case M_BGEUL: | |
3719 | likely = 1; | |
3720 | case M_BGEU: | |
3721 | if (treg == 0) | |
3722 | goto do_true; | |
3723 | if (sreg == 0) | |
3724 | { | |
3725 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 3726 | likely ? "beql" : "beq", "s,t,p", 0, treg); |
252b5132 RH |
3727 | return; |
3728 | } | |
3729 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", AT, sreg, | |
3730 | treg); | |
3731 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 3732 | likely ? "beql" : "beq", "s,t,p", AT, 0); |
252b5132 RH |
3733 | break; |
3734 | ||
3735 | case M_BGTUL_I: | |
3736 | likely = 1; | |
3737 | case M_BGTU_I: | |
3738 | if (sreg == 0 | |
ca4e0257 | 3739 | || (HAVE_32BIT_GPRS |
252b5132 RH |
3740 | && imm_expr.X_op == O_constant |
3741 | && imm_expr.X_add_number == 0xffffffff)) | |
3742 | goto do_false; | |
3743 | if (imm_expr.X_op != O_constant) | |
3744 | as_bad (_("Unsupported large constant")); | |
3745 | imm_expr.X_add_number++; | |
3746 | /* FALLTHROUGH */ | |
3747 | case M_BGEU_I: | |
3748 | case M_BGEUL_I: | |
3749 | if (mask == M_BGEUL_I) | |
3750 | likely = 1; | |
3751 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
3752 | goto do_true; | |
3753 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
3754 | { | |
3755 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 3756 | likely ? "bnel" : "bne", "s,t,p", sreg, 0); |
252b5132 RH |
3757 | return; |
3758 | } | |
3759 | set_at (&icnt, sreg, 1); | |
3760 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 3761 | likely ? "beql" : "beq", "s,t,p", AT, 0); |
252b5132 RH |
3762 | break; |
3763 | ||
3764 | case M_BGTL: | |
3765 | likely = 1; | |
3766 | case M_BGT: | |
3767 | if (treg == 0) | |
3768 | { | |
3769 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 3770 | likely ? "bgtzl" : "bgtz", "s,p", sreg); |
252b5132 RH |
3771 | return; |
3772 | } | |
3773 | if (sreg == 0) | |
3774 | { | |
3775 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 3776 | likely ? "bltzl" : "bltz", "s,p", treg); |
252b5132 RH |
3777 | return; |
3778 | } | |
3779 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", AT, treg, sreg); | |
3780 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 3781 | likely ? "bnel" : "bne", "s,t,p", AT, 0); |
252b5132 RH |
3782 | break; |
3783 | ||
3784 | case M_BGTUL: | |
3785 | likely = 1; | |
3786 | case M_BGTU: | |
3787 | if (treg == 0) | |
3788 | { | |
3789 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 3790 | likely ? "bnel" : "bne", "s,t,p", sreg, 0); |
252b5132 RH |
3791 | return; |
3792 | } | |
3793 | if (sreg == 0) | |
3794 | goto do_false; | |
3795 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", AT, treg, | |
3796 | sreg); | |
3797 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 3798 | likely ? "bnel" : "bne", "s,t,p", AT, 0); |
252b5132 RH |
3799 | break; |
3800 | ||
3801 | case M_BLEL: | |
3802 | likely = 1; | |
3803 | case M_BLE: | |
3804 | if (treg == 0) | |
3805 | { | |
3806 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 3807 | likely ? "blezl" : "blez", "s,p", sreg); |
252b5132 RH |
3808 | return; |
3809 | } | |
3810 | if (sreg == 0) | |
3811 | { | |
3812 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 3813 | likely ? "bgezl" : "bgez", "s,p", treg); |
252b5132 RH |
3814 | return; |
3815 | } | |
3816 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", AT, treg, sreg); | |
3817 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 3818 | likely ? "beql" : "beq", "s,t,p", AT, 0); |
252b5132 RH |
3819 | break; |
3820 | ||
3821 | case M_BLEL_I: | |
3822 | likely = 1; | |
3823 | case M_BLE_I: | |
3824 | maxnum = 0x7fffffff; | |
ca4e0257 | 3825 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
3826 | { |
3827 | maxnum <<= 16; | |
3828 | maxnum |= 0xffff; | |
3829 | maxnum <<= 16; | |
3830 | maxnum |= 0xffff; | |
3831 | } | |
3832 | if (imm_expr.X_op == O_constant | |
3833 | && imm_expr.X_add_number >= maxnum | |
ca4e0257 | 3834 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
3835 | goto do_true; |
3836 | if (imm_expr.X_op != O_constant) | |
3837 | as_bad (_("Unsupported large constant")); | |
3838 | imm_expr.X_add_number++; | |
3839 | /* FALLTHROUGH */ | |
3840 | case M_BLT_I: | |
3841 | case M_BLTL_I: | |
3842 | if (mask == M_BLTL_I) | |
3843 | likely = 1; | |
3844 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
3845 | { | |
3846 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 3847 | likely ? "bltzl" : "bltz", "s,p", sreg); |
252b5132 RH |
3848 | return; |
3849 | } | |
3850 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
3851 | { | |
3852 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 3853 | likely ? "blezl" : "blez", "s,p", sreg); |
252b5132 RH |
3854 | return; |
3855 | } | |
3856 | set_at (&icnt, sreg, 0); | |
3857 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 3858 | likely ? "bnel" : "bne", "s,t,p", AT, 0); |
252b5132 RH |
3859 | break; |
3860 | ||
3861 | case M_BLEUL: | |
3862 | likely = 1; | |
3863 | case M_BLEU: | |
3864 | if (treg == 0) | |
3865 | { | |
3866 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 3867 | likely ? "beql" : "beq", "s,t,p", sreg, 0); |
252b5132 RH |
3868 | return; |
3869 | } | |
3870 | if (sreg == 0) | |
3871 | goto do_true; | |
3872 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", AT, treg, | |
3873 | sreg); | |
3874 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 3875 | likely ? "beql" : "beq", "s,t,p", AT, 0); |
252b5132 RH |
3876 | break; |
3877 | ||
3878 | case M_BLEUL_I: | |
3879 | likely = 1; | |
3880 | case M_BLEU_I: | |
3881 | if (sreg == 0 | |
ca4e0257 | 3882 | || (HAVE_32BIT_GPRS |
252b5132 RH |
3883 | && imm_expr.X_op == O_constant |
3884 | && imm_expr.X_add_number == 0xffffffff)) | |
3885 | goto do_true; | |
3886 | if (imm_expr.X_op != O_constant) | |
3887 | as_bad (_("Unsupported large constant")); | |
3888 | imm_expr.X_add_number++; | |
3889 | /* FALLTHROUGH */ | |
3890 | case M_BLTU_I: | |
3891 | case M_BLTUL_I: | |
3892 | if (mask == M_BLTUL_I) | |
3893 | likely = 1; | |
3894 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
3895 | goto do_false; | |
3896 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
3897 | { | |
3898 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3899 | likely ? "beql" : "beq", | |
3900 | "s,t,p", sreg, 0); | |
3901 | return; | |
3902 | } | |
3903 | set_at (&icnt, sreg, 1); | |
3904 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 3905 | likely ? "bnel" : "bne", "s,t,p", AT, 0); |
252b5132 RH |
3906 | break; |
3907 | ||
3908 | case M_BLTL: | |
3909 | likely = 1; | |
3910 | case M_BLT: | |
3911 | if (treg == 0) | |
3912 | { | |
3913 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 3914 | likely ? "bltzl" : "bltz", "s,p", sreg); |
252b5132 RH |
3915 | return; |
3916 | } | |
3917 | if (sreg == 0) | |
3918 | { | |
3919 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 3920 | likely ? "bgtzl" : "bgtz", "s,p", treg); |
252b5132 RH |
3921 | return; |
3922 | } | |
3923 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", AT, sreg, treg); | |
3924 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 3925 | likely ? "bnel" : "bne", "s,t,p", AT, 0); |
252b5132 RH |
3926 | break; |
3927 | ||
3928 | case M_BLTUL: | |
3929 | likely = 1; | |
3930 | case M_BLTU: | |
3931 | if (treg == 0) | |
3932 | goto do_false; | |
3933 | if (sreg == 0) | |
3934 | { | |
3935 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 3936 | likely ? "bnel" : "bne", "s,t,p", 0, treg); |
252b5132 RH |
3937 | return; |
3938 | } | |
3939 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", AT, sreg, | |
3940 | treg); | |
3941 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 3942 | likely ? "bnel" : "bne", "s,t,p", AT, 0); |
252b5132 RH |
3943 | break; |
3944 | ||
3945 | case M_DDIV_3: | |
3946 | dbl = 1; | |
3947 | case M_DIV_3: | |
3948 | s = "mflo"; | |
3949 | goto do_div3; | |
3950 | case M_DREM_3: | |
3951 | dbl = 1; | |
3952 | case M_REM_3: | |
3953 | s = "mfhi"; | |
3954 | do_div3: | |
3955 | if (treg == 0) | |
3956 | { | |
3957 | as_warn (_("Divide by zero.")); | |
3958 | if (mips_trap) | |
3959 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", 0, 0); | |
3960 | else | |
9117d219 | 3961 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 7); |
252b5132 RH |
3962 | return; |
3963 | } | |
3964 | ||
3965 | mips_emit_delays (true); | |
3966 | ++mips_opts.noreorder; | |
3967 | mips_any_noreorder = 1; | |
3968 | if (mips_trap) | |
3969 | { | |
3970 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", treg, 0); | |
3971 | macro_build ((char *) NULL, &icnt, NULL, | |
9a41af64 | 3972 | dbl ? "ddiv" : "div", "z,s,t", sreg, treg); |
252b5132 RH |
3973 | } |
3974 | else | |
3975 | { | |
3976 | expr1.X_add_number = 8; | |
3977 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, 0); | |
3978 | macro_build ((char *) NULL, &icnt, NULL, | |
9a41af64 | 3979 | dbl ? "ddiv" : "div", "z,s,t", sreg, treg); |
9117d219 | 3980 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 7); |
252b5132 RH |
3981 | } |
3982 | expr1.X_add_number = -1; | |
3983 | macro_build ((char *) NULL, &icnt, &expr1, | |
3984 | dbl ? "daddiu" : "addiu", | |
3985 | "t,r,j", AT, 0, (int) BFD_RELOC_LO16); | |
3986 | expr1.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16); | |
3987 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, AT); | |
3988 | if (dbl) | |
3989 | { | |
3990 | expr1.X_add_number = 1; | |
3991 | macro_build ((char *) NULL, &icnt, &expr1, "daddiu", "t,r,j", AT, 0, | |
3992 | (int) BFD_RELOC_LO16); | |
3993 | macro_build ((char *) NULL, &icnt, NULL, "dsll32", "d,w,<", AT, AT, | |
3994 | 31); | |
3995 | } | |
3996 | else | |
3997 | { | |
3998 | expr1.X_add_number = 0x80000000; | |
3999 | macro_build ((char *) NULL, &icnt, &expr1, "lui", "t,u", AT, | |
4000 | (int) BFD_RELOC_HI16); | |
4001 | } | |
4002 | if (mips_trap) | |
4003 | { | |
4004 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", sreg, AT); | |
4005 | /* We want to close the noreorder block as soon as possible, so | |
4006 | that later insns are available for delay slot filling. */ | |
4007 | --mips_opts.noreorder; | |
4008 | } | |
4009 | else | |
4010 | { | |
4011 | expr1.X_add_number = 8; | |
4012 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", sreg, AT); | |
4013 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); | |
4014 | ||
4015 | /* We want to close the noreorder block as soon as possible, so | |
4016 | that later insns are available for delay slot filling. */ | |
4017 | --mips_opts.noreorder; | |
4018 | ||
9117d219 | 4019 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 6); |
252b5132 RH |
4020 | } |
4021 | macro_build ((char *) NULL, &icnt, NULL, s, "d", dreg); | |
4022 | break; | |
4023 | ||
4024 | case M_DIV_3I: | |
4025 | s = "div"; | |
4026 | s2 = "mflo"; | |
4027 | goto do_divi; | |
4028 | case M_DIVU_3I: | |
4029 | s = "divu"; | |
4030 | s2 = "mflo"; | |
4031 | goto do_divi; | |
4032 | case M_REM_3I: | |
4033 | s = "div"; | |
4034 | s2 = "mfhi"; | |
4035 | goto do_divi; | |
4036 | case M_REMU_3I: | |
4037 | s = "divu"; | |
4038 | s2 = "mfhi"; | |
4039 | goto do_divi; | |
4040 | case M_DDIV_3I: | |
4041 | dbl = 1; | |
4042 | s = "ddiv"; | |
4043 | s2 = "mflo"; | |
4044 | goto do_divi; | |
4045 | case M_DDIVU_3I: | |
4046 | dbl = 1; | |
4047 | s = "ddivu"; | |
4048 | s2 = "mflo"; | |
4049 | goto do_divi; | |
4050 | case M_DREM_3I: | |
4051 | dbl = 1; | |
4052 | s = "ddiv"; | |
4053 | s2 = "mfhi"; | |
4054 | goto do_divi; | |
4055 | case M_DREMU_3I: | |
4056 | dbl = 1; | |
4057 | s = "ddivu"; | |
4058 | s2 = "mfhi"; | |
4059 | do_divi: | |
4060 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4061 | { | |
4062 | as_warn (_("Divide by zero.")); | |
4063 | if (mips_trap) | |
4064 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", 0, 0); | |
4065 | else | |
beae10d5 | 4066 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 7); |
252b5132 RH |
4067 | return; |
4068 | } | |
4069 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4070 | { | |
4071 | if (strcmp (s2, "mflo") == 0) | |
ea1fb5dc | 4072 | move_register (&icnt, dreg, sreg); |
252b5132 | 4073 | else |
ea1fb5dc | 4074 | move_register (&icnt, dreg, 0); |
252b5132 RH |
4075 | return; |
4076 | } | |
4077 | if (imm_expr.X_op == O_constant | |
4078 | && imm_expr.X_add_number == -1 | |
4079 | && s[strlen (s) - 1] != 'u') | |
4080 | { | |
4081 | if (strcmp (s2, "mflo") == 0) | |
4082 | { | |
9a41af64 TS |
4083 | macro_build ((char *) NULL, &icnt, NULL, dbl ? "dneg" : "neg", |
4084 | "d,w", dreg, sreg); | |
252b5132 RH |
4085 | } |
4086 | else | |
ea1fb5dc | 4087 | move_register (&icnt, dreg, 0); |
252b5132 RH |
4088 | return; |
4089 | } | |
4090 | ||
4091 | load_register (&icnt, AT, &imm_expr, dbl); | |
4092 | macro_build ((char *) NULL, &icnt, NULL, s, "z,s,t", sreg, AT); | |
4093 | macro_build ((char *) NULL, &icnt, NULL, s2, "d", dreg); | |
4094 | break; | |
4095 | ||
4096 | case M_DIVU_3: | |
4097 | s = "divu"; | |
4098 | s2 = "mflo"; | |
4099 | goto do_divu3; | |
4100 | case M_REMU_3: | |
4101 | s = "divu"; | |
4102 | s2 = "mfhi"; | |
4103 | goto do_divu3; | |
4104 | case M_DDIVU_3: | |
4105 | s = "ddivu"; | |
4106 | s2 = "mflo"; | |
4107 | goto do_divu3; | |
4108 | case M_DREMU_3: | |
4109 | s = "ddivu"; | |
4110 | s2 = "mfhi"; | |
4111 | do_divu3: | |
4112 | mips_emit_delays (true); | |
4113 | ++mips_opts.noreorder; | |
4114 | mips_any_noreorder = 1; | |
4115 | if (mips_trap) | |
4116 | { | |
4117 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", treg, 0); | |
4118 | macro_build ((char *) NULL, &icnt, NULL, s, "z,s,t", sreg, treg); | |
4119 | /* We want to close the noreorder block as soon as possible, so | |
4120 | that later insns are available for delay slot filling. */ | |
4121 | --mips_opts.noreorder; | |
4122 | } | |
4123 | else | |
4124 | { | |
4125 | expr1.X_add_number = 8; | |
4126 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, 0); | |
4127 | macro_build ((char *) NULL, &icnt, NULL, s, "z,s,t", sreg, treg); | |
4128 | ||
4129 | /* We want to close the noreorder block as soon as possible, so | |
4130 | that later insns are available for delay slot filling. */ | |
4131 | --mips_opts.noreorder; | |
beae10d5 | 4132 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 7); |
252b5132 RH |
4133 | } |
4134 | macro_build ((char *) NULL, &icnt, NULL, s2, "d", dreg); | |
4135 | return; | |
4136 | ||
4137 | case M_DLA_AB: | |
4138 | dbl = 1; | |
4139 | case M_LA_AB: | |
4140 | /* Load the address of a symbol into a register. If breg is not | |
4141 | zero, we then add a base register to it. */ | |
4142 | ||
4143 | /* When generating embedded PIC code, we permit expressions of | |
4144 | the form | |
4145 | la $4,foo-bar | |
bb2d6cd7 | 4146 | where bar is an address in the current section. These are used |
252b5132 RH |
4147 | when getting the addresses of functions. We don't permit |
4148 | X_add_number to be non-zero, because if the symbol is | |
4149 | external the relaxing code needs to know that any addend is | |
4150 | purely the offset to X_op_symbol. */ | |
4151 | if (mips_pic == EMBEDDED_PIC | |
4152 | && offset_expr.X_op == O_subtract | |
49309057 | 4153 | && (symbol_constant_p (offset_expr.X_op_symbol) |
bb2d6cd7 | 4154 | ? S_GET_SEGMENT (offset_expr.X_op_symbol) == now_seg |
49309057 ILT |
4155 | : (symbol_equated_p (offset_expr.X_op_symbol) |
4156 | && (S_GET_SEGMENT | |
4157 | (symbol_get_value_expression (offset_expr.X_op_symbol) | |
4158 | ->X_add_symbol) | |
bb2d6cd7 | 4159 | == now_seg))) |
252b5132 | 4160 | && breg == 0 |
bb2d6cd7 GK |
4161 | && (offset_expr.X_add_number == 0 |
4162 | || OUTPUT_FLAVOR == bfd_target_elf_flavour)) | |
252b5132 RH |
4163 | { |
4164 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
4165 | treg, (int) BFD_RELOC_PCREL_HI16_S); | |
4166 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
ca4e0257 | 4167 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
252b5132 RH |
4168 | "t,r,j", treg, treg, (int) BFD_RELOC_PCREL_LO16); |
4169 | return; | |
4170 | } | |
4171 | ||
4172 | if (offset_expr.X_op != O_symbol | |
4173 | && offset_expr.X_op != O_constant) | |
4174 | { | |
4175 | as_bad (_("expression too complex")); | |
4176 | offset_expr.X_op = O_constant; | |
4177 | } | |
4178 | ||
4179 | if (treg == breg) | |
4180 | { | |
4181 | tempreg = AT; | |
4182 | used_at = 1; | |
4183 | } | |
4184 | else | |
4185 | { | |
4186 | tempreg = treg; | |
4187 | used_at = 0; | |
4188 | } | |
4189 | ||
4190 | if (offset_expr.X_op == O_constant) | |
4191 | load_register (&icnt, tempreg, &offset_expr, dbl); | |
4192 | else if (mips_pic == NO_PIC) | |
4193 | { | |
4194 | /* If this is a reference to an GP relative symbol, we want | |
4195 | addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL) | |
4196 | Otherwise we want | |
4197 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
4198 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
4199 | If we have a constant, we need two instructions anyhow, | |
4200 | so we may as well always use the latter form. */ | |
4201 | if ((valueT) offset_expr.X_add_number >= MAX_GPREL_OFFSET | |
4202 | || nopic_need_relax (offset_expr.X_add_symbol, 1)) | |
4203 | p = NULL; | |
4204 | else | |
4205 | { | |
4206 | frag_grow (20); | |
4207 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
ca4e0257 | 4208 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
252b5132 RH |
4209 | "t,r,j", tempreg, GP, (int) BFD_RELOC_MIPS_GPREL); |
4210 | p = frag_var (rs_machine_dependent, 8, 0, | |
4211 | RELAX_ENCODE (4, 8, 0, 4, 0, | |
4212 | mips_opts.warn_about_macros), | |
4213 | offset_expr.X_add_symbol, (offsetT) 0, | |
4214 | (char *) NULL); | |
4215 | } | |
4216 | macro_build_lui (p, &icnt, &offset_expr, tempreg); | |
4217 | if (p != NULL) | |
4218 | p += 4; | |
4219 | macro_build (p, &icnt, &offset_expr, | |
ca4e0257 | 4220 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
252b5132 RH |
4221 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
4222 | } | |
4223 | else if (mips_pic == SVR4_PIC && ! mips_big_got) | |
4224 | { | |
9117d219 NC |
4225 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
4226 | ||
252b5132 RH |
4227 | /* If this is a reference to an external symbol, and there |
4228 | is no constant, we want | |
4229 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
9117d219 NC |
4230 | or if tempreg is PIC_CALL_REG |
4231 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) | |
252b5132 RH |
4232 | For a local symbol, we want |
4233 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4234 | nop | |
4235 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
4236 | ||
4237 | If we have a small constant, and this is a reference to | |
4238 | an external symbol, we want | |
4239 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4240 | nop | |
4241 | addiu $tempreg,$tempreg,<constant> | |
4242 | For a local symbol, we want the same instruction | |
4243 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
4244 | addiu instruction. | |
4245 | ||
4246 | If we have a large constant, and this is a reference to | |
4247 | an external symbol, we want | |
4248 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4249 | lui $at,<hiconstant> | |
4250 | addiu $at,$at,<loconstant> | |
4251 | addu $tempreg,$tempreg,$at | |
4252 | For a local symbol, we want the same instruction | |
4253 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
4254 | addiu instruction. */ | |
4255 | expr1.X_add_number = offset_expr.X_add_number; | |
4256 | offset_expr.X_add_number = 0; | |
4257 | frag_grow (32); | |
9117d219 NC |
4258 | if (expr1.X_add_number == 0 && tempreg == PIC_CALL_REG) |
4259 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16; | |
252b5132 RH |
4260 | macro_build ((char *) NULL, &icnt, &offset_expr, |
4261 | dbl ? "ld" : "lw", | |
9117d219 | 4262 | "t,o(b)", tempreg, lw_reloc_type, GP); |
252b5132 RH |
4263 | if (expr1.X_add_number == 0) |
4264 | { | |
4265 | int off; | |
4266 | ||
4267 | if (breg == 0) | |
4268 | off = 0; | |
4269 | else | |
4270 | { | |
4271 | /* We're going to put in an addu instruction using | |
4272 | tempreg, so we may as well insert the nop right | |
4273 | now. */ | |
4274 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4275 | "nop", ""); | |
4276 | off = 4; | |
4277 | } | |
4278 | p = frag_var (rs_machine_dependent, 8 - off, 0, | |
4279 | RELAX_ENCODE (0, 8 - off, -4 - off, 4 - off, 0, | |
4280 | (breg == 0 | |
4281 | ? mips_opts.warn_about_macros | |
4282 | : 0)), | |
4283 | offset_expr.X_add_symbol, (offsetT) 0, | |
4284 | (char *) NULL); | |
4285 | if (breg == 0) | |
4286 | { | |
4287 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4288 | p += 4; | |
4289 | } | |
4290 | macro_build (p, &icnt, &expr1, | |
ca4e0257 | 4291 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
252b5132 RH |
4292 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
4293 | /* FIXME: If breg == 0, and the next instruction uses | |
4294 | $tempreg, then if this variant case is used an extra | |
4295 | nop will be generated. */ | |
4296 | } | |
4297 | else if (expr1.X_add_number >= -0x8000 | |
4298 | && expr1.X_add_number < 0x8000) | |
4299 | { | |
4300 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4301 | "nop", ""); | |
4302 | macro_build ((char *) NULL, &icnt, &expr1, | |
ca4e0257 | 4303 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
252b5132 RH |
4304 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
4305 | (void) frag_var (rs_machine_dependent, 0, 0, | |
4306 | RELAX_ENCODE (0, 0, -12, -4, 0, 0), | |
4307 | offset_expr.X_add_symbol, (offsetT) 0, | |
4308 | (char *) NULL); | |
4309 | } | |
4310 | else | |
4311 | { | |
4312 | int off1; | |
4313 | ||
4314 | /* If we are going to add in a base register, and the | |
4315 | target register and the base register are the same, | |
4316 | then we are using AT as a temporary register. Since | |
4317 | we want to load the constant into AT, we add our | |
4318 | current AT (from the global offset table) and the | |
4319 | register into the register now, and pretend we were | |
4320 | not using a base register. */ | |
4321 | if (breg != treg) | |
4322 | off1 = 0; | |
4323 | else | |
4324 | { | |
4325 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4326 | "nop", ""); | |
4327 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 4328 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
4329 | "d,v,t", treg, AT, breg); |
4330 | breg = 0; | |
4331 | tempreg = treg; | |
4332 | off1 = -8; | |
4333 | } | |
4334 | ||
4335 | /* Set mips_optimize around the lui instruction to avoid | |
4336 | inserting an unnecessary nop after the lw. */ | |
4337 | hold_mips_optimize = mips_optimize; | |
4338 | mips_optimize = 2; | |
4339 | macro_build_lui ((char *) NULL, &icnt, &expr1, AT); | |
4340 | mips_optimize = hold_mips_optimize; | |
4341 | ||
4342 | macro_build ((char *) NULL, &icnt, &expr1, | |
ca4e0257 | 4343 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
252b5132 RH |
4344 | "t,r,j", AT, AT, (int) BFD_RELOC_LO16); |
4345 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 4346 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
4347 | "d,v,t", tempreg, tempreg, AT); |
4348 | (void) frag_var (rs_machine_dependent, 0, 0, | |
4349 | RELAX_ENCODE (0, 0, -16 + off1, -8, 0, 0), | |
4350 | offset_expr.X_add_symbol, (offsetT) 0, | |
4351 | (char *) NULL); | |
4352 | used_at = 1; | |
4353 | } | |
4354 | } | |
4355 | else if (mips_pic == SVR4_PIC) | |
4356 | { | |
4357 | int gpdel; | |
9117d219 NC |
4358 | int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; |
4359 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; | |
252b5132 RH |
4360 | |
4361 | /* This is the large GOT case. If this is a reference to an | |
4362 | external symbol, and there is no constant, we want | |
4363 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
4364 | addu $tempreg,$tempreg,$gp | |
4365 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
9117d219 NC |
4366 | or if tempreg is PIC_CALL_REG |
4367 | lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) | |
4368 | addu $tempreg,$tempreg,$gp | |
4369 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) | |
252b5132 RH |
4370 | For a local symbol, we want |
4371 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4372 | nop | |
4373 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
4374 | ||
4375 | If we have a small constant, and this is a reference to | |
4376 | an external symbol, we want | |
4377 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
4378 | addu $tempreg,$tempreg,$gp | |
4379 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
4380 | nop | |
4381 | addiu $tempreg,$tempreg,<constant> | |
4382 | For a local symbol, we want | |
4383 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4384 | nop | |
4385 | addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16) | |
4386 | ||
4387 | If we have a large constant, and this is a reference to | |
4388 | an external symbol, we want | |
4389 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
4390 | addu $tempreg,$tempreg,$gp | |
4391 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
4392 | lui $at,<hiconstant> | |
4393 | addiu $at,$at,<loconstant> | |
4394 | addu $tempreg,$tempreg,$at | |
4395 | For a local symbol, we want | |
4396 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4397 | lui $at,<hiconstant> | |
4398 | addiu $at,$at,<loconstant> (BFD_RELOC_LO16) | |
4399 | addu $tempreg,$tempreg,$at | |
4400 | */ | |
4401 | expr1.X_add_number = offset_expr.X_add_number; | |
4402 | offset_expr.X_add_number = 0; | |
4403 | frag_grow (52); | |
4404 | if (reg_needs_delay (GP)) | |
4405 | gpdel = 4; | |
4406 | else | |
4407 | gpdel = 0; | |
9117d219 NC |
4408 | if (expr1.X_add_number == 0 && tempreg == PIC_CALL_REG) |
4409 | { | |
4410 | lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; | |
4411 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; | |
4412 | } | |
252b5132 | 4413 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", |
9117d219 | 4414 | tempreg, lui_reloc_type); |
252b5132 | 4415 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
ca4e0257 | 4416 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
4417 | "d,v,t", tempreg, tempreg, GP); |
4418 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
4419 | dbl ? "ld" : "lw", | |
9117d219 | 4420 | "t,o(b)", tempreg, lw_reloc_type, tempreg); |
252b5132 RH |
4421 | if (expr1.X_add_number == 0) |
4422 | { | |
4423 | int off; | |
4424 | ||
4425 | if (breg == 0) | |
4426 | off = 0; | |
4427 | else | |
4428 | { | |
4429 | /* We're going to put in an addu instruction using | |
4430 | tempreg, so we may as well insert the nop right | |
4431 | now. */ | |
4432 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4433 | "nop", ""); | |
4434 | off = 4; | |
4435 | } | |
4436 | ||
4437 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, | |
4438 | RELAX_ENCODE (12 + off, 12 + gpdel, gpdel, | |
4439 | 8 + gpdel, 0, | |
4440 | (breg == 0 | |
4441 | ? mips_opts.warn_about_macros | |
4442 | : 0)), | |
4443 | offset_expr.X_add_symbol, (offsetT) 0, | |
4444 | (char *) NULL); | |
4445 | } | |
4446 | else if (expr1.X_add_number >= -0x8000 | |
4447 | && expr1.X_add_number < 0x8000) | |
4448 | { | |
4449 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4450 | "nop", ""); | |
4451 | macro_build ((char *) NULL, &icnt, &expr1, | |
ca4e0257 | 4452 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
252b5132 RH |
4453 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
4454 | ||
4455 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, | |
4456 | RELAX_ENCODE (20, 12 + gpdel, gpdel, 8 + gpdel, 0, | |
4457 | (breg == 0 | |
4458 | ? mips_opts.warn_about_macros | |
4459 | : 0)), | |
4460 | offset_expr.X_add_symbol, (offsetT) 0, | |
4461 | (char *) NULL); | |
4462 | } | |
4463 | else | |
4464 | { | |
4465 | int adj, dreg; | |
4466 | ||
4467 | /* If we are going to add in a base register, and the | |
4468 | target register and the base register are the same, | |
4469 | then we are using AT as a temporary register. Since | |
4470 | we want to load the constant into AT, we add our | |
4471 | current AT (from the global offset table) and the | |
4472 | register into the register now, and pretend we were | |
4473 | not using a base register. */ | |
4474 | if (breg != treg) | |
4475 | { | |
4476 | adj = 0; | |
4477 | dreg = tempreg; | |
4478 | } | |
4479 | else | |
4480 | { | |
4481 | assert (tempreg == AT); | |
4482 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4483 | "nop", ""); | |
4484 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 4485 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
4486 | "d,v,t", treg, AT, breg); |
4487 | dreg = treg; | |
4488 | adj = 8; | |
4489 | } | |
4490 | ||
4491 | /* Set mips_optimize around the lui instruction to avoid | |
4492 | inserting an unnecessary nop after the lw. */ | |
4493 | hold_mips_optimize = mips_optimize; | |
4494 | mips_optimize = 2; | |
4495 | macro_build_lui ((char *) NULL, &icnt, &expr1, AT); | |
4496 | mips_optimize = hold_mips_optimize; | |
4497 | ||
4498 | macro_build ((char *) NULL, &icnt, &expr1, | |
ca4e0257 | 4499 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
252b5132 RH |
4500 | "t,r,j", AT, AT, (int) BFD_RELOC_LO16); |
4501 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 4502 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
4503 | "d,v,t", dreg, dreg, AT); |
4504 | ||
4505 | p = frag_var (rs_machine_dependent, 16 + gpdel + adj, 0, | |
4506 | RELAX_ENCODE (24 + adj, 16 + gpdel + adj, gpdel, | |
4507 | 8 + gpdel, 0, | |
4508 | (breg == 0 | |
4509 | ? mips_opts.warn_about_macros | |
4510 | : 0)), | |
4511 | offset_expr.X_add_symbol, (offsetT) 0, | |
4512 | (char *) NULL); | |
4513 | ||
4514 | used_at = 1; | |
4515 | } | |
4516 | ||
4517 | if (gpdel > 0) | |
4518 | { | |
4519 | /* This is needed because this instruction uses $gp, but | |
4520 | the first instruction on the main stream does not. */ | |
4521 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4522 | p += 4; | |
4523 | } | |
4524 | macro_build (p, &icnt, &offset_expr, | |
4525 | dbl ? "ld" : "lw", | |
4526 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, GP); | |
4527 | p += 4; | |
4528 | if (expr1.X_add_number >= -0x8000 | |
4529 | && expr1.X_add_number < 0x8000) | |
4530 | { | |
4531 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4532 | p += 4; | |
4533 | macro_build (p, &icnt, &expr1, | |
ca4e0257 | 4534 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
252b5132 RH |
4535 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
4536 | /* FIXME: If add_number is 0, and there was no base | |
4537 | register, the external symbol case ended with a load, | |
4538 | so if the symbol turns out to not be external, and | |
4539 | the next instruction uses tempreg, an unnecessary nop | |
4540 | will be inserted. */ | |
4541 | } | |
4542 | else | |
4543 | { | |
4544 | if (breg == treg) | |
4545 | { | |
4546 | /* We must add in the base register now, as in the | |
4547 | external symbol case. */ | |
4548 | assert (tempreg == AT); | |
4549 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4550 | p += 4; | |
4551 | macro_build (p, &icnt, (expressionS *) NULL, | |
ca4e0257 | 4552 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
4553 | "d,v,t", treg, AT, breg); |
4554 | p += 4; | |
4555 | tempreg = treg; | |
4556 | /* We set breg to 0 because we have arranged to add | |
4557 | it in in both cases. */ | |
4558 | breg = 0; | |
4559 | } | |
4560 | ||
4561 | macro_build_lui (p, &icnt, &expr1, AT); | |
4562 | p += 4; | |
4563 | macro_build (p, &icnt, &expr1, | |
ca4e0257 | 4564 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
252b5132 RH |
4565 | "t,r,j", AT, AT, (int) BFD_RELOC_LO16); |
4566 | p += 4; | |
4567 | macro_build (p, &icnt, (expressionS *) NULL, | |
ca4e0257 | 4568 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
4569 | "d,v,t", tempreg, tempreg, AT); |
4570 | p += 4; | |
4571 | } | |
4572 | } | |
4573 | else if (mips_pic == EMBEDDED_PIC) | |
4574 | { | |
4575 | /* We use | |
4576 | addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL) | |
4577 | */ | |
4578 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
ca4e0257 | 4579 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
252b5132 RH |
4580 | "t,r,j", tempreg, GP, (int) BFD_RELOC_MIPS_GPREL); |
4581 | } | |
4582 | else | |
4583 | abort (); | |
4584 | ||
4585 | if (breg != 0) | |
4586 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 4587 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
4588 | "d,v,t", treg, tempreg, breg); |
4589 | ||
4590 | if (! used_at) | |
4591 | return; | |
4592 | ||
4593 | break; | |
4594 | ||
4595 | case M_J_A: | |
4596 | /* The j instruction may not be used in PIC code, since it | |
4597 | requires an absolute address. We convert it to a b | |
4598 | instruction. */ | |
4599 | if (mips_pic == NO_PIC) | |
4600 | macro_build ((char *) NULL, &icnt, &offset_expr, "j", "a"); | |
4601 | else | |
4602 | macro_build ((char *) NULL, &icnt, &offset_expr, "b", "p"); | |
4603 | return; | |
4604 | ||
4605 | /* The jal instructions must be handled as macros because when | |
4606 | generating PIC code they expand to multi-instruction | |
4607 | sequences. Normally they are simple instructions. */ | |
4608 | case M_JAL_1: | |
4609 | dreg = RA; | |
4610 | /* Fall through. */ | |
4611 | case M_JAL_2: | |
4612 | if (mips_pic == NO_PIC | |
4613 | || mips_pic == EMBEDDED_PIC) | |
4614 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "jalr", | |
4615 | "d,s", dreg, sreg); | |
4616 | else if (mips_pic == SVR4_PIC) | |
4617 | { | |
4618 | if (sreg != PIC_CALL_REG) | |
4619 | as_warn (_("MIPS PIC call to register other than $25")); | |
bdaaa2e1 | 4620 | |
252b5132 RH |
4621 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "jalr", |
4622 | "d,s", dreg, sreg); | |
4623 | if (mips_cprestore_offset < 0) | |
4624 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
4625 | else | |
4626 | { | |
4627 | expr1.X_add_number = mips_cprestore_offset; | |
4628 | macro_build ((char *) NULL, &icnt, &expr1, | |
ca4e0257 | 4629 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", |
252b5132 RH |
4630 | "t,o(b)", GP, (int) BFD_RELOC_LO16, mips_frame_reg); |
4631 | } | |
4632 | } | |
4633 | else | |
4634 | abort (); | |
4635 | ||
4636 | return; | |
4637 | ||
4638 | case M_JAL_A: | |
4639 | if (mips_pic == NO_PIC) | |
4640 | macro_build ((char *) NULL, &icnt, &offset_expr, "jal", "a"); | |
4641 | else if (mips_pic == SVR4_PIC) | |
4642 | { | |
4643 | /* If this is a reference to an external symbol, and we are | |
4644 | using a small GOT, we want | |
4645 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16) | |
4646 | nop | |
4647 | jalr $25 | |
4648 | nop | |
4649 | lw $gp,cprestore($sp) | |
4650 | The cprestore value is set using the .cprestore | |
4651 | pseudo-op. If we are using a big GOT, we want | |
4652 | lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16) | |
4653 | addu $25,$25,$gp | |
4654 | lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16) | |
4655 | nop | |
4656 | jalr $25 | |
4657 | nop | |
4658 | lw $gp,cprestore($sp) | |
4659 | If the symbol is not external, we want | |
4660 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4661 | nop | |
4662 | addiu $25,$25,<sym> (BFD_RELOC_LO16) | |
4663 | jalr $25 | |
4664 | nop | |
4665 | lw $gp,cprestore($sp) */ | |
4666 | frag_grow (40); | |
4667 | if (! mips_big_got) | |
4668 | { | |
4669 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
ca4e0257 | 4670 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", |
252b5132 RH |
4671 | "t,o(b)", PIC_CALL_REG, |
4672 | (int) BFD_RELOC_MIPS_CALL16, GP); | |
4673 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4674 | "nop", ""); | |
4675 | p = frag_var (rs_machine_dependent, 4, 0, | |
4676 | RELAX_ENCODE (0, 4, -8, 0, 0, 0), | |
4677 | offset_expr.X_add_symbol, (offsetT) 0, | |
4678 | (char *) NULL); | |
4679 | } | |
4680 | else | |
4681 | { | |
4682 | int gpdel; | |
4683 | ||
4684 | if (reg_needs_delay (GP)) | |
4685 | gpdel = 4; | |
4686 | else | |
4687 | gpdel = 0; | |
4688 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
4689 | PIC_CALL_REG, (int) BFD_RELOC_MIPS_CALL_HI16); | |
4690 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 4691 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
4692 | "d,v,t", PIC_CALL_REG, PIC_CALL_REG, GP); |
4693 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
ca4e0257 | 4694 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", |
252b5132 RH |
4695 | "t,o(b)", PIC_CALL_REG, |
4696 | (int) BFD_RELOC_MIPS_CALL_LO16, PIC_CALL_REG); | |
4697 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4698 | "nop", ""); | |
4699 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, | |
4700 | RELAX_ENCODE (16, 12 + gpdel, gpdel, 8 + gpdel, | |
4701 | 0, 0), | |
4702 | offset_expr.X_add_symbol, (offsetT) 0, | |
4703 | (char *) NULL); | |
4704 | if (gpdel > 0) | |
4705 | { | |
4706 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4707 | p += 4; | |
4708 | } | |
4709 | macro_build (p, &icnt, &offset_expr, | |
ca4e0257 | 4710 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", |
252b5132 RH |
4711 | "t,o(b)", PIC_CALL_REG, |
4712 | (int) BFD_RELOC_MIPS_GOT16, GP); | |
4713 | p += 4; | |
4714 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4715 | p += 4; | |
bdaaa2e1 | 4716 | } |
252b5132 | 4717 | macro_build (p, &icnt, &offset_expr, |
ca4e0257 | 4718 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
252b5132 RH |
4719 | "t,r,j", PIC_CALL_REG, PIC_CALL_REG, |
4720 | (int) BFD_RELOC_LO16); | |
4721 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4722 | "jalr", "s", PIC_CALL_REG); | |
4723 | if (mips_cprestore_offset < 0) | |
4724 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
4725 | else | |
4726 | { | |
4727 | if (mips_opts.noreorder) | |
4728 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4729 | "nop", ""); | |
4730 | expr1.X_add_number = mips_cprestore_offset; | |
4731 | macro_build ((char *) NULL, &icnt, &expr1, | |
ca4e0257 | 4732 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", |
252b5132 RH |
4733 | "t,o(b)", GP, (int) BFD_RELOC_LO16, |
4734 | mips_frame_reg); | |
4735 | } | |
4736 | } | |
4737 | else if (mips_pic == EMBEDDED_PIC) | |
4738 | { | |
4739 | macro_build ((char *) NULL, &icnt, &offset_expr, "bal", "p"); | |
4740 | /* The linker may expand the call to a longer sequence which | |
4741 | uses $at, so we must break rather than return. */ | |
4742 | break; | |
4743 | } | |
4744 | else | |
4745 | abort (); | |
4746 | ||
4747 | return; | |
4748 | ||
4749 | case M_LB_AB: | |
4750 | s = "lb"; | |
4751 | goto ld; | |
4752 | case M_LBU_AB: | |
4753 | s = "lbu"; | |
4754 | goto ld; | |
4755 | case M_LH_AB: | |
4756 | s = "lh"; | |
4757 | goto ld; | |
4758 | case M_LHU_AB: | |
4759 | s = "lhu"; | |
4760 | goto ld; | |
4761 | case M_LW_AB: | |
4762 | s = "lw"; | |
4763 | goto ld; | |
4764 | case M_LWC0_AB: | |
4765 | s = "lwc0"; | |
bdaaa2e1 | 4766 | /* Itbl support may require additional care here. */ |
252b5132 RH |
4767 | coproc = 1; |
4768 | goto ld; | |
4769 | case M_LWC1_AB: | |
4770 | s = "lwc1"; | |
bdaaa2e1 | 4771 | /* Itbl support may require additional care here. */ |
252b5132 RH |
4772 | coproc = 1; |
4773 | goto ld; | |
4774 | case M_LWC2_AB: | |
4775 | s = "lwc2"; | |
bdaaa2e1 | 4776 | /* Itbl support may require additional care here. */ |
252b5132 RH |
4777 | coproc = 1; |
4778 | goto ld; | |
4779 | case M_LWC3_AB: | |
4780 | s = "lwc3"; | |
bdaaa2e1 | 4781 | /* Itbl support may require additional care here. */ |
252b5132 RH |
4782 | coproc = 1; |
4783 | goto ld; | |
4784 | case M_LWL_AB: | |
4785 | s = "lwl"; | |
4786 | lr = 1; | |
4787 | goto ld; | |
4788 | case M_LWR_AB: | |
4789 | s = "lwr"; | |
4790 | lr = 1; | |
4791 | goto ld; | |
4792 | case M_LDC1_AB: | |
ec68c924 | 4793 | if (mips_arch == CPU_R4650) |
252b5132 RH |
4794 | { |
4795 | as_bad (_("opcode not supported on this processor")); | |
4796 | return; | |
4797 | } | |
4798 | s = "ldc1"; | |
bdaaa2e1 | 4799 | /* Itbl support may require additional care here. */ |
252b5132 RH |
4800 | coproc = 1; |
4801 | goto ld; | |
4802 | case M_LDC2_AB: | |
4803 | s = "ldc2"; | |
bdaaa2e1 | 4804 | /* Itbl support may require additional care here. */ |
252b5132 RH |
4805 | coproc = 1; |
4806 | goto ld; | |
4807 | case M_LDC3_AB: | |
4808 | s = "ldc3"; | |
bdaaa2e1 | 4809 | /* Itbl support may require additional care here. */ |
252b5132 RH |
4810 | coproc = 1; |
4811 | goto ld; | |
4812 | case M_LDL_AB: | |
4813 | s = "ldl"; | |
4814 | lr = 1; | |
4815 | goto ld; | |
4816 | case M_LDR_AB: | |
4817 | s = "ldr"; | |
4818 | lr = 1; | |
4819 | goto ld; | |
4820 | case M_LL_AB: | |
4821 | s = "ll"; | |
4822 | goto ld; | |
4823 | case M_LLD_AB: | |
4824 | s = "lld"; | |
4825 | goto ld; | |
4826 | case M_LWU_AB: | |
4827 | s = "lwu"; | |
4828 | ld: | |
4829 | if (breg == treg || coproc || lr) | |
4830 | { | |
4831 | tempreg = AT; | |
4832 | used_at = 1; | |
4833 | } | |
4834 | else | |
4835 | { | |
4836 | tempreg = treg; | |
4837 | used_at = 0; | |
4838 | } | |
4839 | goto ld_st; | |
4840 | case M_SB_AB: | |
4841 | s = "sb"; | |
4842 | goto st; | |
4843 | case M_SH_AB: | |
4844 | s = "sh"; | |
4845 | goto st; | |
4846 | case M_SW_AB: | |
4847 | s = "sw"; | |
4848 | goto st; | |
4849 | case M_SWC0_AB: | |
4850 | s = "swc0"; | |
bdaaa2e1 | 4851 | /* Itbl support may require additional care here. */ |
252b5132 RH |
4852 | coproc = 1; |
4853 | goto st; | |
4854 | case M_SWC1_AB: | |
4855 | s = "swc1"; | |
bdaaa2e1 | 4856 | /* Itbl support may require additional care here. */ |
252b5132 RH |
4857 | coproc = 1; |
4858 | goto st; | |
4859 | case M_SWC2_AB: | |
4860 | s = "swc2"; | |
bdaaa2e1 | 4861 | /* Itbl support may require additional care here. */ |
252b5132 RH |
4862 | coproc = 1; |
4863 | goto st; | |
4864 | case M_SWC3_AB: | |
4865 | s = "swc3"; | |
bdaaa2e1 | 4866 | /* Itbl support may require additional care here. */ |
252b5132 RH |
4867 | coproc = 1; |
4868 | goto st; | |
4869 | case M_SWL_AB: | |
4870 | s = "swl"; | |
4871 | goto st; | |
4872 | case M_SWR_AB: | |
4873 | s = "swr"; | |
4874 | goto st; | |
4875 | case M_SC_AB: | |
4876 | s = "sc"; | |
4877 | goto st; | |
4878 | case M_SCD_AB: | |
4879 | s = "scd"; | |
4880 | goto st; | |
4881 | case M_SDC1_AB: | |
ec68c924 | 4882 | if (mips_arch == CPU_R4650) |
252b5132 RH |
4883 | { |
4884 | as_bad (_("opcode not supported on this processor")); | |
4885 | return; | |
4886 | } | |
4887 | s = "sdc1"; | |
4888 | coproc = 1; | |
bdaaa2e1 | 4889 | /* Itbl support may require additional care here. */ |
252b5132 RH |
4890 | goto st; |
4891 | case M_SDC2_AB: | |
4892 | s = "sdc2"; | |
bdaaa2e1 | 4893 | /* Itbl support may require additional care here. */ |
252b5132 RH |
4894 | coproc = 1; |
4895 | goto st; | |
4896 | case M_SDC3_AB: | |
4897 | s = "sdc3"; | |
bdaaa2e1 | 4898 | /* Itbl support may require additional care here. */ |
252b5132 RH |
4899 | coproc = 1; |
4900 | goto st; | |
4901 | case M_SDL_AB: | |
4902 | s = "sdl"; | |
4903 | goto st; | |
4904 | case M_SDR_AB: | |
4905 | s = "sdr"; | |
4906 | st: | |
4907 | tempreg = AT; | |
4908 | used_at = 1; | |
4909 | ld_st: | |
bdaaa2e1 | 4910 | /* Itbl support may require additional care here. */ |
252b5132 RH |
4911 | if (mask == M_LWC1_AB |
4912 | || mask == M_SWC1_AB | |
4913 | || mask == M_LDC1_AB | |
4914 | || mask == M_SDC1_AB | |
4915 | || mask == M_L_DAB | |
4916 | || mask == M_S_DAB) | |
4917 | fmt = "T,o(b)"; | |
4918 | else if (coproc) | |
4919 | fmt = "E,o(b)"; | |
4920 | else | |
4921 | fmt = "t,o(b)"; | |
4922 | ||
4923 | if (offset_expr.X_op != O_constant | |
4924 | && offset_expr.X_op != O_symbol) | |
4925 | { | |
4926 | as_bad (_("expression too complex")); | |
4927 | offset_expr.X_op = O_constant; | |
4928 | } | |
4929 | ||
4930 | /* A constant expression in PIC code can be handled just as it | |
4931 | is in non PIC code. */ | |
4932 | if (mips_pic == NO_PIC | |
4933 | || offset_expr.X_op == O_constant) | |
4934 | { | |
4935 | /* If this is a reference to a GP relative symbol, and there | |
4936 | is no base register, we want | |
4937 | <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL) | |
4938 | Otherwise, if there is no base register, we want | |
4939 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
4940 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
4941 | If we have a constant, we need two instructions anyhow, | |
4942 | so we always use the latter form. | |
4943 | ||
4944 | If we have a base register, and this is a reference to a | |
4945 | GP relative symbol, we want | |
4946 | addu $tempreg,$breg,$gp | |
4947 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL) | |
4948 | Otherwise we want | |
4949 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
4950 | addu $tempreg,$tempreg,$breg | |
4951 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
4952 | With a constant we always use the latter case. */ | |
4953 | if (breg == 0) | |
4954 | { | |
4955 | if ((valueT) offset_expr.X_add_number >= MAX_GPREL_OFFSET | |
4956 | || nopic_need_relax (offset_expr.X_add_symbol, 1)) | |
4957 | p = NULL; | |
4958 | else | |
4959 | { | |
4960 | frag_grow (20); | |
4961 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
4962 | treg, (int) BFD_RELOC_MIPS_GPREL, GP); | |
4963 | p = frag_var (rs_machine_dependent, 8, 0, | |
4964 | RELAX_ENCODE (4, 8, 0, 4, 0, | |
4965 | (mips_opts.warn_about_macros | |
4966 | || (used_at | |
4967 | && mips_opts.noat))), | |
4968 | offset_expr.X_add_symbol, (offsetT) 0, | |
4969 | (char *) NULL); | |
4970 | used_at = 0; | |
4971 | } | |
4972 | macro_build_lui (p, &icnt, &offset_expr, tempreg); | |
4973 | if (p != NULL) | |
4974 | p += 4; | |
4975 | macro_build (p, &icnt, &offset_expr, s, fmt, treg, | |
4976 | (int) BFD_RELOC_LO16, tempreg); | |
4977 | } | |
4978 | else | |
4979 | { | |
4980 | if ((valueT) offset_expr.X_add_number >= MAX_GPREL_OFFSET | |
4981 | || nopic_need_relax (offset_expr.X_add_symbol, 1)) | |
4982 | p = NULL; | |
4983 | else | |
4984 | { | |
4985 | frag_grow (28); | |
4986 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 4987 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
4988 | "d,v,t", tempreg, breg, GP); |
4989 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
4990 | treg, (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
4991 | p = frag_var (rs_machine_dependent, 12, 0, | |
4992 | RELAX_ENCODE (8, 12, 0, 8, 0, 0), | |
4993 | offset_expr.X_add_symbol, (offsetT) 0, | |
4994 | (char *) NULL); | |
4995 | } | |
4996 | macro_build_lui (p, &icnt, &offset_expr, tempreg); | |
4997 | if (p != NULL) | |
4998 | p += 4; | |
4999 | macro_build (p, &icnt, (expressionS *) NULL, | |
ca4e0257 | 5000 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
5001 | "d,v,t", tempreg, tempreg, breg); |
5002 | if (p != NULL) | |
5003 | p += 4; | |
5004 | macro_build (p, &icnt, &offset_expr, s, fmt, treg, | |
5005 | (int) BFD_RELOC_LO16, tempreg); | |
5006 | } | |
5007 | } | |
5008 | else if (mips_pic == SVR4_PIC && ! mips_big_got) | |
5009 | { | |
5010 | /* If this is a reference to an external symbol, we want | |
5011 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5012 | nop | |
5013 | <op> $treg,0($tempreg) | |
5014 | Otherwise we want | |
5015 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5016 | nop | |
5017 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
5018 | <op> $treg,0($tempreg) | |
5019 | If there is a base register, we add it to $tempreg before | |
5020 | the <op>. If there is a constant, we stick it in the | |
5021 | <op> instruction. We don't handle constants larger than | |
5022 | 16 bits, because we have no way to load the upper 16 bits | |
5023 | (actually, we could handle them for the subset of cases | |
5024 | in which we are not using $at). */ | |
5025 | assert (offset_expr.X_op == O_symbol); | |
5026 | expr1.X_add_number = offset_expr.X_add_number; | |
5027 | offset_expr.X_add_number = 0; | |
5028 | if (expr1.X_add_number < -0x8000 | |
5029 | || expr1.X_add_number >= 0x8000) | |
5030 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
5031 | frag_grow (20); | |
5032 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
ca4e0257 | 5033 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", |
252b5132 RH |
5034 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, GP); |
5035 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); | |
bdaaa2e1 | 5036 | p = frag_var (rs_machine_dependent, 4, 0, |
252b5132 RH |
5037 | RELAX_ENCODE (0, 4, -8, 0, 0, 0), |
5038 | offset_expr.X_add_symbol, (offsetT) 0, | |
5039 | (char *) NULL); | |
5040 | macro_build (p, &icnt, &offset_expr, | |
ca4e0257 | 5041 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
252b5132 RH |
5042 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
5043 | if (breg != 0) | |
5044 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 5045 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
5046 | "d,v,t", tempreg, tempreg, breg); |
5047 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, treg, | |
5048 | (int) BFD_RELOC_LO16, tempreg); | |
5049 | } | |
5050 | else if (mips_pic == SVR4_PIC) | |
5051 | { | |
5052 | int gpdel; | |
5053 | ||
5054 | /* If this is a reference to an external symbol, we want | |
5055 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5056 | addu $tempreg,$tempreg,$gp | |
5057 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5058 | <op> $treg,0($tempreg) | |
5059 | Otherwise we want | |
5060 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5061 | nop | |
5062 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
5063 | <op> $treg,0($tempreg) | |
5064 | If there is a base register, we add it to $tempreg before | |
5065 | the <op>. If there is a constant, we stick it in the | |
5066 | <op> instruction. We don't handle constants larger than | |
5067 | 16 bits, because we have no way to load the upper 16 bits | |
5068 | (actually, we could handle them for the subset of cases | |
5069 | in which we are not using $at). */ | |
5070 | assert (offset_expr.X_op == O_symbol); | |
5071 | expr1.X_add_number = offset_expr.X_add_number; | |
5072 | offset_expr.X_add_number = 0; | |
5073 | if (expr1.X_add_number < -0x8000 | |
5074 | || expr1.X_add_number >= 0x8000) | |
5075 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
5076 | if (reg_needs_delay (GP)) | |
5077 | gpdel = 4; | |
5078 | else | |
5079 | gpdel = 0; | |
5080 | frag_grow (36); | |
5081 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
5082 | tempreg, (int) BFD_RELOC_MIPS_GOT_HI16); | |
5083 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 5084 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
5085 | "d,v,t", tempreg, tempreg, GP); |
5086 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
ca4e0257 | 5087 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", |
252b5132 RH |
5088 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT_LO16, |
5089 | tempreg); | |
5090 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, | |
5091 | RELAX_ENCODE (12, 12 + gpdel, gpdel, 8 + gpdel, 0, 0), | |
5092 | offset_expr.X_add_symbol, (offsetT) 0, (char *) NULL); | |
5093 | if (gpdel > 0) | |
5094 | { | |
5095 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
5096 | p += 4; | |
5097 | } | |
5098 | macro_build (p, &icnt, &offset_expr, | |
ca4e0257 | 5099 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", |
252b5132 RH |
5100 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, GP); |
5101 | p += 4; | |
5102 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
5103 | p += 4; | |
5104 | macro_build (p, &icnt, &offset_expr, | |
ca4e0257 | 5105 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
252b5132 RH |
5106 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
5107 | if (breg != 0) | |
5108 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 5109 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
5110 | "d,v,t", tempreg, tempreg, breg); |
5111 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, treg, | |
5112 | (int) BFD_RELOC_LO16, tempreg); | |
5113 | } | |
5114 | else if (mips_pic == EMBEDDED_PIC) | |
5115 | { | |
5116 | /* If there is no base register, we want | |
5117 | <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL) | |
5118 | If there is a base register, we want | |
5119 | addu $tempreg,$breg,$gp | |
5120 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL) | |
5121 | */ | |
5122 | assert (offset_expr.X_op == O_symbol); | |
5123 | if (breg == 0) | |
5124 | { | |
5125 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
5126 | treg, (int) BFD_RELOC_MIPS_GPREL, GP); | |
5127 | used_at = 0; | |
5128 | } | |
5129 | else | |
5130 | { | |
5131 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 5132 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
5133 | "d,v,t", tempreg, breg, GP); |
5134 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
5135 | treg, (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
5136 | } | |
5137 | } | |
5138 | else | |
5139 | abort (); | |
5140 | ||
5141 | if (! used_at) | |
5142 | return; | |
5143 | ||
5144 | break; | |
5145 | ||
5146 | case M_LI: | |
5147 | case M_LI_S: | |
5148 | load_register (&icnt, treg, &imm_expr, 0); | |
5149 | return; | |
5150 | ||
5151 | case M_DLI: | |
5152 | load_register (&icnt, treg, &imm_expr, 1); | |
5153 | return; | |
5154 | ||
5155 | case M_LI_SS: | |
5156 | if (imm_expr.X_op == O_constant) | |
5157 | { | |
5158 | load_register (&icnt, AT, &imm_expr, 0); | |
5159 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5160 | "mtc1", "t,G", AT, treg); | |
5161 | break; | |
5162 | } | |
5163 | else | |
5164 | { | |
5165 | assert (offset_expr.X_op == O_symbol | |
5166 | && strcmp (segment_name (S_GET_SEGMENT | |
5167 | (offset_expr.X_add_symbol)), | |
5168 | ".lit4") == 0 | |
5169 | && offset_expr.X_add_number == 0); | |
5170 | macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)", | |
5171 | treg, (int) BFD_RELOC_MIPS_LITERAL, GP); | |
5172 | return; | |
5173 | } | |
5174 | ||
5175 | case M_LI_D: | |
ca4e0257 RS |
5176 | /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits |
5177 | wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high | |
5178 | order 32 bits of the value and the low order 32 bits are either | |
5179 | zero or in OFFSET_EXPR. */ | |
252b5132 RH |
5180 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) |
5181 | { | |
ca4e0257 | 5182 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
5183 | load_register (&icnt, treg, &imm_expr, 1); |
5184 | else | |
5185 | { | |
5186 | int hreg, lreg; | |
5187 | ||
5188 | if (target_big_endian) | |
5189 | { | |
5190 | hreg = treg; | |
5191 | lreg = treg + 1; | |
5192 | } | |
5193 | else | |
5194 | { | |
5195 | hreg = treg + 1; | |
5196 | lreg = treg; | |
5197 | } | |
5198 | ||
5199 | if (hreg <= 31) | |
5200 | load_register (&icnt, hreg, &imm_expr, 0); | |
5201 | if (lreg <= 31) | |
5202 | { | |
5203 | if (offset_expr.X_op == O_absent) | |
ea1fb5dc | 5204 | move_register (&icnt, lreg, 0); |
252b5132 RH |
5205 | else |
5206 | { | |
5207 | assert (offset_expr.X_op == O_constant); | |
5208 | load_register (&icnt, lreg, &offset_expr, 0); | |
5209 | } | |
5210 | } | |
5211 | } | |
5212 | return; | |
5213 | } | |
5214 | ||
5215 | /* We know that sym is in the .rdata section. First we get the | |
5216 | upper 16 bits of the address. */ | |
5217 | if (mips_pic == NO_PIC) | |
5218 | { | |
5219 | /* FIXME: This won't work for a 64 bit address. */ | |
5220 | macro_build_lui ((char *) NULL, &icnt, &offset_expr, AT); | |
5221 | } | |
5222 | else if (mips_pic == SVR4_PIC) | |
5223 | { | |
5224 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
ca4e0257 | 5225 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", |
252b5132 RH |
5226 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP); |
5227 | } | |
5228 | else if (mips_pic == EMBEDDED_PIC) | |
5229 | { | |
5230 | /* For embedded PIC we pick up the entire address off $gp in | |
5231 | a single instruction. */ | |
5232 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
ca4e0257 | 5233 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
252b5132 RH |
5234 | "t,r,j", AT, GP, (int) BFD_RELOC_MIPS_GPREL); |
5235 | offset_expr.X_op = O_constant; | |
5236 | offset_expr.X_add_number = 0; | |
5237 | } | |
5238 | else | |
5239 | abort (); | |
bdaaa2e1 | 5240 | |
252b5132 | 5241 | /* Now we load the register(s). */ |
ca4e0257 | 5242 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
5243 | macro_build ((char *) NULL, &icnt, &offset_expr, "ld", "t,o(b)", |
5244 | treg, (int) BFD_RELOC_LO16, AT); | |
5245 | else | |
5246 | { | |
5247 | macro_build ((char *) NULL, &icnt, &offset_expr, "lw", "t,o(b)", | |
5248 | treg, (int) BFD_RELOC_LO16, AT); | |
5249 | if (treg != 31) | |
5250 | { | |
5251 | /* FIXME: How in the world do we deal with the possible | |
5252 | overflow here? */ | |
5253 | offset_expr.X_add_number += 4; | |
5254 | macro_build ((char *) NULL, &icnt, &offset_expr, "lw", "t,o(b)", | |
5255 | treg + 1, (int) BFD_RELOC_LO16, AT); | |
5256 | } | |
5257 | } | |
5258 | ||
5259 | /* To avoid confusion in tc_gen_reloc, we must ensure that this | |
5260 | does not become a variant frag. */ | |
5261 | frag_wane (frag_now); | |
5262 | frag_new (0); | |
5263 | ||
5264 | break; | |
5265 | ||
5266 | case M_LI_DD: | |
ca4e0257 RS |
5267 | /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits |
5268 | wide, IMM_EXPR is the entire value and the GPRs are known to be 64 | |
5269 | bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of | |
5270 | the value and the low order 32 bits are either zero or in | |
5271 | OFFSET_EXPR. */ | |
252b5132 RH |
5272 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) |
5273 | { | |
ca4e0257 RS |
5274 | load_register (&icnt, AT, &imm_expr, HAVE_64BIT_FPRS); |
5275 | if (HAVE_64BIT_FPRS) | |
5276 | { | |
5277 | assert (HAVE_64BIT_GPRS); | |
5278 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5279 | "dmtc1", "t,S", AT, treg); | |
5280 | } | |
252b5132 RH |
5281 | else |
5282 | { | |
5283 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5284 | "mtc1", "t,G", AT, treg + 1); | |
5285 | if (offset_expr.X_op == O_absent) | |
5286 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5287 | "mtc1", "t,G", 0, treg); | |
5288 | else | |
5289 | { | |
5290 | assert (offset_expr.X_op == O_constant); | |
5291 | load_register (&icnt, AT, &offset_expr, 0); | |
5292 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5293 | "mtc1", "t,G", AT, treg); | |
5294 | } | |
5295 | } | |
5296 | break; | |
5297 | } | |
5298 | ||
5299 | assert (offset_expr.X_op == O_symbol | |
5300 | && offset_expr.X_add_number == 0); | |
5301 | s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol)); | |
5302 | if (strcmp (s, ".lit8") == 0) | |
5303 | { | |
e7af610e | 5304 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 RH |
5305 | { |
5306 | macro_build ((char *) NULL, &icnt, &offset_expr, "ldc1", | |
5307 | "T,o(b)", treg, (int) BFD_RELOC_MIPS_LITERAL, GP); | |
5308 | return; | |
5309 | } | |
5310 | breg = GP; | |
5311 | r = BFD_RELOC_MIPS_LITERAL; | |
5312 | goto dob; | |
5313 | } | |
5314 | else | |
5315 | { | |
5316 | assert (strcmp (s, RDATA_SECTION_NAME) == 0); | |
5317 | if (mips_pic == SVR4_PIC) | |
5318 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
ca4e0257 | 5319 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", |
252b5132 RH |
5320 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP); |
5321 | else | |
5322 | { | |
5323 | /* FIXME: This won't work for a 64 bit address. */ | |
5324 | macro_build_lui ((char *) NULL, &icnt, &offset_expr, AT); | |
5325 | } | |
bdaaa2e1 | 5326 | |
e7af610e | 5327 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 RH |
5328 | { |
5329 | macro_build ((char *) NULL, &icnt, &offset_expr, "ldc1", | |
5330 | "T,o(b)", treg, (int) BFD_RELOC_LO16, AT); | |
5331 | ||
5332 | /* To avoid confusion in tc_gen_reloc, we must ensure | |
5333 | that this does not become a variant frag. */ | |
5334 | frag_wane (frag_now); | |
5335 | frag_new (0); | |
5336 | ||
5337 | break; | |
5338 | } | |
5339 | breg = AT; | |
5340 | r = BFD_RELOC_LO16; | |
5341 | goto dob; | |
5342 | } | |
5343 | ||
5344 | case M_L_DOB: | |
ec68c924 | 5345 | if (mips_arch == CPU_R4650) |
252b5132 RH |
5346 | { |
5347 | as_bad (_("opcode not supported on this processor")); | |
5348 | return; | |
5349 | } | |
5350 | /* Even on a big endian machine $fn comes before $fn+1. We have | |
5351 | to adjust when loading from memory. */ | |
5352 | r = BFD_RELOC_LO16; | |
5353 | dob: | |
e7af610e | 5354 | assert (mips_opts.isa == ISA_MIPS1); |
252b5132 RH |
5355 | macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)", |
5356 | target_big_endian ? treg + 1 : treg, | |
5357 | (int) r, breg); | |
5358 | /* FIXME: A possible overflow which I don't know how to deal | |
5359 | with. */ | |
5360 | offset_expr.X_add_number += 4; | |
5361 | macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)", | |
5362 | target_big_endian ? treg : treg + 1, | |
5363 | (int) r, breg); | |
5364 | ||
5365 | /* To avoid confusion in tc_gen_reloc, we must ensure that this | |
5366 | does not become a variant frag. */ | |
5367 | frag_wane (frag_now); | |
5368 | frag_new (0); | |
5369 | ||
5370 | if (breg != AT) | |
5371 | return; | |
5372 | break; | |
5373 | ||
5374 | case M_L_DAB: | |
5375 | /* | |
5376 | * The MIPS assembler seems to check for X_add_number not | |
5377 | * being double aligned and generating: | |
5378 | * lui at,%hi(foo+1) | |
5379 | * addu at,at,v1 | |
5380 | * addiu at,at,%lo(foo+1) | |
5381 | * lwc1 f2,0(at) | |
5382 | * lwc1 f3,4(at) | |
5383 | * But, the resulting address is the same after relocation so why | |
5384 | * generate the extra instruction? | |
5385 | */ | |
ec68c924 | 5386 | if (mips_arch == CPU_R4650) |
252b5132 RH |
5387 | { |
5388 | as_bad (_("opcode not supported on this processor")); | |
5389 | return; | |
5390 | } | |
bdaaa2e1 | 5391 | /* Itbl support may require additional care here. */ |
252b5132 | 5392 | coproc = 1; |
e7af610e | 5393 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 RH |
5394 | { |
5395 | s = "ldc1"; | |
5396 | goto ld; | |
5397 | } | |
5398 | ||
5399 | s = "lwc1"; | |
5400 | fmt = "T,o(b)"; | |
5401 | goto ldd_std; | |
5402 | ||
5403 | case M_S_DAB: | |
ec68c924 | 5404 | if (mips_arch == CPU_R4650) |
252b5132 RH |
5405 | { |
5406 | as_bad (_("opcode not supported on this processor")); | |
5407 | return; | |
5408 | } | |
5409 | ||
e7af610e | 5410 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 RH |
5411 | { |
5412 | s = "sdc1"; | |
5413 | goto st; | |
5414 | } | |
5415 | ||
5416 | s = "swc1"; | |
5417 | fmt = "T,o(b)"; | |
bdaaa2e1 | 5418 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5419 | coproc = 1; |
5420 | goto ldd_std; | |
5421 | ||
5422 | case M_LD_AB: | |
ca4e0257 | 5423 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
5424 | { |
5425 | s = "ld"; | |
5426 | goto ld; | |
5427 | } | |
5428 | ||
5429 | s = "lw"; | |
5430 | fmt = "t,o(b)"; | |
5431 | goto ldd_std; | |
5432 | ||
5433 | case M_SD_AB: | |
ca4e0257 | 5434 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
5435 | { |
5436 | s = "sd"; | |
5437 | goto st; | |
5438 | } | |
5439 | ||
5440 | s = "sw"; | |
5441 | fmt = "t,o(b)"; | |
5442 | ||
5443 | ldd_std: | |
5444 | if (offset_expr.X_op != O_symbol | |
5445 | && offset_expr.X_op != O_constant) | |
5446 | { | |
5447 | as_bad (_("expression too complex")); | |
5448 | offset_expr.X_op = O_constant; | |
5449 | } | |
5450 | ||
5451 | /* Even on a big endian machine $fn comes before $fn+1. We have | |
5452 | to adjust when loading from memory. We set coproc if we must | |
5453 | load $fn+1 first. */ | |
bdaaa2e1 | 5454 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5455 | if (! target_big_endian) |
5456 | coproc = 0; | |
5457 | ||
5458 | if (mips_pic == NO_PIC | |
5459 | || offset_expr.X_op == O_constant) | |
5460 | { | |
5461 | /* If this is a reference to a GP relative symbol, we want | |
5462 | <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL) | |
5463 | <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL) | |
5464 | If we have a base register, we use this | |
5465 | addu $at,$breg,$gp | |
5466 | <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL) | |
5467 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL) | |
5468 | If this is not a GP relative symbol, we want | |
5469 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
5470 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
5471 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
5472 | If there is a base register, we add it to $at after the | |
5473 | lui instruction. If there is a constant, we always use | |
5474 | the last case. */ | |
5475 | if ((valueT) offset_expr.X_add_number >= MAX_GPREL_OFFSET | |
5476 | || nopic_need_relax (offset_expr.X_add_symbol, 1)) | |
5477 | { | |
5478 | p = NULL; | |
5479 | used_at = 1; | |
5480 | } | |
5481 | else | |
5482 | { | |
5483 | int off; | |
5484 | ||
5485 | if (breg == 0) | |
5486 | { | |
5487 | frag_grow (28); | |
5488 | tempreg = GP; | |
5489 | off = 0; | |
5490 | used_at = 0; | |
5491 | } | |
5492 | else | |
5493 | { | |
5494 | frag_grow (36); | |
5495 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 5496 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
5497 | "d,v,t", AT, breg, GP); |
5498 | tempreg = AT; | |
5499 | off = 4; | |
5500 | used_at = 1; | |
5501 | } | |
5502 | ||
beae10d5 | 5503 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5504 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
5505 | coproc ? treg + 1 : treg, | |
5506 | (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
5507 | offset_expr.X_add_number += 4; | |
5508 | ||
5509 | /* Set mips_optimize to 2 to avoid inserting an | |
5510 | undesired nop. */ | |
5511 | hold_mips_optimize = mips_optimize; | |
5512 | mips_optimize = 2; | |
beae10d5 | 5513 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5514 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
5515 | coproc ? treg : treg + 1, | |
5516 | (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
5517 | mips_optimize = hold_mips_optimize; | |
5518 | ||
5519 | p = frag_var (rs_machine_dependent, 12 + off, 0, | |
5520 | RELAX_ENCODE (8 + off, 12 + off, 0, 4 + off, 1, | |
5521 | used_at && mips_opts.noat), | |
5522 | offset_expr.X_add_symbol, (offsetT) 0, | |
5523 | (char *) NULL); | |
5524 | ||
5525 | /* We just generated two relocs. When tc_gen_reloc | |
5526 | handles this case, it will skip the first reloc and | |
5527 | handle the second. The second reloc already has an | |
5528 | extra addend of 4, which we added above. We must | |
5529 | subtract it out, and then subtract another 4 to make | |
5530 | the first reloc come out right. The second reloc | |
5531 | will come out right because we are going to add 4 to | |
5532 | offset_expr when we build its instruction below. | |
5533 | ||
5534 | If we have a symbol, then we don't want to include | |
5535 | the offset, because it will wind up being included | |
5536 | when we generate the reloc. */ | |
5537 | ||
5538 | if (offset_expr.X_op == O_constant) | |
5539 | offset_expr.X_add_number -= 8; | |
5540 | else | |
5541 | { | |
5542 | offset_expr.X_add_number = -4; | |
5543 | offset_expr.X_op = O_constant; | |
5544 | } | |
5545 | } | |
5546 | macro_build_lui (p, &icnt, &offset_expr, AT); | |
5547 | if (p != NULL) | |
5548 | p += 4; | |
5549 | if (breg != 0) | |
5550 | { | |
5551 | macro_build (p, &icnt, (expressionS *) NULL, | |
ca4e0257 | 5552 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
5553 | "d,v,t", AT, breg, AT); |
5554 | if (p != NULL) | |
5555 | p += 4; | |
5556 | } | |
beae10d5 | 5557 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5558 | macro_build (p, &icnt, &offset_expr, s, fmt, |
5559 | coproc ? treg + 1 : treg, | |
5560 | (int) BFD_RELOC_LO16, AT); | |
5561 | if (p != NULL) | |
5562 | p += 4; | |
5563 | /* FIXME: How do we handle overflow here? */ | |
5564 | offset_expr.X_add_number += 4; | |
beae10d5 | 5565 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5566 | macro_build (p, &icnt, &offset_expr, s, fmt, |
5567 | coproc ? treg : treg + 1, | |
5568 | (int) BFD_RELOC_LO16, AT); | |
bdaaa2e1 | 5569 | } |
252b5132 RH |
5570 | else if (mips_pic == SVR4_PIC && ! mips_big_got) |
5571 | { | |
5572 | int off; | |
5573 | ||
5574 | /* If this is a reference to an external symbol, we want | |
5575 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5576 | nop | |
5577 | <op> $treg,0($at) | |
5578 | <op> $treg+1,4($at) | |
5579 | Otherwise we want | |
5580 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5581 | nop | |
5582 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
5583 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
5584 | If there is a base register we add it to $at before the | |
5585 | lwc1 instructions. If there is a constant we include it | |
5586 | in the lwc1 instructions. */ | |
5587 | used_at = 1; | |
5588 | expr1.X_add_number = offset_expr.X_add_number; | |
5589 | offset_expr.X_add_number = 0; | |
5590 | if (expr1.X_add_number < -0x8000 | |
5591 | || expr1.X_add_number >= 0x8000 - 4) | |
5592 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
5593 | if (breg == 0) | |
5594 | off = 0; | |
5595 | else | |
5596 | off = 4; | |
5597 | frag_grow (24 + off); | |
5598 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
ca4e0257 | 5599 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", |
252b5132 RH |
5600 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP); |
5601 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); | |
5602 | if (breg != 0) | |
5603 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 5604 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 | 5605 | "d,v,t", AT, breg, AT); |
beae10d5 | 5606 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5607 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, |
5608 | coproc ? treg + 1 : treg, | |
5609 | (int) BFD_RELOC_LO16, AT); | |
5610 | expr1.X_add_number += 4; | |
5611 | ||
5612 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
5613 | nop. */ | |
5614 | hold_mips_optimize = mips_optimize; | |
5615 | mips_optimize = 2; | |
beae10d5 | 5616 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5617 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, |
5618 | coproc ? treg : treg + 1, | |
5619 | (int) BFD_RELOC_LO16, AT); | |
5620 | mips_optimize = hold_mips_optimize; | |
5621 | ||
5622 | (void) frag_var (rs_machine_dependent, 0, 0, | |
5623 | RELAX_ENCODE (0, 0, -16 - off, -8, 1, 0), | |
5624 | offset_expr.X_add_symbol, (offsetT) 0, | |
5625 | (char *) NULL); | |
5626 | } | |
5627 | else if (mips_pic == SVR4_PIC) | |
5628 | { | |
5629 | int gpdel, off; | |
5630 | ||
5631 | /* If this is a reference to an external symbol, we want | |
5632 | lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5633 | addu $at,$at,$gp | |
5634 | lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16) | |
5635 | nop | |
5636 | <op> $treg,0($at) | |
5637 | <op> $treg+1,4($at) | |
5638 | Otherwise we want | |
5639 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5640 | nop | |
5641 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
5642 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
5643 | If there is a base register we add it to $at before the | |
5644 | lwc1 instructions. If there is a constant we include it | |
5645 | in the lwc1 instructions. */ | |
5646 | used_at = 1; | |
5647 | expr1.X_add_number = offset_expr.X_add_number; | |
5648 | offset_expr.X_add_number = 0; | |
5649 | if (expr1.X_add_number < -0x8000 | |
5650 | || expr1.X_add_number >= 0x8000 - 4) | |
5651 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
5652 | if (reg_needs_delay (GP)) | |
5653 | gpdel = 4; | |
5654 | else | |
5655 | gpdel = 0; | |
5656 | if (breg == 0) | |
5657 | off = 0; | |
5658 | else | |
5659 | off = 4; | |
5660 | frag_grow (56); | |
5661 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
5662 | AT, (int) BFD_RELOC_MIPS_GOT_HI16); | |
5663 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 5664 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
5665 | "d,v,t", AT, AT, GP); |
5666 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
ca4e0257 | 5667 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", |
252b5132 RH |
5668 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT_LO16, AT); |
5669 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); | |
5670 | if (breg != 0) | |
5671 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 5672 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 | 5673 | "d,v,t", AT, breg, AT); |
beae10d5 | 5674 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5675 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, |
5676 | coproc ? treg + 1 : treg, | |
5677 | (int) BFD_RELOC_LO16, AT); | |
5678 | expr1.X_add_number += 4; | |
5679 | ||
5680 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
5681 | nop. */ | |
5682 | hold_mips_optimize = mips_optimize; | |
5683 | mips_optimize = 2; | |
beae10d5 | 5684 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5685 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, |
5686 | coproc ? treg : treg + 1, | |
5687 | (int) BFD_RELOC_LO16, AT); | |
5688 | mips_optimize = hold_mips_optimize; | |
5689 | expr1.X_add_number -= 4; | |
5690 | ||
5691 | p = frag_var (rs_machine_dependent, 16 + gpdel + off, 0, | |
5692 | RELAX_ENCODE (24 + off, 16 + gpdel + off, gpdel, | |
5693 | 8 + gpdel + off, 1, 0), | |
5694 | offset_expr.X_add_symbol, (offsetT) 0, | |
5695 | (char *) NULL); | |
5696 | if (gpdel > 0) | |
5697 | { | |
5698 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
5699 | p += 4; | |
5700 | } | |
5701 | macro_build (p, &icnt, &offset_expr, | |
ca4e0257 | 5702 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", |
252b5132 RH |
5703 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP); |
5704 | p += 4; | |
5705 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
5706 | p += 4; | |
5707 | if (breg != 0) | |
5708 | { | |
5709 | macro_build (p, &icnt, (expressionS *) NULL, | |
ca4e0257 | 5710 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
5711 | "d,v,t", AT, breg, AT); |
5712 | p += 4; | |
5713 | } | |
beae10d5 | 5714 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5715 | macro_build (p, &icnt, &expr1, s, fmt, |
5716 | coproc ? treg + 1 : treg, | |
5717 | (int) BFD_RELOC_LO16, AT); | |
5718 | p += 4; | |
5719 | expr1.X_add_number += 4; | |
5720 | ||
5721 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
5722 | nop. */ | |
5723 | hold_mips_optimize = mips_optimize; | |
5724 | mips_optimize = 2; | |
beae10d5 | 5725 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5726 | macro_build (p, &icnt, &expr1, s, fmt, |
5727 | coproc ? treg : treg + 1, | |
5728 | (int) BFD_RELOC_LO16, AT); | |
5729 | mips_optimize = hold_mips_optimize; | |
5730 | } | |
5731 | else if (mips_pic == EMBEDDED_PIC) | |
5732 | { | |
5733 | /* If there is no base register, we use | |
5734 | <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL) | |
5735 | <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL) | |
5736 | If we have a base register, we use | |
5737 | addu $at,$breg,$gp | |
5738 | <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL) | |
5739 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL) | |
5740 | */ | |
5741 | if (breg == 0) | |
5742 | { | |
5743 | tempreg = GP; | |
5744 | used_at = 0; | |
5745 | } | |
5746 | else | |
5747 | { | |
5748 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 5749 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
5750 | "d,v,t", AT, breg, GP); |
5751 | tempreg = AT; | |
5752 | used_at = 1; | |
5753 | } | |
5754 | ||
beae10d5 | 5755 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5756 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
5757 | coproc ? treg + 1 : treg, | |
5758 | (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
5759 | offset_expr.X_add_number += 4; | |
beae10d5 | 5760 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5761 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
5762 | coproc ? treg : treg + 1, | |
5763 | (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
5764 | } | |
5765 | else | |
5766 | abort (); | |
5767 | ||
5768 | if (! used_at) | |
5769 | return; | |
5770 | ||
5771 | break; | |
5772 | ||
5773 | case M_LD_OB: | |
5774 | s = "lw"; | |
5775 | goto sd_ob; | |
5776 | case M_SD_OB: | |
5777 | s = "sw"; | |
5778 | sd_ob: | |
ca4e0257 | 5779 | assert (HAVE_32BIT_ADDRESSES); |
252b5132 RH |
5780 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, |
5781 | (int) BFD_RELOC_LO16, breg); | |
5782 | offset_expr.X_add_number += 4; | |
5783 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg + 1, | |
5784 | (int) BFD_RELOC_LO16, breg); | |
5785 | return; | |
5786 | ||
5787 | /* New code added to support COPZ instructions. | |
5788 | This code builds table entries out of the macros in mip_opcodes. | |
5789 | R4000 uses interlocks to handle coproc delays. | |
5790 | Other chips (like the R3000) require nops to be inserted for delays. | |
5791 | ||
9a41af64 | 5792 | FIXME: Currently, we require that the user handles delays. |
252b5132 RH |
5793 | In order to fill delay slots for non-interlocked chips, |
5794 | we must have a way to specify delays based on the coprocessor. | |
5795 | Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc. | |
5796 | What are the side-effects of the cop instruction? | |
5797 | What cache support might we have and what are its effects? | |
5798 | Both coprocessor & memory require delays. how long??? | |
bdaaa2e1 | 5799 | What registers are read/set/modified? |
252b5132 RH |
5800 | |
5801 | If an itbl is provided to interpret cop instructions, | |
bdaaa2e1 | 5802 | this knowledge can be encoded in the itbl spec. */ |
252b5132 RH |
5803 | |
5804 | case M_COP0: | |
5805 | s = "c0"; | |
5806 | goto copz; | |
5807 | case M_COP1: | |
5808 | s = "c1"; | |
5809 | goto copz; | |
5810 | case M_COP2: | |
5811 | s = "c2"; | |
5812 | goto copz; | |
5813 | case M_COP3: | |
5814 | s = "c3"; | |
5815 | copz: | |
5816 | /* For now we just do C (same as Cz). The parameter will be | |
5817 | stored in insn_opcode by mips_ip. */ | |
5818 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "C", | |
5819 | ip->insn_opcode); | |
5820 | return; | |
5821 | ||
ea1fb5dc RS |
5822 | case M_MOVE: |
5823 | move_register (&icnt, dreg, sreg); | |
5824 | return; | |
5825 | ||
252b5132 RH |
5826 | #ifdef LOSING_COMPILER |
5827 | default: | |
5828 | /* Try and see if this is a new itbl instruction. | |
5829 | This code builds table entries out of the macros in mip_opcodes. | |
5830 | FIXME: For now we just assemble the expression and pass it's | |
5831 | value along as a 32-bit immediate. | |
bdaaa2e1 | 5832 | We may want to have the assembler assemble this value, |
252b5132 RH |
5833 | so that we gain the assembler's knowledge of delay slots, |
5834 | symbols, etc. | |
5835 | Would it be more efficient to use mask (id) here? */ | |
bdaaa2e1 | 5836 | if (itbl_have_entries |
252b5132 | 5837 | && (immed_expr = itbl_assemble (ip->insn_mo->name, ""))) |
beae10d5 | 5838 | { |
252b5132 RH |
5839 | s = ip->insn_mo->name; |
5840 | s2 = "cop3"; | |
5841 | coproc = ITBL_DECODE_PNUM (immed_expr);; | |
5842 | macro_build ((char *) NULL, &icnt, &immed_expr, s, "C"); | |
5843 | return; | |
beae10d5 | 5844 | } |
252b5132 RH |
5845 | macro2 (ip); |
5846 | return; | |
5847 | } | |
5848 | if (mips_opts.noat) | |
5849 | as_warn (_("Macro used $at after \".set noat\"")); | |
5850 | } | |
bdaaa2e1 | 5851 | |
252b5132 RH |
5852 | static void |
5853 | macro2 (ip) | |
5854 | struct mips_cl_insn *ip; | |
5855 | { | |
5856 | register int treg, sreg, dreg, breg; | |
5857 | int tempreg; | |
5858 | int mask; | |
5859 | int icnt = 0; | |
5860 | int used_at; | |
5861 | expressionS expr1; | |
5862 | const char *s; | |
5863 | const char *s2; | |
5864 | const char *fmt; | |
5865 | int likely = 0; | |
5866 | int dbl = 0; | |
5867 | int coproc = 0; | |
5868 | int lr = 0; | |
5869 | int imm = 0; | |
5870 | int off; | |
5871 | offsetT maxnum; | |
5872 | bfd_reloc_code_real_type r; | |
5873 | char *p; | |
bdaaa2e1 | 5874 | |
252b5132 RH |
5875 | treg = (ip->insn_opcode >> 16) & 0x1f; |
5876 | dreg = (ip->insn_opcode >> 11) & 0x1f; | |
5877 | sreg = breg = (ip->insn_opcode >> 21) & 0x1f; | |
5878 | mask = ip->insn_mo->mask; | |
bdaaa2e1 | 5879 | |
252b5132 RH |
5880 | expr1.X_op = O_constant; |
5881 | expr1.X_op_symbol = NULL; | |
5882 | expr1.X_add_symbol = NULL; | |
5883 | expr1.X_add_number = 1; | |
bdaaa2e1 | 5884 | |
252b5132 RH |
5885 | switch (mask) |
5886 | { | |
5887 | #endif /* LOSING_COMPILER */ | |
5888 | ||
5889 | case M_DMUL: | |
5890 | dbl = 1; | |
5891 | case M_MUL: | |
5892 | macro_build ((char *) NULL, &icnt, NULL, | |
5893 | dbl ? "dmultu" : "multu", | |
5894 | "s,t", sreg, treg); | |
5895 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); | |
5896 | return; | |
5897 | ||
5898 | case M_DMUL_I: | |
5899 | dbl = 1; | |
5900 | case M_MUL_I: | |
5901 | /* The MIPS assembler some times generates shifts and adds. I'm | |
5902 | not trying to be that fancy. GCC should do this for us | |
5903 | anyway. */ | |
5904 | load_register (&icnt, AT, &imm_expr, dbl); | |
5905 | macro_build ((char *) NULL, &icnt, NULL, | |
9a41af64 | 5906 | dbl ? "dmult" : "mult", "s,t", sreg, AT); |
252b5132 RH |
5907 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); |
5908 | break; | |
5909 | ||
5910 | case M_DMULO_I: | |
5911 | dbl = 1; | |
5912 | case M_MULO_I: | |
5913 | imm = 1; | |
5914 | goto do_mulo; | |
5915 | ||
5916 | case M_DMULO: | |
5917 | dbl = 1; | |
5918 | case M_MULO: | |
5919 | do_mulo: | |
5920 | mips_emit_delays (true); | |
5921 | ++mips_opts.noreorder; | |
5922 | mips_any_noreorder = 1; | |
5923 | if (imm) | |
5924 | load_register (&icnt, AT, &imm_expr, dbl); | |
5925 | macro_build ((char *) NULL, &icnt, NULL, | |
9a41af64 | 5926 | dbl ? "dmult" : "mult", "s,t", sreg, imm ? AT : treg); |
252b5132 RH |
5927 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); |
5928 | macro_build ((char *) NULL, &icnt, NULL, | |
9a41af64 | 5929 | dbl ? "dsra32" : "sra", "d,w,<", dreg, dreg, 31); |
252b5132 RH |
5930 | macro_build ((char *) NULL, &icnt, NULL, "mfhi", "d", AT); |
5931 | if (mips_trap) | |
5932 | macro_build ((char *) NULL, &icnt, NULL, "tne", "s,t", dreg, AT); | |
5933 | else | |
5934 | { | |
5935 | expr1.X_add_number = 8; | |
5936 | macro_build ((char *) NULL, &icnt, &expr1, "beq", "s,t,p", dreg, AT); | |
5937 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); | |
beae10d5 | 5938 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 6); |
252b5132 RH |
5939 | } |
5940 | --mips_opts.noreorder; | |
5941 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); | |
5942 | break; | |
5943 | ||
5944 | case M_DMULOU_I: | |
5945 | dbl = 1; | |
5946 | case M_MULOU_I: | |
5947 | imm = 1; | |
5948 | goto do_mulou; | |
5949 | ||
5950 | case M_DMULOU: | |
5951 | dbl = 1; | |
5952 | case M_MULOU: | |
5953 | do_mulou: | |
5954 | mips_emit_delays (true); | |
5955 | ++mips_opts.noreorder; | |
5956 | mips_any_noreorder = 1; | |
5957 | if (imm) | |
5958 | load_register (&icnt, AT, &imm_expr, dbl); | |
5959 | macro_build ((char *) NULL, &icnt, NULL, | |
5960 | dbl ? "dmultu" : "multu", | |
5961 | "s,t", sreg, imm ? AT : treg); | |
5962 | macro_build ((char *) NULL, &icnt, NULL, "mfhi", "d", AT); | |
5963 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); | |
5964 | if (mips_trap) | |
5965 | macro_build ((char *) NULL, &icnt, NULL, "tne", "s,t", AT, 0); | |
5966 | else | |
5967 | { | |
5968 | expr1.X_add_number = 8; | |
5969 | macro_build ((char *) NULL, &icnt, &expr1, "beq", "s,t,p", AT, 0); | |
5970 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); | |
beae10d5 | 5971 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 6); |
252b5132 RH |
5972 | } |
5973 | --mips_opts.noreorder; | |
5974 | break; | |
5975 | ||
5976 | case M_ROL: | |
5977 | macro_build ((char *) NULL, &icnt, NULL, "subu", "d,v,t", AT, 0, treg); | |
5978 | macro_build ((char *) NULL, &icnt, NULL, "srlv", "d,t,s", AT, sreg, AT); | |
5979 | macro_build ((char *) NULL, &icnt, NULL, "sllv", "d,t,s", dreg, sreg, | |
5980 | treg); | |
5981 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT); | |
5982 | break; | |
5983 | ||
5984 | case M_ROL_I: | |
5985 | if (imm_expr.X_op != O_constant) | |
5986 | as_bad (_("rotate count too large")); | |
5987 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", AT, sreg, | |
5988 | (int) (imm_expr.X_add_number & 0x1f)); | |
5989 | macro_build ((char *) NULL, &icnt, NULL, "srl", "d,w,<", dreg, sreg, | |
5990 | (int) ((0 - imm_expr.X_add_number) & 0x1f)); | |
5991 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT); | |
5992 | break; | |
5993 | ||
5994 | case M_ROR: | |
5995 | macro_build ((char *) NULL, &icnt, NULL, "subu", "d,v,t", AT, 0, treg); | |
5996 | macro_build ((char *) NULL, &icnt, NULL, "sllv", "d,t,s", AT, sreg, AT); | |
5997 | macro_build ((char *) NULL, &icnt, NULL, "srlv", "d,t,s", dreg, sreg, | |
5998 | treg); | |
5999 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT); | |
6000 | break; | |
6001 | ||
6002 | case M_ROR_I: | |
6003 | if (imm_expr.X_op != O_constant) | |
6004 | as_bad (_("rotate count too large")); | |
6005 | macro_build ((char *) NULL, &icnt, NULL, "srl", "d,w,<", AT, sreg, | |
6006 | (int) (imm_expr.X_add_number & 0x1f)); | |
6007 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", dreg, sreg, | |
6008 | (int) ((0 - imm_expr.X_add_number) & 0x1f)); | |
6009 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT); | |
6010 | break; | |
6011 | ||
6012 | case M_S_DOB: | |
ec68c924 | 6013 | if (mips_arch == CPU_R4650) |
252b5132 RH |
6014 | { |
6015 | as_bad (_("opcode not supported on this processor")); | |
6016 | return; | |
6017 | } | |
e7af610e | 6018 | assert (mips_opts.isa == ISA_MIPS1); |
252b5132 RH |
6019 | /* Even on a big endian machine $fn comes before $fn+1. We have |
6020 | to adjust when storing to memory. */ | |
6021 | macro_build ((char *) NULL, &icnt, &offset_expr, "swc1", "T,o(b)", | |
6022 | target_big_endian ? treg + 1 : treg, | |
6023 | (int) BFD_RELOC_LO16, breg); | |
6024 | offset_expr.X_add_number += 4; | |
6025 | macro_build ((char *) NULL, &icnt, &offset_expr, "swc1", "T,o(b)", | |
6026 | target_big_endian ? treg : treg + 1, | |
6027 | (int) BFD_RELOC_LO16, breg); | |
6028 | return; | |
6029 | ||
6030 | case M_SEQ: | |
6031 | if (sreg == 0) | |
6032 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, | |
6033 | treg, (int) BFD_RELOC_LO16); | |
6034 | else if (treg == 0) | |
6035 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, | |
6036 | sreg, (int) BFD_RELOC_LO16); | |
6037 | else | |
6038 | { | |
6039 | macro_build ((char *) NULL, &icnt, NULL, "xor", "d,v,t", dreg, | |
6040 | sreg, treg); | |
6041 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, | |
6042 | dreg, (int) BFD_RELOC_LO16); | |
6043 | } | |
6044 | return; | |
6045 | ||
6046 | case M_SEQ_I: | |
6047 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
6048 | { | |
6049 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, | |
6050 | sreg, (int) BFD_RELOC_LO16); | |
6051 | return; | |
6052 | } | |
6053 | if (sreg == 0) | |
6054 | { | |
6055 | as_warn (_("Instruction %s: result is always false"), | |
6056 | ip->insn_mo->name); | |
ea1fb5dc | 6057 | move_register (&icnt, dreg, 0); |
252b5132 RH |
6058 | return; |
6059 | } | |
6060 | if (imm_expr.X_op == O_constant | |
6061 | && imm_expr.X_add_number >= 0 | |
6062 | && imm_expr.X_add_number < 0x10000) | |
6063 | { | |
6064 | macro_build ((char *) NULL, &icnt, &imm_expr, "xori", "t,r,i", dreg, | |
6065 | sreg, (int) BFD_RELOC_LO16); | |
6066 | used_at = 0; | |
6067 | } | |
6068 | else if (imm_expr.X_op == O_constant | |
6069 | && imm_expr.X_add_number > -0x8000 | |
6070 | && imm_expr.X_add_number < 0) | |
6071 | { | |
6072 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
6073 | macro_build ((char *) NULL, &icnt, &imm_expr, | |
ca4e0257 | 6074 | HAVE_32BIT_GPRS ? "addiu" : "daddiu", |
252b5132 RH |
6075 | "t,r,j", dreg, sreg, |
6076 | (int) BFD_RELOC_LO16); | |
6077 | used_at = 0; | |
6078 | } | |
6079 | else | |
6080 | { | |
6081 | load_register (&icnt, AT, &imm_expr, 0); | |
6082 | macro_build ((char *) NULL, &icnt, NULL, "xor", "d,v,t", dreg, | |
6083 | sreg, AT); | |
6084 | used_at = 1; | |
6085 | } | |
6086 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, dreg, | |
6087 | (int) BFD_RELOC_LO16); | |
6088 | if (used_at) | |
6089 | break; | |
6090 | return; | |
6091 | ||
6092 | case M_SGE: /* sreg >= treg <==> not (sreg < treg) */ | |
6093 | s = "slt"; | |
6094 | goto sge; | |
6095 | case M_SGEU: | |
6096 | s = "sltu"; | |
6097 | sge: | |
6098 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, sreg, treg); | |
6099 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, | |
6100 | (int) BFD_RELOC_LO16); | |
6101 | return; | |
6102 | ||
6103 | case M_SGE_I: /* sreg >= I <==> not (sreg < I) */ | |
6104 | case M_SGEU_I: | |
6105 | if (imm_expr.X_op == O_constant | |
6106 | && imm_expr.X_add_number >= -0x8000 | |
6107 | && imm_expr.X_add_number < 0x8000) | |
6108 | { | |
6109 | macro_build ((char *) NULL, &icnt, &imm_expr, | |
6110 | mask == M_SGE_I ? "slti" : "sltiu", | |
6111 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); | |
6112 | used_at = 0; | |
6113 | } | |
6114 | else | |
6115 | { | |
6116 | load_register (&icnt, AT, &imm_expr, 0); | |
6117 | macro_build ((char *) NULL, &icnt, NULL, | |
6118 | mask == M_SGE_I ? "slt" : "sltu", | |
6119 | "d,v,t", dreg, sreg, AT); | |
6120 | used_at = 1; | |
6121 | } | |
6122 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, | |
6123 | (int) BFD_RELOC_LO16); | |
6124 | if (used_at) | |
6125 | break; | |
6126 | return; | |
6127 | ||
6128 | case M_SGT: /* sreg > treg <==> treg < sreg */ | |
6129 | s = "slt"; | |
6130 | goto sgt; | |
6131 | case M_SGTU: | |
6132 | s = "sltu"; | |
6133 | sgt: | |
6134 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, treg, sreg); | |
6135 | return; | |
6136 | ||
6137 | case M_SGT_I: /* sreg > I <==> I < sreg */ | |
6138 | s = "slt"; | |
6139 | goto sgti; | |
6140 | case M_SGTU_I: | |
6141 | s = "sltu"; | |
6142 | sgti: | |
6143 | load_register (&icnt, AT, &imm_expr, 0); | |
6144 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, AT, sreg); | |
6145 | break; | |
6146 | ||
6147 | case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */ | |
6148 | s = "slt"; | |
6149 | goto sle; | |
6150 | case M_SLEU: | |
6151 | s = "sltu"; | |
6152 | sle: | |
6153 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, treg, sreg); | |
6154 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, | |
6155 | (int) BFD_RELOC_LO16); | |
6156 | return; | |
6157 | ||
6158 | case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */ | |
6159 | s = "slt"; | |
6160 | goto slei; | |
6161 | case M_SLEU_I: | |
6162 | s = "sltu"; | |
6163 | slei: | |
6164 | load_register (&icnt, AT, &imm_expr, 0); | |
6165 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, AT, sreg); | |
6166 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, | |
6167 | (int) BFD_RELOC_LO16); | |
6168 | break; | |
6169 | ||
6170 | case M_SLT_I: | |
6171 | if (imm_expr.X_op == O_constant | |
6172 | && imm_expr.X_add_number >= -0x8000 | |
6173 | && imm_expr.X_add_number < 0x8000) | |
6174 | { | |
6175 | macro_build ((char *) NULL, &icnt, &imm_expr, "slti", "t,r,j", | |
6176 | dreg, sreg, (int) BFD_RELOC_LO16); | |
6177 | return; | |
6178 | } | |
6179 | load_register (&icnt, AT, &imm_expr, 0); | |
6180 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", dreg, sreg, AT); | |
6181 | break; | |
6182 | ||
6183 | case M_SLTU_I: | |
6184 | if (imm_expr.X_op == O_constant | |
6185 | && imm_expr.X_add_number >= -0x8000 | |
6186 | && imm_expr.X_add_number < 0x8000) | |
6187 | { | |
6188 | macro_build ((char *) NULL, &icnt, &imm_expr, "sltiu", "t,r,j", | |
6189 | dreg, sreg, (int) BFD_RELOC_LO16); | |
6190 | return; | |
6191 | } | |
6192 | load_register (&icnt, AT, &imm_expr, 0); | |
6193 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, sreg, | |
6194 | AT); | |
6195 | break; | |
6196 | ||
6197 | case M_SNE: | |
6198 | if (sreg == 0) | |
6199 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, | |
6200 | treg); | |
6201 | else if (treg == 0) | |
6202 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, | |
6203 | sreg); | |
6204 | else | |
6205 | { | |
6206 | macro_build ((char *) NULL, &icnt, NULL, "xor", "d,v,t", dreg, | |
6207 | sreg, treg); | |
6208 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, | |
6209 | dreg); | |
6210 | } | |
6211 | return; | |
6212 | ||
6213 | case M_SNE_I: | |
6214 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
6215 | { | |
6216 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, | |
6217 | sreg); | |
6218 | return; | |
6219 | } | |
6220 | if (sreg == 0) | |
6221 | { | |
6222 | as_warn (_("Instruction %s: result is always true"), | |
6223 | ip->insn_mo->name); | |
6224 | macro_build ((char *) NULL, &icnt, &expr1, | |
ca4e0257 | 6225 | HAVE_32BIT_GPRS ? "addiu" : "daddiu", |
252b5132 RH |
6226 | "t,r,j", dreg, 0, (int) BFD_RELOC_LO16); |
6227 | return; | |
6228 | } | |
6229 | if (imm_expr.X_op == O_constant | |
6230 | && imm_expr.X_add_number >= 0 | |
6231 | && imm_expr.X_add_number < 0x10000) | |
6232 | { | |
6233 | macro_build ((char *) NULL, &icnt, &imm_expr, "xori", "t,r,i", | |
6234 | dreg, sreg, (int) BFD_RELOC_LO16); | |
6235 | used_at = 0; | |
6236 | } | |
6237 | else if (imm_expr.X_op == O_constant | |
6238 | && imm_expr.X_add_number > -0x8000 | |
6239 | && imm_expr.X_add_number < 0) | |
6240 | { | |
6241 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
6242 | macro_build ((char *) NULL, &icnt, &imm_expr, | |
ca4e0257 | 6243 | HAVE_32BIT_GPRS ? "addiu" : "daddiu", |
252b5132 RH |
6244 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); |
6245 | used_at = 0; | |
6246 | } | |
6247 | else | |
6248 | { | |
6249 | load_register (&icnt, AT, &imm_expr, 0); | |
6250 | macro_build ((char *) NULL, &icnt, NULL, "xor", "d,v,t", dreg, | |
6251 | sreg, AT); | |
6252 | used_at = 1; | |
6253 | } | |
6254 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, dreg); | |
6255 | if (used_at) | |
6256 | break; | |
6257 | return; | |
6258 | ||
6259 | case M_DSUB_I: | |
6260 | dbl = 1; | |
6261 | case M_SUB_I: | |
6262 | if (imm_expr.X_op == O_constant | |
6263 | && imm_expr.X_add_number > -0x8000 | |
6264 | && imm_expr.X_add_number <= 0x8000) | |
6265 | { | |
6266 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
6267 | macro_build ((char *) NULL, &icnt, &imm_expr, | |
6268 | dbl ? "daddi" : "addi", | |
6269 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); | |
6270 | return; | |
6271 | } | |
6272 | load_register (&icnt, AT, &imm_expr, dbl); | |
6273 | macro_build ((char *) NULL, &icnt, NULL, | |
9a41af64 | 6274 | dbl ? "dsub" : "sub", "d,v,t", dreg, sreg, AT); |
252b5132 RH |
6275 | break; |
6276 | ||
6277 | case M_DSUBU_I: | |
6278 | dbl = 1; | |
6279 | case M_SUBU_I: | |
6280 | if (imm_expr.X_op == O_constant | |
6281 | && imm_expr.X_add_number > -0x8000 | |
6282 | && imm_expr.X_add_number <= 0x8000) | |
6283 | { | |
6284 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
6285 | macro_build ((char *) NULL, &icnt, &imm_expr, | |
6286 | dbl ? "daddiu" : "addiu", | |
6287 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); | |
6288 | return; | |
6289 | } | |
6290 | load_register (&icnt, AT, &imm_expr, dbl); | |
6291 | macro_build ((char *) NULL, &icnt, NULL, | |
9a41af64 | 6292 | dbl ? "dsubu" : "subu", "d,v,t", dreg, sreg, AT); |
252b5132 RH |
6293 | break; |
6294 | ||
6295 | case M_TEQ_I: | |
6296 | s = "teq"; | |
6297 | goto trap; | |
6298 | case M_TGE_I: | |
6299 | s = "tge"; | |
6300 | goto trap; | |
6301 | case M_TGEU_I: | |
6302 | s = "tgeu"; | |
6303 | goto trap; | |
6304 | case M_TLT_I: | |
6305 | s = "tlt"; | |
6306 | goto trap; | |
6307 | case M_TLTU_I: | |
6308 | s = "tltu"; | |
6309 | goto trap; | |
6310 | case M_TNE_I: | |
6311 | s = "tne"; | |
6312 | trap: | |
6313 | load_register (&icnt, AT, &imm_expr, 0); | |
6314 | macro_build ((char *) NULL, &icnt, NULL, s, "s,t", sreg, AT); | |
6315 | break; | |
6316 | ||
252b5132 | 6317 | case M_TRUNCWS: |
43841e91 | 6318 | case M_TRUNCWD: |
e7af610e | 6319 | assert (mips_opts.isa == ISA_MIPS1); |
252b5132 RH |
6320 | sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */ |
6321 | dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */ | |
6322 | ||
6323 | /* | |
6324 | * Is the double cfc1 instruction a bug in the mips assembler; | |
6325 | * or is there a reason for it? | |
6326 | */ | |
6327 | mips_emit_delays (true); | |
6328 | ++mips_opts.noreorder; | |
6329 | mips_any_noreorder = 1; | |
6330 | macro_build ((char *) NULL, &icnt, NULL, "cfc1", "t,G", treg, 31); | |
6331 | macro_build ((char *) NULL, &icnt, NULL, "cfc1", "t,G", treg, 31); | |
6332 | macro_build ((char *) NULL, &icnt, NULL, "nop", ""); | |
6333 | expr1.X_add_number = 3; | |
6334 | macro_build ((char *) NULL, &icnt, &expr1, "ori", "t,r,i", AT, treg, | |
6335 | (int) BFD_RELOC_LO16); | |
6336 | expr1.X_add_number = 2; | |
6337 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", AT, AT, | |
6338 | (int) BFD_RELOC_LO16); | |
6339 | macro_build ((char *) NULL, &icnt, NULL, "ctc1", "t,G", AT, 31); | |
6340 | macro_build ((char *) NULL, &icnt, NULL, "nop", ""); | |
6341 | macro_build ((char *) NULL, &icnt, NULL, | |
6342 | mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S", dreg, sreg); | |
6343 | macro_build ((char *) NULL, &icnt, NULL, "ctc1", "t,G", treg, 31); | |
6344 | macro_build ((char *) NULL, &icnt, NULL, "nop", ""); | |
6345 | --mips_opts.noreorder; | |
6346 | break; | |
6347 | ||
6348 | case M_ULH: | |
6349 | s = "lb"; | |
6350 | goto ulh; | |
6351 | case M_ULHU: | |
6352 | s = "lbu"; | |
6353 | ulh: | |
6354 | if (offset_expr.X_add_number >= 0x7fff) | |
6355 | as_bad (_("operand overflow")); | |
6356 | /* avoid load delay */ | |
6357 | if (! target_big_endian) | |
6358 | offset_expr.X_add_number += 1; | |
6359 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, | |
6360 | (int) BFD_RELOC_LO16, breg); | |
6361 | if (! target_big_endian) | |
6362 | offset_expr.X_add_number -= 1; | |
6363 | else | |
6364 | offset_expr.X_add_number += 1; | |
6365 | macro_build ((char *) NULL, &icnt, &offset_expr, "lbu", "t,o(b)", AT, | |
6366 | (int) BFD_RELOC_LO16, breg); | |
6367 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", treg, treg, 8); | |
6368 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", treg, treg, AT); | |
6369 | break; | |
6370 | ||
6371 | case M_ULD: | |
6372 | s = "ldl"; | |
6373 | s2 = "ldr"; | |
6374 | off = 7; | |
6375 | goto ulw; | |
6376 | case M_ULW: | |
6377 | s = "lwl"; | |
6378 | s2 = "lwr"; | |
6379 | off = 3; | |
6380 | ulw: | |
6381 | if (offset_expr.X_add_number >= 0x8000 - off) | |
6382 | as_bad (_("operand overflow")); | |
6383 | if (! target_big_endian) | |
6384 | offset_expr.X_add_number += off; | |
6385 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, | |
6386 | (int) BFD_RELOC_LO16, breg); | |
6387 | if (! target_big_endian) | |
6388 | offset_expr.X_add_number -= off; | |
6389 | else | |
6390 | offset_expr.X_add_number += off; | |
6391 | macro_build ((char *) NULL, &icnt, &offset_expr, s2, "t,o(b)", treg, | |
6392 | (int) BFD_RELOC_LO16, breg); | |
6393 | return; | |
6394 | ||
6395 | case M_ULD_A: | |
6396 | s = "ldl"; | |
6397 | s2 = "ldr"; | |
6398 | off = 7; | |
6399 | goto ulwa; | |
6400 | case M_ULW_A: | |
6401 | s = "lwl"; | |
6402 | s2 = "lwr"; | |
6403 | off = 3; | |
6404 | ulwa: | |
6405 | load_address (&icnt, AT, &offset_expr); | |
6406 | if (breg != 0) | |
6407 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 6408 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
6409 | "d,v,t", AT, AT, breg); |
6410 | if (! target_big_endian) | |
6411 | expr1.X_add_number = off; | |
6412 | else | |
6413 | expr1.X_add_number = 0; | |
6414 | macro_build ((char *) NULL, &icnt, &expr1, s, "t,o(b)", treg, | |
6415 | (int) BFD_RELOC_LO16, AT); | |
6416 | if (! target_big_endian) | |
6417 | expr1.X_add_number = 0; | |
6418 | else | |
6419 | expr1.X_add_number = off; | |
6420 | macro_build ((char *) NULL, &icnt, &expr1, s2, "t,o(b)", treg, | |
6421 | (int) BFD_RELOC_LO16, AT); | |
6422 | break; | |
6423 | ||
6424 | case M_ULH_A: | |
6425 | case M_ULHU_A: | |
6426 | load_address (&icnt, AT, &offset_expr); | |
6427 | if (breg != 0) | |
6428 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 6429 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
6430 | "d,v,t", AT, AT, breg); |
6431 | if (target_big_endian) | |
6432 | expr1.X_add_number = 0; | |
6433 | macro_build ((char *) NULL, &icnt, &expr1, | |
6434 | mask == M_ULH_A ? "lb" : "lbu", "t,o(b)", treg, | |
6435 | (int) BFD_RELOC_LO16, AT); | |
6436 | if (target_big_endian) | |
6437 | expr1.X_add_number = 1; | |
6438 | else | |
6439 | expr1.X_add_number = 0; | |
6440 | macro_build ((char *) NULL, &icnt, &expr1, "lbu", "t,o(b)", AT, | |
6441 | (int) BFD_RELOC_LO16, AT); | |
6442 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", treg, | |
6443 | treg, 8); | |
6444 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", treg, | |
6445 | treg, AT); | |
6446 | break; | |
6447 | ||
6448 | case M_USH: | |
6449 | if (offset_expr.X_add_number >= 0x7fff) | |
6450 | as_bad (_("operand overflow")); | |
6451 | if (target_big_endian) | |
6452 | offset_expr.X_add_number += 1; | |
6453 | macro_build ((char *) NULL, &icnt, &offset_expr, "sb", "t,o(b)", treg, | |
6454 | (int) BFD_RELOC_LO16, breg); | |
6455 | macro_build ((char *) NULL, &icnt, NULL, "srl", "d,w,<", AT, treg, 8); | |
6456 | if (target_big_endian) | |
6457 | offset_expr.X_add_number -= 1; | |
6458 | else | |
6459 | offset_expr.X_add_number += 1; | |
6460 | macro_build ((char *) NULL, &icnt, &offset_expr, "sb", "t,o(b)", AT, | |
6461 | (int) BFD_RELOC_LO16, breg); | |
6462 | break; | |
6463 | ||
6464 | case M_USD: | |
6465 | s = "sdl"; | |
6466 | s2 = "sdr"; | |
6467 | off = 7; | |
6468 | goto usw; | |
6469 | case M_USW: | |
6470 | s = "swl"; | |
6471 | s2 = "swr"; | |
6472 | off = 3; | |
6473 | usw: | |
6474 | if (offset_expr.X_add_number >= 0x8000 - off) | |
6475 | as_bad (_("operand overflow")); | |
6476 | if (! target_big_endian) | |
6477 | offset_expr.X_add_number += off; | |
6478 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, | |
6479 | (int) BFD_RELOC_LO16, breg); | |
6480 | if (! target_big_endian) | |
6481 | offset_expr.X_add_number -= off; | |
6482 | else | |
6483 | offset_expr.X_add_number += off; | |
6484 | macro_build ((char *) NULL, &icnt, &offset_expr, s2, "t,o(b)", treg, | |
6485 | (int) BFD_RELOC_LO16, breg); | |
6486 | return; | |
6487 | ||
6488 | case M_USD_A: | |
6489 | s = "sdl"; | |
6490 | s2 = "sdr"; | |
6491 | off = 7; | |
6492 | goto uswa; | |
6493 | case M_USW_A: | |
6494 | s = "swl"; | |
6495 | s2 = "swr"; | |
6496 | off = 3; | |
6497 | uswa: | |
6498 | load_address (&icnt, AT, &offset_expr); | |
6499 | if (breg != 0) | |
6500 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 6501 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
6502 | "d,v,t", AT, AT, breg); |
6503 | if (! target_big_endian) | |
6504 | expr1.X_add_number = off; | |
6505 | else | |
6506 | expr1.X_add_number = 0; | |
6507 | macro_build ((char *) NULL, &icnt, &expr1, s, "t,o(b)", treg, | |
6508 | (int) BFD_RELOC_LO16, AT); | |
6509 | if (! target_big_endian) | |
6510 | expr1.X_add_number = 0; | |
6511 | else | |
6512 | expr1.X_add_number = off; | |
6513 | macro_build ((char *) NULL, &icnt, &expr1, s2, "t,o(b)", treg, | |
6514 | (int) BFD_RELOC_LO16, AT); | |
6515 | break; | |
6516 | ||
6517 | case M_USH_A: | |
6518 | load_address (&icnt, AT, &offset_expr); | |
6519 | if (breg != 0) | |
6520 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 6521 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
6522 | "d,v,t", AT, AT, breg); |
6523 | if (! target_big_endian) | |
6524 | expr1.X_add_number = 0; | |
6525 | macro_build ((char *) NULL, &icnt, &expr1, "sb", "t,o(b)", treg, | |
6526 | (int) BFD_RELOC_LO16, AT); | |
6527 | macro_build ((char *) NULL, &icnt, NULL, "srl", "d,w,<", treg, | |
6528 | treg, 8); | |
6529 | if (! target_big_endian) | |
6530 | expr1.X_add_number = 1; | |
6531 | else | |
6532 | expr1.X_add_number = 0; | |
6533 | macro_build ((char *) NULL, &icnt, &expr1, "sb", "t,o(b)", treg, | |
6534 | (int) BFD_RELOC_LO16, AT); | |
6535 | if (! target_big_endian) | |
6536 | expr1.X_add_number = 0; | |
6537 | else | |
6538 | expr1.X_add_number = 1; | |
6539 | macro_build ((char *) NULL, &icnt, &expr1, "lbu", "t,o(b)", AT, | |
6540 | (int) BFD_RELOC_LO16, AT); | |
6541 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", treg, | |
6542 | treg, 8); | |
6543 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", treg, | |
6544 | treg, AT); | |
6545 | break; | |
6546 | ||
6547 | default: | |
6548 | /* FIXME: Check if this is one of the itbl macros, since they | |
bdaaa2e1 | 6549 | are added dynamically. */ |
252b5132 RH |
6550 | as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name); |
6551 | break; | |
6552 | } | |
6553 | if (mips_opts.noat) | |
6554 | as_warn (_("Macro used $at after \".set noat\"")); | |
6555 | } | |
6556 | ||
6557 | /* Implement macros in mips16 mode. */ | |
6558 | ||
6559 | static void | |
6560 | mips16_macro (ip) | |
6561 | struct mips_cl_insn *ip; | |
6562 | { | |
6563 | int mask; | |
6564 | int xreg, yreg, zreg, tmp; | |
6565 | int icnt; | |
6566 | expressionS expr1; | |
6567 | int dbl; | |
6568 | const char *s, *s2, *s3; | |
6569 | ||
6570 | mask = ip->insn_mo->mask; | |
6571 | ||
6572 | xreg = (ip->insn_opcode >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX; | |
6573 | yreg = (ip->insn_opcode >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY; | |
6574 | zreg = (ip->insn_opcode >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ; | |
6575 | ||
6576 | icnt = 0; | |
6577 | ||
6578 | expr1.X_op = O_constant; | |
6579 | expr1.X_op_symbol = NULL; | |
6580 | expr1.X_add_symbol = NULL; | |
6581 | expr1.X_add_number = 1; | |
6582 | ||
6583 | dbl = 0; | |
6584 | ||
6585 | switch (mask) | |
6586 | { | |
6587 | default: | |
6588 | internalError (); | |
6589 | ||
6590 | case M_DDIV_3: | |
6591 | dbl = 1; | |
6592 | case M_DIV_3: | |
6593 | s = "mflo"; | |
6594 | goto do_div3; | |
6595 | case M_DREM_3: | |
6596 | dbl = 1; | |
6597 | case M_REM_3: | |
6598 | s = "mfhi"; | |
6599 | do_div3: | |
6600 | mips_emit_delays (true); | |
6601 | ++mips_opts.noreorder; | |
6602 | mips_any_noreorder = 1; | |
6603 | macro_build ((char *) NULL, &icnt, NULL, | |
6604 | dbl ? "ddiv" : "div", | |
6605 | "0,x,y", xreg, yreg); | |
6606 | expr1.X_add_number = 2; | |
6607 | macro_build ((char *) NULL, &icnt, &expr1, "bnez", "x,p", yreg); | |
beae10d5 | 6608 | macro_build ((char *) NULL, &icnt, NULL, "break", "6", 7); |
bdaaa2e1 | 6609 | |
252b5132 RH |
6610 | /* FIXME: The normal code checks for of -1 / -0x80000000 here, |
6611 | since that causes an overflow. We should do that as well, | |
6612 | but I don't see how to do the comparisons without a temporary | |
6613 | register. */ | |
6614 | --mips_opts.noreorder; | |
6615 | macro_build ((char *) NULL, &icnt, NULL, s, "x", zreg); | |
6616 | break; | |
6617 | ||
6618 | case M_DIVU_3: | |
6619 | s = "divu"; | |
6620 | s2 = "mflo"; | |
6621 | goto do_divu3; | |
6622 | case M_REMU_3: | |
6623 | s = "divu"; | |
6624 | s2 = "mfhi"; | |
6625 | goto do_divu3; | |
6626 | case M_DDIVU_3: | |
6627 | s = "ddivu"; | |
6628 | s2 = "mflo"; | |
6629 | goto do_divu3; | |
6630 | case M_DREMU_3: | |
6631 | s = "ddivu"; | |
6632 | s2 = "mfhi"; | |
6633 | do_divu3: | |
6634 | mips_emit_delays (true); | |
6635 | ++mips_opts.noreorder; | |
6636 | mips_any_noreorder = 1; | |
6637 | macro_build ((char *) NULL, &icnt, NULL, s, "0,x,y", xreg, yreg); | |
6638 | expr1.X_add_number = 2; | |
6639 | macro_build ((char *) NULL, &icnt, &expr1, "bnez", "x,p", yreg); | |
6640 | macro_build ((char *) NULL, &icnt, NULL, "break", "6", 7); | |
6641 | --mips_opts.noreorder; | |
6642 | macro_build ((char *) NULL, &icnt, NULL, s2, "x", zreg); | |
6643 | break; | |
6644 | ||
6645 | case M_DMUL: | |
6646 | dbl = 1; | |
6647 | case M_MUL: | |
6648 | macro_build ((char *) NULL, &icnt, NULL, | |
9a41af64 | 6649 | dbl ? "dmultu" : "multu", "x,y", xreg, yreg); |
252b5132 RH |
6650 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "x", zreg); |
6651 | return; | |
6652 | ||
6653 | case M_DSUBU_I: | |
6654 | dbl = 1; | |
6655 | goto do_subu; | |
6656 | case M_SUBU_I: | |
6657 | do_subu: | |
6658 | if (imm_expr.X_op != O_constant) | |
6659 | as_bad (_("Unsupported large constant")); | |
6660 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
6661 | macro_build ((char *) NULL, &icnt, &imm_expr, | |
9a41af64 | 6662 | dbl ? "daddiu" : "addiu", "y,x,4", yreg, xreg); |
252b5132 RH |
6663 | break; |
6664 | ||
6665 | case M_SUBU_I_2: | |
6666 | if (imm_expr.X_op != O_constant) | |
6667 | as_bad (_("Unsupported large constant")); | |
6668 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
6669 | macro_build ((char *) NULL, &icnt, &imm_expr, "addiu", | |
6670 | "x,k", xreg); | |
6671 | break; | |
6672 | ||
6673 | case M_DSUBU_I_2: | |
6674 | if (imm_expr.X_op != O_constant) | |
6675 | as_bad (_("Unsupported large constant")); | |
6676 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
6677 | macro_build ((char *) NULL, &icnt, &imm_expr, "daddiu", | |
6678 | "y,j", yreg); | |
6679 | break; | |
6680 | ||
6681 | case M_BEQ: | |
6682 | s = "cmp"; | |
6683 | s2 = "bteqz"; | |
6684 | goto do_branch; | |
6685 | case M_BNE: | |
6686 | s = "cmp"; | |
6687 | s2 = "btnez"; | |
6688 | goto do_branch; | |
6689 | case M_BLT: | |
6690 | s = "slt"; | |
6691 | s2 = "btnez"; | |
6692 | goto do_branch; | |
6693 | case M_BLTU: | |
6694 | s = "sltu"; | |
6695 | s2 = "btnez"; | |
6696 | goto do_branch; | |
6697 | case M_BLE: | |
6698 | s = "slt"; | |
6699 | s2 = "bteqz"; | |
6700 | goto do_reverse_branch; | |
6701 | case M_BLEU: | |
6702 | s = "sltu"; | |
6703 | s2 = "bteqz"; | |
6704 | goto do_reverse_branch; | |
6705 | case M_BGE: | |
6706 | s = "slt"; | |
6707 | s2 = "bteqz"; | |
6708 | goto do_branch; | |
6709 | case M_BGEU: | |
6710 | s = "sltu"; | |
6711 | s2 = "bteqz"; | |
6712 | goto do_branch; | |
6713 | case M_BGT: | |
6714 | s = "slt"; | |
6715 | s2 = "btnez"; | |
6716 | goto do_reverse_branch; | |
6717 | case M_BGTU: | |
6718 | s = "sltu"; | |
6719 | s2 = "btnez"; | |
6720 | ||
6721 | do_reverse_branch: | |
6722 | tmp = xreg; | |
6723 | xreg = yreg; | |
6724 | yreg = tmp; | |
6725 | ||
6726 | do_branch: | |
6727 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "x,y", | |
6728 | xreg, yreg); | |
6729 | macro_build ((char *) NULL, &icnt, &offset_expr, s2, "p"); | |
6730 | break; | |
6731 | ||
6732 | case M_BEQ_I: | |
6733 | s = "cmpi"; | |
6734 | s2 = "bteqz"; | |
6735 | s3 = "x,U"; | |
6736 | goto do_branch_i; | |
6737 | case M_BNE_I: | |
6738 | s = "cmpi"; | |
6739 | s2 = "btnez"; | |
6740 | s3 = "x,U"; | |
6741 | goto do_branch_i; | |
6742 | case M_BLT_I: | |
6743 | s = "slti"; | |
6744 | s2 = "btnez"; | |
6745 | s3 = "x,8"; | |
6746 | goto do_branch_i; | |
6747 | case M_BLTU_I: | |
6748 | s = "sltiu"; | |
6749 | s2 = "btnez"; | |
6750 | s3 = "x,8"; | |
6751 | goto do_branch_i; | |
6752 | case M_BLE_I: | |
6753 | s = "slti"; | |
6754 | s2 = "btnez"; | |
6755 | s3 = "x,8"; | |
6756 | goto do_addone_branch_i; | |
6757 | case M_BLEU_I: | |
6758 | s = "sltiu"; | |
6759 | s2 = "btnez"; | |
6760 | s3 = "x,8"; | |
6761 | goto do_addone_branch_i; | |
6762 | case M_BGE_I: | |
6763 | s = "slti"; | |
6764 | s2 = "bteqz"; | |
6765 | s3 = "x,8"; | |
6766 | goto do_branch_i; | |
6767 | case M_BGEU_I: | |
6768 | s = "sltiu"; | |
6769 | s2 = "bteqz"; | |
6770 | s3 = "x,8"; | |
6771 | goto do_branch_i; | |
6772 | case M_BGT_I: | |
6773 | s = "slti"; | |
6774 | s2 = "bteqz"; | |
6775 | s3 = "x,8"; | |
6776 | goto do_addone_branch_i; | |
6777 | case M_BGTU_I: | |
6778 | s = "sltiu"; | |
6779 | s2 = "bteqz"; | |
6780 | s3 = "x,8"; | |
6781 | ||
6782 | do_addone_branch_i: | |
6783 | if (imm_expr.X_op != O_constant) | |
6784 | as_bad (_("Unsupported large constant")); | |
6785 | ++imm_expr.X_add_number; | |
6786 | ||
6787 | do_branch_i: | |
6788 | macro_build ((char *) NULL, &icnt, &imm_expr, s, s3, xreg); | |
6789 | macro_build ((char *) NULL, &icnt, &offset_expr, s2, "p"); | |
6790 | break; | |
6791 | ||
6792 | case M_ABS: | |
6793 | expr1.X_add_number = 0; | |
6794 | macro_build ((char *) NULL, &icnt, &expr1, "slti", "x,8", yreg); | |
6795 | if (xreg != yreg) | |
ea1fb5dc | 6796 | move_register (&icnt, xreg, yreg); |
252b5132 RH |
6797 | expr1.X_add_number = 2; |
6798 | macro_build ((char *) NULL, &icnt, &expr1, "bteqz", "p"); | |
6799 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
6800 | "neg", "x,w", xreg, xreg); | |
6801 | } | |
6802 | } | |
6803 | ||
6804 | /* For consistency checking, verify that all bits are specified either | |
6805 | by the match/mask part of the instruction definition, or by the | |
6806 | operand list. */ | |
6807 | static int | |
6808 | validate_mips_insn (opc) | |
6809 | const struct mips_opcode *opc; | |
6810 | { | |
6811 | const char *p = opc->args; | |
6812 | char c; | |
6813 | unsigned long used_bits = opc->mask; | |
6814 | ||
6815 | if ((used_bits & opc->match) != opc->match) | |
6816 | { | |
6817 | as_bad (_("internal: bad mips opcode (mask error): %s %s"), | |
6818 | opc->name, opc->args); | |
6819 | return 0; | |
6820 | } | |
6821 | #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift))) | |
6822 | while (*p) | |
6823 | switch (c = *p++) | |
6824 | { | |
6825 | case ',': break; | |
6826 | case '(': break; | |
6827 | case ')': break; | |
6828 | case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; | |
6829 | case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; | |
6830 | case 'A': break; | |
4372b673 | 6831 | case 'B': USE_BITS (OP_MASK_CODE20, OP_SH_CODE20); break; |
252b5132 RH |
6832 | case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break; |
6833 | case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break; | |
6834 | case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
6835 | case 'F': break; | |
6836 | case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
156c2f8b | 6837 | case 'H': USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; |
252b5132 | 6838 | case 'I': break; |
e972090a | 6839 | case 'J': USE_BITS (OP_MASK_CODE19, OP_SH_CODE19); break; |
252b5132 RH |
6840 | case 'L': break; |
6841 | case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break; | |
6842 | case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break; | |
6843 | case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break; | |
6844 | case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
6845 | case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
6846 | case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
6847 | case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
6848 | case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break; | |
6849 | case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
6850 | case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break; | |
6851 | case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
6852 | case 'f': break; | |
6853 | case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break; | |
6854 | case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; | |
6855 | case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
6856 | case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break; | |
6857 | case 'l': break; | |
6858 | case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
6859 | case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
6860 | case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break; | |
6861 | case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
6862 | case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
6863 | case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
6864 | case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; | |
6865 | case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
6866 | case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
6867 | case 'x': break; | |
6868 | case 'z': break; | |
6869 | case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break; | |
4372b673 NC |
6870 | case 'U': USE_BITS (OP_MASK_RD, OP_SH_RD); |
6871 | USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
252b5132 RH |
6872 | default: |
6873 | as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"), | |
6874 | c, opc->name, opc->args); | |
6875 | return 0; | |
6876 | } | |
6877 | #undef USE_BITS | |
6878 | if (used_bits != 0xffffffff) | |
6879 | { | |
6880 | as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"), | |
6881 | ~used_bits & 0xffffffff, opc->name, opc->args); | |
6882 | return 0; | |
6883 | } | |
6884 | return 1; | |
6885 | } | |
6886 | ||
6887 | /* This routine assembles an instruction into its binary format. As a | |
6888 | side effect, it sets one of the global variables imm_reloc or | |
6889 | offset_reloc to the type of relocation to do if one of the operands | |
6890 | is an address expression. */ | |
6891 | ||
6892 | static void | |
6893 | mips_ip (str, ip) | |
6894 | char *str; | |
6895 | struct mips_cl_insn *ip; | |
6896 | { | |
6897 | char *s; | |
6898 | const char *args; | |
43841e91 | 6899 | char c = 0; |
252b5132 RH |
6900 | struct mips_opcode *insn; |
6901 | char *argsStart; | |
6902 | unsigned int regno; | |
6903 | unsigned int lastregno = 0; | |
6904 | char *s_reset; | |
6905 | char save_c = 0; | |
6906 | int full_opcode_match = 1; | |
6907 | ||
6908 | insn_error = NULL; | |
6909 | ||
6910 | /* If the instruction contains a '.', we first try to match an instruction | |
6911 | including the '.'. Then we try again without the '.'. */ | |
6912 | insn = NULL; | |
d9a62219 | 6913 | for (s = str; *s != '\0' && !isspace ((unsigned char) *s); ++s) |
252b5132 RH |
6914 | continue; |
6915 | ||
6916 | /* If we stopped on whitespace, then replace the whitespace with null for | |
6917 | the call to hash_find. Save the character we replaced just in case we | |
6918 | have to re-parse the instruction. */ | |
d9a62219 | 6919 | if (isspace ((unsigned char) *s)) |
252b5132 RH |
6920 | { |
6921 | save_c = *s; | |
6922 | *s++ = '\0'; | |
6923 | } | |
bdaaa2e1 | 6924 | |
252b5132 RH |
6925 | insn = (struct mips_opcode *) hash_find (op_hash, str); |
6926 | ||
6927 | /* If we didn't find the instruction in the opcode table, try again, but | |
6928 | this time with just the instruction up to, but not including the | |
6929 | first '.'. */ | |
6930 | if (insn == NULL) | |
6931 | { | |
bdaaa2e1 | 6932 | /* Restore the character we overwrite above (if any). */ |
252b5132 RH |
6933 | if (save_c) |
6934 | *(--s) = save_c; | |
6935 | ||
6936 | /* Scan up to the first '.' or whitespace. */ | |
d9a62219 | 6937 | for (s = str; *s != '\0' && *s != '.' && !isspace ((unsigned char) *s); ++s) |
252b5132 RH |
6938 | continue; |
6939 | ||
6940 | /* If we did not find a '.', then we can quit now. */ | |
6941 | if (*s != '.') | |
6942 | { | |
6943 | insn_error = "unrecognized opcode"; | |
6944 | return; | |
6945 | } | |
6946 | ||
6947 | /* Lookup the instruction in the hash table. */ | |
6948 | *s++ = '\0'; | |
6949 | if ((insn = (struct mips_opcode *) hash_find (op_hash, str)) == NULL) | |
6950 | { | |
6951 | insn_error = "unrecognized opcode"; | |
6952 | return; | |
6953 | } | |
6954 | ||
6955 | full_opcode_match = 0; | |
6956 | } | |
6957 | ||
6958 | argsStart = s; | |
6959 | for (;;) | |
6960 | { | |
252b5132 RH |
6961 | boolean ok; |
6962 | ||
6963 | assert (strcmp (insn->name, str) == 0); | |
6964 | ||
ea1fb5dc | 6965 | if (OPCODE_IS_MEMBER (insn, mips_opts.isa, mips_arch)) |
252b5132 | 6966 | ok = true; |
bdaaa2e1 | 6967 | else |
252b5132 | 6968 | ok = false; |
bdaaa2e1 | 6969 | |
252b5132 RH |
6970 | if (insn->pinfo != INSN_MACRO) |
6971 | { | |
ec68c924 | 6972 | if (mips_arch == CPU_R4650 && (insn->pinfo & FP_D) != 0) |
252b5132 RH |
6973 | ok = false; |
6974 | } | |
6975 | ||
6976 | if (! ok) | |
6977 | { | |
6978 | if (insn + 1 < &mips_opcodes[NUMOPCODES] | |
6979 | && strcmp (insn->name, insn[1].name) == 0) | |
6980 | { | |
6981 | ++insn; | |
6982 | continue; | |
6983 | } | |
252b5132 | 6984 | else |
beae10d5 | 6985 | { |
268f6bed L |
6986 | if (!insn_error) |
6987 | { | |
6988 | static char buf[100]; | |
6989 | sprintf (buf, | |
6990 | _("opcode not supported on this processor: %s (%s)"), | |
ec68c924 | 6991 | mips_cpu_to_str (mips_arch), |
268f6bed | 6992 | mips_isa_to_str (mips_opts.isa)); |
bdaaa2e1 | 6993 | |
268f6bed L |
6994 | insn_error = buf; |
6995 | } | |
6996 | if (save_c) | |
6997 | *(--s) = save_c; | |
2bd7f1f3 | 6998 | return; |
252b5132 | 6999 | } |
252b5132 RH |
7000 | } |
7001 | ||
7002 | ip->insn_mo = insn; | |
7003 | ip->insn_opcode = insn->match; | |
268f6bed | 7004 | insn_error = NULL; |
252b5132 RH |
7005 | for (args = insn->args;; ++args) |
7006 | { | |
7007 | if (*s == ' ') | |
7008 | ++s; | |
7009 | switch (*args) | |
7010 | { | |
7011 | case '\0': /* end of args */ | |
7012 | if (*s == '\0') | |
7013 | return; | |
7014 | break; | |
7015 | ||
7016 | case ',': | |
7017 | if (*s++ == *args) | |
7018 | continue; | |
7019 | s--; | |
7020 | switch (*++args) | |
7021 | { | |
7022 | case 'r': | |
7023 | case 'v': | |
38487616 | 7024 | ip->insn_opcode |= lastregno << OP_SH_RS; |
252b5132 RH |
7025 | continue; |
7026 | ||
7027 | case 'w': | |
38487616 TS |
7028 | ip->insn_opcode |= lastregno << OP_SH_RT; |
7029 | continue; | |
7030 | ||
252b5132 | 7031 | case 'W': |
38487616 | 7032 | ip->insn_opcode |= lastregno << OP_SH_FT; |
252b5132 RH |
7033 | continue; |
7034 | ||
7035 | case 'V': | |
38487616 | 7036 | ip->insn_opcode |= lastregno << OP_SH_FS; |
252b5132 RH |
7037 | continue; |
7038 | } | |
7039 | break; | |
7040 | ||
7041 | case '(': | |
7042 | /* Handle optional base register. | |
7043 | Either the base register is omitted or | |
bdaaa2e1 | 7044 | we must have a left paren. */ |
252b5132 RH |
7045 | /* This is dependent on the next operand specifier |
7046 | is a base register specification. */ | |
7047 | assert (args[1] == 'b' || args[1] == '5' | |
7048 | || args[1] == '-' || args[1] == '4'); | |
7049 | if (*s == '\0') | |
7050 | return; | |
7051 | ||
7052 | case ')': /* these must match exactly */ | |
7053 | if (*s++ == *args) | |
7054 | continue; | |
7055 | break; | |
7056 | ||
7057 | case '<': /* must be at least one digit */ | |
7058 | /* | |
7059 | * According to the manual, if the shift amount is greater | |
7060 | * than 31 or less than 0 the the shift amount should be | |
7061 | * mod 32. In reality the mips assembler issues an error. | |
7062 | * We issue a warning and mask out all but the low 5 bits. | |
7063 | */ | |
7064 | my_getExpression (&imm_expr, s); | |
7065 | check_absolute_expr (ip, &imm_expr); | |
7066 | if ((unsigned long) imm_expr.X_add_number > 31) | |
7067 | { | |
7068 | as_warn (_("Improper shift amount (%ld)"), | |
7069 | (long) imm_expr.X_add_number); | |
38487616 | 7070 | imm_expr.X_add_number &= OP_MASK_SHAMT; |
252b5132 | 7071 | } |
38487616 | 7072 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_SHAMT; |
252b5132 RH |
7073 | imm_expr.X_op = O_absent; |
7074 | s = expr_end; | |
7075 | continue; | |
7076 | ||
7077 | case '>': /* shift amount minus 32 */ | |
7078 | my_getExpression (&imm_expr, s); | |
7079 | check_absolute_expr (ip, &imm_expr); | |
7080 | if ((unsigned long) imm_expr.X_add_number < 32 | |
7081 | || (unsigned long) imm_expr.X_add_number > 63) | |
7082 | break; | |
38487616 | 7083 | ip->insn_opcode |= (imm_expr.X_add_number - 32) << OP_SH_SHAMT; |
252b5132 RH |
7084 | imm_expr.X_op = O_absent; |
7085 | s = expr_end; | |
7086 | continue; | |
7087 | ||
252b5132 RH |
7088 | case 'k': /* cache code */ |
7089 | case 'h': /* prefx code */ | |
7090 | my_getExpression (&imm_expr, s); | |
7091 | check_absolute_expr (ip, &imm_expr); | |
7092 | if ((unsigned long) imm_expr.X_add_number > 31) | |
7093 | { | |
7094 | as_warn (_("Invalid value for `%s' (%lu)"), | |
7095 | ip->insn_mo->name, | |
7096 | (unsigned long) imm_expr.X_add_number); | |
7097 | imm_expr.X_add_number &= 0x1f; | |
7098 | } | |
7099 | if (*args == 'k') | |
7100 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CACHE; | |
7101 | else | |
7102 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_PREFX; | |
7103 | imm_expr.X_op = O_absent; | |
7104 | s = expr_end; | |
7105 | continue; | |
7106 | ||
7107 | case 'c': /* break code */ | |
7108 | my_getExpression (&imm_expr, s); | |
7109 | check_absolute_expr (ip, &imm_expr); | |
7110 | if ((unsigned) imm_expr.X_add_number > 1023) | |
7111 | { | |
7112 | as_warn (_("Illegal break code (%ld)"), | |
7113 | (long) imm_expr.X_add_number); | |
38487616 | 7114 | imm_expr.X_add_number &= OP_MASK_CODE; |
252b5132 | 7115 | } |
38487616 | 7116 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE; |
252b5132 RH |
7117 | imm_expr.X_op = O_absent; |
7118 | s = expr_end; | |
7119 | continue; | |
7120 | ||
7121 | case 'q': /* lower break code */ | |
7122 | my_getExpression (&imm_expr, s); | |
7123 | check_absolute_expr (ip, &imm_expr); | |
7124 | if ((unsigned) imm_expr.X_add_number > 1023) | |
7125 | { | |
7126 | as_warn (_("Illegal lower break code (%ld)"), | |
7127 | (long) imm_expr.X_add_number); | |
38487616 | 7128 | imm_expr.X_add_number &= OP_MASK_CODE2; |
252b5132 | 7129 | } |
38487616 | 7130 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE2; |
252b5132 RH |
7131 | imm_expr.X_op = O_absent; |
7132 | s = expr_end; | |
7133 | continue; | |
7134 | ||
4372b673 | 7135 | case 'B': /* 20-bit syscall/break code. */ |
156c2f8b | 7136 | my_getExpression (&imm_expr, s); |
156c2f8b | 7137 | check_absolute_expr (ip, &imm_expr); |
38487616 | 7138 | if ((unsigned) imm_expr.X_add_number > OP_MASK_CODE20) |
4372b673 | 7139 | as_warn (_("Illegal 20-bit code (%ld)"), |
252b5132 | 7140 | (long) imm_expr.X_add_number); |
38487616 | 7141 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE20; |
252b5132 RH |
7142 | imm_expr.X_op = O_absent; |
7143 | s = expr_end; | |
7144 | continue; | |
7145 | ||
7146 | case 'C': /* Coprocessor code */ | |
beae10d5 | 7147 | my_getExpression (&imm_expr, s); |
252b5132 | 7148 | check_absolute_expr (ip, &imm_expr); |
beae10d5 | 7149 | if ((unsigned long) imm_expr.X_add_number >= (1<<25)) |
252b5132 | 7150 | { |
beae10d5 | 7151 | as_warn (_("Coproccesor code > 25 bits (%ld)"), |
252b5132 | 7152 | (long) imm_expr.X_add_number); |
beae10d5 | 7153 | imm_expr.X_add_number &= ((1<<25) - 1); |
252b5132 | 7154 | } |
beae10d5 KH |
7155 | ip->insn_opcode |= imm_expr.X_add_number; |
7156 | imm_expr.X_op = O_absent; | |
7157 | s = expr_end; | |
7158 | continue; | |
252b5132 | 7159 | |
4372b673 NC |
7160 | case 'J': /* 19-bit wait code. */ |
7161 | my_getExpression (&imm_expr, s); | |
7162 | check_absolute_expr (ip, &imm_expr); | |
38487616 | 7163 | if ((unsigned) imm_expr.X_add_number > OP_MASK_CODE19) |
4372b673 NC |
7164 | as_warn (_("Illegal 19-bit code (%ld)"), |
7165 | (long) imm_expr.X_add_number); | |
38487616 | 7166 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE19; |
4372b673 NC |
7167 | imm_expr.X_op = O_absent; |
7168 | s = expr_end; | |
7169 | continue; | |
7170 | ||
252b5132 | 7171 | case 'P': /* Performance register */ |
beae10d5 | 7172 | my_getExpression (&imm_expr, s); |
252b5132 | 7173 | check_absolute_expr (ip, &imm_expr); |
beae10d5 | 7174 | if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1) |
252b5132 | 7175 | { |
38487616 | 7176 | as_warn (_("Invalid performance register (%ld)"), |
252b5132 | 7177 | (long) imm_expr.X_add_number); |
38487616 | 7178 | imm_expr.X_add_number &= OP_MASK_PERFREG; |
252b5132 | 7179 | } |
38487616 | 7180 | ip->insn_opcode |= (imm_expr.X_add_number << OP_SH_PERFREG); |
beae10d5 KH |
7181 | imm_expr.X_op = O_absent; |
7182 | s = expr_end; | |
7183 | continue; | |
252b5132 RH |
7184 | |
7185 | case 'b': /* base register */ | |
7186 | case 'd': /* destination register */ | |
7187 | case 's': /* source register */ | |
7188 | case 't': /* target register */ | |
7189 | case 'r': /* both target and source */ | |
7190 | case 'v': /* both dest and source */ | |
7191 | case 'w': /* both dest and target */ | |
7192 | case 'E': /* coprocessor target register */ | |
7193 | case 'G': /* coprocessor destination register */ | |
7194 | case 'x': /* ignore register name */ | |
7195 | case 'z': /* must be zero register */ | |
4372b673 | 7196 | case 'U': /* destination register (clo/clz). */ |
252b5132 RH |
7197 | s_reset = s; |
7198 | if (s[0] == '$') | |
7199 | { | |
7200 | ||
d9a62219 | 7201 | if (isdigit ((unsigned char) s[1])) |
252b5132 RH |
7202 | { |
7203 | ++s; | |
7204 | regno = 0; | |
7205 | do | |
7206 | { | |
7207 | regno *= 10; | |
7208 | regno += *s - '0'; | |
7209 | ++s; | |
7210 | } | |
d9a62219 | 7211 | while (isdigit ((unsigned char) *s)); |
252b5132 RH |
7212 | if (regno > 31) |
7213 | as_bad (_("Invalid register number (%d)"), regno); | |
7214 | } | |
7215 | else if (*args == 'E' || *args == 'G') | |
7216 | goto notreg; | |
7217 | else | |
7218 | { | |
7219 | if (s[1] == 'f' && s[2] == 'p') | |
7220 | { | |
7221 | s += 3; | |
7222 | regno = FP; | |
7223 | } | |
7224 | else if (s[1] == 's' && s[2] == 'p') | |
7225 | { | |
7226 | s += 3; | |
7227 | regno = SP; | |
7228 | } | |
7229 | else if (s[1] == 'g' && s[2] == 'p') | |
7230 | { | |
7231 | s += 3; | |
7232 | regno = GP; | |
7233 | } | |
7234 | else if (s[1] == 'a' && s[2] == 't') | |
7235 | { | |
7236 | s += 3; | |
7237 | regno = AT; | |
7238 | } | |
7239 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '0') | |
7240 | { | |
7241 | s += 4; | |
7242 | regno = KT0; | |
7243 | } | |
7244 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '1') | |
7245 | { | |
7246 | s += 4; | |
7247 | regno = KT1; | |
7248 | } | |
7249 | else if (itbl_have_entries) | |
7250 | { | |
7251 | char *p, *n; | |
d7ba4a77 | 7252 | unsigned long r; |
252b5132 | 7253 | |
d7ba4a77 | 7254 | p = s + 1; /* advance past '$' */ |
252b5132 RH |
7255 | n = itbl_get_field (&p); /* n is name */ |
7256 | ||
d7ba4a77 ILT |
7257 | /* See if this is a register defined in an |
7258 | itbl entry. */ | |
7259 | if (itbl_get_reg_val (n, &r)) | |
252b5132 RH |
7260 | { |
7261 | /* Get_field advances to the start of | |
7262 | the next field, so we need to back | |
d7ba4a77 | 7263 | rack to the end of the last field. */ |
bdaaa2e1 | 7264 | if (p) |
252b5132 | 7265 | s = p - 1; |
bdaaa2e1 | 7266 | else |
d7ba4a77 | 7267 | s = strchr (s, '\0'); |
252b5132 RH |
7268 | regno = r; |
7269 | } | |
7270 | else | |
7271 | goto notreg; | |
beae10d5 | 7272 | } |
252b5132 RH |
7273 | else |
7274 | goto notreg; | |
7275 | } | |
7276 | if (regno == AT | |
7277 | && ! mips_opts.noat | |
7278 | && *args != 'E' | |
7279 | && *args != 'G') | |
7280 | as_warn (_("Used $at without \".set noat\"")); | |
7281 | c = *args; | |
7282 | if (*s == ' ') | |
7283 | s++; | |
7284 | if (args[1] != *s) | |
7285 | { | |
7286 | if (c == 'r' || c == 'v' || c == 'w') | |
7287 | { | |
7288 | regno = lastregno; | |
7289 | s = s_reset; | |
7290 | args++; | |
7291 | } | |
7292 | } | |
7293 | /* 'z' only matches $0. */ | |
7294 | if (c == 'z' && regno != 0) | |
7295 | break; | |
7296 | ||
bdaaa2e1 KH |
7297 | /* Now that we have assembled one operand, we use the args string |
7298 | * to figure out where it goes in the instruction. */ | |
252b5132 RH |
7299 | switch (c) |
7300 | { | |
7301 | case 'r': | |
7302 | case 's': | |
7303 | case 'v': | |
7304 | case 'b': | |
38487616 | 7305 | ip->insn_opcode |= regno << OP_SH_RS; |
252b5132 RH |
7306 | break; |
7307 | case 'd': | |
7308 | case 'G': | |
38487616 | 7309 | ip->insn_opcode |= regno << OP_SH_RD; |
252b5132 | 7310 | break; |
4372b673 | 7311 | case 'U': |
38487616 TS |
7312 | ip->insn_opcode |= regno << OP_SH_RD; |
7313 | ip->insn_opcode |= regno << OP_SH_RT; | |
4372b673 | 7314 | break; |
252b5132 RH |
7315 | case 'w': |
7316 | case 't': | |
7317 | case 'E': | |
38487616 | 7318 | ip->insn_opcode |= regno << OP_SH_RT; |
252b5132 RH |
7319 | break; |
7320 | case 'x': | |
7321 | /* This case exists because on the r3000 trunc | |
7322 | expands into a macro which requires a gp | |
7323 | register. On the r6000 or r4000 it is | |
7324 | assembled into a single instruction which | |
7325 | ignores the register. Thus the insn version | |
7326 | is MIPS_ISA2 and uses 'x', and the macro | |
7327 | version is MIPS_ISA1 and uses 't'. */ | |
7328 | break; | |
7329 | case 'z': | |
7330 | /* This case is for the div instruction, which | |
7331 | acts differently if the destination argument | |
7332 | is $0. This only matches $0, and is checked | |
7333 | outside the switch. */ | |
7334 | break; | |
7335 | case 'D': | |
7336 | /* Itbl operand; not yet implemented. FIXME ?? */ | |
7337 | break; | |
7338 | /* What about all other operands like 'i', which | |
7339 | can be specified in the opcode table? */ | |
7340 | } | |
7341 | lastregno = regno; | |
7342 | continue; | |
7343 | } | |
7344 | notreg: | |
7345 | switch (*args++) | |
7346 | { | |
7347 | case 'r': | |
7348 | case 'v': | |
38487616 | 7349 | ip->insn_opcode |= lastregno << OP_SH_RS; |
252b5132 RH |
7350 | continue; |
7351 | case 'w': | |
38487616 | 7352 | ip->insn_opcode |= lastregno << OP_SH_RT; |
252b5132 RH |
7353 | continue; |
7354 | } | |
7355 | break; | |
7356 | ||
7357 | case 'D': /* floating point destination register */ | |
7358 | case 'S': /* floating point source register */ | |
7359 | case 'T': /* floating point target register */ | |
7360 | case 'R': /* floating point source register */ | |
7361 | case 'V': | |
7362 | case 'W': | |
7363 | s_reset = s; | |
d9a62219 | 7364 | if (s[0] == '$' && s[1] == 'f' && isdigit ((unsigned char) s[2])) |
252b5132 RH |
7365 | { |
7366 | s += 2; | |
7367 | regno = 0; | |
7368 | do | |
7369 | { | |
7370 | regno *= 10; | |
7371 | regno += *s - '0'; | |
7372 | ++s; | |
7373 | } | |
d9a62219 | 7374 | while (isdigit ((unsigned char) *s)); |
252b5132 RH |
7375 | |
7376 | if (regno > 31) | |
7377 | as_bad (_("Invalid float register number (%d)"), regno); | |
7378 | ||
7379 | if ((regno & 1) != 0 | |
ca4e0257 | 7380 | && HAVE_32BIT_FPRS |
252b5132 RH |
7381 | && ! (strcmp (str, "mtc1") == 0 |
7382 | || strcmp (str, "mfc1") == 0 | |
7383 | || strcmp (str, "lwc1") == 0 | |
7384 | || strcmp (str, "swc1") == 0 | |
7385 | || strcmp (str, "l.s") == 0 | |
7386 | || strcmp (str, "s.s") == 0)) | |
7387 | as_warn (_("Float register should be even, was %d"), | |
7388 | regno); | |
7389 | ||
7390 | c = *args; | |
7391 | if (*s == ' ') | |
7392 | s++; | |
7393 | if (args[1] != *s) | |
7394 | { | |
7395 | if (c == 'V' || c == 'W') | |
7396 | { | |
7397 | regno = lastregno; | |
7398 | s = s_reset; | |
7399 | args++; | |
7400 | } | |
7401 | } | |
7402 | switch (c) | |
7403 | { | |
7404 | case 'D': | |
38487616 | 7405 | ip->insn_opcode |= regno << OP_SH_FD; |
252b5132 RH |
7406 | break; |
7407 | case 'V': | |
7408 | case 'S': | |
38487616 | 7409 | ip->insn_opcode |= regno << OP_SH_FS; |
252b5132 RH |
7410 | break; |
7411 | case 'W': | |
7412 | case 'T': | |
38487616 | 7413 | ip->insn_opcode |= regno << OP_SH_FT; |
252b5132 RH |
7414 | break; |
7415 | case 'R': | |
38487616 | 7416 | ip->insn_opcode |= regno << OP_SH_FR; |
252b5132 RH |
7417 | break; |
7418 | } | |
7419 | lastregno = regno; | |
7420 | continue; | |
7421 | } | |
7422 | ||
252b5132 RH |
7423 | switch (*args++) |
7424 | { | |
7425 | case 'V': | |
38487616 | 7426 | ip->insn_opcode |= lastregno << OP_SH_FS; |
252b5132 RH |
7427 | continue; |
7428 | case 'W': | |
38487616 | 7429 | ip->insn_opcode |= lastregno << OP_SH_FT; |
252b5132 RH |
7430 | continue; |
7431 | } | |
7432 | break; | |
7433 | ||
7434 | case 'I': | |
7435 | my_getExpression (&imm_expr, s); | |
7436 | if (imm_expr.X_op != O_big | |
7437 | && imm_expr.X_op != O_constant) | |
7438 | insn_error = _("absolute expression required"); | |
7439 | s = expr_end; | |
7440 | continue; | |
7441 | ||
7442 | case 'A': | |
7443 | my_getExpression (&offset_expr, s); | |
7444 | imm_reloc = BFD_RELOC_32; | |
7445 | s = expr_end; | |
7446 | continue; | |
7447 | ||
7448 | case 'F': | |
7449 | case 'L': | |
7450 | case 'f': | |
7451 | case 'l': | |
7452 | { | |
7453 | int f64; | |
ca4e0257 | 7454 | int using_gprs; |
252b5132 RH |
7455 | char *save_in; |
7456 | char *err; | |
7457 | unsigned char temp[8]; | |
7458 | int len; | |
7459 | unsigned int length; | |
7460 | segT seg; | |
7461 | subsegT subseg; | |
7462 | char *p; | |
7463 | ||
7464 | /* These only appear as the last operand in an | |
7465 | instruction, and every instruction that accepts | |
7466 | them in any variant accepts them in all variants. | |
7467 | This means we don't have to worry about backing out | |
7468 | any changes if the instruction does not match. | |
7469 | ||
7470 | The difference between them is the size of the | |
7471 | floating point constant and where it goes. For 'F' | |
7472 | and 'L' the constant is 64 bits; for 'f' and 'l' it | |
7473 | is 32 bits. Where the constant is placed is based | |
7474 | on how the MIPS assembler does things: | |
7475 | F -- .rdata | |
7476 | L -- .lit8 | |
7477 | f -- immediate value | |
7478 | l -- .lit4 | |
7479 | ||
7480 | The .lit4 and .lit8 sections are only used if | |
7481 | permitted by the -G argument. | |
7482 | ||
7483 | When generating embedded PIC code, we use the | |
7484 | .lit8 section but not the .lit4 section (we can do | |
7485 | .lit4 inline easily; we need to put .lit8 | |
7486 | somewhere in the data segment, and using .lit8 | |
7487 | permits the linker to eventually combine identical | |
ca4e0257 RS |
7488 | .lit8 entries). |
7489 | ||
7490 | The code below needs to know whether the target register | |
7491 | is 32 or 64 bits wide. It relies on the fact 'f' and | |
7492 | 'F' are used with GPR-based instructions and 'l' and | |
7493 | 'L' are used with FPR-based instructions. */ | |
252b5132 RH |
7494 | |
7495 | f64 = *args == 'F' || *args == 'L'; | |
ca4e0257 | 7496 | using_gprs = *args == 'F' || *args == 'f'; |
252b5132 RH |
7497 | |
7498 | save_in = input_line_pointer; | |
7499 | input_line_pointer = s; | |
7500 | err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len); | |
7501 | length = len; | |
7502 | s = input_line_pointer; | |
7503 | input_line_pointer = save_in; | |
7504 | if (err != NULL && *err != '\0') | |
7505 | { | |
7506 | as_bad (_("Bad floating point constant: %s"), err); | |
7507 | memset (temp, '\0', sizeof temp); | |
7508 | length = f64 ? 8 : 4; | |
7509 | } | |
7510 | ||
156c2f8b | 7511 | assert (length == (unsigned) (f64 ? 8 : 4)); |
252b5132 RH |
7512 | |
7513 | if (*args == 'f' | |
7514 | || (*args == 'l' | |
7515 | && (! USE_GLOBAL_POINTER_OPT | |
7516 | || mips_pic == EMBEDDED_PIC | |
7517 | || g_switch_value < 4 | |
7518 | || (temp[0] == 0 && temp[1] == 0) | |
7519 | || (temp[2] == 0 && temp[3] == 0)))) | |
7520 | { | |
7521 | imm_expr.X_op = O_constant; | |
7522 | if (! target_big_endian) | |
7523 | imm_expr.X_add_number = bfd_getl32 (temp); | |
7524 | else | |
7525 | imm_expr.X_add_number = bfd_getb32 (temp); | |
7526 | } | |
7527 | else if (length > 4 | |
119d663a | 7528 | && ! mips_disable_float_construction |
ca4e0257 RS |
7529 | /* Constants can only be constructed in GPRs and |
7530 | copied to FPRs if the GPRs are at least as wide | |
7531 | as the FPRs. Force the constant into memory if | |
7532 | we are using 64-bit FPRs but the GPRs are only | |
7533 | 32 bits wide. */ | |
7534 | && (using_gprs | |
7535 | || ! (HAVE_64BIT_FPRS && HAVE_32BIT_GPRS)) | |
252b5132 RH |
7536 | && ((temp[0] == 0 && temp[1] == 0) |
7537 | || (temp[2] == 0 && temp[3] == 0)) | |
7538 | && ((temp[4] == 0 && temp[5] == 0) | |
7539 | || (temp[6] == 0 && temp[7] == 0))) | |
7540 | { | |
ca4e0257 RS |
7541 | /* The value is simple enough to load with a couple of |
7542 | instructions. If using 32-bit registers, set | |
7543 | imm_expr to the high order 32 bits and offset_expr to | |
7544 | the low order 32 bits. Otherwise, set imm_expr to | |
7545 | the entire 64 bit constant. */ | |
7546 | if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS) | |
252b5132 RH |
7547 | { |
7548 | imm_expr.X_op = O_constant; | |
7549 | offset_expr.X_op = O_constant; | |
7550 | if (! target_big_endian) | |
7551 | { | |
7552 | imm_expr.X_add_number = bfd_getl32 (temp + 4); | |
7553 | offset_expr.X_add_number = bfd_getl32 (temp); | |
7554 | } | |
7555 | else | |
7556 | { | |
7557 | imm_expr.X_add_number = bfd_getb32 (temp); | |
7558 | offset_expr.X_add_number = bfd_getb32 (temp + 4); | |
7559 | } | |
7560 | if (offset_expr.X_add_number == 0) | |
7561 | offset_expr.X_op = O_absent; | |
7562 | } | |
7563 | else if (sizeof (imm_expr.X_add_number) > 4) | |
7564 | { | |
7565 | imm_expr.X_op = O_constant; | |
7566 | if (! target_big_endian) | |
7567 | imm_expr.X_add_number = bfd_getl64 (temp); | |
7568 | else | |
7569 | imm_expr.X_add_number = bfd_getb64 (temp); | |
7570 | } | |
7571 | else | |
7572 | { | |
7573 | imm_expr.X_op = O_big; | |
7574 | imm_expr.X_add_number = 4; | |
7575 | if (! target_big_endian) | |
7576 | { | |
7577 | generic_bignum[0] = bfd_getl16 (temp); | |
7578 | generic_bignum[1] = bfd_getl16 (temp + 2); | |
7579 | generic_bignum[2] = bfd_getl16 (temp + 4); | |
7580 | generic_bignum[3] = bfd_getl16 (temp + 6); | |
7581 | } | |
7582 | else | |
7583 | { | |
7584 | generic_bignum[0] = bfd_getb16 (temp + 6); | |
7585 | generic_bignum[1] = bfd_getb16 (temp + 4); | |
7586 | generic_bignum[2] = bfd_getb16 (temp + 2); | |
7587 | generic_bignum[3] = bfd_getb16 (temp); | |
7588 | } | |
7589 | } | |
7590 | } | |
7591 | else | |
7592 | { | |
7593 | const char *newname; | |
7594 | segT new_seg; | |
7595 | ||
7596 | /* Switch to the right section. */ | |
7597 | seg = now_seg; | |
7598 | subseg = now_subseg; | |
7599 | switch (*args) | |
7600 | { | |
7601 | default: /* unused default case avoids warnings. */ | |
7602 | case 'L': | |
7603 | newname = RDATA_SECTION_NAME; | |
bb2d6cd7 GK |
7604 | if ((USE_GLOBAL_POINTER_OPT && g_switch_value >= 8) |
7605 | || mips_pic == EMBEDDED_PIC) | |
252b5132 RH |
7606 | newname = ".lit8"; |
7607 | break; | |
7608 | case 'F': | |
bb2d6cd7 GK |
7609 | if (mips_pic == EMBEDDED_PIC) |
7610 | newname = ".lit8"; | |
7611 | else | |
7612 | newname = RDATA_SECTION_NAME; | |
252b5132 RH |
7613 | break; |
7614 | case 'l': | |
7615 | assert (!USE_GLOBAL_POINTER_OPT | |
7616 | || g_switch_value >= 4); | |
7617 | newname = ".lit4"; | |
7618 | break; | |
7619 | } | |
7620 | new_seg = subseg_new (newname, (subsegT) 0); | |
7621 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
7622 | bfd_set_section_flags (stdoutput, new_seg, | |
7623 | (SEC_ALLOC | |
7624 | | SEC_LOAD | |
7625 | | SEC_READONLY | |
7626 | | SEC_DATA)); | |
7627 | frag_align (*args == 'l' ? 2 : 3, 0, 0); | |
7628 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour | |
7629 | && strcmp (TARGET_OS, "elf") != 0) | |
7630 | record_alignment (new_seg, 4); | |
7631 | else | |
7632 | record_alignment (new_seg, *args == 'l' ? 2 : 3); | |
7633 | if (seg == now_seg) | |
7634 | as_bad (_("Can't use floating point insn in this section")); | |
7635 | ||
7636 | /* Set the argument to the current address in the | |
7637 | section. */ | |
7638 | offset_expr.X_op = O_symbol; | |
7639 | offset_expr.X_add_symbol = | |
7640 | symbol_new ("L0\001", now_seg, | |
7641 | (valueT) frag_now_fix (), frag_now); | |
7642 | offset_expr.X_add_number = 0; | |
7643 | ||
7644 | /* Put the floating point number into the section. */ | |
7645 | p = frag_more ((int) length); | |
7646 | memcpy (p, temp, length); | |
7647 | ||
7648 | /* Switch back to the original section. */ | |
7649 | subseg_set (seg, subseg); | |
7650 | } | |
7651 | } | |
7652 | continue; | |
7653 | ||
7654 | case 'i': /* 16 bit unsigned immediate */ | |
7655 | case 'j': /* 16 bit signed immediate */ | |
7656 | imm_reloc = BFD_RELOC_LO16; | |
7657 | c = my_getSmallExpression (&imm_expr, s); | |
7658 | if (c != '\0') | |
7659 | { | |
7660 | if (c != 'l') | |
7661 | { | |
7662 | if (imm_expr.X_op == O_constant) | |
7663 | imm_expr.X_add_number = | |
7664 | (imm_expr.X_add_number >> 16) & 0xffff; | |
7665 | else if (c == 'h') | |
7666 | { | |
7667 | imm_reloc = BFD_RELOC_HI16_S; | |
7668 | imm_unmatched_hi = true; | |
7669 | } | |
7670 | else | |
7671 | imm_reloc = BFD_RELOC_HI16; | |
7672 | } | |
7673 | else if (imm_expr.X_op == O_constant) | |
7674 | imm_expr.X_add_number &= 0xffff; | |
7675 | } | |
7676 | if (*args == 'i') | |
7677 | { | |
7678 | if ((c == '\0' && imm_expr.X_op != O_constant) | |
7679 | || ((imm_expr.X_add_number < 0 | |
beae10d5 KH |
7680 | || imm_expr.X_add_number >= 0x10000) |
7681 | && imm_expr.X_op == O_constant)) | |
252b5132 RH |
7682 | { |
7683 | if (insn + 1 < &mips_opcodes[NUMOPCODES] && | |
7684 | !strcmp (insn->name, insn[1].name)) | |
7685 | break; | |
2ae7e77b AH |
7686 | if (imm_expr.X_op == O_constant |
7687 | || imm_expr.X_op == O_big) | |
252b5132 RH |
7688 | as_bad (_("16 bit expression not in range 0..65535")); |
7689 | } | |
7690 | } | |
7691 | else | |
7692 | { | |
7693 | int more; | |
7694 | offsetT max; | |
7695 | ||
7696 | /* The upper bound should be 0x8000, but | |
7697 | unfortunately the MIPS assembler accepts numbers | |
7698 | from 0x8000 to 0xffff and sign extends them, and | |
7699 | we want to be compatible. We only permit this | |
7700 | extended range for an instruction which does not | |
7701 | provide any further alternates, since those | |
7702 | alternates may handle other cases. People should | |
7703 | use the numbers they mean, rather than relying on | |
7704 | a mysterious sign extension. */ | |
7705 | more = (insn + 1 < &mips_opcodes[NUMOPCODES] && | |
7706 | strcmp (insn->name, insn[1].name) == 0); | |
7707 | if (more) | |
7708 | max = 0x8000; | |
7709 | else | |
7710 | max = 0x10000; | |
7711 | if ((c == '\0' && imm_expr.X_op != O_constant) | |
7712 | || ((imm_expr.X_add_number < -0x8000 | |
beae10d5 KH |
7713 | || imm_expr.X_add_number >= max) |
7714 | && imm_expr.X_op == O_constant) | |
252b5132 RH |
7715 | || (more |
7716 | && imm_expr.X_add_number < 0 | |
ca4e0257 | 7717 | && HAVE_64BIT_GPRS |
252b5132 RH |
7718 | && imm_expr.X_unsigned |
7719 | && sizeof (imm_expr.X_add_number) <= 4)) | |
7720 | { | |
7721 | if (more) | |
7722 | break; | |
2ae7e77b AH |
7723 | if (imm_expr.X_op == O_constant |
7724 | || imm_expr.X_op == O_big) | |
252b5132 RH |
7725 | as_bad (_("16 bit expression not in range -32768..32767")); |
7726 | } | |
7727 | } | |
7728 | s = expr_end; | |
7729 | continue; | |
7730 | ||
7731 | case 'o': /* 16 bit offset */ | |
7732 | c = my_getSmallExpression (&offset_expr, s); | |
7733 | ||
7734 | /* If this value won't fit into a 16 bit offset, then go | |
7735 | find a macro that will generate the 32 bit offset | |
7736 | code pattern. As a special hack, we accept the | |
7737 | difference of two local symbols as a constant. This | |
7738 | is required to suppose embedded PIC switches, which | |
7739 | use an instruction which looks like | |
7740 | lw $4,$L12-$LS12($4) | |
7741 | The problem with handling this in a more general | |
7742 | fashion is that the macro function doesn't expect to | |
7743 | see anything which can be handled in a single | |
7744 | constant instruction. */ | |
7745 | if (c == 0 | |
7746 | && (offset_expr.X_op != O_constant | |
7747 | || offset_expr.X_add_number >= 0x8000 | |
7748 | || offset_expr.X_add_number < -0x8000) | |
7749 | && (mips_pic != EMBEDDED_PIC | |
7750 | || offset_expr.X_op != O_subtract | |
3dacdf2e NC |
7751 | || (S_GET_SEGMENT (offset_expr.X_add_symbol) |
7752 | != S_GET_SEGMENT (offset_expr.X_op_symbol)))) | |
252b5132 RH |
7753 | break; |
7754 | ||
7755 | if (c == 'h' || c == 'H') | |
7756 | { | |
7757 | if (offset_expr.X_op != O_constant) | |
7758 | break; | |
7759 | offset_expr.X_add_number = | |
7760 | (offset_expr.X_add_number >> 16) & 0xffff; | |
7761 | } | |
7762 | offset_reloc = BFD_RELOC_LO16; | |
7763 | s = expr_end; | |
7764 | continue; | |
7765 | ||
7766 | case 'p': /* pc relative offset */ | |
7767 | offset_reloc = BFD_RELOC_16_PCREL_S2; | |
7768 | my_getExpression (&offset_expr, s); | |
7769 | s = expr_end; | |
7770 | continue; | |
7771 | ||
7772 | case 'u': /* upper 16 bits */ | |
7773 | c = my_getSmallExpression (&imm_expr, s); | |
7774 | imm_reloc = BFD_RELOC_LO16; | |
7775 | if (c) | |
7776 | { | |
7777 | if (c != 'l') | |
7778 | { | |
7779 | if (imm_expr.X_op == O_constant) | |
7780 | imm_expr.X_add_number = | |
7781 | (imm_expr.X_add_number >> 16) & 0xffff; | |
7782 | else if (c == 'h') | |
7783 | { | |
7784 | imm_reloc = BFD_RELOC_HI16_S; | |
7785 | imm_unmatched_hi = true; | |
7786 | } | |
7787 | else | |
7788 | imm_reloc = BFD_RELOC_HI16; | |
7789 | } | |
7790 | else if (imm_expr.X_op == O_constant) | |
7791 | imm_expr.X_add_number &= 0xffff; | |
7792 | } | |
7793 | if (imm_expr.X_op == O_constant | |
7794 | && (imm_expr.X_add_number < 0 | |
7795 | || imm_expr.X_add_number >= 0x10000)) | |
7796 | as_bad (_("lui expression not in range 0..65535")); | |
7797 | s = expr_end; | |
7798 | continue; | |
7799 | ||
7800 | case 'a': /* 26 bit address */ | |
7801 | my_getExpression (&offset_expr, s); | |
7802 | s = expr_end; | |
7803 | offset_reloc = BFD_RELOC_MIPS_JMP; | |
7804 | continue; | |
7805 | ||
7806 | case 'N': /* 3 bit branch condition code */ | |
7807 | case 'M': /* 3 bit compare condition code */ | |
7808 | if (strncmp (s, "$fcc", 4) != 0) | |
7809 | break; | |
7810 | s += 4; | |
7811 | regno = 0; | |
7812 | do | |
7813 | { | |
7814 | regno *= 10; | |
7815 | regno += *s - '0'; | |
7816 | ++s; | |
7817 | } | |
d9a62219 | 7818 | while (isdigit ((unsigned char) *s)); |
252b5132 RH |
7819 | if (regno > 7) |
7820 | as_bad (_("invalid condition code register $fcc%d"), regno); | |
7821 | if (*args == 'N') | |
7822 | ip->insn_opcode |= regno << OP_SH_BCC; | |
7823 | else | |
7824 | ip->insn_opcode |= regno << OP_SH_CCC; | |
beae10d5 | 7825 | continue; |
252b5132 | 7826 | |
156c2f8b NC |
7827 | case 'H': |
7828 | if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X')) | |
7829 | s += 2; | |
7830 | if (isdigit ((unsigned char) *s)) | |
7831 | { | |
7832 | c = 0; | |
7833 | do | |
7834 | { | |
7835 | c *= 10; | |
7836 | c += *s - '0'; | |
7837 | ++s; | |
7838 | } | |
7839 | while (isdigit ((unsigned char) *s)); | |
7840 | } | |
7841 | else | |
7842 | c = 8; /* Invalid sel value. */ | |
7843 | ||
7844 | if (c > 7) | |
7845 | as_bad (_("invalid coprocessor sub-selection value (0-7)")); | |
7846 | ip->insn_opcode |= c; | |
7847 | continue; | |
7848 | ||
252b5132 RH |
7849 | default: |
7850 | as_bad (_("bad char = '%c'\n"), *args); | |
7851 | internalError (); | |
7852 | } | |
7853 | break; | |
7854 | } | |
7855 | /* Args don't match. */ | |
7856 | if (insn + 1 < &mips_opcodes[NUMOPCODES] && | |
7857 | !strcmp (insn->name, insn[1].name)) | |
7858 | { | |
7859 | ++insn; | |
7860 | s = argsStart; | |
268f6bed | 7861 | insn_error = _("illegal operands"); |
252b5132 RH |
7862 | continue; |
7863 | } | |
268f6bed L |
7864 | if (save_c) |
7865 | *(--s) = save_c; | |
252b5132 RH |
7866 | insn_error = _("illegal operands"); |
7867 | return; | |
7868 | } | |
7869 | } | |
7870 | ||
7871 | /* This routine assembles an instruction into its binary format when | |
7872 | assembling for the mips16. As a side effect, it sets one of the | |
7873 | global variables imm_reloc or offset_reloc to the type of | |
7874 | relocation to do if one of the operands is an address expression. | |
7875 | It also sets mips16_small and mips16_ext if the user explicitly | |
7876 | requested a small or extended instruction. */ | |
7877 | ||
7878 | static void | |
7879 | mips16_ip (str, ip) | |
7880 | char *str; | |
7881 | struct mips_cl_insn *ip; | |
7882 | { | |
7883 | char *s; | |
7884 | const char *args; | |
7885 | struct mips_opcode *insn; | |
7886 | char *argsstart; | |
7887 | unsigned int regno; | |
7888 | unsigned int lastregno = 0; | |
7889 | char *s_reset; | |
7890 | ||
7891 | insn_error = NULL; | |
7892 | ||
7893 | mips16_small = false; | |
7894 | mips16_ext = false; | |
7895 | ||
d9a62219 | 7896 | for (s = str; islower ((unsigned char) *s); ++s) |
252b5132 RH |
7897 | ; |
7898 | switch (*s) | |
7899 | { | |
7900 | case '\0': | |
7901 | break; | |
7902 | ||
7903 | case ' ': | |
7904 | *s++ = '\0'; | |
7905 | break; | |
7906 | ||
7907 | case '.': | |
7908 | if (s[1] == 't' && s[2] == ' ') | |
7909 | { | |
7910 | *s = '\0'; | |
7911 | mips16_small = true; | |
7912 | s += 3; | |
7913 | break; | |
7914 | } | |
7915 | else if (s[1] == 'e' && s[2] == ' ') | |
7916 | { | |
7917 | *s = '\0'; | |
7918 | mips16_ext = true; | |
7919 | s += 3; | |
7920 | break; | |
7921 | } | |
7922 | /* Fall through. */ | |
7923 | default: | |
7924 | insn_error = _("unknown opcode"); | |
7925 | return; | |
7926 | } | |
7927 | ||
7928 | if (mips_opts.noautoextend && ! mips16_ext) | |
7929 | mips16_small = true; | |
7930 | ||
7931 | if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL) | |
7932 | { | |
7933 | insn_error = _("unrecognized opcode"); | |
7934 | return; | |
7935 | } | |
7936 | ||
7937 | argsstart = s; | |
7938 | for (;;) | |
7939 | { | |
7940 | assert (strcmp (insn->name, str) == 0); | |
7941 | ||
7942 | ip->insn_mo = insn; | |
7943 | ip->insn_opcode = insn->match; | |
7944 | ip->use_extend = false; | |
7945 | imm_expr.X_op = O_absent; | |
7946 | imm_reloc = BFD_RELOC_UNUSED; | |
7947 | offset_expr.X_op = O_absent; | |
7948 | offset_reloc = BFD_RELOC_UNUSED; | |
7949 | for (args = insn->args; 1; ++args) | |
7950 | { | |
7951 | int c; | |
7952 | ||
7953 | if (*s == ' ') | |
7954 | ++s; | |
7955 | ||
7956 | /* In this switch statement we call break if we did not find | |
7957 | a match, continue if we did find a match, or return if we | |
7958 | are done. */ | |
7959 | ||
7960 | c = *args; | |
7961 | switch (c) | |
7962 | { | |
7963 | case '\0': | |
7964 | if (*s == '\0') | |
7965 | { | |
7966 | /* Stuff the immediate value in now, if we can. */ | |
7967 | if (imm_expr.X_op == O_constant | |
7968 | && imm_reloc > BFD_RELOC_UNUSED | |
7969 | && insn->pinfo != INSN_MACRO) | |
7970 | { | |
7971 | mips16_immed ((char *) NULL, 0, | |
7972 | imm_reloc - BFD_RELOC_UNUSED, | |
7973 | imm_expr.X_add_number, true, mips16_small, | |
7974 | mips16_ext, &ip->insn_opcode, | |
7975 | &ip->use_extend, &ip->extend); | |
7976 | imm_expr.X_op = O_absent; | |
7977 | imm_reloc = BFD_RELOC_UNUSED; | |
7978 | } | |
7979 | ||
7980 | return; | |
7981 | } | |
7982 | break; | |
7983 | ||
7984 | case ',': | |
7985 | if (*s++ == c) | |
7986 | continue; | |
7987 | s--; | |
7988 | switch (*++args) | |
7989 | { | |
7990 | case 'v': | |
7991 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RX; | |
7992 | continue; | |
7993 | case 'w': | |
7994 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RY; | |
7995 | continue; | |
7996 | } | |
7997 | break; | |
7998 | ||
7999 | case '(': | |
8000 | case ')': | |
8001 | if (*s++ == c) | |
8002 | continue; | |
8003 | break; | |
8004 | ||
8005 | case 'v': | |
8006 | case 'w': | |
8007 | if (s[0] != '$') | |
8008 | { | |
8009 | if (c == 'v') | |
8010 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RX; | |
8011 | else | |
8012 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RY; | |
8013 | ++args; | |
8014 | continue; | |
8015 | } | |
8016 | /* Fall through. */ | |
8017 | case 'x': | |
8018 | case 'y': | |
8019 | case 'z': | |
8020 | case 'Z': | |
8021 | case '0': | |
8022 | case 'S': | |
8023 | case 'R': | |
8024 | case 'X': | |
8025 | case 'Y': | |
8026 | if (s[0] != '$') | |
8027 | break; | |
8028 | s_reset = s; | |
d9a62219 | 8029 | if (isdigit ((unsigned char) s[1])) |
252b5132 RH |
8030 | { |
8031 | ++s; | |
8032 | regno = 0; | |
8033 | do | |
8034 | { | |
8035 | regno *= 10; | |
8036 | regno += *s - '0'; | |
8037 | ++s; | |
8038 | } | |
d9a62219 | 8039 | while (isdigit ((unsigned char) *s)); |
252b5132 RH |
8040 | if (regno > 31) |
8041 | { | |
8042 | as_bad (_("invalid register number (%d)"), regno); | |
8043 | regno = 2; | |
8044 | } | |
8045 | } | |
8046 | else | |
8047 | { | |
8048 | if (s[1] == 'f' && s[2] == 'p') | |
8049 | { | |
8050 | s += 3; | |
8051 | regno = FP; | |
8052 | } | |
8053 | else if (s[1] == 's' && s[2] == 'p') | |
8054 | { | |
8055 | s += 3; | |
8056 | regno = SP; | |
8057 | } | |
8058 | else if (s[1] == 'g' && s[2] == 'p') | |
8059 | { | |
8060 | s += 3; | |
8061 | regno = GP; | |
8062 | } | |
8063 | else if (s[1] == 'a' && s[2] == 't') | |
8064 | { | |
8065 | s += 3; | |
8066 | regno = AT; | |
8067 | } | |
8068 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '0') | |
8069 | { | |
8070 | s += 4; | |
8071 | regno = KT0; | |
8072 | } | |
8073 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '1') | |
8074 | { | |
8075 | s += 4; | |
8076 | regno = KT1; | |
8077 | } | |
8078 | else | |
8079 | break; | |
8080 | } | |
8081 | ||
8082 | if (*s == ' ') | |
8083 | ++s; | |
8084 | if (args[1] != *s) | |
8085 | { | |
8086 | if (c == 'v' || c == 'w') | |
8087 | { | |
8088 | regno = mips16_to_32_reg_map[lastregno]; | |
8089 | s = s_reset; | |
8090 | args++; | |
8091 | } | |
8092 | } | |
8093 | ||
8094 | switch (c) | |
8095 | { | |
8096 | case 'x': | |
8097 | case 'y': | |
8098 | case 'z': | |
8099 | case 'v': | |
8100 | case 'w': | |
8101 | case 'Z': | |
8102 | regno = mips32_to_16_reg_map[regno]; | |
8103 | break; | |
8104 | ||
8105 | case '0': | |
8106 | if (regno != 0) | |
8107 | regno = ILLEGAL_REG; | |
8108 | break; | |
8109 | ||
8110 | case 'S': | |
8111 | if (regno != SP) | |
8112 | regno = ILLEGAL_REG; | |
8113 | break; | |
8114 | ||
8115 | case 'R': | |
8116 | if (regno != RA) | |
8117 | regno = ILLEGAL_REG; | |
8118 | break; | |
8119 | ||
8120 | case 'X': | |
8121 | case 'Y': | |
8122 | if (regno == AT && ! mips_opts.noat) | |
8123 | as_warn (_("used $at without \".set noat\"")); | |
8124 | break; | |
8125 | ||
8126 | default: | |
8127 | internalError (); | |
8128 | } | |
8129 | ||
8130 | if (regno == ILLEGAL_REG) | |
8131 | break; | |
8132 | ||
8133 | switch (c) | |
8134 | { | |
8135 | case 'x': | |
8136 | case 'v': | |
8137 | ip->insn_opcode |= regno << MIPS16OP_SH_RX; | |
8138 | break; | |
8139 | case 'y': | |
8140 | case 'w': | |
8141 | ip->insn_opcode |= regno << MIPS16OP_SH_RY; | |
8142 | break; | |
8143 | case 'z': | |
8144 | ip->insn_opcode |= regno << MIPS16OP_SH_RZ; | |
8145 | break; | |
8146 | case 'Z': | |
8147 | ip->insn_opcode |= regno << MIPS16OP_SH_MOVE32Z; | |
8148 | case '0': | |
8149 | case 'S': | |
8150 | case 'R': | |
8151 | break; | |
8152 | case 'X': | |
8153 | ip->insn_opcode |= regno << MIPS16OP_SH_REGR32; | |
8154 | break; | |
8155 | case 'Y': | |
8156 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); | |
8157 | ip->insn_opcode |= regno << MIPS16OP_SH_REG32R; | |
8158 | break; | |
8159 | default: | |
8160 | internalError (); | |
8161 | } | |
8162 | ||
8163 | lastregno = regno; | |
8164 | continue; | |
8165 | ||
8166 | case 'P': | |
8167 | if (strncmp (s, "$pc", 3) == 0) | |
8168 | { | |
8169 | s += 3; | |
8170 | continue; | |
8171 | } | |
8172 | break; | |
8173 | ||
8174 | case '<': | |
8175 | case '>': | |
8176 | case '[': | |
8177 | case ']': | |
8178 | case '4': | |
8179 | case '5': | |
8180 | case 'H': | |
8181 | case 'W': | |
8182 | case 'D': | |
8183 | case 'j': | |
8184 | case '8': | |
8185 | case 'V': | |
8186 | case 'C': | |
8187 | case 'U': | |
8188 | case 'k': | |
8189 | case 'K': | |
8190 | if (s[0] == '%' | |
8191 | && strncmp (s + 1, "gprel(", sizeof "gprel(" - 1) == 0) | |
8192 | { | |
8193 | /* This is %gprel(SYMBOL). We need to read SYMBOL, | |
8194 | and generate the appropriate reloc. If the text | |
8195 | inside %gprel is not a symbol name with an | |
8196 | optional offset, then we generate a normal reloc | |
8197 | and will probably fail later. */ | |
8198 | my_getExpression (&imm_expr, s + sizeof "%gprel" - 1); | |
8199 | if (imm_expr.X_op == O_symbol) | |
8200 | { | |
8201 | mips16_ext = true; | |
8202 | imm_reloc = BFD_RELOC_MIPS16_GPREL; | |
8203 | s = expr_end; | |
8204 | ip->use_extend = true; | |
8205 | ip->extend = 0; | |
8206 | continue; | |
8207 | } | |
8208 | } | |
8209 | else | |
8210 | { | |
8211 | /* Just pick up a normal expression. */ | |
8212 | my_getExpression (&imm_expr, s); | |
8213 | } | |
8214 | ||
8215 | if (imm_expr.X_op == O_register) | |
8216 | { | |
8217 | /* What we thought was an expression turned out to | |
8218 | be a register. */ | |
8219 | ||
8220 | if (s[0] == '(' && args[1] == '(') | |
8221 | { | |
8222 | /* It looks like the expression was omitted | |
8223 | before a register indirection, which means | |
8224 | that the expression is implicitly zero. We | |
8225 | still set up imm_expr, so that we handle | |
8226 | explicit extensions correctly. */ | |
8227 | imm_expr.X_op = O_constant; | |
8228 | imm_expr.X_add_number = 0; | |
8229 | imm_reloc = (int) BFD_RELOC_UNUSED + c; | |
8230 | continue; | |
8231 | } | |
8232 | ||
8233 | break; | |
8234 | } | |
8235 | ||
8236 | /* We need to relax this instruction. */ | |
8237 | imm_reloc = (int) BFD_RELOC_UNUSED + c; | |
8238 | s = expr_end; | |
8239 | continue; | |
8240 | ||
8241 | case 'p': | |
8242 | case 'q': | |
8243 | case 'A': | |
8244 | case 'B': | |
8245 | case 'E': | |
8246 | /* We use offset_reloc rather than imm_reloc for the PC | |
8247 | relative operands. This lets macros with both | |
8248 | immediate and address operands work correctly. */ | |
8249 | my_getExpression (&offset_expr, s); | |
8250 | ||
8251 | if (offset_expr.X_op == O_register) | |
8252 | break; | |
8253 | ||
8254 | /* We need to relax this instruction. */ | |
8255 | offset_reloc = (int) BFD_RELOC_UNUSED + c; | |
8256 | s = expr_end; | |
8257 | continue; | |
8258 | ||
8259 | case '6': /* break code */ | |
8260 | my_getExpression (&imm_expr, s); | |
8261 | check_absolute_expr (ip, &imm_expr); | |
8262 | if ((unsigned long) imm_expr.X_add_number > 63) | |
8263 | { | |
8264 | as_warn (_("Invalid value for `%s' (%lu)"), | |
8265 | ip->insn_mo->name, | |
8266 | (unsigned long) imm_expr.X_add_number); | |
8267 | imm_expr.X_add_number &= 0x3f; | |
8268 | } | |
8269 | ip->insn_opcode |= imm_expr.X_add_number << MIPS16OP_SH_IMM6; | |
8270 | imm_expr.X_op = O_absent; | |
8271 | s = expr_end; | |
8272 | continue; | |
8273 | ||
8274 | case 'a': /* 26 bit address */ | |
8275 | my_getExpression (&offset_expr, s); | |
8276 | s = expr_end; | |
8277 | offset_reloc = BFD_RELOC_MIPS16_JMP; | |
8278 | ip->insn_opcode <<= 16; | |
8279 | continue; | |
8280 | ||
8281 | case 'l': /* register list for entry macro */ | |
8282 | case 'L': /* register list for exit macro */ | |
8283 | { | |
8284 | int mask; | |
8285 | ||
8286 | if (c == 'l') | |
8287 | mask = 0; | |
8288 | else | |
8289 | mask = 7 << 3; | |
8290 | while (*s != '\0') | |
8291 | { | |
8292 | int freg, reg1, reg2; | |
8293 | ||
8294 | while (*s == ' ' || *s == ',') | |
8295 | ++s; | |
8296 | if (*s != '$') | |
8297 | { | |
8298 | as_bad (_("can't parse register list")); | |
8299 | break; | |
8300 | } | |
8301 | ++s; | |
8302 | if (*s != 'f') | |
8303 | freg = 0; | |
8304 | else | |
8305 | { | |
8306 | freg = 1; | |
8307 | ++s; | |
8308 | } | |
8309 | reg1 = 0; | |
d9a62219 | 8310 | while (isdigit ((unsigned char) *s)) |
252b5132 RH |
8311 | { |
8312 | reg1 *= 10; | |
8313 | reg1 += *s - '0'; | |
8314 | ++s; | |
8315 | } | |
8316 | if (*s == ' ') | |
8317 | ++s; | |
8318 | if (*s != '-') | |
8319 | reg2 = reg1; | |
8320 | else | |
8321 | { | |
8322 | ++s; | |
8323 | if (*s != '$') | |
8324 | break; | |
8325 | ++s; | |
8326 | if (freg) | |
8327 | { | |
8328 | if (*s == 'f') | |
8329 | ++s; | |
8330 | else | |
8331 | { | |
8332 | as_bad (_("invalid register list")); | |
8333 | break; | |
8334 | } | |
8335 | } | |
8336 | reg2 = 0; | |
d9a62219 | 8337 | while (isdigit ((unsigned char) *s)) |
252b5132 RH |
8338 | { |
8339 | reg2 *= 10; | |
8340 | reg2 += *s - '0'; | |
8341 | ++s; | |
8342 | } | |
8343 | } | |
8344 | if (freg && reg1 == 0 && reg2 == 0 && c == 'L') | |
8345 | { | |
8346 | mask &= ~ (7 << 3); | |
8347 | mask |= 5 << 3; | |
8348 | } | |
8349 | else if (freg && reg1 == 0 && reg2 == 1 && c == 'L') | |
8350 | { | |
8351 | mask &= ~ (7 << 3); | |
8352 | mask |= 6 << 3; | |
8353 | } | |
8354 | else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L') | |
8355 | mask |= (reg2 - 3) << 3; | |
8356 | else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17) | |
8357 | mask |= (reg2 - 15) << 1; | |
8358 | else if (reg1 == 31 && reg2 == 31) | |
8359 | mask |= 1; | |
8360 | else | |
8361 | { | |
8362 | as_bad (_("invalid register list")); | |
8363 | break; | |
8364 | } | |
8365 | } | |
8366 | /* The mask is filled in in the opcode table for the | |
8367 | benefit of the disassembler. We remove it before | |
8368 | applying the actual mask. */ | |
8369 | ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6); | |
8370 | ip->insn_opcode |= mask << MIPS16OP_SH_IMM6; | |
8371 | } | |
8372 | continue; | |
8373 | ||
8374 | case 'e': /* extend code */ | |
8375 | my_getExpression (&imm_expr, s); | |
8376 | check_absolute_expr (ip, &imm_expr); | |
8377 | if ((unsigned long) imm_expr.X_add_number > 0x7ff) | |
8378 | { | |
8379 | as_warn (_("Invalid value for `%s' (%lu)"), | |
8380 | ip->insn_mo->name, | |
8381 | (unsigned long) imm_expr.X_add_number); | |
8382 | imm_expr.X_add_number &= 0x7ff; | |
8383 | } | |
8384 | ip->insn_opcode |= imm_expr.X_add_number; | |
8385 | imm_expr.X_op = O_absent; | |
8386 | s = expr_end; | |
8387 | continue; | |
8388 | ||
8389 | default: | |
8390 | internalError (); | |
8391 | } | |
8392 | break; | |
8393 | } | |
8394 | ||
8395 | /* Args don't match. */ | |
8396 | if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] && | |
8397 | strcmp (insn->name, insn[1].name) == 0) | |
8398 | { | |
8399 | ++insn; | |
8400 | s = argsstart; | |
8401 | continue; | |
8402 | } | |
8403 | ||
8404 | insn_error = _("illegal operands"); | |
8405 | ||
8406 | return; | |
8407 | } | |
8408 | } | |
8409 | ||
8410 | /* This structure holds information we know about a mips16 immediate | |
8411 | argument type. */ | |
8412 | ||
e972090a NC |
8413 | struct mips16_immed_operand |
8414 | { | |
252b5132 RH |
8415 | /* The type code used in the argument string in the opcode table. */ |
8416 | int type; | |
8417 | /* The number of bits in the short form of the opcode. */ | |
8418 | int nbits; | |
8419 | /* The number of bits in the extended form of the opcode. */ | |
8420 | int extbits; | |
8421 | /* The amount by which the short form is shifted when it is used; | |
8422 | for example, the sw instruction has a shift count of 2. */ | |
8423 | int shift; | |
8424 | /* The amount by which the short form is shifted when it is stored | |
8425 | into the instruction code. */ | |
8426 | int op_shift; | |
8427 | /* Non-zero if the short form is unsigned. */ | |
8428 | int unsp; | |
8429 | /* Non-zero if the extended form is unsigned. */ | |
8430 | int extu; | |
8431 | /* Non-zero if the value is PC relative. */ | |
8432 | int pcrel; | |
8433 | }; | |
8434 | ||
8435 | /* The mips16 immediate operand types. */ | |
8436 | ||
8437 | static const struct mips16_immed_operand mips16_immed_operands[] = | |
8438 | { | |
8439 | { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
8440 | { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
8441 | { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
8442 | { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
8443 | { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 }, | |
8444 | { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
8445 | { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
8446 | { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
8447 | { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
8448 | { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 }, | |
8449 | { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
8450 | { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
8451 | { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
8452 | { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 }, | |
8453 | { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
8454 | { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
8455 | { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
8456 | { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
8457 | { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 }, | |
8458 | { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 }, | |
8459 | { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 } | |
8460 | }; | |
8461 | ||
8462 | #define MIPS16_NUM_IMMED \ | |
8463 | (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0]) | |
8464 | ||
8465 | /* Handle a mips16 instruction with an immediate value. This or's the | |
8466 | small immediate value into *INSN. It sets *USE_EXTEND to indicate | |
8467 | whether an extended value is needed; if one is needed, it sets | |
8468 | *EXTEND to the value. The argument type is TYPE. The value is VAL. | |
8469 | If SMALL is true, an unextended opcode was explicitly requested. | |
8470 | If EXT is true, an extended opcode was explicitly requested. If | |
8471 | WARN is true, warn if EXT does not match reality. */ | |
8472 | ||
8473 | static void | |
8474 | mips16_immed (file, line, type, val, warn, small, ext, insn, use_extend, | |
8475 | extend) | |
8476 | char *file; | |
8477 | unsigned int line; | |
8478 | int type; | |
8479 | offsetT val; | |
8480 | boolean warn; | |
8481 | boolean small; | |
8482 | boolean ext; | |
8483 | unsigned long *insn; | |
8484 | boolean *use_extend; | |
8485 | unsigned short *extend; | |
8486 | { | |
8487 | register const struct mips16_immed_operand *op; | |
8488 | int mintiny, maxtiny; | |
8489 | boolean needext; | |
8490 | ||
8491 | op = mips16_immed_operands; | |
8492 | while (op->type != type) | |
8493 | { | |
8494 | ++op; | |
8495 | assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); | |
8496 | } | |
8497 | ||
8498 | if (op->unsp) | |
8499 | { | |
8500 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
8501 | { | |
8502 | mintiny = 1; | |
8503 | maxtiny = 1 << op->nbits; | |
8504 | } | |
8505 | else | |
8506 | { | |
8507 | mintiny = 0; | |
8508 | maxtiny = (1 << op->nbits) - 1; | |
8509 | } | |
8510 | } | |
8511 | else | |
8512 | { | |
8513 | mintiny = - (1 << (op->nbits - 1)); | |
8514 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
8515 | } | |
8516 | ||
8517 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
8518 | if (type == 'p' || type == 'q') | |
8519 | val /= 2; | |
8520 | ||
8521 | if ((val & ((1 << op->shift) - 1)) != 0 | |
8522 | || val < (mintiny << op->shift) | |
8523 | || val > (maxtiny << op->shift)) | |
8524 | needext = true; | |
8525 | else | |
8526 | needext = false; | |
8527 | ||
8528 | if (warn && ext && ! needext) | |
beae10d5 KH |
8529 | as_warn_where (file, line, |
8530 | _("extended operand requested but not required")); | |
252b5132 RH |
8531 | if (small && needext) |
8532 | as_bad_where (file, line, _("invalid unextended operand value")); | |
8533 | ||
8534 | if (small || (! ext && ! needext)) | |
8535 | { | |
8536 | int insnval; | |
8537 | ||
8538 | *use_extend = false; | |
8539 | insnval = ((val >> op->shift) & ((1 << op->nbits) - 1)); | |
8540 | insnval <<= op->op_shift; | |
8541 | *insn |= insnval; | |
8542 | } | |
8543 | else | |
8544 | { | |
8545 | long minext, maxext; | |
8546 | int extval; | |
8547 | ||
8548 | if (op->extu) | |
8549 | { | |
8550 | minext = 0; | |
8551 | maxext = (1 << op->extbits) - 1; | |
8552 | } | |
8553 | else | |
8554 | { | |
8555 | minext = - (1 << (op->extbits - 1)); | |
8556 | maxext = (1 << (op->extbits - 1)) - 1; | |
8557 | } | |
8558 | if (val < minext || val > maxext) | |
8559 | as_bad_where (file, line, | |
8560 | _("operand value out of range for instruction")); | |
8561 | ||
8562 | *use_extend = true; | |
8563 | if (op->extbits == 16) | |
8564 | { | |
8565 | extval = ((val >> 11) & 0x1f) | (val & 0x7e0); | |
8566 | val &= 0x1f; | |
8567 | } | |
8568 | else if (op->extbits == 15) | |
8569 | { | |
8570 | extval = ((val >> 11) & 0xf) | (val & 0x7f0); | |
8571 | val &= 0xf; | |
8572 | } | |
8573 | else | |
8574 | { | |
8575 | extval = ((val & 0x1f) << 6) | (val & 0x20); | |
8576 | val = 0; | |
8577 | } | |
8578 | ||
8579 | *extend = (unsigned short) extval; | |
8580 | *insn |= val; | |
8581 | } | |
8582 | } | |
8583 | \f | |
8584 | #define LP '(' | |
8585 | #define RP ')' | |
8586 | ||
8587 | static int | |
8588 | my_getSmallExpression (ep, str) | |
8589 | expressionS *ep; | |
8590 | char *str; | |
8591 | { | |
8592 | char *sp; | |
8593 | int c = 0; | |
8594 | ||
8595 | if (*str == ' ') | |
8596 | str++; | |
8597 | if (*str == LP | |
8598 | || (*str == '%' && | |
8599 | ((str[1] == 'h' && str[2] == 'i') | |
8600 | || (str[1] == 'H' && str[2] == 'I') | |
8601 | || (str[1] == 'l' && str[2] == 'o')) | |
8602 | && str[3] == LP)) | |
8603 | { | |
8604 | if (*str == LP) | |
8605 | c = 0; | |
8606 | else | |
8607 | { | |
8608 | c = str[1]; | |
8609 | str += 3; | |
8610 | } | |
8611 | ||
8612 | /* | |
8613 | * A small expression may be followed by a base register. | |
8614 | * Scan to the end of this operand, and then back over a possible | |
8615 | * base register. Then scan the small expression up to that | |
8616 | * point. (Based on code in sparc.c...) | |
8617 | */ | |
8618 | for (sp = str; *sp && *sp != ','; sp++) | |
8619 | ; | |
8620 | if (sp - 4 >= str && sp[-1] == RP) | |
8621 | { | |
d9a62219 | 8622 | if (isdigit ((unsigned char) sp[-2])) |
252b5132 | 8623 | { |
d9a62219 | 8624 | for (sp -= 3; sp >= str && isdigit ((unsigned char) *sp); sp--) |
252b5132 RH |
8625 | ; |
8626 | if (*sp == '$' && sp > str && sp[-1] == LP) | |
8627 | { | |
8628 | sp--; | |
8629 | goto do_it; | |
8630 | } | |
8631 | } | |
8632 | else if (sp - 5 >= str | |
8633 | && sp[-5] == LP | |
8634 | && sp[-4] == '$' | |
8635 | && ((sp[-3] == 'f' && sp[-2] == 'p') | |
8636 | || (sp[-3] == 's' && sp[-2] == 'p') | |
8637 | || (sp[-3] == 'g' && sp[-2] == 'p') | |
8638 | || (sp[-3] == 'a' && sp[-2] == 't'))) | |
8639 | { | |
8640 | sp -= 5; | |
8641 | do_it: | |
8642 | if (sp == str) | |
8643 | { | |
8644 | /* no expression means zero offset */ | |
8645 | if (c) | |
8646 | { | |
8647 | /* %xx(reg) is an error */ | |
8648 | ep->X_op = O_absent; | |
8649 | expr_end = str - 3; | |
8650 | } | |
8651 | else | |
8652 | { | |
8653 | ep->X_op = O_constant; | |
8654 | expr_end = sp; | |
8655 | } | |
8656 | ep->X_add_symbol = NULL; | |
8657 | ep->X_op_symbol = NULL; | |
8658 | ep->X_add_number = 0; | |
8659 | } | |
8660 | else | |
8661 | { | |
8662 | *sp = '\0'; | |
8663 | my_getExpression (ep, str); | |
8664 | *sp = LP; | |
8665 | } | |
8666 | return c; | |
8667 | } | |
8668 | } | |
8669 | } | |
8670 | my_getExpression (ep, str); | |
8671 | return c; /* => %hi or %lo encountered */ | |
8672 | } | |
8673 | ||
8674 | static void | |
8675 | my_getExpression (ep, str) | |
8676 | expressionS *ep; | |
8677 | char *str; | |
8678 | { | |
8679 | char *save_in; | |
98aa84af | 8680 | valueT val; |
252b5132 RH |
8681 | |
8682 | save_in = input_line_pointer; | |
8683 | input_line_pointer = str; | |
8684 | expression (ep); | |
8685 | expr_end = input_line_pointer; | |
8686 | input_line_pointer = save_in; | |
8687 | ||
8688 | /* If we are in mips16 mode, and this is an expression based on `.', | |
8689 | then we bump the value of the symbol by 1 since that is how other | |
8690 | text symbols are handled. We don't bother to handle complex | |
8691 | expressions, just `.' plus or minus a constant. */ | |
8692 | if (mips_opts.mips16 | |
8693 | && ep->X_op == O_symbol | |
8694 | && strcmp (S_GET_NAME (ep->X_add_symbol), FAKE_LABEL_NAME) == 0 | |
8695 | && S_GET_SEGMENT (ep->X_add_symbol) == now_seg | |
49309057 ILT |
8696 | && symbol_get_frag (ep->X_add_symbol) == frag_now |
8697 | && symbol_constant_p (ep->X_add_symbol) | |
98aa84af AM |
8698 | && (val = S_GET_VALUE (ep->X_add_symbol)) == frag_now_fix ()) |
8699 | S_SET_VALUE (ep->X_add_symbol, val + 1); | |
252b5132 RH |
8700 | } |
8701 | ||
8702 | /* Turn a string in input_line_pointer into a floating point constant | |
bc0d738a NC |
8703 | of type TYPE, and store the appropriate bytes in *LITP. The number |
8704 | of LITTLENUMS emitted is stored in *SIZEP. An error message is | |
252b5132 RH |
8705 | returned, or NULL on OK. */ |
8706 | ||
8707 | char * | |
8708 | md_atof (type, litP, sizeP) | |
8709 | int type; | |
8710 | char *litP; | |
8711 | int *sizeP; | |
8712 | { | |
8713 | int prec; | |
8714 | LITTLENUM_TYPE words[4]; | |
8715 | char *t; | |
8716 | int i; | |
8717 | ||
8718 | switch (type) | |
8719 | { | |
8720 | case 'f': | |
8721 | prec = 2; | |
8722 | break; | |
8723 | ||
8724 | case 'd': | |
8725 | prec = 4; | |
8726 | break; | |
8727 | ||
8728 | default: | |
8729 | *sizeP = 0; | |
8730 | return _("bad call to md_atof"); | |
8731 | } | |
8732 | ||
8733 | t = atof_ieee (input_line_pointer, type, words); | |
8734 | if (t) | |
8735 | input_line_pointer = t; | |
8736 | ||
8737 | *sizeP = prec * 2; | |
8738 | ||
8739 | if (! target_big_endian) | |
8740 | { | |
8741 | for (i = prec - 1; i >= 0; i--) | |
8742 | { | |
8743 | md_number_to_chars (litP, (valueT) words[i], 2); | |
8744 | litP += 2; | |
8745 | } | |
8746 | } | |
8747 | else | |
8748 | { | |
8749 | for (i = 0; i < prec; i++) | |
8750 | { | |
8751 | md_number_to_chars (litP, (valueT) words[i], 2); | |
8752 | litP += 2; | |
8753 | } | |
8754 | } | |
bdaaa2e1 | 8755 | |
252b5132 RH |
8756 | return NULL; |
8757 | } | |
8758 | ||
8759 | void | |
8760 | md_number_to_chars (buf, val, n) | |
8761 | char *buf; | |
8762 | valueT val; | |
8763 | int n; | |
8764 | { | |
8765 | if (target_big_endian) | |
8766 | number_to_chars_bigendian (buf, val, n); | |
8767 | else | |
8768 | number_to_chars_littleendian (buf, val, n); | |
8769 | } | |
8770 | \f | |
39c0a331 | 8771 | CONST char *md_shortopts = "nO::g::G:"; |
252b5132 | 8772 | |
e972090a NC |
8773 | struct option md_longopts[] = |
8774 | { | |
252b5132 RH |
8775 | #define OPTION_MIPS1 (OPTION_MD_BASE + 1) |
8776 | {"mips0", no_argument, NULL, OPTION_MIPS1}, | |
8777 | {"mips1", no_argument, NULL, OPTION_MIPS1}, | |
8778 | #define OPTION_MIPS2 (OPTION_MD_BASE + 2) | |
8779 | {"mips2", no_argument, NULL, OPTION_MIPS2}, | |
8780 | #define OPTION_MIPS3 (OPTION_MD_BASE + 3) | |
8781 | {"mips3", no_argument, NULL, OPTION_MIPS3}, | |
8782 | #define OPTION_MIPS4 (OPTION_MD_BASE + 4) | |
8783 | {"mips4", no_argument, NULL, OPTION_MIPS4}, | |
8784 | #define OPTION_MCPU (OPTION_MD_BASE + 5) | |
8785 | {"mcpu", required_argument, NULL, OPTION_MCPU}, | |
8786 | #define OPTION_MEMBEDDED_PIC (OPTION_MD_BASE + 6) | |
8787 | {"membedded-pic", no_argument, NULL, OPTION_MEMBEDDED_PIC}, | |
156c2f8b | 8788 | #define OPTION_TRAP (OPTION_MD_BASE + 7) |
252b5132 RH |
8789 | {"trap", no_argument, NULL, OPTION_TRAP}, |
8790 | {"no-break", no_argument, NULL, OPTION_TRAP}, | |
156c2f8b | 8791 | #define OPTION_BREAK (OPTION_MD_BASE + 8) |
252b5132 RH |
8792 | {"break", no_argument, NULL, OPTION_BREAK}, |
8793 | {"no-trap", no_argument, NULL, OPTION_BREAK}, | |
156c2f8b | 8794 | #define OPTION_EB (OPTION_MD_BASE + 9) |
252b5132 | 8795 | {"EB", no_argument, NULL, OPTION_EB}, |
156c2f8b | 8796 | #define OPTION_EL (OPTION_MD_BASE + 10) |
252b5132 | 8797 | {"EL", no_argument, NULL, OPTION_EL}, |
156c2f8b | 8798 | #define OPTION_M4650 (OPTION_MD_BASE + 11) |
252b5132 | 8799 | {"m4650", no_argument, NULL, OPTION_M4650}, |
156c2f8b | 8800 | #define OPTION_NO_M4650 (OPTION_MD_BASE + 12) |
252b5132 | 8801 | {"no-m4650", no_argument, NULL, OPTION_NO_M4650}, |
156c2f8b | 8802 | #define OPTION_M4010 (OPTION_MD_BASE + 13) |
252b5132 | 8803 | {"m4010", no_argument, NULL, OPTION_M4010}, |
156c2f8b | 8804 | #define OPTION_NO_M4010 (OPTION_MD_BASE + 14) |
252b5132 | 8805 | {"no-m4010", no_argument, NULL, OPTION_NO_M4010}, |
156c2f8b | 8806 | #define OPTION_M4100 (OPTION_MD_BASE + 15) |
252b5132 | 8807 | {"m4100", no_argument, NULL, OPTION_M4100}, |
156c2f8b | 8808 | #define OPTION_NO_M4100 (OPTION_MD_BASE + 16) |
252b5132 | 8809 | {"no-m4100", no_argument, NULL, OPTION_NO_M4100}, |
156c2f8b | 8810 | #define OPTION_MIPS16 (OPTION_MD_BASE + 17) |
252b5132 | 8811 | {"mips16", no_argument, NULL, OPTION_MIPS16}, |
156c2f8b | 8812 | #define OPTION_NO_MIPS16 (OPTION_MD_BASE + 18) |
252b5132 | 8813 | {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16}, |
156c2f8b | 8814 | #define OPTION_M3900 (OPTION_MD_BASE + 19) |
252b5132 | 8815 | {"m3900", no_argument, NULL, OPTION_M3900}, |
156c2f8b | 8816 | #define OPTION_NO_M3900 (OPTION_MD_BASE + 20) |
252b5132 | 8817 | {"no-m3900", no_argument, NULL, OPTION_NO_M3900}, |
156c2f8b | 8818 | #define OPTION_MABI (OPTION_MD_BASE + 21) |
252b5132 | 8819 | {"mabi", required_argument, NULL, OPTION_MABI}, |
156c2f8b | 8820 | #define OPTION_M7000_HILO_FIX (OPTION_MD_BASE + 22) |
6b76fefe | 8821 | {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX}, |
156c2f8b | 8822 | #define OPTION_NO_M7000_HILO_FIX (OPTION_MD_BASE + 23) |
6b76fefe | 8823 | {"no-fix-7000", no_argument, NULL, OPTION_NO_M7000_HILO_FIX}, |
156c2f8b | 8824 | #define OPTION_GP32 (OPTION_MD_BASE + 24) |
c97ef257 | 8825 | {"mgp32", no_argument, NULL, OPTION_GP32}, |
156c2f8b | 8826 | #define OPTION_GP64 (OPTION_MD_BASE + 25) |
c97ef257 | 8827 | {"mgp64", no_argument, NULL, OPTION_GP64}, |
156c2f8b | 8828 | #define OPTION_CONSTRUCT_FLOATS (OPTION_MD_BASE + 26) |
119d663a | 8829 | {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS}, |
156c2f8b | 8830 | #define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MD_BASE + 27) |
119d663a | 8831 | {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS}, |
156c2f8b NC |
8832 | #define OPTION_MIPS32 (OPTION_MD_BASE + 28) |
8833 | {"mips32", no_argument, NULL, OPTION_MIPS32}, | |
84ea6cf2 NC |
8834 | #define OPTION_MIPS5 (OPTION_MD_BASE + 29) |
8835 | {"mips5", no_argument, NULL, OPTION_MIPS5}, | |
8836 | #define OPTION_MIPS64 (OPTION_MD_BASE + 30) | |
8837 | {"mips64", no_argument, NULL, OPTION_MIPS64}, | |
ec68c924 EC |
8838 | #define OPTION_MARCH (OPTION_MD_BASE + 31) |
8839 | {"march", required_argument, NULL, OPTION_MARCH}, | |
8840 | #define OPTION_MTUNE (OPTION_MD_BASE + 32) | |
8841 | {"mtune", required_argument, NULL, OPTION_MTUNE}, | |
ca4e0257 RS |
8842 | #define OPTION_FP32 (OPTION_MD_BASE + 33) |
8843 | {"mfp32", no_argument, NULL, OPTION_FP32}, | |
156c2f8b NC |
8844 | #ifdef OBJ_ELF |
8845 | #define OPTION_ELF_BASE (OPTION_MD_BASE + 35) | |
8846 | #define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0) | |
8847 | #define OPTION_NON_SHARED (OPTION_ELF_BASE + 1) | |
8848 | #define OPTION_XGOT (OPTION_ELF_BASE + 2) | |
8849 | #define OPTION_32 (OPTION_ELF_BASE + 3) | |
8850 | #define OPTION_64 (OPTION_ELF_BASE + 4) | |
8851 | {"KPIC", no_argument, NULL, OPTION_CALL_SHARED}, | |
8852 | {"call_shared", no_argument, NULL, OPTION_CALL_SHARED}, | |
8853 | {"non_shared", no_argument, NULL, OPTION_NON_SHARED}, | |
8854 | {"xgot", no_argument, NULL, OPTION_XGOT}, | |
8855 | {"32", no_argument, NULL, OPTION_32}, | |
8856 | {"64", no_argument, NULL, OPTION_64}, | |
8857 | #endif | |
119d663a | 8858 | |
252b5132 RH |
8859 | {NULL, no_argument, NULL, 0} |
8860 | }; | |
156c2f8b | 8861 | size_t md_longopts_size = sizeof (md_longopts); |
252b5132 RH |
8862 | |
8863 | int | |
8864 | md_parse_option (c, arg) | |
8865 | int c; | |
8866 | char *arg; | |
8867 | { | |
8868 | switch (c) | |
8869 | { | |
119d663a NC |
8870 | case OPTION_CONSTRUCT_FLOATS: |
8871 | mips_disable_float_construction = 0; | |
8872 | break; | |
bdaaa2e1 | 8873 | |
119d663a NC |
8874 | case OPTION_NO_CONSTRUCT_FLOATS: |
8875 | mips_disable_float_construction = 1; | |
8876 | break; | |
bdaaa2e1 | 8877 | |
252b5132 RH |
8878 | case OPTION_TRAP: |
8879 | mips_trap = 1; | |
8880 | break; | |
8881 | ||
8882 | case OPTION_BREAK: | |
8883 | mips_trap = 0; | |
8884 | break; | |
8885 | ||
8886 | case OPTION_EB: | |
8887 | target_big_endian = 1; | |
8888 | break; | |
8889 | ||
8890 | case OPTION_EL: | |
8891 | target_big_endian = 0; | |
8892 | break; | |
8893 | ||
39c0a331 L |
8894 | case 'n': |
8895 | warn_nops = 1; | |
8896 | break; | |
8897 | ||
252b5132 RH |
8898 | case 'O': |
8899 | if (arg && arg[1] == '0') | |
8900 | mips_optimize = 1; | |
8901 | else | |
8902 | mips_optimize = 2; | |
8903 | break; | |
8904 | ||
8905 | case 'g': | |
8906 | if (arg == NULL) | |
8907 | mips_debug = 2; | |
8908 | else | |
8909 | mips_debug = atoi (arg); | |
8910 | /* When the MIPS assembler sees -g or -g2, it does not do | |
8911 | optimizations which limit full symbolic debugging. We take | |
8912 | that to be equivalent to -O0. */ | |
8913 | if (mips_debug == 2) | |
8914 | mips_optimize = 1; | |
8915 | break; | |
8916 | ||
8917 | case OPTION_MIPS1: | |
e7af610e | 8918 | mips_opts.isa = ISA_MIPS1; |
252b5132 RH |
8919 | break; |
8920 | ||
8921 | case OPTION_MIPS2: | |
e7af610e | 8922 | mips_opts.isa = ISA_MIPS2; |
252b5132 RH |
8923 | break; |
8924 | ||
8925 | case OPTION_MIPS3: | |
e7af610e | 8926 | mips_opts.isa = ISA_MIPS3; |
252b5132 RH |
8927 | break; |
8928 | ||
8929 | case OPTION_MIPS4: | |
e7af610e NC |
8930 | mips_opts.isa = ISA_MIPS4; |
8931 | break; | |
8932 | ||
84ea6cf2 NC |
8933 | case OPTION_MIPS5: |
8934 | mips_opts.isa = ISA_MIPS5; | |
8935 | break; | |
8936 | ||
e7af610e NC |
8937 | case OPTION_MIPS32: |
8938 | mips_opts.isa = ISA_MIPS32; | |
252b5132 RH |
8939 | break; |
8940 | ||
84ea6cf2 NC |
8941 | case OPTION_MIPS64: |
8942 | mips_opts.isa = ISA_MIPS64; | |
8943 | break; | |
8944 | ||
ec68c924 EC |
8945 | case OPTION_MTUNE: |
8946 | case OPTION_MARCH: | |
252b5132 RH |
8947 | case OPTION_MCPU: |
8948 | { | |
ec68c924 EC |
8949 | int cpu = CPU_UNKNOWN; |
8950 | ||
e7af610e | 8951 | /* Identify the processor type. */ |
ec68c924 | 8952 | if (strcasecmp (arg, "default") != 0) |
252b5132 | 8953 | { |
e7af610e | 8954 | const struct mips_cpu_info *ci; |
252b5132 | 8955 | |
e7af610e NC |
8956 | ci = mips_cpu_info_from_name (arg); |
8957 | if (ci == NULL || ci->is_isa) | |
ec68c924 EC |
8958 | { |
8959 | switch (c) | |
8960 | { | |
8961 | case OPTION_MTUNE: | |
8962 | as_fatal (_("invalid architecture -mtune=%s"), arg); | |
8963 | break; | |
8964 | case OPTION_MARCH: | |
8965 | as_fatal (_("invalid architecture -march=%s"), arg); | |
8966 | break; | |
8967 | case OPTION_MCPU: | |
8968 | as_fatal (_("invalid architecture -mcpu=%s"), arg); | |
8969 | break; | |
8970 | } | |
8971 | } | |
e7af610e | 8972 | else |
ec68c924 EC |
8973 | cpu = ci->cpu; |
8974 | } | |
8975 | ||
8976 | switch (c) | |
8977 | { | |
8978 | case OPTION_MTUNE: | |
6dce9e24 TS |
8979 | if (mips_tune != CPU_UNKNOWN && mips_tune != cpu) |
8980 | as_warn(_("A different -mtune= was already specified, is now " | |
8981 | "-mtune=%s"), arg); | |
ec68c924 EC |
8982 | mips_tune = cpu; |
8983 | break; | |
8984 | case OPTION_MARCH: | |
6dce9e24 TS |
8985 | if (mips_arch != CPU_UNKNOWN && mips_arch != cpu) |
8986 | as_warn(_("A different -march= was already specified, is now " | |
8987 | "-march=%s"), arg); | |
ec68c924 EC |
8988 | mips_arch = cpu; |
8989 | break; | |
8990 | case OPTION_MCPU: | |
6dce9e24 TS |
8991 | if (mips_cpu != CPU_UNKNOWN && mips_cpu != cpu) |
8992 | as_warn(_("A different -mcpu= was already specified, is now " | |
8993 | "-mcpu=%s"), arg); | |
ec68c924 | 8994 | mips_cpu = cpu; |
252b5132 RH |
8995 | } |
8996 | } | |
8997 | break; | |
8998 | ||
8999 | case OPTION_M4650: | |
6dce9e24 TS |
9000 | if ((mips_arch != CPU_UNKNOWN && mips_arch != CPU_R4650) |
9001 | || (mips_tune != CPU_UNKNOWN && mips_tune != CPU_R4650)) | |
9002 | as_warn(_("A different -march= or -mtune= was already specified, " | |
9003 | "is now -m4650")); | |
ec68c924 EC |
9004 | mips_arch = CPU_R4650; |
9005 | mips_tune = CPU_R4650; | |
252b5132 RH |
9006 | break; |
9007 | ||
9008 | case OPTION_NO_M4650: | |
9009 | break; | |
9010 | ||
9011 | case OPTION_M4010: | |
6dce9e24 TS |
9012 | if ((mips_arch != CPU_UNKNOWN && mips_arch != CPU_R4010) |
9013 | || (mips_tune != CPU_UNKNOWN && mips_tune != CPU_R4010)) | |
9014 | as_warn(_("A different -march= or -mtune= was already specified, " | |
9015 | "is now -m4010")); | |
ec68c924 EC |
9016 | mips_arch = CPU_R4010; |
9017 | mips_tune = CPU_R4010; | |
252b5132 RH |
9018 | break; |
9019 | ||
9020 | case OPTION_NO_M4010: | |
9021 | break; | |
9022 | ||
9023 | case OPTION_M4100: | |
6dce9e24 TS |
9024 | if ((mips_arch != CPU_UNKNOWN && mips_arch != CPU_VR4100) |
9025 | || (mips_tune != CPU_UNKNOWN && mips_tune != CPU_VR4100)) | |
9026 | as_warn(_("A different -march= or -mtune= was already specified, " | |
9027 | "is now -m4100")); | |
ec68c924 EC |
9028 | mips_arch = CPU_VR4100; |
9029 | mips_tune = CPU_VR4100; | |
252b5132 RH |
9030 | break; |
9031 | ||
9032 | case OPTION_NO_M4100: | |
9033 | break; | |
9034 | ||
252b5132 | 9035 | case OPTION_M3900: |
6dce9e24 TS |
9036 | if ((mips_arch != CPU_UNKNOWN && mips_arch != CPU_R3900) |
9037 | || (mips_tune != CPU_UNKNOWN && mips_tune != CPU_R3900)) | |
9038 | as_warn(_("A different -march= or -mtune= was already specified, " | |
9039 | "is now -m3900")); | |
ec68c924 EC |
9040 | mips_arch = CPU_R3900; |
9041 | mips_tune = CPU_R3900; | |
252b5132 | 9042 | break; |
bdaaa2e1 | 9043 | |
252b5132 RH |
9044 | case OPTION_NO_M3900: |
9045 | break; | |
9046 | ||
9047 | case OPTION_MIPS16: | |
9048 | mips_opts.mips16 = 1; | |
9049 | mips_no_prev_insn (false); | |
9050 | break; | |
9051 | ||
9052 | case OPTION_NO_MIPS16: | |
9053 | mips_opts.mips16 = 0; | |
9054 | mips_no_prev_insn (false); | |
9055 | break; | |
9056 | ||
9057 | case OPTION_MEMBEDDED_PIC: | |
9058 | mips_pic = EMBEDDED_PIC; | |
9059 | if (USE_GLOBAL_POINTER_OPT && g_switch_seen) | |
9060 | { | |
9061 | as_bad (_("-G may not be used with embedded PIC code")); | |
9062 | return 0; | |
9063 | } | |
9064 | g_switch_value = 0x7fffffff; | |
9065 | break; | |
9066 | ||
0f074f60 | 9067 | #ifdef OBJ_ELF |
252b5132 RH |
9068 | /* When generating ELF code, we permit -KPIC and -call_shared to |
9069 | select SVR4_PIC, and -non_shared to select no PIC. This is | |
9070 | intended to be compatible with Irix 5. */ | |
9071 | case OPTION_CALL_SHARED: | |
9072 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
9073 | { | |
9074 | as_bad (_("-call_shared is supported only for ELF format")); | |
9075 | return 0; | |
9076 | } | |
9077 | mips_pic = SVR4_PIC; | |
9078 | if (g_switch_seen && g_switch_value != 0) | |
9079 | { | |
9080 | as_bad (_("-G may not be used with SVR4 PIC code")); | |
9081 | return 0; | |
9082 | } | |
9083 | g_switch_value = 0; | |
9084 | break; | |
9085 | ||
9086 | case OPTION_NON_SHARED: | |
9087 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
9088 | { | |
9089 | as_bad (_("-non_shared is supported only for ELF format")); | |
9090 | return 0; | |
9091 | } | |
9092 | mips_pic = NO_PIC; | |
9093 | break; | |
9094 | ||
9095 | /* The -xgot option tells the assembler to use 32 offsets when | |
9096 | accessing the got in SVR4_PIC mode. It is for Irix | |
9097 | compatibility. */ | |
9098 | case OPTION_XGOT: | |
9099 | mips_big_got = 1; | |
9100 | break; | |
0f074f60 | 9101 | #endif /* OBJ_ELF */ |
252b5132 RH |
9102 | |
9103 | case 'G': | |
9104 | if (! USE_GLOBAL_POINTER_OPT) | |
9105 | { | |
9106 | as_bad (_("-G is not supported for this configuration")); | |
9107 | return 0; | |
9108 | } | |
9109 | else if (mips_pic == SVR4_PIC || mips_pic == EMBEDDED_PIC) | |
9110 | { | |
9111 | as_bad (_("-G may not be used with SVR4 or embedded PIC code")); | |
9112 | return 0; | |
9113 | } | |
9114 | else | |
9115 | g_switch_value = atoi (arg); | |
9116 | g_switch_seen = 1; | |
9117 | break; | |
9118 | ||
0f074f60 | 9119 | #ifdef OBJ_ELF |
252b5132 RH |
9120 | /* The -32 and -64 options tell the assembler to output the 32 |
9121 | bit or the 64 bit MIPS ELF format. */ | |
9122 | case OPTION_32: | |
9123 | mips_64 = 0; | |
9124 | break; | |
9125 | ||
9126 | case OPTION_64: | |
9127 | { | |
9128 | const char **list, **l; | |
9129 | ||
9130 | list = bfd_target_list (); | |
9131 | for (l = list; *l != NULL; l++) | |
9132 | if (strcmp (*l, "elf64-bigmips") == 0 | |
f4ddc5e6 L |
9133 | || strcmp (*l, "elf64-littlemips") == 0 |
9134 | || strcmp (*l, "elf64-tradbigmips") == 0 | |
9135 | || strcmp (*l, "elf64-tradlittlemips") == 0) | |
252b5132 RH |
9136 | break; |
9137 | if (*l == NULL) | |
9138 | as_fatal (_("No compiled in support for 64 bit object file format")); | |
9139 | free (list); | |
9140 | mips_64 = 1; | |
9141 | } | |
9142 | break; | |
0f074f60 | 9143 | #endif /* OBJ_ELF */ |
252b5132 | 9144 | |
c97ef257 AH |
9145 | case OPTION_GP32: |
9146 | mips_gp32 = 1; | |
9147 | mips_64 = 0; | |
9148 | ||
9149 | /* We deliberately don't allow "-gp32" to set the MIPS_32BITMODE | |
9150 | flag in object files because to do so would make it | |
9151 | impossible to link with libraries compiled without "-gp32". | |
bdaaa2e1 | 9152 | This is unnecessarily restrictive. |
c97ef257 AH |
9153 | |
9154 | We could solve this problem by adding "-gp32" multilibs to | |
9155 | gcc, but to set this flag before gcc is built with such | |
bdaaa2e1 | 9156 | multilibs will break too many systems. */ |
c97ef257 | 9157 | |
beae10d5 KH |
9158 | #if 0 |
9159 | mips_32bitmode = 1; | |
9160 | #endif | |
c97ef257 AH |
9161 | break; |
9162 | ||
9163 | case OPTION_GP64: | |
9164 | mips_gp32 = 0; | |
9165 | mips_64 = 1; | |
beae10d5 KH |
9166 | #if 0 |
9167 | mips_32bitmode = 0; | |
9168 | #endif | |
c97ef257 | 9169 | break; |
252b5132 | 9170 | |
ca4e0257 RS |
9171 | case OPTION_FP32: |
9172 | mips_fp32 = 1; | |
9173 | break; | |
9174 | ||
252b5132 | 9175 | case OPTION_MABI: |
beae10d5 KH |
9176 | if (strcmp (arg, "32") == 0 |
9177 | || strcmp (arg, "n32") == 0 | |
9178 | || strcmp (arg, "64") == 0 | |
9179 | || strcmp (arg, "o64") == 0 | |
9180 | || strcmp (arg, "eabi") == 0) | |
ca4e0257 RS |
9181 | { |
9182 | mips_abi_string = arg; | |
9183 | mips_32bit_abi = (strcmp (arg, "32") == 0); | |
9184 | } | |
252b5132 RH |
9185 | break; |
9186 | ||
6b76fefe CM |
9187 | case OPTION_M7000_HILO_FIX: |
9188 | mips_7000_hilo_fix = true; | |
9189 | break; | |
9190 | ||
9191 | case OPTION_NO_M7000_HILO_FIX: | |
9192 | mips_7000_hilo_fix = false; | |
9193 | break; | |
9194 | ||
252b5132 RH |
9195 | default: |
9196 | return 0; | |
9197 | } | |
9198 | ||
9199 | return 1; | |
9200 | } | |
9201 | ||
252b5132 RH |
9202 | static void |
9203 | show (stream, string, col_p, first_p) | |
9204 | FILE *stream; | |
9205 | char *string; | |
9206 | int *col_p; | |
9207 | int *first_p; | |
9208 | { | |
9209 | if (*first_p) | |
9210 | { | |
9211 | fprintf (stream, "%24s", ""); | |
9212 | *col_p = 24; | |
9213 | } | |
9214 | else | |
9215 | { | |
9216 | fprintf (stream, ", "); | |
9217 | *col_p += 2; | |
9218 | } | |
9219 | ||
9220 | if (*col_p + strlen (string) > 72) | |
9221 | { | |
9222 | fprintf (stream, "\n%24s", ""); | |
9223 | *col_p = 24; | |
9224 | } | |
9225 | ||
9226 | fprintf (stream, "%s", string); | |
9227 | *col_p += strlen (string); | |
9228 | ||
9229 | *first_p = 0; | |
9230 | } | |
9231 | ||
252b5132 RH |
9232 | void |
9233 | md_show_usage (stream) | |
9234 | FILE *stream; | |
9235 | { | |
9236 | int column, first; | |
9237 | ||
beae10d5 | 9238 | fprintf (stream, _("\ |
252b5132 RH |
9239 | MIPS options:\n\ |
9240 | -membedded-pic generate embedded position independent code\n\ | |
9241 | -EB generate big endian output\n\ | |
9242 | -EL generate little endian output\n\ | |
9a41af64 | 9243 | -g, -g2 do not remove unneeded NOPs or swap branches\n\ |
252b5132 RH |
9244 | -G NUM allow referencing objects up to NUM bytes\n\ |
9245 | implicitly with the gp register [default 8]\n")); | |
beae10d5 | 9246 | fprintf (stream, _("\ |
252b5132 RH |
9247 | -mips1 generate MIPS ISA I instructions\n\ |
9248 | -mips2 generate MIPS ISA II instructions\n\ | |
9249 | -mips3 generate MIPS ISA III instructions\n\ | |
9250 | -mips4 generate MIPS ISA IV instructions\n\ | |
84ea6cf2 | 9251 | -mips5 generate MIPS ISA V instructions\n\ |
e7af610e | 9252 | -mips32 generate MIPS32 ISA instructions\n\ |
84ea6cf2 | 9253 | -mips64 generate MIPS64 ISA instructions\n\ |
ec68c924 | 9254 | -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n")); |
252b5132 RH |
9255 | |
9256 | first = 1; | |
9257 | ||
9258 | show (stream, "2000", &column, &first); | |
9259 | show (stream, "3000", &column, &first); | |
9260 | show (stream, "3900", &column, &first); | |
9261 | show (stream, "4000", &column, &first); | |
9262 | show (stream, "4010", &column, &first); | |
9263 | show (stream, "4100", &column, &first); | |
9264 | show (stream, "4111", &column, &first); | |
9265 | show (stream, "4300", &column, &first); | |
9266 | show (stream, "4400", &column, &first); | |
9267 | show (stream, "4600", &column, &first); | |
9268 | show (stream, "4650", &column, &first); | |
9269 | show (stream, "5000", &column, &first); | |
18ae5d72 EC |
9270 | show (stream, "5200", &column, &first); |
9271 | show (stream, "5230", &column, &first); | |
9272 | show (stream, "5231", &column, &first); | |
9273 | show (stream, "5261", &column, &first); | |
9274 | show (stream, "5721", &column, &first); | |
252b5132 RH |
9275 | show (stream, "6000", &column, &first); |
9276 | show (stream, "8000", &column, &first); | |
9277 | show (stream, "10000", &column, &first); | |
d1cf510e | 9278 | show (stream, "12000", &column, &first); |
e7af610e | 9279 | show (stream, "mips32-4k", &column, &first); |
c6c98b38 | 9280 | show (stream, "sb-1", &column, &first); |
252b5132 RH |
9281 | fputc ('\n', stream); |
9282 | ||
9283 | fprintf (stream, _("\ | |
ec68c924 | 9284 | -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\ |
252b5132 RH |
9285 | -no-mCPU don't generate code specific to CPU.\n\ |
9286 | For -mCPU and -no-mCPU, CPU must be one of:\n")); | |
9287 | ||
9288 | first = 1; | |
9289 | ||
9290 | show (stream, "3900", &column, &first); | |
9291 | show (stream, "4010", &column, &first); | |
9292 | show (stream, "4100", &column, &first); | |
9293 | show (stream, "4650", &column, &first); | |
9294 | fputc ('\n', stream); | |
9295 | ||
beae10d5 | 9296 | fprintf (stream, _("\ |
252b5132 RH |
9297 | -mips16 generate mips16 instructions\n\ |
9298 | -no-mips16 do not generate mips16 instructions\n")); | |
beae10d5 | 9299 | fprintf (stream, _("\ |
ca4e0257 RS |
9300 | -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\ |
9301 | -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\ | |
252b5132 RH |
9302 | -O0 remove unneeded NOPs, do not swap branches\n\ |
9303 | -O remove unneeded NOPs and swap branches\n\ | |
63486801 | 9304 | -n warn about NOPs generated from macros\n\ |
119d663a | 9305 | --[no-]construct-floats [dis]allow floating point values to be constructed\n\ |
252b5132 RH |
9306 | --trap, --no-break trap exception on div by 0 and mult overflow\n\ |
9307 | --break, --no-trap break exception on div by 0 and mult overflow\n")); | |
9308 | #ifdef OBJ_ELF | |
beae10d5 | 9309 | fprintf (stream, _("\ |
252b5132 RH |
9310 | -KPIC, -call_shared generate SVR4 position independent code\n\ |
9311 | -non_shared do not generate position independent code\n\ | |
9312 | -xgot assume a 32 bit GOT\n\ | |
9313 | -32 create 32 bit object file (default)\n\ | |
9314 | -64 create 64 bit object file\n")); | |
9315 | #endif | |
9316 | } | |
9317 | \f | |
9318 | void | |
9319 | mips_init_after_args () | |
9320 | { | |
9321 | /* initialize opcodes */ | |
9322 | bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes; | |
beae10d5 | 9323 | mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes; |
252b5132 RH |
9324 | } |
9325 | ||
9326 | long | |
9327 | md_pcrel_from (fixP) | |
9328 | fixS *fixP; | |
9329 | { | |
9330 | if (OUTPUT_FLAVOR != bfd_target_aout_flavour | |
9331 | && fixP->fx_addsy != (symbolS *) NULL | |
9332 | && ! S_IS_DEFINED (fixP->fx_addsy)) | |
9333 | { | |
9334 | /* This makes a branch to an undefined symbol be a branch to the | |
9335 | current location. */ | |
9336 | return 4; | |
9337 | } | |
9338 | ||
9339 | /* return the address of the delay slot */ | |
9340 | return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address; | |
9341 | } | |
9342 | ||
9343 | /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a | |
9344 | reloc for a cons. We could use the definition there, except that | |
9345 | we want to handle 64 bit relocs specially. */ | |
9346 | ||
9347 | void | |
9348 | cons_fix_new_mips (frag, where, nbytes, exp) | |
43841e91 | 9349 | fragS *frag ATTRIBUTE_UNUSED; |
252b5132 RH |
9350 | int where; |
9351 | unsigned int nbytes; | |
9352 | expressionS *exp; | |
9353 | { | |
9354 | #ifndef OBJ_ELF | |
9355 | /* If we are assembling in 32 bit mode, turn an 8 byte reloc into a | |
9356 | 4 byte reloc. */ | |
9357 | if (nbytes == 8 && ! mips_64) | |
9358 | { | |
9359 | if (target_big_endian) | |
9360 | where += 4; | |
9361 | nbytes = 4; | |
9362 | } | |
9363 | #endif | |
9364 | ||
9365 | if (nbytes != 2 && nbytes != 4 && nbytes != 8) | |
9366 | as_bad (_("Unsupported reloc size %d"), nbytes); | |
9367 | ||
9368 | fix_new_exp (frag_now, where, (int) nbytes, exp, 0, | |
9369 | (nbytes == 2 | |
9370 | ? BFD_RELOC_16 | |
9371 | : (nbytes == 4 ? BFD_RELOC_32 : BFD_RELOC_64))); | |
9372 | } | |
9373 | ||
9374 | /* This is called before the symbol table is processed. In order to | |
9375 | work with gcc when using mips-tfile, we must keep all local labels. | |
9376 | However, in other cases, we want to discard them. If we were | |
9377 | called with -g, but we didn't see any debugging information, it may | |
9378 | mean that gcc is smuggling debugging information through to | |
9379 | mips-tfile, in which case we must generate all local labels. */ | |
9380 | ||
9381 | void | |
9382 | mips_frob_file_before_adjust () | |
9383 | { | |
9384 | #ifndef NO_ECOFF_DEBUGGING | |
9385 | if (ECOFF_DEBUGGING | |
9386 | && mips_debug != 0 | |
9387 | && ! ecoff_debugging_seen) | |
9388 | flag_keep_locals = 1; | |
9389 | #endif | |
9390 | } | |
9391 | ||
9392 | /* Sort any unmatched HI16_S relocs so that they immediately precede | |
9393 | the corresponding LO reloc. This is called before md_apply_fix and | |
9394 | tc_gen_reloc. Unmatched HI16_S relocs can only be generated by | |
9395 | explicit use of the %hi modifier. */ | |
9396 | ||
9397 | void | |
9398 | mips_frob_file () | |
9399 | { | |
9400 | struct mips_hi_fixup *l; | |
9401 | ||
9402 | for (l = mips_hi_fixup_list; l != NULL; l = l->next) | |
9403 | { | |
9404 | segment_info_type *seginfo; | |
9405 | int pass; | |
9406 | ||
9407 | assert (l->fixp->fx_r_type == BFD_RELOC_HI16_S); | |
9408 | ||
9409 | /* Check quickly whether the next fixup happens to be a matching | |
9410 | %lo. */ | |
9411 | if (l->fixp->fx_next != NULL | |
9412 | && l->fixp->fx_next->fx_r_type == BFD_RELOC_LO16 | |
9413 | && l->fixp->fx_addsy == l->fixp->fx_next->fx_addsy | |
9414 | && l->fixp->fx_offset == l->fixp->fx_next->fx_offset) | |
9415 | continue; | |
9416 | ||
9417 | /* Look through the fixups for this segment for a matching %lo. | |
9418 | When we find one, move the %hi just in front of it. We do | |
9419 | this in two passes. In the first pass, we try to find a | |
9420 | unique %lo. In the second pass, we permit multiple %hi | |
9421 | relocs for a single %lo (this is a GNU extension). */ | |
9422 | seginfo = seg_info (l->seg); | |
9423 | for (pass = 0; pass < 2; pass++) | |
9424 | { | |
9425 | fixS *f, *prev; | |
9426 | ||
9427 | prev = NULL; | |
9428 | for (f = seginfo->fix_root; f != NULL; f = f->fx_next) | |
9429 | { | |
9430 | /* Check whether this is a %lo fixup which matches l->fixp. */ | |
9431 | if (f->fx_r_type == BFD_RELOC_LO16 | |
9432 | && f->fx_addsy == l->fixp->fx_addsy | |
9433 | && f->fx_offset == l->fixp->fx_offset | |
9434 | && (pass == 1 | |
9435 | || prev == NULL | |
9436 | || prev->fx_r_type != BFD_RELOC_HI16_S | |
9437 | || prev->fx_addsy != f->fx_addsy | |
9438 | || prev->fx_offset != f->fx_offset)) | |
9439 | { | |
9440 | fixS **pf; | |
9441 | ||
9442 | /* Move l->fixp before f. */ | |
9443 | for (pf = &seginfo->fix_root; | |
9444 | *pf != l->fixp; | |
9445 | pf = &(*pf)->fx_next) | |
9446 | assert (*pf != NULL); | |
9447 | ||
9448 | *pf = l->fixp->fx_next; | |
9449 | ||
9450 | l->fixp->fx_next = f; | |
9451 | if (prev == NULL) | |
9452 | seginfo->fix_root = l->fixp; | |
9453 | else | |
9454 | prev->fx_next = l->fixp; | |
9455 | ||
9456 | break; | |
9457 | } | |
9458 | ||
9459 | prev = f; | |
9460 | } | |
9461 | ||
9462 | if (f != NULL) | |
9463 | break; | |
9464 | ||
9465 | #if 0 /* GCC code motion plus incomplete dead code elimination | |
9466 | can leave a %hi without a %lo. */ | |
9467 | if (pass == 1) | |
9468 | as_warn_where (l->fixp->fx_file, l->fixp->fx_line, | |
9469 | _("Unmatched %%hi reloc")); | |
9470 | #endif | |
9471 | } | |
9472 | } | |
9473 | } | |
9474 | ||
9475 | /* When generating embedded PIC code we need to use a special | |
9476 | relocation to represent the difference of two symbols in the .text | |
9477 | section (switch tables use a difference of this sort). See | |
9478 | include/coff/mips.h for details. This macro checks whether this | |
9479 | fixup requires the special reloc. */ | |
9480 | #define SWITCH_TABLE(fixp) \ | |
9481 | ((fixp)->fx_r_type == BFD_RELOC_32 \ | |
bb2d6cd7 | 9482 | && OUTPUT_FLAVOR != bfd_target_elf_flavour \ |
252b5132 RH |
9483 | && (fixp)->fx_addsy != NULL \ |
9484 | && (fixp)->fx_subsy != NULL \ | |
9485 | && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \ | |
9486 | && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section) | |
9487 | ||
9488 | /* When generating embedded PIC code we must keep all PC relative | |
9489 | relocations, in case the linker has to relax a call. We also need | |
9490 | to keep relocations for switch table entries. */ | |
9491 | ||
252b5132 RH |
9492 | int |
9493 | mips_force_relocation (fixp) | |
9494 | fixS *fixp; | |
9495 | { | |
9496 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT | |
9497 | || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
9498 | return 1; | |
9499 | ||
9500 | return (mips_pic == EMBEDDED_PIC | |
9501 | && (fixp->fx_pcrel | |
9502 | || SWITCH_TABLE (fixp) | |
9503 | || fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S | |
9504 | || fixp->fx_r_type == BFD_RELOC_PCREL_LO16)); | |
9505 | } | |
9506 | ||
9507 | /* Apply a fixup to the object file. */ | |
9508 | ||
9509 | int | |
9510 | md_apply_fix (fixP, valueP) | |
9511 | fixS *fixP; | |
9512 | valueT *valueP; | |
9513 | { | |
9514 | unsigned char *buf; | |
98aa84af AM |
9515 | long insn; |
9516 | valueT value; | |
252b5132 RH |
9517 | |
9518 | assert (fixP->fx_size == 4 | |
9519 | || fixP->fx_r_type == BFD_RELOC_16 | |
9520 | || fixP->fx_r_type == BFD_RELOC_64 | |
9521 | || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT | |
9522 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY); | |
9523 | ||
9524 | value = *valueP; | |
9525 | ||
9526 | /* If we aren't adjusting this fixup to be against the section | |
9527 | symbol, we need to adjust the value. */ | |
9528 | #ifdef OBJ_ELF | |
9529 | if (fixP->fx_addsy != NULL && OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
bb2d6cd7 | 9530 | { |
98aa84af | 9531 | if (S_GET_OTHER (fixP->fx_addsy) == STO_MIPS16 |
ea4ff978 L |
9532 | || ((S_IS_WEAK (fixP->fx_addsy) |
9533 | || S_IS_EXTERN (fixP->fx_addsy)) | |
9534 | && !S_IS_COMMON (fixP->fx_addsy)) | |
98aa84af AM |
9535 | || (symbol_used_in_reloc_p (fixP->fx_addsy) |
9536 | && (((bfd_get_section_flags (stdoutput, | |
9537 | S_GET_SEGMENT (fixP->fx_addsy)) | |
9538 | & SEC_LINK_ONCE) != 0) | |
9539 | || !strncmp (segment_name (S_GET_SEGMENT (fixP->fx_addsy)), | |
9540 | ".gnu.linkonce", | |
9541 | sizeof (".gnu.linkonce") - 1)))) | |
252b5132 | 9542 | |
98aa84af AM |
9543 | { |
9544 | valueT symval = S_GET_VALUE (fixP->fx_addsy); | |
9545 | value -= symval; | |
236bd878 RS |
9546 | if (value != 0 |
9547 | && ! fixP->fx_pcrel | |
9548 | && fixP->fx_r_type != BFD_RELOC_MIPS_GPREL) | |
98aa84af AM |
9549 | { |
9550 | /* In this case, the bfd_install_relocation routine will | |
9551 | incorrectly add the symbol value back in. We just want | |
7461da6e | 9552 | the addend to appear in the object file. */ |
98aa84af | 9553 | value -= symval; |
7461da6e RS |
9554 | |
9555 | /* Make sure the addend is still non-zero. If it became zero | |
9556 | after the last operation, set it to a spurious value and | |
9557 | subtract the same value from the object file's contents. */ | |
9558 | if (value == 0) | |
9559 | { | |
9560 | value = 8; | |
9561 | ||
9562 | /* The in-place addends for LO16 relocations are signed; | |
9563 | leave the matching HI16 in-place addends as zero. */ | |
9564 | if (fixP->fx_r_type != BFD_RELOC_HI16_S) | |
9565 | { | |
9566 | reloc_howto_type *howto; | |
9567 | bfd_vma contents, mask, field; | |
9568 | ||
9569 | howto = bfd_reloc_type_lookup (stdoutput, | |
9570 | fixP->fx_r_type); | |
9571 | ||
9572 | contents = bfd_get_bits (fixP->fx_frag->fr_literal | |
9573 | + fixP->fx_where, | |
9574 | fixP->fx_size * 8, | |
9575 | target_big_endian); | |
9576 | ||
9577 | /* MASK has bits set where the relocation should go. | |
9578 | FIELD is -value, shifted into the appropriate place | |
9579 | for this relocation. */ | |
9580 | mask = 1 << (howto->bitsize - 1); | |
9581 | mask = (((mask - 1) << 1) | 1) << howto->bitpos; | |
9582 | field = (-value >> howto->rightshift) << howto->bitpos; | |
9583 | ||
9584 | bfd_put_bits ((field & mask) | (contents & ~mask), | |
9585 | fixP->fx_frag->fr_literal + fixP->fx_where, | |
9586 | fixP->fx_size * 8, | |
9587 | target_big_endian); | |
9588 | } | |
9589 | } | |
98aa84af AM |
9590 | } |
9591 | } | |
252b5132 | 9592 | |
bb2d6cd7 GK |
9593 | /* This code was generated using trial and error and so is |
9594 | fragile and not trustworthy. If you change it, you should | |
9595 | rerun the elf-rel, elf-rel2, and empic testcases and ensure | |
9596 | they still pass. */ | |
9597 | if (fixP->fx_pcrel || fixP->fx_subsy != NULL) | |
9598 | { | |
9599 | value += fixP->fx_frag->fr_address + fixP->fx_where; | |
9600 | ||
9601 | /* BFD's REL handling, for MIPS, is _very_ weird. | |
9602 | This gives the right results, but it can't possibly | |
9603 | be the way things are supposed to work. */ | |
9604 | if (fixP->fx_r_type != BFD_RELOC_16_PCREL_S2 | |
9605 | || S_GET_SEGMENT (fixP->fx_addsy) != undefined_section) | |
9606 | value += fixP->fx_frag->fr_address + fixP->fx_where; | |
9607 | } | |
9608 | } | |
9609 | #endif | |
252b5132 RH |
9610 | |
9611 | fixP->fx_addnumber = value; /* Remember value for tc_gen_reloc */ | |
9612 | ||
9613 | if (fixP->fx_addsy == NULL && ! fixP->fx_pcrel) | |
9614 | fixP->fx_done = 1; | |
9615 | ||
9616 | switch (fixP->fx_r_type) | |
9617 | { | |
9618 | case BFD_RELOC_MIPS_JMP: | |
9619 | case BFD_RELOC_HI16: | |
9620 | case BFD_RELOC_HI16_S: | |
9621 | case BFD_RELOC_MIPS_GPREL: | |
9622 | case BFD_RELOC_MIPS_LITERAL: | |
9623 | case BFD_RELOC_MIPS_CALL16: | |
9624 | case BFD_RELOC_MIPS_GOT16: | |
9625 | case BFD_RELOC_MIPS_GPREL32: | |
9626 | case BFD_RELOC_MIPS_GOT_HI16: | |
9627 | case BFD_RELOC_MIPS_GOT_LO16: | |
9628 | case BFD_RELOC_MIPS_CALL_HI16: | |
9629 | case BFD_RELOC_MIPS_CALL_LO16: | |
9630 | case BFD_RELOC_MIPS16_GPREL: | |
9631 | if (fixP->fx_pcrel) | |
9632 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
9633 | _("Invalid PC relative reloc")); | |
9634 | /* Nothing needed to do. The value comes from the reloc entry */ | |
9635 | break; | |
9636 | ||
9637 | case BFD_RELOC_MIPS16_JMP: | |
9638 | /* We currently always generate a reloc against a symbol, which | |
9639 | means that we don't want an addend even if the symbol is | |
9640 | defined. */ | |
9641 | fixP->fx_addnumber = 0; | |
9642 | break; | |
9643 | ||
9644 | case BFD_RELOC_PCREL_HI16_S: | |
9645 | /* The addend for this is tricky if it is internal, so we just | |
9646 | do everything here rather than in bfd_install_relocation. */ | |
bdaaa2e1 | 9647 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour |
bb2d6cd7 GK |
9648 | && !fixP->fx_done |
9649 | && value != 0) | |
9650 | break; | |
9651 | if (fixP->fx_addsy | |
9652 | && (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_SECTION_SYM) == 0) | |
252b5132 RH |
9653 | { |
9654 | /* For an external symbol adjust by the address to make it | |
9655 | pcrel_offset. We use the address of the RELLO reloc | |
9656 | which follows this one. */ | |
9657 | value += (fixP->fx_next->fx_frag->fr_address | |
9658 | + fixP->fx_next->fx_where); | |
9659 | } | |
9660 | if (value & 0x8000) | |
9661 | value += 0x10000; | |
9662 | value >>= 16; | |
9663 | buf = (unsigned char *) fixP->fx_frag->fr_literal + fixP->fx_where; | |
9664 | if (target_big_endian) | |
9665 | buf += 2; | |
9666 | md_number_to_chars (buf, value, 2); | |
9667 | break; | |
9668 | ||
9669 | case BFD_RELOC_PCREL_LO16: | |
9670 | /* The addend for this is tricky if it is internal, so we just | |
9671 | do everything here rather than in bfd_install_relocation. */ | |
bdaaa2e1 | 9672 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour |
bb2d6cd7 GK |
9673 | && !fixP->fx_done |
9674 | && value != 0) | |
9675 | break; | |
9676 | if (fixP->fx_addsy | |
9677 | && (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_SECTION_SYM) == 0) | |
252b5132 RH |
9678 | value += fixP->fx_frag->fr_address + fixP->fx_where; |
9679 | buf = (unsigned char *) fixP->fx_frag->fr_literal + fixP->fx_where; | |
9680 | if (target_big_endian) | |
9681 | buf += 2; | |
9682 | md_number_to_chars (buf, value, 2); | |
9683 | break; | |
9684 | ||
9685 | case BFD_RELOC_64: | |
9686 | /* This is handled like BFD_RELOC_32, but we output a sign | |
9687 | extended value if we are only 32 bits. */ | |
9688 | if (fixP->fx_done | |
9689 | || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP))) | |
9690 | { | |
9691 | if (8 <= sizeof (valueT)) | |
9692 | md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where, | |
9693 | value, 8); | |
9694 | else | |
9695 | { | |
9696 | long w1, w2; | |
9697 | long hiv; | |
9698 | ||
9699 | w1 = w2 = fixP->fx_where; | |
9700 | if (target_big_endian) | |
9701 | w1 += 4; | |
9702 | else | |
9703 | w2 += 4; | |
9704 | md_number_to_chars (fixP->fx_frag->fr_literal + w1, value, 4); | |
9705 | if ((value & 0x80000000) != 0) | |
9706 | hiv = 0xffffffff; | |
9707 | else | |
9708 | hiv = 0; | |
9709 | md_number_to_chars (fixP->fx_frag->fr_literal + w2, hiv, 4); | |
9710 | } | |
9711 | } | |
9712 | break; | |
9713 | ||
056350c6 | 9714 | case BFD_RELOC_RVA: |
252b5132 RH |
9715 | case BFD_RELOC_32: |
9716 | /* If we are deleting this reloc entry, we must fill in the | |
9717 | value now. This can happen if we have a .word which is not | |
9718 | resolved when it appears but is later defined. We also need | |
9719 | to fill in the value if this is an embedded PIC switch table | |
9720 | entry. */ | |
9721 | if (fixP->fx_done | |
9722 | || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP))) | |
9723 | md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where, | |
9724 | value, 4); | |
9725 | break; | |
9726 | ||
9727 | case BFD_RELOC_16: | |
9728 | /* If we are deleting this reloc entry, we must fill in the | |
9729 | value now. */ | |
9730 | assert (fixP->fx_size == 2); | |
9731 | if (fixP->fx_done) | |
9732 | md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where, | |
9733 | value, 2); | |
9734 | break; | |
9735 | ||
9736 | case BFD_RELOC_LO16: | |
9737 | /* When handling an embedded PIC switch statement, we can wind | |
9738 | up deleting a LO16 reloc. See the 'o' case in mips_ip. */ | |
9739 | if (fixP->fx_done) | |
9740 | { | |
98aa84af | 9741 | if (value + 0x8000 > 0xffff) |
252b5132 RH |
9742 | as_bad_where (fixP->fx_file, fixP->fx_line, |
9743 | _("relocation overflow")); | |
9744 | buf = (unsigned char *) fixP->fx_frag->fr_literal + fixP->fx_where; | |
9745 | if (target_big_endian) | |
9746 | buf += 2; | |
9747 | md_number_to_chars (buf, value, 2); | |
9748 | } | |
9749 | break; | |
9750 | ||
9751 | case BFD_RELOC_16_PCREL_S2: | |
9752 | /* | |
9753 | * We need to save the bits in the instruction since fixup_segment() | |
9754 | * might be deleting the relocation entry (i.e., a branch within | |
9755 | * the current segment). | |
9756 | */ | |
9757 | if ((value & 0x3) != 0) | |
9758 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
98aa84af | 9759 | _("Branch to odd address (%lx)"), (long) value); |
bb2d6cd7 GK |
9760 | |
9761 | if (!fixP->fx_done && value != 0) | |
9762 | break; | |
9763 | /* If 'value' is zero, the remaining reloc code won't actually | |
9764 | do the store, so it must be done here. This is probably | |
9765 | a bug somewhere. */ | |
9766 | if (!fixP->fx_done) | |
9767 | value -= fixP->fx_frag->fr_address + fixP->fx_where; | |
bdaaa2e1 | 9768 | |
98aa84af | 9769 | value = (offsetT) value >> 2; |
252b5132 RH |
9770 | |
9771 | /* update old instruction data */ | |
9772 | buf = (unsigned char *) (fixP->fx_where + fixP->fx_frag->fr_literal); | |
9773 | if (target_big_endian) | |
9774 | insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3]; | |
9775 | else | |
9776 | insn = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0]; | |
9777 | ||
98aa84af | 9778 | if (value + 0x8000 <= 0xffff) |
252b5132 RH |
9779 | insn |= value & 0xffff; |
9780 | else | |
9781 | { | |
9782 | /* The branch offset is too large. If this is an | |
9783 | unconditional branch, and we are not generating PIC code, | |
9784 | we can convert it to an absolute jump instruction. */ | |
9785 | if (mips_pic == NO_PIC | |
9786 | && fixP->fx_done | |
9787 | && fixP->fx_frag->fr_address >= text_section->vma | |
9788 | && (fixP->fx_frag->fr_address | |
9789 | < text_section->vma + text_section->_raw_size) | |
9790 | && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */ | |
9791 | || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */ | |
9792 | || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */ | |
9793 | { | |
9794 | if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */ | |
9795 | insn = 0x0c000000; /* jal */ | |
9796 | else | |
9797 | insn = 0x08000000; /* j */ | |
9798 | fixP->fx_r_type = BFD_RELOC_MIPS_JMP; | |
9799 | fixP->fx_done = 0; | |
9800 | fixP->fx_addsy = section_symbol (text_section); | |
9801 | fixP->fx_addnumber = (value << 2) + md_pcrel_from (fixP); | |
9802 | } | |
9803 | else | |
9804 | { | |
9805 | /* FIXME. It would be possible in principle to handle | |
9806 | conditional branches which overflow. They could be | |
9807 | transformed into a branch around a jump. This would | |
9808 | require setting up variant frags for each different | |
9809 | branch type. The native MIPS assembler attempts to | |
9810 | handle these cases, but it appears to do it | |
9811 | incorrectly. */ | |
9812 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
9813 | _("Branch out of range")); | |
9814 | } | |
9815 | } | |
9816 | ||
9817 | md_number_to_chars ((char *) buf, (valueT) insn, 4); | |
9818 | break; | |
9819 | ||
9820 | case BFD_RELOC_VTABLE_INHERIT: | |
9821 | fixP->fx_done = 0; | |
9822 | if (fixP->fx_addsy | |
9823 | && !S_IS_DEFINED (fixP->fx_addsy) | |
9824 | && !S_IS_WEAK (fixP->fx_addsy)) | |
9825 | S_SET_WEAK (fixP->fx_addsy); | |
9826 | break; | |
9827 | ||
9828 | case BFD_RELOC_VTABLE_ENTRY: | |
9829 | fixP->fx_done = 0; | |
9830 | break; | |
9831 | ||
9832 | default: | |
9833 | internalError (); | |
9834 | } | |
9835 | ||
9836 | return 1; | |
9837 | } | |
9838 | ||
9839 | #if 0 | |
9840 | void | |
9841 | printInsn (oc) | |
9842 | unsigned long oc; | |
9843 | { | |
9844 | const struct mips_opcode *p; | |
9845 | int treg, sreg, dreg, shamt; | |
9846 | short imm; | |
9847 | const char *args; | |
9848 | int i; | |
9849 | ||
9850 | for (i = 0; i < NUMOPCODES; ++i) | |
9851 | { | |
9852 | p = &mips_opcodes[i]; | |
9853 | if (((oc & p->mask) == p->match) && (p->pinfo != INSN_MACRO)) | |
9854 | { | |
9855 | printf ("%08lx %s\t", oc, p->name); | |
9856 | treg = (oc >> 16) & 0x1f; | |
9857 | sreg = (oc >> 21) & 0x1f; | |
9858 | dreg = (oc >> 11) & 0x1f; | |
9859 | shamt = (oc >> 6) & 0x1f; | |
9860 | imm = oc; | |
9861 | for (args = p->args;; ++args) | |
9862 | { | |
9863 | switch (*args) | |
9864 | { | |
9865 | case '\0': | |
9866 | printf ("\n"); | |
9867 | break; | |
9868 | ||
9869 | case ',': | |
9870 | case '(': | |
9871 | case ')': | |
9872 | printf ("%c", *args); | |
9873 | continue; | |
9874 | ||
9875 | case 'r': | |
9876 | assert (treg == sreg); | |
9877 | printf ("$%d,$%d", treg, sreg); | |
9878 | continue; | |
9879 | ||
9880 | case 'd': | |
9881 | case 'G': | |
9882 | printf ("$%d", dreg); | |
9883 | continue; | |
9884 | ||
9885 | case 't': | |
9886 | case 'E': | |
9887 | printf ("$%d", treg); | |
9888 | continue; | |
9889 | ||
9890 | case 'k': | |
9891 | printf ("0x%x", treg); | |
9892 | continue; | |
9893 | ||
9894 | case 'b': | |
9895 | case 's': | |
9896 | printf ("$%d", sreg); | |
9897 | continue; | |
9898 | ||
9899 | case 'a': | |
9900 | printf ("0x%08lx", oc & 0x1ffffff); | |
9901 | continue; | |
9902 | ||
9903 | case 'i': | |
9904 | case 'j': | |
9905 | case 'o': | |
9906 | case 'u': | |
9907 | printf ("%d", imm); | |
9908 | continue; | |
9909 | ||
9910 | case '<': | |
9911 | case '>': | |
9912 | printf ("$%d", shamt); | |
9913 | continue; | |
9914 | ||
9915 | default: | |
9916 | internalError (); | |
9917 | } | |
9918 | break; | |
9919 | } | |
9920 | return; | |
9921 | } | |
9922 | } | |
9923 | printf (_("%08lx UNDEFINED\n"), oc); | |
9924 | } | |
9925 | #endif | |
9926 | ||
9927 | static symbolS * | |
9928 | get_symbol () | |
9929 | { | |
9930 | int c; | |
9931 | char *name; | |
9932 | symbolS *p; | |
9933 | ||
9934 | name = input_line_pointer; | |
9935 | c = get_symbol_end (); | |
9936 | p = (symbolS *) symbol_find_or_make (name); | |
9937 | *input_line_pointer = c; | |
9938 | return p; | |
9939 | } | |
9940 | ||
9941 | /* Align the current frag to a given power of two. The MIPS assembler | |
9942 | also automatically adjusts any preceding label. */ | |
9943 | ||
9944 | static void | |
9945 | mips_align (to, fill, label) | |
9946 | int to; | |
9947 | int fill; | |
9948 | symbolS *label; | |
9949 | { | |
9950 | mips_emit_delays (false); | |
9951 | frag_align (to, fill, 0); | |
9952 | record_alignment (now_seg, to); | |
9953 | if (label != NULL) | |
9954 | { | |
9955 | assert (S_GET_SEGMENT (label) == now_seg); | |
49309057 | 9956 | symbol_set_frag (label, frag_now); |
252b5132 RH |
9957 | S_SET_VALUE (label, (valueT) frag_now_fix ()); |
9958 | } | |
9959 | } | |
9960 | ||
9961 | /* Align to a given power of two. .align 0 turns off the automatic | |
9962 | alignment used by the data creating pseudo-ops. */ | |
9963 | ||
9964 | static void | |
9965 | s_align (x) | |
43841e91 | 9966 | int x ATTRIBUTE_UNUSED; |
252b5132 RH |
9967 | { |
9968 | register int temp; | |
9969 | register long temp_fill; | |
9970 | long max_alignment = 15; | |
9971 | ||
9972 | /* | |
9973 | ||
9974 | o Note that the assembler pulls down any immediately preceeding label | |
9975 | to the aligned address. | |
9976 | o It's not documented but auto alignment is reinstated by | |
9977 | a .align pseudo instruction. | |
9978 | o Note also that after auto alignment is turned off the mips assembler | |
9979 | issues an error on attempt to assemble an improperly aligned data item. | |
9980 | We don't. | |
9981 | ||
9982 | */ | |
9983 | ||
9984 | temp = get_absolute_expression (); | |
9985 | if (temp > max_alignment) | |
9986 | as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment); | |
9987 | else if (temp < 0) | |
9988 | { | |
9989 | as_warn (_("Alignment negative: 0 assumed.")); | |
9990 | temp = 0; | |
9991 | } | |
9992 | if (*input_line_pointer == ',') | |
9993 | { | |
9994 | input_line_pointer++; | |
9995 | temp_fill = get_absolute_expression (); | |
9996 | } | |
9997 | else | |
9998 | temp_fill = 0; | |
9999 | if (temp) | |
10000 | { | |
10001 | auto_align = 1; | |
10002 | mips_align (temp, (int) temp_fill, | |
10003 | insn_labels != NULL ? insn_labels->label : NULL); | |
10004 | } | |
10005 | else | |
10006 | { | |
10007 | auto_align = 0; | |
10008 | } | |
10009 | ||
10010 | demand_empty_rest_of_line (); | |
10011 | } | |
10012 | ||
10013 | void | |
10014 | mips_flush_pending_output () | |
10015 | { | |
10016 | mips_emit_delays (false); | |
10017 | mips_clear_insn_labels (); | |
10018 | } | |
10019 | ||
10020 | static void | |
10021 | s_change_sec (sec) | |
10022 | int sec; | |
10023 | { | |
10024 | segT seg; | |
10025 | ||
10026 | /* When generating embedded PIC code, we only use the .text, .lit8, | |
10027 | .sdata and .sbss sections. We change the .data and .rdata | |
10028 | pseudo-ops to use .sdata. */ | |
10029 | if (mips_pic == EMBEDDED_PIC | |
10030 | && (sec == 'd' || sec == 'r')) | |
10031 | sec = 's'; | |
10032 | ||
10033 | #ifdef OBJ_ELF | |
10034 | /* The ELF backend needs to know that we are changing sections, so | |
10035 | that .previous works correctly. We could do something like check | |
10036 | for a obj_section_change_hook macro, but that might be confusing | |
10037 | as it would not be appropriate to use it in the section changing | |
10038 | functions in read.c, since obj-elf.c intercepts those. FIXME: | |
10039 | This should be cleaner, somehow. */ | |
10040 | obj_elf_section_change_hook (); | |
10041 | #endif | |
10042 | ||
10043 | mips_emit_delays (false); | |
10044 | switch (sec) | |
10045 | { | |
10046 | case 't': | |
10047 | s_text (0); | |
10048 | break; | |
10049 | case 'd': | |
10050 | s_data (0); | |
10051 | break; | |
10052 | case 'b': | |
10053 | subseg_set (bss_section, (subsegT) get_absolute_expression ()); | |
10054 | demand_empty_rest_of_line (); | |
10055 | break; | |
10056 | ||
10057 | case 'r': | |
10058 | if (USE_GLOBAL_POINTER_OPT) | |
10059 | { | |
10060 | seg = subseg_new (RDATA_SECTION_NAME, | |
10061 | (subsegT) get_absolute_expression ()); | |
10062 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
10063 | { | |
10064 | bfd_set_section_flags (stdoutput, seg, | |
10065 | (SEC_ALLOC | |
10066 | | SEC_LOAD | |
10067 | | SEC_READONLY | |
10068 | | SEC_RELOC | |
10069 | | SEC_DATA)); | |
10070 | if (strcmp (TARGET_OS, "elf") != 0) | |
e799a695 | 10071 | record_alignment (seg, 4); |
252b5132 RH |
10072 | } |
10073 | demand_empty_rest_of_line (); | |
10074 | } | |
10075 | else | |
10076 | { | |
10077 | as_bad (_("No read only data section in this object file format")); | |
10078 | demand_empty_rest_of_line (); | |
10079 | return; | |
10080 | } | |
10081 | break; | |
10082 | ||
10083 | case 's': | |
10084 | if (USE_GLOBAL_POINTER_OPT) | |
10085 | { | |
10086 | seg = subseg_new (".sdata", (subsegT) get_absolute_expression ()); | |
10087 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
10088 | { | |
10089 | bfd_set_section_flags (stdoutput, seg, | |
10090 | SEC_ALLOC | SEC_LOAD | SEC_RELOC | |
10091 | | SEC_DATA); | |
10092 | if (strcmp (TARGET_OS, "elf") != 0) | |
e799a695 | 10093 | record_alignment (seg, 4); |
252b5132 RH |
10094 | } |
10095 | demand_empty_rest_of_line (); | |
10096 | break; | |
10097 | } | |
10098 | else | |
10099 | { | |
10100 | as_bad (_("Global pointers not supported; recompile -G 0")); | |
10101 | demand_empty_rest_of_line (); | |
10102 | return; | |
10103 | } | |
10104 | } | |
10105 | ||
10106 | auto_align = 1; | |
10107 | } | |
10108 | ||
10109 | void | |
10110 | mips_enable_auto_align () | |
10111 | { | |
10112 | auto_align = 1; | |
10113 | } | |
10114 | ||
10115 | static void | |
10116 | s_cons (log_size) | |
10117 | int log_size; | |
10118 | { | |
10119 | symbolS *label; | |
10120 | ||
10121 | label = insn_labels != NULL ? insn_labels->label : NULL; | |
10122 | mips_emit_delays (false); | |
10123 | if (log_size > 0 && auto_align) | |
10124 | mips_align (log_size, 0, label); | |
10125 | mips_clear_insn_labels (); | |
10126 | cons (1 << log_size); | |
10127 | } | |
10128 | ||
10129 | static void | |
10130 | s_float_cons (type) | |
10131 | int type; | |
10132 | { | |
10133 | symbolS *label; | |
10134 | ||
10135 | label = insn_labels != NULL ? insn_labels->label : NULL; | |
10136 | ||
10137 | mips_emit_delays (false); | |
10138 | ||
10139 | if (auto_align) | |
49309057 ILT |
10140 | { |
10141 | if (type == 'd') | |
10142 | mips_align (3, 0, label); | |
10143 | else | |
10144 | mips_align (2, 0, label); | |
10145 | } | |
252b5132 RH |
10146 | |
10147 | mips_clear_insn_labels (); | |
10148 | ||
10149 | float_cons (type); | |
10150 | } | |
10151 | ||
10152 | /* Handle .globl. We need to override it because on Irix 5 you are | |
10153 | permitted to say | |
10154 | .globl foo .text | |
10155 | where foo is an undefined symbol, to mean that foo should be | |
10156 | considered to be the address of a function. */ | |
10157 | ||
10158 | static void | |
10159 | s_mips_globl (x) | |
43841e91 | 10160 | int x ATTRIBUTE_UNUSED; |
252b5132 RH |
10161 | { |
10162 | char *name; | |
10163 | int c; | |
10164 | symbolS *symbolP; | |
10165 | flagword flag; | |
10166 | ||
10167 | name = input_line_pointer; | |
10168 | c = get_symbol_end (); | |
10169 | symbolP = symbol_find_or_make (name); | |
10170 | *input_line_pointer = c; | |
10171 | SKIP_WHITESPACE (); | |
10172 | ||
10173 | /* On Irix 5, every global symbol that is not explicitly labelled as | |
10174 | being a function is apparently labelled as being an object. */ | |
10175 | flag = BSF_OBJECT; | |
10176 | ||
10177 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
10178 | { | |
10179 | char *secname; | |
10180 | asection *sec; | |
10181 | ||
10182 | secname = input_line_pointer; | |
10183 | c = get_symbol_end (); | |
10184 | sec = bfd_get_section_by_name (stdoutput, secname); | |
10185 | if (sec == NULL) | |
10186 | as_bad (_("%s: no such section"), secname); | |
10187 | *input_line_pointer = c; | |
10188 | ||
10189 | if (sec != NULL && (sec->flags & SEC_CODE) != 0) | |
10190 | flag = BSF_FUNCTION; | |
10191 | } | |
10192 | ||
49309057 | 10193 | symbol_get_bfdsym (symbolP)->flags |= flag; |
252b5132 RH |
10194 | |
10195 | S_SET_EXTERNAL (symbolP); | |
10196 | demand_empty_rest_of_line (); | |
10197 | } | |
10198 | ||
10199 | static void | |
10200 | s_option (x) | |
43841e91 | 10201 | int x ATTRIBUTE_UNUSED; |
252b5132 RH |
10202 | { |
10203 | char *opt; | |
10204 | char c; | |
10205 | ||
10206 | opt = input_line_pointer; | |
10207 | c = get_symbol_end (); | |
10208 | ||
10209 | if (*opt == 'O') | |
10210 | { | |
10211 | /* FIXME: What does this mean? */ | |
10212 | } | |
10213 | else if (strncmp (opt, "pic", 3) == 0) | |
10214 | { | |
10215 | int i; | |
10216 | ||
10217 | i = atoi (opt + 3); | |
10218 | if (i == 0) | |
10219 | mips_pic = NO_PIC; | |
10220 | else if (i == 2) | |
10221 | mips_pic = SVR4_PIC; | |
10222 | else | |
10223 | as_bad (_(".option pic%d not supported"), i); | |
10224 | ||
10225 | if (USE_GLOBAL_POINTER_OPT && mips_pic == SVR4_PIC) | |
10226 | { | |
10227 | if (g_switch_seen && g_switch_value != 0) | |
10228 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
10229 | g_switch_value = 0; | |
10230 | bfd_set_gp_size (stdoutput, 0); | |
10231 | } | |
10232 | } | |
10233 | else | |
10234 | as_warn (_("Unrecognized option \"%s\""), opt); | |
10235 | ||
10236 | *input_line_pointer = c; | |
10237 | demand_empty_rest_of_line (); | |
10238 | } | |
10239 | ||
10240 | /* This structure is used to hold a stack of .set values. */ | |
10241 | ||
e972090a NC |
10242 | struct mips_option_stack |
10243 | { | |
252b5132 RH |
10244 | struct mips_option_stack *next; |
10245 | struct mips_set_options options; | |
10246 | }; | |
10247 | ||
10248 | static struct mips_option_stack *mips_opts_stack; | |
10249 | ||
10250 | /* Handle the .set pseudo-op. */ | |
10251 | ||
10252 | static void | |
10253 | s_mipsset (x) | |
43841e91 | 10254 | int x ATTRIBUTE_UNUSED; |
252b5132 RH |
10255 | { |
10256 | char *name = input_line_pointer, ch; | |
10257 | ||
10258 | while (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
10259 | input_line_pointer++; | |
10260 | ch = *input_line_pointer; | |
10261 | *input_line_pointer = '\0'; | |
10262 | ||
10263 | if (strcmp (name, "reorder") == 0) | |
10264 | { | |
10265 | if (mips_opts.noreorder && prev_nop_frag != NULL) | |
10266 | { | |
10267 | /* If we still have pending nops, we can discard them. The | |
10268 | usual nop handling will insert any that are still | |
bdaaa2e1 | 10269 | needed. */ |
252b5132 RH |
10270 | prev_nop_frag->fr_fix -= (prev_nop_frag_holds |
10271 | * (mips_opts.mips16 ? 2 : 4)); | |
10272 | prev_nop_frag = NULL; | |
10273 | } | |
10274 | mips_opts.noreorder = 0; | |
10275 | } | |
10276 | else if (strcmp (name, "noreorder") == 0) | |
10277 | { | |
10278 | mips_emit_delays (true); | |
10279 | mips_opts.noreorder = 1; | |
10280 | mips_any_noreorder = 1; | |
10281 | } | |
10282 | else if (strcmp (name, "at") == 0) | |
10283 | { | |
10284 | mips_opts.noat = 0; | |
10285 | } | |
10286 | else if (strcmp (name, "noat") == 0) | |
10287 | { | |
10288 | mips_opts.noat = 1; | |
10289 | } | |
10290 | else if (strcmp (name, "macro") == 0) | |
10291 | { | |
10292 | mips_opts.warn_about_macros = 0; | |
10293 | } | |
10294 | else if (strcmp (name, "nomacro") == 0) | |
10295 | { | |
10296 | if (mips_opts.noreorder == 0) | |
10297 | as_bad (_("`noreorder' must be set before `nomacro'")); | |
10298 | mips_opts.warn_about_macros = 1; | |
10299 | } | |
10300 | else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0) | |
10301 | { | |
10302 | mips_opts.nomove = 0; | |
10303 | } | |
10304 | else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0) | |
10305 | { | |
10306 | mips_opts.nomove = 1; | |
10307 | } | |
10308 | else if (strcmp (name, "bopt") == 0) | |
10309 | { | |
10310 | mips_opts.nobopt = 0; | |
10311 | } | |
10312 | else if (strcmp (name, "nobopt") == 0) | |
10313 | { | |
10314 | mips_opts.nobopt = 1; | |
10315 | } | |
10316 | else if (strcmp (name, "mips16") == 0 | |
10317 | || strcmp (name, "MIPS-16") == 0) | |
10318 | mips_opts.mips16 = 1; | |
10319 | else if (strcmp (name, "nomips16") == 0 | |
10320 | || strcmp (name, "noMIPS-16") == 0) | |
10321 | mips_opts.mips16 = 0; | |
10322 | else if (strncmp (name, "mips", 4) == 0) | |
10323 | { | |
10324 | int isa; | |
10325 | ||
10326 | /* Permit the user to change the ISA on the fly. Needless to | |
10327 | say, misuse can cause serious problems. */ | |
10328 | isa = atoi (name + 4); | |
e7af610e NC |
10329 | switch (isa) |
10330 | { | |
84ea6cf2 NC |
10331 | case 0: mips_opts.isa = file_mips_isa; break; |
10332 | case 1: mips_opts.isa = ISA_MIPS1; break; | |
10333 | case 2: mips_opts.isa = ISA_MIPS2; break; | |
10334 | case 3: mips_opts.isa = ISA_MIPS3; break; | |
84ea6cf2 | 10335 | case 4: mips_opts.isa = ISA_MIPS4; break; |
9a41af64 | 10336 | case 5: mips_opts.isa = ISA_MIPS5; break; |
84ea6cf2 NC |
10337 | case 32: mips_opts.isa = ISA_MIPS32; break; |
10338 | case 64: mips_opts.isa = ISA_MIPS64; break; | |
10339 | default: as_bad (_("unknown ISA level")); break; | |
e7af610e | 10340 | } |
252b5132 RH |
10341 | } |
10342 | else if (strcmp (name, "autoextend") == 0) | |
10343 | mips_opts.noautoextend = 0; | |
10344 | else if (strcmp (name, "noautoextend") == 0) | |
10345 | mips_opts.noautoextend = 1; | |
10346 | else if (strcmp (name, "push") == 0) | |
10347 | { | |
10348 | struct mips_option_stack *s; | |
10349 | ||
10350 | s = (struct mips_option_stack *) xmalloc (sizeof *s); | |
10351 | s->next = mips_opts_stack; | |
10352 | s->options = mips_opts; | |
10353 | mips_opts_stack = s; | |
10354 | } | |
10355 | else if (strcmp (name, "pop") == 0) | |
10356 | { | |
10357 | struct mips_option_stack *s; | |
10358 | ||
10359 | s = mips_opts_stack; | |
10360 | if (s == NULL) | |
10361 | as_bad (_(".set pop with no .set push")); | |
10362 | else | |
10363 | { | |
10364 | /* If we're changing the reorder mode we need to handle | |
10365 | delay slots correctly. */ | |
10366 | if (s->options.noreorder && ! mips_opts.noreorder) | |
10367 | mips_emit_delays (true); | |
10368 | else if (! s->options.noreorder && mips_opts.noreorder) | |
10369 | { | |
10370 | if (prev_nop_frag != NULL) | |
10371 | { | |
10372 | prev_nop_frag->fr_fix -= (prev_nop_frag_holds | |
10373 | * (mips_opts.mips16 ? 2 : 4)); | |
10374 | prev_nop_frag = NULL; | |
10375 | } | |
10376 | } | |
10377 | ||
10378 | mips_opts = s->options; | |
10379 | mips_opts_stack = s->next; | |
10380 | free (s); | |
10381 | } | |
10382 | } | |
10383 | else | |
10384 | { | |
10385 | as_warn (_("Tried to set unrecognized symbol: %s\n"), name); | |
10386 | } | |
10387 | *input_line_pointer = ch; | |
10388 | demand_empty_rest_of_line (); | |
10389 | } | |
10390 | ||
10391 | /* Handle the .abicalls pseudo-op. I believe this is equivalent to | |
10392 | .option pic2. It means to generate SVR4 PIC calls. */ | |
10393 | ||
10394 | static void | |
10395 | s_abicalls (ignore) | |
43841e91 | 10396 | int ignore ATTRIBUTE_UNUSED; |
252b5132 RH |
10397 | { |
10398 | mips_pic = SVR4_PIC; | |
10399 | if (USE_GLOBAL_POINTER_OPT) | |
10400 | { | |
10401 | if (g_switch_seen && g_switch_value != 0) | |
10402 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
10403 | g_switch_value = 0; | |
10404 | } | |
10405 | bfd_set_gp_size (stdoutput, 0); | |
10406 | demand_empty_rest_of_line (); | |
10407 | } | |
10408 | ||
10409 | /* Handle the .cpload pseudo-op. This is used when generating SVR4 | |
10410 | PIC code. It sets the $gp register for the function based on the | |
10411 | function address, which is in the register named in the argument. | |
10412 | This uses a relocation against _gp_disp, which is handled specially | |
10413 | by the linker. The result is: | |
10414 | lui $gp,%hi(_gp_disp) | |
10415 | addiu $gp,$gp,%lo(_gp_disp) | |
10416 | addu $gp,$gp,.cpload argument | |
10417 | The .cpload argument is normally $25 == $t9. */ | |
10418 | ||
10419 | static void | |
10420 | s_cpload (ignore) | |
43841e91 | 10421 | int ignore ATTRIBUTE_UNUSED; |
252b5132 RH |
10422 | { |
10423 | expressionS ex; | |
10424 | int icnt = 0; | |
10425 | ||
10426 | /* If we are not generating SVR4 PIC code, .cpload is ignored. */ | |
10427 | if (mips_pic != SVR4_PIC) | |
10428 | { | |
10429 | s_ignore (0); | |
10430 | return; | |
10431 | } | |
10432 | ||
10433 | /* .cpload should be a in .set noreorder section. */ | |
10434 | if (mips_opts.noreorder == 0) | |
10435 | as_warn (_(".cpload not in noreorder section")); | |
10436 | ||
10437 | ex.X_op = O_symbol; | |
10438 | ex.X_add_symbol = symbol_find_or_make ("_gp_disp"); | |
10439 | ex.X_op_symbol = NULL; | |
10440 | ex.X_add_number = 0; | |
10441 | ||
10442 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ | |
49309057 | 10443 | symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; |
252b5132 RH |
10444 | |
10445 | macro_build_lui ((char *) NULL, &icnt, &ex, GP); | |
10446 | macro_build ((char *) NULL, &icnt, &ex, "addiu", "t,r,j", GP, GP, | |
10447 | (int) BFD_RELOC_LO16); | |
10448 | ||
10449 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "addu", "d,v,t", | |
10450 | GP, GP, tc_get_register (0)); | |
10451 | ||
10452 | demand_empty_rest_of_line (); | |
10453 | } | |
10454 | ||
10455 | /* Handle the .cprestore pseudo-op. This stores $gp into a given | |
10456 | offset from $sp. The offset is remembered, and after making a PIC | |
10457 | call $gp is restored from that location. */ | |
10458 | ||
10459 | static void | |
10460 | s_cprestore (ignore) | |
43841e91 | 10461 | int ignore ATTRIBUTE_UNUSED; |
252b5132 RH |
10462 | { |
10463 | expressionS ex; | |
10464 | int icnt = 0; | |
10465 | ||
10466 | /* If we are not generating SVR4 PIC code, .cprestore is ignored. */ | |
10467 | if (mips_pic != SVR4_PIC) | |
10468 | { | |
10469 | s_ignore (0); | |
10470 | return; | |
10471 | } | |
10472 | ||
10473 | mips_cprestore_offset = get_absolute_expression (); | |
10474 | ||
10475 | ex.X_op = O_constant; | |
10476 | ex.X_add_symbol = NULL; | |
10477 | ex.X_op_symbol = NULL; | |
10478 | ex.X_add_number = mips_cprestore_offset; | |
10479 | ||
10480 | macro_build ((char *) NULL, &icnt, &ex, | |
ca4e0257 | 10481 | HAVE_32BIT_ADDRESSES ? "sw" : "sd", |
252b5132 RH |
10482 | "t,o(b)", GP, (int) BFD_RELOC_LO16, SP); |
10483 | ||
10484 | demand_empty_rest_of_line (); | |
10485 | } | |
10486 | ||
10487 | /* Handle the .gpword pseudo-op. This is used when generating PIC | |
10488 | code. It generates a 32 bit GP relative reloc. */ | |
10489 | ||
10490 | static void | |
10491 | s_gpword (ignore) | |
43841e91 | 10492 | int ignore ATTRIBUTE_UNUSED; |
252b5132 RH |
10493 | { |
10494 | symbolS *label; | |
10495 | expressionS ex; | |
10496 | char *p; | |
10497 | ||
10498 | /* When not generating PIC code, this is treated as .word. */ | |
10499 | if (mips_pic != SVR4_PIC) | |
10500 | { | |
10501 | s_cons (2); | |
10502 | return; | |
10503 | } | |
10504 | ||
10505 | label = insn_labels != NULL ? insn_labels->label : NULL; | |
10506 | mips_emit_delays (true); | |
10507 | if (auto_align) | |
10508 | mips_align (2, 0, label); | |
10509 | mips_clear_insn_labels (); | |
10510 | ||
10511 | expression (&ex); | |
10512 | ||
10513 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
10514 | { | |
10515 | as_bad (_("Unsupported use of .gpword")); | |
10516 | ignore_rest_of_line (); | |
10517 | } | |
10518 | ||
10519 | p = frag_more (4); | |
10520 | md_number_to_chars (p, (valueT) 0, 4); | |
10521 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, 0, | |
10522 | BFD_RELOC_MIPS_GPREL32); | |
10523 | ||
10524 | demand_empty_rest_of_line (); | |
10525 | } | |
10526 | ||
10527 | /* Handle the .cpadd pseudo-op. This is used when dealing with switch | |
10528 | tables in SVR4 PIC code. */ | |
10529 | ||
10530 | static void | |
10531 | s_cpadd (ignore) | |
43841e91 | 10532 | int ignore ATTRIBUTE_UNUSED; |
252b5132 RH |
10533 | { |
10534 | int icnt = 0; | |
10535 | int reg; | |
10536 | ||
10537 | /* This is ignored when not generating SVR4 PIC code. */ | |
10538 | if (mips_pic != SVR4_PIC) | |
10539 | { | |
10540 | s_ignore (0); | |
10541 | return; | |
10542 | } | |
10543 | ||
10544 | /* Add $gp to the register named as an argument. */ | |
10545 | reg = tc_get_register (0); | |
10546 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 10547 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
10548 | "d,v,t", reg, reg, GP); |
10549 | ||
bdaaa2e1 | 10550 | demand_empty_rest_of_line (); |
252b5132 RH |
10551 | } |
10552 | ||
10553 | /* Handle the .insn pseudo-op. This marks instruction labels in | |
10554 | mips16 mode. This permits the linker to handle them specially, | |
10555 | such as generating jalx instructions when needed. We also make | |
10556 | them odd for the duration of the assembly, in order to generate the | |
10557 | right sort of code. We will make them even in the adjust_symtab | |
10558 | routine, while leaving them marked. This is convenient for the | |
10559 | debugger and the disassembler. The linker knows to make them odd | |
10560 | again. */ | |
10561 | ||
10562 | static void | |
10563 | s_insn (ignore) | |
43841e91 | 10564 | int ignore ATTRIBUTE_UNUSED; |
252b5132 RH |
10565 | { |
10566 | if (mips_opts.mips16) | |
10567 | mips16_mark_labels (); | |
10568 | ||
10569 | demand_empty_rest_of_line (); | |
10570 | } | |
10571 | ||
10572 | /* Handle a .stabn directive. We need these in order to mark a label | |
10573 | as being a mips16 text label correctly. Sometimes the compiler | |
10574 | will emit a label, followed by a .stabn, and then switch sections. | |
10575 | If the label and .stabn are in mips16 mode, then the label is | |
10576 | really a mips16 text label. */ | |
10577 | ||
10578 | static void | |
10579 | s_mips_stab (type) | |
10580 | int type; | |
10581 | { | |
10582 | if (type == 'n' && mips_opts.mips16) | |
10583 | mips16_mark_labels (); | |
10584 | ||
10585 | s_stab (type); | |
10586 | } | |
10587 | ||
10588 | /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. | |
10589 | */ | |
10590 | ||
10591 | static void | |
10592 | s_mips_weakext (ignore) | |
43841e91 | 10593 | int ignore ATTRIBUTE_UNUSED; |
252b5132 RH |
10594 | { |
10595 | char *name; | |
10596 | int c; | |
10597 | symbolS *symbolP; | |
10598 | expressionS exp; | |
10599 | ||
10600 | name = input_line_pointer; | |
10601 | c = get_symbol_end (); | |
10602 | symbolP = symbol_find_or_make (name); | |
10603 | S_SET_WEAK (symbolP); | |
10604 | *input_line_pointer = c; | |
10605 | ||
10606 | SKIP_WHITESPACE (); | |
10607 | ||
10608 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
10609 | { | |
10610 | if (S_IS_DEFINED (symbolP)) | |
10611 | { | |
10612 | as_bad ("Ignoring attempt to redefine symbol `%s'.", | |
10613 | S_GET_NAME (symbolP)); | |
10614 | ignore_rest_of_line (); | |
10615 | return; | |
10616 | } | |
bdaaa2e1 | 10617 | |
252b5132 RH |
10618 | if (*input_line_pointer == ',') |
10619 | { | |
10620 | ++input_line_pointer; | |
10621 | SKIP_WHITESPACE (); | |
10622 | } | |
bdaaa2e1 | 10623 | |
252b5132 RH |
10624 | expression (&exp); |
10625 | if (exp.X_op != O_symbol) | |
10626 | { | |
10627 | as_bad ("bad .weakext directive"); | |
10628 | ignore_rest_of_line(); | |
10629 | return; | |
10630 | } | |
49309057 | 10631 | symbol_set_value_expression (symbolP, &exp); |
252b5132 RH |
10632 | } |
10633 | ||
10634 | demand_empty_rest_of_line (); | |
10635 | } | |
10636 | ||
10637 | /* Parse a register string into a number. Called from the ECOFF code | |
10638 | to parse .frame. The argument is non-zero if this is the frame | |
10639 | register, so that we can record it in mips_frame_reg. */ | |
10640 | ||
10641 | int | |
10642 | tc_get_register (frame) | |
10643 | int frame; | |
10644 | { | |
10645 | int reg; | |
10646 | ||
10647 | SKIP_WHITESPACE (); | |
10648 | if (*input_line_pointer++ != '$') | |
10649 | { | |
10650 | as_warn (_("expected `$'")); | |
10651 | reg = 0; | |
10652 | } | |
10653 | else if (isdigit ((unsigned char) *input_line_pointer)) | |
10654 | { | |
10655 | reg = get_absolute_expression (); | |
10656 | if (reg < 0 || reg >= 32) | |
10657 | { | |
10658 | as_warn (_("Bad register number")); | |
10659 | reg = 0; | |
10660 | } | |
10661 | } | |
10662 | else | |
10663 | { | |
10664 | if (strncmp (input_line_pointer, "fp", 2) == 0) | |
10665 | reg = FP; | |
10666 | else if (strncmp (input_line_pointer, "sp", 2) == 0) | |
10667 | reg = SP; | |
10668 | else if (strncmp (input_line_pointer, "gp", 2) == 0) | |
10669 | reg = GP; | |
10670 | else if (strncmp (input_line_pointer, "at", 2) == 0) | |
10671 | reg = AT; | |
10672 | else | |
10673 | { | |
10674 | as_warn (_("Unrecognized register name")); | |
10675 | reg = 0; | |
10676 | } | |
10677 | input_line_pointer += 2; | |
10678 | } | |
10679 | if (frame) | |
10680 | mips_frame_reg = reg != 0 ? reg : SP; | |
10681 | return reg; | |
10682 | } | |
10683 | ||
10684 | valueT | |
10685 | md_section_align (seg, addr) | |
10686 | asection *seg; | |
10687 | valueT addr; | |
10688 | { | |
10689 | int align = bfd_get_section_alignment (stdoutput, seg); | |
10690 | ||
10691 | #ifdef OBJ_ELF | |
10692 | /* We don't need to align ELF sections to the full alignment. | |
10693 | However, Irix 5 may prefer that we align them at least to a 16 | |
10694 | byte boundary. We don't bother to align the sections if we are | |
10695 | targeted for an embedded system. */ | |
10696 | if (strcmp (TARGET_OS, "elf") == 0) | |
10697 | return addr; | |
10698 | if (align > 4) | |
10699 | align = 4; | |
10700 | #endif | |
10701 | ||
10702 | return ((addr + (1 << align) - 1) & (-1 << align)); | |
10703 | } | |
10704 | ||
10705 | /* Utility routine, called from above as well. If called while the | |
10706 | input file is still being read, it's only an approximation. (For | |
10707 | example, a symbol may later become defined which appeared to be | |
10708 | undefined earlier.) */ | |
10709 | ||
10710 | static int | |
10711 | nopic_need_relax (sym, before_relaxing) | |
10712 | symbolS *sym; | |
10713 | int before_relaxing; | |
10714 | { | |
10715 | if (sym == 0) | |
10716 | return 0; | |
10717 | ||
10718 | if (USE_GLOBAL_POINTER_OPT) | |
10719 | { | |
10720 | const char *symname; | |
10721 | int change; | |
10722 | ||
10723 | /* Find out whether this symbol can be referenced off the GP | |
10724 | register. It can be if it is smaller than the -G size or if | |
10725 | it is in the .sdata or .sbss section. Certain symbols can | |
10726 | not be referenced off the GP, although it appears as though | |
10727 | they can. */ | |
10728 | symname = S_GET_NAME (sym); | |
10729 | if (symname != (const char *) NULL | |
10730 | && (strcmp (symname, "eprol") == 0 | |
10731 | || strcmp (symname, "etext") == 0 | |
10732 | || strcmp (symname, "_gp") == 0 | |
10733 | || strcmp (symname, "edata") == 0 | |
10734 | || strcmp (symname, "_fbss") == 0 | |
10735 | || strcmp (symname, "_fdata") == 0 | |
10736 | || strcmp (symname, "_ftext") == 0 | |
10737 | || strcmp (symname, "end") == 0 | |
10738 | || strcmp (symname, "_gp_disp") == 0)) | |
10739 | change = 1; | |
10740 | else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym)) | |
10741 | && (0 | |
10742 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 ILT |
10743 | || (symbol_get_obj (sym)->ecoff_extern_size != 0 |
10744 | && (symbol_get_obj (sym)->ecoff_extern_size | |
10745 | <= g_switch_value)) | |
252b5132 RH |
10746 | #endif |
10747 | /* We must defer this decision until after the whole | |
10748 | file has been read, since there might be a .extern | |
10749 | after the first use of this symbol. */ | |
10750 | || (before_relaxing | |
10751 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 | 10752 | && symbol_get_obj (sym)->ecoff_extern_size == 0 |
252b5132 RH |
10753 | #endif |
10754 | && S_GET_VALUE (sym) == 0) | |
10755 | || (S_GET_VALUE (sym) != 0 | |
10756 | && S_GET_VALUE (sym) <= g_switch_value))) | |
10757 | change = 0; | |
10758 | else | |
10759 | { | |
10760 | const char *segname; | |
10761 | ||
10762 | segname = segment_name (S_GET_SEGMENT (sym)); | |
10763 | assert (strcmp (segname, ".lit8") != 0 | |
10764 | && strcmp (segname, ".lit4") != 0); | |
10765 | change = (strcmp (segname, ".sdata") != 0 | |
fba2b7f9 GK |
10766 | && strcmp (segname, ".sbss") != 0 |
10767 | && strncmp (segname, ".sdata.", 7) != 0 | |
10768 | && strncmp (segname, ".gnu.linkonce.s.", 16) != 0); | |
252b5132 RH |
10769 | } |
10770 | return change; | |
10771 | } | |
10772 | else | |
10773 | /* We are not optimizing for the GP register. */ | |
10774 | return 1; | |
10775 | } | |
10776 | ||
10777 | /* Given a mips16 variant frag FRAGP, return non-zero if it needs an | |
10778 | extended opcode. SEC is the section the frag is in. */ | |
10779 | ||
10780 | static int | |
10781 | mips16_extended_frag (fragp, sec, stretch) | |
10782 | fragS *fragp; | |
10783 | asection *sec; | |
10784 | long stretch; | |
10785 | { | |
10786 | int type; | |
10787 | register const struct mips16_immed_operand *op; | |
10788 | offsetT val; | |
10789 | int mintiny, maxtiny; | |
10790 | segT symsec; | |
98aa84af | 10791 | fragS *sym_frag; |
252b5132 RH |
10792 | |
10793 | if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype)) | |
10794 | return 0; | |
10795 | if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype)) | |
10796 | return 1; | |
10797 | ||
10798 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
10799 | op = mips16_immed_operands; | |
10800 | while (op->type != type) | |
10801 | { | |
10802 | ++op; | |
10803 | assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); | |
10804 | } | |
10805 | ||
10806 | if (op->unsp) | |
10807 | { | |
10808 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
10809 | { | |
10810 | mintiny = 1; | |
10811 | maxtiny = 1 << op->nbits; | |
10812 | } | |
10813 | else | |
10814 | { | |
10815 | mintiny = 0; | |
10816 | maxtiny = (1 << op->nbits) - 1; | |
10817 | } | |
10818 | } | |
10819 | else | |
10820 | { | |
10821 | mintiny = - (1 << (op->nbits - 1)); | |
10822 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
10823 | } | |
10824 | ||
98aa84af | 10825 | sym_frag = symbol_get_frag (fragp->fr_symbol); |
ac62c346 | 10826 | val = S_GET_VALUE (fragp->fr_symbol); |
98aa84af | 10827 | symsec = S_GET_SEGMENT (fragp->fr_symbol); |
252b5132 RH |
10828 | |
10829 | if (op->pcrel) | |
10830 | { | |
10831 | addressT addr; | |
10832 | ||
10833 | /* We won't have the section when we are called from | |
10834 | mips_relax_frag. However, we will always have been called | |
10835 | from md_estimate_size_before_relax first. If this is a | |
10836 | branch to a different section, we mark it as such. If SEC is | |
10837 | NULL, and the frag is not marked, then it must be a branch to | |
10838 | the same section. */ | |
10839 | if (sec == NULL) | |
10840 | { | |
10841 | if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype)) | |
10842 | return 1; | |
10843 | } | |
10844 | else | |
10845 | { | |
98aa84af | 10846 | /* Must have been called from md_estimate_size_before_relax. */ |
252b5132 RH |
10847 | if (symsec != sec) |
10848 | { | |
10849 | fragp->fr_subtype = | |
10850 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
10851 | ||
10852 | /* FIXME: We should support this, and let the linker | |
10853 | catch branches and loads that are out of range. */ | |
10854 | as_bad_where (fragp->fr_file, fragp->fr_line, | |
10855 | _("unsupported PC relative reference to different section")); | |
10856 | ||
10857 | return 1; | |
10858 | } | |
98aa84af AM |
10859 | if (fragp != sym_frag && sym_frag->fr_address == 0) |
10860 | /* Assume non-extended on the first relaxation pass. | |
10861 | The address we have calculated will be bogus if this is | |
10862 | a forward branch to another frag, as the forward frag | |
10863 | will have fr_address == 0. */ | |
10864 | return 0; | |
252b5132 RH |
10865 | } |
10866 | ||
10867 | /* In this case, we know for sure that the symbol fragment is in | |
98aa84af AM |
10868 | the same section. If the relax_marker of the symbol fragment |
10869 | differs from the relax_marker of this fragment, we have not | |
10870 | yet adjusted the symbol fragment fr_address. We want to add | |
252b5132 RH |
10871 | in STRETCH in order to get a better estimate of the address. |
10872 | This particularly matters because of the shift bits. */ | |
10873 | if (stretch != 0 | |
98aa84af | 10874 | && sym_frag->relax_marker != fragp->relax_marker) |
252b5132 RH |
10875 | { |
10876 | fragS *f; | |
10877 | ||
10878 | /* Adjust stretch for any alignment frag. Note that if have | |
10879 | been expanding the earlier code, the symbol may be | |
10880 | defined in what appears to be an earlier frag. FIXME: | |
10881 | This doesn't handle the fr_subtype field, which specifies | |
10882 | a maximum number of bytes to skip when doing an | |
10883 | alignment. */ | |
98aa84af | 10884 | for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next) |
252b5132 RH |
10885 | { |
10886 | if (f->fr_type == rs_align || f->fr_type == rs_align_code) | |
10887 | { | |
10888 | if (stretch < 0) | |
10889 | stretch = - ((- stretch) | |
10890 | & ~ ((1 << (int) f->fr_offset) - 1)); | |
10891 | else | |
10892 | stretch &= ~ ((1 << (int) f->fr_offset) - 1); | |
10893 | if (stretch == 0) | |
10894 | break; | |
10895 | } | |
10896 | } | |
10897 | if (f != NULL) | |
10898 | val += stretch; | |
10899 | } | |
10900 | ||
10901 | addr = fragp->fr_address + fragp->fr_fix; | |
10902 | ||
10903 | /* The base address rules are complicated. The base address of | |
10904 | a branch is the following instruction. The base address of a | |
10905 | PC relative load or add is the instruction itself, but if it | |
10906 | is in a delay slot (in which case it can not be extended) use | |
10907 | the address of the instruction whose delay slot it is in. */ | |
10908 | if (type == 'p' || type == 'q') | |
10909 | { | |
10910 | addr += 2; | |
10911 | ||
10912 | /* If we are currently assuming that this frag should be | |
10913 | extended, then, the current address is two bytes | |
bdaaa2e1 | 10914 | higher. */ |
252b5132 RH |
10915 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) |
10916 | addr += 2; | |
10917 | ||
10918 | /* Ignore the low bit in the target, since it will be set | |
10919 | for a text label. */ | |
10920 | if ((val & 1) != 0) | |
10921 | --val; | |
10922 | } | |
10923 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) | |
10924 | addr -= 4; | |
10925 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
10926 | addr -= 2; | |
10927 | ||
10928 | val -= addr & ~ ((1 << op->shift) - 1); | |
10929 | ||
10930 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
10931 | if (type == 'p' || type == 'q') | |
10932 | val /= 2; | |
10933 | ||
10934 | /* If any of the shifted bits are set, we must use an extended | |
10935 | opcode. If the address depends on the size of this | |
10936 | instruction, this can lead to a loop, so we arrange to always | |
10937 | use an extended opcode. We only check this when we are in | |
10938 | the main relaxation loop, when SEC is NULL. */ | |
10939 | if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL) | |
10940 | { | |
10941 | fragp->fr_subtype = | |
10942 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
10943 | return 1; | |
10944 | } | |
10945 | ||
10946 | /* If we are about to mark a frag as extended because the value | |
10947 | is precisely maxtiny + 1, then there is a chance of an | |
10948 | infinite loop as in the following code: | |
10949 | la $4,foo | |
10950 | .skip 1020 | |
10951 | .align 2 | |
10952 | foo: | |
10953 | In this case when the la is extended, foo is 0x3fc bytes | |
10954 | away, so the la can be shrunk, but then foo is 0x400 away, so | |
10955 | the la must be extended. To avoid this loop, we mark the | |
10956 | frag as extended if it was small, and is about to become | |
10957 | extended with a value of maxtiny + 1. */ | |
10958 | if (val == ((maxtiny + 1) << op->shift) | |
10959 | && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype) | |
10960 | && sec == NULL) | |
10961 | { | |
10962 | fragp->fr_subtype = | |
10963 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
10964 | return 1; | |
10965 | } | |
10966 | } | |
10967 | else if (symsec != absolute_section && sec != NULL) | |
10968 | as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation")); | |
10969 | ||
10970 | if ((val & ((1 << op->shift) - 1)) != 0 | |
10971 | || val < (mintiny << op->shift) | |
10972 | || val > (maxtiny << op->shift)) | |
10973 | return 1; | |
10974 | else | |
10975 | return 0; | |
10976 | } | |
10977 | ||
10978 | /* Estimate the size of a frag before relaxing. Unless this is the | |
10979 | mips16, we are not really relaxing here, and the final size is | |
10980 | encoded in the subtype information. For the mips16, we have to | |
10981 | decide whether we are using an extended opcode or not. */ | |
10982 | ||
252b5132 RH |
10983 | int |
10984 | md_estimate_size_before_relax (fragp, segtype) | |
10985 | fragS *fragp; | |
10986 | asection *segtype; | |
10987 | { | |
43841e91 | 10988 | int change = 0; |
8614eeee | 10989 | boolean linkonce = false; |
252b5132 RH |
10990 | |
10991 | if (RELAX_MIPS16_P (fragp->fr_subtype)) | |
10992 | { | |
10993 | if (mips16_extended_frag (fragp, segtype, 0)) | |
10994 | { | |
10995 | fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype); | |
10996 | return 4; | |
10997 | } | |
10998 | else | |
10999 | { | |
11000 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype); | |
11001 | return 2; | |
11002 | } | |
11003 | } | |
11004 | ||
11005 | if (mips_pic == NO_PIC) | |
11006 | { | |
11007 | change = nopic_need_relax (fragp->fr_symbol, 0); | |
11008 | } | |
11009 | else if (mips_pic == SVR4_PIC) | |
11010 | { | |
11011 | symbolS *sym; | |
11012 | asection *symsec; | |
11013 | ||
11014 | sym = fragp->fr_symbol; | |
11015 | ||
11016 | /* Handle the case of a symbol equated to another symbol. */ | |
49309057 | 11017 | while (symbol_equated_p (sym) |
252b5132 RH |
11018 | && (! S_IS_DEFINED (sym) || S_IS_COMMON (sym))) |
11019 | { | |
11020 | symbolS *n; | |
11021 | ||
11022 | /* It's possible to get a loop here in a badly written | |
11023 | program. */ | |
49309057 | 11024 | n = symbol_get_value_expression (sym)->X_add_symbol; |
252b5132 RH |
11025 | if (n == sym) |
11026 | break; | |
11027 | sym = n; | |
11028 | } | |
11029 | ||
11030 | symsec = S_GET_SEGMENT (sym); | |
11031 | ||
8614eeee UC |
11032 | /* duplicate the test for LINK_ONCE sections as in adjust_reloc_syms */ |
11033 | if (symsec != segtype && ! S_IS_LOCAL (sym)) | |
beae10d5 KH |
11034 | { |
11035 | if ((bfd_get_section_flags (stdoutput, symsec) & SEC_LINK_ONCE) | |
11036 | != 0) | |
11037 | linkonce = true; | |
11038 | ||
11039 | /* The GNU toolchain uses an extension for ELF: a section | |
11040 | beginning with the magic string .gnu.linkonce is a linkonce | |
11041 | section. */ | |
11042 | if (strncmp (segment_name (symsec), ".gnu.linkonce", | |
11043 | sizeof ".gnu.linkonce" - 1) == 0) | |
11044 | linkonce = true; | |
11045 | } | |
8614eeee | 11046 | |
252b5132 RH |
11047 | /* This must duplicate the test in adjust_reloc_syms. */ |
11048 | change = (symsec != &bfd_und_section | |
11049 | && symsec != &bfd_abs_section | |
426b0403 | 11050 | && ! bfd_is_com_section (symsec) |
8614eeee | 11051 | && !linkonce |
426b0403 | 11052 | #ifdef OBJ_ELF |
ea4ff978 | 11053 | /* A global or weak symbol is treated as external. */ |
46bac6de L |
11054 | && (OUTPUT_FLAVOR == bfd_target_elf_flavour |
11055 | && ! (S_IS_EXTERN (sym) || S_IS_WEAK (sym))) | |
426b0403 AM |
11056 | #endif |
11057 | ); | |
252b5132 RH |
11058 | } |
11059 | else | |
11060 | abort (); | |
11061 | ||
11062 | if (change) | |
11063 | { | |
11064 | /* Record the offset to the first reloc in the fr_opcode field. | |
11065 | This lets md_convert_frag and tc_gen_reloc know that the code | |
11066 | must be expanded. */ | |
11067 | fragp->fr_opcode = (fragp->fr_literal | |
11068 | + fragp->fr_fix | |
11069 | - RELAX_OLD (fragp->fr_subtype) | |
11070 | + RELAX_RELOC1 (fragp->fr_subtype)); | |
11071 | /* FIXME: This really needs as_warn_where. */ | |
11072 | if (RELAX_WARN (fragp->fr_subtype)) | |
9a41af64 TS |
11073 | as_warn (_("AT used after \".set noat\" or macro used after " |
11074 | "\".set nomacro\"")); | |
11075 | ||
11076 | return RELAX_NEW (fragp->fr_subtype) - RELAX_OLD (fragp->fr_subtype); | |
252b5132 RH |
11077 | } |
11078 | ||
9a41af64 | 11079 | return 0; |
252b5132 RH |
11080 | } |
11081 | ||
11082 | /* This is called to see whether a reloc against a defined symbol | |
11083 | should be converted into a reloc against a section. Don't adjust | |
11084 | MIPS16 jump relocations, so we don't have to worry about the format | |
11085 | of the offset in the .o file. Don't adjust relocations against | |
11086 | mips16 symbols, so that the linker can find them if it needs to set | |
11087 | up a stub. */ | |
11088 | ||
11089 | int | |
11090 | mips_fix_adjustable (fixp) | |
11091 | fixS *fixp; | |
11092 | { | |
ea4ff978 L |
11093 | #ifdef OBJ_ELF |
11094 | /* Prevent all adjustments to global symbols. */ | |
46bac6de L |
11095 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour |
11096 | && (S_IS_EXTERN (fixp->fx_addsy) || S_IS_WEAK (fixp->fx_addsy))) | |
ea4ff978 L |
11097 | return 0; |
11098 | #endif | |
252b5132 RH |
11099 | if (fixp->fx_r_type == BFD_RELOC_MIPS16_JMP) |
11100 | return 0; | |
11101 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT | |
11102 | || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
11103 | return 0; | |
11104 | if (fixp->fx_addsy == NULL) | |
11105 | return 1; | |
11106 | #ifdef OBJ_ELF | |
11107 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour | |
11108 | && S_GET_OTHER (fixp->fx_addsy) == STO_MIPS16 | |
11109 | && fixp->fx_subsy == NULL) | |
11110 | return 0; | |
11111 | #endif | |
11112 | return 1; | |
11113 | } | |
11114 | ||
11115 | /* Translate internal representation of relocation info to BFD target | |
11116 | format. */ | |
11117 | ||
11118 | arelent ** | |
11119 | tc_gen_reloc (section, fixp) | |
43841e91 | 11120 | asection *section ATTRIBUTE_UNUSED; |
252b5132 RH |
11121 | fixS *fixp; |
11122 | { | |
11123 | static arelent *retval[4]; | |
11124 | arelent *reloc; | |
11125 | bfd_reloc_code_real_type code; | |
11126 | ||
11127 | reloc = retval[0] = (arelent *) xmalloc (sizeof (arelent)); | |
11128 | retval[1] = NULL; | |
11129 | ||
49309057 ILT |
11130 | reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); |
11131 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
252b5132 RH |
11132 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; |
11133 | ||
11134 | if (mips_pic == EMBEDDED_PIC | |
11135 | && SWITCH_TABLE (fixp)) | |
11136 | { | |
11137 | /* For a switch table entry we use a special reloc. The addend | |
11138 | is actually the difference between the reloc address and the | |
11139 | subtrahend. */ | |
11140 | reloc->addend = reloc->address - S_GET_VALUE (fixp->fx_subsy); | |
11141 | if (OUTPUT_FLAVOR != bfd_target_ecoff_flavour) | |
11142 | as_fatal (_("Double check fx_r_type in tc-mips.c:tc_gen_reloc")); | |
11143 | fixp->fx_r_type = BFD_RELOC_GPREL32; | |
11144 | } | |
bb2d6cd7 GK |
11145 | else if (fixp->fx_pcrel == 0 || OUTPUT_FLAVOR == bfd_target_elf_flavour) |
11146 | reloc->addend = fixp->fx_addnumber; | |
252b5132 RH |
11147 | else if (fixp->fx_r_type == BFD_RELOC_PCREL_LO16) |
11148 | { | |
11149 | /* We use a special addend for an internal RELLO reloc. */ | |
49309057 | 11150 | if (symbol_section_p (fixp->fx_addsy)) |
252b5132 RH |
11151 | reloc->addend = reloc->address - S_GET_VALUE (fixp->fx_subsy); |
11152 | else | |
11153 | reloc->addend = fixp->fx_addnumber + reloc->address; | |
11154 | } | |
11155 | else if (fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S) | |
11156 | { | |
11157 | assert (fixp->fx_next != NULL | |
11158 | && fixp->fx_next->fx_r_type == BFD_RELOC_PCREL_LO16); | |
11159 | /* We use a special addend for an internal RELHI reloc. The | |
11160 | reloc is relative to the RELLO; adjust the addend | |
11161 | accordingly. */ | |
49309057 | 11162 | if (symbol_section_p (fixp->fx_addsy)) |
252b5132 RH |
11163 | reloc->addend = (fixp->fx_next->fx_frag->fr_address |
11164 | + fixp->fx_next->fx_where | |
11165 | - S_GET_VALUE (fixp->fx_subsy)); | |
11166 | else | |
11167 | reloc->addend = (fixp->fx_addnumber | |
11168 | + fixp->fx_next->fx_frag->fr_address | |
11169 | + fixp->fx_next->fx_where); | |
11170 | } | |
252b5132 RH |
11171 | else |
11172 | { | |
11173 | if (OUTPUT_FLAVOR != bfd_target_aout_flavour) | |
11174 | /* A gruesome hack which is a result of the gruesome gas reloc | |
11175 | handling. */ | |
11176 | reloc->addend = reloc->address; | |
11177 | else | |
11178 | reloc->addend = -reloc->address; | |
11179 | } | |
11180 | ||
11181 | /* If this is a variant frag, we may need to adjust the existing | |
11182 | reloc and generate a new one. */ | |
11183 | if (fixp->fx_frag->fr_opcode != NULL | |
11184 | && (fixp->fx_r_type == BFD_RELOC_MIPS_GPREL | |
11185 | || fixp->fx_r_type == BFD_RELOC_MIPS_GOT16 | |
11186 | || fixp->fx_r_type == BFD_RELOC_MIPS_CALL16 | |
11187 | || fixp->fx_r_type == BFD_RELOC_MIPS_GOT_HI16 | |
11188 | || fixp->fx_r_type == BFD_RELOC_MIPS_GOT_LO16 | |
11189 | || fixp->fx_r_type == BFD_RELOC_MIPS_CALL_HI16 | |
11190 | || fixp->fx_r_type == BFD_RELOC_MIPS_CALL_LO16)) | |
11191 | { | |
11192 | arelent *reloc2; | |
11193 | ||
11194 | assert (! RELAX_MIPS16_P (fixp->fx_frag->fr_subtype)); | |
11195 | ||
11196 | /* If this is not the last reloc in this frag, then we have two | |
11197 | GPREL relocs, or a GOT_HI16/GOT_LO16 pair, or a | |
11198 | CALL_HI16/CALL_LO16, both of which are being replaced. Let | |
11199 | the second one handle all of them. */ | |
11200 | if (fixp->fx_next != NULL | |
11201 | && fixp->fx_frag == fixp->fx_next->fx_frag) | |
11202 | { | |
11203 | assert ((fixp->fx_r_type == BFD_RELOC_MIPS_GPREL | |
11204 | && fixp->fx_next->fx_r_type == BFD_RELOC_MIPS_GPREL) | |
11205 | || (fixp->fx_r_type == BFD_RELOC_MIPS_GOT_HI16 | |
11206 | && (fixp->fx_next->fx_r_type | |
11207 | == BFD_RELOC_MIPS_GOT_LO16)) | |
11208 | || (fixp->fx_r_type == BFD_RELOC_MIPS_CALL_HI16 | |
11209 | && (fixp->fx_next->fx_r_type | |
11210 | == BFD_RELOC_MIPS_CALL_LO16))); | |
11211 | retval[0] = NULL; | |
11212 | return retval; | |
11213 | } | |
11214 | ||
11215 | fixp->fx_where = fixp->fx_frag->fr_opcode - fixp->fx_frag->fr_literal; | |
11216 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
11217 | reloc2 = retval[1] = (arelent *) xmalloc (sizeof (arelent)); | |
11218 | retval[2] = NULL; | |
49309057 ILT |
11219 | reloc2->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); |
11220 | *reloc2->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
252b5132 RH |
11221 | reloc2->address = (reloc->address |
11222 | + (RELAX_RELOC2 (fixp->fx_frag->fr_subtype) | |
11223 | - RELAX_RELOC1 (fixp->fx_frag->fr_subtype))); | |
11224 | reloc2->addend = fixp->fx_addnumber; | |
11225 | reloc2->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_LO16); | |
11226 | assert (reloc2->howto != NULL); | |
11227 | ||
11228 | if (RELAX_RELOC3 (fixp->fx_frag->fr_subtype)) | |
11229 | { | |
11230 | arelent *reloc3; | |
11231 | ||
11232 | reloc3 = retval[2] = (arelent *) xmalloc (sizeof (arelent)); | |
11233 | retval[3] = NULL; | |
11234 | *reloc3 = *reloc2; | |
11235 | reloc3->address += 4; | |
11236 | } | |
11237 | ||
11238 | if (mips_pic == NO_PIC) | |
11239 | { | |
11240 | assert (fixp->fx_r_type == BFD_RELOC_MIPS_GPREL); | |
11241 | fixp->fx_r_type = BFD_RELOC_HI16_S; | |
11242 | } | |
11243 | else if (mips_pic == SVR4_PIC) | |
11244 | { | |
11245 | switch (fixp->fx_r_type) | |
11246 | { | |
11247 | default: | |
11248 | abort (); | |
11249 | case BFD_RELOC_MIPS_GOT16: | |
11250 | break; | |
11251 | case BFD_RELOC_MIPS_CALL16: | |
11252 | case BFD_RELOC_MIPS_GOT_LO16: | |
11253 | case BFD_RELOC_MIPS_CALL_LO16: | |
11254 | fixp->fx_r_type = BFD_RELOC_MIPS_GOT16; | |
11255 | break; | |
11256 | } | |
11257 | } | |
11258 | else | |
11259 | abort (); | |
11260 | } | |
11261 | ||
11262 | /* Since MIPS ELF uses Rel instead of Rela, encode the vtable entry | |
11263 | to be used in the relocation's section offset. */ | |
11264 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
11265 | { | |
11266 | reloc->address = reloc->addend; | |
11267 | reloc->addend = 0; | |
11268 | } | |
11269 | ||
11270 | /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that | |
11271 | fixup_segment converted a non-PC relative reloc into a PC | |
11272 | relative reloc. In such a case, we need to convert the reloc | |
11273 | code. */ | |
11274 | code = fixp->fx_r_type; | |
11275 | if (fixp->fx_pcrel) | |
11276 | { | |
11277 | switch (code) | |
11278 | { | |
11279 | case BFD_RELOC_8: | |
11280 | code = BFD_RELOC_8_PCREL; | |
11281 | break; | |
11282 | case BFD_RELOC_16: | |
11283 | code = BFD_RELOC_16_PCREL; | |
11284 | break; | |
11285 | case BFD_RELOC_32: | |
11286 | code = BFD_RELOC_32_PCREL; | |
11287 | break; | |
11288 | case BFD_RELOC_64: | |
11289 | code = BFD_RELOC_64_PCREL; | |
11290 | break; | |
11291 | case BFD_RELOC_8_PCREL: | |
11292 | case BFD_RELOC_16_PCREL: | |
11293 | case BFD_RELOC_32_PCREL: | |
11294 | case BFD_RELOC_64_PCREL: | |
11295 | case BFD_RELOC_16_PCREL_S2: | |
11296 | case BFD_RELOC_PCREL_HI16_S: | |
11297 | case BFD_RELOC_PCREL_LO16: | |
11298 | break; | |
11299 | default: | |
11300 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
11301 | _("Cannot make %s relocation PC relative"), | |
11302 | bfd_get_reloc_code_name (code)); | |
11303 | } | |
11304 | } | |
11305 | ||
11306 | /* To support a PC relative reloc when generating embedded PIC code | |
11307 | for ECOFF, we use a Cygnus extension. We check for that here to | |
11308 | make sure that we don't let such a reloc escape normally. */ | |
bb2d6cd7 GK |
11309 | if ((OUTPUT_FLAVOR == bfd_target_ecoff_flavour |
11310 | || OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
252b5132 RH |
11311 | && code == BFD_RELOC_16_PCREL_S2 |
11312 | && mips_pic != EMBEDDED_PIC) | |
11313 | reloc->howto = NULL; | |
11314 | else | |
11315 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); | |
11316 | ||
11317 | if (reloc->howto == NULL) | |
11318 | { | |
11319 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
11320 | _("Can not represent %s relocation in this object file format"), | |
11321 | bfd_get_reloc_code_name (code)); | |
11322 | retval[0] = NULL; | |
11323 | } | |
11324 | ||
11325 | return retval; | |
11326 | } | |
11327 | ||
11328 | /* Relax a machine dependent frag. This returns the amount by which | |
11329 | the current size of the frag should change. */ | |
11330 | ||
11331 | int | |
11332 | mips_relax_frag (fragp, stretch) | |
11333 | fragS *fragp; | |
11334 | long stretch; | |
11335 | { | |
11336 | if (! RELAX_MIPS16_P (fragp->fr_subtype)) | |
11337 | return 0; | |
11338 | ||
11339 | if (mips16_extended_frag (fragp, (asection *) NULL, stretch)) | |
11340 | { | |
11341 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
11342 | return 0; | |
11343 | fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype); | |
11344 | return 2; | |
11345 | } | |
11346 | else | |
11347 | { | |
11348 | if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
11349 | return 0; | |
11350 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype); | |
11351 | return -2; | |
11352 | } | |
11353 | ||
11354 | return 0; | |
11355 | } | |
11356 | ||
11357 | /* Convert a machine dependent frag. */ | |
11358 | ||
11359 | void | |
11360 | md_convert_frag (abfd, asec, fragp) | |
43841e91 | 11361 | bfd *abfd ATTRIBUTE_UNUSED; |
252b5132 RH |
11362 | segT asec; |
11363 | fragS *fragp; | |
11364 | { | |
11365 | int old, new; | |
11366 | char *fixptr; | |
11367 | ||
11368 | if (RELAX_MIPS16_P (fragp->fr_subtype)) | |
11369 | { | |
11370 | int type; | |
11371 | register const struct mips16_immed_operand *op; | |
11372 | boolean small, ext; | |
11373 | offsetT val; | |
11374 | bfd_byte *buf; | |
11375 | unsigned long insn; | |
11376 | boolean use_extend; | |
11377 | unsigned short extend; | |
11378 | ||
11379 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
11380 | op = mips16_immed_operands; | |
11381 | while (op->type != type) | |
11382 | ++op; | |
11383 | ||
11384 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
11385 | { | |
11386 | small = false; | |
11387 | ext = true; | |
11388 | } | |
11389 | else | |
11390 | { | |
11391 | small = true; | |
11392 | ext = false; | |
11393 | } | |
11394 | ||
6386f3a7 | 11395 | resolve_symbol_value (fragp->fr_symbol); |
252b5132 RH |
11396 | val = S_GET_VALUE (fragp->fr_symbol); |
11397 | if (op->pcrel) | |
11398 | { | |
11399 | addressT addr; | |
11400 | ||
11401 | addr = fragp->fr_address + fragp->fr_fix; | |
11402 | ||
11403 | /* The rules for the base address of a PC relative reloc are | |
11404 | complicated; see mips16_extended_frag. */ | |
11405 | if (type == 'p' || type == 'q') | |
11406 | { | |
11407 | addr += 2; | |
11408 | if (ext) | |
11409 | addr += 2; | |
11410 | /* Ignore the low bit in the target, since it will be | |
11411 | set for a text label. */ | |
11412 | if ((val & 1) != 0) | |
11413 | --val; | |
11414 | } | |
11415 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) | |
11416 | addr -= 4; | |
11417 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
11418 | addr -= 2; | |
11419 | ||
11420 | addr &= ~ (addressT) ((1 << op->shift) - 1); | |
11421 | val -= addr; | |
11422 | ||
11423 | /* Make sure the section winds up with the alignment we have | |
11424 | assumed. */ | |
11425 | if (op->shift > 0) | |
11426 | record_alignment (asec, op->shift); | |
11427 | } | |
11428 | ||
11429 | if (ext | |
11430 | && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype) | |
11431 | || RELAX_MIPS16_DSLOT (fragp->fr_subtype))) | |
11432 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
11433 | _("extended instruction in delay slot")); | |
11434 | ||
11435 | buf = (bfd_byte *) (fragp->fr_literal + fragp->fr_fix); | |
11436 | ||
11437 | if (target_big_endian) | |
11438 | insn = bfd_getb16 (buf); | |
11439 | else | |
11440 | insn = bfd_getl16 (buf); | |
11441 | ||
11442 | mips16_immed (fragp->fr_file, fragp->fr_line, type, val, | |
11443 | RELAX_MIPS16_USER_EXT (fragp->fr_subtype), | |
11444 | small, ext, &insn, &use_extend, &extend); | |
11445 | ||
11446 | if (use_extend) | |
11447 | { | |
11448 | md_number_to_chars (buf, 0xf000 | extend, 2); | |
11449 | fragp->fr_fix += 2; | |
11450 | buf += 2; | |
11451 | } | |
11452 | ||
11453 | md_number_to_chars (buf, insn, 2); | |
11454 | fragp->fr_fix += 2; | |
11455 | buf += 2; | |
11456 | } | |
11457 | else | |
11458 | { | |
11459 | if (fragp->fr_opcode == NULL) | |
11460 | return; | |
11461 | ||
11462 | old = RELAX_OLD (fragp->fr_subtype); | |
11463 | new = RELAX_NEW (fragp->fr_subtype); | |
11464 | fixptr = fragp->fr_literal + fragp->fr_fix; | |
11465 | ||
11466 | if (new > 0) | |
11467 | memcpy (fixptr - old, fixptr, new); | |
11468 | ||
11469 | fragp->fr_fix += new - old; | |
11470 | } | |
11471 | } | |
11472 | ||
11473 | #ifdef OBJ_ELF | |
11474 | ||
11475 | /* This function is called after the relocs have been generated. | |
11476 | We've been storing mips16 text labels as odd. Here we convert them | |
11477 | back to even for the convenience of the debugger. */ | |
11478 | ||
11479 | void | |
11480 | mips_frob_file_after_relocs () | |
11481 | { | |
11482 | asymbol **syms; | |
11483 | unsigned int count, i; | |
11484 | ||
11485 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
11486 | return; | |
11487 | ||
11488 | syms = bfd_get_outsymbols (stdoutput); | |
11489 | count = bfd_get_symcount (stdoutput); | |
11490 | for (i = 0; i < count; i++, syms++) | |
11491 | { | |
11492 | if (elf_symbol (*syms)->internal_elf_sym.st_other == STO_MIPS16 | |
11493 | && ((*syms)->value & 1) != 0) | |
11494 | { | |
11495 | (*syms)->value &= ~1; | |
11496 | /* If the symbol has an odd size, it was probably computed | |
11497 | incorrectly, so adjust that as well. */ | |
11498 | if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0) | |
11499 | ++elf_symbol (*syms)->internal_elf_sym.st_size; | |
11500 | } | |
11501 | } | |
11502 | } | |
11503 | ||
11504 | #endif | |
11505 | ||
11506 | /* This function is called whenever a label is defined. It is used | |
11507 | when handling branch delays; if a branch has a label, we assume we | |
11508 | can not move it. */ | |
11509 | ||
11510 | void | |
11511 | mips_define_label (sym) | |
11512 | symbolS *sym; | |
11513 | { | |
11514 | struct insn_label_list *l; | |
11515 | ||
11516 | if (free_insn_labels == NULL) | |
11517 | l = (struct insn_label_list *) xmalloc (sizeof *l); | |
11518 | else | |
11519 | { | |
11520 | l = free_insn_labels; | |
11521 | free_insn_labels = l->next; | |
11522 | } | |
11523 | ||
11524 | l->label = sym; | |
11525 | l->next = insn_labels; | |
11526 | insn_labels = l; | |
11527 | } | |
11528 | \f | |
11529 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
11530 | ||
11531 | /* Some special processing for a MIPS ELF file. */ | |
11532 | ||
11533 | void | |
11534 | mips_elf_final_processing () | |
11535 | { | |
11536 | /* Write out the register information. */ | |
11537 | if (! mips_64) | |
11538 | { | |
11539 | Elf32_RegInfo s; | |
11540 | ||
11541 | s.ri_gprmask = mips_gprmask; | |
11542 | s.ri_cprmask[0] = mips_cprmask[0]; | |
11543 | s.ri_cprmask[1] = mips_cprmask[1]; | |
11544 | s.ri_cprmask[2] = mips_cprmask[2]; | |
11545 | s.ri_cprmask[3] = mips_cprmask[3]; | |
11546 | /* The gp_value field is set by the MIPS ELF backend. */ | |
11547 | ||
11548 | bfd_mips_elf32_swap_reginfo_out (stdoutput, &s, | |
11549 | ((Elf32_External_RegInfo *) | |
11550 | mips_regmask_frag)); | |
11551 | } | |
11552 | else | |
11553 | { | |
11554 | Elf64_Internal_RegInfo s; | |
11555 | ||
11556 | s.ri_gprmask = mips_gprmask; | |
11557 | s.ri_pad = 0; | |
11558 | s.ri_cprmask[0] = mips_cprmask[0]; | |
11559 | s.ri_cprmask[1] = mips_cprmask[1]; | |
11560 | s.ri_cprmask[2] = mips_cprmask[2]; | |
11561 | s.ri_cprmask[3] = mips_cprmask[3]; | |
11562 | /* The gp_value field is set by the MIPS ELF backend. */ | |
11563 | ||
11564 | bfd_mips_elf64_swap_reginfo_out (stdoutput, &s, | |
11565 | ((Elf64_External_RegInfo *) | |
11566 | mips_regmask_frag)); | |
11567 | } | |
11568 | ||
11569 | /* Set the MIPS ELF flag bits. FIXME: There should probably be some | |
11570 | sort of BFD interface for this. */ | |
11571 | if (mips_any_noreorder) | |
11572 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER; | |
11573 | if (mips_pic != NO_PIC) | |
11574 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC; | |
11575 | ||
bdaaa2e1 | 11576 | /* Set the MIPS ELF ABI flags. */ |
9a41af64 | 11577 | if (mips_abi_string == NULL) |
252b5132 | 11578 | ; |
beae10d5 | 11579 | else if (strcmp (mips_abi_string, "32") == 0) |
252b5132 | 11580 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32; |
beae10d5 | 11581 | else if (strcmp (mips_abi_string, "o64") == 0) |
252b5132 | 11582 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64; |
beae10d5 | 11583 | else if (strcmp (mips_abi_string, "eabi") == 0) |
252b5132 RH |
11584 | { |
11585 | if (mips_eabi64) | |
11586 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64; | |
11587 | else | |
11588 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32; | |
11589 | } | |
11590 | ||
11591 | if (mips_32bitmode) | |
11592 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE; | |
11593 | } | |
11594 | ||
11595 | #endif /* OBJ_ELF || OBJ_MAYBE_ELF */ | |
11596 | \f | |
beae10d5 KH |
11597 | typedef struct proc { |
11598 | symbolS *isym; | |
11599 | unsigned long reg_mask; | |
11600 | unsigned long reg_offset; | |
11601 | unsigned long fpreg_mask; | |
11602 | unsigned long fpreg_offset; | |
11603 | unsigned long frame_offset; | |
11604 | unsigned long frame_reg; | |
11605 | unsigned long pc_reg; | |
11606 | } procS; | |
252b5132 RH |
11607 | |
11608 | static procS cur_proc; | |
11609 | static procS *cur_proc_ptr; | |
11610 | static int numprocs; | |
11611 | ||
0a9ef439 | 11612 | /* Fill in an rs_align_code fragment. */ |
a19d8eb0 | 11613 | |
0a9ef439 RH |
11614 | void |
11615 | mips_handle_align (fragp) | |
11616 | fragS *fragp; | |
a19d8eb0 | 11617 | { |
0a9ef439 RH |
11618 | if (fragp->fr_type != rs_align_code) |
11619 | return; | |
11620 | ||
11621 | if (mips_opts.mips16) | |
a19d8eb0 CP |
11622 | { |
11623 | static const unsigned char be_nop[] = { 0x65, 0x00 }; | |
11624 | static const unsigned char le_nop[] = { 0x00, 0x65 }; | |
11625 | ||
0a9ef439 RH |
11626 | int bytes; |
11627 | char *p; | |
a19d8eb0 | 11628 | |
0a9ef439 RH |
11629 | bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix; |
11630 | p = fragp->fr_literal + fragp->fr_fix; | |
11631 | ||
11632 | if (bytes & 1) | |
11633 | { | |
11634 | *p++ = 0; | |
11635 | fragp->fr_fix += 1; | |
11636 | } | |
11637 | ||
11638 | memcpy (p, (target_big_endian ? be_nop : le_nop), 2); | |
11639 | fragp->fr_var = 2; | |
a19d8eb0 CP |
11640 | } |
11641 | ||
0a9ef439 | 11642 | /* For mips32, a nop is a zero, which we trivially get by doing nothing. */ |
a19d8eb0 CP |
11643 | } |
11644 | ||
252b5132 RH |
11645 | static void |
11646 | md_obj_begin () | |
11647 | { | |
11648 | } | |
11649 | ||
11650 | static void | |
11651 | md_obj_end () | |
11652 | { | |
11653 | /* check for premature end, nesting errors, etc */ | |
11654 | if (cur_proc_ptr) | |
9a41af64 | 11655 | as_warn (_("missing .end at end of assembly")); |
252b5132 RH |
11656 | } |
11657 | ||
11658 | static long | |
11659 | get_number () | |
11660 | { | |
11661 | int negative = 0; | |
11662 | long val = 0; | |
11663 | ||
11664 | if (*input_line_pointer == '-') | |
11665 | { | |
11666 | ++input_line_pointer; | |
11667 | negative = 1; | |
11668 | } | |
d9a62219 | 11669 | if (!isdigit ((unsigned char) *input_line_pointer)) |
252b5132 RH |
11670 | as_bad (_("Expected simple number.")); |
11671 | if (input_line_pointer[0] == '0') | |
11672 | { | |
11673 | if (input_line_pointer[1] == 'x') | |
11674 | { | |
11675 | input_line_pointer += 2; | |
d9a62219 | 11676 | while (isxdigit ((unsigned char) *input_line_pointer)) |
252b5132 RH |
11677 | { |
11678 | val <<= 4; | |
11679 | val |= hex_value (*input_line_pointer++); | |
11680 | } | |
11681 | return negative ? -val : val; | |
11682 | } | |
11683 | else | |
11684 | { | |
11685 | ++input_line_pointer; | |
d9a62219 | 11686 | while (isdigit ((unsigned char) *input_line_pointer)) |
252b5132 RH |
11687 | { |
11688 | val <<= 3; | |
11689 | val |= *input_line_pointer++ - '0'; | |
11690 | } | |
11691 | return negative ? -val : val; | |
11692 | } | |
11693 | } | |
d9a62219 | 11694 | if (!isdigit ((unsigned char) *input_line_pointer)) |
252b5132 RH |
11695 | { |
11696 | printf (_(" *input_line_pointer == '%c' 0x%02x\n"), | |
11697 | *input_line_pointer, *input_line_pointer); | |
11698 | as_warn (_("Invalid number")); | |
11699 | return -1; | |
11700 | } | |
d9a62219 | 11701 | while (isdigit ((unsigned char) *input_line_pointer)) |
252b5132 RH |
11702 | { |
11703 | val *= 10; | |
11704 | val += *input_line_pointer++ - '0'; | |
11705 | } | |
11706 | return negative ? -val : val; | |
11707 | } | |
11708 | ||
11709 | /* The .file directive; just like the usual .file directive, but there | |
11710 | is an initial number which is the ECOFF file index. */ | |
11711 | ||
11712 | static void | |
11713 | s_file (x) | |
43841e91 | 11714 | int x ATTRIBUTE_UNUSED; |
252b5132 RH |
11715 | { |
11716 | int line; | |
11717 | ||
11718 | line = get_number (); | |
11719 | s_app_file (0); | |
11720 | } | |
11721 | ||
252b5132 RH |
11722 | /* The .end directive. */ |
11723 | ||
11724 | static void | |
11725 | s_mips_end (x) | |
43841e91 | 11726 | int x ATTRIBUTE_UNUSED; |
252b5132 RH |
11727 | { |
11728 | symbolS *p; | |
11729 | int maybe_text; | |
11730 | ||
11731 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
11732 | { | |
11733 | p = get_symbol (); | |
11734 | demand_empty_rest_of_line (); | |
11735 | } | |
11736 | else | |
11737 | p = NULL; | |
11738 | ||
11739 | #ifdef BFD_ASSEMBLER | |
11740 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0) | |
11741 | maybe_text = 1; | |
11742 | else | |
11743 | maybe_text = 0; | |
11744 | #else | |
11745 | if (now_seg != data_section && now_seg != bss_section) | |
11746 | maybe_text = 1; | |
11747 | else | |
11748 | maybe_text = 0; | |
11749 | #endif | |
11750 | ||
11751 | if (!maybe_text) | |
11752 | as_warn (_(".end not in text section")); | |
11753 | ||
11754 | if (!cur_proc_ptr) | |
11755 | { | |
11756 | as_warn (_(".end directive without a preceding .ent directive.")); | |
11757 | demand_empty_rest_of_line (); | |
11758 | return; | |
11759 | } | |
11760 | ||
11761 | if (p != NULL) | |
11762 | { | |
11763 | assert (S_GET_NAME (p)); | |
11764 | if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->isym))) | |
11765 | as_warn (_(".end symbol does not match .ent symbol.")); | |
11766 | } | |
11767 | else | |
11768 | as_warn (_(".end directive missing or unknown symbol")); | |
11769 | ||
11770 | #ifdef MIPS_STABS_ELF | |
11771 | { | |
11772 | segT saved_seg = now_seg; | |
11773 | subsegT saved_subseg = now_subseg; | |
252b5132 | 11774 | valueT dot; |
252b5132 RH |
11775 | expressionS exp; |
11776 | char *fragp; | |
11777 | ||
11778 | dot = frag_now_fix (); | |
11779 | ||
11780 | #ifdef md_flush_pending_output | |
11781 | md_flush_pending_output (); | |
11782 | #endif | |
11783 | ||
11784 | assert (pdr_seg); | |
11785 | subseg_set (pdr_seg, 0); | |
11786 | ||
beae10d5 | 11787 | /* Write the symbol. */ |
252b5132 RH |
11788 | exp.X_op = O_symbol; |
11789 | exp.X_add_symbol = p; | |
11790 | exp.X_add_number = 0; | |
11791 | emit_expr (&exp, 4); | |
11792 | ||
beae10d5 | 11793 | fragp = frag_more (7 * 4); |
252b5132 | 11794 | |
beae10d5 KH |
11795 | md_number_to_chars (fragp, (valueT) cur_proc_ptr->reg_mask, 4); |
11796 | md_number_to_chars (fragp + 4, (valueT) cur_proc_ptr->reg_offset, 4); | |
11797 | md_number_to_chars (fragp + 8, (valueT) cur_proc_ptr->fpreg_mask, 4); | |
11798 | md_number_to_chars (fragp + 12, (valueT) cur_proc_ptr->fpreg_offset, 4); | |
11799 | md_number_to_chars (fragp + 16, (valueT) cur_proc_ptr->frame_offset, 4); | |
11800 | md_number_to_chars (fragp + 20, (valueT) cur_proc_ptr->frame_reg, 4); | |
11801 | md_number_to_chars (fragp + 24, (valueT) cur_proc_ptr->pc_reg, 4); | |
252b5132 RH |
11802 | |
11803 | subseg_set (saved_seg, saved_subseg); | |
11804 | } | |
11805 | #endif | |
11806 | ||
11807 | cur_proc_ptr = NULL; | |
11808 | } | |
11809 | ||
11810 | /* The .aent and .ent directives. */ | |
11811 | ||
11812 | static void | |
11813 | s_mips_ent (aent) | |
11814 | int aent; | |
11815 | { | |
11816 | int number = 0; | |
11817 | symbolS *symbolP; | |
11818 | int maybe_text; | |
11819 | ||
11820 | symbolP = get_symbol (); | |
11821 | if (*input_line_pointer == ',') | |
11822 | input_line_pointer++; | |
11823 | SKIP_WHITESPACE (); | |
d9a62219 DE |
11824 | if (isdigit ((unsigned char) *input_line_pointer) |
11825 | || *input_line_pointer == '-') | |
252b5132 RH |
11826 | number = get_number (); |
11827 | ||
11828 | #ifdef BFD_ASSEMBLER | |
11829 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0) | |
11830 | maybe_text = 1; | |
11831 | else | |
11832 | maybe_text = 0; | |
11833 | #else | |
11834 | if (now_seg != data_section && now_seg != bss_section) | |
11835 | maybe_text = 1; | |
11836 | else | |
11837 | maybe_text = 0; | |
11838 | #endif | |
11839 | ||
11840 | if (!maybe_text) | |
11841 | as_warn (_(".ent or .aent not in text section.")); | |
11842 | ||
11843 | if (!aent && cur_proc_ptr) | |
9a41af64 | 11844 | as_warn (_("missing .end")); |
252b5132 RH |
11845 | |
11846 | if (!aent) | |
11847 | { | |
11848 | cur_proc_ptr = &cur_proc; | |
11849 | memset (cur_proc_ptr, '\0', sizeof (procS)); | |
11850 | ||
11851 | cur_proc_ptr->isym = symbolP; | |
11852 | ||
49309057 | 11853 | symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION; |
252b5132 RH |
11854 | |
11855 | numprocs++; | |
11856 | } | |
11857 | ||
11858 | demand_empty_rest_of_line (); | |
11859 | } | |
11860 | ||
11861 | /* The .frame directive. If the mdebug section is present (IRIX 5 native) | |
bdaaa2e1 | 11862 | then ecoff.c (ecoff_directive_frame) is used. For embedded targets, |
252b5132 | 11863 | s_mips_frame is used so that we can set the PDR information correctly. |
bdaaa2e1 | 11864 | We can't use the ecoff routines because they make reference to the ecoff |
252b5132 RH |
11865 | symbol table (in the mdebug section). */ |
11866 | ||
11867 | static void | |
11868 | s_mips_frame (ignore) | |
2b3c5a5d | 11869 | int ignore ATTRIBUTE_UNUSED; |
252b5132 RH |
11870 | { |
11871 | #ifdef MIPS_STABS_ELF | |
11872 | ||
11873 | long val; | |
11874 | ||
beae10d5 | 11875 | if (cur_proc_ptr == (procS *) NULL) |
252b5132 RH |
11876 | { |
11877 | as_warn (_(".frame outside of .ent")); | |
11878 | demand_empty_rest_of_line (); | |
11879 | return; | |
11880 | } | |
11881 | ||
11882 | cur_proc_ptr->frame_reg = tc_get_register (1); | |
11883 | ||
11884 | SKIP_WHITESPACE (); | |
11885 | if (*input_line_pointer++ != ',' | |
11886 | || get_absolute_expression_and_terminator (&val) != ',') | |
11887 | { | |
11888 | as_warn (_("Bad .frame directive")); | |
11889 | --input_line_pointer; | |
11890 | demand_empty_rest_of_line (); | |
11891 | return; | |
11892 | } | |
11893 | ||
11894 | cur_proc_ptr->frame_offset = val; | |
11895 | cur_proc_ptr->pc_reg = tc_get_register (0); | |
11896 | ||
11897 | demand_empty_rest_of_line (); | |
11898 | #else | |
11899 | s_ignore (ignore); | |
11900 | #endif /* MIPS_STABS_ELF */ | |
11901 | } | |
11902 | ||
bdaaa2e1 KH |
11903 | /* The .fmask and .mask directives. If the mdebug section is present |
11904 | (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For | |
252b5132 | 11905 | embedded targets, s_mips_mask is used so that we can set the PDR |
bdaaa2e1 | 11906 | information correctly. We can't use the ecoff routines because they |
252b5132 RH |
11907 | make reference to the ecoff symbol table (in the mdebug section). */ |
11908 | ||
11909 | static void | |
11910 | s_mips_mask (reg_type) | |
11911 | char reg_type; | |
11912 | { | |
11913 | #ifdef MIPS_STABS_ELF | |
11914 | long mask, off; | |
bdaaa2e1 | 11915 | |
252b5132 RH |
11916 | if (cur_proc_ptr == (procS *) NULL) |
11917 | { | |
11918 | as_warn (_(".mask/.fmask outside of .ent")); | |
11919 | demand_empty_rest_of_line (); | |
11920 | return; | |
11921 | } | |
11922 | ||
11923 | if (get_absolute_expression_and_terminator (&mask) != ',') | |
11924 | { | |
11925 | as_warn (_("Bad .mask/.fmask directive")); | |
11926 | --input_line_pointer; | |
11927 | demand_empty_rest_of_line (); | |
11928 | return; | |
11929 | } | |
11930 | ||
11931 | off = get_absolute_expression (); | |
11932 | ||
11933 | if (reg_type == 'F') | |
11934 | { | |
11935 | cur_proc_ptr->fpreg_mask = mask; | |
11936 | cur_proc_ptr->fpreg_offset = off; | |
11937 | } | |
11938 | else | |
11939 | { | |
11940 | cur_proc_ptr->reg_mask = mask; | |
11941 | cur_proc_ptr->reg_offset = off; | |
11942 | } | |
11943 | ||
11944 | demand_empty_rest_of_line (); | |
11945 | #else | |
11946 | s_ignore (reg_type); | |
11947 | #endif /* MIPS_STABS_ELF */ | |
11948 | } | |
11949 | ||
11950 | /* The .loc directive. */ | |
11951 | ||
11952 | #if 0 | |
11953 | static void | |
11954 | s_loc (x) | |
11955 | int x; | |
11956 | { | |
11957 | symbolS *symbolP; | |
11958 | int lineno; | |
11959 | int addroff; | |
11960 | ||
11961 | assert (now_seg == text_section); | |
11962 | ||
11963 | lineno = get_number (); | |
11964 | addroff = frag_now_fix (); | |
11965 | ||
11966 | symbolP = symbol_new ("", N_SLINE, addroff, frag_now); | |
11967 | S_SET_TYPE (symbolP, N_SLINE); | |
11968 | S_SET_OTHER (symbolP, 0); | |
11969 | S_SET_DESC (symbolP, lineno); | |
11970 | symbolP->sy_segment = now_seg; | |
11971 | } | |
11972 | #endif | |
e7af610e NC |
11973 | |
11974 | /* CPU name/ISA/number mapping table. | |
11975 | ||
11976 | Entries are grouped by type. The first matching CPU or ISA entry | |
11977 | gets chosen by CPU or ISA, so it should be the 'canonical' name | |
11978 | for that type. Entries after that within the type are sorted | |
11979 | alphabetically. | |
11980 | ||
11981 | Case is ignored in comparison, so put the canonical entry in the | |
11982 | appropriate case but everything else in lower case to ease eye pain. */ | |
e972090a NC |
11983 | static const struct mips_cpu_info mips_cpu_info_table[] = |
11984 | { | |
e7af610e NC |
11985 | /* MIPS1 ISA */ |
11986 | { "MIPS1", 1, ISA_MIPS1, CPU_R3000, }, | |
11987 | { "mips", 1, ISA_MIPS1, CPU_R3000, }, | |
11988 | ||
11989 | /* MIPS2 ISA */ | |
11990 | { "MIPS2", 1, ISA_MIPS2, CPU_R6000, }, | |
11991 | ||
11992 | /* MIPS3 ISA */ | |
11993 | { "MIPS3", 1, ISA_MIPS3, CPU_R4000, }, | |
11994 | ||
11995 | /* MIPS4 ISA */ | |
11996 | { "MIPS4", 1, ISA_MIPS4, CPU_R8000, }, | |
11997 | ||
84ea6cf2 NC |
11998 | /* MIPS5 ISA */ |
11999 | { "MIPS5", 1, ISA_MIPS5, CPU_MIPS5, }, | |
12000 | { "Generic-MIPS5", 0, ISA_MIPS5, CPU_MIPS5, }, | |
12001 | ||
e7af610e NC |
12002 | /* MIPS32 ISA */ |
12003 | { "MIPS32", 1, ISA_MIPS32, CPU_MIPS32, }, | |
12004 | { "Generic-MIPS32", 0, ISA_MIPS32, CPU_MIPS32, }, | |
12005 | ||
84ea6cf2 | 12006 | #if 1 |
e7af610e NC |
12007 | /* XXX for now, MIPS64 -> MIPS3 because of history */ |
12008 | { "MIPS64", 1, ISA_MIPS3, CPU_R4000 }, /* XXX! */ | |
84ea6cf2 NC |
12009 | #else |
12010 | /* MIPS64 ISA */ | |
12011 | { "MIPS64", 1, ISA_MIPS64, CPU_MIPS64 }, | |
12012 | #endif | |
12013 | { "mips64isa", 1, ISA_MIPS64, CPU_MIPS64 }, | |
12014 | { "Generic-MIPS64", 0, ISA_MIPS64, CPU_MIPS64, }, | |
e7af610e NC |
12015 | |
12016 | /* R2000 CPU */ | |
12017 | { "R2000", 0, ISA_MIPS1, CPU_R2000, }, | |
12018 | { "2000", 0, ISA_MIPS1, CPU_R2000, }, | |
12019 | { "2k", 0, ISA_MIPS1, CPU_R2000, }, | |
12020 | { "r2k", 0, ISA_MIPS1, CPU_R2000, }, | |
12021 | ||
12022 | /* R3000 CPU */ | |
12023 | { "R3000", 0, ISA_MIPS1, CPU_R3000, }, | |
12024 | { "3000", 0, ISA_MIPS1, CPU_R3000, }, | |
12025 | { "3k", 0, ISA_MIPS1, CPU_R3000, }, | |
12026 | { "r3k", 0, ISA_MIPS1, CPU_R3000, }, | |
12027 | ||
12028 | /* TX3900 CPU */ | |
12029 | { "R3900", 0, ISA_MIPS1, CPU_R3900, }, | |
12030 | { "3900", 0, ISA_MIPS1, CPU_R3900, }, | |
e972090a | 12031 | { "mipstx39", 0, ISA_MIPS1, CPU_R3900, }, |
e7af610e NC |
12032 | |
12033 | /* R4000 CPU */ | |
12034 | { "R4000", 0, ISA_MIPS3, CPU_R4000, }, | |
12035 | { "4000", 0, ISA_MIPS3, CPU_R4000, }, | |
12036 | { "4k", 0, ISA_MIPS3, CPU_R4000, }, /* beware */ | |
12037 | { "r4k", 0, ISA_MIPS3, CPU_R4000, }, | |
12038 | ||
12039 | /* R4010 CPU */ | |
12040 | { "R4010", 0, ISA_MIPS2, CPU_R4010, }, | |
12041 | { "4010", 0, ISA_MIPS2, CPU_R4010, }, | |
12042 | ||
12043 | /* R4400 CPU */ | |
12044 | { "R4400", 0, ISA_MIPS3, CPU_R4400, }, | |
12045 | { "4400", 0, ISA_MIPS3, CPU_R4400, }, | |
12046 | ||
12047 | /* R4600 CPU */ | |
12048 | { "R4600", 0, ISA_MIPS3, CPU_R4600, }, | |
12049 | { "4600", 0, ISA_MIPS3, CPU_R4600, }, | |
12050 | { "mips64orion", 0, ISA_MIPS3, CPU_R4600, }, | |
12051 | { "orion", 0, ISA_MIPS3, CPU_R4600, }, | |
12052 | ||
12053 | /* R4650 CPU */ | |
12054 | { "R4650", 0, ISA_MIPS3, CPU_R4650, }, | |
12055 | { "4650", 0, ISA_MIPS3, CPU_R4650, }, | |
12056 | ||
12057 | /* R6000 CPU */ | |
12058 | { "R6000", 0, ISA_MIPS2, CPU_R6000, }, | |
12059 | { "6000", 0, ISA_MIPS2, CPU_R6000, }, | |
12060 | { "6k", 0, ISA_MIPS2, CPU_R6000, }, | |
12061 | { "r6k", 0, ISA_MIPS2, CPU_R6000, }, | |
12062 | ||
12063 | /* R8000 CPU */ | |
12064 | { "R8000", 0, ISA_MIPS4, CPU_R8000, }, | |
12065 | { "8000", 0, ISA_MIPS4, CPU_R8000, }, | |
12066 | { "8k", 0, ISA_MIPS4, CPU_R8000, }, | |
12067 | { "r8k", 0, ISA_MIPS4, CPU_R8000, }, | |
12068 | ||
12069 | /* R10000 CPU */ | |
12070 | { "R10000", 0, ISA_MIPS4, CPU_R10000, }, | |
12071 | { "10000", 0, ISA_MIPS4, CPU_R10000, }, | |
12072 | { "10k", 0, ISA_MIPS4, CPU_R10000, }, | |
12073 | { "r10k", 0, ISA_MIPS4, CPU_R10000, }, | |
12074 | ||
d1cf510e NC |
12075 | /* R12000 CPU */ |
12076 | { "R12000", 0, ISA_MIPS4, CPU_R12000, }, | |
12077 | { "12000", 0, ISA_MIPS4, CPU_R12000, }, | |
12078 | { "12k", 0, ISA_MIPS4, CPU_R12000, }, | |
12079 | { "r12k", 0, ISA_MIPS4, CPU_R12000, }, | |
12080 | ||
e7af610e NC |
12081 | /* VR4100 CPU */ |
12082 | { "VR4100", 0, ISA_MIPS3, CPU_VR4100, }, | |
12083 | { "4100", 0, ISA_MIPS3, CPU_VR4100, }, | |
12084 | { "mips64vr4100", 0, ISA_MIPS3, CPU_VR4100, }, | |
12085 | { "r4100", 0, ISA_MIPS3, CPU_VR4100, }, | |
12086 | ||
12087 | /* VR4111 CPU */ | |
12088 | { "VR4111", 0, ISA_MIPS3, CPU_R4111, }, | |
12089 | { "4111", 0, ISA_MIPS3, CPU_R4111, }, | |
12090 | { "mips64vr4111", 0, ISA_MIPS3, CPU_R4111, }, | |
12091 | { "r4111", 0, ISA_MIPS3, CPU_R4111, }, | |
12092 | ||
12093 | /* VR4300 CPU */ | |
12094 | { "VR4300", 0, ISA_MIPS3, CPU_R4300, }, | |
12095 | { "4300", 0, ISA_MIPS3, CPU_R4300, }, | |
12096 | { "mips64vr4300", 0, ISA_MIPS3, CPU_R4300, }, | |
12097 | { "r4300", 0, ISA_MIPS3, CPU_R4300, }, | |
12098 | ||
12099 | /* VR5000 CPU */ | |
12100 | { "VR5000", 0, ISA_MIPS4, CPU_R5000, }, | |
12101 | { "5000", 0, ISA_MIPS4, CPU_R5000, }, | |
12102 | { "5k", 0, ISA_MIPS4, CPU_R5000, }, | |
12103 | { "mips64vr5000", 0, ISA_MIPS4, CPU_R5000, }, | |
12104 | { "r5000", 0, ISA_MIPS4, CPU_R5000, }, | |
12105 | { "r5200", 0, ISA_MIPS4, CPU_R5000, }, | |
18ae5d72 | 12106 | { "rm5200", 0, ISA_MIPS4, CPU_R5000, }, |
e7af610e | 12107 | { "r5230", 0, ISA_MIPS4, CPU_R5000, }, |
18ae5d72 | 12108 | { "rm5230", 0, ISA_MIPS4, CPU_R5000, }, |
e7af610e | 12109 | { "r5231", 0, ISA_MIPS4, CPU_R5000, }, |
18ae5d72 | 12110 | { "rm5231", 0, ISA_MIPS4, CPU_R5000, }, |
e7af610e | 12111 | { "r5261", 0, ISA_MIPS4, CPU_R5000, }, |
18ae5d72 | 12112 | { "rm5261", 0, ISA_MIPS4, CPU_R5000, }, |
e7af610e | 12113 | { "r5721", 0, ISA_MIPS4, CPU_R5000, }, |
18ae5d72 | 12114 | { "rm5721", 0, ISA_MIPS4, CPU_R5000, }, |
e7af610e NC |
12115 | { "r5k", 0, ISA_MIPS4, CPU_R5000, }, |
12116 | { "r7000", 0, ISA_MIPS4, CPU_R5000, }, | |
12117 | ||
12118 | /* MIPS32 4K CPU */ | |
12119 | { "MIPS32-4K", 0, ISA_MIPS32, CPU_MIPS32_4K, }, | |
12120 | { "4kc", 0, ISA_MIPS32, CPU_MIPS32_4K, }, | |
12121 | { "4km", 0, ISA_MIPS32, CPU_MIPS32_4K, }, | |
12122 | { "4kp", 0, ISA_MIPS32, CPU_MIPS32_4K, }, | |
12123 | { "mips32-4kc", 0, ISA_MIPS32, CPU_MIPS32_4K, }, | |
12124 | { "mips32-4km", 0, ISA_MIPS32, CPU_MIPS32_4K, }, | |
12125 | { "mips32-4kp", 0, ISA_MIPS32, CPU_MIPS32_4K, }, | |
12126 | ||
c6c98b38 NC |
12127 | /* SiByte SB-1 CPU */ |
12128 | { "SB-1", 0, ISA_MIPS64, CPU_SB1, }, | |
e972090a | 12129 | { "sb-1250", 0, ISA_MIPS64, CPU_SB1, }, |
c6c98b38 NC |
12130 | { "sb1", 0, ISA_MIPS64, CPU_SB1, }, |
12131 | { "sb1250", 0, ISA_MIPS64, CPU_SB1, }, | |
12132 | ||
beae10d5 | 12133 | /* End marker. */ |
e7af610e NC |
12134 | { NULL, 0, 0, 0, }, |
12135 | }; | |
12136 | ||
12137 | static const struct mips_cpu_info * | |
12138 | mips_cpu_info_from_name (name) | |
12139 | const char *name; | |
12140 | { | |
12141 | int i; | |
12142 | ||
12143 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
beae10d5 | 12144 | if (strcasecmp (name, mips_cpu_info_table[i].name) == 0) |
e7af610e NC |
12145 | return (&mips_cpu_info_table[i]); |
12146 | ||
e972090a | 12147 | return NULL; |
e7af610e NC |
12148 | } |
12149 | ||
12150 | static const struct mips_cpu_info * | |
12151 | mips_cpu_info_from_isa (isa) | |
12152 | int isa; | |
12153 | { | |
12154 | int i; | |
12155 | ||
12156 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
12157 | if (mips_cpu_info_table[i].is_isa | |
12158 | && isa == mips_cpu_info_table[i].isa) | |
12159 | return (&mips_cpu_info_table[i]); | |
12160 | ||
e972090a | 12161 | return NULL; |
e7af610e NC |
12162 | } |
12163 | ||
12164 | static const struct mips_cpu_info * | |
12165 | mips_cpu_info_from_cpu (cpu) | |
12166 | int cpu; | |
12167 | { | |
12168 | int i; | |
12169 | ||
12170 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
12171 | if (!mips_cpu_info_table[i].is_isa | |
12172 | && cpu == mips_cpu_info_table[i].cpu) | |
12173 | return (&mips_cpu_info_table[i]); | |
12174 | ||
e972090a | 12175 | return NULL; |
e7af610e | 12176 | } |