Commit | Line | Data |
---|---|---|
252b5132 | 1 | /* tc-mips.c -- assemble code for a MIPS chip. |
81912461 | 2 | Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, |
f17c130b | 3 | 2003, 2004, 2005 Free Software Foundation, Inc. |
252b5132 RH |
4 | Contributed by the OSF and Ralph Campbell. |
5 | Written by Keith Knowles and Ralph Campbell, working independently. | |
6 | Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus | |
7 | Support. | |
8 | ||
9 | This file is part of GAS. | |
10 | ||
11 | GAS is free software; you can redistribute it and/or modify | |
12 | it under the terms of the GNU General Public License as published by | |
13 | the Free Software Foundation; either version 2, or (at your option) | |
14 | any later version. | |
15 | ||
16 | GAS is distributed in the hope that it will be useful, | |
17 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | GNU General Public License for more details. | |
20 | ||
21 | You should have received a copy of the GNU General Public License | |
22 | along with GAS; see the file COPYING. If not, write to the Free | |
23 | Software Foundation, 59 Temple Place - Suite 330, Boston, MA | |
24 | 02111-1307, USA. */ | |
25 | ||
26 | #include "as.h" | |
27 | #include "config.h" | |
28 | #include "subsegs.h" | |
3882b010 | 29 | #include "safe-ctype.h" |
252b5132 | 30 | |
252b5132 | 31 | #include <stdarg.h> |
252b5132 RH |
32 | |
33 | #include "opcode/mips.h" | |
34 | #include "itbl-ops.h" | |
c5dd6aab | 35 | #include "dwarf2dbg.h" |
252b5132 RH |
36 | |
37 | #ifdef DEBUG | |
38 | #define DBG(x) printf x | |
39 | #else | |
40 | #define DBG(x) | |
41 | #endif | |
42 | ||
43 | #ifdef OBJ_MAYBE_ELF | |
44 | /* Clean up namespace so we can include obj-elf.h too. */ | |
17a2f251 TS |
45 | static int mips_output_flavor (void); |
46 | static int mips_output_flavor (void) { return OUTPUT_FLAVOR; } | |
252b5132 RH |
47 | #undef OBJ_PROCESS_STAB |
48 | #undef OUTPUT_FLAVOR | |
49 | #undef S_GET_ALIGN | |
50 | #undef S_GET_SIZE | |
51 | #undef S_SET_ALIGN | |
52 | #undef S_SET_SIZE | |
252b5132 RH |
53 | #undef obj_frob_file |
54 | #undef obj_frob_file_after_relocs | |
55 | #undef obj_frob_symbol | |
56 | #undef obj_pop_insert | |
57 | #undef obj_sec_sym_ok_for_reloc | |
58 | #undef OBJ_COPY_SYMBOL_ATTRIBUTES | |
59 | ||
60 | #include "obj-elf.h" | |
61 | /* Fix any of them that we actually care about. */ | |
62 | #undef OUTPUT_FLAVOR | |
63 | #define OUTPUT_FLAVOR mips_output_flavor() | |
64 | #endif | |
65 | ||
66 | #if defined (OBJ_ELF) | |
67 | #include "elf/mips.h" | |
68 | #endif | |
69 | ||
70 | #ifndef ECOFF_DEBUGGING | |
71 | #define NO_ECOFF_DEBUGGING | |
72 | #define ECOFF_DEBUGGING 0 | |
73 | #endif | |
74 | ||
ecb4347a DJ |
75 | int mips_flag_mdebug = -1; |
76 | ||
dcd410fe RO |
77 | /* Control generation of .pdr sections. Off by default on IRIX: the native |
78 | linker doesn't know about and discards them, but relocations against them | |
79 | remain, leading to rld crashes. */ | |
80 | #ifdef TE_IRIX | |
81 | int mips_flag_pdr = FALSE; | |
82 | #else | |
83 | int mips_flag_pdr = TRUE; | |
84 | #endif | |
85 | ||
252b5132 RH |
86 | #include "ecoff.h" |
87 | ||
88 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
89 | static char *mips_regmask_frag; | |
90 | #endif | |
91 | ||
85b51719 | 92 | #define ZERO 0 |
252b5132 RH |
93 | #define AT 1 |
94 | #define TREG 24 | |
95 | #define PIC_CALL_REG 25 | |
96 | #define KT0 26 | |
97 | #define KT1 27 | |
98 | #define GP 28 | |
99 | #define SP 29 | |
100 | #define FP 30 | |
101 | #define RA 31 | |
102 | ||
103 | #define ILLEGAL_REG (32) | |
104 | ||
105 | /* Allow override of standard little-endian ECOFF format. */ | |
106 | ||
107 | #ifndef ECOFF_LITTLE_FORMAT | |
108 | #define ECOFF_LITTLE_FORMAT "ecoff-littlemips" | |
109 | #endif | |
110 | ||
111 | extern int target_big_endian; | |
112 | ||
252b5132 | 113 | /* The name of the readonly data section. */ |
4d0d148d | 114 | #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_ecoff_flavour \ |
252b5132 | 115 | ? ".rdata" \ |
056350c6 NC |
116 | : OUTPUT_FLAVOR == bfd_target_coff_flavour \ |
117 | ? ".rdata" \ | |
252b5132 RH |
118 | : OUTPUT_FLAVOR == bfd_target_elf_flavour \ |
119 | ? ".rodata" \ | |
120 | : (abort (), "")) | |
121 | ||
47e39b9d RS |
122 | /* Information about an instruction, including its format, operands |
123 | and fixups. */ | |
124 | struct mips_cl_insn | |
125 | { | |
126 | /* The opcode's entry in mips_opcodes or mips16_opcodes. */ | |
127 | const struct mips_opcode *insn_mo; | |
128 | ||
129 | /* True if this is a mips16 instruction and if we want the extended | |
130 | form of INSN_MO. */ | |
131 | bfd_boolean use_extend; | |
132 | ||
133 | /* The 16-bit extension instruction to use when USE_EXTEND is true. */ | |
134 | unsigned short extend; | |
135 | ||
136 | /* The 16-bit or 32-bit bitstring of the instruction itself. This is | |
137 | a copy of INSN_MO->match with the operands filled in. */ | |
138 | unsigned long insn_opcode; | |
139 | ||
140 | /* The frag that contains the instruction. */ | |
141 | struct frag *frag; | |
142 | ||
143 | /* The offset into FRAG of the first instruction byte. */ | |
144 | long where; | |
145 | ||
146 | /* The relocs associated with the instruction, if any. */ | |
147 | fixS *fixp[3]; | |
148 | ||
a38419a5 RS |
149 | /* True if this entry cannot be moved from its current position. */ |
150 | unsigned int fixed_p : 1; | |
47e39b9d RS |
151 | |
152 | /* True if this instruction occured in a .set noreorder block. */ | |
153 | unsigned int noreorder_p : 1; | |
154 | ||
2fa15973 RS |
155 | /* True for mips16 instructions that jump to an absolute address. */ |
156 | unsigned int mips16_absolute_jump_p : 1; | |
47e39b9d RS |
157 | }; |
158 | ||
a325df1d TS |
159 | /* The ABI to use. */ |
160 | enum mips_abi_level | |
161 | { | |
162 | NO_ABI = 0, | |
163 | O32_ABI, | |
164 | O64_ABI, | |
165 | N32_ABI, | |
166 | N64_ABI, | |
167 | EABI_ABI | |
168 | }; | |
169 | ||
170 | /* MIPS ABI we are using for this output file. */ | |
316f5878 | 171 | static enum mips_abi_level mips_abi = NO_ABI; |
a325df1d | 172 | |
143d77c5 EC |
173 | /* Whether or not we have code that can call pic code. */ |
174 | int mips_abicalls = FALSE; | |
175 | ||
aa6975fb ILT |
176 | /* Whether or not we have code which can be put into a shared |
177 | library. */ | |
178 | static bfd_boolean mips_in_shared = TRUE; | |
179 | ||
252b5132 RH |
180 | /* This is the set of options which may be modified by the .set |
181 | pseudo-op. We use a struct so that .set push and .set pop are more | |
182 | reliable. */ | |
183 | ||
e972090a NC |
184 | struct mips_set_options |
185 | { | |
252b5132 RH |
186 | /* MIPS ISA (Instruction Set Architecture) level. This is set to -1 |
187 | if it has not been initialized. Changed by `.set mipsN', and the | |
188 | -mipsN command line option, and the default CPU. */ | |
189 | int isa; | |
1f25f5d3 CD |
190 | /* Enabled Application Specific Extensions (ASEs). These are set to -1 |
191 | if they have not been initialized. Changed by `.set <asename>', by | |
192 | command line options, and based on the default architecture. */ | |
193 | int ase_mips3d; | |
deec1734 | 194 | int ase_mdmx; |
252b5132 RH |
195 | /* Whether we are assembling for the mips16 processor. 0 if we are |
196 | not, 1 if we are, and -1 if the value has not been initialized. | |
197 | Changed by `.set mips16' and `.set nomips16', and the -mips16 and | |
198 | -nomips16 command line options, and the default CPU. */ | |
199 | int mips16; | |
200 | /* Non-zero if we should not reorder instructions. Changed by `.set | |
201 | reorder' and `.set noreorder'. */ | |
202 | int noreorder; | |
203 | /* Non-zero if we should not permit the $at ($1) register to be used | |
204 | in instructions. Changed by `.set at' and `.set noat'. */ | |
205 | int noat; | |
206 | /* Non-zero if we should warn when a macro instruction expands into | |
207 | more than one machine instruction. Changed by `.set nomacro' and | |
208 | `.set macro'. */ | |
209 | int warn_about_macros; | |
210 | /* Non-zero if we should not move instructions. Changed by `.set | |
211 | move', `.set volatile', `.set nomove', and `.set novolatile'. */ | |
212 | int nomove; | |
213 | /* Non-zero if we should not optimize branches by moving the target | |
214 | of the branch into the delay slot. Actually, we don't perform | |
215 | this optimization anyhow. Changed by `.set bopt' and `.set | |
216 | nobopt'. */ | |
217 | int nobopt; | |
218 | /* Non-zero if we should not autoextend mips16 instructions. | |
219 | Changed by `.set autoextend' and `.set noautoextend'. */ | |
220 | int noautoextend; | |
a325df1d TS |
221 | /* Restrict general purpose registers and floating point registers |
222 | to 32 bit. This is initially determined when -mgp32 or -mfp32 | |
223 | is passed but can changed if the assembler code uses .set mipsN. */ | |
224 | int gp32; | |
225 | int fp32; | |
fef14a42 TS |
226 | /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march |
227 | command line option, and the default CPU. */ | |
228 | int arch; | |
aed1a261 RS |
229 | /* True if ".set sym32" is in effect. */ |
230 | bfd_boolean sym32; | |
252b5132 RH |
231 | }; |
232 | ||
a325df1d | 233 | /* True if -mgp32 was passed. */ |
a8e8e863 | 234 | static int file_mips_gp32 = -1; |
a325df1d TS |
235 | |
236 | /* True if -mfp32 was passed. */ | |
a8e8e863 | 237 | static int file_mips_fp32 = -1; |
a325df1d | 238 | |
252b5132 | 239 | /* This is the struct we use to hold the current set of options. Note |
a4672219 | 240 | that we must set the isa field to ISA_UNKNOWN and the ASE fields to |
e7af610e | 241 | -1 to indicate that they have not been initialized. */ |
252b5132 | 242 | |
e972090a NC |
243 | static struct mips_set_options mips_opts = |
244 | { | |
aed1a261 | 245 | ISA_UNKNOWN, -1, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0, CPU_UNKNOWN, FALSE |
e7af610e | 246 | }; |
252b5132 RH |
247 | |
248 | /* These variables are filled in with the masks of registers used. | |
249 | The object format code reads them and puts them in the appropriate | |
250 | place. */ | |
251 | unsigned long mips_gprmask; | |
252 | unsigned long mips_cprmask[4]; | |
253 | ||
254 | /* MIPS ISA we are using for this output file. */ | |
e7af610e | 255 | static int file_mips_isa = ISA_UNKNOWN; |
252b5132 | 256 | |
a4672219 TS |
257 | /* True if -mips16 was passed or implied by arguments passed on the |
258 | command line (e.g., by -march). */ | |
259 | static int file_ase_mips16; | |
260 | ||
1f25f5d3 CD |
261 | /* True if -mips3d was passed or implied by arguments passed on the |
262 | command line (e.g., by -march). */ | |
263 | static int file_ase_mips3d; | |
264 | ||
deec1734 CD |
265 | /* True if -mdmx was passed or implied by arguments passed on the |
266 | command line (e.g., by -march). */ | |
267 | static int file_ase_mdmx; | |
268 | ||
ec68c924 | 269 | /* The argument of the -march= flag. The architecture we are assembling. */ |
fef14a42 | 270 | static int file_mips_arch = CPU_UNKNOWN; |
316f5878 | 271 | static const char *mips_arch_string; |
ec68c924 EC |
272 | |
273 | /* The argument of the -mtune= flag. The architecture for which we | |
274 | are optimizing. */ | |
275 | static int mips_tune = CPU_UNKNOWN; | |
316f5878 | 276 | static const char *mips_tune_string; |
ec68c924 | 277 | |
316f5878 | 278 | /* True when generating 32-bit code for a 64-bit processor. */ |
252b5132 RH |
279 | static int mips_32bitmode = 0; |
280 | ||
316f5878 RS |
281 | /* True if the given ABI requires 32-bit registers. */ |
282 | #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI) | |
283 | ||
284 | /* Likewise 64-bit registers. */ | |
285 | #define ABI_NEEDS_64BIT_REGS(ABI) \ | |
286 | ((ABI) == N32_ABI \ | |
287 | || (ABI) == N64_ABI \ | |
288 | || (ABI) == O64_ABI) | |
289 | ||
bdaaa2e1 | 290 | /* Return true if ISA supports 64 bit gp register instructions. */ |
9ce8a5dd | 291 | #define ISA_HAS_64BIT_REGS(ISA) ( \ |
e7af610e NC |
292 | (ISA) == ISA_MIPS3 \ |
293 | || (ISA) == ISA_MIPS4 \ | |
84ea6cf2 | 294 | || (ISA) == ISA_MIPS5 \ |
d1cf510e | 295 | || (ISA) == ISA_MIPS64 \ |
5f74bc13 | 296 | || (ISA) == ISA_MIPS64R2 \ |
9ce8a5dd GRK |
297 | ) |
298 | ||
af7ee8bf CD |
299 | /* Return true if ISA supports 64-bit right rotate (dror et al.) |
300 | instructions. */ | |
301 | #define ISA_HAS_DROR(ISA) ( \ | |
5f74bc13 | 302 | (ISA) == ISA_MIPS64R2 \ |
af7ee8bf CD |
303 | ) |
304 | ||
305 | /* Return true if ISA supports 32-bit right rotate (ror et al.) | |
306 | instructions. */ | |
307 | #define ISA_HAS_ROR(ISA) ( \ | |
308 | (ISA) == ISA_MIPS32R2 \ | |
5f74bc13 | 309 | || (ISA) == ISA_MIPS64R2 \ |
af7ee8bf CD |
310 | ) |
311 | ||
e013f690 | 312 | #define HAVE_32BIT_GPRS \ |
316f5878 | 313 | (mips_opts.gp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
ca4e0257 | 314 | |
e013f690 | 315 | #define HAVE_32BIT_FPRS \ |
316f5878 | 316 | (mips_opts.fp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
ca4e0257 RS |
317 | |
318 | #define HAVE_64BIT_GPRS (! HAVE_32BIT_GPRS) | |
319 | #define HAVE_64BIT_FPRS (! HAVE_32BIT_FPRS) | |
320 | ||
316f5878 | 321 | #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI) |
e013f690 | 322 | |
316f5878 | 323 | #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI) |
e013f690 | 324 | |
3b91255e RS |
325 | /* True if relocations are stored in-place. */ |
326 | #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI) | |
327 | ||
aed1a261 RS |
328 | /* The ABI-derived address size. */ |
329 | #define HAVE_64BIT_ADDRESSES \ | |
330 | (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI)) | |
331 | #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES) | |
e013f690 | 332 | |
aed1a261 RS |
333 | /* The size of symbolic constants (i.e., expressions of the form |
334 | "SYMBOL" or "SYMBOL + OFFSET"). */ | |
335 | #define HAVE_32BIT_SYMBOLS \ | |
336 | (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32) | |
337 | #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS) | |
ca4e0257 | 338 | |
b7c7d6c1 TS |
339 | /* Addresses are loaded in different ways, depending on the address size |
340 | in use. The n32 ABI Documentation also mandates the use of additions | |
341 | with overflow checking, but existing implementations don't follow it. */ | |
f899b4b8 | 342 | #define ADDRESS_ADD_INSN \ |
b7c7d6c1 | 343 | (HAVE_32BIT_ADDRESSES ? "addu" : "daddu") |
f899b4b8 TS |
344 | |
345 | #define ADDRESS_ADDI_INSN \ | |
b7c7d6c1 | 346 | (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu") |
f899b4b8 TS |
347 | |
348 | #define ADDRESS_LOAD_INSN \ | |
349 | (HAVE_32BIT_ADDRESSES ? "lw" : "ld") | |
350 | ||
351 | #define ADDRESS_STORE_INSN \ | |
352 | (HAVE_32BIT_ADDRESSES ? "sw" : "sd") | |
353 | ||
a4672219 | 354 | /* Return true if the given CPU supports the MIPS16 ASE. */ |
3396de36 TS |
355 | #define CPU_HAS_MIPS16(cpu) \ |
356 | (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \ | |
357 | || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0) | |
a4672219 | 358 | |
1f25f5d3 CD |
359 | /* Return true if the given CPU supports the MIPS3D ASE. */ |
360 | #define CPU_HAS_MIPS3D(cpu) ((cpu) == CPU_SB1 \ | |
361 | ) | |
362 | ||
deec1734 | 363 | /* Return true if the given CPU supports the MDMX ASE. */ |
b34976b6 | 364 | #define CPU_HAS_MDMX(cpu) (FALSE \ |
deec1734 CD |
365 | ) |
366 | ||
60b63b72 RS |
367 | /* True if CPU has a dror instruction. */ |
368 | #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500) | |
369 | ||
370 | /* True if CPU has a ror instruction. */ | |
371 | #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU) | |
372 | ||
c8978940 CD |
373 | /* True if mflo and mfhi can be immediately followed by instructions |
374 | which write to the HI and LO registers. | |
375 | ||
376 | According to MIPS specifications, MIPS ISAs I, II, and III need | |
377 | (at least) two instructions between the reads of HI/LO and | |
378 | instructions which write them, and later ISAs do not. Contradicting | |
379 | the MIPS specifications, some MIPS IV processor user manuals (e.g. | |
380 | the UM for the NEC Vr5000) document needing the instructions between | |
381 | HI/LO reads and writes, as well. Therefore, we declare only MIPS32, | |
382 | MIPS64 and later ISAs to have the interlocks, plus any specific | |
383 | earlier-ISA CPUs for which CPU documentation declares that the | |
384 | instructions are really interlocked. */ | |
385 | #define hilo_interlocks \ | |
386 | (mips_opts.isa == ISA_MIPS32 \ | |
387 | || mips_opts.isa == ISA_MIPS32R2 \ | |
388 | || mips_opts.isa == ISA_MIPS64 \ | |
389 | || mips_opts.isa == ISA_MIPS64R2 \ | |
390 | || mips_opts.arch == CPU_R4010 \ | |
391 | || mips_opts.arch == CPU_R10000 \ | |
392 | || mips_opts.arch == CPU_R12000 \ | |
393 | || mips_opts.arch == CPU_RM7000 \ | |
c8978940 CD |
394 | || mips_opts.arch == CPU_VR5500 \ |
395 | ) | |
252b5132 RH |
396 | |
397 | /* Whether the processor uses hardware interlocks to protect reads | |
81912461 ILT |
398 | from the GPRs after they are loaded from memory, and thus does not |
399 | require nops to be inserted. This applies to instructions marked | |
400 | INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA | |
401 | level I. */ | |
252b5132 | 402 | #define gpr_interlocks \ |
e7af610e | 403 | (mips_opts.isa != ISA_MIPS1 \ |
fef14a42 | 404 | || mips_opts.arch == CPU_R3900) |
252b5132 | 405 | |
81912461 ILT |
406 | /* Whether the processor uses hardware interlocks to avoid delays |
407 | required by coprocessor instructions, and thus does not require | |
408 | nops to be inserted. This applies to instructions marked | |
409 | INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays | |
410 | between instructions marked INSN_WRITE_COND_CODE and ones marked | |
411 | INSN_READ_COND_CODE. These nops are only required at MIPS ISA | |
412 | levels I, II, and III. */ | |
bdaaa2e1 | 413 | /* Itbl support may require additional care here. */ |
81912461 ILT |
414 | #define cop_interlocks \ |
415 | ((mips_opts.isa != ISA_MIPS1 \ | |
416 | && mips_opts.isa != ISA_MIPS2 \ | |
417 | && mips_opts.isa != ISA_MIPS3) \ | |
418 | || mips_opts.arch == CPU_R4300 \ | |
81912461 ILT |
419 | ) |
420 | ||
421 | /* Whether the processor uses hardware interlocks to protect reads | |
422 | from coprocessor registers after they are loaded from memory, and | |
423 | thus does not require nops to be inserted. This applies to | |
424 | instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only | |
425 | requires at MIPS ISA level I. */ | |
426 | #define cop_mem_interlocks (mips_opts.isa != ISA_MIPS1) | |
252b5132 | 427 | |
6b76fefe CM |
428 | /* Is this a mfhi or mflo instruction? */ |
429 | #define MF_HILO_INSN(PINFO) \ | |
430 | ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO)) | |
431 | ||
252b5132 RH |
432 | /* MIPS PIC level. */ |
433 | ||
a161fe53 | 434 | enum mips_pic_level mips_pic; |
252b5132 | 435 | |
c9914766 | 436 | /* 1 if we should generate 32 bit offsets from the $gp register in |
252b5132 | 437 | SVR4_PIC mode. Currently has no meaning in other modes. */ |
c9914766 | 438 | static int mips_big_got = 0; |
252b5132 RH |
439 | |
440 | /* 1 if trap instructions should used for overflow rather than break | |
441 | instructions. */ | |
c9914766 | 442 | static int mips_trap = 0; |
252b5132 | 443 | |
119d663a | 444 | /* 1 if double width floating point constants should not be constructed |
b6ff326e | 445 | by assembling two single width halves into two single width floating |
119d663a NC |
446 | point registers which just happen to alias the double width destination |
447 | register. On some architectures this aliasing can be disabled by a bit | |
d547a75e | 448 | in the status register, and the setting of this bit cannot be determined |
119d663a NC |
449 | automatically at assemble time. */ |
450 | static int mips_disable_float_construction; | |
451 | ||
252b5132 RH |
452 | /* Non-zero if any .set noreorder directives were used. */ |
453 | ||
454 | static int mips_any_noreorder; | |
455 | ||
6b76fefe CM |
456 | /* Non-zero if nops should be inserted when the register referenced in |
457 | an mfhi/mflo instruction is read in the next two instructions. */ | |
458 | static int mips_7000_hilo_fix; | |
459 | ||
252b5132 | 460 | /* The size of the small data section. */ |
156c2f8b | 461 | static unsigned int g_switch_value = 8; |
252b5132 RH |
462 | /* Whether the -G option was used. */ |
463 | static int g_switch_seen = 0; | |
464 | ||
465 | #define N_RMASK 0xc4 | |
466 | #define N_VFP 0xd4 | |
467 | ||
468 | /* If we can determine in advance that GP optimization won't be | |
469 | possible, we can skip the relaxation stuff that tries to produce | |
470 | GP-relative references. This makes delay slot optimization work | |
471 | better. | |
472 | ||
473 | This function can only provide a guess, but it seems to work for | |
fba2b7f9 GK |
474 | gcc output. It needs to guess right for gcc, otherwise gcc |
475 | will put what it thinks is a GP-relative instruction in a branch | |
476 | delay slot. | |
252b5132 RH |
477 | |
478 | I don't know if a fix is needed for the SVR4_PIC mode. I've only | |
479 | fixed it for the non-PIC mode. KR 95/04/07 */ | |
17a2f251 | 480 | static int nopic_need_relax (symbolS *, int); |
252b5132 RH |
481 | |
482 | /* handle of the OPCODE hash table */ | |
483 | static struct hash_control *op_hash = NULL; | |
484 | ||
485 | /* The opcode hash table we use for the mips16. */ | |
486 | static struct hash_control *mips16_op_hash = NULL; | |
487 | ||
488 | /* This array holds the chars that always start a comment. If the | |
489 | pre-processor is disabled, these aren't very useful */ | |
490 | const char comment_chars[] = "#"; | |
491 | ||
492 | /* This array holds the chars that only start a comment at the beginning of | |
493 | a line. If the line seems to have the form '# 123 filename' | |
494 | .line and .file directives will appear in the pre-processed output */ | |
495 | /* Note that input_file.c hand checks for '#' at the beginning of the | |
496 | first line of the input file. This is because the compiler outputs | |
bdaaa2e1 | 497 | #NO_APP at the beginning of its output. */ |
252b5132 RH |
498 | /* Also note that C style comments are always supported. */ |
499 | const char line_comment_chars[] = "#"; | |
500 | ||
bdaaa2e1 | 501 | /* This array holds machine specific line separator characters. */ |
63a0b638 | 502 | const char line_separator_chars[] = ";"; |
252b5132 RH |
503 | |
504 | /* Chars that can be used to separate mant from exp in floating point nums */ | |
505 | const char EXP_CHARS[] = "eE"; | |
506 | ||
507 | /* Chars that mean this number is a floating point constant */ | |
508 | /* As in 0f12.456 */ | |
509 | /* or 0d1.2345e12 */ | |
510 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; | |
511 | ||
512 | /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be | |
513 | changed in read.c . Ideally it shouldn't have to know about it at all, | |
514 | but nothing is ideal around here. | |
515 | */ | |
516 | ||
517 | static char *insn_error; | |
518 | ||
519 | static int auto_align = 1; | |
520 | ||
521 | /* When outputting SVR4 PIC code, the assembler needs to know the | |
522 | offset in the stack frame from which to restore the $gp register. | |
523 | This is set by the .cprestore pseudo-op, and saved in this | |
524 | variable. */ | |
525 | static offsetT mips_cprestore_offset = -1; | |
526 | ||
67c1ffbe | 527 | /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some |
6478892d | 528 | more optimizations, it can use a register value instead of a memory-saved |
956cd1d6 | 529 | offset and even an other register than $gp as global pointer. */ |
6478892d TS |
530 | static offsetT mips_cpreturn_offset = -1; |
531 | static int mips_cpreturn_register = -1; | |
532 | static int mips_gp_register = GP; | |
def2e0dd | 533 | static int mips_gprel_offset = 0; |
6478892d | 534 | |
7a621144 DJ |
535 | /* Whether mips_cprestore_offset has been set in the current function |
536 | (or whether it has already been warned about, if not). */ | |
537 | static int mips_cprestore_valid = 0; | |
538 | ||
252b5132 RH |
539 | /* This is the register which holds the stack frame, as set by the |
540 | .frame pseudo-op. This is needed to implement .cprestore. */ | |
541 | static int mips_frame_reg = SP; | |
542 | ||
7a621144 DJ |
543 | /* Whether mips_frame_reg has been set in the current function |
544 | (or whether it has already been warned about, if not). */ | |
545 | static int mips_frame_reg_valid = 0; | |
546 | ||
252b5132 RH |
547 | /* To output NOP instructions correctly, we need to keep information |
548 | about the previous two instructions. */ | |
549 | ||
550 | /* Whether we are optimizing. The default value of 2 means to remove | |
551 | unneeded NOPs and swap branch instructions when possible. A value | |
552 | of 1 means to not swap branches. A value of 0 means to always | |
553 | insert NOPs. */ | |
554 | static int mips_optimize = 2; | |
555 | ||
556 | /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is | |
557 | equivalent to seeing no -g option at all. */ | |
558 | static int mips_debug = 0; | |
559 | ||
47e39b9d RS |
560 | /* A list of previous instructions, with index 0 being the most recent. */ |
561 | static struct mips_cl_insn history[2]; | |
252b5132 | 562 | |
1e915849 RS |
563 | /* Nop instructions used by emit_nop. */ |
564 | static struct mips_cl_insn nop_insn, mips16_nop_insn; | |
565 | ||
566 | /* The appropriate nop for the current mode. */ | |
567 | #define NOP_INSN (mips_opts.mips16 ? &mips16_nop_insn : &nop_insn) | |
252b5132 | 568 | |
252b5132 RH |
569 | /* If this is set, it points to a frag holding nop instructions which |
570 | were inserted before the start of a noreorder section. If those | |
571 | nops turn out to be unnecessary, the size of the frag can be | |
572 | decreased. */ | |
573 | static fragS *prev_nop_frag; | |
574 | ||
575 | /* The number of nop instructions we created in prev_nop_frag. */ | |
576 | static int prev_nop_frag_holds; | |
577 | ||
578 | /* The number of nop instructions that we know we need in | |
bdaaa2e1 | 579 | prev_nop_frag. */ |
252b5132 RH |
580 | static int prev_nop_frag_required; |
581 | ||
582 | /* The number of instructions we've seen since prev_nop_frag. */ | |
583 | static int prev_nop_frag_since; | |
584 | ||
585 | /* For ECOFF and ELF, relocations against symbols are done in two | |
586 | parts, with a HI relocation and a LO relocation. Each relocation | |
587 | has only 16 bits of space to store an addend. This means that in | |
588 | order for the linker to handle carries correctly, it must be able | |
589 | to locate both the HI and the LO relocation. This means that the | |
590 | relocations must appear in order in the relocation table. | |
591 | ||
592 | In order to implement this, we keep track of each unmatched HI | |
593 | relocation. We then sort them so that they immediately precede the | |
bdaaa2e1 | 594 | corresponding LO relocation. */ |
252b5132 | 595 | |
e972090a NC |
596 | struct mips_hi_fixup |
597 | { | |
252b5132 RH |
598 | /* Next HI fixup. */ |
599 | struct mips_hi_fixup *next; | |
600 | /* This fixup. */ | |
601 | fixS *fixp; | |
602 | /* The section this fixup is in. */ | |
603 | segT seg; | |
604 | }; | |
605 | ||
606 | /* The list of unmatched HI relocs. */ | |
607 | ||
608 | static struct mips_hi_fixup *mips_hi_fixup_list; | |
609 | ||
64bdfcaf RS |
610 | /* The frag containing the last explicit relocation operator. |
611 | Null if explicit relocations have not been used. */ | |
612 | ||
613 | static fragS *prev_reloc_op_frag; | |
614 | ||
252b5132 RH |
615 | /* Map normal MIPS register numbers to mips16 register numbers. */ |
616 | ||
617 | #define X ILLEGAL_REG | |
e972090a NC |
618 | static const int mips32_to_16_reg_map[] = |
619 | { | |
252b5132 RH |
620 | X, X, 2, 3, 4, 5, 6, 7, |
621 | X, X, X, X, X, X, X, X, | |
622 | 0, 1, X, X, X, X, X, X, | |
623 | X, X, X, X, X, X, X, X | |
624 | }; | |
625 | #undef X | |
626 | ||
627 | /* Map mips16 register numbers to normal MIPS register numbers. */ | |
628 | ||
e972090a NC |
629 | static const unsigned int mips16_to_32_reg_map[] = |
630 | { | |
252b5132 RH |
631 | 16, 17, 2, 3, 4, 5, 6, 7 |
632 | }; | |
60b63b72 | 633 | |
d766e8ec | 634 | static int mips_fix_vr4120; |
4a6a3df4 AO |
635 | |
636 | /* We don't relax branches by default, since this causes us to expand | |
637 | `la .l2 - .l1' if there's a branch between .l1 and .l2, because we | |
638 | fail to compute the offset before expanding the macro to the most | |
639 | efficient expansion. */ | |
640 | ||
641 | static int mips_relax_branch; | |
252b5132 | 642 | \f |
4d7206a2 RS |
643 | /* The expansion of many macros depends on the type of symbol that |
644 | they refer to. For example, when generating position-dependent code, | |
645 | a macro that refers to a symbol may have two different expansions, | |
646 | one which uses GP-relative addresses and one which uses absolute | |
647 | addresses. When generating SVR4-style PIC, a macro may have | |
648 | different expansions for local and global symbols. | |
649 | ||
650 | We handle these situations by generating both sequences and putting | |
651 | them in variant frags. In position-dependent code, the first sequence | |
652 | will be the GP-relative one and the second sequence will be the | |
653 | absolute one. In SVR4 PIC, the first sequence will be for global | |
654 | symbols and the second will be for local symbols. | |
655 | ||
584892a6 RS |
656 | The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and |
657 | SECOND are the lengths of the two sequences in bytes. These fields | |
658 | can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition, | |
659 | the subtype has the following flags: | |
4d7206a2 | 660 | |
584892a6 RS |
661 | RELAX_USE_SECOND |
662 | Set if it has been decided that we should use the second | |
663 | sequence instead of the first. | |
664 | ||
665 | RELAX_SECOND_LONGER | |
666 | Set in the first variant frag if the macro's second implementation | |
667 | is longer than its first. This refers to the macro as a whole, | |
668 | not an individual relaxation. | |
669 | ||
670 | RELAX_NOMACRO | |
671 | Set in the first variant frag if the macro appeared in a .set nomacro | |
672 | block and if one alternative requires a warning but the other does not. | |
673 | ||
674 | RELAX_DELAY_SLOT | |
675 | Like RELAX_NOMACRO, but indicates that the macro appears in a branch | |
676 | delay slot. | |
4d7206a2 RS |
677 | |
678 | The frag's "opcode" points to the first fixup for relaxable code. | |
679 | ||
680 | Relaxable macros are generated using a sequence such as: | |
681 | ||
682 | relax_start (SYMBOL); | |
683 | ... generate first expansion ... | |
684 | relax_switch (); | |
685 | ... generate second expansion ... | |
686 | relax_end (); | |
687 | ||
688 | The code and fixups for the unwanted alternative are discarded | |
689 | by md_convert_frag. */ | |
584892a6 | 690 | #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND)) |
4d7206a2 | 691 | |
584892a6 RS |
692 | #define RELAX_FIRST(X) (((X) >> 8) & 0xff) |
693 | #define RELAX_SECOND(X) ((X) & 0xff) | |
694 | #define RELAX_USE_SECOND 0x10000 | |
695 | #define RELAX_SECOND_LONGER 0x20000 | |
696 | #define RELAX_NOMACRO 0x40000 | |
697 | #define RELAX_DELAY_SLOT 0x80000 | |
252b5132 | 698 | |
4a6a3df4 AO |
699 | /* Branch without likely bit. If label is out of range, we turn: |
700 | ||
701 | beq reg1, reg2, label | |
702 | delay slot | |
703 | ||
704 | into | |
705 | ||
706 | bne reg1, reg2, 0f | |
707 | nop | |
708 | j label | |
709 | 0: delay slot | |
710 | ||
711 | with the following opcode replacements: | |
712 | ||
713 | beq <-> bne | |
714 | blez <-> bgtz | |
715 | bltz <-> bgez | |
716 | bc1f <-> bc1t | |
717 | ||
718 | bltzal <-> bgezal (with jal label instead of j label) | |
719 | ||
720 | Even though keeping the delay slot instruction in the delay slot of | |
721 | the branch would be more efficient, it would be very tricky to do | |
722 | correctly, because we'd have to introduce a variable frag *after* | |
723 | the delay slot instruction, and expand that instead. Let's do it | |
724 | the easy way for now, even if the branch-not-taken case now costs | |
725 | one additional instruction. Out-of-range branches are not supposed | |
726 | to be common, anyway. | |
727 | ||
728 | Branch likely. If label is out of range, we turn: | |
729 | ||
730 | beql reg1, reg2, label | |
731 | delay slot (annulled if branch not taken) | |
732 | ||
733 | into | |
734 | ||
735 | beql reg1, reg2, 1f | |
736 | nop | |
737 | beql $0, $0, 2f | |
738 | nop | |
739 | 1: j[al] label | |
740 | delay slot (executed only if branch taken) | |
741 | 2: | |
742 | ||
743 | It would be possible to generate a shorter sequence by losing the | |
744 | likely bit, generating something like: | |
b34976b6 | 745 | |
4a6a3df4 AO |
746 | bne reg1, reg2, 0f |
747 | nop | |
748 | j[al] label | |
749 | delay slot (executed only if branch taken) | |
750 | 0: | |
751 | ||
752 | beql -> bne | |
753 | bnel -> beq | |
754 | blezl -> bgtz | |
755 | bgtzl -> blez | |
756 | bltzl -> bgez | |
757 | bgezl -> bltz | |
758 | bc1fl -> bc1t | |
759 | bc1tl -> bc1f | |
760 | ||
761 | bltzall -> bgezal (with jal label instead of j label) | |
762 | bgezall -> bltzal (ditto) | |
763 | ||
764 | ||
765 | but it's not clear that it would actually improve performance. */ | |
af6ae2ad | 766 | #define RELAX_BRANCH_ENCODE(uncond, likely, link, toofar) \ |
4a6a3df4 AO |
767 | ((relax_substateT) \ |
768 | (0xc0000000 \ | |
769 | | ((toofar) ? 1 : 0) \ | |
770 | | ((link) ? 2 : 0) \ | |
771 | | ((likely) ? 4 : 0) \ | |
af6ae2ad | 772 | | ((uncond) ? 8 : 0))) |
4a6a3df4 | 773 | #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000) |
4a6a3df4 AO |
774 | #define RELAX_BRANCH_UNCOND(i) (((i) & 8) != 0) |
775 | #define RELAX_BRANCH_LIKELY(i) (((i) & 4) != 0) | |
776 | #define RELAX_BRANCH_LINK(i) (((i) & 2) != 0) | |
ae6063d4 | 777 | #define RELAX_BRANCH_TOOFAR(i) (((i) & 1) != 0) |
4a6a3df4 | 778 | |
252b5132 RH |
779 | /* For mips16 code, we use an entirely different form of relaxation. |
780 | mips16 supports two versions of most instructions which take | |
781 | immediate values: a small one which takes some small value, and a | |
782 | larger one which takes a 16 bit value. Since branches also follow | |
783 | this pattern, relaxing these values is required. | |
784 | ||
785 | We can assemble both mips16 and normal MIPS code in a single | |
786 | object. Therefore, we need to support this type of relaxation at | |
787 | the same time that we support the relaxation described above. We | |
788 | use the high bit of the subtype field to distinguish these cases. | |
789 | ||
790 | The information we store for this type of relaxation is the | |
791 | argument code found in the opcode file for this relocation, whether | |
792 | the user explicitly requested a small or extended form, and whether | |
793 | the relocation is in a jump or jal delay slot. That tells us the | |
794 | size of the value, and how it should be stored. We also store | |
795 | whether the fragment is considered to be extended or not. We also | |
796 | store whether this is known to be a branch to a different section, | |
797 | whether we have tried to relax this frag yet, and whether we have | |
798 | ever extended a PC relative fragment because of a shift count. */ | |
799 | #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \ | |
800 | (0x80000000 \ | |
801 | | ((type) & 0xff) \ | |
802 | | ((small) ? 0x100 : 0) \ | |
803 | | ((ext) ? 0x200 : 0) \ | |
804 | | ((dslot) ? 0x400 : 0) \ | |
805 | | ((jal_dslot) ? 0x800 : 0)) | |
4a6a3df4 | 806 | #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000) |
252b5132 RH |
807 | #define RELAX_MIPS16_TYPE(i) ((i) & 0xff) |
808 | #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0) | |
809 | #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0) | |
810 | #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0) | |
811 | #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0) | |
812 | #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0) | |
813 | #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000) | |
814 | #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000) | |
815 | #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0) | |
816 | #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000) | |
817 | #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000) | |
885add95 CD |
818 | |
819 | /* Is the given value a sign-extended 32-bit value? */ | |
820 | #define IS_SEXT_32BIT_NUM(x) \ | |
821 | (((x) &~ (offsetT) 0x7fffffff) == 0 \ | |
822 | || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff)) | |
823 | ||
824 | /* Is the given value a sign-extended 16-bit value? */ | |
825 | #define IS_SEXT_16BIT_NUM(x) \ | |
826 | (((x) &~ (offsetT) 0x7fff) == 0 \ | |
827 | || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff)) | |
828 | ||
bf12938e RS |
829 | /* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in |
830 | VALUE << SHIFT. VALUE is evaluated exactly once. */ | |
831 | #define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \ | |
832 | (STRUCT) = (((STRUCT) & ~((MASK) << (SHIFT))) \ | |
833 | | (((VALUE) & (MASK)) << (SHIFT))) | |
834 | ||
835 | /* Extract bits MASK << SHIFT from STRUCT and shift them right | |
836 | SHIFT places. */ | |
837 | #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \ | |
838 | (((STRUCT) >> (SHIFT)) & (MASK)) | |
839 | ||
840 | /* Change INSN's opcode so that the operand given by FIELD has value VALUE. | |
841 | INSN is a mips_cl_insn structure and VALUE is evaluated exactly once. | |
842 | ||
843 | include/opcode/mips.h specifies operand fields using the macros | |
844 | OP_MASK_<FIELD> and OP_SH_<FIELD>. The MIPS16 equivalents start | |
845 | with "MIPS16OP" instead of "OP". */ | |
846 | #define INSERT_OPERAND(FIELD, INSN, VALUE) \ | |
847 | INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD) | |
848 | #define MIPS16_INSERT_OPERAND(FIELD, INSN, VALUE) \ | |
849 | INSERT_BITS ((INSN).insn_opcode, VALUE, \ | |
850 | MIPS16OP_MASK_##FIELD, MIPS16OP_SH_##FIELD) | |
851 | ||
852 | /* Extract the operand given by FIELD from mips_cl_insn INSN. */ | |
853 | #define EXTRACT_OPERAND(FIELD, INSN) \ | |
854 | EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) | |
855 | #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \ | |
856 | EXTRACT_BITS ((INSN).insn_opcode, \ | |
857 | MIPS16OP_MASK_##FIELD, \ | |
858 | MIPS16OP_SH_##FIELD) | |
4d7206a2 RS |
859 | \f |
860 | /* Global variables used when generating relaxable macros. See the | |
861 | comment above RELAX_ENCODE for more details about how relaxation | |
862 | is used. */ | |
863 | static struct { | |
864 | /* 0 if we're not emitting a relaxable macro. | |
865 | 1 if we're emitting the first of the two relaxation alternatives. | |
866 | 2 if we're emitting the second alternative. */ | |
867 | int sequence; | |
868 | ||
869 | /* The first relaxable fixup in the current frag. (In other words, | |
870 | the first fixup that refers to relaxable code.) */ | |
871 | fixS *first_fixup; | |
872 | ||
873 | /* sizes[0] says how many bytes of the first alternative are stored in | |
874 | the current frag. Likewise sizes[1] for the second alternative. */ | |
875 | unsigned int sizes[2]; | |
876 | ||
877 | /* The symbol on which the choice of sequence depends. */ | |
878 | symbolS *symbol; | |
879 | } mips_relax; | |
252b5132 | 880 | \f |
584892a6 RS |
881 | /* Global variables used to decide whether a macro needs a warning. */ |
882 | static struct { | |
883 | /* True if the macro is in a branch delay slot. */ | |
884 | bfd_boolean delay_slot_p; | |
885 | ||
886 | /* For relaxable macros, sizes[0] is the length of the first alternative | |
887 | in bytes and sizes[1] is the length of the second alternative. | |
888 | For non-relaxable macros, both elements give the length of the | |
889 | macro in bytes. */ | |
890 | unsigned int sizes[2]; | |
891 | ||
892 | /* The first variant frag for this macro. */ | |
893 | fragS *first_frag; | |
894 | } mips_macro_warning; | |
895 | \f | |
252b5132 RH |
896 | /* Prototypes for static functions. */ |
897 | ||
17a2f251 | 898 | #define internalError() \ |
252b5132 | 899 | as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__) |
252b5132 RH |
900 | |
901 | enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG }; | |
902 | ||
b34976b6 | 903 | static void append_insn |
4d7206a2 | 904 | (struct mips_cl_insn *ip, expressionS *p, bfd_reloc_code_real_type *r); |
17a2f251 | 905 | static void mips_no_prev_insn (int); |
b34976b6 | 906 | static void mips16_macro_build |
67c0d1eb RS |
907 | (expressionS *, const char *, const char *, va_list); |
908 | static void load_register (int, expressionS *, int); | |
584892a6 RS |
909 | static void macro_start (void); |
910 | static void macro_end (void); | |
17a2f251 TS |
911 | static void macro (struct mips_cl_insn * ip); |
912 | static void mips16_macro (struct mips_cl_insn * ip); | |
252b5132 | 913 | #ifdef LOSING_COMPILER |
17a2f251 | 914 | static void macro2 (struct mips_cl_insn * ip); |
252b5132 | 915 | #endif |
17a2f251 TS |
916 | static void mips_ip (char *str, struct mips_cl_insn * ip); |
917 | static void mips16_ip (char *str, struct mips_cl_insn * ip); | |
b34976b6 | 918 | static void mips16_immed |
17a2f251 TS |
919 | (char *, unsigned int, int, offsetT, bfd_boolean, bfd_boolean, bfd_boolean, |
920 | unsigned long *, bfd_boolean *, unsigned short *); | |
5e0116d5 | 921 | static size_t my_getSmallExpression |
17a2f251 TS |
922 | (expressionS *, bfd_reloc_code_real_type *, char *); |
923 | static void my_getExpression (expressionS *, char *); | |
924 | static void s_align (int); | |
925 | static void s_change_sec (int); | |
926 | static void s_change_section (int); | |
927 | static void s_cons (int); | |
928 | static void s_float_cons (int); | |
929 | static void s_mips_globl (int); | |
930 | static void s_option (int); | |
931 | static void s_mipsset (int); | |
932 | static void s_abicalls (int); | |
933 | static void s_cpload (int); | |
934 | static void s_cpsetup (int); | |
935 | static void s_cplocal (int); | |
936 | static void s_cprestore (int); | |
937 | static void s_cpreturn (int); | |
938 | static void s_gpvalue (int); | |
939 | static void s_gpword (int); | |
940 | static void s_gpdword (int); | |
941 | static void s_cpadd (int); | |
942 | static void s_insn (int); | |
943 | static void md_obj_begin (void); | |
944 | static void md_obj_end (void); | |
945 | static void s_mips_ent (int); | |
946 | static void s_mips_end (int); | |
947 | static void s_mips_frame (int); | |
948 | static void s_mips_mask (int reg_type); | |
949 | static void s_mips_stab (int); | |
950 | static void s_mips_weakext (int); | |
951 | static void s_mips_file (int); | |
952 | static void s_mips_loc (int); | |
953 | static bfd_boolean pic_need_relax (symbolS *, asection *); | |
4a6a3df4 | 954 | static int relaxed_branch_length (fragS *, asection *, int); |
17a2f251 | 955 | static int validate_mips_insn (const struct mips_opcode *); |
e7af610e NC |
956 | |
957 | /* Table and functions used to map between CPU/ISA names, and | |
958 | ISA levels, and CPU numbers. */ | |
959 | ||
e972090a NC |
960 | struct mips_cpu_info |
961 | { | |
e7af610e NC |
962 | const char *name; /* CPU or ISA name. */ |
963 | int is_isa; /* Is this an ISA? (If 0, a CPU.) */ | |
964 | int isa; /* ISA level. */ | |
965 | int cpu; /* CPU number (default CPU if ISA). */ | |
966 | }; | |
967 | ||
17a2f251 TS |
968 | static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *); |
969 | static const struct mips_cpu_info *mips_cpu_info_from_isa (int); | |
970 | static const struct mips_cpu_info *mips_cpu_info_from_arch (int); | |
252b5132 RH |
971 | \f |
972 | /* Pseudo-op table. | |
973 | ||
974 | The following pseudo-ops from the Kane and Heinrich MIPS book | |
975 | should be defined here, but are currently unsupported: .alias, | |
976 | .galive, .gjaldef, .gjrlive, .livereg, .noalias. | |
977 | ||
978 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
979 | specific to the type of debugging information being generated, and | |
980 | should be defined by the object format: .aent, .begin, .bend, | |
981 | .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp, | |
982 | .vreg. | |
983 | ||
984 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
985 | not MIPS CPU specific, but are also not specific to the object file | |
986 | format. This file is probably the best place to define them, but | |
987 | they are not currently supported: .asm0, .endr, .lab, .repeat, | |
988 | .struct. */ | |
989 | ||
e972090a NC |
990 | static const pseudo_typeS mips_pseudo_table[] = |
991 | { | |
beae10d5 | 992 | /* MIPS specific pseudo-ops. */ |
252b5132 RH |
993 | {"option", s_option, 0}, |
994 | {"set", s_mipsset, 0}, | |
995 | {"rdata", s_change_sec, 'r'}, | |
996 | {"sdata", s_change_sec, 's'}, | |
997 | {"livereg", s_ignore, 0}, | |
998 | {"abicalls", s_abicalls, 0}, | |
999 | {"cpload", s_cpload, 0}, | |
6478892d TS |
1000 | {"cpsetup", s_cpsetup, 0}, |
1001 | {"cplocal", s_cplocal, 0}, | |
252b5132 | 1002 | {"cprestore", s_cprestore, 0}, |
6478892d TS |
1003 | {"cpreturn", s_cpreturn, 0}, |
1004 | {"gpvalue", s_gpvalue, 0}, | |
252b5132 | 1005 | {"gpword", s_gpword, 0}, |
10181a0d | 1006 | {"gpdword", s_gpdword, 0}, |
252b5132 RH |
1007 | {"cpadd", s_cpadd, 0}, |
1008 | {"insn", s_insn, 0}, | |
1009 | ||
beae10d5 | 1010 | /* Relatively generic pseudo-ops that happen to be used on MIPS |
252b5132 RH |
1011 | chips. */ |
1012 | {"asciiz", stringer, 1}, | |
1013 | {"bss", s_change_sec, 'b'}, | |
1014 | {"err", s_err, 0}, | |
1015 | {"half", s_cons, 1}, | |
1016 | {"dword", s_cons, 3}, | |
1017 | {"weakext", s_mips_weakext, 0}, | |
1018 | ||
beae10d5 | 1019 | /* These pseudo-ops are defined in read.c, but must be overridden |
252b5132 RH |
1020 | here for one reason or another. */ |
1021 | {"align", s_align, 0}, | |
1022 | {"byte", s_cons, 0}, | |
1023 | {"data", s_change_sec, 'd'}, | |
1024 | {"double", s_float_cons, 'd'}, | |
1025 | {"float", s_float_cons, 'f'}, | |
1026 | {"globl", s_mips_globl, 0}, | |
1027 | {"global", s_mips_globl, 0}, | |
1028 | {"hword", s_cons, 1}, | |
1029 | {"int", s_cons, 2}, | |
1030 | {"long", s_cons, 2}, | |
1031 | {"octa", s_cons, 4}, | |
1032 | {"quad", s_cons, 3}, | |
cca86cc8 | 1033 | {"section", s_change_section, 0}, |
252b5132 RH |
1034 | {"short", s_cons, 1}, |
1035 | {"single", s_float_cons, 'f'}, | |
1036 | {"stabn", s_mips_stab, 'n'}, | |
1037 | {"text", s_change_sec, 't'}, | |
1038 | {"word", s_cons, 2}, | |
add56521 | 1039 | |
add56521 | 1040 | { "extern", ecoff_directive_extern, 0}, |
add56521 | 1041 | |
43841e91 | 1042 | { NULL, NULL, 0 }, |
252b5132 RH |
1043 | }; |
1044 | ||
e972090a NC |
1045 | static const pseudo_typeS mips_nonecoff_pseudo_table[] = |
1046 | { | |
beae10d5 KH |
1047 | /* These pseudo-ops should be defined by the object file format. |
1048 | However, a.out doesn't support them, so we have versions here. */ | |
252b5132 RH |
1049 | {"aent", s_mips_ent, 1}, |
1050 | {"bgnb", s_ignore, 0}, | |
1051 | {"end", s_mips_end, 0}, | |
1052 | {"endb", s_ignore, 0}, | |
1053 | {"ent", s_mips_ent, 0}, | |
c5dd6aab | 1054 | {"file", s_mips_file, 0}, |
252b5132 RH |
1055 | {"fmask", s_mips_mask, 'F'}, |
1056 | {"frame", s_mips_frame, 0}, | |
c5dd6aab | 1057 | {"loc", s_mips_loc, 0}, |
252b5132 RH |
1058 | {"mask", s_mips_mask, 'R'}, |
1059 | {"verstamp", s_ignore, 0}, | |
43841e91 | 1060 | { NULL, NULL, 0 }, |
252b5132 RH |
1061 | }; |
1062 | ||
17a2f251 | 1063 | extern void pop_insert (const pseudo_typeS *); |
252b5132 RH |
1064 | |
1065 | void | |
17a2f251 | 1066 | mips_pop_insert (void) |
252b5132 RH |
1067 | { |
1068 | pop_insert (mips_pseudo_table); | |
1069 | if (! ECOFF_DEBUGGING) | |
1070 | pop_insert (mips_nonecoff_pseudo_table); | |
1071 | } | |
1072 | \f | |
1073 | /* Symbols labelling the current insn. */ | |
1074 | ||
e972090a NC |
1075 | struct insn_label_list |
1076 | { | |
252b5132 RH |
1077 | struct insn_label_list *next; |
1078 | symbolS *label; | |
1079 | }; | |
1080 | ||
1081 | static struct insn_label_list *insn_labels; | |
1082 | static struct insn_label_list *free_insn_labels; | |
1083 | ||
17a2f251 | 1084 | static void mips_clear_insn_labels (void); |
252b5132 RH |
1085 | |
1086 | static inline void | |
17a2f251 | 1087 | mips_clear_insn_labels (void) |
252b5132 RH |
1088 | { |
1089 | register struct insn_label_list **pl; | |
1090 | ||
1091 | for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next) | |
1092 | ; | |
1093 | *pl = insn_labels; | |
1094 | insn_labels = NULL; | |
1095 | } | |
1096 | \f | |
1097 | static char *expr_end; | |
1098 | ||
1099 | /* Expressions which appear in instructions. These are set by | |
1100 | mips_ip. */ | |
1101 | ||
1102 | static expressionS imm_expr; | |
5f74bc13 | 1103 | static expressionS imm2_expr; |
252b5132 RH |
1104 | static expressionS offset_expr; |
1105 | ||
1106 | /* Relocs associated with imm_expr and offset_expr. */ | |
1107 | ||
f6688943 TS |
1108 | static bfd_reloc_code_real_type imm_reloc[3] |
1109 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
1110 | static bfd_reloc_code_real_type offset_reloc[3] | |
1111 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 1112 | |
252b5132 RH |
1113 | /* These are set by mips16_ip if an explicit extension is used. */ |
1114 | ||
b34976b6 | 1115 | static bfd_boolean mips16_small, mips16_ext; |
252b5132 | 1116 | |
7ed4a06a | 1117 | #ifdef OBJ_ELF |
ecb4347a DJ |
1118 | /* The pdr segment for per procedure frame/regmask info. Not used for |
1119 | ECOFF debugging. */ | |
252b5132 RH |
1120 | |
1121 | static segT pdr_seg; | |
7ed4a06a | 1122 | #endif |
252b5132 | 1123 | |
e013f690 TS |
1124 | /* The default target format to use. */ |
1125 | ||
1126 | const char * | |
17a2f251 | 1127 | mips_target_format (void) |
e013f690 TS |
1128 | { |
1129 | switch (OUTPUT_FLAVOR) | |
1130 | { | |
e013f690 TS |
1131 | case bfd_target_ecoff_flavour: |
1132 | return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT; | |
1133 | case bfd_target_coff_flavour: | |
1134 | return "pe-mips"; | |
1135 | case bfd_target_elf_flavour: | |
1136 | #ifdef TE_TMIPS | |
cfe86eaa | 1137 | /* This is traditional mips. */ |
e013f690 | 1138 | return (target_big_endian |
cfe86eaa TS |
1139 | ? (HAVE_64BIT_OBJECTS |
1140 | ? "elf64-tradbigmips" | |
1141 | : (HAVE_NEWABI | |
1142 | ? "elf32-ntradbigmips" : "elf32-tradbigmips")) | |
1143 | : (HAVE_64BIT_OBJECTS | |
1144 | ? "elf64-tradlittlemips" | |
1145 | : (HAVE_NEWABI | |
1146 | ? "elf32-ntradlittlemips" : "elf32-tradlittlemips"))); | |
e013f690 TS |
1147 | #else |
1148 | return (target_big_endian | |
cfe86eaa TS |
1149 | ? (HAVE_64BIT_OBJECTS |
1150 | ? "elf64-bigmips" | |
1151 | : (HAVE_NEWABI | |
1152 | ? "elf32-nbigmips" : "elf32-bigmips")) | |
1153 | : (HAVE_64BIT_OBJECTS | |
1154 | ? "elf64-littlemips" | |
1155 | : (HAVE_NEWABI | |
1156 | ? "elf32-nlittlemips" : "elf32-littlemips"))); | |
e013f690 TS |
1157 | #endif |
1158 | default: | |
1159 | abort (); | |
1160 | return NULL; | |
1161 | } | |
1162 | } | |
1163 | ||
1e915849 RS |
1164 | /* Return the length of instruction INSN. */ |
1165 | ||
1166 | static inline unsigned int | |
1167 | insn_length (const struct mips_cl_insn *insn) | |
1168 | { | |
1169 | if (!mips_opts.mips16) | |
1170 | return 4; | |
1171 | return insn->mips16_absolute_jump_p || insn->use_extend ? 4 : 2; | |
1172 | } | |
1173 | ||
1174 | /* Initialise INSN from opcode entry MO. Leave its position unspecified. */ | |
1175 | ||
1176 | static void | |
1177 | create_insn (struct mips_cl_insn *insn, const struct mips_opcode *mo) | |
1178 | { | |
1179 | size_t i; | |
1180 | ||
1181 | insn->insn_mo = mo; | |
1182 | insn->use_extend = FALSE; | |
1183 | insn->extend = 0; | |
1184 | insn->insn_opcode = mo->match; | |
1185 | insn->frag = NULL; | |
1186 | insn->where = 0; | |
1187 | for (i = 0; i < ARRAY_SIZE (insn->fixp); i++) | |
1188 | insn->fixp[i] = NULL; | |
1189 | insn->fixed_p = (mips_opts.noreorder > 0); | |
1190 | insn->noreorder_p = (mips_opts.noreorder > 0); | |
1191 | insn->mips16_absolute_jump_p = 0; | |
1192 | } | |
1193 | ||
1194 | /* Install INSN at the location specified by its "frag" and "where" fields. */ | |
1195 | ||
1196 | static void | |
1197 | install_insn (const struct mips_cl_insn *insn) | |
1198 | { | |
1199 | char *f = insn->frag->fr_literal + insn->where; | |
1200 | if (!mips_opts.mips16) | |
1201 | md_number_to_chars (f, insn->insn_opcode, 4); | |
1202 | else if (insn->mips16_absolute_jump_p) | |
1203 | { | |
1204 | md_number_to_chars (f, insn->insn_opcode >> 16, 2); | |
1205 | md_number_to_chars (f + 2, insn->insn_opcode & 0xffff, 2); | |
1206 | } | |
1207 | else | |
1208 | { | |
1209 | if (insn->use_extend) | |
1210 | { | |
1211 | md_number_to_chars (f, 0xf000 | insn->extend, 2); | |
1212 | f += 2; | |
1213 | } | |
1214 | md_number_to_chars (f, insn->insn_opcode, 2); | |
1215 | } | |
1216 | } | |
1217 | ||
1218 | /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly | |
1219 | and install the opcode in the new location. */ | |
1220 | ||
1221 | static void | |
1222 | move_insn (struct mips_cl_insn *insn, fragS *frag, long where) | |
1223 | { | |
1224 | size_t i; | |
1225 | ||
1226 | insn->frag = frag; | |
1227 | insn->where = where; | |
1228 | for (i = 0; i < ARRAY_SIZE (insn->fixp); i++) | |
1229 | if (insn->fixp[i] != NULL) | |
1230 | { | |
1231 | insn->fixp[i]->fx_frag = frag; | |
1232 | insn->fixp[i]->fx_where = where; | |
1233 | } | |
1234 | install_insn (insn); | |
1235 | } | |
1236 | ||
1237 | /* Add INSN to the end of the output. */ | |
1238 | ||
1239 | static void | |
1240 | add_fixed_insn (struct mips_cl_insn *insn) | |
1241 | { | |
1242 | char *f = frag_more (insn_length (insn)); | |
1243 | move_insn (insn, frag_now, f - frag_now->fr_literal); | |
1244 | } | |
1245 | ||
1246 | /* Start a variant frag and move INSN to the start of the variant part, | |
1247 | marking it as fixed. The other arguments are as for frag_var. */ | |
1248 | ||
1249 | static void | |
1250 | add_relaxed_insn (struct mips_cl_insn *insn, int max_chars, int var, | |
1251 | relax_substateT subtype, symbolS *symbol, offsetT offset) | |
1252 | { | |
1253 | frag_grow (max_chars); | |
1254 | move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal); | |
1255 | insn->fixed_p = 1; | |
1256 | frag_var (rs_machine_dependent, max_chars, var, | |
1257 | subtype, symbol, offset, NULL); | |
1258 | } | |
1259 | ||
1260 | /* Insert N copies of INSN into the history buffer, starting at | |
1261 | position FIRST. Neither FIRST nor N need to be clipped. */ | |
1262 | ||
1263 | static void | |
1264 | insert_into_history (unsigned int first, unsigned int n, | |
1265 | const struct mips_cl_insn *insn) | |
1266 | { | |
1267 | if (mips_relax.sequence != 2) | |
1268 | { | |
1269 | unsigned int i; | |
1270 | ||
1271 | for (i = ARRAY_SIZE (history); i-- > first;) | |
1272 | if (i >= first + n) | |
1273 | history[i] = history[i - n]; | |
1274 | else | |
1275 | history[i] = *insn; | |
1276 | } | |
1277 | } | |
1278 | ||
1279 | /* Emit a nop instruction, recording it in the history buffer. */ | |
1280 | ||
1281 | static void | |
1282 | emit_nop (void) | |
1283 | { | |
1284 | add_fixed_insn (NOP_INSN); | |
1285 | insert_into_history (0, 1, NOP_INSN); | |
1286 | } | |
1287 | ||
156c2f8b NC |
1288 | /* This function is called once, at assembler startup time. It should |
1289 | set up all the tables, etc. that the MD part of the assembler will need. */ | |
1290 | ||
252b5132 | 1291 | void |
17a2f251 | 1292 | md_begin (void) |
252b5132 | 1293 | { |
252b5132 | 1294 | register const char *retval = NULL; |
156c2f8b | 1295 | int i = 0; |
252b5132 | 1296 | int broken = 0; |
1f25f5d3 | 1297 | |
fef14a42 | 1298 | if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_arch)) |
252b5132 RH |
1299 | as_warn (_("Could not set architecture and machine")); |
1300 | ||
252b5132 RH |
1301 | op_hash = hash_new (); |
1302 | ||
1303 | for (i = 0; i < NUMOPCODES;) | |
1304 | { | |
1305 | const char *name = mips_opcodes[i].name; | |
1306 | ||
17a2f251 | 1307 | retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]); |
252b5132 RH |
1308 | if (retval != NULL) |
1309 | { | |
1310 | fprintf (stderr, _("internal error: can't hash `%s': %s\n"), | |
1311 | mips_opcodes[i].name, retval); | |
1312 | /* Probably a memory allocation problem? Give up now. */ | |
1313 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
1314 | } | |
1315 | do | |
1316 | { | |
1317 | if (mips_opcodes[i].pinfo != INSN_MACRO) | |
1318 | { | |
1319 | if (!validate_mips_insn (&mips_opcodes[i])) | |
1320 | broken = 1; | |
1e915849 RS |
1321 | if (nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0) |
1322 | { | |
1323 | create_insn (&nop_insn, mips_opcodes + i); | |
1324 | nop_insn.fixed_p = 1; | |
1325 | } | |
252b5132 RH |
1326 | } |
1327 | ++i; | |
1328 | } | |
1329 | while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name)); | |
1330 | } | |
1331 | ||
1332 | mips16_op_hash = hash_new (); | |
1333 | ||
1334 | i = 0; | |
1335 | while (i < bfd_mips16_num_opcodes) | |
1336 | { | |
1337 | const char *name = mips16_opcodes[i].name; | |
1338 | ||
17a2f251 | 1339 | retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]); |
252b5132 RH |
1340 | if (retval != NULL) |
1341 | as_fatal (_("internal: can't hash `%s': %s"), | |
1342 | mips16_opcodes[i].name, retval); | |
1343 | do | |
1344 | { | |
1345 | if (mips16_opcodes[i].pinfo != INSN_MACRO | |
1346 | && ((mips16_opcodes[i].match & mips16_opcodes[i].mask) | |
1347 | != mips16_opcodes[i].match)) | |
1348 | { | |
1349 | fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"), | |
1350 | mips16_opcodes[i].name, mips16_opcodes[i].args); | |
1351 | broken = 1; | |
1352 | } | |
1e915849 RS |
1353 | if (mips16_nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0) |
1354 | { | |
1355 | create_insn (&mips16_nop_insn, mips16_opcodes + i); | |
1356 | mips16_nop_insn.fixed_p = 1; | |
1357 | } | |
252b5132 RH |
1358 | ++i; |
1359 | } | |
1360 | while (i < bfd_mips16_num_opcodes | |
1361 | && strcmp (mips16_opcodes[i].name, name) == 0); | |
1362 | } | |
1363 | ||
1364 | if (broken) | |
1365 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
1366 | ||
1367 | /* We add all the general register names to the symbol table. This | |
1368 | helps us detect invalid uses of them. */ | |
1369 | for (i = 0; i < 32; i++) | |
1370 | { | |
1371 | char buf[5]; | |
1372 | ||
1373 | sprintf (buf, "$%d", i); | |
1374 | symbol_table_insert (symbol_new (buf, reg_section, i, | |
1375 | &zero_address_frag)); | |
1376 | } | |
76db943d TS |
1377 | symbol_table_insert (symbol_new ("$ra", reg_section, RA, |
1378 | &zero_address_frag)); | |
252b5132 RH |
1379 | symbol_table_insert (symbol_new ("$fp", reg_section, FP, |
1380 | &zero_address_frag)); | |
1381 | symbol_table_insert (symbol_new ("$sp", reg_section, SP, | |
1382 | &zero_address_frag)); | |
1383 | symbol_table_insert (symbol_new ("$gp", reg_section, GP, | |
1384 | &zero_address_frag)); | |
1385 | symbol_table_insert (symbol_new ("$at", reg_section, AT, | |
1386 | &zero_address_frag)); | |
1387 | symbol_table_insert (symbol_new ("$kt0", reg_section, KT0, | |
1388 | &zero_address_frag)); | |
1389 | symbol_table_insert (symbol_new ("$kt1", reg_section, KT1, | |
1390 | &zero_address_frag)); | |
85b51719 TS |
1391 | symbol_table_insert (symbol_new ("$zero", reg_section, ZERO, |
1392 | &zero_address_frag)); | |
252b5132 RH |
1393 | symbol_table_insert (symbol_new ("$pc", reg_section, -1, |
1394 | &zero_address_frag)); | |
1395 | ||
6047c971 AO |
1396 | /* If we don't add these register names to the symbol table, they |
1397 | may end up being added as regular symbols by operand(), and then | |
1398 | make it to the object file as undefined in case they're not | |
1399 | regarded as local symbols. They're local in o32, since `$' is a | |
1400 | local symbol prefix, but not in n32 or n64. */ | |
1401 | for (i = 0; i < 8; i++) | |
1402 | { | |
1403 | char buf[6]; | |
1404 | ||
1405 | sprintf (buf, "$fcc%i", i); | |
1406 | symbol_table_insert (symbol_new (buf, reg_section, -1, | |
1407 | &zero_address_frag)); | |
1408 | } | |
1409 | ||
b34976b6 | 1410 | mips_no_prev_insn (FALSE); |
252b5132 RH |
1411 | |
1412 | mips_gprmask = 0; | |
1413 | mips_cprmask[0] = 0; | |
1414 | mips_cprmask[1] = 0; | |
1415 | mips_cprmask[2] = 0; | |
1416 | mips_cprmask[3] = 0; | |
1417 | ||
1418 | /* set the default alignment for the text section (2**2) */ | |
1419 | record_alignment (text_section, 2); | |
1420 | ||
4d0d148d | 1421 | bfd_set_gp_size (stdoutput, g_switch_value); |
252b5132 RH |
1422 | |
1423 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
1424 | { | |
1425 | /* On a native system, sections must be aligned to 16 byte | |
1426 | boundaries. When configured for an embedded ELF target, we | |
1427 | don't bother. */ | |
1428 | if (strcmp (TARGET_OS, "elf") != 0) | |
1429 | { | |
1430 | (void) bfd_set_section_alignment (stdoutput, text_section, 4); | |
1431 | (void) bfd_set_section_alignment (stdoutput, data_section, 4); | |
1432 | (void) bfd_set_section_alignment (stdoutput, bss_section, 4); | |
1433 | } | |
1434 | ||
1435 | /* Create a .reginfo section for register masks and a .mdebug | |
1436 | section for debugging information. */ | |
1437 | { | |
1438 | segT seg; | |
1439 | subsegT subseg; | |
1440 | flagword flags; | |
1441 | segT sec; | |
1442 | ||
1443 | seg = now_seg; | |
1444 | subseg = now_subseg; | |
1445 | ||
1446 | /* The ABI says this section should be loaded so that the | |
1447 | running program can access it. However, we don't load it | |
1448 | if we are configured for an embedded target */ | |
1449 | flags = SEC_READONLY | SEC_DATA; | |
1450 | if (strcmp (TARGET_OS, "elf") != 0) | |
1451 | flags |= SEC_ALLOC | SEC_LOAD; | |
1452 | ||
316f5878 | 1453 | if (mips_abi != N64_ABI) |
252b5132 RH |
1454 | { |
1455 | sec = subseg_new (".reginfo", (subsegT) 0); | |
1456 | ||
195325d2 TS |
1457 | bfd_set_section_flags (stdoutput, sec, flags); |
1458 | bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2); | |
bdaaa2e1 | 1459 | |
252b5132 RH |
1460 | #ifdef OBJ_ELF |
1461 | mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo)); | |
1462 | #endif | |
1463 | } | |
1464 | else | |
1465 | { | |
1466 | /* The 64-bit ABI uses a .MIPS.options section rather than | |
1467 | .reginfo section. */ | |
1468 | sec = subseg_new (".MIPS.options", (subsegT) 0); | |
195325d2 TS |
1469 | bfd_set_section_flags (stdoutput, sec, flags); |
1470 | bfd_set_section_alignment (stdoutput, sec, 3); | |
252b5132 RH |
1471 | |
1472 | #ifdef OBJ_ELF | |
1473 | /* Set up the option header. */ | |
1474 | { | |
1475 | Elf_Internal_Options opthdr; | |
1476 | char *f; | |
1477 | ||
1478 | opthdr.kind = ODK_REGINFO; | |
1479 | opthdr.size = (sizeof (Elf_External_Options) | |
1480 | + sizeof (Elf64_External_RegInfo)); | |
1481 | opthdr.section = 0; | |
1482 | opthdr.info = 0; | |
1483 | f = frag_more (sizeof (Elf_External_Options)); | |
1484 | bfd_mips_elf_swap_options_out (stdoutput, &opthdr, | |
1485 | (Elf_External_Options *) f); | |
1486 | ||
1487 | mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo)); | |
1488 | } | |
1489 | #endif | |
1490 | } | |
1491 | ||
1492 | if (ECOFF_DEBUGGING) | |
1493 | { | |
1494 | sec = subseg_new (".mdebug", (subsegT) 0); | |
1495 | (void) bfd_set_section_flags (stdoutput, sec, | |
1496 | SEC_HAS_CONTENTS | SEC_READONLY); | |
1497 | (void) bfd_set_section_alignment (stdoutput, sec, 2); | |
1498 | } | |
ecb4347a | 1499 | #ifdef OBJ_ELF |
dcd410fe | 1500 | else if (OUTPUT_FLAVOR == bfd_target_elf_flavour && mips_flag_pdr) |
ecb4347a DJ |
1501 | { |
1502 | pdr_seg = subseg_new (".pdr", (subsegT) 0); | |
1503 | (void) bfd_set_section_flags (stdoutput, pdr_seg, | |
1504 | SEC_READONLY | SEC_RELOC | |
1505 | | SEC_DEBUGGING); | |
1506 | (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2); | |
1507 | } | |
252b5132 RH |
1508 | #endif |
1509 | ||
1510 | subseg_set (seg, subseg); | |
1511 | } | |
1512 | } | |
1513 | ||
1514 | if (! ECOFF_DEBUGGING) | |
1515 | md_obj_begin (); | |
1516 | } | |
1517 | ||
1518 | void | |
17a2f251 | 1519 | md_mips_end (void) |
252b5132 RH |
1520 | { |
1521 | if (! ECOFF_DEBUGGING) | |
1522 | md_obj_end (); | |
1523 | } | |
1524 | ||
1525 | void | |
17a2f251 | 1526 | md_assemble (char *str) |
252b5132 RH |
1527 | { |
1528 | struct mips_cl_insn insn; | |
f6688943 TS |
1529 | bfd_reloc_code_real_type unused_reloc[3] |
1530 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 RH |
1531 | |
1532 | imm_expr.X_op = O_absent; | |
5f74bc13 | 1533 | imm2_expr.X_op = O_absent; |
252b5132 | 1534 | offset_expr.X_op = O_absent; |
f6688943 TS |
1535 | imm_reloc[0] = BFD_RELOC_UNUSED; |
1536 | imm_reloc[1] = BFD_RELOC_UNUSED; | |
1537 | imm_reloc[2] = BFD_RELOC_UNUSED; | |
1538 | offset_reloc[0] = BFD_RELOC_UNUSED; | |
1539 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
1540 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
1541 | |
1542 | if (mips_opts.mips16) | |
1543 | mips16_ip (str, &insn); | |
1544 | else | |
1545 | { | |
1546 | mips_ip (str, &insn); | |
beae10d5 KH |
1547 | DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"), |
1548 | str, insn.insn_opcode)); | |
252b5132 RH |
1549 | } |
1550 | ||
1551 | if (insn_error) | |
1552 | { | |
1553 | as_bad ("%s `%s'", insn_error, str); | |
1554 | return; | |
1555 | } | |
1556 | ||
1557 | if (insn.insn_mo->pinfo == INSN_MACRO) | |
1558 | { | |
584892a6 | 1559 | macro_start (); |
252b5132 RH |
1560 | if (mips_opts.mips16) |
1561 | mips16_macro (&insn); | |
1562 | else | |
1563 | macro (&insn); | |
584892a6 | 1564 | macro_end (); |
252b5132 RH |
1565 | } |
1566 | else | |
1567 | { | |
1568 | if (imm_expr.X_op != O_absent) | |
4d7206a2 | 1569 | append_insn (&insn, &imm_expr, imm_reloc); |
252b5132 | 1570 | else if (offset_expr.X_op != O_absent) |
4d7206a2 | 1571 | append_insn (&insn, &offset_expr, offset_reloc); |
252b5132 | 1572 | else |
4d7206a2 | 1573 | append_insn (&insn, NULL, unused_reloc); |
252b5132 RH |
1574 | } |
1575 | } | |
1576 | ||
5919d012 RS |
1577 | /* Return true if the given relocation might need a matching %lo(). |
1578 | Note that R_MIPS_GOT16 relocations only need a matching %lo() when | |
1579 | applied to local symbols. */ | |
1580 | ||
1581 | static inline bfd_boolean | |
17a2f251 | 1582 | reloc_needs_lo_p (bfd_reloc_code_real_type reloc) |
5919d012 | 1583 | { |
3b91255e RS |
1584 | return (HAVE_IN_PLACE_ADDENDS |
1585 | && (reloc == BFD_RELOC_HI16_S | |
d6f16593 MR |
1586 | || reloc == BFD_RELOC_MIPS_GOT16 |
1587 | || reloc == BFD_RELOC_MIPS16_HI16_S)); | |
5919d012 RS |
1588 | } |
1589 | ||
1590 | /* Return true if the given fixup is followed by a matching R_MIPS_LO16 | |
1591 | relocation. */ | |
1592 | ||
1593 | static inline bfd_boolean | |
17a2f251 | 1594 | fixup_has_matching_lo_p (fixS *fixp) |
5919d012 RS |
1595 | { |
1596 | return (fixp->fx_next != NULL | |
d6f16593 MR |
1597 | && (fixp->fx_next->fx_r_type == BFD_RELOC_LO16 |
1598 | || fixp->fx_next->fx_r_type == BFD_RELOC_MIPS16_LO16) | |
5919d012 RS |
1599 | && fixp->fx_addsy == fixp->fx_next->fx_addsy |
1600 | && fixp->fx_offset == fixp->fx_next->fx_offset); | |
1601 | } | |
1602 | ||
252b5132 RH |
1603 | /* See whether instruction IP reads register REG. CLASS is the type |
1604 | of register. */ | |
1605 | ||
1606 | static int | |
17a2f251 TS |
1607 | insn_uses_reg (struct mips_cl_insn *ip, unsigned int reg, |
1608 | enum mips_regclass class) | |
252b5132 RH |
1609 | { |
1610 | if (class == MIPS16_REG) | |
1611 | { | |
1612 | assert (mips_opts.mips16); | |
1613 | reg = mips16_to_32_reg_map[reg]; | |
1614 | class = MIPS_GR_REG; | |
1615 | } | |
1616 | ||
85b51719 TS |
1617 | /* Don't report on general register ZERO, since it never changes. */ |
1618 | if (class == MIPS_GR_REG && reg == ZERO) | |
252b5132 RH |
1619 | return 0; |
1620 | ||
1621 | if (class == MIPS_FP_REG) | |
1622 | { | |
1623 | assert (! mips_opts.mips16); | |
1624 | /* If we are called with either $f0 or $f1, we must check $f0. | |
1625 | This is not optimal, because it will introduce an unnecessary | |
1626 | NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would | |
1627 | need to distinguish reading both $f0 and $f1 or just one of | |
1628 | them. Note that we don't have to check the other way, | |
1629 | because there is no instruction that sets both $f0 and $f1 | |
1630 | and requires a delay. */ | |
1631 | if ((ip->insn_mo->pinfo & INSN_READ_FPR_S) | |
bf12938e | 1632 | && ((EXTRACT_OPERAND (FS, *ip) & ~(unsigned) 1) |
252b5132 RH |
1633 | == (reg &~ (unsigned) 1))) |
1634 | return 1; | |
1635 | if ((ip->insn_mo->pinfo & INSN_READ_FPR_T) | |
bf12938e | 1636 | && ((EXTRACT_OPERAND (FT, *ip) & ~(unsigned) 1) |
252b5132 RH |
1637 | == (reg &~ (unsigned) 1))) |
1638 | return 1; | |
1639 | } | |
1640 | else if (! mips_opts.mips16) | |
1641 | { | |
1642 | if ((ip->insn_mo->pinfo & INSN_READ_GPR_S) | |
bf12938e | 1643 | && EXTRACT_OPERAND (RS, *ip) == reg) |
252b5132 RH |
1644 | return 1; |
1645 | if ((ip->insn_mo->pinfo & INSN_READ_GPR_T) | |
bf12938e | 1646 | && EXTRACT_OPERAND (RT, *ip) == reg) |
252b5132 RH |
1647 | return 1; |
1648 | } | |
1649 | else | |
1650 | { | |
1651 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_X) | |
bf12938e | 1652 | && mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, *ip)] == reg) |
252b5132 RH |
1653 | return 1; |
1654 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Y) | |
bf12938e | 1655 | && mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RY, *ip)] == reg) |
252b5132 RH |
1656 | return 1; |
1657 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Z) | |
bf12938e | 1658 | && (mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (MOVE32Z, *ip)] |
252b5132 RH |
1659 | == reg)) |
1660 | return 1; | |
1661 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_T) && reg == TREG) | |
1662 | return 1; | |
1663 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_SP) && reg == SP) | |
1664 | return 1; | |
1665 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_31) && reg == RA) | |
1666 | return 1; | |
1667 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_GPR_X) | |
bf12938e | 1668 | && MIPS16_EXTRACT_OPERAND (REGR32, *ip) == reg) |
252b5132 RH |
1669 | return 1; |
1670 | } | |
1671 | ||
1672 | return 0; | |
1673 | } | |
1674 | ||
1675 | /* This function returns true if modifying a register requires a | |
1676 | delay. */ | |
1677 | ||
1678 | static int | |
17a2f251 | 1679 | reg_needs_delay (unsigned int reg) |
252b5132 RH |
1680 | { |
1681 | unsigned long prev_pinfo; | |
1682 | ||
47e39b9d | 1683 | prev_pinfo = history[0].insn_mo->pinfo; |
252b5132 | 1684 | if (! mips_opts.noreorder |
81912461 ILT |
1685 | && (((prev_pinfo & INSN_LOAD_MEMORY_DELAY) |
1686 | && ! gpr_interlocks) | |
1687 | || ((prev_pinfo & INSN_LOAD_COPROC_DELAY) | |
1688 | && ! cop_interlocks))) | |
252b5132 | 1689 | { |
81912461 ILT |
1690 | /* A load from a coprocessor or from memory. All load delays |
1691 | delay the use of general register rt for one instruction. */ | |
bdaaa2e1 | 1692 | /* Itbl support may require additional care here. */ |
252b5132 | 1693 | know (prev_pinfo & INSN_WRITE_GPR_T); |
bf12938e | 1694 | if (reg == EXTRACT_OPERAND (RT, history[0])) |
252b5132 RH |
1695 | return 1; |
1696 | } | |
1697 | ||
1698 | return 0; | |
1699 | } | |
1700 | ||
1701 | /* Mark instruction labels in mips16 mode. This permits the linker to | |
1702 | handle them specially, such as generating jalx instructions when | |
1703 | needed. We also make them odd for the duration of the assembly, in | |
1704 | order to generate the right sort of code. We will make them even | |
1705 | in the adjust_symtab routine, while leaving them marked. This is | |
1706 | convenient for the debugger and the disassembler. The linker knows | |
1707 | to make them odd again. */ | |
1708 | ||
1709 | static void | |
17a2f251 | 1710 | mips16_mark_labels (void) |
252b5132 RH |
1711 | { |
1712 | if (mips_opts.mips16) | |
1713 | { | |
1714 | struct insn_label_list *l; | |
98aa84af | 1715 | valueT val; |
252b5132 RH |
1716 | |
1717 | for (l = insn_labels; l != NULL; l = l->next) | |
1718 | { | |
1719 | #ifdef OBJ_ELF | |
1720 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
1721 | S_SET_OTHER (l->label, STO_MIPS16); | |
1722 | #endif | |
98aa84af AM |
1723 | val = S_GET_VALUE (l->label); |
1724 | if ((val & 1) == 0) | |
1725 | S_SET_VALUE (l->label, val + 1); | |
252b5132 RH |
1726 | } |
1727 | } | |
1728 | } | |
1729 | ||
4d7206a2 RS |
1730 | /* End the current frag. Make it a variant frag and record the |
1731 | relaxation info. */ | |
1732 | ||
1733 | static void | |
1734 | relax_close_frag (void) | |
1735 | { | |
584892a6 | 1736 | mips_macro_warning.first_frag = frag_now; |
4d7206a2 | 1737 | frag_var (rs_machine_dependent, 0, 0, |
584892a6 | 1738 | RELAX_ENCODE (mips_relax.sizes[0], mips_relax.sizes[1]), |
4d7206a2 RS |
1739 | mips_relax.symbol, 0, (char *) mips_relax.first_fixup); |
1740 | ||
1741 | memset (&mips_relax.sizes, 0, sizeof (mips_relax.sizes)); | |
1742 | mips_relax.first_fixup = 0; | |
1743 | } | |
1744 | ||
1745 | /* Start a new relaxation sequence whose expansion depends on SYMBOL. | |
1746 | See the comment above RELAX_ENCODE for more details. */ | |
1747 | ||
1748 | static void | |
1749 | relax_start (symbolS *symbol) | |
1750 | { | |
1751 | assert (mips_relax.sequence == 0); | |
1752 | mips_relax.sequence = 1; | |
1753 | mips_relax.symbol = symbol; | |
1754 | } | |
1755 | ||
1756 | /* Start generating the second version of a relaxable sequence. | |
1757 | See the comment above RELAX_ENCODE for more details. */ | |
252b5132 RH |
1758 | |
1759 | static void | |
4d7206a2 RS |
1760 | relax_switch (void) |
1761 | { | |
1762 | assert (mips_relax.sequence == 1); | |
1763 | mips_relax.sequence = 2; | |
1764 | } | |
1765 | ||
1766 | /* End the current relaxable sequence. */ | |
1767 | ||
1768 | static void | |
1769 | relax_end (void) | |
1770 | { | |
1771 | assert (mips_relax.sequence == 2); | |
1772 | relax_close_frag (); | |
1773 | mips_relax.sequence = 0; | |
1774 | } | |
1775 | ||
1776 | /* Output an instruction. IP is the instruction information. | |
1777 | ADDRESS_EXPR is an operand of the instruction to be used with | |
1778 | RELOC_TYPE. */ | |
1779 | ||
1780 | static void | |
1781 | append_insn (struct mips_cl_insn *ip, expressionS *address_expr, | |
17a2f251 | 1782 | bfd_reloc_code_real_type *reloc_type) |
252b5132 RH |
1783 | { |
1784 | register unsigned long prev_pinfo, pinfo; | |
252b5132 | 1785 | int nops = 0; |
895921c9 MR |
1786 | relax_stateT prev_insn_frag_type = 0; |
1787 | bfd_boolean relaxed_branch = FALSE; | |
252b5132 RH |
1788 | |
1789 | /* Mark instruction labels in mips16 mode. */ | |
f9419b05 | 1790 | mips16_mark_labels (); |
252b5132 | 1791 | |
47e39b9d | 1792 | prev_pinfo = history[0].insn_mo->pinfo; |
252b5132 RH |
1793 | pinfo = ip->insn_mo->pinfo; |
1794 | ||
4d7206a2 RS |
1795 | if (mips_relax.sequence != 2 |
1796 | && (!mips_opts.noreorder || prev_nop_frag != NULL)) | |
252b5132 RH |
1797 | { |
1798 | int prev_prev_nop; | |
1799 | ||
1800 | /* If the previous insn required any delay slots, see if we need | |
1801 | to insert a NOP or two. There are eight kinds of possible | |
1802 | hazards, of which an instruction can have at most one type. | |
1803 | (1) a load from memory delay | |
1804 | (2) a load from a coprocessor delay | |
1805 | (3) an unconditional branch delay | |
1806 | (4) a conditional branch delay | |
1807 | (5) a move to coprocessor register delay | |
1808 | (6) a load coprocessor register from memory delay | |
1809 | (7) a coprocessor condition code delay | |
1810 | (8) a HI/LO special register delay | |
1811 | ||
1812 | There are a lot of optimizations we could do that we don't. | |
1813 | In particular, we do not, in general, reorder instructions. | |
1814 | If you use gcc with optimization, it will reorder | |
1815 | instructions and generally do much more optimization then we | |
1816 | do here; repeating all that work in the assembler would only | |
1817 | benefit hand written assembly code, and does not seem worth | |
1818 | it. */ | |
1819 | ||
252b5132 RH |
1820 | /* The previous insn might require a delay slot, depending upon |
1821 | the contents of the current insn. */ | |
1822 | if (! mips_opts.mips16 | |
81912461 ILT |
1823 | && (((prev_pinfo & INSN_LOAD_MEMORY_DELAY) |
1824 | && ! gpr_interlocks) | |
1825 | || ((prev_pinfo & INSN_LOAD_COPROC_DELAY) | |
1826 | && ! cop_interlocks))) | |
252b5132 RH |
1827 | { |
1828 | /* A load from a coprocessor or from memory. All load | |
1829 | delays delay the use of general register rt for one | |
81912461 | 1830 | instruction. */ |
beae10d5 | 1831 | /* Itbl support may require additional care here. */ |
252b5132 RH |
1832 | know (prev_pinfo & INSN_WRITE_GPR_T); |
1833 | if (mips_optimize == 0 | |
bf12938e | 1834 | || insn_uses_reg (ip, EXTRACT_OPERAND (RT, history[0]), |
252b5132 RH |
1835 | MIPS_GR_REG)) |
1836 | ++nops; | |
1837 | } | |
1838 | else if (! mips_opts.mips16 | |
252b5132 | 1839 | && (((prev_pinfo & INSN_COPROC_MOVE_DELAY) |
beae10d5 | 1840 | && ! cop_interlocks) |
81912461 ILT |
1841 | || ((prev_pinfo & INSN_COPROC_MEMORY_DELAY) |
1842 | && ! cop_mem_interlocks))) | |
252b5132 RH |
1843 | { |
1844 | /* A generic coprocessor delay. The previous instruction | |
1845 | modified a coprocessor general or control register. If | |
1846 | it modified a control register, we need to avoid any | |
1847 | coprocessor instruction (this is probably not always | |
1848 | required, but it sometimes is). If it modified a general | |
1849 | register, we avoid using that register. | |
1850 | ||
252b5132 RH |
1851 | This case is not handled very well. There is no special |
1852 | knowledge of CP0 handling, and the coprocessors other | |
1853 | than the floating point unit are not distinguished at | |
1854 | all. */ | |
1855 | /* Itbl support may require additional care here. FIXME! | |
bdaaa2e1 | 1856 | Need to modify this to include knowledge about |
252b5132 RH |
1857 | user specified delays! */ |
1858 | if (prev_pinfo & INSN_WRITE_FPR_T) | |
1859 | { | |
1860 | if (mips_optimize == 0 | |
bf12938e | 1861 | || insn_uses_reg (ip, EXTRACT_OPERAND (FT, history[0]), |
252b5132 RH |
1862 | MIPS_FP_REG)) |
1863 | ++nops; | |
1864 | } | |
1865 | else if (prev_pinfo & INSN_WRITE_FPR_S) | |
1866 | { | |
1867 | if (mips_optimize == 0 | |
bf12938e | 1868 | || insn_uses_reg (ip, EXTRACT_OPERAND (FS, history[0]), |
252b5132 RH |
1869 | MIPS_FP_REG)) |
1870 | ++nops; | |
1871 | } | |
1872 | else | |
1873 | { | |
1874 | /* We don't know exactly what the previous instruction | |
1875 | does. If the current instruction uses a coprocessor | |
1876 | register, we must insert a NOP. If previous | |
1877 | instruction may set the condition codes, and the | |
1878 | current instruction uses them, we must insert two | |
1879 | NOPS. */ | |
bdaaa2e1 | 1880 | /* Itbl support may require additional care here. */ |
252b5132 RH |
1881 | if (mips_optimize == 0 |
1882 | || ((prev_pinfo & INSN_WRITE_COND_CODE) | |
1883 | && (pinfo & INSN_READ_COND_CODE))) | |
1884 | nops += 2; | |
1885 | else if (pinfo & INSN_COP) | |
1886 | ++nops; | |
1887 | } | |
1888 | } | |
1889 | else if (! mips_opts.mips16 | |
252b5132 RH |
1890 | && (prev_pinfo & INSN_WRITE_COND_CODE) |
1891 | && ! cop_interlocks) | |
1892 | { | |
1893 | /* The previous instruction sets the coprocessor condition | |
1894 | codes, but does not require a general coprocessor delay | |
1895 | (this means it is a floating point comparison | |
1896 | instruction). If this instruction uses the condition | |
1897 | codes, we need to insert a single NOP. */ | |
beae10d5 | 1898 | /* Itbl support may require additional care here. */ |
252b5132 RH |
1899 | if (mips_optimize == 0 |
1900 | || (pinfo & INSN_READ_COND_CODE)) | |
1901 | ++nops; | |
1902 | } | |
6b76fefe CM |
1903 | |
1904 | /* If we're fixing up mfhi/mflo for the r7000 and the | |
1905 | previous insn was an mfhi/mflo and the current insn | |
1906 | reads the register that the mfhi/mflo wrote to, then | |
1907 | insert two nops. */ | |
1908 | ||
1909 | else if (mips_7000_hilo_fix | |
1910 | && MF_HILO_INSN (prev_pinfo) | |
bf12938e | 1911 | && insn_uses_reg (ip, EXTRACT_OPERAND (RD, history[0]), |
beae10d5 | 1912 | MIPS_GR_REG)) |
6b76fefe CM |
1913 | { |
1914 | nops += 2; | |
1915 | } | |
1916 | ||
1917 | /* If we're fixing up mfhi/mflo for the r7000 and the | |
1918 | 2nd previous insn was an mfhi/mflo and the current insn | |
1919 | reads the register that the mfhi/mflo wrote to, then | |
1920 | insert one nop. */ | |
1921 | ||
1922 | else if (mips_7000_hilo_fix | |
47e39b9d | 1923 | && MF_HILO_INSN (history[1].insn_opcode) |
bf12938e RS |
1924 | && insn_uses_reg (ip, EXTRACT_OPERAND (RD, history[1]), |
1925 | MIPS_GR_REG)) | |
bdaaa2e1 | 1926 | |
6b76fefe | 1927 | { |
f9419b05 | 1928 | ++nops; |
6b76fefe | 1929 | } |
bdaaa2e1 | 1930 | |
252b5132 RH |
1931 | else if (prev_pinfo & INSN_READ_LO) |
1932 | { | |
1933 | /* The previous instruction reads the LO register; if the | |
1934 | current instruction writes to the LO register, we must | |
bdaaa2e1 | 1935 | insert two NOPS. Some newer processors have interlocks. |
67c1ffbe KH |
1936 | Also the tx39's multiply instructions can be executed |
1937 | immediately after a read from HI/LO (without the delay), | |
bdaaa2e1 KH |
1938 | though the tx39's divide insns still do require the |
1939 | delay. */ | |
252b5132 | 1940 | if (! (hilo_interlocks |
048cdf86 | 1941 | || (mips_opts.arch == CPU_R3900 && (pinfo & INSN_MULT))) |
252b5132 RH |
1942 | && (mips_optimize == 0 |
1943 | || (pinfo & INSN_WRITE_LO))) | |
1944 | nops += 2; | |
1945 | /* Most mips16 branch insns don't have a delay slot. | |
1946 | If a read from LO is immediately followed by a branch | |
1947 | to a write to LO we have a read followed by a write | |
1948 | less than 2 insns away. We assume the target of | |
1949 | a branch might be a write to LO, and insert a nop | |
bdaaa2e1 | 1950 | between a read and an immediately following branch. */ |
252b5132 RH |
1951 | else if (mips_opts.mips16 |
1952 | && (mips_optimize == 0 | |
1953 | || (pinfo & MIPS16_INSN_BRANCH))) | |
f9419b05 | 1954 | ++nops; |
252b5132 | 1955 | } |
47e39b9d | 1956 | else if (history[0].insn_mo->pinfo & INSN_READ_HI) |
252b5132 RH |
1957 | { |
1958 | /* The previous instruction reads the HI register; if the | |
1959 | current instruction writes to the HI register, we must | |
1960 | insert a NOP. Some newer processors have interlocks. | |
bdaaa2e1 | 1961 | Also the note tx39's multiply above. */ |
252b5132 | 1962 | if (! (hilo_interlocks |
048cdf86 | 1963 | || (mips_opts.arch == CPU_R3900 && (pinfo & INSN_MULT))) |
252b5132 RH |
1964 | && (mips_optimize == 0 |
1965 | || (pinfo & INSN_WRITE_HI))) | |
1966 | nops += 2; | |
1967 | /* Most mips16 branch insns don't have a delay slot. | |
1968 | If a read from HI is immediately followed by a branch | |
1969 | to a write to HI we have a read followed by a write | |
1970 | less than 2 insns away. We assume the target of | |
1971 | a branch might be a write to HI, and insert a nop | |
bdaaa2e1 | 1972 | between a read and an immediately following branch. */ |
252b5132 RH |
1973 | else if (mips_opts.mips16 |
1974 | && (mips_optimize == 0 | |
1975 | || (pinfo & MIPS16_INSN_BRANCH))) | |
f9419b05 | 1976 | ++nops; |
252b5132 RH |
1977 | } |
1978 | ||
1979 | /* If the previous instruction was in a noreorder section, then | |
1980 | we don't want to insert the nop after all. */ | |
bdaaa2e1 | 1981 | /* Itbl support may require additional care here. */ |
47e39b9d | 1982 | if (history[0].noreorder_p) |
252b5132 RH |
1983 | nops = 0; |
1984 | ||
1985 | /* There are two cases which require two intervening | |
1986 | instructions: 1) setting the condition codes using a move to | |
1987 | coprocessor instruction which requires a general coprocessor | |
1988 | delay and then reading the condition codes 2) reading the HI | |
1989 | or LO register and then writing to it (except on processors | |
1990 | which have interlocks). If we are not already emitting a NOP | |
1991 | instruction, we must check for these cases compared to the | |
1992 | instruction previous to the previous instruction. */ | |
1993 | if ((! mips_opts.mips16 | |
47e39b9d RS |
1994 | && (history[1].insn_mo->pinfo & INSN_COPROC_MOVE_DELAY) |
1995 | && (history[1].insn_mo->pinfo & INSN_WRITE_COND_CODE) | |
252b5132 RH |
1996 | && (pinfo & INSN_READ_COND_CODE) |
1997 | && ! cop_interlocks) | |
47e39b9d | 1998 | || ((history[1].insn_mo->pinfo & INSN_READ_LO) |
252b5132 RH |
1999 | && (pinfo & INSN_WRITE_LO) |
2000 | && ! (hilo_interlocks | |
048cdf86 | 2001 | || (mips_opts.arch == CPU_R3900 && (pinfo & INSN_MULT)))) |
47e39b9d | 2002 | || ((history[1].insn_mo->pinfo & INSN_READ_HI) |
252b5132 RH |
2003 | && (pinfo & INSN_WRITE_HI) |
2004 | && ! (hilo_interlocks | |
048cdf86 | 2005 | || (mips_opts.arch == CPU_R3900 && (pinfo & INSN_MULT))))) |
252b5132 RH |
2006 | prev_prev_nop = 1; |
2007 | else | |
2008 | prev_prev_nop = 0; | |
2009 | ||
47e39b9d | 2010 | if (history[1].noreorder_p) |
252b5132 RH |
2011 | prev_prev_nop = 0; |
2012 | ||
2013 | if (prev_prev_nop && nops == 0) | |
2014 | ++nops; | |
2015 | ||
47e39b9d | 2016 | if (mips_fix_vr4120 && history[0].insn_mo->name) |
60b63b72 RS |
2017 | { |
2018 | /* We're out of bits in pinfo, so we must resort to string | |
2019 | ops here. Shortcuts are selected based on opcodes being | |
d766e8ec | 2020 | limited to the VR4120 instruction set. */ |
60b63b72 | 2021 | int min_nops = 0; |
47e39b9d | 2022 | const char *pn = history[0].insn_mo->name; |
60b63b72 | 2023 | const char *tn = ip->insn_mo->name; |
532c738a RS |
2024 | if (strncmp (pn, "macc", 4) == 0 |
2025 | || strncmp (pn, "dmacc", 5) == 0) | |
60b63b72 RS |
2026 | { |
2027 | /* Errata 21 - [D]DIV[U] after [D]MACC */ | |
2028 | if (strstr (tn, "div")) | |
532c738a | 2029 | min_nops = 1; |
60b63b72 | 2030 | |
532c738a RS |
2031 | /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU |
2032 | instruction is executed immediately after a MACC or | |
2033 | DMACC instruction, the result of [either instruction] | |
2034 | is incorrect." */ | |
2035 | if (strncmp (tn, "mult", 4) == 0 | |
2036 | || strncmp (tn, "dmult", 5) == 0) | |
2037 | min_nops = 1; | |
2038 | ||
2039 | /* Errata 23 - Continuous DMULT[U]/DMACC instructions. | |
2040 | Applies on top of VR4181A MD(1) errata. */ | |
2041 | if (pn[0] == 'd' && strncmp (tn, "dmacc", 5) == 0) | |
2042 | min_nops = 1; | |
60b63b72 RS |
2043 | |
2044 | /* Errata 24 - MT{LO,HI} after [D]MACC */ | |
2045 | if (strcmp (tn, "mtlo") == 0 | |
2046 | || strcmp (tn, "mthi") == 0) | |
532c738a | 2047 | min_nops = 1; |
60b63b72 | 2048 | } |
532c738a RS |
2049 | else if (strncmp (pn, "dmult", 5) == 0 |
2050 | && (strncmp (tn, "dmult", 5) == 0 | |
2051 | || strncmp (tn, "dmacc", 5) == 0)) | |
60b63b72 RS |
2052 | { |
2053 | /* Here is the rest of errata 23. */ | |
2054 | min_nops = 1; | |
2055 | } | |
532c738a RS |
2056 | else if ((strncmp (pn, "dmult", 5) == 0 || strstr (pn, "div")) |
2057 | && (strncmp (tn, "macc", 4) == 0 | |
2058 | || strncmp (tn, "dmacc", 5) == 0)) | |
2059 | { | |
2060 | /* VR4181A errata MD(4): "If a MACC or DMACC instruction is | |
2061 | executed immediately after a DMULT, DMULTU, DIV, DIVU, | |
2062 | DDIV or DDIVU instruction, the result of the MACC or | |
2063 | DMACC instruction is incorrect.". This partly overlaps | |
2064 | the workaround for errata 23. */ | |
2065 | min_nops = 1; | |
2066 | } | |
60b63b72 RS |
2067 | if (nops < min_nops) |
2068 | nops = min_nops; | |
2069 | } | |
2070 | ||
252b5132 RH |
2071 | /* If we are being given a nop instruction, don't bother with |
2072 | one of the nops we would otherwise output. This will only | |
2073 | happen when a nop instruction is used with mips_optimize set | |
2074 | to 0. */ | |
2075 | if (nops > 0 | |
2076 | && ! mips_opts.noreorder | |
156c2f8b | 2077 | && ip->insn_opcode == (unsigned) (mips_opts.mips16 ? 0x6500 : 0)) |
252b5132 RH |
2078 | --nops; |
2079 | ||
2080 | /* Now emit the right number of NOP instructions. */ | |
2081 | if (nops > 0 && ! mips_opts.noreorder) | |
2082 | { | |
2083 | fragS *old_frag; | |
2084 | unsigned long old_frag_offset; | |
2085 | int i; | |
2086 | struct insn_label_list *l; | |
2087 | ||
2088 | old_frag = frag_now; | |
2089 | old_frag_offset = frag_now_fix (); | |
2090 | ||
2091 | for (i = 0; i < nops; i++) | |
2092 | emit_nop (); | |
2093 | ||
2094 | if (listing) | |
2095 | { | |
2096 | listing_prev_line (); | |
2097 | /* We may be at the start of a variant frag. In case we | |
2098 | are, make sure there is enough space for the frag | |
2099 | after the frags created by listing_prev_line. The | |
2100 | argument to frag_grow here must be at least as large | |
2101 | as the argument to all other calls to frag_grow in | |
2102 | this file. We don't have to worry about being in the | |
2103 | middle of a variant frag, because the variants insert | |
2104 | all needed nop instructions themselves. */ | |
2105 | frag_grow (40); | |
2106 | } | |
2107 | ||
2108 | for (l = insn_labels; l != NULL; l = l->next) | |
2109 | { | |
98aa84af AM |
2110 | valueT val; |
2111 | ||
252b5132 | 2112 | assert (S_GET_SEGMENT (l->label) == now_seg); |
49309057 | 2113 | symbol_set_frag (l->label, frag_now); |
98aa84af | 2114 | val = (valueT) frag_now_fix (); |
252b5132 RH |
2115 | /* mips16 text labels are stored as odd. */ |
2116 | if (mips_opts.mips16) | |
f9419b05 | 2117 | ++val; |
98aa84af | 2118 | S_SET_VALUE (l->label, val); |
252b5132 RH |
2119 | } |
2120 | ||
2121 | #ifndef NO_ECOFF_DEBUGGING | |
2122 | if (ECOFF_DEBUGGING) | |
2123 | ecoff_fix_loc (old_frag, old_frag_offset); | |
2124 | #endif | |
2125 | } | |
2126 | else if (prev_nop_frag != NULL) | |
2127 | { | |
2128 | /* We have a frag holding nops we may be able to remove. If | |
2129 | we don't need any nops, we can decrease the size of | |
2130 | prev_nop_frag by the size of one instruction. If we do | |
bdaaa2e1 | 2131 | need some nops, we count them in prev_nops_required. */ |
252b5132 RH |
2132 | if (prev_nop_frag_since == 0) |
2133 | { | |
2134 | if (nops == 0) | |
2135 | { | |
2136 | prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4; | |
2137 | --prev_nop_frag_holds; | |
2138 | } | |
2139 | else | |
2140 | prev_nop_frag_required += nops; | |
2141 | } | |
2142 | else | |
2143 | { | |
2144 | if (prev_prev_nop == 0) | |
2145 | { | |
2146 | prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4; | |
2147 | --prev_nop_frag_holds; | |
2148 | } | |
2149 | else | |
2150 | ++prev_nop_frag_required; | |
2151 | } | |
2152 | ||
2153 | if (prev_nop_frag_holds <= prev_nop_frag_required) | |
2154 | prev_nop_frag = NULL; | |
2155 | ||
2156 | ++prev_nop_frag_since; | |
2157 | ||
2158 | /* Sanity check: by the time we reach the second instruction | |
2159 | after prev_nop_frag, we should have used up all the nops | |
2160 | one way or another. */ | |
2161 | assert (prev_nop_frag_since <= 1 || prev_nop_frag == NULL); | |
2162 | } | |
2163 | } | |
2164 | ||
58e2ea4d MR |
2165 | #ifdef OBJ_ELF |
2166 | /* The value passed to dwarf2_emit_insn is the distance between | |
2167 | the beginning of the current instruction and the address that | |
2168 | should be recorded in the debug tables. For MIPS16 debug info | |
2169 | we want to use ISA-encoded addresses, so we pass -1 for an | |
2170 | address higher by one than the current. */ | |
2171 | dwarf2_emit_insn (mips_opts.mips16 ? -1 : 0); | |
2172 | #endif | |
2173 | ||
895921c9 | 2174 | /* Record the frag type before frag_var. */ |
47e39b9d RS |
2175 | if (history[0].frag) |
2176 | prev_insn_frag_type = history[0].frag->fr_type; | |
895921c9 | 2177 | |
4d7206a2 | 2178 | if (address_expr |
0b25d3e6 | 2179 | && *reloc_type == BFD_RELOC_16_PCREL_S2 |
4a6a3df4 AO |
2180 | && (pinfo & INSN_UNCOND_BRANCH_DELAY || pinfo & INSN_COND_BRANCH_DELAY |
2181 | || pinfo & INSN_COND_BRANCH_LIKELY) | |
2182 | && mips_relax_branch | |
2183 | /* Don't try branch relaxation within .set nomacro, or within | |
2184 | .set noat if we use $at for PIC computations. If it turns | |
2185 | out that the branch was out-of-range, we'll get an error. */ | |
2186 | && !mips_opts.warn_about_macros | |
2187 | && !(mips_opts.noat && mips_pic != NO_PIC) | |
2188 | && !mips_opts.mips16) | |
2189 | { | |
895921c9 | 2190 | relaxed_branch = TRUE; |
1e915849 RS |
2191 | add_relaxed_insn (ip, (relaxed_branch_length |
2192 | (NULL, NULL, | |
2193 | (pinfo & INSN_UNCOND_BRANCH_DELAY) ? -1 | |
2194 | : (pinfo & INSN_COND_BRANCH_LIKELY) ? 1 | |
2195 | : 0)), 4, | |
2196 | RELAX_BRANCH_ENCODE | |
2197 | (pinfo & INSN_UNCOND_BRANCH_DELAY, | |
2198 | pinfo & INSN_COND_BRANCH_LIKELY, | |
2199 | pinfo & INSN_WRITE_GPR_31, | |
2200 | 0), | |
2201 | address_expr->X_add_symbol, | |
2202 | address_expr->X_add_number); | |
4a6a3df4 AO |
2203 | *reloc_type = BFD_RELOC_UNUSED; |
2204 | } | |
2205 | else if (*reloc_type > BFD_RELOC_UNUSED) | |
252b5132 RH |
2206 | { |
2207 | /* We need to set up a variant frag. */ | |
2208 | assert (mips_opts.mips16 && address_expr != NULL); | |
1e915849 RS |
2209 | add_relaxed_insn (ip, 4, 0, |
2210 | RELAX_MIPS16_ENCODE | |
2211 | (*reloc_type - BFD_RELOC_UNUSED, | |
2212 | mips16_small, mips16_ext, | |
2213 | prev_pinfo & INSN_UNCOND_BRANCH_DELAY, | |
2214 | history[0].mips16_absolute_jump_p), | |
2215 | make_expr_symbol (address_expr), 0); | |
252b5132 | 2216 | } |
252b5132 RH |
2217 | else if (mips_opts.mips16 |
2218 | && ! ip->use_extend | |
f6688943 | 2219 | && *reloc_type != BFD_RELOC_MIPS16_JMP) |
252b5132 RH |
2220 | { |
2221 | /* Make sure there is enough room to swap this instruction with | |
2222 | a following jump instruction. */ | |
2223 | frag_grow (6); | |
1e915849 | 2224 | add_fixed_insn (ip); |
252b5132 RH |
2225 | } |
2226 | else | |
2227 | { | |
2228 | if (mips_opts.mips16 | |
2229 | && mips_opts.noreorder | |
2230 | && (prev_pinfo & INSN_UNCOND_BRANCH_DELAY) != 0) | |
2231 | as_warn (_("extended instruction in delay slot")); | |
2232 | ||
4d7206a2 RS |
2233 | if (mips_relax.sequence) |
2234 | { | |
2235 | /* If we've reached the end of this frag, turn it into a variant | |
2236 | frag and record the information for the instructions we've | |
2237 | written so far. */ | |
2238 | if (frag_room () < 4) | |
2239 | relax_close_frag (); | |
2240 | mips_relax.sizes[mips_relax.sequence - 1] += 4; | |
2241 | } | |
2242 | ||
584892a6 RS |
2243 | if (mips_relax.sequence != 2) |
2244 | mips_macro_warning.sizes[0] += 4; | |
2245 | if (mips_relax.sequence != 1) | |
2246 | mips_macro_warning.sizes[1] += 4; | |
2247 | ||
1e915849 RS |
2248 | if (mips_opts.mips16) |
2249 | { | |
2250 | ip->fixed_p = 1; | |
2251 | ip->mips16_absolute_jump_p = (*reloc_type == BFD_RELOC_MIPS16_JMP); | |
2252 | } | |
2253 | add_fixed_insn (ip); | |
252b5132 RH |
2254 | } |
2255 | ||
01a3f561 | 2256 | if (address_expr != NULL && *reloc_type <= BFD_RELOC_UNUSED) |
252b5132 RH |
2257 | { |
2258 | if (address_expr->X_op == O_constant) | |
2259 | { | |
f17c130b | 2260 | unsigned int tmp; |
f6688943 TS |
2261 | |
2262 | switch (*reloc_type) | |
252b5132 RH |
2263 | { |
2264 | case BFD_RELOC_32: | |
2265 | ip->insn_opcode |= address_expr->X_add_number; | |
2266 | break; | |
2267 | ||
f6688943 | 2268 | case BFD_RELOC_MIPS_HIGHEST: |
f17c130b AM |
2269 | tmp = (address_expr->X_add_number + 0x800080008000ull) >> 48; |
2270 | ip->insn_opcode |= tmp & 0xffff; | |
f6688943 TS |
2271 | break; |
2272 | ||
2273 | case BFD_RELOC_MIPS_HIGHER: | |
f17c130b AM |
2274 | tmp = (address_expr->X_add_number + 0x80008000ull) >> 32; |
2275 | ip->insn_opcode |= tmp & 0xffff; | |
f6688943 TS |
2276 | break; |
2277 | ||
2278 | case BFD_RELOC_HI16_S: | |
f17c130b AM |
2279 | tmp = (address_expr->X_add_number + 0x8000) >> 16; |
2280 | ip->insn_opcode |= tmp & 0xffff; | |
f6688943 TS |
2281 | break; |
2282 | ||
2283 | case BFD_RELOC_HI16: | |
2284 | ip->insn_opcode |= (address_expr->X_add_number >> 16) & 0xffff; | |
2285 | break; | |
2286 | ||
01a3f561 | 2287 | case BFD_RELOC_UNUSED: |
252b5132 | 2288 | case BFD_RELOC_LO16: |
ed6fb7bd | 2289 | case BFD_RELOC_MIPS_GOT_DISP: |
252b5132 RH |
2290 | ip->insn_opcode |= address_expr->X_add_number & 0xffff; |
2291 | break; | |
2292 | ||
2293 | case BFD_RELOC_MIPS_JMP: | |
2294 | if ((address_expr->X_add_number & 3) != 0) | |
2295 | as_bad (_("jump to misaligned address (0x%lx)"), | |
2296 | (unsigned long) address_expr->X_add_number); | |
f3c0ec86 | 2297 | if (address_expr->X_add_number & ~0xfffffff) |
7496292d TS |
2298 | as_bad (_("jump address range overflow (0x%lx)"), |
2299 | (unsigned long) address_expr->X_add_number); | |
252b5132 RH |
2300 | ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0x3ffffff; |
2301 | break; | |
2302 | ||
2303 | case BFD_RELOC_MIPS16_JMP: | |
2304 | if ((address_expr->X_add_number & 3) != 0) | |
2305 | as_bad (_("jump to misaligned address (0x%lx)"), | |
2306 | (unsigned long) address_expr->X_add_number); | |
f3c0ec86 | 2307 | if (address_expr->X_add_number & ~0xfffffff) |
7496292d TS |
2308 | as_bad (_("jump address range overflow (0x%lx)"), |
2309 | (unsigned long) address_expr->X_add_number); | |
252b5132 RH |
2310 | ip->insn_opcode |= |
2311 | (((address_expr->X_add_number & 0x7c0000) << 3) | |
2312 | | ((address_expr->X_add_number & 0xf800000) >> 7) | |
2313 | | ((address_expr->X_add_number & 0x3fffc) >> 2)); | |
2314 | break; | |
2315 | ||
252b5132 RH |
2316 | case BFD_RELOC_16_PCREL_S2: |
2317 | goto need_reloc; | |
2318 | ||
2319 | default: | |
2320 | internalError (); | |
2321 | } | |
2322 | } | |
01a3f561 | 2323 | else if (*reloc_type < BFD_RELOC_UNUSED) |
252b5132 | 2324 | need_reloc: |
4d7206a2 RS |
2325 | { |
2326 | reloc_howto_type *howto; | |
2327 | int i; | |
34ce925e | 2328 | |
4d7206a2 RS |
2329 | /* In a compound relocation, it is the final (outermost) |
2330 | operator that determines the relocated field. */ | |
2331 | for (i = 1; i < 3; i++) | |
2332 | if (reloc_type[i] == BFD_RELOC_UNUSED) | |
2333 | break; | |
34ce925e | 2334 | |
4d7206a2 | 2335 | howto = bfd_reloc_type_lookup (stdoutput, reloc_type[i - 1]); |
1e915849 RS |
2336 | ip->fixp[0] = fix_new_exp (ip->frag, ip->where, |
2337 | bfd_get_reloc_size (howto), | |
2338 | address_expr, | |
2339 | reloc_type[0] == BFD_RELOC_16_PCREL_S2, | |
2340 | reloc_type[0]); | |
4d7206a2 RS |
2341 | |
2342 | /* These relocations can have an addend that won't fit in | |
2343 | 4 octets for 64bit assembly. */ | |
2344 | if (HAVE_64BIT_GPRS | |
2345 | && ! howto->partial_inplace | |
2346 | && (reloc_type[0] == BFD_RELOC_16 | |
2347 | || reloc_type[0] == BFD_RELOC_32 | |
2348 | || reloc_type[0] == BFD_RELOC_MIPS_JMP | |
2349 | || reloc_type[0] == BFD_RELOC_HI16_S | |
2350 | || reloc_type[0] == BFD_RELOC_LO16 | |
2351 | || reloc_type[0] == BFD_RELOC_GPREL16 | |
2352 | || reloc_type[0] == BFD_RELOC_MIPS_LITERAL | |
2353 | || reloc_type[0] == BFD_RELOC_GPREL32 | |
2354 | || reloc_type[0] == BFD_RELOC_64 | |
2355 | || reloc_type[0] == BFD_RELOC_CTOR | |
2356 | || reloc_type[0] == BFD_RELOC_MIPS_SUB | |
2357 | || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST | |
2358 | || reloc_type[0] == BFD_RELOC_MIPS_HIGHER | |
2359 | || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP | |
2360 | || reloc_type[0] == BFD_RELOC_MIPS_REL16 | |
d6f16593 MR |
2361 | || reloc_type[0] == BFD_RELOC_MIPS_RELGOT |
2362 | || reloc_type[0] == BFD_RELOC_MIPS16_GPREL | |
2363 | || reloc_type[0] == BFD_RELOC_MIPS16_HI16_S | |
2364 | || reloc_type[0] == BFD_RELOC_MIPS16_LO16)) | |
1e915849 | 2365 | ip->fixp[0]->fx_no_overflow = 1; |
4d7206a2 RS |
2366 | |
2367 | if (mips_relax.sequence) | |
2368 | { | |
2369 | if (mips_relax.first_fixup == 0) | |
1e915849 | 2370 | mips_relax.first_fixup = ip->fixp[0]; |
4d7206a2 RS |
2371 | } |
2372 | else if (reloc_needs_lo_p (*reloc_type)) | |
2373 | { | |
2374 | struct mips_hi_fixup *hi_fixup; | |
252b5132 | 2375 | |
4d7206a2 RS |
2376 | /* Reuse the last entry if it already has a matching %lo. */ |
2377 | hi_fixup = mips_hi_fixup_list; | |
2378 | if (hi_fixup == 0 | |
2379 | || !fixup_has_matching_lo_p (hi_fixup->fixp)) | |
2380 | { | |
2381 | hi_fixup = ((struct mips_hi_fixup *) | |
2382 | xmalloc (sizeof (struct mips_hi_fixup))); | |
2383 | hi_fixup->next = mips_hi_fixup_list; | |
2384 | mips_hi_fixup_list = hi_fixup; | |
252b5132 | 2385 | } |
1e915849 | 2386 | hi_fixup->fixp = ip->fixp[0]; |
4d7206a2 RS |
2387 | hi_fixup->seg = now_seg; |
2388 | } | |
f6688943 | 2389 | |
4d7206a2 RS |
2390 | /* Add fixups for the second and third relocations, if given. |
2391 | Note that the ABI allows the second relocation to be | |
2392 | against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the | |
2393 | moment we only use RSS_UNDEF, but we could add support | |
2394 | for the others if it ever becomes necessary. */ | |
2395 | for (i = 1; i < 3; i++) | |
2396 | if (reloc_type[i] != BFD_RELOC_UNUSED) | |
2397 | { | |
1e915849 RS |
2398 | ip->fixp[i] = fix_new (ip->frag, ip->where, |
2399 | ip->fixp[0]->fx_size, NULL, 0, | |
2400 | FALSE, reloc_type[i]); | |
b1dca8ee RS |
2401 | |
2402 | /* Use fx_tcbit to mark compound relocs. */ | |
1e915849 RS |
2403 | ip->fixp[0]->fx_tcbit = 1; |
2404 | ip->fixp[i]->fx_tcbit = 1; | |
4d7206a2 | 2405 | } |
252b5132 RH |
2406 | } |
2407 | } | |
1e915849 | 2408 | install_insn (ip); |
252b5132 RH |
2409 | |
2410 | /* Update the register mask information. */ | |
2411 | if (! mips_opts.mips16) | |
2412 | { | |
2413 | if (pinfo & INSN_WRITE_GPR_D) | |
bf12938e | 2414 | mips_gprmask |= 1 << EXTRACT_OPERAND (RD, *ip); |
252b5132 | 2415 | if ((pinfo & (INSN_WRITE_GPR_T | INSN_READ_GPR_T)) != 0) |
bf12938e | 2416 | mips_gprmask |= 1 << EXTRACT_OPERAND (RT, *ip); |
252b5132 | 2417 | if (pinfo & INSN_READ_GPR_S) |
bf12938e | 2418 | mips_gprmask |= 1 << EXTRACT_OPERAND (RS, *ip); |
252b5132 | 2419 | if (pinfo & INSN_WRITE_GPR_31) |
f9419b05 | 2420 | mips_gprmask |= 1 << RA; |
252b5132 | 2421 | if (pinfo & INSN_WRITE_FPR_D) |
bf12938e | 2422 | mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FD, *ip); |
252b5132 | 2423 | if ((pinfo & (INSN_WRITE_FPR_S | INSN_READ_FPR_S)) != 0) |
bf12938e | 2424 | mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FS, *ip); |
252b5132 | 2425 | if ((pinfo & (INSN_WRITE_FPR_T | INSN_READ_FPR_T)) != 0) |
bf12938e | 2426 | mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FT, *ip); |
252b5132 | 2427 | if ((pinfo & INSN_READ_FPR_R) != 0) |
bf12938e | 2428 | mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FR, *ip); |
252b5132 RH |
2429 | if (pinfo & INSN_COP) |
2430 | { | |
bdaaa2e1 KH |
2431 | /* We don't keep enough information to sort these cases out. |
2432 | The itbl support does keep this information however, although | |
2433 | we currently don't support itbl fprmats as part of the cop | |
2434 | instruction. May want to add this support in the future. */ | |
252b5132 RH |
2435 | } |
2436 | /* Never set the bit for $0, which is always zero. */ | |
beae10d5 | 2437 | mips_gprmask &= ~1 << 0; |
252b5132 RH |
2438 | } |
2439 | else | |
2440 | { | |
2441 | if (pinfo & (MIPS16_INSN_WRITE_X | MIPS16_INSN_READ_X)) | |
bf12938e | 2442 | mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (RX, *ip); |
252b5132 | 2443 | if (pinfo & (MIPS16_INSN_WRITE_Y | MIPS16_INSN_READ_Y)) |
bf12938e | 2444 | mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (RY, *ip); |
252b5132 | 2445 | if (pinfo & MIPS16_INSN_WRITE_Z) |
bf12938e | 2446 | mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (RZ, *ip); |
252b5132 RH |
2447 | if (pinfo & (MIPS16_INSN_WRITE_T | MIPS16_INSN_READ_T)) |
2448 | mips_gprmask |= 1 << TREG; | |
2449 | if (pinfo & (MIPS16_INSN_WRITE_SP | MIPS16_INSN_READ_SP)) | |
2450 | mips_gprmask |= 1 << SP; | |
2451 | if (pinfo & (MIPS16_INSN_WRITE_31 | MIPS16_INSN_READ_31)) | |
2452 | mips_gprmask |= 1 << RA; | |
2453 | if (pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
2454 | mips_gprmask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode); | |
2455 | if (pinfo & MIPS16_INSN_READ_Z) | |
bf12938e | 2456 | mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (MOVE32Z, *ip); |
252b5132 | 2457 | if (pinfo & MIPS16_INSN_READ_GPR_X) |
bf12938e | 2458 | mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (REGR32, *ip); |
252b5132 RH |
2459 | } |
2460 | ||
4d7206a2 | 2461 | if (mips_relax.sequence != 2 && !mips_opts.noreorder) |
252b5132 RH |
2462 | { |
2463 | /* Filling the branch delay slot is more complex. We try to | |
2464 | switch the branch with the previous instruction, which we can | |
2465 | do if the previous instruction does not set up a condition | |
2466 | that the branch tests and if the branch is not itself the | |
2467 | target of any branch. */ | |
2468 | if ((pinfo & INSN_UNCOND_BRANCH_DELAY) | |
2469 | || (pinfo & INSN_COND_BRANCH_DELAY)) | |
2470 | { | |
2471 | if (mips_optimize < 2 | |
2472 | /* If we have seen .set volatile or .set nomove, don't | |
2473 | optimize. */ | |
2474 | || mips_opts.nomove != 0 | |
a38419a5 RS |
2475 | /* We can't swap if the previous instruction's position |
2476 | is fixed. */ | |
2477 | || history[0].fixed_p | |
252b5132 RH |
2478 | /* If the previous previous insn was in a .set |
2479 | noreorder, we can't swap. Actually, the MIPS | |
2480 | assembler will swap in this situation. However, gcc | |
2481 | configured -with-gnu-as will generate code like | |
2482 | .set noreorder | |
2483 | lw $4,XXX | |
2484 | .set reorder | |
2485 | INSN | |
2486 | bne $4,$0,foo | |
2487 | in which we can not swap the bne and INSN. If gcc is | |
2488 | not configured -with-gnu-as, it does not output the | |
a38419a5 | 2489 | .set pseudo-ops. */ |
47e39b9d | 2490 | || history[1].noreorder_p |
252b5132 RH |
2491 | /* If the branch is itself the target of a branch, we |
2492 | can not swap. We cheat on this; all we check for is | |
2493 | whether there is a label on this instruction. If | |
2494 | there are any branches to anything other than a | |
2495 | label, users must use .set noreorder. */ | |
2496 | || insn_labels != NULL | |
895921c9 MR |
2497 | /* If the previous instruction is in a variant frag |
2498 | other than this branch's one, we cannot do the swap. | |
2499 | This does not apply to the mips16, which uses variant | |
2500 | frags for different purposes. */ | |
252b5132 | 2501 | || (! mips_opts.mips16 |
895921c9 | 2502 | && prev_insn_frag_type == rs_machine_dependent) |
252b5132 RH |
2503 | /* If the branch reads the condition codes, we don't |
2504 | even try to swap, because in the sequence | |
2505 | ctc1 $X,$31 | |
2506 | INSN | |
2507 | INSN | |
2508 | bc1t LABEL | |
2509 | we can not swap, and I don't feel like handling that | |
2510 | case. */ | |
2511 | || (! mips_opts.mips16 | |
81912461 ILT |
2512 | && (pinfo & INSN_READ_COND_CODE) |
2513 | && ! cop_interlocks) | |
252b5132 | 2514 | /* We can not swap with an instruction that requires a |
67c1ffbe | 2515 | delay slot, because the target of the branch might |
252b5132 RH |
2516 | interfere with that instruction. */ |
2517 | || (! mips_opts.mips16 | |
252b5132 | 2518 | && (prev_pinfo |
bdaaa2e1 | 2519 | /* Itbl support may require additional care here. */ |
252b5132 RH |
2520 | & (INSN_LOAD_COPROC_DELAY |
2521 | | INSN_COPROC_MOVE_DELAY | |
81912461 ILT |
2522 | | INSN_WRITE_COND_CODE)) |
2523 | && ! cop_interlocks) | |
252b5132 | 2524 | || (! (hilo_interlocks |
048cdf86 | 2525 | || (mips_opts.arch == CPU_R3900 && (pinfo & INSN_MULT))) |
252b5132 RH |
2526 | && (prev_pinfo |
2527 | & (INSN_READ_LO | |
2528 | | INSN_READ_HI))) | |
2529 | || (! mips_opts.mips16 | |
81912461 ILT |
2530 | && (prev_pinfo & INSN_LOAD_MEMORY_DELAY) |
2531 | && ! gpr_interlocks) | |
252b5132 | 2532 | || (! mips_opts.mips16 |
bdaaa2e1 | 2533 | /* Itbl support may require additional care here. */ |
81912461 ILT |
2534 | && (prev_pinfo & INSN_COPROC_MEMORY_DELAY) |
2535 | && ! cop_mem_interlocks) | |
252b5132 RH |
2536 | /* We do not swap with a trap instruction, since it |
2537 | complicates trap handlers to have the trap | |
2538 | instruction be in a delay slot. */ | |
2539 | || (prev_pinfo & INSN_TRAP) | |
2540 | /* If the branch reads a register that the previous | |
2541 | instruction sets, we can not swap. */ | |
2542 | || (! mips_opts.mips16 | |
2543 | && (prev_pinfo & INSN_WRITE_GPR_T) | |
bf12938e | 2544 | && insn_uses_reg (ip, EXTRACT_OPERAND (RT, history[0]), |
252b5132 RH |
2545 | MIPS_GR_REG)) |
2546 | || (! mips_opts.mips16 | |
2547 | && (prev_pinfo & INSN_WRITE_GPR_D) | |
bf12938e | 2548 | && insn_uses_reg (ip, EXTRACT_OPERAND (RD, history[0]), |
252b5132 RH |
2549 | MIPS_GR_REG)) |
2550 | || (mips_opts.mips16 | |
2551 | && (((prev_pinfo & MIPS16_INSN_WRITE_X) | |
bf12938e RS |
2552 | && (insn_uses_reg |
2553 | (ip, MIPS16_EXTRACT_OPERAND (RX, history[0]), | |
2554 | MIPS16_REG))) | |
252b5132 | 2555 | || ((prev_pinfo & MIPS16_INSN_WRITE_Y) |
bf12938e RS |
2556 | && (insn_uses_reg |
2557 | (ip, MIPS16_EXTRACT_OPERAND (RY, history[0]), | |
2558 | MIPS16_REG))) | |
252b5132 | 2559 | || ((prev_pinfo & MIPS16_INSN_WRITE_Z) |
bf12938e RS |
2560 | && (insn_uses_reg |
2561 | (ip, MIPS16_EXTRACT_OPERAND (RZ, history[0]), | |
2562 | MIPS16_REG))) | |
252b5132 RH |
2563 | || ((prev_pinfo & MIPS16_INSN_WRITE_T) |
2564 | && insn_uses_reg (ip, TREG, MIPS_GR_REG)) | |
2565 | || ((prev_pinfo & MIPS16_INSN_WRITE_31) | |
2566 | && insn_uses_reg (ip, RA, MIPS_GR_REG)) | |
2567 | || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
2568 | && insn_uses_reg (ip, | |
47e39b9d RS |
2569 | MIPS16OP_EXTRACT_REG32R |
2570 | (history[0].insn_opcode), | |
252b5132 RH |
2571 | MIPS_GR_REG)))) |
2572 | /* If the branch writes a register that the previous | |
2573 | instruction sets, we can not swap (we know that | |
2574 | branches write only to RD or to $31). */ | |
2575 | || (! mips_opts.mips16 | |
2576 | && (prev_pinfo & INSN_WRITE_GPR_T) | |
2577 | && (((pinfo & INSN_WRITE_GPR_D) | |
bf12938e RS |
2578 | && (EXTRACT_OPERAND (RT, history[0]) |
2579 | == EXTRACT_OPERAND (RD, *ip))) | |
252b5132 | 2580 | || ((pinfo & INSN_WRITE_GPR_31) |
bf12938e | 2581 | && EXTRACT_OPERAND (RT, history[0]) == RA))) |
252b5132 RH |
2582 | || (! mips_opts.mips16 |
2583 | && (prev_pinfo & INSN_WRITE_GPR_D) | |
2584 | && (((pinfo & INSN_WRITE_GPR_D) | |
bf12938e RS |
2585 | && (EXTRACT_OPERAND (RD, history[0]) |
2586 | == EXTRACT_OPERAND (RD, *ip))) | |
252b5132 | 2587 | || ((pinfo & INSN_WRITE_GPR_31) |
bf12938e | 2588 | && EXTRACT_OPERAND (RD, history[0]) == RA))) |
252b5132 RH |
2589 | || (mips_opts.mips16 |
2590 | && (pinfo & MIPS16_INSN_WRITE_31) | |
2591 | && ((prev_pinfo & MIPS16_INSN_WRITE_31) | |
2592 | || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
47e39b9d | 2593 | && (MIPS16OP_EXTRACT_REG32R (history[0].insn_opcode) |
252b5132 RH |
2594 | == RA)))) |
2595 | /* If the branch writes a register that the previous | |
2596 | instruction reads, we can not swap (we know that | |
2597 | branches only write to RD or to $31). */ | |
2598 | || (! mips_opts.mips16 | |
2599 | && (pinfo & INSN_WRITE_GPR_D) | |
47e39b9d | 2600 | && insn_uses_reg (&history[0], |
bf12938e | 2601 | EXTRACT_OPERAND (RD, *ip), |
252b5132 RH |
2602 | MIPS_GR_REG)) |
2603 | || (! mips_opts.mips16 | |
2604 | && (pinfo & INSN_WRITE_GPR_31) | |
47e39b9d | 2605 | && insn_uses_reg (&history[0], RA, MIPS_GR_REG)) |
252b5132 RH |
2606 | || (mips_opts.mips16 |
2607 | && (pinfo & MIPS16_INSN_WRITE_31) | |
47e39b9d | 2608 | && insn_uses_reg (&history[0], RA, MIPS_GR_REG)) |
252b5132 RH |
2609 | /* If the previous previous instruction has a load |
2610 | delay, and sets a register that the branch reads, we | |
2611 | can not swap. */ | |
2612 | || (! mips_opts.mips16 | |
bdaaa2e1 | 2613 | /* Itbl support may require additional care here. */ |
47e39b9d | 2614 | && (((history[1].insn_mo->pinfo & INSN_LOAD_COPROC_DELAY) |
81912461 | 2615 | && ! cop_interlocks) |
47e39b9d | 2616 | || ((history[1].insn_mo->pinfo |
81912461 ILT |
2617 | & INSN_LOAD_MEMORY_DELAY) |
2618 | && ! gpr_interlocks)) | |
bf12938e | 2619 | && insn_uses_reg (ip, EXTRACT_OPERAND (RT, history[1]), |
252b5132 RH |
2620 | MIPS_GR_REG)) |
2621 | /* If one instruction sets a condition code and the | |
2622 | other one uses a condition code, we can not swap. */ | |
2623 | || ((pinfo & INSN_READ_COND_CODE) | |
2624 | && (prev_pinfo & INSN_WRITE_COND_CODE)) | |
2625 | || ((pinfo & INSN_WRITE_COND_CODE) | |
2626 | && (prev_pinfo & INSN_READ_COND_CODE)) | |
2627 | /* If the previous instruction uses the PC, we can not | |
2628 | swap. */ | |
2629 | || (mips_opts.mips16 | |
2630 | && (prev_pinfo & MIPS16_INSN_READ_PC)) | |
252b5132 RH |
2631 | /* If the previous instruction had a fixup in mips16 |
2632 | mode, we can not swap. This normally means that the | |
2633 | previous instruction was a 4 byte branch anyhow. */ | |
47e39b9d | 2634 | || (mips_opts.mips16 && history[0].fixp[0]) |
bdaaa2e1 KH |
2635 | /* If the previous instruction is a sync, sync.l, or |
2636 | sync.p, we can not swap. */ | |
f173e82e | 2637 | || (prev_pinfo & INSN_SYNC)) |
252b5132 RH |
2638 | { |
2639 | /* We could do even better for unconditional branches to | |
2640 | portions of this object file; we could pick up the | |
2641 | instruction at the destination, put it in the delay | |
2642 | slot, and bump the destination address. */ | |
1e915849 | 2643 | insert_into_history (0, 1, ip); |
252b5132 | 2644 | emit_nop (); |
dd22970f ILT |
2645 | if (mips_relax.sequence) |
2646 | mips_relax.sizes[mips_relax.sequence - 1] += 4; | |
252b5132 RH |
2647 | } |
2648 | else | |
2649 | { | |
2650 | /* It looks like we can actually do the swap. */ | |
1e915849 RS |
2651 | struct mips_cl_insn delay = history[0]; |
2652 | if (mips_opts.mips16) | |
252b5132 | 2653 | { |
1e915849 RS |
2654 | know (delay.frag == ip->frag); |
2655 | move_insn (ip, delay.frag, delay.where); | |
2656 | move_insn (&delay, ip->frag, ip->where + insn_length (ip)); | |
2657 | } | |
2658 | else if (relaxed_branch) | |
2659 | { | |
2660 | /* Add the delay slot instruction to the end of the | |
2661 | current frag and shrink the fixed part of the | |
2662 | original frag. If the branch occupies the tail of | |
2663 | the latter, move it backwards to cover the gap. */ | |
2664 | delay.frag->fr_fix -= 4; | |
2665 | if (delay.frag == ip->frag) | |
2666 | move_insn (ip, ip->frag, ip->where - 4); | |
2667 | add_fixed_insn (&delay); | |
252b5132 RH |
2668 | } |
2669 | else | |
2670 | { | |
1e915849 RS |
2671 | move_insn (&delay, ip->frag, ip->where); |
2672 | move_insn (ip, history[0].frag, history[0].where); | |
252b5132 | 2673 | } |
1e915849 RS |
2674 | history[0] = *ip; |
2675 | delay.fixed_p = 1; | |
2676 | insert_into_history (0, 1, &delay); | |
252b5132 | 2677 | } |
252b5132 RH |
2678 | |
2679 | /* If that was an unconditional branch, forget the previous | |
2680 | insn information. */ | |
2681 | if (pinfo & INSN_UNCOND_BRANCH_DELAY) | |
1e915849 | 2682 | mips_no_prev_insn (FALSE); |
252b5132 RH |
2683 | } |
2684 | else if (pinfo & INSN_COND_BRANCH_LIKELY) | |
2685 | { | |
2686 | /* We don't yet optimize a branch likely. What we should do | |
2687 | is look at the target, copy the instruction found there | |
2688 | into the delay slot, and increment the branch to jump to | |
2689 | the next instruction. */ | |
1e915849 | 2690 | insert_into_history (0, 1, ip); |
252b5132 | 2691 | emit_nop (); |
252b5132 RH |
2692 | } |
2693 | else | |
1e915849 | 2694 | insert_into_history (0, 1, ip); |
252b5132 | 2695 | } |
1e915849 RS |
2696 | else |
2697 | insert_into_history (0, 1, ip); | |
252b5132 RH |
2698 | |
2699 | /* We just output an insn, so the next one doesn't have a label. */ | |
2700 | mips_clear_insn_labels (); | |
252b5132 RH |
2701 | } |
2702 | ||
2703 | /* This function forgets that there was any previous instruction or | |
2704 | label. If PRESERVE is non-zero, it remembers enough information to | |
bdaaa2e1 | 2705 | know whether nops are needed before a noreorder section. */ |
252b5132 RH |
2706 | |
2707 | static void | |
17a2f251 | 2708 | mips_no_prev_insn (int preserve) |
252b5132 | 2709 | { |
1e915849 RS |
2710 | size_t i; |
2711 | ||
252b5132 RH |
2712 | if (! preserve) |
2713 | { | |
252b5132 RH |
2714 | prev_nop_frag = NULL; |
2715 | prev_nop_frag_holds = 0; | |
2716 | prev_nop_frag_required = 0; | |
2717 | prev_nop_frag_since = 0; | |
1e915849 RS |
2718 | for (i = 0; i < ARRAY_SIZE (history); i++) |
2719 | history[i] = (mips_opts.mips16 ? mips16_nop_insn : nop_insn); | |
252b5132 | 2720 | } |
1e915849 RS |
2721 | else |
2722 | for (i = 0; i < ARRAY_SIZE (history); i++) | |
2723 | { | |
2724 | history[i].fixed_p = 1; | |
2725 | history[i].noreorder_p = 0; | |
2726 | history[i].mips16_absolute_jump_p = 0; | |
2727 | } | |
252b5132 RH |
2728 | mips_clear_insn_labels (); |
2729 | } | |
2730 | ||
2731 | /* This function must be called whenever we turn on noreorder or emit | |
2732 | something other than instructions. It inserts any NOPS which might | |
2733 | be needed by the previous instruction, and clears the information | |
2734 | kept for the previous instructions. The INSNS parameter is true if | |
bdaaa2e1 | 2735 | instructions are to follow. */ |
252b5132 RH |
2736 | |
2737 | static void | |
17a2f251 | 2738 | mips_emit_delays (bfd_boolean insns) |
252b5132 RH |
2739 | { |
2740 | if (! mips_opts.noreorder) | |
2741 | { | |
2742 | int nops; | |
2743 | ||
2744 | nops = 0; | |
2745 | if ((! mips_opts.mips16 | |
47e39b9d | 2746 | && ((history[0].insn_mo->pinfo |
81912461 ILT |
2747 | & (INSN_LOAD_COPROC_DELAY |
2748 | | INSN_COPROC_MOVE_DELAY | |
2749 | | INSN_WRITE_COND_CODE)) | |
2750 | && ! cop_interlocks)) | |
252b5132 | 2751 | || (! hilo_interlocks |
47e39b9d | 2752 | && (history[0].insn_mo->pinfo |
252b5132 RH |
2753 | & (INSN_READ_LO |
2754 | | INSN_READ_HI))) | |
2755 | || (! mips_opts.mips16 | |
47e39b9d | 2756 | && (history[0].insn_mo->pinfo & INSN_LOAD_MEMORY_DELAY) |
81912461 | 2757 | && ! gpr_interlocks) |
252b5132 | 2758 | || (! mips_opts.mips16 |
47e39b9d | 2759 | && (history[0].insn_mo->pinfo & INSN_COPROC_MEMORY_DELAY) |
81912461 | 2760 | && ! cop_mem_interlocks)) |
252b5132 | 2761 | { |
beae10d5 | 2762 | /* Itbl support may require additional care here. */ |
252b5132 RH |
2763 | ++nops; |
2764 | if ((! mips_opts.mips16 | |
47e39b9d | 2765 | && ((history[0].insn_mo->pinfo & INSN_WRITE_COND_CODE) |
81912461 | 2766 | && ! cop_interlocks)) |
252b5132 | 2767 | || (! hilo_interlocks |
47e39b9d RS |
2768 | && ((history[0].insn_mo->pinfo & INSN_READ_HI) |
2769 | || (history[0].insn_mo->pinfo & INSN_READ_LO)))) | |
252b5132 RH |
2770 | ++nops; |
2771 | ||
47e39b9d | 2772 | if (history[0].noreorder_p) |
252b5132 RH |
2773 | nops = 0; |
2774 | } | |
2775 | else if ((! mips_opts.mips16 | |
47e39b9d | 2776 | && ((history[1].insn_mo->pinfo & INSN_WRITE_COND_CODE) |
81912461 | 2777 | && ! cop_interlocks)) |
252b5132 | 2778 | || (! hilo_interlocks |
47e39b9d RS |
2779 | && ((history[1].insn_mo->pinfo & INSN_READ_HI) |
2780 | || (history[1].insn_mo->pinfo & INSN_READ_LO)))) | |
252b5132 | 2781 | { |
beae10d5 | 2782 | /* Itbl support may require additional care here. */ |
47e39b9d | 2783 | if (! history[1].noreorder_p) |
252b5132 RH |
2784 | ++nops; |
2785 | } | |
2786 | ||
47e39b9d | 2787 | if (mips_fix_vr4120 && history[0].insn_mo->name) |
60b63b72 RS |
2788 | { |
2789 | int min_nops = 0; | |
47e39b9d | 2790 | const char *pn = history[0].insn_mo->name; |
532c738a RS |
2791 | if (strncmp (pn, "macc", 4) == 0 |
2792 | || strncmp (pn, "dmacc", 5) == 0 | |
2793 | || strncmp (pn, "dmult", 5) == 0 | |
2794 | || strstr (pn, "div")) | |
2795 | min_nops = 1; | |
60b63b72 RS |
2796 | if (nops < min_nops) |
2797 | nops = min_nops; | |
2798 | } | |
2799 | ||
252b5132 RH |
2800 | if (nops > 0) |
2801 | { | |
2802 | struct insn_label_list *l; | |
2803 | ||
2804 | if (insns) | |
2805 | { | |
2806 | /* Record the frag which holds the nop instructions, so | |
2807 | that we can remove them if we don't need them. */ | |
2808 | frag_grow (mips_opts.mips16 ? nops * 2 : nops * 4); | |
2809 | prev_nop_frag = frag_now; | |
2810 | prev_nop_frag_holds = nops; | |
2811 | prev_nop_frag_required = 0; | |
2812 | prev_nop_frag_since = 0; | |
2813 | } | |
2814 | ||
2815 | for (; nops > 0; --nops) | |
1e915849 | 2816 | add_fixed_insn (NOP_INSN); |
252b5132 RH |
2817 | |
2818 | if (insns) | |
2819 | { | |
2820 | /* Move on to a new frag, so that it is safe to simply | |
bdaaa2e1 | 2821 | decrease the size of prev_nop_frag. */ |
252b5132 RH |
2822 | frag_wane (frag_now); |
2823 | frag_new (0); | |
2824 | } | |
2825 | ||
2826 | for (l = insn_labels; l != NULL; l = l->next) | |
2827 | { | |
98aa84af AM |
2828 | valueT val; |
2829 | ||
252b5132 | 2830 | assert (S_GET_SEGMENT (l->label) == now_seg); |
49309057 | 2831 | symbol_set_frag (l->label, frag_now); |
98aa84af | 2832 | val = (valueT) frag_now_fix (); |
252b5132 RH |
2833 | /* mips16 text labels are stored as odd. */ |
2834 | if (mips_opts.mips16) | |
f9419b05 | 2835 | ++val; |
98aa84af | 2836 | S_SET_VALUE (l->label, val); |
252b5132 RH |
2837 | } |
2838 | } | |
2839 | } | |
2840 | ||
2841 | /* Mark instruction labels in mips16 mode. */ | |
f9419b05 | 2842 | if (insns) |
252b5132 RH |
2843 | mips16_mark_labels (); |
2844 | ||
2845 | mips_no_prev_insn (insns); | |
2846 | } | |
2847 | ||
584892a6 RS |
2848 | /* Set up global variables for the start of a new macro. */ |
2849 | ||
2850 | static void | |
2851 | macro_start (void) | |
2852 | { | |
2853 | memset (&mips_macro_warning.sizes, 0, sizeof (mips_macro_warning.sizes)); | |
2854 | mips_macro_warning.delay_slot_p = (mips_opts.noreorder | |
47e39b9d | 2855 | && (history[0].insn_mo->pinfo |
584892a6 RS |
2856 | & (INSN_UNCOND_BRANCH_DELAY |
2857 | | INSN_COND_BRANCH_DELAY | |
2858 | | INSN_COND_BRANCH_LIKELY)) != 0); | |
2859 | } | |
2860 | ||
2861 | /* Given that a macro is longer than 4 bytes, return the appropriate warning | |
2862 | for it. Return null if no warning is needed. SUBTYPE is a bitmask of | |
2863 | RELAX_DELAY_SLOT and RELAX_NOMACRO. */ | |
2864 | ||
2865 | static const char * | |
2866 | macro_warning (relax_substateT subtype) | |
2867 | { | |
2868 | if (subtype & RELAX_DELAY_SLOT) | |
2869 | return _("Macro instruction expanded into multiple instructions" | |
2870 | " in a branch delay slot"); | |
2871 | else if (subtype & RELAX_NOMACRO) | |
2872 | return _("Macro instruction expanded into multiple instructions"); | |
2873 | else | |
2874 | return 0; | |
2875 | } | |
2876 | ||
2877 | /* Finish up a macro. Emit warnings as appropriate. */ | |
2878 | ||
2879 | static void | |
2880 | macro_end (void) | |
2881 | { | |
2882 | if (mips_macro_warning.sizes[0] > 4 || mips_macro_warning.sizes[1] > 4) | |
2883 | { | |
2884 | relax_substateT subtype; | |
2885 | ||
2886 | /* Set up the relaxation warning flags. */ | |
2887 | subtype = 0; | |
2888 | if (mips_macro_warning.sizes[1] > mips_macro_warning.sizes[0]) | |
2889 | subtype |= RELAX_SECOND_LONGER; | |
2890 | if (mips_opts.warn_about_macros) | |
2891 | subtype |= RELAX_NOMACRO; | |
2892 | if (mips_macro_warning.delay_slot_p) | |
2893 | subtype |= RELAX_DELAY_SLOT; | |
2894 | ||
2895 | if (mips_macro_warning.sizes[0] > 4 && mips_macro_warning.sizes[1] > 4) | |
2896 | { | |
2897 | /* Either the macro has a single implementation or both | |
2898 | implementations are longer than 4 bytes. Emit the | |
2899 | warning now. */ | |
2900 | const char *msg = macro_warning (subtype); | |
2901 | if (msg != 0) | |
2902 | as_warn (msg); | |
2903 | } | |
2904 | else | |
2905 | { | |
2906 | /* One implementation might need a warning but the other | |
2907 | definitely doesn't. */ | |
2908 | mips_macro_warning.first_frag->fr_subtype |= subtype; | |
2909 | } | |
2910 | } | |
2911 | } | |
2912 | ||
6e1304d8 RS |
2913 | /* Read a macro's relocation codes from *ARGS and store them in *R. |
2914 | The first argument in *ARGS will be either the code for a single | |
2915 | relocation or -1 followed by the three codes that make up a | |
2916 | composite relocation. */ | |
2917 | ||
2918 | static void | |
2919 | macro_read_relocs (va_list *args, bfd_reloc_code_real_type *r) | |
2920 | { | |
2921 | int i, next; | |
2922 | ||
2923 | next = va_arg (*args, int); | |
2924 | if (next >= 0) | |
2925 | r[0] = (bfd_reloc_code_real_type) next; | |
2926 | else | |
2927 | for (i = 0; i < 3; i++) | |
2928 | r[i] = (bfd_reloc_code_real_type) va_arg (*args, int); | |
2929 | } | |
2930 | ||
252b5132 RH |
2931 | /* Build an instruction created by a macro expansion. This is passed |
2932 | a pointer to the count of instructions created so far, an | |
2933 | expression, the name of the instruction to build, an operand format | |
2934 | string, and corresponding arguments. */ | |
2935 | ||
252b5132 | 2936 | static void |
67c0d1eb | 2937 | macro_build (expressionS *ep, const char *name, const char *fmt, ...) |
252b5132 | 2938 | { |
1e915849 | 2939 | const struct mips_opcode *mo; |
252b5132 | 2940 | struct mips_cl_insn insn; |
f6688943 | 2941 | bfd_reloc_code_real_type r[3]; |
252b5132 | 2942 | va_list args; |
252b5132 | 2943 | |
252b5132 | 2944 | va_start (args, fmt); |
252b5132 | 2945 | |
252b5132 RH |
2946 | if (mips_opts.mips16) |
2947 | { | |
67c0d1eb | 2948 | mips16_macro_build (ep, name, fmt, args); |
252b5132 RH |
2949 | va_end (args); |
2950 | return; | |
2951 | } | |
2952 | ||
f6688943 TS |
2953 | r[0] = BFD_RELOC_UNUSED; |
2954 | r[1] = BFD_RELOC_UNUSED; | |
2955 | r[2] = BFD_RELOC_UNUSED; | |
1e915849 RS |
2956 | mo = (struct mips_opcode *) hash_find (op_hash, name); |
2957 | assert (mo); | |
2958 | assert (strcmp (name, mo->name) == 0); | |
2959 | ||
2960 | /* Search until we get a match for NAME. It is assumed here that | |
2961 | macros will never generate MDMX or MIPS-3D instructions. */ | |
2962 | while (strcmp (fmt, mo->args) != 0 | |
2963 | || mo->pinfo == INSN_MACRO | |
2964 | || !OPCODE_IS_MEMBER (mo, | |
2965 | (mips_opts.isa | |
2966 | | (file_ase_mips16 ? INSN_MIPS16 : 0)), | |
fef14a42 | 2967 | mips_opts.arch) |
1e915849 RS |
2968 | || (mips_opts.arch == CPU_R4650 && (mo->pinfo & FP_D) != 0)) |
2969 | { | |
2970 | ++mo; | |
2971 | assert (mo->name); | |
2972 | assert (strcmp (name, mo->name) == 0); | |
252b5132 RH |
2973 | } |
2974 | ||
1e915849 | 2975 | create_insn (&insn, mo); |
252b5132 RH |
2976 | for (;;) |
2977 | { | |
2978 | switch (*fmt++) | |
2979 | { | |
2980 | case '\0': | |
2981 | break; | |
2982 | ||
2983 | case ',': | |
2984 | case '(': | |
2985 | case ')': | |
2986 | continue; | |
2987 | ||
5f74bc13 CD |
2988 | case '+': |
2989 | switch (*fmt++) | |
2990 | { | |
2991 | case 'A': | |
2992 | case 'E': | |
bf12938e | 2993 | INSERT_OPERAND (SHAMT, insn, va_arg (args, int)); |
5f74bc13 CD |
2994 | continue; |
2995 | ||
2996 | case 'B': | |
2997 | case 'F': | |
2998 | /* Note that in the macro case, these arguments are already | |
2999 | in MSB form. (When handling the instruction in the | |
3000 | non-macro case, these arguments are sizes from which | |
3001 | MSB values must be calculated.) */ | |
bf12938e | 3002 | INSERT_OPERAND (INSMSB, insn, va_arg (args, int)); |
5f74bc13 CD |
3003 | continue; |
3004 | ||
3005 | case 'C': | |
3006 | case 'G': | |
3007 | case 'H': | |
3008 | /* Note that in the macro case, these arguments are already | |
3009 | in MSBD form. (When handling the instruction in the | |
3010 | non-macro case, these arguments are sizes from which | |
3011 | MSBD values must be calculated.) */ | |
bf12938e | 3012 | INSERT_OPERAND (EXTMSBD, insn, va_arg (args, int)); |
5f74bc13 CD |
3013 | continue; |
3014 | ||
3015 | default: | |
3016 | internalError (); | |
3017 | } | |
3018 | continue; | |
3019 | ||
252b5132 RH |
3020 | case 't': |
3021 | case 'w': | |
3022 | case 'E': | |
bf12938e | 3023 | INSERT_OPERAND (RT, insn, va_arg (args, int)); |
252b5132 RH |
3024 | continue; |
3025 | ||
3026 | case 'c': | |
bf12938e | 3027 | INSERT_OPERAND (CODE, insn, va_arg (args, int)); |
38487616 TS |
3028 | continue; |
3029 | ||
252b5132 RH |
3030 | case 'T': |
3031 | case 'W': | |
bf12938e | 3032 | INSERT_OPERAND (FT, insn, va_arg (args, int)); |
252b5132 RH |
3033 | continue; |
3034 | ||
3035 | case 'd': | |
3036 | case 'G': | |
af7ee8bf | 3037 | case 'K': |
bf12938e | 3038 | INSERT_OPERAND (RD, insn, va_arg (args, int)); |
252b5132 RH |
3039 | continue; |
3040 | ||
4372b673 NC |
3041 | case 'U': |
3042 | { | |
3043 | int tmp = va_arg (args, int); | |
3044 | ||
bf12938e RS |
3045 | INSERT_OPERAND (RT, insn, tmp); |
3046 | INSERT_OPERAND (RD, insn, tmp); | |
beae10d5 | 3047 | continue; |
4372b673 NC |
3048 | } |
3049 | ||
252b5132 RH |
3050 | case 'V': |
3051 | case 'S': | |
bf12938e | 3052 | INSERT_OPERAND (FS, insn, va_arg (args, int)); |
252b5132 RH |
3053 | continue; |
3054 | ||
3055 | case 'z': | |
3056 | continue; | |
3057 | ||
3058 | case '<': | |
bf12938e | 3059 | INSERT_OPERAND (SHAMT, insn, va_arg (args, int)); |
252b5132 RH |
3060 | continue; |
3061 | ||
3062 | case 'D': | |
bf12938e | 3063 | INSERT_OPERAND (FD, insn, va_arg (args, int)); |
252b5132 RH |
3064 | continue; |
3065 | ||
3066 | case 'B': | |
bf12938e | 3067 | INSERT_OPERAND (CODE20, insn, va_arg (args, int)); |
252b5132 RH |
3068 | continue; |
3069 | ||
4372b673 | 3070 | case 'J': |
bf12938e | 3071 | INSERT_OPERAND (CODE19, insn, va_arg (args, int)); |
4372b673 NC |
3072 | continue; |
3073 | ||
252b5132 | 3074 | case 'q': |
bf12938e | 3075 | INSERT_OPERAND (CODE2, insn, va_arg (args, int)); |
252b5132 RH |
3076 | continue; |
3077 | ||
3078 | case 'b': | |
3079 | case 's': | |
3080 | case 'r': | |
3081 | case 'v': | |
bf12938e | 3082 | INSERT_OPERAND (RS, insn, va_arg (args, int)); |
252b5132 RH |
3083 | continue; |
3084 | ||
3085 | case 'i': | |
3086 | case 'j': | |
3087 | case 'o': | |
6e1304d8 | 3088 | macro_read_relocs (&args, r); |
cdf6fd85 | 3089 | assert (*r == BFD_RELOC_GPREL16 |
f6688943 TS |
3090 | || *r == BFD_RELOC_MIPS_LITERAL |
3091 | || *r == BFD_RELOC_MIPS_HIGHER | |
3092 | || *r == BFD_RELOC_HI16_S | |
3093 | || *r == BFD_RELOC_LO16 | |
3094 | || *r == BFD_RELOC_MIPS_GOT16 | |
3095 | || *r == BFD_RELOC_MIPS_CALL16 | |
438c16b8 TS |
3096 | || *r == BFD_RELOC_MIPS_GOT_DISP |
3097 | || *r == BFD_RELOC_MIPS_GOT_PAGE | |
3098 | || *r == BFD_RELOC_MIPS_GOT_OFST | |
f6688943 | 3099 | || *r == BFD_RELOC_MIPS_GOT_LO16 |
3e722fb5 | 3100 | || *r == BFD_RELOC_MIPS_CALL_LO16); |
252b5132 RH |
3101 | continue; |
3102 | ||
3103 | case 'u': | |
6e1304d8 | 3104 | macro_read_relocs (&args, r); |
252b5132 RH |
3105 | assert (ep != NULL |
3106 | && (ep->X_op == O_constant | |
3107 | || (ep->X_op == O_symbol | |
f6688943 TS |
3108 | && (*r == BFD_RELOC_MIPS_HIGHEST |
3109 | || *r == BFD_RELOC_HI16_S | |
3110 | || *r == BFD_RELOC_HI16 | |
3111 | || *r == BFD_RELOC_GPREL16 | |
3112 | || *r == BFD_RELOC_MIPS_GOT_HI16 | |
3e722fb5 | 3113 | || *r == BFD_RELOC_MIPS_CALL_HI16)))); |
252b5132 RH |
3114 | continue; |
3115 | ||
3116 | case 'p': | |
3117 | assert (ep != NULL); | |
3118 | /* | |
3119 | * This allows macro() to pass an immediate expression for | |
3120 | * creating short branches without creating a symbol. | |
0b25d3e6 AO |
3121 | * Note that the expression still might come from the assembly |
3122 | * input, in which case the value is not checked for range nor | |
3123 | * is a relocation entry generated (yuck). | |
252b5132 RH |
3124 | */ |
3125 | if (ep->X_op == O_constant) | |
3126 | { | |
3127 | insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff; | |
3128 | ep = NULL; | |
3129 | } | |
3130 | else | |
0b25d3e6 | 3131 | *r = BFD_RELOC_16_PCREL_S2; |
252b5132 RH |
3132 | continue; |
3133 | ||
3134 | case 'a': | |
3135 | assert (ep != NULL); | |
f6688943 | 3136 | *r = BFD_RELOC_MIPS_JMP; |
252b5132 RH |
3137 | continue; |
3138 | ||
3139 | case 'C': | |
3140 | insn.insn_opcode |= va_arg (args, unsigned long); | |
3141 | continue; | |
3142 | ||
3143 | default: | |
3144 | internalError (); | |
3145 | } | |
3146 | break; | |
3147 | } | |
3148 | va_end (args); | |
f6688943 | 3149 | assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
252b5132 | 3150 | |
4d7206a2 | 3151 | append_insn (&insn, ep, r); |
252b5132 RH |
3152 | } |
3153 | ||
3154 | static void | |
67c0d1eb | 3155 | mips16_macro_build (expressionS *ep, const char *name, const char *fmt, |
17a2f251 | 3156 | va_list args) |
252b5132 | 3157 | { |
1e915849 | 3158 | struct mips_opcode *mo; |
252b5132 | 3159 | struct mips_cl_insn insn; |
f6688943 TS |
3160 | bfd_reloc_code_real_type r[3] |
3161 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 3162 | |
1e915849 RS |
3163 | mo = (struct mips_opcode *) hash_find (mips16_op_hash, name); |
3164 | assert (mo); | |
3165 | assert (strcmp (name, mo->name) == 0); | |
252b5132 | 3166 | |
1e915849 | 3167 | while (strcmp (fmt, mo->args) != 0 || mo->pinfo == INSN_MACRO) |
252b5132 | 3168 | { |
1e915849 RS |
3169 | ++mo; |
3170 | assert (mo->name); | |
3171 | assert (strcmp (name, mo->name) == 0); | |
252b5132 RH |
3172 | } |
3173 | ||
1e915849 | 3174 | create_insn (&insn, mo); |
252b5132 RH |
3175 | for (;;) |
3176 | { | |
3177 | int c; | |
3178 | ||
3179 | c = *fmt++; | |
3180 | switch (c) | |
3181 | { | |
3182 | case '\0': | |
3183 | break; | |
3184 | ||
3185 | case ',': | |
3186 | case '(': | |
3187 | case ')': | |
3188 | continue; | |
3189 | ||
3190 | case 'y': | |
3191 | case 'w': | |
bf12938e | 3192 | MIPS16_INSERT_OPERAND (RY, insn, va_arg (args, int)); |
252b5132 RH |
3193 | continue; |
3194 | ||
3195 | case 'x': | |
3196 | case 'v': | |
bf12938e | 3197 | MIPS16_INSERT_OPERAND (RX, insn, va_arg (args, int)); |
252b5132 RH |
3198 | continue; |
3199 | ||
3200 | case 'z': | |
bf12938e | 3201 | MIPS16_INSERT_OPERAND (RZ, insn, va_arg (args, int)); |
252b5132 RH |
3202 | continue; |
3203 | ||
3204 | case 'Z': | |
bf12938e | 3205 | MIPS16_INSERT_OPERAND (MOVE32Z, insn, va_arg (args, int)); |
252b5132 RH |
3206 | continue; |
3207 | ||
3208 | case '0': | |
3209 | case 'S': | |
3210 | case 'P': | |
3211 | case 'R': | |
3212 | continue; | |
3213 | ||
3214 | case 'X': | |
bf12938e | 3215 | MIPS16_INSERT_OPERAND (REGR32, insn, va_arg (args, int)); |
252b5132 RH |
3216 | continue; |
3217 | ||
3218 | case 'Y': | |
3219 | { | |
3220 | int regno; | |
3221 | ||
3222 | regno = va_arg (args, int); | |
3223 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); | |
3224 | insn.insn_opcode |= regno << MIPS16OP_SH_REG32R; | |
3225 | } | |
3226 | continue; | |
3227 | ||
3228 | case '<': | |
3229 | case '>': | |
3230 | case '4': | |
3231 | case '5': | |
3232 | case 'H': | |
3233 | case 'W': | |
3234 | case 'D': | |
3235 | case 'j': | |
3236 | case '8': | |
3237 | case 'V': | |
3238 | case 'C': | |
3239 | case 'U': | |
3240 | case 'k': | |
3241 | case 'K': | |
3242 | case 'p': | |
3243 | case 'q': | |
3244 | { | |
3245 | assert (ep != NULL); | |
3246 | ||
3247 | if (ep->X_op != O_constant) | |
874e8986 | 3248 | *r = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
3249 | else |
3250 | { | |
b34976b6 AM |
3251 | mips16_immed (NULL, 0, c, ep->X_add_number, FALSE, FALSE, |
3252 | FALSE, &insn.insn_opcode, &insn.use_extend, | |
c4e7957c | 3253 | &insn.extend); |
252b5132 | 3254 | ep = NULL; |
f6688943 | 3255 | *r = BFD_RELOC_UNUSED; |
252b5132 RH |
3256 | } |
3257 | } | |
3258 | continue; | |
3259 | ||
3260 | case '6': | |
bf12938e | 3261 | MIPS16_INSERT_OPERAND (IMM6, insn, va_arg (args, int)); |
252b5132 RH |
3262 | continue; |
3263 | } | |
3264 | ||
3265 | break; | |
3266 | } | |
3267 | ||
f6688943 | 3268 | assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
252b5132 | 3269 | |
4d7206a2 | 3270 | append_insn (&insn, ep, r); |
252b5132 RH |
3271 | } |
3272 | ||
438c16b8 TS |
3273 | /* |
3274 | * Generate a "jalr" instruction with a relocation hint to the called | |
3275 | * function. This occurs in NewABI PIC code. | |
3276 | */ | |
3277 | static void | |
67c0d1eb | 3278 | macro_build_jalr (expressionS *ep) |
438c16b8 | 3279 | { |
685736be | 3280 | char *f = NULL; |
b34976b6 | 3281 | |
438c16b8 | 3282 | if (HAVE_NEWABI) |
f21f8242 | 3283 | { |
cc3d92a5 | 3284 | frag_grow (8); |
f21f8242 AO |
3285 | f = frag_more (0); |
3286 | } | |
67c0d1eb | 3287 | macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG); |
438c16b8 | 3288 | if (HAVE_NEWABI) |
f21f8242 | 3289 | fix_new_exp (frag_now, f - frag_now->fr_literal, |
a105a300 | 3290 | 4, ep, FALSE, BFD_RELOC_MIPS_JALR); |
438c16b8 TS |
3291 | } |
3292 | ||
252b5132 RH |
3293 | /* |
3294 | * Generate a "lui" instruction. | |
3295 | */ | |
3296 | static void | |
67c0d1eb | 3297 | macro_build_lui (expressionS *ep, int regnum) |
252b5132 RH |
3298 | { |
3299 | expressionS high_expr; | |
1e915849 | 3300 | const struct mips_opcode *mo; |
252b5132 | 3301 | struct mips_cl_insn insn; |
f6688943 TS |
3302 | bfd_reloc_code_real_type r[3] |
3303 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
5a38dc70 AM |
3304 | const char *name = "lui"; |
3305 | const char *fmt = "t,u"; | |
252b5132 RH |
3306 | |
3307 | assert (! mips_opts.mips16); | |
3308 | ||
4d7206a2 | 3309 | high_expr = *ep; |
252b5132 RH |
3310 | |
3311 | if (high_expr.X_op == O_constant) | |
3312 | { | |
3313 | /* we can compute the instruction now without a relocation entry */ | |
e7d556df TS |
3314 | high_expr.X_add_number = ((high_expr.X_add_number + 0x8000) |
3315 | >> 16) & 0xffff; | |
f6688943 | 3316 | *r = BFD_RELOC_UNUSED; |
252b5132 | 3317 | } |
78e1bb40 | 3318 | else |
252b5132 RH |
3319 | { |
3320 | assert (ep->X_op == O_symbol); | |
bbe506e8 TS |
3321 | /* _gp_disp is a special case, used from s_cpload. |
3322 | __gnu_local_gp is used if mips_no_shared. */ | |
252b5132 | 3323 | assert (mips_pic == NO_PIC |
78e1bb40 | 3324 | || (! HAVE_NEWABI |
aa6975fb ILT |
3325 | && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0) |
3326 | || (! mips_in_shared | |
bbe506e8 TS |
3327 | && strcmp (S_GET_NAME (ep->X_add_symbol), |
3328 | "__gnu_local_gp") == 0)); | |
f6688943 | 3329 | *r = BFD_RELOC_HI16_S; |
252b5132 RH |
3330 | } |
3331 | ||
1e915849 RS |
3332 | mo = hash_find (op_hash, name); |
3333 | assert (strcmp (name, mo->name) == 0); | |
3334 | assert (strcmp (fmt, mo->args) == 0); | |
3335 | create_insn (&insn, mo); | |
252b5132 | 3336 | |
bf12938e RS |
3337 | insn.insn_opcode = insn.insn_mo->match; |
3338 | INSERT_OPERAND (RT, insn, regnum); | |
f6688943 | 3339 | if (*r == BFD_RELOC_UNUSED) |
252b5132 RH |
3340 | { |
3341 | insn.insn_opcode |= high_expr.X_add_number; | |
4d7206a2 | 3342 | append_insn (&insn, NULL, r); |
252b5132 RH |
3343 | } |
3344 | else | |
4d7206a2 | 3345 | append_insn (&insn, &high_expr, r); |
252b5132 RH |
3346 | } |
3347 | ||
885add95 CD |
3348 | /* Generate a sequence of instructions to do a load or store from a constant |
3349 | offset off of a base register (breg) into/from a target register (treg), | |
3350 | using AT if necessary. */ | |
3351 | static void | |
67c0d1eb RS |
3352 | macro_build_ldst_constoffset (expressionS *ep, const char *op, |
3353 | int treg, int breg, int dbl) | |
885add95 CD |
3354 | { |
3355 | assert (ep->X_op == O_constant); | |
3356 | ||
256ab948 | 3357 | /* Sign-extending 32-bit constants makes their handling easier. */ |
d17e7bce TS |
3358 | if (! dbl && ! ((ep->X_add_number & ~((bfd_vma) 0x7fffffff)) |
3359 | == ~((bfd_vma) 0x7fffffff))) | |
ae826530 | 3360 | { |
d17e7bce | 3361 | if (ep->X_add_number & ~((bfd_vma) 0xffffffff)) |
1b8e29e5 | 3362 | as_bad (_("constant too large")); |
ae826530 | 3363 | |
1b8e29e5 TS |
3364 | ep->X_add_number = (((ep->X_add_number & 0xffffffff) ^ 0x80000000) |
3365 | - 0x80000000); | |
ae826530 | 3366 | } |
256ab948 | 3367 | |
67c1ffbe | 3368 | /* Right now, this routine can only handle signed 32-bit constants. */ |
ecd13cd3 | 3369 | if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000)) |
885add95 CD |
3370 | as_warn (_("operand overflow")); |
3371 | ||
3372 | if (IS_SEXT_16BIT_NUM(ep->X_add_number)) | |
3373 | { | |
3374 | /* Signed 16-bit offset will fit in the op. Easy! */ | |
67c0d1eb | 3375 | macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
885add95 CD |
3376 | } |
3377 | else | |
3378 | { | |
3379 | /* 32-bit offset, need multiple instructions and AT, like: | |
3380 | lui $tempreg,const_hi (BFD_RELOC_HI16_S) | |
3381 | addu $tempreg,$tempreg,$breg | |
3382 | <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16) | |
3383 | to handle the complete offset. */ | |
67c0d1eb RS |
3384 | macro_build_lui (ep, AT); |
3385 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); | |
3386 | macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, AT); | |
885add95 CD |
3387 | |
3388 | if (mips_opts.noat) | |
8fc2e39e | 3389 | as_bad (_("Macro used $at after \".set noat\"")); |
885add95 CD |
3390 | } |
3391 | } | |
3392 | ||
252b5132 RH |
3393 | /* set_at() |
3394 | * Generates code to set the $at register to true (one) | |
3395 | * if reg is less than the immediate expression. | |
3396 | */ | |
3397 | static void | |
67c0d1eb | 3398 | set_at (int reg, int unsignedp) |
252b5132 RH |
3399 | { |
3400 | if (imm_expr.X_op == O_constant | |
3401 | && imm_expr.X_add_number >= -0x8000 | |
3402 | && imm_expr.X_add_number < 0x8000) | |
67c0d1eb RS |
3403 | macro_build (&imm_expr, unsignedp ? "sltiu" : "slti", "t,r,j", |
3404 | AT, reg, BFD_RELOC_LO16); | |
252b5132 RH |
3405 | else |
3406 | { | |
67c0d1eb RS |
3407 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
3408 | macro_build (NULL, unsignedp ? "sltu" : "slt", "d,v,t", AT, reg, AT); | |
252b5132 RH |
3409 | } |
3410 | } | |
3411 | ||
13757d0c TS |
3412 | static void |
3413 | normalize_constant_expr (expressionS *ex) | |
3414 | { | |
3415 | if (ex->X_op == O_constant && HAVE_32BIT_GPRS) | |
3416 | ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000) | |
3417 | - 0x80000000); | |
3418 | } | |
3419 | ||
252b5132 RH |
3420 | /* Warn if an expression is not a constant. */ |
3421 | ||
3422 | static void | |
17a2f251 | 3423 | check_absolute_expr (struct mips_cl_insn *ip, expressionS *ex) |
252b5132 RH |
3424 | { |
3425 | if (ex->X_op == O_big) | |
3426 | as_bad (_("unsupported large constant")); | |
3427 | else if (ex->X_op != O_constant) | |
3428 | as_bad (_("Instruction %s requires absolute expression"), ip->insn_mo->name); | |
13757d0c TS |
3429 | |
3430 | normalize_constant_expr (ex); | |
252b5132 RH |
3431 | } |
3432 | ||
3433 | /* Count the leading zeroes by performing a binary chop. This is a | |
3434 | bulky bit of source, but performance is a LOT better for the | |
3435 | majority of values than a simple loop to count the bits: | |
3436 | for (lcnt = 0; (lcnt < 32); lcnt++) | |
3437 | if ((v) & (1 << (31 - lcnt))) | |
3438 | break; | |
3439 | However it is not code size friendly, and the gain will drop a bit | |
3440 | on certain cached systems. | |
3441 | */ | |
3442 | #define COUNT_TOP_ZEROES(v) \ | |
3443 | (((v) & ~0xffff) == 0 \ | |
3444 | ? ((v) & ~0xff) == 0 \ | |
3445 | ? ((v) & ~0xf) == 0 \ | |
3446 | ? ((v) & ~0x3) == 0 \ | |
3447 | ? ((v) & ~0x1) == 0 \ | |
3448 | ? !(v) \ | |
3449 | ? 32 \ | |
3450 | : 31 \ | |
3451 | : 30 \ | |
3452 | : ((v) & ~0x7) == 0 \ | |
3453 | ? 29 \ | |
3454 | : 28 \ | |
3455 | : ((v) & ~0x3f) == 0 \ | |
3456 | ? ((v) & ~0x1f) == 0 \ | |
3457 | ? 27 \ | |
3458 | : 26 \ | |
3459 | : ((v) & ~0x7f) == 0 \ | |
3460 | ? 25 \ | |
3461 | : 24 \ | |
3462 | : ((v) & ~0xfff) == 0 \ | |
3463 | ? ((v) & ~0x3ff) == 0 \ | |
3464 | ? ((v) & ~0x1ff) == 0 \ | |
3465 | ? 23 \ | |
3466 | : 22 \ | |
3467 | : ((v) & ~0x7ff) == 0 \ | |
3468 | ? 21 \ | |
3469 | : 20 \ | |
3470 | : ((v) & ~0x3fff) == 0 \ | |
3471 | ? ((v) & ~0x1fff) == 0 \ | |
3472 | ? 19 \ | |
3473 | : 18 \ | |
3474 | : ((v) & ~0x7fff) == 0 \ | |
3475 | ? 17 \ | |
3476 | : 16 \ | |
3477 | : ((v) & ~0xffffff) == 0 \ | |
3478 | ? ((v) & ~0xfffff) == 0 \ | |
3479 | ? ((v) & ~0x3ffff) == 0 \ | |
3480 | ? ((v) & ~0x1ffff) == 0 \ | |
3481 | ? 15 \ | |
3482 | : 14 \ | |
3483 | : ((v) & ~0x7ffff) == 0 \ | |
3484 | ? 13 \ | |
3485 | : 12 \ | |
3486 | : ((v) & ~0x3fffff) == 0 \ | |
3487 | ? ((v) & ~0x1fffff) == 0 \ | |
3488 | ? 11 \ | |
3489 | : 10 \ | |
3490 | : ((v) & ~0x7fffff) == 0 \ | |
3491 | ? 9 \ | |
3492 | : 8 \ | |
3493 | : ((v) & ~0xfffffff) == 0 \ | |
3494 | ? ((v) & ~0x3ffffff) == 0 \ | |
3495 | ? ((v) & ~0x1ffffff) == 0 \ | |
3496 | ? 7 \ | |
3497 | : 6 \ | |
3498 | : ((v) & ~0x7ffffff) == 0 \ | |
3499 | ? 5 \ | |
3500 | : 4 \ | |
3501 | : ((v) & ~0x3fffffff) == 0 \ | |
3502 | ? ((v) & ~0x1fffffff) == 0 \ | |
3503 | ? 3 \ | |
3504 | : 2 \ | |
3505 | : ((v) & ~0x7fffffff) == 0 \ | |
3506 | ? 1 \ | |
3507 | : 0) | |
3508 | ||
3509 | /* load_register() | |
67c1ffbe | 3510 | * This routine generates the least number of instructions necessary to load |
252b5132 RH |
3511 | * an absolute expression value into a register. |
3512 | */ | |
3513 | static void | |
67c0d1eb | 3514 | load_register (int reg, expressionS *ep, int dbl) |
252b5132 RH |
3515 | { |
3516 | int freg; | |
3517 | expressionS hi32, lo32; | |
3518 | ||
3519 | if (ep->X_op != O_big) | |
3520 | { | |
3521 | assert (ep->X_op == O_constant); | |
256ab948 TS |
3522 | |
3523 | /* Sign-extending 32-bit constants makes their handling easier. */ | |
d17e7bce TS |
3524 | if (! dbl && ! ((ep->X_add_number & ~((bfd_vma) 0x7fffffff)) |
3525 | == ~((bfd_vma) 0x7fffffff))) | |
ae826530 | 3526 | { |
d17e7bce | 3527 | if (ep->X_add_number & ~((bfd_vma) 0xffffffff)) |
1b8e29e5 | 3528 | as_bad (_("constant too large")); |
ae826530 | 3529 | |
1b8e29e5 TS |
3530 | ep->X_add_number = (((ep->X_add_number & 0xffffffff) ^ 0x80000000) |
3531 | - 0x80000000); | |
ae826530 | 3532 | } |
256ab948 TS |
3533 | |
3534 | if (IS_SEXT_16BIT_NUM (ep->X_add_number)) | |
252b5132 RH |
3535 | { |
3536 | /* We can handle 16 bit signed values with an addiu to | |
3537 | $zero. No need to ever use daddiu here, since $zero and | |
3538 | the result are always correct in 32 bit mode. */ | |
67c0d1eb | 3539 | macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
3540 | return; |
3541 | } | |
3542 | else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000) | |
3543 | { | |
3544 | /* We can handle 16 bit unsigned values with an ori to | |
3545 | $zero. */ | |
67c0d1eb | 3546 | macro_build (ep, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
3547 | return; |
3548 | } | |
256ab948 | 3549 | else if ((IS_SEXT_32BIT_NUM (ep->X_add_number))) |
252b5132 RH |
3550 | { |
3551 | /* 32 bit values require an lui. */ | |
67c0d1eb | 3552 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_HI16); |
252b5132 | 3553 | if ((ep->X_add_number & 0xffff) != 0) |
67c0d1eb | 3554 | macro_build (ep, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16); |
252b5132 RH |
3555 | return; |
3556 | } | |
3557 | } | |
3558 | ||
3559 | /* The value is larger than 32 bits. */ | |
3560 | ||
ca4e0257 | 3561 | if (HAVE_32BIT_GPRS) |
252b5132 | 3562 | { |
956cd1d6 TS |
3563 | as_bad (_("Number (0x%lx) larger than 32 bits"), |
3564 | (unsigned long) ep->X_add_number); | |
67c0d1eb | 3565 | macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
3566 | return; |
3567 | } | |
3568 | ||
3569 | if (ep->X_op != O_big) | |
3570 | { | |
3571 | hi32 = *ep; | |
3572 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
3573 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
3574 | hi32.X_add_number &= 0xffffffff; | |
3575 | lo32 = *ep; | |
3576 | lo32.X_add_number &= 0xffffffff; | |
3577 | } | |
3578 | else | |
3579 | { | |
3580 | assert (ep->X_add_number > 2); | |
3581 | if (ep->X_add_number == 3) | |
3582 | generic_bignum[3] = 0; | |
3583 | else if (ep->X_add_number > 4) | |
3584 | as_bad (_("Number larger than 64 bits")); | |
3585 | lo32.X_op = O_constant; | |
3586 | lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16); | |
3587 | hi32.X_op = O_constant; | |
3588 | hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16); | |
3589 | } | |
3590 | ||
3591 | if (hi32.X_add_number == 0) | |
3592 | freg = 0; | |
3593 | else | |
3594 | { | |
3595 | int shift, bit; | |
3596 | unsigned long hi, lo; | |
3597 | ||
956cd1d6 | 3598 | if (hi32.X_add_number == (offsetT) 0xffffffff) |
beae10d5 KH |
3599 | { |
3600 | if ((lo32.X_add_number & 0xffff8000) == 0xffff8000) | |
3601 | { | |
67c0d1eb | 3602 | macro_build (&lo32, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
beae10d5 KH |
3603 | return; |
3604 | } | |
3605 | if (lo32.X_add_number & 0x80000000) | |
3606 | { | |
67c0d1eb | 3607 | macro_build (&lo32, "lui", "t,u", reg, BFD_RELOC_HI16); |
252b5132 | 3608 | if (lo32.X_add_number & 0xffff) |
67c0d1eb | 3609 | macro_build (&lo32, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16); |
beae10d5 KH |
3610 | return; |
3611 | } | |
3612 | } | |
252b5132 RH |
3613 | |
3614 | /* Check for 16bit shifted constant. We know that hi32 is | |
3615 | non-zero, so start the mask on the first bit of the hi32 | |
3616 | value. */ | |
3617 | shift = 17; | |
3618 | do | |
beae10d5 KH |
3619 | { |
3620 | unsigned long himask, lomask; | |
3621 | ||
3622 | if (shift < 32) | |
3623 | { | |
3624 | himask = 0xffff >> (32 - shift); | |
3625 | lomask = (0xffff << shift) & 0xffffffff; | |
3626 | } | |
3627 | else | |
3628 | { | |
3629 | himask = 0xffff << (shift - 32); | |
3630 | lomask = 0; | |
3631 | } | |
3632 | if ((hi32.X_add_number & ~(offsetT) himask) == 0 | |
3633 | && (lo32.X_add_number & ~(offsetT) lomask) == 0) | |
3634 | { | |
3635 | expressionS tmp; | |
3636 | ||
3637 | tmp.X_op = O_constant; | |
3638 | if (shift < 32) | |
3639 | tmp.X_add_number = ((hi32.X_add_number << (32 - shift)) | |
3640 | | (lo32.X_add_number >> shift)); | |
3641 | else | |
3642 | tmp.X_add_number = hi32.X_add_number >> (shift - 32); | |
67c0d1eb RS |
3643 | macro_build (&tmp, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16); |
3644 | macro_build (NULL, (shift >= 32) ? "dsll32" : "dsll", "d,w,<", | |
3645 | reg, reg, (shift >= 32) ? shift - 32 : shift); | |
beae10d5 KH |
3646 | return; |
3647 | } | |
f9419b05 | 3648 | ++shift; |
beae10d5 KH |
3649 | } |
3650 | while (shift <= (64 - 16)); | |
252b5132 RH |
3651 | |
3652 | /* Find the bit number of the lowest one bit, and store the | |
3653 | shifted value in hi/lo. */ | |
3654 | hi = (unsigned long) (hi32.X_add_number & 0xffffffff); | |
3655 | lo = (unsigned long) (lo32.X_add_number & 0xffffffff); | |
3656 | if (lo != 0) | |
3657 | { | |
3658 | bit = 0; | |
3659 | while ((lo & 1) == 0) | |
3660 | { | |
3661 | lo >>= 1; | |
3662 | ++bit; | |
3663 | } | |
3664 | lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit); | |
3665 | hi >>= bit; | |
3666 | } | |
3667 | else | |
3668 | { | |
3669 | bit = 32; | |
3670 | while ((hi & 1) == 0) | |
3671 | { | |
3672 | hi >>= 1; | |
3673 | ++bit; | |
3674 | } | |
3675 | lo = hi; | |
3676 | hi = 0; | |
3677 | } | |
3678 | ||
3679 | /* Optimize if the shifted value is a (power of 2) - 1. */ | |
3680 | if ((hi == 0 && ((lo + 1) & lo) == 0) | |
3681 | || (lo == 0xffffffff && ((hi + 1) & hi) == 0)) | |
beae10d5 KH |
3682 | { |
3683 | shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number); | |
252b5132 | 3684 | if (shift != 0) |
beae10d5 | 3685 | { |
252b5132 RH |
3686 | expressionS tmp; |
3687 | ||
3688 | /* This instruction will set the register to be all | |
3689 | ones. */ | |
beae10d5 KH |
3690 | tmp.X_op = O_constant; |
3691 | tmp.X_add_number = (offsetT) -1; | |
67c0d1eb | 3692 | macro_build (&tmp, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
beae10d5 KH |
3693 | if (bit != 0) |
3694 | { | |
3695 | bit += shift; | |
67c0d1eb RS |
3696 | macro_build (NULL, (bit >= 32) ? "dsll32" : "dsll", "d,w,<", |
3697 | reg, reg, (bit >= 32) ? bit - 32 : bit); | |
beae10d5 | 3698 | } |
67c0d1eb RS |
3699 | macro_build (NULL, (shift >= 32) ? "dsrl32" : "dsrl", "d,w,<", |
3700 | reg, reg, (shift >= 32) ? shift - 32 : shift); | |
beae10d5 KH |
3701 | return; |
3702 | } | |
3703 | } | |
252b5132 RH |
3704 | |
3705 | /* Sign extend hi32 before calling load_register, because we can | |
3706 | generally get better code when we load a sign extended value. */ | |
3707 | if ((hi32.X_add_number & 0x80000000) != 0) | |
beae10d5 | 3708 | hi32.X_add_number |= ~(offsetT) 0xffffffff; |
67c0d1eb | 3709 | load_register (reg, &hi32, 0); |
252b5132 RH |
3710 | freg = reg; |
3711 | } | |
3712 | if ((lo32.X_add_number & 0xffff0000) == 0) | |
3713 | { | |
3714 | if (freg != 0) | |
3715 | { | |
67c0d1eb | 3716 | macro_build (NULL, "dsll32", "d,w,<", reg, freg, 0); |
252b5132 RH |
3717 | freg = reg; |
3718 | } | |
3719 | } | |
3720 | else | |
3721 | { | |
3722 | expressionS mid16; | |
3723 | ||
956cd1d6 | 3724 | if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff)) |
beae10d5 | 3725 | { |
67c0d1eb RS |
3726 | macro_build (&lo32, "lui", "t,u", reg, BFD_RELOC_HI16); |
3727 | macro_build (NULL, "dsrl32", "d,w,<", reg, reg, 0); | |
beae10d5 KH |
3728 | return; |
3729 | } | |
252b5132 RH |
3730 | |
3731 | if (freg != 0) | |
3732 | { | |
67c0d1eb | 3733 | macro_build (NULL, "dsll", "d,w,<", reg, freg, 16); |
252b5132 RH |
3734 | freg = reg; |
3735 | } | |
3736 | mid16 = lo32; | |
3737 | mid16.X_add_number >>= 16; | |
67c0d1eb RS |
3738 | macro_build (&mid16, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16); |
3739 | macro_build (NULL, "dsll", "d,w,<", reg, reg, 16); | |
252b5132 RH |
3740 | freg = reg; |
3741 | } | |
3742 | if ((lo32.X_add_number & 0xffff) != 0) | |
67c0d1eb | 3743 | macro_build (&lo32, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16); |
252b5132 RH |
3744 | } |
3745 | ||
269137b2 TS |
3746 | static inline void |
3747 | load_delay_nop (void) | |
3748 | { | |
3749 | if (!gpr_interlocks) | |
3750 | macro_build (NULL, "nop", ""); | |
3751 | } | |
3752 | ||
252b5132 RH |
3753 | /* Load an address into a register. */ |
3754 | ||
3755 | static void | |
67c0d1eb | 3756 | load_address (int reg, expressionS *ep, int *used_at) |
252b5132 | 3757 | { |
252b5132 RH |
3758 | if (ep->X_op != O_constant |
3759 | && ep->X_op != O_symbol) | |
3760 | { | |
3761 | as_bad (_("expression too complex")); | |
3762 | ep->X_op = O_constant; | |
3763 | } | |
3764 | ||
3765 | if (ep->X_op == O_constant) | |
3766 | { | |
67c0d1eb | 3767 | load_register (reg, ep, HAVE_64BIT_ADDRESSES); |
252b5132 RH |
3768 | return; |
3769 | } | |
3770 | ||
3771 | if (mips_pic == NO_PIC) | |
3772 | { | |
3773 | /* If this is a reference to a GP relative symbol, we want | |
cdf6fd85 | 3774 | addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
3775 | Otherwise we want |
3776 | lui $reg,<sym> (BFD_RELOC_HI16_S) | |
3777 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
d6bc6245 | 3778 | If we have an addend, we always use the latter form. |
76b3015f | 3779 | |
d6bc6245 TS |
3780 | With 64bit address space and a usable $at we want |
3781 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
3782 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
3783 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
3784 | daddiu $at,<sym> (BFD_RELOC_LO16) | |
3785 | dsll32 $reg,0 | |
3a482fd5 | 3786 | daddu $reg,$reg,$at |
76b3015f | 3787 | |
c03099e6 | 3788 | If $at is already in use, we use a path which is suboptimal |
d6bc6245 TS |
3789 | on superscalar processors. |
3790 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
3791 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
3792 | dsll $reg,16 | |
3793 | daddiu $reg,<sym> (BFD_RELOC_HI16_S) | |
3794 | dsll $reg,16 | |
3795 | daddiu $reg,<sym> (BFD_RELOC_LO16) | |
6caf9ef4 TS |
3796 | |
3797 | For GP relative symbols in 64bit address space we can use | |
3798 | the same sequence as in 32bit address space. */ | |
aed1a261 | 3799 | if (HAVE_64BIT_SYMBOLS) |
d6bc6245 | 3800 | { |
6caf9ef4 TS |
3801 | if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET |
3802 | && !nopic_need_relax (ep->X_add_symbol, 1)) | |
3803 | { | |
3804 | relax_start (ep->X_add_symbol); | |
3805 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, | |
3806 | mips_gp_register, BFD_RELOC_GPREL16); | |
3807 | relax_switch (); | |
3808 | } | |
d6bc6245 | 3809 | |
b8285c27 | 3810 | if (*used_at == 0 && !mips_opts.noat) |
d6bc6245 | 3811 | { |
67c0d1eb RS |
3812 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_HIGHEST); |
3813 | macro_build (ep, "lui", "t,u", AT, BFD_RELOC_HI16_S); | |
3814 | macro_build (ep, "daddiu", "t,r,j", reg, reg, | |
3815 | BFD_RELOC_MIPS_HIGHER); | |
3816 | macro_build (ep, "daddiu", "t,r,j", AT, AT, BFD_RELOC_LO16); | |
3817 | macro_build (NULL, "dsll32", "d,w,<", reg, reg, 0); | |
3818 | macro_build (NULL, "daddu", "d,v,t", reg, reg, AT); | |
d6bc6245 TS |
3819 | *used_at = 1; |
3820 | } | |
3821 | else | |
3822 | { | |
67c0d1eb RS |
3823 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_HIGHEST); |
3824 | macro_build (ep, "daddiu", "t,r,j", reg, reg, | |
3825 | BFD_RELOC_MIPS_HIGHER); | |
3826 | macro_build (NULL, "dsll", "d,w,<", reg, reg, 16); | |
3827 | macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_HI16_S); | |
3828 | macro_build (NULL, "dsll", "d,w,<", reg, reg, 16); | |
3829 | macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_LO16); | |
d6bc6245 | 3830 | } |
6caf9ef4 TS |
3831 | |
3832 | if (mips_relax.sequence) | |
3833 | relax_end (); | |
d6bc6245 | 3834 | } |
252b5132 RH |
3835 | else |
3836 | { | |
d6bc6245 | 3837 | if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 3838 | && !nopic_need_relax (ep->X_add_symbol, 1)) |
d6bc6245 | 3839 | { |
4d7206a2 | 3840 | relax_start (ep->X_add_symbol); |
67c0d1eb | 3841 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, |
17a2f251 | 3842 | mips_gp_register, BFD_RELOC_GPREL16); |
4d7206a2 | 3843 | relax_switch (); |
d6bc6245 | 3844 | } |
67c0d1eb RS |
3845 | macro_build_lui (ep, reg); |
3846 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", | |
3847 | reg, reg, BFD_RELOC_LO16); | |
4d7206a2 RS |
3848 | if (mips_relax.sequence) |
3849 | relax_end (); | |
d6bc6245 | 3850 | } |
252b5132 RH |
3851 | } |
3852 | else if (mips_pic == SVR4_PIC && ! mips_big_got) | |
3853 | { | |
3854 | expressionS ex; | |
3855 | ||
3856 | /* If this is a reference to an external symbol, we want | |
3857 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3858 | Otherwise we want | |
3859 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3860 | nop | |
3861 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
f5040a92 AO |
3862 | If there is a constant, it must be added in after. |
3863 | ||
ed6fb7bd | 3864 | If we have NewABI, we want |
f5040a92 AO |
3865 | lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP) |
3866 | unless we're referencing a global symbol with a non-zero | |
3867 | offset, in which case cst must be added separately. */ | |
ed6fb7bd SC |
3868 | if (HAVE_NEWABI) |
3869 | { | |
f5040a92 AO |
3870 | if (ep->X_add_number) |
3871 | { | |
4d7206a2 | 3872 | ex.X_add_number = ep->X_add_number; |
f5040a92 | 3873 | ep->X_add_number = 0; |
4d7206a2 | 3874 | relax_start (ep->X_add_symbol); |
67c0d1eb RS |
3875 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
3876 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
3877 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) |
3878 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
3879 | ex.X_op = O_constant; | |
67c0d1eb | 3880 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 3881 | reg, reg, BFD_RELOC_LO16); |
f5040a92 | 3882 | ep->X_add_number = ex.X_add_number; |
4d7206a2 | 3883 | relax_switch (); |
f5040a92 | 3884 | } |
67c0d1eb | 3885 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 3886 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); |
4d7206a2 RS |
3887 | if (mips_relax.sequence) |
3888 | relax_end (); | |
ed6fb7bd SC |
3889 | } |
3890 | else | |
3891 | { | |
f5040a92 AO |
3892 | ex.X_add_number = ep->X_add_number; |
3893 | ep->X_add_number = 0; | |
67c0d1eb RS |
3894 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
3895 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 3896 | load_delay_nop (); |
4d7206a2 RS |
3897 | relax_start (ep->X_add_symbol); |
3898 | relax_switch (); | |
67c0d1eb | 3899 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
17a2f251 | 3900 | BFD_RELOC_LO16); |
4d7206a2 | 3901 | relax_end (); |
ed6fb7bd | 3902 | |
f5040a92 AO |
3903 | if (ex.X_add_number != 0) |
3904 | { | |
3905 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
3906 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
3907 | ex.X_op = O_constant; | |
67c0d1eb | 3908 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 3909 | reg, reg, BFD_RELOC_LO16); |
f5040a92 | 3910 | } |
252b5132 RH |
3911 | } |
3912 | } | |
3913 | else if (mips_pic == SVR4_PIC) | |
3914 | { | |
3915 | expressionS ex; | |
252b5132 RH |
3916 | |
3917 | /* This is the large GOT case. If this is a reference to an | |
3918 | external symbol, we want | |
3919 | lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
3920 | addu $reg,$reg,$gp | |
3921 | lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16) | |
f5040a92 AO |
3922 | |
3923 | Otherwise, for a reference to a local symbol in old ABI, we want | |
252b5132 RH |
3924 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) |
3925 | nop | |
3926 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
684022ea | 3927 | If there is a constant, it must be added in after. |
f5040a92 AO |
3928 | |
3929 | In the NewABI, for local symbols, with or without offsets, we want: | |
438c16b8 TS |
3930 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) |
3931 | addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) | |
f5040a92 | 3932 | */ |
438c16b8 TS |
3933 | if (HAVE_NEWABI) |
3934 | { | |
4d7206a2 | 3935 | ex.X_add_number = ep->X_add_number; |
f5040a92 | 3936 | ep->X_add_number = 0; |
4d7206a2 | 3937 | relax_start (ep->X_add_symbol); |
67c0d1eb RS |
3938 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_GOT_HI16); |
3939 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
3940 | reg, reg, mips_gp_register); | |
3941 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", | |
3942 | reg, BFD_RELOC_MIPS_GOT_LO16, reg); | |
f5040a92 AO |
3943 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) |
3944 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
3945 | else if (ex.X_add_number) | |
3946 | { | |
3947 | ex.X_op = O_constant; | |
67c0d1eb RS |
3948 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
3949 | BFD_RELOC_LO16); | |
f5040a92 AO |
3950 | } |
3951 | ||
3952 | ep->X_add_number = ex.X_add_number; | |
4d7206a2 | 3953 | relax_switch (); |
67c0d1eb | 3954 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 3955 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); |
67c0d1eb RS |
3956 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
3957 | BFD_RELOC_MIPS_GOT_OFST); | |
4d7206a2 | 3958 | relax_end (); |
438c16b8 | 3959 | } |
252b5132 | 3960 | else |
438c16b8 | 3961 | { |
f5040a92 AO |
3962 | ex.X_add_number = ep->X_add_number; |
3963 | ep->X_add_number = 0; | |
4d7206a2 | 3964 | relax_start (ep->X_add_symbol); |
67c0d1eb RS |
3965 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_GOT_HI16); |
3966 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
3967 | reg, reg, mips_gp_register); | |
3968 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", | |
3969 | reg, BFD_RELOC_MIPS_GOT_LO16, reg); | |
4d7206a2 RS |
3970 | relax_switch (); |
3971 | if (reg_needs_delay (mips_gp_register)) | |
438c16b8 TS |
3972 | { |
3973 | /* We need a nop before loading from $gp. This special | |
3974 | check is required because the lui which starts the main | |
3975 | instruction stream does not refer to $gp, and so will not | |
3976 | insert the nop which may be required. */ | |
67c0d1eb | 3977 | macro_build (NULL, "nop", ""); |
438c16b8 | 3978 | } |
67c0d1eb | 3979 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 3980 | BFD_RELOC_MIPS_GOT16, mips_gp_register); |
269137b2 | 3981 | load_delay_nop (); |
67c0d1eb | 3982 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
17a2f251 | 3983 | BFD_RELOC_LO16); |
4d7206a2 | 3984 | relax_end (); |
438c16b8 | 3985 | |
f5040a92 AO |
3986 | if (ex.X_add_number != 0) |
3987 | { | |
3988 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
3989 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
3990 | ex.X_op = O_constant; | |
67c0d1eb RS |
3991 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
3992 | BFD_RELOC_LO16); | |
f5040a92 | 3993 | } |
252b5132 RH |
3994 | } |
3995 | } | |
252b5132 RH |
3996 | else |
3997 | abort (); | |
8fc2e39e TS |
3998 | |
3999 | if (mips_opts.noat && *used_at == 1) | |
4000 | as_bad (_("Macro used $at after \".set noat\"")); | |
252b5132 RH |
4001 | } |
4002 | ||
ea1fb5dc RS |
4003 | /* Move the contents of register SOURCE into register DEST. */ |
4004 | ||
4005 | static void | |
67c0d1eb | 4006 | move_register (int dest, int source) |
ea1fb5dc | 4007 | { |
67c0d1eb RS |
4008 | macro_build (NULL, HAVE_32BIT_GPRS ? "addu" : "daddu", "d,v,t", |
4009 | dest, source, 0); | |
ea1fb5dc RS |
4010 | } |
4011 | ||
4d7206a2 | 4012 | /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where |
f6a22291 MR |
4013 | LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement. |
4014 | The two alternatives are: | |
4d7206a2 RS |
4015 | |
4016 | Global symbol Local sybmol | |
4017 | ------------- ------------ | |
4018 | lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET) | |
4019 | ... ... | |
4020 | addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET) | |
4021 | ||
4022 | load_got_offset emits the first instruction and add_got_offset | |
f6a22291 MR |
4023 | emits the second for a 16-bit offset or add_got_offset_hilo emits |
4024 | a sequence to add a 32-bit offset using a scratch register. */ | |
4d7206a2 RS |
4025 | |
4026 | static void | |
67c0d1eb | 4027 | load_got_offset (int dest, expressionS *local) |
4d7206a2 RS |
4028 | { |
4029 | expressionS global; | |
4030 | ||
4031 | global = *local; | |
4032 | global.X_add_number = 0; | |
4033 | ||
4034 | relax_start (local->X_add_symbol); | |
67c0d1eb RS |
4035 | macro_build (&global, ADDRESS_LOAD_INSN, "t,o(b)", dest, |
4036 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
4d7206a2 | 4037 | relax_switch (); |
67c0d1eb RS |
4038 | macro_build (local, ADDRESS_LOAD_INSN, "t,o(b)", dest, |
4039 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
4d7206a2 RS |
4040 | relax_end (); |
4041 | } | |
4042 | ||
4043 | static void | |
67c0d1eb | 4044 | add_got_offset (int dest, expressionS *local) |
4d7206a2 RS |
4045 | { |
4046 | expressionS global; | |
4047 | ||
4048 | global.X_op = O_constant; | |
4049 | global.X_op_symbol = NULL; | |
4050 | global.X_add_symbol = NULL; | |
4051 | global.X_add_number = local->X_add_number; | |
4052 | ||
4053 | relax_start (local->X_add_symbol); | |
67c0d1eb | 4054 | macro_build (&global, ADDRESS_ADDI_INSN, "t,r,j", |
4d7206a2 RS |
4055 | dest, dest, BFD_RELOC_LO16); |
4056 | relax_switch (); | |
67c0d1eb | 4057 | macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", dest, dest, BFD_RELOC_LO16); |
4d7206a2 RS |
4058 | relax_end (); |
4059 | } | |
4060 | ||
f6a22291 MR |
4061 | static void |
4062 | add_got_offset_hilo (int dest, expressionS *local, int tmp) | |
4063 | { | |
4064 | expressionS global; | |
4065 | int hold_mips_optimize; | |
4066 | ||
4067 | global.X_op = O_constant; | |
4068 | global.X_op_symbol = NULL; | |
4069 | global.X_add_symbol = NULL; | |
4070 | global.X_add_number = local->X_add_number; | |
4071 | ||
4072 | relax_start (local->X_add_symbol); | |
4073 | load_register (tmp, &global, HAVE_64BIT_ADDRESSES); | |
4074 | relax_switch (); | |
4075 | /* Set mips_optimize around the lui instruction to avoid | |
4076 | inserting an unnecessary nop after the lw. */ | |
4077 | hold_mips_optimize = mips_optimize; | |
4078 | mips_optimize = 2; | |
4079 | macro_build_lui (&global, tmp); | |
4080 | mips_optimize = hold_mips_optimize; | |
4081 | macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", tmp, tmp, BFD_RELOC_LO16); | |
4082 | relax_end (); | |
4083 | ||
4084 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dest, dest, tmp); | |
4085 | } | |
4086 | ||
252b5132 RH |
4087 | /* |
4088 | * Build macros | |
4089 | * This routine implements the seemingly endless macro or synthesized | |
4090 | * instructions and addressing modes in the mips assembly language. Many | |
4091 | * of these macros are simple and are similar to each other. These could | |
67c1ffbe | 4092 | * probably be handled by some kind of table or grammar approach instead of |
252b5132 RH |
4093 | * this verbose method. Others are not simple macros but are more like |
4094 | * optimizing code generation. | |
4095 | * One interesting optimization is when several store macros appear | |
67c1ffbe | 4096 | * consecutively that would load AT with the upper half of the same address. |
252b5132 RH |
4097 | * The ensuing load upper instructions are ommited. This implies some kind |
4098 | * of global optimization. We currently only optimize within a single macro. | |
4099 | * For many of the load and store macros if the address is specified as a | |
4100 | * constant expression in the first 64k of memory (ie ld $2,0x4000c) we | |
4101 | * first load register 'at' with zero and use it as the base register. The | |
4102 | * mips assembler simply uses register $zero. Just one tiny optimization | |
4103 | * we're missing. | |
4104 | */ | |
4105 | static void | |
17a2f251 | 4106 | macro (struct mips_cl_insn *ip) |
252b5132 RH |
4107 | { |
4108 | register int treg, sreg, dreg, breg; | |
4109 | int tempreg; | |
4110 | int mask; | |
43841e91 | 4111 | int used_at = 0; |
252b5132 RH |
4112 | expressionS expr1; |
4113 | const char *s; | |
4114 | const char *s2; | |
4115 | const char *fmt; | |
4116 | int likely = 0; | |
4117 | int dbl = 0; | |
4118 | int coproc = 0; | |
4119 | int lr = 0; | |
4120 | int imm = 0; | |
1abe91b1 | 4121 | int call = 0; |
252b5132 | 4122 | int off; |
67c0d1eb | 4123 | offsetT maxnum; |
252b5132 | 4124 | bfd_reloc_code_real_type r; |
252b5132 RH |
4125 | int hold_mips_optimize; |
4126 | ||
4127 | assert (! mips_opts.mips16); | |
4128 | ||
4129 | treg = (ip->insn_opcode >> 16) & 0x1f; | |
4130 | dreg = (ip->insn_opcode >> 11) & 0x1f; | |
4131 | sreg = breg = (ip->insn_opcode >> 21) & 0x1f; | |
4132 | mask = ip->insn_mo->mask; | |
4133 | ||
4134 | expr1.X_op = O_constant; | |
4135 | expr1.X_op_symbol = NULL; | |
4136 | expr1.X_add_symbol = NULL; | |
4137 | expr1.X_add_number = 1; | |
4138 | ||
4139 | switch (mask) | |
4140 | { | |
4141 | case M_DABS: | |
4142 | dbl = 1; | |
4143 | case M_ABS: | |
4144 | /* bgez $a0,.+12 | |
4145 | move v0,$a0 | |
4146 | sub v0,$zero,$a0 | |
4147 | */ | |
4148 | ||
b34976b6 | 4149 | mips_emit_delays (TRUE); |
252b5132 RH |
4150 | ++mips_opts.noreorder; |
4151 | mips_any_noreorder = 1; | |
4152 | ||
4153 | expr1.X_add_number = 8; | |
67c0d1eb | 4154 | macro_build (&expr1, "bgez", "s,p", sreg); |
252b5132 | 4155 | if (dreg == sreg) |
67c0d1eb | 4156 | macro_build (NULL, "nop", "", 0); |
252b5132 | 4157 | else |
67c0d1eb RS |
4158 | move_register (dreg, sreg); |
4159 | macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, 0, sreg); | |
252b5132 RH |
4160 | |
4161 | --mips_opts.noreorder; | |
8fc2e39e | 4162 | break; |
252b5132 RH |
4163 | |
4164 | case M_ADD_I: | |
4165 | s = "addi"; | |
4166 | s2 = "add"; | |
4167 | goto do_addi; | |
4168 | case M_ADDU_I: | |
4169 | s = "addiu"; | |
4170 | s2 = "addu"; | |
4171 | goto do_addi; | |
4172 | case M_DADD_I: | |
4173 | dbl = 1; | |
4174 | s = "daddi"; | |
4175 | s2 = "dadd"; | |
4176 | goto do_addi; | |
4177 | case M_DADDU_I: | |
4178 | dbl = 1; | |
4179 | s = "daddiu"; | |
4180 | s2 = "daddu"; | |
4181 | do_addi: | |
4182 | if (imm_expr.X_op == O_constant | |
4183 | && imm_expr.X_add_number >= -0x8000 | |
4184 | && imm_expr.X_add_number < 0x8000) | |
4185 | { | |
67c0d1eb | 4186 | macro_build (&imm_expr, s, "t,r,j", treg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 4187 | break; |
252b5132 | 4188 | } |
8fc2e39e | 4189 | used_at = 1; |
67c0d1eb RS |
4190 | load_register (AT, &imm_expr, dbl); |
4191 | macro_build (NULL, s2, "d,v,t", treg, sreg, AT); | |
252b5132 RH |
4192 | break; |
4193 | ||
4194 | case M_AND_I: | |
4195 | s = "andi"; | |
4196 | s2 = "and"; | |
4197 | goto do_bit; | |
4198 | case M_OR_I: | |
4199 | s = "ori"; | |
4200 | s2 = "or"; | |
4201 | goto do_bit; | |
4202 | case M_NOR_I: | |
4203 | s = ""; | |
4204 | s2 = "nor"; | |
4205 | goto do_bit; | |
4206 | case M_XOR_I: | |
4207 | s = "xori"; | |
4208 | s2 = "xor"; | |
4209 | do_bit: | |
4210 | if (imm_expr.X_op == O_constant | |
4211 | && imm_expr.X_add_number >= 0 | |
4212 | && imm_expr.X_add_number < 0x10000) | |
4213 | { | |
4214 | if (mask != M_NOR_I) | |
67c0d1eb | 4215 | macro_build (&imm_expr, s, "t,r,i", treg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
4216 | else |
4217 | { | |
67c0d1eb RS |
4218 | macro_build (&imm_expr, "ori", "t,r,i", |
4219 | treg, sreg, BFD_RELOC_LO16); | |
4220 | macro_build (NULL, "nor", "d,v,t", treg, treg, 0); | |
252b5132 | 4221 | } |
8fc2e39e | 4222 | break; |
252b5132 RH |
4223 | } |
4224 | ||
8fc2e39e | 4225 | used_at = 1; |
67c0d1eb RS |
4226 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
4227 | macro_build (NULL, s2, "d,v,t", treg, sreg, AT); | |
252b5132 RH |
4228 | break; |
4229 | ||
4230 | case M_BEQ_I: | |
4231 | s = "beq"; | |
4232 | goto beq_i; | |
4233 | case M_BEQL_I: | |
4234 | s = "beql"; | |
4235 | likely = 1; | |
4236 | goto beq_i; | |
4237 | case M_BNE_I: | |
4238 | s = "bne"; | |
4239 | goto beq_i; | |
4240 | case M_BNEL_I: | |
4241 | s = "bnel"; | |
4242 | likely = 1; | |
4243 | beq_i: | |
4244 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4245 | { | |
67c0d1eb | 4246 | macro_build (&offset_expr, s, "s,t,p", sreg, 0); |
8fc2e39e | 4247 | break; |
252b5132 | 4248 | } |
8fc2e39e | 4249 | used_at = 1; |
67c0d1eb RS |
4250 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
4251 | macro_build (&offset_expr, s, "s,t,p", sreg, AT); | |
252b5132 RH |
4252 | break; |
4253 | ||
4254 | case M_BGEL: | |
4255 | likely = 1; | |
4256 | case M_BGE: | |
4257 | if (treg == 0) | |
4258 | { | |
67c0d1eb | 4259 | macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", sreg); |
8fc2e39e | 4260 | break; |
252b5132 RH |
4261 | } |
4262 | if (sreg == 0) | |
4263 | { | |
67c0d1eb | 4264 | macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", treg); |
8fc2e39e | 4265 | break; |
252b5132 | 4266 | } |
8fc2e39e | 4267 | used_at = 1; |
67c0d1eb RS |
4268 | macro_build (NULL, "slt", "d,v,t", AT, sreg, treg); |
4269 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
4270 | break; |
4271 | ||
4272 | case M_BGTL_I: | |
4273 | likely = 1; | |
4274 | case M_BGT_I: | |
4275 | /* check for > max integer */ | |
4276 | maxnum = 0x7fffffff; | |
ca4e0257 | 4277 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
4278 | { |
4279 | maxnum <<= 16; | |
4280 | maxnum |= 0xffff; | |
4281 | maxnum <<= 16; | |
4282 | maxnum |= 0xffff; | |
4283 | } | |
4284 | if (imm_expr.X_op == O_constant | |
4285 | && imm_expr.X_add_number >= maxnum | |
ca4e0257 | 4286 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
4287 | { |
4288 | do_false: | |
4289 | /* result is always false */ | |
4290 | if (! likely) | |
67c0d1eb | 4291 | macro_build (NULL, "nop", "", 0); |
252b5132 | 4292 | else |
67c0d1eb | 4293 | macro_build (&offset_expr, "bnel", "s,t,p", 0, 0); |
8fc2e39e | 4294 | break; |
252b5132 RH |
4295 | } |
4296 | if (imm_expr.X_op != O_constant) | |
4297 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 4298 | ++imm_expr.X_add_number; |
252b5132 RH |
4299 | /* FALLTHROUGH */ |
4300 | case M_BGE_I: | |
4301 | case M_BGEL_I: | |
4302 | if (mask == M_BGEL_I) | |
4303 | likely = 1; | |
4304 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4305 | { | |
67c0d1eb | 4306 | macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", sreg); |
8fc2e39e | 4307 | break; |
252b5132 RH |
4308 | } |
4309 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4310 | { | |
67c0d1eb | 4311 | macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", sreg); |
8fc2e39e | 4312 | break; |
252b5132 RH |
4313 | } |
4314 | maxnum = 0x7fffffff; | |
ca4e0257 | 4315 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
4316 | { |
4317 | maxnum <<= 16; | |
4318 | maxnum |= 0xffff; | |
4319 | maxnum <<= 16; | |
4320 | maxnum |= 0xffff; | |
4321 | } | |
4322 | maxnum = - maxnum - 1; | |
4323 | if (imm_expr.X_op == O_constant | |
4324 | && imm_expr.X_add_number <= maxnum | |
ca4e0257 | 4325 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
4326 | { |
4327 | do_true: | |
4328 | /* result is always true */ | |
4329 | as_warn (_("Branch %s is always true"), ip->insn_mo->name); | |
67c0d1eb | 4330 | macro_build (&offset_expr, "b", "p"); |
8fc2e39e | 4331 | break; |
252b5132 | 4332 | } |
8fc2e39e | 4333 | used_at = 1; |
67c0d1eb RS |
4334 | set_at (sreg, 0); |
4335 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
4336 | break; |
4337 | ||
4338 | case M_BGEUL: | |
4339 | likely = 1; | |
4340 | case M_BGEU: | |
4341 | if (treg == 0) | |
4342 | goto do_true; | |
4343 | if (sreg == 0) | |
4344 | { | |
67c0d1eb | 4345 | macro_build (&offset_expr, likely ? "beql" : "beq", |
17a2f251 | 4346 | "s,t,p", 0, treg); |
8fc2e39e | 4347 | break; |
252b5132 | 4348 | } |
8fc2e39e | 4349 | used_at = 1; |
67c0d1eb RS |
4350 | macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg); |
4351 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
4352 | break; |
4353 | ||
4354 | case M_BGTUL_I: | |
4355 | likely = 1; | |
4356 | case M_BGTU_I: | |
4357 | if (sreg == 0 | |
ca4e0257 | 4358 | || (HAVE_32BIT_GPRS |
252b5132 | 4359 | && imm_expr.X_op == O_constant |
956cd1d6 | 4360 | && imm_expr.X_add_number == (offsetT) 0xffffffff)) |
252b5132 RH |
4361 | goto do_false; |
4362 | if (imm_expr.X_op != O_constant) | |
4363 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 4364 | ++imm_expr.X_add_number; |
252b5132 RH |
4365 | /* FALLTHROUGH */ |
4366 | case M_BGEU_I: | |
4367 | case M_BGEUL_I: | |
4368 | if (mask == M_BGEUL_I) | |
4369 | likely = 1; | |
4370 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4371 | goto do_true; | |
4372 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4373 | { | |
67c0d1eb | 4374 | macro_build (&offset_expr, likely ? "bnel" : "bne", |
17a2f251 | 4375 | "s,t,p", sreg, 0); |
8fc2e39e | 4376 | break; |
252b5132 | 4377 | } |
8fc2e39e | 4378 | used_at = 1; |
67c0d1eb RS |
4379 | set_at (sreg, 1); |
4380 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
4381 | break; |
4382 | ||
4383 | case M_BGTL: | |
4384 | likely = 1; | |
4385 | case M_BGT: | |
4386 | if (treg == 0) | |
4387 | { | |
67c0d1eb | 4388 | macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", sreg); |
8fc2e39e | 4389 | break; |
252b5132 RH |
4390 | } |
4391 | if (sreg == 0) | |
4392 | { | |
67c0d1eb | 4393 | macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", treg); |
8fc2e39e | 4394 | break; |
252b5132 | 4395 | } |
8fc2e39e | 4396 | used_at = 1; |
67c0d1eb RS |
4397 | macro_build (NULL, "slt", "d,v,t", AT, treg, sreg); |
4398 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
4399 | break; |
4400 | ||
4401 | case M_BGTUL: | |
4402 | likely = 1; | |
4403 | case M_BGTU: | |
4404 | if (treg == 0) | |
4405 | { | |
67c0d1eb | 4406 | macro_build (&offset_expr, likely ? "bnel" : "bne", |
17a2f251 | 4407 | "s,t,p", sreg, 0); |
8fc2e39e | 4408 | break; |
252b5132 RH |
4409 | } |
4410 | if (sreg == 0) | |
4411 | goto do_false; | |
8fc2e39e | 4412 | used_at = 1; |
67c0d1eb RS |
4413 | macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg); |
4414 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
4415 | break; |
4416 | ||
4417 | case M_BLEL: | |
4418 | likely = 1; | |
4419 | case M_BLE: | |
4420 | if (treg == 0) | |
4421 | { | |
67c0d1eb | 4422 | macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", sreg); |
8fc2e39e | 4423 | break; |
252b5132 RH |
4424 | } |
4425 | if (sreg == 0) | |
4426 | { | |
67c0d1eb | 4427 | macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", treg); |
8fc2e39e | 4428 | break; |
252b5132 | 4429 | } |
8fc2e39e | 4430 | used_at = 1; |
67c0d1eb RS |
4431 | macro_build (NULL, "slt", "d,v,t", AT, treg, sreg); |
4432 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
4433 | break; |
4434 | ||
4435 | case M_BLEL_I: | |
4436 | likely = 1; | |
4437 | case M_BLE_I: | |
4438 | maxnum = 0x7fffffff; | |
ca4e0257 | 4439 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
4440 | { |
4441 | maxnum <<= 16; | |
4442 | maxnum |= 0xffff; | |
4443 | maxnum <<= 16; | |
4444 | maxnum |= 0xffff; | |
4445 | } | |
4446 | if (imm_expr.X_op == O_constant | |
4447 | && imm_expr.X_add_number >= maxnum | |
ca4e0257 | 4448 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
4449 | goto do_true; |
4450 | if (imm_expr.X_op != O_constant) | |
4451 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 4452 | ++imm_expr.X_add_number; |
252b5132 RH |
4453 | /* FALLTHROUGH */ |
4454 | case M_BLT_I: | |
4455 | case M_BLTL_I: | |
4456 | if (mask == M_BLTL_I) | |
4457 | likely = 1; | |
4458 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4459 | { | |
67c0d1eb | 4460 | macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", sreg); |
8fc2e39e | 4461 | break; |
252b5132 RH |
4462 | } |
4463 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4464 | { | |
67c0d1eb | 4465 | macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", sreg); |
8fc2e39e | 4466 | break; |
252b5132 | 4467 | } |
8fc2e39e | 4468 | used_at = 1; |
67c0d1eb RS |
4469 | set_at (sreg, 0); |
4470 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
4471 | break; |
4472 | ||
4473 | case M_BLEUL: | |
4474 | likely = 1; | |
4475 | case M_BLEU: | |
4476 | if (treg == 0) | |
4477 | { | |
67c0d1eb | 4478 | macro_build (&offset_expr, likely ? "beql" : "beq", |
17a2f251 | 4479 | "s,t,p", sreg, 0); |
8fc2e39e | 4480 | break; |
252b5132 RH |
4481 | } |
4482 | if (sreg == 0) | |
4483 | goto do_true; | |
8fc2e39e | 4484 | used_at = 1; |
67c0d1eb RS |
4485 | macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg); |
4486 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
4487 | break; |
4488 | ||
4489 | case M_BLEUL_I: | |
4490 | likely = 1; | |
4491 | case M_BLEU_I: | |
4492 | if (sreg == 0 | |
ca4e0257 | 4493 | || (HAVE_32BIT_GPRS |
252b5132 | 4494 | && imm_expr.X_op == O_constant |
956cd1d6 | 4495 | && imm_expr.X_add_number == (offsetT) 0xffffffff)) |
252b5132 RH |
4496 | goto do_true; |
4497 | if (imm_expr.X_op != O_constant) | |
4498 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 4499 | ++imm_expr.X_add_number; |
252b5132 RH |
4500 | /* FALLTHROUGH */ |
4501 | case M_BLTU_I: | |
4502 | case M_BLTUL_I: | |
4503 | if (mask == M_BLTUL_I) | |
4504 | likely = 1; | |
4505 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4506 | goto do_false; | |
4507 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4508 | { | |
67c0d1eb | 4509 | macro_build (&offset_expr, likely ? "beql" : "beq", |
252b5132 | 4510 | "s,t,p", sreg, 0); |
8fc2e39e | 4511 | break; |
252b5132 | 4512 | } |
8fc2e39e | 4513 | used_at = 1; |
67c0d1eb RS |
4514 | set_at (sreg, 1); |
4515 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
4516 | break; |
4517 | ||
4518 | case M_BLTL: | |
4519 | likely = 1; | |
4520 | case M_BLT: | |
4521 | if (treg == 0) | |
4522 | { | |
67c0d1eb | 4523 | macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", sreg); |
8fc2e39e | 4524 | break; |
252b5132 RH |
4525 | } |
4526 | if (sreg == 0) | |
4527 | { | |
67c0d1eb | 4528 | macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", treg); |
8fc2e39e | 4529 | break; |
252b5132 | 4530 | } |
8fc2e39e | 4531 | used_at = 1; |
67c0d1eb RS |
4532 | macro_build (NULL, "slt", "d,v,t", AT, sreg, treg); |
4533 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
4534 | break; |
4535 | ||
4536 | case M_BLTUL: | |
4537 | likely = 1; | |
4538 | case M_BLTU: | |
4539 | if (treg == 0) | |
4540 | goto do_false; | |
4541 | if (sreg == 0) | |
4542 | { | |
67c0d1eb | 4543 | macro_build (&offset_expr, likely ? "bnel" : "bne", |
17a2f251 | 4544 | "s,t,p", 0, treg); |
8fc2e39e | 4545 | break; |
252b5132 | 4546 | } |
8fc2e39e | 4547 | used_at = 1; |
67c0d1eb RS |
4548 | macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg); |
4549 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
4550 | break; |
4551 | ||
5f74bc13 CD |
4552 | case M_DEXT: |
4553 | { | |
4554 | unsigned long pos; | |
4555 | unsigned long size; | |
4556 | ||
4557 | if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant) | |
4558 | { | |
4559 | as_bad (_("Unsupported large constant")); | |
4560 | pos = size = 1; | |
4561 | } | |
4562 | else | |
4563 | { | |
4564 | pos = (unsigned long) imm_expr.X_add_number; | |
4565 | size = (unsigned long) imm2_expr.X_add_number; | |
4566 | } | |
4567 | ||
4568 | if (pos > 63) | |
4569 | { | |
4570 | as_bad (_("Improper position (%lu)"), pos); | |
4571 | pos = 1; | |
4572 | } | |
4573 | if (size == 0 || size > 64 | |
4574 | || (pos + size - 1) > 63) | |
4575 | { | |
4576 | as_bad (_("Improper extract size (%lu, position %lu)"), | |
4577 | size, pos); | |
4578 | size = 1; | |
4579 | } | |
4580 | ||
4581 | if (size <= 32 && pos < 32) | |
4582 | { | |
4583 | s = "dext"; | |
4584 | fmt = "t,r,+A,+C"; | |
4585 | } | |
4586 | else if (size <= 32) | |
4587 | { | |
4588 | s = "dextu"; | |
4589 | fmt = "t,r,+E,+H"; | |
4590 | } | |
4591 | else | |
4592 | { | |
4593 | s = "dextm"; | |
4594 | fmt = "t,r,+A,+G"; | |
4595 | } | |
67c0d1eb | 4596 | macro_build ((expressionS *) NULL, s, fmt, treg, sreg, pos, size - 1); |
5f74bc13 | 4597 | } |
8fc2e39e | 4598 | break; |
5f74bc13 CD |
4599 | |
4600 | case M_DINS: | |
4601 | { | |
4602 | unsigned long pos; | |
4603 | unsigned long size; | |
4604 | ||
4605 | if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant) | |
4606 | { | |
4607 | as_bad (_("Unsupported large constant")); | |
4608 | pos = size = 1; | |
4609 | } | |
4610 | else | |
4611 | { | |
4612 | pos = (unsigned long) imm_expr.X_add_number; | |
4613 | size = (unsigned long) imm2_expr.X_add_number; | |
4614 | } | |
4615 | ||
4616 | if (pos > 63) | |
4617 | { | |
4618 | as_bad (_("Improper position (%lu)"), pos); | |
4619 | pos = 1; | |
4620 | } | |
4621 | if (size == 0 || size > 64 | |
4622 | || (pos + size - 1) > 63) | |
4623 | { | |
4624 | as_bad (_("Improper insert size (%lu, position %lu)"), | |
4625 | size, pos); | |
4626 | size = 1; | |
4627 | } | |
4628 | ||
4629 | if (pos < 32 && (pos + size - 1) < 32) | |
4630 | { | |
4631 | s = "dins"; | |
4632 | fmt = "t,r,+A,+B"; | |
4633 | } | |
4634 | else if (pos >= 32) | |
4635 | { | |
4636 | s = "dinsu"; | |
4637 | fmt = "t,r,+E,+F"; | |
4638 | } | |
4639 | else | |
4640 | { | |
4641 | s = "dinsm"; | |
4642 | fmt = "t,r,+A,+F"; | |
4643 | } | |
67c0d1eb RS |
4644 | macro_build ((expressionS *) NULL, s, fmt, treg, sreg, pos, |
4645 | pos + size - 1); | |
5f74bc13 | 4646 | } |
8fc2e39e | 4647 | break; |
5f74bc13 | 4648 | |
252b5132 RH |
4649 | case M_DDIV_3: |
4650 | dbl = 1; | |
4651 | case M_DIV_3: | |
4652 | s = "mflo"; | |
4653 | goto do_div3; | |
4654 | case M_DREM_3: | |
4655 | dbl = 1; | |
4656 | case M_REM_3: | |
4657 | s = "mfhi"; | |
4658 | do_div3: | |
4659 | if (treg == 0) | |
4660 | { | |
4661 | as_warn (_("Divide by zero.")); | |
4662 | if (mips_trap) | |
67c0d1eb | 4663 | macro_build (NULL, "teq", "s,t,q", 0, 0, 7); |
252b5132 | 4664 | else |
67c0d1eb | 4665 | macro_build (NULL, "break", "c", 7); |
8fc2e39e | 4666 | break; |
252b5132 RH |
4667 | } |
4668 | ||
b34976b6 | 4669 | mips_emit_delays (TRUE); |
252b5132 RH |
4670 | ++mips_opts.noreorder; |
4671 | mips_any_noreorder = 1; | |
4672 | if (mips_trap) | |
4673 | { | |
67c0d1eb RS |
4674 | macro_build (NULL, "teq", "s,t,q", treg, 0, 7); |
4675 | macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg); | |
252b5132 RH |
4676 | } |
4677 | else | |
4678 | { | |
4679 | expr1.X_add_number = 8; | |
67c0d1eb RS |
4680 | macro_build (&expr1, "bne", "s,t,p", treg, 0); |
4681 | macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg); | |
4682 | macro_build (NULL, "break", "c", 7); | |
252b5132 RH |
4683 | } |
4684 | expr1.X_add_number = -1; | |
8fc2e39e | 4685 | used_at = 1; |
f6a22291 | 4686 | load_register (AT, &expr1, dbl); |
252b5132 | 4687 | expr1.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16); |
67c0d1eb | 4688 | macro_build (&expr1, "bne", "s,t,p", treg, AT); |
252b5132 RH |
4689 | if (dbl) |
4690 | { | |
4691 | expr1.X_add_number = 1; | |
f6a22291 | 4692 | load_register (AT, &expr1, dbl); |
67c0d1eb | 4693 | macro_build (NULL, "dsll32", "d,w,<", AT, AT, 31); |
252b5132 RH |
4694 | } |
4695 | else | |
4696 | { | |
4697 | expr1.X_add_number = 0x80000000; | |
67c0d1eb | 4698 | macro_build (&expr1, "lui", "t,u", AT, BFD_RELOC_HI16); |
252b5132 RH |
4699 | } |
4700 | if (mips_trap) | |
4701 | { | |
67c0d1eb | 4702 | macro_build (NULL, "teq", "s,t,q", sreg, AT, 6); |
252b5132 RH |
4703 | /* We want to close the noreorder block as soon as possible, so |
4704 | that later insns are available for delay slot filling. */ | |
4705 | --mips_opts.noreorder; | |
4706 | } | |
4707 | else | |
4708 | { | |
4709 | expr1.X_add_number = 8; | |
67c0d1eb RS |
4710 | macro_build (&expr1, "bne", "s,t,p", sreg, AT); |
4711 | macro_build (NULL, "nop", "", 0); | |
252b5132 RH |
4712 | |
4713 | /* We want to close the noreorder block as soon as possible, so | |
4714 | that later insns are available for delay slot filling. */ | |
4715 | --mips_opts.noreorder; | |
4716 | ||
67c0d1eb | 4717 | macro_build (NULL, "break", "c", 6); |
252b5132 | 4718 | } |
67c0d1eb | 4719 | macro_build (NULL, s, "d", dreg); |
252b5132 RH |
4720 | break; |
4721 | ||
4722 | case M_DIV_3I: | |
4723 | s = "div"; | |
4724 | s2 = "mflo"; | |
4725 | goto do_divi; | |
4726 | case M_DIVU_3I: | |
4727 | s = "divu"; | |
4728 | s2 = "mflo"; | |
4729 | goto do_divi; | |
4730 | case M_REM_3I: | |
4731 | s = "div"; | |
4732 | s2 = "mfhi"; | |
4733 | goto do_divi; | |
4734 | case M_REMU_3I: | |
4735 | s = "divu"; | |
4736 | s2 = "mfhi"; | |
4737 | goto do_divi; | |
4738 | case M_DDIV_3I: | |
4739 | dbl = 1; | |
4740 | s = "ddiv"; | |
4741 | s2 = "mflo"; | |
4742 | goto do_divi; | |
4743 | case M_DDIVU_3I: | |
4744 | dbl = 1; | |
4745 | s = "ddivu"; | |
4746 | s2 = "mflo"; | |
4747 | goto do_divi; | |
4748 | case M_DREM_3I: | |
4749 | dbl = 1; | |
4750 | s = "ddiv"; | |
4751 | s2 = "mfhi"; | |
4752 | goto do_divi; | |
4753 | case M_DREMU_3I: | |
4754 | dbl = 1; | |
4755 | s = "ddivu"; | |
4756 | s2 = "mfhi"; | |
4757 | do_divi: | |
4758 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4759 | { | |
4760 | as_warn (_("Divide by zero.")); | |
4761 | if (mips_trap) | |
67c0d1eb | 4762 | macro_build (NULL, "teq", "s,t,q", 0, 0, 7); |
252b5132 | 4763 | else |
67c0d1eb | 4764 | macro_build (NULL, "break", "c", 7); |
8fc2e39e | 4765 | break; |
252b5132 RH |
4766 | } |
4767 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4768 | { | |
4769 | if (strcmp (s2, "mflo") == 0) | |
67c0d1eb | 4770 | move_register (dreg, sreg); |
252b5132 | 4771 | else |
67c0d1eb | 4772 | move_register (dreg, 0); |
8fc2e39e | 4773 | break; |
252b5132 RH |
4774 | } |
4775 | if (imm_expr.X_op == O_constant | |
4776 | && imm_expr.X_add_number == -1 | |
4777 | && s[strlen (s) - 1] != 'u') | |
4778 | { | |
4779 | if (strcmp (s2, "mflo") == 0) | |
4780 | { | |
67c0d1eb | 4781 | macro_build (NULL, dbl ? "dneg" : "neg", "d,w", dreg, sreg); |
252b5132 RH |
4782 | } |
4783 | else | |
67c0d1eb | 4784 | move_register (dreg, 0); |
8fc2e39e | 4785 | break; |
252b5132 RH |
4786 | } |
4787 | ||
8fc2e39e | 4788 | used_at = 1; |
67c0d1eb RS |
4789 | load_register (AT, &imm_expr, dbl); |
4790 | macro_build (NULL, s, "z,s,t", sreg, AT); | |
4791 | macro_build (NULL, s2, "d", dreg); | |
252b5132 RH |
4792 | break; |
4793 | ||
4794 | case M_DIVU_3: | |
4795 | s = "divu"; | |
4796 | s2 = "mflo"; | |
4797 | goto do_divu3; | |
4798 | case M_REMU_3: | |
4799 | s = "divu"; | |
4800 | s2 = "mfhi"; | |
4801 | goto do_divu3; | |
4802 | case M_DDIVU_3: | |
4803 | s = "ddivu"; | |
4804 | s2 = "mflo"; | |
4805 | goto do_divu3; | |
4806 | case M_DREMU_3: | |
4807 | s = "ddivu"; | |
4808 | s2 = "mfhi"; | |
4809 | do_divu3: | |
b34976b6 | 4810 | mips_emit_delays (TRUE); |
252b5132 RH |
4811 | ++mips_opts.noreorder; |
4812 | mips_any_noreorder = 1; | |
4813 | if (mips_trap) | |
4814 | { | |
67c0d1eb RS |
4815 | macro_build (NULL, "teq", "s,t,q", treg, 0, 7); |
4816 | macro_build (NULL, s, "z,s,t", sreg, treg); | |
252b5132 RH |
4817 | /* We want to close the noreorder block as soon as possible, so |
4818 | that later insns are available for delay slot filling. */ | |
4819 | --mips_opts.noreorder; | |
4820 | } | |
4821 | else | |
4822 | { | |
4823 | expr1.X_add_number = 8; | |
67c0d1eb RS |
4824 | macro_build (&expr1, "bne", "s,t,p", treg, 0); |
4825 | macro_build (NULL, s, "z,s,t", sreg, treg); | |
252b5132 RH |
4826 | |
4827 | /* We want to close the noreorder block as soon as possible, so | |
4828 | that later insns are available for delay slot filling. */ | |
4829 | --mips_opts.noreorder; | |
67c0d1eb | 4830 | macro_build (NULL, "break", "c", 7); |
252b5132 | 4831 | } |
67c0d1eb | 4832 | macro_build (NULL, s2, "d", dreg); |
8fc2e39e | 4833 | break; |
252b5132 | 4834 | |
1abe91b1 MR |
4835 | case M_DLCA_AB: |
4836 | dbl = 1; | |
4837 | case M_LCA_AB: | |
4838 | call = 1; | |
4839 | goto do_la; | |
252b5132 RH |
4840 | case M_DLA_AB: |
4841 | dbl = 1; | |
4842 | case M_LA_AB: | |
1abe91b1 | 4843 | do_la: |
252b5132 RH |
4844 | /* Load the address of a symbol into a register. If breg is not |
4845 | zero, we then add a base register to it. */ | |
4846 | ||
3bec30a8 TS |
4847 | if (dbl && HAVE_32BIT_GPRS) |
4848 | as_warn (_("dla used to load 32-bit register")); | |
4849 | ||
c90bbe5b | 4850 | if (! dbl && HAVE_64BIT_OBJECTS) |
3bec30a8 TS |
4851 | as_warn (_("la used to load 64-bit address")); |
4852 | ||
0c11417f MR |
4853 | if (offset_expr.X_op == O_constant |
4854 | && offset_expr.X_add_number >= -0x8000 | |
4855 | && offset_expr.X_add_number < 0x8000) | |
4856 | { | |
aed1a261 | 4857 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, |
17a2f251 | 4858 | "t,r,j", treg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 4859 | break; |
0c11417f MR |
4860 | } |
4861 | ||
b8285c27 | 4862 | if (!mips_opts.noat && (treg == breg)) |
afdbd6d0 CD |
4863 | { |
4864 | tempreg = AT; | |
4865 | used_at = 1; | |
4866 | } | |
4867 | else | |
4868 | { | |
4869 | tempreg = treg; | |
afdbd6d0 CD |
4870 | } |
4871 | ||
252b5132 RH |
4872 | if (offset_expr.X_op != O_symbol |
4873 | && offset_expr.X_op != O_constant) | |
4874 | { | |
4875 | as_bad (_("expression too complex")); | |
4876 | offset_expr.X_op = O_constant; | |
4877 | } | |
4878 | ||
252b5132 | 4879 | if (offset_expr.X_op == O_constant) |
aed1a261 | 4880 | load_register (tempreg, &offset_expr, HAVE_64BIT_ADDRESSES); |
252b5132 RH |
4881 | else if (mips_pic == NO_PIC) |
4882 | { | |
d6bc6245 | 4883 | /* If this is a reference to a GP relative symbol, we want |
cdf6fd85 | 4884 | addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
4885 | Otherwise we want |
4886 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
4887 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
4888 | If we have a constant, we need two instructions anyhow, | |
d6bc6245 | 4889 | so we may as well always use the latter form. |
76b3015f | 4890 | |
6caf9ef4 TS |
4891 | With 64bit address space and a usable $at we want |
4892 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
4893 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
4894 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
4895 | daddiu $at,<sym> (BFD_RELOC_LO16) | |
4896 | dsll32 $tempreg,0 | |
4897 | daddu $tempreg,$tempreg,$at | |
4898 | ||
4899 | If $at is already in use, we use a path which is suboptimal | |
4900 | on superscalar processors. | |
4901 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
4902 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
4903 | dsll $tempreg,16 | |
4904 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
4905 | dsll $tempreg,16 | |
4906 | daddiu $tempreg,<sym> (BFD_RELOC_LO16) | |
4907 | ||
4908 | For GP relative symbols in 64bit address space we can use | |
4909 | the same sequence as in 32bit address space. */ | |
aed1a261 | 4910 | if (HAVE_64BIT_SYMBOLS) |
252b5132 | 4911 | { |
6caf9ef4 TS |
4912 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
4913 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) | |
4914 | { | |
4915 | relax_start (offset_expr.X_add_symbol); | |
4916 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
4917 | tempreg, mips_gp_register, BFD_RELOC_GPREL16); | |
4918 | relax_switch (); | |
4919 | } | |
d6bc6245 | 4920 | |
b8285c27 | 4921 | if (used_at == 0 && !mips_opts.noat) |
98d3f06f | 4922 | { |
67c0d1eb | 4923 | macro_build (&offset_expr, "lui", "t,u", |
17a2f251 | 4924 | tempreg, BFD_RELOC_MIPS_HIGHEST); |
67c0d1eb | 4925 | macro_build (&offset_expr, "lui", "t,u", |
17a2f251 | 4926 | AT, BFD_RELOC_HI16_S); |
67c0d1eb | 4927 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 4928 | tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); |
67c0d1eb | 4929 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 4930 | AT, AT, BFD_RELOC_LO16); |
67c0d1eb RS |
4931 | macro_build (NULL, "dsll32", "d,w,<", tempreg, tempreg, 0); |
4932 | macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT); | |
98d3f06f KH |
4933 | used_at = 1; |
4934 | } | |
4935 | else | |
4936 | { | |
67c0d1eb | 4937 | macro_build (&offset_expr, "lui", "t,u", |
17a2f251 | 4938 | tempreg, BFD_RELOC_MIPS_HIGHEST); |
67c0d1eb | 4939 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 4940 | tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); |
67c0d1eb RS |
4941 | macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16); |
4942 | macro_build (&offset_expr, "daddiu", "t,r,j", | |
17a2f251 | 4943 | tempreg, tempreg, BFD_RELOC_HI16_S); |
67c0d1eb RS |
4944 | macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16); |
4945 | macro_build (&offset_expr, "daddiu", "t,r,j", | |
17a2f251 | 4946 | tempreg, tempreg, BFD_RELOC_LO16); |
98d3f06f | 4947 | } |
6caf9ef4 TS |
4948 | |
4949 | if (mips_relax.sequence) | |
4950 | relax_end (); | |
98d3f06f KH |
4951 | } |
4952 | else | |
4953 | { | |
4954 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET | |
6caf9ef4 | 4955 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
98d3f06f | 4956 | { |
4d7206a2 | 4957 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
4958 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
4959 | tempreg, mips_gp_register, BFD_RELOC_GPREL16); | |
4d7206a2 | 4960 | relax_switch (); |
98d3f06f | 4961 | } |
6943caf0 ILT |
4962 | if (!IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) |
4963 | as_bad (_("offset too large")); | |
67c0d1eb RS |
4964 | macro_build_lui (&offset_expr, tempreg); |
4965 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
4966 | tempreg, tempreg, BFD_RELOC_LO16); | |
4d7206a2 RS |
4967 | if (mips_relax.sequence) |
4968 | relax_end (); | |
98d3f06f | 4969 | } |
252b5132 | 4970 | } |
f5040a92 | 4971 | else if (mips_pic == SVR4_PIC && ! mips_big_got && ! HAVE_NEWABI) |
252b5132 | 4972 | { |
9117d219 NC |
4973 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
4974 | ||
252b5132 RH |
4975 | /* If this is a reference to an external symbol, and there |
4976 | is no constant, we want | |
4977 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
1abe91b1 | 4978 | or for lca or if tempreg is PIC_CALL_REG |
9117d219 | 4979 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
252b5132 RH |
4980 | For a local symbol, we want |
4981 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4982 | nop | |
4983 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
4984 | ||
4985 | If we have a small constant, and this is a reference to | |
4986 | an external symbol, we want | |
4987 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4988 | nop | |
4989 | addiu $tempreg,$tempreg,<constant> | |
4990 | For a local symbol, we want the same instruction | |
4991 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
4992 | addiu instruction. | |
4993 | ||
4994 | If we have a large constant, and this is a reference to | |
4995 | an external symbol, we want | |
4996 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4997 | lui $at,<hiconstant> | |
4998 | addiu $at,$at,<loconstant> | |
4999 | addu $tempreg,$tempreg,$at | |
5000 | For a local symbol, we want the same instruction | |
5001 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
ed6fb7bd | 5002 | addiu instruction. |
ed6fb7bd SC |
5003 | */ |
5004 | ||
4d7206a2 | 5005 | if (offset_expr.X_add_number == 0) |
252b5132 | 5006 | { |
4d7206a2 RS |
5007 | if (breg == 0 && (call || tempreg == PIC_CALL_REG)) |
5008 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16; | |
5009 | ||
5010 | relax_start (offset_expr.X_add_symbol); | |
67c0d1eb RS |
5011 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5012 | lw_reloc_type, mips_gp_register); | |
4d7206a2 | 5013 | if (breg != 0) |
252b5132 RH |
5014 | { |
5015 | /* We're going to put in an addu instruction using | |
5016 | tempreg, so we may as well insert the nop right | |
5017 | now. */ | |
269137b2 | 5018 | load_delay_nop (); |
252b5132 | 5019 | } |
4d7206a2 | 5020 | relax_switch (); |
67c0d1eb RS |
5021 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5022 | tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 5023 | load_delay_nop (); |
67c0d1eb RS |
5024 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
5025 | tempreg, tempreg, BFD_RELOC_LO16); | |
4d7206a2 | 5026 | relax_end (); |
252b5132 RH |
5027 | /* FIXME: If breg == 0, and the next instruction uses |
5028 | $tempreg, then if this variant case is used an extra | |
5029 | nop will be generated. */ | |
5030 | } | |
4d7206a2 RS |
5031 | else if (offset_expr.X_add_number >= -0x8000 |
5032 | && offset_expr.X_add_number < 0x8000) | |
252b5132 | 5033 | { |
67c0d1eb | 5034 | load_got_offset (tempreg, &offset_expr); |
269137b2 | 5035 | load_delay_nop (); |
67c0d1eb | 5036 | add_got_offset (tempreg, &offset_expr); |
252b5132 RH |
5037 | } |
5038 | else | |
5039 | { | |
4d7206a2 RS |
5040 | expr1.X_add_number = offset_expr.X_add_number; |
5041 | offset_expr.X_add_number = | |
5042 | ((offset_expr.X_add_number + 0x8000) & 0xffff) - 0x8000; | |
67c0d1eb | 5043 | load_got_offset (tempreg, &offset_expr); |
f6a22291 | 5044 | offset_expr.X_add_number = expr1.X_add_number; |
252b5132 RH |
5045 | /* If we are going to add in a base register, and the |
5046 | target register and the base register are the same, | |
5047 | then we are using AT as a temporary register. Since | |
5048 | we want to load the constant into AT, we add our | |
5049 | current AT (from the global offset table) and the | |
5050 | register into the register now, and pretend we were | |
5051 | not using a base register. */ | |
67c0d1eb | 5052 | if (breg == treg) |
252b5132 | 5053 | { |
269137b2 | 5054 | load_delay_nop (); |
67c0d1eb | 5055 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5056 | treg, AT, breg); |
252b5132 RH |
5057 | breg = 0; |
5058 | tempreg = treg; | |
252b5132 | 5059 | } |
f6a22291 | 5060 | add_got_offset_hilo (tempreg, &offset_expr, AT); |
252b5132 RH |
5061 | used_at = 1; |
5062 | } | |
5063 | } | |
f5040a92 AO |
5064 | else if (mips_pic == SVR4_PIC && ! mips_big_got && HAVE_NEWABI) |
5065 | { | |
67c0d1eb | 5066 | int add_breg_early = 0; |
f5040a92 AO |
5067 | |
5068 | /* If this is a reference to an external, and there is no | |
5069 | constant, or local symbol (*), with or without a | |
5070 | constant, we want | |
5071 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
1abe91b1 | 5072 | or for lca or if tempreg is PIC_CALL_REG |
f5040a92 AO |
5073 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
5074 | ||
5075 | If we have a small constant, and this is a reference to | |
5076 | an external symbol, we want | |
5077 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
5078 | addiu $tempreg,$tempreg,<constant> | |
5079 | ||
5080 | If we have a large constant, and this is a reference to | |
5081 | an external symbol, we want | |
5082 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
5083 | lui $at,<hiconstant> | |
5084 | addiu $at,$at,<loconstant> | |
5085 | addu $tempreg,$tempreg,$at | |
5086 | ||
5087 | (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for | |
5088 | local symbols, even though it introduces an additional | |
5089 | instruction. */ | |
5090 | ||
f5040a92 AO |
5091 | if (offset_expr.X_add_number) |
5092 | { | |
4d7206a2 | 5093 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
5094 | offset_expr.X_add_number = 0; |
5095 | ||
4d7206a2 | 5096 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
5097 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5098 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
5099 | |
5100 | if (expr1.X_add_number >= -0x8000 | |
5101 | && expr1.X_add_number < 0x8000) | |
5102 | { | |
67c0d1eb RS |
5103 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
5104 | tempreg, tempreg, BFD_RELOC_LO16); | |
f5040a92 | 5105 | } |
ecd13cd3 | 5106 | else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000)) |
f5040a92 AO |
5107 | { |
5108 | int dreg; | |
5109 | ||
5110 | /* If we are going to add in a base register, and the | |
5111 | target register and the base register are the same, | |
5112 | then we are using AT as a temporary register. Since | |
5113 | we want to load the constant into AT, we add our | |
5114 | current AT (from the global offset table) and the | |
5115 | register into the register now, and pretend we were | |
5116 | not using a base register. */ | |
5117 | if (breg != treg) | |
5118 | dreg = tempreg; | |
5119 | else | |
5120 | { | |
5121 | assert (tempreg == AT); | |
67c0d1eb RS |
5122 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
5123 | treg, AT, breg); | |
f5040a92 | 5124 | dreg = treg; |
67c0d1eb | 5125 | add_breg_early = 1; |
f5040a92 AO |
5126 | } |
5127 | ||
f6a22291 | 5128 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 5129 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5130 | dreg, dreg, AT); |
f5040a92 | 5131 | |
f5040a92 AO |
5132 | used_at = 1; |
5133 | } | |
5134 | else | |
5135 | as_bad (_("PIC code offset overflow (max 32 signed bits)")); | |
5136 | ||
4d7206a2 | 5137 | relax_switch (); |
f5040a92 AO |
5138 | offset_expr.X_add_number = expr1.X_add_number; |
5139 | ||
67c0d1eb RS |
5140 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5141 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
5142 | if (add_breg_early) | |
f5040a92 | 5143 | { |
67c0d1eb | 5144 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
f899b4b8 | 5145 | treg, tempreg, breg); |
f5040a92 AO |
5146 | breg = 0; |
5147 | tempreg = treg; | |
5148 | } | |
4d7206a2 | 5149 | relax_end (); |
f5040a92 | 5150 | } |
4d7206a2 | 5151 | else if (breg == 0 && (call || tempreg == PIC_CALL_REG)) |
f5040a92 | 5152 | { |
4d7206a2 | 5153 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
5154 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5155 | BFD_RELOC_MIPS_CALL16, mips_gp_register); | |
4d7206a2 | 5156 | relax_switch (); |
67c0d1eb RS |
5157 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5158 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
4d7206a2 | 5159 | relax_end (); |
f5040a92 | 5160 | } |
4d7206a2 | 5161 | else |
f5040a92 | 5162 | { |
67c0d1eb RS |
5163 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5164 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
5165 | } |
5166 | } | |
5167 | else if (mips_pic == SVR4_PIC && ! HAVE_NEWABI) | |
252b5132 | 5168 | { |
67c0d1eb | 5169 | int gpdelay; |
9117d219 NC |
5170 | int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; |
5171 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; | |
ed6fb7bd | 5172 | int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
252b5132 RH |
5173 | |
5174 | /* This is the large GOT case. If this is a reference to an | |
5175 | external symbol, and there is no constant, we want | |
5176 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5177 | addu $tempreg,$tempreg,$gp | |
5178 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
1abe91b1 | 5179 | or for lca or if tempreg is PIC_CALL_REG |
9117d219 NC |
5180 | lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) |
5181 | addu $tempreg,$tempreg,$gp | |
5182 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) | |
252b5132 RH |
5183 | For a local symbol, we want |
5184 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5185 | nop | |
5186 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
5187 | ||
5188 | If we have a small constant, and this is a reference to | |
5189 | an external symbol, we want | |
5190 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5191 | addu $tempreg,$tempreg,$gp | |
5192 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5193 | nop | |
5194 | addiu $tempreg,$tempreg,<constant> | |
5195 | For a local symbol, we want | |
5196 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5197 | nop | |
5198 | addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16) | |
5199 | ||
5200 | If we have a large constant, and this is a reference to | |
5201 | an external symbol, we want | |
5202 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5203 | addu $tempreg,$tempreg,$gp | |
5204 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5205 | lui $at,<hiconstant> | |
5206 | addiu $at,$at,<loconstant> | |
5207 | addu $tempreg,$tempreg,$at | |
5208 | For a local symbol, we want | |
5209 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5210 | lui $at,<hiconstant> | |
5211 | addiu $at,$at,<loconstant> (BFD_RELOC_LO16) | |
5212 | addu $tempreg,$tempreg,$at | |
f5040a92 | 5213 | */ |
438c16b8 | 5214 | |
252b5132 RH |
5215 | expr1.X_add_number = offset_expr.X_add_number; |
5216 | offset_expr.X_add_number = 0; | |
4d7206a2 | 5217 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 5218 | gpdelay = reg_needs_delay (mips_gp_register); |
1abe91b1 MR |
5219 | if (expr1.X_add_number == 0 && breg == 0 |
5220 | && (call || tempreg == PIC_CALL_REG)) | |
9117d219 NC |
5221 | { |
5222 | lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; | |
5223 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; | |
5224 | } | |
67c0d1eb RS |
5225 | macro_build (&offset_expr, "lui", "t,u", tempreg, lui_reloc_type); |
5226 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 5227 | tempreg, tempreg, mips_gp_register); |
67c0d1eb | 5228 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
17a2f251 | 5229 | tempreg, lw_reloc_type, tempreg); |
252b5132 RH |
5230 | if (expr1.X_add_number == 0) |
5231 | { | |
67c0d1eb | 5232 | if (breg != 0) |
252b5132 RH |
5233 | { |
5234 | /* We're going to put in an addu instruction using | |
5235 | tempreg, so we may as well insert the nop right | |
5236 | now. */ | |
269137b2 | 5237 | load_delay_nop (); |
252b5132 | 5238 | } |
252b5132 RH |
5239 | } |
5240 | else if (expr1.X_add_number >= -0x8000 | |
5241 | && expr1.X_add_number < 0x8000) | |
5242 | { | |
269137b2 | 5243 | load_delay_nop (); |
67c0d1eb | 5244 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 5245 | tempreg, tempreg, BFD_RELOC_LO16); |
252b5132 RH |
5246 | } |
5247 | else | |
5248 | { | |
67c0d1eb | 5249 | int dreg; |
252b5132 RH |
5250 | |
5251 | /* If we are going to add in a base register, and the | |
5252 | target register and the base register are the same, | |
5253 | then we are using AT as a temporary register. Since | |
5254 | we want to load the constant into AT, we add our | |
5255 | current AT (from the global offset table) and the | |
5256 | register into the register now, and pretend we were | |
5257 | not using a base register. */ | |
5258 | if (breg != treg) | |
67c0d1eb | 5259 | dreg = tempreg; |
252b5132 RH |
5260 | else |
5261 | { | |
5262 | assert (tempreg == AT); | |
269137b2 | 5263 | load_delay_nop (); |
67c0d1eb | 5264 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5265 | treg, AT, breg); |
252b5132 | 5266 | dreg = treg; |
252b5132 RH |
5267 | } |
5268 | ||
f6a22291 | 5269 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 5270 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT); |
252b5132 | 5271 | |
252b5132 RH |
5272 | used_at = 1; |
5273 | } | |
4d7206a2 RS |
5274 | offset_expr.X_add_number = |
5275 | ((expr1.X_add_number + 0x8000) & 0xffff) - 0x8000; | |
5276 | relax_switch (); | |
252b5132 | 5277 | |
67c0d1eb | 5278 | if (gpdelay) |
252b5132 RH |
5279 | { |
5280 | /* This is needed because this instruction uses $gp, but | |
f5040a92 | 5281 | the first instruction on the main stream does not. */ |
67c0d1eb | 5282 | macro_build (NULL, "nop", ""); |
252b5132 | 5283 | } |
ed6fb7bd | 5284 | |
67c0d1eb RS |
5285 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5286 | local_reloc_type, mips_gp_register); | |
f5040a92 | 5287 | if (expr1.X_add_number >= -0x8000 |
252b5132 RH |
5288 | && expr1.X_add_number < 0x8000) |
5289 | { | |
269137b2 | 5290 | load_delay_nop (); |
67c0d1eb RS |
5291 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
5292 | tempreg, tempreg, BFD_RELOC_LO16); | |
252b5132 | 5293 | /* FIXME: If add_number is 0, and there was no base |
f5040a92 AO |
5294 | register, the external symbol case ended with a load, |
5295 | so if the symbol turns out to not be external, and | |
5296 | the next instruction uses tempreg, an unnecessary nop | |
5297 | will be inserted. */ | |
252b5132 RH |
5298 | } |
5299 | else | |
5300 | { | |
5301 | if (breg == treg) | |
5302 | { | |
5303 | /* We must add in the base register now, as in the | |
f5040a92 | 5304 | external symbol case. */ |
252b5132 | 5305 | assert (tempreg == AT); |
269137b2 | 5306 | load_delay_nop (); |
67c0d1eb | 5307 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5308 | treg, AT, breg); |
252b5132 RH |
5309 | tempreg = treg; |
5310 | /* We set breg to 0 because we have arranged to add | |
f5040a92 | 5311 | it in in both cases. */ |
252b5132 RH |
5312 | breg = 0; |
5313 | } | |
5314 | ||
67c0d1eb RS |
5315 | macro_build_lui (&expr1, AT); |
5316 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
17a2f251 | 5317 | AT, AT, BFD_RELOC_LO16); |
67c0d1eb | 5318 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5319 | tempreg, tempreg, AT); |
8fc2e39e | 5320 | used_at = 1; |
252b5132 | 5321 | } |
4d7206a2 | 5322 | relax_end (); |
252b5132 | 5323 | } |
f5040a92 AO |
5324 | else if (mips_pic == SVR4_PIC && HAVE_NEWABI) |
5325 | { | |
f5040a92 AO |
5326 | int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; |
5327 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; | |
67c0d1eb | 5328 | int add_breg_early = 0; |
f5040a92 AO |
5329 | |
5330 | /* This is the large GOT case. If this is a reference to an | |
5331 | external symbol, and there is no constant, we want | |
5332 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5333 | add $tempreg,$tempreg,$gp | |
5334 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
1abe91b1 | 5335 | or for lca or if tempreg is PIC_CALL_REG |
f5040a92 AO |
5336 | lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) |
5337 | add $tempreg,$tempreg,$gp | |
5338 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) | |
5339 | ||
5340 | If we have a small constant, and this is a reference to | |
5341 | an external symbol, we want | |
5342 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5343 | add $tempreg,$tempreg,$gp | |
5344 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5345 | addi $tempreg,$tempreg,<constant> | |
5346 | ||
5347 | If we have a large constant, and this is a reference to | |
5348 | an external symbol, we want | |
5349 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5350 | addu $tempreg,$tempreg,$gp | |
5351 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5352 | lui $at,<hiconstant> | |
5353 | addi $at,$at,<loconstant> | |
5354 | add $tempreg,$tempreg,$at | |
5355 | ||
5356 | If we have NewABI, and we know it's a local symbol, we want | |
5357 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
5358 | addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) | |
5359 | otherwise we have to resort to GOT_HI16/GOT_LO16. */ | |
5360 | ||
4d7206a2 | 5361 | relax_start (offset_expr.X_add_symbol); |
f5040a92 | 5362 | |
4d7206a2 | 5363 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
5364 | offset_expr.X_add_number = 0; |
5365 | ||
1abe91b1 MR |
5366 | if (expr1.X_add_number == 0 && breg == 0 |
5367 | && (call || tempreg == PIC_CALL_REG)) | |
f5040a92 AO |
5368 | { |
5369 | lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; | |
5370 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; | |
5371 | } | |
67c0d1eb RS |
5372 | macro_build (&offset_expr, "lui", "t,u", tempreg, lui_reloc_type); |
5373 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 5374 | tempreg, tempreg, mips_gp_register); |
67c0d1eb RS |
5375 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5376 | tempreg, lw_reloc_type, tempreg); | |
f5040a92 AO |
5377 | |
5378 | if (expr1.X_add_number == 0) | |
4d7206a2 | 5379 | ; |
f5040a92 AO |
5380 | else if (expr1.X_add_number >= -0x8000 |
5381 | && expr1.X_add_number < 0x8000) | |
5382 | { | |
67c0d1eb | 5383 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 5384 | tempreg, tempreg, BFD_RELOC_LO16); |
f5040a92 | 5385 | } |
ecd13cd3 | 5386 | else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000)) |
f5040a92 AO |
5387 | { |
5388 | int dreg; | |
5389 | ||
5390 | /* If we are going to add in a base register, and the | |
5391 | target register and the base register are the same, | |
5392 | then we are using AT as a temporary register. Since | |
5393 | we want to load the constant into AT, we add our | |
5394 | current AT (from the global offset table) and the | |
5395 | register into the register now, and pretend we were | |
5396 | not using a base register. */ | |
5397 | if (breg != treg) | |
5398 | dreg = tempreg; | |
5399 | else | |
5400 | { | |
5401 | assert (tempreg == AT); | |
67c0d1eb | 5402 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5403 | treg, AT, breg); |
f5040a92 | 5404 | dreg = treg; |
67c0d1eb | 5405 | add_breg_early = 1; |
f5040a92 AO |
5406 | } |
5407 | ||
f6a22291 | 5408 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 5409 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT); |
f5040a92 | 5410 | |
f5040a92 AO |
5411 | used_at = 1; |
5412 | } | |
5413 | else | |
5414 | as_bad (_("PIC code offset overflow (max 32 signed bits)")); | |
5415 | ||
4d7206a2 | 5416 | relax_switch (); |
f5040a92 | 5417 | offset_expr.X_add_number = expr1.X_add_number; |
67c0d1eb RS |
5418 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5419 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
5420 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, | |
5421 | tempreg, BFD_RELOC_MIPS_GOT_OFST); | |
5422 | if (add_breg_early) | |
f5040a92 | 5423 | { |
67c0d1eb | 5424 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5425 | treg, tempreg, breg); |
f5040a92 AO |
5426 | breg = 0; |
5427 | tempreg = treg; | |
5428 | } | |
4d7206a2 | 5429 | relax_end (); |
f5040a92 | 5430 | } |
252b5132 RH |
5431 | else |
5432 | abort (); | |
5433 | ||
5434 | if (breg != 0) | |
aed1a261 | 5435 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", treg, tempreg, breg); |
252b5132 RH |
5436 | break; |
5437 | ||
5438 | case M_J_A: | |
5439 | /* The j instruction may not be used in PIC code, since it | |
5440 | requires an absolute address. We convert it to a b | |
5441 | instruction. */ | |
5442 | if (mips_pic == NO_PIC) | |
67c0d1eb | 5443 | macro_build (&offset_expr, "j", "a"); |
252b5132 | 5444 | else |
67c0d1eb | 5445 | macro_build (&offset_expr, "b", "p"); |
8fc2e39e | 5446 | break; |
252b5132 RH |
5447 | |
5448 | /* The jal instructions must be handled as macros because when | |
5449 | generating PIC code they expand to multi-instruction | |
5450 | sequences. Normally they are simple instructions. */ | |
5451 | case M_JAL_1: | |
5452 | dreg = RA; | |
5453 | /* Fall through. */ | |
5454 | case M_JAL_2: | |
3e722fb5 | 5455 | if (mips_pic == NO_PIC) |
67c0d1eb | 5456 | macro_build (NULL, "jalr", "d,s", dreg, sreg); |
252b5132 RH |
5457 | else if (mips_pic == SVR4_PIC) |
5458 | { | |
5459 | if (sreg != PIC_CALL_REG) | |
5460 | as_warn (_("MIPS PIC call to register other than $25")); | |
bdaaa2e1 | 5461 | |
67c0d1eb | 5462 | macro_build (NULL, "jalr", "d,s", dreg, sreg); |
6478892d | 5463 | if (! HAVE_NEWABI) |
252b5132 | 5464 | { |
6478892d TS |
5465 | if (mips_cprestore_offset < 0) |
5466 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
5467 | else | |
5468 | { | |
7a621144 DJ |
5469 | if (! mips_frame_reg_valid) |
5470 | { | |
5471 | as_warn (_("No .frame pseudo-op used in PIC code")); | |
5472 | /* Quiet this warning. */ | |
5473 | mips_frame_reg_valid = 1; | |
5474 | } | |
5475 | if (! mips_cprestore_valid) | |
5476 | { | |
5477 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
5478 | /* Quiet this warning. */ | |
5479 | mips_cprestore_valid = 1; | |
5480 | } | |
6478892d | 5481 | expr1.X_add_number = mips_cprestore_offset; |
67c0d1eb | 5482 | macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN, |
f899b4b8 | 5483 | mips_gp_register, |
256ab948 TS |
5484 | mips_frame_reg, |
5485 | HAVE_64BIT_ADDRESSES); | |
6478892d | 5486 | } |
252b5132 RH |
5487 | } |
5488 | } | |
5489 | else | |
5490 | abort (); | |
5491 | ||
8fc2e39e | 5492 | break; |
252b5132 RH |
5493 | |
5494 | case M_JAL_A: | |
5495 | if (mips_pic == NO_PIC) | |
67c0d1eb | 5496 | macro_build (&offset_expr, "jal", "a"); |
252b5132 RH |
5497 | else if (mips_pic == SVR4_PIC) |
5498 | { | |
5499 | /* If this is a reference to an external symbol, and we are | |
5500 | using a small GOT, we want | |
5501 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16) | |
5502 | nop | |
f9419b05 | 5503 | jalr $ra,$25 |
252b5132 RH |
5504 | nop |
5505 | lw $gp,cprestore($sp) | |
5506 | The cprestore value is set using the .cprestore | |
5507 | pseudo-op. If we are using a big GOT, we want | |
5508 | lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16) | |
5509 | addu $25,$25,$gp | |
5510 | lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16) | |
5511 | nop | |
f9419b05 | 5512 | jalr $ra,$25 |
252b5132 RH |
5513 | nop |
5514 | lw $gp,cprestore($sp) | |
5515 | If the symbol is not external, we want | |
5516 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5517 | nop | |
5518 | addiu $25,$25,<sym> (BFD_RELOC_LO16) | |
f9419b05 | 5519 | jalr $ra,$25 |
252b5132 | 5520 | nop |
438c16b8 | 5521 | lw $gp,cprestore($sp) |
f5040a92 AO |
5522 | |
5523 | For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16 | |
5524 | sequences above, minus nops, unless the symbol is local, | |
5525 | which enables us to use GOT_PAGE/GOT_OFST (big got) or | |
5526 | GOT_DISP. */ | |
438c16b8 | 5527 | if (HAVE_NEWABI) |
252b5132 | 5528 | { |
f5040a92 AO |
5529 | if (! mips_big_got) |
5530 | { | |
4d7206a2 | 5531 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
5532 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5533 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL16, | |
f5040a92 | 5534 | mips_gp_register); |
4d7206a2 | 5535 | relax_switch (); |
67c0d1eb RS |
5536 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5537 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT_DISP, | |
4d7206a2 RS |
5538 | mips_gp_register); |
5539 | relax_end (); | |
f5040a92 AO |
5540 | } |
5541 | else | |
5542 | { | |
4d7206a2 | 5543 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
5544 | macro_build (&offset_expr, "lui", "t,u", PIC_CALL_REG, |
5545 | BFD_RELOC_MIPS_CALL_HI16); | |
5546 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG, | |
5547 | PIC_CALL_REG, mips_gp_register); | |
5548 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", | |
5549 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16, | |
5550 | PIC_CALL_REG); | |
4d7206a2 | 5551 | relax_switch (); |
67c0d1eb RS |
5552 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5553 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT_PAGE, | |
5554 | mips_gp_register); | |
5555 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
5556 | PIC_CALL_REG, PIC_CALL_REG, | |
17a2f251 | 5557 | BFD_RELOC_MIPS_GOT_OFST); |
4d7206a2 | 5558 | relax_end (); |
f5040a92 | 5559 | } |
684022ea | 5560 | |
67c0d1eb | 5561 | macro_build_jalr (&offset_expr); |
252b5132 RH |
5562 | } |
5563 | else | |
5564 | { | |
4d7206a2 | 5565 | relax_start (offset_expr.X_add_symbol); |
438c16b8 TS |
5566 | if (! mips_big_got) |
5567 | { | |
67c0d1eb RS |
5568 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5569 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL16, | |
17a2f251 | 5570 | mips_gp_register); |
269137b2 | 5571 | load_delay_nop (); |
4d7206a2 | 5572 | relax_switch (); |
438c16b8 | 5573 | } |
252b5132 | 5574 | else |
252b5132 | 5575 | { |
67c0d1eb RS |
5576 | int gpdelay; |
5577 | ||
5578 | gpdelay = reg_needs_delay (mips_gp_register); | |
5579 | macro_build (&offset_expr, "lui", "t,u", PIC_CALL_REG, | |
5580 | BFD_RELOC_MIPS_CALL_HI16); | |
5581 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG, | |
5582 | PIC_CALL_REG, mips_gp_register); | |
5583 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", | |
5584 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16, | |
5585 | PIC_CALL_REG); | |
269137b2 | 5586 | load_delay_nop (); |
4d7206a2 | 5587 | relax_switch (); |
67c0d1eb RS |
5588 | if (gpdelay) |
5589 | macro_build (NULL, "nop", ""); | |
252b5132 | 5590 | } |
67c0d1eb RS |
5591 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5592 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT16, | |
4d7206a2 | 5593 | mips_gp_register); |
269137b2 | 5594 | load_delay_nop (); |
67c0d1eb RS |
5595 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
5596 | PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16); | |
4d7206a2 | 5597 | relax_end (); |
67c0d1eb | 5598 | macro_build_jalr (&offset_expr); |
438c16b8 | 5599 | |
6478892d TS |
5600 | if (mips_cprestore_offset < 0) |
5601 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
5602 | else | |
5603 | { | |
7a621144 DJ |
5604 | if (! mips_frame_reg_valid) |
5605 | { | |
5606 | as_warn (_("No .frame pseudo-op used in PIC code")); | |
5607 | /* Quiet this warning. */ | |
5608 | mips_frame_reg_valid = 1; | |
5609 | } | |
5610 | if (! mips_cprestore_valid) | |
5611 | { | |
5612 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
5613 | /* Quiet this warning. */ | |
5614 | mips_cprestore_valid = 1; | |
5615 | } | |
6478892d | 5616 | if (mips_opts.noreorder) |
67c0d1eb | 5617 | macro_build (NULL, "nop", ""); |
6478892d | 5618 | expr1.X_add_number = mips_cprestore_offset; |
67c0d1eb | 5619 | macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN, |
f899b4b8 | 5620 | mips_gp_register, |
256ab948 TS |
5621 | mips_frame_reg, |
5622 | HAVE_64BIT_ADDRESSES); | |
6478892d | 5623 | } |
252b5132 RH |
5624 | } |
5625 | } | |
252b5132 RH |
5626 | else |
5627 | abort (); | |
5628 | ||
8fc2e39e | 5629 | break; |
252b5132 RH |
5630 | |
5631 | case M_LB_AB: | |
5632 | s = "lb"; | |
5633 | goto ld; | |
5634 | case M_LBU_AB: | |
5635 | s = "lbu"; | |
5636 | goto ld; | |
5637 | case M_LH_AB: | |
5638 | s = "lh"; | |
5639 | goto ld; | |
5640 | case M_LHU_AB: | |
5641 | s = "lhu"; | |
5642 | goto ld; | |
5643 | case M_LW_AB: | |
5644 | s = "lw"; | |
5645 | goto ld; | |
5646 | case M_LWC0_AB: | |
5647 | s = "lwc0"; | |
bdaaa2e1 | 5648 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5649 | coproc = 1; |
5650 | goto ld; | |
5651 | case M_LWC1_AB: | |
5652 | s = "lwc1"; | |
bdaaa2e1 | 5653 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5654 | coproc = 1; |
5655 | goto ld; | |
5656 | case M_LWC2_AB: | |
5657 | s = "lwc2"; | |
bdaaa2e1 | 5658 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5659 | coproc = 1; |
5660 | goto ld; | |
5661 | case M_LWC3_AB: | |
5662 | s = "lwc3"; | |
bdaaa2e1 | 5663 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5664 | coproc = 1; |
5665 | goto ld; | |
5666 | case M_LWL_AB: | |
5667 | s = "lwl"; | |
5668 | lr = 1; | |
5669 | goto ld; | |
5670 | case M_LWR_AB: | |
5671 | s = "lwr"; | |
5672 | lr = 1; | |
5673 | goto ld; | |
5674 | case M_LDC1_AB: | |
fef14a42 | 5675 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
5676 | { |
5677 | as_bad (_("opcode not supported on this processor")); | |
8fc2e39e | 5678 | break; |
252b5132 RH |
5679 | } |
5680 | s = "ldc1"; | |
bdaaa2e1 | 5681 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5682 | coproc = 1; |
5683 | goto ld; | |
5684 | case M_LDC2_AB: | |
5685 | s = "ldc2"; | |
bdaaa2e1 | 5686 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5687 | coproc = 1; |
5688 | goto ld; | |
5689 | case M_LDC3_AB: | |
5690 | s = "ldc3"; | |
bdaaa2e1 | 5691 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5692 | coproc = 1; |
5693 | goto ld; | |
5694 | case M_LDL_AB: | |
5695 | s = "ldl"; | |
5696 | lr = 1; | |
5697 | goto ld; | |
5698 | case M_LDR_AB: | |
5699 | s = "ldr"; | |
5700 | lr = 1; | |
5701 | goto ld; | |
5702 | case M_LL_AB: | |
5703 | s = "ll"; | |
5704 | goto ld; | |
5705 | case M_LLD_AB: | |
5706 | s = "lld"; | |
5707 | goto ld; | |
5708 | case M_LWU_AB: | |
5709 | s = "lwu"; | |
5710 | ld: | |
8fc2e39e | 5711 | if (breg == treg || coproc || lr) |
252b5132 RH |
5712 | { |
5713 | tempreg = AT; | |
5714 | used_at = 1; | |
5715 | } | |
5716 | else | |
5717 | { | |
5718 | tempreg = treg; | |
252b5132 RH |
5719 | } |
5720 | goto ld_st; | |
5721 | case M_SB_AB: | |
5722 | s = "sb"; | |
5723 | goto st; | |
5724 | case M_SH_AB: | |
5725 | s = "sh"; | |
5726 | goto st; | |
5727 | case M_SW_AB: | |
5728 | s = "sw"; | |
5729 | goto st; | |
5730 | case M_SWC0_AB: | |
5731 | s = "swc0"; | |
bdaaa2e1 | 5732 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5733 | coproc = 1; |
5734 | goto st; | |
5735 | case M_SWC1_AB: | |
5736 | s = "swc1"; | |
bdaaa2e1 | 5737 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5738 | coproc = 1; |
5739 | goto st; | |
5740 | case M_SWC2_AB: | |
5741 | s = "swc2"; | |
bdaaa2e1 | 5742 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5743 | coproc = 1; |
5744 | goto st; | |
5745 | case M_SWC3_AB: | |
5746 | s = "swc3"; | |
bdaaa2e1 | 5747 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5748 | coproc = 1; |
5749 | goto st; | |
5750 | case M_SWL_AB: | |
5751 | s = "swl"; | |
5752 | goto st; | |
5753 | case M_SWR_AB: | |
5754 | s = "swr"; | |
5755 | goto st; | |
5756 | case M_SC_AB: | |
5757 | s = "sc"; | |
5758 | goto st; | |
5759 | case M_SCD_AB: | |
5760 | s = "scd"; | |
5761 | goto st; | |
5762 | case M_SDC1_AB: | |
fef14a42 | 5763 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
5764 | { |
5765 | as_bad (_("opcode not supported on this processor")); | |
8fc2e39e | 5766 | break; |
252b5132 RH |
5767 | } |
5768 | s = "sdc1"; | |
5769 | coproc = 1; | |
bdaaa2e1 | 5770 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5771 | goto st; |
5772 | case M_SDC2_AB: | |
5773 | s = "sdc2"; | |
bdaaa2e1 | 5774 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5775 | coproc = 1; |
5776 | goto st; | |
5777 | case M_SDC3_AB: | |
5778 | s = "sdc3"; | |
bdaaa2e1 | 5779 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5780 | coproc = 1; |
5781 | goto st; | |
5782 | case M_SDL_AB: | |
5783 | s = "sdl"; | |
5784 | goto st; | |
5785 | case M_SDR_AB: | |
5786 | s = "sdr"; | |
5787 | st: | |
8fc2e39e TS |
5788 | tempreg = AT; |
5789 | used_at = 1; | |
252b5132 | 5790 | ld_st: |
bdaaa2e1 | 5791 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5792 | if (mask == M_LWC1_AB |
5793 | || mask == M_SWC1_AB | |
5794 | || mask == M_LDC1_AB | |
5795 | || mask == M_SDC1_AB | |
5796 | || mask == M_L_DAB | |
5797 | || mask == M_S_DAB) | |
5798 | fmt = "T,o(b)"; | |
5799 | else if (coproc) | |
5800 | fmt = "E,o(b)"; | |
5801 | else | |
5802 | fmt = "t,o(b)"; | |
5803 | ||
5804 | if (offset_expr.X_op != O_constant | |
5805 | && offset_expr.X_op != O_symbol) | |
5806 | { | |
5807 | as_bad (_("expression too complex")); | |
5808 | offset_expr.X_op = O_constant; | |
5809 | } | |
5810 | ||
5811 | /* A constant expression in PIC code can be handled just as it | |
5812 | is in non PIC code. */ | |
aed1a261 RS |
5813 | if (offset_expr.X_op == O_constant) |
5814 | { | |
5815 | if (HAVE_32BIT_ADDRESSES | |
5816 | && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) | |
5817 | as_bad (_("constant too large")); | |
5818 | ||
5819 | expr1.X_add_number = ((offset_expr.X_add_number + 0x8000) | |
5820 | & ~(bfd_vma) 0xffff); | |
5821 | load_register (tempreg, &expr1, HAVE_64BIT_ADDRESSES); | |
5822 | if (breg != 0) | |
5823 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
5824 | tempreg, tempreg, breg); | |
5825 | macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, tempreg); | |
5826 | } | |
5827 | else if (mips_pic == NO_PIC) | |
252b5132 RH |
5828 | { |
5829 | /* If this is a reference to a GP relative symbol, and there | |
5830 | is no base register, we want | |
cdf6fd85 | 5831 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
252b5132 RH |
5832 | Otherwise, if there is no base register, we want |
5833 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
5834 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
5835 | If we have a constant, we need two instructions anyhow, | |
5836 | so we always use the latter form. | |
5837 | ||
5838 | If we have a base register, and this is a reference to a | |
5839 | GP relative symbol, we want | |
5840 | addu $tempreg,$breg,$gp | |
cdf6fd85 | 5841 | <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16) |
252b5132 RH |
5842 | Otherwise we want |
5843 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
5844 | addu $tempreg,$tempreg,$breg | |
5845 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
d6bc6245 | 5846 | With a constant we always use the latter case. |
76b3015f | 5847 | |
d6bc6245 TS |
5848 | With 64bit address space and no base register and $at usable, |
5849 | we want | |
5850 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5851 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
5852 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5853 | dsll32 $tempreg,0 | |
5854 | daddu $tempreg,$at | |
5855 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
5856 | If we have a base register, we want | |
5857 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5858 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
5859 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5860 | daddu $at,$breg | |
5861 | dsll32 $tempreg,0 | |
5862 | daddu $tempreg,$at | |
5863 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
5864 | ||
5865 | Without $at we can't generate the optimal path for superscalar | |
5866 | processors here since this would require two temporary registers. | |
5867 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5868 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5869 | dsll $tempreg,16 | |
5870 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
5871 | dsll $tempreg,16 | |
5872 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
5873 | If we have a base register, we want | |
5874 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5875 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5876 | dsll $tempreg,16 | |
5877 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
5878 | dsll $tempreg,16 | |
5879 | daddu $tempreg,$tempreg,$breg | |
5880 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
6373ee54 | 5881 | |
6caf9ef4 | 5882 | For GP relative symbols in 64bit address space we can use |
aed1a261 RS |
5883 | the same sequence as in 32bit address space. */ |
5884 | if (HAVE_64BIT_SYMBOLS) | |
d6bc6245 | 5885 | { |
aed1a261 | 5886 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 TS |
5887 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
5888 | { | |
5889 | relax_start (offset_expr.X_add_symbol); | |
5890 | if (breg == 0) | |
5891 | { | |
5892 | macro_build (&offset_expr, s, fmt, treg, | |
5893 | BFD_RELOC_GPREL16, mips_gp_register); | |
5894 | } | |
5895 | else | |
5896 | { | |
5897 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
5898 | tempreg, breg, mips_gp_register); | |
5899 | macro_build (&offset_expr, s, fmt, treg, | |
5900 | BFD_RELOC_GPREL16, tempreg); | |
5901 | } | |
5902 | relax_switch (); | |
5903 | } | |
d6bc6245 | 5904 | |
b8285c27 | 5905 | if (used_at == 0 && !mips_opts.noat) |
d6bc6245 | 5906 | { |
67c0d1eb RS |
5907 | macro_build (&offset_expr, "lui", "t,u", tempreg, |
5908 | BFD_RELOC_MIPS_HIGHEST); | |
5909 | macro_build (&offset_expr, "lui", "t,u", AT, | |
5910 | BFD_RELOC_HI16_S); | |
5911 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
5912 | tempreg, BFD_RELOC_MIPS_HIGHER); | |
d6bc6245 | 5913 | if (breg != 0) |
67c0d1eb RS |
5914 | macro_build (NULL, "daddu", "d,v,t", AT, AT, breg); |
5915 | macro_build (NULL, "dsll32", "d,w,<", tempreg, tempreg, 0); | |
5916 | macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT); | |
5917 | macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, | |
5918 | tempreg); | |
d6bc6245 TS |
5919 | used_at = 1; |
5920 | } | |
5921 | else | |
5922 | { | |
67c0d1eb RS |
5923 | macro_build (&offset_expr, "lui", "t,u", tempreg, |
5924 | BFD_RELOC_MIPS_HIGHEST); | |
5925 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
5926 | tempreg, BFD_RELOC_MIPS_HIGHER); | |
5927 | macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16); | |
5928 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
5929 | tempreg, BFD_RELOC_HI16_S); | |
5930 | macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16); | |
d6bc6245 | 5931 | if (breg != 0) |
67c0d1eb | 5932 | macro_build (NULL, "daddu", "d,v,t", |
17a2f251 | 5933 | tempreg, tempreg, breg); |
67c0d1eb | 5934 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 5935 | BFD_RELOC_LO16, tempreg); |
d6bc6245 | 5936 | } |
6caf9ef4 TS |
5937 | |
5938 | if (mips_relax.sequence) | |
5939 | relax_end (); | |
8fc2e39e | 5940 | break; |
d6bc6245 | 5941 | } |
256ab948 | 5942 | |
252b5132 RH |
5943 | if (breg == 0) |
5944 | { | |
67c0d1eb | 5945 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 5946 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 5947 | { |
4d7206a2 | 5948 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
5949 | macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_GPREL16, |
5950 | mips_gp_register); | |
4d7206a2 | 5951 | relax_switch (); |
252b5132 | 5952 | } |
67c0d1eb RS |
5953 | macro_build_lui (&offset_expr, tempreg); |
5954 | macro_build (&offset_expr, s, fmt, treg, | |
17a2f251 | 5955 | BFD_RELOC_LO16, tempreg); |
4d7206a2 RS |
5956 | if (mips_relax.sequence) |
5957 | relax_end (); | |
252b5132 RH |
5958 | } |
5959 | else | |
5960 | { | |
67c0d1eb | 5961 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 5962 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 5963 | { |
4d7206a2 | 5964 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 5965 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5966 | tempreg, breg, mips_gp_register); |
67c0d1eb | 5967 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 5968 | BFD_RELOC_GPREL16, tempreg); |
4d7206a2 | 5969 | relax_switch (); |
252b5132 | 5970 | } |
67c0d1eb RS |
5971 | macro_build_lui (&offset_expr, tempreg); |
5972 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 5973 | tempreg, tempreg, breg); |
67c0d1eb | 5974 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 5975 | BFD_RELOC_LO16, tempreg); |
4d7206a2 RS |
5976 | if (mips_relax.sequence) |
5977 | relax_end (); | |
252b5132 RH |
5978 | } |
5979 | } | |
5980 | else if (mips_pic == SVR4_PIC && ! mips_big_got) | |
5981 | { | |
ed6fb7bd | 5982 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
f9419b05 | 5983 | |
252b5132 RH |
5984 | /* If this is a reference to an external symbol, we want |
5985 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5986 | nop | |
5987 | <op> $treg,0($tempreg) | |
5988 | Otherwise we want | |
5989 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5990 | nop | |
5991 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
5992 | <op> $treg,0($tempreg) | |
f5040a92 AO |
5993 | |
5994 | For NewABI, we want | |
5995 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
5996 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) | |
5997 | ||
252b5132 RH |
5998 | If there is a base register, we add it to $tempreg before |
5999 | the <op>. If there is a constant, we stick it in the | |
6000 | <op> instruction. We don't handle constants larger than | |
6001 | 16 bits, because we have no way to load the upper 16 bits | |
6002 | (actually, we could handle them for the subset of cases | |
6003 | in which we are not using $at). */ | |
6004 | assert (offset_expr.X_op == O_symbol); | |
f5040a92 AO |
6005 | if (HAVE_NEWABI) |
6006 | { | |
67c0d1eb RS |
6007 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
6008 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
f5040a92 | 6009 | if (breg != 0) |
67c0d1eb | 6010 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6011 | tempreg, tempreg, breg); |
67c0d1eb | 6012 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 6013 | BFD_RELOC_MIPS_GOT_OFST, tempreg); |
f5040a92 AO |
6014 | break; |
6015 | } | |
252b5132 RH |
6016 | expr1.X_add_number = offset_expr.X_add_number; |
6017 | offset_expr.X_add_number = 0; | |
6018 | if (expr1.X_add_number < -0x8000 | |
6019 | || expr1.X_add_number >= 0x8000) | |
6020 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb RS |
6021 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
6022 | lw_reloc_type, mips_gp_register); | |
269137b2 | 6023 | load_delay_nop (); |
4d7206a2 RS |
6024 | relax_start (offset_expr.X_add_symbol); |
6025 | relax_switch (); | |
67c0d1eb RS |
6026 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, |
6027 | tempreg, BFD_RELOC_LO16); | |
4d7206a2 | 6028 | relax_end (); |
252b5132 | 6029 | if (breg != 0) |
67c0d1eb | 6030 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6031 | tempreg, tempreg, breg); |
67c0d1eb | 6032 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
252b5132 | 6033 | } |
f5040a92 | 6034 | else if (mips_pic == SVR4_PIC && ! HAVE_NEWABI) |
252b5132 | 6035 | { |
67c0d1eb | 6036 | int gpdelay; |
252b5132 RH |
6037 | |
6038 | /* If this is a reference to an external symbol, we want | |
6039 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
6040 | addu $tempreg,$tempreg,$gp | |
6041 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
6042 | <op> $treg,0($tempreg) | |
6043 | Otherwise we want | |
6044 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6045 | nop | |
6046 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
6047 | <op> $treg,0($tempreg) | |
6048 | If there is a base register, we add it to $tempreg before | |
6049 | the <op>. If there is a constant, we stick it in the | |
6050 | <op> instruction. We don't handle constants larger than | |
6051 | 16 bits, because we have no way to load the upper 16 bits | |
6052 | (actually, we could handle them for the subset of cases | |
f5040a92 | 6053 | in which we are not using $at). */ |
252b5132 RH |
6054 | assert (offset_expr.X_op == O_symbol); |
6055 | expr1.X_add_number = offset_expr.X_add_number; | |
6056 | offset_expr.X_add_number = 0; | |
6057 | if (expr1.X_add_number < -0x8000 | |
6058 | || expr1.X_add_number >= 0x8000) | |
6059 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 6060 | gpdelay = reg_needs_delay (mips_gp_register); |
4d7206a2 | 6061 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 6062 | macro_build (&offset_expr, "lui", "t,u", tempreg, |
17a2f251 | 6063 | BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
6064 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, |
6065 | mips_gp_register); | |
6066 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
6067 | BFD_RELOC_MIPS_GOT_LO16, tempreg); | |
4d7206a2 | 6068 | relax_switch (); |
67c0d1eb RS |
6069 | if (gpdelay) |
6070 | macro_build (NULL, "nop", ""); | |
6071 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
6072 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 6073 | load_delay_nop (); |
67c0d1eb RS |
6074 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, |
6075 | tempreg, BFD_RELOC_LO16); | |
4d7206a2 RS |
6076 | relax_end (); |
6077 | ||
252b5132 | 6078 | if (breg != 0) |
67c0d1eb | 6079 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6080 | tempreg, tempreg, breg); |
67c0d1eb | 6081 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
252b5132 | 6082 | } |
f5040a92 AO |
6083 | else if (mips_pic == SVR4_PIC && HAVE_NEWABI) |
6084 | { | |
f5040a92 AO |
6085 | /* If this is a reference to an external symbol, we want |
6086 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
6087 | add $tempreg,$tempreg,$gp | |
6088 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
6089 | <op> $treg,<ofst>($tempreg) | |
6090 | Otherwise, for local symbols, we want: | |
6091 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
6092 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */ | |
6093 | assert (offset_expr.X_op == O_symbol); | |
4d7206a2 | 6094 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
6095 | offset_expr.X_add_number = 0; |
6096 | if (expr1.X_add_number < -0x8000 | |
6097 | || expr1.X_add_number >= 0x8000) | |
6098 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4d7206a2 | 6099 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 6100 | macro_build (&offset_expr, "lui", "t,u", tempreg, |
17a2f251 | 6101 | BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
6102 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, |
6103 | mips_gp_register); | |
6104 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
6105 | BFD_RELOC_MIPS_GOT_LO16, tempreg); | |
f5040a92 | 6106 | if (breg != 0) |
67c0d1eb | 6107 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6108 | tempreg, tempreg, breg); |
67c0d1eb | 6109 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
684022ea | 6110 | |
4d7206a2 | 6111 | relax_switch (); |
f5040a92 | 6112 | offset_expr.X_add_number = expr1.X_add_number; |
67c0d1eb RS |
6113 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
6114 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
f5040a92 | 6115 | if (breg != 0) |
67c0d1eb | 6116 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6117 | tempreg, tempreg, breg); |
67c0d1eb | 6118 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 6119 | BFD_RELOC_MIPS_GOT_OFST, tempreg); |
4d7206a2 | 6120 | relax_end (); |
f5040a92 | 6121 | } |
252b5132 RH |
6122 | else |
6123 | abort (); | |
6124 | ||
252b5132 RH |
6125 | break; |
6126 | ||
6127 | case M_LI: | |
6128 | case M_LI_S: | |
67c0d1eb | 6129 | load_register (treg, &imm_expr, 0); |
8fc2e39e | 6130 | break; |
252b5132 RH |
6131 | |
6132 | case M_DLI: | |
67c0d1eb | 6133 | load_register (treg, &imm_expr, 1); |
8fc2e39e | 6134 | break; |
252b5132 RH |
6135 | |
6136 | case M_LI_SS: | |
6137 | if (imm_expr.X_op == O_constant) | |
6138 | { | |
8fc2e39e | 6139 | used_at = 1; |
67c0d1eb RS |
6140 | load_register (AT, &imm_expr, 0); |
6141 | macro_build (NULL, "mtc1", "t,G", AT, treg); | |
252b5132 RH |
6142 | break; |
6143 | } | |
6144 | else | |
6145 | { | |
6146 | assert (offset_expr.X_op == O_symbol | |
6147 | && strcmp (segment_name (S_GET_SEGMENT | |
6148 | (offset_expr.X_add_symbol)), | |
6149 | ".lit4") == 0 | |
6150 | && offset_expr.X_add_number == 0); | |
67c0d1eb | 6151 | macro_build (&offset_expr, "lwc1", "T,o(b)", treg, |
17a2f251 | 6152 | BFD_RELOC_MIPS_LITERAL, mips_gp_register); |
8fc2e39e | 6153 | break; |
252b5132 RH |
6154 | } |
6155 | ||
6156 | case M_LI_D: | |
ca4e0257 RS |
6157 | /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits |
6158 | wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high | |
6159 | order 32 bits of the value and the low order 32 bits are either | |
6160 | zero or in OFFSET_EXPR. */ | |
252b5132 RH |
6161 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) |
6162 | { | |
ca4e0257 | 6163 | if (HAVE_64BIT_GPRS) |
67c0d1eb | 6164 | load_register (treg, &imm_expr, 1); |
252b5132 RH |
6165 | else |
6166 | { | |
6167 | int hreg, lreg; | |
6168 | ||
6169 | if (target_big_endian) | |
6170 | { | |
6171 | hreg = treg; | |
6172 | lreg = treg + 1; | |
6173 | } | |
6174 | else | |
6175 | { | |
6176 | hreg = treg + 1; | |
6177 | lreg = treg; | |
6178 | } | |
6179 | ||
6180 | if (hreg <= 31) | |
67c0d1eb | 6181 | load_register (hreg, &imm_expr, 0); |
252b5132 RH |
6182 | if (lreg <= 31) |
6183 | { | |
6184 | if (offset_expr.X_op == O_absent) | |
67c0d1eb | 6185 | move_register (lreg, 0); |
252b5132 RH |
6186 | else |
6187 | { | |
6188 | assert (offset_expr.X_op == O_constant); | |
67c0d1eb | 6189 | load_register (lreg, &offset_expr, 0); |
252b5132 RH |
6190 | } |
6191 | } | |
6192 | } | |
8fc2e39e | 6193 | break; |
252b5132 RH |
6194 | } |
6195 | ||
6196 | /* We know that sym is in the .rdata section. First we get the | |
6197 | upper 16 bits of the address. */ | |
6198 | if (mips_pic == NO_PIC) | |
6199 | { | |
67c0d1eb | 6200 | macro_build_lui (&offset_expr, AT); |
8fc2e39e | 6201 | used_at = 1; |
252b5132 RH |
6202 | } |
6203 | else if (mips_pic == SVR4_PIC) | |
6204 | { | |
67c0d1eb RS |
6205 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, |
6206 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
8fc2e39e | 6207 | used_at = 1; |
252b5132 | 6208 | } |
252b5132 RH |
6209 | else |
6210 | abort (); | |
bdaaa2e1 | 6211 | |
252b5132 | 6212 | /* Now we load the register(s). */ |
ca4e0257 | 6213 | if (HAVE_64BIT_GPRS) |
8fc2e39e TS |
6214 | { |
6215 | used_at = 1; | |
6216 | macro_build (&offset_expr, "ld", "t,o(b)", treg, BFD_RELOC_LO16, AT); | |
6217 | } | |
252b5132 RH |
6218 | else |
6219 | { | |
8fc2e39e | 6220 | used_at = 1; |
67c0d1eb | 6221 | macro_build (&offset_expr, "lw", "t,o(b)", treg, BFD_RELOC_LO16, AT); |
f9419b05 | 6222 | if (treg != RA) |
252b5132 RH |
6223 | { |
6224 | /* FIXME: How in the world do we deal with the possible | |
6225 | overflow here? */ | |
6226 | offset_expr.X_add_number += 4; | |
67c0d1eb | 6227 | macro_build (&offset_expr, "lw", "t,o(b)", |
17a2f251 | 6228 | treg + 1, BFD_RELOC_LO16, AT); |
252b5132 RH |
6229 | } |
6230 | } | |
252b5132 RH |
6231 | break; |
6232 | ||
6233 | case M_LI_DD: | |
ca4e0257 RS |
6234 | /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits |
6235 | wide, IMM_EXPR is the entire value and the GPRs are known to be 64 | |
6236 | bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of | |
6237 | the value and the low order 32 bits are either zero or in | |
6238 | OFFSET_EXPR. */ | |
252b5132 RH |
6239 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) |
6240 | { | |
8fc2e39e | 6241 | used_at = 1; |
67c0d1eb | 6242 | load_register (AT, &imm_expr, HAVE_64BIT_FPRS); |
ca4e0257 RS |
6243 | if (HAVE_64BIT_FPRS) |
6244 | { | |
6245 | assert (HAVE_64BIT_GPRS); | |
67c0d1eb | 6246 | macro_build (NULL, "dmtc1", "t,S", AT, treg); |
ca4e0257 | 6247 | } |
252b5132 RH |
6248 | else |
6249 | { | |
67c0d1eb | 6250 | macro_build (NULL, "mtc1", "t,G", AT, treg + 1); |
252b5132 | 6251 | if (offset_expr.X_op == O_absent) |
67c0d1eb | 6252 | macro_build (NULL, "mtc1", "t,G", 0, treg); |
252b5132 RH |
6253 | else |
6254 | { | |
6255 | assert (offset_expr.X_op == O_constant); | |
67c0d1eb RS |
6256 | load_register (AT, &offset_expr, 0); |
6257 | macro_build (NULL, "mtc1", "t,G", AT, treg); | |
252b5132 RH |
6258 | } |
6259 | } | |
6260 | break; | |
6261 | } | |
6262 | ||
6263 | assert (offset_expr.X_op == O_symbol | |
6264 | && offset_expr.X_add_number == 0); | |
6265 | s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol)); | |
6266 | if (strcmp (s, ".lit8") == 0) | |
6267 | { | |
e7af610e | 6268 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 | 6269 | { |
67c0d1eb | 6270 | macro_build (&offset_expr, "ldc1", "T,o(b)", treg, |
17a2f251 | 6271 | BFD_RELOC_MIPS_LITERAL, mips_gp_register); |
8fc2e39e | 6272 | break; |
252b5132 | 6273 | } |
c9914766 | 6274 | breg = mips_gp_register; |
252b5132 RH |
6275 | r = BFD_RELOC_MIPS_LITERAL; |
6276 | goto dob; | |
6277 | } | |
6278 | else | |
6279 | { | |
6280 | assert (strcmp (s, RDATA_SECTION_NAME) == 0); | |
8fc2e39e | 6281 | used_at = 1; |
252b5132 | 6282 | if (mips_pic == SVR4_PIC) |
67c0d1eb RS |
6283 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, |
6284 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
252b5132 RH |
6285 | else |
6286 | { | |
6287 | /* FIXME: This won't work for a 64 bit address. */ | |
67c0d1eb | 6288 | macro_build_lui (&offset_expr, AT); |
252b5132 | 6289 | } |
bdaaa2e1 | 6290 | |
e7af610e | 6291 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 | 6292 | { |
67c0d1eb RS |
6293 | macro_build (&offset_expr, "ldc1", "T,o(b)", |
6294 | treg, BFD_RELOC_LO16, AT); | |
252b5132 RH |
6295 | break; |
6296 | } | |
6297 | breg = AT; | |
6298 | r = BFD_RELOC_LO16; | |
6299 | goto dob; | |
6300 | } | |
6301 | ||
6302 | case M_L_DOB: | |
fef14a42 | 6303 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
6304 | { |
6305 | as_bad (_("opcode not supported on this processor")); | |
8fc2e39e | 6306 | break; |
252b5132 RH |
6307 | } |
6308 | /* Even on a big endian machine $fn comes before $fn+1. We have | |
6309 | to adjust when loading from memory. */ | |
6310 | r = BFD_RELOC_LO16; | |
6311 | dob: | |
e7af610e | 6312 | assert (mips_opts.isa == ISA_MIPS1); |
67c0d1eb | 6313 | macro_build (&offset_expr, "lwc1", "T,o(b)", |
17a2f251 | 6314 | target_big_endian ? treg + 1 : treg, r, breg); |
252b5132 RH |
6315 | /* FIXME: A possible overflow which I don't know how to deal |
6316 | with. */ | |
6317 | offset_expr.X_add_number += 4; | |
67c0d1eb | 6318 | macro_build (&offset_expr, "lwc1", "T,o(b)", |
17a2f251 | 6319 | target_big_endian ? treg : treg + 1, r, breg); |
252b5132 RH |
6320 | break; |
6321 | ||
6322 | case M_L_DAB: | |
6323 | /* | |
6324 | * The MIPS assembler seems to check for X_add_number not | |
6325 | * being double aligned and generating: | |
6326 | * lui at,%hi(foo+1) | |
6327 | * addu at,at,v1 | |
6328 | * addiu at,at,%lo(foo+1) | |
6329 | * lwc1 f2,0(at) | |
6330 | * lwc1 f3,4(at) | |
6331 | * But, the resulting address is the same after relocation so why | |
6332 | * generate the extra instruction? | |
6333 | */ | |
fef14a42 | 6334 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
6335 | { |
6336 | as_bad (_("opcode not supported on this processor")); | |
8fc2e39e | 6337 | break; |
252b5132 | 6338 | } |
bdaaa2e1 | 6339 | /* Itbl support may require additional care here. */ |
252b5132 | 6340 | coproc = 1; |
e7af610e | 6341 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 RH |
6342 | { |
6343 | s = "ldc1"; | |
6344 | goto ld; | |
6345 | } | |
6346 | ||
6347 | s = "lwc1"; | |
6348 | fmt = "T,o(b)"; | |
6349 | goto ldd_std; | |
6350 | ||
6351 | case M_S_DAB: | |
fef14a42 | 6352 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
6353 | { |
6354 | as_bad (_("opcode not supported on this processor")); | |
8fc2e39e | 6355 | break; |
252b5132 RH |
6356 | } |
6357 | ||
e7af610e | 6358 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 RH |
6359 | { |
6360 | s = "sdc1"; | |
6361 | goto st; | |
6362 | } | |
6363 | ||
6364 | s = "swc1"; | |
6365 | fmt = "T,o(b)"; | |
bdaaa2e1 | 6366 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6367 | coproc = 1; |
6368 | goto ldd_std; | |
6369 | ||
6370 | case M_LD_AB: | |
ca4e0257 | 6371 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
6372 | { |
6373 | s = "ld"; | |
6374 | goto ld; | |
6375 | } | |
6376 | ||
6377 | s = "lw"; | |
6378 | fmt = "t,o(b)"; | |
6379 | goto ldd_std; | |
6380 | ||
6381 | case M_SD_AB: | |
ca4e0257 | 6382 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
6383 | { |
6384 | s = "sd"; | |
6385 | goto st; | |
6386 | } | |
6387 | ||
6388 | s = "sw"; | |
6389 | fmt = "t,o(b)"; | |
6390 | ||
6391 | ldd_std: | |
6392 | if (offset_expr.X_op != O_symbol | |
6393 | && offset_expr.X_op != O_constant) | |
6394 | { | |
6395 | as_bad (_("expression too complex")); | |
6396 | offset_expr.X_op = O_constant; | |
6397 | } | |
6398 | ||
6399 | /* Even on a big endian machine $fn comes before $fn+1. We have | |
6400 | to adjust when loading from memory. We set coproc if we must | |
6401 | load $fn+1 first. */ | |
bdaaa2e1 | 6402 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6403 | if (! target_big_endian) |
6404 | coproc = 0; | |
6405 | ||
6406 | if (mips_pic == NO_PIC | |
6407 | || offset_expr.X_op == O_constant) | |
6408 | { | |
6409 | /* If this is a reference to a GP relative symbol, we want | |
cdf6fd85 TS |
6410 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
6411 | <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16) | |
252b5132 RH |
6412 | If we have a base register, we use this |
6413 | addu $at,$breg,$gp | |
cdf6fd85 TS |
6414 | <op> $treg,<sym>($at) (BFD_RELOC_GPREL16) |
6415 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16) | |
252b5132 RH |
6416 | If this is not a GP relative symbol, we want |
6417 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
6418 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
6419 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
6420 | If there is a base register, we add it to $at after the | |
6421 | lui instruction. If there is a constant, we always use | |
6422 | the last case. */ | |
6caf9ef4 TS |
6423 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6424 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) | |
252b5132 | 6425 | { |
4d7206a2 | 6426 | relax_start (offset_expr.X_add_symbol); |
252b5132 RH |
6427 | if (breg == 0) |
6428 | { | |
c9914766 | 6429 | tempreg = mips_gp_register; |
252b5132 RH |
6430 | } |
6431 | else | |
6432 | { | |
67c0d1eb | 6433 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6434 | AT, breg, mips_gp_register); |
252b5132 | 6435 | tempreg = AT; |
252b5132 RH |
6436 | used_at = 1; |
6437 | } | |
6438 | ||
beae10d5 | 6439 | /* Itbl support may require additional care here. */ |
67c0d1eb | 6440 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 6441 | BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
6442 | offset_expr.X_add_number += 4; |
6443 | ||
6444 | /* Set mips_optimize to 2 to avoid inserting an | |
6445 | undesired nop. */ | |
6446 | hold_mips_optimize = mips_optimize; | |
6447 | mips_optimize = 2; | |
beae10d5 | 6448 | /* Itbl support may require additional care here. */ |
67c0d1eb | 6449 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 6450 | BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
6451 | mips_optimize = hold_mips_optimize; |
6452 | ||
4d7206a2 | 6453 | relax_switch (); |
252b5132 RH |
6454 | |
6455 | /* We just generated two relocs. When tc_gen_reloc | |
6456 | handles this case, it will skip the first reloc and | |
6457 | handle the second. The second reloc already has an | |
6458 | extra addend of 4, which we added above. We must | |
6459 | subtract it out, and then subtract another 4 to make | |
6460 | the first reloc come out right. The second reloc | |
6461 | will come out right because we are going to add 4 to | |
6462 | offset_expr when we build its instruction below. | |
6463 | ||
6464 | If we have a symbol, then we don't want to include | |
6465 | the offset, because it will wind up being included | |
6466 | when we generate the reloc. */ | |
6467 | ||
6468 | if (offset_expr.X_op == O_constant) | |
6469 | offset_expr.X_add_number -= 8; | |
6470 | else | |
6471 | { | |
6472 | offset_expr.X_add_number = -4; | |
6473 | offset_expr.X_op = O_constant; | |
6474 | } | |
6475 | } | |
8fc2e39e | 6476 | used_at = 1; |
67c0d1eb | 6477 | macro_build_lui (&offset_expr, AT); |
252b5132 | 6478 | if (breg != 0) |
67c0d1eb | 6479 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 6480 | /* Itbl support may require additional care here. */ |
67c0d1eb | 6481 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 6482 | BFD_RELOC_LO16, AT); |
252b5132 RH |
6483 | /* FIXME: How do we handle overflow here? */ |
6484 | offset_expr.X_add_number += 4; | |
beae10d5 | 6485 | /* Itbl support may require additional care here. */ |
67c0d1eb | 6486 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 6487 | BFD_RELOC_LO16, AT); |
4d7206a2 RS |
6488 | if (mips_relax.sequence) |
6489 | relax_end (); | |
bdaaa2e1 | 6490 | } |
252b5132 RH |
6491 | else if (mips_pic == SVR4_PIC && ! mips_big_got) |
6492 | { | |
252b5132 RH |
6493 | /* If this is a reference to an external symbol, we want |
6494 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6495 | nop | |
6496 | <op> $treg,0($at) | |
6497 | <op> $treg+1,4($at) | |
6498 | Otherwise we want | |
6499 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6500 | nop | |
6501 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
6502 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
6503 | If there is a base register we add it to $at before the | |
6504 | lwc1 instructions. If there is a constant we include it | |
6505 | in the lwc1 instructions. */ | |
6506 | used_at = 1; | |
6507 | expr1.X_add_number = offset_expr.X_add_number; | |
252b5132 RH |
6508 | if (expr1.X_add_number < -0x8000 |
6509 | || expr1.X_add_number >= 0x8000 - 4) | |
6510 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 6511 | load_got_offset (AT, &offset_expr); |
269137b2 | 6512 | load_delay_nop (); |
252b5132 | 6513 | if (breg != 0) |
67c0d1eb | 6514 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
252b5132 RH |
6515 | |
6516 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
6517 | nop. */ | |
6518 | hold_mips_optimize = mips_optimize; | |
6519 | mips_optimize = 2; | |
4d7206a2 | 6520 | |
beae10d5 | 6521 | /* Itbl support may require additional care here. */ |
4d7206a2 | 6522 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
6523 | macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg, |
6524 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 6525 | expr1.X_add_number += 4; |
67c0d1eb RS |
6526 | macro_build (&expr1, s, fmt, coproc ? treg : treg + 1, |
6527 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 6528 | relax_switch (); |
67c0d1eb RS |
6529 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
6530 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 6531 | offset_expr.X_add_number += 4; |
67c0d1eb RS |
6532 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
6533 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 6534 | relax_end (); |
252b5132 | 6535 | |
4d7206a2 | 6536 | mips_optimize = hold_mips_optimize; |
252b5132 RH |
6537 | } |
6538 | else if (mips_pic == SVR4_PIC) | |
6539 | { | |
67c0d1eb | 6540 | int gpdelay; |
252b5132 RH |
6541 | |
6542 | /* If this is a reference to an external symbol, we want | |
6543 | lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
6544 | addu $at,$at,$gp | |
6545 | lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16) | |
6546 | nop | |
6547 | <op> $treg,0($at) | |
6548 | <op> $treg+1,4($at) | |
6549 | Otherwise we want | |
6550 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6551 | nop | |
6552 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
6553 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
6554 | If there is a base register we add it to $at before the | |
6555 | lwc1 instructions. If there is a constant we include it | |
6556 | in the lwc1 instructions. */ | |
6557 | used_at = 1; | |
6558 | expr1.X_add_number = offset_expr.X_add_number; | |
6559 | offset_expr.X_add_number = 0; | |
6560 | if (expr1.X_add_number < -0x8000 | |
6561 | || expr1.X_add_number >= 0x8000 - 4) | |
6562 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 6563 | gpdelay = reg_needs_delay (mips_gp_register); |
4d7206a2 | 6564 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
6565 | macro_build (&offset_expr, "lui", "t,u", |
6566 | AT, BFD_RELOC_MIPS_GOT_HI16); | |
6567 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 6568 | AT, AT, mips_gp_register); |
67c0d1eb | 6569 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
17a2f251 | 6570 | AT, BFD_RELOC_MIPS_GOT_LO16, AT); |
269137b2 | 6571 | load_delay_nop (); |
252b5132 | 6572 | if (breg != 0) |
67c0d1eb | 6573 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 6574 | /* Itbl support may require additional care here. */ |
67c0d1eb | 6575 | macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 6576 | BFD_RELOC_LO16, AT); |
252b5132 RH |
6577 | expr1.X_add_number += 4; |
6578 | ||
6579 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
6580 | nop. */ | |
6581 | hold_mips_optimize = mips_optimize; | |
6582 | mips_optimize = 2; | |
beae10d5 | 6583 | /* Itbl support may require additional care here. */ |
67c0d1eb | 6584 | macro_build (&expr1, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 6585 | BFD_RELOC_LO16, AT); |
252b5132 RH |
6586 | mips_optimize = hold_mips_optimize; |
6587 | expr1.X_add_number -= 4; | |
6588 | ||
4d7206a2 RS |
6589 | relax_switch (); |
6590 | offset_expr.X_add_number = expr1.X_add_number; | |
67c0d1eb RS |
6591 | if (gpdelay) |
6592 | macro_build (NULL, "nop", ""); | |
6593 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, | |
6594 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 6595 | load_delay_nop (); |
252b5132 | 6596 | if (breg != 0) |
67c0d1eb | 6597 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 6598 | /* Itbl support may require additional care here. */ |
67c0d1eb RS |
6599 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
6600 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 6601 | offset_expr.X_add_number += 4; |
252b5132 RH |
6602 | |
6603 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
6604 | nop. */ | |
6605 | hold_mips_optimize = mips_optimize; | |
6606 | mips_optimize = 2; | |
beae10d5 | 6607 | /* Itbl support may require additional care here. */ |
67c0d1eb RS |
6608 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
6609 | BFD_RELOC_LO16, AT); | |
252b5132 | 6610 | mips_optimize = hold_mips_optimize; |
4d7206a2 | 6611 | relax_end (); |
252b5132 | 6612 | } |
252b5132 RH |
6613 | else |
6614 | abort (); | |
6615 | ||
252b5132 RH |
6616 | break; |
6617 | ||
6618 | case M_LD_OB: | |
6619 | s = "lw"; | |
6620 | goto sd_ob; | |
6621 | case M_SD_OB: | |
6622 | s = "sw"; | |
6623 | sd_ob: | |
ca4e0257 | 6624 | assert (HAVE_32BIT_ADDRESSES); |
67c0d1eb | 6625 | macro_build (&offset_expr, s, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
252b5132 | 6626 | offset_expr.X_add_number += 4; |
67c0d1eb | 6627 | macro_build (&offset_expr, s, "t,o(b)", treg + 1, BFD_RELOC_LO16, breg); |
8fc2e39e | 6628 | break; |
252b5132 RH |
6629 | |
6630 | /* New code added to support COPZ instructions. | |
6631 | This code builds table entries out of the macros in mip_opcodes. | |
6632 | R4000 uses interlocks to handle coproc delays. | |
6633 | Other chips (like the R3000) require nops to be inserted for delays. | |
6634 | ||
f72c8c98 | 6635 | FIXME: Currently, we require that the user handle delays. |
252b5132 RH |
6636 | In order to fill delay slots for non-interlocked chips, |
6637 | we must have a way to specify delays based on the coprocessor. | |
6638 | Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc. | |
6639 | What are the side-effects of the cop instruction? | |
6640 | What cache support might we have and what are its effects? | |
6641 | Both coprocessor & memory require delays. how long??? | |
bdaaa2e1 | 6642 | What registers are read/set/modified? |
252b5132 RH |
6643 | |
6644 | If an itbl is provided to interpret cop instructions, | |
bdaaa2e1 | 6645 | this knowledge can be encoded in the itbl spec. */ |
252b5132 RH |
6646 | |
6647 | case M_COP0: | |
6648 | s = "c0"; | |
6649 | goto copz; | |
6650 | case M_COP1: | |
6651 | s = "c1"; | |
6652 | goto copz; | |
6653 | case M_COP2: | |
6654 | s = "c2"; | |
6655 | goto copz; | |
6656 | case M_COP3: | |
6657 | s = "c3"; | |
6658 | copz: | |
6659 | /* For now we just do C (same as Cz). The parameter will be | |
6660 | stored in insn_opcode by mips_ip. */ | |
67c0d1eb | 6661 | macro_build (NULL, s, "C", ip->insn_opcode); |
8fc2e39e | 6662 | break; |
252b5132 | 6663 | |
ea1fb5dc | 6664 | case M_MOVE: |
67c0d1eb | 6665 | move_register (dreg, sreg); |
8fc2e39e | 6666 | break; |
ea1fb5dc | 6667 | |
252b5132 RH |
6668 | #ifdef LOSING_COMPILER |
6669 | default: | |
6670 | /* Try and see if this is a new itbl instruction. | |
6671 | This code builds table entries out of the macros in mip_opcodes. | |
6672 | FIXME: For now we just assemble the expression and pass it's | |
6673 | value along as a 32-bit immediate. | |
bdaaa2e1 | 6674 | We may want to have the assembler assemble this value, |
252b5132 RH |
6675 | so that we gain the assembler's knowledge of delay slots, |
6676 | symbols, etc. | |
6677 | Would it be more efficient to use mask (id) here? */ | |
bdaaa2e1 | 6678 | if (itbl_have_entries |
252b5132 | 6679 | && (immed_expr = itbl_assemble (ip->insn_mo->name, ""))) |
beae10d5 | 6680 | { |
252b5132 RH |
6681 | s = ip->insn_mo->name; |
6682 | s2 = "cop3"; | |
6683 | coproc = ITBL_DECODE_PNUM (immed_expr);; | |
67c0d1eb | 6684 | macro_build (&immed_expr, s, "C"); |
8fc2e39e | 6685 | break; |
beae10d5 | 6686 | } |
252b5132 | 6687 | macro2 (ip); |
8fc2e39e | 6688 | break; |
252b5132 | 6689 | } |
8fc2e39e TS |
6690 | if (mips_opts.noat && used_at) |
6691 | as_bad (_("Macro used $at after \".set noat\"")); | |
252b5132 | 6692 | } |
bdaaa2e1 | 6693 | |
252b5132 | 6694 | static void |
17a2f251 | 6695 | macro2 (struct mips_cl_insn *ip) |
252b5132 RH |
6696 | { |
6697 | register int treg, sreg, dreg, breg; | |
6698 | int tempreg; | |
6699 | int mask; | |
252b5132 RH |
6700 | int used_at; |
6701 | expressionS expr1; | |
6702 | const char *s; | |
6703 | const char *s2; | |
6704 | const char *fmt; | |
6705 | int likely = 0; | |
6706 | int dbl = 0; | |
6707 | int coproc = 0; | |
6708 | int lr = 0; | |
6709 | int imm = 0; | |
6710 | int off; | |
6711 | offsetT maxnum; | |
6712 | bfd_reloc_code_real_type r; | |
bdaaa2e1 | 6713 | |
252b5132 RH |
6714 | treg = (ip->insn_opcode >> 16) & 0x1f; |
6715 | dreg = (ip->insn_opcode >> 11) & 0x1f; | |
6716 | sreg = breg = (ip->insn_opcode >> 21) & 0x1f; | |
6717 | mask = ip->insn_mo->mask; | |
bdaaa2e1 | 6718 | |
252b5132 RH |
6719 | expr1.X_op = O_constant; |
6720 | expr1.X_op_symbol = NULL; | |
6721 | expr1.X_add_symbol = NULL; | |
6722 | expr1.X_add_number = 1; | |
bdaaa2e1 | 6723 | |
252b5132 RH |
6724 | switch (mask) |
6725 | { | |
6726 | #endif /* LOSING_COMPILER */ | |
6727 | ||
6728 | case M_DMUL: | |
6729 | dbl = 1; | |
6730 | case M_MUL: | |
67c0d1eb RS |
6731 | macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", sreg, treg); |
6732 | macro_build (NULL, "mflo", "d", dreg); | |
8fc2e39e | 6733 | break; |
252b5132 RH |
6734 | |
6735 | case M_DMUL_I: | |
6736 | dbl = 1; | |
6737 | case M_MUL_I: | |
6738 | /* The MIPS assembler some times generates shifts and adds. I'm | |
6739 | not trying to be that fancy. GCC should do this for us | |
6740 | anyway. */ | |
8fc2e39e | 6741 | used_at = 1; |
67c0d1eb RS |
6742 | load_register (AT, &imm_expr, dbl); |
6743 | macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, AT); | |
6744 | macro_build (NULL, "mflo", "d", dreg); | |
252b5132 RH |
6745 | break; |
6746 | ||
6747 | case M_DMULO_I: | |
6748 | dbl = 1; | |
6749 | case M_MULO_I: | |
6750 | imm = 1; | |
6751 | goto do_mulo; | |
6752 | ||
6753 | case M_DMULO: | |
6754 | dbl = 1; | |
6755 | case M_MULO: | |
6756 | do_mulo: | |
b34976b6 | 6757 | mips_emit_delays (TRUE); |
252b5132 RH |
6758 | ++mips_opts.noreorder; |
6759 | mips_any_noreorder = 1; | |
8fc2e39e | 6760 | used_at = 1; |
252b5132 | 6761 | if (imm) |
67c0d1eb RS |
6762 | load_register (AT, &imm_expr, dbl); |
6763 | macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, imm ? AT : treg); | |
6764 | macro_build (NULL, "mflo", "d", dreg); | |
6765 | macro_build (NULL, dbl ? "dsra32" : "sra", "d,w,<", dreg, dreg, RA); | |
6766 | macro_build (NULL, "mfhi", "d", AT); | |
252b5132 | 6767 | if (mips_trap) |
67c0d1eb | 6768 | macro_build (NULL, "tne", "s,t,q", dreg, AT, 6); |
252b5132 RH |
6769 | else |
6770 | { | |
6771 | expr1.X_add_number = 8; | |
67c0d1eb RS |
6772 | macro_build (&expr1, "beq", "s,t,p", dreg, AT); |
6773 | macro_build (NULL, "nop", "", 0); | |
6774 | macro_build (NULL, "break", "c", 6); | |
252b5132 RH |
6775 | } |
6776 | --mips_opts.noreorder; | |
67c0d1eb | 6777 | macro_build (NULL, "mflo", "d", dreg); |
252b5132 RH |
6778 | break; |
6779 | ||
6780 | case M_DMULOU_I: | |
6781 | dbl = 1; | |
6782 | case M_MULOU_I: | |
6783 | imm = 1; | |
6784 | goto do_mulou; | |
6785 | ||
6786 | case M_DMULOU: | |
6787 | dbl = 1; | |
6788 | case M_MULOU: | |
6789 | do_mulou: | |
b34976b6 | 6790 | mips_emit_delays (TRUE); |
252b5132 RH |
6791 | ++mips_opts.noreorder; |
6792 | mips_any_noreorder = 1; | |
8fc2e39e | 6793 | used_at = 1; |
252b5132 | 6794 | if (imm) |
67c0d1eb RS |
6795 | load_register (AT, &imm_expr, dbl); |
6796 | macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", | |
17a2f251 | 6797 | sreg, imm ? AT : treg); |
67c0d1eb RS |
6798 | macro_build (NULL, "mfhi", "d", AT); |
6799 | macro_build (NULL, "mflo", "d", dreg); | |
252b5132 | 6800 | if (mips_trap) |
67c0d1eb | 6801 | macro_build (NULL, "tne", "s,t,q", AT, 0, 6); |
252b5132 RH |
6802 | else |
6803 | { | |
6804 | expr1.X_add_number = 8; | |
67c0d1eb RS |
6805 | macro_build (&expr1, "beq", "s,t,p", AT, 0); |
6806 | macro_build (NULL, "nop", "", 0); | |
6807 | macro_build (NULL, "break", "c", 6); | |
252b5132 RH |
6808 | } |
6809 | --mips_opts.noreorder; | |
6810 | break; | |
6811 | ||
771c7ce4 | 6812 | case M_DROL: |
fef14a42 | 6813 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 CD |
6814 | { |
6815 | if (dreg == sreg) | |
6816 | { | |
6817 | tempreg = AT; | |
6818 | used_at = 1; | |
6819 | } | |
6820 | else | |
6821 | { | |
6822 | tempreg = dreg; | |
82dd0097 | 6823 | } |
67c0d1eb RS |
6824 | macro_build (NULL, "dnegu", "d,w", tempreg, treg); |
6825 | macro_build (NULL, "drorv", "d,t,s", dreg, sreg, tempreg); | |
8fc2e39e | 6826 | break; |
82dd0097 | 6827 | } |
8fc2e39e | 6828 | used_at = 1; |
67c0d1eb RS |
6829 | macro_build (NULL, "dsubu", "d,v,t", AT, 0, treg); |
6830 | macro_build (NULL, "dsrlv", "d,t,s", AT, sreg, AT); | |
6831 | macro_build (NULL, "dsllv", "d,t,s", dreg, sreg, treg); | |
6832 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
6833 | break; |
6834 | ||
252b5132 | 6835 | case M_ROL: |
fef14a42 | 6836 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 CD |
6837 | { |
6838 | if (dreg == sreg) | |
6839 | { | |
6840 | tempreg = AT; | |
6841 | used_at = 1; | |
6842 | } | |
6843 | else | |
6844 | { | |
6845 | tempreg = dreg; | |
82dd0097 | 6846 | } |
67c0d1eb RS |
6847 | macro_build (NULL, "negu", "d,w", tempreg, treg); |
6848 | macro_build (NULL, "rorv", "d,t,s", dreg, sreg, tempreg); | |
8fc2e39e | 6849 | break; |
82dd0097 | 6850 | } |
8fc2e39e | 6851 | used_at = 1; |
67c0d1eb RS |
6852 | macro_build (NULL, "subu", "d,v,t", AT, 0, treg); |
6853 | macro_build (NULL, "srlv", "d,t,s", AT, sreg, AT); | |
6854 | macro_build (NULL, "sllv", "d,t,s", dreg, sreg, treg); | |
6855 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
6856 | break; |
6857 | ||
771c7ce4 TS |
6858 | case M_DROL_I: |
6859 | { | |
6860 | unsigned int rot; | |
82dd0097 | 6861 | char *l, *r; |
771c7ce4 TS |
6862 | |
6863 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 6864 | as_bad (_("Improper rotate count")); |
771c7ce4 | 6865 | rot = imm_expr.X_add_number & 0x3f; |
fef14a42 | 6866 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
60b63b72 RS |
6867 | { |
6868 | rot = (64 - rot) & 0x3f; | |
6869 | if (rot >= 32) | |
67c0d1eb | 6870 | macro_build (NULL, "dror32", "d,w,<", dreg, sreg, rot - 32); |
60b63b72 | 6871 | else |
67c0d1eb | 6872 | macro_build (NULL, "dror", "d,w,<", dreg, sreg, rot); |
8fc2e39e | 6873 | break; |
60b63b72 | 6874 | } |
483fc7cd | 6875 | if (rot == 0) |
483fc7cd | 6876 | { |
67c0d1eb | 6877 | macro_build (NULL, "dsrl", "d,w,<", dreg, sreg, 0); |
8fc2e39e | 6878 | break; |
483fc7cd | 6879 | } |
82dd0097 CD |
6880 | l = (rot < 0x20) ? "dsll" : "dsll32"; |
6881 | r = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32"; | |
6882 | rot &= 0x1f; | |
8fc2e39e | 6883 | used_at = 1; |
67c0d1eb RS |
6884 | macro_build (NULL, l, "d,w,<", AT, sreg, rot); |
6885 | macro_build (NULL, r, "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); | |
6886 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
6887 | } |
6888 | break; | |
6889 | ||
252b5132 | 6890 | case M_ROL_I: |
771c7ce4 TS |
6891 | { |
6892 | unsigned int rot; | |
6893 | ||
6894 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 6895 | as_bad (_("Improper rotate count")); |
771c7ce4 | 6896 | rot = imm_expr.X_add_number & 0x1f; |
fef14a42 | 6897 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
60b63b72 | 6898 | { |
67c0d1eb | 6899 | macro_build (NULL, "ror", "d,w,<", dreg, sreg, (32 - rot) & 0x1f); |
8fc2e39e | 6900 | break; |
60b63b72 | 6901 | } |
483fc7cd | 6902 | if (rot == 0) |
483fc7cd | 6903 | { |
67c0d1eb | 6904 | macro_build (NULL, "srl", "d,w,<", dreg, sreg, 0); |
8fc2e39e | 6905 | break; |
483fc7cd | 6906 | } |
8fc2e39e | 6907 | used_at = 1; |
67c0d1eb RS |
6908 | macro_build (NULL, "sll", "d,w,<", AT, sreg, rot); |
6909 | macro_build (NULL, "srl", "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); | |
6910 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
6911 | } |
6912 | break; | |
6913 | ||
6914 | case M_DROR: | |
fef14a42 | 6915 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 | 6916 | { |
67c0d1eb | 6917 | macro_build (NULL, "drorv", "d,t,s", dreg, sreg, treg); |
8fc2e39e | 6918 | break; |
82dd0097 | 6919 | } |
8fc2e39e | 6920 | used_at = 1; |
67c0d1eb RS |
6921 | macro_build (NULL, "dsubu", "d,v,t", AT, 0, treg); |
6922 | macro_build (NULL, "dsllv", "d,t,s", AT, sreg, AT); | |
6923 | macro_build (NULL, "dsrlv", "d,t,s", dreg, sreg, treg); | |
6924 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
6925 | break; |
6926 | ||
6927 | case M_ROR: | |
fef14a42 | 6928 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 | 6929 | { |
67c0d1eb | 6930 | macro_build (NULL, "rorv", "d,t,s", dreg, sreg, treg); |
8fc2e39e | 6931 | break; |
82dd0097 | 6932 | } |
8fc2e39e | 6933 | used_at = 1; |
67c0d1eb RS |
6934 | macro_build (NULL, "subu", "d,v,t", AT, 0, treg); |
6935 | macro_build (NULL, "sllv", "d,t,s", AT, sreg, AT); | |
6936 | macro_build (NULL, "srlv", "d,t,s", dreg, sreg, treg); | |
6937 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
6938 | break; |
6939 | ||
771c7ce4 TS |
6940 | case M_DROR_I: |
6941 | { | |
6942 | unsigned int rot; | |
82dd0097 | 6943 | char *l, *r; |
771c7ce4 TS |
6944 | |
6945 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 6946 | as_bad (_("Improper rotate count")); |
771c7ce4 | 6947 | rot = imm_expr.X_add_number & 0x3f; |
fef14a42 | 6948 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 CD |
6949 | { |
6950 | if (rot >= 32) | |
67c0d1eb | 6951 | macro_build (NULL, "dror32", "d,w,<", dreg, sreg, rot - 32); |
82dd0097 | 6952 | else |
67c0d1eb | 6953 | macro_build (NULL, "dror", "d,w,<", dreg, sreg, rot); |
8fc2e39e | 6954 | break; |
82dd0097 | 6955 | } |
483fc7cd | 6956 | if (rot == 0) |
483fc7cd | 6957 | { |
67c0d1eb | 6958 | macro_build (NULL, "dsrl", "d,w,<", dreg, sreg, 0); |
8fc2e39e | 6959 | break; |
483fc7cd | 6960 | } |
82dd0097 CD |
6961 | r = (rot < 0x20) ? "dsrl" : "dsrl32"; |
6962 | l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32"; | |
6963 | rot &= 0x1f; | |
8fc2e39e | 6964 | used_at = 1; |
67c0d1eb RS |
6965 | macro_build (NULL, r, "d,w,<", AT, sreg, rot); |
6966 | macro_build (NULL, l, "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); | |
6967 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
6968 | } |
6969 | break; | |
6970 | ||
252b5132 | 6971 | case M_ROR_I: |
771c7ce4 TS |
6972 | { |
6973 | unsigned int rot; | |
6974 | ||
6975 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 6976 | as_bad (_("Improper rotate count")); |
771c7ce4 | 6977 | rot = imm_expr.X_add_number & 0x1f; |
fef14a42 | 6978 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 | 6979 | { |
67c0d1eb | 6980 | macro_build (NULL, "ror", "d,w,<", dreg, sreg, rot); |
8fc2e39e | 6981 | break; |
82dd0097 | 6982 | } |
483fc7cd | 6983 | if (rot == 0) |
483fc7cd | 6984 | { |
67c0d1eb | 6985 | macro_build (NULL, "srl", "d,w,<", dreg, sreg, 0); |
8fc2e39e | 6986 | break; |
483fc7cd | 6987 | } |
8fc2e39e | 6988 | used_at = 1; |
67c0d1eb RS |
6989 | macro_build (NULL, "srl", "d,w,<", AT, sreg, rot); |
6990 | macro_build (NULL, "sll", "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); | |
6991 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 | 6992 | } |
252b5132 RH |
6993 | break; |
6994 | ||
6995 | case M_S_DOB: | |
fef14a42 | 6996 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
6997 | { |
6998 | as_bad (_("opcode not supported on this processor")); | |
8fc2e39e | 6999 | break; |
252b5132 | 7000 | } |
e7af610e | 7001 | assert (mips_opts.isa == ISA_MIPS1); |
252b5132 RH |
7002 | /* Even on a big endian machine $fn comes before $fn+1. We have |
7003 | to adjust when storing to memory. */ | |
67c0d1eb RS |
7004 | macro_build (&offset_expr, "swc1", "T,o(b)", |
7005 | target_big_endian ? treg + 1 : treg, BFD_RELOC_LO16, breg); | |
252b5132 | 7006 | offset_expr.X_add_number += 4; |
67c0d1eb RS |
7007 | macro_build (&offset_expr, "swc1", "T,o(b)", |
7008 | target_big_endian ? treg : treg + 1, BFD_RELOC_LO16, breg); | |
8fc2e39e | 7009 | break; |
252b5132 RH |
7010 | |
7011 | case M_SEQ: | |
7012 | if (sreg == 0) | |
67c0d1eb | 7013 | macro_build (&expr1, "sltiu", "t,r,j", dreg, treg, BFD_RELOC_LO16); |
252b5132 | 7014 | else if (treg == 0) |
67c0d1eb | 7015 | macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7016 | else |
7017 | { | |
67c0d1eb RS |
7018 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg); |
7019 | macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16); | |
252b5132 | 7020 | } |
8fc2e39e | 7021 | break; |
252b5132 RH |
7022 | |
7023 | case M_SEQ_I: | |
7024 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
7025 | { | |
67c0d1eb | 7026 | macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 7027 | break; |
252b5132 RH |
7028 | } |
7029 | if (sreg == 0) | |
7030 | { | |
7031 | as_warn (_("Instruction %s: result is always false"), | |
7032 | ip->insn_mo->name); | |
67c0d1eb | 7033 | move_register (dreg, 0); |
8fc2e39e | 7034 | break; |
252b5132 RH |
7035 | } |
7036 | if (imm_expr.X_op == O_constant | |
7037 | && imm_expr.X_add_number >= 0 | |
7038 | && imm_expr.X_add_number < 0x10000) | |
7039 | { | |
67c0d1eb | 7040 | macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7041 | } |
7042 | else if (imm_expr.X_op == O_constant | |
7043 | && imm_expr.X_add_number > -0x8000 | |
7044 | && imm_expr.X_add_number < 0) | |
7045 | { | |
7046 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 7047 | macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu", |
17a2f251 | 7048 | "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7049 | } |
7050 | else | |
7051 | { | |
67c0d1eb RS |
7052 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7053 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7054 | used_at = 1; |
7055 | } | |
67c0d1eb | 7056 | macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16); |
8fc2e39e | 7057 | break; |
252b5132 RH |
7058 | |
7059 | case M_SGE: /* sreg >= treg <==> not (sreg < treg) */ | |
7060 | s = "slt"; | |
7061 | goto sge; | |
7062 | case M_SGEU: | |
7063 | s = "sltu"; | |
7064 | sge: | |
67c0d1eb RS |
7065 | macro_build (NULL, s, "d,v,t", dreg, sreg, treg); |
7066 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
8fc2e39e | 7067 | break; |
252b5132 RH |
7068 | |
7069 | case M_SGE_I: /* sreg >= I <==> not (sreg < I) */ | |
7070 | case M_SGEU_I: | |
7071 | if (imm_expr.X_op == O_constant | |
7072 | && imm_expr.X_add_number >= -0x8000 | |
7073 | && imm_expr.X_add_number < 0x8000) | |
7074 | { | |
67c0d1eb RS |
7075 | macro_build (&imm_expr, mask == M_SGE_I ? "slti" : "sltiu", "t,r,j", |
7076 | dreg, sreg, BFD_RELOC_LO16); | |
252b5132 RH |
7077 | } |
7078 | else | |
7079 | { | |
67c0d1eb RS |
7080 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7081 | macro_build (NULL, mask == M_SGE_I ? "slt" : "sltu", "d,v,t", | |
7082 | dreg, sreg, AT); | |
252b5132 RH |
7083 | used_at = 1; |
7084 | } | |
67c0d1eb | 7085 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); |
8fc2e39e | 7086 | break; |
252b5132 RH |
7087 | |
7088 | case M_SGT: /* sreg > treg <==> treg < sreg */ | |
7089 | s = "slt"; | |
7090 | goto sgt; | |
7091 | case M_SGTU: | |
7092 | s = "sltu"; | |
7093 | sgt: | |
67c0d1eb | 7094 | macro_build (NULL, s, "d,v,t", dreg, treg, sreg); |
8fc2e39e | 7095 | break; |
252b5132 RH |
7096 | |
7097 | case M_SGT_I: /* sreg > I <==> I < sreg */ | |
7098 | s = "slt"; | |
7099 | goto sgti; | |
7100 | case M_SGTU_I: | |
7101 | s = "sltu"; | |
7102 | sgti: | |
8fc2e39e | 7103 | used_at = 1; |
67c0d1eb RS |
7104 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7105 | macro_build (NULL, s, "d,v,t", dreg, AT, sreg); | |
252b5132 RH |
7106 | break; |
7107 | ||
2396cfb9 | 7108 | case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */ |
252b5132 RH |
7109 | s = "slt"; |
7110 | goto sle; | |
7111 | case M_SLEU: | |
7112 | s = "sltu"; | |
7113 | sle: | |
67c0d1eb RS |
7114 | macro_build (NULL, s, "d,v,t", dreg, treg, sreg); |
7115 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
8fc2e39e | 7116 | break; |
252b5132 | 7117 | |
2396cfb9 | 7118 | case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */ |
252b5132 RH |
7119 | s = "slt"; |
7120 | goto slei; | |
7121 | case M_SLEU_I: | |
7122 | s = "sltu"; | |
7123 | slei: | |
8fc2e39e | 7124 | used_at = 1; |
67c0d1eb RS |
7125 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7126 | macro_build (NULL, s, "d,v,t", dreg, AT, sreg); | |
7127 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
252b5132 RH |
7128 | break; |
7129 | ||
7130 | case M_SLT_I: | |
7131 | if (imm_expr.X_op == O_constant | |
7132 | && imm_expr.X_add_number >= -0x8000 | |
7133 | && imm_expr.X_add_number < 0x8000) | |
7134 | { | |
67c0d1eb | 7135 | macro_build (&imm_expr, "slti", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 7136 | break; |
252b5132 | 7137 | } |
8fc2e39e | 7138 | used_at = 1; |
67c0d1eb RS |
7139 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7140 | macro_build (NULL, "slt", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7141 | break; |
7142 | ||
7143 | case M_SLTU_I: | |
7144 | if (imm_expr.X_op == O_constant | |
7145 | && imm_expr.X_add_number >= -0x8000 | |
7146 | && imm_expr.X_add_number < 0x8000) | |
7147 | { | |
67c0d1eb | 7148 | macro_build (&imm_expr, "sltiu", "t,r,j", dreg, sreg, |
17a2f251 | 7149 | BFD_RELOC_LO16); |
8fc2e39e | 7150 | break; |
252b5132 | 7151 | } |
8fc2e39e | 7152 | used_at = 1; |
67c0d1eb RS |
7153 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7154 | macro_build (NULL, "sltu", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7155 | break; |
7156 | ||
7157 | case M_SNE: | |
7158 | if (sreg == 0) | |
67c0d1eb | 7159 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, treg); |
252b5132 | 7160 | else if (treg == 0) |
67c0d1eb | 7161 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg); |
252b5132 RH |
7162 | else |
7163 | { | |
67c0d1eb RS |
7164 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg); |
7165 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg); | |
252b5132 | 7166 | } |
8fc2e39e | 7167 | break; |
252b5132 RH |
7168 | |
7169 | case M_SNE_I: | |
7170 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
7171 | { | |
67c0d1eb | 7172 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg); |
8fc2e39e | 7173 | break; |
252b5132 RH |
7174 | } |
7175 | if (sreg == 0) | |
7176 | { | |
7177 | as_warn (_("Instruction %s: result is always true"), | |
7178 | ip->insn_mo->name); | |
67c0d1eb RS |
7179 | macro_build (&expr1, HAVE_32BIT_GPRS ? "addiu" : "daddiu", "t,r,j", |
7180 | dreg, 0, BFD_RELOC_LO16); | |
8fc2e39e | 7181 | break; |
252b5132 RH |
7182 | } |
7183 | if (imm_expr.X_op == O_constant | |
7184 | && imm_expr.X_add_number >= 0 | |
7185 | && imm_expr.X_add_number < 0x10000) | |
7186 | { | |
67c0d1eb | 7187 | macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7188 | } |
7189 | else if (imm_expr.X_op == O_constant | |
7190 | && imm_expr.X_add_number > -0x8000 | |
7191 | && imm_expr.X_add_number < 0) | |
7192 | { | |
7193 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 7194 | macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu", |
17a2f251 | 7195 | "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7196 | } |
7197 | else | |
7198 | { | |
67c0d1eb RS |
7199 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7200 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7201 | used_at = 1; |
7202 | } | |
67c0d1eb | 7203 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg); |
8fc2e39e | 7204 | break; |
252b5132 RH |
7205 | |
7206 | case M_DSUB_I: | |
7207 | dbl = 1; | |
7208 | case M_SUB_I: | |
7209 | if (imm_expr.X_op == O_constant | |
7210 | && imm_expr.X_add_number > -0x8000 | |
7211 | && imm_expr.X_add_number <= 0x8000) | |
7212 | { | |
7213 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb RS |
7214 | macro_build (&imm_expr, dbl ? "daddi" : "addi", "t,r,j", |
7215 | dreg, sreg, BFD_RELOC_LO16); | |
8fc2e39e | 7216 | break; |
252b5132 | 7217 | } |
8fc2e39e | 7218 | used_at = 1; |
67c0d1eb RS |
7219 | load_register (AT, &imm_expr, dbl); |
7220 | macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7221 | break; |
7222 | ||
7223 | case M_DSUBU_I: | |
7224 | dbl = 1; | |
7225 | case M_SUBU_I: | |
7226 | if (imm_expr.X_op == O_constant | |
7227 | && imm_expr.X_add_number > -0x8000 | |
7228 | && imm_expr.X_add_number <= 0x8000) | |
7229 | { | |
7230 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb RS |
7231 | macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "t,r,j", |
7232 | dreg, sreg, BFD_RELOC_LO16); | |
8fc2e39e | 7233 | break; |
252b5132 | 7234 | } |
8fc2e39e | 7235 | used_at = 1; |
67c0d1eb RS |
7236 | load_register (AT, &imm_expr, dbl); |
7237 | macro_build (NULL, dbl ? "dsubu" : "subu", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7238 | break; |
7239 | ||
7240 | case M_TEQ_I: | |
7241 | s = "teq"; | |
7242 | goto trap; | |
7243 | case M_TGE_I: | |
7244 | s = "tge"; | |
7245 | goto trap; | |
7246 | case M_TGEU_I: | |
7247 | s = "tgeu"; | |
7248 | goto trap; | |
7249 | case M_TLT_I: | |
7250 | s = "tlt"; | |
7251 | goto trap; | |
7252 | case M_TLTU_I: | |
7253 | s = "tltu"; | |
7254 | goto trap; | |
7255 | case M_TNE_I: | |
7256 | s = "tne"; | |
7257 | trap: | |
8fc2e39e | 7258 | used_at = 1; |
67c0d1eb RS |
7259 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7260 | macro_build (NULL, s, "s,t", sreg, AT); | |
252b5132 RH |
7261 | break; |
7262 | ||
252b5132 | 7263 | case M_TRUNCWS: |
43841e91 | 7264 | case M_TRUNCWD: |
e7af610e | 7265 | assert (mips_opts.isa == ISA_MIPS1); |
8fc2e39e | 7266 | used_at = 1; |
252b5132 RH |
7267 | sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */ |
7268 | dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */ | |
7269 | ||
7270 | /* | |
7271 | * Is the double cfc1 instruction a bug in the mips assembler; | |
7272 | * or is there a reason for it? | |
7273 | */ | |
b34976b6 | 7274 | mips_emit_delays (TRUE); |
252b5132 RH |
7275 | ++mips_opts.noreorder; |
7276 | mips_any_noreorder = 1; | |
67c0d1eb RS |
7277 | macro_build (NULL, "cfc1", "t,G", treg, RA); |
7278 | macro_build (NULL, "cfc1", "t,G", treg, RA); | |
7279 | macro_build (NULL, "nop", ""); | |
252b5132 | 7280 | expr1.X_add_number = 3; |
67c0d1eb | 7281 | macro_build (&expr1, "ori", "t,r,i", AT, treg, BFD_RELOC_LO16); |
252b5132 | 7282 | expr1.X_add_number = 2; |
67c0d1eb RS |
7283 | macro_build (&expr1, "xori", "t,r,i", AT, AT, BFD_RELOC_LO16); |
7284 | macro_build (NULL, "ctc1", "t,G", AT, RA); | |
7285 | macro_build (NULL, "nop", ""); | |
7286 | macro_build (NULL, mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S", | |
7287 | dreg, sreg); | |
7288 | macro_build (NULL, "ctc1", "t,G", treg, RA); | |
7289 | macro_build (NULL, "nop", ""); | |
252b5132 RH |
7290 | --mips_opts.noreorder; |
7291 | break; | |
7292 | ||
7293 | case M_ULH: | |
7294 | s = "lb"; | |
7295 | goto ulh; | |
7296 | case M_ULHU: | |
7297 | s = "lbu"; | |
7298 | ulh: | |
8fc2e39e | 7299 | used_at = 1; |
252b5132 RH |
7300 | if (offset_expr.X_add_number >= 0x7fff) |
7301 | as_bad (_("operand overflow")); | |
252b5132 | 7302 | if (! target_big_endian) |
f9419b05 | 7303 | ++offset_expr.X_add_number; |
67c0d1eb | 7304 | macro_build (&offset_expr, s, "t,o(b)", AT, BFD_RELOC_LO16, breg); |
252b5132 | 7305 | if (! target_big_endian) |
f9419b05 | 7306 | --offset_expr.X_add_number; |
252b5132 | 7307 | else |
f9419b05 | 7308 | ++offset_expr.X_add_number; |
67c0d1eb RS |
7309 | macro_build (&offset_expr, "lbu", "t,o(b)", treg, BFD_RELOC_LO16, breg); |
7310 | macro_build (NULL, "sll", "d,w,<", AT, AT, 8); | |
7311 | macro_build (NULL, "or", "d,v,t", treg, treg, AT); | |
252b5132 RH |
7312 | break; |
7313 | ||
7314 | case M_ULD: | |
7315 | s = "ldl"; | |
7316 | s2 = "ldr"; | |
7317 | off = 7; | |
7318 | goto ulw; | |
7319 | case M_ULW: | |
7320 | s = "lwl"; | |
7321 | s2 = "lwr"; | |
7322 | off = 3; | |
7323 | ulw: | |
7324 | if (offset_expr.X_add_number >= 0x8000 - off) | |
7325 | as_bad (_("operand overflow")); | |
af22f5b2 CD |
7326 | if (treg != breg) |
7327 | tempreg = treg; | |
7328 | else | |
8fc2e39e TS |
7329 | { |
7330 | used_at = 1; | |
7331 | tempreg = AT; | |
7332 | } | |
252b5132 RH |
7333 | if (! target_big_endian) |
7334 | offset_expr.X_add_number += off; | |
67c0d1eb | 7335 | macro_build (&offset_expr, s, "t,o(b)", tempreg, BFD_RELOC_LO16, breg); |
252b5132 RH |
7336 | if (! target_big_endian) |
7337 | offset_expr.X_add_number -= off; | |
7338 | else | |
7339 | offset_expr.X_add_number += off; | |
67c0d1eb | 7340 | macro_build (&offset_expr, s2, "t,o(b)", tempreg, BFD_RELOC_LO16, breg); |
af22f5b2 CD |
7341 | |
7342 | /* If necessary, move the result in tempreg the final destination. */ | |
7343 | if (treg == tempreg) | |
8fc2e39e | 7344 | break; |
af22f5b2 | 7345 | /* Protect second load's delay slot. */ |
017315e4 | 7346 | load_delay_nop (); |
67c0d1eb | 7347 | move_register (treg, tempreg); |
af22f5b2 | 7348 | break; |
252b5132 RH |
7349 | |
7350 | case M_ULD_A: | |
7351 | s = "ldl"; | |
7352 | s2 = "ldr"; | |
7353 | off = 7; | |
7354 | goto ulwa; | |
7355 | case M_ULW_A: | |
7356 | s = "lwl"; | |
7357 | s2 = "lwr"; | |
7358 | off = 3; | |
7359 | ulwa: | |
d6bc6245 | 7360 | used_at = 1; |
67c0d1eb | 7361 | load_address (AT, &offset_expr, &used_at); |
252b5132 | 7362 | if (breg != 0) |
67c0d1eb | 7363 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); |
252b5132 RH |
7364 | if (! target_big_endian) |
7365 | expr1.X_add_number = off; | |
7366 | else | |
7367 | expr1.X_add_number = 0; | |
67c0d1eb | 7368 | macro_build (&expr1, s, "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
7369 | if (! target_big_endian) |
7370 | expr1.X_add_number = 0; | |
7371 | else | |
7372 | expr1.X_add_number = off; | |
67c0d1eb | 7373 | macro_build (&expr1, s2, "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
7374 | break; |
7375 | ||
7376 | case M_ULH_A: | |
7377 | case M_ULHU_A: | |
d6bc6245 | 7378 | used_at = 1; |
67c0d1eb | 7379 | load_address (AT, &offset_expr, &used_at); |
252b5132 | 7380 | if (breg != 0) |
67c0d1eb | 7381 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); |
252b5132 RH |
7382 | if (target_big_endian) |
7383 | expr1.X_add_number = 0; | |
67c0d1eb | 7384 | macro_build (&expr1, mask == M_ULH_A ? "lb" : "lbu", "t,o(b)", |
17a2f251 | 7385 | treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
7386 | if (target_big_endian) |
7387 | expr1.X_add_number = 1; | |
7388 | else | |
7389 | expr1.X_add_number = 0; | |
67c0d1eb RS |
7390 | macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT); |
7391 | macro_build (NULL, "sll", "d,w,<", treg, treg, 8); | |
7392 | macro_build (NULL, "or", "d,v,t", treg, treg, AT); | |
252b5132 RH |
7393 | break; |
7394 | ||
7395 | case M_USH: | |
8fc2e39e | 7396 | used_at = 1; |
252b5132 RH |
7397 | if (offset_expr.X_add_number >= 0x7fff) |
7398 | as_bad (_("operand overflow")); | |
7399 | if (target_big_endian) | |
f9419b05 | 7400 | ++offset_expr.X_add_number; |
67c0d1eb RS |
7401 | macro_build (&offset_expr, "sb", "t,o(b)", treg, BFD_RELOC_LO16, breg); |
7402 | macro_build (NULL, "srl", "d,w,<", AT, treg, 8); | |
252b5132 | 7403 | if (target_big_endian) |
f9419b05 | 7404 | --offset_expr.X_add_number; |
252b5132 | 7405 | else |
f9419b05 | 7406 | ++offset_expr.X_add_number; |
67c0d1eb | 7407 | macro_build (&offset_expr, "sb", "t,o(b)", AT, BFD_RELOC_LO16, breg); |
252b5132 RH |
7408 | break; |
7409 | ||
7410 | case M_USD: | |
7411 | s = "sdl"; | |
7412 | s2 = "sdr"; | |
7413 | off = 7; | |
7414 | goto usw; | |
7415 | case M_USW: | |
7416 | s = "swl"; | |
7417 | s2 = "swr"; | |
7418 | off = 3; | |
7419 | usw: | |
7420 | if (offset_expr.X_add_number >= 0x8000 - off) | |
7421 | as_bad (_("operand overflow")); | |
7422 | if (! target_big_endian) | |
7423 | offset_expr.X_add_number += off; | |
67c0d1eb | 7424 | macro_build (&offset_expr, s, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
252b5132 RH |
7425 | if (! target_big_endian) |
7426 | offset_expr.X_add_number -= off; | |
7427 | else | |
7428 | offset_expr.X_add_number += off; | |
67c0d1eb | 7429 | macro_build (&offset_expr, s2, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
8fc2e39e | 7430 | break; |
252b5132 RH |
7431 | |
7432 | case M_USD_A: | |
7433 | s = "sdl"; | |
7434 | s2 = "sdr"; | |
7435 | off = 7; | |
7436 | goto uswa; | |
7437 | case M_USW_A: | |
7438 | s = "swl"; | |
7439 | s2 = "swr"; | |
7440 | off = 3; | |
7441 | uswa: | |
d6bc6245 | 7442 | used_at = 1; |
67c0d1eb | 7443 | load_address (AT, &offset_expr, &used_at); |
252b5132 | 7444 | if (breg != 0) |
67c0d1eb | 7445 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); |
252b5132 RH |
7446 | if (! target_big_endian) |
7447 | expr1.X_add_number = off; | |
7448 | else | |
7449 | expr1.X_add_number = 0; | |
67c0d1eb | 7450 | macro_build (&expr1, s, "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
7451 | if (! target_big_endian) |
7452 | expr1.X_add_number = 0; | |
7453 | else | |
7454 | expr1.X_add_number = off; | |
67c0d1eb | 7455 | macro_build (&expr1, s2, "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
7456 | break; |
7457 | ||
7458 | case M_USH_A: | |
d6bc6245 | 7459 | used_at = 1; |
67c0d1eb | 7460 | load_address (AT, &offset_expr, &used_at); |
252b5132 | 7461 | if (breg != 0) |
67c0d1eb | 7462 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); |
252b5132 RH |
7463 | if (! target_big_endian) |
7464 | expr1.X_add_number = 0; | |
67c0d1eb RS |
7465 | macro_build (&expr1, "sb", "t,o(b)", treg, BFD_RELOC_LO16, AT); |
7466 | macro_build (NULL, "srl", "d,w,<", treg, treg, 8); | |
252b5132 RH |
7467 | if (! target_big_endian) |
7468 | expr1.X_add_number = 1; | |
7469 | else | |
7470 | expr1.X_add_number = 0; | |
67c0d1eb | 7471 | macro_build (&expr1, "sb", "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
7472 | if (! target_big_endian) |
7473 | expr1.X_add_number = 0; | |
7474 | else | |
7475 | expr1.X_add_number = 1; | |
67c0d1eb RS |
7476 | macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT); |
7477 | macro_build (NULL, "sll", "d,w,<", treg, treg, 8); | |
7478 | macro_build (NULL, "or", "d,v,t", treg, treg, AT); | |
252b5132 RH |
7479 | break; |
7480 | ||
7481 | default: | |
7482 | /* FIXME: Check if this is one of the itbl macros, since they | |
bdaaa2e1 | 7483 | are added dynamically. */ |
252b5132 RH |
7484 | as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name); |
7485 | break; | |
7486 | } | |
8fc2e39e TS |
7487 | if (mips_opts.noat && used_at) |
7488 | as_bad (_("Macro used $at after \".set noat\"")); | |
252b5132 RH |
7489 | } |
7490 | ||
7491 | /* Implement macros in mips16 mode. */ | |
7492 | ||
7493 | static void | |
17a2f251 | 7494 | mips16_macro (struct mips_cl_insn *ip) |
252b5132 RH |
7495 | { |
7496 | int mask; | |
7497 | int xreg, yreg, zreg, tmp; | |
252b5132 RH |
7498 | expressionS expr1; |
7499 | int dbl; | |
7500 | const char *s, *s2, *s3; | |
7501 | ||
7502 | mask = ip->insn_mo->mask; | |
7503 | ||
bf12938e RS |
7504 | xreg = MIPS16_EXTRACT_OPERAND (RX, *ip); |
7505 | yreg = MIPS16_EXTRACT_OPERAND (RY, *ip); | |
7506 | zreg = MIPS16_EXTRACT_OPERAND (RZ, *ip); | |
252b5132 | 7507 | |
252b5132 RH |
7508 | expr1.X_op = O_constant; |
7509 | expr1.X_op_symbol = NULL; | |
7510 | expr1.X_add_symbol = NULL; | |
7511 | expr1.X_add_number = 1; | |
7512 | ||
7513 | dbl = 0; | |
7514 | ||
7515 | switch (mask) | |
7516 | { | |
7517 | default: | |
7518 | internalError (); | |
7519 | ||
7520 | case M_DDIV_3: | |
7521 | dbl = 1; | |
7522 | case M_DIV_3: | |
7523 | s = "mflo"; | |
7524 | goto do_div3; | |
7525 | case M_DREM_3: | |
7526 | dbl = 1; | |
7527 | case M_REM_3: | |
7528 | s = "mfhi"; | |
7529 | do_div3: | |
b34976b6 | 7530 | mips_emit_delays (TRUE); |
252b5132 RH |
7531 | ++mips_opts.noreorder; |
7532 | mips_any_noreorder = 1; | |
67c0d1eb | 7533 | macro_build (NULL, dbl ? "ddiv" : "div", "0,x,y", xreg, yreg); |
252b5132 | 7534 | expr1.X_add_number = 2; |
67c0d1eb RS |
7535 | macro_build (&expr1, "bnez", "x,p", yreg); |
7536 | macro_build (NULL, "break", "6", 7); | |
bdaaa2e1 | 7537 | |
252b5132 RH |
7538 | /* FIXME: The normal code checks for of -1 / -0x80000000 here, |
7539 | since that causes an overflow. We should do that as well, | |
7540 | but I don't see how to do the comparisons without a temporary | |
7541 | register. */ | |
7542 | --mips_opts.noreorder; | |
67c0d1eb | 7543 | macro_build (NULL, s, "x", zreg); |
252b5132 RH |
7544 | break; |
7545 | ||
7546 | case M_DIVU_3: | |
7547 | s = "divu"; | |
7548 | s2 = "mflo"; | |
7549 | goto do_divu3; | |
7550 | case M_REMU_3: | |
7551 | s = "divu"; | |
7552 | s2 = "mfhi"; | |
7553 | goto do_divu3; | |
7554 | case M_DDIVU_3: | |
7555 | s = "ddivu"; | |
7556 | s2 = "mflo"; | |
7557 | goto do_divu3; | |
7558 | case M_DREMU_3: | |
7559 | s = "ddivu"; | |
7560 | s2 = "mfhi"; | |
7561 | do_divu3: | |
b34976b6 | 7562 | mips_emit_delays (TRUE); |
252b5132 RH |
7563 | ++mips_opts.noreorder; |
7564 | mips_any_noreorder = 1; | |
67c0d1eb | 7565 | macro_build (NULL, s, "0,x,y", xreg, yreg); |
252b5132 | 7566 | expr1.X_add_number = 2; |
67c0d1eb RS |
7567 | macro_build (&expr1, "bnez", "x,p", yreg); |
7568 | macro_build (NULL, "break", "6", 7); | |
252b5132 | 7569 | --mips_opts.noreorder; |
67c0d1eb | 7570 | macro_build (NULL, s2, "x", zreg); |
252b5132 RH |
7571 | break; |
7572 | ||
7573 | case M_DMUL: | |
7574 | dbl = 1; | |
7575 | case M_MUL: | |
67c0d1eb RS |
7576 | macro_build (NULL, dbl ? "dmultu" : "multu", "x,y", xreg, yreg); |
7577 | macro_build (NULL, "mflo", "x", zreg); | |
8fc2e39e | 7578 | break; |
252b5132 RH |
7579 | |
7580 | case M_DSUBU_I: | |
7581 | dbl = 1; | |
7582 | goto do_subu; | |
7583 | case M_SUBU_I: | |
7584 | do_subu: | |
7585 | if (imm_expr.X_op != O_constant) | |
7586 | as_bad (_("Unsupported large constant")); | |
7587 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 7588 | macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "y,x,4", yreg, xreg); |
252b5132 RH |
7589 | break; |
7590 | ||
7591 | case M_SUBU_I_2: | |
7592 | if (imm_expr.X_op != O_constant) | |
7593 | as_bad (_("Unsupported large constant")); | |
7594 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 7595 | macro_build (&imm_expr, "addiu", "x,k", xreg); |
252b5132 RH |
7596 | break; |
7597 | ||
7598 | case M_DSUBU_I_2: | |
7599 | if (imm_expr.X_op != O_constant) | |
7600 | as_bad (_("Unsupported large constant")); | |
7601 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 7602 | macro_build (&imm_expr, "daddiu", "y,j", yreg); |
252b5132 RH |
7603 | break; |
7604 | ||
7605 | case M_BEQ: | |
7606 | s = "cmp"; | |
7607 | s2 = "bteqz"; | |
7608 | goto do_branch; | |
7609 | case M_BNE: | |
7610 | s = "cmp"; | |
7611 | s2 = "btnez"; | |
7612 | goto do_branch; | |
7613 | case M_BLT: | |
7614 | s = "slt"; | |
7615 | s2 = "btnez"; | |
7616 | goto do_branch; | |
7617 | case M_BLTU: | |
7618 | s = "sltu"; | |
7619 | s2 = "btnez"; | |
7620 | goto do_branch; | |
7621 | case M_BLE: | |
7622 | s = "slt"; | |
7623 | s2 = "bteqz"; | |
7624 | goto do_reverse_branch; | |
7625 | case M_BLEU: | |
7626 | s = "sltu"; | |
7627 | s2 = "bteqz"; | |
7628 | goto do_reverse_branch; | |
7629 | case M_BGE: | |
7630 | s = "slt"; | |
7631 | s2 = "bteqz"; | |
7632 | goto do_branch; | |
7633 | case M_BGEU: | |
7634 | s = "sltu"; | |
7635 | s2 = "bteqz"; | |
7636 | goto do_branch; | |
7637 | case M_BGT: | |
7638 | s = "slt"; | |
7639 | s2 = "btnez"; | |
7640 | goto do_reverse_branch; | |
7641 | case M_BGTU: | |
7642 | s = "sltu"; | |
7643 | s2 = "btnez"; | |
7644 | ||
7645 | do_reverse_branch: | |
7646 | tmp = xreg; | |
7647 | xreg = yreg; | |
7648 | yreg = tmp; | |
7649 | ||
7650 | do_branch: | |
67c0d1eb RS |
7651 | macro_build (NULL, s, "x,y", xreg, yreg); |
7652 | macro_build (&offset_expr, s2, "p"); | |
252b5132 RH |
7653 | break; |
7654 | ||
7655 | case M_BEQ_I: | |
7656 | s = "cmpi"; | |
7657 | s2 = "bteqz"; | |
7658 | s3 = "x,U"; | |
7659 | goto do_branch_i; | |
7660 | case M_BNE_I: | |
7661 | s = "cmpi"; | |
7662 | s2 = "btnez"; | |
7663 | s3 = "x,U"; | |
7664 | goto do_branch_i; | |
7665 | case M_BLT_I: | |
7666 | s = "slti"; | |
7667 | s2 = "btnez"; | |
7668 | s3 = "x,8"; | |
7669 | goto do_branch_i; | |
7670 | case M_BLTU_I: | |
7671 | s = "sltiu"; | |
7672 | s2 = "btnez"; | |
7673 | s3 = "x,8"; | |
7674 | goto do_branch_i; | |
7675 | case M_BLE_I: | |
7676 | s = "slti"; | |
7677 | s2 = "btnez"; | |
7678 | s3 = "x,8"; | |
7679 | goto do_addone_branch_i; | |
7680 | case M_BLEU_I: | |
7681 | s = "sltiu"; | |
7682 | s2 = "btnez"; | |
7683 | s3 = "x,8"; | |
7684 | goto do_addone_branch_i; | |
7685 | case M_BGE_I: | |
7686 | s = "slti"; | |
7687 | s2 = "bteqz"; | |
7688 | s3 = "x,8"; | |
7689 | goto do_branch_i; | |
7690 | case M_BGEU_I: | |
7691 | s = "sltiu"; | |
7692 | s2 = "bteqz"; | |
7693 | s3 = "x,8"; | |
7694 | goto do_branch_i; | |
7695 | case M_BGT_I: | |
7696 | s = "slti"; | |
7697 | s2 = "bteqz"; | |
7698 | s3 = "x,8"; | |
7699 | goto do_addone_branch_i; | |
7700 | case M_BGTU_I: | |
7701 | s = "sltiu"; | |
7702 | s2 = "bteqz"; | |
7703 | s3 = "x,8"; | |
7704 | ||
7705 | do_addone_branch_i: | |
7706 | if (imm_expr.X_op != O_constant) | |
7707 | as_bad (_("Unsupported large constant")); | |
7708 | ++imm_expr.X_add_number; | |
7709 | ||
7710 | do_branch_i: | |
67c0d1eb RS |
7711 | macro_build (&imm_expr, s, s3, xreg); |
7712 | macro_build (&offset_expr, s2, "p"); | |
252b5132 RH |
7713 | break; |
7714 | ||
7715 | case M_ABS: | |
7716 | expr1.X_add_number = 0; | |
67c0d1eb | 7717 | macro_build (&expr1, "slti", "x,8", yreg); |
252b5132 | 7718 | if (xreg != yreg) |
67c0d1eb | 7719 | move_register (xreg, yreg); |
252b5132 | 7720 | expr1.X_add_number = 2; |
67c0d1eb RS |
7721 | macro_build (&expr1, "bteqz", "p"); |
7722 | macro_build (NULL, "neg", "x,w", xreg, xreg); | |
252b5132 RH |
7723 | } |
7724 | } | |
7725 | ||
7726 | /* For consistency checking, verify that all bits are specified either | |
7727 | by the match/mask part of the instruction definition, or by the | |
7728 | operand list. */ | |
7729 | static int | |
17a2f251 | 7730 | validate_mips_insn (const struct mips_opcode *opc) |
252b5132 RH |
7731 | { |
7732 | const char *p = opc->args; | |
7733 | char c; | |
7734 | unsigned long used_bits = opc->mask; | |
7735 | ||
7736 | if ((used_bits & opc->match) != opc->match) | |
7737 | { | |
7738 | as_bad (_("internal: bad mips opcode (mask error): %s %s"), | |
7739 | opc->name, opc->args); | |
7740 | return 0; | |
7741 | } | |
7742 | #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift))) | |
7743 | while (*p) | |
7744 | switch (c = *p++) | |
7745 | { | |
7746 | case ',': break; | |
7747 | case '(': break; | |
7748 | case ')': break; | |
af7ee8bf CD |
7749 | case '+': |
7750 | switch (c = *p++) | |
7751 | { | |
7752 | case 'A': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; | |
7753 | case 'B': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break; | |
7754 | case 'C': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
bbcc0807 CD |
7755 | case 'D': USE_BITS (OP_MASK_RD, OP_SH_RD); |
7756 | USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; | |
5f74bc13 CD |
7757 | case 'E': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
7758 | case 'F': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break; | |
7759 | case 'G': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
7760 | case 'H': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
7761 | case 'I': break; | |
af7ee8bf CD |
7762 | default: |
7763 | as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"), | |
7764 | c, opc->name, opc->args); | |
7765 | return 0; | |
7766 | } | |
7767 | break; | |
252b5132 RH |
7768 | case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
7769 | case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; | |
7770 | case 'A': break; | |
4372b673 | 7771 | case 'B': USE_BITS (OP_MASK_CODE20, OP_SH_CODE20); break; |
252b5132 RH |
7772 | case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break; |
7773 | case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break; | |
7774 | case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
7775 | case 'F': break; | |
7776 | case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
156c2f8b | 7777 | case 'H': USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; |
252b5132 | 7778 | case 'I': break; |
e972090a | 7779 | case 'J': USE_BITS (OP_MASK_CODE19, OP_SH_CODE19); break; |
af7ee8bf | 7780 | case 'K': USE_BITS (OP_MASK_RD, OP_SH_RD); break; |
252b5132 RH |
7781 | case 'L': break; |
7782 | case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break; | |
7783 | case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break; | |
deec1734 CD |
7784 | case 'O': USE_BITS (OP_MASK_ALN, OP_SH_ALN); break; |
7785 | case 'Q': USE_BITS (OP_MASK_VSEL, OP_SH_VSEL); | |
7786 | USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
252b5132 RH |
7787 | case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break; |
7788 | case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
7789 | case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
7790 | case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
7791 | case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
deec1734 CD |
7792 | case 'X': USE_BITS (OP_MASK_FD, OP_SH_FD); break; |
7793 | case 'Y': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
7794 | case 'Z': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
252b5132 RH |
7795 | case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break; |
7796 | case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
7797 | case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break; | |
7798 | case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
7799 | case 'f': break; | |
7800 | case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break; | |
7801 | case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; | |
7802 | case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
7803 | case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break; | |
7804 | case 'l': break; | |
7805 | case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
7806 | case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
7807 | case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break; | |
7808 | case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
7809 | case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
7810 | case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
7811 | case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; | |
7812 | case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
7813 | case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
7814 | case 'x': break; | |
7815 | case 'z': break; | |
7816 | case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break; | |
4372b673 NC |
7817 | case 'U': USE_BITS (OP_MASK_RD, OP_SH_RD); |
7818 | USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
60b63b72 RS |
7819 | case 'e': USE_BITS (OP_MASK_VECBYTE, OP_SH_VECBYTE); break; |
7820 | case '%': USE_BITS (OP_MASK_VECALIGN, OP_SH_VECALIGN); break; | |
7821 | case '[': break; | |
7822 | case ']': break; | |
252b5132 RH |
7823 | default: |
7824 | as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"), | |
7825 | c, opc->name, opc->args); | |
7826 | return 0; | |
7827 | } | |
7828 | #undef USE_BITS | |
7829 | if (used_bits != 0xffffffff) | |
7830 | { | |
7831 | as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"), | |
7832 | ~used_bits & 0xffffffff, opc->name, opc->args); | |
7833 | return 0; | |
7834 | } | |
7835 | return 1; | |
7836 | } | |
7837 | ||
7838 | /* This routine assembles an instruction into its binary format. As a | |
7839 | side effect, it sets one of the global variables imm_reloc or | |
7840 | offset_reloc to the type of relocation to do if one of the operands | |
7841 | is an address expression. */ | |
7842 | ||
7843 | static void | |
17a2f251 | 7844 | mips_ip (char *str, struct mips_cl_insn *ip) |
252b5132 RH |
7845 | { |
7846 | char *s; | |
7847 | const char *args; | |
43841e91 | 7848 | char c = 0; |
252b5132 RH |
7849 | struct mips_opcode *insn; |
7850 | char *argsStart; | |
7851 | unsigned int regno; | |
7852 | unsigned int lastregno = 0; | |
af7ee8bf | 7853 | unsigned int lastpos = 0; |
071742cf | 7854 | unsigned int limlo, limhi; |
252b5132 RH |
7855 | char *s_reset; |
7856 | char save_c = 0; | |
252b5132 RH |
7857 | |
7858 | insn_error = NULL; | |
7859 | ||
7860 | /* If the instruction contains a '.', we first try to match an instruction | |
7861 | including the '.'. Then we try again without the '.'. */ | |
7862 | insn = NULL; | |
3882b010 | 7863 | for (s = str; *s != '\0' && !ISSPACE (*s); ++s) |
252b5132 RH |
7864 | continue; |
7865 | ||
7866 | /* If we stopped on whitespace, then replace the whitespace with null for | |
7867 | the call to hash_find. Save the character we replaced just in case we | |
7868 | have to re-parse the instruction. */ | |
3882b010 | 7869 | if (ISSPACE (*s)) |
252b5132 RH |
7870 | { |
7871 | save_c = *s; | |
7872 | *s++ = '\0'; | |
7873 | } | |
bdaaa2e1 | 7874 | |
252b5132 RH |
7875 | insn = (struct mips_opcode *) hash_find (op_hash, str); |
7876 | ||
7877 | /* If we didn't find the instruction in the opcode table, try again, but | |
7878 | this time with just the instruction up to, but not including the | |
7879 | first '.'. */ | |
7880 | if (insn == NULL) | |
7881 | { | |
bdaaa2e1 | 7882 | /* Restore the character we overwrite above (if any). */ |
252b5132 RH |
7883 | if (save_c) |
7884 | *(--s) = save_c; | |
7885 | ||
7886 | /* Scan up to the first '.' or whitespace. */ | |
3882b010 L |
7887 | for (s = str; |
7888 | *s != '\0' && *s != '.' && !ISSPACE (*s); | |
7889 | ++s) | |
252b5132 RH |
7890 | continue; |
7891 | ||
7892 | /* If we did not find a '.', then we can quit now. */ | |
7893 | if (*s != '.') | |
7894 | { | |
7895 | insn_error = "unrecognized opcode"; | |
7896 | return; | |
7897 | } | |
7898 | ||
7899 | /* Lookup the instruction in the hash table. */ | |
7900 | *s++ = '\0'; | |
7901 | if ((insn = (struct mips_opcode *) hash_find (op_hash, str)) == NULL) | |
7902 | { | |
7903 | insn_error = "unrecognized opcode"; | |
7904 | return; | |
7905 | } | |
252b5132 RH |
7906 | } |
7907 | ||
7908 | argsStart = s; | |
7909 | for (;;) | |
7910 | { | |
b34976b6 | 7911 | bfd_boolean ok; |
252b5132 RH |
7912 | |
7913 | assert (strcmp (insn->name, str) == 0); | |
7914 | ||
1f25f5d3 CD |
7915 | if (OPCODE_IS_MEMBER (insn, |
7916 | (mips_opts.isa | |
3396de36 | 7917 | | (file_ase_mips16 ? INSN_MIPS16 : 0) |
deec1734 | 7918 | | (mips_opts.ase_mdmx ? INSN_MDMX : 0) |
98d3f06f | 7919 | | (mips_opts.ase_mips3d ? INSN_MIPS3D : 0)), |
fef14a42 | 7920 | mips_opts.arch)) |
b34976b6 | 7921 | ok = TRUE; |
bdaaa2e1 | 7922 | else |
b34976b6 | 7923 | ok = FALSE; |
bdaaa2e1 | 7924 | |
252b5132 RH |
7925 | if (insn->pinfo != INSN_MACRO) |
7926 | { | |
fef14a42 | 7927 | if (mips_opts.arch == CPU_R4650 && (insn->pinfo & FP_D) != 0) |
b34976b6 | 7928 | ok = FALSE; |
252b5132 RH |
7929 | } |
7930 | ||
7931 | if (! ok) | |
7932 | { | |
7933 | if (insn + 1 < &mips_opcodes[NUMOPCODES] | |
7934 | && strcmp (insn->name, insn[1].name) == 0) | |
7935 | { | |
7936 | ++insn; | |
7937 | continue; | |
7938 | } | |
252b5132 | 7939 | else |
beae10d5 | 7940 | { |
268f6bed L |
7941 | if (!insn_error) |
7942 | { | |
7943 | static char buf[100]; | |
fef14a42 TS |
7944 | sprintf (buf, |
7945 | _("opcode not supported on this processor: %s (%s)"), | |
7946 | mips_cpu_info_from_arch (mips_opts.arch)->name, | |
7947 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
268f6bed L |
7948 | insn_error = buf; |
7949 | } | |
7950 | if (save_c) | |
7951 | *(--s) = save_c; | |
2bd7f1f3 | 7952 | return; |
252b5132 | 7953 | } |
252b5132 RH |
7954 | } |
7955 | ||
1e915849 | 7956 | create_insn (ip, insn); |
268f6bed | 7957 | insn_error = NULL; |
252b5132 RH |
7958 | for (args = insn->args;; ++args) |
7959 | { | |
deec1734 CD |
7960 | int is_mdmx; |
7961 | ||
ad8d3bb3 | 7962 | s += strspn (s, " \t"); |
deec1734 | 7963 | is_mdmx = 0; |
252b5132 RH |
7964 | switch (*args) |
7965 | { | |
7966 | case '\0': /* end of args */ | |
7967 | if (*s == '\0') | |
7968 | return; | |
7969 | break; | |
7970 | ||
7971 | case ',': | |
7972 | if (*s++ == *args) | |
7973 | continue; | |
7974 | s--; | |
7975 | switch (*++args) | |
7976 | { | |
7977 | case 'r': | |
7978 | case 'v': | |
bf12938e | 7979 | INSERT_OPERAND (RS, *ip, lastregno); |
252b5132 RH |
7980 | continue; |
7981 | ||
7982 | case 'w': | |
bf12938e | 7983 | INSERT_OPERAND (RT, *ip, lastregno); |
38487616 TS |
7984 | continue; |
7985 | ||
252b5132 | 7986 | case 'W': |
bf12938e | 7987 | INSERT_OPERAND (FT, *ip, lastregno); |
252b5132 RH |
7988 | continue; |
7989 | ||
7990 | case 'V': | |
bf12938e | 7991 | INSERT_OPERAND (FS, *ip, lastregno); |
252b5132 RH |
7992 | continue; |
7993 | } | |
7994 | break; | |
7995 | ||
7996 | case '(': | |
7997 | /* Handle optional base register. | |
7998 | Either the base register is omitted or | |
bdaaa2e1 | 7999 | we must have a left paren. */ |
252b5132 RH |
8000 | /* This is dependent on the next operand specifier |
8001 | is a base register specification. */ | |
8002 | assert (args[1] == 'b' || args[1] == '5' | |
8003 | || args[1] == '-' || args[1] == '4'); | |
8004 | if (*s == '\0') | |
8005 | return; | |
8006 | ||
8007 | case ')': /* these must match exactly */ | |
60b63b72 RS |
8008 | case '[': |
8009 | case ']': | |
252b5132 RH |
8010 | if (*s++ == *args) |
8011 | continue; | |
8012 | break; | |
8013 | ||
af7ee8bf CD |
8014 | case '+': /* Opcode extension character. */ |
8015 | switch (*++args) | |
8016 | { | |
071742cf CD |
8017 | case 'A': /* ins/ext position, becomes LSB. */ |
8018 | limlo = 0; | |
8019 | limhi = 31; | |
5f74bc13 CD |
8020 | goto do_lsb; |
8021 | case 'E': | |
8022 | limlo = 32; | |
8023 | limhi = 63; | |
8024 | goto do_lsb; | |
8025 | do_lsb: | |
071742cf CD |
8026 | my_getExpression (&imm_expr, s); |
8027 | check_absolute_expr (ip, &imm_expr); | |
8028 | if ((unsigned long) imm_expr.X_add_number < limlo | |
8029 | || (unsigned long) imm_expr.X_add_number > limhi) | |
8030 | { | |
8031 | as_bad (_("Improper position (%lu)"), | |
8032 | (unsigned long) imm_expr.X_add_number); | |
8033 | imm_expr.X_add_number = limlo; | |
8034 | } | |
8035 | lastpos = imm_expr.X_add_number; | |
bf12938e | 8036 | INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number); |
071742cf CD |
8037 | imm_expr.X_op = O_absent; |
8038 | s = expr_end; | |
8039 | continue; | |
8040 | ||
8041 | case 'B': /* ins size, becomes MSB. */ | |
8042 | limlo = 1; | |
8043 | limhi = 32; | |
5f74bc13 CD |
8044 | goto do_msb; |
8045 | case 'F': | |
8046 | limlo = 33; | |
8047 | limhi = 64; | |
8048 | goto do_msb; | |
8049 | do_msb: | |
071742cf CD |
8050 | my_getExpression (&imm_expr, s); |
8051 | check_absolute_expr (ip, &imm_expr); | |
8052 | /* Check for negative input so that small negative numbers | |
8053 | will not succeed incorrectly. The checks against | |
8054 | (pos+size) transitively check "size" itself, | |
8055 | assuming that "pos" is reasonable. */ | |
8056 | if ((long) imm_expr.X_add_number < 0 | |
8057 | || ((unsigned long) imm_expr.X_add_number | |
8058 | + lastpos) < limlo | |
8059 | || ((unsigned long) imm_expr.X_add_number | |
8060 | + lastpos) > limhi) | |
8061 | { | |
8062 | as_bad (_("Improper insert size (%lu, position %lu)"), | |
8063 | (unsigned long) imm_expr.X_add_number, | |
8064 | (unsigned long) lastpos); | |
8065 | imm_expr.X_add_number = limlo - lastpos; | |
8066 | } | |
bf12938e RS |
8067 | INSERT_OPERAND (INSMSB, *ip, |
8068 | lastpos + imm_expr.X_add_number - 1); | |
071742cf CD |
8069 | imm_expr.X_op = O_absent; |
8070 | s = expr_end; | |
8071 | continue; | |
8072 | ||
8073 | case 'C': /* ext size, becomes MSBD. */ | |
8074 | limlo = 1; | |
8075 | limhi = 32; | |
5f74bc13 CD |
8076 | goto do_msbd; |
8077 | case 'G': | |
8078 | limlo = 33; | |
8079 | limhi = 64; | |
8080 | goto do_msbd; | |
8081 | case 'H': | |
8082 | limlo = 33; | |
8083 | limhi = 64; | |
8084 | goto do_msbd; | |
8085 | do_msbd: | |
071742cf CD |
8086 | my_getExpression (&imm_expr, s); |
8087 | check_absolute_expr (ip, &imm_expr); | |
8088 | /* Check for negative input so that small negative numbers | |
8089 | will not succeed incorrectly. The checks against | |
8090 | (pos+size) transitively check "size" itself, | |
8091 | assuming that "pos" is reasonable. */ | |
8092 | if ((long) imm_expr.X_add_number < 0 | |
8093 | || ((unsigned long) imm_expr.X_add_number | |
8094 | + lastpos) < limlo | |
8095 | || ((unsigned long) imm_expr.X_add_number | |
8096 | + lastpos) > limhi) | |
8097 | { | |
8098 | as_bad (_("Improper extract size (%lu, position %lu)"), | |
8099 | (unsigned long) imm_expr.X_add_number, | |
8100 | (unsigned long) lastpos); | |
8101 | imm_expr.X_add_number = limlo - lastpos; | |
8102 | } | |
bf12938e | 8103 | INSERT_OPERAND (EXTMSBD, *ip, imm_expr.X_add_number - 1); |
071742cf CD |
8104 | imm_expr.X_op = O_absent; |
8105 | s = expr_end; | |
8106 | continue; | |
af7ee8bf | 8107 | |
bbcc0807 CD |
8108 | case 'D': |
8109 | /* +D is for disassembly only; never match. */ | |
8110 | break; | |
8111 | ||
5f74bc13 CD |
8112 | case 'I': |
8113 | /* "+I" is like "I", except that imm2_expr is used. */ | |
8114 | my_getExpression (&imm2_expr, s); | |
8115 | if (imm2_expr.X_op != O_big | |
8116 | && imm2_expr.X_op != O_constant) | |
8117 | insn_error = _("absolute expression required"); | |
13757d0c | 8118 | normalize_constant_expr (&imm2_expr); |
5f74bc13 CD |
8119 | s = expr_end; |
8120 | continue; | |
8121 | ||
af7ee8bf CD |
8122 | default: |
8123 | as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"), | |
8124 | *args, insn->name, insn->args); | |
8125 | /* Further processing is fruitless. */ | |
8126 | return; | |
8127 | } | |
8128 | break; | |
8129 | ||
252b5132 RH |
8130 | case '<': /* must be at least one digit */ |
8131 | /* | |
8132 | * According to the manual, if the shift amount is greater | |
b6ff326e KH |
8133 | * than 31 or less than 0, then the shift amount should be |
8134 | * mod 32. In reality the mips assembler issues an error. | |
252b5132 RH |
8135 | * We issue a warning and mask out all but the low 5 bits. |
8136 | */ | |
8137 | my_getExpression (&imm_expr, s); | |
8138 | check_absolute_expr (ip, &imm_expr); | |
8139 | if ((unsigned long) imm_expr.X_add_number > 31) | |
bf12938e RS |
8140 | as_warn (_("Improper shift amount (%lu)"), |
8141 | (unsigned long) imm_expr.X_add_number); | |
8142 | INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number); | |
252b5132 RH |
8143 | imm_expr.X_op = O_absent; |
8144 | s = expr_end; | |
8145 | continue; | |
8146 | ||
8147 | case '>': /* shift amount minus 32 */ | |
8148 | my_getExpression (&imm_expr, s); | |
8149 | check_absolute_expr (ip, &imm_expr); | |
8150 | if ((unsigned long) imm_expr.X_add_number < 32 | |
8151 | || (unsigned long) imm_expr.X_add_number > 63) | |
8152 | break; | |
bf12938e | 8153 | INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number - 32); |
252b5132 RH |
8154 | imm_expr.X_op = O_absent; |
8155 | s = expr_end; | |
8156 | continue; | |
8157 | ||
252b5132 RH |
8158 | case 'k': /* cache code */ |
8159 | case 'h': /* prefx code */ | |
8160 | my_getExpression (&imm_expr, s); | |
8161 | check_absolute_expr (ip, &imm_expr); | |
8162 | if ((unsigned long) imm_expr.X_add_number > 31) | |
bf12938e RS |
8163 | as_warn (_("Invalid value for `%s' (%lu)"), |
8164 | ip->insn_mo->name, | |
8165 | (unsigned long) imm_expr.X_add_number); | |
252b5132 | 8166 | if (*args == 'k') |
bf12938e | 8167 | INSERT_OPERAND (CACHE, *ip, imm_expr.X_add_number); |
252b5132 | 8168 | else |
bf12938e | 8169 | INSERT_OPERAND (PREFX, *ip, imm_expr.X_add_number); |
252b5132 RH |
8170 | imm_expr.X_op = O_absent; |
8171 | s = expr_end; | |
8172 | continue; | |
8173 | ||
8174 | case 'c': /* break code */ | |
8175 | my_getExpression (&imm_expr, s); | |
8176 | check_absolute_expr (ip, &imm_expr); | |
793b27f4 | 8177 | if ((unsigned long) imm_expr.X_add_number > 1023) |
bf12938e RS |
8178 | as_warn (_("Illegal break code (%lu)"), |
8179 | (unsigned long) imm_expr.X_add_number); | |
8180 | INSERT_OPERAND (CODE, *ip, imm_expr.X_add_number); | |
252b5132 RH |
8181 | imm_expr.X_op = O_absent; |
8182 | s = expr_end; | |
8183 | continue; | |
8184 | ||
8185 | case 'q': /* lower break code */ | |
8186 | my_getExpression (&imm_expr, s); | |
8187 | check_absolute_expr (ip, &imm_expr); | |
793b27f4 | 8188 | if ((unsigned long) imm_expr.X_add_number > 1023) |
bf12938e RS |
8189 | as_warn (_("Illegal lower break code (%lu)"), |
8190 | (unsigned long) imm_expr.X_add_number); | |
8191 | INSERT_OPERAND (CODE2, *ip, imm_expr.X_add_number); | |
252b5132 RH |
8192 | imm_expr.X_op = O_absent; |
8193 | s = expr_end; | |
8194 | continue; | |
8195 | ||
4372b673 | 8196 | case 'B': /* 20-bit syscall/break code. */ |
156c2f8b | 8197 | my_getExpression (&imm_expr, s); |
156c2f8b | 8198 | check_absolute_expr (ip, &imm_expr); |
793b27f4 TS |
8199 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE20) |
8200 | as_warn (_("Illegal 20-bit code (%lu)"), | |
8201 | (unsigned long) imm_expr.X_add_number); | |
bf12938e | 8202 | INSERT_OPERAND (CODE20, *ip, imm_expr.X_add_number); |
252b5132 RH |
8203 | imm_expr.X_op = O_absent; |
8204 | s = expr_end; | |
8205 | continue; | |
8206 | ||
98d3f06f | 8207 | case 'C': /* Coprocessor code */ |
beae10d5 | 8208 | my_getExpression (&imm_expr, s); |
252b5132 | 8209 | check_absolute_expr (ip, &imm_expr); |
98d3f06f | 8210 | if ((unsigned long) imm_expr.X_add_number >= (1 << 25)) |
252b5132 | 8211 | { |
793b27f4 TS |
8212 | as_warn (_("Coproccesor code > 25 bits (%lu)"), |
8213 | (unsigned long) imm_expr.X_add_number); | |
98d3f06f | 8214 | imm_expr.X_add_number &= ((1 << 25) - 1); |
252b5132 | 8215 | } |
beae10d5 KH |
8216 | ip->insn_opcode |= imm_expr.X_add_number; |
8217 | imm_expr.X_op = O_absent; | |
8218 | s = expr_end; | |
8219 | continue; | |
252b5132 | 8220 | |
4372b673 NC |
8221 | case 'J': /* 19-bit wait code. */ |
8222 | my_getExpression (&imm_expr, s); | |
8223 | check_absolute_expr (ip, &imm_expr); | |
793b27f4 TS |
8224 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE19) |
8225 | as_warn (_("Illegal 19-bit code (%lu)"), | |
8226 | (unsigned long) imm_expr.X_add_number); | |
bf12938e | 8227 | INSERT_OPERAND (CODE19, *ip, imm_expr.X_add_number); |
4372b673 NC |
8228 | imm_expr.X_op = O_absent; |
8229 | s = expr_end; | |
8230 | continue; | |
8231 | ||
252b5132 | 8232 | case 'P': /* Performance register */ |
beae10d5 | 8233 | my_getExpression (&imm_expr, s); |
252b5132 | 8234 | check_absolute_expr (ip, &imm_expr); |
beae10d5 | 8235 | if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1) |
bf12938e RS |
8236 | as_warn (_("Invalid performance register (%lu)"), |
8237 | (unsigned long) imm_expr.X_add_number); | |
8238 | INSERT_OPERAND (PERFREG, *ip, imm_expr.X_add_number); | |
beae10d5 KH |
8239 | imm_expr.X_op = O_absent; |
8240 | s = expr_end; | |
8241 | continue; | |
252b5132 RH |
8242 | |
8243 | case 'b': /* base register */ | |
8244 | case 'd': /* destination register */ | |
8245 | case 's': /* source register */ | |
8246 | case 't': /* target register */ | |
8247 | case 'r': /* both target and source */ | |
8248 | case 'v': /* both dest and source */ | |
8249 | case 'w': /* both dest and target */ | |
8250 | case 'E': /* coprocessor target register */ | |
8251 | case 'G': /* coprocessor destination register */ | |
af7ee8bf | 8252 | case 'K': /* 'rdhwr' destination register */ |
252b5132 RH |
8253 | case 'x': /* ignore register name */ |
8254 | case 'z': /* must be zero register */ | |
4372b673 | 8255 | case 'U': /* destination register (clo/clz). */ |
252b5132 RH |
8256 | s_reset = s; |
8257 | if (s[0] == '$') | |
8258 | { | |
8259 | ||
3882b010 | 8260 | if (ISDIGIT (s[1])) |
252b5132 RH |
8261 | { |
8262 | ++s; | |
8263 | regno = 0; | |
8264 | do | |
8265 | { | |
8266 | regno *= 10; | |
8267 | regno += *s - '0'; | |
8268 | ++s; | |
8269 | } | |
3882b010 | 8270 | while (ISDIGIT (*s)); |
252b5132 RH |
8271 | if (regno > 31) |
8272 | as_bad (_("Invalid register number (%d)"), regno); | |
8273 | } | |
af7ee8bf | 8274 | else if (*args == 'E' || *args == 'G' || *args == 'K') |
252b5132 RH |
8275 | goto notreg; |
8276 | else | |
8277 | { | |
76db943d TS |
8278 | if (s[1] == 'r' && s[2] == 'a') |
8279 | { | |
8280 | s += 3; | |
8281 | regno = RA; | |
8282 | } | |
8283 | else if (s[1] == 'f' && s[2] == 'p') | |
252b5132 RH |
8284 | { |
8285 | s += 3; | |
8286 | regno = FP; | |
8287 | } | |
8288 | else if (s[1] == 's' && s[2] == 'p') | |
8289 | { | |
8290 | s += 3; | |
8291 | regno = SP; | |
8292 | } | |
8293 | else if (s[1] == 'g' && s[2] == 'p') | |
8294 | { | |
8295 | s += 3; | |
8296 | regno = GP; | |
8297 | } | |
8298 | else if (s[1] == 'a' && s[2] == 't') | |
8299 | { | |
8300 | s += 3; | |
8301 | regno = AT; | |
8302 | } | |
8303 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '0') | |
8304 | { | |
8305 | s += 4; | |
8306 | regno = KT0; | |
8307 | } | |
8308 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '1') | |
8309 | { | |
8310 | s += 4; | |
8311 | regno = KT1; | |
8312 | } | |
85b51719 TS |
8313 | else if (s[1] == 'z' && s[2] == 'e' && s[3] == 'r' && s[4] == 'o') |
8314 | { | |
8315 | s += 5; | |
8316 | regno = ZERO; | |
8317 | } | |
252b5132 RH |
8318 | else if (itbl_have_entries) |
8319 | { | |
8320 | char *p, *n; | |
d7ba4a77 | 8321 | unsigned long r; |
252b5132 | 8322 | |
d7ba4a77 | 8323 | p = s + 1; /* advance past '$' */ |
252b5132 RH |
8324 | n = itbl_get_field (&p); /* n is name */ |
8325 | ||
d7ba4a77 ILT |
8326 | /* See if this is a register defined in an |
8327 | itbl entry. */ | |
8328 | if (itbl_get_reg_val (n, &r)) | |
252b5132 RH |
8329 | { |
8330 | /* Get_field advances to the start of | |
8331 | the next field, so we need to back | |
d7ba4a77 | 8332 | rack to the end of the last field. */ |
bdaaa2e1 | 8333 | if (p) |
252b5132 | 8334 | s = p - 1; |
bdaaa2e1 | 8335 | else |
d7ba4a77 | 8336 | s = strchr (s, '\0'); |
252b5132 RH |
8337 | regno = r; |
8338 | } | |
8339 | else | |
8340 | goto notreg; | |
beae10d5 | 8341 | } |
252b5132 RH |
8342 | else |
8343 | goto notreg; | |
8344 | } | |
8345 | if (regno == AT | |
8346 | && ! mips_opts.noat | |
8347 | && *args != 'E' | |
af7ee8bf CD |
8348 | && *args != 'G' |
8349 | && *args != 'K') | |
252b5132 RH |
8350 | as_warn (_("Used $at without \".set noat\"")); |
8351 | c = *args; | |
8352 | if (*s == ' ') | |
f9419b05 | 8353 | ++s; |
252b5132 RH |
8354 | if (args[1] != *s) |
8355 | { | |
8356 | if (c == 'r' || c == 'v' || c == 'w') | |
8357 | { | |
8358 | regno = lastregno; | |
8359 | s = s_reset; | |
f9419b05 | 8360 | ++args; |
252b5132 RH |
8361 | } |
8362 | } | |
8363 | /* 'z' only matches $0. */ | |
8364 | if (c == 'z' && regno != 0) | |
8365 | break; | |
8366 | ||
bdaaa2e1 KH |
8367 | /* Now that we have assembled one operand, we use the args string |
8368 | * to figure out where it goes in the instruction. */ | |
252b5132 RH |
8369 | switch (c) |
8370 | { | |
8371 | case 'r': | |
8372 | case 's': | |
8373 | case 'v': | |
8374 | case 'b': | |
bf12938e | 8375 | INSERT_OPERAND (RS, *ip, regno); |
252b5132 RH |
8376 | break; |
8377 | case 'd': | |
8378 | case 'G': | |
af7ee8bf | 8379 | case 'K': |
bf12938e | 8380 | INSERT_OPERAND (RD, *ip, regno); |
252b5132 | 8381 | break; |
4372b673 | 8382 | case 'U': |
bf12938e RS |
8383 | INSERT_OPERAND (RD, *ip, regno); |
8384 | INSERT_OPERAND (RT, *ip, regno); | |
4372b673 | 8385 | break; |
252b5132 RH |
8386 | case 'w': |
8387 | case 't': | |
8388 | case 'E': | |
bf12938e | 8389 | INSERT_OPERAND (RT, *ip, regno); |
252b5132 RH |
8390 | break; |
8391 | case 'x': | |
8392 | /* This case exists because on the r3000 trunc | |
8393 | expands into a macro which requires a gp | |
8394 | register. On the r6000 or r4000 it is | |
8395 | assembled into a single instruction which | |
8396 | ignores the register. Thus the insn version | |
8397 | is MIPS_ISA2 and uses 'x', and the macro | |
8398 | version is MIPS_ISA1 and uses 't'. */ | |
8399 | break; | |
8400 | case 'z': | |
8401 | /* This case is for the div instruction, which | |
8402 | acts differently if the destination argument | |
8403 | is $0. This only matches $0, and is checked | |
8404 | outside the switch. */ | |
8405 | break; | |
8406 | case 'D': | |
8407 | /* Itbl operand; not yet implemented. FIXME ?? */ | |
8408 | break; | |
8409 | /* What about all other operands like 'i', which | |
8410 | can be specified in the opcode table? */ | |
8411 | } | |
8412 | lastregno = regno; | |
8413 | continue; | |
8414 | } | |
8415 | notreg: | |
8416 | switch (*args++) | |
8417 | { | |
8418 | case 'r': | |
8419 | case 'v': | |
bf12938e | 8420 | INSERT_OPERAND (RS, *ip, lastregno); |
252b5132 RH |
8421 | continue; |
8422 | case 'w': | |
bf12938e | 8423 | INSERT_OPERAND (RT, *ip, lastregno); |
252b5132 RH |
8424 | continue; |
8425 | } | |
8426 | break; | |
8427 | ||
deec1734 CD |
8428 | case 'O': /* MDMX alignment immediate constant. */ |
8429 | my_getExpression (&imm_expr, s); | |
8430 | check_absolute_expr (ip, &imm_expr); | |
8431 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_ALN) | |
bf12938e RS |
8432 | as_warn ("Improper align amount (%ld), using low bits", |
8433 | (long) imm_expr.X_add_number); | |
8434 | INSERT_OPERAND (ALN, *ip, imm_expr.X_add_number); | |
deec1734 CD |
8435 | imm_expr.X_op = O_absent; |
8436 | s = expr_end; | |
8437 | continue; | |
8438 | ||
8439 | case 'Q': /* MDMX vector, element sel, or const. */ | |
8440 | if (s[0] != '$') | |
8441 | { | |
8442 | /* MDMX Immediate. */ | |
8443 | my_getExpression (&imm_expr, s); | |
8444 | check_absolute_expr (ip, &imm_expr); | |
8445 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_FT) | |
bf12938e RS |
8446 | as_warn (_("Invalid MDMX Immediate (%ld)"), |
8447 | (long) imm_expr.X_add_number); | |
8448 | INSERT_OPERAND (FT, *ip, imm_expr.X_add_number); | |
deec1734 CD |
8449 | if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL)) |
8450 | ip->insn_opcode |= MDMX_FMTSEL_IMM_QH << OP_SH_VSEL; | |
8451 | else | |
8452 | ip->insn_opcode |= MDMX_FMTSEL_IMM_OB << OP_SH_VSEL; | |
deec1734 CD |
8453 | imm_expr.X_op = O_absent; |
8454 | s = expr_end; | |
8455 | continue; | |
8456 | } | |
8457 | /* Not MDMX Immediate. Fall through. */ | |
8458 | case 'X': /* MDMX destination register. */ | |
8459 | case 'Y': /* MDMX source register. */ | |
8460 | case 'Z': /* MDMX target register. */ | |
8461 | is_mdmx = 1; | |
252b5132 RH |
8462 | case 'D': /* floating point destination register */ |
8463 | case 'S': /* floating point source register */ | |
8464 | case 'T': /* floating point target register */ | |
8465 | case 'R': /* floating point source register */ | |
8466 | case 'V': | |
8467 | case 'W': | |
8468 | s_reset = s; | |
deec1734 CD |
8469 | /* Accept $fN for FP and MDMX register numbers, and in |
8470 | addition accept $vN for MDMX register numbers. */ | |
8471 | if ((s[0] == '$' && s[1] == 'f' && ISDIGIT (s[2])) | |
8472 | || (is_mdmx != 0 && s[0] == '$' && s[1] == 'v' | |
8473 | && ISDIGIT (s[2]))) | |
252b5132 RH |
8474 | { |
8475 | s += 2; | |
8476 | regno = 0; | |
8477 | do | |
8478 | { | |
8479 | regno *= 10; | |
8480 | regno += *s - '0'; | |
8481 | ++s; | |
8482 | } | |
3882b010 | 8483 | while (ISDIGIT (*s)); |
252b5132 RH |
8484 | |
8485 | if (regno > 31) | |
8486 | as_bad (_("Invalid float register number (%d)"), regno); | |
8487 | ||
8488 | if ((regno & 1) != 0 | |
ca4e0257 | 8489 | && HAVE_32BIT_FPRS |
252b5132 RH |
8490 | && ! (strcmp (str, "mtc1") == 0 |
8491 | || strcmp (str, "mfc1") == 0 | |
8492 | || strcmp (str, "lwc1") == 0 | |
8493 | || strcmp (str, "swc1") == 0 | |
8494 | || strcmp (str, "l.s") == 0 | |
8495 | || strcmp (str, "s.s") == 0)) | |
8496 | as_warn (_("Float register should be even, was %d"), | |
8497 | regno); | |
8498 | ||
8499 | c = *args; | |
8500 | if (*s == ' ') | |
f9419b05 | 8501 | ++s; |
252b5132 RH |
8502 | if (args[1] != *s) |
8503 | { | |
8504 | if (c == 'V' || c == 'W') | |
8505 | { | |
8506 | regno = lastregno; | |
8507 | s = s_reset; | |
f9419b05 | 8508 | ++args; |
252b5132 RH |
8509 | } |
8510 | } | |
8511 | switch (c) | |
8512 | { | |
8513 | case 'D': | |
deec1734 | 8514 | case 'X': |
bf12938e | 8515 | INSERT_OPERAND (FD, *ip, regno); |
252b5132 RH |
8516 | break; |
8517 | case 'V': | |
8518 | case 'S': | |
deec1734 | 8519 | case 'Y': |
bf12938e | 8520 | INSERT_OPERAND (FS, *ip, regno); |
252b5132 | 8521 | break; |
deec1734 CD |
8522 | case 'Q': |
8523 | /* This is like 'Z', but also needs to fix the MDMX | |
8524 | vector/scalar select bits. Note that the | |
8525 | scalar immediate case is handled above. */ | |
8526 | if (*s == '[') | |
8527 | { | |
8528 | int is_qh = (ip->insn_opcode & (1 << OP_SH_VSEL)); | |
8529 | int max_el = (is_qh ? 3 : 7); | |
8530 | s++; | |
8531 | my_getExpression(&imm_expr, s); | |
8532 | check_absolute_expr (ip, &imm_expr); | |
8533 | s = expr_end; | |
8534 | if (imm_expr.X_add_number > max_el) | |
8535 | as_bad(_("Bad element selector %ld"), | |
8536 | (long) imm_expr.X_add_number); | |
8537 | imm_expr.X_add_number &= max_el; | |
8538 | ip->insn_opcode |= (imm_expr.X_add_number | |
8539 | << (OP_SH_VSEL + | |
8540 | (is_qh ? 2 : 1))); | |
01a3f561 | 8541 | imm_expr.X_op = O_absent; |
deec1734 CD |
8542 | if (*s != ']') |
8543 | as_warn(_("Expecting ']' found '%s'"), s); | |
8544 | else | |
8545 | s++; | |
8546 | } | |
8547 | else | |
8548 | { | |
8549 | if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL)) | |
8550 | ip->insn_opcode |= (MDMX_FMTSEL_VEC_QH | |
8551 | << OP_SH_VSEL); | |
8552 | else | |
8553 | ip->insn_opcode |= (MDMX_FMTSEL_VEC_OB << | |
8554 | OP_SH_VSEL); | |
8555 | } | |
8556 | /* Fall through */ | |
252b5132 RH |
8557 | case 'W': |
8558 | case 'T': | |
deec1734 | 8559 | case 'Z': |
bf12938e | 8560 | INSERT_OPERAND (FT, *ip, regno); |
252b5132 RH |
8561 | break; |
8562 | case 'R': | |
bf12938e | 8563 | INSERT_OPERAND (FR, *ip, regno); |
252b5132 RH |
8564 | break; |
8565 | } | |
8566 | lastregno = regno; | |
8567 | continue; | |
8568 | } | |
8569 | ||
252b5132 RH |
8570 | switch (*args++) |
8571 | { | |
8572 | case 'V': | |
bf12938e | 8573 | INSERT_OPERAND (FS, *ip, lastregno); |
252b5132 RH |
8574 | continue; |
8575 | case 'W': | |
bf12938e | 8576 | INSERT_OPERAND (FT, *ip, lastregno); |
252b5132 RH |
8577 | continue; |
8578 | } | |
8579 | break; | |
8580 | ||
8581 | case 'I': | |
8582 | my_getExpression (&imm_expr, s); | |
8583 | if (imm_expr.X_op != O_big | |
8584 | && imm_expr.X_op != O_constant) | |
8585 | insn_error = _("absolute expression required"); | |
13757d0c | 8586 | normalize_constant_expr (&imm_expr); |
252b5132 RH |
8587 | s = expr_end; |
8588 | continue; | |
8589 | ||
8590 | case 'A': | |
8591 | my_getExpression (&offset_expr, s); | |
f6688943 | 8592 | *imm_reloc = BFD_RELOC_32; |
252b5132 RH |
8593 | s = expr_end; |
8594 | continue; | |
8595 | ||
8596 | case 'F': | |
8597 | case 'L': | |
8598 | case 'f': | |
8599 | case 'l': | |
8600 | { | |
8601 | int f64; | |
ca4e0257 | 8602 | int using_gprs; |
252b5132 RH |
8603 | char *save_in; |
8604 | char *err; | |
8605 | unsigned char temp[8]; | |
8606 | int len; | |
8607 | unsigned int length; | |
8608 | segT seg; | |
8609 | subsegT subseg; | |
8610 | char *p; | |
8611 | ||
8612 | /* These only appear as the last operand in an | |
8613 | instruction, and every instruction that accepts | |
8614 | them in any variant accepts them in all variants. | |
8615 | This means we don't have to worry about backing out | |
8616 | any changes if the instruction does not match. | |
8617 | ||
8618 | The difference between them is the size of the | |
8619 | floating point constant and where it goes. For 'F' | |
8620 | and 'L' the constant is 64 bits; for 'f' and 'l' it | |
8621 | is 32 bits. Where the constant is placed is based | |
8622 | on how the MIPS assembler does things: | |
8623 | F -- .rdata | |
8624 | L -- .lit8 | |
8625 | f -- immediate value | |
8626 | l -- .lit4 | |
8627 | ||
8628 | The .lit4 and .lit8 sections are only used if | |
8629 | permitted by the -G argument. | |
8630 | ||
ca4e0257 RS |
8631 | The code below needs to know whether the target register |
8632 | is 32 or 64 bits wide. It relies on the fact 'f' and | |
8633 | 'F' are used with GPR-based instructions and 'l' and | |
8634 | 'L' are used with FPR-based instructions. */ | |
252b5132 RH |
8635 | |
8636 | f64 = *args == 'F' || *args == 'L'; | |
ca4e0257 | 8637 | using_gprs = *args == 'F' || *args == 'f'; |
252b5132 RH |
8638 | |
8639 | save_in = input_line_pointer; | |
8640 | input_line_pointer = s; | |
8641 | err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len); | |
8642 | length = len; | |
8643 | s = input_line_pointer; | |
8644 | input_line_pointer = save_in; | |
8645 | if (err != NULL && *err != '\0') | |
8646 | { | |
8647 | as_bad (_("Bad floating point constant: %s"), err); | |
8648 | memset (temp, '\0', sizeof temp); | |
8649 | length = f64 ? 8 : 4; | |
8650 | } | |
8651 | ||
156c2f8b | 8652 | assert (length == (unsigned) (f64 ? 8 : 4)); |
252b5132 RH |
8653 | |
8654 | if (*args == 'f' | |
8655 | || (*args == 'l' | |
3e722fb5 | 8656 | && (g_switch_value < 4 |
252b5132 RH |
8657 | || (temp[0] == 0 && temp[1] == 0) |
8658 | || (temp[2] == 0 && temp[3] == 0)))) | |
8659 | { | |
8660 | imm_expr.X_op = O_constant; | |
8661 | if (! target_big_endian) | |
8662 | imm_expr.X_add_number = bfd_getl32 (temp); | |
8663 | else | |
8664 | imm_expr.X_add_number = bfd_getb32 (temp); | |
8665 | } | |
8666 | else if (length > 4 | |
119d663a | 8667 | && ! mips_disable_float_construction |
ca4e0257 RS |
8668 | /* Constants can only be constructed in GPRs and |
8669 | copied to FPRs if the GPRs are at least as wide | |
8670 | as the FPRs. Force the constant into memory if | |
8671 | we are using 64-bit FPRs but the GPRs are only | |
8672 | 32 bits wide. */ | |
8673 | && (using_gprs | |
8674 | || ! (HAVE_64BIT_FPRS && HAVE_32BIT_GPRS)) | |
252b5132 RH |
8675 | && ((temp[0] == 0 && temp[1] == 0) |
8676 | || (temp[2] == 0 && temp[3] == 0)) | |
8677 | && ((temp[4] == 0 && temp[5] == 0) | |
8678 | || (temp[6] == 0 && temp[7] == 0))) | |
8679 | { | |
ca4e0257 RS |
8680 | /* The value is simple enough to load with a couple of |
8681 | instructions. If using 32-bit registers, set | |
8682 | imm_expr to the high order 32 bits and offset_expr to | |
8683 | the low order 32 bits. Otherwise, set imm_expr to | |
8684 | the entire 64 bit constant. */ | |
8685 | if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS) | |
252b5132 RH |
8686 | { |
8687 | imm_expr.X_op = O_constant; | |
8688 | offset_expr.X_op = O_constant; | |
8689 | if (! target_big_endian) | |
8690 | { | |
8691 | imm_expr.X_add_number = bfd_getl32 (temp + 4); | |
8692 | offset_expr.X_add_number = bfd_getl32 (temp); | |
8693 | } | |
8694 | else | |
8695 | { | |
8696 | imm_expr.X_add_number = bfd_getb32 (temp); | |
8697 | offset_expr.X_add_number = bfd_getb32 (temp + 4); | |
8698 | } | |
8699 | if (offset_expr.X_add_number == 0) | |
8700 | offset_expr.X_op = O_absent; | |
8701 | } | |
8702 | else if (sizeof (imm_expr.X_add_number) > 4) | |
8703 | { | |
8704 | imm_expr.X_op = O_constant; | |
8705 | if (! target_big_endian) | |
8706 | imm_expr.X_add_number = bfd_getl64 (temp); | |
8707 | else | |
8708 | imm_expr.X_add_number = bfd_getb64 (temp); | |
8709 | } | |
8710 | else | |
8711 | { | |
8712 | imm_expr.X_op = O_big; | |
8713 | imm_expr.X_add_number = 4; | |
8714 | if (! target_big_endian) | |
8715 | { | |
8716 | generic_bignum[0] = bfd_getl16 (temp); | |
8717 | generic_bignum[1] = bfd_getl16 (temp + 2); | |
8718 | generic_bignum[2] = bfd_getl16 (temp + 4); | |
8719 | generic_bignum[3] = bfd_getl16 (temp + 6); | |
8720 | } | |
8721 | else | |
8722 | { | |
8723 | generic_bignum[0] = bfd_getb16 (temp + 6); | |
8724 | generic_bignum[1] = bfd_getb16 (temp + 4); | |
8725 | generic_bignum[2] = bfd_getb16 (temp + 2); | |
8726 | generic_bignum[3] = bfd_getb16 (temp); | |
8727 | } | |
8728 | } | |
8729 | } | |
8730 | else | |
8731 | { | |
8732 | const char *newname; | |
8733 | segT new_seg; | |
8734 | ||
8735 | /* Switch to the right section. */ | |
8736 | seg = now_seg; | |
8737 | subseg = now_subseg; | |
8738 | switch (*args) | |
8739 | { | |
8740 | default: /* unused default case avoids warnings. */ | |
8741 | case 'L': | |
8742 | newname = RDATA_SECTION_NAME; | |
3e722fb5 | 8743 | if (g_switch_value >= 8) |
252b5132 RH |
8744 | newname = ".lit8"; |
8745 | break; | |
8746 | case 'F': | |
3e722fb5 | 8747 | newname = RDATA_SECTION_NAME; |
252b5132 RH |
8748 | break; |
8749 | case 'l': | |
4d0d148d | 8750 | assert (g_switch_value >= 4); |
252b5132 RH |
8751 | newname = ".lit4"; |
8752 | break; | |
8753 | } | |
8754 | new_seg = subseg_new (newname, (subsegT) 0); | |
8755 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
8756 | bfd_set_section_flags (stdoutput, new_seg, | |
8757 | (SEC_ALLOC | |
8758 | | SEC_LOAD | |
8759 | | SEC_READONLY | |
8760 | | SEC_DATA)); | |
8761 | frag_align (*args == 'l' ? 2 : 3, 0, 0); | |
8762 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour | |
8763 | && strcmp (TARGET_OS, "elf") != 0) | |
8764 | record_alignment (new_seg, 4); | |
8765 | else | |
8766 | record_alignment (new_seg, *args == 'l' ? 2 : 3); | |
8767 | if (seg == now_seg) | |
8768 | as_bad (_("Can't use floating point insn in this section")); | |
8769 | ||
8770 | /* Set the argument to the current address in the | |
8771 | section. */ | |
8772 | offset_expr.X_op = O_symbol; | |
8773 | offset_expr.X_add_symbol = | |
8774 | symbol_new ("L0\001", now_seg, | |
8775 | (valueT) frag_now_fix (), frag_now); | |
8776 | offset_expr.X_add_number = 0; | |
8777 | ||
8778 | /* Put the floating point number into the section. */ | |
8779 | p = frag_more ((int) length); | |
8780 | memcpy (p, temp, length); | |
8781 | ||
8782 | /* Switch back to the original section. */ | |
8783 | subseg_set (seg, subseg); | |
8784 | } | |
8785 | } | |
8786 | continue; | |
8787 | ||
8788 | case 'i': /* 16 bit unsigned immediate */ | |
8789 | case 'j': /* 16 bit signed immediate */ | |
f6688943 | 8790 | *imm_reloc = BFD_RELOC_LO16; |
5e0116d5 | 8791 | if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0) |
252b5132 RH |
8792 | { |
8793 | int more; | |
5e0116d5 RS |
8794 | offsetT minval, maxval; |
8795 | ||
8796 | more = (insn + 1 < &mips_opcodes[NUMOPCODES] | |
8797 | && strcmp (insn->name, insn[1].name) == 0); | |
8798 | ||
8799 | /* If the expression was written as an unsigned number, | |
8800 | only treat it as signed if there are no more | |
8801 | alternatives. */ | |
8802 | if (more | |
8803 | && *args == 'j' | |
8804 | && sizeof (imm_expr.X_add_number) <= 4 | |
8805 | && imm_expr.X_op == O_constant | |
8806 | && imm_expr.X_add_number < 0 | |
8807 | && imm_expr.X_unsigned | |
8808 | && HAVE_64BIT_GPRS) | |
8809 | break; | |
8810 | ||
8811 | /* For compatibility with older assemblers, we accept | |
8812 | 0x8000-0xffff as signed 16-bit numbers when only | |
8813 | signed numbers are allowed. */ | |
8814 | if (*args == 'i') | |
8815 | minval = 0, maxval = 0xffff; | |
8816 | else if (more) | |
8817 | minval = -0x8000, maxval = 0x7fff; | |
252b5132 | 8818 | else |
5e0116d5 RS |
8819 | minval = -0x8000, maxval = 0xffff; |
8820 | ||
8821 | if (imm_expr.X_op != O_constant | |
8822 | || imm_expr.X_add_number < minval | |
8823 | || imm_expr.X_add_number > maxval) | |
252b5132 RH |
8824 | { |
8825 | if (more) | |
8826 | break; | |
2ae7e77b AH |
8827 | if (imm_expr.X_op == O_constant |
8828 | || imm_expr.X_op == O_big) | |
5e0116d5 | 8829 | as_bad (_("expression out of range")); |
252b5132 RH |
8830 | } |
8831 | } | |
8832 | s = expr_end; | |
8833 | continue; | |
8834 | ||
8835 | case 'o': /* 16 bit offset */ | |
5e0116d5 RS |
8836 | /* Check whether there is only a single bracketed expression |
8837 | left. If so, it must be the base register and the | |
8838 | constant must be zero. */ | |
8839 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
8840 | { | |
8841 | offset_expr.X_op = O_constant; | |
8842 | offset_expr.X_add_number = 0; | |
8843 | continue; | |
8844 | } | |
252b5132 RH |
8845 | |
8846 | /* If this value won't fit into a 16 bit offset, then go | |
8847 | find a macro that will generate the 32 bit offset | |
afdbd6d0 | 8848 | code pattern. */ |
5e0116d5 | 8849 | if (my_getSmallExpression (&offset_expr, offset_reloc, s) == 0 |
252b5132 RH |
8850 | && (offset_expr.X_op != O_constant |
8851 | || offset_expr.X_add_number >= 0x8000 | |
afdbd6d0 | 8852 | || offset_expr.X_add_number < -0x8000)) |
252b5132 RH |
8853 | break; |
8854 | ||
252b5132 RH |
8855 | s = expr_end; |
8856 | continue; | |
8857 | ||
8858 | case 'p': /* pc relative offset */ | |
0b25d3e6 | 8859 | *offset_reloc = BFD_RELOC_16_PCREL_S2; |
252b5132 RH |
8860 | my_getExpression (&offset_expr, s); |
8861 | s = expr_end; | |
8862 | continue; | |
8863 | ||
8864 | case 'u': /* upper 16 bits */ | |
5e0116d5 RS |
8865 | if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0 |
8866 | && imm_expr.X_op == O_constant | |
8867 | && (imm_expr.X_add_number < 0 | |
8868 | || imm_expr.X_add_number >= 0x10000)) | |
252b5132 RH |
8869 | as_bad (_("lui expression not in range 0..65535")); |
8870 | s = expr_end; | |
8871 | continue; | |
8872 | ||
8873 | case 'a': /* 26 bit address */ | |
8874 | my_getExpression (&offset_expr, s); | |
8875 | s = expr_end; | |
f6688943 | 8876 | *offset_reloc = BFD_RELOC_MIPS_JMP; |
252b5132 RH |
8877 | continue; |
8878 | ||
8879 | case 'N': /* 3 bit branch condition code */ | |
8880 | case 'M': /* 3 bit compare condition code */ | |
8881 | if (strncmp (s, "$fcc", 4) != 0) | |
8882 | break; | |
8883 | s += 4; | |
8884 | regno = 0; | |
8885 | do | |
8886 | { | |
8887 | regno *= 10; | |
8888 | regno += *s - '0'; | |
8889 | ++s; | |
8890 | } | |
3882b010 | 8891 | while (ISDIGIT (*s)); |
252b5132 | 8892 | if (regno > 7) |
30c378fd CD |
8893 | as_bad (_("Invalid condition code register $fcc%d"), regno); |
8894 | if ((strcmp(str + strlen(str) - 3, ".ps") == 0 | |
8895 | || strcmp(str + strlen(str) - 5, "any2f") == 0 | |
8896 | || strcmp(str + strlen(str) - 5, "any2t") == 0) | |
8897 | && (regno & 1) != 0) | |
8898 | as_warn(_("Condition code register should be even for %s, was %d"), | |
8899 | str, regno); | |
8900 | if ((strcmp(str + strlen(str) - 5, "any4f") == 0 | |
8901 | || strcmp(str + strlen(str) - 5, "any4t") == 0) | |
8902 | && (regno & 3) != 0) | |
8903 | as_warn(_("Condition code register should be 0 or 4 for %s, was %d"), | |
8904 | str, regno); | |
252b5132 | 8905 | if (*args == 'N') |
bf12938e | 8906 | INSERT_OPERAND (BCC, *ip, regno); |
252b5132 | 8907 | else |
bf12938e | 8908 | INSERT_OPERAND (CCC, *ip, regno); |
beae10d5 | 8909 | continue; |
252b5132 | 8910 | |
156c2f8b NC |
8911 | case 'H': |
8912 | if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X')) | |
8913 | s += 2; | |
3882b010 | 8914 | if (ISDIGIT (*s)) |
156c2f8b NC |
8915 | { |
8916 | c = 0; | |
8917 | do | |
8918 | { | |
8919 | c *= 10; | |
8920 | c += *s - '0'; | |
8921 | ++s; | |
8922 | } | |
3882b010 | 8923 | while (ISDIGIT (*s)); |
156c2f8b NC |
8924 | } |
8925 | else | |
8926 | c = 8; /* Invalid sel value. */ | |
8927 | ||
8928 | if (c > 7) | |
8929 | as_bad (_("invalid coprocessor sub-selection value (0-7)")); | |
8930 | ip->insn_opcode |= c; | |
8931 | continue; | |
8932 | ||
60b63b72 RS |
8933 | case 'e': |
8934 | /* Must be at least one digit. */ | |
8935 | my_getExpression (&imm_expr, s); | |
8936 | check_absolute_expr (ip, &imm_expr); | |
8937 | ||
8938 | if ((unsigned long) imm_expr.X_add_number | |
8939 | > (unsigned long) OP_MASK_VECBYTE) | |
8940 | { | |
8941 | as_bad (_("bad byte vector index (%ld)"), | |
8942 | (long) imm_expr.X_add_number); | |
8943 | imm_expr.X_add_number = 0; | |
8944 | } | |
8945 | ||
bf12938e | 8946 | INSERT_OPERAND (VECBYTE, *ip, imm_expr.X_add_number); |
60b63b72 RS |
8947 | imm_expr.X_op = O_absent; |
8948 | s = expr_end; | |
8949 | continue; | |
8950 | ||
8951 | case '%': | |
8952 | my_getExpression (&imm_expr, s); | |
8953 | check_absolute_expr (ip, &imm_expr); | |
8954 | ||
8955 | if ((unsigned long) imm_expr.X_add_number | |
8956 | > (unsigned long) OP_MASK_VECALIGN) | |
8957 | { | |
8958 | as_bad (_("bad byte vector index (%ld)"), | |
8959 | (long) imm_expr.X_add_number); | |
8960 | imm_expr.X_add_number = 0; | |
8961 | } | |
8962 | ||
bf12938e | 8963 | INSERT_OPERAND (VECALIGN, *ip, imm_expr.X_add_number); |
60b63b72 RS |
8964 | imm_expr.X_op = O_absent; |
8965 | s = expr_end; | |
8966 | continue; | |
8967 | ||
252b5132 RH |
8968 | default: |
8969 | as_bad (_("bad char = '%c'\n"), *args); | |
8970 | internalError (); | |
8971 | } | |
8972 | break; | |
8973 | } | |
8974 | /* Args don't match. */ | |
8975 | if (insn + 1 < &mips_opcodes[NUMOPCODES] && | |
8976 | !strcmp (insn->name, insn[1].name)) | |
8977 | { | |
8978 | ++insn; | |
8979 | s = argsStart; | |
268f6bed | 8980 | insn_error = _("illegal operands"); |
252b5132 RH |
8981 | continue; |
8982 | } | |
268f6bed L |
8983 | if (save_c) |
8984 | *(--s) = save_c; | |
252b5132 RH |
8985 | insn_error = _("illegal operands"); |
8986 | return; | |
8987 | } | |
8988 | } | |
8989 | ||
8990 | /* This routine assembles an instruction into its binary format when | |
8991 | assembling for the mips16. As a side effect, it sets one of the | |
8992 | global variables imm_reloc or offset_reloc to the type of | |
8993 | relocation to do if one of the operands is an address expression. | |
8994 | It also sets mips16_small and mips16_ext if the user explicitly | |
8995 | requested a small or extended instruction. */ | |
8996 | ||
8997 | static void | |
17a2f251 | 8998 | mips16_ip (char *str, struct mips_cl_insn *ip) |
252b5132 RH |
8999 | { |
9000 | char *s; | |
9001 | const char *args; | |
9002 | struct mips_opcode *insn; | |
9003 | char *argsstart; | |
9004 | unsigned int regno; | |
9005 | unsigned int lastregno = 0; | |
9006 | char *s_reset; | |
d6f16593 | 9007 | size_t i; |
252b5132 RH |
9008 | |
9009 | insn_error = NULL; | |
9010 | ||
b34976b6 AM |
9011 | mips16_small = FALSE; |
9012 | mips16_ext = FALSE; | |
252b5132 | 9013 | |
3882b010 | 9014 | for (s = str; ISLOWER (*s); ++s) |
252b5132 RH |
9015 | ; |
9016 | switch (*s) | |
9017 | { | |
9018 | case '\0': | |
9019 | break; | |
9020 | ||
9021 | case ' ': | |
9022 | *s++ = '\0'; | |
9023 | break; | |
9024 | ||
9025 | case '.': | |
9026 | if (s[1] == 't' && s[2] == ' ') | |
9027 | { | |
9028 | *s = '\0'; | |
b34976b6 | 9029 | mips16_small = TRUE; |
252b5132 RH |
9030 | s += 3; |
9031 | break; | |
9032 | } | |
9033 | else if (s[1] == 'e' && s[2] == ' ') | |
9034 | { | |
9035 | *s = '\0'; | |
b34976b6 | 9036 | mips16_ext = TRUE; |
252b5132 RH |
9037 | s += 3; |
9038 | break; | |
9039 | } | |
9040 | /* Fall through. */ | |
9041 | default: | |
9042 | insn_error = _("unknown opcode"); | |
9043 | return; | |
9044 | } | |
9045 | ||
9046 | if (mips_opts.noautoextend && ! mips16_ext) | |
b34976b6 | 9047 | mips16_small = TRUE; |
252b5132 RH |
9048 | |
9049 | if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL) | |
9050 | { | |
9051 | insn_error = _("unrecognized opcode"); | |
9052 | return; | |
9053 | } | |
9054 | ||
9055 | argsstart = s; | |
9056 | for (;;) | |
9057 | { | |
9058 | assert (strcmp (insn->name, str) == 0); | |
9059 | ||
1e915849 | 9060 | create_insn (ip, insn); |
252b5132 | 9061 | imm_expr.X_op = O_absent; |
f6688943 TS |
9062 | imm_reloc[0] = BFD_RELOC_UNUSED; |
9063 | imm_reloc[1] = BFD_RELOC_UNUSED; | |
9064 | imm_reloc[2] = BFD_RELOC_UNUSED; | |
5f74bc13 | 9065 | imm2_expr.X_op = O_absent; |
252b5132 | 9066 | offset_expr.X_op = O_absent; |
f6688943 TS |
9067 | offset_reloc[0] = BFD_RELOC_UNUSED; |
9068 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
9069 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
9070 | for (args = insn->args; 1; ++args) |
9071 | { | |
9072 | int c; | |
9073 | ||
9074 | if (*s == ' ') | |
9075 | ++s; | |
9076 | ||
9077 | /* In this switch statement we call break if we did not find | |
9078 | a match, continue if we did find a match, or return if we | |
9079 | are done. */ | |
9080 | ||
9081 | c = *args; | |
9082 | switch (c) | |
9083 | { | |
9084 | case '\0': | |
9085 | if (*s == '\0') | |
9086 | { | |
9087 | /* Stuff the immediate value in now, if we can. */ | |
9088 | if (imm_expr.X_op == O_constant | |
f6688943 | 9089 | && *imm_reloc > BFD_RELOC_UNUSED |
252b5132 RH |
9090 | && insn->pinfo != INSN_MACRO) |
9091 | { | |
d6f16593 MR |
9092 | valueT tmp; |
9093 | ||
9094 | switch (*offset_reloc) | |
9095 | { | |
9096 | case BFD_RELOC_MIPS16_HI16_S: | |
9097 | tmp = (imm_expr.X_add_number + 0x8000) >> 16; | |
9098 | break; | |
9099 | ||
9100 | case BFD_RELOC_MIPS16_HI16: | |
9101 | tmp = imm_expr.X_add_number >> 16; | |
9102 | break; | |
9103 | ||
9104 | case BFD_RELOC_MIPS16_LO16: | |
9105 | tmp = ((imm_expr.X_add_number + 0x8000) & 0xffff) | |
9106 | - 0x8000; | |
9107 | break; | |
9108 | ||
9109 | case BFD_RELOC_UNUSED: | |
9110 | tmp = imm_expr.X_add_number; | |
9111 | break; | |
9112 | ||
9113 | default: | |
9114 | internalError (); | |
9115 | } | |
9116 | *offset_reloc = BFD_RELOC_UNUSED; | |
9117 | ||
c4e7957c | 9118 | mips16_immed (NULL, 0, *imm_reloc - BFD_RELOC_UNUSED, |
d6f16593 | 9119 | tmp, TRUE, mips16_small, |
252b5132 RH |
9120 | mips16_ext, &ip->insn_opcode, |
9121 | &ip->use_extend, &ip->extend); | |
9122 | imm_expr.X_op = O_absent; | |
f6688943 | 9123 | *imm_reloc = BFD_RELOC_UNUSED; |
252b5132 RH |
9124 | } |
9125 | ||
9126 | return; | |
9127 | } | |
9128 | break; | |
9129 | ||
9130 | case ',': | |
9131 | if (*s++ == c) | |
9132 | continue; | |
9133 | s--; | |
9134 | switch (*++args) | |
9135 | { | |
9136 | case 'v': | |
bf12938e | 9137 | MIPS16_INSERT_OPERAND (RX, *ip, lastregno); |
252b5132 RH |
9138 | continue; |
9139 | case 'w': | |
bf12938e | 9140 | MIPS16_INSERT_OPERAND (RY, *ip, lastregno); |
252b5132 RH |
9141 | continue; |
9142 | } | |
9143 | break; | |
9144 | ||
9145 | case '(': | |
9146 | case ')': | |
9147 | if (*s++ == c) | |
9148 | continue; | |
9149 | break; | |
9150 | ||
9151 | case 'v': | |
9152 | case 'w': | |
9153 | if (s[0] != '$') | |
9154 | { | |
9155 | if (c == 'v') | |
bf12938e | 9156 | MIPS16_INSERT_OPERAND (RX, *ip, lastregno); |
252b5132 | 9157 | else |
bf12938e | 9158 | MIPS16_INSERT_OPERAND (RY, *ip, lastregno); |
252b5132 RH |
9159 | ++args; |
9160 | continue; | |
9161 | } | |
9162 | /* Fall through. */ | |
9163 | case 'x': | |
9164 | case 'y': | |
9165 | case 'z': | |
9166 | case 'Z': | |
9167 | case '0': | |
9168 | case 'S': | |
9169 | case 'R': | |
9170 | case 'X': | |
9171 | case 'Y': | |
9172 | if (s[0] != '$') | |
9173 | break; | |
9174 | s_reset = s; | |
3882b010 | 9175 | if (ISDIGIT (s[1])) |
252b5132 RH |
9176 | { |
9177 | ++s; | |
9178 | regno = 0; | |
9179 | do | |
9180 | { | |
9181 | regno *= 10; | |
9182 | regno += *s - '0'; | |
9183 | ++s; | |
9184 | } | |
3882b010 | 9185 | while (ISDIGIT (*s)); |
252b5132 RH |
9186 | if (regno > 31) |
9187 | { | |
9188 | as_bad (_("invalid register number (%d)"), regno); | |
9189 | regno = 2; | |
9190 | } | |
9191 | } | |
9192 | else | |
9193 | { | |
76db943d TS |
9194 | if (s[1] == 'r' && s[2] == 'a') |
9195 | { | |
9196 | s += 3; | |
9197 | regno = RA; | |
9198 | } | |
9199 | else if (s[1] == 'f' && s[2] == 'p') | |
252b5132 RH |
9200 | { |
9201 | s += 3; | |
9202 | regno = FP; | |
9203 | } | |
9204 | else if (s[1] == 's' && s[2] == 'p') | |
9205 | { | |
9206 | s += 3; | |
9207 | regno = SP; | |
9208 | } | |
9209 | else if (s[1] == 'g' && s[2] == 'p') | |
9210 | { | |
9211 | s += 3; | |
9212 | regno = GP; | |
9213 | } | |
9214 | else if (s[1] == 'a' && s[2] == 't') | |
9215 | { | |
9216 | s += 3; | |
9217 | regno = AT; | |
9218 | } | |
9219 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '0') | |
9220 | { | |
9221 | s += 4; | |
9222 | regno = KT0; | |
9223 | } | |
9224 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '1') | |
9225 | { | |
9226 | s += 4; | |
9227 | regno = KT1; | |
9228 | } | |
85b51719 TS |
9229 | else if (s[1] == 'z' && s[2] == 'e' && s[3] == 'r' && s[4] == 'o') |
9230 | { | |
9231 | s += 5; | |
9232 | regno = ZERO; | |
9233 | } | |
252b5132 RH |
9234 | else |
9235 | break; | |
9236 | } | |
9237 | ||
9238 | if (*s == ' ') | |
9239 | ++s; | |
9240 | if (args[1] != *s) | |
9241 | { | |
9242 | if (c == 'v' || c == 'w') | |
9243 | { | |
9244 | regno = mips16_to_32_reg_map[lastregno]; | |
9245 | s = s_reset; | |
f9419b05 | 9246 | ++args; |
252b5132 RH |
9247 | } |
9248 | } | |
9249 | ||
9250 | switch (c) | |
9251 | { | |
9252 | case 'x': | |
9253 | case 'y': | |
9254 | case 'z': | |
9255 | case 'v': | |
9256 | case 'w': | |
9257 | case 'Z': | |
9258 | regno = mips32_to_16_reg_map[regno]; | |
9259 | break; | |
9260 | ||
9261 | case '0': | |
9262 | if (regno != 0) | |
9263 | regno = ILLEGAL_REG; | |
9264 | break; | |
9265 | ||
9266 | case 'S': | |
9267 | if (regno != SP) | |
9268 | regno = ILLEGAL_REG; | |
9269 | break; | |
9270 | ||
9271 | case 'R': | |
9272 | if (regno != RA) | |
9273 | regno = ILLEGAL_REG; | |
9274 | break; | |
9275 | ||
9276 | case 'X': | |
9277 | case 'Y': | |
9278 | if (regno == AT && ! mips_opts.noat) | |
9279 | as_warn (_("used $at without \".set noat\"")); | |
9280 | break; | |
9281 | ||
9282 | default: | |
9283 | internalError (); | |
9284 | } | |
9285 | ||
9286 | if (regno == ILLEGAL_REG) | |
9287 | break; | |
9288 | ||
9289 | switch (c) | |
9290 | { | |
9291 | case 'x': | |
9292 | case 'v': | |
bf12938e | 9293 | MIPS16_INSERT_OPERAND (RX, *ip, regno); |
252b5132 RH |
9294 | break; |
9295 | case 'y': | |
9296 | case 'w': | |
bf12938e | 9297 | MIPS16_INSERT_OPERAND (RY, *ip, regno); |
252b5132 RH |
9298 | break; |
9299 | case 'z': | |
bf12938e | 9300 | MIPS16_INSERT_OPERAND (RZ, *ip, regno); |
252b5132 RH |
9301 | break; |
9302 | case 'Z': | |
bf12938e | 9303 | MIPS16_INSERT_OPERAND (MOVE32Z, *ip, regno); |
252b5132 RH |
9304 | case '0': |
9305 | case 'S': | |
9306 | case 'R': | |
9307 | break; | |
9308 | case 'X': | |
bf12938e | 9309 | MIPS16_INSERT_OPERAND (REGR32, *ip, regno); |
252b5132 RH |
9310 | break; |
9311 | case 'Y': | |
9312 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); | |
bf12938e | 9313 | MIPS16_INSERT_OPERAND (REG32R, *ip, regno); |
252b5132 RH |
9314 | break; |
9315 | default: | |
9316 | internalError (); | |
9317 | } | |
9318 | ||
9319 | lastregno = regno; | |
9320 | continue; | |
9321 | ||
9322 | case 'P': | |
9323 | if (strncmp (s, "$pc", 3) == 0) | |
9324 | { | |
9325 | s += 3; | |
9326 | continue; | |
9327 | } | |
9328 | break; | |
9329 | ||
252b5132 RH |
9330 | case '5': |
9331 | case 'H': | |
9332 | case 'W': | |
9333 | case 'D': | |
9334 | case 'j': | |
252b5132 RH |
9335 | case 'V': |
9336 | case 'C': | |
9337 | case 'U': | |
9338 | case 'k': | |
9339 | case 'K': | |
d6f16593 MR |
9340 | i = my_getSmallExpression (&imm_expr, imm_reloc, s); |
9341 | if (i > 0) | |
252b5132 | 9342 | { |
d6f16593 | 9343 | if (imm_expr.X_op != O_constant) |
252b5132 | 9344 | { |
b34976b6 | 9345 | mips16_ext = TRUE; |
b34976b6 | 9346 | ip->use_extend = TRUE; |
252b5132 | 9347 | ip->extend = 0; |
252b5132 | 9348 | } |
d6f16593 MR |
9349 | else |
9350 | { | |
9351 | /* We need to relax this instruction. */ | |
9352 | *offset_reloc = *imm_reloc; | |
9353 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; | |
9354 | } | |
9355 | s = expr_end; | |
9356 | continue; | |
252b5132 | 9357 | } |
d6f16593 MR |
9358 | *imm_reloc = BFD_RELOC_UNUSED; |
9359 | /* Fall through. */ | |
9360 | case '<': | |
9361 | case '>': | |
9362 | case '[': | |
9363 | case ']': | |
9364 | case '4': | |
9365 | case '8': | |
9366 | my_getExpression (&imm_expr, s); | |
252b5132 RH |
9367 | if (imm_expr.X_op == O_register) |
9368 | { | |
9369 | /* What we thought was an expression turned out to | |
9370 | be a register. */ | |
9371 | ||
9372 | if (s[0] == '(' && args[1] == '(') | |
9373 | { | |
9374 | /* It looks like the expression was omitted | |
9375 | before a register indirection, which means | |
9376 | that the expression is implicitly zero. We | |
9377 | still set up imm_expr, so that we handle | |
9378 | explicit extensions correctly. */ | |
9379 | imm_expr.X_op = O_constant; | |
9380 | imm_expr.X_add_number = 0; | |
f6688943 | 9381 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
9382 | continue; |
9383 | } | |
9384 | ||
9385 | break; | |
9386 | } | |
9387 | ||
9388 | /* We need to relax this instruction. */ | |
f6688943 | 9389 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
9390 | s = expr_end; |
9391 | continue; | |
9392 | ||
9393 | case 'p': | |
9394 | case 'q': | |
9395 | case 'A': | |
9396 | case 'B': | |
9397 | case 'E': | |
9398 | /* We use offset_reloc rather than imm_reloc for the PC | |
9399 | relative operands. This lets macros with both | |
9400 | immediate and address operands work correctly. */ | |
9401 | my_getExpression (&offset_expr, s); | |
9402 | ||
9403 | if (offset_expr.X_op == O_register) | |
9404 | break; | |
9405 | ||
9406 | /* We need to relax this instruction. */ | |
f6688943 | 9407 | *offset_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
9408 | s = expr_end; |
9409 | continue; | |
9410 | ||
9411 | case '6': /* break code */ | |
9412 | my_getExpression (&imm_expr, s); | |
9413 | check_absolute_expr (ip, &imm_expr); | |
9414 | if ((unsigned long) imm_expr.X_add_number > 63) | |
bf12938e RS |
9415 | as_warn (_("Invalid value for `%s' (%lu)"), |
9416 | ip->insn_mo->name, | |
9417 | (unsigned long) imm_expr.X_add_number); | |
9418 | MIPS16_INSERT_OPERAND (IMM6, *ip, imm_expr.X_add_number); | |
252b5132 RH |
9419 | imm_expr.X_op = O_absent; |
9420 | s = expr_end; | |
9421 | continue; | |
9422 | ||
9423 | case 'a': /* 26 bit address */ | |
9424 | my_getExpression (&offset_expr, s); | |
9425 | s = expr_end; | |
f6688943 | 9426 | *offset_reloc = BFD_RELOC_MIPS16_JMP; |
252b5132 RH |
9427 | ip->insn_opcode <<= 16; |
9428 | continue; | |
9429 | ||
9430 | case 'l': /* register list for entry macro */ | |
9431 | case 'L': /* register list for exit macro */ | |
9432 | { | |
9433 | int mask; | |
9434 | ||
9435 | if (c == 'l') | |
9436 | mask = 0; | |
9437 | else | |
9438 | mask = 7 << 3; | |
9439 | while (*s != '\0') | |
9440 | { | |
9441 | int freg, reg1, reg2; | |
9442 | ||
9443 | while (*s == ' ' || *s == ',') | |
9444 | ++s; | |
9445 | if (*s != '$') | |
9446 | { | |
9447 | as_bad (_("can't parse register list")); | |
9448 | break; | |
9449 | } | |
9450 | ++s; | |
9451 | if (*s != 'f') | |
9452 | freg = 0; | |
9453 | else | |
9454 | { | |
9455 | freg = 1; | |
9456 | ++s; | |
9457 | } | |
9458 | reg1 = 0; | |
3882b010 | 9459 | while (ISDIGIT (*s)) |
252b5132 RH |
9460 | { |
9461 | reg1 *= 10; | |
9462 | reg1 += *s - '0'; | |
9463 | ++s; | |
9464 | } | |
9465 | if (*s == ' ') | |
9466 | ++s; | |
9467 | if (*s != '-') | |
9468 | reg2 = reg1; | |
9469 | else | |
9470 | { | |
9471 | ++s; | |
9472 | if (*s != '$') | |
9473 | break; | |
9474 | ++s; | |
9475 | if (freg) | |
9476 | { | |
9477 | if (*s == 'f') | |
9478 | ++s; | |
9479 | else | |
9480 | { | |
9481 | as_bad (_("invalid register list")); | |
9482 | break; | |
9483 | } | |
9484 | } | |
9485 | reg2 = 0; | |
3882b010 | 9486 | while (ISDIGIT (*s)) |
252b5132 RH |
9487 | { |
9488 | reg2 *= 10; | |
9489 | reg2 += *s - '0'; | |
9490 | ++s; | |
9491 | } | |
9492 | } | |
9493 | if (freg && reg1 == 0 && reg2 == 0 && c == 'L') | |
9494 | { | |
9495 | mask &= ~ (7 << 3); | |
9496 | mask |= 5 << 3; | |
9497 | } | |
9498 | else if (freg && reg1 == 0 && reg2 == 1 && c == 'L') | |
9499 | { | |
9500 | mask &= ~ (7 << 3); | |
9501 | mask |= 6 << 3; | |
9502 | } | |
9503 | else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L') | |
9504 | mask |= (reg2 - 3) << 3; | |
9505 | else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17) | |
9506 | mask |= (reg2 - 15) << 1; | |
f9419b05 | 9507 | else if (reg1 == RA && reg2 == RA) |
252b5132 RH |
9508 | mask |= 1; |
9509 | else | |
9510 | { | |
9511 | as_bad (_("invalid register list")); | |
9512 | break; | |
9513 | } | |
9514 | } | |
9515 | /* The mask is filled in in the opcode table for the | |
9516 | benefit of the disassembler. We remove it before | |
9517 | applying the actual mask. */ | |
9518 | ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6); | |
9519 | ip->insn_opcode |= mask << MIPS16OP_SH_IMM6; | |
9520 | } | |
9521 | continue; | |
9522 | ||
9523 | case 'e': /* extend code */ | |
9524 | my_getExpression (&imm_expr, s); | |
9525 | check_absolute_expr (ip, &imm_expr); | |
9526 | if ((unsigned long) imm_expr.X_add_number > 0x7ff) | |
9527 | { | |
9528 | as_warn (_("Invalid value for `%s' (%lu)"), | |
9529 | ip->insn_mo->name, | |
9530 | (unsigned long) imm_expr.X_add_number); | |
9531 | imm_expr.X_add_number &= 0x7ff; | |
9532 | } | |
9533 | ip->insn_opcode |= imm_expr.X_add_number; | |
9534 | imm_expr.X_op = O_absent; | |
9535 | s = expr_end; | |
9536 | continue; | |
9537 | ||
9538 | default: | |
9539 | internalError (); | |
9540 | } | |
9541 | break; | |
9542 | } | |
9543 | ||
9544 | /* Args don't match. */ | |
9545 | if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] && | |
9546 | strcmp (insn->name, insn[1].name) == 0) | |
9547 | { | |
9548 | ++insn; | |
9549 | s = argsstart; | |
9550 | continue; | |
9551 | } | |
9552 | ||
9553 | insn_error = _("illegal operands"); | |
9554 | ||
9555 | return; | |
9556 | } | |
9557 | } | |
9558 | ||
9559 | /* This structure holds information we know about a mips16 immediate | |
9560 | argument type. */ | |
9561 | ||
e972090a NC |
9562 | struct mips16_immed_operand |
9563 | { | |
252b5132 RH |
9564 | /* The type code used in the argument string in the opcode table. */ |
9565 | int type; | |
9566 | /* The number of bits in the short form of the opcode. */ | |
9567 | int nbits; | |
9568 | /* The number of bits in the extended form of the opcode. */ | |
9569 | int extbits; | |
9570 | /* The amount by which the short form is shifted when it is used; | |
9571 | for example, the sw instruction has a shift count of 2. */ | |
9572 | int shift; | |
9573 | /* The amount by which the short form is shifted when it is stored | |
9574 | into the instruction code. */ | |
9575 | int op_shift; | |
9576 | /* Non-zero if the short form is unsigned. */ | |
9577 | int unsp; | |
9578 | /* Non-zero if the extended form is unsigned. */ | |
9579 | int extu; | |
9580 | /* Non-zero if the value is PC relative. */ | |
9581 | int pcrel; | |
9582 | }; | |
9583 | ||
9584 | /* The mips16 immediate operand types. */ | |
9585 | ||
9586 | static const struct mips16_immed_operand mips16_immed_operands[] = | |
9587 | { | |
9588 | { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
9589 | { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
9590 | { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
9591 | { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
9592 | { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 }, | |
9593 | { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
9594 | { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
9595 | { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
9596 | { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
9597 | { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 }, | |
9598 | { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
9599 | { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
9600 | { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
9601 | { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 }, | |
9602 | { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
9603 | { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
9604 | { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
9605 | { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
9606 | { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 }, | |
9607 | { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 }, | |
9608 | { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 } | |
9609 | }; | |
9610 | ||
9611 | #define MIPS16_NUM_IMMED \ | |
9612 | (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0]) | |
9613 | ||
9614 | /* Handle a mips16 instruction with an immediate value. This or's the | |
9615 | small immediate value into *INSN. It sets *USE_EXTEND to indicate | |
9616 | whether an extended value is needed; if one is needed, it sets | |
9617 | *EXTEND to the value. The argument type is TYPE. The value is VAL. | |
9618 | If SMALL is true, an unextended opcode was explicitly requested. | |
9619 | If EXT is true, an extended opcode was explicitly requested. If | |
9620 | WARN is true, warn if EXT does not match reality. */ | |
9621 | ||
9622 | static void | |
17a2f251 TS |
9623 | mips16_immed (char *file, unsigned int line, int type, offsetT val, |
9624 | bfd_boolean warn, bfd_boolean small, bfd_boolean ext, | |
9625 | unsigned long *insn, bfd_boolean *use_extend, | |
9626 | unsigned short *extend) | |
252b5132 RH |
9627 | { |
9628 | register const struct mips16_immed_operand *op; | |
9629 | int mintiny, maxtiny; | |
b34976b6 | 9630 | bfd_boolean needext; |
252b5132 RH |
9631 | |
9632 | op = mips16_immed_operands; | |
9633 | while (op->type != type) | |
9634 | { | |
9635 | ++op; | |
9636 | assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); | |
9637 | } | |
9638 | ||
9639 | if (op->unsp) | |
9640 | { | |
9641 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
9642 | { | |
9643 | mintiny = 1; | |
9644 | maxtiny = 1 << op->nbits; | |
9645 | } | |
9646 | else | |
9647 | { | |
9648 | mintiny = 0; | |
9649 | maxtiny = (1 << op->nbits) - 1; | |
9650 | } | |
9651 | } | |
9652 | else | |
9653 | { | |
9654 | mintiny = - (1 << (op->nbits - 1)); | |
9655 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
9656 | } | |
9657 | ||
9658 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
9659 | if (type == 'p' || type == 'q') | |
9660 | val /= 2; | |
9661 | ||
9662 | if ((val & ((1 << op->shift) - 1)) != 0 | |
9663 | || val < (mintiny << op->shift) | |
9664 | || val > (maxtiny << op->shift)) | |
b34976b6 | 9665 | needext = TRUE; |
252b5132 | 9666 | else |
b34976b6 | 9667 | needext = FALSE; |
252b5132 RH |
9668 | |
9669 | if (warn && ext && ! needext) | |
beae10d5 KH |
9670 | as_warn_where (file, line, |
9671 | _("extended operand requested but not required")); | |
252b5132 RH |
9672 | if (small && needext) |
9673 | as_bad_where (file, line, _("invalid unextended operand value")); | |
9674 | ||
9675 | if (small || (! ext && ! needext)) | |
9676 | { | |
9677 | int insnval; | |
9678 | ||
b34976b6 | 9679 | *use_extend = FALSE; |
252b5132 RH |
9680 | insnval = ((val >> op->shift) & ((1 << op->nbits) - 1)); |
9681 | insnval <<= op->op_shift; | |
9682 | *insn |= insnval; | |
9683 | } | |
9684 | else | |
9685 | { | |
9686 | long minext, maxext; | |
9687 | int extval; | |
9688 | ||
9689 | if (op->extu) | |
9690 | { | |
9691 | minext = 0; | |
9692 | maxext = (1 << op->extbits) - 1; | |
9693 | } | |
9694 | else | |
9695 | { | |
9696 | minext = - (1 << (op->extbits - 1)); | |
9697 | maxext = (1 << (op->extbits - 1)) - 1; | |
9698 | } | |
9699 | if (val < minext || val > maxext) | |
9700 | as_bad_where (file, line, | |
9701 | _("operand value out of range for instruction")); | |
9702 | ||
b34976b6 | 9703 | *use_extend = TRUE; |
252b5132 RH |
9704 | if (op->extbits == 16) |
9705 | { | |
9706 | extval = ((val >> 11) & 0x1f) | (val & 0x7e0); | |
9707 | val &= 0x1f; | |
9708 | } | |
9709 | else if (op->extbits == 15) | |
9710 | { | |
9711 | extval = ((val >> 11) & 0xf) | (val & 0x7f0); | |
9712 | val &= 0xf; | |
9713 | } | |
9714 | else | |
9715 | { | |
9716 | extval = ((val & 0x1f) << 6) | (val & 0x20); | |
9717 | val = 0; | |
9718 | } | |
9719 | ||
9720 | *extend = (unsigned short) extval; | |
9721 | *insn |= val; | |
9722 | } | |
9723 | } | |
9724 | \f | |
d6f16593 | 9725 | struct percent_op_match |
ad8d3bb3 | 9726 | { |
5e0116d5 RS |
9727 | const char *str; |
9728 | bfd_reloc_code_real_type reloc; | |
d6f16593 MR |
9729 | }; |
9730 | ||
9731 | static const struct percent_op_match mips_percent_op[] = | |
ad8d3bb3 | 9732 | { |
5e0116d5 | 9733 | {"%lo", BFD_RELOC_LO16}, |
ad8d3bb3 | 9734 | #ifdef OBJ_ELF |
5e0116d5 RS |
9735 | {"%call_hi", BFD_RELOC_MIPS_CALL_HI16}, |
9736 | {"%call_lo", BFD_RELOC_MIPS_CALL_LO16}, | |
9737 | {"%call16", BFD_RELOC_MIPS_CALL16}, | |
9738 | {"%got_disp", BFD_RELOC_MIPS_GOT_DISP}, | |
9739 | {"%got_page", BFD_RELOC_MIPS_GOT_PAGE}, | |
9740 | {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST}, | |
9741 | {"%got_hi", BFD_RELOC_MIPS_GOT_HI16}, | |
9742 | {"%got_lo", BFD_RELOC_MIPS_GOT_LO16}, | |
9743 | {"%got", BFD_RELOC_MIPS_GOT16}, | |
9744 | {"%gp_rel", BFD_RELOC_GPREL16}, | |
9745 | {"%half", BFD_RELOC_16}, | |
9746 | {"%highest", BFD_RELOC_MIPS_HIGHEST}, | |
9747 | {"%higher", BFD_RELOC_MIPS_HIGHER}, | |
9748 | {"%neg", BFD_RELOC_MIPS_SUB}, | |
3f98094e DJ |
9749 | {"%tlsgd", BFD_RELOC_MIPS_TLS_GD}, |
9750 | {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM}, | |
9751 | {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16}, | |
9752 | {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16}, | |
9753 | {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16}, | |
9754 | {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16}, | |
9755 | {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL}, | |
ad8d3bb3 | 9756 | #endif |
5e0116d5 | 9757 | {"%hi", BFD_RELOC_HI16_S} |
ad8d3bb3 TS |
9758 | }; |
9759 | ||
d6f16593 MR |
9760 | static const struct percent_op_match mips16_percent_op[] = |
9761 | { | |
9762 | {"%lo", BFD_RELOC_MIPS16_LO16}, | |
9763 | {"%gprel", BFD_RELOC_MIPS16_GPREL}, | |
9764 | {"%hi", BFD_RELOC_MIPS16_HI16_S} | |
9765 | }; | |
9766 | ||
252b5132 | 9767 | |
5e0116d5 RS |
9768 | /* Return true if *STR points to a relocation operator. When returning true, |
9769 | move *STR over the operator and store its relocation code in *RELOC. | |
9770 | Leave both *STR and *RELOC alone when returning false. */ | |
9771 | ||
9772 | static bfd_boolean | |
17a2f251 | 9773 | parse_relocation (char **str, bfd_reloc_code_real_type *reloc) |
252b5132 | 9774 | { |
d6f16593 MR |
9775 | const struct percent_op_match *percent_op; |
9776 | size_t limit, i; | |
9777 | ||
9778 | if (mips_opts.mips16) | |
9779 | { | |
9780 | percent_op = mips16_percent_op; | |
9781 | limit = ARRAY_SIZE (mips16_percent_op); | |
9782 | } | |
9783 | else | |
9784 | { | |
9785 | percent_op = mips_percent_op; | |
9786 | limit = ARRAY_SIZE (mips_percent_op); | |
9787 | } | |
76b3015f | 9788 | |
d6f16593 | 9789 | for (i = 0; i < limit; i++) |
5e0116d5 | 9790 | if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0) |
394f9b3a | 9791 | { |
3f98094e DJ |
9792 | int len = strlen (percent_op[i].str); |
9793 | ||
9794 | if (!ISSPACE ((*str)[len]) && (*str)[len] != '(') | |
9795 | continue; | |
9796 | ||
5e0116d5 RS |
9797 | *str += strlen (percent_op[i].str); |
9798 | *reloc = percent_op[i].reloc; | |
394f9b3a | 9799 | |
5e0116d5 RS |
9800 | /* Check whether the output BFD supports this relocation. |
9801 | If not, issue an error and fall back on something safe. */ | |
9802 | if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc)) | |
394f9b3a | 9803 | { |
5e0116d5 RS |
9804 | as_bad ("relocation %s isn't supported by the current ABI", |
9805 | percent_op[i].str); | |
01a3f561 | 9806 | *reloc = BFD_RELOC_UNUSED; |
394f9b3a | 9807 | } |
5e0116d5 | 9808 | return TRUE; |
394f9b3a | 9809 | } |
5e0116d5 | 9810 | return FALSE; |
394f9b3a | 9811 | } |
ad8d3bb3 | 9812 | |
ad8d3bb3 | 9813 | |
5e0116d5 RS |
9814 | /* Parse string STR as a 16-bit relocatable operand. Store the |
9815 | expression in *EP and the relocations in the array starting | |
9816 | at RELOC. Return the number of relocation operators used. | |
ad8d3bb3 | 9817 | |
01a3f561 | 9818 | On exit, EXPR_END points to the first character after the expression. */ |
ad8d3bb3 | 9819 | |
5e0116d5 | 9820 | static size_t |
17a2f251 TS |
9821 | my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc, |
9822 | char *str) | |
ad8d3bb3 | 9823 | { |
5e0116d5 RS |
9824 | bfd_reloc_code_real_type reversed_reloc[3]; |
9825 | size_t reloc_index, i; | |
09b8f35a RS |
9826 | int crux_depth, str_depth; |
9827 | char *crux; | |
5e0116d5 RS |
9828 | |
9829 | /* Search for the start of the main expression, recoding relocations | |
09b8f35a RS |
9830 | in REVERSED_RELOC. End the loop with CRUX pointing to the start |
9831 | of the main expression and with CRUX_DEPTH containing the number | |
9832 | of open brackets at that point. */ | |
9833 | reloc_index = -1; | |
9834 | str_depth = 0; | |
9835 | do | |
fb1b3232 | 9836 | { |
09b8f35a RS |
9837 | reloc_index++; |
9838 | crux = str; | |
9839 | crux_depth = str_depth; | |
9840 | ||
9841 | /* Skip over whitespace and brackets, keeping count of the number | |
9842 | of brackets. */ | |
9843 | while (*str == ' ' || *str == '\t' || *str == '(') | |
9844 | if (*str++ == '(') | |
9845 | str_depth++; | |
5e0116d5 | 9846 | } |
09b8f35a RS |
9847 | while (*str == '%' |
9848 | && reloc_index < (HAVE_NEWABI ? 3 : 1) | |
9849 | && parse_relocation (&str, &reversed_reloc[reloc_index])); | |
ad8d3bb3 | 9850 | |
09b8f35a | 9851 | my_getExpression (ep, crux); |
5e0116d5 | 9852 | str = expr_end; |
394f9b3a | 9853 | |
5e0116d5 | 9854 | /* Match every open bracket. */ |
09b8f35a | 9855 | while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t')) |
5e0116d5 | 9856 | if (*str++ == ')') |
09b8f35a | 9857 | crux_depth--; |
394f9b3a | 9858 | |
09b8f35a | 9859 | if (crux_depth > 0) |
5e0116d5 | 9860 | as_bad ("unclosed '('"); |
394f9b3a | 9861 | |
5e0116d5 | 9862 | expr_end = str; |
252b5132 | 9863 | |
01a3f561 | 9864 | if (reloc_index != 0) |
64bdfcaf RS |
9865 | { |
9866 | prev_reloc_op_frag = frag_now; | |
9867 | for (i = 0; i < reloc_index; i++) | |
9868 | reloc[i] = reversed_reloc[reloc_index - 1 - i]; | |
9869 | } | |
fb1b3232 | 9870 | |
5e0116d5 | 9871 | return reloc_index; |
252b5132 RH |
9872 | } |
9873 | ||
9874 | static void | |
17a2f251 | 9875 | my_getExpression (expressionS *ep, char *str) |
252b5132 RH |
9876 | { |
9877 | char *save_in; | |
98aa84af | 9878 | valueT val; |
252b5132 RH |
9879 | |
9880 | save_in = input_line_pointer; | |
9881 | input_line_pointer = str; | |
9882 | expression (ep); | |
9883 | expr_end = input_line_pointer; | |
9884 | input_line_pointer = save_in; | |
9885 | ||
9886 | /* If we are in mips16 mode, and this is an expression based on `.', | |
9887 | then we bump the value of the symbol by 1 since that is how other | |
9888 | text symbols are handled. We don't bother to handle complex | |
9889 | expressions, just `.' plus or minus a constant. */ | |
9890 | if (mips_opts.mips16 | |
9891 | && ep->X_op == O_symbol | |
9892 | && strcmp (S_GET_NAME (ep->X_add_symbol), FAKE_LABEL_NAME) == 0 | |
9893 | && S_GET_SEGMENT (ep->X_add_symbol) == now_seg | |
49309057 ILT |
9894 | && symbol_get_frag (ep->X_add_symbol) == frag_now |
9895 | && symbol_constant_p (ep->X_add_symbol) | |
98aa84af AM |
9896 | && (val = S_GET_VALUE (ep->X_add_symbol)) == frag_now_fix ()) |
9897 | S_SET_VALUE (ep->X_add_symbol, val + 1); | |
252b5132 RH |
9898 | } |
9899 | ||
9900 | /* Turn a string in input_line_pointer into a floating point constant | |
bc0d738a NC |
9901 | of type TYPE, and store the appropriate bytes in *LITP. The number |
9902 | of LITTLENUMS emitted is stored in *SIZEP. An error message is | |
252b5132 RH |
9903 | returned, or NULL on OK. */ |
9904 | ||
9905 | char * | |
17a2f251 | 9906 | md_atof (int type, char *litP, int *sizeP) |
252b5132 RH |
9907 | { |
9908 | int prec; | |
9909 | LITTLENUM_TYPE words[4]; | |
9910 | char *t; | |
9911 | int i; | |
9912 | ||
9913 | switch (type) | |
9914 | { | |
9915 | case 'f': | |
9916 | prec = 2; | |
9917 | break; | |
9918 | ||
9919 | case 'd': | |
9920 | prec = 4; | |
9921 | break; | |
9922 | ||
9923 | default: | |
9924 | *sizeP = 0; | |
9925 | return _("bad call to md_atof"); | |
9926 | } | |
9927 | ||
9928 | t = atof_ieee (input_line_pointer, type, words); | |
9929 | if (t) | |
9930 | input_line_pointer = t; | |
9931 | ||
9932 | *sizeP = prec * 2; | |
9933 | ||
9934 | if (! target_big_endian) | |
9935 | { | |
9936 | for (i = prec - 1; i >= 0; i--) | |
9937 | { | |
17a2f251 | 9938 | md_number_to_chars (litP, words[i], 2); |
252b5132 RH |
9939 | litP += 2; |
9940 | } | |
9941 | } | |
9942 | else | |
9943 | { | |
9944 | for (i = 0; i < prec; i++) | |
9945 | { | |
17a2f251 | 9946 | md_number_to_chars (litP, words[i], 2); |
252b5132 RH |
9947 | litP += 2; |
9948 | } | |
9949 | } | |
bdaaa2e1 | 9950 | |
252b5132 RH |
9951 | return NULL; |
9952 | } | |
9953 | ||
9954 | void | |
17a2f251 | 9955 | md_number_to_chars (char *buf, valueT val, int n) |
252b5132 RH |
9956 | { |
9957 | if (target_big_endian) | |
9958 | number_to_chars_bigendian (buf, val, n); | |
9959 | else | |
9960 | number_to_chars_littleendian (buf, val, n); | |
9961 | } | |
9962 | \f | |
ae948b86 | 9963 | #ifdef OBJ_ELF |
e013f690 TS |
9964 | static int support_64bit_objects(void) |
9965 | { | |
9966 | const char **list, **l; | |
aa3d8fdf | 9967 | int yes; |
e013f690 TS |
9968 | |
9969 | list = bfd_target_list (); | |
9970 | for (l = list; *l != NULL; l++) | |
9971 | #ifdef TE_TMIPS | |
9972 | /* This is traditional mips */ | |
9973 | if (strcmp (*l, "elf64-tradbigmips") == 0 | |
9974 | || strcmp (*l, "elf64-tradlittlemips") == 0) | |
9975 | #else | |
9976 | if (strcmp (*l, "elf64-bigmips") == 0 | |
9977 | || strcmp (*l, "elf64-littlemips") == 0) | |
9978 | #endif | |
9979 | break; | |
aa3d8fdf | 9980 | yes = (*l != NULL); |
e013f690 | 9981 | free (list); |
aa3d8fdf | 9982 | return yes; |
e013f690 | 9983 | } |
ae948b86 | 9984 | #endif /* OBJ_ELF */ |
e013f690 | 9985 | |
78849248 | 9986 | const char *md_shortopts = "O::g::G:"; |
252b5132 | 9987 | |
e972090a NC |
9988 | struct option md_longopts[] = |
9989 | { | |
f9b4148d CD |
9990 | /* Options which specify architecture. */ |
9991 | #define OPTION_ARCH_BASE (OPTION_MD_BASE) | |
9992 | #define OPTION_MARCH (OPTION_ARCH_BASE + 0) | |
9993 | {"march", required_argument, NULL, OPTION_MARCH}, | |
9994 | #define OPTION_MTUNE (OPTION_ARCH_BASE + 1) | |
9995 | {"mtune", required_argument, NULL, OPTION_MTUNE}, | |
9996 | #define OPTION_MIPS1 (OPTION_ARCH_BASE + 2) | |
252b5132 RH |
9997 | {"mips0", no_argument, NULL, OPTION_MIPS1}, |
9998 | {"mips1", no_argument, NULL, OPTION_MIPS1}, | |
f9b4148d | 9999 | #define OPTION_MIPS2 (OPTION_ARCH_BASE + 3) |
252b5132 | 10000 | {"mips2", no_argument, NULL, OPTION_MIPS2}, |
f9b4148d | 10001 | #define OPTION_MIPS3 (OPTION_ARCH_BASE + 4) |
252b5132 | 10002 | {"mips3", no_argument, NULL, OPTION_MIPS3}, |
f9b4148d | 10003 | #define OPTION_MIPS4 (OPTION_ARCH_BASE + 5) |
252b5132 | 10004 | {"mips4", no_argument, NULL, OPTION_MIPS4}, |
f9b4148d | 10005 | #define OPTION_MIPS5 (OPTION_ARCH_BASE + 6) |
ae948b86 | 10006 | {"mips5", no_argument, NULL, OPTION_MIPS5}, |
f9b4148d | 10007 | #define OPTION_MIPS32 (OPTION_ARCH_BASE + 7) |
ae948b86 | 10008 | {"mips32", no_argument, NULL, OPTION_MIPS32}, |
f9b4148d | 10009 | #define OPTION_MIPS64 (OPTION_ARCH_BASE + 8) |
ae948b86 | 10010 | {"mips64", no_argument, NULL, OPTION_MIPS64}, |
f9b4148d CD |
10011 | #define OPTION_MIPS32R2 (OPTION_ARCH_BASE + 9) |
10012 | {"mips32r2", no_argument, NULL, OPTION_MIPS32R2}, | |
5f74bc13 CD |
10013 | #define OPTION_MIPS64R2 (OPTION_ARCH_BASE + 10) |
10014 | {"mips64r2", no_argument, NULL, OPTION_MIPS64R2}, | |
f9b4148d CD |
10015 | |
10016 | /* Options which specify Application Specific Extensions (ASEs). */ | |
5f74bc13 | 10017 | #define OPTION_ASE_BASE (OPTION_ARCH_BASE + 11) |
f9b4148d CD |
10018 | #define OPTION_MIPS16 (OPTION_ASE_BASE + 0) |
10019 | {"mips16", no_argument, NULL, OPTION_MIPS16}, | |
10020 | #define OPTION_NO_MIPS16 (OPTION_ASE_BASE + 1) | |
10021 | {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16}, | |
10022 | #define OPTION_MIPS3D (OPTION_ASE_BASE + 2) | |
10023 | {"mips3d", no_argument, NULL, OPTION_MIPS3D}, | |
10024 | #define OPTION_NO_MIPS3D (OPTION_ASE_BASE + 3) | |
10025 | {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D}, | |
10026 | #define OPTION_MDMX (OPTION_ASE_BASE + 4) | |
10027 | {"mdmx", no_argument, NULL, OPTION_MDMX}, | |
10028 | #define OPTION_NO_MDMX (OPTION_ASE_BASE + 5) | |
10029 | {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX}, | |
10030 | ||
10031 | /* Old-style architecture options. Don't add more of these. */ | |
10032 | #define OPTION_COMPAT_ARCH_BASE (OPTION_ASE_BASE + 6) | |
10033 | #define OPTION_M4650 (OPTION_COMPAT_ARCH_BASE + 0) | |
10034 | {"m4650", no_argument, NULL, OPTION_M4650}, | |
10035 | #define OPTION_NO_M4650 (OPTION_COMPAT_ARCH_BASE + 1) | |
10036 | {"no-m4650", no_argument, NULL, OPTION_NO_M4650}, | |
10037 | #define OPTION_M4010 (OPTION_COMPAT_ARCH_BASE + 2) | |
10038 | {"m4010", no_argument, NULL, OPTION_M4010}, | |
10039 | #define OPTION_NO_M4010 (OPTION_COMPAT_ARCH_BASE + 3) | |
10040 | {"no-m4010", no_argument, NULL, OPTION_NO_M4010}, | |
10041 | #define OPTION_M4100 (OPTION_COMPAT_ARCH_BASE + 4) | |
10042 | {"m4100", no_argument, NULL, OPTION_M4100}, | |
10043 | #define OPTION_NO_M4100 (OPTION_COMPAT_ARCH_BASE + 5) | |
10044 | {"no-m4100", no_argument, NULL, OPTION_NO_M4100}, | |
10045 | #define OPTION_M3900 (OPTION_COMPAT_ARCH_BASE + 6) | |
10046 | {"m3900", no_argument, NULL, OPTION_M3900}, | |
10047 | #define OPTION_NO_M3900 (OPTION_COMPAT_ARCH_BASE + 7) | |
10048 | {"no-m3900", no_argument, NULL, OPTION_NO_M3900}, | |
10049 | ||
10050 | /* Options which enable bug fixes. */ | |
10051 | #define OPTION_FIX_BASE (OPTION_COMPAT_ARCH_BASE + 8) | |
10052 | #define OPTION_M7000_HILO_FIX (OPTION_FIX_BASE + 0) | |
10053 | {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX}, | |
10054 | #define OPTION_MNO_7000_HILO_FIX (OPTION_FIX_BASE + 1) | |
10055 | {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, | |
10056 | {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, | |
d766e8ec RS |
10057 | #define OPTION_FIX_VR4120 (OPTION_FIX_BASE + 2) |
10058 | #define OPTION_NO_FIX_VR4120 (OPTION_FIX_BASE + 3) | |
10059 | {"mfix-vr4120", no_argument, NULL, OPTION_FIX_VR4120}, | |
10060 | {"mno-fix-vr4120", no_argument, NULL, OPTION_NO_FIX_VR4120}, | |
f9b4148d CD |
10061 | |
10062 | /* Miscellaneous options. */ | |
10063 | #define OPTION_MISC_BASE (OPTION_FIX_BASE + 4) | |
1ffcab4b | 10064 | #define OPTION_TRAP (OPTION_MISC_BASE + 0) |
252b5132 RH |
10065 | {"trap", no_argument, NULL, OPTION_TRAP}, |
10066 | {"no-break", no_argument, NULL, OPTION_TRAP}, | |
1ffcab4b | 10067 | #define OPTION_BREAK (OPTION_MISC_BASE + 1) |
252b5132 RH |
10068 | {"break", no_argument, NULL, OPTION_BREAK}, |
10069 | {"no-trap", no_argument, NULL, OPTION_BREAK}, | |
1ffcab4b | 10070 | #define OPTION_EB (OPTION_MISC_BASE + 2) |
252b5132 | 10071 | {"EB", no_argument, NULL, OPTION_EB}, |
1ffcab4b | 10072 | #define OPTION_EL (OPTION_MISC_BASE + 3) |
252b5132 | 10073 | {"EL", no_argument, NULL, OPTION_EL}, |
1ffcab4b | 10074 | #define OPTION_FP32 (OPTION_MISC_BASE + 4) |
ae948b86 | 10075 | {"mfp32", no_argument, NULL, OPTION_FP32}, |
1ffcab4b | 10076 | #define OPTION_GP32 (OPTION_MISC_BASE + 5) |
c97ef257 | 10077 | {"mgp32", no_argument, NULL, OPTION_GP32}, |
1ffcab4b | 10078 | #define OPTION_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 6) |
119d663a | 10079 | {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS}, |
1ffcab4b | 10080 | #define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 7) |
119d663a | 10081 | {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS}, |
1ffcab4b | 10082 | #define OPTION_FP64 (OPTION_MISC_BASE + 8) |
316f5878 | 10083 | {"mfp64", no_argument, NULL, OPTION_FP64}, |
1ffcab4b | 10084 | #define OPTION_GP64 (OPTION_MISC_BASE + 9) |
ae948b86 | 10085 | {"mgp64", no_argument, NULL, OPTION_GP64}, |
1ffcab4b CD |
10086 | #define OPTION_RELAX_BRANCH (OPTION_MISC_BASE + 10) |
10087 | #define OPTION_NO_RELAX_BRANCH (OPTION_MISC_BASE + 11) | |
4a6a3df4 AO |
10088 | {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH}, |
10089 | {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH}, | |
aa6975fb ILT |
10090 | #define OPTION_MSHARED (OPTION_MISC_BASE + 12) |
10091 | #define OPTION_MNO_SHARED (OPTION_MISC_BASE + 13) | |
10092 | {"mshared", no_argument, NULL, OPTION_MSHARED}, | |
10093 | {"mno-shared", no_argument, NULL, OPTION_MNO_SHARED}, | |
aed1a261 RS |
10094 | #define OPTION_MSYM32 (OPTION_MISC_BASE + 14) |
10095 | #define OPTION_MNO_SYM32 (OPTION_MISC_BASE + 15) | |
10096 | {"msym32", no_argument, NULL, OPTION_MSYM32}, | |
10097 | {"mno-sym32", no_argument, NULL, OPTION_MNO_SYM32}, | |
f9b4148d CD |
10098 | |
10099 | /* ELF-specific options. */ | |
156c2f8b | 10100 | #ifdef OBJ_ELF |
aed1a261 | 10101 | #define OPTION_ELF_BASE (OPTION_MISC_BASE + 16) |
156c2f8b | 10102 | #define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0) |
156c2f8b NC |
10103 | {"KPIC", no_argument, NULL, OPTION_CALL_SHARED}, |
10104 | {"call_shared", no_argument, NULL, OPTION_CALL_SHARED}, | |
ae948b86 | 10105 | #define OPTION_NON_SHARED (OPTION_ELF_BASE + 1) |
156c2f8b | 10106 | {"non_shared", no_argument, NULL, OPTION_NON_SHARED}, |
ae948b86 | 10107 | #define OPTION_XGOT (OPTION_ELF_BASE + 2) |
156c2f8b | 10108 | {"xgot", no_argument, NULL, OPTION_XGOT}, |
ae948b86 TS |
10109 | #define OPTION_MABI (OPTION_ELF_BASE + 3) |
10110 | {"mabi", required_argument, NULL, OPTION_MABI}, | |
10111 | #define OPTION_32 (OPTION_ELF_BASE + 4) | |
156c2f8b | 10112 | {"32", no_argument, NULL, OPTION_32}, |
ae948b86 | 10113 | #define OPTION_N32 (OPTION_ELF_BASE + 5) |
e013f690 | 10114 | {"n32", no_argument, NULL, OPTION_N32}, |
ae948b86 | 10115 | #define OPTION_64 (OPTION_ELF_BASE + 6) |
156c2f8b | 10116 | {"64", no_argument, NULL, OPTION_64}, |
ecb4347a DJ |
10117 | #define OPTION_MDEBUG (OPTION_ELF_BASE + 7) |
10118 | {"mdebug", no_argument, NULL, OPTION_MDEBUG}, | |
10119 | #define OPTION_NO_MDEBUG (OPTION_ELF_BASE + 8) | |
10120 | {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG}, | |
dcd410fe RO |
10121 | #define OPTION_PDR (OPTION_ELF_BASE + 9) |
10122 | {"mpdr", no_argument, NULL, OPTION_PDR}, | |
10123 | #define OPTION_NO_PDR (OPTION_ELF_BASE + 10) | |
10124 | {"mno-pdr", no_argument, NULL, OPTION_NO_PDR}, | |
ae948b86 | 10125 | #endif /* OBJ_ELF */ |
f9b4148d | 10126 | |
252b5132 RH |
10127 | {NULL, no_argument, NULL, 0} |
10128 | }; | |
156c2f8b | 10129 | size_t md_longopts_size = sizeof (md_longopts); |
252b5132 | 10130 | |
316f5878 RS |
10131 | /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to |
10132 | NEW_VALUE. Warn if another value was already specified. Note: | |
10133 | we have to defer parsing the -march and -mtune arguments in order | |
10134 | to handle 'from-abi' correctly, since the ABI might be specified | |
10135 | in a later argument. */ | |
10136 | ||
10137 | static void | |
17a2f251 | 10138 | mips_set_option_string (const char **string_ptr, const char *new_value) |
316f5878 RS |
10139 | { |
10140 | if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0) | |
10141 | as_warn (_("A different %s was already specified, is now %s"), | |
10142 | string_ptr == &mips_arch_string ? "-march" : "-mtune", | |
10143 | new_value); | |
10144 | ||
10145 | *string_ptr = new_value; | |
10146 | } | |
10147 | ||
252b5132 | 10148 | int |
17a2f251 | 10149 | md_parse_option (int c, char *arg) |
252b5132 RH |
10150 | { |
10151 | switch (c) | |
10152 | { | |
119d663a NC |
10153 | case OPTION_CONSTRUCT_FLOATS: |
10154 | mips_disable_float_construction = 0; | |
10155 | break; | |
bdaaa2e1 | 10156 | |
119d663a NC |
10157 | case OPTION_NO_CONSTRUCT_FLOATS: |
10158 | mips_disable_float_construction = 1; | |
10159 | break; | |
bdaaa2e1 | 10160 | |
252b5132 RH |
10161 | case OPTION_TRAP: |
10162 | mips_trap = 1; | |
10163 | break; | |
10164 | ||
10165 | case OPTION_BREAK: | |
10166 | mips_trap = 0; | |
10167 | break; | |
10168 | ||
10169 | case OPTION_EB: | |
10170 | target_big_endian = 1; | |
10171 | break; | |
10172 | ||
10173 | case OPTION_EL: | |
10174 | target_big_endian = 0; | |
10175 | break; | |
10176 | ||
10177 | case 'O': | |
10178 | if (arg && arg[1] == '0') | |
10179 | mips_optimize = 1; | |
10180 | else | |
10181 | mips_optimize = 2; | |
10182 | break; | |
10183 | ||
10184 | case 'g': | |
10185 | if (arg == NULL) | |
10186 | mips_debug = 2; | |
10187 | else | |
10188 | mips_debug = atoi (arg); | |
10189 | /* When the MIPS assembler sees -g or -g2, it does not do | |
10190 | optimizations which limit full symbolic debugging. We take | |
10191 | that to be equivalent to -O0. */ | |
10192 | if (mips_debug == 2) | |
10193 | mips_optimize = 1; | |
10194 | break; | |
10195 | ||
10196 | case OPTION_MIPS1: | |
316f5878 | 10197 | file_mips_isa = ISA_MIPS1; |
252b5132 RH |
10198 | break; |
10199 | ||
10200 | case OPTION_MIPS2: | |
316f5878 | 10201 | file_mips_isa = ISA_MIPS2; |
252b5132 RH |
10202 | break; |
10203 | ||
10204 | case OPTION_MIPS3: | |
316f5878 | 10205 | file_mips_isa = ISA_MIPS3; |
252b5132 RH |
10206 | break; |
10207 | ||
10208 | case OPTION_MIPS4: | |
316f5878 | 10209 | file_mips_isa = ISA_MIPS4; |
e7af610e NC |
10210 | break; |
10211 | ||
84ea6cf2 | 10212 | case OPTION_MIPS5: |
316f5878 | 10213 | file_mips_isa = ISA_MIPS5; |
84ea6cf2 NC |
10214 | break; |
10215 | ||
e7af610e | 10216 | case OPTION_MIPS32: |
316f5878 | 10217 | file_mips_isa = ISA_MIPS32; |
252b5132 RH |
10218 | break; |
10219 | ||
af7ee8bf CD |
10220 | case OPTION_MIPS32R2: |
10221 | file_mips_isa = ISA_MIPS32R2; | |
10222 | break; | |
10223 | ||
5f74bc13 CD |
10224 | case OPTION_MIPS64R2: |
10225 | file_mips_isa = ISA_MIPS64R2; | |
10226 | break; | |
10227 | ||
84ea6cf2 | 10228 | case OPTION_MIPS64: |
316f5878 | 10229 | file_mips_isa = ISA_MIPS64; |
84ea6cf2 NC |
10230 | break; |
10231 | ||
ec68c924 | 10232 | case OPTION_MTUNE: |
316f5878 RS |
10233 | mips_set_option_string (&mips_tune_string, arg); |
10234 | break; | |
ec68c924 | 10235 | |
316f5878 RS |
10236 | case OPTION_MARCH: |
10237 | mips_set_option_string (&mips_arch_string, arg); | |
252b5132 RH |
10238 | break; |
10239 | ||
10240 | case OPTION_M4650: | |
316f5878 RS |
10241 | mips_set_option_string (&mips_arch_string, "4650"); |
10242 | mips_set_option_string (&mips_tune_string, "4650"); | |
252b5132 RH |
10243 | break; |
10244 | ||
10245 | case OPTION_NO_M4650: | |
10246 | break; | |
10247 | ||
10248 | case OPTION_M4010: | |
316f5878 RS |
10249 | mips_set_option_string (&mips_arch_string, "4010"); |
10250 | mips_set_option_string (&mips_tune_string, "4010"); | |
252b5132 RH |
10251 | break; |
10252 | ||
10253 | case OPTION_NO_M4010: | |
10254 | break; | |
10255 | ||
10256 | case OPTION_M4100: | |
316f5878 RS |
10257 | mips_set_option_string (&mips_arch_string, "4100"); |
10258 | mips_set_option_string (&mips_tune_string, "4100"); | |
252b5132 RH |
10259 | break; |
10260 | ||
10261 | case OPTION_NO_M4100: | |
10262 | break; | |
10263 | ||
252b5132 | 10264 | case OPTION_M3900: |
316f5878 RS |
10265 | mips_set_option_string (&mips_arch_string, "3900"); |
10266 | mips_set_option_string (&mips_tune_string, "3900"); | |
252b5132 | 10267 | break; |
bdaaa2e1 | 10268 | |
252b5132 RH |
10269 | case OPTION_NO_M3900: |
10270 | break; | |
10271 | ||
deec1734 CD |
10272 | case OPTION_MDMX: |
10273 | mips_opts.ase_mdmx = 1; | |
10274 | break; | |
10275 | ||
10276 | case OPTION_NO_MDMX: | |
10277 | mips_opts.ase_mdmx = 0; | |
10278 | break; | |
10279 | ||
252b5132 RH |
10280 | case OPTION_MIPS16: |
10281 | mips_opts.mips16 = 1; | |
b34976b6 | 10282 | mips_no_prev_insn (FALSE); |
252b5132 RH |
10283 | break; |
10284 | ||
10285 | case OPTION_NO_MIPS16: | |
10286 | mips_opts.mips16 = 0; | |
b34976b6 | 10287 | mips_no_prev_insn (FALSE); |
252b5132 RH |
10288 | break; |
10289 | ||
1f25f5d3 CD |
10290 | case OPTION_MIPS3D: |
10291 | mips_opts.ase_mips3d = 1; | |
10292 | break; | |
10293 | ||
10294 | case OPTION_NO_MIPS3D: | |
10295 | mips_opts.ase_mips3d = 0; | |
10296 | break; | |
10297 | ||
d766e8ec RS |
10298 | case OPTION_FIX_VR4120: |
10299 | mips_fix_vr4120 = 1; | |
60b63b72 RS |
10300 | break; |
10301 | ||
d766e8ec RS |
10302 | case OPTION_NO_FIX_VR4120: |
10303 | mips_fix_vr4120 = 0; | |
60b63b72 RS |
10304 | break; |
10305 | ||
4a6a3df4 AO |
10306 | case OPTION_RELAX_BRANCH: |
10307 | mips_relax_branch = 1; | |
10308 | break; | |
10309 | ||
10310 | case OPTION_NO_RELAX_BRANCH: | |
10311 | mips_relax_branch = 0; | |
10312 | break; | |
10313 | ||
aa6975fb ILT |
10314 | case OPTION_MSHARED: |
10315 | mips_in_shared = TRUE; | |
10316 | break; | |
10317 | ||
10318 | case OPTION_MNO_SHARED: | |
10319 | mips_in_shared = FALSE; | |
10320 | break; | |
10321 | ||
aed1a261 RS |
10322 | case OPTION_MSYM32: |
10323 | mips_opts.sym32 = TRUE; | |
10324 | break; | |
10325 | ||
10326 | case OPTION_MNO_SYM32: | |
10327 | mips_opts.sym32 = FALSE; | |
10328 | break; | |
10329 | ||
0f074f60 | 10330 | #ifdef OBJ_ELF |
252b5132 RH |
10331 | /* When generating ELF code, we permit -KPIC and -call_shared to |
10332 | select SVR4_PIC, and -non_shared to select no PIC. This is | |
10333 | intended to be compatible with Irix 5. */ | |
10334 | case OPTION_CALL_SHARED: | |
10335 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
10336 | { | |
10337 | as_bad (_("-call_shared is supported only for ELF format")); | |
10338 | return 0; | |
10339 | } | |
10340 | mips_pic = SVR4_PIC; | |
143d77c5 | 10341 | mips_abicalls = TRUE; |
252b5132 RH |
10342 | if (g_switch_seen && g_switch_value != 0) |
10343 | { | |
10344 | as_bad (_("-G may not be used with SVR4 PIC code")); | |
10345 | return 0; | |
10346 | } | |
10347 | g_switch_value = 0; | |
10348 | break; | |
10349 | ||
10350 | case OPTION_NON_SHARED: | |
10351 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
10352 | { | |
10353 | as_bad (_("-non_shared is supported only for ELF format")); | |
10354 | return 0; | |
10355 | } | |
10356 | mips_pic = NO_PIC; | |
143d77c5 | 10357 | mips_abicalls = FALSE; |
252b5132 RH |
10358 | break; |
10359 | ||
10360 | /* The -xgot option tells the assembler to use 32 offsets when | |
10361 | accessing the got in SVR4_PIC mode. It is for Irix | |
10362 | compatibility. */ | |
10363 | case OPTION_XGOT: | |
10364 | mips_big_got = 1; | |
10365 | break; | |
0f074f60 | 10366 | #endif /* OBJ_ELF */ |
252b5132 RH |
10367 | |
10368 | case 'G': | |
6caf9ef4 TS |
10369 | g_switch_value = atoi (arg); |
10370 | g_switch_seen = 1; | |
10371 | if (mips_pic == SVR4_PIC && g_switch_value != 0) | |
252b5132 | 10372 | { |
3e722fb5 | 10373 | as_bad (_("-G may not be used with SVR4 PIC code")); |
252b5132 RH |
10374 | return 0; |
10375 | } | |
252b5132 RH |
10376 | break; |
10377 | ||
0f074f60 | 10378 | #ifdef OBJ_ELF |
34ba82a8 TS |
10379 | /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32 |
10380 | and -mabi=64. */ | |
252b5132 | 10381 | case OPTION_32: |
34ba82a8 TS |
10382 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
10383 | { | |
10384 | as_bad (_("-32 is supported for ELF format only")); | |
10385 | return 0; | |
10386 | } | |
316f5878 | 10387 | mips_abi = O32_ABI; |
252b5132 RH |
10388 | break; |
10389 | ||
e013f690 | 10390 | case OPTION_N32: |
34ba82a8 TS |
10391 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
10392 | { | |
10393 | as_bad (_("-n32 is supported for ELF format only")); | |
10394 | return 0; | |
10395 | } | |
316f5878 | 10396 | mips_abi = N32_ABI; |
e013f690 | 10397 | break; |
252b5132 | 10398 | |
e013f690 | 10399 | case OPTION_64: |
34ba82a8 TS |
10400 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
10401 | { | |
10402 | as_bad (_("-64 is supported for ELF format only")); | |
10403 | return 0; | |
10404 | } | |
316f5878 | 10405 | mips_abi = N64_ABI; |
e013f690 TS |
10406 | if (! support_64bit_objects()) |
10407 | as_fatal (_("No compiled in support for 64 bit object file format")); | |
252b5132 | 10408 | break; |
ae948b86 | 10409 | #endif /* OBJ_ELF */ |
252b5132 | 10410 | |
c97ef257 | 10411 | case OPTION_GP32: |
a325df1d | 10412 | file_mips_gp32 = 1; |
c97ef257 AH |
10413 | break; |
10414 | ||
10415 | case OPTION_GP64: | |
a325df1d | 10416 | file_mips_gp32 = 0; |
c97ef257 | 10417 | break; |
252b5132 | 10418 | |
ca4e0257 | 10419 | case OPTION_FP32: |
a325df1d | 10420 | file_mips_fp32 = 1; |
316f5878 RS |
10421 | break; |
10422 | ||
10423 | case OPTION_FP64: | |
10424 | file_mips_fp32 = 0; | |
ca4e0257 RS |
10425 | break; |
10426 | ||
ae948b86 | 10427 | #ifdef OBJ_ELF |
252b5132 | 10428 | case OPTION_MABI: |
34ba82a8 TS |
10429 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
10430 | { | |
10431 | as_bad (_("-mabi is supported for ELF format only")); | |
10432 | return 0; | |
10433 | } | |
e013f690 | 10434 | if (strcmp (arg, "32") == 0) |
316f5878 | 10435 | mips_abi = O32_ABI; |
e013f690 | 10436 | else if (strcmp (arg, "o64") == 0) |
316f5878 | 10437 | mips_abi = O64_ABI; |
e013f690 | 10438 | else if (strcmp (arg, "n32") == 0) |
316f5878 | 10439 | mips_abi = N32_ABI; |
e013f690 TS |
10440 | else if (strcmp (arg, "64") == 0) |
10441 | { | |
316f5878 | 10442 | mips_abi = N64_ABI; |
e013f690 TS |
10443 | if (! support_64bit_objects()) |
10444 | as_fatal (_("No compiled in support for 64 bit object file " | |
10445 | "format")); | |
10446 | } | |
10447 | else if (strcmp (arg, "eabi") == 0) | |
316f5878 | 10448 | mips_abi = EABI_ABI; |
e013f690 | 10449 | else |
da0e507f TS |
10450 | { |
10451 | as_fatal (_("invalid abi -mabi=%s"), arg); | |
10452 | return 0; | |
10453 | } | |
252b5132 | 10454 | break; |
e013f690 | 10455 | #endif /* OBJ_ELF */ |
252b5132 | 10456 | |
6b76fefe | 10457 | case OPTION_M7000_HILO_FIX: |
b34976b6 | 10458 | mips_7000_hilo_fix = TRUE; |
6b76fefe CM |
10459 | break; |
10460 | ||
9ee72ff1 | 10461 | case OPTION_MNO_7000_HILO_FIX: |
b34976b6 | 10462 | mips_7000_hilo_fix = FALSE; |
6b76fefe CM |
10463 | break; |
10464 | ||
ecb4347a DJ |
10465 | #ifdef OBJ_ELF |
10466 | case OPTION_MDEBUG: | |
b34976b6 | 10467 | mips_flag_mdebug = TRUE; |
ecb4347a DJ |
10468 | break; |
10469 | ||
10470 | case OPTION_NO_MDEBUG: | |
b34976b6 | 10471 | mips_flag_mdebug = FALSE; |
ecb4347a | 10472 | break; |
dcd410fe RO |
10473 | |
10474 | case OPTION_PDR: | |
10475 | mips_flag_pdr = TRUE; | |
10476 | break; | |
10477 | ||
10478 | case OPTION_NO_PDR: | |
10479 | mips_flag_pdr = FALSE; | |
10480 | break; | |
ecb4347a DJ |
10481 | #endif /* OBJ_ELF */ |
10482 | ||
252b5132 RH |
10483 | default: |
10484 | return 0; | |
10485 | } | |
10486 | ||
10487 | return 1; | |
10488 | } | |
316f5878 RS |
10489 | \f |
10490 | /* Set up globals to generate code for the ISA or processor | |
10491 | described by INFO. */ | |
252b5132 | 10492 | |
252b5132 | 10493 | static void |
17a2f251 | 10494 | mips_set_architecture (const struct mips_cpu_info *info) |
252b5132 | 10495 | { |
316f5878 | 10496 | if (info != 0) |
252b5132 | 10497 | { |
fef14a42 TS |
10498 | file_mips_arch = info->cpu; |
10499 | mips_opts.arch = info->cpu; | |
316f5878 | 10500 | mips_opts.isa = info->isa; |
252b5132 | 10501 | } |
252b5132 RH |
10502 | } |
10503 | ||
252b5132 | 10504 | |
316f5878 | 10505 | /* Likewise for tuning. */ |
252b5132 | 10506 | |
316f5878 | 10507 | static void |
17a2f251 | 10508 | mips_set_tune (const struct mips_cpu_info *info) |
316f5878 RS |
10509 | { |
10510 | if (info != 0) | |
fef14a42 | 10511 | mips_tune = info->cpu; |
316f5878 | 10512 | } |
80cc45a5 | 10513 | |
34ba82a8 | 10514 | |
252b5132 | 10515 | void |
17a2f251 | 10516 | mips_after_parse_args (void) |
e9670677 | 10517 | { |
fef14a42 TS |
10518 | const struct mips_cpu_info *arch_info = 0; |
10519 | const struct mips_cpu_info *tune_info = 0; | |
10520 | ||
e9670677 | 10521 | /* GP relative stuff not working for PE */ |
6caf9ef4 | 10522 | if (strncmp (TARGET_OS, "pe", 2) == 0) |
e9670677 | 10523 | { |
6caf9ef4 | 10524 | if (g_switch_seen && g_switch_value != 0) |
e9670677 MR |
10525 | as_bad (_("-G not supported in this configuration.")); |
10526 | g_switch_value = 0; | |
10527 | } | |
10528 | ||
cac012d6 AO |
10529 | if (mips_abi == NO_ABI) |
10530 | mips_abi = MIPS_DEFAULT_ABI; | |
10531 | ||
22923709 RS |
10532 | /* The following code determines the architecture and register size. |
10533 | Similar code was added to GCC 3.3 (see override_options() in | |
10534 | config/mips/mips.c). The GAS and GCC code should be kept in sync | |
10535 | as much as possible. */ | |
e9670677 | 10536 | |
316f5878 | 10537 | if (mips_arch_string != 0) |
fef14a42 | 10538 | arch_info = mips_parse_cpu ("-march", mips_arch_string); |
e9670677 | 10539 | |
316f5878 | 10540 | if (file_mips_isa != ISA_UNKNOWN) |
e9670677 | 10541 | { |
316f5878 | 10542 | /* Handle -mipsN. At this point, file_mips_isa contains the |
fef14a42 | 10543 | ISA level specified by -mipsN, while arch_info->isa contains |
316f5878 | 10544 | the -march selection (if any). */ |
fef14a42 | 10545 | if (arch_info != 0) |
e9670677 | 10546 | { |
316f5878 RS |
10547 | /* -march takes precedence over -mipsN, since it is more descriptive. |
10548 | There's no harm in specifying both as long as the ISA levels | |
10549 | are the same. */ | |
fef14a42 | 10550 | if (file_mips_isa != arch_info->isa) |
316f5878 RS |
10551 | as_bad (_("-%s conflicts with the other architecture options, which imply -%s"), |
10552 | mips_cpu_info_from_isa (file_mips_isa)->name, | |
fef14a42 | 10553 | mips_cpu_info_from_isa (arch_info->isa)->name); |
e9670677 | 10554 | } |
316f5878 | 10555 | else |
fef14a42 | 10556 | arch_info = mips_cpu_info_from_isa (file_mips_isa); |
e9670677 MR |
10557 | } |
10558 | ||
fef14a42 TS |
10559 | if (arch_info == 0) |
10560 | arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT); | |
e9670677 | 10561 | |
fef14a42 | 10562 | if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa)) |
316f5878 | 10563 | as_bad ("-march=%s is not compatible with the selected ABI", |
fef14a42 TS |
10564 | arch_info->name); |
10565 | ||
10566 | mips_set_architecture (arch_info); | |
10567 | ||
10568 | /* Optimize for file_mips_arch, unless -mtune selects a different processor. */ | |
10569 | if (mips_tune_string != 0) | |
10570 | tune_info = mips_parse_cpu ("-mtune", mips_tune_string); | |
e9670677 | 10571 | |
fef14a42 TS |
10572 | if (tune_info == 0) |
10573 | mips_set_tune (arch_info); | |
10574 | else | |
10575 | mips_set_tune (tune_info); | |
e9670677 | 10576 | |
316f5878 | 10577 | if (file_mips_gp32 >= 0) |
e9670677 | 10578 | { |
316f5878 RS |
10579 | /* The user specified the size of the integer registers. Make sure |
10580 | it agrees with the ABI and ISA. */ | |
10581 | if (file_mips_gp32 == 0 && !ISA_HAS_64BIT_REGS (mips_opts.isa)) | |
10582 | as_bad (_("-mgp64 used with a 32-bit processor")); | |
10583 | else if (file_mips_gp32 == 1 && ABI_NEEDS_64BIT_REGS (mips_abi)) | |
10584 | as_bad (_("-mgp32 used with a 64-bit ABI")); | |
10585 | else if (file_mips_gp32 == 0 && ABI_NEEDS_32BIT_REGS (mips_abi)) | |
10586 | as_bad (_("-mgp64 used with a 32-bit ABI")); | |
e9670677 MR |
10587 | } |
10588 | else | |
10589 | { | |
316f5878 RS |
10590 | /* Infer the integer register size from the ABI and processor. |
10591 | Restrict ourselves to 32-bit registers if that's all the | |
10592 | processor has, or if the ABI cannot handle 64-bit registers. */ | |
10593 | file_mips_gp32 = (ABI_NEEDS_32BIT_REGS (mips_abi) | |
10594 | || !ISA_HAS_64BIT_REGS (mips_opts.isa)); | |
e9670677 MR |
10595 | } |
10596 | ||
316f5878 RS |
10597 | /* ??? GAS treats single-float processors as though they had 64-bit |
10598 | float registers (although it complains when double-precision | |
10599 | instructions are used). As things stand, saying they have 32-bit | |
10600 | registers would lead to spurious "register must be even" messages. | |
10601 | So here we assume float registers are always the same size as | |
10602 | integer ones, unless the user says otherwise. */ | |
10603 | if (file_mips_fp32 < 0) | |
10604 | file_mips_fp32 = file_mips_gp32; | |
e9670677 | 10605 | |
316f5878 | 10606 | /* End of GCC-shared inference code. */ |
e9670677 | 10607 | |
17a2f251 TS |
10608 | /* This flag is set when we have a 64-bit capable CPU but use only |
10609 | 32-bit wide registers. Note that EABI does not use it. */ | |
10610 | if (ISA_HAS_64BIT_REGS (mips_opts.isa) | |
10611 | && ((mips_abi == NO_ABI && file_mips_gp32 == 1) | |
10612 | || mips_abi == O32_ABI)) | |
316f5878 | 10613 | mips_32bitmode = 1; |
e9670677 MR |
10614 | |
10615 | if (mips_opts.isa == ISA_MIPS1 && mips_trap) | |
10616 | as_bad (_("trap exception not supported at ISA 1")); | |
10617 | ||
e9670677 MR |
10618 | /* If the selected architecture includes support for ASEs, enable |
10619 | generation of code for them. */ | |
a4672219 | 10620 | if (mips_opts.mips16 == -1) |
fef14a42 | 10621 | mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_arch)) ? 1 : 0; |
ffdefa66 | 10622 | if (mips_opts.ase_mips3d == -1) |
fef14a42 | 10623 | mips_opts.ase_mips3d = (CPU_HAS_MIPS3D (file_mips_arch)) ? 1 : 0; |
ffdefa66 | 10624 | if (mips_opts.ase_mdmx == -1) |
fef14a42 | 10625 | mips_opts.ase_mdmx = (CPU_HAS_MDMX (file_mips_arch)) ? 1 : 0; |
e9670677 | 10626 | |
e9670677 | 10627 | file_mips_isa = mips_opts.isa; |
a4672219 | 10628 | file_ase_mips16 = mips_opts.mips16; |
e9670677 MR |
10629 | file_ase_mips3d = mips_opts.ase_mips3d; |
10630 | file_ase_mdmx = mips_opts.ase_mdmx; | |
10631 | mips_opts.gp32 = file_mips_gp32; | |
10632 | mips_opts.fp32 = file_mips_fp32; | |
10633 | ||
ecb4347a DJ |
10634 | if (mips_flag_mdebug < 0) |
10635 | { | |
10636 | #ifdef OBJ_MAYBE_ECOFF | |
10637 | if (OUTPUT_FLAVOR == bfd_target_ecoff_flavour) | |
10638 | mips_flag_mdebug = 1; | |
10639 | else | |
10640 | #endif /* OBJ_MAYBE_ECOFF */ | |
10641 | mips_flag_mdebug = 0; | |
10642 | } | |
e9670677 MR |
10643 | } |
10644 | \f | |
10645 | void | |
17a2f251 | 10646 | mips_init_after_args (void) |
252b5132 RH |
10647 | { |
10648 | /* initialize opcodes */ | |
10649 | bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes; | |
beae10d5 | 10650 | mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes; |
252b5132 RH |
10651 | } |
10652 | ||
10653 | long | |
17a2f251 | 10654 | md_pcrel_from (fixS *fixP) |
252b5132 | 10655 | { |
a7ebbfdf TS |
10656 | valueT addr = fixP->fx_where + fixP->fx_frag->fr_address; |
10657 | switch (fixP->fx_r_type) | |
10658 | { | |
10659 | case BFD_RELOC_16_PCREL_S2: | |
10660 | case BFD_RELOC_MIPS_JMP: | |
10661 | /* Return the address of the delay slot. */ | |
10662 | return addr + 4; | |
10663 | default: | |
10664 | return addr; | |
10665 | } | |
252b5132 RH |
10666 | } |
10667 | ||
252b5132 RH |
10668 | /* This is called before the symbol table is processed. In order to |
10669 | work with gcc when using mips-tfile, we must keep all local labels. | |
10670 | However, in other cases, we want to discard them. If we were | |
10671 | called with -g, but we didn't see any debugging information, it may | |
10672 | mean that gcc is smuggling debugging information through to | |
10673 | mips-tfile, in which case we must generate all local labels. */ | |
10674 | ||
10675 | void | |
17a2f251 | 10676 | mips_frob_file_before_adjust (void) |
252b5132 RH |
10677 | { |
10678 | #ifndef NO_ECOFF_DEBUGGING | |
10679 | if (ECOFF_DEBUGGING | |
10680 | && mips_debug != 0 | |
10681 | && ! ecoff_debugging_seen) | |
10682 | flag_keep_locals = 1; | |
10683 | #endif | |
10684 | } | |
10685 | ||
3b91255e RS |
10686 | /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede |
10687 | the corresponding LO16 reloc. This is called before md_apply_fix3 and | |
10688 | tc_gen_reloc. Unmatched relocs can only be generated by use of explicit | |
10689 | relocation operators. | |
10690 | ||
10691 | For our purposes, a %lo() expression matches a %got() or %hi() | |
10692 | expression if: | |
10693 | ||
10694 | (a) it refers to the same symbol; and | |
10695 | (b) the offset applied in the %lo() expression is no lower than | |
10696 | the offset applied in the %got() or %hi(). | |
10697 | ||
10698 | (b) allows us to cope with code like: | |
10699 | ||
10700 | lui $4,%hi(foo) | |
10701 | lh $4,%lo(foo+2)($4) | |
10702 | ||
10703 | ...which is legal on RELA targets, and has a well-defined behaviour | |
10704 | if the user knows that adding 2 to "foo" will not induce a carry to | |
10705 | the high 16 bits. | |
10706 | ||
10707 | When several %lo()s match a particular %got() or %hi(), we use the | |
10708 | following rules to distinguish them: | |
10709 | ||
10710 | (1) %lo()s with smaller offsets are a better match than %lo()s with | |
10711 | higher offsets. | |
10712 | ||
10713 | (2) %lo()s with no matching %got() or %hi() are better than those | |
10714 | that already have a matching %got() or %hi(). | |
10715 | ||
10716 | (3) later %lo()s are better than earlier %lo()s. | |
10717 | ||
10718 | These rules are applied in order. | |
10719 | ||
10720 | (1) means, among other things, that %lo()s with identical offsets are | |
10721 | chosen if they exist. | |
10722 | ||
10723 | (2) means that we won't associate several high-part relocations with | |
10724 | the same low-part relocation unless there's no alternative. Having | |
10725 | several high parts for the same low part is a GNU extension; this rule | |
10726 | allows careful users to avoid it. | |
10727 | ||
10728 | (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order, | |
10729 | with the last high-part relocation being at the front of the list. | |
10730 | It therefore makes sense to choose the last matching low-part | |
10731 | relocation, all other things being equal. It's also easier | |
10732 | to code that way. */ | |
252b5132 RH |
10733 | |
10734 | void | |
17a2f251 | 10735 | mips_frob_file (void) |
252b5132 RH |
10736 | { |
10737 | struct mips_hi_fixup *l; | |
10738 | ||
10739 | for (l = mips_hi_fixup_list; l != NULL; l = l->next) | |
10740 | { | |
10741 | segment_info_type *seginfo; | |
3b91255e RS |
10742 | bfd_boolean matched_lo_p; |
10743 | fixS **hi_pos, **lo_pos, **pos; | |
252b5132 | 10744 | |
5919d012 | 10745 | assert (reloc_needs_lo_p (l->fixp->fx_r_type)); |
252b5132 | 10746 | |
5919d012 RS |
10747 | /* If a GOT16 relocation turns out to be against a global symbol, |
10748 | there isn't supposed to be a matching LO. */ | |
10749 | if (l->fixp->fx_r_type == BFD_RELOC_MIPS_GOT16 | |
10750 | && !pic_need_relax (l->fixp->fx_addsy, l->seg)) | |
10751 | continue; | |
10752 | ||
10753 | /* Check quickly whether the next fixup happens to be a matching %lo. */ | |
10754 | if (fixup_has_matching_lo_p (l->fixp)) | |
252b5132 RH |
10755 | continue; |
10756 | ||
252b5132 | 10757 | seginfo = seg_info (l->seg); |
252b5132 | 10758 | |
3b91255e RS |
10759 | /* Set HI_POS to the position of this relocation in the chain. |
10760 | Set LO_POS to the position of the chosen low-part relocation. | |
10761 | MATCHED_LO_P is true on entry to the loop if *POS is a low-part | |
10762 | relocation that matches an immediately-preceding high-part | |
10763 | relocation. */ | |
10764 | hi_pos = NULL; | |
10765 | lo_pos = NULL; | |
10766 | matched_lo_p = FALSE; | |
10767 | for (pos = &seginfo->fix_root; *pos != NULL; pos = &(*pos)->fx_next) | |
10768 | { | |
10769 | if (*pos == l->fixp) | |
10770 | hi_pos = pos; | |
10771 | ||
10772 | if ((*pos)->fx_r_type == BFD_RELOC_LO16 | |
10773 | && (*pos)->fx_addsy == l->fixp->fx_addsy | |
10774 | && (*pos)->fx_offset >= l->fixp->fx_offset | |
10775 | && (lo_pos == NULL | |
10776 | || (*pos)->fx_offset < (*lo_pos)->fx_offset | |
10777 | || (!matched_lo_p | |
10778 | && (*pos)->fx_offset == (*lo_pos)->fx_offset))) | |
10779 | lo_pos = pos; | |
10780 | ||
10781 | matched_lo_p = (reloc_needs_lo_p ((*pos)->fx_r_type) | |
10782 | && fixup_has_matching_lo_p (*pos)); | |
10783 | } | |
10784 | ||
10785 | /* If we found a match, remove the high-part relocation from its | |
10786 | current position and insert it before the low-part relocation. | |
10787 | Make the offsets match so that fixup_has_matching_lo_p() | |
10788 | will return true. | |
10789 | ||
10790 | We don't warn about unmatched high-part relocations since some | |
10791 | versions of gcc have been known to emit dead "lui ...%hi(...)" | |
10792 | instructions. */ | |
10793 | if (lo_pos != NULL) | |
10794 | { | |
10795 | l->fixp->fx_offset = (*lo_pos)->fx_offset; | |
10796 | if (l->fixp->fx_next != *lo_pos) | |
252b5132 | 10797 | { |
3b91255e RS |
10798 | *hi_pos = l->fixp->fx_next; |
10799 | l->fixp->fx_next = *lo_pos; | |
10800 | *lo_pos = l->fixp; | |
252b5132 | 10801 | } |
252b5132 RH |
10802 | } |
10803 | } | |
10804 | } | |
10805 | ||
3e722fb5 | 10806 | /* We may have combined relocations without symbols in the N32/N64 ABI. |
f6688943 | 10807 | We have to prevent gas from dropping them. */ |
252b5132 | 10808 | |
252b5132 | 10809 | int |
17a2f251 | 10810 | mips_force_relocation (fixS *fixp) |
252b5132 | 10811 | { |
ae6063d4 | 10812 | if (generic_force_reloc (fixp)) |
252b5132 RH |
10813 | return 1; |
10814 | ||
f6688943 TS |
10815 | if (HAVE_NEWABI |
10816 | && S_GET_SEGMENT (fixp->fx_addsy) == bfd_abs_section_ptr | |
10817 | && (fixp->fx_r_type == BFD_RELOC_MIPS_SUB | |
10818 | || fixp->fx_r_type == BFD_RELOC_HI16_S | |
10819 | || fixp->fx_r_type == BFD_RELOC_LO16)) | |
10820 | return 1; | |
10821 | ||
3e722fb5 | 10822 | return 0; |
252b5132 RH |
10823 | } |
10824 | ||
45f8dfe8 AO |
10825 | /* This hook is called before a fix is simplified. We don't really |
10826 | decide whether to skip a fix here. Rather, we turn global symbols | |
10827 | used as branch targets into local symbols, such that they undergo | |
10828 | simplification. We can only do this if the symbol is defined and | |
10829 | it is in the same section as the branch. If this doesn't hold, we | |
10830 | emit a better error message than just saying the relocation is not | |
10831 | valid for the selected object format. | |
10832 | ||
10833 | FIXP is the fix-up we're going to try to simplify, SEG is the | |
10834 | segment in which the fix up occurs. The return value should be | |
10835 | non-zero to indicate the fix-up is valid for further | |
10836 | simplifications. */ | |
10837 | ||
10838 | int | |
17a2f251 | 10839 | mips_validate_fix (struct fix *fixP, asection *seg) |
45f8dfe8 AO |
10840 | { |
10841 | /* There's a lot of discussion on whether it should be possible to | |
10842 | use R_MIPS_PC16 to represent branch relocations. The outcome | |
10843 | seems to be that it can, but gas/bfd are very broken in creating | |
10844 | RELA relocations for this, so for now we only accept branches to | |
10845 | symbols in the same section. Anything else is of dubious value, | |
10846 | since there's no guarantee that at link time the symbol would be | |
10847 | in range. Even for branches to local symbols this is arguably | |
10848 | wrong, since it we assume the symbol is not going to be | |
10849 | overridden, which should be possible per ELF library semantics, | |
10850 | but then, there isn't a dynamic relocation that could be used to | |
10851 | this effect, and the target would likely be out of range as well. | |
10852 | ||
10853 | Unfortunately, it seems that there is too much code out there | |
10854 | that relies on branches to symbols that are global to be resolved | |
10855 | as if they were local, like the IRIX tools do, so we do it as | |
10856 | well, but with a warning so that people are reminded to fix their | |
10857 | code. If we ever get back to using R_MIPS_PC16 for branch | |
10858 | targets, this entire block should go away (and probably the | |
10859 | whole function). */ | |
10860 | ||
10861 | if (fixP->fx_r_type == BFD_RELOC_16_PCREL_S2 | |
3e722fb5 CD |
10862 | && ((OUTPUT_FLAVOR == bfd_target_ecoff_flavour |
10863 | || OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
45f8dfe8 AO |
10864 | || bfd_reloc_type_lookup (stdoutput, BFD_RELOC_16_PCREL_S2) == NULL) |
10865 | && fixP->fx_addsy) | |
10866 | { | |
10867 | if (! S_IS_DEFINED (fixP->fx_addsy)) | |
10868 | { | |
10869 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
10870 | _("Cannot branch to undefined symbol.")); | |
10871 | /* Avoid any further errors about this fixup. */ | |
10872 | fixP->fx_done = 1; | |
10873 | } | |
10874 | else if (S_GET_SEGMENT (fixP->fx_addsy) != seg) | |
10875 | { | |
10876 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
10877 | _("Cannot branch to symbol in another section.")); | |
10878 | fixP->fx_done = 1; | |
10879 | } | |
10880 | else if (S_IS_EXTERNAL (fixP->fx_addsy)) | |
10881 | { | |
10882 | symbolS *sym = fixP->fx_addsy; | |
10883 | ||
115695a8 CD |
10884 | if (mips_pic == SVR4_PIC) |
10885 | as_warn_where (fixP->fx_file, fixP->fx_line, | |
10886 | _("Pretending global symbol used as branch target is local.")); | |
45f8dfe8 AO |
10887 | |
10888 | fixP->fx_addsy = symbol_create (S_GET_NAME (sym), | |
10889 | S_GET_SEGMENT (sym), | |
10890 | S_GET_VALUE (sym), | |
10891 | symbol_get_frag (sym)); | |
10892 | copy_symbol_attributes (fixP->fx_addsy, sym); | |
10893 | S_CLEAR_EXTERNAL (fixP->fx_addsy); | |
10894 | assert (symbol_resolved_p (sym)); | |
10895 | symbol_mark_resolved (fixP->fx_addsy); | |
10896 | } | |
10897 | } | |
10898 | ||
10899 | return 1; | |
10900 | } | |
10901 | ||
252b5132 RH |
10902 | /* Apply a fixup to the object file. */ |
10903 | ||
94f592af | 10904 | void |
17a2f251 | 10905 | md_apply_fix3 (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) |
252b5132 | 10906 | { |
874e8986 | 10907 | bfd_byte *buf; |
98aa84af | 10908 | long insn; |
a7ebbfdf | 10909 | reloc_howto_type *howto; |
252b5132 | 10910 | |
a7ebbfdf TS |
10911 | /* We ignore generic BFD relocations we don't know about. */ |
10912 | howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type); | |
10913 | if (! howto) | |
10914 | return; | |
65551fa4 | 10915 | |
252b5132 RH |
10916 | assert (fixP->fx_size == 4 |
10917 | || fixP->fx_r_type == BFD_RELOC_16 | |
10918 | || fixP->fx_r_type == BFD_RELOC_64 | |
f6688943 TS |
10919 | || fixP->fx_r_type == BFD_RELOC_CTOR |
10920 | || fixP->fx_r_type == BFD_RELOC_MIPS_SUB | |
252b5132 | 10921 | || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
a7ebbfdf | 10922 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY); |
252b5132 | 10923 | |
a7ebbfdf | 10924 | buf = (bfd_byte *) (fixP->fx_frag->fr_literal + fixP->fx_where); |
252b5132 | 10925 | |
3e722fb5 | 10926 | assert (! fixP->fx_pcrel); |
b1dca8ee RS |
10927 | |
10928 | /* Don't treat parts of a composite relocation as done. There are two | |
10929 | reasons for this: | |
10930 | ||
10931 | (1) The second and third parts will be against 0 (RSS_UNDEF) but | |
10932 | should nevertheless be emitted if the first part is. | |
10933 | ||
10934 | (2) In normal usage, composite relocations are never assembly-time | |
10935 | constants. The easiest way of dealing with the pathological | |
10936 | exceptions is to generate a relocation against STN_UNDEF and | |
10937 | leave everything up to the linker. */ | |
10938 | if (fixP->fx_addsy == NULL && fixP->fx_tcbit == 0) | |
252b5132 RH |
10939 | fixP->fx_done = 1; |
10940 | ||
10941 | switch (fixP->fx_r_type) | |
10942 | { | |
3f98094e DJ |
10943 | case BFD_RELOC_MIPS_TLS_GD: |
10944 | case BFD_RELOC_MIPS_TLS_LDM: | |
10945 | case BFD_RELOC_MIPS_TLS_DTPREL_HI16: | |
10946 | case BFD_RELOC_MIPS_TLS_DTPREL_LO16: | |
10947 | case BFD_RELOC_MIPS_TLS_GOTTPREL: | |
10948 | case BFD_RELOC_MIPS_TLS_TPREL_HI16: | |
10949 | case BFD_RELOC_MIPS_TLS_TPREL_LO16: | |
10950 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
10951 | /* fall through */ | |
10952 | ||
252b5132 | 10953 | case BFD_RELOC_MIPS_JMP: |
e369bcce TS |
10954 | case BFD_RELOC_MIPS_SHIFT5: |
10955 | case BFD_RELOC_MIPS_SHIFT6: | |
10956 | case BFD_RELOC_MIPS_GOT_DISP: | |
10957 | case BFD_RELOC_MIPS_GOT_PAGE: | |
10958 | case BFD_RELOC_MIPS_GOT_OFST: | |
10959 | case BFD_RELOC_MIPS_SUB: | |
10960 | case BFD_RELOC_MIPS_INSERT_A: | |
10961 | case BFD_RELOC_MIPS_INSERT_B: | |
10962 | case BFD_RELOC_MIPS_DELETE: | |
10963 | case BFD_RELOC_MIPS_HIGHEST: | |
10964 | case BFD_RELOC_MIPS_HIGHER: | |
10965 | case BFD_RELOC_MIPS_SCN_DISP: | |
10966 | case BFD_RELOC_MIPS_REL16: | |
10967 | case BFD_RELOC_MIPS_RELGOT: | |
10968 | case BFD_RELOC_MIPS_JALR: | |
252b5132 RH |
10969 | case BFD_RELOC_HI16: |
10970 | case BFD_RELOC_HI16_S: | |
cdf6fd85 | 10971 | case BFD_RELOC_GPREL16: |
252b5132 RH |
10972 | case BFD_RELOC_MIPS_LITERAL: |
10973 | case BFD_RELOC_MIPS_CALL16: | |
10974 | case BFD_RELOC_MIPS_GOT16: | |
cdf6fd85 | 10975 | case BFD_RELOC_GPREL32: |
252b5132 RH |
10976 | case BFD_RELOC_MIPS_GOT_HI16: |
10977 | case BFD_RELOC_MIPS_GOT_LO16: | |
10978 | case BFD_RELOC_MIPS_CALL_HI16: | |
10979 | case BFD_RELOC_MIPS_CALL_LO16: | |
10980 | case BFD_RELOC_MIPS16_GPREL: | |
d6f16593 MR |
10981 | case BFD_RELOC_MIPS16_HI16: |
10982 | case BFD_RELOC_MIPS16_HI16_S: | |
3e722fb5 | 10983 | assert (! fixP->fx_pcrel); |
252b5132 RH |
10984 | /* Nothing needed to do. The value comes from the reloc entry */ |
10985 | break; | |
10986 | ||
10987 | case BFD_RELOC_MIPS16_JMP: | |
10988 | /* We currently always generate a reloc against a symbol, which | |
10989 | means that we don't want an addend even if the symbol is | |
10990 | defined. */ | |
a7ebbfdf | 10991 | *valP = 0; |
252b5132 RH |
10992 | break; |
10993 | ||
252b5132 RH |
10994 | case BFD_RELOC_64: |
10995 | /* This is handled like BFD_RELOC_32, but we output a sign | |
10996 | extended value if we are only 32 bits. */ | |
3e722fb5 | 10997 | if (fixP->fx_done) |
252b5132 RH |
10998 | { |
10999 | if (8 <= sizeof (valueT)) | |
2132e3a3 | 11000 | md_number_to_chars ((char *) buf, *valP, 8); |
252b5132 RH |
11001 | else |
11002 | { | |
a7ebbfdf | 11003 | valueT hiv; |
252b5132 | 11004 | |
a7ebbfdf | 11005 | if ((*valP & 0x80000000) != 0) |
252b5132 RH |
11006 | hiv = 0xffffffff; |
11007 | else | |
11008 | hiv = 0; | |
a7ebbfdf TS |
11009 | md_number_to_chars ((char *)(buf + target_big_endian ? 4 : 0), |
11010 | *valP, 4); | |
11011 | md_number_to_chars ((char *)(buf + target_big_endian ? 0 : 4), | |
11012 | hiv, 4); | |
252b5132 RH |
11013 | } |
11014 | } | |
11015 | break; | |
11016 | ||
056350c6 | 11017 | case BFD_RELOC_RVA: |
252b5132 RH |
11018 | case BFD_RELOC_32: |
11019 | /* If we are deleting this reloc entry, we must fill in the | |
11020 | value now. This can happen if we have a .word which is not | |
3e722fb5 CD |
11021 | resolved when it appears but is later defined. */ |
11022 | if (fixP->fx_done) | |
2132e3a3 | 11023 | md_number_to_chars ((char *) buf, *valP, 4); |
252b5132 RH |
11024 | break; |
11025 | ||
11026 | case BFD_RELOC_16: | |
11027 | /* If we are deleting this reloc entry, we must fill in the | |
11028 | value now. */ | |
252b5132 | 11029 | if (fixP->fx_done) |
2132e3a3 | 11030 | md_number_to_chars ((char *) buf, *valP, 2); |
252b5132 RH |
11031 | break; |
11032 | ||
11033 | case BFD_RELOC_LO16: | |
d6f16593 | 11034 | case BFD_RELOC_MIPS16_LO16: |
3e722fb5 CD |
11035 | /* FIXME: Now that embedded-PIC is gone, some of this code/comment |
11036 | may be safe to remove, but if so it's not obvious. */ | |
252b5132 RH |
11037 | /* When handling an embedded PIC switch statement, we can wind |
11038 | up deleting a LO16 reloc. See the 'o' case in mips_ip. */ | |
11039 | if (fixP->fx_done) | |
11040 | { | |
a7ebbfdf | 11041 | if (*valP + 0x8000 > 0xffff) |
252b5132 RH |
11042 | as_bad_where (fixP->fx_file, fixP->fx_line, |
11043 | _("relocation overflow")); | |
252b5132 RH |
11044 | if (target_big_endian) |
11045 | buf += 2; | |
2132e3a3 | 11046 | md_number_to_chars ((char *) buf, *valP, 2); |
252b5132 RH |
11047 | } |
11048 | break; | |
11049 | ||
11050 | case BFD_RELOC_16_PCREL_S2: | |
a7ebbfdf | 11051 | if ((*valP & 0x3) != 0) |
cb56d3d3 | 11052 | as_bad_where (fixP->fx_file, fixP->fx_line, |
a7ebbfdf | 11053 | _("Branch to odd address (%lx)"), (long) *valP); |
cb56d3d3 | 11054 | |
252b5132 RH |
11055 | /* |
11056 | * We need to save the bits in the instruction since fixup_segment() | |
11057 | * might be deleting the relocation entry (i.e., a branch within | |
11058 | * the current segment). | |
11059 | */ | |
a7ebbfdf | 11060 | if (! fixP->fx_done) |
bb2d6cd7 | 11061 | break; |
252b5132 RH |
11062 | |
11063 | /* update old instruction data */ | |
252b5132 RH |
11064 | if (target_big_endian) |
11065 | insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3]; | |
11066 | else | |
11067 | insn = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0]; | |
11068 | ||
a7ebbfdf TS |
11069 | if (*valP + 0x20000 <= 0x3ffff) |
11070 | { | |
11071 | insn |= (*valP >> 2) & 0xffff; | |
2132e3a3 | 11072 | md_number_to_chars ((char *) buf, insn, 4); |
a7ebbfdf TS |
11073 | } |
11074 | else if (mips_pic == NO_PIC | |
11075 | && fixP->fx_done | |
11076 | && fixP->fx_frag->fr_address >= text_section->vma | |
11077 | && (fixP->fx_frag->fr_address | |
587aac4e | 11078 | < text_section->vma + bfd_get_section_size (text_section)) |
a7ebbfdf TS |
11079 | && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */ |
11080 | || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */ | |
11081 | || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */ | |
252b5132 RH |
11082 | { |
11083 | /* The branch offset is too large. If this is an | |
11084 | unconditional branch, and we are not generating PIC code, | |
11085 | we can convert it to an absolute jump instruction. */ | |
a7ebbfdf TS |
11086 | if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */ |
11087 | insn = 0x0c000000; /* jal */ | |
252b5132 | 11088 | else |
a7ebbfdf TS |
11089 | insn = 0x08000000; /* j */ |
11090 | fixP->fx_r_type = BFD_RELOC_MIPS_JMP; | |
11091 | fixP->fx_done = 0; | |
11092 | fixP->fx_addsy = section_symbol (text_section); | |
11093 | *valP += md_pcrel_from (fixP); | |
2132e3a3 | 11094 | md_number_to_chars ((char *) buf, insn, 4); |
a7ebbfdf TS |
11095 | } |
11096 | else | |
11097 | { | |
11098 | /* If we got here, we have branch-relaxation disabled, | |
11099 | and there's nothing we can do to fix this instruction | |
11100 | without turning it into a longer sequence. */ | |
11101 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11102 | _("Branch out of range")); | |
252b5132 | 11103 | } |
252b5132 RH |
11104 | break; |
11105 | ||
11106 | case BFD_RELOC_VTABLE_INHERIT: | |
11107 | fixP->fx_done = 0; | |
11108 | if (fixP->fx_addsy | |
11109 | && !S_IS_DEFINED (fixP->fx_addsy) | |
11110 | && !S_IS_WEAK (fixP->fx_addsy)) | |
11111 | S_SET_WEAK (fixP->fx_addsy); | |
11112 | break; | |
11113 | ||
11114 | case BFD_RELOC_VTABLE_ENTRY: | |
11115 | fixP->fx_done = 0; | |
11116 | break; | |
11117 | ||
11118 | default: | |
11119 | internalError (); | |
11120 | } | |
a7ebbfdf TS |
11121 | |
11122 | /* Remember value for tc_gen_reloc. */ | |
11123 | fixP->fx_addnumber = *valP; | |
252b5132 RH |
11124 | } |
11125 | ||
252b5132 | 11126 | static symbolS * |
17a2f251 | 11127 | get_symbol (void) |
252b5132 RH |
11128 | { |
11129 | int c; | |
11130 | char *name; | |
11131 | symbolS *p; | |
11132 | ||
11133 | name = input_line_pointer; | |
11134 | c = get_symbol_end (); | |
11135 | p = (symbolS *) symbol_find_or_make (name); | |
11136 | *input_line_pointer = c; | |
11137 | return p; | |
11138 | } | |
11139 | ||
11140 | /* Align the current frag to a given power of two. The MIPS assembler | |
11141 | also automatically adjusts any preceding label. */ | |
11142 | ||
11143 | static void | |
17a2f251 | 11144 | mips_align (int to, int fill, symbolS *label) |
252b5132 | 11145 | { |
b34976b6 | 11146 | mips_emit_delays (FALSE); |
252b5132 RH |
11147 | frag_align (to, fill, 0); |
11148 | record_alignment (now_seg, to); | |
11149 | if (label != NULL) | |
11150 | { | |
11151 | assert (S_GET_SEGMENT (label) == now_seg); | |
49309057 | 11152 | symbol_set_frag (label, frag_now); |
252b5132 RH |
11153 | S_SET_VALUE (label, (valueT) frag_now_fix ()); |
11154 | } | |
11155 | } | |
11156 | ||
11157 | /* Align to a given power of two. .align 0 turns off the automatic | |
11158 | alignment used by the data creating pseudo-ops. */ | |
11159 | ||
11160 | static void | |
17a2f251 | 11161 | s_align (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
11162 | { |
11163 | register int temp; | |
11164 | register long temp_fill; | |
11165 | long max_alignment = 15; | |
11166 | ||
11167 | /* | |
11168 | ||
67c1ffbe | 11169 | o Note that the assembler pulls down any immediately preceding label |
252b5132 RH |
11170 | to the aligned address. |
11171 | o It's not documented but auto alignment is reinstated by | |
11172 | a .align pseudo instruction. | |
11173 | o Note also that after auto alignment is turned off the mips assembler | |
11174 | issues an error on attempt to assemble an improperly aligned data item. | |
11175 | We don't. | |
11176 | ||
11177 | */ | |
11178 | ||
11179 | temp = get_absolute_expression (); | |
11180 | if (temp > max_alignment) | |
11181 | as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment); | |
11182 | else if (temp < 0) | |
11183 | { | |
11184 | as_warn (_("Alignment negative: 0 assumed.")); | |
11185 | temp = 0; | |
11186 | } | |
11187 | if (*input_line_pointer == ',') | |
11188 | { | |
f9419b05 | 11189 | ++input_line_pointer; |
252b5132 RH |
11190 | temp_fill = get_absolute_expression (); |
11191 | } | |
11192 | else | |
11193 | temp_fill = 0; | |
11194 | if (temp) | |
11195 | { | |
11196 | auto_align = 1; | |
11197 | mips_align (temp, (int) temp_fill, | |
11198 | insn_labels != NULL ? insn_labels->label : NULL); | |
11199 | } | |
11200 | else | |
11201 | { | |
11202 | auto_align = 0; | |
11203 | } | |
11204 | ||
11205 | demand_empty_rest_of_line (); | |
11206 | } | |
11207 | ||
11208 | void | |
17a2f251 | 11209 | mips_flush_pending_output (void) |
252b5132 | 11210 | { |
b34976b6 | 11211 | mips_emit_delays (FALSE); |
252b5132 RH |
11212 | mips_clear_insn_labels (); |
11213 | } | |
11214 | ||
11215 | static void | |
17a2f251 | 11216 | s_change_sec (int sec) |
252b5132 RH |
11217 | { |
11218 | segT seg; | |
11219 | ||
252b5132 RH |
11220 | #ifdef OBJ_ELF |
11221 | /* The ELF backend needs to know that we are changing sections, so | |
11222 | that .previous works correctly. We could do something like check | |
b6ff326e | 11223 | for an obj_section_change_hook macro, but that might be confusing |
252b5132 RH |
11224 | as it would not be appropriate to use it in the section changing |
11225 | functions in read.c, since obj-elf.c intercepts those. FIXME: | |
11226 | This should be cleaner, somehow. */ | |
11227 | obj_elf_section_change_hook (); | |
11228 | #endif | |
11229 | ||
b34976b6 | 11230 | mips_emit_delays (FALSE); |
252b5132 RH |
11231 | switch (sec) |
11232 | { | |
11233 | case 't': | |
11234 | s_text (0); | |
11235 | break; | |
11236 | case 'd': | |
11237 | s_data (0); | |
11238 | break; | |
11239 | case 'b': | |
11240 | subseg_set (bss_section, (subsegT) get_absolute_expression ()); | |
11241 | demand_empty_rest_of_line (); | |
11242 | break; | |
11243 | ||
11244 | case 'r': | |
4d0d148d TS |
11245 | seg = subseg_new (RDATA_SECTION_NAME, |
11246 | (subsegT) get_absolute_expression ()); | |
11247 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
252b5132 | 11248 | { |
4d0d148d TS |
11249 | bfd_set_section_flags (stdoutput, seg, (SEC_ALLOC | SEC_LOAD |
11250 | | SEC_READONLY | SEC_RELOC | |
11251 | | SEC_DATA)); | |
11252 | if (strcmp (TARGET_OS, "elf") != 0) | |
11253 | record_alignment (seg, 4); | |
252b5132 | 11254 | } |
4d0d148d | 11255 | demand_empty_rest_of_line (); |
252b5132 RH |
11256 | break; |
11257 | ||
11258 | case 's': | |
4d0d148d TS |
11259 | seg = subseg_new (".sdata", (subsegT) get_absolute_expression ()); |
11260 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
252b5132 | 11261 | { |
4d0d148d TS |
11262 | bfd_set_section_flags (stdoutput, seg, |
11263 | SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA); | |
11264 | if (strcmp (TARGET_OS, "elf") != 0) | |
11265 | record_alignment (seg, 4); | |
252b5132 | 11266 | } |
4d0d148d TS |
11267 | demand_empty_rest_of_line (); |
11268 | break; | |
252b5132 RH |
11269 | } |
11270 | ||
11271 | auto_align = 1; | |
11272 | } | |
b34976b6 | 11273 | |
cca86cc8 | 11274 | void |
17a2f251 | 11275 | s_change_section (int ignore ATTRIBUTE_UNUSED) |
cca86cc8 | 11276 | { |
7ed4a06a | 11277 | #ifdef OBJ_ELF |
cca86cc8 SC |
11278 | char *section_name; |
11279 | char c; | |
684022ea | 11280 | char next_c = 0; |
cca86cc8 SC |
11281 | int section_type; |
11282 | int section_flag; | |
11283 | int section_entry_size; | |
11284 | int section_alignment; | |
b34976b6 | 11285 | |
7ed4a06a TS |
11286 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
11287 | return; | |
11288 | ||
cca86cc8 SC |
11289 | section_name = input_line_pointer; |
11290 | c = get_symbol_end (); | |
a816d1ed AO |
11291 | if (c) |
11292 | next_c = *(input_line_pointer + 1); | |
cca86cc8 | 11293 | |
4cf0dd0d TS |
11294 | /* Do we have .section Name<,"flags">? */ |
11295 | if (c != ',' || (c == ',' && next_c == '"')) | |
cca86cc8 | 11296 | { |
4cf0dd0d TS |
11297 | /* just after name is now '\0'. */ |
11298 | *input_line_pointer = c; | |
cca86cc8 SC |
11299 | input_line_pointer = section_name; |
11300 | obj_elf_section (ignore); | |
11301 | return; | |
11302 | } | |
11303 | input_line_pointer++; | |
11304 | ||
11305 | /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */ | |
11306 | if (c == ',') | |
11307 | section_type = get_absolute_expression (); | |
11308 | else | |
11309 | section_type = 0; | |
11310 | if (*input_line_pointer++ == ',') | |
11311 | section_flag = get_absolute_expression (); | |
11312 | else | |
11313 | section_flag = 0; | |
11314 | if (*input_line_pointer++ == ',') | |
11315 | section_entry_size = get_absolute_expression (); | |
11316 | else | |
11317 | section_entry_size = 0; | |
11318 | if (*input_line_pointer++ == ',') | |
11319 | section_alignment = get_absolute_expression (); | |
11320 | else | |
11321 | section_alignment = 0; | |
11322 | ||
a816d1ed AO |
11323 | section_name = xstrdup (section_name); |
11324 | ||
8ab8a5c8 RS |
11325 | /* When using the generic form of .section (as implemented by obj-elf.c), |
11326 | there's no way to set the section type to SHT_MIPS_DWARF. Users have | |
11327 | traditionally had to fall back on the more common @progbits instead. | |
11328 | ||
11329 | There's nothing really harmful in this, since bfd will correct | |
11330 | SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it | |
11331 | means that, for backwards compatibiltiy, the special_section entries | |
11332 | for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF. | |
11333 | ||
11334 | Even so, we shouldn't force users of the MIPS .section syntax to | |
11335 | incorrectly label the sections as SHT_PROGBITS. The best compromise | |
11336 | seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the | |
11337 | generic type-checking code. */ | |
11338 | if (section_type == SHT_MIPS_DWARF) | |
11339 | section_type = SHT_PROGBITS; | |
11340 | ||
cca86cc8 SC |
11341 | obj_elf_change_section (section_name, section_type, section_flag, |
11342 | section_entry_size, 0, 0, 0); | |
a816d1ed AO |
11343 | |
11344 | if (now_seg->name != section_name) | |
11345 | free (section_name); | |
7ed4a06a | 11346 | #endif /* OBJ_ELF */ |
cca86cc8 | 11347 | } |
252b5132 RH |
11348 | |
11349 | void | |
17a2f251 | 11350 | mips_enable_auto_align (void) |
252b5132 RH |
11351 | { |
11352 | auto_align = 1; | |
11353 | } | |
11354 | ||
11355 | static void | |
17a2f251 | 11356 | s_cons (int log_size) |
252b5132 RH |
11357 | { |
11358 | symbolS *label; | |
11359 | ||
11360 | label = insn_labels != NULL ? insn_labels->label : NULL; | |
b34976b6 | 11361 | mips_emit_delays (FALSE); |
252b5132 RH |
11362 | if (log_size > 0 && auto_align) |
11363 | mips_align (log_size, 0, label); | |
11364 | mips_clear_insn_labels (); | |
11365 | cons (1 << log_size); | |
11366 | } | |
11367 | ||
11368 | static void | |
17a2f251 | 11369 | s_float_cons (int type) |
252b5132 RH |
11370 | { |
11371 | symbolS *label; | |
11372 | ||
11373 | label = insn_labels != NULL ? insn_labels->label : NULL; | |
11374 | ||
b34976b6 | 11375 | mips_emit_delays (FALSE); |
252b5132 RH |
11376 | |
11377 | if (auto_align) | |
49309057 ILT |
11378 | { |
11379 | if (type == 'd') | |
11380 | mips_align (3, 0, label); | |
11381 | else | |
11382 | mips_align (2, 0, label); | |
11383 | } | |
252b5132 RH |
11384 | |
11385 | mips_clear_insn_labels (); | |
11386 | ||
11387 | float_cons (type); | |
11388 | } | |
11389 | ||
11390 | /* Handle .globl. We need to override it because on Irix 5 you are | |
11391 | permitted to say | |
11392 | .globl foo .text | |
11393 | where foo is an undefined symbol, to mean that foo should be | |
11394 | considered to be the address of a function. */ | |
11395 | ||
11396 | static void | |
17a2f251 | 11397 | s_mips_globl (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
11398 | { |
11399 | char *name; | |
11400 | int c; | |
11401 | symbolS *symbolP; | |
11402 | flagword flag; | |
11403 | ||
11404 | name = input_line_pointer; | |
11405 | c = get_symbol_end (); | |
11406 | symbolP = symbol_find_or_make (name); | |
11407 | *input_line_pointer = c; | |
11408 | SKIP_WHITESPACE (); | |
11409 | ||
11410 | /* On Irix 5, every global symbol that is not explicitly labelled as | |
11411 | being a function is apparently labelled as being an object. */ | |
11412 | flag = BSF_OBJECT; | |
11413 | ||
11414 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
11415 | { | |
11416 | char *secname; | |
11417 | asection *sec; | |
11418 | ||
11419 | secname = input_line_pointer; | |
11420 | c = get_symbol_end (); | |
11421 | sec = bfd_get_section_by_name (stdoutput, secname); | |
11422 | if (sec == NULL) | |
11423 | as_bad (_("%s: no such section"), secname); | |
11424 | *input_line_pointer = c; | |
11425 | ||
11426 | if (sec != NULL && (sec->flags & SEC_CODE) != 0) | |
11427 | flag = BSF_FUNCTION; | |
11428 | } | |
11429 | ||
49309057 | 11430 | symbol_get_bfdsym (symbolP)->flags |= flag; |
252b5132 RH |
11431 | |
11432 | S_SET_EXTERNAL (symbolP); | |
11433 | demand_empty_rest_of_line (); | |
11434 | } | |
11435 | ||
11436 | static void | |
17a2f251 | 11437 | s_option (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
11438 | { |
11439 | char *opt; | |
11440 | char c; | |
11441 | ||
11442 | opt = input_line_pointer; | |
11443 | c = get_symbol_end (); | |
11444 | ||
11445 | if (*opt == 'O') | |
11446 | { | |
11447 | /* FIXME: What does this mean? */ | |
11448 | } | |
11449 | else if (strncmp (opt, "pic", 3) == 0) | |
11450 | { | |
11451 | int i; | |
11452 | ||
11453 | i = atoi (opt + 3); | |
11454 | if (i == 0) | |
11455 | mips_pic = NO_PIC; | |
11456 | else if (i == 2) | |
143d77c5 | 11457 | { |
252b5132 | 11458 | mips_pic = SVR4_PIC; |
143d77c5 EC |
11459 | mips_abicalls = TRUE; |
11460 | } | |
252b5132 RH |
11461 | else |
11462 | as_bad (_(".option pic%d not supported"), i); | |
11463 | ||
4d0d148d | 11464 | if (mips_pic == SVR4_PIC) |
252b5132 RH |
11465 | { |
11466 | if (g_switch_seen && g_switch_value != 0) | |
11467 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
11468 | g_switch_value = 0; | |
11469 | bfd_set_gp_size (stdoutput, 0); | |
11470 | } | |
11471 | } | |
11472 | else | |
11473 | as_warn (_("Unrecognized option \"%s\""), opt); | |
11474 | ||
11475 | *input_line_pointer = c; | |
11476 | demand_empty_rest_of_line (); | |
11477 | } | |
11478 | ||
11479 | /* This structure is used to hold a stack of .set values. */ | |
11480 | ||
e972090a NC |
11481 | struct mips_option_stack |
11482 | { | |
252b5132 RH |
11483 | struct mips_option_stack *next; |
11484 | struct mips_set_options options; | |
11485 | }; | |
11486 | ||
11487 | static struct mips_option_stack *mips_opts_stack; | |
11488 | ||
11489 | /* Handle the .set pseudo-op. */ | |
11490 | ||
11491 | static void | |
17a2f251 | 11492 | s_mipsset (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
11493 | { |
11494 | char *name = input_line_pointer, ch; | |
11495 | ||
11496 | while (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
f9419b05 | 11497 | ++input_line_pointer; |
252b5132 RH |
11498 | ch = *input_line_pointer; |
11499 | *input_line_pointer = '\0'; | |
11500 | ||
11501 | if (strcmp (name, "reorder") == 0) | |
11502 | { | |
11503 | if (mips_opts.noreorder && prev_nop_frag != NULL) | |
11504 | { | |
11505 | /* If we still have pending nops, we can discard them. The | |
11506 | usual nop handling will insert any that are still | |
bdaaa2e1 | 11507 | needed. */ |
252b5132 RH |
11508 | prev_nop_frag->fr_fix -= (prev_nop_frag_holds |
11509 | * (mips_opts.mips16 ? 2 : 4)); | |
11510 | prev_nop_frag = NULL; | |
11511 | } | |
11512 | mips_opts.noreorder = 0; | |
11513 | } | |
11514 | else if (strcmp (name, "noreorder") == 0) | |
11515 | { | |
b34976b6 | 11516 | mips_emit_delays (TRUE); |
252b5132 RH |
11517 | mips_opts.noreorder = 1; |
11518 | mips_any_noreorder = 1; | |
11519 | } | |
11520 | else if (strcmp (name, "at") == 0) | |
11521 | { | |
11522 | mips_opts.noat = 0; | |
11523 | } | |
11524 | else if (strcmp (name, "noat") == 0) | |
11525 | { | |
11526 | mips_opts.noat = 1; | |
11527 | } | |
11528 | else if (strcmp (name, "macro") == 0) | |
11529 | { | |
11530 | mips_opts.warn_about_macros = 0; | |
11531 | } | |
11532 | else if (strcmp (name, "nomacro") == 0) | |
11533 | { | |
11534 | if (mips_opts.noreorder == 0) | |
11535 | as_bad (_("`noreorder' must be set before `nomacro'")); | |
11536 | mips_opts.warn_about_macros = 1; | |
11537 | } | |
11538 | else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0) | |
11539 | { | |
11540 | mips_opts.nomove = 0; | |
11541 | } | |
11542 | else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0) | |
11543 | { | |
11544 | mips_opts.nomove = 1; | |
11545 | } | |
11546 | else if (strcmp (name, "bopt") == 0) | |
11547 | { | |
11548 | mips_opts.nobopt = 0; | |
11549 | } | |
11550 | else if (strcmp (name, "nobopt") == 0) | |
11551 | { | |
11552 | mips_opts.nobopt = 1; | |
11553 | } | |
11554 | else if (strcmp (name, "mips16") == 0 | |
11555 | || strcmp (name, "MIPS-16") == 0) | |
11556 | mips_opts.mips16 = 1; | |
11557 | else if (strcmp (name, "nomips16") == 0 | |
11558 | || strcmp (name, "noMIPS-16") == 0) | |
11559 | mips_opts.mips16 = 0; | |
1f25f5d3 CD |
11560 | else if (strcmp (name, "mips3d") == 0) |
11561 | mips_opts.ase_mips3d = 1; | |
11562 | else if (strcmp (name, "nomips3d") == 0) | |
11563 | mips_opts.ase_mips3d = 0; | |
a4672219 TS |
11564 | else if (strcmp (name, "mdmx") == 0) |
11565 | mips_opts.ase_mdmx = 1; | |
11566 | else if (strcmp (name, "nomdmx") == 0) | |
11567 | mips_opts.ase_mdmx = 0; | |
1a2c1fad | 11568 | else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0) |
252b5132 | 11569 | { |
af7ee8bf | 11570 | int reset = 0; |
252b5132 | 11571 | |
1a2c1fad CD |
11572 | /* Permit the user to change the ISA and architecture on the fly. |
11573 | Needless to say, misuse can cause serious problems. */ | |
81a21e38 | 11574 | if (strcmp (name, "mips0") == 0 || strcmp (name, "arch=default") == 0) |
af7ee8bf CD |
11575 | { |
11576 | reset = 1; | |
11577 | mips_opts.isa = file_mips_isa; | |
1a2c1fad | 11578 | mips_opts.arch = file_mips_arch; |
1a2c1fad CD |
11579 | } |
11580 | else if (strncmp (name, "arch=", 5) == 0) | |
11581 | { | |
11582 | const struct mips_cpu_info *p; | |
11583 | ||
11584 | p = mips_parse_cpu("internal use", name + 5); | |
11585 | if (!p) | |
11586 | as_bad (_("unknown architecture %s"), name + 5); | |
11587 | else | |
11588 | { | |
11589 | mips_opts.arch = p->cpu; | |
11590 | mips_opts.isa = p->isa; | |
11591 | } | |
11592 | } | |
81a21e38 TS |
11593 | else if (strncmp (name, "mips", 4) == 0) |
11594 | { | |
11595 | const struct mips_cpu_info *p; | |
11596 | ||
11597 | p = mips_parse_cpu("internal use", name); | |
11598 | if (!p) | |
11599 | as_bad (_("unknown ISA level %s"), name + 4); | |
11600 | else | |
11601 | { | |
11602 | mips_opts.arch = p->cpu; | |
11603 | mips_opts.isa = p->isa; | |
11604 | } | |
11605 | } | |
af7ee8bf | 11606 | else |
81a21e38 | 11607 | as_bad (_("unknown ISA or architecture %s"), name); |
af7ee8bf CD |
11608 | |
11609 | switch (mips_opts.isa) | |
98d3f06f KH |
11610 | { |
11611 | case 0: | |
98d3f06f | 11612 | break; |
af7ee8bf CD |
11613 | case ISA_MIPS1: |
11614 | case ISA_MIPS2: | |
11615 | case ISA_MIPS32: | |
11616 | case ISA_MIPS32R2: | |
98d3f06f KH |
11617 | mips_opts.gp32 = 1; |
11618 | mips_opts.fp32 = 1; | |
11619 | break; | |
af7ee8bf CD |
11620 | case ISA_MIPS3: |
11621 | case ISA_MIPS4: | |
11622 | case ISA_MIPS5: | |
11623 | case ISA_MIPS64: | |
5f74bc13 | 11624 | case ISA_MIPS64R2: |
98d3f06f KH |
11625 | mips_opts.gp32 = 0; |
11626 | mips_opts.fp32 = 0; | |
11627 | break; | |
11628 | default: | |
11629 | as_bad (_("unknown ISA level %s"), name + 4); | |
11630 | break; | |
11631 | } | |
af7ee8bf | 11632 | if (reset) |
98d3f06f | 11633 | { |
af7ee8bf CD |
11634 | mips_opts.gp32 = file_mips_gp32; |
11635 | mips_opts.fp32 = file_mips_fp32; | |
98d3f06f | 11636 | } |
252b5132 RH |
11637 | } |
11638 | else if (strcmp (name, "autoextend") == 0) | |
11639 | mips_opts.noautoextend = 0; | |
11640 | else if (strcmp (name, "noautoextend") == 0) | |
11641 | mips_opts.noautoextend = 1; | |
11642 | else if (strcmp (name, "push") == 0) | |
11643 | { | |
11644 | struct mips_option_stack *s; | |
11645 | ||
11646 | s = (struct mips_option_stack *) xmalloc (sizeof *s); | |
11647 | s->next = mips_opts_stack; | |
11648 | s->options = mips_opts; | |
11649 | mips_opts_stack = s; | |
11650 | } | |
11651 | else if (strcmp (name, "pop") == 0) | |
11652 | { | |
11653 | struct mips_option_stack *s; | |
11654 | ||
11655 | s = mips_opts_stack; | |
11656 | if (s == NULL) | |
11657 | as_bad (_(".set pop with no .set push")); | |
11658 | else | |
11659 | { | |
11660 | /* If we're changing the reorder mode we need to handle | |
11661 | delay slots correctly. */ | |
11662 | if (s->options.noreorder && ! mips_opts.noreorder) | |
b34976b6 | 11663 | mips_emit_delays (TRUE); |
252b5132 RH |
11664 | else if (! s->options.noreorder && mips_opts.noreorder) |
11665 | { | |
11666 | if (prev_nop_frag != NULL) | |
11667 | { | |
11668 | prev_nop_frag->fr_fix -= (prev_nop_frag_holds | |
11669 | * (mips_opts.mips16 ? 2 : 4)); | |
11670 | prev_nop_frag = NULL; | |
11671 | } | |
11672 | } | |
11673 | ||
11674 | mips_opts = s->options; | |
11675 | mips_opts_stack = s->next; | |
11676 | free (s); | |
11677 | } | |
11678 | } | |
aed1a261 RS |
11679 | else if (strcmp (name, "sym32") == 0) |
11680 | mips_opts.sym32 = TRUE; | |
11681 | else if (strcmp (name, "nosym32") == 0) | |
11682 | mips_opts.sym32 = FALSE; | |
252b5132 RH |
11683 | else |
11684 | { | |
11685 | as_warn (_("Tried to set unrecognized symbol: %s\n"), name); | |
11686 | } | |
11687 | *input_line_pointer = ch; | |
11688 | demand_empty_rest_of_line (); | |
11689 | } | |
11690 | ||
11691 | /* Handle the .abicalls pseudo-op. I believe this is equivalent to | |
11692 | .option pic2. It means to generate SVR4 PIC calls. */ | |
11693 | ||
11694 | static void | |
17a2f251 | 11695 | s_abicalls (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
11696 | { |
11697 | mips_pic = SVR4_PIC; | |
143d77c5 | 11698 | mips_abicalls = TRUE; |
4d0d148d TS |
11699 | |
11700 | if (g_switch_seen && g_switch_value != 0) | |
11701 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
11702 | g_switch_value = 0; | |
11703 | ||
252b5132 RH |
11704 | bfd_set_gp_size (stdoutput, 0); |
11705 | demand_empty_rest_of_line (); | |
11706 | } | |
11707 | ||
11708 | /* Handle the .cpload pseudo-op. This is used when generating SVR4 | |
11709 | PIC code. It sets the $gp register for the function based on the | |
11710 | function address, which is in the register named in the argument. | |
11711 | This uses a relocation against _gp_disp, which is handled specially | |
11712 | by the linker. The result is: | |
11713 | lui $gp,%hi(_gp_disp) | |
11714 | addiu $gp,$gp,%lo(_gp_disp) | |
11715 | addu $gp,$gp,.cpload argument | |
aa6975fb ILT |
11716 | The .cpload argument is normally $25 == $t9. |
11717 | ||
11718 | The -mno-shared option changes this to: | |
bbe506e8 TS |
11719 | lui $gp,%hi(__gnu_local_gp) |
11720 | addiu $gp,$gp,%lo(__gnu_local_gp) | |
aa6975fb ILT |
11721 | and the argument is ignored. This saves an instruction, but the |
11722 | resulting code is not position independent; it uses an absolute | |
bbe506e8 TS |
11723 | address for __gnu_local_gp. Thus code assembled with -mno-shared |
11724 | can go into an ordinary executable, but not into a shared library. */ | |
252b5132 RH |
11725 | |
11726 | static void | |
17a2f251 | 11727 | s_cpload (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
11728 | { |
11729 | expressionS ex; | |
aa6975fb ILT |
11730 | int reg; |
11731 | int in_shared; | |
252b5132 | 11732 | |
6478892d TS |
11733 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
11734 | .cpload is ignored. */ | |
11735 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) | |
252b5132 RH |
11736 | { |
11737 | s_ignore (0); | |
11738 | return; | |
11739 | } | |
11740 | ||
d3ecfc59 | 11741 | /* .cpload should be in a .set noreorder section. */ |
252b5132 RH |
11742 | if (mips_opts.noreorder == 0) |
11743 | as_warn (_(".cpload not in noreorder section")); | |
11744 | ||
aa6975fb ILT |
11745 | reg = tc_get_register (0); |
11746 | ||
11747 | /* If we need to produce a 64-bit address, we are better off using | |
11748 | the default instruction sequence. */ | |
aed1a261 | 11749 | in_shared = mips_in_shared || HAVE_64BIT_SYMBOLS; |
aa6975fb | 11750 | |
252b5132 | 11751 | ex.X_op = O_symbol; |
bbe506e8 TS |
11752 | ex.X_add_symbol = symbol_find_or_make (in_shared ? "_gp_disp" : |
11753 | "__gnu_local_gp"); | |
252b5132 RH |
11754 | ex.X_op_symbol = NULL; |
11755 | ex.X_add_number = 0; | |
11756 | ||
11757 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ | |
49309057 | 11758 | symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; |
252b5132 | 11759 | |
584892a6 | 11760 | macro_start (); |
67c0d1eb RS |
11761 | macro_build_lui (&ex, mips_gp_register); |
11762 | macro_build (&ex, "addiu", "t,r,j", mips_gp_register, | |
17a2f251 | 11763 | mips_gp_register, BFD_RELOC_LO16); |
aa6975fb ILT |
11764 | if (in_shared) |
11765 | macro_build (NULL, "addu", "d,v,t", mips_gp_register, | |
11766 | mips_gp_register, reg); | |
584892a6 | 11767 | macro_end (); |
252b5132 RH |
11768 | |
11769 | demand_empty_rest_of_line (); | |
11770 | } | |
11771 | ||
6478892d TS |
11772 | /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is: |
11773 | .cpsetup $reg1, offset|$reg2, label | |
11774 | ||
11775 | If offset is given, this results in: | |
11776 | sd $gp, offset($sp) | |
956cd1d6 | 11777 | lui $gp, %hi(%neg(%gp_rel(label))) |
698b7d9d TS |
11778 | addiu $gp, $gp, %lo(%neg(%gp_rel(label))) |
11779 | daddu $gp, $gp, $reg1 | |
6478892d TS |
11780 | |
11781 | If $reg2 is given, this results in: | |
11782 | daddu $reg2, $gp, $0 | |
956cd1d6 | 11783 | lui $gp, %hi(%neg(%gp_rel(label))) |
698b7d9d TS |
11784 | addiu $gp, $gp, %lo(%neg(%gp_rel(label))) |
11785 | daddu $gp, $gp, $reg1 | |
aa6975fb ILT |
11786 | $reg1 is normally $25 == $t9. |
11787 | ||
11788 | The -mno-shared option replaces the last three instructions with | |
11789 | lui $gp,%hi(_gp) | |
11790 | addiu $gp,$gp,%lo(_gp) | |
11791 | */ | |
11792 | ||
6478892d | 11793 | static void |
17a2f251 | 11794 | s_cpsetup (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
11795 | { |
11796 | expressionS ex_off; | |
11797 | expressionS ex_sym; | |
11798 | int reg1; | |
6478892d | 11799 | |
8586fc66 | 11800 | /* If we are not generating SVR4 PIC code, .cpsetup is ignored. |
6478892d TS |
11801 | We also need NewABI support. */ |
11802 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
11803 | { | |
11804 | s_ignore (0); | |
11805 | return; | |
11806 | } | |
11807 | ||
11808 | reg1 = tc_get_register (0); | |
11809 | SKIP_WHITESPACE (); | |
11810 | if (*input_line_pointer != ',') | |
11811 | { | |
11812 | as_bad (_("missing argument separator ',' for .cpsetup")); | |
11813 | return; | |
11814 | } | |
11815 | else | |
80245285 | 11816 | ++input_line_pointer; |
6478892d TS |
11817 | SKIP_WHITESPACE (); |
11818 | if (*input_line_pointer == '$') | |
80245285 TS |
11819 | { |
11820 | mips_cpreturn_register = tc_get_register (0); | |
11821 | mips_cpreturn_offset = -1; | |
11822 | } | |
6478892d | 11823 | else |
80245285 TS |
11824 | { |
11825 | mips_cpreturn_offset = get_absolute_expression (); | |
11826 | mips_cpreturn_register = -1; | |
11827 | } | |
6478892d TS |
11828 | SKIP_WHITESPACE (); |
11829 | if (*input_line_pointer != ',') | |
11830 | { | |
11831 | as_bad (_("missing argument separator ',' for .cpsetup")); | |
11832 | return; | |
11833 | } | |
11834 | else | |
f9419b05 | 11835 | ++input_line_pointer; |
6478892d | 11836 | SKIP_WHITESPACE (); |
f21f8242 | 11837 | expression (&ex_sym); |
6478892d | 11838 | |
584892a6 | 11839 | macro_start (); |
6478892d TS |
11840 | if (mips_cpreturn_register == -1) |
11841 | { | |
11842 | ex_off.X_op = O_constant; | |
11843 | ex_off.X_add_symbol = NULL; | |
11844 | ex_off.X_op_symbol = NULL; | |
11845 | ex_off.X_add_number = mips_cpreturn_offset; | |
11846 | ||
67c0d1eb | 11847 | macro_build (&ex_off, "sd", "t,o(b)", mips_gp_register, |
17a2f251 | 11848 | BFD_RELOC_LO16, SP); |
6478892d TS |
11849 | } |
11850 | else | |
67c0d1eb | 11851 | macro_build (NULL, "daddu", "d,v,t", mips_cpreturn_register, |
17a2f251 | 11852 | mips_gp_register, 0); |
6478892d | 11853 | |
aed1a261 | 11854 | if (mips_in_shared || HAVE_64BIT_SYMBOLS) |
aa6975fb ILT |
11855 | { |
11856 | macro_build (&ex_sym, "lui", "t,u", mips_gp_register, | |
11857 | -1, BFD_RELOC_GPREL16, BFD_RELOC_MIPS_SUB, | |
11858 | BFD_RELOC_HI16_S); | |
11859 | ||
11860 | macro_build (&ex_sym, "addiu", "t,r,j", mips_gp_register, | |
11861 | mips_gp_register, -1, BFD_RELOC_GPREL16, | |
11862 | BFD_RELOC_MIPS_SUB, BFD_RELOC_LO16); | |
11863 | ||
11864 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register, | |
11865 | mips_gp_register, reg1); | |
11866 | } | |
11867 | else | |
11868 | { | |
11869 | expressionS ex; | |
11870 | ||
11871 | ex.X_op = O_symbol; | |
11872 | ex.X_add_symbol = symbol_find_or_make ("_gp"); | |
11873 | ex.X_op_symbol = NULL; | |
11874 | ex.X_add_number = 0; | |
6e1304d8 | 11875 | |
aa6975fb ILT |
11876 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ |
11877 | symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; | |
11878 | ||
11879 | macro_build_lui (&ex, mips_gp_register); | |
11880 | macro_build (&ex, "addiu", "t,r,j", mips_gp_register, | |
11881 | mips_gp_register, BFD_RELOC_LO16); | |
11882 | } | |
f21f8242 | 11883 | |
584892a6 | 11884 | macro_end (); |
6478892d TS |
11885 | |
11886 | demand_empty_rest_of_line (); | |
11887 | } | |
11888 | ||
11889 | static void | |
17a2f251 | 11890 | s_cplocal (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
11891 | { |
11892 | /* If we are not generating SVR4 PIC code, or if this is not NewABI code, | |
11893 | .cplocal is ignored. */ | |
11894 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
11895 | { | |
11896 | s_ignore (0); | |
11897 | return; | |
11898 | } | |
11899 | ||
11900 | mips_gp_register = tc_get_register (0); | |
85b51719 | 11901 | demand_empty_rest_of_line (); |
6478892d TS |
11902 | } |
11903 | ||
252b5132 RH |
11904 | /* Handle the .cprestore pseudo-op. This stores $gp into a given |
11905 | offset from $sp. The offset is remembered, and after making a PIC | |
11906 | call $gp is restored from that location. */ | |
11907 | ||
11908 | static void | |
17a2f251 | 11909 | s_cprestore (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
11910 | { |
11911 | expressionS ex; | |
252b5132 | 11912 | |
6478892d | 11913 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
c9914766 | 11914 | .cprestore is ignored. */ |
6478892d | 11915 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) |
252b5132 RH |
11916 | { |
11917 | s_ignore (0); | |
11918 | return; | |
11919 | } | |
11920 | ||
11921 | mips_cprestore_offset = get_absolute_expression (); | |
7a621144 | 11922 | mips_cprestore_valid = 1; |
252b5132 RH |
11923 | |
11924 | ex.X_op = O_constant; | |
11925 | ex.X_add_symbol = NULL; | |
11926 | ex.X_op_symbol = NULL; | |
11927 | ex.X_add_number = mips_cprestore_offset; | |
11928 | ||
584892a6 | 11929 | macro_start (); |
67c0d1eb RS |
11930 | macro_build_ldst_constoffset (&ex, ADDRESS_STORE_INSN, mips_gp_register, |
11931 | SP, HAVE_64BIT_ADDRESSES); | |
584892a6 | 11932 | macro_end (); |
252b5132 RH |
11933 | |
11934 | demand_empty_rest_of_line (); | |
11935 | } | |
11936 | ||
6478892d | 11937 | /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset |
67c1ffbe | 11938 | was given in the preceding .cpsetup, it results in: |
6478892d | 11939 | ld $gp, offset($sp) |
76b3015f | 11940 | |
6478892d | 11941 | If a register $reg2 was given there, it results in: |
609f23f4 | 11942 | daddu $gp, $reg2, $0 |
6478892d TS |
11943 | */ |
11944 | static void | |
17a2f251 | 11945 | s_cpreturn (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
11946 | { |
11947 | expressionS ex; | |
6478892d TS |
11948 | |
11949 | /* If we are not generating SVR4 PIC code, .cpreturn is ignored. | |
11950 | We also need NewABI support. */ | |
11951 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
11952 | { | |
11953 | s_ignore (0); | |
11954 | return; | |
11955 | } | |
11956 | ||
584892a6 | 11957 | macro_start (); |
6478892d TS |
11958 | if (mips_cpreturn_register == -1) |
11959 | { | |
11960 | ex.X_op = O_constant; | |
11961 | ex.X_add_symbol = NULL; | |
11962 | ex.X_op_symbol = NULL; | |
11963 | ex.X_add_number = mips_cpreturn_offset; | |
11964 | ||
67c0d1eb | 11965 | macro_build (&ex, "ld", "t,o(b)", mips_gp_register, BFD_RELOC_LO16, SP); |
6478892d TS |
11966 | } |
11967 | else | |
67c0d1eb | 11968 | macro_build (NULL, "daddu", "d,v,t", mips_gp_register, |
17a2f251 | 11969 | mips_cpreturn_register, 0); |
584892a6 | 11970 | macro_end (); |
6478892d TS |
11971 | |
11972 | demand_empty_rest_of_line (); | |
11973 | } | |
11974 | ||
11975 | /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC | |
11976 | code. It sets the offset to use in gp_rel relocations. */ | |
11977 | ||
11978 | static void | |
17a2f251 | 11979 | s_gpvalue (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
11980 | { |
11981 | /* If we are not generating SVR4 PIC code, .gpvalue is ignored. | |
11982 | We also need NewABI support. */ | |
11983 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
11984 | { | |
11985 | s_ignore (0); | |
11986 | return; | |
11987 | } | |
11988 | ||
def2e0dd | 11989 | mips_gprel_offset = get_absolute_expression (); |
6478892d TS |
11990 | |
11991 | demand_empty_rest_of_line (); | |
11992 | } | |
11993 | ||
252b5132 RH |
11994 | /* Handle the .gpword pseudo-op. This is used when generating PIC |
11995 | code. It generates a 32 bit GP relative reloc. */ | |
11996 | ||
11997 | static void | |
17a2f251 | 11998 | s_gpword (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
11999 | { |
12000 | symbolS *label; | |
12001 | expressionS ex; | |
12002 | char *p; | |
12003 | ||
12004 | /* When not generating PIC code, this is treated as .word. */ | |
12005 | if (mips_pic != SVR4_PIC) | |
12006 | { | |
12007 | s_cons (2); | |
12008 | return; | |
12009 | } | |
12010 | ||
12011 | label = insn_labels != NULL ? insn_labels->label : NULL; | |
b34976b6 | 12012 | mips_emit_delays (TRUE); |
252b5132 RH |
12013 | if (auto_align) |
12014 | mips_align (2, 0, label); | |
12015 | mips_clear_insn_labels (); | |
12016 | ||
12017 | expression (&ex); | |
12018 | ||
12019 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
12020 | { | |
12021 | as_bad (_("Unsupported use of .gpword")); | |
12022 | ignore_rest_of_line (); | |
12023 | } | |
12024 | ||
12025 | p = frag_more (4); | |
17a2f251 | 12026 | md_number_to_chars (p, 0, 4); |
b34976b6 | 12027 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, |
cdf6fd85 | 12028 | BFD_RELOC_GPREL32); |
252b5132 RH |
12029 | |
12030 | demand_empty_rest_of_line (); | |
12031 | } | |
12032 | ||
10181a0d | 12033 | static void |
17a2f251 | 12034 | s_gpdword (int ignore ATTRIBUTE_UNUSED) |
10181a0d AO |
12035 | { |
12036 | symbolS *label; | |
12037 | expressionS ex; | |
12038 | char *p; | |
12039 | ||
12040 | /* When not generating PIC code, this is treated as .dword. */ | |
12041 | if (mips_pic != SVR4_PIC) | |
12042 | { | |
12043 | s_cons (3); | |
12044 | return; | |
12045 | } | |
12046 | ||
12047 | label = insn_labels != NULL ? insn_labels->label : NULL; | |
b34976b6 | 12048 | mips_emit_delays (TRUE); |
10181a0d AO |
12049 | if (auto_align) |
12050 | mips_align (3, 0, label); | |
12051 | mips_clear_insn_labels (); | |
12052 | ||
12053 | expression (&ex); | |
12054 | ||
12055 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
12056 | { | |
12057 | as_bad (_("Unsupported use of .gpdword")); | |
12058 | ignore_rest_of_line (); | |
12059 | } | |
12060 | ||
12061 | p = frag_more (8); | |
17a2f251 | 12062 | md_number_to_chars (p, 0, 8); |
a105a300 | 12063 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, |
6e1304d8 | 12064 | BFD_RELOC_GPREL32)->fx_tcbit = 1; |
10181a0d AO |
12065 | |
12066 | /* GPREL32 composed with 64 gives a 64-bit GP offset. */ | |
6e1304d8 RS |
12067 | fix_new (frag_now, p - frag_now->fr_literal, 8, NULL, 0, |
12068 | FALSE, BFD_RELOC_64)->fx_tcbit = 1; | |
10181a0d AO |
12069 | |
12070 | demand_empty_rest_of_line (); | |
12071 | } | |
12072 | ||
252b5132 RH |
12073 | /* Handle the .cpadd pseudo-op. This is used when dealing with switch |
12074 | tables in SVR4 PIC code. */ | |
12075 | ||
12076 | static void | |
17a2f251 | 12077 | s_cpadd (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 12078 | { |
252b5132 RH |
12079 | int reg; |
12080 | ||
10181a0d AO |
12081 | /* This is ignored when not generating SVR4 PIC code. */ |
12082 | if (mips_pic != SVR4_PIC) | |
252b5132 RH |
12083 | { |
12084 | s_ignore (0); | |
12085 | return; | |
12086 | } | |
12087 | ||
12088 | /* Add $gp to the register named as an argument. */ | |
584892a6 | 12089 | macro_start (); |
252b5132 | 12090 | reg = tc_get_register (0); |
67c0d1eb | 12091 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register); |
584892a6 | 12092 | macro_end (); |
252b5132 | 12093 | |
bdaaa2e1 | 12094 | demand_empty_rest_of_line (); |
252b5132 RH |
12095 | } |
12096 | ||
12097 | /* Handle the .insn pseudo-op. This marks instruction labels in | |
12098 | mips16 mode. This permits the linker to handle them specially, | |
12099 | such as generating jalx instructions when needed. We also make | |
12100 | them odd for the duration of the assembly, in order to generate the | |
12101 | right sort of code. We will make them even in the adjust_symtab | |
12102 | routine, while leaving them marked. This is convenient for the | |
12103 | debugger and the disassembler. The linker knows to make them odd | |
12104 | again. */ | |
12105 | ||
12106 | static void | |
17a2f251 | 12107 | s_insn (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 12108 | { |
f9419b05 | 12109 | mips16_mark_labels (); |
252b5132 RH |
12110 | |
12111 | demand_empty_rest_of_line (); | |
12112 | } | |
12113 | ||
12114 | /* Handle a .stabn directive. We need these in order to mark a label | |
12115 | as being a mips16 text label correctly. Sometimes the compiler | |
12116 | will emit a label, followed by a .stabn, and then switch sections. | |
12117 | If the label and .stabn are in mips16 mode, then the label is | |
12118 | really a mips16 text label. */ | |
12119 | ||
12120 | static void | |
17a2f251 | 12121 | s_mips_stab (int type) |
252b5132 | 12122 | { |
f9419b05 | 12123 | if (type == 'n') |
252b5132 RH |
12124 | mips16_mark_labels (); |
12125 | ||
12126 | s_stab (type); | |
12127 | } | |
12128 | ||
12129 | /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. | |
12130 | */ | |
12131 | ||
12132 | static void | |
17a2f251 | 12133 | s_mips_weakext (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
12134 | { |
12135 | char *name; | |
12136 | int c; | |
12137 | symbolS *symbolP; | |
12138 | expressionS exp; | |
12139 | ||
12140 | name = input_line_pointer; | |
12141 | c = get_symbol_end (); | |
12142 | symbolP = symbol_find_or_make (name); | |
12143 | S_SET_WEAK (symbolP); | |
12144 | *input_line_pointer = c; | |
12145 | ||
12146 | SKIP_WHITESPACE (); | |
12147 | ||
12148 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
12149 | { | |
12150 | if (S_IS_DEFINED (symbolP)) | |
12151 | { | |
956cd1d6 | 12152 | as_bad ("ignoring attempt to redefine symbol %s", |
252b5132 RH |
12153 | S_GET_NAME (symbolP)); |
12154 | ignore_rest_of_line (); | |
12155 | return; | |
12156 | } | |
bdaaa2e1 | 12157 | |
252b5132 RH |
12158 | if (*input_line_pointer == ',') |
12159 | { | |
12160 | ++input_line_pointer; | |
12161 | SKIP_WHITESPACE (); | |
12162 | } | |
bdaaa2e1 | 12163 | |
252b5132 RH |
12164 | expression (&exp); |
12165 | if (exp.X_op != O_symbol) | |
12166 | { | |
12167 | as_bad ("bad .weakext directive"); | |
98d3f06f | 12168 | ignore_rest_of_line (); |
252b5132 RH |
12169 | return; |
12170 | } | |
49309057 | 12171 | symbol_set_value_expression (symbolP, &exp); |
252b5132 RH |
12172 | } |
12173 | ||
12174 | demand_empty_rest_of_line (); | |
12175 | } | |
12176 | ||
12177 | /* Parse a register string into a number. Called from the ECOFF code | |
12178 | to parse .frame. The argument is non-zero if this is the frame | |
12179 | register, so that we can record it in mips_frame_reg. */ | |
12180 | ||
12181 | int | |
17a2f251 | 12182 | tc_get_register (int frame) |
252b5132 RH |
12183 | { |
12184 | int reg; | |
12185 | ||
12186 | SKIP_WHITESPACE (); | |
12187 | if (*input_line_pointer++ != '$') | |
12188 | { | |
12189 | as_warn (_("expected `$'")); | |
85b51719 | 12190 | reg = ZERO; |
252b5132 | 12191 | } |
3882b010 | 12192 | else if (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
12193 | { |
12194 | reg = get_absolute_expression (); | |
12195 | if (reg < 0 || reg >= 32) | |
12196 | { | |
12197 | as_warn (_("Bad register number")); | |
85b51719 | 12198 | reg = ZERO; |
252b5132 RH |
12199 | } |
12200 | } | |
12201 | else | |
12202 | { | |
76db943d | 12203 | if (strncmp (input_line_pointer, "ra", 2) == 0) |
85b51719 TS |
12204 | { |
12205 | reg = RA; | |
12206 | input_line_pointer += 2; | |
12207 | } | |
76db943d | 12208 | else if (strncmp (input_line_pointer, "fp", 2) == 0) |
85b51719 TS |
12209 | { |
12210 | reg = FP; | |
12211 | input_line_pointer += 2; | |
12212 | } | |
252b5132 | 12213 | else if (strncmp (input_line_pointer, "sp", 2) == 0) |
85b51719 TS |
12214 | { |
12215 | reg = SP; | |
12216 | input_line_pointer += 2; | |
12217 | } | |
252b5132 | 12218 | else if (strncmp (input_line_pointer, "gp", 2) == 0) |
85b51719 TS |
12219 | { |
12220 | reg = GP; | |
12221 | input_line_pointer += 2; | |
12222 | } | |
252b5132 | 12223 | else if (strncmp (input_line_pointer, "at", 2) == 0) |
85b51719 TS |
12224 | { |
12225 | reg = AT; | |
12226 | input_line_pointer += 2; | |
12227 | } | |
12228 | else if (strncmp (input_line_pointer, "kt0", 3) == 0) | |
12229 | { | |
12230 | reg = KT0; | |
12231 | input_line_pointer += 3; | |
12232 | } | |
12233 | else if (strncmp (input_line_pointer, "kt1", 3) == 0) | |
12234 | { | |
12235 | reg = KT1; | |
12236 | input_line_pointer += 3; | |
12237 | } | |
12238 | else if (strncmp (input_line_pointer, "zero", 4) == 0) | |
12239 | { | |
12240 | reg = ZERO; | |
12241 | input_line_pointer += 4; | |
12242 | } | |
252b5132 RH |
12243 | else |
12244 | { | |
12245 | as_warn (_("Unrecognized register name")); | |
85b51719 TS |
12246 | reg = ZERO; |
12247 | while (ISALNUM(*input_line_pointer)) | |
12248 | input_line_pointer++; | |
252b5132 | 12249 | } |
252b5132 RH |
12250 | } |
12251 | if (frame) | |
7a621144 DJ |
12252 | { |
12253 | mips_frame_reg = reg != 0 ? reg : SP; | |
12254 | mips_frame_reg_valid = 1; | |
12255 | mips_cprestore_valid = 0; | |
12256 | } | |
252b5132 RH |
12257 | return reg; |
12258 | } | |
12259 | ||
12260 | valueT | |
17a2f251 | 12261 | md_section_align (asection *seg, valueT addr) |
252b5132 RH |
12262 | { |
12263 | int align = bfd_get_section_alignment (stdoutput, seg); | |
12264 | ||
12265 | #ifdef OBJ_ELF | |
12266 | /* We don't need to align ELF sections to the full alignment. | |
12267 | However, Irix 5 may prefer that we align them at least to a 16 | |
12268 | byte boundary. We don't bother to align the sections if we are | |
12269 | targeted for an embedded system. */ | |
12270 | if (strcmp (TARGET_OS, "elf") == 0) | |
12271 | return addr; | |
12272 | if (align > 4) | |
12273 | align = 4; | |
12274 | #endif | |
12275 | ||
12276 | return ((addr + (1 << align) - 1) & (-1 << align)); | |
12277 | } | |
12278 | ||
12279 | /* Utility routine, called from above as well. If called while the | |
12280 | input file is still being read, it's only an approximation. (For | |
12281 | example, a symbol may later become defined which appeared to be | |
12282 | undefined earlier.) */ | |
12283 | ||
12284 | static int | |
17a2f251 | 12285 | nopic_need_relax (symbolS *sym, int before_relaxing) |
252b5132 RH |
12286 | { |
12287 | if (sym == 0) | |
12288 | return 0; | |
12289 | ||
4d0d148d | 12290 | if (g_switch_value > 0) |
252b5132 RH |
12291 | { |
12292 | const char *symname; | |
12293 | int change; | |
12294 | ||
c9914766 | 12295 | /* Find out whether this symbol can be referenced off the $gp |
252b5132 RH |
12296 | register. It can be if it is smaller than the -G size or if |
12297 | it is in the .sdata or .sbss section. Certain symbols can | |
c9914766 | 12298 | not be referenced off the $gp, although it appears as though |
252b5132 RH |
12299 | they can. */ |
12300 | symname = S_GET_NAME (sym); | |
12301 | if (symname != (const char *) NULL | |
12302 | && (strcmp (symname, "eprol") == 0 | |
12303 | || strcmp (symname, "etext") == 0 | |
12304 | || strcmp (symname, "_gp") == 0 | |
12305 | || strcmp (symname, "edata") == 0 | |
12306 | || strcmp (symname, "_fbss") == 0 | |
12307 | || strcmp (symname, "_fdata") == 0 | |
12308 | || strcmp (symname, "_ftext") == 0 | |
12309 | || strcmp (symname, "end") == 0 | |
12310 | || strcmp (symname, "_gp_disp") == 0)) | |
12311 | change = 1; | |
12312 | else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym)) | |
12313 | && (0 | |
12314 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 ILT |
12315 | || (symbol_get_obj (sym)->ecoff_extern_size != 0 |
12316 | && (symbol_get_obj (sym)->ecoff_extern_size | |
12317 | <= g_switch_value)) | |
252b5132 RH |
12318 | #endif |
12319 | /* We must defer this decision until after the whole | |
12320 | file has been read, since there might be a .extern | |
12321 | after the first use of this symbol. */ | |
12322 | || (before_relaxing | |
12323 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 | 12324 | && symbol_get_obj (sym)->ecoff_extern_size == 0 |
252b5132 RH |
12325 | #endif |
12326 | && S_GET_VALUE (sym) == 0) | |
12327 | || (S_GET_VALUE (sym) != 0 | |
12328 | && S_GET_VALUE (sym) <= g_switch_value))) | |
12329 | change = 0; | |
12330 | else | |
12331 | { | |
12332 | const char *segname; | |
12333 | ||
12334 | segname = segment_name (S_GET_SEGMENT (sym)); | |
12335 | assert (strcmp (segname, ".lit8") != 0 | |
12336 | && strcmp (segname, ".lit4") != 0); | |
12337 | change = (strcmp (segname, ".sdata") != 0 | |
fba2b7f9 GK |
12338 | && strcmp (segname, ".sbss") != 0 |
12339 | && strncmp (segname, ".sdata.", 7) != 0 | |
12340 | && strncmp (segname, ".gnu.linkonce.s.", 16) != 0); | |
252b5132 RH |
12341 | } |
12342 | return change; | |
12343 | } | |
12344 | else | |
c9914766 | 12345 | /* We are not optimizing for the $gp register. */ |
252b5132 RH |
12346 | return 1; |
12347 | } | |
12348 | ||
5919d012 RS |
12349 | |
12350 | /* Return true if the given symbol should be considered local for SVR4 PIC. */ | |
12351 | ||
12352 | static bfd_boolean | |
17a2f251 | 12353 | pic_need_relax (symbolS *sym, asection *segtype) |
5919d012 RS |
12354 | { |
12355 | asection *symsec; | |
12356 | bfd_boolean linkonce; | |
12357 | ||
12358 | /* Handle the case of a symbol equated to another symbol. */ | |
12359 | while (symbol_equated_reloc_p (sym)) | |
12360 | { | |
12361 | symbolS *n; | |
12362 | ||
12363 | /* It's possible to get a loop here in a badly written | |
12364 | program. */ | |
12365 | n = symbol_get_value_expression (sym)->X_add_symbol; | |
12366 | if (n == sym) | |
12367 | break; | |
12368 | sym = n; | |
12369 | } | |
12370 | ||
12371 | symsec = S_GET_SEGMENT (sym); | |
12372 | ||
12373 | /* duplicate the test for LINK_ONCE sections as in adjust_reloc_syms */ | |
12374 | linkonce = FALSE; | |
12375 | if (symsec != segtype && ! S_IS_LOCAL (sym)) | |
12376 | { | |
12377 | if ((bfd_get_section_flags (stdoutput, symsec) & SEC_LINK_ONCE) | |
12378 | != 0) | |
12379 | linkonce = TRUE; | |
12380 | ||
12381 | /* The GNU toolchain uses an extension for ELF: a section | |
12382 | beginning with the magic string .gnu.linkonce is a linkonce | |
12383 | section. */ | |
12384 | if (strncmp (segment_name (symsec), ".gnu.linkonce", | |
12385 | sizeof ".gnu.linkonce" - 1) == 0) | |
12386 | linkonce = TRUE; | |
12387 | } | |
12388 | ||
12389 | /* This must duplicate the test in adjust_reloc_syms. */ | |
12390 | return (symsec != &bfd_und_section | |
12391 | && symsec != &bfd_abs_section | |
12392 | && ! bfd_is_com_section (symsec) | |
12393 | && !linkonce | |
12394 | #ifdef OBJ_ELF | |
12395 | /* A global or weak symbol is treated as external. */ | |
12396 | && (OUTPUT_FLAVOR != bfd_target_elf_flavour | |
3e722fb5 | 12397 | || (! S_IS_WEAK (sym) && ! S_IS_EXTERNAL (sym))) |
5919d012 RS |
12398 | #endif |
12399 | ); | |
12400 | } | |
12401 | ||
12402 | ||
252b5132 RH |
12403 | /* Given a mips16 variant frag FRAGP, return non-zero if it needs an |
12404 | extended opcode. SEC is the section the frag is in. */ | |
12405 | ||
12406 | static int | |
17a2f251 | 12407 | mips16_extended_frag (fragS *fragp, asection *sec, long stretch) |
252b5132 RH |
12408 | { |
12409 | int type; | |
12410 | register const struct mips16_immed_operand *op; | |
12411 | offsetT val; | |
12412 | int mintiny, maxtiny; | |
12413 | segT symsec; | |
98aa84af | 12414 | fragS *sym_frag; |
252b5132 RH |
12415 | |
12416 | if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype)) | |
12417 | return 0; | |
12418 | if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype)) | |
12419 | return 1; | |
12420 | ||
12421 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
12422 | op = mips16_immed_operands; | |
12423 | while (op->type != type) | |
12424 | { | |
12425 | ++op; | |
12426 | assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); | |
12427 | } | |
12428 | ||
12429 | if (op->unsp) | |
12430 | { | |
12431 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
12432 | { | |
12433 | mintiny = 1; | |
12434 | maxtiny = 1 << op->nbits; | |
12435 | } | |
12436 | else | |
12437 | { | |
12438 | mintiny = 0; | |
12439 | maxtiny = (1 << op->nbits) - 1; | |
12440 | } | |
12441 | } | |
12442 | else | |
12443 | { | |
12444 | mintiny = - (1 << (op->nbits - 1)); | |
12445 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
12446 | } | |
12447 | ||
98aa84af | 12448 | sym_frag = symbol_get_frag (fragp->fr_symbol); |
ac62c346 | 12449 | val = S_GET_VALUE (fragp->fr_symbol); |
98aa84af | 12450 | symsec = S_GET_SEGMENT (fragp->fr_symbol); |
252b5132 RH |
12451 | |
12452 | if (op->pcrel) | |
12453 | { | |
12454 | addressT addr; | |
12455 | ||
12456 | /* We won't have the section when we are called from | |
12457 | mips_relax_frag. However, we will always have been called | |
12458 | from md_estimate_size_before_relax first. If this is a | |
12459 | branch to a different section, we mark it as such. If SEC is | |
12460 | NULL, and the frag is not marked, then it must be a branch to | |
12461 | the same section. */ | |
12462 | if (sec == NULL) | |
12463 | { | |
12464 | if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype)) | |
12465 | return 1; | |
12466 | } | |
12467 | else | |
12468 | { | |
98aa84af | 12469 | /* Must have been called from md_estimate_size_before_relax. */ |
252b5132 RH |
12470 | if (symsec != sec) |
12471 | { | |
12472 | fragp->fr_subtype = | |
12473 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
12474 | ||
12475 | /* FIXME: We should support this, and let the linker | |
12476 | catch branches and loads that are out of range. */ | |
12477 | as_bad_where (fragp->fr_file, fragp->fr_line, | |
12478 | _("unsupported PC relative reference to different section")); | |
12479 | ||
12480 | return 1; | |
12481 | } | |
98aa84af AM |
12482 | if (fragp != sym_frag && sym_frag->fr_address == 0) |
12483 | /* Assume non-extended on the first relaxation pass. | |
12484 | The address we have calculated will be bogus if this is | |
12485 | a forward branch to another frag, as the forward frag | |
12486 | will have fr_address == 0. */ | |
12487 | return 0; | |
252b5132 RH |
12488 | } |
12489 | ||
12490 | /* In this case, we know for sure that the symbol fragment is in | |
98aa84af AM |
12491 | the same section. If the relax_marker of the symbol fragment |
12492 | differs from the relax_marker of this fragment, we have not | |
12493 | yet adjusted the symbol fragment fr_address. We want to add | |
252b5132 RH |
12494 | in STRETCH in order to get a better estimate of the address. |
12495 | This particularly matters because of the shift bits. */ | |
12496 | if (stretch != 0 | |
98aa84af | 12497 | && sym_frag->relax_marker != fragp->relax_marker) |
252b5132 RH |
12498 | { |
12499 | fragS *f; | |
12500 | ||
12501 | /* Adjust stretch for any alignment frag. Note that if have | |
12502 | been expanding the earlier code, the symbol may be | |
12503 | defined in what appears to be an earlier frag. FIXME: | |
12504 | This doesn't handle the fr_subtype field, which specifies | |
12505 | a maximum number of bytes to skip when doing an | |
12506 | alignment. */ | |
98aa84af | 12507 | for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next) |
252b5132 RH |
12508 | { |
12509 | if (f->fr_type == rs_align || f->fr_type == rs_align_code) | |
12510 | { | |
12511 | if (stretch < 0) | |
12512 | stretch = - ((- stretch) | |
12513 | & ~ ((1 << (int) f->fr_offset) - 1)); | |
12514 | else | |
12515 | stretch &= ~ ((1 << (int) f->fr_offset) - 1); | |
12516 | if (stretch == 0) | |
12517 | break; | |
12518 | } | |
12519 | } | |
12520 | if (f != NULL) | |
12521 | val += stretch; | |
12522 | } | |
12523 | ||
12524 | addr = fragp->fr_address + fragp->fr_fix; | |
12525 | ||
12526 | /* The base address rules are complicated. The base address of | |
12527 | a branch is the following instruction. The base address of a | |
12528 | PC relative load or add is the instruction itself, but if it | |
12529 | is in a delay slot (in which case it can not be extended) use | |
12530 | the address of the instruction whose delay slot it is in. */ | |
12531 | if (type == 'p' || type == 'q') | |
12532 | { | |
12533 | addr += 2; | |
12534 | ||
12535 | /* If we are currently assuming that this frag should be | |
12536 | extended, then, the current address is two bytes | |
bdaaa2e1 | 12537 | higher. */ |
252b5132 RH |
12538 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) |
12539 | addr += 2; | |
12540 | ||
12541 | /* Ignore the low bit in the target, since it will be set | |
12542 | for a text label. */ | |
12543 | if ((val & 1) != 0) | |
12544 | --val; | |
12545 | } | |
12546 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) | |
12547 | addr -= 4; | |
12548 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
12549 | addr -= 2; | |
12550 | ||
12551 | val -= addr & ~ ((1 << op->shift) - 1); | |
12552 | ||
12553 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
12554 | if (type == 'p' || type == 'q') | |
12555 | val /= 2; | |
12556 | ||
12557 | /* If any of the shifted bits are set, we must use an extended | |
12558 | opcode. If the address depends on the size of this | |
12559 | instruction, this can lead to a loop, so we arrange to always | |
12560 | use an extended opcode. We only check this when we are in | |
12561 | the main relaxation loop, when SEC is NULL. */ | |
12562 | if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL) | |
12563 | { | |
12564 | fragp->fr_subtype = | |
12565 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
12566 | return 1; | |
12567 | } | |
12568 | ||
12569 | /* If we are about to mark a frag as extended because the value | |
12570 | is precisely maxtiny + 1, then there is a chance of an | |
12571 | infinite loop as in the following code: | |
12572 | la $4,foo | |
12573 | .skip 1020 | |
12574 | .align 2 | |
12575 | foo: | |
12576 | In this case when the la is extended, foo is 0x3fc bytes | |
12577 | away, so the la can be shrunk, but then foo is 0x400 away, so | |
12578 | the la must be extended. To avoid this loop, we mark the | |
12579 | frag as extended if it was small, and is about to become | |
12580 | extended with a value of maxtiny + 1. */ | |
12581 | if (val == ((maxtiny + 1) << op->shift) | |
12582 | && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype) | |
12583 | && sec == NULL) | |
12584 | { | |
12585 | fragp->fr_subtype = | |
12586 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
12587 | return 1; | |
12588 | } | |
12589 | } | |
12590 | else if (symsec != absolute_section && sec != NULL) | |
12591 | as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation")); | |
12592 | ||
12593 | if ((val & ((1 << op->shift) - 1)) != 0 | |
12594 | || val < (mintiny << op->shift) | |
12595 | || val > (maxtiny << op->shift)) | |
12596 | return 1; | |
12597 | else | |
12598 | return 0; | |
12599 | } | |
12600 | ||
4a6a3df4 AO |
12601 | /* Compute the length of a branch sequence, and adjust the |
12602 | RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the | |
12603 | worst-case length is computed, with UPDATE being used to indicate | |
12604 | whether an unconditional (-1), branch-likely (+1) or regular (0) | |
12605 | branch is to be computed. */ | |
12606 | static int | |
17a2f251 | 12607 | relaxed_branch_length (fragS *fragp, asection *sec, int update) |
4a6a3df4 | 12608 | { |
b34976b6 | 12609 | bfd_boolean toofar; |
4a6a3df4 AO |
12610 | int length; |
12611 | ||
12612 | if (fragp | |
12613 | && S_IS_DEFINED (fragp->fr_symbol) | |
12614 | && sec == S_GET_SEGMENT (fragp->fr_symbol)) | |
12615 | { | |
12616 | addressT addr; | |
12617 | offsetT val; | |
12618 | ||
12619 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; | |
12620 | ||
12621 | addr = fragp->fr_address + fragp->fr_fix + 4; | |
12622 | ||
12623 | val -= addr; | |
12624 | ||
12625 | toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2); | |
12626 | } | |
12627 | else if (fragp) | |
12628 | /* If the symbol is not defined or it's in a different segment, | |
12629 | assume the user knows what's going on and emit a short | |
12630 | branch. */ | |
b34976b6 | 12631 | toofar = FALSE; |
4a6a3df4 | 12632 | else |
b34976b6 | 12633 | toofar = TRUE; |
4a6a3df4 AO |
12634 | |
12635 | if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) | |
12636 | fragp->fr_subtype | |
af6ae2ad | 12637 | = RELAX_BRANCH_ENCODE (RELAX_BRANCH_UNCOND (fragp->fr_subtype), |
4a6a3df4 AO |
12638 | RELAX_BRANCH_LIKELY (fragp->fr_subtype), |
12639 | RELAX_BRANCH_LINK (fragp->fr_subtype), | |
12640 | toofar); | |
12641 | ||
12642 | length = 4; | |
12643 | if (toofar) | |
12644 | { | |
12645 | if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0)) | |
12646 | length += 8; | |
12647 | ||
12648 | if (mips_pic != NO_PIC) | |
12649 | { | |
12650 | /* Additional space for PIC loading of target address. */ | |
12651 | length += 8; | |
12652 | if (mips_opts.isa == ISA_MIPS1) | |
12653 | /* Additional space for $at-stabilizing nop. */ | |
12654 | length += 4; | |
12655 | } | |
12656 | ||
12657 | /* If branch is conditional. */ | |
12658 | if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0)) | |
12659 | length += 8; | |
12660 | } | |
b34976b6 | 12661 | |
4a6a3df4 AO |
12662 | return length; |
12663 | } | |
12664 | ||
252b5132 RH |
12665 | /* Estimate the size of a frag before relaxing. Unless this is the |
12666 | mips16, we are not really relaxing here, and the final size is | |
12667 | encoded in the subtype information. For the mips16, we have to | |
12668 | decide whether we are using an extended opcode or not. */ | |
12669 | ||
252b5132 | 12670 | int |
17a2f251 | 12671 | md_estimate_size_before_relax (fragS *fragp, asection *segtype) |
252b5132 | 12672 | { |
5919d012 | 12673 | int change; |
252b5132 | 12674 | |
4a6a3df4 AO |
12675 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
12676 | { | |
12677 | ||
b34976b6 AM |
12678 | fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE); |
12679 | ||
4a6a3df4 AO |
12680 | return fragp->fr_var; |
12681 | } | |
12682 | ||
252b5132 | 12683 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
177b4a6a AO |
12684 | /* We don't want to modify the EXTENDED bit here; it might get us |
12685 | into infinite loops. We change it only in mips_relax_frag(). */ | |
12686 | return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2); | |
252b5132 RH |
12687 | |
12688 | if (mips_pic == NO_PIC) | |
5919d012 | 12689 | change = nopic_need_relax (fragp->fr_symbol, 0); |
252b5132 | 12690 | else if (mips_pic == SVR4_PIC) |
5919d012 | 12691 | change = pic_need_relax (fragp->fr_symbol, segtype); |
252b5132 RH |
12692 | else |
12693 | abort (); | |
12694 | ||
12695 | if (change) | |
12696 | { | |
4d7206a2 | 12697 | fragp->fr_subtype |= RELAX_USE_SECOND; |
4d7206a2 | 12698 | return -RELAX_FIRST (fragp->fr_subtype); |
252b5132 | 12699 | } |
4d7206a2 RS |
12700 | else |
12701 | return -RELAX_SECOND (fragp->fr_subtype); | |
252b5132 RH |
12702 | } |
12703 | ||
12704 | /* This is called to see whether a reloc against a defined symbol | |
de7e6852 | 12705 | should be converted into a reloc against a section. */ |
252b5132 RH |
12706 | |
12707 | int | |
17a2f251 | 12708 | mips_fix_adjustable (fixS *fixp) |
252b5132 | 12709 | { |
de7e6852 RS |
12710 | /* Don't adjust MIPS16 jump relocations, so we don't have to worry |
12711 | about the format of the offset in the .o file. */ | |
252b5132 RH |
12712 | if (fixp->fx_r_type == BFD_RELOC_MIPS16_JMP) |
12713 | return 0; | |
a161fe53 | 12714 | |
252b5132 RH |
12715 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
12716 | || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
12717 | return 0; | |
a161fe53 | 12718 | |
252b5132 RH |
12719 | if (fixp->fx_addsy == NULL) |
12720 | return 1; | |
a161fe53 | 12721 | |
de7e6852 RS |
12722 | /* If symbol SYM is in a mergeable section, relocations of the form |
12723 | SYM + 0 can usually be made section-relative. The mergeable data | |
12724 | is then identified by the section offset rather than by the symbol. | |
12725 | ||
12726 | However, if we're generating REL LO16 relocations, the offset is split | |
12727 | between the LO16 and parterning high part relocation. The linker will | |
12728 | need to recalculate the complete offset in order to correctly identify | |
12729 | the merge data. | |
12730 | ||
12731 | The linker has traditionally not looked for the parterning high part | |
12732 | relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be | |
12733 | placed anywhere. Rather than break backwards compatibility by changing | |
12734 | this, it seems better not to force the issue, and instead keep the | |
12735 | original symbol. This will work with either linker behavior. */ | |
12736 | if ((fixp->fx_r_type == BFD_RELOC_LO16 || reloc_needs_lo_p (fixp->fx_r_type)) | |
12737 | && HAVE_IN_PLACE_ADDENDS | |
12738 | && (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_MERGE) != 0) | |
12739 | return 0; | |
12740 | ||
252b5132 | 12741 | #ifdef OBJ_ELF |
de7e6852 RS |
12742 | /* Don't adjust relocations against mips16 symbols, so that the linker |
12743 | can find them if it needs to set up a stub. */ | |
252b5132 RH |
12744 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour |
12745 | && S_GET_OTHER (fixp->fx_addsy) == STO_MIPS16 | |
12746 | && fixp->fx_subsy == NULL) | |
12747 | return 0; | |
12748 | #endif | |
a161fe53 | 12749 | |
252b5132 RH |
12750 | return 1; |
12751 | } | |
12752 | ||
12753 | /* Translate internal representation of relocation info to BFD target | |
12754 | format. */ | |
12755 | ||
12756 | arelent ** | |
17a2f251 | 12757 | tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) |
252b5132 RH |
12758 | { |
12759 | static arelent *retval[4]; | |
12760 | arelent *reloc; | |
12761 | bfd_reloc_code_real_type code; | |
12762 | ||
4b0cff4e TS |
12763 | memset (retval, 0, sizeof(retval)); |
12764 | reloc = retval[0] = (arelent *) xcalloc (1, sizeof (arelent)); | |
49309057 ILT |
12765 | reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); |
12766 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
252b5132 RH |
12767 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; |
12768 | ||
3e722fb5 CD |
12769 | assert (! fixp->fx_pcrel); |
12770 | reloc->addend = fixp->fx_addnumber; | |
252b5132 | 12771 | |
438c16b8 TS |
12772 | /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable |
12773 | entry to be used in the relocation's section offset. */ | |
12774 | if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
252b5132 RH |
12775 | { |
12776 | reloc->address = reloc->addend; | |
12777 | reloc->addend = 0; | |
12778 | } | |
12779 | ||
252b5132 | 12780 | code = fixp->fx_r_type; |
252b5132 | 12781 | |
3e722fb5 CD |
12782 | /* To support a PC relative reloc, we used a Cygnus extension. |
12783 | We check for that here to make sure that we don't let such a | |
12784 | reloc escape normally. (FIXME: This was formerly used by | |
12785 | embedded-PIC support, but is now used by branch handling in | |
12786 | general. That probably should be fixed.) */ | |
0b25d3e6 AO |
12787 | if ((OUTPUT_FLAVOR == bfd_target_ecoff_flavour |
12788 | || OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
3e722fb5 | 12789 | && code == BFD_RELOC_16_PCREL_S2) |
0b25d3e6 AO |
12790 | reloc->howto = NULL; |
12791 | else | |
12792 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); | |
12793 | ||
252b5132 RH |
12794 | if (reloc->howto == NULL) |
12795 | { | |
12796 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
12797 | _("Can not represent %s relocation in this object file format"), | |
12798 | bfd_get_reloc_code_name (code)); | |
12799 | retval[0] = NULL; | |
12800 | } | |
12801 | ||
12802 | return retval; | |
12803 | } | |
12804 | ||
12805 | /* Relax a machine dependent frag. This returns the amount by which | |
12806 | the current size of the frag should change. */ | |
12807 | ||
12808 | int | |
17a2f251 | 12809 | mips_relax_frag (asection *sec, fragS *fragp, long stretch) |
252b5132 | 12810 | { |
4a6a3df4 AO |
12811 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
12812 | { | |
12813 | offsetT old_var = fragp->fr_var; | |
b34976b6 AM |
12814 | |
12815 | fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE); | |
4a6a3df4 AO |
12816 | |
12817 | return fragp->fr_var - old_var; | |
12818 | } | |
12819 | ||
252b5132 RH |
12820 | if (! RELAX_MIPS16_P (fragp->fr_subtype)) |
12821 | return 0; | |
12822 | ||
c4e7957c | 12823 | if (mips16_extended_frag (fragp, NULL, stretch)) |
252b5132 RH |
12824 | { |
12825 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
12826 | return 0; | |
12827 | fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype); | |
12828 | return 2; | |
12829 | } | |
12830 | else | |
12831 | { | |
12832 | if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
12833 | return 0; | |
12834 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype); | |
12835 | return -2; | |
12836 | } | |
12837 | ||
12838 | return 0; | |
12839 | } | |
12840 | ||
12841 | /* Convert a machine dependent frag. */ | |
12842 | ||
12843 | void | |
17a2f251 | 12844 | md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp) |
252b5132 | 12845 | { |
4a6a3df4 AO |
12846 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
12847 | { | |
12848 | bfd_byte *buf; | |
12849 | unsigned long insn; | |
12850 | expressionS exp; | |
12851 | fixS *fixp; | |
b34976b6 | 12852 | |
4a6a3df4 AO |
12853 | buf = (bfd_byte *)fragp->fr_literal + fragp->fr_fix; |
12854 | ||
12855 | if (target_big_endian) | |
12856 | insn = bfd_getb32 (buf); | |
12857 | else | |
12858 | insn = bfd_getl32 (buf); | |
b34976b6 | 12859 | |
4a6a3df4 AO |
12860 | if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) |
12861 | { | |
12862 | /* We generate a fixup instead of applying it right now | |
12863 | because, if there are linker relaxations, we're going to | |
12864 | need the relocations. */ | |
12865 | exp.X_op = O_symbol; | |
12866 | exp.X_add_symbol = fragp->fr_symbol; | |
12867 | exp.X_add_number = fragp->fr_offset; | |
12868 | ||
12869 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
0b25d3e6 AO |
12870 | 4, &exp, 1, |
12871 | BFD_RELOC_16_PCREL_S2); | |
4a6a3df4 AO |
12872 | fixp->fx_file = fragp->fr_file; |
12873 | fixp->fx_line = fragp->fr_line; | |
b34976b6 | 12874 | |
2132e3a3 | 12875 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
12876 | buf += 4; |
12877 | } | |
12878 | else | |
12879 | { | |
12880 | int i; | |
12881 | ||
12882 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
12883 | _("relaxed out-of-range branch into a jump")); | |
12884 | ||
12885 | if (RELAX_BRANCH_UNCOND (fragp->fr_subtype)) | |
12886 | goto uncond; | |
12887 | ||
12888 | if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
12889 | { | |
12890 | /* Reverse the branch. */ | |
12891 | switch ((insn >> 28) & 0xf) | |
12892 | { | |
12893 | case 4: | |
12894 | /* bc[0-3][tf]l? and bc1any[24][ft] instructions can | |
12895 | have the condition reversed by tweaking a single | |
12896 | bit, and their opcodes all have 0x4???????. */ | |
12897 | assert ((insn & 0xf1000000) == 0x41000000); | |
12898 | insn ^= 0x00010000; | |
12899 | break; | |
12900 | ||
12901 | case 0: | |
12902 | /* bltz 0x04000000 bgez 0x04010000 | |
12903 | bltzal 0x04100000 bgezal 0x04110000 */ | |
12904 | assert ((insn & 0xfc0e0000) == 0x04000000); | |
12905 | insn ^= 0x00010000; | |
12906 | break; | |
b34976b6 | 12907 | |
4a6a3df4 AO |
12908 | case 1: |
12909 | /* beq 0x10000000 bne 0x14000000 | |
12910 | blez 0x18000000 bgtz 0x1c000000 */ | |
12911 | insn ^= 0x04000000; | |
12912 | break; | |
12913 | ||
12914 | default: | |
12915 | abort (); | |
12916 | } | |
12917 | } | |
12918 | ||
12919 | if (RELAX_BRANCH_LINK (fragp->fr_subtype)) | |
12920 | { | |
12921 | /* Clear the and-link bit. */ | |
12922 | assert ((insn & 0xfc1c0000) == 0x04100000); | |
12923 | ||
12924 | /* bltzal 0x04100000 bgezal 0x04110000 | |
12925 | bltzall 0x04120000 bgezall 0x04130000 */ | |
12926 | insn &= ~0x00100000; | |
12927 | } | |
12928 | ||
12929 | /* Branch over the branch (if the branch was likely) or the | |
12930 | full jump (not likely case). Compute the offset from the | |
12931 | current instruction to branch to. */ | |
12932 | if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
12933 | i = 16; | |
12934 | else | |
12935 | { | |
12936 | /* How many bytes in instructions we've already emitted? */ | |
12937 | i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix; | |
12938 | /* How many bytes in instructions from here to the end? */ | |
12939 | i = fragp->fr_var - i; | |
12940 | } | |
12941 | /* Convert to instruction count. */ | |
12942 | i >>= 2; | |
12943 | /* Branch counts from the next instruction. */ | |
b34976b6 | 12944 | i--; |
4a6a3df4 AO |
12945 | insn |= i; |
12946 | /* Branch over the jump. */ | |
2132e3a3 | 12947 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
12948 | buf += 4; |
12949 | ||
12950 | /* Nop */ | |
2132e3a3 | 12951 | md_number_to_chars ((char *) buf, 0, 4); |
4a6a3df4 AO |
12952 | buf += 4; |
12953 | ||
12954 | if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
12955 | { | |
12956 | /* beql $0, $0, 2f */ | |
12957 | insn = 0x50000000; | |
12958 | /* Compute the PC offset from the current instruction to | |
12959 | the end of the variable frag. */ | |
12960 | /* How many bytes in instructions we've already emitted? */ | |
12961 | i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix; | |
12962 | /* How many bytes in instructions from here to the end? */ | |
12963 | i = fragp->fr_var - i; | |
12964 | /* Convert to instruction count. */ | |
12965 | i >>= 2; | |
12966 | /* Don't decrement i, because we want to branch over the | |
12967 | delay slot. */ | |
12968 | ||
12969 | insn |= i; | |
2132e3a3 | 12970 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
12971 | buf += 4; |
12972 | ||
2132e3a3 | 12973 | md_number_to_chars ((char *) buf, 0, 4); |
4a6a3df4 AO |
12974 | buf += 4; |
12975 | } | |
12976 | ||
12977 | uncond: | |
12978 | if (mips_pic == NO_PIC) | |
12979 | { | |
12980 | /* j or jal. */ | |
12981 | insn = (RELAX_BRANCH_LINK (fragp->fr_subtype) | |
12982 | ? 0x0c000000 : 0x08000000); | |
12983 | exp.X_op = O_symbol; | |
12984 | exp.X_add_symbol = fragp->fr_symbol; | |
12985 | exp.X_add_number = fragp->fr_offset; | |
12986 | ||
12987 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
12988 | 4, &exp, 0, BFD_RELOC_MIPS_JMP); | |
12989 | fixp->fx_file = fragp->fr_file; | |
12990 | fixp->fx_line = fragp->fr_line; | |
12991 | ||
2132e3a3 | 12992 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
12993 | buf += 4; |
12994 | } | |
12995 | else | |
12996 | { | |
12997 | /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */ | |
12998 | insn = HAVE_64BIT_ADDRESSES ? 0xdf810000 : 0x8f810000; | |
12999 | exp.X_op = O_symbol; | |
13000 | exp.X_add_symbol = fragp->fr_symbol; | |
13001 | exp.X_add_number = fragp->fr_offset; | |
13002 | ||
13003 | if (fragp->fr_offset) | |
13004 | { | |
13005 | exp.X_add_symbol = make_expr_symbol (&exp); | |
13006 | exp.X_add_number = 0; | |
13007 | } | |
13008 | ||
13009 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
13010 | 4, &exp, 0, BFD_RELOC_MIPS_GOT16); | |
13011 | fixp->fx_file = fragp->fr_file; | |
13012 | fixp->fx_line = fragp->fr_line; | |
13013 | ||
2132e3a3 | 13014 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 | 13015 | buf += 4; |
b34976b6 | 13016 | |
4a6a3df4 AO |
13017 | if (mips_opts.isa == ISA_MIPS1) |
13018 | { | |
13019 | /* nop */ | |
2132e3a3 | 13020 | md_number_to_chars ((char *) buf, 0, 4); |
4a6a3df4 AO |
13021 | buf += 4; |
13022 | } | |
13023 | ||
13024 | /* d/addiu $at, $at, <sym> R_MIPS_LO16 */ | |
13025 | insn = HAVE_64BIT_ADDRESSES ? 0x64210000 : 0x24210000; | |
13026 | ||
13027 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
13028 | 4, &exp, 0, BFD_RELOC_LO16); | |
13029 | fixp->fx_file = fragp->fr_file; | |
13030 | fixp->fx_line = fragp->fr_line; | |
b34976b6 | 13031 | |
2132e3a3 | 13032 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
13033 | buf += 4; |
13034 | ||
13035 | /* j(al)r $at. */ | |
13036 | if (RELAX_BRANCH_LINK (fragp->fr_subtype)) | |
13037 | insn = 0x0020f809; | |
13038 | else | |
13039 | insn = 0x00200008; | |
13040 | ||
2132e3a3 | 13041 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
13042 | buf += 4; |
13043 | } | |
13044 | } | |
13045 | ||
13046 | assert (buf == (bfd_byte *)fragp->fr_literal | |
13047 | + fragp->fr_fix + fragp->fr_var); | |
13048 | ||
13049 | fragp->fr_fix += fragp->fr_var; | |
13050 | ||
13051 | return; | |
13052 | } | |
13053 | ||
252b5132 RH |
13054 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
13055 | { | |
13056 | int type; | |
13057 | register const struct mips16_immed_operand *op; | |
b34976b6 | 13058 | bfd_boolean small, ext; |
252b5132 RH |
13059 | offsetT val; |
13060 | bfd_byte *buf; | |
13061 | unsigned long insn; | |
b34976b6 | 13062 | bfd_boolean use_extend; |
252b5132 RH |
13063 | unsigned short extend; |
13064 | ||
13065 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
13066 | op = mips16_immed_operands; | |
13067 | while (op->type != type) | |
13068 | ++op; | |
13069 | ||
13070 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
13071 | { | |
b34976b6 AM |
13072 | small = FALSE; |
13073 | ext = TRUE; | |
252b5132 RH |
13074 | } |
13075 | else | |
13076 | { | |
b34976b6 AM |
13077 | small = TRUE; |
13078 | ext = FALSE; | |
252b5132 RH |
13079 | } |
13080 | ||
6386f3a7 | 13081 | resolve_symbol_value (fragp->fr_symbol); |
252b5132 RH |
13082 | val = S_GET_VALUE (fragp->fr_symbol); |
13083 | if (op->pcrel) | |
13084 | { | |
13085 | addressT addr; | |
13086 | ||
13087 | addr = fragp->fr_address + fragp->fr_fix; | |
13088 | ||
13089 | /* The rules for the base address of a PC relative reloc are | |
13090 | complicated; see mips16_extended_frag. */ | |
13091 | if (type == 'p' || type == 'q') | |
13092 | { | |
13093 | addr += 2; | |
13094 | if (ext) | |
13095 | addr += 2; | |
13096 | /* Ignore the low bit in the target, since it will be | |
13097 | set for a text label. */ | |
13098 | if ((val & 1) != 0) | |
13099 | --val; | |
13100 | } | |
13101 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) | |
13102 | addr -= 4; | |
13103 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
13104 | addr -= 2; | |
13105 | ||
13106 | addr &= ~ (addressT) ((1 << op->shift) - 1); | |
13107 | val -= addr; | |
13108 | ||
13109 | /* Make sure the section winds up with the alignment we have | |
13110 | assumed. */ | |
13111 | if (op->shift > 0) | |
13112 | record_alignment (asec, op->shift); | |
13113 | } | |
13114 | ||
13115 | if (ext | |
13116 | && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype) | |
13117 | || RELAX_MIPS16_DSLOT (fragp->fr_subtype))) | |
13118 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
13119 | _("extended instruction in delay slot")); | |
13120 | ||
13121 | buf = (bfd_byte *) (fragp->fr_literal + fragp->fr_fix); | |
13122 | ||
13123 | if (target_big_endian) | |
13124 | insn = bfd_getb16 (buf); | |
13125 | else | |
13126 | insn = bfd_getl16 (buf); | |
13127 | ||
13128 | mips16_immed (fragp->fr_file, fragp->fr_line, type, val, | |
13129 | RELAX_MIPS16_USER_EXT (fragp->fr_subtype), | |
13130 | small, ext, &insn, &use_extend, &extend); | |
13131 | ||
13132 | if (use_extend) | |
13133 | { | |
2132e3a3 | 13134 | md_number_to_chars ((char *) buf, 0xf000 | extend, 2); |
252b5132 RH |
13135 | fragp->fr_fix += 2; |
13136 | buf += 2; | |
13137 | } | |
13138 | ||
2132e3a3 | 13139 | md_number_to_chars ((char *) buf, insn, 2); |
252b5132 RH |
13140 | fragp->fr_fix += 2; |
13141 | buf += 2; | |
13142 | } | |
13143 | else | |
13144 | { | |
4d7206a2 RS |
13145 | int first, second; |
13146 | fixS *fixp; | |
252b5132 | 13147 | |
4d7206a2 RS |
13148 | first = RELAX_FIRST (fragp->fr_subtype); |
13149 | second = RELAX_SECOND (fragp->fr_subtype); | |
13150 | fixp = (fixS *) fragp->fr_opcode; | |
252b5132 | 13151 | |
584892a6 RS |
13152 | /* Possibly emit a warning if we've chosen the longer option. */ |
13153 | if (((fragp->fr_subtype & RELAX_USE_SECOND) != 0) | |
13154 | == ((fragp->fr_subtype & RELAX_SECOND_LONGER) != 0)) | |
13155 | { | |
13156 | const char *msg = macro_warning (fragp->fr_subtype); | |
13157 | if (msg != 0) | |
13158 | as_warn_where (fragp->fr_file, fragp->fr_line, msg); | |
13159 | } | |
13160 | ||
4d7206a2 RS |
13161 | /* Go through all the fixups for the first sequence. Disable them |
13162 | (by marking them as done) if we're going to use the second | |
13163 | sequence instead. */ | |
13164 | while (fixp | |
13165 | && fixp->fx_frag == fragp | |
13166 | && fixp->fx_where < fragp->fr_fix - second) | |
13167 | { | |
13168 | if (fragp->fr_subtype & RELAX_USE_SECOND) | |
13169 | fixp->fx_done = 1; | |
13170 | fixp = fixp->fx_next; | |
13171 | } | |
252b5132 | 13172 | |
4d7206a2 RS |
13173 | /* Go through the fixups for the second sequence. Disable them if |
13174 | we're going to use the first sequence, otherwise adjust their | |
13175 | addresses to account for the relaxation. */ | |
13176 | while (fixp && fixp->fx_frag == fragp) | |
13177 | { | |
13178 | if (fragp->fr_subtype & RELAX_USE_SECOND) | |
13179 | fixp->fx_where -= first; | |
13180 | else | |
13181 | fixp->fx_done = 1; | |
13182 | fixp = fixp->fx_next; | |
13183 | } | |
13184 | ||
13185 | /* Now modify the frag contents. */ | |
13186 | if (fragp->fr_subtype & RELAX_USE_SECOND) | |
13187 | { | |
13188 | char *start; | |
13189 | ||
13190 | start = fragp->fr_literal + fragp->fr_fix - first - second; | |
13191 | memmove (start, start + first, second); | |
13192 | fragp->fr_fix -= first; | |
13193 | } | |
13194 | else | |
13195 | fragp->fr_fix -= second; | |
252b5132 RH |
13196 | } |
13197 | } | |
13198 | ||
13199 | #ifdef OBJ_ELF | |
13200 | ||
13201 | /* This function is called after the relocs have been generated. | |
13202 | We've been storing mips16 text labels as odd. Here we convert them | |
13203 | back to even for the convenience of the debugger. */ | |
13204 | ||
13205 | void | |
17a2f251 | 13206 | mips_frob_file_after_relocs (void) |
252b5132 RH |
13207 | { |
13208 | asymbol **syms; | |
13209 | unsigned int count, i; | |
13210 | ||
13211 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
13212 | return; | |
13213 | ||
13214 | syms = bfd_get_outsymbols (stdoutput); | |
13215 | count = bfd_get_symcount (stdoutput); | |
13216 | for (i = 0; i < count; i++, syms++) | |
13217 | { | |
13218 | if (elf_symbol (*syms)->internal_elf_sym.st_other == STO_MIPS16 | |
13219 | && ((*syms)->value & 1) != 0) | |
13220 | { | |
13221 | (*syms)->value &= ~1; | |
13222 | /* If the symbol has an odd size, it was probably computed | |
13223 | incorrectly, so adjust that as well. */ | |
13224 | if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0) | |
13225 | ++elf_symbol (*syms)->internal_elf_sym.st_size; | |
13226 | } | |
13227 | } | |
13228 | } | |
13229 | ||
13230 | #endif | |
13231 | ||
13232 | /* This function is called whenever a label is defined. It is used | |
13233 | when handling branch delays; if a branch has a label, we assume we | |
13234 | can not move it. */ | |
13235 | ||
13236 | void | |
17a2f251 | 13237 | mips_define_label (symbolS *sym) |
252b5132 RH |
13238 | { |
13239 | struct insn_label_list *l; | |
13240 | ||
13241 | if (free_insn_labels == NULL) | |
13242 | l = (struct insn_label_list *) xmalloc (sizeof *l); | |
13243 | else | |
13244 | { | |
13245 | l = free_insn_labels; | |
13246 | free_insn_labels = l->next; | |
13247 | } | |
13248 | ||
13249 | l->label = sym; | |
13250 | l->next = insn_labels; | |
13251 | insn_labels = l; | |
13252 | } | |
13253 | \f | |
13254 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
13255 | ||
13256 | /* Some special processing for a MIPS ELF file. */ | |
13257 | ||
13258 | void | |
17a2f251 | 13259 | mips_elf_final_processing (void) |
252b5132 RH |
13260 | { |
13261 | /* Write out the register information. */ | |
316f5878 | 13262 | if (mips_abi != N64_ABI) |
252b5132 RH |
13263 | { |
13264 | Elf32_RegInfo s; | |
13265 | ||
13266 | s.ri_gprmask = mips_gprmask; | |
13267 | s.ri_cprmask[0] = mips_cprmask[0]; | |
13268 | s.ri_cprmask[1] = mips_cprmask[1]; | |
13269 | s.ri_cprmask[2] = mips_cprmask[2]; | |
13270 | s.ri_cprmask[3] = mips_cprmask[3]; | |
13271 | /* The gp_value field is set by the MIPS ELF backend. */ | |
13272 | ||
13273 | bfd_mips_elf32_swap_reginfo_out (stdoutput, &s, | |
13274 | ((Elf32_External_RegInfo *) | |
13275 | mips_regmask_frag)); | |
13276 | } | |
13277 | else | |
13278 | { | |
13279 | Elf64_Internal_RegInfo s; | |
13280 | ||
13281 | s.ri_gprmask = mips_gprmask; | |
13282 | s.ri_pad = 0; | |
13283 | s.ri_cprmask[0] = mips_cprmask[0]; | |
13284 | s.ri_cprmask[1] = mips_cprmask[1]; | |
13285 | s.ri_cprmask[2] = mips_cprmask[2]; | |
13286 | s.ri_cprmask[3] = mips_cprmask[3]; | |
13287 | /* The gp_value field is set by the MIPS ELF backend. */ | |
13288 | ||
13289 | bfd_mips_elf64_swap_reginfo_out (stdoutput, &s, | |
13290 | ((Elf64_External_RegInfo *) | |
13291 | mips_regmask_frag)); | |
13292 | } | |
13293 | ||
13294 | /* Set the MIPS ELF flag bits. FIXME: There should probably be some | |
13295 | sort of BFD interface for this. */ | |
13296 | if (mips_any_noreorder) | |
13297 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER; | |
13298 | if (mips_pic != NO_PIC) | |
143d77c5 | 13299 | { |
252b5132 | 13300 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC; |
143d77c5 EC |
13301 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC; |
13302 | } | |
13303 | if (mips_abicalls) | |
13304 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC; | |
252b5132 | 13305 | |
98d3f06f | 13306 | /* Set MIPS ELF flags for ASEs. */ |
a4672219 TS |
13307 | if (file_ase_mips16) |
13308 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16; | |
1f25f5d3 CD |
13309 | #if 0 /* XXX FIXME */ |
13310 | if (file_ase_mips3d) | |
13311 | elf_elfheader (stdoutput)->e_flags |= ???; | |
13312 | #endif | |
deec1734 CD |
13313 | if (file_ase_mdmx) |
13314 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX; | |
1f25f5d3 | 13315 | |
bdaaa2e1 | 13316 | /* Set the MIPS ELF ABI flags. */ |
316f5878 | 13317 | if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32) |
252b5132 | 13318 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32; |
316f5878 | 13319 | else if (mips_abi == O64_ABI) |
252b5132 | 13320 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64; |
316f5878 | 13321 | else if (mips_abi == EABI_ABI) |
252b5132 | 13322 | { |
316f5878 | 13323 | if (!file_mips_gp32) |
252b5132 RH |
13324 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64; |
13325 | else | |
13326 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32; | |
13327 | } | |
316f5878 | 13328 | else if (mips_abi == N32_ABI) |
be00bddd TS |
13329 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2; |
13330 | ||
c9914766 | 13331 | /* Nothing to do for N64_ABI. */ |
252b5132 RH |
13332 | |
13333 | if (mips_32bitmode) | |
13334 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE; | |
13335 | } | |
13336 | ||
13337 | #endif /* OBJ_ELF || OBJ_MAYBE_ELF */ | |
13338 | \f | |
beae10d5 | 13339 | typedef struct proc { |
9b2f1d35 EC |
13340 | symbolS *func_sym; |
13341 | symbolS *func_end_sym; | |
beae10d5 KH |
13342 | unsigned long reg_mask; |
13343 | unsigned long reg_offset; | |
13344 | unsigned long fpreg_mask; | |
13345 | unsigned long fpreg_offset; | |
13346 | unsigned long frame_offset; | |
13347 | unsigned long frame_reg; | |
13348 | unsigned long pc_reg; | |
13349 | } procS; | |
252b5132 RH |
13350 | |
13351 | static procS cur_proc; | |
13352 | static procS *cur_proc_ptr; | |
13353 | static int numprocs; | |
13354 | ||
0a9ef439 | 13355 | /* Fill in an rs_align_code fragment. */ |
a19d8eb0 | 13356 | |
0a9ef439 | 13357 | void |
17a2f251 | 13358 | mips_handle_align (fragS *fragp) |
a19d8eb0 | 13359 | { |
0a9ef439 RH |
13360 | if (fragp->fr_type != rs_align_code) |
13361 | return; | |
13362 | ||
13363 | if (mips_opts.mips16) | |
a19d8eb0 CP |
13364 | { |
13365 | static const unsigned char be_nop[] = { 0x65, 0x00 }; | |
13366 | static const unsigned char le_nop[] = { 0x00, 0x65 }; | |
13367 | ||
0a9ef439 RH |
13368 | int bytes; |
13369 | char *p; | |
a19d8eb0 | 13370 | |
0a9ef439 RH |
13371 | bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix; |
13372 | p = fragp->fr_literal + fragp->fr_fix; | |
13373 | ||
13374 | if (bytes & 1) | |
13375 | { | |
13376 | *p++ = 0; | |
f9419b05 | 13377 | fragp->fr_fix++; |
0a9ef439 RH |
13378 | } |
13379 | ||
13380 | memcpy (p, (target_big_endian ? be_nop : le_nop), 2); | |
13381 | fragp->fr_var = 2; | |
a19d8eb0 CP |
13382 | } |
13383 | ||
0a9ef439 | 13384 | /* For mips32, a nop is a zero, which we trivially get by doing nothing. */ |
a19d8eb0 CP |
13385 | } |
13386 | ||
252b5132 | 13387 | static void |
17a2f251 | 13388 | md_obj_begin (void) |
252b5132 RH |
13389 | { |
13390 | } | |
13391 | ||
13392 | static void | |
17a2f251 | 13393 | md_obj_end (void) |
252b5132 RH |
13394 | { |
13395 | /* check for premature end, nesting errors, etc */ | |
13396 | if (cur_proc_ptr) | |
9a41af64 | 13397 | as_warn (_("missing .end at end of assembly")); |
252b5132 RH |
13398 | } |
13399 | ||
13400 | static long | |
17a2f251 | 13401 | get_number (void) |
252b5132 RH |
13402 | { |
13403 | int negative = 0; | |
13404 | long val = 0; | |
13405 | ||
13406 | if (*input_line_pointer == '-') | |
13407 | { | |
13408 | ++input_line_pointer; | |
13409 | negative = 1; | |
13410 | } | |
3882b010 | 13411 | if (!ISDIGIT (*input_line_pointer)) |
956cd1d6 | 13412 | as_bad (_("expected simple number")); |
252b5132 RH |
13413 | if (input_line_pointer[0] == '0') |
13414 | { | |
13415 | if (input_line_pointer[1] == 'x') | |
13416 | { | |
13417 | input_line_pointer += 2; | |
3882b010 | 13418 | while (ISXDIGIT (*input_line_pointer)) |
252b5132 RH |
13419 | { |
13420 | val <<= 4; | |
13421 | val |= hex_value (*input_line_pointer++); | |
13422 | } | |
13423 | return negative ? -val : val; | |
13424 | } | |
13425 | else | |
13426 | { | |
13427 | ++input_line_pointer; | |
3882b010 | 13428 | while (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
13429 | { |
13430 | val <<= 3; | |
13431 | val |= *input_line_pointer++ - '0'; | |
13432 | } | |
13433 | return negative ? -val : val; | |
13434 | } | |
13435 | } | |
3882b010 | 13436 | if (!ISDIGIT (*input_line_pointer)) |
252b5132 RH |
13437 | { |
13438 | printf (_(" *input_line_pointer == '%c' 0x%02x\n"), | |
13439 | *input_line_pointer, *input_line_pointer); | |
956cd1d6 | 13440 | as_warn (_("invalid number")); |
252b5132 RH |
13441 | return -1; |
13442 | } | |
3882b010 | 13443 | while (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
13444 | { |
13445 | val *= 10; | |
13446 | val += *input_line_pointer++ - '0'; | |
13447 | } | |
13448 | return negative ? -val : val; | |
13449 | } | |
13450 | ||
13451 | /* The .file directive; just like the usual .file directive, but there | |
c5dd6aab DJ |
13452 | is an initial number which is the ECOFF file index. In the non-ECOFF |
13453 | case .file implies DWARF-2. */ | |
13454 | ||
13455 | static void | |
17a2f251 | 13456 | s_mips_file (int x ATTRIBUTE_UNUSED) |
c5dd6aab | 13457 | { |
ecb4347a DJ |
13458 | static int first_file_directive = 0; |
13459 | ||
c5dd6aab DJ |
13460 | if (ECOFF_DEBUGGING) |
13461 | { | |
13462 | get_number (); | |
13463 | s_app_file (0); | |
13464 | } | |
13465 | else | |
ecb4347a DJ |
13466 | { |
13467 | char *filename; | |
13468 | ||
13469 | filename = dwarf2_directive_file (0); | |
13470 | ||
13471 | /* Versions of GCC up to 3.1 start files with a ".file" | |
13472 | directive even for stabs output. Make sure that this | |
13473 | ".file" is handled. Note that you need a version of GCC | |
13474 | after 3.1 in order to support DWARF-2 on MIPS. */ | |
13475 | if (filename != NULL && ! first_file_directive) | |
13476 | { | |
13477 | (void) new_logical_line (filename, -1); | |
c04f5787 | 13478 | s_app_file_string (filename, 0); |
ecb4347a DJ |
13479 | } |
13480 | first_file_directive = 1; | |
13481 | } | |
c5dd6aab DJ |
13482 | } |
13483 | ||
13484 | /* The .loc directive, implying DWARF-2. */ | |
252b5132 RH |
13485 | |
13486 | static void | |
17a2f251 | 13487 | s_mips_loc (int x ATTRIBUTE_UNUSED) |
252b5132 | 13488 | { |
c5dd6aab DJ |
13489 | if (!ECOFF_DEBUGGING) |
13490 | dwarf2_directive_loc (0); | |
252b5132 RH |
13491 | } |
13492 | ||
252b5132 RH |
13493 | /* The .end directive. */ |
13494 | ||
13495 | static void | |
17a2f251 | 13496 | s_mips_end (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
13497 | { |
13498 | symbolS *p; | |
252b5132 | 13499 | |
7a621144 DJ |
13500 | /* Following functions need their own .frame and .cprestore directives. */ |
13501 | mips_frame_reg_valid = 0; | |
13502 | mips_cprestore_valid = 0; | |
13503 | ||
252b5132 RH |
13504 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
13505 | { | |
13506 | p = get_symbol (); | |
13507 | demand_empty_rest_of_line (); | |
13508 | } | |
13509 | else | |
13510 | p = NULL; | |
13511 | ||
14949570 | 13512 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0) |
252b5132 RH |
13513 | as_warn (_(".end not in text section")); |
13514 | ||
13515 | if (!cur_proc_ptr) | |
13516 | { | |
13517 | as_warn (_(".end directive without a preceding .ent directive.")); | |
13518 | demand_empty_rest_of_line (); | |
13519 | return; | |
13520 | } | |
13521 | ||
13522 | if (p != NULL) | |
13523 | { | |
13524 | assert (S_GET_NAME (p)); | |
9b2f1d35 | 13525 | if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->func_sym))) |
252b5132 | 13526 | as_warn (_(".end symbol does not match .ent symbol.")); |
ecb4347a DJ |
13527 | |
13528 | if (debug_type == DEBUG_STABS) | |
13529 | stabs_generate_asm_endfunc (S_GET_NAME (p), | |
13530 | S_GET_NAME (p)); | |
252b5132 RH |
13531 | } |
13532 | else | |
13533 | as_warn (_(".end directive missing or unknown symbol")); | |
13534 | ||
2132e3a3 | 13535 | #ifdef OBJ_ELF |
9b2f1d35 EC |
13536 | /* Create an expression to calculate the size of the function. */ |
13537 | if (p && cur_proc_ptr) | |
13538 | { | |
13539 | OBJ_SYMFIELD_TYPE *obj = symbol_get_obj (p); | |
13540 | expressionS *exp = xmalloc (sizeof (expressionS)); | |
13541 | ||
13542 | obj->size = exp; | |
13543 | exp->X_op = O_subtract; | |
13544 | exp->X_add_symbol = symbol_temp_new_now (); | |
13545 | exp->X_op_symbol = p; | |
13546 | exp->X_add_number = 0; | |
13547 | ||
13548 | cur_proc_ptr->func_end_sym = exp->X_add_symbol; | |
13549 | } | |
13550 | ||
ecb4347a | 13551 | /* Generate a .pdr section. */ |
dcd410fe RO |
13552 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING |
13553 | && mips_flag_pdr) | |
ecb4347a DJ |
13554 | { |
13555 | segT saved_seg = now_seg; | |
13556 | subsegT saved_subseg = now_subseg; | |
13557 | valueT dot; | |
13558 | expressionS exp; | |
13559 | char *fragp; | |
252b5132 | 13560 | |
ecb4347a | 13561 | dot = frag_now_fix (); |
252b5132 RH |
13562 | |
13563 | #ifdef md_flush_pending_output | |
ecb4347a | 13564 | md_flush_pending_output (); |
252b5132 RH |
13565 | #endif |
13566 | ||
ecb4347a DJ |
13567 | assert (pdr_seg); |
13568 | subseg_set (pdr_seg, 0); | |
252b5132 | 13569 | |
ecb4347a DJ |
13570 | /* Write the symbol. */ |
13571 | exp.X_op = O_symbol; | |
13572 | exp.X_add_symbol = p; | |
13573 | exp.X_add_number = 0; | |
13574 | emit_expr (&exp, 4); | |
252b5132 | 13575 | |
ecb4347a | 13576 | fragp = frag_more (7 * 4); |
252b5132 | 13577 | |
17a2f251 TS |
13578 | md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4); |
13579 | md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4); | |
13580 | md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4); | |
13581 | md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4); | |
13582 | md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4); | |
13583 | md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4); | |
13584 | md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4); | |
252b5132 | 13585 | |
ecb4347a DJ |
13586 | subseg_set (saved_seg, saved_subseg); |
13587 | } | |
13588 | #endif /* OBJ_ELF */ | |
252b5132 RH |
13589 | |
13590 | cur_proc_ptr = NULL; | |
13591 | } | |
13592 | ||
13593 | /* The .aent and .ent directives. */ | |
13594 | ||
13595 | static void | |
17a2f251 | 13596 | s_mips_ent (int aent) |
252b5132 | 13597 | { |
252b5132 | 13598 | symbolS *symbolP; |
252b5132 RH |
13599 | |
13600 | symbolP = get_symbol (); | |
13601 | if (*input_line_pointer == ',') | |
f9419b05 | 13602 | ++input_line_pointer; |
252b5132 | 13603 | SKIP_WHITESPACE (); |
3882b010 | 13604 | if (ISDIGIT (*input_line_pointer) |
d9a62219 | 13605 | || *input_line_pointer == '-') |
874e8986 | 13606 | get_number (); |
252b5132 | 13607 | |
14949570 | 13608 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0) |
252b5132 RH |
13609 | as_warn (_(".ent or .aent not in text section.")); |
13610 | ||
13611 | if (!aent && cur_proc_ptr) | |
9a41af64 | 13612 | as_warn (_("missing .end")); |
252b5132 RH |
13613 | |
13614 | if (!aent) | |
13615 | { | |
7a621144 DJ |
13616 | /* This function needs its own .frame and .cprestore directives. */ |
13617 | mips_frame_reg_valid = 0; | |
13618 | mips_cprestore_valid = 0; | |
13619 | ||
252b5132 RH |
13620 | cur_proc_ptr = &cur_proc; |
13621 | memset (cur_proc_ptr, '\0', sizeof (procS)); | |
13622 | ||
9b2f1d35 | 13623 | cur_proc_ptr->func_sym = symbolP; |
252b5132 | 13624 | |
49309057 | 13625 | symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION; |
252b5132 | 13626 | |
f9419b05 | 13627 | ++numprocs; |
ecb4347a DJ |
13628 | |
13629 | if (debug_type == DEBUG_STABS) | |
13630 | stabs_generate_asm_func (S_GET_NAME (symbolP), | |
13631 | S_GET_NAME (symbolP)); | |
252b5132 RH |
13632 | } |
13633 | ||
13634 | demand_empty_rest_of_line (); | |
13635 | } | |
13636 | ||
13637 | /* The .frame directive. If the mdebug section is present (IRIX 5 native) | |
bdaaa2e1 | 13638 | then ecoff.c (ecoff_directive_frame) is used. For embedded targets, |
252b5132 | 13639 | s_mips_frame is used so that we can set the PDR information correctly. |
bdaaa2e1 | 13640 | We can't use the ecoff routines because they make reference to the ecoff |
252b5132 RH |
13641 | symbol table (in the mdebug section). */ |
13642 | ||
13643 | static void | |
17a2f251 | 13644 | s_mips_frame (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 13645 | { |
ecb4347a DJ |
13646 | #ifdef OBJ_ELF |
13647 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING) | |
13648 | { | |
13649 | long val; | |
252b5132 | 13650 | |
ecb4347a DJ |
13651 | if (cur_proc_ptr == (procS *) NULL) |
13652 | { | |
13653 | as_warn (_(".frame outside of .ent")); | |
13654 | demand_empty_rest_of_line (); | |
13655 | return; | |
13656 | } | |
252b5132 | 13657 | |
ecb4347a DJ |
13658 | cur_proc_ptr->frame_reg = tc_get_register (1); |
13659 | ||
13660 | SKIP_WHITESPACE (); | |
13661 | if (*input_line_pointer++ != ',' | |
13662 | || get_absolute_expression_and_terminator (&val) != ',') | |
13663 | { | |
13664 | as_warn (_("Bad .frame directive")); | |
13665 | --input_line_pointer; | |
13666 | demand_empty_rest_of_line (); | |
13667 | return; | |
13668 | } | |
252b5132 | 13669 | |
ecb4347a DJ |
13670 | cur_proc_ptr->frame_offset = val; |
13671 | cur_proc_ptr->pc_reg = tc_get_register (0); | |
252b5132 | 13672 | |
252b5132 | 13673 | demand_empty_rest_of_line (); |
252b5132 | 13674 | } |
ecb4347a DJ |
13675 | else |
13676 | #endif /* OBJ_ELF */ | |
13677 | s_ignore (ignore); | |
252b5132 RH |
13678 | } |
13679 | ||
bdaaa2e1 KH |
13680 | /* The .fmask and .mask directives. If the mdebug section is present |
13681 | (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For | |
252b5132 | 13682 | embedded targets, s_mips_mask is used so that we can set the PDR |
bdaaa2e1 | 13683 | information correctly. We can't use the ecoff routines because they |
252b5132 RH |
13684 | make reference to the ecoff symbol table (in the mdebug section). */ |
13685 | ||
13686 | static void | |
17a2f251 | 13687 | s_mips_mask (int reg_type) |
252b5132 | 13688 | { |
ecb4347a DJ |
13689 | #ifdef OBJ_ELF |
13690 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING) | |
252b5132 | 13691 | { |
ecb4347a | 13692 | long mask, off; |
252b5132 | 13693 | |
ecb4347a DJ |
13694 | if (cur_proc_ptr == (procS *) NULL) |
13695 | { | |
13696 | as_warn (_(".mask/.fmask outside of .ent")); | |
13697 | demand_empty_rest_of_line (); | |
13698 | return; | |
13699 | } | |
252b5132 | 13700 | |
ecb4347a DJ |
13701 | if (get_absolute_expression_and_terminator (&mask) != ',') |
13702 | { | |
13703 | as_warn (_("Bad .mask/.fmask directive")); | |
13704 | --input_line_pointer; | |
13705 | demand_empty_rest_of_line (); | |
13706 | return; | |
13707 | } | |
252b5132 | 13708 | |
ecb4347a DJ |
13709 | off = get_absolute_expression (); |
13710 | ||
13711 | if (reg_type == 'F') | |
13712 | { | |
13713 | cur_proc_ptr->fpreg_mask = mask; | |
13714 | cur_proc_ptr->fpreg_offset = off; | |
13715 | } | |
13716 | else | |
13717 | { | |
13718 | cur_proc_ptr->reg_mask = mask; | |
13719 | cur_proc_ptr->reg_offset = off; | |
13720 | } | |
13721 | ||
13722 | demand_empty_rest_of_line (); | |
252b5132 RH |
13723 | } |
13724 | else | |
ecb4347a DJ |
13725 | #endif /* OBJ_ELF */ |
13726 | s_ignore (reg_type); | |
252b5132 RH |
13727 | } |
13728 | ||
316f5878 RS |
13729 | /* A table describing all the processors gas knows about. Names are |
13730 | matched in the order listed. | |
e7af610e | 13731 | |
316f5878 RS |
13732 | To ease comparison, please keep this table in the same order as |
13733 | gcc's mips_cpu_info_table[]. */ | |
e972090a NC |
13734 | static const struct mips_cpu_info mips_cpu_info_table[] = |
13735 | { | |
316f5878 RS |
13736 | /* Entries for generic ISAs */ |
13737 | { "mips1", 1, ISA_MIPS1, CPU_R3000 }, | |
13738 | { "mips2", 1, ISA_MIPS2, CPU_R6000 }, | |
13739 | { "mips3", 1, ISA_MIPS3, CPU_R4000 }, | |
13740 | { "mips4", 1, ISA_MIPS4, CPU_R8000 }, | |
13741 | { "mips5", 1, ISA_MIPS5, CPU_MIPS5 }, | |
13742 | { "mips32", 1, ISA_MIPS32, CPU_MIPS32 }, | |
af7ee8bf | 13743 | { "mips32r2", 1, ISA_MIPS32R2, CPU_MIPS32R2 }, |
316f5878 | 13744 | { "mips64", 1, ISA_MIPS64, CPU_MIPS64 }, |
5f74bc13 | 13745 | { "mips64r2", 1, ISA_MIPS64R2, CPU_MIPS64R2 }, |
316f5878 RS |
13746 | |
13747 | /* MIPS I */ | |
13748 | { "r3000", 0, ISA_MIPS1, CPU_R3000 }, | |
13749 | { "r2000", 0, ISA_MIPS1, CPU_R3000 }, | |
13750 | { "r3900", 0, ISA_MIPS1, CPU_R3900 }, | |
13751 | ||
13752 | /* MIPS II */ | |
13753 | { "r6000", 0, ISA_MIPS2, CPU_R6000 }, | |
13754 | ||
13755 | /* MIPS III */ | |
13756 | { "r4000", 0, ISA_MIPS3, CPU_R4000 }, | |
13757 | { "r4010", 0, ISA_MIPS2, CPU_R4010 }, | |
13758 | { "vr4100", 0, ISA_MIPS3, CPU_VR4100 }, | |
13759 | { "vr4111", 0, ISA_MIPS3, CPU_R4111 }, | |
60b63b72 RS |
13760 | { "vr4120", 0, ISA_MIPS3, CPU_VR4120 }, |
13761 | { "vr4130", 0, ISA_MIPS3, CPU_VR4120 }, | |
13762 | { "vr4181", 0, ISA_MIPS3, CPU_R4111 }, | |
316f5878 RS |
13763 | { "vr4300", 0, ISA_MIPS3, CPU_R4300 }, |
13764 | { "r4400", 0, ISA_MIPS3, CPU_R4400 }, | |
13765 | { "r4600", 0, ISA_MIPS3, CPU_R4600 }, | |
13766 | { "orion", 0, ISA_MIPS3, CPU_R4600 }, | |
13767 | { "r4650", 0, ISA_MIPS3, CPU_R4650 }, | |
13768 | ||
13769 | /* MIPS IV */ | |
13770 | { "r8000", 0, ISA_MIPS4, CPU_R8000 }, | |
13771 | { "r10000", 0, ISA_MIPS4, CPU_R10000 }, | |
13772 | { "r12000", 0, ISA_MIPS4, CPU_R12000 }, | |
13773 | { "vr5000", 0, ISA_MIPS4, CPU_R5000 }, | |
60b63b72 RS |
13774 | { "vr5400", 0, ISA_MIPS4, CPU_VR5400 }, |
13775 | { "vr5500", 0, ISA_MIPS4, CPU_VR5500 }, | |
316f5878 RS |
13776 | { "rm5200", 0, ISA_MIPS4, CPU_R5000 }, |
13777 | { "rm5230", 0, ISA_MIPS4, CPU_R5000 }, | |
13778 | { "rm5231", 0, ISA_MIPS4, CPU_R5000 }, | |
13779 | { "rm5261", 0, ISA_MIPS4, CPU_R5000 }, | |
13780 | { "rm5721", 0, ISA_MIPS4, CPU_R5000 }, | |
5a7ea749 | 13781 | { "rm7000", 0, ISA_MIPS4, CPU_RM7000 }, |
9a92f48d | 13782 | { "rm9000", 0, ISA_MIPS4, CPU_RM9000 }, |
316f5878 RS |
13783 | |
13784 | /* MIPS 32 */ | |
fef14a42 | 13785 | { "4kc", 0, ISA_MIPS32, CPU_MIPS32 }, |
316f5878 RS |
13786 | { "4km", 0, ISA_MIPS32, CPU_MIPS32 }, |
13787 | { "4kp", 0, ISA_MIPS32, CPU_MIPS32 }, | |
e7af610e | 13788 | |
316f5878 RS |
13789 | /* MIPS 64 */ |
13790 | { "5kc", 0, ISA_MIPS64, CPU_MIPS64 }, | |
13791 | { "20kc", 0, ISA_MIPS64, CPU_MIPS64 }, | |
e7af610e | 13792 | |
c7a23324 | 13793 | /* Broadcom SB-1 CPU core */ |
316f5878 | 13794 | { "sb1", 0, ISA_MIPS64, CPU_SB1 }, |
e7af610e | 13795 | |
316f5878 RS |
13796 | /* End marker */ |
13797 | { NULL, 0, 0, 0 } | |
13798 | }; | |
e7af610e | 13799 | |
84ea6cf2 | 13800 | |
316f5878 RS |
13801 | /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL |
13802 | with a final "000" replaced by "k". Ignore case. | |
e7af610e | 13803 | |
316f5878 | 13804 | Note: this function is shared between GCC and GAS. */ |
c6c98b38 | 13805 | |
b34976b6 | 13806 | static bfd_boolean |
17a2f251 | 13807 | mips_strict_matching_cpu_name_p (const char *canonical, const char *given) |
316f5878 RS |
13808 | { |
13809 | while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical)) | |
13810 | given++, canonical++; | |
13811 | ||
13812 | return ((*given == 0 && *canonical == 0) | |
13813 | || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0)); | |
13814 | } | |
13815 | ||
13816 | ||
13817 | /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied | |
13818 | CPU name. We've traditionally allowed a lot of variation here. | |
13819 | ||
13820 | Note: this function is shared between GCC and GAS. */ | |
13821 | ||
b34976b6 | 13822 | static bfd_boolean |
17a2f251 | 13823 | mips_matching_cpu_name_p (const char *canonical, const char *given) |
316f5878 RS |
13824 | { |
13825 | /* First see if the name matches exactly, or with a final "000" | |
13826 | turned into "k". */ | |
13827 | if (mips_strict_matching_cpu_name_p (canonical, given)) | |
b34976b6 | 13828 | return TRUE; |
316f5878 RS |
13829 | |
13830 | /* If not, try comparing based on numerical designation alone. | |
13831 | See if GIVEN is an unadorned number, or 'r' followed by a number. */ | |
13832 | if (TOLOWER (*given) == 'r') | |
13833 | given++; | |
13834 | if (!ISDIGIT (*given)) | |
b34976b6 | 13835 | return FALSE; |
316f5878 RS |
13836 | |
13837 | /* Skip over some well-known prefixes in the canonical name, | |
13838 | hoping to find a number there too. */ | |
13839 | if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r') | |
13840 | canonical += 2; | |
13841 | else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm') | |
13842 | canonical += 2; | |
13843 | else if (TOLOWER (canonical[0]) == 'r') | |
13844 | canonical += 1; | |
13845 | ||
13846 | return mips_strict_matching_cpu_name_p (canonical, given); | |
13847 | } | |
13848 | ||
13849 | ||
13850 | /* Parse an option that takes the name of a processor as its argument. | |
13851 | OPTION is the name of the option and CPU_STRING is the argument. | |
13852 | Return the corresponding processor enumeration if the CPU_STRING is | |
13853 | recognized, otherwise report an error and return null. | |
13854 | ||
13855 | A similar function exists in GCC. */ | |
e7af610e NC |
13856 | |
13857 | static const struct mips_cpu_info * | |
17a2f251 | 13858 | mips_parse_cpu (const char *option, const char *cpu_string) |
e7af610e | 13859 | { |
316f5878 | 13860 | const struct mips_cpu_info *p; |
e7af610e | 13861 | |
316f5878 RS |
13862 | /* 'from-abi' selects the most compatible architecture for the given |
13863 | ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the | |
13864 | EABIs, we have to decide whether we're using the 32-bit or 64-bit | |
13865 | version. Look first at the -mgp options, if given, otherwise base | |
13866 | the choice on MIPS_DEFAULT_64BIT. | |
e7af610e | 13867 | |
316f5878 RS |
13868 | Treat NO_ABI like the EABIs. One reason to do this is that the |
13869 | plain 'mips' and 'mips64' configs have 'from-abi' as their default | |
13870 | architecture. This code picks MIPS I for 'mips' and MIPS III for | |
13871 | 'mips64', just as we did in the days before 'from-abi'. */ | |
13872 | if (strcasecmp (cpu_string, "from-abi") == 0) | |
13873 | { | |
13874 | if (ABI_NEEDS_32BIT_REGS (mips_abi)) | |
13875 | return mips_cpu_info_from_isa (ISA_MIPS1); | |
13876 | ||
13877 | if (ABI_NEEDS_64BIT_REGS (mips_abi)) | |
13878 | return mips_cpu_info_from_isa (ISA_MIPS3); | |
13879 | ||
13880 | if (file_mips_gp32 >= 0) | |
13881 | return mips_cpu_info_from_isa (file_mips_gp32 ? ISA_MIPS1 : ISA_MIPS3); | |
13882 | ||
13883 | return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT | |
13884 | ? ISA_MIPS3 | |
13885 | : ISA_MIPS1); | |
13886 | } | |
13887 | ||
13888 | /* 'default' has traditionally been a no-op. Probably not very useful. */ | |
13889 | if (strcasecmp (cpu_string, "default") == 0) | |
13890 | return 0; | |
13891 | ||
13892 | for (p = mips_cpu_info_table; p->name != 0; p++) | |
13893 | if (mips_matching_cpu_name_p (p->name, cpu_string)) | |
13894 | return p; | |
13895 | ||
13896 | as_bad ("Bad value (%s) for %s", cpu_string, option); | |
13897 | return 0; | |
e7af610e NC |
13898 | } |
13899 | ||
316f5878 RS |
13900 | /* Return the canonical processor information for ISA (a member of the |
13901 | ISA_MIPS* enumeration). */ | |
13902 | ||
e7af610e | 13903 | static const struct mips_cpu_info * |
17a2f251 | 13904 | mips_cpu_info_from_isa (int isa) |
e7af610e NC |
13905 | { |
13906 | int i; | |
13907 | ||
13908 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
13909 | if (mips_cpu_info_table[i].is_isa | |
316f5878 | 13910 | && isa == mips_cpu_info_table[i].isa) |
e7af610e NC |
13911 | return (&mips_cpu_info_table[i]); |
13912 | ||
e972090a | 13913 | return NULL; |
e7af610e | 13914 | } |
fef14a42 TS |
13915 | |
13916 | static const struct mips_cpu_info * | |
17a2f251 | 13917 | mips_cpu_info_from_arch (int arch) |
fef14a42 TS |
13918 | { |
13919 | int i; | |
13920 | ||
13921 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
13922 | if (arch == mips_cpu_info_table[i].cpu) | |
13923 | return (&mips_cpu_info_table[i]); | |
13924 | ||
13925 | return NULL; | |
13926 | } | |
316f5878 RS |
13927 | \f |
13928 | static void | |
17a2f251 | 13929 | show (FILE *stream, const char *string, int *col_p, int *first_p) |
316f5878 RS |
13930 | { |
13931 | if (*first_p) | |
13932 | { | |
13933 | fprintf (stream, "%24s", ""); | |
13934 | *col_p = 24; | |
13935 | } | |
13936 | else | |
13937 | { | |
13938 | fprintf (stream, ", "); | |
13939 | *col_p += 2; | |
13940 | } | |
e7af610e | 13941 | |
316f5878 RS |
13942 | if (*col_p + strlen (string) > 72) |
13943 | { | |
13944 | fprintf (stream, "\n%24s", ""); | |
13945 | *col_p = 24; | |
13946 | } | |
13947 | ||
13948 | fprintf (stream, "%s", string); | |
13949 | *col_p += strlen (string); | |
13950 | ||
13951 | *first_p = 0; | |
13952 | } | |
13953 | ||
13954 | void | |
17a2f251 | 13955 | md_show_usage (FILE *stream) |
e7af610e | 13956 | { |
316f5878 RS |
13957 | int column, first; |
13958 | size_t i; | |
13959 | ||
13960 | fprintf (stream, _("\ | |
13961 | MIPS options:\n\ | |
316f5878 RS |
13962 | -EB generate big endian output\n\ |
13963 | -EL generate little endian output\n\ | |
13964 | -g, -g2 do not remove unneeded NOPs or swap branches\n\ | |
13965 | -G NUM allow referencing objects up to NUM bytes\n\ | |
13966 | implicitly with the gp register [default 8]\n")); | |
13967 | fprintf (stream, _("\ | |
13968 | -mips1 generate MIPS ISA I instructions\n\ | |
13969 | -mips2 generate MIPS ISA II instructions\n\ | |
13970 | -mips3 generate MIPS ISA III instructions\n\ | |
13971 | -mips4 generate MIPS ISA IV instructions\n\ | |
13972 | -mips5 generate MIPS ISA V instructions\n\ | |
13973 | -mips32 generate MIPS32 ISA instructions\n\ | |
af7ee8bf | 13974 | -mips32r2 generate MIPS32 release 2 ISA instructions\n\ |
316f5878 | 13975 | -mips64 generate MIPS64 ISA instructions\n\ |
5f74bc13 | 13976 | -mips64r2 generate MIPS64 release 2 ISA instructions\n\ |
316f5878 RS |
13977 | -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n")); |
13978 | ||
13979 | first = 1; | |
e7af610e NC |
13980 | |
13981 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
316f5878 RS |
13982 | show (stream, mips_cpu_info_table[i].name, &column, &first); |
13983 | show (stream, "from-abi", &column, &first); | |
13984 | fputc ('\n', stream); | |
e7af610e | 13985 | |
316f5878 RS |
13986 | fprintf (stream, _("\ |
13987 | -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\ | |
13988 | -no-mCPU don't generate code specific to CPU.\n\ | |
13989 | For -mCPU and -no-mCPU, CPU must be one of:\n")); | |
13990 | ||
13991 | first = 1; | |
13992 | ||
13993 | show (stream, "3900", &column, &first); | |
13994 | show (stream, "4010", &column, &first); | |
13995 | show (stream, "4100", &column, &first); | |
13996 | show (stream, "4650", &column, &first); | |
13997 | fputc ('\n', stream); | |
13998 | ||
13999 | fprintf (stream, _("\ | |
14000 | -mips16 generate mips16 instructions\n\ | |
14001 | -no-mips16 do not generate mips16 instructions\n")); | |
14002 | fprintf (stream, _("\ | |
d766e8ec | 14003 | -mfix-vr4120 work around certain VR4120 errata\n\ |
316f5878 RS |
14004 | -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\ |
14005 | -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\ | |
aed1a261 RS |
14006 | -mno-shared optimize output for executables\n\ |
14007 | -msym32 assume all symbols have 32-bit values\n\ | |
316f5878 RS |
14008 | -O0 remove unneeded NOPs, do not swap branches\n\ |
14009 | -O remove unneeded NOPs and swap branches\n\ | |
316f5878 RS |
14010 | --[no-]construct-floats [dis]allow floating point values to be constructed\n\ |
14011 | --trap, --no-break trap exception on div by 0 and mult overflow\n\ | |
14012 | --break, --no-trap break exception on div by 0 and mult overflow\n")); | |
14013 | #ifdef OBJ_ELF | |
14014 | fprintf (stream, _("\ | |
14015 | -KPIC, -call_shared generate SVR4 position independent code\n\ | |
14016 | -non_shared do not generate position independent code\n\ | |
14017 | -xgot assume a 32 bit GOT\n\ | |
dcd410fe | 14018 | -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\ |
bbe506e8 TS |
14019 | -mshared, -mno-shared disable/enable .cpload optimization for\n\ |
14020 | non-shared code\n\ | |
316f5878 RS |
14021 | -mabi=ABI create ABI conformant object file for:\n")); |
14022 | ||
14023 | first = 1; | |
14024 | ||
14025 | show (stream, "32", &column, &first); | |
14026 | show (stream, "o64", &column, &first); | |
14027 | show (stream, "n32", &column, &first); | |
14028 | show (stream, "64", &column, &first); | |
14029 | show (stream, "eabi", &column, &first); | |
14030 | ||
14031 | fputc ('\n', stream); | |
14032 | ||
14033 | fprintf (stream, _("\ | |
14034 | -32 create o32 ABI object file (default)\n\ | |
14035 | -n32 create n32 ABI object file\n\ | |
14036 | -64 create 64 ABI object file\n")); | |
14037 | #endif | |
e7af610e | 14038 | } |
14e777e0 KB |
14039 | |
14040 | enum dwarf2_format | |
17a2f251 | 14041 | mips_dwarf2_format (void) |
14e777e0 KB |
14042 | { |
14043 | if (mips_abi == N64_ABI) | |
1de5b6a1 AO |
14044 | { |
14045 | #ifdef TE_IRIX | |
14046 | return dwarf2_format_64bit_irix; | |
14047 | #else | |
14048 | return dwarf2_format_64bit; | |
14049 | #endif | |
14050 | } | |
14e777e0 KB |
14051 | else |
14052 | return dwarf2_format_32bit; | |
14053 | } | |
73369e65 EC |
14054 | |
14055 | int | |
14056 | mips_dwarf2_addr_size (void) | |
14057 | { | |
14058 | if (mips_abi == N64_ABI) | |
14059 | return 8; | |
73369e65 EC |
14060 | else |
14061 | return 4; | |
14062 | } |