Commit | Line | Data |
---|---|---|
252b5132 | 1 | /* tc-mips.c -- assemble code for a MIPS chip. |
81912461 | 2 | Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, |
f17c130b | 3 | 2003, 2004, 2005 Free Software Foundation, Inc. |
252b5132 RH |
4 | Contributed by the OSF and Ralph Campbell. |
5 | Written by Keith Knowles and Ralph Campbell, working independently. | |
6 | Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus | |
7 | Support. | |
8 | ||
9 | This file is part of GAS. | |
10 | ||
11 | GAS is free software; you can redistribute it and/or modify | |
12 | it under the terms of the GNU General Public License as published by | |
13 | the Free Software Foundation; either version 2, or (at your option) | |
14 | any later version. | |
15 | ||
16 | GAS is distributed in the hope that it will be useful, | |
17 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | GNU General Public License for more details. | |
20 | ||
21 | You should have received a copy of the GNU General Public License | |
22 | along with GAS; see the file COPYING. If not, write to the Free | |
4b4da160 NC |
23 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
24 | 02110-1301, USA. */ | |
252b5132 RH |
25 | |
26 | #include "as.h" | |
27 | #include "config.h" | |
28 | #include "subsegs.h" | |
3882b010 | 29 | #include "safe-ctype.h" |
252b5132 | 30 | |
252b5132 | 31 | #include <stdarg.h> |
252b5132 RH |
32 | |
33 | #include "opcode/mips.h" | |
34 | #include "itbl-ops.h" | |
c5dd6aab | 35 | #include "dwarf2dbg.h" |
5862107c | 36 | #include "dw2gencfi.h" |
252b5132 RH |
37 | |
38 | #ifdef DEBUG | |
39 | #define DBG(x) printf x | |
40 | #else | |
41 | #define DBG(x) | |
42 | #endif | |
43 | ||
44 | #ifdef OBJ_MAYBE_ELF | |
45 | /* Clean up namespace so we can include obj-elf.h too. */ | |
17a2f251 TS |
46 | static int mips_output_flavor (void); |
47 | static int mips_output_flavor (void) { return OUTPUT_FLAVOR; } | |
252b5132 RH |
48 | #undef OBJ_PROCESS_STAB |
49 | #undef OUTPUT_FLAVOR | |
50 | #undef S_GET_ALIGN | |
51 | #undef S_GET_SIZE | |
52 | #undef S_SET_ALIGN | |
53 | #undef S_SET_SIZE | |
252b5132 RH |
54 | #undef obj_frob_file |
55 | #undef obj_frob_file_after_relocs | |
56 | #undef obj_frob_symbol | |
57 | #undef obj_pop_insert | |
58 | #undef obj_sec_sym_ok_for_reloc | |
59 | #undef OBJ_COPY_SYMBOL_ATTRIBUTES | |
60 | ||
61 | #include "obj-elf.h" | |
62 | /* Fix any of them that we actually care about. */ | |
63 | #undef OUTPUT_FLAVOR | |
64 | #define OUTPUT_FLAVOR mips_output_flavor() | |
65 | #endif | |
66 | ||
67 | #if defined (OBJ_ELF) | |
68 | #include "elf/mips.h" | |
69 | #endif | |
70 | ||
71 | #ifndef ECOFF_DEBUGGING | |
72 | #define NO_ECOFF_DEBUGGING | |
73 | #define ECOFF_DEBUGGING 0 | |
74 | #endif | |
75 | ||
ecb4347a DJ |
76 | int mips_flag_mdebug = -1; |
77 | ||
dcd410fe RO |
78 | /* Control generation of .pdr sections. Off by default on IRIX: the native |
79 | linker doesn't know about and discards them, but relocations against them | |
80 | remain, leading to rld crashes. */ | |
81 | #ifdef TE_IRIX | |
82 | int mips_flag_pdr = FALSE; | |
83 | #else | |
84 | int mips_flag_pdr = TRUE; | |
85 | #endif | |
86 | ||
252b5132 RH |
87 | #include "ecoff.h" |
88 | ||
89 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
90 | static char *mips_regmask_frag; | |
91 | #endif | |
92 | ||
85b51719 | 93 | #define ZERO 0 |
252b5132 RH |
94 | #define AT 1 |
95 | #define TREG 24 | |
96 | #define PIC_CALL_REG 25 | |
97 | #define KT0 26 | |
98 | #define KT1 27 | |
99 | #define GP 28 | |
100 | #define SP 29 | |
101 | #define FP 30 | |
102 | #define RA 31 | |
103 | ||
104 | #define ILLEGAL_REG (32) | |
105 | ||
106 | /* Allow override of standard little-endian ECOFF format. */ | |
107 | ||
108 | #ifndef ECOFF_LITTLE_FORMAT | |
109 | #define ECOFF_LITTLE_FORMAT "ecoff-littlemips" | |
110 | #endif | |
111 | ||
112 | extern int target_big_endian; | |
113 | ||
252b5132 | 114 | /* The name of the readonly data section. */ |
4d0d148d | 115 | #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_ecoff_flavour \ |
252b5132 | 116 | ? ".rdata" \ |
056350c6 NC |
117 | : OUTPUT_FLAVOR == bfd_target_coff_flavour \ |
118 | ? ".rdata" \ | |
252b5132 RH |
119 | : OUTPUT_FLAVOR == bfd_target_elf_flavour \ |
120 | ? ".rodata" \ | |
121 | : (abort (), "")) | |
122 | ||
47e39b9d RS |
123 | /* Information about an instruction, including its format, operands |
124 | and fixups. */ | |
125 | struct mips_cl_insn | |
126 | { | |
127 | /* The opcode's entry in mips_opcodes or mips16_opcodes. */ | |
128 | const struct mips_opcode *insn_mo; | |
129 | ||
130 | /* True if this is a mips16 instruction and if we want the extended | |
131 | form of INSN_MO. */ | |
132 | bfd_boolean use_extend; | |
133 | ||
134 | /* The 16-bit extension instruction to use when USE_EXTEND is true. */ | |
135 | unsigned short extend; | |
136 | ||
137 | /* The 16-bit or 32-bit bitstring of the instruction itself. This is | |
138 | a copy of INSN_MO->match with the operands filled in. */ | |
139 | unsigned long insn_opcode; | |
140 | ||
141 | /* The frag that contains the instruction. */ | |
142 | struct frag *frag; | |
143 | ||
144 | /* The offset into FRAG of the first instruction byte. */ | |
145 | long where; | |
146 | ||
147 | /* The relocs associated with the instruction, if any. */ | |
148 | fixS *fixp[3]; | |
149 | ||
a38419a5 RS |
150 | /* True if this entry cannot be moved from its current position. */ |
151 | unsigned int fixed_p : 1; | |
47e39b9d | 152 | |
708587a4 | 153 | /* True if this instruction occurred in a .set noreorder block. */ |
47e39b9d RS |
154 | unsigned int noreorder_p : 1; |
155 | ||
2fa15973 RS |
156 | /* True for mips16 instructions that jump to an absolute address. */ |
157 | unsigned int mips16_absolute_jump_p : 1; | |
47e39b9d RS |
158 | }; |
159 | ||
a325df1d TS |
160 | /* The ABI to use. */ |
161 | enum mips_abi_level | |
162 | { | |
163 | NO_ABI = 0, | |
164 | O32_ABI, | |
165 | O64_ABI, | |
166 | N32_ABI, | |
167 | N64_ABI, | |
168 | EABI_ABI | |
169 | }; | |
170 | ||
171 | /* MIPS ABI we are using for this output file. */ | |
316f5878 | 172 | static enum mips_abi_level mips_abi = NO_ABI; |
a325df1d | 173 | |
143d77c5 EC |
174 | /* Whether or not we have code that can call pic code. */ |
175 | int mips_abicalls = FALSE; | |
176 | ||
aa6975fb ILT |
177 | /* Whether or not we have code which can be put into a shared |
178 | library. */ | |
179 | static bfd_boolean mips_in_shared = TRUE; | |
180 | ||
252b5132 RH |
181 | /* This is the set of options which may be modified by the .set |
182 | pseudo-op. We use a struct so that .set push and .set pop are more | |
183 | reliable. */ | |
184 | ||
e972090a NC |
185 | struct mips_set_options |
186 | { | |
252b5132 RH |
187 | /* MIPS ISA (Instruction Set Architecture) level. This is set to -1 |
188 | if it has not been initialized. Changed by `.set mipsN', and the | |
189 | -mipsN command line option, and the default CPU. */ | |
190 | int isa; | |
1f25f5d3 CD |
191 | /* Enabled Application Specific Extensions (ASEs). These are set to -1 |
192 | if they have not been initialized. Changed by `.set <asename>', by | |
193 | command line options, and based on the default architecture. */ | |
194 | int ase_mips3d; | |
deec1734 | 195 | int ase_mdmx; |
e16bfa71 | 196 | int ase_smartmips; |
74cd071d | 197 | int ase_dsp; |
ef2e4d86 | 198 | int ase_mt; |
252b5132 RH |
199 | /* Whether we are assembling for the mips16 processor. 0 if we are |
200 | not, 1 if we are, and -1 if the value has not been initialized. | |
201 | Changed by `.set mips16' and `.set nomips16', and the -mips16 and | |
202 | -nomips16 command line options, and the default CPU. */ | |
203 | int mips16; | |
204 | /* Non-zero if we should not reorder instructions. Changed by `.set | |
205 | reorder' and `.set noreorder'. */ | |
206 | int noreorder; | |
207 | /* Non-zero if we should not permit the $at ($1) register to be used | |
208 | in instructions. Changed by `.set at' and `.set noat'. */ | |
209 | int noat; | |
210 | /* Non-zero if we should warn when a macro instruction expands into | |
211 | more than one machine instruction. Changed by `.set nomacro' and | |
212 | `.set macro'. */ | |
213 | int warn_about_macros; | |
214 | /* Non-zero if we should not move instructions. Changed by `.set | |
215 | move', `.set volatile', `.set nomove', and `.set novolatile'. */ | |
216 | int nomove; | |
217 | /* Non-zero if we should not optimize branches by moving the target | |
218 | of the branch into the delay slot. Actually, we don't perform | |
219 | this optimization anyhow. Changed by `.set bopt' and `.set | |
220 | nobopt'. */ | |
221 | int nobopt; | |
222 | /* Non-zero if we should not autoextend mips16 instructions. | |
223 | Changed by `.set autoextend' and `.set noautoextend'. */ | |
224 | int noautoextend; | |
a325df1d TS |
225 | /* Restrict general purpose registers and floating point registers |
226 | to 32 bit. This is initially determined when -mgp32 or -mfp32 | |
227 | is passed but can changed if the assembler code uses .set mipsN. */ | |
228 | int gp32; | |
229 | int fp32; | |
fef14a42 TS |
230 | /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march |
231 | command line option, and the default CPU. */ | |
232 | int arch; | |
aed1a261 RS |
233 | /* True if ".set sym32" is in effect. */ |
234 | bfd_boolean sym32; | |
252b5132 RH |
235 | }; |
236 | ||
a325df1d | 237 | /* True if -mgp32 was passed. */ |
a8e8e863 | 238 | static int file_mips_gp32 = -1; |
a325df1d TS |
239 | |
240 | /* True if -mfp32 was passed. */ | |
a8e8e863 | 241 | static int file_mips_fp32 = -1; |
a325df1d | 242 | |
252b5132 | 243 | /* This is the struct we use to hold the current set of options. Note |
a4672219 | 244 | that we must set the isa field to ISA_UNKNOWN and the ASE fields to |
e7af610e | 245 | -1 to indicate that they have not been initialized. */ |
252b5132 | 246 | |
e972090a NC |
247 | static struct mips_set_options mips_opts = |
248 | { | |
e16bfa71 | 249 | ISA_UNKNOWN, -1, -1, 0, -1, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0, CPU_UNKNOWN, FALSE |
e7af610e | 250 | }; |
252b5132 RH |
251 | |
252 | /* These variables are filled in with the masks of registers used. | |
253 | The object format code reads them and puts them in the appropriate | |
254 | place. */ | |
255 | unsigned long mips_gprmask; | |
256 | unsigned long mips_cprmask[4]; | |
257 | ||
258 | /* MIPS ISA we are using for this output file. */ | |
e7af610e | 259 | static int file_mips_isa = ISA_UNKNOWN; |
252b5132 | 260 | |
a4672219 TS |
261 | /* True if -mips16 was passed or implied by arguments passed on the |
262 | command line (e.g., by -march). */ | |
263 | static int file_ase_mips16; | |
264 | ||
1f25f5d3 CD |
265 | /* True if -mips3d was passed or implied by arguments passed on the |
266 | command line (e.g., by -march). */ | |
267 | static int file_ase_mips3d; | |
268 | ||
deec1734 CD |
269 | /* True if -mdmx was passed or implied by arguments passed on the |
270 | command line (e.g., by -march). */ | |
271 | static int file_ase_mdmx; | |
272 | ||
e16bfa71 TS |
273 | /* True if -msmartmips was passed or implied by arguments passed on the |
274 | command line (e.g., by -march). */ | |
275 | static int file_ase_smartmips; | |
276 | ||
277 | #define ISA_SUPPORT_SMARTMIPS (mips_opts.isa == ISA_MIPS32 \ | |
278 | || mips_opts.isa == ISA_MIPS32R2) | |
279 | ||
74cd071d CF |
280 | /* True if -mdsp was passed or implied by arguments passed on the |
281 | command line (e.g., by -march). */ | |
282 | static int file_ase_dsp; | |
283 | ||
ef2e4d86 CF |
284 | /* True if -mmt was passed or implied by arguments passed on the |
285 | command line (e.g., by -march). */ | |
286 | static int file_ase_mt; | |
287 | ||
ec68c924 | 288 | /* The argument of the -march= flag. The architecture we are assembling. */ |
fef14a42 | 289 | static int file_mips_arch = CPU_UNKNOWN; |
316f5878 | 290 | static const char *mips_arch_string; |
ec68c924 EC |
291 | |
292 | /* The argument of the -mtune= flag. The architecture for which we | |
293 | are optimizing. */ | |
294 | static int mips_tune = CPU_UNKNOWN; | |
316f5878 | 295 | static const char *mips_tune_string; |
ec68c924 | 296 | |
316f5878 | 297 | /* True when generating 32-bit code for a 64-bit processor. */ |
252b5132 RH |
298 | static int mips_32bitmode = 0; |
299 | ||
316f5878 RS |
300 | /* True if the given ABI requires 32-bit registers. */ |
301 | #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI) | |
302 | ||
303 | /* Likewise 64-bit registers. */ | |
304 | #define ABI_NEEDS_64BIT_REGS(ABI) \ | |
305 | ((ABI) == N32_ABI \ | |
306 | || (ABI) == N64_ABI \ | |
307 | || (ABI) == O64_ABI) | |
308 | ||
bdaaa2e1 | 309 | /* Return true if ISA supports 64 bit gp register instructions. */ |
9ce8a5dd | 310 | #define ISA_HAS_64BIT_REGS(ISA) ( \ |
e7af610e NC |
311 | (ISA) == ISA_MIPS3 \ |
312 | || (ISA) == ISA_MIPS4 \ | |
84ea6cf2 | 313 | || (ISA) == ISA_MIPS5 \ |
d1cf510e | 314 | || (ISA) == ISA_MIPS64 \ |
5f74bc13 | 315 | || (ISA) == ISA_MIPS64R2 \ |
9ce8a5dd GRK |
316 | ) |
317 | ||
af7ee8bf CD |
318 | /* Return true if ISA supports 64-bit right rotate (dror et al.) |
319 | instructions. */ | |
320 | #define ISA_HAS_DROR(ISA) ( \ | |
5f74bc13 | 321 | (ISA) == ISA_MIPS64R2 \ |
af7ee8bf CD |
322 | ) |
323 | ||
324 | /* Return true if ISA supports 32-bit right rotate (ror et al.) | |
325 | instructions. */ | |
326 | #define ISA_HAS_ROR(ISA) ( \ | |
327 | (ISA) == ISA_MIPS32R2 \ | |
5f74bc13 | 328 | || (ISA) == ISA_MIPS64R2 \ |
e16bfa71 | 329 | || mips_opts.ase_smartmips \ |
af7ee8bf CD |
330 | ) |
331 | ||
e013f690 | 332 | #define HAVE_32BIT_GPRS \ |
316f5878 | 333 | (mips_opts.gp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
ca4e0257 | 334 | |
e013f690 | 335 | #define HAVE_32BIT_FPRS \ |
316f5878 | 336 | (mips_opts.fp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
ca4e0257 RS |
337 | |
338 | #define HAVE_64BIT_GPRS (! HAVE_32BIT_GPRS) | |
339 | #define HAVE_64BIT_FPRS (! HAVE_32BIT_FPRS) | |
340 | ||
316f5878 | 341 | #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI) |
e013f690 | 342 | |
316f5878 | 343 | #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI) |
e013f690 | 344 | |
3b91255e RS |
345 | /* True if relocations are stored in-place. */ |
346 | #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI) | |
347 | ||
aed1a261 RS |
348 | /* The ABI-derived address size. */ |
349 | #define HAVE_64BIT_ADDRESSES \ | |
350 | (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI)) | |
351 | #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES) | |
e013f690 | 352 | |
aed1a261 RS |
353 | /* The size of symbolic constants (i.e., expressions of the form |
354 | "SYMBOL" or "SYMBOL + OFFSET"). */ | |
355 | #define HAVE_32BIT_SYMBOLS \ | |
356 | (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32) | |
357 | #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS) | |
ca4e0257 | 358 | |
b7c7d6c1 TS |
359 | /* Addresses are loaded in different ways, depending on the address size |
360 | in use. The n32 ABI Documentation also mandates the use of additions | |
361 | with overflow checking, but existing implementations don't follow it. */ | |
f899b4b8 | 362 | #define ADDRESS_ADD_INSN \ |
b7c7d6c1 | 363 | (HAVE_32BIT_ADDRESSES ? "addu" : "daddu") |
f899b4b8 TS |
364 | |
365 | #define ADDRESS_ADDI_INSN \ | |
b7c7d6c1 | 366 | (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu") |
f899b4b8 TS |
367 | |
368 | #define ADDRESS_LOAD_INSN \ | |
369 | (HAVE_32BIT_ADDRESSES ? "lw" : "ld") | |
370 | ||
371 | #define ADDRESS_STORE_INSN \ | |
372 | (HAVE_32BIT_ADDRESSES ? "sw" : "sd") | |
373 | ||
a4672219 | 374 | /* Return true if the given CPU supports the MIPS16 ASE. */ |
3396de36 TS |
375 | #define CPU_HAS_MIPS16(cpu) \ |
376 | (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \ | |
377 | || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0) | |
a4672219 | 378 | |
1f25f5d3 CD |
379 | /* Return true if the given CPU supports the MIPS3D ASE. */ |
380 | #define CPU_HAS_MIPS3D(cpu) ((cpu) == CPU_SB1 \ | |
381 | ) | |
382 | ||
deec1734 | 383 | /* Return true if the given CPU supports the MDMX ASE. */ |
b34976b6 | 384 | #define CPU_HAS_MDMX(cpu) (FALSE \ |
deec1734 CD |
385 | ) |
386 | ||
74cd071d CF |
387 | /* Return true if the given CPU supports the DSP ASE. */ |
388 | #define CPU_HAS_DSP(cpu) (FALSE \ | |
389 | ) | |
390 | ||
ef2e4d86 CF |
391 | /* Return true if the given CPU supports the MT ASE. */ |
392 | #define CPU_HAS_MT(cpu) (FALSE \ | |
393 | ) | |
394 | ||
60b63b72 RS |
395 | /* True if CPU has a dror instruction. */ |
396 | #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500) | |
397 | ||
398 | /* True if CPU has a ror instruction. */ | |
399 | #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU) | |
400 | ||
c8978940 CD |
401 | /* True if mflo and mfhi can be immediately followed by instructions |
402 | which write to the HI and LO registers. | |
403 | ||
404 | According to MIPS specifications, MIPS ISAs I, II, and III need | |
405 | (at least) two instructions between the reads of HI/LO and | |
406 | instructions which write them, and later ISAs do not. Contradicting | |
407 | the MIPS specifications, some MIPS IV processor user manuals (e.g. | |
408 | the UM for the NEC Vr5000) document needing the instructions between | |
409 | HI/LO reads and writes, as well. Therefore, we declare only MIPS32, | |
410 | MIPS64 and later ISAs to have the interlocks, plus any specific | |
411 | earlier-ISA CPUs for which CPU documentation declares that the | |
412 | instructions are really interlocked. */ | |
413 | #define hilo_interlocks \ | |
414 | (mips_opts.isa == ISA_MIPS32 \ | |
415 | || mips_opts.isa == ISA_MIPS32R2 \ | |
416 | || mips_opts.isa == ISA_MIPS64 \ | |
417 | || mips_opts.isa == ISA_MIPS64R2 \ | |
418 | || mips_opts.arch == CPU_R4010 \ | |
419 | || mips_opts.arch == CPU_R10000 \ | |
420 | || mips_opts.arch == CPU_R12000 \ | |
421 | || mips_opts.arch == CPU_RM7000 \ | |
c8978940 CD |
422 | || mips_opts.arch == CPU_VR5500 \ |
423 | ) | |
252b5132 RH |
424 | |
425 | /* Whether the processor uses hardware interlocks to protect reads | |
81912461 ILT |
426 | from the GPRs after they are loaded from memory, and thus does not |
427 | require nops to be inserted. This applies to instructions marked | |
428 | INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA | |
429 | level I. */ | |
252b5132 | 430 | #define gpr_interlocks \ |
e7af610e | 431 | (mips_opts.isa != ISA_MIPS1 \ |
fef14a42 | 432 | || mips_opts.arch == CPU_R3900) |
252b5132 | 433 | |
81912461 ILT |
434 | /* Whether the processor uses hardware interlocks to avoid delays |
435 | required by coprocessor instructions, and thus does not require | |
436 | nops to be inserted. This applies to instructions marked | |
437 | INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays | |
438 | between instructions marked INSN_WRITE_COND_CODE and ones marked | |
439 | INSN_READ_COND_CODE. These nops are only required at MIPS ISA | |
440 | levels I, II, and III. */ | |
bdaaa2e1 | 441 | /* Itbl support may require additional care here. */ |
81912461 ILT |
442 | #define cop_interlocks \ |
443 | ((mips_opts.isa != ISA_MIPS1 \ | |
444 | && mips_opts.isa != ISA_MIPS2 \ | |
445 | && mips_opts.isa != ISA_MIPS3) \ | |
446 | || mips_opts.arch == CPU_R4300 \ | |
81912461 ILT |
447 | ) |
448 | ||
449 | /* Whether the processor uses hardware interlocks to protect reads | |
450 | from coprocessor registers after they are loaded from memory, and | |
451 | thus does not require nops to be inserted. This applies to | |
452 | instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only | |
453 | requires at MIPS ISA level I. */ | |
454 | #define cop_mem_interlocks (mips_opts.isa != ISA_MIPS1) | |
252b5132 | 455 | |
6b76fefe CM |
456 | /* Is this a mfhi or mflo instruction? */ |
457 | #define MF_HILO_INSN(PINFO) \ | |
458 | ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO)) | |
459 | ||
252b5132 RH |
460 | /* MIPS PIC level. */ |
461 | ||
a161fe53 | 462 | enum mips_pic_level mips_pic; |
252b5132 | 463 | |
c9914766 | 464 | /* 1 if we should generate 32 bit offsets from the $gp register in |
252b5132 | 465 | SVR4_PIC mode. Currently has no meaning in other modes. */ |
c9914766 | 466 | static int mips_big_got = 0; |
252b5132 RH |
467 | |
468 | /* 1 if trap instructions should used for overflow rather than break | |
469 | instructions. */ | |
c9914766 | 470 | static int mips_trap = 0; |
252b5132 | 471 | |
119d663a | 472 | /* 1 if double width floating point constants should not be constructed |
b6ff326e | 473 | by assembling two single width halves into two single width floating |
119d663a NC |
474 | point registers which just happen to alias the double width destination |
475 | register. On some architectures this aliasing can be disabled by a bit | |
d547a75e | 476 | in the status register, and the setting of this bit cannot be determined |
119d663a NC |
477 | automatically at assemble time. */ |
478 | static int mips_disable_float_construction; | |
479 | ||
252b5132 RH |
480 | /* Non-zero if any .set noreorder directives were used. */ |
481 | ||
482 | static int mips_any_noreorder; | |
483 | ||
6b76fefe CM |
484 | /* Non-zero if nops should be inserted when the register referenced in |
485 | an mfhi/mflo instruction is read in the next two instructions. */ | |
486 | static int mips_7000_hilo_fix; | |
487 | ||
252b5132 | 488 | /* The size of the small data section. */ |
156c2f8b | 489 | static unsigned int g_switch_value = 8; |
252b5132 RH |
490 | /* Whether the -G option was used. */ |
491 | static int g_switch_seen = 0; | |
492 | ||
493 | #define N_RMASK 0xc4 | |
494 | #define N_VFP 0xd4 | |
495 | ||
496 | /* If we can determine in advance that GP optimization won't be | |
497 | possible, we can skip the relaxation stuff that tries to produce | |
498 | GP-relative references. This makes delay slot optimization work | |
499 | better. | |
500 | ||
501 | This function can only provide a guess, but it seems to work for | |
fba2b7f9 GK |
502 | gcc output. It needs to guess right for gcc, otherwise gcc |
503 | will put what it thinks is a GP-relative instruction in a branch | |
504 | delay slot. | |
252b5132 RH |
505 | |
506 | I don't know if a fix is needed for the SVR4_PIC mode. I've only | |
507 | fixed it for the non-PIC mode. KR 95/04/07 */ | |
17a2f251 | 508 | static int nopic_need_relax (symbolS *, int); |
252b5132 RH |
509 | |
510 | /* handle of the OPCODE hash table */ | |
511 | static struct hash_control *op_hash = NULL; | |
512 | ||
513 | /* The opcode hash table we use for the mips16. */ | |
514 | static struct hash_control *mips16_op_hash = NULL; | |
515 | ||
516 | /* This array holds the chars that always start a comment. If the | |
517 | pre-processor is disabled, these aren't very useful */ | |
518 | const char comment_chars[] = "#"; | |
519 | ||
520 | /* This array holds the chars that only start a comment at the beginning of | |
521 | a line. If the line seems to have the form '# 123 filename' | |
522 | .line and .file directives will appear in the pre-processed output */ | |
523 | /* Note that input_file.c hand checks for '#' at the beginning of the | |
524 | first line of the input file. This is because the compiler outputs | |
bdaaa2e1 | 525 | #NO_APP at the beginning of its output. */ |
252b5132 RH |
526 | /* Also note that C style comments are always supported. */ |
527 | const char line_comment_chars[] = "#"; | |
528 | ||
bdaaa2e1 | 529 | /* This array holds machine specific line separator characters. */ |
63a0b638 | 530 | const char line_separator_chars[] = ";"; |
252b5132 RH |
531 | |
532 | /* Chars that can be used to separate mant from exp in floating point nums */ | |
533 | const char EXP_CHARS[] = "eE"; | |
534 | ||
535 | /* Chars that mean this number is a floating point constant */ | |
536 | /* As in 0f12.456 */ | |
537 | /* or 0d1.2345e12 */ | |
538 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; | |
539 | ||
540 | /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be | |
541 | changed in read.c . Ideally it shouldn't have to know about it at all, | |
542 | but nothing is ideal around here. | |
543 | */ | |
544 | ||
545 | static char *insn_error; | |
546 | ||
547 | static int auto_align = 1; | |
548 | ||
549 | /* When outputting SVR4 PIC code, the assembler needs to know the | |
550 | offset in the stack frame from which to restore the $gp register. | |
551 | This is set by the .cprestore pseudo-op, and saved in this | |
552 | variable. */ | |
553 | static offsetT mips_cprestore_offset = -1; | |
554 | ||
67c1ffbe | 555 | /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some |
6478892d | 556 | more optimizations, it can use a register value instead of a memory-saved |
956cd1d6 | 557 | offset and even an other register than $gp as global pointer. */ |
6478892d TS |
558 | static offsetT mips_cpreturn_offset = -1; |
559 | static int mips_cpreturn_register = -1; | |
560 | static int mips_gp_register = GP; | |
def2e0dd | 561 | static int mips_gprel_offset = 0; |
6478892d | 562 | |
7a621144 DJ |
563 | /* Whether mips_cprestore_offset has been set in the current function |
564 | (or whether it has already been warned about, if not). */ | |
565 | static int mips_cprestore_valid = 0; | |
566 | ||
252b5132 RH |
567 | /* This is the register which holds the stack frame, as set by the |
568 | .frame pseudo-op. This is needed to implement .cprestore. */ | |
569 | static int mips_frame_reg = SP; | |
570 | ||
7a621144 DJ |
571 | /* Whether mips_frame_reg has been set in the current function |
572 | (or whether it has already been warned about, if not). */ | |
573 | static int mips_frame_reg_valid = 0; | |
574 | ||
252b5132 RH |
575 | /* To output NOP instructions correctly, we need to keep information |
576 | about the previous two instructions. */ | |
577 | ||
578 | /* Whether we are optimizing. The default value of 2 means to remove | |
579 | unneeded NOPs and swap branch instructions when possible. A value | |
580 | of 1 means to not swap branches. A value of 0 means to always | |
581 | insert NOPs. */ | |
582 | static int mips_optimize = 2; | |
583 | ||
584 | /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is | |
585 | equivalent to seeing no -g option at all. */ | |
586 | static int mips_debug = 0; | |
587 | ||
7d8e00cf RS |
588 | /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */ |
589 | #define MAX_VR4130_NOPS 4 | |
590 | ||
591 | /* The maximum number of NOPs needed to fill delay slots. */ | |
592 | #define MAX_DELAY_NOPS 2 | |
593 | ||
594 | /* The maximum number of NOPs needed for any purpose. */ | |
595 | #define MAX_NOPS 4 | |
71400594 RS |
596 | |
597 | /* A list of previous instructions, with index 0 being the most recent. | |
598 | We need to look back MAX_NOPS instructions when filling delay slots | |
599 | or working around processor errata. We need to look back one | |
600 | instruction further if we're thinking about using history[0] to | |
601 | fill a branch delay slot. */ | |
602 | static struct mips_cl_insn history[1 + MAX_NOPS]; | |
252b5132 | 603 | |
1e915849 RS |
604 | /* Nop instructions used by emit_nop. */ |
605 | static struct mips_cl_insn nop_insn, mips16_nop_insn; | |
606 | ||
607 | /* The appropriate nop for the current mode. */ | |
608 | #define NOP_INSN (mips_opts.mips16 ? &mips16_nop_insn : &nop_insn) | |
252b5132 | 609 | |
252b5132 RH |
610 | /* If this is set, it points to a frag holding nop instructions which |
611 | were inserted before the start of a noreorder section. If those | |
612 | nops turn out to be unnecessary, the size of the frag can be | |
613 | decreased. */ | |
614 | static fragS *prev_nop_frag; | |
615 | ||
616 | /* The number of nop instructions we created in prev_nop_frag. */ | |
617 | static int prev_nop_frag_holds; | |
618 | ||
619 | /* The number of nop instructions that we know we need in | |
bdaaa2e1 | 620 | prev_nop_frag. */ |
252b5132 RH |
621 | static int prev_nop_frag_required; |
622 | ||
623 | /* The number of instructions we've seen since prev_nop_frag. */ | |
624 | static int prev_nop_frag_since; | |
625 | ||
626 | /* For ECOFF and ELF, relocations against symbols are done in two | |
627 | parts, with a HI relocation and a LO relocation. Each relocation | |
628 | has only 16 bits of space to store an addend. This means that in | |
629 | order for the linker to handle carries correctly, it must be able | |
630 | to locate both the HI and the LO relocation. This means that the | |
631 | relocations must appear in order in the relocation table. | |
632 | ||
633 | In order to implement this, we keep track of each unmatched HI | |
634 | relocation. We then sort them so that they immediately precede the | |
bdaaa2e1 | 635 | corresponding LO relocation. */ |
252b5132 | 636 | |
e972090a NC |
637 | struct mips_hi_fixup |
638 | { | |
252b5132 RH |
639 | /* Next HI fixup. */ |
640 | struct mips_hi_fixup *next; | |
641 | /* This fixup. */ | |
642 | fixS *fixp; | |
643 | /* The section this fixup is in. */ | |
644 | segT seg; | |
645 | }; | |
646 | ||
647 | /* The list of unmatched HI relocs. */ | |
648 | ||
649 | static struct mips_hi_fixup *mips_hi_fixup_list; | |
650 | ||
64bdfcaf RS |
651 | /* The frag containing the last explicit relocation operator. |
652 | Null if explicit relocations have not been used. */ | |
653 | ||
654 | static fragS *prev_reloc_op_frag; | |
655 | ||
252b5132 RH |
656 | /* Map normal MIPS register numbers to mips16 register numbers. */ |
657 | ||
658 | #define X ILLEGAL_REG | |
e972090a NC |
659 | static const int mips32_to_16_reg_map[] = |
660 | { | |
252b5132 RH |
661 | X, X, 2, 3, 4, 5, 6, 7, |
662 | X, X, X, X, X, X, X, X, | |
663 | 0, 1, X, X, X, X, X, X, | |
664 | X, X, X, X, X, X, X, X | |
665 | }; | |
666 | #undef X | |
667 | ||
668 | /* Map mips16 register numbers to normal MIPS register numbers. */ | |
669 | ||
e972090a NC |
670 | static const unsigned int mips16_to_32_reg_map[] = |
671 | { | |
252b5132 RH |
672 | 16, 17, 2, 3, 4, 5, 6, 7 |
673 | }; | |
60b63b72 | 674 | |
71400594 RS |
675 | /* Classifies the kind of instructions we're interested in when |
676 | implementing -mfix-vr4120. */ | |
677 | enum fix_vr4120_class { | |
678 | FIX_VR4120_MACC, | |
679 | FIX_VR4120_DMACC, | |
680 | FIX_VR4120_MULT, | |
681 | FIX_VR4120_DMULT, | |
682 | FIX_VR4120_DIV, | |
683 | FIX_VR4120_MTHILO, | |
684 | NUM_FIX_VR4120_CLASSES | |
685 | }; | |
686 | ||
687 | /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if | |
688 | there must be at least one other instruction between an instruction | |
689 | of type X and an instruction of type Y. */ | |
690 | static unsigned int vr4120_conflicts[NUM_FIX_VR4120_CLASSES]; | |
691 | ||
692 | /* True if -mfix-vr4120 is in force. */ | |
d766e8ec | 693 | static int mips_fix_vr4120; |
4a6a3df4 | 694 | |
7d8e00cf RS |
695 | /* ...likewise -mfix-vr4130. */ |
696 | static int mips_fix_vr4130; | |
697 | ||
4a6a3df4 AO |
698 | /* We don't relax branches by default, since this causes us to expand |
699 | `la .l2 - .l1' if there's a branch between .l1 and .l2, because we | |
700 | fail to compute the offset before expanding the macro to the most | |
701 | efficient expansion. */ | |
702 | ||
703 | static int mips_relax_branch; | |
252b5132 | 704 | \f |
4d7206a2 RS |
705 | /* The expansion of many macros depends on the type of symbol that |
706 | they refer to. For example, when generating position-dependent code, | |
707 | a macro that refers to a symbol may have two different expansions, | |
708 | one which uses GP-relative addresses and one which uses absolute | |
709 | addresses. When generating SVR4-style PIC, a macro may have | |
710 | different expansions for local and global symbols. | |
711 | ||
712 | We handle these situations by generating both sequences and putting | |
713 | them in variant frags. In position-dependent code, the first sequence | |
714 | will be the GP-relative one and the second sequence will be the | |
715 | absolute one. In SVR4 PIC, the first sequence will be for global | |
716 | symbols and the second will be for local symbols. | |
717 | ||
584892a6 RS |
718 | The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and |
719 | SECOND are the lengths of the two sequences in bytes. These fields | |
720 | can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition, | |
721 | the subtype has the following flags: | |
4d7206a2 | 722 | |
584892a6 RS |
723 | RELAX_USE_SECOND |
724 | Set if it has been decided that we should use the second | |
725 | sequence instead of the first. | |
726 | ||
727 | RELAX_SECOND_LONGER | |
728 | Set in the first variant frag if the macro's second implementation | |
729 | is longer than its first. This refers to the macro as a whole, | |
730 | not an individual relaxation. | |
731 | ||
732 | RELAX_NOMACRO | |
733 | Set in the first variant frag if the macro appeared in a .set nomacro | |
734 | block and if one alternative requires a warning but the other does not. | |
735 | ||
736 | RELAX_DELAY_SLOT | |
737 | Like RELAX_NOMACRO, but indicates that the macro appears in a branch | |
738 | delay slot. | |
4d7206a2 RS |
739 | |
740 | The frag's "opcode" points to the first fixup for relaxable code. | |
741 | ||
742 | Relaxable macros are generated using a sequence such as: | |
743 | ||
744 | relax_start (SYMBOL); | |
745 | ... generate first expansion ... | |
746 | relax_switch (); | |
747 | ... generate second expansion ... | |
748 | relax_end (); | |
749 | ||
750 | The code and fixups for the unwanted alternative are discarded | |
751 | by md_convert_frag. */ | |
584892a6 | 752 | #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND)) |
4d7206a2 | 753 | |
584892a6 RS |
754 | #define RELAX_FIRST(X) (((X) >> 8) & 0xff) |
755 | #define RELAX_SECOND(X) ((X) & 0xff) | |
756 | #define RELAX_USE_SECOND 0x10000 | |
757 | #define RELAX_SECOND_LONGER 0x20000 | |
758 | #define RELAX_NOMACRO 0x40000 | |
759 | #define RELAX_DELAY_SLOT 0x80000 | |
252b5132 | 760 | |
4a6a3df4 AO |
761 | /* Branch without likely bit. If label is out of range, we turn: |
762 | ||
763 | beq reg1, reg2, label | |
764 | delay slot | |
765 | ||
766 | into | |
767 | ||
768 | bne reg1, reg2, 0f | |
769 | nop | |
770 | j label | |
771 | 0: delay slot | |
772 | ||
773 | with the following opcode replacements: | |
774 | ||
775 | beq <-> bne | |
776 | blez <-> bgtz | |
777 | bltz <-> bgez | |
778 | bc1f <-> bc1t | |
779 | ||
780 | bltzal <-> bgezal (with jal label instead of j label) | |
781 | ||
782 | Even though keeping the delay slot instruction in the delay slot of | |
783 | the branch would be more efficient, it would be very tricky to do | |
784 | correctly, because we'd have to introduce a variable frag *after* | |
785 | the delay slot instruction, and expand that instead. Let's do it | |
786 | the easy way for now, even if the branch-not-taken case now costs | |
787 | one additional instruction. Out-of-range branches are not supposed | |
788 | to be common, anyway. | |
789 | ||
790 | Branch likely. If label is out of range, we turn: | |
791 | ||
792 | beql reg1, reg2, label | |
793 | delay slot (annulled if branch not taken) | |
794 | ||
795 | into | |
796 | ||
797 | beql reg1, reg2, 1f | |
798 | nop | |
799 | beql $0, $0, 2f | |
800 | nop | |
801 | 1: j[al] label | |
802 | delay slot (executed only if branch taken) | |
803 | 2: | |
804 | ||
805 | It would be possible to generate a shorter sequence by losing the | |
806 | likely bit, generating something like: | |
b34976b6 | 807 | |
4a6a3df4 AO |
808 | bne reg1, reg2, 0f |
809 | nop | |
810 | j[al] label | |
811 | delay slot (executed only if branch taken) | |
812 | 0: | |
813 | ||
814 | beql -> bne | |
815 | bnel -> beq | |
816 | blezl -> bgtz | |
817 | bgtzl -> blez | |
818 | bltzl -> bgez | |
819 | bgezl -> bltz | |
820 | bc1fl -> bc1t | |
821 | bc1tl -> bc1f | |
822 | ||
823 | bltzall -> bgezal (with jal label instead of j label) | |
824 | bgezall -> bltzal (ditto) | |
825 | ||
826 | ||
827 | but it's not clear that it would actually improve performance. */ | |
af6ae2ad | 828 | #define RELAX_BRANCH_ENCODE(uncond, likely, link, toofar) \ |
4a6a3df4 AO |
829 | ((relax_substateT) \ |
830 | (0xc0000000 \ | |
831 | | ((toofar) ? 1 : 0) \ | |
832 | | ((link) ? 2 : 0) \ | |
833 | | ((likely) ? 4 : 0) \ | |
af6ae2ad | 834 | | ((uncond) ? 8 : 0))) |
4a6a3df4 | 835 | #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000) |
4a6a3df4 AO |
836 | #define RELAX_BRANCH_UNCOND(i) (((i) & 8) != 0) |
837 | #define RELAX_BRANCH_LIKELY(i) (((i) & 4) != 0) | |
838 | #define RELAX_BRANCH_LINK(i) (((i) & 2) != 0) | |
ae6063d4 | 839 | #define RELAX_BRANCH_TOOFAR(i) (((i) & 1) != 0) |
4a6a3df4 | 840 | |
252b5132 RH |
841 | /* For mips16 code, we use an entirely different form of relaxation. |
842 | mips16 supports two versions of most instructions which take | |
843 | immediate values: a small one which takes some small value, and a | |
844 | larger one which takes a 16 bit value. Since branches also follow | |
845 | this pattern, relaxing these values is required. | |
846 | ||
847 | We can assemble both mips16 and normal MIPS code in a single | |
848 | object. Therefore, we need to support this type of relaxation at | |
849 | the same time that we support the relaxation described above. We | |
850 | use the high bit of the subtype field to distinguish these cases. | |
851 | ||
852 | The information we store for this type of relaxation is the | |
853 | argument code found in the opcode file for this relocation, whether | |
854 | the user explicitly requested a small or extended form, and whether | |
855 | the relocation is in a jump or jal delay slot. That tells us the | |
856 | size of the value, and how it should be stored. We also store | |
857 | whether the fragment is considered to be extended or not. We also | |
858 | store whether this is known to be a branch to a different section, | |
859 | whether we have tried to relax this frag yet, and whether we have | |
860 | ever extended a PC relative fragment because of a shift count. */ | |
861 | #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \ | |
862 | (0x80000000 \ | |
863 | | ((type) & 0xff) \ | |
864 | | ((small) ? 0x100 : 0) \ | |
865 | | ((ext) ? 0x200 : 0) \ | |
866 | | ((dslot) ? 0x400 : 0) \ | |
867 | | ((jal_dslot) ? 0x800 : 0)) | |
4a6a3df4 | 868 | #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000) |
252b5132 RH |
869 | #define RELAX_MIPS16_TYPE(i) ((i) & 0xff) |
870 | #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0) | |
871 | #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0) | |
872 | #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0) | |
873 | #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0) | |
874 | #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0) | |
875 | #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000) | |
876 | #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000) | |
877 | #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0) | |
878 | #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000) | |
879 | #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000) | |
885add95 CD |
880 | |
881 | /* Is the given value a sign-extended 32-bit value? */ | |
882 | #define IS_SEXT_32BIT_NUM(x) \ | |
883 | (((x) &~ (offsetT) 0x7fffffff) == 0 \ | |
884 | || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff)) | |
885 | ||
886 | /* Is the given value a sign-extended 16-bit value? */ | |
887 | #define IS_SEXT_16BIT_NUM(x) \ | |
888 | (((x) &~ (offsetT) 0x7fff) == 0 \ | |
889 | || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff)) | |
890 | ||
2051e8c4 MR |
891 | /* Is the given value a zero-extended 32-bit value? Or a negated one? */ |
892 | #define IS_ZEXT_32BIT_NUM(x) \ | |
893 | (((x) &~ (offsetT) 0xffffffff) == 0 \ | |
894 | || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff)) | |
895 | ||
bf12938e RS |
896 | /* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in |
897 | VALUE << SHIFT. VALUE is evaluated exactly once. */ | |
898 | #define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \ | |
899 | (STRUCT) = (((STRUCT) & ~((MASK) << (SHIFT))) \ | |
900 | | (((VALUE) & (MASK)) << (SHIFT))) | |
901 | ||
902 | /* Extract bits MASK << SHIFT from STRUCT and shift them right | |
903 | SHIFT places. */ | |
904 | #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \ | |
905 | (((STRUCT) >> (SHIFT)) & (MASK)) | |
906 | ||
907 | /* Change INSN's opcode so that the operand given by FIELD has value VALUE. | |
908 | INSN is a mips_cl_insn structure and VALUE is evaluated exactly once. | |
909 | ||
910 | include/opcode/mips.h specifies operand fields using the macros | |
911 | OP_MASK_<FIELD> and OP_SH_<FIELD>. The MIPS16 equivalents start | |
912 | with "MIPS16OP" instead of "OP". */ | |
913 | #define INSERT_OPERAND(FIELD, INSN, VALUE) \ | |
914 | INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD) | |
915 | #define MIPS16_INSERT_OPERAND(FIELD, INSN, VALUE) \ | |
916 | INSERT_BITS ((INSN).insn_opcode, VALUE, \ | |
917 | MIPS16OP_MASK_##FIELD, MIPS16OP_SH_##FIELD) | |
918 | ||
919 | /* Extract the operand given by FIELD from mips_cl_insn INSN. */ | |
920 | #define EXTRACT_OPERAND(FIELD, INSN) \ | |
921 | EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) | |
922 | #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \ | |
923 | EXTRACT_BITS ((INSN).insn_opcode, \ | |
924 | MIPS16OP_MASK_##FIELD, \ | |
925 | MIPS16OP_SH_##FIELD) | |
4d7206a2 RS |
926 | \f |
927 | /* Global variables used when generating relaxable macros. See the | |
928 | comment above RELAX_ENCODE for more details about how relaxation | |
929 | is used. */ | |
930 | static struct { | |
931 | /* 0 if we're not emitting a relaxable macro. | |
932 | 1 if we're emitting the first of the two relaxation alternatives. | |
933 | 2 if we're emitting the second alternative. */ | |
934 | int sequence; | |
935 | ||
936 | /* The first relaxable fixup in the current frag. (In other words, | |
937 | the first fixup that refers to relaxable code.) */ | |
938 | fixS *first_fixup; | |
939 | ||
940 | /* sizes[0] says how many bytes of the first alternative are stored in | |
941 | the current frag. Likewise sizes[1] for the second alternative. */ | |
942 | unsigned int sizes[2]; | |
943 | ||
944 | /* The symbol on which the choice of sequence depends. */ | |
945 | symbolS *symbol; | |
946 | } mips_relax; | |
252b5132 | 947 | \f |
584892a6 RS |
948 | /* Global variables used to decide whether a macro needs a warning. */ |
949 | static struct { | |
950 | /* True if the macro is in a branch delay slot. */ | |
951 | bfd_boolean delay_slot_p; | |
952 | ||
953 | /* For relaxable macros, sizes[0] is the length of the first alternative | |
954 | in bytes and sizes[1] is the length of the second alternative. | |
955 | For non-relaxable macros, both elements give the length of the | |
956 | macro in bytes. */ | |
957 | unsigned int sizes[2]; | |
958 | ||
959 | /* The first variant frag for this macro. */ | |
960 | fragS *first_frag; | |
961 | } mips_macro_warning; | |
962 | \f | |
252b5132 RH |
963 | /* Prototypes for static functions. */ |
964 | ||
17a2f251 | 965 | #define internalError() \ |
252b5132 | 966 | as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__) |
252b5132 RH |
967 | |
968 | enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG }; | |
969 | ||
b34976b6 | 970 | static void append_insn |
4d7206a2 | 971 | (struct mips_cl_insn *ip, expressionS *p, bfd_reloc_code_real_type *r); |
7d10b47d | 972 | static void mips_no_prev_insn (void); |
b34976b6 | 973 | static void mips16_macro_build |
67c0d1eb RS |
974 | (expressionS *, const char *, const char *, va_list); |
975 | static void load_register (int, expressionS *, int); | |
584892a6 RS |
976 | static void macro_start (void); |
977 | static void macro_end (void); | |
17a2f251 TS |
978 | static void macro (struct mips_cl_insn * ip); |
979 | static void mips16_macro (struct mips_cl_insn * ip); | |
252b5132 | 980 | #ifdef LOSING_COMPILER |
17a2f251 | 981 | static void macro2 (struct mips_cl_insn * ip); |
252b5132 | 982 | #endif |
17a2f251 TS |
983 | static void mips_ip (char *str, struct mips_cl_insn * ip); |
984 | static void mips16_ip (char *str, struct mips_cl_insn * ip); | |
b34976b6 | 985 | static void mips16_immed |
17a2f251 TS |
986 | (char *, unsigned int, int, offsetT, bfd_boolean, bfd_boolean, bfd_boolean, |
987 | unsigned long *, bfd_boolean *, unsigned short *); | |
5e0116d5 | 988 | static size_t my_getSmallExpression |
17a2f251 TS |
989 | (expressionS *, bfd_reloc_code_real_type *, char *); |
990 | static void my_getExpression (expressionS *, char *); | |
991 | static void s_align (int); | |
992 | static void s_change_sec (int); | |
993 | static void s_change_section (int); | |
994 | static void s_cons (int); | |
995 | static void s_float_cons (int); | |
996 | static void s_mips_globl (int); | |
997 | static void s_option (int); | |
998 | static void s_mipsset (int); | |
999 | static void s_abicalls (int); | |
1000 | static void s_cpload (int); | |
1001 | static void s_cpsetup (int); | |
1002 | static void s_cplocal (int); | |
1003 | static void s_cprestore (int); | |
1004 | static void s_cpreturn (int); | |
1005 | static void s_gpvalue (int); | |
1006 | static void s_gpword (int); | |
1007 | static void s_gpdword (int); | |
1008 | static void s_cpadd (int); | |
1009 | static void s_insn (int); | |
1010 | static void md_obj_begin (void); | |
1011 | static void md_obj_end (void); | |
1012 | static void s_mips_ent (int); | |
1013 | static void s_mips_end (int); | |
1014 | static void s_mips_frame (int); | |
1015 | static void s_mips_mask (int reg_type); | |
1016 | static void s_mips_stab (int); | |
1017 | static void s_mips_weakext (int); | |
1018 | static void s_mips_file (int); | |
1019 | static void s_mips_loc (int); | |
1020 | static bfd_boolean pic_need_relax (symbolS *, asection *); | |
4a6a3df4 | 1021 | static int relaxed_branch_length (fragS *, asection *, int); |
17a2f251 | 1022 | static int validate_mips_insn (const struct mips_opcode *); |
e7af610e NC |
1023 | |
1024 | /* Table and functions used to map between CPU/ISA names, and | |
1025 | ISA levels, and CPU numbers. */ | |
1026 | ||
e972090a NC |
1027 | struct mips_cpu_info |
1028 | { | |
e7af610e NC |
1029 | const char *name; /* CPU or ISA name. */ |
1030 | int is_isa; /* Is this an ISA? (If 0, a CPU.) */ | |
1031 | int isa; /* ISA level. */ | |
1032 | int cpu; /* CPU number (default CPU if ISA). */ | |
1033 | }; | |
1034 | ||
17a2f251 TS |
1035 | static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *); |
1036 | static const struct mips_cpu_info *mips_cpu_info_from_isa (int); | |
1037 | static const struct mips_cpu_info *mips_cpu_info_from_arch (int); | |
252b5132 RH |
1038 | \f |
1039 | /* Pseudo-op table. | |
1040 | ||
1041 | The following pseudo-ops from the Kane and Heinrich MIPS book | |
1042 | should be defined here, but are currently unsupported: .alias, | |
1043 | .galive, .gjaldef, .gjrlive, .livereg, .noalias. | |
1044 | ||
1045 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
1046 | specific to the type of debugging information being generated, and | |
1047 | should be defined by the object format: .aent, .begin, .bend, | |
1048 | .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp, | |
1049 | .vreg. | |
1050 | ||
1051 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
1052 | not MIPS CPU specific, but are also not specific to the object file | |
1053 | format. This file is probably the best place to define them, but | |
1054 | they are not currently supported: .asm0, .endr, .lab, .repeat, | |
1055 | .struct. */ | |
1056 | ||
e972090a NC |
1057 | static const pseudo_typeS mips_pseudo_table[] = |
1058 | { | |
beae10d5 | 1059 | /* MIPS specific pseudo-ops. */ |
252b5132 RH |
1060 | {"option", s_option, 0}, |
1061 | {"set", s_mipsset, 0}, | |
1062 | {"rdata", s_change_sec, 'r'}, | |
1063 | {"sdata", s_change_sec, 's'}, | |
1064 | {"livereg", s_ignore, 0}, | |
1065 | {"abicalls", s_abicalls, 0}, | |
1066 | {"cpload", s_cpload, 0}, | |
6478892d TS |
1067 | {"cpsetup", s_cpsetup, 0}, |
1068 | {"cplocal", s_cplocal, 0}, | |
252b5132 | 1069 | {"cprestore", s_cprestore, 0}, |
6478892d TS |
1070 | {"cpreturn", s_cpreturn, 0}, |
1071 | {"gpvalue", s_gpvalue, 0}, | |
252b5132 | 1072 | {"gpword", s_gpword, 0}, |
10181a0d | 1073 | {"gpdword", s_gpdword, 0}, |
252b5132 RH |
1074 | {"cpadd", s_cpadd, 0}, |
1075 | {"insn", s_insn, 0}, | |
1076 | ||
beae10d5 | 1077 | /* Relatively generic pseudo-ops that happen to be used on MIPS |
252b5132 RH |
1078 | chips. */ |
1079 | {"asciiz", stringer, 1}, | |
1080 | {"bss", s_change_sec, 'b'}, | |
1081 | {"err", s_err, 0}, | |
1082 | {"half", s_cons, 1}, | |
1083 | {"dword", s_cons, 3}, | |
1084 | {"weakext", s_mips_weakext, 0}, | |
1085 | ||
beae10d5 | 1086 | /* These pseudo-ops are defined in read.c, but must be overridden |
252b5132 RH |
1087 | here for one reason or another. */ |
1088 | {"align", s_align, 0}, | |
1089 | {"byte", s_cons, 0}, | |
1090 | {"data", s_change_sec, 'd'}, | |
1091 | {"double", s_float_cons, 'd'}, | |
1092 | {"float", s_float_cons, 'f'}, | |
1093 | {"globl", s_mips_globl, 0}, | |
1094 | {"global", s_mips_globl, 0}, | |
1095 | {"hword", s_cons, 1}, | |
1096 | {"int", s_cons, 2}, | |
1097 | {"long", s_cons, 2}, | |
1098 | {"octa", s_cons, 4}, | |
1099 | {"quad", s_cons, 3}, | |
cca86cc8 | 1100 | {"section", s_change_section, 0}, |
252b5132 RH |
1101 | {"short", s_cons, 1}, |
1102 | {"single", s_float_cons, 'f'}, | |
1103 | {"stabn", s_mips_stab, 'n'}, | |
1104 | {"text", s_change_sec, 't'}, | |
1105 | {"word", s_cons, 2}, | |
add56521 | 1106 | |
add56521 | 1107 | { "extern", ecoff_directive_extern, 0}, |
add56521 | 1108 | |
43841e91 | 1109 | { NULL, NULL, 0 }, |
252b5132 RH |
1110 | }; |
1111 | ||
e972090a NC |
1112 | static const pseudo_typeS mips_nonecoff_pseudo_table[] = |
1113 | { | |
beae10d5 KH |
1114 | /* These pseudo-ops should be defined by the object file format. |
1115 | However, a.out doesn't support them, so we have versions here. */ | |
252b5132 RH |
1116 | {"aent", s_mips_ent, 1}, |
1117 | {"bgnb", s_ignore, 0}, | |
1118 | {"end", s_mips_end, 0}, | |
1119 | {"endb", s_ignore, 0}, | |
1120 | {"ent", s_mips_ent, 0}, | |
c5dd6aab | 1121 | {"file", s_mips_file, 0}, |
252b5132 RH |
1122 | {"fmask", s_mips_mask, 'F'}, |
1123 | {"frame", s_mips_frame, 0}, | |
c5dd6aab | 1124 | {"loc", s_mips_loc, 0}, |
252b5132 RH |
1125 | {"mask", s_mips_mask, 'R'}, |
1126 | {"verstamp", s_ignore, 0}, | |
43841e91 | 1127 | { NULL, NULL, 0 }, |
252b5132 RH |
1128 | }; |
1129 | ||
17a2f251 | 1130 | extern void pop_insert (const pseudo_typeS *); |
252b5132 RH |
1131 | |
1132 | void | |
17a2f251 | 1133 | mips_pop_insert (void) |
252b5132 RH |
1134 | { |
1135 | pop_insert (mips_pseudo_table); | |
1136 | if (! ECOFF_DEBUGGING) | |
1137 | pop_insert (mips_nonecoff_pseudo_table); | |
1138 | } | |
1139 | \f | |
1140 | /* Symbols labelling the current insn. */ | |
1141 | ||
e972090a NC |
1142 | struct insn_label_list |
1143 | { | |
252b5132 RH |
1144 | struct insn_label_list *next; |
1145 | symbolS *label; | |
1146 | }; | |
1147 | ||
1148 | static struct insn_label_list *insn_labels; | |
1149 | static struct insn_label_list *free_insn_labels; | |
1150 | ||
17a2f251 | 1151 | static void mips_clear_insn_labels (void); |
252b5132 RH |
1152 | |
1153 | static inline void | |
17a2f251 | 1154 | mips_clear_insn_labels (void) |
252b5132 RH |
1155 | { |
1156 | register struct insn_label_list **pl; | |
1157 | ||
1158 | for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next) | |
1159 | ; | |
1160 | *pl = insn_labels; | |
1161 | insn_labels = NULL; | |
1162 | } | |
1163 | \f | |
1164 | static char *expr_end; | |
1165 | ||
1166 | /* Expressions which appear in instructions. These are set by | |
1167 | mips_ip. */ | |
1168 | ||
1169 | static expressionS imm_expr; | |
5f74bc13 | 1170 | static expressionS imm2_expr; |
252b5132 RH |
1171 | static expressionS offset_expr; |
1172 | ||
1173 | /* Relocs associated with imm_expr and offset_expr. */ | |
1174 | ||
f6688943 TS |
1175 | static bfd_reloc_code_real_type imm_reloc[3] |
1176 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
1177 | static bfd_reloc_code_real_type offset_reloc[3] | |
1178 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 1179 | |
252b5132 RH |
1180 | /* These are set by mips16_ip if an explicit extension is used. */ |
1181 | ||
b34976b6 | 1182 | static bfd_boolean mips16_small, mips16_ext; |
252b5132 | 1183 | |
7ed4a06a | 1184 | #ifdef OBJ_ELF |
ecb4347a DJ |
1185 | /* The pdr segment for per procedure frame/regmask info. Not used for |
1186 | ECOFF debugging. */ | |
252b5132 RH |
1187 | |
1188 | static segT pdr_seg; | |
7ed4a06a | 1189 | #endif |
252b5132 | 1190 | |
e013f690 TS |
1191 | /* The default target format to use. */ |
1192 | ||
1193 | const char * | |
17a2f251 | 1194 | mips_target_format (void) |
e013f690 TS |
1195 | { |
1196 | switch (OUTPUT_FLAVOR) | |
1197 | { | |
e013f690 TS |
1198 | case bfd_target_ecoff_flavour: |
1199 | return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT; | |
1200 | case bfd_target_coff_flavour: | |
1201 | return "pe-mips"; | |
1202 | case bfd_target_elf_flavour: | |
0a44bf69 RS |
1203 | #ifdef TE_VXWORKS |
1204 | if (!HAVE_64BIT_OBJECTS && !HAVE_NEWABI) | |
1205 | return (target_big_endian | |
1206 | ? "elf32-bigmips-vxworks" | |
1207 | : "elf32-littlemips-vxworks"); | |
1208 | #endif | |
e013f690 | 1209 | #ifdef TE_TMIPS |
cfe86eaa | 1210 | /* This is traditional mips. */ |
e013f690 | 1211 | return (target_big_endian |
cfe86eaa TS |
1212 | ? (HAVE_64BIT_OBJECTS |
1213 | ? "elf64-tradbigmips" | |
1214 | : (HAVE_NEWABI | |
1215 | ? "elf32-ntradbigmips" : "elf32-tradbigmips")) | |
1216 | : (HAVE_64BIT_OBJECTS | |
1217 | ? "elf64-tradlittlemips" | |
1218 | : (HAVE_NEWABI | |
1219 | ? "elf32-ntradlittlemips" : "elf32-tradlittlemips"))); | |
e013f690 TS |
1220 | #else |
1221 | return (target_big_endian | |
cfe86eaa TS |
1222 | ? (HAVE_64BIT_OBJECTS |
1223 | ? "elf64-bigmips" | |
1224 | : (HAVE_NEWABI | |
1225 | ? "elf32-nbigmips" : "elf32-bigmips")) | |
1226 | : (HAVE_64BIT_OBJECTS | |
1227 | ? "elf64-littlemips" | |
1228 | : (HAVE_NEWABI | |
1229 | ? "elf32-nlittlemips" : "elf32-littlemips"))); | |
e013f690 TS |
1230 | #endif |
1231 | default: | |
1232 | abort (); | |
1233 | return NULL; | |
1234 | } | |
1235 | } | |
1236 | ||
1e915849 RS |
1237 | /* Return the length of instruction INSN. */ |
1238 | ||
1239 | static inline unsigned int | |
1240 | insn_length (const struct mips_cl_insn *insn) | |
1241 | { | |
1242 | if (!mips_opts.mips16) | |
1243 | return 4; | |
1244 | return insn->mips16_absolute_jump_p || insn->use_extend ? 4 : 2; | |
1245 | } | |
1246 | ||
1247 | /* Initialise INSN from opcode entry MO. Leave its position unspecified. */ | |
1248 | ||
1249 | static void | |
1250 | create_insn (struct mips_cl_insn *insn, const struct mips_opcode *mo) | |
1251 | { | |
1252 | size_t i; | |
1253 | ||
1254 | insn->insn_mo = mo; | |
1255 | insn->use_extend = FALSE; | |
1256 | insn->extend = 0; | |
1257 | insn->insn_opcode = mo->match; | |
1258 | insn->frag = NULL; | |
1259 | insn->where = 0; | |
1260 | for (i = 0; i < ARRAY_SIZE (insn->fixp); i++) | |
1261 | insn->fixp[i] = NULL; | |
1262 | insn->fixed_p = (mips_opts.noreorder > 0); | |
1263 | insn->noreorder_p = (mips_opts.noreorder > 0); | |
1264 | insn->mips16_absolute_jump_p = 0; | |
1265 | } | |
1266 | ||
1267 | /* Install INSN at the location specified by its "frag" and "where" fields. */ | |
1268 | ||
1269 | static void | |
1270 | install_insn (const struct mips_cl_insn *insn) | |
1271 | { | |
1272 | char *f = insn->frag->fr_literal + insn->where; | |
1273 | if (!mips_opts.mips16) | |
1274 | md_number_to_chars (f, insn->insn_opcode, 4); | |
1275 | else if (insn->mips16_absolute_jump_p) | |
1276 | { | |
1277 | md_number_to_chars (f, insn->insn_opcode >> 16, 2); | |
1278 | md_number_to_chars (f + 2, insn->insn_opcode & 0xffff, 2); | |
1279 | } | |
1280 | else | |
1281 | { | |
1282 | if (insn->use_extend) | |
1283 | { | |
1284 | md_number_to_chars (f, 0xf000 | insn->extend, 2); | |
1285 | f += 2; | |
1286 | } | |
1287 | md_number_to_chars (f, insn->insn_opcode, 2); | |
1288 | } | |
1289 | } | |
1290 | ||
1291 | /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly | |
1292 | and install the opcode in the new location. */ | |
1293 | ||
1294 | static void | |
1295 | move_insn (struct mips_cl_insn *insn, fragS *frag, long where) | |
1296 | { | |
1297 | size_t i; | |
1298 | ||
1299 | insn->frag = frag; | |
1300 | insn->where = where; | |
1301 | for (i = 0; i < ARRAY_SIZE (insn->fixp); i++) | |
1302 | if (insn->fixp[i] != NULL) | |
1303 | { | |
1304 | insn->fixp[i]->fx_frag = frag; | |
1305 | insn->fixp[i]->fx_where = where; | |
1306 | } | |
1307 | install_insn (insn); | |
1308 | } | |
1309 | ||
1310 | /* Add INSN to the end of the output. */ | |
1311 | ||
1312 | static void | |
1313 | add_fixed_insn (struct mips_cl_insn *insn) | |
1314 | { | |
1315 | char *f = frag_more (insn_length (insn)); | |
1316 | move_insn (insn, frag_now, f - frag_now->fr_literal); | |
1317 | } | |
1318 | ||
1319 | /* Start a variant frag and move INSN to the start of the variant part, | |
1320 | marking it as fixed. The other arguments are as for frag_var. */ | |
1321 | ||
1322 | static void | |
1323 | add_relaxed_insn (struct mips_cl_insn *insn, int max_chars, int var, | |
1324 | relax_substateT subtype, symbolS *symbol, offsetT offset) | |
1325 | { | |
1326 | frag_grow (max_chars); | |
1327 | move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal); | |
1328 | insn->fixed_p = 1; | |
1329 | frag_var (rs_machine_dependent, max_chars, var, | |
1330 | subtype, symbol, offset, NULL); | |
1331 | } | |
1332 | ||
1333 | /* Insert N copies of INSN into the history buffer, starting at | |
1334 | position FIRST. Neither FIRST nor N need to be clipped. */ | |
1335 | ||
1336 | static void | |
1337 | insert_into_history (unsigned int first, unsigned int n, | |
1338 | const struct mips_cl_insn *insn) | |
1339 | { | |
1340 | if (mips_relax.sequence != 2) | |
1341 | { | |
1342 | unsigned int i; | |
1343 | ||
1344 | for (i = ARRAY_SIZE (history); i-- > first;) | |
1345 | if (i >= first + n) | |
1346 | history[i] = history[i - n]; | |
1347 | else | |
1348 | history[i] = *insn; | |
1349 | } | |
1350 | } | |
1351 | ||
1352 | /* Emit a nop instruction, recording it in the history buffer. */ | |
1353 | ||
1354 | static void | |
1355 | emit_nop (void) | |
1356 | { | |
1357 | add_fixed_insn (NOP_INSN); | |
1358 | insert_into_history (0, 1, NOP_INSN); | |
1359 | } | |
1360 | ||
71400594 RS |
1361 | /* Initialize vr4120_conflicts. There is a bit of duplication here: |
1362 | the idea is to make it obvious at a glance that each errata is | |
1363 | included. */ | |
1364 | ||
1365 | static void | |
1366 | init_vr4120_conflicts (void) | |
1367 | { | |
1368 | #define CONFLICT(FIRST, SECOND) \ | |
1369 | vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND | |
1370 | ||
1371 | /* Errata 21 - [D]DIV[U] after [D]MACC */ | |
1372 | CONFLICT (MACC, DIV); | |
1373 | CONFLICT (DMACC, DIV); | |
1374 | ||
1375 | /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */ | |
1376 | CONFLICT (DMULT, DMULT); | |
1377 | CONFLICT (DMULT, DMACC); | |
1378 | CONFLICT (DMACC, DMULT); | |
1379 | CONFLICT (DMACC, DMACC); | |
1380 | ||
1381 | /* Errata 24 - MT{LO,HI} after [D]MACC */ | |
1382 | CONFLICT (MACC, MTHILO); | |
1383 | CONFLICT (DMACC, MTHILO); | |
1384 | ||
1385 | /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU | |
1386 | instruction is executed immediately after a MACC or DMACC | |
1387 | instruction, the result of [either instruction] is incorrect." */ | |
1388 | CONFLICT (MACC, MULT); | |
1389 | CONFLICT (MACC, DMULT); | |
1390 | CONFLICT (DMACC, MULT); | |
1391 | CONFLICT (DMACC, DMULT); | |
1392 | ||
1393 | /* VR4181A errata MD(4): "If a MACC or DMACC instruction is | |
1394 | executed immediately after a DMULT, DMULTU, DIV, DIVU, | |
1395 | DDIV or DDIVU instruction, the result of the MACC or | |
1396 | DMACC instruction is incorrect.". */ | |
1397 | CONFLICT (DMULT, MACC); | |
1398 | CONFLICT (DMULT, DMACC); | |
1399 | CONFLICT (DIV, MACC); | |
1400 | CONFLICT (DIV, DMACC); | |
1401 | ||
1402 | #undef CONFLICT | |
1403 | } | |
1404 | ||
156c2f8b NC |
1405 | /* This function is called once, at assembler startup time. It should |
1406 | set up all the tables, etc. that the MD part of the assembler will need. */ | |
1407 | ||
252b5132 | 1408 | void |
17a2f251 | 1409 | md_begin (void) |
252b5132 | 1410 | { |
252b5132 | 1411 | register const char *retval = NULL; |
156c2f8b | 1412 | int i = 0; |
252b5132 | 1413 | int broken = 0; |
1f25f5d3 | 1414 | |
0a44bf69 RS |
1415 | if (mips_pic != NO_PIC) |
1416 | { | |
1417 | if (g_switch_seen && g_switch_value != 0) | |
1418 | as_bad (_("-G may not be used in position-independent code")); | |
1419 | g_switch_value = 0; | |
1420 | } | |
1421 | ||
fef14a42 | 1422 | if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_arch)) |
252b5132 RH |
1423 | as_warn (_("Could not set architecture and machine")); |
1424 | ||
252b5132 RH |
1425 | op_hash = hash_new (); |
1426 | ||
1427 | for (i = 0; i < NUMOPCODES;) | |
1428 | { | |
1429 | const char *name = mips_opcodes[i].name; | |
1430 | ||
17a2f251 | 1431 | retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]); |
252b5132 RH |
1432 | if (retval != NULL) |
1433 | { | |
1434 | fprintf (stderr, _("internal error: can't hash `%s': %s\n"), | |
1435 | mips_opcodes[i].name, retval); | |
1436 | /* Probably a memory allocation problem? Give up now. */ | |
1437 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
1438 | } | |
1439 | do | |
1440 | { | |
1441 | if (mips_opcodes[i].pinfo != INSN_MACRO) | |
1442 | { | |
1443 | if (!validate_mips_insn (&mips_opcodes[i])) | |
1444 | broken = 1; | |
1e915849 RS |
1445 | if (nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0) |
1446 | { | |
1447 | create_insn (&nop_insn, mips_opcodes + i); | |
1448 | nop_insn.fixed_p = 1; | |
1449 | } | |
252b5132 RH |
1450 | } |
1451 | ++i; | |
1452 | } | |
1453 | while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name)); | |
1454 | } | |
1455 | ||
1456 | mips16_op_hash = hash_new (); | |
1457 | ||
1458 | i = 0; | |
1459 | while (i < bfd_mips16_num_opcodes) | |
1460 | { | |
1461 | const char *name = mips16_opcodes[i].name; | |
1462 | ||
17a2f251 | 1463 | retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]); |
252b5132 RH |
1464 | if (retval != NULL) |
1465 | as_fatal (_("internal: can't hash `%s': %s"), | |
1466 | mips16_opcodes[i].name, retval); | |
1467 | do | |
1468 | { | |
1469 | if (mips16_opcodes[i].pinfo != INSN_MACRO | |
1470 | && ((mips16_opcodes[i].match & mips16_opcodes[i].mask) | |
1471 | != mips16_opcodes[i].match)) | |
1472 | { | |
1473 | fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"), | |
1474 | mips16_opcodes[i].name, mips16_opcodes[i].args); | |
1475 | broken = 1; | |
1476 | } | |
1e915849 RS |
1477 | if (mips16_nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0) |
1478 | { | |
1479 | create_insn (&mips16_nop_insn, mips16_opcodes + i); | |
1480 | mips16_nop_insn.fixed_p = 1; | |
1481 | } | |
252b5132 RH |
1482 | ++i; |
1483 | } | |
1484 | while (i < bfd_mips16_num_opcodes | |
1485 | && strcmp (mips16_opcodes[i].name, name) == 0); | |
1486 | } | |
1487 | ||
1488 | if (broken) | |
1489 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
1490 | ||
1491 | /* We add all the general register names to the symbol table. This | |
1492 | helps us detect invalid uses of them. */ | |
1493 | for (i = 0; i < 32; i++) | |
1494 | { | |
1495 | char buf[5]; | |
1496 | ||
1497 | sprintf (buf, "$%d", i); | |
1498 | symbol_table_insert (symbol_new (buf, reg_section, i, | |
1499 | &zero_address_frag)); | |
1500 | } | |
76db943d TS |
1501 | symbol_table_insert (symbol_new ("$ra", reg_section, RA, |
1502 | &zero_address_frag)); | |
252b5132 RH |
1503 | symbol_table_insert (symbol_new ("$fp", reg_section, FP, |
1504 | &zero_address_frag)); | |
1505 | symbol_table_insert (symbol_new ("$sp", reg_section, SP, | |
1506 | &zero_address_frag)); | |
1507 | symbol_table_insert (symbol_new ("$gp", reg_section, GP, | |
1508 | &zero_address_frag)); | |
1509 | symbol_table_insert (symbol_new ("$at", reg_section, AT, | |
1510 | &zero_address_frag)); | |
1511 | symbol_table_insert (symbol_new ("$kt0", reg_section, KT0, | |
1512 | &zero_address_frag)); | |
1513 | symbol_table_insert (symbol_new ("$kt1", reg_section, KT1, | |
1514 | &zero_address_frag)); | |
85b51719 TS |
1515 | symbol_table_insert (symbol_new ("$zero", reg_section, ZERO, |
1516 | &zero_address_frag)); | |
252b5132 RH |
1517 | symbol_table_insert (symbol_new ("$pc", reg_section, -1, |
1518 | &zero_address_frag)); | |
1519 | ||
6047c971 AO |
1520 | /* If we don't add these register names to the symbol table, they |
1521 | may end up being added as regular symbols by operand(), and then | |
1522 | make it to the object file as undefined in case they're not | |
1523 | regarded as local symbols. They're local in o32, since `$' is a | |
1524 | local symbol prefix, but not in n32 or n64. */ | |
1525 | for (i = 0; i < 8; i++) | |
1526 | { | |
1527 | char buf[6]; | |
1528 | ||
1529 | sprintf (buf, "$fcc%i", i); | |
1530 | symbol_table_insert (symbol_new (buf, reg_section, -1, | |
1531 | &zero_address_frag)); | |
1532 | } | |
1533 | ||
7d10b47d | 1534 | mips_no_prev_insn (); |
252b5132 RH |
1535 | |
1536 | mips_gprmask = 0; | |
1537 | mips_cprmask[0] = 0; | |
1538 | mips_cprmask[1] = 0; | |
1539 | mips_cprmask[2] = 0; | |
1540 | mips_cprmask[3] = 0; | |
1541 | ||
1542 | /* set the default alignment for the text section (2**2) */ | |
1543 | record_alignment (text_section, 2); | |
1544 | ||
4d0d148d | 1545 | bfd_set_gp_size (stdoutput, g_switch_value); |
252b5132 RH |
1546 | |
1547 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
1548 | { | |
0a44bf69 RS |
1549 | /* On a native system other than VxWorks, sections must be aligned |
1550 | to 16 byte boundaries. When configured for an embedded ELF | |
1551 | target, we don't bother. */ | |
1552 | if (strcmp (TARGET_OS, "elf") != 0 | |
1553 | && strcmp (TARGET_OS, "vxworks") != 0) | |
252b5132 RH |
1554 | { |
1555 | (void) bfd_set_section_alignment (stdoutput, text_section, 4); | |
1556 | (void) bfd_set_section_alignment (stdoutput, data_section, 4); | |
1557 | (void) bfd_set_section_alignment (stdoutput, bss_section, 4); | |
1558 | } | |
1559 | ||
1560 | /* Create a .reginfo section for register masks and a .mdebug | |
1561 | section for debugging information. */ | |
1562 | { | |
1563 | segT seg; | |
1564 | subsegT subseg; | |
1565 | flagword flags; | |
1566 | segT sec; | |
1567 | ||
1568 | seg = now_seg; | |
1569 | subseg = now_subseg; | |
1570 | ||
1571 | /* The ABI says this section should be loaded so that the | |
1572 | running program can access it. However, we don't load it | |
1573 | if we are configured for an embedded target */ | |
1574 | flags = SEC_READONLY | SEC_DATA; | |
1575 | if (strcmp (TARGET_OS, "elf") != 0) | |
1576 | flags |= SEC_ALLOC | SEC_LOAD; | |
1577 | ||
316f5878 | 1578 | if (mips_abi != N64_ABI) |
252b5132 RH |
1579 | { |
1580 | sec = subseg_new (".reginfo", (subsegT) 0); | |
1581 | ||
195325d2 TS |
1582 | bfd_set_section_flags (stdoutput, sec, flags); |
1583 | bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2); | |
bdaaa2e1 | 1584 | |
252b5132 RH |
1585 | #ifdef OBJ_ELF |
1586 | mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo)); | |
1587 | #endif | |
1588 | } | |
1589 | else | |
1590 | { | |
1591 | /* The 64-bit ABI uses a .MIPS.options section rather than | |
1592 | .reginfo section. */ | |
1593 | sec = subseg_new (".MIPS.options", (subsegT) 0); | |
195325d2 TS |
1594 | bfd_set_section_flags (stdoutput, sec, flags); |
1595 | bfd_set_section_alignment (stdoutput, sec, 3); | |
252b5132 RH |
1596 | |
1597 | #ifdef OBJ_ELF | |
1598 | /* Set up the option header. */ | |
1599 | { | |
1600 | Elf_Internal_Options opthdr; | |
1601 | char *f; | |
1602 | ||
1603 | opthdr.kind = ODK_REGINFO; | |
1604 | opthdr.size = (sizeof (Elf_External_Options) | |
1605 | + sizeof (Elf64_External_RegInfo)); | |
1606 | opthdr.section = 0; | |
1607 | opthdr.info = 0; | |
1608 | f = frag_more (sizeof (Elf_External_Options)); | |
1609 | bfd_mips_elf_swap_options_out (stdoutput, &opthdr, | |
1610 | (Elf_External_Options *) f); | |
1611 | ||
1612 | mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo)); | |
1613 | } | |
1614 | #endif | |
1615 | } | |
1616 | ||
1617 | if (ECOFF_DEBUGGING) | |
1618 | { | |
1619 | sec = subseg_new (".mdebug", (subsegT) 0); | |
1620 | (void) bfd_set_section_flags (stdoutput, sec, | |
1621 | SEC_HAS_CONTENTS | SEC_READONLY); | |
1622 | (void) bfd_set_section_alignment (stdoutput, sec, 2); | |
1623 | } | |
ecb4347a | 1624 | #ifdef OBJ_ELF |
dcd410fe | 1625 | else if (OUTPUT_FLAVOR == bfd_target_elf_flavour && mips_flag_pdr) |
ecb4347a DJ |
1626 | { |
1627 | pdr_seg = subseg_new (".pdr", (subsegT) 0); | |
1628 | (void) bfd_set_section_flags (stdoutput, pdr_seg, | |
1629 | SEC_READONLY | SEC_RELOC | |
1630 | | SEC_DEBUGGING); | |
1631 | (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2); | |
1632 | } | |
252b5132 RH |
1633 | #endif |
1634 | ||
1635 | subseg_set (seg, subseg); | |
1636 | } | |
1637 | } | |
1638 | ||
1639 | if (! ECOFF_DEBUGGING) | |
1640 | md_obj_begin (); | |
71400594 RS |
1641 | |
1642 | if (mips_fix_vr4120) | |
1643 | init_vr4120_conflicts (); | |
252b5132 RH |
1644 | } |
1645 | ||
1646 | void | |
17a2f251 | 1647 | md_mips_end (void) |
252b5132 RH |
1648 | { |
1649 | if (! ECOFF_DEBUGGING) | |
1650 | md_obj_end (); | |
1651 | } | |
1652 | ||
1653 | void | |
17a2f251 | 1654 | md_assemble (char *str) |
252b5132 RH |
1655 | { |
1656 | struct mips_cl_insn insn; | |
f6688943 TS |
1657 | bfd_reloc_code_real_type unused_reloc[3] |
1658 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 RH |
1659 | |
1660 | imm_expr.X_op = O_absent; | |
5f74bc13 | 1661 | imm2_expr.X_op = O_absent; |
252b5132 | 1662 | offset_expr.X_op = O_absent; |
f6688943 TS |
1663 | imm_reloc[0] = BFD_RELOC_UNUSED; |
1664 | imm_reloc[1] = BFD_RELOC_UNUSED; | |
1665 | imm_reloc[2] = BFD_RELOC_UNUSED; | |
1666 | offset_reloc[0] = BFD_RELOC_UNUSED; | |
1667 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
1668 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
1669 | |
1670 | if (mips_opts.mips16) | |
1671 | mips16_ip (str, &insn); | |
1672 | else | |
1673 | { | |
1674 | mips_ip (str, &insn); | |
beae10d5 KH |
1675 | DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"), |
1676 | str, insn.insn_opcode)); | |
252b5132 RH |
1677 | } |
1678 | ||
1679 | if (insn_error) | |
1680 | { | |
1681 | as_bad ("%s `%s'", insn_error, str); | |
1682 | return; | |
1683 | } | |
1684 | ||
1685 | if (insn.insn_mo->pinfo == INSN_MACRO) | |
1686 | { | |
584892a6 | 1687 | macro_start (); |
252b5132 RH |
1688 | if (mips_opts.mips16) |
1689 | mips16_macro (&insn); | |
1690 | else | |
1691 | macro (&insn); | |
584892a6 | 1692 | macro_end (); |
252b5132 RH |
1693 | } |
1694 | else | |
1695 | { | |
1696 | if (imm_expr.X_op != O_absent) | |
4d7206a2 | 1697 | append_insn (&insn, &imm_expr, imm_reloc); |
252b5132 | 1698 | else if (offset_expr.X_op != O_absent) |
4d7206a2 | 1699 | append_insn (&insn, &offset_expr, offset_reloc); |
252b5132 | 1700 | else |
4d7206a2 | 1701 | append_insn (&insn, NULL, unused_reloc); |
252b5132 RH |
1702 | } |
1703 | } | |
1704 | ||
5919d012 | 1705 | /* Return true if the given relocation might need a matching %lo(). |
0a44bf69 RS |
1706 | This is only "might" because SVR4 R_MIPS_GOT16 relocations only |
1707 | need a matching %lo() when applied to local symbols. */ | |
5919d012 RS |
1708 | |
1709 | static inline bfd_boolean | |
17a2f251 | 1710 | reloc_needs_lo_p (bfd_reloc_code_real_type reloc) |
5919d012 | 1711 | { |
3b91255e RS |
1712 | return (HAVE_IN_PLACE_ADDENDS |
1713 | && (reloc == BFD_RELOC_HI16_S | |
0a44bf69 RS |
1714 | || reloc == BFD_RELOC_MIPS16_HI16_S |
1715 | /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo(); | |
1716 | all GOT16 relocations evaluate to "G". */ | |
1717 | || (reloc == BFD_RELOC_MIPS_GOT16 && mips_pic != VXWORKS_PIC))); | |
5919d012 RS |
1718 | } |
1719 | ||
1720 | /* Return true if the given fixup is followed by a matching R_MIPS_LO16 | |
1721 | relocation. */ | |
1722 | ||
1723 | static inline bfd_boolean | |
17a2f251 | 1724 | fixup_has_matching_lo_p (fixS *fixp) |
5919d012 RS |
1725 | { |
1726 | return (fixp->fx_next != NULL | |
d6f16593 MR |
1727 | && (fixp->fx_next->fx_r_type == BFD_RELOC_LO16 |
1728 | || fixp->fx_next->fx_r_type == BFD_RELOC_MIPS16_LO16) | |
5919d012 RS |
1729 | && fixp->fx_addsy == fixp->fx_next->fx_addsy |
1730 | && fixp->fx_offset == fixp->fx_next->fx_offset); | |
1731 | } | |
1732 | ||
252b5132 RH |
1733 | /* See whether instruction IP reads register REG. CLASS is the type |
1734 | of register. */ | |
1735 | ||
1736 | static int | |
71400594 | 1737 | insn_uses_reg (const struct mips_cl_insn *ip, unsigned int reg, |
17a2f251 | 1738 | enum mips_regclass class) |
252b5132 RH |
1739 | { |
1740 | if (class == MIPS16_REG) | |
1741 | { | |
1742 | assert (mips_opts.mips16); | |
1743 | reg = mips16_to_32_reg_map[reg]; | |
1744 | class = MIPS_GR_REG; | |
1745 | } | |
1746 | ||
85b51719 TS |
1747 | /* Don't report on general register ZERO, since it never changes. */ |
1748 | if (class == MIPS_GR_REG && reg == ZERO) | |
252b5132 RH |
1749 | return 0; |
1750 | ||
1751 | if (class == MIPS_FP_REG) | |
1752 | { | |
1753 | assert (! mips_opts.mips16); | |
1754 | /* If we are called with either $f0 or $f1, we must check $f0. | |
1755 | This is not optimal, because it will introduce an unnecessary | |
1756 | NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would | |
1757 | need to distinguish reading both $f0 and $f1 or just one of | |
1758 | them. Note that we don't have to check the other way, | |
1759 | because there is no instruction that sets both $f0 and $f1 | |
1760 | and requires a delay. */ | |
1761 | if ((ip->insn_mo->pinfo & INSN_READ_FPR_S) | |
bf12938e | 1762 | && ((EXTRACT_OPERAND (FS, *ip) & ~(unsigned) 1) |
252b5132 RH |
1763 | == (reg &~ (unsigned) 1))) |
1764 | return 1; | |
1765 | if ((ip->insn_mo->pinfo & INSN_READ_FPR_T) | |
bf12938e | 1766 | && ((EXTRACT_OPERAND (FT, *ip) & ~(unsigned) 1) |
252b5132 RH |
1767 | == (reg &~ (unsigned) 1))) |
1768 | return 1; | |
1769 | } | |
1770 | else if (! mips_opts.mips16) | |
1771 | { | |
1772 | if ((ip->insn_mo->pinfo & INSN_READ_GPR_S) | |
bf12938e | 1773 | && EXTRACT_OPERAND (RS, *ip) == reg) |
252b5132 RH |
1774 | return 1; |
1775 | if ((ip->insn_mo->pinfo & INSN_READ_GPR_T) | |
bf12938e | 1776 | && EXTRACT_OPERAND (RT, *ip) == reg) |
252b5132 RH |
1777 | return 1; |
1778 | } | |
1779 | else | |
1780 | { | |
1781 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_X) | |
bf12938e | 1782 | && mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, *ip)] == reg) |
252b5132 RH |
1783 | return 1; |
1784 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Y) | |
bf12938e | 1785 | && mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RY, *ip)] == reg) |
252b5132 RH |
1786 | return 1; |
1787 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Z) | |
bf12938e | 1788 | && (mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (MOVE32Z, *ip)] |
252b5132 RH |
1789 | == reg)) |
1790 | return 1; | |
1791 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_T) && reg == TREG) | |
1792 | return 1; | |
1793 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_SP) && reg == SP) | |
1794 | return 1; | |
1795 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_31) && reg == RA) | |
1796 | return 1; | |
1797 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_GPR_X) | |
bf12938e | 1798 | && MIPS16_EXTRACT_OPERAND (REGR32, *ip) == reg) |
252b5132 RH |
1799 | return 1; |
1800 | } | |
1801 | ||
1802 | return 0; | |
1803 | } | |
1804 | ||
1805 | /* This function returns true if modifying a register requires a | |
1806 | delay. */ | |
1807 | ||
1808 | static int | |
17a2f251 | 1809 | reg_needs_delay (unsigned int reg) |
252b5132 RH |
1810 | { |
1811 | unsigned long prev_pinfo; | |
1812 | ||
47e39b9d | 1813 | prev_pinfo = history[0].insn_mo->pinfo; |
252b5132 | 1814 | if (! mips_opts.noreorder |
81912461 ILT |
1815 | && (((prev_pinfo & INSN_LOAD_MEMORY_DELAY) |
1816 | && ! gpr_interlocks) | |
1817 | || ((prev_pinfo & INSN_LOAD_COPROC_DELAY) | |
1818 | && ! cop_interlocks))) | |
252b5132 | 1819 | { |
81912461 ILT |
1820 | /* A load from a coprocessor or from memory. All load delays |
1821 | delay the use of general register rt for one instruction. */ | |
bdaaa2e1 | 1822 | /* Itbl support may require additional care here. */ |
252b5132 | 1823 | know (prev_pinfo & INSN_WRITE_GPR_T); |
bf12938e | 1824 | if (reg == EXTRACT_OPERAND (RT, history[0])) |
252b5132 RH |
1825 | return 1; |
1826 | } | |
1827 | ||
1828 | return 0; | |
1829 | } | |
1830 | ||
404a8071 RS |
1831 | /* Move all labels in insn_labels to the current insertion point. */ |
1832 | ||
1833 | static void | |
1834 | mips_move_labels (void) | |
1835 | { | |
1836 | struct insn_label_list *l; | |
1837 | valueT val; | |
1838 | ||
1839 | for (l = insn_labels; l != NULL; l = l->next) | |
1840 | { | |
1841 | assert (S_GET_SEGMENT (l->label) == now_seg); | |
1842 | symbol_set_frag (l->label, frag_now); | |
1843 | val = (valueT) frag_now_fix (); | |
1844 | /* mips16 text labels are stored as odd. */ | |
1845 | if (mips_opts.mips16) | |
1846 | ++val; | |
1847 | S_SET_VALUE (l->label, val); | |
1848 | } | |
1849 | } | |
1850 | ||
252b5132 RH |
1851 | /* Mark instruction labels in mips16 mode. This permits the linker to |
1852 | handle them specially, such as generating jalx instructions when | |
1853 | needed. We also make them odd for the duration of the assembly, in | |
1854 | order to generate the right sort of code. We will make them even | |
1855 | in the adjust_symtab routine, while leaving them marked. This is | |
1856 | convenient for the debugger and the disassembler. The linker knows | |
1857 | to make them odd again. */ | |
1858 | ||
1859 | static void | |
17a2f251 | 1860 | mips16_mark_labels (void) |
252b5132 RH |
1861 | { |
1862 | if (mips_opts.mips16) | |
1863 | { | |
1864 | struct insn_label_list *l; | |
98aa84af | 1865 | valueT val; |
252b5132 RH |
1866 | |
1867 | for (l = insn_labels; l != NULL; l = l->next) | |
1868 | { | |
1869 | #ifdef OBJ_ELF | |
1870 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
1871 | S_SET_OTHER (l->label, STO_MIPS16); | |
1872 | #endif | |
98aa84af AM |
1873 | val = S_GET_VALUE (l->label); |
1874 | if ((val & 1) == 0) | |
1875 | S_SET_VALUE (l->label, val + 1); | |
252b5132 RH |
1876 | } |
1877 | } | |
1878 | } | |
1879 | ||
4d7206a2 RS |
1880 | /* End the current frag. Make it a variant frag and record the |
1881 | relaxation info. */ | |
1882 | ||
1883 | static void | |
1884 | relax_close_frag (void) | |
1885 | { | |
584892a6 | 1886 | mips_macro_warning.first_frag = frag_now; |
4d7206a2 | 1887 | frag_var (rs_machine_dependent, 0, 0, |
584892a6 | 1888 | RELAX_ENCODE (mips_relax.sizes[0], mips_relax.sizes[1]), |
4d7206a2 RS |
1889 | mips_relax.symbol, 0, (char *) mips_relax.first_fixup); |
1890 | ||
1891 | memset (&mips_relax.sizes, 0, sizeof (mips_relax.sizes)); | |
1892 | mips_relax.first_fixup = 0; | |
1893 | } | |
1894 | ||
1895 | /* Start a new relaxation sequence whose expansion depends on SYMBOL. | |
1896 | See the comment above RELAX_ENCODE for more details. */ | |
1897 | ||
1898 | static void | |
1899 | relax_start (symbolS *symbol) | |
1900 | { | |
1901 | assert (mips_relax.sequence == 0); | |
1902 | mips_relax.sequence = 1; | |
1903 | mips_relax.symbol = symbol; | |
1904 | } | |
1905 | ||
1906 | /* Start generating the second version of a relaxable sequence. | |
1907 | See the comment above RELAX_ENCODE for more details. */ | |
252b5132 RH |
1908 | |
1909 | static void | |
4d7206a2 RS |
1910 | relax_switch (void) |
1911 | { | |
1912 | assert (mips_relax.sequence == 1); | |
1913 | mips_relax.sequence = 2; | |
1914 | } | |
1915 | ||
1916 | /* End the current relaxable sequence. */ | |
1917 | ||
1918 | static void | |
1919 | relax_end (void) | |
1920 | { | |
1921 | assert (mips_relax.sequence == 2); | |
1922 | relax_close_frag (); | |
1923 | mips_relax.sequence = 0; | |
1924 | } | |
1925 | ||
71400594 RS |
1926 | /* Classify an instruction according to the FIX_VR4120_* enumeration. |
1927 | Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected | |
1928 | by VR4120 errata. */ | |
4d7206a2 | 1929 | |
71400594 RS |
1930 | static unsigned int |
1931 | classify_vr4120_insn (const char *name) | |
252b5132 | 1932 | { |
71400594 RS |
1933 | if (strncmp (name, "macc", 4) == 0) |
1934 | return FIX_VR4120_MACC; | |
1935 | if (strncmp (name, "dmacc", 5) == 0) | |
1936 | return FIX_VR4120_DMACC; | |
1937 | if (strncmp (name, "mult", 4) == 0) | |
1938 | return FIX_VR4120_MULT; | |
1939 | if (strncmp (name, "dmult", 5) == 0) | |
1940 | return FIX_VR4120_DMULT; | |
1941 | if (strstr (name, "div")) | |
1942 | return FIX_VR4120_DIV; | |
1943 | if (strcmp (name, "mtlo") == 0 || strcmp (name, "mthi") == 0) | |
1944 | return FIX_VR4120_MTHILO; | |
1945 | return NUM_FIX_VR4120_CLASSES; | |
1946 | } | |
252b5132 | 1947 | |
71400594 RS |
1948 | /* Return the number of instructions that must separate INSN1 and INSN2, |
1949 | where INSN1 is the earlier instruction. Return the worst-case value | |
1950 | for any INSN2 if INSN2 is null. */ | |
252b5132 | 1951 | |
71400594 RS |
1952 | static unsigned int |
1953 | insns_between (const struct mips_cl_insn *insn1, | |
1954 | const struct mips_cl_insn *insn2) | |
1955 | { | |
1956 | unsigned long pinfo1, pinfo2; | |
1957 | ||
1958 | /* This function needs to know which pinfo flags are set for INSN2 | |
1959 | and which registers INSN2 uses. The former is stored in PINFO2 and | |
1960 | the latter is tested via INSN2_USES_REG. If INSN2 is null, PINFO2 | |
1961 | will have every flag set and INSN2_USES_REG will always return true. */ | |
1962 | pinfo1 = insn1->insn_mo->pinfo; | |
1963 | pinfo2 = insn2 ? insn2->insn_mo->pinfo : ~0U; | |
252b5132 | 1964 | |
71400594 RS |
1965 | #define INSN2_USES_REG(REG, CLASS) \ |
1966 | (insn2 == NULL || insn_uses_reg (insn2, REG, CLASS)) | |
1967 | ||
1968 | /* For most targets, write-after-read dependencies on the HI and LO | |
1969 | registers must be separated by at least two instructions. */ | |
1970 | if (!hilo_interlocks) | |
252b5132 | 1971 | { |
71400594 RS |
1972 | if ((pinfo1 & INSN_READ_LO) && (pinfo2 & INSN_WRITE_LO)) |
1973 | return 2; | |
1974 | if ((pinfo1 & INSN_READ_HI) && (pinfo2 & INSN_WRITE_HI)) | |
1975 | return 2; | |
1976 | } | |
1977 | ||
1978 | /* If we're working around r7000 errata, there must be two instructions | |
1979 | between an mfhi or mflo and any instruction that uses the result. */ | |
1980 | if (mips_7000_hilo_fix | |
1981 | && MF_HILO_INSN (pinfo1) | |
1982 | && INSN2_USES_REG (EXTRACT_OPERAND (RD, *insn1), MIPS_GR_REG)) | |
1983 | return 2; | |
1984 | ||
1985 | /* If working around VR4120 errata, check for combinations that need | |
1986 | a single intervening instruction. */ | |
1987 | if (mips_fix_vr4120) | |
1988 | { | |
1989 | unsigned int class1, class2; | |
252b5132 | 1990 | |
71400594 RS |
1991 | class1 = classify_vr4120_insn (insn1->insn_mo->name); |
1992 | if (class1 != NUM_FIX_VR4120_CLASSES && vr4120_conflicts[class1] != 0) | |
252b5132 | 1993 | { |
71400594 RS |
1994 | if (insn2 == NULL) |
1995 | return 1; | |
1996 | class2 = classify_vr4120_insn (insn2->insn_mo->name); | |
1997 | if (vr4120_conflicts[class1] & (1 << class2)) | |
1998 | return 1; | |
252b5132 | 1999 | } |
71400594 RS |
2000 | } |
2001 | ||
2002 | if (!mips_opts.mips16) | |
2003 | { | |
2004 | /* Check for GPR or coprocessor load delays. All such delays | |
2005 | are on the RT register. */ | |
2006 | /* Itbl support may require additional care here. */ | |
2007 | if ((!gpr_interlocks && (pinfo1 & INSN_LOAD_MEMORY_DELAY)) | |
2008 | || (!cop_interlocks && (pinfo1 & INSN_LOAD_COPROC_DELAY))) | |
252b5132 | 2009 | { |
71400594 RS |
2010 | know (pinfo1 & INSN_WRITE_GPR_T); |
2011 | if (INSN2_USES_REG (EXTRACT_OPERAND (RT, *insn1), MIPS_GR_REG)) | |
2012 | return 1; | |
2013 | } | |
2014 | ||
2015 | /* Check for generic coprocessor hazards. | |
2016 | ||
2017 | This case is not handled very well. There is no special | |
2018 | knowledge of CP0 handling, and the coprocessors other than | |
2019 | the floating point unit are not distinguished at all. */ | |
2020 | /* Itbl support may require additional care here. FIXME! | |
2021 | Need to modify this to include knowledge about | |
2022 | user specified delays! */ | |
2023 | else if ((!cop_interlocks && (pinfo1 & INSN_COPROC_MOVE_DELAY)) | |
2024 | || (!cop_mem_interlocks && (pinfo1 & INSN_COPROC_MEMORY_DELAY))) | |
2025 | { | |
2026 | /* Handle cases where INSN1 writes to a known general coprocessor | |
2027 | register. There must be a one instruction delay before INSN2 | |
2028 | if INSN2 reads that register, otherwise no delay is needed. */ | |
2029 | if (pinfo1 & INSN_WRITE_FPR_T) | |
252b5132 | 2030 | { |
71400594 RS |
2031 | if (INSN2_USES_REG (EXTRACT_OPERAND (FT, *insn1), MIPS_FP_REG)) |
2032 | return 1; | |
252b5132 | 2033 | } |
71400594 | 2034 | else if (pinfo1 & INSN_WRITE_FPR_S) |
252b5132 | 2035 | { |
71400594 RS |
2036 | if (INSN2_USES_REG (EXTRACT_OPERAND (FS, *insn1), MIPS_FP_REG)) |
2037 | return 1; | |
252b5132 RH |
2038 | } |
2039 | else | |
2040 | { | |
71400594 RS |
2041 | /* Read-after-write dependencies on the control registers |
2042 | require a two-instruction gap. */ | |
2043 | if ((pinfo1 & INSN_WRITE_COND_CODE) | |
2044 | && (pinfo2 & INSN_READ_COND_CODE)) | |
2045 | return 2; | |
2046 | ||
2047 | /* We don't know exactly what INSN1 does. If INSN2 is | |
2048 | also a coprocessor instruction, assume there must be | |
2049 | a one instruction gap. */ | |
2050 | if (pinfo2 & INSN_COP) | |
2051 | return 1; | |
252b5132 RH |
2052 | } |
2053 | } | |
6b76fefe | 2054 | |
71400594 RS |
2055 | /* Check for read-after-write dependencies on the coprocessor |
2056 | control registers in cases where INSN1 does not need a general | |
2057 | coprocessor delay. This means that INSN1 is a floating point | |
2058 | comparison instruction. */ | |
2059 | /* Itbl support may require additional care here. */ | |
2060 | else if (!cop_interlocks | |
2061 | && (pinfo1 & INSN_WRITE_COND_CODE) | |
2062 | && (pinfo2 & INSN_READ_COND_CODE)) | |
2063 | return 1; | |
2064 | } | |
6b76fefe | 2065 | |
71400594 | 2066 | #undef INSN2_USES_REG |
6b76fefe | 2067 | |
71400594 RS |
2068 | return 0; |
2069 | } | |
6b76fefe | 2070 | |
7d8e00cf RS |
2071 | /* Return the number of nops that would be needed to work around the |
2072 | VR4130 mflo/mfhi errata if instruction INSN immediately followed | |
2073 | the MAX_VR4130_NOPS instructions described by HISTORY. */ | |
2074 | ||
2075 | static int | |
2076 | nops_for_vr4130 (const struct mips_cl_insn *history, | |
2077 | const struct mips_cl_insn *insn) | |
2078 | { | |
2079 | int i, j, reg; | |
2080 | ||
2081 | /* Check if the instruction writes to HI or LO. MTHI and MTLO | |
2082 | are not affected by the errata. */ | |
2083 | if (insn != 0 | |
2084 | && ((insn->insn_mo->pinfo & (INSN_WRITE_HI | INSN_WRITE_LO)) == 0 | |
2085 | || strcmp (insn->insn_mo->name, "mtlo") == 0 | |
2086 | || strcmp (insn->insn_mo->name, "mthi") == 0)) | |
2087 | return 0; | |
2088 | ||
2089 | /* Search for the first MFLO or MFHI. */ | |
2090 | for (i = 0; i < MAX_VR4130_NOPS; i++) | |
2091 | if (!history[i].noreorder_p && MF_HILO_INSN (history[i].insn_mo->pinfo)) | |
2092 | { | |
2093 | /* Extract the destination register. */ | |
2094 | if (mips_opts.mips16) | |
2095 | reg = mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, history[i])]; | |
2096 | else | |
2097 | reg = EXTRACT_OPERAND (RD, history[i]); | |
2098 | ||
2099 | /* No nops are needed if INSN reads that register. */ | |
2100 | if (insn != NULL && insn_uses_reg (insn, reg, MIPS_GR_REG)) | |
2101 | return 0; | |
2102 | ||
2103 | /* ...or if any of the intervening instructions do. */ | |
2104 | for (j = 0; j < i; j++) | |
2105 | if (insn_uses_reg (&history[j], reg, MIPS_GR_REG)) | |
2106 | return 0; | |
2107 | ||
2108 | return MAX_VR4130_NOPS - i; | |
2109 | } | |
2110 | return 0; | |
2111 | } | |
2112 | ||
71400594 RS |
2113 | /* Return the number of nops that would be needed if instruction INSN |
2114 | immediately followed the MAX_NOPS instructions given by HISTORY, | |
2115 | where HISTORY[0] is the most recent instruction. If INSN is null, | |
2116 | return the worse-case number of nops for any instruction. */ | |
bdaaa2e1 | 2117 | |
71400594 RS |
2118 | static int |
2119 | nops_for_insn (const struct mips_cl_insn *history, | |
2120 | const struct mips_cl_insn *insn) | |
2121 | { | |
2122 | int i, nops, tmp_nops; | |
bdaaa2e1 | 2123 | |
71400594 | 2124 | nops = 0; |
7d8e00cf | 2125 | for (i = 0; i < MAX_DELAY_NOPS; i++) |
71400594 RS |
2126 | if (!history[i].noreorder_p) |
2127 | { | |
2128 | tmp_nops = insns_between (history + i, insn) - i; | |
2129 | if (tmp_nops > nops) | |
2130 | nops = tmp_nops; | |
2131 | } | |
7d8e00cf RS |
2132 | |
2133 | if (mips_fix_vr4130) | |
2134 | { | |
2135 | tmp_nops = nops_for_vr4130 (history, insn); | |
2136 | if (tmp_nops > nops) | |
2137 | nops = tmp_nops; | |
2138 | } | |
2139 | ||
71400594 RS |
2140 | return nops; |
2141 | } | |
252b5132 | 2142 | |
71400594 RS |
2143 | /* The variable arguments provide NUM_INSNS extra instructions that |
2144 | might be added to HISTORY. Return the largest number of nops that | |
2145 | would be needed after the extended sequence. */ | |
252b5132 | 2146 | |
71400594 RS |
2147 | static int |
2148 | nops_for_sequence (int num_insns, const struct mips_cl_insn *history, ...) | |
2149 | { | |
2150 | va_list args; | |
2151 | struct mips_cl_insn buffer[MAX_NOPS]; | |
2152 | struct mips_cl_insn *cursor; | |
2153 | int nops; | |
2154 | ||
2155 | va_start (args, history); | |
2156 | cursor = buffer + num_insns; | |
2157 | memcpy (cursor, history, (MAX_NOPS - num_insns) * sizeof (*cursor)); | |
2158 | while (cursor > buffer) | |
2159 | *--cursor = *va_arg (args, const struct mips_cl_insn *); | |
2160 | ||
2161 | nops = nops_for_insn (buffer, NULL); | |
2162 | va_end (args); | |
2163 | return nops; | |
2164 | } | |
252b5132 | 2165 | |
71400594 RS |
2166 | /* Like nops_for_insn, but if INSN is a branch, take into account the |
2167 | worst-case delay for the branch target. */ | |
252b5132 | 2168 | |
71400594 RS |
2169 | static int |
2170 | nops_for_insn_or_target (const struct mips_cl_insn *history, | |
2171 | const struct mips_cl_insn *insn) | |
2172 | { | |
2173 | int nops, tmp_nops; | |
60b63b72 | 2174 | |
71400594 RS |
2175 | nops = nops_for_insn (history, insn); |
2176 | if (insn->insn_mo->pinfo & (INSN_UNCOND_BRANCH_DELAY | |
2177 | | INSN_COND_BRANCH_DELAY | |
2178 | | INSN_COND_BRANCH_LIKELY)) | |
2179 | { | |
2180 | tmp_nops = nops_for_sequence (2, history, insn, NOP_INSN); | |
2181 | if (tmp_nops > nops) | |
2182 | nops = tmp_nops; | |
2183 | } | |
2184 | else if (mips_opts.mips16 && (insn->insn_mo->pinfo & MIPS16_INSN_BRANCH)) | |
2185 | { | |
2186 | tmp_nops = nops_for_sequence (1, history, insn); | |
2187 | if (tmp_nops > nops) | |
2188 | nops = tmp_nops; | |
2189 | } | |
2190 | return nops; | |
2191 | } | |
2192 | ||
2193 | /* Output an instruction. IP is the instruction information. | |
2194 | ADDRESS_EXPR is an operand of the instruction to be used with | |
2195 | RELOC_TYPE. */ | |
2196 | ||
2197 | static void | |
2198 | append_insn (struct mips_cl_insn *ip, expressionS *address_expr, | |
2199 | bfd_reloc_code_real_type *reloc_type) | |
2200 | { | |
2201 | register unsigned long prev_pinfo, pinfo; | |
2202 | relax_stateT prev_insn_frag_type = 0; | |
2203 | bfd_boolean relaxed_branch = FALSE; | |
2204 | ||
2205 | /* Mark instruction labels in mips16 mode. */ | |
2206 | mips16_mark_labels (); | |
2207 | ||
2208 | prev_pinfo = history[0].insn_mo->pinfo; | |
2209 | pinfo = ip->insn_mo->pinfo; | |
2210 | ||
2211 | if (mips_relax.sequence != 2 && !mips_opts.noreorder) | |
2212 | { | |
2213 | /* There are a lot of optimizations we could do that we don't. | |
2214 | In particular, we do not, in general, reorder instructions. | |
2215 | If you use gcc with optimization, it will reorder | |
2216 | instructions and generally do much more optimization then we | |
2217 | do here; repeating all that work in the assembler would only | |
2218 | benefit hand written assembly code, and does not seem worth | |
2219 | it. */ | |
2220 | int nops = (mips_optimize == 0 | |
2221 | ? nops_for_insn (history, NULL) | |
2222 | : nops_for_insn_or_target (history, ip)); | |
2223 | if (nops > 0) | |
252b5132 RH |
2224 | { |
2225 | fragS *old_frag; | |
2226 | unsigned long old_frag_offset; | |
2227 | int i; | |
252b5132 RH |
2228 | |
2229 | old_frag = frag_now; | |
2230 | old_frag_offset = frag_now_fix (); | |
2231 | ||
2232 | for (i = 0; i < nops; i++) | |
2233 | emit_nop (); | |
2234 | ||
2235 | if (listing) | |
2236 | { | |
2237 | listing_prev_line (); | |
2238 | /* We may be at the start of a variant frag. In case we | |
2239 | are, make sure there is enough space for the frag | |
2240 | after the frags created by listing_prev_line. The | |
2241 | argument to frag_grow here must be at least as large | |
2242 | as the argument to all other calls to frag_grow in | |
2243 | this file. We don't have to worry about being in the | |
2244 | middle of a variant frag, because the variants insert | |
2245 | all needed nop instructions themselves. */ | |
2246 | frag_grow (40); | |
2247 | } | |
2248 | ||
404a8071 | 2249 | mips_move_labels (); |
252b5132 RH |
2250 | |
2251 | #ifndef NO_ECOFF_DEBUGGING | |
2252 | if (ECOFF_DEBUGGING) | |
2253 | ecoff_fix_loc (old_frag, old_frag_offset); | |
2254 | #endif | |
2255 | } | |
71400594 RS |
2256 | } |
2257 | else if (mips_relax.sequence != 2 && prev_nop_frag != NULL) | |
2258 | { | |
2259 | /* Work out how many nops in prev_nop_frag are needed by IP. */ | |
2260 | int nops = nops_for_insn_or_target (history, ip); | |
2261 | assert (nops <= prev_nop_frag_holds); | |
252b5132 | 2262 | |
71400594 RS |
2263 | /* Enforce NOPS as a minimum. */ |
2264 | if (nops > prev_nop_frag_required) | |
2265 | prev_nop_frag_required = nops; | |
252b5132 | 2266 | |
71400594 RS |
2267 | if (prev_nop_frag_holds == prev_nop_frag_required) |
2268 | { | |
2269 | /* Settle for the current number of nops. Update the history | |
2270 | accordingly (for the benefit of any future .set reorder code). */ | |
2271 | prev_nop_frag = NULL; | |
2272 | insert_into_history (prev_nop_frag_since, | |
2273 | prev_nop_frag_holds, NOP_INSN); | |
2274 | } | |
2275 | else | |
2276 | { | |
2277 | /* Allow this instruction to replace one of the nops that was | |
2278 | tentatively added to prev_nop_frag. */ | |
2279 | prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4; | |
2280 | prev_nop_frag_holds--; | |
2281 | prev_nop_frag_since++; | |
252b5132 RH |
2282 | } |
2283 | } | |
2284 | ||
58e2ea4d MR |
2285 | #ifdef OBJ_ELF |
2286 | /* The value passed to dwarf2_emit_insn is the distance between | |
2287 | the beginning of the current instruction and the address that | |
2288 | should be recorded in the debug tables. For MIPS16 debug info | |
2289 | we want to use ISA-encoded addresses, so we pass -1 for an | |
2290 | address higher by one than the current. */ | |
2291 | dwarf2_emit_insn (mips_opts.mips16 ? -1 : 0); | |
2292 | #endif | |
2293 | ||
895921c9 | 2294 | /* Record the frag type before frag_var. */ |
47e39b9d RS |
2295 | if (history[0].frag) |
2296 | prev_insn_frag_type = history[0].frag->fr_type; | |
895921c9 | 2297 | |
4d7206a2 | 2298 | if (address_expr |
0b25d3e6 | 2299 | && *reloc_type == BFD_RELOC_16_PCREL_S2 |
4a6a3df4 AO |
2300 | && (pinfo & INSN_UNCOND_BRANCH_DELAY || pinfo & INSN_COND_BRANCH_DELAY |
2301 | || pinfo & INSN_COND_BRANCH_LIKELY) | |
2302 | && mips_relax_branch | |
2303 | /* Don't try branch relaxation within .set nomacro, or within | |
2304 | .set noat if we use $at for PIC computations. If it turns | |
2305 | out that the branch was out-of-range, we'll get an error. */ | |
2306 | && !mips_opts.warn_about_macros | |
2307 | && !(mips_opts.noat && mips_pic != NO_PIC) | |
2308 | && !mips_opts.mips16) | |
2309 | { | |
895921c9 | 2310 | relaxed_branch = TRUE; |
1e915849 RS |
2311 | add_relaxed_insn (ip, (relaxed_branch_length |
2312 | (NULL, NULL, | |
2313 | (pinfo & INSN_UNCOND_BRANCH_DELAY) ? -1 | |
2314 | : (pinfo & INSN_COND_BRANCH_LIKELY) ? 1 | |
2315 | : 0)), 4, | |
2316 | RELAX_BRANCH_ENCODE | |
2317 | (pinfo & INSN_UNCOND_BRANCH_DELAY, | |
2318 | pinfo & INSN_COND_BRANCH_LIKELY, | |
2319 | pinfo & INSN_WRITE_GPR_31, | |
2320 | 0), | |
2321 | address_expr->X_add_symbol, | |
2322 | address_expr->X_add_number); | |
4a6a3df4 AO |
2323 | *reloc_type = BFD_RELOC_UNUSED; |
2324 | } | |
2325 | else if (*reloc_type > BFD_RELOC_UNUSED) | |
252b5132 RH |
2326 | { |
2327 | /* We need to set up a variant frag. */ | |
2328 | assert (mips_opts.mips16 && address_expr != NULL); | |
1e915849 RS |
2329 | add_relaxed_insn (ip, 4, 0, |
2330 | RELAX_MIPS16_ENCODE | |
2331 | (*reloc_type - BFD_RELOC_UNUSED, | |
2332 | mips16_small, mips16_ext, | |
2333 | prev_pinfo & INSN_UNCOND_BRANCH_DELAY, | |
2334 | history[0].mips16_absolute_jump_p), | |
2335 | make_expr_symbol (address_expr), 0); | |
252b5132 | 2336 | } |
252b5132 RH |
2337 | else if (mips_opts.mips16 |
2338 | && ! ip->use_extend | |
f6688943 | 2339 | && *reloc_type != BFD_RELOC_MIPS16_JMP) |
9497f5ac | 2340 | { |
b8ee1a6e DU |
2341 | if ((pinfo & INSN_UNCOND_BRANCH_DELAY) == 0) |
2342 | /* Make sure there is enough room to swap this instruction with | |
2343 | a following jump instruction. */ | |
2344 | frag_grow (6); | |
1e915849 | 2345 | add_fixed_insn (ip); |
252b5132 RH |
2346 | } |
2347 | else | |
2348 | { | |
2349 | if (mips_opts.mips16 | |
2350 | && mips_opts.noreorder | |
2351 | && (prev_pinfo & INSN_UNCOND_BRANCH_DELAY) != 0) | |
2352 | as_warn (_("extended instruction in delay slot")); | |
2353 | ||
4d7206a2 RS |
2354 | if (mips_relax.sequence) |
2355 | { | |
2356 | /* If we've reached the end of this frag, turn it into a variant | |
2357 | frag and record the information for the instructions we've | |
2358 | written so far. */ | |
2359 | if (frag_room () < 4) | |
2360 | relax_close_frag (); | |
2361 | mips_relax.sizes[mips_relax.sequence - 1] += 4; | |
2362 | } | |
2363 | ||
584892a6 RS |
2364 | if (mips_relax.sequence != 2) |
2365 | mips_macro_warning.sizes[0] += 4; | |
2366 | if (mips_relax.sequence != 1) | |
2367 | mips_macro_warning.sizes[1] += 4; | |
2368 | ||
1e915849 RS |
2369 | if (mips_opts.mips16) |
2370 | { | |
2371 | ip->fixed_p = 1; | |
2372 | ip->mips16_absolute_jump_p = (*reloc_type == BFD_RELOC_MIPS16_JMP); | |
2373 | } | |
2374 | add_fixed_insn (ip); | |
252b5132 RH |
2375 | } |
2376 | ||
01a3f561 | 2377 | if (address_expr != NULL && *reloc_type <= BFD_RELOC_UNUSED) |
252b5132 RH |
2378 | { |
2379 | if (address_expr->X_op == O_constant) | |
2380 | { | |
f17c130b | 2381 | unsigned int tmp; |
f6688943 TS |
2382 | |
2383 | switch (*reloc_type) | |
252b5132 RH |
2384 | { |
2385 | case BFD_RELOC_32: | |
2386 | ip->insn_opcode |= address_expr->X_add_number; | |
2387 | break; | |
2388 | ||
f6688943 | 2389 | case BFD_RELOC_MIPS_HIGHEST: |
f17c130b AM |
2390 | tmp = (address_expr->X_add_number + 0x800080008000ull) >> 48; |
2391 | ip->insn_opcode |= tmp & 0xffff; | |
f6688943 TS |
2392 | break; |
2393 | ||
2394 | case BFD_RELOC_MIPS_HIGHER: | |
f17c130b AM |
2395 | tmp = (address_expr->X_add_number + 0x80008000ull) >> 32; |
2396 | ip->insn_opcode |= tmp & 0xffff; | |
f6688943 TS |
2397 | break; |
2398 | ||
2399 | case BFD_RELOC_HI16_S: | |
f17c130b AM |
2400 | tmp = (address_expr->X_add_number + 0x8000) >> 16; |
2401 | ip->insn_opcode |= tmp & 0xffff; | |
f6688943 TS |
2402 | break; |
2403 | ||
2404 | case BFD_RELOC_HI16: | |
2405 | ip->insn_opcode |= (address_expr->X_add_number >> 16) & 0xffff; | |
2406 | break; | |
2407 | ||
01a3f561 | 2408 | case BFD_RELOC_UNUSED: |
252b5132 | 2409 | case BFD_RELOC_LO16: |
ed6fb7bd | 2410 | case BFD_RELOC_MIPS_GOT_DISP: |
252b5132 RH |
2411 | ip->insn_opcode |= address_expr->X_add_number & 0xffff; |
2412 | break; | |
2413 | ||
2414 | case BFD_RELOC_MIPS_JMP: | |
2415 | if ((address_expr->X_add_number & 3) != 0) | |
2416 | as_bad (_("jump to misaligned address (0x%lx)"), | |
2417 | (unsigned long) address_expr->X_add_number); | |
2418 | ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0x3ffffff; | |
2419 | break; | |
2420 | ||
2421 | case BFD_RELOC_MIPS16_JMP: | |
2422 | if ((address_expr->X_add_number & 3) != 0) | |
2423 | as_bad (_("jump to misaligned address (0x%lx)"), | |
2424 | (unsigned long) address_expr->X_add_number); | |
2425 | ip->insn_opcode |= | |
2426 | (((address_expr->X_add_number & 0x7c0000) << 3) | |
2427 | | ((address_expr->X_add_number & 0xf800000) >> 7) | |
2428 | | ((address_expr->X_add_number & 0x3fffc) >> 2)); | |
2429 | break; | |
2430 | ||
252b5132 | 2431 | case BFD_RELOC_16_PCREL_S2: |
bad36eac DJ |
2432 | if ((address_expr->X_add_number & 3) != 0) |
2433 | as_bad (_("branch to misaligned address (0x%lx)"), | |
2434 | (unsigned long) address_expr->X_add_number); | |
2435 | if (mips_relax_branch) | |
2436 | goto need_reloc; | |
2437 | if ((address_expr->X_add_number + 0x20000) & ~0x3ffff) | |
2438 | as_bad (_("branch address range overflow (0x%lx)"), | |
2439 | (unsigned long) address_expr->X_add_number); | |
2440 | ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0xffff; | |
2441 | break; | |
252b5132 RH |
2442 | |
2443 | default: | |
2444 | internalError (); | |
2445 | } | |
2446 | } | |
01a3f561 | 2447 | else if (*reloc_type < BFD_RELOC_UNUSED) |
252b5132 | 2448 | need_reloc: |
4d7206a2 RS |
2449 | { |
2450 | reloc_howto_type *howto; | |
2451 | int i; | |
34ce925e | 2452 | |
4d7206a2 RS |
2453 | /* In a compound relocation, it is the final (outermost) |
2454 | operator that determines the relocated field. */ | |
2455 | for (i = 1; i < 3; i++) | |
2456 | if (reloc_type[i] == BFD_RELOC_UNUSED) | |
2457 | break; | |
34ce925e | 2458 | |
4d7206a2 | 2459 | howto = bfd_reloc_type_lookup (stdoutput, reloc_type[i - 1]); |
1e915849 RS |
2460 | ip->fixp[0] = fix_new_exp (ip->frag, ip->where, |
2461 | bfd_get_reloc_size (howto), | |
2462 | address_expr, | |
2463 | reloc_type[0] == BFD_RELOC_16_PCREL_S2, | |
2464 | reloc_type[0]); | |
4d7206a2 RS |
2465 | |
2466 | /* These relocations can have an addend that won't fit in | |
2467 | 4 octets for 64bit assembly. */ | |
2468 | if (HAVE_64BIT_GPRS | |
2469 | && ! howto->partial_inplace | |
2470 | && (reloc_type[0] == BFD_RELOC_16 | |
2471 | || reloc_type[0] == BFD_RELOC_32 | |
2472 | || reloc_type[0] == BFD_RELOC_MIPS_JMP | |
2473 | || reloc_type[0] == BFD_RELOC_HI16_S | |
2474 | || reloc_type[0] == BFD_RELOC_LO16 | |
2475 | || reloc_type[0] == BFD_RELOC_GPREL16 | |
2476 | || reloc_type[0] == BFD_RELOC_MIPS_LITERAL | |
2477 | || reloc_type[0] == BFD_RELOC_GPREL32 | |
2478 | || reloc_type[0] == BFD_RELOC_64 | |
2479 | || reloc_type[0] == BFD_RELOC_CTOR | |
2480 | || reloc_type[0] == BFD_RELOC_MIPS_SUB | |
2481 | || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST | |
2482 | || reloc_type[0] == BFD_RELOC_MIPS_HIGHER | |
2483 | || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP | |
2484 | || reloc_type[0] == BFD_RELOC_MIPS_REL16 | |
d6f16593 MR |
2485 | || reloc_type[0] == BFD_RELOC_MIPS_RELGOT |
2486 | || reloc_type[0] == BFD_RELOC_MIPS16_GPREL | |
2487 | || reloc_type[0] == BFD_RELOC_MIPS16_HI16_S | |
2488 | || reloc_type[0] == BFD_RELOC_MIPS16_LO16)) | |
1e915849 | 2489 | ip->fixp[0]->fx_no_overflow = 1; |
4d7206a2 RS |
2490 | |
2491 | if (mips_relax.sequence) | |
2492 | { | |
2493 | if (mips_relax.first_fixup == 0) | |
1e915849 | 2494 | mips_relax.first_fixup = ip->fixp[0]; |
4d7206a2 RS |
2495 | } |
2496 | else if (reloc_needs_lo_p (*reloc_type)) | |
2497 | { | |
2498 | struct mips_hi_fixup *hi_fixup; | |
252b5132 | 2499 | |
4d7206a2 RS |
2500 | /* Reuse the last entry if it already has a matching %lo. */ |
2501 | hi_fixup = mips_hi_fixup_list; | |
2502 | if (hi_fixup == 0 | |
2503 | || !fixup_has_matching_lo_p (hi_fixup->fixp)) | |
2504 | { | |
2505 | hi_fixup = ((struct mips_hi_fixup *) | |
2506 | xmalloc (sizeof (struct mips_hi_fixup))); | |
2507 | hi_fixup->next = mips_hi_fixup_list; | |
2508 | mips_hi_fixup_list = hi_fixup; | |
252b5132 | 2509 | } |
1e915849 | 2510 | hi_fixup->fixp = ip->fixp[0]; |
4d7206a2 RS |
2511 | hi_fixup->seg = now_seg; |
2512 | } | |
f6688943 | 2513 | |
4d7206a2 RS |
2514 | /* Add fixups for the second and third relocations, if given. |
2515 | Note that the ABI allows the second relocation to be | |
2516 | against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the | |
2517 | moment we only use RSS_UNDEF, but we could add support | |
2518 | for the others if it ever becomes necessary. */ | |
2519 | for (i = 1; i < 3; i++) | |
2520 | if (reloc_type[i] != BFD_RELOC_UNUSED) | |
2521 | { | |
1e915849 RS |
2522 | ip->fixp[i] = fix_new (ip->frag, ip->where, |
2523 | ip->fixp[0]->fx_size, NULL, 0, | |
2524 | FALSE, reloc_type[i]); | |
b1dca8ee RS |
2525 | |
2526 | /* Use fx_tcbit to mark compound relocs. */ | |
1e915849 RS |
2527 | ip->fixp[0]->fx_tcbit = 1; |
2528 | ip->fixp[i]->fx_tcbit = 1; | |
4d7206a2 | 2529 | } |
252b5132 RH |
2530 | } |
2531 | } | |
1e915849 | 2532 | install_insn (ip); |
252b5132 RH |
2533 | |
2534 | /* Update the register mask information. */ | |
2535 | if (! mips_opts.mips16) | |
2536 | { | |
2537 | if (pinfo & INSN_WRITE_GPR_D) | |
bf12938e | 2538 | mips_gprmask |= 1 << EXTRACT_OPERAND (RD, *ip); |
252b5132 | 2539 | if ((pinfo & (INSN_WRITE_GPR_T | INSN_READ_GPR_T)) != 0) |
bf12938e | 2540 | mips_gprmask |= 1 << EXTRACT_OPERAND (RT, *ip); |
252b5132 | 2541 | if (pinfo & INSN_READ_GPR_S) |
bf12938e | 2542 | mips_gprmask |= 1 << EXTRACT_OPERAND (RS, *ip); |
252b5132 | 2543 | if (pinfo & INSN_WRITE_GPR_31) |
f9419b05 | 2544 | mips_gprmask |= 1 << RA; |
252b5132 | 2545 | if (pinfo & INSN_WRITE_FPR_D) |
bf12938e | 2546 | mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FD, *ip); |
252b5132 | 2547 | if ((pinfo & (INSN_WRITE_FPR_S | INSN_READ_FPR_S)) != 0) |
bf12938e | 2548 | mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FS, *ip); |
252b5132 | 2549 | if ((pinfo & (INSN_WRITE_FPR_T | INSN_READ_FPR_T)) != 0) |
bf12938e | 2550 | mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FT, *ip); |
252b5132 | 2551 | if ((pinfo & INSN_READ_FPR_R) != 0) |
bf12938e | 2552 | mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FR, *ip); |
252b5132 RH |
2553 | if (pinfo & INSN_COP) |
2554 | { | |
bdaaa2e1 KH |
2555 | /* We don't keep enough information to sort these cases out. |
2556 | The itbl support does keep this information however, although | |
2557 | we currently don't support itbl fprmats as part of the cop | |
2558 | instruction. May want to add this support in the future. */ | |
252b5132 RH |
2559 | } |
2560 | /* Never set the bit for $0, which is always zero. */ | |
beae10d5 | 2561 | mips_gprmask &= ~1 << 0; |
252b5132 RH |
2562 | } |
2563 | else | |
2564 | { | |
2565 | if (pinfo & (MIPS16_INSN_WRITE_X | MIPS16_INSN_READ_X)) | |
bf12938e | 2566 | mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (RX, *ip); |
252b5132 | 2567 | if (pinfo & (MIPS16_INSN_WRITE_Y | MIPS16_INSN_READ_Y)) |
bf12938e | 2568 | mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (RY, *ip); |
252b5132 | 2569 | if (pinfo & MIPS16_INSN_WRITE_Z) |
bf12938e | 2570 | mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (RZ, *ip); |
252b5132 RH |
2571 | if (pinfo & (MIPS16_INSN_WRITE_T | MIPS16_INSN_READ_T)) |
2572 | mips_gprmask |= 1 << TREG; | |
2573 | if (pinfo & (MIPS16_INSN_WRITE_SP | MIPS16_INSN_READ_SP)) | |
2574 | mips_gprmask |= 1 << SP; | |
2575 | if (pinfo & (MIPS16_INSN_WRITE_31 | MIPS16_INSN_READ_31)) | |
2576 | mips_gprmask |= 1 << RA; | |
2577 | if (pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
2578 | mips_gprmask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode); | |
2579 | if (pinfo & MIPS16_INSN_READ_Z) | |
bf12938e | 2580 | mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (MOVE32Z, *ip); |
252b5132 | 2581 | if (pinfo & MIPS16_INSN_READ_GPR_X) |
bf12938e | 2582 | mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (REGR32, *ip); |
252b5132 RH |
2583 | } |
2584 | ||
4d7206a2 | 2585 | if (mips_relax.sequence != 2 && !mips_opts.noreorder) |
252b5132 RH |
2586 | { |
2587 | /* Filling the branch delay slot is more complex. We try to | |
2588 | switch the branch with the previous instruction, which we can | |
2589 | do if the previous instruction does not set up a condition | |
2590 | that the branch tests and if the branch is not itself the | |
2591 | target of any branch. */ | |
2592 | if ((pinfo & INSN_UNCOND_BRANCH_DELAY) | |
2593 | || (pinfo & INSN_COND_BRANCH_DELAY)) | |
2594 | { | |
2595 | if (mips_optimize < 2 | |
2596 | /* If we have seen .set volatile or .set nomove, don't | |
2597 | optimize. */ | |
2598 | || mips_opts.nomove != 0 | |
a38419a5 RS |
2599 | /* We can't swap if the previous instruction's position |
2600 | is fixed. */ | |
2601 | || history[0].fixed_p | |
252b5132 RH |
2602 | /* If the previous previous insn was in a .set |
2603 | noreorder, we can't swap. Actually, the MIPS | |
2604 | assembler will swap in this situation. However, gcc | |
2605 | configured -with-gnu-as will generate code like | |
2606 | .set noreorder | |
2607 | lw $4,XXX | |
2608 | .set reorder | |
2609 | INSN | |
2610 | bne $4,$0,foo | |
2611 | in which we can not swap the bne and INSN. If gcc is | |
2612 | not configured -with-gnu-as, it does not output the | |
a38419a5 | 2613 | .set pseudo-ops. */ |
47e39b9d | 2614 | || history[1].noreorder_p |
252b5132 RH |
2615 | /* If the branch is itself the target of a branch, we |
2616 | can not swap. We cheat on this; all we check for is | |
2617 | whether there is a label on this instruction. If | |
2618 | there are any branches to anything other than a | |
2619 | label, users must use .set noreorder. */ | |
2620 | || insn_labels != NULL | |
895921c9 MR |
2621 | /* If the previous instruction is in a variant frag |
2622 | other than this branch's one, we cannot do the swap. | |
2623 | This does not apply to the mips16, which uses variant | |
2624 | frags for different purposes. */ | |
252b5132 | 2625 | || (! mips_opts.mips16 |
895921c9 | 2626 | && prev_insn_frag_type == rs_machine_dependent) |
71400594 RS |
2627 | /* Check for conflicts between the branch and the instructions |
2628 | before the candidate delay slot. */ | |
2629 | || nops_for_insn (history + 1, ip) > 0 | |
2630 | /* Check for conflicts between the swapped sequence and the | |
2631 | target of the branch. */ | |
2632 | || nops_for_sequence (2, history + 1, ip, history) > 0 | |
252b5132 RH |
2633 | /* We do not swap with a trap instruction, since it |
2634 | complicates trap handlers to have the trap | |
2635 | instruction be in a delay slot. */ | |
2636 | || (prev_pinfo & INSN_TRAP) | |
2637 | /* If the branch reads a register that the previous | |
2638 | instruction sets, we can not swap. */ | |
2639 | || (! mips_opts.mips16 | |
2640 | && (prev_pinfo & INSN_WRITE_GPR_T) | |
bf12938e | 2641 | && insn_uses_reg (ip, EXTRACT_OPERAND (RT, history[0]), |
252b5132 RH |
2642 | MIPS_GR_REG)) |
2643 | || (! mips_opts.mips16 | |
2644 | && (prev_pinfo & INSN_WRITE_GPR_D) | |
bf12938e | 2645 | && insn_uses_reg (ip, EXTRACT_OPERAND (RD, history[0]), |
252b5132 RH |
2646 | MIPS_GR_REG)) |
2647 | || (mips_opts.mips16 | |
2648 | && (((prev_pinfo & MIPS16_INSN_WRITE_X) | |
bf12938e RS |
2649 | && (insn_uses_reg |
2650 | (ip, MIPS16_EXTRACT_OPERAND (RX, history[0]), | |
2651 | MIPS16_REG))) | |
252b5132 | 2652 | || ((prev_pinfo & MIPS16_INSN_WRITE_Y) |
bf12938e RS |
2653 | && (insn_uses_reg |
2654 | (ip, MIPS16_EXTRACT_OPERAND (RY, history[0]), | |
2655 | MIPS16_REG))) | |
252b5132 | 2656 | || ((prev_pinfo & MIPS16_INSN_WRITE_Z) |
bf12938e RS |
2657 | && (insn_uses_reg |
2658 | (ip, MIPS16_EXTRACT_OPERAND (RZ, history[0]), | |
2659 | MIPS16_REG))) | |
252b5132 RH |
2660 | || ((prev_pinfo & MIPS16_INSN_WRITE_T) |
2661 | && insn_uses_reg (ip, TREG, MIPS_GR_REG)) | |
2662 | || ((prev_pinfo & MIPS16_INSN_WRITE_31) | |
2663 | && insn_uses_reg (ip, RA, MIPS_GR_REG)) | |
2664 | || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
2665 | && insn_uses_reg (ip, | |
47e39b9d RS |
2666 | MIPS16OP_EXTRACT_REG32R |
2667 | (history[0].insn_opcode), | |
252b5132 RH |
2668 | MIPS_GR_REG)))) |
2669 | /* If the branch writes a register that the previous | |
2670 | instruction sets, we can not swap (we know that | |
2671 | branches write only to RD or to $31). */ | |
2672 | || (! mips_opts.mips16 | |
2673 | && (prev_pinfo & INSN_WRITE_GPR_T) | |
2674 | && (((pinfo & INSN_WRITE_GPR_D) | |
bf12938e RS |
2675 | && (EXTRACT_OPERAND (RT, history[0]) |
2676 | == EXTRACT_OPERAND (RD, *ip))) | |
252b5132 | 2677 | || ((pinfo & INSN_WRITE_GPR_31) |
bf12938e | 2678 | && EXTRACT_OPERAND (RT, history[0]) == RA))) |
252b5132 RH |
2679 | || (! mips_opts.mips16 |
2680 | && (prev_pinfo & INSN_WRITE_GPR_D) | |
2681 | && (((pinfo & INSN_WRITE_GPR_D) | |
bf12938e RS |
2682 | && (EXTRACT_OPERAND (RD, history[0]) |
2683 | == EXTRACT_OPERAND (RD, *ip))) | |
252b5132 | 2684 | || ((pinfo & INSN_WRITE_GPR_31) |
bf12938e | 2685 | && EXTRACT_OPERAND (RD, history[0]) == RA))) |
252b5132 RH |
2686 | || (mips_opts.mips16 |
2687 | && (pinfo & MIPS16_INSN_WRITE_31) | |
2688 | && ((prev_pinfo & MIPS16_INSN_WRITE_31) | |
2689 | || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
47e39b9d | 2690 | && (MIPS16OP_EXTRACT_REG32R (history[0].insn_opcode) |
252b5132 RH |
2691 | == RA)))) |
2692 | /* If the branch writes a register that the previous | |
2693 | instruction reads, we can not swap (we know that | |
2694 | branches only write to RD or to $31). */ | |
2695 | || (! mips_opts.mips16 | |
2696 | && (pinfo & INSN_WRITE_GPR_D) | |
47e39b9d | 2697 | && insn_uses_reg (&history[0], |
bf12938e | 2698 | EXTRACT_OPERAND (RD, *ip), |
252b5132 RH |
2699 | MIPS_GR_REG)) |
2700 | || (! mips_opts.mips16 | |
2701 | && (pinfo & INSN_WRITE_GPR_31) | |
47e39b9d | 2702 | && insn_uses_reg (&history[0], RA, MIPS_GR_REG)) |
252b5132 RH |
2703 | || (mips_opts.mips16 |
2704 | && (pinfo & MIPS16_INSN_WRITE_31) | |
47e39b9d | 2705 | && insn_uses_reg (&history[0], RA, MIPS_GR_REG)) |
252b5132 RH |
2706 | /* If one instruction sets a condition code and the |
2707 | other one uses a condition code, we can not swap. */ | |
2708 | || ((pinfo & INSN_READ_COND_CODE) | |
2709 | && (prev_pinfo & INSN_WRITE_COND_CODE)) | |
2710 | || ((pinfo & INSN_WRITE_COND_CODE) | |
2711 | && (prev_pinfo & INSN_READ_COND_CODE)) | |
2712 | /* If the previous instruction uses the PC, we can not | |
2713 | swap. */ | |
2714 | || (mips_opts.mips16 | |
2715 | && (prev_pinfo & MIPS16_INSN_READ_PC)) | |
252b5132 RH |
2716 | /* If the previous instruction had a fixup in mips16 |
2717 | mode, we can not swap. This normally means that the | |
2718 | previous instruction was a 4 byte branch anyhow. */ | |
47e39b9d | 2719 | || (mips_opts.mips16 && history[0].fixp[0]) |
bdaaa2e1 KH |
2720 | /* If the previous instruction is a sync, sync.l, or |
2721 | sync.p, we can not swap. */ | |
f173e82e | 2722 | || (prev_pinfo & INSN_SYNC)) |
252b5132 | 2723 | { |
29024861 DU |
2724 | if (mips_opts.mips16 |
2725 | && (pinfo & INSN_UNCOND_BRANCH_DELAY) | |
2726 | && (pinfo & (MIPS16_INSN_READ_X | MIPS16_INSN_READ_31)) | |
2727 | && (mips_opts.isa == ISA_MIPS32 | |
2728 | || mips_opts.isa == ISA_MIPS32R2 | |
2729 | || mips_opts.isa == ISA_MIPS64 | |
2730 | || mips_opts.isa == ISA_MIPS64R2)) | |
2731 | { | |
2732 | /* Convert MIPS16 jr/jalr into a "compact" jump. */ | |
2733 | ip->insn_opcode |= 0x0080; | |
2734 | install_insn (ip); | |
2735 | insert_into_history (0, 1, ip); | |
2736 | } | |
2737 | else | |
2738 | { | |
2739 | /* We could do even better for unconditional branches to | |
2740 | portions of this object file; we could pick up the | |
2741 | instruction at the destination, put it in the delay | |
2742 | slot, and bump the destination address. */ | |
2743 | insert_into_history (0, 1, ip); | |
2744 | emit_nop (); | |
2745 | } | |
2746 | ||
dd22970f ILT |
2747 | if (mips_relax.sequence) |
2748 | mips_relax.sizes[mips_relax.sequence - 1] += 4; | |
252b5132 RH |
2749 | } |
2750 | else | |
2751 | { | |
2752 | /* It looks like we can actually do the swap. */ | |
1e915849 RS |
2753 | struct mips_cl_insn delay = history[0]; |
2754 | if (mips_opts.mips16) | |
252b5132 | 2755 | { |
b8ee1a6e DU |
2756 | know (delay.frag == ip->frag); |
2757 | move_insn (ip, delay.frag, delay.where); | |
2758 | move_insn (&delay, ip->frag, ip->where + insn_length (ip)); | |
1e915849 RS |
2759 | } |
2760 | else if (relaxed_branch) | |
2761 | { | |
2762 | /* Add the delay slot instruction to the end of the | |
2763 | current frag and shrink the fixed part of the | |
2764 | original frag. If the branch occupies the tail of | |
2765 | the latter, move it backwards to cover the gap. */ | |
2766 | delay.frag->fr_fix -= 4; | |
2767 | if (delay.frag == ip->frag) | |
2768 | move_insn (ip, ip->frag, ip->where - 4); | |
2769 | add_fixed_insn (&delay); | |
252b5132 RH |
2770 | } |
2771 | else | |
2772 | { | |
1e915849 RS |
2773 | move_insn (&delay, ip->frag, ip->where); |
2774 | move_insn (ip, history[0].frag, history[0].where); | |
252b5132 | 2775 | } |
1e915849 RS |
2776 | history[0] = *ip; |
2777 | delay.fixed_p = 1; | |
2778 | insert_into_history (0, 1, &delay); | |
252b5132 | 2779 | } |
252b5132 RH |
2780 | |
2781 | /* If that was an unconditional branch, forget the previous | |
2782 | insn information. */ | |
2783 | if (pinfo & INSN_UNCOND_BRANCH_DELAY) | |
7d10b47d | 2784 | mips_no_prev_insn (); |
252b5132 RH |
2785 | } |
2786 | else if (pinfo & INSN_COND_BRANCH_LIKELY) | |
2787 | { | |
2788 | /* We don't yet optimize a branch likely. What we should do | |
2789 | is look at the target, copy the instruction found there | |
2790 | into the delay slot, and increment the branch to jump to | |
2791 | the next instruction. */ | |
1e915849 | 2792 | insert_into_history (0, 1, ip); |
252b5132 | 2793 | emit_nop (); |
252b5132 RH |
2794 | } |
2795 | else | |
1e915849 | 2796 | insert_into_history (0, 1, ip); |
252b5132 | 2797 | } |
1e915849 RS |
2798 | else |
2799 | insert_into_history (0, 1, ip); | |
252b5132 RH |
2800 | |
2801 | /* We just output an insn, so the next one doesn't have a label. */ | |
2802 | mips_clear_insn_labels (); | |
252b5132 RH |
2803 | } |
2804 | ||
7d10b47d | 2805 | /* Forget that there was any previous instruction or label. */ |
252b5132 RH |
2806 | |
2807 | static void | |
7d10b47d | 2808 | mips_no_prev_insn (void) |
252b5132 | 2809 | { |
7d10b47d RS |
2810 | prev_nop_frag = NULL; |
2811 | insert_into_history (0, ARRAY_SIZE (history), NOP_INSN); | |
252b5132 RH |
2812 | mips_clear_insn_labels (); |
2813 | } | |
2814 | ||
7d10b47d RS |
2815 | /* This function must be called before we emit something other than |
2816 | instructions. It is like mips_no_prev_insn except that it inserts | |
2817 | any NOPS that might be needed by previous instructions. */ | |
252b5132 | 2818 | |
7d10b47d RS |
2819 | void |
2820 | mips_emit_delays (void) | |
252b5132 RH |
2821 | { |
2822 | if (! mips_opts.noreorder) | |
2823 | { | |
71400594 | 2824 | int nops = nops_for_insn (history, NULL); |
252b5132 RH |
2825 | if (nops > 0) |
2826 | { | |
7d10b47d RS |
2827 | while (nops-- > 0) |
2828 | add_fixed_insn (NOP_INSN); | |
2829 | mips_move_labels (); | |
2830 | } | |
2831 | } | |
2832 | mips_no_prev_insn (); | |
2833 | } | |
2834 | ||
2835 | /* Start a (possibly nested) noreorder block. */ | |
2836 | ||
2837 | static void | |
2838 | start_noreorder (void) | |
2839 | { | |
2840 | if (mips_opts.noreorder == 0) | |
2841 | { | |
2842 | unsigned int i; | |
2843 | int nops; | |
2844 | ||
2845 | /* None of the instructions before the .set noreorder can be moved. */ | |
2846 | for (i = 0; i < ARRAY_SIZE (history); i++) | |
2847 | history[i].fixed_p = 1; | |
2848 | ||
2849 | /* Insert any nops that might be needed between the .set noreorder | |
2850 | block and the previous instructions. We will later remove any | |
2851 | nops that turn out not to be needed. */ | |
2852 | nops = nops_for_insn (history, NULL); | |
2853 | if (nops > 0) | |
2854 | { | |
2855 | if (mips_optimize != 0) | |
252b5132 RH |
2856 | { |
2857 | /* Record the frag which holds the nop instructions, so | |
2858 | that we can remove them if we don't need them. */ | |
2859 | frag_grow (mips_opts.mips16 ? nops * 2 : nops * 4); | |
2860 | prev_nop_frag = frag_now; | |
2861 | prev_nop_frag_holds = nops; | |
2862 | prev_nop_frag_required = 0; | |
2863 | prev_nop_frag_since = 0; | |
2864 | } | |
2865 | ||
2866 | for (; nops > 0; --nops) | |
1e915849 | 2867 | add_fixed_insn (NOP_INSN); |
252b5132 | 2868 | |
7d10b47d RS |
2869 | /* Move on to a new frag, so that it is safe to simply |
2870 | decrease the size of prev_nop_frag. */ | |
2871 | frag_wane (frag_now); | |
2872 | frag_new (0); | |
404a8071 | 2873 | mips_move_labels (); |
252b5132 | 2874 | } |
7d10b47d RS |
2875 | mips16_mark_labels (); |
2876 | mips_clear_insn_labels (); | |
252b5132 | 2877 | } |
7d10b47d RS |
2878 | mips_opts.noreorder++; |
2879 | mips_any_noreorder = 1; | |
2880 | } | |
252b5132 | 2881 | |
7d10b47d | 2882 | /* End a nested noreorder block. */ |
252b5132 | 2883 | |
7d10b47d RS |
2884 | static void |
2885 | end_noreorder (void) | |
2886 | { | |
2887 | mips_opts.noreorder--; | |
2888 | if (mips_opts.noreorder == 0 && prev_nop_frag != NULL) | |
2889 | { | |
2890 | /* Commit to inserting prev_nop_frag_required nops and go back to | |
2891 | handling nop insertion the .set reorder way. */ | |
2892 | prev_nop_frag->fr_fix -= ((prev_nop_frag_holds - prev_nop_frag_required) | |
2893 | * (mips_opts.mips16 ? 2 : 4)); | |
2894 | insert_into_history (prev_nop_frag_since, | |
2895 | prev_nop_frag_required, NOP_INSN); | |
2896 | prev_nop_frag = NULL; | |
2897 | } | |
252b5132 RH |
2898 | } |
2899 | ||
584892a6 RS |
2900 | /* Set up global variables for the start of a new macro. */ |
2901 | ||
2902 | static void | |
2903 | macro_start (void) | |
2904 | { | |
2905 | memset (&mips_macro_warning.sizes, 0, sizeof (mips_macro_warning.sizes)); | |
2906 | mips_macro_warning.delay_slot_p = (mips_opts.noreorder | |
47e39b9d | 2907 | && (history[0].insn_mo->pinfo |
584892a6 RS |
2908 | & (INSN_UNCOND_BRANCH_DELAY |
2909 | | INSN_COND_BRANCH_DELAY | |
2910 | | INSN_COND_BRANCH_LIKELY)) != 0); | |
2911 | } | |
2912 | ||
2913 | /* Given that a macro is longer than 4 bytes, return the appropriate warning | |
2914 | for it. Return null if no warning is needed. SUBTYPE is a bitmask of | |
2915 | RELAX_DELAY_SLOT and RELAX_NOMACRO. */ | |
2916 | ||
2917 | static const char * | |
2918 | macro_warning (relax_substateT subtype) | |
2919 | { | |
2920 | if (subtype & RELAX_DELAY_SLOT) | |
2921 | return _("Macro instruction expanded into multiple instructions" | |
2922 | " in a branch delay slot"); | |
2923 | else if (subtype & RELAX_NOMACRO) | |
2924 | return _("Macro instruction expanded into multiple instructions"); | |
2925 | else | |
2926 | return 0; | |
2927 | } | |
2928 | ||
2929 | /* Finish up a macro. Emit warnings as appropriate. */ | |
2930 | ||
2931 | static void | |
2932 | macro_end (void) | |
2933 | { | |
2934 | if (mips_macro_warning.sizes[0] > 4 || mips_macro_warning.sizes[1] > 4) | |
2935 | { | |
2936 | relax_substateT subtype; | |
2937 | ||
2938 | /* Set up the relaxation warning flags. */ | |
2939 | subtype = 0; | |
2940 | if (mips_macro_warning.sizes[1] > mips_macro_warning.sizes[0]) | |
2941 | subtype |= RELAX_SECOND_LONGER; | |
2942 | if (mips_opts.warn_about_macros) | |
2943 | subtype |= RELAX_NOMACRO; | |
2944 | if (mips_macro_warning.delay_slot_p) | |
2945 | subtype |= RELAX_DELAY_SLOT; | |
2946 | ||
2947 | if (mips_macro_warning.sizes[0] > 4 && mips_macro_warning.sizes[1] > 4) | |
2948 | { | |
2949 | /* Either the macro has a single implementation or both | |
2950 | implementations are longer than 4 bytes. Emit the | |
2951 | warning now. */ | |
2952 | const char *msg = macro_warning (subtype); | |
2953 | if (msg != 0) | |
2954 | as_warn (msg); | |
2955 | } | |
2956 | else | |
2957 | { | |
2958 | /* One implementation might need a warning but the other | |
2959 | definitely doesn't. */ | |
2960 | mips_macro_warning.first_frag->fr_subtype |= subtype; | |
2961 | } | |
2962 | } | |
2963 | } | |
2964 | ||
6e1304d8 RS |
2965 | /* Read a macro's relocation codes from *ARGS and store them in *R. |
2966 | The first argument in *ARGS will be either the code for a single | |
2967 | relocation or -1 followed by the three codes that make up a | |
2968 | composite relocation. */ | |
2969 | ||
2970 | static void | |
2971 | macro_read_relocs (va_list *args, bfd_reloc_code_real_type *r) | |
2972 | { | |
2973 | int i, next; | |
2974 | ||
2975 | next = va_arg (*args, int); | |
2976 | if (next >= 0) | |
2977 | r[0] = (bfd_reloc_code_real_type) next; | |
2978 | else | |
2979 | for (i = 0; i < 3; i++) | |
2980 | r[i] = (bfd_reloc_code_real_type) va_arg (*args, int); | |
2981 | } | |
2982 | ||
252b5132 RH |
2983 | /* Build an instruction created by a macro expansion. This is passed |
2984 | a pointer to the count of instructions created so far, an | |
2985 | expression, the name of the instruction to build, an operand format | |
2986 | string, and corresponding arguments. */ | |
2987 | ||
252b5132 | 2988 | static void |
67c0d1eb | 2989 | macro_build (expressionS *ep, const char *name, const char *fmt, ...) |
252b5132 | 2990 | { |
1e915849 | 2991 | const struct mips_opcode *mo; |
252b5132 | 2992 | struct mips_cl_insn insn; |
f6688943 | 2993 | bfd_reloc_code_real_type r[3]; |
252b5132 | 2994 | va_list args; |
252b5132 | 2995 | |
252b5132 | 2996 | va_start (args, fmt); |
252b5132 | 2997 | |
252b5132 RH |
2998 | if (mips_opts.mips16) |
2999 | { | |
67c0d1eb | 3000 | mips16_macro_build (ep, name, fmt, args); |
252b5132 RH |
3001 | va_end (args); |
3002 | return; | |
3003 | } | |
3004 | ||
f6688943 TS |
3005 | r[0] = BFD_RELOC_UNUSED; |
3006 | r[1] = BFD_RELOC_UNUSED; | |
3007 | r[2] = BFD_RELOC_UNUSED; | |
1e915849 RS |
3008 | mo = (struct mips_opcode *) hash_find (op_hash, name); |
3009 | assert (mo); | |
3010 | assert (strcmp (name, mo->name) == 0); | |
3011 | ||
3012 | /* Search until we get a match for NAME. It is assumed here that | |
3013 | macros will never generate MDMX or MIPS-3D instructions. */ | |
3014 | while (strcmp (fmt, mo->args) != 0 | |
3015 | || mo->pinfo == INSN_MACRO | |
3016 | || !OPCODE_IS_MEMBER (mo, | |
3017 | (mips_opts.isa | |
9b3f89ee | 3018 | | (mips_opts.mips16 ? INSN_MIPS16 : 0) |
e16bfa71 | 3019 | | (mips_opts.ase_smartmips ? INSN_SMARTMIPS : 0)), |
fef14a42 | 3020 | mips_opts.arch) |
1e915849 RS |
3021 | || (mips_opts.arch == CPU_R4650 && (mo->pinfo & FP_D) != 0)) |
3022 | { | |
3023 | ++mo; | |
3024 | assert (mo->name); | |
3025 | assert (strcmp (name, mo->name) == 0); | |
252b5132 RH |
3026 | } |
3027 | ||
1e915849 | 3028 | create_insn (&insn, mo); |
252b5132 RH |
3029 | for (;;) |
3030 | { | |
3031 | switch (*fmt++) | |
3032 | { | |
3033 | case '\0': | |
3034 | break; | |
3035 | ||
3036 | case ',': | |
3037 | case '(': | |
3038 | case ')': | |
3039 | continue; | |
3040 | ||
5f74bc13 CD |
3041 | case '+': |
3042 | switch (*fmt++) | |
3043 | { | |
3044 | case 'A': | |
3045 | case 'E': | |
bf12938e | 3046 | INSERT_OPERAND (SHAMT, insn, va_arg (args, int)); |
5f74bc13 CD |
3047 | continue; |
3048 | ||
3049 | case 'B': | |
3050 | case 'F': | |
3051 | /* Note that in the macro case, these arguments are already | |
3052 | in MSB form. (When handling the instruction in the | |
3053 | non-macro case, these arguments are sizes from which | |
3054 | MSB values must be calculated.) */ | |
bf12938e | 3055 | INSERT_OPERAND (INSMSB, insn, va_arg (args, int)); |
5f74bc13 CD |
3056 | continue; |
3057 | ||
3058 | case 'C': | |
3059 | case 'G': | |
3060 | case 'H': | |
3061 | /* Note that in the macro case, these arguments are already | |
3062 | in MSBD form. (When handling the instruction in the | |
3063 | non-macro case, these arguments are sizes from which | |
3064 | MSBD values must be calculated.) */ | |
bf12938e | 3065 | INSERT_OPERAND (EXTMSBD, insn, va_arg (args, int)); |
5f74bc13 CD |
3066 | continue; |
3067 | ||
3068 | default: | |
3069 | internalError (); | |
3070 | } | |
3071 | continue; | |
3072 | ||
252b5132 RH |
3073 | case 't': |
3074 | case 'w': | |
3075 | case 'E': | |
bf12938e | 3076 | INSERT_OPERAND (RT, insn, va_arg (args, int)); |
252b5132 RH |
3077 | continue; |
3078 | ||
3079 | case 'c': | |
bf12938e | 3080 | INSERT_OPERAND (CODE, insn, va_arg (args, int)); |
38487616 TS |
3081 | continue; |
3082 | ||
252b5132 RH |
3083 | case 'T': |
3084 | case 'W': | |
bf12938e | 3085 | INSERT_OPERAND (FT, insn, va_arg (args, int)); |
252b5132 RH |
3086 | continue; |
3087 | ||
3088 | case 'd': | |
3089 | case 'G': | |
af7ee8bf | 3090 | case 'K': |
bf12938e | 3091 | INSERT_OPERAND (RD, insn, va_arg (args, int)); |
252b5132 RH |
3092 | continue; |
3093 | ||
4372b673 NC |
3094 | case 'U': |
3095 | { | |
3096 | int tmp = va_arg (args, int); | |
3097 | ||
bf12938e RS |
3098 | INSERT_OPERAND (RT, insn, tmp); |
3099 | INSERT_OPERAND (RD, insn, tmp); | |
beae10d5 | 3100 | continue; |
4372b673 NC |
3101 | } |
3102 | ||
252b5132 RH |
3103 | case 'V': |
3104 | case 'S': | |
bf12938e | 3105 | INSERT_OPERAND (FS, insn, va_arg (args, int)); |
252b5132 RH |
3106 | continue; |
3107 | ||
3108 | case 'z': | |
3109 | continue; | |
3110 | ||
3111 | case '<': | |
bf12938e | 3112 | INSERT_OPERAND (SHAMT, insn, va_arg (args, int)); |
252b5132 RH |
3113 | continue; |
3114 | ||
3115 | case 'D': | |
bf12938e | 3116 | INSERT_OPERAND (FD, insn, va_arg (args, int)); |
252b5132 RH |
3117 | continue; |
3118 | ||
3119 | case 'B': | |
bf12938e | 3120 | INSERT_OPERAND (CODE20, insn, va_arg (args, int)); |
252b5132 RH |
3121 | continue; |
3122 | ||
4372b673 | 3123 | case 'J': |
bf12938e | 3124 | INSERT_OPERAND (CODE19, insn, va_arg (args, int)); |
4372b673 NC |
3125 | continue; |
3126 | ||
252b5132 | 3127 | case 'q': |
bf12938e | 3128 | INSERT_OPERAND (CODE2, insn, va_arg (args, int)); |
252b5132 RH |
3129 | continue; |
3130 | ||
3131 | case 'b': | |
3132 | case 's': | |
3133 | case 'r': | |
3134 | case 'v': | |
bf12938e | 3135 | INSERT_OPERAND (RS, insn, va_arg (args, int)); |
252b5132 RH |
3136 | continue; |
3137 | ||
3138 | case 'i': | |
3139 | case 'j': | |
3140 | case 'o': | |
6e1304d8 | 3141 | macro_read_relocs (&args, r); |
cdf6fd85 | 3142 | assert (*r == BFD_RELOC_GPREL16 |
f6688943 TS |
3143 | || *r == BFD_RELOC_MIPS_LITERAL |
3144 | || *r == BFD_RELOC_MIPS_HIGHER | |
3145 | || *r == BFD_RELOC_HI16_S | |
3146 | || *r == BFD_RELOC_LO16 | |
3147 | || *r == BFD_RELOC_MIPS_GOT16 | |
3148 | || *r == BFD_RELOC_MIPS_CALL16 | |
438c16b8 TS |
3149 | || *r == BFD_RELOC_MIPS_GOT_DISP |
3150 | || *r == BFD_RELOC_MIPS_GOT_PAGE | |
3151 | || *r == BFD_RELOC_MIPS_GOT_OFST | |
f6688943 | 3152 | || *r == BFD_RELOC_MIPS_GOT_LO16 |
3e722fb5 | 3153 | || *r == BFD_RELOC_MIPS_CALL_LO16); |
252b5132 RH |
3154 | continue; |
3155 | ||
3156 | case 'u': | |
6e1304d8 | 3157 | macro_read_relocs (&args, r); |
252b5132 RH |
3158 | assert (ep != NULL |
3159 | && (ep->X_op == O_constant | |
3160 | || (ep->X_op == O_symbol | |
f6688943 TS |
3161 | && (*r == BFD_RELOC_MIPS_HIGHEST |
3162 | || *r == BFD_RELOC_HI16_S | |
3163 | || *r == BFD_RELOC_HI16 | |
3164 | || *r == BFD_RELOC_GPREL16 | |
3165 | || *r == BFD_RELOC_MIPS_GOT_HI16 | |
3e722fb5 | 3166 | || *r == BFD_RELOC_MIPS_CALL_HI16)))); |
252b5132 RH |
3167 | continue; |
3168 | ||
3169 | case 'p': | |
3170 | assert (ep != NULL); | |
bad36eac | 3171 | |
252b5132 RH |
3172 | /* |
3173 | * This allows macro() to pass an immediate expression for | |
3174 | * creating short branches without creating a symbol. | |
bad36eac DJ |
3175 | * |
3176 | * We don't allow branch relaxation for these branches, as | |
3177 | * they should only appear in ".set nomacro" anyway. | |
252b5132 RH |
3178 | */ |
3179 | if (ep->X_op == O_constant) | |
3180 | { | |
bad36eac DJ |
3181 | if ((ep->X_add_number & 3) != 0) |
3182 | as_bad (_("branch to misaligned address (0x%lx)"), | |
3183 | (unsigned long) ep->X_add_number); | |
3184 | if ((ep->X_add_number + 0x20000) & ~0x3ffff) | |
3185 | as_bad (_("branch address range overflow (0x%lx)"), | |
3186 | (unsigned long) ep->X_add_number); | |
252b5132 RH |
3187 | insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff; |
3188 | ep = NULL; | |
3189 | } | |
3190 | else | |
0b25d3e6 | 3191 | *r = BFD_RELOC_16_PCREL_S2; |
252b5132 RH |
3192 | continue; |
3193 | ||
3194 | case 'a': | |
3195 | assert (ep != NULL); | |
f6688943 | 3196 | *r = BFD_RELOC_MIPS_JMP; |
252b5132 RH |
3197 | continue; |
3198 | ||
3199 | case 'C': | |
3200 | insn.insn_opcode |= va_arg (args, unsigned long); | |
3201 | continue; | |
3202 | ||
d43b4baf TS |
3203 | case 'k': |
3204 | insn.insn_opcode |= va_arg (args, unsigned long) << OP_SH_CACHE; | |
3205 | continue; | |
3206 | ||
252b5132 RH |
3207 | default: |
3208 | internalError (); | |
3209 | } | |
3210 | break; | |
3211 | } | |
3212 | va_end (args); | |
f6688943 | 3213 | assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
252b5132 | 3214 | |
4d7206a2 | 3215 | append_insn (&insn, ep, r); |
252b5132 RH |
3216 | } |
3217 | ||
3218 | static void | |
67c0d1eb | 3219 | mips16_macro_build (expressionS *ep, const char *name, const char *fmt, |
17a2f251 | 3220 | va_list args) |
252b5132 | 3221 | { |
1e915849 | 3222 | struct mips_opcode *mo; |
252b5132 | 3223 | struct mips_cl_insn insn; |
f6688943 TS |
3224 | bfd_reloc_code_real_type r[3] |
3225 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 3226 | |
1e915849 RS |
3227 | mo = (struct mips_opcode *) hash_find (mips16_op_hash, name); |
3228 | assert (mo); | |
3229 | assert (strcmp (name, mo->name) == 0); | |
252b5132 | 3230 | |
1e915849 | 3231 | while (strcmp (fmt, mo->args) != 0 || mo->pinfo == INSN_MACRO) |
252b5132 | 3232 | { |
1e915849 RS |
3233 | ++mo; |
3234 | assert (mo->name); | |
3235 | assert (strcmp (name, mo->name) == 0); | |
252b5132 RH |
3236 | } |
3237 | ||
1e915849 | 3238 | create_insn (&insn, mo); |
252b5132 RH |
3239 | for (;;) |
3240 | { | |
3241 | int c; | |
3242 | ||
3243 | c = *fmt++; | |
3244 | switch (c) | |
3245 | { | |
3246 | case '\0': | |
3247 | break; | |
3248 | ||
3249 | case ',': | |
3250 | case '(': | |
3251 | case ')': | |
3252 | continue; | |
3253 | ||
3254 | case 'y': | |
3255 | case 'w': | |
bf12938e | 3256 | MIPS16_INSERT_OPERAND (RY, insn, va_arg (args, int)); |
252b5132 RH |
3257 | continue; |
3258 | ||
3259 | case 'x': | |
3260 | case 'v': | |
bf12938e | 3261 | MIPS16_INSERT_OPERAND (RX, insn, va_arg (args, int)); |
252b5132 RH |
3262 | continue; |
3263 | ||
3264 | case 'z': | |
bf12938e | 3265 | MIPS16_INSERT_OPERAND (RZ, insn, va_arg (args, int)); |
252b5132 RH |
3266 | continue; |
3267 | ||
3268 | case 'Z': | |
bf12938e | 3269 | MIPS16_INSERT_OPERAND (MOVE32Z, insn, va_arg (args, int)); |
252b5132 RH |
3270 | continue; |
3271 | ||
3272 | case '0': | |
3273 | case 'S': | |
3274 | case 'P': | |
3275 | case 'R': | |
3276 | continue; | |
3277 | ||
3278 | case 'X': | |
bf12938e | 3279 | MIPS16_INSERT_OPERAND (REGR32, insn, va_arg (args, int)); |
252b5132 RH |
3280 | continue; |
3281 | ||
3282 | case 'Y': | |
3283 | { | |
3284 | int regno; | |
3285 | ||
3286 | regno = va_arg (args, int); | |
3287 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); | |
3288 | insn.insn_opcode |= regno << MIPS16OP_SH_REG32R; | |
3289 | } | |
3290 | continue; | |
3291 | ||
3292 | case '<': | |
3293 | case '>': | |
3294 | case '4': | |
3295 | case '5': | |
3296 | case 'H': | |
3297 | case 'W': | |
3298 | case 'D': | |
3299 | case 'j': | |
3300 | case '8': | |
3301 | case 'V': | |
3302 | case 'C': | |
3303 | case 'U': | |
3304 | case 'k': | |
3305 | case 'K': | |
3306 | case 'p': | |
3307 | case 'q': | |
3308 | { | |
3309 | assert (ep != NULL); | |
3310 | ||
3311 | if (ep->X_op != O_constant) | |
874e8986 | 3312 | *r = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
3313 | else |
3314 | { | |
b34976b6 AM |
3315 | mips16_immed (NULL, 0, c, ep->X_add_number, FALSE, FALSE, |
3316 | FALSE, &insn.insn_opcode, &insn.use_extend, | |
c4e7957c | 3317 | &insn.extend); |
252b5132 | 3318 | ep = NULL; |
f6688943 | 3319 | *r = BFD_RELOC_UNUSED; |
252b5132 RH |
3320 | } |
3321 | } | |
3322 | continue; | |
3323 | ||
3324 | case '6': | |
bf12938e | 3325 | MIPS16_INSERT_OPERAND (IMM6, insn, va_arg (args, int)); |
252b5132 RH |
3326 | continue; |
3327 | } | |
3328 | ||
3329 | break; | |
3330 | } | |
3331 | ||
f6688943 | 3332 | assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
252b5132 | 3333 | |
4d7206a2 | 3334 | append_insn (&insn, ep, r); |
252b5132 RH |
3335 | } |
3336 | ||
2051e8c4 MR |
3337 | /* |
3338 | * Sign-extend 32-bit mode constants that have bit 31 set and all | |
3339 | * higher bits unset. | |
3340 | */ | |
9f872bbe | 3341 | static void |
2051e8c4 MR |
3342 | normalize_constant_expr (expressionS *ex) |
3343 | { | |
9ee2a2d4 | 3344 | if (ex->X_op == O_constant |
2051e8c4 MR |
3345 | && IS_ZEXT_32BIT_NUM (ex->X_add_number)) |
3346 | ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000) | |
3347 | - 0x80000000); | |
3348 | } | |
3349 | ||
3350 | /* | |
3351 | * Sign-extend 32-bit mode address offsets that have bit 31 set and | |
3352 | * all higher bits unset. | |
3353 | */ | |
3354 | static void | |
3355 | normalize_address_expr (expressionS *ex) | |
3356 | { | |
3357 | if (((ex->X_op == O_constant && HAVE_32BIT_ADDRESSES) | |
3358 | || (ex->X_op == O_symbol && HAVE_32BIT_SYMBOLS)) | |
3359 | && IS_ZEXT_32BIT_NUM (ex->X_add_number)) | |
3360 | ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000) | |
3361 | - 0x80000000); | |
3362 | } | |
3363 | ||
438c16b8 TS |
3364 | /* |
3365 | * Generate a "jalr" instruction with a relocation hint to the called | |
3366 | * function. This occurs in NewABI PIC code. | |
3367 | */ | |
3368 | static void | |
67c0d1eb | 3369 | macro_build_jalr (expressionS *ep) |
438c16b8 | 3370 | { |
685736be | 3371 | char *f = NULL; |
b34976b6 | 3372 | |
438c16b8 | 3373 | if (HAVE_NEWABI) |
f21f8242 | 3374 | { |
cc3d92a5 | 3375 | frag_grow (8); |
f21f8242 AO |
3376 | f = frag_more (0); |
3377 | } | |
67c0d1eb | 3378 | macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG); |
438c16b8 | 3379 | if (HAVE_NEWABI) |
f21f8242 | 3380 | fix_new_exp (frag_now, f - frag_now->fr_literal, |
a105a300 | 3381 | 4, ep, FALSE, BFD_RELOC_MIPS_JALR); |
438c16b8 TS |
3382 | } |
3383 | ||
252b5132 RH |
3384 | /* |
3385 | * Generate a "lui" instruction. | |
3386 | */ | |
3387 | static void | |
67c0d1eb | 3388 | macro_build_lui (expressionS *ep, int regnum) |
252b5132 RH |
3389 | { |
3390 | expressionS high_expr; | |
1e915849 | 3391 | const struct mips_opcode *mo; |
252b5132 | 3392 | struct mips_cl_insn insn; |
f6688943 TS |
3393 | bfd_reloc_code_real_type r[3] |
3394 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
5a38dc70 AM |
3395 | const char *name = "lui"; |
3396 | const char *fmt = "t,u"; | |
252b5132 RH |
3397 | |
3398 | assert (! mips_opts.mips16); | |
3399 | ||
4d7206a2 | 3400 | high_expr = *ep; |
252b5132 RH |
3401 | |
3402 | if (high_expr.X_op == O_constant) | |
3403 | { | |
3404 | /* we can compute the instruction now without a relocation entry */ | |
e7d556df TS |
3405 | high_expr.X_add_number = ((high_expr.X_add_number + 0x8000) |
3406 | >> 16) & 0xffff; | |
f6688943 | 3407 | *r = BFD_RELOC_UNUSED; |
252b5132 | 3408 | } |
78e1bb40 | 3409 | else |
252b5132 RH |
3410 | { |
3411 | assert (ep->X_op == O_symbol); | |
bbe506e8 TS |
3412 | /* _gp_disp is a special case, used from s_cpload. |
3413 | __gnu_local_gp is used if mips_no_shared. */ | |
252b5132 | 3414 | assert (mips_pic == NO_PIC |
78e1bb40 | 3415 | || (! HAVE_NEWABI |
aa6975fb ILT |
3416 | && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0) |
3417 | || (! mips_in_shared | |
bbe506e8 TS |
3418 | && strcmp (S_GET_NAME (ep->X_add_symbol), |
3419 | "__gnu_local_gp") == 0)); | |
f6688943 | 3420 | *r = BFD_RELOC_HI16_S; |
252b5132 RH |
3421 | } |
3422 | ||
1e915849 RS |
3423 | mo = hash_find (op_hash, name); |
3424 | assert (strcmp (name, mo->name) == 0); | |
3425 | assert (strcmp (fmt, mo->args) == 0); | |
3426 | create_insn (&insn, mo); | |
252b5132 | 3427 | |
bf12938e RS |
3428 | insn.insn_opcode = insn.insn_mo->match; |
3429 | INSERT_OPERAND (RT, insn, regnum); | |
f6688943 | 3430 | if (*r == BFD_RELOC_UNUSED) |
252b5132 RH |
3431 | { |
3432 | insn.insn_opcode |= high_expr.X_add_number; | |
4d7206a2 | 3433 | append_insn (&insn, NULL, r); |
252b5132 RH |
3434 | } |
3435 | else | |
4d7206a2 | 3436 | append_insn (&insn, &high_expr, r); |
252b5132 RH |
3437 | } |
3438 | ||
885add95 CD |
3439 | /* Generate a sequence of instructions to do a load or store from a constant |
3440 | offset off of a base register (breg) into/from a target register (treg), | |
3441 | using AT if necessary. */ | |
3442 | static void | |
67c0d1eb RS |
3443 | macro_build_ldst_constoffset (expressionS *ep, const char *op, |
3444 | int treg, int breg, int dbl) | |
885add95 CD |
3445 | { |
3446 | assert (ep->X_op == O_constant); | |
3447 | ||
256ab948 | 3448 | /* Sign-extending 32-bit constants makes their handling easier. */ |
2051e8c4 MR |
3449 | if (!dbl) |
3450 | normalize_constant_expr (ep); | |
256ab948 | 3451 | |
67c1ffbe | 3452 | /* Right now, this routine can only handle signed 32-bit constants. */ |
ecd13cd3 | 3453 | if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000)) |
885add95 CD |
3454 | as_warn (_("operand overflow")); |
3455 | ||
3456 | if (IS_SEXT_16BIT_NUM(ep->X_add_number)) | |
3457 | { | |
3458 | /* Signed 16-bit offset will fit in the op. Easy! */ | |
67c0d1eb | 3459 | macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
885add95 CD |
3460 | } |
3461 | else | |
3462 | { | |
3463 | /* 32-bit offset, need multiple instructions and AT, like: | |
3464 | lui $tempreg,const_hi (BFD_RELOC_HI16_S) | |
3465 | addu $tempreg,$tempreg,$breg | |
3466 | <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16) | |
3467 | to handle the complete offset. */ | |
67c0d1eb RS |
3468 | macro_build_lui (ep, AT); |
3469 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); | |
3470 | macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, AT); | |
885add95 CD |
3471 | |
3472 | if (mips_opts.noat) | |
8fc2e39e | 3473 | as_bad (_("Macro used $at after \".set noat\"")); |
885add95 CD |
3474 | } |
3475 | } | |
3476 | ||
252b5132 RH |
3477 | /* set_at() |
3478 | * Generates code to set the $at register to true (one) | |
3479 | * if reg is less than the immediate expression. | |
3480 | */ | |
3481 | static void | |
67c0d1eb | 3482 | set_at (int reg, int unsignedp) |
252b5132 RH |
3483 | { |
3484 | if (imm_expr.X_op == O_constant | |
3485 | && imm_expr.X_add_number >= -0x8000 | |
3486 | && imm_expr.X_add_number < 0x8000) | |
67c0d1eb RS |
3487 | macro_build (&imm_expr, unsignedp ? "sltiu" : "slti", "t,r,j", |
3488 | AT, reg, BFD_RELOC_LO16); | |
252b5132 RH |
3489 | else |
3490 | { | |
67c0d1eb RS |
3491 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
3492 | macro_build (NULL, unsignedp ? "sltu" : "slt", "d,v,t", AT, reg, AT); | |
252b5132 RH |
3493 | } |
3494 | } | |
3495 | ||
3496 | /* Warn if an expression is not a constant. */ | |
3497 | ||
3498 | static void | |
17a2f251 | 3499 | check_absolute_expr (struct mips_cl_insn *ip, expressionS *ex) |
252b5132 RH |
3500 | { |
3501 | if (ex->X_op == O_big) | |
3502 | as_bad (_("unsupported large constant")); | |
3503 | else if (ex->X_op != O_constant) | |
9ee2a2d4 MR |
3504 | as_bad (_("Instruction %s requires absolute expression"), |
3505 | ip->insn_mo->name); | |
13757d0c | 3506 | |
9ee2a2d4 MR |
3507 | if (HAVE_32BIT_GPRS) |
3508 | normalize_constant_expr (ex); | |
252b5132 RH |
3509 | } |
3510 | ||
3511 | /* Count the leading zeroes by performing a binary chop. This is a | |
3512 | bulky bit of source, but performance is a LOT better for the | |
3513 | majority of values than a simple loop to count the bits: | |
3514 | for (lcnt = 0; (lcnt < 32); lcnt++) | |
3515 | if ((v) & (1 << (31 - lcnt))) | |
3516 | break; | |
3517 | However it is not code size friendly, and the gain will drop a bit | |
3518 | on certain cached systems. | |
3519 | */ | |
3520 | #define COUNT_TOP_ZEROES(v) \ | |
3521 | (((v) & ~0xffff) == 0 \ | |
3522 | ? ((v) & ~0xff) == 0 \ | |
3523 | ? ((v) & ~0xf) == 0 \ | |
3524 | ? ((v) & ~0x3) == 0 \ | |
3525 | ? ((v) & ~0x1) == 0 \ | |
3526 | ? !(v) \ | |
3527 | ? 32 \ | |
3528 | : 31 \ | |
3529 | : 30 \ | |
3530 | : ((v) & ~0x7) == 0 \ | |
3531 | ? 29 \ | |
3532 | : 28 \ | |
3533 | : ((v) & ~0x3f) == 0 \ | |
3534 | ? ((v) & ~0x1f) == 0 \ | |
3535 | ? 27 \ | |
3536 | : 26 \ | |
3537 | : ((v) & ~0x7f) == 0 \ | |
3538 | ? 25 \ | |
3539 | : 24 \ | |
3540 | : ((v) & ~0xfff) == 0 \ | |
3541 | ? ((v) & ~0x3ff) == 0 \ | |
3542 | ? ((v) & ~0x1ff) == 0 \ | |
3543 | ? 23 \ | |
3544 | : 22 \ | |
3545 | : ((v) & ~0x7ff) == 0 \ | |
3546 | ? 21 \ | |
3547 | : 20 \ | |
3548 | : ((v) & ~0x3fff) == 0 \ | |
3549 | ? ((v) & ~0x1fff) == 0 \ | |
3550 | ? 19 \ | |
3551 | : 18 \ | |
3552 | : ((v) & ~0x7fff) == 0 \ | |
3553 | ? 17 \ | |
3554 | : 16 \ | |
3555 | : ((v) & ~0xffffff) == 0 \ | |
3556 | ? ((v) & ~0xfffff) == 0 \ | |
3557 | ? ((v) & ~0x3ffff) == 0 \ | |
3558 | ? ((v) & ~0x1ffff) == 0 \ | |
3559 | ? 15 \ | |
3560 | : 14 \ | |
3561 | : ((v) & ~0x7ffff) == 0 \ | |
3562 | ? 13 \ | |
3563 | : 12 \ | |
3564 | : ((v) & ~0x3fffff) == 0 \ | |
3565 | ? ((v) & ~0x1fffff) == 0 \ | |
3566 | ? 11 \ | |
3567 | : 10 \ | |
3568 | : ((v) & ~0x7fffff) == 0 \ | |
3569 | ? 9 \ | |
3570 | : 8 \ | |
3571 | : ((v) & ~0xfffffff) == 0 \ | |
3572 | ? ((v) & ~0x3ffffff) == 0 \ | |
3573 | ? ((v) & ~0x1ffffff) == 0 \ | |
3574 | ? 7 \ | |
3575 | : 6 \ | |
3576 | : ((v) & ~0x7ffffff) == 0 \ | |
3577 | ? 5 \ | |
3578 | : 4 \ | |
3579 | : ((v) & ~0x3fffffff) == 0 \ | |
3580 | ? ((v) & ~0x1fffffff) == 0 \ | |
3581 | ? 3 \ | |
3582 | : 2 \ | |
3583 | : ((v) & ~0x7fffffff) == 0 \ | |
3584 | ? 1 \ | |
3585 | : 0) | |
3586 | ||
3587 | /* load_register() | |
67c1ffbe | 3588 | * This routine generates the least number of instructions necessary to load |
252b5132 RH |
3589 | * an absolute expression value into a register. |
3590 | */ | |
3591 | static void | |
67c0d1eb | 3592 | load_register (int reg, expressionS *ep, int dbl) |
252b5132 RH |
3593 | { |
3594 | int freg; | |
3595 | expressionS hi32, lo32; | |
3596 | ||
3597 | if (ep->X_op != O_big) | |
3598 | { | |
3599 | assert (ep->X_op == O_constant); | |
256ab948 TS |
3600 | |
3601 | /* Sign-extending 32-bit constants makes their handling easier. */ | |
2051e8c4 MR |
3602 | if (!dbl) |
3603 | normalize_constant_expr (ep); | |
256ab948 TS |
3604 | |
3605 | if (IS_SEXT_16BIT_NUM (ep->X_add_number)) | |
252b5132 RH |
3606 | { |
3607 | /* We can handle 16 bit signed values with an addiu to | |
3608 | $zero. No need to ever use daddiu here, since $zero and | |
3609 | the result are always correct in 32 bit mode. */ | |
67c0d1eb | 3610 | macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
3611 | return; |
3612 | } | |
3613 | else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000) | |
3614 | { | |
3615 | /* We can handle 16 bit unsigned values with an ori to | |
3616 | $zero. */ | |
67c0d1eb | 3617 | macro_build (ep, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
3618 | return; |
3619 | } | |
256ab948 | 3620 | else if ((IS_SEXT_32BIT_NUM (ep->X_add_number))) |
252b5132 RH |
3621 | { |
3622 | /* 32 bit values require an lui. */ | |
67c0d1eb | 3623 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_HI16); |
252b5132 | 3624 | if ((ep->X_add_number & 0xffff) != 0) |
67c0d1eb | 3625 | macro_build (ep, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16); |
252b5132 RH |
3626 | return; |
3627 | } | |
3628 | } | |
3629 | ||
3630 | /* The value is larger than 32 bits. */ | |
3631 | ||
2051e8c4 | 3632 | if (!dbl || HAVE_32BIT_GPRS) |
252b5132 | 3633 | { |
55e08f71 NC |
3634 | char value[32]; |
3635 | ||
3636 | sprintf_vma (value, ep->X_add_number); | |
20e1fcfd | 3637 | as_bad (_("Number (0x%s) larger than 32 bits"), value); |
67c0d1eb | 3638 | macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
3639 | return; |
3640 | } | |
3641 | ||
3642 | if (ep->X_op != O_big) | |
3643 | { | |
3644 | hi32 = *ep; | |
3645 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
3646 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
3647 | hi32.X_add_number &= 0xffffffff; | |
3648 | lo32 = *ep; | |
3649 | lo32.X_add_number &= 0xffffffff; | |
3650 | } | |
3651 | else | |
3652 | { | |
3653 | assert (ep->X_add_number > 2); | |
3654 | if (ep->X_add_number == 3) | |
3655 | generic_bignum[3] = 0; | |
3656 | else if (ep->X_add_number > 4) | |
3657 | as_bad (_("Number larger than 64 bits")); | |
3658 | lo32.X_op = O_constant; | |
3659 | lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16); | |
3660 | hi32.X_op = O_constant; | |
3661 | hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16); | |
3662 | } | |
3663 | ||
3664 | if (hi32.X_add_number == 0) | |
3665 | freg = 0; | |
3666 | else | |
3667 | { | |
3668 | int shift, bit; | |
3669 | unsigned long hi, lo; | |
3670 | ||
956cd1d6 | 3671 | if (hi32.X_add_number == (offsetT) 0xffffffff) |
beae10d5 KH |
3672 | { |
3673 | if ((lo32.X_add_number & 0xffff8000) == 0xffff8000) | |
3674 | { | |
67c0d1eb | 3675 | macro_build (&lo32, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
beae10d5 KH |
3676 | return; |
3677 | } | |
3678 | if (lo32.X_add_number & 0x80000000) | |
3679 | { | |
67c0d1eb | 3680 | macro_build (&lo32, "lui", "t,u", reg, BFD_RELOC_HI16); |
252b5132 | 3681 | if (lo32.X_add_number & 0xffff) |
67c0d1eb | 3682 | macro_build (&lo32, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16); |
beae10d5 KH |
3683 | return; |
3684 | } | |
3685 | } | |
252b5132 RH |
3686 | |
3687 | /* Check for 16bit shifted constant. We know that hi32 is | |
3688 | non-zero, so start the mask on the first bit of the hi32 | |
3689 | value. */ | |
3690 | shift = 17; | |
3691 | do | |
beae10d5 KH |
3692 | { |
3693 | unsigned long himask, lomask; | |
3694 | ||
3695 | if (shift < 32) | |
3696 | { | |
3697 | himask = 0xffff >> (32 - shift); | |
3698 | lomask = (0xffff << shift) & 0xffffffff; | |
3699 | } | |
3700 | else | |
3701 | { | |
3702 | himask = 0xffff << (shift - 32); | |
3703 | lomask = 0; | |
3704 | } | |
3705 | if ((hi32.X_add_number & ~(offsetT) himask) == 0 | |
3706 | && (lo32.X_add_number & ~(offsetT) lomask) == 0) | |
3707 | { | |
3708 | expressionS tmp; | |
3709 | ||
3710 | tmp.X_op = O_constant; | |
3711 | if (shift < 32) | |
3712 | tmp.X_add_number = ((hi32.X_add_number << (32 - shift)) | |
3713 | | (lo32.X_add_number >> shift)); | |
3714 | else | |
3715 | tmp.X_add_number = hi32.X_add_number >> (shift - 32); | |
67c0d1eb RS |
3716 | macro_build (&tmp, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16); |
3717 | macro_build (NULL, (shift >= 32) ? "dsll32" : "dsll", "d,w,<", | |
3718 | reg, reg, (shift >= 32) ? shift - 32 : shift); | |
beae10d5 KH |
3719 | return; |
3720 | } | |
f9419b05 | 3721 | ++shift; |
beae10d5 KH |
3722 | } |
3723 | while (shift <= (64 - 16)); | |
252b5132 RH |
3724 | |
3725 | /* Find the bit number of the lowest one bit, and store the | |
3726 | shifted value in hi/lo. */ | |
3727 | hi = (unsigned long) (hi32.X_add_number & 0xffffffff); | |
3728 | lo = (unsigned long) (lo32.X_add_number & 0xffffffff); | |
3729 | if (lo != 0) | |
3730 | { | |
3731 | bit = 0; | |
3732 | while ((lo & 1) == 0) | |
3733 | { | |
3734 | lo >>= 1; | |
3735 | ++bit; | |
3736 | } | |
3737 | lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit); | |
3738 | hi >>= bit; | |
3739 | } | |
3740 | else | |
3741 | { | |
3742 | bit = 32; | |
3743 | while ((hi & 1) == 0) | |
3744 | { | |
3745 | hi >>= 1; | |
3746 | ++bit; | |
3747 | } | |
3748 | lo = hi; | |
3749 | hi = 0; | |
3750 | } | |
3751 | ||
3752 | /* Optimize if the shifted value is a (power of 2) - 1. */ | |
3753 | if ((hi == 0 && ((lo + 1) & lo) == 0) | |
3754 | || (lo == 0xffffffff && ((hi + 1) & hi) == 0)) | |
beae10d5 KH |
3755 | { |
3756 | shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number); | |
252b5132 | 3757 | if (shift != 0) |
beae10d5 | 3758 | { |
252b5132 RH |
3759 | expressionS tmp; |
3760 | ||
3761 | /* This instruction will set the register to be all | |
3762 | ones. */ | |
beae10d5 KH |
3763 | tmp.X_op = O_constant; |
3764 | tmp.X_add_number = (offsetT) -1; | |
67c0d1eb | 3765 | macro_build (&tmp, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
beae10d5 KH |
3766 | if (bit != 0) |
3767 | { | |
3768 | bit += shift; | |
67c0d1eb RS |
3769 | macro_build (NULL, (bit >= 32) ? "dsll32" : "dsll", "d,w,<", |
3770 | reg, reg, (bit >= 32) ? bit - 32 : bit); | |
beae10d5 | 3771 | } |
67c0d1eb RS |
3772 | macro_build (NULL, (shift >= 32) ? "dsrl32" : "dsrl", "d,w,<", |
3773 | reg, reg, (shift >= 32) ? shift - 32 : shift); | |
beae10d5 KH |
3774 | return; |
3775 | } | |
3776 | } | |
252b5132 RH |
3777 | |
3778 | /* Sign extend hi32 before calling load_register, because we can | |
3779 | generally get better code when we load a sign extended value. */ | |
3780 | if ((hi32.X_add_number & 0x80000000) != 0) | |
beae10d5 | 3781 | hi32.X_add_number |= ~(offsetT) 0xffffffff; |
67c0d1eb | 3782 | load_register (reg, &hi32, 0); |
252b5132 RH |
3783 | freg = reg; |
3784 | } | |
3785 | if ((lo32.X_add_number & 0xffff0000) == 0) | |
3786 | { | |
3787 | if (freg != 0) | |
3788 | { | |
67c0d1eb | 3789 | macro_build (NULL, "dsll32", "d,w,<", reg, freg, 0); |
252b5132 RH |
3790 | freg = reg; |
3791 | } | |
3792 | } | |
3793 | else | |
3794 | { | |
3795 | expressionS mid16; | |
3796 | ||
956cd1d6 | 3797 | if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff)) |
beae10d5 | 3798 | { |
67c0d1eb RS |
3799 | macro_build (&lo32, "lui", "t,u", reg, BFD_RELOC_HI16); |
3800 | macro_build (NULL, "dsrl32", "d,w,<", reg, reg, 0); | |
beae10d5 KH |
3801 | return; |
3802 | } | |
252b5132 RH |
3803 | |
3804 | if (freg != 0) | |
3805 | { | |
67c0d1eb | 3806 | macro_build (NULL, "dsll", "d,w,<", reg, freg, 16); |
252b5132 RH |
3807 | freg = reg; |
3808 | } | |
3809 | mid16 = lo32; | |
3810 | mid16.X_add_number >>= 16; | |
67c0d1eb RS |
3811 | macro_build (&mid16, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16); |
3812 | macro_build (NULL, "dsll", "d,w,<", reg, reg, 16); | |
252b5132 RH |
3813 | freg = reg; |
3814 | } | |
3815 | if ((lo32.X_add_number & 0xffff) != 0) | |
67c0d1eb | 3816 | macro_build (&lo32, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16); |
252b5132 RH |
3817 | } |
3818 | ||
269137b2 TS |
3819 | static inline void |
3820 | load_delay_nop (void) | |
3821 | { | |
3822 | if (!gpr_interlocks) | |
3823 | macro_build (NULL, "nop", ""); | |
3824 | } | |
3825 | ||
252b5132 RH |
3826 | /* Load an address into a register. */ |
3827 | ||
3828 | static void | |
67c0d1eb | 3829 | load_address (int reg, expressionS *ep, int *used_at) |
252b5132 | 3830 | { |
252b5132 RH |
3831 | if (ep->X_op != O_constant |
3832 | && ep->X_op != O_symbol) | |
3833 | { | |
3834 | as_bad (_("expression too complex")); | |
3835 | ep->X_op = O_constant; | |
3836 | } | |
3837 | ||
3838 | if (ep->X_op == O_constant) | |
3839 | { | |
67c0d1eb | 3840 | load_register (reg, ep, HAVE_64BIT_ADDRESSES); |
252b5132 RH |
3841 | return; |
3842 | } | |
3843 | ||
3844 | if (mips_pic == NO_PIC) | |
3845 | { | |
3846 | /* If this is a reference to a GP relative symbol, we want | |
cdf6fd85 | 3847 | addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
3848 | Otherwise we want |
3849 | lui $reg,<sym> (BFD_RELOC_HI16_S) | |
3850 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
d6bc6245 | 3851 | If we have an addend, we always use the latter form. |
76b3015f | 3852 | |
d6bc6245 TS |
3853 | With 64bit address space and a usable $at we want |
3854 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
3855 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
3856 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
3857 | daddiu $at,<sym> (BFD_RELOC_LO16) | |
3858 | dsll32 $reg,0 | |
3a482fd5 | 3859 | daddu $reg,$reg,$at |
76b3015f | 3860 | |
c03099e6 | 3861 | If $at is already in use, we use a path which is suboptimal |
d6bc6245 TS |
3862 | on superscalar processors. |
3863 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
3864 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
3865 | dsll $reg,16 | |
3866 | daddiu $reg,<sym> (BFD_RELOC_HI16_S) | |
3867 | dsll $reg,16 | |
3868 | daddiu $reg,<sym> (BFD_RELOC_LO16) | |
6caf9ef4 TS |
3869 | |
3870 | For GP relative symbols in 64bit address space we can use | |
3871 | the same sequence as in 32bit address space. */ | |
aed1a261 | 3872 | if (HAVE_64BIT_SYMBOLS) |
d6bc6245 | 3873 | { |
6caf9ef4 TS |
3874 | if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET |
3875 | && !nopic_need_relax (ep->X_add_symbol, 1)) | |
3876 | { | |
3877 | relax_start (ep->X_add_symbol); | |
3878 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, | |
3879 | mips_gp_register, BFD_RELOC_GPREL16); | |
3880 | relax_switch (); | |
3881 | } | |
d6bc6245 | 3882 | |
b8285c27 | 3883 | if (*used_at == 0 && !mips_opts.noat) |
d6bc6245 | 3884 | { |
67c0d1eb RS |
3885 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_HIGHEST); |
3886 | macro_build (ep, "lui", "t,u", AT, BFD_RELOC_HI16_S); | |
3887 | macro_build (ep, "daddiu", "t,r,j", reg, reg, | |
3888 | BFD_RELOC_MIPS_HIGHER); | |
3889 | macro_build (ep, "daddiu", "t,r,j", AT, AT, BFD_RELOC_LO16); | |
3890 | macro_build (NULL, "dsll32", "d,w,<", reg, reg, 0); | |
3891 | macro_build (NULL, "daddu", "d,v,t", reg, reg, AT); | |
d6bc6245 TS |
3892 | *used_at = 1; |
3893 | } | |
3894 | else | |
3895 | { | |
67c0d1eb RS |
3896 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_HIGHEST); |
3897 | macro_build (ep, "daddiu", "t,r,j", reg, reg, | |
3898 | BFD_RELOC_MIPS_HIGHER); | |
3899 | macro_build (NULL, "dsll", "d,w,<", reg, reg, 16); | |
3900 | macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_HI16_S); | |
3901 | macro_build (NULL, "dsll", "d,w,<", reg, reg, 16); | |
3902 | macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_LO16); | |
d6bc6245 | 3903 | } |
6caf9ef4 TS |
3904 | |
3905 | if (mips_relax.sequence) | |
3906 | relax_end (); | |
d6bc6245 | 3907 | } |
252b5132 RH |
3908 | else |
3909 | { | |
d6bc6245 | 3910 | if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 3911 | && !nopic_need_relax (ep->X_add_symbol, 1)) |
d6bc6245 | 3912 | { |
4d7206a2 | 3913 | relax_start (ep->X_add_symbol); |
67c0d1eb | 3914 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, |
17a2f251 | 3915 | mips_gp_register, BFD_RELOC_GPREL16); |
4d7206a2 | 3916 | relax_switch (); |
d6bc6245 | 3917 | } |
67c0d1eb RS |
3918 | macro_build_lui (ep, reg); |
3919 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", | |
3920 | reg, reg, BFD_RELOC_LO16); | |
4d7206a2 RS |
3921 | if (mips_relax.sequence) |
3922 | relax_end (); | |
d6bc6245 | 3923 | } |
252b5132 | 3924 | } |
0a44bf69 | 3925 | else if (!mips_big_got) |
252b5132 RH |
3926 | { |
3927 | expressionS ex; | |
3928 | ||
3929 | /* If this is a reference to an external symbol, we want | |
3930 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3931 | Otherwise we want | |
3932 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3933 | nop | |
3934 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
f5040a92 AO |
3935 | If there is a constant, it must be added in after. |
3936 | ||
ed6fb7bd | 3937 | If we have NewABI, we want |
f5040a92 AO |
3938 | lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP) |
3939 | unless we're referencing a global symbol with a non-zero | |
3940 | offset, in which case cst must be added separately. */ | |
ed6fb7bd SC |
3941 | if (HAVE_NEWABI) |
3942 | { | |
f5040a92 AO |
3943 | if (ep->X_add_number) |
3944 | { | |
4d7206a2 | 3945 | ex.X_add_number = ep->X_add_number; |
f5040a92 | 3946 | ep->X_add_number = 0; |
4d7206a2 | 3947 | relax_start (ep->X_add_symbol); |
67c0d1eb RS |
3948 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
3949 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
3950 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) |
3951 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
3952 | ex.X_op = O_constant; | |
67c0d1eb | 3953 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 3954 | reg, reg, BFD_RELOC_LO16); |
f5040a92 | 3955 | ep->X_add_number = ex.X_add_number; |
4d7206a2 | 3956 | relax_switch (); |
f5040a92 | 3957 | } |
67c0d1eb | 3958 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 3959 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); |
4d7206a2 RS |
3960 | if (mips_relax.sequence) |
3961 | relax_end (); | |
ed6fb7bd SC |
3962 | } |
3963 | else | |
3964 | { | |
f5040a92 AO |
3965 | ex.X_add_number = ep->X_add_number; |
3966 | ep->X_add_number = 0; | |
67c0d1eb RS |
3967 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
3968 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 3969 | load_delay_nop (); |
4d7206a2 RS |
3970 | relax_start (ep->X_add_symbol); |
3971 | relax_switch (); | |
67c0d1eb | 3972 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
17a2f251 | 3973 | BFD_RELOC_LO16); |
4d7206a2 | 3974 | relax_end (); |
ed6fb7bd | 3975 | |
f5040a92 AO |
3976 | if (ex.X_add_number != 0) |
3977 | { | |
3978 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
3979 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
3980 | ex.X_op = O_constant; | |
67c0d1eb | 3981 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 3982 | reg, reg, BFD_RELOC_LO16); |
f5040a92 | 3983 | } |
252b5132 RH |
3984 | } |
3985 | } | |
0a44bf69 | 3986 | else if (mips_big_got) |
252b5132 RH |
3987 | { |
3988 | expressionS ex; | |
252b5132 RH |
3989 | |
3990 | /* This is the large GOT case. If this is a reference to an | |
3991 | external symbol, we want | |
3992 | lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
3993 | addu $reg,$reg,$gp | |
3994 | lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16) | |
f5040a92 AO |
3995 | |
3996 | Otherwise, for a reference to a local symbol in old ABI, we want | |
252b5132 RH |
3997 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) |
3998 | nop | |
3999 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
684022ea | 4000 | If there is a constant, it must be added in after. |
f5040a92 AO |
4001 | |
4002 | In the NewABI, for local symbols, with or without offsets, we want: | |
438c16b8 TS |
4003 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) |
4004 | addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) | |
f5040a92 | 4005 | */ |
438c16b8 TS |
4006 | if (HAVE_NEWABI) |
4007 | { | |
4d7206a2 | 4008 | ex.X_add_number = ep->X_add_number; |
f5040a92 | 4009 | ep->X_add_number = 0; |
4d7206a2 | 4010 | relax_start (ep->X_add_symbol); |
67c0d1eb RS |
4011 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_GOT_HI16); |
4012 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
4013 | reg, reg, mips_gp_register); | |
4014 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", | |
4015 | reg, BFD_RELOC_MIPS_GOT_LO16, reg); | |
f5040a92 AO |
4016 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) |
4017 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4018 | else if (ex.X_add_number) | |
4019 | { | |
4020 | ex.X_op = O_constant; | |
67c0d1eb RS |
4021 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
4022 | BFD_RELOC_LO16); | |
f5040a92 AO |
4023 | } |
4024 | ||
4025 | ep->X_add_number = ex.X_add_number; | |
4d7206a2 | 4026 | relax_switch (); |
67c0d1eb | 4027 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 4028 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); |
67c0d1eb RS |
4029 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
4030 | BFD_RELOC_MIPS_GOT_OFST); | |
4d7206a2 | 4031 | relax_end (); |
438c16b8 | 4032 | } |
252b5132 | 4033 | else |
438c16b8 | 4034 | { |
f5040a92 AO |
4035 | ex.X_add_number = ep->X_add_number; |
4036 | ep->X_add_number = 0; | |
4d7206a2 | 4037 | relax_start (ep->X_add_symbol); |
67c0d1eb RS |
4038 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_GOT_HI16); |
4039 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
4040 | reg, reg, mips_gp_register); | |
4041 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", | |
4042 | reg, BFD_RELOC_MIPS_GOT_LO16, reg); | |
4d7206a2 RS |
4043 | relax_switch (); |
4044 | if (reg_needs_delay (mips_gp_register)) | |
438c16b8 TS |
4045 | { |
4046 | /* We need a nop before loading from $gp. This special | |
4047 | check is required because the lui which starts the main | |
4048 | instruction stream does not refer to $gp, and so will not | |
4049 | insert the nop which may be required. */ | |
67c0d1eb | 4050 | macro_build (NULL, "nop", ""); |
438c16b8 | 4051 | } |
67c0d1eb | 4052 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 4053 | BFD_RELOC_MIPS_GOT16, mips_gp_register); |
269137b2 | 4054 | load_delay_nop (); |
67c0d1eb | 4055 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
17a2f251 | 4056 | BFD_RELOC_LO16); |
4d7206a2 | 4057 | relax_end (); |
438c16b8 | 4058 | |
f5040a92 AO |
4059 | if (ex.X_add_number != 0) |
4060 | { | |
4061 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
4062 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4063 | ex.X_op = O_constant; | |
67c0d1eb RS |
4064 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
4065 | BFD_RELOC_LO16); | |
f5040a92 | 4066 | } |
252b5132 RH |
4067 | } |
4068 | } | |
252b5132 RH |
4069 | else |
4070 | abort (); | |
8fc2e39e TS |
4071 | |
4072 | if (mips_opts.noat && *used_at == 1) | |
4073 | as_bad (_("Macro used $at after \".set noat\"")); | |
252b5132 RH |
4074 | } |
4075 | ||
ea1fb5dc RS |
4076 | /* Move the contents of register SOURCE into register DEST. */ |
4077 | ||
4078 | static void | |
67c0d1eb | 4079 | move_register (int dest, int source) |
ea1fb5dc | 4080 | { |
67c0d1eb RS |
4081 | macro_build (NULL, HAVE_32BIT_GPRS ? "addu" : "daddu", "d,v,t", |
4082 | dest, source, 0); | |
ea1fb5dc RS |
4083 | } |
4084 | ||
4d7206a2 | 4085 | /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where |
f6a22291 MR |
4086 | LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement. |
4087 | The two alternatives are: | |
4d7206a2 RS |
4088 | |
4089 | Global symbol Local sybmol | |
4090 | ------------- ------------ | |
4091 | lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET) | |
4092 | ... ... | |
4093 | addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET) | |
4094 | ||
4095 | load_got_offset emits the first instruction and add_got_offset | |
f6a22291 MR |
4096 | emits the second for a 16-bit offset or add_got_offset_hilo emits |
4097 | a sequence to add a 32-bit offset using a scratch register. */ | |
4d7206a2 RS |
4098 | |
4099 | static void | |
67c0d1eb | 4100 | load_got_offset (int dest, expressionS *local) |
4d7206a2 RS |
4101 | { |
4102 | expressionS global; | |
4103 | ||
4104 | global = *local; | |
4105 | global.X_add_number = 0; | |
4106 | ||
4107 | relax_start (local->X_add_symbol); | |
67c0d1eb RS |
4108 | macro_build (&global, ADDRESS_LOAD_INSN, "t,o(b)", dest, |
4109 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
4d7206a2 | 4110 | relax_switch (); |
67c0d1eb RS |
4111 | macro_build (local, ADDRESS_LOAD_INSN, "t,o(b)", dest, |
4112 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
4d7206a2 RS |
4113 | relax_end (); |
4114 | } | |
4115 | ||
4116 | static void | |
67c0d1eb | 4117 | add_got_offset (int dest, expressionS *local) |
4d7206a2 RS |
4118 | { |
4119 | expressionS global; | |
4120 | ||
4121 | global.X_op = O_constant; | |
4122 | global.X_op_symbol = NULL; | |
4123 | global.X_add_symbol = NULL; | |
4124 | global.X_add_number = local->X_add_number; | |
4125 | ||
4126 | relax_start (local->X_add_symbol); | |
67c0d1eb | 4127 | macro_build (&global, ADDRESS_ADDI_INSN, "t,r,j", |
4d7206a2 RS |
4128 | dest, dest, BFD_RELOC_LO16); |
4129 | relax_switch (); | |
67c0d1eb | 4130 | macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", dest, dest, BFD_RELOC_LO16); |
4d7206a2 RS |
4131 | relax_end (); |
4132 | } | |
4133 | ||
f6a22291 MR |
4134 | static void |
4135 | add_got_offset_hilo (int dest, expressionS *local, int tmp) | |
4136 | { | |
4137 | expressionS global; | |
4138 | int hold_mips_optimize; | |
4139 | ||
4140 | global.X_op = O_constant; | |
4141 | global.X_op_symbol = NULL; | |
4142 | global.X_add_symbol = NULL; | |
4143 | global.X_add_number = local->X_add_number; | |
4144 | ||
4145 | relax_start (local->X_add_symbol); | |
4146 | load_register (tmp, &global, HAVE_64BIT_ADDRESSES); | |
4147 | relax_switch (); | |
4148 | /* Set mips_optimize around the lui instruction to avoid | |
4149 | inserting an unnecessary nop after the lw. */ | |
4150 | hold_mips_optimize = mips_optimize; | |
4151 | mips_optimize = 2; | |
4152 | macro_build_lui (&global, tmp); | |
4153 | mips_optimize = hold_mips_optimize; | |
4154 | macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", tmp, tmp, BFD_RELOC_LO16); | |
4155 | relax_end (); | |
4156 | ||
4157 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dest, dest, tmp); | |
4158 | } | |
4159 | ||
252b5132 RH |
4160 | /* |
4161 | * Build macros | |
4162 | * This routine implements the seemingly endless macro or synthesized | |
4163 | * instructions and addressing modes in the mips assembly language. Many | |
4164 | * of these macros are simple and are similar to each other. These could | |
67c1ffbe | 4165 | * probably be handled by some kind of table or grammar approach instead of |
252b5132 RH |
4166 | * this verbose method. Others are not simple macros but are more like |
4167 | * optimizing code generation. | |
4168 | * One interesting optimization is when several store macros appear | |
67c1ffbe | 4169 | * consecutively that would load AT with the upper half of the same address. |
252b5132 RH |
4170 | * The ensuing load upper instructions are ommited. This implies some kind |
4171 | * of global optimization. We currently only optimize within a single macro. | |
4172 | * For many of the load and store macros if the address is specified as a | |
4173 | * constant expression in the first 64k of memory (ie ld $2,0x4000c) we | |
4174 | * first load register 'at' with zero and use it as the base register. The | |
4175 | * mips assembler simply uses register $zero. Just one tiny optimization | |
4176 | * we're missing. | |
4177 | */ | |
4178 | static void | |
17a2f251 | 4179 | macro (struct mips_cl_insn *ip) |
252b5132 RH |
4180 | { |
4181 | register int treg, sreg, dreg, breg; | |
4182 | int tempreg; | |
4183 | int mask; | |
43841e91 | 4184 | int used_at = 0; |
252b5132 RH |
4185 | expressionS expr1; |
4186 | const char *s; | |
4187 | const char *s2; | |
4188 | const char *fmt; | |
4189 | int likely = 0; | |
4190 | int dbl = 0; | |
4191 | int coproc = 0; | |
4192 | int lr = 0; | |
4193 | int imm = 0; | |
1abe91b1 | 4194 | int call = 0; |
252b5132 | 4195 | int off; |
67c0d1eb | 4196 | offsetT maxnum; |
252b5132 | 4197 | bfd_reloc_code_real_type r; |
252b5132 RH |
4198 | int hold_mips_optimize; |
4199 | ||
4200 | assert (! mips_opts.mips16); | |
4201 | ||
4202 | treg = (ip->insn_opcode >> 16) & 0x1f; | |
4203 | dreg = (ip->insn_opcode >> 11) & 0x1f; | |
4204 | sreg = breg = (ip->insn_opcode >> 21) & 0x1f; | |
4205 | mask = ip->insn_mo->mask; | |
4206 | ||
4207 | expr1.X_op = O_constant; | |
4208 | expr1.X_op_symbol = NULL; | |
4209 | expr1.X_add_symbol = NULL; | |
4210 | expr1.X_add_number = 1; | |
4211 | ||
4212 | switch (mask) | |
4213 | { | |
4214 | case M_DABS: | |
4215 | dbl = 1; | |
4216 | case M_ABS: | |
4217 | /* bgez $a0,.+12 | |
4218 | move v0,$a0 | |
4219 | sub v0,$zero,$a0 | |
4220 | */ | |
4221 | ||
7d10b47d | 4222 | start_noreorder (); |
252b5132 RH |
4223 | |
4224 | expr1.X_add_number = 8; | |
67c0d1eb | 4225 | macro_build (&expr1, "bgez", "s,p", sreg); |
252b5132 | 4226 | if (dreg == sreg) |
67c0d1eb | 4227 | macro_build (NULL, "nop", "", 0); |
252b5132 | 4228 | else |
67c0d1eb RS |
4229 | move_register (dreg, sreg); |
4230 | macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, 0, sreg); | |
252b5132 | 4231 | |
7d10b47d | 4232 | end_noreorder (); |
8fc2e39e | 4233 | break; |
252b5132 RH |
4234 | |
4235 | case M_ADD_I: | |
4236 | s = "addi"; | |
4237 | s2 = "add"; | |
4238 | goto do_addi; | |
4239 | case M_ADDU_I: | |
4240 | s = "addiu"; | |
4241 | s2 = "addu"; | |
4242 | goto do_addi; | |
4243 | case M_DADD_I: | |
4244 | dbl = 1; | |
4245 | s = "daddi"; | |
4246 | s2 = "dadd"; | |
4247 | goto do_addi; | |
4248 | case M_DADDU_I: | |
4249 | dbl = 1; | |
4250 | s = "daddiu"; | |
4251 | s2 = "daddu"; | |
4252 | do_addi: | |
4253 | if (imm_expr.X_op == O_constant | |
4254 | && imm_expr.X_add_number >= -0x8000 | |
4255 | && imm_expr.X_add_number < 0x8000) | |
4256 | { | |
67c0d1eb | 4257 | macro_build (&imm_expr, s, "t,r,j", treg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 4258 | break; |
252b5132 | 4259 | } |
8fc2e39e | 4260 | used_at = 1; |
67c0d1eb RS |
4261 | load_register (AT, &imm_expr, dbl); |
4262 | macro_build (NULL, s2, "d,v,t", treg, sreg, AT); | |
252b5132 RH |
4263 | break; |
4264 | ||
4265 | case M_AND_I: | |
4266 | s = "andi"; | |
4267 | s2 = "and"; | |
4268 | goto do_bit; | |
4269 | case M_OR_I: | |
4270 | s = "ori"; | |
4271 | s2 = "or"; | |
4272 | goto do_bit; | |
4273 | case M_NOR_I: | |
4274 | s = ""; | |
4275 | s2 = "nor"; | |
4276 | goto do_bit; | |
4277 | case M_XOR_I: | |
4278 | s = "xori"; | |
4279 | s2 = "xor"; | |
4280 | do_bit: | |
4281 | if (imm_expr.X_op == O_constant | |
4282 | && imm_expr.X_add_number >= 0 | |
4283 | && imm_expr.X_add_number < 0x10000) | |
4284 | { | |
4285 | if (mask != M_NOR_I) | |
67c0d1eb | 4286 | macro_build (&imm_expr, s, "t,r,i", treg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
4287 | else |
4288 | { | |
67c0d1eb RS |
4289 | macro_build (&imm_expr, "ori", "t,r,i", |
4290 | treg, sreg, BFD_RELOC_LO16); | |
4291 | macro_build (NULL, "nor", "d,v,t", treg, treg, 0); | |
252b5132 | 4292 | } |
8fc2e39e | 4293 | break; |
252b5132 RH |
4294 | } |
4295 | ||
8fc2e39e | 4296 | used_at = 1; |
67c0d1eb RS |
4297 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
4298 | macro_build (NULL, s2, "d,v,t", treg, sreg, AT); | |
252b5132 RH |
4299 | break; |
4300 | ||
4301 | case M_BEQ_I: | |
4302 | s = "beq"; | |
4303 | goto beq_i; | |
4304 | case M_BEQL_I: | |
4305 | s = "beql"; | |
4306 | likely = 1; | |
4307 | goto beq_i; | |
4308 | case M_BNE_I: | |
4309 | s = "bne"; | |
4310 | goto beq_i; | |
4311 | case M_BNEL_I: | |
4312 | s = "bnel"; | |
4313 | likely = 1; | |
4314 | beq_i: | |
4315 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4316 | { | |
67c0d1eb | 4317 | macro_build (&offset_expr, s, "s,t,p", sreg, 0); |
8fc2e39e | 4318 | break; |
252b5132 | 4319 | } |
8fc2e39e | 4320 | used_at = 1; |
67c0d1eb RS |
4321 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
4322 | macro_build (&offset_expr, s, "s,t,p", sreg, AT); | |
252b5132 RH |
4323 | break; |
4324 | ||
4325 | case M_BGEL: | |
4326 | likely = 1; | |
4327 | case M_BGE: | |
4328 | if (treg == 0) | |
4329 | { | |
67c0d1eb | 4330 | macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", sreg); |
8fc2e39e | 4331 | break; |
252b5132 RH |
4332 | } |
4333 | if (sreg == 0) | |
4334 | { | |
67c0d1eb | 4335 | macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", treg); |
8fc2e39e | 4336 | break; |
252b5132 | 4337 | } |
8fc2e39e | 4338 | used_at = 1; |
67c0d1eb RS |
4339 | macro_build (NULL, "slt", "d,v,t", AT, sreg, treg); |
4340 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
4341 | break; |
4342 | ||
4343 | case M_BGTL_I: | |
4344 | likely = 1; | |
4345 | case M_BGT_I: | |
4346 | /* check for > max integer */ | |
4347 | maxnum = 0x7fffffff; | |
ca4e0257 | 4348 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
4349 | { |
4350 | maxnum <<= 16; | |
4351 | maxnum |= 0xffff; | |
4352 | maxnum <<= 16; | |
4353 | maxnum |= 0xffff; | |
4354 | } | |
4355 | if (imm_expr.X_op == O_constant | |
4356 | && imm_expr.X_add_number >= maxnum | |
ca4e0257 | 4357 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
4358 | { |
4359 | do_false: | |
4360 | /* result is always false */ | |
4361 | if (! likely) | |
67c0d1eb | 4362 | macro_build (NULL, "nop", "", 0); |
252b5132 | 4363 | else |
67c0d1eb | 4364 | macro_build (&offset_expr, "bnel", "s,t,p", 0, 0); |
8fc2e39e | 4365 | break; |
252b5132 RH |
4366 | } |
4367 | if (imm_expr.X_op != O_constant) | |
4368 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 4369 | ++imm_expr.X_add_number; |
252b5132 RH |
4370 | /* FALLTHROUGH */ |
4371 | case M_BGE_I: | |
4372 | case M_BGEL_I: | |
4373 | if (mask == M_BGEL_I) | |
4374 | likely = 1; | |
4375 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4376 | { | |
67c0d1eb | 4377 | macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", sreg); |
8fc2e39e | 4378 | break; |
252b5132 RH |
4379 | } |
4380 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4381 | { | |
67c0d1eb | 4382 | macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", sreg); |
8fc2e39e | 4383 | break; |
252b5132 RH |
4384 | } |
4385 | maxnum = 0x7fffffff; | |
ca4e0257 | 4386 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
4387 | { |
4388 | maxnum <<= 16; | |
4389 | maxnum |= 0xffff; | |
4390 | maxnum <<= 16; | |
4391 | maxnum |= 0xffff; | |
4392 | } | |
4393 | maxnum = - maxnum - 1; | |
4394 | if (imm_expr.X_op == O_constant | |
4395 | && imm_expr.X_add_number <= maxnum | |
ca4e0257 | 4396 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
4397 | { |
4398 | do_true: | |
4399 | /* result is always true */ | |
4400 | as_warn (_("Branch %s is always true"), ip->insn_mo->name); | |
67c0d1eb | 4401 | macro_build (&offset_expr, "b", "p"); |
8fc2e39e | 4402 | break; |
252b5132 | 4403 | } |
8fc2e39e | 4404 | used_at = 1; |
67c0d1eb RS |
4405 | set_at (sreg, 0); |
4406 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
4407 | break; |
4408 | ||
4409 | case M_BGEUL: | |
4410 | likely = 1; | |
4411 | case M_BGEU: | |
4412 | if (treg == 0) | |
4413 | goto do_true; | |
4414 | if (sreg == 0) | |
4415 | { | |
67c0d1eb | 4416 | macro_build (&offset_expr, likely ? "beql" : "beq", |
17a2f251 | 4417 | "s,t,p", 0, treg); |
8fc2e39e | 4418 | break; |
252b5132 | 4419 | } |
8fc2e39e | 4420 | used_at = 1; |
67c0d1eb RS |
4421 | macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg); |
4422 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
4423 | break; |
4424 | ||
4425 | case M_BGTUL_I: | |
4426 | likely = 1; | |
4427 | case M_BGTU_I: | |
4428 | if (sreg == 0 | |
ca4e0257 | 4429 | || (HAVE_32BIT_GPRS |
252b5132 | 4430 | && imm_expr.X_op == O_constant |
956cd1d6 | 4431 | && imm_expr.X_add_number == (offsetT) 0xffffffff)) |
252b5132 RH |
4432 | goto do_false; |
4433 | if (imm_expr.X_op != O_constant) | |
4434 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 4435 | ++imm_expr.X_add_number; |
252b5132 RH |
4436 | /* FALLTHROUGH */ |
4437 | case M_BGEU_I: | |
4438 | case M_BGEUL_I: | |
4439 | if (mask == M_BGEUL_I) | |
4440 | likely = 1; | |
4441 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4442 | goto do_true; | |
4443 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4444 | { | |
67c0d1eb | 4445 | macro_build (&offset_expr, likely ? "bnel" : "bne", |
17a2f251 | 4446 | "s,t,p", sreg, 0); |
8fc2e39e | 4447 | break; |
252b5132 | 4448 | } |
8fc2e39e | 4449 | used_at = 1; |
67c0d1eb RS |
4450 | set_at (sreg, 1); |
4451 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
4452 | break; |
4453 | ||
4454 | case M_BGTL: | |
4455 | likely = 1; | |
4456 | case M_BGT: | |
4457 | if (treg == 0) | |
4458 | { | |
67c0d1eb | 4459 | macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", sreg); |
8fc2e39e | 4460 | break; |
252b5132 RH |
4461 | } |
4462 | if (sreg == 0) | |
4463 | { | |
67c0d1eb | 4464 | macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", treg); |
8fc2e39e | 4465 | break; |
252b5132 | 4466 | } |
8fc2e39e | 4467 | used_at = 1; |
67c0d1eb RS |
4468 | macro_build (NULL, "slt", "d,v,t", AT, treg, sreg); |
4469 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
4470 | break; |
4471 | ||
4472 | case M_BGTUL: | |
4473 | likely = 1; | |
4474 | case M_BGTU: | |
4475 | if (treg == 0) | |
4476 | { | |
67c0d1eb | 4477 | macro_build (&offset_expr, likely ? "bnel" : "bne", |
17a2f251 | 4478 | "s,t,p", sreg, 0); |
8fc2e39e | 4479 | break; |
252b5132 RH |
4480 | } |
4481 | if (sreg == 0) | |
4482 | goto do_false; | |
8fc2e39e | 4483 | used_at = 1; |
67c0d1eb RS |
4484 | macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg); |
4485 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
4486 | break; |
4487 | ||
4488 | case M_BLEL: | |
4489 | likely = 1; | |
4490 | case M_BLE: | |
4491 | if (treg == 0) | |
4492 | { | |
67c0d1eb | 4493 | macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", sreg); |
8fc2e39e | 4494 | break; |
252b5132 RH |
4495 | } |
4496 | if (sreg == 0) | |
4497 | { | |
67c0d1eb | 4498 | macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", treg); |
8fc2e39e | 4499 | break; |
252b5132 | 4500 | } |
8fc2e39e | 4501 | used_at = 1; |
67c0d1eb RS |
4502 | macro_build (NULL, "slt", "d,v,t", AT, treg, sreg); |
4503 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
4504 | break; |
4505 | ||
4506 | case M_BLEL_I: | |
4507 | likely = 1; | |
4508 | case M_BLE_I: | |
4509 | maxnum = 0x7fffffff; | |
ca4e0257 | 4510 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
4511 | { |
4512 | maxnum <<= 16; | |
4513 | maxnum |= 0xffff; | |
4514 | maxnum <<= 16; | |
4515 | maxnum |= 0xffff; | |
4516 | } | |
4517 | if (imm_expr.X_op == O_constant | |
4518 | && imm_expr.X_add_number >= maxnum | |
ca4e0257 | 4519 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
4520 | goto do_true; |
4521 | if (imm_expr.X_op != O_constant) | |
4522 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 4523 | ++imm_expr.X_add_number; |
252b5132 RH |
4524 | /* FALLTHROUGH */ |
4525 | case M_BLT_I: | |
4526 | case M_BLTL_I: | |
4527 | if (mask == M_BLTL_I) | |
4528 | likely = 1; | |
4529 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4530 | { | |
67c0d1eb | 4531 | macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", sreg); |
8fc2e39e | 4532 | break; |
252b5132 RH |
4533 | } |
4534 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4535 | { | |
67c0d1eb | 4536 | macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", sreg); |
8fc2e39e | 4537 | break; |
252b5132 | 4538 | } |
8fc2e39e | 4539 | used_at = 1; |
67c0d1eb RS |
4540 | set_at (sreg, 0); |
4541 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
4542 | break; |
4543 | ||
4544 | case M_BLEUL: | |
4545 | likely = 1; | |
4546 | case M_BLEU: | |
4547 | if (treg == 0) | |
4548 | { | |
67c0d1eb | 4549 | macro_build (&offset_expr, likely ? "beql" : "beq", |
17a2f251 | 4550 | "s,t,p", sreg, 0); |
8fc2e39e | 4551 | break; |
252b5132 RH |
4552 | } |
4553 | if (sreg == 0) | |
4554 | goto do_true; | |
8fc2e39e | 4555 | used_at = 1; |
67c0d1eb RS |
4556 | macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg); |
4557 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
4558 | break; |
4559 | ||
4560 | case M_BLEUL_I: | |
4561 | likely = 1; | |
4562 | case M_BLEU_I: | |
4563 | if (sreg == 0 | |
ca4e0257 | 4564 | || (HAVE_32BIT_GPRS |
252b5132 | 4565 | && imm_expr.X_op == O_constant |
956cd1d6 | 4566 | && imm_expr.X_add_number == (offsetT) 0xffffffff)) |
252b5132 RH |
4567 | goto do_true; |
4568 | if (imm_expr.X_op != O_constant) | |
4569 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 4570 | ++imm_expr.X_add_number; |
252b5132 RH |
4571 | /* FALLTHROUGH */ |
4572 | case M_BLTU_I: | |
4573 | case M_BLTUL_I: | |
4574 | if (mask == M_BLTUL_I) | |
4575 | likely = 1; | |
4576 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4577 | goto do_false; | |
4578 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4579 | { | |
67c0d1eb | 4580 | macro_build (&offset_expr, likely ? "beql" : "beq", |
252b5132 | 4581 | "s,t,p", sreg, 0); |
8fc2e39e | 4582 | break; |
252b5132 | 4583 | } |
8fc2e39e | 4584 | used_at = 1; |
67c0d1eb RS |
4585 | set_at (sreg, 1); |
4586 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
4587 | break; |
4588 | ||
4589 | case M_BLTL: | |
4590 | likely = 1; | |
4591 | case M_BLT: | |
4592 | if (treg == 0) | |
4593 | { | |
67c0d1eb | 4594 | macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", sreg); |
8fc2e39e | 4595 | break; |
252b5132 RH |
4596 | } |
4597 | if (sreg == 0) | |
4598 | { | |
67c0d1eb | 4599 | macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", treg); |
8fc2e39e | 4600 | break; |
252b5132 | 4601 | } |
8fc2e39e | 4602 | used_at = 1; |
67c0d1eb RS |
4603 | macro_build (NULL, "slt", "d,v,t", AT, sreg, treg); |
4604 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
4605 | break; |
4606 | ||
4607 | case M_BLTUL: | |
4608 | likely = 1; | |
4609 | case M_BLTU: | |
4610 | if (treg == 0) | |
4611 | goto do_false; | |
4612 | if (sreg == 0) | |
4613 | { | |
67c0d1eb | 4614 | macro_build (&offset_expr, likely ? "bnel" : "bne", |
17a2f251 | 4615 | "s,t,p", 0, treg); |
8fc2e39e | 4616 | break; |
252b5132 | 4617 | } |
8fc2e39e | 4618 | used_at = 1; |
67c0d1eb RS |
4619 | macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg); |
4620 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
4621 | break; |
4622 | ||
5f74bc13 CD |
4623 | case M_DEXT: |
4624 | { | |
4625 | unsigned long pos; | |
4626 | unsigned long size; | |
4627 | ||
4628 | if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant) | |
4629 | { | |
4630 | as_bad (_("Unsupported large constant")); | |
4631 | pos = size = 1; | |
4632 | } | |
4633 | else | |
4634 | { | |
4635 | pos = (unsigned long) imm_expr.X_add_number; | |
4636 | size = (unsigned long) imm2_expr.X_add_number; | |
4637 | } | |
4638 | ||
4639 | if (pos > 63) | |
4640 | { | |
4641 | as_bad (_("Improper position (%lu)"), pos); | |
4642 | pos = 1; | |
4643 | } | |
4644 | if (size == 0 || size > 64 | |
4645 | || (pos + size - 1) > 63) | |
4646 | { | |
4647 | as_bad (_("Improper extract size (%lu, position %lu)"), | |
4648 | size, pos); | |
4649 | size = 1; | |
4650 | } | |
4651 | ||
4652 | if (size <= 32 && pos < 32) | |
4653 | { | |
4654 | s = "dext"; | |
4655 | fmt = "t,r,+A,+C"; | |
4656 | } | |
4657 | else if (size <= 32) | |
4658 | { | |
4659 | s = "dextu"; | |
4660 | fmt = "t,r,+E,+H"; | |
4661 | } | |
4662 | else | |
4663 | { | |
4664 | s = "dextm"; | |
4665 | fmt = "t,r,+A,+G"; | |
4666 | } | |
67c0d1eb | 4667 | macro_build ((expressionS *) NULL, s, fmt, treg, sreg, pos, size - 1); |
5f74bc13 | 4668 | } |
8fc2e39e | 4669 | break; |
5f74bc13 CD |
4670 | |
4671 | case M_DINS: | |
4672 | { | |
4673 | unsigned long pos; | |
4674 | unsigned long size; | |
4675 | ||
4676 | if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant) | |
4677 | { | |
4678 | as_bad (_("Unsupported large constant")); | |
4679 | pos = size = 1; | |
4680 | } | |
4681 | else | |
4682 | { | |
4683 | pos = (unsigned long) imm_expr.X_add_number; | |
4684 | size = (unsigned long) imm2_expr.X_add_number; | |
4685 | } | |
4686 | ||
4687 | if (pos > 63) | |
4688 | { | |
4689 | as_bad (_("Improper position (%lu)"), pos); | |
4690 | pos = 1; | |
4691 | } | |
4692 | if (size == 0 || size > 64 | |
4693 | || (pos + size - 1) > 63) | |
4694 | { | |
4695 | as_bad (_("Improper insert size (%lu, position %lu)"), | |
4696 | size, pos); | |
4697 | size = 1; | |
4698 | } | |
4699 | ||
4700 | if (pos < 32 && (pos + size - 1) < 32) | |
4701 | { | |
4702 | s = "dins"; | |
4703 | fmt = "t,r,+A,+B"; | |
4704 | } | |
4705 | else if (pos >= 32) | |
4706 | { | |
4707 | s = "dinsu"; | |
4708 | fmt = "t,r,+E,+F"; | |
4709 | } | |
4710 | else | |
4711 | { | |
4712 | s = "dinsm"; | |
4713 | fmt = "t,r,+A,+F"; | |
4714 | } | |
67c0d1eb RS |
4715 | macro_build ((expressionS *) NULL, s, fmt, treg, sreg, pos, |
4716 | pos + size - 1); | |
5f74bc13 | 4717 | } |
8fc2e39e | 4718 | break; |
5f74bc13 | 4719 | |
252b5132 RH |
4720 | case M_DDIV_3: |
4721 | dbl = 1; | |
4722 | case M_DIV_3: | |
4723 | s = "mflo"; | |
4724 | goto do_div3; | |
4725 | case M_DREM_3: | |
4726 | dbl = 1; | |
4727 | case M_REM_3: | |
4728 | s = "mfhi"; | |
4729 | do_div3: | |
4730 | if (treg == 0) | |
4731 | { | |
4732 | as_warn (_("Divide by zero.")); | |
4733 | if (mips_trap) | |
67c0d1eb | 4734 | macro_build (NULL, "teq", "s,t,q", 0, 0, 7); |
252b5132 | 4735 | else |
67c0d1eb | 4736 | macro_build (NULL, "break", "c", 7); |
8fc2e39e | 4737 | break; |
252b5132 RH |
4738 | } |
4739 | ||
7d10b47d | 4740 | start_noreorder (); |
252b5132 RH |
4741 | if (mips_trap) |
4742 | { | |
67c0d1eb RS |
4743 | macro_build (NULL, "teq", "s,t,q", treg, 0, 7); |
4744 | macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg); | |
252b5132 RH |
4745 | } |
4746 | else | |
4747 | { | |
4748 | expr1.X_add_number = 8; | |
67c0d1eb RS |
4749 | macro_build (&expr1, "bne", "s,t,p", treg, 0); |
4750 | macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg); | |
4751 | macro_build (NULL, "break", "c", 7); | |
252b5132 RH |
4752 | } |
4753 | expr1.X_add_number = -1; | |
8fc2e39e | 4754 | used_at = 1; |
f6a22291 | 4755 | load_register (AT, &expr1, dbl); |
252b5132 | 4756 | expr1.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16); |
67c0d1eb | 4757 | macro_build (&expr1, "bne", "s,t,p", treg, AT); |
252b5132 RH |
4758 | if (dbl) |
4759 | { | |
4760 | expr1.X_add_number = 1; | |
f6a22291 | 4761 | load_register (AT, &expr1, dbl); |
67c0d1eb | 4762 | macro_build (NULL, "dsll32", "d,w,<", AT, AT, 31); |
252b5132 RH |
4763 | } |
4764 | else | |
4765 | { | |
4766 | expr1.X_add_number = 0x80000000; | |
67c0d1eb | 4767 | macro_build (&expr1, "lui", "t,u", AT, BFD_RELOC_HI16); |
252b5132 RH |
4768 | } |
4769 | if (mips_trap) | |
4770 | { | |
67c0d1eb | 4771 | macro_build (NULL, "teq", "s,t,q", sreg, AT, 6); |
252b5132 RH |
4772 | /* We want to close the noreorder block as soon as possible, so |
4773 | that later insns are available for delay slot filling. */ | |
7d10b47d | 4774 | end_noreorder (); |
252b5132 RH |
4775 | } |
4776 | else | |
4777 | { | |
4778 | expr1.X_add_number = 8; | |
67c0d1eb RS |
4779 | macro_build (&expr1, "bne", "s,t,p", sreg, AT); |
4780 | macro_build (NULL, "nop", "", 0); | |
252b5132 RH |
4781 | |
4782 | /* We want to close the noreorder block as soon as possible, so | |
4783 | that later insns are available for delay slot filling. */ | |
7d10b47d | 4784 | end_noreorder (); |
252b5132 | 4785 | |
67c0d1eb | 4786 | macro_build (NULL, "break", "c", 6); |
252b5132 | 4787 | } |
67c0d1eb | 4788 | macro_build (NULL, s, "d", dreg); |
252b5132 RH |
4789 | break; |
4790 | ||
4791 | case M_DIV_3I: | |
4792 | s = "div"; | |
4793 | s2 = "mflo"; | |
4794 | goto do_divi; | |
4795 | case M_DIVU_3I: | |
4796 | s = "divu"; | |
4797 | s2 = "mflo"; | |
4798 | goto do_divi; | |
4799 | case M_REM_3I: | |
4800 | s = "div"; | |
4801 | s2 = "mfhi"; | |
4802 | goto do_divi; | |
4803 | case M_REMU_3I: | |
4804 | s = "divu"; | |
4805 | s2 = "mfhi"; | |
4806 | goto do_divi; | |
4807 | case M_DDIV_3I: | |
4808 | dbl = 1; | |
4809 | s = "ddiv"; | |
4810 | s2 = "mflo"; | |
4811 | goto do_divi; | |
4812 | case M_DDIVU_3I: | |
4813 | dbl = 1; | |
4814 | s = "ddivu"; | |
4815 | s2 = "mflo"; | |
4816 | goto do_divi; | |
4817 | case M_DREM_3I: | |
4818 | dbl = 1; | |
4819 | s = "ddiv"; | |
4820 | s2 = "mfhi"; | |
4821 | goto do_divi; | |
4822 | case M_DREMU_3I: | |
4823 | dbl = 1; | |
4824 | s = "ddivu"; | |
4825 | s2 = "mfhi"; | |
4826 | do_divi: | |
4827 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4828 | { | |
4829 | as_warn (_("Divide by zero.")); | |
4830 | if (mips_trap) | |
67c0d1eb | 4831 | macro_build (NULL, "teq", "s,t,q", 0, 0, 7); |
252b5132 | 4832 | else |
67c0d1eb | 4833 | macro_build (NULL, "break", "c", 7); |
8fc2e39e | 4834 | break; |
252b5132 RH |
4835 | } |
4836 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4837 | { | |
4838 | if (strcmp (s2, "mflo") == 0) | |
67c0d1eb | 4839 | move_register (dreg, sreg); |
252b5132 | 4840 | else |
67c0d1eb | 4841 | move_register (dreg, 0); |
8fc2e39e | 4842 | break; |
252b5132 RH |
4843 | } |
4844 | if (imm_expr.X_op == O_constant | |
4845 | && imm_expr.X_add_number == -1 | |
4846 | && s[strlen (s) - 1] != 'u') | |
4847 | { | |
4848 | if (strcmp (s2, "mflo") == 0) | |
4849 | { | |
67c0d1eb | 4850 | macro_build (NULL, dbl ? "dneg" : "neg", "d,w", dreg, sreg); |
252b5132 RH |
4851 | } |
4852 | else | |
67c0d1eb | 4853 | move_register (dreg, 0); |
8fc2e39e | 4854 | break; |
252b5132 RH |
4855 | } |
4856 | ||
8fc2e39e | 4857 | used_at = 1; |
67c0d1eb RS |
4858 | load_register (AT, &imm_expr, dbl); |
4859 | macro_build (NULL, s, "z,s,t", sreg, AT); | |
4860 | macro_build (NULL, s2, "d", dreg); | |
252b5132 RH |
4861 | break; |
4862 | ||
4863 | case M_DIVU_3: | |
4864 | s = "divu"; | |
4865 | s2 = "mflo"; | |
4866 | goto do_divu3; | |
4867 | case M_REMU_3: | |
4868 | s = "divu"; | |
4869 | s2 = "mfhi"; | |
4870 | goto do_divu3; | |
4871 | case M_DDIVU_3: | |
4872 | s = "ddivu"; | |
4873 | s2 = "mflo"; | |
4874 | goto do_divu3; | |
4875 | case M_DREMU_3: | |
4876 | s = "ddivu"; | |
4877 | s2 = "mfhi"; | |
4878 | do_divu3: | |
7d10b47d | 4879 | start_noreorder (); |
252b5132 RH |
4880 | if (mips_trap) |
4881 | { | |
67c0d1eb RS |
4882 | macro_build (NULL, "teq", "s,t,q", treg, 0, 7); |
4883 | macro_build (NULL, s, "z,s,t", sreg, treg); | |
252b5132 RH |
4884 | /* We want to close the noreorder block as soon as possible, so |
4885 | that later insns are available for delay slot filling. */ | |
7d10b47d | 4886 | end_noreorder (); |
252b5132 RH |
4887 | } |
4888 | else | |
4889 | { | |
4890 | expr1.X_add_number = 8; | |
67c0d1eb RS |
4891 | macro_build (&expr1, "bne", "s,t,p", treg, 0); |
4892 | macro_build (NULL, s, "z,s,t", sreg, treg); | |
252b5132 RH |
4893 | |
4894 | /* We want to close the noreorder block as soon as possible, so | |
4895 | that later insns are available for delay slot filling. */ | |
7d10b47d | 4896 | end_noreorder (); |
67c0d1eb | 4897 | macro_build (NULL, "break", "c", 7); |
252b5132 | 4898 | } |
67c0d1eb | 4899 | macro_build (NULL, s2, "d", dreg); |
8fc2e39e | 4900 | break; |
252b5132 | 4901 | |
1abe91b1 MR |
4902 | case M_DLCA_AB: |
4903 | dbl = 1; | |
4904 | case M_LCA_AB: | |
4905 | call = 1; | |
4906 | goto do_la; | |
252b5132 RH |
4907 | case M_DLA_AB: |
4908 | dbl = 1; | |
4909 | case M_LA_AB: | |
1abe91b1 | 4910 | do_la: |
252b5132 RH |
4911 | /* Load the address of a symbol into a register. If breg is not |
4912 | zero, we then add a base register to it. */ | |
4913 | ||
3bec30a8 TS |
4914 | if (dbl && HAVE_32BIT_GPRS) |
4915 | as_warn (_("dla used to load 32-bit register")); | |
4916 | ||
c90bbe5b | 4917 | if (! dbl && HAVE_64BIT_OBJECTS) |
3bec30a8 TS |
4918 | as_warn (_("la used to load 64-bit address")); |
4919 | ||
0c11417f MR |
4920 | if (offset_expr.X_op == O_constant |
4921 | && offset_expr.X_add_number >= -0x8000 | |
4922 | && offset_expr.X_add_number < 0x8000) | |
4923 | { | |
aed1a261 | 4924 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, |
17a2f251 | 4925 | "t,r,j", treg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 4926 | break; |
0c11417f MR |
4927 | } |
4928 | ||
b8285c27 | 4929 | if (!mips_opts.noat && (treg == breg)) |
afdbd6d0 CD |
4930 | { |
4931 | tempreg = AT; | |
4932 | used_at = 1; | |
4933 | } | |
4934 | else | |
4935 | { | |
4936 | tempreg = treg; | |
afdbd6d0 CD |
4937 | } |
4938 | ||
252b5132 RH |
4939 | if (offset_expr.X_op != O_symbol |
4940 | && offset_expr.X_op != O_constant) | |
4941 | { | |
4942 | as_bad (_("expression too complex")); | |
4943 | offset_expr.X_op = O_constant; | |
4944 | } | |
4945 | ||
252b5132 | 4946 | if (offset_expr.X_op == O_constant) |
aed1a261 | 4947 | load_register (tempreg, &offset_expr, HAVE_64BIT_ADDRESSES); |
252b5132 RH |
4948 | else if (mips_pic == NO_PIC) |
4949 | { | |
d6bc6245 | 4950 | /* If this is a reference to a GP relative symbol, we want |
cdf6fd85 | 4951 | addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
4952 | Otherwise we want |
4953 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
4954 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
4955 | If we have a constant, we need two instructions anyhow, | |
d6bc6245 | 4956 | so we may as well always use the latter form. |
76b3015f | 4957 | |
6caf9ef4 TS |
4958 | With 64bit address space and a usable $at we want |
4959 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
4960 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
4961 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
4962 | daddiu $at,<sym> (BFD_RELOC_LO16) | |
4963 | dsll32 $tempreg,0 | |
4964 | daddu $tempreg,$tempreg,$at | |
4965 | ||
4966 | If $at is already in use, we use a path which is suboptimal | |
4967 | on superscalar processors. | |
4968 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
4969 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
4970 | dsll $tempreg,16 | |
4971 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
4972 | dsll $tempreg,16 | |
4973 | daddiu $tempreg,<sym> (BFD_RELOC_LO16) | |
4974 | ||
4975 | For GP relative symbols in 64bit address space we can use | |
4976 | the same sequence as in 32bit address space. */ | |
aed1a261 | 4977 | if (HAVE_64BIT_SYMBOLS) |
252b5132 | 4978 | { |
6caf9ef4 TS |
4979 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
4980 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) | |
4981 | { | |
4982 | relax_start (offset_expr.X_add_symbol); | |
4983 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
4984 | tempreg, mips_gp_register, BFD_RELOC_GPREL16); | |
4985 | relax_switch (); | |
4986 | } | |
d6bc6245 | 4987 | |
b8285c27 | 4988 | if (used_at == 0 && !mips_opts.noat) |
98d3f06f | 4989 | { |
67c0d1eb | 4990 | macro_build (&offset_expr, "lui", "t,u", |
17a2f251 | 4991 | tempreg, BFD_RELOC_MIPS_HIGHEST); |
67c0d1eb | 4992 | macro_build (&offset_expr, "lui", "t,u", |
17a2f251 | 4993 | AT, BFD_RELOC_HI16_S); |
67c0d1eb | 4994 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 4995 | tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); |
67c0d1eb | 4996 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 4997 | AT, AT, BFD_RELOC_LO16); |
67c0d1eb RS |
4998 | macro_build (NULL, "dsll32", "d,w,<", tempreg, tempreg, 0); |
4999 | macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT); | |
98d3f06f KH |
5000 | used_at = 1; |
5001 | } | |
5002 | else | |
5003 | { | |
67c0d1eb | 5004 | macro_build (&offset_expr, "lui", "t,u", |
17a2f251 | 5005 | tempreg, BFD_RELOC_MIPS_HIGHEST); |
67c0d1eb | 5006 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 5007 | tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); |
67c0d1eb RS |
5008 | macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16); |
5009 | macro_build (&offset_expr, "daddiu", "t,r,j", | |
17a2f251 | 5010 | tempreg, tempreg, BFD_RELOC_HI16_S); |
67c0d1eb RS |
5011 | macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16); |
5012 | macro_build (&offset_expr, "daddiu", "t,r,j", | |
17a2f251 | 5013 | tempreg, tempreg, BFD_RELOC_LO16); |
98d3f06f | 5014 | } |
6caf9ef4 TS |
5015 | |
5016 | if (mips_relax.sequence) | |
5017 | relax_end (); | |
98d3f06f KH |
5018 | } |
5019 | else | |
5020 | { | |
5021 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET | |
6caf9ef4 | 5022 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
98d3f06f | 5023 | { |
4d7206a2 | 5024 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
5025 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
5026 | tempreg, mips_gp_register, BFD_RELOC_GPREL16); | |
4d7206a2 | 5027 | relax_switch (); |
98d3f06f | 5028 | } |
6943caf0 ILT |
5029 | if (!IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) |
5030 | as_bad (_("offset too large")); | |
67c0d1eb RS |
5031 | macro_build_lui (&offset_expr, tempreg); |
5032 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
5033 | tempreg, tempreg, BFD_RELOC_LO16); | |
4d7206a2 RS |
5034 | if (mips_relax.sequence) |
5035 | relax_end (); | |
98d3f06f | 5036 | } |
252b5132 | 5037 | } |
0a44bf69 | 5038 | else if (!mips_big_got && !HAVE_NEWABI) |
252b5132 | 5039 | { |
9117d219 NC |
5040 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
5041 | ||
252b5132 RH |
5042 | /* If this is a reference to an external symbol, and there |
5043 | is no constant, we want | |
5044 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
1abe91b1 | 5045 | or for lca or if tempreg is PIC_CALL_REG |
9117d219 | 5046 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
252b5132 RH |
5047 | For a local symbol, we want |
5048 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5049 | nop | |
5050 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
5051 | ||
5052 | If we have a small constant, and this is a reference to | |
5053 | an external symbol, we want | |
5054 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5055 | nop | |
5056 | addiu $tempreg,$tempreg,<constant> | |
5057 | For a local symbol, we want the same instruction | |
5058 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
5059 | addiu instruction. | |
5060 | ||
5061 | If we have a large constant, and this is a reference to | |
5062 | an external symbol, we want | |
5063 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5064 | lui $at,<hiconstant> | |
5065 | addiu $at,$at,<loconstant> | |
5066 | addu $tempreg,$tempreg,$at | |
5067 | For a local symbol, we want the same instruction | |
5068 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
ed6fb7bd | 5069 | addiu instruction. |
ed6fb7bd SC |
5070 | */ |
5071 | ||
4d7206a2 | 5072 | if (offset_expr.X_add_number == 0) |
252b5132 | 5073 | { |
0a44bf69 RS |
5074 | if (mips_pic == SVR4_PIC |
5075 | && breg == 0 | |
5076 | && (call || tempreg == PIC_CALL_REG)) | |
4d7206a2 RS |
5077 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16; |
5078 | ||
5079 | relax_start (offset_expr.X_add_symbol); | |
67c0d1eb RS |
5080 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5081 | lw_reloc_type, mips_gp_register); | |
4d7206a2 | 5082 | if (breg != 0) |
252b5132 RH |
5083 | { |
5084 | /* We're going to put in an addu instruction using | |
5085 | tempreg, so we may as well insert the nop right | |
5086 | now. */ | |
269137b2 | 5087 | load_delay_nop (); |
252b5132 | 5088 | } |
4d7206a2 | 5089 | relax_switch (); |
67c0d1eb RS |
5090 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5091 | tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 5092 | load_delay_nop (); |
67c0d1eb RS |
5093 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
5094 | tempreg, tempreg, BFD_RELOC_LO16); | |
4d7206a2 | 5095 | relax_end (); |
252b5132 RH |
5096 | /* FIXME: If breg == 0, and the next instruction uses |
5097 | $tempreg, then if this variant case is used an extra | |
5098 | nop will be generated. */ | |
5099 | } | |
4d7206a2 RS |
5100 | else if (offset_expr.X_add_number >= -0x8000 |
5101 | && offset_expr.X_add_number < 0x8000) | |
252b5132 | 5102 | { |
67c0d1eb | 5103 | load_got_offset (tempreg, &offset_expr); |
269137b2 | 5104 | load_delay_nop (); |
67c0d1eb | 5105 | add_got_offset (tempreg, &offset_expr); |
252b5132 RH |
5106 | } |
5107 | else | |
5108 | { | |
4d7206a2 RS |
5109 | expr1.X_add_number = offset_expr.X_add_number; |
5110 | offset_expr.X_add_number = | |
5111 | ((offset_expr.X_add_number + 0x8000) & 0xffff) - 0x8000; | |
67c0d1eb | 5112 | load_got_offset (tempreg, &offset_expr); |
f6a22291 | 5113 | offset_expr.X_add_number = expr1.X_add_number; |
252b5132 RH |
5114 | /* If we are going to add in a base register, and the |
5115 | target register and the base register are the same, | |
5116 | then we are using AT as a temporary register. Since | |
5117 | we want to load the constant into AT, we add our | |
5118 | current AT (from the global offset table) and the | |
5119 | register into the register now, and pretend we were | |
5120 | not using a base register. */ | |
67c0d1eb | 5121 | if (breg == treg) |
252b5132 | 5122 | { |
269137b2 | 5123 | load_delay_nop (); |
67c0d1eb | 5124 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5125 | treg, AT, breg); |
252b5132 RH |
5126 | breg = 0; |
5127 | tempreg = treg; | |
252b5132 | 5128 | } |
f6a22291 | 5129 | add_got_offset_hilo (tempreg, &offset_expr, AT); |
252b5132 RH |
5130 | used_at = 1; |
5131 | } | |
5132 | } | |
0a44bf69 | 5133 | else if (!mips_big_got && HAVE_NEWABI) |
f5040a92 | 5134 | { |
67c0d1eb | 5135 | int add_breg_early = 0; |
f5040a92 AO |
5136 | |
5137 | /* If this is a reference to an external, and there is no | |
5138 | constant, or local symbol (*), with or without a | |
5139 | constant, we want | |
5140 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
1abe91b1 | 5141 | or for lca or if tempreg is PIC_CALL_REG |
f5040a92 AO |
5142 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
5143 | ||
5144 | If we have a small constant, and this is a reference to | |
5145 | an external symbol, we want | |
5146 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
5147 | addiu $tempreg,$tempreg,<constant> | |
5148 | ||
5149 | If we have a large constant, and this is a reference to | |
5150 | an external symbol, we want | |
5151 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
5152 | lui $at,<hiconstant> | |
5153 | addiu $at,$at,<loconstant> | |
5154 | addu $tempreg,$tempreg,$at | |
5155 | ||
5156 | (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for | |
5157 | local symbols, even though it introduces an additional | |
5158 | instruction. */ | |
5159 | ||
f5040a92 AO |
5160 | if (offset_expr.X_add_number) |
5161 | { | |
4d7206a2 | 5162 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
5163 | offset_expr.X_add_number = 0; |
5164 | ||
4d7206a2 | 5165 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
5166 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5167 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
5168 | |
5169 | if (expr1.X_add_number >= -0x8000 | |
5170 | && expr1.X_add_number < 0x8000) | |
5171 | { | |
67c0d1eb RS |
5172 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
5173 | tempreg, tempreg, BFD_RELOC_LO16); | |
f5040a92 | 5174 | } |
ecd13cd3 | 5175 | else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000)) |
f5040a92 AO |
5176 | { |
5177 | int dreg; | |
5178 | ||
5179 | /* If we are going to add in a base register, and the | |
5180 | target register and the base register are the same, | |
5181 | then we are using AT as a temporary register. Since | |
5182 | we want to load the constant into AT, we add our | |
5183 | current AT (from the global offset table) and the | |
5184 | register into the register now, and pretend we were | |
5185 | not using a base register. */ | |
5186 | if (breg != treg) | |
5187 | dreg = tempreg; | |
5188 | else | |
5189 | { | |
5190 | assert (tempreg == AT); | |
67c0d1eb RS |
5191 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
5192 | treg, AT, breg); | |
f5040a92 | 5193 | dreg = treg; |
67c0d1eb | 5194 | add_breg_early = 1; |
f5040a92 AO |
5195 | } |
5196 | ||
f6a22291 | 5197 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 5198 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5199 | dreg, dreg, AT); |
f5040a92 | 5200 | |
f5040a92 AO |
5201 | used_at = 1; |
5202 | } | |
5203 | else | |
5204 | as_bad (_("PIC code offset overflow (max 32 signed bits)")); | |
5205 | ||
4d7206a2 | 5206 | relax_switch (); |
f5040a92 AO |
5207 | offset_expr.X_add_number = expr1.X_add_number; |
5208 | ||
67c0d1eb RS |
5209 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5210 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
5211 | if (add_breg_early) | |
f5040a92 | 5212 | { |
67c0d1eb | 5213 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
f899b4b8 | 5214 | treg, tempreg, breg); |
f5040a92 AO |
5215 | breg = 0; |
5216 | tempreg = treg; | |
5217 | } | |
4d7206a2 | 5218 | relax_end (); |
f5040a92 | 5219 | } |
4d7206a2 | 5220 | else if (breg == 0 && (call || tempreg == PIC_CALL_REG)) |
f5040a92 | 5221 | { |
4d7206a2 | 5222 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
5223 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5224 | BFD_RELOC_MIPS_CALL16, mips_gp_register); | |
4d7206a2 | 5225 | relax_switch (); |
67c0d1eb RS |
5226 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5227 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
4d7206a2 | 5228 | relax_end (); |
f5040a92 | 5229 | } |
4d7206a2 | 5230 | else |
f5040a92 | 5231 | { |
67c0d1eb RS |
5232 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5233 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
5234 | } |
5235 | } | |
0a44bf69 | 5236 | else if (mips_big_got && !HAVE_NEWABI) |
252b5132 | 5237 | { |
67c0d1eb | 5238 | int gpdelay; |
9117d219 NC |
5239 | int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; |
5240 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; | |
ed6fb7bd | 5241 | int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
252b5132 RH |
5242 | |
5243 | /* This is the large GOT case. If this is a reference to an | |
5244 | external symbol, and there is no constant, we want | |
5245 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5246 | addu $tempreg,$tempreg,$gp | |
5247 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
1abe91b1 | 5248 | or for lca or if tempreg is PIC_CALL_REG |
9117d219 NC |
5249 | lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) |
5250 | addu $tempreg,$tempreg,$gp | |
5251 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) | |
252b5132 RH |
5252 | For a local symbol, we want |
5253 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5254 | nop | |
5255 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
5256 | ||
5257 | If we have a small constant, and this is a reference to | |
5258 | an external symbol, we want | |
5259 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5260 | addu $tempreg,$tempreg,$gp | |
5261 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5262 | nop | |
5263 | addiu $tempreg,$tempreg,<constant> | |
5264 | For a local symbol, we want | |
5265 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5266 | nop | |
5267 | addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16) | |
5268 | ||
5269 | If we have a large constant, and this is a reference to | |
5270 | an external symbol, we want | |
5271 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5272 | addu $tempreg,$tempreg,$gp | |
5273 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5274 | lui $at,<hiconstant> | |
5275 | addiu $at,$at,<loconstant> | |
5276 | addu $tempreg,$tempreg,$at | |
5277 | For a local symbol, we want | |
5278 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5279 | lui $at,<hiconstant> | |
5280 | addiu $at,$at,<loconstant> (BFD_RELOC_LO16) | |
5281 | addu $tempreg,$tempreg,$at | |
f5040a92 | 5282 | */ |
438c16b8 | 5283 | |
252b5132 RH |
5284 | expr1.X_add_number = offset_expr.X_add_number; |
5285 | offset_expr.X_add_number = 0; | |
4d7206a2 | 5286 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 5287 | gpdelay = reg_needs_delay (mips_gp_register); |
1abe91b1 MR |
5288 | if (expr1.X_add_number == 0 && breg == 0 |
5289 | && (call || tempreg == PIC_CALL_REG)) | |
9117d219 NC |
5290 | { |
5291 | lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; | |
5292 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; | |
5293 | } | |
67c0d1eb RS |
5294 | macro_build (&offset_expr, "lui", "t,u", tempreg, lui_reloc_type); |
5295 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 5296 | tempreg, tempreg, mips_gp_register); |
67c0d1eb | 5297 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
17a2f251 | 5298 | tempreg, lw_reloc_type, tempreg); |
252b5132 RH |
5299 | if (expr1.X_add_number == 0) |
5300 | { | |
67c0d1eb | 5301 | if (breg != 0) |
252b5132 RH |
5302 | { |
5303 | /* We're going to put in an addu instruction using | |
5304 | tempreg, so we may as well insert the nop right | |
5305 | now. */ | |
269137b2 | 5306 | load_delay_nop (); |
252b5132 | 5307 | } |
252b5132 RH |
5308 | } |
5309 | else if (expr1.X_add_number >= -0x8000 | |
5310 | && expr1.X_add_number < 0x8000) | |
5311 | { | |
269137b2 | 5312 | load_delay_nop (); |
67c0d1eb | 5313 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 5314 | tempreg, tempreg, BFD_RELOC_LO16); |
252b5132 RH |
5315 | } |
5316 | else | |
5317 | { | |
67c0d1eb | 5318 | int dreg; |
252b5132 RH |
5319 | |
5320 | /* If we are going to add in a base register, and the | |
5321 | target register and the base register are the same, | |
5322 | then we are using AT as a temporary register. Since | |
5323 | we want to load the constant into AT, we add our | |
5324 | current AT (from the global offset table) and the | |
5325 | register into the register now, and pretend we were | |
5326 | not using a base register. */ | |
5327 | if (breg != treg) | |
67c0d1eb | 5328 | dreg = tempreg; |
252b5132 RH |
5329 | else |
5330 | { | |
5331 | assert (tempreg == AT); | |
269137b2 | 5332 | load_delay_nop (); |
67c0d1eb | 5333 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5334 | treg, AT, breg); |
252b5132 | 5335 | dreg = treg; |
252b5132 RH |
5336 | } |
5337 | ||
f6a22291 | 5338 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 5339 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT); |
252b5132 | 5340 | |
252b5132 RH |
5341 | used_at = 1; |
5342 | } | |
4d7206a2 RS |
5343 | offset_expr.X_add_number = |
5344 | ((expr1.X_add_number + 0x8000) & 0xffff) - 0x8000; | |
5345 | relax_switch (); | |
252b5132 | 5346 | |
67c0d1eb | 5347 | if (gpdelay) |
252b5132 RH |
5348 | { |
5349 | /* This is needed because this instruction uses $gp, but | |
f5040a92 | 5350 | the first instruction on the main stream does not. */ |
67c0d1eb | 5351 | macro_build (NULL, "nop", ""); |
252b5132 | 5352 | } |
ed6fb7bd | 5353 | |
67c0d1eb RS |
5354 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5355 | local_reloc_type, mips_gp_register); | |
f5040a92 | 5356 | if (expr1.X_add_number >= -0x8000 |
252b5132 RH |
5357 | && expr1.X_add_number < 0x8000) |
5358 | { | |
269137b2 | 5359 | load_delay_nop (); |
67c0d1eb RS |
5360 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
5361 | tempreg, tempreg, BFD_RELOC_LO16); | |
252b5132 | 5362 | /* FIXME: If add_number is 0, and there was no base |
f5040a92 AO |
5363 | register, the external symbol case ended with a load, |
5364 | so if the symbol turns out to not be external, and | |
5365 | the next instruction uses tempreg, an unnecessary nop | |
5366 | will be inserted. */ | |
252b5132 RH |
5367 | } |
5368 | else | |
5369 | { | |
5370 | if (breg == treg) | |
5371 | { | |
5372 | /* We must add in the base register now, as in the | |
f5040a92 | 5373 | external symbol case. */ |
252b5132 | 5374 | assert (tempreg == AT); |
269137b2 | 5375 | load_delay_nop (); |
67c0d1eb | 5376 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5377 | treg, AT, breg); |
252b5132 RH |
5378 | tempreg = treg; |
5379 | /* We set breg to 0 because we have arranged to add | |
f5040a92 | 5380 | it in in both cases. */ |
252b5132 RH |
5381 | breg = 0; |
5382 | } | |
5383 | ||
67c0d1eb RS |
5384 | macro_build_lui (&expr1, AT); |
5385 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
17a2f251 | 5386 | AT, AT, BFD_RELOC_LO16); |
67c0d1eb | 5387 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5388 | tempreg, tempreg, AT); |
8fc2e39e | 5389 | used_at = 1; |
252b5132 | 5390 | } |
4d7206a2 | 5391 | relax_end (); |
252b5132 | 5392 | } |
0a44bf69 | 5393 | else if (mips_big_got && HAVE_NEWABI) |
f5040a92 | 5394 | { |
f5040a92 AO |
5395 | int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; |
5396 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; | |
67c0d1eb | 5397 | int add_breg_early = 0; |
f5040a92 AO |
5398 | |
5399 | /* This is the large GOT case. If this is a reference to an | |
5400 | external symbol, and there is no constant, we want | |
5401 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5402 | add $tempreg,$tempreg,$gp | |
5403 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
1abe91b1 | 5404 | or for lca or if tempreg is PIC_CALL_REG |
f5040a92 AO |
5405 | lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) |
5406 | add $tempreg,$tempreg,$gp | |
5407 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) | |
5408 | ||
5409 | If we have a small constant, and this is a reference to | |
5410 | an external symbol, we want | |
5411 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5412 | add $tempreg,$tempreg,$gp | |
5413 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5414 | addi $tempreg,$tempreg,<constant> | |
5415 | ||
5416 | If we have a large constant, and this is a reference to | |
5417 | an external symbol, we want | |
5418 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5419 | addu $tempreg,$tempreg,$gp | |
5420 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5421 | lui $at,<hiconstant> | |
5422 | addi $at,$at,<loconstant> | |
5423 | add $tempreg,$tempreg,$at | |
5424 | ||
5425 | If we have NewABI, and we know it's a local symbol, we want | |
5426 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
5427 | addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) | |
5428 | otherwise we have to resort to GOT_HI16/GOT_LO16. */ | |
5429 | ||
4d7206a2 | 5430 | relax_start (offset_expr.X_add_symbol); |
f5040a92 | 5431 | |
4d7206a2 | 5432 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
5433 | offset_expr.X_add_number = 0; |
5434 | ||
1abe91b1 MR |
5435 | if (expr1.X_add_number == 0 && breg == 0 |
5436 | && (call || tempreg == PIC_CALL_REG)) | |
f5040a92 AO |
5437 | { |
5438 | lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; | |
5439 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; | |
5440 | } | |
67c0d1eb RS |
5441 | macro_build (&offset_expr, "lui", "t,u", tempreg, lui_reloc_type); |
5442 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 5443 | tempreg, tempreg, mips_gp_register); |
67c0d1eb RS |
5444 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5445 | tempreg, lw_reloc_type, tempreg); | |
f5040a92 AO |
5446 | |
5447 | if (expr1.X_add_number == 0) | |
4d7206a2 | 5448 | ; |
f5040a92 AO |
5449 | else if (expr1.X_add_number >= -0x8000 |
5450 | && expr1.X_add_number < 0x8000) | |
5451 | { | |
67c0d1eb | 5452 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 5453 | tempreg, tempreg, BFD_RELOC_LO16); |
f5040a92 | 5454 | } |
ecd13cd3 | 5455 | else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000)) |
f5040a92 AO |
5456 | { |
5457 | int dreg; | |
5458 | ||
5459 | /* If we are going to add in a base register, and the | |
5460 | target register and the base register are the same, | |
5461 | then we are using AT as a temporary register. Since | |
5462 | we want to load the constant into AT, we add our | |
5463 | current AT (from the global offset table) and the | |
5464 | register into the register now, and pretend we were | |
5465 | not using a base register. */ | |
5466 | if (breg != treg) | |
5467 | dreg = tempreg; | |
5468 | else | |
5469 | { | |
5470 | assert (tempreg == AT); | |
67c0d1eb | 5471 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5472 | treg, AT, breg); |
f5040a92 | 5473 | dreg = treg; |
67c0d1eb | 5474 | add_breg_early = 1; |
f5040a92 AO |
5475 | } |
5476 | ||
f6a22291 | 5477 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 5478 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT); |
f5040a92 | 5479 | |
f5040a92 AO |
5480 | used_at = 1; |
5481 | } | |
5482 | else | |
5483 | as_bad (_("PIC code offset overflow (max 32 signed bits)")); | |
5484 | ||
4d7206a2 | 5485 | relax_switch (); |
f5040a92 | 5486 | offset_expr.X_add_number = expr1.X_add_number; |
67c0d1eb RS |
5487 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5488 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
5489 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, | |
5490 | tempreg, BFD_RELOC_MIPS_GOT_OFST); | |
5491 | if (add_breg_early) | |
f5040a92 | 5492 | { |
67c0d1eb | 5493 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5494 | treg, tempreg, breg); |
f5040a92 AO |
5495 | breg = 0; |
5496 | tempreg = treg; | |
5497 | } | |
4d7206a2 | 5498 | relax_end (); |
f5040a92 | 5499 | } |
252b5132 RH |
5500 | else |
5501 | abort (); | |
5502 | ||
5503 | if (breg != 0) | |
aed1a261 | 5504 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", treg, tempreg, breg); |
252b5132 RH |
5505 | break; |
5506 | ||
5507 | case M_J_A: | |
5508 | /* The j instruction may not be used in PIC code, since it | |
5509 | requires an absolute address. We convert it to a b | |
5510 | instruction. */ | |
5511 | if (mips_pic == NO_PIC) | |
67c0d1eb | 5512 | macro_build (&offset_expr, "j", "a"); |
252b5132 | 5513 | else |
67c0d1eb | 5514 | macro_build (&offset_expr, "b", "p"); |
8fc2e39e | 5515 | break; |
252b5132 RH |
5516 | |
5517 | /* The jal instructions must be handled as macros because when | |
5518 | generating PIC code they expand to multi-instruction | |
5519 | sequences. Normally they are simple instructions. */ | |
5520 | case M_JAL_1: | |
5521 | dreg = RA; | |
5522 | /* Fall through. */ | |
5523 | case M_JAL_2: | |
3e722fb5 | 5524 | if (mips_pic == NO_PIC) |
67c0d1eb | 5525 | macro_build (NULL, "jalr", "d,s", dreg, sreg); |
0a44bf69 | 5526 | else |
252b5132 RH |
5527 | { |
5528 | if (sreg != PIC_CALL_REG) | |
5529 | as_warn (_("MIPS PIC call to register other than $25")); | |
bdaaa2e1 | 5530 | |
67c0d1eb | 5531 | macro_build (NULL, "jalr", "d,s", dreg, sreg); |
0a44bf69 | 5532 | if (mips_pic == SVR4_PIC && !HAVE_NEWABI) |
252b5132 | 5533 | { |
6478892d TS |
5534 | if (mips_cprestore_offset < 0) |
5535 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
5536 | else | |
5537 | { | |
7a621144 DJ |
5538 | if (! mips_frame_reg_valid) |
5539 | { | |
5540 | as_warn (_("No .frame pseudo-op used in PIC code")); | |
5541 | /* Quiet this warning. */ | |
5542 | mips_frame_reg_valid = 1; | |
5543 | } | |
5544 | if (! mips_cprestore_valid) | |
5545 | { | |
5546 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
5547 | /* Quiet this warning. */ | |
5548 | mips_cprestore_valid = 1; | |
5549 | } | |
6478892d | 5550 | expr1.X_add_number = mips_cprestore_offset; |
67c0d1eb | 5551 | macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN, |
f899b4b8 | 5552 | mips_gp_register, |
256ab948 TS |
5553 | mips_frame_reg, |
5554 | HAVE_64BIT_ADDRESSES); | |
6478892d | 5555 | } |
252b5132 RH |
5556 | } |
5557 | } | |
252b5132 | 5558 | |
8fc2e39e | 5559 | break; |
252b5132 RH |
5560 | |
5561 | case M_JAL_A: | |
5562 | if (mips_pic == NO_PIC) | |
67c0d1eb | 5563 | macro_build (&offset_expr, "jal", "a"); |
252b5132 RH |
5564 | else if (mips_pic == SVR4_PIC) |
5565 | { | |
5566 | /* If this is a reference to an external symbol, and we are | |
5567 | using a small GOT, we want | |
5568 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16) | |
5569 | nop | |
f9419b05 | 5570 | jalr $ra,$25 |
252b5132 RH |
5571 | nop |
5572 | lw $gp,cprestore($sp) | |
5573 | The cprestore value is set using the .cprestore | |
5574 | pseudo-op. If we are using a big GOT, we want | |
5575 | lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16) | |
5576 | addu $25,$25,$gp | |
5577 | lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16) | |
5578 | nop | |
f9419b05 | 5579 | jalr $ra,$25 |
252b5132 RH |
5580 | nop |
5581 | lw $gp,cprestore($sp) | |
5582 | If the symbol is not external, we want | |
5583 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5584 | nop | |
5585 | addiu $25,$25,<sym> (BFD_RELOC_LO16) | |
f9419b05 | 5586 | jalr $ra,$25 |
252b5132 | 5587 | nop |
438c16b8 | 5588 | lw $gp,cprestore($sp) |
f5040a92 AO |
5589 | |
5590 | For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16 | |
5591 | sequences above, minus nops, unless the symbol is local, | |
5592 | which enables us to use GOT_PAGE/GOT_OFST (big got) or | |
5593 | GOT_DISP. */ | |
438c16b8 | 5594 | if (HAVE_NEWABI) |
252b5132 | 5595 | { |
f5040a92 AO |
5596 | if (! mips_big_got) |
5597 | { | |
4d7206a2 | 5598 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
5599 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5600 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL16, | |
f5040a92 | 5601 | mips_gp_register); |
4d7206a2 | 5602 | relax_switch (); |
67c0d1eb RS |
5603 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5604 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT_DISP, | |
4d7206a2 RS |
5605 | mips_gp_register); |
5606 | relax_end (); | |
f5040a92 AO |
5607 | } |
5608 | else | |
5609 | { | |
4d7206a2 | 5610 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
5611 | macro_build (&offset_expr, "lui", "t,u", PIC_CALL_REG, |
5612 | BFD_RELOC_MIPS_CALL_HI16); | |
5613 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG, | |
5614 | PIC_CALL_REG, mips_gp_register); | |
5615 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", | |
5616 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16, | |
5617 | PIC_CALL_REG); | |
4d7206a2 | 5618 | relax_switch (); |
67c0d1eb RS |
5619 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5620 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT_PAGE, | |
5621 | mips_gp_register); | |
5622 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
5623 | PIC_CALL_REG, PIC_CALL_REG, | |
17a2f251 | 5624 | BFD_RELOC_MIPS_GOT_OFST); |
4d7206a2 | 5625 | relax_end (); |
f5040a92 | 5626 | } |
684022ea | 5627 | |
67c0d1eb | 5628 | macro_build_jalr (&offset_expr); |
252b5132 RH |
5629 | } |
5630 | else | |
5631 | { | |
4d7206a2 | 5632 | relax_start (offset_expr.X_add_symbol); |
438c16b8 TS |
5633 | if (! mips_big_got) |
5634 | { | |
67c0d1eb RS |
5635 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5636 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL16, | |
17a2f251 | 5637 | mips_gp_register); |
269137b2 | 5638 | load_delay_nop (); |
4d7206a2 | 5639 | relax_switch (); |
438c16b8 | 5640 | } |
252b5132 | 5641 | else |
252b5132 | 5642 | { |
67c0d1eb RS |
5643 | int gpdelay; |
5644 | ||
5645 | gpdelay = reg_needs_delay (mips_gp_register); | |
5646 | macro_build (&offset_expr, "lui", "t,u", PIC_CALL_REG, | |
5647 | BFD_RELOC_MIPS_CALL_HI16); | |
5648 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG, | |
5649 | PIC_CALL_REG, mips_gp_register); | |
5650 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", | |
5651 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16, | |
5652 | PIC_CALL_REG); | |
269137b2 | 5653 | load_delay_nop (); |
4d7206a2 | 5654 | relax_switch (); |
67c0d1eb RS |
5655 | if (gpdelay) |
5656 | macro_build (NULL, "nop", ""); | |
252b5132 | 5657 | } |
67c0d1eb RS |
5658 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5659 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT16, | |
4d7206a2 | 5660 | mips_gp_register); |
269137b2 | 5661 | load_delay_nop (); |
67c0d1eb RS |
5662 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
5663 | PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16); | |
4d7206a2 | 5664 | relax_end (); |
67c0d1eb | 5665 | macro_build_jalr (&offset_expr); |
438c16b8 | 5666 | |
6478892d TS |
5667 | if (mips_cprestore_offset < 0) |
5668 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
5669 | else | |
5670 | { | |
7a621144 DJ |
5671 | if (! mips_frame_reg_valid) |
5672 | { | |
5673 | as_warn (_("No .frame pseudo-op used in PIC code")); | |
5674 | /* Quiet this warning. */ | |
5675 | mips_frame_reg_valid = 1; | |
5676 | } | |
5677 | if (! mips_cprestore_valid) | |
5678 | { | |
5679 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
5680 | /* Quiet this warning. */ | |
5681 | mips_cprestore_valid = 1; | |
5682 | } | |
6478892d | 5683 | if (mips_opts.noreorder) |
67c0d1eb | 5684 | macro_build (NULL, "nop", ""); |
6478892d | 5685 | expr1.X_add_number = mips_cprestore_offset; |
67c0d1eb | 5686 | macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN, |
f899b4b8 | 5687 | mips_gp_register, |
256ab948 TS |
5688 | mips_frame_reg, |
5689 | HAVE_64BIT_ADDRESSES); | |
6478892d | 5690 | } |
252b5132 RH |
5691 | } |
5692 | } | |
0a44bf69 RS |
5693 | else if (mips_pic == VXWORKS_PIC) |
5694 | as_bad (_("Non-PIC jump used in PIC library")); | |
252b5132 RH |
5695 | else |
5696 | abort (); | |
5697 | ||
8fc2e39e | 5698 | break; |
252b5132 RH |
5699 | |
5700 | case M_LB_AB: | |
5701 | s = "lb"; | |
5702 | goto ld; | |
5703 | case M_LBU_AB: | |
5704 | s = "lbu"; | |
5705 | goto ld; | |
5706 | case M_LH_AB: | |
5707 | s = "lh"; | |
5708 | goto ld; | |
5709 | case M_LHU_AB: | |
5710 | s = "lhu"; | |
5711 | goto ld; | |
5712 | case M_LW_AB: | |
5713 | s = "lw"; | |
5714 | goto ld; | |
5715 | case M_LWC0_AB: | |
5716 | s = "lwc0"; | |
bdaaa2e1 | 5717 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5718 | coproc = 1; |
5719 | goto ld; | |
5720 | case M_LWC1_AB: | |
5721 | s = "lwc1"; | |
bdaaa2e1 | 5722 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5723 | coproc = 1; |
5724 | goto ld; | |
5725 | case M_LWC2_AB: | |
5726 | s = "lwc2"; | |
bdaaa2e1 | 5727 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5728 | coproc = 1; |
5729 | goto ld; | |
5730 | case M_LWC3_AB: | |
5731 | s = "lwc3"; | |
bdaaa2e1 | 5732 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5733 | coproc = 1; |
5734 | goto ld; | |
5735 | case M_LWL_AB: | |
5736 | s = "lwl"; | |
5737 | lr = 1; | |
5738 | goto ld; | |
5739 | case M_LWR_AB: | |
5740 | s = "lwr"; | |
5741 | lr = 1; | |
5742 | goto ld; | |
5743 | case M_LDC1_AB: | |
fef14a42 | 5744 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
5745 | { |
5746 | as_bad (_("opcode not supported on this processor")); | |
8fc2e39e | 5747 | break; |
252b5132 RH |
5748 | } |
5749 | s = "ldc1"; | |
bdaaa2e1 | 5750 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5751 | coproc = 1; |
5752 | goto ld; | |
5753 | case M_LDC2_AB: | |
5754 | s = "ldc2"; | |
bdaaa2e1 | 5755 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5756 | coproc = 1; |
5757 | goto ld; | |
5758 | case M_LDC3_AB: | |
5759 | s = "ldc3"; | |
bdaaa2e1 | 5760 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5761 | coproc = 1; |
5762 | goto ld; | |
5763 | case M_LDL_AB: | |
5764 | s = "ldl"; | |
5765 | lr = 1; | |
5766 | goto ld; | |
5767 | case M_LDR_AB: | |
5768 | s = "ldr"; | |
5769 | lr = 1; | |
5770 | goto ld; | |
5771 | case M_LL_AB: | |
5772 | s = "ll"; | |
5773 | goto ld; | |
5774 | case M_LLD_AB: | |
5775 | s = "lld"; | |
5776 | goto ld; | |
5777 | case M_LWU_AB: | |
5778 | s = "lwu"; | |
5779 | ld: | |
8fc2e39e | 5780 | if (breg == treg || coproc || lr) |
252b5132 RH |
5781 | { |
5782 | tempreg = AT; | |
5783 | used_at = 1; | |
5784 | } | |
5785 | else | |
5786 | { | |
5787 | tempreg = treg; | |
252b5132 RH |
5788 | } |
5789 | goto ld_st; | |
5790 | case M_SB_AB: | |
5791 | s = "sb"; | |
5792 | goto st; | |
5793 | case M_SH_AB: | |
5794 | s = "sh"; | |
5795 | goto st; | |
5796 | case M_SW_AB: | |
5797 | s = "sw"; | |
5798 | goto st; | |
5799 | case M_SWC0_AB: | |
5800 | s = "swc0"; | |
bdaaa2e1 | 5801 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5802 | coproc = 1; |
5803 | goto st; | |
5804 | case M_SWC1_AB: | |
5805 | s = "swc1"; | |
bdaaa2e1 | 5806 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5807 | coproc = 1; |
5808 | goto st; | |
5809 | case M_SWC2_AB: | |
5810 | s = "swc2"; | |
bdaaa2e1 | 5811 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5812 | coproc = 1; |
5813 | goto st; | |
5814 | case M_SWC3_AB: | |
5815 | s = "swc3"; | |
bdaaa2e1 | 5816 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5817 | coproc = 1; |
5818 | goto st; | |
5819 | case M_SWL_AB: | |
5820 | s = "swl"; | |
5821 | goto st; | |
5822 | case M_SWR_AB: | |
5823 | s = "swr"; | |
5824 | goto st; | |
5825 | case M_SC_AB: | |
5826 | s = "sc"; | |
5827 | goto st; | |
5828 | case M_SCD_AB: | |
5829 | s = "scd"; | |
5830 | goto st; | |
d43b4baf TS |
5831 | case M_CACHE_AB: |
5832 | s = "cache"; | |
5833 | goto st; | |
252b5132 | 5834 | case M_SDC1_AB: |
fef14a42 | 5835 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
5836 | { |
5837 | as_bad (_("opcode not supported on this processor")); | |
8fc2e39e | 5838 | break; |
252b5132 RH |
5839 | } |
5840 | s = "sdc1"; | |
5841 | coproc = 1; | |
bdaaa2e1 | 5842 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5843 | goto st; |
5844 | case M_SDC2_AB: | |
5845 | s = "sdc2"; | |
bdaaa2e1 | 5846 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5847 | coproc = 1; |
5848 | goto st; | |
5849 | case M_SDC3_AB: | |
5850 | s = "sdc3"; | |
bdaaa2e1 | 5851 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5852 | coproc = 1; |
5853 | goto st; | |
5854 | case M_SDL_AB: | |
5855 | s = "sdl"; | |
5856 | goto st; | |
5857 | case M_SDR_AB: | |
5858 | s = "sdr"; | |
5859 | st: | |
8fc2e39e TS |
5860 | tempreg = AT; |
5861 | used_at = 1; | |
252b5132 | 5862 | ld_st: |
bdaaa2e1 | 5863 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5864 | if (mask == M_LWC1_AB |
5865 | || mask == M_SWC1_AB | |
5866 | || mask == M_LDC1_AB | |
5867 | || mask == M_SDC1_AB | |
5868 | || mask == M_L_DAB | |
5869 | || mask == M_S_DAB) | |
5870 | fmt = "T,o(b)"; | |
d43b4baf TS |
5871 | else if (mask == M_CACHE_AB) |
5872 | fmt = "k,o(b)"; | |
252b5132 RH |
5873 | else if (coproc) |
5874 | fmt = "E,o(b)"; | |
5875 | else | |
5876 | fmt = "t,o(b)"; | |
5877 | ||
5878 | if (offset_expr.X_op != O_constant | |
5879 | && offset_expr.X_op != O_symbol) | |
5880 | { | |
5881 | as_bad (_("expression too complex")); | |
5882 | offset_expr.X_op = O_constant; | |
5883 | } | |
5884 | ||
2051e8c4 MR |
5885 | if (HAVE_32BIT_ADDRESSES |
5886 | && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) | |
55e08f71 NC |
5887 | { |
5888 | char value [32]; | |
5889 | ||
5890 | sprintf_vma (value, offset_expr.X_add_number); | |
20e1fcfd | 5891 | as_bad (_("Number (0x%s) larger than 32 bits"), value); |
55e08f71 | 5892 | } |
2051e8c4 | 5893 | |
252b5132 RH |
5894 | /* A constant expression in PIC code can be handled just as it |
5895 | is in non PIC code. */ | |
aed1a261 RS |
5896 | if (offset_expr.X_op == O_constant) |
5897 | { | |
aed1a261 RS |
5898 | expr1.X_add_number = ((offset_expr.X_add_number + 0x8000) |
5899 | & ~(bfd_vma) 0xffff); | |
2051e8c4 | 5900 | normalize_address_expr (&expr1); |
aed1a261 RS |
5901 | load_register (tempreg, &expr1, HAVE_64BIT_ADDRESSES); |
5902 | if (breg != 0) | |
5903 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
5904 | tempreg, tempreg, breg); | |
5905 | macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, tempreg); | |
5906 | } | |
5907 | else if (mips_pic == NO_PIC) | |
252b5132 RH |
5908 | { |
5909 | /* If this is a reference to a GP relative symbol, and there | |
5910 | is no base register, we want | |
cdf6fd85 | 5911 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
252b5132 RH |
5912 | Otherwise, if there is no base register, we want |
5913 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
5914 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
5915 | If we have a constant, we need two instructions anyhow, | |
5916 | so we always use the latter form. | |
5917 | ||
5918 | If we have a base register, and this is a reference to a | |
5919 | GP relative symbol, we want | |
5920 | addu $tempreg,$breg,$gp | |
cdf6fd85 | 5921 | <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16) |
252b5132 RH |
5922 | Otherwise we want |
5923 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
5924 | addu $tempreg,$tempreg,$breg | |
5925 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
d6bc6245 | 5926 | With a constant we always use the latter case. |
76b3015f | 5927 | |
d6bc6245 TS |
5928 | With 64bit address space and no base register and $at usable, |
5929 | we want | |
5930 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5931 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
5932 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5933 | dsll32 $tempreg,0 | |
5934 | daddu $tempreg,$at | |
5935 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
5936 | If we have a base register, we want | |
5937 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5938 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
5939 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5940 | daddu $at,$breg | |
5941 | dsll32 $tempreg,0 | |
5942 | daddu $tempreg,$at | |
5943 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
5944 | ||
5945 | Without $at we can't generate the optimal path for superscalar | |
5946 | processors here since this would require two temporary registers. | |
5947 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5948 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5949 | dsll $tempreg,16 | |
5950 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
5951 | dsll $tempreg,16 | |
5952 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
5953 | If we have a base register, we want | |
5954 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5955 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5956 | dsll $tempreg,16 | |
5957 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
5958 | dsll $tempreg,16 | |
5959 | daddu $tempreg,$tempreg,$breg | |
5960 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
6373ee54 | 5961 | |
6caf9ef4 | 5962 | For GP relative symbols in 64bit address space we can use |
aed1a261 RS |
5963 | the same sequence as in 32bit address space. */ |
5964 | if (HAVE_64BIT_SYMBOLS) | |
d6bc6245 | 5965 | { |
aed1a261 | 5966 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 TS |
5967 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
5968 | { | |
5969 | relax_start (offset_expr.X_add_symbol); | |
5970 | if (breg == 0) | |
5971 | { | |
5972 | macro_build (&offset_expr, s, fmt, treg, | |
5973 | BFD_RELOC_GPREL16, mips_gp_register); | |
5974 | } | |
5975 | else | |
5976 | { | |
5977 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
5978 | tempreg, breg, mips_gp_register); | |
5979 | macro_build (&offset_expr, s, fmt, treg, | |
5980 | BFD_RELOC_GPREL16, tempreg); | |
5981 | } | |
5982 | relax_switch (); | |
5983 | } | |
d6bc6245 | 5984 | |
b8285c27 | 5985 | if (used_at == 0 && !mips_opts.noat) |
d6bc6245 | 5986 | { |
67c0d1eb RS |
5987 | macro_build (&offset_expr, "lui", "t,u", tempreg, |
5988 | BFD_RELOC_MIPS_HIGHEST); | |
5989 | macro_build (&offset_expr, "lui", "t,u", AT, | |
5990 | BFD_RELOC_HI16_S); | |
5991 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
5992 | tempreg, BFD_RELOC_MIPS_HIGHER); | |
d6bc6245 | 5993 | if (breg != 0) |
67c0d1eb RS |
5994 | macro_build (NULL, "daddu", "d,v,t", AT, AT, breg); |
5995 | macro_build (NULL, "dsll32", "d,w,<", tempreg, tempreg, 0); | |
5996 | macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT); | |
5997 | macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, | |
5998 | tempreg); | |
d6bc6245 TS |
5999 | used_at = 1; |
6000 | } | |
6001 | else | |
6002 | { | |
67c0d1eb RS |
6003 | macro_build (&offset_expr, "lui", "t,u", tempreg, |
6004 | BFD_RELOC_MIPS_HIGHEST); | |
6005 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
6006 | tempreg, BFD_RELOC_MIPS_HIGHER); | |
6007 | macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16); | |
6008 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
6009 | tempreg, BFD_RELOC_HI16_S); | |
6010 | macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16); | |
d6bc6245 | 6011 | if (breg != 0) |
67c0d1eb | 6012 | macro_build (NULL, "daddu", "d,v,t", |
17a2f251 | 6013 | tempreg, tempreg, breg); |
67c0d1eb | 6014 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 6015 | BFD_RELOC_LO16, tempreg); |
d6bc6245 | 6016 | } |
6caf9ef4 TS |
6017 | |
6018 | if (mips_relax.sequence) | |
6019 | relax_end (); | |
8fc2e39e | 6020 | break; |
d6bc6245 | 6021 | } |
256ab948 | 6022 | |
252b5132 RH |
6023 | if (breg == 0) |
6024 | { | |
67c0d1eb | 6025 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 6026 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 6027 | { |
4d7206a2 | 6028 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
6029 | macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_GPREL16, |
6030 | mips_gp_register); | |
4d7206a2 | 6031 | relax_switch (); |
252b5132 | 6032 | } |
67c0d1eb RS |
6033 | macro_build_lui (&offset_expr, tempreg); |
6034 | macro_build (&offset_expr, s, fmt, treg, | |
17a2f251 | 6035 | BFD_RELOC_LO16, tempreg); |
4d7206a2 RS |
6036 | if (mips_relax.sequence) |
6037 | relax_end (); | |
252b5132 RH |
6038 | } |
6039 | else | |
6040 | { | |
67c0d1eb | 6041 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 6042 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 6043 | { |
4d7206a2 | 6044 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 6045 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6046 | tempreg, breg, mips_gp_register); |
67c0d1eb | 6047 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 6048 | BFD_RELOC_GPREL16, tempreg); |
4d7206a2 | 6049 | relax_switch (); |
252b5132 | 6050 | } |
67c0d1eb RS |
6051 | macro_build_lui (&offset_expr, tempreg); |
6052 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 6053 | tempreg, tempreg, breg); |
67c0d1eb | 6054 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 6055 | BFD_RELOC_LO16, tempreg); |
4d7206a2 RS |
6056 | if (mips_relax.sequence) |
6057 | relax_end (); | |
252b5132 RH |
6058 | } |
6059 | } | |
0a44bf69 | 6060 | else if (!mips_big_got) |
252b5132 | 6061 | { |
ed6fb7bd | 6062 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
f9419b05 | 6063 | |
252b5132 RH |
6064 | /* If this is a reference to an external symbol, we want |
6065 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6066 | nop | |
6067 | <op> $treg,0($tempreg) | |
6068 | Otherwise we want | |
6069 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6070 | nop | |
6071 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
6072 | <op> $treg,0($tempreg) | |
f5040a92 AO |
6073 | |
6074 | For NewABI, we want | |
6075 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
6076 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) | |
6077 | ||
252b5132 RH |
6078 | If there is a base register, we add it to $tempreg before |
6079 | the <op>. If there is a constant, we stick it in the | |
6080 | <op> instruction. We don't handle constants larger than | |
6081 | 16 bits, because we have no way to load the upper 16 bits | |
6082 | (actually, we could handle them for the subset of cases | |
6083 | in which we are not using $at). */ | |
6084 | assert (offset_expr.X_op == O_symbol); | |
f5040a92 AO |
6085 | if (HAVE_NEWABI) |
6086 | { | |
67c0d1eb RS |
6087 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
6088 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
f5040a92 | 6089 | if (breg != 0) |
67c0d1eb | 6090 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6091 | tempreg, tempreg, breg); |
67c0d1eb | 6092 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 6093 | BFD_RELOC_MIPS_GOT_OFST, tempreg); |
f5040a92 AO |
6094 | break; |
6095 | } | |
252b5132 RH |
6096 | expr1.X_add_number = offset_expr.X_add_number; |
6097 | offset_expr.X_add_number = 0; | |
6098 | if (expr1.X_add_number < -0x8000 | |
6099 | || expr1.X_add_number >= 0x8000) | |
6100 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb RS |
6101 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
6102 | lw_reloc_type, mips_gp_register); | |
269137b2 | 6103 | load_delay_nop (); |
4d7206a2 RS |
6104 | relax_start (offset_expr.X_add_symbol); |
6105 | relax_switch (); | |
67c0d1eb RS |
6106 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, |
6107 | tempreg, BFD_RELOC_LO16); | |
4d7206a2 | 6108 | relax_end (); |
252b5132 | 6109 | if (breg != 0) |
67c0d1eb | 6110 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6111 | tempreg, tempreg, breg); |
67c0d1eb | 6112 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
252b5132 | 6113 | } |
0a44bf69 | 6114 | else if (mips_big_got && !HAVE_NEWABI) |
252b5132 | 6115 | { |
67c0d1eb | 6116 | int gpdelay; |
252b5132 RH |
6117 | |
6118 | /* If this is a reference to an external symbol, we want | |
6119 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
6120 | addu $tempreg,$tempreg,$gp | |
6121 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
6122 | <op> $treg,0($tempreg) | |
6123 | Otherwise we want | |
6124 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6125 | nop | |
6126 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
6127 | <op> $treg,0($tempreg) | |
6128 | If there is a base register, we add it to $tempreg before | |
6129 | the <op>. If there is a constant, we stick it in the | |
6130 | <op> instruction. We don't handle constants larger than | |
6131 | 16 bits, because we have no way to load the upper 16 bits | |
6132 | (actually, we could handle them for the subset of cases | |
f5040a92 | 6133 | in which we are not using $at). */ |
252b5132 RH |
6134 | assert (offset_expr.X_op == O_symbol); |
6135 | expr1.X_add_number = offset_expr.X_add_number; | |
6136 | offset_expr.X_add_number = 0; | |
6137 | if (expr1.X_add_number < -0x8000 | |
6138 | || expr1.X_add_number >= 0x8000) | |
6139 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 6140 | gpdelay = reg_needs_delay (mips_gp_register); |
4d7206a2 | 6141 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 6142 | macro_build (&offset_expr, "lui", "t,u", tempreg, |
17a2f251 | 6143 | BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
6144 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, |
6145 | mips_gp_register); | |
6146 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
6147 | BFD_RELOC_MIPS_GOT_LO16, tempreg); | |
4d7206a2 | 6148 | relax_switch (); |
67c0d1eb RS |
6149 | if (gpdelay) |
6150 | macro_build (NULL, "nop", ""); | |
6151 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
6152 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 6153 | load_delay_nop (); |
67c0d1eb RS |
6154 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, |
6155 | tempreg, BFD_RELOC_LO16); | |
4d7206a2 RS |
6156 | relax_end (); |
6157 | ||
252b5132 | 6158 | if (breg != 0) |
67c0d1eb | 6159 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6160 | tempreg, tempreg, breg); |
67c0d1eb | 6161 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
252b5132 | 6162 | } |
0a44bf69 | 6163 | else if (mips_big_got && HAVE_NEWABI) |
f5040a92 | 6164 | { |
f5040a92 AO |
6165 | /* If this is a reference to an external symbol, we want |
6166 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
6167 | add $tempreg,$tempreg,$gp | |
6168 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
6169 | <op> $treg,<ofst>($tempreg) | |
6170 | Otherwise, for local symbols, we want: | |
6171 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
6172 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */ | |
6173 | assert (offset_expr.X_op == O_symbol); | |
4d7206a2 | 6174 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
6175 | offset_expr.X_add_number = 0; |
6176 | if (expr1.X_add_number < -0x8000 | |
6177 | || expr1.X_add_number >= 0x8000) | |
6178 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4d7206a2 | 6179 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 6180 | macro_build (&offset_expr, "lui", "t,u", tempreg, |
17a2f251 | 6181 | BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
6182 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, |
6183 | mips_gp_register); | |
6184 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
6185 | BFD_RELOC_MIPS_GOT_LO16, tempreg); | |
f5040a92 | 6186 | if (breg != 0) |
67c0d1eb | 6187 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6188 | tempreg, tempreg, breg); |
67c0d1eb | 6189 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
684022ea | 6190 | |
4d7206a2 | 6191 | relax_switch (); |
f5040a92 | 6192 | offset_expr.X_add_number = expr1.X_add_number; |
67c0d1eb RS |
6193 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
6194 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
f5040a92 | 6195 | if (breg != 0) |
67c0d1eb | 6196 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6197 | tempreg, tempreg, breg); |
67c0d1eb | 6198 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 6199 | BFD_RELOC_MIPS_GOT_OFST, tempreg); |
4d7206a2 | 6200 | relax_end (); |
f5040a92 | 6201 | } |
252b5132 RH |
6202 | else |
6203 | abort (); | |
6204 | ||
252b5132 RH |
6205 | break; |
6206 | ||
6207 | case M_LI: | |
6208 | case M_LI_S: | |
67c0d1eb | 6209 | load_register (treg, &imm_expr, 0); |
8fc2e39e | 6210 | break; |
252b5132 RH |
6211 | |
6212 | case M_DLI: | |
67c0d1eb | 6213 | load_register (treg, &imm_expr, 1); |
8fc2e39e | 6214 | break; |
252b5132 RH |
6215 | |
6216 | case M_LI_SS: | |
6217 | if (imm_expr.X_op == O_constant) | |
6218 | { | |
8fc2e39e | 6219 | used_at = 1; |
67c0d1eb RS |
6220 | load_register (AT, &imm_expr, 0); |
6221 | macro_build (NULL, "mtc1", "t,G", AT, treg); | |
252b5132 RH |
6222 | break; |
6223 | } | |
6224 | else | |
6225 | { | |
6226 | assert (offset_expr.X_op == O_symbol | |
6227 | && strcmp (segment_name (S_GET_SEGMENT | |
6228 | (offset_expr.X_add_symbol)), | |
6229 | ".lit4") == 0 | |
6230 | && offset_expr.X_add_number == 0); | |
67c0d1eb | 6231 | macro_build (&offset_expr, "lwc1", "T,o(b)", treg, |
17a2f251 | 6232 | BFD_RELOC_MIPS_LITERAL, mips_gp_register); |
8fc2e39e | 6233 | break; |
252b5132 RH |
6234 | } |
6235 | ||
6236 | case M_LI_D: | |
ca4e0257 RS |
6237 | /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits |
6238 | wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high | |
6239 | order 32 bits of the value and the low order 32 bits are either | |
6240 | zero or in OFFSET_EXPR. */ | |
252b5132 RH |
6241 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) |
6242 | { | |
ca4e0257 | 6243 | if (HAVE_64BIT_GPRS) |
67c0d1eb | 6244 | load_register (treg, &imm_expr, 1); |
252b5132 RH |
6245 | else |
6246 | { | |
6247 | int hreg, lreg; | |
6248 | ||
6249 | if (target_big_endian) | |
6250 | { | |
6251 | hreg = treg; | |
6252 | lreg = treg + 1; | |
6253 | } | |
6254 | else | |
6255 | { | |
6256 | hreg = treg + 1; | |
6257 | lreg = treg; | |
6258 | } | |
6259 | ||
6260 | if (hreg <= 31) | |
67c0d1eb | 6261 | load_register (hreg, &imm_expr, 0); |
252b5132 RH |
6262 | if (lreg <= 31) |
6263 | { | |
6264 | if (offset_expr.X_op == O_absent) | |
67c0d1eb | 6265 | move_register (lreg, 0); |
252b5132 RH |
6266 | else |
6267 | { | |
6268 | assert (offset_expr.X_op == O_constant); | |
67c0d1eb | 6269 | load_register (lreg, &offset_expr, 0); |
252b5132 RH |
6270 | } |
6271 | } | |
6272 | } | |
8fc2e39e | 6273 | break; |
252b5132 RH |
6274 | } |
6275 | ||
6276 | /* We know that sym is in the .rdata section. First we get the | |
6277 | upper 16 bits of the address. */ | |
6278 | if (mips_pic == NO_PIC) | |
6279 | { | |
67c0d1eb | 6280 | macro_build_lui (&offset_expr, AT); |
8fc2e39e | 6281 | used_at = 1; |
252b5132 | 6282 | } |
0a44bf69 | 6283 | else |
252b5132 | 6284 | { |
67c0d1eb RS |
6285 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, |
6286 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
8fc2e39e | 6287 | used_at = 1; |
252b5132 | 6288 | } |
bdaaa2e1 | 6289 | |
252b5132 | 6290 | /* Now we load the register(s). */ |
ca4e0257 | 6291 | if (HAVE_64BIT_GPRS) |
8fc2e39e TS |
6292 | { |
6293 | used_at = 1; | |
6294 | macro_build (&offset_expr, "ld", "t,o(b)", treg, BFD_RELOC_LO16, AT); | |
6295 | } | |
252b5132 RH |
6296 | else |
6297 | { | |
8fc2e39e | 6298 | used_at = 1; |
67c0d1eb | 6299 | macro_build (&offset_expr, "lw", "t,o(b)", treg, BFD_RELOC_LO16, AT); |
f9419b05 | 6300 | if (treg != RA) |
252b5132 RH |
6301 | { |
6302 | /* FIXME: How in the world do we deal with the possible | |
6303 | overflow here? */ | |
6304 | offset_expr.X_add_number += 4; | |
67c0d1eb | 6305 | macro_build (&offset_expr, "lw", "t,o(b)", |
17a2f251 | 6306 | treg + 1, BFD_RELOC_LO16, AT); |
252b5132 RH |
6307 | } |
6308 | } | |
252b5132 RH |
6309 | break; |
6310 | ||
6311 | case M_LI_DD: | |
ca4e0257 RS |
6312 | /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits |
6313 | wide, IMM_EXPR is the entire value and the GPRs are known to be 64 | |
6314 | bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of | |
6315 | the value and the low order 32 bits are either zero or in | |
6316 | OFFSET_EXPR. */ | |
252b5132 RH |
6317 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) |
6318 | { | |
8fc2e39e | 6319 | used_at = 1; |
67c0d1eb | 6320 | load_register (AT, &imm_expr, HAVE_64BIT_FPRS); |
ca4e0257 RS |
6321 | if (HAVE_64BIT_FPRS) |
6322 | { | |
6323 | assert (HAVE_64BIT_GPRS); | |
67c0d1eb | 6324 | macro_build (NULL, "dmtc1", "t,S", AT, treg); |
ca4e0257 | 6325 | } |
252b5132 RH |
6326 | else |
6327 | { | |
67c0d1eb | 6328 | macro_build (NULL, "mtc1", "t,G", AT, treg + 1); |
252b5132 | 6329 | if (offset_expr.X_op == O_absent) |
67c0d1eb | 6330 | macro_build (NULL, "mtc1", "t,G", 0, treg); |
252b5132 RH |
6331 | else |
6332 | { | |
6333 | assert (offset_expr.X_op == O_constant); | |
67c0d1eb RS |
6334 | load_register (AT, &offset_expr, 0); |
6335 | macro_build (NULL, "mtc1", "t,G", AT, treg); | |
252b5132 RH |
6336 | } |
6337 | } | |
6338 | break; | |
6339 | } | |
6340 | ||
6341 | assert (offset_expr.X_op == O_symbol | |
6342 | && offset_expr.X_add_number == 0); | |
6343 | s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol)); | |
6344 | if (strcmp (s, ".lit8") == 0) | |
6345 | { | |
e7af610e | 6346 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 | 6347 | { |
67c0d1eb | 6348 | macro_build (&offset_expr, "ldc1", "T,o(b)", treg, |
17a2f251 | 6349 | BFD_RELOC_MIPS_LITERAL, mips_gp_register); |
8fc2e39e | 6350 | break; |
252b5132 | 6351 | } |
c9914766 | 6352 | breg = mips_gp_register; |
252b5132 RH |
6353 | r = BFD_RELOC_MIPS_LITERAL; |
6354 | goto dob; | |
6355 | } | |
6356 | else | |
6357 | { | |
6358 | assert (strcmp (s, RDATA_SECTION_NAME) == 0); | |
8fc2e39e | 6359 | used_at = 1; |
0a44bf69 | 6360 | if (mips_pic != NO_PIC) |
67c0d1eb RS |
6361 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, |
6362 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
252b5132 RH |
6363 | else |
6364 | { | |
6365 | /* FIXME: This won't work for a 64 bit address. */ | |
67c0d1eb | 6366 | macro_build_lui (&offset_expr, AT); |
252b5132 | 6367 | } |
bdaaa2e1 | 6368 | |
e7af610e | 6369 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 | 6370 | { |
67c0d1eb RS |
6371 | macro_build (&offset_expr, "ldc1", "T,o(b)", |
6372 | treg, BFD_RELOC_LO16, AT); | |
252b5132 RH |
6373 | break; |
6374 | } | |
6375 | breg = AT; | |
6376 | r = BFD_RELOC_LO16; | |
6377 | goto dob; | |
6378 | } | |
6379 | ||
6380 | case M_L_DOB: | |
fef14a42 | 6381 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
6382 | { |
6383 | as_bad (_("opcode not supported on this processor")); | |
8fc2e39e | 6384 | break; |
252b5132 RH |
6385 | } |
6386 | /* Even on a big endian machine $fn comes before $fn+1. We have | |
6387 | to adjust when loading from memory. */ | |
6388 | r = BFD_RELOC_LO16; | |
6389 | dob: | |
e7af610e | 6390 | assert (mips_opts.isa == ISA_MIPS1); |
67c0d1eb | 6391 | macro_build (&offset_expr, "lwc1", "T,o(b)", |
17a2f251 | 6392 | target_big_endian ? treg + 1 : treg, r, breg); |
252b5132 RH |
6393 | /* FIXME: A possible overflow which I don't know how to deal |
6394 | with. */ | |
6395 | offset_expr.X_add_number += 4; | |
67c0d1eb | 6396 | macro_build (&offset_expr, "lwc1", "T,o(b)", |
17a2f251 | 6397 | target_big_endian ? treg : treg + 1, r, breg); |
252b5132 RH |
6398 | break; |
6399 | ||
6400 | case M_L_DAB: | |
6401 | /* | |
6402 | * The MIPS assembler seems to check for X_add_number not | |
6403 | * being double aligned and generating: | |
6404 | * lui at,%hi(foo+1) | |
6405 | * addu at,at,v1 | |
6406 | * addiu at,at,%lo(foo+1) | |
6407 | * lwc1 f2,0(at) | |
6408 | * lwc1 f3,4(at) | |
6409 | * But, the resulting address is the same after relocation so why | |
6410 | * generate the extra instruction? | |
6411 | */ | |
fef14a42 | 6412 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
6413 | { |
6414 | as_bad (_("opcode not supported on this processor")); | |
8fc2e39e | 6415 | break; |
252b5132 | 6416 | } |
bdaaa2e1 | 6417 | /* Itbl support may require additional care here. */ |
252b5132 | 6418 | coproc = 1; |
e7af610e | 6419 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 RH |
6420 | { |
6421 | s = "ldc1"; | |
6422 | goto ld; | |
6423 | } | |
6424 | ||
6425 | s = "lwc1"; | |
6426 | fmt = "T,o(b)"; | |
6427 | goto ldd_std; | |
6428 | ||
6429 | case M_S_DAB: | |
fef14a42 | 6430 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
6431 | { |
6432 | as_bad (_("opcode not supported on this processor")); | |
8fc2e39e | 6433 | break; |
252b5132 RH |
6434 | } |
6435 | ||
e7af610e | 6436 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 RH |
6437 | { |
6438 | s = "sdc1"; | |
6439 | goto st; | |
6440 | } | |
6441 | ||
6442 | s = "swc1"; | |
6443 | fmt = "T,o(b)"; | |
bdaaa2e1 | 6444 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6445 | coproc = 1; |
6446 | goto ldd_std; | |
6447 | ||
6448 | case M_LD_AB: | |
ca4e0257 | 6449 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
6450 | { |
6451 | s = "ld"; | |
6452 | goto ld; | |
6453 | } | |
6454 | ||
6455 | s = "lw"; | |
6456 | fmt = "t,o(b)"; | |
6457 | goto ldd_std; | |
6458 | ||
6459 | case M_SD_AB: | |
ca4e0257 | 6460 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
6461 | { |
6462 | s = "sd"; | |
6463 | goto st; | |
6464 | } | |
6465 | ||
6466 | s = "sw"; | |
6467 | fmt = "t,o(b)"; | |
6468 | ||
6469 | ldd_std: | |
6470 | if (offset_expr.X_op != O_symbol | |
6471 | && offset_expr.X_op != O_constant) | |
6472 | { | |
6473 | as_bad (_("expression too complex")); | |
6474 | offset_expr.X_op = O_constant; | |
6475 | } | |
6476 | ||
2051e8c4 MR |
6477 | if (HAVE_32BIT_ADDRESSES |
6478 | && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) | |
55e08f71 NC |
6479 | { |
6480 | char value [32]; | |
6481 | ||
6482 | sprintf_vma (value, offset_expr.X_add_number); | |
20e1fcfd | 6483 | as_bad (_("Number (0x%s) larger than 32 bits"), value); |
55e08f71 | 6484 | } |
2051e8c4 | 6485 | |
252b5132 RH |
6486 | /* Even on a big endian machine $fn comes before $fn+1. We have |
6487 | to adjust when loading from memory. We set coproc if we must | |
6488 | load $fn+1 first. */ | |
bdaaa2e1 | 6489 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6490 | if (! target_big_endian) |
6491 | coproc = 0; | |
6492 | ||
6493 | if (mips_pic == NO_PIC | |
6494 | || offset_expr.X_op == O_constant) | |
6495 | { | |
6496 | /* If this is a reference to a GP relative symbol, we want | |
cdf6fd85 TS |
6497 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
6498 | <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16) | |
252b5132 RH |
6499 | If we have a base register, we use this |
6500 | addu $at,$breg,$gp | |
cdf6fd85 TS |
6501 | <op> $treg,<sym>($at) (BFD_RELOC_GPREL16) |
6502 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16) | |
252b5132 RH |
6503 | If this is not a GP relative symbol, we want |
6504 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
6505 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
6506 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
6507 | If there is a base register, we add it to $at after the | |
6508 | lui instruction. If there is a constant, we always use | |
6509 | the last case. */ | |
39a59cf8 MR |
6510 | if (offset_expr.X_op == O_symbol |
6511 | && (valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET | |
6caf9ef4 | 6512 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 6513 | { |
4d7206a2 | 6514 | relax_start (offset_expr.X_add_symbol); |
252b5132 RH |
6515 | if (breg == 0) |
6516 | { | |
c9914766 | 6517 | tempreg = mips_gp_register; |
252b5132 RH |
6518 | } |
6519 | else | |
6520 | { | |
67c0d1eb | 6521 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6522 | AT, breg, mips_gp_register); |
252b5132 | 6523 | tempreg = AT; |
252b5132 RH |
6524 | used_at = 1; |
6525 | } | |
6526 | ||
beae10d5 | 6527 | /* Itbl support may require additional care here. */ |
67c0d1eb | 6528 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 6529 | BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
6530 | offset_expr.X_add_number += 4; |
6531 | ||
6532 | /* Set mips_optimize to 2 to avoid inserting an | |
6533 | undesired nop. */ | |
6534 | hold_mips_optimize = mips_optimize; | |
6535 | mips_optimize = 2; | |
beae10d5 | 6536 | /* Itbl support may require additional care here. */ |
67c0d1eb | 6537 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 6538 | BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
6539 | mips_optimize = hold_mips_optimize; |
6540 | ||
4d7206a2 | 6541 | relax_switch (); |
252b5132 RH |
6542 | |
6543 | /* We just generated two relocs. When tc_gen_reloc | |
6544 | handles this case, it will skip the first reloc and | |
6545 | handle the second. The second reloc already has an | |
6546 | extra addend of 4, which we added above. We must | |
6547 | subtract it out, and then subtract another 4 to make | |
6548 | the first reloc come out right. The second reloc | |
6549 | will come out right because we are going to add 4 to | |
6550 | offset_expr when we build its instruction below. | |
6551 | ||
6552 | If we have a symbol, then we don't want to include | |
6553 | the offset, because it will wind up being included | |
6554 | when we generate the reloc. */ | |
6555 | ||
6556 | if (offset_expr.X_op == O_constant) | |
6557 | offset_expr.X_add_number -= 8; | |
6558 | else | |
6559 | { | |
6560 | offset_expr.X_add_number = -4; | |
6561 | offset_expr.X_op = O_constant; | |
6562 | } | |
6563 | } | |
8fc2e39e | 6564 | used_at = 1; |
67c0d1eb | 6565 | macro_build_lui (&offset_expr, AT); |
252b5132 | 6566 | if (breg != 0) |
67c0d1eb | 6567 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 6568 | /* Itbl support may require additional care here. */ |
67c0d1eb | 6569 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 6570 | BFD_RELOC_LO16, AT); |
252b5132 RH |
6571 | /* FIXME: How do we handle overflow here? */ |
6572 | offset_expr.X_add_number += 4; | |
beae10d5 | 6573 | /* Itbl support may require additional care here. */ |
67c0d1eb | 6574 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 6575 | BFD_RELOC_LO16, AT); |
4d7206a2 RS |
6576 | if (mips_relax.sequence) |
6577 | relax_end (); | |
bdaaa2e1 | 6578 | } |
0a44bf69 | 6579 | else if (!mips_big_got) |
252b5132 | 6580 | { |
252b5132 RH |
6581 | /* If this is a reference to an external symbol, we want |
6582 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6583 | nop | |
6584 | <op> $treg,0($at) | |
6585 | <op> $treg+1,4($at) | |
6586 | Otherwise we want | |
6587 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6588 | nop | |
6589 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
6590 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
6591 | If there is a base register we add it to $at before the | |
6592 | lwc1 instructions. If there is a constant we include it | |
6593 | in the lwc1 instructions. */ | |
6594 | used_at = 1; | |
6595 | expr1.X_add_number = offset_expr.X_add_number; | |
252b5132 RH |
6596 | if (expr1.X_add_number < -0x8000 |
6597 | || expr1.X_add_number >= 0x8000 - 4) | |
6598 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 6599 | load_got_offset (AT, &offset_expr); |
269137b2 | 6600 | load_delay_nop (); |
252b5132 | 6601 | if (breg != 0) |
67c0d1eb | 6602 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
252b5132 RH |
6603 | |
6604 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
6605 | nop. */ | |
6606 | hold_mips_optimize = mips_optimize; | |
6607 | mips_optimize = 2; | |
4d7206a2 | 6608 | |
beae10d5 | 6609 | /* Itbl support may require additional care here. */ |
4d7206a2 | 6610 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
6611 | macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg, |
6612 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 6613 | expr1.X_add_number += 4; |
67c0d1eb RS |
6614 | macro_build (&expr1, s, fmt, coproc ? treg : treg + 1, |
6615 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 6616 | relax_switch (); |
67c0d1eb RS |
6617 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
6618 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 6619 | offset_expr.X_add_number += 4; |
67c0d1eb RS |
6620 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
6621 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 6622 | relax_end (); |
252b5132 | 6623 | |
4d7206a2 | 6624 | mips_optimize = hold_mips_optimize; |
252b5132 | 6625 | } |
0a44bf69 | 6626 | else if (mips_big_got) |
252b5132 | 6627 | { |
67c0d1eb | 6628 | int gpdelay; |
252b5132 RH |
6629 | |
6630 | /* If this is a reference to an external symbol, we want | |
6631 | lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
6632 | addu $at,$at,$gp | |
6633 | lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16) | |
6634 | nop | |
6635 | <op> $treg,0($at) | |
6636 | <op> $treg+1,4($at) | |
6637 | Otherwise we want | |
6638 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6639 | nop | |
6640 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
6641 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
6642 | If there is a base register we add it to $at before the | |
6643 | lwc1 instructions. If there is a constant we include it | |
6644 | in the lwc1 instructions. */ | |
6645 | used_at = 1; | |
6646 | expr1.X_add_number = offset_expr.X_add_number; | |
6647 | offset_expr.X_add_number = 0; | |
6648 | if (expr1.X_add_number < -0x8000 | |
6649 | || expr1.X_add_number >= 0x8000 - 4) | |
6650 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 6651 | gpdelay = reg_needs_delay (mips_gp_register); |
4d7206a2 | 6652 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
6653 | macro_build (&offset_expr, "lui", "t,u", |
6654 | AT, BFD_RELOC_MIPS_GOT_HI16); | |
6655 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 6656 | AT, AT, mips_gp_register); |
67c0d1eb | 6657 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
17a2f251 | 6658 | AT, BFD_RELOC_MIPS_GOT_LO16, AT); |
269137b2 | 6659 | load_delay_nop (); |
252b5132 | 6660 | if (breg != 0) |
67c0d1eb | 6661 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 6662 | /* Itbl support may require additional care here. */ |
67c0d1eb | 6663 | macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 6664 | BFD_RELOC_LO16, AT); |
252b5132 RH |
6665 | expr1.X_add_number += 4; |
6666 | ||
6667 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
6668 | nop. */ | |
6669 | hold_mips_optimize = mips_optimize; | |
6670 | mips_optimize = 2; | |
beae10d5 | 6671 | /* Itbl support may require additional care here. */ |
67c0d1eb | 6672 | macro_build (&expr1, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 6673 | BFD_RELOC_LO16, AT); |
252b5132 RH |
6674 | mips_optimize = hold_mips_optimize; |
6675 | expr1.X_add_number -= 4; | |
6676 | ||
4d7206a2 RS |
6677 | relax_switch (); |
6678 | offset_expr.X_add_number = expr1.X_add_number; | |
67c0d1eb RS |
6679 | if (gpdelay) |
6680 | macro_build (NULL, "nop", ""); | |
6681 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, | |
6682 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 6683 | load_delay_nop (); |
252b5132 | 6684 | if (breg != 0) |
67c0d1eb | 6685 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 6686 | /* Itbl support may require additional care here. */ |
67c0d1eb RS |
6687 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
6688 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 6689 | offset_expr.X_add_number += 4; |
252b5132 RH |
6690 | |
6691 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
6692 | nop. */ | |
6693 | hold_mips_optimize = mips_optimize; | |
6694 | mips_optimize = 2; | |
beae10d5 | 6695 | /* Itbl support may require additional care here. */ |
67c0d1eb RS |
6696 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
6697 | BFD_RELOC_LO16, AT); | |
252b5132 | 6698 | mips_optimize = hold_mips_optimize; |
4d7206a2 | 6699 | relax_end (); |
252b5132 | 6700 | } |
252b5132 RH |
6701 | else |
6702 | abort (); | |
6703 | ||
252b5132 RH |
6704 | break; |
6705 | ||
6706 | case M_LD_OB: | |
6707 | s = "lw"; | |
6708 | goto sd_ob; | |
6709 | case M_SD_OB: | |
6710 | s = "sw"; | |
6711 | sd_ob: | |
ca4e0257 | 6712 | assert (HAVE_32BIT_ADDRESSES); |
67c0d1eb | 6713 | macro_build (&offset_expr, s, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
252b5132 | 6714 | offset_expr.X_add_number += 4; |
67c0d1eb | 6715 | macro_build (&offset_expr, s, "t,o(b)", treg + 1, BFD_RELOC_LO16, breg); |
8fc2e39e | 6716 | break; |
252b5132 RH |
6717 | |
6718 | /* New code added to support COPZ instructions. | |
6719 | This code builds table entries out of the macros in mip_opcodes. | |
6720 | R4000 uses interlocks to handle coproc delays. | |
6721 | Other chips (like the R3000) require nops to be inserted for delays. | |
6722 | ||
f72c8c98 | 6723 | FIXME: Currently, we require that the user handle delays. |
252b5132 RH |
6724 | In order to fill delay slots for non-interlocked chips, |
6725 | we must have a way to specify delays based on the coprocessor. | |
6726 | Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc. | |
6727 | What are the side-effects of the cop instruction? | |
6728 | What cache support might we have and what are its effects? | |
6729 | Both coprocessor & memory require delays. how long??? | |
bdaaa2e1 | 6730 | What registers are read/set/modified? |
252b5132 RH |
6731 | |
6732 | If an itbl is provided to interpret cop instructions, | |
bdaaa2e1 | 6733 | this knowledge can be encoded in the itbl spec. */ |
252b5132 RH |
6734 | |
6735 | case M_COP0: | |
6736 | s = "c0"; | |
6737 | goto copz; | |
6738 | case M_COP1: | |
6739 | s = "c1"; | |
6740 | goto copz; | |
6741 | case M_COP2: | |
6742 | s = "c2"; | |
6743 | goto copz; | |
6744 | case M_COP3: | |
6745 | s = "c3"; | |
6746 | copz: | |
6747 | /* For now we just do C (same as Cz). The parameter will be | |
6748 | stored in insn_opcode by mips_ip. */ | |
67c0d1eb | 6749 | macro_build (NULL, s, "C", ip->insn_opcode); |
8fc2e39e | 6750 | break; |
252b5132 | 6751 | |
ea1fb5dc | 6752 | case M_MOVE: |
67c0d1eb | 6753 | move_register (dreg, sreg); |
8fc2e39e | 6754 | break; |
ea1fb5dc | 6755 | |
252b5132 RH |
6756 | #ifdef LOSING_COMPILER |
6757 | default: | |
6758 | /* Try and see if this is a new itbl instruction. | |
6759 | This code builds table entries out of the macros in mip_opcodes. | |
6760 | FIXME: For now we just assemble the expression and pass it's | |
6761 | value along as a 32-bit immediate. | |
bdaaa2e1 | 6762 | We may want to have the assembler assemble this value, |
252b5132 RH |
6763 | so that we gain the assembler's knowledge of delay slots, |
6764 | symbols, etc. | |
6765 | Would it be more efficient to use mask (id) here? */ | |
bdaaa2e1 | 6766 | if (itbl_have_entries |
252b5132 | 6767 | && (immed_expr = itbl_assemble (ip->insn_mo->name, ""))) |
beae10d5 | 6768 | { |
252b5132 RH |
6769 | s = ip->insn_mo->name; |
6770 | s2 = "cop3"; | |
6771 | coproc = ITBL_DECODE_PNUM (immed_expr);; | |
67c0d1eb | 6772 | macro_build (&immed_expr, s, "C"); |
8fc2e39e | 6773 | break; |
beae10d5 | 6774 | } |
252b5132 | 6775 | macro2 (ip); |
8fc2e39e | 6776 | break; |
252b5132 | 6777 | } |
8fc2e39e TS |
6778 | if (mips_opts.noat && used_at) |
6779 | as_bad (_("Macro used $at after \".set noat\"")); | |
252b5132 | 6780 | } |
bdaaa2e1 | 6781 | |
252b5132 | 6782 | static void |
17a2f251 | 6783 | macro2 (struct mips_cl_insn *ip) |
252b5132 RH |
6784 | { |
6785 | register int treg, sreg, dreg, breg; | |
6786 | int tempreg; | |
6787 | int mask; | |
252b5132 RH |
6788 | int used_at; |
6789 | expressionS expr1; | |
6790 | const char *s; | |
6791 | const char *s2; | |
6792 | const char *fmt; | |
6793 | int likely = 0; | |
6794 | int dbl = 0; | |
6795 | int coproc = 0; | |
6796 | int lr = 0; | |
6797 | int imm = 0; | |
6798 | int off; | |
6799 | offsetT maxnum; | |
6800 | bfd_reloc_code_real_type r; | |
bdaaa2e1 | 6801 | |
252b5132 RH |
6802 | treg = (ip->insn_opcode >> 16) & 0x1f; |
6803 | dreg = (ip->insn_opcode >> 11) & 0x1f; | |
6804 | sreg = breg = (ip->insn_opcode >> 21) & 0x1f; | |
6805 | mask = ip->insn_mo->mask; | |
bdaaa2e1 | 6806 | |
252b5132 RH |
6807 | expr1.X_op = O_constant; |
6808 | expr1.X_op_symbol = NULL; | |
6809 | expr1.X_add_symbol = NULL; | |
6810 | expr1.X_add_number = 1; | |
bdaaa2e1 | 6811 | |
252b5132 RH |
6812 | switch (mask) |
6813 | { | |
6814 | #endif /* LOSING_COMPILER */ | |
6815 | ||
6816 | case M_DMUL: | |
6817 | dbl = 1; | |
6818 | case M_MUL: | |
67c0d1eb RS |
6819 | macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", sreg, treg); |
6820 | macro_build (NULL, "mflo", "d", dreg); | |
8fc2e39e | 6821 | break; |
252b5132 RH |
6822 | |
6823 | case M_DMUL_I: | |
6824 | dbl = 1; | |
6825 | case M_MUL_I: | |
6826 | /* The MIPS assembler some times generates shifts and adds. I'm | |
6827 | not trying to be that fancy. GCC should do this for us | |
6828 | anyway. */ | |
8fc2e39e | 6829 | used_at = 1; |
67c0d1eb RS |
6830 | load_register (AT, &imm_expr, dbl); |
6831 | macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, AT); | |
6832 | macro_build (NULL, "mflo", "d", dreg); | |
252b5132 RH |
6833 | break; |
6834 | ||
6835 | case M_DMULO_I: | |
6836 | dbl = 1; | |
6837 | case M_MULO_I: | |
6838 | imm = 1; | |
6839 | goto do_mulo; | |
6840 | ||
6841 | case M_DMULO: | |
6842 | dbl = 1; | |
6843 | case M_MULO: | |
6844 | do_mulo: | |
7d10b47d | 6845 | start_noreorder (); |
8fc2e39e | 6846 | used_at = 1; |
252b5132 | 6847 | if (imm) |
67c0d1eb RS |
6848 | load_register (AT, &imm_expr, dbl); |
6849 | macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, imm ? AT : treg); | |
6850 | macro_build (NULL, "mflo", "d", dreg); | |
6851 | macro_build (NULL, dbl ? "dsra32" : "sra", "d,w,<", dreg, dreg, RA); | |
6852 | macro_build (NULL, "mfhi", "d", AT); | |
252b5132 | 6853 | if (mips_trap) |
67c0d1eb | 6854 | macro_build (NULL, "tne", "s,t,q", dreg, AT, 6); |
252b5132 RH |
6855 | else |
6856 | { | |
6857 | expr1.X_add_number = 8; | |
67c0d1eb RS |
6858 | macro_build (&expr1, "beq", "s,t,p", dreg, AT); |
6859 | macro_build (NULL, "nop", "", 0); | |
6860 | macro_build (NULL, "break", "c", 6); | |
252b5132 | 6861 | } |
7d10b47d | 6862 | end_noreorder (); |
67c0d1eb | 6863 | macro_build (NULL, "mflo", "d", dreg); |
252b5132 RH |
6864 | break; |
6865 | ||
6866 | case M_DMULOU_I: | |
6867 | dbl = 1; | |
6868 | case M_MULOU_I: | |
6869 | imm = 1; | |
6870 | goto do_mulou; | |
6871 | ||
6872 | case M_DMULOU: | |
6873 | dbl = 1; | |
6874 | case M_MULOU: | |
6875 | do_mulou: | |
7d10b47d | 6876 | start_noreorder (); |
8fc2e39e | 6877 | used_at = 1; |
252b5132 | 6878 | if (imm) |
67c0d1eb RS |
6879 | load_register (AT, &imm_expr, dbl); |
6880 | macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", | |
17a2f251 | 6881 | sreg, imm ? AT : treg); |
67c0d1eb RS |
6882 | macro_build (NULL, "mfhi", "d", AT); |
6883 | macro_build (NULL, "mflo", "d", dreg); | |
252b5132 | 6884 | if (mips_trap) |
67c0d1eb | 6885 | macro_build (NULL, "tne", "s,t,q", AT, 0, 6); |
252b5132 RH |
6886 | else |
6887 | { | |
6888 | expr1.X_add_number = 8; | |
67c0d1eb RS |
6889 | macro_build (&expr1, "beq", "s,t,p", AT, 0); |
6890 | macro_build (NULL, "nop", "", 0); | |
6891 | macro_build (NULL, "break", "c", 6); | |
252b5132 | 6892 | } |
7d10b47d | 6893 | end_noreorder (); |
252b5132 RH |
6894 | break; |
6895 | ||
771c7ce4 | 6896 | case M_DROL: |
fef14a42 | 6897 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 CD |
6898 | { |
6899 | if (dreg == sreg) | |
6900 | { | |
6901 | tempreg = AT; | |
6902 | used_at = 1; | |
6903 | } | |
6904 | else | |
6905 | { | |
6906 | tempreg = dreg; | |
82dd0097 | 6907 | } |
67c0d1eb RS |
6908 | macro_build (NULL, "dnegu", "d,w", tempreg, treg); |
6909 | macro_build (NULL, "drorv", "d,t,s", dreg, sreg, tempreg); | |
8fc2e39e | 6910 | break; |
82dd0097 | 6911 | } |
8fc2e39e | 6912 | used_at = 1; |
67c0d1eb RS |
6913 | macro_build (NULL, "dsubu", "d,v,t", AT, 0, treg); |
6914 | macro_build (NULL, "dsrlv", "d,t,s", AT, sreg, AT); | |
6915 | macro_build (NULL, "dsllv", "d,t,s", dreg, sreg, treg); | |
6916 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
6917 | break; |
6918 | ||
252b5132 | 6919 | case M_ROL: |
fef14a42 | 6920 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 CD |
6921 | { |
6922 | if (dreg == sreg) | |
6923 | { | |
6924 | tempreg = AT; | |
6925 | used_at = 1; | |
6926 | } | |
6927 | else | |
6928 | { | |
6929 | tempreg = dreg; | |
82dd0097 | 6930 | } |
67c0d1eb RS |
6931 | macro_build (NULL, "negu", "d,w", tempreg, treg); |
6932 | macro_build (NULL, "rorv", "d,t,s", dreg, sreg, tempreg); | |
8fc2e39e | 6933 | break; |
82dd0097 | 6934 | } |
8fc2e39e | 6935 | used_at = 1; |
67c0d1eb RS |
6936 | macro_build (NULL, "subu", "d,v,t", AT, 0, treg); |
6937 | macro_build (NULL, "srlv", "d,t,s", AT, sreg, AT); | |
6938 | macro_build (NULL, "sllv", "d,t,s", dreg, sreg, treg); | |
6939 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
6940 | break; |
6941 | ||
771c7ce4 TS |
6942 | case M_DROL_I: |
6943 | { | |
6944 | unsigned int rot; | |
82dd0097 | 6945 | char *l, *r; |
771c7ce4 TS |
6946 | |
6947 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 6948 | as_bad (_("Improper rotate count")); |
771c7ce4 | 6949 | rot = imm_expr.X_add_number & 0x3f; |
fef14a42 | 6950 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
60b63b72 RS |
6951 | { |
6952 | rot = (64 - rot) & 0x3f; | |
6953 | if (rot >= 32) | |
67c0d1eb | 6954 | macro_build (NULL, "dror32", "d,w,<", dreg, sreg, rot - 32); |
60b63b72 | 6955 | else |
67c0d1eb | 6956 | macro_build (NULL, "dror", "d,w,<", dreg, sreg, rot); |
8fc2e39e | 6957 | break; |
60b63b72 | 6958 | } |
483fc7cd | 6959 | if (rot == 0) |
483fc7cd | 6960 | { |
67c0d1eb | 6961 | macro_build (NULL, "dsrl", "d,w,<", dreg, sreg, 0); |
8fc2e39e | 6962 | break; |
483fc7cd | 6963 | } |
82dd0097 CD |
6964 | l = (rot < 0x20) ? "dsll" : "dsll32"; |
6965 | r = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32"; | |
6966 | rot &= 0x1f; | |
8fc2e39e | 6967 | used_at = 1; |
67c0d1eb RS |
6968 | macro_build (NULL, l, "d,w,<", AT, sreg, rot); |
6969 | macro_build (NULL, r, "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); | |
6970 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
6971 | } |
6972 | break; | |
6973 | ||
252b5132 | 6974 | case M_ROL_I: |
771c7ce4 TS |
6975 | { |
6976 | unsigned int rot; | |
6977 | ||
6978 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 6979 | as_bad (_("Improper rotate count")); |
771c7ce4 | 6980 | rot = imm_expr.X_add_number & 0x1f; |
fef14a42 | 6981 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
60b63b72 | 6982 | { |
67c0d1eb | 6983 | macro_build (NULL, "ror", "d,w,<", dreg, sreg, (32 - rot) & 0x1f); |
8fc2e39e | 6984 | break; |
60b63b72 | 6985 | } |
483fc7cd | 6986 | if (rot == 0) |
483fc7cd | 6987 | { |
67c0d1eb | 6988 | macro_build (NULL, "srl", "d,w,<", dreg, sreg, 0); |
8fc2e39e | 6989 | break; |
483fc7cd | 6990 | } |
8fc2e39e | 6991 | used_at = 1; |
67c0d1eb RS |
6992 | macro_build (NULL, "sll", "d,w,<", AT, sreg, rot); |
6993 | macro_build (NULL, "srl", "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); | |
6994 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
6995 | } |
6996 | break; | |
6997 | ||
6998 | case M_DROR: | |
fef14a42 | 6999 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 | 7000 | { |
67c0d1eb | 7001 | macro_build (NULL, "drorv", "d,t,s", dreg, sreg, treg); |
8fc2e39e | 7002 | break; |
82dd0097 | 7003 | } |
8fc2e39e | 7004 | used_at = 1; |
67c0d1eb RS |
7005 | macro_build (NULL, "dsubu", "d,v,t", AT, 0, treg); |
7006 | macro_build (NULL, "dsllv", "d,t,s", AT, sreg, AT); | |
7007 | macro_build (NULL, "dsrlv", "d,t,s", dreg, sreg, treg); | |
7008 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
7009 | break; |
7010 | ||
7011 | case M_ROR: | |
fef14a42 | 7012 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 | 7013 | { |
67c0d1eb | 7014 | macro_build (NULL, "rorv", "d,t,s", dreg, sreg, treg); |
8fc2e39e | 7015 | break; |
82dd0097 | 7016 | } |
8fc2e39e | 7017 | used_at = 1; |
67c0d1eb RS |
7018 | macro_build (NULL, "subu", "d,v,t", AT, 0, treg); |
7019 | macro_build (NULL, "sllv", "d,t,s", AT, sreg, AT); | |
7020 | macro_build (NULL, "srlv", "d,t,s", dreg, sreg, treg); | |
7021 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
7022 | break; |
7023 | ||
771c7ce4 TS |
7024 | case M_DROR_I: |
7025 | { | |
7026 | unsigned int rot; | |
82dd0097 | 7027 | char *l, *r; |
771c7ce4 TS |
7028 | |
7029 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 7030 | as_bad (_("Improper rotate count")); |
771c7ce4 | 7031 | rot = imm_expr.X_add_number & 0x3f; |
fef14a42 | 7032 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 CD |
7033 | { |
7034 | if (rot >= 32) | |
67c0d1eb | 7035 | macro_build (NULL, "dror32", "d,w,<", dreg, sreg, rot - 32); |
82dd0097 | 7036 | else |
67c0d1eb | 7037 | macro_build (NULL, "dror", "d,w,<", dreg, sreg, rot); |
8fc2e39e | 7038 | break; |
82dd0097 | 7039 | } |
483fc7cd | 7040 | if (rot == 0) |
483fc7cd | 7041 | { |
67c0d1eb | 7042 | macro_build (NULL, "dsrl", "d,w,<", dreg, sreg, 0); |
8fc2e39e | 7043 | break; |
483fc7cd | 7044 | } |
82dd0097 CD |
7045 | r = (rot < 0x20) ? "dsrl" : "dsrl32"; |
7046 | l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32"; | |
7047 | rot &= 0x1f; | |
8fc2e39e | 7048 | used_at = 1; |
67c0d1eb RS |
7049 | macro_build (NULL, r, "d,w,<", AT, sreg, rot); |
7050 | macro_build (NULL, l, "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); | |
7051 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
7052 | } |
7053 | break; | |
7054 | ||
252b5132 | 7055 | case M_ROR_I: |
771c7ce4 TS |
7056 | { |
7057 | unsigned int rot; | |
7058 | ||
7059 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 7060 | as_bad (_("Improper rotate count")); |
771c7ce4 | 7061 | rot = imm_expr.X_add_number & 0x1f; |
fef14a42 | 7062 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 | 7063 | { |
67c0d1eb | 7064 | macro_build (NULL, "ror", "d,w,<", dreg, sreg, rot); |
8fc2e39e | 7065 | break; |
82dd0097 | 7066 | } |
483fc7cd | 7067 | if (rot == 0) |
483fc7cd | 7068 | { |
67c0d1eb | 7069 | macro_build (NULL, "srl", "d,w,<", dreg, sreg, 0); |
8fc2e39e | 7070 | break; |
483fc7cd | 7071 | } |
8fc2e39e | 7072 | used_at = 1; |
67c0d1eb RS |
7073 | macro_build (NULL, "srl", "d,w,<", AT, sreg, rot); |
7074 | macro_build (NULL, "sll", "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); | |
7075 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 | 7076 | } |
252b5132 RH |
7077 | break; |
7078 | ||
7079 | case M_S_DOB: | |
fef14a42 | 7080 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
7081 | { |
7082 | as_bad (_("opcode not supported on this processor")); | |
8fc2e39e | 7083 | break; |
252b5132 | 7084 | } |
e7af610e | 7085 | assert (mips_opts.isa == ISA_MIPS1); |
252b5132 RH |
7086 | /* Even on a big endian machine $fn comes before $fn+1. We have |
7087 | to adjust when storing to memory. */ | |
67c0d1eb RS |
7088 | macro_build (&offset_expr, "swc1", "T,o(b)", |
7089 | target_big_endian ? treg + 1 : treg, BFD_RELOC_LO16, breg); | |
252b5132 | 7090 | offset_expr.X_add_number += 4; |
67c0d1eb RS |
7091 | macro_build (&offset_expr, "swc1", "T,o(b)", |
7092 | target_big_endian ? treg : treg + 1, BFD_RELOC_LO16, breg); | |
8fc2e39e | 7093 | break; |
252b5132 RH |
7094 | |
7095 | case M_SEQ: | |
7096 | if (sreg == 0) | |
67c0d1eb | 7097 | macro_build (&expr1, "sltiu", "t,r,j", dreg, treg, BFD_RELOC_LO16); |
252b5132 | 7098 | else if (treg == 0) |
67c0d1eb | 7099 | macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7100 | else |
7101 | { | |
67c0d1eb RS |
7102 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg); |
7103 | macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16); | |
252b5132 | 7104 | } |
8fc2e39e | 7105 | break; |
252b5132 RH |
7106 | |
7107 | case M_SEQ_I: | |
7108 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
7109 | { | |
67c0d1eb | 7110 | macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 7111 | break; |
252b5132 RH |
7112 | } |
7113 | if (sreg == 0) | |
7114 | { | |
7115 | as_warn (_("Instruction %s: result is always false"), | |
7116 | ip->insn_mo->name); | |
67c0d1eb | 7117 | move_register (dreg, 0); |
8fc2e39e | 7118 | break; |
252b5132 RH |
7119 | } |
7120 | if (imm_expr.X_op == O_constant | |
7121 | && imm_expr.X_add_number >= 0 | |
7122 | && imm_expr.X_add_number < 0x10000) | |
7123 | { | |
67c0d1eb | 7124 | macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7125 | } |
7126 | else if (imm_expr.X_op == O_constant | |
7127 | && imm_expr.X_add_number > -0x8000 | |
7128 | && imm_expr.X_add_number < 0) | |
7129 | { | |
7130 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 7131 | macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu", |
17a2f251 | 7132 | "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7133 | } |
7134 | else | |
7135 | { | |
67c0d1eb RS |
7136 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7137 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7138 | used_at = 1; |
7139 | } | |
67c0d1eb | 7140 | macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16); |
8fc2e39e | 7141 | break; |
252b5132 RH |
7142 | |
7143 | case M_SGE: /* sreg >= treg <==> not (sreg < treg) */ | |
7144 | s = "slt"; | |
7145 | goto sge; | |
7146 | case M_SGEU: | |
7147 | s = "sltu"; | |
7148 | sge: | |
67c0d1eb RS |
7149 | macro_build (NULL, s, "d,v,t", dreg, sreg, treg); |
7150 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
8fc2e39e | 7151 | break; |
252b5132 RH |
7152 | |
7153 | case M_SGE_I: /* sreg >= I <==> not (sreg < I) */ | |
7154 | case M_SGEU_I: | |
7155 | if (imm_expr.X_op == O_constant | |
7156 | && imm_expr.X_add_number >= -0x8000 | |
7157 | && imm_expr.X_add_number < 0x8000) | |
7158 | { | |
67c0d1eb RS |
7159 | macro_build (&imm_expr, mask == M_SGE_I ? "slti" : "sltiu", "t,r,j", |
7160 | dreg, sreg, BFD_RELOC_LO16); | |
252b5132 RH |
7161 | } |
7162 | else | |
7163 | { | |
67c0d1eb RS |
7164 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7165 | macro_build (NULL, mask == M_SGE_I ? "slt" : "sltu", "d,v,t", | |
7166 | dreg, sreg, AT); | |
252b5132 RH |
7167 | used_at = 1; |
7168 | } | |
67c0d1eb | 7169 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); |
8fc2e39e | 7170 | break; |
252b5132 RH |
7171 | |
7172 | case M_SGT: /* sreg > treg <==> treg < sreg */ | |
7173 | s = "slt"; | |
7174 | goto sgt; | |
7175 | case M_SGTU: | |
7176 | s = "sltu"; | |
7177 | sgt: | |
67c0d1eb | 7178 | macro_build (NULL, s, "d,v,t", dreg, treg, sreg); |
8fc2e39e | 7179 | break; |
252b5132 RH |
7180 | |
7181 | case M_SGT_I: /* sreg > I <==> I < sreg */ | |
7182 | s = "slt"; | |
7183 | goto sgti; | |
7184 | case M_SGTU_I: | |
7185 | s = "sltu"; | |
7186 | sgti: | |
8fc2e39e | 7187 | used_at = 1; |
67c0d1eb RS |
7188 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7189 | macro_build (NULL, s, "d,v,t", dreg, AT, sreg); | |
252b5132 RH |
7190 | break; |
7191 | ||
2396cfb9 | 7192 | case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */ |
252b5132 RH |
7193 | s = "slt"; |
7194 | goto sle; | |
7195 | case M_SLEU: | |
7196 | s = "sltu"; | |
7197 | sle: | |
67c0d1eb RS |
7198 | macro_build (NULL, s, "d,v,t", dreg, treg, sreg); |
7199 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
8fc2e39e | 7200 | break; |
252b5132 | 7201 | |
2396cfb9 | 7202 | case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */ |
252b5132 RH |
7203 | s = "slt"; |
7204 | goto slei; | |
7205 | case M_SLEU_I: | |
7206 | s = "sltu"; | |
7207 | slei: | |
8fc2e39e | 7208 | used_at = 1; |
67c0d1eb RS |
7209 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7210 | macro_build (NULL, s, "d,v,t", dreg, AT, sreg); | |
7211 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
252b5132 RH |
7212 | break; |
7213 | ||
7214 | case M_SLT_I: | |
7215 | if (imm_expr.X_op == O_constant | |
7216 | && imm_expr.X_add_number >= -0x8000 | |
7217 | && imm_expr.X_add_number < 0x8000) | |
7218 | { | |
67c0d1eb | 7219 | macro_build (&imm_expr, "slti", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 7220 | break; |
252b5132 | 7221 | } |
8fc2e39e | 7222 | used_at = 1; |
67c0d1eb RS |
7223 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7224 | macro_build (NULL, "slt", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7225 | break; |
7226 | ||
7227 | case M_SLTU_I: | |
7228 | if (imm_expr.X_op == O_constant | |
7229 | && imm_expr.X_add_number >= -0x8000 | |
7230 | && imm_expr.X_add_number < 0x8000) | |
7231 | { | |
67c0d1eb | 7232 | macro_build (&imm_expr, "sltiu", "t,r,j", dreg, sreg, |
17a2f251 | 7233 | BFD_RELOC_LO16); |
8fc2e39e | 7234 | break; |
252b5132 | 7235 | } |
8fc2e39e | 7236 | used_at = 1; |
67c0d1eb RS |
7237 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7238 | macro_build (NULL, "sltu", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7239 | break; |
7240 | ||
7241 | case M_SNE: | |
7242 | if (sreg == 0) | |
67c0d1eb | 7243 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, treg); |
252b5132 | 7244 | else if (treg == 0) |
67c0d1eb | 7245 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg); |
252b5132 RH |
7246 | else |
7247 | { | |
67c0d1eb RS |
7248 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg); |
7249 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg); | |
252b5132 | 7250 | } |
8fc2e39e | 7251 | break; |
252b5132 RH |
7252 | |
7253 | case M_SNE_I: | |
7254 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
7255 | { | |
67c0d1eb | 7256 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg); |
8fc2e39e | 7257 | break; |
252b5132 RH |
7258 | } |
7259 | if (sreg == 0) | |
7260 | { | |
7261 | as_warn (_("Instruction %s: result is always true"), | |
7262 | ip->insn_mo->name); | |
67c0d1eb RS |
7263 | macro_build (&expr1, HAVE_32BIT_GPRS ? "addiu" : "daddiu", "t,r,j", |
7264 | dreg, 0, BFD_RELOC_LO16); | |
8fc2e39e | 7265 | break; |
252b5132 RH |
7266 | } |
7267 | if (imm_expr.X_op == O_constant | |
7268 | && imm_expr.X_add_number >= 0 | |
7269 | && imm_expr.X_add_number < 0x10000) | |
7270 | { | |
67c0d1eb | 7271 | macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7272 | } |
7273 | else if (imm_expr.X_op == O_constant | |
7274 | && imm_expr.X_add_number > -0x8000 | |
7275 | && imm_expr.X_add_number < 0) | |
7276 | { | |
7277 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 7278 | macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu", |
17a2f251 | 7279 | "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7280 | } |
7281 | else | |
7282 | { | |
67c0d1eb RS |
7283 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7284 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7285 | used_at = 1; |
7286 | } | |
67c0d1eb | 7287 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg); |
8fc2e39e | 7288 | break; |
252b5132 RH |
7289 | |
7290 | case M_DSUB_I: | |
7291 | dbl = 1; | |
7292 | case M_SUB_I: | |
7293 | if (imm_expr.X_op == O_constant | |
7294 | && imm_expr.X_add_number > -0x8000 | |
7295 | && imm_expr.X_add_number <= 0x8000) | |
7296 | { | |
7297 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb RS |
7298 | macro_build (&imm_expr, dbl ? "daddi" : "addi", "t,r,j", |
7299 | dreg, sreg, BFD_RELOC_LO16); | |
8fc2e39e | 7300 | break; |
252b5132 | 7301 | } |
8fc2e39e | 7302 | used_at = 1; |
67c0d1eb RS |
7303 | load_register (AT, &imm_expr, dbl); |
7304 | macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7305 | break; |
7306 | ||
7307 | case M_DSUBU_I: | |
7308 | dbl = 1; | |
7309 | case M_SUBU_I: | |
7310 | if (imm_expr.X_op == O_constant | |
7311 | && imm_expr.X_add_number > -0x8000 | |
7312 | && imm_expr.X_add_number <= 0x8000) | |
7313 | { | |
7314 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb RS |
7315 | macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "t,r,j", |
7316 | dreg, sreg, BFD_RELOC_LO16); | |
8fc2e39e | 7317 | break; |
252b5132 | 7318 | } |
8fc2e39e | 7319 | used_at = 1; |
67c0d1eb RS |
7320 | load_register (AT, &imm_expr, dbl); |
7321 | macro_build (NULL, dbl ? "dsubu" : "subu", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7322 | break; |
7323 | ||
7324 | case M_TEQ_I: | |
7325 | s = "teq"; | |
7326 | goto trap; | |
7327 | case M_TGE_I: | |
7328 | s = "tge"; | |
7329 | goto trap; | |
7330 | case M_TGEU_I: | |
7331 | s = "tgeu"; | |
7332 | goto trap; | |
7333 | case M_TLT_I: | |
7334 | s = "tlt"; | |
7335 | goto trap; | |
7336 | case M_TLTU_I: | |
7337 | s = "tltu"; | |
7338 | goto trap; | |
7339 | case M_TNE_I: | |
7340 | s = "tne"; | |
7341 | trap: | |
8fc2e39e | 7342 | used_at = 1; |
67c0d1eb RS |
7343 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7344 | macro_build (NULL, s, "s,t", sreg, AT); | |
252b5132 RH |
7345 | break; |
7346 | ||
252b5132 | 7347 | case M_TRUNCWS: |
43841e91 | 7348 | case M_TRUNCWD: |
e7af610e | 7349 | assert (mips_opts.isa == ISA_MIPS1); |
8fc2e39e | 7350 | used_at = 1; |
252b5132 RH |
7351 | sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */ |
7352 | dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */ | |
7353 | ||
7354 | /* | |
7355 | * Is the double cfc1 instruction a bug in the mips assembler; | |
7356 | * or is there a reason for it? | |
7357 | */ | |
7d10b47d | 7358 | start_noreorder (); |
67c0d1eb RS |
7359 | macro_build (NULL, "cfc1", "t,G", treg, RA); |
7360 | macro_build (NULL, "cfc1", "t,G", treg, RA); | |
7361 | macro_build (NULL, "nop", ""); | |
252b5132 | 7362 | expr1.X_add_number = 3; |
67c0d1eb | 7363 | macro_build (&expr1, "ori", "t,r,i", AT, treg, BFD_RELOC_LO16); |
252b5132 | 7364 | expr1.X_add_number = 2; |
67c0d1eb RS |
7365 | macro_build (&expr1, "xori", "t,r,i", AT, AT, BFD_RELOC_LO16); |
7366 | macro_build (NULL, "ctc1", "t,G", AT, RA); | |
7367 | macro_build (NULL, "nop", ""); | |
7368 | macro_build (NULL, mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S", | |
7369 | dreg, sreg); | |
7370 | macro_build (NULL, "ctc1", "t,G", treg, RA); | |
7371 | macro_build (NULL, "nop", ""); | |
7d10b47d | 7372 | end_noreorder (); |
252b5132 RH |
7373 | break; |
7374 | ||
7375 | case M_ULH: | |
7376 | s = "lb"; | |
7377 | goto ulh; | |
7378 | case M_ULHU: | |
7379 | s = "lbu"; | |
7380 | ulh: | |
8fc2e39e | 7381 | used_at = 1; |
252b5132 RH |
7382 | if (offset_expr.X_add_number >= 0x7fff) |
7383 | as_bad (_("operand overflow")); | |
252b5132 | 7384 | if (! target_big_endian) |
f9419b05 | 7385 | ++offset_expr.X_add_number; |
67c0d1eb | 7386 | macro_build (&offset_expr, s, "t,o(b)", AT, BFD_RELOC_LO16, breg); |
252b5132 | 7387 | if (! target_big_endian) |
f9419b05 | 7388 | --offset_expr.X_add_number; |
252b5132 | 7389 | else |
f9419b05 | 7390 | ++offset_expr.X_add_number; |
67c0d1eb RS |
7391 | macro_build (&offset_expr, "lbu", "t,o(b)", treg, BFD_RELOC_LO16, breg); |
7392 | macro_build (NULL, "sll", "d,w,<", AT, AT, 8); | |
7393 | macro_build (NULL, "or", "d,v,t", treg, treg, AT); | |
252b5132 RH |
7394 | break; |
7395 | ||
7396 | case M_ULD: | |
7397 | s = "ldl"; | |
7398 | s2 = "ldr"; | |
7399 | off = 7; | |
7400 | goto ulw; | |
7401 | case M_ULW: | |
7402 | s = "lwl"; | |
7403 | s2 = "lwr"; | |
7404 | off = 3; | |
7405 | ulw: | |
7406 | if (offset_expr.X_add_number >= 0x8000 - off) | |
7407 | as_bad (_("operand overflow")); | |
af22f5b2 CD |
7408 | if (treg != breg) |
7409 | tempreg = treg; | |
7410 | else | |
8fc2e39e TS |
7411 | { |
7412 | used_at = 1; | |
7413 | tempreg = AT; | |
7414 | } | |
252b5132 RH |
7415 | if (! target_big_endian) |
7416 | offset_expr.X_add_number += off; | |
67c0d1eb | 7417 | macro_build (&offset_expr, s, "t,o(b)", tempreg, BFD_RELOC_LO16, breg); |
252b5132 RH |
7418 | if (! target_big_endian) |
7419 | offset_expr.X_add_number -= off; | |
7420 | else | |
7421 | offset_expr.X_add_number += off; | |
67c0d1eb | 7422 | macro_build (&offset_expr, s2, "t,o(b)", tempreg, BFD_RELOC_LO16, breg); |
af22f5b2 CD |
7423 | |
7424 | /* If necessary, move the result in tempreg the final destination. */ | |
7425 | if (treg == tempreg) | |
8fc2e39e | 7426 | break; |
af22f5b2 | 7427 | /* Protect second load's delay slot. */ |
017315e4 | 7428 | load_delay_nop (); |
67c0d1eb | 7429 | move_register (treg, tempreg); |
af22f5b2 | 7430 | break; |
252b5132 RH |
7431 | |
7432 | case M_ULD_A: | |
7433 | s = "ldl"; | |
7434 | s2 = "ldr"; | |
7435 | off = 7; | |
7436 | goto ulwa; | |
7437 | case M_ULW_A: | |
7438 | s = "lwl"; | |
7439 | s2 = "lwr"; | |
7440 | off = 3; | |
7441 | ulwa: | |
d6bc6245 | 7442 | used_at = 1; |
67c0d1eb | 7443 | load_address (AT, &offset_expr, &used_at); |
252b5132 | 7444 | if (breg != 0) |
67c0d1eb | 7445 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); |
252b5132 RH |
7446 | if (! target_big_endian) |
7447 | expr1.X_add_number = off; | |
7448 | else | |
7449 | expr1.X_add_number = 0; | |
67c0d1eb | 7450 | macro_build (&expr1, s, "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
7451 | if (! target_big_endian) |
7452 | expr1.X_add_number = 0; | |
7453 | else | |
7454 | expr1.X_add_number = off; | |
67c0d1eb | 7455 | macro_build (&expr1, s2, "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
7456 | break; |
7457 | ||
7458 | case M_ULH_A: | |
7459 | case M_ULHU_A: | |
d6bc6245 | 7460 | used_at = 1; |
67c0d1eb | 7461 | load_address (AT, &offset_expr, &used_at); |
252b5132 | 7462 | if (breg != 0) |
67c0d1eb | 7463 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); |
252b5132 RH |
7464 | if (target_big_endian) |
7465 | expr1.X_add_number = 0; | |
67c0d1eb | 7466 | macro_build (&expr1, mask == M_ULH_A ? "lb" : "lbu", "t,o(b)", |
17a2f251 | 7467 | treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
7468 | if (target_big_endian) |
7469 | expr1.X_add_number = 1; | |
7470 | else | |
7471 | expr1.X_add_number = 0; | |
67c0d1eb RS |
7472 | macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT); |
7473 | macro_build (NULL, "sll", "d,w,<", treg, treg, 8); | |
7474 | macro_build (NULL, "or", "d,v,t", treg, treg, AT); | |
252b5132 RH |
7475 | break; |
7476 | ||
7477 | case M_USH: | |
8fc2e39e | 7478 | used_at = 1; |
252b5132 RH |
7479 | if (offset_expr.X_add_number >= 0x7fff) |
7480 | as_bad (_("operand overflow")); | |
7481 | if (target_big_endian) | |
f9419b05 | 7482 | ++offset_expr.X_add_number; |
67c0d1eb RS |
7483 | macro_build (&offset_expr, "sb", "t,o(b)", treg, BFD_RELOC_LO16, breg); |
7484 | macro_build (NULL, "srl", "d,w,<", AT, treg, 8); | |
252b5132 | 7485 | if (target_big_endian) |
f9419b05 | 7486 | --offset_expr.X_add_number; |
252b5132 | 7487 | else |
f9419b05 | 7488 | ++offset_expr.X_add_number; |
67c0d1eb | 7489 | macro_build (&offset_expr, "sb", "t,o(b)", AT, BFD_RELOC_LO16, breg); |
252b5132 RH |
7490 | break; |
7491 | ||
7492 | case M_USD: | |
7493 | s = "sdl"; | |
7494 | s2 = "sdr"; | |
7495 | off = 7; | |
7496 | goto usw; | |
7497 | case M_USW: | |
7498 | s = "swl"; | |
7499 | s2 = "swr"; | |
7500 | off = 3; | |
7501 | usw: | |
7502 | if (offset_expr.X_add_number >= 0x8000 - off) | |
7503 | as_bad (_("operand overflow")); | |
7504 | if (! target_big_endian) | |
7505 | offset_expr.X_add_number += off; | |
67c0d1eb | 7506 | macro_build (&offset_expr, s, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
252b5132 RH |
7507 | if (! target_big_endian) |
7508 | offset_expr.X_add_number -= off; | |
7509 | else | |
7510 | offset_expr.X_add_number += off; | |
67c0d1eb | 7511 | macro_build (&offset_expr, s2, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
8fc2e39e | 7512 | break; |
252b5132 RH |
7513 | |
7514 | case M_USD_A: | |
7515 | s = "sdl"; | |
7516 | s2 = "sdr"; | |
7517 | off = 7; | |
7518 | goto uswa; | |
7519 | case M_USW_A: | |
7520 | s = "swl"; | |
7521 | s2 = "swr"; | |
7522 | off = 3; | |
7523 | uswa: | |
d6bc6245 | 7524 | used_at = 1; |
67c0d1eb | 7525 | load_address (AT, &offset_expr, &used_at); |
252b5132 | 7526 | if (breg != 0) |
67c0d1eb | 7527 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); |
252b5132 RH |
7528 | if (! target_big_endian) |
7529 | expr1.X_add_number = off; | |
7530 | else | |
7531 | expr1.X_add_number = 0; | |
67c0d1eb | 7532 | macro_build (&expr1, s, "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
7533 | if (! target_big_endian) |
7534 | expr1.X_add_number = 0; | |
7535 | else | |
7536 | expr1.X_add_number = off; | |
67c0d1eb | 7537 | macro_build (&expr1, s2, "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
7538 | break; |
7539 | ||
7540 | case M_USH_A: | |
d6bc6245 | 7541 | used_at = 1; |
67c0d1eb | 7542 | load_address (AT, &offset_expr, &used_at); |
252b5132 | 7543 | if (breg != 0) |
67c0d1eb | 7544 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); |
252b5132 RH |
7545 | if (! target_big_endian) |
7546 | expr1.X_add_number = 0; | |
67c0d1eb RS |
7547 | macro_build (&expr1, "sb", "t,o(b)", treg, BFD_RELOC_LO16, AT); |
7548 | macro_build (NULL, "srl", "d,w,<", treg, treg, 8); | |
252b5132 RH |
7549 | if (! target_big_endian) |
7550 | expr1.X_add_number = 1; | |
7551 | else | |
7552 | expr1.X_add_number = 0; | |
67c0d1eb | 7553 | macro_build (&expr1, "sb", "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
7554 | if (! target_big_endian) |
7555 | expr1.X_add_number = 0; | |
7556 | else | |
7557 | expr1.X_add_number = 1; | |
67c0d1eb RS |
7558 | macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT); |
7559 | macro_build (NULL, "sll", "d,w,<", treg, treg, 8); | |
7560 | macro_build (NULL, "or", "d,v,t", treg, treg, AT); | |
252b5132 RH |
7561 | break; |
7562 | ||
7563 | default: | |
7564 | /* FIXME: Check if this is one of the itbl macros, since they | |
bdaaa2e1 | 7565 | are added dynamically. */ |
252b5132 RH |
7566 | as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name); |
7567 | break; | |
7568 | } | |
8fc2e39e TS |
7569 | if (mips_opts.noat && used_at) |
7570 | as_bad (_("Macro used $at after \".set noat\"")); | |
252b5132 RH |
7571 | } |
7572 | ||
7573 | /* Implement macros in mips16 mode. */ | |
7574 | ||
7575 | static void | |
17a2f251 | 7576 | mips16_macro (struct mips_cl_insn *ip) |
252b5132 RH |
7577 | { |
7578 | int mask; | |
7579 | int xreg, yreg, zreg, tmp; | |
252b5132 RH |
7580 | expressionS expr1; |
7581 | int dbl; | |
7582 | const char *s, *s2, *s3; | |
7583 | ||
7584 | mask = ip->insn_mo->mask; | |
7585 | ||
bf12938e RS |
7586 | xreg = MIPS16_EXTRACT_OPERAND (RX, *ip); |
7587 | yreg = MIPS16_EXTRACT_OPERAND (RY, *ip); | |
7588 | zreg = MIPS16_EXTRACT_OPERAND (RZ, *ip); | |
252b5132 | 7589 | |
252b5132 RH |
7590 | expr1.X_op = O_constant; |
7591 | expr1.X_op_symbol = NULL; | |
7592 | expr1.X_add_symbol = NULL; | |
7593 | expr1.X_add_number = 1; | |
7594 | ||
7595 | dbl = 0; | |
7596 | ||
7597 | switch (mask) | |
7598 | { | |
7599 | default: | |
7600 | internalError (); | |
7601 | ||
7602 | case M_DDIV_3: | |
7603 | dbl = 1; | |
7604 | case M_DIV_3: | |
7605 | s = "mflo"; | |
7606 | goto do_div3; | |
7607 | case M_DREM_3: | |
7608 | dbl = 1; | |
7609 | case M_REM_3: | |
7610 | s = "mfhi"; | |
7611 | do_div3: | |
7d10b47d | 7612 | start_noreorder (); |
67c0d1eb | 7613 | macro_build (NULL, dbl ? "ddiv" : "div", "0,x,y", xreg, yreg); |
252b5132 | 7614 | expr1.X_add_number = 2; |
67c0d1eb RS |
7615 | macro_build (&expr1, "bnez", "x,p", yreg); |
7616 | macro_build (NULL, "break", "6", 7); | |
bdaaa2e1 | 7617 | |
252b5132 RH |
7618 | /* FIXME: The normal code checks for of -1 / -0x80000000 here, |
7619 | since that causes an overflow. We should do that as well, | |
7620 | but I don't see how to do the comparisons without a temporary | |
7621 | register. */ | |
7d10b47d | 7622 | end_noreorder (); |
67c0d1eb | 7623 | macro_build (NULL, s, "x", zreg); |
252b5132 RH |
7624 | break; |
7625 | ||
7626 | case M_DIVU_3: | |
7627 | s = "divu"; | |
7628 | s2 = "mflo"; | |
7629 | goto do_divu3; | |
7630 | case M_REMU_3: | |
7631 | s = "divu"; | |
7632 | s2 = "mfhi"; | |
7633 | goto do_divu3; | |
7634 | case M_DDIVU_3: | |
7635 | s = "ddivu"; | |
7636 | s2 = "mflo"; | |
7637 | goto do_divu3; | |
7638 | case M_DREMU_3: | |
7639 | s = "ddivu"; | |
7640 | s2 = "mfhi"; | |
7641 | do_divu3: | |
7d10b47d | 7642 | start_noreorder (); |
67c0d1eb | 7643 | macro_build (NULL, s, "0,x,y", xreg, yreg); |
252b5132 | 7644 | expr1.X_add_number = 2; |
67c0d1eb RS |
7645 | macro_build (&expr1, "bnez", "x,p", yreg); |
7646 | macro_build (NULL, "break", "6", 7); | |
7d10b47d | 7647 | end_noreorder (); |
67c0d1eb | 7648 | macro_build (NULL, s2, "x", zreg); |
252b5132 RH |
7649 | break; |
7650 | ||
7651 | case M_DMUL: | |
7652 | dbl = 1; | |
7653 | case M_MUL: | |
67c0d1eb RS |
7654 | macro_build (NULL, dbl ? "dmultu" : "multu", "x,y", xreg, yreg); |
7655 | macro_build (NULL, "mflo", "x", zreg); | |
8fc2e39e | 7656 | break; |
252b5132 RH |
7657 | |
7658 | case M_DSUBU_I: | |
7659 | dbl = 1; | |
7660 | goto do_subu; | |
7661 | case M_SUBU_I: | |
7662 | do_subu: | |
7663 | if (imm_expr.X_op != O_constant) | |
7664 | as_bad (_("Unsupported large constant")); | |
7665 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 7666 | macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "y,x,4", yreg, xreg); |
252b5132 RH |
7667 | break; |
7668 | ||
7669 | case M_SUBU_I_2: | |
7670 | if (imm_expr.X_op != O_constant) | |
7671 | as_bad (_("Unsupported large constant")); | |
7672 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 7673 | macro_build (&imm_expr, "addiu", "x,k", xreg); |
252b5132 RH |
7674 | break; |
7675 | ||
7676 | case M_DSUBU_I_2: | |
7677 | if (imm_expr.X_op != O_constant) | |
7678 | as_bad (_("Unsupported large constant")); | |
7679 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 7680 | macro_build (&imm_expr, "daddiu", "y,j", yreg); |
252b5132 RH |
7681 | break; |
7682 | ||
7683 | case M_BEQ: | |
7684 | s = "cmp"; | |
7685 | s2 = "bteqz"; | |
7686 | goto do_branch; | |
7687 | case M_BNE: | |
7688 | s = "cmp"; | |
7689 | s2 = "btnez"; | |
7690 | goto do_branch; | |
7691 | case M_BLT: | |
7692 | s = "slt"; | |
7693 | s2 = "btnez"; | |
7694 | goto do_branch; | |
7695 | case M_BLTU: | |
7696 | s = "sltu"; | |
7697 | s2 = "btnez"; | |
7698 | goto do_branch; | |
7699 | case M_BLE: | |
7700 | s = "slt"; | |
7701 | s2 = "bteqz"; | |
7702 | goto do_reverse_branch; | |
7703 | case M_BLEU: | |
7704 | s = "sltu"; | |
7705 | s2 = "bteqz"; | |
7706 | goto do_reverse_branch; | |
7707 | case M_BGE: | |
7708 | s = "slt"; | |
7709 | s2 = "bteqz"; | |
7710 | goto do_branch; | |
7711 | case M_BGEU: | |
7712 | s = "sltu"; | |
7713 | s2 = "bteqz"; | |
7714 | goto do_branch; | |
7715 | case M_BGT: | |
7716 | s = "slt"; | |
7717 | s2 = "btnez"; | |
7718 | goto do_reverse_branch; | |
7719 | case M_BGTU: | |
7720 | s = "sltu"; | |
7721 | s2 = "btnez"; | |
7722 | ||
7723 | do_reverse_branch: | |
7724 | tmp = xreg; | |
7725 | xreg = yreg; | |
7726 | yreg = tmp; | |
7727 | ||
7728 | do_branch: | |
67c0d1eb RS |
7729 | macro_build (NULL, s, "x,y", xreg, yreg); |
7730 | macro_build (&offset_expr, s2, "p"); | |
252b5132 RH |
7731 | break; |
7732 | ||
7733 | case M_BEQ_I: | |
7734 | s = "cmpi"; | |
7735 | s2 = "bteqz"; | |
7736 | s3 = "x,U"; | |
7737 | goto do_branch_i; | |
7738 | case M_BNE_I: | |
7739 | s = "cmpi"; | |
7740 | s2 = "btnez"; | |
7741 | s3 = "x,U"; | |
7742 | goto do_branch_i; | |
7743 | case M_BLT_I: | |
7744 | s = "slti"; | |
7745 | s2 = "btnez"; | |
7746 | s3 = "x,8"; | |
7747 | goto do_branch_i; | |
7748 | case M_BLTU_I: | |
7749 | s = "sltiu"; | |
7750 | s2 = "btnez"; | |
7751 | s3 = "x,8"; | |
7752 | goto do_branch_i; | |
7753 | case M_BLE_I: | |
7754 | s = "slti"; | |
7755 | s2 = "btnez"; | |
7756 | s3 = "x,8"; | |
7757 | goto do_addone_branch_i; | |
7758 | case M_BLEU_I: | |
7759 | s = "sltiu"; | |
7760 | s2 = "btnez"; | |
7761 | s3 = "x,8"; | |
7762 | goto do_addone_branch_i; | |
7763 | case M_BGE_I: | |
7764 | s = "slti"; | |
7765 | s2 = "bteqz"; | |
7766 | s3 = "x,8"; | |
7767 | goto do_branch_i; | |
7768 | case M_BGEU_I: | |
7769 | s = "sltiu"; | |
7770 | s2 = "bteqz"; | |
7771 | s3 = "x,8"; | |
7772 | goto do_branch_i; | |
7773 | case M_BGT_I: | |
7774 | s = "slti"; | |
7775 | s2 = "bteqz"; | |
7776 | s3 = "x,8"; | |
7777 | goto do_addone_branch_i; | |
7778 | case M_BGTU_I: | |
7779 | s = "sltiu"; | |
7780 | s2 = "bteqz"; | |
7781 | s3 = "x,8"; | |
7782 | ||
7783 | do_addone_branch_i: | |
7784 | if (imm_expr.X_op != O_constant) | |
7785 | as_bad (_("Unsupported large constant")); | |
7786 | ++imm_expr.X_add_number; | |
7787 | ||
7788 | do_branch_i: | |
67c0d1eb RS |
7789 | macro_build (&imm_expr, s, s3, xreg); |
7790 | macro_build (&offset_expr, s2, "p"); | |
252b5132 RH |
7791 | break; |
7792 | ||
7793 | case M_ABS: | |
7794 | expr1.X_add_number = 0; | |
67c0d1eb | 7795 | macro_build (&expr1, "slti", "x,8", yreg); |
252b5132 | 7796 | if (xreg != yreg) |
67c0d1eb | 7797 | move_register (xreg, yreg); |
252b5132 | 7798 | expr1.X_add_number = 2; |
67c0d1eb RS |
7799 | macro_build (&expr1, "bteqz", "p"); |
7800 | macro_build (NULL, "neg", "x,w", xreg, xreg); | |
252b5132 RH |
7801 | } |
7802 | } | |
7803 | ||
7804 | /* For consistency checking, verify that all bits are specified either | |
7805 | by the match/mask part of the instruction definition, or by the | |
7806 | operand list. */ | |
7807 | static int | |
17a2f251 | 7808 | validate_mips_insn (const struct mips_opcode *opc) |
252b5132 RH |
7809 | { |
7810 | const char *p = opc->args; | |
7811 | char c; | |
7812 | unsigned long used_bits = opc->mask; | |
7813 | ||
7814 | if ((used_bits & opc->match) != opc->match) | |
7815 | { | |
7816 | as_bad (_("internal: bad mips opcode (mask error): %s %s"), | |
7817 | opc->name, opc->args); | |
7818 | return 0; | |
7819 | } | |
7820 | #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift))) | |
7821 | while (*p) | |
7822 | switch (c = *p++) | |
7823 | { | |
7824 | case ',': break; | |
7825 | case '(': break; | |
7826 | case ')': break; | |
af7ee8bf CD |
7827 | case '+': |
7828 | switch (c = *p++) | |
7829 | { | |
9bcd4f99 TS |
7830 | case '1': USE_BITS (OP_MASK_UDI1, OP_SH_UDI1); break; |
7831 | case '2': USE_BITS (OP_MASK_UDI2, OP_SH_UDI2); break; | |
7832 | case '3': USE_BITS (OP_MASK_UDI3, OP_SH_UDI3); break; | |
7833 | case '4': USE_BITS (OP_MASK_UDI4, OP_SH_UDI4); break; | |
af7ee8bf CD |
7834 | case 'A': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
7835 | case 'B': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break; | |
7836 | case 'C': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
bbcc0807 CD |
7837 | case 'D': USE_BITS (OP_MASK_RD, OP_SH_RD); |
7838 | USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; | |
5f74bc13 CD |
7839 | case 'E': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
7840 | case 'F': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break; | |
7841 | case 'G': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
7842 | case 'H': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
7843 | case 'I': break; | |
ef2e4d86 CF |
7844 | case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break; |
7845 | case 'T': USE_BITS (OP_MASK_RT, OP_SH_RT); | |
7846 | USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; | |
af7ee8bf CD |
7847 | default: |
7848 | as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"), | |
7849 | c, opc->name, opc->args); | |
7850 | return 0; | |
7851 | } | |
7852 | break; | |
252b5132 RH |
7853 | case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
7854 | case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; | |
7855 | case 'A': break; | |
4372b673 | 7856 | case 'B': USE_BITS (OP_MASK_CODE20, OP_SH_CODE20); break; |
252b5132 RH |
7857 | case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break; |
7858 | case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break; | |
7859 | case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
7860 | case 'F': break; | |
7861 | case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
156c2f8b | 7862 | case 'H': USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; |
252b5132 | 7863 | case 'I': break; |
e972090a | 7864 | case 'J': USE_BITS (OP_MASK_CODE19, OP_SH_CODE19); break; |
af7ee8bf | 7865 | case 'K': USE_BITS (OP_MASK_RD, OP_SH_RD); break; |
252b5132 RH |
7866 | case 'L': break; |
7867 | case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break; | |
7868 | case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break; | |
deec1734 CD |
7869 | case 'O': USE_BITS (OP_MASK_ALN, OP_SH_ALN); break; |
7870 | case 'Q': USE_BITS (OP_MASK_VSEL, OP_SH_VSEL); | |
7871 | USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
252b5132 RH |
7872 | case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break; |
7873 | case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
7874 | case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
7875 | case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
7876 | case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
deec1734 CD |
7877 | case 'X': USE_BITS (OP_MASK_FD, OP_SH_FD); break; |
7878 | case 'Y': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
7879 | case 'Z': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
252b5132 RH |
7880 | case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break; |
7881 | case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
7882 | case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break; | |
7883 | case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
7884 | case 'f': break; | |
7885 | case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break; | |
7886 | case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; | |
7887 | case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
7888 | case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break; | |
7889 | case 'l': break; | |
7890 | case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
7891 | case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
7892 | case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break; | |
7893 | case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
7894 | case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
7895 | case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
7896 | case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; | |
7897 | case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
7898 | case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
7899 | case 'x': break; | |
7900 | case 'z': break; | |
7901 | case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break; | |
4372b673 NC |
7902 | case 'U': USE_BITS (OP_MASK_RD, OP_SH_RD); |
7903 | USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
60b63b72 RS |
7904 | case 'e': USE_BITS (OP_MASK_VECBYTE, OP_SH_VECBYTE); break; |
7905 | case '%': USE_BITS (OP_MASK_VECALIGN, OP_SH_VECALIGN); break; | |
7906 | case '[': break; | |
7907 | case ']': break; | |
74cd071d CF |
7908 | case '3': USE_BITS (OP_MASK_SA3, OP_SH_SA3); break; |
7909 | case '4': USE_BITS (OP_MASK_SA4, OP_SH_SA4); break; | |
7910 | case '5': USE_BITS (OP_MASK_IMM8, OP_SH_IMM8); break; | |
7911 | case '6': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
7912 | case '7': USE_BITS (OP_MASK_DSPACC, OP_SH_DSPACC); break; | |
7913 | case '8': USE_BITS (OP_MASK_WRDSP, OP_SH_WRDSP); break; | |
7914 | case '9': USE_BITS (OP_MASK_DSPACC_S, OP_SH_DSPACC_S);break; | |
7915 | case '0': USE_BITS (OP_MASK_DSPSFT, OP_SH_DSPSFT); break; | |
7916 | case '\'': USE_BITS (OP_MASK_RDDSP, OP_SH_RDDSP); break; | |
7917 | case ':': USE_BITS (OP_MASK_DSPSFT_7, OP_SH_DSPSFT_7);break; | |
7918 | case '@': USE_BITS (OP_MASK_IMM10, OP_SH_IMM10); break; | |
ef2e4d86 CF |
7919 | case '!': USE_BITS (OP_MASK_MT_U, OP_SH_MT_U); break; |
7920 | case '$': USE_BITS (OP_MASK_MT_H, OP_SH_MT_H); break; | |
7921 | case '*': USE_BITS (OP_MASK_MTACC_T, OP_SH_MTACC_T); break; | |
7922 | case '&': USE_BITS (OP_MASK_MTACC_D, OP_SH_MTACC_D); break; | |
7923 | case 'g': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
252b5132 RH |
7924 | default: |
7925 | as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"), | |
7926 | c, opc->name, opc->args); | |
7927 | return 0; | |
7928 | } | |
7929 | #undef USE_BITS | |
7930 | if (used_bits != 0xffffffff) | |
7931 | { | |
7932 | as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"), | |
7933 | ~used_bits & 0xffffffff, opc->name, opc->args); | |
7934 | return 0; | |
7935 | } | |
7936 | return 1; | |
7937 | } | |
7938 | ||
9bcd4f99 TS |
7939 | /* UDI immediates. */ |
7940 | struct mips_immed { | |
7941 | char type; | |
7942 | unsigned int shift; | |
7943 | unsigned long mask; | |
7944 | const char * desc; | |
7945 | }; | |
7946 | ||
7947 | static const struct mips_immed mips_immed[] = { | |
7948 | { '1', OP_SH_UDI1, OP_MASK_UDI1, 0}, | |
7949 | { '2', OP_SH_UDI2, OP_MASK_UDI2, 0}, | |
7950 | { '3', OP_SH_UDI3, OP_MASK_UDI3, 0}, | |
7951 | { '4', OP_SH_UDI4, OP_MASK_UDI4, 0}, | |
7952 | { 0,0,0,0 } | |
7953 | }; | |
7954 | ||
252b5132 RH |
7955 | /* This routine assembles an instruction into its binary format. As a |
7956 | side effect, it sets one of the global variables imm_reloc or | |
7957 | offset_reloc to the type of relocation to do if one of the operands | |
7958 | is an address expression. */ | |
7959 | ||
7960 | static void | |
17a2f251 | 7961 | mips_ip (char *str, struct mips_cl_insn *ip) |
252b5132 RH |
7962 | { |
7963 | char *s; | |
7964 | const char *args; | |
43841e91 | 7965 | char c = 0; |
252b5132 RH |
7966 | struct mips_opcode *insn; |
7967 | char *argsStart; | |
7968 | unsigned int regno; | |
7969 | unsigned int lastregno = 0; | |
af7ee8bf | 7970 | unsigned int lastpos = 0; |
071742cf | 7971 | unsigned int limlo, limhi; |
252b5132 RH |
7972 | char *s_reset; |
7973 | char save_c = 0; | |
74cd071d | 7974 | offsetT min_range, max_range; |
252b5132 RH |
7975 | |
7976 | insn_error = NULL; | |
7977 | ||
7978 | /* If the instruction contains a '.', we first try to match an instruction | |
7979 | including the '.'. Then we try again without the '.'. */ | |
7980 | insn = NULL; | |
3882b010 | 7981 | for (s = str; *s != '\0' && !ISSPACE (*s); ++s) |
252b5132 RH |
7982 | continue; |
7983 | ||
7984 | /* If we stopped on whitespace, then replace the whitespace with null for | |
7985 | the call to hash_find. Save the character we replaced just in case we | |
7986 | have to re-parse the instruction. */ | |
3882b010 | 7987 | if (ISSPACE (*s)) |
252b5132 RH |
7988 | { |
7989 | save_c = *s; | |
7990 | *s++ = '\0'; | |
7991 | } | |
bdaaa2e1 | 7992 | |
252b5132 RH |
7993 | insn = (struct mips_opcode *) hash_find (op_hash, str); |
7994 | ||
7995 | /* If we didn't find the instruction in the opcode table, try again, but | |
7996 | this time with just the instruction up to, but not including the | |
7997 | first '.'. */ | |
7998 | if (insn == NULL) | |
7999 | { | |
bdaaa2e1 | 8000 | /* Restore the character we overwrite above (if any). */ |
252b5132 RH |
8001 | if (save_c) |
8002 | *(--s) = save_c; | |
8003 | ||
8004 | /* Scan up to the first '.' or whitespace. */ | |
3882b010 L |
8005 | for (s = str; |
8006 | *s != '\0' && *s != '.' && !ISSPACE (*s); | |
8007 | ++s) | |
252b5132 RH |
8008 | continue; |
8009 | ||
8010 | /* If we did not find a '.', then we can quit now. */ | |
8011 | if (*s != '.') | |
8012 | { | |
8013 | insn_error = "unrecognized opcode"; | |
8014 | return; | |
8015 | } | |
8016 | ||
8017 | /* Lookup the instruction in the hash table. */ | |
8018 | *s++ = '\0'; | |
8019 | if ((insn = (struct mips_opcode *) hash_find (op_hash, str)) == NULL) | |
8020 | { | |
8021 | insn_error = "unrecognized opcode"; | |
8022 | return; | |
8023 | } | |
252b5132 RH |
8024 | } |
8025 | ||
8026 | argsStart = s; | |
8027 | for (;;) | |
8028 | { | |
b34976b6 | 8029 | bfd_boolean ok; |
252b5132 RH |
8030 | |
8031 | assert (strcmp (insn->name, str) == 0); | |
8032 | ||
1f25f5d3 CD |
8033 | if (OPCODE_IS_MEMBER (insn, |
8034 | (mips_opts.isa | |
9b3f89ee TS |
8035 | /* We don't check for mips_opts.mips16 here since |
8036 | we want to allow jalx if -mips16 was specified | |
8037 | on the command line. */ | |
3396de36 | 8038 | | (file_ase_mips16 ? INSN_MIPS16 : 0) |
deec1734 | 8039 | | (mips_opts.ase_mdmx ? INSN_MDMX : 0) |
74cd071d | 8040 | | (mips_opts.ase_dsp ? INSN_DSP : 0) |
ef2e4d86 | 8041 | | (mips_opts.ase_mt ? INSN_MT : 0) |
e16bfa71 TS |
8042 | | (mips_opts.ase_mips3d ? INSN_MIPS3D : 0) |
8043 | | (mips_opts.ase_smartmips ? INSN_SMARTMIPS : 0)), | |
fef14a42 | 8044 | mips_opts.arch)) |
b34976b6 | 8045 | ok = TRUE; |
bdaaa2e1 | 8046 | else |
b34976b6 | 8047 | ok = FALSE; |
bdaaa2e1 | 8048 | |
252b5132 RH |
8049 | if (insn->pinfo != INSN_MACRO) |
8050 | { | |
fef14a42 | 8051 | if (mips_opts.arch == CPU_R4650 && (insn->pinfo & FP_D) != 0) |
b34976b6 | 8052 | ok = FALSE; |
252b5132 RH |
8053 | } |
8054 | ||
8055 | if (! ok) | |
8056 | { | |
8057 | if (insn + 1 < &mips_opcodes[NUMOPCODES] | |
8058 | && strcmp (insn->name, insn[1].name) == 0) | |
8059 | { | |
8060 | ++insn; | |
8061 | continue; | |
8062 | } | |
252b5132 | 8063 | else |
beae10d5 | 8064 | { |
268f6bed L |
8065 | if (!insn_error) |
8066 | { | |
8067 | static char buf[100]; | |
fef14a42 TS |
8068 | sprintf (buf, |
8069 | _("opcode not supported on this processor: %s (%s)"), | |
8070 | mips_cpu_info_from_arch (mips_opts.arch)->name, | |
8071 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
268f6bed L |
8072 | insn_error = buf; |
8073 | } | |
8074 | if (save_c) | |
8075 | *(--s) = save_c; | |
2bd7f1f3 | 8076 | return; |
252b5132 | 8077 | } |
252b5132 RH |
8078 | } |
8079 | ||
1e915849 | 8080 | create_insn (ip, insn); |
268f6bed | 8081 | insn_error = NULL; |
252b5132 RH |
8082 | for (args = insn->args;; ++args) |
8083 | { | |
deec1734 CD |
8084 | int is_mdmx; |
8085 | ||
ad8d3bb3 | 8086 | s += strspn (s, " \t"); |
deec1734 | 8087 | is_mdmx = 0; |
252b5132 RH |
8088 | switch (*args) |
8089 | { | |
8090 | case '\0': /* end of args */ | |
8091 | if (*s == '\0') | |
8092 | return; | |
8093 | break; | |
8094 | ||
74cd071d CF |
8095 | case '3': /* dsp 3-bit unsigned immediate in bit 21 */ |
8096 | my_getExpression (&imm_expr, s); | |
8097 | check_absolute_expr (ip, &imm_expr); | |
8098 | if (imm_expr.X_add_number & ~OP_MASK_SA3) | |
8099 | { | |
8100 | as_warn (_("DSP immediate not in range 0..%d (%lu)"), | |
8101 | OP_MASK_SA3, (unsigned long) imm_expr.X_add_number); | |
8102 | imm_expr.X_add_number &= OP_MASK_SA3; | |
8103 | } | |
8104 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_SA3; | |
8105 | imm_expr.X_op = O_absent; | |
8106 | s = expr_end; | |
8107 | continue; | |
8108 | ||
8109 | case '4': /* dsp 4-bit unsigned immediate in bit 21 */ | |
8110 | my_getExpression (&imm_expr, s); | |
8111 | check_absolute_expr (ip, &imm_expr); | |
8112 | if (imm_expr.X_add_number & ~OP_MASK_SA4) | |
8113 | { | |
8114 | as_warn (_("DSP immediate not in range 0..%d (%lu)"), | |
8115 | OP_MASK_SA4, (unsigned long) imm_expr.X_add_number); | |
8116 | imm_expr.X_add_number &= OP_MASK_SA4; | |
8117 | } | |
8118 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_SA4; | |
8119 | imm_expr.X_op = O_absent; | |
8120 | s = expr_end; | |
8121 | continue; | |
8122 | ||
8123 | case '5': /* dsp 8-bit unsigned immediate in bit 16 */ | |
8124 | my_getExpression (&imm_expr, s); | |
8125 | check_absolute_expr (ip, &imm_expr); | |
8126 | if (imm_expr.X_add_number & ~OP_MASK_IMM8) | |
8127 | { | |
8128 | as_warn (_("DSP immediate not in range 0..%d (%lu)"), | |
8129 | OP_MASK_IMM8, (unsigned long) imm_expr.X_add_number); | |
8130 | imm_expr.X_add_number &= OP_MASK_IMM8; | |
8131 | } | |
8132 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_IMM8; | |
8133 | imm_expr.X_op = O_absent; | |
8134 | s = expr_end; | |
8135 | continue; | |
8136 | ||
8137 | case '6': /* dsp 5-bit unsigned immediate in bit 21 */ | |
8138 | my_getExpression (&imm_expr, s); | |
8139 | check_absolute_expr (ip, &imm_expr); | |
8140 | if (imm_expr.X_add_number & ~OP_MASK_RS) | |
8141 | { | |
8142 | as_warn (_("DSP immediate not in range 0..%d (%lu)"), | |
8143 | OP_MASK_RS, (unsigned long) imm_expr.X_add_number); | |
8144 | imm_expr.X_add_number &= OP_MASK_RS; | |
8145 | } | |
8146 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_RS; | |
8147 | imm_expr.X_op = O_absent; | |
8148 | s = expr_end; | |
8149 | continue; | |
8150 | ||
8151 | case '7': /* four dsp accumulators in bits 11,12 */ | |
8152 | if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' && | |
8153 | s[3] >= '0' && s[3] <= '3') | |
8154 | { | |
8155 | regno = s[3] - '0'; | |
8156 | s += 4; | |
8157 | ip->insn_opcode |= regno << OP_SH_DSPACC; | |
8158 | continue; | |
8159 | } | |
8160 | else | |
8161 | as_bad (_("Invalid dsp acc register")); | |
8162 | break; | |
8163 | ||
8164 | case '8': /* dsp 6-bit unsigned immediate in bit 11 */ | |
8165 | my_getExpression (&imm_expr, s); | |
8166 | check_absolute_expr (ip, &imm_expr); | |
8167 | if (imm_expr.X_add_number & ~OP_MASK_WRDSP) | |
8168 | { | |
8169 | as_warn (_("DSP immediate not in range 0..%d (%lu)"), | |
8170 | OP_MASK_WRDSP, | |
8171 | (unsigned long) imm_expr.X_add_number); | |
8172 | imm_expr.X_add_number &= OP_MASK_WRDSP; | |
8173 | } | |
8174 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_WRDSP; | |
8175 | imm_expr.X_op = O_absent; | |
8176 | s = expr_end; | |
8177 | continue; | |
8178 | ||
8179 | case '9': /* four dsp accumulators in bits 21,22 */ | |
8180 | if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' && | |
8181 | s[3] >= '0' && s[3] <= '3') | |
8182 | { | |
8183 | regno = s[3] - '0'; | |
8184 | s += 4; | |
8185 | ip->insn_opcode |= regno << OP_SH_DSPACC_S; | |
8186 | continue; | |
8187 | } | |
8188 | else | |
8189 | as_bad (_("Invalid dsp acc register")); | |
8190 | break; | |
8191 | ||
8192 | case '0': /* dsp 6-bit signed immediate in bit 20 */ | |
8193 | my_getExpression (&imm_expr, s); | |
8194 | check_absolute_expr (ip, &imm_expr); | |
8195 | min_range = -((OP_MASK_DSPSFT + 1) >> 1); | |
8196 | max_range = ((OP_MASK_DSPSFT + 1) >> 1) - 1; | |
8197 | if (imm_expr.X_add_number < min_range || | |
8198 | imm_expr.X_add_number > max_range) | |
8199 | { | |
8200 | as_warn (_("DSP immediate not in range %ld..%ld (%ld)"), | |
8201 | (long) min_range, (long) max_range, | |
8202 | (long) imm_expr.X_add_number); | |
8203 | } | |
8204 | imm_expr.X_add_number &= OP_MASK_DSPSFT; | |
8205 | ip->insn_opcode |= ((unsigned long) imm_expr.X_add_number | |
8206 | << OP_SH_DSPSFT); | |
8207 | imm_expr.X_op = O_absent; | |
8208 | s = expr_end; | |
8209 | continue; | |
8210 | ||
8211 | case '\'': /* dsp 6-bit unsigned immediate in bit 16 */ | |
8212 | my_getExpression (&imm_expr, s); | |
8213 | check_absolute_expr (ip, &imm_expr); | |
8214 | if (imm_expr.X_add_number & ~OP_MASK_RDDSP) | |
8215 | { | |
8216 | as_warn (_("DSP immediate not in range 0..%d (%lu)"), | |
8217 | OP_MASK_RDDSP, | |
8218 | (unsigned long) imm_expr.X_add_number); | |
8219 | imm_expr.X_add_number &= OP_MASK_RDDSP; | |
8220 | } | |
8221 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_RDDSP; | |
8222 | imm_expr.X_op = O_absent; | |
8223 | s = expr_end; | |
8224 | continue; | |
8225 | ||
8226 | case ':': /* dsp 7-bit signed immediate in bit 19 */ | |
8227 | my_getExpression (&imm_expr, s); | |
8228 | check_absolute_expr (ip, &imm_expr); | |
8229 | min_range = -((OP_MASK_DSPSFT_7 + 1) >> 1); | |
8230 | max_range = ((OP_MASK_DSPSFT_7 + 1) >> 1) - 1; | |
8231 | if (imm_expr.X_add_number < min_range || | |
8232 | imm_expr.X_add_number > max_range) | |
8233 | { | |
8234 | as_warn (_("DSP immediate not in range %ld..%ld (%ld)"), | |
8235 | (long) min_range, (long) max_range, | |
8236 | (long) imm_expr.X_add_number); | |
8237 | } | |
8238 | imm_expr.X_add_number &= OP_MASK_DSPSFT_7; | |
8239 | ip->insn_opcode |= ((unsigned long) imm_expr.X_add_number | |
8240 | << OP_SH_DSPSFT_7); | |
8241 | imm_expr.X_op = O_absent; | |
8242 | s = expr_end; | |
8243 | continue; | |
8244 | ||
8245 | case '@': /* dsp 10-bit signed immediate in bit 16 */ | |
8246 | my_getExpression (&imm_expr, s); | |
8247 | check_absolute_expr (ip, &imm_expr); | |
8248 | min_range = -((OP_MASK_IMM10 + 1) >> 1); | |
8249 | max_range = ((OP_MASK_IMM10 + 1) >> 1) - 1; | |
8250 | if (imm_expr.X_add_number < min_range || | |
8251 | imm_expr.X_add_number > max_range) | |
8252 | { | |
8253 | as_warn (_("DSP immediate not in range %ld..%ld (%ld)"), | |
8254 | (long) min_range, (long) max_range, | |
8255 | (long) imm_expr.X_add_number); | |
8256 | } | |
8257 | imm_expr.X_add_number &= OP_MASK_IMM10; | |
8258 | ip->insn_opcode |= ((unsigned long) imm_expr.X_add_number | |
8259 | << OP_SH_IMM10); | |
8260 | imm_expr.X_op = O_absent; | |
8261 | s = expr_end; | |
8262 | continue; | |
8263 | ||
ef2e4d86 CF |
8264 | case '!': /* mt 1-bit unsigned immediate in bit 5 */ |
8265 | my_getExpression (&imm_expr, s); | |
8266 | check_absolute_expr (ip, &imm_expr); | |
8267 | if (imm_expr.X_add_number & ~OP_MASK_MT_U) | |
8268 | { | |
8269 | as_warn (_("MT immediate not in range 0..%d (%lu)"), | |
8270 | OP_MASK_MT_U, (unsigned long) imm_expr.X_add_number); | |
8271 | imm_expr.X_add_number &= OP_MASK_MT_U; | |
8272 | } | |
8273 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_MT_U; | |
8274 | imm_expr.X_op = O_absent; | |
8275 | s = expr_end; | |
8276 | continue; | |
8277 | ||
8278 | case '$': /* mt 1-bit unsigned immediate in bit 4 */ | |
8279 | my_getExpression (&imm_expr, s); | |
8280 | check_absolute_expr (ip, &imm_expr); | |
8281 | if (imm_expr.X_add_number & ~OP_MASK_MT_H) | |
8282 | { | |
8283 | as_warn (_("MT immediate not in range 0..%d (%lu)"), | |
8284 | OP_MASK_MT_H, (unsigned long) imm_expr.X_add_number); | |
8285 | imm_expr.X_add_number &= OP_MASK_MT_H; | |
8286 | } | |
8287 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_MT_H; | |
8288 | imm_expr.X_op = O_absent; | |
8289 | s = expr_end; | |
8290 | continue; | |
8291 | ||
8292 | case '*': /* four dsp accumulators in bits 18,19 */ | |
8293 | if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' && | |
8294 | s[3] >= '0' && s[3] <= '3') | |
8295 | { | |
8296 | regno = s[3] - '0'; | |
8297 | s += 4; | |
8298 | ip->insn_opcode |= regno << OP_SH_MTACC_T; | |
8299 | continue; | |
8300 | } | |
8301 | else | |
8302 | as_bad (_("Invalid dsp/smartmips acc register")); | |
8303 | break; | |
8304 | ||
8305 | case '&': /* four dsp accumulators in bits 13,14 */ | |
8306 | if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' && | |
8307 | s[3] >= '0' && s[3] <= '3') | |
8308 | { | |
8309 | regno = s[3] - '0'; | |
8310 | s += 4; | |
8311 | ip->insn_opcode |= regno << OP_SH_MTACC_D; | |
8312 | continue; | |
8313 | } | |
8314 | else | |
8315 | as_bad (_("Invalid dsp/smartmips acc register")); | |
8316 | break; | |
8317 | ||
252b5132 RH |
8318 | case ',': |
8319 | if (*s++ == *args) | |
8320 | continue; | |
8321 | s--; | |
8322 | switch (*++args) | |
8323 | { | |
8324 | case 'r': | |
8325 | case 'v': | |
bf12938e | 8326 | INSERT_OPERAND (RS, *ip, lastregno); |
252b5132 RH |
8327 | continue; |
8328 | ||
8329 | case 'w': | |
bf12938e | 8330 | INSERT_OPERAND (RT, *ip, lastregno); |
38487616 TS |
8331 | continue; |
8332 | ||
252b5132 | 8333 | case 'W': |
bf12938e | 8334 | INSERT_OPERAND (FT, *ip, lastregno); |
252b5132 RH |
8335 | continue; |
8336 | ||
8337 | case 'V': | |
bf12938e | 8338 | INSERT_OPERAND (FS, *ip, lastregno); |
252b5132 RH |
8339 | continue; |
8340 | } | |
8341 | break; | |
8342 | ||
8343 | case '(': | |
8344 | /* Handle optional base register. | |
8345 | Either the base register is omitted or | |
bdaaa2e1 | 8346 | we must have a left paren. */ |
252b5132 RH |
8347 | /* This is dependent on the next operand specifier |
8348 | is a base register specification. */ | |
8349 | assert (args[1] == 'b' || args[1] == '5' | |
8350 | || args[1] == '-' || args[1] == '4'); | |
8351 | if (*s == '\0') | |
8352 | return; | |
8353 | ||
8354 | case ')': /* these must match exactly */ | |
60b63b72 RS |
8355 | case '[': |
8356 | case ']': | |
252b5132 RH |
8357 | if (*s++ == *args) |
8358 | continue; | |
8359 | break; | |
8360 | ||
af7ee8bf CD |
8361 | case '+': /* Opcode extension character. */ |
8362 | switch (*++args) | |
8363 | { | |
9bcd4f99 TS |
8364 | case '1': /* UDI immediates. */ |
8365 | case '2': | |
8366 | case '3': | |
8367 | case '4': | |
8368 | { | |
8369 | const struct mips_immed *imm = mips_immed; | |
8370 | ||
8371 | while (imm->type && imm->type != *args) | |
8372 | ++imm; | |
8373 | if (! imm->type) | |
8374 | internalError (); | |
8375 | my_getExpression (&imm_expr, s); | |
8376 | check_absolute_expr (ip, &imm_expr); | |
8377 | if ((unsigned long) imm_expr.X_add_number & ~imm->mask) | |
8378 | { | |
8379 | as_warn (_("Illegal %s number (%lu, 0x%lx)"), | |
8380 | imm->desc ? imm->desc : ip->insn_mo->name, | |
8381 | (unsigned long) imm_expr.X_add_number, | |
8382 | (unsigned long) imm_expr.X_add_number); | |
8383 | imm_expr.X_add_number &= imm->mask; | |
8384 | } | |
8385 | ip->insn_opcode |= ((unsigned long) imm_expr.X_add_number | |
8386 | << imm->shift); | |
8387 | imm_expr.X_op = O_absent; | |
8388 | s = expr_end; | |
8389 | } | |
8390 | continue; | |
8391 | ||
071742cf CD |
8392 | case 'A': /* ins/ext position, becomes LSB. */ |
8393 | limlo = 0; | |
8394 | limhi = 31; | |
5f74bc13 CD |
8395 | goto do_lsb; |
8396 | case 'E': | |
8397 | limlo = 32; | |
8398 | limhi = 63; | |
8399 | goto do_lsb; | |
8400 | do_lsb: | |
071742cf CD |
8401 | my_getExpression (&imm_expr, s); |
8402 | check_absolute_expr (ip, &imm_expr); | |
8403 | if ((unsigned long) imm_expr.X_add_number < limlo | |
8404 | || (unsigned long) imm_expr.X_add_number > limhi) | |
8405 | { | |
8406 | as_bad (_("Improper position (%lu)"), | |
8407 | (unsigned long) imm_expr.X_add_number); | |
8408 | imm_expr.X_add_number = limlo; | |
8409 | } | |
8410 | lastpos = imm_expr.X_add_number; | |
bf12938e | 8411 | INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number); |
071742cf CD |
8412 | imm_expr.X_op = O_absent; |
8413 | s = expr_end; | |
8414 | continue; | |
8415 | ||
8416 | case 'B': /* ins size, becomes MSB. */ | |
8417 | limlo = 1; | |
8418 | limhi = 32; | |
5f74bc13 CD |
8419 | goto do_msb; |
8420 | case 'F': | |
8421 | limlo = 33; | |
8422 | limhi = 64; | |
8423 | goto do_msb; | |
8424 | do_msb: | |
071742cf CD |
8425 | my_getExpression (&imm_expr, s); |
8426 | check_absolute_expr (ip, &imm_expr); | |
8427 | /* Check for negative input so that small negative numbers | |
8428 | will not succeed incorrectly. The checks against | |
8429 | (pos+size) transitively check "size" itself, | |
8430 | assuming that "pos" is reasonable. */ | |
8431 | if ((long) imm_expr.X_add_number < 0 | |
8432 | || ((unsigned long) imm_expr.X_add_number | |
8433 | + lastpos) < limlo | |
8434 | || ((unsigned long) imm_expr.X_add_number | |
8435 | + lastpos) > limhi) | |
8436 | { | |
8437 | as_bad (_("Improper insert size (%lu, position %lu)"), | |
8438 | (unsigned long) imm_expr.X_add_number, | |
8439 | (unsigned long) lastpos); | |
8440 | imm_expr.X_add_number = limlo - lastpos; | |
8441 | } | |
bf12938e RS |
8442 | INSERT_OPERAND (INSMSB, *ip, |
8443 | lastpos + imm_expr.X_add_number - 1); | |
071742cf CD |
8444 | imm_expr.X_op = O_absent; |
8445 | s = expr_end; | |
8446 | continue; | |
8447 | ||
8448 | case 'C': /* ext size, becomes MSBD. */ | |
8449 | limlo = 1; | |
8450 | limhi = 32; | |
5f74bc13 CD |
8451 | goto do_msbd; |
8452 | case 'G': | |
8453 | limlo = 33; | |
8454 | limhi = 64; | |
8455 | goto do_msbd; | |
8456 | case 'H': | |
8457 | limlo = 33; | |
8458 | limhi = 64; | |
8459 | goto do_msbd; | |
8460 | do_msbd: | |
071742cf CD |
8461 | my_getExpression (&imm_expr, s); |
8462 | check_absolute_expr (ip, &imm_expr); | |
8463 | /* Check for negative input so that small negative numbers | |
8464 | will not succeed incorrectly. The checks against | |
8465 | (pos+size) transitively check "size" itself, | |
8466 | assuming that "pos" is reasonable. */ | |
8467 | if ((long) imm_expr.X_add_number < 0 | |
8468 | || ((unsigned long) imm_expr.X_add_number | |
8469 | + lastpos) < limlo | |
8470 | || ((unsigned long) imm_expr.X_add_number | |
8471 | + lastpos) > limhi) | |
8472 | { | |
8473 | as_bad (_("Improper extract size (%lu, position %lu)"), | |
8474 | (unsigned long) imm_expr.X_add_number, | |
8475 | (unsigned long) lastpos); | |
8476 | imm_expr.X_add_number = limlo - lastpos; | |
8477 | } | |
bf12938e | 8478 | INSERT_OPERAND (EXTMSBD, *ip, imm_expr.X_add_number - 1); |
071742cf CD |
8479 | imm_expr.X_op = O_absent; |
8480 | s = expr_end; | |
8481 | continue; | |
af7ee8bf | 8482 | |
bbcc0807 CD |
8483 | case 'D': |
8484 | /* +D is for disassembly only; never match. */ | |
8485 | break; | |
8486 | ||
5f74bc13 CD |
8487 | case 'I': |
8488 | /* "+I" is like "I", except that imm2_expr is used. */ | |
8489 | my_getExpression (&imm2_expr, s); | |
8490 | if (imm2_expr.X_op != O_big | |
8491 | && imm2_expr.X_op != O_constant) | |
8492 | insn_error = _("absolute expression required"); | |
9ee2a2d4 MR |
8493 | if (HAVE_32BIT_GPRS) |
8494 | normalize_constant_expr (&imm2_expr); | |
5f74bc13 CD |
8495 | s = expr_end; |
8496 | continue; | |
8497 | ||
ef2e4d86 CF |
8498 | case 'T': /* Coprocessor register */ |
8499 | /* +T is for disassembly only; never match. */ | |
8500 | break; | |
8501 | ||
8502 | case 't': /* Coprocessor register number */ | |
8503 | if (s[0] == '$' && ISDIGIT (s[1])) | |
8504 | { | |
8505 | ++s; | |
8506 | regno = 0; | |
8507 | do | |
8508 | { | |
8509 | regno *= 10; | |
8510 | regno += *s - '0'; | |
8511 | ++s; | |
8512 | } | |
8513 | while (ISDIGIT (*s)); | |
8514 | if (regno > 31) | |
8515 | as_bad (_("Invalid register number (%d)"), regno); | |
8516 | else | |
8517 | { | |
8518 | ip->insn_opcode |= regno << OP_SH_RT; | |
8519 | continue; | |
8520 | } | |
8521 | } | |
8522 | else | |
8523 | as_bad (_("Invalid coprocessor 0 register number")); | |
8524 | break; | |
8525 | ||
af7ee8bf CD |
8526 | default: |
8527 | as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"), | |
8528 | *args, insn->name, insn->args); | |
8529 | /* Further processing is fruitless. */ | |
8530 | return; | |
8531 | } | |
8532 | break; | |
8533 | ||
252b5132 RH |
8534 | case '<': /* must be at least one digit */ |
8535 | /* | |
8536 | * According to the manual, if the shift amount is greater | |
b6ff326e KH |
8537 | * than 31 or less than 0, then the shift amount should be |
8538 | * mod 32. In reality the mips assembler issues an error. | |
252b5132 RH |
8539 | * We issue a warning and mask out all but the low 5 bits. |
8540 | */ | |
8541 | my_getExpression (&imm_expr, s); | |
8542 | check_absolute_expr (ip, &imm_expr); | |
8543 | if ((unsigned long) imm_expr.X_add_number > 31) | |
bf12938e RS |
8544 | as_warn (_("Improper shift amount (%lu)"), |
8545 | (unsigned long) imm_expr.X_add_number); | |
8546 | INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number); | |
252b5132 RH |
8547 | imm_expr.X_op = O_absent; |
8548 | s = expr_end; | |
8549 | continue; | |
8550 | ||
8551 | case '>': /* shift amount minus 32 */ | |
8552 | my_getExpression (&imm_expr, s); | |
8553 | check_absolute_expr (ip, &imm_expr); | |
8554 | if ((unsigned long) imm_expr.X_add_number < 32 | |
8555 | || (unsigned long) imm_expr.X_add_number > 63) | |
8556 | break; | |
bf12938e | 8557 | INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number - 32); |
252b5132 RH |
8558 | imm_expr.X_op = O_absent; |
8559 | s = expr_end; | |
8560 | continue; | |
8561 | ||
252b5132 RH |
8562 | case 'k': /* cache code */ |
8563 | case 'h': /* prefx code */ | |
8564 | my_getExpression (&imm_expr, s); | |
8565 | check_absolute_expr (ip, &imm_expr); | |
8566 | if ((unsigned long) imm_expr.X_add_number > 31) | |
bf12938e RS |
8567 | as_warn (_("Invalid value for `%s' (%lu)"), |
8568 | ip->insn_mo->name, | |
8569 | (unsigned long) imm_expr.X_add_number); | |
252b5132 | 8570 | if (*args == 'k') |
bf12938e | 8571 | INSERT_OPERAND (CACHE, *ip, imm_expr.X_add_number); |
252b5132 | 8572 | else |
bf12938e | 8573 | INSERT_OPERAND (PREFX, *ip, imm_expr.X_add_number); |
252b5132 RH |
8574 | imm_expr.X_op = O_absent; |
8575 | s = expr_end; | |
8576 | continue; | |
8577 | ||
8578 | case 'c': /* break code */ | |
8579 | my_getExpression (&imm_expr, s); | |
8580 | check_absolute_expr (ip, &imm_expr); | |
793b27f4 | 8581 | if ((unsigned long) imm_expr.X_add_number > 1023) |
bf12938e RS |
8582 | as_warn (_("Illegal break code (%lu)"), |
8583 | (unsigned long) imm_expr.X_add_number); | |
8584 | INSERT_OPERAND (CODE, *ip, imm_expr.X_add_number); | |
252b5132 RH |
8585 | imm_expr.X_op = O_absent; |
8586 | s = expr_end; | |
8587 | continue; | |
8588 | ||
8589 | case 'q': /* lower break code */ | |
8590 | my_getExpression (&imm_expr, s); | |
8591 | check_absolute_expr (ip, &imm_expr); | |
793b27f4 | 8592 | if ((unsigned long) imm_expr.X_add_number > 1023) |
bf12938e RS |
8593 | as_warn (_("Illegal lower break code (%lu)"), |
8594 | (unsigned long) imm_expr.X_add_number); | |
8595 | INSERT_OPERAND (CODE2, *ip, imm_expr.X_add_number); | |
252b5132 RH |
8596 | imm_expr.X_op = O_absent; |
8597 | s = expr_end; | |
8598 | continue; | |
8599 | ||
4372b673 | 8600 | case 'B': /* 20-bit syscall/break code. */ |
156c2f8b | 8601 | my_getExpression (&imm_expr, s); |
156c2f8b | 8602 | check_absolute_expr (ip, &imm_expr); |
793b27f4 TS |
8603 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE20) |
8604 | as_warn (_("Illegal 20-bit code (%lu)"), | |
8605 | (unsigned long) imm_expr.X_add_number); | |
bf12938e | 8606 | INSERT_OPERAND (CODE20, *ip, imm_expr.X_add_number); |
252b5132 RH |
8607 | imm_expr.X_op = O_absent; |
8608 | s = expr_end; | |
8609 | continue; | |
8610 | ||
98d3f06f | 8611 | case 'C': /* Coprocessor code */ |
beae10d5 | 8612 | my_getExpression (&imm_expr, s); |
252b5132 | 8613 | check_absolute_expr (ip, &imm_expr); |
98d3f06f | 8614 | if ((unsigned long) imm_expr.X_add_number >= (1 << 25)) |
252b5132 | 8615 | { |
793b27f4 TS |
8616 | as_warn (_("Coproccesor code > 25 bits (%lu)"), |
8617 | (unsigned long) imm_expr.X_add_number); | |
98d3f06f | 8618 | imm_expr.X_add_number &= ((1 << 25) - 1); |
252b5132 | 8619 | } |
beae10d5 KH |
8620 | ip->insn_opcode |= imm_expr.X_add_number; |
8621 | imm_expr.X_op = O_absent; | |
8622 | s = expr_end; | |
8623 | continue; | |
252b5132 | 8624 | |
4372b673 NC |
8625 | case 'J': /* 19-bit wait code. */ |
8626 | my_getExpression (&imm_expr, s); | |
8627 | check_absolute_expr (ip, &imm_expr); | |
793b27f4 TS |
8628 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE19) |
8629 | as_warn (_("Illegal 19-bit code (%lu)"), | |
8630 | (unsigned long) imm_expr.X_add_number); | |
bf12938e | 8631 | INSERT_OPERAND (CODE19, *ip, imm_expr.X_add_number); |
4372b673 NC |
8632 | imm_expr.X_op = O_absent; |
8633 | s = expr_end; | |
8634 | continue; | |
8635 | ||
252b5132 | 8636 | case 'P': /* Performance register */ |
beae10d5 | 8637 | my_getExpression (&imm_expr, s); |
252b5132 | 8638 | check_absolute_expr (ip, &imm_expr); |
beae10d5 | 8639 | if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1) |
bf12938e RS |
8640 | as_warn (_("Invalid performance register (%lu)"), |
8641 | (unsigned long) imm_expr.X_add_number); | |
8642 | INSERT_OPERAND (PERFREG, *ip, imm_expr.X_add_number); | |
beae10d5 KH |
8643 | imm_expr.X_op = O_absent; |
8644 | s = expr_end; | |
8645 | continue; | |
252b5132 RH |
8646 | |
8647 | case 'b': /* base register */ | |
8648 | case 'd': /* destination register */ | |
8649 | case 's': /* source register */ | |
8650 | case 't': /* target register */ | |
8651 | case 'r': /* both target and source */ | |
8652 | case 'v': /* both dest and source */ | |
8653 | case 'w': /* both dest and target */ | |
8654 | case 'E': /* coprocessor target register */ | |
8655 | case 'G': /* coprocessor destination register */ | |
af7ee8bf | 8656 | case 'K': /* 'rdhwr' destination register */ |
252b5132 RH |
8657 | case 'x': /* ignore register name */ |
8658 | case 'z': /* must be zero register */ | |
4372b673 | 8659 | case 'U': /* destination register (clo/clz). */ |
ef2e4d86 | 8660 | case 'g': /* coprocessor destination register */ |
252b5132 RH |
8661 | s_reset = s; |
8662 | if (s[0] == '$') | |
8663 | { | |
3882b010 | 8664 | if (ISDIGIT (s[1])) |
252b5132 RH |
8665 | { |
8666 | ++s; | |
8667 | regno = 0; | |
8668 | do | |
8669 | { | |
8670 | regno *= 10; | |
8671 | regno += *s - '0'; | |
8672 | ++s; | |
8673 | } | |
3882b010 | 8674 | while (ISDIGIT (*s)); |
252b5132 RH |
8675 | if (regno > 31) |
8676 | as_bad (_("Invalid register number (%d)"), regno); | |
8677 | } | |
af7ee8bf | 8678 | else if (*args == 'E' || *args == 'G' || *args == 'K') |
252b5132 RH |
8679 | goto notreg; |
8680 | else | |
8681 | { | |
76db943d TS |
8682 | if (s[1] == 'r' && s[2] == 'a') |
8683 | { | |
8684 | s += 3; | |
8685 | regno = RA; | |
8686 | } | |
8687 | else if (s[1] == 'f' && s[2] == 'p') | |
252b5132 RH |
8688 | { |
8689 | s += 3; | |
8690 | regno = FP; | |
8691 | } | |
8692 | else if (s[1] == 's' && s[2] == 'p') | |
8693 | { | |
8694 | s += 3; | |
8695 | regno = SP; | |
8696 | } | |
8697 | else if (s[1] == 'g' && s[2] == 'p') | |
8698 | { | |
8699 | s += 3; | |
8700 | regno = GP; | |
8701 | } | |
8702 | else if (s[1] == 'a' && s[2] == 't') | |
8703 | { | |
8704 | s += 3; | |
8705 | regno = AT; | |
8706 | } | |
8707 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '0') | |
8708 | { | |
8709 | s += 4; | |
8710 | regno = KT0; | |
8711 | } | |
8712 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '1') | |
8713 | { | |
8714 | s += 4; | |
8715 | regno = KT1; | |
8716 | } | |
85b51719 TS |
8717 | else if (s[1] == 'z' && s[2] == 'e' && s[3] == 'r' && s[4] == 'o') |
8718 | { | |
8719 | s += 5; | |
8720 | regno = ZERO; | |
8721 | } | |
252b5132 RH |
8722 | else if (itbl_have_entries) |
8723 | { | |
8724 | char *p, *n; | |
d7ba4a77 | 8725 | unsigned long r; |
252b5132 | 8726 | |
d7ba4a77 | 8727 | p = s + 1; /* advance past '$' */ |
252b5132 RH |
8728 | n = itbl_get_field (&p); /* n is name */ |
8729 | ||
d7ba4a77 ILT |
8730 | /* See if this is a register defined in an |
8731 | itbl entry. */ | |
8732 | if (itbl_get_reg_val (n, &r)) | |
252b5132 RH |
8733 | { |
8734 | /* Get_field advances to the start of | |
8735 | the next field, so we need to back | |
d7ba4a77 | 8736 | rack to the end of the last field. */ |
bdaaa2e1 | 8737 | if (p) |
252b5132 | 8738 | s = p - 1; |
bdaaa2e1 | 8739 | else |
d7ba4a77 | 8740 | s = strchr (s, '\0'); |
252b5132 RH |
8741 | regno = r; |
8742 | } | |
8743 | else | |
8744 | goto notreg; | |
beae10d5 | 8745 | } |
252b5132 RH |
8746 | else |
8747 | goto notreg; | |
8748 | } | |
8749 | if (regno == AT | |
8750 | && ! mips_opts.noat | |
8751 | && *args != 'E' | |
af7ee8bf CD |
8752 | && *args != 'G' |
8753 | && *args != 'K') | |
252b5132 RH |
8754 | as_warn (_("Used $at without \".set noat\"")); |
8755 | c = *args; | |
8756 | if (*s == ' ') | |
f9419b05 | 8757 | ++s; |
252b5132 RH |
8758 | if (args[1] != *s) |
8759 | { | |
8760 | if (c == 'r' || c == 'v' || c == 'w') | |
8761 | { | |
8762 | regno = lastregno; | |
8763 | s = s_reset; | |
f9419b05 | 8764 | ++args; |
252b5132 RH |
8765 | } |
8766 | } | |
8767 | /* 'z' only matches $0. */ | |
8768 | if (c == 'z' && regno != 0) | |
8769 | break; | |
8770 | ||
bdaaa2e1 KH |
8771 | /* Now that we have assembled one operand, we use the args string |
8772 | * to figure out where it goes in the instruction. */ | |
252b5132 RH |
8773 | switch (c) |
8774 | { | |
8775 | case 'r': | |
8776 | case 's': | |
8777 | case 'v': | |
8778 | case 'b': | |
bf12938e | 8779 | INSERT_OPERAND (RS, *ip, regno); |
252b5132 RH |
8780 | break; |
8781 | case 'd': | |
8782 | case 'G': | |
af7ee8bf | 8783 | case 'K': |
ef2e4d86 | 8784 | case 'g': |
bf12938e | 8785 | INSERT_OPERAND (RD, *ip, regno); |
252b5132 | 8786 | break; |
4372b673 | 8787 | case 'U': |
bf12938e RS |
8788 | INSERT_OPERAND (RD, *ip, regno); |
8789 | INSERT_OPERAND (RT, *ip, regno); | |
4372b673 | 8790 | break; |
252b5132 RH |
8791 | case 'w': |
8792 | case 't': | |
8793 | case 'E': | |
bf12938e | 8794 | INSERT_OPERAND (RT, *ip, regno); |
252b5132 RH |
8795 | break; |
8796 | case 'x': | |
8797 | /* This case exists because on the r3000 trunc | |
8798 | expands into a macro which requires a gp | |
8799 | register. On the r6000 or r4000 it is | |
8800 | assembled into a single instruction which | |
8801 | ignores the register. Thus the insn version | |
8802 | is MIPS_ISA2 and uses 'x', and the macro | |
8803 | version is MIPS_ISA1 and uses 't'. */ | |
8804 | break; | |
8805 | case 'z': | |
8806 | /* This case is for the div instruction, which | |
8807 | acts differently if the destination argument | |
8808 | is $0. This only matches $0, and is checked | |
8809 | outside the switch. */ | |
8810 | break; | |
8811 | case 'D': | |
8812 | /* Itbl operand; not yet implemented. FIXME ?? */ | |
8813 | break; | |
8814 | /* What about all other operands like 'i', which | |
8815 | can be specified in the opcode table? */ | |
8816 | } | |
8817 | lastregno = regno; | |
8818 | continue; | |
8819 | } | |
8820 | notreg: | |
8821 | switch (*args++) | |
8822 | { | |
8823 | case 'r': | |
8824 | case 'v': | |
bf12938e | 8825 | INSERT_OPERAND (RS, *ip, lastregno); |
252b5132 RH |
8826 | continue; |
8827 | case 'w': | |
bf12938e | 8828 | INSERT_OPERAND (RT, *ip, lastregno); |
252b5132 RH |
8829 | continue; |
8830 | } | |
8831 | break; | |
8832 | ||
deec1734 CD |
8833 | case 'O': /* MDMX alignment immediate constant. */ |
8834 | my_getExpression (&imm_expr, s); | |
8835 | check_absolute_expr (ip, &imm_expr); | |
8836 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_ALN) | |
bf12938e RS |
8837 | as_warn ("Improper align amount (%ld), using low bits", |
8838 | (long) imm_expr.X_add_number); | |
8839 | INSERT_OPERAND (ALN, *ip, imm_expr.X_add_number); | |
deec1734 CD |
8840 | imm_expr.X_op = O_absent; |
8841 | s = expr_end; | |
8842 | continue; | |
8843 | ||
8844 | case 'Q': /* MDMX vector, element sel, or const. */ | |
8845 | if (s[0] != '$') | |
8846 | { | |
8847 | /* MDMX Immediate. */ | |
8848 | my_getExpression (&imm_expr, s); | |
8849 | check_absolute_expr (ip, &imm_expr); | |
8850 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_FT) | |
bf12938e RS |
8851 | as_warn (_("Invalid MDMX Immediate (%ld)"), |
8852 | (long) imm_expr.X_add_number); | |
8853 | INSERT_OPERAND (FT, *ip, imm_expr.X_add_number); | |
deec1734 CD |
8854 | if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL)) |
8855 | ip->insn_opcode |= MDMX_FMTSEL_IMM_QH << OP_SH_VSEL; | |
8856 | else | |
8857 | ip->insn_opcode |= MDMX_FMTSEL_IMM_OB << OP_SH_VSEL; | |
deec1734 CD |
8858 | imm_expr.X_op = O_absent; |
8859 | s = expr_end; | |
8860 | continue; | |
8861 | } | |
8862 | /* Not MDMX Immediate. Fall through. */ | |
8863 | case 'X': /* MDMX destination register. */ | |
8864 | case 'Y': /* MDMX source register. */ | |
8865 | case 'Z': /* MDMX target register. */ | |
8866 | is_mdmx = 1; | |
252b5132 RH |
8867 | case 'D': /* floating point destination register */ |
8868 | case 'S': /* floating point source register */ | |
8869 | case 'T': /* floating point target register */ | |
8870 | case 'R': /* floating point source register */ | |
8871 | case 'V': | |
8872 | case 'W': | |
8873 | s_reset = s; | |
deec1734 CD |
8874 | /* Accept $fN for FP and MDMX register numbers, and in |
8875 | addition accept $vN for MDMX register numbers. */ | |
8876 | if ((s[0] == '$' && s[1] == 'f' && ISDIGIT (s[2])) | |
8877 | || (is_mdmx != 0 && s[0] == '$' && s[1] == 'v' | |
8878 | && ISDIGIT (s[2]))) | |
252b5132 RH |
8879 | { |
8880 | s += 2; | |
8881 | regno = 0; | |
8882 | do | |
8883 | { | |
8884 | regno *= 10; | |
8885 | regno += *s - '0'; | |
8886 | ++s; | |
8887 | } | |
3882b010 | 8888 | while (ISDIGIT (*s)); |
252b5132 RH |
8889 | |
8890 | if (regno > 31) | |
8891 | as_bad (_("Invalid float register number (%d)"), regno); | |
8892 | ||
8893 | if ((regno & 1) != 0 | |
ca4e0257 | 8894 | && HAVE_32BIT_FPRS |
252b5132 RH |
8895 | && ! (strcmp (str, "mtc1") == 0 |
8896 | || strcmp (str, "mfc1") == 0 | |
8897 | || strcmp (str, "lwc1") == 0 | |
8898 | || strcmp (str, "swc1") == 0 | |
8899 | || strcmp (str, "l.s") == 0 | |
ef2e4d86 CF |
8900 | || strcmp (str, "s.s") == 0 |
8901 | || strcmp (str, "mftc1") == 0 | |
8902 | || strcmp (str, "mfthc1") == 0 | |
8903 | || strcmp (str, "cftc1") == 0 | |
8904 | || strcmp (str, "mttc1") == 0 | |
8905 | || strcmp (str, "mtthc1") == 0 | |
8906 | || strcmp (str, "cttc1") == 0)) | |
252b5132 RH |
8907 | as_warn (_("Float register should be even, was %d"), |
8908 | regno); | |
8909 | ||
8910 | c = *args; | |
8911 | if (*s == ' ') | |
f9419b05 | 8912 | ++s; |
252b5132 RH |
8913 | if (args[1] != *s) |
8914 | { | |
8915 | if (c == 'V' || c == 'W') | |
8916 | { | |
8917 | regno = lastregno; | |
8918 | s = s_reset; | |
f9419b05 | 8919 | ++args; |
252b5132 RH |
8920 | } |
8921 | } | |
8922 | switch (c) | |
8923 | { | |
8924 | case 'D': | |
deec1734 | 8925 | case 'X': |
bf12938e | 8926 | INSERT_OPERAND (FD, *ip, regno); |
252b5132 RH |
8927 | break; |
8928 | case 'V': | |
8929 | case 'S': | |
deec1734 | 8930 | case 'Y': |
bf12938e | 8931 | INSERT_OPERAND (FS, *ip, regno); |
252b5132 | 8932 | break; |
deec1734 CD |
8933 | case 'Q': |
8934 | /* This is like 'Z', but also needs to fix the MDMX | |
8935 | vector/scalar select bits. Note that the | |
8936 | scalar immediate case is handled above. */ | |
8937 | if (*s == '[') | |
8938 | { | |
8939 | int is_qh = (ip->insn_opcode & (1 << OP_SH_VSEL)); | |
8940 | int max_el = (is_qh ? 3 : 7); | |
8941 | s++; | |
8942 | my_getExpression(&imm_expr, s); | |
8943 | check_absolute_expr (ip, &imm_expr); | |
8944 | s = expr_end; | |
8945 | if (imm_expr.X_add_number > max_el) | |
8946 | as_bad(_("Bad element selector %ld"), | |
8947 | (long) imm_expr.X_add_number); | |
8948 | imm_expr.X_add_number &= max_el; | |
8949 | ip->insn_opcode |= (imm_expr.X_add_number | |
8950 | << (OP_SH_VSEL + | |
8951 | (is_qh ? 2 : 1))); | |
01a3f561 | 8952 | imm_expr.X_op = O_absent; |
deec1734 CD |
8953 | if (*s != ']') |
8954 | as_warn(_("Expecting ']' found '%s'"), s); | |
8955 | else | |
8956 | s++; | |
8957 | } | |
8958 | else | |
8959 | { | |
8960 | if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL)) | |
8961 | ip->insn_opcode |= (MDMX_FMTSEL_VEC_QH | |
8962 | << OP_SH_VSEL); | |
8963 | else | |
8964 | ip->insn_opcode |= (MDMX_FMTSEL_VEC_OB << | |
8965 | OP_SH_VSEL); | |
8966 | } | |
8967 | /* Fall through */ | |
252b5132 RH |
8968 | case 'W': |
8969 | case 'T': | |
deec1734 | 8970 | case 'Z': |
bf12938e | 8971 | INSERT_OPERAND (FT, *ip, regno); |
252b5132 RH |
8972 | break; |
8973 | case 'R': | |
bf12938e | 8974 | INSERT_OPERAND (FR, *ip, regno); |
252b5132 RH |
8975 | break; |
8976 | } | |
8977 | lastregno = regno; | |
8978 | continue; | |
8979 | } | |
8980 | ||
252b5132 RH |
8981 | switch (*args++) |
8982 | { | |
8983 | case 'V': | |
bf12938e | 8984 | INSERT_OPERAND (FS, *ip, lastregno); |
252b5132 RH |
8985 | continue; |
8986 | case 'W': | |
bf12938e | 8987 | INSERT_OPERAND (FT, *ip, lastregno); |
252b5132 RH |
8988 | continue; |
8989 | } | |
8990 | break; | |
8991 | ||
8992 | case 'I': | |
8993 | my_getExpression (&imm_expr, s); | |
8994 | if (imm_expr.X_op != O_big | |
8995 | && imm_expr.X_op != O_constant) | |
8996 | insn_error = _("absolute expression required"); | |
9ee2a2d4 MR |
8997 | if (HAVE_32BIT_GPRS) |
8998 | normalize_constant_expr (&imm_expr); | |
252b5132 RH |
8999 | s = expr_end; |
9000 | continue; | |
9001 | ||
9002 | case 'A': | |
9003 | my_getExpression (&offset_expr, s); | |
2051e8c4 | 9004 | normalize_address_expr (&offset_expr); |
f6688943 | 9005 | *imm_reloc = BFD_RELOC_32; |
252b5132 RH |
9006 | s = expr_end; |
9007 | continue; | |
9008 | ||
9009 | case 'F': | |
9010 | case 'L': | |
9011 | case 'f': | |
9012 | case 'l': | |
9013 | { | |
9014 | int f64; | |
ca4e0257 | 9015 | int using_gprs; |
252b5132 RH |
9016 | char *save_in; |
9017 | char *err; | |
9018 | unsigned char temp[8]; | |
9019 | int len; | |
9020 | unsigned int length; | |
9021 | segT seg; | |
9022 | subsegT subseg; | |
9023 | char *p; | |
9024 | ||
9025 | /* These only appear as the last operand in an | |
9026 | instruction, and every instruction that accepts | |
9027 | them in any variant accepts them in all variants. | |
9028 | This means we don't have to worry about backing out | |
9029 | any changes if the instruction does not match. | |
9030 | ||
9031 | The difference between them is the size of the | |
9032 | floating point constant and where it goes. For 'F' | |
9033 | and 'L' the constant is 64 bits; for 'f' and 'l' it | |
9034 | is 32 bits. Where the constant is placed is based | |
9035 | on how the MIPS assembler does things: | |
9036 | F -- .rdata | |
9037 | L -- .lit8 | |
9038 | f -- immediate value | |
9039 | l -- .lit4 | |
9040 | ||
9041 | The .lit4 and .lit8 sections are only used if | |
9042 | permitted by the -G argument. | |
9043 | ||
ca4e0257 RS |
9044 | The code below needs to know whether the target register |
9045 | is 32 or 64 bits wide. It relies on the fact 'f' and | |
9046 | 'F' are used with GPR-based instructions and 'l' and | |
9047 | 'L' are used with FPR-based instructions. */ | |
252b5132 RH |
9048 | |
9049 | f64 = *args == 'F' || *args == 'L'; | |
ca4e0257 | 9050 | using_gprs = *args == 'F' || *args == 'f'; |
252b5132 RH |
9051 | |
9052 | save_in = input_line_pointer; | |
9053 | input_line_pointer = s; | |
9054 | err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len); | |
9055 | length = len; | |
9056 | s = input_line_pointer; | |
9057 | input_line_pointer = save_in; | |
9058 | if (err != NULL && *err != '\0') | |
9059 | { | |
9060 | as_bad (_("Bad floating point constant: %s"), err); | |
9061 | memset (temp, '\0', sizeof temp); | |
9062 | length = f64 ? 8 : 4; | |
9063 | } | |
9064 | ||
156c2f8b | 9065 | assert (length == (unsigned) (f64 ? 8 : 4)); |
252b5132 RH |
9066 | |
9067 | if (*args == 'f' | |
9068 | || (*args == 'l' | |
3e722fb5 | 9069 | && (g_switch_value < 4 |
252b5132 RH |
9070 | || (temp[0] == 0 && temp[1] == 0) |
9071 | || (temp[2] == 0 && temp[3] == 0)))) | |
9072 | { | |
9073 | imm_expr.X_op = O_constant; | |
9074 | if (! target_big_endian) | |
9075 | imm_expr.X_add_number = bfd_getl32 (temp); | |
9076 | else | |
9077 | imm_expr.X_add_number = bfd_getb32 (temp); | |
9078 | } | |
9079 | else if (length > 4 | |
119d663a | 9080 | && ! mips_disable_float_construction |
ca4e0257 RS |
9081 | /* Constants can only be constructed in GPRs and |
9082 | copied to FPRs if the GPRs are at least as wide | |
9083 | as the FPRs. Force the constant into memory if | |
9084 | we are using 64-bit FPRs but the GPRs are only | |
9085 | 32 bits wide. */ | |
9086 | && (using_gprs | |
9087 | || ! (HAVE_64BIT_FPRS && HAVE_32BIT_GPRS)) | |
252b5132 RH |
9088 | && ((temp[0] == 0 && temp[1] == 0) |
9089 | || (temp[2] == 0 && temp[3] == 0)) | |
9090 | && ((temp[4] == 0 && temp[5] == 0) | |
9091 | || (temp[6] == 0 && temp[7] == 0))) | |
9092 | { | |
ca4e0257 RS |
9093 | /* The value is simple enough to load with a couple of |
9094 | instructions. If using 32-bit registers, set | |
9095 | imm_expr to the high order 32 bits and offset_expr to | |
9096 | the low order 32 bits. Otherwise, set imm_expr to | |
9097 | the entire 64 bit constant. */ | |
9098 | if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS) | |
252b5132 RH |
9099 | { |
9100 | imm_expr.X_op = O_constant; | |
9101 | offset_expr.X_op = O_constant; | |
9102 | if (! target_big_endian) | |
9103 | { | |
9104 | imm_expr.X_add_number = bfd_getl32 (temp + 4); | |
9105 | offset_expr.X_add_number = bfd_getl32 (temp); | |
9106 | } | |
9107 | else | |
9108 | { | |
9109 | imm_expr.X_add_number = bfd_getb32 (temp); | |
9110 | offset_expr.X_add_number = bfd_getb32 (temp + 4); | |
9111 | } | |
9112 | if (offset_expr.X_add_number == 0) | |
9113 | offset_expr.X_op = O_absent; | |
9114 | } | |
9115 | else if (sizeof (imm_expr.X_add_number) > 4) | |
9116 | { | |
9117 | imm_expr.X_op = O_constant; | |
9118 | if (! target_big_endian) | |
9119 | imm_expr.X_add_number = bfd_getl64 (temp); | |
9120 | else | |
9121 | imm_expr.X_add_number = bfd_getb64 (temp); | |
9122 | } | |
9123 | else | |
9124 | { | |
9125 | imm_expr.X_op = O_big; | |
9126 | imm_expr.X_add_number = 4; | |
9127 | if (! target_big_endian) | |
9128 | { | |
9129 | generic_bignum[0] = bfd_getl16 (temp); | |
9130 | generic_bignum[1] = bfd_getl16 (temp + 2); | |
9131 | generic_bignum[2] = bfd_getl16 (temp + 4); | |
9132 | generic_bignum[3] = bfd_getl16 (temp + 6); | |
9133 | } | |
9134 | else | |
9135 | { | |
9136 | generic_bignum[0] = bfd_getb16 (temp + 6); | |
9137 | generic_bignum[1] = bfd_getb16 (temp + 4); | |
9138 | generic_bignum[2] = bfd_getb16 (temp + 2); | |
9139 | generic_bignum[3] = bfd_getb16 (temp); | |
9140 | } | |
9141 | } | |
9142 | } | |
9143 | else | |
9144 | { | |
9145 | const char *newname; | |
9146 | segT new_seg; | |
9147 | ||
9148 | /* Switch to the right section. */ | |
9149 | seg = now_seg; | |
9150 | subseg = now_subseg; | |
9151 | switch (*args) | |
9152 | { | |
9153 | default: /* unused default case avoids warnings. */ | |
9154 | case 'L': | |
9155 | newname = RDATA_SECTION_NAME; | |
3e722fb5 | 9156 | if (g_switch_value >= 8) |
252b5132 RH |
9157 | newname = ".lit8"; |
9158 | break; | |
9159 | case 'F': | |
3e722fb5 | 9160 | newname = RDATA_SECTION_NAME; |
252b5132 RH |
9161 | break; |
9162 | case 'l': | |
4d0d148d | 9163 | assert (g_switch_value >= 4); |
252b5132 RH |
9164 | newname = ".lit4"; |
9165 | break; | |
9166 | } | |
9167 | new_seg = subseg_new (newname, (subsegT) 0); | |
9168 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
9169 | bfd_set_section_flags (stdoutput, new_seg, | |
9170 | (SEC_ALLOC | |
9171 | | SEC_LOAD | |
9172 | | SEC_READONLY | |
9173 | | SEC_DATA)); | |
9174 | frag_align (*args == 'l' ? 2 : 3, 0, 0); | |
9175 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour | |
9176 | && strcmp (TARGET_OS, "elf") != 0) | |
9177 | record_alignment (new_seg, 4); | |
9178 | else | |
9179 | record_alignment (new_seg, *args == 'l' ? 2 : 3); | |
9180 | if (seg == now_seg) | |
9181 | as_bad (_("Can't use floating point insn in this section")); | |
9182 | ||
9183 | /* Set the argument to the current address in the | |
9184 | section. */ | |
9185 | offset_expr.X_op = O_symbol; | |
9186 | offset_expr.X_add_symbol = | |
9187 | symbol_new ("L0\001", now_seg, | |
9188 | (valueT) frag_now_fix (), frag_now); | |
9189 | offset_expr.X_add_number = 0; | |
9190 | ||
9191 | /* Put the floating point number into the section. */ | |
9192 | p = frag_more ((int) length); | |
9193 | memcpy (p, temp, length); | |
9194 | ||
9195 | /* Switch back to the original section. */ | |
9196 | subseg_set (seg, subseg); | |
9197 | } | |
9198 | } | |
9199 | continue; | |
9200 | ||
9201 | case 'i': /* 16 bit unsigned immediate */ | |
9202 | case 'j': /* 16 bit signed immediate */ | |
f6688943 | 9203 | *imm_reloc = BFD_RELOC_LO16; |
5e0116d5 | 9204 | if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0) |
252b5132 RH |
9205 | { |
9206 | int more; | |
5e0116d5 RS |
9207 | offsetT minval, maxval; |
9208 | ||
9209 | more = (insn + 1 < &mips_opcodes[NUMOPCODES] | |
9210 | && strcmp (insn->name, insn[1].name) == 0); | |
9211 | ||
9212 | /* If the expression was written as an unsigned number, | |
9213 | only treat it as signed if there are no more | |
9214 | alternatives. */ | |
9215 | if (more | |
9216 | && *args == 'j' | |
9217 | && sizeof (imm_expr.X_add_number) <= 4 | |
9218 | && imm_expr.X_op == O_constant | |
9219 | && imm_expr.X_add_number < 0 | |
9220 | && imm_expr.X_unsigned | |
9221 | && HAVE_64BIT_GPRS) | |
9222 | break; | |
9223 | ||
9224 | /* For compatibility with older assemblers, we accept | |
9225 | 0x8000-0xffff as signed 16-bit numbers when only | |
9226 | signed numbers are allowed. */ | |
9227 | if (*args == 'i') | |
9228 | minval = 0, maxval = 0xffff; | |
9229 | else if (more) | |
9230 | minval = -0x8000, maxval = 0x7fff; | |
252b5132 | 9231 | else |
5e0116d5 RS |
9232 | minval = -0x8000, maxval = 0xffff; |
9233 | ||
9234 | if (imm_expr.X_op != O_constant | |
9235 | || imm_expr.X_add_number < minval | |
9236 | || imm_expr.X_add_number > maxval) | |
252b5132 RH |
9237 | { |
9238 | if (more) | |
9239 | break; | |
2ae7e77b AH |
9240 | if (imm_expr.X_op == O_constant |
9241 | || imm_expr.X_op == O_big) | |
5e0116d5 | 9242 | as_bad (_("expression out of range")); |
252b5132 RH |
9243 | } |
9244 | } | |
9245 | s = expr_end; | |
9246 | continue; | |
9247 | ||
9248 | case 'o': /* 16 bit offset */ | |
5e0116d5 RS |
9249 | /* Check whether there is only a single bracketed expression |
9250 | left. If so, it must be the base register and the | |
9251 | constant must be zero. */ | |
9252 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
9253 | { | |
9254 | offset_expr.X_op = O_constant; | |
9255 | offset_expr.X_add_number = 0; | |
9256 | continue; | |
9257 | } | |
252b5132 RH |
9258 | |
9259 | /* If this value won't fit into a 16 bit offset, then go | |
9260 | find a macro that will generate the 32 bit offset | |
afdbd6d0 | 9261 | code pattern. */ |
5e0116d5 | 9262 | if (my_getSmallExpression (&offset_expr, offset_reloc, s) == 0 |
252b5132 RH |
9263 | && (offset_expr.X_op != O_constant |
9264 | || offset_expr.X_add_number >= 0x8000 | |
afdbd6d0 | 9265 | || offset_expr.X_add_number < -0x8000)) |
252b5132 RH |
9266 | break; |
9267 | ||
252b5132 RH |
9268 | s = expr_end; |
9269 | continue; | |
9270 | ||
9271 | case 'p': /* pc relative offset */ | |
0b25d3e6 | 9272 | *offset_reloc = BFD_RELOC_16_PCREL_S2; |
252b5132 RH |
9273 | my_getExpression (&offset_expr, s); |
9274 | s = expr_end; | |
9275 | continue; | |
9276 | ||
9277 | case 'u': /* upper 16 bits */ | |
5e0116d5 RS |
9278 | if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0 |
9279 | && imm_expr.X_op == O_constant | |
9280 | && (imm_expr.X_add_number < 0 | |
9281 | || imm_expr.X_add_number >= 0x10000)) | |
252b5132 RH |
9282 | as_bad (_("lui expression not in range 0..65535")); |
9283 | s = expr_end; | |
9284 | continue; | |
9285 | ||
9286 | case 'a': /* 26 bit address */ | |
9287 | my_getExpression (&offset_expr, s); | |
9288 | s = expr_end; | |
f6688943 | 9289 | *offset_reloc = BFD_RELOC_MIPS_JMP; |
252b5132 RH |
9290 | continue; |
9291 | ||
9292 | case 'N': /* 3 bit branch condition code */ | |
9293 | case 'M': /* 3 bit compare condition code */ | |
9294 | if (strncmp (s, "$fcc", 4) != 0) | |
9295 | break; | |
9296 | s += 4; | |
9297 | regno = 0; | |
9298 | do | |
9299 | { | |
9300 | regno *= 10; | |
9301 | regno += *s - '0'; | |
9302 | ++s; | |
9303 | } | |
3882b010 | 9304 | while (ISDIGIT (*s)); |
252b5132 | 9305 | if (regno > 7) |
30c378fd CD |
9306 | as_bad (_("Invalid condition code register $fcc%d"), regno); |
9307 | if ((strcmp(str + strlen(str) - 3, ".ps") == 0 | |
9308 | || strcmp(str + strlen(str) - 5, "any2f") == 0 | |
9309 | || strcmp(str + strlen(str) - 5, "any2t") == 0) | |
9310 | && (regno & 1) != 0) | |
9311 | as_warn(_("Condition code register should be even for %s, was %d"), | |
9312 | str, regno); | |
9313 | if ((strcmp(str + strlen(str) - 5, "any4f") == 0 | |
9314 | || strcmp(str + strlen(str) - 5, "any4t") == 0) | |
9315 | && (regno & 3) != 0) | |
9316 | as_warn(_("Condition code register should be 0 or 4 for %s, was %d"), | |
9317 | str, regno); | |
252b5132 | 9318 | if (*args == 'N') |
bf12938e | 9319 | INSERT_OPERAND (BCC, *ip, regno); |
252b5132 | 9320 | else |
bf12938e | 9321 | INSERT_OPERAND (CCC, *ip, regno); |
beae10d5 | 9322 | continue; |
252b5132 | 9323 | |
156c2f8b NC |
9324 | case 'H': |
9325 | if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X')) | |
9326 | s += 2; | |
3882b010 | 9327 | if (ISDIGIT (*s)) |
156c2f8b NC |
9328 | { |
9329 | c = 0; | |
9330 | do | |
9331 | { | |
9332 | c *= 10; | |
9333 | c += *s - '0'; | |
9334 | ++s; | |
9335 | } | |
3882b010 | 9336 | while (ISDIGIT (*s)); |
156c2f8b NC |
9337 | } |
9338 | else | |
9339 | c = 8; /* Invalid sel value. */ | |
9340 | ||
9341 | if (c > 7) | |
9342 | as_bad (_("invalid coprocessor sub-selection value (0-7)")); | |
9343 | ip->insn_opcode |= c; | |
9344 | continue; | |
9345 | ||
60b63b72 RS |
9346 | case 'e': |
9347 | /* Must be at least one digit. */ | |
9348 | my_getExpression (&imm_expr, s); | |
9349 | check_absolute_expr (ip, &imm_expr); | |
9350 | ||
9351 | if ((unsigned long) imm_expr.X_add_number | |
9352 | > (unsigned long) OP_MASK_VECBYTE) | |
9353 | { | |
9354 | as_bad (_("bad byte vector index (%ld)"), | |
9355 | (long) imm_expr.X_add_number); | |
9356 | imm_expr.X_add_number = 0; | |
9357 | } | |
9358 | ||
bf12938e | 9359 | INSERT_OPERAND (VECBYTE, *ip, imm_expr.X_add_number); |
60b63b72 RS |
9360 | imm_expr.X_op = O_absent; |
9361 | s = expr_end; | |
9362 | continue; | |
9363 | ||
9364 | case '%': | |
9365 | my_getExpression (&imm_expr, s); | |
9366 | check_absolute_expr (ip, &imm_expr); | |
9367 | ||
9368 | if ((unsigned long) imm_expr.X_add_number | |
9369 | > (unsigned long) OP_MASK_VECALIGN) | |
9370 | { | |
9371 | as_bad (_("bad byte vector index (%ld)"), | |
9372 | (long) imm_expr.X_add_number); | |
9373 | imm_expr.X_add_number = 0; | |
9374 | } | |
9375 | ||
bf12938e | 9376 | INSERT_OPERAND (VECALIGN, *ip, imm_expr.X_add_number); |
60b63b72 RS |
9377 | imm_expr.X_op = O_absent; |
9378 | s = expr_end; | |
9379 | continue; | |
9380 | ||
252b5132 RH |
9381 | default: |
9382 | as_bad (_("bad char = '%c'\n"), *args); | |
9383 | internalError (); | |
9384 | } | |
9385 | break; | |
9386 | } | |
9387 | /* Args don't match. */ | |
9388 | if (insn + 1 < &mips_opcodes[NUMOPCODES] && | |
9389 | !strcmp (insn->name, insn[1].name)) | |
9390 | { | |
9391 | ++insn; | |
9392 | s = argsStart; | |
268f6bed | 9393 | insn_error = _("illegal operands"); |
252b5132 RH |
9394 | continue; |
9395 | } | |
268f6bed L |
9396 | if (save_c) |
9397 | *(--s) = save_c; | |
252b5132 RH |
9398 | insn_error = _("illegal operands"); |
9399 | return; | |
9400 | } | |
9401 | } | |
9402 | ||
0499d65b TS |
9403 | #define SKIP_SPACE_TABS(S) { while (*(S) == ' ' || *(S) == '\t') ++(S); } |
9404 | ||
252b5132 RH |
9405 | /* This routine assembles an instruction into its binary format when |
9406 | assembling for the mips16. As a side effect, it sets one of the | |
9407 | global variables imm_reloc or offset_reloc to the type of | |
9408 | relocation to do if one of the operands is an address expression. | |
9409 | It also sets mips16_small and mips16_ext if the user explicitly | |
9410 | requested a small or extended instruction. */ | |
9411 | ||
9412 | static void | |
17a2f251 | 9413 | mips16_ip (char *str, struct mips_cl_insn *ip) |
252b5132 RH |
9414 | { |
9415 | char *s; | |
9416 | const char *args; | |
9417 | struct mips_opcode *insn; | |
9418 | char *argsstart; | |
9419 | unsigned int regno; | |
9420 | unsigned int lastregno = 0; | |
9421 | char *s_reset; | |
d6f16593 | 9422 | size_t i; |
252b5132 RH |
9423 | |
9424 | insn_error = NULL; | |
9425 | ||
b34976b6 AM |
9426 | mips16_small = FALSE; |
9427 | mips16_ext = FALSE; | |
252b5132 | 9428 | |
3882b010 | 9429 | for (s = str; ISLOWER (*s); ++s) |
252b5132 RH |
9430 | ; |
9431 | switch (*s) | |
9432 | { | |
9433 | case '\0': | |
9434 | break; | |
9435 | ||
9436 | case ' ': | |
9437 | *s++ = '\0'; | |
9438 | break; | |
9439 | ||
9440 | case '.': | |
9441 | if (s[1] == 't' && s[2] == ' ') | |
9442 | { | |
9443 | *s = '\0'; | |
b34976b6 | 9444 | mips16_small = TRUE; |
252b5132 RH |
9445 | s += 3; |
9446 | break; | |
9447 | } | |
9448 | else if (s[1] == 'e' && s[2] == ' ') | |
9449 | { | |
9450 | *s = '\0'; | |
b34976b6 | 9451 | mips16_ext = TRUE; |
252b5132 RH |
9452 | s += 3; |
9453 | break; | |
9454 | } | |
9455 | /* Fall through. */ | |
9456 | default: | |
9457 | insn_error = _("unknown opcode"); | |
9458 | return; | |
9459 | } | |
9460 | ||
9461 | if (mips_opts.noautoextend && ! mips16_ext) | |
b34976b6 | 9462 | mips16_small = TRUE; |
252b5132 RH |
9463 | |
9464 | if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL) | |
9465 | { | |
9466 | insn_error = _("unrecognized opcode"); | |
9467 | return; | |
9468 | } | |
9469 | ||
9470 | argsstart = s; | |
9471 | for (;;) | |
9472 | { | |
9b3f89ee TS |
9473 | bfd_boolean ok; |
9474 | ||
252b5132 RH |
9475 | assert (strcmp (insn->name, str) == 0); |
9476 | ||
9b3f89ee TS |
9477 | if (OPCODE_IS_MEMBER (insn, mips_opts.isa, mips_opts.arch)) |
9478 | ok = TRUE; | |
9479 | else | |
9480 | ok = FALSE; | |
9481 | ||
9482 | if (! ok) | |
9483 | { | |
9484 | if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] | |
9485 | && strcmp (insn->name, insn[1].name) == 0) | |
9486 | { | |
9487 | ++insn; | |
9488 | continue; | |
9489 | } | |
9490 | else | |
9491 | { | |
9492 | if (!insn_error) | |
9493 | { | |
9494 | static char buf[100]; | |
9495 | sprintf (buf, | |
9496 | _("opcode not supported on this processor: %s (%s)"), | |
9497 | mips_cpu_info_from_arch (mips_opts.arch)->name, | |
9498 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
9499 | insn_error = buf; | |
9500 | } | |
9501 | return; | |
9502 | } | |
9503 | } | |
9504 | ||
1e915849 | 9505 | create_insn (ip, insn); |
252b5132 | 9506 | imm_expr.X_op = O_absent; |
f6688943 TS |
9507 | imm_reloc[0] = BFD_RELOC_UNUSED; |
9508 | imm_reloc[1] = BFD_RELOC_UNUSED; | |
9509 | imm_reloc[2] = BFD_RELOC_UNUSED; | |
5f74bc13 | 9510 | imm2_expr.X_op = O_absent; |
252b5132 | 9511 | offset_expr.X_op = O_absent; |
f6688943 TS |
9512 | offset_reloc[0] = BFD_RELOC_UNUSED; |
9513 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
9514 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
9515 | for (args = insn->args; 1; ++args) |
9516 | { | |
9517 | int c; | |
9518 | ||
9519 | if (*s == ' ') | |
9520 | ++s; | |
9521 | ||
9522 | /* In this switch statement we call break if we did not find | |
9523 | a match, continue if we did find a match, or return if we | |
9524 | are done. */ | |
9525 | ||
9526 | c = *args; | |
9527 | switch (c) | |
9528 | { | |
9529 | case '\0': | |
9530 | if (*s == '\0') | |
9531 | { | |
9532 | /* Stuff the immediate value in now, if we can. */ | |
9533 | if (imm_expr.X_op == O_constant | |
f6688943 | 9534 | && *imm_reloc > BFD_RELOC_UNUSED |
252b5132 RH |
9535 | && insn->pinfo != INSN_MACRO) |
9536 | { | |
d6f16593 MR |
9537 | valueT tmp; |
9538 | ||
9539 | switch (*offset_reloc) | |
9540 | { | |
9541 | case BFD_RELOC_MIPS16_HI16_S: | |
9542 | tmp = (imm_expr.X_add_number + 0x8000) >> 16; | |
9543 | break; | |
9544 | ||
9545 | case BFD_RELOC_MIPS16_HI16: | |
9546 | tmp = imm_expr.X_add_number >> 16; | |
9547 | break; | |
9548 | ||
9549 | case BFD_RELOC_MIPS16_LO16: | |
9550 | tmp = ((imm_expr.X_add_number + 0x8000) & 0xffff) | |
9551 | - 0x8000; | |
9552 | break; | |
9553 | ||
9554 | case BFD_RELOC_UNUSED: | |
9555 | tmp = imm_expr.X_add_number; | |
9556 | break; | |
9557 | ||
9558 | default: | |
9559 | internalError (); | |
9560 | } | |
9561 | *offset_reloc = BFD_RELOC_UNUSED; | |
9562 | ||
c4e7957c | 9563 | mips16_immed (NULL, 0, *imm_reloc - BFD_RELOC_UNUSED, |
d6f16593 | 9564 | tmp, TRUE, mips16_small, |
252b5132 RH |
9565 | mips16_ext, &ip->insn_opcode, |
9566 | &ip->use_extend, &ip->extend); | |
9567 | imm_expr.X_op = O_absent; | |
f6688943 | 9568 | *imm_reloc = BFD_RELOC_UNUSED; |
252b5132 RH |
9569 | } |
9570 | ||
9571 | return; | |
9572 | } | |
9573 | break; | |
9574 | ||
9575 | case ',': | |
9576 | if (*s++ == c) | |
9577 | continue; | |
9578 | s--; | |
9579 | switch (*++args) | |
9580 | { | |
9581 | case 'v': | |
bf12938e | 9582 | MIPS16_INSERT_OPERAND (RX, *ip, lastregno); |
252b5132 RH |
9583 | continue; |
9584 | case 'w': | |
bf12938e | 9585 | MIPS16_INSERT_OPERAND (RY, *ip, lastregno); |
252b5132 RH |
9586 | continue; |
9587 | } | |
9588 | break; | |
9589 | ||
9590 | case '(': | |
9591 | case ')': | |
9592 | if (*s++ == c) | |
9593 | continue; | |
9594 | break; | |
9595 | ||
9596 | case 'v': | |
9597 | case 'w': | |
9598 | if (s[0] != '$') | |
9599 | { | |
9600 | if (c == 'v') | |
bf12938e | 9601 | MIPS16_INSERT_OPERAND (RX, *ip, lastregno); |
252b5132 | 9602 | else |
bf12938e | 9603 | MIPS16_INSERT_OPERAND (RY, *ip, lastregno); |
252b5132 RH |
9604 | ++args; |
9605 | continue; | |
9606 | } | |
9607 | /* Fall through. */ | |
9608 | case 'x': | |
9609 | case 'y': | |
9610 | case 'z': | |
9611 | case 'Z': | |
9612 | case '0': | |
9613 | case 'S': | |
9614 | case 'R': | |
9615 | case 'X': | |
9616 | case 'Y': | |
9617 | if (s[0] != '$') | |
9618 | break; | |
9619 | s_reset = s; | |
3882b010 | 9620 | if (ISDIGIT (s[1])) |
252b5132 RH |
9621 | { |
9622 | ++s; | |
9623 | regno = 0; | |
9624 | do | |
9625 | { | |
9626 | regno *= 10; | |
9627 | regno += *s - '0'; | |
9628 | ++s; | |
9629 | } | |
3882b010 | 9630 | while (ISDIGIT (*s)); |
252b5132 RH |
9631 | if (regno > 31) |
9632 | { | |
9633 | as_bad (_("invalid register number (%d)"), regno); | |
9634 | regno = 2; | |
9635 | } | |
9636 | } | |
9637 | else | |
9638 | { | |
76db943d TS |
9639 | if (s[1] == 'r' && s[2] == 'a') |
9640 | { | |
9641 | s += 3; | |
9642 | regno = RA; | |
9643 | } | |
9644 | else if (s[1] == 'f' && s[2] == 'p') | |
252b5132 RH |
9645 | { |
9646 | s += 3; | |
9647 | regno = FP; | |
9648 | } | |
9649 | else if (s[1] == 's' && s[2] == 'p') | |
9650 | { | |
9651 | s += 3; | |
9652 | regno = SP; | |
9653 | } | |
9654 | else if (s[1] == 'g' && s[2] == 'p') | |
9655 | { | |
9656 | s += 3; | |
9657 | regno = GP; | |
9658 | } | |
9659 | else if (s[1] == 'a' && s[2] == 't') | |
9660 | { | |
9661 | s += 3; | |
9662 | regno = AT; | |
9663 | } | |
9664 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '0') | |
9665 | { | |
9666 | s += 4; | |
9667 | regno = KT0; | |
9668 | } | |
9669 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '1') | |
9670 | { | |
9671 | s += 4; | |
9672 | regno = KT1; | |
9673 | } | |
85b51719 TS |
9674 | else if (s[1] == 'z' && s[2] == 'e' && s[3] == 'r' && s[4] == 'o') |
9675 | { | |
9676 | s += 5; | |
9677 | regno = ZERO; | |
9678 | } | |
252b5132 RH |
9679 | else |
9680 | break; | |
9681 | } | |
9682 | ||
9683 | if (*s == ' ') | |
9684 | ++s; | |
9685 | if (args[1] != *s) | |
9686 | { | |
9687 | if (c == 'v' || c == 'w') | |
9688 | { | |
9689 | regno = mips16_to_32_reg_map[lastregno]; | |
9690 | s = s_reset; | |
f9419b05 | 9691 | ++args; |
252b5132 RH |
9692 | } |
9693 | } | |
9694 | ||
9695 | switch (c) | |
9696 | { | |
9697 | case 'x': | |
9698 | case 'y': | |
9699 | case 'z': | |
9700 | case 'v': | |
9701 | case 'w': | |
9702 | case 'Z': | |
9703 | regno = mips32_to_16_reg_map[regno]; | |
9704 | break; | |
9705 | ||
9706 | case '0': | |
9707 | if (regno != 0) | |
9708 | regno = ILLEGAL_REG; | |
9709 | break; | |
9710 | ||
9711 | case 'S': | |
9712 | if (regno != SP) | |
9713 | regno = ILLEGAL_REG; | |
9714 | break; | |
9715 | ||
9716 | case 'R': | |
9717 | if (regno != RA) | |
9718 | regno = ILLEGAL_REG; | |
9719 | break; | |
9720 | ||
9721 | case 'X': | |
9722 | case 'Y': | |
9723 | if (regno == AT && ! mips_opts.noat) | |
9724 | as_warn (_("used $at without \".set noat\"")); | |
9725 | break; | |
9726 | ||
9727 | default: | |
9728 | internalError (); | |
9729 | } | |
9730 | ||
9731 | if (regno == ILLEGAL_REG) | |
9732 | break; | |
9733 | ||
9734 | switch (c) | |
9735 | { | |
9736 | case 'x': | |
9737 | case 'v': | |
bf12938e | 9738 | MIPS16_INSERT_OPERAND (RX, *ip, regno); |
252b5132 RH |
9739 | break; |
9740 | case 'y': | |
9741 | case 'w': | |
bf12938e | 9742 | MIPS16_INSERT_OPERAND (RY, *ip, regno); |
252b5132 RH |
9743 | break; |
9744 | case 'z': | |
bf12938e | 9745 | MIPS16_INSERT_OPERAND (RZ, *ip, regno); |
252b5132 RH |
9746 | break; |
9747 | case 'Z': | |
bf12938e | 9748 | MIPS16_INSERT_OPERAND (MOVE32Z, *ip, regno); |
252b5132 RH |
9749 | case '0': |
9750 | case 'S': | |
9751 | case 'R': | |
9752 | break; | |
9753 | case 'X': | |
bf12938e | 9754 | MIPS16_INSERT_OPERAND (REGR32, *ip, regno); |
252b5132 RH |
9755 | break; |
9756 | case 'Y': | |
9757 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); | |
bf12938e | 9758 | MIPS16_INSERT_OPERAND (REG32R, *ip, regno); |
252b5132 RH |
9759 | break; |
9760 | default: | |
9761 | internalError (); | |
9762 | } | |
9763 | ||
9764 | lastregno = regno; | |
9765 | continue; | |
9766 | ||
9767 | case 'P': | |
9768 | if (strncmp (s, "$pc", 3) == 0) | |
9769 | { | |
9770 | s += 3; | |
9771 | continue; | |
9772 | } | |
9773 | break; | |
9774 | ||
252b5132 RH |
9775 | case '5': |
9776 | case 'H': | |
9777 | case 'W': | |
9778 | case 'D': | |
9779 | case 'j': | |
252b5132 RH |
9780 | case 'V': |
9781 | case 'C': | |
9782 | case 'U': | |
9783 | case 'k': | |
9784 | case 'K': | |
d6f16593 MR |
9785 | i = my_getSmallExpression (&imm_expr, imm_reloc, s); |
9786 | if (i > 0) | |
252b5132 | 9787 | { |
d6f16593 | 9788 | if (imm_expr.X_op != O_constant) |
252b5132 | 9789 | { |
b34976b6 | 9790 | mips16_ext = TRUE; |
b34976b6 | 9791 | ip->use_extend = TRUE; |
252b5132 | 9792 | ip->extend = 0; |
252b5132 | 9793 | } |
d6f16593 MR |
9794 | else |
9795 | { | |
9796 | /* We need to relax this instruction. */ | |
9797 | *offset_reloc = *imm_reloc; | |
9798 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; | |
9799 | } | |
9800 | s = expr_end; | |
9801 | continue; | |
252b5132 | 9802 | } |
d6f16593 MR |
9803 | *imm_reloc = BFD_RELOC_UNUSED; |
9804 | /* Fall through. */ | |
9805 | case '<': | |
9806 | case '>': | |
9807 | case '[': | |
9808 | case ']': | |
9809 | case '4': | |
9810 | case '8': | |
9811 | my_getExpression (&imm_expr, s); | |
252b5132 RH |
9812 | if (imm_expr.X_op == O_register) |
9813 | { | |
9814 | /* What we thought was an expression turned out to | |
9815 | be a register. */ | |
9816 | ||
9817 | if (s[0] == '(' && args[1] == '(') | |
9818 | { | |
9819 | /* It looks like the expression was omitted | |
9820 | before a register indirection, which means | |
9821 | that the expression is implicitly zero. We | |
9822 | still set up imm_expr, so that we handle | |
9823 | explicit extensions correctly. */ | |
9824 | imm_expr.X_op = O_constant; | |
9825 | imm_expr.X_add_number = 0; | |
f6688943 | 9826 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
9827 | continue; |
9828 | } | |
9829 | ||
9830 | break; | |
9831 | } | |
9832 | ||
9833 | /* We need to relax this instruction. */ | |
f6688943 | 9834 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
9835 | s = expr_end; |
9836 | continue; | |
9837 | ||
9838 | case 'p': | |
9839 | case 'q': | |
9840 | case 'A': | |
9841 | case 'B': | |
9842 | case 'E': | |
9843 | /* We use offset_reloc rather than imm_reloc for the PC | |
9844 | relative operands. This lets macros with both | |
9845 | immediate and address operands work correctly. */ | |
9846 | my_getExpression (&offset_expr, s); | |
9847 | ||
9848 | if (offset_expr.X_op == O_register) | |
9849 | break; | |
9850 | ||
9851 | /* We need to relax this instruction. */ | |
f6688943 | 9852 | *offset_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
9853 | s = expr_end; |
9854 | continue; | |
9855 | ||
9856 | case '6': /* break code */ | |
9857 | my_getExpression (&imm_expr, s); | |
9858 | check_absolute_expr (ip, &imm_expr); | |
9859 | if ((unsigned long) imm_expr.X_add_number > 63) | |
bf12938e RS |
9860 | as_warn (_("Invalid value for `%s' (%lu)"), |
9861 | ip->insn_mo->name, | |
9862 | (unsigned long) imm_expr.X_add_number); | |
9863 | MIPS16_INSERT_OPERAND (IMM6, *ip, imm_expr.X_add_number); | |
252b5132 RH |
9864 | imm_expr.X_op = O_absent; |
9865 | s = expr_end; | |
9866 | continue; | |
9867 | ||
9868 | case 'a': /* 26 bit address */ | |
9869 | my_getExpression (&offset_expr, s); | |
9870 | s = expr_end; | |
f6688943 | 9871 | *offset_reloc = BFD_RELOC_MIPS16_JMP; |
252b5132 RH |
9872 | ip->insn_opcode <<= 16; |
9873 | continue; | |
9874 | ||
9875 | case 'l': /* register list for entry macro */ | |
9876 | case 'L': /* register list for exit macro */ | |
9877 | { | |
9878 | int mask; | |
9879 | ||
9880 | if (c == 'l') | |
9881 | mask = 0; | |
9882 | else | |
9883 | mask = 7 << 3; | |
9884 | while (*s != '\0') | |
9885 | { | |
9886 | int freg, reg1, reg2; | |
9887 | ||
9888 | while (*s == ' ' || *s == ',') | |
9889 | ++s; | |
9890 | if (*s != '$') | |
9891 | { | |
9892 | as_bad (_("can't parse register list")); | |
9893 | break; | |
9894 | } | |
9895 | ++s; | |
9896 | if (*s != 'f') | |
9897 | freg = 0; | |
9898 | else | |
9899 | { | |
9900 | freg = 1; | |
9901 | ++s; | |
9902 | } | |
9903 | reg1 = 0; | |
3882b010 | 9904 | while (ISDIGIT (*s)) |
252b5132 RH |
9905 | { |
9906 | reg1 *= 10; | |
9907 | reg1 += *s - '0'; | |
9908 | ++s; | |
9909 | } | |
9910 | if (*s == ' ') | |
9911 | ++s; | |
9912 | if (*s != '-') | |
9913 | reg2 = reg1; | |
9914 | else | |
9915 | { | |
9916 | ++s; | |
9917 | if (*s != '$') | |
9918 | break; | |
9919 | ++s; | |
9920 | if (freg) | |
9921 | { | |
9922 | if (*s == 'f') | |
9923 | ++s; | |
9924 | else | |
9925 | { | |
9926 | as_bad (_("invalid register list")); | |
9927 | break; | |
9928 | } | |
9929 | } | |
9930 | reg2 = 0; | |
3882b010 | 9931 | while (ISDIGIT (*s)) |
252b5132 RH |
9932 | { |
9933 | reg2 *= 10; | |
9934 | reg2 += *s - '0'; | |
9935 | ++s; | |
9936 | } | |
9937 | } | |
9938 | if (freg && reg1 == 0 && reg2 == 0 && c == 'L') | |
9939 | { | |
9940 | mask &= ~ (7 << 3); | |
9941 | mask |= 5 << 3; | |
9942 | } | |
9943 | else if (freg && reg1 == 0 && reg2 == 1 && c == 'L') | |
9944 | { | |
9945 | mask &= ~ (7 << 3); | |
9946 | mask |= 6 << 3; | |
9947 | } | |
9948 | else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L') | |
9949 | mask |= (reg2 - 3) << 3; | |
9950 | else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17) | |
9951 | mask |= (reg2 - 15) << 1; | |
f9419b05 | 9952 | else if (reg1 == RA && reg2 == RA) |
252b5132 RH |
9953 | mask |= 1; |
9954 | else | |
9955 | { | |
9956 | as_bad (_("invalid register list")); | |
9957 | break; | |
9958 | } | |
9959 | } | |
9960 | /* The mask is filled in in the opcode table for the | |
9961 | benefit of the disassembler. We remove it before | |
9962 | applying the actual mask. */ | |
9963 | ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6); | |
9964 | ip->insn_opcode |= mask << MIPS16OP_SH_IMM6; | |
9965 | } | |
9966 | continue; | |
9967 | ||
0499d65b TS |
9968 | case 'm': /* Register list for save insn. */ |
9969 | case 'M': /* Register list for restore insn. */ | |
9970 | { | |
9971 | int opcode = 0; | |
9972 | int framesz = 0, seen_framesz = 0; | |
9973 | int args = 0, statics = 0, sregs = 0; | |
9974 | ||
9975 | while (*s != '\0') | |
9976 | { | |
9977 | unsigned int reg1, reg2; | |
9978 | ||
9979 | SKIP_SPACE_TABS (s); | |
9980 | while (*s == ',') | |
9981 | ++s; | |
9982 | SKIP_SPACE_TABS (s); | |
9983 | ||
9984 | my_getExpression (&imm_expr, s); | |
9985 | if (imm_expr.X_op == O_constant) | |
9986 | { | |
9987 | /* Handle the frame size. */ | |
9988 | if (seen_framesz) | |
9989 | { | |
9990 | as_bad (_("more than one frame size in list")); | |
9991 | break; | |
9992 | } | |
9993 | seen_framesz = 1; | |
9994 | framesz = imm_expr.X_add_number; | |
9995 | imm_expr.X_op = O_absent; | |
9996 | s = expr_end; | |
9997 | continue; | |
9998 | } | |
9999 | ||
10000 | if (*s != '$') | |
10001 | { | |
10002 | as_bad (_("can't parse register list")); | |
10003 | break; | |
10004 | } | |
10005 | ++s; | |
10006 | ||
10007 | reg1 = 0; | |
10008 | while (ISDIGIT (*s)) | |
10009 | { | |
10010 | reg1 *= 10; | |
10011 | reg1 += *s - '0'; | |
10012 | ++s; | |
10013 | } | |
10014 | SKIP_SPACE_TABS (s); | |
10015 | if (*s != '-') | |
10016 | reg2 = reg1; | |
10017 | else | |
10018 | { | |
10019 | ++s; | |
10020 | if (*s != '$') | |
10021 | { | |
10022 | as_bad (_("can't parse register list")); | |
10023 | break; | |
10024 | } | |
10025 | ++s; | |
10026 | reg2 = 0; | |
10027 | while (ISDIGIT (*s)) | |
10028 | { | |
10029 | reg2 *= 10; | |
10030 | reg2 += *s - '0'; | |
10031 | ++s; | |
10032 | } | |
10033 | } | |
10034 | ||
10035 | while (reg1 <= reg2) | |
10036 | { | |
10037 | if (reg1 >= 4 && reg1 <= 7) | |
10038 | { | |
10039 | if (c == 'm' && !seen_framesz) | |
10040 | /* args $a0-$a3 */ | |
10041 | args |= 1 << (reg1 - 4); | |
10042 | else | |
10043 | /* statics $a0-$a3 */ | |
10044 | statics |= 1 << (reg1 - 4); | |
10045 | } | |
10046 | else if ((reg1 >= 16 && reg1 <= 23) || reg1 == 30) | |
10047 | { | |
10048 | /* $s0-$s8 */ | |
10049 | sregs |= 1 << ((reg1 == 30) ? 8 : (reg1 - 16)); | |
10050 | } | |
10051 | else if (reg1 == 31) | |
10052 | { | |
10053 | /* Add $ra to insn. */ | |
10054 | opcode |= 0x40; | |
10055 | } | |
10056 | else | |
10057 | { | |
10058 | as_bad (_("unexpected register in list")); | |
10059 | break; | |
10060 | } | |
10061 | if (++reg1 == 24) | |
10062 | reg1 = 30; | |
10063 | } | |
10064 | } | |
10065 | ||
10066 | /* Encode args/statics combination. */ | |
10067 | if (args & statics) | |
10068 | as_bad (_("arg/static registers overlap")); | |
10069 | else if (args == 0xf) | |
10070 | /* All $a0-$a3 are args. */ | |
10071 | opcode |= MIPS16_ALL_ARGS << 16; | |
10072 | else if (statics == 0xf) | |
10073 | /* All $a0-$a3 are statics. */ | |
10074 | opcode |= MIPS16_ALL_STATICS << 16; | |
10075 | else | |
10076 | { | |
10077 | int narg = 0, nstat = 0; | |
10078 | ||
10079 | /* Count arg registers. */ | |
10080 | while (args & 0x1) | |
10081 | { | |
10082 | args >>= 1; | |
10083 | narg++; | |
10084 | } | |
10085 | if (args != 0) | |
10086 | as_bad (_("invalid arg register list")); | |
10087 | ||
10088 | /* Count static registers. */ | |
10089 | while (statics & 0x8) | |
10090 | { | |
10091 | statics = (statics << 1) & 0xf; | |
10092 | nstat++; | |
10093 | } | |
10094 | if (statics != 0) | |
10095 | as_bad (_("invalid static register list")); | |
10096 | ||
10097 | /* Encode args/statics. */ | |
10098 | opcode |= ((narg << 2) | nstat) << 16; | |
10099 | } | |
10100 | ||
10101 | /* Encode $s0/$s1. */ | |
10102 | if (sregs & (1 << 0)) /* $s0 */ | |
10103 | opcode |= 0x20; | |
10104 | if (sregs & (1 << 1)) /* $s1 */ | |
10105 | opcode |= 0x10; | |
10106 | sregs >>= 2; | |
10107 | ||
10108 | if (sregs != 0) | |
10109 | { | |
10110 | /* Count regs $s2-$s8. */ | |
10111 | int nsreg = 0; | |
10112 | while (sregs & 1) | |
10113 | { | |
10114 | sregs >>= 1; | |
10115 | nsreg++; | |
10116 | } | |
10117 | if (sregs != 0) | |
10118 | as_bad (_("invalid static register list")); | |
10119 | /* Encode $s2-$s8. */ | |
10120 | opcode |= nsreg << 24; | |
10121 | } | |
10122 | ||
10123 | /* Encode frame size. */ | |
10124 | if (!seen_framesz) | |
10125 | as_bad (_("missing frame size")); | |
10126 | else if ((framesz & 7) != 0 || framesz < 0 | |
10127 | || framesz > 0xff * 8) | |
10128 | as_bad (_("invalid frame size")); | |
10129 | else if (framesz != 128 || (opcode >> 16) != 0) | |
10130 | { | |
10131 | framesz /= 8; | |
10132 | opcode |= (((framesz & 0xf0) << 16) | |
10133 | | (framesz & 0x0f)); | |
10134 | } | |
10135 | ||
10136 | /* Finally build the instruction. */ | |
10137 | if ((opcode >> 16) != 0 || framesz == 0) | |
10138 | { | |
10139 | ip->use_extend = TRUE; | |
10140 | ip->extend = opcode >> 16; | |
10141 | } | |
10142 | ip->insn_opcode |= opcode & 0x7f; | |
10143 | } | |
10144 | continue; | |
10145 | ||
252b5132 RH |
10146 | case 'e': /* extend code */ |
10147 | my_getExpression (&imm_expr, s); | |
10148 | check_absolute_expr (ip, &imm_expr); | |
10149 | if ((unsigned long) imm_expr.X_add_number > 0x7ff) | |
10150 | { | |
10151 | as_warn (_("Invalid value for `%s' (%lu)"), | |
10152 | ip->insn_mo->name, | |
10153 | (unsigned long) imm_expr.X_add_number); | |
10154 | imm_expr.X_add_number &= 0x7ff; | |
10155 | } | |
10156 | ip->insn_opcode |= imm_expr.X_add_number; | |
10157 | imm_expr.X_op = O_absent; | |
10158 | s = expr_end; | |
10159 | continue; | |
10160 | ||
10161 | default: | |
10162 | internalError (); | |
10163 | } | |
10164 | break; | |
10165 | } | |
10166 | ||
10167 | /* Args don't match. */ | |
10168 | if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] && | |
10169 | strcmp (insn->name, insn[1].name) == 0) | |
10170 | { | |
10171 | ++insn; | |
10172 | s = argsstart; | |
10173 | continue; | |
10174 | } | |
10175 | ||
10176 | insn_error = _("illegal operands"); | |
10177 | ||
10178 | return; | |
10179 | } | |
10180 | } | |
10181 | ||
10182 | /* This structure holds information we know about a mips16 immediate | |
10183 | argument type. */ | |
10184 | ||
e972090a NC |
10185 | struct mips16_immed_operand |
10186 | { | |
252b5132 RH |
10187 | /* The type code used in the argument string in the opcode table. */ |
10188 | int type; | |
10189 | /* The number of bits in the short form of the opcode. */ | |
10190 | int nbits; | |
10191 | /* The number of bits in the extended form of the opcode. */ | |
10192 | int extbits; | |
10193 | /* The amount by which the short form is shifted when it is used; | |
10194 | for example, the sw instruction has a shift count of 2. */ | |
10195 | int shift; | |
10196 | /* The amount by which the short form is shifted when it is stored | |
10197 | into the instruction code. */ | |
10198 | int op_shift; | |
10199 | /* Non-zero if the short form is unsigned. */ | |
10200 | int unsp; | |
10201 | /* Non-zero if the extended form is unsigned. */ | |
10202 | int extu; | |
10203 | /* Non-zero if the value is PC relative. */ | |
10204 | int pcrel; | |
10205 | }; | |
10206 | ||
10207 | /* The mips16 immediate operand types. */ | |
10208 | ||
10209 | static const struct mips16_immed_operand mips16_immed_operands[] = | |
10210 | { | |
10211 | { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
10212 | { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
10213 | { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
10214 | { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
10215 | { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 }, | |
10216 | { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
10217 | { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
10218 | { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
10219 | { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
10220 | { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 }, | |
10221 | { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
10222 | { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
10223 | { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
10224 | { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 }, | |
10225 | { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
10226 | { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
10227 | { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
10228 | { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
10229 | { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 }, | |
10230 | { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 }, | |
10231 | { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 } | |
10232 | }; | |
10233 | ||
10234 | #define MIPS16_NUM_IMMED \ | |
10235 | (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0]) | |
10236 | ||
10237 | /* Handle a mips16 instruction with an immediate value. This or's the | |
10238 | small immediate value into *INSN. It sets *USE_EXTEND to indicate | |
10239 | whether an extended value is needed; if one is needed, it sets | |
10240 | *EXTEND to the value. The argument type is TYPE. The value is VAL. | |
10241 | If SMALL is true, an unextended opcode was explicitly requested. | |
10242 | If EXT is true, an extended opcode was explicitly requested. If | |
10243 | WARN is true, warn if EXT does not match reality. */ | |
10244 | ||
10245 | static void | |
17a2f251 TS |
10246 | mips16_immed (char *file, unsigned int line, int type, offsetT val, |
10247 | bfd_boolean warn, bfd_boolean small, bfd_boolean ext, | |
10248 | unsigned long *insn, bfd_boolean *use_extend, | |
10249 | unsigned short *extend) | |
252b5132 RH |
10250 | { |
10251 | register const struct mips16_immed_operand *op; | |
10252 | int mintiny, maxtiny; | |
b34976b6 | 10253 | bfd_boolean needext; |
252b5132 RH |
10254 | |
10255 | op = mips16_immed_operands; | |
10256 | while (op->type != type) | |
10257 | { | |
10258 | ++op; | |
10259 | assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); | |
10260 | } | |
10261 | ||
10262 | if (op->unsp) | |
10263 | { | |
10264 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
10265 | { | |
10266 | mintiny = 1; | |
10267 | maxtiny = 1 << op->nbits; | |
10268 | } | |
10269 | else | |
10270 | { | |
10271 | mintiny = 0; | |
10272 | maxtiny = (1 << op->nbits) - 1; | |
10273 | } | |
10274 | } | |
10275 | else | |
10276 | { | |
10277 | mintiny = - (1 << (op->nbits - 1)); | |
10278 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
10279 | } | |
10280 | ||
10281 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
10282 | if (type == 'p' || type == 'q') | |
10283 | val /= 2; | |
10284 | ||
10285 | if ((val & ((1 << op->shift) - 1)) != 0 | |
10286 | || val < (mintiny << op->shift) | |
10287 | || val > (maxtiny << op->shift)) | |
b34976b6 | 10288 | needext = TRUE; |
252b5132 | 10289 | else |
b34976b6 | 10290 | needext = FALSE; |
252b5132 RH |
10291 | |
10292 | if (warn && ext && ! needext) | |
beae10d5 KH |
10293 | as_warn_where (file, line, |
10294 | _("extended operand requested but not required")); | |
252b5132 RH |
10295 | if (small && needext) |
10296 | as_bad_where (file, line, _("invalid unextended operand value")); | |
10297 | ||
10298 | if (small || (! ext && ! needext)) | |
10299 | { | |
10300 | int insnval; | |
10301 | ||
b34976b6 | 10302 | *use_extend = FALSE; |
252b5132 RH |
10303 | insnval = ((val >> op->shift) & ((1 << op->nbits) - 1)); |
10304 | insnval <<= op->op_shift; | |
10305 | *insn |= insnval; | |
10306 | } | |
10307 | else | |
10308 | { | |
10309 | long minext, maxext; | |
10310 | int extval; | |
10311 | ||
10312 | if (op->extu) | |
10313 | { | |
10314 | minext = 0; | |
10315 | maxext = (1 << op->extbits) - 1; | |
10316 | } | |
10317 | else | |
10318 | { | |
10319 | minext = - (1 << (op->extbits - 1)); | |
10320 | maxext = (1 << (op->extbits - 1)) - 1; | |
10321 | } | |
10322 | if (val < minext || val > maxext) | |
10323 | as_bad_where (file, line, | |
10324 | _("operand value out of range for instruction")); | |
10325 | ||
b34976b6 | 10326 | *use_extend = TRUE; |
252b5132 RH |
10327 | if (op->extbits == 16) |
10328 | { | |
10329 | extval = ((val >> 11) & 0x1f) | (val & 0x7e0); | |
10330 | val &= 0x1f; | |
10331 | } | |
10332 | else if (op->extbits == 15) | |
10333 | { | |
10334 | extval = ((val >> 11) & 0xf) | (val & 0x7f0); | |
10335 | val &= 0xf; | |
10336 | } | |
10337 | else | |
10338 | { | |
10339 | extval = ((val & 0x1f) << 6) | (val & 0x20); | |
10340 | val = 0; | |
10341 | } | |
10342 | ||
10343 | *extend = (unsigned short) extval; | |
10344 | *insn |= val; | |
10345 | } | |
10346 | } | |
10347 | \f | |
d6f16593 | 10348 | struct percent_op_match |
ad8d3bb3 | 10349 | { |
5e0116d5 RS |
10350 | const char *str; |
10351 | bfd_reloc_code_real_type reloc; | |
d6f16593 MR |
10352 | }; |
10353 | ||
10354 | static const struct percent_op_match mips_percent_op[] = | |
ad8d3bb3 | 10355 | { |
5e0116d5 | 10356 | {"%lo", BFD_RELOC_LO16}, |
ad8d3bb3 | 10357 | #ifdef OBJ_ELF |
5e0116d5 RS |
10358 | {"%call_hi", BFD_RELOC_MIPS_CALL_HI16}, |
10359 | {"%call_lo", BFD_RELOC_MIPS_CALL_LO16}, | |
10360 | {"%call16", BFD_RELOC_MIPS_CALL16}, | |
10361 | {"%got_disp", BFD_RELOC_MIPS_GOT_DISP}, | |
10362 | {"%got_page", BFD_RELOC_MIPS_GOT_PAGE}, | |
10363 | {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST}, | |
10364 | {"%got_hi", BFD_RELOC_MIPS_GOT_HI16}, | |
10365 | {"%got_lo", BFD_RELOC_MIPS_GOT_LO16}, | |
10366 | {"%got", BFD_RELOC_MIPS_GOT16}, | |
10367 | {"%gp_rel", BFD_RELOC_GPREL16}, | |
10368 | {"%half", BFD_RELOC_16}, | |
10369 | {"%highest", BFD_RELOC_MIPS_HIGHEST}, | |
10370 | {"%higher", BFD_RELOC_MIPS_HIGHER}, | |
10371 | {"%neg", BFD_RELOC_MIPS_SUB}, | |
3f98094e DJ |
10372 | {"%tlsgd", BFD_RELOC_MIPS_TLS_GD}, |
10373 | {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM}, | |
10374 | {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16}, | |
10375 | {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16}, | |
10376 | {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16}, | |
10377 | {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16}, | |
10378 | {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL}, | |
ad8d3bb3 | 10379 | #endif |
5e0116d5 | 10380 | {"%hi", BFD_RELOC_HI16_S} |
ad8d3bb3 TS |
10381 | }; |
10382 | ||
d6f16593 MR |
10383 | static const struct percent_op_match mips16_percent_op[] = |
10384 | { | |
10385 | {"%lo", BFD_RELOC_MIPS16_LO16}, | |
10386 | {"%gprel", BFD_RELOC_MIPS16_GPREL}, | |
10387 | {"%hi", BFD_RELOC_MIPS16_HI16_S} | |
10388 | }; | |
10389 | ||
252b5132 | 10390 | |
5e0116d5 RS |
10391 | /* Return true if *STR points to a relocation operator. When returning true, |
10392 | move *STR over the operator and store its relocation code in *RELOC. | |
10393 | Leave both *STR and *RELOC alone when returning false. */ | |
10394 | ||
10395 | static bfd_boolean | |
17a2f251 | 10396 | parse_relocation (char **str, bfd_reloc_code_real_type *reloc) |
252b5132 | 10397 | { |
d6f16593 MR |
10398 | const struct percent_op_match *percent_op; |
10399 | size_t limit, i; | |
10400 | ||
10401 | if (mips_opts.mips16) | |
10402 | { | |
10403 | percent_op = mips16_percent_op; | |
10404 | limit = ARRAY_SIZE (mips16_percent_op); | |
10405 | } | |
10406 | else | |
10407 | { | |
10408 | percent_op = mips_percent_op; | |
10409 | limit = ARRAY_SIZE (mips_percent_op); | |
10410 | } | |
76b3015f | 10411 | |
d6f16593 | 10412 | for (i = 0; i < limit; i++) |
5e0116d5 | 10413 | if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0) |
394f9b3a | 10414 | { |
3f98094e DJ |
10415 | int len = strlen (percent_op[i].str); |
10416 | ||
10417 | if (!ISSPACE ((*str)[len]) && (*str)[len] != '(') | |
10418 | continue; | |
10419 | ||
5e0116d5 RS |
10420 | *str += strlen (percent_op[i].str); |
10421 | *reloc = percent_op[i].reloc; | |
394f9b3a | 10422 | |
5e0116d5 RS |
10423 | /* Check whether the output BFD supports this relocation. |
10424 | If not, issue an error and fall back on something safe. */ | |
10425 | if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc)) | |
394f9b3a | 10426 | { |
5e0116d5 RS |
10427 | as_bad ("relocation %s isn't supported by the current ABI", |
10428 | percent_op[i].str); | |
01a3f561 | 10429 | *reloc = BFD_RELOC_UNUSED; |
394f9b3a | 10430 | } |
5e0116d5 | 10431 | return TRUE; |
394f9b3a | 10432 | } |
5e0116d5 | 10433 | return FALSE; |
394f9b3a | 10434 | } |
ad8d3bb3 | 10435 | |
ad8d3bb3 | 10436 | |
5e0116d5 RS |
10437 | /* Parse string STR as a 16-bit relocatable operand. Store the |
10438 | expression in *EP and the relocations in the array starting | |
10439 | at RELOC. Return the number of relocation operators used. | |
ad8d3bb3 | 10440 | |
01a3f561 | 10441 | On exit, EXPR_END points to the first character after the expression. */ |
ad8d3bb3 | 10442 | |
5e0116d5 | 10443 | static size_t |
17a2f251 TS |
10444 | my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc, |
10445 | char *str) | |
ad8d3bb3 | 10446 | { |
5e0116d5 RS |
10447 | bfd_reloc_code_real_type reversed_reloc[3]; |
10448 | size_t reloc_index, i; | |
09b8f35a RS |
10449 | int crux_depth, str_depth; |
10450 | char *crux; | |
5e0116d5 RS |
10451 | |
10452 | /* Search for the start of the main expression, recoding relocations | |
09b8f35a RS |
10453 | in REVERSED_RELOC. End the loop with CRUX pointing to the start |
10454 | of the main expression and with CRUX_DEPTH containing the number | |
10455 | of open brackets at that point. */ | |
10456 | reloc_index = -1; | |
10457 | str_depth = 0; | |
10458 | do | |
fb1b3232 | 10459 | { |
09b8f35a RS |
10460 | reloc_index++; |
10461 | crux = str; | |
10462 | crux_depth = str_depth; | |
10463 | ||
10464 | /* Skip over whitespace and brackets, keeping count of the number | |
10465 | of brackets. */ | |
10466 | while (*str == ' ' || *str == '\t' || *str == '(') | |
10467 | if (*str++ == '(') | |
10468 | str_depth++; | |
5e0116d5 | 10469 | } |
09b8f35a RS |
10470 | while (*str == '%' |
10471 | && reloc_index < (HAVE_NEWABI ? 3 : 1) | |
10472 | && parse_relocation (&str, &reversed_reloc[reloc_index])); | |
ad8d3bb3 | 10473 | |
09b8f35a | 10474 | my_getExpression (ep, crux); |
5e0116d5 | 10475 | str = expr_end; |
394f9b3a | 10476 | |
5e0116d5 | 10477 | /* Match every open bracket. */ |
09b8f35a | 10478 | while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t')) |
5e0116d5 | 10479 | if (*str++ == ')') |
09b8f35a | 10480 | crux_depth--; |
394f9b3a | 10481 | |
09b8f35a | 10482 | if (crux_depth > 0) |
5e0116d5 | 10483 | as_bad ("unclosed '('"); |
394f9b3a | 10484 | |
5e0116d5 | 10485 | expr_end = str; |
252b5132 | 10486 | |
01a3f561 | 10487 | if (reloc_index != 0) |
64bdfcaf RS |
10488 | { |
10489 | prev_reloc_op_frag = frag_now; | |
10490 | for (i = 0; i < reloc_index; i++) | |
10491 | reloc[i] = reversed_reloc[reloc_index - 1 - i]; | |
10492 | } | |
fb1b3232 | 10493 | |
5e0116d5 | 10494 | return reloc_index; |
252b5132 RH |
10495 | } |
10496 | ||
10497 | static void | |
17a2f251 | 10498 | my_getExpression (expressionS *ep, char *str) |
252b5132 RH |
10499 | { |
10500 | char *save_in; | |
98aa84af | 10501 | valueT val; |
252b5132 RH |
10502 | |
10503 | save_in = input_line_pointer; | |
10504 | input_line_pointer = str; | |
10505 | expression (ep); | |
10506 | expr_end = input_line_pointer; | |
10507 | input_line_pointer = save_in; | |
10508 | ||
10509 | /* If we are in mips16 mode, and this is an expression based on `.', | |
10510 | then we bump the value of the symbol by 1 since that is how other | |
10511 | text symbols are handled. We don't bother to handle complex | |
10512 | expressions, just `.' plus or minus a constant. */ | |
10513 | if (mips_opts.mips16 | |
10514 | && ep->X_op == O_symbol | |
10515 | && strcmp (S_GET_NAME (ep->X_add_symbol), FAKE_LABEL_NAME) == 0 | |
10516 | && S_GET_SEGMENT (ep->X_add_symbol) == now_seg | |
49309057 ILT |
10517 | && symbol_get_frag (ep->X_add_symbol) == frag_now |
10518 | && symbol_constant_p (ep->X_add_symbol) | |
98aa84af AM |
10519 | && (val = S_GET_VALUE (ep->X_add_symbol)) == frag_now_fix ()) |
10520 | S_SET_VALUE (ep->X_add_symbol, val + 1); | |
252b5132 RH |
10521 | } |
10522 | ||
10523 | /* Turn a string in input_line_pointer into a floating point constant | |
bc0d738a NC |
10524 | of type TYPE, and store the appropriate bytes in *LITP. The number |
10525 | of LITTLENUMS emitted is stored in *SIZEP. An error message is | |
252b5132 RH |
10526 | returned, or NULL on OK. */ |
10527 | ||
10528 | char * | |
17a2f251 | 10529 | md_atof (int type, char *litP, int *sizeP) |
252b5132 RH |
10530 | { |
10531 | int prec; | |
10532 | LITTLENUM_TYPE words[4]; | |
10533 | char *t; | |
10534 | int i; | |
10535 | ||
10536 | switch (type) | |
10537 | { | |
10538 | case 'f': | |
10539 | prec = 2; | |
10540 | break; | |
10541 | ||
10542 | case 'd': | |
10543 | prec = 4; | |
10544 | break; | |
10545 | ||
10546 | default: | |
10547 | *sizeP = 0; | |
10548 | return _("bad call to md_atof"); | |
10549 | } | |
10550 | ||
10551 | t = atof_ieee (input_line_pointer, type, words); | |
10552 | if (t) | |
10553 | input_line_pointer = t; | |
10554 | ||
10555 | *sizeP = prec * 2; | |
10556 | ||
10557 | if (! target_big_endian) | |
10558 | { | |
10559 | for (i = prec - 1; i >= 0; i--) | |
10560 | { | |
17a2f251 | 10561 | md_number_to_chars (litP, words[i], 2); |
252b5132 RH |
10562 | litP += 2; |
10563 | } | |
10564 | } | |
10565 | else | |
10566 | { | |
10567 | for (i = 0; i < prec; i++) | |
10568 | { | |
17a2f251 | 10569 | md_number_to_chars (litP, words[i], 2); |
252b5132 RH |
10570 | litP += 2; |
10571 | } | |
10572 | } | |
bdaaa2e1 | 10573 | |
252b5132 RH |
10574 | return NULL; |
10575 | } | |
10576 | ||
10577 | void | |
17a2f251 | 10578 | md_number_to_chars (char *buf, valueT val, int n) |
252b5132 RH |
10579 | { |
10580 | if (target_big_endian) | |
10581 | number_to_chars_bigendian (buf, val, n); | |
10582 | else | |
10583 | number_to_chars_littleendian (buf, val, n); | |
10584 | } | |
10585 | \f | |
ae948b86 | 10586 | #ifdef OBJ_ELF |
e013f690 TS |
10587 | static int support_64bit_objects(void) |
10588 | { | |
10589 | const char **list, **l; | |
aa3d8fdf | 10590 | int yes; |
e013f690 TS |
10591 | |
10592 | list = bfd_target_list (); | |
10593 | for (l = list; *l != NULL; l++) | |
10594 | #ifdef TE_TMIPS | |
10595 | /* This is traditional mips */ | |
10596 | if (strcmp (*l, "elf64-tradbigmips") == 0 | |
10597 | || strcmp (*l, "elf64-tradlittlemips") == 0) | |
10598 | #else | |
10599 | if (strcmp (*l, "elf64-bigmips") == 0 | |
10600 | || strcmp (*l, "elf64-littlemips") == 0) | |
10601 | #endif | |
10602 | break; | |
aa3d8fdf | 10603 | yes = (*l != NULL); |
e013f690 | 10604 | free (list); |
aa3d8fdf | 10605 | return yes; |
e013f690 | 10606 | } |
ae948b86 | 10607 | #endif /* OBJ_ELF */ |
e013f690 | 10608 | |
78849248 | 10609 | const char *md_shortopts = "O::g::G:"; |
252b5132 | 10610 | |
e972090a NC |
10611 | struct option md_longopts[] = |
10612 | { | |
f9b4148d CD |
10613 | /* Options which specify architecture. */ |
10614 | #define OPTION_ARCH_BASE (OPTION_MD_BASE) | |
10615 | #define OPTION_MARCH (OPTION_ARCH_BASE + 0) | |
10616 | {"march", required_argument, NULL, OPTION_MARCH}, | |
10617 | #define OPTION_MTUNE (OPTION_ARCH_BASE + 1) | |
10618 | {"mtune", required_argument, NULL, OPTION_MTUNE}, | |
10619 | #define OPTION_MIPS1 (OPTION_ARCH_BASE + 2) | |
252b5132 RH |
10620 | {"mips0", no_argument, NULL, OPTION_MIPS1}, |
10621 | {"mips1", no_argument, NULL, OPTION_MIPS1}, | |
f9b4148d | 10622 | #define OPTION_MIPS2 (OPTION_ARCH_BASE + 3) |
252b5132 | 10623 | {"mips2", no_argument, NULL, OPTION_MIPS2}, |
f9b4148d | 10624 | #define OPTION_MIPS3 (OPTION_ARCH_BASE + 4) |
252b5132 | 10625 | {"mips3", no_argument, NULL, OPTION_MIPS3}, |
f9b4148d | 10626 | #define OPTION_MIPS4 (OPTION_ARCH_BASE + 5) |
252b5132 | 10627 | {"mips4", no_argument, NULL, OPTION_MIPS4}, |
f9b4148d | 10628 | #define OPTION_MIPS5 (OPTION_ARCH_BASE + 6) |
ae948b86 | 10629 | {"mips5", no_argument, NULL, OPTION_MIPS5}, |
f9b4148d | 10630 | #define OPTION_MIPS32 (OPTION_ARCH_BASE + 7) |
ae948b86 | 10631 | {"mips32", no_argument, NULL, OPTION_MIPS32}, |
f9b4148d | 10632 | #define OPTION_MIPS64 (OPTION_ARCH_BASE + 8) |
ae948b86 | 10633 | {"mips64", no_argument, NULL, OPTION_MIPS64}, |
f9b4148d CD |
10634 | #define OPTION_MIPS32R2 (OPTION_ARCH_BASE + 9) |
10635 | {"mips32r2", no_argument, NULL, OPTION_MIPS32R2}, | |
5f74bc13 CD |
10636 | #define OPTION_MIPS64R2 (OPTION_ARCH_BASE + 10) |
10637 | {"mips64r2", no_argument, NULL, OPTION_MIPS64R2}, | |
f9b4148d CD |
10638 | |
10639 | /* Options which specify Application Specific Extensions (ASEs). */ | |
5f74bc13 | 10640 | #define OPTION_ASE_BASE (OPTION_ARCH_BASE + 11) |
f9b4148d CD |
10641 | #define OPTION_MIPS16 (OPTION_ASE_BASE + 0) |
10642 | {"mips16", no_argument, NULL, OPTION_MIPS16}, | |
10643 | #define OPTION_NO_MIPS16 (OPTION_ASE_BASE + 1) | |
10644 | {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16}, | |
10645 | #define OPTION_MIPS3D (OPTION_ASE_BASE + 2) | |
10646 | {"mips3d", no_argument, NULL, OPTION_MIPS3D}, | |
10647 | #define OPTION_NO_MIPS3D (OPTION_ASE_BASE + 3) | |
10648 | {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D}, | |
10649 | #define OPTION_MDMX (OPTION_ASE_BASE + 4) | |
10650 | {"mdmx", no_argument, NULL, OPTION_MDMX}, | |
10651 | #define OPTION_NO_MDMX (OPTION_ASE_BASE + 5) | |
10652 | {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX}, | |
74cd071d CF |
10653 | #define OPTION_DSP (OPTION_ASE_BASE + 6) |
10654 | {"mdsp", no_argument, NULL, OPTION_DSP}, | |
10655 | #define OPTION_NO_DSP (OPTION_ASE_BASE + 7) | |
10656 | {"mno-dsp", no_argument, NULL, OPTION_NO_DSP}, | |
ef2e4d86 CF |
10657 | #define OPTION_MT (OPTION_ASE_BASE + 8) |
10658 | {"mmt", no_argument, NULL, OPTION_MT}, | |
10659 | #define OPTION_NO_MT (OPTION_ASE_BASE + 9) | |
10660 | {"mno-mt", no_argument, NULL, OPTION_NO_MT}, | |
e16bfa71 TS |
10661 | #define OPTION_SMARTMIPS (OPTION_ASE_BASE + 10) |
10662 | {"msmartmips", no_argument, NULL, OPTION_SMARTMIPS}, | |
10663 | #define OPTION_NO_SMARTMIPS (OPTION_ASE_BASE + 11) | |
10664 | {"mno-smartmips", no_argument, NULL, OPTION_NO_SMARTMIPS}, | |
f9b4148d CD |
10665 | |
10666 | /* Old-style architecture options. Don't add more of these. */ | |
e16bfa71 | 10667 | #define OPTION_COMPAT_ARCH_BASE (OPTION_ASE_BASE + 12) |
f9b4148d CD |
10668 | #define OPTION_M4650 (OPTION_COMPAT_ARCH_BASE + 0) |
10669 | {"m4650", no_argument, NULL, OPTION_M4650}, | |
10670 | #define OPTION_NO_M4650 (OPTION_COMPAT_ARCH_BASE + 1) | |
10671 | {"no-m4650", no_argument, NULL, OPTION_NO_M4650}, | |
10672 | #define OPTION_M4010 (OPTION_COMPAT_ARCH_BASE + 2) | |
10673 | {"m4010", no_argument, NULL, OPTION_M4010}, | |
10674 | #define OPTION_NO_M4010 (OPTION_COMPAT_ARCH_BASE + 3) | |
10675 | {"no-m4010", no_argument, NULL, OPTION_NO_M4010}, | |
10676 | #define OPTION_M4100 (OPTION_COMPAT_ARCH_BASE + 4) | |
10677 | {"m4100", no_argument, NULL, OPTION_M4100}, | |
10678 | #define OPTION_NO_M4100 (OPTION_COMPAT_ARCH_BASE + 5) | |
10679 | {"no-m4100", no_argument, NULL, OPTION_NO_M4100}, | |
10680 | #define OPTION_M3900 (OPTION_COMPAT_ARCH_BASE + 6) | |
10681 | {"m3900", no_argument, NULL, OPTION_M3900}, | |
10682 | #define OPTION_NO_M3900 (OPTION_COMPAT_ARCH_BASE + 7) | |
10683 | {"no-m3900", no_argument, NULL, OPTION_NO_M3900}, | |
10684 | ||
10685 | /* Options which enable bug fixes. */ | |
10686 | #define OPTION_FIX_BASE (OPTION_COMPAT_ARCH_BASE + 8) | |
10687 | #define OPTION_M7000_HILO_FIX (OPTION_FIX_BASE + 0) | |
10688 | {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX}, | |
10689 | #define OPTION_MNO_7000_HILO_FIX (OPTION_FIX_BASE + 1) | |
10690 | {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, | |
10691 | {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, | |
d766e8ec RS |
10692 | #define OPTION_FIX_VR4120 (OPTION_FIX_BASE + 2) |
10693 | #define OPTION_NO_FIX_VR4120 (OPTION_FIX_BASE + 3) | |
10694 | {"mfix-vr4120", no_argument, NULL, OPTION_FIX_VR4120}, | |
10695 | {"mno-fix-vr4120", no_argument, NULL, OPTION_NO_FIX_VR4120}, | |
7d8e00cf RS |
10696 | #define OPTION_FIX_VR4130 (OPTION_FIX_BASE + 4) |
10697 | #define OPTION_NO_FIX_VR4130 (OPTION_FIX_BASE + 5) | |
10698 | {"mfix-vr4130", no_argument, NULL, OPTION_FIX_VR4130}, | |
10699 | {"mno-fix-vr4130", no_argument, NULL, OPTION_NO_FIX_VR4130}, | |
f9b4148d CD |
10700 | |
10701 | /* Miscellaneous options. */ | |
7d8e00cf | 10702 | #define OPTION_MISC_BASE (OPTION_FIX_BASE + 6) |
1ffcab4b | 10703 | #define OPTION_TRAP (OPTION_MISC_BASE + 0) |
252b5132 RH |
10704 | {"trap", no_argument, NULL, OPTION_TRAP}, |
10705 | {"no-break", no_argument, NULL, OPTION_TRAP}, | |
1ffcab4b | 10706 | #define OPTION_BREAK (OPTION_MISC_BASE + 1) |
252b5132 RH |
10707 | {"break", no_argument, NULL, OPTION_BREAK}, |
10708 | {"no-trap", no_argument, NULL, OPTION_BREAK}, | |
1ffcab4b | 10709 | #define OPTION_EB (OPTION_MISC_BASE + 2) |
252b5132 | 10710 | {"EB", no_argument, NULL, OPTION_EB}, |
1ffcab4b | 10711 | #define OPTION_EL (OPTION_MISC_BASE + 3) |
252b5132 | 10712 | {"EL", no_argument, NULL, OPTION_EL}, |
1ffcab4b | 10713 | #define OPTION_FP32 (OPTION_MISC_BASE + 4) |
ae948b86 | 10714 | {"mfp32", no_argument, NULL, OPTION_FP32}, |
1ffcab4b | 10715 | #define OPTION_GP32 (OPTION_MISC_BASE + 5) |
c97ef257 | 10716 | {"mgp32", no_argument, NULL, OPTION_GP32}, |
1ffcab4b | 10717 | #define OPTION_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 6) |
119d663a | 10718 | {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS}, |
1ffcab4b | 10719 | #define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 7) |
119d663a | 10720 | {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS}, |
1ffcab4b | 10721 | #define OPTION_FP64 (OPTION_MISC_BASE + 8) |
316f5878 | 10722 | {"mfp64", no_argument, NULL, OPTION_FP64}, |
1ffcab4b | 10723 | #define OPTION_GP64 (OPTION_MISC_BASE + 9) |
ae948b86 | 10724 | {"mgp64", no_argument, NULL, OPTION_GP64}, |
1ffcab4b CD |
10725 | #define OPTION_RELAX_BRANCH (OPTION_MISC_BASE + 10) |
10726 | #define OPTION_NO_RELAX_BRANCH (OPTION_MISC_BASE + 11) | |
4a6a3df4 AO |
10727 | {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH}, |
10728 | {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH}, | |
aa6975fb ILT |
10729 | #define OPTION_MSHARED (OPTION_MISC_BASE + 12) |
10730 | #define OPTION_MNO_SHARED (OPTION_MISC_BASE + 13) | |
10731 | {"mshared", no_argument, NULL, OPTION_MSHARED}, | |
10732 | {"mno-shared", no_argument, NULL, OPTION_MNO_SHARED}, | |
aed1a261 RS |
10733 | #define OPTION_MSYM32 (OPTION_MISC_BASE + 14) |
10734 | #define OPTION_MNO_SYM32 (OPTION_MISC_BASE + 15) | |
10735 | {"msym32", no_argument, NULL, OPTION_MSYM32}, | |
10736 | {"mno-sym32", no_argument, NULL, OPTION_MNO_SYM32}, | |
f9b4148d CD |
10737 | |
10738 | /* ELF-specific options. */ | |
156c2f8b | 10739 | #ifdef OBJ_ELF |
aed1a261 | 10740 | #define OPTION_ELF_BASE (OPTION_MISC_BASE + 16) |
156c2f8b | 10741 | #define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0) |
156c2f8b NC |
10742 | {"KPIC", no_argument, NULL, OPTION_CALL_SHARED}, |
10743 | {"call_shared", no_argument, NULL, OPTION_CALL_SHARED}, | |
ae948b86 | 10744 | #define OPTION_NON_SHARED (OPTION_ELF_BASE + 1) |
156c2f8b | 10745 | {"non_shared", no_argument, NULL, OPTION_NON_SHARED}, |
ae948b86 | 10746 | #define OPTION_XGOT (OPTION_ELF_BASE + 2) |
156c2f8b | 10747 | {"xgot", no_argument, NULL, OPTION_XGOT}, |
ae948b86 TS |
10748 | #define OPTION_MABI (OPTION_ELF_BASE + 3) |
10749 | {"mabi", required_argument, NULL, OPTION_MABI}, | |
10750 | #define OPTION_32 (OPTION_ELF_BASE + 4) | |
156c2f8b | 10751 | {"32", no_argument, NULL, OPTION_32}, |
ae948b86 | 10752 | #define OPTION_N32 (OPTION_ELF_BASE + 5) |
e013f690 | 10753 | {"n32", no_argument, NULL, OPTION_N32}, |
ae948b86 | 10754 | #define OPTION_64 (OPTION_ELF_BASE + 6) |
156c2f8b | 10755 | {"64", no_argument, NULL, OPTION_64}, |
ecb4347a DJ |
10756 | #define OPTION_MDEBUG (OPTION_ELF_BASE + 7) |
10757 | {"mdebug", no_argument, NULL, OPTION_MDEBUG}, | |
10758 | #define OPTION_NO_MDEBUG (OPTION_ELF_BASE + 8) | |
10759 | {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG}, | |
dcd410fe RO |
10760 | #define OPTION_PDR (OPTION_ELF_BASE + 9) |
10761 | {"mpdr", no_argument, NULL, OPTION_PDR}, | |
10762 | #define OPTION_NO_PDR (OPTION_ELF_BASE + 10) | |
10763 | {"mno-pdr", no_argument, NULL, OPTION_NO_PDR}, | |
0a44bf69 RS |
10764 | #define OPTION_MVXWORKS_PIC (OPTION_ELF_BASE + 11) |
10765 | {"mvxworks-pic", no_argument, NULL, OPTION_MVXWORKS_PIC}, | |
ae948b86 | 10766 | #endif /* OBJ_ELF */ |
f9b4148d | 10767 | |
252b5132 RH |
10768 | {NULL, no_argument, NULL, 0} |
10769 | }; | |
156c2f8b | 10770 | size_t md_longopts_size = sizeof (md_longopts); |
252b5132 | 10771 | |
316f5878 RS |
10772 | /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to |
10773 | NEW_VALUE. Warn if another value was already specified. Note: | |
10774 | we have to defer parsing the -march and -mtune arguments in order | |
10775 | to handle 'from-abi' correctly, since the ABI might be specified | |
10776 | in a later argument. */ | |
10777 | ||
10778 | static void | |
17a2f251 | 10779 | mips_set_option_string (const char **string_ptr, const char *new_value) |
316f5878 RS |
10780 | { |
10781 | if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0) | |
10782 | as_warn (_("A different %s was already specified, is now %s"), | |
10783 | string_ptr == &mips_arch_string ? "-march" : "-mtune", | |
10784 | new_value); | |
10785 | ||
10786 | *string_ptr = new_value; | |
10787 | } | |
10788 | ||
252b5132 | 10789 | int |
17a2f251 | 10790 | md_parse_option (int c, char *arg) |
252b5132 RH |
10791 | { |
10792 | switch (c) | |
10793 | { | |
119d663a NC |
10794 | case OPTION_CONSTRUCT_FLOATS: |
10795 | mips_disable_float_construction = 0; | |
10796 | break; | |
bdaaa2e1 | 10797 | |
119d663a NC |
10798 | case OPTION_NO_CONSTRUCT_FLOATS: |
10799 | mips_disable_float_construction = 1; | |
10800 | break; | |
bdaaa2e1 | 10801 | |
252b5132 RH |
10802 | case OPTION_TRAP: |
10803 | mips_trap = 1; | |
10804 | break; | |
10805 | ||
10806 | case OPTION_BREAK: | |
10807 | mips_trap = 0; | |
10808 | break; | |
10809 | ||
10810 | case OPTION_EB: | |
10811 | target_big_endian = 1; | |
10812 | break; | |
10813 | ||
10814 | case OPTION_EL: | |
10815 | target_big_endian = 0; | |
10816 | break; | |
10817 | ||
10818 | case 'O': | |
10819 | if (arg && arg[1] == '0') | |
10820 | mips_optimize = 1; | |
10821 | else | |
10822 | mips_optimize = 2; | |
10823 | break; | |
10824 | ||
10825 | case 'g': | |
10826 | if (arg == NULL) | |
10827 | mips_debug = 2; | |
10828 | else | |
10829 | mips_debug = atoi (arg); | |
10830 | /* When the MIPS assembler sees -g or -g2, it does not do | |
10831 | optimizations which limit full symbolic debugging. We take | |
10832 | that to be equivalent to -O0. */ | |
10833 | if (mips_debug == 2) | |
10834 | mips_optimize = 1; | |
10835 | break; | |
10836 | ||
10837 | case OPTION_MIPS1: | |
316f5878 | 10838 | file_mips_isa = ISA_MIPS1; |
252b5132 RH |
10839 | break; |
10840 | ||
10841 | case OPTION_MIPS2: | |
316f5878 | 10842 | file_mips_isa = ISA_MIPS2; |
252b5132 RH |
10843 | break; |
10844 | ||
10845 | case OPTION_MIPS3: | |
316f5878 | 10846 | file_mips_isa = ISA_MIPS3; |
252b5132 RH |
10847 | break; |
10848 | ||
10849 | case OPTION_MIPS4: | |
316f5878 | 10850 | file_mips_isa = ISA_MIPS4; |
e7af610e NC |
10851 | break; |
10852 | ||
84ea6cf2 | 10853 | case OPTION_MIPS5: |
316f5878 | 10854 | file_mips_isa = ISA_MIPS5; |
84ea6cf2 NC |
10855 | break; |
10856 | ||
e7af610e | 10857 | case OPTION_MIPS32: |
316f5878 | 10858 | file_mips_isa = ISA_MIPS32; |
252b5132 RH |
10859 | break; |
10860 | ||
af7ee8bf CD |
10861 | case OPTION_MIPS32R2: |
10862 | file_mips_isa = ISA_MIPS32R2; | |
10863 | break; | |
10864 | ||
5f74bc13 CD |
10865 | case OPTION_MIPS64R2: |
10866 | file_mips_isa = ISA_MIPS64R2; | |
10867 | break; | |
10868 | ||
84ea6cf2 | 10869 | case OPTION_MIPS64: |
316f5878 | 10870 | file_mips_isa = ISA_MIPS64; |
84ea6cf2 NC |
10871 | break; |
10872 | ||
ec68c924 | 10873 | case OPTION_MTUNE: |
316f5878 RS |
10874 | mips_set_option_string (&mips_tune_string, arg); |
10875 | break; | |
ec68c924 | 10876 | |
316f5878 RS |
10877 | case OPTION_MARCH: |
10878 | mips_set_option_string (&mips_arch_string, arg); | |
252b5132 RH |
10879 | break; |
10880 | ||
10881 | case OPTION_M4650: | |
316f5878 RS |
10882 | mips_set_option_string (&mips_arch_string, "4650"); |
10883 | mips_set_option_string (&mips_tune_string, "4650"); | |
252b5132 RH |
10884 | break; |
10885 | ||
10886 | case OPTION_NO_M4650: | |
10887 | break; | |
10888 | ||
10889 | case OPTION_M4010: | |
316f5878 RS |
10890 | mips_set_option_string (&mips_arch_string, "4010"); |
10891 | mips_set_option_string (&mips_tune_string, "4010"); | |
252b5132 RH |
10892 | break; |
10893 | ||
10894 | case OPTION_NO_M4010: | |
10895 | break; | |
10896 | ||
10897 | case OPTION_M4100: | |
316f5878 RS |
10898 | mips_set_option_string (&mips_arch_string, "4100"); |
10899 | mips_set_option_string (&mips_tune_string, "4100"); | |
252b5132 RH |
10900 | break; |
10901 | ||
10902 | case OPTION_NO_M4100: | |
10903 | break; | |
10904 | ||
252b5132 | 10905 | case OPTION_M3900: |
316f5878 RS |
10906 | mips_set_option_string (&mips_arch_string, "3900"); |
10907 | mips_set_option_string (&mips_tune_string, "3900"); | |
252b5132 | 10908 | break; |
bdaaa2e1 | 10909 | |
252b5132 RH |
10910 | case OPTION_NO_M3900: |
10911 | break; | |
10912 | ||
deec1734 CD |
10913 | case OPTION_MDMX: |
10914 | mips_opts.ase_mdmx = 1; | |
10915 | break; | |
10916 | ||
10917 | case OPTION_NO_MDMX: | |
10918 | mips_opts.ase_mdmx = 0; | |
10919 | break; | |
10920 | ||
74cd071d CF |
10921 | case OPTION_DSP: |
10922 | mips_opts.ase_dsp = 1; | |
10923 | break; | |
10924 | ||
10925 | case OPTION_NO_DSP: | |
10926 | mips_opts.ase_dsp = 0; | |
10927 | break; | |
10928 | ||
ef2e4d86 CF |
10929 | case OPTION_MT: |
10930 | mips_opts.ase_mt = 1; | |
10931 | break; | |
10932 | ||
10933 | case OPTION_NO_MT: | |
10934 | mips_opts.ase_mt = 0; | |
10935 | break; | |
10936 | ||
252b5132 RH |
10937 | case OPTION_MIPS16: |
10938 | mips_opts.mips16 = 1; | |
7d10b47d | 10939 | mips_no_prev_insn (); |
252b5132 RH |
10940 | break; |
10941 | ||
10942 | case OPTION_NO_MIPS16: | |
10943 | mips_opts.mips16 = 0; | |
7d10b47d | 10944 | mips_no_prev_insn (); |
252b5132 RH |
10945 | break; |
10946 | ||
1f25f5d3 CD |
10947 | case OPTION_MIPS3D: |
10948 | mips_opts.ase_mips3d = 1; | |
10949 | break; | |
10950 | ||
10951 | case OPTION_NO_MIPS3D: | |
10952 | mips_opts.ase_mips3d = 0; | |
10953 | break; | |
10954 | ||
e16bfa71 TS |
10955 | case OPTION_SMARTMIPS: |
10956 | mips_opts.ase_smartmips = 1; | |
10957 | break; | |
10958 | ||
10959 | case OPTION_NO_SMARTMIPS: | |
10960 | mips_opts.ase_smartmips = 0; | |
10961 | break; | |
10962 | ||
d766e8ec RS |
10963 | case OPTION_FIX_VR4120: |
10964 | mips_fix_vr4120 = 1; | |
60b63b72 RS |
10965 | break; |
10966 | ||
d766e8ec RS |
10967 | case OPTION_NO_FIX_VR4120: |
10968 | mips_fix_vr4120 = 0; | |
60b63b72 RS |
10969 | break; |
10970 | ||
7d8e00cf RS |
10971 | case OPTION_FIX_VR4130: |
10972 | mips_fix_vr4130 = 1; | |
10973 | break; | |
10974 | ||
10975 | case OPTION_NO_FIX_VR4130: | |
10976 | mips_fix_vr4130 = 0; | |
10977 | break; | |
10978 | ||
4a6a3df4 AO |
10979 | case OPTION_RELAX_BRANCH: |
10980 | mips_relax_branch = 1; | |
10981 | break; | |
10982 | ||
10983 | case OPTION_NO_RELAX_BRANCH: | |
10984 | mips_relax_branch = 0; | |
10985 | break; | |
10986 | ||
aa6975fb ILT |
10987 | case OPTION_MSHARED: |
10988 | mips_in_shared = TRUE; | |
10989 | break; | |
10990 | ||
10991 | case OPTION_MNO_SHARED: | |
10992 | mips_in_shared = FALSE; | |
10993 | break; | |
10994 | ||
aed1a261 RS |
10995 | case OPTION_MSYM32: |
10996 | mips_opts.sym32 = TRUE; | |
10997 | break; | |
10998 | ||
10999 | case OPTION_MNO_SYM32: | |
11000 | mips_opts.sym32 = FALSE; | |
11001 | break; | |
11002 | ||
0f074f60 | 11003 | #ifdef OBJ_ELF |
252b5132 RH |
11004 | /* When generating ELF code, we permit -KPIC and -call_shared to |
11005 | select SVR4_PIC, and -non_shared to select no PIC. This is | |
11006 | intended to be compatible with Irix 5. */ | |
11007 | case OPTION_CALL_SHARED: | |
11008 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
11009 | { | |
11010 | as_bad (_("-call_shared is supported only for ELF format")); | |
11011 | return 0; | |
11012 | } | |
11013 | mips_pic = SVR4_PIC; | |
143d77c5 | 11014 | mips_abicalls = TRUE; |
252b5132 RH |
11015 | break; |
11016 | ||
11017 | case OPTION_NON_SHARED: | |
11018 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
11019 | { | |
11020 | as_bad (_("-non_shared is supported only for ELF format")); | |
11021 | return 0; | |
11022 | } | |
11023 | mips_pic = NO_PIC; | |
143d77c5 | 11024 | mips_abicalls = FALSE; |
252b5132 RH |
11025 | break; |
11026 | ||
44075ae2 TS |
11027 | /* The -xgot option tells the assembler to use 32 bit offsets |
11028 | when accessing the got in SVR4_PIC mode. It is for Irix | |
252b5132 RH |
11029 | compatibility. */ |
11030 | case OPTION_XGOT: | |
11031 | mips_big_got = 1; | |
11032 | break; | |
0f074f60 | 11033 | #endif /* OBJ_ELF */ |
252b5132 RH |
11034 | |
11035 | case 'G': | |
6caf9ef4 TS |
11036 | g_switch_value = atoi (arg); |
11037 | g_switch_seen = 1; | |
252b5132 RH |
11038 | break; |
11039 | ||
0f074f60 | 11040 | #ifdef OBJ_ELF |
34ba82a8 TS |
11041 | /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32 |
11042 | and -mabi=64. */ | |
252b5132 | 11043 | case OPTION_32: |
34ba82a8 TS |
11044 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
11045 | { | |
11046 | as_bad (_("-32 is supported for ELF format only")); | |
11047 | return 0; | |
11048 | } | |
316f5878 | 11049 | mips_abi = O32_ABI; |
252b5132 RH |
11050 | break; |
11051 | ||
e013f690 | 11052 | case OPTION_N32: |
34ba82a8 TS |
11053 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
11054 | { | |
11055 | as_bad (_("-n32 is supported for ELF format only")); | |
11056 | return 0; | |
11057 | } | |
316f5878 | 11058 | mips_abi = N32_ABI; |
e013f690 | 11059 | break; |
252b5132 | 11060 | |
e013f690 | 11061 | case OPTION_64: |
34ba82a8 TS |
11062 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
11063 | { | |
11064 | as_bad (_("-64 is supported for ELF format only")); | |
11065 | return 0; | |
11066 | } | |
316f5878 | 11067 | mips_abi = N64_ABI; |
e013f690 TS |
11068 | if (! support_64bit_objects()) |
11069 | as_fatal (_("No compiled in support for 64 bit object file format")); | |
252b5132 | 11070 | break; |
ae948b86 | 11071 | #endif /* OBJ_ELF */ |
252b5132 | 11072 | |
c97ef257 | 11073 | case OPTION_GP32: |
a325df1d | 11074 | file_mips_gp32 = 1; |
c97ef257 AH |
11075 | break; |
11076 | ||
11077 | case OPTION_GP64: | |
a325df1d | 11078 | file_mips_gp32 = 0; |
c97ef257 | 11079 | break; |
252b5132 | 11080 | |
ca4e0257 | 11081 | case OPTION_FP32: |
a325df1d | 11082 | file_mips_fp32 = 1; |
316f5878 RS |
11083 | break; |
11084 | ||
11085 | case OPTION_FP64: | |
11086 | file_mips_fp32 = 0; | |
ca4e0257 RS |
11087 | break; |
11088 | ||
ae948b86 | 11089 | #ifdef OBJ_ELF |
252b5132 | 11090 | case OPTION_MABI: |
34ba82a8 TS |
11091 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
11092 | { | |
11093 | as_bad (_("-mabi is supported for ELF format only")); | |
11094 | return 0; | |
11095 | } | |
e013f690 | 11096 | if (strcmp (arg, "32") == 0) |
316f5878 | 11097 | mips_abi = O32_ABI; |
e013f690 | 11098 | else if (strcmp (arg, "o64") == 0) |
316f5878 | 11099 | mips_abi = O64_ABI; |
e013f690 | 11100 | else if (strcmp (arg, "n32") == 0) |
316f5878 | 11101 | mips_abi = N32_ABI; |
e013f690 TS |
11102 | else if (strcmp (arg, "64") == 0) |
11103 | { | |
316f5878 | 11104 | mips_abi = N64_ABI; |
e013f690 TS |
11105 | if (! support_64bit_objects()) |
11106 | as_fatal (_("No compiled in support for 64 bit object file " | |
11107 | "format")); | |
11108 | } | |
11109 | else if (strcmp (arg, "eabi") == 0) | |
316f5878 | 11110 | mips_abi = EABI_ABI; |
e013f690 | 11111 | else |
da0e507f TS |
11112 | { |
11113 | as_fatal (_("invalid abi -mabi=%s"), arg); | |
11114 | return 0; | |
11115 | } | |
252b5132 | 11116 | break; |
e013f690 | 11117 | #endif /* OBJ_ELF */ |
252b5132 | 11118 | |
6b76fefe | 11119 | case OPTION_M7000_HILO_FIX: |
b34976b6 | 11120 | mips_7000_hilo_fix = TRUE; |
6b76fefe CM |
11121 | break; |
11122 | ||
9ee72ff1 | 11123 | case OPTION_MNO_7000_HILO_FIX: |
b34976b6 | 11124 | mips_7000_hilo_fix = FALSE; |
6b76fefe CM |
11125 | break; |
11126 | ||
ecb4347a DJ |
11127 | #ifdef OBJ_ELF |
11128 | case OPTION_MDEBUG: | |
b34976b6 | 11129 | mips_flag_mdebug = TRUE; |
ecb4347a DJ |
11130 | break; |
11131 | ||
11132 | case OPTION_NO_MDEBUG: | |
b34976b6 | 11133 | mips_flag_mdebug = FALSE; |
ecb4347a | 11134 | break; |
dcd410fe RO |
11135 | |
11136 | case OPTION_PDR: | |
11137 | mips_flag_pdr = TRUE; | |
11138 | break; | |
11139 | ||
11140 | case OPTION_NO_PDR: | |
11141 | mips_flag_pdr = FALSE; | |
11142 | break; | |
0a44bf69 RS |
11143 | |
11144 | case OPTION_MVXWORKS_PIC: | |
11145 | mips_pic = VXWORKS_PIC; | |
11146 | break; | |
ecb4347a DJ |
11147 | #endif /* OBJ_ELF */ |
11148 | ||
252b5132 RH |
11149 | default: |
11150 | return 0; | |
11151 | } | |
11152 | ||
11153 | return 1; | |
11154 | } | |
316f5878 RS |
11155 | \f |
11156 | /* Set up globals to generate code for the ISA or processor | |
11157 | described by INFO. */ | |
252b5132 | 11158 | |
252b5132 | 11159 | static void |
17a2f251 | 11160 | mips_set_architecture (const struct mips_cpu_info *info) |
252b5132 | 11161 | { |
316f5878 | 11162 | if (info != 0) |
252b5132 | 11163 | { |
fef14a42 TS |
11164 | file_mips_arch = info->cpu; |
11165 | mips_opts.arch = info->cpu; | |
316f5878 | 11166 | mips_opts.isa = info->isa; |
252b5132 | 11167 | } |
252b5132 RH |
11168 | } |
11169 | ||
252b5132 | 11170 | |
316f5878 | 11171 | /* Likewise for tuning. */ |
252b5132 | 11172 | |
316f5878 | 11173 | static void |
17a2f251 | 11174 | mips_set_tune (const struct mips_cpu_info *info) |
316f5878 RS |
11175 | { |
11176 | if (info != 0) | |
fef14a42 | 11177 | mips_tune = info->cpu; |
316f5878 | 11178 | } |
80cc45a5 | 11179 | |
34ba82a8 | 11180 | |
252b5132 | 11181 | void |
17a2f251 | 11182 | mips_after_parse_args (void) |
e9670677 | 11183 | { |
fef14a42 TS |
11184 | const struct mips_cpu_info *arch_info = 0; |
11185 | const struct mips_cpu_info *tune_info = 0; | |
11186 | ||
e9670677 | 11187 | /* GP relative stuff not working for PE */ |
6caf9ef4 | 11188 | if (strncmp (TARGET_OS, "pe", 2) == 0) |
e9670677 | 11189 | { |
6caf9ef4 | 11190 | if (g_switch_seen && g_switch_value != 0) |
e9670677 MR |
11191 | as_bad (_("-G not supported in this configuration.")); |
11192 | g_switch_value = 0; | |
11193 | } | |
11194 | ||
cac012d6 AO |
11195 | if (mips_abi == NO_ABI) |
11196 | mips_abi = MIPS_DEFAULT_ABI; | |
11197 | ||
22923709 RS |
11198 | /* The following code determines the architecture and register size. |
11199 | Similar code was added to GCC 3.3 (see override_options() in | |
11200 | config/mips/mips.c). The GAS and GCC code should be kept in sync | |
11201 | as much as possible. */ | |
e9670677 | 11202 | |
316f5878 | 11203 | if (mips_arch_string != 0) |
fef14a42 | 11204 | arch_info = mips_parse_cpu ("-march", mips_arch_string); |
e9670677 | 11205 | |
316f5878 | 11206 | if (file_mips_isa != ISA_UNKNOWN) |
e9670677 | 11207 | { |
316f5878 | 11208 | /* Handle -mipsN. At this point, file_mips_isa contains the |
fef14a42 | 11209 | ISA level specified by -mipsN, while arch_info->isa contains |
316f5878 | 11210 | the -march selection (if any). */ |
fef14a42 | 11211 | if (arch_info != 0) |
e9670677 | 11212 | { |
316f5878 RS |
11213 | /* -march takes precedence over -mipsN, since it is more descriptive. |
11214 | There's no harm in specifying both as long as the ISA levels | |
11215 | are the same. */ | |
fef14a42 | 11216 | if (file_mips_isa != arch_info->isa) |
316f5878 RS |
11217 | as_bad (_("-%s conflicts with the other architecture options, which imply -%s"), |
11218 | mips_cpu_info_from_isa (file_mips_isa)->name, | |
fef14a42 | 11219 | mips_cpu_info_from_isa (arch_info->isa)->name); |
e9670677 | 11220 | } |
316f5878 | 11221 | else |
fef14a42 | 11222 | arch_info = mips_cpu_info_from_isa (file_mips_isa); |
e9670677 MR |
11223 | } |
11224 | ||
fef14a42 TS |
11225 | if (arch_info == 0) |
11226 | arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT); | |
e9670677 | 11227 | |
fef14a42 | 11228 | if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa)) |
316f5878 | 11229 | as_bad ("-march=%s is not compatible with the selected ABI", |
fef14a42 TS |
11230 | arch_info->name); |
11231 | ||
11232 | mips_set_architecture (arch_info); | |
11233 | ||
11234 | /* Optimize for file_mips_arch, unless -mtune selects a different processor. */ | |
11235 | if (mips_tune_string != 0) | |
11236 | tune_info = mips_parse_cpu ("-mtune", mips_tune_string); | |
e9670677 | 11237 | |
fef14a42 TS |
11238 | if (tune_info == 0) |
11239 | mips_set_tune (arch_info); | |
11240 | else | |
11241 | mips_set_tune (tune_info); | |
e9670677 | 11242 | |
316f5878 | 11243 | if (file_mips_gp32 >= 0) |
e9670677 | 11244 | { |
316f5878 RS |
11245 | /* The user specified the size of the integer registers. Make sure |
11246 | it agrees with the ABI and ISA. */ | |
11247 | if (file_mips_gp32 == 0 && !ISA_HAS_64BIT_REGS (mips_opts.isa)) | |
11248 | as_bad (_("-mgp64 used with a 32-bit processor")); | |
11249 | else if (file_mips_gp32 == 1 && ABI_NEEDS_64BIT_REGS (mips_abi)) | |
11250 | as_bad (_("-mgp32 used with a 64-bit ABI")); | |
11251 | else if (file_mips_gp32 == 0 && ABI_NEEDS_32BIT_REGS (mips_abi)) | |
11252 | as_bad (_("-mgp64 used with a 32-bit ABI")); | |
e9670677 MR |
11253 | } |
11254 | else | |
11255 | { | |
316f5878 RS |
11256 | /* Infer the integer register size from the ABI and processor. |
11257 | Restrict ourselves to 32-bit registers if that's all the | |
11258 | processor has, or if the ABI cannot handle 64-bit registers. */ | |
11259 | file_mips_gp32 = (ABI_NEEDS_32BIT_REGS (mips_abi) | |
11260 | || !ISA_HAS_64BIT_REGS (mips_opts.isa)); | |
e9670677 MR |
11261 | } |
11262 | ||
316f5878 RS |
11263 | /* ??? GAS treats single-float processors as though they had 64-bit |
11264 | float registers (although it complains when double-precision | |
11265 | instructions are used). As things stand, saying they have 32-bit | |
11266 | registers would lead to spurious "register must be even" messages. | |
11267 | So here we assume float registers are always the same size as | |
11268 | integer ones, unless the user says otherwise. */ | |
11269 | if (file_mips_fp32 < 0) | |
11270 | file_mips_fp32 = file_mips_gp32; | |
e9670677 | 11271 | |
316f5878 | 11272 | /* End of GCC-shared inference code. */ |
e9670677 | 11273 | |
17a2f251 TS |
11274 | /* This flag is set when we have a 64-bit capable CPU but use only |
11275 | 32-bit wide registers. Note that EABI does not use it. */ | |
11276 | if (ISA_HAS_64BIT_REGS (mips_opts.isa) | |
11277 | && ((mips_abi == NO_ABI && file_mips_gp32 == 1) | |
11278 | || mips_abi == O32_ABI)) | |
316f5878 | 11279 | mips_32bitmode = 1; |
e9670677 MR |
11280 | |
11281 | if (mips_opts.isa == ISA_MIPS1 && mips_trap) | |
11282 | as_bad (_("trap exception not supported at ISA 1")); | |
11283 | ||
e9670677 MR |
11284 | /* If the selected architecture includes support for ASEs, enable |
11285 | generation of code for them. */ | |
a4672219 | 11286 | if (mips_opts.mips16 == -1) |
fef14a42 | 11287 | mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_arch)) ? 1 : 0; |
ffdefa66 | 11288 | if (mips_opts.ase_mips3d == -1) |
fef14a42 | 11289 | mips_opts.ase_mips3d = (CPU_HAS_MIPS3D (file_mips_arch)) ? 1 : 0; |
ffdefa66 | 11290 | if (mips_opts.ase_mdmx == -1) |
fef14a42 | 11291 | mips_opts.ase_mdmx = (CPU_HAS_MDMX (file_mips_arch)) ? 1 : 0; |
74cd071d CF |
11292 | if (mips_opts.ase_dsp == -1) |
11293 | mips_opts.ase_dsp = (CPU_HAS_DSP (file_mips_arch)) ? 1 : 0; | |
ef2e4d86 CF |
11294 | if (mips_opts.ase_mt == -1) |
11295 | mips_opts.ase_mt = (CPU_HAS_MT (file_mips_arch)) ? 1 : 0; | |
e9670677 | 11296 | |
e9670677 | 11297 | file_mips_isa = mips_opts.isa; |
a4672219 | 11298 | file_ase_mips16 = mips_opts.mips16; |
e9670677 MR |
11299 | file_ase_mips3d = mips_opts.ase_mips3d; |
11300 | file_ase_mdmx = mips_opts.ase_mdmx; | |
e16bfa71 | 11301 | file_ase_smartmips = mips_opts.ase_smartmips; |
74cd071d | 11302 | file_ase_dsp = mips_opts.ase_dsp; |
ef2e4d86 | 11303 | file_ase_mt = mips_opts.ase_mt; |
e9670677 MR |
11304 | mips_opts.gp32 = file_mips_gp32; |
11305 | mips_opts.fp32 = file_mips_fp32; | |
11306 | ||
ecb4347a DJ |
11307 | if (mips_flag_mdebug < 0) |
11308 | { | |
11309 | #ifdef OBJ_MAYBE_ECOFF | |
11310 | if (OUTPUT_FLAVOR == bfd_target_ecoff_flavour) | |
11311 | mips_flag_mdebug = 1; | |
11312 | else | |
11313 | #endif /* OBJ_MAYBE_ECOFF */ | |
11314 | mips_flag_mdebug = 0; | |
11315 | } | |
e9670677 MR |
11316 | } |
11317 | \f | |
11318 | void | |
17a2f251 | 11319 | mips_init_after_args (void) |
252b5132 RH |
11320 | { |
11321 | /* initialize opcodes */ | |
11322 | bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes; | |
beae10d5 | 11323 | mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes; |
252b5132 RH |
11324 | } |
11325 | ||
11326 | long | |
17a2f251 | 11327 | md_pcrel_from (fixS *fixP) |
252b5132 | 11328 | { |
a7ebbfdf TS |
11329 | valueT addr = fixP->fx_where + fixP->fx_frag->fr_address; |
11330 | switch (fixP->fx_r_type) | |
11331 | { | |
11332 | case BFD_RELOC_16_PCREL_S2: | |
11333 | case BFD_RELOC_MIPS_JMP: | |
11334 | /* Return the address of the delay slot. */ | |
11335 | return addr + 4; | |
11336 | default: | |
11337 | return addr; | |
11338 | } | |
252b5132 RH |
11339 | } |
11340 | ||
252b5132 RH |
11341 | /* This is called before the symbol table is processed. In order to |
11342 | work with gcc when using mips-tfile, we must keep all local labels. | |
11343 | However, in other cases, we want to discard them. If we were | |
11344 | called with -g, but we didn't see any debugging information, it may | |
11345 | mean that gcc is smuggling debugging information through to | |
11346 | mips-tfile, in which case we must generate all local labels. */ | |
11347 | ||
11348 | void | |
17a2f251 | 11349 | mips_frob_file_before_adjust (void) |
252b5132 RH |
11350 | { |
11351 | #ifndef NO_ECOFF_DEBUGGING | |
11352 | if (ECOFF_DEBUGGING | |
11353 | && mips_debug != 0 | |
11354 | && ! ecoff_debugging_seen) | |
11355 | flag_keep_locals = 1; | |
11356 | #endif | |
11357 | } | |
11358 | ||
3b91255e | 11359 | /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede |
55cf6793 | 11360 | the corresponding LO16 reloc. This is called before md_apply_fix and |
3b91255e RS |
11361 | tc_gen_reloc. Unmatched relocs can only be generated by use of explicit |
11362 | relocation operators. | |
11363 | ||
11364 | For our purposes, a %lo() expression matches a %got() or %hi() | |
11365 | expression if: | |
11366 | ||
11367 | (a) it refers to the same symbol; and | |
11368 | (b) the offset applied in the %lo() expression is no lower than | |
11369 | the offset applied in the %got() or %hi(). | |
11370 | ||
11371 | (b) allows us to cope with code like: | |
11372 | ||
11373 | lui $4,%hi(foo) | |
11374 | lh $4,%lo(foo+2)($4) | |
11375 | ||
11376 | ...which is legal on RELA targets, and has a well-defined behaviour | |
11377 | if the user knows that adding 2 to "foo" will not induce a carry to | |
11378 | the high 16 bits. | |
11379 | ||
11380 | When several %lo()s match a particular %got() or %hi(), we use the | |
11381 | following rules to distinguish them: | |
11382 | ||
11383 | (1) %lo()s with smaller offsets are a better match than %lo()s with | |
11384 | higher offsets. | |
11385 | ||
11386 | (2) %lo()s with no matching %got() or %hi() are better than those | |
11387 | that already have a matching %got() or %hi(). | |
11388 | ||
11389 | (3) later %lo()s are better than earlier %lo()s. | |
11390 | ||
11391 | These rules are applied in order. | |
11392 | ||
11393 | (1) means, among other things, that %lo()s with identical offsets are | |
11394 | chosen if they exist. | |
11395 | ||
11396 | (2) means that we won't associate several high-part relocations with | |
11397 | the same low-part relocation unless there's no alternative. Having | |
11398 | several high parts for the same low part is a GNU extension; this rule | |
11399 | allows careful users to avoid it. | |
11400 | ||
11401 | (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order, | |
11402 | with the last high-part relocation being at the front of the list. | |
11403 | It therefore makes sense to choose the last matching low-part | |
11404 | relocation, all other things being equal. It's also easier | |
11405 | to code that way. */ | |
252b5132 RH |
11406 | |
11407 | void | |
17a2f251 | 11408 | mips_frob_file (void) |
252b5132 RH |
11409 | { |
11410 | struct mips_hi_fixup *l; | |
11411 | ||
11412 | for (l = mips_hi_fixup_list; l != NULL; l = l->next) | |
11413 | { | |
11414 | segment_info_type *seginfo; | |
3b91255e RS |
11415 | bfd_boolean matched_lo_p; |
11416 | fixS **hi_pos, **lo_pos, **pos; | |
252b5132 | 11417 | |
5919d012 | 11418 | assert (reloc_needs_lo_p (l->fixp->fx_r_type)); |
252b5132 | 11419 | |
5919d012 RS |
11420 | /* If a GOT16 relocation turns out to be against a global symbol, |
11421 | there isn't supposed to be a matching LO. */ | |
11422 | if (l->fixp->fx_r_type == BFD_RELOC_MIPS_GOT16 | |
11423 | && !pic_need_relax (l->fixp->fx_addsy, l->seg)) | |
11424 | continue; | |
11425 | ||
11426 | /* Check quickly whether the next fixup happens to be a matching %lo. */ | |
11427 | if (fixup_has_matching_lo_p (l->fixp)) | |
252b5132 RH |
11428 | continue; |
11429 | ||
252b5132 | 11430 | seginfo = seg_info (l->seg); |
252b5132 | 11431 | |
3b91255e RS |
11432 | /* Set HI_POS to the position of this relocation in the chain. |
11433 | Set LO_POS to the position of the chosen low-part relocation. | |
11434 | MATCHED_LO_P is true on entry to the loop if *POS is a low-part | |
11435 | relocation that matches an immediately-preceding high-part | |
11436 | relocation. */ | |
11437 | hi_pos = NULL; | |
11438 | lo_pos = NULL; | |
11439 | matched_lo_p = FALSE; | |
11440 | for (pos = &seginfo->fix_root; *pos != NULL; pos = &(*pos)->fx_next) | |
11441 | { | |
11442 | if (*pos == l->fixp) | |
11443 | hi_pos = pos; | |
11444 | ||
704803a9 MR |
11445 | if (((*pos)->fx_r_type == BFD_RELOC_LO16 |
11446 | || (*pos)->fx_r_type == BFD_RELOC_MIPS16_LO16) | |
3b91255e RS |
11447 | && (*pos)->fx_addsy == l->fixp->fx_addsy |
11448 | && (*pos)->fx_offset >= l->fixp->fx_offset | |
11449 | && (lo_pos == NULL | |
11450 | || (*pos)->fx_offset < (*lo_pos)->fx_offset | |
11451 | || (!matched_lo_p | |
11452 | && (*pos)->fx_offset == (*lo_pos)->fx_offset))) | |
11453 | lo_pos = pos; | |
11454 | ||
11455 | matched_lo_p = (reloc_needs_lo_p ((*pos)->fx_r_type) | |
11456 | && fixup_has_matching_lo_p (*pos)); | |
11457 | } | |
11458 | ||
11459 | /* If we found a match, remove the high-part relocation from its | |
11460 | current position and insert it before the low-part relocation. | |
11461 | Make the offsets match so that fixup_has_matching_lo_p() | |
11462 | will return true. | |
11463 | ||
11464 | We don't warn about unmatched high-part relocations since some | |
11465 | versions of gcc have been known to emit dead "lui ...%hi(...)" | |
11466 | instructions. */ | |
11467 | if (lo_pos != NULL) | |
11468 | { | |
11469 | l->fixp->fx_offset = (*lo_pos)->fx_offset; | |
11470 | if (l->fixp->fx_next != *lo_pos) | |
252b5132 | 11471 | { |
3b91255e RS |
11472 | *hi_pos = l->fixp->fx_next; |
11473 | l->fixp->fx_next = *lo_pos; | |
11474 | *lo_pos = l->fixp; | |
252b5132 | 11475 | } |
252b5132 RH |
11476 | } |
11477 | } | |
11478 | } | |
11479 | ||
3e722fb5 | 11480 | /* We may have combined relocations without symbols in the N32/N64 ABI. |
f6688943 | 11481 | We have to prevent gas from dropping them. */ |
252b5132 | 11482 | |
252b5132 | 11483 | int |
17a2f251 | 11484 | mips_force_relocation (fixS *fixp) |
252b5132 | 11485 | { |
ae6063d4 | 11486 | if (generic_force_reloc (fixp)) |
252b5132 RH |
11487 | return 1; |
11488 | ||
f6688943 TS |
11489 | if (HAVE_NEWABI |
11490 | && S_GET_SEGMENT (fixp->fx_addsy) == bfd_abs_section_ptr | |
11491 | && (fixp->fx_r_type == BFD_RELOC_MIPS_SUB | |
11492 | || fixp->fx_r_type == BFD_RELOC_HI16_S | |
11493 | || fixp->fx_r_type == BFD_RELOC_LO16)) | |
11494 | return 1; | |
11495 | ||
3e722fb5 | 11496 | return 0; |
252b5132 RH |
11497 | } |
11498 | ||
11499 | /* Apply a fixup to the object file. */ | |
11500 | ||
94f592af | 11501 | void |
55cf6793 | 11502 | md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) |
252b5132 | 11503 | { |
874e8986 | 11504 | bfd_byte *buf; |
98aa84af | 11505 | long insn; |
a7ebbfdf | 11506 | reloc_howto_type *howto; |
252b5132 | 11507 | |
a7ebbfdf TS |
11508 | /* We ignore generic BFD relocations we don't know about. */ |
11509 | howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type); | |
11510 | if (! howto) | |
11511 | return; | |
65551fa4 | 11512 | |
252b5132 RH |
11513 | assert (fixP->fx_size == 4 |
11514 | || fixP->fx_r_type == BFD_RELOC_16 | |
11515 | || fixP->fx_r_type == BFD_RELOC_64 | |
f6688943 TS |
11516 | || fixP->fx_r_type == BFD_RELOC_CTOR |
11517 | || fixP->fx_r_type == BFD_RELOC_MIPS_SUB | |
252b5132 | 11518 | || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
a7ebbfdf | 11519 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY); |
252b5132 | 11520 | |
a7ebbfdf | 11521 | buf = (bfd_byte *) (fixP->fx_frag->fr_literal + fixP->fx_where); |
252b5132 | 11522 | |
bad36eac | 11523 | assert (! fixP->fx_pcrel || fixP->fx_r_type == BFD_RELOC_16_PCREL_S2); |
b1dca8ee RS |
11524 | |
11525 | /* Don't treat parts of a composite relocation as done. There are two | |
11526 | reasons for this: | |
11527 | ||
11528 | (1) The second and third parts will be against 0 (RSS_UNDEF) but | |
11529 | should nevertheless be emitted if the first part is. | |
11530 | ||
11531 | (2) In normal usage, composite relocations are never assembly-time | |
11532 | constants. The easiest way of dealing with the pathological | |
11533 | exceptions is to generate a relocation against STN_UNDEF and | |
11534 | leave everything up to the linker. */ | |
bad36eac | 11535 | if (fixP->fx_addsy == NULL && ! fixP->fx_pcrel && fixP->fx_tcbit == 0) |
252b5132 RH |
11536 | fixP->fx_done = 1; |
11537 | ||
11538 | switch (fixP->fx_r_type) | |
11539 | { | |
3f98094e DJ |
11540 | case BFD_RELOC_MIPS_TLS_GD: |
11541 | case BFD_RELOC_MIPS_TLS_LDM: | |
11542 | case BFD_RELOC_MIPS_TLS_DTPREL_HI16: | |
11543 | case BFD_RELOC_MIPS_TLS_DTPREL_LO16: | |
11544 | case BFD_RELOC_MIPS_TLS_GOTTPREL: | |
11545 | case BFD_RELOC_MIPS_TLS_TPREL_HI16: | |
11546 | case BFD_RELOC_MIPS_TLS_TPREL_LO16: | |
11547 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
11548 | /* fall through */ | |
11549 | ||
252b5132 | 11550 | case BFD_RELOC_MIPS_JMP: |
e369bcce TS |
11551 | case BFD_RELOC_MIPS_SHIFT5: |
11552 | case BFD_RELOC_MIPS_SHIFT6: | |
11553 | case BFD_RELOC_MIPS_GOT_DISP: | |
11554 | case BFD_RELOC_MIPS_GOT_PAGE: | |
11555 | case BFD_RELOC_MIPS_GOT_OFST: | |
11556 | case BFD_RELOC_MIPS_SUB: | |
11557 | case BFD_RELOC_MIPS_INSERT_A: | |
11558 | case BFD_RELOC_MIPS_INSERT_B: | |
11559 | case BFD_RELOC_MIPS_DELETE: | |
11560 | case BFD_RELOC_MIPS_HIGHEST: | |
11561 | case BFD_RELOC_MIPS_HIGHER: | |
11562 | case BFD_RELOC_MIPS_SCN_DISP: | |
11563 | case BFD_RELOC_MIPS_REL16: | |
11564 | case BFD_RELOC_MIPS_RELGOT: | |
11565 | case BFD_RELOC_MIPS_JALR: | |
252b5132 RH |
11566 | case BFD_RELOC_HI16: |
11567 | case BFD_RELOC_HI16_S: | |
cdf6fd85 | 11568 | case BFD_RELOC_GPREL16: |
252b5132 RH |
11569 | case BFD_RELOC_MIPS_LITERAL: |
11570 | case BFD_RELOC_MIPS_CALL16: | |
11571 | case BFD_RELOC_MIPS_GOT16: | |
cdf6fd85 | 11572 | case BFD_RELOC_GPREL32: |
252b5132 RH |
11573 | case BFD_RELOC_MIPS_GOT_HI16: |
11574 | case BFD_RELOC_MIPS_GOT_LO16: | |
11575 | case BFD_RELOC_MIPS_CALL_HI16: | |
11576 | case BFD_RELOC_MIPS_CALL_LO16: | |
11577 | case BFD_RELOC_MIPS16_GPREL: | |
d6f16593 MR |
11578 | case BFD_RELOC_MIPS16_HI16: |
11579 | case BFD_RELOC_MIPS16_HI16_S: | |
252b5132 RH |
11580 | /* Nothing needed to do. The value comes from the reloc entry */ |
11581 | break; | |
11582 | ||
11583 | case BFD_RELOC_MIPS16_JMP: | |
11584 | /* We currently always generate a reloc against a symbol, which | |
11585 | means that we don't want an addend even if the symbol is | |
11586 | defined. */ | |
a7ebbfdf | 11587 | *valP = 0; |
252b5132 RH |
11588 | break; |
11589 | ||
252b5132 RH |
11590 | case BFD_RELOC_64: |
11591 | /* This is handled like BFD_RELOC_32, but we output a sign | |
11592 | extended value if we are only 32 bits. */ | |
3e722fb5 | 11593 | if (fixP->fx_done) |
252b5132 RH |
11594 | { |
11595 | if (8 <= sizeof (valueT)) | |
2132e3a3 | 11596 | md_number_to_chars ((char *) buf, *valP, 8); |
252b5132 RH |
11597 | else |
11598 | { | |
a7ebbfdf | 11599 | valueT hiv; |
252b5132 | 11600 | |
a7ebbfdf | 11601 | if ((*valP & 0x80000000) != 0) |
252b5132 RH |
11602 | hiv = 0xffffffff; |
11603 | else | |
11604 | hiv = 0; | |
b215186b | 11605 | md_number_to_chars ((char *)(buf + (target_big_endian ? 4 : 0)), |
a7ebbfdf | 11606 | *valP, 4); |
b215186b | 11607 | md_number_to_chars ((char *)(buf + (target_big_endian ? 0 : 4)), |
a7ebbfdf | 11608 | hiv, 4); |
252b5132 RH |
11609 | } |
11610 | } | |
11611 | break; | |
11612 | ||
056350c6 | 11613 | case BFD_RELOC_RVA: |
252b5132 RH |
11614 | case BFD_RELOC_32: |
11615 | /* If we are deleting this reloc entry, we must fill in the | |
11616 | value now. This can happen if we have a .word which is not | |
3e722fb5 CD |
11617 | resolved when it appears but is later defined. */ |
11618 | if (fixP->fx_done) | |
2132e3a3 | 11619 | md_number_to_chars ((char *) buf, *valP, 4); |
252b5132 RH |
11620 | break; |
11621 | ||
11622 | case BFD_RELOC_16: | |
11623 | /* If we are deleting this reloc entry, we must fill in the | |
11624 | value now. */ | |
252b5132 | 11625 | if (fixP->fx_done) |
2132e3a3 | 11626 | md_number_to_chars ((char *) buf, *valP, 2); |
252b5132 RH |
11627 | break; |
11628 | ||
11629 | case BFD_RELOC_LO16: | |
d6f16593 | 11630 | case BFD_RELOC_MIPS16_LO16: |
3e722fb5 CD |
11631 | /* FIXME: Now that embedded-PIC is gone, some of this code/comment |
11632 | may be safe to remove, but if so it's not obvious. */ | |
252b5132 RH |
11633 | /* When handling an embedded PIC switch statement, we can wind |
11634 | up deleting a LO16 reloc. See the 'o' case in mips_ip. */ | |
11635 | if (fixP->fx_done) | |
11636 | { | |
a7ebbfdf | 11637 | if (*valP + 0x8000 > 0xffff) |
252b5132 RH |
11638 | as_bad_where (fixP->fx_file, fixP->fx_line, |
11639 | _("relocation overflow")); | |
252b5132 RH |
11640 | if (target_big_endian) |
11641 | buf += 2; | |
2132e3a3 | 11642 | md_number_to_chars ((char *) buf, *valP, 2); |
252b5132 RH |
11643 | } |
11644 | break; | |
11645 | ||
11646 | case BFD_RELOC_16_PCREL_S2: | |
a7ebbfdf | 11647 | if ((*valP & 0x3) != 0) |
cb56d3d3 | 11648 | as_bad_where (fixP->fx_file, fixP->fx_line, |
bad36eac | 11649 | _("Branch to misaligned address (%lx)"), (long) *valP); |
cb56d3d3 | 11650 | |
252b5132 RH |
11651 | /* |
11652 | * We need to save the bits in the instruction since fixup_segment() | |
11653 | * might be deleting the relocation entry (i.e., a branch within | |
11654 | * the current segment). | |
11655 | */ | |
a7ebbfdf | 11656 | if (! fixP->fx_done) |
bb2d6cd7 | 11657 | break; |
252b5132 RH |
11658 | |
11659 | /* update old instruction data */ | |
252b5132 RH |
11660 | if (target_big_endian) |
11661 | insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3]; | |
11662 | else | |
11663 | insn = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0]; | |
11664 | ||
a7ebbfdf TS |
11665 | if (*valP + 0x20000 <= 0x3ffff) |
11666 | { | |
11667 | insn |= (*valP >> 2) & 0xffff; | |
2132e3a3 | 11668 | md_number_to_chars ((char *) buf, insn, 4); |
a7ebbfdf TS |
11669 | } |
11670 | else if (mips_pic == NO_PIC | |
11671 | && fixP->fx_done | |
11672 | && fixP->fx_frag->fr_address >= text_section->vma | |
11673 | && (fixP->fx_frag->fr_address | |
587aac4e | 11674 | < text_section->vma + bfd_get_section_size (text_section)) |
a7ebbfdf TS |
11675 | && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */ |
11676 | || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */ | |
11677 | || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */ | |
252b5132 RH |
11678 | { |
11679 | /* The branch offset is too large. If this is an | |
11680 | unconditional branch, and we are not generating PIC code, | |
11681 | we can convert it to an absolute jump instruction. */ | |
a7ebbfdf TS |
11682 | if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */ |
11683 | insn = 0x0c000000; /* jal */ | |
252b5132 | 11684 | else |
a7ebbfdf TS |
11685 | insn = 0x08000000; /* j */ |
11686 | fixP->fx_r_type = BFD_RELOC_MIPS_JMP; | |
11687 | fixP->fx_done = 0; | |
11688 | fixP->fx_addsy = section_symbol (text_section); | |
11689 | *valP += md_pcrel_from (fixP); | |
2132e3a3 | 11690 | md_number_to_chars ((char *) buf, insn, 4); |
a7ebbfdf TS |
11691 | } |
11692 | else | |
11693 | { | |
11694 | /* If we got here, we have branch-relaxation disabled, | |
11695 | and there's nothing we can do to fix this instruction | |
11696 | without turning it into a longer sequence. */ | |
11697 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11698 | _("Branch out of range")); | |
252b5132 | 11699 | } |
252b5132 RH |
11700 | break; |
11701 | ||
11702 | case BFD_RELOC_VTABLE_INHERIT: | |
11703 | fixP->fx_done = 0; | |
11704 | if (fixP->fx_addsy | |
11705 | && !S_IS_DEFINED (fixP->fx_addsy) | |
11706 | && !S_IS_WEAK (fixP->fx_addsy)) | |
11707 | S_SET_WEAK (fixP->fx_addsy); | |
11708 | break; | |
11709 | ||
11710 | case BFD_RELOC_VTABLE_ENTRY: | |
11711 | fixP->fx_done = 0; | |
11712 | break; | |
11713 | ||
11714 | default: | |
11715 | internalError (); | |
11716 | } | |
a7ebbfdf TS |
11717 | |
11718 | /* Remember value for tc_gen_reloc. */ | |
11719 | fixP->fx_addnumber = *valP; | |
252b5132 RH |
11720 | } |
11721 | ||
252b5132 | 11722 | static symbolS * |
17a2f251 | 11723 | get_symbol (void) |
252b5132 RH |
11724 | { |
11725 | int c; | |
11726 | char *name; | |
11727 | symbolS *p; | |
11728 | ||
11729 | name = input_line_pointer; | |
11730 | c = get_symbol_end (); | |
11731 | p = (symbolS *) symbol_find_or_make (name); | |
11732 | *input_line_pointer = c; | |
11733 | return p; | |
11734 | } | |
11735 | ||
11736 | /* Align the current frag to a given power of two. The MIPS assembler | |
11737 | also automatically adjusts any preceding label. */ | |
11738 | ||
11739 | static void | |
17a2f251 | 11740 | mips_align (int to, int fill, symbolS *label) |
252b5132 | 11741 | { |
7d10b47d | 11742 | mips_emit_delays (); |
252b5132 RH |
11743 | frag_align (to, fill, 0); |
11744 | record_alignment (now_seg, to); | |
11745 | if (label != NULL) | |
11746 | { | |
11747 | assert (S_GET_SEGMENT (label) == now_seg); | |
49309057 | 11748 | symbol_set_frag (label, frag_now); |
252b5132 RH |
11749 | S_SET_VALUE (label, (valueT) frag_now_fix ()); |
11750 | } | |
11751 | } | |
11752 | ||
11753 | /* Align to a given power of two. .align 0 turns off the automatic | |
11754 | alignment used by the data creating pseudo-ops. */ | |
11755 | ||
11756 | static void | |
17a2f251 | 11757 | s_align (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
11758 | { |
11759 | register int temp; | |
11760 | register long temp_fill; | |
11761 | long max_alignment = 15; | |
11762 | ||
11763 | /* | |
11764 | ||
67c1ffbe | 11765 | o Note that the assembler pulls down any immediately preceding label |
252b5132 RH |
11766 | to the aligned address. |
11767 | o It's not documented but auto alignment is reinstated by | |
11768 | a .align pseudo instruction. | |
11769 | o Note also that after auto alignment is turned off the mips assembler | |
11770 | issues an error on attempt to assemble an improperly aligned data item. | |
11771 | We don't. | |
11772 | ||
11773 | */ | |
11774 | ||
11775 | temp = get_absolute_expression (); | |
11776 | if (temp > max_alignment) | |
11777 | as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment); | |
11778 | else if (temp < 0) | |
11779 | { | |
11780 | as_warn (_("Alignment negative: 0 assumed.")); | |
11781 | temp = 0; | |
11782 | } | |
11783 | if (*input_line_pointer == ',') | |
11784 | { | |
f9419b05 | 11785 | ++input_line_pointer; |
252b5132 RH |
11786 | temp_fill = get_absolute_expression (); |
11787 | } | |
11788 | else | |
11789 | temp_fill = 0; | |
11790 | if (temp) | |
11791 | { | |
11792 | auto_align = 1; | |
11793 | mips_align (temp, (int) temp_fill, | |
11794 | insn_labels != NULL ? insn_labels->label : NULL); | |
11795 | } | |
11796 | else | |
11797 | { | |
11798 | auto_align = 0; | |
11799 | } | |
11800 | ||
11801 | demand_empty_rest_of_line (); | |
11802 | } | |
11803 | ||
252b5132 | 11804 | static void |
17a2f251 | 11805 | s_change_sec (int sec) |
252b5132 RH |
11806 | { |
11807 | segT seg; | |
11808 | ||
252b5132 RH |
11809 | #ifdef OBJ_ELF |
11810 | /* The ELF backend needs to know that we are changing sections, so | |
11811 | that .previous works correctly. We could do something like check | |
b6ff326e | 11812 | for an obj_section_change_hook macro, but that might be confusing |
252b5132 RH |
11813 | as it would not be appropriate to use it in the section changing |
11814 | functions in read.c, since obj-elf.c intercepts those. FIXME: | |
11815 | This should be cleaner, somehow. */ | |
11816 | obj_elf_section_change_hook (); | |
11817 | #endif | |
11818 | ||
7d10b47d | 11819 | mips_emit_delays (); |
252b5132 RH |
11820 | switch (sec) |
11821 | { | |
11822 | case 't': | |
11823 | s_text (0); | |
11824 | break; | |
11825 | case 'd': | |
11826 | s_data (0); | |
11827 | break; | |
11828 | case 'b': | |
11829 | subseg_set (bss_section, (subsegT) get_absolute_expression ()); | |
11830 | demand_empty_rest_of_line (); | |
11831 | break; | |
11832 | ||
11833 | case 'r': | |
4d0d148d TS |
11834 | seg = subseg_new (RDATA_SECTION_NAME, |
11835 | (subsegT) get_absolute_expression ()); | |
11836 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
252b5132 | 11837 | { |
4d0d148d TS |
11838 | bfd_set_section_flags (stdoutput, seg, (SEC_ALLOC | SEC_LOAD |
11839 | | SEC_READONLY | SEC_RELOC | |
11840 | | SEC_DATA)); | |
11841 | if (strcmp (TARGET_OS, "elf") != 0) | |
11842 | record_alignment (seg, 4); | |
252b5132 | 11843 | } |
4d0d148d | 11844 | demand_empty_rest_of_line (); |
252b5132 RH |
11845 | break; |
11846 | ||
11847 | case 's': | |
4d0d148d TS |
11848 | seg = subseg_new (".sdata", (subsegT) get_absolute_expression ()); |
11849 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
252b5132 | 11850 | { |
4d0d148d TS |
11851 | bfd_set_section_flags (stdoutput, seg, |
11852 | SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA); | |
11853 | if (strcmp (TARGET_OS, "elf") != 0) | |
11854 | record_alignment (seg, 4); | |
252b5132 | 11855 | } |
4d0d148d TS |
11856 | demand_empty_rest_of_line (); |
11857 | break; | |
252b5132 RH |
11858 | } |
11859 | ||
11860 | auto_align = 1; | |
11861 | } | |
b34976b6 | 11862 | |
cca86cc8 | 11863 | void |
17a2f251 | 11864 | s_change_section (int ignore ATTRIBUTE_UNUSED) |
cca86cc8 | 11865 | { |
7ed4a06a | 11866 | #ifdef OBJ_ELF |
cca86cc8 SC |
11867 | char *section_name; |
11868 | char c; | |
684022ea | 11869 | char next_c = 0; |
cca86cc8 SC |
11870 | int section_type; |
11871 | int section_flag; | |
11872 | int section_entry_size; | |
11873 | int section_alignment; | |
b34976b6 | 11874 | |
7ed4a06a TS |
11875 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
11876 | return; | |
11877 | ||
cca86cc8 SC |
11878 | section_name = input_line_pointer; |
11879 | c = get_symbol_end (); | |
a816d1ed AO |
11880 | if (c) |
11881 | next_c = *(input_line_pointer + 1); | |
cca86cc8 | 11882 | |
4cf0dd0d TS |
11883 | /* Do we have .section Name<,"flags">? */ |
11884 | if (c != ',' || (c == ',' && next_c == '"')) | |
cca86cc8 | 11885 | { |
4cf0dd0d TS |
11886 | /* just after name is now '\0'. */ |
11887 | *input_line_pointer = c; | |
cca86cc8 SC |
11888 | input_line_pointer = section_name; |
11889 | obj_elf_section (ignore); | |
11890 | return; | |
11891 | } | |
11892 | input_line_pointer++; | |
11893 | ||
11894 | /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */ | |
11895 | if (c == ',') | |
11896 | section_type = get_absolute_expression (); | |
11897 | else | |
11898 | section_type = 0; | |
11899 | if (*input_line_pointer++ == ',') | |
11900 | section_flag = get_absolute_expression (); | |
11901 | else | |
11902 | section_flag = 0; | |
11903 | if (*input_line_pointer++ == ',') | |
11904 | section_entry_size = get_absolute_expression (); | |
11905 | else | |
11906 | section_entry_size = 0; | |
11907 | if (*input_line_pointer++ == ',') | |
11908 | section_alignment = get_absolute_expression (); | |
11909 | else | |
11910 | section_alignment = 0; | |
11911 | ||
a816d1ed AO |
11912 | section_name = xstrdup (section_name); |
11913 | ||
8ab8a5c8 RS |
11914 | /* When using the generic form of .section (as implemented by obj-elf.c), |
11915 | there's no way to set the section type to SHT_MIPS_DWARF. Users have | |
11916 | traditionally had to fall back on the more common @progbits instead. | |
11917 | ||
11918 | There's nothing really harmful in this, since bfd will correct | |
11919 | SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it | |
708587a4 | 11920 | means that, for backwards compatibility, the special_section entries |
8ab8a5c8 RS |
11921 | for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF. |
11922 | ||
11923 | Even so, we shouldn't force users of the MIPS .section syntax to | |
11924 | incorrectly label the sections as SHT_PROGBITS. The best compromise | |
11925 | seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the | |
11926 | generic type-checking code. */ | |
11927 | if (section_type == SHT_MIPS_DWARF) | |
11928 | section_type = SHT_PROGBITS; | |
11929 | ||
cca86cc8 SC |
11930 | obj_elf_change_section (section_name, section_type, section_flag, |
11931 | section_entry_size, 0, 0, 0); | |
a816d1ed AO |
11932 | |
11933 | if (now_seg->name != section_name) | |
11934 | free (section_name); | |
7ed4a06a | 11935 | #endif /* OBJ_ELF */ |
cca86cc8 | 11936 | } |
252b5132 RH |
11937 | |
11938 | void | |
17a2f251 | 11939 | mips_enable_auto_align (void) |
252b5132 RH |
11940 | { |
11941 | auto_align = 1; | |
11942 | } | |
11943 | ||
11944 | static void | |
17a2f251 | 11945 | s_cons (int log_size) |
252b5132 RH |
11946 | { |
11947 | symbolS *label; | |
11948 | ||
11949 | label = insn_labels != NULL ? insn_labels->label : NULL; | |
7d10b47d | 11950 | mips_emit_delays (); |
252b5132 RH |
11951 | if (log_size > 0 && auto_align) |
11952 | mips_align (log_size, 0, label); | |
11953 | mips_clear_insn_labels (); | |
11954 | cons (1 << log_size); | |
11955 | } | |
11956 | ||
11957 | static void | |
17a2f251 | 11958 | s_float_cons (int type) |
252b5132 RH |
11959 | { |
11960 | symbolS *label; | |
11961 | ||
11962 | label = insn_labels != NULL ? insn_labels->label : NULL; | |
11963 | ||
7d10b47d | 11964 | mips_emit_delays (); |
252b5132 RH |
11965 | |
11966 | if (auto_align) | |
49309057 ILT |
11967 | { |
11968 | if (type == 'd') | |
11969 | mips_align (3, 0, label); | |
11970 | else | |
11971 | mips_align (2, 0, label); | |
11972 | } | |
252b5132 RH |
11973 | |
11974 | mips_clear_insn_labels (); | |
11975 | ||
11976 | float_cons (type); | |
11977 | } | |
11978 | ||
11979 | /* Handle .globl. We need to override it because on Irix 5 you are | |
11980 | permitted to say | |
11981 | .globl foo .text | |
11982 | where foo is an undefined symbol, to mean that foo should be | |
11983 | considered to be the address of a function. */ | |
11984 | ||
11985 | static void | |
17a2f251 | 11986 | s_mips_globl (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
11987 | { |
11988 | char *name; | |
11989 | int c; | |
11990 | symbolS *symbolP; | |
11991 | flagword flag; | |
11992 | ||
8a06b769 | 11993 | do |
252b5132 | 11994 | { |
8a06b769 | 11995 | name = input_line_pointer; |
252b5132 | 11996 | c = get_symbol_end (); |
8a06b769 TS |
11997 | symbolP = symbol_find_or_make (name); |
11998 | S_SET_EXTERNAL (symbolP); | |
11999 | ||
252b5132 | 12000 | *input_line_pointer = c; |
8a06b769 | 12001 | SKIP_WHITESPACE (); |
252b5132 | 12002 | |
8a06b769 TS |
12003 | /* On Irix 5, every global symbol that is not explicitly labelled as |
12004 | being a function is apparently labelled as being an object. */ | |
12005 | flag = BSF_OBJECT; | |
252b5132 | 12006 | |
8a06b769 TS |
12007 | if (!is_end_of_line[(unsigned char) *input_line_pointer] |
12008 | && (*input_line_pointer != ',')) | |
12009 | { | |
12010 | char *secname; | |
12011 | asection *sec; | |
12012 | ||
12013 | secname = input_line_pointer; | |
12014 | c = get_symbol_end (); | |
12015 | sec = bfd_get_section_by_name (stdoutput, secname); | |
12016 | if (sec == NULL) | |
12017 | as_bad (_("%s: no such section"), secname); | |
12018 | *input_line_pointer = c; | |
12019 | ||
12020 | if (sec != NULL && (sec->flags & SEC_CODE) != 0) | |
12021 | flag = BSF_FUNCTION; | |
12022 | } | |
12023 | ||
12024 | symbol_get_bfdsym (symbolP)->flags |= flag; | |
12025 | ||
12026 | c = *input_line_pointer; | |
12027 | if (c == ',') | |
12028 | { | |
12029 | input_line_pointer++; | |
12030 | SKIP_WHITESPACE (); | |
12031 | if (is_end_of_line[(unsigned char) *input_line_pointer]) | |
12032 | c = '\n'; | |
12033 | } | |
12034 | } | |
12035 | while (c == ','); | |
252b5132 | 12036 | |
252b5132 RH |
12037 | demand_empty_rest_of_line (); |
12038 | } | |
12039 | ||
12040 | static void | |
17a2f251 | 12041 | s_option (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
12042 | { |
12043 | char *opt; | |
12044 | char c; | |
12045 | ||
12046 | opt = input_line_pointer; | |
12047 | c = get_symbol_end (); | |
12048 | ||
12049 | if (*opt == 'O') | |
12050 | { | |
12051 | /* FIXME: What does this mean? */ | |
12052 | } | |
12053 | else if (strncmp (opt, "pic", 3) == 0) | |
12054 | { | |
12055 | int i; | |
12056 | ||
12057 | i = atoi (opt + 3); | |
12058 | if (i == 0) | |
12059 | mips_pic = NO_PIC; | |
12060 | else if (i == 2) | |
143d77c5 | 12061 | { |
252b5132 | 12062 | mips_pic = SVR4_PIC; |
143d77c5 EC |
12063 | mips_abicalls = TRUE; |
12064 | } | |
252b5132 RH |
12065 | else |
12066 | as_bad (_(".option pic%d not supported"), i); | |
12067 | ||
4d0d148d | 12068 | if (mips_pic == SVR4_PIC) |
252b5132 RH |
12069 | { |
12070 | if (g_switch_seen && g_switch_value != 0) | |
12071 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
12072 | g_switch_value = 0; | |
12073 | bfd_set_gp_size (stdoutput, 0); | |
12074 | } | |
12075 | } | |
12076 | else | |
12077 | as_warn (_("Unrecognized option \"%s\""), opt); | |
12078 | ||
12079 | *input_line_pointer = c; | |
12080 | demand_empty_rest_of_line (); | |
12081 | } | |
12082 | ||
12083 | /* This structure is used to hold a stack of .set values. */ | |
12084 | ||
e972090a NC |
12085 | struct mips_option_stack |
12086 | { | |
252b5132 RH |
12087 | struct mips_option_stack *next; |
12088 | struct mips_set_options options; | |
12089 | }; | |
12090 | ||
12091 | static struct mips_option_stack *mips_opts_stack; | |
12092 | ||
12093 | /* Handle the .set pseudo-op. */ | |
12094 | ||
12095 | static void | |
17a2f251 | 12096 | s_mipsset (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
12097 | { |
12098 | char *name = input_line_pointer, ch; | |
12099 | ||
12100 | while (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
f9419b05 | 12101 | ++input_line_pointer; |
252b5132 RH |
12102 | ch = *input_line_pointer; |
12103 | *input_line_pointer = '\0'; | |
12104 | ||
12105 | if (strcmp (name, "reorder") == 0) | |
12106 | { | |
7d10b47d RS |
12107 | if (mips_opts.noreorder) |
12108 | end_noreorder (); | |
252b5132 RH |
12109 | } |
12110 | else if (strcmp (name, "noreorder") == 0) | |
12111 | { | |
7d10b47d RS |
12112 | if (!mips_opts.noreorder) |
12113 | start_noreorder (); | |
252b5132 RH |
12114 | } |
12115 | else if (strcmp (name, "at") == 0) | |
12116 | { | |
12117 | mips_opts.noat = 0; | |
12118 | } | |
12119 | else if (strcmp (name, "noat") == 0) | |
12120 | { | |
12121 | mips_opts.noat = 1; | |
12122 | } | |
12123 | else if (strcmp (name, "macro") == 0) | |
12124 | { | |
12125 | mips_opts.warn_about_macros = 0; | |
12126 | } | |
12127 | else if (strcmp (name, "nomacro") == 0) | |
12128 | { | |
12129 | if (mips_opts.noreorder == 0) | |
12130 | as_bad (_("`noreorder' must be set before `nomacro'")); | |
12131 | mips_opts.warn_about_macros = 1; | |
12132 | } | |
12133 | else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0) | |
12134 | { | |
12135 | mips_opts.nomove = 0; | |
12136 | } | |
12137 | else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0) | |
12138 | { | |
12139 | mips_opts.nomove = 1; | |
12140 | } | |
12141 | else if (strcmp (name, "bopt") == 0) | |
12142 | { | |
12143 | mips_opts.nobopt = 0; | |
12144 | } | |
12145 | else if (strcmp (name, "nobopt") == 0) | |
12146 | { | |
12147 | mips_opts.nobopt = 1; | |
12148 | } | |
12149 | else if (strcmp (name, "mips16") == 0 | |
12150 | || strcmp (name, "MIPS-16") == 0) | |
12151 | mips_opts.mips16 = 1; | |
12152 | else if (strcmp (name, "nomips16") == 0 | |
12153 | || strcmp (name, "noMIPS-16") == 0) | |
12154 | mips_opts.mips16 = 0; | |
e16bfa71 TS |
12155 | else if (strcmp (name, "smartmips") == 0) |
12156 | { | |
12157 | if (!ISA_SUPPORT_SMARTMIPS) | |
12158 | as_warn ("%s ISA does not support SmartMIPS ASE", | |
12159 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
12160 | mips_opts.ase_smartmips = 1; | |
12161 | } | |
12162 | else if (strcmp (name, "nosmartmips") == 0) | |
12163 | mips_opts.ase_smartmips = 0; | |
1f25f5d3 CD |
12164 | else if (strcmp (name, "mips3d") == 0) |
12165 | mips_opts.ase_mips3d = 1; | |
12166 | else if (strcmp (name, "nomips3d") == 0) | |
12167 | mips_opts.ase_mips3d = 0; | |
a4672219 TS |
12168 | else if (strcmp (name, "mdmx") == 0) |
12169 | mips_opts.ase_mdmx = 1; | |
12170 | else if (strcmp (name, "nomdmx") == 0) | |
12171 | mips_opts.ase_mdmx = 0; | |
74cd071d CF |
12172 | else if (strcmp (name, "dsp") == 0) |
12173 | mips_opts.ase_dsp = 1; | |
12174 | else if (strcmp (name, "nodsp") == 0) | |
12175 | mips_opts.ase_dsp = 0; | |
ef2e4d86 CF |
12176 | else if (strcmp (name, "mt") == 0) |
12177 | mips_opts.ase_mt = 1; | |
12178 | else if (strcmp (name, "nomt") == 0) | |
12179 | mips_opts.ase_mt = 0; | |
1a2c1fad | 12180 | else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0) |
252b5132 | 12181 | { |
af7ee8bf | 12182 | int reset = 0; |
252b5132 | 12183 | |
1a2c1fad CD |
12184 | /* Permit the user to change the ISA and architecture on the fly. |
12185 | Needless to say, misuse can cause serious problems. */ | |
81a21e38 | 12186 | if (strcmp (name, "mips0") == 0 || strcmp (name, "arch=default") == 0) |
af7ee8bf CD |
12187 | { |
12188 | reset = 1; | |
12189 | mips_opts.isa = file_mips_isa; | |
1a2c1fad | 12190 | mips_opts.arch = file_mips_arch; |
1a2c1fad CD |
12191 | } |
12192 | else if (strncmp (name, "arch=", 5) == 0) | |
12193 | { | |
12194 | const struct mips_cpu_info *p; | |
12195 | ||
12196 | p = mips_parse_cpu("internal use", name + 5); | |
12197 | if (!p) | |
12198 | as_bad (_("unknown architecture %s"), name + 5); | |
12199 | else | |
12200 | { | |
12201 | mips_opts.arch = p->cpu; | |
12202 | mips_opts.isa = p->isa; | |
12203 | } | |
12204 | } | |
81a21e38 TS |
12205 | else if (strncmp (name, "mips", 4) == 0) |
12206 | { | |
12207 | const struct mips_cpu_info *p; | |
12208 | ||
12209 | p = mips_parse_cpu("internal use", name); | |
12210 | if (!p) | |
12211 | as_bad (_("unknown ISA level %s"), name + 4); | |
12212 | else | |
12213 | { | |
12214 | mips_opts.arch = p->cpu; | |
12215 | mips_opts.isa = p->isa; | |
12216 | } | |
12217 | } | |
af7ee8bf | 12218 | else |
81a21e38 | 12219 | as_bad (_("unknown ISA or architecture %s"), name); |
af7ee8bf CD |
12220 | |
12221 | switch (mips_opts.isa) | |
98d3f06f KH |
12222 | { |
12223 | case 0: | |
98d3f06f | 12224 | break; |
af7ee8bf CD |
12225 | case ISA_MIPS1: |
12226 | case ISA_MIPS2: | |
12227 | case ISA_MIPS32: | |
12228 | case ISA_MIPS32R2: | |
98d3f06f KH |
12229 | mips_opts.gp32 = 1; |
12230 | mips_opts.fp32 = 1; | |
12231 | break; | |
af7ee8bf CD |
12232 | case ISA_MIPS3: |
12233 | case ISA_MIPS4: | |
12234 | case ISA_MIPS5: | |
12235 | case ISA_MIPS64: | |
5f74bc13 | 12236 | case ISA_MIPS64R2: |
98d3f06f KH |
12237 | mips_opts.gp32 = 0; |
12238 | mips_opts.fp32 = 0; | |
12239 | break; | |
12240 | default: | |
12241 | as_bad (_("unknown ISA level %s"), name + 4); | |
12242 | break; | |
12243 | } | |
af7ee8bf | 12244 | if (reset) |
98d3f06f | 12245 | { |
af7ee8bf CD |
12246 | mips_opts.gp32 = file_mips_gp32; |
12247 | mips_opts.fp32 = file_mips_fp32; | |
98d3f06f | 12248 | } |
252b5132 RH |
12249 | } |
12250 | else if (strcmp (name, "autoextend") == 0) | |
12251 | mips_opts.noautoextend = 0; | |
12252 | else if (strcmp (name, "noautoextend") == 0) | |
12253 | mips_opts.noautoextend = 1; | |
12254 | else if (strcmp (name, "push") == 0) | |
12255 | { | |
12256 | struct mips_option_stack *s; | |
12257 | ||
12258 | s = (struct mips_option_stack *) xmalloc (sizeof *s); | |
12259 | s->next = mips_opts_stack; | |
12260 | s->options = mips_opts; | |
12261 | mips_opts_stack = s; | |
12262 | } | |
12263 | else if (strcmp (name, "pop") == 0) | |
12264 | { | |
12265 | struct mips_option_stack *s; | |
12266 | ||
12267 | s = mips_opts_stack; | |
12268 | if (s == NULL) | |
12269 | as_bad (_(".set pop with no .set push")); | |
12270 | else | |
12271 | { | |
12272 | /* If we're changing the reorder mode we need to handle | |
12273 | delay slots correctly. */ | |
12274 | if (s->options.noreorder && ! mips_opts.noreorder) | |
7d10b47d | 12275 | start_noreorder (); |
252b5132 | 12276 | else if (! s->options.noreorder && mips_opts.noreorder) |
7d10b47d | 12277 | end_noreorder (); |
252b5132 RH |
12278 | |
12279 | mips_opts = s->options; | |
12280 | mips_opts_stack = s->next; | |
12281 | free (s); | |
12282 | } | |
12283 | } | |
aed1a261 RS |
12284 | else if (strcmp (name, "sym32") == 0) |
12285 | mips_opts.sym32 = TRUE; | |
12286 | else if (strcmp (name, "nosym32") == 0) | |
12287 | mips_opts.sym32 = FALSE; | |
252b5132 RH |
12288 | else |
12289 | { | |
12290 | as_warn (_("Tried to set unrecognized symbol: %s\n"), name); | |
12291 | } | |
12292 | *input_line_pointer = ch; | |
12293 | demand_empty_rest_of_line (); | |
12294 | } | |
12295 | ||
12296 | /* Handle the .abicalls pseudo-op. I believe this is equivalent to | |
12297 | .option pic2. It means to generate SVR4 PIC calls. */ | |
12298 | ||
12299 | static void | |
17a2f251 | 12300 | s_abicalls (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
12301 | { |
12302 | mips_pic = SVR4_PIC; | |
143d77c5 | 12303 | mips_abicalls = TRUE; |
4d0d148d TS |
12304 | |
12305 | if (g_switch_seen && g_switch_value != 0) | |
12306 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
12307 | g_switch_value = 0; | |
12308 | ||
252b5132 RH |
12309 | bfd_set_gp_size (stdoutput, 0); |
12310 | demand_empty_rest_of_line (); | |
12311 | } | |
12312 | ||
12313 | /* Handle the .cpload pseudo-op. This is used when generating SVR4 | |
12314 | PIC code. It sets the $gp register for the function based on the | |
12315 | function address, which is in the register named in the argument. | |
12316 | This uses a relocation against _gp_disp, which is handled specially | |
12317 | by the linker. The result is: | |
12318 | lui $gp,%hi(_gp_disp) | |
12319 | addiu $gp,$gp,%lo(_gp_disp) | |
12320 | addu $gp,$gp,.cpload argument | |
aa6975fb ILT |
12321 | The .cpload argument is normally $25 == $t9. |
12322 | ||
12323 | The -mno-shared option changes this to: | |
bbe506e8 TS |
12324 | lui $gp,%hi(__gnu_local_gp) |
12325 | addiu $gp,$gp,%lo(__gnu_local_gp) | |
aa6975fb ILT |
12326 | and the argument is ignored. This saves an instruction, but the |
12327 | resulting code is not position independent; it uses an absolute | |
bbe506e8 TS |
12328 | address for __gnu_local_gp. Thus code assembled with -mno-shared |
12329 | can go into an ordinary executable, but not into a shared library. */ | |
252b5132 RH |
12330 | |
12331 | static void | |
17a2f251 | 12332 | s_cpload (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
12333 | { |
12334 | expressionS ex; | |
aa6975fb ILT |
12335 | int reg; |
12336 | int in_shared; | |
252b5132 | 12337 | |
6478892d TS |
12338 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
12339 | .cpload is ignored. */ | |
12340 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) | |
252b5132 RH |
12341 | { |
12342 | s_ignore (0); | |
12343 | return; | |
12344 | } | |
12345 | ||
d3ecfc59 | 12346 | /* .cpload should be in a .set noreorder section. */ |
252b5132 RH |
12347 | if (mips_opts.noreorder == 0) |
12348 | as_warn (_(".cpload not in noreorder section")); | |
12349 | ||
aa6975fb ILT |
12350 | reg = tc_get_register (0); |
12351 | ||
12352 | /* If we need to produce a 64-bit address, we are better off using | |
12353 | the default instruction sequence. */ | |
aed1a261 | 12354 | in_shared = mips_in_shared || HAVE_64BIT_SYMBOLS; |
aa6975fb | 12355 | |
252b5132 | 12356 | ex.X_op = O_symbol; |
bbe506e8 TS |
12357 | ex.X_add_symbol = symbol_find_or_make (in_shared ? "_gp_disp" : |
12358 | "__gnu_local_gp"); | |
252b5132 RH |
12359 | ex.X_op_symbol = NULL; |
12360 | ex.X_add_number = 0; | |
12361 | ||
12362 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ | |
49309057 | 12363 | symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; |
252b5132 | 12364 | |
584892a6 | 12365 | macro_start (); |
67c0d1eb RS |
12366 | macro_build_lui (&ex, mips_gp_register); |
12367 | macro_build (&ex, "addiu", "t,r,j", mips_gp_register, | |
17a2f251 | 12368 | mips_gp_register, BFD_RELOC_LO16); |
aa6975fb ILT |
12369 | if (in_shared) |
12370 | macro_build (NULL, "addu", "d,v,t", mips_gp_register, | |
12371 | mips_gp_register, reg); | |
584892a6 | 12372 | macro_end (); |
252b5132 RH |
12373 | |
12374 | demand_empty_rest_of_line (); | |
12375 | } | |
12376 | ||
6478892d TS |
12377 | /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is: |
12378 | .cpsetup $reg1, offset|$reg2, label | |
12379 | ||
12380 | If offset is given, this results in: | |
12381 | sd $gp, offset($sp) | |
956cd1d6 | 12382 | lui $gp, %hi(%neg(%gp_rel(label))) |
698b7d9d TS |
12383 | addiu $gp, $gp, %lo(%neg(%gp_rel(label))) |
12384 | daddu $gp, $gp, $reg1 | |
6478892d TS |
12385 | |
12386 | If $reg2 is given, this results in: | |
12387 | daddu $reg2, $gp, $0 | |
956cd1d6 | 12388 | lui $gp, %hi(%neg(%gp_rel(label))) |
698b7d9d TS |
12389 | addiu $gp, $gp, %lo(%neg(%gp_rel(label))) |
12390 | daddu $gp, $gp, $reg1 | |
aa6975fb ILT |
12391 | $reg1 is normally $25 == $t9. |
12392 | ||
12393 | The -mno-shared option replaces the last three instructions with | |
12394 | lui $gp,%hi(_gp) | |
12395 | addiu $gp,$gp,%lo(_gp) | |
12396 | */ | |
12397 | ||
6478892d | 12398 | static void |
17a2f251 | 12399 | s_cpsetup (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
12400 | { |
12401 | expressionS ex_off; | |
12402 | expressionS ex_sym; | |
12403 | int reg1; | |
6478892d | 12404 | |
8586fc66 | 12405 | /* If we are not generating SVR4 PIC code, .cpsetup is ignored. |
6478892d TS |
12406 | We also need NewABI support. */ |
12407 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
12408 | { | |
12409 | s_ignore (0); | |
12410 | return; | |
12411 | } | |
12412 | ||
12413 | reg1 = tc_get_register (0); | |
12414 | SKIP_WHITESPACE (); | |
12415 | if (*input_line_pointer != ',') | |
12416 | { | |
12417 | as_bad (_("missing argument separator ',' for .cpsetup")); | |
12418 | return; | |
12419 | } | |
12420 | else | |
80245285 | 12421 | ++input_line_pointer; |
6478892d TS |
12422 | SKIP_WHITESPACE (); |
12423 | if (*input_line_pointer == '$') | |
80245285 TS |
12424 | { |
12425 | mips_cpreturn_register = tc_get_register (0); | |
12426 | mips_cpreturn_offset = -1; | |
12427 | } | |
6478892d | 12428 | else |
80245285 TS |
12429 | { |
12430 | mips_cpreturn_offset = get_absolute_expression (); | |
12431 | mips_cpreturn_register = -1; | |
12432 | } | |
6478892d TS |
12433 | SKIP_WHITESPACE (); |
12434 | if (*input_line_pointer != ',') | |
12435 | { | |
12436 | as_bad (_("missing argument separator ',' for .cpsetup")); | |
12437 | return; | |
12438 | } | |
12439 | else | |
f9419b05 | 12440 | ++input_line_pointer; |
6478892d | 12441 | SKIP_WHITESPACE (); |
f21f8242 | 12442 | expression (&ex_sym); |
6478892d | 12443 | |
584892a6 | 12444 | macro_start (); |
6478892d TS |
12445 | if (mips_cpreturn_register == -1) |
12446 | { | |
12447 | ex_off.X_op = O_constant; | |
12448 | ex_off.X_add_symbol = NULL; | |
12449 | ex_off.X_op_symbol = NULL; | |
12450 | ex_off.X_add_number = mips_cpreturn_offset; | |
12451 | ||
67c0d1eb | 12452 | macro_build (&ex_off, "sd", "t,o(b)", mips_gp_register, |
17a2f251 | 12453 | BFD_RELOC_LO16, SP); |
6478892d TS |
12454 | } |
12455 | else | |
67c0d1eb | 12456 | macro_build (NULL, "daddu", "d,v,t", mips_cpreturn_register, |
17a2f251 | 12457 | mips_gp_register, 0); |
6478892d | 12458 | |
aed1a261 | 12459 | if (mips_in_shared || HAVE_64BIT_SYMBOLS) |
aa6975fb ILT |
12460 | { |
12461 | macro_build (&ex_sym, "lui", "t,u", mips_gp_register, | |
12462 | -1, BFD_RELOC_GPREL16, BFD_RELOC_MIPS_SUB, | |
12463 | BFD_RELOC_HI16_S); | |
12464 | ||
12465 | macro_build (&ex_sym, "addiu", "t,r,j", mips_gp_register, | |
12466 | mips_gp_register, -1, BFD_RELOC_GPREL16, | |
12467 | BFD_RELOC_MIPS_SUB, BFD_RELOC_LO16); | |
12468 | ||
12469 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register, | |
12470 | mips_gp_register, reg1); | |
12471 | } | |
12472 | else | |
12473 | { | |
12474 | expressionS ex; | |
12475 | ||
12476 | ex.X_op = O_symbol; | |
4184909a | 12477 | ex.X_add_symbol = symbol_find_or_make ("__gnu_local_gp"); |
aa6975fb ILT |
12478 | ex.X_op_symbol = NULL; |
12479 | ex.X_add_number = 0; | |
6e1304d8 | 12480 | |
aa6975fb ILT |
12481 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ |
12482 | symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; | |
12483 | ||
12484 | macro_build_lui (&ex, mips_gp_register); | |
12485 | macro_build (&ex, "addiu", "t,r,j", mips_gp_register, | |
12486 | mips_gp_register, BFD_RELOC_LO16); | |
12487 | } | |
f21f8242 | 12488 | |
584892a6 | 12489 | macro_end (); |
6478892d TS |
12490 | |
12491 | demand_empty_rest_of_line (); | |
12492 | } | |
12493 | ||
12494 | static void | |
17a2f251 | 12495 | s_cplocal (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
12496 | { |
12497 | /* If we are not generating SVR4 PIC code, or if this is not NewABI code, | |
12498 | .cplocal is ignored. */ | |
12499 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
12500 | { | |
12501 | s_ignore (0); | |
12502 | return; | |
12503 | } | |
12504 | ||
12505 | mips_gp_register = tc_get_register (0); | |
85b51719 | 12506 | demand_empty_rest_of_line (); |
6478892d TS |
12507 | } |
12508 | ||
252b5132 RH |
12509 | /* Handle the .cprestore pseudo-op. This stores $gp into a given |
12510 | offset from $sp. The offset is remembered, and after making a PIC | |
12511 | call $gp is restored from that location. */ | |
12512 | ||
12513 | static void | |
17a2f251 | 12514 | s_cprestore (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
12515 | { |
12516 | expressionS ex; | |
252b5132 | 12517 | |
6478892d | 12518 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
c9914766 | 12519 | .cprestore is ignored. */ |
6478892d | 12520 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) |
252b5132 RH |
12521 | { |
12522 | s_ignore (0); | |
12523 | return; | |
12524 | } | |
12525 | ||
12526 | mips_cprestore_offset = get_absolute_expression (); | |
7a621144 | 12527 | mips_cprestore_valid = 1; |
252b5132 RH |
12528 | |
12529 | ex.X_op = O_constant; | |
12530 | ex.X_add_symbol = NULL; | |
12531 | ex.X_op_symbol = NULL; | |
12532 | ex.X_add_number = mips_cprestore_offset; | |
12533 | ||
584892a6 | 12534 | macro_start (); |
67c0d1eb RS |
12535 | macro_build_ldst_constoffset (&ex, ADDRESS_STORE_INSN, mips_gp_register, |
12536 | SP, HAVE_64BIT_ADDRESSES); | |
584892a6 | 12537 | macro_end (); |
252b5132 RH |
12538 | |
12539 | demand_empty_rest_of_line (); | |
12540 | } | |
12541 | ||
6478892d | 12542 | /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset |
67c1ffbe | 12543 | was given in the preceding .cpsetup, it results in: |
6478892d | 12544 | ld $gp, offset($sp) |
76b3015f | 12545 | |
6478892d | 12546 | If a register $reg2 was given there, it results in: |
609f23f4 | 12547 | daddu $gp, $reg2, $0 |
6478892d TS |
12548 | */ |
12549 | static void | |
17a2f251 | 12550 | s_cpreturn (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
12551 | { |
12552 | expressionS ex; | |
6478892d TS |
12553 | |
12554 | /* If we are not generating SVR4 PIC code, .cpreturn is ignored. | |
12555 | We also need NewABI support. */ | |
12556 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
12557 | { | |
12558 | s_ignore (0); | |
12559 | return; | |
12560 | } | |
12561 | ||
584892a6 | 12562 | macro_start (); |
6478892d TS |
12563 | if (mips_cpreturn_register == -1) |
12564 | { | |
12565 | ex.X_op = O_constant; | |
12566 | ex.X_add_symbol = NULL; | |
12567 | ex.X_op_symbol = NULL; | |
12568 | ex.X_add_number = mips_cpreturn_offset; | |
12569 | ||
67c0d1eb | 12570 | macro_build (&ex, "ld", "t,o(b)", mips_gp_register, BFD_RELOC_LO16, SP); |
6478892d TS |
12571 | } |
12572 | else | |
67c0d1eb | 12573 | macro_build (NULL, "daddu", "d,v,t", mips_gp_register, |
17a2f251 | 12574 | mips_cpreturn_register, 0); |
584892a6 | 12575 | macro_end (); |
6478892d TS |
12576 | |
12577 | demand_empty_rest_of_line (); | |
12578 | } | |
12579 | ||
12580 | /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC | |
12581 | code. It sets the offset to use in gp_rel relocations. */ | |
12582 | ||
12583 | static void | |
17a2f251 | 12584 | s_gpvalue (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
12585 | { |
12586 | /* If we are not generating SVR4 PIC code, .gpvalue is ignored. | |
12587 | We also need NewABI support. */ | |
12588 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
12589 | { | |
12590 | s_ignore (0); | |
12591 | return; | |
12592 | } | |
12593 | ||
def2e0dd | 12594 | mips_gprel_offset = get_absolute_expression (); |
6478892d TS |
12595 | |
12596 | demand_empty_rest_of_line (); | |
12597 | } | |
12598 | ||
252b5132 RH |
12599 | /* Handle the .gpword pseudo-op. This is used when generating PIC |
12600 | code. It generates a 32 bit GP relative reloc. */ | |
12601 | ||
12602 | static void | |
17a2f251 | 12603 | s_gpword (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
12604 | { |
12605 | symbolS *label; | |
12606 | expressionS ex; | |
12607 | char *p; | |
12608 | ||
12609 | /* When not generating PIC code, this is treated as .word. */ | |
12610 | if (mips_pic != SVR4_PIC) | |
12611 | { | |
12612 | s_cons (2); | |
12613 | return; | |
12614 | } | |
12615 | ||
12616 | label = insn_labels != NULL ? insn_labels->label : NULL; | |
7d10b47d | 12617 | mips_emit_delays (); |
252b5132 RH |
12618 | if (auto_align) |
12619 | mips_align (2, 0, label); | |
12620 | mips_clear_insn_labels (); | |
12621 | ||
12622 | expression (&ex); | |
12623 | ||
12624 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
12625 | { | |
12626 | as_bad (_("Unsupported use of .gpword")); | |
12627 | ignore_rest_of_line (); | |
12628 | } | |
12629 | ||
12630 | p = frag_more (4); | |
17a2f251 | 12631 | md_number_to_chars (p, 0, 4); |
b34976b6 | 12632 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, |
cdf6fd85 | 12633 | BFD_RELOC_GPREL32); |
252b5132 RH |
12634 | |
12635 | demand_empty_rest_of_line (); | |
12636 | } | |
12637 | ||
10181a0d | 12638 | static void |
17a2f251 | 12639 | s_gpdword (int ignore ATTRIBUTE_UNUSED) |
10181a0d AO |
12640 | { |
12641 | symbolS *label; | |
12642 | expressionS ex; | |
12643 | char *p; | |
12644 | ||
12645 | /* When not generating PIC code, this is treated as .dword. */ | |
12646 | if (mips_pic != SVR4_PIC) | |
12647 | { | |
12648 | s_cons (3); | |
12649 | return; | |
12650 | } | |
12651 | ||
12652 | label = insn_labels != NULL ? insn_labels->label : NULL; | |
7d10b47d | 12653 | mips_emit_delays (); |
10181a0d AO |
12654 | if (auto_align) |
12655 | mips_align (3, 0, label); | |
12656 | mips_clear_insn_labels (); | |
12657 | ||
12658 | expression (&ex); | |
12659 | ||
12660 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
12661 | { | |
12662 | as_bad (_("Unsupported use of .gpdword")); | |
12663 | ignore_rest_of_line (); | |
12664 | } | |
12665 | ||
12666 | p = frag_more (8); | |
17a2f251 | 12667 | md_number_to_chars (p, 0, 8); |
a105a300 | 12668 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, |
6e1304d8 | 12669 | BFD_RELOC_GPREL32)->fx_tcbit = 1; |
10181a0d AO |
12670 | |
12671 | /* GPREL32 composed with 64 gives a 64-bit GP offset. */ | |
6e1304d8 RS |
12672 | fix_new (frag_now, p - frag_now->fr_literal, 8, NULL, 0, |
12673 | FALSE, BFD_RELOC_64)->fx_tcbit = 1; | |
10181a0d AO |
12674 | |
12675 | demand_empty_rest_of_line (); | |
12676 | } | |
12677 | ||
252b5132 RH |
12678 | /* Handle the .cpadd pseudo-op. This is used when dealing with switch |
12679 | tables in SVR4 PIC code. */ | |
12680 | ||
12681 | static void | |
17a2f251 | 12682 | s_cpadd (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 12683 | { |
252b5132 RH |
12684 | int reg; |
12685 | ||
10181a0d AO |
12686 | /* This is ignored when not generating SVR4 PIC code. */ |
12687 | if (mips_pic != SVR4_PIC) | |
252b5132 RH |
12688 | { |
12689 | s_ignore (0); | |
12690 | return; | |
12691 | } | |
12692 | ||
12693 | /* Add $gp to the register named as an argument. */ | |
584892a6 | 12694 | macro_start (); |
252b5132 | 12695 | reg = tc_get_register (0); |
67c0d1eb | 12696 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register); |
584892a6 | 12697 | macro_end (); |
252b5132 | 12698 | |
bdaaa2e1 | 12699 | demand_empty_rest_of_line (); |
252b5132 RH |
12700 | } |
12701 | ||
12702 | /* Handle the .insn pseudo-op. This marks instruction labels in | |
12703 | mips16 mode. This permits the linker to handle them specially, | |
12704 | such as generating jalx instructions when needed. We also make | |
12705 | them odd for the duration of the assembly, in order to generate the | |
12706 | right sort of code. We will make them even in the adjust_symtab | |
12707 | routine, while leaving them marked. This is convenient for the | |
12708 | debugger and the disassembler. The linker knows to make them odd | |
12709 | again. */ | |
12710 | ||
12711 | static void | |
17a2f251 | 12712 | s_insn (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 12713 | { |
f9419b05 | 12714 | mips16_mark_labels (); |
252b5132 RH |
12715 | |
12716 | demand_empty_rest_of_line (); | |
12717 | } | |
12718 | ||
12719 | /* Handle a .stabn directive. We need these in order to mark a label | |
12720 | as being a mips16 text label correctly. Sometimes the compiler | |
12721 | will emit a label, followed by a .stabn, and then switch sections. | |
12722 | If the label and .stabn are in mips16 mode, then the label is | |
12723 | really a mips16 text label. */ | |
12724 | ||
12725 | static void | |
17a2f251 | 12726 | s_mips_stab (int type) |
252b5132 | 12727 | { |
f9419b05 | 12728 | if (type == 'n') |
252b5132 RH |
12729 | mips16_mark_labels (); |
12730 | ||
12731 | s_stab (type); | |
12732 | } | |
12733 | ||
12734 | /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. | |
12735 | */ | |
12736 | ||
12737 | static void | |
17a2f251 | 12738 | s_mips_weakext (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
12739 | { |
12740 | char *name; | |
12741 | int c; | |
12742 | symbolS *symbolP; | |
12743 | expressionS exp; | |
12744 | ||
12745 | name = input_line_pointer; | |
12746 | c = get_symbol_end (); | |
12747 | symbolP = symbol_find_or_make (name); | |
12748 | S_SET_WEAK (symbolP); | |
12749 | *input_line_pointer = c; | |
12750 | ||
12751 | SKIP_WHITESPACE (); | |
12752 | ||
12753 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
12754 | { | |
12755 | if (S_IS_DEFINED (symbolP)) | |
12756 | { | |
956cd1d6 | 12757 | as_bad ("ignoring attempt to redefine symbol %s", |
252b5132 RH |
12758 | S_GET_NAME (symbolP)); |
12759 | ignore_rest_of_line (); | |
12760 | return; | |
12761 | } | |
bdaaa2e1 | 12762 | |
252b5132 RH |
12763 | if (*input_line_pointer == ',') |
12764 | { | |
12765 | ++input_line_pointer; | |
12766 | SKIP_WHITESPACE (); | |
12767 | } | |
bdaaa2e1 | 12768 | |
252b5132 RH |
12769 | expression (&exp); |
12770 | if (exp.X_op != O_symbol) | |
12771 | { | |
12772 | as_bad ("bad .weakext directive"); | |
98d3f06f | 12773 | ignore_rest_of_line (); |
252b5132 RH |
12774 | return; |
12775 | } | |
49309057 | 12776 | symbol_set_value_expression (symbolP, &exp); |
252b5132 RH |
12777 | } |
12778 | ||
12779 | demand_empty_rest_of_line (); | |
12780 | } | |
12781 | ||
12782 | /* Parse a register string into a number. Called from the ECOFF code | |
12783 | to parse .frame. The argument is non-zero if this is the frame | |
12784 | register, so that we can record it in mips_frame_reg. */ | |
12785 | ||
12786 | int | |
17a2f251 | 12787 | tc_get_register (int frame) |
252b5132 RH |
12788 | { |
12789 | int reg; | |
12790 | ||
12791 | SKIP_WHITESPACE (); | |
12792 | if (*input_line_pointer++ != '$') | |
12793 | { | |
12794 | as_warn (_("expected `$'")); | |
85b51719 | 12795 | reg = ZERO; |
252b5132 | 12796 | } |
3882b010 | 12797 | else if (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
12798 | { |
12799 | reg = get_absolute_expression (); | |
12800 | if (reg < 0 || reg >= 32) | |
12801 | { | |
12802 | as_warn (_("Bad register number")); | |
85b51719 | 12803 | reg = ZERO; |
252b5132 RH |
12804 | } |
12805 | } | |
12806 | else | |
12807 | { | |
76db943d | 12808 | if (strncmp (input_line_pointer, "ra", 2) == 0) |
85b51719 TS |
12809 | { |
12810 | reg = RA; | |
12811 | input_line_pointer += 2; | |
12812 | } | |
76db943d | 12813 | else if (strncmp (input_line_pointer, "fp", 2) == 0) |
85b51719 TS |
12814 | { |
12815 | reg = FP; | |
12816 | input_line_pointer += 2; | |
12817 | } | |
252b5132 | 12818 | else if (strncmp (input_line_pointer, "sp", 2) == 0) |
85b51719 TS |
12819 | { |
12820 | reg = SP; | |
12821 | input_line_pointer += 2; | |
12822 | } | |
252b5132 | 12823 | else if (strncmp (input_line_pointer, "gp", 2) == 0) |
85b51719 TS |
12824 | { |
12825 | reg = GP; | |
12826 | input_line_pointer += 2; | |
12827 | } | |
252b5132 | 12828 | else if (strncmp (input_line_pointer, "at", 2) == 0) |
85b51719 TS |
12829 | { |
12830 | reg = AT; | |
12831 | input_line_pointer += 2; | |
12832 | } | |
12833 | else if (strncmp (input_line_pointer, "kt0", 3) == 0) | |
12834 | { | |
12835 | reg = KT0; | |
12836 | input_line_pointer += 3; | |
12837 | } | |
12838 | else if (strncmp (input_line_pointer, "kt1", 3) == 0) | |
12839 | { | |
12840 | reg = KT1; | |
12841 | input_line_pointer += 3; | |
12842 | } | |
12843 | else if (strncmp (input_line_pointer, "zero", 4) == 0) | |
12844 | { | |
12845 | reg = ZERO; | |
12846 | input_line_pointer += 4; | |
12847 | } | |
252b5132 RH |
12848 | else |
12849 | { | |
12850 | as_warn (_("Unrecognized register name")); | |
85b51719 TS |
12851 | reg = ZERO; |
12852 | while (ISALNUM(*input_line_pointer)) | |
12853 | input_line_pointer++; | |
252b5132 | 12854 | } |
252b5132 RH |
12855 | } |
12856 | if (frame) | |
7a621144 DJ |
12857 | { |
12858 | mips_frame_reg = reg != 0 ? reg : SP; | |
12859 | mips_frame_reg_valid = 1; | |
12860 | mips_cprestore_valid = 0; | |
12861 | } | |
252b5132 RH |
12862 | return reg; |
12863 | } | |
12864 | ||
12865 | valueT | |
17a2f251 | 12866 | md_section_align (asection *seg, valueT addr) |
252b5132 RH |
12867 | { |
12868 | int align = bfd_get_section_alignment (stdoutput, seg); | |
12869 | ||
12870 | #ifdef OBJ_ELF | |
12871 | /* We don't need to align ELF sections to the full alignment. | |
12872 | However, Irix 5 may prefer that we align them at least to a 16 | |
12873 | byte boundary. We don't bother to align the sections if we are | |
12874 | targeted for an embedded system. */ | |
12875 | if (strcmp (TARGET_OS, "elf") == 0) | |
12876 | return addr; | |
12877 | if (align > 4) | |
12878 | align = 4; | |
12879 | #endif | |
12880 | ||
12881 | return ((addr + (1 << align) - 1) & (-1 << align)); | |
12882 | } | |
12883 | ||
12884 | /* Utility routine, called from above as well. If called while the | |
12885 | input file is still being read, it's only an approximation. (For | |
12886 | example, a symbol may later become defined which appeared to be | |
12887 | undefined earlier.) */ | |
12888 | ||
12889 | static int | |
17a2f251 | 12890 | nopic_need_relax (symbolS *sym, int before_relaxing) |
252b5132 RH |
12891 | { |
12892 | if (sym == 0) | |
12893 | return 0; | |
12894 | ||
4d0d148d | 12895 | if (g_switch_value > 0) |
252b5132 RH |
12896 | { |
12897 | const char *symname; | |
12898 | int change; | |
12899 | ||
c9914766 | 12900 | /* Find out whether this symbol can be referenced off the $gp |
252b5132 RH |
12901 | register. It can be if it is smaller than the -G size or if |
12902 | it is in the .sdata or .sbss section. Certain symbols can | |
c9914766 | 12903 | not be referenced off the $gp, although it appears as though |
252b5132 RH |
12904 | they can. */ |
12905 | symname = S_GET_NAME (sym); | |
12906 | if (symname != (const char *) NULL | |
12907 | && (strcmp (symname, "eprol") == 0 | |
12908 | || strcmp (symname, "etext") == 0 | |
12909 | || strcmp (symname, "_gp") == 0 | |
12910 | || strcmp (symname, "edata") == 0 | |
12911 | || strcmp (symname, "_fbss") == 0 | |
12912 | || strcmp (symname, "_fdata") == 0 | |
12913 | || strcmp (symname, "_ftext") == 0 | |
12914 | || strcmp (symname, "end") == 0 | |
12915 | || strcmp (symname, "_gp_disp") == 0)) | |
12916 | change = 1; | |
12917 | else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym)) | |
12918 | && (0 | |
12919 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 ILT |
12920 | || (symbol_get_obj (sym)->ecoff_extern_size != 0 |
12921 | && (symbol_get_obj (sym)->ecoff_extern_size | |
12922 | <= g_switch_value)) | |
252b5132 RH |
12923 | #endif |
12924 | /* We must defer this decision until after the whole | |
12925 | file has been read, since there might be a .extern | |
12926 | after the first use of this symbol. */ | |
12927 | || (before_relaxing | |
12928 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 | 12929 | && symbol_get_obj (sym)->ecoff_extern_size == 0 |
252b5132 RH |
12930 | #endif |
12931 | && S_GET_VALUE (sym) == 0) | |
12932 | || (S_GET_VALUE (sym) != 0 | |
12933 | && S_GET_VALUE (sym) <= g_switch_value))) | |
12934 | change = 0; | |
12935 | else | |
12936 | { | |
12937 | const char *segname; | |
12938 | ||
12939 | segname = segment_name (S_GET_SEGMENT (sym)); | |
12940 | assert (strcmp (segname, ".lit8") != 0 | |
12941 | && strcmp (segname, ".lit4") != 0); | |
12942 | change = (strcmp (segname, ".sdata") != 0 | |
fba2b7f9 GK |
12943 | && strcmp (segname, ".sbss") != 0 |
12944 | && strncmp (segname, ".sdata.", 7) != 0 | |
12945 | && strncmp (segname, ".gnu.linkonce.s.", 16) != 0); | |
252b5132 RH |
12946 | } |
12947 | return change; | |
12948 | } | |
12949 | else | |
c9914766 | 12950 | /* We are not optimizing for the $gp register. */ |
252b5132 RH |
12951 | return 1; |
12952 | } | |
12953 | ||
5919d012 RS |
12954 | |
12955 | /* Return true if the given symbol should be considered local for SVR4 PIC. */ | |
12956 | ||
12957 | static bfd_boolean | |
17a2f251 | 12958 | pic_need_relax (symbolS *sym, asection *segtype) |
5919d012 RS |
12959 | { |
12960 | asection *symsec; | |
12961 | bfd_boolean linkonce; | |
12962 | ||
12963 | /* Handle the case of a symbol equated to another symbol. */ | |
12964 | while (symbol_equated_reloc_p (sym)) | |
12965 | { | |
12966 | symbolS *n; | |
12967 | ||
12968 | /* It's possible to get a loop here in a badly written | |
12969 | program. */ | |
12970 | n = symbol_get_value_expression (sym)->X_add_symbol; | |
12971 | if (n == sym) | |
12972 | break; | |
12973 | sym = n; | |
12974 | } | |
12975 | ||
12976 | symsec = S_GET_SEGMENT (sym); | |
12977 | ||
12978 | /* duplicate the test for LINK_ONCE sections as in adjust_reloc_syms */ | |
12979 | linkonce = FALSE; | |
12980 | if (symsec != segtype && ! S_IS_LOCAL (sym)) | |
12981 | { | |
12982 | if ((bfd_get_section_flags (stdoutput, symsec) & SEC_LINK_ONCE) | |
12983 | != 0) | |
12984 | linkonce = TRUE; | |
12985 | ||
12986 | /* The GNU toolchain uses an extension for ELF: a section | |
12987 | beginning with the magic string .gnu.linkonce is a linkonce | |
12988 | section. */ | |
12989 | if (strncmp (segment_name (symsec), ".gnu.linkonce", | |
12990 | sizeof ".gnu.linkonce" - 1) == 0) | |
12991 | linkonce = TRUE; | |
12992 | } | |
12993 | ||
12994 | /* This must duplicate the test in adjust_reloc_syms. */ | |
12995 | return (symsec != &bfd_und_section | |
12996 | && symsec != &bfd_abs_section | |
12997 | && ! bfd_is_com_section (symsec) | |
12998 | && !linkonce | |
12999 | #ifdef OBJ_ELF | |
13000 | /* A global or weak symbol is treated as external. */ | |
13001 | && (OUTPUT_FLAVOR != bfd_target_elf_flavour | |
3e722fb5 | 13002 | || (! S_IS_WEAK (sym) && ! S_IS_EXTERNAL (sym))) |
5919d012 RS |
13003 | #endif |
13004 | ); | |
13005 | } | |
13006 | ||
13007 | ||
252b5132 RH |
13008 | /* Given a mips16 variant frag FRAGP, return non-zero if it needs an |
13009 | extended opcode. SEC is the section the frag is in. */ | |
13010 | ||
13011 | static int | |
17a2f251 | 13012 | mips16_extended_frag (fragS *fragp, asection *sec, long stretch) |
252b5132 RH |
13013 | { |
13014 | int type; | |
13015 | register const struct mips16_immed_operand *op; | |
13016 | offsetT val; | |
13017 | int mintiny, maxtiny; | |
13018 | segT symsec; | |
98aa84af | 13019 | fragS *sym_frag; |
252b5132 RH |
13020 | |
13021 | if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype)) | |
13022 | return 0; | |
13023 | if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype)) | |
13024 | return 1; | |
13025 | ||
13026 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
13027 | op = mips16_immed_operands; | |
13028 | while (op->type != type) | |
13029 | { | |
13030 | ++op; | |
13031 | assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); | |
13032 | } | |
13033 | ||
13034 | if (op->unsp) | |
13035 | { | |
13036 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
13037 | { | |
13038 | mintiny = 1; | |
13039 | maxtiny = 1 << op->nbits; | |
13040 | } | |
13041 | else | |
13042 | { | |
13043 | mintiny = 0; | |
13044 | maxtiny = (1 << op->nbits) - 1; | |
13045 | } | |
13046 | } | |
13047 | else | |
13048 | { | |
13049 | mintiny = - (1 << (op->nbits - 1)); | |
13050 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
13051 | } | |
13052 | ||
98aa84af | 13053 | sym_frag = symbol_get_frag (fragp->fr_symbol); |
ac62c346 | 13054 | val = S_GET_VALUE (fragp->fr_symbol); |
98aa84af | 13055 | symsec = S_GET_SEGMENT (fragp->fr_symbol); |
252b5132 RH |
13056 | |
13057 | if (op->pcrel) | |
13058 | { | |
13059 | addressT addr; | |
13060 | ||
13061 | /* We won't have the section when we are called from | |
13062 | mips_relax_frag. However, we will always have been called | |
13063 | from md_estimate_size_before_relax first. If this is a | |
13064 | branch to a different section, we mark it as such. If SEC is | |
13065 | NULL, and the frag is not marked, then it must be a branch to | |
13066 | the same section. */ | |
13067 | if (sec == NULL) | |
13068 | { | |
13069 | if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype)) | |
13070 | return 1; | |
13071 | } | |
13072 | else | |
13073 | { | |
98aa84af | 13074 | /* Must have been called from md_estimate_size_before_relax. */ |
252b5132 RH |
13075 | if (symsec != sec) |
13076 | { | |
13077 | fragp->fr_subtype = | |
13078 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
13079 | ||
13080 | /* FIXME: We should support this, and let the linker | |
13081 | catch branches and loads that are out of range. */ | |
13082 | as_bad_where (fragp->fr_file, fragp->fr_line, | |
13083 | _("unsupported PC relative reference to different section")); | |
13084 | ||
13085 | return 1; | |
13086 | } | |
98aa84af AM |
13087 | if (fragp != sym_frag && sym_frag->fr_address == 0) |
13088 | /* Assume non-extended on the first relaxation pass. | |
13089 | The address we have calculated will be bogus if this is | |
13090 | a forward branch to another frag, as the forward frag | |
13091 | will have fr_address == 0. */ | |
13092 | return 0; | |
252b5132 RH |
13093 | } |
13094 | ||
13095 | /* In this case, we know for sure that the symbol fragment is in | |
98aa84af AM |
13096 | the same section. If the relax_marker of the symbol fragment |
13097 | differs from the relax_marker of this fragment, we have not | |
13098 | yet adjusted the symbol fragment fr_address. We want to add | |
252b5132 RH |
13099 | in STRETCH in order to get a better estimate of the address. |
13100 | This particularly matters because of the shift bits. */ | |
13101 | if (stretch != 0 | |
98aa84af | 13102 | && sym_frag->relax_marker != fragp->relax_marker) |
252b5132 RH |
13103 | { |
13104 | fragS *f; | |
13105 | ||
13106 | /* Adjust stretch for any alignment frag. Note that if have | |
13107 | been expanding the earlier code, the symbol may be | |
13108 | defined in what appears to be an earlier frag. FIXME: | |
13109 | This doesn't handle the fr_subtype field, which specifies | |
13110 | a maximum number of bytes to skip when doing an | |
13111 | alignment. */ | |
98aa84af | 13112 | for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next) |
252b5132 RH |
13113 | { |
13114 | if (f->fr_type == rs_align || f->fr_type == rs_align_code) | |
13115 | { | |
13116 | if (stretch < 0) | |
13117 | stretch = - ((- stretch) | |
13118 | & ~ ((1 << (int) f->fr_offset) - 1)); | |
13119 | else | |
13120 | stretch &= ~ ((1 << (int) f->fr_offset) - 1); | |
13121 | if (stretch == 0) | |
13122 | break; | |
13123 | } | |
13124 | } | |
13125 | if (f != NULL) | |
13126 | val += stretch; | |
13127 | } | |
13128 | ||
13129 | addr = fragp->fr_address + fragp->fr_fix; | |
13130 | ||
13131 | /* The base address rules are complicated. The base address of | |
13132 | a branch is the following instruction. The base address of a | |
13133 | PC relative load or add is the instruction itself, but if it | |
13134 | is in a delay slot (in which case it can not be extended) use | |
13135 | the address of the instruction whose delay slot it is in. */ | |
13136 | if (type == 'p' || type == 'q') | |
13137 | { | |
13138 | addr += 2; | |
13139 | ||
13140 | /* If we are currently assuming that this frag should be | |
13141 | extended, then, the current address is two bytes | |
bdaaa2e1 | 13142 | higher. */ |
252b5132 RH |
13143 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) |
13144 | addr += 2; | |
13145 | ||
13146 | /* Ignore the low bit in the target, since it will be set | |
13147 | for a text label. */ | |
13148 | if ((val & 1) != 0) | |
13149 | --val; | |
13150 | } | |
13151 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) | |
13152 | addr -= 4; | |
13153 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
13154 | addr -= 2; | |
13155 | ||
13156 | val -= addr & ~ ((1 << op->shift) - 1); | |
13157 | ||
13158 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
13159 | if (type == 'p' || type == 'q') | |
13160 | val /= 2; | |
13161 | ||
13162 | /* If any of the shifted bits are set, we must use an extended | |
13163 | opcode. If the address depends on the size of this | |
13164 | instruction, this can lead to a loop, so we arrange to always | |
13165 | use an extended opcode. We only check this when we are in | |
13166 | the main relaxation loop, when SEC is NULL. */ | |
13167 | if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL) | |
13168 | { | |
13169 | fragp->fr_subtype = | |
13170 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
13171 | return 1; | |
13172 | } | |
13173 | ||
13174 | /* If we are about to mark a frag as extended because the value | |
13175 | is precisely maxtiny + 1, then there is a chance of an | |
13176 | infinite loop as in the following code: | |
13177 | la $4,foo | |
13178 | .skip 1020 | |
13179 | .align 2 | |
13180 | foo: | |
13181 | In this case when the la is extended, foo is 0x3fc bytes | |
13182 | away, so the la can be shrunk, but then foo is 0x400 away, so | |
13183 | the la must be extended. To avoid this loop, we mark the | |
13184 | frag as extended if it was small, and is about to become | |
13185 | extended with a value of maxtiny + 1. */ | |
13186 | if (val == ((maxtiny + 1) << op->shift) | |
13187 | && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype) | |
13188 | && sec == NULL) | |
13189 | { | |
13190 | fragp->fr_subtype = | |
13191 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
13192 | return 1; | |
13193 | } | |
13194 | } | |
13195 | else if (symsec != absolute_section && sec != NULL) | |
13196 | as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation")); | |
13197 | ||
13198 | if ((val & ((1 << op->shift) - 1)) != 0 | |
13199 | || val < (mintiny << op->shift) | |
13200 | || val > (maxtiny << op->shift)) | |
13201 | return 1; | |
13202 | else | |
13203 | return 0; | |
13204 | } | |
13205 | ||
4a6a3df4 AO |
13206 | /* Compute the length of a branch sequence, and adjust the |
13207 | RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the | |
13208 | worst-case length is computed, with UPDATE being used to indicate | |
13209 | whether an unconditional (-1), branch-likely (+1) or regular (0) | |
13210 | branch is to be computed. */ | |
13211 | static int | |
17a2f251 | 13212 | relaxed_branch_length (fragS *fragp, asection *sec, int update) |
4a6a3df4 | 13213 | { |
b34976b6 | 13214 | bfd_boolean toofar; |
4a6a3df4 AO |
13215 | int length; |
13216 | ||
13217 | if (fragp | |
13218 | && S_IS_DEFINED (fragp->fr_symbol) | |
13219 | && sec == S_GET_SEGMENT (fragp->fr_symbol)) | |
13220 | { | |
13221 | addressT addr; | |
13222 | offsetT val; | |
13223 | ||
13224 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; | |
13225 | ||
13226 | addr = fragp->fr_address + fragp->fr_fix + 4; | |
13227 | ||
13228 | val -= addr; | |
13229 | ||
13230 | toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2); | |
13231 | } | |
13232 | else if (fragp) | |
13233 | /* If the symbol is not defined or it's in a different segment, | |
13234 | assume the user knows what's going on and emit a short | |
13235 | branch. */ | |
b34976b6 | 13236 | toofar = FALSE; |
4a6a3df4 | 13237 | else |
b34976b6 | 13238 | toofar = TRUE; |
4a6a3df4 AO |
13239 | |
13240 | if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) | |
13241 | fragp->fr_subtype | |
af6ae2ad | 13242 | = RELAX_BRANCH_ENCODE (RELAX_BRANCH_UNCOND (fragp->fr_subtype), |
4a6a3df4 AO |
13243 | RELAX_BRANCH_LIKELY (fragp->fr_subtype), |
13244 | RELAX_BRANCH_LINK (fragp->fr_subtype), | |
13245 | toofar); | |
13246 | ||
13247 | length = 4; | |
13248 | if (toofar) | |
13249 | { | |
13250 | if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0)) | |
13251 | length += 8; | |
13252 | ||
13253 | if (mips_pic != NO_PIC) | |
13254 | { | |
13255 | /* Additional space for PIC loading of target address. */ | |
13256 | length += 8; | |
13257 | if (mips_opts.isa == ISA_MIPS1) | |
13258 | /* Additional space for $at-stabilizing nop. */ | |
13259 | length += 4; | |
13260 | } | |
13261 | ||
13262 | /* If branch is conditional. */ | |
13263 | if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0)) | |
13264 | length += 8; | |
13265 | } | |
b34976b6 | 13266 | |
4a6a3df4 AO |
13267 | return length; |
13268 | } | |
13269 | ||
252b5132 RH |
13270 | /* Estimate the size of a frag before relaxing. Unless this is the |
13271 | mips16, we are not really relaxing here, and the final size is | |
13272 | encoded in the subtype information. For the mips16, we have to | |
13273 | decide whether we are using an extended opcode or not. */ | |
13274 | ||
252b5132 | 13275 | int |
17a2f251 | 13276 | md_estimate_size_before_relax (fragS *fragp, asection *segtype) |
252b5132 | 13277 | { |
5919d012 | 13278 | int change; |
252b5132 | 13279 | |
4a6a3df4 AO |
13280 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
13281 | { | |
13282 | ||
b34976b6 AM |
13283 | fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE); |
13284 | ||
4a6a3df4 AO |
13285 | return fragp->fr_var; |
13286 | } | |
13287 | ||
252b5132 | 13288 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
177b4a6a AO |
13289 | /* We don't want to modify the EXTENDED bit here; it might get us |
13290 | into infinite loops. We change it only in mips_relax_frag(). */ | |
13291 | return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2); | |
252b5132 RH |
13292 | |
13293 | if (mips_pic == NO_PIC) | |
5919d012 | 13294 | change = nopic_need_relax (fragp->fr_symbol, 0); |
252b5132 | 13295 | else if (mips_pic == SVR4_PIC) |
5919d012 | 13296 | change = pic_need_relax (fragp->fr_symbol, segtype); |
0a44bf69 RS |
13297 | else if (mips_pic == VXWORKS_PIC) |
13298 | /* For vxworks, GOT16 relocations never have a corresponding LO16. */ | |
13299 | change = 0; | |
252b5132 RH |
13300 | else |
13301 | abort (); | |
13302 | ||
13303 | if (change) | |
13304 | { | |
4d7206a2 | 13305 | fragp->fr_subtype |= RELAX_USE_SECOND; |
4d7206a2 | 13306 | return -RELAX_FIRST (fragp->fr_subtype); |
252b5132 | 13307 | } |
4d7206a2 RS |
13308 | else |
13309 | return -RELAX_SECOND (fragp->fr_subtype); | |
252b5132 RH |
13310 | } |
13311 | ||
13312 | /* This is called to see whether a reloc against a defined symbol | |
de7e6852 | 13313 | should be converted into a reloc against a section. */ |
252b5132 RH |
13314 | |
13315 | int | |
17a2f251 | 13316 | mips_fix_adjustable (fixS *fixp) |
252b5132 | 13317 | { |
de7e6852 RS |
13318 | /* Don't adjust MIPS16 jump relocations, so we don't have to worry |
13319 | about the format of the offset in the .o file. */ | |
252b5132 RH |
13320 | if (fixp->fx_r_type == BFD_RELOC_MIPS16_JMP) |
13321 | return 0; | |
a161fe53 | 13322 | |
252b5132 RH |
13323 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
13324 | || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
13325 | return 0; | |
a161fe53 | 13326 | |
252b5132 RH |
13327 | if (fixp->fx_addsy == NULL) |
13328 | return 1; | |
a161fe53 | 13329 | |
de7e6852 RS |
13330 | /* If symbol SYM is in a mergeable section, relocations of the form |
13331 | SYM + 0 can usually be made section-relative. The mergeable data | |
13332 | is then identified by the section offset rather than by the symbol. | |
13333 | ||
13334 | However, if we're generating REL LO16 relocations, the offset is split | |
13335 | between the LO16 and parterning high part relocation. The linker will | |
13336 | need to recalculate the complete offset in order to correctly identify | |
13337 | the merge data. | |
13338 | ||
13339 | The linker has traditionally not looked for the parterning high part | |
13340 | relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be | |
13341 | placed anywhere. Rather than break backwards compatibility by changing | |
13342 | this, it seems better not to force the issue, and instead keep the | |
13343 | original symbol. This will work with either linker behavior. */ | |
704803a9 MR |
13344 | if ((fixp->fx_r_type == BFD_RELOC_LO16 |
13345 | || fixp->fx_r_type == BFD_RELOC_MIPS16_LO16 | |
13346 | || reloc_needs_lo_p (fixp->fx_r_type)) | |
de7e6852 RS |
13347 | && HAVE_IN_PLACE_ADDENDS |
13348 | && (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_MERGE) != 0) | |
13349 | return 0; | |
13350 | ||
252b5132 | 13351 | #ifdef OBJ_ELF |
de7e6852 RS |
13352 | /* Don't adjust relocations against mips16 symbols, so that the linker |
13353 | can find them if it needs to set up a stub. */ | |
252b5132 RH |
13354 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour |
13355 | && S_GET_OTHER (fixp->fx_addsy) == STO_MIPS16 | |
13356 | && fixp->fx_subsy == NULL) | |
13357 | return 0; | |
13358 | #endif | |
a161fe53 | 13359 | |
252b5132 RH |
13360 | return 1; |
13361 | } | |
13362 | ||
13363 | /* Translate internal representation of relocation info to BFD target | |
13364 | format. */ | |
13365 | ||
13366 | arelent ** | |
17a2f251 | 13367 | tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) |
252b5132 RH |
13368 | { |
13369 | static arelent *retval[4]; | |
13370 | arelent *reloc; | |
13371 | bfd_reloc_code_real_type code; | |
13372 | ||
4b0cff4e TS |
13373 | memset (retval, 0, sizeof(retval)); |
13374 | reloc = retval[0] = (arelent *) xcalloc (1, sizeof (arelent)); | |
49309057 ILT |
13375 | reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); |
13376 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
252b5132 RH |
13377 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; |
13378 | ||
bad36eac DJ |
13379 | if (fixp->fx_pcrel) |
13380 | { | |
13381 | assert (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2); | |
13382 | ||
13383 | /* At this point, fx_addnumber is "symbol offset - pcrel address". | |
13384 | Relocations want only the symbol offset. */ | |
13385 | reloc->addend = fixp->fx_addnumber + reloc->address; | |
13386 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
13387 | { | |
13388 | /* A gruesome hack which is a result of the gruesome gas | |
13389 | reloc handling. What's worse, for COFF (as opposed to | |
13390 | ECOFF), we might need yet another copy of reloc->address. | |
13391 | See bfd_install_relocation. */ | |
13392 | reloc->addend += reloc->address; | |
13393 | } | |
13394 | } | |
13395 | else | |
13396 | reloc->addend = fixp->fx_addnumber; | |
252b5132 | 13397 | |
438c16b8 TS |
13398 | /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable |
13399 | entry to be used in the relocation's section offset. */ | |
13400 | if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
252b5132 RH |
13401 | { |
13402 | reloc->address = reloc->addend; | |
13403 | reloc->addend = 0; | |
13404 | } | |
13405 | ||
252b5132 | 13406 | code = fixp->fx_r_type; |
252b5132 | 13407 | |
bad36eac | 13408 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); |
252b5132 RH |
13409 | if (reloc->howto == NULL) |
13410 | { | |
13411 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
13412 | _("Can not represent %s relocation in this object file format"), | |
13413 | bfd_get_reloc_code_name (code)); | |
13414 | retval[0] = NULL; | |
13415 | } | |
13416 | ||
13417 | return retval; | |
13418 | } | |
13419 | ||
13420 | /* Relax a machine dependent frag. This returns the amount by which | |
13421 | the current size of the frag should change. */ | |
13422 | ||
13423 | int | |
17a2f251 | 13424 | mips_relax_frag (asection *sec, fragS *fragp, long stretch) |
252b5132 | 13425 | { |
4a6a3df4 AO |
13426 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
13427 | { | |
13428 | offsetT old_var = fragp->fr_var; | |
b34976b6 AM |
13429 | |
13430 | fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE); | |
4a6a3df4 AO |
13431 | |
13432 | return fragp->fr_var - old_var; | |
13433 | } | |
13434 | ||
252b5132 RH |
13435 | if (! RELAX_MIPS16_P (fragp->fr_subtype)) |
13436 | return 0; | |
13437 | ||
c4e7957c | 13438 | if (mips16_extended_frag (fragp, NULL, stretch)) |
252b5132 RH |
13439 | { |
13440 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
13441 | return 0; | |
13442 | fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype); | |
13443 | return 2; | |
13444 | } | |
13445 | else | |
13446 | { | |
13447 | if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
13448 | return 0; | |
13449 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype); | |
13450 | return -2; | |
13451 | } | |
13452 | ||
13453 | return 0; | |
13454 | } | |
13455 | ||
13456 | /* Convert a machine dependent frag. */ | |
13457 | ||
13458 | void | |
17a2f251 | 13459 | md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp) |
252b5132 | 13460 | { |
4a6a3df4 AO |
13461 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
13462 | { | |
13463 | bfd_byte *buf; | |
13464 | unsigned long insn; | |
13465 | expressionS exp; | |
13466 | fixS *fixp; | |
b34976b6 | 13467 | |
4a6a3df4 AO |
13468 | buf = (bfd_byte *)fragp->fr_literal + fragp->fr_fix; |
13469 | ||
13470 | if (target_big_endian) | |
13471 | insn = bfd_getb32 (buf); | |
13472 | else | |
13473 | insn = bfd_getl32 (buf); | |
b34976b6 | 13474 | |
4a6a3df4 AO |
13475 | if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) |
13476 | { | |
13477 | /* We generate a fixup instead of applying it right now | |
13478 | because, if there are linker relaxations, we're going to | |
13479 | need the relocations. */ | |
13480 | exp.X_op = O_symbol; | |
13481 | exp.X_add_symbol = fragp->fr_symbol; | |
13482 | exp.X_add_number = fragp->fr_offset; | |
13483 | ||
13484 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
bad36eac | 13485 | 4, &exp, 1, BFD_RELOC_16_PCREL_S2); |
4a6a3df4 AO |
13486 | fixp->fx_file = fragp->fr_file; |
13487 | fixp->fx_line = fragp->fr_line; | |
b34976b6 | 13488 | |
2132e3a3 | 13489 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
13490 | buf += 4; |
13491 | } | |
13492 | else | |
13493 | { | |
13494 | int i; | |
13495 | ||
13496 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
13497 | _("relaxed out-of-range branch into a jump")); | |
13498 | ||
13499 | if (RELAX_BRANCH_UNCOND (fragp->fr_subtype)) | |
13500 | goto uncond; | |
13501 | ||
13502 | if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
13503 | { | |
13504 | /* Reverse the branch. */ | |
13505 | switch ((insn >> 28) & 0xf) | |
13506 | { | |
13507 | case 4: | |
13508 | /* bc[0-3][tf]l? and bc1any[24][ft] instructions can | |
13509 | have the condition reversed by tweaking a single | |
13510 | bit, and their opcodes all have 0x4???????. */ | |
13511 | assert ((insn & 0xf1000000) == 0x41000000); | |
13512 | insn ^= 0x00010000; | |
13513 | break; | |
13514 | ||
13515 | case 0: | |
13516 | /* bltz 0x04000000 bgez 0x04010000 | |
13517 | bltzal 0x04100000 bgezal 0x04110000 */ | |
13518 | assert ((insn & 0xfc0e0000) == 0x04000000); | |
13519 | insn ^= 0x00010000; | |
13520 | break; | |
b34976b6 | 13521 | |
4a6a3df4 AO |
13522 | case 1: |
13523 | /* beq 0x10000000 bne 0x14000000 | |
13524 | blez 0x18000000 bgtz 0x1c000000 */ | |
13525 | insn ^= 0x04000000; | |
13526 | break; | |
13527 | ||
13528 | default: | |
13529 | abort (); | |
13530 | } | |
13531 | } | |
13532 | ||
13533 | if (RELAX_BRANCH_LINK (fragp->fr_subtype)) | |
13534 | { | |
13535 | /* Clear the and-link bit. */ | |
13536 | assert ((insn & 0xfc1c0000) == 0x04100000); | |
13537 | ||
13538 | /* bltzal 0x04100000 bgezal 0x04110000 | |
13539 | bltzall 0x04120000 bgezall 0x04130000 */ | |
13540 | insn &= ~0x00100000; | |
13541 | } | |
13542 | ||
13543 | /* Branch over the branch (if the branch was likely) or the | |
13544 | full jump (not likely case). Compute the offset from the | |
13545 | current instruction to branch to. */ | |
13546 | if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
13547 | i = 16; | |
13548 | else | |
13549 | { | |
13550 | /* How many bytes in instructions we've already emitted? */ | |
13551 | i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix; | |
13552 | /* How many bytes in instructions from here to the end? */ | |
13553 | i = fragp->fr_var - i; | |
13554 | } | |
13555 | /* Convert to instruction count. */ | |
13556 | i >>= 2; | |
13557 | /* Branch counts from the next instruction. */ | |
b34976b6 | 13558 | i--; |
4a6a3df4 AO |
13559 | insn |= i; |
13560 | /* Branch over the jump. */ | |
2132e3a3 | 13561 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
13562 | buf += 4; |
13563 | ||
13564 | /* Nop */ | |
2132e3a3 | 13565 | md_number_to_chars ((char *) buf, 0, 4); |
4a6a3df4 AO |
13566 | buf += 4; |
13567 | ||
13568 | if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
13569 | { | |
13570 | /* beql $0, $0, 2f */ | |
13571 | insn = 0x50000000; | |
13572 | /* Compute the PC offset from the current instruction to | |
13573 | the end of the variable frag. */ | |
13574 | /* How many bytes in instructions we've already emitted? */ | |
13575 | i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix; | |
13576 | /* How many bytes in instructions from here to the end? */ | |
13577 | i = fragp->fr_var - i; | |
13578 | /* Convert to instruction count. */ | |
13579 | i >>= 2; | |
13580 | /* Don't decrement i, because we want to branch over the | |
13581 | delay slot. */ | |
13582 | ||
13583 | insn |= i; | |
2132e3a3 | 13584 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
13585 | buf += 4; |
13586 | ||
2132e3a3 | 13587 | md_number_to_chars ((char *) buf, 0, 4); |
4a6a3df4 AO |
13588 | buf += 4; |
13589 | } | |
13590 | ||
13591 | uncond: | |
13592 | if (mips_pic == NO_PIC) | |
13593 | { | |
13594 | /* j or jal. */ | |
13595 | insn = (RELAX_BRANCH_LINK (fragp->fr_subtype) | |
13596 | ? 0x0c000000 : 0x08000000); | |
13597 | exp.X_op = O_symbol; | |
13598 | exp.X_add_symbol = fragp->fr_symbol; | |
13599 | exp.X_add_number = fragp->fr_offset; | |
13600 | ||
13601 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
13602 | 4, &exp, 0, BFD_RELOC_MIPS_JMP); | |
13603 | fixp->fx_file = fragp->fr_file; | |
13604 | fixp->fx_line = fragp->fr_line; | |
13605 | ||
2132e3a3 | 13606 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
13607 | buf += 4; |
13608 | } | |
13609 | else | |
13610 | { | |
13611 | /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */ | |
13612 | insn = HAVE_64BIT_ADDRESSES ? 0xdf810000 : 0x8f810000; | |
13613 | exp.X_op = O_symbol; | |
13614 | exp.X_add_symbol = fragp->fr_symbol; | |
13615 | exp.X_add_number = fragp->fr_offset; | |
13616 | ||
13617 | if (fragp->fr_offset) | |
13618 | { | |
13619 | exp.X_add_symbol = make_expr_symbol (&exp); | |
13620 | exp.X_add_number = 0; | |
13621 | } | |
13622 | ||
13623 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
13624 | 4, &exp, 0, BFD_RELOC_MIPS_GOT16); | |
13625 | fixp->fx_file = fragp->fr_file; | |
13626 | fixp->fx_line = fragp->fr_line; | |
13627 | ||
2132e3a3 | 13628 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 | 13629 | buf += 4; |
b34976b6 | 13630 | |
4a6a3df4 AO |
13631 | if (mips_opts.isa == ISA_MIPS1) |
13632 | { | |
13633 | /* nop */ | |
2132e3a3 | 13634 | md_number_to_chars ((char *) buf, 0, 4); |
4a6a3df4 AO |
13635 | buf += 4; |
13636 | } | |
13637 | ||
13638 | /* d/addiu $at, $at, <sym> R_MIPS_LO16 */ | |
13639 | insn = HAVE_64BIT_ADDRESSES ? 0x64210000 : 0x24210000; | |
13640 | ||
13641 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
13642 | 4, &exp, 0, BFD_RELOC_LO16); | |
13643 | fixp->fx_file = fragp->fr_file; | |
13644 | fixp->fx_line = fragp->fr_line; | |
b34976b6 | 13645 | |
2132e3a3 | 13646 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
13647 | buf += 4; |
13648 | ||
13649 | /* j(al)r $at. */ | |
13650 | if (RELAX_BRANCH_LINK (fragp->fr_subtype)) | |
13651 | insn = 0x0020f809; | |
13652 | else | |
13653 | insn = 0x00200008; | |
13654 | ||
2132e3a3 | 13655 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
13656 | buf += 4; |
13657 | } | |
13658 | } | |
13659 | ||
13660 | assert (buf == (bfd_byte *)fragp->fr_literal | |
13661 | + fragp->fr_fix + fragp->fr_var); | |
13662 | ||
13663 | fragp->fr_fix += fragp->fr_var; | |
13664 | ||
13665 | return; | |
13666 | } | |
13667 | ||
252b5132 RH |
13668 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
13669 | { | |
13670 | int type; | |
13671 | register const struct mips16_immed_operand *op; | |
b34976b6 | 13672 | bfd_boolean small, ext; |
252b5132 RH |
13673 | offsetT val; |
13674 | bfd_byte *buf; | |
13675 | unsigned long insn; | |
b34976b6 | 13676 | bfd_boolean use_extend; |
252b5132 RH |
13677 | unsigned short extend; |
13678 | ||
13679 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
13680 | op = mips16_immed_operands; | |
13681 | while (op->type != type) | |
13682 | ++op; | |
13683 | ||
13684 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
13685 | { | |
b34976b6 AM |
13686 | small = FALSE; |
13687 | ext = TRUE; | |
252b5132 RH |
13688 | } |
13689 | else | |
13690 | { | |
b34976b6 AM |
13691 | small = TRUE; |
13692 | ext = FALSE; | |
252b5132 RH |
13693 | } |
13694 | ||
6386f3a7 | 13695 | resolve_symbol_value (fragp->fr_symbol); |
252b5132 RH |
13696 | val = S_GET_VALUE (fragp->fr_symbol); |
13697 | if (op->pcrel) | |
13698 | { | |
13699 | addressT addr; | |
13700 | ||
13701 | addr = fragp->fr_address + fragp->fr_fix; | |
13702 | ||
13703 | /* The rules for the base address of a PC relative reloc are | |
13704 | complicated; see mips16_extended_frag. */ | |
13705 | if (type == 'p' || type == 'q') | |
13706 | { | |
13707 | addr += 2; | |
13708 | if (ext) | |
13709 | addr += 2; | |
13710 | /* Ignore the low bit in the target, since it will be | |
13711 | set for a text label. */ | |
13712 | if ((val & 1) != 0) | |
13713 | --val; | |
13714 | } | |
13715 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) | |
13716 | addr -= 4; | |
13717 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
13718 | addr -= 2; | |
13719 | ||
13720 | addr &= ~ (addressT) ((1 << op->shift) - 1); | |
13721 | val -= addr; | |
13722 | ||
13723 | /* Make sure the section winds up with the alignment we have | |
13724 | assumed. */ | |
13725 | if (op->shift > 0) | |
13726 | record_alignment (asec, op->shift); | |
13727 | } | |
13728 | ||
13729 | if (ext | |
13730 | && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype) | |
13731 | || RELAX_MIPS16_DSLOT (fragp->fr_subtype))) | |
13732 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
13733 | _("extended instruction in delay slot")); | |
13734 | ||
13735 | buf = (bfd_byte *) (fragp->fr_literal + fragp->fr_fix); | |
13736 | ||
13737 | if (target_big_endian) | |
13738 | insn = bfd_getb16 (buf); | |
13739 | else | |
13740 | insn = bfd_getl16 (buf); | |
13741 | ||
13742 | mips16_immed (fragp->fr_file, fragp->fr_line, type, val, | |
13743 | RELAX_MIPS16_USER_EXT (fragp->fr_subtype), | |
13744 | small, ext, &insn, &use_extend, &extend); | |
13745 | ||
13746 | if (use_extend) | |
13747 | { | |
2132e3a3 | 13748 | md_number_to_chars ((char *) buf, 0xf000 | extend, 2); |
252b5132 RH |
13749 | fragp->fr_fix += 2; |
13750 | buf += 2; | |
13751 | } | |
13752 | ||
2132e3a3 | 13753 | md_number_to_chars ((char *) buf, insn, 2); |
252b5132 RH |
13754 | fragp->fr_fix += 2; |
13755 | buf += 2; | |
13756 | } | |
13757 | else | |
13758 | { | |
4d7206a2 RS |
13759 | int first, second; |
13760 | fixS *fixp; | |
252b5132 | 13761 | |
4d7206a2 RS |
13762 | first = RELAX_FIRST (fragp->fr_subtype); |
13763 | second = RELAX_SECOND (fragp->fr_subtype); | |
13764 | fixp = (fixS *) fragp->fr_opcode; | |
252b5132 | 13765 | |
584892a6 RS |
13766 | /* Possibly emit a warning if we've chosen the longer option. */ |
13767 | if (((fragp->fr_subtype & RELAX_USE_SECOND) != 0) | |
13768 | == ((fragp->fr_subtype & RELAX_SECOND_LONGER) != 0)) | |
13769 | { | |
13770 | const char *msg = macro_warning (fragp->fr_subtype); | |
13771 | if (msg != 0) | |
13772 | as_warn_where (fragp->fr_file, fragp->fr_line, msg); | |
13773 | } | |
13774 | ||
4d7206a2 RS |
13775 | /* Go through all the fixups for the first sequence. Disable them |
13776 | (by marking them as done) if we're going to use the second | |
13777 | sequence instead. */ | |
13778 | while (fixp | |
13779 | && fixp->fx_frag == fragp | |
13780 | && fixp->fx_where < fragp->fr_fix - second) | |
13781 | { | |
13782 | if (fragp->fr_subtype & RELAX_USE_SECOND) | |
13783 | fixp->fx_done = 1; | |
13784 | fixp = fixp->fx_next; | |
13785 | } | |
252b5132 | 13786 | |
4d7206a2 RS |
13787 | /* Go through the fixups for the second sequence. Disable them if |
13788 | we're going to use the first sequence, otherwise adjust their | |
13789 | addresses to account for the relaxation. */ | |
13790 | while (fixp && fixp->fx_frag == fragp) | |
13791 | { | |
13792 | if (fragp->fr_subtype & RELAX_USE_SECOND) | |
13793 | fixp->fx_where -= first; | |
13794 | else | |
13795 | fixp->fx_done = 1; | |
13796 | fixp = fixp->fx_next; | |
13797 | } | |
13798 | ||
13799 | /* Now modify the frag contents. */ | |
13800 | if (fragp->fr_subtype & RELAX_USE_SECOND) | |
13801 | { | |
13802 | char *start; | |
13803 | ||
13804 | start = fragp->fr_literal + fragp->fr_fix - first - second; | |
13805 | memmove (start, start + first, second); | |
13806 | fragp->fr_fix -= first; | |
13807 | } | |
13808 | else | |
13809 | fragp->fr_fix -= second; | |
252b5132 RH |
13810 | } |
13811 | } | |
13812 | ||
13813 | #ifdef OBJ_ELF | |
13814 | ||
13815 | /* This function is called after the relocs have been generated. | |
13816 | We've been storing mips16 text labels as odd. Here we convert them | |
13817 | back to even for the convenience of the debugger. */ | |
13818 | ||
13819 | void | |
17a2f251 | 13820 | mips_frob_file_after_relocs (void) |
252b5132 RH |
13821 | { |
13822 | asymbol **syms; | |
13823 | unsigned int count, i; | |
13824 | ||
13825 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
13826 | return; | |
13827 | ||
13828 | syms = bfd_get_outsymbols (stdoutput); | |
13829 | count = bfd_get_symcount (stdoutput); | |
13830 | for (i = 0; i < count; i++, syms++) | |
13831 | { | |
13832 | if (elf_symbol (*syms)->internal_elf_sym.st_other == STO_MIPS16 | |
13833 | && ((*syms)->value & 1) != 0) | |
13834 | { | |
13835 | (*syms)->value &= ~1; | |
13836 | /* If the symbol has an odd size, it was probably computed | |
13837 | incorrectly, so adjust that as well. */ | |
13838 | if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0) | |
13839 | ++elf_symbol (*syms)->internal_elf_sym.st_size; | |
13840 | } | |
13841 | } | |
13842 | } | |
13843 | ||
13844 | #endif | |
13845 | ||
13846 | /* This function is called whenever a label is defined. It is used | |
13847 | when handling branch delays; if a branch has a label, we assume we | |
13848 | can not move it. */ | |
13849 | ||
13850 | void | |
17a2f251 | 13851 | mips_define_label (symbolS *sym) |
252b5132 RH |
13852 | { |
13853 | struct insn_label_list *l; | |
13854 | ||
13855 | if (free_insn_labels == NULL) | |
13856 | l = (struct insn_label_list *) xmalloc (sizeof *l); | |
13857 | else | |
13858 | { | |
13859 | l = free_insn_labels; | |
13860 | free_insn_labels = l->next; | |
13861 | } | |
13862 | ||
13863 | l->label = sym; | |
13864 | l->next = insn_labels; | |
13865 | insn_labels = l; | |
07a53e5c RH |
13866 | |
13867 | #ifdef OBJ_ELF | |
13868 | dwarf2_emit_label (sym); | |
13869 | #endif | |
252b5132 RH |
13870 | } |
13871 | \f | |
13872 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
13873 | ||
13874 | /* Some special processing for a MIPS ELF file. */ | |
13875 | ||
13876 | void | |
17a2f251 | 13877 | mips_elf_final_processing (void) |
252b5132 RH |
13878 | { |
13879 | /* Write out the register information. */ | |
316f5878 | 13880 | if (mips_abi != N64_ABI) |
252b5132 RH |
13881 | { |
13882 | Elf32_RegInfo s; | |
13883 | ||
13884 | s.ri_gprmask = mips_gprmask; | |
13885 | s.ri_cprmask[0] = mips_cprmask[0]; | |
13886 | s.ri_cprmask[1] = mips_cprmask[1]; | |
13887 | s.ri_cprmask[2] = mips_cprmask[2]; | |
13888 | s.ri_cprmask[3] = mips_cprmask[3]; | |
13889 | /* The gp_value field is set by the MIPS ELF backend. */ | |
13890 | ||
13891 | bfd_mips_elf32_swap_reginfo_out (stdoutput, &s, | |
13892 | ((Elf32_External_RegInfo *) | |
13893 | mips_regmask_frag)); | |
13894 | } | |
13895 | else | |
13896 | { | |
13897 | Elf64_Internal_RegInfo s; | |
13898 | ||
13899 | s.ri_gprmask = mips_gprmask; | |
13900 | s.ri_pad = 0; | |
13901 | s.ri_cprmask[0] = mips_cprmask[0]; | |
13902 | s.ri_cprmask[1] = mips_cprmask[1]; | |
13903 | s.ri_cprmask[2] = mips_cprmask[2]; | |
13904 | s.ri_cprmask[3] = mips_cprmask[3]; | |
13905 | /* The gp_value field is set by the MIPS ELF backend. */ | |
13906 | ||
13907 | bfd_mips_elf64_swap_reginfo_out (stdoutput, &s, | |
13908 | ((Elf64_External_RegInfo *) | |
13909 | mips_regmask_frag)); | |
13910 | } | |
13911 | ||
13912 | /* Set the MIPS ELF flag bits. FIXME: There should probably be some | |
13913 | sort of BFD interface for this. */ | |
13914 | if (mips_any_noreorder) | |
13915 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER; | |
13916 | if (mips_pic != NO_PIC) | |
143d77c5 | 13917 | { |
252b5132 | 13918 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC; |
143d77c5 EC |
13919 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC; |
13920 | } | |
13921 | if (mips_abicalls) | |
13922 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC; | |
252b5132 | 13923 | |
98d3f06f | 13924 | /* Set MIPS ELF flags for ASEs. */ |
74cd071d CF |
13925 | /* We may need to define a new flag for DSP ASE, and set this flag when |
13926 | file_ase_dsp is true. */ | |
ef2e4d86 CF |
13927 | /* We may need to define a new flag for MT ASE, and set this flag when |
13928 | file_ase_mt is true. */ | |
a4672219 TS |
13929 | if (file_ase_mips16) |
13930 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16; | |
1f25f5d3 CD |
13931 | #if 0 /* XXX FIXME */ |
13932 | if (file_ase_mips3d) | |
13933 | elf_elfheader (stdoutput)->e_flags |= ???; | |
13934 | #endif | |
deec1734 CD |
13935 | if (file_ase_mdmx) |
13936 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX; | |
1f25f5d3 | 13937 | |
bdaaa2e1 | 13938 | /* Set the MIPS ELF ABI flags. */ |
316f5878 | 13939 | if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32) |
252b5132 | 13940 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32; |
316f5878 | 13941 | else if (mips_abi == O64_ABI) |
252b5132 | 13942 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64; |
316f5878 | 13943 | else if (mips_abi == EABI_ABI) |
252b5132 | 13944 | { |
316f5878 | 13945 | if (!file_mips_gp32) |
252b5132 RH |
13946 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64; |
13947 | else | |
13948 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32; | |
13949 | } | |
316f5878 | 13950 | else if (mips_abi == N32_ABI) |
be00bddd TS |
13951 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2; |
13952 | ||
c9914766 | 13953 | /* Nothing to do for N64_ABI. */ |
252b5132 RH |
13954 | |
13955 | if (mips_32bitmode) | |
13956 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE; | |
13957 | } | |
13958 | ||
13959 | #endif /* OBJ_ELF || OBJ_MAYBE_ELF */ | |
13960 | \f | |
beae10d5 | 13961 | typedef struct proc { |
9b2f1d35 EC |
13962 | symbolS *func_sym; |
13963 | symbolS *func_end_sym; | |
beae10d5 KH |
13964 | unsigned long reg_mask; |
13965 | unsigned long reg_offset; | |
13966 | unsigned long fpreg_mask; | |
13967 | unsigned long fpreg_offset; | |
13968 | unsigned long frame_offset; | |
13969 | unsigned long frame_reg; | |
13970 | unsigned long pc_reg; | |
13971 | } procS; | |
252b5132 RH |
13972 | |
13973 | static procS cur_proc; | |
13974 | static procS *cur_proc_ptr; | |
13975 | static int numprocs; | |
13976 | ||
0a9ef439 | 13977 | /* Fill in an rs_align_code fragment. */ |
a19d8eb0 | 13978 | |
0a9ef439 | 13979 | void |
17a2f251 | 13980 | mips_handle_align (fragS *fragp) |
a19d8eb0 | 13981 | { |
0a9ef439 RH |
13982 | if (fragp->fr_type != rs_align_code) |
13983 | return; | |
13984 | ||
13985 | if (mips_opts.mips16) | |
a19d8eb0 CP |
13986 | { |
13987 | static const unsigned char be_nop[] = { 0x65, 0x00 }; | |
13988 | static const unsigned char le_nop[] = { 0x00, 0x65 }; | |
13989 | ||
0a9ef439 RH |
13990 | int bytes; |
13991 | char *p; | |
a19d8eb0 | 13992 | |
0a9ef439 RH |
13993 | bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix; |
13994 | p = fragp->fr_literal + fragp->fr_fix; | |
13995 | ||
13996 | if (bytes & 1) | |
13997 | { | |
13998 | *p++ = 0; | |
f9419b05 | 13999 | fragp->fr_fix++; |
0a9ef439 RH |
14000 | } |
14001 | ||
14002 | memcpy (p, (target_big_endian ? be_nop : le_nop), 2); | |
14003 | fragp->fr_var = 2; | |
a19d8eb0 CP |
14004 | } |
14005 | ||
0a9ef439 | 14006 | /* For mips32, a nop is a zero, which we trivially get by doing nothing. */ |
a19d8eb0 CP |
14007 | } |
14008 | ||
252b5132 | 14009 | static void |
17a2f251 | 14010 | md_obj_begin (void) |
252b5132 RH |
14011 | { |
14012 | } | |
14013 | ||
14014 | static void | |
17a2f251 | 14015 | md_obj_end (void) |
252b5132 RH |
14016 | { |
14017 | /* check for premature end, nesting errors, etc */ | |
14018 | if (cur_proc_ptr) | |
9a41af64 | 14019 | as_warn (_("missing .end at end of assembly")); |
252b5132 RH |
14020 | } |
14021 | ||
14022 | static long | |
17a2f251 | 14023 | get_number (void) |
252b5132 RH |
14024 | { |
14025 | int negative = 0; | |
14026 | long val = 0; | |
14027 | ||
14028 | if (*input_line_pointer == '-') | |
14029 | { | |
14030 | ++input_line_pointer; | |
14031 | negative = 1; | |
14032 | } | |
3882b010 | 14033 | if (!ISDIGIT (*input_line_pointer)) |
956cd1d6 | 14034 | as_bad (_("expected simple number")); |
252b5132 RH |
14035 | if (input_line_pointer[0] == '0') |
14036 | { | |
14037 | if (input_line_pointer[1] == 'x') | |
14038 | { | |
14039 | input_line_pointer += 2; | |
3882b010 | 14040 | while (ISXDIGIT (*input_line_pointer)) |
252b5132 RH |
14041 | { |
14042 | val <<= 4; | |
14043 | val |= hex_value (*input_line_pointer++); | |
14044 | } | |
14045 | return negative ? -val : val; | |
14046 | } | |
14047 | else | |
14048 | { | |
14049 | ++input_line_pointer; | |
3882b010 | 14050 | while (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
14051 | { |
14052 | val <<= 3; | |
14053 | val |= *input_line_pointer++ - '0'; | |
14054 | } | |
14055 | return negative ? -val : val; | |
14056 | } | |
14057 | } | |
3882b010 | 14058 | if (!ISDIGIT (*input_line_pointer)) |
252b5132 RH |
14059 | { |
14060 | printf (_(" *input_line_pointer == '%c' 0x%02x\n"), | |
14061 | *input_line_pointer, *input_line_pointer); | |
956cd1d6 | 14062 | as_warn (_("invalid number")); |
252b5132 RH |
14063 | return -1; |
14064 | } | |
3882b010 | 14065 | while (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
14066 | { |
14067 | val *= 10; | |
14068 | val += *input_line_pointer++ - '0'; | |
14069 | } | |
14070 | return negative ? -val : val; | |
14071 | } | |
14072 | ||
14073 | /* The .file directive; just like the usual .file directive, but there | |
c5dd6aab DJ |
14074 | is an initial number which is the ECOFF file index. In the non-ECOFF |
14075 | case .file implies DWARF-2. */ | |
14076 | ||
14077 | static void | |
17a2f251 | 14078 | s_mips_file (int x ATTRIBUTE_UNUSED) |
c5dd6aab | 14079 | { |
ecb4347a DJ |
14080 | static int first_file_directive = 0; |
14081 | ||
c5dd6aab DJ |
14082 | if (ECOFF_DEBUGGING) |
14083 | { | |
14084 | get_number (); | |
14085 | s_app_file (0); | |
14086 | } | |
14087 | else | |
ecb4347a DJ |
14088 | { |
14089 | char *filename; | |
14090 | ||
14091 | filename = dwarf2_directive_file (0); | |
14092 | ||
14093 | /* Versions of GCC up to 3.1 start files with a ".file" | |
14094 | directive even for stabs output. Make sure that this | |
14095 | ".file" is handled. Note that you need a version of GCC | |
14096 | after 3.1 in order to support DWARF-2 on MIPS. */ | |
14097 | if (filename != NULL && ! first_file_directive) | |
14098 | { | |
14099 | (void) new_logical_line (filename, -1); | |
c04f5787 | 14100 | s_app_file_string (filename, 0); |
ecb4347a DJ |
14101 | } |
14102 | first_file_directive = 1; | |
14103 | } | |
c5dd6aab DJ |
14104 | } |
14105 | ||
14106 | /* The .loc directive, implying DWARF-2. */ | |
252b5132 RH |
14107 | |
14108 | static void | |
17a2f251 | 14109 | s_mips_loc (int x ATTRIBUTE_UNUSED) |
252b5132 | 14110 | { |
c5dd6aab DJ |
14111 | if (!ECOFF_DEBUGGING) |
14112 | dwarf2_directive_loc (0); | |
252b5132 RH |
14113 | } |
14114 | ||
252b5132 RH |
14115 | /* The .end directive. */ |
14116 | ||
14117 | static void | |
17a2f251 | 14118 | s_mips_end (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
14119 | { |
14120 | symbolS *p; | |
252b5132 | 14121 | |
7a621144 DJ |
14122 | /* Following functions need their own .frame and .cprestore directives. */ |
14123 | mips_frame_reg_valid = 0; | |
14124 | mips_cprestore_valid = 0; | |
14125 | ||
252b5132 RH |
14126 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
14127 | { | |
14128 | p = get_symbol (); | |
14129 | demand_empty_rest_of_line (); | |
14130 | } | |
14131 | else | |
14132 | p = NULL; | |
14133 | ||
14949570 | 14134 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0) |
252b5132 RH |
14135 | as_warn (_(".end not in text section")); |
14136 | ||
14137 | if (!cur_proc_ptr) | |
14138 | { | |
14139 | as_warn (_(".end directive without a preceding .ent directive.")); | |
14140 | demand_empty_rest_of_line (); | |
14141 | return; | |
14142 | } | |
14143 | ||
14144 | if (p != NULL) | |
14145 | { | |
14146 | assert (S_GET_NAME (p)); | |
9b2f1d35 | 14147 | if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->func_sym))) |
252b5132 | 14148 | as_warn (_(".end symbol does not match .ent symbol.")); |
ecb4347a DJ |
14149 | |
14150 | if (debug_type == DEBUG_STABS) | |
14151 | stabs_generate_asm_endfunc (S_GET_NAME (p), | |
14152 | S_GET_NAME (p)); | |
252b5132 RH |
14153 | } |
14154 | else | |
14155 | as_warn (_(".end directive missing or unknown symbol")); | |
14156 | ||
2132e3a3 | 14157 | #ifdef OBJ_ELF |
9b2f1d35 EC |
14158 | /* Create an expression to calculate the size of the function. */ |
14159 | if (p && cur_proc_ptr) | |
14160 | { | |
14161 | OBJ_SYMFIELD_TYPE *obj = symbol_get_obj (p); | |
14162 | expressionS *exp = xmalloc (sizeof (expressionS)); | |
14163 | ||
14164 | obj->size = exp; | |
14165 | exp->X_op = O_subtract; | |
14166 | exp->X_add_symbol = symbol_temp_new_now (); | |
14167 | exp->X_op_symbol = p; | |
14168 | exp->X_add_number = 0; | |
14169 | ||
14170 | cur_proc_ptr->func_end_sym = exp->X_add_symbol; | |
14171 | } | |
14172 | ||
ecb4347a | 14173 | /* Generate a .pdr section. */ |
dcd410fe RO |
14174 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING |
14175 | && mips_flag_pdr) | |
ecb4347a DJ |
14176 | { |
14177 | segT saved_seg = now_seg; | |
14178 | subsegT saved_subseg = now_subseg; | |
14179 | valueT dot; | |
14180 | expressionS exp; | |
14181 | char *fragp; | |
252b5132 | 14182 | |
ecb4347a | 14183 | dot = frag_now_fix (); |
252b5132 RH |
14184 | |
14185 | #ifdef md_flush_pending_output | |
ecb4347a | 14186 | md_flush_pending_output (); |
252b5132 RH |
14187 | #endif |
14188 | ||
ecb4347a DJ |
14189 | assert (pdr_seg); |
14190 | subseg_set (pdr_seg, 0); | |
252b5132 | 14191 | |
ecb4347a DJ |
14192 | /* Write the symbol. */ |
14193 | exp.X_op = O_symbol; | |
14194 | exp.X_add_symbol = p; | |
14195 | exp.X_add_number = 0; | |
14196 | emit_expr (&exp, 4); | |
252b5132 | 14197 | |
ecb4347a | 14198 | fragp = frag_more (7 * 4); |
252b5132 | 14199 | |
17a2f251 TS |
14200 | md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4); |
14201 | md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4); | |
14202 | md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4); | |
14203 | md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4); | |
14204 | md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4); | |
14205 | md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4); | |
14206 | md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4); | |
252b5132 | 14207 | |
ecb4347a DJ |
14208 | subseg_set (saved_seg, saved_subseg); |
14209 | } | |
14210 | #endif /* OBJ_ELF */ | |
252b5132 RH |
14211 | |
14212 | cur_proc_ptr = NULL; | |
14213 | } | |
14214 | ||
14215 | /* The .aent and .ent directives. */ | |
14216 | ||
14217 | static void | |
17a2f251 | 14218 | s_mips_ent (int aent) |
252b5132 | 14219 | { |
252b5132 | 14220 | symbolS *symbolP; |
252b5132 RH |
14221 | |
14222 | symbolP = get_symbol (); | |
14223 | if (*input_line_pointer == ',') | |
f9419b05 | 14224 | ++input_line_pointer; |
252b5132 | 14225 | SKIP_WHITESPACE (); |
3882b010 | 14226 | if (ISDIGIT (*input_line_pointer) |
d9a62219 | 14227 | || *input_line_pointer == '-') |
874e8986 | 14228 | get_number (); |
252b5132 | 14229 | |
14949570 | 14230 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0) |
252b5132 RH |
14231 | as_warn (_(".ent or .aent not in text section.")); |
14232 | ||
14233 | if (!aent && cur_proc_ptr) | |
9a41af64 | 14234 | as_warn (_("missing .end")); |
252b5132 RH |
14235 | |
14236 | if (!aent) | |
14237 | { | |
7a621144 DJ |
14238 | /* This function needs its own .frame and .cprestore directives. */ |
14239 | mips_frame_reg_valid = 0; | |
14240 | mips_cprestore_valid = 0; | |
14241 | ||
252b5132 RH |
14242 | cur_proc_ptr = &cur_proc; |
14243 | memset (cur_proc_ptr, '\0', sizeof (procS)); | |
14244 | ||
9b2f1d35 | 14245 | cur_proc_ptr->func_sym = symbolP; |
252b5132 | 14246 | |
49309057 | 14247 | symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION; |
252b5132 | 14248 | |
f9419b05 | 14249 | ++numprocs; |
ecb4347a DJ |
14250 | |
14251 | if (debug_type == DEBUG_STABS) | |
14252 | stabs_generate_asm_func (S_GET_NAME (symbolP), | |
14253 | S_GET_NAME (symbolP)); | |
252b5132 RH |
14254 | } |
14255 | ||
14256 | demand_empty_rest_of_line (); | |
14257 | } | |
14258 | ||
14259 | /* The .frame directive. If the mdebug section is present (IRIX 5 native) | |
bdaaa2e1 | 14260 | then ecoff.c (ecoff_directive_frame) is used. For embedded targets, |
252b5132 | 14261 | s_mips_frame is used so that we can set the PDR information correctly. |
bdaaa2e1 | 14262 | We can't use the ecoff routines because they make reference to the ecoff |
252b5132 RH |
14263 | symbol table (in the mdebug section). */ |
14264 | ||
14265 | static void | |
17a2f251 | 14266 | s_mips_frame (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 14267 | { |
ecb4347a DJ |
14268 | #ifdef OBJ_ELF |
14269 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING) | |
14270 | { | |
14271 | long val; | |
252b5132 | 14272 | |
ecb4347a DJ |
14273 | if (cur_proc_ptr == (procS *) NULL) |
14274 | { | |
14275 | as_warn (_(".frame outside of .ent")); | |
14276 | demand_empty_rest_of_line (); | |
14277 | return; | |
14278 | } | |
252b5132 | 14279 | |
ecb4347a DJ |
14280 | cur_proc_ptr->frame_reg = tc_get_register (1); |
14281 | ||
14282 | SKIP_WHITESPACE (); | |
14283 | if (*input_line_pointer++ != ',' | |
14284 | || get_absolute_expression_and_terminator (&val) != ',') | |
14285 | { | |
14286 | as_warn (_("Bad .frame directive")); | |
14287 | --input_line_pointer; | |
14288 | demand_empty_rest_of_line (); | |
14289 | return; | |
14290 | } | |
252b5132 | 14291 | |
ecb4347a DJ |
14292 | cur_proc_ptr->frame_offset = val; |
14293 | cur_proc_ptr->pc_reg = tc_get_register (0); | |
252b5132 | 14294 | |
252b5132 | 14295 | demand_empty_rest_of_line (); |
252b5132 | 14296 | } |
ecb4347a DJ |
14297 | else |
14298 | #endif /* OBJ_ELF */ | |
14299 | s_ignore (ignore); | |
252b5132 RH |
14300 | } |
14301 | ||
bdaaa2e1 KH |
14302 | /* The .fmask and .mask directives. If the mdebug section is present |
14303 | (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For | |
252b5132 | 14304 | embedded targets, s_mips_mask is used so that we can set the PDR |
bdaaa2e1 | 14305 | information correctly. We can't use the ecoff routines because they |
252b5132 RH |
14306 | make reference to the ecoff symbol table (in the mdebug section). */ |
14307 | ||
14308 | static void | |
17a2f251 | 14309 | s_mips_mask (int reg_type) |
252b5132 | 14310 | { |
ecb4347a DJ |
14311 | #ifdef OBJ_ELF |
14312 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING) | |
252b5132 | 14313 | { |
ecb4347a | 14314 | long mask, off; |
252b5132 | 14315 | |
ecb4347a DJ |
14316 | if (cur_proc_ptr == (procS *) NULL) |
14317 | { | |
14318 | as_warn (_(".mask/.fmask outside of .ent")); | |
14319 | demand_empty_rest_of_line (); | |
14320 | return; | |
14321 | } | |
252b5132 | 14322 | |
ecb4347a DJ |
14323 | if (get_absolute_expression_and_terminator (&mask) != ',') |
14324 | { | |
14325 | as_warn (_("Bad .mask/.fmask directive")); | |
14326 | --input_line_pointer; | |
14327 | demand_empty_rest_of_line (); | |
14328 | return; | |
14329 | } | |
252b5132 | 14330 | |
ecb4347a DJ |
14331 | off = get_absolute_expression (); |
14332 | ||
14333 | if (reg_type == 'F') | |
14334 | { | |
14335 | cur_proc_ptr->fpreg_mask = mask; | |
14336 | cur_proc_ptr->fpreg_offset = off; | |
14337 | } | |
14338 | else | |
14339 | { | |
14340 | cur_proc_ptr->reg_mask = mask; | |
14341 | cur_proc_ptr->reg_offset = off; | |
14342 | } | |
14343 | ||
14344 | demand_empty_rest_of_line (); | |
252b5132 RH |
14345 | } |
14346 | else | |
ecb4347a DJ |
14347 | #endif /* OBJ_ELF */ |
14348 | s_ignore (reg_type); | |
252b5132 RH |
14349 | } |
14350 | ||
316f5878 RS |
14351 | /* A table describing all the processors gas knows about. Names are |
14352 | matched in the order listed. | |
e7af610e | 14353 | |
316f5878 RS |
14354 | To ease comparison, please keep this table in the same order as |
14355 | gcc's mips_cpu_info_table[]. */ | |
e972090a NC |
14356 | static const struct mips_cpu_info mips_cpu_info_table[] = |
14357 | { | |
316f5878 RS |
14358 | /* Entries for generic ISAs */ |
14359 | { "mips1", 1, ISA_MIPS1, CPU_R3000 }, | |
14360 | { "mips2", 1, ISA_MIPS2, CPU_R6000 }, | |
14361 | { "mips3", 1, ISA_MIPS3, CPU_R4000 }, | |
14362 | { "mips4", 1, ISA_MIPS4, CPU_R8000 }, | |
14363 | { "mips5", 1, ISA_MIPS5, CPU_MIPS5 }, | |
14364 | { "mips32", 1, ISA_MIPS32, CPU_MIPS32 }, | |
af7ee8bf | 14365 | { "mips32r2", 1, ISA_MIPS32R2, CPU_MIPS32R2 }, |
316f5878 | 14366 | { "mips64", 1, ISA_MIPS64, CPU_MIPS64 }, |
5f74bc13 | 14367 | { "mips64r2", 1, ISA_MIPS64R2, CPU_MIPS64R2 }, |
316f5878 RS |
14368 | |
14369 | /* MIPS I */ | |
14370 | { "r3000", 0, ISA_MIPS1, CPU_R3000 }, | |
14371 | { "r2000", 0, ISA_MIPS1, CPU_R3000 }, | |
14372 | { "r3900", 0, ISA_MIPS1, CPU_R3900 }, | |
14373 | ||
14374 | /* MIPS II */ | |
14375 | { "r6000", 0, ISA_MIPS2, CPU_R6000 }, | |
14376 | ||
14377 | /* MIPS III */ | |
14378 | { "r4000", 0, ISA_MIPS3, CPU_R4000 }, | |
14379 | { "r4010", 0, ISA_MIPS2, CPU_R4010 }, | |
14380 | { "vr4100", 0, ISA_MIPS3, CPU_VR4100 }, | |
14381 | { "vr4111", 0, ISA_MIPS3, CPU_R4111 }, | |
60b63b72 RS |
14382 | { "vr4120", 0, ISA_MIPS3, CPU_VR4120 }, |
14383 | { "vr4130", 0, ISA_MIPS3, CPU_VR4120 }, | |
14384 | { "vr4181", 0, ISA_MIPS3, CPU_R4111 }, | |
316f5878 RS |
14385 | { "vr4300", 0, ISA_MIPS3, CPU_R4300 }, |
14386 | { "r4400", 0, ISA_MIPS3, CPU_R4400 }, | |
14387 | { "r4600", 0, ISA_MIPS3, CPU_R4600 }, | |
14388 | { "orion", 0, ISA_MIPS3, CPU_R4600 }, | |
14389 | { "r4650", 0, ISA_MIPS3, CPU_R4650 }, | |
14390 | ||
14391 | /* MIPS IV */ | |
14392 | { "r8000", 0, ISA_MIPS4, CPU_R8000 }, | |
14393 | { "r10000", 0, ISA_MIPS4, CPU_R10000 }, | |
14394 | { "r12000", 0, ISA_MIPS4, CPU_R12000 }, | |
14395 | { "vr5000", 0, ISA_MIPS4, CPU_R5000 }, | |
60b63b72 RS |
14396 | { "vr5400", 0, ISA_MIPS4, CPU_VR5400 }, |
14397 | { "vr5500", 0, ISA_MIPS4, CPU_VR5500 }, | |
316f5878 RS |
14398 | { "rm5200", 0, ISA_MIPS4, CPU_R5000 }, |
14399 | { "rm5230", 0, ISA_MIPS4, CPU_R5000 }, | |
14400 | { "rm5231", 0, ISA_MIPS4, CPU_R5000 }, | |
14401 | { "rm5261", 0, ISA_MIPS4, CPU_R5000 }, | |
14402 | { "rm5721", 0, ISA_MIPS4, CPU_R5000 }, | |
5a7ea749 | 14403 | { "rm7000", 0, ISA_MIPS4, CPU_RM7000 }, |
9a92f48d | 14404 | { "rm9000", 0, ISA_MIPS4, CPU_RM9000 }, |
316f5878 RS |
14405 | |
14406 | /* MIPS 32 */ | |
fef14a42 | 14407 | { "4kc", 0, ISA_MIPS32, CPU_MIPS32 }, |
316f5878 RS |
14408 | { "4km", 0, ISA_MIPS32, CPU_MIPS32 }, |
14409 | { "4kp", 0, ISA_MIPS32, CPU_MIPS32 }, | |
e7af610e | 14410 | |
32b26a03 MR |
14411 | /* MIPS32 Release 2 */ |
14412 | { "m4k", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
14413 | { "24k", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
14414 | { "24kc", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
14415 | { "24kf", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
14416 | { "24kx", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
14417 | ||
316f5878 RS |
14418 | /* MIPS 64 */ |
14419 | { "5kc", 0, ISA_MIPS64, CPU_MIPS64 }, | |
ff324200 | 14420 | { "5kf", 0, ISA_MIPS64, CPU_MIPS64 }, |
316f5878 | 14421 | { "20kc", 0, ISA_MIPS64, CPU_MIPS64 }, |
e7af610e | 14422 | |
c7a23324 | 14423 | /* Broadcom SB-1 CPU core */ |
316f5878 | 14424 | { "sb1", 0, ISA_MIPS64, CPU_SB1 }, |
e7af610e | 14425 | |
316f5878 RS |
14426 | /* End marker */ |
14427 | { NULL, 0, 0, 0 } | |
14428 | }; | |
e7af610e | 14429 | |
84ea6cf2 | 14430 | |
316f5878 RS |
14431 | /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL |
14432 | with a final "000" replaced by "k". Ignore case. | |
e7af610e | 14433 | |
316f5878 | 14434 | Note: this function is shared between GCC and GAS. */ |
c6c98b38 | 14435 | |
b34976b6 | 14436 | static bfd_boolean |
17a2f251 | 14437 | mips_strict_matching_cpu_name_p (const char *canonical, const char *given) |
316f5878 RS |
14438 | { |
14439 | while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical)) | |
14440 | given++, canonical++; | |
14441 | ||
14442 | return ((*given == 0 && *canonical == 0) | |
14443 | || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0)); | |
14444 | } | |
14445 | ||
14446 | ||
14447 | /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied | |
14448 | CPU name. We've traditionally allowed a lot of variation here. | |
14449 | ||
14450 | Note: this function is shared between GCC and GAS. */ | |
14451 | ||
b34976b6 | 14452 | static bfd_boolean |
17a2f251 | 14453 | mips_matching_cpu_name_p (const char *canonical, const char *given) |
316f5878 RS |
14454 | { |
14455 | /* First see if the name matches exactly, or with a final "000" | |
14456 | turned into "k". */ | |
14457 | if (mips_strict_matching_cpu_name_p (canonical, given)) | |
b34976b6 | 14458 | return TRUE; |
316f5878 RS |
14459 | |
14460 | /* If not, try comparing based on numerical designation alone. | |
14461 | See if GIVEN is an unadorned number, or 'r' followed by a number. */ | |
14462 | if (TOLOWER (*given) == 'r') | |
14463 | given++; | |
14464 | if (!ISDIGIT (*given)) | |
b34976b6 | 14465 | return FALSE; |
316f5878 RS |
14466 | |
14467 | /* Skip over some well-known prefixes in the canonical name, | |
14468 | hoping to find a number there too. */ | |
14469 | if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r') | |
14470 | canonical += 2; | |
14471 | else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm') | |
14472 | canonical += 2; | |
14473 | else if (TOLOWER (canonical[0]) == 'r') | |
14474 | canonical += 1; | |
14475 | ||
14476 | return mips_strict_matching_cpu_name_p (canonical, given); | |
14477 | } | |
14478 | ||
14479 | ||
14480 | /* Parse an option that takes the name of a processor as its argument. | |
14481 | OPTION is the name of the option and CPU_STRING is the argument. | |
14482 | Return the corresponding processor enumeration if the CPU_STRING is | |
14483 | recognized, otherwise report an error and return null. | |
14484 | ||
14485 | A similar function exists in GCC. */ | |
e7af610e NC |
14486 | |
14487 | static const struct mips_cpu_info * | |
17a2f251 | 14488 | mips_parse_cpu (const char *option, const char *cpu_string) |
e7af610e | 14489 | { |
316f5878 | 14490 | const struct mips_cpu_info *p; |
e7af610e | 14491 | |
316f5878 RS |
14492 | /* 'from-abi' selects the most compatible architecture for the given |
14493 | ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the | |
14494 | EABIs, we have to decide whether we're using the 32-bit or 64-bit | |
14495 | version. Look first at the -mgp options, if given, otherwise base | |
14496 | the choice on MIPS_DEFAULT_64BIT. | |
e7af610e | 14497 | |
316f5878 RS |
14498 | Treat NO_ABI like the EABIs. One reason to do this is that the |
14499 | plain 'mips' and 'mips64' configs have 'from-abi' as their default | |
14500 | architecture. This code picks MIPS I for 'mips' and MIPS III for | |
14501 | 'mips64', just as we did in the days before 'from-abi'. */ | |
14502 | if (strcasecmp (cpu_string, "from-abi") == 0) | |
14503 | { | |
14504 | if (ABI_NEEDS_32BIT_REGS (mips_abi)) | |
14505 | return mips_cpu_info_from_isa (ISA_MIPS1); | |
14506 | ||
14507 | if (ABI_NEEDS_64BIT_REGS (mips_abi)) | |
14508 | return mips_cpu_info_from_isa (ISA_MIPS3); | |
14509 | ||
14510 | if (file_mips_gp32 >= 0) | |
14511 | return mips_cpu_info_from_isa (file_mips_gp32 ? ISA_MIPS1 : ISA_MIPS3); | |
14512 | ||
14513 | return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT | |
14514 | ? ISA_MIPS3 | |
14515 | : ISA_MIPS1); | |
14516 | } | |
14517 | ||
14518 | /* 'default' has traditionally been a no-op. Probably not very useful. */ | |
14519 | if (strcasecmp (cpu_string, "default") == 0) | |
14520 | return 0; | |
14521 | ||
14522 | for (p = mips_cpu_info_table; p->name != 0; p++) | |
14523 | if (mips_matching_cpu_name_p (p->name, cpu_string)) | |
14524 | return p; | |
14525 | ||
14526 | as_bad ("Bad value (%s) for %s", cpu_string, option); | |
14527 | return 0; | |
e7af610e NC |
14528 | } |
14529 | ||
316f5878 RS |
14530 | /* Return the canonical processor information for ISA (a member of the |
14531 | ISA_MIPS* enumeration). */ | |
14532 | ||
e7af610e | 14533 | static const struct mips_cpu_info * |
17a2f251 | 14534 | mips_cpu_info_from_isa (int isa) |
e7af610e NC |
14535 | { |
14536 | int i; | |
14537 | ||
14538 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
14539 | if (mips_cpu_info_table[i].is_isa | |
316f5878 | 14540 | && isa == mips_cpu_info_table[i].isa) |
e7af610e NC |
14541 | return (&mips_cpu_info_table[i]); |
14542 | ||
e972090a | 14543 | return NULL; |
e7af610e | 14544 | } |
fef14a42 TS |
14545 | |
14546 | static const struct mips_cpu_info * | |
17a2f251 | 14547 | mips_cpu_info_from_arch (int arch) |
fef14a42 TS |
14548 | { |
14549 | int i; | |
14550 | ||
14551 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
14552 | if (arch == mips_cpu_info_table[i].cpu) | |
14553 | return (&mips_cpu_info_table[i]); | |
14554 | ||
14555 | return NULL; | |
14556 | } | |
316f5878 RS |
14557 | \f |
14558 | static void | |
17a2f251 | 14559 | show (FILE *stream, const char *string, int *col_p, int *first_p) |
316f5878 RS |
14560 | { |
14561 | if (*first_p) | |
14562 | { | |
14563 | fprintf (stream, "%24s", ""); | |
14564 | *col_p = 24; | |
14565 | } | |
14566 | else | |
14567 | { | |
14568 | fprintf (stream, ", "); | |
14569 | *col_p += 2; | |
14570 | } | |
e7af610e | 14571 | |
316f5878 RS |
14572 | if (*col_p + strlen (string) > 72) |
14573 | { | |
14574 | fprintf (stream, "\n%24s", ""); | |
14575 | *col_p = 24; | |
14576 | } | |
14577 | ||
14578 | fprintf (stream, "%s", string); | |
14579 | *col_p += strlen (string); | |
14580 | ||
14581 | *first_p = 0; | |
14582 | } | |
14583 | ||
14584 | void | |
17a2f251 | 14585 | md_show_usage (FILE *stream) |
e7af610e | 14586 | { |
316f5878 RS |
14587 | int column, first; |
14588 | size_t i; | |
14589 | ||
14590 | fprintf (stream, _("\ | |
14591 | MIPS options:\n\ | |
316f5878 RS |
14592 | -EB generate big endian output\n\ |
14593 | -EL generate little endian output\n\ | |
14594 | -g, -g2 do not remove unneeded NOPs or swap branches\n\ | |
14595 | -G NUM allow referencing objects up to NUM bytes\n\ | |
14596 | implicitly with the gp register [default 8]\n")); | |
14597 | fprintf (stream, _("\ | |
14598 | -mips1 generate MIPS ISA I instructions\n\ | |
14599 | -mips2 generate MIPS ISA II instructions\n\ | |
14600 | -mips3 generate MIPS ISA III instructions\n\ | |
14601 | -mips4 generate MIPS ISA IV instructions\n\ | |
14602 | -mips5 generate MIPS ISA V instructions\n\ | |
14603 | -mips32 generate MIPS32 ISA instructions\n\ | |
af7ee8bf | 14604 | -mips32r2 generate MIPS32 release 2 ISA instructions\n\ |
316f5878 | 14605 | -mips64 generate MIPS64 ISA instructions\n\ |
5f74bc13 | 14606 | -mips64r2 generate MIPS64 release 2 ISA instructions\n\ |
316f5878 RS |
14607 | -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n")); |
14608 | ||
14609 | first = 1; | |
e7af610e NC |
14610 | |
14611 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
316f5878 RS |
14612 | show (stream, mips_cpu_info_table[i].name, &column, &first); |
14613 | show (stream, "from-abi", &column, &first); | |
14614 | fputc ('\n', stream); | |
e7af610e | 14615 | |
316f5878 RS |
14616 | fprintf (stream, _("\ |
14617 | -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\ | |
14618 | -no-mCPU don't generate code specific to CPU.\n\ | |
14619 | For -mCPU and -no-mCPU, CPU must be one of:\n")); | |
14620 | ||
14621 | first = 1; | |
14622 | ||
14623 | show (stream, "3900", &column, &first); | |
14624 | show (stream, "4010", &column, &first); | |
14625 | show (stream, "4100", &column, &first); | |
14626 | show (stream, "4650", &column, &first); | |
14627 | fputc ('\n', stream); | |
14628 | ||
14629 | fprintf (stream, _("\ | |
14630 | -mips16 generate mips16 instructions\n\ | |
14631 | -no-mips16 do not generate mips16 instructions\n")); | |
14632 | fprintf (stream, _("\ | |
e16bfa71 TS |
14633 | -msmartmips generate smartmips instructions\n\ |
14634 | -mno-smartmips do not generate smartmips instructions\n")); | |
14635 | fprintf (stream, _("\ | |
74cd071d CF |
14636 | -mdsp generate DSP instructions\n\ |
14637 | -mno-dsp do not generate DSP instructions\n")); | |
14638 | fprintf (stream, _("\ | |
ef2e4d86 CF |
14639 | -mmt generate MT instructions\n\ |
14640 | -mno-mt do not generate MT instructions\n")); | |
14641 | fprintf (stream, _("\ | |
d766e8ec | 14642 | -mfix-vr4120 work around certain VR4120 errata\n\ |
7d8e00cf | 14643 | -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\ |
316f5878 RS |
14644 | -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\ |
14645 | -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\ | |
aed1a261 RS |
14646 | -mno-shared optimize output for executables\n\ |
14647 | -msym32 assume all symbols have 32-bit values\n\ | |
316f5878 RS |
14648 | -O0 remove unneeded NOPs, do not swap branches\n\ |
14649 | -O remove unneeded NOPs and swap branches\n\ | |
316f5878 RS |
14650 | --[no-]construct-floats [dis]allow floating point values to be constructed\n\ |
14651 | --trap, --no-break trap exception on div by 0 and mult overflow\n\ | |
14652 | --break, --no-trap break exception on div by 0 and mult overflow\n")); | |
14653 | #ifdef OBJ_ELF | |
14654 | fprintf (stream, _("\ | |
14655 | -KPIC, -call_shared generate SVR4 position independent code\n\ | |
14656 | -non_shared do not generate position independent code\n\ | |
14657 | -xgot assume a 32 bit GOT\n\ | |
dcd410fe | 14658 | -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\ |
bbe506e8 TS |
14659 | -mshared, -mno-shared disable/enable .cpload optimization for\n\ |
14660 | non-shared code\n\ | |
316f5878 RS |
14661 | -mabi=ABI create ABI conformant object file for:\n")); |
14662 | ||
14663 | first = 1; | |
14664 | ||
14665 | show (stream, "32", &column, &first); | |
14666 | show (stream, "o64", &column, &first); | |
14667 | show (stream, "n32", &column, &first); | |
14668 | show (stream, "64", &column, &first); | |
14669 | show (stream, "eabi", &column, &first); | |
14670 | ||
14671 | fputc ('\n', stream); | |
14672 | ||
14673 | fprintf (stream, _("\ | |
14674 | -32 create o32 ABI object file (default)\n\ | |
14675 | -n32 create n32 ABI object file\n\ | |
14676 | -64 create 64 ABI object file\n")); | |
14677 | #endif | |
e7af610e | 14678 | } |
14e777e0 KB |
14679 | |
14680 | enum dwarf2_format | |
17a2f251 | 14681 | mips_dwarf2_format (void) |
14e777e0 KB |
14682 | { |
14683 | if (mips_abi == N64_ABI) | |
1de5b6a1 AO |
14684 | { |
14685 | #ifdef TE_IRIX | |
14686 | return dwarf2_format_64bit_irix; | |
14687 | #else | |
14688 | return dwarf2_format_64bit; | |
14689 | #endif | |
14690 | } | |
14e777e0 KB |
14691 | else |
14692 | return dwarf2_format_32bit; | |
14693 | } | |
73369e65 EC |
14694 | |
14695 | int | |
14696 | mips_dwarf2_addr_size (void) | |
14697 | { | |
14698 | if (mips_abi == N64_ABI) | |
14699 | return 8; | |
73369e65 EC |
14700 | else |
14701 | return 4; | |
14702 | } | |
5862107c EC |
14703 | |
14704 | /* Standard calling conventions leave the CFA at SP on entry. */ | |
14705 | void | |
14706 | mips_cfi_frame_initial_instructions (void) | |
14707 | { | |
14708 | cfi_add_CFA_def_cfa_register (SP); | |
14709 | } | |
14710 |