opcodes/
[deliverable/binutils-gdb.git] / gas / config / tc-mips.c
CommitLineData
252b5132 1/* tc-mips.c -- assemble code for a MIPS chip.
81912461 2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
e407c74b 3 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012, 2013
c67a084a 4 Free Software Foundation, Inc.
252b5132
RH
5 Contributed by the OSF and Ralph Campbell.
6 Written by Keith Knowles and Ralph Campbell, working independently.
7 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
8 Support.
9
10 This file is part of GAS.
11
12 GAS is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
ec2655a6 14 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH
15 any later version.
16
17 GAS is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
21
22 You should have received a copy of the GNU General Public License
23 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC
24 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
25 02110-1301, USA. */
252b5132
RH
26
27#include "as.h"
28#include "config.h"
29#include "subsegs.h"
3882b010 30#include "safe-ctype.h"
252b5132 31
252b5132
RH
32#include "opcode/mips.h"
33#include "itbl-ops.h"
c5dd6aab 34#include "dwarf2dbg.h"
5862107c 35#include "dw2gencfi.h"
252b5132 36
42429eac
RS
37/* Check assumptions made in this file. */
38typedef char static_assert1[sizeof (offsetT) < 8 ? -1 : 1];
39typedef char static_assert2[sizeof (valueT) < 8 ? -1 : 1];
40
252b5132
RH
41#ifdef DEBUG
42#define DBG(x) printf x
43#else
44#define DBG(x)
45#endif
46
9e12b7a2
RS
47#define SKIP_SPACE_TABS(S) \
48 do { while (*(S) == ' ' || *(S) == '\t') ++(S); } while (0)
49
252b5132 50/* Clean up namespace so we can include obj-elf.h too. */
17a2f251
TS
51static int mips_output_flavor (void);
52static int mips_output_flavor (void) { return OUTPUT_FLAVOR; }
252b5132
RH
53#undef OBJ_PROCESS_STAB
54#undef OUTPUT_FLAVOR
55#undef S_GET_ALIGN
56#undef S_GET_SIZE
57#undef S_SET_ALIGN
58#undef S_SET_SIZE
252b5132
RH
59#undef obj_frob_file
60#undef obj_frob_file_after_relocs
61#undef obj_frob_symbol
62#undef obj_pop_insert
63#undef obj_sec_sym_ok_for_reloc
64#undef OBJ_COPY_SYMBOL_ATTRIBUTES
65
66#include "obj-elf.h"
67/* Fix any of them that we actually care about. */
68#undef OUTPUT_FLAVOR
69#define OUTPUT_FLAVOR mips_output_flavor()
252b5132 70
252b5132 71#include "elf/mips.h"
252b5132
RH
72
73#ifndef ECOFF_DEBUGGING
74#define NO_ECOFF_DEBUGGING
75#define ECOFF_DEBUGGING 0
76#endif
77
ecb4347a
DJ
78int mips_flag_mdebug = -1;
79
dcd410fe
RO
80/* Control generation of .pdr sections. Off by default on IRIX: the native
81 linker doesn't know about and discards them, but relocations against them
82 remain, leading to rld crashes. */
83#ifdef TE_IRIX
84int mips_flag_pdr = FALSE;
85#else
86int mips_flag_pdr = TRUE;
87#endif
88
252b5132
RH
89#include "ecoff.h"
90
252b5132 91static char *mips_regmask_frag;
252b5132 92
85b51719 93#define ZERO 0
741fe287 94#define ATREG 1
df58fc94
RS
95#define S0 16
96#define S7 23
252b5132
RH
97#define TREG 24
98#define PIC_CALL_REG 25
99#define KT0 26
100#define KT1 27
101#define GP 28
102#define SP 29
103#define FP 30
104#define RA 31
105
106#define ILLEGAL_REG (32)
107
741fe287
MR
108#define AT mips_opts.at
109
252b5132
RH
110extern int target_big_endian;
111
252b5132 112/* The name of the readonly data section. */
e8044f35 113#define RDATA_SECTION_NAME ".rodata"
252b5132 114
a4e06468
RS
115/* Ways in which an instruction can be "appended" to the output. */
116enum append_method {
117 /* Just add it normally. */
118 APPEND_ADD,
119
120 /* Add it normally and then add a nop. */
121 APPEND_ADD_WITH_NOP,
122
123 /* Turn an instruction with a delay slot into a "compact" version. */
124 APPEND_ADD_COMPACT,
125
126 /* Insert the instruction before the last one. */
127 APPEND_SWAP
128};
129
47e39b9d
RS
130/* Information about an instruction, including its format, operands
131 and fixups. */
132struct mips_cl_insn
133{
134 /* The opcode's entry in mips_opcodes or mips16_opcodes. */
135 const struct mips_opcode *insn_mo;
136
47e39b9d 137 /* The 16-bit or 32-bit bitstring of the instruction itself. This is
5c04167a
RS
138 a copy of INSN_MO->match with the operands filled in. If we have
139 decided to use an extended MIPS16 instruction, this includes the
140 extension. */
47e39b9d
RS
141 unsigned long insn_opcode;
142
143 /* The frag that contains the instruction. */
144 struct frag *frag;
145
146 /* The offset into FRAG of the first instruction byte. */
147 long where;
148
149 /* The relocs associated with the instruction, if any. */
150 fixS *fixp[3];
151
a38419a5
RS
152 /* True if this entry cannot be moved from its current position. */
153 unsigned int fixed_p : 1;
47e39b9d 154
708587a4 155 /* True if this instruction occurred in a .set noreorder block. */
47e39b9d
RS
156 unsigned int noreorder_p : 1;
157
2fa15973
RS
158 /* True for mips16 instructions that jump to an absolute address. */
159 unsigned int mips16_absolute_jump_p : 1;
15be625d
CM
160
161 /* True if this instruction is complete. */
162 unsigned int complete_p : 1;
e407c74b
NC
163
164 /* True if this instruction is cleared from history by unconditional
165 branch. */
166 unsigned int cleared_p : 1;
47e39b9d
RS
167};
168
a325df1d
TS
169/* The ABI to use. */
170enum mips_abi_level
171{
172 NO_ABI = 0,
173 O32_ABI,
174 O64_ABI,
175 N32_ABI,
176 N64_ABI,
177 EABI_ABI
178};
179
180/* MIPS ABI we are using for this output file. */
316f5878 181static enum mips_abi_level mips_abi = NO_ABI;
a325df1d 182
143d77c5
EC
183/* Whether or not we have code that can call pic code. */
184int mips_abicalls = FALSE;
185
aa6975fb
ILT
186/* Whether or not we have code which can be put into a shared
187 library. */
188static bfd_boolean mips_in_shared = TRUE;
189
252b5132
RH
190/* This is the set of options which may be modified by the .set
191 pseudo-op. We use a struct so that .set push and .set pop are more
192 reliable. */
193
e972090a
NC
194struct mips_set_options
195{
252b5132
RH
196 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
197 if it has not been initialized. Changed by `.set mipsN', and the
198 -mipsN command line option, and the default CPU. */
199 int isa;
846ef2d0
RS
200 /* Enabled Application Specific Extensions (ASEs). Changed by `.set
201 <asename>', by command line options, and based on the default
202 architecture. */
203 int ase;
252b5132
RH
204 /* Whether we are assembling for the mips16 processor. 0 if we are
205 not, 1 if we are, and -1 if the value has not been initialized.
206 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
207 -nomips16 command line options, and the default CPU. */
208 int mips16;
df58fc94
RS
209 /* Whether we are assembling for the mipsMIPS ASE. 0 if we are not,
210 1 if we are, and -1 if the value has not been initialized. Changed
211 by `.set micromips' and `.set nomicromips', and the -mmicromips
212 and -mno-micromips command line options, and the default CPU. */
213 int micromips;
252b5132
RH
214 /* Non-zero if we should not reorder instructions. Changed by `.set
215 reorder' and `.set noreorder'. */
216 int noreorder;
741fe287
MR
217 /* Non-zero if we should not permit the register designated "assembler
218 temporary" to be used in instructions. The value is the register
219 number, normally $at ($1). Changed by `.set at=REG', `.set noat'
220 (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */
221 unsigned int at;
252b5132
RH
222 /* Non-zero if we should warn when a macro instruction expands into
223 more than one machine instruction. Changed by `.set nomacro' and
224 `.set macro'. */
225 int warn_about_macros;
226 /* Non-zero if we should not move instructions. Changed by `.set
227 move', `.set volatile', `.set nomove', and `.set novolatile'. */
228 int nomove;
229 /* Non-zero if we should not optimize branches by moving the target
230 of the branch into the delay slot. Actually, we don't perform
231 this optimization anyhow. Changed by `.set bopt' and `.set
232 nobopt'. */
233 int nobopt;
234 /* Non-zero if we should not autoextend mips16 instructions.
235 Changed by `.set autoextend' and `.set noautoextend'. */
236 int noautoextend;
833794fc
MR
237 /* True if we should only emit 32-bit microMIPS instructions.
238 Changed by `.set insn32' and `.set noinsn32', and the -minsn32
239 and -mno-insn32 command line options. */
240 bfd_boolean insn32;
a325df1d
TS
241 /* Restrict general purpose registers and floating point registers
242 to 32 bit. This is initially determined when -mgp32 or -mfp32
243 is passed but can changed if the assembler code uses .set mipsN. */
244 int gp32;
245 int fp32;
fef14a42
TS
246 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
247 command line option, and the default CPU. */
248 int arch;
aed1a261
RS
249 /* True if ".set sym32" is in effect. */
250 bfd_boolean sym32;
037b32b9
AN
251 /* True if floating-point operations are not allowed. Changed by .set
252 softfloat or .set hardfloat, by command line options -msoft-float or
253 -mhard-float. The default is false. */
254 bfd_boolean soft_float;
255
256 /* True if only single-precision floating-point operations are allowed.
257 Changed by .set singlefloat or .set doublefloat, command-line options
258 -msingle-float or -mdouble-float. The default is false. */
259 bfd_boolean single_float;
252b5132
RH
260};
261
037b32b9
AN
262/* This is the struct we use to hold the current set of options. Note
263 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
264 -1 to indicate that they have not been initialized. */
265
a325df1d 266/* True if -mgp32 was passed. */
a8e8e863 267static int file_mips_gp32 = -1;
a325df1d
TS
268
269/* True if -mfp32 was passed. */
a8e8e863 270static int file_mips_fp32 = -1;
a325df1d 271
037b32b9
AN
272/* 1 if -msoft-float, 0 if -mhard-float. The default is 0. */
273static int file_mips_soft_float = 0;
274
275/* 1 if -msingle-float, 0 if -mdouble-float. The default is 0. */
276static int file_mips_single_float = 0;
252b5132 277
ba92f887
MR
278/* True if -mnan=2008, false if -mnan=legacy. */
279static bfd_boolean mips_flag_nan2008 = FALSE;
280
e972090a
NC
281static struct mips_set_options mips_opts =
282{
846ef2d0 283 /* isa */ ISA_UNKNOWN, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1,
b015e599 284 /* noreorder */ 0, /* at */ ATREG, /* warn_about_macros */ 0,
833794fc
MR
285 /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE,
286 /* gp32 */ 0, /* fp32 */ 0, /* arch */ CPU_UNKNOWN, /* sym32 */ FALSE,
b015e599 287 /* soft_float */ FALSE, /* single_float */ FALSE
e7af610e 288};
252b5132 289
846ef2d0
RS
290/* The set of ASEs that were selected on the command line, either
291 explicitly via ASE options or implicitly through things like -march. */
292static unsigned int file_ase;
293
294/* Which bits of file_ase were explicitly set or cleared by ASE options. */
295static unsigned int file_ase_explicit;
296
252b5132
RH
297/* These variables are filled in with the masks of registers used.
298 The object format code reads them and puts them in the appropriate
299 place. */
300unsigned long mips_gprmask;
301unsigned long mips_cprmask[4];
302
303/* MIPS ISA we are using for this output file. */
e7af610e 304static int file_mips_isa = ISA_UNKNOWN;
252b5132 305
738f4d98 306/* True if any MIPS16 code was produced. */
a4672219
TS
307static int file_ase_mips16;
308
3994f87e
TS
309#define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \
310 || mips_opts.isa == ISA_MIPS32R2 \
311 || mips_opts.isa == ISA_MIPS64 \
312 || mips_opts.isa == ISA_MIPS64R2)
313
df58fc94
RS
314/* True if any microMIPS code was produced. */
315static int file_ase_micromips;
316
b12dd2e4
CF
317/* True if we want to create R_MIPS_JALR for jalr $25. */
318#ifdef TE_IRIX
1180b5a4 319#define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI
b12dd2e4 320#else
1180b5a4
RS
321/* As a GNU extension, we use R_MIPS_JALR for o32 too. However,
322 because there's no place for any addend, the only acceptable
323 expression is a bare symbol. */
324#define MIPS_JALR_HINT_P(EXPR) \
325 (!HAVE_IN_PLACE_ADDENDS \
326 || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0))
b12dd2e4
CF
327#endif
328
ec68c924 329/* The argument of the -march= flag. The architecture we are assembling. */
fef14a42 330static int file_mips_arch = CPU_UNKNOWN;
316f5878 331static const char *mips_arch_string;
ec68c924
EC
332
333/* The argument of the -mtune= flag. The architecture for which we
334 are optimizing. */
335static int mips_tune = CPU_UNKNOWN;
316f5878 336static const char *mips_tune_string;
ec68c924 337
316f5878 338/* True when generating 32-bit code for a 64-bit processor. */
252b5132
RH
339static int mips_32bitmode = 0;
340
316f5878
RS
341/* True if the given ABI requires 32-bit registers. */
342#define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
343
344/* Likewise 64-bit registers. */
707bfff6
TS
345#define ABI_NEEDS_64BIT_REGS(ABI) \
346 ((ABI) == N32_ABI \
347 || (ABI) == N64_ABI \
316f5878
RS
348 || (ABI) == O64_ABI)
349
ad3fea08 350/* Return true if ISA supports 64 bit wide gp registers. */
707bfff6
TS
351#define ISA_HAS_64BIT_REGS(ISA) \
352 ((ISA) == ISA_MIPS3 \
353 || (ISA) == ISA_MIPS4 \
354 || (ISA) == ISA_MIPS5 \
355 || (ISA) == ISA_MIPS64 \
356 || (ISA) == ISA_MIPS64R2)
9ce8a5dd 357
ad3fea08
TS
358/* Return true if ISA supports 64 bit wide float registers. */
359#define ISA_HAS_64BIT_FPRS(ISA) \
360 ((ISA) == ISA_MIPS3 \
361 || (ISA) == ISA_MIPS4 \
362 || (ISA) == ISA_MIPS5 \
363 || (ISA) == ISA_MIPS32R2 \
364 || (ISA) == ISA_MIPS64 \
365 || (ISA) == ISA_MIPS64R2)
366
af7ee8bf
CD
367/* Return true if ISA supports 64-bit right rotate (dror et al.)
368 instructions. */
707bfff6 369#define ISA_HAS_DROR(ISA) \
df58fc94
RS
370 ((ISA) == ISA_MIPS64R2 \
371 || (mips_opts.micromips \
372 && ISA_HAS_64BIT_REGS (ISA)) \
373 )
af7ee8bf
CD
374
375/* Return true if ISA supports 32-bit right rotate (ror et al.)
376 instructions. */
707bfff6
TS
377#define ISA_HAS_ROR(ISA) \
378 ((ISA) == ISA_MIPS32R2 \
379 || (ISA) == ISA_MIPS64R2 \
846ef2d0 380 || (mips_opts.ase & ASE_SMARTMIPS) \
df58fc94
RS
381 || mips_opts.micromips \
382 )
707bfff6 383
7455baf8
TS
384/* Return true if ISA supports single-precision floats in odd registers. */
385#define ISA_HAS_ODD_SINGLE_FPR(ISA) \
386 ((ISA) == ISA_MIPS32 \
387 || (ISA) == ISA_MIPS32R2 \
388 || (ISA) == ISA_MIPS64 \
389 || (ISA) == ISA_MIPS64R2)
af7ee8bf 390
ad3fea08
TS
391/* Return true if ISA supports move to/from high part of a 64-bit
392 floating-point register. */
393#define ISA_HAS_MXHC1(ISA) \
394 ((ISA) == ISA_MIPS32R2 \
395 || (ISA) == ISA_MIPS64R2)
396
e013f690 397#define HAVE_32BIT_GPRS \
ad3fea08 398 (mips_opts.gp32 || !ISA_HAS_64BIT_REGS (mips_opts.isa))
ca4e0257 399
e013f690 400#define HAVE_32BIT_FPRS \
ad3fea08 401 (mips_opts.fp32 || !ISA_HAS_64BIT_FPRS (mips_opts.isa))
ca4e0257 402
ad3fea08
TS
403#define HAVE_64BIT_GPRS (!HAVE_32BIT_GPRS)
404#define HAVE_64BIT_FPRS (!HAVE_32BIT_FPRS)
ca4e0257 405
316f5878 406#define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
e013f690 407
316f5878 408#define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
e013f690 409
3b91255e
RS
410/* True if relocations are stored in-place. */
411#define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
412
aed1a261
RS
413/* The ABI-derived address size. */
414#define HAVE_64BIT_ADDRESSES \
415 (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
416#define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
e013f690 417
aed1a261
RS
418/* The size of symbolic constants (i.e., expressions of the form
419 "SYMBOL" or "SYMBOL + OFFSET"). */
420#define HAVE_32BIT_SYMBOLS \
421 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
422#define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
ca4e0257 423
b7c7d6c1
TS
424/* Addresses are loaded in different ways, depending on the address size
425 in use. The n32 ABI Documentation also mandates the use of additions
426 with overflow checking, but existing implementations don't follow it. */
f899b4b8 427#define ADDRESS_ADD_INSN \
b7c7d6c1 428 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
f899b4b8
TS
429
430#define ADDRESS_ADDI_INSN \
b7c7d6c1 431 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
f899b4b8
TS
432
433#define ADDRESS_LOAD_INSN \
434 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
435
436#define ADDRESS_STORE_INSN \
437 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
438
a4672219 439/* Return true if the given CPU supports the MIPS16 ASE. */
3396de36
TS
440#define CPU_HAS_MIPS16(cpu) \
441 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
442 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
a4672219 443
2309ddf2 444/* Return true if the given CPU supports the microMIPS ASE. */
df58fc94
RS
445#define CPU_HAS_MICROMIPS(cpu) 0
446
60b63b72
RS
447/* True if CPU has a dror instruction. */
448#define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
449
450/* True if CPU has a ror instruction. */
451#define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
452
dd6a37e7 453/* True if CPU is in the Octeon family */
432233b3 454#define CPU_IS_OCTEON(CPU) ((CPU) == CPU_OCTEON || (CPU) == CPU_OCTEONP || (CPU) == CPU_OCTEON2)
dd6a37e7 455
dd3cbb7e 456/* True if CPU has seq/sne and seqi/snei instructions. */
dd6a37e7 457#define CPU_HAS_SEQ(CPU) (CPU_IS_OCTEON (CPU))
dd3cbb7e 458
0aa27725
RS
459/* True, if CPU has support for ldc1 and sdc1. */
460#define CPU_HAS_LDC1_SDC1(CPU) \
461 ((mips_opts.isa != ISA_MIPS1) && ((CPU) != CPU_R5900))
462
c8978940
CD
463/* True if mflo and mfhi can be immediately followed by instructions
464 which write to the HI and LO registers.
465
466 According to MIPS specifications, MIPS ISAs I, II, and III need
467 (at least) two instructions between the reads of HI/LO and
468 instructions which write them, and later ISAs do not. Contradicting
469 the MIPS specifications, some MIPS IV processor user manuals (e.g.
470 the UM for the NEC Vr5000) document needing the instructions between
471 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
472 MIPS64 and later ISAs to have the interlocks, plus any specific
473 earlier-ISA CPUs for which CPU documentation declares that the
474 instructions are really interlocked. */
475#define hilo_interlocks \
476 (mips_opts.isa == ISA_MIPS32 \
477 || mips_opts.isa == ISA_MIPS32R2 \
478 || mips_opts.isa == ISA_MIPS64 \
479 || mips_opts.isa == ISA_MIPS64R2 \
480 || mips_opts.arch == CPU_R4010 \
e407c74b 481 || mips_opts.arch == CPU_R5900 \
c8978940
CD
482 || mips_opts.arch == CPU_R10000 \
483 || mips_opts.arch == CPU_R12000 \
3aa3176b
TS
484 || mips_opts.arch == CPU_R14000 \
485 || mips_opts.arch == CPU_R16000 \
c8978940 486 || mips_opts.arch == CPU_RM7000 \
c8978940 487 || mips_opts.arch == CPU_VR5500 \
df58fc94 488 || mips_opts.micromips \
c8978940 489 )
252b5132
RH
490
491/* Whether the processor uses hardware interlocks to protect reads
81912461
ILT
492 from the GPRs after they are loaded from memory, and thus does not
493 require nops to be inserted. This applies to instructions marked
494 INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA
df58fc94
RS
495 level I and microMIPS mode instructions are always interlocked. */
496#define gpr_interlocks \
497 (mips_opts.isa != ISA_MIPS1 \
498 || mips_opts.arch == CPU_R3900 \
e407c74b 499 || mips_opts.arch == CPU_R5900 \
df58fc94
RS
500 || mips_opts.micromips \
501 )
252b5132 502
81912461
ILT
503/* Whether the processor uses hardware interlocks to avoid delays
504 required by coprocessor instructions, and thus does not require
505 nops to be inserted. This applies to instructions marked
506 INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays
507 between instructions marked INSN_WRITE_COND_CODE and ones marked
508 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
df58fc94
RS
509 levels I, II, and III and microMIPS mode instructions are always
510 interlocked. */
bdaaa2e1 511/* Itbl support may require additional care here. */
81912461
ILT
512#define cop_interlocks \
513 ((mips_opts.isa != ISA_MIPS1 \
514 && mips_opts.isa != ISA_MIPS2 \
515 && mips_opts.isa != ISA_MIPS3) \
516 || mips_opts.arch == CPU_R4300 \
df58fc94 517 || mips_opts.micromips \
81912461
ILT
518 )
519
520/* Whether the processor uses hardware interlocks to protect reads
521 from coprocessor registers after they are loaded from memory, and
522 thus does not require nops to be inserted. This applies to
523 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
df58fc94
RS
524 requires at MIPS ISA level I and microMIPS mode instructions are
525 always interlocked. */
526#define cop_mem_interlocks \
527 (mips_opts.isa != ISA_MIPS1 \
528 || mips_opts.micromips \
529 )
252b5132 530
6b76fefe
CM
531/* Is this a mfhi or mflo instruction? */
532#define MF_HILO_INSN(PINFO) \
b19e8a9b
AN
533 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
534
df58fc94
RS
535/* Whether code compression (either of the MIPS16 or the microMIPS ASEs)
536 has been selected. This implies, in particular, that addresses of text
537 labels have their LSB set. */
538#define HAVE_CODE_COMPRESSION \
539 ((mips_opts.mips16 | mips_opts.micromips) != 0)
540
42429eac
RS
541/* The minimum and maximum signed values that can be stored in a GPR. */
542#define GPR_SMAX ((offsetT) (((valueT) 1 << (HAVE_64BIT_GPRS ? 63 : 31)) - 1))
543#define GPR_SMIN (-GPR_SMAX - 1)
544
252b5132
RH
545/* MIPS PIC level. */
546
a161fe53 547enum mips_pic_level mips_pic;
252b5132 548
c9914766 549/* 1 if we should generate 32 bit offsets from the $gp register in
252b5132 550 SVR4_PIC mode. Currently has no meaning in other modes. */
c9914766 551static int mips_big_got = 0;
252b5132
RH
552
553/* 1 if trap instructions should used for overflow rather than break
554 instructions. */
c9914766 555static int mips_trap = 0;
252b5132 556
119d663a 557/* 1 if double width floating point constants should not be constructed
b6ff326e 558 by assembling two single width halves into two single width floating
119d663a
NC
559 point registers which just happen to alias the double width destination
560 register. On some architectures this aliasing can be disabled by a bit
d547a75e 561 in the status register, and the setting of this bit cannot be determined
119d663a
NC
562 automatically at assemble time. */
563static int mips_disable_float_construction;
564
252b5132
RH
565/* Non-zero if any .set noreorder directives were used. */
566
567static int mips_any_noreorder;
568
6b76fefe
CM
569/* Non-zero if nops should be inserted when the register referenced in
570 an mfhi/mflo instruction is read in the next two instructions. */
571static int mips_7000_hilo_fix;
572
02ffd3e4 573/* The size of objects in the small data section. */
156c2f8b 574static unsigned int g_switch_value = 8;
252b5132
RH
575/* Whether the -G option was used. */
576static int g_switch_seen = 0;
577
578#define N_RMASK 0xc4
579#define N_VFP 0xd4
580
581/* If we can determine in advance that GP optimization won't be
582 possible, we can skip the relaxation stuff that tries to produce
583 GP-relative references. This makes delay slot optimization work
584 better.
585
586 This function can only provide a guess, but it seems to work for
fba2b7f9
GK
587 gcc output. It needs to guess right for gcc, otherwise gcc
588 will put what it thinks is a GP-relative instruction in a branch
589 delay slot.
252b5132
RH
590
591 I don't know if a fix is needed for the SVR4_PIC mode. I've only
592 fixed it for the non-PIC mode. KR 95/04/07 */
17a2f251 593static int nopic_need_relax (symbolS *, int);
252b5132
RH
594
595/* handle of the OPCODE hash table */
596static struct hash_control *op_hash = NULL;
597
598/* The opcode hash table we use for the mips16. */
599static struct hash_control *mips16_op_hash = NULL;
600
df58fc94
RS
601/* The opcode hash table we use for the microMIPS ASE. */
602static struct hash_control *micromips_op_hash = NULL;
603
252b5132
RH
604/* This array holds the chars that always start a comment. If the
605 pre-processor is disabled, these aren't very useful */
606const char comment_chars[] = "#";
607
608/* This array holds the chars that only start a comment at the beginning of
609 a line. If the line seems to have the form '# 123 filename'
610 .line and .file directives will appear in the pre-processed output */
611/* Note that input_file.c hand checks for '#' at the beginning of the
612 first line of the input file. This is because the compiler outputs
bdaaa2e1 613 #NO_APP at the beginning of its output. */
252b5132
RH
614/* Also note that C style comments are always supported. */
615const char line_comment_chars[] = "#";
616
bdaaa2e1 617/* This array holds machine specific line separator characters. */
63a0b638 618const char line_separator_chars[] = ";";
252b5132
RH
619
620/* Chars that can be used to separate mant from exp in floating point nums */
621const char EXP_CHARS[] = "eE";
622
623/* Chars that mean this number is a floating point constant */
624/* As in 0f12.456 */
625/* or 0d1.2345e12 */
626const char FLT_CHARS[] = "rRsSfFdDxXpP";
627
628/* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
629 changed in read.c . Ideally it shouldn't have to know about it at all,
630 but nothing is ideal around here.
631 */
632
633static char *insn_error;
634
635static int auto_align = 1;
636
637/* When outputting SVR4 PIC code, the assembler needs to know the
638 offset in the stack frame from which to restore the $gp register.
639 This is set by the .cprestore pseudo-op, and saved in this
640 variable. */
641static offsetT mips_cprestore_offset = -1;
642
67c1ffbe 643/* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
6478892d 644 more optimizations, it can use a register value instead of a memory-saved
956cd1d6 645 offset and even an other register than $gp as global pointer. */
6478892d
TS
646static offsetT mips_cpreturn_offset = -1;
647static int mips_cpreturn_register = -1;
648static int mips_gp_register = GP;
def2e0dd 649static int mips_gprel_offset = 0;
6478892d 650
7a621144
DJ
651/* Whether mips_cprestore_offset has been set in the current function
652 (or whether it has already been warned about, if not). */
653static int mips_cprestore_valid = 0;
654
252b5132
RH
655/* This is the register which holds the stack frame, as set by the
656 .frame pseudo-op. This is needed to implement .cprestore. */
657static int mips_frame_reg = SP;
658
7a621144
DJ
659/* Whether mips_frame_reg has been set in the current function
660 (or whether it has already been warned about, if not). */
661static int mips_frame_reg_valid = 0;
662
252b5132
RH
663/* To output NOP instructions correctly, we need to keep information
664 about the previous two instructions. */
665
666/* Whether we are optimizing. The default value of 2 means to remove
667 unneeded NOPs and swap branch instructions when possible. A value
668 of 1 means to not swap branches. A value of 0 means to always
669 insert NOPs. */
670static int mips_optimize = 2;
671
672/* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
673 equivalent to seeing no -g option at all. */
674static int mips_debug = 0;
675
7d8e00cf
RS
676/* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */
677#define MAX_VR4130_NOPS 4
678
679/* The maximum number of NOPs needed to fill delay slots. */
680#define MAX_DELAY_NOPS 2
681
682/* The maximum number of NOPs needed for any purpose. */
683#define MAX_NOPS 4
71400594
RS
684
685/* A list of previous instructions, with index 0 being the most recent.
686 We need to look back MAX_NOPS instructions when filling delay slots
687 or working around processor errata. We need to look back one
688 instruction further if we're thinking about using history[0] to
689 fill a branch delay slot. */
690static struct mips_cl_insn history[1 + MAX_NOPS];
252b5132 691
1e915849 692/* Nop instructions used by emit_nop. */
df58fc94
RS
693static struct mips_cl_insn nop_insn;
694static struct mips_cl_insn mips16_nop_insn;
695static struct mips_cl_insn micromips_nop16_insn;
696static struct mips_cl_insn micromips_nop32_insn;
1e915849
RS
697
698/* The appropriate nop for the current mode. */
833794fc
MR
699#define NOP_INSN (mips_opts.mips16 \
700 ? &mips16_nop_insn \
701 : (mips_opts.micromips \
702 ? (mips_opts.insn32 \
703 ? &micromips_nop32_insn \
704 : &micromips_nop16_insn) \
705 : &nop_insn))
df58fc94
RS
706
707/* The size of NOP_INSN in bytes. */
833794fc
MR
708#define NOP_INSN_SIZE ((mips_opts.mips16 \
709 || (mips_opts.micromips && !mips_opts.insn32)) \
710 ? 2 : 4)
252b5132 711
252b5132
RH
712/* If this is set, it points to a frag holding nop instructions which
713 were inserted before the start of a noreorder section. If those
714 nops turn out to be unnecessary, the size of the frag can be
715 decreased. */
716static fragS *prev_nop_frag;
717
718/* The number of nop instructions we created in prev_nop_frag. */
719static int prev_nop_frag_holds;
720
721/* The number of nop instructions that we know we need in
bdaaa2e1 722 prev_nop_frag. */
252b5132
RH
723static int prev_nop_frag_required;
724
725/* The number of instructions we've seen since prev_nop_frag. */
726static int prev_nop_frag_since;
727
e8044f35
RS
728/* Relocations against symbols are sometimes done in two parts, with a HI
729 relocation and a LO relocation. Each relocation has only 16 bits of
730 space to store an addend. This means that in order for the linker to
731 handle carries correctly, it must be able to locate both the HI and
732 the LO relocation. This means that the relocations must appear in
733 order in the relocation table.
252b5132
RH
734
735 In order to implement this, we keep track of each unmatched HI
736 relocation. We then sort them so that they immediately precede the
bdaaa2e1 737 corresponding LO relocation. */
252b5132 738
e972090a
NC
739struct mips_hi_fixup
740{
252b5132
RH
741 /* Next HI fixup. */
742 struct mips_hi_fixup *next;
743 /* This fixup. */
744 fixS *fixp;
745 /* The section this fixup is in. */
746 segT seg;
747};
748
749/* The list of unmatched HI relocs. */
750
751static struct mips_hi_fixup *mips_hi_fixup_list;
752
64bdfcaf
RS
753/* The frag containing the last explicit relocation operator.
754 Null if explicit relocations have not been used. */
755
756static fragS *prev_reloc_op_frag;
757
252b5132
RH
758/* Map mips16 register numbers to normal MIPS register numbers. */
759
e972090a
NC
760static const unsigned int mips16_to_32_reg_map[] =
761{
252b5132
RH
762 16, 17, 2, 3, 4, 5, 6, 7
763};
60b63b72 764
df58fc94
RS
765/* Map microMIPS register numbers to normal MIPS register numbers. */
766
767#define micromips_to_32_reg_b_map mips16_to_32_reg_map
768#define micromips_to_32_reg_c_map mips16_to_32_reg_map
769#define micromips_to_32_reg_d_map mips16_to_32_reg_map
770#define micromips_to_32_reg_e_map mips16_to_32_reg_map
771#define micromips_to_32_reg_f_map mips16_to_32_reg_map
772#define micromips_to_32_reg_g_map mips16_to_32_reg_map
773
774/* The microMIPS registers with type h. */
e76ff5ab 775static const unsigned int micromips_to_32_reg_h_map1[] =
df58fc94
RS
776{
777 5, 5, 6, 4, 4, 4, 4, 4
778};
e76ff5ab 779static const unsigned int micromips_to_32_reg_h_map2[] =
df58fc94
RS
780{
781 6, 7, 7, 21, 22, 5, 6, 7
782};
783
784#define micromips_to_32_reg_l_map mips16_to_32_reg_map
785
786/* The microMIPS registers with type m. */
787static const unsigned int micromips_to_32_reg_m_map[] =
788{
789 0, 17, 2, 3, 16, 18, 19, 20
790};
791
792#define micromips_to_32_reg_n_map micromips_to_32_reg_m_map
793
794/* The microMIPS registers with type q. */
795static const unsigned int micromips_to_32_reg_q_map[] =
796{
797 0, 17, 2, 3, 4, 5, 6, 7
798};
799
71400594
RS
800/* Classifies the kind of instructions we're interested in when
801 implementing -mfix-vr4120. */
c67a084a
NC
802enum fix_vr4120_class
803{
71400594
RS
804 FIX_VR4120_MACC,
805 FIX_VR4120_DMACC,
806 FIX_VR4120_MULT,
807 FIX_VR4120_DMULT,
808 FIX_VR4120_DIV,
809 FIX_VR4120_MTHILO,
810 NUM_FIX_VR4120_CLASSES
811};
812
c67a084a
NC
813/* ...likewise -mfix-loongson2f-jump. */
814static bfd_boolean mips_fix_loongson2f_jump;
815
816/* ...likewise -mfix-loongson2f-nop. */
817static bfd_boolean mips_fix_loongson2f_nop;
818
819/* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */
820static bfd_boolean mips_fix_loongson2f;
821
71400594
RS
822/* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if
823 there must be at least one other instruction between an instruction
824 of type X and an instruction of type Y. */
825static unsigned int vr4120_conflicts[NUM_FIX_VR4120_CLASSES];
826
827/* True if -mfix-vr4120 is in force. */
d766e8ec 828static int mips_fix_vr4120;
4a6a3df4 829
7d8e00cf
RS
830/* ...likewise -mfix-vr4130. */
831static int mips_fix_vr4130;
832
6a32d874
CM
833/* ...likewise -mfix-24k. */
834static int mips_fix_24k;
835
d954098f
DD
836/* ...likewise -mfix-cn63xxp1 */
837static bfd_boolean mips_fix_cn63xxp1;
838
4a6a3df4
AO
839/* We don't relax branches by default, since this causes us to expand
840 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
841 fail to compute the offset before expanding the macro to the most
842 efficient expansion. */
843
844static int mips_relax_branch;
252b5132 845\f
4d7206a2
RS
846/* The expansion of many macros depends on the type of symbol that
847 they refer to. For example, when generating position-dependent code,
848 a macro that refers to a symbol may have two different expansions,
849 one which uses GP-relative addresses and one which uses absolute
850 addresses. When generating SVR4-style PIC, a macro may have
851 different expansions for local and global symbols.
852
853 We handle these situations by generating both sequences and putting
854 them in variant frags. In position-dependent code, the first sequence
855 will be the GP-relative one and the second sequence will be the
856 absolute one. In SVR4 PIC, the first sequence will be for global
857 symbols and the second will be for local symbols.
858
584892a6
RS
859 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
860 SECOND are the lengths of the two sequences in bytes. These fields
861 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
862 the subtype has the following flags:
4d7206a2 863
584892a6
RS
864 RELAX_USE_SECOND
865 Set if it has been decided that we should use the second
866 sequence instead of the first.
867
868 RELAX_SECOND_LONGER
869 Set in the first variant frag if the macro's second implementation
870 is longer than its first. This refers to the macro as a whole,
871 not an individual relaxation.
872
873 RELAX_NOMACRO
874 Set in the first variant frag if the macro appeared in a .set nomacro
875 block and if one alternative requires a warning but the other does not.
876
877 RELAX_DELAY_SLOT
878 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
879 delay slot.
4d7206a2 880
df58fc94
RS
881 RELAX_DELAY_SLOT_16BIT
882 Like RELAX_DELAY_SLOT, but indicates that the delay slot requires a
883 16-bit instruction.
884
885 RELAX_DELAY_SLOT_SIZE_FIRST
886 Like RELAX_DELAY_SLOT, but indicates that the first implementation of
887 the macro is of the wrong size for the branch delay slot.
888
889 RELAX_DELAY_SLOT_SIZE_SECOND
890 Like RELAX_DELAY_SLOT, but indicates that the second implementation of
891 the macro is of the wrong size for the branch delay slot.
892
4d7206a2
RS
893 The frag's "opcode" points to the first fixup for relaxable code.
894
895 Relaxable macros are generated using a sequence such as:
896
897 relax_start (SYMBOL);
898 ... generate first expansion ...
899 relax_switch ();
900 ... generate second expansion ...
901 relax_end ();
902
903 The code and fixups for the unwanted alternative are discarded
904 by md_convert_frag. */
584892a6 905#define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND))
4d7206a2 906
584892a6
RS
907#define RELAX_FIRST(X) (((X) >> 8) & 0xff)
908#define RELAX_SECOND(X) ((X) & 0xff)
909#define RELAX_USE_SECOND 0x10000
910#define RELAX_SECOND_LONGER 0x20000
911#define RELAX_NOMACRO 0x40000
912#define RELAX_DELAY_SLOT 0x80000
df58fc94
RS
913#define RELAX_DELAY_SLOT_16BIT 0x100000
914#define RELAX_DELAY_SLOT_SIZE_FIRST 0x200000
915#define RELAX_DELAY_SLOT_SIZE_SECOND 0x400000
252b5132 916
4a6a3df4
AO
917/* Branch without likely bit. If label is out of range, we turn:
918
919 beq reg1, reg2, label
920 delay slot
921
922 into
923
924 bne reg1, reg2, 0f
925 nop
926 j label
927 0: delay slot
928
929 with the following opcode replacements:
930
931 beq <-> bne
932 blez <-> bgtz
933 bltz <-> bgez
934 bc1f <-> bc1t
935
936 bltzal <-> bgezal (with jal label instead of j label)
937
938 Even though keeping the delay slot instruction in the delay slot of
939 the branch would be more efficient, it would be very tricky to do
940 correctly, because we'd have to introduce a variable frag *after*
941 the delay slot instruction, and expand that instead. Let's do it
942 the easy way for now, even if the branch-not-taken case now costs
943 one additional instruction. Out-of-range branches are not supposed
944 to be common, anyway.
945
946 Branch likely. If label is out of range, we turn:
947
948 beql reg1, reg2, label
949 delay slot (annulled if branch not taken)
950
951 into
952
953 beql reg1, reg2, 1f
954 nop
955 beql $0, $0, 2f
956 nop
957 1: j[al] label
958 delay slot (executed only if branch taken)
959 2:
960
961 It would be possible to generate a shorter sequence by losing the
962 likely bit, generating something like:
b34976b6 963
4a6a3df4
AO
964 bne reg1, reg2, 0f
965 nop
966 j[al] label
967 delay slot (executed only if branch taken)
968 0:
969
970 beql -> bne
971 bnel -> beq
972 blezl -> bgtz
973 bgtzl -> blez
974 bltzl -> bgez
975 bgezl -> bltz
976 bc1fl -> bc1t
977 bc1tl -> bc1f
978
979 bltzall -> bgezal (with jal label instead of j label)
980 bgezall -> bltzal (ditto)
981
982
983 but it's not clear that it would actually improve performance. */
66b3e8da
MR
984#define RELAX_BRANCH_ENCODE(at, uncond, likely, link, toofar) \
985 ((relax_substateT) \
986 (0xc0000000 \
987 | ((at) & 0x1f) \
988 | ((toofar) ? 0x20 : 0) \
989 | ((link) ? 0x40 : 0) \
990 | ((likely) ? 0x80 : 0) \
991 | ((uncond) ? 0x100 : 0)))
4a6a3df4 992#define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
66b3e8da
MR
993#define RELAX_BRANCH_UNCOND(i) (((i) & 0x100) != 0)
994#define RELAX_BRANCH_LIKELY(i) (((i) & 0x80) != 0)
995#define RELAX_BRANCH_LINK(i) (((i) & 0x40) != 0)
996#define RELAX_BRANCH_TOOFAR(i) (((i) & 0x20) != 0)
997#define RELAX_BRANCH_AT(i) ((i) & 0x1f)
4a6a3df4 998
252b5132
RH
999/* For mips16 code, we use an entirely different form of relaxation.
1000 mips16 supports two versions of most instructions which take
1001 immediate values: a small one which takes some small value, and a
1002 larger one which takes a 16 bit value. Since branches also follow
1003 this pattern, relaxing these values is required.
1004
1005 We can assemble both mips16 and normal MIPS code in a single
1006 object. Therefore, we need to support this type of relaxation at
1007 the same time that we support the relaxation described above. We
1008 use the high bit of the subtype field to distinguish these cases.
1009
1010 The information we store for this type of relaxation is the
1011 argument code found in the opcode file for this relocation, whether
1012 the user explicitly requested a small or extended form, and whether
1013 the relocation is in a jump or jal delay slot. That tells us the
1014 size of the value, and how it should be stored. We also store
1015 whether the fragment is considered to be extended or not. We also
1016 store whether this is known to be a branch to a different section,
1017 whether we have tried to relax this frag yet, and whether we have
1018 ever extended a PC relative fragment because of a shift count. */
1019#define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
1020 (0x80000000 \
1021 | ((type) & 0xff) \
1022 | ((small) ? 0x100 : 0) \
1023 | ((ext) ? 0x200 : 0) \
1024 | ((dslot) ? 0x400 : 0) \
1025 | ((jal_dslot) ? 0x800 : 0))
4a6a3df4 1026#define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
252b5132
RH
1027#define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
1028#define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
1029#define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
1030#define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
1031#define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
1032#define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
1033#define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
1034#define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
1035#define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
1036#define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
1037#define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
885add95 1038
df58fc94
RS
1039/* For microMIPS code, we use relaxation similar to one we use for
1040 MIPS16 code. Some instructions that take immediate values support
1041 two encodings: a small one which takes some small value, and a
1042 larger one which takes a 16 bit value. As some branches also follow
1043 this pattern, relaxing these values is required.
1044
1045 We can assemble both microMIPS and normal MIPS code in a single
1046 object. Therefore, we need to support this type of relaxation at
1047 the same time that we support the relaxation described above. We
1048 use one of the high bits of the subtype field to distinguish these
1049 cases.
1050
1051 The information we store for this type of relaxation is the argument
1052 code found in the opcode file for this relocation, the register
40209cad
MR
1053 selected as the assembler temporary, whether the branch is
1054 unconditional, whether it is compact, whether it stores the link
1055 address implicitly in $ra, whether relaxation of out-of-range 32-bit
1056 branches to a sequence of instructions is enabled, and whether the
1057 displacement of a branch is too large to fit as an immediate argument
1058 of a 16-bit and a 32-bit branch, respectively. */
1059#define RELAX_MICROMIPS_ENCODE(type, at, uncond, compact, link, \
1060 relax32, toofar16, toofar32) \
1061 (0x40000000 \
1062 | ((type) & 0xff) \
1063 | (((at) & 0x1f) << 8) \
1064 | ((uncond) ? 0x2000 : 0) \
1065 | ((compact) ? 0x4000 : 0) \
1066 | ((link) ? 0x8000 : 0) \
1067 | ((relax32) ? 0x10000 : 0) \
1068 | ((toofar16) ? 0x20000 : 0) \
1069 | ((toofar32) ? 0x40000 : 0))
df58fc94
RS
1070#define RELAX_MICROMIPS_P(i) (((i) & 0xc0000000) == 0x40000000)
1071#define RELAX_MICROMIPS_TYPE(i) ((i) & 0xff)
1072#define RELAX_MICROMIPS_AT(i) (((i) >> 8) & 0x1f)
40209cad
MR
1073#define RELAX_MICROMIPS_UNCOND(i) (((i) & 0x2000) != 0)
1074#define RELAX_MICROMIPS_COMPACT(i) (((i) & 0x4000) != 0)
1075#define RELAX_MICROMIPS_LINK(i) (((i) & 0x8000) != 0)
1076#define RELAX_MICROMIPS_RELAX32(i) (((i) & 0x10000) != 0)
1077
1078#define RELAX_MICROMIPS_TOOFAR16(i) (((i) & 0x20000) != 0)
1079#define RELAX_MICROMIPS_MARK_TOOFAR16(i) ((i) | 0x20000)
1080#define RELAX_MICROMIPS_CLEAR_TOOFAR16(i) ((i) & ~0x20000)
1081#define RELAX_MICROMIPS_TOOFAR32(i) (((i) & 0x40000) != 0)
1082#define RELAX_MICROMIPS_MARK_TOOFAR32(i) ((i) | 0x40000)
1083#define RELAX_MICROMIPS_CLEAR_TOOFAR32(i) ((i) & ~0x40000)
df58fc94 1084
43c0598f
RS
1085/* Sign-extend 16-bit value X. */
1086#define SEXT_16BIT(X) ((((X) + 0x8000) & 0xffff) - 0x8000)
1087
885add95
CD
1088/* Is the given value a sign-extended 32-bit value? */
1089#define IS_SEXT_32BIT_NUM(x) \
1090 (((x) &~ (offsetT) 0x7fffffff) == 0 \
1091 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
1092
1093/* Is the given value a sign-extended 16-bit value? */
1094#define IS_SEXT_16BIT_NUM(x) \
1095 (((x) &~ (offsetT) 0x7fff) == 0 \
1096 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
1097
df58fc94
RS
1098/* Is the given value a sign-extended 12-bit value? */
1099#define IS_SEXT_12BIT_NUM(x) \
1100 (((((x) & 0xfff) ^ 0x800LL) - 0x800LL) == (x))
1101
7f3c4072
CM
1102/* Is the given value a sign-extended 9-bit value? */
1103#define IS_SEXT_9BIT_NUM(x) \
1104 (((((x) & 0x1ff) ^ 0x100LL) - 0x100LL) == (x))
1105
2051e8c4
MR
1106/* Is the given value a zero-extended 32-bit value? Or a negated one? */
1107#define IS_ZEXT_32BIT_NUM(x) \
1108 (((x) &~ (offsetT) 0xffffffff) == 0 \
1109 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
1110
bf12938e
RS
1111/* Extract bits MASK << SHIFT from STRUCT and shift them right
1112 SHIFT places. */
1113#define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
1114 (((STRUCT) >> (SHIFT)) & (MASK))
1115
bf12938e 1116/* Extract the operand given by FIELD from mips_cl_insn INSN. */
df58fc94
RS
1117#define EXTRACT_OPERAND(MICROMIPS, FIELD, INSN) \
1118 (!(MICROMIPS) \
1119 ? EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) \
1120 : EXTRACT_BITS ((INSN).insn_opcode, \
1121 MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD))
bf12938e
RS
1122#define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \
1123 EXTRACT_BITS ((INSN).insn_opcode, \
1124 MIPS16OP_MASK_##FIELD, \
1125 MIPS16OP_SH_##FIELD)
5c04167a
RS
1126
1127/* The MIPS16 EXTEND opcode, shifted left 16 places. */
1128#define MIPS16_EXTEND (0xf000U << 16)
4d7206a2 1129\f
df58fc94
RS
1130/* Whether or not we are emitting a branch-likely macro. */
1131static bfd_boolean emit_branch_likely_macro = FALSE;
1132
4d7206a2
RS
1133/* Global variables used when generating relaxable macros. See the
1134 comment above RELAX_ENCODE for more details about how relaxation
1135 is used. */
1136static struct {
1137 /* 0 if we're not emitting a relaxable macro.
1138 1 if we're emitting the first of the two relaxation alternatives.
1139 2 if we're emitting the second alternative. */
1140 int sequence;
1141
1142 /* The first relaxable fixup in the current frag. (In other words,
1143 the first fixup that refers to relaxable code.) */
1144 fixS *first_fixup;
1145
1146 /* sizes[0] says how many bytes of the first alternative are stored in
1147 the current frag. Likewise sizes[1] for the second alternative. */
1148 unsigned int sizes[2];
1149
1150 /* The symbol on which the choice of sequence depends. */
1151 symbolS *symbol;
1152} mips_relax;
252b5132 1153\f
584892a6
RS
1154/* Global variables used to decide whether a macro needs a warning. */
1155static struct {
1156 /* True if the macro is in a branch delay slot. */
1157 bfd_boolean delay_slot_p;
1158
df58fc94
RS
1159 /* Set to the length in bytes required if the macro is in a delay slot
1160 that requires a specific length of instruction, otherwise zero. */
1161 unsigned int delay_slot_length;
1162
584892a6
RS
1163 /* For relaxable macros, sizes[0] is the length of the first alternative
1164 in bytes and sizes[1] is the length of the second alternative.
1165 For non-relaxable macros, both elements give the length of the
1166 macro in bytes. */
1167 unsigned int sizes[2];
1168
df58fc94
RS
1169 /* For relaxable macros, first_insn_sizes[0] is the length of the first
1170 instruction of the first alternative in bytes and first_insn_sizes[1]
1171 is the length of the first instruction of the second alternative.
1172 For non-relaxable macros, both elements give the length of the first
1173 instruction in bytes.
1174
1175 Set to zero if we haven't yet seen the first instruction. */
1176 unsigned int first_insn_sizes[2];
1177
1178 /* For relaxable macros, insns[0] is the number of instructions for the
1179 first alternative and insns[1] is the number of instructions for the
1180 second alternative.
1181
1182 For non-relaxable macros, both elements give the number of
1183 instructions for the macro. */
1184 unsigned int insns[2];
1185
584892a6
RS
1186 /* The first variant frag for this macro. */
1187 fragS *first_frag;
1188} mips_macro_warning;
1189\f
252b5132
RH
1190/* Prototypes for static functions. */
1191
252b5132
RH
1192enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG };
1193
b34976b6 1194static void append_insn
df58fc94
RS
1195 (struct mips_cl_insn *, expressionS *, bfd_reloc_code_real_type *,
1196 bfd_boolean expansionp);
7d10b47d 1197static void mips_no_prev_insn (void);
c67a084a 1198static void macro_build (expressionS *, const char *, const char *, ...);
b34976b6 1199static void mips16_macro_build
03ea81db 1200 (expressionS *, const char *, const char *, va_list *);
67c0d1eb 1201static void load_register (int, expressionS *, int);
584892a6
RS
1202static void macro_start (void);
1203static void macro_end (void);
833794fc 1204static void macro (struct mips_cl_insn *ip, char *str);
17a2f251 1205static void mips16_macro (struct mips_cl_insn * ip);
17a2f251
TS
1206static void mips_ip (char *str, struct mips_cl_insn * ip);
1207static void mips16_ip (char *str, struct mips_cl_insn * ip);
b34976b6 1208static void mips16_immed
43c0598f
RS
1209 (char *, unsigned int, int, bfd_reloc_code_real_type, offsetT,
1210 unsigned int, unsigned long *);
5e0116d5 1211static size_t my_getSmallExpression
17a2f251
TS
1212 (expressionS *, bfd_reloc_code_real_type *, char *);
1213static void my_getExpression (expressionS *, char *);
1214static void s_align (int);
1215static void s_change_sec (int);
1216static void s_change_section (int);
1217static void s_cons (int);
1218static void s_float_cons (int);
1219static void s_mips_globl (int);
1220static void s_option (int);
1221static void s_mipsset (int);
1222static void s_abicalls (int);
1223static void s_cpload (int);
1224static void s_cpsetup (int);
1225static void s_cplocal (int);
1226static void s_cprestore (int);
1227static void s_cpreturn (int);
741d6ea8
JM
1228static void s_dtprelword (int);
1229static void s_dtpreldword (int);
d0f13682
CLT
1230static void s_tprelword (int);
1231static void s_tpreldword (int);
17a2f251
TS
1232static void s_gpvalue (int);
1233static void s_gpword (int);
1234static void s_gpdword (int);
a3f278e2 1235static void s_ehword (int);
17a2f251
TS
1236static void s_cpadd (int);
1237static void s_insn (int);
ba92f887 1238static void s_nan (int);
17a2f251
TS
1239static void md_obj_begin (void);
1240static void md_obj_end (void);
1241static void s_mips_ent (int);
1242static void s_mips_end (int);
1243static void s_mips_frame (int);
1244static void s_mips_mask (int reg_type);
1245static void s_mips_stab (int);
1246static void s_mips_weakext (int);
1247static void s_mips_file (int);
1248static void s_mips_loc (int);
1249static bfd_boolean pic_need_relax (symbolS *, asection *);
4a6a3df4 1250static int relaxed_branch_length (fragS *, asection *, int);
df58fc94
RS
1251static int relaxed_micromips_16bit_branch_length (fragS *, asection *, int);
1252static int relaxed_micromips_32bit_branch_length (fragS *, asection *, int);
e7af610e
NC
1253
1254/* Table and functions used to map between CPU/ISA names, and
1255 ISA levels, and CPU numbers. */
1256
e972090a
NC
1257struct mips_cpu_info
1258{
e7af610e 1259 const char *name; /* CPU or ISA name. */
d16afab6
RS
1260 int flags; /* MIPS_CPU_* flags. */
1261 int ase; /* Set of ASEs implemented by the CPU. */
e7af610e
NC
1262 int isa; /* ISA level. */
1263 int cpu; /* CPU number (default CPU if ISA). */
1264};
1265
ad3fea08 1266#define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */
ad3fea08 1267
17a2f251
TS
1268static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *);
1269static const struct mips_cpu_info *mips_cpu_info_from_isa (int);
1270static const struct mips_cpu_info *mips_cpu_info_from_arch (int);
252b5132 1271\f
c31f3936
RS
1272/* Command-line options. */
1273const char *md_shortopts = "O::g::G:";
1274
1275enum options
1276 {
1277 OPTION_MARCH = OPTION_MD_BASE,
1278 OPTION_MTUNE,
1279 OPTION_MIPS1,
1280 OPTION_MIPS2,
1281 OPTION_MIPS3,
1282 OPTION_MIPS4,
1283 OPTION_MIPS5,
1284 OPTION_MIPS32,
1285 OPTION_MIPS64,
1286 OPTION_MIPS32R2,
1287 OPTION_MIPS64R2,
1288 OPTION_MIPS16,
1289 OPTION_NO_MIPS16,
1290 OPTION_MIPS3D,
1291 OPTION_NO_MIPS3D,
1292 OPTION_MDMX,
1293 OPTION_NO_MDMX,
1294 OPTION_DSP,
1295 OPTION_NO_DSP,
1296 OPTION_MT,
1297 OPTION_NO_MT,
1298 OPTION_VIRT,
1299 OPTION_NO_VIRT,
1300 OPTION_SMARTMIPS,
1301 OPTION_NO_SMARTMIPS,
1302 OPTION_DSPR2,
1303 OPTION_NO_DSPR2,
1304 OPTION_EVA,
1305 OPTION_NO_EVA,
1306 OPTION_MICROMIPS,
1307 OPTION_NO_MICROMIPS,
1308 OPTION_MCU,
1309 OPTION_NO_MCU,
1310 OPTION_COMPAT_ARCH_BASE,
1311 OPTION_M4650,
1312 OPTION_NO_M4650,
1313 OPTION_M4010,
1314 OPTION_NO_M4010,
1315 OPTION_M4100,
1316 OPTION_NO_M4100,
1317 OPTION_M3900,
1318 OPTION_NO_M3900,
1319 OPTION_M7000_HILO_FIX,
1320 OPTION_MNO_7000_HILO_FIX,
1321 OPTION_FIX_24K,
1322 OPTION_NO_FIX_24K,
1323 OPTION_FIX_LOONGSON2F_JUMP,
1324 OPTION_NO_FIX_LOONGSON2F_JUMP,
1325 OPTION_FIX_LOONGSON2F_NOP,
1326 OPTION_NO_FIX_LOONGSON2F_NOP,
1327 OPTION_FIX_VR4120,
1328 OPTION_NO_FIX_VR4120,
1329 OPTION_FIX_VR4130,
1330 OPTION_NO_FIX_VR4130,
1331 OPTION_FIX_CN63XXP1,
1332 OPTION_NO_FIX_CN63XXP1,
1333 OPTION_TRAP,
1334 OPTION_BREAK,
1335 OPTION_EB,
1336 OPTION_EL,
1337 OPTION_FP32,
1338 OPTION_GP32,
1339 OPTION_CONSTRUCT_FLOATS,
1340 OPTION_NO_CONSTRUCT_FLOATS,
1341 OPTION_FP64,
1342 OPTION_GP64,
1343 OPTION_RELAX_BRANCH,
1344 OPTION_NO_RELAX_BRANCH,
833794fc
MR
1345 OPTION_INSN32,
1346 OPTION_NO_INSN32,
c31f3936
RS
1347 OPTION_MSHARED,
1348 OPTION_MNO_SHARED,
1349 OPTION_MSYM32,
1350 OPTION_MNO_SYM32,
1351 OPTION_SOFT_FLOAT,
1352 OPTION_HARD_FLOAT,
1353 OPTION_SINGLE_FLOAT,
1354 OPTION_DOUBLE_FLOAT,
1355 OPTION_32,
c31f3936
RS
1356 OPTION_CALL_SHARED,
1357 OPTION_CALL_NONPIC,
1358 OPTION_NON_SHARED,
1359 OPTION_XGOT,
1360 OPTION_MABI,
1361 OPTION_N32,
1362 OPTION_64,
1363 OPTION_MDEBUG,
1364 OPTION_NO_MDEBUG,
1365 OPTION_PDR,
1366 OPTION_NO_PDR,
1367 OPTION_MVXWORKS_PIC,
ba92f887 1368 OPTION_NAN,
c31f3936
RS
1369 OPTION_END_OF_ENUM
1370 };
1371
1372struct option md_longopts[] =
1373{
1374 /* Options which specify architecture. */
1375 {"march", required_argument, NULL, OPTION_MARCH},
1376 {"mtune", required_argument, NULL, OPTION_MTUNE},
1377 {"mips0", no_argument, NULL, OPTION_MIPS1},
1378 {"mips1", no_argument, NULL, OPTION_MIPS1},
1379 {"mips2", no_argument, NULL, OPTION_MIPS2},
1380 {"mips3", no_argument, NULL, OPTION_MIPS3},
1381 {"mips4", no_argument, NULL, OPTION_MIPS4},
1382 {"mips5", no_argument, NULL, OPTION_MIPS5},
1383 {"mips32", no_argument, NULL, OPTION_MIPS32},
1384 {"mips64", no_argument, NULL, OPTION_MIPS64},
1385 {"mips32r2", no_argument, NULL, OPTION_MIPS32R2},
1386 {"mips64r2", no_argument, NULL, OPTION_MIPS64R2},
1387
1388 /* Options which specify Application Specific Extensions (ASEs). */
1389 {"mips16", no_argument, NULL, OPTION_MIPS16},
1390 {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16},
1391 {"mips3d", no_argument, NULL, OPTION_MIPS3D},
1392 {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D},
1393 {"mdmx", no_argument, NULL, OPTION_MDMX},
1394 {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX},
1395 {"mdsp", no_argument, NULL, OPTION_DSP},
1396 {"mno-dsp", no_argument, NULL, OPTION_NO_DSP},
1397 {"mmt", no_argument, NULL, OPTION_MT},
1398 {"mno-mt", no_argument, NULL, OPTION_NO_MT},
1399 {"msmartmips", no_argument, NULL, OPTION_SMARTMIPS},
1400 {"mno-smartmips", no_argument, NULL, OPTION_NO_SMARTMIPS},
1401 {"mdspr2", no_argument, NULL, OPTION_DSPR2},
1402 {"mno-dspr2", no_argument, NULL, OPTION_NO_DSPR2},
1403 {"meva", no_argument, NULL, OPTION_EVA},
1404 {"mno-eva", no_argument, NULL, OPTION_NO_EVA},
1405 {"mmicromips", no_argument, NULL, OPTION_MICROMIPS},
1406 {"mno-micromips", no_argument, NULL, OPTION_NO_MICROMIPS},
1407 {"mmcu", no_argument, NULL, OPTION_MCU},
1408 {"mno-mcu", no_argument, NULL, OPTION_NO_MCU},
1409 {"mvirt", no_argument, NULL, OPTION_VIRT},
1410 {"mno-virt", no_argument, NULL, OPTION_NO_VIRT},
1411
1412 /* Old-style architecture options. Don't add more of these. */
1413 {"m4650", no_argument, NULL, OPTION_M4650},
1414 {"no-m4650", no_argument, NULL, OPTION_NO_M4650},
1415 {"m4010", no_argument, NULL, OPTION_M4010},
1416 {"no-m4010", no_argument, NULL, OPTION_NO_M4010},
1417 {"m4100", no_argument, NULL, OPTION_M4100},
1418 {"no-m4100", no_argument, NULL, OPTION_NO_M4100},
1419 {"m3900", no_argument, NULL, OPTION_M3900},
1420 {"no-m3900", no_argument, NULL, OPTION_NO_M3900},
1421
1422 /* Options which enable bug fixes. */
1423 {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX},
1424 {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
1425 {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
1426 {"mfix-loongson2f-jump", no_argument, NULL, OPTION_FIX_LOONGSON2F_JUMP},
1427 {"mno-fix-loongson2f-jump", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_JUMP},
1428 {"mfix-loongson2f-nop", no_argument, NULL, OPTION_FIX_LOONGSON2F_NOP},
1429 {"mno-fix-loongson2f-nop", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_NOP},
1430 {"mfix-vr4120", no_argument, NULL, OPTION_FIX_VR4120},
1431 {"mno-fix-vr4120", no_argument, NULL, OPTION_NO_FIX_VR4120},
1432 {"mfix-vr4130", no_argument, NULL, OPTION_FIX_VR4130},
1433 {"mno-fix-vr4130", no_argument, NULL, OPTION_NO_FIX_VR4130},
1434 {"mfix-24k", no_argument, NULL, OPTION_FIX_24K},
1435 {"mno-fix-24k", no_argument, NULL, OPTION_NO_FIX_24K},
1436 {"mfix-cn63xxp1", no_argument, NULL, OPTION_FIX_CN63XXP1},
1437 {"mno-fix-cn63xxp1", no_argument, NULL, OPTION_NO_FIX_CN63XXP1},
1438
1439 /* Miscellaneous options. */
1440 {"trap", no_argument, NULL, OPTION_TRAP},
1441 {"no-break", no_argument, NULL, OPTION_TRAP},
1442 {"break", no_argument, NULL, OPTION_BREAK},
1443 {"no-trap", no_argument, NULL, OPTION_BREAK},
1444 {"EB", no_argument, NULL, OPTION_EB},
1445 {"EL", no_argument, NULL, OPTION_EL},
1446 {"mfp32", no_argument, NULL, OPTION_FP32},
1447 {"mgp32", no_argument, NULL, OPTION_GP32},
1448 {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS},
1449 {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS},
1450 {"mfp64", no_argument, NULL, OPTION_FP64},
1451 {"mgp64", no_argument, NULL, OPTION_GP64},
1452 {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH},
1453 {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH},
833794fc
MR
1454 {"minsn32", no_argument, NULL, OPTION_INSN32},
1455 {"mno-insn32", no_argument, NULL, OPTION_NO_INSN32},
c31f3936
RS
1456 {"mshared", no_argument, NULL, OPTION_MSHARED},
1457 {"mno-shared", no_argument, NULL, OPTION_MNO_SHARED},
1458 {"msym32", no_argument, NULL, OPTION_MSYM32},
1459 {"mno-sym32", no_argument, NULL, OPTION_MNO_SYM32},
1460 {"msoft-float", no_argument, NULL, OPTION_SOFT_FLOAT},
1461 {"mhard-float", no_argument, NULL, OPTION_HARD_FLOAT},
1462 {"msingle-float", no_argument, NULL, OPTION_SINGLE_FLOAT},
1463 {"mdouble-float", no_argument, NULL, OPTION_DOUBLE_FLOAT},
1464
1465 /* Strictly speaking this next option is ELF specific,
1466 but we allow it for other ports as well in order to
1467 make testing easier. */
1468 {"32", no_argument, NULL, OPTION_32},
1469
1470 /* ELF-specific options. */
c31f3936
RS
1471 {"KPIC", no_argument, NULL, OPTION_CALL_SHARED},
1472 {"call_shared", no_argument, NULL, OPTION_CALL_SHARED},
1473 {"call_nonpic", no_argument, NULL, OPTION_CALL_NONPIC},
1474 {"non_shared", no_argument, NULL, OPTION_NON_SHARED},
1475 {"xgot", no_argument, NULL, OPTION_XGOT},
1476 {"mabi", required_argument, NULL, OPTION_MABI},
1477 {"n32", no_argument, NULL, OPTION_N32},
1478 {"64", no_argument, NULL, OPTION_64},
1479 {"mdebug", no_argument, NULL, OPTION_MDEBUG},
1480 {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG},
1481 {"mpdr", no_argument, NULL, OPTION_PDR},
1482 {"mno-pdr", no_argument, NULL, OPTION_NO_PDR},
1483 {"mvxworks-pic", no_argument, NULL, OPTION_MVXWORKS_PIC},
ba92f887 1484 {"mnan", required_argument, NULL, OPTION_NAN},
c31f3936
RS
1485
1486 {NULL, no_argument, NULL, 0}
1487};
1488size_t md_longopts_size = sizeof (md_longopts);
1489\f
c6278170
RS
1490/* Information about either an Application Specific Extension or an
1491 optional architecture feature that, for simplicity, we treat in the
1492 same way as an ASE. */
1493struct mips_ase
1494{
1495 /* The name of the ASE, used in both the command-line and .set options. */
1496 const char *name;
1497
1498 /* The associated ASE_* flags. If the ASE is available on both 32-bit
1499 and 64-bit architectures, the flags here refer to the subset that
1500 is available on both. */
1501 unsigned int flags;
1502
1503 /* The ASE_* flag used for instructions that are available on 64-bit
1504 architectures but that are not included in FLAGS. */
1505 unsigned int flags64;
1506
1507 /* The command-line options that turn the ASE on and off. */
1508 int option_on;
1509 int option_off;
1510
1511 /* The minimum required architecture revisions for MIPS32, MIPS64,
1512 microMIPS32 and microMIPS64, or -1 if the extension isn't supported. */
1513 int mips32_rev;
1514 int mips64_rev;
1515 int micromips32_rev;
1516 int micromips64_rev;
1517};
1518
1519/* A table of all supported ASEs. */
1520static const struct mips_ase mips_ases[] = {
1521 { "dsp", ASE_DSP, ASE_DSP64,
1522 OPTION_DSP, OPTION_NO_DSP,
1523 2, 2, 2, 2 },
1524
1525 { "dspr2", ASE_DSP | ASE_DSPR2, 0,
1526 OPTION_DSPR2, OPTION_NO_DSPR2,
1527 2, 2, 2, 2 },
1528
1529 { "eva", ASE_EVA, 0,
1530 OPTION_EVA, OPTION_NO_EVA,
1531 2, 2, 2, 2 },
1532
1533 { "mcu", ASE_MCU, 0,
1534 OPTION_MCU, OPTION_NO_MCU,
1535 2, 2, 2, 2 },
1536
1537 /* Deprecated in MIPS64r5, but we don't implement that yet. */
1538 { "mdmx", ASE_MDMX, 0,
1539 OPTION_MDMX, OPTION_NO_MDMX,
1540 -1, 1, -1, -1 },
1541
1542 /* Requires 64-bit FPRs, so the minimum MIPS32 revision is 2. */
1543 { "mips3d", ASE_MIPS3D, 0,
1544 OPTION_MIPS3D, OPTION_NO_MIPS3D,
1545 2, 1, -1, -1 },
1546
1547 { "mt", ASE_MT, 0,
1548 OPTION_MT, OPTION_NO_MT,
1549 2, 2, -1, -1 },
1550
1551 { "smartmips", ASE_SMARTMIPS, 0,
1552 OPTION_SMARTMIPS, OPTION_NO_SMARTMIPS,
1553 1, -1, -1, -1 },
1554
1555 { "virt", ASE_VIRT, ASE_VIRT64,
1556 OPTION_VIRT, OPTION_NO_VIRT,
1557 2, 2, 2, 2 }
1558};
1559
1560/* The set of ASEs that require -mfp64. */
1561#define FP64_ASES (ASE_MIPS3D | ASE_MDMX)
1562
1563/* Groups of ASE_* flags that represent different revisions of an ASE. */
1564static const unsigned int mips_ase_groups[] = {
1565 ASE_DSP | ASE_DSPR2
1566};
1567\f
252b5132
RH
1568/* Pseudo-op table.
1569
1570 The following pseudo-ops from the Kane and Heinrich MIPS book
1571 should be defined here, but are currently unsupported: .alias,
1572 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
1573
1574 The following pseudo-ops from the Kane and Heinrich MIPS book are
1575 specific to the type of debugging information being generated, and
1576 should be defined by the object format: .aent, .begin, .bend,
1577 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
1578 .vreg.
1579
1580 The following pseudo-ops from the Kane and Heinrich MIPS book are
1581 not MIPS CPU specific, but are also not specific to the object file
1582 format. This file is probably the best place to define them, but
d84bcf09 1583 they are not currently supported: .asm0, .endr, .lab, .struct. */
252b5132 1584
e972090a
NC
1585static const pseudo_typeS mips_pseudo_table[] =
1586{
beae10d5 1587 /* MIPS specific pseudo-ops. */
252b5132
RH
1588 {"option", s_option, 0},
1589 {"set", s_mipsset, 0},
1590 {"rdata", s_change_sec, 'r'},
1591 {"sdata", s_change_sec, 's'},
1592 {"livereg", s_ignore, 0},
1593 {"abicalls", s_abicalls, 0},
1594 {"cpload", s_cpload, 0},
6478892d
TS
1595 {"cpsetup", s_cpsetup, 0},
1596 {"cplocal", s_cplocal, 0},
252b5132 1597 {"cprestore", s_cprestore, 0},
6478892d 1598 {"cpreturn", s_cpreturn, 0},
741d6ea8
JM
1599 {"dtprelword", s_dtprelword, 0},
1600 {"dtpreldword", s_dtpreldword, 0},
d0f13682
CLT
1601 {"tprelword", s_tprelword, 0},
1602 {"tpreldword", s_tpreldword, 0},
6478892d 1603 {"gpvalue", s_gpvalue, 0},
252b5132 1604 {"gpword", s_gpword, 0},
10181a0d 1605 {"gpdword", s_gpdword, 0},
a3f278e2 1606 {"ehword", s_ehword, 0},
252b5132
RH
1607 {"cpadd", s_cpadd, 0},
1608 {"insn", s_insn, 0},
ba92f887 1609 {"nan", s_nan, 0},
252b5132 1610
beae10d5 1611 /* Relatively generic pseudo-ops that happen to be used on MIPS
252b5132 1612 chips. */
38a57ae7 1613 {"asciiz", stringer, 8 + 1},
252b5132
RH
1614 {"bss", s_change_sec, 'b'},
1615 {"err", s_err, 0},
1616 {"half", s_cons, 1},
1617 {"dword", s_cons, 3},
1618 {"weakext", s_mips_weakext, 0},
7c752c2a
TS
1619 {"origin", s_org, 0},
1620 {"repeat", s_rept, 0},
252b5132 1621
998b3c36
MR
1622 /* For MIPS this is non-standard, but we define it for consistency. */
1623 {"sbss", s_change_sec, 'B'},
1624
beae10d5 1625 /* These pseudo-ops are defined in read.c, but must be overridden
252b5132
RH
1626 here for one reason or another. */
1627 {"align", s_align, 0},
1628 {"byte", s_cons, 0},
1629 {"data", s_change_sec, 'd'},
1630 {"double", s_float_cons, 'd'},
1631 {"float", s_float_cons, 'f'},
1632 {"globl", s_mips_globl, 0},
1633 {"global", s_mips_globl, 0},
1634 {"hword", s_cons, 1},
1635 {"int", s_cons, 2},
1636 {"long", s_cons, 2},
1637 {"octa", s_cons, 4},
1638 {"quad", s_cons, 3},
cca86cc8 1639 {"section", s_change_section, 0},
252b5132
RH
1640 {"short", s_cons, 1},
1641 {"single", s_float_cons, 'f'},
754e2bb9 1642 {"stabd", s_mips_stab, 'd'},
252b5132 1643 {"stabn", s_mips_stab, 'n'},
754e2bb9 1644 {"stabs", s_mips_stab, 's'},
252b5132
RH
1645 {"text", s_change_sec, 't'},
1646 {"word", s_cons, 2},
add56521 1647
add56521 1648 { "extern", ecoff_directive_extern, 0},
add56521 1649
43841e91 1650 { NULL, NULL, 0 },
252b5132
RH
1651};
1652
e972090a
NC
1653static const pseudo_typeS mips_nonecoff_pseudo_table[] =
1654{
beae10d5
KH
1655 /* These pseudo-ops should be defined by the object file format.
1656 However, a.out doesn't support them, so we have versions here. */
252b5132
RH
1657 {"aent", s_mips_ent, 1},
1658 {"bgnb", s_ignore, 0},
1659 {"end", s_mips_end, 0},
1660 {"endb", s_ignore, 0},
1661 {"ent", s_mips_ent, 0},
c5dd6aab 1662 {"file", s_mips_file, 0},
252b5132
RH
1663 {"fmask", s_mips_mask, 'F'},
1664 {"frame", s_mips_frame, 0},
c5dd6aab 1665 {"loc", s_mips_loc, 0},
252b5132
RH
1666 {"mask", s_mips_mask, 'R'},
1667 {"verstamp", s_ignore, 0},
43841e91 1668 { NULL, NULL, 0 },
252b5132
RH
1669};
1670
3ae8dd8d
MR
1671/* Export the ABI address size for use by TC_ADDRESS_BYTES for the
1672 purpose of the `.dc.a' internal pseudo-op. */
1673
1674int
1675mips_address_bytes (void)
1676{
1677 return HAVE_64BIT_ADDRESSES ? 8 : 4;
1678}
1679
17a2f251 1680extern void pop_insert (const pseudo_typeS *);
252b5132
RH
1681
1682void
17a2f251 1683mips_pop_insert (void)
252b5132
RH
1684{
1685 pop_insert (mips_pseudo_table);
1686 if (! ECOFF_DEBUGGING)
1687 pop_insert (mips_nonecoff_pseudo_table);
1688}
1689\f
1690/* Symbols labelling the current insn. */
1691
e972090a
NC
1692struct insn_label_list
1693{
252b5132
RH
1694 struct insn_label_list *next;
1695 symbolS *label;
1696};
1697
252b5132 1698static struct insn_label_list *free_insn_labels;
742a56fe 1699#define label_list tc_segment_info_data.labels
252b5132 1700
17a2f251 1701static void mips_clear_insn_labels (void);
df58fc94
RS
1702static void mips_mark_labels (void);
1703static void mips_compressed_mark_labels (void);
252b5132
RH
1704
1705static inline void
17a2f251 1706mips_clear_insn_labels (void)
252b5132
RH
1707{
1708 register struct insn_label_list **pl;
a8dbcb85 1709 segment_info_type *si;
252b5132 1710
a8dbcb85
TS
1711 if (now_seg)
1712 {
1713 for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next)
1714 ;
1715
1716 si = seg_info (now_seg);
1717 *pl = si->label_list;
1718 si->label_list = NULL;
1719 }
252b5132 1720}
a8dbcb85 1721
df58fc94
RS
1722/* Mark instruction labels in MIPS16/microMIPS mode. */
1723
1724static inline void
1725mips_mark_labels (void)
1726{
1727 if (HAVE_CODE_COMPRESSION)
1728 mips_compressed_mark_labels ();
1729}
252b5132
RH
1730\f
1731static char *expr_end;
1732
77bd4346
RS
1733/* Expressions which appear in macro instructions. These are set by
1734 mips_ip and read by macro. */
252b5132
RH
1735
1736static expressionS imm_expr;
5f74bc13 1737static expressionS imm2_expr;
252b5132 1738
77bd4346
RS
1739/* The relocatable field in an instruction and the relocs associated
1740 with it. These variables are used for instructions like LUI and
1741 JAL as well as true offsets. They are also used for address
1742 operands in macros. */
252b5132 1743
77bd4346 1744static expressionS offset_expr;
f6688943
TS
1745static bfd_reloc_code_real_type offset_reloc[3]
1746 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
252b5132 1747
df58fc94
RS
1748/* This is set to the resulting size of the instruction to be produced
1749 by mips16_ip if an explicit extension is used or by mips_ip if an
1750 explicit size is supplied. */
252b5132 1751
df58fc94 1752static unsigned int forced_insn_length;
252b5132 1753
e1b47bd5
RS
1754/* True if we are assembling an instruction. All dot symbols defined during
1755 this time should be treated as code labels. */
1756
1757static bfd_boolean mips_assembling_insn;
1758
ecb4347a
DJ
1759/* The pdr segment for per procedure frame/regmask info. Not used for
1760 ECOFF debugging. */
252b5132
RH
1761
1762static segT pdr_seg;
252b5132 1763
e013f690
TS
1764/* The default target format to use. */
1765
aeffff67
RS
1766#if defined (TE_FreeBSD)
1767#define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd"
1768#elif defined (TE_TMIPS)
1769#define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips"
1770#else
1771#define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips"
1772#endif
1773
e013f690 1774const char *
17a2f251 1775mips_target_format (void)
e013f690
TS
1776{
1777 switch (OUTPUT_FLAVOR)
1778 {
e013f690 1779 case bfd_target_elf_flavour:
0a44bf69
RS
1780#ifdef TE_VXWORKS
1781 if (!HAVE_64BIT_OBJECTS && !HAVE_NEWABI)
1782 return (target_big_endian
1783 ? "elf32-bigmips-vxworks"
1784 : "elf32-littlemips-vxworks");
1785#endif
e013f690 1786 return (target_big_endian
cfe86eaa 1787 ? (HAVE_64BIT_OBJECTS
aeffff67 1788 ? ELF_TARGET ("elf64-", "big")
cfe86eaa 1789 : (HAVE_NEWABI
aeffff67
RS
1790 ? ELF_TARGET ("elf32-n", "big")
1791 : ELF_TARGET ("elf32-", "big")))
cfe86eaa 1792 : (HAVE_64BIT_OBJECTS
aeffff67 1793 ? ELF_TARGET ("elf64-", "little")
cfe86eaa 1794 : (HAVE_NEWABI
aeffff67
RS
1795 ? ELF_TARGET ("elf32-n", "little")
1796 : ELF_TARGET ("elf32-", "little"))));
e013f690
TS
1797 default:
1798 abort ();
1799 return NULL;
1800 }
1801}
1802
c6278170
RS
1803/* Return the ISA revision that is currently in use, or 0 if we are
1804 generating code for MIPS V or below. */
1805
1806static int
1807mips_isa_rev (void)
1808{
1809 if (mips_opts.isa == ISA_MIPS32R2 || mips_opts.isa == ISA_MIPS64R2)
1810 return 2;
1811
1812 /* microMIPS implies revision 2 or above. */
1813 if (mips_opts.micromips)
1814 return 2;
1815
1816 if (mips_opts.isa == ISA_MIPS32 || mips_opts.isa == ISA_MIPS64)
1817 return 1;
1818
1819 return 0;
1820}
1821
1822/* Return the mask of all ASEs that are revisions of those in FLAGS. */
1823
1824static unsigned int
1825mips_ase_mask (unsigned int flags)
1826{
1827 unsigned int i;
1828
1829 for (i = 0; i < ARRAY_SIZE (mips_ase_groups); i++)
1830 if (flags & mips_ase_groups[i])
1831 flags |= mips_ase_groups[i];
1832 return flags;
1833}
1834
1835/* Check whether the current ISA supports ASE. Issue a warning if
1836 appropriate. */
1837
1838static void
1839mips_check_isa_supports_ase (const struct mips_ase *ase)
1840{
1841 const char *base;
1842 int min_rev, size;
1843 static unsigned int warned_isa;
1844 static unsigned int warned_fp32;
1845
1846 if (ISA_HAS_64BIT_REGS (mips_opts.isa))
1847 min_rev = mips_opts.micromips ? ase->micromips64_rev : ase->mips64_rev;
1848 else
1849 min_rev = mips_opts.micromips ? ase->micromips32_rev : ase->mips32_rev;
1850 if ((min_rev < 0 || mips_isa_rev () < min_rev)
1851 && (warned_isa & ase->flags) != ase->flags)
1852 {
1853 warned_isa |= ase->flags;
1854 base = mips_opts.micromips ? "microMIPS" : "MIPS";
1855 size = ISA_HAS_64BIT_REGS (mips_opts.isa) ? 64 : 32;
1856 if (min_rev < 0)
1857 as_warn (_("The %d-bit %s architecture does not support the"
1858 " `%s' extension"), size, base, ase->name);
1859 else
1860 as_warn (_("The `%s' extension requires %s%d revision %d or greater"),
1861 ase->name, base, size, min_rev);
1862 }
1863 if ((ase->flags & FP64_ASES)
1864 && mips_opts.fp32
1865 && (warned_fp32 & ase->flags) != ase->flags)
1866 {
1867 warned_fp32 |= ase->flags;
1868 as_warn (_("The `%s' extension requires 64-bit FPRs"), ase->name);
1869 }
1870}
1871
1872/* Check all enabled ASEs to see whether they are supported by the
1873 chosen architecture. */
1874
1875static void
1876mips_check_isa_supports_ases (void)
1877{
1878 unsigned int i, mask;
1879
1880 for (i = 0; i < ARRAY_SIZE (mips_ases); i++)
1881 {
1882 mask = mips_ase_mask (mips_ases[i].flags);
1883 if ((mips_opts.ase & mask) == mips_ases[i].flags)
1884 mips_check_isa_supports_ase (&mips_ases[i]);
1885 }
1886}
1887
1888/* Set the state of ASE to ENABLED_P. Return the mask of ASE_* flags
1889 that were affected. */
1890
1891static unsigned int
1892mips_set_ase (const struct mips_ase *ase, bfd_boolean enabled_p)
1893{
1894 unsigned int mask;
1895
1896 mask = mips_ase_mask (ase->flags);
1897 mips_opts.ase &= ~mask;
1898 if (enabled_p)
1899 mips_opts.ase |= ase->flags;
1900 return mask;
1901}
1902
1903/* Return the ASE called NAME, or null if none. */
1904
1905static const struct mips_ase *
1906mips_lookup_ase (const char *name)
1907{
1908 unsigned int i;
1909
1910 for (i = 0; i < ARRAY_SIZE (mips_ases); i++)
1911 if (strcmp (name, mips_ases[i].name) == 0)
1912 return &mips_ases[i];
1913 return NULL;
1914}
1915
df58fc94
RS
1916/* Return the length of a microMIPS instruction in bytes. If bits of
1917 the mask beyond the low 16 are 0, then it is a 16-bit instruction.
1918 Otherwise assume a 32-bit instruction; 48-bit instructions (0x1f
1919 major opcode) will require further modifications to the opcode
1920 table. */
1921
1922static inline unsigned int
1923micromips_insn_length (const struct mips_opcode *mo)
1924{
1925 return (mo->mask >> 16) == 0 ? 2 : 4;
1926}
1927
5c04167a
RS
1928/* Return the length of MIPS16 instruction OPCODE. */
1929
1930static inline unsigned int
1931mips16_opcode_length (unsigned long opcode)
1932{
1933 return (opcode >> 16) == 0 ? 2 : 4;
1934}
1935
1e915849
RS
1936/* Return the length of instruction INSN. */
1937
1938static inline unsigned int
1939insn_length (const struct mips_cl_insn *insn)
1940{
df58fc94
RS
1941 if (mips_opts.micromips)
1942 return micromips_insn_length (insn->insn_mo);
1943 else if (mips_opts.mips16)
5c04167a 1944 return mips16_opcode_length (insn->insn_opcode);
df58fc94 1945 else
1e915849 1946 return 4;
1e915849
RS
1947}
1948
1949/* Initialise INSN from opcode entry MO. Leave its position unspecified. */
1950
1951static void
1952create_insn (struct mips_cl_insn *insn, const struct mips_opcode *mo)
1953{
1954 size_t i;
1955
1956 insn->insn_mo = mo;
1e915849
RS
1957 insn->insn_opcode = mo->match;
1958 insn->frag = NULL;
1959 insn->where = 0;
1960 for (i = 0; i < ARRAY_SIZE (insn->fixp); i++)
1961 insn->fixp[i] = NULL;
1962 insn->fixed_p = (mips_opts.noreorder > 0);
1963 insn->noreorder_p = (mips_opts.noreorder > 0);
1964 insn->mips16_absolute_jump_p = 0;
15be625d 1965 insn->complete_p = 0;
e407c74b 1966 insn->cleared_p = 0;
1e915849
RS
1967}
1968
e077a1c8
RS
1969/* Install UVAL as the value of OPERAND in INSN. */
1970
1971static inline void
1972insn_insert_operand (struct mips_cl_insn *insn,
1973 const struct mips_operand *operand, unsigned int uval)
1974{
1975 insn->insn_opcode = mips_insert_operand (operand, insn->insn_opcode, uval);
1976}
1977
df58fc94 1978/* Record the current MIPS16/microMIPS mode in now_seg. */
742a56fe
RS
1979
1980static void
df58fc94 1981mips_record_compressed_mode (void)
742a56fe
RS
1982{
1983 segment_info_type *si;
1984
1985 si = seg_info (now_seg);
1986 if (si->tc_segment_info_data.mips16 != mips_opts.mips16)
1987 si->tc_segment_info_data.mips16 = mips_opts.mips16;
df58fc94
RS
1988 if (si->tc_segment_info_data.micromips != mips_opts.micromips)
1989 si->tc_segment_info_data.micromips = mips_opts.micromips;
742a56fe
RS
1990}
1991
4d68580a
RS
1992/* Read a standard MIPS instruction from BUF. */
1993
1994static unsigned long
1995read_insn (char *buf)
1996{
1997 if (target_big_endian)
1998 return bfd_getb32 ((bfd_byte *) buf);
1999 else
2000 return bfd_getl32 ((bfd_byte *) buf);
2001}
2002
2003/* Write standard MIPS instruction INSN to BUF. Return a pointer to
2004 the next byte. */
2005
2006static char *
2007write_insn (char *buf, unsigned int insn)
2008{
2009 md_number_to_chars (buf, insn, 4);
2010 return buf + 4;
2011}
2012
2013/* Read a microMIPS or MIPS16 opcode from BUF, given that it
2014 has length LENGTH. */
2015
2016static unsigned long
2017read_compressed_insn (char *buf, unsigned int length)
2018{
2019 unsigned long insn;
2020 unsigned int i;
2021
2022 insn = 0;
2023 for (i = 0; i < length; i += 2)
2024 {
2025 insn <<= 16;
2026 if (target_big_endian)
2027 insn |= bfd_getb16 ((char *) buf);
2028 else
2029 insn |= bfd_getl16 ((char *) buf);
2030 buf += 2;
2031 }
2032 return insn;
2033}
2034
5c04167a
RS
2035/* Write microMIPS or MIPS16 instruction INSN to BUF, given that the
2036 instruction is LENGTH bytes long. Return a pointer to the next byte. */
2037
2038static char *
2039write_compressed_insn (char *buf, unsigned int insn, unsigned int length)
2040{
2041 unsigned int i;
2042
2043 for (i = 0; i < length; i += 2)
2044 md_number_to_chars (buf + i, insn >> ((length - i - 2) * 8), 2);
2045 return buf + length;
2046}
2047
1e915849
RS
2048/* Install INSN at the location specified by its "frag" and "where" fields. */
2049
2050static void
2051install_insn (const struct mips_cl_insn *insn)
2052{
2053 char *f = insn->frag->fr_literal + insn->where;
5c04167a
RS
2054 if (HAVE_CODE_COMPRESSION)
2055 write_compressed_insn (f, insn->insn_opcode, insn_length (insn));
1e915849 2056 else
4d68580a 2057 write_insn (f, insn->insn_opcode);
df58fc94 2058 mips_record_compressed_mode ();
1e915849
RS
2059}
2060
2061/* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
2062 and install the opcode in the new location. */
2063
2064static void
2065move_insn (struct mips_cl_insn *insn, fragS *frag, long where)
2066{
2067 size_t i;
2068
2069 insn->frag = frag;
2070 insn->where = where;
2071 for (i = 0; i < ARRAY_SIZE (insn->fixp); i++)
2072 if (insn->fixp[i] != NULL)
2073 {
2074 insn->fixp[i]->fx_frag = frag;
2075 insn->fixp[i]->fx_where = where;
2076 }
2077 install_insn (insn);
2078}
2079
2080/* Add INSN to the end of the output. */
2081
2082static void
2083add_fixed_insn (struct mips_cl_insn *insn)
2084{
2085 char *f = frag_more (insn_length (insn));
2086 move_insn (insn, frag_now, f - frag_now->fr_literal);
2087}
2088
2089/* Start a variant frag and move INSN to the start of the variant part,
2090 marking it as fixed. The other arguments are as for frag_var. */
2091
2092static void
2093add_relaxed_insn (struct mips_cl_insn *insn, int max_chars, int var,
2094 relax_substateT subtype, symbolS *symbol, offsetT offset)
2095{
2096 frag_grow (max_chars);
2097 move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal);
2098 insn->fixed_p = 1;
2099 frag_var (rs_machine_dependent, max_chars, var,
2100 subtype, symbol, offset, NULL);
2101}
2102
2103/* Insert N copies of INSN into the history buffer, starting at
2104 position FIRST. Neither FIRST nor N need to be clipped. */
2105
2106static void
2107insert_into_history (unsigned int first, unsigned int n,
2108 const struct mips_cl_insn *insn)
2109{
2110 if (mips_relax.sequence != 2)
2111 {
2112 unsigned int i;
2113
2114 for (i = ARRAY_SIZE (history); i-- > first;)
2115 if (i >= first + n)
2116 history[i] = history[i - n];
2117 else
2118 history[i] = *insn;
2119 }
2120}
2121
71400594
RS
2122/* Initialize vr4120_conflicts. There is a bit of duplication here:
2123 the idea is to make it obvious at a glance that each errata is
2124 included. */
2125
2126static void
2127init_vr4120_conflicts (void)
2128{
2129#define CONFLICT(FIRST, SECOND) \
2130 vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND
2131
2132 /* Errata 21 - [D]DIV[U] after [D]MACC */
2133 CONFLICT (MACC, DIV);
2134 CONFLICT (DMACC, DIV);
2135
2136 /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */
2137 CONFLICT (DMULT, DMULT);
2138 CONFLICT (DMULT, DMACC);
2139 CONFLICT (DMACC, DMULT);
2140 CONFLICT (DMACC, DMACC);
2141
2142 /* Errata 24 - MT{LO,HI} after [D]MACC */
2143 CONFLICT (MACC, MTHILO);
2144 CONFLICT (DMACC, MTHILO);
2145
2146 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
2147 instruction is executed immediately after a MACC or DMACC
2148 instruction, the result of [either instruction] is incorrect." */
2149 CONFLICT (MACC, MULT);
2150 CONFLICT (MACC, DMULT);
2151 CONFLICT (DMACC, MULT);
2152 CONFLICT (DMACC, DMULT);
2153
2154 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
2155 executed immediately after a DMULT, DMULTU, DIV, DIVU,
2156 DDIV or DDIVU instruction, the result of the MACC or
2157 DMACC instruction is incorrect.". */
2158 CONFLICT (DMULT, MACC);
2159 CONFLICT (DMULT, DMACC);
2160 CONFLICT (DIV, MACC);
2161 CONFLICT (DIV, DMACC);
2162
2163#undef CONFLICT
2164}
2165
707bfff6
TS
2166struct regname {
2167 const char *name;
2168 unsigned int num;
2169};
2170
2171#define RTYPE_MASK 0x1ff00
2172#define RTYPE_NUM 0x00100
2173#define RTYPE_FPU 0x00200
2174#define RTYPE_FCC 0x00400
2175#define RTYPE_VEC 0x00800
2176#define RTYPE_GP 0x01000
2177#define RTYPE_CP0 0x02000
2178#define RTYPE_PC 0x04000
2179#define RTYPE_ACC 0x08000
2180#define RTYPE_CCC 0x10000
2181#define RNUM_MASK 0x000ff
2182#define RWARN 0x80000
2183
2184#define GENERIC_REGISTER_NUMBERS \
2185 {"$0", RTYPE_NUM | 0}, \
2186 {"$1", RTYPE_NUM | 1}, \
2187 {"$2", RTYPE_NUM | 2}, \
2188 {"$3", RTYPE_NUM | 3}, \
2189 {"$4", RTYPE_NUM | 4}, \
2190 {"$5", RTYPE_NUM | 5}, \
2191 {"$6", RTYPE_NUM | 6}, \
2192 {"$7", RTYPE_NUM | 7}, \
2193 {"$8", RTYPE_NUM | 8}, \
2194 {"$9", RTYPE_NUM | 9}, \
2195 {"$10", RTYPE_NUM | 10}, \
2196 {"$11", RTYPE_NUM | 11}, \
2197 {"$12", RTYPE_NUM | 12}, \
2198 {"$13", RTYPE_NUM | 13}, \
2199 {"$14", RTYPE_NUM | 14}, \
2200 {"$15", RTYPE_NUM | 15}, \
2201 {"$16", RTYPE_NUM | 16}, \
2202 {"$17", RTYPE_NUM | 17}, \
2203 {"$18", RTYPE_NUM | 18}, \
2204 {"$19", RTYPE_NUM | 19}, \
2205 {"$20", RTYPE_NUM | 20}, \
2206 {"$21", RTYPE_NUM | 21}, \
2207 {"$22", RTYPE_NUM | 22}, \
2208 {"$23", RTYPE_NUM | 23}, \
2209 {"$24", RTYPE_NUM | 24}, \
2210 {"$25", RTYPE_NUM | 25}, \
2211 {"$26", RTYPE_NUM | 26}, \
2212 {"$27", RTYPE_NUM | 27}, \
2213 {"$28", RTYPE_NUM | 28}, \
2214 {"$29", RTYPE_NUM | 29}, \
2215 {"$30", RTYPE_NUM | 30}, \
2216 {"$31", RTYPE_NUM | 31}
2217
2218#define FPU_REGISTER_NAMES \
2219 {"$f0", RTYPE_FPU | 0}, \
2220 {"$f1", RTYPE_FPU | 1}, \
2221 {"$f2", RTYPE_FPU | 2}, \
2222 {"$f3", RTYPE_FPU | 3}, \
2223 {"$f4", RTYPE_FPU | 4}, \
2224 {"$f5", RTYPE_FPU | 5}, \
2225 {"$f6", RTYPE_FPU | 6}, \
2226 {"$f7", RTYPE_FPU | 7}, \
2227 {"$f8", RTYPE_FPU | 8}, \
2228 {"$f9", RTYPE_FPU | 9}, \
2229 {"$f10", RTYPE_FPU | 10}, \
2230 {"$f11", RTYPE_FPU | 11}, \
2231 {"$f12", RTYPE_FPU | 12}, \
2232 {"$f13", RTYPE_FPU | 13}, \
2233 {"$f14", RTYPE_FPU | 14}, \
2234 {"$f15", RTYPE_FPU | 15}, \
2235 {"$f16", RTYPE_FPU | 16}, \
2236 {"$f17", RTYPE_FPU | 17}, \
2237 {"$f18", RTYPE_FPU | 18}, \
2238 {"$f19", RTYPE_FPU | 19}, \
2239 {"$f20", RTYPE_FPU | 20}, \
2240 {"$f21", RTYPE_FPU | 21}, \
2241 {"$f22", RTYPE_FPU | 22}, \
2242 {"$f23", RTYPE_FPU | 23}, \
2243 {"$f24", RTYPE_FPU | 24}, \
2244 {"$f25", RTYPE_FPU | 25}, \
2245 {"$f26", RTYPE_FPU | 26}, \
2246 {"$f27", RTYPE_FPU | 27}, \
2247 {"$f28", RTYPE_FPU | 28}, \
2248 {"$f29", RTYPE_FPU | 29}, \
2249 {"$f30", RTYPE_FPU | 30}, \
2250 {"$f31", RTYPE_FPU | 31}
2251
2252#define FPU_CONDITION_CODE_NAMES \
2253 {"$fcc0", RTYPE_FCC | 0}, \
2254 {"$fcc1", RTYPE_FCC | 1}, \
2255 {"$fcc2", RTYPE_FCC | 2}, \
2256 {"$fcc3", RTYPE_FCC | 3}, \
2257 {"$fcc4", RTYPE_FCC | 4}, \
2258 {"$fcc5", RTYPE_FCC | 5}, \
2259 {"$fcc6", RTYPE_FCC | 6}, \
2260 {"$fcc7", RTYPE_FCC | 7}
2261
2262#define COPROC_CONDITION_CODE_NAMES \
2263 {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \
2264 {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \
2265 {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \
2266 {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \
2267 {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \
2268 {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \
2269 {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \
2270 {"$cc7", RTYPE_FCC | RTYPE_CCC | 7}
2271
2272#define N32N64_SYMBOLIC_REGISTER_NAMES \
2273 {"$a4", RTYPE_GP | 8}, \
2274 {"$a5", RTYPE_GP | 9}, \
2275 {"$a6", RTYPE_GP | 10}, \
2276 {"$a7", RTYPE_GP | 11}, \
2277 {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \
2278 {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \
2279 {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \
2280 {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \
2281 {"$t0", RTYPE_GP | 12}, \
2282 {"$t1", RTYPE_GP | 13}, \
2283 {"$t2", RTYPE_GP | 14}, \
2284 {"$t3", RTYPE_GP | 15}
2285
2286#define O32_SYMBOLIC_REGISTER_NAMES \
2287 {"$t0", RTYPE_GP | 8}, \
2288 {"$t1", RTYPE_GP | 9}, \
2289 {"$t2", RTYPE_GP | 10}, \
2290 {"$t3", RTYPE_GP | 11}, \
2291 {"$t4", RTYPE_GP | 12}, \
2292 {"$t5", RTYPE_GP | 13}, \
2293 {"$t6", RTYPE_GP | 14}, \
2294 {"$t7", RTYPE_GP | 15}, \
2295 {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \
2296 {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \
2297 {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \
2298 {"$ta3", RTYPE_GP | 15} /* alias for $t7 */
2299
2300/* Remaining symbolic register names */
2301#define SYMBOLIC_REGISTER_NAMES \
2302 {"$zero", RTYPE_GP | 0}, \
2303 {"$at", RTYPE_GP | 1}, \
2304 {"$AT", RTYPE_GP | 1}, \
2305 {"$v0", RTYPE_GP | 2}, \
2306 {"$v1", RTYPE_GP | 3}, \
2307 {"$a0", RTYPE_GP | 4}, \
2308 {"$a1", RTYPE_GP | 5}, \
2309 {"$a2", RTYPE_GP | 6}, \
2310 {"$a3", RTYPE_GP | 7}, \
2311 {"$s0", RTYPE_GP | 16}, \
2312 {"$s1", RTYPE_GP | 17}, \
2313 {"$s2", RTYPE_GP | 18}, \
2314 {"$s3", RTYPE_GP | 19}, \
2315 {"$s4", RTYPE_GP | 20}, \
2316 {"$s5", RTYPE_GP | 21}, \
2317 {"$s6", RTYPE_GP | 22}, \
2318 {"$s7", RTYPE_GP | 23}, \
2319 {"$t8", RTYPE_GP | 24}, \
2320 {"$t9", RTYPE_GP | 25}, \
2321 {"$k0", RTYPE_GP | 26}, \
2322 {"$kt0", RTYPE_GP | 26}, \
2323 {"$k1", RTYPE_GP | 27}, \
2324 {"$kt1", RTYPE_GP | 27}, \
2325 {"$gp", RTYPE_GP | 28}, \
2326 {"$sp", RTYPE_GP | 29}, \
2327 {"$s8", RTYPE_GP | 30}, \
2328 {"$fp", RTYPE_GP | 30}, \
2329 {"$ra", RTYPE_GP | 31}
2330
2331#define MIPS16_SPECIAL_REGISTER_NAMES \
2332 {"$pc", RTYPE_PC | 0}
2333
2334#define MDMX_VECTOR_REGISTER_NAMES \
2335 /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \
2336 /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \
2337 {"$v2", RTYPE_VEC | 2}, \
2338 {"$v3", RTYPE_VEC | 3}, \
2339 {"$v4", RTYPE_VEC | 4}, \
2340 {"$v5", RTYPE_VEC | 5}, \
2341 {"$v6", RTYPE_VEC | 6}, \
2342 {"$v7", RTYPE_VEC | 7}, \
2343 {"$v8", RTYPE_VEC | 8}, \
2344 {"$v9", RTYPE_VEC | 9}, \
2345 {"$v10", RTYPE_VEC | 10}, \
2346 {"$v11", RTYPE_VEC | 11}, \
2347 {"$v12", RTYPE_VEC | 12}, \
2348 {"$v13", RTYPE_VEC | 13}, \
2349 {"$v14", RTYPE_VEC | 14}, \
2350 {"$v15", RTYPE_VEC | 15}, \
2351 {"$v16", RTYPE_VEC | 16}, \
2352 {"$v17", RTYPE_VEC | 17}, \
2353 {"$v18", RTYPE_VEC | 18}, \
2354 {"$v19", RTYPE_VEC | 19}, \
2355 {"$v20", RTYPE_VEC | 20}, \
2356 {"$v21", RTYPE_VEC | 21}, \
2357 {"$v22", RTYPE_VEC | 22}, \
2358 {"$v23", RTYPE_VEC | 23}, \
2359 {"$v24", RTYPE_VEC | 24}, \
2360 {"$v25", RTYPE_VEC | 25}, \
2361 {"$v26", RTYPE_VEC | 26}, \
2362 {"$v27", RTYPE_VEC | 27}, \
2363 {"$v28", RTYPE_VEC | 28}, \
2364 {"$v29", RTYPE_VEC | 29}, \
2365 {"$v30", RTYPE_VEC | 30}, \
2366 {"$v31", RTYPE_VEC | 31}
2367
2368#define MIPS_DSP_ACCUMULATOR_NAMES \
2369 {"$ac0", RTYPE_ACC | 0}, \
2370 {"$ac1", RTYPE_ACC | 1}, \
2371 {"$ac2", RTYPE_ACC | 2}, \
2372 {"$ac3", RTYPE_ACC | 3}
2373
2374static const struct regname reg_names[] = {
2375 GENERIC_REGISTER_NUMBERS,
2376 FPU_REGISTER_NAMES,
2377 FPU_CONDITION_CODE_NAMES,
2378 COPROC_CONDITION_CODE_NAMES,
2379
2380 /* The $txx registers depends on the abi,
2381 these will be added later into the symbol table from
2382 one of the tables below once mips_abi is set after
2383 parsing of arguments from the command line. */
2384 SYMBOLIC_REGISTER_NAMES,
2385
2386 MIPS16_SPECIAL_REGISTER_NAMES,
2387 MDMX_VECTOR_REGISTER_NAMES,
2388 MIPS_DSP_ACCUMULATOR_NAMES,
2389 {0, 0}
2390};
2391
2392static const struct regname reg_names_o32[] = {
2393 O32_SYMBOLIC_REGISTER_NAMES,
2394 {0, 0}
2395};
2396
2397static const struct regname reg_names_n32n64[] = {
2398 N32N64_SYMBOLIC_REGISTER_NAMES,
2399 {0, 0}
2400};
2401
a92713e6
RS
2402/* Register symbols $v0 and $v1 map to GPRs 2 and 3, but they can also be
2403 interpreted as vector registers 0 and 1. If SYMVAL is the value of one
2404 of these register symbols, return the associated vector register,
2405 otherwise return SYMVAL itself. */
df58fc94 2406
a92713e6
RS
2407static unsigned int
2408mips_prefer_vec_regno (unsigned int symval)
707bfff6 2409{
a92713e6
RS
2410 if ((symval & -2) == (RTYPE_GP | 2))
2411 return RTYPE_VEC | (symval & 1);
2412 return symval;
2413}
2414
2415/* Return true if the string at *SPTR is a valid register name. If so,
2416 move *SPTR past the register and store the register's symbol value
2417 in *SYMVAL. This symbol value includes the register number
2418 (RNUM_MASK) and register type (RTYPE_MASK). */
2419
2420static bfd_boolean
2421mips_parse_register (char **sptr, unsigned int *symval)
2422{
2423 symbolS *symbol;
2424 char *s, *e;
707bfff6 2425 char save_c;
707bfff6
TS
2426
2427 /* Find end of name. */
a92713e6 2428 s = e = *sptr;
707bfff6
TS
2429 if (is_name_beginner (*e))
2430 ++e;
2431 while (is_part_of_name (*e))
2432 ++e;
2433
2434 /* Terminate name. */
2435 save_c = *e;
2436 *e = '\0';
2437
a92713e6
RS
2438 /* Look up the name. */
2439 symbol = symbol_find (s);
2440 *e = save_c;
2441
2442 if (!symbol || S_GET_SEGMENT (symbol) != reg_section)
2443 return FALSE;
2444
2445 *sptr = e;
2446 *symval = S_GET_VALUE (symbol);
2447 return TRUE;
2448}
2449
2450/* Check if SPTR points at a valid register specifier according to TYPES.
2451 If so, then return 1, advance S to consume the specifier and store
2452 the register's number in REGNOP, otherwise return 0. */
2453
2454static int
2455reg_lookup (char **s, unsigned int types, unsigned int *regnop)
2456{
2457 unsigned int regno;
2458
2459 if (mips_parse_register (s, &regno))
707bfff6 2460 {
a92713e6
RS
2461 if (types & RTYPE_VEC)
2462 regno = mips_prefer_vec_regno (regno);
2463 if (regno & types)
2464 regno &= RNUM_MASK;
2465 else
2466 regno = ~0;
707bfff6 2467 }
a92713e6 2468 else
707bfff6 2469 {
a92713e6
RS
2470 if (types & RWARN)
2471 as_warn (_("Unrecognized register name `%s'"), *s);
2472 regno = ~0;
707bfff6 2473 }
707bfff6 2474 if (regnop)
a92713e6
RS
2475 *regnop = regno;
2476 return regno <= RNUM_MASK;
707bfff6
TS
2477}
2478
a92713e6
RS
2479/* Token types for parsed operand lists. */
2480enum mips_operand_token_type {
2481 /* A plain register, e.g. $f2. */
2482 OT_REG,
df58fc94 2483
a92713e6
RS
2484 /* An element of a vector, e.g. $v0[1]. */
2485 OT_REG_ELEMENT,
df58fc94 2486
a92713e6
RS
2487 /* A continuous range of registers, e.g. $s0-$s4. */
2488 OT_REG_RANGE,
2489
2490 /* A (possibly relocated) expression. */
2491 OT_INTEGER,
2492
2493 /* A floating-point value. */
2494 OT_FLOAT,
2495
2496 /* A single character. This can be '(', ')' or ',', but '(' only appears
2497 before OT_REGs. */
2498 OT_CHAR,
2499
2500 /* The end of the operand list. */
2501 OT_END
2502};
2503
2504/* A parsed operand token. */
2505struct mips_operand_token
2506{
2507 /* The type of token. */
2508 enum mips_operand_token_type type;
2509 union
2510 {
2511 /* The register symbol value for an OT_REG. */
2512 unsigned int regno;
2513
2514 /* The register symbol value and index for an OT_REG_ELEMENT. */
2515 struct {
2516 unsigned int regno;
2517 addressT index;
2518 } reg_element;
2519
2520 /* The two register symbol values involved in an OT_REG_RANGE. */
2521 struct {
2522 unsigned int regno1;
2523 unsigned int regno2;
2524 } reg_range;
2525
2526 /* The value of an OT_INTEGER. The value is represented as an
2527 expression and the relocation operators that were applied to
2528 that expression. The reloc entries are BFD_RELOC_UNUSED if no
2529 relocation operators were used. */
2530 struct {
2531 expressionS value;
2532 bfd_reloc_code_real_type relocs[3];
2533 } integer;
2534
2535 /* The binary data for an OT_FLOAT constant, and the number of bytes
2536 in the constant. */
2537 struct {
2538 unsigned char data[8];
2539 int length;
2540 } flt;
2541
2542 /* The character represented by an OT_CHAR. */
2543 char ch;
2544 } u;
2545};
2546
2547/* An obstack used to construct lists of mips_operand_tokens. */
2548static struct obstack mips_operand_tokens;
2549
2550/* Give TOKEN type TYPE and add it to mips_operand_tokens. */
2551
2552static void
2553mips_add_token (struct mips_operand_token *token,
2554 enum mips_operand_token_type type)
2555{
2556 token->type = type;
2557 obstack_grow (&mips_operand_tokens, token, sizeof (*token));
2558}
2559
2560/* Check whether S is '(' followed by a register name. Add OT_CHAR
2561 and OT_REG tokens for them if so, and return a pointer to the first
2562 unconsumed character. Return null otherwise. */
2563
2564static char *
2565mips_parse_base_start (char *s)
2566{
2567 struct mips_operand_token token;
2309ddf2 2568 unsigned int regno;
df58fc94 2569
a92713e6
RS
2570 if (*s != '(')
2571 return 0;
2572
2573 ++s;
2574 SKIP_SPACE_TABS (s);
2575 if (!mips_parse_register (&s, &regno))
2576 return 0;
2577
2578 token.u.ch = '(';
2579 mips_add_token (&token, OT_CHAR);
2580
2581 token.u.regno = regno;
2582 mips_add_token (&token, OT_REG);
2583
2584 return s;
2585}
2586
2587/* Parse one or more tokens from S. Return a pointer to the first
2588 unconsumed character on success. Return null if an error was found
2589 and store the error text in insn_error. FLOAT_FORMAT is as for
2590 mips_parse_arguments. */
2591
2592static char *
2593mips_parse_argument_token (char *s, char float_format)
2594{
2595 char *end, *save_in, *err;
2596 unsigned int regno1, regno2;
2597 struct mips_operand_token token;
2598
2599 /* First look for "($reg", since we want to treat that as an
2600 OT_CHAR and OT_REG rather than an expression. */
2601 end = mips_parse_base_start (s);
2602 if (end)
2603 return end;
2604
2605 /* Handle other characters that end up as OT_CHARs. */
2606 if (*s == ')' || *s == ',')
2607 {
2608 token.u.ch = *s;
2609 mips_add_token (&token, OT_CHAR);
2610 ++s;
2611 return s;
2612 }
2613
2614 /* Handle tokens that start with a register. */
2615 if (mips_parse_register (&s, &regno1))
df58fc94 2616 {
a92713e6
RS
2617 SKIP_SPACE_TABS (s);
2618 if (*s == '-')
df58fc94 2619 {
a92713e6
RS
2620 /* A register range. */
2621 ++s;
2622 SKIP_SPACE_TABS (s);
2623 if (!mips_parse_register (&s, &regno2))
2624 {
2625 insn_error = _("Invalid register range");
2626 return 0;
2627 }
df58fc94 2628
a92713e6
RS
2629 token.u.reg_range.regno1 = regno1;
2630 token.u.reg_range.regno2 = regno2;
2631 mips_add_token (&token, OT_REG_RANGE);
2632 return s;
2633 }
2634 else if (*s == '[')
df58fc94 2635 {
a92713e6
RS
2636 /* A vector element. */
2637 expressionS element;
2638
2639 ++s;
2640 SKIP_SPACE_TABS (s);
2641 my_getExpression (&element, s);
2642 if (element.X_op != O_constant)
2643 {
2644 insn_error = _("Vector element must be constant");
2645 return 0;
2646 }
2647 s = expr_end;
2648 SKIP_SPACE_TABS (s);
2649 if (*s != ']')
2650 {
2651 insn_error = _("Missing `]'");
2652 return 0;
2653 }
2654 ++s;
2655
2656 token.u.reg_element.regno = regno1;
2657 token.u.reg_element.index = element.X_add_number;
2658 mips_add_token (&token, OT_REG_ELEMENT);
2659 return s;
df58fc94 2660 }
df58fc94 2661
a92713e6
RS
2662 /* Looks like just a plain register. */
2663 token.u.regno = regno1;
2664 mips_add_token (&token, OT_REG);
2665 return s;
df58fc94
RS
2666 }
2667
a92713e6
RS
2668 if (float_format)
2669 {
2670 /* First try to treat expressions as floats. */
2671 save_in = input_line_pointer;
2672 input_line_pointer = s;
2673 err = md_atof (float_format, (char *) token.u.flt.data,
2674 &token.u.flt.length);
2675 end = input_line_pointer;
2676 input_line_pointer = save_in;
2677 if (err && *err)
2678 {
2679 insn_error = err;
2680 return 0;
2681 }
2682 if (s != end)
2683 {
2684 mips_add_token (&token, OT_FLOAT);
2685 return end;
2686 }
2687 }
2688
2689 /* Treat everything else as an integer expression. */
2690 token.u.integer.relocs[0] = BFD_RELOC_UNUSED;
2691 token.u.integer.relocs[1] = BFD_RELOC_UNUSED;
2692 token.u.integer.relocs[2] = BFD_RELOC_UNUSED;
2693 my_getSmallExpression (&token.u.integer.value, token.u.integer.relocs, s);
2694 s = expr_end;
2695 mips_add_token (&token, OT_INTEGER);
2696 return s;
2697}
2698
2699/* S points to the operand list for an instruction. FLOAT_FORMAT is 'f'
2700 if expressions should be treated as 32-bit floating-point constants,
2701 'd' if they should be treated as 64-bit floating-point constants,
2702 or 0 if they should be treated as integer expressions (the usual case).
2703
2704 Return a list of tokens on success, otherwise return 0. The caller
2705 must obstack_free the list after use. */
2706
2707static struct mips_operand_token *
2708mips_parse_arguments (char *s, char float_format)
2709{
2710 struct mips_operand_token token;
2711
2712 SKIP_SPACE_TABS (s);
2713 while (*s)
2714 {
2715 s = mips_parse_argument_token (s, float_format);
2716 if (!s)
2717 {
2718 obstack_free (&mips_operand_tokens,
2719 obstack_finish (&mips_operand_tokens));
2720 return 0;
2721 }
2722 SKIP_SPACE_TABS (s);
2723 }
2724 mips_add_token (&token, OT_END);
2725 return (struct mips_operand_token *) obstack_finish (&mips_operand_tokens);
df58fc94
RS
2726}
2727
d301a56b
RS
2728/* Return TRUE if opcode MO is valid on the currently selected ISA, ASE
2729 and architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */
037b32b9
AN
2730
2731static bfd_boolean
f79e2745 2732is_opcode_valid (const struct mips_opcode *mo)
037b32b9
AN
2733{
2734 int isa = mips_opts.isa;
846ef2d0 2735 int ase = mips_opts.ase;
037b32b9 2736 int fp_s, fp_d;
c6278170 2737 unsigned int i;
037b32b9 2738
c6278170
RS
2739 if (ISA_HAS_64BIT_REGS (mips_opts.isa))
2740 for (i = 0; i < ARRAY_SIZE (mips_ases); i++)
2741 if ((ase & mips_ases[i].flags) == mips_ases[i].flags)
2742 ase |= mips_ases[i].flags64;
037b32b9 2743
d301a56b 2744 if (!opcode_is_member (mo, isa, ase, mips_opts.arch))
037b32b9
AN
2745 return FALSE;
2746
2747 /* Check whether the instruction or macro requires single-precision or
2748 double-precision floating-point support. Note that this information is
2749 stored differently in the opcode table for insns and macros. */
2750 if (mo->pinfo == INSN_MACRO)
2751 {
2752 fp_s = mo->pinfo2 & INSN2_M_FP_S;
2753 fp_d = mo->pinfo2 & INSN2_M_FP_D;
2754 }
2755 else
2756 {
2757 fp_s = mo->pinfo & FP_S;
2758 fp_d = mo->pinfo & FP_D;
2759 }
2760
2761 if (fp_d && (mips_opts.soft_float || mips_opts.single_float))
2762 return FALSE;
2763
2764 if (fp_s && mips_opts.soft_float)
2765 return FALSE;
2766
2767 return TRUE;
2768}
2769
2770/* Return TRUE if the MIPS16 opcode MO is valid on the currently
2771 selected ISA and architecture. */
2772
2773static bfd_boolean
2774is_opcode_valid_16 (const struct mips_opcode *mo)
2775{
d301a56b 2776 return opcode_is_member (mo, mips_opts.isa, 0, mips_opts.arch);
037b32b9
AN
2777}
2778
df58fc94
RS
2779/* Return TRUE if the size of the microMIPS opcode MO matches one
2780 explicitly requested. Always TRUE in the standard MIPS mode. */
2781
2782static bfd_boolean
2783is_size_valid (const struct mips_opcode *mo)
2784{
2785 if (!mips_opts.micromips)
2786 return TRUE;
2787
833794fc
MR
2788 if (mips_opts.insn32)
2789 {
2790 if (mo->pinfo != INSN_MACRO && micromips_insn_length (mo) != 4)
2791 return FALSE;
2792 if ((mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0)
2793 return FALSE;
2794 }
df58fc94
RS
2795 if (!forced_insn_length)
2796 return TRUE;
2797 if (mo->pinfo == INSN_MACRO)
2798 return FALSE;
2799 return forced_insn_length == micromips_insn_length (mo);
2800}
2801
2802/* Return TRUE if the microMIPS opcode MO is valid for the delay slot
e64af278
MR
2803 of the preceding instruction. Always TRUE in the standard MIPS mode.
2804
2805 We don't accept macros in 16-bit delay slots to avoid a case where
2806 a macro expansion fails because it relies on a preceding 32-bit real
2807 instruction to have matched and does not handle the operands correctly.
2808 The only macros that may expand to 16-bit instructions are JAL that
2809 cannot be placed in a delay slot anyway, and corner cases of BALIGN
2810 and BGT (that likewise cannot be placed in a delay slot) that decay to
2811 a NOP. In all these cases the macros precede any corresponding real
2812 instruction definitions in the opcode table, so they will match in the
2813 second pass where the size of the delay slot is ignored and therefore
2814 produce correct code. */
df58fc94
RS
2815
2816static bfd_boolean
2817is_delay_slot_valid (const struct mips_opcode *mo)
2818{
2819 if (!mips_opts.micromips)
2820 return TRUE;
2821
2822 if (mo->pinfo == INSN_MACRO)
c06dec14 2823 return (history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) == 0;
df58fc94
RS
2824 if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0
2825 && micromips_insn_length (mo) != 4)
2826 return FALSE;
2827 if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0
2828 && micromips_insn_length (mo) != 2)
2829 return FALSE;
2830
2831 return TRUE;
2832}
2833
ab902481
RS
2834/* For consistency checking, verify that all bits of OPCODE are
2835 specified either by the match/mask part of the instruction
2836 definition, or by the operand list. INSN_BITS says which
2837 bits of the instruction are significant and DECODE_OPERAND
2838 provides the mips_operand description of each operand. */
2839
2840static int
2841validate_mips_insn (const struct mips_opcode *opcode,
2842 unsigned long insn_bits,
2843 const struct mips_operand *(*decode_operand) (const char *))
2844{
2845 const char *s;
2846 unsigned long used_bits, doubled, undefined;
2847 const struct mips_operand *operand;
2848
2849 if ((opcode->mask & opcode->match) != opcode->match)
2850 {
2851 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
2852 opcode->name, opcode->args);
2853 return 0;
2854 }
2855 used_bits = 0;
2856 for (s = opcode->args; *s; ++s)
2857 switch (*s)
2858 {
2859 case ',':
2860 case '(':
2861 case ')':
2862 break;
2863
2864 default:
2865 operand = decode_operand (s);
2866 if (!operand)
2867 {
2868 as_bad (_("internal: unknown operand type: %s %s"),
2869 opcode->name, opcode->args);
2870 return 0;
2871 }
2872 used_bits |= ((1 << operand->size) - 1) << operand->lsb;
2873 if (operand->type == OP_MDMX_IMM_REG)
2874 /* Bit 5 is the format selector (OB vs QH). The opcode table
2875 has separate entries for each format. */
2876 used_bits &= ~(1 << (operand->lsb + 5));
2877 /* Skip prefix characters. */
2878 if (*s == '+' || *s == 'm')
2879 ++s;
2880 break;
2881 }
2882 doubled = used_bits & opcode->mask & insn_bits;
2883 if (doubled)
2884 {
2885 as_bad (_("internal: bad mips opcode (bits 0x%08lx doubly defined):"
2886 " %s %s"), doubled, opcode->name, opcode->args);
2887 return 0;
2888 }
2889 used_bits |= opcode->mask;
2890 undefined = ~used_bits & insn_bits;
2891 if (undefined)
2892 {
2893 as_bad (_("internal: bad mips opcode (bits 0x%08lx undefined): %s %s"),
2894 undefined, opcode->name, opcode->args);
2895 return 0;
2896 }
2897 used_bits &= ~insn_bits;
2898 if (used_bits)
2899 {
2900 as_bad (_("internal: bad mips opcode (bits 0x%08lx defined): %s %s"),
2901 used_bits, opcode->name, opcode->args);
2902 return 0;
2903 }
2904 return 1;
2905}
2906
2907/* The microMIPS version of validate_mips_insn. */
2908
2909static int
2910validate_micromips_insn (const struct mips_opcode *opc)
2911{
2912 unsigned long insn_bits;
2913 unsigned long major;
2914 unsigned int length;
2915
2916 length = micromips_insn_length (opc);
2917 if (length != 2 && length != 4)
2918 {
2919 as_bad (_("Internal error: bad microMIPS opcode (incorrect length: %u): "
2920 "%s %s"), length, opc->name, opc->args);
2921 return 0;
2922 }
2923 major = opc->match >> (10 + 8 * (length - 2));
2924 if ((length == 2 && (major & 7) != 1 && (major & 6) != 2)
2925 || (length == 4 && (major & 7) != 0 && (major & 4) != 4))
2926 {
2927 as_bad (_("Internal error: bad microMIPS opcode "
2928 "(opcode/length mismatch): %s %s"), opc->name, opc->args);
2929 return 0;
2930 }
2931
2932 /* Shift piecewise to avoid an overflow where unsigned long is 32-bit. */
2933 insn_bits = 1 << 4 * length;
2934 insn_bits <<= 4 * length;
2935 insn_bits -= 1;
2936 return validate_mips_insn (opc, insn_bits, decode_micromips_operand);
2937}
2938
707bfff6
TS
2939/* This function is called once, at assembler startup time. It should set up
2940 all the tables, etc. that the MD part of the assembler will need. */
156c2f8b 2941
252b5132 2942void
17a2f251 2943md_begin (void)
252b5132 2944{
3994f87e 2945 const char *retval = NULL;
156c2f8b 2946 int i = 0;
252b5132 2947 int broken = 0;
1f25f5d3 2948
0a44bf69
RS
2949 if (mips_pic != NO_PIC)
2950 {
2951 if (g_switch_seen && g_switch_value != 0)
2952 as_bad (_("-G may not be used in position-independent code"));
2953 g_switch_value = 0;
2954 }
2955
fef14a42 2956 if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_arch))
252b5132
RH
2957 as_warn (_("Could not set architecture and machine"));
2958
252b5132
RH
2959 op_hash = hash_new ();
2960
2961 for (i = 0; i < NUMOPCODES;)
2962 {
2963 const char *name = mips_opcodes[i].name;
2964
17a2f251 2965 retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]);
252b5132
RH
2966 if (retval != NULL)
2967 {
2968 fprintf (stderr, _("internal error: can't hash `%s': %s\n"),
2969 mips_opcodes[i].name, retval);
2970 /* Probably a memory allocation problem? Give up now. */
2971 as_fatal (_("Broken assembler. No assembly attempted."));
2972 }
2973 do
2974 {
2975 if (mips_opcodes[i].pinfo != INSN_MACRO)
2976 {
ab902481
RS
2977 if (!validate_mips_insn (&mips_opcodes[i], 0xffffffff,
2978 decode_mips_operand))
252b5132 2979 broken = 1;
1e915849
RS
2980 if (nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0)
2981 {
2982 create_insn (&nop_insn, mips_opcodes + i);
c67a084a
NC
2983 if (mips_fix_loongson2f_nop)
2984 nop_insn.insn_opcode = LOONGSON2F_NOP_INSN;
1e915849
RS
2985 nop_insn.fixed_p = 1;
2986 }
252b5132
RH
2987 }
2988 ++i;
2989 }
2990 while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name));
2991 }
2992
2993 mips16_op_hash = hash_new ();
2994
2995 i = 0;
2996 while (i < bfd_mips16_num_opcodes)
2997 {
2998 const char *name = mips16_opcodes[i].name;
2999
17a2f251 3000 retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]);
252b5132
RH
3001 if (retval != NULL)
3002 as_fatal (_("internal: can't hash `%s': %s"),
3003 mips16_opcodes[i].name, retval);
3004 do
3005 {
3006 if (mips16_opcodes[i].pinfo != INSN_MACRO
3007 && ((mips16_opcodes[i].match & mips16_opcodes[i].mask)
3008 != mips16_opcodes[i].match))
3009 {
3010 fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"),
3011 mips16_opcodes[i].name, mips16_opcodes[i].args);
3012 broken = 1;
3013 }
1e915849
RS
3014 if (mips16_nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0)
3015 {
3016 create_insn (&mips16_nop_insn, mips16_opcodes + i);
3017 mips16_nop_insn.fixed_p = 1;
3018 }
252b5132
RH
3019 ++i;
3020 }
3021 while (i < bfd_mips16_num_opcodes
3022 && strcmp (mips16_opcodes[i].name, name) == 0);
3023 }
3024
df58fc94
RS
3025 micromips_op_hash = hash_new ();
3026
3027 i = 0;
3028 while (i < bfd_micromips_num_opcodes)
3029 {
3030 const char *name = micromips_opcodes[i].name;
3031
3032 retval = hash_insert (micromips_op_hash, name,
3033 (void *) &micromips_opcodes[i]);
3034 if (retval != NULL)
3035 as_fatal (_("internal: can't hash `%s': %s"),
3036 micromips_opcodes[i].name, retval);
3037 do
3038 if (micromips_opcodes[i].pinfo != INSN_MACRO)
3039 {
3040 struct mips_cl_insn *micromips_nop_insn;
3041
3042 if (!validate_micromips_insn (&micromips_opcodes[i]))
3043 broken = 1;
3044
3045 if (micromips_insn_length (micromips_opcodes + i) == 2)
3046 micromips_nop_insn = &micromips_nop16_insn;
3047 else if (micromips_insn_length (micromips_opcodes + i) == 4)
3048 micromips_nop_insn = &micromips_nop32_insn;
3049 else
3050 continue;
3051
3052 if (micromips_nop_insn->insn_mo == NULL
3053 && strcmp (name, "nop") == 0)
3054 {
3055 create_insn (micromips_nop_insn, micromips_opcodes + i);
3056 micromips_nop_insn->fixed_p = 1;
3057 }
3058 }
3059 while (++i < bfd_micromips_num_opcodes
3060 && strcmp (micromips_opcodes[i].name, name) == 0);
3061 }
3062
252b5132
RH
3063 if (broken)
3064 as_fatal (_("Broken assembler. No assembly attempted."));
3065
3066 /* We add all the general register names to the symbol table. This
3067 helps us detect invalid uses of them. */
707bfff6
TS
3068 for (i = 0; reg_names[i].name; i++)
3069 symbol_table_insert (symbol_new (reg_names[i].name, reg_section,
8fc4ee9b 3070 reg_names[i].num, /* & RNUM_MASK, */
707bfff6
TS
3071 &zero_address_frag));
3072 if (HAVE_NEWABI)
3073 for (i = 0; reg_names_n32n64[i].name; i++)
3074 symbol_table_insert (symbol_new (reg_names_n32n64[i].name, reg_section,
8fc4ee9b 3075 reg_names_n32n64[i].num, /* & RNUM_MASK, */
252b5132 3076 &zero_address_frag));
707bfff6
TS
3077 else
3078 for (i = 0; reg_names_o32[i].name; i++)
3079 symbol_table_insert (symbol_new (reg_names_o32[i].name, reg_section,
8fc4ee9b 3080 reg_names_o32[i].num, /* & RNUM_MASK, */
6047c971 3081 &zero_address_frag));
6047c971 3082
a92713e6
RS
3083 obstack_init (&mips_operand_tokens);
3084
7d10b47d 3085 mips_no_prev_insn ();
252b5132
RH
3086
3087 mips_gprmask = 0;
3088 mips_cprmask[0] = 0;
3089 mips_cprmask[1] = 0;
3090 mips_cprmask[2] = 0;
3091 mips_cprmask[3] = 0;
3092
3093 /* set the default alignment for the text section (2**2) */
3094 record_alignment (text_section, 2);
3095
4d0d148d 3096 bfd_set_gp_size (stdoutput, g_switch_value);
252b5132 3097
f3ded42a
RS
3098 /* On a native system other than VxWorks, sections must be aligned
3099 to 16 byte boundaries. When configured for an embedded ELF
3100 target, we don't bother. */
3101 if (strncmp (TARGET_OS, "elf", 3) != 0
3102 && strncmp (TARGET_OS, "vxworks", 7) != 0)
252b5132 3103 {
f3ded42a
RS
3104 (void) bfd_set_section_alignment (stdoutput, text_section, 4);
3105 (void) bfd_set_section_alignment (stdoutput, data_section, 4);
3106 (void) bfd_set_section_alignment (stdoutput, bss_section, 4);
3107 }
252b5132 3108
f3ded42a
RS
3109 /* Create a .reginfo section for register masks and a .mdebug
3110 section for debugging information. */
3111 {
3112 segT seg;
3113 subsegT subseg;
3114 flagword flags;
3115 segT sec;
3116
3117 seg = now_seg;
3118 subseg = now_subseg;
3119
3120 /* The ABI says this section should be loaded so that the
3121 running program can access it. However, we don't load it
3122 if we are configured for an embedded target */
3123 flags = SEC_READONLY | SEC_DATA;
3124 if (strncmp (TARGET_OS, "elf", 3) != 0)
3125 flags |= SEC_ALLOC | SEC_LOAD;
3126
3127 if (mips_abi != N64_ABI)
252b5132 3128 {
f3ded42a 3129 sec = subseg_new (".reginfo", (subsegT) 0);
bdaaa2e1 3130
f3ded42a
RS
3131 bfd_set_section_flags (stdoutput, sec, flags);
3132 bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2);
252b5132 3133
f3ded42a
RS
3134 mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo));
3135 }
3136 else
3137 {
3138 /* The 64-bit ABI uses a .MIPS.options section rather than
3139 .reginfo section. */
3140 sec = subseg_new (".MIPS.options", (subsegT) 0);
3141 bfd_set_section_flags (stdoutput, sec, flags);
3142 bfd_set_section_alignment (stdoutput, sec, 3);
252b5132 3143
f3ded42a
RS
3144 /* Set up the option header. */
3145 {
3146 Elf_Internal_Options opthdr;
3147 char *f;
3148
3149 opthdr.kind = ODK_REGINFO;
3150 opthdr.size = (sizeof (Elf_External_Options)
3151 + sizeof (Elf64_External_RegInfo));
3152 opthdr.section = 0;
3153 opthdr.info = 0;
3154 f = frag_more (sizeof (Elf_External_Options));
3155 bfd_mips_elf_swap_options_out (stdoutput, &opthdr,
3156 (Elf_External_Options *) f);
3157
3158 mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo));
3159 }
3160 }
252b5132 3161
f3ded42a
RS
3162 if (ECOFF_DEBUGGING)
3163 {
3164 sec = subseg_new (".mdebug", (subsegT) 0);
3165 (void) bfd_set_section_flags (stdoutput, sec,
3166 SEC_HAS_CONTENTS | SEC_READONLY);
3167 (void) bfd_set_section_alignment (stdoutput, sec, 2);
252b5132 3168 }
f3ded42a
RS
3169 else if (mips_flag_pdr)
3170 {
3171 pdr_seg = subseg_new (".pdr", (subsegT) 0);
3172 (void) bfd_set_section_flags (stdoutput, pdr_seg,
3173 SEC_READONLY | SEC_RELOC
3174 | SEC_DEBUGGING);
3175 (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2);
3176 }
3177
3178 subseg_set (seg, subseg);
3179 }
252b5132
RH
3180
3181 if (! ECOFF_DEBUGGING)
3182 md_obj_begin ();
71400594
RS
3183
3184 if (mips_fix_vr4120)
3185 init_vr4120_conflicts ();
252b5132
RH
3186}
3187
3188void
17a2f251 3189md_mips_end (void)
252b5132 3190{
02b1ab82 3191 mips_emit_delays ();
252b5132
RH
3192 if (! ECOFF_DEBUGGING)
3193 md_obj_end ();
3194}
3195
3196void
17a2f251 3197md_assemble (char *str)
252b5132
RH
3198{
3199 struct mips_cl_insn insn;
f6688943
TS
3200 bfd_reloc_code_real_type unused_reloc[3]
3201 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
252b5132
RH
3202
3203 imm_expr.X_op = O_absent;
5f74bc13 3204 imm2_expr.X_op = O_absent;
252b5132 3205 offset_expr.X_op = O_absent;
f6688943
TS
3206 offset_reloc[0] = BFD_RELOC_UNUSED;
3207 offset_reloc[1] = BFD_RELOC_UNUSED;
3208 offset_reloc[2] = BFD_RELOC_UNUSED;
252b5132 3209
e1b47bd5
RS
3210 mips_mark_labels ();
3211 mips_assembling_insn = TRUE;
3212
252b5132
RH
3213 if (mips_opts.mips16)
3214 mips16_ip (str, &insn);
3215 else
3216 {
3217 mips_ip (str, &insn);
beae10d5
KH
3218 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
3219 str, insn.insn_opcode));
252b5132
RH
3220 }
3221
3222 if (insn_error)
e1b47bd5
RS
3223 as_bad ("%s `%s'", insn_error, str);
3224 else if (insn.insn_mo->pinfo == INSN_MACRO)
252b5132 3225 {
584892a6 3226 macro_start ();
252b5132
RH
3227 if (mips_opts.mips16)
3228 mips16_macro (&insn);
3229 else
833794fc 3230 macro (&insn, str);
584892a6 3231 macro_end ();
252b5132
RH
3232 }
3233 else
3234 {
77bd4346 3235 if (offset_expr.X_op != O_absent)
df58fc94 3236 append_insn (&insn, &offset_expr, offset_reloc, FALSE);
252b5132 3237 else
df58fc94 3238 append_insn (&insn, NULL, unused_reloc, FALSE);
252b5132 3239 }
e1b47bd5
RS
3240
3241 mips_assembling_insn = FALSE;
252b5132
RH
3242}
3243
738e5348
RS
3244/* Convenience functions for abstracting away the differences between
3245 MIPS16 and non-MIPS16 relocations. */
3246
3247static inline bfd_boolean
3248mips16_reloc_p (bfd_reloc_code_real_type reloc)
3249{
3250 switch (reloc)
3251 {
3252 case BFD_RELOC_MIPS16_JMP:
3253 case BFD_RELOC_MIPS16_GPREL:
3254 case BFD_RELOC_MIPS16_GOT16:
3255 case BFD_RELOC_MIPS16_CALL16:
3256 case BFD_RELOC_MIPS16_HI16_S:
3257 case BFD_RELOC_MIPS16_HI16:
3258 case BFD_RELOC_MIPS16_LO16:
3259 return TRUE;
3260
3261 default:
3262 return FALSE;
3263 }
3264}
3265
df58fc94
RS
3266static inline bfd_boolean
3267micromips_reloc_p (bfd_reloc_code_real_type reloc)
3268{
3269 switch (reloc)
3270 {
3271 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
3272 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
3273 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
3274 case BFD_RELOC_MICROMIPS_GPREL16:
3275 case BFD_RELOC_MICROMIPS_JMP:
3276 case BFD_RELOC_MICROMIPS_HI16:
3277 case BFD_RELOC_MICROMIPS_HI16_S:
3278 case BFD_RELOC_MICROMIPS_LO16:
3279 case BFD_RELOC_MICROMIPS_LITERAL:
3280 case BFD_RELOC_MICROMIPS_GOT16:
3281 case BFD_RELOC_MICROMIPS_CALL16:
3282 case BFD_RELOC_MICROMIPS_GOT_HI16:
3283 case BFD_RELOC_MICROMIPS_GOT_LO16:
3284 case BFD_RELOC_MICROMIPS_CALL_HI16:
3285 case BFD_RELOC_MICROMIPS_CALL_LO16:
3286 case BFD_RELOC_MICROMIPS_SUB:
3287 case BFD_RELOC_MICROMIPS_GOT_PAGE:
3288 case BFD_RELOC_MICROMIPS_GOT_OFST:
3289 case BFD_RELOC_MICROMIPS_GOT_DISP:
3290 case BFD_RELOC_MICROMIPS_HIGHEST:
3291 case BFD_RELOC_MICROMIPS_HIGHER:
3292 case BFD_RELOC_MICROMIPS_SCN_DISP:
3293 case BFD_RELOC_MICROMIPS_JALR:
3294 return TRUE;
3295
3296 default:
3297 return FALSE;
3298 }
3299}
3300
2309ddf2
MR
3301static inline bfd_boolean
3302jmp_reloc_p (bfd_reloc_code_real_type reloc)
3303{
3304 return reloc == BFD_RELOC_MIPS_JMP || reloc == BFD_RELOC_MICROMIPS_JMP;
3305}
3306
738e5348
RS
3307static inline bfd_boolean
3308got16_reloc_p (bfd_reloc_code_real_type reloc)
3309{
2309ddf2 3310 return (reloc == BFD_RELOC_MIPS_GOT16 || reloc == BFD_RELOC_MIPS16_GOT16
df58fc94 3311 || reloc == BFD_RELOC_MICROMIPS_GOT16);
738e5348
RS
3312}
3313
3314static inline bfd_boolean
3315hi16_reloc_p (bfd_reloc_code_real_type reloc)
3316{
2309ddf2 3317 return (reloc == BFD_RELOC_HI16_S || reloc == BFD_RELOC_MIPS16_HI16_S
df58fc94 3318 || reloc == BFD_RELOC_MICROMIPS_HI16_S);
738e5348
RS
3319}
3320
3321static inline bfd_boolean
3322lo16_reloc_p (bfd_reloc_code_real_type reloc)
3323{
2309ddf2 3324 return (reloc == BFD_RELOC_LO16 || reloc == BFD_RELOC_MIPS16_LO16
df58fc94
RS
3325 || reloc == BFD_RELOC_MICROMIPS_LO16);
3326}
3327
df58fc94
RS
3328static inline bfd_boolean
3329jalr_reloc_p (bfd_reloc_code_real_type reloc)
3330{
2309ddf2 3331 return reloc == BFD_RELOC_MIPS_JALR || reloc == BFD_RELOC_MICROMIPS_JALR;
738e5348
RS
3332}
3333
f2ae14a1
RS
3334static inline bfd_boolean
3335gprel16_reloc_p (bfd_reloc_code_real_type reloc)
3336{
3337 return (reloc == BFD_RELOC_GPREL16 || reloc == BFD_RELOC_MIPS16_GPREL
3338 || reloc == BFD_RELOC_MICROMIPS_GPREL16);
3339}
3340
2de39019
CM
3341/* Return true if RELOC is a PC-relative relocation that does not have
3342 full address range. */
3343
3344static inline bfd_boolean
3345limited_pcrel_reloc_p (bfd_reloc_code_real_type reloc)
3346{
3347 switch (reloc)
3348 {
3349 case BFD_RELOC_16_PCREL_S2:
3350 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
3351 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
3352 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
3353 return TRUE;
3354
b47468a6
CM
3355 case BFD_RELOC_32_PCREL:
3356 return HAVE_64BIT_ADDRESSES;
3357
2de39019
CM
3358 default:
3359 return FALSE;
3360 }
3361}
b47468a6 3362
5919d012 3363/* Return true if the given relocation might need a matching %lo().
0a44bf69
RS
3364 This is only "might" because SVR4 R_MIPS_GOT16 relocations only
3365 need a matching %lo() when applied to local symbols. */
5919d012
RS
3366
3367static inline bfd_boolean
17a2f251 3368reloc_needs_lo_p (bfd_reloc_code_real_type reloc)
5919d012 3369{
3b91255e 3370 return (HAVE_IN_PLACE_ADDENDS
738e5348 3371 && (hi16_reloc_p (reloc)
0a44bf69
RS
3372 /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo();
3373 all GOT16 relocations evaluate to "G". */
738e5348
RS
3374 || (got16_reloc_p (reloc) && mips_pic != VXWORKS_PIC)));
3375}
3376
3377/* Return the type of %lo() reloc needed by RELOC, given that
3378 reloc_needs_lo_p. */
3379
3380static inline bfd_reloc_code_real_type
3381matching_lo_reloc (bfd_reloc_code_real_type reloc)
3382{
df58fc94
RS
3383 return (mips16_reloc_p (reloc) ? BFD_RELOC_MIPS16_LO16
3384 : (micromips_reloc_p (reloc) ? BFD_RELOC_MICROMIPS_LO16
3385 : BFD_RELOC_LO16));
5919d012
RS
3386}
3387
3388/* Return true if the given fixup is followed by a matching R_MIPS_LO16
3389 relocation. */
3390
3391static inline bfd_boolean
17a2f251 3392fixup_has_matching_lo_p (fixS *fixp)
5919d012
RS
3393{
3394 return (fixp->fx_next != NULL
738e5348 3395 && fixp->fx_next->fx_r_type == matching_lo_reloc (fixp->fx_r_type)
5919d012
RS
3396 && fixp->fx_addsy == fixp->fx_next->fx_addsy
3397 && fixp->fx_offset == fixp->fx_next->fx_offset);
3398}
3399
462427c4
RS
3400/* Move all labels in LABELS to the current insertion point. TEXT_P
3401 says whether the labels refer to text or data. */
404a8071
RS
3402
3403static void
462427c4 3404mips_move_labels (struct insn_label_list *labels, bfd_boolean text_p)
404a8071
RS
3405{
3406 struct insn_label_list *l;
3407 valueT val;
3408
462427c4 3409 for (l = labels; l != NULL; l = l->next)
404a8071 3410 {
9c2799c2 3411 gas_assert (S_GET_SEGMENT (l->label) == now_seg);
404a8071
RS
3412 symbol_set_frag (l->label, frag_now);
3413 val = (valueT) frag_now_fix ();
df58fc94 3414 /* MIPS16/microMIPS text labels are stored as odd. */
462427c4 3415 if (text_p && HAVE_CODE_COMPRESSION)
404a8071
RS
3416 ++val;
3417 S_SET_VALUE (l->label, val);
3418 }
3419}
3420
462427c4
RS
3421/* Move all labels in insn_labels to the current insertion point
3422 and treat them as text labels. */
3423
3424static void
3425mips_move_text_labels (void)
3426{
3427 mips_move_labels (seg_info (now_seg)->label_list, TRUE);
3428}
3429
5f0fe04b
TS
3430static bfd_boolean
3431s_is_linkonce (symbolS *sym, segT from_seg)
3432{
3433 bfd_boolean linkonce = FALSE;
3434 segT symseg = S_GET_SEGMENT (sym);
3435
3436 if (symseg != from_seg && !S_IS_LOCAL (sym))
3437 {
3438 if ((bfd_get_section_flags (stdoutput, symseg) & SEC_LINK_ONCE))
3439 linkonce = TRUE;
5f0fe04b
TS
3440 /* The GNU toolchain uses an extension for ELF: a section
3441 beginning with the magic string .gnu.linkonce is a
3442 linkonce section. */
3443 if (strncmp (segment_name (symseg), ".gnu.linkonce",
3444 sizeof ".gnu.linkonce" - 1) == 0)
3445 linkonce = TRUE;
5f0fe04b
TS
3446 }
3447 return linkonce;
3448}
3449
e1b47bd5 3450/* Mark MIPS16 or microMIPS instruction label LABEL. This permits the
df58fc94
RS
3451 linker to handle them specially, such as generating jalx instructions
3452 when needed. We also make them odd for the duration of the assembly,
3453 in order to generate the right sort of code. We will make them even
252b5132
RH
3454 in the adjust_symtab routine, while leaving them marked. This is
3455 convenient for the debugger and the disassembler. The linker knows
3456 to make them odd again. */
3457
3458static void
e1b47bd5 3459mips_compressed_mark_label (symbolS *label)
252b5132 3460{
df58fc94 3461 gas_assert (HAVE_CODE_COMPRESSION);
a8dbcb85 3462
f3ded42a
RS
3463 if (mips_opts.mips16)
3464 S_SET_OTHER (label, ELF_ST_SET_MIPS16 (S_GET_OTHER (label)));
3465 else
3466 S_SET_OTHER (label, ELF_ST_SET_MICROMIPS (S_GET_OTHER (label)));
e1b47bd5
RS
3467 if ((S_GET_VALUE (label) & 1) == 0
3468 /* Don't adjust the address if the label is global or weak, or
3469 in a link-once section, since we'll be emitting symbol reloc
3470 references to it which will be patched up by the linker, and
3471 the final value of the symbol may or may not be MIPS16/microMIPS. */
3472 && !S_IS_WEAK (label)
3473 && !S_IS_EXTERNAL (label)
3474 && !s_is_linkonce (label, now_seg))
3475 S_SET_VALUE (label, S_GET_VALUE (label) | 1);
3476}
3477
3478/* Mark preceding MIPS16 or microMIPS instruction labels. */
3479
3480static void
3481mips_compressed_mark_labels (void)
3482{
3483 struct insn_label_list *l;
3484
3485 for (l = seg_info (now_seg)->label_list; l != NULL; l = l->next)
3486 mips_compressed_mark_label (l->label);
252b5132
RH
3487}
3488
4d7206a2
RS
3489/* End the current frag. Make it a variant frag and record the
3490 relaxation info. */
3491
3492static void
3493relax_close_frag (void)
3494{
584892a6 3495 mips_macro_warning.first_frag = frag_now;
4d7206a2 3496 frag_var (rs_machine_dependent, 0, 0,
584892a6 3497 RELAX_ENCODE (mips_relax.sizes[0], mips_relax.sizes[1]),
4d7206a2
RS
3498 mips_relax.symbol, 0, (char *) mips_relax.first_fixup);
3499
3500 memset (&mips_relax.sizes, 0, sizeof (mips_relax.sizes));
3501 mips_relax.first_fixup = 0;
3502}
3503
3504/* Start a new relaxation sequence whose expansion depends on SYMBOL.
3505 See the comment above RELAX_ENCODE for more details. */
3506
3507static void
3508relax_start (symbolS *symbol)
3509{
9c2799c2 3510 gas_assert (mips_relax.sequence == 0);
4d7206a2
RS
3511 mips_relax.sequence = 1;
3512 mips_relax.symbol = symbol;
3513}
3514
3515/* Start generating the second version of a relaxable sequence.
3516 See the comment above RELAX_ENCODE for more details. */
252b5132
RH
3517
3518static void
4d7206a2
RS
3519relax_switch (void)
3520{
9c2799c2 3521 gas_assert (mips_relax.sequence == 1);
4d7206a2
RS
3522 mips_relax.sequence = 2;
3523}
3524
3525/* End the current relaxable sequence. */
3526
3527static void
3528relax_end (void)
3529{
9c2799c2 3530 gas_assert (mips_relax.sequence == 2);
4d7206a2
RS
3531 relax_close_frag ();
3532 mips_relax.sequence = 0;
3533}
3534
11625dd8
RS
3535/* Return true if IP is a delayed branch or jump. */
3536
3537static inline bfd_boolean
3538delayed_branch_p (const struct mips_cl_insn *ip)
3539{
3540 return (ip->insn_mo->pinfo & (INSN_UNCOND_BRANCH_DELAY
3541 | INSN_COND_BRANCH_DELAY
3542 | INSN_COND_BRANCH_LIKELY)) != 0;
3543}
3544
3545/* Return true if IP is a compact branch or jump. */
3546
3547static inline bfd_boolean
3548compact_branch_p (const struct mips_cl_insn *ip)
3549{
3550 if (mips_opts.mips16)
3551 return (ip->insn_mo->pinfo & (MIPS16_INSN_UNCOND_BRANCH
3552 | MIPS16_INSN_COND_BRANCH)) != 0;
3553 else
3554 return (ip->insn_mo->pinfo2 & (INSN2_UNCOND_BRANCH
3555 | INSN2_COND_BRANCH)) != 0;
3556}
3557
3558/* Return true if IP is an unconditional branch or jump. */
3559
3560static inline bfd_boolean
3561uncond_branch_p (const struct mips_cl_insn *ip)
3562{
3563 return ((ip->insn_mo->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0
3564 || (mips_opts.mips16
3565 ? (ip->insn_mo->pinfo & MIPS16_INSN_UNCOND_BRANCH) != 0
3566 : (ip->insn_mo->pinfo2 & INSN2_UNCOND_BRANCH) != 0));
3567}
3568
3569/* Return true if IP is a branch-likely instruction. */
3570
3571static inline bfd_boolean
3572branch_likely_p (const struct mips_cl_insn *ip)
3573{
3574 return (ip->insn_mo->pinfo & INSN_COND_BRANCH_LIKELY) != 0;
3575}
3576
14fe068b
RS
3577/* Return the type of nop that should be used to fill the delay slot
3578 of delayed branch IP. */
3579
3580static struct mips_cl_insn *
3581get_delay_slot_nop (const struct mips_cl_insn *ip)
3582{
3583 if (mips_opts.micromips
3584 && (ip->insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
3585 return &micromips_nop32_insn;
3586 return NOP_INSN;
3587}
3588
2309ddf2 3589/* Return the mask of core registers that IP reads or writes. */
df58fc94
RS
3590
3591static unsigned int
3592gpr_mod_mask (const struct mips_cl_insn *ip)
3593{
2309ddf2 3594 unsigned long pinfo2;
df58fc94
RS
3595 unsigned int mask;
3596
3597 mask = 0;
df58fc94
RS
3598 pinfo2 = ip->insn_mo->pinfo2;
3599 if (mips_opts.micromips)
3600 {
df58fc94
RS
3601 if (pinfo2 & INSN2_MOD_GPR_MD)
3602 mask |= 1 << micromips_to_32_reg_d_map[EXTRACT_OPERAND (1, MD, *ip)];
df58fc94
RS
3603 if (pinfo2 & INSN2_MOD_GPR_MF)
3604 mask |= 1 << micromips_to_32_reg_f_map[EXTRACT_OPERAND (1, MF, *ip)];
df58fc94
RS
3605 if (pinfo2 & INSN2_MOD_SP)
3606 mask |= 1 << SP;
3607 }
3608 return mask;
3609}
3610
4c260379
RS
3611/* Return the mask of core registers that IP reads. */
3612
3613static unsigned int
3614gpr_read_mask (const struct mips_cl_insn *ip)
3615{
3616 unsigned long pinfo, pinfo2;
3617 unsigned int mask;
3618
df58fc94 3619 mask = gpr_mod_mask (ip);
4c260379
RS
3620 pinfo = ip->insn_mo->pinfo;
3621 pinfo2 = ip->insn_mo->pinfo2;
3622 if (mips_opts.mips16)
3623 {
3624 if (pinfo & MIPS16_INSN_READ_X)
3625 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, *ip)];
3626 if (pinfo & MIPS16_INSN_READ_Y)
3627 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RY, *ip)];
3628 if (pinfo & MIPS16_INSN_READ_T)
3629 mask |= 1 << TREG;
3630 if (pinfo & MIPS16_INSN_READ_SP)
3631 mask |= 1 << SP;
3632 if (pinfo & MIPS16_INSN_READ_31)
3633 mask |= 1 << RA;
3634 if (pinfo & MIPS16_INSN_READ_Z)
3635 mask |= 1 << (mips16_to_32_reg_map
3636 [MIPS16_EXTRACT_OPERAND (MOVE32Z, *ip)]);
3637 if (pinfo & MIPS16_INSN_READ_GPR_X)
3638 mask |= 1 << MIPS16_EXTRACT_OPERAND (REGR32, *ip);
3639 }
3640 else
3641 {
3642 if (pinfo2 & INSN2_READ_GPR_D)
2309ddf2 3643 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RD, *ip);
4c260379 3644 if (pinfo & INSN_READ_GPR_T)
2309ddf2 3645 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RT, *ip);
4c260379 3646 if (pinfo & INSN_READ_GPR_S)
2309ddf2
MR
3647 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RS, *ip);
3648 if (pinfo2 & INSN2_READ_GP)
3649 mask |= 1 << GP;
3650 if (pinfo2 & INSN2_READ_GPR_31)
3651 mask |= 1 << RA;
4c260379 3652 if (pinfo2 & INSN2_READ_GPR_Z)
2309ddf2 3653 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RZ, *ip);
4c260379 3654 }
2b0c8b40
MR
3655 if (mips_opts.micromips)
3656 {
3657 if (pinfo2 & INSN2_READ_GPR_MC)
3658 mask |= 1 << micromips_to_32_reg_c_map[EXTRACT_OPERAND (1, MC, *ip)];
3659 if (pinfo2 & INSN2_READ_GPR_ME)
3660 mask |= 1 << micromips_to_32_reg_e_map[EXTRACT_OPERAND (1, ME, *ip)];
3661 if (pinfo2 & INSN2_READ_GPR_MG)
3662 mask |= 1 << micromips_to_32_reg_g_map[EXTRACT_OPERAND (1, MG, *ip)];
3663 if (pinfo2 & INSN2_READ_GPR_MJ)
3664 mask |= 1 << EXTRACT_OPERAND (1, MJ, *ip);
3665 if (pinfo2 & INSN2_READ_GPR_MMN)
3666 {
3667 mask |= 1 << micromips_to_32_reg_m_map[EXTRACT_OPERAND (1, MM, *ip)];
3668 mask |= 1 << micromips_to_32_reg_n_map[EXTRACT_OPERAND (1, MN, *ip)];
3669 }
3670 if (pinfo2 & INSN2_READ_GPR_MP)
3671 mask |= 1 << EXTRACT_OPERAND (1, MP, *ip);
3672 if (pinfo2 & INSN2_READ_GPR_MQ)
3673 mask |= 1 << micromips_to_32_reg_q_map[EXTRACT_OPERAND (1, MQ, *ip)];
3674 }
fe35f09f
RS
3675 /* Don't include register 0. */
3676 return mask & ~1;
4c260379
RS
3677}
3678
3679/* Return the mask of core registers that IP writes. */
3680
3681static unsigned int
3682gpr_write_mask (const struct mips_cl_insn *ip)
3683{
3684 unsigned long pinfo, pinfo2;
3685 unsigned int mask;
3686
df58fc94 3687 mask = gpr_mod_mask (ip);
4c260379
RS
3688 pinfo = ip->insn_mo->pinfo;
3689 pinfo2 = ip->insn_mo->pinfo2;
3690 if (mips_opts.mips16)
3691 {
3692 if (pinfo & MIPS16_INSN_WRITE_X)
3693 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, *ip)];
3694 if (pinfo & MIPS16_INSN_WRITE_Y)
3695 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RY, *ip)];
3696 if (pinfo & MIPS16_INSN_WRITE_Z)
3697 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RZ, *ip)];
3698 if (pinfo & MIPS16_INSN_WRITE_T)
3699 mask |= 1 << TREG;
3700 if (pinfo & MIPS16_INSN_WRITE_SP)
3701 mask |= 1 << SP;
3702 if (pinfo & MIPS16_INSN_WRITE_31)
3703 mask |= 1 << RA;
3704 if (pinfo & MIPS16_INSN_WRITE_GPR_Y)
3705 mask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode);
3706 }
3707 else
3708 {
3709 if (pinfo & INSN_WRITE_GPR_D)
df58fc94 3710 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RD, *ip);
4c260379 3711 if (pinfo & INSN_WRITE_GPR_T)
df58fc94 3712 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RT, *ip);
2b0c8b40 3713 if (pinfo & INSN_WRITE_GPR_S)
2309ddf2 3714 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RS, *ip);
4c260379
RS
3715 if (pinfo & INSN_WRITE_GPR_31)
3716 mask |= 1 << RA;
3717 if (pinfo2 & INSN2_WRITE_GPR_Z)
df58fc94 3718 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RZ, *ip);
4c260379 3719 }
2b0c8b40
MR
3720 if (mips_opts.micromips)
3721 {
3722 if (pinfo2 & INSN2_WRITE_GPR_MB)
3723 mask |= 1 << micromips_to_32_reg_b_map[EXTRACT_OPERAND (1, MB, *ip)];
e76ff5ab 3724 if (pinfo2 & INSN2_WRITE_GPR_MH)
2b0c8b40 3725 {
e76ff5ab
RS
3726 mask |= 1 << micromips_to_32_reg_h_map1[EXTRACT_OPERAND (1, MH, *ip)];
3727 mask |= 1 << micromips_to_32_reg_h_map2[EXTRACT_OPERAND (1, MH, *ip)];
2b0c8b40
MR
3728 }
3729 if (pinfo2 & INSN2_WRITE_GPR_MJ)
3730 mask |= 1 << EXTRACT_OPERAND (1, MJ, *ip);
3731 if (pinfo2 & INSN2_WRITE_GPR_MP)
3732 mask |= 1 << EXTRACT_OPERAND (1, MP, *ip);
3733 }
fe35f09f
RS
3734 /* Don't include register 0. */
3735 return mask & ~1;
4c260379
RS
3736}
3737
3738/* Return the mask of floating-point registers that IP reads. */
3739
3740static unsigned int
3741fpr_read_mask (const struct mips_cl_insn *ip)
3742{
3743 unsigned long pinfo, pinfo2;
3744 unsigned int mask;
3745
3746 mask = 0;
3747 pinfo = ip->insn_mo->pinfo;
3748 pinfo2 = ip->insn_mo->pinfo2;
2309ddf2 3749 if (!mips_opts.mips16)
df58fc94
RS
3750 {
3751 if (pinfo2 & INSN2_READ_FPR_D)
2309ddf2 3752 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FD, *ip);
4c260379 3753 if (pinfo & INSN_READ_FPR_S)
df58fc94 3754 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FS, *ip);
4c260379 3755 if (pinfo & INSN_READ_FPR_T)
df58fc94 3756 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FT, *ip);
4c260379 3757 if (pinfo & INSN_READ_FPR_R)
df58fc94 3758 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FR, *ip);
4c260379 3759 if (pinfo2 & INSN2_READ_FPR_Z)
df58fc94 3760 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FZ, *ip);
4c260379
RS
3761 }
3762 /* Conservatively treat all operands to an FP_D instruction are doubles.
3763 (This is overly pessimistic for things like cvt.d.s.) */
3764 if (HAVE_32BIT_FPRS && (pinfo & FP_D))
3765 mask |= mask << 1;
3766 return mask;
3767}
3768
3769/* Return the mask of floating-point registers that IP writes. */
3770
3771static unsigned int
3772fpr_write_mask (const struct mips_cl_insn *ip)
3773{
3774 unsigned long pinfo, pinfo2;
3775 unsigned int mask;
3776
3777 mask = 0;
3778 pinfo = ip->insn_mo->pinfo;
3779 pinfo2 = ip->insn_mo->pinfo2;
2309ddf2 3780 if (!mips_opts.mips16)
4c260379
RS
3781 {
3782 if (pinfo & INSN_WRITE_FPR_D)
df58fc94 3783 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FD, *ip);
4c260379 3784 if (pinfo & INSN_WRITE_FPR_S)
df58fc94 3785 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FS, *ip);
4c260379 3786 if (pinfo & INSN_WRITE_FPR_T)
df58fc94 3787 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FT, *ip);
4c260379 3788 if (pinfo2 & INSN2_WRITE_FPR_Z)
df58fc94 3789 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FZ, *ip);
4c260379
RS
3790 }
3791 /* Conservatively treat all operands to an FP_D instruction are doubles.
3792 (This is overly pessimistic for things like cvt.s.d.) */
3793 if (HAVE_32BIT_FPRS && (pinfo & FP_D))
3794 mask |= mask << 1;
3795 return mask;
3796}
3797
a1d78564
RS
3798/* Operand OPNUM of INSN is an odd-numbered floating-point register.
3799 Check whether that is allowed. */
3800
3801static bfd_boolean
3802mips_oddfpreg_ok (const struct mips_opcode *insn, int opnum)
3803{
3804 const char *s = insn->name;
3805
3806 if (insn->pinfo == INSN_MACRO)
3807 /* Let a macro pass, we'll catch it later when it is expanded. */
3808 return TRUE;
3809
3810 if (ISA_HAS_ODD_SINGLE_FPR (mips_opts.isa) || mips_opts.arch == CPU_R5900)
3811 {
3812 /* Allow odd registers for single-precision ops. */
3813 switch (insn->pinfo & (FP_S | FP_D))
3814 {
3815 case FP_S:
3816 case 0:
3817 return TRUE;
3818 case FP_D:
3819 return FALSE;
3820 default:
3821 break;
3822 }
3823
3824 /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */
3825 s = strchr (insn->name, '.');
3826 if (s != NULL && opnum == 2)
3827 s = strchr (s + 1, '.');
3828 return (s != NULL && (s[1] == 'w' || s[1] == 's'));
3829 }
3830
3831 /* Single-precision coprocessor loads and moves are OK too. */
3832 if ((insn->pinfo & FP_S)
3833 && (insn->pinfo & (INSN_COPROC_MEMORY_DELAY | INSN_STORE_MEMORY
3834 | INSN_LOAD_COPROC_DELAY | INSN_COPROC_MOVE_DELAY)))
3835 return TRUE;
3836
3837 return FALSE;
3838}
3839
a1d78564
RS
3840/* Report that user-supplied argument ARGNUM for INSN was VAL, but should
3841 have been in the range [MIN_VAL, MAX_VAL]. PRINT_HEX says whether
3842 this operand is normally printed in hex or decimal. */
3843
3844static void
3845report_bad_range (struct mips_cl_insn *insn, int argnum,
3846 offsetT val, int min_val, int max_val,
3847 bfd_boolean print_hex)
3848{
3849 if (print_hex && val >= 0)
3850 as_bad (_("Operand %d of `%s' must be in the range [0x%x, 0x%x],"
3851 " was 0x%lx."),
3852 argnum, insn->insn_mo->name, min_val, max_val, (unsigned long) val);
3853 else if (print_hex)
3854 as_bad (_("Operand %d of `%s' must be in the range [0x%x, 0x%x],"
3855 " was %ld."),
3856 argnum, insn->insn_mo->name, min_val, max_val, (unsigned long) val);
3857 else
3858 as_bad (_("Operand %d of `%s' must be in the range [%d, %d],"
3859 " was %ld."),
3860 argnum, insn->insn_mo->name, min_val, max_val, (unsigned long) val);
3861}
3862
3863/* Report an invalid combination of position and size operands for a bitfield
3864 operation. POS and SIZE are the values that were given. */
3865
3866static void
3867report_bad_field (offsetT pos, offsetT size)
3868{
3869 as_bad (_("Invalid field specification (position %ld, size %ld)"),
3870 (unsigned long) pos, (unsigned long) size);
3871}
3872
3873/* Information about an instruction argument that we're trying to match. */
3874struct mips_arg_info
3875{
3876 /* The instruction so far. */
3877 struct mips_cl_insn *insn;
3878
a92713e6
RS
3879 /* The first unconsumed operand token. */
3880 struct mips_operand_token *token;
3881
a1d78564
RS
3882 /* The 1-based operand number, in terms of insn->insn_mo->args. */
3883 int opnum;
3884
3885 /* The 1-based argument number, for error reporting. This does not
3886 count elided optional registers, etc.. */
3887 int argnum;
3888
3889 /* The last OP_REG operand seen, or ILLEGAL_REG if none. */
3890 unsigned int last_regno;
3891
3892 /* If the first operand was an OP_REG, this is the register that it
3893 specified, otherwise it is ILLEGAL_REG. */
3894 unsigned int dest_regno;
3895
3896 /* The value of the last OP_INT operand. Only used for OP_MSB,
3897 where it gives the lsb position. */
3898 unsigned int last_op_int;
3899
3900 /* If true, match routines should silently reject invalid arguments.
3901 If false, match routines can accept invalid arguments as long as
3902 they report an appropriate error. They still have the option of
3903 silently rejecting arguments, in which case a generic "Invalid operands"
3904 style of error will be used instead. */
3905 bfd_boolean soft_match;
3906
3907 /* If true, the OP_INT match routine should treat plain symbolic operands
3908 as if a relocation operator like %lo(...) had been used. This is only
3909 ever true if the operand can be relocated. */
3910 bfd_boolean allow_nonconst;
3911
3912 /* When true, the OP_INT match routine should allow unsigned N-bit
3913 arguments to be used where a signed N-bit operand is expected. */
3914 bfd_boolean lax_max;
3915
a1d78564
RS
3916 /* True if a reference to the current AT register was seen. */
3917 bfd_boolean seen_at;
3918};
3919
a92713e6
RS
3920/* Try to match an OT_CHAR token for character CH. Consume the token
3921 and return true on success, otherwise return false. */
a1d78564 3922
a92713e6
RS
3923static bfd_boolean
3924match_char (struct mips_arg_info *arg, char ch)
a1d78564 3925{
a92713e6
RS
3926 if (arg->token->type == OT_CHAR && arg->token->u.ch == ch)
3927 {
3928 ++arg->token;
3929 if (ch == ',')
3930 arg->argnum += 1;
3931 return TRUE;
3932 }
3933 return FALSE;
3934}
a1d78564 3935
a92713e6
RS
3936/* Try to get an expression from the next tokens in ARG. Consume the
3937 tokens and return true on success, storing the expression value in
3938 VALUE and relocation types in R. */
3939
3940static bfd_boolean
3941match_expression (struct mips_arg_info *arg, expressionS *value,
3942 bfd_reloc_code_real_type *r)
3943{
3944 if (arg->token->type == OT_INTEGER)
a1d78564 3945 {
a92713e6
RS
3946 *value = arg->token->u.integer.value;
3947 memcpy (r, arg->token->u.integer.relocs, 3 * sizeof (*r));
3948 ++arg->token;
3949 return TRUE;
3950 }
3951
3952 /* Error-reporting is more consistent if we treat registers as O_register
3953 rather than rejecting them outright. "$1", "($1)" and "(($1))" are
3954 then handled in the same way. */
3955 if (arg->token->type == OT_REG)
3956 {
3957 value->X_add_number = arg->token->u.regno;
3958 ++arg->token;
a1d78564 3959 }
a92713e6
RS
3960 else if (arg->token[0].type == OT_CHAR
3961 && arg->token[0].u.ch == '('
3962 && arg->token[1].type == OT_REG
3963 && arg->token[2].type == OT_CHAR
3964 && arg->token[2].u.ch == ')')
3965 {
3966 value->X_add_number = arg->token[1].u.regno;
3967 arg->token += 3;
3968 }
3969 else
3970 return FALSE;
3971
3972 value->X_op = O_register;
3973 r[0] = r[1] = r[2] = BFD_RELOC_UNUSED;
3974 return TRUE;
3975}
3976
3977/* Try to get a constant expression from the next tokens in ARG. Consume
3978 the tokens and return return true on success, storing the constant value
3979 in *VALUE. Use FALLBACK as the value if the match succeeded with an
3980 error. */
3981
3982static bfd_boolean
3983match_const_int (struct mips_arg_info *arg, offsetT *value, offsetT fallback)
3984{
3985 expressionS ex;
3986 bfd_reloc_code_real_type r[3];
a1d78564 3987
a92713e6
RS
3988 if (!match_expression (arg, &ex, r))
3989 return FALSE;
3990
3991 if (r[0] == BFD_RELOC_UNUSED && ex.X_op == O_constant)
a1d78564
RS
3992 *value = ex.X_add_number;
3993 else
3994 {
a92713e6
RS
3995 if (arg->soft_match)
3996 return FALSE;
a1d78564
RS
3997 as_bad (_("Operand %d of `%s' must be constant"),
3998 arg->argnum, arg->insn->insn_mo->name);
3999 *value = fallback;
4000 }
a92713e6 4001 return TRUE;
a1d78564
RS
4002}
4003
4004/* Return the RTYPE_* flags for a register operand of type TYPE that
4005 appears in instruction OPCODE. */
4006
4007static unsigned int
4008convert_reg_type (const struct mips_opcode *opcode,
4009 enum mips_reg_operand_type type)
4010{
4011 switch (type)
4012 {
4013 case OP_REG_GP:
4014 return RTYPE_NUM | RTYPE_GP;
4015
4016 case OP_REG_FP:
4017 /* Allow vector register names for MDMX if the instruction is a 64-bit
4018 FPR load, store or move (including moves to and from GPRs). */
4019 if ((mips_opts.ase & ASE_MDMX)
4020 && (opcode->pinfo & FP_D)
4021 && (opcode->pinfo & (INSN_COPROC_MOVE_DELAY
4022 | INSN_COPROC_MEMORY_DELAY
4023 | INSN_LOAD_COPROC_DELAY
4024 | INSN_LOAD_MEMORY_DELAY
4025 | INSN_STORE_MEMORY)))
4026 return RTYPE_FPU | RTYPE_VEC;
4027 return RTYPE_FPU;
4028
4029 case OP_REG_CCC:
4030 if (opcode->pinfo & (FP_D | FP_S))
4031 return RTYPE_CCC | RTYPE_FCC;
4032 return RTYPE_CCC;
4033
4034 case OP_REG_VEC:
4035 if (opcode->membership & INSN_5400)
4036 return RTYPE_FPU;
4037 return RTYPE_FPU | RTYPE_VEC;
4038
4039 case OP_REG_ACC:
4040 return RTYPE_ACC;
4041
4042 case OP_REG_COPRO:
4043 if (opcode->name[strlen (opcode->name) - 1] == '0')
4044 return RTYPE_NUM | RTYPE_CP0;
4045 return RTYPE_NUM;
4046
4047 case OP_REG_HW:
4048 return RTYPE_NUM;
4049 }
4050 abort ();
4051}
4052
4053/* ARG is register REGNO, of type TYPE. Warn about any dubious registers. */
4054
4055static void
4056check_regno (struct mips_arg_info *arg,
4057 enum mips_reg_operand_type type, unsigned int regno)
4058{
4059 if (AT && type == OP_REG_GP && regno == AT)
4060 arg->seen_at = TRUE;
4061
4062 if (type == OP_REG_FP
4063 && (regno & 1) != 0
4064 && HAVE_32BIT_FPRS
4065 && !mips_oddfpreg_ok (arg->insn->insn_mo, arg->opnum))
4066 as_warn (_("Float register should be even, was %d"), regno);
4067
4068 if (type == OP_REG_CCC)
4069 {
4070 const char *name;
4071 size_t length;
4072
4073 name = arg->insn->insn_mo->name;
4074 length = strlen (name);
4075 if ((regno & 1) != 0
4076 && ((length >= 3 && strcmp (name + length - 3, ".ps") == 0)
4077 || (length >= 5 && strncmp (name + length - 5, "any2", 4) == 0)))
4078 as_warn (_("Condition code register should be even for %s, was %d"),
4079 name, regno);
4080
4081 if ((regno & 3) != 0
4082 && (length >= 5 && strncmp (name + length - 5, "any4", 4) == 0))
4083 as_warn (_("Condition code register should be 0 or 4 for %s, was %d"),
4084 name, regno);
4085 }
4086}
4087
a92713e6
RS
4088/* ARG is a register with symbol value SYMVAL. Try to interpret it as
4089 a register of type TYPE. Return true on success, storing the register
4090 number in *REGNO and warning about any dubious uses. */
4091
4092static bfd_boolean
4093match_regno (struct mips_arg_info *arg, enum mips_reg_operand_type type,
4094 unsigned int symval, unsigned int *regno)
4095{
4096 if (type == OP_REG_VEC)
4097 symval = mips_prefer_vec_regno (symval);
4098 if (!(symval & convert_reg_type (arg->insn->insn_mo, type)))
4099 return FALSE;
4100
4101 *regno = symval & RNUM_MASK;
4102 check_regno (arg, type, *regno);
4103 return TRUE;
4104}
4105
4106/* Try to interpret the next token in ARG as a register of type TYPE.
4107 Consume the token and return true on success, storing the register
4108 number in *REGNO. Return false on failure. */
4109
4110static bfd_boolean
4111match_reg (struct mips_arg_info *arg, enum mips_reg_operand_type type,
4112 unsigned int *regno)
4113{
4114 if (arg->token->type == OT_REG
4115 && match_regno (arg, type, arg->token->u.regno, regno))
4116 {
4117 ++arg->token;
4118 return TRUE;
4119 }
4120 return FALSE;
4121}
4122
4123/* Try to interpret the next token in ARG as a range of registers of type TYPE.
4124 Consume the token and return true on success, storing the register numbers
4125 in *REGNO1 and *REGNO2. Return false on failure. */
4126
4127static bfd_boolean
4128match_reg_range (struct mips_arg_info *arg, enum mips_reg_operand_type type,
4129 unsigned int *regno1, unsigned int *regno2)
4130{
4131 if (match_reg (arg, type, regno1))
4132 {
4133 *regno2 = *regno1;
4134 return TRUE;
4135 }
4136 if (arg->token->type == OT_REG_RANGE
4137 && match_regno (arg, type, arg->token->u.reg_range.regno1, regno1)
4138 && match_regno (arg, type, arg->token->u.reg_range.regno2, regno2)
4139 && *regno1 <= *regno2)
4140 {
4141 ++arg->token;
4142 return TRUE;
4143 }
4144 return FALSE;
4145}
4146
a1d78564
RS
4147/* OP_INT matcher. */
4148
a92713e6 4149static bfd_boolean
a1d78564 4150match_int_operand (struct mips_arg_info *arg,
a92713e6 4151 const struct mips_operand *operand_base)
a1d78564
RS
4152{
4153 const struct mips_int_operand *operand;
4154 unsigned int uval, mask;
4155 int min_val, max_val, factor;
4156 offsetT sval;
4157 bfd_boolean print_hex;
4158
4159 operand = (const struct mips_int_operand *) operand_base;
4160 factor = 1 << operand->shift;
4161 mask = (1 << operand_base->size) - 1;
4162 max_val = (operand->max_val + operand->bias) << operand->shift;
4163 min_val = max_val - (mask << operand->shift);
4164 if (arg->lax_max)
4165 max_val = mask << operand->shift;
4166
a92713e6
RS
4167 if (arg->token->type == OT_CHAR && arg->token->u.ch == '(')
4168 /* Assume we have an elided offset. The later match will fail
4169 if this turns out to be wrong. */
4170 sval = 0;
4171 else if (operand_base->lsb == 0
4172 && operand_base->size == 16
4173 && operand->shift == 0
4174 && operand->bias == 0
4175 && (operand->max_val == 32767 || operand->max_val == 65535))
a1d78564
RS
4176 {
4177 /* The operand can be relocated. */
a92713e6
RS
4178 if (!match_expression (arg, &offset_expr, offset_reloc))
4179 return FALSE;
4180
4181 if (offset_reloc[0] != BFD_RELOC_UNUSED)
a1d78564
RS
4182 /* Relocation operators were used. Accept the arguent and
4183 leave the relocation value in offset_expr and offset_relocs
4184 for the caller to process. */
a92713e6
RS
4185 return TRUE;
4186
4187 if (offset_expr.X_op != O_constant)
a1d78564 4188 {
a92713e6
RS
4189 /* If non-constant operands are allowed then leave them for
4190 the caller to process, otherwise fail the match. */
4191 if (!arg->allow_nonconst)
4192 return FALSE;
4193 offset_reloc[0] = BFD_RELOC_LO16;
4194 return TRUE;
a1d78564 4195 }
a92713e6 4196
a1d78564
RS
4197 /* Clear the global state; we're going to install the operand
4198 ourselves. */
a92713e6 4199 sval = offset_expr.X_add_number;
a1d78564
RS
4200 offset_expr.X_op = O_absent;
4201 }
4202 else
4203 {
a92713e6
RS
4204 if (!match_const_int (arg, &sval, min_val))
4205 return FALSE;
a1d78564
RS
4206 }
4207
4208 arg->last_op_int = sval;
4209
4210 /* Check the range. If there's a problem, record the lowest acceptable
4211 value in arg->last_op_int in order to prevent an unhelpful error
4212 from OP_MSB too.
4213
4214 Bit counts have traditionally been printed in hex by the disassembler
4215 but printed as decimal in error messages. Only resort to hex if
4216 the operand is bigger than 6 bits. */
4217 print_hex = operand->print_hex && operand_base->size > 6;
4218 if (sval < min_val || sval > max_val)
4219 {
4220 if (arg->soft_match)
a92713e6 4221 return FALSE;
a1d78564
RS
4222 report_bad_range (arg->insn, arg->argnum, sval, min_val, max_val,
4223 print_hex);
4224 arg->last_op_int = min_val;
4225 }
4226 else if (sval % factor)
4227 {
4228 if (arg->soft_match)
a92713e6 4229 return FALSE;
a1d78564
RS
4230 as_bad (print_hex && sval >= 0
4231 ? _("Operand %d of `%s' must be a factor of %d, was 0x%lx.")
4232 : _("Operand %d of `%s' must be a factor of %d, was %ld."),
4233 arg->argnum, arg->insn->insn_mo->name, factor,
4234 (unsigned long) sval);
4235 arg->last_op_int = min_val;
4236 }
4237
4238 uval = (unsigned int) sval >> operand->shift;
4239 uval -= operand->bias;
4240
4241 /* Handle -mfix-cn63xxp1. */
4242 if (arg->opnum == 1
4243 && mips_fix_cn63xxp1
4244 && !mips_opts.micromips
4245 && strcmp ("pref", arg->insn->insn_mo->name) == 0)
4246 switch (uval)
4247 {
4248 case 5:
4249 case 25:
4250 case 26:
4251 case 27:
4252 case 28:
4253 case 29:
4254 case 30:
4255 case 31:
4256 /* These are ok. */
4257 break;
4258
4259 default:
4260 /* The rest must be changed to 28. */
4261 uval = 28;
4262 break;
4263 }
4264
4265 insn_insert_operand (arg->insn, operand_base, uval);
a92713e6 4266 return TRUE;
a1d78564
RS
4267}
4268
4269/* OP_MAPPED_INT matcher. */
4270
a92713e6 4271static bfd_boolean
a1d78564 4272match_mapped_int_operand (struct mips_arg_info *arg,
a92713e6 4273 const struct mips_operand *operand_base)
a1d78564
RS
4274{
4275 const struct mips_mapped_int_operand *operand;
4276 unsigned int uval, num_vals;
4277 offsetT sval;
4278
4279 operand = (const struct mips_mapped_int_operand *) operand_base;
a92713e6
RS
4280 if (!match_const_int (arg, &sval, operand->int_map[0]))
4281 return FALSE;
a1d78564
RS
4282
4283 num_vals = 1 << operand_base->size;
4284 for (uval = 0; uval < num_vals; uval++)
4285 if (operand->int_map[uval] == sval)
4286 break;
4287 if (uval == num_vals)
a92713e6 4288 return FALSE;
a1d78564
RS
4289
4290 insn_insert_operand (arg->insn, operand_base, uval);
a92713e6 4291 return TRUE;
a1d78564
RS
4292}
4293
4294/* OP_MSB matcher. */
4295
a92713e6 4296static bfd_boolean
a1d78564 4297match_msb_operand (struct mips_arg_info *arg,
a92713e6 4298 const struct mips_operand *operand_base)
a1d78564
RS
4299{
4300 const struct mips_msb_operand *operand;
4301 int min_val, max_val, max_high;
4302 offsetT size, sval, high;
4303
4304 operand = (const struct mips_msb_operand *) operand_base;
4305 min_val = operand->bias;
4306 max_val = min_val + (1 << operand_base->size) - 1;
4307 max_high = operand->opsize;
4308
a92713e6
RS
4309 if (!match_const_int (arg, &size, 1))
4310 return FALSE;
a1d78564
RS
4311
4312 high = size + arg->last_op_int;
4313 sval = operand->add_lsb ? high : size;
4314
4315 if (size < 0 || high > max_high || sval < min_val || sval > max_val)
4316 {
4317 if (arg->soft_match)
a92713e6 4318 return FALSE;
a1d78564
RS
4319 report_bad_field (arg->last_op_int, size);
4320 sval = min_val;
4321 }
4322 insn_insert_operand (arg->insn, operand_base, sval - min_val);
a92713e6 4323 return TRUE;
a1d78564
RS
4324}
4325
4326/* OP_REG matcher. */
4327
a92713e6 4328static bfd_boolean
a1d78564 4329match_reg_operand (struct mips_arg_info *arg,
a92713e6 4330 const struct mips_operand *operand_base)
a1d78564
RS
4331{
4332 const struct mips_reg_operand *operand;
a92713e6 4333 unsigned int regno, uval, num_vals;
a1d78564
RS
4334
4335 operand = (const struct mips_reg_operand *) operand_base;
a92713e6
RS
4336 if (!match_reg (arg, operand->reg_type, &regno))
4337 return FALSE;
a1d78564
RS
4338
4339 if (operand->reg_map)
4340 {
4341 num_vals = 1 << operand->root.size;
4342 for (uval = 0; uval < num_vals; uval++)
4343 if (operand->reg_map[uval] == regno)
4344 break;
4345 if (num_vals == uval)
a92713e6 4346 return FALSE;
a1d78564
RS
4347 }
4348 else
4349 uval = regno;
4350
a1d78564
RS
4351 arg->last_regno = regno;
4352 if (arg->opnum == 1)
4353 arg->dest_regno = regno;
4354 insn_insert_operand (arg->insn, operand_base, uval);
a92713e6 4355 return TRUE;
a1d78564
RS
4356}
4357
4358/* OP_REG_PAIR matcher. */
4359
a92713e6 4360static bfd_boolean
a1d78564 4361match_reg_pair_operand (struct mips_arg_info *arg,
a92713e6 4362 const struct mips_operand *operand_base)
a1d78564
RS
4363{
4364 const struct mips_reg_pair_operand *operand;
a92713e6 4365 unsigned int regno1, regno2, uval, num_vals;
a1d78564
RS
4366
4367 operand = (const struct mips_reg_pair_operand *) operand_base;
a92713e6
RS
4368 if (!match_reg (arg, operand->reg_type, &regno1)
4369 || !match_char (arg, ',')
4370 || !match_reg (arg, operand->reg_type, &regno2))
4371 return FALSE;
a1d78564
RS
4372
4373 num_vals = 1 << operand_base->size;
4374 for (uval = 0; uval < num_vals; uval++)
4375 if (operand->reg1_map[uval] == regno1 && operand->reg2_map[uval] == regno2)
4376 break;
4377 if (uval == num_vals)
a92713e6 4378 return FALSE;
a1d78564 4379
a1d78564 4380 insn_insert_operand (arg->insn, operand_base, uval);
a92713e6 4381 return TRUE;
a1d78564
RS
4382}
4383
4384/* OP_PCREL matcher. The caller chooses the relocation type. */
4385
a92713e6
RS
4386static bfd_boolean
4387match_pcrel_operand (struct mips_arg_info *arg)
a1d78564 4388{
a92713e6
RS
4389 bfd_reloc_code_real_type r[3];
4390
4391 return match_expression (arg, &offset_expr, r) && r[0] == BFD_RELOC_UNUSED;
a1d78564
RS
4392}
4393
4394/* OP_PERF_REG matcher. */
4395
a92713e6 4396static bfd_boolean
a1d78564 4397match_perf_reg_operand (struct mips_arg_info *arg,
a92713e6 4398 const struct mips_operand *operand)
a1d78564
RS
4399{
4400 offsetT sval;
4401
a92713e6
RS
4402 if (!match_const_int (arg, &sval, 0))
4403 return FALSE;
a1d78564
RS
4404
4405 if (sval != 0
4406 && (sval != 1
4407 || (mips_opts.arch == CPU_R5900
4408 && (strcmp (arg->insn->insn_mo->name, "mfps") == 0
4409 || strcmp (arg->insn->insn_mo->name, "mtps") == 0))))
4410 {
4411 if (arg->soft_match)
a92713e6 4412 return FALSE;
a1d78564
RS
4413 as_bad (_("Invalid performance register (%ld)"), (unsigned long) sval);
4414 }
4415
4416 insn_insert_operand (arg->insn, operand, sval);
a92713e6 4417 return TRUE;
a1d78564
RS
4418}
4419
4420/* OP_ADDIUSP matcher. */
4421
a92713e6 4422static bfd_boolean
a1d78564 4423match_addiusp_operand (struct mips_arg_info *arg,
a92713e6 4424 const struct mips_operand *operand)
a1d78564
RS
4425{
4426 offsetT sval;
4427 unsigned int uval;
4428
a92713e6
RS
4429 if (!match_const_int (arg, &sval, -256))
4430 return FALSE;
a1d78564
RS
4431
4432 if (sval % 4)
a92713e6 4433 return FALSE;
a1d78564
RS
4434
4435 sval /= 4;
4436 if (!(sval >= -258 && sval <= 257) || (sval >= -2 && sval <= 1))
a92713e6 4437 return FALSE;
a1d78564
RS
4438
4439 uval = (unsigned int) sval;
4440 uval = ((uval >> 1) & ~0xff) | (uval & 0xff);
4441 insn_insert_operand (arg->insn, operand, uval);
a92713e6 4442 return TRUE;
a1d78564
RS
4443}
4444
4445/* OP_CLO_CLZ_DEST matcher. */
4446
a92713e6 4447static bfd_boolean
a1d78564 4448match_clo_clz_dest_operand (struct mips_arg_info *arg,
a92713e6 4449 const struct mips_operand *operand)
a1d78564
RS
4450{
4451 unsigned int regno;
4452
a92713e6
RS
4453 if (!match_reg (arg, OP_REG_GP, &regno))
4454 return FALSE;
a1d78564 4455
a1d78564 4456 insn_insert_operand (arg->insn, operand, regno | (regno << 5));
a92713e6 4457 return TRUE;
a1d78564
RS
4458}
4459
4460/* OP_LWM_SWM_LIST matcher. */
4461
a92713e6 4462static bfd_boolean
a1d78564 4463match_lwm_swm_list_operand (struct mips_arg_info *arg,
a92713e6 4464 const struct mips_operand *operand)
a1d78564 4465{
a92713e6
RS
4466 unsigned int reglist, sregs, ra, regno1, regno2;
4467 struct mips_arg_info reset;
a1d78564 4468
a92713e6
RS
4469 reglist = 0;
4470 if (!match_reg_range (arg, OP_REG_GP, &regno1, &regno2))
4471 return FALSE;
4472 do
4473 {
4474 if (regno2 == FP && regno1 >= S0 && regno1 <= S7)
4475 {
4476 reglist |= 1 << FP;
4477 regno2 = S7;
4478 }
4479 reglist |= ((1U << regno2 << 1) - 1) & -(1U << regno1);
4480 reset = *arg;
4481 }
4482 while (match_char (arg, ',')
4483 && match_reg_range (arg, OP_REG_GP, &regno1, &regno2));
4484 *arg = reset;
a1d78564
RS
4485
4486 if (operand->size == 2)
4487 {
4488 /* The list must include both ra and s0-sN, for 0 <= N <= 3. E.g.:
4489
4490 s0, ra
4491 s0, s1, ra, s2, s3
4492 s0-s2, ra
4493
4494 and any permutations of these. */
4495 if ((reglist & 0xfff1ffff) != 0x80010000)
a92713e6 4496 return FALSE;
a1d78564
RS
4497
4498 sregs = (reglist >> 17) & 7;
4499 ra = 0;
4500 }
4501 else
4502 {
4503 /* The list must include at least one of ra and s0-sN,
4504 for 0 <= N <= 8. (Note that there is a gap between s7 and s8,
4505 which are $23 and $30 respectively.) E.g.:
4506
4507 ra
4508 s0
4509 ra, s0, s1, s2
4510 s0-s8
4511 s0-s5, ra
4512
4513 and any permutations of these. */
4514 if ((reglist & 0x3f00ffff) != 0)
a92713e6 4515 return FALSE;
a1d78564
RS
4516
4517 ra = (reglist >> 27) & 0x10;
4518 sregs = ((reglist >> 22) & 0x100) | ((reglist >> 16) & 0xff);
4519 }
4520 sregs += 1;
4521 if ((sregs & -sregs) != sregs)
a92713e6 4522 return FALSE;
a1d78564
RS
4523
4524 insn_insert_operand (arg->insn, operand, (ffs (sregs) - 1) | ra);
a92713e6 4525 return TRUE;
a1d78564
RS
4526}
4527
364215c8
RS
4528/* OP_ENTRY_EXIT_LIST matcher. */
4529
a92713e6 4530static unsigned int
364215c8 4531match_entry_exit_operand (struct mips_arg_info *arg,
a92713e6 4532 const struct mips_operand *operand)
364215c8
RS
4533{
4534 unsigned int mask;
4535 bfd_boolean is_exit;
4536
4537 /* The format is the same for both ENTRY and EXIT, but the constraints
4538 are different. */
4539 is_exit = strcmp (arg->insn->insn_mo->name, "exit") == 0;
4540 mask = (is_exit ? 7 << 3 : 0);
a92713e6 4541 do
364215c8
RS
4542 {
4543 unsigned int regno1, regno2;
4544 bfd_boolean is_freg;
4545
a92713e6 4546 if (match_reg_range (arg, OP_REG_GP, &regno1, &regno2))
364215c8 4547 is_freg = FALSE;
a92713e6 4548 else if (match_reg_range (arg, OP_REG_FP, &regno1, &regno2))
364215c8
RS
4549 is_freg = TRUE;
4550 else
a92713e6 4551 return FALSE;
364215c8
RS
4552
4553 if (is_exit && is_freg && regno1 == 0 && regno2 < 2)
4554 {
4555 mask &= ~(7 << 3);
4556 mask |= (5 + regno2) << 3;
4557 }
4558 else if (!is_exit && regno1 == 4 && regno2 >= 4 && regno2 <= 7)
4559 mask |= (regno2 - 3) << 3;
4560 else if (regno1 == 16 && regno2 >= 16 && regno2 <= 17)
4561 mask |= (regno2 - 15) << 1;
4562 else if (regno1 == RA && regno2 == RA)
4563 mask |= 1;
4564 else
a92713e6 4565 return FALSE;
364215c8 4566 }
a92713e6
RS
4567 while (match_char (arg, ','));
4568
364215c8 4569 insn_insert_operand (arg->insn, operand, mask);
a92713e6 4570 return TRUE;
364215c8
RS
4571}
4572
4573/* OP_SAVE_RESTORE_LIST matcher. */
4574
a92713e6
RS
4575static bfd_boolean
4576match_save_restore_list_operand (struct mips_arg_info *arg)
364215c8
RS
4577{
4578 unsigned int opcode, args, statics, sregs;
4579 unsigned int num_frame_sizes, num_args, num_statics, num_sregs;
364215c8
RS
4580 offsetT frame_size;
4581 const char *error;
4582
4583 error = 0;
4584 opcode = arg->insn->insn_opcode;
4585 frame_size = 0;
4586 num_frame_sizes = 0;
4587 args = 0;
4588 statics = 0;
4589 sregs = 0;
a92713e6 4590 do
364215c8
RS
4591 {
4592 unsigned int regno1, regno2;
4593
a92713e6 4594 if (arg->token->type == OT_INTEGER)
364215c8
RS
4595 {
4596 /* Handle the frame size. */
a92713e6
RS
4597 if (!match_const_int (arg, &frame_size, 0))
4598 return FALSE;
364215c8 4599 num_frame_sizes += 1;
364215c8
RS
4600 }
4601 else
4602 {
a92713e6
RS
4603 if (!match_reg_range (arg, OP_REG_GP, &regno1, &regno2))
4604 return FALSE;
364215c8
RS
4605
4606 while (regno1 <= regno2)
4607 {
4608 if (regno1 >= 4 && regno1 <= 7)
4609 {
4610 if (num_frame_sizes == 0)
4611 /* args $a0-$a3 */
4612 args |= 1 << (regno1 - 4);
4613 else
4614 /* statics $a0-$a3 */
4615 statics |= 1 << (regno1 - 4);
4616 }
4617 else if (regno1 >= 16 && regno1 <= 23)
4618 /* $s0-$s7 */
4619 sregs |= 1 << (regno1 - 16);
4620 else if (regno1 == 30)
4621 /* $s8 */
4622 sregs |= 1 << 8;
4623 else if (regno1 == 31)
4624 /* Add $ra to insn. */
4625 opcode |= 0x40;
4626 else
a92713e6 4627 return FALSE;
364215c8
RS
4628 regno1 += 1;
4629 if (regno1 == 24)
4630 regno1 = 30;
4631 }
4632 }
364215c8 4633 }
a92713e6 4634 while (match_char (arg, ','));
364215c8
RS
4635
4636 /* Encode args/statics combination. */
4637 if (args & statics)
a92713e6 4638 return FALSE;
364215c8
RS
4639 else if (args == 0xf)
4640 /* All $a0-$a3 are args. */
4641 opcode |= MIPS16_ALL_ARGS << 16;
4642 else if (statics == 0xf)
4643 /* All $a0-$a3 are statics. */
4644 opcode |= MIPS16_ALL_STATICS << 16;
4645 else
4646 {
4647 /* Count arg registers. */
4648 num_args = 0;
4649 while (args & 0x1)
4650 {
4651 args >>= 1;
4652 num_args += 1;
4653 }
4654 if (args != 0)
a92713e6 4655 return FALSE;
364215c8
RS
4656
4657 /* Count static registers. */
4658 num_statics = 0;
4659 while (statics & 0x8)
4660 {
4661 statics = (statics << 1) & 0xf;
4662 num_statics += 1;
4663 }
4664 if (statics != 0)
a92713e6 4665 return FALSE;
364215c8
RS
4666
4667 /* Encode args/statics. */
4668 opcode |= ((num_args << 2) | num_statics) << 16;
4669 }
4670
4671 /* Encode $s0/$s1. */
4672 if (sregs & (1 << 0)) /* $s0 */
4673 opcode |= 0x20;
4674 if (sregs & (1 << 1)) /* $s1 */
4675 opcode |= 0x10;
4676 sregs >>= 2;
4677
4678 /* Encode $s2-$s8. */
4679 num_sregs = 0;
4680 while (sregs & 1)
4681 {
4682 sregs >>= 1;
4683 num_sregs += 1;
4684 }
4685 if (sregs != 0)
a92713e6 4686 return FALSE;
364215c8
RS
4687 opcode |= num_sregs << 24;
4688
4689 /* Encode frame size. */
4690 if (num_frame_sizes == 0)
4691 error = _("Missing frame size");
4692 else if (num_frame_sizes > 1)
4693 error = _("Frame size specified twice");
4694 else if ((frame_size & 7) != 0 || frame_size < 0 || frame_size > 0xff * 8)
4695 error = _("Invalid frame size");
4696 else if (frame_size != 128 || (opcode >> 16) != 0)
4697 {
4698 frame_size /= 8;
4699 opcode |= (((frame_size & 0xf0) << 16)
4700 | (frame_size & 0x0f));
4701 }
4702
4703 if (error)
4704 {
4705 if (arg->soft_match)
a92713e6 4706 return FALSE;
4a06e5a2 4707 as_bad ("%s", error);
364215c8
RS
4708 }
4709
4710 /* Finally build the instruction. */
4711 if ((opcode >> 16) != 0 || frame_size == 0)
4712 opcode |= MIPS16_EXTEND;
4713 arg->insn->insn_opcode = opcode;
a92713e6 4714 return TRUE;
364215c8
RS
4715}
4716
a1d78564
RS
4717/* OP_MDMX_IMM_REG matcher. */
4718
a92713e6 4719static bfd_boolean
a1d78564 4720match_mdmx_imm_reg_operand (struct mips_arg_info *arg,
a92713e6 4721 const struct mips_operand *operand)
a1d78564 4722{
a92713e6 4723 unsigned int regno, uval;
a1d78564
RS
4724 bfd_boolean is_qh;
4725 const struct mips_opcode *opcode;
4726
4727 /* The mips_opcode records whether this is an octobyte or quadhalf
4728 instruction. Start out with that bit in place. */
4729 opcode = arg->insn->insn_mo;
4730 uval = mips_extract_operand (operand, opcode->match);
4731 is_qh = (uval != 0);
4732
a92713e6 4733 if (arg->token->type == OT_REG || arg->token->type == OT_REG_ELEMENT)
a1d78564
RS
4734 {
4735 if ((opcode->membership & INSN_5400)
4736 && strcmp (opcode->name, "rzu.ob") == 0)
4737 {
4738 if (arg->soft_match)
a92713e6 4739 return FALSE;
a1d78564
RS
4740 as_bad (_("Operand %d of `%s' must be an immediate"),
4741 arg->argnum, opcode->name);
4742 }
4743
4744 /* Check whether this is a vector register or a broadcast of
4745 a single element. */
a92713e6 4746 if (arg->token->type == OT_REG_ELEMENT)
a1d78564 4747 {
a92713e6
RS
4748 if (!match_regno (arg, OP_REG_VEC, arg->token->u.reg_element.regno,
4749 &regno))
4750 return FALSE;
4751 if (arg->token->u.reg_element.index > (is_qh ? 3 : 7))
a1d78564
RS
4752 {
4753 if (arg->soft_match)
a92713e6 4754 return FALSE;
a1d78564 4755 as_bad (_("Invalid element selector"));
a1d78564 4756 }
a1d78564 4757 else
a92713e6 4758 uval |= arg->token->u.reg_element.index << (is_qh ? 2 : 1) << 5;
a1d78564
RS
4759 }
4760 else
4761 {
4762 /* A full vector. */
4763 if ((opcode->membership & INSN_5400)
4764 && (strcmp (opcode->name, "sll.ob") == 0
4765 || strcmp (opcode->name, "srl.ob") == 0))
4766 {
4767 if (arg->soft_match)
a92713e6 4768 return FALSE;
a1d78564
RS
4769 as_bad (_("Operand %d of `%s' must be scalar"),
4770 arg->argnum, opcode->name);
4771 }
4772
a92713e6
RS
4773 if (!match_regno (arg, OP_REG_VEC, arg->token->u.regno, &regno))
4774 return FALSE;
a1d78564
RS
4775 if (is_qh)
4776 uval |= MDMX_FMTSEL_VEC_QH << 5;
4777 else
4778 uval |= MDMX_FMTSEL_VEC_OB << 5;
4779 }
a1d78564 4780 uval |= regno;
a92713e6 4781 ++arg->token;
a1d78564
RS
4782 }
4783 else
4784 {
4785 offsetT sval;
4786
a92713e6
RS
4787 if (!match_const_int (arg, &sval, 0))
4788 return FALSE;
a1d78564
RS
4789 if (sval < 0 || sval > 31)
4790 {
4791 if (arg->soft_match)
a92713e6 4792 return FALSE;
a1d78564
RS
4793 report_bad_range (arg->insn, arg->argnum, sval, 0, 31, FALSE);
4794 }
4795 uval |= (sval & 31);
4796 if (is_qh)
4797 uval |= MDMX_FMTSEL_IMM_QH << 5;
4798 else
4799 uval |= MDMX_FMTSEL_IMM_OB << 5;
4800 }
4801 insn_insert_operand (arg->insn, operand, uval);
a92713e6 4802 return TRUE;
a1d78564
RS
4803}
4804
4805/* OP_PC matcher. */
4806
a92713e6
RS
4807static bfd_boolean
4808match_pc_operand (struct mips_arg_info *arg)
a1d78564 4809{
a92713e6
RS
4810 if (arg->token->type == OT_REG && (arg->token->u.regno & RTYPE_PC))
4811 {
4812 ++arg->token;
4813 return TRUE;
4814 }
4815 return FALSE;
a1d78564
RS
4816}
4817
4818/* OP_REPEAT_DEST_REG and OP_REPEAT_PREV_REG matcher. OTHER_REGNO is the
4819 register that we need to match. */
4820
a92713e6
RS
4821static bfd_boolean
4822match_tied_reg_operand (struct mips_arg_info *arg, unsigned int other_regno)
a1d78564
RS
4823{
4824 unsigned int regno;
4825
a92713e6 4826 return match_reg (arg, OP_REG_GP, &regno) && regno == other_regno;
a1d78564
RS
4827}
4828
89565f1b
RS
4829/* Read a floating-point constant from S for LI.S or LI.D. LENGTH is
4830 the length of the value in bytes (4 for float, 8 for double) and
4831 USING_GPRS says whether the destination is a GPR rather than an FPR.
4832
4833 Return the constant in IMM and OFFSET as follows:
4834
4835 - If the constant should be loaded via memory, set IMM to O_absent and
4836 OFFSET to the memory address.
4837
4838 - Otherwise, if the constant should be loaded into two 32-bit registers,
4839 set IMM to the O_constant to load into the high register and OFFSET
4840 to the corresponding value for the low register.
4841
4842 - Otherwise, set IMM to the full O_constant and set OFFSET to O_absent.
4843
4844 These constants only appear as the last operand in an instruction,
4845 and every instruction that accepts them in any variant accepts them
4846 in all variants. This means we don't have to worry about backing out
4847 any changes if the instruction does not match. We just match
4848 unconditionally and report an error if the constant is invalid. */
4849
a92713e6
RS
4850static bfd_boolean
4851match_float_constant (struct mips_arg_info *arg, expressionS *imm,
4852 expressionS *offset, int length, bfd_boolean using_gprs)
89565f1b 4853{
a92713e6 4854 char *p;
89565f1b
RS
4855 segT seg, new_seg;
4856 subsegT subseg;
4857 const char *newname;
a92713e6 4858 unsigned char *data;
89565f1b
RS
4859
4860 /* Where the constant is placed is based on how the MIPS assembler
4861 does things:
4862
4863 length == 4 && using_gprs -- immediate value only
4864 length == 8 && using_gprs -- .rdata or immediate value
4865 length == 4 && !using_gprs -- .lit4 or immediate value
4866 length == 8 && !using_gprs -- .lit8 or immediate value
4867
4868 The .lit4 and .lit8 sections are only used if permitted by the
4869 -G argument. */
a92713e6
RS
4870 if (arg->token->type != OT_FLOAT)
4871 return FALSE;
4872
4873 gas_assert (arg->token->u.flt.length == length);
4874 data = arg->token->u.flt.data;
4875 ++arg->token;
89565f1b
RS
4876
4877 /* Handle 32-bit constants for which an immediate value is best. */
4878 if (length == 4
4879 && (using_gprs
4880 || g_switch_value < 4
4881 || (data[0] == 0 && data[1] == 0)
4882 || (data[2] == 0 && data[3] == 0)))
4883 {
4884 imm->X_op = O_constant;
4885 if (!target_big_endian)
4886 imm->X_add_number = bfd_getl32 (data);
4887 else
4888 imm->X_add_number = bfd_getb32 (data);
4889 offset->X_op = O_absent;
a92713e6 4890 return TRUE;
89565f1b
RS
4891 }
4892
4893 /* Handle 64-bit constants for which an immediate value is best. */
4894 if (length == 8
4895 && !mips_disable_float_construction
4896 /* Constants can only be constructed in GPRs and copied
4897 to FPRs if the GPRs are at least as wide as the FPRs.
4898 Force the constant into memory if we are using 64-bit FPRs
4899 but the GPRs are only 32 bits wide. */
4900 /* ??? No longer true with the addition of MTHC1, but this
4901 is legacy code... */
4902 && (using_gprs || !(HAVE_64BIT_FPRS && HAVE_32BIT_GPRS))
4903 && ((data[0] == 0 && data[1] == 0)
4904 || (data[2] == 0 && data[3] == 0))
4905 && ((data[4] == 0 && data[5] == 0)
4906 || (data[6] == 0 && data[7] == 0)))
4907 {
4908 /* The value is simple enough to load with a couple of instructions.
4909 If using 32-bit registers, set IMM to the high order 32 bits and
4910 OFFSET to the low order 32 bits. Otherwise, set IMM to the entire
4911 64 bit constant. */
4912 if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS)
4913 {
4914 imm->X_op = O_constant;
4915 offset->X_op = O_constant;
4916 if (!target_big_endian)
4917 {
4918 imm->X_add_number = bfd_getl32 (data + 4);
4919 offset->X_add_number = bfd_getl32 (data);
4920 }
4921 else
4922 {
4923 imm->X_add_number = bfd_getb32 (data);
4924 offset->X_add_number = bfd_getb32 (data + 4);
4925 }
4926 if (offset->X_add_number == 0)
4927 offset->X_op = O_absent;
4928 }
4929 else
4930 {
4931 imm->X_op = O_constant;
4932 if (!target_big_endian)
4933 imm->X_add_number = bfd_getl64 (data);
4934 else
4935 imm->X_add_number = bfd_getb64 (data);
4936 offset->X_op = O_absent;
4937 }
a92713e6 4938 return TRUE;
89565f1b
RS
4939 }
4940
4941 /* Switch to the right section. */
4942 seg = now_seg;
4943 subseg = now_subseg;
4944 if (length == 4)
4945 {
4946 gas_assert (!using_gprs && g_switch_value >= 4);
4947 newname = ".lit4";
4948 }
4949 else
4950 {
4951 if (using_gprs || g_switch_value < 8)
4952 newname = RDATA_SECTION_NAME;
4953 else
4954 newname = ".lit8";
4955 }
4956
4957 new_seg = subseg_new (newname, (subsegT) 0);
4958 bfd_set_section_flags (stdoutput, new_seg,
4959 SEC_ALLOC | SEC_LOAD | SEC_READONLY | SEC_DATA);
4960 frag_align (length == 4 ? 2 : 3, 0, 0);
4961 if (strncmp (TARGET_OS, "elf", 3) != 0)
4962 record_alignment (new_seg, 4);
4963 else
4964 record_alignment (new_seg, length == 4 ? 2 : 3);
4965 if (seg == now_seg)
4966 as_bad (_("Can't use floating point insn in this section"));
4967
4968 /* Set the argument to the current address in the section. */
4969 imm->X_op = O_absent;
4970 offset->X_op = O_symbol;
4971 offset->X_add_symbol = symbol_temp_new_now ();
4972 offset->X_add_number = 0;
4973
4974 /* Put the floating point number into the section. */
4975 p = frag_more (length);
4976 memcpy (p, data, length);
4977
4978 /* Switch back to the original section. */
4979 subseg_set (seg, subseg);
a92713e6 4980 return TRUE;
89565f1b
RS
4981}
4982
a1d78564
RS
4983/* S is the text seen for ARG. Match it against OPERAND. Return the end
4984 of the argument text if the match is successful, otherwise return null. */
4985
a92713e6 4986static bfd_boolean
a1d78564 4987match_operand (struct mips_arg_info *arg,
a92713e6 4988 const struct mips_operand *operand)
a1d78564
RS
4989{
4990 switch (operand->type)
4991 {
4992 case OP_INT:
a92713e6 4993 return match_int_operand (arg, operand);
a1d78564
RS
4994
4995 case OP_MAPPED_INT:
a92713e6 4996 return match_mapped_int_operand (arg, operand);
a1d78564
RS
4997
4998 case OP_MSB:
a92713e6 4999 return match_msb_operand (arg, operand);
a1d78564
RS
5000
5001 case OP_REG:
a92713e6 5002 return match_reg_operand (arg, operand);
a1d78564
RS
5003
5004 case OP_REG_PAIR:
a92713e6 5005 return match_reg_pair_operand (arg, operand);
a1d78564
RS
5006
5007 case OP_PCREL:
a92713e6 5008 return match_pcrel_operand (arg);
a1d78564
RS
5009
5010 case OP_PERF_REG:
a92713e6 5011 return match_perf_reg_operand (arg, operand);
a1d78564
RS
5012
5013 case OP_ADDIUSP_INT:
a92713e6 5014 return match_addiusp_operand (arg, operand);
a1d78564
RS
5015
5016 case OP_CLO_CLZ_DEST:
a92713e6 5017 return match_clo_clz_dest_operand (arg, operand);
a1d78564
RS
5018
5019 case OP_LWM_SWM_LIST:
a92713e6 5020 return match_lwm_swm_list_operand (arg, operand);
a1d78564
RS
5021
5022 case OP_ENTRY_EXIT_LIST:
a92713e6 5023 return match_entry_exit_operand (arg, operand);
364215c8 5024
a1d78564 5025 case OP_SAVE_RESTORE_LIST:
a92713e6 5026 return match_save_restore_list_operand (arg);
a1d78564
RS
5027
5028 case OP_MDMX_IMM_REG:
a92713e6 5029 return match_mdmx_imm_reg_operand (arg, operand);
a1d78564
RS
5030
5031 case OP_REPEAT_DEST_REG:
a92713e6 5032 return match_tied_reg_operand (arg, arg->dest_regno);
a1d78564
RS
5033
5034 case OP_REPEAT_PREV_REG:
a92713e6 5035 return match_tied_reg_operand (arg, arg->last_regno);
a1d78564
RS
5036
5037 case OP_PC:
a92713e6 5038 return match_pc_operand (arg);
a1d78564
RS
5039 }
5040 abort ();
5041}
5042
5043/* ARG is the state after successfully matching an instruction.
5044 Issue any queued-up warnings. */
5045
5046static void
5047check_completed_insn (struct mips_arg_info *arg)
5048{
5049 if (arg->seen_at)
5050 {
5051 if (AT == ATREG)
5052 as_warn (_("Used $at without \".set noat\""));
5053 else
5054 as_warn (_("Used $%u with \".set at=$%u\""), AT, AT);
5055 }
5056}
a1d78564 5057
85fcb30f
RS
5058/* Return true if modifying general-purpose register REG needs a delay. */
5059
5060static bfd_boolean
5061reg_needs_delay (unsigned int reg)
5062{
5063 unsigned long prev_pinfo;
5064
5065 prev_pinfo = history[0].insn_mo->pinfo;
5066 if (!mips_opts.noreorder
5067 && (((prev_pinfo & INSN_LOAD_MEMORY_DELAY) && !gpr_interlocks)
5068 || ((prev_pinfo & INSN_LOAD_COPROC_DELAY) && !cop_interlocks))
5069 && (gpr_write_mask (&history[0]) & (1 << reg)))
5070 return TRUE;
5071
5072 return FALSE;
5073}
5074
71400594
RS
5075/* Classify an instruction according to the FIX_VR4120_* enumeration.
5076 Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected
5077 by VR4120 errata. */
4d7206a2 5078
71400594
RS
5079static unsigned int
5080classify_vr4120_insn (const char *name)
252b5132 5081{
71400594
RS
5082 if (strncmp (name, "macc", 4) == 0)
5083 return FIX_VR4120_MACC;
5084 if (strncmp (name, "dmacc", 5) == 0)
5085 return FIX_VR4120_DMACC;
5086 if (strncmp (name, "mult", 4) == 0)
5087 return FIX_VR4120_MULT;
5088 if (strncmp (name, "dmult", 5) == 0)
5089 return FIX_VR4120_DMULT;
5090 if (strstr (name, "div"))
5091 return FIX_VR4120_DIV;
5092 if (strcmp (name, "mtlo") == 0 || strcmp (name, "mthi") == 0)
5093 return FIX_VR4120_MTHILO;
5094 return NUM_FIX_VR4120_CLASSES;
5095}
252b5132 5096
ff239038
CM
5097#define INSN_ERET 0x42000018
5098#define INSN_DERET 0x4200001f
5099
71400594
RS
5100/* Return the number of instructions that must separate INSN1 and INSN2,
5101 where INSN1 is the earlier instruction. Return the worst-case value
5102 for any INSN2 if INSN2 is null. */
252b5132 5103
71400594
RS
5104static unsigned int
5105insns_between (const struct mips_cl_insn *insn1,
5106 const struct mips_cl_insn *insn2)
5107{
5108 unsigned long pinfo1, pinfo2;
4c260379 5109 unsigned int mask;
71400594 5110
85fcb30f
RS
5111 /* If INFO2 is null, pessimistically assume that all flags are set for
5112 the second instruction. */
71400594
RS
5113 pinfo1 = insn1->insn_mo->pinfo;
5114 pinfo2 = insn2 ? insn2->insn_mo->pinfo : ~0U;
252b5132 5115
71400594
RS
5116 /* For most targets, write-after-read dependencies on the HI and LO
5117 registers must be separated by at least two instructions. */
5118 if (!hilo_interlocks)
252b5132 5119 {
71400594
RS
5120 if ((pinfo1 & INSN_READ_LO) && (pinfo2 & INSN_WRITE_LO))
5121 return 2;
5122 if ((pinfo1 & INSN_READ_HI) && (pinfo2 & INSN_WRITE_HI))
5123 return 2;
5124 }
5125
5126 /* If we're working around r7000 errata, there must be two instructions
5127 between an mfhi or mflo and any instruction that uses the result. */
5128 if (mips_7000_hilo_fix
df58fc94 5129 && !mips_opts.micromips
71400594 5130 && MF_HILO_INSN (pinfo1)
85fcb30f 5131 && (insn2 == NULL || (gpr_read_mask (insn2) & gpr_write_mask (insn1))))
71400594
RS
5132 return 2;
5133
ff239038
CM
5134 /* If we're working around 24K errata, one instruction is required
5135 if an ERET or DERET is followed by a branch instruction. */
df58fc94 5136 if (mips_fix_24k && !mips_opts.micromips)
ff239038
CM
5137 {
5138 if (insn1->insn_opcode == INSN_ERET
5139 || insn1->insn_opcode == INSN_DERET)
5140 {
5141 if (insn2 == NULL
5142 || insn2->insn_opcode == INSN_ERET
5143 || insn2->insn_opcode == INSN_DERET
11625dd8 5144 || delayed_branch_p (insn2))
ff239038
CM
5145 return 1;
5146 }
5147 }
5148
71400594
RS
5149 /* If working around VR4120 errata, check for combinations that need
5150 a single intervening instruction. */
df58fc94 5151 if (mips_fix_vr4120 && !mips_opts.micromips)
71400594
RS
5152 {
5153 unsigned int class1, class2;
252b5132 5154
71400594
RS
5155 class1 = classify_vr4120_insn (insn1->insn_mo->name);
5156 if (class1 != NUM_FIX_VR4120_CLASSES && vr4120_conflicts[class1] != 0)
252b5132 5157 {
71400594
RS
5158 if (insn2 == NULL)
5159 return 1;
5160 class2 = classify_vr4120_insn (insn2->insn_mo->name);
5161 if (vr4120_conflicts[class1] & (1 << class2))
5162 return 1;
252b5132 5163 }
71400594
RS
5164 }
5165
df58fc94 5166 if (!HAVE_CODE_COMPRESSION)
71400594
RS
5167 {
5168 /* Check for GPR or coprocessor load delays. All such delays
5169 are on the RT register. */
5170 /* Itbl support may require additional care here. */
5171 if ((!gpr_interlocks && (pinfo1 & INSN_LOAD_MEMORY_DELAY))
5172 || (!cop_interlocks && (pinfo1 & INSN_LOAD_COPROC_DELAY)))
252b5132 5173 {
85fcb30f 5174 if (insn2 == NULL || (gpr_read_mask (insn2) & gpr_write_mask (insn1)))
71400594
RS
5175 return 1;
5176 }
5177
5178 /* Check for generic coprocessor hazards.
5179
5180 This case is not handled very well. There is no special
5181 knowledge of CP0 handling, and the coprocessors other than
5182 the floating point unit are not distinguished at all. */
5183 /* Itbl support may require additional care here. FIXME!
5184 Need to modify this to include knowledge about
5185 user specified delays! */
5186 else if ((!cop_interlocks && (pinfo1 & INSN_COPROC_MOVE_DELAY))
5187 || (!cop_mem_interlocks && (pinfo1 & INSN_COPROC_MEMORY_DELAY)))
5188 {
5189 /* Handle cases where INSN1 writes to a known general coprocessor
5190 register. There must be a one instruction delay before INSN2
5191 if INSN2 reads that register, otherwise no delay is needed. */
4c260379
RS
5192 mask = fpr_write_mask (insn1);
5193 if (mask != 0)
252b5132 5194 {
4c260379 5195 if (!insn2 || (mask & fpr_read_mask (insn2)) != 0)
71400594 5196 return 1;
252b5132
RH
5197 }
5198 else
5199 {
71400594
RS
5200 /* Read-after-write dependencies on the control registers
5201 require a two-instruction gap. */
5202 if ((pinfo1 & INSN_WRITE_COND_CODE)
5203 && (pinfo2 & INSN_READ_COND_CODE))
5204 return 2;
5205
5206 /* We don't know exactly what INSN1 does. If INSN2 is
5207 also a coprocessor instruction, assume there must be
5208 a one instruction gap. */
5209 if (pinfo2 & INSN_COP)
5210 return 1;
252b5132
RH
5211 }
5212 }
6b76fefe 5213
71400594
RS
5214 /* Check for read-after-write dependencies on the coprocessor
5215 control registers in cases where INSN1 does not need a general
5216 coprocessor delay. This means that INSN1 is a floating point
5217 comparison instruction. */
5218 /* Itbl support may require additional care here. */
5219 else if (!cop_interlocks
5220 && (pinfo1 & INSN_WRITE_COND_CODE)
5221 && (pinfo2 & INSN_READ_COND_CODE))
5222 return 1;
5223 }
6b76fefe 5224
71400594
RS
5225 return 0;
5226}
6b76fefe 5227
7d8e00cf
RS
5228/* Return the number of nops that would be needed to work around the
5229 VR4130 mflo/mfhi errata if instruction INSN immediately followed
932d1a1b
RS
5230 the MAX_VR4130_NOPS instructions described by HIST. Ignore hazards
5231 that are contained within the first IGNORE instructions of HIST. */
7d8e00cf
RS
5232
5233static int
932d1a1b 5234nops_for_vr4130 (int ignore, const struct mips_cl_insn *hist,
7d8e00cf
RS
5235 const struct mips_cl_insn *insn)
5236{
4c260379
RS
5237 int i, j;
5238 unsigned int mask;
7d8e00cf
RS
5239
5240 /* Check if the instruction writes to HI or LO. MTHI and MTLO
5241 are not affected by the errata. */
5242 if (insn != 0
5243 && ((insn->insn_mo->pinfo & (INSN_WRITE_HI | INSN_WRITE_LO)) == 0
5244 || strcmp (insn->insn_mo->name, "mtlo") == 0
5245 || strcmp (insn->insn_mo->name, "mthi") == 0))
5246 return 0;
5247
5248 /* Search for the first MFLO or MFHI. */
5249 for (i = 0; i < MAX_VR4130_NOPS; i++)
91d6fa6a 5250 if (MF_HILO_INSN (hist[i].insn_mo->pinfo))
7d8e00cf
RS
5251 {
5252 /* Extract the destination register. */
4c260379 5253 mask = gpr_write_mask (&hist[i]);
7d8e00cf
RS
5254
5255 /* No nops are needed if INSN reads that register. */
4c260379 5256 if (insn != NULL && (gpr_read_mask (insn) & mask) != 0)
7d8e00cf
RS
5257 return 0;
5258
5259 /* ...or if any of the intervening instructions do. */
5260 for (j = 0; j < i; j++)
4c260379 5261 if (gpr_read_mask (&hist[j]) & mask)
7d8e00cf
RS
5262 return 0;
5263
932d1a1b
RS
5264 if (i >= ignore)
5265 return MAX_VR4130_NOPS - i;
7d8e00cf
RS
5266 }
5267 return 0;
5268}
5269
15be625d
CM
5270#define BASE_REG_EQ(INSN1, INSN2) \
5271 ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \
5272 == (((INSN2) >> OP_SH_RS) & OP_MASK_RS))
5273
5274/* Return the minimum alignment for this store instruction. */
5275
5276static int
5277fix_24k_align_to (const struct mips_opcode *mo)
5278{
5279 if (strcmp (mo->name, "sh") == 0)
5280 return 2;
5281
5282 if (strcmp (mo->name, "swc1") == 0
5283 || strcmp (mo->name, "swc2") == 0
5284 || strcmp (mo->name, "sw") == 0
5285 || strcmp (mo->name, "sc") == 0
5286 || strcmp (mo->name, "s.s") == 0)
5287 return 4;
5288
5289 if (strcmp (mo->name, "sdc1") == 0
5290 || strcmp (mo->name, "sdc2") == 0
5291 || strcmp (mo->name, "s.d") == 0)
5292 return 8;
5293
5294 /* sb, swl, swr */
5295 return 1;
5296}
5297
5298struct fix_24k_store_info
5299 {
5300 /* Immediate offset, if any, for this store instruction. */
5301 short off;
5302 /* Alignment required by this store instruction. */
5303 int align_to;
5304 /* True for register offsets. */
5305 int register_offset;
5306 };
5307
5308/* Comparison function used by qsort. */
5309
5310static int
5311fix_24k_sort (const void *a, const void *b)
5312{
5313 const struct fix_24k_store_info *pos1 = a;
5314 const struct fix_24k_store_info *pos2 = b;
5315
5316 return (pos1->off - pos2->off);
5317}
5318
5319/* INSN is a store instruction. Try to record the store information
5320 in STINFO. Return false if the information isn't known. */
5321
5322static bfd_boolean
5323fix_24k_record_store_info (struct fix_24k_store_info *stinfo,
ab9794cf 5324 const struct mips_cl_insn *insn)
15be625d
CM
5325{
5326 /* The instruction must have a known offset. */
5327 if (!insn->complete_p || !strstr (insn->insn_mo->args, "o("))
5328 return FALSE;
5329
5330 stinfo->off = (insn->insn_opcode >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE;
5331 stinfo->align_to = fix_24k_align_to (insn->insn_mo);
5332 return TRUE;
5333}
5334
932d1a1b
RS
5335/* Return the number of nops that would be needed to work around the 24k
5336 "lost data on stores during refill" errata if instruction INSN
5337 immediately followed the 2 instructions described by HIST.
5338 Ignore hazards that are contained within the first IGNORE
5339 instructions of HIST.
5340
5341 Problem: The FSB (fetch store buffer) acts as an intermediate buffer
5342 for the data cache refills and store data. The following describes
5343 the scenario where the store data could be lost.
5344
5345 * A data cache miss, due to either a load or a store, causing fill
5346 data to be supplied by the memory subsystem
5347 * The first three doublewords of fill data are returned and written
5348 into the cache
5349 * A sequence of four stores occurs in consecutive cycles around the
5350 final doubleword of the fill:
5351 * Store A
5352 * Store B
5353 * Store C
5354 * Zero, One or more instructions
5355 * Store D
5356
5357 The four stores A-D must be to different doublewords of the line that
5358 is being filled. The fourth instruction in the sequence above permits
5359 the fill of the final doubleword to be transferred from the FSB into
5360 the cache. In the sequence above, the stores may be either integer
5361 (sb, sh, sw, swr, swl, sc) or coprocessor (swc1/swc2, sdc1/sdc2,
5362 swxc1, sdxc1, suxc1) stores, as long as the four stores are to
5363 different doublewords on the line. If the floating point unit is
5364 running in 1:2 mode, it is not possible to create the sequence above
5365 using only floating point store instructions.
15be625d
CM
5366
5367 In this case, the cache line being filled is incorrectly marked
5368 invalid, thereby losing the data from any store to the line that
5369 occurs between the original miss and the completion of the five
5370 cycle sequence shown above.
5371
932d1a1b 5372 The workarounds are:
15be625d 5373
932d1a1b
RS
5374 * Run the data cache in write-through mode.
5375 * Insert a non-store instruction between
5376 Store A and Store B or Store B and Store C. */
15be625d
CM
5377
5378static int
932d1a1b 5379nops_for_24k (int ignore, const struct mips_cl_insn *hist,
15be625d
CM
5380 const struct mips_cl_insn *insn)
5381{
5382 struct fix_24k_store_info pos[3];
5383 int align, i, base_offset;
5384
932d1a1b
RS
5385 if (ignore >= 2)
5386 return 0;
5387
ab9794cf
RS
5388 /* If the previous instruction wasn't a store, there's nothing to
5389 worry about. */
15be625d
CM
5390 if ((hist[0].insn_mo->pinfo & INSN_STORE_MEMORY) == 0)
5391 return 0;
5392
ab9794cf
RS
5393 /* If the instructions after the previous one are unknown, we have
5394 to assume the worst. */
5395 if (!insn)
15be625d
CM
5396 return 1;
5397
ab9794cf
RS
5398 /* Check whether we are dealing with three consecutive stores. */
5399 if ((insn->insn_mo->pinfo & INSN_STORE_MEMORY) == 0
5400 || (hist[1].insn_mo->pinfo & INSN_STORE_MEMORY) == 0)
15be625d
CM
5401 return 0;
5402
5403 /* If we don't know the relationship between the store addresses,
5404 assume the worst. */
ab9794cf 5405 if (!BASE_REG_EQ (insn->insn_opcode, hist[0].insn_opcode)
15be625d
CM
5406 || !BASE_REG_EQ (insn->insn_opcode, hist[1].insn_opcode))
5407 return 1;
5408
5409 if (!fix_24k_record_store_info (&pos[0], insn)
5410 || !fix_24k_record_store_info (&pos[1], &hist[0])
5411 || !fix_24k_record_store_info (&pos[2], &hist[1]))
5412 return 1;
5413
5414 qsort (&pos, 3, sizeof (struct fix_24k_store_info), fix_24k_sort);
5415
5416 /* Pick a value of ALIGN and X such that all offsets are adjusted by
5417 X bytes and such that the base register + X is known to be aligned
5418 to align bytes. */
5419
5420 if (((insn->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == SP)
5421 align = 8;
5422 else
5423 {
5424 align = pos[0].align_to;
5425 base_offset = pos[0].off;
5426 for (i = 1; i < 3; i++)
5427 if (align < pos[i].align_to)
5428 {
5429 align = pos[i].align_to;
5430 base_offset = pos[i].off;
5431 }
5432 for (i = 0; i < 3; i++)
5433 pos[i].off -= base_offset;
5434 }
5435
5436 pos[0].off &= ~align + 1;
5437 pos[1].off &= ~align + 1;
5438 pos[2].off &= ~align + 1;
5439
5440 /* If any two stores write to the same chunk, they also write to the
5441 same doubleword. The offsets are still sorted at this point. */
5442 if (pos[0].off == pos[1].off || pos[1].off == pos[2].off)
5443 return 0;
5444
5445 /* A range of at least 9 bytes is needed for the stores to be in
5446 non-overlapping doublewords. */
5447 if (pos[2].off - pos[0].off <= 8)
5448 return 0;
5449
5450 if (pos[2].off - pos[1].off >= 24
5451 || pos[1].off - pos[0].off >= 24
5452 || pos[2].off - pos[0].off >= 32)
5453 return 0;
5454
5455 return 1;
5456}
5457
71400594 5458/* Return the number of nops that would be needed if instruction INSN
91d6fa6a 5459 immediately followed the MAX_NOPS instructions given by HIST,
932d1a1b
RS
5460 where HIST[0] is the most recent instruction. Ignore hazards
5461 between INSN and the first IGNORE instructions in HIST.
5462
5463 If INSN is null, return the worse-case number of nops for any
5464 instruction. */
bdaaa2e1 5465
71400594 5466static int
932d1a1b 5467nops_for_insn (int ignore, const struct mips_cl_insn *hist,
71400594
RS
5468 const struct mips_cl_insn *insn)
5469{
5470 int i, nops, tmp_nops;
bdaaa2e1 5471
71400594 5472 nops = 0;
932d1a1b 5473 for (i = ignore; i < MAX_DELAY_NOPS; i++)
65b02341 5474 {
91d6fa6a 5475 tmp_nops = insns_between (hist + i, insn) - i;
65b02341
RS
5476 if (tmp_nops > nops)
5477 nops = tmp_nops;
5478 }
7d8e00cf 5479
df58fc94 5480 if (mips_fix_vr4130 && !mips_opts.micromips)
7d8e00cf 5481 {
932d1a1b 5482 tmp_nops = nops_for_vr4130 (ignore, hist, insn);
7d8e00cf
RS
5483 if (tmp_nops > nops)
5484 nops = tmp_nops;
5485 }
5486
df58fc94 5487 if (mips_fix_24k && !mips_opts.micromips)
15be625d 5488 {
932d1a1b 5489 tmp_nops = nops_for_24k (ignore, hist, insn);
15be625d
CM
5490 if (tmp_nops > nops)
5491 nops = tmp_nops;
5492 }
5493
71400594
RS
5494 return nops;
5495}
252b5132 5496
71400594 5497/* The variable arguments provide NUM_INSNS extra instructions that
91d6fa6a 5498 might be added to HIST. Return the largest number of nops that
932d1a1b
RS
5499 would be needed after the extended sequence, ignoring hazards
5500 in the first IGNORE instructions. */
252b5132 5501
71400594 5502static int
932d1a1b
RS
5503nops_for_sequence (int num_insns, int ignore,
5504 const struct mips_cl_insn *hist, ...)
71400594
RS
5505{
5506 va_list args;
5507 struct mips_cl_insn buffer[MAX_NOPS];
5508 struct mips_cl_insn *cursor;
5509 int nops;
5510
91d6fa6a 5511 va_start (args, hist);
71400594 5512 cursor = buffer + num_insns;
91d6fa6a 5513 memcpy (cursor, hist, (MAX_NOPS - num_insns) * sizeof (*cursor));
71400594
RS
5514 while (cursor > buffer)
5515 *--cursor = *va_arg (args, const struct mips_cl_insn *);
5516
932d1a1b 5517 nops = nops_for_insn (ignore, buffer, NULL);
71400594
RS
5518 va_end (args);
5519 return nops;
5520}
252b5132 5521
71400594
RS
5522/* Like nops_for_insn, but if INSN is a branch, take into account the
5523 worst-case delay for the branch target. */
252b5132 5524
71400594 5525static int
932d1a1b 5526nops_for_insn_or_target (int ignore, const struct mips_cl_insn *hist,
71400594
RS
5527 const struct mips_cl_insn *insn)
5528{
5529 int nops, tmp_nops;
60b63b72 5530
932d1a1b 5531 nops = nops_for_insn (ignore, hist, insn);
11625dd8 5532 if (delayed_branch_p (insn))
71400594 5533 {
932d1a1b 5534 tmp_nops = nops_for_sequence (2, ignore ? ignore + 2 : 0,
14fe068b 5535 hist, insn, get_delay_slot_nop (insn));
71400594
RS
5536 if (tmp_nops > nops)
5537 nops = tmp_nops;
5538 }
11625dd8 5539 else if (compact_branch_p (insn))
71400594 5540 {
932d1a1b 5541 tmp_nops = nops_for_sequence (1, ignore ? ignore + 1 : 0, hist, insn);
71400594
RS
5542 if (tmp_nops > nops)
5543 nops = tmp_nops;
5544 }
5545 return nops;
5546}
5547
c67a084a
NC
5548/* Fix NOP issue: Replace nops by "or at,at,zero". */
5549
5550static void
5551fix_loongson2f_nop (struct mips_cl_insn * ip)
5552{
df58fc94 5553 gas_assert (!HAVE_CODE_COMPRESSION);
c67a084a
NC
5554 if (strcmp (ip->insn_mo->name, "nop") == 0)
5555 ip->insn_opcode = LOONGSON2F_NOP_INSN;
5556}
5557
5558/* Fix Jump Issue: Eliminate instruction fetch from outside 256M region
5559 jr target pc &= 'hffff_ffff_cfff_ffff. */
5560
5561static void
5562fix_loongson2f_jump (struct mips_cl_insn * ip)
5563{
df58fc94 5564 gas_assert (!HAVE_CODE_COMPRESSION);
c67a084a
NC
5565 if (strcmp (ip->insn_mo->name, "j") == 0
5566 || strcmp (ip->insn_mo->name, "jr") == 0
5567 || strcmp (ip->insn_mo->name, "jalr") == 0)
5568 {
5569 int sreg;
5570 expressionS ep;
5571
5572 if (! mips_opts.at)
5573 return;
5574
df58fc94 5575 sreg = EXTRACT_OPERAND (0, RS, *ip);
c67a084a
NC
5576 if (sreg == ZERO || sreg == KT0 || sreg == KT1 || sreg == ATREG)
5577 return;
5578
5579 ep.X_op = O_constant;
5580 ep.X_add_number = 0xcfff0000;
5581 macro_build (&ep, "lui", "t,u", ATREG, BFD_RELOC_HI16);
5582 ep.X_add_number = 0xffff;
5583 macro_build (&ep, "ori", "t,r,i", ATREG, ATREG, BFD_RELOC_LO16);
5584 macro_build (NULL, "and", "d,v,t", sreg, sreg, ATREG);
5585 }
5586}
5587
5588static void
5589fix_loongson2f (struct mips_cl_insn * ip)
5590{
5591 if (mips_fix_loongson2f_nop)
5592 fix_loongson2f_nop (ip);
5593
5594 if (mips_fix_loongson2f_jump)
5595 fix_loongson2f_jump (ip);
5596}
5597
a4e06468
RS
5598/* IP is a branch that has a delay slot, and we need to fill it
5599 automatically. Return true if we can do that by swapping IP
e407c74b
NC
5600 with the previous instruction.
5601 ADDRESS_EXPR is an operand of the instruction to be used with
5602 RELOC_TYPE. */
a4e06468
RS
5603
5604static bfd_boolean
e407c74b
NC
5605can_swap_branch_p (struct mips_cl_insn *ip, expressionS *address_expr,
5606 bfd_reloc_code_real_type *reloc_type)
a4e06468 5607{
2b0c8b40 5608 unsigned long pinfo, pinfo2, prev_pinfo, prev_pinfo2;
a4e06468
RS
5609 unsigned int gpr_read, gpr_write, prev_gpr_read, prev_gpr_write;
5610
5611 /* -O2 and above is required for this optimization. */
5612 if (mips_optimize < 2)
5613 return FALSE;
5614
5615 /* If we have seen .set volatile or .set nomove, don't optimize. */
5616 if (mips_opts.nomove)
5617 return FALSE;
5618
5619 /* We can't swap if the previous instruction's position is fixed. */
5620 if (history[0].fixed_p)
5621 return FALSE;
5622
5623 /* If the previous previous insn was in a .set noreorder, we can't
5624 swap. Actually, the MIPS assembler will swap in this situation.
5625 However, gcc configured -with-gnu-as will generate code like
5626
5627 .set noreorder
5628 lw $4,XXX
5629 .set reorder
5630 INSN
5631 bne $4,$0,foo
5632
5633 in which we can not swap the bne and INSN. If gcc is not configured
5634 -with-gnu-as, it does not output the .set pseudo-ops. */
5635 if (history[1].noreorder_p)
5636 return FALSE;
5637
87333bb7
MR
5638 /* If the previous instruction had a fixup in mips16 mode, we can not swap.
5639 This means that the previous instruction was a 4-byte one anyhow. */
a4e06468
RS
5640 if (mips_opts.mips16 && history[0].fixp[0])
5641 return FALSE;
5642
5643 /* If the branch is itself the target of a branch, we can not swap.
5644 We cheat on this; all we check for is whether there is a label on
5645 this instruction. If there are any branches to anything other than
5646 a label, users must use .set noreorder. */
5647 if (seg_info (now_seg)->label_list)
5648 return FALSE;
5649
5650 /* If the previous instruction is in a variant frag other than this
2309ddf2 5651 branch's one, we cannot do the swap. This does not apply to
9301f9c3
MR
5652 MIPS16 code, which uses variant frags for different purposes. */
5653 if (!mips_opts.mips16
a4e06468
RS
5654 && history[0].frag
5655 && history[0].frag->fr_type == rs_machine_dependent)
5656 return FALSE;
5657
bcd530a7
RS
5658 /* We do not swap with instructions that cannot architecturally
5659 be placed in a branch delay slot, such as SYNC or ERET. We
5660 also refrain from swapping with a trap instruction, since it
5661 complicates trap handlers to have the trap instruction be in
5662 a delay slot. */
a4e06468 5663 prev_pinfo = history[0].insn_mo->pinfo;
bcd530a7 5664 if (prev_pinfo & INSN_NO_DELAY_SLOT)
a4e06468
RS
5665 return FALSE;
5666
5667 /* Check for conflicts between the branch and the instructions
5668 before the candidate delay slot. */
5669 if (nops_for_insn (0, history + 1, ip) > 0)
5670 return FALSE;
5671
5672 /* Check for conflicts between the swapped sequence and the
5673 target of the branch. */
5674 if (nops_for_sequence (2, 0, history + 1, ip, history) > 0)
5675 return FALSE;
5676
5677 /* If the branch reads a register that the previous
5678 instruction sets, we can not swap. */
5679 gpr_read = gpr_read_mask (ip);
5680 prev_gpr_write = gpr_write_mask (&history[0]);
5681 if (gpr_read & prev_gpr_write)
5682 return FALSE;
5683
5684 /* If the branch writes a register that the previous
5685 instruction sets, we can not swap. */
5686 gpr_write = gpr_write_mask (ip);
5687 if (gpr_write & prev_gpr_write)
5688 return FALSE;
5689
5690 /* If the branch writes a register that the previous
5691 instruction reads, we can not swap. */
5692 prev_gpr_read = gpr_read_mask (&history[0]);
5693 if (gpr_write & prev_gpr_read)
5694 return FALSE;
5695
5696 /* If one instruction sets a condition code and the
5697 other one uses a condition code, we can not swap. */
5698 pinfo = ip->insn_mo->pinfo;
5699 if ((pinfo & INSN_READ_COND_CODE)
5700 && (prev_pinfo & INSN_WRITE_COND_CODE))
5701 return FALSE;
5702 if ((pinfo & INSN_WRITE_COND_CODE)
5703 && (prev_pinfo & INSN_READ_COND_CODE))
5704 return FALSE;
5705
5706 /* If the previous instruction uses the PC, we can not swap. */
2b0c8b40 5707 prev_pinfo2 = history[0].insn_mo->pinfo2;
a4e06468
RS
5708 if (mips_opts.mips16 && (prev_pinfo & MIPS16_INSN_READ_PC))
5709 return FALSE;
2b0c8b40
MR
5710 if (mips_opts.micromips && (prev_pinfo2 & INSN2_READ_PC))
5711 return FALSE;
a4e06468 5712
df58fc94
RS
5713 /* If the previous instruction has an incorrect size for a fixed
5714 branch delay slot in microMIPS mode, we cannot swap. */
2309ddf2
MR
5715 pinfo2 = ip->insn_mo->pinfo2;
5716 if (mips_opts.micromips
5717 && (pinfo2 & INSN2_BRANCH_DELAY_16BIT)
5718 && insn_length (history) != 2)
5719 return FALSE;
5720 if (mips_opts.micromips
5721 && (pinfo2 & INSN2_BRANCH_DELAY_32BIT)
5722 && insn_length (history) != 4)
5723 return FALSE;
5724
e407c74b
NC
5725 /* On R5900 short loops need to be fixed by inserting a nop in
5726 the branch delay slots.
5727 A short loop can be terminated too early. */
5728 if (mips_opts.arch == CPU_R5900
5729 /* Check if instruction has a parameter, ignore "j $31". */
5730 && (address_expr != NULL)
5731 /* Parameter must be 16 bit. */
5732 && (*reloc_type == BFD_RELOC_16_PCREL_S2)
5733 /* Branch to same segment. */
5734 && (S_GET_SEGMENT(address_expr->X_add_symbol) == now_seg)
5735 /* Branch to same code fragment. */
5736 && (symbol_get_frag(address_expr->X_add_symbol) == frag_now)
5737 /* Can only calculate branch offset if value is known. */
5738 && symbol_constant_p(address_expr->X_add_symbol)
5739 /* Check if branch is really conditional. */
5740 && !((ip->insn_opcode & 0xffff0000) == 0x10000000 /* beq $0,$0 */
5741 || (ip->insn_opcode & 0xffff0000) == 0x04010000 /* bgez $0 */
5742 || (ip->insn_opcode & 0xffff0000) == 0x04110000)) /* bgezal $0 */
5743 {
5744 int distance;
5745 /* Check if loop is shorter than 6 instructions including
5746 branch and delay slot. */
5747 distance = frag_now_fix() - S_GET_VALUE(address_expr->X_add_symbol);
5748 if (distance <= 20)
5749 {
5750 int i;
5751 int rv;
5752
5753 rv = FALSE;
5754 /* When the loop includes branches or jumps,
5755 it is not a short loop. */
5756 for (i = 0; i < (distance / 4); i++)
5757 {
5758 if ((history[i].cleared_p)
5759 || delayed_branch_p(&history[i]))
5760 {
5761 rv = TRUE;
5762 break;
5763 }
5764 }
5765 if (rv == FALSE)
5766 {
5767 /* Insert nop after branch to fix short loop. */
5768 return FALSE;
5769 }
5770 }
5771 }
5772
a4e06468
RS
5773 return TRUE;
5774}
5775
e407c74b
NC
5776/* Decide how we should add IP to the instruction stream.
5777 ADDRESS_EXPR is an operand of the instruction to be used with
5778 RELOC_TYPE. */
a4e06468
RS
5779
5780static enum append_method
e407c74b
NC
5781get_append_method (struct mips_cl_insn *ip, expressionS *address_expr,
5782 bfd_reloc_code_real_type *reloc_type)
a4e06468
RS
5783{
5784 unsigned long pinfo;
5785
5786 /* The relaxed version of a macro sequence must be inherently
5787 hazard-free. */
5788 if (mips_relax.sequence == 2)
5789 return APPEND_ADD;
5790
5791 /* We must not dabble with instructions in a ".set norerorder" block. */
5792 if (mips_opts.noreorder)
5793 return APPEND_ADD;
5794
5795 /* Otherwise, it's our responsibility to fill branch delay slots. */
11625dd8 5796 if (delayed_branch_p (ip))
a4e06468 5797 {
e407c74b
NC
5798 if (!branch_likely_p (ip)
5799 && can_swap_branch_p (ip, address_expr, reloc_type))
a4e06468
RS
5800 return APPEND_SWAP;
5801
11625dd8 5802 pinfo = ip->insn_mo->pinfo;
a4e06468
RS
5803 if (mips_opts.mips16
5804 && ISA_SUPPORTS_MIPS16E
a4e06468
RS
5805 && (pinfo & (MIPS16_INSN_READ_X | MIPS16_INSN_READ_31)))
5806 return APPEND_ADD_COMPACT;
5807
5808 return APPEND_ADD_WITH_NOP;
5809 }
5810
a4e06468
RS
5811 return APPEND_ADD;
5812}
5813
ceb94aa5
RS
5814/* IP is a MIPS16 instruction whose opcode we have just changed.
5815 Point IP->insn_mo to the new opcode's definition. */
5816
5817static void
5818find_altered_mips16_opcode (struct mips_cl_insn *ip)
5819{
5820 const struct mips_opcode *mo, *end;
5821
5822 end = &mips16_opcodes[bfd_mips16_num_opcodes];
5823 for (mo = ip->insn_mo; mo < end; mo++)
5824 if ((ip->insn_opcode & mo->mask) == mo->match)
5825 {
5826 ip->insn_mo = mo;
5827 return;
5828 }
5829 abort ();
5830}
5831
df58fc94
RS
5832/* For microMIPS macros, we need to generate a local number label
5833 as the target of branches. */
5834#define MICROMIPS_LABEL_CHAR '\037'
5835static unsigned long micromips_target_label;
5836static char micromips_target_name[32];
5837
5838static char *
5839micromips_label_name (void)
5840{
5841 char *p = micromips_target_name;
5842 char symbol_name_temporary[24];
5843 unsigned long l;
5844 int i;
5845
5846 if (*p)
5847 return p;
5848
5849 i = 0;
5850 l = micromips_target_label;
5851#ifdef LOCAL_LABEL_PREFIX
5852 *p++ = LOCAL_LABEL_PREFIX;
5853#endif
5854 *p++ = 'L';
5855 *p++ = MICROMIPS_LABEL_CHAR;
5856 do
5857 {
5858 symbol_name_temporary[i++] = l % 10 + '0';
5859 l /= 10;
5860 }
5861 while (l != 0);
5862 while (i > 0)
5863 *p++ = symbol_name_temporary[--i];
5864 *p = '\0';
5865
5866 return micromips_target_name;
5867}
5868
5869static void
5870micromips_label_expr (expressionS *label_expr)
5871{
5872 label_expr->X_op = O_symbol;
5873 label_expr->X_add_symbol = symbol_find_or_make (micromips_label_name ());
5874 label_expr->X_add_number = 0;
5875}
5876
5877static void
5878micromips_label_inc (void)
5879{
5880 micromips_target_label++;
5881 *micromips_target_name = '\0';
5882}
5883
5884static void
5885micromips_add_label (void)
5886{
5887 symbolS *s;
5888
5889 s = colon (micromips_label_name ());
5890 micromips_label_inc ();
f3ded42a 5891 S_SET_OTHER (s, ELF_ST_SET_MICROMIPS (S_GET_OTHER (s)));
df58fc94
RS
5892}
5893
5894/* If assembling microMIPS code, then return the microMIPS reloc
5895 corresponding to the requested one if any. Otherwise return
5896 the reloc unchanged. */
5897
5898static bfd_reloc_code_real_type
5899micromips_map_reloc (bfd_reloc_code_real_type reloc)
5900{
5901 static const bfd_reloc_code_real_type relocs[][2] =
5902 {
5903 /* Keep sorted incrementally by the left-hand key. */
5904 { BFD_RELOC_16_PCREL_S2, BFD_RELOC_MICROMIPS_16_PCREL_S1 },
5905 { BFD_RELOC_GPREL16, BFD_RELOC_MICROMIPS_GPREL16 },
5906 { BFD_RELOC_MIPS_JMP, BFD_RELOC_MICROMIPS_JMP },
5907 { BFD_RELOC_HI16, BFD_RELOC_MICROMIPS_HI16 },
5908 { BFD_RELOC_HI16_S, BFD_RELOC_MICROMIPS_HI16_S },
5909 { BFD_RELOC_LO16, BFD_RELOC_MICROMIPS_LO16 },
5910 { BFD_RELOC_MIPS_LITERAL, BFD_RELOC_MICROMIPS_LITERAL },
5911 { BFD_RELOC_MIPS_GOT16, BFD_RELOC_MICROMIPS_GOT16 },
5912 { BFD_RELOC_MIPS_CALL16, BFD_RELOC_MICROMIPS_CALL16 },
5913 { BFD_RELOC_MIPS_GOT_HI16, BFD_RELOC_MICROMIPS_GOT_HI16 },
5914 { BFD_RELOC_MIPS_GOT_LO16, BFD_RELOC_MICROMIPS_GOT_LO16 },
5915 { BFD_RELOC_MIPS_CALL_HI16, BFD_RELOC_MICROMIPS_CALL_HI16 },
5916 { BFD_RELOC_MIPS_CALL_LO16, BFD_RELOC_MICROMIPS_CALL_LO16 },
5917 { BFD_RELOC_MIPS_SUB, BFD_RELOC_MICROMIPS_SUB },
5918 { BFD_RELOC_MIPS_GOT_PAGE, BFD_RELOC_MICROMIPS_GOT_PAGE },
5919 { BFD_RELOC_MIPS_GOT_OFST, BFD_RELOC_MICROMIPS_GOT_OFST },
5920 { BFD_RELOC_MIPS_GOT_DISP, BFD_RELOC_MICROMIPS_GOT_DISP },
5921 { BFD_RELOC_MIPS_HIGHEST, BFD_RELOC_MICROMIPS_HIGHEST },
5922 { BFD_RELOC_MIPS_HIGHER, BFD_RELOC_MICROMIPS_HIGHER },
5923 { BFD_RELOC_MIPS_SCN_DISP, BFD_RELOC_MICROMIPS_SCN_DISP },
5924 { BFD_RELOC_MIPS_TLS_GD, BFD_RELOC_MICROMIPS_TLS_GD },
5925 { BFD_RELOC_MIPS_TLS_LDM, BFD_RELOC_MICROMIPS_TLS_LDM },
5926 { BFD_RELOC_MIPS_TLS_DTPREL_HI16, BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16 },
5927 { BFD_RELOC_MIPS_TLS_DTPREL_LO16, BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16 },
5928 { BFD_RELOC_MIPS_TLS_GOTTPREL, BFD_RELOC_MICROMIPS_TLS_GOTTPREL },
5929 { BFD_RELOC_MIPS_TLS_TPREL_HI16, BFD_RELOC_MICROMIPS_TLS_TPREL_HI16 },
5930 { BFD_RELOC_MIPS_TLS_TPREL_LO16, BFD_RELOC_MICROMIPS_TLS_TPREL_LO16 }
5931 };
5932 bfd_reloc_code_real_type r;
5933 size_t i;
5934
5935 if (!mips_opts.micromips)
5936 return reloc;
5937 for (i = 0; i < ARRAY_SIZE (relocs); i++)
5938 {
5939 r = relocs[i][0];
5940 if (r > reloc)
5941 return reloc;
5942 if (r == reloc)
5943 return relocs[i][1];
5944 }
5945 return reloc;
5946}
5947
b886a2ab
RS
5948/* Try to resolve relocation RELOC against constant OPERAND at assembly time.
5949 Return true on success, storing the resolved value in RESULT. */
5950
5951static bfd_boolean
5952calculate_reloc (bfd_reloc_code_real_type reloc, offsetT operand,
5953 offsetT *result)
5954{
5955 switch (reloc)
5956 {
5957 case BFD_RELOC_MIPS_HIGHEST:
5958 case BFD_RELOC_MICROMIPS_HIGHEST:
5959 *result = ((operand + 0x800080008000ull) >> 48) & 0xffff;
5960 return TRUE;
5961
5962 case BFD_RELOC_MIPS_HIGHER:
5963 case BFD_RELOC_MICROMIPS_HIGHER:
5964 *result = ((operand + 0x80008000ull) >> 32) & 0xffff;
5965 return TRUE;
5966
5967 case BFD_RELOC_HI16_S:
5968 case BFD_RELOC_MICROMIPS_HI16_S:
5969 case BFD_RELOC_MIPS16_HI16_S:
5970 *result = ((operand + 0x8000) >> 16) & 0xffff;
5971 return TRUE;
5972
5973 case BFD_RELOC_HI16:
5974 case BFD_RELOC_MICROMIPS_HI16:
5975 case BFD_RELOC_MIPS16_HI16:
5976 *result = (operand >> 16) & 0xffff;
5977 return TRUE;
5978
5979 case BFD_RELOC_LO16:
5980 case BFD_RELOC_MICROMIPS_LO16:
5981 case BFD_RELOC_MIPS16_LO16:
5982 *result = operand & 0xffff;
5983 return TRUE;
5984
5985 case BFD_RELOC_UNUSED:
5986 *result = operand;
5987 return TRUE;
5988
5989 default:
5990 return FALSE;
5991 }
5992}
5993
71400594
RS
5994/* Output an instruction. IP is the instruction information.
5995 ADDRESS_EXPR is an operand of the instruction to be used with
df58fc94
RS
5996 RELOC_TYPE. EXPANSIONP is true if the instruction is part of
5997 a macro expansion. */
71400594
RS
5998
5999static void
6000append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
df58fc94 6001 bfd_reloc_code_real_type *reloc_type, bfd_boolean expansionp)
71400594 6002{
14fe068b 6003 unsigned long prev_pinfo2, pinfo;
71400594 6004 bfd_boolean relaxed_branch = FALSE;
a4e06468 6005 enum append_method method;
2309ddf2 6006 bfd_boolean relax32;
2b0c8b40 6007 int branch_disp;
71400594 6008
2309ddf2 6009 if (mips_fix_loongson2f && !HAVE_CODE_COMPRESSION)
c67a084a
NC
6010 fix_loongson2f (ip);
6011
738f4d98 6012 file_ase_mips16 |= mips_opts.mips16;
df58fc94 6013 file_ase_micromips |= mips_opts.micromips;
738f4d98 6014
df58fc94 6015 prev_pinfo2 = history[0].insn_mo->pinfo2;
71400594 6016 pinfo = ip->insn_mo->pinfo;
df58fc94
RS
6017
6018 if (mips_opts.micromips
6019 && !expansionp
6020 && (((prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0
6021 && micromips_insn_length (ip->insn_mo) != 2)
6022 || ((prev_pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0
6023 && micromips_insn_length (ip->insn_mo) != 4)))
6024 as_warn (_("Wrong size instruction in a %u-bit branch delay slot"),
6025 (prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 ? 16 : 32);
71400594 6026
15be625d
CM
6027 if (address_expr == NULL)
6028 ip->complete_p = 1;
b886a2ab
RS
6029 else if (reloc_type[0] <= BFD_RELOC_UNUSED
6030 && reloc_type[1] == BFD_RELOC_UNUSED
6031 && reloc_type[2] == BFD_RELOC_UNUSED
15be625d
CM
6032 && address_expr->X_op == O_constant)
6033 {
15be625d
CM
6034 switch (*reloc_type)
6035 {
15be625d 6036 case BFD_RELOC_MIPS_JMP:
df58fc94
RS
6037 {
6038 int shift;
6039
6040 shift = mips_opts.micromips ? 1 : 2;
6041 if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0)
6042 as_bad (_("jump to misaligned address (0x%lx)"),
6043 (unsigned long) address_expr->X_add_number);
6044 ip->insn_opcode |= ((address_expr->X_add_number >> shift)
6045 & 0x3ffffff);
335574df 6046 ip->complete_p = 1;
df58fc94 6047 }
15be625d
CM
6048 break;
6049
6050 case BFD_RELOC_MIPS16_JMP:
6051 if ((address_expr->X_add_number & 3) != 0)
6052 as_bad (_("jump to misaligned address (0x%lx)"),
6053 (unsigned long) address_expr->X_add_number);
6054 ip->insn_opcode |=
6055 (((address_expr->X_add_number & 0x7c0000) << 3)
6056 | ((address_expr->X_add_number & 0xf800000) >> 7)
6057 | ((address_expr->X_add_number & 0x3fffc) >> 2));
335574df 6058 ip->complete_p = 1;
15be625d
CM
6059 break;
6060
6061 case BFD_RELOC_16_PCREL_S2:
df58fc94
RS
6062 {
6063 int shift;
6064
6065 shift = mips_opts.micromips ? 1 : 2;
6066 if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0)
6067 as_bad (_("branch to misaligned address (0x%lx)"),
6068 (unsigned long) address_expr->X_add_number);
6069 if (!mips_relax_branch)
6070 {
6071 if ((address_expr->X_add_number + (1 << (shift + 15)))
6072 & ~((1 << (shift + 16)) - 1))
6073 as_bad (_("branch address range overflow (0x%lx)"),
6074 (unsigned long) address_expr->X_add_number);
6075 ip->insn_opcode |= ((address_expr->X_add_number >> shift)
6076 & 0xffff);
6077 }
df58fc94 6078 }
15be625d
CM
6079 break;
6080
6081 default:
b886a2ab
RS
6082 {
6083 offsetT value;
6084
6085 if (calculate_reloc (*reloc_type, address_expr->X_add_number,
6086 &value))
6087 {
6088 ip->insn_opcode |= value & 0xffff;
6089 ip->complete_p = 1;
6090 }
6091 }
6092 break;
6093 }
15be625d
CM
6094 }
6095
71400594
RS
6096 if (mips_relax.sequence != 2 && !mips_opts.noreorder)
6097 {
6098 /* There are a lot of optimizations we could do that we don't.
6099 In particular, we do not, in general, reorder instructions.
6100 If you use gcc with optimization, it will reorder
6101 instructions and generally do much more optimization then we
6102 do here; repeating all that work in the assembler would only
6103 benefit hand written assembly code, and does not seem worth
6104 it. */
6105 int nops = (mips_optimize == 0
932d1a1b
RS
6106 ? nops_for_insn (0, history, NULL)
6107 : nops_for_insn_or_target (0, history, ip));
71400594 6108 if (nops > 0)
252b5132
RH
6109 {
6110 fragS *old_frag;
6111 unsigned long old_frag_offset;
6112 int i;
252b5132
RH
6113
6114 old_frag = frag_now;
6115 old_frag_offset = frag_now_fix ();
6116
6117 for (i = 0; i < nops; i++)
14fe068b
RS
6118 add_fixed_insn (NOP_INSN);
6119 insert_into_history (0, nops, NOP_INSN);
252b5132
RH
6120
6121 if (listing)
6122 {
6123 listing_prev_line ();
6124 /* We may be at the start of a variant frag. In case we
6125 are, make sure there is enough space for the frag
6126 after the frags created by listing_prev_line. The
6127 argument to frag_grow here must be at least as large
6128 as the argument to all other calls to frag_grow in
6129 this file. We don't have to worry about being in the
6130 middle of a variant frag, because the variants insert
6131 all needed nop instructions themselves. */
6132 frag_grow (40);
6133 }
6134
462427c4 6135 mips_move_text_labels ();
252b5132
RH
6136
6137#ifndef NO_ECOFF_DEBUGGING
6138 if (ECOFF_DEBUGGING)
6139 ecoff_fix_loc (old_frag, old_frag_offset);
6140#endif
6141 }
71400594
RS
6142 }
6143 else if (mips_relax.sequence != 2 && prev_nop_frag != NULL)
6144 {
932d1a1b
RS
6145 int nops;
6146
6147 /* Work out how many nops in prev_nop_frag are needed by IP,
6148 ignoring hazards generated by the first prev_nop_frag_since
6149 instructions. */
6150 nops = nops_for_insn_or_target (prev_nop_frag_since, history, ip);
9c2799c2 6151 gas_assert (nops <= prev_nop_frag_holds);
252b5132 6152
71400594
RS
6153 /* Enforce NOPS as a minimum. */
6154 if (nops > prev_nop_frag_required)
6155 prev_nop_frag_required = nops;
252b5132 6156
71400594
RS
6157 if (prev_nop_frag_holds == prev_nop_frag_required)
6158 {
6159 /* Settle for the current number of nops. Update the history
6160 accordingly (for the benefit of any future .set reorder code). */
6161 prev_nop_frag = NULL;
6162 insert_into_history (prev_nop_frag_since,
6163 prev_nop_frag_holds, NOP_INSN);
6164 }
6165 else
6166 {
6167 /* Allow this instruction to replace one of the nops that was
6168 tentatively added to prev_nop_frag. */
df58fc94 6169 prev_nop_frag->fr_fix -= NOP_INSN_SIZE;
71400594
RS
6170 prev_nop_frag_holds--;
6171 prev_nop_frag_since++;
252b5132
RH
6172 }
6173 }
6174
e407c74b 6175 method = get_append_method (ip, address_expr, reloc_type);
2b0c8b40 6176 branch_disp = method == APPEND_SWAP ? insn_length (history) : 0;
a4e06468 6177
e410add4
RS
6178 dwarf2_emit_insn (0);
6179 /* We want MIPS16 and microMIPS debug info to use ISA-encoded addresses,
6180 so "move" the instruction address accordingly.
6181
6182 Also, it doesn't seem appropriate for the assembler to reorder .loc
6183 entries. If this instruction is a branch that we are going to swap
6184 with the previous instruction, the two instructions should be
6185 treated as a unit, and the debug information for both instructions
6186 should refer to the start of the branch sequence. Using the
6187 current position is certainly wrong when swapping a 32-bit branch
6188 and a 16-bit delay slot, since the current position would then be
6189 in the middle of a branch. */
6190 dwarf2_move_insn ((HAVE_CODE_COMPRESSION ? 1 : 0) - branch_disp);
58e2ea4d 6191
df58fc94
RS
6192 relax32 = (mips_relax_branch
6193 /* Don't try branch relaxation within .set nomacro, or within
6194 .set noat if we use $at for PIC computations. If it turns
6195 out that the branch was out-of-range, we'll get an error. */
6196 && !mips_opts.warn_about_macros
6197 && (mips_opts.at || mips_pic == NO_PIC)
3bf0dbfb
MR
6198 /* Don't relax BPOSGE32/64 or BC1ANY2T/F and BC1ANY4T/F
6199 as they have no complementing branches. */
6200 && !(ip->insn_mo->ase & (ASE_MIPS3D | ASE_DSP64 | ASE_DSP)));
df58fc94
RS
6201
6202 if (!HAVE_CODE_COMPRESSION
6203 && address_expr
6204 && relax32
0b25d3e6 6205 && *reloc_type == BFD_RELOC_16_PCREL_S2
11625dd8 6206 && delayed_branch_p (ip))
4a6a3df4 6207 {
895921c9 6208 relaxed_branch = TRUE;
1e915849
RS
6209 add_relaxed_insn (ip, (relaxed_branch_length
6210 (NULL, NULL,
11625dd8
RS
6211 uncond_branch_p (ip) ? -1
6212 : branch_likely_p (ip) ? 1
1e915849
RS
6213 : 0)), 4,
6214 RELAX_BRANCH_ENCODE
66b3e8da 6215 (AT,
11625dd8
RS
6216 uncond_branch_p (ip),
6217 branch_likely_p (ip),
1e915849
RS
6218 pinfo & INSN_WRITE_GPR_31,
6219 0),
6220 address_expr->X_add_symbol,
6221 address_expr->X_add_number);
4a6a3df4
AO
6222 *reloc_type = BFD_RELOC_UNUSED;
6223 }
df58fc94
RS
6224 else if (mips_opts.micromips
6225 && address_expr
6226 && ((relax32 && *reloc_type == BFD_RELOC_16_PCREL_S2)
6227 || *reloc_type > BFD_RELOC_UNUSED)
40209cad
MR
6228 && (delayed_branch_p (ip) || compact_branch_p (ip))
6229 /* Don't try branch relaxation when users specify
6230 16-bit/32-bit instructions. */
6231 && !forced_insn_length)
df58fc94
RS
6232 {
6233 bfd_boolean relax16 = *reloc_type > BFD_RELOC_UNUSED;
6234 int type = relax16 ? *reloc_type - BFD_RELOC_UNUSED : 0;
11625dd8
RS
6235 int uncond = uncond_branch_p (ip) ? -1 : 0;
6236 int compact = compact_branch_p (ip);
df58fc94
RS
6237 int al = pinfo & INSN_WRITE_GPR_31;
6238 int length32;
6239
6240 gas_assert (address_expr != NULL);
6241 gas_assert (!mips_relax.sequence);
6242
2b0c8b40 6243 relaxed_branch = TRUE;
df58fc94
RS
6244 length32 = relaxed_micromips_32bit_branch_length (NULL, NULL, uncond);
6245 add_relaxed_insn (ip, relax32 ? length32 : 4, relax16 ? 2 : 4,
40209cad
MR
6246 RELAX_MICROMIPS_ENCODE (type, AT, uncond, compact, al,
6247 relax32, 0, 0),
df58fc94
RS
6248 address_expr->X_add_symbol,
6249 address_expr->X_add_number);
6250 *reloc_type = BFD_RELOC_UNUSED;
6251 }
6252 else if (mips_opts.mips16 && *reloc_type > BFD_RELOC_UNUSED)
252b5132
RH
6253 {
6254 /* We need to set up a variant frag. */
df58fc94 6255 gas_assert (address_expr != NULL);
1e915849
RS
6256 add_relaxed_insn (ip, 4, 0,
6257 RELAX_MIPS16_ENCODE
6258 (*reloc_type - BFD_RELOC_UNUSED,
df58fc94 6259 forced_insn_length == 2, forced_insn_length == 4,
11625dd8 6260 delayed_branch_p (&history[0]),
1e915849
RS
6261 history[0].mips16_absolute_jump_p),
6262 make_expr_symbol (address_expr), 0);
252b5132 6263 }
5c04167a 6264 else if (mips_opts.mips16 && insn_length (ip) == 2)
9497f5ac 6265 {
11625dd8 6266 if (!delayed_branch_p (ip))
b8ee1a6e
DU
6267 /* Make sure there is enough room to swap this instruction with
6268 a following jump instruction. */
6269 frag_grow (6);
1e915849 6270 add_fixed_insn (ip);
252b5132
RH
6271 }
6272 else
6273 {
6274 if (mips_opts.mips16
6275 && mips_opts.noreorder
11625dd8 6276 && delayed_branch_p (&history[0]))
252b5132
RH
6277 as_warn (_("extended instruction in delay slot"));
6278
4d7206a2
RS
6279 if (mips_relax.sequence)
6280 {
6281 /* If we've reached the end of this frag, turn it into a variant
6282 frag and record the information for the instructions we've
6283 written so far. */
6284 if (frag_room () < 4)
6285 relax_close_frag ();
df58fc94 6286 mips_relax.sizes[mips_relax.sequence - 1] += insn_length (ip);
4d7206a2
RS
6287 }
6288
584892a6 6289 if (mips_relax.sequence != 2)
df58fc94
RS
6290 {
6291 if (mips_macro_warning.first_insn_sizes[0] == 0)
6292 mips_macro_warning.first_insn_sizes[0] = insn_length (ip);
6293 mips_macro_warning.sizes[0] += insn_length (ip);
6294 mips_macro_warning.insns[0]++;
6295 }
584892a6 6296 if (mips_relax.sequence != 1)
df58fc94
RS
6297 {
6298 if (mips_macro_warning.first_insn_sizes[1] == 0)
6299 mips_macro_warning.first_insn_sizes[1] = insn_length (ip);
6300 mips_macro_warning.sizes[1] += insn_length (ip);
6301 mips_macro_warning.insns[1]++;
6302 }
584892a6 6303
1e915849
RS
6304 if (mips_opts.mips16)
6305 {
6306 ip->fixed_p = 1;
6307 ip->mips16_absolute_jump_p = (*reloc_type == BFD_RELOC_MIPS16_JMP);
6308 }
6309 add_fixed_insn (ip);
252b5132
RH
6310 }
6311
9fe77896 6312 if (!ip->complete_p && *reloc_type < BFD_RELOC_UNUSED)
252b5132 6313 {
df58fc94 6314 bfd_reloc_code_real_type final_type[3];
2309ddf2 6315 reloc_howto_type *howto0;
9fe77896
RS
6316 reloc_howto_type *howto;
6317 int i;
34ce925e 6318
df58fc94
RS
6319 /* Perform any necessary conversion to microMIPS relocations
6320 and find out how many relocations there actually are. */
6321 for (i = 0; i < 3 && reloc_type[i] != BFD_RELOC_UNUSED; i++)
6322 final_type[i] = micromips_map_reloc (reloc_type[i]);
6323
9fe77896
RS
6324 /* In a compound relocation, it is the final (outermost)
6325 operator that determines the relocated field. */
2309ddf2 6326 howto = howto0 = bfd_reloc_type_lookup (stdoutput, final_type[i - 1]);
e8044f35
RS
6327 if (!howto)
6328 abort ();
2309ddf2
MR
6329
6330 if (i > 1)
6331 howto0 = bfd_reloc_type_lookup (stdoutput, final_type[0]);
9fe77896
RS
6332 ip->fixp[0] = fix_new_exp (ip->frag, ip->where,
6333 bfd_get_reloc_size (howto),
6334 address_expr,
2309ddf2
MR
6335 howto0 && howto0->pc_relative,
6336 final_type[0]);
9fe77896
RS
6337
6338 /* Tag symbols that have a R_MIPS16_26 relocation against them. */
2309ddf2 6339 if (final_type[0] == BFD_RELOC_MIPS16_JMP && ip->fixp[0]->fx_addsy)
9fe77896
RS
6340 *symbol_get_tc (ip->fixp[0]->fx_addsy) = 1;
6341
6342 /* These relocations can have an addend that won't fit in
6343 4 octets for 64bit assembly. */
6344 if (HAVE_64BIT_GPRS
6345 && ! howto->partial_inplace
6346 && (reloc_type[0] == BFD_RELOC_16
6347 || reloc_type[0] == BFD_RELOC_32
6348 || reloc_type[0] == BFD_RELOC_MIPS_JMP
6349 || reloc_type[0] == BFD_RELOC_GPREL16
6350 || reloc_type[0] == BFD_RELOC_MIPS_LITERAL
6351 || reloc_type[0] == BFD_RELOC_GPREL32
6352 || reloc_type[0] == BFD_RELOC_64
6353 || reloc_type[0] == BFD_RELOC_CTOR
6354 || reloc_type[0] == BFD_RELOC_MIPS_SUB
6355 || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST
6356 || reloc_type[0] == BFD_RELOC_MIPS_HIGHER
6357 || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP
6358 || reloc_type[0] == BFD_RELOC_MIPS_REL16
6359 || reloc_type[0] == BFD_RELOC_MIPS_RELGOT
6360 || reloc_type[0] == BFD_RELOC_MIPS16_GPREL
6361 || hi16_reloc_p (reloc_type[0])
6362 || lo16_reloc_p (reloc_type[0])))
6363 ip->fixp[0]->fx_no_overflow = 1;
6364
ddaf2c41
MR
6365 /* These relocations can have an addend that won't fit in 2 octets. */
6366 if (reloc_type[0] == BFD_RELOC_MICROMIPS_7_PCREL_S1
6367 || reloc_type[0] == BFD_RELOC_MICROMIPS_10_PCREL_S1)
6368 ip->fixp[0]->fx_no_overflow = 1;
6369
9fe77896
RS
6370 if (mips_relax.sequence)
6371 {
6372 if (mips_relax.first_fixup == 0)
6373 mips_relax.first_fixup = ip->fixp[0];
6374 }
6375 else if (reloc_needs_lo_p (*reloc_type))
6376 {
6377 struct mips_hi_fixup *hi_fixup;
6378
6379 /* Reuse the last entry if it already has a matching %lo. */
6380 hi_fixup = mips_hi_fixup_list;
6381 if (hi_fixup == 0
6382 || !fixup_has_matching_lo_p (hi_fixup->fixp))
4d7206a2 6383 {
9fe77896
RS
6384 hi_fixup = ((struct mips_hi_fixup *)
6385 xmalloc (sizeof (struct mips_hi_fixup)));
6386 hi_fixup->next = mips_hi_fixup_list;
6387 mips_hi_fixup_list = hi_fixup;
4d7206a2 6388 }
9fe77896
RS
6389 hi_fixup->fixp = ip->fixp[0];
6390 hi_fixup->seg = now_seg;
6391 }
252b5132 6392
9fe77896
RS
6393 /* Add fixups for the second and third relocations, if given.
6394 Note that the ABI allows the second relocation to be
6395 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
6396 moment we only use RSS_UNDEF, but we could add support
6397 for the others if it ever becomes necessary. */
6398 for (i = 1; i < 3; i++)
6399 if (reloc_type[i] != BFD_RELOC_UNUSED)
6400 {
6401 ip->fixp[i] = fix_new (ip->frag, ip->where,
6402 ip->fixp[0]->fx_size, NULL, 0,
df58fc94 6403 FALSE, final_type[i]);
f6688943 6404
9fe77896
RS
6405 /* Use fx_tcbit to mark compound relocs. */
6406 ip->fixp[0]->fx_tcbit = 1;
6407 ip->fixp[i]->fx_tcbit = 1;
6408 }
252b5132 6409 }
1e915849 6410 install_insn (ip);
252b5132
RH
6411
6412 /* Update the register mask information. */
4c260379
RS
6413 mips_gprmask |= gpr_read_mask (ip) | gpr_write_mask (ip);
6414 mips_cprmask[1] |= fpr_read_mask (ip) | fpr_write_mask (ip);
252b5132 6415
a4e06468 6416 switch (method)
252b5132 6417 {
a4e06468
RS
6418 case APPEND_ADD:
6419 insert_into_history (0, 1, ip);
6420 break;
6421
6422 case APPEND_ADD_WITH_NOP:
14fe068b
RS
6423 {
6424 struct mips_cl_insn *nop;
6425
6426 insert_into_history (0, 1, ip);
6427 nop = get_delay_slot_nop (ip);
6428 add_fixed_insn (nop);
6429 insert_into_history (0, 1, nop);
6430 if (mips_relax.sequence)
6431 mips_relax.sizes[mips_relax.sequence - 1] += insn_length (nop);
6432 }
a4e06468
RS
6433 break;
6434
6435 case APPEND_ADD_COMPACT:
6436 /* Convert MIPS16 jr/jalr into a "compact" jump. */
6437 gas_assert (mips_opts.mips16);
6438 ip->insn_opcode |= 0x0080;
6439 find_altered_mips16_opcode (ip);
6440 install_insn (ip);
6441 insert_into_history (0, 1, ip);
6442 break;
6443
6444 case APPEND_SWAP:
6445 {
6446 struct mips_cl_insn delay = history[0];
6447 if (mips_opts.mips16)
6448 {
6449 know (delay.frag == ip->frag);
6450 move_insn (ip, delay.frag, delay.where);
6451 move_insn (&delay, ip->frag, ip->where + insn_length (ip));
6452 }
464ab0e5 6453 else if (relaxed_branch || delay.frag != ip->frag)
a4e06468
RS
6454 {
6455 /* Add the delay slot instruction to the end of the
6456 current frag and shrink the fixed part of the
6457 original frag. If the branch occupies the tail of
6458 the latter, move it backwards to cover the gap. */
2b0c8b40 6459 delay.frag->fr_fix -= branch_disp;
a4e06468 6460 if (delay.frag == ip->frag)
2b0c8b40 6461 move_insn (ip, ip->frag, ip->where - branch_disp);
a4e06468
RS
6462 add_fixed_insn (&delay);
6463 }
6464 else
6465 {
2b0c8b40
MR
6466 move_insn (&delay, ip->frag,
6467 ip->where - branch_disp + insn_length (ip));
a4e06468
RS
6468 move_insn (ip, history[0].frag, history[0].where);
6469 }
6470 history[0] = *ip;
6471 delay.fixed_p = 1;
6472 insert_into_history (0, 1, &delay);
6473 }
6474 break;
252b5132
RH
6475 }
6476
13408f1e 6477 /* If we have just completed an unconditional branch, clear the history. */
11625dd8
RS
6478 if ((delayed_branch_p (&history[1]) && uncond_branch_p (&history[1]))
6479 || (compact_branch_p (&history[0]) && uncond_branch_p (&history[0])))
e407c74b
NC
6480 {
6481 unsigned int i;
6482
79850f26 6483 mips_no_prev_insn ();
13408f1e 6484
e407c74b 6485 for (i = 0; i < ARRAY_SIZE (history); i++)
79850f26 6486 history[i].cleared_p = 1;
e407c74b
NC
6487 }
6488
df58fc94
RS
6489 /* We need to emit a label at the end of branch-likely macros. */
6490 if (emit_branch_likely_macro)
6491 {
6492 emit_branch_likely_macro = FALSE;
6493 micromips_add_label ();
6494 }
6495
252b5132
RH
6496 /* We just output an insn, so the next one doesn't have a label. */
6497 mips_clear_insn_labels ();
252b5132
RH
6498}
6499
e407c74b
NC
6500/* Forget that there was any previous instruction or label.
6501 When BRANCH is true, the branch history is also flushed. */
252b5132
RH
6502
6503static void
7d10b47d 6504mips_no_prev_insn (void)
252b5132 6505{
7d10b47d
RS
6506 prev_nop_frag = NULL;
6507 insert_into_history (0, ARRAY_SIZE (history), NOP_INSN);
252b5132
RH
6508 mips_clear_insn_labels ();
6509}
6510
7d10b47d
RS
6511/* This function must be called before we emit something other than
6512 instructions. It is like mips_no_prev_insn except that it inserts
6513 any NOPS that might be needed by previous instructions. */
252b5132 6514
7d10b47d
RS
6515void
6516mips_emit_delays (void)
252b5132
RH
6517{
6518 if (! mips_opts.noreorder)
6519 {
932d1a1b 6520 int nops = nops_for_insn (0, history, NULL);
252b5132
RH
6521 if (nops > 0)
6522 {
7d10b47d
RS
6523 while (nops-- > 0)
6524 add_fixed_insn (NOP_INSN);
462427c4 6525 mips_move_text_labels ();
7d10b47d
RS
6526 }
6527 }
6528 mips_no_prev_insn ();
6529}
6530
6531/* Start a (possibly nested) noreorder block. */
6532
6533static void
6534start_noreorder (void)
6535{
6536 if (mips_opts.noreorder == 0)
6537 {
6538 unsigned int i;
6539 int nops;
6540
6541 /* None of the instructions before the .set noreorder can be moved. */
6542 for (i = 0; i < ARRAY_SIZE (history); i++)
6543 history[i].fixed_p = 1;
6544
6545 /* Insert any nops that might be needed between the .set noreorder
6546 block and the previous instructions. We will later remove any
6547 nops that turn out not to be needed. */
932d1a1b 6548 nops = nops_for_insn (0, history, NULL);
7d10b47d
RS
6549 if (nops > 0)
6550 {
6551 if (mips_optimize != 0)
252b5132
RH
6552 {
6553 /* Record the frag which holds the nop instructions, so
6554 that we can remove them if we don't need them. */
df58fc94 6555 frag_grow (nops * NOP_INSN_SIZE);
252b5132
RH
6556 prev_nop_frag = frag_now;
6557 prev_nop_frag_holds = nops;
6558 prev_nop_frag_required = 0;
6559 prev_nop_frag_since = 0;
6560 }
6561
6562 for (; nops > 0; --nops)
1e915849 6563 add_fixed_insn (NOP_INSN);
252b5132 6564
7d10b47d
RS
6565 /* Move on to a new frag, so that it is safe to simply
6566 decrease the size of prev_nop_frag. */
6567 frag_wane (frag_now);
6568 frag_new (0);
462427c4 6569 mips_move_text_labels ();
252b5132 6570 }
df58fc94 6571 mips_mark_labels ();
7d10b47d 6572 mips_clear_insn_labels ();
252b5132 6573 }
7d10b47d
RS
6574 mips_opts.noreorder++;
6575 mips_any_noreorder = 1;
6576}
252b5132 6577
7d10b47d 6578/* End a nested noreorder block. */
252b5132 6579
7d10b47d
RS
6580static void
6581end_noreorder (void)
6582{
6583 mips_opts.noreorder--;
6584 if (mips_opts.noreorder == 0 && prev_nop_frag != NULL)
6585 {
6586 /* Commit to inserting prev_nop_frag_required nops and go back to
6587 handling nop insertion the .set reorder way. */
6588 prev_nop_frag->fr_fix -= ((prev_nop_frag_holds - prev_nop_frag_required)
df58fc94 6589 * NOP_INSN_SIZE);
7d10b47d
RS
6590 insert_into_history (prev_nop_frag_since,
6591 prev_nop_frag_required, NOP_INSN);
6592 prev_nop_frag = NULL;
6593 }
252b5132
RH
6594}
6595
584892a6
RS
6596/* Set up global variables for the start of a new macro. */
6597
6598static void
6599macro_start (void)
6600{
6601 memset (&mips_macro_warning.sizes, 0, sizeof (mips_macro_warning.sizes));
df58fc94
RS
6602 memset (&mips_macro_warning.first_insn_sizes, 0,
6603 sizeof (mips_macro_warning.first_insn_sizes));
6604 memset (&mips_macro_warning.insns, 0, sizeof (mips_macro_warning.insns));
584892a6 6605 mips_macro_warning.delay_slot_p = (mips_opts.noreorder
11625dd8 6606 && delayed_branch_p (&history[0]));
df58fc94
RS
6607 switch (history[0].insn_mo->pinfo2
6608 & (INSN2_BRANCH_DELAY_32BIT | INSN2_BRANCH_DELAY_16BIT))
6609 {
6610 case INSN2_BRANCH_DELAY_32BIT:
6611 mips_macro_warning.delay_slot_length = 4;
6612 break;
6613 case INSN2_BRANCH_DELAY_16BIT:
6614 mips_macro_warning.delay_slot_length = 2;
6615 break;
6616 default:
6617 mips_macro_warning.delay_slot_length = 0;
6618 break;
6619 }
6620 mips_macro_warning.first_frag = NULL;
584892a6
RS
6621}
6622
df58fc94
RS
6623/* Given that a macro is longer than one instruction or of the wrong size,
6624 return the appropriate warning for it. Return null if no warning is
6625 needed. SUBTYPE is a bitmask of RELAX_DELAY_SLOT, RELAX_DELAY_SLOT_16BIT,
6626 RELAX_DELAY_SLOT_SIZE_FIRST, RELAX_DELAY_SLOT_SIZE_SECOND,
6627 and RELAX_NOMACRO. */
584892a6
RS
6628
6629static const char *
6630macro_warning (relax_substateT subtype)
6631{
6632 if (subtype & RELAX_DELAY_SLOT)
6633 return _("Macro instruction expanded into multiple instructions"
6634 " in a branch delay slot");
6635 else if (subtype & RELAX_NOMACRO)
6636 return _("Macro instruction expanded into multiple instructions");
df58fc94
RS
6637 else if (subtype & (RELAX_DELAY_SLOT_SIZE_FIRST
6638 | RELAX_DELAY_SLOT_SIZE_SECOND))
6639 return ((subtype & RELAX_DELAY_SLOT_16BIT)
6640 ? _("Macro instruction expanded into a wrong size instruction"
6641 " in a 16-bit branch delay slot")
6642 : _("Macro instruction expanded into a wrong size instruction"
6643 " in a 32-bit branch delay slot"));
584892a6
RS
6644 else
6645 return 0;
6646}
6647
6648/* Finish up a macro. Emit warnings as appropriate. */
6649
6650static void
6651macro_end (void)
6652{
df58fc94
RS
6653 /* Relaxation warning flags. */
6654 relax_substateT subtype = 0;
6655
6656 /* Check delay slot size requirements. */
6657 if (mips_macro_warning.delay_slot_length == 2)
6658 subtype |= RELAX_DELAY_SLOT_16BIT;
6659 if (mips_macro_warning.delay_slot_length != 0)
584892a6 6660 {
df58fc94
RS
6661 if (mips_macro_warning.delay_slot_length
6662 != mips_macro_warning.first_insn_sizes[0])
6663 subtype |= RELAX_DELAY_SLOT_SIZE_FIRST;
6664 if (mips_macro_warning.delay_slot_length
6665 != mips_macro_warning.first_insn_sizes[1])
6666 subtype |= RELAX_DELAY_SLOT_SIZE_SECOND;
6667 }
584892a6 6668
df58fc94
RS
6669 /* Check instruction count requirements. */
6670 if (mips_macro_warning.insns[0] > 1 || mips_macro_warning.insns[1] > 1)
6671 {
6672 if (mips_macro_warning.insns[1] > mips_macro_warning.insns[0])
584892a6
RS
6673 subtype |= RELAX_SECOND_LONGER;
6674 if (mips_opts.warn_about_macros)
6675 subtype |= RELAX_NOMACRO;
6676 if (mips_macro_warning.delay_slot_p)
6677 subtype |= RELAX_DELAY_SLOT;
df58fc94 6678 }
584892a6 6679
df58fc94
RS
6680 /* If both alternatives fail to fill a delay slot correctly,
6681 emit the warning now. */
6682 if ((subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0
6683 && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0)
6684 {
6685 relax_substateT s;
6686 const char *msg;
6687
6688 s = subtype & (RELAX_DELAY_SLOT_16BIT
6689 | RELAX_DELAY_SLOT_SIZE_FIRST
6690 | RELAX_DELAY_SLOT_SIZE_SECOND);
6691 msg = macro_warning (s);
6692 if (msg != NULL)
6693 as_warn ("%s", msg);
6694 subtype &= ~s;
6695 }
6696
6697 /* If both implementations are longer than 1 instruction, then emit the
6698 warning now. */
6699 if (mips_macro_warning.insns[0] > 1 && mips_macro_warning.insns[1] > 1)
6700 {
6701 relax_substateT s;
6702 const char *msg;
6703
6704 s = subtype & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT);
6705 msg = macro_warning (s);
6706 if (msg != NULL)
6707 as_warn ("%s", msg);
6708 subtype &= ~s;
584892a6 6709 }
df58fc94
RS
6710
6711 /* If any flags still set, then one implementation might need a warning
6712 and the other either will need one of a different kind or none at all.
6713 Pass any remaining flags over to relaxation. */
6714 if (mips_macro_warning.first_frag != NULL)
6715 mips_macro_warning.first_frag->fr_subtype |= subtype;
584892a6
RS
6716}
6717
df58fc94
RS
6718/* Instruction operand formats used in macros that vary between
6719 standard MIPS and microMIPS code. */
6720
833794fc 6721static const char * const brk_fmt[2][2] = { { "c", "c" }, { "mF", "c" } };
df58fc94
RS
6722static const char * const cop12_fmt[2] = { "E,o(b)", "E,~(b)" };
6723static const char * const jalr_fmt[2] = { "d,s", "t,s" };
6724static const char * const lui_fmt[2] = { "t,u", "s,u" };
6725static const char * const mem12_fmt[2] = { "t,o(b)", "t,~(b)" };
833794fc 6726static const char * const mfhl_fmt[2][2] = { { "d", "d" }, { "mj", "s" } };
df58fc94
RS
6727static const char * const shft_fmt[2] = { "d,w,<", "t,r,<" };
6728static const char * const trap_fmt[2] = { "s,t,q", "s,t,|" };
6729
833794fc 6730#define BRK_FMT (brk_fmt[mips_opts.micromips][mips_opts.insn32])
df58fc94
RS
6731#define COP12_FMT (cop12_fmt[mips_opts.micromips])
6732#define JALR_FMT (jalr_fmt[mips_opts.micromips])
6733#define LUI_FMT (lui_fmt[mips_opts.micromips])
6734#define MEM12_FMT (mem12_fmt[mips_opts.micromips])
833794fc 6735#define MFHL_FMT (mfhl_fmt[mips_opts.micromips][mips_opts.insn32])
df58fc94
RS
6736#define SHFT_FMT (shft_fmt[mips_opts.micromips])
6737#define TRAP_FMT (trap_fmt[mips_opts.micromips])
6738
6e1304d8
RS
6739/* Read a macro's relocation codes from *ARGS and store them in *R.
6740 The first argument in *ARGS will be either the code for a single
6741 relocation or -1 followed by the three codes that make up a
6742 composite relocation. */
6743
6744static void
6745macro_read_relocs (va_list *args, bfd_reloc_code_real_type *r)
6746{
6747 int i, next;
6748
6749 next = va_arg (*args, int);
6750 if (next >= 0)
6751 r[0] = (bfd_reloc_code_real_type) next;
6752 else
f2ae14a1
RS
6753 {
6754 for (i = 0; i < 3; i++)
6755 r[i] = (bfd_reloc_code_real_type) va_arg (*args, int);
6756 /* This function is only used for 16-bit relocation fields.
6757 To make the macro code simpler, treat an unrelocated value
6758 in the same way as BFD_RELOC_LO16. */
6759 if (r[0] == BFD_RELOC_UNUSED)
6760 r[0] = BFD_RELOC_LO16;
6761 }
6e1304d8
RS
6762}
6763
252b5132
RH
6764/* Build an instruction created by a macro expansion. This is passed
6765 a pointer to the count of instructions created so far, an
6766 expression, the name of the instruction to build, an operand format
6767 string, and corresponding arguments. */
6768
252b5132 6769static void
67c0d1eb 6770macro_build (expressionS *ep, const char *name, const char *fmt, ...)
252b5132 6771{
df58fc94 6772 const struct mips_opcode *mo = NULL;
f6688943 6773 bfd_reloc_code_real_type r[3];
df58fc94 6774 const struct mips_opcode *amo;
e077a1c8 6775 const struct mips_operand *operand;
df58fc94
RS
6776 struct hash_control *hash;
6777 struct mips_cl_insn insn;
252b5132 6778 va_list args;
e077a1c8 6779 unsigned int uval;
252b5132 6780
252b5132 6781 va_start (args, fmt);
252b5132 6782
252b5132
RH
6783 if (mips_opts.mips16)
6784 {
03ea81db 6785 mips16_macro_build (ep, name, fmt, &args);
252b5132
RH
6786 va_end (args);
6787 return;
6788 }
6789
f6688943
TS
6790 r[0] = BFD_RELOC_UNUSED;
6791 r[1] = BFD_RELOC_UNUSED;
6792 r[2] = BFD_RELOC_UNUSED;
df58fc94
RS
6793 hash = mips_opts.micromips ? micromips_op_hash : op_hash;
6794 amo = (struct mips_opcode *) hash_find (hash, name);
6795 gas_assert (amo);
6796 gas_assert (strcmp (name, amo->name) == 0);
1e915849 6797
df58fc94 6798 do
8b082fb1
TS
6799 {
6800 /* Search until we get a match for NAME. It is assumed here that
df58fc94
RS
6801 macros will never generate MDMX, MIPS-3D, or MT instructions.
6802 We try to match an instruction that fulfils the branch delay
6803 slot instruction length requirement (if any) of the previous
6804 instruction. While doing this we record the first instruction
6805 seen that matches all the other conditions and use it anyway
6806 if the requirement cannot be met; we will issue an appropriate
6807 warning later on. */
6808 if (strcmp (fmt, amo->args) == 0
6809 && amo->pinfo != INSN_MACRO
6810 && is_opcode_valid (amo)
6811 && is_size_valid (amo))
6812 {
6813 if (is_delay_slot_valid (amo))
6814 {
6815 mo = amo;
6816 break;
6817 }
6818 else if (!mo)
6819 mo = amo;
6820 }
8b082fb1 6821
df58fc94
RS
6822 ++amo;
6823 gas_assert (amo->name);
252b5132 6824 }
df58fc94 6825 while (strcmp (name, amo->name) == 0);
252b5132 6826
df58fc94 6827 gas_assert (mo);
1e915849 6828 create_insn (&insn, mo);
e077a1c8 6829 for (; *fmt; ++fmt)
252b5132 6830 {
e077a1c8 6831 switch (*fmt)
252b5132 6832 {
252b5132
RH
6833 case ',':
6834 case '(':
6835 case ')':
252b5132 6836 case 'z':
e077a1c8 6837 break;
252b5132
RH
6838
6839 case 'i':
6840 case 'j':
6e1304d8 6841 macro_read_relocs (&args, r);
9c2799c2 6842 gas_assert (*r == BFD_RELOC_GPREL16
e391c024
RS
6843 || *r == BFD_RELOC_MIPS_HIGHER
6844 || *r == BFD_RELOC_HI16_S
6845 || *r == BFD_RELOC_LO16
6846 || *r == BFD_RELOC_MIPS_GOT_OFST);
e077a1c8 6847 break;
e391c024
RS
6848
6849 case 'o':
6850 macro_read_relocs (&args, r);
e077a1c8 6851 break;
252b5132
RH
6852
6853 case 'u':
6e1304d8 6854 macro_read_relocs (&args, r);
9c2799c2 6855 gas_assert (ep != NULL
90ecf173
MR
6856 && (ep->X_op == O_constant
6857 || (ep->X_op == O_symbol
6858 && (*r == BFD_RELOC_MIPS_HIGHEST
6859 || *r == BFD_RELOC_HI16_S
6860 || *r == BFD_RELOC_HI16
6861 || *r == BFD_RELOC_GPREL16
6862 || *r == BFD_RELOC_MIPS_GOT_HI16
6863 || *r == BFD_RELOC_MIPS_CALL_HI16))));
e077a1c8 6864 break;
252b5132
RH
6865
6866 case 'p':
9c2799c2 6867 gas_assert (ep != NULL);
bad36eac 6868
252b5132
RH
6869 /*
6870 * This allows macro() to pass an immediate expression for
6871 * creating short branches without creating a symbol.
bad36eac
DJ
6872 *
6873 * We don't allow branch relaxation for these branches, as
6874 * they should only appear in ".set nomacro" anyway.
252b5132
RH
6875 */
6876 if (ep->X_op == O_constant)
6877 {
df58fc94
RS
6878 /* For microMIPS we always use relocations for branches.
6879 So we should not resolve immediate values. */
6880 gas_assert (!mips_opts.micromips);
6881
bad36eac
DJ
6882 if ((ep->X_add_number & 3) != 0)
6883 as_bad (_("branch to misaligned address (0x%lx)"),
6884 (unsigned long) ep->X_add_number);
6885 if ((ep->X_add_number + 0x20000) & ~0x3ffff)
6886 as_bad (_("branch address range overflow (0x%lx)"),
6887 (unsigned long) ep->X_add_number);
252b5132
RH
6888 insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff;
6889 ep = NULL;
6890 }
6891 else
0b25d3e6 6892 *r = BFD_RELOC_16_PCREL_S2;
e077a1c8 6893 break;
252b5132
RH
6894
6895 case 'a':
9c2799c2 6896 gas_assert (ep != NULL);
f6688943 6897 *r = BFD_RELOC_MIPS_JMP;
e077a1c8 6898 break;
d43b4baf 6899
252b5132 6900 default:
e077a1c8
RS
6901 operand = (mips_opts.micromips
6902 ? decode_micromips_operand (fmt)
6903 : decode_mips_operand (fmt));
6904 if (!operand)
6905 abort ();
6906
6907 uval = va_arg (args, int);
6908 if (operand->type == OP_CLO_CLZ_DEST)
6909 uval |= (uval << 5);
6910 insn_insert_operand (&insn, operand, uval);
6911
6912 if (*fmt == '+' || *fmt == 'm')
6913 ++fmt;
6914 break;
252b5132 6915 }
252b5132
RH
6916 }
6917 va_end (args);
9c2799c2 6918 gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
252b5132 6919
df58fc94 6920 append_insn (&insn, ep, r, TRUE);
252b5132
RH
6921}
6922
6923static void
67c0d1eb 6924mips16_macro_build (expressionS *ep, const char *name, const char *fmt,
03ea81db 6925 va_list *args)
252b5132 6926{
1e915849 6927 struct mips_opcode *mo;
252b5132 6928 struct mips_cl_insn insn;
e077a1c8 6929 const struct mips_operand *operand;
f6688943
TS
6930 bfd_reloc_code_real_type r[3]
6931 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
252b5132 6932
1e915849 6933 mo = (struct mips_opcode *) hash_find (mips16_op_hash, name);
9c2799c2
NC
6934 gas_assert (mo);
6935 gas_assert (strcmp (name, mo->name) == 0);
252b5132 6936
1e915849 6937 while (strcmp (fmt, mo->args) != 0 || mo->pinfo == INSN_MACRO)
252b5132 6938 {
1e915849 6939 ++mo;
9c2799c2
NC
6940 gas_assert (mo->name);
6941 gas_assert (strcmp (name, mo->name) == 0);
252b5132
RH
6942 }
6943
1e915849 6944 create_insn (&insn, mo);
e077a1c8 6945 for (; *fmt; ++fmt)
252b5132
RH
6946 {
6947 int c;
6948
e077a1c8 6949 c = *fmt;
252b5132
RH
6950 switch (c)
6951 {
252b5132
RH
6952 case ',':
6953 case '(':
6954 case ')':
e077a1c8 6955 break;
252b5132
RH
6956
6957 case '0':
6958 case 'S':
6959 case 'P':
6960 case 'R':
e077a1c8 6961 break;
252b5132
RH
6962
6963 case '<':
6964 case '>':
6965 case '4':
6966 case '5':
6967 case 'H':
6968 case 'W':
6969 case 'D':
6970 case 'j':
6971 case '8':
6972 case 'V':
6973 case 'C':
6974 case 'U':
6975 case 'k':
6976 case 'K':
6977 case 'p':
6978 case 'q':
6979 {
b886a2ab
RS
6980 offsetT value;
6981
9c2799c2 6982 gas_assert (ep != NULL);
252b5132
RH
6983
6984 if (ep->X_op != O_constant)
874e8986 6985 *r = (int) BFD_RELOC_UNUSED + c;
b886a2ab 6986 else if (calculate_reloc (*r, ep->X_add_number, &value))
252b5132 6987 {
b886a2ab 6988 mips16_immed (NULL, 0, c, *r, value, 0, &insn.insn_opcode);
252b5132 6989 ep = NULL;
f6688943 6990 *r = BFD_RELOC_UNUSED;
252b5132
RH
6991 }
6992 }
e077a1c8 6993 break;
252b5132 6994
e077a1c8
RS
6995 default:
6996 operand = decode_mips16_operand (c, FALSE);
6997 if (!operand)
6998 abort ();
252b5132 6999
4a06e5a2 7000 insn_insert_operand (&insn, operand, va_arg (*args, int));
e077a1c8
RS
7001 break;
7002 }
252b5132
RH
7003 }
7004
9c2799c2 7005 gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
252b5132 7006
df58fc94 7007 append_insn (&insn, ep, r, TRUE);
252b5132
RH
7008}
7009
2051e8c4
MR
7010/*
7011 * Sign-extend 32-bit mode constants that have bit 31 set and all
7012 * higher bits unset.
7013 */
9f872bbe 7014static void
2051e8c4
MR
7015normalize_constant_expr (expressionS *ex)
7016{
9ee2a2d4 7017 if (ex->X_op == O_constant
2051e8c4
MR
7018 && IS_ZEXT_32BIT_NUM (ex->X_add_number))
7019 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
7020 - 0x80000000);
7021}
7022
7023/*
7024 * Sign-extend 32-bit mode address offsets that have bit 31 set and
7025 * all higher bits unset.
7026 */
7027static void
7028normalize_address_expr (expressionS *ex)
7029{
7030 if (((ex->X_op == O_constant && HAVE_32BIT_ADDRESSES)
7031 || (ex->X_op == O_symbol && HAVE_32BIT_SYMBOLS))
7032 && IS_ZEXT_32BIT_NUM (ex->X_add_number))
7033 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
7034 - 0x80000000);
7035}
7036
438c16b8
TS
7037/*
7038 * Generate a "jalr" instruction with a relocation hint to the called
7039 * function. This occurs in NewABI PIC code.
7040 */
7041static void
df58fc94 7042macro_build_jalr (expressionS *ep, int cprestore)
438c16b8 7043{
df58fc94
RS
7044 static const bfd_reloc_code_real_type jalr_relocs[2]
7045 = { BFD_RELOC_MIPS_JALR, BFD_RELOC_MICROMIPS_JALR };
7046 bfd_reloc_code_real_type jalr_reloc = jalr_relocs[mips_opts.micromips];
7047 const char *jalr;
685736be 7048 char *f = NULL;
b34976b6 7049
1180b5a4 7050 if (MIPS_JALR_HINT_P (ep))
f21f8242 7051 {
cc3d92a5 7052 frag_grow (8);
f21f8242
AO
7053 f = frag_more (0);
7054 }
2906b037 7055 if (mips_opts.micromips)
df58fc94 7056 {
833794fc
MR
7057 jalr = ((mips_opts.noreorder && !cprestore) || mips_opts.insn32
7058 ? "jalr" : "jalrs");
e64af278 7059 if (MIPS_JALR_HINT_P (ep)
833794fc 7060 || mips_opts.insn32
e64af278 7061 || (history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
df58fc94
RS
7062 macro_build (NULL, jalr, "t,s", RA, PIC_CALL_REG);
7063 else
7064 macro_build (NULL, jalr, "mj", PIC_CALL_REG);
7065 }
2906b037
MR
7066 else
7067 macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG);
1180b5a4 7068 if (MIPS_JALR_HINT_P (ep))
df58fc94 7069 fix_new_exp (frag_now, f - frag_now->fr_literal, 4, ep, FALSE, jalr_reloc);
438c16b8
TS
7070}
7071
252b5132
RH
7072/*
7073 * Generate a "lui" instruction.
7074 */
7075static void
67c0d1eb 7076macro_build_lui (expressionS *ep, int regnum)
252b5132 7077{
9c2799c2 7078 gas_assert (! mips_opts.mips16);
252b5132 7079
df58fc94 7080 if (ep->X_op != O_constant)
252b5132 7081 {
9c2799c2 7082 gas_assert (ep->X_op == O_symbol);
bbe506e8
TS
7083 /* _gp_disp is a special case, used from s_cpload.
7084 __gnu_local_gp is used if mips_no_shared. */
9c2799c2 7085 gas_assert (mips_pic == NO_PIC
78e1bb40 7086 || (! HAVE_NEWABI
aa6975fb
ILT
7087 && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0)
7088 || (! mips_in_shared
bbe506e8
TS
7089 && strcmp (S_GET_NAME (ep->X_add_symbol),
7090 "__gnu_local_gp") == 0));
252b5132
RH
7091 }
7092
df58fc94 7093 macro_build (ep, "lui", LUI_FMT, regnum, BFD_RELOC_HI16_S);
252b5132
RH
7094}
7095
885add95
CD
7096/* Generate a sequence of instructions to do a load or store from a constant
7097 offset off of a base register (breg) into/from a target register (treg),
7098 using AT if necessary. */
7099static void
67c0d1eb
RS
7100macro_build_ldst_constoffset (expressionS *ep, const char *op,
7101 int treg, int breg, int dbl)
885add95 7102{
9c2799c2 7103 gas_assert (ep->X_op == O_constant);
885add95 7104
256ab948 7105 /* Sign-extending 32-bit constants makes their handling easier. */
2051e8c4
MR
7106 if (!dbl)
7107 normalize_constant_expr (ep);
256ab948 7108
67c1ffbe 7109 /* Right now, this routine can only handle signed 32-bit constants. */
ecd13cd3 7110 if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000))
885add95
CD
7111 as_warn (_("operand overflow"));
7112
7113 if (IS_SEXT_16BIT_NUM(ep->X_add_number))
7114 {
7115 /* Signed 16-bit offset will fit in the op. Easy! */
67c0d1eb 7116 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, breg);
885add95
CD
7117 }
7118 else
7119 {
7120 /* 32-bit offset, need multiple instructions and AT, like:
7121 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
7122 addu $tempreg,$tempreg,$breg
7123 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
7124 to handle the complete offset. */
67c0d1eb
RS
7125 macro_build_lui (ep, AT);
7126 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
7127 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, AT);
885add95 7128
741fe287 7129 if (!mips_opts.at)
8fc2e39e 7130 as_bad (_("Macro used $at after \".set noat\""));
885add95
CD
7131 }
7132}
7133
252b5132
RH
7134/* set_at()
7135 * Generates code to set the $at register to true (one)
7136 * if reg is less than the immediate expression.
7137 */
7138static void
67c0d1eb 7139set_at (int reg, int unsignedp)
252b5132
RH
7140{
7141 if (imm_expr.X_op == O_constant
7142 && imm_expr.X_add_number >= -0x8000
7143 && imm_expr.X_add_number < 0x8000)
67c0d1eb
RS
7144 macro_build (&imm_expr, unsignedp ? "sltiu" : "slti", "t,r,j",
7145 AT, reg, BFD_RELOC_LO16);
252b5132
RH
7146 else
7147 {
67c0d1eb
RS
7148 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7149 macro_build (NULL, unsignedp ? "sltu" : "slt", "d,v,t", AT, reg, AT);
252b5132
RH
7150 }
7151}
7152
252b5132
RH
7153/* Count the leading zeroes by performing a binary chop. This is a
7154 bulky bit of source, but performance is a LOT better for the
7155 majority of values than a simple loop to count the bits:
7156 for (lcnt = 0; (lcnt < 32); lcnt++)
7157 if ((v) & (1 << (31 - lcnt)))
7158 break;
7159 However it is not code size friendly, and the gain will drop a bit
7160 on certain cached systems.
7161*/
7162#define COUNT_TOP_ZEROES(v) \
7163 (((v) & ~0xffff) == 0 \
7164 ? ((v) & ~0xff) == 0 \
7165 ? ((v) & ~0xf) == 0 \
7166 ? ((v) & ~0x3) == 0 \
7167 ? ((v) & ~0x1) == 0 \
7168 ? !(v) \
7169 ? 32 \
7170 : 31 \
7171 : 30 \
7172 : ((v) & ~0x7) == 0 \
7173 ? 29 \
7174 : 28 \
7175 : ((v) & ~0x3f) == 0 \
7176 ? ((v) & ~0x1f) == 0 \
7177 ? 27 \
7178 : 26 \
7179 : ((v) & ~0x7f) == 0 \
7180 ? 25 \
7181 : 24 \
7182 : ((v) & ~0xfff) == 0 \
7183 ? ((v) & ~0x3ff) == 0 \
7184 ? ((v) & ~0x1ff) == 0 \
7185 ? 23 \
7186 : 22 \
7187 : ((v) & ~0x7ff) == 0 \
7188 ? 21 \
7189 : 20 \
7190 : ((v) & ~0x3fff) == 0 \
7191 ? ((v) & ~0x1fff) == 0 \
7192 ? 19 \
7193 : 18 \
7194 : ((v) & ~0x7fff) == 0 \
7195 ? 17 \
7196 : 16 \
7197 : ((v) & ~0xffffff) == 0 \
7198 ? ((v) & ~0xfffff) == 0 \
7199 ? ((v) & ~0x3ffff) == 0 \
7200 ? ((v) & ~0x1ffff) == 0 \
7201 ? 15 \
7202 : 14 \
7203 : ((v) & ~0x7ffff) == 0 \
7204 ? 13 \
7205 : 12 \
7206 : ((v) & ~0x3fffff) == 0 \
7207 ? ((v) & ~0x1fffff) == 0 \
7208 ? 11 \
7209 : 10 \
7210 : ((v) & ~0x7fffff) == 0 \
7211 ? 9 \
7212 : 8 \
7213 : ((v) & ~0xfffffff) == 0 \
7214 ? ((v) & ~0x3ffffff) == 0 \
7215 ? ((v) & ~0x1ffffff) == 0 \
7216 ? 7 \
7217 : 6 \
7218 : ((v) & ~0x7ffffff) == 0 \
7219 ? 5 \
7220 : 4 \
7221 : ((v) & ~0x3fffffff) == 0 \
7222 ? ((v) & ~0x1fffffff) == 0 \
7223 ? 3 \
7224 : 2 \
7225 : ((v) & ~0x7fffffff) == 0 \
7226 ? 1 \
7227 : 0)
7228
7229/* load_register()
67c1ffbe 7230 * This routine generates the least number of instructions necessary to load
252b5132
RH
7231 * an absolute expression value into a register.
7232 */
7233static void
67c0d1eb 7234load_register (int reg, expressionS *ep, int dbl)
252b5132
RH
7235{
7236 int freg;
7237 expressionS hi32, lo32;
7238
7239 if (ep->X_op != O_big)
7240 {
9c2799c2 7241 gas_assert (ep->X_op == O_constant);
256ab948
TS
7242
7243 /* Sign-extending 32-bit constants makes their handling easier. */
2051e8c4
MR
7244 if (!dbl)
7245 normalize_constant_expr (ep);
256ab948
TS
7246
7247 if (IS_SEXT_16BIT_NUM (ep->X_add_number))
252b5132
RH
7248 {
7249 /* We can handle 16 bit signed values with an addiu to
7250 $zero. No need to ever use daddiu here, since $zero and
7251 the result are always correct in 32 bit mode. */
67c0d1eb 7252 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
252b5132
RH
7253 return;
7254 }
7255 else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000)
7256 {
7257 /* We can handle 16 bit unsigned values with an ori to
7258 $zero. */
67c0d1eb 7259 macro_build (ep, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16);
252b5132
RH
7260 return;
7261 }
256ab948 7262 else if ((IS_SEXT_32BIT_NUM (ep->X_add_number)))
252b5132
RH
7263 {
7264 /* 32 bit values require an lui. */
df58fc94 7265 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_HI16);
252b5132 7266 if ((ep->X_add_number & 0xffff) != 0)
67c0d1eb 7267 macro_build (ep, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
252b5132
RH
7268 return;
7269 }
7270 }
7271
7272 /* The value is larger than 32 bits. */
7273
2051e8c4 7274 if (!dbl || HAVE_32BIT_GPRS)
252b5132 7275 {
55e08f71
NC
7276 char value[32];
7277
7278 sprintf_vma (value, ep->X_add_number);
20e1fcfd 7279 as_bad (_("Number (0x%s) larger than 32 bits"), value);
67c0d1eb 7280 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
252b5132
RH
7281 return;
7282 }
7283
7284 if (ep->X_op != O_big)
7285 {
7286 hi32 = *ep;
7287 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
7288 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
7289 hi32.X_add_number &= 0xffffffff;
7290 lo32 = *ep;
7291 lo32.X_add_number &= 0xffffffff;
7292 }
7293 else
7294 {
9c2799c2 7295 gas_assert (ep->X_add_number > 2);
252b5132
RH
7296 if (ep->X_add_number == 3)
7297 generic_bignum[3] = 0;
7298 else if (ep->X_add_number > 4)
7299 as_bad (_("Number larger than 64 bits"));
7300 lo32.X_op = O_constant;
7301 lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16);
7302 hi32.X_op = O_constant;
7303 hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16);
7304 }
7305
7306 if (hi32.X_add_number == 0)
7307 freg = 0;
7308 else
7309 {
7310 int shift, bit;
7311 unsigned long hi, lo;
7312
956cd1d6 7313 if (hi32.X_add_number == (offsetT) 0xffffffff)
beae10d5
KH
7314 {
7315 if ((lo32.X_add_number & 0xffff8000) == 0xffff8000)
7316 {
67c0d1eb 7317 macro_build (&lo32, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
beae10d5
KH
7318 return;
7319 }
7320 if (lo32.X_add_number & 0x80000000)
7321 {
df58fc94 7322 macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16);
252b5132 7323 if (lo32.X_add_number & 0xffff)
67c0d1eb 7324 macro_build (&lo32, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
beae10d5
KH
7325 return;
7326 }
7327 }
252b5132
RH
7328
7329 /* Check for 16bit shifted constant. We know that hi32 is
7330 non-zero, so start the mask on the first bit of the hi32
7331 value. */
7332 shift = 17;
7333 do
beae10d5
KH
7334 {
7335 unsigned long himask, lomask;
7336
7337 if (shift < 32)
7338 {
7339 himask = 0xffff >> (32 - shift);
7340 lomask = (0xffff << shift) & 0xffffffff;
7341 }
7342 else
7343 {
7344 himask = 0xffff << (shift - 32);
7345 lomask = 0;
7346 }
7347 if ((hi32.X_add_number & ~(offsetT) himask) == 0
7348 && (lo32.X_add_number & ~(offsetT) lomask) == 0)
7349 {
7350 expressionS tmp;
7351
7352 tmp.X_op = O_constant;
7353 if (shift < 32)
7354 tmp.X_add_number = ((hi32.X_add_number << (32 - shift))
7355 | (lo32.X_add_number >> shift));
7356 else
7357 tmp.X_add_number = hi32.X_add_number >> (shift - 32);
67c0d1eb 7358 macro_build (&tmp, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16);
df58fc94 7359 macro_build (NULL, (shift >= 32) ? "dsll32" : "dsll", SHFT_FMT,
67c0d1eb 7360 reg, reg, (shift >= 32) ? shift - 32 : shift);
beae10d5
KH
7361 return;
7362 }
f9419b05 7363 ++shift;
beae10d5
KH
7364 }
7365 while (shift <= (64 - 16));
252b5132
RH
7366
7367 /* Find the bit number of the lowest one bit, and store the
7368 shifted value in hi/lo. */
7369 hi = (unsigned long) (hi32.X_add_number & 0xffffffff);
7370 lo = (unsigned long) (lo32.X_add_number & 0xffffffff);
7371 if (lo != 0)
7372 {
7373 bit = 0;
7374 while ((lo & 1) == 0)
7375 {
7376 lo >>= 1;
7377 ++bit;
7378 }
7379 lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit);
7380 hi >>= bit;
7381 }
7382 else
7383 {
7384 bit = 32;
7385 while ((hi & 1) == 0)
7386 {
7387 hi >>= 1;
7388 ++bit;
7389 }
7390 lo = hi;
7391 hi = 0;
7392 }
7393
7394 /* Optimize if the shifted value is a (power of 2) - 1. */
7395 if ((hi == 0 && ((lo + 1) & lo) == 0)
7396 || (lo == 0xffffffff && ((hi + 1) & hi) == 0))
beae10d5
KH
7397 {
7398 shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number);
252b5132 7399 if (shift != 0)
beae10d5 7400 {
252b5132
RH
7401 expressionS tmp;
7402
7403 /* This instruction will set the register to be all
7404 ones. */
beae10d5
KH
7405 tmp.X_op = O_constant;
7406 tmp.X_add_number = (offsetT) -1;
67c0d1eb 7407 macro_build (&tmp, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
beae10d5
KH
7408 if (bit != 0)
7409 {
7410 bit += shift;
df58fc94 7411 macro_build (NULL, (bit >= 32) ? "dsll32" : "dsll", SHFT_FMT,
67c0d1eb 7412 reg, reg, (bit >= 32) ? bit - 32 : bit);
beae10d5 7413 }
df58fc94 7414 macro_build (NULL, (shift >= 32) ? "dsrl32" : "dsrl", SHFT_FMT,
67c0d1eb 7415 reg, reg, (shift >= 32) ? shift - 32 : shift);
beae10d5
KH
7416 return;
7417 }
7418 }
252b5132
RH
7419
7420 /* Sign extend hi32 before calling load_register, because we can
7421 generally get better code when we load a sign extended value. */
7422 if ((hi32.X_add_number & 0x80000000) != 0)
beae10d5 7423 hi32.X_add_number |= ~(offsetT) 0xffffffff;
67c0d1eb 7424 load_register (reg, &hi32, 0);
252b5132
RH
7425 freg = reg;
7426 }
7427 if ((lo32.X_add_number & 0xffff0000) == 0)
7428 {
7429 if (freg != 0)
7430 {
df58fc94 7431 macro_build (NULL, "dsll32", SHFT_FMT, reg, freg, 0);
252b5132
RH
7432 freg = reg;
7433 }
7434 }
7435 else
7436 {
7437 expressionS mid16;
7438
956cd1d6 7439 if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff))
beae10d5 7440 {
df58fc94
RS
7441 macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16);
7442 macro_build (NULL, "dsrl32", SHFT_FMT, reg, reg, 0);
beae10d5
KH
7443 return;
7444 }
252b5132
RH
7445
7446 if (freg != 0)
7447 {
df58fc94 7448 macro_build (NULL, "dsll", SHFT_FMT, reg, freg, 16);
252b5132
RH
7449 freg = reg;
7450 }
7451 mid16 = lo32;
7452 mid16.X_add_number >>= 16;
67c0d1eb 7453 macro_build (&mid16, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
df58fc94 7454 macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16);
252b5132
RH
7455 freg = reg;
7456 }
7457 if ((lo32.X_add_number & 0xffff) != 0)
67c0d1eb 7458 macro_build (&lo32, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
252b5132
RH
7459}
7460
269137b2
TS
7461static inline void
7462load_delay_nop (void)
7463{
7464 if (!gpr_interlocks)
7465 macro_build (NULL, "nop", "");
7466}
7467
252b5132
RH
7468/* Load an address into a register. */
7469
7470static void
67c0d1eb 7471load_address (int reg, expressionS *ep, int *used_at)
252b5132 7472{
252b5132
RH
7473 if (ep->X_op != O_constant
7474 && ep->X_op != O_symbol)
7475 {
7476 as_bad (_("expression too complex"));
7477 ep->X_op = O_constant;
7478 }
7479
7480 if (ep->X_op == O_constant)
7481 {
67c0d1eb 7482 load_register (reg, ep, HAVE_64BIT_ADDRESSES);
252b5132
RH
7483 return;
7484 }
7485
7486 if (mips_pic == NO_PIC)
7487 {
7488 /* If this is a reference to a GP relative symbol, we want
cdf6fd85 7489 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
252b5132
RH
7490 Otherwise we want
7491 lui $reg,<sym> (BFD_RELOC_HI16_S)
7492 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
d6bc6245 7493 If we have an addend, we always use the latter form.
76b3015f 7494
d6bc6245
TS
7495 With 64bit address space and a usable $at we want
7496 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
7497 lui $at,<sym> (BFD_RELOC_HI16_S)
7498 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
7499 daddiu $at,<sym> (BFD_RELOC_LO16)
7500 dsll32 $reg,0
3a482fd5 7501 daddu $reg,$reg,$at
76b3015f 7502
c03099e6 7503 If $at is already in use, we use a path which is suboptimal
d6bc6245
TS
7504 on superscalar processors.
7505 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
7506 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
7507 dsll $reg,16
7508 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
7509 dsll $reg,16
7510 daddiu $reg,<sym> (BFD_RELOC_LO16)
6caf9ef4
TS
7511
7512 For GP relative symbols in 64bit address space we can use
7513 the same sequence as in 32bit address space. */
aed1a261 7514 if (HAVE_64BIT_SYMBOLS)
d6bc6245 7515 {
6caf9ef4
TS
7516 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
7517 && !nopic_need_relax (ep->X_add_symbol, 1))
7518 {
7519 relax_start (ep->X_add_symbol);
7520 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
7521 mips_gp_register, BFD_RELOC_GPREL16);
7522 relax_switch ();
7523 }
d6bc6245 7524
741fe287 7525 if (*used_at == 0 && mips_opts.at)
d6bc6245 7526 {
df58fc94
RS
7527 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST);
7528 macro_build (ep, "lui", LUI_FMT, AT, BFD_RELOC_HI16_S);
67c0d1eb
RS
7529 macro_build (ep, "daddiu", "t,r,j", reg, reg,
7530 BFD_RELOC_MIPS_HIGHER);
7531 macro_build (ep, "daddiu", "t,r,j", AT, AT, BFD_RELOC_LO16);
df58fc94 7532 macro_build (NULL, "dsll32", SHFT_FMT, reg, reg, 0);
67c0d1eb 7533 macro_build (NULL, "daddu", "d,v,t", reg, reg, AT);
d6bc6245
TS
7534 *used_at = 1;
7535 }
7536 else
7537 {
df58fc94 7538 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST);
67c0d1eb
RS
7539 macro_build (ep, "daddiu", "t,r,j", reg, reg,
7540 BFD_RELOC_MIPS_HIGHER);
df58fc94 7541 macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16);
67c0d1eb 7542 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_HI16_S);
df58fc94 7543 macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16);
67c0d1eb 7544 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_LO16);
d6bc6245 7545 }
6caf9ef4
TS
7546
7547 if (mips_relax.sequence)
7548 relax_end ();
d6bc6245 7549 }
252b5132
RH
7550 else
7551 {
d6bc6245 7552 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
6caf9ef4 7553 && !nopic_need_relax (ep->X_add_symbol, 1))
d6bc6245 7554 {
4d7206a2 7555 relax_start (ep->X_add_symbol);
67c0d1eb 7556 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
17a2f251 7557 mips_gp_register, BFD_RELOC_GPREL16);
4d7206a2 7558 relax_switch ();
d6bc6245 7559 }
67c0d1eb
RS
7560 macro_build_lui (ep, reg);
7561 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j",
7562 reg, reg, BFD_RELOC_LO16);
4d7206a2
RS
7563 if (mips_relax.sequence)
7564 relax_end ();
d6bc6245 7565 }
252b5132 7566 }
0a44bf69 7567 else if (!mips_big_got)
252b5132
RH
7568 {
7569 expressionS ex;
7570
7571 /* If this is a reference to an external symbol, we want
7572 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7573 Otherwise we want
7574 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7575 nop
7576 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
f5040a92
AO
7577 If there is a constant, it must be added in after.
7578
ed6fb7bd 7579 If we have NewABI, we want
f5040a92
AO
7580 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
7581 unless we're referencing a global symbol with a non-zero
7582 offset, in which case cst must be added separately. */
ed6fb7bd
SC
7583 if (HAVE_NEWABI)
7584 {
f5040a92
AO
7585 if (ep->X_add_number)
7586 {
4d7206a2 7587 ex.X_add_number = ep->X_add_number;
f5040a92 7588 ep->X_add_number = 0;
4d7206a2 7589 relax_start (ep->X_add_symbol);
67c0d1eb
RS
7590 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
7591 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
f5040a92
AO
7592 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
7593 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
7594 ex.X_op = O_constant;
67c0d1eb 7595 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j",
17a2f251 7596 reg, reg, BFD_RELOC_LO16);
f5040a92 7597 ep->X_add_number = ex.X_add_number;
4d7206a2 7598 relax_switch ();
f5040a92 7599 }
67c0d1eb 7600 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
17a2f251 7601 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
4d7206a2
RS
7602 if (mips_relax.sequence)
7603 relax_end ();
ed6fb7bd
SC
7604 }
7605 else
7606 {
f5040a92
AO
7607 ex.X_add_number = ep->X_add_number;
7608 ep->X_add_number = 0;
67c0d1eb
RS
7609 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
7610 BFD_RELOC_MIPS_GOT16, mips_gp_register);
269137b2 7611 load_delay_nop ();
4d7206a2
RS
7612 relax_start (ep->X_add_symbol);
7613 relax_switch ();
67c0d1eb 7614 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
17a2f251 7615 BFD_RELOC_LO16);
4d7206a2 7616 relax_end ();
ed6fb7bd 7617
f5040a92
AO
7618 if (ex.X_add_number != 0)
7619 {
7620 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
7621 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
7622 ex.X_op = O_constant;
67c0d1eb 7623 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j",
17a2f251 7624 reg, reg, BFD_RELOC_LO16);
f5040a92 7625 }
252b5132
RH
7626 }
7627 }
0a44bf69 7628 else if (mips_big_got)
252b5132
RH
7629 {
7630 expressionS ex;
252b5132
RH
7631
7632 /* This is the large GOT case. If this is a reference to an
7633 external symbol, we want
7634 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7635 addu $reg,$reg,$gp
7636 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
f5040a92
AO
7637
7638 Otherwise, for a reference to a local symbol in old ABI, we want
252b5132
RH
7639 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7640 nop
7641 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
684022ea 7642 If there is a constant, it must be added in after.
f5040a92
AO
7643
7644 In the NewABI, for local symbols, with or without offsets, we want:
438c16b8
TS
7645 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
7646 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
f5040a92 7647 */
438c16b8
TS
7648 if (HAVE_NEWABI)
7649 {
4d7206a2 7650 ex.X_add_number = ep->X_add_number;
f5040a92 7651 ep->X_add_number = 0;
4d7206a2 7652 relax_start (ep->X_add_symbol);
df58fc94 7653 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16);
67c0d1eb
RS
7654 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7655 reg, reg, mips_gp_register);
7656 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)",
7657 reg, BFD_RELOC_MIPS_GOT_LO16, reg);
f5040a92
AO
7658 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
7659 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
7660 else if (ex.X_add_number)
7661 {
7662 ex.X_op = O_constant;
67c0d1eb
RS
7663 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
7664 BFD_RELOC_LO16);
f5040a92
AO
7665 }
7666
7667 ep->X_add_number = ex.X_add_number;
4d7206a2 7668 relax_switch ();
67c0d1eb 7669 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
17a2f251 7670 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
67c0d1eb
RS
7671 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
7672 BFD_RELOC_MIPS_GOT_OFST);
4d7206a2 7673 relax_end ();
438c16b8 7674 }
252b5132 7675 else
438c16b8 7676 {
f5040a92
AO
7677 ex.X_add_number = ep->X_add_number;
7678 ep->X_add_number = 0;
4d7206a2 7679 relax_start (ep->X_add_symbol);
df58fc94 7680 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16);
67c0d1eb
RS
7681 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7682 reg, reg, mips_gp_register);
7683 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)",
7684 reg, BFD_RELOC_MIPS_GOT_LO16, reg);
4d7206a2
RS
7685 relax_switch ();
7686 if (reg_needs_delay (mips_gp_register))
438c16b8
TS
7687 {
7688 /* We need a nop before loading from $gp. This special
7689 check is required because the lui which starts the main
7690 instruction stream does not refer to $gp, and so will not
7691 insert the nop which may be required. */
67c0d1eb 7692 macro_build (NULL, "nop", "");
438c16b8 7693 }
67c0d1eb 7694 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
17a2f251 7695 BFD_RELOC_MIPS_GOT16, mips_gp_register);
269137b2 7696 load_delay_nop ();
67c0d1eb 7697 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
17a2f251 7698 BFD_RELOC_LO16);
4d7206a2 7699 relax_end ();
438c16b8 7700
f5040a92
AO
7701 if (ex.X_add_number != 0)
7702 {
7703 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
7704 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
7705 ex.X_op = O_constant;
67c0d1eb
RS
7706 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
7707 BFD_RELOC_LO16);
f5040a92 7708 }
252b5132
RH
7709 }
7710 }
252b5132
RH
7711 else
7712 abort ();
8fc2e39e 7713
741fe287 7714 if (!mips_opts.at && *used_at == 1)
8fc2e39e 7715 as_bad (_("Macro used $at after \".set noat\""));
252b5132
RH
7716}
7717
ea1fb5dc
RS
7718/* Move the contents of register SOURCE into register DEST. */
7719
7720static void
67c0d1eb 7721move_register (int dest, int source)
ea1fb5dc 7722{
df58fc94
RS
7723 /* Prefer to use a 16-bit microMIPS instruction unless the previous
7724 instruction specifically requires a 32-bit one. */
7725 if (mips_opts.micromips
833794fc 7726 && !mips_opts.insn32
df58fc94 7727 && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
7951ca42 7728 macro_build (NULL, "move", "mp,mj", dest, source);
df58fc94
RS
7729 else
7730 macro_build (NULL, HAVE_32BIT_GPRS ? "addu" : "daddu", "d,v,t",
7731 dest, source, 0);
ea1fb5dc
RS
7732}
7733
4d7206a2 7734/* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
f6a22291
MR
7735 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
7736 The two alternatives are:
4d7206a2
RS
7737
7738 Global symbol Local sybmol
7739 ------------- ------------
7740 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
7741 ... ...
7742 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
7743
7744 load_got_offset emits the first instruction and add_got_offset
f6a22291
MR
7745 emits the second for a 16-bit offset or add_got_offset_hilo emits
7746 a sequence to add a 32-bit offset using a scratch register. */
4d7206a2
RS
7747
7748static void
67c0d1eb 7749load_got_offset (int dest, expressionS *local)
4d7206a2
RS
7750{
7751 expressionS global;
7752
7753 global = *local;
7754 global.X_add_number = 0;
7755
7756 relax_start (local->X_add_symbol);
67c0d1eb
RS
7757 macro_build (&global, ADDRESS_LOAD_INSN, "t,o(b)", dest,
7758 BFD_RELOC_MIPS_GOT16, mips_gp_register);
4d7206a2 7759 relax_switch ();
67c0d1eb
RS
7760 macro_build (local, ADDRESS_LOAD_INSN, "t,o(b)", dest,
7761 BFD_RELOC_MIPS_GOT16, mips_gp_register);
4d7206a2
RS
7762 relax_end ();
7763}
7764
7765static void
67c0d1eb 7766add_got_offset (int dest, expressionS *local)
4d7206a2
RS
7767{
7768 expressionS global;
7769
7770 global.X_op = O_constant;
7771 global.X_op_symbol = NULL;
7772 global.X_add_symbol = NULL;
7773 global.X_add_number = local->X_add_number;
7774
7775 relax_start (local->X_add_symbol);
67c0d1eb 7776 macro_build (&global, ADDRESS_ADDI_INSN, "t,r,j",
4d7206a2
RS
7777 dest, dest, BFD_RELOC_LO16);
7778 relax_switch ();
67c0d1eb 7779 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", dest, dest, BFD_RELOC_LO16);
4d7206a2
RS
7780 relax_end ();
7781}
7782
f6a22291
MR
7783static void
7784add_got_offset_hilo (int dest, expressionS *local, int tmp)
7785{
7786 expressionS global;
7787 int hold_mips_optimize;
7788
7789 global.X_op = O_constant;
7790 global.X_op_symbol = NULL;
7791 global.X_add_symbol = NULL;
7792 global.X_add_number = local->X_add_number;
7793
7794 relax_start (local->X_add_symbol);
7795 load_register (tmp, &global, HAVE_64BIT_ADDRESSES);
7796 relax_switch ();
7797 /* Set mips_optimize around the lui instruction to avoid
7798 inserting an unnecessary nop after the lw. */
7799 hold_mips_optimize = mips_optimize;
7800 mips_optimize = 2;
7801 macro_build_lui (&global, tmp);
7802 mips_optimize = hold_mips_optimize;
7803 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", tmp, tmp, BFD_RELOC_LO16);
7804 relax_end ();
7805
7806 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dest, dest, tmp);
7807}
7808
df58fc94
RS
7809/* Emit a sequence of instructions to emulate a branch likely operation.
7810 BR is an ordinary branch corresponding to one to be emulated. BRNEG
7811 is its complementing branch with the original condition negated.
7812 CALL is set if the original branch specified the link operation.
7813 EP, FMT, SREG and TREG specify the usual macro_build() parameters.
7814
7815 Code like this is produced in the noreorder mode:
7816
7817 BRNEG <args>, 1f
7818 nop
7819 b <sym>
7820 delay slot (executed only if branch taken)
7821 1:
7822
7823 or, if CALL is set:
7824
7825 BRNEG <args>, 1f
7826 nop
7827 bal <sym>
7828 delay slot (executed only if branch taken)
7829 1:
7830
7831 In the reorder mode the delay slot would be filled with a nop anyway,
7832 so code produced is simply:
7833
7834 BR <args>, <sym>
7835 nop
7836
7837 This function is used when producing code for the microMIPS ASE that
7838 does not implement branch likely instructions in hardware. */
7839
7840static void
7841macro_build_branch_likely (const char *br, const char *brneg,
7842 int call, expressionS *ep, const char *fmt,
7843 unsigned int sreg, unsigned int treg)
7844{
7845 int noreorder = mips_opts.noreorder;
7846 expressionS expr1;
7847
7848 gas_assert (mips_opts.micromips);
7849 start_noreorder ();
7850 if (noreorder)
7851 {
7852 micromips_label_expr (&expr1);
7853 macro_build (&expr1, brneg, fmt, sreg, treg);
7854 macro_build (NULL, "nop", "");
7855 macro_build (ep, call ? "bal" : "b", "p");
7856
7857 /* Set to true so that append_insn adds a label. */
7858 emit_branch_likely_macro = TRUE;
7859 }
7860 else
7861 {
7862 macro_build (ep, br, fmt, sreg, treg);
7863 macro_build (NULL, "nop", "");
7864 }
7865 end_noreorder ();
7866}
7867
7868/* Emit a coprocessor branch-likely macro specified by TYPE, using CC as
7869 the condition code tested. EP specifies the branch target. */
7870
7871static void
7872macro_build_branch_ccl (int type, expressionS *ep, unsigned int cc)
7873{
7874 const int call = 0;
7875 const char *brneg;
7876 const char *br;
7877
7878 switch (type)
7879 {
7880 case M_BC1FL:
7881 br = "bc1f";
7882 brneg = "bc1t";
7883 break;
7884 case M_BC1TL:
7885 br = "bc1t";
7886 brneg = "bc1f";
7887 break;
7888 case M_BC2FL:
7889 br = "bc2f";
7890 brneg = "bc2t";
7891 break;
7892 case M_BC2TL:
7893 br = "bc2t";
7894 brneg = "bc2f";
7895 break;
7896 default:
7897 abort ();
7898 }
7899 macro_build_branch_likely (br, brneg, call, ep, "N,p", cc, ZERO);
7900}
7901
7902/* Emit a two-argument branch macro specified by TYPE, using SREG as
7903 the register tested. EP specifies the branch target. */
7904
7905static void
7906macro_build_branch_rs (int type, expressionS *ep, unsigned int sreg)
7907{
7908 const char *brneg = NULL;
7909 const char *br;
7910 int call = 0;
7911
7912 switch (type)
7913 {
7914 case M_BGEZ:
7915 br = "bgez";
7916 break;
7917 case M_BGEZL:
7918 br = mips_opts.micromips ? "bgez" : "bgezl";
7919 brneg = "bltz";
7920 break;
7921 case M_BGEZALL:
7922 gas_assert (mips_opts.micromips);
833794fc 7923 br = mips_opts.insn32 ? "bgezal" : "bgezals";
df58fc94
RS
7924 brneg = "bltz";
7925 call = 1;
7926 break;
7927 case M_BGTZ:
7928 br = "bgtz";
7929 break;
7930 case M_BGTZL:
7931 br = mips_opts.micromips ? "bgtz" : "bgtzl";
7932 brneg = "blez";
7933 break;
7934 case M_BLEZ:
7935 br = "blez";
7936 break;
7937 case M_BLEZL:
7938 br = mips_opts.micromips ? "blez" : "blezl";
7939 brneg = "bgtz";
7940 break;
7941 case M_BLTZ:
7942 br = "bltz";
7943 break;
7944 case M_BLTZL:
7945 br = mips_opts.micromips ? "bltz" : "bltzl";
7946 brneg = "bgez";
7947 break;
7948 case M_BLTZALL:
7949 gas_assert (mips_opts.micromips);
833794fc 7950 br = mips_opts.insn32 ? "bltzal" : "bltzals";
df58fc94
RS
7951 brneg = "bgez";
7952 call = 1;
7953 break;
7954 default:
7955 abort ();
7956 }
7957 if (mips_opts.micromips && brneg)
7958 macro_build_branch_likely (br, brneg, call, ep, "s,p", sreg, ZERO);
7959 else
7960 macro_build (ep, br, "s,p", sreg);
7961}
7962
7963/* Emit a three-argument branch macro specified by TYPE, using SREG and
7964 TREG as the registers tested. EP specifies the branch target. */
7965
7966static void
7967macro_build_branch_rsrt (int type, expressionS *ep,
7968 unsigned int sreg, unsigned int treg)
7969{
7970 const char *brneg = NULL;
7971 const int call = 0;
7972 const char *br;
7973
7974 switch (type)
7975 {
7976 case M_BEQ:
7977 case M_BEQ_I:
7978 br = "beq";
7979 break;
7980 case M_BEQL:
7981 case M_BEQL_I:
7982 br = mips_opts.micromips ? "beq" : "beql";
7983 brneg = "bne";
7984 break;
7985 case M_BNE:
7986 case M_BNE_I:
7987 br = "bne";
7988 break;
7989 case M_BNEL:
7990 case M_BNEL_I:
7991 br = mips_opts.micromips ? "bne" : "bnel";
7992 brneg = "beq";
7993 break;
7994 default:
7995 abort ();
7996 }
7997 if (mips_opts.micromips && brneg)
7998 macro_build_branch_likely (br, brneg, call, ep, "s,t,p", sreg, treg);
7999 else
8000 macro_build (ep, br, "s,t,p", sreg, treg);
8001}
8002
f2ae14a1
RS
8003/* Return the high part that should be loaded in order to make the low
8004 part of VALUE accessible using an offset of OFFBITS bits. */
8005
8006static offsetT
8007offset_high_part (offsetT value, unsigned int offbits)
8008{
8009 offsetT bias;
8010 addressT low_mask;
8011
8012 if (offbits == 0)
8013 return value;
8014 bias = 1 << (offbits - 1);
8015 low_mask = bias * 2 - 1;
8016 return (value + bias) & ~low_mask;
8017}
8018
8019/* Return true if the value stored in offset_expr and offset_reloc
8020 fits into a signed offset of OFFBITS bits. RANGE is the maximum
8021 amount that the caller wants to add without inducing overflow
8022 and ALIGN is the known alignment of the value in bytes. */
8023
8024static bfd_boolean
8025small_offset_p (unsigned int range, unsigned int align, unsigned int offbits)
8026{
8027 if (offbits == 16)
8028 {
8029 /* Accept any relocation operator if overflow isn't a concern. */
8030 if (range < align && *offset_reloc != BFD_RELOC_UNUSED)
8031 return TRUE;
8032
8033 /* These relocations are guaranteed not to overflow in correct links. */
8034 if (*offset_reloc == BFD_RELOC_MIPS_LITERAL
8035 || gprel16_reloc_p (*offset_reloc))
8036 return TRUE;
8037 }
8038 if (offset_expr.X_op == O_constant
8039 && offset_high_part (offset_expr.X_add_number, offbits) == 0
8040 && offset_high_part (offset_expr.X_add_number + range, offbits) == 0)
8041 return TRUE;
8042 return FALSE;
8043}
8044
252b5132
RH
8045/*
8046 * Build macros
8047 * This routine implements the seemingly endless macro or synthesized
8048 * instructions and addressing modes in the mips assembly language. Many
8049 * of these macros are simple and are similar to each other. These could
67c1ffbe 8050 * probably be handled by some kind of table or grammar approach instead of
252b5132
RH
8051 * this verbose method. Others are not simple macros but are more like
8052 * optimizing code generation.
8053 * One interesting optimization is when several store macros appear
67c1ffbe 8054 * consecutively that would load AT with the upper half of the same address.
252b5132
RH
8055 * The ensuing load upper instructions are ommited. This implies some kind
8056 * of global optimization. We currently only optimize within a single macro.
8057 * For many of the load and store macros if the address is specified as a
8058 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
8059 * first load register 'at' with zero and use it as the base register. The
8060 * mips assembler simply uses register $zero. Just one tiny optimization
8061 * we're missing.
8062 */
8063static void
833794fc 8064macro (struct mips_cl_insn *ip, char *str)
252b5132 8065{
741fe287
MR
8066 unsigned int treg, sreg, dreg, breg;
8067 unsigned int tempreg;
252b5132 8068 int mask;
43841e91 8069 int used_at = 0;
df58fc94 8070 expressionS label_expr;
252b5132 8071 expressionS expr1;
df58fc94 8072 expressionS *ep;
252b5132
RH
8073 const char *s;
8074 const char *s2;
8075 const char *fmt;
8076 int likely = 0;
252b5132 8077 int coproc = 0;
7f3c4072 8078 int offbits = 16;
1abe91b1 8079 int call = 0;
df58fc94
RS
8080 int jals = 0;
8081 int dbl = 0;
8082 int imm = 0;
8083 int ust = 0;
8084 int lp = 0;
f2ae14a1 8085 bfd_boolean large_offset;
252b5132 8086 int off;
252b5132 8087 int hold_mips_optimize;
f2ae14a1 8088 unsigned int align;
252b5132 8089
9c2799c2 8090 gas_assert (! mips_opts.mips16);
252b5132 8091
df58fc94
RS
8092 treg = EXTRACT_OPERAND (mips_opts.micromips, RT, *ip);
8093 dreg = EXTRACT_OPERAND (mips_opts.micromips, RD, *ip);
8094 sreg = breg = EXTRACT_OPERAND (mips_opts.micromips, RS, *ip);
252b5132
RH
8095 mask = ip->insn_mo->mask;
8096
df58fc94
RS
8097 label_expr.X_op = O_constant;
8098 label_expr.X_op_symbol = NULL;
8099 label_expr.X_add_symbol = NULL;
8100 label_expr.X_add_number = 0;
8101
252b5132
RH
8102 expr1.X_op = O_constant;
8103 expr1.X_op_symbol = NULL;
8104 expr1.X_add_symbol = NULL;
8105 expr1.X_add_number = 1;
f2ae14a1 8106 align = 1;
252b5132
RH
8107
8108 switch (mask)
8109 {
8110 case M_DABS:
8111 dbl = 1;
8112 case M_ABS:
df58fc94
RS
8113 /* bgez $a0,1f
8114 move v0,$a0
8115 sub v0,$zero,$a0
8116 1:
8117 */
252b5132 8118
7d10b47d 8119 start_noreorder ();
252b5132 8120
df58fc94
RS
8121 if (mips_opts.micromips)
8122 micromips_label_expr (&label_expr);
8123 else
8124 label_expr.X_add_number = 8;
8125 macro_build (&label_expr, "bgez", "s,p", sreg);
252b5132 8126 if (dreg == sreg)
a605d2b3 8127 macro_build (NULL, "nop", "");
252b5132 8128 else
67c0d1eb
RS
8129 move_register (dreg, sreg);
8130 macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, 0, sreg);
df58fc94
RS
8131 if (mips_opts.micromips)
8132 micromips_add_label ();
252b5132 8133
7d10b47d 8134 end_noreorder ();
8fc2e39e 8135 break;
252b5132
RH
8136
8137 case M_ADD_I:
8138 s = "addi";
8139 s2 = "add";
8140 goto do_addi;
8141 case M_ADDU_I:
8142 s = "addiu";
8143 s2 = "addu";
8144 goto do_addi;
8145 case M_DADD_I:
8146 dbl = 1;
8147 s = "daddi";
8148 s2 = "dadd";
df58fc94
RS
8149 if (!mips_opts.micromips)
8150 goto do_addi;
8151 if (imm_expr.X_op == O_constant
8152 && imm_expr.X_add_number >= -0x200
8153 && imm_expr.X_add_number < 0x200)
8154 {
8155 macro_build (NULL, s, "t,r,.", treg, sreg, imm_expr.X_add_number);
8156 break;
8157 }
8158 goto do_addi_i;
252b5132
RH
8159 case M_DADDU_I:
8160 dbl = 1;
8161 s = "daddiu";
8162 s2 = "daddu";
8163 do_addi:
8164 if (imm_expr.X_op == O_constant
8165 && imm_expr.X_add_number >= -0x8000
8166 && imm_expr.X_add_number < 0x8000)
8167 {
67c0d1eb 8168 macro_build (&imm_expr, s, "t,r,j", treg, sreg, BFD_RELOC_LO16);
8fc2e39e 8169 break;
252b5132 8170 }
df58fc94 8171 do_addi_i:
8fc2e39e 8172 used_at = 1;
67c0d1eb
RS
8173 load_register (AT, &imm_expr, dbl);
8174 macro_build (NULL, s2, "d,v,t", treg, sreg, AT);
252b5132
RH
8175 break;
8176
8177 case M_AND_I:
8178 s = "andi";
8179 s2 = "and";
8180 goto do_bit;
8181 case M_OR_I:
8182 s = "ori";
8183 s2 = "or";
8184 goto do_bit;
8185 case M_NOR_I:
8186 s = "";
8187 s2 = "nor";
8188 goto do_bit;
8189 case M_XOR_I:
8190 s = "xori";
8191 s2 = "xor";
8192 do_bit:
8193 if (imm_expr.X_op == O_constant
8194 && imm_expr.X_add_number >= 0
8195 && imm_expr.X_add_number < 0x10000)
8196 {
8197 if (mask != M_NOR_I)
67c0d1eb 8198 macro_build (&imm_expr, s, "t,r,i", treg, sreg, BFD_RELOC_LO16);
252b5132
RH
8199 else
8200 {
67c0d1eb
RS
8201 macro_build (&imm_expr, "ori", "t,r,i",
8202 treg, sreg, BFD_RELOC_LO16);
8203 macro_build (NULL, "nor", "d,v,t", treg, treg, 0);
252b5132 8204 }
8fc2e39e 8205 break;
252b5132
RH
8206 }
8207
8fc2e39e 8208 used_at = 1;
67c0d1eb
RS
8209 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
8210 macro_build (NULL, s2, "d,v,t", treg, sreg, AT);
252b5132
RH
8211 break;
8212
8b082fb1
TS
8213 case M_BALIGN:
8214 switch (imm_expr.X_add_number)
8215 {
8216 case 0:
8217 macro_build (NULL, "nop", "");
8218 break;
8219 case 2:
8220 macro_build (NULL, "packrl.ph", "d,s,t", treg, treg, sreg);
8221 break;
03f66e8a
MR
8222 case 1:
8223 case 3:
8b082fb1 8224 macro_build (NULL, "balign", "t,s,2", treg, sreg,
90ecf173 8225 (int) imm_expr.X_add_number);
8b082fb1 8226 break;
03f66e8a
MR
8227 default:
8228 as_bad (_("BALIGN immediate not 0, 1, 2 or 3 (%lu)"),
8229 (unsigned long) imm_expr.X_add_number);
8230 break;
8b082fb1
TS
8231 }
8232 break;
8233
df58fc94
RS
8234 case M_BC1FL:
8235 case M_BC1TL:
8236 case M_BC2FL:
8237 case M_BC2TL:
8238 gas_assert (mips_opts.micromips);
8239 macro_build_branch_ccl (mask, &offset_expr,
8240 EXTRACT_OPERAND (1, BCC, *ip));
8241 break;
8242
252b5132 8243 case M_BEQ_I:
252b5132 8244 case M_BEQL_I:
252b5132 8245 case M_BNE_I:
252b5132 8246 case M_BNEL_I:
252b5132 8247 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
df58fc94
RS
8248 treg = 0;
8249 else
252b5132 8250 {
df58fc94
RS
8251 treg = AT;
8252 used_at = 1;
8253 load_register (treg, &imm_expr, HAVE_64BIT_GPRS);
252b5132 8254 }
df58fc94
RS
8255 /* Fall through. */
8256 case M_BEQL:
8257 case M_BNEL:
8258 macro_build_branch_rsrt (mask, &offset_expr, sreg, treg);
252b5132
RH
8259 break;
8260
8261 case M_BGEL:
8262 likely = 1;
8263 case M_BGE:
8264 if (treg == 0)
df58fc94
RS
8265 macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, sreg);
8266 else if (sreg == 0)
8267 macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, treg);
8268 else
252b5132 8269 {
df58fc94
RS
8270 used_at = 1;
8271 macro_build (NULL, "slt", "d,v,t", AT, sreg, treg);
8272 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
8273 &offset_expr, AT, ZERO);
252b5132 8274 }
df58fc94
RS
8275 break;
8276
8277 case M_BGEZL:
8278 case M_BGEZALL:
8279 case M_BGTZL:
8280 case M_BLEZL:
8281 case M_BLTZL:
8282 case M_BLTZALL:
8283 macro_build_branch_rs (mask, &offset_expr, sreg);
252b5132
RH
8284 break;
8285
8286 case M_BGTL_I:
8287 likely = 1;
8288 case M_BGT_I:
90ecf173 8289 /* Check for > max integer. */
42429eac 8290 if (imm_expr.X_op == O_constant && imm_expr.X_add_number >= GPR_SMAX)
252b5132
RH
8291 {
8292 do_false:
90ecf173 8293 /* Result is always false. */
252b5132 8294 if (! likely)
a605d2b3 8295 macro_build (NULL, "nop", "");
252b5132 8296 else
df58fc94 8297 macro_build_branch_rsrt (M_BNEL, &offset_expr, ZERO, ZERO);
8fc2e39e 8298 break;
252b5132
RH
8299 }
8300 if (imm_expr.X_op != O_constant)
8301 as_bad (_("Unsupported large constant"));
f9419b05 8302 ++imm_expr.X_add_number;
252b5132
RH
8303 /* FALLTHROUGH */
8304 case M_BGE_I:
8305 case M_BGEL_I:
8306 if (mask == M_BGEL_I)
8307 likely = 1;
8308 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
8309 {
df58fc94
RS
8310 macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ,
8311 &offset_expr, sreg);
8fc2e39e 8312 break;
252b5132
RH
8313 }
8314 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
8315 {
df58fc94
RS
8316 macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ,
8317 &offset_expr, sreg);
8fc2e39e 8318 break;
252b5132 8319 }
42429eac 8320 if (imm_expr.X_op == O_constant && imm_expr.X_add_number <= GPR_SMIN)
252b5132
RH
8321 {
8322 do_true:
8323 /* result is always true */
8324 as_warn (_("Branch %s is always true"), ip->insn_mo->name);
67c0d1eb 8325 macro_build (&offset_expr, "b", "p");
8fc2e39e 8326 break;
252b5132 8327 }
8fc2e39e 8328 used_at = 1;
67c0d1eb 8329 set_at (sreg, 0);
df58fc94
RS
8330 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
8331 &offset_expr, AT, ZERO);
252b5132
RH
8332 break;
8333
8334 case M_BGEUL:
8335 likely = 1;
8336 case M_BGEU:
8337 if (treg == 0)
8338 goto do_true;
df58fc94
RS
8339 else if (sreg == 0)
8340 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
8341 &offset_expr, ZERO, treg);
8342 else
252b5132 8343 {
df58fc94
RS
8344 used_at = 1;
8345 macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg);
8346 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
8347 &offset_expr, AT, ZERO);
252b5132 8348 }
252b5132
RH
8349 break;
8350
8351 case M_BGTUL_I:
8352 likely = 1;
8353 case M_BGTU_I:
8354 if (sreg == 0
ca4e0257 8355 || (HAVE_32BIT_GPRS
252b5132 8356 && imm_expr.X_op == O_constant
f01dc953 8357 && imm_expr.X_add_number == -1))
252b5132
RH
8358 goto do_false;
8359 if (imm_expr.X_op != O_constant)
8360 as_bad (_("Unsupported large constant"));
f9419b05 8361 ++imm_expr.X_add_number;
252b5132
RH
8362 /* FALLTHROUGH */
8363 case M_BGEU_I:
8364 case M_BGEUL_I:
8365 if (mask == M_BGEUL_I)
8366 likely = 1;
8367 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
8368 goto do_true;
df58fc94
RS
8369 else if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
8370 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
8371 &offset_expr, sreg, ZERO);
8372 else
252b5132 8373 {
df58fc94
RS
8374 used_at = 1;
8375 set_at (sreg, 1);
8376 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
8377 &offset_expr, AT, ZERO);
252b5132 8378 }
252b5132
RH
8379 break;
8380
8381 case M_BGTL:
8382 likely = 1;
8383 case M_BGT:
8384 if (treg == 0)
df58fc94
RS
8385 macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, sreg);
8386 else if (sreg == 0)
8387 macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, treg);
8388 else
252b5132 8389 {
df58fc94
RS
8390 used_at = 1;
8391 macro_build (NULL, "slt", "d,v,t", AT, treg, sreg);
8392 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
8393 &offset_expr, AT, ZERO);
252b5132 8394 }
252b5132
RH
8395 break;
8396
8397 case M_BGTUL:
8398 likely = 1;
8399 case M_BGTU:
8400 if (treg == 0)
df58fc94
RS
8401 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
8402 &offset_expr, sreg, ZERO);
8403 else if (sreg == 0)
8404 goto do_false;
8405 else
252b5132 8406 {
df58fc94
RS
8407 used_at = 1;
8408 macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg);
8409 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
8410 &offset_expr, AT, ZERO);
252b5132 8411 }
252b5132
RH
8412 break;
8413
8414 case M_BLEL:
8415 likely = 1;
8416 case M_BLE:
8417 if (treg == 0)
df58fc94
RS
8418 macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, sreg);
8419 else if (sreg == 0)
8420 macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, treg);
8421 else
252b5132 8422 {
df58fc94
RS
8423 used_at = 1;
8424 macro_build (NULL, "slt", "d,v,t", AT, treg, sreg);
8425 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
8426 &offset_expr, AT, ZERO);
252b5132 8427 }
252b5132
RH
8428 break;
8429
8430 case M_BLEL_I:
8431 likely = 1;
8432 case M_BLE_I:
42429eac 8433 if (imm_expr.X_op == O_constant && imm_expr.X_add_number >= GPR_SMAX)
252b5132
RH
8434 goto do_true;
8435 if (imm_expr.X_op != O_constant)
8436 as_bad (_("Unsupported large constant"));
f9419b05 8437 ++imm_expr.X_add_number;
252b5132
RH
8438 /* FALLTHROUGH */
8439 case M_BLT_I:
8440 case M_BLTL_I:
8441 if (mask == M_BLTL_I)
8442 likely = 1;
8443 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
df58fc94
RS
8444 macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, sreg);
8445 else if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
8446 macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, sreg);
8447 else
252b5132 8448 {
df58fc94
RS
8449 used_at = 1;
8450 set_at (sreg, 0);
8451 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
8452 &offset_expr, AT, ZERO);
252b5132 8453 }
252b5132
RH
8454 break;
8455
8456 case M_BLEUL:
8457 likely = 1;
8458 case M_BLEU:
8459 if (treg == 0)
df58fc94
RS
8460 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
8461 &offset_expr, sreg, ZERO);
8462 else if (sreg == 0)
8463 goto do_true;
8464 else
252b5132 8465 {
df58fc94
RS
8466 used_at = 1;
8467 macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg);
8468 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
8469 &offset_expr, AT, ZERO);
252b5132 8470 }
252b5132
RH
8471 break;
8472
8473 case M_BLEUL_I:
8474 likely = 1;
8475 case M_BLEU_I:
8476 if (sreg == 0
ca4e0257 8477 || (HAVE_32BIT_GPRS
252b5132 8478 && imm_expr.X_op == O_constant
f01dc953 8479 && imm_expr.X_add_number == -1))
252b5132
RH
8480 goto do_true;
8481 if (imm_expr.X_op != O_constant)
8482 as_bad (_("Unsupported large constant"));
f9419b05 8483 ++imm_expr.X_add_number;
252b5132
RH
8484 /* FALLTHROUGH */
8485 case M_BLTU_I:
8486 case M_BLTUL_I:
8487 if (mask == M_BLTUL_I)
8488 likely = 1;
8489 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
8490 goto do_false;
df58fc94
RS
8491 else if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
8492 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
8493 &offset_expr, sreg, ZERO);
8494 else
252b5132 8495 {
df58fc94
RS
8496 used_at = 1;
8497 set_at (sreg, 1);
8498 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
8499 &offset_expr, AT, ZERO);
252b5132 8500 }
252b5132
RH
8501 break;
8502
8503 case M_BLTL:
8504 likely = 1;
8505 case M_BLT:
8506 if (treg == 0)
df58fc94
RS
8507 macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, sreg);
8508 else if (sreg == 0)
8509 macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, treg);
8510 else
252b5132 8511 {
df58fc94
RS
8512 used_at = 1;
8513 macro_build (NULL, "slt", "d,v,t", AT, sreg, treg);
8514 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
8515 &offset_expr, AT, ZERO);
252b5132 8516 }
252b5132
RH
8517 break;
8518
8519 case M_BLTUL:
8520 likely = 1;
8521 case M_BLTU:
8522 if (treg == 0)
8523 goto do_false;
df58fc94
RS
8524 else if (sreg == 0)
8525 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
8526 &offset_expr, ZERO, treg);
8527 else
252b5132 8528 {
df58fc94
RS
8529 used_at = 1;
8530 macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg);
8531 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
8532 &offset_expr, AT, ZERO);
252b5132 8533 }
252b5132
RH
8534 break;
8535
5f74bc13
CD
8536 case M_DEXT:
8537 {
d5818fca
MR
8538 /* Use unsigned arithmetic. */
8539 addressT pos;
8540 addressT size;
5f74bc13 8541
90ecf173 8542 if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant)
5f74bc13
CD
8543 {
8544 as_bad (_("Unsupported large constant"));
8545 pos = size = 1;
8546 }
8547 else
8548 {
d5818fca
MR
8549 pos = imm_expr.X_add_number;
8550 size = imm2_expr.X_add_number;
5f74bc13
CD
8551 }
8552
8553 if (pos > 63)
8554 {
9e12b7a2 8555 report_bad_range (ip, 3, pos, 0, 63, FALSE);
5f74bc13
CD
8556 pos = 1;
8557 }
90ecf173 8558 if (size == 0 || size > 64 || (pos + size - 1) > 63)
5f74bc13 8559 {
9e12b7a2 8560 report_bad_field (pos, size);
5f74bc13
CD
8561 size = 1;
8562 }
8563
8564 if (size <= 32 && pos < 32)
8565 {
8566 s = "dext";
8567 fmt = "t,r,+A,+C";
8568 }
8569 else if (size <= 32)
8570 {
8571 s = "dextu";
8572 fmt = "t,r,+E,+H";
8573 }
8574 else
8575 {
8576 s = "dextm";
8577 fmt = "t,r,+A,+G";
8578 }
d5818fca
MR
8579 macro_build ((expressionS *) NULL, s, fmt, treg, sreg, (int) pos,
8580 (int) (size - 1));
5f74bc13 8581 }
8fc2e39e 8582 break;
5f74bc13
CD
8583
8584 case M_DINS:
8585 {
d5818fca
MR
8586 /* Use unsigned arithmetic. */
8587 addressT pos;
8588 addressT size;
5f74bc13 8589
90ecf173 8590 if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant)
5f74bc13
CD
8591 {
8592 as_bad (_("Unsupported large constant"));
8593 pos = size = 1;
8594 }
8595 else
8596 {
d5818fca
MR
8597 pos = imm_expr.X_add_number;
8598 size = imm2_expr.X_add_number;
5f74bc13
CD
8599 }
8600
8601 if (pos > 63)
8602 {
9e12b7a2 8603 report_bad_range (ip, 3, pos, 0, 63, FALSE);
5f74bc13
CD
8604 pos = 1;
8605 }
90ecf173 8606 if (size == 0 || size > 64 || (pos + size - 1) > 63)
5f74bc13 8607 {
9e12b7a2 8608 report_bad_field (pos, size);
5f74bc13
CD
8609 size = 1;
8610 }
8611
8612 if (pos < 32 && (pos + size - 1) < 32)
8613 {
8614 s = "dins";
8615 fmt = "t,r,+A,+B";
8616 }
8617 else if (pos >= 32)
8618 {
8619 s = "dinsu";
8620 fmt = "t,r,+E,+F";
8621 }
8622 else
8623 {
8624 s = "dinsm";
8625 fmt = "t,r,+A,+F";
8626 }
750bdd57
AS
8627 macro_build ((expressionS *) NULL, s, fmt, treg, sreg, (int) pos,
8628 (int) (pos + size - 1));
5f74bc13 8629 }
8fc2e39e 8630 break;
5f74bc13 8631
252b5132
RH
8632 case M_DDIV_3:
8633 dbl = 1;
8634 case M_DIV_3:
8635 s = "mflo";
8636 goto do_div3;
8637 case M_DREM_3:
8638 dbl = 1;
8639 case M_REM_3:
8640 s = "mfhi";
8641 do_div3:
8642 if (treg == 0)
8643 {
8644 as_warn (_("Divide by zero."));
8645 if (mips_trap)
df58fc94 8646 macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7);
252b5132 8647 else
df58fc94 8648 macro_build (NULL, "break", BRK_FMT, 7);
8fc2e39e 8649 break;
252b5132
RH
8650 }
8651
7d10b47d 8652 start_noreorder ();
252b5132
RH
8653 if (mips_trap)
8654 {
df58fc94 8655 macro_build (NULL, "teq", TRAP_FMT, treg, ZERO, 7);
67c0d1eb 8656 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg);
252b5132
RH
8657 }
8658 else
8659 {
df58fc94
RS
8660 if (mips_opts.micromips)
8661 micromips_label_expr (&label_expr);
8662 else
8663 label_expr.X_add_number = 8;
8664 macro_build (&label_expr, "bne", "s,t,p", treg, ZERO);
67c0d1eb 8665 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg);
df58fc94
RS
8666 macro_build (NULL, "break", BRK_FMT, 7);
8667 if (mips_opts.micromips)
8668 micromips_add_label ();
252b5132
RH
8669 }
8670 expr1.X_add_number = -1;
8fc2e39e 8671 used_at = 1;
f6a22291 8672 load_register (AT, &expr1, dbl);
df58fc94
RS
8673 if (mips_opts.micromips)
8674 micromips_label_expr (&label_expr);
8675 else
8676 label_expr.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16);
8677 macro_build (&label_expr, "bne", "s,t,p", treg, AT);
252b5132
RH
8678 if (dbl)
8679 {
8680 expr1.X_add_number = 1;
f6a22291 8681 load_register (AT, &expr1, dbl);
df58fc94 8682 macro_build (NULL, "dsll32", SHFT_FMT, AT, AT, 31);
252b5132
RH
8683 }
8684 else
8685 {
8686 expr1.X_add_number = 0x80000000;
df58fc94 8687 macro_build (&expr1, "lui", LUI_FMT, AT, BFD_RELOC_HI16);
252b5132
RH
8688 }
8689 if (mips_trap)
8690 {
df58fc94 8691 macro_build (NULL, "teq", TRAP_FMT, sreg, AT, 6);
252b5132
RH
8692 /* We want to close the noreorder block as soon as possible, so
8693 that later insns are available for delay slot filling. */
7d10b47d 8694 end_noreorder ();
252b5132
RH
8695 }
8696 else
8697 {
df58fc94
RS
8698 if (mips_opts.micromips)
8699 micromips_label_expr (&label_expr);
8700 else
8701 label_expr.X_add_number = 8;
8702 macro_build (&label_expr, "bne", "s,t,p", sreg, AT);
a605d2b3 8703 macro_build (NULL, "nop", "");
252b5132
RH
8704
8705 /* We want to close the noreorder block as soon as possible, so
8706 that later insns are available for delay slot filling. */
7d10b47d 8707 end_noreorder ();
252b5132 8708
df58fc94 8709 macro_build (NULL, "break", BRK_FMT, 6);
252b5132 8710 }
df58fc94
RS
8711 if (mips_opts.micromips)
8712 micromips_add_label ();
8713 macro_build (NULL, s, MFHL_FMT, dreg);
252b5132
RH
8714 break;
8715
8716 case M_DIV_3I:
8717 s = "div";
8718 s2 = "mflo";
8719 goto do_divi;
8720 case M_DIVU_3I:
8721 s = "divu";
8722 s2 = "mflo";
8723 goto do_divi;
8724 case M_REM_3I:
8725 s = "div";
8726 s2 = "mfhi";
8727 goto do_divi;
8728 case M_REMU_3I:
8729 s = "divu";
8730 s2 = "mfhi";
8731 goto do_divi;
8732 case M_DDIV_3I:
8733 dbl = 1;
8734 s = "ddiv";
8735 s2 = "mflo";
8736 goto do_divi;
8737 case M_DDIVU_3I:
8738 dbl = 1;
8739 s = "ddivu";
8740 s2 = "mflo";
8741 goto do_divi;
8742 case M_DREM_3I:
8743 dbl = 1;
8744 s = "ddiv";
8745 s2 = "mfhi";
8746 goto do_divi;
8747 case M_DREMU_3I:
8748 dbl = 1;
8749 s = "ddivu";
8750 s2 = "mfhi";
8751 do_divi:
8752 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
8753 {
8754 as_warn (_("Divide by zero."));
8755 if (mips_trap)
df58fc94 8756 macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7);
252b5132 8757 else
df58fc94 8758 macro_build (NULL, "break", BRK_FMT, 7);
8fc2e39e 8759 break;
252b5132
RH
8760 }
8761 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
8762 {
8763 if (strcmp (s2, "mflo") == 0)
67c0d1eb 8764 move_register (dreg, sreg);
252b5132 8765 else
c80c840e 8766 move_register (dreg, ZERO);
8fc2e39e 8767 break;
252b5132
RH
8768 }
8769 if (imm_expr.X_op == O_constant
8770 && imm_expr.X_add_number == -1
8771 && s[strlen (s) - 1] != 'u')
8772 {
8773 if (strcmp (s2, "mflo") == 0)
8774 {
67c0d1eb 8775 macro_build (NULL, dbl ? "dneg" : "neg", "d,w", dreg, sreg);
252b5132
RH
8776 }
8777 else
c80c840e 8778 move_register (dreg, ZERO);
8fc2e39e 8779 break;
252b5132
RH
8780 }
8781
8fc2e39e 8782 used_at = 1;
67c0d1eb
RS
8783 load_register (AT, &imm_expr, dbl);
8784 macro_build (NULL, s, "z,s,t", sreg, AT);
df58fc94 8785 macro_build (NULL, s2, MFHL_FMT, dreg);
252b5132
RH
8786 break;
8787
8788 case M_DIVU_3:
8789 s = "divu";
8790 s2 = "mflo";
8791 goto do_divu3;
8792 case M_REMU_3:
8793 s = "divu";
8794 s2 = "mfhi";
8795 goto do_divu3;
8796 case M_DDIVU_3:
8797 s = "ddivu";
8798 s2 = "mflo";
8799 goto do_divu3;
8800 case M_DREMU_3:
8801 s = "ddivu";
8802 s2 = "mfhi";
8803 do_divu3:
7d10b47d 8804 start_noreorder ();
252b5132
RH
8805 if (mips_trap)
8806 {
df58fc94 8807 macro_build (NULL, "teq", TRAP_FMT, treg, ZERO, 7);
67c0d1eb 8808 macro_build (NULL, s, "z,s,t", sreg, treg);
252b5132
RH
8809 /* We want to close the noreorder block as soon as possible, so
8810 that later insns are available for delay slot filling. */
7d10b47d 8811 end_noreorder ();
252b5132
RH
8812 }
8813 else
8814 {
df58fc94
RS
8815 if (mips_opts.micromips)
8816 micromips_label_expr (&label_expr);
8817 else
8818 label_expr.X_add_number = 8;
8819 macro_build (&label_expr, "bne", "s,t,p", treg, ZERO);
67c0d1eb 8820 macro_build (NULL, s, "z,s,t", sreg, treg);
252b5132
RH
8821
8822 /* We want to close the noreorder block as soon as possible, so
8823 that later insns are available for delay slot filling. */
7d10b47d 8824 end_noreorder ();
df58fc94
RS
8825 macro_build (NULL, "break", BRK_FMT, 7);
8826 if (mips_opts.micromips)
8827 micromips_add_label ();
252b5132 8828 }
df58fc94 8829 macro_build (NULL, s2, MFHL_FMT, dreg);
8fc2e39e 8830 break;
252b5132 8831
1abe91b1
MR
8832 case M_DLCA_AB:
8833 dbl = 1;
8834 case M_LCA_AB:
8835 call = 1;
8836 goto do_la;
252b5132
RH
8837 case M_DLA_AB:
8838 dbl = 1;
8839 case M_LA_AB:
1abe91b1 8840 do_la:
252b5132
RH
8841 /* Load the address of a symbol into a register. If breg is not
8842 zero, we then add a base register to it. */
8843
3bec30a8
TS
8844 if (dbl && HAVE_32BIT_GPRS)
8845 as_warn (_("dla used to load 32-bit register"));
8846
90ecf173 8847 if (!dbl && HAVE_64BIT_OBJECTS)
3bec30a8
TS
8848 as_warn (_("la used to load 64-bit address"));
8849
f2ae14a1 8850 if (small_offset_p (0, align, 16))
0c11417f 8851 {
f2ae14a1
RS
8852 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", treg, breg,
8853 -1, offset_reloc[0], offset_reloc[1], offset_reloc[2]);
8fc2e39e 8854 break;
0c11417f
MR
8855 }
8856
741fe287 8857 if (mips_opts.at && (treg == breg))
afdbd6d0
CD
8858 {
8859 tempreg = AT;
8860 used_at = 1;
8861 }
8862 else
8863 {
8864 tempreg = treg;
afdbd6d0
CD
8865 }
8866
252b5132
RH
8867 if (offset_expr.X_op != O_symbol
8868 && offset_expr.X_op != O_constant)
8869 {
f71d0d44 8870 as_bad (_("Expression too complex"));
252b5132
RH
8871 offset_expr.X_op = O_constant;
8872 }
8873
252b5132 8874 if (offset_expr.X_op == O_constant)
aed1a261 8875 load_register (tempreg, &offset_expr, HAVE_64BIT_ADDRESSES);
252b5132
RH
8876 else if (mips_pic == NO_PIC)
8877 {
d6bc6245 8878 /* If this is a reference to a GP relative symbol, we want
cdf6fd85 8879 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
252b5132
RH
8880 Otherwise we want
8881 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
8882 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
8883 If we have a constant, we need two instructions anyhow,
d6bc6245 8884 so we may as well always use the latter form.
76b3015f 8885
6caf9ef4
TS
8886 With 64bit address space and a usable $at we want
8887 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8888 lui $at,<sym> (BFD_RELOC_HI16_S)
8889 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
8890 daddiu $at,<sym> (BFD_RELOC_LO16)
8891 dsll32 $tempreg,0
8892 daddu $tempreg,$tempreg,$at
8893
8894 If $at is already in use, we use a path which is suboptimal
8895 on superscalar processors.
8896 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8897 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
8898 dsll $tempreg,16
8899 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
8900 dsll $tempreg,16
8901 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
8902
8903 For GP relative symbols in 64bit address space we can use
8904 the same sequence as in 32bit address space. */
aed1a261 8905 if (HAVE_64BIT_SYMBOLS)
252b5132 8906 {
6caf9ef4
TS
8907 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
8908 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
8909 {
8910 relax_start (offset_expr.X_add_symbol);
8911 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
8912 tempreg, mips_gp_register, BFD_RELOC_GPREL16);
8913 relax_switch ();
8914 }
d6bc6245 8915
741fe287 8916 if (used_at == 0 && mips_opts.at)
98d3f06f 8917 {
df58fc94 8918 macro_build (&offset_expr, "lui", LUI_FMT,
17a2f251 8919 tempreg, BFD_RELOC_MIPS_HIGHEST);
df58fc94 8920 macro_build (&offset_expr, "lui", LUI_FMT,
17a2f251 8921 AT, BFD_RELOC_HI16_S);
67c0d1eb 8922 macro_build (&offset_expr, "daddiu", "t,r,j",
17a2f251 8923 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
67c0d1eb 8924 macro_build (&offset_expr, "daddiu", "t,r,j",
17a2f251 8925 AT, AT, BFD_RELOC_LO16);
df58fc94 8926 macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0);
67c0d1eb 8927 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT);
98d3f06f
KH
8928 used_at = 1;
8929 }
8930 else
8931 {
df58fc94 8932 macro_build (&offset_expr, "lui", LUI_FMT,
17a2f251 8933 tempreg, BFD_RELOC_MIPS_HIGHEST);
67c0d1eb 8934 macro_build (&offset_expr, "daddiu", "t,r,j",
17a2f251 8935 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
df58fc94 8936 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
67c0d1eb 8937 macro_build (&offset_expr, "daddiu", "t,r,j",
17a2f251 8938 tempreg, tempreg, BFD_RELOC_HI16_S);
df58fc94 8939 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
67c0d1eb 8940 macro_build (&offset_expr, "daddiu", "t,r,j",
17a2f251 8941 tempreg, tempreg, BFD_RELOC_LO16);
98d3f06f 8942 }
6caf9ef4
TS
8943
8944 if (mips_relax.sequence)
8945 relax_end ();
98d3f06f
KH
8946 }
8947 else
8948 {
8949 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
6caf9ef4 8950 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
98d3f06f 8951 {
4d7206a2 8952 relax_start (offset_expr.X_add_symbol);
67c0d1eb
RS
8953 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
8954 tempreg, mips_gp_register, BFD_RELOC_GPREL16);
4d7206a2 8955 relax_switch ();
98d3f06f 8956 }
6943caf0 8957 if (!IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
f71d0d44 8958 as_bad (_("Offset too large"));
67c0d1eb
RS
8959 macro_build_lui (&offset_expr, tempreg);
8960 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
8961 tempreg, tempreg, BFD_RELOC_LO16);
4d7206a2
RS
8962 if (mips_relax.sequence)
8963 relax_end ();
98d3f06f 8964 }
252b5132 8965 }
0a44bf69 8966 else if (!mips_big_got && !HAVE_NEWABI)
252b5132 8967 {
9117d219
NC
8968 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
8969
252b5132
RH
8970 /* If this is a reference to an external symbol, and there
8971 is no constant, we want
8972 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
1abe91b1 8973 or for lca or if tempreg is PIC_CALL_REG
9117d219 8974 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
252b5132
RH
8975 For a local symbol, we want
8976 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8977 nop
8978 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
8979
8980 If we have a small constant, and this is a reference to
8981 an external symbol, we want
8982 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8983 nop
8984 addiu $tempreg,$tempreg,<constant>
8985 For a local symbol, we want the same instruction
8986 sequence, but we output a BFD_RELOC_LO16 reloc on the
8987 addiu instruction.
8988
8989 If we have a large constant, and this is a reference to
8990 an external symbol, we want
8991 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8992 lui $at,<hiconstant>
8993 addiu $at,$at,<loconstant>
8994 addu $tempreg,$tempreg,$at
8995 For a local symbol, we want the same instruction
8996 sequence, but we output a BFD_RELOC_LO16 reloc on the
ed6fb7bd 8997 addiu instruction.
ed6fb7bd
SC
8998 */
8999
4d7206a2 9000 if (offset_expr.X_add_number == 0)
252b5132 9001 {
0a44bf69
RS
9002 if (mips_pic == SVR4_PIC
9003 && breg == 0
9004 && (call || tempreg == PIC_CALL_REG))
4d7206a2
RS
9005 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16;
9006
9007 relax_start (offset_expr.X_add_symbol);
67c0d1eb
RS
9008 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
9009 lw_reloc_type, mips_gp_register);
4d7206a2 9010 if (breg != 0)
252b5132
RH
9011 {
9012 /* We're going to put in an addu instruction using
9013 tempreg, so we may as well insert the nop right
9014 now. */
269137b2 9015 load_delay_nop ();
252b5132 9016 }
4d7206a2 9017 relax_switch ();
67c0d1eb
RS
9018 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
9019 tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register);
269137b2 9020 load_delay_nop ();
67c0d1eb
RS
9021 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
9022 tempreg, tempreg, BFD_RELOC_LO16);
4d7206a2 9023 relax_end ();
252b5132
RH
9024 /* FIXME: If breg == 0, and the next instruction uses
9025 $tempreg, then if this variant case is used an extra
9026 nop will be generated. */
9027 }
4d7206a2
RS
9028 else if (offset_expr.X_add_number >= -0x8000
9029 && offset_expr.X_add_number < 0x8000)
252b5132 9030 {
67c0d1eb 9031 load_got_offset (tempreg, &offset_expr);
269137b2 9032 load_delay_nop ();
67c0d1eb 9033 add_got_offset (tempreg, &offset_expr);
252b5132
RH
9034 }
9035 else
9036 {
4d7206a2
RS
9037 expr1.X_add_number = offset_expr.X_add_number;
9038 offset_expr.X_add_number =
43c0598f 9039 SEXT_16BIT (offset_expr.X_add_number);
67c0d1eb 9040 load_got_offset (tempreg, &offset_expr);
f6a22291 9041 offset_expr.X_add_number = expr1.X_add_number;
252b5132
RH
9042 /* If we are going to add in a base register, and the
9043 target register and the base register are the same,
9044 then we are using AT as a temporary register. Since
9045 we want to load the constant into AT, we add our
9046 current AT (from the global offset table) and the
9047 register into the register now, and pretend we were
9048 not using a base register. */
67c0d1eb 9049 if (breg == treg)
252b5132 9050 {
269137b2 9051 load_delay_nop ();
67c0d1eb 9052 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
17a2f251 9053 treg, AT, breg);
252b5132
RH
9054 breg = 0;
9055 tempreg = treg;
252b5132 9056 }
f6a22291 9057 add_got_offset_hilo (tempreg, &offset_expr, AT);
252b5132
RH
9058 used_at = 1;
9059 }
9060 }
0a44bf69 9061 else if (!mips_big_got && HAVE_NEWABI)
f5040a92 9062 {
67c0d1eb 9063 int add_breg_early = 0;
f5040a92
AO
9064
9065 /* If this is a reference to an external, and there is no
9066 constant, or local symbol (*), with or without a
9067 constant, we want
9068 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
1abe91b1 9069 or for lca or if tempreg is PIC_CALL_REG
f5040a92
AO
9070 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
9071
9072 If we have a small constant, and this is a reference to
9073 an external symbol, we want
9074 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
9075 addiu $tempreg,$tempreg,<constant>
9076
9077 If we have a large constant, and this is a reference to
9078 an external symbol, we want
9079 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
9080 lui $at,<hiconstant>
9081 addiu $at,$at,<loconstant>
9082 addu $tempreg,$tempreg,$at
9083
9084 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
9085 local symbols, even though it introduces an additional
9086 instruction. */
9087
f5040a92
AO
9088 if (offset_expr.X_add_number)
9089 {
4d7206a2 9090 expr1.X_add_number = offset_expr.X_add_number;
f5040a92
AO
9091 offset_expr.X_add_number = 0;
9092
4d7206a2 9093 relax_start (offset_expr.X_add_symbol);
67c0d1eb
RS
9094 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
9095 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
f5040a92
AO
9096
9097 if (expr1.X_add_number >= -0x8000
9098 && expr1.X_add_number < 0x8000)
9099 {
67c0d1eb
RS
9100 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
9101 tempreg, tempreg, BFD_RELOC_LO16);
f5040a92 9102 }
ecd13cd3 9103 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
f5040a92 9104 {
f5040a92
AO
9105 /* If we are going to add in a base register, and the
9106 target register and the base register are the same,
9107 then we are using AT as a temporary register. Since
9108 we want to load the constant into AT, we add our
9109 current AT (from the global offset table) and the
9110 register into the register now, and pretend we were
9111 not using a base register. */
9112 if (breg != treg)
9113 dreg = tempreg;
9114 else
9115 {
9c2799c2 9116 gas_assert (tempreg == AT);
67c0d1eb
RS
9117 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9118 treg, AT, breg);
f5040a92 9119 dreg = treg;
67c0d1eb 9120 add_breg_early = 1;
f5040a92
AO
9121 }
9122
f6a22291 9123 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
67c0d1eb 9124 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
17a2f251 9125 dreg, dreg, AT);
f5040a92 9126
f5040a92
AO
9127 used_at = 1;
9128 }
9129 else
9130 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
9131
4d7206a2 9132 relax_switch ();
f5040a92
AO
9133 offset_expr.X_add_number = expr1.X_add_number;
9134
67c0d1eb
RS
9135 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
9136 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
9137 if (add_breg_early)
f5040a92 9138 {
67c0d1eb 9139 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
f899b4b8 9140 treg, tempreg, breg);
f5040a92
AO
9141 breg = 0;
9142 tempreg = treg;
9143 }
4d7206a2 9144 relax_end ();
f5040a92 9145 }
4d7206a2 9146 else if (breg == 0 && (call || tempreg == PIC_CALL_REG))
f5040a92 9147 {
4d7206a2 9148 relax_start (offset_expr.X_add_symbol);
67c0d1eb
RS
9149 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
9150 BFD_RELOC_MIPS_CALL16, mips_gp_register);
4d7206a2 9151 relax_switch ();
67c0d1eb
RS
9152 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
9153 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
4d7206a2 9154 relax_end ();
f5040a92 9155 }
4d7206a2 9156 else
f5040a92 9157 {
67c0d1eb
RS
9158 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
9159 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
f5040a92
AO
9160 }
9161 }
0a44bf69 9162 else if (mips_big_got && !HAVE_NEWABI)
252b5132 9163 {
67c0d1eb 9164 int gpdelay;
9117d219
NC
9165 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
9166 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
ed6fb7bd 9167 int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
252b5132
RH
9168
9169 /* This is the large GOT case. If this is a reference to an
9170 external symbol, and there is no constant, we want
9171 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
9172 addu $tempreg,$tempreg,$gp
9173 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
1abe91b1 9174 or for lca or if tempreg is PIC_CALL_REG
9117d219
NC
9175 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
9176 addu $tempreg,$tempreg,$gp
9177 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
252b5132
RH
9178 For a local symbol, we want
9179 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9180 nop
9181 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
9182
9183 If we have a small constant, and this is a reference to
9184 an external symbol, we want
9185 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
9186 addu $tempreg,$tempreg,$gp
9187 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
9188 nop
9189 addiu $tempreg,$tempreg,<constant>
9190 For a local symbol, we want
9191 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9192 nop
9193 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
9194
9195 If we have a large constant, and this is a reference to
9196 an external symbol, we want
9197 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
9198 addu $tempreg,$tempreg,$gp
9199 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
9200 lui $at,<hiconstant>
9201 addiu $at,$at,<loconstant>
9202 addu $tempreg,$tempreg,$at
9203 For a local symbol, we want
9204 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9205 lui $at,<hiconstant>
9206 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
9207 addu $tempreg,$tempreg,$at
f5040a92 9208 */
438c16b8 9209
252b5132
RH
9210 expr1.X_add_number = offset_expr.X_add_number;
9211 offset_expr.X_add_number = 0;
4d7206a2 9212 relax_start (offset_expr.X_add_symbol);
67c0d1eb 9213 gpdelay = reg_needs_delay (mips_gp_register);
1abe91b1
MR
9214 if (expr1.X_add_number == 0 && breg == 0
9215 && (call || tempreg == PIC_CALL_REG))
9117d219
NC
9216 {
9217 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
9218 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
9219 }
df58fc94 9220 macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type);
67c0d1eb 9221 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
17a2f251 9222 tempreg, tempreg, mips_gp_register);
67c0d1eb 9223 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
17a2f251 9224 tempreg, lw_reloc_type, tempreg);
252b5132
RH
9225 if (expr1.X_add_number == 0)
9226 {
67c0d1eb 9227 if (breg != 0)
252b5132
RH
9228 {
9229 /* We're going to put in an addu instruction using
9230 tempreg, so we may as well insert the nop right
9231 now. */
269137b2 9232 load_delay_nop ();
252b5132 9233 }
252b5132
RH
9234 }
9235 else if (expr1.X_add_number >= -0x8000
9236 && expr1.X_add_number < 0x8000)
9237 {
269137b2 9238 load_delay_nop ();
67c0d1eb 9239 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
17a2f251 9240 tempreg, tempreg, BFD_RELOC_LO16);
252b5132
RH
9241 }
9242 else
9243 {
252b5132
RH
9244 /* If we are going to add in a base register, and the
9245 target register and the base register are the same,
9246 then we are using AT as a temporary register. Since
9247 we want to load the constant into AT, we add our
9248 current AT (from the global offset table) and the
9249 register into the register now, and pretend we were
9250 not using a base register. */
9251 if (breg != treg)
67c0d1eb 9252 dreg = tempreg;
252b5132
RH
9253 else
9254 {
9c2799c2 9255 gas_assert (tempreg == AT);
269137b2 9256 load_delay_nop ();
67c0d1eb 9257 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
17a2f251 9258 treg, AT, breg);
252b5132 9259 dreg = treg;
252b5132
RH
9260 }
9261
f6a22291 9262 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
67c0d1eb 9263 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
252b5132 9264
252b5132
RH
9265 used_at = 1;
9266 }
43c0598f 9267 offset_expr.X_add_number = SEXT_16BIT (expr1.X_add_number);
4d7206a2 9268 relax_switch ();
252b5132 9269
67c0d1eb 9270 if (gpdelay)
252b5132
RH
9271 {
9272 /* This is needed because this instruction uses $gp, but
f5040a92 9273 the first instruction on the main stream does not. */
67c0d1eb 9274 macro_build (NULL, "nop", "");
252b5132 9275 }
ed6fb7bd 9276
67c0d1eb
RS
9277 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
9278 local_reloc_type, mips_gp_register);
f5040a92 9279 if (expr1.X_add_number >= -0x8000
252b5132
RH
9280 && expr1.X_add_number < 0x8000)
9281 {
269137b2 9282 load_delay_nop ();
67c0d1eb
RS
9283 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
9284 tempreg, tempreg, BFD_RELOC_LO16);
252b5132 9285 /* FIXME: If add_number is 0, and there was no base
f5040a92
AO
9286 register, the external symbol case ended with a load,
9287 so if the symbol turns out to not be external, and
9288 the next instruction uses tempreg, an unnecessary nop
9289 will be inserted. */
252b5132
RH
9290 }
9291 else
9292 {
9293 if (breg == treg)
9294 {
9295 /* We must add in the base register now, as in the
f5040a92 9296 external symbol case. */
9c2799c2 9297 gas_assert (tempreg == AT);
269137b2 9298 load_delay_nop ();
67c0d1eb 9299 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
17a2f251 9300 treg, AT, breg);
252b5132
RH
9301 tempreg = treg;
9302 /* We set breg to 0 because we have arranged to add
f5040a92 9303 it in in both cases. */
252b5132
RH
9304 breg = 0;
9305 }
9306
67c0d1eb
RS
9307 macro_build_lui (&expr1, AT);
9308 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
17a2f251 9309 AT, AT, BFD_RELOC_LO16);
67c0d1eb 9310 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
17a2f251 9311 tempreg, tempreg, AT);
8fc2e39e 9312 used_at = 1;
252b5132 9313 }
4d7206a2 9314 relax_end ();
252b5132 9315 }
0a44bf69 9316 else if (mips_big_got && HAVE_NEWABI)
f5040a92 9317 {
f5040a92
AO
9318 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
9319 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
67c0d1eb 9320 int add_breg_early = 0;
f5040a92
AO
9321
9322 /* This is the large GOT case. If this is a reference to an
9323 external symbol, and there is no constant, we want
9324 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
9325 add $tempreg,$tempreg,$gp
9326 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
1abe91b1 9327 or for lca or if tempreg is PIC_CALL_REG
f5040a92
AO
9328 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
9329 add $tempreg,$tempreg,$gp
9330 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
9331
9332 If we have a small constant, and this is a reference to
9333 an external symbol, we want
9334 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
9335 add $tempreg,$tempreg,$gp
9336 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
9337 addi $tempreg,$tempreg,<constant>
9338
9339 If we have a large constant, and this is a reference to
9340 an external symbol, we want
9341 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
9342 addu $tempreg,$tempreg,$gp
9343 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
9344 lui $at,<hiconstant>
9345 addi $at,$at,<loconstant>
9346 add $tempreg,$tempreg,$at
9347
9348 If we have NewABI, and we know it's a local symbol, we want
9349 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
9350 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
9351 otherwise we have to resort to GOT_HI16/GOT_LO16. */
9352
4d7206a2 9353 relax_start (offset_expr.X_add_symbol);
f5040a92 9354
4d7206a2 9355 expr1.X_add_number = offset_expr.X_add_number;
f5040a92
AO
9356 offset_expr.X_add_number = 0;
9357
1abe91b1
MR
9358 if (expr1.X_add_number == 0 && breg == 0
9359 && (call || tempreg == PIC_CALL_REG))
f5040a92
AO
9360 {
9361 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
9362 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
9363 }
df58fc94 9364 macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type);
67c0d1eb 9365 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
17a2f251 9366 tempreg, tempreg, mips_gp_register);
67c0d1eb
RS
9367 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
9368 tempreg, lw_reloc_type, tempreg);
f5040a92
AO
9369
9370 if (expr1.X_add_number == 0)
4d7206a2 9371 ;
f5040a92
AO
9372 else if (expr1.X_add_number >= -0x8000
9373 && expr1.X_add_number < 0x8000)
9374 {
67c0d1eb 9375 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
17a2f251 9376 tempreg, tempreg, BFD_RELOC_LO16);
f5040a92 9377 }
ecd13cd3 9378 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
f5040a92 9379 {
f5040a92
AO
9380 /* If we are going to add in a base register, and the
9381 target register and the base register are the same,
9382 then we are using AT as a temporary register. Since
9383 we want to load the constant into AT, we add our
9384 current AT (from the global offset table) and the
9385 register into the register now, and pretend we were
9386 not using a base register. */
9387 if (breg != treg)
9388 dreg = tempreg;
9389 else
9390 {
9c2799c2 9391 gas_assert (tempreg == AT);
67c0d1eb 9392 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
17a2f251 9393 treg, AT, breg);
f5040a92 9394 dreg = treg;
67c0d1eb 9395 add_breg_early = 1;
f5040a92
AO
9396 }
9397
f6a22291 9398 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
67c0d1eb 9399 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
f5040a92 9400
f5040a92
AO
9401 used_at = 1;
9402 }
9403 else
9404 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
9405
4d7206a2 9406 relax_switch ();
f5040a92 9407 offset_expr.X_add_number = expr1.X_add_number;
67c0d1eb
RS
9408 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
9409 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
9410 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
9411 tempreg, BFD_RELOC_MIPS_GOT_OFST);
9412 if (add_breg_early)
f5040a92 9413 {
67c0d1eb 9414 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
17a2f251 9415 treg, tempreg, breg);
f5040a92
AO
9416 breg = 0;
9417 tempreg = treg;
9418 }
4d7206a2 9419 relax_end ();
f5040a92 9420 }
252b5132
RH
9421 else
9422 abort ();
9423
9424 if (breg != 0)
aed1a261 9425 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", treg, tempreg, breg);
252b5132
RH
9426 break;
9427
52b6b6b9 9428 case M_MSGSND:
df58fc94 9429 gas_assert (!mips_opts.micromips);
c8276761 9430 macro_build (NULL, "c2", "C", (treg << 16) | 0x01);
c7af4273 9431 break;
52b6b6b9
JM
9432
9433 case M_MSGLD:
df58fc94 9434 gas_assert (!mips_opts.micromips);
c8276761 9435 macro_build (NULL, "c2", "C", 0x02);
c7af4273 9436 break;
52b6b6b9
JM
9437
9438 case M_MSGLD_T:
df58fc94 9439 gas_assert (!mips_opts.micromips);
c8276761 9440 macro_build (NULL, "c2", "C", (treg << 16) | 0x02);
c7af4273 9441 break;
52b6b6b9
JM
9442
9443 case M_MSGWAIT:
df58fc94 9444 gas_assert (!mips_opts.micromips);
52b6b6b9 9445 macro_build (NULL, "c2", "C", 3);
c7af4273 9446 break;
52b6b6b9
JM
9447
9448 case M_MSGWAIT_T:
df58fc94 9449 gas_assert (!mips_opts.micromips);
c8276761 9450 macro_build (NULL, "c2", "C", (treg << 16) | 0x03);
c7af4273 9451 break;
52b6b6b9 9452
252b5132
RH
9453 case M_J_A:
9454 /* The j instruction may not be used in PIC code, since it
9455 requires an absolute address. We convert it to a b
9456 instruction. */
9457 if (mips_pic == NO_PIC)
67c0d1eb 9458 macro_build (&offset_expr, "j", "a");
252b5132 9459 else
67c0d1eb 9460 macro_build (&offset_expr, "b", "p");
8fc2e39e 9461 break;
252b5132
RH
9462
9463 /* The jal instructions must be handled as macros because when
9464 generating PIC code they expand to multi-instruction
9465 sequences. Normally they are simple instructions. */
df58fc94
RS
9466 case M_JALS_1:
9467 dreg = RA;
9468 /* Fall through. */
9469 case M_JALS_2:
9470 gas_assert (mips_opts.micromips);
833794fc
MR
9471 if (mips_opts.insn32)
9472 {
9473 as_bad (_("Opcode not supported in the `insn32' mode `%s'"), str);
9474 break;
9475 }
df58fc94
RS
9476 jals = 1;
9477 goto jal;
252b5132
RH
9478 case M_JAL_1:
9479 dreg = RA;
9480 /* Fall through. */
9481 case M_JAL_2:
df58fc94 9482 jal:
3e722fb5 9483 if (mips_pic == NO_PIC)
df58fc94
RS
9484 {
9485 s = jals ? "jalrs" : "jalr";
e64af278 9486 if (mips_opts.micromips
833794fc 9487 && !mips_opts.insn32
e64af278
MR
9488 && dreg == RA
9489 && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
df58fc94
RS
9490 macro_build (NULL, s, "mj", sreg);
9491 else
9492 macro_build (NULL, s, JALR_FMT, dreg, sreg);
9493 }
0a44bf69 9494 else
252b5132 9495 {
df58fc94
RS
9496 int cprestore = (mips_pic == SVR4_PIC && !HAVE_NEWABI
9497 && mips_cprestore_offset >= 0);
9498
252b5132
RH
9499 if (sreg != PIC_CALL_REG)
9500 as_warn (_("MIPS PIC call to register other than $25"));
bdaaa2e1 9501
833794fc
MR
9502 s = ((mips_opts.micromips
9503 && !mips_opts.insn32
9504 && (!mips_opts.noreorder || cprestore))
df58fc94 9505 ? "jalrs" : "jalr");
e64af278 9506 if (mips_opts.micromips
833794fc 9507 && !mips_opts.insn32
e64af278
MR
9508 && dreg == RA
9509 && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
df58fc94
RS
9510 macro_build (NULL, s, "mj", sreg);
9511 else
9512 macro_build (NULL, s, JALR_FMT, dreg, sreg);
0a44bf69 9513 if (mips_pic == SVR4_PIC && !HAVE_NEWABI)
252b5132 9514 {
6478892d
TS
9515 if (mips_cprestore_offset < 0)
9516 as_warn (_("No .cprestore pseudo-op used in PIC code"));
9517 else
9518 {
90ecf173 9519 if (!mips_frame_reg_valid)
7a621144
DJ
9520 {
9521 as_warn (_("No .frame pseudo-op used in PIC code"));
9522 /* Quiet this warning. */
9523 mips_frame_reg_valid = 1;
9524 }
90ecf173 9525 if (!mips_cprestore_valid)
7a621144
DJ
9526 {
9527 as_warn (_("No .cprestore pseudo-op used in PIC code"));
9528 /* Quiet this warning. */
9529 mips_cprestore_valid = 1;
9530 }
d3fca0b5
MR
9531 if (mips_opts.noreorder)
9532 macro_build (NULL, "nop", "");
6478892d 9533 expr1.X_add_number = mips_cprestore_offset;
67c0d1eb 9534 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
f899b4b8 9535 mips_gp_register,
256ab948
TS
9536 mips_frame_reg,
9537 HAVE_64BIT_ADDRESSES);
6478892d 9538 }
252b5132
RH
9539 }
9540 }
252b5132 9541
8fc2e39e 9542 break;
252b5132 9543
df58fc94
RS
9544 case M_JALS_A:
9545 gas_assert (mips_opts.micromips);
833794fc
MR
9546 if (mips_opts.insn32)
9547 {
9548 as_bad (_("Opcode not supported in the `insn32' mode `%s'"), str);
9549 break;
9550 }
df58fc94
RS
9551 jals = 1;
9552 /* Fall through. */
252b5132
RH
9553 case M_JAL_A:
9554 if (mips_pic == NO_PIC)
df58fc94 9555 macro_build (&offset_expr, jals ? "jals" : "jal", "a");
252b5132
RH
9556 else if (mips_pic == SVR4_PIC)
9557 {
9558 /* If this is a reference to an external symbol, and we are
9559 using a small GOT, we want
9560 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
9561 nop
f9419b05 9562 jalr $ra,$25
252b5132
RH
9563 nop
9564 lw $gp,cprestore($sp)
9565 The cprestore value is set using the .cprestore
9566 pseudo-op. If we are using a big GOT, we want
9567 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
9568 addu $25,$25,$gp
9569 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
9570 nop
f9419b05 9571 jalr $ra,$25
252b5132
RH
9572 nop
9573 lw $gp,cprestore($sp)
9574 If the symbol is not external, we want
9575 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9576 nop
9577 addiu $25,$25,<sym> (BFD_RELOC_LO16)
f9419b05 9578 jalr $ra,$25
252b5132 9579 nop
438c16b8 9580 lw $gp,cprestore($sp)
f5040a92
AO
9581
9582 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
9583 sequences above, minus nops, unless the symbol is local,
9584 which enables us to use GOT_PAGE/GOT_OFST (big got) or
9585 GOT_DISP. */
438c16b8 9586 if (HAVE_NEWABI)
252b5132 9587 {
90ecf173 9588 if (!mips_big_got)
f5040a92 9589 {
4d7206a2 9590 relax_start (offset_expr.X_add_symbol);
67c0d1eb
RS
9591 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
9592 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
f5040a92 9593 mips_gp_register);
4d7206a2 9594 relax_switch ();
67c0d1eb
RS
9595 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
9596 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_DISP,
4d7206a2
RS
9597 mips_gp_register);
9598 relax_end ();
f5040a92
AO
9599 }
9600 else
9601 {
4d7206a2 9602 relax_start (offset_expr.X_add_symbol);
df58fc94 9603 macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG,
67c0d1eb
RS
9604 BFD_RELOC_MIPS_CALL_HI16);
9605 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
9606 PIC_CALL_REG, mips_gp_register);
9607 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
9608 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
9609 PIC_CALL_REG);
4d7206a2 9610 relax_switch ();
67c0d1eb
RS
9611 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
9612 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_PAGE,
9613 mips_gp_register);
9614 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
9615 PIC_CALL_REG, PIC_CALL_REG,
17a2f251 9616 BFD_RELOC_MIPS_GOT_OFST);
4d7206a2 9617 relax_end ();
f5040a92 9618 }
684022ea 9619
df58fc94 9620 macro_build_jalr (&offset_expr, 0);
252b5132
RH
9621 }
9622 else
9623 {
4d7206a2 9624 relax_start (offset_expr.X_add_symbol);
90ecf173 9625 if (!mips_big_got)
438c16b8 9626 {
67c0d1eb
RS
9627 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
9628 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
17a2f251 9629 mips_gp_register);
269137b2 9630 load_delay_nop ();
4d7206a2 9631 relax_switch ();
438c16b8 9632 }
252b5132 9633 else
252b5132 9634 {
67c0d1eb
RS
9635 int gpdelay;
9636
9637 gpdelay = reg_needs_delay (mips_gp_register);
df58fc94 9638 macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG,
67c0d1eb
RS
9639 BFD_RELOC_MIPS_CALL_HI16);
9640 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
9641 PIC_CALL_REG, mips_gp_register);
9642 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
9643 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
9644 PIC_CALL_REG);
269137b2 9645 load_delay_nop ();
4d7206a2 9646 relax_switch ();
67c0d1eb
RS
9647 if (gpdelay)
9648 macro_build (NULL, "nop", "");
252b5132 9649 }
67c0d1eb
RS
9650 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
9651 PIC_CALL_REG, BFD_RELOC_MIPS_GOT16,
4d7206a2 9652 mips_gp_register);
269137b2 9653 load_delay_nop ();
67c0d1eb
RS
9654 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
9655 PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16);
4d7206a2 9656 relax_end ();
df58fc94 9657 macro_build_jalr (&offset_expr, mips_cprestore_offset >= 0);
438c16b8 9658
6478892d
TS
9659 if (mips_cprestore_offset < 0)
9660 as_warn (_("No .cprestore pseudo-op used in PIC code"));
9661 else
9662 {
90ecf173 9663 if (!mips_frame_reg_valid)
7a621144
DJ
9664 {
9665 as_warn (_("No .frame pseudo-op used in PIC code"));
9666 /* Quiet this warning. */
9667 mips_frame_reg_valid = 1;
9668 }
90ecf173 9669 if (!mips_cprestore_valid)
7a621144
DJ
9670 {
9671 as_warn (_("No .cprestore pseudo-op used in PIC code"));
9672 /* Quiet this warning. */
9673 mips_cprestore_valid = 1;
9674 }
6478892d 9675 if (mips_opts.noreorder)
67c0d1eb 9676 macro_build (NULL, "nop", "");
6478892d 9677 expr1.X_add_number = mips_cprestore_offset;
67c0d1eb 9678 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
f899b4b8 9679 mips_gp_register,
256ab948
TS
9680 mips_frame_reg,
9681 HAVE_64BIT_ADDRESSES);
6478892d 9682 }
252b5132
RH
9683 }
9684 }
0a44bf69
RS
9685 else if (mips_pic == VXWORKS_PIC)
9686 as_bad (_("Non-PIC jump used in PIC library"));
252b5132
RH
9687 else
9688 abort ();
9689
8fc2e39e 9690 break;
252b5132 9691
7f3c4072 9692 case M_LBUE_AB:
7f3c4072
CM
9693 s = "lbue";
9694 fmt = "t,+j(b)";
9695 offbits = 9;
9696 goto ld_st;
9697 case M_LHUE_AB:
7f3c4072
CM
9698 s = "lhue";
9699 fmt = "t,+j(b)";
9700 offbits = 9;
9701 goto ld_st;
9702 case M_LBE_AB:
7f3c4072
CM
9703 s = "lbe";
9704 fmt = "t,+j(b)";
9705 offbits = 9;
9706 goto ld_st;
9707 case M_LHE_AB:
7f3c4072
CM
9708 s = "lhe";
9709 fmt = "t,+j(b)";
9710 offbits = 9;
9711 goto ld_st;
9712 case M_LLE_AB:
7f3c4072
CM
9713 s = "lle";
9714 fmt = "t,+j(b)";
9715 offbits = 9;
9716 goto ld_st;
9717 case M_LWE_AB:
7f3c4072
CM
9718 s = "lwe";
9719 fmt = "t,+j(b)";
9720 offbits = 9;
9721 goto ld_st;
9722 case M_LWLE_AB:
7f3c4072
CM
9723 s = "lwle";
9724 fmt = "t,+j(b)";
9725 offbits = 9;
9726 goto ld_st;
9727 case M_LWRE_AB:
7f3c4072
CM
9728 s = "lwre";
9729 fmt = "t,+j(b)";
9730 offbits = 9;
9731 goto ld_st;
9732 case M_SBE_AB:
7f3c4072
CM
9733 s = "sbe";
9734 fmt = "t,+j(b)";
9735 offbits = 9;
9736 goto ld_st;
9737 case M_SCE_AB:
7f3c4072
CM
9738 s = "sce";
9739 fmt = "t,+j(b)";
9740 offbits = 9;
9741 goto ld_st;
9742 case M_SHE_AB:
7f3c4072
CM
9743 s = "she";
9744 fmt = "t,+j(b)";
9745 offbits = 9;
9746 goto ld_st;
9747 case M_SWE_AB:
7f3c4072
CM
9748 s = "swe";
9749 fmt = "t,+j(b)";
9750 offbits = 9;
9751 goto ld_st;
9752 case M_SWLE_AB:
7f3c4072
CM
9753 s = "swle";
9754 fmt = "t,+j(b)";
9755 offbits = 9;
9756 goto ld_st;
9757 case M_SWRE_AB:
7f3c4072
CM
9758 s = "swre";
9759 fmt = "t,+j(b)";
9760 offbits = 9;
9761 goto ld_st;
dec0624d 9762 case M_ACLR_AB:
dec0624d
MR
9763 s = "aclr";
9764 treg = EXTRACT_OPERAND (mips_opts.micromips, 3BITPOS, *ip);
9765 fmt = "\\,~(b)";
7f3c4072 9766 offbits = 12;
dec0624d
MR
9767 goto ld_st;
9768 case M_ASET_AB:
dec0624d
MR
9769 s = "aset";
9770 treg = EXTRACT_OPERAND (mips_opts.micromips, 3BITPOS, *ip);
9771 fmt = "\\,~(b)";
7f3c4072 9772 offbits = 12;
dec0624d 9773 goto ld_st;
252b5132
RH
9774 case M_LB_AB:
9775 s = "lb";
df58fc94 9776 fmt = "t,o(b)";
252b5132
RH
9777 goto ld;
9778 case M_LBU_AB:
9779 s = "lbu";
df58fc94 9780 fmt = "t,o(b)";
252b5132
RH
9781 goto ld;
9782 case M_LH_AB:
9783 s = "lh";
df58fc94 9784 fmt = "t,o(b)";
252b5132
RH
9785 goto ld;
9786 case M_LHU_AB:
9787 s = "lhu";
df58fc94 9788 fmt = "t,o(b)";
252b5132
RH
9789 goto ld;
9790 case M_LW_AB:
9791 s = "lw";
df58fc94 9792 fmt = "t,o(b)";
252b5132
RH
9793 goto ld;
9794 case M_LWC0_AB:
df58fc94 9795 gas_assert (!mips_opts.micromips);
252b5132 9796 s = "lwc0";
df58fc94 9797 fmt = "E,o(b)";
bdaaa2e1 9798 /* Itbl support may require additional care here. */
252b5132 9799 coproc = 1;
df58fc94 9800 goto ld_st;
252b5132
RH
9801 case M_LWC1_AB:
9802 s = "lwc1";
df58fc94 9803 fmt = "T,o(b)";
bdaaa2e1 9804 /* Itbl support may require additional care here. */
252b5132 9805 coproc = 1;
df58fc94 9806 goto ld_st;
252b5132
RH
9807 case M_LWC2_AB:
9808 s = "lwc2";
df58fc94 9809 fmt = COP12_FMT;
7f3c4072 9810 offbits = (mips_opts.micromips ? 12 : 16);
bdaaa2e1 9811 /* Itbl support may require additional care here. */
252b5132 9812 coproc = 1;
df58fc94 9813 goto ld_st;
252b5132 9814 case M_LWC3_AB:
df58fc94 9815 gas_assert (!mips_opts.micromips);
252b5132 9816 s = "lwc3";
df58fc94 9817 fmt = "E,o(b)";
bdaaa2e1 9818 /* Itbl support may require additional care here. */
252b5132 9819 coproc = 1;
df58fc94 9820 goto ld_st;
252b5132
RH
9821 case M_LWL_AB:
9822 s = "lwl";
df58fc94 9823 fmt = MEM12_FMT;
7f3c4072 9824 offbits = (mips_opts.micromips ? 12 : 16);
df58fc94 9825 goto ld_st;
252b5132
RH
9826 case M_LWR_AB:
9827 s = "lwr";
df58fc94 9828 fmt = MEM12_FMT;
7f3c4072 9829 offbits = (mips_opts.micromips ? 12 : 16);
df58fc94 9830 goto ld_st;
252b5132 9831 case M_LDC1_AB:
252b5132 9832 s = "ldc1";
df58fc94 9833 fmt = "T,o(b)";
bdaaa2e1 9834 /* Itbl support may require additional care here. */
252b5132 9835 coproc = 1;
df58fc94 9836 goto ld_st;
252b5132
RH
9837 case M_LDC2_AB:
9838 s = "ldc2";
df58fc94 9839 fmt = COP12_FMT;
7f3c4072 9840 offbits = (mips_opts.micromips ? 12 : 16);
bdaaa2e1 9841 /* Itbl support may require additional care here. */
252b5132 9842 coproc = 1;
df58fc94 9843 goto ld_st;
c77c0862 9844 case M_LQC2_AB:
c77c0862
RS
9845 s = "lqc2";
9846 fmt = "E,o(b)";
9847 /* Itbl support may require additional care here. */
9848 coproc = 1;
9849 goto ld_st;
252b5132
RH
9850 case M_LDC3_AB:
9851 s = "ldc3";
df58fc94 9852 fmt = "E,o(b)";
bdaaa2e1 9853 /* Itbl support may require additional care here. */
252b5132 9854 coproc = 1;
df58fc94 9855 goto ld_st;
252b5132
RH
9856 case M_LDL_AB:
9857 s = "ldl";
df58fc94 9858 fmt = MEM12_FMT;
7f3c4072 9859 offbits = (mips_opts.micromips ? 12 : 16);
df58fc94 9860 goto ld_st;
252b5132
RH
9861 case M_LDR_AB:
9862 s = "ldr";
df58fc94 9863 fmt = MEM12_FMT;
7f3c4072 9864 offbits = (mips_opts.micromips ? 12 : 16);
df58fc94 9865 goto ld_st;
252b5132
RH
9866 case M_LL_AB:
9867 s = "ll";
df58fc94 9868 fmt = MEM12_FMT;
7f3c4072 9869 offbits = (mips_opts.micromips ? 12 : 16);
252b5132
RH
9870 goto ld;
9871 case M_LLD_AB:
9872 s = "lld";
df58fc94 9873 fmt = MEM12_FMT;
7f3c4072 9874 offbits = (mips_opts.micromips ? 12 : 16);
252b5132
RH
9875 goto ld;
9876 case M_LWU_AB:
9877 s = "lwu";
df58fc94 9878 fmt = MEM12_FMT;
7f3c4072 9879 offbits = (mips_opts.micromips ? 12 : 16);
df58fc94
RS
9880 goto ld;
9881 case M_LWP_AB:
df58fc94
RS
9882 gas_assert (mips_opts.micromips);
9883 s = "lwp";
9884 fmt = "t,~(b)";
7f3c4072 9885 offbits = 12;
df58fc94
RS
9886 lp = 1;
9887 goto ld;
9888 case M_LDP_AB:
df58fc94
RS
9889 gas_assert (mips_opts.micromips);
9890 s = "ldp";
9891 fmt = "t,~(b)";
7f3c4072 9892 offbits = 12;
df58fc94
RS
9893 lp = 1;
9894 goto ld;
9895 case M_LWM_AB:
df58fc94
RS
9896 gas_assert (mips_opts.micromips);
9897 s = "lwm";
9898 fmt = "n,~(b)";
7f3c4072 9899 offbits = 12;
df58fc94
RS
9900 goto ld_st;
9901 case M_LDM_AB:
df58fc94
RS
9902 gas_assert (mips_opts.micromips);
9903 s = "ldm";
9904 fmt = "n,~(b)";
7f3c4072 9905 offbits = 12;
df58fc94
RS
9906 goto ld_st;
9907
252b5132 9908 ld:
f19ccbda
MR
9909 /* We don't want to use $0 as tempreg. */
9910 if (breg == treg + lp || treg + lp == ZERO)
df58fc94 9911 goto ld_st;
252b5132 9912 else
df58fc94
RS
9913 tempreg = treg + lp;
9914 goto ld_noat;
9915
252b5132
RH
9916 case M_SB_AB:
9917 s = "sb";
df58fc94
RS
9918 fmt = "t,o(b)";
9919 goto ld_st;
252b5132
RH
9920 case M_SH_AB:
9921 s = "sh";
df58fc94
RS
9922 fmt = "t,o(b)";
9923 goto ld_st;
252b5132
RH
9924 case M_SW_AB:
9925 s = "sw";
df58fc94
RS
9926 fmt = "t,o(b)";
9927 goto ld_st;
252b5132 9928 case M_SWC0_AB:
df58fc94 9929 gas_assert (!mips_opts.micromips);
252b5132 9930 s = "swc0";
df58fc94 9931 fmt = "E,o(b)";
bdaaa2e1 9932 /* Itbl support may require additional care here. */
252b5132 9933 coproc = 1;
df58fc94 9934 goto ld_st;
252b5132
RH
9935 case M_SWC1_AB:
9936 s = "swc1";
df58fc94 9937 fmt = "T,o(b)";
bdaaa2e1 9938 /* Itbl support may require additional care here. */
252b5132 9939 coproc = 1;
df58fc94 9940 goto ld_st;
252b5132
RH
9941 case M_SWC2_AB:
9942 s = "swc2";
df58fc94 9943 fmt = COP12_FMT;
7f3c4072 9944 offbits = (mips_opts.micromips ? 12 : 16);
bdaaa2e1 9945 /* Itbl support may require additional care here. */
252b5132 9946 coproc = 1;
df58fc94 9947 goto ld_st;
252b5132 9948 case M_SWC3_AB:
df58fc94 9949 gas_assert (!mips_opts.micromips);
252b5132 9950 s = "swc3";
df58fc94 9951 fmt = "E,o(b)";
bdaaa2e1 9952 /* Itbl support may require additional care here. */
252b5132 9953 coproc = 1;
df58fc94 9954 goto ld_st;
252b5132
RH
9955 case M_SWL_AB:
9956 s = "swl";
df58fc94 9957 fmt = MEM12_FMT;
7f3c4072 9958 offbits = (mips_opts.micromips ? 12 : 16);
df58fc94 9959 goto ld_st;
252b5132
RH
9960 case M_SWR_AB:
9961 s = "swr";
df58fc94 9962 fmt = MEM12_FMT;
7f3c4072 9963 offbits = (mips_opts.micromips ? 12 : 16);
df58fc94 9964 goto ld_st;
252b5132
RH
9965 case M_SC_AB:
9966 s = "sc";
df58fc94 9967 fmt = MEM12_FMT;
7f3c4072 9968 offbits = (mips_opts.micromips ? 12 : 16);
df58fc94 9969 goto ld_st;
252b5132
RH
9970 case M_SCD_AB:
9971 s = "scd";
df58fc94 9972 fmt = MEM12_FMT;
7f3c4072 9973 offbits = (mips_opts.micromips ? 12 : 16);
df58fc94 9974 goto ld_st;
d43b4baf
TS
9975 case M_CACHE_AB:
9976 s = "cache";
df58fc94 9977 fmt = mips_opts.micromips ? "k,~(b)" : "k,o(b)";
7f3c4072
CM
9978 offbits = (mips_opts.micromips ? 12 : 16);
9979 goto ld_st;
9980 case M_CACHEE_AB:
7f3c4072
CM
9981 s = "cachee";
9982 fmt = "k,+j(b)";
9983 offbits = 9;
df58fc94 9984 goto ld_st;
3eebd5eb
MR
9985 case M_PREF_AB:
9986 s = "pref";
df58fc94 9987 fmt = !mips_opts.micromips ? "k,o(b)" : "k,~(b)";
7f3c4072
CM
9988 offbits = (mips_opts.micromips ? 12 : 16);
9989 goto ld_st;
9990 case M_PREFE_AB:
7f3c4072
CM
9991 s = "prefe";
9992 fmt = "k,+j(b)";
9993 offbits = 9;
df58fc94 9994 goto ld_st;
252b5132 9995 case M_SDC1_AB:
252b5132 9996 s = "sdc1";
df58fc94 9997 fmt = "T,o(b)";
252b5132 9998 coproc = 1;
bdaaa2e1 9999 /* Itbl support may require additional care here. */
df58fc94 10000 goto ld_st;
252b5132
RH
10001 case M_SDC2_AB:
10002 s = "sdc2";
df58fc94 10003 fmt = COP12_FMT;
7f3c4072 10004 offbits = (mips_opts.micromips ? 12 : 16);
c77c0862
RS
10005 /* Itbl support may require additional care here. */
10006 coproc = 1;
10007 goto ld_st;
10008 case M_SQC2_AB:
c77c0862
RS
10009 s = "sqc2";
10010 fmt = "E,o(b)";
bdaaa2e1 10011 /* Itbl support may require additional care here. */
252b5132 10012 coproc = 1;
df58fc94 10013 goto ld_st;
252b5132 10014 case M_SDC3_AB:
df58fc94 10015 gas_assert (!mips_opts.micromips);
252b5132 10016 s = "sdc3";
df58fc94 10017 fmt = "E,o(b)";
bdaaa2e1 10018 /* Itbl support may require additional care here. */
252b5132 10019 coproc = 1;
df58fc94 10020 goto ld_st;
252b5132
RH
10021 case M_SDL_AB:
10022 s = "sdl";
df58fc94 10023 fmt = MEM12_FMT;
7f3c4072 10024 offbits = (mips_opts.micromips ? 12 : 16);
df58fc94 10025 goto ld_st;
252b5132
RH
10026 case M_SDR_AB:
10027 s = "sdr";
df58fc94 10028 fmt = MEM12_FMT;
7f3c4072 10029 offbits = (mips_opts.micromips ? 12 : 16);
df58fc94
RS
10030 goto ld_st;
10031 case M_SWP_AB:
df58fc94
RS
10032 gas_assert (mips_opts.micromips);
10033 s = "swp";
10034 fmt = "t,~(b)";
7f3c4072 10035 offbits = 12;
df58fc94
RS
10036 goto ld_st;
10037 case M_SDP_AB:
df58fc94
RS
10038 gas_assert (mips_opts.micromips);
10039 s = "sdp";
10040 fmt = "t,~(b)";
7f3c4072 10041 offbits = 12;
df58fc94
RS
10042 goto ld_st;
10043 case M_SWM_AB:
df58fc94
RS
10044 gas_assert (mips_opts.micromips);
10045 s = "swm";
10046 fmt = "n,~(b)";
7f3c4072 10047 offbits = 12;
df58fc94
RS
10048 goto ld_st;
10049 case M_SDM_AB:
df58fc94
RS
10050 gas_assert (mips_opts.micromips);
10051 s = "sdm";
10052 fmt = "n,~(b)";
7f3c4072 10053 offbits = 12;
df58fc94
RS
10054
10055 ld_st:
8fc2e39e 10056 tempreg = AT;
df58fc94 10057 ld_noat:
f2ae14a1
RS
10058 if (small_offset_p (0, align, 16))
10059 {
10060 /* The first case exists for M_LD_AB and M_SD_AB, which are
10061 macros for o32 but which should act like normal instructions
10062 otherwise. */
10063 if (offbits == 16)
10064 macro_build (&offset_expr, s, fmt, treg, -1, offset_reloc[0],
10065 offset_reloc[1], offset_reloc[2], breg);
10066 else if (small_offset_p (0, align, offbits))
10067 {
10068 if (offbits == 0)
10069 macro_build (NULL, s, fmt, treg, breg);
10070 else
10071 macro_build (NULL, s, fmt, treg,
c8276761 10072 (int) offset_expr.X_add_number, breg);
f2ae14a1
RS
10073 }
10074 else
10075 {
10076 if (tempreg == AT)
10077 used_at = 1;
10078 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
10079 tempreg, breg, -1, offset_reloc[0],
10080 offset_reloc[1], offset_reloc[2]);
10081 if (offbits == 0)
10082 macro_build (NULL, s, fmt, treg, tempreg);
10083 else
c8276761 10084 macro_build (NULL, s, fmt, treg, 0, tempreg);
f2ae14a1
RS
10085 }
10086 break;
10087 }
10088
10089 if (tempreg == AT)
10090 used_at = 1;
10091
252b5132
RH
10092 if (offset_expr.X_op != O_constant
10093 && offset_expr.X_op != O_symbol)
10094 {
f71d0d44 10095 as_bad (_("Expression too complex"));
252b5132
RH
10096 offset_expr.X_op = O_constant;
10097 }
10098
2051e8c4
MR
10099 if (HAVE_32BIT_ADDRESSES
10100 && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
55e08f71
NC
10101 {
10102 char value [32];
10103
10104 sprintf_vma (value, offset_expr.X_add_number);
20e1fcfd 10105 as_bad (_("Number (0x%s) larger than 32 bits"), value);
55e08f71 10106 }
2051e8c4 10107
252b5132
RH
10108 /* A constant expression in PIC code can be handled just as it
10109 is in non PIC code. */
aed1a261
RS
10110 if (offset_expr.X_op == O_constant)
10111 {
f2ae14a1
RS
10112 expr1.X_add_number = offset_high_part (offset_expr.X_add_number,
10113 offbits == 0 ? 16 : offbits);
10114 offset_expr.X_add_number -= expr1.X_add_number;
df58fc94 10115
f2ae14a1
RS
10116 load_register (tempreg, &expr1, HAVE_64BIT_ADDRESSES);
10117 if (breg != 0)
10118 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10119 tempreg, tempreg, breg);
7f3c4072 10120 if (offbits == 0)
dd6a37e7 10121 {
f2ae14a1 10122 if (offset_expr.X_add_number != 0)
dd6a37e7 10123 macro_build (&offset_expr, ADDRESS_ADDI_INSN,
f2ae14a1 10124 "t,r,j", tempreg, tempreg, BFD_RELOC_LO16);
dd6a37e7
AP
10125 macro_build (NULL, s, fmt, treg, tempreg);
10126 }
7f3c4072 10127 else if (offbits == 16)
f2ae14a1 10128 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, tempreg);
df58fc94 10129 else
f2ae14a1 10130 macro_build (NULL, s, fmt, treg,
c8276761 10131 (int) offset_expr.X_add_number, tempreg);
df58fc94 10132 }
7f3c4072 10133 else if (offbits != 16)
df58fc94 10134 {
7f3c4072
CM
10135 /* The offset field is too narrow to be used for a low-part
10136 relocation, so load the whole address into the auxillary
f2ae14a1
RS
10137 register. */
10138 load_address (tempreg, &offset_expr, &used_at);
10139 if (breg != 0)
10140 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10141 tempreg, tempreg, breg);
7f3c4072 10142 if (offbits == 0)
dd6a37e7
AP
10143 macro_build (NULL, s, fmt, treg, tempreg);
10144 else
c8276761 10145 macro_build (NULL, s, fmt, treg, 0, tempreg);
aed1a261
RS
10146 }
10147 else if (mips_pic == NO_PIC)
252b5132
RH
10148 {
10149 /* If this is a reference to a GP relative symbol, and there
10150 is no base register, we want
cdf6fd85 10151 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
252b5132
RH
10152 Otherwise, if there is no base register, we want
10153 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
10154 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
10155 If we have a constant, we need two instructions anyhow,
10156 so we always use the latter form.
10157
10158 If we have a base register, and this is a reference to a
10159 GP relative symbol, we want
10160 addu $tempreg,$breg,$gp
cdf6fd85 10161 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
252b5132
RH
10162 Otherwise we want
10163 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
10164 addu $tempreg,$tempreg,$breg
10165 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
d6bc6245 10166 With a constant we always use the latter case.
76b3015f 10167
d6bc6245
TS
10168 With 64bit address space and no base register and $at usable,
10169 we want
10170 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
10171 lui $at,<sym> (BFD_RELOC_HI16_S)
10172 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
10173 dsll32 $tempreg,0
10174 daddu $tempreg,$at
10175 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
10176 If we have a base register, we want
10177 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
10178 lui $at,<sym> (BFD_RELOC_HI16_S)
10179 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
10180 daddu $at,$breg
10181 dsll32 $tempreg,0
10182 daddu $tempreg,$at
10183 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
10184
10185 Without $at we can't generate the optimal path for superscalar
10186 processors here since this would require two temporary registers.
10187 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
10188 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
10189 dsll $tempreg,16
10190 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
10191 dsll $tempreg,16
10192 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
10193 If we have a base register, we want
10194 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
10195 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
10196 dsll $tempreg,16
10197 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
10198 dsll $tempreg,16
10199 daddu $tempreg,$tempreg,$breg
10200 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6373ee54 10201
6caf9ef4 10202 For GP relative symbols in 64bit address space we can use
aed1a261
RS
10203 the same sequence as in 32bit address space. */
10204 if (HAVE_64BIT_SYMBOLS)
d6bc6245 10205 {
aed1a261 10206 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
6caf9ef4
TS
10207 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
10208 {
10209 relax_start (offset_expr.X_add_symbol);
10210 if (breg == 0)
10211 {
10212 macro_build (&offset_expr, s, fmt, treg,
10213 BFD_RELOC_GPREL16, mips_gp_register);
10214 }
10215 else
10216 {
10217 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10218 tempreg, breg, mips_gp_register);
10219 macro_build (&offset_expr, s, fmt, treg,
10220 BFD_RELOC_GPREL16, tempreg);
10221 }
10222 relax_switch ();
10223 }
d6bc6245 10224
741fe287 10225 if (used_at == 0 && mips_opts.at)
d6bc6245 10226 {
df58fc94 10227 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
67c0d1eb 10228 BFD_RELOC_MIPS_HIGHEST);
df58fc94 10229 macro_build (&offset_expr, "lui", LUI_FMT, AT,
67c0d1eb
RS
10230 BFD_RELOC_HI16_S);
10231 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
10232 tempreg, BFD_RELOC_MIPS_HIGHER);
d6bc6245 10233 if (breg != 0)
67c0d1eb 10234 macro_build (NULL, "daddu", "d,v,t", AT, AT, breg);
df58fc94 10235 macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0);
67c0d1eb
RS
10236 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT);
10237 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16,
10238 tempreg);
d6bc6245
TS
10239 used_at = 1;
10240 }
10241 else
10242 {
df58fc94 10243 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
67c0d1eb
RS
10244 BFD_RELOC_MIPS_HIGHEST);
10245 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
10246 tempreg, BFD_RELOC_MIPS_HIGHER);
df58fc94 10247 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
67c0d1eb
RS
10248 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
10249 tempreg, BFD_RELOC_HI16_S);
df58fc94 10250 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
d6bc6245 10251 if (breg != 0)
67c0d1eb 10252 macro_build (NULL, "daddu", "d,v,t",
17a2f251 10253 tempreg, tempreg, breg);
67c0d1eb 10254 macro_build (&offset_expr, s, fmt, treg,
17a2f251 10255 BFD_RELOC_LO16, tempreg);
d6bc6245 10256 }
6caf9ef4
TS
10257
10258 if (mips_relax.sequence)
10259 relax_end ();
8fc2e39e 10260 break;
d6bc6245 10261 }
256ab948 10262
252b5132
RH
10263 if (breg == 0)
10264 {
67c0d1eb 10265 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
6caf9ef4 10266 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
252b5132 10267 {
4d7206a2 10268 relax_start (offset_expr.X_add_symbol);
67c0d1eb
RS
10269 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_GPREL16,
10270 mips_gp_register);
4d7206a2 10271 relax_switch ();
252b5132 10272 }
67c0d1eb
RS
10273 macro_build_lui (&offset_expr, tempreg);
10274 macro_build (&offset_expr, s, fmt, treg,
17a2f251 10275 BFD_RELOC_LO16, tempreg);
4d7206a2
RS
10276 if (mips_relax.sequence)
10277 relax_end ();
252b5132
RH
10278 }
10279 else
10280 {
67c0d1eb 10281 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
6caf9ef4 10282 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
252b5132 10283 {
4d7206a2 10284 relax_start (offset_expr.X_add_symbol);
67c0d1eb 10285 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
17a2f251 10286 tempreg, breg, mips_gp_register);
67c0d1eb 10287 macro_build (&offset_expr, s, fmt, treg,
17a2f251 10288 BFD_RELOC_GPREL16, tempreg);
4d7206a2 10289 relax_switch ();
252b5132 10290 }
67c0d1eb
RS
10291 macro_build_lui (&offset_expr, tempreg);
10292 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
17a2f251 10293 tempreg, tempreg, breg);
67c0d1eb 10294 macro_build (&offset_expr, s, fmt, treg,
17a2f251 10295 BFD_RELOC_LO16, tempreg);
4d7206a2
RS
10296 if (mips_relax.sequence)
10297 relax_end ();
252b5132
RH
10298 }
10299 }
0a44bf69 10300 else if (!mips_big_got)
252b5132 10301 {
ed6fb7bd 10302 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
f9419b05 10303
252b5132
RH
10304 /* If this is a reference to an external symbol, we want
10305 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10306 nop
10307 <op> $treg,0($tempreg)
10308 Otherwise we want
10309 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10310 nop
10311 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
10312 <op> $treg,0($tempreg)
f5040a92
AO
10313
10314 For NewABI, we want
10315 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
10316 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
10317
252b5132
RH
10318 If there is a base register, we add it to $tempreg before
10319 the <op>. If there is a constant, we stick it in the
10320 <op> instruction. We don't handle constants larger than
10321 16 bits, because we have no way to load the upper 16 bits
10322 (actually, we could handle them for the subset of cases
10323 in which we are not using $at). */
9c2799c2 10324 gas_assert (offset_expr.X_op == O_symbol);
f5040a92
AO
10325 if (HAVE_NEWABI)
10326 {
67c0d1eb
RS
10327 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
10328 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
f5040a92 10329 if (breg != 0)
67c0d1eb 10330 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
17a2f251 10331 tempreg, tempreg, breg);
67c0d1eb 10332 macro_build (&offset_expr, s, fmt, treg,
17a2f251 10333 BFD_RELOC_MIPS_GOT_OFST, tempreg);
f5040a92
AO
10334 break;
10335 }
252b5132
RH
10336 expr1.X_add_number = offset_expr.X_add_number;
10337 offset_expr.X_add_number = 0;
10338 if (expr1.X_add_number < -0x8000
10339 || expr1.X_add_number >= 0x8000)
10340 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
67c0d1eb
RS
10341 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
10342 lw_reloc_type, mips_gp_register);
269137b2 10343 load_delay_nop ();
4d7206a2
RS
10344 relax_start (offset_expr.X_add_symbol);
10345 relax_switch ();
67c0d1eb
RS
10346 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
10347 tempreg, BFD_RELOC_LO16);
4d7206a2 10348 relax_end ();
252b5132 10349 if (breg != 0)
67c0d1eb 10350 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
17a2f251 10351 tempreg, tempreg, breg);
67c0d1eb 10352 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
252b5132 10353 }
0a44bf69 10354 else if (mips_big_got && !HAVE_NEWABI)
252b5132 10355 {
67c0d1eb 10356 int gpdelay;
252b5132
RH
10357
10358 /* If this is a reference to an external symbol, we want
10359 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10360 addu $tempreg,$tempreg,$gp
10361 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10362 <op> $treg,0($tempreg)
10363 Otherwise we want
10364 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10365 nop
10366 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
10367 <op> $treg,0($tempreg)
10368 If there is a base register, we add it to $tempreg before
10369 the <op>. If there is a constant, we stick it in the
10370 <op> instruction. We don't handle constants larger than
10371 16 bits, because we have no way to load the upper 16 bits
10372 (actually, we could handle them for the subset of cases
f5040a92 10373 in which we are not using $at). */
9c2799c2 10374 gas_assert (offset_expr.X_op == O_symbol);
252b5132
RH
10375 expr1.X_add_number = offset_expr.X_add_number;
10376 offset_expr.X_add_number = 0;
10377 if (expr1.X_add_number < -0x8000
10378 || expr1.X_add_number >= 0x8000)
10379 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
67c0d1eb 10380 gpdelay = reg_needs_delay (mips_gp_register);
4d7206a2 10381 relax_start (offset_expr.X_add_symbol);
df58fc94 10382 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
17a2f251 10383 BFD_RELOC_MIPS_GOT_HI16);
67c0d1eb
RS
10384 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
10385 mips_gp_register);
10386 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
10387 BFD_RELOC_MIPS_GOT_LO16, tempreg);
4d7206a2 10388 relax_switch ();
67c0d1eb
RS
10389 if (gpdelay)
10390 macro_build (NULL, "nop", "");
10391 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
10392 BFD_RELOC_MIPS_GOT16, mips_gp_register);
269137b2 10393 load_delay_nop ();
67c0d1eb
RS
10394 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
10395 tempreg, BFD_RELOC_LO16);
4d7206a2
RS
10396 relax_end ();
10397
252b5132 10398 if (breg != 0)
67c0d1eb 10399 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
17a2f251 10400 tempreg, tempreg, breg);
67c0d1eb 10401 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
252b5132 10402 }
0a44bf69 10403 else if (mips_big_got && HAVE_NEWABI)
f5040a92 10404 {
f5040a92
AO
10405 /* If this is a reference to an external symbol, we want
10406 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10407 add $tempreg,$tempreg,$gp
10408 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10409 <op> $treg,<ofst>($tempreg)
10410 Otherwise, for local symbols, we want:
10411 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
10412 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
9c2799c2 10413 gas_assert (offset_expr.X_op == O_symbol);
4d7206a2 10414 expr1.X_add_number = offset_expr.X_add_number;
f5040a92
AO
10415 offset_expr.X_add_number = 0;
10416 if (expr1.X_add_number < -0x8000
10417 || expr1.X_add_number >= 0x8000)
10418 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4d7206a2 10419 relax_start (offset_expr.X_add_symbol);
df58fc94 10420 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
17a2f251 10421 BFD_RELOC_MIPS_GOT_HI16);
67c0d1eb
RS
10422 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
10423 mips_gp_register);
10424 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
10425 BFD_RELOC_MIPS_GOT_LO16, tempreg);
f5040a92 10426 if (breg != 0)
67c0d1eb 10427 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
17a2f251 10428 tempreg, tempreg, breg);
67c0d1eb 10429 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
684022ea 10430
4d7206a2 10431 relax_switch ();
f5040a92 10432 offset_expr.X_add_number = expr1.X_add_number;
67c0d1eb
RS
10433 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
10434 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
f5040a92 10435 if (breg != 0)
67c0d1eb 10436 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
17a2f251 10437 tempreg, tempreg, breg);
67c0d1eb 10438 macro_build (&offset_expr, s, fmt, treg,
17a2f251 10439 BFD_RELOC_MIPS_GOT_OFST, tempreg);
4d7206a2 10440 relax_end ();
f5040a92 10441 }
252b5132
RH
10442 else
10443 abort ();
10444
252b5132
RH
10445 break;
10446
833794fc
MR
10447 case M_JRADDIUSP:
10448 gas_assert (mips_opts.micromips);
10449 gas_assert (mips_opts.insn32);
10450 start_noreorder ();
10451 macro_build (NULL, "jr", "s", RA);
10452 expr1.X_add_number = EXTRACT_OPERAND (1, IMMP, *ip) << 2;
10453 macro_build (&expr1, "addiu", "t,r,j", SP, SP, BFD_RELOC_LO16);
10454 end_noreorder ();
10455 break;
10456
10457 case M_JRC:
10458 gas_assert (mips_opts.micromips);
10459 gas_assert (mips_opts.insn32);
10460 macro_build (NULL, "jr", "s", sreg);
10461 if (mips_opts.noreorder)
10462 macro_build (NULL, "nop", "");
10463 break;
10464
252b5132
RH
10465 case M_LI:
10466 case M_LI_S:
67c0d1eb 10467 load_register (treg, &imm_expr, 0);
8fc2e39e 10468 break;
252b5132
RH
10469
10470 case M_DLI:
67c0d1eb 10471 load_register (treg, &imm_expr, 1);
8fc2e39e 10472 break;
252b5132
RH
10473
10474 case M_LI_SS:
10475 if (imm_expr.X_op == O_constant)
10476 {
8fc2e39e 10477 used_at = 1;
67c0d1eb
RS
10478 load_register (AT, &imm_expr, 0);
10479 macro_build (NULL, "mtc1", "t,G", AT, treg);
252b5132
RH
10480 break;
10481 }
10482 else
10483 {
9c2799c2 10484 gas_assert (offset_expr.X_op == O_symbol
90ecf173
MR
10485 && strcmp (segment_name (S_GET_SEGMENT
10486 (offset_expr.X_add_symbol)),
10487 ".lit4") == 0
10488 && offset_expr.X_add_number == 0);
67c0d1eb 10489 macro_build (&offset_expr, "lwc1", "T,o(b)", treg,
17a2f251 10490 BFD_RELOC_MIPS_LITERAL, mips_gp_register);
8fc2e39e 10491 break;
252b5132
RH
10492 }
10493
10494 case M_LI_D:
ca4e0257
RS
10495 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
10496 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
10497 order 32 bits of the value and the low order 32 bits are either
10498 zero or in OFFSET_EXPR. */
252b5132
RH
10499 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
10500 {
ca4e0257 10501 if (HAVE_64BIT_GPRS)
67c0d1eb 10502 load_register (treg, &imm_expr, 1);
252b5132
RH
10503 else
10504 {
10505 int hreg, lreg;
10506
10507 if (target_big_endian)
10508 {
10509 hreg = treg;
10510 lreg = treg + 1;
10511 }
10512 else
10513 {
10514 hreg = treg + 1;
10515 lreg = treg;
10516 }
10517
10518 if (hreg <= 31)
67c0d1eb 10519 load_register (hreg, &imm_expr, 0);
252b5132
RH
10520 if (lreg <= 31)
10521 {
10522 if (offset_expr.X_op == O_absent)
67c0d1eb 10523 move_register (lreg, 0);
252b5132
RH
10524 else
10525 {
9c2799c2 10526 gas_assert (offset_expr.X_op == O_constant);
67c0d1eb 10527 load_register (lreg, &offset_expr, 0);
252b5132
RH
10528 }
10529 }
10530 }
8fc2e39e 10531 break;
252b5132
RH
10532 }
10533
10534 /* We know that sym is in the .rdata section. First we get the
10535 upper 16 bits of the address. */
10536 if (mips_pic == NO_PIC)
10537 {
67c0d1eb 10538 macro_build_lui (&offset_expr, AT);
8fc2e39e 10539 used_at = 1;
252b5132 10540 }
0a44bf69 10541 else
252b5132 10542 {
67c0d1eb
RS
10543 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
10544 BFD_RELOC_MIPS_GOT16, mips_gp_register);
8fc2e39e 10545 used_at = 1;
252b5132 10546 }
bdaaa2e1 10547
252b5132 10548 /* Now we load the register(s). */
ca4e0257 10549 if (HAVE_64BIT_GPRS)
8fc2e39e
TS
10550 {
10551 used_at = 1;
10552 macro_build (&offset_expr, "ld", "t,o(b)", treg, BFD_RELOC_LO16, AT);
10553 }
252b5132
RH
10554 else
10555 {
8fc2e39e 10556 used_at = 1;
67c0d1eb 10557 macro_build (&offset_expr, "lw", "t,o(b)", treg, BFD_RELOC_LO16, AT);
f9419b05 10558 if (treg != RA)
252b5132
RH
10559 {
10560 /* FIXME: How in the world do we deal with the possible
10561 overflow here? */
10562 offset_expr.X_add_number += 4;
67c0d1eb 10563 macro_build (&offset_expr, "lw", "t,o(b)",
17a2f251 10564 treg + 1, BFD_RELOC_LO16, AT);
252b5132
RH
10565 }
10566 }
252b5132
RH
10567 break;
10568
10569 case M_LI_DD:
ca4e0257
RS
10570 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
10571 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
10572 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
10573 the value and the low order 32 bits are either zero or in
10574 OFFSET_EXPR. */
252b5132
RH
10575 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
10576 {
8fc2e39e 10577 used_at = 1;
67c0d1eb 10578 load_register (AT, &imm_expr, HAVE_64BIT_FPRS);
ca4e0257
RS
10579 if (HAVE_64BIT_FPRS)
10580 {
9c2799c2 10581 gas_assert (HAVE_64BIT_GPRS);
67c0d1eb 10582 macro_build (NULL, "dmtc1", "t,S", AT, treg);
ca4e0257 10583 }
252b5132
RH
10584 else
10585 {
67c0d1eb 10586 macro_build (NULL, "mtc1", "t,G", AT, treg + 1);
252b5132 10587 if (offset_expr.X_op == O_absent)
67c0d1eb 10588 macro_build (NULL, "mtc1", "t,G", 0, treg);
252b5132
RH
10589 else
10590 {
9c2799c2 10591 gas_assert (offset_expr.X_op == O_constant);
67c0d1eb
RS
10592 load_register (AT, &offset_expr, 0);
10593 macro_build (NULL, "mtc1", "t,G", AT, treg);
252b5132
RH
10594 }
10595 }
10596 break;
10597 }
10598
9c2799c2 10599 gas_assert (offset_expr.X_op == O_symbol
90ecf173 10600 && offset_expr.X_add_number == 0);
252b5132
RH
10601 s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol));
10602 if (strcmp (s, ".lit8") == 0)
f2ae14a1
RS
10603 {
10604 breg = mips_gp_register;
10605 offset_reloc[0] = BFD_RELOC_MIPS_LITERAL;
10606 offset_reloc[1] = BFD_RELOC_UNUSED;
10607 offset_reloc[2] = BFD_RELOC_UNUSED;
252b5132
RH
10608 }
10609 else
10610 {
9c2799c2 10611 gas_assert (strcmp (s, RDATA_SECTION_NAME) == 0);
8fc2e39e 10612 used_at = 1;
0a44bf69 10613 if (mips_pic != NO_PIC)
67c0d1eb
RS
10614 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
10615 BFD_RELOC_MIPS_GOT16, mips_gp_register);
252b5132
RH
10616 else
10617 {
10618 /* FIXME: This won't work for a 64 bit address. */
67c0d1eb 10619 macro_build_lui (&offset_expr, AT);
252b5132 10620 }
bdaaa2e1 10621
252b5132 10622 breg = AT;
f2ae14a1
RS
10623 offset_reloc[0] = BFD_RELOC_LO16;
10624 offset_reloc[1] = BFD_RELOC_UNUSED;
10625 offset_reloc[2] = BFD_RELOC_UNUSED;
10626 }
10627 align = 8;
10628 /* Fall through */
c4a68bea 10629
252b5132
RH
10630 case M_L_DAB:
10631 /*
10632 * The MIPS assembler seems to check for X_add_number not
10633 * being double aligned and generating:
10634 * lui at,%hi(foo+1)
10635 * addu at,at,v1
10636 * addiu at,at,%lo(foo+1)
10637 * lwc1 f2,0(at)
10638 * lwc1 f3,4(at)
10639 * But, the resulting address is the same after relocation so why
10640 * generate the extra instruction?
10641 */
bdaaa2e1 10642 /* Itbl support may require additional care here. */
252b5132 10643 coproc = 1;
df58fc94 10644 fmt = "T,o(b)";
0aa27725 10645 if (CPU_HAS_LDC1_SDC1 (mips_opts.arch))
252b5132
RH
10646 {
10647 s = "ldc1";
df58fc94 10648 goto ld_st;
252b5132 10649 }
252b5132 10650 s = "lwc1";
252b5132
RH
10651 goto ldd_std;
10652
10653 case M_S_DAB:
df58fc94
RS
10654 gas_assert (!mips_opts.micromips);
10655 /* Itbl support may require additional care here. */
10656 coproc = 1;
10657 fmt = "T,o(b)";
0aa27725 10658 if (CPU_HAS_LDC1_SDC1 (mips_opts.arch))
252b5132
RH
10659 {
10660 s = "sdc1";
df58fc94 10661 goto ld_st;
252b5132 10662 }
252b5132 10663 s = "swc1";
252b5132
RH
10664 goto ldd_std;
10665
e407c74b
NC
10666 case M_LQ_AB:
10667 fmt = "t,o(b)";
10668 s = "lq";
10669 goto ld;
10670
10671 case M_SQ_AB:
10672 fmt = "t,o(b)";
10673 s = "sq";
10674 goto ld_st;
10675
252b5132 10676 case M_LD_AB:
df58fc94 10677 fmt = "t,o(b)";
ca4e0257 10678 if (HAVE_64BIT_GPRS)
252b5132
RH
10679 {
10680 s = "ld";
10681 goto ld;
10682 }
252b5132 10683 s = "lw";
252b5132
RH
10684 goto ldd_std;
10685
10686 case M_SD_AB:
df58fc94 10687 fmt = "t,o(b)";
ca4e0257 10688 if (HAVE_64BIT_GPRS)
252b5132
RH
10689 {
10690 s = "sd";
df58fc94 10691 goto ld_st;
252b5132 10692 }
252b5132 10693 s = "sw";
252b5132
RH
10694
10695 ldd_std:
f2ae14a1
RS
10696 /* Even on a big endian machine $fn comes before $fn+1. We have
10697 to adjust when loading from memory. We set coproc if we must
10698 load $fn+1 first. */
10699 /* Itbl support may require additional care here. */
10700 if (!target_big_endian)
10701 coproc = 0;
10702
10703 if (small_offset_p (0, align, 16))
10704 {
10705 ep = &offset_expr;
10706 if (!small_offset_p (4, align, 16))
10707 {
10708 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", AT, breg,
10709 -1, offset_reloc[0], offset_reloc[1],
10710 offset_reloc[2]);
10711 expr1.X_add_number = 0;
10712 ep = &expr1;
10713 breg = AT;
10714 used_at = 1;
10715 offset_reloc[0] = BFD_RELOC_LO16;
10716 offset_reloc[1] = BFD_RELOC_UNUSED;
10717 offset_reloc[2] = BFD_RELOC_UNUSED;
10718 }
10719 if (strcmp (s, "lw") == 0 && treg == breg)
10720 {
10721 ep->X_add_number += 4;
10722 macro_build (ep, s, fmt, treg + 1, -1, offset_reloc[0],
10723 offset_reloc[1], offset_reloc[2], breg);
10724 ep->X_add_number -= 4;
10725 macro_build (ep, s, fmt, treg, -1, offset_reloc[0],
10726 offset_reloc[1], offset_reloc[2], breg);
10727 }
10728 else
10729 {
10730 macro_build (ep, s, fmt, coproc ? treg + 1 : treg, -1,
10731 offset_reloc[0], offset_reloc[1], offset_reloc[2],
10732 breg);
10733 ep->X_add_number += 4;
10734 macro_build (ep, s, fmt, coproc ? treg : treg + 1, -1,
10735 offset_reloc[0], offset_reloc[1], offset_reloc[2],
10736 breg);
10737 }
10738 break;
10739 }
10740
252b5132
RH
10741 if (offset_expr.X_op != O_symbol
10742 && offset_expr.X_op != O_constant)
10743 {
f71d0d44 10744 as_bad (_("Expression too complex"));
252b5132
RH
10745 offset_expr.X_op = O_constant;
10746 }
10747
2051e8c4
MR
10748 if (HAVE_32BIT_ADDRESSES
10749 && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
55e08f71
NC
10750 {
10751 char value [32];
10752
10753 sprintf_vma (value, offset_expr.X_add_number);
20e1fcfd 10754 as_bad (_("Number (0x%s) larger than 32 bits"), value);
55e08f71 10755 }
2051e8c4 10756
90ecf173 10757 if (mips_pic == NO_PIC || offset_expr.X_op == O_constant)
252b5132
RH
10758 {
10759 /* If this is a reference to a GP relative symbol, we want
cdf6fd85
TS
10760 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
10761 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
252b5132
RH
10762 If we have a base register, we use this
10763 addu $at,$breg,$gp
cdf6fd85
TS
10764 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
10765 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
252b5132
RH
10766 If this is not a GP relative symbol, we want
10767 lui $at,<sym> (BFD_RELOC_HI16_S)
10768 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
10769 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
10770 If there is a base register, we add it to $at after the
10771 lui instruction. If there is a constant, we always use
10772 the last case. */
39a59cf8
MR
10773 if (offset_expr.X_op == O_symbol
10774 && (valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
6caf9ef4 10775 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
252b5132 10776 {
4d7206a2 10777 relax_start (offset_expr.X_add_symbol);
252b5132
RH
10778 if (breg == 0)
10779 {
c9914766 10780 tempreg = mips_gp_register;
252b5132
RH
10781 }
10782 else
10783 {
67c0d1eb 10784 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
17a2f251 10785 AT, breg, mips_gp_register);
252b5132 10786 tempreg = AT;
252b5132
RH
10787 used_at = 1;
10788 }
10789
beae10d5 10790 /* Itbl support may require additional care here. */
67c0d1eb 10791 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
17a2f251 10792 BFD_RELOC_GPREL16, tempreg);
252b5132
RH
10793 offset_expr.X_add_number += 4;
10794
10795 /* Set mips_optimize to 2 to avoid inserting an
10796 undesired nop. */
10797 hold_mips_optimize = mips_optimize;
10798 mips_optimize = 2;
beae10d5 10799 /* Itbl support may require additional care here. */
67c0d1eb 10800 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
17a2f251 10801 BFD_RELOC_GPREL16, tempreg);
252b5132
RH
10802 mips_optimize = hold_mips_optimize;
10803
4d7206a2 10804 relax_switch ();
252b5132 10805
0970e49e 10806 offset_expr.X_add_number -= 4;
252b5132 10807 }
8fc2e39e 10808 used_at = 1;
f2ae14a1
RS
10809 if (offset_high_part (offset_expr.X_add_number, 16)
10810 != offset_high_part (offset_expr.X_add_number + 4, 16))
10811 {
10812 load_address (AT, &offset_expr, &used_at);
10813 offset_expr.X_op = O_constant;
10814 offset_expr.X_add_number = 0;
10815 }
10816 else
10817 macro_build_lui (&offset_expr, AT);
252b5132 10818 if (breg != 0)
67c0d1eb 10819 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
beae10d5 10820 /* Itbl support may require additional care here. */
67c0d1eb 10821 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
17a2f251 10822 BFD_RELOC_LO16, AT);
252b5132
RH
10823 /* FIXME: How do we handle overflow here? */
10824 offset_expr.X_add_number += 4;
beae10d5 10825 /* Itbl support may require additional care here. */
67c0d1eb 10826 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
17a2f251 10827 BFD_RELOC_LO16, AT);
4d7206a2
RS
10828 if (mips_relax.sequence)
10829 relax_end ();
bdaaa2e1 10830 }
0a44bf69 10831 else if (!mips_big_got)
252b5132 10832 {
252b5132
RH
10833 /* If this is a reference to an external symbol, we want
10834 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10835 nop
10836 <op> $treg,0($at)
10837 <op> $treg+1,4($at)
10838 Otherwise we want
10839 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10840 nop
10841 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
10842 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
10843 If there is a base register we add it to $at before the
10844 lwc1 instructions. If there is a constant we include it
10845 in the lwc1 instructions. */
10846 used_at = 1;
10847 expr1.X_add_number = offset_expr.X_add_number;
252b5132
RH
10848 if (expr1.X_add_number < -0x8000
10849 || expr1.X_add_number >= 0x8000 - 4)
10850 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
67c0d1eb 10851 load_got_offset (AT, &offset_expr);
269137b2 10852 load_delay_nop ();
252b5132 10853 if (breg != 0)
67c0d1eb 10854 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
252b5132
RH
10855
10856 /* Set mips_optimize to 2 to avoid inserting an undesired
10857 nop. */
10858 hold_mips_optimize = mips_optimize;
10859 mips_optimize = 2;
4d7206a2 10860
beae10d5 10861 /* Itbl support may require additional care here. */
4d7206a2 10862 relax_start (offset_expr.X_add_symbol);
67c0d1eb
RS
10863 macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg,
10864 BFD_RELOC_LO16, AT);
4d7206a2 10865 expr1.X_add_number += 4;
67c0d1eb
RS
10866 macro_build (&expr1, s, fmt, coproc ? treg : treg + 1,
10867 BFD_RELOC_LO16, AT);
4d7206a2 10868 relax_switch ();
67c0d1eb
RS
10869 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
10870 BFD_RELOC_LO16, AT);
4d7206a2 10871 offset_expr.X_add_number += 4;
67c0d1eb
RS
10872 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
10873 BFD_RELOC_LO16, AT);
4d7206a2 10874 relax_end ();
252b5132 10875
4d7206a2 10876 mips_optimize = hold_mips_optimize;
252b5132 10877 }
0a44bf69 10878 else if (mips_big_got)
252b5132 10879 {
67c0d1eb 10880 int gpdelay;
252b5132
RH
10881
10882 /* If this is a reference to an external symbol, we want
10883 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10884 addu $at,$at,$gp
10885 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
10886 nop
10887 <op> $treg,0($at)
10888 <op> $treg+1,4($at)
10889 Otherwise we want
10890 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10891 nop
10892 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
10893 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
10894 If there is a base register we add it to $at before the
10895 lwc1 instructions. If there is a constant we include it
10896 in the lwc1 instructions. */
10897 used_at = 1;
10898 expr1.X_add_number = offset_expr.X_add_number;
10899 offset_expr.X_add_number = 0;
10900 if (expr1.X_add_number < -0x8000
10901 || expr1.X_add_number >= 0x8000 - 4)
10902 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
67c0d1eb 10903 gpdelay = reg_needs_delay (mips_gp_register);
4d7206a2 10904 relax_start (offset_expr.X_add_symbol);
df58fc94 10905 macro_build (&offset_expr, "lui", LUI_FMT,
67c0d1eb
RS
10906 AT, BFD_RELOC_MIPS_GOT_HI16);
10907 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
17a2f251 10908 AT, AT, mips_gp_register);
67c0d1eb 10909 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
17a2f251 10910 AT, BFD_RELOC_MIPS_GOT_LO16, AT);
269137b2 10911 load_delay_nop ();
252b5132 10912 if (breg != 0)
67c0d1eb 10913 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
beae10d5 10914 /* Itbl support may require additional care here. */
67c0d1eb 10915 macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg,
17a2f251 10916 BFD_RELOC_LO16, AT);
252b5132
RH
10917 expr1.X_add_number += 4;
10918
10919 /* Set mips_optimize to 2 to avoid inserting an undesired
10920 nop. */
10921 hold_mips_optimize = mips_optimize;
10922 mips_optimize = 2;
beae10d5 10923 /* Itbl support may require additional care here. */
67c0d1eb 10924 macro_build (&expr1, s, fmt, coproc ? treg : treg + 1,
17a2f251 10925 BFD_RELOC_LO16, AT);
252b5132
RH
10926 mips_optimize = hold_mips_optimize;
10927 expr1.X_add_number -= 4;
10928
4d7206a2
RS
10929 relax_switch ();
10930 offset_expr.X_add_number = expr1.X_add_number;
67c0d1eb
RS
10931 if (gpdelay)
10932 macro_build (NULL, "nop", "");
10933 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
10934 BFD_RELOC_MIPS_GOT16, mips_gp_register);
269137b2 10935 load_delay_nop ();
252b5132 10936 if (breg != 0)
67c0d1eb 10937 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
beae10d5 10938 /* Itbl support may require additional care here. */
67c0d1eb
RS
10939 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
10940 BFD_RELOC_LO16, AT);
4d7206a2 10941 offset_expr.X_add_number += 4;
252b5132
RH
10942
10943 /* Set mips_optimize to 2 to avoid inserting an undesired
10944 nop. */
10945 hold_mips_optimize = mips_optimize;
10946 mips_optimize = 2;
beae10d5 10947 /* Itbl support may require additional care here. */
67c0d1eb
RS
10948 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
10949 BFD_RELOC_LO16, AT);
252b5132 10950 mips_optimize = hold_mips_optimize;
4d7206a2 10951 relax_end ();
252b5132 10952 }
252b5132
RH
10953 else
10954 abort ();
10955
252b5132 10956 break;
dd6a37e7
AP
10957
10958 case M_SAA_AB:
dd6a37e7 10959 s = "saa";
7f3c4072 10960 offbits = 0;
dd6a37e7
AP
10961 fmt = "t,(b)";
10962 goto ld_st;
10963 case M_SAAD_AB:
dd6a37e7 10964 s = "saad";
7f3c4072 10965 offbits = 0;
dd6a37e7
AP
10966 fmt = "t,(b)";
10967 goto ld_st;
10968
252b5132
RH
10969 /* New code added to support COPZ instructions.
10970 This code builds table entries out of the macros in mip_opcodes.
10971 R4000 uses interlocks to handle coproc delays.
10972 Other chips (like the R3000) require nops to be inserted for delays.
10973
f72c8c98 10974 FIXME: Currently, we require that the user handle delays.
252b5132
RH
10975 In order to fill delay slots for non-interlocked chips,
10976 we must have a way to specify delays based on the coprocessor.
10977 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
10978 What are the side-effects of the cop instruction?
10979 What cache support might we have and what are its effects?
10980 Both coprocessor & memory require delays. how long???
bdaaa2e1 10981 What registers are read/set/modified?
252b5132
RH
10982
10983 If an itbl is provided to interpret cop instructions,
bdaaa2e1 10984 this knowledge can be encoded in the itbl spec. */
252b5132
RH
10985
10986 case M_COP0:
10987 s = "c0";
10988 goto copz;
10989 case M_COP1:
10990 s = "c1";
10991 goto copz;
10992 case M_COP2:
10993 s = "c2";
10994 goto copz;
10995 case M_COP3:
10996 s = "c3";
10997 copz:
df58fc94 10998 gas_assert (!mips_opts.micromips);
252b5132
RH
10999 /* For now we just do C (same as Cz). The parameter will be
11000 stored in insn_opcode by mips_ip. */
c8276761 11001 macro_build (NULL, s, "C", (int) ip->insn_opcode);
8fc2e39e 11002 break;
252b5132 11003
ea1fb5dc 11004 case M_MOVE:
67c0d1eb 11005 move_register (dreg, sreg);
8fc2e39e 11006 break;
ea1fb5dc 11007
833794fc
MR
11008 case M_MOVEP:
11009 gas_assert (mips_opts.micromips);
11010 gas_assert (mips_opts.insn32);
e76ff5ab
RS
11011 dreg = micromips_to_32_reg_h_map1[EXTRACT_OPERAND (1, MH, *ip)];
11012 breg = micromips_to_32_reg_h_map2[EXTRACT_OPERAND (1, MH, *ip)];
833794fc
MR
11013 sreg = micromips_to_32_reg_m_map[EXTRACT_OPERAND (1, MM, *ip)];
11014 treg = micromips_to_32_reg_n_map[EXTRACT_OPERAND (1, MN, *ip)];
11015 move_register (dreg, sreg);
11016 move_register (breg, treg);
11017 break;
11018
252b5132
RH
11019 case M_DMUL:
11020 dbl = 1;
11021 case M_MUL:
e407c74b
NC
11022 if (mips_opts.arch == CPU_R5900)
11023 {
11024 macro_build (NULL, dbl ? "dmultu" : "multu", "d,s,t", dreg, sreg, treg);
11025 }
11026 else
11027 {
67c0d1eb 11028 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", sreg, treg);
df58fc94 11029 macro_build (NULL, "mflo", MFHL_FMT, dreg);
e407c74b 11030 }
8fc2e39e 11031 break;
252b5132
RH
11032
11033 case M_DMUL_I:
11034 dbl = 1;
11035 case M_MUL_I:
11036 /* The MIPS assembler some times generates shifts and adds. I'm
11037 not trying to be that fancy. GCC should do this for us
11038 anyway. */
8fc2e39e 11039 used_at = 1;
67c0d1eb
RS
11040 load_register (AT, &imm_expr, dbl);
11041 macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, AT);
df58fc94 11042 macro_build (NULL, "mflo", MFHL_FMT, dreg);
252b5132
RH
11043 break;
11044
11045 case M_DMULO_I:
11046 dbl = 1;
11047 case M_MULO_I:
11048 imm = 1;
11049 goto do_mulo;
11050
11051 case M_DMULO:
11052 dbl = 1;
11053 case M_MULO:
11054 do_mulo:
7d10b47d 11055 start_noreorder ();
8fc2e39e 11056 used_at = 1;
252b5132 11057 if (imm)
67c0d1eb
RS
11058 load_register (AT, &imm_expr, dbl);
11059 macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, imm ? AT : treg);
df58fc94
RS
11060 macro_build (NULL, "mflo", MFHL_FMT, dreg);
11061 macro_build (NULL, dbl ? "dsra32" : "sra", SHFT_FMT, dreg, dreg, RA);
11062 macro_build (NULL, "mfhi", MFHL_FMT, AT);
252b5132 11063 if (mips_trap)
df58fc94 11064 macro_build (NULL, "tne", TRAP_FMT, dreg, AT, 6);
252b5132
RH
11065 else
11066 {
df58fc94
RS
11067 if (mips_opts.micromips)
11068 micromips_label_expr (&label_expr);
11069 else
11070 label_expr.X_add_number = 8;
11071 macro_build (&label_expr, "beq", "s,t,p", dreg, AT);
a605d2b3 11072 macro_build (NULL, "nop", "");
df58fc94
RS
11073 macro_build (NULL, "break", BRK_FMT, 6);
11074 if (mips_opts.micromips)
11075 micromips_add_label ();
252b5132 11076 }
7d10b47d 11077 end_noreorder ();
df58fc94 11078 macro_build (NULL, "mflo", MFHL_FMT, dreg);
252b5132
RH
11079 break;
11080
11081 case M_DMULOU_I:
11082 dbl = 1;
11083 case M_MULOU_I:
11084 imm = 1;
11085 goto do_mulou;
11086
11087 case M_DMULOU:
11088 dbl = 1;
11089 case M_MULOU:
11090 do_mulou:
7d10b47d 11091 start_noreorder ();
8fc2e39e 11092 used_at = 1;
252b5132 11093 if (imm)
67c0d1eb
RS
11094 load_register (AT, &imm_expr, dbl);
11095 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t",
17a2f251 11096 sreg, imm ? AT : treg);
df58fc94
RS
11097 macro_build (NULL, "mfhi", MFHL_FMT, AT);
11098 macro_build (NULL, "mflo", MFHL_FMT, dreg);
252b5132 11099 if (mips_trap)
df58fc94 11100 macro_build (NULL, "tne", TRAP_FMT, AT, ZERO, 6);
252b5132
RH
11101 else
11102 {
df58fc94
RS
11103 if (mips_opts.micromips)
11104 micromips_label_expr (&label_expr);
11105 else
11106 label_expr.X_add_number = 8;
11107 macro_build (&label_expr, "beq", "s,t,p", AT, ZERO);
a605d2b3 11108 macro_build (NULL, "nop", "");
df58fc94
RS
11109 macro_build (NULL, "break", BRK_FMT, 6);
11110 if (mips_opts.micromips)
11111 micromips_add_label ();
252b5132 11112 }
7d10b47d 11113 end_noreorder ();
252b5132
RH
11114 break;
11115
771c7ce4 11116 case M_DROL:
fef14a42 11117 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
82dd0097
CD
11118 {
11119 if (dreg == sreg)
11120 {
11121 tempreg = AT;
11122 used_at = 1;
11123 }
11124 else
11125 {
11126 tempreg = dreg;
82dd0097 11127 }
67c0d1eb
RS
11128 macro_build (NULL, "dnegu", "d,w", tempreg, treg);
11129 macro_build (NULL, "drorv", "d,t,s", dreg, sreg, tempreg);
8fc2e39e 11130 break;
82dd0097 11131 }
8fc2e39e 11132 used_at = 1;
c80c840e 11133 macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, treg);
67c0d1eb
RS
11134 macro_build (NULL, "dsrlv", "d,t,s", AT, sreg, AT);
11135 macro_build (NULL, "dsllv", "d,t,s", dreg, sreg, treg);
11136 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
771c7ce4
TS
11137 break;
11138
252b5132 11139 case M_ROL:
fef14a42 11140 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
82dd0097
CD
11141 {
11142 if (dreg == sreg)
11143 {
11144 tempreg = AT;
11145 used_at = 1;
11146 }
11147 else
11148 {
11149 tempreg = dreg;
82dd0097 11150 }
67c0d1eb
RS
11151 macro_build (NULL, "negu", "d,w", tempreg, treg);
11152 macro_build (NULL, "rorv", "d,t,s", dreg, sreg, tempreg);
8fc2e39e 11153 break;
82dd0097 11154 }
8fc2e39e 11155 used_at = 1;
c80c840e 11156 macro_build (NULL, "subu", "d,v,t", AT, ZERO, treg);
67c0d1eb
RS
11157 macro_build (NULL, "srlv", "d,t,s", AT, sreg, AT);
11158 macro_build (NULL, "sllv", "d,t,s", dreg, sreg, treg);
11159 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
252b5132
RH
11160 break;
11161
771c7ce4
TS
11162 case M_DROL_I:
11163 {
11164 unsigned int rot;
91d6fa6a
NC
11165 char *l;
11166 char *rr;
771c7ce4
TS
11167
11168 if (imm_expr.X_op != O_constant)
82dd0097 11169 as_bad (_("Improper rotate count"));
771c7ce4 11170 rot = imm_expr.X_add_number & 0x3f;
fef14a42 11171 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
60b63b72
RS
11172 {
11173 rot = (64 - rot) & 0x3f;
11174 if (rot >= 32)
df58fc94 11175 macro_build (NULL, "dror32", SHFT_FMT, dreg, sreg, rot - 32);
60b63b72 11176 else
df58fc94 11177 macro_build (NULL, "dror", SHFT_FMT, dreg, sreg, rot);
8fc2e39e 11178 break;
60b63b72 11179 }
483fc7cd 11180 if (rot == 0)
483fc7cd 11181 {
df58fc94 11182 macro_build (NULL, "dsrl", SHFT_FMT, dreg, sreg, 0);
8fc2e39e 11183 break;
483fc7cd 11184 }
82dd0097 11185 l = (rot < 0x20) ? "dsll" : "dsll32";
91d6fa6a 11186 rr = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32";
82dd0097 11187 rot &= 0x1f;
8fc2e39e 11188 used_at = 1;
df58fc94
RS
11189 macro_build (NULL, l, SHFT_FMT, AT, sreg, rot);
11190 macro_build (NULL, rr, SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f);
67c0d1eb 11191 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
771c7ce4
TS
11192 }
11193 break;
11194
252b5132 11195 case M_ROL_I:
771c7ce4
TS
11196 {
11197 unsigned int rot;
11198
11199 if (imm_expr.X_op != O_constant)
82dd0097 11200 as_bad (_("Improper rotate count"));
771c7ce4 11201 rot = imm_expr.X_add_number & 0x1f;
fef14a42 11202 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
60b63b72 11203 {
df58fc94 11204 macro_build (NULL, "ror", SHFT_FMT, dreg, sreg, (32 - rot) & 0x1f);
8fc2e39e 11205 break;
60b63b72 11206 }
483fc7cd 11207 if (rot == 0)
483fc7cd 11208 {
df58fc94 11209 macro_build (NULL, "srl", SHFT_FMT, dreg, sreg, 0);
8fc2e39e 11210 break;
483fc7cd 11211 }
8fc2e39e 11212 used_at = 1;
df58fc94
RS
11213 macro_build (NULL, "sll", SHFT_FMT, AT, sreg, rot);
11214 macro_build (NULL, "srl", SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f);
67c0d1eb 11215 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
771c7ce4
TS
11216 }
11217 break;
11218
11219 case M_DROR:
fef14a42 11220 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
82dd0097 11221 {
67c0d1eb 11222 macro_build (NULL, "drorv", "d,t,s", dreg, sreg, treg);
8fc2e39e 11223 break;
82dd0097 11224 }
8fc2e39e 11225 used_at = 1;
c80c840e 11226 macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, treg);
67c0d1eb
RS
11227 macro_build (NULL, "dsllv", "d,t,s", AT, sreg, AT);
11228 macro_build (NULL, "dsrlv", "d,t,s", dreg, sreg, treg);
11229 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
252b5132
RH
11230 break;
11231
11232 case M_ROR:
fef14a42 11233 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
82dd0097 11234 {
67c0d1eb 11235 macro_build (NULL, "rorv", "d,t,s", dreg, sreg, treg);
8fc2e39e 11236 break;
82dd0097 11237 }
8fc2e39e 11238 used_at = 1;
c80c840e 11239 macro_build (NULL, "subu", "d,v,t", AT, ZERO, treg);
67c0d1eb
RS
11240 macro_build (NULL, "sllv", "d,t,s", AT, sreg, AT);
11241 macro_build (NULL, "srlv", "d,t,s", dreg, sreg, treg);
11242 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
252b5132
RH
11243 break;
11244
771c7ce4
TS
11245 case M_DROR_I:
11246 {
11247 unsigned int rot;
91d6fa6a
NC
11248 char *l;
11249 char *rr;
771c7ce4
TS
11250
11251 if (imm_expr.X_op != O_constant)
82dd0097 11252 as_bad (_("Improper rotate count"));
771c7ce4 11253 rot = imm_expr.X_add_number & 0x3f;
fef14a42 11254 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
82dd0097
CD
11255 {
11256 if (rot >= 32)
df58fc94 11257 macro_build (NULL, "dror32", SHFT_FMT, dreg, sreg, rot - 32);
82dd0097 11258 else
df58fc94 11259 macro_build (NULL, "dror", SHFT_FMT, dreg, sreg, rot);
8fc2e39e 11260 break;
82dd0097 11261 }
483fc7cd 11262 if (rot == 0)
483fc7cd 11263 {
df58fc94 11264 macro_build (NULL, "dsrl", SHFT_FMT, dreg, sreg, 0);
8fc2e39e 11265 break;
483fc7cd 11266 }
91d6fa6a 11267 rr = (rot < 0x20) ? "dsrl" : "dsrl32";
82dd0097
CD
11268 l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32";
11269 rot &= 0x1f;
8fc2e39e 11270 used_at = 1;
df58fc94
RS
11271 macro_build (NULL, rr, SHFT_FMT, AT, sreg, rot);
11272 macro_build (NULL, l, SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f);
67c0d1eb 11273 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
771c7ce4
TS
11274 }
11275 break;
11276
252b5132 11277 case M_ROR_I:
771c7ce4
TS
11278 {
11279 unsigned int rot;
11280
11281 if (imm_expr.X_op != O_constant)
82dd0097 11282 as_bad (_("Improper rotate count"));
771c7ce4 11283 rot = imm_expr.X_add_number & 0x1f;
fef14a42 11284 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
82dd0097 11285 {
df58fc94 11286 macro_build (NULL, "ror", SHFT_FMT, dreg, sreg, rot);
8fc2e39e 11287 break;
82dd0097 11288 }
483fc7cd 11289 if (rot == 0)
483fc7cd 11290 {
df58fc94 11291 macro_build (NULL, "srl", SHFT_FMT, dreg, sreg, 0);
8fc2e39e 11292 break;
483fc7cd 11293 }
8fc2e39e 11294 used_at = 1;
df58fc94
RS
11295 macro_build (NULL, "srl", SHFT_FMT, AT, sreg, rot);
11296 macro_build (NULL, "sll", SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f);
67c0d1eb 11297 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
771c7ce4 11298 }
252b5132
RH
11299 break;
11300
252b5132
RH
11301 case M_SEQ:
11302 if (sreg == 0)
67c0d1eb 11303 macro_build (&expr1, "sltiu", "t,r,j", dreg, treg, BFD_RELOC_LO16);
252b5132 11304 else if (treg == 0)
67c0d1eb 11305 macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
252b5132
RH
11306 else
11307 {
67c0d1eb
RS
11308 macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg);
11309 macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16);
252b5132 11310 }
8fc2e39e 11311 break;
252b5132
RH
11312
11313 case M_SEQ_I:
11314 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
11315 {
67c0d1eb 11316 macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
8fc2e39e 11317 break;
252b5132
RH
11318 }
11319 if (sreg == 0)
11320 {
11321 as_warn (_("Instruction %s: result is always false"),
11322 ip->insn_mo->name);
67c0d1eb 11323 move_register (dreg, 0);
8fc2e39e 11324 break;
252b5132 11325 }
dd3cbb7e
NC
11326 if (CPU_HAS_SEQ (mips_opts.arch)
11327 && -512 <= imm_expr.X_add_number
11328 && imm_expr.X_add_number < 512)
11329 {
11330 macro_build (NULL, "seqi", "t,r,+Q", dreg, sreg,
750bdd57 11331 (int) imm_expr.X_add_number);
dd3cbb7e
NC
11332 break;
11333 }
252b5132
RH
11334 if (imm_expr.X_op == O_constant
11335 && imm_expr.X_add_number >= 0
11336 && imm_expr.X_add_number < 0x10000)
11337 {
67c0d1eb 11338 macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16);
252b5132
RH
11339 }
11340 else if (imm_expr.X_op == O_constant
11341 && imm_expr.X_add_number > -0x8000
11342 && imm_expr.X_add_number < 0)
11343 {
11344 imm_expr.X_add_number = -imm_expr.X_add_number;
67c0d1eb 11345 macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu",
17a2f251 11346 "t,r,j", dreg, sreg, BFD_RELOC_LO16);
252b5132 11347 }
dd3cbb7e
NC
11348 else if (CPU_HAS_SEQ (mips_opts.arch))
11349 {
11350 used_at = 1;
11351 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
11352 macro_build (NULL, "seq", "d,v,t", dreg, sreg, AT);
11353 break;
11354 }
252b5132
RH
11355 else
11356 {
67c0d1eb
RS
11357 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
11358 macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT);
252b5132
RH
11359 used_at = 1;
11360 }
67c0d1eb 11361 macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16);
8fc2e39e 11362 break;
252b5132
RH
11363
11364 case M_SGE: /* sreg >= treg <==> not (sreg < treg) */
11365 s = "slt";
11366 goto sge;
11367 case M_SGEU:
11368 s = "sltu";
11369 sge:
67c0d1eb
RS
11370 macro_build (NULL, s, "d,v,t", dreg, sreg, treg);
11371 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
8fc2e39e 11372 break;
252b5132
RH
11373
11374 case M_SGE_I: /* sreg >= I <==> not (sreg < I) */
11375 case M_SGEU_I:
11376 if (imm_expr.X_op == O_constant
11377 && imm_expr.X_add_number >= -0x8000
11378 && imm_expr.X_add_number < 0x8000)
11379 {
67c0d1eb
RS
11380 macro_build (&imm_expr, mask == M_SGE_I ? "slti" : "sltiu", "t,r,j",
11381 dreg, sreg, BFD_RELOC_LO16);
252b5132
RH
11382 }
11383 else
11384 {
67c0d1eb
RS
11385 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
11386 macro_build (NULL, mask == M_SGE_I ? "slt" : "sltu", "d,v,t",
11387 dreg, sreg, AT);
252b5132
RH
11388 used_at = 1;
11389 }
67c0d1eb 11390 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
8fc2e39e 11391 break;
252b5132
RH
11392
11393 case M_SGT: /* sreg > treg <==> treg < sreg */
11394 s = "slt";
11395 goto sgt;
11396 case M_SGTU:
11397 s = "sltu";
11398 sgt:
67c0d1eb 11399 macro_build (NULL, s, "d,v,t", dreg, treg, sreg);
8fc2e39e 11400 break;
252b5132
RH
11401
11402 case M_SGT_I: /* sreg > I <==> I < sreg */
11403 s = "slt";
11404 goto sgti;
11405 case M_SGTU_I:
11406 s = "sltu";
11407 sgti:
8fc2e39e 11408 used_at = 1;
67c0d1eb
RS
11409 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
11410 macro_build (NULL, s, "d,v,t", dreg, AT, sreg);
252b5132
RH
11411 break;
11412
2396cfb9 11413 case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
252b5132
RH
11414 s = "slt";
11415 goto sle;
11416 case M_SLEU:
11417 s = "sltu";
11418 sle:
67c0d1eb
RS
11419 macro_build (NULL, s, "d,v,t", dreg, treg, sreg);
11420 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
8fc2e39e 11421 break;
252b5132 11422
2396cfb9 11423 case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
252b5132
RH
11424 s = "slt";
11425 goto slei;
11426 case M_SLEU_I:
11427 s = "sltu";
11428 slei:
8fc2e39e 11429 used_at = 1;
67c0d1eb
RS
11430 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
11431 macro_build (NULL, s, "d,v,t", dreg, AT, sreg);
11432 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
252b5132
RH
11433 break;
11434
11435 case M_SLT_I:
11436 if (imm_expr.X_op == O_constant
11437 && imm_expr.X_add_number >= -0x8000
11438 && imm_expr.X_add_number < 0x8000)
11439 {
67c0d1eb 11440 macro_build (&imm_expr, "slti", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
8fc2e39e 11441 break;
252b5132 11442 }
8fc2e39e 11443 used_at = 1;
67c0d1eb
RS
11444 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
11445 macro_build (NULL, "slt", "d,v,t", dreg, sreg, AT);
252b5132
RH
11446 break;
11447
11448 case M_SLTU_I:
11449 if (imm_expr.X_op == O_constant
11450 && imm_expr.X_add_number >= -0x8000
11451 && imm_expr.X_add_number < 0x8000)
11452 {
67c0d1eb 11453 macro_build (&imm_expr, "sltiu", "t,r,j", dreg, sreg,
17a2f251 11454 BFD_RELOC_LO16);
8fc2e39e 11455 break;
252b5132 11456 }
8fc2e39e 11457 used_at = 1;
67c0d1eb
RS
11458 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
11459 macro_build (NULL, "sltu", "d,v,t", dreg, sreg, AT);
252b5132
RH
11460 break;
11461
11462 case M_SNE:
11463 if (sreg == 0)
67c0d1eb 11464 macro_build (NULL, "sltu", "d,v,t", dreg, 0, treg);
252b5132 11465 else if (treg == 0)
67c0d1eb 11466 macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg);
252b5132
RH
11467 else
11468 {
67c0d1eb
RS
11469 macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg);
11470 macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg);
252b5132 11471 }
8fc2e39e 11472 break;
252b5132
RH
11473
11474 case M_SNE_I:
11475 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
11476 {
67c0d1eb 11477 macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg);
8fc2e39e 11478 break;
252b5132
RH
11479 }
11480 if (sreg == 0)
11481 {
11482 as_warn (_("Instruction %s: result is always true"),
11483 ip->insn_mo->name);
67c0d1eb
RS
11484 macro_build (&expr1, HAVE_32BIT_GPRS ? "addiu" : "daddiu", "t,r,j",
11485 dreg, 0, BFD_RELOC_LO16);
8fc2e39e 11486 break;
252b5132 11487 }
dd3cbb7e
NC
11488 if (CPU_HAS_SEQ (mips_opts.arch)
11489 && -512 <= imm_expr.X_add_number
11490 && imm_expr.X_add_number < 512)
11491 {
11492 macro_build (NULL, "snei", "t,r,+Q", dreg, sreg,
750bdd57 11493 (int) imm_expr.X_add_number);
dd3cbb7e
NC
11494 break;
11495 }
252b5132
RH
11496 if (imm_expr.X_op == O_constant
11497 && imm_expr.X_add_number >= 0
11498 && imm_expr.X_add_number < 0x10000)
11499 {
67c0d1eb 11500 macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16);
252b5132
RH
11501 }
11502 else if (imm_expr.X_op == O_constant
11503 && imm_expr.X_add_number > -0x8000
11504 && imm_expr.X_add_number < 0)
11505 {
11506 imm_expr.X_add_number = -imm_expr.X_add_number;
67c0d1eb 11507 macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu",
17a2f251 11508 "t,r,j", dreg, sreg, BFD_RELOC_LO16);
252b5132 11509 }
dd3cbb7e
NC
11510 else if (CPU_HAS_SEQ (mips_opts.arch))
11511 {
11512 used_at = 1;
11513 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
11514 macro_build (NULL, "sne", "d,v,t", dreg, sreg, AT);
11515 break;
11516 }
252b5132
RH
11517 else
11518 {
67c0d1eb
RS
11519 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
11520 macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT);
252b5132
RH
11521 used_at = 1;
11522 }
67c0d1eb 11523 macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg);
8fc2e39e 11524 break;
252b5132 11525
df58fc94
RS
11526 case M_SUB_I:
11527 s = "addi";
11528 s2 = "sub";
11529 goto do_subi;
11530 case M_SUBU_I:
11531 s = "addiu";
11532 s2 = "subu";
11533 goto do_subi;
252b5132
RH
11534 case M_DSUB_I:
11535 dbl = 1;
df58fc94
RS
11536 s = "daddi";
11537 s2 = "dsub";
11538 if (!mips_opts.micromips)
11539 goto do_subi;
252b5132 11540 if (imm_expr.X_op == O_constant
df58fc94
RS
11541 && imm_expr.X_add_number > -0x200
11542 && imm_expr.X_add_number <= 0x200)
252b5132 11543 {
df58fc94 11544 macro_build (NULL, s, "t,r,.", dreg, sreg, -imm_expr.X_add_number);
8fc2e39e 11545 break;
252b5132 11546 }
df58fc94 11547 goto do_subi_i;
252b5132
RH
11548 case M_DSUBU_I:
11549 dbl = 1;
df58fc94
RS
11550 s = "daddiu";
11551 s2 = "dsubu";
11552 do_subi:
252b5132
RH
11553 if (imm_expr.X_op == O_constant
11554 && imm_expr.X_add_number > -0x8000
11555 && imm_expr.X_add_number <= 0x8000)
11556 {
11557 imm_expr.X_add_number = -imm_expr.X_add_number;
df58fc94 11558 macro_build (&imm_expr, s, "t,r,j", dreg, sreg, BFD_RELOC_LO16);
8fc2e39e 11559 break;
252b5132 11560 }
df58fc94 11561 do_subi_i:
8fc2e39e 11562 used_at = 1;
67c0d1eb 11563 load_register (AT, &imm_expr, dbl);
df58fc94 11564 macro_build (NULL, s2, "d,v,t", dreg, sreg, AT);
252b5132
RH
11565 break;
11566
11567 case M_TEQ_I:
11568 s = "teq";
11569 goto trap;
11570 case M_TGE_I:
11571 s = "tge";
11572 goto trap;
11573 case M_TGEU_I:
11574 s = "tgeu";
11575 goto trap;
11576 case M_TLT_I:
11577 s = "tlt";
11578 goto trap;
11579 case M_TLTU_I:
11580 s = "tltu";
11581 goto trap;
11582 case M_TNE_I:
11583 s = "tne";
11584 trap:
8fc2e39e 11585 used_at = 1;
67c0d1eb
RS
11586 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
11587 macro_build (NULL, s, "s,t", sreg, AT);
252b5132
RH
11588 break;
11589
252b5132 11590 case M_TRUNCWS:
43841e91 11591 case M_TRUNCWD:
df58fc94 11592 gas_assert (!mips_opts.micromips);
0aa27725 11593 gas_assert (mips_opts.isa == ISA_MIPS1);
8fc2e39e 11594 used_at = 1;
252b5132
RH
11595 sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */
11596 dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */
11597
11598 /*
11599 * Is the double cfc1 instruction a bug in the mips assembler;
11600 * or is there a reason for it?
11601 */
7d10b47d 11602 start_noreorder ();
67c0d1eb
RS
11603 macro_build (NULL, "cfc1", "t,G", treg, RA);
11604 macro_build (NULL, "cfc1", "t,G", treg, RA);
11605 macro_build (NULL, "nop", "");
252b5132 11606 expr1.X_add_number = 3;
67c0d1eb 11607 macro_build (&expr1, "ori", "t,r,i", AT, treg, BFD_RELOC_LO16);
252b5132 11608 expr1.X_add_number = 2;
67c0d1eb
RS
11609 macro_build (&expr1, "xori", "t,r,i", AT, AT, BFD_RELOC_LO16);
11610 macro_build (NULL, "ctc1", "t,G", AT, RA);
11611 macro_build (NULL, "nop", "");
11612 macro_build (NULL, mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S",
11613 dreg, sreg);
11614 macro_build (NULL, "ctc1", "t,G", treg, RA);
11615 macro_build (NULL, "nop", "");
7d10b47d 11616 end_noreorder ();
252b5132
RH
11617 break;
11618
f2ae14a1 11619 case M_ULH_AB:
252b5132 11620 s = "lb";
df58fc94
RS
11621 s2 = "lbu";
11622 off = 1;
11623 goto uld_st;
f2ae14a1 11624 case M_ULHU_AB:
252b5132 11625 s = "lbu";
df58fc94
RS
11626 s2 = "lbu";
11627 off = 1;
11628 goto uld_st;
f2ae14a1 11629 case M_ULW_AB:
df58fc94
RS
11630 s = "lwl";
11631 s2 = "lwr";
7f3c4072 11632 offbits = (mips_opts.micromips ? 12 : 16);
df58fc94
RS
11633 off = 3;
11634 goto uld_st;
f2ae14a1 11635 case M_ULD_AB:
252b5132
RH
11636 s = "ldl";
11637 s2 = "ldr";
7f3c4072 11638 offbits = (mips_opts.micromips ? 12 : 16);
252b5132 11639 off = 7;
df58fc94 11640 goto uld_st;
f2ae14a1 11641 case M_USH_AB:
df58fc94
RS
11642 s = "sb";
11643 s2 = "sb";
11644 off = 1;
11645 ust = 1;
11646 goto uld_st;
f2ae14a1 11647 case M_USW_AB:
df58fc94
RS
11648 s = "swl";
11649 s2 = "swr";
7f3c4072 11650 offbits = (mips_opts.micromips ? 12 : 16);
252b5132 11651 off = 3;
df58fc94
RS
11652 ust = 1;
11653 goto uld_st;
f2ae14a1 11654 case M_USD_AB:
df58fc94
RS
11655 s = "sdl";
11656 s2 = "sdr";
7f3c4072 11657 offbits = (mips_opts.micromips ? 12 : 16);
df58fc94
RS
11658 off = 7;
11659 ust = 1;
11660
11661 uld_st:
f2ae14a1 11662 large_offset = !small_offset_p (off, align, offbits);
df58fc94
RS
11663 ep = &offset_expr;
11664 expr1.X_add_number = 0;
f2ae14a1 11665 if (large_offset)
df58fc94
RS
11666 {
11667 used_at = 1;
11668 tempreg = AT;
f2ae14a1
RS
11669 if (small_offset_p (0, align, 16))
11670 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", tempreg, breg, -1,
11671 offset_reloc[0], offset_reloc[1], offset_reloc[2]);
11672 else
11673 {
11674 load_address (tempreg, ep, &used_at);
11675 if (breg != 0)
11676 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11677 tempreg, tempreg, breg);
11678 }
11679 offset_reloc[0] = BFD_RELOC_LO16;
11680 offset_reloc[1] = BFD_RELOC_UNUSED;
11681 offset_reloc[2] = BFD_RELOC_UNUSED;
df58fc94
RS
11682 breg = tempreg;
11683 tempreg = treg;
11684 ep = &expr1;
11685 }
11686 else if (!ust && treg == breg)
8fc2e39e
TS
11687 {
11688 used_at = 1;
11689 tempreg = AT;
11690 }
252b5132 11691 else
df58fc94 11692 tempreg = treg;
af22f5b2 11693
df58fc94
RS
11694 if (off == 1)
11695 goto ulh_sh;
252b5132 11696
90ecf173 11697 if (!target_big_endian)
df58fc94 11698 ep->X_add_number += off;
f2ae14a1 11699 if (offbits == 12)
c8276761 11700 macro_build (NULL, s, "t,~(b)", tempreg, (int) ep->X_add_number, breg);
f2ae14a1
RS
11701 else
11702 macro_build (ep, s, "t,o(b)", tempreg, -1,
11703 offset_reloc[0], offset_reloc[1], offset_reloc[2], breg);
df58fc94 11704
90ecf173 11705 if (!target_big_endian)
df58fc94 11706 ep->X_add_number -= off;
252b5132 11707 else
df58fc94 11708 ep->X_add_number += off;
f2ae14a1 11709 if (offbits == 12)
df58fc94 11710 macro_build (NULL, s2, "t,~(b)",
c8276761 11711 tempreg, (int) ep->X_add_number, breg);
f2ae14a1
RS
11712 else
11713 macro_build (ep, s2, "t,o(b)", tempreg, -1,
11714 offset_reloc[0], offset_reloc[1], offset_reloc[2], breg);
252b5132 11715
df58fc94
RS
11716 /* If necessary, move the result in tempreg to the final destination. */
11717 if (!ust && treg != tempreg)
11718 {
11719 /* Protect second load's delay slot. */
11720 load_delay_nop ();
11721 move_register (treg, tempreg);
11722 }
8fc2e39e 11723 break;
252b5132 11724
df58fc94 11725 ulh_sh:
d6bc6245 11726 used_at = 1;
df58fc94
RS
11727 if (target_big_endian == ust)
11728 ep->X_add_number += off;
f2ae14a1
RS
11729 tempreg = ust || large_offset ? treg : AT;
11730 macro_build (ep, s, "t,o(b)", tempreg, -1,
11731 offset_reloc[0], offset_reloc[1], offset_reloc[2], breg);
df58fc94
RS
11732
11733 /* For halfword transfers we need a temporary register to shuffle
11734 bytes. Unfortunately for M_USH_A we have none available before
11735 the next store as AT holds the base address. We deal with this
11736 case by clobbering TREG and then restoring it as with ULH. */
f2ae14a1 11737 tempreg = ust == large_offset ? treg : AT;
df58fc94
RS
11738 if (ust)
11739 macro_build (NULL, "srl", SHFT_FMT, tempreg, treg, 8);
11740
11741 if (target_big_endian == ust)
11742 ep->X_add_number -= off;
252b5132 11743 else
df58fc94 11744 ep->X_add_number += off;
f2ae14a1
RS
11745 macro_build (ep, s2, "t,o(b)", tempreg, -1,
11746 offset_reloc[0], offset_reloc[1], offset_reloc[2], breg);
252b5132 11747
df58fc94 11748 /* For M_USH_A re-retrieve the LSB. */
f2ae14a1 11749 if (ust && large_offset)
df58fc94
RS
11750 {
11751 if (target_big_endian)
11752 ep->X_add_number += off;
11753 else
11754 ep->X_add_number -= off;
f2ae14a1
RS
11755 macro_build (&expr1, "lbu", "t,o(b)", AT, -1,
11756 offset_reloc[0], offset_reloc[1], offset_reloc[2], AT);
df58fc94
RS
11757 }
11758 /* For ULH and M_USH_A OR the LSB in. */
f2ae14a1 11759 if (!ust || large_offset)
df58fc94 11760 {
f2ae14a1 11761 tempreg = !large_offset ? AT : treg;
df58fc94
RS
11762 macro_build (NULL, "sll", SHFT_FMT, tempreg, tempreg, 8);
11763 macro_build (NULL, "or", "d,v,t", treg, treg, AT);
11764 }
252b5132
RH
11765 break;
11766
11767 default:
11768 /* FIXME: Check if this is one of the itbl macros, since they
bdaaa2e1 11769 are added dynamically. */
252b5132
RH
11770 as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name);
11771 break;
11772 }
741fe287 11773 if (!mips_opts.at && used_at)
8fc2e39e 11774 as_bad (_("Macro used $at after \".set noat\""));
252b5132
RH
11775}
11776
11777/* Implement macros in mips16 mode. */
11778
11779static void
17a2f251 11780mips16_macro (struct mips_cl_insn *ip)
252b5132
RH
11781{
11782 int mask;
11783 int xreg, yreg, zreg, tmp;
252b5132
RH
11784 expressionS expr1;
11785 int dbl;
11786 const char *s, *s2, *s3;
11787
11788 mask = ip->insn_mo->mask;
11789
bf12938e
RS
11790 xreg = MIPS16_EXTRACT_OPERAND (RX, *ip);
11791 yreg = MIPS16_EXTRACT_OPERAND (RY, *ip);
11792 zreg = MIPS16_EXTRACT_OPERAND (RZ, *ip);
252b5132 11793
252b5132
RH
11794 expr1.X_op = O_constant;
11795 expr1.X_op_symbol = NULL;
11796 expr1.X_add_symbol = NULL;
11797 expr1.X_add_number = 1;
11798
11799 dbl = 0;
11800
11801 switch (mask)
11802 {
11803 default:
b37df7c4 11804 abort ();
252b5132
RH
11805
11806 case M_DDIV_3:
11807 dbl = 1;
11808 case M_DIV_3:
11809 s = "mflo";
11810 goto do_div3;
11811 case M_DREM_3:
11812 dbl = 1;
11813 case M_REM_3:
11814 s = "mfhi";
11815 do_div3:
7d10b47d 11816 start_noreorder ();
67c0d1eb 11817 macro_build (NULL, dbl ? "ddiv" : "div", "0,x,y", xreg, yreg);
252b5132 11818 expr1.X_add_number = 2;
67c0d1eb
RS
11819 macro_build (&expr1, "bnez", "x,p", yreg);
11820 macro_build (NULL, "break", "6", 7);
bdaaa2e1 11821
252b5132
RH
11822 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
11823 since that causes an overflow. We should do that as well,
11824 but I don't see how to do the comparisons without a temporary
11825 register. */
7d10b47d 11826 end_noreorder ();
67c0d1eb 11827 macro_build (NULL, s, "x", zreg);
252b5132
RH
11828 break;
11829
11830 case M_DIVU_3:
11831 s = "divu";
11832 s2 = "mflo";
11833 goto do_divu3;
11834 case M_REMU_3:
11835 s = "divu";
11836 s2 = "mfhi";
11837 goto do_divu3;
11838 case M_DDIVU_3:
11839 s = "ddivu";
11840 s2 = "mflo";
11841 goto do_divu3;
11842 case M_DREMU_3:
11843 s = "ddivu";
11844 s2 = "mfhi";
11845 do_divu3:
7d10b47d 11846 start_noreorder ();
67c0d1eb 11847 macro_build (NULL, s, "0,x,y", xreg, yreg);
252b5132 11848 expr1.X_add_number = 2;
67c0d1eb
RS
11849 macro_build (&expr1, "bnez", "x,p", yreg);
11850 macro_build (NULL, "break", "6", 7);
7d10b47d 11851 end_noreorder ();
67c0d1eb 11852 macro_build (NULL, s2, "x", zreg);
252b5132
RH
11853 break;
11854
11855 case M_DMUL:
11856 dbl = 1;
11857 case M_MUL:
67c0d1eb
RS
11858 macro_build (NULL, dbl ? "dmultu" : "multu", "x,y", xreg, yreg);
11859 macro_build (NULL, "mflo", "x", zreg);
8fc2e39e 11860 break;
252b5132
RH
11861
11862 case M_DSUBU_I:
11863 dbl = 1;
11864 goto do_subu;
11865 case M_SUBU_I:
11866 do_subu:
11867 if (imm_expr.X_op != O_constant)
11868 as_bad (_("Unsupported large constant"));
11869 imm_expr.X_add_number = -imm_expr.X_add_number;
67c0d1eb 11870 macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "y,x,4", yreg, xreg);
252b5132
RH
11871 break;
11872
11873 case M_SUBU_I_2:
11874 if (imm_expr.X_op != O_constant)
11875 as_bad (_("Unsupported large constant"));
11876 imm_expr.X_add_number = -imm_expr.X_add_number;
67c0d1eb 11877 macro_build (&imm_expr, "addiu", "x,k", xreg);
252b5132
RH
11878 break;
11879
11880 case M_DSUBU_I_2:
11881 if (imm_expr.X_op != O_constant)
11882 as_bad (_("Unsupported large constant"));
11883 imm_expr.X_add_number = -imm_expr.X_add_number;
67c0d1eb 11884 macro_build (&imm_expr, "daddiu", "y,j", yreg);
252b5132
RH
11885 break;
11886
11887 case M_BEQ:
11888 s = "cmp";
11889 s2 = "bteqz";
11890 goto do_branch;
11891 case M_BNE:
11892 s = "cmp";
11893 s2 = "btnez";
11894 goto do_branch;
11895 case M_BLT:
11896 s = "slt";
11897 s2 = "btnez";
11898 goto do_branch;
11899 case M_BLTU:
11900 s = "sltu";
11901 s2 = "btnez";
11902 goto do_branch;
11903 case M_BLE:
11904 s = "slt";
11905 s2 = "bteqz";
11906 goto do_reverse_branch;
11907 case M_BLEU:
11908 s = "sltu";
11909 s2 = "bteqz";
11910 goto do_reverse_branch;
11911 case M_BGE:
11912 s = "slt";
11913 s2 = "bteqz";
11914 goto do_branch;
11915 case M_BGEU:
11916 s = "sltu";
11917 s2 = "bteqz";
11918 goto do_branch;
11919 case M_BGT:
11920 s = "slt";
11921 s2 = "btnez";
11922 goto do_reverse_branch;
11923 case M_BGTU:
11924 s = "sltu";
11925 s2 = "btnez";
11926
11927 do_reverse_branch:
11928 tmp = xreg;
11929 xreg = yreg;
11930 yreg = tmp;
11931
11932 do_branch:
67c0d1eb
RS
11933 macro_build (NULL, s, "x,y", xreg, yreg);
11934 macro_build (&offset_expr, s2, "p");
252b5132
RH
11935 break;
11936
11937 case M_BEQ_I:
11938 s = "cmpi";
11939 s2 = "bteqz";
11940 s3 = "x,U";
11941 goto do_branch_i;
11942 case M_BNE_I:
11943 s = "cmpi";
11944 s2 = "btnez";
11945 s3 = "x,U";
11946 goto do_branch_i;
11947 case M_BLT_I:
11948 s = "slti";
11949 s2 = "btnez";
11950 s3 = "x,8";
11951 goto do_branch_i;
11952 case M_BLTU_I:
11953 s = "sltiu";
11954 s2 = "btnez";
11955 s3 = "x,8";
11956 goto do_branch_i;
11957 case M_BLE_I:
11958 s = "slti";
11959 s2 = "btnez";
11960 s3 = "x,8";
11961 goto do_addone_branch_i;
11962 case M_BLEU_I:
11963 s = "sltiu";
11964 s2 = "btnez";
11965 s3 = "x,8";
11966 goto do_addone_branch_i;
11967 case M_BGE_I:
11968 s = "slti";
11969 s2 = "bteqz";
11970 s3 = "x,8";
11971 goto do_branch_i;
11972 case M_BGEU_I:
11973 s = "sltiu";
11974 s2 = "bteqz";
11975 s3 = "x,8";
11976 goto do_branch_i;
11977 case M_BGT_I:
11978 s = "slti";
11979 s2 = "bteqz";
11980 s3 = "x,8";
11981 goto do_addone_branch_i;
11982 case M_BGTU_I:
11983 s = "sltiu";
11984 s2 = "bteqz";
11985 s3 = "x,8";
11986
11987 do_addone_branch_i:
11988 if (imm_expr.X_op != O_constant)
11989 as_bad (_("Unsupported large constant"));
11990 ++imm_expr.X_add_number;
11991
11992 do_branch_i:
67c0d1eb
RS
11993 macro_build (&imm_expr, s, s3, xreg);
11994 macro_build (&offset_expr, s2, "p");
252b5132
RH
11995 break;
11996
11997 case M_ABS:
11998 expr1.X_add_number = 0;
67c0d1eb 11999 macro_build (&expr1, "slti", "x,8", yreg);
252b5132 12000 if (xreg != yreg)
67c0d1eb 12001 move_register (xreg, yreg);
252b5132 12002 expr1.X_add_number = 2;
67c0d1eb
RS
12003 macro_build (&expr1, "bteqz", "p");
12004 macro_build (NULL, "neg", "x,w", xreg, xreg);
252b5132
RH
12005 }
12006}
12007
77bd4346
RS
12008/* Assemble an instruction into its binary format. If the instruction
12009 is a macro, set imm_expr, imm2_expr and offset_expr to the values
12010 associated with "I", "+I" and "A" operands respectively. Otherwise
12011 store the value of the relocatable field (if any) in offset_expr.
12012 In both cases set offset_reloc to the relocation operators applied
12013 to offset_expr. */
252b5132
RH
12014
12015static void
17a2f251 12016mips_ip (char *str, struct mips_cl_insn *ip)
252b5132 12017{
df58fc94
RS
12018 bfd_boolean wrong_delay_slot_insns = FALSE;
12019 bfd_boolean need_delay_slot_ok = TRUE;
12020 struct mips_opcode *firstinsn = NULL;
12021 const struct mips_opcode *past;
12022 struct hash_control *hash;
252b5132 12023 const char *args;
43841e91 12024 char c = 0;
252b5132 12025 struct mips_opcode *insn;
df58fc94 12026 long opend;
a40bc9dd 12027 char *name;
df58fc94 12028 char *dot;
a92713e6 12029 char format;
a40bc9dd 12030 long end;
9e12b7a2
RS
12031 const struct mips_operand *operand;
12032 struct mips_arg_info arg;
a92713e6
RS
12033 struct mips_operand_token *tokens;
12034 bfd_boolean optional_reg;
252b5132
RH
12035
12036 insn_error = NULL;
12037
df58fc94
RS
12038 if (mips_opts.micromips)
12039 {
12040 hash = micromips_op_hash;
12041 past = &micromips_opcodes[bfd_micromips_num_opcodes];
12042 }
12043 else
12044 {
12045 hash = op_hash;
12046 past = &mips_opcodes[NUMOPCODES];
12047 }
12048 forced_insn_length = 0;
252b5132 12049 insn = NULL;
252b5132 12050
df58fc94 12051 /* We first try to match an instruction up to a space or to the end. */
a40bc9dd
RS
12052 for (end = 0; str[end] != '\0' && !ISSPACE (str[end]); end++)
12053 continue;
bdaaa2e1 12054
a40bc9dd
RS
12055 /* Make a copy of the instruction so that we can fiddle with it. */
12056 name = alloca (end + 1);
12057 memcpy (name, str, end);
12058 name[end] = '\0';
252b5132 12059
df58fc94
RS
12060 for (;;)
12061 {
12062 insn = (struct mips_opcode *) hash_find (hash, name);
12063
12064 if (insn != NULL || !mips_opts.micromips)
12065 break;
12066 if (forced_insn_length)
12067 break;
12068
12069 /* See if there's an instruction size override suffix,
12070 either `16' or `32', at the end of the mnemonic proper,
12071 that defines the operation, i.e. before the first `.'
12072 character if any. Strip it and retry. */
12073 dot = strchr (name, '.');
12074 opend = dot != NULL ? dot - name : end;
12075 if (opend < 3)
12076 break;
12077 if (name[opend - 2] == '1' && name[opend - 1] == '6')
12078 forced_insn_length = 2;
12079 else if (name[opend - 2] == '3' && name[opend - 1] == '2')
12080 forced_insn_length = 4;
12081 else
12082 break;
12083 memcpy (name + opend - 2, name + opend, end - opend + 1);
12084 }
252b5132
RH
12085 if (insn == NULL)
12086 {
a40bc9dd
RS
12087 insn_error = _("Unrecognized opcode");
12088 return;
252b5132
RH
12089 }
12090
a92713e6
RS
12091 if (strcmp (name, "li.s") == 0)
12092 format = 'f';
12093 else if (strcmp (name, "li.d") == 0)
12094 format = 'd';
12095 else
12096 format = 0;
12097 tokens = mips_parse_arguments (str + end, format);
12098 if (!tokens)
12099 return;
12100
df58fc94
RS
12101 /* For microMIPS instructions placed in a fixed-length branch delay slot
12102 we make up to two passes over the relevant fragment of the opcode
12103 table. First we try instructions that meet the delay slot's length
12104 requirement. If none matched, then we retry with the remaining ones
12105 and if one matches, then we use it and then issue an appropriate
12106 warning later on. */
252b5132
RH
12107 for (;;)
12108 {
df58fc94
RS
12109 bfd_boolean delay_slot_ok;
12110 bfd_boolean size_ok;
b34976b6 12111 bfd_boolean ok;
9e12b7a2 12112 bfd_boolean more_alts;
252b5132 12113
a40bc9dd 12114 gas_assert (strcmp (insn->name, name) == 0);
252b5132 12115
f79e2745 12116 ok = is_opcode_valid (insn);
df58fc94
RS
12117 size_ok = is_size_valid (insn);
12118 delay_slot_ok = is_delay_slot_valid (insn);
12119 if (!delay_slot_ok && !wrong_delay_slot_insns)
252b5132 12120 {
df58fc94
RS
12121 firstinsn = insn;
12122 wrong_delay_slot_insns = TRUE;
12123 }
9e12b7a2
RS
12124 more_alts = (insn + 1 < past
12125 && strcmp (insn[0].name, insn[1].name) == 0);
df58fc94
RS
12126 if (!ok || !size_ok || delay_slot_ok != need_delay_slot_ok)
12127 {
12128 static char buf[256];
12129
9e12b7a2 12130 if (more_alts)
252b5132
RH
12131 {
12132 ++insn;
12133 continue;
12134 }
df58fc94 12135 if (wrong_delay_slot_insns && need_delay_slot_ok)
beae10d5 12136 {
df58fc94
RS
12137 gas_assert (firstinsn);
12138 need_delay_slot_ok = FALSE;
12139 past = insn + 1;
12140 insn = firstinsn;
12141 continue;
252b5132 12142 }
df58fc94 12143
a92713e6 12144 obstack_free (&mips_operand_tokens, tokens);
df58fc94
RS
12145 if (insn_error)
12146 return;
12147
12148 if (!ok)
7bd942df 12149 sprintf (buf, _("Opcode not supported on this processor: %s (%s)"),
df58fc94
RS
12150 mips_cpu_info_from_arch (mips_opts.arch)->name,
12151 mips_cpu_info_from_isa (mips_opts.isa)->name);
833794fc
MR
12152 else if (mips_opts.insn32)
12153 sprintf (buf, _("Opcode not supported in the `insn32' mode"));
df58fc94
RS
12154 else
12155 sprintf (buf, _("Unrecognized %u-bit version of microMIPS opcode"),
12156 8 * forced_insn_length);
12157 insn_error = buf;
12158
12159 return;
252b5132
RH
12160 }
12161
f2ae14a1
RS
12162 imm_expr.X_op = O_absent;
12163 imm2_expr.X_op = O_absent;
12164 offset_expr.X_op = O_absent;
f2ae14a1
RS
12165 offset_reloc[0] = BFD_RELOC_UNUSED;
12166 offset_reloc[1] = BFD_RELOC_UNUSED;
12167 offset_reloc[2] = BFD_RELOC_UNUSED;
12168
1e915849 12169 create_insn (ip, insn);
268f6bed 12170 insn_error = NULL;
9e12b7a2
RS
12171 memset (&arg, 0, sizeof (arg));
12172 arg.insn = ip;
a92713e6 12173 arg.token = tokens;
9e12b7a2
RS
12174 arg.argnum = 1;
12175 arg.last_regno = ILLEGAL_REG;
12176 arg.dest_regno = ILLEGAL_REG;
12177 arg.soft_match = (more_alts
12178 || (wrong_delay_slot_insns && need_delay_slot_ok));
252b5132
RH
12179 for (args = insn->args;; ++args)
12180 {
a92713e6 12181 if (arg.token->type == OT_END)
252b5132 12182 {
9e12b7a2
RS
12183 /* Handle unary instructions in which only one operand is given.
12184 The source is then the same as the destination. */
12185 if (arg.opnum == 1 && *args == ',')
12186 switch (args[1])
12187 {
12188 case 'r':
12189 case 'v':
12190 case 'w':
12191 case 'W':
12192 case 'V':
a92713e6 12193 arg.token = tokens;
9e12b7a2 12194 arg.argnum = 1;
9e12b7a2
RS
12195 continue;
12196 }
74cd071d 12197
9e12b7a2
RS
12198 /* Treat elided base registers as $0. */
12199 if (strcmp (args, "(b)") == 0)
12200 args += 3;
74cd071d 12201
9e12b7a2
RS
12202 /* Fail the match if there were too few operands. */
12203 if (*args)
12204 break;
74cd071d 12205
9e12b7a2
RS
12206 /* Successful match. */
12207 if (arg.dest_regno == arg.last_regno
12208 && strncmp (ip->insn_mo->name, "jalr", 4) == 0)
74cd071d 12209 {
9e12b7a2
RS
12210 if (arg.opnum == 2)
12211 as_bad (_("Source and destination must be different"));
12212 else if (arg.last_regno == 31)
12213 as_bad (_("A destination register must be supplied"));
74cd071d 12214 }
9e12b7a2 12215 check_completed_insn (&arg);
a92713e6 12216 obstack_free (&mips_operand_tokens, tokens);
9e12b7a2
RS
12217 return;
12218 }
74cd071d 12219
9e12b7a2
RS
12220 /* Fail the match if the line has too many operands. */
12221 if (*args == 0)
12222 break;
12223
12224 /* Handle characters that need to match exactly. */
12225 if (*args == '(' || *args == ')' || *args == ',')
12226 {
a92713e6
RS
12227 if (match_char (&arg, *args))
12228 continue;
12229 break;
9e12b7a2 12230 }
74cd071d 12231
9e12b7a2
RS
12232 /* Handle special macro operands. Work out the properties of
12233 other operands. */
12234 arg.opnum += 1;
9e12b7a2 12235 arg.lax_max = FALSE;
a92713e6 12236 optional_reg = FALSE;
9e12b7a2
RS
12237 switch (*args)
12238 {
12239 case '+':
12240 switch (args[1])
74cd071d 12241 {
9e12b7a2
RS
12242 case '1':
12243 case '2':
12244 case '3':
12245 case '4':
12246 case 'B':
12247 case 'C':
12248 case 'F':
12249 case 'G':
12250 case 'H':
12251 case 'J':
12252 case 'Q':
12253 case 'S':
12254 case 's':
12255 /* If these integer forms come last, there is no other
12256 form of the instruction that could match. Prefer to
12257 give detailed error messages where possible. */
12258 if (args[2] == 0)
12259 arg.soft_match = FALSE;
12260 break;
12261
12262 case 'I':
12263 /* "+I" is like "I", except that imm2_expr is used. */
a92713e6
RS
12264 if (match_const_int (&arg, &imm2_expr.X_add_number, 0))
12265 imm2_expr.X_op = O_constant;
12266 else
12267 insn_error = _("absolute expression required");
9e12b7a2
RS
12268 if (HAVE_32BIT_GPRS)
12269 normalize_constant_expr (&imm2_expr);
9e12b7a2 12270 ++args;
74cd071d 12271 continue;
9e12b7a2
RS
12272
12273 case 'i':
12274 *offset_reloc = BFD_RELOC_MIPS_JMP;
12275 break;
74cd071d 12276 }
74cd071d
CF
12277 break;
12278
9e12b7a2
RS
12279 case '\'':
12280 case ':':
12281 case '@':
12282 case '^':
12283 case '$':
12284 case '\\':
12285 case '%':
12286 case '|':
03f66e8a 12287 case '0':
9e12b7a2
RS
12288 case '1':
12289 case '2':
12290 case '3':
12291 case '4':
12292 case '5':
12293 case '6':
12294 case '8':
12295 case 'B':
12296 case 'C':
12297 case 'J':
12298 case 'O':
12299 case 'P':
12300 case 'Q':
12301 case 'c':
12302 case 'h':
12303 case 'q':
12304 /* If these integer forms come last, there is no other
12305 form of the instruction that could match. Prefer to
12306 give detailed error messages where possible. */
12307 if (args[1] == 0)
12308 arg.soft_match = FALSE;
12309 break;
74cd071d 12310
9e12b7a2
RS
12311 case 'r':
12312 case 'v':
12313 case 'w':
12314 case 'W':
12315 case 'V':
12316 /* We have already matched a comma by this point, so the register
12317 is only optional if there is another operand to come. */
12318 gas_assert (arg.opnum == 2);
a92713e6 12319 optional_reg = (args[1] == ',');
9e12b7a2 12320 break;
ef2e4d86 12321
9e12b7a2 12322 case 'I':
a92713e6
RS
12323 if (match_const_int (&arg, &imm_expr.X_add_number, 0))
12324 imm_expr.X_op = O_constant;
12325 else
9e12b7a2
RS
12326 insn_error = _("absolute expression required");
12327 if (HAVE_32BIT_GPRS)
12328 normalize_constant_expr (&imm_expr);
ef2e4d86
CF
12329 continue;
12330
9e12b7a2 12331 case 'A':
a92713e6 12332 if (arg.token->type == OT_CHAR && arg.token->u.ch == '(')
ef2e4d86 12333 {
9e12b7a2
RS
12334 /* Assume that the offset has been elided and that what
12335 we saw was a base register. The match will fail later
12336 if that assumption turns out to be wrong. */
12337 offset_expr.X_op = O_constant;
12338 offset_expr.X_add_number = 0;
ef2e4d86 12339 }
a92713e6
RS
12340 else if (match_expression (&arg, &offset_expr, offset_reloc))
12341 normalize_address_expr (&offset_expr);
ef2e4d86 12342 else
a92713e6 12343 insn_error = _("absolute expression required");
9e12b7a2 12344 continue;
ef2e4d86 12345
9e12b7a2 12346 case 'F':
a92713e6
RS
12347 if (!match_float_constant (&arg, &imm_expr, &offset_expr,
12348 8, TRUE))
12349 insn_error = _("floating-point expression required");
89565f1b
RS
12350 continue;
12351
9e12b7a2 12352 case 'L':
a92713e6
RS
12353 if (!match_float_constant (&arg, &imm_expr, &offset_expr,
12354 8, FALSE))
12355 insn_error = _("floating-point expression required");
89565f1b 12356 continue;
90ecf173 12357
89565f1b 12358 case 'f':
a92713e6
RS
12359 if (!match_float_constant (&arg, &imm_expr, &offset_expr,
12360 4, TRUE))
12361 insn_error = _("floating-point expression required");
89565f1b 12362 continue;
b015e599 12363
89565f1b 12364 case 'l':
a92713e6
RS
12365 if (!match_float_constant (&arg, &imm_expr, &offset_expr,
12366 4, FALSE))
12367 insn_error = _("floating-point expression required");
9e12b7a2 12368 continue;
252b5132 12369
9e12b7a2
RS
12370 /* ??? This is the traditional behavior, but is flaky if
12371 there are alternative versions of the same instruction
12372 for different subarchitectures. The next alternative
12373 might not be suitable. */
12374 case 'j':
12375 /* For compatibility with older assemblers, we accept
12376 0x8000-0xffff as signed 16-bit numbers when only
12377 signed numbers are allowed. */
12378 arg.lax_max = !more_alts;
12379 case 'i':
12380 /* Only accept non-constant operands if this is the
12381 final alternative. Later alternatives might include
12382 a macro implementation. */
12383 arg.allow_nonconst = !more_alts;
12384 break;
252b5132 12385
9e12b7a2
RS
12386 case 'u':
12387 /* There are no macro implementations for out-of-range values. */
12388 arg.allow_nonconst = TRUE;
12389 break;
60b63b72 12390
9e12b7a2
RS
12391 case 'o':
12392 /* There should always be a macro implementation. */
12393 arg.allow_nonconst = FALSE;
12394 break;
df58fc94 12395
9e12b7a2
RS
12396 case 'p':
12397 *offset_reloc = BFD_RELOC_16_PCREL_S2;
12398 break;
df58fc94 12399
9e12b7a2
RS
12400 case 'a':
12401 *offset_reloc = BFD_RELOC_MIPS_JMP;
df58fc94 12402 break;
60b63b72 12403
9e12b7a2 12404 case 'm':
df58fc94 12405 gas_assert (mips_opts.micromips);
9e12b7a2
RS
12406 c = args[1];
12407 switch (c)
12408 {
12409 case 't':
12410 case 'c':
12411 case 'e':
12412 /* We have already matched a comma by this point,
12413 so the register is only optional if there is another
12414 operand to come. */
12415 gas_assert (arg.opnum == 2);
a92713e6 12416 optional_reg = (args[2] == ',');
df58fc94
RS
12417 break;
12418
9e12b7a2
RS
12419 case 'D':
12420 case 'E':
12421 if (!forced_insn_length)
12422 *offset_reloc = (int) BFD_RELOC_UNUSED + c;
12423 else if (c == 'D')
12424 *offset_reloc = BFD_RELOC_MICROMIPS_10_PCREL_S1;
12425 else
12426 *offset_reloc = BFD_RELOC_MICROMIPS_7_PCREL_S1;
df58fc94 12427 break;
9e12b7a2
RS
12428 }
12429 break;
12430 }
df58fc94 12431
9e12b7a2
RS
12432 operand = (mips_opts.micromips
12433 ? decode_micromips_operand (args)
12434 : decode_mips_operand (args));
12435 if (!operand)
12436 abort ();
df58fc94 12437
a92713e6
RS
12438 if (optional_reg
12439 && (arg.token[0].type != OT_REG
12440 || arg.token[1].type == OT_END))
9e12b7a2
RS
12441 {
12442 /* Assume that the register has been elided and is the
12443 same as the first operand. */
a92713e6 12444 arg.token = tokens;
9e12b7a2 12445 arg.argnum = 1;
9e12b7a2 12446 }
a92713e6
RS
12447
12448 if (!match_operand (&arg, operand))
9e12b7a2 12449 break;
60b63b72 12450
9e12b7a2
RS
12451 /* Skip prefixes. */
12452 if (*args == '+' || *args == 'm')
12453 args++;
60b63b72 12454
9e12b7a2 12455 continue;
252b5132
RH
12456 }
12457 /* Args don't match. */
df58fc94 12458 insn_error = _("Illegal operands");
9e12b7a2 12459 if (more_alts)
252b5132
RH
12460 {
12461 ++insn;
252b5132
RH
12462 continue;
12463 }
9e12b7a2 12464 if (wrong_delay_slot_insns && need_delay_slot_ok)
df58fc94
RS
12465 {
12466 gas_assert (firstinsn);
12467 need_delay_slot_ok = FALSE;
12468 past = insn + 1;
12469 insn = firstinsn;
12470 continue;
12471 }
a92713e6 12472 obstack_free (&mips_operand_tokens, tokens);
252b5132
RH
12473 return;
12474 }
12475}
12476
77bd4346
RS
12477/* As for mips_ip, but used when assembling MIPS16 code.
12478 Also set forced_insn_length to the resulting instruction size in
12479 bytes if the user explicitly requested a small or extended instruction. */
252b5132
RH
12480
12481static void
17a2f251 12482mips16_ip (char *str, struct mips_cl_insn *ip)
252b5132
RH
12483{
12484 char *s;
12485 const char *args;
12486 struct mips_opcode *insn;
364215c8
RS
12487 const struct mips_operand *operand;
12488 const struct mips_operand *ext_operand;
12489 struct mips_arg_info arg;
a92713e6
RS
12490 struct mips_operand_token *tokens;
12491 bfd_boolean optional_reg;
252b5132
RH
12492
12493 insn_error = NULL;
12494
df58fc94 12495 forced_insn_length = 0;
252b5132 12496
3882b010 12497 for (s = str; ISLOWER (*s); ++s)
252b5132
RH
12498 ;
12499 switch (*s)
12500 {
12501 case '\0':
12502 break;
12503
12504 case ' ':
12505 *s++ = '\0';
12506 break;
12507
12508 case '.':
12509 if (s[1] == 't' && s[2] == ' ')
12510 {
12511 *s = '\0';
df58fc94 12512 forced_insn_length = 2;
252b5132
RH
12513 s += 3;
12514 break;
12515 }
12516 else if (s[1] == 'e' && s[2] == ' ')
12517 {
12518 *s = '\0';
df58fc94 12519 forced_insn_length = 4;
252b5132
RH
12520 s += 3;
12521 break;
12522 }
12523 /* Fall through. */
12524 default:
12525 insn_error = _("unknown opcode");
12526 return;
12527 }
12528
df58fc94
RS
12529 if (mips_opts.noautoextend && !forced_insn_length)
12530 forced_insn_length = 2;
252b5132
RH
12531
12532 if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL)
12533 {
12534 insn_error = _("unrecognized opcode");
12535 return;
12536 }
12537
a92713e6
RS
12538 tokens = mips_parse_arguments (s, 0);
12539 if (!tokens)
12540 return;
12541
252b5132
RH
12542 for (;;)
12543 {
9b3f89ee 12544 bfd_boolean ok;
364215c8 12545 bfd_boolean more_alts;
77bd4346 12546 char relax_char;
9b3f89ee 12547
9c2799c2 12548 gas_assert (strcmp (insn->name, str) == 0);
252b5132 12549
037b32b9 12550 ok = is_opcode_valid_16 (insn);
364215c8
RS
12551 more_alts = (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes]
12552 && strcmp (insn[0].name, insn[1].name) == 0);
9b3f89ee
TS
12553 if (! ok)
12554 {
364215c8 12555 if (more_alts)
9b3f89ee
TS
12556 {
12557 ++insn;
12558 continue;
12559 }
12560 else
12561 {
12562 if (!insn_error)
12563 {
12564 static char buf[100];
12565 sprintf (buf,
7bd942df 12566 _("Opcode not supported on this processor: %s (%s)"),
9b3f89ee
TS
12567 mips_cpu_info_from_arch (mips_opts.arch)->name,
12568 mips_cpu_info_from_isa (mips_opts.isa)->name);
12569 insn_error = buf;
12570 }
a92713e6 12571 obstack_free (&mips_operand_tokens, tokens);
9b3f89ee
TS
12572 return;
12573 }
12574 }
12575
1e915849 12576 create_insn (ip, insn);
252b5132 12577 imm_expr.X_op = O_absent;
5f74bc13 12578 imm2_expr.X_op = O_absent;
252b5132 12579 offset_expr.X_op = O_absent;
f6688943
TS
12580 offset_reloc[0] = BFD_RELOC_UNUSED;
12581 offset_reloc[1] = BFD_RELOC_UNUSED;
12582 offset_reloc[2] = BFD_RELOC_UNUSED;
77bd4346 12583 relax_char = 0;
364215c8
RS
12584
12585 memset (&arg, 0, sizeof (arg));
12586 arg.insn = ip;
a92713e6 12587 arg.token = tokens;
364215c8
RS
12588 arg.argnum = 1;
12589 arg.last_regno = ILLEGAL_REG;
12590 arg.dest_regno = ILLEGAL_REG;
12591 arg.soft_match = more_alts;
12592 relax_char = 0;
252b5132
RH
12593 for (args = insn->args; 1; ++args)
12594 {
12595 int c;
12596
a92713e6 12597 if (arg.token->type == OT_END)
252b5132 12598 {
364215c8 12599 offsetT value;
252b5132 12600
364215c8
RS
12601 /* Handle unary instructions in which only one operand is given.
12602 The source is then the same as the destination. */
12603 if (arg.opnum == 1 && *args == ',')
12604 switch (args[1])
12605 {
12606 case 'v':
12607 case 'w':
a92713e6 12608 arg.token = tokens;
364215c8 12609 arg.argnum = 1;
364215c8
RS
12610 continue;
12611 }
252b5132 12612
364215c8
RS
12613 /* Fail the match if there were too few operands. */
12614 if (*args)
12615 break;
252b5132 12616
364215c8
RS
12617 /* Successful match. Stuff the immediate value in now, if
12618 we can. */
12619 if (insn->pinfo == INSN_MACRO)
252b5132 12620 {
364215c8
RS
12621 gas_assert (relax_char == 0);
12622 gas_assert (*offset_reloc == BFD_RELOC_UNUSED);
252b5132 12623 }
364215c8
RS
12624 else if (relax_char
12625 && offset_expr.X_op == O_constant
12626 && calculate_reloc (*offset_reloc,
12627 offset_expr.X_add_number,
12628 &value))
252b5132 12629 {
364215c8
RS
12630 mips16_immed (NULL, 0, relax_char, *offset_reloc, value,
12631 forced_insn_length, &ip->insn_opcode);
12632 offset_expr.X_op = O_absent;
12633 *offset_reloc = BFD_RELOC_UNUSED;
252b5132 12634 }
364215c8 12635 else if (relax_char && *offset_reloc != BFD_RELOC_UNUSED)
252b5132 12636 {
364215c8
RS
12637 if (forced_insn_length == 2)
12638 as_bad (_("invalid unextended operand value"));
12639 forced_insn_length = 4;
12640 ip->insn_opcode |= MIPS16_EXTEND;
252b5132 12641 }
364215c8
RS
12642 else if (relax_char)
12643 *offset_reloc = (int) BFD_RELOC_UNUSED + relax_char;
252b5132 12644
364215c8 12645 check_completed_insn (&arg);
a92713e6 12646 obstack_free (&mips_operand_tokens, tokens);
364215c8
RS
12647 return;
12648 }
252b5132 12649
364215c8
RS
12650 /* Fail the match if the line has too many operands. */
12651 if (*args == 0)
12652 break;
252b5132 12653
364215c8
RS
12654 /* Handle characters that need to match exactly. */
12655 if (*args == '(' || *args == ')' || *args == ',')
12656 {
a92713e6
RS
12657 if (match_char (&arg, *args))
12658 continue;
12659 break;
364215c8 12660 }
252b5132 12661
364215c8 12662 arg.opnum += 1;
a92713e6 12663 optional_reg = FALSE;
364215c8
RS
12664 c = *args;
12665 switch (c)
12666 {
12667 case 'v':
12668 case 'w':
a92713e6 12669 optional_reg = (args[1] == ',');
252b5132
RH
12670 break;
12671
252b5132
RH
12672 case 'p':
12673 case 'q':
12674 case 'A':
12675 case 'B':
12676 case 'E':
77bd4346 12677 relax_char = c;
364215c8 12678 break;
252b5132 12679
cc537e56 12680 case 'I':
a92713e6
RS
12681 if (match_const_int (&arg, &imm_expr.X_add_number, 0))
12682 imm_expr.X_op = O_constant;
12683 else
cc537e56
RS
12684 insn_error = _("absolute expression required");
12685 if (HAVE_32BIT_GPRS)
12686 normalize_constant_expr (&imm_expr);
cc537e56
RS
12687 continue;
12688
364215c8 12689 case 'a':
27c5c572 12690 case 'i':
f6688943 12691 *offset_reloc = BFD_RELOC_MIPS16_JMP;
252b5132 12692 ip->insn_opcode <<= 16;
364215c8
RS
12693 break;
12694 }
0499d65b 12695
364215c8
RS
12696 operand = decode_mips16_operand (c, FALSE);
12697 if (!operand)
12698 abort ();
0499d65b 12699
364215c8
RS
12700 /* '6' is a special case. It is used for BREAK and SDBBP,
12701 whose operands are only meaningful to the software that decodes
12702 them. This means that there is no architectural reason why
12703 they cannot be prefixed by EXTEND, but in practice,
12704 exception handlers will only look at the instruction
12705 itself. We therefore allow '6' to be extended when
12706 disassembling but not when assembling. */
12707 if (operand->type != OP_PCREL && c != '6')
12708 {
12709 ext_operand = decode_mips16_operand (c, TRUE);
12710 if (operand != ext_operand)
252b5132 12711 {
a92713e6 12712 if (arg.token->type == OT_CHAR && arg.token->u.ch == '(')
364215c8 12713 {
a92713e6
RS
12714 offset_expr.X_op = O_constant;
12715 offset_expr.X_add_number = 0;
12716 relax_char = c;
12717 continue;
364215c8 12718 }
a92713e6
RS
12719
12720 /* We need the OT_INTEGER check because some MIPS16
12721 immediate variants are listed before the register ones. */
12722 if (arg.token->type != OT_INTEGER
12723 || !match_expression (&arg, &offset_expr, offset_reloc))
12724 break;
12725
364215c8
RS
12726 /* '8' is used for SLTI(U) and has traditionally not
12727 been allowed to take relocation operators. */
a92713e6
RS
12728 if (offset_reloc[0] != BFD_RELOC_UNUSED
12729 && (ext_operand->size != 16 || c == '8'))
364215c8 12730 break;
a92713e6 12731
364215c8
RS
12732 relax_char = c;
12733 continue;
252b5132 12734 }
364215c8 12735 }
252b5132 12736
a92713e6
RS
12737 if (optional_reg
12738 && (arg.token[0].type != OT_REG
12739 || arg.token[1].type == OT_END))
364215c8
RS
12740 {
12741 /* Assume that the register has been elided and is the
12742 same as the first operand. */
a92713e6 12743 arg.token = tokens;
364215c8 12744 arg.argnum = 1;
252b5132 12745 }
a92713e6
RS
12746
12747 if (!match_operand (&arg, operand))
364215c8
RS
12748 break;
12749 continue;
252b5132
RH
12750 }
12751
12752 /* Args don't match. */
364215c8 12753 if (more_alts)
252b5132
RH
12754 {
12755 ++insn;
252b5132
RH
12756 continue;
12757 }
12758
12759 insn_error = _("illegal operands");
12760
a92713e6 12761 obstack_free (&mips_operand_tokens, tokens);
252b5132
RH
12762 return;
12763 }
12764}
12765
12766/* This structure holds information we know about a mips16 immediate
12767 argument type. */
12768
e972090a
NC
12769struct mips16_immed_operand
12770{
252b5132
RH
12771 /* The type code used in the argument string in the opcode table. */
12772 int type;
12773 /* The number of bits in the short form of the opcode. */
12774 int nbits;
12775 /* The number of bits in the extended form of the opcode. */
12776 int extbits;
12777 /* The amount by which the short form is shifted when it is used;
12778 for example, the sw instruction has a shift count of 2. */
12779 int shift;
12780 /* The amount by which the short form is shifted when it is stored
12781 into the instruction code. */
12782 int op_shift;
12783 /* Non-zero if the short form is unsigned. */
12784 int unsp;
12785 /* Non-zero if the extended form is unsigned. */
12786 int extu;
12787 /* Non-zero if the value is PC relative. */
12788 int pcrel;
12789};
12790
12791/* The mips16 immediate operand types. */
12792
12793static const struct mips16_immed_operand mips16_immed_operands[] =
12794{
12795 { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 },
12796 { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 },
12797 { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 },
12798 { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 },
12799 { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 },
12800 { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 },
12801 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 },
12802 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 },
12803 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 },
12804 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 },
12805 { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 },
12806 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 },
12807 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 },
12808 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 },
12809 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 },
12810 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 },
12811 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 },
12812 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 },
12813 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 },
12814 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 },
12815 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 }
12816};
12817
12818#define MIPS16_NUM_IMMED \
12819 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
12820
b886a2ab
RS
12821/* Marshal immediate value VAL for an extended MIPS16 instruction.
12822 NBITS is the number of significant bits in VAL. */
12823
12824static unsigned long
12825mips16_immed_extend (offsetT val, unsigned int nbits)
12826{
12827 int extval;
12828 if (nbits == 16)
12829 {
12830 extval = ((val >> 11) & 0x1f) | (val & 0x7e0);
12831 val &= 0x1f;
12832 }
12833 else if (nbits == 15)
12834 {
12835 extval = ((val >> 11) & 0xf) | (val & 0x7f0);
12836 val &= 0xf;
12837 }
12838 else
12839 {
12840 extval = ((val & 0x1f) << 6) | (val & 0x20);
12841 val = 0;
12842 }
12843 return (extval << 16) | val;
12844}
12845
5c04167a
RS
12846/* Install immediate value VAL into MIPS16 instruction *INSN,
12847 extending it if necessary. The instruction in *INSN may
12848 already be extended.
12849
43c0598f
RS
12850 RELOC is the relocation that produced VAL, or BFD_RELOC_UNUSED
12851 if none. In the former case, VAL is a 16-bit number with no
12852 defined signedness.
12853
12854 TYPE is the type of the immediate field. USER_INSN_LENGTH
12855 is the length that the user requested, or 0 if none. */
252b5132
RH
12856
12857static void
43c0598f
RS
12858mips16_immed (char *file, unsigned int line, int type,
12859 bfd_reloc_code_real_type reloc, offsetT val,
5c04167a 12860 unsigned int user_insn_length, unsigned long *insn)
252b5132 12861{
3994f87e 12862 const struct mips16_immed_operand *op;
252b5132 12863 int mintiny, maxtiny;
252b5132
RH
12864
12865 op = mips16_immed_operands;
12866 while (op->type != type)
12867 {
12868 ++op;
9c2799c2 12869 gas_assert (op < mips16_immed_operands + MIPS16_NUM_IMMED);
252b5132
RH
12870 }
12871
12872 if (op->unsp)
12873 {
12874 if (type == '<' || type == '>' || type == '[' || type == ']')
12875 {
12876 mintiny = 1;
12877 maxtiny = 1 << op->nbits;
12878 }
12879 else
12880 {
12881 mintiny = 0;
12882 maxtiny = (1 << op->nbits) - 1;
12883 }
43c0598f
RS
12884 if (reloc != BFD_RELOC_UNUSED)
12885 val &= 0xffff;
252b5132
RH
12886 }
12887 else
12888 {
12889 mintiny = - (1 << (op->nbits - 1));
12890 maxtiny = (1 << (op->nbits - 1)) - 1;
43c0598f
RS
12891 if (reloc != BFD_RELOC_UNUSED)
12892 val = SEXT_16BIT (val);
252b5132
RH
12893 }
12894
12895 /* Branch offsets have an implicit 0 in the lowest bit. */
12896 if (type == 'p' || type == 'q')
12897 val /= 2;
12898
12899 if ((val & ((1 << op->shift) - 1)) != 0
12900 || val < (mintiny << op->shift)
12901 || val > (maxtiny << op->shift))
5c04167a
RS
12902 {
12903 /* We need an extended instruction. */
12904 if (user_insn_length == 2)
12905 as_bad_where (file, line, _("invalid unextended operand value"));
12906 else
12907 *insn |= MIPS16_EXTEND;
12908 }
12909 else if (user_insn_length == 4)
12910 {
12911 /* The operand doesn't force an unextended instruction to be extended.
12912 Warn if the user wanted an extended instruction anyway. */
12913 *insn |= MIPS16_EXTEND;
12914 as_warn_where (file, line,
12915 _("extended operand requested but not required"));
12916 }
252b5132 12917
5c04167a 12918 if (mips16_opcode_length (*insn) == 2)
252b5132
RH
12919 {
12920 int insnval;
12921
252b5132
RH
12922 insnval = ((val >> op->shift) & ((1 << op->nbits) - 1));
12923 insnval <<= op->op_shift;
12924 *insn |= insnval;
12925 }
12926 else
12927 {
12928 long minext, maxext;
252b5132 12929
43c0598f 12930 if (reloc == BFD_RELOC_UNUSED)
252b5132 12931 {
43c0598f
RS
12932 if (op->extu)
12933 {
12934 minext = 0;
12935 maxext = (1 << op->extbits) - 1;
12936 }
12937 else
12938 {
12939 minext = - (1 << (op->extbits - 1));
12940 maxext = (1 << (op->extbits - 1)) - 1;
12941 }
12942 if (val < minext || val > maxext)
12943 as_bad_where (file, line,
12944 _("operand value out of range for instruction"));
252b5132 12945 }
252b5132 12946
b886a2ab 12947 *insn |= mips16_immed_extend (val, op->extbits);
252b5132
RH
12948 }
12949}
12950\f
d6f16593 12951struct percent_op_match
ad8d3bb3 12952{
5e0116d5
RS
12953 const char *str;
12954 bfd_reloc_code_real_type reloc;
d6f16593
MR
12955};
12956
12957static const struct percent_op_match mips_percent_op[] =
ad8d3bb3 12958{
5e0116d5 12959 {"%lo", BFD_RELOC_LO16},
5e0116d5
RS
12960 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16},
12961 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16},
12962 {"%call16", BFD_RELOC_MIPS_CALL16},
12963 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP},
12964 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE},
12965 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST},
12966 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16},
12967 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16},
12968 {"%got", BFD_RELOC_MIPS_GOT16},
12969 {"%gp_rel", BFD_RELOC_GPREL16},
12970 {"%half", BFD_RELOC_16},
12971 {"%highest", BFD_RELOC_MIPS_HIGHEST},
12972 {"%higher", BFD_RELOC_MIPS_HIGHER},
12973 {"%neg", BFD_RELOC_MIPS_SUB},
3f98094e
DJ
12974 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD},
12975 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM},
12976 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16},
12977 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16},
12978 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16},
12979 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16},
12980 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL},
5e0116d5 12981 {"%hi", BFD_RELOC_HI16_S}
ad8d3bb3
TS
12982};
12983
d6f16593
MR
12984static const struct percent_op_match mips16_percent_op[] =
12985{
12986 {"%lo", BFD_RELOC_MIPS16_LO16},
12987 {"%gprel", BFD_RELOC_MIPS16_GPREL},
738e5348
RS
12988 {"%got", BFD_RELOC_MIPS16_GOT16},
12989 {"%call16", BFD_RELOC_MIPS16_CALL16},
d0f13682
CLT
12990 {"%hi", BFD_RELOC_MIPS16_HI16_S},
12991 {"%tlsgd", BFD_RELOC_MIPS16_TLS_GD},
12992 {"%tlsldm", BFD_RELOC_MIPS16_TLS_LDM},
12993 {"%dtprel_hi", BFD_RELOC_MIPS16_TLS_DTPREL_HI16},
12994 {"%dtprel_lo", BFD_RELOC_MIPS16_TLS_DTPREL_LO16},
12995 {"%tprel_hi", BFD_RELOC_MIPS16_TLS_TPREL_HI16},
12996 {"%tprel_lo", BFD_RELOC_MIPS16_TLS_TPREL_LO16},
12997 {"%gottprel", BFD_RELOC_MIPS16_TLS_GOTTPREL}
d6f16593
MR
12998};
12999
252b5132 13000
5e0116d5
RS
13001/* Return true if *STR points to a relocation operator. When returning true,
13002 move *STR over the operator and store its relocation code in *RELOC.
13003 Leave both *STR and *RELOC alone when returning false. */
13004
13005static bfd_boolean
17a2f251 13006parse_relocation (char **str, bfd_reloc_code_real_type *reloc)
252b5132 13007{
d6f16593
MR
13008 const struct percent_op_match *percent_op;
13009 size_t limit, i;
13010
13011 if (mips_opts.mips16)
13012 {
13013 percent_op = mips16_percent_op;
13014 limit = ARRAY_SIZE (mips16_percent_op);
13015 }
13016 else
13017 {
13018 percent_op = mips_percent_op;
13019 limit = ARRAY_SIZE (mips_percent_op);
13020 }
76b3015f 13021
d6f16593 13022 for (i = 0; i < limit; i++)
5e0116d5 13023 if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0)
394f9b3a 13024 {
3f98094e
DJ
13025 int len = strlen (percent_op[i].str);
13026
13027 if (!ISSPACE ((*str)[len]) && (*str)[len] != '(')
13028 continue;
13029
5e0116d5
RS
13030 *str += strlen (percent_op[i].str);
13031 *reloc = percent_op[i].reloc;
394f9b3a 13032
5e0116d5
RS
13033 /* Check whether the output BFD supports this relocation.
13034 If not, issue an error and fall back on something safe. */
13035 if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc))
394f9b3a 13036 {
20203fb9 13037 as_bad (_("relocation %s isn't supported by the current ABI"),
5e0116d5 13038 percent_op[i].str);
01a3f561 13039 *reloc = BFD_RELOC_UNUSED;
394f9b3a 13040 }
5e0116d5 13041 return TRUE;
394f9b3a 13042 }
5e0116d5 13043 return FALSE;
394f9b3a 13044}
ad8d3bb3 13045
ad8d3bb3 13046
5e0116d5
RS
13047/* Parse string STR as a 16-bit relocatable operand. Store the
13048 expression in *EP and the relocations in the array starting
13049 at RELOC. Return the number of relocation operators used.
ad8d3bb3 13050
01a3f561 13051 On exit, EXPR_END points to the first character after the expression. */
ad8d3bb3 13052
5e0116d5 13053static size_t
17a2f251
TS
13054my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc,
13055 char *str)
ad8d3bb3 13056{
5e0116d5
RS
13057 bfd_reloc_code_real_type reversed_reloc[3];
13058 size_t reloc_index, i;
09b8f35a
RS
13059 int crux_depth, str_depth;
13060 char *crux;
5e0116d5
RS
13061
13062 /* Search for the start of the main expression, recoding relocations
09b8f35a
RS
13063 in REVERSED_RELOC. End the loop with CRUX pointing to the start
13064 of the main expression and with CRUX_DEPTH containing the number
13065 of open brackets at that point. */
13066 reloc_index = -1;
13067 str_depth = 0;
13068 do
fb1b3232 13069 {
09b8f35a
RS
13070 reloc_index++;
13071 crux = str;
13072 crux_depth = str_depth;
13073
13074 /* Skip over whitespace and brackets, keeping count of the number
13075 of brackets. */
13076 while (*str == ' ' || *str == '\t' || *str == '(')
13077 if (*str++ == '(')
13078 str_depth++;
5e0116d5 13079 }
09b8f35a
RS
13080 while (*str == '%'
13081 && reloc_index < (HAVE_NEWABI ? 3 : 1)
13082 && parse_relocation (&str, &reversed_reloc[reloc_index]));
ad8d3bb3 13083
09b8f35a 13084 my_getExpression (ep, crux);
5e0116d5 13085 str = expr_end;
394f9b3a 13086
5e0116d5 13087 /* Match every open bracket. */
09b8f35a 13088 while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t'))
5e0116d5 13089 if (*str++ == ')')
09b8f35a 13090 crux_depth--;
394f9b3a 13091
09b8f35a 13092 if (crux_depth > 0)
20203fb9 13093 as_bad (_("unclosed '('"));
394f9b3a 13094
5e0116d5 13095 expr_end = str;
252b5132 13096
01a3f561 13097 if (reloc_index != 0)
64bdfcaf
RS
13098 {
13099 prev_reloc_op_frag = frag_now;
13100 for (i = 0; i < reloc_index; i++)
13101 reloc[i] = reversed_reloc[reloc_index - 1 - i];
13102 }
fb1b3232 13103
5e0116d5 13104 return reloc_index;
252b5132
RH
13105}
13106
13107static void
17a2f251 13108my_getExpression (expressionS *ep, char *str)
252b5132
RH
13109{
13110 char *save_in;
13111
13112 save_in = input_line_pointer;
13113 input_line_pointer = str;
13114 expression (ep);
13115 expr_end = input_line_pointer;
13116 input_line_pointer = save_in;
252b5132
RH
13117}
13118
252b5132 13119char *
17a2f251 13120md_atof (int type, char *litP, int *sizeP)
252b5132 13121{
499ac353 13122 return ieee_md_atof (type, litP, sizeP, target_big_endian);
252b5132
RH
13123}
13124
13125void
17a2f251 13126md_number_to_chars (char *buf, valueT val, int n)
252b5132
RH
13127{
13128 if (target_big_endian)
13129 number_to_chars_bigendian (buf, val, n);
13130 else
13131 number_to_chars_littleendian (buf, val, n);
13132}
13133\f
e013f690
TS
13134static int support_64bit_objects(void)
13135{
13136 const char **list, **l;
aa3d8fdf 13137 int yes;
e013f690
TS
13138
13139 list = bfd_target_list ();
13140 for (l = list; *l != NULL; l++)
aeffff67
RS
13141 if (strcmp (*l, ELF_TARGET ("elf64-", "big")) == 0
13142 || strcmp (*l, ELF_TARGET ("elf64-", "little")) == 0)
e013f690 13143 break;
aa3d8fdf 13144 yes = (*l != NULL);
e013f690 13145 free (list);
aa3d8fdf 13146 return yes;
e013f690
TS
13147}
13148
316f5878
RS
13149/* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
13150 NEW_VALUE. Warn if another value was already specified. Note:
13151 we have to defer parsing the -march and -mtune arguments in order
13152 to handle 'from-abi' correctly, since the ABI might be specified
13153 in a later argument. */
13154
13155static void
17a2f251 13156mips_set_option_string (const char **string_ptr, const char *new_value)
316f5878
RS
13157{
13158 if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0)
13159 as_warn (_("A different %s was already specified, is now %s"),
13160 string_ptr == &mips_arch_string ? "-march" : "-mtune",
13161 new_value);
13162
13163 *string_ptr = new_value;
13164}
13165
252b5132 13166int
17a2f251 13167md_parse_option (int c, char *arg)
252b5132 13168{
c6278170
RS
13169 unsigned int i;
13170
13171 for (i = 0; i < ARRAY_SIZE (mips_ases); i++)
13172 if (c == mips_ases[i].option_on || c == mips_ases[i].option_off)
13173 {
13174 file_ase_explicit |= mips_set_ase (&mips_ases[i],
13175 c == mips_ases[i].option_on);
13176 return 1;
13177 }
13178
252b5132
RH
13179 switch (c)
13180 {
119d663a
NC
13181 case OPTION_CONSTRUCT_FLOATS:
13182 mips_disable_float_construction = 0;
13183 break;
bdaaa2e1 13184
119d663a
NC
13185 case OPTION_NO_CONSTRUCT_FLOATS:
13186 mips_disable_float_construction = 1;
13187 break;
bdaaa2e1 13188
252b5132
RH
13189 case OPTION_TRAP:
13190 mips_trap = 1;
13191 break;
13192
13193 case OPTION_BREAK:
13194 mips_trap = 0;
13195 break;
13196
13197 case OPTION_EB:
13198 target_big_endian = 1;
13199 break;
13200
13201 case OPTION_EL:
13202 target_big_endian = 0;
13203 break;
13204
13205 case 'O':
4ffff32f
TS
13206 if (arg == NULL)
13207 mips_optimize = 1;
13208 else if (arg[0] == '0')
13209 mips_optimize = 0;
13210 else if (arg[0] == '1')
252b5132
RH
13211 mips_optimize = 1;
13212 else
13213 mips_optimize = 2;
13214 break;
13215
13216 case 'g':
13217 if (arg == NULL)
13218 mips_debug = 2;
13219 else
13220 mips_debug = atoi (arg);
252b5132
RH
13221 break;
13222
13223 case OPTION_MIPS1:
316f5878 13224 file_mips_isa = ISA_MIPS1;
252b5132
RH
13225 break;
13226
13227 case OPTION_MIPS2:
316f5878 13228 file_mips_isa = ISA_MIPS2;
252b5132
RH
13229 break;
13230
13231 case OPTION_MIPS3:
316f5878 13232 file_mips_isa = ISA_MIPS3;
252b5132
RH
13233 break;
13234
13235 case OPTION_MIPS4:
316f5878 13236 file_mips_isa = ISA_MIPS4;
e7af610e
NC
13237 break;
13238
84ea6cf2 13239 case OPTION_MIPS5:
316f5878 13240 file_mips_isa = ISA_MIPS5;
84ea6cf2
NC
13241 break;
13242
e7af610e 13243 case OPTION_MIPS32:
316f5878 13244 file_mips_isa = ISA_MIPS32;
252b5132
RH
13245 break;
13246
af7ee8bf
CD
13247 case OPTION_MIPS32R2:
13248 file_mips_isa = ISA_MIPS32R2;
13249 break;
13250
5f74bc13
CD
13251 case OPTION_MIPS64R2:
13252 file_mips_isa = ISA_MIPS64R2;
13253 break;
13254
84ea6cf2 13255 case OPTION_MIPS64:
316f5878 13256 file_mips_isa = ISA_MIPS64;
84ea6cf2
NC
13257 break;
13258
ec68c924 13259 case OPTION_MTUNE:
316f5878
RS
13260 mips_set_option_string (&mips_tune_string, arg);
13261 break;
ec68c924 13262
316f5878
RS
13263 case OPTION_MARCH:
13264 mips_set_option_string (&mips_arch_string, arg);
252b5132
RH
13265 break;
13266
13267 case OPTION_M4650:
316f5878
RS
13268 mips_set_option_string (&mips_arch_string, "4650");
13269 mips_set_option_string (&mips_tune_string, "4650");
252b5132
RH
13270 break;
13271
13272 case OPTION_NO_M4650:
13273 break;
13274
13275 case OPTION_M4010:
316f5878
RS
13276 mips_set_option_string (&mips_arch_string, "4010");
13277 mips_set_option_string (&mips_tune_string, "4010");
252b5132
RH
13278 break;
13279
13280 case OPTION_NO_M4010:
13281 break;
13282
13283 case OPTION_M4100:
316f5878
RS
13284 mips_set_option_string (&mips_arch_string, "4100");
13285 mips_set_option_string (&mips_tune_string, "4100");
252b5132
RH
13286 break;
13287
13288 case OPTION_NO_M4100:
13289 break;
13290
252b5132 13291 case OPTION_M3900:
316f5878
RS
13292 mips_set_option_string (&mips_arch_string, "3900");
13293 mips_set_option_string (&mips_tune_string, "3900");
252b5132 13294 break;
bdaaa2e1 13295
252b5132
RH
13296 case OPTION_NO_M3900:
13297 break;
13298
df58fc94
RS
13299 case OPTION_MICROMIPS:
13300 if (mips_opts.mips16 == 1)
13301 {
13302 as_bad (_("-mmicromips cannot be used with -mips16"));
13303 return 0;
13304 }
13305 mips_opts.micromips = 1;
13306 mips_no_prev_insn ();
13307 break;
13308
13309 case OPTION_NO_MICROMIPS:
13310 mips_opts.micromips = 0;
13311 mips_no_prev_insn ();
13312 break;
13313
252b5132 13314 case OPTION_MIPS16:
df58fc94
RS
13315 if (mips_opts.micromips == 1)
13316 {
13317 as_bad (_("-mips16 cannot be used with -micromips"));
13318 return 0;
13319 }
252b5132 13320 mips_opts.mips16 = 1;
7d10b47d 13321 mips_no_prev_insn ();
252b5132
RH
13322 break;
13323
13324 case OPTION_NO_MIPS16:
13325 mips_opts.mips16 = 0;
7d10b47d 13326 mips_no_prev_insn ();
252b5132
RH
13327 break;
13328
6a32d874
CM
13329 case OPTION_FIX_24K:
13330 mips_fix_24k = 1;
13331 break;
13332
13333 case OPTION_NO_FIX_24K:
13334 mips_fix_24k = 0;
13335 break;
13336
c67a084a
NC
13337 case OPTION_FIX_LOONGSON2F_JUMP:
13338 mips_fix_loongson2f_jump = TRUE;
13339 break;
13340
13341 case OPTION_NO_FIX_LOONGSON2F_JUMP:
13342 mips_fix_loongson2f_jump = FALSE;
13343 break;
13344
13345 case OPTION_FIX_LOONGSON2F_NOP:
13346 mips_fix_loongson2f_nop = TRUE;
13347 break;
13348
13349 case OPTION_NO_FIX_LOONGSON2F_NOP:
13350 mips_fix_loongson2f_nop = FALSE;
13351 break;
13352
d766e8ec
RS
13353 case OPTION_FIX_VR4120:
13354 mips_fix_vr4120 = 1;
60b63b72
RS
13355 break;
13356
d766e8ec
RS
13357 case OPTION_NO_FIX_VR4120:
13358 mips_fix_vr4120 = 0;
60b63b72
RS
13359 break;
13360
7d8e00cf
RS
13361 case OPTION_FIX_VR4130:
13362 mips_fix_vr4130 = 1;
13363 break;
13364
13365 case OPTION_NO_FIX_VR4130:
13366 mips_fix_vr4130 = 0;
13367 break;
13368
d954098f
DD
13369 case OPTION_FIX_CN63XXP1:
13370 mips_fix_cn63xxp1 = TRUE;
13371 break;
13372
13373 case OPTION_NO_FIX_CN63XXP1:
13374 mips_fix_cn63xxp1 = FALSE;
13375 break;
13376
4a6a3df4
AO
13377 case OPTION_RELAX_BRANCH:
13378 mips_relax_branch = 1;
13379 break;
13380
13381 case OPTION_NO_RELAX_BRANCH:
13382 mips_relax_branch = 0;
13383 break;
13384
833794fc
MR
13385 case OPTION_INSN32:
13386 mips_opts.insn32 = TRUE;
13387 break;
13388
13389 case OPTION_NO_INSN32:
13390 mips_opts.insn32 = FALSE;
13391 break;
13392
aa6975fb
ILT
13393 case OPTION_MSHARED:
13394 mips_in_shared = TRUE;
13395 break;
13396
13397 case OPTION_MNO_SHARED:
13398 mips_in_shared = FALSE;
13399 break;
13400
aed1a261
RS
13401 case OPTION_MSYM32:
13402 mips_opts.sym32 = TRUE;
13403 break;
13404
13405 case OPTION_MNO_SYM32:
13406 mips_opts.sym32 = FALSE;
13407 break;
13408
252b5132
RH
13409 /* When generating ELF code, we permit -KPIC and -call_shared to
13410 select SVR4_PIC, and -non_shared to select no PIC. This is
13411 intended to be compatible with Irix 5. */
13412 case OPTION_CALL_SHARED:
252b5132 13413 mips_pic = SVR4_PIC;
143d77c5 13414 mips_abicalls = TRUE;
252b5132
RH
13415 break;
13416
861fb55a 13417 case OPTION_CALL_NONPIC:
861fb55a
DJ
13418 mips_pic = NO_PIC;
13419 mips_abicalls = TRUE;
13420 break;
13421
252b5132 13422 case OPTION_NON_SHARED:
252b5132 13423 mips_pic = NO_PIC;
143d77c5 13424 mips_abicalls = FALSE;
252b5132
RH
13425 break;
13426
44075ae2
TS
13427 /* The -xgot option tells the assembler to use 32 bit offsets
13428 when accessing the got in SVR4_PIC mode. It is for Irix
252b5132
RH
13429 compatibility. */
13430 case OPTION_XGOT:
13431 mips_big_got = 1;
13432 break;
13433
13434 case 'G':
6caf9ef4
TS
13435 g_switch_value = atoi (arg);
13436 g_switch_seen = 1;
252b5132
RH
13437 break;
13438
34ba82a8
TS
13439 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
13440 and -mabi=64. */
252b5132 13441 case OPTION_32:
f3ded42a 13442 mips_abi = O32_ABI;
252b5132
RH
13443 break;
13444
e013f690 13445 case OPTION_N32:
316f5878 13446 mips_abi = N32_ABI;
e013f690 13447 break;
252b5132 13448
e013f690 13449 case OPTION_64:
316f5878 13450 mips_abi = N64_ABI;
f43abd2b 13451 if (!support_64bit_objects())
e013f690 13452 as_fatal (_("No compiled in support for 64 bit object file format"));
252b5132
RH
13453 break;
13454
c97ef257 13455 case OPTION_GP32:
a325df1d 13456 file_mips_gp32 = 1;
c97ef257
AH
13457 break;
13458
13459 case OPTION_GP64:
a325df1d 13460 file_mips_gp32 = 0;
c97ef257 13461 break;
252b5132 13462
ca4e0257 13463 case OPTION_FP32:
a325df1d 13464 file_mips_fp32 = 1;
316f5878
RS
13465 break;
13466
13467 case OPTION_FP64:
13468 file_mips_fp32 = 0;
ca4e0257
RS
13469 break;
13470
037b32b9
AN
13471 case OPTION_SINGLE_FLOAT:
13472 file_mips_single_float = 1;
13473 break;
13474
13475 case OPTION_DOUBLE_FLOAT:
13476 file_mips_single_float = 0;
13477 break;
13478
13479 case OPTION_SOFT_FLOAT:
13480 file_mips_soft_float = 1;
13481 break;
13482
13483 case OPTION_HARD_FLOAT:
13484 file_mips_soft_float = 0;
13485 break;
13486
252b5132 13487 case OPTION_MABI:
e013f690 13488 if (strcmp (arg, "32") == 0)
316f5878 13489 mips_abi = O32_ABI;
e013f690 13490 else if (strcmp (arg, "o64") == 0)
316f5878 13491 mips_abi = O64_ABI;
e013f690 13492 else if (strcmp (arg, "n32") == 0)
316f5878 13493 mips_abi = N32_ABI;
e013f690
TS
13494 else if (strcmp (arg, "64") == 0)
13495 {
316f5878 13496 mips_abi = N64_ABI;
e013f690
TS
13497 if (! support_64bit_objects())
13498 as_fatal (_("No compiled in support for 64 bit object file "
13499 "format"));
13500 }
13501 else if (strcmp (arg, "eabi") == 0)
316f5878 13502 mips_abi = EABI_ABI;
e013f690 13503 else
da0e507f
TS
13504 {
13505 as_fatal (_("invalid abi -mabi=%s"), arg);
13506 return 0;
13507 }
252b5132
RH
13508 break;
13509
6b76fefe 13510 case OPTION_M7000_HILO_FIX:
b34976b6 13511 mips_7000_hilo_fix = TRUE;
6b76fefe
CM
13512 break;
13513
9ee72ff1 13514 case OPTION_MNO_7000_HILO_FIX:
b34976b6 13515 mips_7000_hilo_fix = FALSE;
6b76fefe
CM
13516 break;
13517
ecb4347a 13518 case OPTION_MDEBUG:
b34976b6 13519 mips_flag_mdebug = TRUE;
ecb4347a
DJ
13520 break;
13521
13522 case OPTION_NO_MDEBUG:
b34976b6 13523 mips_flag_mdebug = FALSE;
ecb4347a 13524 break;
dcd410fe
RO
13525
13526 case OPTION_PDR:
13527 mips_flag_pdr = TRUE;
13528 break;
13529
13530 case OPTION_NO_PDR:
13531 mips_flag_pdr = FALSE;
13532 break;
0a44bf69
RS
13533
13534 case OPTION_MVXWORKS_PIC:
13535 mips_pic = VXWORKS_PIC;
13536 break;
ecb4347a 13537
ba92f887
MR
13538 case OPTION_NAN:
13539 if (strcmp (arg, "2008") == 0)
13540 mips_flag_nan2008 = TRUE;
13541 else if (strcmp (arg, "legacy") == 0)
13542 mips_flag_nan2008 = FALSE;
13543 else
13544 {
13545 as_fatal (_("Invalid NaN setting -mnan=%s"), arg);
13546 return 0;
13547 }
13548 break;
13549
252b5132
RH
13550 default:
13551 return 0;
13552 }
13553
c67a084a
NC
13554 mips_fix_loongson2f = mips_fix_loongson2f_nop || mips_fix_loongson2f_jump;
13555
252b5132
RH
13556 return 1;
13557}
316f5878
RS
13558\f
13559/* Set up globals to generate code for the ISA or processor
13560 described by INFO. */
252b5132 13561
252b5132 13562static void
17a2f251 13563mips_set_architecture (const struct mips_cpu_info *info)
252b5132 13564{
316f5878 13565 if (info != 0)
252b5132 13566 {
fef14a42
TS
13567 file_mips_arch = info->cpu;
13568 mips_opts.arch = info->cpu;
316f5878 13569 mips_opts.isa = info->isa;
252b5132 13570 }
252b5132
RH
13571}
13572
252b5132 13573
316f5878 13574/* Likewise for tuning. */
252b5132 13575
316f5878 13576static void
17a2f251 13577mips_set_tune (const struct mips_cpu_info *info)
316f5878
RS
13578{
13579 if (info != 0)
fef14a42 13580 mips_tune = info->cpu;
316f5878 13581}
80cc45a5 13582
34ba82a8 13583
252b5132 13584void
17a2f251 13585mips_after_parse_args (void)
e9670677 13586{
fef14a42
TS
13587 const struct mips_cpu_info *arch_info = 0;
13588 const struct mips_cpu_info *tune_info = 0;
13589
e9670677 13590 /* GP relative stuff not working for PE */
6caf9ef4 13591 if (strncmp (TARGET_OS, "pe", 2) == 0)
e9670677 13592 {
6caf9ef4 13593 if (g_switch_seen && g_switch_value != 0)
e9670677
MR
13594 as_bad (_("-G not supported in this configuration."));
13595 g_switch_value = 0;
13596 }
13597
cac012d6
AO
13598 if (mips_abi == NO_ABI)
13599 mips_abi = MIPS_DEFAULT_ABI;
13600
22923709
RS
13601 /* The following code determines the architecture and register size.
13602 Similar code was added to GCC 3.3 (see override_options() in
13603 config/mips/mips.c). The GAS and GCC code should be kept in sync
13604 as much as possible. */
e9670677 13605
316f5878 13606 if (mips_arch_string != 0)
fef14a42 13607 arch_info = mips_parse_cpu ("-march", mips_arch_string);
e9670677 13608
316f5878 13609 if (file_mips_isa != ISA_UNKNOWN)
e9670677 13610 {
316f5878 13611 /* Handle -mipsN. At this point, file_mips_isa contains the
fef14a42 13612 ISA level specified by -mipsN, while arch_info->isa contains
316f5878 13613 the -march selection (if any). */
fef14a42 13614 if (arch_info != 0)
e9670677 13615 {
316f5878
RS
13616 /* -march takes precedence over -mipsN, since it is more descriptive.
13617 There's no harm in specifying both as long as the ISA levels
13618 are the same. */
fef14a42 13619 if (file_mips_isa != arch_info->isa)
316f5878
RS
13620 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
13621 mips_cpu_info_from_isa (file_mips_isa)->name,
fef14a42 13622 mips_cpu_info_from_isa (arch_info->isa)->name);
e9670677 13623 }
316f5878 13624 else
fef14a42 13625 arch_info = mips_cpu_info_from_isa (file_mips_isa);
e9670677
MR
13626 }
13627
fef14a42 13628 if (arch_info == 0)
95bfe26e
MF
13629 {
13630 arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT);
13631 gas_assert (arch_info);
13632 }
e9670677 13633
fef14a42 13634 if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa))
20203fb9 13635 as_bad (_("-march=%s is not compatible with the selected ABI"),
fef14a42
TS
13636 arch_info->name);
13637
13638 mips_set_architecture (arch_info);
13639
13640 /* Optimize for file_mips_arch, unless -mtune selects a different processor. */
13641 if (mips_tune_string != 0)
13642 tune_info = mips_parse_cpu ("-mtune", mips_tune_string);
e9670677 13643
fef14a42
TS
13644 if (tune_info == 0)
13645 mips_set_tune (arch_info);
13646 else
13647 mips_set_tune (tune_info);
e9670677 13648
316f5878 13649 if (file_mips_gp32 >= 0)
e9670677 13650 {
316f5878
RS
13651 /* The user specified the size of the integer registers. Make sure
13652 it agrees with the ABI and ISA. */
13653 if (file_mips_gp32 == 0 && !ISA_HAS_64BIT_REGS (mips_opts.isa))
13654 as_bad (_("-mgp64 used with a 32-bit processor"));
13655 else if (file_mips_gp32 == 1 && ABI_NEEDS_64BIT_REGS (mips_abi))
13656 as_bad (_("-mgp32 used with a 64-bit ABI"));
13657 else if (file_mips_gp32 == 0 && ABI_NEEDS_32BIT_REGS (mips_abi))
13658 as_bad (_("-mgp64 used with a 32-bit ABI"));
e9670677
MR
13659 }
13660 else
13661 {
316f5878
RS
13662 /* Infer the integer register size from the ABI and processor.
13663 Restrict ourselves to 32-bit registers if that's all the
13664 processor has, or if the ABI cannot handle 64-bit registers. */
13665 file_mips_gp32 = (ABI_NEEDS_32BIT_REGS (mips_abi)
13666 || !ISA_HAS_64BIT_REGS (mips_opts.isa));
e9670677
MR
13667 }
13668
ad3fea08
TS
13669 switch (file_mips_fp32)
13670 {
13671 default:
13672 case -1:
13673 /* No user specified float register size.
13674 ??? GAS treats single-float processors as though they had 64-bit
13675 float registers (although it complains when double-precision
13676 instructions are used). As things stand, saying they have 32-bit
13677 registers would lead to spurious "register must be even" messages.
13678 So here we assume float registers are never smaller than the
13679 integer ones. */
13680 if (file_mips_gp32 == 0)
13681 /* 64-bit integer registers implies 64-bit float registers. */
13682 file_mips_fp32 = 0;
c6278170 13683 else if ((mips_opts.ase & FP64_ASES)
ad3fea08
TS
13684 && ISA_HAS_64BIT_FPRS (mips_opts.isa))
13685 /* -mips3d and -mdmx imply 64-bit float registers, if possible. */
13686 file_mips_fp32 = 0;
13687 else
13688 /* 32-bit float registers. */
13689 file_mips_fp32 = 1;
13690 break;
13691
13692 /* The user specified the size of the float registers. Check if it
13693 agrees with the ABI and ISA. */
13694 case 0:
13695 if (!ISA_HAS_64BIT_FPRS (mips_opts.isa))
13696 as_bad (_("-mfp64 used with a 32-bit fpu"));
13697 else if (ABI_NEEDS_32BIT_REGS (mips_abi)
13698 && !ISA_HAS_MXHC1 (mips_opts.isa))
13699 as_warn (_("-mfp64 used with a 32-bit ABI"));
13700 break;
13701 case 1:
13702 if (ABI_NEEDS_64BIT_REGS (mips_abi))
13703 as_warn (_("-mfp32 used with a 64-bit ABI"));
13704 break;
13705 }
e9670677 13706
316f5878 13707 /* End of GCC-shared inference code. */
e9670677 13708
17a2f251
TS
13709 /* This flag is set when we have a 64-bit capable CPU but use only
13710 32-bit wide registers. Note that EABI does not use it. */
13711 if (ISA_HAS_64BIT_REGS (mips_opts.isa)
13712 && ((mips_abi == NO_ABI && file_mips_gp32 == 1)
13713 || mips_abi == O32_ABI))
316f5878 13714 mips_32bitmode = 1;
e9670677
MR
13715
13716 if (mips_opts.isa == ISA_MIPS1 && mips_trap)
13717 as_bad (_("trap exception not supported at ISA 1"));
13718
e9670677
MR
13719 /* If the selected architecture includes support for ASEs, enable
13720 generation of code for them. */
a4672219 13721 if (mips_opts.mips16 == -1)
fef14a42 13722 mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_arch)) ? 1 : 0;
df58fc94
RS
13723 if (mips_opts.micromips == -1)
13724 mips_opts.micromips = (CPU_HAS_MICROMIPS (file_mips_arch)) ? 1 : 0;
846ef2d0
RS
13725
13726 /* MIPS3D and MDMX require 64-bit FPRs, so -mfp32 should stop those
13727 ASEs from being selected implicitly. */
13728 if (file_mips_fp32 == 1)
13729 file_ase_explicit |= ASE_MIPS3D | ASE_MDMX;
13730
13731 /* If the user didn't explicitly select or deselect a particular ASE,
13732 use the default setting for the CPU. */
13733 mips_opts.ase |= (arch_info->ase & ~file_ase_explicit);
13734
e9670677 13735 file_mips_isa = mips_opts.isa;
846ef2d0 13736 file_ase = mips_opts.ase;
e9670677
MR
13737 mips_opts.gp32 = file_mips_gp32;
13738 mips_opts.fp32 = file_mips_fp32;
037b32b9
AN
13739 mips_opts.soft_float = file_mips_soft_float;
13740 mips_opts.single_float = file_mips_single_float;
e9670677 13741
c6278170
RS
13742 mips_check_isa_supports_ases ();
13743
ecb4347a 13744 if (mips_flag_mdebug < 0)
e8044f35 13745 mips_flag_mdebug = 0;
e9670677
MR
13746}
13747\f
13748void
17a2f251 13749mips_init_after_args (void)
252b5132
RH
13750{
13751 /* initialize opcodes */
13752 bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes;
beae10d5 13753 mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes;
252b5132
RH
13754}
13755
13756long
17a2f251 13757md_pcrel_from (fixS *fixP)
252b5132 13758{
a7ebbfdf
TS
13759 valueT addr = fixP->fx_where + fixP->fx_frag->fr_address;
13760 switch (fixP->fx_r_type)
13761 {
df58fc94
RS
13762 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
13763 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
13764 /* Return the address of the delay slot. */
13765 return addr + 2;
13766
13767 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
13768 case BFD_RELOC_MICROMIPS_JMP:
a7ebbfdf
TS
13769 case BFD_RELOC_16_PCREL_S2:
13770 case BFD_RELOC_MIPS_JMP:
13771 /* Return the address of the delay slot. */
13772 return addr + 4;
df58fc94 13773
b47468a6
CM
13774 case BFD_RELOC_32_PCREL:
13775 return addr;
13776
a7ebbfdf 13777 default:
58ea3d6a 13778 /* We have no relocation type for PC relative MIPS16 instructions. */
64817874
TS
13779 if (fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != now_seg)
13780 as_bad_where (fixP->fx_file, fixP->fx_line,
13781 _("PC relative MIPS16 instruction references a different section"));
a7ebbfdf
TS
13782 return addr;
13783 }
252b5132
RH
13784}
13785
252b5132
RH
13786/* This is called before the symbol table is processed. In order to
13787 work with gcc when using mips-tfile, we must keep all local labels.
13788 However, in other cases, we want to discard them. If we were
13789 called with -g, but we didn't see any debugging information, it may
13790 mean that gcc is smuggling debugging information through to
13791 mips-tfile, in which case we must generate all local labels. */
13792
13793void
17a2f251 13794mips_frob_file_before_adjust (void)
252b5132
RH
13795{
13796#ifndef NO_ECOFF_DEBUGGING
13797 if (ECOFF_DEBUGGING
13798 && mips_debug != 0
13799 && ! ecoff_debugging_seen)
13800 flag_keep_locals = 1;
13801#endif
13802}
13803
3b91255e 13804/* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
55cf6793 13805 the corresponding LO16 reloc. This is called before md_apply_fix and
3b91255e
RS
13806 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
13807 relocation operators.
13808
13809 For our purposes, a %lo() expression matches a %got() or %hi()
13810 expression if:
13811
13812 (a) it refers to the same symbol; and
13813 (b) the offset applied in the %lo() expression is no lower than
13814 the offset applied in the %got() or %hi().
13815
13816 (b) allows us to cope with code like:
13817
13818 lui $4,%hi(foo)
13819 lh $4,%lo(foo+2)($4)
13820
13821 ...which is legal on RELA targets, and has a well-defined behaviour
13822 if the user knows that adding 2 to "foo" will not induce a carry to
13823 the high 16 bits.
13824
13825 When several %lo()s match a particular %got() or %hi(), we use the
13826 following rules to distinguish them:
13827
13828 (1) %lo()s with smaller offsets are a better match than %lo()s with
13829 higher offsets.
13830
13831 (2) %lo()s with no matching %got() or %hi() are better than those
13832 that already have a matching %got() or %hi().
13833
13834 (3) later %lo()s are better than earlier %lo()s.
13835
13836 These rules are applied in order.
13837
13838 (1) means, among other things, that %lo()s with identical offsets are
13839 chosen if they exist.
13840
13841 (2) means that we won't associate several high-part relocations with
13842 the same low-part relocation unless there's no alternative. Having
13843 several high parts for the same low part is a GNU extension; this rule
13844 allows careful users to avoid it.
13845
13846 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
13847 with the last high-part relocation being at the front of the list.
13848 It therefore makes sense to choose the last matching low-part
13849 relocation, all other things being equal. It's also easier
13850 to code that way. */
252b5132
RH
13851
13852void
17a2f251 13853mips_frob_file (void)
252b5132
RH
13854{
13855 struct mips_hi_fixup *l;
35903be0 13856 bfd_reloc_code_real_type looking_for_rtype = BFD_RELOC_UNUSED;
252b5132
RH
13857
13858 for (l = mips_hi_fixup_list; l != NULL; l = l->next)
13859 {
13860 segment_info_type *seginfo;
3b91255e
RS
13861 bfd_boolean matched_lo_p;
13862 fixS **hi_pos, **lo_pos, **pos;
252b5132 13863
9c2799c2 13864 gas_assert (reloc_needs_lo_p (l->fixp->fx_r_type));
252b5132 13865
5919d012 13866 /* If a GOT16 relocation turns out to be against a global symbol,
b886a2ab
RS
13867 there isn't supposed to be a matching LO. Ignore %gots against
13868 constants; we'll report an error for those later. */
738e5348 13869 if (got16_reloc_p (l->fixp->fx_r_type)
b886a2ab
RS
13870 && !(l->fixp->fx_addsy
13871 && pic_need_relax (l->fixp->fx_addsy, l->seg)))
5919d012
RS
13872 continue;
13873
13874 /* Check quickly whether the next fixup happens to be a matching %lo. */
13875 if (fixup_has_matching_lo_p (l->fixp))
252b5132
RH
13876 continue;
13877
252b5132 13878 seginfo = seg_info (l->seg);
252b5132 13879
3b91255e
RS
13880 /* Set HI_POS to the position of this relocation in the chain.
13881 Set LO_POS to the position of the chosen low-part relocation.
13882 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
13883 relocation that matches an immediately-preceding high-part
13884 relocation. */
13885 hi_pos = NULL;
13886 lo_pos = NULL;
13887 matched_lo_p = FALSE;
738e5348 13888 looking_for_rtype = matching_lo_reloc (l->fixp->fx_r_type);
35903be0 13889
3b91255e
RS
13890 for (pos = &seginfo->fix_root; *pos != NULL; pos = &(*pos)->fx_next)
13891 {
13892 if (*pos == l->fixp)
13893 hi_pos = pos;
13894
35903be0 13895 if ((*pos)->fx_r_type == looking_for_rtype
30cfc97a 13896 && symbol_same_p ((*pos)->fx_addsy, l->fixp->fx_addsy)
3b91255e
RS
13897 && (*pos)->fx_offset >= l->fixp->fx_offset
13898 && (lo_pos == NULL
13899 || (*pos)->fx_offset < (*lo_pos)->fx_offset
13900 || (!matched_lo_p
13901 && (*pos)->fx_offset == (*lo_pos)->fx_offset)))
13902 lo_pos = pos;
13903
13904 matched_lo_p = (reloc_needs_lo_p ((*pos)->fx_r_type)
13905 && fixup_has_matching_lo_p (*pos));
13906 }
13907
13908 /* If we found a match, remove the high-part relocation from its
13909 current position and insert it before the low-part relocation.
13910 Make the offsets match so that fixup_has_matching_lo_p()
13911 will return true.
13912
13913 We don't warn about unmatched high-part relocations since some
13914 versions of gcc have been known to emit dead "lui ...%hi(...)"
13915 instructions. */
13916 if (lo_pos != NULL)
13917 {
13918 l->fixp->fx_offset = (*lo_pos)->fx_offset;
13919 if (l->fixp->fx_next != *lo_pos)
252b5132 13920 {
3b91255e
RS
13921 *hi_pos = l->fixp->fx_next;
13922 l->fixp->fx_next = *lo_pos;
13923 *lo_pos = l->fixp;
252b5132 13924 }
252b5132
RH
13925 }
13926 }
13927}
13928
252b5132 13929int
17a2f251 13930mips_force_relocation (fixS *fixp)
252b5132 13931{
ae6063d4 13932 if (generic_force_reloc (fixp))
252b5132
RH
13933 return 1;
13934
df58fc94
RS
13935 /* We want to keep BFD_RELOC_MICROMIPS_*_PCREL_S1 relocation,
13936 so that the linker relaxation can update targets. */
13937 if (fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1
13938 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1
13939 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1)
13940 return 1;
13941
3e722fb5 13942 return 0;
252b5132
RH
13943}
13944
b886a2ab
RS
13945/* Read the instruction associated with RELOC from BUF. */
13946
13947static unsigned int
13948read_reloc_insn (char *buf, bfd_reloc_code_real_type reloc)
13949{
13950 if (mips16_reloc_p (reloc) || micromips_reloc_p (reloc))
13951 return read_compressed_insn (buf, 4);
13952 else
13953 return read_insn (buf);
13954}
13955
13956/* Write instruction INSN to BUF, given that it has been relocated
13957 by RELOC. */
13958
13959static void
13960write_reloc_insn (char *buf, bfd_reloc_code_real_type reloc,
13961 unsigned long insn)
13962{
13963 if (mips16_reloc_p (reloc) || micromips_reloc_p (reloc))
13964 write_compressed_insn (buf, insn, 4);
13965 else
13966 write_insn (buf, insn);
13967}
13968
252b5132
RH
13969/* Apply a fixup to the object file. */
13970
94f592af 13971void
55cf6793 13972md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
252b5132 13973{
4d68580a 13974 char *buf;
b886a2ab 13975 unsigned long insn;
a7ebbfdf 13976 reloc_howto_type *howto;
252b5132 13977
a7ebbfdf
TS
13978 /* We ignore generic BFD relocations we don't know about. */
13979 howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type);
13980 if (! howto)
13981 return;
65551fa4 13982
df58fc94
RS
13983 gas_assert (fixP->fx_size == 2
13984 || fixP->fx_size == 4
90ecf173
MR
13985 || fixP->fx_r_type == BFD_RELOC_16
13986 || fixP->fx_r_type == BFD_RELOC_64
13987 || fixP->fx_r_type == BFD_RELOC_CTOR
13988 || fixP->fx_r_type == BFD_RELOC_MIPS_SUB
df58fc94 13989 || fixP->fx_r_type == BFD_RELOC_MICROMIPS_SUB
90ecf173
MR
13990 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
13991 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY
13992 || fixP->fx_r_type == BFD_RELOC_MIPS_TLS_DTPREL64);
252b5132 13993
4d68580a 13994 buf = fixP->fx_frag->fr_literal + fixP->fx_where;
252b5132 13995
df58fc94
RS
13996 gas_assert (!fixP->fx_pcrel || fixP->fx_r_type == BFD_RELOC_16_PCREL_S2
13997 || fixP->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1
13998 || fixP->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1
b47468a6
CM
13999 || fixP->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1
14000 || fixP->fx_r_type == BFD_RELOC_32_PCREL);
b1dca8ee
RS
14001
14002 /* Don't treat parts of a composite relocation as done. There are two
14003 reasons for this:
14004
14005 (1) The second and third parts will be against 0 (RSS_UNDEF) but
14006 should nevertheless be emitted if the first part is.
14007
14008 (2) In normal usage, composite relocations are never assembly-time
14009 constants. The easiest way of dealing with the pathological
14010 exceptions is to generate a relocation against STN_UNDEF and
14011 leave everything up to the linker. */
3994f87e 14012 if (fixP->fx_addsy == NULL && !fixP->fx_pcrel && fixP->fx_tcbit == 0)
252b5132
RH
14013 fixP->fx_done = 1;
14014
14015 switch (fixP->fx_r_type)
14016 {
3f98094e
DJ
14017 case BFD_RELOC_MIPS_TLS_GD:
14018 case BFD_RELOC_MIPS_TLS_LDM:
741d6ea8
JM
14019 case BFD_RELOC_MIPS_TLS_DTPREL32:
14020 case BFD_RELOC_MIPS_TLS_DTPREL64:
3f98094e
DJ
14021 case BFD_RELOC_MIPS_TLS_DTPREL_HI16:
14022 case BFD_RELOC_MIPS_TLS_DTPREL_LO16:
14023 case BFD_RELOC_MIPS_TLS_GOTTPREL:
d0f13682
CLT
14024 case BFD_RELOC_MIPS_TLS_TPREL32:
14025 case BFD_RELOC_MIPS_TLS_TPREL64:
3f98094e
DJ
14026 case BFD_RELOC_MIPS_TLS_TPREL_HI16:
14027 case BFD_RELOC_MIPS_TLS_TPREL_LO16:
df58fc94
RS
14028 case BFD_RELOC_MICROMIPS_TLS_GD:
14029 case BFD_RELOC_MICROMIPS_TLS_LDM:
14030 case BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16:
14031 case BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16:
14032 case BFD_RELOC_MICROMIPS_TLS_GOTTPREL:
14033 case BFD_RELOC_MICROMIPS_TLS_TPREL_HI16:
14034 case BFD_RELOC_MICROMIPS_TLS_TPREL_LO16:
d0f13682
CLT
14035 case BFD_RELOC_MIPS16_TLS_GD:
14036 case BFD_RELOC_MIPS16_TLS_LDM:
14037 case BFD_RELOC_MIPS16_TLS_DTPREL_HI16:
14038 case BFD_RELOC_MIPS16_TLS_DTPREL_LO16:
14039 case BFD_RELOC_MIPS16_TLS_GOTTPREL:
14040 case BFD_RELOC_MIPS16_TLS_TPREL_HI16:
14041 case BFD_RELOC_MIPS16_TLS_TPREL_LO16:
b886a2ab
RS
14042 if (!fixP->fx_addsy)
14043 {
14044 as_bad_where (fixP->fx_file, fixP->fx_line,
14045 _("TLS relocation against a constant"));
14046 break;
14047 }
3f98094e
DJ
14048 S_SET_THREAD_LOCAL (fixP->fx_addsy);
14049 /* fall through */
14050
252b5132 14051 case BFD_RELOC_MIPS_JMP:
e369bcce
TS
14052 case BFD_RELOC_MIPS_SHIFT5:
14053 case BFD_RELOC_MIPS_SHIFT6:
14054 case BFD_RELOC_MIPS_GOT_DISP:
14055 case BFD_RELOC_MIPS_GOT_PAGE:
14056 case BFD_RELOC_MIPS_GOT_OFST:
14057 case BFD_RELOC_MIPS_SUB:
14058 case BFD_RELOC_MIPS_INSERT_A:
14059 case BFD_RELOC_MIPS_INSERT_B:
14060 case BFD_RELOC_MIPS_DELETE:
14061 case BFD_RELOC_MIPS_HIGHEST:
14062 case BFD_RELOC_MIPS_HIGHER:
14063 case BFD_RELOC_MIPS_SCN_DISP:
14064 case BFD_RELOC_MIPS_REL16:
14065 case BFD_RELOC_MIPS_RELGOT:
14066 case BFD_RELOC_MIPS_JALR:
252b5132
RH
14067 case BFD_RELOC_HI16:
14068 case BFD_RELOC_HI16_S:
b886a2ab 14069 case BFD_RELOC_LO16:
cdf6fd85 14070 case BFD_RELOC_GPREL16:
252b5132
RH
14071 case BFD_RELOC_MIPS_LITERAL:
14072 case BFD_RELOC_MIPS_CALL16:
14073 case BFD_RELOC_MIPS_GOT16:
cdf6fd85 14074 case BFD_RELOC_GPREL32:
252b5132
RH
14075 case BFD_RELOC_MIPS_GOT_HI16:
14076 case BFD_RELOC_MIPS_GOT_LO16:
14077 case BFD_RELOC_MIPS_CALL_HI16:
14078 case BFD_RELOC_MIPS_CALL_LO16:
14079 case BFD_RELOC_MIPS16_GPREL:
738e5348
RS
14080 case BFD_RELOC_MIPS16_GOT16:
14081 case BFD_RELOC_MIPS16_CALL16:
d6f16593
MR
14082 case BFD_RELOC_MIPS16_HI16:
14083 case BFD_RELOC_MIPS16_HI16_S:
b886a2ab 14084 case BFD_RELOC_MIPS16_LO16:
252b5132 14085 case BFD_RELOC_MIPS16_JMP:
df58fc94
RS
14086 case BFD_RELOC_MICROMIPS_JMP:
14087 case BFD_RELOC_MICROMIPS_GOT_DISP:
14088 case BFD_RELOC_MICROMIPS_GOT_PAGE:
14089 case BFD_RELOC_MICROMIPS_GOT_OFST:
14090 case BFD_RELOC_MICROMIPS_SUB:
14091 case BFD_RELOC_MICROMIPS_HIGHEST:
14092 case BFD_RELOC_MICROMIPS_HIGHER:
14093 case BFD_RELOC_MICROMIPS_SCN_DISP:
14094 case BFD_RELOC_MICROMIPS_JALR:
14095 case BFD_RELOC_MICROMIPS_HI16:
14096 case BFD_RELOC_MICROMIPS_HI16_S:
b886a2ab 14097 case BFD_RELOC_MICROMIPS_LO16:
df58fc94
RS
14098 case BFD_RELOC_MICROMIPS_GPREL16:
14099 case BFD_RELOC_MICROMIPS_LITERAL:
14100 case BFD_RELOC_MICROMIPS_CALL16:
14101 case BFD_RELOC_MICROMIPS_GOT16:
14102 case BFD_RELOC_MICROMIPS_GOT_HI16:
14103 case BFD_RELOC_MICROMIPS_GOT_LO16:
14104 case BFD_RELOC_MICROMIPS_CALL_HI16:
14105 case BFD_RELOC_MICROMIPS_CALL_LO16:
067ec077 14106 case BFD_RELOC_MIPS_EH:
b886a2ab
RS
14107 if (fixP->fx_done)
14108 {
14109 offsetT value;
14110
14111 if (calculate_reloc (fixP->fx_r_type, *valP, &value))
14112 {
14113 insn = read_reloc_insn (buf, fixP->fx_r_type);
14114 if (mips16_reloc_p (fixP->fx_r_type))
14115 insn |= mips16_immed_extend (value, 16);
14116 else
14117 insn |= (value & 0xffff);
14118 write_reloc_insn (buf, fixP->fx_r_type, insn);
14119 }
14120 else
14121 as_bad_where (fixP->fx_file, fixP->fx_line,
14122 _("Unsupported constant in relocation"));
14123 }
252b5132
RH
14124 break;
14125
252b5132
RH
14126 case BFD_RELOC_64:
14127 /* This is handled like BFD_RELOC_32, but we output a sign
14128 extended value if we are only 32 bits. */
3e722fb5 14129 if (fixP->fx_done)
252b5132
RH
14130 {
14131 if (8 <= sizeof (valueT))
4d68580a 14132 md_number_to_chars (buf, *valP, 8);
252b5132
RH
14133 else
14134 {
a7ebbfdf 14135 valueT hiv;
252b5132 14136
a7ebbfdf 14137 if ((*valP & 0x80000000) != 0)
252b5132
RH
14138 hiv = 0xffffffff;
14139 else
14140 hiv = 0;
4d68580a
RS
14141 md_number_to_chars (buf + (target_big_endian ? 4 : 0), *valP, 4);
14142 md_number_to_chars (buf + (target_big_endian ? 0 : 4), hiv, 4);
252b5132
RH
14143 }
14144 }
14145 break;
14146
056350c6 14147 case BFD_RELOC_RVA:
252b5132 14148 case BFD_RELOC_32:
b47468a6 14149 case BFD_RELOC_32_PCREL:
252b5132
RH
14150 case BFD_RELOC_16:
14151 /* If we are deleting this reloc entry, we must fill in the
54f4ddb3
TS
14152 value now. This can happen if we have a .word which is not
14153 resolved when it appears but is later defined. */
252b5132 14154 if (fixP->fx_done)
4d68580a 14155 md_number_to_chars (buf, *valP, fixP->fx_size);
252b5132
RH
14156 break;
14157
252b5132 14158 case BFD_RELOC_16_PCREL_S2:
a7ebbfdf 14159 if ((*valP & 0x3) != 0)
cb56d3d3 14160 as_bad_where (fixP->fx_file, fixP->fx_line,
bad36eac 14161 _("Branch to misaligned address (%lx)"), (long) *valP);
cb56d3d3 14162
54f4ddb3
TS
14163 /* We need to save the bits in the instruction since fixup_segment()
14164 might be deleting the relocation entry (i.e., a branch within
14165 the current segment). */
a7ebbfdf 14166 if (! fixP->fx_done)
bb2d6cd7 14167 break;
252b5132 14168
54f4ddb3 14169 /* Update old instruction data. */
4d68580a 14170 insn = read_insn (buf);
252b5132 14171
a7ebbfdf
TS
14172 if (*valP + 0x20000 <= 0x3ffff)
14173 {
14174 insn |= (*valP >> 2) & 0xffff;
4d68580a 14175 write_insn (buf, insn);
a7ebbfdf
TS
14176 }
14177 else if (mips_pic == NO_PIC
14178 && fixP->fx_done
14179 && fixP->fx_frag->fr_address >= text_section->vma
14180 && (fixP->fx_frag->fr_address
587aac4e 14181 < text_section->vma + bfd_get_section_size (text_section))
a7ebbfdf
TS
14182 && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */
14183 || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */
14184 || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */
252b5132
RH
14185 {
14186 /* The branch offset is too large. If this is an
14187 unconditional branch, and we are not generating PIC code,
14188 we can convert it to an absolute jump instruction. */
a7ebbfdf
TS
14189 if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */
14190 insn = 0x0c000000; /* jal */
252b5132 14191 else
a7ebbfdf
TS
14192 insn = 0x08000000; /* j */
14193 fixP->fx_r_type = BFD_RELOC_MIPS_JMP;
14194 fixP->fx_done = 0;
14195 fixP->fx_addsy = section_symbol (text_section);
14196 *valP += md_pcrel_from (fixP);
4d68580a 14197 write_insn (buf, insn);
a7ebbfdf
TS
14198 }
14199 else
14200 {
14201 /* If we got here, we have branch-relaxation disabled,
14202 and there's nothing we can do to fix this instruction
14203 without turning it into a longer sequence. */
14204 as_bad_where (fixP->fx_file, fixP->fx_line,
14205 _("Branch out of range"));
252b5132 14206 }
252b5132
RH
14207 break;
14208
df58fc94
RS
14209 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
14210 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
14211 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
14212 /* We adjust the offset back to even. */
14213 if ((*valP & 0x1) != 0)
14214 --(*valP);
14215
14216 if (! fixP->fx_done)
14217 break;
14218
14219 /* Should never visit here, because we keep the relocation. */
14220 abort ();
14221 break;
14222
252b5132
RH
14223 case BFD_RELOC_VTABLE_INHERIT:
14224 fixP->fx_done = 0;
14225 if (fixP->fx_addsy
14226 && !S_IS_DEFINED (fixP->fx_addsy)
14227 && !S_IS_WEAK (fixP->fx_addsy))
14228 S_SET_WEAK (fixP->fx_addsy);
14229 break;
14230
14231 case BFD_RELOC_VTABLE_ENTRY:
14232 fixP->fx_done = 0;
14233 break;
14234
14235 default:
b37df7c4 14236 abort ();
252b5132 14237 }
a7ebbfdf
TS
14238
14239 /* Remember value for tc_gen_reloc. */
14240 fixP->fx_addnumber = *valP;
252b5132
RH
14241}
14242
252b5132 14243static symbolS *
17a2f251 14244get_symbol (void)
252b5132
RH
14245{
14246 int c;
14247 char *name;
14248 symbolS *p;
14249
14250 name = input_line_pointer;
14251 c = get_symbol_end ();
14252 p = (symbolS *) symbol_find_or_make (name);
14253 *input_line_pointer = c;
14254 return p;
14255}
14256
742a56fe
RS
14257/* Align the current frag to a given power of two. If a particular
14258 fill byte should be used, FILL points to an integer that contains
14259 that byte, otherwise FILL is null.
14260
462427c4
RS
14261 This function used to have the comment:
14262
14263 The MIPS assembler also automatically adjusts any preceding label.
14264
14265 The implementation therefore applied the adjustment to a maximum of
14266 one label. However, other label adjustments are applied to batches
14267 of labels, and adjusting just one caused problems when new labels
14268 were added for the sake of debugging or unwind information.
14269 We therefore adjust all preceding labels (given as LABELS) instead. */
252b5132
RH
14270
14271static void
462427c4 14272mips_align (int to, int *fill, struct insn_label_list *labels)
252b5132 14273{
7d10b47d 14274 mips_emit_delays ();
df58fc94 14275 mips_record_compressed_mode ();
742a56fe
RS
14276 if (fill == NULL && subseg_text_p (now_seg))
14277 frag_align_code (to, 0);
14278 else
14279 frag_align (to, fill ? *fill : 0, 0);
252b5132 14280 record_alignment (now_seg, to);
462427c4 14281 mips_move_labels (labels, FALSE);
252b5132
RH
14282}
14283
14284/* Align to a given power of two. .align 0 turns off the automatic
14285 alignment used by the data creating pseudo-ops. */
14286
14287static void
17a2f251 14288s_align (int x ATTRIBUTE_UNUSED)
252b5132 14289{
742a56fe 14290 int temp, fill_value, *fill_ptr;
49954fb4 14291 long max_alignment = 28;
252b5132 14292
54f4ddb3 14293 /* o Note that the assembler pulls down any immediately preceding label
252b5132 14294 to the aligned address.
54f4ddb3 14295 o It's not documented but auto alignment is reinstated by
252b5132 14296 a .align pseudo instruction.
54f4ddb3 14297 o Note also that after auto alignment is turned off the mips assembler
252b5132 14298 issues an error on attempt to assemble an improperly aligned data item.
54f4ddb3 14299 We don't. */
252b5132
RH
14300
14301 temp = get_absolute_expression ();
14302 if (temp > max_alignment)
14303 as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment);
14304 else if (temp < 0)
14305 {
14306 as_warn (_("Alignment negative: 0 assumed."));
14307 temp = 0;
14308 }
14309 if (*input_line_pointer == ',')
14310 {
f9419b05 14311 ++input_line_pointer;
742a56fe
RS
14312 fill_value = get_absolute_expression ();
14313 fill_ptr = &fill_value;
252b5132
RH
14314 }
14315 else
742a56fe 14316 fill_ptr = 0;
252b5132
RH
14317 if (temp)
14318 {
a8dbcb85
TS
14319 segment_info_type *si = seg_info (now_seg);
14320 struct insn_label_list *l = si->label_list;
54f4ddb3 14321 /* Auto alignment should be switched on by next section change. */
252b5132 14322 auto_align = 1;
462427c4 14323 mips_align (temp, fill_ptr, l);
252b5132
RH
14324 }
14325 else
14326 {
14327 auto_align = 0;
14328 }
14329
14330 demand_empty_rest_of_line ();
14331}
14332
252b5132 14333static void
17a2f251 14334s_change_sec (int sec)
252b5132
RH
14335{
14336 segT seg;
14337
252b5132
RH
14338 /* The ELF backend needs to know that we are changing sections, so
14339 that .previous works correctly. We could do something like check
b6ff326e 14340 for an obj_section_change_hook macro, but that might be confusing
252b5132
RH
14341 as it would not be appropriate to use it in the section changing
14342 functions in read.c, since obj-elf.c intercepts those. FIXME:
14343 This should be cleaner, somehow. */
f3ded42a 14344 obj_elf_section_change_hook ();
252b5132 14345
7d10b47d 14346 mips_emit_delays ();
6a32d874 14347
252b5132
RH
14348 switch (sec)
14349 {
14350 case 't':
14351 s_text (0);
14352 break;
14353 case 'd':
14354 s_data (0);
14355 break;
14356 case 'b':
14357 subseg_set (bss_section, (subsegT) get_absolute_expression ());
14358 demand_empty_rest_of_line ();
14359 break;
14360
14361 case 'r':
4d0d148d
TS
14362 seg = subseg_new (RDATA_SECTION_NAME,
14363 (subsegT) get_absolute_expression ());
f3ded42a
RS
14364 bfd_set_section_flags (stdoutput, seg, (SEC_ALLOC | SEC_LOAD
14365 | SEC_READONLY | SEC_RELOC
14366 | SEC_DATA));
14367 if (strncmp (TARGET_OS, "elf", 3) != 0)
14368 record_alignment (seg, 4);
4d0d148d 14369 demand_empty_rest_of_line ();
252b5132
RH
14370 break;
14371
14372 case 's':
4d0d148d 14373 seg = subseg_new (".sdata", (subsegT) get_absolute_expression ());
f3ded42a
RS
14374 bfd_set_section_flags (stdoutput, seg,
14375 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA);
14376 if (strncmp (TARGET_OS, "elf", 3) != 0)
14377 record_alignment (seg, 4);
4d0d148d
TS
14378 demand_empty_rest_of_line ();
14379 break;
998b3c36
MR
14380
14381 case 'B':
14382 seg = subseg_new (".sbss", (subsegT) get_absolute_expression ());
f3ded42a
RS
14383 bfd_set_section_flags (stdoutput, seg, SEC_ALLOC);
14384 if (strncmp (TARGET_OS, "elf", 3) != 0)
14385 record_alignment (seg, 4);
998b3c36
MR
14386 demand_empty_rest_of_line ();
14387 break;
252b5132
RH
14388 }
14389
14390 auto_align = 1;
14391}
b34976b6 14392
cca86cc8 14393void
17a2f251 14394s_change_section (int ignore ATTRIBUTE_UNUSED)
cca86cc8 14395{
cca86cc8
SC
14396 char *section_name;
14397 char c;
684022ea 14398 char next_c = 0;
cca86cc8
SC
14399 int section_type;
14400 int section_flag;
14401 int section_entry_size;
14402 int section_alignment;
b34976b6 14403
cca86cc8
SC
14404 section_name = input_line_pointer;
14405 c = get_symbol_end ();
a816d1ed
AO
14406 if (c)
14407 next_c = *(input_line_pointer + 1);
cca86cc8 14408
4cf0dd0d
TS
14409 /* Do we have .section Name<,"flags">? */
14410 if (c != ',' || (c == ',' && next_c == '"'))
cca86cc8 14411 {
4cf0dd0d
TS
14412 /* just after name is now '\0'. */
14413 *input_line_pointer = c;
cca86cc8
SC
14414 input_line_pointer = section_name;
14415 obj_elf_section (ignore);
14416 return;
14417 }
14418 input_line_pointer++;
14419
14420 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
14421 if (c == ',')
14422 section_type = get_absolute_expression ();
14423 else
14424 section_type = 0;
14425 if (*input_line_pointer++ == ',')
14426 section_flag = get_absolute_expression ();
14427 else
14428 section_flag = 0;
14429 if (*input_line_pointer++ == ',')
14430 section_entry_size = get_absolute_expression ();
14431 else
14432 section_entry_size = 0;
14433 if (*input_line_pointer++ == ',')
14434 section_alignment = get_absolute_expression ();
14435 else
14436 section_alignment = 0;
87975d2a
AM
14437 /* FIXME: really ignore? */
14438 (void) section_alignment;
cca86cc8 14439
a816d1ed
AO
14440 section_name = xstrdup (section_name);
14441
8ab8a5c8
RS
14442 /* When using the generic form of .section (as implemented by obj-elf.c),
14443 there's no way to set the section type to SHT_MIPS_DWARF. Users have
14444 traditionally had to fall back on the more common @progbits instead.
14445
14446 There's nothing really harmful in this, since bfd will correct
14447 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
708587a4 14448 means that, for backwards compatibility, the special_section entries
8ab8a5c8
RS
14449 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
14450
14451 Even so, we shouldn't force users of the MIPS .section syntax to
14452 incorrectly label the sections as SHT_PROGBITS. The best compromise
14453 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
14454 generic type-checking code. */
14455 if (section_type == SHT_MIPS_DWARF)
14456 section_type = SHT_PROGBITS;
14457
cca86cc8
SC
14458 obj_elf_change_section (section_name, section_type, section_flag,
14459 section_entry_size, 0, 0, 0);
a816d1ed
AO
14460
14461 if (now_seg->name != section_name)
14462 free (section_name);
cca86cc8 14463}
252b5132
RH
14464
14465void
17a2f251 14466mips_enable_auto_align (void)
252b5132
RH
14467{
14468 auto_align = 1;
14469}
14470
14471static void
17a2f251 14472s_cons (int log_size)
252b5132 14473{
a8dbcb85
TS
14474 segment_info_type *si = seg_info (now_seg);
14475 struct insn_label_list *l = si->label_list;
252b5132 14476
7d10b47d 14477 mips_emit_delays ();
252b5132 14478 if (log_size > 0 && auto_align)
462427c4 14479 mips_align (log_size, 0, l);
252b5132 14480 cons (1 << log_size);
a1facbec 14481 mips_clear_insn_labels ();
252b5132
RH
14482}
14483
14484static void
17a2f251 14485s_float_cons (int type)
252b5132 14486{
a8dbcb85
TS
14487 segment_info_type *si = seg_info (now_seg);
14488 struct insn_label_list *l = si->label_list;
252b5132 14489
7d10b47d 14490 mips_emit_delays ();
252b5132
RH
14491
14492 if (auto_align)
49309057
ILT
14493 {
14494 if (type == 'd')
462427c4 14495 mips_align (3, 0, l);
49309057 14496 else
462427c4 14497 mips_align (2, 0, l);
49309057 14498 }
252b5132 14499
252b5132 14500 float_cons (type);
a1facbec 14501 mips_clear_insn_labels ();
252b5132
RH
14502}
14503
14504/* Handle .globl. We need to override it because on Irix 5 you are
14505 permitted to say
14506 .globl foo .text
14507 where foo is an undefined symbol, to mean that foo should be
14508 considered to be the address of a function. */
14509
14510static void
17a2f251 14511s_mips_globl (int x ATTRIBUTE_UNUSED)
252b5132
RH
14512{
14513 char *name;
14514 int c;
14515 symbolS *symbolP;
14516 flagword flag;
14517
8a06b769 14518 do
252b5132 14519 {
8a06b769 14520 name = input_line_pointer;
252b5132 14521 c = get_symbol_end ();
8a06b769
TS
14522 symbolP = symbol_find_or_make (name);
14523 S_SET_EXTERNAL (symbolP);
14524
252b5132 14525 *input_line_pointer = c;
8a06b769 14526 SKIP_WHITESPACE ();
252b5132 14527
8a06b769
TS
14528 /* On Irix 5, every global symbol that is not explicitly labelled as
14529 being a function is apparently labelled as being an object. */
14530 flag = BSF_OBJECT;
252b5132 14531
8a06b769
TS
14532 if (!is_end_of_line[(unsigned char) *input_line_pointer]
14533 && (*input_line_pointer != ','))
14534 {
14535 char *secname;
14536 asection *sec;
14537
14538 secname = input_line_pointer;
14539 c = get_symbol_end ();
14540 sec = bfd_get_section_by_name (stdoutput, secname);
14541 if (sec == NULL)
14542 as_bad (_("%s: no such section"), secname);
14543 *input_line_pointer = c;
14544
14545 if (sec != NULL && (sec->flags & SEC_CODE) != 0)
14546 flag = BSF_FUNCTION;
14547 }
14548
14549 symbol_get_bfdsym (symbolP)->flags |= flag;
14550
14551 c = *input_line_pointer;
14552 if (c == ',')
14553 {
14554 input_line_pointer++;
14555 SKIP_WHITESPACE ();
14556 if (is_end_of_line[(unsigned char) *input_line_pointer])
14557 c = '\n';
14558 }
14559 }
14560 while (c == ',');
252b5132 14561
252b5132
RH
14562 demand_empty_rest_of_line ();
14563}
14564
14565static void
17a2f251 14566s_option (int x ATTRIBUTE_UNUSED)
252b5132
RH
14567{
14568 char *opt;
14569 char c;
14570
14571 opt = input_line_pointer;
14572 c = get_symbol_end ();
14573
14574 if (*opt == 'O')
14575 {
14576 /* FIXME: What does this mean? */
14577 }
14578 else if (strncmp (opt, "pic", 3) == 0)
14579 {
14580 int i;
14581
14582 i = atoi (opt + 3);
14583 if (i == 0)
14584 mips_pic = NO_PIC;
14585 else if (i == 2)
143d77c5 14586 {
8b828383 14587 mips_pic = SVR4_PIC;
143d77c5
EC
14588 mips_abicalls = TRUE;
14589 }
252b5132
RH
14590 else
14591 as_bad (_(".option pic%d not supported"), i);
14592
4d0d148d 14593 if (mips_pic == SVR4_PIC)
252b5132
RH
14594 {
14595 if (g_switch_seen && g_switch_value != 0)
14596 as_warn (_("-G may not be used with SVR4 PIC code"));
14597 g_switch_value = 0;
14598 bfd_set_gp_size (stdoutput, 0);
14599 }
14600 }
14601 else
14602 as_warn (_("Unrecognized option \"%s\""), opt);
14603
14604 *input_line_pointer = c;
14605 demand_empty_rest_of_line ();
14606}
14607
14608/* This structure is used to hold a stack of .set values. */
14609
e972090a
NC
14610struct mips_option_stack
14611{
252b5132
RH
14612 struct mips_option_stack *next;
14613 struct mips_set_options options;
14614};
14615
14616static struct mips_option_stack *mips_opts_stack;
14617
14618/* Handle the .set pseudo-op. */
14619
14620static void
17a2f251 14621s_mipsset (int x ATTRIBUTE_UNUSED)
252b5132
RH
14622{
14623 char *name = input_line_pointer, ch;
c6278170 14624 const struct mips_ase *ase;
252b5132
RH
14625
14626 while (!is_end_of_line[(unsigned char) *input_line_pointer])
f9419b05 14627 ++input_line_pointer;
252b5132
RH
14628 ch = *input_line_pointer;
14629 *input_line_pointer = '\0';
14630
14631 if (strcmp (name, "reorder") == 0)
14632 {
7d10b47d
RS
14633 if (mips_opts.noreorder)
14634 end_noreorder ();
252b5132
RH
14635 }
14636 else if (strcmp (name, "noreorder") == 0)
14637 {
7d10b47d
RS
14638 if (!mips_opts.noreorder)
14639 start_noreorder ();
252b5132 14640 }
741fe287
MR
14641 else if (strncmp (name, "at=", 3) == 0)
14642 {
14643 char *s = name + 3;
14644
14645 if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, &mips_opts.at))
14646 as_bad (_("Unrecognized register name `%s'"), s);
14647 }
252b5132
RH
14648 else if (strcmp (name, "at") == 0)
14649 {
741fe287 14650 mips_opts.at = ATREG;
252b5132
RH
14651 }
14652 else if (strcmp (name, "noat") == 0)
14653 {
741fe287 14654 mips_opts.at = ZERO;
252b5132
RH
14655 }
14656 else if (strcmp (name, "macro") == 0)
14657 {
14658 mips_opts.warn_about_macros = 0;
14659 }
14660 else if (strcmp (name, "nomacro") == 0)
14661 {
14662 if (mips_opts.noreorder == 0)
14663 as_bad (_("`noreorder' must be set before `nomacro'"));
14664 mips_opts.warn_about_macros = 1;
14665 }
14666 else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0)
14667 {
14668 mips_opts.nomove = 0;
14669 }
14670 else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0)
14671 {
14672 mips_opts.nomove = 1;
14673 }
14674 else if (strcmp (name, "bopt") == 0)
14675 {
14676 mips_opts.nobopt = 0;
14677 }
14678 else if (strcmp (name, "nobopt") == 0)
14679 {
14680 mips_opts.nobopt = 1;
14681 }
ad3fea08
TS
14682 else if (strcmp (name, "gp=default") == 0)
14683 mips_opts.gp32 = file_mips_gp32;
14684 else if (strcmp (name, "gp=32") == 0)
14685 mips_opts.gp32 = 1;
14686 else if (strcmp (name, "gp=64") == 0)
14687 {
14688 if (!ISA_HAS_64BIT_REGS (mips_opts.isa))
20203fb9 14689 as_warn (_("%s isa does not support 64-bit registers"),
ad3fea08
TS
14690 mips_cpu_info_from_isa (mips_opts.isa)->name);
14691 mips_opts.gp32 = 0;
14692 }
14693 else if (strcmp (name, "fp=default") == 0)
14694 mips_opts.fp32 = file_mips_fp32;
14695 else if (strcmp (name, "fp=32") == 0)
14696 mips_opts.fp32 = 1;
14697 else if (strcmp (name, "fp=64") == 0)
14698 {
14699 if (!ISA_HAS_64BIT_FPRS (mips_opts.isa))
20203fb9 14700 as_warn (_("%s isa does not support 64-bit floating point registers"),
ad3fea08
TS
14701 mips_cpu_info_from_isa (mips_opts.isa)->name);
14702 mips_opts.fp32 = 0;
14703 }
037b32b9
AN
14704 else if (strcmp (name, "softfloat") == 0)
14705 mips_opts.soft_float = 1;
14706 else if (strcmp (name, "hardfloat") == 0)
14707 mips_opts.soft_float = 0;
14708 else if (strcmp (name, "singlefloat") == 0)
14709 mips_opts.single_float = 1;
14710 else if (strcmp (name, "doublefloat") == 0)
14711 mips_opts.single_float = 0;
252b5132
RH
14712 else if (strcmp (name, "mips16") == 0
14713 || strcmp (name, "MIPS-16") == 0)
df58fc94
RS
14714 {
14715 if (mips_opts.micromips == 1)
14716 as_fatal (_("`mips16' cannot be used with `micromips'"));
14717 mips_opts.mips16 = 1;
14718 }
252b5132
RH
14719 else if (strcmp (name, "nomips16") == 0
14720 || strcmp (name, "noMIPS-16") == 0)
14721 mips_opts.mips16 = 0;
df58fc94
RS
14722 else if (strcmp (name, "micromips") == 0)
14723 {
14724 if (mips_opts.mips16 == 1)
14725 as_fatal (_("`micromips' cannot be used with `mips16'"));
14726 mips_opts.micromips = 1;
14727 }
14728 else if (strcmp (name, "nomicromips") == 0)
14729 mips_opts.micromips = 0;
c6278170
RS
14730 else if (name[0] == 'n'
14731 && name[1] == 'o'
14732 && (ase = mips_lookup_ase (name + 2)))
14733 mips_set_ase (ase, FALSE);
14734 else if ((ase = mips_lookup_ase (name)))
14735 mips_set_ase (ase, TRUE);
1a2c1fad 14736 else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0)
252b5132 14737 {
af7ee8bf 14738 int reset = 0;
252b5132 14739
1a2c1fad
CD
14740 /* Permit the user to change the ISA and architecture on the fly.
14741 Needless to say, misuse can cause serious problems. */
81a21e38 14742 if (strcmp (name, "mips0") == 0 || strcmp (name, "arch=default") == 0)
af7ee8bf
CD
14743 {
14744 reset = 1;
14745 mips_opts.isa = file_mips_isa;
1a2c1fad 14746 mips_opts.arch = file_mips_arch;
1a2c1fad
CD
14747 }
14748 else if (strncmp (name, "arch=", 5) == 0)
14749 {
14750 const struct mips_cpu_info *p;
14751
14752 p = mips_parse_cpu("internal use", name + 5);
14753 if (!p)
14754 as_bad (_("unknown architecture %s"), name + 5);
14755 else
14756 {
14757 mips_opts.arch = p->cpu;
14758 mips_opts.isa = p->isa;
14759 }
14760 }
81a21e38
TS
14761 else if (strncmp (name, "mips", 4) == 0)
14762 {
14763 const struct mips_cpu_info *p;
14764
14765 p = mips_parse_cpu("internal use", name);
14766 if (!p)
14767 as_bad (_("unknown ISA level %s"), name + 4);
14768 else
14769 {
14770 mips_opts.arch = p->cpu;
14771 mips_opts.isa = p->isa;
14772 }
14773 }
af7ee8bf 14774 else
81a21e38 14775 as_bad (_("unknown ISA or architecture %s"), name);
af7ee8bf
CD
14776
14777 switch (mips_opts.isa)
98d3f06f
KH
14778 {
14779 case 0:
98d3f06f 14780 break;
af7ee8bf
CD
14781 case ISA_MIPS1:
14782 case ISA_MIPS2:
14783 case ISA_MIPS32:
14784 case ISA_MIPS32R2:
98d3f06f
KH
14785 mips_opts.gp32 = 1;
14786 mips_opts.fp32 = 1;
14787 break;
af7ee8bf
CD
14788 case ISA_MIPS3:
14789 case ISA_MIPS4:
14790 case ISA_MIPS5:
14791 case ISA_MIPS64:
5f74bc13 14792 case ISA_MIPS64R2:
98d3f06f 14793 mips_opts.gp32 = 0;
e407c74b
NC
14794 if (mips_opts.arch == CPU_R5900)
14795 {
14796 mips_opts.fp32 = 1;
14797 }
14798 else
14799 {
98d3f06f 14800 mips_opts.fp32 = 0;
e407c74b 14801 }
98d3f06f
KH
14802 break;
14803 default:
14804 as_bad (_("unknown ISA level %s"), name + 4);
14805 break;
14806 }
af7ee8bf 14807 if (reset)
98d3f06f 14808 {
af7ee8bf
CD
14809 mips_opts.gp32 = file_mips_gp32;
14810 mips_opts.fp32 = file_mips_fp32;
98d3f06f 14811 }
252b5132
RH
14812 }
14813 else if (strcmp (name, "autoextend") == 0)
14814 mips_opts.noautoextend = 0;
14815 else if (strcmp (name, "noautoextend") == 0)
14816 mips_opts.noautoextend = 1;
833794fc
MR
14817 else if (strcmp (name, "insn32") == 0)
14818 mips_opts.insn32 = TRUE;
14819 else if (strcmp (name, "noinsn32") == 0)
14820 mips_opts.insn32 = FALSE;
252b5132
RH
14821 else if (strcmp (name, "push") == 0)
14822 {
14823 struct mips_option_stack *s;
14824
14825 s = (struct mips_option_stack *) xmalloc (sizeof *s);
14826 s->next = mips_opts_stack;
14827 s->options = mips_opts;
14828 mips_opts_stack = s;
14829 }
14830 else if (strcmp (name, "pop") == 0)
14831 {
14832 struct mips_option_stack *s;
14833
14834 s = mips_opts_stack;
14835 if (s == NULL)
14836 as_bad (_(".set pop with no .set push"));
14837 else
14838 {
14839 /* If we're changing the reorder mode we need to handle
14840 delay slots correctly. */
14841 if (s->options.noreorder && ! mips_opts.noreorder)
7d10b47d 14842 start_noreorder ();
252b5132 14843 else if (! s->options.noreorder && mips_opts.noreorder)
7d10b47d 14844 end_noreorder ();
252b5132
RH
14845
14846 mips_opts = s->options;
14847 mips_opts_stack = s->next;
14848 free (s);
14849 }
14850 }
aed1a261
RS
14851 else if (strcmp (name, "sym32") == 0)
14852 mips_opts.sym32 = TRUE;
14853 else if (strcmp (name, "nosym32") == 0)
14854 mips_opts.sym32 = FALSE;
e6559e01
JM
14855 else if (strchr (name, ','))
14856 {
14857 /* Generic ".set" directive; use the generic handler. */
14858 *input_line_pointer = ch;
14859 input_line_pointer = name;
14860 s_set (0);
14861 return;
14862 }
252b5132
RH
14863 else
14864 {
14865 as_warn (_("Tried to set unrecognized symbol: %s\n"), name);
14866 }
c6278170 14867 mips_check_isa_supports_ases ();
252b5132
RH
14868 *input_line_pointer = ch;
14869 demand_empty_rest_of_line ();
14870}
14871
14872/* Handle the .abicalls pseudo-op. I believe this is equivalent to
14873 .option pic2. It means to generate SVR4 PIC calls. */
14874
14875static void
17a2f251 14876s_abicalls (int ignore ATTRIBUTE_UNUSED)
252b5132
RH
14877{
14878 mips_pic = SVR4_PIC;
143d77c5 14879 mips_abicalls = TRUE;
4d0d148d
TS
14880
14881 if (g_switch_seen && g_switch_value != 0)
14882 as_warn (_("-G may not be used with SVR4 PIC code"));
14883 g_switch_value = 0;
14884
252b5132
RH
14885 bfd_set_gp_size (stdoutput, 0);
14886 demand_empty_rest_of_line ();
14887}
14888
14889/* Handle the .cpload pseudo-op. This is used when generating SVR4
14890 PIC code. It sets the $gp register for the function based on the
14891 function address, which is in the register named in the argument.
14892 This uses a relocation against _gp_disp, which is handled specially
14893 by the linker. The result is:
14894 lui $gp,%hi(_gp_disp)
14895 addiu $gp,$gp,%lo(_gp_disp)
14896 addu $gp,$gp,.cpload argument
aa6975fb
ILT
14897 The .cpload argument is normally $25 == $t9.
14898
14899 The -mno-shared option changes this to:
bbe506e8
TS
14900 lui $gp,%hi(__gnu_local_gp)
14901 addiu $gp,$gp,%lo(__gnu_local_gp)
aa6975fb
ILT
14902 and the argument is ignored. This saves an instruction, but the
14903 resulting code is not position independent; it uses an absolute
bbe506e8
TS
14904 address for __gnu_local_gp. Thus code assembled with -mno-shared
14905 can go into an ordinary executable, but not into a shared library. */
252b5132
RH
14906
14907static void
17a2f251 14908s_cpload (int ignore ATTRIBUTE_UNUSED)
252b5132
RH
14909{
14910 expressionS ex;
aa6975fb
ILT
14911 int reg;
14912 int in_shared;
252b5132 14913
6478892d
TS
14914 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
14915 .cpload is ignored. */
14916 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
252b5132
RH
14917 {
14918 s_ignore (0);
14919 return;
14920 }
14921
a276b80c
MR
14922 if (mips_opts.mips16)
14923 {
14924 as_bad (_("%s not supported in MIPS16 mode"), ".cpload");
14925 ignore_rest_of_line ();
14926 return;
14927 }
14928
d3ecfc59 14929 /* .cpload should be in a .set noreorder section. */
252b5132
RH
14930 if (mips_opts.noreorder == 0)
14931 as_warn (_(".cpload not in noreorder section"));
14932
aa6975fb
ILT
14933 reg = tc_get_register (0);
14934
14935 /* If we need to produce a 64-bit address, we are better off using
14936 the default instruction sequence. */
aed1a261 14937 in_shared = mips_in_shared || HAVE_64BIT_SYMBOLS;
aa6975fb 14938
252b5132 14939 ex.X_op = O_symbol;
bbe506e8
TS
14940 ex.X_add_symbol = symbol_find_or_make (in_shared ? "_gp_disp" :
14941 "__gnu_local_gp");
252b5132
RH
14942 ex.X_op_symbol = NULL;
14943 ex.X_add_number = 0;
14944
14945 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
49309057 14946 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
252b5132 14947
8a75745d
MR
14948 mips_mark_labels ();
14949 mips_assembling_insn = TRUE;
14950
584892a6 14951 macro_start ();
67c0d1eb
RS
14952 macro_build_lui (&ex, mips_gp_register);
14953 macro_build (&ex, "addiu", "t,r,j", mips_gp_register,
17a2f251 14954 mips_gp_register, BFD_RELOC_LO16);
aa6975fb
ILT
14955 if (in_shared)
14956 macro_build (NULL, "addu", "d,v,t", mips_gp_register,
14957 mips_gp_register, reg);
584892a6 14958 macro_end ();
252b5132 14959
8a75745d 14960 mips_assembling_insn = FALSE;
252b5132
RH
14961 demand_empty_rest_of_line ();
14962}
14963
6478892d
TS
14964/* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
14965 .cpsetup $reg1, offset|$reg2, label
14966
14967 If offset is given, this results in:
14968 sd $gp, offset($sp)
956cd1d6 14969 lui $gp, %hi(%neg(%gp_rel(label)))
698b7d9d
TS
14970 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
14971 daddu $gp, $gp, $reg1
6478892d
TS
14972
14973 If $reg2 is given, this results in:
14974 daddu $reg2, $gp, $0
956cd1d6 14975 lui $gp, %hi(%neg(%gp_rel(label)))
698b7d9d
TS
14976 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
14977 daddu $gp, $gp, $reg1
aa6975fb
ILT
14978 $reg1 is normally $25 == $t9.
14979
14980 The -mno-shared option replaces the last three instructions with
14981 lui $gp,%hi(_gp)
54f4ddb3 14982 addiu $gp,$gp,%lo(_gp) */
aa6975fb 14983
6478892d 14984static void
17a2f251 14985s_cpsetup (int ignore ATTRIBUTE_UNUSED)
6478892d
TS
14986{
14987 expressionS ex_off;
14988 expressionS ex_sym;
14989 int reg1;
6478892d 14990
8586fc66 14991 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
6478892d
TS
14992 We also need NewABI support. */
14993 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
14994 {
14995 s_ignore (0);
14996 return;
14997 }
14998
a276b80c
MR
14999 if (mips_opts.mips16)
15000 {
15001 as_bad (_("%s not supported in MIPS16 mode"), ".cpsetup");
15002 ignore_rest_of_line ();
15003 return;
15004 }
15005
6478892d
TS
15006 reg1 = tc_get_register (0);
15007 SKIP_WHITESPACE ();
15008 if (*input_line_pointer != ',')
15009 {
15010 as_bad (_("missing argument separator ',' for .cpsetup"));
15011 return;
15012 }
15013 else
80245285 15014 ++input_line_pointer;
6478892d
TS
15015 SKIP_WHITESPACE ();
15016 if (*input_line_pointer == '$')
80245285
TS
15017 {
15018 mips_cpreturn_register = tc_get_register (0);
15019 mips_cpreturn_offset = -1;
15020 }
6478892d 15021 else
80245285
TS
15022 {
15023 mips_cpreturn_offset = get_absolute_expression ();
15024 mips_cpreturn_register = -1;
15025 }
6478892d
TS
15026 SKIP_WHITESPACE ();
15027 if (*input_line_pointer != ',')
15028 {
15029 as_bad (_("missing argument separator ',' for .cpsetup"));
15030 return;
15031 }
15032 else
f9419b05 15033 ++input_line_pointer;
6478892d 15034 SKIP_WHITESPACE ();
f21f8242 15035 expression (&ex_sym);
6478892d 15036
8a75745d
MR
15037 mips_mark_labels ();
15038 mips_assembling_insn = TRUE;
15039
584892a6 15040 macro_start ();
6478892d
TS
15041 if (mips_cpreturn_register == -1)
15042 {
15043 ex_off.X_op = O_constant;
15044 ex_off.X_add_symbol = NULL;
15045 ex_off.X_op_symbol = NULL;
15046 ex_off.X_add_number = mips_cpreturn_offset;
15047
67c0d1eb 15048 macro_build (&ex_off, "sd", "t,o(b)", mips_gp_register,
17a2f251 15049 BFD_RELOC_LO16, SP);
6478892d
TS
15050 }
15051 else
67c0d1eb 15052 macro_build (NULL, "daddu", "d,v,t", mips_cpreturn_register,
17a2f251 15053 mips_gp_register, 0);
6478892d 15054
aed1a261 15055 if (mips_in_shared || HAVE_64BIT_SYMBOLS)
aa6975fb 15056 {
df58fc94 15057 macro_build (&ex_sym, "lui", LUI_FMT, mips_gp_register,
aa6975fb
ILT
15058 -1, BFD_RELOC_GPREL16, BFD_RELOC_MIPS_SUB,
15059 BFD_RELOC_HI16_S);
15060
15061 macro_build (&ex_sym, "addiu", "t,r,j", mips_gp_register,
15062 mips_gp_register, -1, BFD_RELOC_GPREL16,
15063 BFD_RELOC_MIPS_SUB, BFD_RELOC_LO16);
15064
15065 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register,
15066 mips_gp_register, reg1);
15067 }
15068 else
15069 {
15070 expressionS ex;
15071
15072 ex.X_op = O_symbol;
4184909a 15073 ex.X_add_symbol = symbol_find_or_make ("__gnu_local_gp");
aa6975fb
ILT
15074 ex.X_op_symbol = NULL;
15075 ex.X_add_number = 0;
6e1304d8 15076
aa6975fb
ILT
15077 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
15078 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
15079
15080 macro_build_lui (&ex, mips_gp_register);
15081 macro_build (&ex, "addiu", "t,r,j", mips_gp_register,
15082 mips_gp_register, BFD_RELOC_LO16);
15083 }
f21f8242 15084
584892a6 15085 macro_end ();
6478892d 15086
8a75745d 15087 mips_assembling_insn = FALSE;
6478892d
TS
15088 demand_empty_rest_of_line ();
15089}
15090
15091static void
17a2f251 15092s_cplocal (int ignore ATTRIBUTE_UNUSED)
6478892d
TS
15093{
15094 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
54f4ddb3 15095 .cplocal is ignored. */
6478892d
TS
15096 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
15097 {
15098 s_ignore (0);
15099 return;
15100 }
15101
a276b80c
MR
15102 if (mips_opts.mips16)
15103 {
15104 as_bad (_("%s not supported in MIPS16 mode"), ".cplocal");
15105 ignore_rest_of_line ();
15106 return;
15107 }
15108
6478892d 15109 mips_gp_register = tc_get_register (0);
85b51719 15110 demand_empty_rest_of_line ();
6478892d
TS
15111}
15112
252b5132
RH
15113/* Handle the .cprestore pseudo-op. This stores $gp into a given
15114 offset from $sp. The offset is remembered, and after making a PIC
15115 call $gp is restored from that location. */
15116
15117static void
17a2f251 15118s_cprestore (int ignore ATTRIBUTE_UNUSED)
252b5132
RH
15119{
15120 expressionS ex;
252b5132 15121
6478892d 15122 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
c9914766 15123 .cprestore is ignored. */
6478892d 15124 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
252b5132
RH
15125 {
15126 s_ignore (0);
15127 return;
15128 }
15129
a276b80c
MR
15130 if (mips_opts.mips16)
15131 {
15132 as_bad (_("%s not supported in MIPS16 mode"), ".cprestore");
15133 ignore_rest_of_line ();
15134 return;
15135 }
15136
252b5132 15137 mips_cprestore_offset = get_absolute_expression ();
7a621144 15138 mips_cprestore_valid = 1;
252b5132
RH
15139
15140 ex.X_op = O_constant;
15141 ex.X_add_symbol = NULL;
15142 ex.X_op_symbol = NULL;
15143 ex.X_add_number = mips_cprestore_offset;
15144
8a75745d
MR
15145 mips_mark_labels ();
15146 mips_assembling_insn = TRUE;
15147
584892a6 15148 macro_start ();
67c0d1eb
RS
15149 macro_build_ldst_constoffset (&ex, ADDRESS_STORE_INSN, mips_gp_register,
15150 SP, HAVE_64BIT_ADDRESSES);
584892a6 15151 macro_end ();
252b5132 15152
8a75745d 15153 mips_assembling_insn = FALSE;
252b5132
RH
15154 demand_empty_rest_of_line ();
15155}
15156
6478892d 15157/* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
67c1ffbe 15158 was given in the preceding .cpsetup, it results in:
6478892d 15159 ld $gp, offset($sp)
76b3015f 15160
6478892d 15161 If a register $reg2 was given there, it results in:
54f4ddb3
TS
15162 daddu $gp, $reg2, $0 */
15163
6478892d 15164static void
17a2f251 15165s_cpreturn (int ignore ATTRIBUTE_UNUSED)
6478892d
TS
15166{
15167 expressionS ex;
6478892d
TS
15168
15169 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
15170 We also need NewABI support. */
15171 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
15172 {
15173 s_ignore (0);
15174 return;
15175 }
15176
a276b80c
MR
15177 if (mips_opts.mips16)
15178 {
15179 as_bad (_("%s not supported in MIPS16 mode"), ".cpreturn");
15180 ignore_rest_of_line ();
15181 return;
15182 }
15183
8a75745d
MR
15184 mips_mark_labels ();
15185 mips_assembling_insn = TRUE;
15186
584892a6 15187 macro_start ();
6478892d
TS
15188 if (mips_cpreturn_register == -1)
15189 {
15190 ex.X_op = O_constant;
15191 ex.X_add_symbol = NULL;
15192 ex.X_op_symbol = NULL;
15193 ex.X_add_number = mips_cpreturn_offset;
15194
67c0d1eb 15195 macro_build (&ex, "ld", "t,o(b)", mips_gp_register, BFD_RELOC_LO16, SP);
6478892d
TS
15196 }
15197 else
67c0d1eb 15198 macro_build (NULL, "daddu", "d,v,t", mips_gp_register,
17a2f251 15199 mips_cpreturn_register, 0);
584892a6 15200 macro_end ();
6478892d 15201
8a75745d 15202 mips_assembling_insn = FALSE;
6478892d
TS
15203 demand_empty_rest_of_line ();
15204}
15205
d0f13682
CLT
15206/* Handle a .dtprelword, .dtpreldword, .tprelword, or .tpreldword
15207 pseudo-op; DIRSTR says which. The pseudo-op generates a BYTES-size
15208 DTP- or TP-relative relocation of type RTYPE, for use in either DWARF
15209 debug information or MIPS16 TLS. */
741d6ea8
JM
15210
15211static void
d0f13682
CLT
15212s_tls_rel_directive (const size_t bytes, const char *dirstr,
15213 bfd_reloc_code_real_type rtype)
741d6ea8
JM
15214{
15215 expressionS ex;
15216 char *p;
15217
15218 expression (&ex);
15219
15220 if (ex.X_op != O_symbol)
15221 {
d0f13682 15222 as_bad (_("Unsupported use of %s"), dirstr);
741d6ea8
JM
15223 ignore_rest_of_line ();
15224 }
15225
15226 p = frag_more (bytes);
15227 md_number_to_chars (p, 0, bytes);
d0f13682 15228 fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, FALSE, rtype);
741d6ea8 15229 demand_empty_rest_of_line ();
de64cffd 15230 mips_clear_insn_labels ();
741d6ea8
JM
15231}
15232
15233/* Handle .dtprelword. */
15234
15235static void
15236s_dtprelword (int ignore ATTRIBUTE_UNUSED)
15237{
d0f13682 15238 s_tls_rel_directive (4, ".dtprelword", BFD_RELOC_MIPS_TLS_DTPREL32);
741d6ea8
JM
15239}
15240
15241/* Handle .dtpreldword. */
15242
15243static void
15244s_dtpreldword (int ignore ATTRIBUTE_UNUSED)
15245{
d0f13682
CLT
15246 s_tls_rel_directive (8, ".dtpreldword", BFD_RELOC_MIPS_TLS_DTPREL64);
15247}
15248
15249/* Handle .tprelword. */
15250
15251static void
15252s_tprelword (int ignore ATTRIBUTE_UNUSED)
15253{
15254 s_tls_rel_directive (4, ".tprelword", BFD_RELOC_MIPS_TLS_TPREL32);
15255}
15256
15257/* Handle .tpreldword. */
15258
15259static void
15260s_tpreldword (int ignore ATTRIBUTE_UNUSED)
15261{
15262 s_tls_rel_directive (8, ".tpreldword", BFD_RELOC_MIPS_TLS_TPREL64);
741d6ea8
JM
15263}
15264
6478892d
TS
15265/* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
15266 code. It sets the offset to use in gp_rel relocations. */
15267
15268static void
17a2f251 15269s_gpvalue (int ignore ATTRIBUTE_UNUSED)
6478892d
TS
15270{
15271 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
15272 We also need NewABI support. */
15273 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
15274 {
15275 s_ignore (0);
15276 return;
15277 }
15278
def2e0dd 15279 mips_gprel_offset = get_absolute_expression ();
6478892d
TS
15280
15281 demand_empty_rest_of_line ();
15282}
15283
252b5132
RH
15284/* Handle the .gpword pseudo-op. This is used when generating PIC
15285 code. It generates a 32 bit GP relative reloc. */
15286
15287static void
17a2f251 15288s_gpword (int ignore ATTRIBUTE_UNUSED)
252b5132 15289{
a8dbcb85
TS
15290 segment_info_type *si;
15291 struct insn_label_list *l;
252b5132
RH
15292 expressionS ex;
15293 char *p;
15294
15295 /* When not generating PIC code, this is treated as .word. */
15296 if (mips_pic != SVR4_PIC)
15297 {
15298 s_cons (2);
15299 return;
15300 }
15301
a8dbcb85
TS
15302 si = seg_info (now_seg);
15303 l = si->label_list;
7d10b47d 15304 mips_emit_delays ();
252b5132 15305 if (auto_align)
462427c4 15306 mips_align (2, 0, l);
252b5132
RH
15307
15308 expression (&ex);
a1facbec 15309 mips_clear_insn_labels ();
252b5132
RH
15310
15311 if (ex.X_op != O_symbol || ex.X_add_number != 0)
15312 {
15313 as_bad (_("Unsupported use of .gpword"));
15314 ignore_rest_of_line ();
15315 }
15316
15317 p = frag_more (4);
17a2f251 15318 md_number_to_chars (p, 0, 4);
b34976b6 15319 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
cdf6fd85 15320 BFD_RELOC_GPREL32);
252b5132
RH
15321
15322 demand_empty_rest_of_line ();
15323}
15324
10181a0d 15325static void
17a2f251 15326s_gpdword (int ignore ATTRIBUTE_UNUSED)
10181a0d 15327{
a8dbcb85
TS
15328 segment_info_type *si;
15329 struct insn_label_list *l;
10181a0d
AO
15330 expressionS ex;
15331 char *p;
15332
15333 /* When not generating PIC code, this is treated as .dword. */
15334 if (mips_pic != SVR4_PIC)
15335 {
15336 s_cons (3);
15337 return;
15338 }
15339
a8dbcb85
TS
15340 si = seg_info (now_seg);
15341 l = si->label_list;
7d10b47d 15342 mips_emit_delays ();
10181a0d 15343 if (auto_align)
462427c4 15344 mips_align (3, 0, l);
10181a0d
AO
15345
15346 expression (&ex);
a1facbec 15347 mips_clear_insn_labels ();
10181a0d
AO
15348
15349 if (ex.X_op != O_symbol || ex.X_add_number != 0)
15350 {
15351 as_bad (_("Unsupported use of .gpdword"));
15352 ignore_rest_of_line ();
15353 }
15354
15355 p = frag_more (8);
17a2f251 15356 md_number_to_chars (p, 0, 8);
a105a300 15357 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
6e1304d8 15358 BFD_RELOC_GPREL32)->fx_tcbit = 1;
10181a0d
AO
15359
15360 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
6e1304d8
RS
15361 fix_new (frag_now, p - frag_now->fr_literal, 8, NULL, 0,
15362 FALSE, BFD_RELOC_64)->fx_tcbit = 1;
10181a0d
AO
15363
15364 demand_empty_rest_of_line ();
15365}
15366
a3f278e2
CM
15367/* Handle the .ehword pseudo-op. This is used when generating unwinding
15368 tables. It generates a R_MIPS_EH reloc. */
15369
15370static void
15371s_ehword (int ignore ATTRIBUTE_UNUSED)
15372{
15373 expressionS ex;
15374 char *p;
15375
15376 mips_emit_delays ();
15377
15378 expression (&ex);
15379 mips_clear_insn_labels ();
15380
15381 if (ex.X_op != O_symbol || ex.X_add_number != 0)
15382 {
15383 as_bad (_("Unsupported use of .ehword"));
15384 ignore_rest_of_line ();
15385 }
15386
15387 p = frag_more (4);
15388 md_number_to_chars (p, 0, 4);
15389 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
15390 BFD_RELOC_MIPS_EH);
15391
15392 demand_empty_rest_of_line ();
15393}
15394
252b5132
RH
15395/* Handle the .cpadd pseudo-op. This is used when dealing with switch
15396 tables in SVR4 PIC code. */
15397
15398static void
17a2f251 15399s_cpadd (int ignore ATTRIBUTE_UNUSED)
252b5132 15400{
252b5132
RH
15401 int reg;
15402
10181a0d
AO
15403 /* This is ignored when not generating SVR4 PIC code. */
15404 if (mips_pic != SVR4_PIC)
252b5132
RH
15405 {
15406 s_ignore (0);
15407 return;
15408 }
15409
8a75745d
MR
15410 mips_mark_labels ();
15411 mips_assembling_insn = TRUE;
15412
252b5132 15413 /* Add $gp to the register named as an argument. */
584892a6 15414 macro_start ();
252b5132 15415 reg = tc_get_register (0);
67c0d1eb 15416 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register);
584892a6 15417 macro_end ();
252b5132 15418
8a75745d 15419 mips_assembling_insn = FALSE;
bdaaa2e1 15420 demand_empty_rest_of_line ();
252b5132
RH
15421}
15422
15423/* Handle the .insn pseudo-op. This marks instruction labels in
df58fc94 15424 mips16/micromips mode. This permits the linker to handle them specially,
252b5132
RH
15425 such as generating jalx instructions when needed. We also make
15426 them odd for the duration of the assembly, in order to generate the
15427 right sort of code. We will make them even in the adjust_symtab
15428 routine, while leaving them marked. This is convenient for the
15429 debugger and the disassembler. The linker knows to make them odd
15430 again. */
15431
15432static void
17a2f251 15433s_insn (int ignore ATTRIBUTE_UNUSED)
252b5132 15434{
df58fc94 15435 mips_mark_labels ();
252b5132
RH
15436
15437 demand_empty_rest_of_line ();
15438}
15439
ba92f887
MR
15440/* Handle the .nan pseudo-op. */
15441
15442static void
15443s_nan (int ignore ATTRIBUTE_UNUSED)
15444{
15445 static const char str_legacy[] = "legacy";
15446 static const char str_2008[] = "2008";
15447 size_t i;
15448
15449 for (i = 0; !is_end_of_line[(unsigned char) input_line_pointer[i]]; i++);
15450
15451 if (i == sizeof (str_2008) - 1
15452 && memcmp (input_line_pointer, str_2008, i) == 0)
15453 mips_flag_nan2008 = TRUE;
15454 else if (i == sizeof (str_legacy) - 1
15455 && memcmp (input_line_pointer, str_legacy, i) == 0)
15456 mips_flag_nan2008 = FALSE;
15457 else
15458 as_bad (_("Bad .nan directive"));
15459
15460 input_line_pointer += i;
15461 demand_empty_rest_of_line ();
15462}
15463
754e2bb9
RS
15464/* Handle a .stab[snd] directive. Ideally these directives would be
15465 implemented in a transparent way, so that removing them would not
15466 have any effect on the generated instructions. However, s_stab
15467 internally changes the section, so in practice we need to decide
15468 now whether the preceding label marks compressed code. We do not
15469 support changing the compression mode of a label after a .stab*
15470 directive, such as in:
15471
15472 foo:
15473 .stabs ...
15474 .set mips16
15475
15476 so the current mode wins. */
252b5132
RH
15477
15478static void
17a2f251 15479s_mips_stab (int type)
252b5132 15480{
754e2bb9 15481 mips_mark_labels ();
252b5132
RH
15482 s_stab (type);
15483}
15484
54f4ddb3 15485/* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */
252b5132
RH
15486
15487static void
17a2f251 15488s_mips_weakext (int ignore ATTRIBUTE_UNUSED)
252b5132
RH
15489{
15490 char *name;
15491 int c;
15492 symbolS *symbolP;
15493 expressionS exp;
15494
15495 name = input_line_pointer;
15496 c = get_symbol_end ();
15497 symbolP = symbol_find_or_make (name);
15498 S_SET_WEAK (symbolP);
15499 *input_line_pointer = c;
15500
15501 SKIP_WHITESPACE ();
15502
15503 if (! is_end_of_line[(unsigned char) *input_line_pointer])
15504 {
15505 if (S_IS_DEFINED (symbolP))
15506 {
20203fb9 15507 as_bad (_("ignoring attempt to redefine symbol %s"),
252b5132
RH
15508 S_GET_NAME (symbolP));
15509 ignore_rest_of_line ();
15510 return;
15511 }
bdaaa2e1 15512
252b5132
RH
15513 if (*input_line_pointer == ',')
15514 {
15515 ++input_line_pointer;
15516 SKIP_WHITESPACE ();
15517 }
bdaaa2e1 15518
252b5132
RH
15519 expression (&exp);
15520 if (exp.X_op != O_symbol)
15521 {
20203fb9 15522 as_bad (_("bad .weakext directive"));
98d3f06f 15523 ignore_rest_of_line ();
252b5132
RH
15524 return;
15525 }
49309057 15526 symbol_set_value_expression (symbolP, &exp);
252b5132
RH
15527 }
15528
15529 demand_empty_rest_of_line ();
15530}
15531
15532/* Parse a register string into a number. Called from the ECOFF code
15533 to parse .frame. The argument is non-zero if this is the frame
15534 register, so that we can record it in mips_frame_reg. */
15535
15536int
17a2f251 15537tc_get_register (int frame)
252b5132 15538{
707bfff6 15539 unsigned int reg;
252b5132
RH
15540
15541 SKIP_WHITESPACE ();
707bfff6
TS
15542 if (! reg_lookup (&input_line_pointer, RWARN | RTYPE_NUM | RTYPE_GP, &reg))
15543 reg = 0;
252b5132 15544 if (frame)
7a621144
DJ
15545 {
15546 mips_frame_reg = reg != 0 ? reg : SP;
15547 mips_frame_reg_valid = 1;
15548 mips_cprestore_valid = 0;
15549 }
252b5132
RH
15550 return reg;
15551}
15552
15553valueT
17a2f251 15554md_section_align (asection *seg, valueT addr)
252b5132
RH
15555{
15556 int align = bfd_get_section_alignment (stdoutput, seg);
15557
f3ded42a
RS
15558 /* We don't need to align ELF sections to the full alignment.
15559 However, Irix 5 may prefer that we align them at least to a 16
15560 byte boundary. We don't bother to align the sections if we
15561 are targeted for an embedded system. */
15562 if (strncmp (TARGET_OS, "elf", 3) == 0)
15563 return addr;
15564 if (align > 4)
15565 align = 4;
252b5132
RH
15566
15567 return ((addr + (1 << align) - 1) & (-1 << align));
15568}
15569
15570/* Utility routine, called from above as well. If called while the
15571 input file is still being read, it's only an approximation. (For
15572 example, a symbol may later become defined which appeared to be
15573 undefined earlier.) */
15574
15575static int
17a2f251 15576nopic_need_relax (symbolS *sym, int before_relaxing)
252b5132
RH
15577{
15578 if (sym == 0)
15579 return 0;
15580
4d0d148d 15581 if (g_switch_value > 0)
252b5132
RH
15582 {
15583 const char *symname;
15584 int change;
15585
c9914766 15586 /* Find out whether this symbol can be referenced off the $gp
252b5132
RH
15587 register. It can be if it is smaller than the -G size or if
15588 it is in the .sdata or .sbss section. Certain symbols can
c9914766 15589 not be referenced off the $gp, although it appears as though
252b5132
RH
15590 they can. */
15591 symname = S_GET_NAME (sym);
15592 if (symname != (const char *) NULL
15593 && (strcmp (symname, "eprol") == 0
15594 || strcmp (symname, "etext") == 0
15595 || strcmp (symname, "_gp") == 0
15596 || strcmp (symname, "edata") == 0
15597 || strcmp (symname, "_fbss") == 0
15598 || strcmp (symname, "_fdata") == 0
15599 || strcmp (symname, "_ftext") == 0
15600 || strcmp (symname, "end") == 0
15601 || strcmp (symname, "_gp_disp") == 0))
15602 change = 1;
15603 else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym))
15604 && (0
15605#ifndef NO_ECOFF_DEBUGGING
49309057
ILT
15606 || (symbol_get_obj (sym)->ecoff_extern_size != 0
15607 && (symbol_get_obj (sym)->ecoff_extern_size
15608 <= g_switch_value))
252b5132
RH
15609#endif
15610 /* We must defer this decision until after the whole
15611 file has been read, since there might be a .extern
15612 after the first use of this symbol. */
15613 || (before_relaxing
15614#ifndef NO_ECOFF_DEBUGGING
49309057 15615 && symbol_get_obj (sym)->ecoff_extern_size == 0
252b5132
RH
15616#endif
15617 && S_GET_VALUE (sym) == 0)
15618 || (S_GET_VALUE (sym) != 0
15619 && S_GET_VALUE (sym) <= g_switch_value)))
15620 change = 0;
15621 else
15622 {
15623 const char *segname;
15624
15625 segname = segment_name (S_GET_SEGMENT (sym));
9c2799c2 15626 gas_assert (strcmp (segname, ".lit8") != 0
252b5132
RH
15627 && strcmp (segname, ".lit4") != 0);
15628 change = (strcmp (segname, ".sdata") != 0
fba2b7f9
GK
15629 && strcmp (segname, ".sbss") != 0
15630 && strncmp (segname, ".sdata.", 7) != 0
d4dc2f22
TS
15631 && strncmp (segname, ".sbss.", 6) != 0
15632 && strncmp (segname, ".gnu.linkonce.sb.", 17) != 0
fba2b7f9 15633 && strncmp (segname, ".gnu.linkonce.s.", 16) != 0);
252b5132
RH
15634 }
15635 return change;
15636 }
15637 else
c9914766 15638 /* We are not optimizing for the $gp register. */
252b5132
RH
15639 return 1;
15640}
15641
5919d012
RS
15642
15643/* Return true if the given symbol should be considered local for SVR4 PIC. */
15644
15645static bfd_boolean
17a2f251 15646pic_need_relax (symbolS *sym, asection *segtype)
5919d012
RS
15647{
15648 asection *symsec;
5919d012
RS
15649
15650 /* Handle the case of a symbol equated to another symbol. */
15651 while (symbol_equated_reloc_p (sym))
15652 {
15653 symbolS *n;
15654
5f0fe04b 15655 /* It's possible to get a loop here in a badly written program. */
5919d012
RS
15656 n = symbol_get_value_expression (sym)->X_add_symbol;
15657 if (n == sym)
15658 break;
15659 sym = n;
15660 }
15661
df1f3cda
DD
15662 if (symbol_section_p (sym))
15663 return TRUE;
15664
5919d012
RS
15665 symsec = S_GET_SEGMENT (sym);
15666
5919d012 15667 /* This must duplicate the test in adjust_reloc_syms. */
45dfa85a
AM
15668 return (!bfd_is_und_section (symsec)
15669 && !bfd_is_abs_section (symsec)
5f0fe04b
TS
15670 && !bfd_is_com_section (symsec)
15671 && !s_is_linkonce (sym, segtype)
5919d012 15672 /* A global or weak symbol is treated as external. */
f3ded42a 15673 && (!S_IS_WEAK (sym) && !S_IS_EXTERNAL (sym)));
5919d012
RS
15674}
15675
15676
252b5132
RH
15677/* Given a mips16 variant frag FRAGP, return non-zero if it needs an
15678 extended opcode. SEC is the section the frag is in. */
15679
15680static int
17a2f251 15681mips16_extended_frag (fragS *fragp, asection *sec, long stretch)
252b5132
RH
15682{
15683 int type;
3994f87e 15684 const struct mips16_immed_operand *op;
252b5132
RH
15685 offsetT val;
15686 int mintiny, maxtiny;
15687 segT symsec;
98aa84af 15688 fragS *sym_frag;
252b5132
RH
15689
15690 if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype))
15691 return 0;
15692 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype))
15693 return 1;
15694
15695 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
15696 op = mips16_immed_operands;
15697 while (op->type != type)
15698 {
15699 ++op;
9c2799c2 15700 gas_assert (op < mips16_immed_operands + MIPS16_NUM_IMMED);
252b5132
RH
15701 }
15702
15703 if (op->unsp)
15704 {
15705 if (type == '<' || type == '>' || type == '[' || type == ']')
15706 {
15707 mintiny = 1;
15708 maxtiny = 1 << op->nbits;
15709 }
15710 else
15711 {
15712 mintiny = 0;
15713 maxtiny = (1 << op->nbits) - 1;
15714 }
15715 }
15716 else
15717 {
15718 mintiny = - (1 << (op->nbits - 1));
15719 maxtiny = (1 << (op->nbits - 1)) - 1;
15720 }
15721
98aa84af 15722 sym_frag = symbol_get_frag (fragp->fr_symbol);
ac62c346 15723 val = S_GET_VALUE (fragp->fr_symbol);
98aa84af 15724 symsec = S_GET_SEGMENT (fragp->fr_symbol);
252b5132
RH
15725
15726 if (op->pcrel)
15727 {
15728 addressT addr;
15729
15730 /* We won't have the section when we are called from
15731 mips_relax_frag. However, we will always have been called
15732 from md_estimate_size_before_relax first. If this is a
15733 branch to a different section, we mark it as such. If SEC is
15734 NULL, and the frag is not marked, then it must be a branch to
15735 the same section. */
15736 if (sec == NULL)
15737 {
15738 if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype))
15739 return 1;
15740 }
15741 else
15742 {
98aa84af 15743 /* Must have been called from md_estimate_size_before_relax. */
252b5132
RH
15744 if (symsec != sec)
15745 {
15746 fragp->fr_subtype =
15747 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
15748
15749 /* FIXME: We should support this, and let the linker
15750 catch branches and loads that are out of range. */
15751 as_bad_where (fragp->fr_file, fragp->fr_line,
15752 _("unsupported PC relative reference to different section"));
15753
15754 return 1;
15755 }
98aa84af
AM
15756 if (fragp != sym_frag && sym_frag->fr_address == 0)
15757 /* Assume non-extended on the first relaxation pass.
15758 The address we have calculated will be bogus if this is
15759 a forward branch to another frag, as the forward frag
15760 will have fr_address == 0. */
15761 return 0;
252b5132
RH
15762 }
15763
15764 /* In this case, we know for sure that the symbol fragment is in
98aa84af
AM
15765 the same section. If the relax_marker of the symbol fragment
15766 differs from the relax_marker of this fragment, we have not
15767 yet adjusted the symbol fragment fr_address. We want to add
252b5132
RH
15768 in STRETCH in order to get a better estimate of the address.
15769 This particularly matters because of the shift bits. */
15770 if (stretch != 0
98aa84af 15771 && sym_frag->relax_marker != fragp->relax_marker)
252b5132
RH
15772 {
15773 fragS *f;
15774
15775 /* Adjust stretch for any alignment frag. Note that if have
15776 been expanding the earlier code, the symbol may be
15777 defined in what appears to be an earlier frag. FIXME:
15778 This doesn't handle the fr_subtype field, which specifies
15779 a maximum number of bytes to skip when doing an
15780 alignment. */
98aa84af 15781 for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next)
252b5132
RH
15782 {
15783 if (f->fr_type == rs_align || f->fr_type == rs_align_code)
15784 {
15785 if (stretch < 0)
15786 stretch = - ((- stretch)
15787 & ~ ((1 << (int) f->fr_offset) - 1));
15788 else
15789 stretch &= ~ ((1 << (int) f->fr_offset) - 1);
15790 if (stretch == 0)
15791 break;
15792 }
15793 }
15794 if (f != NULL)
15795 val += stretch;
15796 }
15797
15798 addr = fragp->fr_address + fragp->fr_fix;
15799
15800 /* The base address rules are complicated. The base address of
15801 a branch is the following instruction. The base address of a
15802 PC relative load or add is the instruction itself, but if it
15803 is in a delay slot (in which case it can not be extended) use
15804 the address of the instruction whose delay slot it is in. */
15805 if (type == 'p' || type == 'q')
15806 {
15807 addr += 2;
15808
15809 /* If we are currently assuming that this frag should be
15810 extended, then, the current address is two bytes
bdaaa2e1 15811 higher. */
252b5132
RH
15812 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
15813 addr += 2;
15814
15815 /* Ignore the low bit in the target, since it will be set
15816 for a text label. */
15817 if ((val & 1) != 0)
15818 --val;
15819 }
15820 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
15821 addr -= 4;
15822 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
15823 addr -= 2;
15824
15825 val -= addr & ~ ((1 << op->shift) - 1);
15826
15827 /* Branch offsets have an implicit 0 in the lowest bit. */
15828 if (type == 'p' || type == 'q')
15829 val /= 2;
15830
15831 /* If any of the shifted bits are set, we must use an extended
15832 opcode. If the address depends on the size of this
15833 instruction, this can lead to a loop, so we arrange to always
15834 use an extended opcode. We only check this when we are in
15835 the main relaxation loop, when SEC is NULL. */
15836 if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL)
15837 {
15838 fragp->fr_subtype =
15839 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
15840 return 1;
15841 }
15842
15843 /* If we are about to mark a frag as extended because the value
15844 is precisely maxtiny + 1, then there is a chance of an
15845 infinite loop as in the following code:
15846 la $4,foo
15847 .skip 1020
15848 .align 2
15849 foo:
15850 In this case when the la is extended, foo is 0x3fc bytes
15851 away, so the la can be shrunk, but then foo is 0x400 away, so
15852 the la must be extended. To avoid this loop, we mark the
15853 frag as extended if it was small, and is about to become
15854 extended with a value of maxtiny + 1. */
15855 if (val == ((maxtiny + 1) << op->shift)
15856 && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)
15857 && sec == NULL)
15858 {
15859 fragp->fr_subtype =
15860 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
15861 return 1;
15862 }
15863 }
15864 else if (symsec != absolute_section && sec != NULL)
15865 as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation"));
15866
15867 if ((val & ((1 << op->shift) - 1)) != 0
15868 || val < (mintiny << op->shift)
15869 || val > (maxtiny << op->shift))
15870 return 1;
15871 else
15872 return 0;
15873}
15874
4a6a3df4
AO
15875/* Compute the length of a branch sequence, and adjust the
15876 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
15877 worst-case length is computed, with UPDATE being used to indicate
15878 whether an unconditional (-1), branch-likely (+1) or regular (0)
15879 branch is to be computed. */
15880static int
17a2f251 15881relaxed_branch_length (fragS *fragp, asection *sec, int update)
4a6a3df4 15882{
b34976b6 15883 bfd_boolean toofar;
4a6a3df4
AO
15884 int length;
15885
15886 if (fragp
15887 && S_IS_DEFINED (fragp->fr_symbol)
15888 && sec == S_GET_SEGMENT (fragp->fr_symbol))
15889 {
15890 addressT addr;
15891 offsetT val;
15892
15893 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
15894
15895 addr = fragp->fr_address + fragp->fr_fix + 4;
15896
15897 val -= addr;
15898
15899 toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2);
15900 }
15901 else if (fragp)
15902 /* If the symbol is not defined or it's in a different segment,
15903 assume the user knows what's going on and emit a short
15904 branch. */
b34976b6 15905 toofar = FALSE;
4a6a3df4 15906 else
b34976b6 15907 toofar = TRUE;
4a6a3df4
AO
15908
15909 if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
15910 fragp->fr_subtype
66b3e8da
MR
15911 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp->fr_subtype),
15912 RELAX_BRANCH_UNCOND (fragp->fr_subtype),
4a6a3df4
AO
15913 RELAX_BRANCH_LIKELY (fragp->fr_subtype),
15914 RELAX_BRANCH_LINK (fragp->fr_subtype),
15915 toofar);
15916
15917 length = 4;
15918 if (toofar)
15919 {
15920 if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0))
15921 length += 8;
15922
15923 if (mips_pic != NO_PIC)
15924 {
15925 /* Additional space for PIC loading of target address. */
15926 length += 8;
15927 if (mips_opts.isa == ISA_MIPS1)
15928 /* Additional space for $at-stabilizing nop. */
15929 length += 4;
15930 }
15931
15932 /* If branch is conditional. */
15933 if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0))
15934 length += 8;
15935 }
b34976b6 15936
4a6a3df4
AO
15937 return length;
15938}
15939
df58fc94
RS
15940/* Compute the length of a branch sequence, and adjust the
15941 RELAX_MICROMIPS_TOOFAR32 bit accordingly. If FRAGP is NULL, the
15942 worst-case length is computed, with UPDATE being used to indicate
15943 whether an unconditional (-1), or regular (0) branch is to be
15944 computed. */
15945
15946static int
15947relaxed_micromips_32bit_branch_length (fragS *fragp, asection *sec, int update)
15948{
15949 bfd_boolean toofar;
15950 int length;
15951
15952 if (fragp
15953 && S_IS_DEFINED (fragp->fr_symbol)
15954 && sec == S_GET_SEGMENT (fragp->fr_symbol))
15955 {
15956 addressT addr;
15957 offsetT val;
15958
15959 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
15960 /* Ignore the low bit in the target, since it will be set
15961 for a text label. */
15962 if ((val & 1) != 0)
15963 --val;
15964
15965 addr = fragp->fr_address + fragp->fr_fix + 4;
15966
15967 val -= addr;
15968
15969 toofar = val < - (0x8000 << 1) || val >= (0x8000 << 1);
15970 }
15971 else if (fragp)
15972 /* If the symbol is not defined or it's in a different segment,
15973 assume the user knows what's going on and emit a short
15974 branch. */
15975 toofar = FALSE;
15976 else
15977 toofar = TRUE;
15978
15979 if (fragp && update
15980 && toofar != RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype))
15981 fragp->fr_subtype = (toofar
15982 ? RELAX_MICROMIPS_MARK_TOOFAR32 (fragp->fr_subtype)
15983 : RELAX_MICROMIPS_CLEAR_TOOFAR32 (fragp->fr_subtype));
15984
15985 length = 4;
15986 if (toofar)
15987 {
15988 bfd_boolean compact_known = fragp != NULL;
15989 bfd_boolean compact = FALSE;
15990 bfd_boolean uncond;
15991
15992 if (compact_known)
15993 compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype);
15994 if (fragp)
15995 uncond = RELAX_MICROMIPS_UNCOND (fragp->fr_subtype);
15996 else
15997 uncond = update < 0;
15998
15999 /* If label is out of range, we turn branch <br>:
16000
16001 <br> label # 4 bytes
16002 0:
16003
16004 into:
16005
16006 j label # 4 bytes
16007 nop # 2 bytes if compact && !PIC
16008 0:
16009 */
16010 if (mips_pic == NO_PIC && (!compact_known || compact))
16011 length += 2;
16012
16013 /* If assembling PIC code, we further turn:
16014
16015 j label # 4 bytes
16016
16017 into:
16018
16019 lw/ld at, %got(label)(gp) # 4 bytes
16020 d/addiu at, %lo(label) # 4 bytes
16021 jr/c at # 2 bytes
16022 */
16023 if (mips_pic != NO_PIC)
16024 length += 6;
16025
16026 /* If branch <br> is conditional, we prepend negated branch <brneg>:
16027
16028 <brneg> 0f # 4 bytes
16029 nop # 2 bytes if !compact
16030 */
16031 if (!uncond)
16032 length += (compact_known && compact) ? 4 : 6;
16033 }
16034
16035 return length;
16036}
16037
16038/* Compute the length of a branch, and adjust the RELAX_MICROMIPS_TOOFAR16
16039 bit accordingly. */
16040
16041static int
16042relaxed_micromips_16bit_branch_length (fragS *fragp, asection *sec, int update)
16043{
16044 bfd_boolean toofar;
16045
df58fc94
RS
16046 if (fragp
16047 && S_IS_DEFINED (fragp->fr_symbol)
16048 && sec == S_GET_SEGMENT (fragp->fr_symbol))
16049 {
16050 addressT addr;
16051 offsetT val;
16052 int type;
16053
16054 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
16055 /* Ignore the low bit in the target, since it will be set
16056 for a text label. */
16057 if ((val & 1) != 0)
16058 --val;
16059
16060 /* Assume this is a 2-byte branch. */
16061 addr = fragp->fr_address + fragp->fr_fix + 2;
16062
16063 /* We try to avoid the infinite loop by not adding 2 more bytes for
16064 long branches. */
16065
16066 val -= addr;
16067
16068 type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype);
16069 if (type == 'D')
16070 toofar = val < - (0x200 << 1) || val >= (0x200 << 1);
16071 else if (type == 'E')
16072 toofar = val < - (0x40 << 1) || val >= (0x40 << 1);
16073 else
16074 abort ();
16075 }
16076 else
16077 /* If the symbol is not defined or it's in a different segment,
16078 we emit a normal 32-bit branch. */
16079 toofar = TRUE;
16080
16081 if (fragp && update
16082 && toofar != RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype))
16083 fragp->fr_subtype
16084 = toofar ? RELAX_MICROMIPS_MARK_TOOFAR16 (fragp->fr_subtype)
16085 : RELAX_MICROMIPS_CLEAR_TOOFAR16 (fragp->fr_subtype);
16086
16087 if (toofar)
16088 return 4;
16089
16090 return 2;
16091}
16092
252b5132
RH
16093/* Estimate the size of a frag before relaxing. Unless this is the
16094 mips16, we are not really relaxing here, and the final size is
16095 encoded in the subtype information. For the mips16, we have to
16096 decide whether we are using an extended opcode or not. */
16097
252b5132 16098int
17a2f251 16099md_estimate_size_before_relax (fragS *fragp, asection *segtype)
252b5132 16100{
5919d012 16101 int change;
252b5132 16102
4a6a3df4
AO
16103 if (RELAX_BRANCH_P (fragp->fr_subtype))
16104 {
16105
b34976b6
AM
16106 fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE);
16107
4a6a3df4
AO
16108 return fragp->fr_var;
16109 }
16110
252b5132 16111 if (RELAX_MIPS16_P (fragp->fr_subtype))
177b4a6a
AO
16112 /* We don't want to modify the EXTENDED bit here; it might get us
16113 into infinite loops. We change it only in mips_relax_frag(). */
16114 return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2);
252b5132 16115
df58fc94
RS
16116 if (RELAX_MICROMIPS_P (fragp->fr_subtype))
16117 {
16118 int length = 4;
16119
16120 if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0)
16121 length = relaxed_micromips_16bit_branch_length (fragp, segtype, FALSE);
16122 if (length == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype))
16123 length = relaxed_micromips_32bit_branch_length (fragp, segtype, FALSE);
16124 fragp->fr_var = length;
16125
16126 return length;
16127 }
16128
252b5132 16129 if (mips_pic == NO_PIC)
5919d012 16130 change = nopic_need_relax (fragp->fr_symbol, 0);
252b5132 16131 else if (mips_pic == SVR4_PIC)
5919d012 16132 change = pic_need_relax (fragp->fr_symbol, segtype);
0a44bf69
RS
16133 else if (mips_pic == VXWORKS_PIC)
16134 /* For vxworks, GOT16 relocations never have a corresponding LO16. */
16135 change = 0;
252b5132
RH
16136 else
16137 abort ();
16138
16139 if (change)
16140 {
4d7206a2 16141 fragp->fr_subtype |= RELAX_USE_SECOND;
4d7206a2 16142 return -RELAX_FIRST (fragp->fr_subtype);
252b5132 16143 }
4d7206a2
RS
16144 else
16145 return -RELAX_SECOND (fragp->fr_subtype);
252b5132
RH
16146}
16147
16148/* This is called to see whether a reloc against a defined symbol
de7e6852 16149 should be converted into a reloc against a section. */
252b5132
RH
16150
16151int
17a2f251 16152mips_fix_adjustable (fixS *fixp)
252b5132 16153{
252b5132
RH
16154 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
16155 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
16156 return 0;
a161fe53 16157
252b5132
RH
16158 if (fixp->fx_addsy == NULL)
16159 return 1;
a161fe53 16160
de7e6852
RS
16161 /* If symbol SYM is in a mergeable section, relocations of the form
16162 SYM + 0 can usually be made section-relative. The mergeable data
16163 is then identified by the section offset rather than by the symbol.
16164
16165 However, if we're generating REL LO16 relocations, the offset is split
16166 between the LO16 and parterning high part relocation. The linker will
16167 need to recalculate the complete offset in order to correctly identify
16168 the merge data.
16169
16170 The linker has traditionally not looked for the parterning high part
16171 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
16172 placed anywhere. Rather than break backwards compatibility by changing
16173 this, it seems better not to force the issue, and instead keep the
16174 original symbol. This will work with either linker behavior. */
738e5348 16175 if ((lo16_reloc_p (fixp->fx_r_type)
704803a9 16176 || reloc_needs_lo_p (fixp->fx_r_type))
de7e6852
RS
16177 && HAVE_IN_PLACE_ADDENDS
16178 && (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_MERGE) != 0)
16179 return 0;
16180
ce70d90a 16181 /* There is no place to store an in-place offset for JALR relocations.
2de39019
CM
16182 Likewise an in-range offset of limited PC-relative relocations may
16183 overflow the in-place relocatable field if recalculated against the
16184 start address of the symbol's containing section. */
ce70d90a 16185 if (HAVE_IN_PLACE_ADDENDS
2de39019
CM
16186 && (limited_pcrel_reloc_p (fixp->fx_r_type)
16187 || jalr_reloc_p (fixp->fx_r_type)))
1180b5a4
RS
16188 return 0;
16189
b314ec0e
RS
16190 /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve
16191 to a floating-point stub. The same is true for non-R_MIPS16_26
16192 relocations against MIPS16 functions; in this case, the stub becomes
16193 the function's canonical address.
16194
16195 Floating-point stubs are stored in unique .mips16.call.* or
16196 .mips16.fn.* sections. If a stub T for function F is in section S,
16197 the first relocation in section S must be against F; this is how the
16198 linker determines the target function. All relocations that might
16199 resolve to T must also be against F. We therefore have the following
16200 restrictions, which are given in an intentionally-redundant way:
16201
16202 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16
16203 symbols.
16204
16205 2. We cannot reduce a stub's relocations against non-MIPS16 symbols
16206 if that stub might be used.
16207
16208 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16
16209 symbols.
16210
16211 4. We cannot reduce a stub's relocations against MIPS16 symbols if
16212 that stub might be used.
16213
16214 There is a further restriction:
16215
df58fc94
RS
16216 5. We cannot reduce jump relocations (R_MIPS_26, R_MIPS16_26 or
16217 R_MICROMIPS_26_S1) against MIPS16 or microMIPS symbols on
16218 targets with in-place addends; the relocation field cannot
b314ec0e
RS
16219 encode the low bit.
16220
df58fc94
RS
16221 For simplicity, we deal with (3)-(4) by not reducing _any_ relocation
16222 against a MIPS16 symbol. We deal with (5) by by not reducing any
16223 such relocations on REL targets.
b314ec0e
RS
16224
16225 We deal with (1)-(2) by saying that, if there's a R_MIPS16_26
16226 relocation against some symbol R, no relocation against R may be
16227 reduced. (Note that this deals with (2) as well as (1) because
16228 relocations against global symbols will never be reduced on ELF
16229 targets.) This approach is a little simpler than trying to detect
16230 stub sections, and gives the "all or nothing" per-symbol consistency
16231 that we have for MIPS16 symbols. */
f3ded42a 16232 if (fixp->fx_subsy == NULL
30c09090 16233 && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp->fx_addsy))
df58fc94
RS
16234 || *symbol_get_tc (fixp->fx_addsy)
16235 || (HAVE_IN_PLACE_ADDENDS
16236 && ELF_ST_IS_MICROMIPS (S_GET_OTHER (fixp->fx_addsy))
16237 && jmp_reloc_p (fixp->fx_r_type))))
252b5132 16238 return 0;
a161fe53 16239
252b5132
RH
16240 return 1;
16241}
16242
16243/* Translate internal representation of relocation info to BFD target
16244 format. */
16245
16246arelent **
17a2f251 16247tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
252b5132
RH
16248{
16249 static arelent *retval[4];
16250 arelent *reloc;
16251 bfd_reloc_code_real_type code;
16252
4b0cff4e
TS
16253 memset (retval, 0, sizeof(retval));
16254 reloc = retval[0] = (arelent *) xcalloc (1, sizeof (arelent));
49309057
ILT
16255 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
16256 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH
16257 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
16258
bad36eac
DJ
16259 if (fixp->fx_pcrel)
16260 {
df58fc94
RS
16261 gas_assert (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2
16262 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1
16263 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1
b47468a6
CM
16264 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1
16265 || fixp->fx_r_type == BFD_RELOC_32_PCREL);
bad36eac
DJ
16266
16267 /* At this point, fx_addnumber is "symbol offset - pcrel address".
16268 Relocations want only the symbol offset. */
16269 reloc->addend = fixp->fx_addnumber + reloc->address;
bad36eac
DJ
16270 }
16271 else
16272 reloc->addend = fixp->fx_addnumber;
252b5132 16273
438c16b8
TS
16274 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
16275 entry to be used in the relocation's section offset. */
16276 if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
252b5132
RH
16277 {
16278 reloc->address = reloc->addend;
16279 reloc->addend = 0;
16280 }
16281
252b5132 16282 code = fixp->fx_r_type;
252b5132 16283
bad36eac 16284 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
252b5132
RH
16285 if (reloc->howto == NULL)
16286 {
16287 as_bad_where (fixp->fx_file, fixp->fx_line,
16288 _("Can not represent %s relocation in this object file format"),
16289 bfd_get_reloc_code_name (code));
16290 retval[0] = NULL;
16291 }
16292
16293 return retval;
16294}
16295
16296/* Relax a machine dependent frag. This returns the amount by which
16297 the current size of the frag should change. */
16298
16299int
17a2f251 16300mips_relax_frag (asection *sec, fragS *fragp, long stretch)
252b5132 16301{
4a6a3df4
AO
16302 if (RELAX_BRANCH_P (fragp->fr_subtype))
16303 {
16304 offsetT old_var = fragp->fr_var;
b34976b6
AM
16305
16306 fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE);
4a6a3df4
AO
16307
16308 return fragp->fr_var - old_var;
16309 }
16310
df58fc94
RS
16311 if (RELAX_MICROMIPS_P (fragp->fr_subtype))
16312 {
16313 offsetT old_var = fragp->fr_var;
16314 offsetT new_var = 4;
16315
16316 if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0)
16317 new_var = relaxed_micromips_16bit_branch_length (fragp, sec, TRUE);
16318 if (new_var == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype))
16319 new_var = relaxed_micromips_32bit_branch_length (fragp, sec, TRUE);
16320 fragp->fr_var = new_var;
16321
16322 return new_var - old_var;
16323 }
16324
252b5132
RH
16325 if (! RELAX_MIPS16_P (fragp->fr_subtype))
16326 return 0;
16327
c4e7957c 16328 if (mips16_extended_frag (fragp, NULL, stretch))
252b5132
RH
16329 {
16330 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
16331 return 0;
16332 fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype);
16333 return 2;
16334 }
16335 else
16336 {
16337 if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
16338 return 0;
16339 fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype);
16340 return -2;
16341 }
16342
16343 return 0;
16344}
16345
16346/* Convert a machine dependent frag. */
16347
16348void
17a2f251 16349md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp)
252b5132 16350{
4a6a3df4
AO
16351 if (RELAX_BRANCH_P (fragp->fr_subtype))
16352 {
4d68580a 16353 char *buf;
4a6a3df4
AO
16354 unsigned long insn;
16355 expressionS exp;
16356 fixS *fixp;
b34976b6 16357
4d68580a
RS
16358 buf = fragp->fr_literal + fragp->fr_fix;
16359 insn = read_insn (buf);
b34976b6 16360
4a6a3df4
AO
16361 if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
16362 {
16363 /* We generate a fixup instead of applying it right now
16364 because, if there are linker relaxations, we're going to
16365 need the relocations. */
16366 exp.X_op = O_symbol;
16367 exp.X_add_symbol = fragp->fr_symbol;
16368 exp.X_add_number = fragp->fr_offset;
16369
4d68580a
RS
16370 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, TRUE,
16371 BFD_RELOC_16_PCREL_S2);
4a6a3df4
AO
16372 fixp->fx_file = fragp->fr_file;
16373 fixp->fx_line = fragp->fr_line;
b34976b6 16374
4d68580a 16375 buf = write_insn (buf, insn);
4a6a3df4
AO
16376 }
16377 else
16378 {
16379 int i;
16380
16381 as_warn_where (fragp->fr_file, fragp->fr_line,
5c4f07ba 16382 _("Relaxed out-of-range branch into a jump"));
4a6a3df4
AO
16383
16384 if (RELAX_BRANCH_UNCOND (fragp->fr_subtype))
16385 goto uncond;
16386
16387 if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype))
16388 {
16389 /* Reverse the branch. */
16390 switch ((insn >> 28) & 0xf)
16391 {
16392 case 4:
3bf0dbfb
MR
16393 /* bc[0-3][tf]l? instructions can have the condition
16394 reversed by tweaking a single TF bit, and their
16395 opcodes all have 0x4???????. */
16396 gas_assert ((insn & 0xf3e00000) == 0x41000000);
4a6a3df4
AO
16397 insn ^= 0x00010000;
16398 break;
16399
16400 case 0:
16401 /* bltz 0x04000000 bgez 0x04010000
54f4ddb3 16402 bltzal 0x04100000 bgezal 0x04110000 */
9c2799c2 16403 gas_assert ((insn & 0xfc0e0000) == 0x04000000);
4a6a3df4
AO
16404 insn ^= 0x00010000;
16405 break;
b34976b6 16406
4a6a3df4
AO
16407 case 1:
16408 /* beq 0x10000000 bne 0x14000000
54f4ddb3 16409 blez 0x18000000 bgtz 0x1c000000 */
4a6a3df4
AO
16410 insn ^= 0x04000000;
16411 break;
16412
16413 default:
16414 abort ();
16415 }
16416 }
16417
16418 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
16419 {
16420 /* Clear the and-link bit. */
9c2799c2 16421 gas_assert ((insn & 0xfc1c0000) == 0x04100000);
4a6a3df4 16422
54f4ddb3
TS
16423 /* bltzal 0x04100000 bgezal 0x04110000
16424 bltzall 0x04120000 bgezall 0x04130000 */
4a6a3df4
AO
16425 insn &= ~0x00100000;
16426 }
16427
16428 /* Branch over the branch (if the branch was likely) or the
16429 full jump (not likely case). Compute the offset from the
16430 current instruction to branch to. */
16431 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
16432 i = 16;
16433 else
16434 {
16435 /* How many bytes in instructions we've already emitted? */
4d68580a 16436 i = buf - fragp->fr_literal - fragp->fr_fix;
4a6a3df4
AO
16437 /* How many bytes in instructions from here to the end? */
16438 i = fragp->fr_var - i;
16439 }
16440 /* Convert to instruction count. */
16441 i >>= 2;
16442 /* Branch counts from the next instruction. */
b34976b6 16443 i--;
4a6a3df4
AO
16444 insn |= i;
16445 /* Branch over the jump. */
4d68580a 16446 buf = write_insn (buf, insn);
4a6a3df4 16447
54f4ddb3 16448 /* nop */
4d68580a 16449 buf = write_insn (buf, 0);
4a6a3df4
AO
16450
16451 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
16452 {
16453 /* beql $0, $0, 2f */
16454 insn = 0x50000000;
16455 /* Compute the PC offset from the current instruction to
16456 the end of the variable frag. */
16457 /* How many bytes in instructions we've already emitted? */
4d68580a 16458 i = buf - fragp->fr_literal - fragp->fr_fix;
4a6a3df4
AO
16459 /* How many bytes in instructions from here to the end? */
16460 i = fragp->fr_var - i;
16461 /* Convert to instruction count. */
16462 i >>= 2;
16463 /* Don't decrement i, because we want to branch over the
16464 delay slot. */
4a6a3df4 16465 insn |= i;
4a6a3df4 16466
4d68580a
RS
16467 buf = write_insn (buf, insn);
16468 buf = write_insn (buf, 0);
4a6a3df4
AO
16469 }
16470
16471 uncond:
16472 if (mips_pic == NO_PIC)
16473 {
16474 /* j or jal. */
16475 insn = (RELAX_BRANCH_LINK (fragp->fr_subtype)
16476 ? 0x0c000000 : 0x08000000);
16477 exp.X_op = O_symbol;
16478 exp.X_add_symbol = fragp->fr_symbol;
16479 exp.X_add_number = fragp->fr_offset;
16480
4d68580a
RS
16481 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp,
16482 FALSE, BFD_RELOC_MIPS_JMP);
4a6a3df4
AO
16483 fixp->fx_file = fragp->fr_file;
16484 fixp->fx_line = fragp->fr_line;
16485
4d68580a 16486 buf = write_insn (buf, insn);
4a6a3df4
AO
16487 }
16488 else
16489 {
66b3e8da
MR
16490 unsigned long at = RELAX_BRANCH_AT (fragp->fr_subtype);
16491
4a6a3df4 16492 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
66b3e8da
MR
16493 insn = HAVE_64BIT_ADDRESSES ? 0xdf800000 : 0x8f800000;
16494 insn |= at << OP_SH_RT;
4a6a3df4
AO
16495 exp.X_op = O_symbol;
16496 exp.X_add_symbol = fragp->fr_symbol;
16497 exp.X_add_number = fragp->fr_offset;
16498
16499 if (fragp->fr_offset)
16500 {
16501 exp.X_add_symbol = make_expr_symbol (&exp);
16502 exp.X_add_number = 0;
16503 }
16504
4d68580a
RS
16505 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp,
16506 FALSE, BFD_RELOC_MIPS_GOT16);
4a6a3df4
AO
16507 fixp->fx_file = fragp->fr_file;
16508 fixp->fx_line = fragp->fr_line;
16509
4d68580a 16510 buf = write_insn (buf, insn);
b34976b6 16511
4a6a3df4 16512 if (mips_opts.isa == ISA_MIPS1)
4d68580a
RS
16513 /* nop */
16514 buf = write_insn (buf, 0);
4a6a3df4
AO
16515
16516 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
66b3e8da
MR
16517 insn = HAVE_64BIT_ADDRESSES ? 0x64000000 : 0x24000000;
16518 insn |= at << OP_SH_RS | at << OP_SH_RT;
4a6a3df4 16519
4d68580a
RS
16520 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp,
16521 FALSE, BFD_RELOC_LO16);
4a6a3df4
AO
16522 fixp->fx_file = fragp->fr_file;
16523 fixp->fx_line = fragp->fr_line;
b34976b6 16524
4d68580a 16525 buf = write_insn (buf, insn);
4a6a3df4
AO
16526
16527 /* j(al)r $at. */
16528 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
66b3e8da 16529 insn = 0x0000f809;
4a6a3df4 16530 else
66b3e8da
MR
16531 insn = 0x00000008;
16532 insn |= at << OP_SH_RS;
4a6a3df4 16533
4d68580a 16534 buf = write_insn (buf, insn);
4a6a3df4
AO
16535 }
16536 }
16537
4a6a3df4 16538 fragp->fr_fix += fragp->fr_var;
4d68580a 16539 gas_assert (buf == fragp->fr_literal + fragp->fr_fix);
4a6a3df4
AO
16540 return;
16541 }
16542
df58fc94
RS
16543 /* Relax microMIPS branches. */
16544 if (RELAX_MICROMIPS_P (fragp->fr_subtype))
16545 {
4d68580a 16546 char *buf = fragp->fr_literal + fragp->fr_fix;
df58fc94
RS
16547 bfd_boolean compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype);
16548 bfd_boolean al = RELAX_MICROMIPS_LINK (fragp->fr_subtype);
16549 int type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype);
2309ddf2 16550 bfd_boolean short_ds;
df58fc94
RS
16551 unsigned long insn;
16552 expressionS exp;
16553 fixS *fixp;
16554
16555 exp.X_op = O_symbol;
16556 exp.X_add_symbol = fragp->fr_symbol;
16557 exp.X_add_number = fragp->fr_offset;
16558
16559 fragp->fr_fix += fragp->fr_var;
16560
16561 /* Handle 16-bit branches that fit or are forced to fit. */
16562 if (type != 0 && !RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype))
16563 {
16564 /* We generate a fixup instead of applying it right now,
16565 because if there is linker relaxation, we're going to
16566 need the relocations. */
16567 if (type == 'D')
4d68580a 16568 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 2, &exp, TRUE,
df58fc94
RS
16569 BFD_RELOC_MICROMIPS_10_PCREL_S1);
16570 else if (type == 'E')
4d68580a 16571 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 2, &exp, TRUE,
df58fc94
RS
16572 BFD_RELOC_MICROMIPS_7_PCREL_S1);
16573 else
16574 abort ();
16575
16576 fixp->fx_file = fragp->fr_file;
16577 fixp->fx_line = fragp->fr_line;
16578
16579 /* These relocations can have an addend that won't fit in
16580 2 octets. */
16581 fixp->fx_no_overflow = 1;
16582
16583 return;
16584 }
16585
2309ddf2 16586 /* Handle 32-bit branches that fit or are forced to fit. */
df58fc94
RS
16587 if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)
16588 || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype))
16589 {
16590 /* We generate a fixup instead of applying it right now,
16591 because if there is linker relaxation, we're going to
16592 need the relocations. */
4d68580a
RS
16593 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, TRUE,
16594 BFD_RELOC_MICROMIPS_16_PCREL_S1);
df58fc94
RS
16595 fixp->fx_file = fragp->fr_file;
16596 fixp->fx_line = fragp->fr_line;
16597
16598 if (type == 0)
16599 return;
16600 }
16601
16602 /* Relax 16-bit branches to 32-bit branches. */
16603 if (type != 0)
16604 {
4d68580a 16605 insn = read_compressed_insn (buf, 2);
df58fc94
RS
16606
16607 if ((insn & 0xfc00) == 0xcc00) /* b16 */
16608 insn = 0x94000000; /* beq */
16609 else if ((insn & 0xdc00) == 0x8c00) /* beqz16/bnez16 */
16610 {
16611 unsigned long regno;
16612
16613 regno = (insn >> MICROMIPSOP_SH_MD) & MICROMIPSOP_MASK_MD;
16614 regno = micromips_to_32_reg_d_map [regno];
16615 insn = ((insn & 0x2000) << 16) | 0x94000000; /* beq/bne */
16616 insn |= regno << MICROMIPSOP_SH_RS;
16617 }
16618 else
16619 abort ();
16620
16621 /* Nothing else to do, just write it out. */
16622 if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)
16623 || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype))
16624 {
4d68580a
RS
16625 buf = write_compressed_insn (buf, insn, 4);
16626 gas_assert (buf == fragp->fr_literal + fragp->fr_fix);
df58fc94
RS
16627 return;
16628 }
16629 }
16630 else
4d68580a 16631 insn = read_compressed_insn (buf, 4);
df58fc94
RS
16632
16633 /* Relax 32-bit branches to a sequence of instructions. */
16634 as_warn_where (fragp->fr_file, fragp->fr_line,
16635 _("Relaxed out-of-range branch into a jump"));
16636
2309ddf2
MR
16637 /* Set the short-delay-slot bit. */
16638 short_ds = al && (insn & 0x02000000) != 0;
df58fc94
RS
16639
16640 if (!RELAX_MICROMIPS_UNCOND (fragp->fr_subtype))
16641 {
16642 symbolS *l;
16643
16644 /* Reverse the branch. */
16645 if ((insn & 0xfc000000) == 0x94000000 /* beq */
16646 || (insn & 0xfc000000) == 0xb4000000) /* bne */
16647 insn ^= 0x20000000;
16648 else if ((insn & 0xffe00000) == 0x40000000 /* bltz */
16649 || (insn & 0xffe00000) == 0x40400000 /* bgez */
16650 || (insn & 0xffe00000) == 0x40800000 /* blez */
16651 || (insn & 0xffe00000) == 0x40c00000 /* bgtz */
16652 || (insn & 0xffe00000) == 0x40a00000 /* bnezc */
16653 || (insn & 0xffe00000) == 0x40e00000 /* beqzc */
16654 || (insn & 0xffe00000) == 0x40200000 /* bltzal */
16655 || (insn & 0xffe00000) == 0x40600000 /* bgezal */
16656 || (insn & 0xffe00000) == 0x42200000 /* bltzals */
16657 || (insn & 0xffe00000) == 0x42600000) /* bgezals */
16658 insn ^= 0x00400000;
16659 else if ((insn & 0xffe30000) == 0x43800000 /* bc1f */
16660 || (insn & 0xffe30000) == 0x43a00000 /* bc1t */
16661 || (insn & 0xffe30000) == 0x42800000 /* bc2f */
16662 || (insn & 0xffe30000) == 0x42a00000) /* bc2t */
16663 insn ^= 0x00200000;
16664 else
16665 abort ();
16666
16667 if (al)
16668 {
16669 /* Clear the and-link and short-delay-slot bits. */
16670 gas_assert ((insn & 0xfda00000) == 0x40200000);
16671
16672 /* bltzal 0x40200000 bgezal 0x40600000 */
16673 /* bltzals 0x42200000 bgezals 0x42600000 */
16674 insn &= ~0x02200000;
16675 }
16676
16677 /* Make a label at the end for use with the branch. */
16678 l = symbol_new (micromips_label_name (), asec, fragp->fr_fix, fragp);
16679 micromips_label_inc ();
f3ded42a 16680 S_SET_OTHER (l, ELF_ST_SET_MICROMIPS (S_GET_OTHER (l)));
df58fc94
RS
16681
16682 /* Refer to it. */
4d68580a
RS
16683 fixp = fix_new (fragp, buf - fragp->fr_literal, 4, l, 0, TRUE,
16684 BFD_RELOC_MICROMIPS_16_PCREL_S1);
df58fc94
RS
16685 fixp->fx_file = fragp->fr_file;
16686 fixp->fx_line = fragp->fr_line;
16687
16688 /* Branch over the jump. */
4d68580a 16689 buf = write_compressed_insn (buf, insn, 4);
df58fc94 16690 if (!compact)
4d68580a
RS
16691 /* nop */
16692 buf = write_compressed_insn (buf, 0x0c00, 2);
df58fc94
RS
16693 }
16694
16695 if (mips_pic == NO_PIC)
16696 {
2309ddf2
MR
16697 unsigned long jal = short_ds ? 0x74000000 : 0xf4000000; /* jal/s */
16698
df58fc94
RS
16699 /* j/jal/jals <sym> R_MICROMIPS_26_S1 */
16700 insn = al ? jal : 0xd4000000;
16701
4d68580a
RS
16702 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE,
16703 BFD_RELOC_MICROMIPS_JMP);
df58fc94
RS
16704 fixp->fx_file = fragp->fr_file;
16705 fixp->fx_line = fragp->fr_line;
16706
4d68580a 16707 buf = write_compressed_insn (buf, insn, 4);
df58fc94 16708 if (compact)
4d68580a
RS
16709 /* nop */
16710 buf = write_compressed_insn (buf, 0x0c00, 2);
df58fc94
RS
16711 }
16712 else
16713 {
16714 unsigned long at = RELAX_MICROMIPS_AT (fragp->fr_subtype);
2309ddf2
MR
16715 unsigned long jalr = short_ds ? 0x45e0 : 0x45c0; /* jalr/s */
16716 unsigned long jr = compact ? 0x45a0 : 0x4580; /* jr/c */
df58fc94
RS
16717
16718 /* lw/ld $at, <sym>($gp) R_MICROMIPS_GOT16 */
16719 insn = HAVE_64BIT_ADDRESSES ? 0xdc1c0000 : 0xfc1c0000;
16720 insn |= at << MICROMIPSOP_SH_RT;
16721
16722 if (exp.X_add_number)
16723 {
16724 exp.X_add_symbol = make_expr_symbol (&exp);
16725 exp.X_add_number = 0;
16726 }
16727
4d68580a
RS
16728 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE,
16729 BFD_RELOC_MICROMIPS_GOT16);
df58fc94
RS
16730 fixp->fx_file = fragp->fr_file;
16731 fixp->fx_line = fragp->fr_line;
16732
4d68580a 16733 buf = write_compressed_insn (buf, insn, 4);
df58fc94
RS
16734
16735 /* d/addiu $at, $at, <sym> R_MICROMIPS_LO16 */
16736 insn = HAVE_64BIT_ADDRESSES ? 0x5c000000 : 0x30000000;
16737 insn |= at << MICROMIPSOP_SH_RT | at << MICROMIPSOP_SH_RS;
16738
4d68580a
RS
16739 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE,
16740 BFD_RELOC_MICROMIPS_LO16);
df58fc94
RS
16741 fixp->fx_file = fragp->fr_file;
16742 fixp->fx_line = fragp->fr_line;
16743
4d68580a 16744 buf = write_compressed_insn (buf, insn, 4);
df58fc94
RS
16745
16746 /* jr/jrc/jalr/jalrs $at */
16747 insn = al ? jalr : jr;
16748 insn |= at << MICROMIPSOP_SH_MJ;
16749
4d68580a 16750 buf = write_compressed_insn (buf, insn, 2);
df58fc94
RS
16751 }
16752
4d68580a 16753 gas_assert (buf == fragp->fr_literal + fragp->fr_fix);
df58fc94
RS
16754 return;
16755 }
16756
252b5132
RH
16757 if (RELAX_MIPS16_P (fragp->fr_subtype))
16758 {
16759 int type;
3994f87e 16760 const struct mips16_immed_operand *op;
252b5132 16761 offsetT val;
5c04167a
RS
16762 char *buf;
16763 unsigned int user_length, length;
252b5132 16764 unsigned long insn;
5c04167a 16765 bfd_boolean ext;
252b5132
RH
16766
16767 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
16768 op = mips16_immed_operands;
16769 while (op->type != type)
16770 ++op;
16771
5c04167a 16772 ext = RELAX_MIPS16_EXTENDED (fragp->fr_subtype);
5f5f22c0 16773 val = resolve_symbol_value (fragp->fr_symbol);
252b5132
RH
16774 if (op->pcrel)
16775 {
16776 addressT addr;
16777
16778 addr = fragp->fr_address + fragp->fr_fix;
16779
16780 /* The rules for the base address of a PC relative reloc are
16781 complicated; see mips16_extended_frag. */
16782 if (type == 'p' || type == 'q')
16783 {
16784 addr += 2;
16785 if (ext)
16786 addr += 2;
16787 /* Ignore the low bit in the target, since it will be
16788 set for a text label. */
16789 if ((val & 1) != 0)
16790 --val;
16791 }
16792 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
16793 addr -= 4;
16794 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
16795 addr -= 2;
16796
16797 addr &= ~ (addressT) ((1 << op->shift) - 1);
16798 val -= addr;
16799
16800 /* Make sure the section winds up with the alignment we have
16801 assumed. */
16802 if (op->shift > 0)
16803 record_alignment (asec, op->shift);
16804 }
16805
16806 if (ext
16807 && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)
16808 || RELAX_MIPS16_DSLOT (fragp->fr_subtype)))
16809 as_warn_where (fragp->fr_file, fragp->fr_line,
16810 _("extended instruction in delay slot"));
16811
5c04167a 16812 buf = fragp->fr_literal + fragp->fr_fix;
252b5132 16813
4d68580a 16814 insn = read_compressed_insn (buf, 2);
5c04167a
RS
16815 if (ext)
16816 insn |= MIPS16_EXTEND;
252b5132 16817
5c04167a
RS
16818 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype))
16819 user_length = 4;
16820 else if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype))
16821 user_length = 2;
16822 else
16823 user_length = 0;
16824
43c0598f 16825 mips16_immed (fragp->fr_file, fragp->fr_line, type,
c150d1d2 16826 BFD_RELOC_UNUSED, val, user_length, &insn);
252b5132 16827
5c04167a
RS
16828 length = (ext ? 4 : 2);
16829 gas_assert (mips16_opcode_length (insn) == length);
16830 write_compressed_insn (buf, insn, length);
16831 fragp->fr_fix += length;
252b5132
RH
16832 }
16833 else
16834 {
df58fc94
RS
16835 relax_substateT subtype = fragp->fr_subtype;
16836 bfd_boolean second_longer = (subtype & RELAX_SECOND_LONGER) != 0;
16837 bfd_boolean use_second = (subtype & RELAX_USE_SECOND) != 0;
4d7206a2
RS
16838 int first, second;
16839 fixS *fixp;
252b5132 16840
df58fc94
RS
16841 first = RELAX_FIRST (subtype);
16842 second = RELAX_SECOND (subtype);
4d7206a2 16843 fixp = (fixS *) fragp->fr_opcode;
252b5132 16844
df58fc94
RS
16845 /* If the delay slot chosen does not match the size of the instruction,
16846 then emit a warning. */
16847 if ((!use_second && (subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0)
16848 || (use_second && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0))
16849 {
16850 relax_substateT s;
16851 const char *msg;
16852
16853 s = subtype & (RELAX_DELAY_SLOT_16BIT
16854 | RELAX_DELAY_SLOT_SIZE_FIRST
16855 | RELAX_DELAY_SLOT_SIZE_SECOND);
16856 msg = macro_warning (s);
16857 if (msg != NULL)
db9b2be4 16858 as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg);
df58fc94
RS
16859 subtype &= ~s;
16860 }
16861
584892a6 16862 /* Possibly emit a warning if we've chosen the longer option. */
df58fc94 16863 if (use_second == second_longer)
584892a6 16864 {
df58fc94
RS
16865 relax_substateT s;
16866 const char *msg;
16867
16868 s = (subtype
16869 & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT));
16870 msg = macro_warning (s);
16871 if (msg != NULL)
db9b2be4 16872 as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg);
df58fc94 16873 subtype &= ~s;
584892a6
RS
16874 }
16875
4d7206a2
RS
16876 /* Go through all the fixups for the first sequence. Disable them
16877 (by marking them as done) if we're going to use the second
16878 sequence instead. */
16879 while (fixp
16880 && fixp->fx_frag == fragp
16881 && fixp->fx_where < fragp->fr_fix - second)
16882 {
df58fc94 16883 if (subtype & RELAX_USE_SECOND)
4d7206a2
RS
16884 fixp->fx_done = 1;
16885 fixp = fixp->fx_next;
16886 }
252b5132 16887
4d7206a2
RS
16888 /* Go through the fixups for the second sequence. Disable them if
16889 we're going to use the first sequence, otherwise adjust their
16890 addresses to account for the relaxation. */
16891 while (fixp && fixp->fx_frag == fragp)
16892 {
df58fc94 16893 if (subtype & RELAX_USE_SECOND)
4d7206a2
RS
16894 fixp->fx_where -= first;
16895 else
16896 fixp->fx_done = 1;
16897 fixp = fixp->fx_next;
16898 }
16899
16900 /* Now modify the frag contents. */
df58fc94 16901 if (subtype & RELAX_USE_SECOND)
4d7206a2
RS
16902 {
16903 char *start;
16904
16905 start = fragp->fr_literal + fragp->fr_fix - first - second;
16906 memmove (start, start + first, second);
16907 fragp->fr_fix -= first;
16908 }
16909 else
16910 fragp->fr_fix -= second;
252b5132
RH
16911 }
16912}
16913
252b5132
RH
16914/* This function is called after the relocs have been generated.
16915 We've been storing mips16 text labels as odd. Here we convert them
16916 back to even for the convenience of the debugger. */
16917
16918void
17a2f251 16919mips_frob_file_after_relocs (void)
252b5132
RH
16920{
16921 asymbol **syms;
16922 unsigned int count, i;
16923
252b5132
RH
16924 syms = bfd_get_outsymbols (stdoutput);
16925 count = bfd_get_symcount (stdoutput);
16926 for (i = 0; i < count; i++, syms++)
df58fc94
RS
16927 if (ELF_ST_IS_COMPRESSED (elf_symbol (*syms)->internal_elf_sym.st_other)
16928 && ((*syms)->value & 1) != 0)
16929 {
16930 (*syms)->value &= ~1;
16931 /* If the symbol has an odd size, it was probably computed
16932 incorrectly, so adjust that as well. */
16933 if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0)
16934 ++elf_symbol (*syms)->internal_elf_sym.st_size;
16935 }
252b5132
RH
16936}
16937
a1facbec
MR
16938/* This function is called whenever a label is defined, including fake
16939 labels instantiated off the dot special symbol. It is used when
16940 handling branch delays; if a branch has a label, we assume we cannot
16941 move it. This also bumps the value of the symbol by 1 in compressed
16942 code. */
252b5132 16943
e1b47bd5 16944static void
a1facbec 16945mips_record_label (symbolS *sym)
252b5132 16946{
a8dbcb85 16947 segment_info_type *si = seg_info (now_seg);
252b5132
RH
16948 struct insn_label_list *l;
16949
16950 if (free_insn_labels == NULL)
16951 l = (struct insn_label_list *) xmalloc (sizeof *l);
16952 else
16953 {
16954 l = free_insn_labels;
16955 free_insn_labels = l->next;
16956 }
16957
16958 l->label = sym;
a8dbcb85
TS
16959 l->next = si->label_list;
16960 si->label_list = l;
a1facbec 16961}
07a53e5c 16962
a1facbec
MR
16963/* This function is called as tc_frob_label() whenever a label is defined
16964 and adds a DWARF-2 record we only want for true labels. */
16965
16966void
16967mips_define_label (symbolS *sym)
16968{
16969 mips_record_label (sym);
07a53e5c 16970 dwarf2_emit_label (sym);
252b5132 16971}
e1b47bd5
RS
16972
16973/* This function is called by tc_new_dot_label whenever a new dot symbol
16974 is defined. */
16975
16976void
16977mips_add_dot_label (symbolS *sym)
16978{
16979 mips_record_label (sym);
16980 if (mips_assembling_insn && HAVE_CODE_COMPRESSION)
16981 mips_compressed_mark_label (sym);
16982}
252b5132 16983\f
252b5132
RH
16984/* Some special processing for a MIPS ELF file. */
16985
16986void
17a2f251 16987mips_elf_final_processing (void)
252b5132
RH
16988{
16989 /* Write out the register information. */
316f5878 16990 if (mips_abi != N64_ABI)
252b5132
RH
16991 {
16992 Elf32_RegInfo s;
16993
16994 s.ri_gprmask = mips_gprmask;
16995 s.ri_cprmask[0] = mips_cprmask[0];
16996 s.ri_cprmask[1] = mips_cprmask[1];
16997 s.ri_cprmask[2] = mips_cprmask[2];
16998 s.ri_cprmask[3] = mips_cprmask[3];
16999 /* The gp_value field is set by the MIPS ELF backend. */
17000
17001 bfd_mips_elf32_swap_reginfo_out (stdoutput, &s,
17002 ((Elf32_External_RegInfo *)
17003 mips_regmask_frag));
17004 }
17005 else
17006 {
17007 Elf64_Internal_RegInfo s;
17008
17009 s.ri_gprmask = mips_gprmask;
17010 s.ri_pad = 0;
17011 s.ri_cprmask[0] = mips_cprmask[0];
17012 s.ri_cprmask[1] = mips_cprmask[1];
17013 s.ri_cprmask[2] = mips_cprmask[2];
17014 s.ri_cprmask[3] = mips_cprmask[3];
17015 /* The gp_value field is set by the MIPS ELF backend. */
17016
17017 bfd_mips_elf64_swap_reginfo_out (stdoutput, &s,
17018 ((Elf64_External_RegInfo *)
17019 mips_regmask_frag));
17020 }
17021
17022 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
17023 sort of BFD interface for this. */
17024 if (mips_any_noreorder)
17025 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER;
17026 if (mips_pic != NO_PIC)
143d77c5 17027 {
8b828383 17028 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC;
143d77c5
EC
17029 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
17030 }
17031 if (mips_abicalls)
17032 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
252b5132 17033
b015e599
AP
17034 /* Set MIPS ELF flags for ASEs. Note that not all ASEs have flags
17035 defined at present; this might need to change in future. */
a4672219
TS
17036 if (file_ase_mips16)
17037 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16;
df58fc94
RS
17038 if (file_ase_micromips)
17039 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MICROMIPS;
846ef2d0 17040 if (file_ase & ASE_MDMX)
deec1734 17041 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX;
1f25f5d3 17042
bdaaa2e1 17043 /* Set the MIPS ELF ABI flags. */
316f5878 17044 if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32)
252b5132 17045 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32;
316f5878 17046 else if (mips_abi == O64_ABI)
252b5132 17047 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64;
316f5878 17048 else if (mips_abi == EABI_ABI)
252b5132 17049 {
316f5878 17050 if (!file_mips_gp32)
252b5132
RH
17051 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64;
17052 else
17053 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32;
17054 }
316f5878 17055 else if (mips_abi == N32_ABI)
be00bddd
TS
17056 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2;
17057
c9914766 17058 /* Nothing to do for N64_ABI. */
252b5132
RH
17059
17060 if (mips_32bitmode)
17061 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE;
ad3fea08 17062
ba92f887
MR
17063 if (mips_flag_nan2008)
17064 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NAN2008;
17065
ad3fea08
TS
17066#if 0 /* XXX FIXME */
17067 /* 32 bit code with 64 bit FP registers. */
17068 if (!file_mips_fp32 && ABI_NEEDS_32BIT_REGS (mips_abi))
17069 elf_elfheader (stdoutput)->e_flags |= ???;
17070#endif
252b5132 17071}
252b5132 17072\f
beae10d5 17073typedef struct proc {
9b2f1d35
EC
17074 symbolS *func_sym;
17075 symbolS *func_end_sym;
beae10d5
KH
17076 unsigned long reg_mask;
17077 unsigned long reg_offset;
17078 unsigned long fpreg_mask;
17079 unsigned long fpreg_offset;
17080 unsigned long frame_offset;
17081 unsigned long frame_reg;
17082 unsigned long pc_reg;
17083} procS;
252b5132
RH
17084
17085static procS cur_proc;
17086static procS *cur_proc_ptr;
17087static int numprocs;
17088
df58fc94
RS
17089/* Implement NOP_OPCODE. We encode a MIPS16 nop as "1", a microMIPS nop
17090 as "2", and a normal nop as "0". */
17091
17092#define NOP_OPCODE_MIPS 0
17093#define NOP_OPCODE_MIPS16 1
17094#define NOP_OPCODE_MICROMIPS 2
742a56fe
RS
17095
17096char
17097mips_nop_opcode (void)
17098{
df58fc94
RS
17099 if (seg_info (now_seg)->tc_segment_info_data.micromips)
17100 return NOP_OPCODE_MICROMIPS;
17101 else if (seg_info (now_seg)->tc_segment_info_data.mips16)
17102 return NOP_OPCODE_MIPS16;
17103 else
17104 return NOP_OPCODE_MIPS;
742a56fe
RS
17105}
17106
df58fc94
RS
17107/* Fill in an rs_align_code fragment. Unlike elsewhere we want to use
17108 32-bit microMIPS NOPs here (if applicable). */
a19d8eb0 17109
0a9ef439 17110void
17a2f251 17111mips_handle_align (fragS *fragp)
a19d8eb0 17112{
df58fc94 17113 char nop_opcode;
742a56fe 17114 char *p;
c67a084a
NC
17115 int bytes, size, excess;
17116 valueT opcode;
742a56fe 17117
0a9ef439
RH
17118 if (fragp->fr_type != rs_align_code)
17119 return;
17120
742a56fe 17121 p = fragp->fr_literal + fragp->fr_fix;
df58fc94
RS
17122 nop_opcode = *p;
17123 switch (nop_opcode)
a19d8eb0 17124 {
df58fc94
RS
17125 case NOP_OPCODE_MICROMIPS:
17126 opcode = micromips_nop32_insn.insn_opcode;
17127 size = 4;
17128 break;
17129 case NOP_OPCODE_MIPS16:
c67a084a
NC
17130 opcode = mips16_nop_insn.insn_opcode;
17131 size = 2;
df58fc94
RS
17132 break;
17133 case NOP_OPCODE_MIPS:
17134 default:
c67a084a
NC
17135 opcode = nop_insn.insn_opcode;
17136 size = 4;
df58fc94 17137 break;
c67a084a 17138 }
a19d8eb0 17139
c67a084a
NC
17140 bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
17141 excess = bytes % size;
df58fc94
RS
17142
17143 /* Handle the leading part if we're not inserting a whole number of
17144 instructions, and make it the end of the fixed part of the frag.
17145 Try to fit in a short microMIPS NOP if applicable and possible,
17146 and use zeroes otherwise. */
17147 gas_assert (excess < 4);
17148 fragp->fr_fix += excess;
17149 switch (excess)
c67a084a 17150 {
df58fc94
RS
17151 case 3:
17152 *p++ = '\0';
17153 /* Fall through. */
17154 case 2:
833794fc 17155 if (nop_opcode == NOP_OPCODE_MICROMIPS && !mips_opts.insn32)
df58fc94 17156 {
4d68580a 17157 p = write_compressed_insn (p, micromips_nop16_insn.insn_opcode, 2);
df58fc94
RS
17158 break;
17159 }
17160 *p++ = '\0';
17161 /* Fall through. */
17162 case 1:
17163 *p++ = '\0';
17164 /* Fall through. */
17165 case 0:
17166 break;
a19d8eb0 17167 }
c67a084a
NC
17168
17169 md_number_to_chars (p, opcode, size);
17170 fragp->fr_var = size;
a19d8eb0
CP
17171}
17172
252b5132 17173static void
17a2f251 17174md_obj_begin (void)
252b5132
RH
17175{
17176}
17177
17178static void
17a2f251 17179md_obj_end (void)
252b5132 17180{
54f4ddb3 17181 /* Check for premature end, nesting errors, etc. */
252b5132 17182 if (cur_proc_ptr)
9a41af64 17183 as_warn (_("missing .end at end of assembly"));
252b5132
RH
17184}
17185
17186static long
17a2f251 17187get_number (void)
252b5132
RH
17188{
17189 int negative = 0;
17190 long val = 0;
17191
17192 if (*input_line_pointer == '-')
17193 {
17194 ++input_line_pointer;
17195 negative = 1;
17196 }
3882b010 17197 if (!ISDIGIT (*input_line_pointer))
956cd1d6 17198 as_bad (_("expected simple number"));
252b5132
RH
17199 if (input_line_pointer[0] == '0')
17200 {
17201 if (input_line_pointer[1] == 'x')
17202 {
17203 input_line_pointer += 2;
3882b010 17204 while (ISXDIGIT (*input_line_pointer))
252b5132
RH
17205 {
17206 val <<= 4;
17207 val |= hex_value (*input_line_pointer++);
17208 }
17209 return negative ? -val : val;
17210 }
17211 else
17212 {
17213 ++input_line_pointer;
3882b010 17214 while (ISDIGIT (*input_line_pointer))
252b5132
RH
17215 {
17216 val <<= 3;
17217 val |= *input_line_pointer++ - '0';
17218 }
17219 return negative ? -val : val;
17220 }
17221 }
3882b010 17222 if (!ISDIGIT (*input_line_pointer))
252b5132
RH
17223 {
17224 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
17225 *input_line_pointer, *input_line_pointer);
956cd1d6 17226 as_warn (_("invalid number"));
252b5132
RH
17227 return -1;
17228 }
3882b010 17229 while (ISDIGIT (*input_line_pointer))
252b5132
RH
17230 {
17231 val *= 10;
17232 val += *input_line_pointer++ - '0';
17233 }
17234 return negative ? -val : val;
17235}
17236
17237/* The .file directive; just like the usual .file directive, but there
c5dd6aab
DJ
17238 is an initial number which is the ECOFF file index. In the non-ECOFF
17239 case .file implies DWARF-2. */
17240
17241static void
17a2f251 17242s_mips_file (int x ATTRIBUTE_UNUSED)
c5dd6aab 17243{
ecb4347a
DJ
17244 static int first_file_directive = 0;
17245
c5dd6aab
DJ
17246 if (ECOFF_DEBUGGING)
17247 {
17248 get_number ();
17249 s_app_file (0);
17250 }
17251 else
ecb4347a
DJ
17252 {
17253 char *filename;
17254
17255 filename = dwarf2_directive_file (0);
17256
17257 /* Versions of GCC up to 3.1 start files with a ".file"
17258 directive even for stabs output. Make sure that this
17259 ".file" is handled. Note that you need a version of GCC
17260 after 3.1 in order to support DWARF-2 on MIPS. */
17261 if (filename != NULL && ! first_file_directive)
17262 {
17263 (void) new_logical_line (filename, -1);
c04f5787 17264 s_app_file_string (filename, 0);
ecb4347a
DJ
17265 }
17266 first_file_directive = 1;
17267 }
c5dd6aab
DJ
17268}
17269
17270/* The .loc directive, implying DWARF-2. */
252b5132
RH
17271
17272static void
17a2f251 17273s_mips_loc (int x ATTRIBUTE_UNUSED)
252b5132 17274{
c5dd6aab
DJ
17275 if (!ECOFF_DEBUGGING)
17276 dwarf2_directive_loc (0);
252b5132
RH
17277}
17278
252b5132
RH
17279/* The .end directive. */
17280
17281static void
17a2f251 17282s_mips_end (int x ATTRIBUTE_UNUSED)
252b5132
RH
17283{
17284 symbolS *p;
252b5132 17285
7a621144
DJ
17286 /* Following functions need their own .frame and .cprestore directives. */
17287 mips_frame_reg_valid = 0;
17288 mips_cprestore_valid = 0;
17289
252b5132
RH
17290 if (!is_end_of_line[(unsigned char) *input_line_pointer])
17291 {
17292 p = get_symbol ();
17293 demand_empty_rest_of_line ();
17294 }
17295 else
17296 p = NULL;
17297
14949570 17298 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
252b5132
RH
17299 as_warn (_(".end not in text section"));
17300
17301 if (!cur_proc_ptr)
17302 {
17303 as_warn (_(".end directive without a preceding .ent directive."));
17304 demand_empty_rest_of_line ();
17305 return;
17306 }
17307
17308 if (p != NULL)
17309 {
9c2799c2 17310 gas_assert (S_GET_NAME (p));
9b2f1d35 17311 if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->func_sym)))
252b5132 17312 as_warn (_(".end symbol does not match .ent symbol."));
ecb4347a
DJ
17313
17314 if (debug_type == DEBUG_STABS)
17315 stabs_generate_asm_endfunc (S_GET_NAME (p),
17316 S_GET_NAME (p));
252b5132
RH
17317 }
17318 else
17319 as_warn (_(".end directive missing or unknown symbol"));
17320
9b2f1d35
EC
17321 /* Create an expression to calculate the size of the function. */
17322 if (p && cur_proc_ptr)
17323 {
17324 OBJ_SYMFIELD_TYPE *obj = symbol_get_obj (p);
17325 expressionS *exp = xmalloc (sizeof (expressionS));
17326
17327 obj->size = exp;
17328 exp->X_op = O_subtract;
17329 exp->X_add_symbol = symbol_temp_new_now ();
17330 exp->X_op_symbol = p;
17331 exp->X_add_number = 0;
17332
17333 cur_proc_ptr->func_end_sym = exp->X_add_symbol;
17334 }
17335
ecb4347a 17336 /* Generate a .pdr section. */
f3ded42a 17337 if (!ECOFF_DEBUGGING && mips_flag_pdr)
ecb4347a
DJ
17338 {
17339 segT saved_seg = now_seg;
17340 subsegT saved_subseg = now_subseg;
ecb4347a
DJ
17341 expressionS exp;
17342 char *fragp;
252b5132 17343
252b5132 17344#ifdef md_flush_pending_output
ecb4347a 17345 md_flush_pending_output ();
252b5132
RH
17346#endif
17347
9c2799c2 17348 gas_assert (pdr_seg);
ecb4347a 17349 subseg_set (pdr_seg, 0);
252b5132 17350
ecb4347a
DJ
17351 /* Write the symbol. */
17352 exp.X_op = O_symbol;
17353 exp.X_add_symbol = p;
17354 exp.X_add_number = 0;
17355 emit_expr (&exp, 4);
252b5132 17356
ecb4347a 17357 fragp = frag_more (7 * 4);
252b5132 17358
17a2f251
TS
17359 md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4);
17360 md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4);
17361 md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4);
17362 md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4);
17363 md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4);
17364 md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4);
17365 md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4);
252b5132 17366
ecb4347a
DJ
17367 subseg_set (saved_seg, saved_subseg);
17368 }
252b5132
RH
17369
17370 cur_proc_ptr = NULL;
17371}
17372
17373/* The .aent and .ent directives. */
17374
17375static void
17a2f251 17376s_mips_ent (int aent)
252b5132 17377{
252b5132 17378 symbolS *symbolP;
252b5132
RH
17379
17380 symbolP = get_symbol ();
17381 if (*input_line_pointer == ',')
f9419b05 17382 ++input_line_pointer;
252b5132 17383 SKIP_WHITESPACE ();
3882b010 17384 if (ISDIGIT (*input_line_pointer)
d9a62219 17385 || *input_line_pointer == '-')
874e8986 17386 get_number ();
252b5132 17387
14949570 17388 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
252b5132
RH
17389 as_warn (_(".ent or .aent not in text section."));
17390
17391 if (!aent && cur_proc_ptr)
9a41af64 17392 as_warn (_("missing .end"));
252b5132
RH
17393
17394 if (!aent)
17395 {
7a621144
DJ
17396 /* This function needs its own .frame and .cprestore directives. */
17397 mips_frame_reg_valid = 0;
17398 mips_cprestore_valid = 0;
17399
252b5132
RH
17400 cur_proc_ptr = &cur_proc;
17401 memset (cur_proc_ptr, '\0', sizeof (procS));
17402
9b2f1d35 17403 cur_proc_ptr->func_sym = symbolP;
252b5132 17404
f9419b05 17405 ++numprocs;
ecb4347a
DJ
17406
17407 if (debug_type == DEBUG_STABS)
17408 stabs_generate_asm_func (S_GET_NAME (symbolP),
17409 S_GET_NAME (symbolP));
252b5132
RH
17410 }
17411
7c0fc524
MR
17412 symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION;
17413
252b5132
RH
17414 demand_empty_rest_of_line ();
17415}
17416
17417/* The .frame directive. If the mdebug section is present (IRIX 5 native)
bdaaa2e1 17418 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
252b5132 17419 s_mips_frame is used so that we can set the PDR information correctly.
bdaaa2e1 17420 We can't use the ecoff routines because they make reference to the ecoff
252b5132
RH
17421 symbol table (in the mdebug section). */
17422
17423static void
17a2f251 17424s_mips_frame (int ignore ATTRIBUTE_UNUSED)
252b5132 17425{
f3ded42a
RS
17426 if (ECOFF_DEBUGGING)
17427 s_ignore (ignore);
17428 else
ecb4347a
DJ
17429 {
17430 long val;
252b5132 17431
ecb4347a
DJ
17432 if (cur_proc_ptr == (procS *) NULL)
17433 {
17434 as_warn (_(".frame outside of .ent"));
17435 demand_empty_rest_of_line ();
17436 return;
17437 }
252b5132 17438
ecb4347a
DJ
17439 cur_proc_ptr->frame_reg = tc_get_register (1);
17440
17441 SKIP_WHITESPACE ();
17442 if (*input_line_pointer++ != ','
17443 || get_absolute_expression_and_terminator (&val) != ',')
17444 {
17445 as_warn (_("Bad .frame directive"));
17446 --input_line_pointer;
17447 demand_empty_rest_of_line ();
17448 return;
17449 }
252b5132 17450
ecb4347a
DJ
17451 cur_proc_ptr->frame_offset = val;
17452 cur_proc_ptr->pc_reg = tc_get_register (0);
252b5132 17453
252b5132 17454 demand_empty_rest_of_line ();
252b5132 17455 }
252b5132
RH
17456}
17457
bdaaa2e1
KH
17458/* The .fmask and .mask directives. If the mdebug section is present
17459 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
252b5132 17460 embedded targets, s_mips_mask is used so that we can set the PDR
bdaaa2e1 17461 information correctly. We can't use the ecoff routines because they
252b5132
RH
17462 make reference to the ecoff symbol table (in the mdebug section). */
17463
17464static void
17a2f251 17465s_mips_mask (int reg_type)
252b5132 17466{
f3ded42a
RS
17467 if (ECOFF_DEBUGGING)
17468 s_ignore (reg_type);
17469 else
252b5132 17470 {
ecb4347a 17471 long mask, off;
252b5132 17472
ecb4347a
DJ
17473 if (cur_proc_ptr == (procS *) NULL)
17474 {
17475 as_warn (_(".mask/.fmask outside of .ent"));
17476 demand_empty_rest_of_line ();
17477 return;
17478 }
252b5132 17479
ecb4347a
DJ
17480 if (get_absolute_expression_and_terminator (&mask) != ',')
17481 {
17482 as_warn (_("Bad .mask/.fmask directive"));
17483 --input_line_pointer;
17484 demand_empty_rest_of_line ();
17485 return;
17486 }
252b5132 17487
ecb4347a
DJ
17488 off = get_absolute_expression ();
17489
17490 if (reg_type == 'F')
17491 {
17492 cur_proc_ptr->fpreg_mask = mask;
17493 cur_proc_ptr->fpreg_offset = off;
17494 }
17495 else
17496 {
17497 cur_proc_ptr->reg_mask = mask;
17498 cur_proc_ptr->reg_offset = off;
17499 }
17500
17501 demand_empty_rest_of_line ();
252b5132 17502 }
252b5132
RH
17503}
17504
316f5878
RS
17505/* A table describing all the processors gas knows about. Names are
17506 matched in the order listed.
e7af610e 17507
316f5878
RS
17508 To ease comparison, please keep this table in the same order as
17509 gcc's mips_cpu_info_table[]. */
e972090a
NC
17510static const struct mips_cpu_info mips_cpu_info_table[] =
17511{
316f5878 17512 /* Entries for generic ISAs */
d16afab6
RS
17513 { "mips1", MIPS_CPU_IS_ISA, 0, ISA_MIPS1, CPU_R3000 },
17514 { "mips2", MIPS_CPU_IS_ISA, 0, ISA_MIPS2, CPU_R6000 },
17515 { "mips3", MIPS_CPU_IS_ISA, 0, ISA_MIPS3, CPU_R4000 },
17516 { "mips4", MIPS_CPU_IS_ISA, 0, ISA_MIPS4, CPU_R8000 },
17517 { "mips5", MIPS_CPU_IS_ISA, 0, ISA_MIPS5, CPU_MIPS5 },
17518 { "mips32", MIPS_CPU_IS_ISA, 0, ISA_MIPS32, CPU_MIPS32 },
17519 { "mips32r2", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
17520 { "mips64", MIPS_CPU_IS_ISA, 0, ISA_MIPS64, CPU_MIPS64 },
17521 { "mips64r2", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R2, CPU_MIPS64R2 },
316f5878
RS
17522
17523 /* MIPS I */
d16afab6
RS
17524 { "r3000", 0, 0, ISA_MIPS1, CPU_R3000 },
17525 { "r2000", 0, 0, ISA_MIPS1, CPU_R3000 },
17526 { "r3900", 0, 0, ISA_MIPS1, CPU_R3900 },
316f5878
RS
17527
17528 /* MIPS II */
d16afab6 17529 { "r6000", 0, 0, ISA_MIPS2, CPU_R6000 },
316f5878
RS
17530
17531 /* MIPS III */
d16afab6
RS
17532 { "r4000", 0, 0, ISA_MIPS3, CPU_R4000 },
17533 { "r4010", 0, 0, ISA_MIPS2, CPU_R4010 },
17534 { "vr4100", 0, 0, ISA_MIPS3, CPU_VR4100 },
17535 { "vr4111", 0, 0, ISA_MIPS3, CPU_R4111 },
17536 { "vr4120", 0, 0, ISA_MIPS3, CPU_VR4120 },
17537 { "vr4130", 0, 0, ISA_MIPS3, CPU_VR4120 },
17538 { "vr4181", 0, 0, ISA_MIPS3, CPU_R4111 },
17539 { "vr4300", 0, 0, ISA_MIPS3, CPU_R4300 },
17540 { "r4400", 0, 0, ISA_MIPS3, CPU_R4400 },
17541 { "r4600", 0, 0, ISA_MIPS3, CPU_R4600 },
17542 { "orion", 0, 0, ISA_MIPS3, CPU_R4600 },
17543 { "r4650", 0, 0, ISA_MIPS3, CPU_R4650 },
17544 { "r5900", 0, 0, ISA_MIPS3, CPU_R5900 },
b15591bb 17545 /* ST Microelectronics Loongson 2E and 2F cores */
d16afab6
RS
17546 { "loongson2e", 0, 0, ISA_MIPS3, CPU_LOONGSON_2E },
17547 { "loongson2f", 0, 0, ISA_MIPS3, CPU_LOONGSON_2F },
316f5878
RS
17548
17549 /* MIPS IV */
d16afab6
RS
17550 { "r8000", 0, 0, ISA_MIPS4, CPU_R8000 },
17551 { "r10000", 0, 0, ISA_MIPS4, CPU_R10000 },
17552 { "r12000", 0, 0, ISA_MIPS4, CPU_R12000 },
17553 { "r14000", 0, 0, ISA_MIPS4, CPU_R14000 },
17554 { "r16000", 0, 0, ISA_MIPS4, CPU_R16000 },
17555 { "vr5000", 0, 0, ISA_MIPS4, CPU_R5000 },
17556 { "vr5400", 0, 0, ISA_MIPS4, CPU_VR5400 },
17557 { "vr5500", 0, 0, ISA_MIPS4, CPU_VR5500 },
17558 { "rm5200", 0, 0, ISA_MIPS4, CPU_R5000 },
17559 { "rm5230", 0, 0, ISA_MIPS4, CPU_R5000 },
17560 { "rm5231", 0, 0, ISA_MIPS4, CPU_R5000 },
17561 { "rm5261", 0, 0, ISA_MIPS4, CPU_R5000 },
17562 { "rm5721", 0, 0, ISA_MIPS4, CPU_R5000 },
17563 { "rm7000", 0, 0, ISA_MIPS4, CPU_RM7000 },
17564 { "rm9000", 0, 0, ISA_MIPS4, CPU_RM9000 },
316f5878
RS
17565
17566 /* MIPS 32 */
d16afab6
RS
17567 { "4kc", 0, 0, ISA_MIPS32, CPU_MIPS32 },
17568 { "4km", 0, 0, ISA_MIPS32, CPU_MIPS32 },
17569 { "4kp", 0, 0, ISA_MIPS32, CPU_MIPS32 },
17570 { "4ksc", 0, ASE_SMARTMIPS, ISA_MIPS32, CPU_MIPS32 },
ad3fea08
TS
17571
17572 /* MIPS 32 Release 2 */
d16afab6
RS
17573 { "4kec", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
17574 { "4kem", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
17575 { "4kep", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
17576 { "4ksd", 0, ASE_SMARTMIPS, ISA_MIPS32R2, CPU_MIPS32R2 },
17577 { "m4k", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
17578 { "m4kp", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
17579 { "m14k", 0, ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 },
17580 { "m14kc", 0, ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 },
17581 { "m14ke", 0, ASE_DSP | ASE_DSPR2 | ASE_MCU,
17582 ISA_MIPS32R2, CPU_MIPS32R2 },
17583 { "m14kec", 0, ASE_DSP | ASE_DSPR2 | ASE_MCU,
17584 ISA_MIPS32R2, CPU_MIPS32R2 },
17585 { "24kc", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
17586 { "24kf2_1", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
17587 { "24kf", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
17588 { "24kf1_1", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
0fdf1951 17589 /* Deprecated forms of the above. */
d16afab6
RS
17590 { "24kfx", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
17591 { "24kx", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
01fd108f 17592 /* 24KE is a 24K with DSP ASE, other ASEs are optional. */
d16afab6
RS
17593 { "24kec", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
17594 { "24kef2_1", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
17595 { "24kef", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
17596 { "24kef1_1", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
0fdf1951 17597 /* Deprecated forms of the above. */
d16afab6
RS
17598 { "24kefx", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
17599 { "24kex", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
01fd108f 17600 /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */
d16afab6
RS
17601 { "34kc", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
17602 { "34kf2_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
17603 { "34kf", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
17604 { "34kf1_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
0fdf1951 17605 /* Deprecated forms of the above. */
d16afab6
RS
17606 { "34kfx", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
17607 { "34kx", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
711eefe4 17608 /* 34Kn is a 34kc without DSP. */
d16afab6 17609 { "34kn", 0, ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
01fd108f 17610 /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */
d16afab6
RS
17611 { "74kc", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
17612 { "74kf2_1", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
17613 { "74kf", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
17614 { "74kf1_1", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
17615 { "74kf3_2", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
0fdf1951 17616 /* Deprecated forms of the above. */
d16afab6
RS
17617 { "74kfx", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
17618 { "74kx", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
30f8113a 17619 /* 1004K cores are multiprocessor versions of the 34K. */
d16afab6
RS
17620 { "1004kc", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
17621 { "1004kf2_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
17622 { "1004kf", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
17623 { "1004kf1_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
32b26a03 17624
316f5878 17625 /* MIPS 64 */
d16afab6
RS
17626 { "5kc", 0, 0, ISA_MIPS64, CPU_MIPS64 },
17627 { "5kf", 0, 0, ISA_MIPS64, CPU_MIPS64 },
17628 { "20kc", 0, ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 },
17629 { "25kf", 0, ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 },
ad3fea08 17630
c7a23324 17631 /* Broadcom SB-1 CPU core */
d16afab6 17632 { "sb1", 0, ASE_MIPS3D | ASE_MDMX, ISA_MIPS64, CPU_SB1 },
1e85aad8 17633 /* Broadcom SB-1A CPU core */
d16afab6 17634 { "sb1a", 0, ASE_MIPS3D | ASE_MDMX, ISA_MIPS64, CPU_SB1 },
d051516a 17635
d16afab6 17636 { "loongson3a", 0, 0, ISA_MIPS64, CPU_LOONGSON_3A },
e7af610e 17637
ed163775
MR
17638 /* MIPS 64 Release 2 */
17639
967344c6 17640 /* Cavium Networks Octeon CPU core */
d16afab6
RS
17641 { "octeon", 0, 0, ISA_MIPS64R2, CPU_OCTEON },
17642 { "octeon+", 0, 0, ISA_MIPS64R2, CPU_OCTEONP },
17643 { "octeon2", 0, 0, ISA_MIPS64R2, CPU_OCTEON2 },
967344c6 17644
52b6b6b9 17645 /* RMI Xlr */
d16afab6 17646 { "xlr", 0, 0, ISA_MIPS64, CPU_XLR },
52b6b6b9 17647
55a36193
MK
17648 /* Broadcom XLP.
17649 XLP is mostly like XLR, with the prominent exception that it is
17650 MIPS64R2 rather than MIPS64. */
d16afab6 17651 { "xlp", 0, 0, ISA_MIPS64R2, CPU_XLR },
55a36193 17652
316f5878 17653 /* End marker */
d16afab6 17654 { NULL, 0, 0, 0, 0 }
316f5878 17655};
e7af610e 17656
84ea6cf2 17657
316f5878
RS
17658/* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
17659 with a final "000" replaced by "k". Ignore case.
e7af610e 17660
316f5878 17661 Note: this function is shared between GCC and GAS. */
c6c98b38 17662
b34976b6 17663static bfd_boolean
17a2f251 17664mips_strict_matching_cpu_name_p (const char *canonical, const char *given)
316f5878
RS
17665{
17666 while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical))
17667 given++, canonical++;
17668
17669 return ((*given == 0 && *canonical == 0)
17670 || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0));
17671}
17672
17673
17674/* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
17675 CPU name. We've traditionally allowed a lot of variation here.
17676
17677 Note: this function is shared between GCC and GAS. */
17678
b34976b6 17679static bfd_boolean
17a2f251 17680mips_matching_cpu_name_p (const char *canonical, const char *given)
316f5878
RS
17681{
17682 /* First see if the name matches exactly, or with a final "000"
17683 turned into "k". */
17684 if (mips_strict_matching_cpu_name_p (canonical, given))
b34976b6 17685 return TRUE;
316f5878
RS
17686
17687 /* If not, try comparing based on numerical designation alone.
17688 See if GIVEN is an unadorned number, or 'r' followed by a number. */
17689 if (TOLOWER (*given) == 'r')
17690 given++;
17691 if (!ISDIGIT (*given))
b34976b6 17692 return FALSE;
316f5878
RS
17693
17694 /* Skip over some well-known prefixes in the canonical name,
17695 hoping to find a number there too. */
17696 if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r')
17697 canonical += 2;
17698 else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm')
17699 canonical += 2;
17700 else if (TOLOWER (canonical[0]) == 'r')
17701 canonical += 1;
17702
17703 return mips_strict_matching_cpu_name_p (canonical, given);
17704}
17705
17706
17707/* Parse an option that takes the name of a processor as its argument.
17708 OPTION is the name of the option and CPU_STRING is the argument.
17709 Return the corresponding processor enumeration if the CPU_STRING is
17710 recognized, otherwise report an error and return null.
17711
17712 A similar function exists in GCC. */
e7af610e
NC
17713
17714static const struct mips_cpu_info *
17a2f251 17715mips_parse_cpu (const char *option, const char *cpu_string)
e7af610e 17716{
316f5878 17717 const struct mips_cpu_info *p;
e7af610e 17718
316f5878
RS
17719 /* 'from-abi' selects the most compatible architecture for the given
17720 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
17721 EABIs, we have to decide whether we're using the 32-bit or 64-bit
17722 version. Look first at the -mgp options, if given, otherwise base
17723 the choice on MIPS_DEFAULT_64BIT.
e7af610e 17724
316f5878
RS
17725 Treat NO_ABI like the EABIs. One reason to do this is that the
17726 plain 'mips' and 'mips64' configs have 'from-abi' as their default
17727 architecture. This code picks MIPS I for 'mips' and MIPS III for
17728 'mips64', just as we did in the days before 'from-abi'. */
17729 if (strcasecmp (cpu_string, "from-abi") == 0)
17730 {
17731 if (ABI_NEEDS_32BIT_REGS (mips_abi))
17732 return mips_cpu_info_from_isa (ISA_MIPS1);
17733
17734 if (ABI_NEEDS_64BIT_REGS (mips_abi))
17735 return mips_cpu_info_from_isa (ISA_MIPS3);
17736
17737 if (file_mips_gp32 >= 0)
17738 return mips_cpu_info_from_isa (file_mips_gp32 ? ISA_MIPS1 : ISA_MIPS3);
17739
17740 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
17741 ? ISA_MIPS3
17742 : ISA_MIPS1);
17743 }
17744
17745 /* 'default' has traditionally been a no-op. Probably not very useful. */
17746 if (strcasecmp (cpu_string, "default") == 0)
17747 return 0;
17748
17749 for (p = mips_cpu_info_table; p->name != 0; p++)
17750 if (mips_matching_cpu_name_p (p->name, cpu_string))
17751 return p;
17752
20203fb9 17753 as_bad (_("Bad value (%s) for %s"), cpu_string, option);
316f5878 17754 return 0;
e7af610e
NC
17755}
17756
316f5878
RS
17757/* Return the canonical processor information for ISA (a member of the
17758 ISA_MIPS* enumeration). */
17759
e7af610e 17760static const struct mips_cpu_info *
17a2f251 17761mips_cpu_info_from_isa (int isa)
e7af610e
NC
17762{
17763 int i;
17764
17765 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
ad3fea08 17766 if ((mips_cpu_info_table[i].flags & MIPS_CPU_IS_ISA)
316f5878 17767 && isa == mips_cpu_info_table[i].isa)
e7af610e
NC
17768 return (&mips_cpu_info_table[i]);
17769
e972090a 17770 return NULL;
e7af610e 17771}
fef14a42
TS
17772
17773static const struct mips_cpu_info *
17a2f251 17774mips_cpu_info_from_arch (int arch)
fef14a42
TS
17775{
17776 int i;
17777
17778 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
17779 if (arch == mips_cpu_info_table[i].cpu)
17780 return (&mips_cpu_info_table[i]);
17781
17782 return NULL;
17783}
316f5878
RS
17784\f
17785static void
17a2f251 17786show (FILE *stream, const char *string, int *col_p, int *first_p)
316f5878
RS
17787{
17788 if (*first_p)
17789 {
17790 fprintf (stream, "%24s", "");
17791 *col_p = 24;
17792 }
17793 else
17794 {
17795 fprintf (stream, ", ");
17796 *col_p += 2;
17797 }
e7af610e 17798
316f5878
RS
17799 if (*col_p + strlen (string) > 72)
17800 {
17801 fprintf (stream, "\n%24s", "");
17802 *col_p = 24;
17803 }
17804
17805 fprintf (stream, "%s", string);
17806 *col_p += strlen (string);
17807
17808 *first_p = 0;
17809}
17810
17811void
17a2f251 17812md_show_usage (FILE *stream)
e7af610e 17813{
316f5878
RS
17814 int column, first;
17815 size_t i;
17816
17817 fprintf (stream, _("\
17818MIPS options:\n\
316f5878
RS
17819-EB generate big endian output\n\
17820-EL generate little endian output\n\
17821-g, -g2 do not remove unneeded NOPs or swap branches\n\
17822-G NUM allow referencing objects up to NUM bytes\n\
17823 implicitly with the gp register [default 8]\n"));
17824 fprintf (stream, _("\
17825-mips1 generate MIPS ISA I instructions\n\
17826-mips2 generate MIPS ISA II instructions\n\
17827-mips3 generate MIPS ISA III instructions\n\
17828-mips4 generate MIPS ISA IV instructions\n\
17829-mips5 generate MIPS ISA V instructions\n\
17830-mips32 generate MIPS32 ISA instructions\n\
af7ee8bf 17831-mips32r2 generate MIPS32 release 2 ISA instructions\n\
316f5878 17832-mips64 generate MIPS64 ISA instructions\n\
5f74bc13 17833-mips64r2 generate MIPS64 release 2 ISA instructions\n\
316f5878
RS
17834-march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
17835
17836 first = 1;
e7af610e
NC
17837
17838 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
316f5878
RS
17839 show (stream, mips_cpu_info_table[i].name, &column, &first);
17840 show (stream, "from-abi", &column, &first);
17841 fputc ('\n', stream);
e7af610e 17842
316f5878
RS
17843 fprintf (stream, _("\
17844-mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
17845-no-mCPU don't generate code specific to CPU.\n\
17846 For -mCPU and -no-mCPU, CPU must be one of:\n"));
17847
17848 first = 1;
17849
17850 show (stream, "3900", &column, &first);
17851 show (stream, "4010", &column, &first);
17852 show (stream, "4100", &column, &first);
17853 show (stream, "4650", &column, &first);
17854 fputc ('\n', stream);
17855
17856 fprintf (stream, _("\
17857-mips16 generate mips16 instructions\n\
17858-no-mips16 do not generate mips16 instructions\n"));
17859 fprintf (stream, _("\
df58fc94
RS
17860-mmicromips generate microMIPS instructions\n\
17861-mno-micromips do not generate microMIPS instructions\n"));
17862 fprintf (stream, _("\
e16bfa71
TS
17863-msmartmips generate smartmips instructions\n\
17864-mno-smartmips do not generate smartmips instructions\n"));
17865 fprintf (stream, _("\
74cd071d
CF
17866-mdsp generate DSP instructions\n\
17867-mno-dsp do not generate DSP instructions\n"));
17868 fprintf (stream, _("\
8b082fb1
TS
17869-mdspr2 generate DSP R2 instructions\n\
17870-mno-dspr2 do not generate DSP R2 instructions\n"));
17871 fprintf (stream, _("\
ef2e4d86
CF
17872-mmt generate MT instructions\n\
17873-mno-mt do not generate MT instructions\n"));
17874 fprintf (stream, _("\
dec0624d
MR
17875-mmcu generate MCU instructions\n\
17876-mno-mcu do not generate MCU instructions\n"));
17877 fprintf (stream, _("\
b015e599
AP
17878-mvirt generate Virtualization instructions\n\
17879-mno-virt do not generate Virtualization instructions\n"));
17880 fprintf (stream, _("\
833794fc
MR
17881-minsn32 only generate 32-bit microMIPS instructions\n\
17882-mno-insn32 generate all microMIPS instructions\n"));
17883 fprintf (stream, _("\
c67a084a
NC
17884-mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\
17885-mfix-loongson2f-nop work around Loongson2F NOP errata\n\
d766e8ec 17886-mfix-vr4120 work around certain VR4120 errata\n\
7d8e00cf 17887-mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
6a32d874 17888-mfix-24k insert a nop after ERET and DERET instructions\n\
d954098f 17889-mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\
316f5878
RS
17890-mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
17891-mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
aed1a261 17892-msym32 assume all symbols have 32-bit values\n\
316f5878
RS
17893-O0 remove unneeded NOPs, do not swap branches\n\
17894-O remove unneeded NOPs and swap branches\n\
316f5878
RS
17895--trap, --no-break trap exception on div by 0 and mult overflow\n\
17896--break, --no-trap break exception on div by 0 and mult overflow\n"));
037b32b9
AN
17897 fprintf (stream, _("\
17898-mhard-float allow floating-point instructions\n\
17899-msoft-float do not allow floating-point instructions\n\
17900-msingle-float only allow 32-bit floating-point operations\n\
17901-mdouble-float allow 32-bit and 64-bit floating-point operations\n\
3bf0dbfb 17902--[no-]construct-floats [dis]allow floating point values to be constructed\n\
ba92f887
MR
17903--[no-]relax-branch [dis]allow out-of-range branches to be relaxed\n\
17904-mnan=ENCODING select an IEEE 754 NaN encoding convention, either of:\n"));
17905
17906 first = 1;
17907
17908 show (stream, "legacy", &column, &first);
17909 show (stream, "2008", &column, &first);
17910
17911 fputc ('\n', stream);
17912
316f5878
RS
17913 fprintf (stream, _("\
17914-KPIC, -call_shared generate SVR4 position independent code\n\
861fb55a 17915-call_nonpic generate non-PIC code that can operate with DSOs\n\
0c000745 17916-mvxworks-pic generate VxWorks position independent code\n\
861fb55a 17917-non_shared do not generate code that can operate with DSOs\n\
316f5878 17918-xgot assume a 32 bit GOT\n\
dcd410fe 17919-mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
bbe506e8 17920-mshared, -mno-shared disable/enable .cpload optimization for\n\
d821e36b 17921 position dependent (non shared) code\n\
316f5878
RS
17922-mabi=ABI create ABI conformant object file for:\n"));
17923
17924 first = 1;
17925
17926 show (stream, "32", &column, &first);
17927 show (stream, "o64", &column, &first);
17928 show (stream, "n32", &column, &first);
17929 show (stream, "64", &column, &first);
17930 show (stream, "eabi", &column, &first);
17931
17932 fputc ('\n', stream);
17933
17934 fprintf (stream, _("\
17935-32 create o32 ABI object file (default)\n\
17936-n32 create n32 ABI object file\n\
17937-64 create 64 ABI object file\n"));
e7af610e 17938}
14e777e0 17939
1575952e 17940#ifdef TE_IRIX
14e777e0 17941enum dwarf2_format
413a266c 17942mips_dwarf2_format (asection *sec ATTRIBUTE_UNUSED)
14e777e0 17943{
369943fe 17944 if (HAVE_64BIT_SYMBOLS)
1575952e 17945 return dwarf2_format_64bit_irix;
14e777e0
KB
17946 else
17947 return dwarf2_format_32bit;
17948}
1575952e 17949#endif
73369e65
EC
17950
17951int
17952mips_dwarf2_addr_size (void)
17953{
6b6b3450 17954 if (HAVE_64BIT_OBJECTS)
73369e65 17955 return 8;
73369e65
EC
17956 else
17957 return 4;
17958}
5862107c
EC
17959
17960/* Standard calling conventions leave the CFA at SP on entry. */
17961void
17962mips_cfi_frame_initial_instructions (void)
17963{
17964 cfi_add_CFA_def_cfa_register (SP);
17965}
17966
707bfff6
TS
17967int
17968tc_mips_regname_to_dw2regnum (char *regname)
17969{
17970 unsigned int regnum = -1;
17971 unsigned int reg;
17972
17973 if (reg_lookup (&regname, RTYPE_GP | RTYPE_NUM, &reg))
17974 regnum = reg;
17975
17976 return regnum;
17977}
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