Commit | Line | Data |
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252b5132 | 1 | /* tc-mips.c -- assemble code for a MIPS chip. |
f7e42eb4 | 2 | Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001 |
82efde3a | 3 | Free Software Foundation, Inc. |
252b5132 RH |
4 | Contributed by the OSF and Ralph Campbell. |
5 | Written by Keith Knowles and Ralph Campbell, working independently. | |
6 | Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus | |
7 | Support. | |
8 | ||
9 | This file is part of GAS. | |
10 | ||
11 | GAS is free software; you can redistribute it and/or modify | |
12 | it under the terms of the GNU General Public License as published by | |
13 | the Free Software Foundation; either version 2, or (at your option) | |
14 | any later version. | |
15 | ||
16 | GAS is distributed in the hope that it will be useful, | |
17 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | GNU General Public License for more details. | |
20 | ||
21 | You should have received a copy of the GNU General Public License | |
22 | along with GAS; see the file COPYING. If not, write to the Free | |
23 | Software Foundation, 59 Temple Place - Suite 330, Boston, MA | |
24 | 02111-1307, USA. */ | |
25 | ||
26 | #include "as.h" | |
27 | #include "config.h" | |
28 | #include "subsegs.h" | |
3882b010 | 29 | #include "safe-ctype.h" |
252b5132 RH |
30 | |
31 | #ifdef USE_STDARG | |
32 | #include <stdarg.h> | |
33 | #endif | |
34 | #ifdef USE_VARARGS | |
35 | #include <varargs.h> | |
36 | #endif | |
37 | ||
38 | #include "opcode/mips.h" | |
39 | #include "itbl-ops.h" | |
40 | ||
41 | #ifdef DEBUG | |
42 | #define DBG(x) printf x | |
43 | #else | |
44 | #define DBG(x) | |
45 | #endif | |
46 | ||
47 | #ifdef OBJ_MAYBE_ELF | |
48 | /* Clean up namespace so we can include obj-elf.h too. */ | |
49 | static int mips_output_flavor PARAMS ((void)); | |
50 | static int mips_output_flavor () { return OUTPUT_FLAVOR; } | |
51 | #undef OBJ_PROCESS_STAB | |
52 | #undef OUTPUT_FLAVOR | |
53 | #undef S_GET_ALIGN | |
54 | #undef S_GET_SIZE | |
55 | #undef S_SET_ALIGN | |
56 | #undef S_SET_SIZE | |
252b5132 RH |
57 | #undef obj_frob_file |
58 | #undef obj_frob_file_after_relocs | |
59 | #undef obj_frob_symbol | |
60 | #undef obj_pop_insert | |
61 | #undef obj_sec_sym_ok_for_reloc | |
62 | #undef OBJ_COPY_SYMBOL_ATTRIBUTES | |
63 | ||
64 | #include "obj-elf.h" | |
65 | /* Fix any of them that we actually care about. */ | |
66 | #undef OUTPUT_FLAVOR | |
67 | #define OUTPUT_FLAVOR mips_output_flavor() | |
68 | #endif | |
69 | ||
70 | #if defined (OBJ_ELF) | |
71 | #include "elf/mips.h" | |
72 | #endif | |
73 | ||
74 | #ifndef ECOFF_DEBUGGING | |
75 | #define NO_ECOFF_DEBUGGING | |
76 | #define ECOFF_DEBUGGING 0 | |
77 | #endif | |
78 | ||
79 | #include "ecoff.h" | |
80 | ||
81 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
82 | static char *mips_regmask_frag; | |
83 | #endif | |
84 | ||
85 | #define AT 1 | |
86 | #define TREG 24 | |
87 | #define PIC_CALL_REG 25 | |
88 | #define KT0 26 | |
89 | #define KT1 27 | |
90 | #define GP 28 | |
91 | #define SP 29 | |
92 | #define FP 30 | |
93 | #define RA 31 | |
94 | ||
95 | #define ILLEGAL_REG (32) | |
96 | ||
97 | /* Allow override of standard little-endian ECOFF format. */ | |
98 | ||
99 | #ifndef ECOFF_LITTLE_FORMAT | |
100 | #define ECOFF_LITTLE_FORMAT "ecoff-littlemips" | |
101 | #endif | |
102 | ||
103 | extern int target_big_endian; | |
104 | ||
252b5132 RH |
105 | /* The name of the readonly data section. */ |
106 | #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \ | |
107 | ? ".data" \ | |
108 | : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \ | |
109 | ? ".rdata" \ | |
056350c6 NC |
110 | : OUTPUT_FLAVOR == bfd_target_coff_flavour \ |
111 | ? ".rdata" \ | |
252b5132 RH |
112 | : OUTPUT_FLAVOR == bfd_target_elf_flavour \ |
113 | ? ".rodata" \ | |
114 | : (abort (), "")) | |
115 | ||
116 | /* This is the set of options which may be modified by the .set | |
117 | pseudo-op. We use a struct so that .set push and .set pop are more | |
118 | reliable. */ | |
119 | ||
e972090a NC |
120 | struct mips_set_options |
121 | { | |
252b5132 RH |
122 | /* MIPS ISA (Instruction Set Architecture) level. This is set to -1 |
123 | if it has not been initialized. Changed by `.set mipsN', and the | |
124 | -mipsN command line option, and the default CPU. */ | |
125 | int isa; | |
126 | /* Whether we are assembling for the mips16 processor. 0 if we are | |
127 | not, 1 if we are, and -1 if the value has not been initialized. | |
128 | Changed by `.set mips16' and `.set nomips16', and the -mips16 and | |
129 | -nomips16 command line options, and the default CPU. */ | |
130 | int mips16; | |
131 | /* Non-zero if we should not reorder instructions. Changed by `.set | |
132 | reorder' and `.set noreorder'. */ | |
133 | int noreorder; | |
134 | /* Non-zero if we should not permit the $at ($1) register to be used | |
135 | in instructions. Changed by `.set at' and `.set noat'. */ | |
136 | int noat; | |
137 | /* Non-zero if we should warn when a macro instruction expands into | |
138 | more than one machine instruction. Changed by `.set nomacro' and | |
139 | `.set macro'. */ | |
140 | int warn_about_macros; | |
141 | /* Non-zero if we should not move instructions. Changed by `.set | |
142 | move', `.set volatile', `.set nomove', and `.set novolatile'. */ | |
143 | int nomove; | |
144 | /* Non-zero if we should not optimize branches by moving the target | |
145 | of the branch into the delay slot. Actually, we don't perform | |
146 | this optimization anyhow. Changed by `.set bopt' and `.set | |
147 | nobopt'. */ | |
148 | int nobopt; | |
149 | /* Non-zero if we should not autoextend mips16 instructions. | |
150 | Changed by `.set autoextend' and `.set noautoextend'. */ | |
151 | int noautoextend; | |
152 | }; | |
153 | ||
154 | /* This is the struct we use to hold the current set of options. Note | |
e7af610e NC |
155 | that we must set the isa field to ISA_UNKNOWN and the mips16 field to |
156 | -1 to indicate that they have not been initialized. */ | |
252b5132 | 157 | |
e972090a NC |
158 | static struct mips_set_options mips_opts = |
159 | { | |
e7af610e NC |
160 | ISA_UNKNOWN, -1, 0, 0, 0, 0, 0, 0 |
161 | }; | |
252b5132 RH |
162 | |
163 | /* These variables are filled in with the masks of registers used. | |
164 | The object format code reads them and puts them in the appropriate | |
165 | place. */ | |
166 | unsigned long mips_gprmask; | |
167 | unsigned long mips_cprmask[4]; | |
168 | ||
169 | /* MIPS ISA we are using for this output file. */ | |
e7af610e | 170 | static int file_mips_isa = ISA_UNKNOWN; |
252b5132 | 171 | |
ec68c924 | 172 | /* The argument of the -mcpu= flag. Historical for code generation. */ |
e7af610e | 173 | static int mips_cpu = CPU_UNKNOWN; |
252b5132 | 174 | |
ec68c924 EC |
175 | /* The argument of the -march= flag. The architecture we are assembling. */ |
176 | static int mips_arch = CPU_UNKNOWN; | |
177 | ||
178 | /* The argument of the -mtune= flag. The architecture for which we | |
179 | are optimizing. */ | |
180 | static int mips_tune = CPU_UNKNOWN; | |
181 | ||
e013f690 TS |
182 | /* The ABI to use. */ |
183 | enum mips_abi_level | |
184 | { | |
185 | NO_ABI = 0, | |
186 | O32_ABI, | |
187 | O64_ABI, | |
188 | N32_ABI, | |
189 | N64_ABI, | |
190 | EABI_ABI | |
191 | }; | |
192 | ||
193 | static enum mips_abi_level mips_abi = NO_ABI; | |
252b5132 | 194 | |
2f4dcb11 | 195 | /* Whether we should mark the file EABI64 or EABI32. */ |
252b5132 RH |
196 | static int mips_eabi64 = 0; |
197 | ||
198 | /* If they asked for mips1 or mips2 and a cpu that is | |
bdaaa2e1 | 199 | mips3 or greater, then mark the object file 32BITMODE. */ |
252b5132 RH |
200 | static int mips_32bitmode = 0; |
201 | ||
bdaaa2e1 | 202 | /* True if -mgp32 was passed. */ |
c97ef257 AH |
203 | static int mips_gp32 = 0; |
204 | ||
ca4e0257 RS |
205 | /* True if -mfp32 was passed. */ |
206 | static int mips_fp32 = 0; | |
207 | ||
9ce8a5dd GRK |
208 | /* Some ISA's have delay slots for instructions which read or write |
209 | from a coprocessor (eg. mips1-mips3); some don't (eg mips4). | |
bdaaa2e1 | 210 | Return true if instructions marked INSN_LOAD_COPROC_DELAY, |
9ce8a5dd GRK |
211 | INSN_COPROC_MOVE_DELAY, or INSN_WRITE_COND_CODE actually have a |
212 | delay slot in this ISA. The uses of this macro assume that any | |
213 | ISA that has delay slots for one of these, has them for all. They | |
214 | also assume that ISAs which don't have delays for these insns, don't | |
bdaaa2e1 | 215 | have delays for the INSN_LOAD_MEMORY_DELAY instructions either. */ |
9ce8a5dd | 216 | #define ISA_HAS_COPROC_DELAYS(ISA) ( \ |
e7af610e NC |
217 | (ISA) == ISA_MIPS1 \ |
218 | || (ISA) == ISA_MIPS2 \ | |
219 | || (ISA) == ISA_MIPS3 \ | |
9ce8a5dd GRK |
220 | ) |
221 | ||
bdaaa2e1 | 222 | /* Return true if ISA supports 64 bit gp register instructions. */ |
9ce8a5dd | 223 | #define ISA_HAS_64BIT_REGS(ISA) ( \ |
e7af610e NC |
224 | (ISA) == ISA_MIPS3 \ |
225 | || (ISA) == ISA_MIPS4 \ | |
84ea6cf2 | 226 | || (ISA) == ISA_MIPS5 \ |
d1cf510e | 227 | || (ISA) == ISA_MIPS64 \ |
9ce8a5dd GRK |
228 | ) |
229 | ||
e013f690 TS |
230 | #define HAVE_32BIT_GPRS \ |
231 | (mips_gp32 \ | |
232 | || mips_abi == O32_ABI \ | |
233 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) | |
ca4e0257 | 234 | |
e013f690 TS |
235 | #define HAVE_32BIT_FPRS \ |
236 | (mips_fp32 \ | |
237 | || mips_abi == O32_ABI \ | |
238 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) | |
ca4e0257 RS |
239 | |
240 | #define HAVE_64BIT_GPRS (! HAVE_32BIT_GPRS) | |
241 | #define HAVE_64BIT_FPRS (! HAVE_32BIT_FPRS) | |
242 | ||
e013f690 TS |
243 | #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI) |
244 | ||
245 | #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI) | |
246 | ||
247 | /* We can only have 64bit addresses if the object file format | |
248 | supports it. */ | |
249 | #define HAVE_32BIT_ADDRESSES \ | |
250 | (HAVE_32BIT_GPRS \ | |
251 | || bfd_arch_bits_per_address (stdoutput) == 32 \ | |
252 | || ! HAVE_64BIT_OBJECTS) | |
253 | ||
254 | #define HAVE_64BIT_ADDRESSES (! HAVE_32BIT_ADDRESSES) | |
ca4e0257 | 255 | |
bdaaa2e1 | 256 | /* Whether the processor uses hardware interlocks to protect |
252b5132 | 257 | reads from the HI and LO registers, and thus does not |
ec68c924 | 258 | require nops to be inserted. */ |
252b5132 | 259 | |
ec68c924 | 260 | #define hilo_interlocks (mips_arch == CPU_R4010 \ |
252b5132 RH |
261 | ) |
262 | ||
263 | /* Whether the processor uses hardware interlocks to protect reads | |
264 | from the GPRs, and thus does not require nops to be inserted. */ | |
265 | #define gpr_interlocks \ | |
e7af610e | 266 | (mips_opts.isa != ISA_MIPS1 \ |
ec68c924 | 267 | || mips_arch == CPU_R3900) |
252b5132 RH |
268 | |
269 | /* As with other "interlocks" this is used by hardware that has FP | |
270 | (co-processor) interlocks. */ | |
bdaaa2e1 | 271 | /* Itbl support may require additional care here. */ |
ec68c924 | 272 | #define cop_interlocks (mips_arch == CPU_R4300 \ |
252b5132 RH |
273 | ) |
274 | ||
6b76fefe CM |
275 | /* Is this a mfhi or mflo instruction? */ |
276 | #define MF_HILO_INSN(PINFO) \ | |
277 | ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO)) | |
278 | ||
252b5132 RH |
279 | /* MIPS PIC level. */ |
280 | ||
e972090a NC |
281 | enum mips_pic_level |
282 | { | |
252b5132 RH |
283 | /* Do not generate PIC code. */ |
284 | NO_PIC, | |
285 | ||
286 | /* Generate PIC code as in Irix 4. This is not implemented, and I'm | |
287 | not sure what it is supposed to do. */ | |
288 | IRIX4_PIC, | |
289 | ||
290 | /* Generate PIC code as in the SVR4 MIPS ABI. */ | |
291 | SVR4_PIC, | |
292 | ||
293 | /* Generate PIC code without using a global offset table: the data | |
294 | segment has a maximum size of 64K, all data references are off | |
295 | the $gp register, and all text references are PC relative. This | |
296 | is used on some embedded systems. */ | |
297 | EMBEDDED_PIC | |
298 | }; | |
299 | ||
300 | static enum mips_pic_level mips_pic; | |
301 | ||
39c0a331 L |
302 | /* Warn about all NOPS that the assembler generates. */ |
303 | static int warn_nops = 0; | |
304 | ||
252b5132 RH |
305 | /* 1 if we should generate 32 bit offsets from the GP register in |
306 | SVR4_PIC mode. Currently has no meaning in other modes. */ | |
307 | static int mips_big_got; | |
308 | ||
309 | /* 1 if trap instructions should used for overflow rather than break | |
310 | instructions. */ | |
311 | static int mips_trap; | |
312 | ||
119d663a | 313 | /* 1 if double width floating point constants should not be constructed |
b6ff326e | 314 | by assembling two single width halves into two single width floating |
119d663a NC |
315 | point registers which just happen to alias the double width destination |
316 | register. On some architectures this aliasing can be disabled by a bit | |
d547a75e | 317 | in the status register, and the setting of this bit cannot be determined |
119d663a NC |
318 | automatically at assemble time. */ |
319 | static int mips_disable_float_construction; | |
320 | ||
252b5132 RH |
321 | /* Non-zero if any .set noreorder directives were used. */ |
322 | ||
323 | static int mips_any_noreorder; | |
324 | ||
6b76fefe CM |
325 | /* Non-zero if nops should be inserted when the register referenced in |
326 | an mfhi/mflo instruction is read in the next two instructions. */ | |
327 | static int mips_7000_hilo_fix; | |
328 | ||
252b5132 | 329 | /* The size of the small data section. */ |
156c2f8b | 330 | static unsigned int g_switch_value = 8; |
252b5132 RH |
331 | /* Whether the -G option was used. */ |
332 | static int g_switch_seen = 0; | |
333 | ||
334 | #define N_RMASK 0xc4 | |
335 | #define N_VFP 0xd4 | |
336 | ||
337 | /* If we can determine in advance that GP optimization won't be | |
338 | possible, we can skip the relaxation stuff that tries to produce | |
339 | GP-relative references. This makes delay slot optimization work | |
340 | better. | |
341 | ||
342 | This function can only provide a guess, but it seems to work for | |
fba2b7f9 GK |
343 | gcc output. It needs to guess right for gcc, otherwise gcc |
344 | will put what it thinks is a GP-relative instruction in a branch | |
345 | delay slot. | |
252b5132 RH |
346 | |
347 | I don't know if a fix is needed for the SVR4_PIC mode. I've only | |
348 | fixed it for the non-PIC mode. KR 95/04/07 */ | |
349 | static int nopic_need_relax PARAMS ((symbolS *, int)); | |
350 | ||
351 | /* handle of the OPCODE hash table */ | |
352 | static struct hash_control *op_hash = NULL; | |
353 | ||
354 | /* The opcode hash table we use for the mips16. */ | |
355 | static struct hash_control *mips16_op_hash = NULL; | |
356 | ||
357 | /* This array holds the chars that always start a comment. If the | |
358 | pre-processor is disabled, these aren't very useful */ | |
359 | const char comment_chars[] = "#"; | |
360 | ||
361 | /* This array holds the chars that only start a comment at the beginning of | |
362 | a line. If the line seems to have the form '# 123 filename' | |
363 | .line and .file directives will appear in the pre-processed output */ | |
364 | /* Note that input_file.c hand checks for '#' at the beginning of the | |
365 | first line of the input file. This is because the compiler outputs | |
bdaaa2e1 | 366 | #NO_APP at the beginning of its output. */ |
252b5132 RH |
367 | /* Also note that C style comments are always supported. */ |
368 | const char line_comment_chars[] = "#"; | |
369 | ||
bdaaa2e1 | 370 | /* This array holds machine specific line separator characters. */ |
63a0b638 | 371 | const char line_separator_chars[] = ";"; |
252b5132 RH |
372 | |
373 | /* Chars that can be used to separate mant from exp in floating point nums */ | |
374 | const char EXP_CHARS[] = "eE"; | |
375 | ||
376 | /* Chars that mean this number is a floating point constant */ | |
377 | /* As in 0f12.456 */ | |
378 | /* or 0d1.2345e12 */ | |
379 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; | |
380 | ||
381 | /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be | |
382 | changed in read.c . Ideally it shouldn't have to know about it at all, | |
383 | but nothing is ideal around here. | |
384 | */ | |
385 | ||
386 | static char *insn_error; | |
387 | ||
388 | static int auto_align = 1; | |
389 | ||
390 | /* When outputting SVR4 PIC code, the assembler needs to know the | |
391 | offset in the stack frame from which to restore the $gp register. | |
392 | This is set by the .cprestore pseudo-op, and saved in this | |
393 | variable. */ | |
394 | static offsetT mips_cprestore_offset = -1; | |
395 | ||
6478892d TS |
396 | /* Similiar for NewABI PIC code, where $gp is callee-saved. NewABI has some |
397 | more optimizations, it can use a register value instead of a memory-saved | |
398 | offset and even an other than GP as global pointer. */ | |
399 | static offsetT mips_cpreturn_offset = -1; | |
400 | static int mips_cpreturn_register = -1; | |
401 | static int mips_gp_register = GP; | |
402 | ||
252b5132 RH |
403 | /* This is the register which holds the stack frame, as set by the |
404 | .frame pseudo-op. This is needed to implement .cprestore. */ | |
405 | static int mips_frame_reg = SP; | |
406 | ||
407 | /* To output NOP instructions correctly, we need to keep information | |
408 | about the previous two instructions. */ | |
409 | ||
410 | /* Whether we are optimizing. The default value of 2 means to remove | |
411 | unneeded NOPs and swap branch instructions when possible. A value | |
412 | of 1 means to not swap branches. A value of 0 means to always | |
413 | insert NOPs. */ | |
414 | static int mips_optimize = 2; | |
415 | ||
416 | /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is | |
417 | equivalent to seeing no -g option at all. */ | |
418 | static int mips_debug = 0; | |
419 | ||
420 | /* The previous instruction. */ | |
421 | static struct mips_cl_insn prev_insn; | |
422 | ||
423 | /* The instruction before prev_insn. */ | |
424 | static struct mips_cl_insn prev_prev_insn; | |
425 | ||
426 | /* If we don't want information for prev_insn or prev_prev_insn, we | |
427 | point the insn_mo field at this dummy integer. */ | |
43841e91 | 428 | static const struct mips_opcode dummy_opcode = { NULL, NULL, 0, 0, 0, 0 }; |
252b5132 RH |
429 | |
430 | /* Non-zero if prev_insn is valid. */ | |
431 | static int prev_insn_valid; | |
432 | ||
433 | /* The frag for the previous instruction. */ | |
434 | static struct frag *prev_insn_frag; | |
435 | ||
436 | /* The offset into prev_insn_frag for the previous instruction. */ | |
437 | static long prev_insn_where; | |
438 | ||
439 | /* The reloc type for the previous instruction, if any. */ | |
f6688943 | 440 | static bfd_reloc_code_real_type prev_insn_reloc_type[3]; |
252b5132 RH |
441 | |
442 | /* The reloc for the previous instruction, if any. */ | |
f6688943 | 443 | static fixS *prev_insn_fixp[3]; |
252b5132 RH |
444 | |
445 | /* Non-zero if the previous instruction was in a delay slot. */ | |
446 | static int prev_insn_is_delay_slot; | |
447 | ||
448 | /* Non-zero if the previous instruction was in a .set noreorder. */ | |
449 | static int prev_insn_unreordered; | |
450 | ||
451 | /* Non-zero if the previous instruction uses an extend opcode (if | |
452 | mips16). */ | |
453 | static int prev_insn_extended; | |
454 | ||
455 | /* Non-zero if the previous previous instruction was in a .set | |
456 | noreorder. */ | |
457 | static int prev_prev_insn_unreordered; | |
458 | ||
459 | /* If this is set, it points to a frag holding nop instructions which | |
460 | were inserted before the start of a noreorder section. If those | |
461 | nops turn out to be unnecessary, the size of the frag can be | |
462 | decreased. */ | |
463 | static fragS *prev_nop_frag; | |
464 | ||
465 | /* The number of nop instructions we created in prev_nop_frag. */ | |
466 | static int prev_nop_frag_holds; | |
467 | ||
468 | /* The number of nop instructions that we know we need in | |
bdaaa2e1 | 469 | prev_nop_frag. */ |
252b5132 RH |
470 | static int prev_nop_frag_required; |
471 | ||
472 | /* The number of instructions we've seen since prev_nop_frag. */ | |
473 | static int prev_nop_frag_since; | |
474 | ||
475 | /* For ECOFF and ELF, relocations against symbols are done in two | |
476 | parts, with a HI relocation and a LO relocation. Each relocation | |
477 | has only 16 bits of space to store an addend. This means that in | |
478 | order for the linker to handle carries correctly, it must be able | |
479 | to locate both the HI and the LO relocation. This means that the | |
480 | relocations must appear in order in the relocation table. | |
481 | ||
482 | In order to implement this, we keep track of each unmatched HI | |
483 | relocation. We then sort them so that they immediately precede the | |
bdaaa2e1 | 484 | corresponding LO relocation. */ |
252b5132 | 485 | |
e972090a NC |
486 | struct mips_hi_fixup |
487 | { | |
252b5132 RH |
488 | /* Next HI fixup. */ |
489 | struct mips_hi_fixup *next; | |
490 | /* This fixup. */ | |
491 | fixS *fixp; | |
492 | /* The section this fixup is in. */ | |
493 | segT seg; | |
494 | }; | |
495 | ||
496 | /* The list of unmatched HI relocs. */ | |
497 | ||
498 | static struct mips_hi_fixup *mips_hi_fixup_list; | |
499 | ||
500 | /* Map normal MIPS register numbers to mips16 register numbers. */ | |
501 | ||
502 | #define X ILLEGAL_REG | |
e972090a NC |
503 | static const int mips32_to_16_reg_map[] = |
504 | { | |
252b5132 RH |
505 | X, X, 2, 3, 4, 5, 6, 7, |
506 | X, X, X, X, X, X, X, X, | |
507 | 0, 1, X, X, X, X, X, X, | |
508 | X, X, X, X, X, X, X, X | |
509 | }; | |
510 | #undef X | |
511 | ||
512 | /* Map mips16 register numbers to normal MIPS register numbers. */ | |
513 | ||
e972090a NC |
514 | static const unsigned int mips16_to_32_reg_map[] = |
515 | { | |
252b5132 RH |
516 | 16, 17, 2, 3, 4, 5, 6, 7 |
517 | }; | |
518 | \f | |
519 | /* Since the MIPS does not have multiple forms of PC relative | |
520 | instructions, we do not have to do relaxing as is done on other | |
521 | platforms. However, we do have to handle GP relative addressing | |
522 | correctly, which turns out to be a similar problem. | |
523 | ||
524 | Every macro that refers to a symbol can occur in (at least) two | |
525 | forms, one with GP relative addressing and one without. For | |
526 | example, loading a global variable into a register generally uses | |
527 | a macro instruction like this: | |
528 | lw $4,i | |
529 | If i can be addressed off the GP register (this is true if it is in | |
530 | the .sbss or .sdata section, or if it is known to be smaller than | |
531 | the -G argument) this will generate the following instruction: | |
532 | lw $4,i($gp) | |
533 | This instruction will use a GPREL reloc. If i can not be addressed | |
534 | off the GP register, the following instruction sequence will be used: | |
535 | lui $at,i | |
536 | lw $4,i($at) | |
537 | In this case the first instruction will have a HI16 reloc, and the | |
538 | second reloc will have a LO16 reloc. Both relocs will be against | |
539 | the symbol i. | |
540 | ||
541 | The issue here is that we may not know whether i is GP addressable | |
542 | until after we see the instruction that uses it. Therefore, we | |
543 | want to be able to choose the final instruction sequence only at | |
544 | the end of the assembly. This is similar to the way other | |
545 | platforms choose the size of a PC relative instruction only at the | |
546 | end of assembly. | |
547 | ||
548 | When generating position independent code we do not use GP | |
549 | addressing in quite the same way, but the issue still arises as | |
550 | external symbols and local symbols must be handled differently. | |
551 | ||
552 | We handle these issues by actually generating both possible | |
553 | instruction sequences. The longer one is put in a frag_var with | |
554 | type rs_machine_dependent. We encode what to do with the frag in | |
555 | the subtype field. We encode (1) the number of existing bytes to | |
556 | replace, (2) the number of new bytes to use, (3) the offset from | |
557 | the start of the existing bytes to the first reloc we must generate | |
558 | (that is, the offset is applied from the start of the existing | |
559 | bytes after they are replaced by the new bytes, if any), (4) the | |
560 | offset from the start of the existing bytes to the second reloc, | |
561 | (5) whether a third reloc is needed (the third reloc is always four | |
562 | bytes after the second reloc), and (6) whether to warn if this | |
563 | variant is used (this is sometimes needed if .set nomacro or .set | |
564 | noat is in effect). All these numbers are reasonably small. | |
565 | ||
566 | Generating two instruction sequences must be handled carefully to | |
567 | ensure that delay slots are handled correctly. Fortunately, there | |
568 | are a limited number of cases. When the second instruction | |
569 | sequence is generated, append_insn is directed to maintain the | |
570 | existing delay slot information, so it continues to apply to any | |
571 | code after the second instruction sequence. This means that the | |
572 | second instruction sequence must not impose any requirements not | |
573 | required by the first instruction sequence. | |
574 | ||
575 | These variant frags are then handled in functions called by the | |
576 | machine independent code. md_estimate_size_before_relax returns | |
577 | the final size of the frag. md_convert_frag sets up the final form | |
578 | of the frag. tc_gen_reloc adjust the first reloc and adds a second | |
579 | one if needed. */ | |
580 | #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \ | |
581 | ((relax_substateT) \ | |
582 | (((old) << 23) \ | |
583 | | ((new) << 16) \ | |
584 | | (((reloc1) + 64) << 9) \ | |
585 | | (((reloc2) + 64) << 2) \ | |
586 | | ((reloc3) ? (1 << 1) : 0) \ | |
587 | | ((warn) ? 1 : 0))) | |
588 | #define RELAX_OLD(i) (((i) >> 23) & 0x7f) | |
589 | #define RELAX_NEW(i) (((i) >> 16) & 0x7f) | |
9a41af64 TS |
590 | #define RELAX_RELOC1(i) ((valueT) (((i) >> 9) & 0x7f) - 64) |
591 | #define RELAX_RELOC2(i) ((valueT) (((i) >> 2) & 0x7f) - 64) | |
252b5132 RH |
592 | #define RELAX_RELOC3(i) (((i) >> 1) & 1) |
593 | #define RELAX_WARN(i) ((i) & 1) | |
594 | ||
595 | /* For mips16 code, we use an entirely different form of relaxation. | |
596 | mips16 supports two versions of most instructions which take | |
597 | immediate values: a small one which takes some small value, and a | |
598 | larger one which takes a 16 bit value. Since branches also follow | |
599 | this pattern, relaxing these values is required. | |
600 | ||
601 | We can assemble both mips16 and normal MIPS code in a single | |
602 | object. Therefore, we need to support this type of relaxation at | |
603 | the same time that we support the relaxation described above. We | |
604 | use the high bit of the subtype field to distinguish these cases. | |
605 | ||
606 | The information we store for this type of relaxation is the | |
607 | argument code found in the opcode file for this relocation, whether | |
608 | the user explicitly requested a small or extended form, and whether | |
609 | the relocation is in a jump or jal delay slot. That tells us the | |
610 | size of the value, and how it should be stored. We also store | |
611 | whether the fragment is considered to be extended or not. We also | |
612 | store whether this is known to be a branch to a different section, | |
613 | whether we have tried to relax this frag yet, and whether we have | |
614 | ever extended a PC relative fragment because of a shift count. */ | |
615 | #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \ | |
616 | (0x80000000 \ | |
617 | | ((type) & 0xff) \ | |
618 | | ((small) ? 0x100 : 0) \ | |
619 | | ((ext) ? 0x200 : 0) \ | |
620 | | ((dslot) ? 0x400 : 0) \ | |
621 | | ((jal_dslot) ? 0x800 : 0)) | |
622 | #define RELAX_MIPS16_P(i) (((i) & 0x80000000) != 0) | |
623 | #define RELAX_MIPS16_TYPE(i) ((i) & 0xff) | |
624 | #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0) | |
625 | #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0) | |
626 | #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0) | |
627 | #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0) | |
628 | #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0) | |
629 | #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000) | |
630 | #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000) | |
631 | #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0) | |
632 | #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000) | |
633 | #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000) | |
634 | \f | |
635 | /* Prototypes for static functions. */ | |
636 | ||
637 | #ifdef __STDC__ | |
638 | #define internalError() \ | |
639 | as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__) | |
640 | #else | |
641 | #define internalError() as_fatal (_("MIPS internal Error")); | |
642 | #endif | |
643 | ||
644 | enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG }; | |
645 | ||
646 | static int insn_uses_reg PARAMS ((struct mips_cl_insn *ip, | |
647 | unsigned int reg, enum mips_regclass class)); | |
156c2f8b | 648 | static int reg_needs_delay PARAMS ((unsigned int)); |
252b5132 RH |
649 | static void mips16_mark_labels PARAMS ((void)); |
650 | static void append_insn PARAMS ((char *place, | |
651 | struct mips_cl_insn * ip, | |
652 | expressionS * p, | |
f6688943 | 653 | bfd_reloc_code_real_type *r, |
252b5132 RH |
654 | boolean)); |
655 | static void mips_no_prev_insn PARAMS ((int)); | |
656 | static void mips_emit_delays PARAMS ((boolean)); | |
657 | #ifdef USE_STDARG | |
658 | static void macro_build PARAMS ((char *place, int *counter, expressionS * ep, | |
659 | const char *name, const char *fmt, | |
660 | ...)); | |
661 | #else | |
662 | static void macro_build (); | |
663 | #endif | |
664 | static void mips16_macro_build PARAMS ((char *, int *, expressionS *, | |
665 | const char *, const char *, | |
666 | va_list)); | |
667 | static void macro_build_lui PARAMS ((char *place, int *counter, | |
668 | expressionS * ep, int regnum)); | |
669 | static void set_at PARAMS ((int *counter, int reg, int unsignedp)); | |
670 | static void check_absolute_expr PARAMS ((struct mips_cl_insn * ip, | |
671 | expressionS *)); | |
672 | static void load_register PARAMS ((int *, int, expressionS *, int)); | |
d6bc6245 | 673 | static void load_address PARAMS ((int *, int, expressionS *, int, int *)); |
ea1fb5dc | 674 | static void move_register PARAMS ((int *, int, int)); |
252b5132 RH |
675 | static void macro PARAMS ((struct mips_cl_insn * ip)); |
676 | static void mips16_macro PARAMS ((struct mips_cl_insn * ip)); | |
677 | #ifdef LOSING_COMPILER | |
678 | static void macro2 PARAMS ((struct mips_cl_insn * ip)); | |
679 | #endif | |
680 | static void mips_ip PARAMS ((char *str, struct mips_cl_insn * ip)); | |
681 | static void mips16_ip PARAMS ((char *str, struct mips_cl_insn * ip)); | |
682 | static void mips16_immed PARAMS ((char *, unsigned int, int, offsetT, boolean, | |
683 | boolean, boolean, unsigned long *, | |
684 | boolean *, unsigned short *)); | |
ad8d3bb3 TS |
685 | static int my_getSmallParser PARAMS ((char **, unsigned int *, int *)); |
686 | static int my_getSmallExpression PARAMS ((expressionS *, char *)); | |
687 | static void my_getExpression PARAMS ((expressionS *, char *)); | |
e013f690 | 688 | static int support_64bit_objects PARAMS((void)); |
252b5132 RH |
689 | static symbolS *get_symbol PARAMS ((void)); |
690 | static void mips_align PARAMS ((int to, int fill, symbolS *label)); | |
691 | static void s_align PARAMS ((int)); | |
692 | static void s_change_sec PARAMS ((int)); | |
693 | static void s_cons PARAMS ((int)); | |
694 | static void s_float_cons PARAMS ((int)); | |
695 | static void s_mips_globl PARAMS ((int)); | |
696 | static void s_option PARAMS ((int)); | |
697 | static void s_mipsset PARAMS ((int)); | |
698 | static void s_abicalls PARAMS ((int)); | |
699 | static void s_cpload PARAMS ((int)); | |
6478892d TS |
700 | static void s_cpsetup PARAMS ((int)); |
701 | static void s_cplocal PARAMS ((int)); | |
252b5132 | 702 | static void s_cprestore PARAMS ((int)); |
6478892d TS |
703 | static void s_cpreturn PARAMS ((int)); |
704 | static void s_gpvalue PARAMS ((int)); | |
252b5132 RH |
705 | static void s_gpword PARAMS ((int)); |
706 | static void s_cpadd PARAMS ((int)); | |
707 | static void s_insn PARAMS ((int)); | |
708 | static void md_obj_begin PARAMS ((void)); | |
709 | static void md_obj_end PARAMS ((void)); | |
710 | static long get_number PARAMS ((void)); | |
711 | static void s_mips_ent PARAMS ((int)); | |
712 | static void s_mips_end PARAMS ((int)); | |
713 | static void s_mips_frame PARAMS ((int)); | |
714 | static void s_mips_mask PARAMS ((int)); | |
715 | static void s_mips_stab PARAMS ((int)); | |
716 | static void s_mips_weakext PARAMS ((int)); | |
717 | static void s_file PARAMS ((int)); | |
718 | static int mips16_extended_frag PARAMS ((fragS *, asection *, long)); | |
e7af610e NC |
719 | static const char *mips_isa_to_str PARAMS ((int)); |
720 | static const char *mips_cpu_to_str PARAMS ((int)); | |
252b5132 | 721 | static int validate_mips_insn PARAMS ((const struct mips_opcode *)); |
e87a0284 | 722 | static void show PARAMS ((FILE *, char *, int *, int *)); |
e7af610e | 723 | |
ad8d3bb3 | 724 | /* Return values of my_getSmallExpression(). */ |
fb1b3232 | 725 | |
ad8d3bb3 | 726 | enum small_ex_type |
fb1b3232 TS |
727 | { |
728 | S_EX_NONE = 0, | |
ad8d3bb3 TS |
729 | S_EX_REGISTER, |
730 | ||
731 | /* Direct relocation creation by %percent_op(). */ | |
732 | S_EX_HALF, | |
fb1b3232 | 733 | S_EX_HI, |
ad8d3bb3 TS |
734 | S_EX_LO, |
735 | S_EX_GP_REL, | |
736 | S_EX_GOT, | |
737 | S_EX_CALL16, | |
738 | S_EX_GOT_DISP, | |
739 | S_EX_GOT_PAGE, | |
740 | S_EX_GOT_OFST, | |
741 | S_EX_GOT_HI, | |
742 | S_EX_GOT_LO, | |
743 | S_EX_NEG, | |
fb1b3232 TS |
744 | S_EX_HIGHER, |
745 | S_EX_HIGHEST, | |
ad8d3bb3 TS |
746 | S_EX_CALL_HI, |
747 | S_EX_CALL_LO | |
fb1b3232 TS |
748 | }; |
749 | ||
e7af610e NC |
750 | /* Table and functions used to map between CPU/ISA names, and |
751 | ISA levels, and CPU numbers. */ | |
752 | ||
e972090a NC |
753 | struct mips_cpu_info |
754 | { | |
e7af610e NC |
755 | const char *name; /* CPU or ISA name. */ |
756 | int is_isa; /* Is this an ISA? (If 0, a CPU.) */ | |
757 | int isa; /* ISA level. */ | |
758 | int cpu; /* CPU number (default CPU if ISA). */ | |
759 | }; | |
760 | ||
761 | static const struct mips_cpu_info *mips_cpu_info_from_name PARAMS ((const char *)); | |
762 | static const struct mips_cpu_info *mips_cpu_info_from_isa PARAMS ((int)); | |
763 | static const struct mips_cpu_info *mips_cpu_info_from_cpu PARAMS ((int)); | |
252b5132 RH |
764 | \f |
765 | /* Pseudo-op table. | |
766 | ||
767 | The following pseudo-ops from the Kane and Heinrich MIPS book | |
768 | should be defined here, but are currently unsupported: .alias, | |
769 | .galive, .gjaldef, .gjrlive, .livereg, .noalias. | |
770 | ||
771 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
772 | specific to the type of debugging information being generated, and | |
773 | should be defined by the object format: .aent, .begin, .bend, | |
774 | .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp, | |
775 | .vreg. | |
776 | ||
777 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
778 | not MIPS CPU specific, but are also not specific to the object file | |
779 | format. This file is probably the best place to define them, but | |
780 | they are not currently supported: .asm0, .endr, .lab, .repeat, | |
781 | .struct. */ | |
782 | ||
e972090a NC |
783 | static const pseudo_typeS mips_pseudo_table[] = |
784 | { | |
beae10d5 | 785 | /* MIPS specific pseudo-ops. */ |
252b5132 RH |
786 | {"option", s_option, 0}, |
787 | {"set", s_mipsset, 0}, | |
788 | {"rdata", s_change_sec, 'r'}, | |
789 | {"sdata", s_change_sec, 's'}, | |
790 | {"livereg", s_ignore, 0}, | |
791 | {"abicalls", s_abicalls, 0}, | |
792 | {"cpload", s_cpload, 0}, | |
6478892d TS |
793 | {"cpsetup", s_cpsetup, 0}, |
794 | {"cplocal", s_cplocal, 0}, | |
252b5132 | 795 | {"cprestore", s_cprestore, 0}, |
6478892d TS |
796 | {"cpreturn", s_cpreturn, 0}, |
797 | {"gpvalue", s_gpvalue, 0}, | |
252b5132 RH |
798 | {"gpword", s_gpword, 0}, |
799 | {"cpadd", s_cpadd, 0}, | |
800 | {"insn", s_insn, 0}, | |
801 | ||
beae10d5 | 802 | /* Relatively generic pseudo-ops that happen to be used on MIPS |
252b5132 RH |
803 | chips. */ |
804 | {"asciiz", stringer, 1}, | |
805 | {"bss", s_change_sec, 'b'}, | |
806 | {"err", s_err, 0}, | |
807 | {"half", s_cons, 1}, | |
808 | {"dword", s_cons, 3}, | |
809 | {"weakext", s_mips_weakext, 0}, | |
810 | ||
beae10d5 | 811 | /* These pseudo-ops are defined in read.c, but must be overridden |
252b5132 RH |
812 | here for one reason or another. */ |
813 | {"align", s_align, 0}, | |
814 | {"byte", s_cons, 0}, | |
815 | {"data", s_change_sec, 'd'}, | |
816 | {"double", s_float_cons, 'd'}, | |
817 | {"float", s_float_cons, 'f'}, | |
818 | {"globl", s_mips_globl, 0}, | |
819 | {"global", s_mips_globl, 0}, | |
820 | {"hword", s_cons, 1}, | |
821 | {"int", s_cons, 2}, | |
822 | {"long", s_cons, 2}, | |
823 | {"octa", s_cons, 4}, | |
824 | {"quad", s_cons, 3}, | |
825 | {"short", s_cons, 1}, | |
826 | {"single", s_float_cons, 'f'}, | |
827 | {"stabn", s_mips_stab, 'n'}, | |
828 | {"text", s_change_sec, 't'}, | |
829 | {"word", s_cons, 2}, | |
add56521 L |
830 | |
831 | #ifdef MIPS_STABS_ELF | |
832 | { "extern", ecoff_directive_extern, 0}, | |
833 | #endif | |
834 | ||
43841e91 | 835 | { NULL, NULL, 0 }, |
252b5132 RH |
836 | }; |
837 | ||
e972090a NC |
838 | static const pseudo_typeS mips_nonecoff_pseudo_table[] = |
839 | { | |
beae10d5 KH |
840 | /* These pseudo-ops should be defined by the object file format. |
841 | However, a.out doesn't support them, so we have versions here. */ | |
252b5132 RH |
842 | {"aent", s_mips_ent, 1}, |
843 | {"bgnb", s_ignore, 0}, | |
844 | {"end", s_mips_end, 0}, | |
845 | {"endb", s_ignore, 0}, | |
846 | {"ent", s_mips_ent, 0}, | |
847 | {"file", s_file, 0}, | |
848 | {"fmask", s_mips_mask, 'F'}, | |
849 | {"frame", s_mips_frame, 0}, | |
850 | {"loc", s_ignore, 0}, | |
851 | {"mask", s_mips_mask, 'R'}, | |
852 | {"verstamp", s_ignore, 0}, | |
43841e91 | 853 | { NULL, NULL, 0 }, |
252b5132 RH |
854 | }; |
855 | ||
856 | extern void pop_insert PARAMS ((const pseudo_typeS *)); | |
857 | ||
858 | void | |
859 | mips_pop_insert () | |
860 | { | |
861 | pop_insert (mips_pseudo_table); | |
862 | if (! ECOFF_DEBUGGING) | |
863 | pop_insert (mips_nonecoff_pseudo_table); | |
864 | } | |
865 | \f | |
866 | /* Symbols labelling the current insn. */ | |
867 | ||
e972090a NC |
868 | struct insn_label_list |
869 | { | |
252b5132 RH |
870 | struct insn_label_list *next; |
871 | symbolS *label; | |
872 | }; | |
873 | ||
874 | static struct insn_label_list *insn_labels; | |
875 | static struct insn_label_list *free_insn_labels; | |
876 | ||
877 | static void mips_clear_insn_labels PARAMS ((void)); | |
878 | ||
879 | static inline void | |
880 | mips_clear_insn_labels () | |
881 | { | |
882 | register struct insn_label_list **pl; | |
883 | ||
884 | for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next) | |
885 | ; | |
886 | *pl = insn_labels; | |
887 | insn_labels = NULL; | |
888 | } | |
889 | \f | |
890 | static char *expr_end; | |
891 | ||
892 | /* Expressions which appear in instructions. These are set by | |
893 | mips_ip. */ | |
894 | ||
895 | static expressionS imm_expr; | |
896 | static expressionS offset_expr; | |
897 | ||
898 | /* Relocs associated with imm_expr and offset_expr. */ | |
899 | ||
f6688943 TS |
900 | static bfd_reloc_code_real_type imm_reloc[3] |
901 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
902 | static bfd_reloc_code_real_type offset_reloc[3] | |
903 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 RH |
904 | |
905 | /* This is set by mips_ip if imm_reloc is an unmatched HI16_S reloc. */ | |
906 | ||
907 | static boolean imm_unmatched_hi; | |
908 | ||
909 | /* These are set by mips16_ip if an explicit extension is used. */ | |
910 | ||
911 | static boolean mips16_small, mips16_ext; | |
912 | ||
913 | #ifdef MIPS_STABS_ELF | |
914 | /* The pdr segment for per procedure frame/regmask info */ | |
915 | ||
916 | static segT pdr_seg; | |
917 | #endif | |
918 | ||
e7af610e NC |
919 | static const char * |
920 | mips_isa_to_str (isa) | |
921 | int isa; | |
922 | { | |
923 | const struct mips_cpu_info *ci; | |
924 | static char s[20]; | |
925 | ||
926 | ci = mips_cpu_info_from_isa (isa); | |
927 | if (ci != NULL) | |
928 | return (ci->name); | |
929 | ||
930 | sprintf (s, "ISA#%d", isa); | |
931 | return s; | |
932 | } | |
933 | ||
934 | static const char * | |
156c2f8b NC |
935 | mips_cpu_to_str (cpu) |
936 | int cpu; | |
937 | { | |
e7af610e | 938 | const struct mips_cpu_info *ci; |
156c2f8b | 939 | static char s[16]; |
e7af610e NC |
940 | |
941 | ci = mips_cpu_info_from_cpu (cpu); | |
942 | if (ci != NULL) | |
943 | return (ci->name); | |
944 | ||
945 | sprintf (s, "CPU#%d", cpu); | |
946 | return s; | |
156c2f8b NC |
947 | } |
948 | ||
e013f690 TS |
949 | /* The default target format to use. */ |
950 | ||
951 | const char * | |
952 | mips_target_format () | |
953 | { | |
954 | switch (OUTPUT_FLAVOR) | |
955 | { | |
956 | case bfd_target_aout_flavour: | |
957 | return target_big_endian ? "a.out-mips-big" : "a.out-mips-little"; | |
958 | case bfd_target_ecoff_flavour: | |
959 | return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT; | |
960 | case bfd_target_coff_flavour: | |
961 | return "pe-mips"; | |
962 | case bfd_target_elf_flavour: | |
963 | #ifdef TE_TMIPS | |
964 | /* This is traditional mips */ | |
965 | return (target_big_endian | |
966 | ? (HAVE_64BIT_OBJECTS ? "elf64-tradbigmips" | |
967 | : "elf32-tradbigmips") | |
968 | : (HAVE_64BIT_OBJECTS ? "elf64-tradlittlemips" | |
969 | : "elf32-tradlittlemips")); | |
970 | #else | |
971 | return (target_big_endian | |
972 | ? (HAVE_64BIT_OBJECTS ? "elf64-bigmips" : "elf32-bigmips") | |
973 | : (HAVE_64BIT_OBJECTS ? "elf64-littlemips" | |
974 | : "elf32-littlemips")); | |
975 | #endif | |
976 | default: | |
977 | abort (); | |
978 | return NULL; | |
979 | } | |
980 | } | |
981 | ||
156c2f8b NC |
982 | /* This function is called once, at assembler startup time. It should |
983 | set up all the tables, etc. that the MD part of the assembler will need. */ | |
984 | ||
252b5132 RH |
985 | void |
986 | md_begin () | |
987 | { | |
252b5132 | 988 | register const char *retval = NULL; |
156c2f8b | 989 | int i = 0; |
252b5132 RH |
990 | const char *cpu; |
991 | char *a = NULL; | |
992 | int broken = 0; | |
993 | int mips_isa_from_cpu; | |
e7af610e NC |
994 | int target_cpu_had_mips16 = 0; |
995 | const struct mips_cpu_info *ci; | |
252b5132 | 996 | |
056350c6 NC |
997 | /* GP relative stuff not working for PE */ |
998 | if (strncmp (TARGET_OS, "pe", 2) == 0 | |
999 | && g_switch_value != 0) | |
1000 | { | |
1001 | if (g_switch_seen) | |
1002 | as_bad (_("-G not supported in this configuration.")); | |
1003 | g_switch_value = 0; | |
1004 | } | |
1005 | ||
252b5132 RH |
1006 | cpu = TARGET_CPU; |
1007 | if (strcmp (cpu + (sizeof TARGET_CPU) - 3, "el") == 0) | |
1008 | { | |
1009 | a = xmalloc (sizeof TARGET_CPU); | |
1010 | strcpy (a, TARGET_CPU); | |
1011 | a[(sizeof TARGET_CPU) - 3] = '\0'; | |
1012 | cpu = a; | |
1013 | } | |
1014 | ||
e7af610e | 1015 | if (strncmp (cpu, "mips16", sizeof "mips16" - 1) == 0) |
252b5132 | 1016 | { |
e7af610e NC |
1017 | target_cpu_had_mips16 = 1; |
1018 | cpu += sizeof "mips16" - 1; | |
252b5132 RH |
1019 | } |
1020 | ||
e7af610e NC |
1021 | if (mips_opts.mips16 < 0) |
1022 | mips_opts.mips16 = target_cpu_had_mips16; | |
252b5132 | 1023 | |
6dce9e24 TS |
1024 | /* Backward compatibility for historic -mcpu= option. Check for |
1025 | incompatible options, warn if -mcpu is used. */ | |
1026 | if (mips_cpu != CPU_UNKNOWN | |
1027 | && mips_arch != CPU_UNKNOWN | |
1028 | && mips_cpu != mips_arch) | |
1029 | { | |
1030 | as_fatal (_("The -mcpu option can't be used together with -march. " | |
1031 | "Use -mtune instead of -mcpu.")); | |
1032 | } | |
1033 | ||
1034 | if (mips_cpu != CPU_UNKNOWN | |
1035 | && mips_tune != CPU_UNKNOWN | |
1036 | && mips_cpu != mips_tune) | |
1037 | { | |
1038 | as_fatal (_("The -mcpu option can't be used together with -mtune. " | |
1039 | "Use -march instead of -mcpu.")); | |
1040 | } | |
1041 | ||
1042 | if (mips_arch == CPU_UNKNOWN && mips_cpu != CPU_UNKNOWN) | |
1043 | { | |
1044 | ci = mips_cpu_info_from_cpu (mips_cpu); | |
1045 | assert (ci != NULL); | |
1046 | mips_arch = ci->cpu; | |
1047 | as_warn (_("The -mcpu option is deprecated. Please use -march and " | |
1048 | "-mtune instead.")); | |
1049 | } | |
1050 | ||
ec68c924 | 1051 | /* At this point, mips_arch will either be CPU_UNKNOWN if no ARCH was |
e7af610e NC |
1052 | specified on the command line, or some other value if one was. |
1053 | Similarly, mips_opts.isa will be ISA_UNKNOWN if not specified on | |
1054 | the command line, or will be set otherwise if one was. */ | |
ec68c924 | 1055 | if (mips_arch != CPU_UNKNOWN && mips_opts.isa != ISA_UNKNOWN) |
252b5132 | 1056 | { |
1ff54a84 TS |
1057 | /* We have to check if the isa is the default isa of arch. Otherwise |
1058 | we'll get invalid object file headers. */ | |
1059 | ci = mips_cpu_info_from_cpu (mips_arch); | |
1060 | assert (ci != NULL); | |
1061 | if (mips_opts.isa != ci->isa) | |
1062 | { | |
1063 | /* This really should be an error instead of a warning, but old | |
1064 | compilers only have -mcpu which sets both arch and tune. For | |
1065 | now, we discard arch and preserve tune. */ | |
1066 | as_warn (_("The -march option is incompatible to -mipsN and " | |
1067 | "therefore ignored.")); | |
1068 | if (mips_tune == CPU_UNKNOWN) | |
1069 | mips_tune = mips_arch; | |
1070 | ci = mips_cpu_info_from_isa (mips_opts.isa); | |
1071 | assert (ci != NULL); | |
1072 | mips_arch = ci->cpu; | |
1073 | } | |
252b5132 | 1074 | } |
ec68c924 | 1075 | else if (mips_arch != CPU_UNKNOWN && mips_opts.isa == ISA_UNKNOWN) |
252b5132 | 1076 | { |
ec68c924 EC |
1077 | /* We have ARCH, we need ISA. */ |
1078 | ci = mips_cpu_info_from_cpu (mips_arch); | |
e7af610e NC |
1079 | assert (ci != NULL); |
1080 | mips_opts.isa = ci->isa; | |
1081 | } | |
ec68c924 | 1082 | else if (mips_arch == CPU_UNKNOWN && mips_opts.isa != ISA_UNKNOWN) |
e7af610e | 1083 | { |
ec68c924 | 1084 | /* We have ISA, we need default ARCH. */ |
e7af610e NC |
1085 | ci = mips_cpu_info_from_isa (mips_opts.isa); |
1086 | assert (ci != NULL); | |
ec68c924 EC |
1087 | mips_arch = ci->cpu; |
1088 | } | |
e7af610e NC |
1089 | else |
1090 | { | |
ec68c924 | 1091 | /* We need to set both ISA and ARCH from target cpu. */ |
e7af610e NC |
1092 | ci = mips_cpu_info_from_name (cpu); |
1093 | if (ci == NULL) | |
beae10d5 | 1094 | ci = mips_cpu_info_from_cpu (CPU_R3000); |
e7af610e NC |
1095 | assert (ci != NULL); |
1096 | mips_opts.isa = ci->isa; | |
ec68c924 | 1097 | mips_arch = ci->cpu; |
252b5132 RH |
1098 | } |
1099 | ||
ec68c924 EC |
1100 | if (mips_tune == CPU_UNKNOWN) |
1101 | mips_tune = mips_arch; | |
1102 | ||
1103 | ci = mips_cpu_info_from_cpu (mips_arch); | |
e7af610e NC |
1104 | assert (ci != NULL); |
1105 | mips_isa_from_cpu = ci->isa; | |
1106 | ||
252b5132 | 1107 | /* End of TARGET_CPU processing, get rid of malloced memory |
bdaaa2e1 | 1108 | if necessary. */ |
252b5132 RH |
1109 | cpu = NULL; |
1110 | if (a != NULL) | |
1111 | { | |
156c2f8b NC |
1112 | free (a); |
1113 | a = NULL; | |
252b5132 RH |
1114 | } |
1115 | ||
e7af610e | 1116 | if (mips_opts.isa == ISA_MIPS1 && mips_trap) |
252b5132 RH |
1117 | as_bad (_("trap exception not supported at ISA 1")); |
1118 | ||
1119 | /* Set the EABI kind based on the ISA before the user gets | |
1120 | to change the ISA with directives. This isn't really | |
bdaaa2e1 | 1121 | the best, but then neither is basing the abi on the isa. */ |
9ce8a5dd | 1122 | if (ISA_HAS_64BIT_REGS (mips_opts.isa) |
e013f690 | 1123 | && mips_abi == EABI_ABI) |
252b5132 RH |
1124 | mips_eabi64 = 1; |
1125 | ||
e7af610e NC |
1126 | /* If they asked for mips1 or mips2 and a cpu that is |
1127 | mips3 or greater, then mark the object file 32BITMODE. */ | |
1128 | if (mips_isa_from_cpu != ISA_UNKNOWN | |
1129 | && ! ISA_HAS_64BIT_REGS (mips_opts.isa) | |
1130 | && ISA_HAS_64BIT_REGS (mips_isa_from_cpu)) | |
1131 | mips_32bitmode = 1; | |
252b5132 | 1132 | |
ec68c924 | 1133 | if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, mips_arch)) |
252b5132 RH |
1134 | as_warn (_("Could not set architecture and machine")); |
1135 | ||
1136 | file_mips_isa = mips_opts.isa; | |
1137 | ||
1138 | op_hash = hash_new (); | |
1139 | ||
1140 | for (i = 0; i < NUMOPCODES;) | |
1141 | { | |
1142 | const char *name = mips_opcodes[i].name; | |
1143 | ||
1144 | retval = hash_insert (op_hash, name, (PTR) &mips_opcodes[i]); | |
1145 | if (retval != NULL) | |
1146 | { | |
1147 | fprintf (stderr, _("internal error: can't hash `%s': %s\n"), | |
1148 | mips_opcodes[i].name, retval); | |
1149 | /* Probably a memory allocation problem? Give up now. */ | |
1150 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
1151 | } | |
1152 | do | |
1153 | { | |
1154 | if (mips_opcodes[i].pinfo != INSN_MACRO) | |
1155 | { | |
1156 | if (!validate_mips_insn (&mips_opcodes[i])) | |
1157 | broken = 1; | |
1158 | } | |
1159 | ++i; | |
1160 | } | |
1161 | while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name)); | |
1162 | } | |
1163 | ||
1164 | mips16_op_hash = hash_new (); | |
1165 | ||
1166 | i = 0; | |
1167 | while (i < bfd_mips16_num_opcodes) | |
1168 | { | |
1169 | const char *name = mips16_opcodes[i].name; | |
1170 | ||
1171 | retval = hash_insert (mips16_op_hash, name, (PTR) &mips16_opcodes[i]); | |
1172 | if (retval != NULL) | |
1173 | as_fatal (_("internal: can't hash `%s': %s"), | |
1174 | mips16_opcodes[i].name, retval); | |
1175 | do | |
1176 | { | |
1177 | if (mips16_opcodes[i].pinfo != INSN_MACRO | |
1178 | && ((mips16_opcodes[i].match & mips16_opcodes[i].mask) | |
1179 | != mips16_opcodes[i].match)) | |
1180 | { | |
1181 | fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"), | |
1182 | mips16_opcodes[i].name, mips16_opcodes[i].args); | |
1183 | broken = 1; | |
1184 | } | |
1185 | ++i; | |
1186 | } | |
1187 | while (i < bfd_mips16_num_opcodes | |
1188 | && strcmp (mips16_opcodes[i].name, name) == 0); | |
1189 | } | |
1190 | ||
1191 | if (broken) | |
1192 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
1193 | ||
1194 | /* We add all the general register names to the symbol table. This | |
1195 | helps us detect invalid uses of them. */ | |
1196 | for (i = 0; i < 32; i++) | |
1197 | { | |
1198 | char buf[5]; | |
1199 | ||
1200 | sprintf (buf, "$%d", i); | |
1201 | symbol_table_insert (symbol_new (buf, reg_section, i, | |
1202 | &zero_address_frag)); | |
1203 | } | |
1204 | symbol_table_insert (symbol_new ("$fp", reg_section, FP, | |
1205 | &zero_address_frag)); | |
1206 | symbol_table_insert (symbol_new ("$sp", reg_section, SP, | |
1207 | &zero_address_frag)); | |
1208 | symbol_table_insert (symbol_new ("$gp", reg_section, GP, | |
1209 | &zero_address_frag)); | |
1210 | symbol_table_insert (symbol_new ("$at", reg_section, AT, | |
1211 | &zero_address_frag)); | |
1212 | symbol_table_insert (symbol_new ("$kt0", reg_section, KT0, | |
1213 | &zero_address_frag)); | |
1214 | symbol_table_insert (symbol_new ("$kt1", reg_section, KT1, | |
1215 | &zero_address_frag)); | |
1216 | symbol_table_insert (symbol_new ("$pc", reg_section, -1, | |
1217 | &zero_address_frag)); | |
1218 | ||
1219 | mips_no_prev_insn (false); | |
1220 | ||
1221 | mips_gprmask = 0; | |
1222 | mips_cprmask[0] = 0; | |
1223 | mips_cprmask[1] = 0; | |
1224 | mips_cprmask[2] = 0; | |
1225 | mips_cprmask[3] = 0; | |
1226 | ||
1227 | /* set the default alignment for the text section (2**2) */ | |
1228 | record_alignment (text_section, 2); | |
1229 | ||
1230 | if (USE_GLOBAL_POINTER_OPT) | |
1231 | bfd_set_gp_size (stdoutput, g_switch_value); | |
1232 | ||
1233 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
1234 | { | |
1235 | /* On a native system, sections must be aligned to 16 byte | |
1236 | boundaries. When configured for an embedded ELF target, we | |
1237 | don't bother. */ | |
1238 | if (strcmp (TARGET_OS, "elf") != 0) | |
1239 | { | |
1240 | (void) bfd_set_section_alignment (stdoutput, text_section, 4); | |
1241 | (void) bfd_set_section_alignment (stdoutput, data_section, 4); | |
1242 | (void) bfd_set_section_alignment (stdoutput, bss_section, 4); | |
1243 | } | |
1244 | ||
1245 | /* Create a .reginfo section for register masks and a .mdebug | |
1246 | section for debugging information. */ | |
1247 | { | |
1248 | segT seg; | |
1249 | subsegT subseg; | |
1250 | flagword flags; | |
1251 | segT sec; | |
1252 | ||
1253 | seg = now_seg; | |
1254 | subseg = now_subseg; | |
1255 | ||
1256 | /* The ABI says this section should be loaded so that the | |
1257 | running program can access it. However, we don't load it | |
1258 | if we are configured for an embedded target */ | |
1259 | flags = SEC_READONLY | SEC_DATA; | |
1260 | if (strcmp (TARGET_OS, "elf") != 0) | |
1261 | flags |= SEC_ALLOC | SEC_LOAD; | |
1262 | ||
e013f690 | 1263 | if (! HAVE_NEWABI) |
252b5132 RH |
1264 | { |
1265 | sec = subseg_new (".reginfo", (subsegT) 0); | |
1266 | ||
252b5132 RH |
1267 | (void) bfd_set_section_flags (stdoutput, sec, flags); |
1268 | (void) bfd_set_section_alignment (stdoutput, sec, 2); | |
bdaaa2e1 | 1269 | |
252b5132 RH |
1270 | #ifdef OBJ_ELF |
1271 | mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo)); | |
1272 | #endif | |
1273 | } | |
1274 | else | |
1275 | { | |
1276 | /* The 64-bit ABI uses a .MIPS.options section rather than | |
1277 | .reginfo section. */ | |
1278 | sec = subseg_new (".MIPS.options", (subsegT) 0); | |
1279 | (void) bfd_set_section_flags (stdoutput, sec, flags); | |
1280 | (void) bfd_set_section_alignment (stdoutput, sec, 3); | |
1281 | ||
1282 | #ifdef OBJ_ELF | |
1283 | /* Set up the option header. */ | |
1284 | { | |
1285 | Elf_Internal_Options opthdr; | |
1286 | char *f; | |
1287 | ||
1288 | opthdr.kind = ODK_REGINFO; | |
1289 | opthdr.size = (sizeof (Elf_External_Options) | |
1290 | + sizeof (Elf64_External_RegInfo)); | |
1291 | opthdr.section = 0; | |
1292 | opthdr.info = 0; | |
1293 | f = frag_more (sizeof (Elf_External_Options)); | |
1294 | bfd_mips_elf_swap_options_out (stdoutput, &opthdr, | |
1295 | (Elf_External_Options *) f); | |
1296 | ||
1297 | mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo)); | |
1298 | } | |
1299 | #endif | |
1300 | } | |
1301 | ||
1302 | if (ECOFF_DEBUGGING) | |
1303 | { | |
1304 | sec = subseg_new (".mdebug", (subsegT) 0); | |
1305 | (void) bfd_set_section_flags (stdoutput, sec, | |
1306 | SEC_HAS_CONTENTS | SEC_READONLY); | |
1307 | (void) bfd_set_section_alignment (stdoutput, sec, 2); | |
1308 | } | |
1309 | ||
1310 | #ifdef MIPS_STABS_ELF | |
1311 | pdr_seg = subseg_new (".pdr", (subsegT) 0); | |
1312 | (void) bfd_set_section_flags (stdoutput, pdr_seg, | |
1313 | SEC_READONLY | SEC_RELOC | SEC_DEBUGGING); | |
1314 | (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2); | |
1315 | #endif | |
1316 | ||
1317 | subseg_set (seg, subseg); | |
1318 | } | |
1319 | } | |
1320 | ||
1321 | if (! ECOFF_DEBUGGING) | |
1322 | md_obj_begin (); | |
1323 | } | |
1324 | ||
1325 | void | |
1326 | md_mips_end () | |
1327 | { | |
1328 | if (! ECOFF_DEBUGGING) | |
1329 | md_obj_end (); | |
1330 | } | |
1331 | ||
1332 | void | |
1333 | md_assemble (str) | |
1334 | char *str; | |
1335 | { | |
1336 | struct mips_cl_insn insn; | |
f6688943 TS |
1337 | bfd_reloc_code_real_type unused_reloc[3] |
1338 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 RH |
1339 | |
1340 | imm_expr.X_op = O_absent; | |
252b5132 RH |
1341 | imm_unmatched_hi = false; |
1342 | offset_expr.X_op = O_absent; | |
f6688943 TS |
1343 | imm_reloc[0] = BFD_RELOC_UNUSED; |
1344 | imm_reloc[1] = BFD_RELOC_UNUSED; | |
1345 | imm_reloc[2] = BFD_RELOC_UNUSED; | |
1346 | offset_reloc[0] = BFD_RELOC_UNUSED; | |
1347 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
1348 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
1349 | |
1350 | if (mips_opts.mips16) | |
1351 | mips16_ip (str, &insn); | |
1352 | else | |
1353 | { | |
1354 | mips_ip (str, &insn); | |
beae10d5 KH |
1355 | DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"), |
1356 | str, insn.insn_opcode)); | |
252b5132 RH |
1357 | } |
1358 | ||
1359 | if (insn_error) | |
1360 | { | |
1361 | as_bad ("%s `%s'", insn_error, str); | |
1362 | return; | |
1363 | } | |
1364 | ||
1365 | if (insn.insn_mo->pinfo == INSN_MACRO) | |
1366 | { | |
1367 | if (mips_opts.mips16) | |
1368 | mips16_macro (&insn); | |
1369 | else | |
1370 | macro (&insn); | |
1371 | } | |
1372 | else | |
1373 | { | |
1374 | if (imm_expr.X_op != O_absent) | |
1375 | append_insn ((char *) NULL, &insn, &imm_expr, imm_reloc, | |
1376 | imm_unmatched_hi); | |
1377 | else if (offset_expr.X_op != O_absent) | |
1378 | append_insn ((char *) NULL, &insn, &offset_expr, offset_reloc, false); | |
1379 | else | |
f6688943 | 1380 | append_insn ((char *) NULL, &insn, NULL, unused_reloc, false); |
252b5132 RH |
1381 | } |
1382 | } | |
1383 | ||
1384 | /* See whether instruction IP reads register REG. CLASS is the type | |
1385 | of register. */ | |
1386 | ||
1387 | static int | |
1388 | insn_uses_reg (ip, reg, class) | |
1389 | struct mips_cl_insn *ip; | |
1390 | unsigned int reg; | |
1391 | enum mips_regclass class; | |
1392 | { | |
1393 | if (class == MIPS16_REG) | |
1394 | { | |
1395 | assert (mips_opts.mips16); | |
1396 | reg = mips16_to_32_reg_map[reg]; | |
1397 | class = MIPS_GR_REG; | |
1398 | } | |
1399 | ||
1400 | /* Don't report on general register 0, since it never changes. */ | |
1401 | if (class == MIPS_GR_REG && reg == 0) | |
1402 | return 0; | |
1403 | ||
1404 | if (class == MIPS_FP_REG) | |
1405 | { | |
1406 | assert (! mips_opts.mips16); | |
1407 | /* If we are called with either $f0 or $f1, we must check $f0. | |
1408 | This is not optimal, because it will introduce an unnecessary | |
1409 | NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would | |
1410 | need to distinguish reading both $f0 and $f1 or just one of | |
1411 | them. Note that we don't have to check the other way, | |
1412 | because there is no instruction that sets both $f0 and $f1 | |
1413 | and requires a delay. */ | |
1414 | if ((ip->insn_mo->pinfo & INSN_READ_FPR_S) | |
1415 | && ((((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS) &~(unsigned)1) | |
1416 | == (reg &~ (unsigned) 1))) | |
1417 | return 1; | |
1418 | if ((ip->insn_mo->pinfo & INSN_READ_FPR_T) | |
1419 | && ((((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT) &~(unsigned)1) | |
1420 | == (reg &~ (unsigned) 1))) | |
1421 | return 1; | |
1422 | } | |
1423 | else if (! mips_opts.mips16) | |
1424 | { | |
1425 | if ((ip->insn_mo->pinfo & INSN_READ_GPR_S) | |
1426 | && ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == reg) | |
1427 | return 1; | |
1428 | if ((ip->insn_mo->pinfo & INSN_READ_GPR_T) | |
1429 | && ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT) == reg) | |
1430 | return 1; | |
1431 | } | |
1432 | else | |
1433 | { | |
1434 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_X) | |
1435 | && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_RX) | |
1436 | & MIPS16OP_MASK_RX)] | |
1437 | == reg)) | |
1438 | return 1; | |
1439 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Y) | |
1440 | && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_RY) | |
1441 | & MIPS16OP_MASK_RY)] | |
1442 | == reg)) | |
1443 | return 1; | |
1444 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Z) | |
1445 | && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z) | |
1446 | & MIPS16OP_MASK_MOVE32Z)] | |
1447 | == reg)) | |
1448 | return 1; | |
1449 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_T) && reg == TREG) | |
1450 | return 1; | |
1451 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_SP) && reg == SP) | |
1452 | return 1; | |
1453 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_31) && reg == RA) | |
1454 | return 1; | |
1455 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_GPR_X) | |
1456 | && ((ip->insn_opcode >> MIPS16OP_SH_REGR32) | |
1457 | & MIPS16OP_MASK_REGR32) == reg) | |
1458 | return 1; | |
1459 | } | |
1460 | ||
1461 | return 0; | |
1462 | } | |
1463 | ||
1464 | /* This function returns true if modifying a register requires a | |
1465 | delay. */ | |
1466 | ||
1467 | static int | |
1468 | reg_needs_delay (reg) | |
156c2f8b | 1469 | unsigned int reg; |
252b5132 RH |
1470 | { |
1471 | unsigned long prev_pinfo; | |
1472 | ||
1473 | prev_pinfo = prev_insn.insn_mo->pinfo; | |
1474 | if (! mips_opts.noreorder | |
9ce8a5dd | 1475 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 RH |
1476 | && ((prev_pinfo & INSN_LOAD_COPROC_DELAY) |
1477 | || (! gpr_interlocks | |
1478 | && (prev_pinfo & INSN_LOAD_MEMORY_DELAY)))) | |
1479 | { | |
1480 | /* A load from a coprocessor or from memory. All load | |
1481 | delays delay the use of general register rt for one | |
1482 | instruction on the r3000. The r6000 and r4000 use | |
1483 | interlocks. */ | |
bdaaa2e1 | 1484 | /* Itbl support may require additional care here. */ |
252b5132 RH |
1485 | know (prev_pinfo & INSN_WRITE_GPR_T); |
1486 | if (reg == ((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT)) | |
1487 | return 1; | |
1488 | } | |
1489 | ||
1490 | return 0; | |
1491 | } | |
1492 | ||
1493 | /* Mark instruction labels in mips16 mode. This permits the linker to | |
1494 | handle them specially, such as generating jalx instructions when | |
1495 | needed. We also make them odd for the duration of the assembly, in | |
1496 | order to generate the right sort of code. We will make them even | |
1497 | in the adjust_symtab routine, while leaving them marked. This is | |
1498 | convenient for the debugger and the disassembler. The linker knows | |
1499 | to make them odd again. */ | |
1500 | ||
1501 | static void | |
1502 | mips16_mark_labels () | |
1503 | { | |
1504 | if (mips_opts.mips16) | |
1505 | { | |
1506 | struct insn_label_list *l; | |
98aa84af | 1507 | valueT val; |
252b5132 RH |
1508 | |
1509 | for (l = insn_labels; l != NULL; l = l->next) | |
1510 | { | |
1511 | #ifdef OBJ_ELF | |
1512 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
1513 | S_SET_OTHER (l->label, STO_MIPS16); | |
1514 | #endif | |
98aa84af AM |
1515 | val = S_GET_VALUE (l->label); |
1516 | if ((val & 1) == 0) | |
1517 | S_SET_VALUE (l->label, val + 1); | |
252b5132 RH |
1518 | } |
1519 | } | |
1520 | } | |
1521 | ||
1522 | /* Output an instruction. PLACE is where to put the instruction; if | |
1523 | it is NULL, this uses frag_more to get room. IP is the instruction | |
1524 | information. ADDRESS_EXPR is an operand of the instruction to be | |
1525 | used with RELOC_TYPE. */ | |
1526 | ||
1527 | static void | |
1528 | append_insn (place, ip, address_expr, reloc_type, unmatched_hi) | |
1529 | char *place; | |
1530 | struct mips_cl_insn *ip; | |
1531 | expressionS *address_expr; | |
f6688943 | 1532 | bfd_reloc_code_real_type *reloc_type; |
252b5132 RH |
1533 | boolean unmatched_hi; |
1534 | { | |
1535 | register unsigned long prev_pinfo, pinfo; | |
1536 | char *f; | |
f6688943 | 1537 | fixS *fixp[3]; |
252b5132 RH |
1538 | int nops = 0; |
1539 | ||
1540 | /* Mark instruction labels in mips16 mode. */ | |
1541 | if (mips_opts.mips16) | |
1542 | mips16_mark_labels (); | |
1543 | ||
1544 | prev_pinfo = prev_insn.insn_mo->pinfo; | |
1545 | pinfo = ip->insn_mo->pinfo; | |
1546 | ||
1547 | if (place == NULL && (! mips_opts.noreorder || prev_nop_frag != NULL)) | |
1548 | { | |
1549 | int prev_prev_nop; | |
1550 | ||
1551 | /* If the previous insn required any delay slots, see if we need | |
1552 | to insert a NOP or two. There are eight kinds of possible | |
1553 | hazards, of which an instruction can have at most one type. | |
1554 | (1) a load from memory delay | |
1555 | (2) a load from a coprocessor delay | |
1556 | (3) an unconditional branch delay | |
1557 | (4) a conditional branch delay | |
1558 | (5) a move to coprocessor register delay | |
1559 | (6) a load coprocessor register from memory delay | |
1560 | (7) a coprocessor condition code delay | |
1561 | (8) a HI/LO special register delay | |
1562 | ||
1563 | There are a lot of optimizations we could do that we don't. | |
1564 | In particular, we do not, in general, reorder instructions. | |
1565 | If you use gcc with optimization, it will reorder | |
1566 | instructions and generally do much more optimization then we | |
1567 | do here; repeating all that work in the assembler would only | |
1568 | benefit hand written assembly code, and does not seem worth | |
1569 | it. */ | |
1570 | ||
1571 | /* This is how a NOP is emitted. */ | |
1572 | #define emit_nop() \ | |
1573 | (mips_opts.mips16 \ | |
1574 | ? md_number_to_chars (frag_more (2), 0x6500, 2) \ | |
1575 | : md_number_to_chars (frag_more (4), 0, 4)) | |
1576 | ||
1577 | /* The previous insn might require a delay slot, depending upon | |
1578 | the contents of the current insn. */ | |
1579 | if (! mips_opts.mips16 | |
9ce8a5dd | 1580 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 RH |
1581 | && (((prev_pinfo & INSN_LOAD_COPROC_DELAY) |
1582 | && ! cop_interlocks) | |
1583 | || (! gpr_interlocks | |
1584 | && (prev_pinfo & INSN_LOAD_MEMORY_DELAY)))) | |
1585 | { | |
1586 | /* A load from a coprocessor or from memory. All load | |
1587 | delays delay the use of general register rt for one | |
1588 | instruction on the r3000. The r6000 and r4000 use | |
1589 | interlocks. */ | |
beae10d5 | 1590 | /* Itbl support may require additional care here. */ |
252b5132 RH |
1591 | know (prev_pinfo & INSN_WRITE_GPR_T); |
1592 | if (mips_optimize == 0 | |
1593 | || insn_uses_reg (ip, | |
1594 | ((prev_insn.insn_opcode >> OP_SH_RT) | |
1595 | & OP_MASK_RT), | |
1596 | MIPS_GR_REG)) | |
1597 | ++nops; | |
1598 | } | |
1599 | else if (! mips_opts.mips16 | |
9ce8a5dd | 1600 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 | 1601 | && (((prev_pinfo & INSN_COPROC_MOVE_DELAY) |
beae10d5 | 1602 | && ! cop_interlocks) |
e7af610e | 1603 | || (mips_opts.isa == ISA_MIPS1 |
252b5132 RH |
1604 | && (prev_pinfo & INSN_COPROC_MEMORY_DELAY)))) |
1605 | { | |
1606 | /* A generic coprocessor delay. The previous instruction | |
1607 | modified a coprocessor general or control register. If | |
1608 | it modified a control register, we need to avoid any | |
1609 | coprocessor instruction (this is probably not always | |
1610 | required, but it sometimes is). If it modified a general | |
1611 | register, we avoid using that register. | |
1612 | ||
1613 | On the r6000 and r4000 loading a coprocessor register | |
1614 | from memory is interlocked, and does not require a delay. | |
1615 | ||
1616 | This case is not handled very well. There is no special | |
1617 | knowledge of CP0 handling, and the coprocessors other | |
1618 | than the floating point unit are not distinguished at | |
1619 | all. */ | |
1620 | /* Itbl support may require additional care here. FIXME! | |
bdaaa2e1 | 1621 | Need to modify this to include knowledge about |
252b5132 RH |
1622 | user specified delays! */ |
1623 | if (prev_pinfo & INSN_WRITE_FPR_T) | |
1624 | { | |
1625 | if (mips_optimize == 0 | |
1626 | || insn_uses_reg (ip, | |
1627 | ((prev_insn.insn_opcode >> OP_SH_FT) | |
1628 | & OP_MASK_FT), | |
1629 | MIPS_FP_REG)) | |
1630 | ++nops; | |
1631 | } | |
1632 | else if (prev_pinfo & INSN_WRITE_FPR_S) | |
1633 | { | |
1634 | if (mips_optimize == 0 | |
1635 | || insn_uses_reg (ip, | |
1636 | ((prev_insn.insn_opcode >> OP_SH_FS) | |
1637 | & OP_MASK_FS), | |
1638 | MIPS_FP_REG)) | |
1639 | ++nops; | |
1640 | } | |
1641 | else | |
1642 | { | |
1643 | /* We don't know exactly what the previous instruction | |
1644 | does. If the current instruction uses a coprocessor | |
1645 | register, we must insert a NOP. If previous | |
1646 | instruction may set the condition codes, and the | |
1647 | current instruction uses them, we must insert two | |
1648 | NOPS. */ | |
bdaaa2e1 | 1649 | /* Itbl support may require additional care here. */ |
252b5132 RH |
1650 | if (mips_optimize == 0 |
1651 | || ((prev_pinfo & INSN_WRITE_COND_CODE) | |
1652 | && (pinfo & INSN_READ_COND_CODE))) | |
1653 | nops += 2; | |
1654 | else if (pinfo & INSN_COP) | |
1655 | ++nops; | |
1656 | } | |
1657 | } | |
1658 | else if (! mips_opts.mips16 | |
9ce8a5dd | 1659 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 RH |
1660 | && (prev_pinfo & INSN_WRITE_COND_CODE) |
1661 | && ! cop_interlocks) | |
1662 | { | |
1663 | /* The previous instruction sets the coprocessor condition | |
1664 | codes, but does not require a general coprocessor delay | |
1665 | (this means it is a floating point comparison | |
1666 | instruction). If this instruction uses the condition | |
1667 | codes, we need to insert a single NOP. */ | |
beae10d5 | 1668 | /* Itbl support may require additional care here. */ |
252b5132 RH |
1669 | if (mips_optimize == 0 |
1670 | || (pinfo & INSN_READ_COND_CODE)) | |
1671 | ++nops; | |
1672 | } | |
6b76fefe CM |
1673 | |
1674 | /* If we're fixing up mfhi/mflo for the r7000 and the | |
1675 | previous insn was an mfhi/mflo and the current insn | |
1676 | reads the register that the mfhi/mflo wrote to, then | |
1677 | insert two nops. */ | |
1678 | ||
1679 | else if (mips_7000_hilo_fix | |
1680 | && MF_HILO_INSN (prev_pinfo) | |
1681 | && insn_uses_reg (ip, ((prev_insn.insn_opcode >> OP_SH_RD) | |
beae10d5 KH |
1682 | & OP_MASK_RD), |
1683 | MIPS_GR_REG)) | |
6b76fefe CM |
1684 | { |
1685 | nops += 2; | |
1686 | } | |
1687 | ||
1688 | /* If we're fixing up mfhi/mflo for the r7000 and the | |
1689 | 2nd previous insn was an mfhi/mflo and the current insn | |
1690 | reads the register that the mfhi/mflo wrote to, then | |
1691 | insert one nop. */ | |
1692 | ||
1693 | else if (mips_7000_hilo_fix | |
1694 | && MF_HILO_INSN (prev_prev_insn.insn_opcode) | |
1695 | && insn_uses_reg (ip, ((prev_prev_insn.insn_opcode >> OP_SH_RD) | |
1696 | & OP_MASK_RD), | |
1697 | MIPS_GR_REG)) | |
bdaaa2e1 | 1698 | |
6b76fefe CM |
1699 | { |
1700 | nops += 1; | |
1701 | } | |
bdaaa2e1 | 1702 | |
252b5132 RH |
1703 | else if (prev_pinfo & INSN_READ_LO) |
1704 | { | |
1705 | /* The previous instruction reads the LO register; if the | |
1706 | current instruction writes to the LO register, we must | |
bdaaa2e1 KH |
1707 | insert two NOPS. Some newer processors have interlocks. |
1708 | Also the tx39's multiply instructions can be exectuted | |
252b5132 | 1709 | immediatly after a read from HI/LO (without the delay), |
bdaaa2e1 KH |
1710 | though the tx39's divide insns still do require the |
1711 | delay. */ | |
252b5132 | 1712 | if (! (hilo_interlocks |
ec68c924 | 1713 | || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT))) |
252b5132 RH |
1714 | && (mips_optimize == 0 |
1715 | || (pinfo & INSN_WRITE_LO))) | |
1716 | nops += 2; | |
1717 | /* Most mips16 branch insns don't have a delay slot. | |
1718 | If a read from LO is immediately followed by a branch | |
1719 | to a write to LO we have a read followed by a write | |
1720 | less than 2 insns away. We assume the target of | |
1721 | a branch might be a write to LO, and insert a nop | |
bdaaa2e1 | 1722 | between a read and an immediately following branch. */ |
252b5132 RH |
1723 | else if (mips_opts.mips16 |
1724 | && (mips_optimize == 0 | |
1725 | || (pinfo & MIPS16_INSN_BRANCH))) | |
1726 | nops += 1; | |
1727 | } | |
1728 | else if (prev_insn.insn_mo->pinfo & INSN_READ_HI) | |
1729 | { | |
1730 | /* The previous instruction reads the HI register; if the | |
1731 | current instruction writes to the HI register, we must | |
1732 | insert a NOP. Some newer processors have interlocks. | |
bdaaa2e1 | 1733 | Also the note tx39's multiply above. */ |
252b5132 | 1734 | if (! (hilo_interlocks |
ec68c924 | 1735 | || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT))) |
252b5132 RH |
1736 | && (mips_optimize == 0 |
1737 | || (pinfo & INSN_WRITE_HI))) | |
1738 | nops += 2; | |
1739 | /* Most mips16 branch insns don't have a delay slot. | |
1740 | If a read from HI is immediately followed by a branch | |
1741 | to a write to HI we have a read followed by a write | |
1742 | less than 2 insns away. We assume the target of | |
1743 | a branch might be a write to HI, and insert a nop | |
bdaaa2e1 | 1744 | between a read and an immediately following branch. */ |
252b5132 RH |
1745 | else if (mips_opts.mips16 |
1746 | && (mips_optimize == 0 | |
1747 | || (pinfo & MIPS16_INSN_BRANCH))) | |
1748 | nops += 1; | |
1749 | } | |
1750 | ||
1751 | /* If the previous instruction was in a noreorder section, then | |
1752 | we don't want to insert the nop after all. */ | |
bdaaa2e1 | 1753 | /* Itbl support may require additional care here. */ |
252b5132 RH |
1754 | if (prev_insn_unreordered) |
1755 | nops = 0; | |
1756 | ||
1757 | /* There are two cases which require two intervening | |
1758 | instructions: 1) setting the condition codes using a move to | |
1759 | coprocessor instruction which requires a general coprocessor | |
1760 | delay and then reading the condition codes 2) reading the HI | |
1761 | or LO register and then writing to it (except on processors | |
1762 | which have interlocks). If we are not already emitting a NOP | |
1763 | instruction, we must check for these cases compared to the | |
1764 | instruction previous to the previous instruction. */ | |
1765 | if ((! mips_opts.mips16 | |
9ce8a5dd | 1766 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 RH |
1767 | && (prev_prev_insn.insn_mo->pinfo & INSN_COPROC_MOVE_DELAY) |
1768 | && (prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE) | |
1769 | && (pinfo & INSN_READ_COND_CODE) | |
1770 | && ! cop_interlocks) | |
1771 | || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_LO) | |
1772 | && (pinfo & INSN_WRITE_LO) | |
1773 | && ! (hilo_interlocks | |
ec68c924 | 1774 | || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT)))) |
252b5132 RH |
1775 | || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI) |
1776 | && (pinfo & INSN_WRITE_HI) | |
1777 | && ! (hilo_interlocks | |
ec68c924 | 1778 | || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT))))) |
252b5132 RH |
1779 | prev_prev_nop = 1; |
1780 | else | |
1781 | prev_prev_nop = 0; | |
1782 | ||
1783 | if (prev_prev_insn_unreordered) | |
1784 | prev_prev_nop = 0; | |
1785 | ||
1786 | if (prev_prev_nop && nops == 0) | |
1787 | ++nops; | |
1788 | ||
1789 | /* If we are being given a nop instruction, don't bother with | |
1790 | one of the nops we would otherwise output. This will only | |
1791 | happen when a nop instruction is used with mips_optimize set | |
1792 | to 0. */ | |
1793 | if (nops > 0 | |
1794 | && ! mips_opts.noreorder | |
156c2f8b | 1795 | && ip->insn_opcode == (unsigned) (mips_opts.mips16 ? 0x6500 : 0)) |
252b5132 RH |
1796 | --nops; |
1797 | ||
1798 | /* Now emit the right number of NOP instructions. */ | |
1799 | if (nops > 0 && ! mips_opts.noreorder) | |
1800 | { | |
1801 | fragS *old_frag; | |
1802 | unsigned long old_frag_offset; | |
1803 | int i; | |
1804 | struct insn_label_list *l; | |
1805 | ||
1806 | old_frag = frag_now; | |
1807 | old_frag_offset = frag_now_fix (); | |
1808 | ||
1809 | for (i = 0; i < nops; i++) | |
1810 | emit_nop (); | |
1811 | ||
1812 | if (listing) | |
1813 | { | |
1814 | listing_prev_line (); | |
1815 | /* We may be at the start of a variant frag. In case we | |
1816 | are, make sure there is enough space for the frag | |
1817 | after the frags created by listing_prev_line. The | |
1818 | argument to frag_grow here must be at least as large | |
1819 | as the argument to all other calls to frag_grow in | |
1820 | this file. We don't have to worry about being in the | |
1821 | middle of a variant frag, because the variants insert | |
1822 | all needed nop instructions themselves. */ | |
1823 | frag_grow (40); | |
1824 | } | |
1825 | ||
1826 | for (l = insn_labels; l != NULL; l = l->next) | |
1827 | { | |
98aa84af AM |
1828 | valueT val; |
1829 | ||
252b5132 | 1830 | assert (S_GET_SEGMENT (l->label) == now_seg); |
49309057 | 1831 | symbol_set_frag (l->label, frag_now); |
98aa84af | 1832 | val = (valueT) frag_now_fix (); |
252b5132 RH |
1833 | /* mips16 text labels are stored as odd. */ |
1834 | if (mips_opts.mips16) | |
98aa84af AM |
1835 | val += 1; |
1836 | S_SET_VALUE (l->label, val); | |
252b5132 RH |
1837 | } |
1838 | ||
1839 | #ifndef NO_ECOFF_DEBUGGING | |
1840 | if (ECOFF_DEBUGGING) | |
1841 | ecoff_fix_loc (old_frag, old_frag_offset); | |
1842 | #endif | |
1843 | } | |
1844 | else if (prev_nop_frag != NULL) | |
1845 | { | |
1846 | /* We have a frag holding nops we may be able to remove. If | |
1847 | we don't need any nops, we can decrease the size of | |
1848 | prev_nop_frag by the size of one instruction. If we do | |
bdaaa2e1 | 1849 | need some nops, we count them in prev_nops_required. */ |
252b5132 RH |
1850 | if (prev_nop_frag_since == 0) |
1851 | { | |
1852 | if (nops == 0) | |
1853 | { | |
1854 | prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4; | |
1855 | --prev_nop_frag_holds; | |
1856 | } | |
1857 | else | |
1858 | prev_nop_frag_required += nops; | |
1859 | } | |
1860 | else | |
1861 | { | |
1862 | if (prev_prev_nop == 0) | |
1863 | { | |
1864 | prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4; | |
1865 | --prev_nop_frag_holds; | |
1866 | } | |
1867 | else | |
1868 | ++prev_nop_frag_required; | |
1869 | } | |
1870 | ||
1871 | if (prev_nop_frag_holds <= prev_nop_frag_required) | |
1872 | prev_nop_frag = NULL; | |
1873 | ||
1874 | ++prev_nop_frag_since; | |
1875 | ||
1876 | /* Sanity check: by the time we reach the second instruction | |
1877 | after prev_nop_frag, we should have used up all the nops | |
1878 | one way or another. */ | |
1879 | assert (prev_nop_frag_since <= 1 || prev_nop_frag == NULL); | |
1880 | } | |
1881 | } | |
1882 | ||
f6688943 | 1883 | if (*reloc_type > BFD_RELOC_UNUSED) |
252b5132 RH |
1884 | { |
1885 | /* We need to set up a variant frag. */ | |
1886 | assert (mips_opts.mips16 && address_expr != NULL); | |
1887 | f = frag_var (rs_machine_dependent, 4, 0, | |
f6688943 | 1888 | RELAX_MIPS16_ENCODE (*reloc_type - BFD_RELOC_UNUSED, |
252b5132 RH |
1889 | mips16_small, mips16_ext, |
1890 | (prev_pinfo | |
1891 | & INSN_UNCOND_BRANCH_DELAY), | |
f6688943 | 1892 | (*prev_insn_reloc_type |
252b5132 RH |
1893 | == BFD_RELOC_MIPS16_JMP)), |
1894 | make_expr_symbol (address_expr), (offsetT) 0, | |
1895 | (char *) NULL); | |
1896 | } | |
1897 | else if (place != NULL) | |
1898 | f = place; | |
1899 | else if (mips_opts.mips16 | |
1900 | && ! ip->use_extend | |
f6688943 | 1901 | && *reloc_type != BFD_RELOC_MIPS16_JMP) |
252b5132 RH |
1902 | { |
1903 | /* Make sure there is enough room to swap this instruction with | |
1904 | a following jump instruction. */ | |
1905 | frag_grow (6); | |
1906 | f = frag_more (2); | |
1907 | } | |
1908 | else | |
1909 | { | |
1910 | if (mips_opts.mips16 | |
1911 | && mips_opts.noreorder | |
1912 | && (prev_pinfo & INSN_UNCOND_BRANCH_DELAY) != 0) | |
1913 | as_warn (_("extended instruction in delay slot")); | |
1914 | ||
1915 | f = frag_more (4); | |
1916 | } | |
1917 | ||
f6688943 TS |
1918 | fixp[0] = fixp[1] = fixp[2] = NULL; |
1919 | if (address_expr != NULL && *reloc_type < BFD_RELOC_UNUSED) | |
252b5132 RH |
1920 | { |
1921 | if (address_expr->X_op == O_constant) | |
1922 | { | |
f6688943 TS |
1923 | unsigned long tmp; |
1924 | ||
1925 | switch (*reloc_type) | |
252b5132 RH |
1926 | { |
1927 | case BFD_RELOC_32: | |
1928 | ip->insn_opcode |= address_expr->X_add_number; | |
1929 | break; | |
1930 | ||
f6688943 TS |
1931 | case BFD_RELOC_MIPS_HIGHEST: |
1932 | tmp = (address_expr->X_add_number + 0x800080008000) >> 16; | |
1933 | tmp >>= 16; | |
1934 | ip->insn_opcode |= (tmp >> 16) & 0xffff; | |
1935 | break; | |
1936 | ||
1937 | case BFD_RELOC_MIPS_HIGHER: | |
1938 | tmp = (address_expr->X_add_number + 0x80008000) >> 16; | |
1939 | ip->insn_opcode |= (tmp >> 16) & 0xffff; | |
1940 | break; | |
1941 | ||
1942 | case BFD_RELOC_HI16_S: | |
1943 | ip->insn_opcode |= ((address_expr->X_add_number + 0x8000) | |
1944 | >> 16) & 0xffff; | |
1945 | break; | |
1946 | ||
1947 | case BFD_RELOC_HI16: | |
1948 | ip->insn_opcode |= (address_expr->X_add_number >> 16) & 0xffff; | |
1949 | break; | |
1950 | ||
252b5132 RH |
1951 | case BFD_RELOC_LO16: |
1952 | ip->insn_opcode |= address_expr->X_add_number & 0xffff; | |
1953 | break; | |
1954 | ||
1955 | case BFD_RELOC_MIPS_JMP: | |
1956 | if ((address_expr->X_add_number & 3) != 0) | |
1957 | as_bad (_("jump to misaligned address (0x%lx)"), | |
1958 | (unsigned long) address_expr->X_add_number); | |
1959 | ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0x3ffffff; | |
1960 | break; | |
1961 | ||
1962 | case BFD_RELOC_MIPS16_JMP: | |
1963 | if ((address_expr->X_add_number & 3) != 0) | |
1964 | as_bad (_("jump to misaligned address (0x%lx)"), | |
1965 | (unsigned long) address_expr->X_add_number); | |
1966 | ip->insn_opcode |= | |
1967 | (((address_expr->X_add_number & 0x7c0000) << 3) | |
1968 | | ((address_expr->X_add_number & 0xf800000) >> 7) | |
1969 | | ((address_expr->X_add_number & 0x3fffc) >> 2)); | |
1970 | break; | |
1971 | ||
cb56d3d3 | 1972 | case BFD_RELOC_16_PCREL: |
233b8738 | 1973 | ip->insn_opcode |= address_expr->X_add_number & 0xffff; |
cb56d3d3 TS |
1974 | break; |
1975 | ||
252b5132 RH |
1976 | case BFD_RELOC_16_PCREL_S2: |
1977 | goto need_reloc; | |
1978 | ||
1979 | default: | |
1980 | internalError (); | |
1981 | } | |
1982 | } | |
1983 | else | |
1984 | { | |
1985 | need_reloc: | |
f6688943 | 1986 | /* Don't generate a reloc if we are writing into a variant frag. */ |
252b5132 RH |
1987 | if (place == NULL) |
1988 | { | |
f6688943 TS |
1989 | fixp[0] = fix_new_exp (frag_now, f - frag_now->fr_literal, 4, |
1990 | address_expr, | |
1991 | (*reloc_type == BFD_RELOC_16_PCREL | |
1992 | || *reloc_type == BFD_RELOC_16_PCREL_S2), | |
1993 | reloc_type[0]); | |
1994 | ||
b6ff326e | 1995 | /* These relocations can have an addend that won't fit in |
f6688943 TS |
1996 | 4 octets for 64bit assembly. */ |
1997 | if (HAVE_64BIT_GPRS && | |
1998 | (*reloc_type == BFD_RELOC_16 | |
1999 | || *reloc_type == BFD_RELOC_32 | |
2000 | || *reloc_type == BFD_RELOC_MIPS_JMP | |
2001 | || *reloc_type == BFD_RELOC_HI16_S | |
2002 | || *reloc_type == BFD_RELOC_LO16 | |
2003 | || *reloc_type == BFD_RELOC_GPREL16 | |
2004 | || *reloc_type == BFD_RELOC_MIPS_LITERAL | |
2005 | || *reloc_type == BFD_RELOC_GPREL32 | |
2006 | || *reloc_type == BFD_RELOC_64 | |
2007 | || *reloc_type == BFD_RELOC_CTOR | |
2008 | || *reloc_type == BFD_RELOC_MIPS_SUB | |
2009 | || *reloc_type == BFD_RELOC_MIPS_HIGHEST | |
2010 | || *reloc_type == BFD_RELOC_MIPS_HIGHER | |
2011 | || *reloc_type == BFD_RELOC_MIPS_SCN_DISP | |
2012 | || *reloc_type == BFD_RELOC_MIPS_REL16 | |
2013 | || *reloc_type == BFD_RELOC_MIPS_RELGOT)) | |
2014 | fixp[0]->fx_no_overflow = 1; | |
2015 | ||
252b5132 RH |
2016 | if (unmatched_hi) |
2017 | { | |
2018 | struct mips_hi_fixup *hi_fixup; | |
2019 | ||
f6688943 | 2020 | assert (*reloc_type == BFD_RELOC_HI16_S); |
252b5132 RH |
2021 | hi_fixup = ((struct mips_hi_fixup *) |
2022 | xmalloc (sizeof (struct mips_hi_fixup))); | |
f6688943 | 2023 | hi_fixup->fixp = fixp[0]; |
252b5132 RH |
2024 | hi_fixup->seg = now_seg; |
2025 | hi_fixup->next = mips_hi_fixup_list; | |
2026 | mips_hi_fixup_list = hi_fixup; | |
2027 | } | |
f6688943 TS |
2028 | |
2029 | if (reloc_type[1] != BFD_RELOC_UNUSED) | |
2030 | { | |
2031 | /* FIXME: This symbol can be one of | |
2032 | RSS_UNDEF, RSS_GP, RSS_GP0, RSS_LOC. */ | |
2033 | address_expr->X_op = O_absent; | |
2034 | address_expr->X_add_symbol = 0; | |
2035 | address_expr->X_add_number = 0; | |
2036 | ||
2037 | fixp[1] = fix_new_exp (frag_now, f - frag_now->fr_literal, | |
2038 | 4, address_expr, false, | |
2039 | reloc_type[1]); | |
2040 | ||
b6ff326e | 2041 | /* These relocations can have an addend that won't fit in |
f6688943 TS |
2042 | 4 octets for 64bit assembly. */ |
2043 | if (HAVE_64BIT_GPRS && | |
2044 | (*reloc_type == BFD_RELOC_16 | |
2045 | || *reloc_type == BFD_RELOC_32 | |
2046 | || *reloc_type == BFD_RELOC_MIPS_JMP | |
2047 | || *reloc_type == BFD_RELOC_HI16_S | |
2048 | || *reloc_type == BFD_RELOC_LO16 | |
2049 | || *reloc_type == BFD_RELOC_GPREL16 | |
2050 | || *reloc_type == BFD_RELOC_MIPS_LITERAL | |
2051 | || *reloc_type == BFD_RELOC_GPREL32 | |
2052 | || *reloc_type == BFD_RELOC_64 | |
2053 | || *reloc_type == BFD_RELOC_CTOR | |
2054 | || *reloc_type == BFD_RELOC_MIPS_SUB | |
2055 | || *reloc_type == BFD_RELOC_MIPS_HIGHEST | |
2056 | || *reloc_type == BFD_RELOC_MIPS_HIGHER | |
2057 | || *reloc_type == BFD_RELOC_MIPS_SCN_DISP | |
2058 | || *reloc_type == BFD_RELOC_MIPS_REL16 | |
2059 | || *reloc_type == BFD_RELOC_MIPS_RELGOT)) | |
2060 | fixp[1]->fx_no_overflow = 1; | |
2061 | ||
2062 | if (reloc_type[2] != BFD_RELOC_UNUSED) | |
2063 | { | |
2064 | address_expr->X_op = O_absent; | |
2065 | address_expr->X_add_symbol = 0; | |
2066 | address_expr->X_add_number = 0; | |
2067 | ||
2068 | fixp[2] = fix_new_exp (frag_now, | |
2069 | f - frag_now->fr_literal, 4, | |
2070 | address_expr, false, | |
2071 | reloc_type[2]); | |
2072 | ||
b6ff326e | 2073 | /* These relocations can have an addend that won't fit in |
f6688943 TS |
2074 | 4 octets for 64bit assembly. */ |
2075 | if (HAVE_64BIT_GPRS && | |
2076 | (*reloc_type == BFD_RELOC_16 | |
2077 | || *reloc_type == BFD_RELOC_32 | |
2078 | || *reloc_type == BFD_RELOC_MIPS_JMP | |
2079 | || *reloc_type == BFD_RELOC_HI16_S | |
2080 | || *reloc_type == BFD_RELOC_LO16 | |
2081 | || *reloc_type == BFD_RELOC_GPREL16 | |
2082 | || *reloc_type == BFD_RELOC_MIPS_LITERAL | |
2083 | || *reloc_type == BFD_RELOC_GPREL32 | |
2084 | || *reloc_type == BFD_RELOC_64 | |
2085 | || *reloc_type == BFD_RELOC_CTOR | |
2086 | || *reloc_type == BFD_RELOC_MIPS_SUB | |
2087 | || *reloc_type == BFD_RELOC_MIPS_HIGHEST | |
2088 | || *reloc_type == BFD_RELOC_MIPS_HIGHER | |
2089 | || *reloc_type == BFD_RELOC_MIPS_SCN_DISP | |
2090 | || *reloc_type == BFD_RELOC_MIPS_REL16 | |
2091 | || *reloc_type == BFD_RELOC_MIPS_RELGOT)) | |
2092 | fixp[2]->fx_no_overflow = 1; | |
2093 | } | |
2094 | } | |
252b5132 RH |
2095 | } |
2096 | } | |
2097 | } | |
2098 | ||
2099 | if (! mips_opts.mips16) | |
2100 | md_number_to_chars (f, ip->insn_opcode, 4); | |
f6688943 | 2101 | else if (*reloc_type == BFD_RELOC_MIPS16_JMP) |
252b5132 RH |
2102 | { |
2103 | md_number_to_chars (f, ip->insn_opcode >> 16, 2); | |
2104 | md_number_to_chars (f + 2, ip->insn_opcode & 0xffff, 2); | |
2105 | } | |
2106 | else | |
2107 | { | |
2108 | if (ip->use_extend) | |
2109 | { | |
2110 | md_number_to_chars (f, 0xf000 | ip->extend, 2); | |
2111 | f += 2; | |
2112 | } | |
2113 | md_number_to_chars (f, ip->insn_opcode, 2); | |
2114 | } | |
2115 | ||
2116 | /* Update the register mask information. */ | |
2117 | if (! mips_opts.mips16) | |
2118 | { | |
2119 | if (pinfo & INSN_WRITE_GPR_D) | |
2120 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD); | |
2121 | if ((pinfo & (INSN_WRITE_GPR_T | INSN_READ_GPR_T)) != 0) | |
2122 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT); | |
2123 | if (pinfo & INSN_READ_GPR_S) | |
2124 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS); | |
2125 | if (pinfo & INSN_WRITE_GPR_31) | |
2126 | mips_gprmask |= 1 << 31; | |
2127 | if (pinfo & INSN_WRITE_FPR_D) | |
2128 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FD) & OP_MASK_FD); | |
2129 | if ((pinfo & (INSN_WRITE_FPR_S | INSN_READ_FPR_S)) != 0) | |
2130 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS); | |
2131 | if ((pinfo & (INSN_WRITE_FPR_T | INSN_READ_FPR_T)) != 0) | |
2132 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT); | |
2133 | if ((pinfo & INSN_READ_FPR_R) != 0) | |
2134 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FR) & OP_MASK_FR); | |
2135 | if (pinfo & INSN_COP) | |
2136 | { | |
bdaaa2e1 KH |
2137 | /* We don't keep enough information to sort these cases out. |
2138 | The itbl support does keep this information however, although | |
2139 | we currently don't support itbl fprmats as part of the cop | |
2140 | instruction. May want to add this support in the future. */ | |
252b5132 RH |
2141 | } |
2142 | /* Never set the bit for $0, which is always zero. */ | |
beae10d5 | 2143 | mips_gprmask &= ~1 << 0; |
252b5132 RH |
2144 | } |
2145 | else | |
2146 | { | |
2147 | if (pinfo & (MIPS16_INSN_WRITE_X | MIPS16_INSN_READ_X)) | |
2148 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RX) | |
2149 | & MIPS16OP_MASK_RX); | |
2150 | if (pinfo & (MIPS16_INSN_WRITE_Y | MIPS16_INSN_READ_Y)) | |
2151 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RY) | |
2152 | & MIPS16OP_MASK_RY); | |
2153 | if (pinfo & MIPS16_INSN_WRITE_Z) | |
2154 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RZ) | |
2155 | & MIPS16OP_MASK_RZ); | |
2156 | if (pinfo & (MIPS16_INSN_WRITE_T | MIPS16_INSN_READ_T)) | |
2157 | mips_gprmask |= 1 << TREG; | |
2158 | if (pinfo & (MIPS16_INSN_WRITE_SP | MIPS16_INSN_READ_SP)) | |
2159 | mips_gprmask |= 1 << SP; | |
2160 | if (pinfo & (MIPS16_INSN_WRITE_31 | MIPS16_INSN_READ_31)) | |
2161 | mips_gprmask |= 1 << RA; | |
2162 | if (pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
2163 | mips_gprmask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode); | |
2164 | if (pinfo & MIPS16_INSN_READ_Z) | |
2165 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z) | |
2166 | & MIPS16OP_MASK_MOVE32Z); | |
2167 | if (pinfo & MIPS16_INSN_READ_GPR_X) | |
2168 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_REGR32) | |
2169 | & MIPS16OP_MASK_REGR32); | |
2170 | } | |
2171 | ||
2172 | if (place == NULL && ! mips_opts.noreorder) | |
2173 | { | |
2174 | /* Filling the branch delay slot is more complex. We try to | |
2175 | switch the branch with the previous instruction, which we can | |
2176 | do if the previous instruction does not set up a condition | |
2177 | that the branch tests and if the branch is not itself the | |
2178 | target of any branch. */ | |
2179 | if ((pinfo & INSN_UNCOND_BRANCH_DELAY) | |
2180 | || (pinfo & INSN_COND_BRANCH_DELAY)) | |
2181 | { | |
2182 | if (mips_optimize < 2 | |
2183 | /* If we have seen .set volatile or .set nomove, don't | |
2184 | optimize. */ | |
2185 | || mips_opts.nomove != 0 | |
2186 | /* If we had to emit any NOP instructions, then we | |
2187 | already know we can not swap. */ | |
2188 | || nops != 0 | |
2189 | /* If we don't even know the previous insn, we can not | |
bdaaa2e1 | 2190 | swap. */ |
252b5132 RH |
2191 | || ! prev_insn_valid |
2192 | /* If the previous insn is already in a branch delay | |
2193 | slot, then we can not swap. */ | |
2194 | || prev_insn_is_delay_slot | |
2195 | /* If the previous previous insn was in a .set | |
2196 | noreorder, we can't swap. Actually, the MIPS | |
2197 | assembler will swap in this situation. However, gcc | |
2198 | configured -with-gnu-as will generate code like | |
2199 | .set noreorder | |
2200 | lw $4,XXX | |
2201 | .set reorder | |
2202 | INSN | |
2203 | bne $4,$0,foo | |
2204 | in which we can not swap the bne and INSN. If gcc is | |
2205 | not configured -with-gnu-as, it does not output the | |
2206 | .set pseudo-ops. We don't have to check | |
2207 | prev_insn_unreordered, because prev_insn_valid will | |
2208 | be 0 in that case. We don't want to use | |
2209 | prev_prev_insn_valid, because we do want to be able | |
2210 | to swap at the start of a function. */ | |
2211 | || prev_prev_insn_unreordered | |
2212 | /* If the branch is itself the target of a branch, we | |
2213 | can not swap. We cheat on this; all we check for is | |
2214 | whether there is a label on this instruction. If | |
2215 | there are any branches to anything other than a | |
2216 | label, users must use .set noreorder. */ | |
2217 | || insn_labels != NULL | |
2218 | /* If the previous instruction is in a variant frag, we | |
2219 | can not do the swap. This does not apply to the | |
2220 | mips16, which uses variant frags for different | |
2221 | purposes. */ | |
2222 | || (! mips_opts.mips16 | |
2223 | && prev_insn_frag->fr_type == rs_machine_dependent) | |
2224 | /* If the branch reads the condition codes, we don't | |
2225 | even try to swap, because in the sequence | |
2226 | ctc1 $X,$31 | |
2227 | INSN | |
2228 | INSN | |
2229 | bc1t LABEL | |
2230 | we can not swap, and I don't feel like handling that | |
2231 | case. */ | |
2232 | || (! mips_opts.mips16 | |
9ce8a5dd | 2233 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 RH |
2234 | && (pinfo & INSN_READ_COND_CODE)) |
2235 | /* We can not swap with an instruction that requires a | |
2236 | delay slot, becase the target of the branch might | |
2237 | interfere with that instruction. */ | |
2238 | || (! mips_opts.mips16 | |
9ce8a5dd | 2239 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 | 2240 | && (prev_pinfo |
bdaaa2e1 | 2241 | /* Itbl support may require additional care here. */ |
252b5132 RH |
2242 | & (INSN_LOAD_COPROC_DELAY |
2243 | | INSN_COPROC_MOVE_DELAY | |
2244 | | INSN_WRITE_COND_CODE))) | |
2245 | || (! (hilo_interlocks | |
ec68c924 | 2246 | || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT))) |
252b5132 RH |
2247 | && (prev_pinfo |
2248 | & (INSN_READ_LO | |
2249 | | INSN_READ_HI))) | |
2250 | || (! mips_opts.mips16 | |
2251 | && ! gpr_interlocks | |
2252 | && (prev_pinfo & INSN_LOAD_MEMORY_DELAY)) | |
2253 | || (! mips_opts.mips16 | |
e7af610e | 2254 | && mips_opts.isa == ISA_MIPS1 |
bdaaa2e1 | 2255 | /* Itbl support may require additional care here. */ |
252b5132 RH |
2256 | && (prev_pinfo & INSN_COPROC_MEMORY_DELAY)) |
2257 | /* We can not swap with a branch instruction. */ | |
2258 | || (prev_pinfo | |
2259 | & (INSN_UNCOND_BRANCH_DELAY | |
2260 | | INSN_COND_BRANCH_DELAY | |
2261 | | INSN_COND_BRANCH_LIKELY)) | |
2262 | /* We do not swap with a trap instruction, since it | |
2263 | complicates trap handlers to have the trap | |
2264 | instruction be in a delay slot. */ | |
2265 | || (prev_pinfo & INSN_TRAP) | |
2266 | /* If the branch reads a register that the previous | |
2267 | instruction sets, we can not swap. */ | |
2268 | || (! mips_opts.mips16 | |
2269 | && (prev_pinfo & INSN_WRITE_GPR_T) | |
2270 | && insn_uses_reg (ip, | |
2271 | ((prev_insn.insn_opcode >> OP_SH_RT) | |
2272 | & OP_MASK_RT), | |
2273 | MIPS_GR_REG)) | |
2274 | || (! mips_opts.mips16 | |
2275 | && (prev_pinfo & INSN_WRITE_GPR_D) | |
2276 | && insn_uses_reg (ip, | |
2277 | ((prev_insn.insn_opcode >> OP_SH_RD) | |
2278 | & OP_MASK_RD), | |
2279 | MIPS_GR_REG)) | |
2280 | || (mips_opts.mips16 | |
2281 | && (((prev_pinfo & MIPS16_INSN_WRITE_X) | |
2282 | && insn_uses_reg (ip, | |
2283 | ((prev_insn.insn_opcode | |
2284 | >> MIPS16OP_SH_RX) | |
2285 | & MIPS16OP_MASK_RX), | |
2286 | MIPS16_REG)) | |
2287 | || ((prev_pinfo & MIPS16_INSN_WRITE_Y) | |
2288 | && insn_uses_reg (ip, | |
2289 | ((prev_insn.insn_opcode | |
2290 | >> MIPS16OP_SH_RY) | |
2291 | & MIPS16OP_MASK_RY), | |
2292 | MIPS16_REG)) | |
2293 | || ((prev_pinfo & MIPS16_INSN_WRITE_Z) | |
2294 | && insn_uses_reg (ip, | |
2295 | ((prev_insn.insn_opcode | |
2296 | >> MIPS16OP_SH_RZ) | |
2297 | & MIPS16OP_MASK_RZ), | |
2298 | MIPS16_REG)) | |
2299 | || ((prev_pinfo & MIPS16_INSN_WRITE_T) | |
2300 | && insn_uses_reg (ip, TREG, MIPS_GR_REG)) | |
2301 | || ((prev_pinfo & MIPS16_INSN_WRITE_31) | |
2302 | && insn_uses_reg (ip, RA, MIPS_GR_REG)) | |
2303 | || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
2304 | && insn_uses_reg (ip, | |
2305 | MIPS16OP_EXTRACT_REG32R (prev_insn. | |
2306 | insn_opcode), | |
2307 | MIPS_GR_REG)))) | |
2308 | /* If the branch writes a register that the previous | |
2309 | instruction sets, we can not swap (we know that | |
2310 | branches write only to RD or to $31). */ | |
2311 | || (! mips_opts.mips16 | |
2312 | && (prev_pinfo & INSN_WRITE_GPR_T) | |
2313 | && (((pinfo & INSN_WRITE_GPR_D) | |
2314 | && (((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT) | |
2315 | == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD))) | |
2316 | || ((pinfo & INSN_WRITE_GPR_31) | |
2317 | && (((prev_insn.insn_opcode >> OP_SH_RT) | |
2318 | & OP_MASK_RT) | |
2319 | == 31)))) | |
2320 | || (! mips_opts.mips16 | |
2321 | && (prev_pinfo & INSN_WRITE_GPR_D) | |
2322 | && (((pinfo & INSN_WRITE_GPR_D) | |
2323 | && (((prev_insn.insn_opcode >> OP_SH_RD) & OP_MASK_RD) | |
2324 | == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD))) | |
2325 | || ((pinfo & INSN_WRITE_GPR_31) | |
2326 | && (((prev_insn.insn_opcode >> OP_SH_RD) | |
2327 | & OP_MASK_RD) | |
2328 | == 31)))) | |
2329 | || (mips_opts.mips16 | |
2330 | && (pinfo & MIPS16_INSN_WRITE_31) | |
2331 | && ((prev_pinfo & MIPS16_INSN_WRITE_31) | |
2332 | || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
2333 | && (MIPS16OP_EXTRACT_REG32R (prev_insn.insn_opcode) | |
2334 | == RA)))) | |
2335 | /* If the branch writes a register that the previous | |
2336 | instruction reads, we can not swap (we know that | |
2337 | branches only write to RD or to $31). */ | |
2338 | || (! mips_opts.mips16 | |
2339 | && (pinfo & INSN_WRITE_GPR_D) | |
2340 | && insn_uses_reg (&prev_insn, | |
2341 | ((ip->insn_opcode >> OP_SH_RD) | |
2342 | & OP_MASK_RD), | |
2343 | MIPS_GR_REG)) | |
2344 | || (! mips_opts.mips16 | |
2345 | && (pinfo & INSN_WRITE_GPR_31) | |
2346 | && insn_uses_reg (&prev_insn, 31, MIPS_GR_REG)) | |
2347 | || (mips_opts.mips16 | |
2348 | && (pinfo & MIPS16_INSN_WRITE_31) | |
2349 | && insn_uses_reg (&prev_insn, RA, MIPS_GR_REG)) | |
2350 | /* If we are generating embedded PIC code, the branch | |
2351 | might be expanded into a sequence which uses $at, so | |
2352 | we can't swap with an instruction which reads it. */ | |
2353 | || (mips_pic == EMBEDDED_PIC | |
2354 | && insn_uses_reg (&prev_insn, AT, MIPS_GR_REG)) | |
2355 | /* If the previous previous instruction has a load | |
2356 | delay, and sets a register that the branch reads, we | |
2357 | can not swap. */ | |
2358 | || (! mips_opts.mips16 | |
9ce8a5dd | 2359 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
bdaaa2e1 | 2360 | /* Itbl support may require additional care here. */ |
252b5132 RH |
2361 | && ((prev_prev_insn.insn_mo->pinfo & INSN_LOAD_COPROC_DELAY) |
2362 | || (! gpr_interlocks | |
2363 | && (prev_prev_insn.insn_mo->pinfo | |
2364 | & INSN_LOAD_MEMORY_DELAY))) | |
2365 | && insn_uses_reg (ip, | |
2366 | ((prev_prev_insn.insn_opcode >> OP_SH_RT) | |
2367 | & OP_MASK_RT), | |
2368 | MIPS_GR_REG)) | |
2369 | /* If one instruction sets a condition code and the | |
2370 | other one uses a condition code, we can not swap. */ | |
2371 | || ((pinfo & INSN_READ_COND_CODE) | |
2372 | && (prev_pinfo & INSN_WRITE_COND_CODE)) | |
2373 | || ((pinfo & INSN_WRITE_COND_CODE) | |
2374 | && (prev_pinfo & INSN_READ_COND_CODE)) | |
2375 | /* If the previous instruction uses the PC, we can not | |
2376 | swap. */ | |
2377 | || (mips_opts.mips16 | |
2378 | && (prev_pinfo & MIPS16_INSN_READ_PC)) | |
2379 | /* If the previous instruction was extended, we can not | |
2380 | swap. */ | |
2381 | || (mips_opts.mips16 && prev_insn_extended) | |
2382 | /* If the previous instruction had a fixup in mips16 | |
2383 | mode, we can not swap. This normally means that the | |
2384 | previous instruction was a 4 byte branch anyhow. */ | |
f6688943 | 2385 | || (mips_opts.mips16 && prev_insn_fixp[0]) |
bdaaa2e1 KH |
2386 | /* If the previous instruction is a sync, sync.l, or |
2387 | sync.p, we can not swap. */ | |
f173e82e | 2388 | || (prev_pinfo & INSN_SYNC)) |
252b5132 RH |
2389 | { |
2390 | /* We could do even better for unconditional branches to | |
2391 | portions of this object file; we could pick up the | |
2392 | instruction at the destination, put it in the delay | |
2393 | slot, and bump the destination address. */ | |
2394 | emit_nop (); | |
2395 | /* Update the previous insn information. */ | |
2396 | prev_prev_insn = *ip; | |
2397 | prev_insn.insn_mo = &dummy_opcode; | |
2398 | } | |
2399 | else | |
2400 | { | |
2401 | /* It looks like we can actually do the swap. */ | |
2402 | if (! mips_opts.mips16) | |
2403 | { | |
2404 | char *prev_f; | |
2405 | char temp[4]; | |
2406 | ||
2407 | prev_f = prev_insn_frag->fr_literal + prev_insn_where; | |
2408 | memcpy (temp, prev_f, 4); | |
2409 | memcpy (prev_f, f, 4); | |
2410 | memcpy (f, temp, 4); | |
f6688943 TS |
2411 | if (prev_insn_fixp[0]) |
2412 | { | |
2413 | prev_insn_fixp[0]->fx_frag = frag_now; | |
2414 | prev_insn_fixp[0]->fx_where = f - frag_now->fr_literal; | |
2415 | } | |
2416 | if (prev_insn_fixp[1]) | |
2417 | { | |
2418 | prev_insn_fixp[1]->fx_frag = frag_now; | |
2419 | prev_insn_fixp[1]->fx_where = f - frag_now->fr_literal; | |
2420 | } | |
2421 | if (prev_insn_fixp[2]) | |
252b5132 | 2422 | { |
f6688943 TS |
2423 | prev_insn_fixp[2]->fx_frag = frag_now; |
2424 | prev_insn_fixp[2]->fx_where = f - frag_now->fr_literal; | |
252b5132 | 2425 | } |
f6688943 | 2426 | if (fixp[0]) |
252b5132 | 2427 | { |
f6688943 TS |
2428 | fixp[0]->fx_frag = prev_insn_frag; |
2429 | fixp[0]->fx_where = prev_insn_where; | |
2430 | } | |
2431 | if (fixp[1]) | |
2432 | { | |
2433 | fixp[1]->fx_frag = prev_insn_frag; | |
2434 | fixp[1]->fx_where = prev_insn_where; | |
2435 | } | |
2436 | if (fixp[2]) | |
2437 | { | |
2438 | fixp[2]->fx_frag = prev_insn_frag; | |
2439 | fixp[2]->fx_where = prev_insn_where; | |
252b5132 RH |
2440 | } |
2441 | } | |
2442 | else | |
2443 | { | |
2444 | char *prev_f; | |
2445 | char temp[2]; | |
2446 | ||
f6688943 TS |
2447 | assert (prev_insn_fixp[0] == NULL); |
2448 | assert (prev_insn_fixp[1] == NULL); | |
2449 | assert (prev_insn_fixp[2] == NULL); | |
252b5132 RH |
2450 | prev_f = prev_insn_frag->fr_literal + prev_insn_where; |
2451 | memcpy (temp, prev_f, 2); | |
2452 | memcpy (prev_f, f, 2); | |
f6688943 | 2453 | if (*reloc_type != BFD_RELOC_MIPS16_JMP) |
252b5132 | 2454 | { |
f6688943 | 2455 | assert (*reloc_type == BFD_RELOC_UNUSED); |
252b5132 RH |
2456 | memcpy (f, temp, 2); |
2457 | } | |
2458 | else | |
2459 | { | |
2460 | memcpy (f, f + 2, 2); | |
2461 | memcpy (f + 2, temp, 2); | |
2462 | } | |
f6688943 TS |
2463 | if (fixp[0]) |
2464 | { | |
2465 | fixp[0]->fx_frag = prev_insn_frag; | |
2466 | fixp[0]->fx_where = prev_insn_where; | |
2467 | } | |
2468 | if (fixp[1]) | |
2469 | { | |
2470 | fixp[1]->fx_frag = prev_insn_frag; | |
2471 | fixp[1]->fx_where = prev_insn_where; | |
2472 | } | |
2473 | if (fixp[2]) | |
252b5132 | 2474 | { |
f6688943 TS |
2475 | fixp[2]->fx_frag = prev_insn_frag; |
2476 | fixp[2]->fx_where = prev_insn_where; | |
252b5132 RH |
2477 | } |
2478 | } | |
2479 | ||
2480 | /* Update the previous insn information; leave prev_insn | |
2481 | unchanged. */ | |
2482 | prev_prev_insn = *ip; | |
2483 | } | |
2484 | prev_insn_is_delay_slot = 1; | |
2485 | ||
2486 | /* If that was an unconditional branch, forget the previous | |
2487 | insn information. */ | |
2488 | if (pinfo & INSN_UNCOND_BRANCH_DELAY) | |
2489 | { | |
2490 | prev_prev_insn.insn_mo = &dummy_opcode; | |
2491 | prev_insn.insn_mo = &dummy_opcode; | |
2492 | } | |
2493 | ||
f6688943 TS |
2494 | prev_insn_fixp[0] = NULL; |
2495 | prev_insn_fixp[1] = NULL; | |
2496 | prev_insn_fixp[2] = NULL; | |
2497 | prev_insn_reloc_type[0] = BFD_RELOC_UNUSED; | |
2498 | prev_insn_reloc_type[1] = BFD_RELOC_UNUSED; | |
2499 | prev_insn_reloc_type[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
2500 | prev_insn_extended = 0; |
2501 | } | |
2502 | else if (pinfo & INSN_COND_BRANCH_LIKELY) | |
2503 | { | |
2504 | /* We don't yet optimize a branch likely. What we should do | |
2505 | is look at the target, copy the instruction found there | |
2506 | into the delay slot, and increment the branch to jump to | |
2507 | the next instruction. */ | |
2508 | emit_nop (); | |
2509 | /* Update the previous insn information. */ | |
2510 | prev_prev_insn = *ip; | |
2511 | prev_insn.insn_mo = &dummy_opcode; | |
f6688943 TS |
2512 | prev_insn_fixp[0] = NULL; |
2513 | prev_insn_fixp[1] = NULL; | |
2514 | prev_insn_fixp[2] = NULL; | |
2515 | prev_insn_reloc_type[0] = BFD_RELOC_UNUSED; | |
2516 | prev_insn_reloc_type[1] = BFD_RELOC_UNUSED; | |
2517 | prev_insn_reloc_type[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
2518 | prev_insn_extended = 0; |
2519 | } | |
2520 | else | |
2521 | { | |
2522 | /* Update the previous insn information. */ | |
2523 | if (nops > 0) | |
2524 | prev_prev_insn.insn_mo = &dummy_opcode; | |
2525 | else | |
2526 | prev_prev_insn = prev_insn; | |
2527 | prev_insn = *ip; | |
2528 | ||
2529 | /* Any time we see a branch, we always fill the delay slot | |
2530 | immediately; since this insn is not a branch, we know it | |
2531 | is not in a delay slot. */ | |
2532 | prev_insn_is_delay_slot = 0; | |
2533 | ||
f6688943 TS |
2534 | prev_insn_fixp[0] = fixp[0]; |
2535 | prev_insn_fixp[1] = fixp[1]; | |
2536 | prev_insn_fixp[2] = fixp[2]; | |
2537 | prev_insn_reloc_type[0] = reloc_type[0]; | |
2538 | prev_insn_reloc_type[1] = reloc_type[1]; | |
2539 | prev_insn_reloc_type[2] = reloc_type[2]; | |
252b5132 RH |
2540 | if (mips_opts.mips16) |
2541 | prev_insn_extended = (ip->use_extend | |
f6688943 | 2542 | || *reloc_type > BFD_RELOC_UNUSED); |
252b5132 RH |
2543 | } |
2544 | ||
2545 | prev_prev_insn_unreordered = prev_insn_unreordered; | |
2546 | prev_insn_unreordered = 0; | |
2547 | prev_insn_frag = frag_now; | |
2548 | prev_insn_where = f - frag_now->fr_literal; | |
2549 | prev_insn_valid = 1; | |
2550 | } | |
2551 | else if (place == NULL) | |
2552 | { | |
2553 | /* We need to record a bit of information even when we are not | |
2554 | reordering, in order to determine the base address for mips16 | |
2555 | PC relative relocs. */ | |
2556 | prev_prev_insn = prev_insn; | |
2557 | prev_insn = *ip; | |
f6688943 TS |
2558 | prev_insn_reloc_type[0] = reloc_type[0]; |
2559 | prev_insn_reloc_type[1] = reloc_type[1]; | |
2560 | prev_insn_reloc_type[2] = reloc_type[2]; | |
252b5132 RH |
2561 | prev_prev_insn_unreordered = prev_insn_unreordered; |
2562 | prev_insn_unreordered = 1; | |
2563 | } | |
2564 | ||
2565 | /* We just output an insn, so the next one doesn't have a label. */ | |
2566 | mips_clear_insn_labels (); | |
2567 | ||
2568 | /* We must ensure that a fixup associated with an unmatched %hi | |
2569 | reloc does not become a variant frag. Otherwise, the | |
2570 | rearrangement of %hi relocs in frob_file may confuse | |
2571 | tc_gen_reloc. */ | |
2572 | if (unmatched_hi) | |
2573 | { | |
2574 | frag_wane (frag_now); | |
2575 | frag_new (0); | |
2576 | } | |
2577 | } | |
2578 | ||
2579 | /* This function forgets that there was any previous instruction or | |
2580 | label. If PRESERVE is non-zero, it remembers enough information to | |
bdaaa2e1 | 2581 | know whether nops are needed before a noreorder section. */ |
252b5132 RH |
2582 | |
2583 | static void | |
2584 | mips_no_prev_insn (preserve) | |
2585 | int preserve; | |
2586 | { | |
2587 | if (! preserve) | |
2588 | { | |
2589 | prev_insn.insn_mo = &dummy_opcode; | |
2590 | prev_prev_insn.insn_mo = &dummy_opcode; | |
2591 | prev_nop_frag = NULL; | |
2592 | prev_nop_frag_holds = 0; | |
2593 | prev_nop_frag_required = 0; | |
2594 | prev_nop_frag_since = 0; | |
2595 | } | |
2596 | prev_insn_valid = 0; | |
2597 | prev_insn_is_delay_slot = 0; | |
2598 | prev_insn_unreordered = 0; | |
2599 | prev_insn_extended = 0; | |
f6688943 TS |
2600 | prev_insn_reloc_type[0] = BFD_RELOC_UNUSED; |
2601 | prev_insn_reloc_type[1] = BFD_RELOC_UNUSED; | |
2602 | prev_insn_reloc_type[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
2603 | prev_prev_insn_unreordered = 0; |
2604 | mips_clear_insn_labels (); | |
2605 | } | |
2606 | ||
2607 | /* This function must be called whenever we turn on noreorder or emit | |
2608 | something other than instructions. It inserts any NOPS which might | |
2609 | be needed by the previous instruction, and clears the information | |
2610 | kept for the previous instructions. The INSNS parameter is true if | |
bdaaa2e1 | 2611 | instructions are to follow. */ |
252b5132 RH |
2612 | |
2613 | static void | |
2614 | mips_emit_delays (insns) | |
2615 | boolean insns; | |
2616 | { | |
2617 | if (! mips_opts.noreorder) | |
2618 | { | |
2619 | int nops; | |
2620 | ||
2621 | nops = 0; | |
2622 | if ((! mips_opts.mips16 | |
9ce8a5dd | 2623 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 RH |
2624 | && (! cop_interlocks |
2625 | && (prev_insn.insn_mo->pinfo | |
2626 | & (INSN_LOAD_COPROC_DELAY | |
2627 | | INSN_COPROC_MOVE_DELAY | |
2628 | | INSN_WRITE_COND_CODE)))) | |
2629 | || (! hilo_interlocks | |
2630 | && (prev_insn.insn_mo->pinfo | |
2631 | & (INSN_READ_LO | |
2632 | | INSN_READ_HI))) | |
2633 | || (! mips_opts.mips16 | |
2634 | && ! gpr_interlocks | |
bdaaa2e1 | 2635 | && (prev_insn.insn_mo->pinfo |
252b5132 RH |
2636 | & INSN_LOAD_MEMORY_DELAY)) |
2637 | || (! mips_opts.mips16 | |
e7af610e | 2638 | && mips_opts.isa == ISA_MIPS1 |
252b5132 RH |
2639 | && (prev_insn.insn_mo->pinfo |
2640 | & INSN_COPROC_MEMORY_DELAY))) | |
2641 | { | |
beae10d5 | 2642 | /* Itbl support may require additional care here. */ |
252b5132 RH |
2643 | ++nops; |
2644 | if ((! mips_opts.mips16 | |
9ce8a5dd | 2645 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 RH |
2646 | && (! cop_interlocks |
2647 | && prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)) | |
2648 | || (! hilo_interlocks | |
2649 | && ((prev_insn.insn_mo->pinfo & INSN_READ_HI) | |
2650 | || (prev_insn.insn_mo->pinfo & INSN_READ_LO)))) | |
2651 | ++nops; | |
2652 | ||
2653 | if (prev_insn_unreordered) | |
2654 | nops = 0; | |
2655 | } | |
2656 | else if ((! mips_opts.mips16 | |
9ce8a5dd | 2657 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 RH |
2658 | && (! cop_interlocks |
2659 | && prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)) | |
2660 | || (! hilo_interlocks | |
2661 | && ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI) | |
2662 | || (prev_prev_insn.insn_mo->pinfo & INSN_READ_LO)))) | |
2663 | { | |
beae10d5 | 2664 | /* Itbl support may require additional care here. */ |
252b5132 RH |
2665 | if (! prev_prev_insn_unreordered) |
2666 | ++nops; | |
2667 | } | |
2668 | ||
2669 | if (nops > 0) | |
2670 | { | |
2671 | struct insn_label_list *l; | |
2672 | ||
2673 | if (insns) | |
2674 | { | |
2675 | /* Record the frag which holds the nop instructions, so | |
2676 | that we can remove them if we don't need them. */ | |
2677 | frag_grow (mips_opts.mips16 ? nops * 2 : nops * 4); | |
2678 | prev_nop_frag = frag_now; | |
2679 | prev_nop_frag_holds = nops; | |
2680 | prev_nop_frag_required = 0; | |
2681 | prev_nop_frag_since = 0; | |
2682 | } | |
2683 | ||
2684 | for (; nops > 0; --nops) | |
2685 | emit_nop (); | |
2686 | ||
2687 | if (insns) | |
2688 | { | |
2689 | /* Move on to a new frag, so that it is safe to simply | |
bdaaa2e1 | 2690 | decrease the size of prev_nop_frag. */ |
252b5132 RH |
2691 | frag_wane (frag_now); |
2692 | frag_new (0); | |
2693 | } | |
2694 | ||
2695 | for (l = insn_labels; l != NULL; l = l->next) | |
2696 | { | |
98aa84af AM |
2697 | valueT val; |
2698 | ||
252b5132 | 2699 | assert (S_GET_SEGMENT (l->label) == now_seg); |
49309057 | 2700 | symbol_set_frag (l->label, frag_now); |
98aa84af | 2701 | val = (valueT) frag_now_fix (); |
252b5132 RH |
2702 | /* mips16 text labels are stored as odd. */ |
2703 | if (mips_opts.mips16) | |
98aa84af AM |
2704 | val += 1; |
2705 | S_SET_VALUE (l->label, val); | |
252b5132 RH |
2706 | } |
2707 | } | |
2708 | } | |
2709 | ||
2710 | /* Mark instruction labels in mips16 mode. */ | |
2711 | if (mips_opts.mips16 && insns) | |
2712 | mips16_mark_labels (); | |
2713 | ||
2714 | mips_no_prev_insn (insns); | |
2715 | } | |
2716 | ||
2717 | /* Build an instruction created by a macro expansion. This is passed | |
2718 | a pointer to the count of instructions created so far, an | |
2719 | expression, the name of the instruction to build, an operand format | |
2720 | string, and corresponding arguments. */ | |
2721 | ||
2722 | #ifdef USE_STDARG | |
2723 | static void | |
2724 | macro_build (char *place, | |
2725 | int *counter, | |
2726 | expressionS * ep, | |
2727 | const char *name, | |
2728 | const char *fmt, | |
2729 | ...) | |
2730 | #else | |
2731 | static void | |
2732 | macro_build (place, counter, ep, name, fmt, va_alist) | |
2733 | char *place; | |
2734 | int *counter; | |
2735 | expressionS *ep; | |
2736 | const char *name; | |
2737 | const char *fmt; | |
2738 | va_dcl | |
2739 | #endif | |
2740 | { | |
2741 | struct mips_cl_insn insn; | |
f6688943 | 2742 | bfd_reloc_code_real_type r[3]; |
252b5132 | 2743 | va_list args; |
252b5132 RH |
2744 | |
2745 | #ifdef USE_STDARG | |
2746 | va_start (args, fmt); | |
2747 | #else | |
2748 | va_start (args); | |
2749 | #endif | |
2750 | ||
2751 | /* | |
2752 | * If the macro is about to expand into a second instruction, | |
2753 | * print a warning if needed. We need to pass ip as a parameter | |
2754 | * to generate a better warning message here... | |
2755 | */ | |
2756 | if (mips_opts.warn_about_macros && place == NULL && *counter == 1) | |
2757 | as_warn (_("Macro instruction expanded into multiple instructions")); | |
2758 | ||
2759 | if (place == NULL) | |
2760 | *counter += 1; /* bump instruction counter */ | |
2761 | ||
2762 | if (mips_opts.mips16) | |
2763 | { | |
2764 | mips16_macro_build (place, counter, ep, name, fmt, args); | |
2765 | va_end (args); | |
2766 | return; | |
2767 | } | |
2768 | ||
f6688943 TS |
2769 | r[0] = BFD_RELOC_UNUSED; |
2770 | r[1] = BFD_RELOC_UNUSED; | |
2771 | r[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
2772 | insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name); |
2773 | assert (insn.insn_mo); | |
2774 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
2775 | ||
2776 | /* Search until we get a match for NAME. */ | |
2777 | while (1) | |
2778 | { | |
252b5132 RH |
2779 | if (strcmp (fmt, insn.insn_mo->args) == 0 |
2780 | && insn.insn_mo->pinfo != INSN_MACRO | |
ea1fb5dc | 2781 | && OPCODE_IS_MEMBER (insn.insn_mo, mips_opts.isa, mips_arch) |
ec68c924 | 2782 | && (mips_arch != CPU_R4650 || (insn.insn_mo->pinfo & FP_D) == 0)) |
252b5132 RH |
2783 | break; |
2784 | ||
2785 | ++insn.insn_mo; | |
2786 | assert (insn.insn_mo->name); | |
2787 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
2788 | } | |
2789 | ||
2790 | insn.insn_opcode = insn.insn_mo->match; | |
2791 | for (;;) | |
2792 | { | |
2793 | switch (*fmt++) | |
2794 | { | |
2795 | case '\0': | |
2796 | break; | |
2797 | ||
2798 | case ',': | |
2799 | case '(': | |
2800 | case ')': | |
2801 | continue; | |
2802 | ||
2803 | case 't': | |
2804 | case 'w': | |
2805 | case 'E': | |
38487616 | 2806 | insn.insn_opcode |= va_arg (args, int) << OP_SH_RT; |
252b5132 RH |
2807 | continue; |
2808 | ||
2809 | case 'c': | |
38487616 TS |
2810 | insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE; |
2811 | continue; | |
2812 | ||
252b5132 RH |
2813 | case 'T': |
2814 | case 'W': | |
38487616 | 2815 | insn.insn_opcode |= va_arg (args, int) << OP_SH_FT; |
252b5132 RH |
2816 | continue; |
2817 | ||
2818 | case 'd': | |
2819 | case 'G': | |
38487616 | 2820 | insn.insn_opcode |= va_arg (args, int) << OP_SH_RD; |
252b5132 RH |
2821 | continue; |
2822 | ||
4372b673 NC |
2823 | case 'U': |
2824 | { | |
2825 | int tmp = va_arg (args, int); | |
2826 | ||
38487616 TS |
2827 | insn.insn_opcode |= tmp << OP_SH_RT; |
2828 | insn.insn_opcode |= tmp << OP_SH_RD; | |
beae10d5 | 2829 | continue; |
4372b673 NC |
2830 | } |
2831 | ||
252b5132 RH |
2832 | case 'V': |
2833 | case 'S': | |
38487616 | 2834 | insn.insn_opcode |= va_arg (args, int) << OP_SH_FS; |
252b5132 RH |
2835 | continue; |
2836 | ||
2837 | case 'z': | |
2838 | continue; | |
2839 | ||
2840 | case '<': | |
38487616 | 2841 | insn.insn_opcode |= va_arg (args, int) << OP_SH_SHAMT; |
252b5132 RH |
2842 | continue; |
2843 | ||
2844 | case 'D': | |
38487616 | 2845 | insn.insn_opcode |= va_arg (args, int) << OP_SH_FD; |
252b5132 RH |
2846 | continue; |
2847 | ||
2848 | case 'B': | |
38487616 | 2849 | insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE20; |
252b5132 RH |
2850 | continue; |
2851 | ||
4372b673 | 2852 | case 'J': |
38487616 | 2853 | insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE19; |
4372b673 NC |
2854 | continue; |
2855 | ||
252b5132 | 2856 | case 'q': |
38487616 | 2857 | insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE2; |
252b5132 RH |
2858 | continue; |
2859 | ||
2860 | case 'b': | |
2861 | case 's': | |
2862 | case 'r': | |
2863 | case 'v': | |
38487616 | 2864 | insn.insn_opcode |= va_arg (args, int) << OP_SH_RS; |
252b5132 RH |
2865 | continue; |
2866 | ||
2867 | case 'i': | |
2868 | case 'j': | |
2869 | case 'o': | |
f6688943 TS |
2870 | *r = (bfd_reloc_code_real_type) va_arg (args, int); |
2871 | assert (*r == BFD_RELOC_MIPS_GPREL | |
2872 | || *r == BFD_RELOC_MIPS_LITERAL | |
2873 | || *r == BFD_RELOC_MIPS_HIGHER | |
2874 | || *r == BFD_RELOC_HI16_S | |
2875 | || *r == BFD_RELOC_LO16 | |
2876 | || *r == BFD_RELOC_MIPS_GOT16 | |
2877 | || *r == BFD_RELOC_MIPS_CALL16 | |
2878 | || *r == BFD_RELOC_MIPS_GOT_LO16 | |
2879 | || *r == BFD_RELOC_MIPS_CALL_LO16 | |
252b5132 | 2880 | || (ep->X_op == O_subtract |
f6688943 | 2881 | && *r == BFD_RELOC_PCREL_LO16)); |
252b5132 RH |
2882 | continue; |
2883 | ||
2884 | case 'u': | |
f6688943 | 2885 | *r = (bfd_reloc_code_real_type) va_arg (args, int); |
252b5132 RH |
2886 | assert (ep != NULL |
2887 | && (ep->X_op == O_constant | |
2888 | || (ep->X_op == O_symbol | |
f6688943 TS |
2889 | && (*r == BFD_RELOC_MIPS_HIGHEST |
2890 | || *r == BFD_RELOC_HI16_S | |
2891 | || *r == BFD_RELOC_HI16 | |
2892 | || *r == BFD_RELOC_GPREL16 | |
2893 | || *r == BFD_RELOC_MIPS_GOT_HI16 | |
2894 | || *r == BFD_RELOC_MIPS_CALL_HI16)) | |
252b5132 | 2895 | || (ep->X_op == O_subtract |
f6688943 | 2896 | && *r == BFD_RELOC_PCREL_HI16_S))); |
252b5132 RH |
2897 | continue; |
2898 | ||
2899 | case 'p': | |
2900 | assert (ep != NULL); | |
2901 | /* | |
2902 | * This allows macro() to pass an immediate expression for | |
2903 | * creating short branches without creating a symbol. | |
2904 | * Note that the expression still might come from the assembly | |
2905 | * input, in which case the value is not checked for range nor | |
2906 | * is a relocation entry generated (yuck). | |
2907 | */ | |
2908 | if (ep->X_op == O_constant) | |
2909 | { | |
2910 | insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff; | |
2911 | ep = NULL; | |
2912 | } | |
2913 | else | |
cb56d3d3 | 2914 | if (mips_pic == EMBEDDED_PIC) |
f6688943 | 2915 | *r = BFD_RELOC_16_PCREL_S2; |
cb56d3d3 | 2916 | else |
f6688943 | 2917 | *r = BFD_RELOC_16_PCREL; |
252b5132 RH |
2918 | continue; |
2919 | ||
2920 | case 'a': | |
2921 | assert (ep != NULL); | |
f6688943 | 2922 | *r = BFD_RELOC_MIPS_JMP; |
252b5132 RH |
2923 | continue; |
2924 | ||
2925 | case 'C': | |
2926 | insn.insn_opcode |= va_arg (args, unsigned long); | |
2927 | continue; | |
2928 | ||
2929 | default: | |
2930 | internalError (); | |
2931 | } | |
2932 | break; | |
2933 | } | |
2934 | va_end (args); | |
f6688943 | 2935 | assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
252b5132 RH |
2936 | |
2937 | append_insn (place, &insn, ep, r, false); | |
2938 | } | |
2939 | ||
2940 | static void | |
2941 | mips16_macro_build (place, counter, ep, name, fmt, args) | |
2942 | char *place; | |
43841e91 | 2943 | int *counter ATTRIBUTE_UNUSED; |
252b5132 RH |
2944 | expressionS *ep; |
2945 | const char *name; | |
2946 | const char *fmt; | |
2947 | va_list args; | |
2948 | { | |
2949 | struct mips_cl_insn insn; | |
f6688943 TS |
2950 | bfd_reloc_code_real_type r[3] |
2951 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 2952 | |
252b5132 RH |
2953 | insn.insn_mo = (struct mips_opcode *) hash_find (mips16_op_hash, name); |
2954 | assert (insn.insn_mo); | |
2955 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
2956 | ||
2957 | while (strcmp (fmt, insn.insn_mo->args) != 0 | |
2958 | || insn.insn_mo->pinfo == INSN_MACRO) | |
2959 | { | |
2960 | ++insn.insn_mo; | |
2961 | assert (insn.insn_mo->name); | |
2962 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
2963 | } | |
2964 | ||
2965 | insn.insn_opcode = insn.insn_mo->match; | |
2966 | insn.use_extend = false; | |
2967 | ||
2968 | for (;;) | |
2969 | { | |
2970 | int c; | |
2971 | ||
2972 | c = *fmt++; | |
2973 | switch (c) | |
2974 | { | |
2975 | case '\0': | |
2976 | break; | |
2977 | ||
2978 | case ',': | |
2979 | case '(': | |
2980 | case ')': | |
2981 | continue; | |
2982 | ||
2983 | case 'y': | |
2984 | case 'w': | |
2985 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RY; | |
2986 | continue; | |
2987 | ||
2988 | case 'x': | |
2989 | case 'v': | |
2990 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RX; | |
2991 | continue; | |
2992 | ||
2993 | case 'z': | |
2994 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RZ; | |
2995 | continue; | |
2996 | ||
2997 | case 'Z': | |
2998 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_MOVE32Z; | |
2999 | continue; | |
3000 | ||
3001 | case '0': | |
3002 | case 'S': | |
3003 | case 'P': | |
3004 | case 'R': | |
3005 | continue; | |
3006 | ||
3007 | case 'X': | |
3008 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_REGR32; | |
3009 | continue; | |
3010 | ||
3011 | case 'Y': | |
3012 | { | |
3013 | int regno; | |
3014 | ||
3015 | regno = va_arg (args, int); | |
3016 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); | |
3017 | insn.insn_opcode |= regno << MIPS16OP_SH_REG32R; | |
3018 | } | |
3019 | continue; | |
3020 | ||
3021 | case '<': | |
3022 | case '>': | |
3023 | case '4': | |
3024 | case '5': | |
3025 | case 'H': | |
3026 | case 'W': | |
3027 | case 'D': | |
3028 | case 'j': | |
3029 | case '8': | |
3030 | case 'V': | |
3031 | case 'C': | |
3032 | case 'U': | |
3033 | case 'k': | |
3034 | case 'K': | |
3035 | case 'p': | |
3036 | case 'q': | |
3037 | { | |
3038 | assert (ep != NULL); | |
3039 | ||
3040 | if (ep->X_op != O_constant) | |
f6688943 | 3041 | *r = BFD_RELOC_UNUSED + c; |
252b5132 RH |
3042 | else |
3043 | { | |
3044 | mips16_immed ((char *) NULL, 0, c, ep->X_add_number, false, | |
3045 | false, false, &insn.insn_opcode, | |
3046 | &insn.use_extend, &insn.extend); | |
3047 | ep = NULL; | |
f6688943 | 3048 | *r = BFD_RELOC_UNUSED; |
252b5132 RH |
3049 | } |
3050 | } | |
3051 | continue; | |
3052 | ||
3053 | case '6': | |
3054 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_IMM6; | |
3055 | continue; | |
3056 | } | |
3057 | ||
3058 | break; | |
3059 | } | |
3060 | ||
f6688943 | 3061 | assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
252b5132 RH |
3062 | |
3063 | append_insn (place, &insn, ep, r, false); | |
3064 | } | |
3065 | ||
3066 | /* | |
3067 | * Generate a "lui" instruction. | |
3068 | */ | |
3069 | static void | |
3070 | macro_build_lui (place, counter, ep, regnum) | |
3071 | char *place; | |
3072 | int *counter; | |
3073 | expressionS *ep; | |
3074 | int regnum; | |
3075 | { | |
3076 | expressionS high_expr; | |
3077 | struct mips_cl_insn insn; | |
f6688943 TS |
3078 | bfd_reloc_code_real_type r[3] |
3079 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 RH |
3080 | CONST char *name = "lui"; |
3081 | CONST char *fmt = "t,u"; | |
3082 | ||
3083 | assert (! mips_opts.mips16); | |
3084 | ||
3085 | if (place == NULL) | |
3086 | high_expr = *ep; | |
3087 | else | |
3088 | { | |
3089 | high_expr.X_op = O_constant; | |
3090 | high_expr.X_add_number = ep->X_add_number; | |
3091 | } | |
3092 | ||
3093 | if (high_expr.X_op == O_constant) | |
3094 | { | |
3095 | /* we can compute the instruction now without a relocation entry */ | |
e7d556df TS |
3096 | high_expr.X_add_number = ((high_expr.X_add_number + 0x8000) |
3097 | >> 16) & 0xffff; | |
f6688943 | 3098 | *r = BFD_RELOC_UNUSED; |
252b5132 | 3099 | } |
f6688943 | 3100 | else if (! HAVE_NEWABI) |
252b5132 RH |
3101 | { |
3102 | assert (ep->X_op == O_symbol); | |
3103 | /* _gp_disp is a special case, used from s_cpload. */ | |
3104 | assert (mips_pic == NO_PIC | |
3105 | || strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0); | |
f6688943 | 3106 | *r = BFD_RELOC_HI16_S; |
252b5132 RH |
3107 | } |
3108 | ||
3109 | /* | |
3110 | * If the macro is about to expand into a second instruction, | |
3111 | * print a warning if needed. We need to pass ip as a parameter | |
3112 | * to generate a better warning message here... | |
3113 | */ | |
3114 | if (mips_opts.warn_about_macros && place == NULL && *counter == 1) | |
3115 | as_warn (_("Macro instruction expanded into multiple instructions")); | |
3116 | ||
3117 | if (place == NULL) | |
3118 | *counter += 1; /* bump instruction counter */ | |
3119 | ||
3120 | insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name); | |
3121 | assert (insn.insn_mo); | |
3122 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
3123 | assert (strcmp (fmt, insn.insn_mo->args) == 0); | |
3124 | ||
3125 | insn.insn_opcode = insn.insn_mo->match | (regnum << OP_SH_RT); | |
f6688943 | 3126 | if (*r == BFD_RELOC_UNUSED) |
252b5132 RH |
3127 | { |
3128 | insn.insn_opcode |= high_expr.X_add_number; | |
3129 | append_insn (place, &insn, NULL, r, false); | |
3130 | } | |
3131 | else | |
3132 | append_insn (place, &insn, &high_expr, r, false); | |
3133 | } | |
3134 | ||
3135 | /* set_at() | |
3136 | * Generates code to set the $at register to true (one) | |
3137 | * if reg is less than the immediate expression. | |
3138 | */ | |
3139 | static void | |
3140 | set_at (counter, reg, unsignedp) | |
3141 | int *counter; | |
3142 | int reg; | |
3143 | int unsignedp; | |
3144 | { | |
3145 | if (imm_expr.X_op == O_constant | |
3146 | && imm_expr.X_add_number >= -0x8000 | |
3147 | && imm_expr.X_add_number < 0x8000) | |
3148 | macro_build ((char *) NULL, counter, &imm_expr, | |
3149 | unsignedp ? "sltiu" : "slti", | |
3150 | "t,r,j", AT, reg, (int) BFD_RELOC_LO16); | |
3151 | else | |
3152 | { | |
3153 | load_register (counter, AT, &imm_expr, 0); | |
3154 | macro_build ((char *) NULL, counter, NULL, | |
3155 | unsignedp ? "sltu" : "slt", | |
3156 | "d,v,t", AT, reg, AT); | |
3157 | } | |
3158 | } | |
3159 | ||
3160 | /* Warn if an expression is not a constant. */ | |
3161 | ||
3162 | static void | |
3163 | check_absolute_expr (ip, ex) | |
3164 | struct mips_cl_insn *ip; | |
3165 | expressionS *ex; | |
3166 | { | |
3167 | if (ex->X_op == O_big) | |
3168 | as_bad (_("unsupported large constant")); | |
3169 | else if (ex->X_op != O_constant) | |
3170 | as_bad (_("Instruction %s requires absolute expression"), ip->insn_mo->name); | |
3171 | } | |
3172 | ||
3173 | /* Count the leading zeroes by performing a binary chop. This is a | |
3174 | bulky bit of source, but performance is a LOT better for the | |
3175 | majority of values than a simple loop to count the bits: | |
3176 | for (lcnt = 0; (lcnt < 32); lcnt++) | |
3177 | if ((v) & (1 << (31 - lcnt))) | |
3178 | break; | |
3179 | However it is not code size friendly, and the gain will drop a bit | |
3180 | on certain cached systems. | |
3181 | */ | |
3182 | #define COUNT_TOP_ZEROES(v) \ | |
3183 | (((v) & ~0xffff) == 0 \ | |
3184 | ? ((v) & ~0xff) == 0 \ | |
3185 | ? ((v) & ~0xf) == 0 \ | |
3186 | ? ((v) & ~0x3) == 0 \ | |
3187 | ? ((v) & ~0x1) == 0 \ | |
3188 | ? !(v) \ | |
3189 | ? 32 \ | |
3190 | : 31 \ | |
3191 | : 30 \ | |
3192 | : ((v) & ~0x7) == 0 \ | |
3193 | ? 29 \ | |
3194 | : 28 \ | |
3195 | : ((v) & ~0x3f) == 0 \ | |
3196 | ? ((v) & ~0x1f) == 0 \ | |
3197 | ? 27 \ | |
3198 | : 26 \ | |
3199 | : ((v) & ~0x7f) == 0 \ | |
3200 | ? 25 \ | |
3201 | : 24 \ | |
3202 | : ((v) & ~0xfff) == 0 \ | |
3203 | ? ((v) & ~0x3ff) == 0 \ | |
3204 | ? ((v) & ~0x1ff) == 0 \ | |
3205 | ? 23 \ | |
3206 | : 22 \ | |
3207 | : ((v) & ~0x7ff) == 0 \ | |
3208 | ? 21 \ | |
3209 | : 20 \ | |
3210 | : ((v) & ~0x3fff) == 0 \ | |
3211 | ? ((v) & ~0x1fff) == 0 \ | |
3212 | ? 19 \ | |
3213 | : 18 \ | |
3214 | : ((v) & ~0x7fff) == 0 \ | |
3215 | ? 17 \ | |
3216 | : 16 \ | |
3217 | : ((v) & ~0xffffff) == 0 \ | |
3218 | ? ((v) & ~0xfffff) == 0 \ | |
3219 | ? ((v) & ~0x3ffff) == 0 \ | |
3220 | ? ((v) & ~0x1ffff) == 0 \ | |
3221 | ? 15 \ | |
3222 | : 14 \ | |
3223 | : ((v) & ~0x7ffff) == 0 \ | |
3224 | ? 13 \ | |
3225 | : 12 \ | |
3226 | : ((v) & ~0x3fffff) == 0 \ | |
3227 | ? ((v) & ~0x1fffff) == 0 \ | |
3228 | ? 11 \ | |
3229 | : 10 \ | |
3230 | : ((v) & ~0x7fffff) == 0 \ | |
3231 | ? 9 \ | |
3232 | : 8 \ | |
3233 | : ((v) & ~0xfffffff) == 0 \ | |
3234 | ? ((v) & ~0x3ffffff) == 0 \ | |
3235 | ? ((v) & ~0x1ffffff) == 0 \ | |
3236 | ? 7 \ | |
3237 | : 6 \ | |
3238 | : ((v) & ~0x7ffffff) == 0 \ | |
3239 | ? 5 \ | |
3240 | : 4 \ | |
3241 | : ((v) & ~0x3fffffff) == 0 \ | |
3242 | ? ((v) & ~0x1fffffff) == 0 \ | |
3243 | ? 3 \ | |
3244 | : 2 \ | |
3245 | : ((v) & ~0x7fffffff) == 0 \ | |
3246 | ? 1 \ | |
3247 | : 0) | |
3248 | ||
3249 | /* load_register() | |
3250 | * This routine generates the least number of instructions neccessary to load | |
3251 | * an absolute expression value into a register. | |
3252 | */ | |
3253 | static void | |
3254 | load_register (counter, reg, ep, dbl) | |
3255 | int *counter; | |
3256 | int reg; | |
3257 | expressionS *ep; | |
3258 | int dbl; | |
3259 | { | |
3260 | int freg; | |
3261 | expressionS hi32, lo32; | |
3262 | ||
3263 | if (ep->X_op != O_big) | |
3264 | { | |
3265 | assert (ep->X_op == O_constant); | |
3266 | if (ep->X_add_number < 0x8000 | |
3267 | && (ep->X_add_number >= 0 | |
3268 | || (ep->X_add_number >= -0x8000 | |
3269 | && (! dbl | |
3270 | || ! ep->X_unsigned | |
3271 | || sizeof (ep->X_add_number) > 4)))) | |
3272 | { | |
3273 | /* We can handle 16 bit signed values with an addiu to | |
3274 | $zero. No need to ever use daddiu here, since $zero and | |
3275 | the result are always correct in 32 bit mode. */ | |
3276 | macro_build ((char *) NULL, counter, ep, "addiu", "t,r,j", reg, 0, | |
3277 | (int) BFD_RELOC_LO16); | |
3278 | return; | |
3279 | } | |
3280 | else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000) | |
3281 | { | |
3282 | /* We can handle 16 bit unsigned values with an ori to | |
3283 | $zero. */ | |
3284 | macro_build ((char *) NULL, counter, ep, "ori", "t,r,i", reg, 0, | |
3285 | (int) BFD_RELOC_LO16); | |
3286 | return; | |
3287 | } | |
3288 | else if ((((ep->X_add_number &~ (offsetT) 0x7fffffff) == 0 | |
3289 | || ((ep->X_add_number &~ (offsetT) 0x7fffffff) | |
3290 | == ~ (offsetT) 0x7fffffff)) | |
3291 | && (! dbl | |
3292 | || ! ep->X_unsigned | |
3293 | || sizeof (ep->X_add_number) > 4 | |
3294 | || (ep->X_add_number & 0x80000000) == 0)) | |
ca4e0257 | 3295 | || ((HAVE_32BIT_GPRS || ! dbl) |
252b5132 | 3296 | && (ep->X_add_number &~ (offsetT) 0xffffffff) == 0) |
ca4e0257 | 3297 | || (HAVE_32BIT_GPRS |
252b5132 RH |
3298 | && ! dbl |
3299 | && ((ep->X_add_number &~ (offsetT) 0xffffffff) | |
3300 | == ~ (offsetT) 0xffffffff))) | |
3301 | { | |
3302 | /* 32 bit values require an lui. */ | |
3303 | macro_build ((char *) NULL, counter, ep, "lui", "t,u", reg, | |
3304 | (int) BFD_RELOC_HI16); | |
3305 | if ((ep->X_add_number & 0xffff) != 0) | |
3306 | macro_build ((char *) NULL, counter, ep, "ori", "t,r,i", reg, reg, | |
3307 | (int) BFD_RELOC_LO16); | |
3308 | return; | |
3309 | } | |
3310 | } | |
3311 | ||
3312 | /* The value is larger than 32 bits. */ | |
3313 | ||
ca4e0257 | 3314 | if (HAVE_32BIT_GPRS) |
252b5132 RH |
3315 | { |
3316 | as_bad (_("Number larger than 32 bits")); | |
3317 | macro_build ((char *) NULL, counter, ep, "addiu", "t,r,j", reg, 0, | |
3318 | (int) BFD_RELOC_LO16); | |
3319 | return; | |
3320 | } | |
3321 | ||
3322 | if (ep->X_op != O_big) | |
3323 | { | |
3324 | hi32 = *ep; | |
3325 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
3326 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
3327 | hi32.X_add_number &= 0xffffffff; | |
3328 | lo32 = *ep; | |
3329 | lo32.X_add_number &= 0xffffffff; | |
3330 | } | |
3331 | else | |
3332 | { | |
3333 | assert (ep->X_add_number > 2); | |
3334 | if (ep->X_add_number == 3) | |
3335 | generic_bignum[3] = 0; | |
3336 | else if (ep->X_add_number > 4) | |
3337 | as_bad (_("Number larger than 64 bits")); | |
3338 | lo32.X_op = O_constant; | |
3339 | lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16); | |
3340 | hi32.X_op = O_constant; | |
3341 | hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16); | |
3342 | } | |
3343 | ||
3344 | if (hi32.X_add_number == 0) | |
3345 | freg = 0; | |
3346 | else | |
3347 | { | |
3348 | int shift, bit; | |
3349 | unsigned long hi, lo; | |
3350 | ||
3351 | if (hi32.X_add_number == 0xffffffff) | |
beae10d5 KH |
3352 | { |
3353 | if ((lo32.X_add_number & 0xffff8000) == 0xffff8000) | |
3354 | { | |
3355 | macro_build ((char *) NULL, counter, &lo32, "addiu", "t,r,j", | |
252b5132 | 3356 | reg, 0, (int) BFD_RELOC_LO16); |
beae10d5 KH |
3357 | return; |
3358 | } | |
3359 | if (lo32.X_add_number & 0x80000000) | |
3360 | { | |
3361 | macro_build ((char *) NULL, counter, &lo32, "lui", "t,u", reg, | |
3362 | (int) BFD_RELOC_HI16); | |
252b5132 RH |
3363 | if (lo32.X_add_number & 0xffff) |
3364 | macro_build ((char *) NULL, counter, &lo32, "ori", "t,r,i", | |
3365 | reg, reg, (int) BFD_RELOC_LO16); | |
beae10d5 KH |
3366 | return; |
3367 | } | |
3368 | } | |
252b5132 RH |
3369 | |
3370 | /* Check for 16bit shifted constant. We know that hi32 is | |
3371 | non-zero, so start the mask on the first bit of the hi32 | |
3372 | value. */ | |
3373 | shift = 17; | |
3374 | do | |
beae10d5 KH |
3375 | { |
3376 | unsigned long himask, lomask; | |
3377 | ||
3378 | if (shift < 32) | |
3379 | { | |
3380 | himask = 0xffff >> (32 - shift); | |
3381 | lomask = (0xffff << shift) & 0xffffffff; | |
3382 | } | |
3383 | else | |
3384 | { | |
3385 | himask = 0xffff << (shift - 32); | |
3386 | lomask = 0; | |
3387 | } | |
3388 | if ((hi32.X_add_number & ~(offsetT) himask) == 0 | |
3389 | && (lo32.X_add_number & ~(offsetT) lomask) == 0) | |
3390 | { | |
3391 | expressionS tmp; | |
3392 | ||
3393 | tmp.X_op = O_constant; | |
3394 | if (shift < 32) | |
3395 | tmp.X_add_number = ((hi32.X_add_number << (32 - shift)) | |
3396 | | (lo32.X_add_number >> shift)); | |
3397 | else | |
3398 | tmp.X_add_number = hi32.X_add_number >> (shift - 32); | |
3399 | macro_build ((char *) NULL, counter, &tmp, | |
3400 | "ori", "t,r,i", reg, 0, | |
3401 | (int) BFD_RELOC_LO16); | |
3402 | macro_build ((char *) NULL, counter, NULL, | |
3403 | (shift >= 32) ? "dsll32" : "dsll", | |
3404 | "d,w,<", reg, reg, | |
3405 | (shift >= 32) ? shift - 32 : shift); | |
3406 | return; | |
3407 | } | |
3408 | shift++; | |
3409 | } | |
3410 | while (shift <= (64 - 16)); | |
252b5132 RH |
3411 | |
3412 | /* Find the bit number of the lowest one bit, and store the | |
3413 | shifted value in hi/lo. */ | |
3414 | hi = (unsigned long) (hi32.X_add_number & 0xffffffff); | |
3415 | lo = (unsigned long) (lo32.X_add_number & 0xffffffff); | |
3416 | if (lo != 0) | |
3417 | { | |
3418 | bit = 0; | |
3419 | while ((lo & 1) == 0) | |
3420 | { | |
3421 | lo >>= 1; | |
3422 | ++bit; | |
3423 | } | |
3424 | lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit); | |
3425 | hi >>= bit; | |
3426 | } | |
3427 | else | |
3428 | { | |
3429 | bit = 32; | |
3430 | while ((hi & 1) == 0) | |
3431 | { | |
3432 | hi >>= 1; | |
3433 | ++bit; | |
3434 | } | |
3435 | lo = hi; | |
3436 | hi = 0; | |
3437 | } | |
3438 | ||
3439 | /* Optimize if the shifted value is a (power of 2) - 1. */ | |
3440 | if ((hi == 0 && ((lo + 1) & lo) == 0) | |
3441 | || (lo == 0xffffffff && ((hi + 1) & hi) == 0)) | |
beae10d5 KH |
3442 | { |
3443 | shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number); | |
252b5132 | 3444 | if (shift != 0) |
beae10d5 | 3445 | { |
252b5132 RH |
3446 | expressionS tmp; |
3447 | ||
3448 | /* This instruction will set the register to be all | |
3449 | ones. */ | |
beae10d5 KH |
3450 | tmp.X_op = O_constant; |
3451 | tmp.X_add_number = (offsetT) -1; | |
3452 | macro_build ((char *) NULL, counter, &tmp, "addiu", "t,r,j", | |
252b5132 | 3453 | reg, 0, (int) BFD_RELOC_LO16); |
beae10d5 KH |
3454 | if (bit != 0) |
3455 | { | |
3456 | bit += shift; | |
3457 | macro_build ((char *) NULL, counter, NULL, | |
3458 | (bit >= 32) ? "dsll32" : "dsll", | |
3459 | "d,w,<", reg, reg, | |
3460 | (bit >= 32) ? bit - 32 : bit); | |
3461 | } | |
3462 | macro_build ((char *) NULL, counter, NULL, | |
252b5132 | 3463 | (shift >= 32) ? "dsrl32" : "dsrl", |
beae10d5 | 3464 | "d,w,<", reg, reg, |
252b5132 | 3465 | (shift >= 32) ? shift - 32 : shift); |
beae10d5 KH |
3466 | return; |
3467 | } | |
3468 | } | |
252b5132 RH |
3469 | |
3470 | /* Sign extend hi32 before calling load_register, because we can | |
3471 | generally get better code when we load a sign extended value. */ | |
3472 | if ((hi32.X_add_number & 0x80000000) != 0) | |
beae10d5 | 3473 | hi32.X_add_number |= ~(offsetT) 0xffffffff; |
252b5132 RH |
3474 | load_register (counter, reg, &hi32, 0); |
3475 | freg = reg; | |
3476 | } | |
3477 | if ((lo32.X_add_number & 0xffff0000) == 0) | |
3478 | { | |
3479 | if (freg != 0) | |
3480 | { | |
3481 | macro_build ((char *) NULL, counter, NULL, "dsll32", "d,w,<", reg, | |
3482 | freg, 0); | |
3483 | freg = reg; | |
3484 | } | |
3485 | } | |
3486 | else | |
3487 | { | |
3488 | expressionS mid16; | |
3489 | ||
3490 | if ((freg == 0) && (lo32.X_add_number == 0xffffffff)) | |
beae10d5 | 3491 | { |
252b5132 RH |
3492 | macro_build ((char *) NULL, counter, &lo32, "lui", "t,u", reg, |
3493 | (int) BFD_RELOC_HI16); | |
beae10d5 KH |
3494 | macro_build ((char *) NULL, counter, NULL, "dsrl32", "d,w,<", reg, |
3495 | reg, 0); | |
3496 | return; | |
3497 | } | |
252b5132 RH |
3498 | |
3499 | if (freg != 0) | |
3500 | { | |
3501 | macro_build ((char *) NULL, counter, NULL, "dsll", "d,w,<", reg, | |
3502 | freg, 16); | |
3503 | freg = reg; | |
3504 | } | |
3505 | mid16 = lo32; | |
3506 | mid16.X_add_number >>= 16; | |
3507 | macro_build ((char *) NULL, counter, &mid16, "ori", "t,r,i", reg, | |
3508 | freg, (int) BFD_RELOC_LO16); | |
3509 | macro_build ((char *) NULL, counter, NULL, "dsll", "d,w,<", reg, | |
3510 | reg, 16); | |
3511 | freg = reg; | |
3512 | } | |
3513 | if ((lo32.X_add_number & 0xffff) != 0) | |
3514 | macro_build ((char *) NULL, counter, &lo32, "ori", "t,r,i", reg, freg, | |
3515 | (int) BFD_RELOC_LO16); | |
3516 | } | |
3517 | ||
3518 | /* Load an address into a register. */ | |
3519 | ||
3520 | static void | |
d6bc6245 | 3521 | load_address (counter, reg, ep, dbl, used_at) |
252b5132 RH |
3522 | int *counter; |
3523 | int reg; | |
3524 | expressionS *ep; | |
d6bc6245 TS |
3525 | int dbl; |
3526 | int *used_at; | |
252b5132 RH |
3527 | { |
3528 | char *p; | |
3529 | ||
3530 | if (ep->X_op != O_constant | |
3531 | && ep->X_op != O_symbol) | |
3532 | { | |
3533 | as_bad (_("expression too complex")); | |
3534 | ep->X_op = O_constant; | |
3535 | } | |
3536 | ||
3537 | if (ep->X_op == O_constant) | |
3538 | { | |
d6bc6245 | 3539 | load_register (counter, reg, ep, dbl); |
252b5132 RH |
3540 | return; |
3541 | } | |
3542 | ||
3543 | if (mips_pic == NO_PIC) | |
3544 | { | |
3545 | /* If this is a reference to a GP relative symbol, we want | |
3546 | addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL) | |
3547 | Otherwise we want | |
3548 | lui $reg,<sym> (BFD_RELOC_HI16_S) | |
3549 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
d6bc6245 TS |
3550 | If we have an addend, we always use the latter form. |
3551 | ||
3552 | With 64bit address space and a usable $at we want | |
3553 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
3554 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
3555 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
3556 | daddiu $at,<sym> (BFD_RELOC_LO16) | |
3557 | dsll32 $reg,0 | |
3558 | dadd $reg,$reg,$at | |
3559 | ||
3560 | If $at is already in use, we use an path which is suboptimal | |
3561 | on superscalar processors. | |
3562 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
3563 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
3564 | dsll $reg,16 | |
3565 | daddiu $reg,<sym> (BFD_RELOC_HI16_S) | |
3566 | dsll $reg,16 | |
3567 | daddiu $reg,<sym> (BFD_RELOC_LO16) | |
3568 | */ | |
3569 | if (HAVE_64BIT_ADDRESSES) | |
3570 | { | |
3571 | p = NULL; | |
3572 | ||
3573 | /* We don't do GP optimization for now because RELAX_ENCODE can't | |
3574 | hold the data for such large chunks. */ | |
3575 | ||
3576 | if (*used_at == 0) | |
3577 | { | |
3578 | macro_build (p, counter, ep, "lui", "t,u", | |
3579 | reg, (int) BFD_RELOC_MIPS_HIGHEST); | |
3580 | macro_build (p, counter, ep, "lui", "t,u", | |
3581 | AT, (int) BFD_RELOC_HI16_S); | |
3582 | macro_build (p, counter, ep, "daddiu", "t,r,j", | |
3583 | reg, reg, (int) BFD_RELOC_MIPS_HIGHER); | |
3584 | macro_build (p, counter, ep, "daddiu", "t,r,j", | |
3585 | AT, AT, (int) BFD_RELOC_LO16); | |
3586 | macro_build (p, counter, NULL, "dsll32", "d,w,<", | |
3587 | reg, reg, 0); | |
3588 | macro_build (p, counter, NULL, "dadd", "d,v,t", | |
3589 | reg, reg, AT); | |
3590 | *used_at = 1; | |
3591 | } | |
3592 | else | |
3593 | { | |
3594 | macro_build (p, counter, ep, "lui", "t,u", | |
3595 | reg, (int) BFD_RELOC_MIPS_HIGHEST); | |
3596 | macro_build (p, counter, ep, "daddiu", "t,r,j", | |
3597 | reg, reg, (int) BFD_RELOC_MIPS_HIGHER); | |
3598 | macro_build (p, counter, NULL, "dsll", "d,w,<", | |
3599 | reg, reg, 16); | |
3600 | macro_build (p, counter, ep, "daddiu", "t,r,j", | |
3601 | reg, reg, (int) BFD_RELOC_HI16_S); | |
3602 | macro_build (p, counter, NULL, "dsll", "d,w,<", | |
3603 | reg, reg, 16); | |
3604 | macro_build (p, counter, ep, "daddiu", "t,r,j", | |
3605 | reg, reg, (int) BFD_RELOC_LO16); | |
3606 | } | |
3607 | } | |
252b5132 RH |
3608 | else |
3609 | { | |
d6bc6245 TS |
3610 | p = NULL; |
3611 | if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET | |
3612 | && ! nopic_need_relax (ep->X_add_symbol, 1)) | |
3613 | { | |
3614 | frag_grow (20); | |
3615 | macro_build ((char *) NULL, counter, ep, | |
3616 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", | |
3617 | "t,r,j", reg, GP, (int) BFD_RELOC_MIPS_GPREL); | |
3618 | p = frag_var (rs_machine_dependent, 8, 0, | |
3619 | RELAX_ENCODE (4, 8, 0, 4, 0, | |
3620 | mips_opts.warn_about_macros), | |
3621 | ep->X_add_symbol, (offsetT) 0, (char *) NULL); | |
3622 | } | |
3623 | macro_build_lui (p, counter, ep, reg); | |
3624 | if (p != NULL) | |
3625 | p += 4; | |
3626 | macro_build (p, counter, ep, | |
ca4e0257 | 3627 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
d6bc6245 TS |
3628 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); |
3629 | } | |
252b5132 RH |
3630 | } |
3631 | else if (mips_pic == SVR4_PIC && ! mips_big_got) | |
3632 | { | |
3633 | expressionS ex; | |
3634 | ||
3635 | /* If this is a reference to an external symbol, we want | |
3636 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3637 | Otherwise we want | |
3638 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3639 | nop | |
3640 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
3641 | If there is a constant, it must be added in after. */ | |
3642 | ex.X_add_number = ep->X_add_number; | |
3643 | ep->X_add_number = 0; | |
3644 | frag_grow (20); | |
3645 | macro_build ((char *) NULL, counter, ep, | |
ca4e0257 | 3646 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", |
252b5132 RH |
3647 | "t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT16, GP); |
3648 | macro_build ((char *) NULL, counter, (expressionS *) NULL, "nop", ""); | |
3649 | p = frag_var (rs_machine_dependent, 4, 0, | |
3650 | RELAX_ENCODE (0, 4, -8, 0, 0, mips_opts.warn_about_macros), | |
3651 | ep->X_add_symbol, (offsetT) 0, (char *) NULL); | |
3652 | macro_build (p, counter, ep, | |
ca4e0257 | 3653 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
252b5132 RH |
3654 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); |
3655 | if (ex.X_add_number != 0) | |
3656 | { | |
3657 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
3658 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
3659 | ex.X_op = O_constant; | |
3660 | macro_build ((char *) NULL, counter, &ex, | |
ca4e0257 | 3661 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
252b5132 RH |
3662 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); |
3663 | } | |
3664 | } | |
3665 | else if (mips_pic == SVR4_PIC) | |
3666 | { | |
3667 | expressionS ex; | |
3668 | int off; | |
3669 | ||
3670 | /* This is the large GOT case. If this is a reference to an | |
3671 | external symbol, we want | |
3672 | lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
3673 | addu $reg,$reg,$gp | |
3674 | lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16) | |
3675 | Otherwise, for a reference to a local symbol, we want | |
3676 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3677 | nop | |
3678 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
3679 | If there is a constant, it must be added in after. */ | |
3680 | ex.X_add_number = ep->X_add_number; | |
3681 | ep->X_add_number = 0; | |
3682 | if (reg_needs_delay (GP)) | |
3683 | off = 4; | |
3684 | else | |
3685 | off = 0; | |
3686 | frag_grow (32); | |
3687 | macro_build ((char *) NULL, counter, ep, "lui", "t,u", reg, | |
3688 | (int) BFD_RELOC_MIPS_GOT_HI16); | |
3689 | macro_build ((char *) NULL, counter, (expressionS *) NULL, | |
ca4e0257 | 3690 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
3691 | "d,v,t", reg, reg, GP); |
3692 | macro_build ((char *) NULL, counter, ep, | |
ca4e0257 | 3693 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", |
252b5132 RH |
3694 | "t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT_LO16, reg); |
3695 | p = frag_var (rs_machine_dependent, 12 + off, 0, | |
3696 | RELAX_ENCODE (12, 12 + off, off, 8 + off, 0, | |
3697 | mips_opts.warn_about_macros), | |
3698 | ep->X_add_symbol, (offsetT) 0, (char *) NULL); | |
3699 | if (off > 0) | |
3700 | { | |
3701 | /* We need a nop before loading from $gp. This special | |
3702 | check is required because the lui which starts the main | |
3703 | instruction stream does not refer to $gp, and so will not | |
3704 | insert the nop which may be required. */ | |
3705 | macro_build (p, counter, (expressionS *) NULL, "nop", ""); | |
3706 | p += 4; | |
3707 | } | |
9a41af64 | 3708 | macro_build (p, counter, ep, HAVE_32BIT_ADDRESSES ? "lw" : "ld", |
252b5132 RH |
3709 | "t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT16, GP); |
3710 | p += 4; | |
3711 | macro_build (p, counter, (expressionS *) NULL, "nop", ""); | |
3712 | p += 4; | |
9a41af64 | 3713 | macro_build (p, counter, ep, HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
252b5132 RH |
3714 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); |
3715 | if (ex.X_add_number != 0) | |
3716 | { | |
3717 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
3718 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
3719 | ex.X_op = O_constant; | |
3720 | macro_build ((char *) NULL, counter, &ex, | |
ca4e0257 | 3721 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
252b5132 RH |
3722 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); |
3723 | } | |
3724 | } | |
3725 | else if (mips_pic == EMBEDDED_PIC) | |
3726 | { | |
3727 | /* We always do | |
3728 | addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL) | |
3729 | */ | |
3730 | macro_build ((char *) NULL, counter, ep, | |
ca4e0257 | 3731 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
252b5132 RH |
3732 | "t,r,j", reg, GP, (int) BFD_RELOC_MIPS_GPREL); |
3733 | } | |
3734 | else | |
3735 | abort (); | |
3736 | } | |
3737 | ||
ea1fb5dc RS |
3738 | /* Move the contents of register SOURCE into register DEST. */ |
3739 | ||
3740 | static void | |
3741 | move_register (counter, dest, source) | |
3742 | int *counter; | |
3743 | int dest; | |
3744 | int source; | |
3745 | { | |
3746 | macro_build ((char *) NULL, counter, (expressionS *) NULL, | |
3747 | HAVE_32BIT_GPRS ? "addu" : "daddu", | |
3748 | "d,v,t", dest, source, 0); | |
3749 | } | |
3750 | ||
252b5132 RH |
3751 | /* |
3752 | * Build macros | |
3753 | * This routine implements the seemingly endless macro or synthesized | |
3754 | * instructions and addressing modes in the mips assembly language. Many | |
3755 | * of these macros are simple and are similar to each other. These could | |
3756 | * probably be handled by some kind of table or grammer aproach instead of | |
3757 | * this verbose method. Others are not simple macros but are more like | |
3758 | * optimizing code generation. | |
3759 | * One interesting optimization is when several store macros appear | |
3760 | * consecutivly that would load AT with the upper half of the same address. | |
3761 | * The ensuing load upper instructions are ommited. This implies some kind | |
3762 | * of global optimization. We currently only optimize within a single macro. | |
3763 | * For many of the load and store macros if the address is specified as a | |
3764 | * constant expression in the first 64k of memory (ie ld $2,0x4000c) we | |
3765 | * first load register 'at' with zero and use it as the base register. The | |
3766 | * mips assembler simply uses register $zero. Just one tiny optimization | |
3767 | * we're missing. | |
3768 | */ | |
3769 | static void | |
3770 | macro (ip) | |
3771 | struct mips_cl_insn *ip; | |
3772 | { | |
3773 | register int treg, sreg, dreg, breg; | |
3774 | int tempreg; | |
3775 | int mask; | |
3776 | int icnt = 0; | |
43841e91 | 3777 | int used_at = 0; |
252b5132 RH |
3778 | expressionS expr1; |
3779 | const char *s; | |
3780 | const char *s2; | |
3781 | const char *fmt; | |
3782 | int likely = 0; | |
3783 | int dbl = 0; | |
3784 | int coproc = 0; | |
3785 | int lr = 0; | |
3786 | int imm = 0; | |
3787 | offsetT maxnum; | |
3788 | int off; | |
3789 | bfd_reloc_code_real_type r; | |
3790 | char *p; | |
3791 | int hold_mips_optimize; | |
3792 | ||
3793 | assert (! mips_opts.mips16); | |
3794 | ||
3795 | treg = (ip->insn_opcode >> 16) & 0x1f; | |
3796 | dreg = (ip->insn_opcode >> 11) & 0x1f; | |
3797 | sreg = breg = (ip->insn_opcode >> 21) & 0x1f; | |
3798 | mask = ip->insn_mo->mask; | |
3799 | ||
3800 | expr1.X_op = O_constant; | |
3801 | expr1.X_op_symbol = NULL; | |
3802 | expr1.X_add_symbol = NULL; | |
3803 | expr1.X_add_number = 1; | |
3804 | ||
3805 | switch (mask) | |
3806 | { | |
3807 | case M_DABS: | |
3808 | dbl = 1; | |
3809 | case M_ABS: | |
3810 | /* bgez $a0,.+12 | |
3811 | move v0,$a0 | |
3812 | sub v0,$zero,$a0 | |
3813 | */ | |
3814 | ||
3815 | mips_emit_delays (true); | |
3816 | ++mips_opts.noreorder; | |
3817 | mips_any_noreorder = 1; | |
3818 | ||
3819 | expr1.X_add_number = 8; | |
3820 | macro_build ((char *) NULL, &icnt, &expr1, "bgez", "s,p", sreg); | |
3821 | if (dreg == sreg) | |
3822 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); | |
3823 | else | |
ea1fb5dc | 3824 | move_register (&icnt, dreg, sreg); |
252b5132 | 3825 | macro_build ((char *) NULL, &icnt, NULL, |
9a41af64 | 3826 | dbl ? "dsub" : "sub", "d,v,t", dreg, 0, sreg); |
252b5132 RH |
3827 | |
3828 | --mips_opts.noreorder; | |
3829 | return; | |
3830 | ||
3831 | case M_ADD_I: | |
3832 | s = "addi"; | |
3833 | s2 = "add"; | |
3834 | goto do_addi; | |
3835 | case M_ADDU_I: | |
3836 | s = "addiu"; | |
3837 | s2 = "addu"; | |
3838 | goto do_addi; | |
3839 | case M_DADD_I: | |
3840 | dbl = 1; | |
3841 | s = "daddi"; | |
3842 | s2 = "dadd"; | |
3843 | goto do_addi; | |
3844 | case M_DADDU_I: | |
3845 | dbl = 1; | |
3846 | s = "daddiu"; | |
3847 | s2 = "daddu"; | |
3848 | do_addi: | |
3849 | if (imm_expr.X_op == O_constant | |
3850 | && imm_expr.X_add_number >= -0x8000 | |
3851 | && imm_expr.X_add_number < 0x8000) | |
3852 | { | |
3853 | macro_build ((char *) NULL, &icnt, &imm_expr, s, "t,r,j", treg, sreg, | |
3854 | (int) BFD_RELOC_LO16); | |
3855 | return; | |
3856 | } | |
3857 | load_register (&icnt, AT, &imm_expr, dbl); | |
3858 | macro_build ((char *) NULL, &icnt, NULL, s2, "d,v,t", treg, sreg, AT); | |
3859 | break; | |
3860 | ||
3861 | case M_AND_I: | |
3862 | s = "andi"; | |
3863 | s2 = "and"; | |
3864 | goto do_bit; | |
3865 | case M_OR_I: | |
3866 | s = "ori"; | |
3867 | s2 = "or"; | |
3868 | goto do_bit; | |
3869 | case M_NOR_I: | |
3870 | s = ""; | |
3871 | s2 = "nor"; | |
3872 | goto do_bit; | |
3873 | case M_XOR_I: | |
3874 | s = "xori"; | |
3875 | s2 = "xor"; | |
3876 | do_bit: | |
3877 | if (imm_expr.X_op == O_constant | |
3878 | && imm_expr.X_add_number >= 0 | |
3879 | && imm_expr.X_add_number < 0x10000) | |
3880 | { | |
3881 | if (mask != M_NOR_I) | |
3882 | macro_build ((char *) NULL, &icnt, &imm_expr, s, "t,r,i", treg, | |
3883 | sreg, (int) BFD_RELOC_LO16); | |
3884 | else | |
3885 | { | |
3886 | macro_build ((char *) NULL, &icnt, &imm_expr, "ori", "t,r,i", | |
3887 | treg, sreg, (int) BFD_RELOC_LO16); | |
3888 | macro_build ((char *) NULL, &icnt, NULL, "nor", "d,v,t", | |
3889 | treg, treg, 0); | |
3890 | } | |
3891 | return; | |
3892 | } | |
3893 | ||
d6bc6245 | 3894 | load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS); |
252b5132 RH |
3895 | macro_build ((char *) NULL, &icnt, NULL, s2, "d,v,t", treg, sreg, AT); |
3896 | break; | |
3897 | ||
3898 | case M_BEQ_I: | |
3899 | s = "beq"; | |
3900 | goto beq_i; | |
3901 | case M_BEQL_I: | |
3902 | s = "beql"; | |
3903 | likely = 1; | |
3904 | goto beq_i; | |
3905 | case M_BNE_I: | |
3906 | s = "bne"; | |
3907 | goto beq_i; | |
3908 | case M_BNEL_I: | |
3909 | s = "bnel"; | |
3910 | likely = 1; | |
3911 | beq_i: | |
3912 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
3913 | { | |
3914 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "s,t,p", sreg, | |
3915 | 0); | |
3916 | return; | |
3917 | } | |
3918 | load_register (&icnt, AT, &imm_expr, 0); | |
3919 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "s,t,p", sreg, AT); | |
3920 | break; | |
3921 | ||
3922 | case M_BGEL: | |
3923 | likely = 1; | |
3924 | case M_BGE: | |
3925 | if (treg == 0) | |
3926 | { | |
3927 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3928 | likely ? "bgezl" : "bgez", | |
3929 | "s,p", sreg); | |
3930 | return; | |
3931 | } | |
3932 | if (sreg == 0) | |
3933 | { | |
3934 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3935 | likely ? "blezl" : "blez", | |
3936 | "s,p", treg); | |
3937 | return; | |
3938 | } | |
3939 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", AT, sreg, treg); | |
3940 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 3941 | likely ? "beql" : "beq", "s,t,p", AT, 0); |
252b5132 RH |
3942 | break; |
3943 | ||
3944 | case M_BGTL_I: | |
3945 | likely = 1; | |
3946 | case M_BGT_I: | |
3947 | /* check for > max integer */ | |
3948 | maxnum = 0x7fffffff; | |
ca4e0257 | 3949 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
3950 | { |
3951 | maxnum <<= 16; | |
3952 | maxnum |= 0xffff; | |
3953 | maxnum <<= 16; | |
3954 | maxnum |= 0xffff; | |
3955 | } | |
3956 | if (imm_expr.X_op == O_constant | |
3957 | && imm_expr.X_add_number >= maxnum | |
ca4e0257 | 3958 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
3959 | { |
3960 | do_false: | |
3961 | /* result is always false */ | |
3962 | if (! likely) | |
3963 | { | |
39c0a331 L |
3964 | if (warn_nops) |
3965 | as_warn (_("Branch %s is always false (nop)"), | |
3966 | ip->insn_mo->name); | |
252b5132 RH |
3967 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); |
3968 | } | |
3969 | else | |
3970 | { | |
39c0a331 L |
3971 | if (warn_nops) |
3972 | as_warn (_("Branch likely %s is always false"), | |
3973 | ip->insn_mo->name); | |
252b5132 RH |
3974 | macro_build ((char *) NULL, &icnt, &offset_expr, "bnel", |
3975 | "s,t,p", 0, 0); | |
3976 | } | |
3977 | return; | |
3978 | } | |
3979 | if (imm_expr.X_op != O_constant) | |
3980 | as_bad (_("Unsupported large constant")); | |
3981 | imm_expr.X_add_number++; | |
3982 | /* FALLTHROUGH */ | |
3983 | case M_BGE_I: | |
3984 | case M_BGEL_I: | |
3985 | if (mask == M_BGEL_I) | |
3986 | likely = 1; | |
3987 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
3988 | { | |
3989 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 3990 | likely ? "bgezl" : "bgez", "s,p", sreg); |
252b5132 RH |
3991 | return; |
3992 | } | |
3993 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
3994 | { | |
3995 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 3996 | likely ? "bgtzl" : "bgtz", "s,p", sreg); |
252b5132 RH |
3997 | return; |
3998 | } | |
3999 | maxnum = 0x7fffffff; | |
ca4e0257 | 4000 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
4001 | { |
4002 | maxnum <<= 16; | |
4003 | maxnum |= 0xffff; | |
4004 | maxnum <<= 16; | |
4005 | maxnum |= 0xffff; | |
4006 | } | |
4007 | maxnum = - maxnum - 1; | |
4008 | if (imm_expr.X_op == O_constant | |
4009 | && imm_expr.X_add_number <= maxnum | |
ca4e0257 | 4010 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
4011 | { |
4012 | do_true: | |
4013 | /* result is always true */ | |
4014 | as_warn (_("Branch %s is always true"), ip->insn_mo->name); | |
4015 | macro_build ((char *) NULL, &icnt, &offset_expr, "b", "p"); | |
4016 | return; | |
4017 | } | |
4018 | set_at (&icnt, sreg, 0); | |
4019 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4020 | likely ? "beql" : "beq", "s,t,p", AT, 0); |
252b5132 RH |
4021 | break; |
4022 | ||
4023 | case M_BGEUL: | |
4024 | likely = 1; | |
4025 | case M_BGEU: | |
4026 | if (treg == 0) | |
4027 | goto do_true; | |
4028 | if (sreg == 0) | |
4029 | { | |
4030 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4031 | likely ? "beql" : "beq", "s,t,p", 0, treg); |
252b5132 RH |
4032 | return; |
4033 | } | |
4034 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", AT, sreg, | |
4035 | treg); | |
4036 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4037 | likely ? "beql" : "beq", "s,t,p", AT, 0); |
252b5132 RH |
4038 | break; |
4039 | ||
4040 | case M_BGTUL_I: | |
4041 | likely = 1; | |
4042 | case M_BGTU_I: | |
4043 | if (sreg == 0 | |
ca4e0257 | 4044 | || (HAVE_32BIT_GPRS |
252b5132 RH |
4045 | && imm_expr.X_op == O_constant |
4046 | && imm_expr.X_add_number == 0xffffffff)) | |
4047 | goto do_false; | |
4048 | if (imm_expr.X_op != O_constant) | |
4049 | as_bad (_("Unsupported large constant")); | |
4050 | imm_expr.X_add_number++; | |
4051 | /* FALLTHROUGH */ | |
4052 | case M_BGEU_I: | |
4053 | case M_BGEUL_I: | |
4054 | if (mask == M_BGEUL_I) | |
4055 | likely = 1; | |
4056 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4057 | goto do_true; | |
4058 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4059 | { | |
4060 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4061 | likely ? "bnel" : "bne", "s,t,p", sreg, 0); |
252b5132 RH |
4062 | return; |
4063 | } | |
4064 | set_at (&icnt, sreg, 1); | |
4065 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4066 | likely ? "beql" : "beq", "s,t,p", AT, 0); |
252b5132 RH |
4067 | break; |
4068 | ||
4069 | case M_BGTL: | |
4070 | likely = 1; | |
4071 | case M_BGT: | |
4072 | if (treg == 0) | |
4073 | { | |
4074 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4075 | likely ? "bgtzl" : "bgtz", "s,p", sreg); |
252b5132 RH |
4076 | return; |
4077 | } | |
4078 | if (sreg == 0) | |
4079 | { | |
4080 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4081 | likely ? "bltzl" : "bltz", "s,p", treg); |
252b5132 RH |
4082 | return; |
4083 | } | |
4084 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", AT, treg, sreg); | |
4085 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4086 | likely ? "bnel" : "bne", "s,t,p", AT, 0); |
252b5132 RH |
4087 | break; |
4088 | ||
4089 | case M_BGTUL: | |
4090 | likely = 1; | |
4091 | case M_BGTU: | |
4092 | if (treg == 0) | |
4093 | { | |
4094 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4095 | likely ? "bnel" : "bne", "s,t,p", sreg, 0); |
252b5132 RH |
4096 | return; |
4097 | } | |
4098 | if (sreg == 0) | |
4099 | goto do_false; | |
4100 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", AT, treg, | |
4101 | sreg); | |
4102 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4103 | likely ? "bnel" : "bne", "s,t,p", AT, 0); |
252b5132 RH |
4104 | break; |
4105 | ||
4106 | case M_BLEL: | |
4107 | likely = 1; | |
4108 | case M_BLE: | |
4109 | if (treg == 0) | |
4110 | { | |
4111 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4112 | likely ? "blezl" : "blez", "s,p", sreg); |
252b5132 RH |
4113 | return; |
4114 | } | |
4115 | if (sreg == 0) | |
4116 | { | |
4117 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4118 | likely ? "bgezl" : "bgez", "s,p", treg); |
252b5132 RH |
4119 | return; |
4120 | } | |
4121 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", AT, treg, sreg); | |
4122 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4123 | likely ? "beql" : "beq", "s,t,p", AT, 0); |
252b5132 RH |
4124 | break; |
4125 | ||
4126 | case M_BLEL_I: | |
4127 | likely = 1; | |
4128 | case M_BLE_I: | |
4129 | maxnum = 0x7fffffff; | |
ca4e0257 | 4130 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
4131 | { |
4132 | maxnum <<= 16; | |
4133 | maxnum |= 0xffff; | |
4134 | maxnum <<= 16; | |
4135 | maxnum |= 0xffff; | |
4136 | } | |
4137 | if (imm_expr.X_op == O_constant | |
4138 | && imm_expr.X_add_number >= maxnum | |
ca4e0257 | 4139 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
4140 | goto do_true; |
4141 | if (imm_expr.X_op != O_constant) | |
4142 | as_bad (_("Unsupported large constant")); | |
4143 | imm_expr.X_add_number++; | |
4144 | /* FALLTHROUGH */ | |
4145 | case M_BLT_I: | |
4146 | case M_BLTL_I: | |
4147 | if (mask == M_BLTL_I) | |
4148 | likely = 1; | |
4149 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4150 | { | |
4151 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4152 | likely ? "bltzl" : "bltz", "s,p", sreg); |
252b5132 RH |
4153 | return; |
4154 | } | |
4155 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4156 | { | |
4157 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4158 | likely ? "blezl" : "blez", "s,p", sreg); |
252b5132 RH |
4159 | return; |
4160 | } | |
4161 | set_at (&icnt, sreg, 0); | |
4162 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4163 | likely ? "bnel" : "bne", "s,t,p", AT, 0); |
252b5132 RH |
4164 | break; |
4165 | ||
4166 | case M_BLEUL: | |
4167 | likely = 1; | |
4168 | case M_BLEU: | |
4169 | if (treg == 0) | |
4170 | { | |
4171 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4172 | likely ? "beql" : "beq", "s,t,p", sreg, 0); |
252b5132 RH |
4173 | return; |
4174 | } | |
4175 | if (sreg == 0) | |
4176 | goto do_true; | |
4177 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", AT, treg, | |
4178 | sreg); | |
4179 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4180 | likely ? "beql" : "beq", "s,t,p", AT, 0); |
252b5132 RH |
4181 | break; |
4182 | ||
4183 | case M_BLEUL_I: | |
4184 | likely = 1; | |
4185 | case M_BLEU_I: | |
4186 | if (sreg == 0 | |
ca4e0257 | 4187 | || (HAVE_32BIT_GPRS |
252b5132 RH |
4188 | && imm_expr.X_op == O_constant |
4189 | && imm_expr.X_add_number == 0xffffffff)) | |
4190 | goto do_true; | |
4191 | if (imm_expr.X_op != O_constant) | |
4192 | as_bad (_("Unsupported large constant")); | |
4193 | imm_expr.X_add_number++; | |
4194 | /* FALLTHROUGH */ | |
4195 | case M_BLTU_I: | |
4196 | case M_BLTUL_I: | |
4197 | if (mask == M_BLTUL_I) | |
4198 | likely = 1; | |
4199 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4200 | goto do_false; | |
4201 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4202 | { | |
4203 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
4204 | likely ? "beql" : "beq", | |
4205 | "s,t,p", sreg, 0); | |
4206 | return; | |
4207 | } | |
4208 | set_at (&icnt, sreg, 1); | |
4209 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4210 | likely ? "bnel" : "bne", "s,t,p", AT, 0); |
252b5132 RH |
4211 | break; |
4212 | ||
4213 | case M_BLTL: | |
4214 | likely = 1; | |
4215 | case M_BLT: | |
4216 | if (treg == 0) | |
4217 | { | |
4218 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4219 | likely ? "bltzl" : "bltz", "s,p", sreg); |
252b5132 RH |
4220 | return; |
4221 | } | |
4222 | if (sreg == 0) | |
4223 | { | |
4224 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4225 | likely ? "bgtzl" : "bgtz", "s,p", treg); |
252b5132 RH |
4226 | return; |
4227 | } | |
4228 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", AT, sreg, treg); | |
4229 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4230 | likely ? "bnel" : "bne", "s,t,p", AT, 0); |
252b5132 RH |
4231 | break; |
4232 | ||
4233 | case M_BLTUL: | |
4234 | likely = 1; | |
4235 | case M_BLTU: | |
4236 | if (treg == 0) | |
4237 | goto do_false; | |
4238 | if (sreg == 0) | |
4239 | { | |
4240 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4241 | likely ? "bnel" : "bne", "s,t,p", 0, treg); |
252b5132 RH |
4242 | return; |
4243 | } | |
4244 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", AT, sreg, | |
4245 | treg); | |
4246 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4247 | likely ? "bnel" : "bne", "s,t,p", AT, 0); |
252b5132 RH |
4248 | break; |
4249 | ||
4250 | case M_DDIV_3: | |
4251 | dbl = 1; | |
4252 | case M_DIV_3: | |
4253 | s = "mflo"; | |
4254 | goto do_div3; | |
4255 | case M_DREM_3: | |
4256 | dbl = 1; | |
4257 | case M_REM_3: | |
4258 | s = "mfhi"; | |
4259 | do_div3: | |
4260 | if (treg == 0) | |
4261 | { | |
4262 | as_warn (_("Divide by zero.")); | |
4263 | if (mips_trap) | |
4264 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", 0, 0); | |
4265 | else | |
9117d219 | 4266 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 7); |
252b5132 RH |
4267 | return; |
4268 | } | |
4269 | ||
4270 | mips_emit_delays (true); | |
4271 | ++mips_opts.noreorder; | |
4272 | mips_any_noreorder = 1; | |
4273 | if (mips_trap) | |
4274 | { | |
4275 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", treg, 0); | |
4276 | macro_build ((char *) NULL, &icnt, NULL, | |
9a41af64 | 4277 | dbl ? "ddiv" : "div", "z,s,t", sreg, treg); |
252b5132 RH |
4278 | } |
4279 | else | |
4280 | { | |
4281 | expr1.X_add_number = 8; | |
4282 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, 0); | |
4283 | macro_build ((char *) NULL, &icnt, NULL, | |
9a41af64 | 4284 | dbl ? "ddiv" : "div", "z,s,t", sreg, treg); |
9117d219 | 4285 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 7); |
252b5132 RH |
4286 | } |
4287 | expr1.X_add_number = -1; | |
4288 | macro_build ((char *) NULL, &icnt, &expr1, | |
4289 | dbl ? "daddiu" : "addiu", | |
4290 | "t,r,j", AT, 0, (int) BFD_RELOC_LO16); | |
4291 | expr1.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16); | |
4292 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, AT); | |
4293 | if (dbl) | |
4294 | { | |
4295 | expr1.X_add_number = 1; | |
4296 | macro_build ((char *) NULL, &icnt, &expr1, "daddiu", "t,r,j", AT, 0, | |
4297 | (int) BFD_RELOC_LO16); | |
4298 | macro_build ((char *) NULL, &icnt, NULL, "dsll32", "d,w,<", AT, AT, | |
4299 | 31); | |
4300 | } | |
4301 | else | |
4302 | { | |
4303 | expr1.X_add_number = 0x80000000; | |
4304 | macro_build ((char *) NULL, &icnt, &expr1, "lui", "t,u", AT, | |
4305 | (int) BFD_RELOC_HI16); | |
4306 | } | |
4307 | if (mips_trap) | |
4308 | { | |
4309 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", sreg, AT); | |
4310 | /* We want to close the noreorder block as soon as possible, so | |
4311 | that later insns are available for delay slot filling. */ | |
4312 | --mips_opts.noreorder; | |
4313 | } | |
4314 | else | |
4315 | { | |
4316 | expr1.X_add_number = 8; | |
4317 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", sreg, AT); | |
4318 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); | |
4319 | ||
4320 | /* We want to close the noreorder block as soon as possible, so | |
4321 | that later insns are available for delay slot filling. */ | |
4322 | --mips_opts.noreorder; | |
4323 | ||
9117d219 | 4324 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 6); |
252b5132 RH |
4325 | } |
4326 | macro_build ((char *) NULL, &icnt, NULL, s, "d", dreg); | |
4327 | break; | |
4328 | ||
4329 | case M_DIV_3I: | |
4330 | s = "div"; | |
4331 | s2 = "mflo"; | |
4332 | goto do_divi; | |
4333 | case M_DIVU_3I: | |
4334 | s = "divu"; | |
4335 | s2 = "mflo"; | |
4336 | goto do_divi; | |
4337 | case M_REM_3I: | |
4338 | s = "div"; | |
4339 | s2 = "mfhi"; | |
4340 | goto do_divi; | |
4341 | case M_REMU_3I: | |
4342 | s = "divu"; | |
4343 | s2 = "mfhi"; | |
4344 | goto do_divi; | |
4345 | case M_DDIV_3I: | |
4346 | dbl = 1; | |
4347 | s = "ddiv"; | |
4348 | s2 = "mflo"; | |
4349 | goto do_divi; | |
4350 | case M_DDIVU_3I: | |
4351 | dbl = 1; | |
4352 | s = "ddivu"; | |
4353 | s2 = "mflo"; | |
4354 | goto do_divi; | |
4355 | case M_DREM_3I: | |
4356 | dbl = 1; | |
4357 | s = "ddiv"; | |
4358 | s2 = "mfhi"; | |
4359 | goto do_divi; | |
4360 | case M_DREMU_3I: | |
4361 | dbl = 1; | |
4362 | s = "ddivu"; | |
4363 | s2 = "mfhi"; | |
4364 | do_divi: | |
4365 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4366 | { | |
4367 | as_warn (_("Divide by zero.")); | |
4368 | if (mips_trap) | |
4369 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", 0, 0); | |
4370 | else | |
beae10d5 | 4371 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 7); |
252b5132 RH |
4372 | return; |
4373 | } | |
4374 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4375 | { | |
4376 | if (strcmp (s2, "mflo") == 0) | |
ea1fb5dc | 4377 | move_register (&icnt, dreg, sreg); |
252b5132 | 4378 | else |
ea1fb5dc | 4379 | move_register (&icnt, dreg, 0); |
252b5132 RH |
4380 | return; |
4381 | } | |
4382 | if (imm_expr.X_op == O_constant | |
4383 | && imm_expr.X_add_number == -1 | |
4384 | && s[strlen (s) - 1] != 'u') | |
4385 | { | |
4386 | if (strcmp (s2, "mflo") == 0) | |
4387 | { | |
9a41af64 TS |
4388 | macro_build ((char *) NULL, &icnt, NULL, dbl ? "dneg" : "neg", |
4389 | "d,w", dreg, sreg); | |
252b5132 RH |
4390 | } |
4391 | else | |
ea1fb5dc | 4392 | move_register (&icnt, dreg, 0); |
252b5132 RH |
4393 | return; |
4394 | } | |
4395 | ||
4396 | load_register (&icnt, AT, &imm_expr, dbl); | |
4397 | macro_build ((char *) NULL, &icnt, NULL, s, "z,s,t", sreg, AT); | |
4398 | macro_build ((char *) NULL, &icnt, NULL, s2, "d", dreg); | |
4399 | break; | |
4400 | ||
4401 | case M_DIVU_3: | |
4402 | s = "divu"; | |
4403 | s2 = "mflo"; | |
4404 | goto do_divu3; | |
4405 | case M_REMU_3: | |
4406 | s = "divu"; | |
4407 | s2 = "mfhi"; | |
4408 | goto do_divu3; | |
4409 | case M_DDIVU_3: | |
4410 | s = "ddivu"; | |
4411 | s2 = "mflo"; | |
4412 | goto do_divu3; | |
4413 | case M_DREMU_3: | |
4414 | s = "ddivu"; | |
4415 | s2 = "mfhi"; | |
4416 | do_divu3: | |
4417 | mips_emit_delays (true); | |
4418 | ++mips_opts.noreorder; | |
4419 | mips_any_noreorder = 1; | |
4420 | if (mips_trap) | |
4421 | { | |
4422 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", treg, 0); | |
4423 | macro_build ((char *) NULL, &icnt, NULL, s, "z,s,t", sreg, treg); | |
4424 | /* We want to close the noreorder block as soon as possible, so | |
4425 | that later insns are available for delay slot filling. */ | |
4426 | --mips_opts.noreorder; | |
4427 | } | |
4428 | else | |
4429 | { | |
4430 | expr1.X_add_number = 8; | |
4431 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, 0); | |
4432 | macro_build ((char *) NULL, &icnt, NULL, s, "z,s,t", sreg, treg); | |
4433 | ||
4434 | /* We want to close the noreorder block as soon as possible, so | |
4435 | that later insns are available for delay slot filling. */ | |
4436 | --mips_opts.noreorder; | |
beae10d5 | 4437 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 7); |
252b5132 RH |
4438 | } |
4439 | macro_build ((char *) NULL, &icnt, NULL, s2, "d", dreg); | |
4440 | return; | |
4441 | ||
4442 | case M_DLA_AB: | |
4443 | dbl = 1; | |
4444 | case M_LA_AB: | |
4445 | /* Load the address of a symbol into a register. If breg is not | |
4446 | zero, we then add a base register to it. */ | |
4447 | ||
4448 | /* When generating embedded PIC code, we permit expressions of | |
4449 | the form | |
4450 | la $4,foo-bar | |
bb2d6cd7 | 4451 | where bar is an address in the current section. These are used |
252b5132 RH |
4452 | when getting the addresses of functions. We don't permit |
4453 | X_add_number to be non-zero, because if the symbol is | |
4454 | external the relaxing code needs to know that any addend is | |
4455 | purely the offset to X_op_symbol. */ | |
4456 | if (mips_pic == EMBEDDED_PIC | |
4457 | && offset_expr.X_op == O_subtract | |
49309057 | 4458 | && (symbol_constant_p (offset_expr.X_op_symbol) |
bb2d6cd7 | 4459 | ? S_GET_SEGMENT (offset_expr.X_op_symbol) == now_seg |
49309057 ILT |
4460 | : (symbol_equated_p (offset_expr.X_op_symbol) |
4461 | && (S_GET_SEGMENT | |
4462 | (symbol_get_value_expression (offset_expr.X_op_symbol) | |
4463 | ->X_add_symbol) | |
bb2d6cd7 | 4464 | == now_seg))) |
252b5132 | 4465 | && breg == 0 |
bb2d6cd7 GK |
4466 | && (offset_expr.X_add_number == 0 |
4467 | || OUTPUT_FLAVOR == bfd_target_elf_flavour)) | |
252b5132 RH |
4468 | { |
4469 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
4470 | treg, (int) BFD_RELOC_PCREL_HI16_S); | |
4471 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
ca4e0257 | 4472 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
252b5132 RH |
4473 | "t,r,j", treg, treg, (int) BFD_RELOC_PCREL_LO16); |
4474 | return; | |
4475 | } | |
4476 | ||
4477 | if (offset_expr.X_op != O_symbol | |
4478 | && offset_expr.X_op != O_constant) | |
4479 | { | |
4480 | as_bad (_("expression too complex")); | |
4481 | offset_expr.X_op = O_constant; | |
4482 | } | |
4483 | ||
4484 | if (treg == breg) | |
4485 | { | |
4486 | tempreg = AT; | |
4487 | used_at = 1; | |
4488 | } | |
4489 | else | |
4490 | { | |
4491 | tempreg = treg; | |
4492 | used_at = 0; | |
4493 | } | |
4494 | ||
4495 | if (offset_expr.X_op == O_constant) | |
4496 | load_register (&icnt, tempreg, &offset_expr, dbl); | |
4497 | else if (mips_pic == NO_PIC) | |
4498 | { | |
d6bc6245 | 4499 | /* If this is a reference to a GP relative symbol, we want |
252b5132 RH |
4500 | addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL) |
4501 | Otherwise we want | |
4502 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
4503 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
4504 | If we have a constant, we need two instructions anyhow, | |
d6bc6245 TS |
4505 | so we may as well always use the latter form. |
4506 | ||
4507 | With 64bit address space and a usable $at we want | |
4508 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
4509 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
4510 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
4511 | daddiu $at,<sym> (BFD_RELOC_LO16) | |
4512 | dsll32 $tempreg,0 | |
4513 | dadd $tempreg,$tempreg,$at | |
4514 | ||
4515 | If $at is already in use, we use an path which is suboptimal | |
4516 | on superscalar processors. | |
4517 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
4518 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
4519 | dsll $tempreg,16 | |
4520 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
4521 | dsll $tempreg,16 | |
4522 | daddiu $tempreg,<sym> (BFD_RELOC_LO16) | |
4523 | */ | |
4524 | p = NULL; | |
4525 | if (HAVE_64BIT_ADDRESSES) | |
252b5132 | 4526 | { |
d6bc6245 TS |
4527 | /* We don't do GP optimization for now because RELAX_ENCODE can't |
4528 | hold the data for such large chunks. */ | |
4529 | ||
4530 | if (used_at == 0) | |
4531 | { | |
4532 | macro_build (p, &icnt, &offset_expr, "lui", "t,u", | |
4533 | tempreg, (int) BFD_RELOC_MIPS_HIGHEST); | |
4534 | macro_build (p, &icnt, &offset_expr, "lui", "t,u", | |
4535 | AT, (int) BFD_RELOC_HI16_S); | |
4536 | macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j", | |
4537 | tempreg, tempreg, (int) BFD_RELOC_MIPS_HIGHER); | |
4538 | macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j", | |
4539 | AT, AT, (int) BFD_RELOC_LO16); | |
4540 | macro_build (p, &icnt, NULL, "dsll32", "d,w,<", | |
4541 | tempreg, tempreg, 0); | |
4542 | macro_build (p, &icnt, NULL, "dadd", "d,v,t", | |
4543 | tempreg, tempreg, AT); | |
4544 | used_at = 1; | |
4545 | } | |
4546 | else | |
4547 | { | |
4548 | macro_build (p, &icnt, &offset_expr, "lui", "t,u", | |
4549 | tempreg, (int) BFD_RELOC_MIPS_HIGHEST); | |
4550 | macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j", | |
4551 | tempreg, tempreg, (int) BFD_RELOC_MIPS_HIGHER); | |
4552 | macro_build (p, &icnt, NULL, "dsll", "d,w,<", | |
4553 | tempreg, tempreg, 16); | |
4554 | macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j", | |
4555 | tempreg, tempreg, (int) BFD_RELOC_HI16_S); | |
4556 | macro_build (p, &icnt, NULL, "dsll", "d,w,<", | |
4557 | tempreg, tempreg, 16); | |
4558 | macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j", | |
4559 | tempreg, tempreg, (int) BFD_RELOC_LO16); | |
4560 | } | |
4561 | } | |
4562 | else | |
4563 | { | |
4564 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET | |
4565 | && ! nopic_need_relax (offset_expr.X_add_symbol, 1)) | |
4566 | { | |
4567 | frag_grow (20); | |
4568 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
4569 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", | |
4570 | "t,r,j", tempreg, GP, (int) BFD_RELOC_MIPS_GPREL); | |
4571 | p = frag_var (rs_machine_dependent, 8, 0, | |
4572 | RELAX_ENCODE (4, 8, 0, 4, 0, | |
4573 | mips_opts.warn_about_macros), | |
4574 | offset_expr.X_add_symbol, (offsetT) 0, | |
4575 | (char *) NULL); | |
4576 | } | |
4577 | macro_build_lui (p, &icnt, &offset_expr, tempreg); | |
4578 | if (p != NULL) | |
4579 | p += 4; | |
4580 | macro_build (p, &icnt, &offset_expr, | |
4581 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", | |
4582 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); | |
4583 | } | |
252b5132 RH |
4584 | } |
4585 | else if (mips_pic == SVR4_PIC && ! mips_big_got) | |
4586 | { | |
9117d219 NC |
4587 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
4588 | ||
252b5132 RH |
4589 | /* If this is a reference to an external symbol, and there |
4590 | is no constant, we want | |
4591 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
9117d219 NC |
4592 | or if tempreg is PIC_CALL_REG |
4593 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) | |
252b5132 RH |
4594 | For a local symbol, we want |
4595 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4596 | nop | |
4597 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
4598 | ||
4599 | If we have a small constant, and this is a reference to | |
4600 | an external symbol, we want | |
4601 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4602 | nop | |
4603 | addiu $tempreg,$tempreg,<constant> | |
4604 | For a local symbol, we want the same instruction | |
4605 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
4606 | addiu instruction. | |
4607 | ||
4608 | If we have a large constant, and this is a reference to | |
4609 | an external symbol, we want | |
4610 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4611 | lui $at,<hiconstant> | |
4612 | addiu $at,$at,<loconstant> | |
4613 | addu $tempreg,$tempreg,$at | |
4614 | For a local symbol, we want the same instruction | |
4615 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
4616 | addiu instruction. */ | |
4617 | expr1.X_add_number = offset_expr.X_add_number; | |
4618 | offset_expr.X_add_number = 0; | |
4619 | frag_grow (32); | |
9117d219 NC |
4620 | if (expr1.X_add_number == 0 && tempreg == PIC_CALL_REG) |
4621 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16; | |
252b5132 RH |
4622 | macro_build ((char *) NULL, &icnt, &offset_expr, |
4623 | dbl ? "ld" : "lw", | |
9117d219 | 4624 | "t,o(b)", tempreg, lw_reloc_type, GP); |
252b5132 RH |
4625 | if (expr1.X_add_number == 0) |
4626 | { | |
4627 | int off; | |
4628 | ||
4629 | if (breg == 0) | |
4630 | off = 0; | |
4631 | else | |
4632 | { | |
4633 | /* We're going to put in an addu instruction using | |
4634 | tempreg, so we may as well insert the nop right | |
4635 | now. */ | |
4636 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4637 | "nop", ""); | |
4638 | off = 4; | |
4639 | } | |
4640 | p = frag_var (rs_machine_dependent, 8 - off, 0, | |
4641 | RELAX_ENCODE (0, 8 - off, -4 - off, 4 - off, 0, | |
4642 | (breg == 0 | |
4643 | ? mips_opts.warn_about_macros | |
4644 | : 0)), | |
4645 | offset_expr.X_add_symbol, (offsetT) 0, | |
4646 | (char *) NULL); | |
4647 | if (breg == 0) | |
4648 | { | |
4649 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4650 | p += 4; | |
4651 | } | |
4652 | macro_build (p, &icnt, &expr1, | |
ca4e0257 | 4653 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
252b5132 RH |
4654 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
4655 | /* FIXME: If breg == 0, and the next instruction uses | |
4656 | $tempreg, then if this variant case is used an extra | |
4657 | nop will be generated. */ | |
4658 | } | |
4659 | else if (expr1.X_add_number >= -0x8000 | |
4660 | && expr1.X_add_number < 0x8000) | |
4661 | { | |
4662 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4663 | "nop", ""); | |
4664 | macro_build ((char *) NULL, &icnt, &expr1, | |
ca4e0257 | 4665 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
252b5132 RH |
4666 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
4667 | (void) frag_var (rs_machine_dependent, 0, 0, | |
4668 | RELAX_ENCODE (0, 0, -12, -4, 0, 0), | |
4669 | offset_expr.X_add_symbol, (offsetT) 0, | |
4670 | (char *) NULL); | |
4671 | } | |
4672 | else | |
4673 | { | |
4674 | int off1; | |
4675 | ||
4676 | /* If we are going to add in a base register, and the | |
4677 | target register and the base register are the same, | |
4678 | then we are using AT as a temporary register. Since | |
4679 | we want to load the constant into AT, we add our | |
4680 | current AT (from the global offset table) and the | |
4681 | register into the register now, and pretend we were | |
4682 | not using a base register. */ | |
4683 | if (breg != treg) | |
4684 | off1 = 0; | |
4685 | else | |
4686 | { | |
4687 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4688 | "nop", ""); | |
4689 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 4690 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
4691 | "d,v,t", treg, AT, breg); |
4692 | breg = 0; | |
4693 | tempreg = treg; | |
4694 | off1 = -8; | |
4695 | } | |
4696 | ||
4697 | /* Set mips_optimize around the lui instruction to avoid | |
4698 | inserting an unnecessary nop after the lw. */ | |
4699 | hold_mips_optimize = mips_optimize; | |
4700 | mips_optimize = 2; | |
4701 | macro_build_lui ((char *) NULL, &icnt, &expr1, AT); | |
4702 | mips_optimize = hold_mips_optimize; | |
4703 | ||
4704 | macro_build ((char *) NULL, &icnt, &expr1, | |
ca4e0257 | 4705 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
252b5132 RH |
4706 | "t,r,j", AT, AT, (int) BFD_RELOC_LO16); |
4707 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 4708 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
4709 | "d,v,t", tempreg, tempreg, AT); |
4710 | (void) frag_var (rs_machine_dependent, 0, 0, | |
4711 | RELAX_ENCODE (0, 0, -16 + off1, -8, 0, 0), | |
4712 | offset_expr.X_add_symbol, (offsetT) 0, | |
4713 | (char *) NULL); | |
4714 | used_at = 1; | |
4715 | } | |
4716 | } | |
4717 | else if (mips_pic == SVR4_PIC) | |
4718 | { | |
4719 | int gpdel; | |
9117d219 NC |
4720 | int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; |
4721 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; | |
252b5132 RH |
4722 | |
4723 | /* This is the large GOT case. If this is a reference to an | |
4724 | external symbol, and there is no constant, we want | |
4725 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
4726 | addu $tempreg,$tempreg,$gp | |
4727 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
9117d219 NC |
4728 | or if tempreg is PIC_CALL_REG |
4729 | lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) | |
4730 | addu $tempreg,$tempreg,$gp | |
4731 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) | |
252b5132 RH |
4732 | For a local symbol, we want |
4733 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4734 | nop | |
4735 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
4736 | ||
4737 | If we have a small constant, and this is a reference to | |
4738 | an external symbol, we want | |
4739 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
4740 | addu $tempreg,$tempreg,$gp | |
4741 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
4742 | nop | |
4743 | addiu $tempreg,$tempreg,<constant> | |
4744 | For a local symbol, we want | |
4745 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4746 | nop | |
4747 | addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16) | |
4748 | ||
4749 | If we have a large constant, and this is a reference to | |
4750 | an external symbol, we want | |
4751 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
4752 | addu $tempreg,$tempreg,$gp | |
4753 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
4754 | lui $at,<hiconstant> | |
4755 | addiu $at,$at,<loconstant> | |
4756 | addu $tempreg,$tempreg,$at | |
4757 | For a local symbol, we want | |
4758 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4759 | lui $at,<hiconstant> | |
4760 | addiu $at,$at,<loconstant> (BFD_RELOC_LO16) | |
4761 | addu $tempreg,$tempreg,$at | |
4762 | */ | |
4763 | expr1.X_add_number = offset_expr.X_add_number; | |
4764 | offset_expr.X_add_number = 0; | |
4765 | frag_grow (52); | |
4766 | if (reg_needs_delay (GP)) | |
4767 | gpdel = 4; | |
4768 | else | |
4769 | gpdel = 0; | |
9117d219 NC |
4770 | if (expr1.X_add_number == 0 && tempreg == PIC_CALL_REG) |
4771 | { | |
4772 | lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; | |
4773 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; | |
4774 | } | |
252b5132 | 4775 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", |
9117d219 | 4776 | tempreg, lui_reloc_type); |
252b5132 | 4777 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
ca4e0257 | 4778 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
4779 | "d,v,t", tempreg, tempreg, GP); |
4780 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
4781 | dbl ? "ld" : "lw", | |
9117d219 | 4782 | "t,o(b)", tempreg, lw_reloc_type, tempreg); |
252b5132 RH |
4783 | if (expr1.X_add_number == 0) |
4784 | { | |
4785 | int off; | |
4786 | ||
4787 | if (breg == 0) | |
4788 | off = 0; | |
4789 | else | |
4790 | { | |
4791 | /* We're going to put in an addu instruction using | |
4792 | tempreg, so we may as well insert the nop right | |
4793 | now. */ | |
4794 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4795 | "nop", ""); | |
4796 | off = 4; | |
4797 | } | |
4798 | ||
4799 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, | |
4800 | RELAX_ENCODE (12 + off, 12 + gpdel, gpdel, | |
4801 | 8 + gpdel, 0, | |
4802 | (breg == 0 | |
4803 | ? mips_opts.warn_about_macros | |
4804 | : 0)), | |
4805 | offset_expr.X_add_symbol, (offsetT) 0, | |
4806 | (char *) NULL); | |
4807 | } | |
4808 | else if (expr1.X_add_number >= -0x8000 | |
4809 | && expr1.X_add_number < 0x8000) | |
4810 | { | |
4811 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4812 | "nop", ""); | |
4813 | macro_build ((char *) NULL, &icnt, &expr1, | |
ca4e0257 | 4814 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
252b5132 RH |
4815 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
4816 | ||
4817 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, | |
4818 | RELAX_ENCODE (20, 12 + gpdel, gpdel, 8 + gpdel, 0, | |
4819 | (breg == 0 | |
4820 | ? mips_opts.warn_about_macros | |
4821 | : 0)), | |
4822 | offset_expr.X_add_symbol, (offsetT) 0, | |
4823 | (char *) NULL); | |
4824 | } | |
4825 | else | |
4826 | { | |
4827 | int adj, dreg; | |
4828 | ||
4829 | /* If we are going to add in a base register, and the | |
4830 | target register and the base register are the same, | |
4831 | then we are using AT as a temporary register. Since | |
4832 | we want to load the constant into AT, we add our | |
4833 | current AT (from the global offset table) and the | |
4834 | register into the register now, and pretend we were | |
4835 | not using a base register. */ | |
4836 | if (breg != treg) | |
4837 | { | |
4838 | adj = 0; | |
4839 | dreg = tempreg; | |
4840 | } | |
4841 | else | |
4842 | { | |
4843 | assert (tempreg == AT); | |
4844 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4845 | "nop", ""); | |
4846 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 4847 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
4848 | "d,v,t", treg, AT, breg); |
4849 | dreg = treg; | |
4850 | adj = 8; | |
4851 | } | |
4852 | ||
4853 | /* Set mips_optimize around the lui instruction to avoid | |
4854 | inserting an unnecessary nop after the lw. */ | |
4855 | hold_mips_optimize = mips_optimize; | |
4856 | mips_optimize = 2; | |
4857 | macro_build_lui ((char *) NULL, &icnt, &expr1, AT); | |
4858 | mips_optimize = hold_mips_optimize; | |
4859 | ||
4860 | macro_build ((char *) NULL, &icnt, &expr1, | |
ca4e0257 | 4861 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
252b5132 RH |
4862 | "t,r,j", AT, AT, (int) BFD_RELOC_LO16); |
4863 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 4864 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
4865 | "d,v,t", dreg, dreg, AT); |
4866 | ||
4867 | p = frag_var (rs_machine_dependent, 16 + gpdel + adj, 0, | |
4868 | RELAX_ENCODE (24 + adj, 16 + gpdel + adj, gpdel, | |
4869 | 8 + gpdel, 0, | |
4870 | (breg == 0 | |
4871 | ? mips_opts.warn_about_macros | |
4872 | : 0)), | |
4873 | offset_expr.X_add_symbol, (offsetT) 0, | |
4874 | (char *) NULL); | |
4875 | ||
4876 | used_at = 1; | |
4877 | } | |
4878 | ||
4879 | if (gpdel > 0) | |
4880 | { | |
4881 | /* This is needed because this instruction uses $gp, but | |
4882 | the first instruction on the main stream does not. */ | |
4883 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4884 | p += 4; | |
4885 | } | |
4886 | macro_build (p, &icnt, &offset_expr, | |
4887 | dbl ? "ld" : "lw", | |
4888 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, GP); | |
4889 | p += 4; | |
4890 | if (expr1.X_add_number >= -0x8000 | |
4891 | && expr1.X_add_number < 0x8000) | |
4892 | { | |
4893 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4894 | p += 4; | |
4895 | macro_build (p, &icnt, &expr1, | |
ca4e0257 | 4896 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
252b5132 RH |
4897 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
4898 | /* FIXME: If add_number is 0, and there was no base | |
4899 | register, the external symbol case ended with a load, | |
4900 | so if the symbol turns out to not be external, and | |
4901 | the next instruction uses tempreg, an unnecessary nop | |
4902 | will be inserted. */ | |
4903 | } | |
4904 | else | |
4905 | { | |
4906 | if (breg == treg) | |
4907 | { | |
4908 | /* We must add in the base register now, as in the | |
4909 | external symbol case. */ | |
4910 | assert (tempreg == AT); | |
4911 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4912 | p += 4; | |
4913 | macro_build (p, &icnt, (expressionS *) NULL, | |
ca4e0257 | 4914 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
4915 | "d,v,t", treg, AT, breg); |
4916 | p += 4; | |
4917 | tempreg = treg; | |
4918 | /* We set breg to 0 because we have arranged to add | |
4919 | it in in both cases. */ | |
4920 | breg = 0; | |
4921 | } | |
4922 | ||
4923 | macro_build_lui (p, &icnt, &expr1, AT); | |
4924 | p += 4; | |
4925 | macro_build (p, &icnt, &expr1, | |
ca4e0257 | 4926 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
252b5132 RH |
4927 | "t,r,j", AT, AT, (int) BFD_RELOC_LO16); |
4928 | p += 4; | |
4929 | macro_build (p, &icnt, (expressionS *) NULL, | |
ca4e0257 | 4930 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
4931 | "d,v,t", tempreg, tempreg, AT); |
4932 | p += 4; | |
4933 | } | |
4934 | } | |
4935 | else if (mips_pic == EMBEDDED_PIC) | |
4936 | { | |
4937 | /* We use | |
4938 | addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL) | |
4939 | */ | |
4940 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
ca4e0257 | 4941 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
252b5132 RH |
4942 | "t,r,j", tempreg, GP, (int) BFD_RELOC_MIPS_GPREL); |
4943 | } | |
4944 | else | |
4945 | abort (); | |
4946 | ||
4947 | if (breg != 0) | |
4948 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 4949 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
4950 | "d,v,t", treg, tempreg, breg); |
4951 | ||
4952 | if (! used_at) | |
4953 | return; | |
4954 | ||
4955 | break; | |
4956 | ||
4957 | case M_J_A: | |
4958 | /* The j instruction may not be used in PIC code, since it | |
4959 | requires an absolute address. We convert it to a b | |
4960 | instruction. */ | |
4961 | if (mips_pic == NO_PIC) | |
4962 | macro_build ((char *) NULL, &icnt, &offset_expr, "j", "a"); | |
4963 | else | |
4964 | macro_build ((char *) NULL, &icnt, &offset_expr, "b", "p"); | |
4965 | return; | |
4966 | ||
4967 | /* The jal instructions must be handled as macros because when | |
4968 | generating PIC code they expand to multi-instruction | |
4969 | sequences. Normally they are simple instructions. */ | |
4970 | case M_JAL_1: | |
4971 | dreg = RA; | |
4972 | /* Fall through. */ | |
4973 | case M_JAL_2: | |
4974 | if (mips_pic == NO_PIC | |
4975 | || mips_pic == EMBEDDED_PIC) | |
4976 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "jalr", | |
4977 | "d,s", dreg, sreg); | |
4978 | else if (mips_pic == SVR4_PIC) | |
4979 | { | |
4980 | if (sreg != PIC_CALL_REG) | |
4981 | as_warn (_("MIPS PIC call to register other than $25")); | |
bdaaa2e1 | 4982 | |
252b5132 RH |
4983 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "jalr", |
4984 | "d,s", dreg, sreg); | |
6478892d | 4985 | if (! HAVE_NEWABI) |
252b5132 | 4986 | { |
6478892d TS |
4987 | if (mips_cprestore_offset < 0) |
4988 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
4989 | else | |
4990 | { | |
4991 | expr1.X_add_number = mips_cprestore_offset; | |
4992 | macro_build ((char *) NULL, &icnt, &expr1, | |
4993 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", "t,o(b)", | |
4994 | GP, (int) BFD_RELOC_LO16, mips_frame_reg); | |
4995 | } | |
252b5132 RH |
4996 | } |
4997 | } | |
4998 | else | |
4999 | abort (); | |
5000 | ||
5001 | return; | |
5002 | ||
5003 | case M_JAL_A: | |
5004 | if (mips_pic == NO_PIC) | |
5005 | macro_build ((char *) NULL, &icnt, &offset_expr, "jal", "a"); | |
5006 | else if (mips_pic == SVR4_PIC) | |
5007 | { | |
5008 | /* If this is a reference to an external symbol, and we are | |
5009 | using a small GOT, we want | |
5010 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16) | |
5011 | nop | |
5012 | jalr $25 | |
5013 | nop | |
5014 | lw $gp,cprestore($sp) | |
5015 | The cprestore value is set using the .cprestore | |
5016 | pseudo-op. If we are using a big GOT, we want | |
5017 | lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16) | |
5018 | addu $25,$25,$gp | |
5019 | lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16) | |
5020 | nop | |
5021 | jalr $25 | |
5022 | nop | |
5023 | lw $gp,cprestore($sp) | |
5024 | If the symbol is not external, we want | |
5025 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5026 | nop | |
5027 | addiu $25,$25,<sym> (BFD_RELOC_LO16) | |
5028 | jalr $25 | |
5029 | nop | |
5030 | lw $gp,cprestore($sp) */ | |
5031 | frag_grow (40); | |
5032 | if (! mips_big_got) | |
5033 | { | |
5034 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
ca4e0257 | 5035 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", |
252b5132 RH |
5036 | "t,o(b)", PIC_CALL_REG, |
5037 | (int) BFD_RELOC_MIPS_CALL16, GP); | |
5038 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5039 | "nop", ""); | |
5040 | p = frag_var (rs_machine_dependent, 4, 0, | |
5041 | RELAX_ENCODE (0, 4, -8, 0, 0, 0), | |
5042 | offset_expr.X_add_symbol, (offsetT) 0, | |
5043 | (char *) NULL); | |
5044 | } | |
5045 | else | |
5046 | { | |
5047 | int gpdel; | |
5048 | ||
5049 | if (reg_needs_delay (GP)) | |
5050 | gpdel = 4; | |
5051 | else | |
5052 | gpdel = 0; | |
5053 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
5054 | PIC_CALL_REG, (int) BFD_RELOC_MIPS_CALL_HI16); | |
5055 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 5056 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
5057 | "d,v,t", PIC_CALL_REG, PIC_CALL_REG, GP); |
5058 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
ca4e0257 | 5059 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", |
252b5132 RH |
5060 | "t,o(b)", PIC_CALL_REG, |
5061 | (int) BFD_RELOC_MIPS_CALL_LO16, PIC_CALL_REG); | |
5062 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5063 | "nop", ""); | |
5064 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, | |
5065 | RELAX_ENCODE (16, 12 + gpdel, gpdel, 8 + gpdel, | |
5066 | 0, 0), | |
5067 | offset_expr.X_add_symbol, (offsetT) 0, | |
5068 | (char *) NULL); | |
5069 | if (gpdel > 0) | |
5070 | { | |
5071 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
5072 | p += 4; | |
5073 | } | |
5074 | macro_build (p, &icnt, &offset_expr, | |
ca4e0257 | 5075 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", |
252b5132 RH |
5076 | "t,o(b)", PIC_CALL_REG, |
5077 | (int) BFD_RELOC_MIPS_GOT16, GP); | |
5078 | p += 4; | |
5079 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
5080 | p += 4; | |
bdaaa2e1 | 5081 | } |
252b5132 | 5082 | macro_build (p, &icnt, &offset_expr, |
ca4e0257 | 5083 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
252b5132 RH |
5084 | "t,r,j", PIC_CALL_REG, PIC_CALL_REG, |
5085 | (int) BFD_RELOC_LO16); | |
5086 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5087 | "jalr", "s", PIC_CALL_REG); | |
6478892d | 5088 | if (! HAVE_NEWABI) |
252b5132 | 5089 | { |
6478892d TS |
5090 | if (mips_cprestore_offset < 0) |
5091 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
5092 | else | |
5093 | { | |
5094 | if (mips_opts.noreorder) | |
5095 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
252b5132 | 5096 | "nop", ""); |
6478892d TS |
5097 | expr1.X_add_number = mips_cprestore_offset; |
5098 | macro_build ((char *) NULL, &icnt, &expr1, | |
5099 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", "t,o(b)", | |
5100 | GP, (int) BFD_RELOC_LO16, mips_frame_reg); | |
5101 | } | |
252b5132 RH |
5102 | } |
5103 | } | |
5104 | else if (mips_pic == EMBEDDED_PIC) | |
5105 | { | |
5106 | macro_build ((char *) NULL, &icnt, &offset_expr, "bal", "p"); | |
5107 | /* The linker may expand the call to a longer sequence which | |
5108 | uses $at, so we must break rather than return. */ | |
5109 | break; | |
5110 | } | |
5111 | else | |
5112 | abort (); | |
5113 | ||
5114 | return; | |
5115 | ||
5116 | case M_LB_AB: | |
5117 | s = "lb"; | |
5118 | goto ld; | |
5119 | case M_LBU_AB: | |
5120 | s = "lbu"; | |
5121 | goto ld; | |
5122 | case M_LH_AB: | |
5123 | s = "lh"; | |
5124 | goto ld; | |
5125 | case M_LHU_AB: | |
5126 | s = "lhu"; | |
5127 | goto ld; | |
5128 | case M_LW_AB: | |
5129 | s = "lw"; | |
5130 | goto ld; | |
5131 | case M_LWC0_AB: | |
5132 | s = "lwc0"; | |
bdaaa2e1 | 5133 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5134 | coproc = 1; |
5135 | goto ld; | |
5136 | case M_LWC1_AB: | |
5137 | s = "lwc1"; | |
bdaaa2e1 | 5138 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5139 | coproc = 1; |
5140 | goto ld; | |
5141 | case M_LWC2_AB: | |
5142 | s = "lwc2"; | |
bdaaa2e1 | 5143 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5144 | coproc = 1; |
5145 | goto ld; | |
5146 | case M_LWC3_AB: | |
5147 | s = "lwc3"; | |
bdaaa2e1 | 5148 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5149 | coproc = 1; |
5150 | goto ld; | |
5151 | case M_LWL_AB: | |
5152 | s = "lwl"; | |
5153 | lr = 1; | |
5154 | goto ld; | |
5155 | case M_LWR_AB: | |
5156 | s = "lwr"; | |
5157 | lr = 1; | |
5158 | goto ld; | |
5159 | case M_LDC1_AB: | |
ec68c924 | 5160 | if (mips_arch == CPU_R4650) |
252b5132 RH |
5161 | { |
5162 | as_bad (_("opcode not supported on this processor")); | |
5163 | return; | |
5164 | } | |
5165 | s = "ldc1"; | |
bdaaa2e1 | 5166 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5167 | coproc = 1; |
5168 | goto ld; | |
5169 | case M_LDC2_AB: | |
5170 | s = "ldc2"; | |
bdaaa2e1 | 5171 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5172 | coproc = 1; |
5173 | goto ld; | |
5174 | case M_LDC3_AB: | |
5175 | s = "ldc3"; | |
bdaaa2e1 | 5176 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5177 | coproc = 1; |
5178 | goto ld; | |
5179 | case M_LDL_AB: | |
5180 | s = "ldl"; | |
5181 | lr = 1; | |
5182 | goto ld; | |
5183 | case M_LDR_AB: | |
5184 | s = "ldr"; | |
5185 | lr = 1; | |
5186 | goto ld; | |
5187 | case M_LL_AB: | |
5188 | s = "ll"; | |
5189 | goto ld; | |
5190 | case M_LLD_AB: | |
5191 | s = "lld"; | |
5192 | goto ld; | |
5193 | case M_LWU_AB: | |
5194 | s = "lwu"; | |
5195 | ld: | |
5196 | if (breg == treg || coproc || lr) | |
5197 | { | |
5198 | tempreg = AT; | |
5199 | used_at = 1; | |
5200 | } | |
5201 | else | |
5202 | { | |
5203 | tempreg = treg; | |
5204 | used_at = 0; | |
5205 | } | |
5206 | goto ld_st; | |
5207 | case M_SB_AB: | |
5208 | s = "sb"; | |
5209 | goto st; | |
5210 | case M_SH_AB: | |
5211 | s = "sh"; | |
5212 | goto st; | |
5213 | case M_SW_AB: | |
5214 | s = "sw"; | |
5215 | goto st; | |
5216 | case M_SWC0_AB: | |
5217 | s = "swc0"; | |
bdaaa2e1 | 5218 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5219 | coproc = 1; |
5220 | goto st; | |
5221 | case M_SWC1_AB: | |
5222 | s = "swc1"; | |
bdaaa2e1 | 5223 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5224 | coproc = 1; |
5225 | goto st; | |
5226 | case M_SWC2_AB: | |
5227 | s = "swc2"; | |
bdaaa2e1 | 5228 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5229 | coproc = 1; |
5230 | goto st; | |
5231 | case M_SWC3_AB: | |
5232 | s = "swc3"; | |
bdaaa2e1 | 5233 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5234 | coproc = 1; |
5235 | goto st; | |
5236 | case M_SWL_AB: | |
5237 | s = "swl"; | |
5238 | goto st; | |
5239 | case M_SWR_AB: | |
5240 | s = "swr"; | |
5241 | goto st; | |
5242 | case M_SC_AB: | |
5243 | s = "sc"; | |
5244 | goto st; | |
5245 | case M_SCD_AB: | |
5246 | s = "scd"; | |
5247 | goto st; | |
5248 | case M_SDC1_AB: | |
ec68c924 | 5249 | if (mips_arch == CPU_R4650) |
252b5132 RH |
5250 | { |
5251 | as_bad (_("opcode not supported on this processor")); | |
5252 | return; | |
5253 | } | |
5254 | s = "sdc1"; | |
5255 | coproc = 1; | |
bdaaa2e1 | 5256 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5257 | goto st; |
5258 | case M_SDC2_AB: | |
5259 | s = "sdc2"; | |
bdaaa2e1 | 5260 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5261 | coproc = 1; |
5262 | goto st; | |
5263 | case M_SDC3_AB: | |
5264 | s = "sdc3"; | |
bdaaa2e1 | 5265 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5266 | coproc = 1; |
5267 | goto st; | |
5268 | case M_SDL_AB: | |
5269 | s = "sdl"; | |
5270 | goto st; | |
5271 | case M_SDR_AB: | |
5272 | s = "sdr"; | |
5273 | st: | |
5274 | tempreg = AT; | |
5275 | used_at = 1; | |
5276 | ld_st: | |
bdaaa2e1 | 5277 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5278 | if (mask == M_LWC1_AB |
5279 | || mask == M_SWC1_AB | |
5280 | || mask == M_LDC1_AB | |
5281 | || mask == M_SDC1_AB | |
5282 | || mask == M_L_DAB | |
5283 | || mask == M_S_DAB) | |
5284 | fmt = "T,o(b)"; | |
5285 | else if (coproc) | |
5286 | fmt = "E,o(b)"; | |
5287 | else | |
5288 | fmt = "t,o(b)"; | |
5289 | ||
5290 | if (offset_expr.X_op != O_constant | |
5291 | && offset_expr.X_op != O_symbol) | |
5292 | { | |
5293 | as_bad (_("expression too complex")); | |
5294 | offset_expr.X_op = O_constant; | |
5295 | } | |
5296 | ||
5297 | /* A constant expression in PIC code can be handled just as it | |
5298 | is in non PIC code. */ | |
5299 | if (mips_pic == NO_PIC | |
5300 | || offset_expr.X_op == O_constant) | |
5301 | { | |
5302 | /* If this is a reference to a GP relative symbol, and there | |
5303 | is no base register, we want | |
5304 | <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL) | |
5305 | Otherwise, if there is no base register, we want | |
5306 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
5307 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
5308 | If we have a constant, we need two instructions anyhow, | |
5309 | so we always use the latter form. | |
5310 | ||
5311 | If we have a base register, and this is a reference to a | |
5312 | GP relative symbol, we want | |
5313 | addu $tempreg,$breg,$gp | |
5314 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL) | |
5315 | Otherwise we want | |
5316 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
5317 | addu $tempreg,$tempreg,$breg | |
5318 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
d6bc6245 TS |
5319 | With a constant we always use the latter case. |
5320 | ||
5321 | With 64bit address space and no base register and $at usable, | |
5322 | we want | |
5323 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5324 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
5325 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5326 | dsll32 $tempreg,0 | |
5327 | daddu $tempreg,$at | |
5328 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
5329 | If we have a base register, we want | |
5330 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5331 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
5332 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5333 | daddu $at,$breg | |
5334 | dsll32 $tempreg,0 | |
5335 | daddu $tempreg,$at | |
5336 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
5337 | ||
5338 | Without $at we can't generate the optimal path for superscalar | |
5339 | processors here since this would require two temporary registers. | |
5340 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5341 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5342 | dsll $tempreg,16 | |
5343 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
5344 | dsll $tempreg,16 | |
5345 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
5346 | If we have a base register, we want | |
5347 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5348 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5349 | dsll $tempreg,16 | |
5350 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
5351 | dsll $tempreg,16 | |
5352 | daddu $tempreg,$tempreg,$breg | |
5353 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
5354 | */ | |
5355 | if (HAVE_64BIT_ADDRESSES) | |
5356 | { | |
5357 | p = NULL; | |
5358 | ||
5359 | /* We don't do GP optimization for now because RELAX_ENCODE can't | |
5360 | hold the data for such large chunks. */ | |
5361 | ||
5362 | if (used_at == 0) | |
5363 | { | |
5364 | macro_build (p, &icnt, &offset_expr, "lui", "t,u", | |
5365 | tempreg, (int) BFD_RELOC_MIPS_HIGHEST); | |
5366 | macro_build (p, &icnt, &offset_expr, "lui", "t,u", | |
5367 | AT, (int) BFD_RELOC_HI16_S); | |
5368 | macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j", | |
5369 | tempreg, tempreg, (int) BFD_RELOC_MIPS_HIGHER); | |
5370 | if (breg != 0) | |
5371 | macro_build (p, &icnt, NULL, "daddu", "d,v,t", | |
5372 | AT, AT, breg); | |
5373 | macro_build (p, &icnt, NULL, "dsll32", "d,w,<", | |
5374 | tempreg, tempreg, 0); | |
5375 | macro_build (p, &icnt, NULL, "daddu", "d,v,t", | |
5376 | tempreg, tempreg, AT); | |
5377 | macro_build (p, &icnt, &offset_expr, s, | |
5378 | fmt, treg, (int) BFD_RELOC_LO16, tempreg); | |
5379 | used_at = 1; | |
5380 | } | |
5381 | else | |
5382 | { | |
5383 | macro_build (p, &icnt, &offset_expr, "lui", "t,u", | |
5384 | tempreg, (int) BFD_RELOC_MIPS_HIGHEST); | |
5385 | macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j", | |
5386 | tempreg, tempreg, (int) BFD_RELOC_MIPS_HIGHER); | |
5387 | macro_build (p, &icnt, NULL, "dsll", "d,w,<", | |
5388 | tempreg, tempreg, 16); | |
5389 | macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j", | |
5390 | tempreg, tempreg, (int) BFD_RELOC_HI16_S); | |
5391 | macro_build (p, &icnt, NULL, "dsll", "d,w,<", | |
5392 | tempreg, tempreg, 16); | |
5393 | if (breg != 0) | |
5394 | macro_build (p, &icnt, NULL, "daddu", "d,v,t", | |
5395 | tempreg, tempreg, breg); | |
5396 | macro_build (p, &icnt, &offset_expr, s, | |
5397 | fmt, treg, (int) BFD_RELOC_LO16, tempreg); | |
5398 | } | |
5399 | ||
5400 | return; | |
5401 | } | |
5402 | ||
252b5132 RH |
5403 | if (breg == 0) |
5404 | { | |
e7d556df | 5405 | if ((valueT) offset_expr.X_add_number > MAX_GPREL_OFFSET |
252b5132 RH |
5406 | || nopic_need_relax (offset_expr.X_add_symbol, 1)) |
5407 | p = NULL; | |
5408 | else | |
5409 | { | |
5410 | frag_grow (20); | |
5411 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
5412 | treg, (int) BFD_RELOC_MIPS_GPREL, GP); | |
5413 | p = frag_var (rs_machine_dependent, 8, 0, | |
5414 | RELAX_ENCODE (4, 8, 0, 4, 0, | |
5415 | (mips_opts.warn_about_macros | |
5416 | || (used_at | |
5417 | && mips_opts.noat))), | |
5418 | offset_expr.X_add_symbol, (offsetT) 0, | |
5419 | (char *) NULL); | |
5420 | used_at = 0; | |
5421 | } | |
5422 | macro_build_lui (p, &icnt, &offset_expr, tempreg); | |
5423 | if (p != NULL) | |
5424 | p += 4; | |
5425 | macro_build (p, &icnt, &offset_expr, s, fmt, treg, | |
5426 | (int) BFD_RELOC_LO16, tempreg); | |
5427 | } | |
5428 | else | |
5429 | { | |
e7d556df | 5430 | if ((valueT) offset_expr.X_add_number > MAX_GPREL_OFFSET |
252b5132 RH |
5431 | || nopic_need_relax (offset_expr.X_add_symbol, 1)) |
5432 | p = NULL; | |
5433 | else | |
5434 | { | |
5435 | frag_grow (28); | |
5436 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 5437 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
5438 | "d,v,t", tempreg, breg, GP); |
5439 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
5440 | treg, (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
5441 | p = frag_var (rs_machine_dependent, 12, 0, | |
5442 | RELAX_ENCODE (8, 12, 0, 8, 0, 0), | |
5443 | offset_expr.X_add_symbol, (offsetT) 0, | |
5444 | (char *) NULL); | |
5445 | } | |
5446 | macro_build_lui (p, &icnt, &offset_expr, tempreg); | |
5447 | if (p != NULL) | |
5448 | p += 4; | |
5449 | macro_build (p, &icnt, (expressionS *) NULL, | |
ca4e0257 | 5450 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
5451 | "d,v,t", tempreg, tempreg, breg); |
5452 | if (p != NULL) | |
5453 | p += 4; | |
5454 | macro_build (p, &icnt, &offset_expr, s, fmt, treg, | |
5455 | (int) BFD_RELOC_LO16, tempreg); | |
5456 | } | |
5457 | } | |
5458 | else if (mips_pic == SVR4_PIC && ! mips_big_got) | |
5459 | { | |
5460 | /* If this is a reference to an external symbol, we want | |
5461 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5462 | nop | |
5463 | <op> $treg,0($tempreg) | |
5464 | Otherwise we want | |
5465 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5466 | nop | |
5467 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
5468 | <op> $treg,0($tempreg) | |
5469 | If there is a base register, we add it to $tempreg before | |
5470 | the <op>. If there is a constant, we stick it in the | |
5471 | <op> instruction. We don't handle constants larger than | |
5472 | 16 bits, because we have no way to load the upper 16 bits | |
5473 | (actually, we could handle them for the subset of cases | |
5474 | in which we are not using $at). */ | |
5475 | assert (offset_expr.X_op == O_symbol); | |
5476 | expr1.X_add_number = offset_expr.X_add_number; | |
5477 | offset_expr.X_add_number = 0; | |
5478 | if (expr1.X_add_number < -0x8000 | |
5479 | || expr1.X_add_number >= 0x8000) | |
5480 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
5481 | frag_grow (20); | |
5482 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
ca4e0257 | 5483 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", |
252b5132 RH |
5484 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, GP); |
5485 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); | |
bdaaa2e1 | 5486 | p = frag_var (rs_machine_dependent, 4, 0, |
252b5132 RH |
5487 | RELAX_ENCODE (0, 4, -8, 0, 0, 0), |
5488 | offset_expr.X_add_symbol, (offsetT) 0, | |
5489 | (char *) NULL); | |
5490 | macro_build (p, &icnt, &offset_expr, | |
ca4e0257 | 5491 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
252b5132 RH |
5492 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
5493 | if (breg != 0) | |
5494 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 5495 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
5496 | "d,v,t", tempreg, tempreg, breg); |
5497 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, treg, | |
5498 | (int) BFD_RELOC_LO16, tempreg); | |
5499 | } | |
5500 | else if (mips_pic == SVR4_PIC) | |
5501 | { | |
5502 | int gpdel; | |
5503 | ||
5504 | /* If this is a reference to an external symbol, we want | |
5505 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5506 | addu $tempreg,$tempreg,$gp | |
5507 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5508 | <op> $treg,0($tempreg) | |
5509 | Otherwise we want | |
5510 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5511 | nop | |
5512 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
5513 | <op> $treg,0($tempreg) | |
5514 | If there is a base register, we add it to $tempreg before | |
5515 | the <op>. If there is a constant, we stick it in the | |
5516 | <op> instruction. We don't handle constants larger than | |
5517 | 16 bits, because we have no way to load the upper 16 bits | |
5518 | (actually, we could handle them for the subset of cases | |
5519 | in which we are not using $at). */ | |
5520 | assert (offset_expr.X_op == O_symbol); | |
5521 | expr1.X_add_number = offset_expr.X_add_number; | |
5522 | offset_expr.X_add_number = 0; | |
5523 | if (expr1.X_add_number < -0x8000 | |
5524 | || expr1.X_add_number >= 0x8000) | |
5525 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
5526 | if (reg_needs_delay (GP)) | |
5527 | gpdel = 4; | |
5528 | else | |
5529 | gpdel = 0; | |
5530 | frag_grow (36); | |
5531 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
5532 | tempreg, (int) BFD_RELOC_MIPS_GOT_HI16); | |
5533 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 5534 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
5535 | "d,v,t", tempreg, tempreg, GP); |
5536 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
ca4e0257 | 5537 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", |
252b5132 RH |
5538 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT_LO16, |
5539 | tempreg); | |
5540 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, | |
5541 | RELAX_ENCODE (12, 12 + gpdel, gpdel, 8 + gpdel, 0, 0), | |
5542 | offset_expr.X_add_symbol, (offsetT) 0, (char *) NULL); | |
5543 | if (gpdel > 0) | |
5544 | { | |
5545 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
5546 | p += 4; | |
5547 | } | |
5548 | macro_build (p, &icnt, &offset_expr, | |
ca4e0257 | 5549 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", |
252b5132 RH |
5550 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, GP); |
5551 | p += 4; | |
5552 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
5553 | p += 4; | |
5554 | macro_build (p, &icnt, &offset_expr, | |
ca4e0257 | 5555 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
252b5132 RH |
5556 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
5557 | if (breg != 0) | |
5558 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 5559 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
5560 | "d,v,t", tempreg, tempreg, breg); |
5561 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, treg, | |
5562 | (int) BFD_RELOC_LO16, tempreg); | |
5563 | } | |
5564 | else if (mips_pic == EMBEDDED_PIC) | |
5565 | { | |
5566 | /* If there is no base register, we want | |
5567 | <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL) | |
5568 | If there is a base register, we want | |
5569 | addu $tempreg,$breg,$gp | |
5570 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL) | |
5571 | */ | |
5572 | assert (offset_expr.X_op == O_symbol); | |
5573 | if (breg == 0) | |
5574 | { | |
5575 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
5576 | treg, (int) BFD_RELOC_MIPS_GPREL, GP); | |
5577 | used_at = 0; | |
5578 | } | |
5579 | else | |
5580 | { | |
5581 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 5582 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
5583 | "d,v,t", tempreg, breg, GP); |
5584 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
5585 | treg, (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
5586 | } | |
5587 | } | |
5588 | else | |
5589 | abort (); | |
5590 | ||
5591 | if (! used_at) | |
5592 | return; | |
5593 | ||
5594 | break; | |
5595 | ||
5596 | case M_LI: | |
5597 | case M_LI_S: | |
5598 | load_register (&icnt, treg, &imm_expr, 0); | |
5599 | return; | |
5600 | ||
5601 | case M_DLI: | |
5602 | load_register (&icnt, treg, &imm_expr, 1); | |
5603 | return; | |
5604 | ||
5605 | case M_LI_SS: | |
5606 | if (imm_expr.X_op == O_constant) | |
5607 | { | |
5608 | load_register (&icnt, AT, &imm_expr, 0); | |
5609 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5610 | "mtc1", "t,G", AT, treg); | |
5611 | break; | |
5612 | } | |
5613 | else | |
5614 | { | |
5615 | assert (offset_expr.X_op == O_symbol | |
5616 | && strcmp (segment_name (S_GET_SEGMENT | |
5617 | (offset_expr.X_add_symbol)), | |
5618 | ".lit4") == 0 | |
5619 | && offset_expr.X_add_number == 0); | |
5620 | macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)", | |
5621 | treg, (int) BFD_RELOC_MIPS_LITERAL, GP); | |
5622 | return; | |
5623 | } | |
5624 | ||
5625 | case M_LI_D: | |
ca4e0257 RS |
5626 | /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits |
5627 | wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high | |
5628 | order 32 bits of the value and the low order 32 bits are either | |
5629 | zero or in OFFSET_EXPR. */ | |
252b5132 RH |
5630 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) |
5631 | { | |
ca4e0257 | 5632 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
5633 | load_register (&icnt, treg, &imm_expr, 1); |
5634 | else | |
5635 | { | |
5636 | int hreg, lreg; | |
5637 | ||
5638 | if (target_big_endian) | |
5639 | { | |
5640 | hreg = treg; | |
5641 | lreg = treg + 1; | |
5642 | } | |
5643 | else | |
5644 | { | |
5645 | hreg = treg + 1; | |
5646 | lreg = treg; | |
5647 | } | |
5648 | ||
5649 | if (hreg <= 31) | |
5650 | load_register (&icnt, hreg, &imm_expr, 0); | |
5651 | if (lreg <= 31) | |
5652 | { | |
5653 | if (offset_expr.X_op == O_absent) | |
ea1fb5dc | 5654 | move_register (&icnt, lreg, 0); |
252b5132 RH |
5655 | else |
5656 | { | |
5657 | assert (offset_expr.X_op == O_constant); | |
5658 | load_register (&icnt, lreg, &offset_expr, 0); | |
5659 | } | |
5660 | } | |
5661 | } | |
5662 | return; | |
5663 | } | |
5664 | ||
5665 | /* We know that sym is in the .rdata section. First we get the | |
5666 | upper 16 bits of the address. */ | |
5667 | if (mips_pic == NO_PIC) | |
5668 | { | |
5669 | /* FIXME: This won't work for a 64 bit address. */ | |
5670 | macro_build_lui ((char *) NULL, &icnt, &offset_expr, AT); | |
5671 | } | |
5672 | else if (mips_pic == SVR4_PIC) | |
5673 | { | |
5674 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
ca4e0257 | 5675 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", |
252b5132 RH |
5676 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP); |
5677 | } | |
5678 | else if (mips_pic == EMBEDDED_PIC) | |
5679 | { | |
5680 | /* For embedded PIC we pick up the entire address off $gp in | |
5681 | a single instruction. */ | |
5682 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
ca4e0257 | 5683 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
252b5132 RH |
5684 | "t,r,j", AT, GP, (int) BFD_RELOC_MIPS_GPREL); |
5685 | offset_expr.X_op = O_constant; | |
5686 | offset_expr.X_add_number = 0; | |
5687 | } | |
5688 | else | |
5689 | abort (); | |
bdaaa2e1 | 5690 | |
252b5132 | 5691 | /* Now we load the register(s). */ |
ca4e0257 | 5692 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
5693 | macro_build ((char *) NULL, &icnt, &offset_expr, "ld", "t,o(b)", |
5694 | treg, (int) BFD_RELOC_LO16, AT); | |
5695 | else | |
5696 | { | |
5697 | macro_build ((char *) NULL, &icnt, &offset_expr, "lw", "t,o(b)", | |
5698 | treg, (int) BFD_RELOC_LO16, AT); | |
5699 | if (treg != 31) | |
5700 | { | |
5701 | /* FIXME: How in the world do we deal with the possible | |
5702 | overflow here? */ | |
5703 | offset_expr.X_add_number += 4; | |
5704 | macro_build ((char *) NULL, &icnt, &offset_expr, "lw", "t,o(b)", | |
5705 | treg + 1, (int) BFD_RELOC_LO16, AT); | |
5706 | } | |
5707 | } | |
5708 | ||
5709 | /* To avoid confusion in tc_gen_reloc, we must ensure that this | |
5710 | does not become a variant frag. */ | |
5711 | frag_wane (frag_now); | |
5712 | frag_new (0); | |
5713 | ||
5714 | break; | |
5715 | ||
5716 | case M_LI_DD: | |
ca4e0257 RS |
5717 | /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits |
5718 | wide, IMM_EXPR is the entire value and the GPRs are known to be 64 | |
5719 | bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of | |
5720 | the value and the low order 32 bits are either zero or in | |
5721 | OFFSET_EXPR. */ | |
252b5132 RH |
5722 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) |
5723 | { | |
ca4e0257 RS |
5724 | load_register (&icnt, AT, &imm_expr, HAVE_64BIT_FPRS); |
5725 | if (HAVE_64BIT_FPRS) | |
5726 | { | |
5727 | assert (HAVE_64BIT_GPRS); | |
5728 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5729 | "dmtc1", "t,S", AT, treg); | |
5730 | } | |
252b5132 RH |
5731 | else |
5732 | { | |
5733 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5734 | "mtc1", "t,G", AT, treg + 1); | |
5735 | if (offset_expr.X_op == O_absent) | |
5736 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5737 | "mtc1", "t,G", 0, treg); | |
5738 | else | |
5739 | { | |
5740 | assert (offset_expr.X_op == O_constant); | |
5741 | load_register (&icnt, AT, &offset_expr, 0); | |
5742 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5743 | "mtc1", "t,G", AT, treg); | |
5744 | } | |
5745 | } | |
5746 | break; | |
5747 | } | |
5748 | ||
5749 | assert (offset_expr.X_op == O_symbol | |
5750 | && offset_expr.X_add_number == 0); | |
5751 | s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol)); | |
5752 | if (strcmp (s, ".lit8") == 0) | |
5753 | { | |
e7af610e | 5754 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 RH |
5755 | { |
5756 | macro_build ((char *) NULL, &icnt, &offset_expr, "ldc1", | |
5757 | "T,o(b)", treg, (int) BFD_RELOC_MIPS_LITERAL, GP); | |
5758 | return; | |
5759 | } | |
5760 | breg = GP; | |
5761 | r = BFD_RELOC_MIPS_LITERAL; | |
5762 | goto dob; | |
5763 | } | |
5764 | else | |
5765 | { | |
5766 | assert (strcmp (s, RDATA_SECTION_NAME) == 0); | |
5767 | if (mips_pic == SVR4_PIC) | |
5768 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
ca4e0257 | 5769 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", |
252b5132 RH |
5770 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP); |
5771 | else | |
5772 | { | |
5773 | /* FIXME: This won't work for a 64 bit address. */ | |
5774 | macro_build_lui ((char *) NULL, &icnt, &offset_expr, AT); | |
5775 | } | |
bdaaa2e1 | 5776 | |
e7af610e | 5777 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 RH |
5778 | { |
5779 | macro_build ((char *) NULL, &icnt, &offset_expr, "ldc1", | |
5780 | "T,o(b)", treg, (int) BFD_RELOC_LO16, AT); | |
5781 | ||
5782 | /* To avoid confusion in tc_gen_reloc, we must ensure | |
5783 | that this does not become a variant frag. */ | |
5784 | frag_wane (frag_now); | |
5785 | frag_new (0); | |
5786 | ||
5787 | break; | |
5788 | } | |
5789 | breg = AT; | |
5790 | r = BFD_RELOC_LO16; | |
5791 | goto dob; | |
5792 | } | |
5793 | ||
5794 | case M_L_DOB: | |
ec68c924 | 5795 | if (mips_arch == CPU_R4650) |
252b5132 RH |
5796 | { |
5797 | as_bad (_("opcode not supported on this processor")); | |
5798 | return; | |
5799 | } | |
5800 | /* Even on a big endian machine $fn comes before $fn+1. We have | |
5801 | to adjust when loading from memory. */ | |
5802 | r = BFD_RELOC_LO16; | |
5803 | dob: | |
e7af610e | 5804 | assert (mips_opts.isa == ISA_MIPS1); |
252b5132 RH |
5805 | macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)", |
5806 | target_big_endian ? treg + 1 : treg, | |
5807 | (int) r, breg); | |
5808 | /* FIXME: A possible overflow which I don't know how to deal | |
5809 | with. */ | |
5810 | offset_expr.X_add_number += 4; | |
5811 | macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)", | |
5812 | target_big_endian ? treg : treg + 1, | |
5813 | (int) r, breg); | |
5814 | ||
5815 | /* To avoid confusion in tc_gen_reloc, we must ensure that this | |
5816 | does not become a variant frag. */ | |
5817 | frag_wane (frag_now); | |
5818 | frag_new (0); | |
5819 | ||
5820 | if (breg != AT) | |
5821 | return; | |
5822 | break; | |
5823 | ||
5824 | case M_L_DAB: | |
5825 | /* | |
5826 | * The MIPS assembler seems to check for X_add_number not | |
5827 | * being double aligned and generating: | |
5828 | * lui at,%hi(foo+1) | |
5829 | * addu at,at,v1 | |
5830 | * addiu at,at,%lo(foo+1) | |
5831 | * lwc1 f2,0(at) | |
5832 | * lwc1 f3,4(at) | |
5833 | * But, the resulting address is the same after relocation so why | |
5834 | * generate the extra instruction? | |
5835 | */ | |
ec68c924 | 5836 | if (mips_arch == CPU_R4650) |
252b5132 RH |
5837 | { |
5838 | as_bad (_("opcode not supported on this processor")); | |
5839 | return; | |
5840 | } | |
bdaaa2e1 | 5841 | /* Itbl support may require additional care here. */ |
252b5132 | 5842 | coproc = 1; |
e7af610e | 5843 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 RH |
5844 | { |
5845 | s = "ldc1"; | |
5846 | goto ld; | |
5847 | } | |
5848 | ||
5849 | s = "lwc1"; | |
5850 | fmt = "T,o(b)"; | |
5851 | goto ldd_std; | |
5852 | ||
5853 | case M_S_DAB: | |
ec68c924 | 5854 | if (mips_arch == CPU_R4650) |
252b5132 RH |
5855 | { |
5856 | as_bad (_("opcode not supported on this processor")); | |
5857 | return; | |
5858 | } | |
5859 | ||
e7af610e | 5860 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 RH |
5861 | { |
5862 | s = "sdc1"; | |
5863 | goto st; | |
5864 | } | |
5865 | ||
5866 | s = "swc1"; | |
5867 | fmt = "T,o(b)"; | |
bdaaa2e1 | 5868 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5869 | coproc = 1; |
5870 | goto ldd_std; | |
5871 | ||
5872 | case M_LD_AB: | |
ca4e0257 | 5873 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
5874 | { |
5875 | s = "ld"; | |
5876 | goto ld; | |
5877 | } | |
5878 | ||
5879 | s = "lw"; | |
5880 | fmt = "t,o(b)"; | |
5881 | goto ldd_std; | |
5882 | ||
5883 | case M_SD_AB: | |
ca4e0257 | 5884 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
5885 | { |
5886 | s = "sd"; | |
5887 | goto st; | |
5888 | } | |
5889 | ||
5890 | s = "sw"; | |
5891 | fmt = "t,o(b)"; | |
5892 | ||
5893 | ldd_std: | |
5894 | if (offset_expr.X_op != O_symbol | |
5895 | && offset_expr.X_op != O_constant) | |
5896 | { | |
5897 | as_bad (_("expression too complex")); | |
5898 | offset_expr.X_op = O_constant; | |
5899 | } | |
5900 | ||
5901 | /* Even on a big endian machine $fn comes before $fn+1. We have | |
5902 | to adjust when loading from memory. We set coproc if we must | |
5903 | load $fn+1 first. */ | |
bdaaa2e1 | 5904 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5905 | if (! target_big_endian) |
5906 | coproc = 0; | |
5907 | ||
5908 | if (mips_pic == NO_PIC | |
5909 | || offset_expr.X_op == O_constant) | |
5910 | { | |
5911 | /* If this is a reference to a GP relative symbol, we want | |
5912 | <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL) | |
5913 | <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL) | |
5914 | If we have a base register, we use this | |
5915 | addu $at,$breg,$gp | |
5916 | <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL) | |
5917 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL) | |
5918 | If this is not a GP relative symbol, we want | |
5919 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
5920 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
5921 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
5922 | If there is a base register, we add it to $at after the | |
5923 | lui instruction. If there is a constant, we always use | |
5924 | the last case. */ | |
e7d556df | 5925 | if ((valueT) offset_expr.X_add_number > MAX_GPREL_OFFSET |
252b5132 RH |
5926 | || nopic_need_relax (offset_expr.X_add_symbol, 1)) |
5927 | { | |
5928 | p = NULL; | |
5929 | used_at = 1; | |
5930 | } | |
5931 | else | |
5932 | { | |
5933 | int off; | |
5934 | ||
5935 | if (breg == 0) | |
5936 | { | |
5937 | frag_grow (28); | |
5938 | tempreg = GP; | |
5939 | off = 0; | |
5940 | used_at = 0; | |
5941 | } | |
5942 | else | |
5943 | { | |
5944 | frag_grow (36); | |
5945 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 5946 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
5947 | "d,v,t", AT, breg, GP); |
5948 | tempreg = AT; | |
5949 | off = 4; | |
5950 | used_at = 1; | |
5951 | } | |
5952 | ||
beae10d5 | 5953 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5954 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
5955 | coproc ? treg + 1 : treg, | |
5956 | (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
5957 | offset_expr.X_add_number += 4; | |
5958 | ||
5959 | /* Set mips_optimize to 2 to avoid inserting an | |
5960 | undesired nop. */ | |
5961 | hold_mips_optimize = mips_optimize; | |
5962 | mips_optimize = 2; | |
beae10d5 | 5963 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5964 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
5965 | coproc ? treg : treg + 1, | |
5966 | (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
5967 | mips_optimize = hold_mips_optimize; | |
5968 | ||
5969 | p = frag_var (rs_machine_dependent, 12 + off, 0, | |
5970 | RELAX_ENCODE (8 + off, 12 + off, 0, 4 + off, 1, | |
5971 | used_at && mips_opts.noat), | |
5972 | offset_expr.X_add_symbol, (offsetT) 0, | |
5973 | (char *) NULL); | |
5974 | ||
5975 | /* We just generated two relocs. When tc_gen_reloc | |
5976 | handles this case, it will skip the first reloc and | |
5977 | handle the second. The second reloc already has an | |
5978 | extra addend of 4, which we added above. We must | |
5979 | subtract it out, and then subtract another 4 to make | |
5980 | the first reloc come out right. The second reloc | |
5981 | will come out right because we are going to add 4 to | |
5982 | offset_expr when we build its instruction below. | |
5983 | ||
5984 | If we have a symbol, then we don't want to include | |
5985 | the offset, because it will wind up being included | |
5986 | when we generate the reloc. */ | |
5987 | ||
5988 | if (offset_expr.X_op == O_constant) | |
5989 | offset_expr.X_add_number -= 8; | |
5990 | else | |
5991 | { | |
5992 | offset_expr.X_add_number = -4; | |
5993 | offset_expr.X_op = O_constant; | |
5994 | } | |
5995 | } | |
5996 | macro_build_lui (p, &icnt, &offset_expr, AT); | |
5997 | if (p != NULL) | |
5998 | p += 4; | |
5999 | if (breg != 0) | |
6000 | { | |
6001 | macro_build (p, &icnt, (expressionS *) NULL, | |
ca4e0257 | 6002 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
6003 | "d,v,t", AT, breg, AT); |
6004 | if (p != NULL) | |
6005 | p += 4; | |
6006 | } | |
beae10d5 | 6007 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6008 | macro_build (p, &icnt, &offset_expr, s, fmt, |
6009 | coproc ? treg + 1 : treg, | |
6010 | (int) BFD_RELOC_LO16, AT); | |
6011 | if (p != NULL) | |
6012 | p += 4; | |
6013 | /* FIXME: How do we handle overflow here? */ | |
6014 | offset_expr.X_add_number += 4; | |
beae10d5 | 6015 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6016 | macro_build (p, &icnt, &offset_expr, s, fmt, |
6017 | coproc ? treg : treg + 1, | |
6018 | (int) BFD_RELOC_LO16, AT); | |
bdaaa2e1 | 6019 | } |
252b5132 RH |
6020 | else if (mips_pic == SVR4_PIC && ! mips_big_got) |
6021 | { | |
6022 | int off; | |
6023 | ||
6024 | /* If this is a reference to an external symbol, we want | |
6025 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6026 | nop | |
6027 | <op> $treg,0($at) | |
6028 | <op> $treg+1,4($at) | |
6029 | Otherwise we want | |
6030 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6031 | nop | |
6032 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
6033 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
6034 | If there is a base register we add it to $at before the | |
6035 | lwc1 instructions. If there is a constant we include it | |
6036 | in the lwc1 instructions. */ | |
6037 | used_at = 1; | |
6038 | expr1.X_add_number = offset_expr.X_add_number; | |
6039 | offset_expr.X_add_number = 0; | |
6040 | if (expr1.X_add_number < -0x8000 | |
6041 | || expr1.X_add_number >= 0x8000 - 4) | |
6042 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
6043 | if (breg == 0) | |
6044 | off = 0; | |
6045 | else | |
6046 | off = 4; | |
6047 | frag_grow (24 + off); | |
6048 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
ca4e0257 | 6049 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", |
252b5132 RH |
6050 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP); |
6051 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); | |
6052 | if (breg != 0) | |
6053 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 6054 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 | 6055 | "d,v,t", AT, breg, AT); |
beae10d5 | 6056 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6057 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, |
6058 | coproc ? treg + 1 : treg, | |
6059 | (int) BFD_RELOC_LO16, AT); | |
6060 | expr1.X_add_number += 4; | |
6061 | ||
6062 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
6063 | nop. */ | |
6064 | hold_mips_optimize = mips_optimize; | |
6065 | mips_optimize = 2; | |
beae10d5 | 6066 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6067 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, |
6068 | coproc ? treg : treg + 1, | |
6069 | (int) BFD_RELOC_LO16, AT); | |
6070 | mips_optimize = hold_mips_optimize; | |
6071 | ||
6072 | (void) frag_var (rs_machine_dependent, 0, 0, | |
6073 | RELAX_ENCODE (0, 0, -16 - off, -8, 1, 0), | |
6074 | offset_expr.X_add_symbol, (offsetT) 0, | |
6075 | (char *) NULL); | |
6076 | } | |
6077 | else if (mips_pic == SVR4_PIC) | |
6078 | { | |
6079 | int gpdel, off; | |
6080 | ||
6081 | /* If this is a reference to an external symbol, we want | |
6082 | lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
6083 | addu $at,$at,$gp | |
6084 | lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16) | |
6085 | nop | |
6086 | <op> $treg,0($at) | |
6087 | <op> $treg+1,4($at) | |
6088 | Otherwise we want | |
6089 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6090 | nop | |
6091 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
6092 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
6093 | If there is a base register we add it to $at before the | |
6094 | lwc1 instructions. If there is a constant we include it | |
6095 | in the lwc1 instructions. */ | |
6096 | used_at = 1; | |
6097 | expr1.X_add_number = offset_expr.X_add_number; | |
6098 | offset_expr.X_add_number = 0; | |
6099 | if (expr1.X_add_number < -0x8000 | |
6100 | || expr1.X_add_number >= 0x8000 - 4) | |
6101 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
6102 | if (reg_needs_delay (GP)) | |
6103 | gpdel = 4; | |
6104 | else | |
6105 | gpdel = 0; | |
6106 | if (breg == 0) | |
6107 | off = 0; | |
6108 | else | |
6109 | off = 4; | |
6110 | frag_grow (56); | |
6111 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
6112 | AT, (int) BFD_RELOC_MIPS_GOT_HI16); | |
6113 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 6114 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
6115 | "d,v,t", AT, AT, GP); |
6116 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
ca4e0257 | 6117 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", |
252b5132 RH |
6118 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT_LO16, AT); |
6119 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); | |
6120 | if (breg != 0) | |
6121 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 6122 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 | 6123 | "d,v,t", AT, breg, AT); |
beae10d5 | 6124 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6125 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, |
6126 | coproc ? treg + 1 : treg, | |
6127 | (int) BFD_RELOC_LO16, AT); | |
6128 | expr1.X_add_number += 4; | |
6129 | ||
6130 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
6131 | nop. */ | |
6132 | hold_mips_optimize = mips_optimize; | |
6133 | mips_optimize = 2; | |
beae10d5 | 6134 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6135 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, |
6136 | coproc ? treg : treg + 1, | |
6137 | (int) BFD_RELOC_LO16, AT); | |
6138 | mips_optimize = hold_mips_optimize; | |
6139 | expr1.X_add_number -= 4; | |
6140 | ||
6141 | p = frag_var (rs_machine_dependent, 16 + gpdel + off, 0, | |
6142 | RELAX_ENCODE (24 + off, 16 + gpdel + off, gpdel, | |
6143 | 8 + gpdel + off, 1, 0), | |
6144 | offset_expr.X_add_symbol, (offsetT) 0, | |
6145 | (char *) NULL); | |
6146 | if (gpdel > 0) | |
6147 | { | |
6148 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
6149 | p += 4; | |
6150 | } | |
6151 | macro_build (p, &icnt, &offset_expr, | |
ca4e0257 | 6152 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", |
252b5132 RH |
6153 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP); |
6154 | p += 4; | |
6155 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
6156 | p += 4; | |
6157 | if (breg != 0) | |
6158 | { | |
6159 | macro_build (p, &icnt, (expressionS *) NULL, | |
ca4e0257 | 6160 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
6161 | "d,v,t", AT, breg, AT); |
6162 | p += 4; | |
6163 | } | |
beae10d5 | 6164 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6165 | macro_build (p, &icnt, &expr1, s, fmt, |
6166 | coproc ? treg + 1 : treg, | |
6167 | (int) BFD_RELOC_LO16, AT); | |
6168 | p += 4; | |
6169 | expr1.X_add_number += 4; | |
6170 | ||
6171 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
6172 | nop. */ | |
6173 | hold_mips_optimize = mips_optimize; | |
6174 | mips_optimize = 2; | |
beae10d5 | 6175 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6176 | macro_build (p, &icnt, &expr1, s, fmt, |
6177 | coproc ? treg : treg + 1, | |
6178 | (int) BFD_RELOC_LO16, AT); | |
6179 | mips_optimize = hold_mips_optimize; | |
6180 | } | |
6181 | else if (mips_pic == EMBEDDED_PIC) | |
6182 | { | |
6183 | /* If there is no base register, we use | |
6184 | <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL) | |
6185 | <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL) | |
6186 | If we have a base register, we use | |
6187 | addu $at,$breg,$gp | |
6188 | <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL) | |
6189 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL) | |
6190 | */ | |
6191 | if (breg == 0) | |
6192 | { | |
6193 | tempreg = GP; | |
6194 | used_at = 0; | |
6195 | } | |
6196 | else | |
6197 | { | |
6198 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 6199 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
6200 | "d,v,t", AT, breg, GP); |
6201 | tempreg = AT; | |
6202 | used_at = 1; | |
6203 | } | |
6204 | ||
beae10d5 | 6205 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6206 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
6207 | coproc ? treg + 1 : treg, | |
6208 | (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
6209 | offset_expr.X_add_number += 4; | |
beae10d5 | 6210 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6211 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
6212 | coproc ? treg : treg + 1, | |
6213 | (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
6214 | } | |
6215 | else | |
6216 | abort (); | |
6217 | ||
6218 | if (! used_at) | |
6219 | return; | |
6220 | ||
6221 | break; | |
6222 | ||
6223 | case M_LD_OB: | |
6224 | s = "lw"; | |
6225 | goto sd_ob; | |
6226 | case M_SD_OB: | |
6227 | s = "sw"; | |
6228 | sd_ob: | |
ca4e0257 | 6229 | assert (HAVE_32BIT_ADDRESSES); |
252b5132 RH |
6230 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, |
6231 | (int) BFD_RELOC_LO16, breg); | |
6232 | offset_expr.X_add_number += 4; | |
6233 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg + 1, | |
6234 | (int) BFD_RELOC_LO16, breg); | |
6235 | return; | |
6236 | ||
6237 | /* New code added to support COPZ instructions. | |
6238 | This code builds table entries out of the macros in mip_opcodes. | |
6239 | R4000 uses interlocks to handle coproc delays. | |
6240 | Other chips (like the R3000) require nops to be inserted for delays. | |
6241 | ||
f72c8c98 | 6242 | FIXME: Currently, we require that the user handle delays. |
252b5132 RH |
6243 | In order to fill delay slots for non-interlocked chips, |
6244 | we must have a way to specify delays based on the coprocessor. | |
6245 | Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc. | |
6246 | What are the side-effects of the cop instruction? | |
6247 | What cache support might we have and what are its effects? | |
6248 | Both coprocessor & memory require delays. how long??? | |
bdaaa2e1 | 6249 | What registers are read/set/modified? |
252b5132 RH |
6250 | |
6251 | If an itbl is provided to interpret cop instructions, | |
bdaaa2e1 | 6252 | this knowledge can be encoded in the itbl spec. */ |
252b5132 RH |
6253 | |
6254 | case M_COP0: | |
6255 | s = "c0"; | |
6256 | goto copz; | |
6257 | case M_COP1: | |
6258 | s = "c1"; | |
6259 | goto copz; | |
6260 | case M_COP2: | |
6261 | s = "c2"; | |
6262 | goto copz; | |
6263 | case M_COP3: | |
6264 | s = "c3"; | |
6265 | copz: | |
6266 | /* For now we just do C (same as Cz). The parameter will be | |
6267 | stored in insn_opcode by mips_ip. */ | |
6268 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "C", | |
6269 | ip->insn_opcode); | |
6270 | return; | |
6271 | ||
ea1fb5dc RS |
6272 | case M_MOVE: |
6273 | move_register (&icnt, dreg, sreg); | |
6274 | return; | |
6275 | ||
252b5132 RH |
6276 | #ifdef LOSING_COMPILER |
6277 | default: | |
6278 | /* Try and see if this is a new itbl instruction. | |
6279 | This code builds table entries out of the macros in mip_opcodes. | |
6280 | FIXME: For now we just assemble the expression and pass it's | |
6281 | value along as a 32-bit immediate. | |
bdaaa2e1 | 6282 | We may want to have the assembler assemble this value, |
252b5132 RH |
6283 | so that we gain the assembler's knowledge of delay slots, |
6284 | symbols, etc. | |
6285 | Would it be more efficient to use mask (id) here? */ | |
bdaaa2e1 | 6286 | if (itbl_have_entries |
252b5132 | 6287 | && (immed_expr = itbl_assemble (ip->insn_mo->name, ""))) |
beae10d5 | 6288 | { |
252b5132 RH |
6289 | s = ip->insn_mo->name; |
6290 | s2 = "cop3"; | |
6291 | coproc = ITBL_DECODE_PNUM (immed_expr);; | |
6292 | macro_build ((char *) NULL, &icnt, &immed_expr, s, "C"); | |
6293 | return; | |
beae10d5 | 6294 | } |
252b5132 RH |
6295 | macro2 (ip); |
6296 | return; | |
6297 | } | |
6298 | if (mips_opts.noat) | |
6299 | as_warn (_("Macro used $at after \".set noat\"")); | |
6300 | } | |
bdaaa2e1 | 6301 | |
252b5132 RH |
6302 | static void |
6303 | macro2 (ip) | |
6304 | struct mips_cl_insn *ip; | |
6305 | { | |
6306 | register int treg, sreg, dreg, breg; | |
6307 | int tempreg; | |
6308 | int mask; | |
6309 | int icnt = 0; | |
6310 | int used_at; | |
6311 | expressionS expr1; | |
6312 | const char *s; | |
6313 | const char *s2; | |
6314 | const char *fmt; | |
6315 | int likely = 0; | |
6316 | int dbl = 0; | |
6317 | int coproc = 0; | |
6318 | int lr = 0; | |
6319 | int imm = 0; | |
6320 | int off; | |
6321 | offsetT maxnum; | |
6322 | bfd_reloc_code_real_type r; | |
6323 | char *p; | |
bdaaa2e1 | 6324 | |
252b5132 RH |
6325 | treg = (ip->insn_opcode >> 16) & 0x1f; |
6326 | dreg = (ip->insn_opcode >> 11) & 0x1f; | |
6327 | sreg = breg = (ip->insn_opcode >> 21) & 0x1f; | |
6328 | mask = ip->insn_mo->mask; | |
bdaaa2e1 | 6329 | |
252b5132 RH |
6330 | expr1.X_op = O_constant; |
6331 | expr1.X_op_symbol = NULL; | |
6332 | expr1.X_add_symbol = NULL; | |
6333 | expr1.X_add_number = 1; | |
bdaaa2e1 | 6334 | |
252b5132 RH |
6335 | switch (mask) |
6336 | { | |
6337 | #endif /* LOSING_COMPILER */ | |
6338 | ||
6339 | case M_DMUL: | |
6340 | dbl = 1; | |
6341 | case M_MUL: | |
6342 | macro_build ((char *) NULL, &icnt, NULL, | |
6343 | dbl ? "dmultu" : "multu", | |
6344 | "s,t", sreg, treg); | |
6345 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); | |
6346 | return; | |
6347 | ||
6348 | case M_DMUL_I: | |
6349 | dbl = 1; | |
6350 | case M_MUL_I: | |
6351 | /* The MIPS assembler some times generates shifts and adds. I'm | |
6352 | not trying to be that fancy. GCC should do this for us | |
6353 | anyway. */ | |
6354 | load_register (&icnt, AT, &imm_expr, dbl); | |
6355 | macro_build ((char *) NULL, &icnt, NULL, | |
9a41af64 | 6356 | dbl ? "dmult" : "mult", "s,t", sreg, AT); |
252b5132 RH |
6357 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); |
6358 | break; | |
6359 | ||
6360 | case M_DMULO_I: | |
6361 | dbl = 1; | |
6362 | case M_MULO_I: | |
6363 | imm = 1; | |
6364 | goto do_mulo; | |
6365 | ||
6366 | case M_DMULO: | |
6367 | dbl = 1; | |
6368 | case M_MULO: | |
6369 | do_mulo: | |
6370 | mips_emit_delays (true); | |
6371 | ++mips_opts.noreorder; | |
6372 | mips_any_noreorder = 1; | |
6373 | if (imm) | |
6374 | load_register (&icnt, AT, &imm_expr, dbl); | |
6375 | macro_build ((char *) NULL, &icnt, NULL, | |
9a41af64 | 6376 | dbl ? "dmult" : "mult", "s,t", sreg, imm ? AT : treg); |
252b5132 RH |
6377 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); |
6378 | macro_build ((char *) NULL, &icnt, NULL, | |
9a41af64 | 6379 | dbl ? "dsra32" : "sra", "d,w,<", dreg, dreg, 31); |
252b5132 RH |
6380 | macro_build ((char *) NULL, &icnt, NULL, "mfhi", "d", AT); |
6381 | if (mips_trap) | |
6382 | macro_build ((char *) NULL, &icnt, NULL, "tne", "s,t", dreg, AT); | |
6383 | else | |
6384 | { | |
6385 | expr1.X_add_number = 8; | |
6386 | macro_build ((char *) NULL, &icnt, &expr1, "beq", "s,t,p", dreg, AT); | |
6387 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); | |
beae10d5 | 6388 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 6); |
252b5132 RH |
6389 | } |
6390 | --mips_opts.noreorder; | |
6391 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); | |
6392 | break; | |
6393 | ||
6394 | case M_DMULOU_I: | |
6395 | dbl = 1; | |
6396 | case M_MULOU_I: | |
6397 | imm = 1; | |
6398 | goto do_mulou; | |
6399 | ||
6400 | case M_DMULOU: | |
6401 | dbl = 1; | |
6402 | case M_MULOU: | |
6403 | do_mulou: | |
6404 | mips_emit_delays (true); | |
6405 | ++mips_opts.noreorder; | |
6406 | mips_any_noreorder = 1; | |
6407 | if (imm) | |
6408 | load_register (&icnt, AT, &imm_expr, dbl); | |
6409 | macro_build ((char *) NULL, &icnt, NULL, | |
6410 | dbl ? "dmultu" : "multu", | |
6411 | "s,t", sreg, imm ? AT : treg); | |
6412 | macro_build ((char *) NULL, &icnt, NULL, "mfhi", "d", AT); | |
6413 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); | |
6414 | if (mips_trap) | |
6415 | macro_build ((char *) NULL, &icnt, NULL, "tne", "s,t", AT, 0); | |
6416 | else | |
6417 | { | |
6418 | expr1.X_add_number = 8; | |
6419 | macro_build ((char *) NULL, &icnt, &expr1, "beq", "s,t,p", AT, 0); | |
6420 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); | |
beae10d5 | 6421 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 6); |
252b5132 RH |
6422 | } |
6423 | --mips_opts.noreorder; | |
6424 | break; | |
6425 | ||
6426 | case M_ROL: | |
6427 | macro_build ((char *) NULL, &icnt, NULL, "subu", "d,v,t", AT, 0, treg); | |
6428 | macro_build ((char *) NULL, &icnt, NULL, "srlv", "d,t,s", AT, sreg, AT); | |
6429 | macro_build ((char *) NULL, &icnt, NULL, "sllv", "d,t,s", dreg, sreg, | |
6430 | treg); | |
6431 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT); | |
6432 | break; | |
6433 | ||
6434 | case M_ROL_I: | |
6435 | if (imm_expr.X_op != O_constant) | |
6436 | as_bad (_("rotate count too large")); | |
6437 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", AT, sreg, | |
6438 | (int) (imm_expr.X_add_number & 0x1f)); | |
6439 | macro_build ((char *) NULL, &icnt, NULL, "srl", "d,w,<", dreg, sreg, | |
6440 | (int) ((0 - imm_expr.X_add_number) & 0x1f)); | |
6441 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT); | |
6442 | break; | |
6443 | ||
6444 | case M_ROR: | |
6445 | macro_build ((char *) NULL, &icnt, NULL, "subu", "d,v,t", AT, 0, treg); | |
6446 | macro_build ((char *) NULL, &icnt, NULL, "sllv", "d,t,s", AT, sreg, AT); | |
6447 | macro_build ((char *) NULL, &icnt, NULL, "srlv", "d,t,s", dreg, sreg, | |
6448 | treg); | |
6449 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT); | |
6450 | break; | |
6451 | ||
6452 | case M_ROR_I: | |
6453 | if (imm_expr.X_op != O_constant) | |
6454 | as_bad (_("rotate count too large")); | |
6455 | macro_build ((char *) NULL, &icnt, NULL, "srl", "d,w,<", AT, sreg, | |
6456 | (int) (imm_expr.X_add_number & 0x1f)); | |
6457 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", dreg, sreg, | |
6458 | (int) ((0 - imm_expr.X_add_number) & 0x1f)); | |
6459 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT); | |
6460 | break; | |
6461 | ||
6462 | case M_S_DOB: | |
ec68c924 | 6463 | if (mips_arch == CPU_R4650) |
252b5132 RH |
6464 | { |
6465 | as_bad (_("opcode not supported on this processor")); | |
6466 | return; | |
6467 | } | |
e7af610e | 6468 | assert (mips_opts.isa == ISA_MIPS1); |
252b5132 RH |
6469 | /* Even on a big endian machine $fn comes before $fn+1. We have |
6470 | to adjust when storing to memory. */ | |
6471 | macro_build ((char *) NULL, &icnt, &offset_expr, "swc1", "T,o(b)", | |
6472 | target_big_endian ? treg + 1 : treg, | |
6473 | (int) BFD_RELOC_LO16, breg); | |
6474 | offset_expr.X_add_number += 4; | |
6475 | macro_build ((char *) NULL, &icnt, &offset_expr, "swc1", "T,o(b)", | |
6476 | target_big_endian ? treg : treg + 1, | |
6477 | (int) BFD_RELOC_LO16, breg); | |
6478 | return; | |
6479 | ||
6480 | case M_SEQ: | |
6481 | if (sreg == 0) | |
6482 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, | |
6483 | treg, (int) BFD_RELOC_LO16); | |
6484 | else if (treg == 0) | |
6485 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, | |
6486 | sreg, (int) BFD_RELOC_LO16); | |
6487 | else | |
6488 | { | |
6489 | macro_build ((char *) NULL, &icnt, NULL, "xor", "d,v,t", dreg, | |
6490 | sreg, treg); | |
6491 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, | |
6492 | dreg, (int) BFD_RELOC_LO16); | |
6493 | } | |
6494 | return; | |
6495 | ||
6496 | case M_SEQ_I: | |
6497 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
6498 | { | |
6499 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, | |
6500 | sreg, (int) BFD_RELOC_LO16); | |
6501 | return; | |
6502 | } | |
6503 | if (sreg == 0) | |
6504 | { | |
6505 | as_warn (_("Instruction %s: result is always false"), | |
6506 | ip->insn_mo->name); | |
ea1fb5dc | 6507 | move_register (&icnt, dreg, 0); |
252b5132 RH |
6508 | return; |
6509 | } | |
6510 | if (imm_expr.X_op == O_constant | |
6511 | && imm_expr.X_add_number >= 0 | |
6512 | && imm_expr.X_add_number < 0x10000) | |
6513 | { | |
6514 | macro_build ((char *) NULL, &icnt, &imm_expr, "xori", "t,r,i", dreg, | |
6515 | sreg, (int) BFD_RELOC_LO16); | |
6516 | used_at = 0; | |
6517 | } | |
6518 | else if (imm_expr.X_op == O_constant | |
6519 | && imm_expr.X_add_number > -0x8000 | |
6520 | && imm_expr.X_add_number < 0) | |
6521 | { | |
6522 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
6523 | macro_build ((char *) NULL, &icnt, &imm_expr, | |
ca4e0257 | 6524 | HAVE_32BIT_GPRS ? "addiu" : "daddiu", |
252b5132 RH |
6525 | "t,r,j", dreg, sreg, |
6526 | (int) BFD_RELOC_LO16); | |
6527 | used_at = 0; | |
6528 | } | |
6529 | else | |
6530 | { | |
6531 | load_register (&icnt, AT, &imm_expr, 0); | |
6532 | macro_build ((char *) NULL, &icnt, NULL, "xor", "d,v,t", dreg, | |
6533 | sreg, AT); | |
6534 | used_at = 1; | |
6535 | } | |
6536 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, dreg, | |
6537 | (int) BFD_RELOC_LO16); | |
6538 | if (used_at) | |
6539 | break; | |
6540 | return; | |
6541 | ||
6542 | case M_SGE: /* sreg >= treg <==> not (sreg < treg) */ | |
6543 | s = "slt"; | |
6544 | goto sge; | |
6545 | case M_SGEU: | |
6546 | s = "sltu"; | |
6547 | sge: | |
6548 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, sreg, treg); | |
6549 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, | |
6550 | (int) BFD_RELOC_LO16); | |
6551 | return; | |
6552 | ||
6553 | case M_SGE_I: /* sreg >= I <==> not (sreg < I) */ | |
6554 | case M_SGEU_I: | |
6555 | if (imm_expr.X_op == O_constant | |
6556 | && imm_expr.X_add_number >= -0x8000 | |
6557 | && imm_expr.X_add_number < 0x8000) | |
6558 | { | |
6559 | macro_build ((char *) NULL, &icnt, &imm_expr, | |
6560 | mask == M_SGE_I ? "slti" : "sltiu", | |
6561 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); | |
6562 | used_at = 0; | |
6563 | } | |
6564 | else | |
6565 | { | |
6566 | load_register (&icnt, AT, &imm_expr, 0); | |
6567 | macro_build ((char *) NULL, &icnt, NULL, | |
6568 | mask == M_SGE_I ? "slt" : "sltu", | |
6569 | "d,v,t", dreg, sreg, AT); | |
6570 | used_at = 1; | |
6571 | } | |
6572 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, | |
6573 | (int) BFD_RELOC_LO16); | |
6574 | if (used_at) | |
6575 | break; | |
6576 | return; | |
6577 | ||
6578 | case M_SGT: /* sreg > treg <==> treg < sreg */ | |
6579 | s = "slt"; | |
6580 | goto sgt; | |
6581 | case M_SGTU: | |
6582 | s = "sltu"; | |
6583 | sgt: | |
6584 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, treg, sreg); | |
6585 | return; | |
6586 | ||
6587 | case M_SGT_I: /* sreg > I <==> I < sreg */ | |
6588 | s = "slt"; | |
6589 | goto sgti; | |
6590 | case M_SGTU_I: | |
6591 | s = "sltu"; | |
6592 | sgti: | |
6593 | load_register (&icnt, AT, &imm_expr, 0); | |
6594 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, AT, sreg); | |
6595 | break; | |
6596 | ||
6597 | case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */ | |
6598 | s = "slt"; | |
6599 | goto sle; | |
6600 | case M_SLEU: | |
6601 | s = "sltu"; | |
6602 | sle: | |
6603 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, treg, sreg); | |
6604 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, | |
6605 | (int) BFD_RELOC_LO16); | |
6606 | return; | |
6607 | ||
6608 | case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */ | |
6609 | s = "slt"; | |
6610 | goto slei; | |
6611 | case M_SLEU_I: | |
6612 | s = "sltu"; | |
6613 | slei: | |
6614 | load_register (&icnt, AT, &imm_expr, 0); | |
6615 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, AT, sreg); | |
6616 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, | |
6617 | (int) BFD_RELOC_LO16); | |
6618 | break; | |
6619 | ||
6620 | case M_SLT_I: | |
6621 | if (imm_expr.X_op == O_constant | |
6622 | && imm_expr.X_add_number >= -0x8000 | |
6623 | && imm_expr.X_add_number < 0x8000) | |
6624 | { | |
6625 | macro_build ((char *) NULL, &icnt, &imm_expr, "slti", "t,r,j", | |
6626 | dreg, sreg, (int) BFD_RELOC_LO16); | |
6627 | return; | |
6628 | } | |
6629 | load_register (&icnt, AT, &imm_expr, 0); | |
6630 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", dreg, sreg, AT); | |
6631 | break; | |
6632 | ||
6633 | case M_SLTU_I: | |
6634 | if (imm_expr.X_op == O_constant | |
6635 | && imm_expr.X_add_number >= -0x8000 | |
6636 | && imm_expr.X_add_number < 0x8000) | |
6637 | { | |
6638 | macro_build ((char *) NULL, &icnt, &imm_expr, "sltiu", "t,r,j", | |
6639 | dreg, sreg, (int) BFD_RELOC_LO16); | |
6640 | return; | |
6641 | } | |
6642 | load_register (&icnt, AT, &imm_expr, 0); | |
6643 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, sreg, | |
6644 | AT); | |
6645 | break; | |
6646 | ||
6647 | case M_SNE: | |
6648 | if (sreg == 0) | |
6649 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, | |
6650 | treg); | |
6651 | else if (treg == 0) | |
6652 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, | |
6653 | sreg); | |
6654 | else | |
6655 | { | |
6656 | macro_build ((char *) NULL, &icnt, NULL, "xor", "d,v,t", dreg, | |
6657 | sreg, treg); | |
6658 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, | |
6659 | dreg); | |
6660 | } | |
6661 | return; | |
6662 | ||
6663 | case M_SNE_I: | |
6664 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
6665 | { | |
6666 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, | |
6667 | sreg); | |
6668 | return; | |
6669 | } | |
6670 | if (sreg == 0) | |
6671 | { | |
6672 | as_warn (_("Instruction %s: result is always true"), | |
6673 | ip->insn_mo->name); | |
6674 | macro_build ((char *) NULL, &icnt, &expr1, | |
ca4e0257 | 6675 | HAVE_32BIT_GPRS ? "addiu" : "daddiu", |
252b5132 RH |
6676 | "t,r,j", dreg, 0, (int) BFD_RELOC_LO16); |
6677 | return; | |
6678 | } | |
6679 | if (imm_expr.X_op == O_constant | |
6680 | && imm_expr.X_add_number >= 0 | |
6681 | && imm_expr.X_add_number < 0x10000) | |
6682 | { | |
6683 | macro_build ((char *) NULL, &icnt, &imm_expr, "xori", "t,r,i", | |
6684 | dreg, sreg, (int) BFD_RELOC_LO16); | |
6685 | used_at = 0; | |
6686 | } | |
6687 | else if (imm_expr.X_op == O_constant | |
6688 | && imm_expr.X_add_number > -0x8000 | |
6689 | && imm_expr.X_add_number < 0) | |
6690 | { | |
6691 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
6692 | macro_build ((char *) NULL, &icnt, &imm_expr, | |
ca4e0257 | 6693 | HAVE_32BIT_GPRS ? "addiu" : "daddiu", |
252b5132 RH |
6694 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); |
6695 | used_at = 0; | |
6696 | } | |
6697 | else | |
6698 | { | |
6699 | load_register (&icnt, AT, &imm_expr, 0); | |
6700 | macro_build ((char *) NULL, &icnt, NULL, "xor", "d,v,t", dreg, | |
6701 | sreg, AT); | |
6702 | used_at = 1; | |
6703 | } | |
6704 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, dreg); | |
6705 | if (used_at) | |
6706 | break; | |
6707 | return; | |
6708 | ||
6709 | case M_DSUB_I: | |
6710 | dbl = 1; | |
6711 | case M_SUB_I: | |
6712 | if (imm_expr.X_op == O_constant | |
6713 | && imm_expr.X_add_number > -0x8000 | |
6714 | && imm_expr.X_add_number <= 0x8000) | |
6715 | { | |
6716 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
6717 | macro_build ((char *) NULL, &icnt, &imm_expr, | |
6718 | dbl ? "daddi" : "addi", | |
6719 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); | |
6720 | return; | |
6721 | } | |
6722 | load_register (&icnt, AT, &imm_expr, dbl); | |
6723 | macro_build ((char *) NULL, &icnt, NULL, | |
9a41af64 | 6724 | dbl ? "dsub" : "sub", "d,v,t", dreg, sreg, AT); |
252b5132 RH |
6725 | break; |
6726 | ||
6727 | case M_DSUBU_I: | |
6728 | dbl = 1; | |
6729 | case M_SUBU_I: | |
6730 | if (imm_expr.X_op == O_constant | |
6731 | && imm_expr.X_add_number > -0x8000 | |
6732 | && imm_expr.X_add_number <= 0x8000) | |
6733 | { | |
6734 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
6735 | macro_build ((char *) NULL, &icnt, &imm_expr, | |
6736 | dbl ? "daddiu" : "addiu", | |
6737 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); | |
6738 | return; | |
6739 | } | |
6740 | load_register (&icnt, AT, &imm_expr, dbl); | |
6741 | macro_build ((char *) NULL, &icnt, NULL, | |
9a41af64 | 6742 | dbl ? "dsubu" : "subu", "d,v,t", dreg, sreg, AT); |
252b5132 RH |
6743 | break; |
6744 | ||
6745 | case M_TEQ_I: | |
6746 | s = "teq"; | |
6747 | goto trap; | |
6748 | case M_TGE_I: | |
6749 | s = "tge"; | |
6750 | goto trap; | |
6751 | case M_TGEU_I: | |
6752 | s = "tgeu"; | |
6753 | goto trap; | |
6754 | case M_TLT_I: | |
6755 | s = "tlt"; | |
6756 | goto trap; | |
6757 | case M_TLTU_I: | |
6758 | s = "tltu"; | |
6759 | goto trap; | |
6760 | case M_TNE_I: | |
6761 | s = "tne"; | |
6762 | trap: | |
6763 | load_register (&icnt, AT, &imm_expr, 0); | |
6764 | macro_build ((char *) NULL, &icnt, NULL, s, "s,t", sreg, AT); | |
6765 | break; | |
6766 | ||
252b5132 | 6767 | case M_TRUNCWS: |
43841e91 | 6768 | case M_TRUNCWD: |
e7af610e | 6769 | assert (mips_opts.isa == ISA_MIPS1); |
252b5132 RH |
6770 | sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */ |
6771 | dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */ | |
6772 | ||
6773 | /* | |
6774 | * Is the double cfc1 instruction a bug in the mips assembler; | |
6775 | * or is there a reason for it? | |
6776 | */ | |
6777 | mips_emit_delays (true); | |
6778 | ++mips_opts.noreorder; | |
6779 | mips_any_noreorder = 1; | |
6780 | macro_build ((char *) NULL, &icnt, NULL, "cfc1", "t,G", treg, 31); | |
6781 | macro_build ((char *) NULL, &icnt, NULL, "cfc1", "t,G", treg, 31); | |
6782 | macro_build ((char *) NULL, &icnt, NULL, "nop", ""); | |
6783 | expr1.X_add_number = 3; | |
6784 | macro_build ((char *) NULL, &icnt, &expr1, "ori", "t,r,i", AT, treg, | |
6785 | (int) BFD_RELOC_LO16); | |
6786 | expr1.X_add_number = 2; | |
6787 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", AT, AT, | |
6788 | (int) BFD_RELOC_LO16); | |
6789 | macro_build ((char *) NULL, &icnt, NULL, "ctc1", "t,G", AT, 31); | |
6790 | macro_build ((char *) NULL, &icnt, NULL, "nop", ""); | |
6791 | macro_build ((char *) NULL, &icnt, NULL, | |
6792 | mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S", dreg, sreg); | |
6793 | macro_build ((char *) NULL, &icnt, NULL, "ctc1", "t,G", treg, 31); | |
6794 | macro_build ((char *) NULL, &icnt, NULL, "nop", ""); | |
6795 | --mips_opts.noreorder; | |
6796 | break; | |
6797 | ||
6798 | case M_ULH: | |
6799 | s = "lb"; | |
6800 | goto ulh; | |
6801 | case M_ULHU: | |
6802 | s = "lbu"; | |
6803 | ulh: | |
6804 | if (offset_expr.X_add_number >= 0x7fff) | |
6805 | as_bad (_("operand overflow")); | |
6806 | /* avoid load delay */ | |
6807 | if (! target_big_endian) | |
6808 | offset_expr.X_add_number += 1; | |
6809 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, | |
6810 | (int) BFD_RELOC_LO16, breg); | |
6811 | if (! target_big_endian) | |
6812 | offset_expr.X_add_number -= 1; | |
6813 | else | |
6814 | offset_expr.X_add_number += 1; | |
6815 | macro_build ((char *) NULL, &icnt, &offset_expr, "lbu", "t,o(b)", AT, | |
6816 | (int) BFD_RELOC_LO16, breg); | |
6817 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", treg, treg, 8); | |
6818 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", treg, treg, AT); | |
6819 | break; | |
6820 | ||
6821 | case M_ULD: | |
6822 | s = "ldl"; | |
6823 | s2 = "ldr"; | |
6824 | off = 7; | |
6825 | goto ulw; | |
6826 | case M_ULW: | |
6827 | s = "lwl"; | |
6828 | s2 = "lwr"; | |
6829 | off = 3; | |
6830 | ulw: | |
6831 | if (offset_expr.X_add_number >= 0x8000 - off) | |
6832 | as_bad (_("operand overflow")); | |
6833 | if (! target_big_endian) | |
6834 | offset_expr.X_add_number += off; | |
6835 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, | |
6836 | (int) BFD_RELOC_LO16, breg); | |
6837 | if (! target_big_endian) | |
6838 | offset_expr.X_add_number -= off; | |
6839 | else | |
6840 | offset_expr.X_add_number += off; | |
6841 | macro_build ((char *) NULL, &icnt, &offset_expr, s2, "t,o(b)", treg, | |
6842 | (int) BFD_RELOC_LO16, breg); | |
6843 | return; | |
6844 | ||
6845 | case M_ULD_A: | |
6846 | s = "ldl"; | |
6847 | s2 = "ldr"; | |
6848 | off = 7; | |
6849 | goto ulwa; | |
6850 | case M_ULW_A: | |
6851 | s = "lwl"; | |
6852 | s2 = "lwr"; | |
6853 | off = 3; | |
6854 | ulwa: | |
d6bc6245 TS |
6855 | used_at = 1; |
6856 | load_address (&icnt, AT, &offset_expr, HAVE_64BIT_ADDRESSES, &used_at); | |
252b5132 RH |
6857 | if (breg != 0) |
6858 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 6859 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
6860 | "d,v,t", AT, AT, breg); |
6861 | if (! target_big_endian) | |
6862 | expr1.X_add_number = off; | |
6863 | else | |
6864 | expr1.X_add_number = 0; | |
6865 | macro_build ((char *) NULL, &icnt, &expr1, s, "t,o(b)", treg, | |
6866 | (int) BFD_RELOC_LO16, AT); | |
6867 | if (! target_big_endian) | |
6868 | expr1.X_add_number = 0; | |
6869 | else | |
6870 | expr1.X_add_number = off; | |
6871 | macro_build ((char *) NULL, &icnt, &expr1, s2, "t,o(b)", treg, | |
6872 | (int) BFD_RELOC_LO16, AT); | |
6873 | break; | |
6874 | ||
6875 | case M_ULH_A: | |
6876 | case M_ULHU_A: | |
d6bc6245 TS |
6877 | used_at = 1; |
6878 | load_address (&icnt, AT, &offset_expr, HAVE_64BIT_ADDRESSES, &used_at); | |
252b5132 RH |
6879 | if (breg != 0) |
6880 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 6881 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
6882 | "d,v,t", AT, AT, breg); |
6883 | if (target_big_endian) | |
6884 | expr1.X_add_number = 0; | |
6885 | macro_build ((char *) NULL, &icnt, &expr1, | |
6886 | mask == M_ULH_A ? "lb" : "lbu", "t,o(b)", treg, | |
6887 | (int) BFD_RELOC_LO16, AT); | |
6888 | if (target_big_endian) | |
6889 | expr1.X_add_number = 1; | |
6890 | else | |
6891 | expr1.X_add_number = 0; | |
6892 | macro_build ((char *) NULL, &icnt, &expr1, "lbu", "t,o(b)", AT, | |
6893 | (int) BFD_RELOC_LO16, AT); | |
6894 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", treg, | |
6895 | treg, 8); | |
6896 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", treg, | |
6897 | treg, AT); | |
6898 | break; | |
6899 | ||
6900 | case M_USH: | |
6901 | if (offset_expr.X_add_number >= 0x7fff) | |
6902 | as_bad (_("operand overflow")); | |
6903 | if (target_big_endian) | |
6904 | offset_expr.X_add_number += 1; | |
6905 | macro_build ((char *) NULL, &icnt, &offset_expr, "sb", "t,o(b)", treg, | |
6906 | (int) BFD_RELOC_LO16, breg); | |
6907 | macro_build ((char *) NULL, &icnt, NULL, "srl", "d,w,<", AT, treg, 8); | |
6908 | if (target_big_endian) | |
6909 | offset_expr.X_add_number -= 1; | |
6910 | else | |
6911 | offset_expr.X_add_number += 1; | |
6912 | macro_build ((char *) NULL, &icnt, &offset_expr, "sb", "t,o(b)", AT, | |
6913 | (int) BFD_RELOC_LO16, breg); | |
6914 | break; | |
6915 | ||
6916 | case M_USD: | |
6917 | s = "sdl"; | |
6918 | s2 = "sdr"; | |
6919 | off = 7; | |
6920 | goto usw; | |
6921 | case M_USW: | |
6922 | s = "swl"; | |
6923 | s2 = "swr"; | |
6924 | off = 3; | |
6925 | usw: | |
6926 | if (offset_expr.X_add_number >= 0x8000 - off) | |
6927 | as_bad (_("operand overflow")); | |
6928 | if (! target_big_endian) | |
6929 | offset_expr.X_add_number += off; | |
6930 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, | |
6931 | (int) BFD_RELOC_LO16, breg); | |
6932 | if (! target_big_endian) | |
6933 | offset_expr.X_add_number -= off; | |
6934 | else | |
6935 | offset_expr.X_add_number += off; | |
6936 | macro_build ((char *) NULL, &icnt, &offset_expr, s2, "t,o(b)", treg, | |
6937 | (int) BFD_RELOC_LO16, breg); | |
6938 | return; | |
6939 | ||
6940 | case M_USD_A: | |
6941 | s = "sdl"; | |
6942 | s2 = "sdr"; | |
6943 | off = 7; | |
6944 | goto uswa; | |
6945 | case M_USW_A: | |
6946 | s = "swl"; | |
6947 | s2 = "swr"; | |
6948 | off = 3; | |
6949 | uswa: | |
d6bc6245 TS |
6950 | used_at = 1; |
6951 | load_address (&icnt, AT, &offset_expr, HAVE_64BIT_ADDRESSES, &used_at); | |
252b5132 RH |
6952 | if (breg != 0) |
6953 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 6954 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
6955 | "d,v,t", AT, AT, breg); |
6956 | if (! target_big_endian) | |
6957 | expr1.X_add_number = off; | |
6958 | else | |
6959 | expr1.X_add_number = 0; | |
6960 | macro_build ((char *) NULL, &icnt, &expr1, s, "t,o(b)", treg, | |
6961 | (int) BFD_RELOC_LO16, AT); | |
6962 | if (! target_big_endian) | |
6963 | expr1.X_add_number = 0; | |
6964 | else | |
6965 | expr1.X_add_number = off; | |
6966 | macro_build ((char *) NULL, &icnt, &expr1, s2, "t,o(b)", treg, | |
6967 | (int) BFD_RELOC_LO16, AT); | |
6968 | break; | |
6969 | ||
6970 | case M_USH_A: | |
d6bc6245 TS |
6971 | used_at = 1; |
6972 | load_address (&icnt, AT, &offset_expr, HAVE_64BIT_ADDRESSES, &used_at); | |
252b5132 RH |
6973 | if (breg != 0) |
6974 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 6975 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
6976 | "d,v,t", AT, AT, breg); |
6977 | if (! target_big_endian) | |
6978 | expr1.X_add_number = 0; | |
6979 | macro_build ((char *) NULL, &icnt, &expr1, "sb", "t,o(b)", treg, | |
6980 | (int) BFD_RELOC_LO16, AT); | |
6981 | macro_build ((char *) NULL, &icnt, NULL, "srl", "d,w,<", treg, | |
6982 | treg, 8); | |
6983 | if (! target_big_endian) | |
6984 | expr1.X_add_number = 1; | |
6985 | else | |
6986 | expr1.X_add_number = 0; | |
6987 | macro_build ((char *) NULL, &icnt, &expr1, "sb", "t,o(b)", treg, | |
6988 | (int) BFD_RELOC_LO16, AT); | |
6989 | if (! target_big_endian) | |
6990 | expr1.X_add_number = 0; | |
6991 | else | |
6992 | expr1.X_add_number = 1; | |
6993 | macro_build ((char *) NULL, &icnt, &expr1, "lbu", "t,o(b)", AT, | |
6994 | (int) BFD_RELOC_LO16, AT); | |
6995 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", treg, | |
6996 | treg, 8); | |
6997 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", treg, | |
6998 | treg, AT); | |
6999 | break; | |
7000 | ||
7001 | default: | |
7002 | /* FIXME: Check if this is one of the itbl macros, since they | |
bdaaa2e1 | 7003 | are added dynamically. */ |
252b5132 RH |
7004 | as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name); |
7005 | break; | |
7006 | } | |
7007 | if (mips_opts.noat) | |
7008 | as_warn (_("Macro used $at after \".set noat\"")); | |
7009 | } | |
7010 | ||
7011 | /* Implement macros in mips16 mode. */ | |
7012 | ||
7013 | static void | |
7014 | mips16_macro (ip) | |
7015 | struct mips_cl_insn *ip; | |
7016 | { | |
7017 | int mask; | |
7018 | int xreg, yreg, zreg, tmp; | |
7019 | int icnt; | |
7020 | expressionS expr1; | |
7021 | int dbl; | |
7022 | const char *s, *s2, *s3; | |
7023 | ||
7024 | mask = ip->insn_mo->mask; | |
7025 | ||
7026 | xreg = (ip->insn_opcode >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX; | |
7027 | yreg = (ip->insn_opcode >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY; | |
7028 | zreg = (ip->insn_opcode >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ; | |
7029 | ||
7030 | icnt = 0; | |
7031 | ||
7032 | expr1.X_op = O_constant; | |
7033 | expr1.X_op_symbol = NULL; | |
7034 | expr1.X_add_symbol = NULL; | |
7035 | expr1.X_add_number = 1; | |
7036 | ||
7037 | dbl = 0; | |
7038 | ||
7039 | switch (mask) | |
7040 | { | |
7041 | default: | |
7042 | internalError (); | |
7043 | ||
7044 | case M_DDIV_3: | |
7045 | dbl = 1; | |
7046 | case M_DIV_3: | |
7047 | s = "mflo"; | |
7048 | goto do_div3; | |
7049 | case M_DREM_3: | |
7050 | dbl = 1; | |
7051 | case M_REM_3: | |
7052 | s = "mfhi"; | |
7053 | do_div3: | |
7054 | mips_emit_delays (true); | |
7055 | ++mips_opts.noreorder; | |
7056 | mips_any_noreorder = 1; | |
7057 | macro_build ((char *) NULL, &icnt, NULL, | |
7058 | dbl ? "ddiv" : "div", | |
7059 | "0,x,y", xreg, yreg); | |
7060 | expr1.X_add_number = 2; | |
7061 | macro_build ((char *) NULL, &icnt, &expr1, "bnez", "x,p", yreg); | |
beae10d5 | 7062 | macro_build ((char *) NULL, &icnt, NULL, "break", "6", 7); |
bdaaa2e1 | 7063 | |
252b5132 RH |
7064 | /* FIXME: The normal code checks for of -1 / -0x80000000 here, |
7065 | since that causes an overflow. We should do that as well, | |
7066 | but I don't see how to do the comparisons without a temporary | |
7067 | register. */ | |
7068 | --mips_opts.noreorder; | |
7069 | macro_build ((char *) NULL, &icnt, NULL, s, "x", zreg); | |
7070 | break; | |
7071 | ||
7072 | case M_DIVU_3: | |
7073 | s = "divu"; | |
7074 | s2 = "mflo"; | |
7075 | goto do_divu3; | |
7076 | case M_REMU_3: | |
7077 | s = "divu"; | |
7078 | s2 = "mfhi"; | |
7079 | goto do_divu3; | |
7080 | case M_DDIVU_3: | |
7081 | s = "ddivu"; | |
7082 | s2 = "mflo"; | |
7083 | goto do_divu3; | |
7084 | case M_DREMU_3: | |
7085 | s = "ddivu"; | |
7086 | s2 = "mfhi"; | |
7087 | do_divu3: | |
7088 | mips_emit_delays (true); | |
7089 | ++mips_opts.noreorder; | |
7090 | mips_any_noreorder = 1; | |
7091 | macro_build ((char *) NULL, &icnt, NULL, s, "0,x,y", xreg, yreg); | |
7092 | expr1.X_add_number = 2; | |
7093 | macro_build ((char *) NULL, &icnt, &expr1, "bnez", "x,p", yreg); | |
7094 | macro_build ((char *) NULL, &icnt, NULL, "break", "6", 7); | |
7095 | --mips_opts.noreorder; | |
7096 | macro_build ((char *) NULL, &icnt, NULL, s2, "x", zreg); | |
7097 | break; | |
7098 | ||
7099 | case M_DMUL: | |
7100 | dbl = 1; | |
7101 | case M_MUL: | |
7102 | macro_build ((char *) NULL, &icnt, NULL, | |
9a41af64 | 7103 | dbl ? "dmultu" : "multu", "x,y", xreg, yreg); |
252b5132 RH |
7104 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "x", zreg); |
7105 | return; | |
7106 | ||
7107 | case M_DSUBU_I: | |
7108 | dbl = 1; | |
7109 | goto do_subu; | |
7110 | case M_SUBU_I: | |
7111 | do_subu: | |
7112 | if (imm_expr.X_op != O_constant) | |
7113 | as_bad (_("Unsupported large constant")); | |
7114 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
7115 | macro_build ((char *) NULL, &icnt, &imm_expr, | |
9a41af64 | 7116 | dbl ? "daddiu" : "addiu", "y,x,4", yreg, xreg); |
252b5132 RH |
7117 | break; |
7118 | ||
7119 | case M_SUBU_I_2: | |
7120 | if (imm_expr.X_op != O_constant) | |
7121 | as_bad (_("Unsupported large constant")); | |
7122 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
7123 | macro_build ((char *) NULL, &icnt, &imm_expr, "addiu", | |
7124 | "x,k", xreg); | |
7125 | break; | |
7126 | ||
7127 | case M_DSUBU_I_2: | |
7128 | if (imm_expr.X_op != O_constant) | |
7129 | as_bad (_("Unsupported large constant")); | |
7130 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
7131 | macro_build ((char *) NULL, &icnt, &imm_expr, "daddiu", | |
7132 | "y,j", yreg); | |
7133 | break; | |
7134 | ||
7135 | case M_BEQ: | |
7136 | s = "cmp"; | |
7137 | s2 = "bteqz"; | |
7138 | goto do_branch; | |
7139 | case M_BNE: | |
7140 | s = "cmp"; | |
7141 | s2 = "btnez"; | |
7142 | goto do_branch; | |
7143 | case M_BLT: | |
7144 | s = "slt"; | |
7145 | s2 = "btnez"; | |
7146 | goto do_branch; | |
7147 | case M_BLTU: | |
7148 | s = "sltu"; | |
7149 | s2 = "btnez"; | |
7150 | goto do_branch; | |
7151 | case M_BLE: | |
7152 | s = "slt"; | |
7153 | s2 = "bteqz"; | |
7154 | goto do_reverse_branch; | |
7155 | case M_BLEU: | |
7156 | s = "sltu"; | |
7157 | s2 = "bteqz"; | |
7158 | goto do_reverse_branch; | |
7159 | case M_BGE: | |
7160 | s = "slt"; | |
7161 | s2 = "bteqz"; | |
7162 | goto do_branch; | |
7163 | case M_BGEU: | |
7164 | s = "sltu"; | |
7165 | s2 = "bteqz"; | |
7166 | goto do_branch; | |
7167 | case M_BGT: | |
7168 | s = "slt"; | |
7169 | s2 = "btnez"; | |
7170 | goto do_reverse_branch; | |
7171 | case M_BGTU: | |
7172 | s = "sltu"; | |
7173 | s2 = "btnez"; | |
7174 | ||
7175 | do_reverse_branch: | |
7176 | tmp = xreg; | |
7177 | xreg = yreg; | |
7178 | yreg = tmp; | |
7179 | ||
7180 | do_branch: | |
7181 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "x,y", | |
7182 | xreg, yreg); | |
7183 | macro_build ((char *) NULL, &icnt, &offset_expr, s2, "p"); | |
7184 | break; | |
7185 | ||
7186 | case M_BEQ_I: | |
7187 | s = "cmpi"; | |
7188 | s2 = "bteqz"; | |
7189 | s3 = "x,U"; | |
7190 | goto do_branch_i; | |
7191 | case M_BNE_I: | |
7192 | s = "cmpi"; | |
7193 | s2 = "btnez"; | |
7194 | s3 = "x,U"; | |
7195 | goto do_branch_i; | |
7196 | case M_BLT_I: | |
7197 | s = "slti"; | |
7198 | s2 = "btnez"; | |
7199 | s3 = "x,8"; | |
7200 | goto do_branch_i; | |
7201 | case M_BLTU_I: | |
7202 | s = "sltiu"; | |
7203 | s2 = "btnez"; | |
7204 | s3 = "x,8"; | |
7205 | goto do_branch_i; | |
7206 | case M_BLE_I: | |
7207 | s = "slti"; | |
7208 | s2 = "btnez"; | |
7209 | s3 = "x,8"; | |
7210 | goto do_addone_branch_i; | |
7211 | case M_BLEU_I: | |
7212 | s = "sltiu"; | |
7213 | s2 = "btnez"; | |
7214 | s3 = "x,8"; | |
7215 | goto do_addone_branch_i; | |
7216 | case M_BGE_I: | |
7217 | s = "slti"; | |
7218 | s2 = "bteqz"; | |
7219 | s3 = "x,8"; | |
7220 | goto do_branch_i; | |
7221 | case M_BGEU_I: | |
7222 | s = "sltiu"; | |
7223 | s2 = "bteqz"; | |
7224 | s3 = "x,8"; | |
7225 | goto do_branch_i; | |
7226 | case M_BGT_I: | |
7227 | s = "slti"; | |
7228 | s2 = "bteqz"; | |
7229 | s3 = "x,8"; | |
7230 | goto do_addone_branch_i; | |
7231 | case M_BGTU_I: | |
7232 | s = "sltiu"; | |
7233 | s2 = "bteqz"; | |
7234 | s3 = "x,8"; | |
7235 | ||
7236 | do_addone_branch_i: | |
7237 | if (imm_expr.X_op != O_constant) | |
7238 | as_bad (_("Unsupported large constant")); | |
7239 | ++imm_expr.X_add_number; | |
7240 | ||
7241 | do_branch_i: | |
7242 | macro_build ((char *) NULL, &icnt, &imm_expr, s, s3, xreg); | |
7243 | macro_build ((char *) NULL, &icnt, &offset_expr, s2, "p"); | |
7244 | break; | |
7245 | ||
7246 | case M_ABS: | |
7247 | expr1.X_add_number = 0; | |
7248 | macro_build ((char *) NULL, &icnt, &expr1, "slti", "x,8", yreg); | |
7249 | if (xreg != yreg) | |
ea1fb5dc | 7250 | move_register (&icnt, xreg, yreg); |
252b5132 RH |
7251 | expr1.X_add_number = 2; |
7252 | macro_build ((char *) NULL, &icnt, &expr1, "bteqz", "p"); | |
7253 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
7254 | "neg", "x,w", xreg, xreg); | |
7255 | } | |
7256 | } | |
7257 | ||
7258 | /* For consistency checking, verify that all bits are specified either | |
7259 | by the match/mask part of the instruction definition, or by the | |
7260 | operand list. */ | |
7261 | static int | |
7262 | validate_mips_insn (opc) | |
7263 | const struct mips_opcode *opc; | |
7264 | { | |
7265 | const char *p = opc->args; | |
7266 | char c; | |
7267 | unsigned long used_bits = opc->mask; | |
7268 | ||
7269 | if ((used_bits & opc->match) != opc->match) | |
7270 | { | |
7271 | as_bad (_("internal: bad mips opcode (mask error): %s %s"), | |
7272 | opc->name, opc->args); | |
7273 | return 0; | |
7274 | } | |
7275 | #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift))) | |
7276 | while (*p) | |
7277 | switch (c = *p++) | |
7278 | { | |
7279 | case ',': break; | |
7280 | case '(': break; | |
7281 | case ')': break; | |
7282 | case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; | |
7283 | case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; | |
7284 | case 'A': break; | |
4372b673 | 7285 | case 'B': USE_BITS (OP_MASK_CODE20, OP_SH_CODE20); break; |
252b5132 RH |
7286 | case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break; |
7287 | case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break; | |
7288 | case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
7289 | case 'F': break; | |
7290 | case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
156c2f8b | 7291 | case 'H': USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; |
252b5132 | 7292 | case 'I': break; |
e972090a | 7293 | case 'J': USE_BITS (OP_MASK_CODE19, OP_SH_CODE19); break; |
252b5132 RH |
7294 | case 'L': break; |
7295 | case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break; | |
7296 | case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break; | |
7297 | case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break; | |
7298 | case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
7299 | case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
7300 | case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
7301 | case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
7302 | case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break; | |
7303 | case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
7304 | case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break; | |
7305 | case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
7306 | case 'f': break; | |
7307 | case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break; | |
7308 | case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; | |
7309 | case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
7310 | case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break; | |
7311 | case 'l': break; | |
7312 | case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
7313 | case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
7314 | case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break; | |
7315 | case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
7316 | case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
7317 | case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
7318 | case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; | |
7319 | case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
7320 | case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
7321 | case 'x': break; | |
7322 | case 'z': break; | |
7323 | case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break; | |
4372b673 NC |
7324 | case 'U': USE_BITS (OP_MASK_RD, OP_SH_RD); |
7325 | USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
252b5132 RH |
7326 | default: |
7327 | as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"), | |
7328 | c, opc->name, opc->args); | |
7329 | return 0; | |
7330 | } | |
7331 | #undef USE_BITS | |
7332 | if (used_bits != 0xffffffff) | |
7333 | { | |
7334 | as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"), | |
7335 | ~used_bits & 0xffffffff, opc->name, opc->args); | |
7336 | return 0; | |
7337 | } | |
7338 | return 1; | |
7339 | } | |
7340 | ||
7341 | /* This routine assembles an instruction into its binary format. As a | |
7342 | side effect, it sets one of the global variables imm_reloc or | |
7343 | offset_reloc to the type of relocation to do if one of the operands | |
7344 | is an address expression. */ | |
7345 | ||
7346 | static void | |
7347 | mips_ip (str, ip) | |
7348 | char *str; | |
7349 | struct mips_cl_insn *ip; | |
7350 | { | |
7351 | char *s; | |
7352 | const char *args; | |
43841e91 | 7353 | char c = 0; |
252b5132 RH |
7354 | struct mips_opcode *insn; |
7355 | char *argsStart; | |
7356 | unsigned int regno; | |
7357 | unsigned int lastregno = 0; | |
7358 | char *s_reset; | |
7359 | char save_c = 0; | |
7360 | int full_opcode_match = 1; | |
7361 | ||
7362 | insn_error = NULL; | |
7363 | ||
7364 | /* If the instruction contains a '.', we first try to match an instruction | |
7365 | including the '.'. Then we try again without the '.'. */ | |
7366 | insn = NULL; | |
3882b010 | 7367 | for (s = str; *s != '\0' && !ISSPACE (*s); ++s) |
252b5132 RH |
7368 | continue; |
7369 | ||
7370 | /* If we stopped on whitespace, then replace the whitespace with null for | |
7371 | the call to hash_find. Save the character we replaced just in case we | |
7372 | have to re-parse the instruction. */ | |
3882b010 | 7373 | if (ISSPACE (*s)) |
252b5132 RH |
7374 | { |
7375 | save_c = *s; | |
7376 | *s++ = '\0'; | |
7377 | } | |
bdaaa2e1 | 7378 | |
252b5132 RH |
7379 | insn = (struct mips_opcode *) hash_find (op_hash, str); |
7380 | ||
7381 | /* If we didn't find the instruction in the opcode table, try again, but | |
7382 | this time with just the instruction up to, but not including the | |
7383 | first '.'. */ | |
7384 | if (insn == NULL) | |
7385 | { | |
bdaaa2e1 | 7386 | /* Restore the character we overwrite above (if any). */ |
252b5132 RH |
7387 | if (save_c) |
7388 | *(--s) = save_c; | |
7389 | ||
7390 | /* Scan up to the first '.' or whitespace. */ | |
3882b010 L |
7391 | for (s = str; |
7392 | *s != '\0' && *s != '.' && !ISSPACE (*s); | |
7393 | ++s) | |
252b5132 RH |
7394 | continue; |
7395 | ||
7396 | /* If we did not find a '.', then we can quit now. */ | |
7397 | if (*s != '.') | |
7398 | { | |
7399 | insn_error = "unrecognized opcode"; | |
7400 | return; | |
7401 | } | |
7402 | ||
7403 | /* Lookup the instruction in the hash table. */ | |
7404 | *s++ = '\0'; | |
7405 | if ((insn = (struct mips_opcode *) hash_find (op_hash, str)) == NULL) | |
7406 | { | |
7407 | insn_error = "unrecognized opcode"; | |
7408 | return; | |
7409 | } | |
7410 | ||
7411 | full_opcode_match = 0; | |
7412 | } | |
7413 | ||
7414 | argsStart = s; | |
7415 | for (;;) | |
7416 | { | |
252b5132 RH |
7417 | boolean ok; |
7418 | ||
7419 | assert (strcmp (insn->name, str) == 0); | |
7420 | ||
ea1fb5dc | 7421 | if (OPCODE_IS_MEMBER (insn, mips_opts.isa, mips_arch)) |
252b5132 | 7422 | ok = true; |
bdaaa2e1 | 7423 | else |
252b5132 | 7424 | ok = false; |
bdaaa2e1 | 7425 | |
252b5132 RH |
7426 | if (insn->pinfo != INSN_MACRO) |
7427 | { | |
ec68c924 | 7428 | if (mips_arch == CPU_R4650 && (insn->pinfo & FP_D) != 0) |
252b5132 RH |
7429 | ok = false; |
7430 | } | |
7431 | ||
7432 | if (! ok) | |
7433 | { | |
7434 | if (insn + 1 < &mips_opcodes[NUMOPCODES] | |
7435 | && strcmp (insn->name, insn[1].name) == 0) | |
7436 | { | |
7437 | ++insn; | |
7438 | continue; | |
7439 | } | |
252b5132 | 7440 | else |
beae10d5 | 7441 | { |
268f6bed L |
7442 | if (!insn_error) |
7443 | { | |
7444 | static char buf[100]; | |
7445 | sprintf (buf, | |
7446 | _("opcode not supported on this processor: %s (%s)"), | |
ec68c924 | 7447 | mips_cpu_to_str (mips_arch), |
268f6bed | 7448 | mips_isa_to_str (mips_opts.isa)); |
bdaaa2e1 | 7449 | |
268f6bed L |
7450 | insn_error = buf; |
7451 | } | |
7452 | if (save_c) | |
7453 | *(--s) = save_c; | |
2bd7f1f3 | 7454 | return; |
252b5132 | 7455 | } |
252b5132 RH |
7456 | } |
7457 | ||
7458 | ip->insn_mo = insn; | |
7459 | ip->insn_opcode = insn->match; | |
268f6bed | 7460 | insn_error = NULL; |
252b5132 RH |
7461 | for (args = insn->args;; ++args) |
7462 | { | |
ad8d3bb3 | 7463 | s += strspn (s, " \t"); |
252b5132 RH |
7464 | switch (*args) |
7465 | { | |
7466 | case '\0': /* end of args */ | |
7467 | if (*s == '\0') | |
7468 | return; | |
7469 | break; | |
7470 | ||
7471 | case ',': | |
7472 | if (*s++ == *args) | |
7473 | continue; | |
7474 | s--; | |
7475 | switch (*++args) | |
7476 | { | |
7477 | case 'r': | |
7478 | case 'v': | |
38487616 | 7479 | ip->insn_opcode |= lastregno << OP_SH_RS; |
252b5132 RH |
7480 | continue; |
7481 | ||
7482 | case 'w': | |
38487616 TS |
7483 | ip->insn_opcode |= lastregno << OP_SH_RT; |
7484 | continue; | |
7485 | ||
252b5132 | 7486 | case 'W': |
38487616 | 7487 | ip->insn_opcode |= lastregno << OP_SH_FT; |
252b5132 RH |
7488 | continue; |
7489 | ||
7490 | case 'V': | |
38487616 | 7491 | ip->insn_opcode |= lastregno << OP_SH_FS; |
252b5132 RH |
7492 | continue; |
7493 | } | |
7494 | break; | |
7495 | ||
7496 | case '(': | |
7497 | /* Handle optional base register. | |
7498 | Either the base register is omitted or | |
bdaaa2e1 | 7499 | we must have a left paren. */ |
252b5132 RH |
7500 | /* This is dependent on the next operand specifier |
7501 | is a base register specification. */ | |
7502 | assert (args[1] == 'b' || args[1] == '5' | |
7503 | || args[1] == '-' || args[1] == '4'); | |
7504 | if (*s == '\0') | |
7505 | return; | |
7506 | ||
7507 | case ')': /* these must match exactly */ | |
7508 | if (*s++ == *args) | |
7509 | continue; | |
7510 | break; | |
7511 | ||
7512 | case '<': /* must be at least one digit */ | |
7513 | /* | |
7514 | * According to the manual, if the shift amount is greater | |
b6ff326e KH |
7515 | * than 31 or less than 0, then the shift amount should be |
7516 | * mod 32. In reality the mips assembler issues an error. | |
252b5132 RH |
7517 | * We issue a warning and mask out all but the low 5 bits. |
7518 | */ | |
7519 | my_getExpression (&imm_expr, s); | |
7520 | check_absolute_expr (ip, &imm_expr); | |
7521 | if ((unsigned long) imm_expr.X_add_number > 31) | |
7522 | { | |
7523 | as_warn (_("Improper shift amount (%ld)"), | |
7524 | (long) imm_expr.X_add_number); | |
38487616 | 7525 | imm_expr.X_add_number &= OP_MASK_SHAMT; |
252b5132 | 7526 | } |
38487616 | 7527 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_SHAMT; |
252b5132 RH |
7528 | imm_expr.X_op = O_absent; |
7529 | s = expr_end; | |
7530 | continue; | |
7531 | ||
7532 | case '>': /* shift amount minus 32 */ | |
7533 | my_getExpression (&imm_expr, s); | |
7534 | check_absolute_expr (ip, &imm_expr); | |
7535 | if ((unsigned long) imm_expr.X_add_number < 32 | |
7536 | || (unsigned long) imm_expr.X_add_number > 63) | |
7537 | break; | |
38487616 | 7538 | ip->insn_opcode |= (imm_expr.X_add_number - 32) << OP_SH_SHAMT; |
252b5132 RH |
7539 | imm_expr.X_op = O_absent; |
7540 | s = expr_end; | |
7541 | continue; | |
7542 | ||
252b5132 RH |
7543 | case 'k': /* cache code */ |
7544 | case 'h': /* prefx code */ | |
7545 | my_getExpression (&imm_expr, s); | |
7546 | check_absolute_expr (ip, &imm_expr); | |
7547 | if ((unsigned long) imm_expr.X_add_number > 31) | |
7548 | { | |
7549 | as_warn (_("Invalid value for `%s' (%lu)"), | |
7550 | ip->insn_mo->name, | |
7551 | (unsigned long) imm_expr.X_add_number); | |
7552 | imm_expr.X_add_number &= 0x1f; | |
7553 | } | |
7554 | if (*args == 'k') | |
7555 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CACHE; | |
7556 | else | |
7557 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_PREFX; | |
7558 | imm_expr.X_op = O_absent; | |
7559 | s = expr_end; | |
7560 | continue; | |
7561 | ||
7562 | case 'c': /* break code */ | |
7563 | my_getExpression (&imm_expr, s); | |
7564 | check_absolute_expr (ip, &imm_expr); | |
7565 | if ((unsigned) imm_expr.X_add_number > 1023) | |
7566 | { | |
7567 | as_warn (_("Illegal break code (%ld)"), | |
7568 | (long) imm_expr.X_add_number); | |
38487616 | 7569 | imm_expr.X_add_number &= OP_MASK_CODE; |
252b5132 | 7570 | } |
38487616 | 7571 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE; |
252b5132 RH |
7572 | imm_expr.X_op = O_absent; |
7573 | s = expr_end; | |
7574 | continue; | |
7575 | ||
7576 | case 'q': /* lower break code */ | |
7577 | my_getExpression (&imm_expr, s); | |
7578 | check_absolute_expr (ip, &imm_expr); | |
7579 | if ((unsigned) imm_expr.X_add_number > 1023) | |
7580 | { | |
7581 | as_warn (_("Illegal lower break code (%ld)"), | |
7582 | (long) imm_expr.X_add_number); | |
38487616 | 7583 | imm_expr.X_add_number &= OP_MASK_CODE2; |
252b5132 | 7584 | } |
38487616 | 7585 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE2; |
252b5132 RH |
7586 | imm_expr.X_op = O_absent; |
7587 | s = expr_end; | |
7588 | continue; | |
7589 | ||
4372b673 | 7590 | case 'B': /* 20-bit syscall/break code. */ |
156c2f8b | 7591 | my_getExpression (&imm_expr, s); |
156c2f8b | 7592 | check_absolute_expr (ip, &imm_expr); |
38487616 | 7593 | if ((unsigned) imm_expr.X_add_number > OP_MASK_CODE20) |
4372b673 | 7594 | as_warn (_("Illegal 20-bit code (%ld)"), |
252b5132 | 7595 | (long) imm_expr.X_add_number); |
38487616 | 7596 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE20; |
252b5132 RH |
7597 | imm_expr.X_op = O_absent; |
7598 | s = expr_end; | |
7599 | continue; | |
7600 | ||
7601 | case 'C': /* Coprocessor code */ | |
beae10d5 | 7602 | my_getExpression (&imm_expr, s); |
252b5132 | 7603 | check_absolute_expr (ip, &imm_expr); |
beae10d5 | 7604 | if ((unsigned long) imm_expr.X_add_number >= (1<<25)) |
252b5132 | 7605 | { |
beae10d5 | 7606 | as_warn (_("Coproccesor code > 25 bits (%ld)"), |
252b5132 | 7607 | (long) imm_expr.X_add_number); |
beae10d5 | 7608 | imm_expr.X_add_number &= ((1<<25) - 1); |
252b5132 | 7609 | } |
beae10d5 KH |
7610 | ip->insn_opcode |= imm_expr.X_add_number; |
7611 | imm_expr.X_op = O_absent; | |
7612 | s = expr_end; | |
7613 | continue; | |
252b5132 | 7614 | |
4372b673 NC |
7615 | case 'J': /* 19-bit wait code. */ |
7616 | my_getExpression (&imm_expr, s); | |
7617 | check_absolute_expr (ip, &imm_expr); | |
38487616 | 7618 | if ((unsigned) imm_expr.X_add_number > OP_MASK_CODE19) |
4372b673 NC |
7619 | as_warn (_("Illegal 19-bit code (%ld)"), |
7620 | (long) imm_expr.X_add_number); | |
38487616 | 7621 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE19; |
4372b673 NC |
7622 | imm_expr.X_op = O_absent; |
7623 | s = expr_end; | |
7624 | continue; | |
7625 | ||
252b5132 | 7626 | case 'P': /* Performance register */ |
beae10d5 | 7627 | my_getExpression (&imm_expr, s); |
252b5132 | 7628 | check_absolute_expr (ip, &imm_expr); |
beae10d5 | 7629 | if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1) |
252b5132 | 7630 | { |
38487616 | 7631 | as_warn (_("Invalid performance register (%ld)"), |
252b5132 | 7632 | (long) imm_expr.X_add_number); |
38487616 | 7633 | imm_expr.X_add_number &= OP_MASK_PERFREG; |
252b5132 | 7634 | } |
38487616 | 7635 | ip->insn_opcode |= (imm_expr.X_add_number << OP_SH_PERFREG); |
beae10d5 KH |
7636 | imm_expr.X_op = O_absent; |
7637 | s = expr_end; | |
7638 | continue; | |
252b5132 RH |
7639 | |
7640 | case 'b': /* base register */ | |
7641 | case 'd': /* destination register */ | |
7642 | case 's': /* source register */ | |
7643 | case 't': /* target register */ | |
7644 | case 'r': /* both target and source */ | |
7645 | case 'v': /* both dest and source */ | |
7646 | case 'w': /* both dest and target */ | |
7647 | case 'E': /* coprocessor target register */ | |
7648 | case 'G': /* coprocessor destination register */ | |
7649 | case 'x': /* ignore register name */ | |
7650 | case 'z': /* must be zero register */ | |
4372b673 | 7651 | case 'U': /* destination register (clo/clz). */ |
252b5132 RH |
7652 | s_reset = s; |
7653 | if (s[0] == '$') | |
7654 | { | |
7655 | ||
3882b010 | 7656 | if (ISDIGIT (s[1])) |
252b5132 RH |
7657 | { |
7658 | ++s; | |
7659 | regno = 0; | |
7660 | do | |
7661 | { | |
7662 | regno *= 10; | |
7663 | regno += *s - '0'; | |
7664 | ++s; | |
7665 | } | |
3882b010 | 7666 | while (ISDIGIT (*s)); |
252b5132 RH |
7667 | if (regno > 31) |
7668 | as_bad (_("Invalid register number (%d)"), regno); | |
7669 | } | |
7670 | else if (*args == 'E' || *args == 'G') | |
7671 | goto notreg; | |
7672 | else | |
7673 | { | |
7674 | if (s[1] == 'f' && s[2] == 'p') | |
7675 | { | |
7676 | s += 3; | |
7677 | regno = FP; | |
7678 | } | |
7679 | else if (s[1] == 's' && s[2] == 'p') | |
7680 | { | |
7681 | s += 3; | |
7682 | regno = SP; | |
7683 | } | |
7684 | else if (s[1] == 'g' && s[2] == 'p') | |
7685 | { | |
7686 | s += 3; | |
7687 | regno = GP; | |
7688 | } | |
7689 | else if (s[1] == 'a' && s[2] == 't') | |
7690 | { | |
7691 | s += 3; | |
7692 | regno = AT; | |
7693 | } | |
7694 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '0') | |
7695 | { | |
7696 | s += 4; | |
7697 | regno = KT0; | |
7698 | } | |
7699 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '1') | |
7700 | { | |
7701 | s += 4; | |
7702 | regno = KT1; | |
7703 | } | |
7704 | else if (itbl_have_entries) | |
7705 | { | |
7706 | char *p, *n; | |
d7ba4a77 | 7707 | unsigned long r; |
252b5132 | 7708 | |
d7ba4a77 | 7709 | p = s + 1; /* advance past '$' */ |
252b5132 RH |
7710 | n = itbl_get_field (&p); /* n is name */ |
7711 | ||
d7ba4a77 ILT |
7712 | /* See if this is a register defined in an |
7713 | itbl entry. */ | |
7714 | if (itbl_get_reg_val (n, &r)) | |
252b5132 RH |
7715 | { |
7716 | /* Get_field advances to the start of | |
7717 | the next field, so we need to back | |
d7ba4a77 | 7718 | rack to the end of the last field. */ |
bdaaa2e1 | 7719 | if (p) |
252b5132 | 7720 | s = p - 1; |
bdaaa2e1 | 7721 | else |
d7ba4a77 | 7722 | s = strchr (s, '\0'); |
252b5132 RH |
7723 | regno = r; |
7724 | } | |
7725 | else | |
7726 | goto notreg; | |
beae10d5 | 7727 | } |
252b5132 RH |
7728 | else |
7729 | goto notreg; | |
7730 | } | |
7731 | if (regno == AT | |
7732 | && ! mips_opts.noat | |
7733 | && *args != 'E' | |
7734 | && *args != 'G') | |
7735 | as_warn (_("Used $at without \".set noat\"")); | |
7736 | c = *args; | |
7737 | if (*s == ' ') | |
7738 | s++; | |
7739 | if (args[1] != *s) | |
7740 | { | |
7741 | if (c == 'r' || c == 'v' || c == 'w') | |
7742 | { | |
7743 | regno = lastregno; | |
7744 | s = s_reset; | |
7745 | args++; | |
7746 | } | |
7747 | } | |
7748 | /* 'z' only matches $0. */ | |
7749 | if (c == 'z' && regno != 0) | |
7750 | break; | |
7751 | ||
bdaaa2e1 KH |
7752 | /* Now that we have assembled one operand, we use the args string |
7753 | * to figure out where it goes in the instruction. */ | |
252b5132 RH |
7754 | switch (c) |
7755 | { | |
7756 | case 'r': | |
7757 | case 's': | |
7758 | case 'v': | |
7759 | case 'b': | |
38487616 | 7760 | ip->insn_opcode |= regno << OP_SH_RS; |
252b5132 RH |
7761 | break; |
7762 | case 'd': | |
7763 | case 'G': | |
38487616 | 7764 | ip->insn_opcode |= regno << OP_SH_RD; |
252b5132 | 7765 | break; |
4372b673 | 7766 | case 'U': |
38487616 TS |
7767 | ip->insn_opcode |= regno << OP_SH_RD; |
7768 | ip->insn_opcode |= regno << OP_SH_RT; | |
4372b673 | 7769 | break; |
252b5132 RH |
7770 | case 'w': |
7771 | case 't': | |
7772 | case 'E': | |
38487616 | 7773 | ip->insn_opcode |= regno << OP_SH_RT; |
252b5132 RH |
7774 | break; |
7775 | case 'x': | |
7776 | /* This case exists because on the r3000 trunc | |
7777 | expands into a macro which requires a gp | |
7778 | register. On the r6000 or r4000 it is | |
7779 | assembled into a single instruction which | |
7780 | ignores the register. Thus the insn version | |
7781 | is MIPS_ISA2 and uses 'x', and the macro | |
7782 | version is MIPS_ISA1 and uses 't'. */ | |
7783 | break; | |
7784 | case 'z': | |
7785 | /* This case is for the div instruction, which | |
7786 | acts differently if the destination argument | |
7787 | is $0. This only matches $0, and is checked | |
7788 | outside the switch. */ | |
7789 | break; | |
7790 | case 'D': | |
7791 | /* Itbl operand; not yet implemented. FIXME ?? */ | |
7792 | break; | |
7793 | /* What about all other operands like 'i', which | |
7794 | can be specified in the opcode table? */ | |
7795 | } | |
7796 | lastregno = regno; | |
7797 | continue; | |
7798 | } | |
7799 | notreg: | |
7800 | switch (*args++) | |
7801 | { | |
7802 | case 'r': | |
7803 | case 'v': | |
38487616 | 7804 | ip->insn_opcode |= lastregno << OP_SH_RS; |
252b5132 RH |
7805 | continue; |
7806 | case 'w': | |
38487616 | 7807 | ip->insn_opcode |= lastregno << OP_SH_RT; |
252b5132 RH |
7808 | continue; |
7809 | } | |
7810 | break; | |
7811 | ||
7812 | case 'D': /* floating point destination register */ | |
7813 | case 'S': /* floating point source register */ | |
7814 | case 'T': /* floating point target register */ | |
7815 | case 'R': /* floating point source register */ | |
7816 | case 'V': | |
7817 | case 'W': | |
7818 | s_reset = s; | |
3882b010 L |
7819 | if (s[0] == '$' && s[1] == 'f' |
7820 | && ISDIGIT (s[2])) | |
252b5132 RH |
7821 | { |
7822 | s += 2; | |
7823 | regno = 0; | |
7824 | do | |
7825 | { | |
7826 | regno *= 10; | |
7827 | regno += *s - '0'; | |
7828 | ++s; | |
7829 | } | |
3882b010 | 7830 | while (ISDIGIT (*s)); |
252b5132 RH |
7831 | |
7832 | if (regno > 31) | |
7833 | as_bad (_("Invalid float register number (%d)"), regno); | |
7834 | ||
7835 | if ((regno & 1) != 0 | |
ca4e0257 | 7836 | && HAVE_32BIT_FPRS |
252b5132 RH |
7837 | && ! (strcmp (str, "mtc1") == 0 |
7838 | || strcmp (str, "mfc1") == 0 | |
7839 | || strcmp (str, "lwc1") == 0 | |
7840 | || strcmp (str, "swc1") == 0 | |
7841 | || strcmp (str, "l.s") == 0 | |
7842 | || strcmp (str, "s.s") == 0)) | |
7843 | as_warn (_("Float register should be even, was %d"), | |
7844 | regno); | |
7845 | ||
7846 | c = *args; | |
7847 | if (*s == ' ') | |
7848 | s++; | |
7849 | if (args[1] != *s) | |
7850 | { | |
7851 | if (c == 'V' || c == 'W') | |
7852 | { | |
7853 | regno = lastregno; | |
7854 | s = s_reset; | |
7855 | args++; | |
7856 | } | |
7857 | } | |
7858 | switch (c) | |
7859 | { | |
7860 | case 'D': | |
38487616 | 7861 | ip->insn_opcode |= regno << OP_SH_FD; |
252b5132 RH |
7862 | break; |
7863 | case 'V': | |
7864 | case 'S': | |
38487616 | 7865 | ip->insn_opcode |= regno << OP_SH_FS; |
252b5132 RH |
7866 | break; |
7867 | case 'W': | |
7868 | case 'T': | |
38487616 | 7869 | ip->insn_opcode |= regno << OP_SH_FT; |
252b5132 RH |
7870 | break; |
7871 | case 'R': | |
38487616 | 7872 | ip->insn_opcode |= regno << OP_SH_FR; |
252b5132 RH |
7873 | break; |
7874 | } | |
7875 | lastregno = regno; | |
7876 | continue; | |
7877 | } | |
7878 | ||
252b5132 RH |
7879 | switch (*args++) |
7880 | { | |
7881 | case 'V': | |
38487616 | 7882 | ip->insn_opcode |= lastregno << OP_SH_FS; |
252b5132 RH |
7883 | continue; |
7884 | case 'W': | |
38487616 | 7885 | ip->insn_opcode |= lastregno << OP_SH_FT; |
252b5132 RH |
7886 | continue; |
7887 | } | |
7888 | break; | |
7889 | ||
7890 | case 'I': | |
7891 | my_getExpression (&imm_expr, s); | |
7892 | if (imm_expr.X_op != O_big | |
7893 | && imm_expr.X_op != O_constant) | |
7894 | insn_error = _("absolute expression required"); | |
7895 | s = expr_end; | |
7896 | continue; | |
7897 | ||
7898 | case 'A': | |
7899 | my_getExpression (&offset_expr, s); | |
f6688943 | 7900 | *imm_reloc = BFD_RELOC_32; |
252b5132 RH |
7901 | s = expr_end; |
7902 | continue; | |
7903 | ||
7904 | case 'F': | |
7905 | case 'L': | |
7906 | case 'f': | |
7907 | case 'l': | |
7908 | { | |
7909 | int f64; | |
ca4e0257 | 7910 | int using_gprs; |
252b5132 RH |
7911 | char *save_in; |
7912 | char *err; | |
7913 | unsigned char temp[8]; | |
7914 | int len; | |
7915 | unsigned int length; | |
7916 | segT seg; | |
7917 | subsegT subseg; | |
7918 | char *p; | |
7919 | ||
7920 | /* These only appear as the last operand in an | |
7921 | instruction, and every instruction that accepts | |
7922 | them in any variant accepts them in all variants. | |
7923 | This means we don't have to worry about backing out | |
7924 | any changes if the instruction does not match. | |
7925 | ||
7926 | The difference between them is the size of the | |
7927 | floating point constant and where it goes. For 'F' | |
7928 | and 'L' the constant is 64 bits; for 'f' and 'l' it | |
7929 | is 32 bits. Where the constant is placed is based | |
7930 | on how the MIPS assembler does things: | |
7931 | F -- .rdata | |
7932 | L -- .lit8 | |
7933 | f -- immediate value | |
7934 | l -- .lit4 | |
7935 | ||
7936 | The .lit4 and .lit8 sections are only used if | |
7937 | permitted by the -G argument. | |
7938 | ||
7939 | When generating embedded PIC code, we use the | |
7940 | .lit8 section but not the .lit4 section (we can do | |
7941 | .lit4 inline easily; we need to put .lit8 | |
7942 | somewhere in the data segment, and using .lit8 | |
7943 | permits the linker to eventually combine identical | |
ca4e0257 RS |
7944 | .lit8 entries). |
7945 | ||
7946 | The code below needs to know whether the target register | |
7947 | is 32 or 64 bits wide. It relies on the fact 'f' and | |
7948 | 'F' are used with GPR-based instructions and 'l' and | |
7949 | 'L' are used with FPR-based instructions. */ | |
252b5132 RH |
7950 | |
7951 | f64 = *args == 'F' || *args == 'L'; | |
ca4e0257 | 7952 | using_gprs = *args == 'F' || *args == 'f'; |
252b5132 RH |
7953 | |
7954 | save_in = input_line_pointer; | |
7955 | input_line_pointer = s; | |
7956 | err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len); | |
7957 | length = len; | |
7958 | s = input_line_pointer; | |
7959 | input_line_pointer = save_in; | |
7960 | if (err != NULL && *err != '\0') | |
7961 | { | |
7962 | as_bad (_("Bad floating point constant: %s"), err); | |
7963 | memset (temp, '\0', sizeof temp); | |
7964 | length = f64 ? 8 : 4; | |
7965 | } | |
7966 | ||
156c2f8b | 7967 | assert (length == (unsigned) (f64 ? 8 : 4)); |
252b5132 RH |
7968 | |
7969 | if (*args == 'f' | |
7970 | || (*args == 'l' | |
7971 | && (! USE_GLOBAL_POINTER_OPT | |
7972 | || mips_pic == EMBEDDED_PIC | |
7973 | || g_switch_value < 4 | |
7974 | || (temp[0] == 0 && temp[1] == 0) | |
7975 | || (temp[2] == 0 && temp[3] == 0)))) | |
7976 | { | |
7977 | imm_expr.X_op = O_constant; | |
7978 | if (! target_big_endian) | |
7979 | imm_expr.X_add_number = bfd_getl32 (temp); | |
7980 | else | |
7981 | imm_expr.X_add_number = bfd_getb32 (temp); | |
7982 | } | |
7983 | else if (length > 4 | |
119d663a | 7984 | && ! mips_disable_float_construction |
ca4e0257 RS |
7985 | /* Constants can only be constructed in GPRs and |
7986 | copied to FPRs if the GPRs are at least as wide | |
7987 | as the FPRs. Force the constant into memory if | |
7988 | we are using 64-bit FPRs but the GPRs are only | |
7989 | 32 bits wide. */ | |
7990 | && (using_gprs | |
7991 | || ! (HAVE_64BIT_FPRS && HAVE_32BIT_GPRS)) | |
252b5132 RH |
7992 | && ((temp[0] == 0 && temp[1] == 0) |
7993 | || (temp[2] == 0 && temp[3] == 0)) | |
7994 | && ((temp[4] == 0 && temp[5] == 0) | |
7995 | || (temp[6] == 0 && temp[7] == 0))) | |
7996 | { | |
ca4e0257 RS |
7997 | /* The value is simple enough to load with a couple of |
7998 | instructions. If using 32-bit registers, set | |
7999 | imm_expr to the high order 32 bits and offset_expr to | |
8000 | the low order 32 bits. Otherwise, set imm_expr to | |
8001 | the entire 64 bit constant. */ | |
8002 | if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS) | |
252b5132 RH |
8003 | { |
8004 | imm_expr.X_op = O_constant; | |
8005 | offset_expr.X_op = O_constant; | |
8006 | if (! target_big_endian) | |
8007 | { | |
8008 | imm_expr.X_add_number = bfd_getl32 (temp + 4); | |
8009 | offset_expr.X_add_number = bfd_getl32 (temp); | |
8010 | } | |
8011 | else | |
8012 | { | |
8013 | imm_expr.X_add_number = bfd_getb32 (temp); | |
8014 | offset_expr.X_add_number = bfd_getb32 (temp + 4); | |
8015 | } | |
8016 | if (offset_expr.X_add_number == 0) | |
8017 | offset_expr.X_op = O_absent; | |
8018 | } | |
8019 | else if (sizeof (imm_expr.X_add_number) > 4) | |
8020 | { | |
8021 | imm_expr.X_op = O_constant; | |
8022 | if (! target_big_endian) | |
8023 | imm_expr.X_add_number = bfd_getl64 (temp); | |
8024 | else | |
8025 | imm_expr.X_add_number = bfd_getb64 (temp); | |
8026 | } | |
8027 | else | |
8028 | { | |
8029 | imm_expr.X_op = O_big; | |
8030 | imm_expr.X_add_number = 4; | |
8031 | if (! target_big_endian) | |
8032 | { | |
8033 | generic_bignum[0] = bfd_getl16 (temp); | |
8034 | generic_bignum[1] = bfd_getl16 (temp + 2); | |
8035 | generic_bignum[2] = bfd_getl16 (temp + 4); | |
8036 | generic_bignum[3] = bfd_getl16 (temp + 6); | |
8037 | } | |
8038 | else | |
8039 | { | |
8040 | generic_bignum[0] = bfd_getb16 (temp + 6); | |
8041 | generic_bignum[1] = bfd_getb16 (temp + 4); | |
8042 | generic_bignum[2] = bfd_getb16 (temp + 2); | |
8043 | generic_bignum[3] = bfd_getb16 (temp); | |
8044 | } | |
8045 | } | |
8046 | } | |
8047 | else | |
8048 | { | |
8049 | const char *newname; | |
8050 | segT new_seg; | |
8051 | ||
8052 | /* Switch to the right section. */ | |
8053 | seg = now_seg; | |
8054 | subseg = now_subseg; | |
8055 | switch (*args) | |
8056 | { | |
8057 | default: /* unused default case avoids warnings. */ | |
8058 | case 'L': | |
8059 | newname = RDATA_SECTION_NAME; | |
bb2d6cd7 GK |
8060 | if ((USE_GLOBAL_POINTER_OPT && g_switch_value >= 8) |
8061 | || mips_pic == EMBEDDED_PIC) | |
252b5132 RH |
8062 | newname = ".lit8"; |
8063 | break; | |
8064 | case 'F': | |
bb2d6cd7 GK |
8065 | if (mips_pic == EMBEDDED_PIC) |
8066 | newname = ".lit8"; | |
8067 | else | |
8068 | newname = RDATA_SECTION_NAME; | |
252b5132 RH |
8069 | break; |
8070 | case 'l': | |
8071 | assert (!USE_GLOBAL_POINTER_OPT | |
8072 | || g_switch_value >= 4); | |
8073 | newname = ".lit4"; | |
8074 | break; | |
8075 | } | |
8076 | new_seg = subseg_new (newname, (subsegT) 0); | |
8077 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
8078 | bfd_set_section_flags (stdoutput, new_seg, | |
8079 | (SEC_ALLOC | |
8080 | | SEC_LOAD | |
8081 | | SEC_READONLY | |
8082 | | SEC_DATA)); | |
8083 | frag_align (*args == 'l' ? 2 : 3, 0, 0); | |
8084 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour | |
8085 | && strcmp (TARGET_OS, "elf") != 0) | |
8086 | record_alignment (new_seg, 4); | |
8087 | else | |
8088 | record_alignment (new_seg, *args == 'l' ? 2 : 3); | |
8089 | if (seg == now_seg) | |
8090 | as_bad (_("Can't use floating point insn in this section")); | |
8091 | ||
8092 | /* Set the argument to the current address in the | |
8093 | section. */ | |
8094 | offset_expr.X_op = O_symbol; | |
8095 | offset_expr.X_add_symbol = | |
8096 | symbol_new ("L0\001", now_seg, | |
8097 | (valueT) frag_now_fix (), frag_now); | |
8098 | offset_expr.X_add_number = 0; | |
8099 | ||
8100 | /* Put the floating point number into the section. */ | |
8101 | p = frag_more ((int) length); | |
8102 | memcpy (p, temp, length); | |
8103 | ||
8104 | /* Switch back to the original section. */ | |
8105 | subseg_set (seg, subseg); | |
8106 | } | |
8107 | } | |
8108 | continue; | |
8109 | ||
8110 | case 'i': /* 16 bit unsigned immediate */ | |
8111 | case 'j': /* 16 bit signed immediate */ | |
f6688943 | 8112 | *imm_reloc = BFD_RELOC_LO16; |
252b5132 | 8113 | c = my_getSmallExpression (&imm_expr, s); |
fb1b3232 | 8114 | if (c != S_EX_NONE) |
252b5132 | 8115 | { |
fb1b3232 | 8116 | if (c != S_EX_LO) |
252b5132 RH |
8117 | { |
8118 | if (imm_expr.X_op == O_constant) | |
8119 | imm_expr.X_add_number = | |
8120 | (imm_expr.X_add_number >> 16) & 0xffff; | |
ad8d3bb3 | 8121 | #ifdef OBJ_ELF |
fb1b3232 | 8122 | else if (c == S_EX_HIGHEST) |
f6688943 | 8123 | *imm_reloc = BFD_RELOC_MIPS_HIGHEST; |
fb1b3232 | 8124 | else if (c == S_EX_HIGHER) |
f6688943 | 8125 | *imm_reloc = BFD_RELOC_MIPS_HIGHER; |
ad8d3bb3 TS |
8126 | else if (c == S_EX_GP_REL) |
8127 | { | |
8128 | /* This occurs in NewABI only. */ | |
8129 | c = my_getSmallExpression (&imm_expr, s); | |
8130 | if (c != S_EX_NEG) | |
8131 | as_bad (_("bad composition of relocations")); | |
8132 | else | |
8133 | { | |
8134 | c = my_getSmallExpression (&imm_expr, s); | |
8135 | if (c != S_EX_LO) | |
8136 | as_bad (_("bad composition of relocations")); | |
8137 | else | |
8138 | { | |
8139 | imm_reloc[0] = BFD_RELOC_GPREL16; | |
8140 | imm_reloc[1] = BFD_RELOC_MIPS_SUB; | |
8141 | imm_reloc[2] = BFD_RELOC_LO16; | |
8142 | } | |
8143 | } | |
8144 | } | |
8145 | #endif | |
fb1b3232 | 8146 | else if (c == S_EX_HI) |
252b5132 | 8147 | { |
f6688943 | 8148 | *imm_reloc = BFD_RELOC_HI16_S; |
252b5132 RH |
8149 | imm_unmatched_hi = true; |
8150 | } | |
8151 | else | |
f6688943 | 8152 | *imm_reloc = BFD_RELOC_HI16; |
252b5132 RH |
8153 | } |
8154 | else if (imm_expr.X_op == O_constant) | |
8155 | imm_expr.X_add_number &= 0xffff; | |
8156 | } | |
8157 | if (*args == 'i') | |
8158 | { | |
fb1b3232 | 8159 | if ((c == S_EX_NONE && imm_expr.X_op != O_constant) |
252b5132 | 8160 | || ((imm_expr.X_add_number < 0 |
beae10d5 KH |
8161 | || imm_expr.X_add_number >= 0x10000) |
8162 | && imm_expr.X_op == O_constant)) | |
252b5132 RH |
8163 | { |
8164 | if (insn + 1 < &mips_opcodes[NUMOPCODES] && | |
8165 | !strcmp (insn->name, insn[1].name)) | |
8166 | break; | |
2ae7e77b AH |
8167 | if (imm_expr.X_op == O_constant |
8168 | || imm_expr.X_op == O_big) | |
252b5132 RH |
8169 | as_bad (_("16 bit expression not in range 0..65535")); |
8170 | } | |
8171 | } | |
8172 | else | |
8173 | { | |
8174 | int more; | |
8175 | offsetT max; | |
8176 | ||
8177 | /* The upper bound should be 0x8000, but | |
8178 | unfortunately the MIPS assembler accepts numbers | |
8179 | from 0x8000 to 0xffff and sign extends them, and | |
8180 | we want to be compatible. We only permit this | |
8181 | extended range for an instruction which does not | |
8182 | provide any further alternates, since those | |
8183 | alternates may handle other cases. People should | |
8184 | use the numbers they mean, rather than relying on | |
8185 | a mysterious sign extension. */ | |
8186 | more = (insn + 1 < &mips_opcodes[NUMOPCODES] && | |
8187 | strcmp (insn->name, insn[1].name) == 0); | |
8188 | if (more) | |
8189 | max = 0x8000; | |
8190 | else | |
8191 | max = 0x10000; | |
fb1b3232 | 8192 | if ((c == S_EX_NONE && imm_expr.X_op != O_constant) |
252b5132 | 8193 | || ((imm_expr.X_add_number < -0x8000 |
beae10d5 KH |
8194 | || imm_expr.X_add_number >= max) |
8195 | && imm_expr.X_op == O_constant) | |
252b5132 RH |
8196 | || (more |
8197 | && imm_expr.X_add_number < 0 | |
ca4e0257 | 8198 | && HAVE_64BIT_GPRS |
252b5132 RH |
8199 | && imm_expr.X_unsigned |
8200 | && sizeof (imm_expr.X_add_number) <= 4)) | |
8201 | { | |
8202 | if (more) | |
8203 | break; | |
2ae7e77b AH |
8204 | if (imm_expr.X_op == O_constant |
8205 | || imm_expr.X_op == O_big) | |
252b5132 RH |
8206 | as_bad (_("16 bit expression not in range -32768..32767")); |
8207 | } | |
8208 | } | |
8209 | s = expr_end; | |
8210 | continue; | |
8211 | ||
8212 | case 'o': /* 16 bit offset */ | |
8213 | c = my_getSmallExpression (&offset_expr, s); | |
8214 | ||
8215 | /* If this value won't fit into a 16 bit offset, then go | |
8216 | find a macro that will generate the 32 bit offset | |
8217 | code pattern. As a special hack, we accept the | |
8218 | difference of two local symbols as a constant. This | |
8219 | is required to suppose embedded PIC switches, which | |
8220 | use an instruction which looks like | |
8221 | lw $4,$L12-$LS12($4) | |
8222 | The problem with handling this in a more general | |
8223 | fashion is that the macro function doesn't expect to | |
8224 | see anything which can be handled in a single | |
8225 | constant instruction. */ | |
fb1b3232 | 8226 | if (c == S_EX_NONE |
252b5132 RH |
8227 | && (offset_expr.X_op != O_constant |
8228 | || offset_expr.X_add_number >= 0x8000 | |
8229 | || offset_expr.X_add_number < -0x8000) | |
8230 | && (mips_pic != EMBEDDED_PIC | |
8231 | || offset_expr.X_op != O_subtract | |
3dacdf2e NC |
8232 | || (S_GET_SEGMENT (offset_expr.X_add_symbol) |
8233 | != S_GET_SEGMENT (offset_expr.X_op_symbol)))) | |
252b5132 RH |
8234 | break; |
8235 | ||
fb1b3232 | 8236 | if (c == S_EX_HI) |
252b5132 RH |
8237 | { |
8238 | if (offset_expr.X_op != O_constant) | |
8239 | break; | |
8240 | offset_expr.X_add_number = | |
8241 | (offset_expr.X_add_number >> 16) & 0xffff; | |
8242 | } | |
f6688943 | 8243 | *offset_reloc = BFD_RELOC_LO16; |
252b5132 RH |
8244 | s = expr_end; |
8245 | continue; | |
8246 | ||
8247 | case 'p': /* pc relative offset */ | |
cb56d3d3 | 8248 | if (mips_pic == EMBEDDED_PIC) |
f6688943 | 8249 | *offset_reloc = BFD_RELOC_16_PCREL_S2; |
cb56d3d3 | 8250 | else |
f6688943 | 8251 | *offset_reloc = BFD_RELOC_16_PCREL; |
252b5132 RH |
8252 | my_getExpression (&offset_expr, s); |
8253 | s = expr_end; | |
8254 | continue; | |
8255 | ||
8256 | case 'u': /* upper 16 bits */ | |
8257 | c = my_getSmallExpression (&imm_expr, s); | |
f6688943 | 8258 | *imm_reloc = BFD_RELOC_LO16; |
e7d556df | 8259 | if (c != S_EX_NONE) |
252b5132 | 8260 | { |
fb1b3232 | 8261 | if (c != S_EX_LO) |
252b5132 RH |
8262 | { |
8263 | if (imm_expr.X_op == O_constant) | |
8264 | imm_expr.X_add_number = | |
8265 | (imm_expr.X_add_number >> 16) & 0xffff; | |
ad8d3bb3 | 8266 | #ifdef OBJ_ELF |
fb1b3232 | 8267 | else if (c == S_EX_HIGHEST) |
f6688943 | 8268 | *imm_reloc = BFD_RELOC_MIPS_HIGHEST; |
fb1b3232 | 8269 | else if (c == S_EX_HI) |
252b5132 | 8270 | { |
f6688943 | 8271 | *imm_reloc = BFD_RELOC_HI16_S; |
252b5132 RH |
8272 | imm_unmatched_hi = true; |
8273 | } | |
ad8d3bb3 TS |
8274 | else if (c == S_EX_GP_REL) |
8275 | { | |
8276 | /* This occurs in NewABI only. */ | |
8277 | c = my_getSmallExpression (&imm_expr, s); | |
8278 | if (c != S_EX_NEG) | |
8279 | as_bad (_("bad composition of relocations")); | |
8280 | else | |
8281 | { | |
8282 | c = my_getSmallExpression (&imm_expr, s); | |
8283 | if (c != S_EX_HI) | |
8284 | as_bad (_("bad composition of relocations")); | |
8285 | else | |
8286 | { | |
8287 | imm_reloc[0] = BFD_RELOC_GPREL16; | |
8288 | imm_reloc[1] = BFD_RELOC_MIPS_SUB; | |
8289 | imm_reloc[2] = BFD_RELOC_HI16_S; | |
8290 | } | |
8291 | } | |
8292 | } | |
8293 | #endif | |
252b5132 | 8294 | else |
f6688943 | 8295 | *imm_reloc = BFD_RELOC_HI16; |
252b5132 RH |
8296 | } |
8297 | else if (imm_expr.X_op == O_constant) | |
8298 | imm_expr.X_add_number &= 0xffff; | |
8299 | } | |
8300 | if (imm_expr.X_op == O_constant | |
8301 | && (imm_expr.X_add_number < 0 | |
8302 | || imm_expr.X_add_number >= 0x10000)) | |
8303 | as_bad (_("lui expression not in range 0..65535")); | |
8304 | s = expr_end; | |
8305 | continue; | |
8306 | ||
8307 | case 'a': /* 26 bit address */ | |
8308 | my_getExpression (&offset_expr, s); | |
8309 | s = expr_end; | |
f6688943 | 8310 | *offset_reloc = BFD_RELOC_MIPS_JMP; |
252b5132 RH |
8311 | continue; |
8312 | ||
8313 | case 'N': /* 3 bit branch condition code */ | |
8314 | case 'M': /* 3 bit compare condition code */ | |
8315 | if (strncmp (s, "$fcc", 4) != 0) | |
8316 | break; | |
8317 | s += 4; | |
8318 | regno = 0; | |
8319 | do | |
8320 | { | |
8321 | regno *= 10; | |
8322 | regno += *s - '0'; | |
8323 | ++s; | |
8324 | } | |
3882b010 | 8325 | while (ISDIGIT (*s)); |
252b5132 RH |
8326 | if (regno > 7) |
8327 | as_bad (_("invalid condition code register $fcc%d"), regno); | |
8328 | if (*args == 'N') | |
8329 | ip->insn_opcode |= regno << OP_SH_BCC; | |
8330 | else | |
8331 | ip->insn_opcode |= regno << OP_SH_CCC; | |
beae10d5 | 8332 | continue; |
252b5132 | 8333 | |
156c2f8b NC |
8334 | case 'H': |
8335 | if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X')) | |
8336 | s += 2; | |
3882b010 | 8337 | if (ISDIGIT (*s)) |
156c2f8b NC |
8338 | { |
8339 | c = 0; | |
8340 | do | |
8341 | { | |
8342 | c *= 10; | |
8343 | c += *s - '0'; | |
8344 | ++s; | |
8345 | } | |
3882b010 | 8346 | while (ISDIGIT (*s)); |
156c2f8b NC |
8347 | } |
8348 | else | |
8349 | c = 8; /* Invalid sel value. */ | |
8350 | ||
8351 | if (c > 7) | |
8352 | as_bad (_("invalid coprocessor sub-selection value (0-7)")); | |
8353 | ip->insn_opcode |= c; | |
8354 | continue; | |
8355 | ||
252b5132 RH |
8356 | default: |
8357 | as_bad (_("bad char = '%c'\n"), *args); | |
8358 | internalError (); | |
8359 | } | |
8360 | break; | |
8361 | } | |
8362 | /* Args don't match. */ | |
8363 | if (insn + 1 < &mips_opcodes[NUMOPCODES] && | |
8364 | !strcmp (insn->name, insn[1].name)) | |
8365 | { | |
8366 | ++insn; | |
8367 | s = argsStart; | |
268f6bed | 8368 | insn_error = _("illegal operands"); |
252b5132 RH |
8369 | continue; |
8370 | } | |
268f6bed L |
8371 | if (save_c) |
8372 | *(--s) = save_c; | |
252b5132 RH |
8373 | insn_error = _("illegal operands"); |
8374 | return; | |
8375 | } | |
8376 | } | |
8377 | ||
8378 | /* This routine assembles an instruction into its binary format when | |
8379 | assembling for the mips16. As a side effect, it sets one of the | |
8380 | global variables imm_reloc or offset_reloc to the type of | |
8381 | relocation to do if one of the operands is an address expression. | |
8382 | It also sets mips16_small and mips16_ext if the user explicitly | |
8383 | requested a small or extended instruction. */ | |
8384 | ||
8385 | static void | |
8386 | mips16_ip (str, ip) | |
8387 | char *str; | |
8388 | struct mips_cl_insn *ip; | |
8389 | { | |
8390 | char *s; | |
8391 | const char *args; | |
8392 | struct mips_opcode *insn; | |
8393 | char *argsstart; | |
8394 | unsigned int regno; | |
8395 | unsigned int lastregno = 0; | |
8396 | char *s_reset; | |
8397 | ||
8398 | insn_error = NULL; | |
8399 | ||
8400 | mips16_small = false; | |
8401 | mips16_ext = false; | |
8402 | ||
3882b010 | 8403 | for (s = str; ISLOWER (*s); ++s) |
252b5132 RH |
8404 | ; |
8405 | switch (*s) | |
8406 | { | |
8407 | case '\0': | |
8408 | break; | |
8409 | ||
8410 | case ' ': | |
8411 | *s++ = '\0'; | |
8412 | break; | |
8413 | ||
8414 | case '.': | |
8415 | if (s[1] == 't' && s[2] == ' ') | |
8416 | { | |
8417 | *s = '\0'; | |
8418 | mips16_small = true; | |
8419 | s += 3; | |
8420 | break; | |
8421 | } | |
8422 | else if (s[1] == 'e' && s[2] == ' ') | |
8423 | { | |
8424 | *s = '\0'; | |
8425 | mips16_ext = true; | |
8426 | s += 3; | |
8427 | break; | |
8428 | } | |
8429 | /* Fall through. */ | |
8430 | default: | |
8431 | insn_error = _("unknown opcode"); | |
8432 | return; | |
8433 | } | |
8434 | ||
8435 | if (mips_opts.noautoextend && ! mips16_ext) | |
8436 | mips16_small = true; | |
8437 | ||
8438 | if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL) | |
8439 | { | |
8440 | insn_error = _("unrecognized opcode"); | |
8441 | return; | |
8442 | } | |
8443 | ||
8444 | argsstart = s; | |
8445 | for (;;) | |
8446 | { | |
8447 | assert (strcmp (insn->name, str) == 0); | |
8448 | ||
8449 | ip->insn_mo = insn; | |
8450 | ip->insn_opcode = insn->match; | |
8451 | ip->use_extend = false; | |
8452 | imm_expr.X_op = O_absent; | |
f6688943 TS |
8453 | imm_reloc[0] = BFD_RELOC_UNUSED; |
8454 | imm_reloc[1] = BFD_RELOC_UNUSED; | |
8455 | imm_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 | 8456 | offset_expr.X_op = O_absent; |
f6688943 TS |
8457 | offset_reloc[0] = BFD_RELOC_UNUSED; |
8458 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
8459 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
8460 | for (args = insn->args; 1; ++args) |
8461 | { | |
8462 | int c; | |
8463 | ||
8464 | if (*s == ' ') | |
8465 | ++s; | |
8466 | ||
8467 | /* In this switch statement we call break if we did not find | |
8468 | a match, continue if we did find a match, or return if we | |
8469 | are done. */ | |
8470 | ||
8471 | c = *args; | |
8472 | switch (c) | |
8473 | { | |
8474 | case '\0': | |
8475 | if (*s == '\0') | |
8476 | { | |
8477 | /* Stuff the immediate value in now, if we can. */ | |
8478 | if (imm_expr.X_op == O_constant | |
f6688943 | 8479 | && *imm_reloc > BFD_RELOC_UNUSED |
252b5132 RH |
8480 | && insn->pinfo != INSN_MACRO) |
8481 | { | |
8482 | mips16_immed ((char *) NULL, 0, | |
f6688943 | 8483 | *imm_reloc - BFD_RELOC_UNUSED, |
252b5132 RH |
8484 | imm_expr.X_add_number, true, mips16_small, |
8485 | mips16_ext, &ip->insn_opcode, | |
8486 | &ip->use_extend, &ip->extend); | |
8487 | imm_expr.X_op = O_absent; | |
f6688943 | 8488 | *imm_reloc = BFD_RELOC_UNUSED; |
252b5132 RH |
8489 | } |
8490 | ||
8491 | return; | |
8492 | } | |
8493 | break; | |
8494 | ||
8495 | case ',': | |
8496 | if (*s++ == c) | |
8497 | continue; | |
8498 | s--; | |
8499 | switch (*++args) | |
8500 | { | |
8501 | case 'v': | |
8502 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RX; | |
8503 | continue; | |
8504 | case 'w': | |
8505 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RY; | |
8506 | continue; | |
8507 | } | |
8508 | break; | |
8509 | ||
8510 | case '(': | |
8511 | case ')': | |
8512 | if (*s++ == c) | |
8513 | continue; | |
8514 | break; | |
8515 | ||
8516 | case 'v': | |
8517 | case 'w': | |
8518 | if (s[0] != '$') | |
8519 | { | |
8520 | if (c == 'v') | |
8521 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RX; | |
8522 | else | |
8523 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RY; | |
8524 | ++args; | |
8525 | continue; | |
8526 | } | |
8527 | /* Fall through. */ | |
8528 | case 'x': | |
8529 | case 'y': | |
8530 | case 'z': | |
8531 | case 'Z': | |
8532 | case '0': | |
8533 | case 'S': | |
8534 | case 'R': | |
8535 | case 'X': | |
8536 | case 'Y': | |
8537 | if (s[0] != '$') | |
8538 | break; | |
8539 | s_reset = s; | |
3882b010 | 8540 | if (ISDIGIT (s[1])) |
252b5132 RH |
8541 | { |
8542 | ++s; | |
8543 | regno = 0; | |
8544 | do | |
8545 | { | |
8546 | regno *= 10; | |
8547 | regno += *s - '0'; | |
8548 | ++s; | |
8549 | } | |
3882b010 | 8550 | while (ISDIGIT (*s)); |
252b5132 RH |
8551 | if (regno > 31) |
8552 | { | |
8553 | as_bad (_("invalid register number (%d)"), regno); | |
8554 | regno = 2; | |
8555 | } | |
8556 | } | |
8557 | else | |
8558 | { | |
8559 | if (s[1] == 'f' && s[2] == 'p') | |
8560 | { | |
8561 | s += 3; | |
8562 | regno = FP; | |
8563 | } | |
8564 | else if (s[1] == 's' && s[2] == 'p') | |
8565 | { | |
8566 | s += 3; | |
8567 | regno = SP; | |
8568 | } | |
8569 | else if (s[1] == 'g' && s[2] == 'p') | |
8570 | { | |
8571 | s += 3; | |
8572 | regno = GP; | |
8573 | } | |
8574 | else if (s[1] == 'a' && s[2] == 't') | |
8575 | { | |
8576 | s += 3; | |
8577 | regno = AT; | |
8578 | } | |
8579 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '0') | |
8580 | { | |
8581 | s += 4; | |
8582 | regno = KT0; | |
8583 | } | |
8584 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '1') | |
8585 | { | |
8586 | s += 4; | |
8587 | regno = KT1; | |
8588 | } | |
8589 | else | |
8590 | break; | |
8591 | } | |
8592 | ||
8593 | if (*s == ' ') | |
8594 | ++s; | |
8595 | if (args[1] != *s) | |
8596 | { | |
8597 | if (c == 'v' || c == 'w') | |
8598 | { | |
8599 | regno = mips16_to_32_reg_map[lastregno]; | |
8600 | s = s_reset; | |
8601 | args++; | |
8602 | } | |
8603 | } | |
8604 | ||
8605 | switch (c) | |
8606 | { | |
8607 | case 'x': | |
8608 | case 'y': | |
8609 | case 'z': | |
8610 | case 'v': | |
8611 | case 'w': | |
8612 | case 'Z': | |
8613 | regno = mips32_to_16_reg_map[regno]; | |
8614 | break; | |
8615 | ||
8616 | case '0': | |
8617 | if (regno != 0) | |
8618 | regno = ILLEGAL_REG; | |
8619 | break; | |
8620 | ||
8621 | case 'S': | |
8622 | if (regno != SP) | |
8623 | regno = ILLEGAL_REG; | |
8624 | break; | |
8625 | ||
8626 | case 'R': | |
8627 | if (regno != RA) | |
8628 | regno = ILLEGAL_REG; | |
8629 | break; | |
8630 | ||
8631 | case 'X': | |
8632 | case 'Y': | |
8633 | if (regno == AT && ! mips_opts.noat) | |
8634 | as_warn (_("used $at without \".set noat\"")); | |
8635 | break; | |
8636 | ||
8637 | default: | |
8638 | internalError (); | |
8639 | } | |
8640 | ||
8641 | if (regno == ILLEGAL_REG) | |
8642 | break; | |
8643 | ||
8644 | switch (c) | |
8645 | { | |
8646 | case 'x': | |
8647 | case 'v': | |
8648 | ip->insn_opcode |= regno << MIPS16OP_SH_RX; | |
8649 | break; | |
8650 | case 'y': | |
8651 | case 'w': | |
8652 | ip->insn_opcode |= regno << MIPS16OP_SH_RY; | |
8653 | break; | |
8654 | case 'z': | |
8655 | ip->insn_opcode |= regno << MIPS16OP_SH_RZ; | |
8656 | break; | |
8657 | case 'Z': | |
8658 | ip->insn_opcode |= regno << MIPS16OP_SH_MOVE32Z; | |
8659 | case '0': | |
8660 | case 'S': | |
8661 | case 'R': | |
8662 | break; | |
8663 | case 'X': | |
8664 | ip->insn_opcode |= regno << MIPS16OP_SH_REGR32; | |
8665 | break; | |
8666 | case 'Y': | |
8667 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); | |
8668 | ip->insn_opcode |= regno << MIPS16OP_SH_REG32R; | |
8669 | break; | |
8670 | default: | |
8671 | internalError (); | |
8672 | } | |
8673 | ||
8674 | lastregno = regno; | |
8675 | continue; | |
8676 | ||
8677 | case 'P': | |
8678 | if (strncmp (s, "$pc", 3) == 0) | |
8679 | { | |
8680 | s += 3; | |
8681 | continue; | |
8682 | } | |
8683 | break; | |
8684 | ||
8685 | case '<': | |
8686 | case '>': | |
8687 | case '[': | |
8688 | case ']': | |
8689 | case '4': | |
8690 | case '5': | |
8691 | case 'H': | |
8692 | case 'W': | |
8693 | case 'D': | |
8694 | case 'j': | |
8695 | case '8': | |
8696 | case 'V': | |
8697 | case 'C': | |
8698 | case 'U': | |
8699 | case 'k': | |
8700 | case 'K': | |
8701 | if (s[0] == '%' | |
8702 | && strncmp (s + 1, "gprel(", sizeof "gprel(" - 1) == 0) | |
8703 | { | |
8704 | /* This is %gprel(SYMBOL). We need to read SYMBOL, | |
8705 | and generate the appropriate reloc. If the text | |
8706 | inside %gprel is not a symbol name with an | |
8707 | optional offset, then we generate a normal reloc | |
8708 | and will probably fail later. */ | |
8709 | my_getExpression (&imm_expr, s + sizeof "%gprel" - 1); | |
8710 | if (imm_expr.X_op == O_symbol) | |
8711 | { | |
8712 | mips16_ext = true; | |
f6688943 | 8713 | *imm_reloc = BFD_RELOC_MIPS16_GPREL; |
252b5132 RH |
8714 | s = expr_end; |
8715 | ip->use_extend = true; | |
8716 | ip->extend = 0; | |
8717 | continue; | |
8718 | } | |
8719 | } | |
8720 | else | |
8721 | { | |
8722 | /* Just pick up a normal expression. */ | |
8723 | my_getExpression (&imm_expr, s); | |
8724 | } | |
8725 | ||
8726 | if (imm_expr.X_op == O_register) | |
8727 | { | |
8728 | /* What we thought was an expression turned out to | |
8729 | be a register. */ | |
8730 | ||
8731 | if (s[0] == '(' && args[1] == '(') | |
8732 | { | |
8733 | /* It looks like the expression was omitted | |
8734 | before a register indirection, which means | |
8735 | that the expression is implicitly zero. We | |
8736 | still set up imm_expr, so that we handle | |
8737 | explicit extensions correctly. */ | |
8738 | imm_expr.X_op = O_constant; | |
8739 | imm_expr.X_add_number = 0; | |
f6688943 | 8740 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
8741 | continue; |
8742 | } | |
8743 | ||
8744 | break; | |
8745 | } | |
8746 | ||
8747 | /* We need to relax this instruction. */ | |
f6688943 | 8748 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
8749 | s = expr_end; |
8750 | continue; | |
8751 | ||
8752 | case 'p': | |
8753 | case 'q': | |
8754 | case 'A': | |
8755 | case 'B': | |
8756 | case 'E': | |
8757 | /* We use offset_reloc rather than imm_reloc for the PC | |
8758 | relative operands. This lets macros with both | |
8759 | immediate and address operands work correctly. */ | |
8760 | my_getExpression (&offset_expr, s); | |
8761 | ||
8762 | if (offset_expr.X_op == O_register) | |
8763 | break; | |
8764 | ||
8765 | /* We need to relax this instruction. */ | |
f6688943 | 8766 | *offset_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
8767 | s = expr_end; |
8768 | continue; | |
8769 | ||
8770 | case '6': /* break code */ | |
8771 | my_getExpression (&imm_expr, s); | |
8772 | check_absolute_expr (ip, &imm_expr); | |
8773 | if ((unsigned long) imm_expr.X_add_number > 63) | |
8774 | { | |
8775 | as_warn (_("Invalid value for `%s' (%lu)"), | |
8776 | ip->insn_mo->name, | |
8777 | (unsigned long) imm_expr.X_add_number); | |
8778 | imm_expr.X_add_number &= 0x3f; | |
8779 | } | |
8780 | ip->insn_opcode |= imm_expr.X_add_number << MIPS16OP_SH_IMM6; | |
8781 | imm_expr.X_op = O_absent; | |
8782 | s = expr_end; | |
8783 | continue; | |
8784 | ||
8785 | case 'a': /* 26 bit address */ | |
8786 | my_getExpression (&offset_expr, s); | |
8787 | s = expr_end; | |
f6688943 | 8788 | *offset_reloc = BFD_RELOC_MIPS16_JMP; |
252b5132 RH |
8789 | ip->insn_opcode <<= 16; |
8790 | continue; | |
8791 | ||
8792 | case 'l': /* register list for entry macro */ | |
8793 | case 'L': /* register list for exit macro */ | |
8794 | { | |
8795 | int mask; | |
8796 | ||
8797 | if (c == 'l') | |
8798 | mask = 0; | |
8799 | else | |
8800 | mask = 7 << 3; | |
8801 | while (*s != '\0') | |
8802 | { | |
8803 | int freg, reg1, reg2; | |
8804 | ||
8805 | while (*s == ' ' || *s == ',') | |
8806 | ++s; | |
8807 | if (*s != '$') | |
8808 | { | |
8809 | as_bad (_("can't parse register list")); | |
8810 | break; | |
8811 | } | |
8812 | ++s; | |
8813 | if (*s != 'f') | |
8814 | freg = 0; | |
8815 | else | |
8816 | { | |
8817 | freg = 1; | |
8818 | ++s; | |
8819 | } | |
8820 | reg1 = 0; | |
3882b010 | 8821 | while (ISDIGIT (*s)) |
252b5132 RH |
8822 | { |
8823 | reg1 *= 10; | |
8824 | reg1 += *s - '0'; | |
8825 | ++s; | |
8826 | } | |
8827 | if (*s == ' ') | |
8828 | ++s; | |
8829 | if (*s != '-') | |
8830 | reg2 = reg1; | |
8831 | else | |
8832 | { | |
8833 | ++s; | |
8834 | if (*s != '$') | |
8835 | break; | |
8836 | ++s; | |
8837 | if (freg) | |
8838 | { | |
8839 | if (*s == 'f') | |
8840 | ++s; | |
8841 | else | |
8842 | { | |
8843 | as_bad (_("invalid register list")); | |
8844 | break; | |
8845 | } | |
8846 | } | |
8847 | reg2 = 0; | |
3882b010 | 8848 | while (ISDIGIT (*s)) |
252b5132 RH |
8849 | { |
8850 | reg2 *= 10; | |
8851 | reg2 += *s - '0'; | |
8852 | ++s; | |
8853 | } | |
8854 | } | |
8855 | if (freg && reg1 == 0 && reg2 == 0 && c == 'L') | |
8856 | { | |
8857 | mask &= ~ (7 << 3); | |
8858 | mask |= 5 << 3; | |
8859 | } | |
8860 | else if (freg && reg1 == 0 && reg2 == 1 && c == 'L') | |
8861 | { | |
8862 | mask &= ~ (7 << 3); | |
8863 | mask |= 6 << 3; | |
8864 | } | |
8865 | else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L') | |
8866 | mask |= (reg2 - 3) << 3; | |
8867 | else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17) | |
8868 | mask |= (reg2 - 15) << 1; | |
8869 | else if (reg1 == 31 && reg2 == 31) | |
8870 | mask |= 1; | |
8871 | else | |
8872 | { | |
8873 | as_bad (_("invalid register list")); | |
8874 | break; | |
8875 | } | |
8876 | } | |
8877 | /* The mask is filled in in the opcode table for the | |
8878 | benefit of the disassembler. We remove it before | |
8879 | applying the actual mask. */ | |
8880 | ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6); | |
8881 | ip->insn_opcode |= mask << MIPS16OP_SH_IMM6; | |
8882 | } | |
8883 | continue; | |
8884 | ||
8885 | case 'e': /* extend code */ | |
8886 | my_getExpression (&imm_expr, s); | |
8887 | check_absolute_expr (ip, &imm_expr); | |
8888 | if ((unsigned long) imm_expr.X_add_number > 0x7ff) | |
8889 | { | |
8890 | as_warn (_("Invalid value for `%s' (%lu)"), | |
8891 | ip->insn_mo->name, | |
8892 | (unsigned long) imm_expr.X_add_number); | |
8893 | imm_expr.X_add_number &= 0x7ff; | |
8894 | } | |
8895 | ip->insn_opcode |= imm_expr.X_add_number; | |
8896 | imm_expr.X_op = O_absent; | |
8897 | s = expr_end; | |
8898 | continue; | |
8899 | ||
8900 | default: | |
8901 | internalError (); | |
8902 | } | |
8903 | break; | |
8904 | } | |
8905 | ||
8906 | /* Args don't match. */ | |
8907 | if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] && | |
8908 | strcmp (insn->name, insn[1].name) == 0) | |
8909 | { | |
8910 | ++insn; | |
8911 | s = argsstart; | |
8912 | continue; | |
8913 | } | |
8914 | ||
8915 | insn_error = _("illegal operands"); | |
8916 | ||
8917 | return; | |
8918 | } | |
8919 | } | |
8920 | ||
8921 | /* This structure holds information we know about a mips16 immediate | |
8922 | argument type. */ | |
8923 | ||
e972090a NC |
8924 | struct mips16_immed_operand |
8925 | { | |
252b5132 RH |
8926 | /* The type code used in the argument string in the opcode table. */ |
8927 | int type; | |
8928 | /* The number of bits in the short form of the opcode. */ | |
8929 | int nbits; | |
8930 | /* The number of bits in the extended form of the opcode. */ | |
8931 | int extbits; | |
8932 | /* The amount by which the short form is shifted when it is used; | |
8933 | for example, the sw instruction has a shift count of 2. */ | |
8934 | int shift; | |
8935 | /* The amount by which the short form is shifted when it is stored | |
8936 | into the instruction code. */ | |
8937 | int op_shift; | |
8938 | /* Non-zero if the short form is unsigned. */ | |
8939 | int unsp; | |
8940 | /* Non-zero if the extended form is unsigned. */ | |
8941 | int extu; | |
8942 | /* Non-zero if the value is PC relative. */ | |
8943 | int pcrel; | |
8944 | }; | |
8945 | ||
8946 | /* The mips16 immediate operand types. */ | |
8947 | ||
8948 | static const struct mips16_immed_operand mips16_immed_operands[] = | |
8949 | { | |
8950 | { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
8951 | { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
8952 | { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
8953 | { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
8954 | { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 }, | |
8955 | { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
8956 | { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
8957 | { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
8958 | { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
8959 | { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 }, | |
8960 | { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
8961 | { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
8962 | { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
8963 | { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 }, | |
8964 | { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
8965 | { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
8966 | { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
8967 | { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
8968 | { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 }, | |
8969 | { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 }, | |
8970 | { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 } | |
8971 | }; | |
8972 | ||
8973 | #define MIPS16_NUM_IMMED \ | |
8974 | (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0]) | |
8975 | ||
8976 | /* Handle a mips16 instruction with an immediate value. This or's the | |
8977 | small immediate value into *INSN. It sets *USE_EXTEND to indicate | |
8978 | whether an extended value is needed; if one is needed, it sets | |
8979 | *EXTEND to the value. The argument type is TYPE. The value is VAL. | |
8980 | If SMALL is true, an unextended opcode was explicitly requested. | |
8981 | If EXT is true, an extended opcode was explicitly requested. If | |
8982 | WARN is true, warn if EXT does not match reality. */ | |
8983 | ||
8984 | static void | |
8985 | mips16_immed (file, line, type, val, warn, small, ext, insn, use_extend, | |
8986 | extend) | |
8987 | char *file; | |
8988 | unsigned int line; | |
8989 | int type; | |
8990 | offsetT val; | |
8991 | boolean warn; | |
8992 | boolean small; | |
8993 | boolean ext; | |
8994 | unsigned long *insn; | |
8995 | boolean *use_extend; | |
8996 | unsigned short *extend; | |
8997 | { | |
8998 | register const struct mips16_immed_operand *op; | |
8999 | int mintiny, maxtiny; | |
9000 | boolean needext; | |
9001 | ||
9002 | op = mips16_immed_operands; | |
9003 | while (op->type != type) | |
9004 | { | |
9005 | ++op; | |
9006 | assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); | |
9007 | } | |
9008 | ||
9009 | if (op->unsp) | |
9010 | { | |
9011 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
9012 | { | |
9013 | mintiny = 1; | |
9014 | maxtiny = 1 << op->nbits; | |
9015 | } | |
9016 | else | |
9017 | { | |
9018 | mintiny = 0; | |
9019 | maxtiny = (1 << op->nbits) - 1; | |
9020 | } | |
9021 | } | |
9022 | else | |
9023 | { | |
9024 | mintiny = - (1 << (op->nbits - 1)); | |
9025 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
9026 | } | |
9027 | ||
9028 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
9029 | if (type == 'p' || type == 'q') | |
9030 | val /= 2; | |
9031 | ||
9032 | if ((val & ((1 << op->shift) - 1)) != 0 | |
9033 | || val < (mintiny << op->shift) | |
9034 | || val > (maxtiny << op->shift)) | |
9035 | needext = true; | |
9036 | else | |
9037 | needext = false; | |
9038 | ||
9039 | if (warn && ext && ! needext) | |
beae10d5 KH |
9040 | as_warn_where (file, line, |
9041 | _("extended operand requested but not required")); | |
252b5132 RH |
9042 | if (small && needext) |
9043 | as_bad_where (file, line, _("invalid unextended operand value")); | |
9044 | ||
9045 | if (small || (! ext && ! needext)) | |
9046 | { | |
9047 | int insnval; | |
9048 | ||
9049 | *use_extend = false; | |
9050 | insnval = ((val >> op->shift) & ((1 << op->nbits) - 1)); | |
9051 | insnval <<= op->op_shift; | |
9052 | *insn |= insnval; | |
9053 | } | |
9054 | else | |
9055 | { | |
9056 | long minext, maxext; | |
9057 | int extval; | |
9058 | ||
9059 | if (op->extu) | |
9060 | { | |
9061 | minext = 0; | |
9062 | maxext = (1 << op->extbits) - 1; | |
9063 | } | |
9064 | else | |
9065 | { | |
9066 | minext = - (1 << (op->extbits - 1)); | |
9067 | maxext = (1 << (op->extbits - 1)) - 1; | |
9068 | } | |
9069 | if (val < minext || val > maxext) | |
9070 | as_bad_where (file, line, | |
9071 | _("operand value out of range for instruction")); | |
9072 | ||
9073 | *use_extend = true; | |
9074 | if (op->extbits == 16) | |
9075 | { | |
9076 | extval = ((val >> 11) & 0x1f) | (val & 0x7e0); | |
9077 | val &= 0x1f; | |
9078 | } | |
9079 | else if (op->extbits == 15) | |
9080 | { | |
9081 | extval = ((val >> 11) & 0xf) | (val & 0x7f0); | |
9082 | val &= 0xf; | |
9083 | } | |
9084 | else | |
9085 | { | |
9086 | extval = ((val & 0x1f) << 6) | (val & 0x20); | |
9087 | val = 0; | |
9088 | } | |
9089 | ||
9090 | *extend = (unsigned short) extval; | |
9091 | *insn |= val; | |
9092 | } | |
9093 | } | |
9094 | \f | |
ad8d3bb3 TS |
9095 | static struct percent_op_match |
9096 | { | |
9097 | const char *str; | |
9098 | const enum small_ex_type type; | |
9099 | } percent_op[] = | |
9100 | { | |
9101 | #ifdef OBJ_ELF | |
9102 | {"%half", S_EX_HALF}, | |
9103 | #endif | |
9104 | {"%hi", S_EX_HI}, | |
9105 | {"%lo", S_EX_LO}, | |
9106 | #ifdef OBJ_ELF | |
9107 | {"%gp_rel", S_EX_GP_REL}, | |
9108 | {"%got", S_EX_GOT}, | |
9109 | {"%call16", S_EX_CALL16}, | |
9110 | {"%got_disp", S_EX_GOT_DISP}, | |
9111 | {"%got_page", S_EX_GOT_PAGE}, | |
9112 | {"%got_ofst", S_EX_GOT_OFST}, | |
9113 | {"%got_hi", S_EX_GOT_HI}, | |
9114 | {"%got_lo", S_EX_GOT_LO}, | |
9115 | {"%neg", S_EX_NEG}, | |
9116 | {"%higher", S_EX_HIGHER}, | |
9117 | {"%highest", S_EX_HIGHEST}, | |
9118 | {"%call_hi", S_EX_CALL_HI}, | |
9119 | {"%call_lo", S_EX_CALL_LO} | |
9120 | #endif | |
9121 | }; | |
9122 | ||
9123 | /* Parse small expression input. STR gets adjusted to eat up whitespace. | |
9124 | It detects valid "%percent_op(...)" and "($reg)" strings. Percent_op's | |
9125 | can be nested, this is handled by blanking the innermost, parsing the | |
9126 | rest by subsequent calls. */ | |
252b5132 RH |
9127 | |
9128 | static int | |
ad8d3bb3 TS |
9129 | my_getSmallParser (str, len, nestlevel) |
9130 | char **str; | |
9131 | unsigned int *len; | |
9132 | int *nestlevel; | |
252b5132 | 9133 | { |
ad8d3bb3 | 9134 | int type = S_EX_NONE; |
252b5132 | 9135 | |
ad8d3bb3 TS |
9136 | *len = 0; |
9137 | *str += strspn (*str, " \t"); | |
9138 | if (**str == '(') | |
252b5132 | 9139 | { |
ad8d3bb3 TS |
9140 | char *b = *str + 1 + strspn (*str + 1, " \t"); |
9141 | char *e; | |
9142 | ||
9143 | /* Check for base register. */ | |
9144 | if (b[0] == '$') | |
9145 | { | |
9146 | if (strchr (b, ')') | |
9147 | && (e = b + strcspn (b, ") \t")) | |
9148 | && e - b > 1 && e - b < 4) | |
9149 | { | |
9150 | if ((e - b == 3 | |
9151 | && ((b[1] == 'f' && b[2] == 'p') | |
9152 | || (b[1] == 's' && b[2] == 'p') | |
9153 | || (b[1] == 'g' && b[2] == 'p') | |
9154 | || (b[1] == 'a' && b[2] == 't') | |
9155 | || (ISDIGIT (b[1]) | |
9156 | && ISDIGIT (b[2])))) | |
9157 | || (ISDIGIT (b[1]))) | |
9158 | { | |
9159 | *len = strcspn (*str, ")") + 1; | |
9160 | return S_EX_REGISTER; | |
9161 | } | |
9162 | } | |
9163 | } | |
9164 | else if (b[0] == '%') | |
9165 | { | |
9166 | *str = b; | |
9167 | goto percent_op; | |
9168 | } | |
9169 | else | |
9170 | /* Some other expression in the braces. */ | |
9171 | *len = strcspn (*str, ")") + 1; | |
fb1b3232 | 9172 | } |
ad8d3bb3 TS |
9173 | /* Check for percent_op. */ |
9174 | else if (*str[0] == '%') | |
fb1b3232 | 9175 | { |
ad8d3bb3 TS |
9176 | char *tmp; |
9177 | unsigned int i; | |
9178 | ||
9179 | percent_op: | |
9180 | tmp = *str + 1; | |
9181 | i = 0; | |
9182 | ||
9183 | while (ISALPHA (*tmp) || *tmp == '_') | |
9184 | { | |
9185 | *tmp = TOLOWER (*tmp); | |
9186 | tmp++; | |
9187 | } | |
9188 | while (i < (sizeof (percent_op) / sizeof (struct percent_op_match))) | |
9189 | { | |
9190 | if (strncmp (*str, percent_op[i].str, strlen (percent_op[i].str))) | |
9191 | i++; | |
9192 | else | |
9193 | { | |
9194 | type = percent_op[i].type; | |
9195 | ||
9196 | /* Only %hi and %lo are allowed for OldABI. */ | |
9197 | if (! HAVE_NEWABI && type != S_EX_HI && type != S_EX_LO) | |
9198 | return S_EX_NONE; | |
9199 | ||
9200 | *len = strlen (percent_op[i].str); | |
9201 | (*nestlevel)++; | |
9202 | return type; | |
9203 | } | |
9204 | } | |
fb1b3232 | 9205 | } |
ad8d3bb3 TS |
9206 | |
9207 | /* Any other expression. */ | |
9208 | return S_EX_NONE; | |
9209 | } | |
9210 | ||
9211 | static int | |
9212 | my_getSmallExpression (ep, str) | |
9213 | expressionS *ep; | |
9214 | char *str; | |
9215 | { | |
9216 | static char *oldstr = NULL; | |
9217 | int c = S_EX_NONE; | |
9218 | int oldc; | |
9219 | int nest_level = 0; | |
9220 | unsigned int len; | |
9221 | ||
9222 | /* Don't update oldstr if the last call had nested percent_op's. */ | |
9223 | if (! oldstr) | |
9224 | oldstr = str; | |
9225 | ||
9226 | do | |
fb1b3232 | 9227 | { |
ad8d3bb3 TS |
9228 | oldc = c; |
9229 | c = my_getSmallParser (&str, &len, &nest_level); | |
9230 | if (c != S_EX_NONE && c != S_EX_REGISTER) | |
9231 | str += len; | |
fb1b3232 | 9232 | } |
ad8d3bb3 TS |
9233 | while (c != S_EX_NONE && c != S_EX_REGISTER); |
9234 | ||
9235 | /* A percent_op was encountered. */ | |
9236 | if (nest_level) | |
fb1b3232 | 9237 | { |
b6ff326e | 9238 | /* Don't try to get an expression if it is already blanked out. */ |
ad8d3bb3 TS |
9239 | if (*(str + strspn (str + 1, " )")) != ')') |
9240 | { | |
9241 | char save; | |
9242 | ||
9243 | save = *(str + len); | |
9244 | *(str + len) = '\0'; | |
9245 | my_getExpression (ep, str); | |
9246 | *(str + len) = save; | |
9247 | } | |
9248 | if (nest_level > 1) | |
9249 | { | |
9250 | /* blank out including the % sign. */ | |
9251 | char *p = strrchr (oldstr, '%'); | |
9252 | memset (p, ' ', str - p + len); | |
9253 | str = oldstr; | |
9254 | } | |
9255 | else | |
9256 | { | |
9257 | expr_end = strchr (str, ')') + 1; | |
9258 | } | |
9259 | c = oldc; | |
fb1b3232 | 9260 | } |
ad8d3bb3 | 9261 | else if (c == S_EX_NONE) |
fb1b3232 | 9262 | { |
ad8d3bb3 | 9263 | my_getExpression (ep, str); |
fb1b3232 | 9264 | } |
ad8d3bb3 | 9265 | else if (c == S_EX_REGISTER) |
fb1b3232 | 9266 | { |
ad8d3bb3 TS |
9267 | ep->X_op = O_constant; |
9268 | expr_end = str; | |
9269 | ep->X_add_symbol = NULL; | |
9270 | ep->X_op_symbol = NULL; | |
9271 | ep->X_add_number = 0; | |
fb1b3232 | 9272 | } |
fb1b3232 TS |
9273 | else |
9274 | { | |
ad8d3bb3 | 9275 | as_fatal(_("internal error")); |
fb1b3232 | 9276 | } |
252b5132 | 9277 | |
ad8d3bb3 TS |
9278 | if (nest_level <= 1) |
9279 | oldstr = NULL; | |
fb1b3232 | 9280 | |
fb1b3232 | 9281 | return c; |
252b5132 RH |
9282 | } |
9283 | ||
9284 | static void | |
9285 | my_getExpression (ep, str) | |
9286 | expressionS *ep; | |
9287 | char *str; | |
9288 | { | |
9289 | char *save_in; | |
98aa84af | 9290 | valueT val; |
252b5132 RH |
9291 | |
9292 | save_in = input_line_pointer; | |
9293 | input_line_pointer = str; | |
9294 | expression (ep); | |
9295 | expr_end = input_line_pointer; | |
9296 | input_line_pointer = save_in; | |
9297 | ||
9298 | /* If we are in mips16 mode, and this is an expression based on `.', | |
9299 | then we bump the value of the symbol by 1 since that is how other | |
9300 | text symbols are handled. We don't bother to handle complex | |
9301 | expressions, just `.' plus or minus a constant. */ | |
9302 | if (mips_opts.mips16 | |
9303 | && ep->X_op == O_symbol | |
9304 | && strcmp (S_GET_NAME (ep->X_add_symbol), FAKE_LABEL_NAME) == 0 | |
9305 | && S_GET_SEGMENT (ep->X_add_symbol) == now_seg | |
49309057 ILT |
9306 | && symbol_get_frag (ep->X_add_symbol) == frag_now |
9307 | && symbol_constant_p (ep->X_add_symbol) | |
98aa84af AM |
9308 | && (val = S_GET_VALUE (ep->X_add_symbol)) == frag_now_fix ()) |
9309 | S_SET_VALUE (ep->X_add_symbol, val + 1); | |
252b5132 RH |
9310 | } |
9311 | ||
9312 | /* Turn a string in input_line_pointer into a floating point constant | |
bc0d738a NC |
9313 | of type TYPE, and store the appropriate bytes in *LITP. The number |
9314 | of LITTLENUMS emitted is stored in *SIZEP. An error message is | |
252b5132 RH |
9315 | returned, or NULL on OK. */ |
9316 | ||
9317 | char * | |
9318 | md_atof (type, litP, sizeP) | |
9319 | int type; | |
9320 | char *litP; | |
9321 | int *sizeP; | |
9322 | { | |
9323 | int prec; | |
9324 | LITTLENUM_TYPE words[4]; | |
9325 | char *t; | |
9326 | int i; | |
9327 | ||
9328 | switch (type) | |
9329 | { | |
9330 | case 'f': | |
9331 | prec = 2; | |
9332 | break; | |
9333 | ||
9334 | case 'd': | |
9335 | prec = 4; | |
9336 | break; | |
9337 | ||
9338 | default: | |
9339 | *sizeP = 0; | |
9340 | return _("bad call to md_atof"); | |
9341 | } | |
9342 | ||
9343 | t = atof_ieee (input_line_pointer, type, words); | |
9344 | if (t) | |
9345 | input_line_pointer = t; | |
9346 | ||
9347 | *sizeP = prec * 2; | |
9348 | ||
9349 | if (! target_big_endian) | |
9350 | { | |
9351 | for (i = prec - 1; i >= 0; i--) | |
9352 | { | |
9353 | md_number_to_chars (litP, (valueT) words[i], 2); | |
9354 | litP += 2; | |
9355 | } | |
9356 | } | |
9357 | else | |
9358 | { | |
9359 | for (i = 0; i < prec; i++) | |
9360 | { | |
9361 | md_number_to_chars (litP, (valueT) words[i], 2); | |
9362 | litP += 2; | |
9363 | } | |
9364 | } | |
bdaaa2e1 | 9365 | |
252b5132 RH |
9366 | return NULL; |
9367 | } | |
9368 | ||
9369 | void | |
9370 | md_number_to_chars (buf, val, n) | |
9371 | char *buf; | |
9372 | valueT val; | |
9373 | int n; | |
9374 | { | |
9375 | if (target_big_endian) | |
9376 | number_to_chars_bigendian (buf, val, n); | |
9377 | else | |
9378 | number_to_chars_littleendian (buf, val, n); | |
9379 | } | |
9380 | \f | |
e013f690 TS |
9381 | static int support_64bit_objects(void) |
9382 | { | |
9383 | const char **list, **l; | |
9384 | ||
9385 | list = bfd_target_list (); | |
9386 | for (l = list; *l != NULL; l++) | |
9387 | #ifdef TE_TMIPS | |
9388 | /* This is traditional mips */ | |
9389 | if (strcmp (*l, "elf64-tradbigmips") == 0 | |
9390 | || strcmp (*l, "elf64-tradlittlemips") == 0) | |
9391 | #else | |
9392 | if (strcmp (*l, "elf64-bigmips") == 0 | |
9393 | || strcmp (*l, "elf64-littlemips") == 0) | |
9394 | #endif | |
9395 | break; | |
9396 | free (list); | |
9397 | return (*l != NULL); | |
9398 | } | |
9399 | ||
39c0a331 | 9400 | CONST char *md_shortopts = "nO::g::G:"; |
252b5132 | 9401 | |
e972090a NC |
9402 | struct option md_longopts[] = |
9403 | { | |
252b5132 RH |
9404 | #define OPTION_MIPS1 (OPTION_MD_BASE + 1) |
9405 | {"mips0", no_argument, NULL, OPTION_MIPS1}, | |
9406 | {"mips1", no_argument, NULL, OPTION_MIPS1}, | |
9407 | #define OPTION_MIPS2 (OPTION_MD_BASE + 2) | |
9408 | {"mips2", no_argument, NULL, OPTION_MIPS2}, | |
9409 | #define OPTION_MIPS3 (OPTION_MD_BASE + 3) | |
9410 | {"mips3", no_argument, NULL, OPTION_MIPS3}, | |
9411 | #define OPTION_MIPS4 (OPTION_MD_BASE + 4) | |
9412 | {"mips4", no_argument, NULL, OPTION_MIPS4}, | |
9413 | #define OPTION_MCPU (OPTION_MD_BASE + 5) | |
9414 | {"mcpu", required_argument, NULL, OPTION_MCPU}, | |
9415 | #define OPTION_MEMBEDDED_PIC (OPTION_MD_BASE + 6) | |
9416 | {"membedded-pic", no_argument, NULL, OPTION_MEMBEDDED_PIC}, | |
156c2f8b | 9417 | #define OPTION_TRAP (OPTION_MD_BASE + 7) |
252b5132 RH |
9418 | {"trap", no_argument, NULL, OPTION_TRAP}, |
9419 | {"no-break", no_argument, NULL, OPTION_TRAP}, | |
156c2f8b | 9420 | #define OPTION_BREAK (OPTION_MD_BASE + 8) |
252b5132 RH |
9421 | {"break", no_argument, NULL, OPTION_BREAK}, |
9422 | {"no-trap", no_argument, NULL, OPTION_BREAK}, | |
156c2f8b | 9423 | #define OPTION_EB (OPTION_MD_BASE + 9) |
252b5132 | 9424 | {"EB", no_argument, NULL, OPTION_EB}, |
156c2f8b | 9425 | #define OPTION_EL (OPTION_MD_BASE + 10) |
252b5132 | 9426 | {"EL", no_argument, NULL, OPTION_EL}, |
156c2f8b | 9427 | #define OPTION_M4650 (OPTION_MD_BASE + 11) |
252b5132 | 9428 | {"m4650", no_argument, NULL, OPTION_M4650}, |
156c2f8b | 9429 | #define OPTION_NO_M4650 (OPTION_MD_BASE + 12) |
252b5132 | 9430 | {"no-m4650", no_argument, NULL, OPTION_NO_M4650}, |
156c2f8b | 9431 | #define OPTION_M4010 (OPTION_MD_BASE + 13) |
252b5132 | 9432 | {"m4010", no_argument, NULL, OPTION_M4010}, |
156c2f8b | 9433 | #define OPTION_NO_M4010 (OPTION_MD_BASE + 14) |
252b5132 | 9434 | {"no-m4010", no_argument, NULL, OPTION_NO_M4010}, |
156c2f8b | 9435 | #define OPTION_M4100 (OPTION_MD_BASE + 15) |
252b5132 | 9436 | {"m4100", no_argument, NULL, OPTION_M4100}, |
156c2f8b | 9437 | #define OPTION_NO_M4100 (OPTION_MD_BASE + 16) |
252b5132 | 9438 | {"no-m4100", no_argument, NULL, OPTION_NO_M4100}, |
156c2f8b | 9439 | #define OPTION_MIPS16 (OPTION_MD_BASE + 17) |
252b5132 | 9440 | {"mips16", no_argument, NULL, OPTION_MIPS16}, |
156c2f8b | 9441 | #define OPTION_NO_MIPS16 (OPTION_MD_BASE + 18) |
252b5132 | 9442 | {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16}, |
156c2f8b | 9443 | #define OPTION_M3900 (OPTION_MD_BASE + 19) |
252b5132 | 9444 | {"m3900", no_argument, NULL, OPTION_M3900}, |
156c2f8b | 9445 | #define OPTION_NO_M3900 (OPTION_MD_BASE + 20) |
252b5132 | 9446 | {"no-m3900", no_argument, NULL, OPTION_NO_M3900}, |
156c2f8b | 9447 | #define OPTION_MABI (OPTION_MD_BASE + 21) |
252b5132 | 9448 | {"mabi", required_argument, NULL, OPTION_MABI}, |
156c2f8b | 9449 | #define OPTION_M7000_HILO_FIX (OPTION_MD_BASE + 22) |
6b76fefe | 9450 | {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX}, |
156c2f8b | 9451 | #define OPTION_NO_M7000_HILO_FIX (OPTION_MD_BASE + 23) |
6b76fefe | 9452 | {"no-fix-7000", no_argument, NULL, OPTION_NO_M7000_HILO_FIX}, |
156c2f8b | 9453 | #define OPTION_GP32 (OPTION_MD_BASE + 24) |
c97ef257 | 9454 | {"mgp32", no_argument, NULL, OPTION_GP32}, |
156c2f8b | 9455 | #define OPTION_GP64 (OPTION_MD_BASE + 25) |
c97ef257 | 9456 | {"mgp64", no_argument, NULL, OPTION_GP64}, |
156c2f8b | 9457 | #define OPTION_CONSTRUCT_FLOATS (OPTION_MD_BASE + 26) |
119d663a | 9458 | {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS}, |
156c2f8b | 9459 | #define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MD_BASE + 27) |
119d663a | 9460 | {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS}, |
156c2f8b NC |
9461 | #define OPTION_MIPS32 (OPTION_MD_BASE + 28) |
9462 | {"mips32", no_argument, NULL, OPTION_MIPS32}, | |
84ea6cf2 NC |
9463 | #define OPTION_MIPS5 (OPTION_MD_BASE + 29) |
9464 | {"mips5", no_argument, NULL, OPTION_MIPS5}, | |
9465 | #define OPTION_MIPS64 (OPTION_MD_BASE + 30) | |
9466 | {"mips64", no_argument, NULL, OPTION_MIPS64}, | |
ec68c924 EC |
9467 | #define OPTION_MARCH (OPTION_MD_BASE + 31) |
9468 | {"march", required_argument, NULL, OPTION_MARCH}, | |
9469 | #define OPTION_MTUNE (OPTION_MD_BASE + 32) | |
9470 | {"mtune", required_argument, NULL, OPTION_MTUNE}, | |
ca4e0257 RS |
9471 | #define OPTION_FP32 (OPTION_MD_BASE + 33) |
9472 | {"mfp32", no_argument, NULL, OPTION_FP32}, | |
156c2f8b NC |
9473 | #ifdef OBJ_ELF |
9474 | #define OPTION_ELF_BASE (OPTION_MD_BASE + 35) | |
9475 | #define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0) | |
9476 | #define OPTION_NON_SHARED (OPTION_ELF_BASE + 1) | |
9477 | #define OPTION_XGOT (OPTION_ELF_BASE + 2) | |
9478 | #define OPTION_32 (OPTION_ELF_BASE + 3) | |
e013f690 TS |
9479 | #define OPTION_N32 (OPTION_ELF_BASE + 4) |
9480 | #define OPTION_64 (OPTION_ELF_BASE + 5) | |
156c2f8b NC |
9481 | {"KPIC", no_argument, NULL, OPTION_CALL_SHARED}, |
9482 | {"call_shared", no_argument, NULL, OPTION_CALL_SHARED}, | |
9483 | {"non_shared", no_argument, NULL, OPTION_NON_SHARED}, | |
9484 | {"xgot", no_argument, NULL, OPTION_XGOT}, | |
9485 | {"32", no_argument, NULL, OPTION_32}, | |
e013f690 | 9486 | {"n32", no_argument, NULL, OPTION_N32}, |
156c2f8b NC |
9487 | {"64", no_argument, NULL, OPTION_64}, |
9488 | #endif | |
119d663a | 9489 | |
252b5132 RH |
9490 | {NULL, no_argument, NULL, 0} |
9491 | }; | |
156c2f8b | 9492 | size_t md_longopts_size = sizeof (md_longopts); |
252b5132 RH |
9493 | |
9494 | int | |
9495 | md_parse_option (c, arg) | |
9496 | int c; | |
9497 | char *arg; | |
9498 | { | |
9499 | switch (c) | |
9500 | { | |
119d663a NC |
9501 | case OPTION_CONSTRUCT_FLOATS: |
9502 | mips_disable_float_construction = 0; | |
9503 | break; | |
bdaaa2e1 | 9504 | |
119d663a NC |
9505 | case OPTION_NO_CONSTRUCT_FLOATS: |
9506 | mips_disable_float_construction = 1; | |
9507 | break; | |
bdaaa2e1 | 9508 | |
252b5132 RH |
9509 | case OPTION_TRAP: |
9510 | mips_trap = 1; | |
9511 | break; | |
9512 | ||
9513 | case OPTION_BREAK: | |
9514 | mips_trap = 0; | |
9515 | break; | |
9516 | ||
9517 | case OPTION_EB: | |
9518 | target_big_endian = 1; | |
9519 | break; | |
9520 | ||
9521 | case OPTION_EL: | |
9522 | target_big_endian = 0; | |
9523 | break; | |
9524 | ||
39c0a331 L |
9525 | case 'n': |
9526 | warn_nops = 1; | |
9527 | break; | |
9528 | ||
252b5132 RH |
9529 | case 'O': |
9530 | if (arg && arg[1] == '0') | |
9531 | mips_optimize = 1; | |
9532 | else | |
9533 | mips_optimize = 2; | |
9534 | break; | |
9535 | ||
9536 | case 'g': | |
9537 | if (arg == NULL) | |
9538 | mips_debug = 2; | |
9539 | else | |
9540 | mips_debug = atoi (arg); | |
9541 | /* When the MIPS assembler sees -g or -g2, it does not do | |
9542 | optimizations which limit full symbolic debugging. We take | |
9543 | that to be equivalent to -O0. */ | |
9544 | if (mips_debug == 2) | |
9545 | mips_optimize = 1; | |
9546 | break; | |
9547 | ||
9548 | case OPTION_MIPS1: | |
e7af610e | 9549 | mips_opts.isa = ISA_MIPS1; |
252b5132 RH |
9550 | break; |
9551 | ||
9552 | case OPTION_MIPS2: | |
e7af610e | 9553 | mips_opts.isa = ISA_MIPS2; |
252b5132 RH |
9554 | break; |
9555 | ||
9556 | case OPTION_MIPS3: | |
e7af610e | 9557 | mips_opts.isa = ISA_MIPS3; |
252b5132 RH |
9558 | break; |
9559 | ||
9560 | case OPTION_MIPS4: | |
e7af610e NC |
9561 | mips_opts.isa = ISA_MIPS4; |
9562 | break; | |
9563 | ||
84ea6cf2 NC |
9564 | case OPTION_MIPS5: |
9565 | mips_opts.isa = ISA_MIPS5; | |
9566 | break; | |
9567 | ||
e7af610e NC |
9568 | case OPTION_MIPS32: |
9569 | mips_opts.isa = ISA_MIPS32; | |
252b5132 RH |
9570 | break; |
9571 | ||
84ea6cf2 NC |
9572 | case OPTION_MIPS64: |
9573 | mips_opts.isa = ISA_MIPS64; | |
9574 | break; | |
9575 | ||
ec68c924 EC |
9576 | case OPTION_MTUNE: |
9577 | case OPTION_MARCH: | |
252b5132 RH |
9578 | case OPTION_MCPU: |
9579 | { | |
ec68c924 EC |
9580 | int cpu = CPU_UNKNOWN; |
9581 | ||
e7af610e | 9582 | /* Identify the processor type. */ |
ec68c924 | 9583 | if (strcasecmp (arg, "default") != 0) |
252b5132 | 9584 | { |
e7af610e | 9585 | const struct mips_cpu_info *ci; |
252b5132 | 9586 | |
e7af610e NC |
9587 | ci = mips_cpu_info_from_name (arg); |
9588 | if (ci == NULL || ci->is_isa) | |
ec68c924 EC |
9589 | { |
9590 | switch (c) | |
9591 | { | |
9592 | case OPTION_MTUNE: | |
9593 | as_fatal (_("invalid architecture -mtune=%s"), arg); | |
9594 | break; | |
9595 | case OPTION_MARCH: | |
9596 | as_fatal (_("invalid architecture -march=%s"), arg); | |
9597 | break; | |
9598 | case OPTION_MCPU: | |
9599 | as_fatal (_("invalid architecture -mcpu=%s"), arg); | |
9600 | break; | |
9601 | } | |
9602 | } | |
e7af610e | 9603 | else |
ec68c924 EC |
9604 | cpu = ci->cpu; |
9605 | } | |
9606 | ||
9607 | switch (c) | |
9608 | { | |
9609 | case OPTION_MTUNE: | |
6dce9e24 TS |
9610 | if (mips_tune != CPU_UNKNOWN && mips_tune != cpu) |
9611 | as_warn(_("A different -mtune= was already specified, is now " | |
9612 | "-mtune=%s"), arg); | |
ec68c924 EC |
9613 | mips_tune = cpu; |
9614 | break; | |
9615 | case OPTION_MARCH: | |
6dce9e24 TS |
9616 | if (mips_arch != CPU_UNKNOWN && mips_arch != cpu) |
9617 | as_warn(_("A different -march= was already specified, is now " | |
9618 | "-march=%s"), arg); | |
ec68c924 EC |
9619 | mips_arch = cpu; |
9620 | break; | |
9621 | case OPTION_MCPU: | |
6dce9e24 TS |
9622 | if (mips_cpu != CPU_UNKNOWN && mips_cpu != cpu) |
9623 | as_warn(_("A different -mcpu= was already specified, is now " | |
9624 | "-mcpu=%s"), arg); | |
ec68c924 | 9625 | mips_cpu = cpu; |
252b5132 RH |
9626 | } |
9627 | } | |
9628 | break; | |
9629 | ||
9630 | case OPTION_M4650: | |
6dce9e24 TS |
9631 | if ((mips_arch != CPU_UNKNOWN && mips_arch != CPU_R4650) |
9632 | || (mips_tune != CPU_UNKNOWN && mips_tune != CPU_R4650)) | |
9633 | as_warn(_("A different -march= or -mtune= was already specified, " | |
9634 | "is now -m4650")); | |
ec68c924 EC |
9635 | mips_arch = CPU_R4650; |
9636 | mips_tune = CPU_R4650; | |
252b5132 RH |
9637 | break; |
9638 | ||
9639 | case OPTION_NO_M4650: | |
9640 | break; | |
9641 | ||
9642 | case OPTION_M4010: | |
6dce9e24 TS |
9643 | if ((mips_arch != CPU_UNKNOWN && mips_arch != CPU_R4010) |
9644 | || (mips_tune != CPU_UNKNOWN && mips_tune != CPU_R4010)) | |
9645 | as_warn(_("A different -march= or -mtune= was already specified, " | |
9646 | "is now -m4010")); | |
ec68c924 EC |
9647 | mips_arch = CPU_R4010; |
9648 | mips_tune = CPU_R4010; | |
252b5132 RH |
9649 | break; |
9650 | ||
9651 | case OPTION_NO_M4010: | |
9652 | break; | |
9653 | ||
9654 | case OPTION_M4100: | |
6dce9e24 TS |
9655 | if ((mips_arch != CPU_UNKNOWN && mips_arch != CPU_VR4100) |
9656 | || (mips_tune != CPU_UNKNOWN && mips_tune != CPU_VR4100)) | |
9657 | as_warn(_("A different -march= or -mtune= was already specified, " | |
9658 | "is now -m4100")); | |
ec68c924 EC |
9659 | mips_arch = CPU_VR4100; |
9660 | mips_tune = CPU_VR4100; | |
252b5132 RH |
9661 | break; |
9662 | ||
9663 | case OPTION_NO_M4100: | |
9664 | break; | |
9665 | ||
252b5132 | 9666 | case OPTION_M3900: |
6dce9e24 TS |
9667 | if ((mips_arch != CPU_UNKNOWN && mips_arch != CPU_R3900) |
9668 | || (mips_tune != CPU_UNKNOWN && mips_tune != CPU_R3900)) | |
9669 | as_warn(_("A different -march= or -mtune= was already specified, " | |
9670 | "is now -m3900")); | |
ec68c924 EC |
9671 | mips_arch = CPU_R3900; |
9672 | mips_tune = CPU_R3900; | |
252b5132 | 9673 | break; |
bdaaa2e1 | 9674 | |
252b5132 RH |
9675 | case OPTION_NO_M3900: |
9676 | break; | |
9677 | ||
9678 | case OPTION_MIPS16: | |
9679 | mips_opts.mips16 = 1; | |
9680 | mips_no_prev_insn (false); | |
9681 | break; | |
9682 | ||
9683 | case OPTION_NO_MIPS16: | |
9684 | mips_opts.mips16 = 0; | |
9685 | mips_no_prev_insn (false); | |
9686 | break; | |
9687 | ||
9688 | case OPTION_MEMBEDDED_PIC: | |
9689 | mips_pic = EMBEDDED_PIC; | |
9690 | if (USE_GLOBAL_POINTER_OPT && g_switch_seen) | |
9691 | { | |
9692 | as_bad (_("-G may not be used with embedded PIC code")); | |
9693 | return 0; | |
9694 | } | |
9695 | g_switch_value = 0x7fffffff; | |
9696 | break; | |
9697 | ||
0f074f60 | 9698 | #ifdef OBJ_ELF |
252b5132 RH |
9699 | /* When generating ELF code, we permit -KPIC and -call_shared to |
9700 | select SVR4_PIC, and -non_shared to select no PIC. This is | |
9701 | intended to be compatible with Irix 5. */ | |
9702 | case OPTION_CALL_SHARED: | |
9703 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
9704 | { | |
9705 | as_bad (_("-call_shared is supported only for ELF format")); | |
9706 | return 0; | |
9707 | } | |
9708 | mips_pic = SVR4_PIC; | |
9709 | if (g_switch_seen && g_switch_value != 0) | |
9710 | { | |
9711 | as_bad (_("-G may not be used with SVR4 PIC code")); | |
9712 | return 0; | |
9713 | } | |
9714 | g_switch_value = 0; | |
9715 | break; | |
9716 | ||
9717 | case OPTION_NON_SHARED: | |
9718 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
9719 | { | |
9720 | as_bad (_("-non_shared is supported only for ELF format")); | |
9721 | return 0; | |
9722 | } | |
9723 | mips_pic = NO_PIC; | |
9724 | break; | |
9725 | ||
9726 | /* The -xgot option tells the assembler to use 32 offsets when | |
9727 | accessing the got in SVR4_PIC mode. It is for Irix | |
9728 | compatibility. */ | |
9729 | case OPTION_XGOT: | |
9730 | mips_big_got = 1; | |
9731 | break; | |
0f074f60 | 9732 | #endif /* OBJ_ELF */ |
252b5132 RH |
9733 | |
9734 | case 'G': | |
9735 | if (! USE_GLOBAL_POINTER_OPT) | |
9736 | { | |
9737 | as_bad (_("-G is not supported for this configuration")); | |
9738 | return 0; | |
9739 | } | |
9740 | else if (mips_pic == SVR4_PIC || mips_pic == EMBEDDED_PIC) | |
9741 | { | |
9742 | as_bad (_("-G may not be used with SVR4 or embedded PIC code")); | |
9743 | return 0; | |
9744 | } | |
9745 | else | |
9746 | g_switch_value = atoi (arg); | |
9747 | g_switch_seen = 1; | |
9748 | break; | |
9749 | ||
0f074f60 | 9750 | #ifdef OBJ_ELF |
252b5132 RH |
9751 | /* The -32 and -64 options tell the assembler to output the 32 |
9752 | bit or the 64 bit MIPS ELF format. */ | |
9753 | case OPTION_32: | |
e013f690 | 9754 | mips_abi = O32_ABI; |
252b5132 RH |
9755 | break; |
9756 | ||
e013f690 TS |
9757 | case OPTION_N32: |
9758 | mips_abi = N32_ABI; | |
9759 | break; | |
252b5132 | 9760 | |
e013f690 TS |
9761 | case OPTION_64: |
9762 | mips_abi = N64_ABI; | |
9763 | if (! support_64bit_objects()) | |
9764 | as_fatal (_("No compiled in support for 64 bit object file format")); | |
252b5132 RH |
9765 | break; |
9766 | ||
c97ef257 AH |
9767 | case OPTION_GP32: |
9768 | mips_gp32 = 1; | |
e013f690 TS |
9769 | if (mips_abi != O32_ABI) |
9770 | mips_abi = NO_ABI; | |
c97ef257 AH |
9771 | break; |
9772 | ||
9773 | case OPTION_GP64: | |
9774 | mips_gp32 = 0; | |
e013f690 TS |
9775 | if (mips_abi == O32_ABI) |
9776 | mips_abi = NO_ABI; | |
c97ef257 | 9777 | break; |
252b5132 | 9778 | |
ca4e0257 RS |
9779 | case OPTION_FP32: |
9780 | mips_fp32 = 1; | |
e013f690 TS |
9781 | if (mips_abi != O32_ABI) |
9782 | mips_abi = NO_ABI; | |
ca4e0257 RS |
9783 | break; |
9784 | ||
252b5132 | 9785 | case OPTION_MABI: |
e013f690 TS |
9786 | if (strcmp (arg, "32") == 0) |
9787 | mips_abi = O32_ABI; | |
9788 | else if (strcmp (arg, "o64") == 0) | |
9789 | mips_abi = O64_ABI; | |
9790 | else if (strcmp (arg, "n32") == 0) | |
9791 | mips_abi = N32_ABI; | |
9792 | else if (strcmp (arg, "64") == 0) | |
9793 | { | |
9794 | mips_abi = N64_ABI; | |
9795 | if (! support_64bit_objects()) | |
9796 | as_fatal (_("No compiled in support for 64 bit object file " | |
9797 | "format")); | |
9798 | } | |
9799 | else if (strcmp (arg, "eabi") == 0) | |
9800 | mips_abi = EABI_ABI; | |
9801 | else | |
9802 | mips_abi = NO_ABI; | |
252b5132 | 9803 | break; |
e013f690 | 9804 | #endif /* OBJ_ELF */ |
252b5132 | 9805 | |
6b76fefe CM |
9806 | case OPTION_M7000_HILO_FIX: |
9807 | mips_7000_hilo_fix = true; | |
9808 | break; | |
9809 | ||
9810 | case OPTION_NO_M7000_HILO_FIX: | |
9811 | mips_7000_hilo_fix = false; | |
9812 | break; | |
9813 | ||
252b5132 RH |
9814 | default: |
9815 | return 0; | |
9816 | } | |
9817 | ||
9818 | return 1; | |
9819 | } | |
9820 | ||
252b5132 RH |
9821 | static void |
9822 | show (stream, string, col_p, first_p) | |
9823 | FILE *stream; | |
9824 | char *string; | |
9825 | int *col_p; | |
9826 | int *first_p; | |
9827 | { | |
9828 | if (*first_p) | |
9829 | { | |
9830 | fprintf (stream, "%24s", ""); | |
9831 | *col_p = 24; | |
9832 | } | |
9833 | else | |
9834 | { | |
9835 | fprintf (stream, ", "); | |
9836 | *col_p += 2; | |
9837 | } | |
9838 | ||
9839 | if (*col_p + strlen (string) > 72) | |
9840 | { | |
9841 | fprintf (stream, "\n%24s", ""); | |
9842 | *col_p = 24; | |
9843 | } | |
9844 | ||
9845 | fprintf (stream, "%s", string); | |
9846 | *col_p += strlen (string); | |
9847 | ||
9848 | *first_p = 0; | |
9849 | } | |
9850 | ||
252b5132 RH |
9851 | void |
9852 | md_show_usage (stream) | |
9853 | FILE *stream; | |
9854 | { | |
9855 | int column, first; | |
9856 | ||
beae10d5 | 9857 | fprintf (stream, _("\ |
252b5132 RH |
9858 | MIPS options:\n\ |
9859 | -membedded-pic generate embedded position independent code\n\ | |
9860 | -EB generate big endian output\n\ | |
9861 | -EL generate little endian output\n\ | |
9a41af64 | 9862 | -g, -g2 do not remove unneeded NOPs or swap branches\n\ |
252b5132 RH |
9863 | -G NUM allow referencing objects up to NUM bytes\n\ |
9864 | implicitly with the gp register [default 8]\n")); | |
beae10d5 | 9865 | fprintf (stream, _("\ |
252b5132 RH |
9866 | -mips1 generate MIPS ISA I instructions\n\ |
9867 | -mips2 generate MIPS ISA II instructions\n\ | |
9868 | -mips3 generate MIPS ISA III instructions\n\ | |
9869 | -mips4 generate MIPS ISA IV instructions\n\ | |
84ea6cf2 | 9870 | -mips5 generate MIPS ISA V instructions\n\ |
e7af610e | 9871 | -mips32 generate MIPS32 ISA instructions\n\ |
84ea6cf2 | 9872 | -mips64 generate MIPS64 ISA instructions\n\ |
ec68c924 | 9873 | -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n")); |
252b5132 RH |
9874 | |
9875 | first = 1; | |
9876 | ||
9877 | show (stream, "2000", &column, &first); | |
9878 | show (stream, "3000", &column, &first); | |
9879 | show (stream, "3900", &column, &first); | |
9880 | show (stream, "4000", &column, &first); | |
9881 | show (stream, "4010", &column, &first); | |
9882 | show (stream, "4100", &column, &first); | |
9883 | show (stream, "4111", &column, &first); | |
9884 | show (stream, "4300", &column, &first); | |
9885 | show (stream, "4400", &column, &first); | |
9886 | show (stream, "4600", &column, &first); | |
9887 | show (stream, "4650", &column, &first); | |
9888 | show (stream, "5000", &column, &first); | |
18ae5d72 EC |
9889 | show (stream, "5200", &column, &first); |
9890 | show (stream, "5230", &column, &first); | |
9891 | show (stream, "5231", &column, &first); | |
9892 | show (stream, "5261", &column, &first); | |
9893 | show (stream, "5721", &column, &first); | |
252b5132 RH |
9894 | show (stream, "6000", &column, &first); |
9895 | show (stream, "8000", &column, &first); | |
9896 | show (stream, "10000", &column, &first); | |
d1cf510e | 9897 | show (stream, "12000", &column, &first); |
c6c98b38 | 9898 | show (stream, "sb-1", &column, &first); |
252b5132 RH |
9899 | fputc ('\n', stream); |
9900 | ||
9901 | fprintf (stream, _("\ | |
ec68c924 | 9902 | -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\ |
252b5132 RH |
9903 | -no-mCPU don't generate code specific to CPU.\n\ |
9904 | For -mCPU and -no-mCPU, CPU must be one of:\n")); | |
9905 | ||
9906 | first = 1; | |
9907 | ||
9908 | show (stream, "3900", &column, &first); | |
9909 | show (stream, "4010", &column, &first); | |
9910 | show (stream, "4100", &column, &first); | |
9911 | show (stream, "4650", &column, &first); | |
9912 | fputc ('\n', stream); | |
9913 | ||
beae10d5 | 9914 | fprintf (stream, _("\ |
252b5132 RH |
9915 | -mips16 generate mips16 instructions\n\ |
9916 | -no-mips16 do not generate mips16 instructions\n")); | |
beae10d5 | 9917 | fprintf (stream, _("\ |
ca4e0257 RS |
9918 | -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\ |
9919 | -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\ | |
252b5132 RH |
9920 | -O0 remove unneeded NOPs, do not swap branches\n\ |
9921 | -O remove unneeded NOPs and swap branches\n\ | |
63486801 | 9922 | -n warn about NOPs generated from macros\n\ |
119d663a | 9923 | --[no-]construct-floats [dis]allow floating point values to be constructed\n\ |
252b5132 RH |
9924 | --trap, --no-break trap exception on div by 0 and mult overflow\n\ |
9925 | --break, --no-trap break exception on div by 0 and mult overflow\n")); | |
9926 | #ifdef OBJ_ELF | |
beae10d5 | 9927 | fprintf (stream, _("\ |
252b5132 RH |
9928 | -KPIC, -call_shared generate SVR4 position independent code\n\ |
9929 | -non_shared do not generate position independent code\n\ | |
9930 | -xgot assume a 32 bit GOT\n\ | |
e013f690 TS |
9931 | -32 create o32 ABI object file (default)\n\ |
9932 | -n32 create n32 ABI object file\n\ | |
9933 | -64 create 64 ABI object file\n")); | |
252b5132 RH |
9934 | #endif |
9935 | } | |
9936 | \f | |
9937 | void | |
9938 | mips_init_after_args () | |
9939 | { | |
9940 | /* initialize opcodes */ | |
9941 | bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes; | |
beae10d5 | 9942 | mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes; |
252b5132 RH |
9943 | } |
9944 | ||
9945 | long | |
9946 | md_pcrel_from (fixP) | |
9947 | fixS *fixP; | |
9948 | { | |
9949 | if (OUTPUT_FLAVOR != bfd_target_aout_flavour | |
9950 | && fixP->fx_addsy != (symbolS *) NULL | |
9951 | && ! S_IS_DEFINED (fixP->fx_addsy)) | |
9952 | { | |
6478892d TS |
9953 | /* This makes a branch to an undefined symbol be a branch to the |
9954 | current location. */ | |
cb56d3d3 | 9955 | if (mips_pic == EMBEDDED_PIC) |
6478892d | 9956 | return 4; |
cb56d3d3 | 9957 | else |
6478892d | 9958 | return 1; |
252b5132 RH |
9959 | } |
9960 | ||
9961 | /* return the address of the delay slot */ | |
9962 | return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address; | |
9963 | } | |
9964 | ||
252b5132 RH |
9965 | /* This is called before the symbol table is processed. In order to |
9966 | work with gcc when using mips-tfile, we must keep all local labels. | |
9967 | However, in other cases, we want to discard them. If we were | |
9968 | called with -g, but we didn't see any debugging information, it may | |
9969 | mean that gcc is smuggling debugging information through to | |
9970 | mips-tfile, in which case we must generate all local labels. */ | |
9971 | ||
9972 | void | |
9973 | mips_frob_file_before_adjust () | |
9974 | { | |
9975 | #ifndef NO_ECOFF_DEBUGGING | |
9976 | if (ECOFF_DEBUGGING | |
9977 | && mips_debug != 0 | |
9978 | && ! ecoff_debugging_seen) | |
9979 | flag_keep_locals = 1; | |
9980 | #endif | |
9981 | } | |
9982 | ||
9983 | /* Sort any unmatched HI16_S relocs so that they immediately precede | |
9984 | the corresponding LO reloc. This is called before md_apply_fix and | |
9985 | tc_gen_reloc. Unmatched HI16_S relocs can only be generated by | |
9986 | explicit use of the %hi modifier. */ | |
9987 | ||
9988 | void | |
9989 | mips_frob_file () | |
9990 | { | |
9991 | struct mips_hi_fixup *l; | |
9992 | ||
9993 | for (l = mips_hi_fixup_list; l != NULL; l = l->next) | |
9994 | { | |
9995 | segment_info_type *seginfo; | |
9996 | int pass; | |
9997 | ||
9998 | assert (l->fixp->fx_r_type == BFD_RELOC_HI16_S); | |
9999 | ||
10000 | /* Check quickly whether the next fixup happens to be a matching | |
10001 | %lo. */ | |
10002 | if (l->fixp->fx_next != NULL | |
10003 | && l->fixp->fx_next->fx_r_type == BFD_RELOC_LO16 | |
10004 | && l->fixp->fx_addsy == l->fixp->fx_next->fx_addsy | |
10005 | && l->fixp->fx_offset == l->fixp->fx_next->fx_offset) | |
10006 | continue; | |
10007 | ||
10008 | /* Look through the fixups for this segment for a matching %lo. | |
10009 | When we find one, move the %hi just in front of it. We do | |
10010 | this in two passes. In the first pass, we try to find a | |
10011 | unique %lo. In the second pass, we permit multiple %hi | |
10012 | relocs for a single %lo (this is a GNU extension). */ | |
10013 | seginfo = seg_info (l->seg); | |
10014 | for (pass = 0; pass < 2; pass++) | |
10015 | { | |
10016 | fixS *f, *prev; | |
10017 | ||
10018 | prev = NULL; | |
10019 | for (f = seginfo->fix_root; f != NULL; f = f->fx_next) | |
10020 | { | |
10021 | /* Check whether this is a %lo fixup which matches l->fixp. */ | |
10022 | if (f->fx_r_type == BFD_RELOC_LO16 | |
10023 | && f->fx_addsy == l->fixp->fx_addsy | |
10024 | && f->fx_offset == l->fixp->fx_offset | |
10025 | && (pass == 1 | |
10026 | || prev == NULL | |
10027 | || prev->fx_r_type != BFD_RELOC_HI16_S | |
10028 | || prev->fx_addsy != f->fx_addsy | |
10029 | || prev->fx_offset != f->fx_offset)) | |
10030 | { | |
10031 | fixS **pf; | |
10032 | ||
10033 | /* Move l->fixp before f. */ | |
10034 | for (pf = &seginfo->fix_root; | |
10035 | *pf != l->fixp; | |
10036 | pf = &(*pf)->fx_next) | |
10037 | assert (*pf != NULL); | |
10038 | ||
10039 | *pf = l->fixp->fx_next; | |
10040 | ||
10041 | l->fixp->fx_next = f; | |
10042 | if (prev == NULL) | |
10043 | seginfo->fix_root = l->fixp; | |
10044 | else | |
10045 | prev->fx_next = l->fixp; | |
10046 | ||
10047 | break; | |
10048 | } | |
10049 | ||
10050 | prev = f; | |
10051 | } | |
10052 | ||
10053 | if (f != NULL) | |
10054 | break; | |
10055 | ||
10056 | #if 0 /* GCC code motion plus incomplete dead code elimination | |
10057 | can leave a %hi without a %lo. */ | |
10058 | if (pass == 1) | |
10059 | as_warn_where (l->fixp->fx_file, l->fixp->fx_line, | |
10060 | _("Unmatched %%hi reloc")); | |
10061 | #endif | |
10062 | } | |
10063 | } | |
10064 | } | |
10065 | ||
10066 | /* When generating embedded PIC code we need to use a special | |
10067 | relocation to represent the difference of two symbols in the .text | |
10068 | section (switch tables use a difference of this sort). See | |
10069 | include/coff/mips.h for details. This macro checks whether this | |
10070 | fixup requires the special reloc. */ | |
10071 | #define SWITCH_TABLE(fixp) \ | |
10072 | ((fixp)->fx_r_type == BFD_RELOC_32 \ | |
bb2d6cd7 | 10073 | && OUTPUT_FLAVOR != bfd_target_elf_flavour \ |
252b5132 RH |
10074 | && (fixp)->fx_addsy != NULL \ |
10075 | && (fixp)->fx_subsy != NULL \ | |
10076 | && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \ | |
10077 | && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section) | |
10078 | ||
10079 | /* When generating embedded PIC code we must keep all PC relative | |
10080 | relocations, in case the linker has to relax a call. We also need | |
f6688943 TS |
10081 | to keep relocations for switch table entries. |
10082 | ||
10083 | We may have combined relocations without symbols in the N32/N64 ABI. | |
10084 | We have to prevent gas from dropping them. */ | |
252b5132 | 10085 | |
252b5132 RH |
10086 | int |
10087 | mips_force_relocation (fixp) | |
10088 | fixS *fixp; | |
10089 | { | |
10090 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT | |
10091 | || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
10092 | return 1; | |
10093 | ||
f6688943 TS |
10094 | if (HAVE_NEWABI |
10095 | && S_GET_SEGMENT (fixp->fx_addsy) == bfd_abs_section_ptr | |
10096 | && (fixp->fx_r_type == BFD_RELOC_MIPS_SUB | |
10097 | || fixp->fx_r_type == BFD_RELOC_HI16_S | |
10098 | || fixp->fx_r_type == BFD_RELOC_LO16)) | |
10099 | return 1; | |
10100 | ||
6478892d TS |
10101 | if (HAVE_NEWABI |
10102 | && S_GET_SEGMENT (fixp->fx_addsy) == bfd_abs_section_ptr | |
10103 | && (fixp->fx_r_type == BFD_RELOC_MIPS_SUB | |
10104 | || fixp->fx_r_type == BFD_RELOC_HI16_S | |
10105 | || fixp->fx_r_type == BFD_RELOC_LO16)) | |
10106 | return 1; | |
10107 | ||
252b5132 RH |
10108 | return (mips_pic == EMBEDDED_PIC |
10109 | && (fixp->fx_pcrel | |
10110 | || SWITCH_TABLE (fixp) | |
10111 | || fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S | |
10112 | || fixp->fx_r_type == BFD_RELOC_PCREL_LO16)); | |
10113 | } | |
10114 | ||
10115 | /* Apply a fixup to the object file. */ | |
10116 | ||
10117 | int | |
10118 | md_apply_fix (fixP, valueP) | |
10119 | fixS *fixP; | |
10120 | valueT *valueP; | |
10121 | { | |
10122 | unsigned char *buf; | |
98aa84af AM |
10123 | long insn; |
10124 | valueT value; | |
252b5132 RH |
10125 | |
10126 | assert (fixP->fx_size == 4 | |
10127 | || fixP->fx_r_type == BFD_RELOC_16 | |
f6688943 TS |
10128 | || fixP->fx_r_type == BFD_RELOC_32 |
10129 | || fixP->fx_r_type == BFD_RELOC_MIPS_JMP | |
10130 | || fixP->fx_r_type == BFD_RELOC_HI16_S | |
10131 | || fixP->fx_r_type == BFD_RELOC_LO16 | |
10132 | || fixP->fx_r_type == BFD_RELOC_GPREL16 | |
10133 | || fixP->fx_r_type == BFD_RELOC_MIPS_LITERAL | |
10134 | || fixP->fx_r_type == BFD_RELOC_GPREL32 | |
252b5132 | 10135 | || fixP->fx_r_type == BFD_RELOC_64 |
f6688943 TS |
10136 | || fixP->fx_r_type == BFD_RELOC_CTOR |
10137 | || fixP->fx_r_type == BFD_RELOC_MIPS_SUB | |
10138 | || fixP->fx_r_type == BFD_RELOC_MIPS_HIGHEST | |
10139 | || fixP->fx_r_type == BFD_RELOC_MIPS_HIGHER | |
10140 | || fixP->fx_r_type == BFD_RELOC_MIPS_SCN_DISP | |
10141 | || fixP->fx_r_type == BFD_RELOC_MIPS_REL16 | |
10142 | || fixP->fx_r_type == BFD_RELOC_MIPS_RELGOT | |
252b5132 RH |
10143 | || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
10144 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY); | |
10145 | ||
10146 | value = *valueP; | |
10147 | ||
10148 | /* If we aren't adjusting this fixup to be against the section | |
10149 | symbol, we need to adjust the value. */ | |
10150 | #ifdef OBJ_ELF | |
10151 | if (fixP->fx_addsy != NULL && OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
bb2d6cd7 | 10152 | { |
98aa84af | 10153 | if (S_GET_OTHER (fixP->fx_addsy) == STO_MIPS16 |
ea4ff978 L |
10154 | || ((S_IS_WEAK (fixP->fx_addsy) |
10155 | || S_IS_EXTERN (fixP->fx_addsy)) | |
10156 | && !S_IS_COMMON (fixP->fx_addsy)) | |
98aa84af AM |
10157 | || (symbol_used_in_reloc_p (fixP->fx_addsy) |
10158 | && (((bfd_get_section_flags (stdoutput, | |
10159 | S_GET_SEGMENT (fixP->fx_addsy)) | |
10160 | & SEC_LINK_ONCE) != 0) | |
10161 | || !strncmp (segment_name (S_GET_SEGMENT (fixP->fx_addsy)), | |
10162 | ".gnu.linkonce", | |
10163 | sizeof (".gnu.linkonce") - 1)))) | |
252b5132 | 10164 | |
98aa84af AM |
10165 | { |
10166 | valueT symval = S_GET_VALUE (fixP->fx_addsy); | |
10167 | value -= symval; | |
236bd878 RS |
10168 | if (value != 0 |
10169 | && ! fixP->fx_pcrel | |
10170 | && fixP->fx_r_type != BFD_RELOC_MIPS_GPREL) | |
98aa84af AM |
10171 | { |
10172 | /* In this case, the bfd_install_relocation routine will | |
10173 | incorrectly add the symbol value back in. We just want | |
7461da6e | 10174 | the addend to appear in the object file. */ |
98aa84af | 10175 | value -= symval; |
7461da6e RS |
10176 | |
10177 | /* Make sure the addend is still non-zero. If it became zero | |
10178 | after the last operation, set it to a spurious value and | |
10179 | subtract the same value from the object file's contents. */ | |
10180 | if (value == 0) | |
10181 | { | |
10182 | value = 8; | |
10183 | ||
10184 | /* The in-place addends for LO16 relocations are signed; | |
10185 | leave the matching HI16 in-place addends as zero. */ | |
10186 | if (fixP->fx_r_type != BFD_RELOC_HI16_S) | |
10187 | { | |
10188 | reloc_howto_type *howto; | |
10189 | bfd_vma contents, mask, field; | |
10190 | ||
10191 | howto = bfd_reloc_type_lookup (stdoutput, | |
10192 | fixP->fx_r_type); | |
10193 | ||
10194 | contents = bfd_get_bits (fixP->fx_frag->fr_literal | |
10195 | + fixP->fx_where, | |
10196 | fixP->fx_size * 8, | |
10197 | target_big_endian); | |
10198 | ||
10199 | /* MASK has bits set where the relocation should go. | |
10200 | FIELD is -value, shifted into the appropriate place | |
10201 | for this relocation. */ | |
10202 | mask = 1 << (howto->bitsize - 1); | |
10203 | mask = (((mask - 1) << 1) | 1) << howto->bitpos; | |
10204 | field = (-value >> howto->rightshift) << howto->bitpos; | |
10205 | ||
10206 | bfd_put_bits ((field & mask) | (contents & ~mask), | |
10207 | fixP->fx_frag->fr_literal + fixP->fx_where, | |
10208 | fixP->fx_size * 8, | |
10209 | target_big_endian); | |
10210 | } | |
10211 | } | |
98aa84af AM |
10212 | } |
10213 | } | |
252b5132 | 10214 | |
bb2d6cd7 GK |
10215 | /* This code was generated using trial and error and so is |
10216 | fragile and not trustworthy. If you change it, you should | |
10217 | rerun the elf-rel, elf-rel2, and empic testcases and ensure | |
10218 | they still pass. */ | |
10219 | if (fixP->fx_pcrel || fixP->fx_subsy != NULL) | |
10220 | { | |
10221 | value += fixP->fx_frag->fr_address + fixP->fx_where; | |
10222 | ||
10223 | /* BFD's REL handling, for MIPS, is _very_ weird. | |
10224 | This gives the right results, but it can't possibly | |
10225 | be the way things are supposed to work. */ | |
cb56d3d3 TS |
10226 | if ((fixP->fx_r_type != BFD_RELOC_16_PCREL |
10227 | && fixP->fx_r_type != BFD_RELOC_16_PCREL_S2) | |
bb2d6cd7 GK |
10228 | || S_GET_SEGMENT (fixP->fx_addsy) != undefined_section) |
10229 | value += fixP->fx_frag->fr_address + fixP->fx_where; | |
10230 | } | |
10231 | } | |
10232 | #endif | |
252b5132 RH |
10233 | |
10234 | fixP->fx_addnumber = value; /* Remember value for tc_gen_reloc */ | |
10235 | ||
10236 | if (fixP->fx_addsy == NULL && ! fixP->fx_pcrel) | |
10237 | fixP->fx_done = 1; | |
10238 | ||
10239 | switch (fixP->fx_r_type) | |
10240 | { | |
10241 | case BFD_RELOC_MIPS_JMP: | |
e369bcce TS |
10242 | case BFD_RELOC_MIPS_SHIFT5: |
10243 | case BFD_RELOC_MIPS_SHIFT6: | |
10244 | case BFD_RELOC_MIPS_GOT_DISP: | |
10245 | case BFD_RELOC_MIPS_GOT_PAGE: | |
10246 | case BFD_RELOC_MIPS_GOT_OFST: | |
10247 | case BFD_RELOC_MIPS_SUB: | |
10248 | case BFD_RELOC_MIPS_INSERT_A: | |
10249 | case BFD_RELOC_MIPS_INSERT_B: | |
10250 | case BFD_RELOC_MIPS_DELETE: | |
10251 | case BFD_RELOC_MIPS_HIGHEST: | |
10252 | case BFD_RELOC_MIPS_HIGHER: | |
10253 | case BFD_RELOC_MIPS_SCN_DISP: | |
10254 | case BFD_RELOC_MIPS_REL16: | |
10255 | case BFD_RELOC_MIPS_RELGOT: | |
10256 | case BFD_RELOC_MIPS_JALR: | |
252b5132 RH |
10257 | case BFD_RELOC_HI16: |
10258 | case BFD_RELOC_HI16_S: | |
10259 | case BFD_RELOC_MIPS_GPREL: | |
10260 | case BFD_RELOC_MIPS_LITERAL: | |
10261 | case BFD_RELOC_MIPS_CALL16: | |
10262 | case BFD_RELOC_MIPS_GOT16: | |
10263 | case BFD_RELOC_MIPS_GPREL32: | |
10264 | case BFD_RELOC_MIPS_GOT_HI16: | |
10265 | case BFD_RELOC_MIPS_GOT_LO16: | |
10266 | case BFD_RELOC_MIPS_CALL_HI16: | |
10267 | case BFD_RELOC_MIPS_CALL_LO16: | |
10268 | case BFD_RELOC_MIPS16_GPREL: | |
10269 | if (fixP->fx_pcrel) | |
10270 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
10271 | _("Invalid PC relative reloc")); | |
10272 | /* Nothing needed to do. The value comes from the reloc entry */ | |
10273 | break; | |
10274 | ||
10275 | case BFD_RELOC_MIPS16_JMP: | |
10276 | /* We currently always generate a reloc against a symbol, which | |
10277 | means that we don't want an addend even if the symbol is | |
10278 | defined. */ | |
10279 | fixP->fx_addnumber = 0; | |
10280 | break; | |
10281 | ||
10282 | case BFD_RELOC_PCREL_HI16_S: | |
10283 | /* The addend for this is tricky if it is internal, so we just | |
10284 | do everything here rather than in bfd_install_relocation. */ | |
bdaaa2e1 | 10285 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour |
bb2d6cd7 GK |
10286 | && !fixP->fx_done |
10287 | && value != 0) | |
10288 | break; | |
10289 | if (fixP->fx_addsy | |
10290 | && (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_SECTION_SYM) == 0) | |
252b5132 RH |
10291 | { |
10292 | /* For an external symbol adjust by the address to make it | |
10293 | pcrel_offset. We use the address of the RELLO reloc | |
10294 | which follows this one. */ | |
10295 | value += (fixP->fx_next->fx_frag->fr_address | |
10296 | + fixP->fx_next->fx_where); | |
10297 | } | |
e7d556df | 10298 | value = ((value + 0x8000) >> 16) & 0xffff; |
252b5132 RH |
10299 | buf = (unsigned char *) fixP->fx_frag->fr_literal + fixP->fx_where; |
10300 | if (target_big_endian) | |
10301 | buf += 2; | |
10302 | md_number_to_chars (buf, value, 2); | |
10303 | break; | |
10304 | ||
10305 | case BFD_RELOC_PCREL_LO16: | |
10306 | /* The addend for this is tricky if it is internal, so we just | |
10307 | do everything here rather than in bfd_install_relocation. */ | |
bdaaa2e1 | 10308 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour |
bb2d6cd7 GK |
10309 | && !fixP->fx_done |
10310 | && value != 0) | |
10311 | break; | |
10312 | if (fixP->fx_addsy | |
10313 | && (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_SECTION_SYM) == 0) | |
252b5132 RH |
10314 | value += fixP->fx_frag->fr_address + fixP->fx_where; |
10315 | buf = (unsigned char *) fixP->fx_frag->fr_literal + fixP->fx_where; | |
10316 | if (target_big_endian) | |
10317 | buf += 2; | |
10318 | md_number_to_chars (buf, value, 2); | |
10319 | break; | |
10320 | ||
10321 | case BFD_RELOC_64: | |
10322 | /* This is handled like BFD_RELOC_32, but we output a sign | |
10323 | extended value if we are only 32 bits. */ | |
10324 | if (fixP->fx_done | |
10325 | || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP))) | |
10326 | { | |
10327 | if (8 <= sizeof (valueT)) | |
10328 | md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where, | |
10329 | value, 8); | |
10330 | else | |
10331 | { | |
10332 | long w1, w2; | |
10333 | long hiv; | |
10334 | ||
10335 | w1 = w2 = fixP->fx_where; | |
10336 | if (target_big_endian) | |
10337 | w1 += 4; | |
10338 | else | |
10339 | w2 += 4; | |
10340 | md_number_to_chars (fixP->fx_frag->fr_literal + w1, value, 4); | |
10341 | if ((value & 0x80000000) != 0) | |
10342 | hiv = 0xffffffff; | |
10343 | else | |
10344 | hiv = 0; | |
10345 | md_number_to_chars (fixP->fx_frag->fr_literal + w2, hiv, 4); | |
10346 | } | |
10347 | } | |
10348 | break; | |
10349 | ||
056350c6 | 10350 | case BFD_RELOC_RVA: |
252b5132 RH |
10351 | case BFD_RELOC_32: |
10352 | /* If we are deleting this reloc entry, we must fill in the | |
10353 | value now. This can happen if we have a .word which is not | |
10354 | resolved when it appears but is later defined. We also need | |
10355 | to fill in the value if this is an embedded PIC switch table | |
10356 | entry. */ | |
10357 | if (fixP->fx_done | |
10358 | || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP))) | |
10359 | md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where, | |
10360 | value, 4); | |
10361 | break; | |
10362 | ||
10363 | case BFD_RELOC_16: | |
10364 | /* If we are deleting this reloc entry, we must fill in the | |
10365 | value now. */ | |
10366 | assert (fixP->fx_size == 2); | |
10367 | if (fixP->fx_done) | |
10368 | md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where, | |
10369 | value, 2); | |
10370 | break; | |
10371 | ||
10372 | case BFD_RELOC_LO16: | |
10373 | /* When handling an embedded PIC switch statement, we can wind | |
10374 | up deleting a LO16 reloc. See the 'o' case in mips_ip. */ | |
10375 | if (fixP->fx_done) | |
10376 | { | |
98aa84af | 10377 | if (value + 0x8000 > 0xffff) |
252b5132 RH |
10378 | as_bad_where (fixP->fx_file, fixP->fx_line, |
10379 | _("relocation overflow")); | |
10380 | buf = (unsigned char *) fixP->fx_frag->fr_literal + fixP->fx_where; | |
10381 | if (target_big_endian) | |
10382 | buf += 2; | |
10383 | md_number_to_chars (buf, value, 2); | |
10384 | } | |
10385 | break; | |
10386 | ||
10387 | case BFD_RELOC_16_PCREL_S2: | |
cb56d3d3 TS |
10388 | if ((value & 0x3) != 0) |
10389 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
10390 | _("Branch to odd address (%lx)"), (long) value); | |
10391 | ||
10392 | /* Fall through. */ | |
10393 | ||
10394 | case BFD_RELOC_16_PCREL: | |
252b5132 RH |
10395 | /* |
10396 | * We need to save the bits in the instruction since fixup_segment() | |
10397 | * might be deleting the relocation entry (i.e., a branch within | |
10398 | * the current segment). | |
10399 | */ | |
bb2d6cd7 GK |
10400 | if (!fixP->fx_done && value != 0) |
10401 | break; | |
10402 | /* If 'value' is zero, the remaining reloc code won't actually | |
10403 | do the store, so it must be done here. This is probably | |
10404 | a bug somewhere. */ | |
10405 | if (!fixP->fx_done) | |
10406 | value -= fixP->fx_frag->fr_address + fixP->fx_where; | |
bdaaa2e1 | 10407 | |
98aa84af | 10408 | value = (offsetT) value >> 2; |
252b5132 RH |
10409 | |
10410 | /* update old instruction data */ | |
10411 | buf = (unsigned char *) (fixP->fx_where + fixP->fx_frag->fr_literal); | |
10412 | if (target_big_endian) | |
10413 | insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3]; | |
10414 | else | |
10415 | insn = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0]; | |
10416 | ||
98aa84af | 10417 | if (value + 0x8000 <= 0xffff) |
252b5132 RH |
10418 | insn |= value & 0xffff; |
10419 | else | |
10420 | { | |
10421 | /* The branch offset is too large. If this is an | |
10422 | unconditional branch, and we are not generating PIC code, | |
10423 | we can convert it to an absolute jump instruction. */ | |
10424 | if (mips_pic == NO_PIC | |
10425 | && fixP->fx_done | |
10426 | && fixP->fx_frag->fr_address >= text_section->vma | |
10427 | && (fixP->fx_frag->fr_address | |
10428 | < text_section->vma + text_section->_raw_size) | |
10429 | && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */ | |
10430 | || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */ | |
10431 | || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */ | |
10432 | { | |
10433 | if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */ | |
10434 | insn = 0x0c000000; /* jal */ | |
10435 | else | |
10436 | insn = 0x08000000; /* j */ | |
10437 | fixP->fx_r_type = BFD_RELOC_MIPS_JMP; | |
10438 | fixP->fx_done = 0; | |
10439 | fixP->fx_addsy = section_symbol (text_section); | |
10440 | fixP->fx_addnumber = (value << 2) + md_pcrel_from (fixP); | |
10441 | } | |
10442 | else | |
10443 | { | |
10444 | /* FIXME. It would be possible in principle to handle | |
10445 | conditional branches which overflow. They could be | |
10446 | transformed into a branch around a jump. This would | |
10447 | require setting up variant frags for each different | |
10448 | branch type. The native MIPS assembler attempts to | |
10449 | handle these cases, but it appears to do it | |
10450 | incorrectly. */ | |
10451 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
10452 | _("Branch out of range")); | |
10453 | } | |
10454 | } | |
10455 | ||
10456 | md_number_to_chars ((char *) buf, (valueT) insn, 4); | |
10457 | break; | |
10458 | ||
10459 | case BFD_RELOC_VTABLE_INHERIT: | |
10460 | fixP->fx_done = 0; | |
10461 | if (fixP->fx_addsy | |
10462 | && !S_IS_DEFINED (fixP->fx_addsy) | |
10463 | && !S_IS_WEAK (fixP->fx_addsy)) | |
10464 | S_SET_WEAK (fixP->fx_addsy); | |
10465 | break; | |
10466 | ||
10467 | case BFD_RELOC_VTABLE_ENTRY: | |
10468 | fixP->fx_done = 0; | |
10469 | break; | |
10470 | ||
10471 | default: | |
10472 | internalError (); | |
10473 | } | |
10474 | ||
10475 | return 1; | |
10476 | } | |
10477 | ||
10478 | #if 0 | |
10479 | void | |
10480 | printInsn (oc) | |
10481 | unsigned long oc; | |
10482 | { | |
10483 | const struct mips_opcode *p; | |
10484 | int treg, sreg, dreg, shamt; | |
10485 | short imm; | |
10486 | const char *args; | |
10487 | int i; | |
10488 | ||
10489 | for (i = 0; i < NUMOPCODES; ++i) | |
10490 | { | |
10491 | p = &mips_opcodes[i]; | |
10492 | if (((oc & p->mask) == p->match) && (p->pinfo != INSN_MACRO)) | |
10493 | { | |
10494 | printf ("%08lx %s\t", oc, p->name); | |
10495 | treg = (oc >> 16) & 0x1f; | |
10496 | sreg = (oc >> 21) & 0x1f; | |
10497 | dreg = (oc >> 11) & 0x1f; | |
10498 | shamt = (oc >> 6) & 0x1f; | |
10499 | imm = oc; | |
10500 | for (args = p->args;; ++args) | |
10501 | { | |
10502 | switch (*args) | |
10503 | { | |
10504 | case '\0': | |
10505 | printf ("\n"); | |
10506 | break; | |
10507 | ||
10508 | case ',': | |
10509 | case '(': | |
10510 | case ')': | |
10511 | printf ("%c", *args); | |
10512 | continue; | |
10513 | ||
10514 | case 'r': | |
10515 | assert (treg == sreg); | |
10516 | printf ("$%d,$%d", treg, sreg); | |
10517 | continue; | |
10518 | ||
10519 | case 'd': | |
10520 | case 'G': | |
10521 | printf ("$%d", dreg); | |
10522 | continue; | |
10523 | ||
10524 | case 't': | |
10525 | case 'E': | |
10526 | printf ("$%d", treg); | |
10527 | continue; | |
10528 | ||
10529 | case 'k': | |
10530 | printf ("0x%x", treg); | |
10531 | continue; | |
10532 | ||
10533 | case 'b': | |
10534 | case 's': | |
10535 | printf ("$%d", sreg); | |
10536 | continue; | |
10537 | ||
10538 | case 'a': | |
10539 | printf ("0x%08lx", oc & 0x1ffffff); | |
10540 | continue; | |
10541 | ||
10542 | case 'i': | |
10543 | case 'j': | |
10544 | case 'o': | |
10545 | case 'u': | |
10546 | printf ("%d", imm); | |
10547 | continue; | |
10548 | ||
10549 | case '<': | |
10550 | case '>': | |
10551 | printf ("$%d", shamt); | |
10552 | continue; | |
10553 | ||
10554 | default: | |
10555 | internalError (); | |
10556 | } | |
10557 | break; | |
10558 | } | |
10559 | return; | |
10560 | } | |
10561 | } | |
10562 | printf (_("%08lx UNDEFINED\n"), oc); | |
10563 | } | |
10564 | #endif | |
10565 | ||
10566 | static symbolS * | |
10567 | get_symbol () | |
10568 | { | |
10569 | int c; | |
10570 | char *name; | |
10571 | symbolS *p; | |
10572 | ||
10573 | name = input_line_pointer; | |
10574 | c = get_symbol_end (); | |
10575 | p = (symbolS *) symbol_find_or_make (name); | |
10576 | *input_line_pointer = c; | |
10577 | return p; | |
10578 | } | |
10579 | ||
10580 | /* Align the current frag to a given power of two. The MIPS assembler | |
10581 | also automatically adjusts any preceding label. */ | |
10582 | ||
10583 | static void | |
10584 | mips_align (to, fill, label) | |
10585 | int to; | |
10586 | int fill; | |
10587 | symbolS *label; | |
10588 | { | |
10589 | mips_emit_delays (false); | |
10590 | frag_align (to, fill, 0); | |
10591 | record_alignment (now_seg, to); | |
10592 | if (label != NULL) | |
10593 | { | |
10594 | assert (S_GET_SEGMENT (label) == now_seg); | |
49309057 | 10595 | symbol_set_frag (label, frag_now); |
252b5132 RH |
10596 | S_SET_VALUE (label, (valueT) frag_now_fix ()); |
10597 | } | |
10598 | } | |
10599 | ||
10600 | /* Align to a given power of two. .align 0 turns off the automatic | |
10601 | alignment used by the data creating pseudo-ops. */ | |
10602 | ||
10603 | static void | |
10604 | s_align (x) | |
43841e91 | 10605 | int x ATTRIBUTE_UNUSED; |
252b5132 RH |
10606 | { |
10607 | register int temp; | |
10608 | register long temp_fill; | |
10609 | long max_alignment = 15; | |
10610 | ||
10611 | /* | |
10612 | ||
10613 | o Note that the assembler pulls down any immediately preceeding label | |
10614 | to the aligned address. | |
10615 | o It's not documented but auto alignment is reinstated by | |
10616 | a .align pseudo instruction. | |
10617 | o Note also that after auto alignment is turned off the mips assembler | |
10618 | issues an error on attempt to assemble an improperly aligned data item. | |
10619 | We don't. | |
10620 | ||
10621 | */ | |
10622 | ||
10623 | temp = get_absolute_expression (); | |
10624 | if (temp > max_alignment) | |
10625 | as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment); | |
10626 | else if (temp < 0) | |
10627 | { | |
10628 | as_warn (_("Alignment negative: 0 assumed.")); | |
10629 | temp = 0; | |
10630 | } | |
10631 | if (*input_line_pointer == ',') | |
10632 | { | |
10633 | input_line_pointer++; | |
10634 | temp_fill = get_absolute_expression (); | |
10635 | } | |
10636 | else | |
10637 | temp_fill = 0; | |
10638 | if (temp) | |
10639 | { | |
10640 | auto_align = 1; | |
10641 | mips_align (temp, (int) temp_fill, | |
10642 | insn_labels != NULL ? insn_labels->label : NULL); | |
10643 | } | |
10644 | else | |
10645 | { | |
10646 | auto_align = 0; | |
10647 | } | |
10648 | ||
10649 | demand_empty_rest_of_line (); | |
10650 | } | |
10651 | ||
10652 | void | |
10653 | mips_flush_pending_output () | |
10654 | { | |
10655 | mips_emit_delays (false); | |
10656 | mips_clear_insn_labels (); | |
10657 | } | |
10658 | ||
10659 | static void | |
10660 | s_change_sec (sec) | |
10661 | int sec; | |
10662 | { | |
10663 | segT seg; | |
10664 | ||
10665 | /* When generating embedded PIC code, we only use the .text, .lit8, | |
10666 | .sdata and .sbss sections. We change the .data and .rdata | |
10667 | pseudo-ops to use .sdata. */ | |
10668 | if (mips_pic == EMBEDDED_PIC | |
10669 | && (sec == 'd' || sec == 'r')) | |
10670 | sec = 's'; | |
10671 | ||
10672 | #ifdef OBJ_ELF | |
10673 | /* The ELF backend needs to know that we are changing sections, so | |
10674 | that .previous works correctly. We could do something like check | |
b6ff326e | 10675 | for an obj_section_change_hook macro, but that might be confusing |
252b5132 RH |
10676 | as it would not be appropriate to use it in the section changing |
10677 | functions in read.c, since obj-elf.c intercepts those. FIXME: | |
10678 | This should be cleaner, somehow. */ | |
10679 | obj_elf_section_change_hook (); | |
10680 | #endif | |
10681 | ||
10682 | mips_emit_delays (false); | |
10683 | switch (sec) | |
10684 | { | |
10685 | case 't': | |
10686 | s_text (0); | |
10687 | break; | |
10688 | case 'd': | |
10689 | s_data (0); | |
10690 | break; | |
10691 | case 'b': | |
10692 | subseg_set (bss_section, (subsegT) get_absolute_expression ()); | |
10693 | demand_empty_rest_of_line (); | |
10694 | break; | |
10695 | ||
10696 | case 'r': | |
10697 | if (USE_GLOBAL_POINTER_OPT) | |
10698 | { | |
10699 | seg = subseg_new (RDATA_SECTION_NAME, | |
10700 | (subsegT) get_absolute_expression ()); | |
10701 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
10702 | { | |
10703 | bfd_set_section_flags (stdoutput, seg, | |
10704 | (SEC_ALLOC | |
10705 | | SEC_LOAD | |
10706 | | SEC_READONLY | |
10707 | | SEC_RELOC | |
10708 | | SEC_DATA)); | |
10709 | if (strcmp (TARGET_OS, "elf") != 0) | |
e799a695 | 10710 | record_alignment (seg, 4); |
252b5132 RH |
10711 | } |
10712 | demand_empty_rest_of_line (); | |
10713 | } | |
10714 | else | |
10715 | { | |
10716 | as_bad (_("No read only data section in this object file format")); | |
10717 | demand_empty_rest_of_line (); | |
10718 | return; | |
10719 | } | |
10720 | break; | |
10721 | ||
10722 | case 's': | |
10723 | if (USE_GLOBAL_POINTER_OPT) | |
10724 | { | |
10725 | seg = subseg_new (".sdata", (subsegT) get_absolute_expression ()); | |
10726 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
10727 | { | |
10728 | bfd_set_section_flags (stdoutput, seg, | |
10729 | SEC_ALLOC | SEC_LOAD | SEC_RELOC | |
10730 | | SEC_DATA); | |
10731 | if (strcmp (TARGET_OS, "elf") != 0) | |
e799a695 | 10732 | record_alignment (seg, 4); |
252b5132 RH |
10733 | } |
10734 | demand_empty_rest_of_line (); | |
10735 | break; | |
10736 | } | |
10737 | else | |
10738 | { | |
10739 | as_bad (_("Global pointers not supported; recompile -G 0")); | |
10740 | demand_empty_rest_of_line (); | |
10741 | return; | |
10742 | } | |
10743 | } | |
10744 | ||
10745 | auto_align = 1; | |
10746 | } | |
10747 | ||
10748 | void | |
10749 | mips_enable_auto_align () | |
10750 | { | |
10751 | auto_align = 1; | |
10752 | } | |
10753 | ||
10754 | static void | |
10755 | s_cons (log_size) | |
10756 | int log_size; | |
10757 | { | |
10758 | symbolS *label; | |
10759 | ||
10760 | label = insn_labels != NULL ? insn_labels->label : NULL; | |
10761 | mips_emit_delays (false); | |
10762 | if (log_size > 0 && auto_align) | |
10763 | mips_align (log_size, 0, label); | |
10764 | mips_clear_insn_labels (); | |
10765 | cons (1 << log_size); | |
10766 | } | |
10767 | ||
10768 | static void | |
10769 | s_float_cons (type) | |
10770 | int type; | |
10771 | { | |
10772 | symbolS *label; | |
10773 | ||
10774 | label = insn_labels != NULL ? insn_labels->label : NULL; | |
10775 | ||
10776 | mips_emit_delays (false); | |
10777 | ||
10778 | if (auto_align) | |
49309057 ILT |
10779 | { |
10780 | if (type == 'd') | |
10781 | mips_align (3, 0, label); | |
10782 | else | |
10783 | mips_align (2, 0, label); | |
10784 | } | |
252b5132 RH |
10785 | |
10786 | mips_clear_insn_labels (); | |
10787 | ||
10788 | float_cons (type); | |
10789 | } | |
10790 | ||
10791 | /* Handle .globl. We need to override it because on Irix 5 you are | |
10792 | permitted to say | |
10793 | .globl foo .text | |
10794 | where foo is an undefined symbol, to mean that foo should be | |
10795 | considered to be the address of a function. */ | |
10796 | ||
10797 | static void | |
10798 | s_mips_globl (x) | |
43841e91 | 10799 | int x ATTRIBUTE_UNUSED; |
252b5132 RH |
10800 | { |
10801 | char *name; | |
10802 | int c; | |
10803 | symbolS *symbolP; | |
10804 | flagword flag; | |
10805 | ||
10806 | name = input_line_pointer; | |
10807 | c = get_symbol_end (); | |
10808 | symbolP = symbol_find_or_make (name); | |
10809 | *input_line_pointer = c; | |
10810 | SKIP_WHITESPACE (); | |
10811 | ||
10812 | /* On Irix 5, every global symbol that is not explicitly labelled as | |
10813 | being a function is apparently labelled as being an object. */ | |
10814 | flag = BSF_OBJECT; | |
10815 | ||
10816 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
10817 | { | |
10818 | char *secname; | |
10819 | asection *sec; | |
10820 | ||
10821 | secname = input_line_pointer; | |
10822 | c = get_symbol_end (); | |
10823 | sec = bfd_get_section_by_name (stdoutput, secname); | |
10824 | if (sec == NULL) | |
10825 | as_bad (_("%s: no such section"), secname); | |
10826 | *input_line_pointer = c; | |
10827 | ||
10828 | if (sec != NULL && (sec->flags & SEC_CODE) != 0) | |
10829 | flag = BSF_FUNCTION; | |
10830 | } | |
10831 | ||
49309057 | 10832 | symbol_get_bfdsym (symbolP)->flags |= flag; |
252b5132 RH |
10833 | |
10834 | S_SET_EXTERNAL (symbolP); | |
10835 | demand_empty_rest_of_line (); | |
10836 | } | |
10837 | ||
10838 | static void | |
10839 | s_option (x) | |
43841e91 | 10840 | int x ATTRIBUTE_UNUSED; |
252b5132 RH |
10841 | { |
10842 | char *opt; | |
10843 | char c; | |
10844 | ||
10845 | opt = input_line_pointer; | |
10846 | c = get_symbol_end (); | |
10847 | ||
10848 | if (*opt == 'O') | |
10849 | { | |
10850 | /* FIXME: What does this mean? */ | |
10851 | } | |
10852 | else if (strncmp (opt, "pic", 3) == 0) | |
10853 | { | |
10854 | int i; | |
10855 | ||
10856 | i = atoi (opt + 3); | |
10857 | if (i == 0) | |
10858 | mips_pic = NO_PIC; | |
10859 | else if (i == 2) | |
10860 | mips_pic = SVR4_PIC; | |
10861 | else | |
10862 | as_bad (_(".option pic%d not supported"), i); | |
10863 | ||
10864 | if (USE_GLOBAL_POINTER_OPT && mips_pic == SVR4_PIC) | |
10865 | { | |
10866 | if (g_switch_seen && g_switch_value != 0) | |
10867 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
10868 | g_switch_value = 0; | |
10869 | bfd_set_gp_size (stdoutput, 0); | |
10870 | } | |
10871 | } | |
10872 | else | |
10873 | as_warn (_("Unrecognized option \"%s\""), opt); | |
10874 | ||
10875 | *input_line_pointer = c; | |
10876 | demand_empty_rest_of_line (); | |
10877 | } | |
10878 | ||
10879 | /* This structure is used to hold a stack of .set values. */ | |
10880 | ||
e972090a NC |
10881 | struct mips_option_stack |
10882 | { | |
252b5132 RH |
10883 | struct mips_option_stack *next; |
10884 | struct mips_set_options options; | |
10885 | }; | |
10886 | ||
10887 | static struct mips_option_stack *mips_opts_stack; | |
10888 | ||
10889 | /* Handle the .set pseudo-op. */ | |
10890 | ||
10891 | static void | |
10892 | s_mipsset (x) | |
43841e91 | 10893 | int x ATTRIBUTE_UNUSED; |
252b5132 RH |
10894 | { |
10895 | char *name = input_line_pointer, ch; | |
10896 | ||
10897 | while (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
10898 | input_line_pointer++; | |
10899 | ch = *input_line_pointer; | |
10900 | *input_line_pointer = '\0'; | |
10901 | ||
10902 | if (strcmp (name, "reorder") == 0) | |
10903 | { | |
10904 | if (mips_opts.noreorder && prev_nop_frag != NULL) | |
10905 | { | |
10906 | /* If we still have pending nops, we can discard them. The | |
10907 | usual nop handling will insert any that are still | |
bdaaa2e1 | 10908 | needed. */ |
252b5132 RH |
10909 | prev_nop_frag->fr_fix -= (prev_nop_frag_holds |
10910 | * (mips_opts.mips16 ? 2 : 4)); | |
10911 | prev_nop_frag = NULL; | |
10912 | } | |
10913 | mips_opts.noreorder = 0; | |
10914 | } | |
10915 | else if (strcmp (name, "noreorder") == 0) | |
10916 | { | |
10917 | mips_emit_delays (true); | |
10918 | mips_opts.noreorder = 1; | |
10919 | mips_any_noreorder = 1; | |
10920 | } | |
10921 | else if (strcmp (name, "at") == 0) | |
10922 | { | |
10923 | mips_opts.noat = 0; | |
10924 | } | |
10925 | else if (strcmp (name, "noat") == 0) | |
10926 | { | |
10927 | mips_opts.noat = 1; | |
10928 | } | |
10929 | else if (strcmp (name, "macro") == 0) | |
10930 | { | |
10931 | mips_opts.warn_about_macros = 0; | |
10932 | } | |
10933 | else if (strcmp (name, "nomacro") == 0) | |
10934 | { | |
10935 | if (mips_opts.noreorder == 0) | |
10936 | as_bad (_("`noreorder' must be set before `nomacro'")); | |
10937 | mips_opts.warn_about_macros = 1; | |
10938 | } | |
10939 | else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0) | |
10940 | { | |
10941 | mips_opts.nomove = 0; | |
10942 | } | |
10943 | else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0) | |
10944 | { | |
10945 | mips_opts.nomove = 1; | |
10946 | } | |
10947 | else if (strcmp (name, "bopt") == 0) | |
10948 | { | |
10949 | mips_opts.nobopt = 0; | |
10950 | } | |
10951 | else if (strcmp (name, "nobopt") == 0) | |
10952 | { | |
10953 | mips_opts.nobopt = 1; | |
10954 | } | |
10955 | else if (strcmp (name, "mips16") == 0 | |
10956 | || strcmp (name, "MIPS-16") == 0) | |
10957 | mips_opts.mips16 = 1; | |
10958 | else if (strcmp (name, "nomips16") == 0 | |
10959 | || strcmp (name, "noMIPS-16") == 0) | |
10960 | mips_opts.mips16 = 0; | |
10961 | else if (strncmp (name, "mips", 4) == 0) | |
10962 | { | |
10963 | int isa; | |
553178e4 TS |
10964 | static int saved_mips_gp32; |
10965 | static int saved_mips_fp32; | |
e013f690 | 10966 | static enum mips_abi_level saved_mips_abi; |
553178e4 | 10967 | static int is_saved; |
252b5132 RH |
10968 | |
10969 | /* Permit the user to change the ISA on the fly. Needless to | |
10970 | say, misuse can cause serious problems. */ | |
10971 | isa = atoi (name + 4); | |
553178e4 TS |
10972 | switch (isa) |
10973 | { | |
10974 | case 0: | |
10975 | mips_gp32 = saved_mips_gp32; | |
10976 | mips_fp32 = saved_mips_fp32; | |
e013f690 | 10977 | mips_abi = saved_mips_abi; |
553178e4 TS |
10978 | is_saved = 0; |
10979 | break; | |
10980 | case 1: | |
10981 | case 2: | |
10982 | case 32: | |
10983 | if (! is_saved) | |
10984 | { | |
10985 | saved_mips_gp32 = mips_gp32; | |
10986 | saved_mips_fp32 = mips_fp32; | |
e013f690 | 10987 | saved_mips_abi = mips_abi; |
553178e4 TS |
10988 | } |
10989 | mips_gp32 = 1; | |
10990 | mips_fp32 = 1; | |
10991 | is_saved = 1; | |
10992 | break; | |
10993 | case 3: | |
10994 | case 4: | |
10995 | case 5: | |
10996 | case 64: | |
10997 | if (! is_saved) | |
10998 | { | |
10999 | saved_mips_gp32 = mips_gp32; | |
11000 | saved_mips_fp32 = mips_fp32; | |
e013f690 | 11001 | saved_mips_abi = mips_abi; |
553178e4 TS |
11002 | } |
11003 | mips_gp32 = 0; | |
11004 | mips_fp32 = 0; | |
e013f690 | 11005 | mips_abi = NO_ABI; |
553178e4 TS |
11006 | is_saved = 1; |
11007 | break; | |
11008 | default: | |
11009 | as_bad (_("unknown ISA level")); | |
11010 | break; | |
11011 | } | |
11012 | ||
e7af610e NC |
11013 | switch (isa) |
11014 | { | |
84ea6cf2 NC |
11015 | case 0: mips_opts.isa = file_mips_isa; break; |
11016 | case 1: mips_opts.isa = ISA_MIPS1; break; | |
11017 | case 2: mips_opts.isa = ISA_MIPS2; break; | |
11018 | case 3: mips_opts.isa = ISA_MIPS3; break; | |
84ea6cf2 | 11019 | case 4: mips_opts.isa = ISA_MIPS4; break; |
9a41af64 | 11020 | case 5: mips_opts.isa = ISA_MIPS5; break; |
84ea6cf2 NC |
11021 | case 32: mips_opts.isa = ISA_MIPS32; break; |
11022 | case 64: mips_opts.isa = ISA_MIPS64; break; | |
11023 | default: as_bad (_("unknown ISA level")); break; | |
e7af610e | 11024 | } |
252b5132 RH |
11025 | } |
11026 | else if (strcmp (name, "autoextend") == 0) | |
11027 | mips_opts.noautoextend = 0; | |
11028 | else if (strcmp (name, "noautoextend") == 0) | |
11029 | mips_opts.noautoextend = 1; | |
11030 | else if (strcmp (name, "push") == 0) | |
11031 | { | |
11032 | struct mips_option_stack *s; | |
11033 | ||
11034 | s = (struct mips_option_stack *) xmalloc (sizeof *s); | |
11035 | s->next = mips_opts_stack; | |
11036 | s->options = mips_opts; | |
11037 | mips_opts_stack = s; | |
11038 | } | |
11039 | else if (strcmp (name, "pop") == 0) | |
11040 | { | |
11041 | struct mips_option_stack *s; | |
11042 | ||
11043 | s = mips_opts_stack; | |
11044 | if (s == NULL) | |
11045 | as_bad (_(".set pop with no .set push")); | |
11046 | else | |
11047 | { | |
11048 | /* If we're changing the reorder mode we need to handle | |
11049 | delay slots correctly. */ | |
11050 | if (s->options.noreorder && ! mips_opts.noreorder) | |
11051 | mips_emit_delays (true); | |
11052 | else if (! s->options.noreorder && mips_opts.noreorder) | |
11053 | { | |
11054 | if (prev_nop_frag != NULL) | |
11055 | { | |
11056 | prev_nop_frag->fr_fix -= (prev_nop_frag_holds | |
11057 | * (mips_opts.mips16 ? 2 : 4)); | |
11058 | prev_nop_frag = NULL; | |
11059 | } | |
11060 | } | |
11061 | ||
11062 | mips_opts = s->options; | |
11063 | mips_opts_stack = s->next; | |
11064 | free (s); | |
11065 | } | |
11066 | } | |
11067 | else | |
11068 | { | |
11069 | as_warn (_("Tried to set unrecognized symbol: %s\n"), name); | |
11070 | } | |
11071 | *input_line_pointer = ch; | |
11072 | demand_empty_rest_of_line (); | |
11073 | } | |
11074 | ||
11075 | /* Handle the .abicalls pseudo-op. I believe this is equivalent to | |
11076 | .option pic2. It means to generate SVR4 PIC calls. */ | |
11077 | ||
11078 | static void | |
11079 | s_abicalls (ignore) | |
43841e91 | 11080 | int ignore ATTRIBUTE_UNUSED; |
252b5132 RH |
11081 | { |
11082 | mips_pic = SVR4_PIC; | |
11083 | if (USE_GLOBAL_POINTER_OPT) | |
11084 | { | |
11085 | if (g_switch_seen && g_switch_value != 0) | |
11086 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
11087 | g_switch_value = 0; | |
11088 | } | |
11089 | bfd_set_gp_size (stdoutput, 0); | |
11090 | demand_empty_rest_of_line (); | |
11091 | } | |
11092 | ||
11093 | /* Handle the .cpload pseudo-op. This is used when generating SVR4 | |
11094 | PIC code. It sets the $gp register for the function based on the | |
11095 | function address, which is in the register named in the argument. | |
11096 | This uses a relocation against _gp_disp, which is handled specially | |
11097 | by the linker. The result is: | |
11098 | lui $gp,%hi(_gp_disp) | |
11099 | addiu $gp,$gp,%lo(_gp_disp) | |
11100 | addu $gp,$gp,.cpload argument | |
11101 | The .cpload argument is normally $25 == $t9. */ | |
11102 | ||
11103 | static void | |
11104 | s_cpload (ignore) | |
43841e91 | 11105 | int ignore ATTRIBUTE_UNUSED; |
252b5132 RH |
11106 | { |
11107 | expressionS ex; | |
11108 | int icnt = 0; | |
11109 | ||
6478892d TS |
11110 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
11111 | .cpload is ignored. */ | |
11112 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) | |
252b5132 RH |
11113 | { |
11114 | s_ignore (0); | |
11115 | return; | |
11116 | } | |
11117 | ||
b6ff326e | 11118 | /* .cpload should be in .set noreorder section. */ |
252b5132 RH |
11119 | if (mips_opts.noreorder == 0) |
11120 | as_warn (_(".cpload not in noreorder section")); | |
11121 | ||
11122 | ex.X_op = O_symbol; | |
11123 | ex.X_add_symbol = symbol_find_or_make ("_gp_disp"); | |
11124 | ex.X_op_symbol = NULL; | |
11125 | ex.X_add_number = 0; | |
11126 | ||
11127 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ | |
49309057 | 11128 | symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; |
252b5132 RH |
11129 | |
11130 | macro_build_lui ((char *) NULL, &icnt, &ex, GP); | |
11131 | macro_build ((char *) NULL, &icnt, &ex, "addiu", "t,r,j", GP, GP, | |
11132 | (int) BFD_RELOC_LO16); | |
11133 | ||
11134 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "addu", "d,v,t", | |
11135 | GP, GP, tc_get_register (0)); | |
11136 | ||
11137 | demand_empty_rest_of_line (); | |
11138 | } | |
11139 | ||
6478892d TS |
11140 | /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is: |
11141 | .cpsetup $reg1, offset|$reg2, label | |
11142 | ||
11143 | If offset is given, this results in: | |
11144 | sd $gp, offset($sp) | |
11145 | lui $gp, %gp_rel(%neg(%hi(label))) | |
11146 | daddiu $gp, $gp, %gp_rel(%neg(%lo(label))) | |
11147 | addu $gp, $gp, $reg1 | |
11148 | ||
11149 | If $reg2 is given, this results in: | |
11150 | daddu $reg2, $gp, $0 | |
11151 | lui $gp, %gp_rel(%neg(%hi(label))) | |
11152 | daddiu $gp, $gp, %gp_rel(%neg(%lo(label))) | |
11153 | addu $gp, $gp, $reg1 | |
11154 | */ | |
11155 | static void | |
11156 | s_cpsetup (ignore) | |
11157 | int ignore ATTRIBUTE_UNUSED; | |
11158 | { | |
11159 | expressionS ex_off; | |
11160 | expressionS ex_sym; | |
11161 | int reg1; | |
11162 | int icnt = 0; | |
11163 | char *sym; | |
11164 | ||
11165 | /* If we are not generating SVR4 PIC code, .cpload is ignored. | |
11166 | We also need NewABI support. */ | |
11167 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
11168 | { | |
11169 | s_ignore (0); | |
11170 | return; | |
11171 | } | |
11172 | ||
11173 | reg1 = tc_get_register (0); | |
11174 | SKIP_WHITESPACE (); | |
11175 | if (*input_line_pointer != ',') | |
11176 | { | |
11177 | as_bad (_("missing argument separator ',' for .cpsetup")); | |
11178 | return; | |
11179 | } | |
11180 | else | |
11181 | input_line_pointer++; | |
11182 | SKIP_WHITESPACE (); | |
11183 | if (*input_line_pointer == '$') | |
11184 | mips_cpreturn_register = tc_get_register (0); | |
11185 | else | |
11186 | mips_cpreturn_offset = get_absolute_expression (); | |
11187 | SKIP_WHITESPACE (); | |
11188 | if (*input_line_pointer != ',') | |
11189 | { | |
11190 | as_bad (_("missing argument separator ',' for .cpsetup")); | |
11191 | return; | |
11192 | } | |
11193 | else | |
11194 | input_line_pointer++; | |
11195 | SKIP_WHITESPACE (); | |
11196 | sym = input_line_pointer; | |
11197 | while (ISALNUM (*input_line_pointer)) | |
11198 | input_line_pointer++; | |
11199 | *input_line_pointer = 0; | |
11200 | ||
11201 | ex_sym.X_op = O_symbol; | |
11202 | ex_sym.X_add_symbol = symbol_find_or_make (sym); | |
11203 | ex_sym.X_op_symbol = NULL; | |
11204 | ex_sym.X_add_number = 0; | |
11205 | ||
11206 | if (mips_cpreturn_register == -1) | |
11207 | { | |
11208 | ex_off.X_op = O_constant; | |
11209 | ex_off.X_add_symbol = NULL; | |
11210 | ex_off.X_op_symbol = NULL; | |
11211 | ex_off.X_add_number = mips_cpreturn_offset; | |
11212 | ||
11213 | macro_build ((char *) NULL, &icnt, &ex_off, "sd", "t,o(b)", | |
11214 | mips_gp_register, (int) BFD_RELOC_LO16, SP); | |
11215 | } | |
11216 | else | |
11217 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "daddu", | |
11218 | "d,v,t", mips_cpreturn_register, mips_gp_register, 0); | |
11219 | ||
11220 | macro_build ((char *) NULL, &icnt, &ex_sym, "lui", "t,u", mips_gp_register, | |
11221 | (int) BFD_RELOC_GPREL16); | |
11222 | fix_new (frag_now, (char *) prev_insn_fixp - 4 - frag_now->fr_literal, 0, | |
11223 | NULL, 0, 0, BFD_RELOC_MIPS_SUB); | |
11224 | fix_new (frag_now, (char *) prev_insn_fixp - 4 - frag_now->fr_literal, 0, | |
11225 | NULL, 0, 0, BFD_RELOC_HI16_S); | |
11226 | macro_build ((char *) NULL, &icnt, &ex_sym, "addiu", "t,r,j", | |
11227 | mips_gp_register, mips_gp_register, (int) BFD_RELOC_GPREL16); | |
11228 | fix_new (frag_now, (char *) prev_insn_fixp - 4 - frag_now->fr_literal, 0, | |
11229 | NULL, 0, 0, BFD_RELOC_MIPS_SUB); | |
11230 | fix_new (frag_now, (char *) prev_insn_fixp - 4 - frag_now->fr_literal, 0, | |
11231 | NULL, 0, 0, BFD_RELOC_LO16); | |
11232 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "daddu", | |
11233 | "d,v,t", mips_gp_register, mips_gp_register, reg1); | |
11234 | ||
11235 | demand_empty_rest_of_line (); | |
11236 | } | |
11237 | ||
11238 | static void | |
11239 | s_cplocal (ignore) | |
11240 | int ignore ATTRIBUTE_UNUSED; | |
11241 | { | |
11242 | /* If we are not generating SVR4 PIC code, or if this is not NewABI code, | |
11243 | .cplocal is ignored. */ | |
11244 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
11245 | { | |
11246 | s_ignore (0); | |
11247 | return; | |
11248 | } | |
11249 | ||
11250 | mips_gp_register = tc_get_register (0); | |
11251 | } | |
11252 | ||
252b5132 RH |
11253 | /* Handle the .cprestore pseudo-op. This stores $gp into a given |
11254 | offset from $sp. The offset is remembered, and after making a PIC | |
11255 | call $gp is restored from that location. */ | |
11256 | ||
11257 | static void | |
11258 | s_cprestore (ignore) | |
43841e91 | 11259 | int ignore ATTRIBUTE_UNUSED; |
252b5132 RH |
11260 | { |
11261 | expressionS ex; | |
11262 | int icnt = 0; | |
11263 | ||
6478892d TS |
11264 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
11265 | .cprestore is ignored. */ | |
11266 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) | |
252b5132 RH |
11267 | { |
11268 | s_ignore (0); | |
11269 | return; | |
11270 | } | |
11271 | ||
11272 | mips_cprestore_offset = get_absolute_expression (); | |
11273 | ||
11274 | ex.X_op = O_constant; | |
11275 | ex.X_add_symbol = NULL; | |
11276 | ex.X_op_symbol = NULL; | |
11277 | ex.X_add_number = mips_cprestore_offset; | |
11278 | ||
11279 | macro_build ((char *) NULL, &icnt, &ex, | |
ca4e0257 | 11280 | HAVE_32BIT_ADDRESSES ? "sw" : "sd", |
252b5132 RH |
11281 | "t,o(b)", GP, (int) BFD_RELOC_LO16, SP); |
11282 | ||
11283 | demand_empty_rest_of_line (); | |
11284 | } | |
11285 | ||
6478892d TS |
11286 | /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset |
11287 | was given in the preceeding .gpsetup, it results in: | |
11288 | ld $gp, offset($sp) | |
11289 | ||
11290 | If a register $reg2 was given there, it results in: | |
11291 | daddiu $gp, $gp, $reg2 | |
11292 | */ | |
11293 | static void | |
11294 | s_cpreturn (ignore) | |
11295 | int ignore ATTRIBUTE_UNUSED; | |
11296 | { | |
11297 | expressionS ex; | |
11298 | int icnt = 0; | |
11299 | ||
11300 | /* If we are not generating SVR4 PIC code, .cpreturn is ignored. | |
11301 | We also need NewABI support. */ | |
11302 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
11303 | { | |
11304 | s_ignore (0); | |
11305 | return; | |
11306 | } | |
11307 | ||
11308 | if (mips_cpreturn_register == -1) | |
11309 | { | |
11310 | ex.X_op = O_constant; | |
11311 | ex.X_add_symbol = NULL; | |
11312 | ex.X_op_symbol = NULL; | |
11313 | ex.X_add_number = mips_cpreturn_offset; | |
11314 | ||
11315 | macro_build ((char *) NULL, &icnt, &ex, "ld", "t,o(b)", | |
11316 | mips_gp_register, (int) BFD_RELOC_LO16, SP); | |
11317 | } | |
11318 | else | |
11319 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "daddu", | |
11320 | "d,v,t", mips_gp_register, mips_cpreturn_register, 0); | |
11321 | ||
11322 | demand_empty_rest_of_line (); | |
11323 | } | |
11324 | ||
11325 | /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC | |
11326 | code. It sets the offset to use in gp_rel relocations. */ | |
11327 | ||
11328 | static void | |
11329 | s_gpvalue (ignore) | |
11330 | int ignore ATTRIBUTE_UNUSED; | |
11331 | { | |
11332 | /* If we are not generating SVR4 PIC code, .gpvalue is ignored. | |
11333 | We also need NewABI support. */ | |
11334 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
11335 | { | |
11336 | s_ignore (0); | |
11337 | return; | |
11338 | } | |
11339 | ||
11340 | mips_cpreturn_offset = get_absolute_expression (); | |
11341 | ||
11342 | demand_empty_rest_of_line (); | |
11343 | } | |
11344 | ||
252b5132 RH |
11345 | /* Handle the .gpword pseudo-op. This is used when generating PIC |
11346 | code. It generates a 32 bit GP relative reloc. */ | |
11347 | ||
11348 | static void | |
11349 | s_gpword (ignore) | |
43841e91 | 11350 | int ignore ATTRIBUTE_UNUSED; |
252b5132 RH |
11351 | { |
11352 | symbolS *label; | |
11353 | expressionS ex; | |
11354 | char *p; | |
11355 | ||
11356 | /* When not generating PIC code, this is treated as .word. */ | |
11357 | if (mips_pic != SVR4_PIC) | |
11358 | { | |
11359 | s_cons (2); | |
11360 | return; | |
11361 | } | |
11362 | ||
11363 | label = insn_labels != NULL ? insn_labels->label : NULL; | |
11364 | mips_emit_delays (true); | |
11365 | if (auto_align) | |
11366 | mips_align (2, 0, label); | |
11367 | mips_clear_insn_labels (); | |
11368 | ||
11369 | expression (&ex); | |
11370 | ||
11371 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
11372 | { | |
11373 | as_bad (_("Unsupported use of .gpword")); | |
11374 | ignore_rest_of_line (); | |
11375 | } | |
11376 | ||
11377 | p = frag_more (4); | |
11378 | md_number_to_chars (p, (valueT) 0, 4); | |
11379 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, 0, | |
11380 | BFD_RELOC_MIPS_GPREL32); | |
11381 | ||
11382 | demand_empty_rest_of_line (); | |
11383 | } | |
11384 | ||
11385 | /* Handle the .cpadd pseudo-op. This is used when dealing with switch | |
11386 | tables in SVR4 PIC code. */ | |
11387 | ||
11388 | static void | |
11389 | s_cpadd (ignore) | |
43841e91 | 11390 | int ignore ATTRIBUTE_UNUSED; |
252b5132 RH |
11391 | { |
11392 | int icnt = 0; | |
11393 | int reg; | |
11394 | ||
6478892d TS |
11395 | /* This is ignored when not generating SVR4 PIC code or if this is NewABI |
11396 | code. */ | |
11397 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) | |
252b5132 RH |
11398 | { |
11399 | s_ignore (0); | |
11400 | return; | |
11401 | } | |
11402 | ||
11403 | /* Add $gp to the register named as an argument. */ | |
11404 | reg = tc_get_register (0); | |
11405 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 11406 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
11407 | "d,v,t", reg, reg, GP); |
11408 | ||
bdaaa2e1 | 11409 | demand_empty_rest_of_line (); |
252b5132 RH |
11410 | } |
11411 | ||
11412 | /* Handle the .insn pseudo-op. This marks instruction labels in | |
11413 | mips16 mode. This permits the linker to handle them specially, | |
11414 | such as generating jalx instructions when needed. We also make | |
11415 | them odd for the duration of the assembly, in order to generate the | |
11416 | right sort of code. We will make them even in the adjust_symtab | |
11417 | routine, while leaving them marked. This is convenient for the | |
11418 | debugger and the disassembler. The linker knows to make them odd | |
11419 | again. */ | |
11420 | ||
11421 | static void | |
11422 | s_insn (ignore) | |
43841e91 | 11423 | int ignore ATTRIBUTE_UNUSED; |
252b5132 RH |
11424 | { |
11425 | if (mips_opts.mips16) | |
11426 | mips16_mark_labels (); | |
11427 | ||
11428 | demand_empty_rest_of_line (); | |
11429 | } | |
11430 | ||
11431 | /* Handle a .stabn directive. We need these in order to mark a label | |
11432 | as being a mips16 text label correctly. Sometimes the compiler | |
11433 | will emit a label, followed by a .stabn, and then switch sections. | |
11434 | If the label and .stabn are in mips16 mode, then the label is | |
11435 | really a mips16 text label. */ | |
11436 | ||
11437 | static void | |
11438 | s_mips_stab (type) | |
11439 | int type; | |
11440 | { | |
11441 | if (type == 'n' && mips_opts.mips16) | |
11442 | mips16_mark_labels (); | |
11443 | ||
11444 | s_stab (type); | |
11445 | } | |
11446 | ||
11447 | /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. | |
11448 | */ | |
11449 | ||
11450 | static void | |
11451 | s_mips_weakext (ignore) | |
43841e91 | 11452 | int ignore ATTRIBUTE_UNUSED; |
252b5132 RH |
11453 | { |
11454 | char *name; | |
11455 | int c; | |
11456 | symbolS *symbolP; | |
11457 | expressionS exp; | |
11458 | ||
11459 | name = input_line_pointer; | |
11460 | c = get_symbol_end (); | |
11461 | symbolP = symbol_find_or_make (name); | |
11462 | S_SET_WEAK (symbolP); | |
11463 | *input_line_pointer = c; | |
11464 | ||
11465 | SKIP_WHITESPACE (); | |
11466 | ||
11467 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
11468 | { | |
11469 | if (S_IS_DEFINED (symbolP)) | |
11470 | { | |
11471 | as_bad ("Ignoring attempt to redefine symbol `%s'.", | |
11472 | S_GET_NAME (symbolP)); | |
11473 | ignore_rest_of_line (); | |
11474 | return; | |
11475 | } | |
bdaaa2e1 | 11476 | |
252b5132 RH |
11477 | if (*input_line_pointer == ',') |
11478 | { | |
11479 | ++input_line_pointer; | |
11480 | SKIP_WHITESPACE (); | |
11481 | } | |
bdaaa2e1 | 11482 | |
252b5132 RH |
11483 | expression (&exp); |
11484 | if (exp.X_op != O_symbol) | |
11485 | { | |
11486 | as_bad ("bad .weakext directive"); | |
11487 | ignore_rest_of_line(); | |
11488 | return; | |
11489 | } | |
49309057 | 11490 | symbol_set_value_expression (symbolP, &exp); |
252b5132 RH |
11491 | } |
11492 | ||
11493 | demand_empty_rest_of_line (); | |
11494 | } | |
11495 | ||
11496 | /* Parse a register string into a number. Called from the ECOFF code | |
11497 | to parse .frame. The argument is non-zero if this is the frame | |
11498 | register, so that we can record it in mips_frame_reg. */ | |
11499 | ||
11500 | int | |
11501 | tc_get_register (frame) | |
11502 | int frame; | |
11503 | { | |
11504 | int reg; | |
11505 | ||
11506 | SKIP_WHITESPACE (); | |
11507 | if (*input_line_pointer++ != '$') | |
11508 | { | |
11509 | as_warn (_("expected `$'")); | |
11510 | reg = 0; | |
11511 | } | |
3882b010 | 11512 | else if (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
11513 | { |
11514 | reg = get_absolute_expression (); | |
11515 | if (reg < 0 || reg >= 32) | |
11516 | { | |
11517 | as_warn (_("Bad register number")); | |
11518 | reg = 0; | |
11519 | } | |
11520 | } | |
11521 | else | |
11522 | { | |
11523 | if (strncmp (input_line_pointer, "fp", 2) == 0) | |
11524 | reg = FP; | |
11525 | else if (strncmp (input_line_pointer, "sp", 2) == 0) | |
11526 | reg = SP; | |
11527 | else if (strncmp (input_line_pointer, "gp", 2) == 0) | |
11528 | reg = GP; | |
11529 | else if (strncmp (input_line_pointer, "at", 2) == 0) | |
11530 | reg = AT; | |
11531 | else | |
11532 | { | |
11533 | as_warn (_("Unrecognized register name")); | |
11534 | reg = 0; | |
11535 | } | |
11536 | input_line_pointer += 2; | |
11537 | } | |
11538 | if (frame) | |
11539 | mips_frame_reg = reg != 0 ? reg : SP; | |
11540 | return reg; | |
11541 | } | |
11542 | ||
11543 | valueT | |
11544 | md_section_align (seg, addr) | |
11545 | asection *seg; | |
11546 | valueT addr; | |
11547 | { | |
11548 | int align = bfd_get_section_alignment (stdoutput, seg); | |
11549 | ||
11550 | #ifdef OBJ_ELF | |
11551 | /* We don't need to align ELF sections to the full alignment. | |
11552 | However, Irix 5 may prefer that we align them at least to a 16 | |
11553 | byte boundary. We don't bother to align the sections if we are | |
11554 | targeted for an embedded system. */ | |
11555 | if (strcmp (TARGET_OS, "elf") == 0) | |
11556 | return addr; | |
11557 | if (align > 4) | |
11558 | align = 4; | |
11559 | #endif | |
11560 | ||
11561 | return ((addr + (1 << align) - 1) & (-1 << align)); | |
11562 | } | |
11563 | ||
11564 | /* Utility routine, called from above as well. If called while the | |
11565 | input file is still being read, it's only an approximation. (For | |
11566 | example, a symbol may later become defined which appeared to be | |
11567 | undefined earlier.) */ | |
11568 | ||
11569 | static int | |
11570 | nopic_need_relax (sym, before_relaxing) | |
11571 | symbolS *sym; | |
11572 | int before_relaxing; | |
11573 | { | |
11574 | if (sym == 0) | |
11575 | return 0; | |
11576 | ||
6478892d | 11577 | if (USE_GLOBAL_POINTER_OPT && g_switch_value > 0) |
252b5132 RH |
11578 | { |
11579 | const char *symname; | |
11580 | int change; | |
11581 | ||
11582 | /* Find out whether this symbol can be referenced off the GP | |
11583 | register. It can be if it is smaller than the -G size or if | |
11584 | it is in the .sdata or .sbss section. Certain symbols can | |
11585 | not be referenced off the GP, although it appears as though | |
11586 | they can. */ | |
11587 | symname = S_GET_NAME (sym); | |
11588 | if (symname != (const char *) NULL | |
11589 | && (strcmp (symname, "eprol") == 0 | |
11590 | || strcmp (symname, "etext") == 0 | |
11591 | || strcmp (symname, "_gp") == 0 | |
11592 | || strcmp (symname, "edata") == 0 | |
11593 | || strcmp (symname, "_fbss") == 0 | |
11594 | || strcmp (symname, "_fdata") == 0 | |
11595 | || strcmp (symname, "_ftext") == 0 | |
11596 | || strcmp (symname, "end") == 0 | |
11597 | || strcmp (symname, "_gp_disp") == 0)) | |
11598 | change = 1; | |
11599 | else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym)) | |
11600 | && (0 | |
11601 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 ILT |
11602 | || (symbol_get_obj (sym)->ecoff_extern_size != 0 |
11603 | && (symbol_get_obj (sym)->ecoff_extern_size | |
11604 | <= g_switch_value)) | |
252b5132 RH |
11605 | #endif |
11606 | /* We must defer this decision until after the whole | |
11607 | file has been read, since there might be a .extern | |
11608 | after the first use of this symbol. */ | |
11609 | || (before_relaxing | |
11610 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 | 11611 | && symbol_get_obj (sym)->ecoff_extern_size == 0 |
252b5132 RH |
11612 | #endif |
11613 | && S_GET_VALUE (sym) == 0) | |
11614 | || (S_GET_VALUE (sym) != 0 | |
11615 | && S_GET_VALUE (sym) <= g_switch_value))) | |
11616 | change = 0; | |
11617 | else | |
11618 | { | |
11619 | const char *segname; | |
11620 | ||
11621 | segname = segment_name (S_GET_SEGMENT (sym)); | |
11622 | assert (strcmp (segname, ".lit8") != 0 | |
11623 | && strcmp (segname, ".lit4") != 0); | |
11624 | change = (strcmp (segname, ".sdata") != 0 | |
fba2b7f9 GK |
11625 | && strcmp (segname, ".sbss") != 0 |
11626 | && strncmp (segname, ".sdata.", 7) != 0 | |
11627 | && strncmp (segname, ".gnu.linkonce.s.", 16) != 0); | |
252b5132 RH |
11628 | } |
11629 | return change; | |
11630 | } | |
11631 | else | |
11632 | /* We are not optimizing for the GP register. */ | |
11633 | return 1; | |
11634 | } | |
11635 | ||
11636 | /* Given a mips16 variant frag FRAGP, return non-zero if it needs an | |
11637 | extended opcode. SEC is the section the frag is in. */ | |
11638 | ||
11639 | static int | |
11640 | mips16_extended_frag (fragp, sec, stretch) | |
11641 | fragS *fragp; | |
11642 | asection *sec; | |
11643 | long stretch; | |
11644 | { | |
11645 | int type; | |
11646 | register const struct mips16_immed_operand *op; | |
11647 | offsetT val; | |
11648 | int mintiny, maxtiny; | |
11649 | segT symsec; | |
98aa84af | 11650 | fragS *sym_frag; |
252b5132 RH |
11651 | |
11652 | if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype)) | |
11653 | return 0; | |
11654 | if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype)) | |
11655 | return 1; | |
11656 | ||
11657 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
11658 | op = mips16_immed_operands; | |
11659 | while (op->type != type) | |
11660 | { | |
11661 | ++op; | |
11662 | assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); | |
11663 | } | |
11664 | ||
11665 | if (op->unsp) | |
11666 | { | |
11667 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
11668 | { | |
11669 | mintiny = 1; | |
11670 | maxtiny = 1 << op->nbits; | |
11671 | } | |
11672 | else | |
11673 | { | |
11674 | mintiny = 0; | |
11675 | maxtiny = (1 << op->nbits) - 1; | |
11676 | } | |
11677 | } | |
11678 | else | |
11679 | { | |
11680 | mintiny = - (1 << (op->nbits - 1)); | |
11681 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
11682 | } | |
11683 | ||
98aa84af | 11684 | sym_frag = symbol_get_frag (fragp->fr_symbol); |
ac62c346 | 11685 | val = S_GET_VALUE (fragp->fr_symbol); |
98aa84af | 11686 | symsec = S_GET_SEGMENT (fragp->fr_symbol); |
252b5132 RH |
11687 | |
11688 | if (op->pcrel) | |
11689 | { | |
11690 | addressT addr; | |
11691 | ||
11692 | /* We won't have the section when we are called from | |
11693 | mips_relax_frag. However, we will always have been called | |
11694 | from md_estimate_size_before_relax first. If this is a | |
11695 | branch to a different section, we mark it as such. If SEC is | |
11696 | NULL, and the frag is not marked, then it must be a branch to | |
11697 | the same section. */ | |
11698 | if (sec == NULL) | |
11699 | { | |
11700 | if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype)) | |
11701 | return 1; | |
11702 | } | |
11703 | else | |
11704 | { | |
98aa84af | 11705 | /* Must have been called from md_estimate_size_before_relax. */ |
252b5132 RH |
11706 | if (symsec != sec) |
11707 | { | |
11708 | fragp->fr_subtype = | |
11709 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
11710 | ||
11711 | /* FIXME: We should support this, and let the linker | |
11712 | catch branches and loads that are out of range. */ | |
11713 | as_bad_where (fragp->fr_file, fragp->fr_line, | |
11714 | _("unsupported PC relative reference to different section")); | |
11715 | ||
11716 | return 1; | |
11717 | } | |
98aa84af AM |
11718 | if (fragp != sym_frag && sym_frag->fr_address == 0) |
11719 | /* Assume non-extended on the first relaxation pass. | |
11720 | The address we have calculated will be bogus if this is | |
11721 | a forward branch to another frag, as the forward frag | |
11722 | will have fr_address == 0. */ | |
11723 | return 0; | |
252b5132 RH |
11724 | } |
11725 | ||
11726 | /* In this case, we know for sure that the symbol fragment is in | |
98aa84af AM |
11727 | the same section. If the relax_marker of the symbol fragment |
11728 | differs from the relax_marker of this fragment, we have not | |
11729 | yet adjusted the symbol fragment fr_address. We want to add | |
252b5132 RH |
11730 | in STRETCH in order to get a better estimate of the address. |
11731 | This particularly matters because of the shift bits. */ | |
11732 | if (stretch != 0 | |
98aa84af | 11733 | && sym_frag->relax_marker != fragp->relax_marker) |
252b5132 RH |
11734 | { |
11735 | fragS *f; | |
11736 | ||
11737 | /* Adjust stretch for any alignment frag. Note that if have | |
11738 | been expanding the earlier code, the symbol may be | |
11739 | defined in what appears to be an earlier frag. FIXME: | |
11740 | This doesn't handle the fr_subtype field, which specifies | |
11741 | a maximum number of bytes to skip when doing an | |
11742 | alignment. */ | |
98aa84af | 11743 | for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next) |
252b5132 RH |
11744 | { |
11745 | if (f->fr_type == rs_align || f->fr_type == rs_align_code) | |
11746 | { | |
11747 | if (stretch < 0) | |
11748 | stretch = - ((- stretch) | |
11749 | & ~ ((1 << (int) f->fr_offset) - 1)); | |
11750 | else | |
11751 | stretch &= ~ ((1 << (int) f->fr_offset) - 1); | |
11752 | if (stretch == 0) | |
11753 | break; | |
11754 | } | |
11755 | } | |
11756 | if (f != NULL) | |
11757 | val += stretch; | |
11758 | } | |
11759 | ||
11760 | addr = fragp->fr_address + fragp->fr_fix; | |
11761 | ||
11762 | /* The base address rules are complicated. The base address of | |
11763 | a branch is the following instruction. The base address of a | |
11764 | PC relative load or add is the instruction itself, but if it | |
11765 | is in a delay slot (in which case it can not be extended) use | |
11766 | the address of the instruction whose delay slot it is in. */ | |
11767 | if (type == 'p' || type == 'q') | |
11768 | { | |
11769 | addr += 2; | |
11770 | ||
11771 | /* If we are currently assuming that this frag should be | |
11772 | extended, then, the current address is two bytes | |
bdaaa2e1 | 11773 | higher. */ |
252b5132 RH |
11774 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) |
11775 | addr += 2; | |
11776 | ||
11777 | /* Ignore the low bit in the target, since it will be set | |
11778 | for a text label. */ | |
11779 | if ((val & 1) != 0) | |
11780 | --val; | |
11781 | } | |
11782 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) | |
11783 | addr -= 4; | |
11784 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
11785 | addr -= 2; | |
11786 | ||
11787 | val -= addr & ~ ((1 << op->shift) - 1); | |
11788 | ||
11789 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
11790 | if (type == 'p' || type == 'q') | |
11791 | val /= 2; | |
11792 | ||
11793 | /* If any of the shifted bits are set, we must use an extended | |
11794 | opcode. If the address depends on the size of this | |
11795 | instruction, this can lead to a loop, so we arrange to always | |
11796 | use an extended opcode. We only check this when we are in | |
11797 | the main relaxation loop, when SEC is NULL. */ | |
11798 | if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL) | |
11799 | { | |
11800 | fragp->fr_subtype = | |
11801 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
11802 | return 1; | |
11803 | } | |
11804 | ||
11805 | /* If we are about to mark a frag as extended because the value | |
11806 | is precisely maxtiny + 1, then there is a chance of an | |
11807 | infinite loop as in the following code: | |
11808 | la $4,foo | |
11809 | .skip 1020 | |
11810 | .align 2 | |
11811 | foo: | |
11812 | In this case when the la is extended, foo is 0x3fc bytes | |
11813 | away, so the la can be shrunk, but then foo is 0x400 away, so | |
11814 | the la must be extended. To avoid this loop, we mark the | |
11815 | frag as extended if it was small, and is about to become | |
11816 | extended with a value of maxtiny + 1. */ | |
11817 | if (val == ((maxtiny + 1) << op->shift) | |
11818 | && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype) | |
11819 | && sec == NULL) | |
11820 | { | |
11821 | fragp->fr_subtype = | |
11822 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
11823 | return 1; | |
11824 | } | |
11825 | } | |
11826 | else if (symsec != absolute_section && sec != NULL) | |
11827 | as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation")); | |
11828 | ||
11829 | if ((val & ((1 << op->shift) - 1)) != 0 | |
11830 | || val < (mintiny << op->shift) | |
11831 | || val > (maxtiny << op->shift)) | |
11832 | return 1; | |
11833 | else | |
11834 | return 0; | |
11835 | } | |
11836 | ||
11837 | /* Estimate the size of a frag before relaxing. Unless this is the | |
11838 | mips16, we are not really relaxing here, and the final size is | |
11839 | encoded in the subtype information. For the mips16, we have to | |
11840 | decide whether we are using an extended opcode or not. */ | |
11841 | ||
252b5132 RH |
11842 | int |
11843 | md_estimate_size_before_relax (fragp, segtype) | |
11844 | fragS *fragp; | |
11845 | asection *segtype; | |
11846 | { | |
43841e91 | 11847 | int change = 0; |
8614eeee | 11848 | boolean linkonce = false; |
252b5132 RH |
11849 | |
11850 | if (RELAX_MIPS16_P (fragp->fr_subtype)) | |
11851 | { | |
11852 | if (mips16_extended_frag (fragp, segtype, 0)) | |
11853 | { | |
11854 | fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype); | |
11855 | return 4; | |
11856 | } | |
11857 | else | |
11858 | { | |
11859 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype); | |
11860 | return 2; | |
11861 | } | |
11862 | } | |
11863 | ||
11864 | if (mips_pic == NO_PIC) | |
11865 | { | |
11866 | change = nopic_need_relax (fragp->fr_symbol, 0); | |
11867 | } | |
11868 | else if (mips_pic == SVR4_PIC) | |
11869 | { | |
11870 | symbolS *sym; | |
11871 | asection *symsec; | |
11872 | ||
11873 | sym = fragp->fr_symbol; | |
11874 | ||
11875 | /* Handle the case of a symbol equated to another symbol. */ | |
e0890092 | 11876 | while (symbol_equated_reloc_p (sym)) |
252b5132 RH |
11877 | { |
11878 | symbolS *n; | |
11879 | ||
11880 | /* It's possible to get a loop here in a badly written | |
11881 | program. */ | |
49309057 | 11882 | n = symbol_get_value_expression (sym)->X_add_symbol; |
252b5132 RH |
11883 | if (n == sym) |
11884 | break; | |
11885 | sym = n; | |
11886 | } | |
11887 | ||
11888 | symsec = S_GET_SEGMENT (sym); | |
11889 | ||
8614eeee UC |
11890 | /* duplicate the test for LINK_ONCE sections as in adjust_reloc_syms */ |
11891 | if (symsec != segtype && ! S_IS_LOCAL (sym)) | |
beae10d5 KH |
11892 | { |
11893 | if ((bfd_get_section_flags (stdoutput, symsec) & SEC_LINK_ONCE) | |
11894 | != 0) | |
11895 | linkonce = true; | |
11896 | ||
11897 | /* The GNU toolchain uses an extension for ELF: a section | |
11898 | beginning with the magic string .gnu.linkonce is a linkonce | |
11899 | section. */ | |
11900 | if (strncmp (segment_name (symsec), ".gnu.linkonce", | |
11901 | sizeof ".gnu.linkonce" - 1) == 0) | |
11902 | linkonce = true; | |
11903 | } | |
8614eeee | 11904 | |
252b5132 RH |
11905 | /* This must duplicate the test in adjust_reloc_syms. */ |
11906 | change = (symsec != &bfd_und_section | |
11907 | && symsec != &bfd_abs_section | |
426b0403 | 11908 | && ! bfd_is_com_section (symsec) |
8614eeee | 11909 | && !linkonce |
426b0403 | 11910 | #ifdef OBJ_ELF |
ea4ff978 | 11911 | /* A global or weak symbol is treated as external. */ |
46bac6de L |
11912 | && (OUTPUT_FLAVOR == bfd_target_elf_flavour |
11913 | && ! (S_IS_EXTERN (sym) || S_IS_WEAK (sym))) | |
426b0403 AM |
11914 | #endif |
11915 | ); | |
252b5132 RH |
11916 | } |
11917 | else | |
11918 | abort (); | |
11919 | ||
11920 | if (change) | |
11921 | { | |
11922 | /* Record the offset to the first reloc in the fr_opcode field. | |
11923 | This lets md_convert_frag and tc_gen_reloc know that the code | |
11924 | must be expanded. */ | |
11925 | fragp->fr_opcode = (fragp->fr_literal | |
11926 | + fragp->fr_fix | |
11927 | - RELAX_OLD (fragp->fr_subtype) | |
11928 | + RELAX_RELOC1 (fragp->fr_subtype)); | |
11929 | /* FIXME: This really needs as_warn_where. */ | |
11930 | if (RELAX_WARN (fragp->fr_subtype)) | |
9a41af64 TS |
11931 | as_warn (_("AT used after \".set noat\" or macro used after " |
11932 | "\".set nomacro\"")); | |
11933 | ||
11934 | return RELAX_NEW (fragp->fr_subtype) - RELAX_OLD (fragp->fr_subtype); | |
252b5132 RH |
11935 | } |
11936 | ||
9a41af64 | 11937 | return 0; |
252b5132 RH |
11938 | } |
11939 | ||
11940 | /* This is called to see whether a reloc against a defined symbol | |
11941 | should be converted into a reloc against a section. Don't adjust | |
11942 | MIPS16 jump relocations, so we don't have to worry about the format | |
11943 | of the offset in the .o file. Don't adjust relocations against | |
11944 | mips16 symbols, so that the linker can find them if it needs to set | |
11945 | up a stub. */ | |
11946 | ||
11947 | int | |
11948 | mips_fix_adjustable (fixp) | |
11949 | fixS *fixp; | |
11950 | { | |
ea4ff978 L |
11951 | #ifdef OBJ_ELF |
11952 | /* Prevent all adjustments to global symbols. */ | |
46bac6de L |
11953 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour |
11954 | && (S_IS_EXTERN (fixp->fx_addsy) || S_IS_WEAK (fixp->fx_addsy))) | |
ea4ff978 L |
11955 | return 0; |
11956 | #endif | |
252b5132 RH |
11957 | if (fixp->fx_r_type == BFD_RELOC_MIPS16_JMP) |
11958 | return 0; | |
11959 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT | |
11960 | || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
11961 | return 0; | |
11962 | if (fixp->fx_addsy == NULL) | |
11963 | return 1; | |
11964 | #ifdef OBJ_ELF | |
11965 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour | |
11966 | && S_GET_OTHER (fixp->fx_addsy) == STO_MIPS16 | |
11967 | && fixp->fx_subsy == NULL) | |
11968 | return 0; | |
11969 | #endif | |
11970 | return 1; | |
11971 | } | |
11972 | ||
11973 | /* Translate internal representation of relocation info to BFD target | |
11974 | format. */ | |
11975 | ||
11976 | arelent ** | |
11977 | tc_gen_reloc (section, fixp) | |
43841e91 | 11978 | asection *section ATTRIBUTE_UNUSED; |
252b5132 RH |
11979 | fixS *fixp; |
11980 | { | |
11981 | static arelent *retval[4]; | |
11982 | arelent *reloc; | |
11983 | bfd_reloc_code_real_type code; | |
11984 | ||
11985 | reloc = retval[0] = (arelent *) xmalloc (sizeof (arelent)); | |
11986 | retval[1] = NULL; | |
11987 | ||
49309057 ILT |
11988 | reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); |
11989 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
252b5132 RH |
11990 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; |
11991 | ||
11992 | if (mips_pic == EMBEDDED_PIC | |
11993 | && SWITCH_TABLE (fixp)) | |
11994 | { | |
11995 | /* For a switch table entry we use a special reloc. The addend | |
11996 | is actually the difference between the reloc address and the | |
11997 | subtrahend. */ | |
11998 | reloc->addend = reloc->address - S_GET_VALUE (fixp->fx_subsy); | |
11999 | if (OUTPUT_FLAVOR != bfd_target_ecoff_flavour) | |
12000 | as_fatal (_("Double check fx_r_type in tc-mips.c:tc_gen_reloc")); | |
12001 | fixp->fx_r_type = BFD_RELOC_GPREL32; | |
12002 | } | |
bb2d6cd7 GK |
12003 | else if (fixp->fx_pcrel == 0 || OUTPUT_FLAVOR == bfd_target_elf_flavour) |
12004 | reloc->addend = fixp->fx_addnumber; | |
252b5132 RH |
12005 | else if (fixp->fx_r_type == BFD_RELOC_PCREL_LO16) |
12006 | { | |
12007 | /* We use a special addend for an internal RELLO reloc. */ | |
49309057 | 12008 | if (symbol_section_p (fixp->fx_addsy)) |
252b5132 RH |
12009 | reloc->addend = reloc->address - S_GET_VALUE (fixp->fx_subsy); |
12010 | else | |
12011 | reloc->addend = fixp->fx_addnumber + reloc->address; | |
12012 | } | |
12013 | else if (fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S) | |
12014 | { | |
12015 | assert (fixp->fx_next != NULL | |
12016 | && fixp->fx_next->fx_r_type == BFD_RELOC_PCREL_LO16); | |
12017 | /* We use a special addend for an internal RELHI reloc. The | |
12018 | reloc is relative to the RELLO; adjust the addend | |
12019 | accordingly. */ | |
49309057 | 12020 | if (symbol_section_p (fixp->fx_addsy)) |
252b5132 RH |
12021 | reloc->addend = (fixp->fx_next->fx_frag->fr_address |
12022 | + fixp->fx_next->fx_where | |
12023 | - S_GET_VALUE (fixp->fx_subsy)); | |
12024 | else | |
12025 | reloc->addend = (fixp->fx_addnumber | |
12026 | + fixp->fx_next->fx_frag->fr_address | |
12027 | + fixp->fx_next->fx_where); | |
12028 | } | |
252b5132 RH |
12029 | else |
12030 | { | |
12031 | if (OUTPUT_FLAVOR != bfd_target_aout_flavour) | |
12032 | /* A gruesome hack which is a result of the gruesome gas reloc | |
12033 | handling. */ | |
12034 | reloc->addend = reloc->address; | |
12035 | else | |
12036 | reloc->addend = -reloc->address; | |
12037 | } | |
12038 | ||
12039 | /* If this is a variant frag, we may need to adjust the existing | |
12040 | reloc and generate a new one. */ | |
12041 | if (fixp->fx_frag->fr_opcode != NULL | |
12042 | && (fixp->fx_r_type == BFD_RELOC_MIPS_GPREL | |
12043 | || fixp->fx_r_type == BFD_RELOC_MIPS_GOT16 | |
12044 | || fixp->fx_r_type == BFD_RELOC_MIPS_CALL16 | |
12045 | || fixp->fx_r_type == BFD_RELOC_MIPS_GOT_HI16 | |
12046 | || fixp->fx_r_type == BFD_RELOC_MIPS_GOT_LO16 | |
12047 | || fixp->fx_r_type == BFD_RELOC_MIPS_CALL_HI16 | |
6478892d TS |
12048 | || fixp->fx_r_type == BFD_RELOC_MIPS_CALL_LO16) |
12049 | && ! HAVE_NEWABI) | |
252b5132 RH |
12050 | { |
12051 | arelent *reloc2; | |
12052 | ||
12053 | assert (! RELAX_MIPS16_P (fixp->fx_frag->fr_subtype)); | |
12054 | ||
12055 | /* If this is not the last reloc in this frag, then we have two | |
12056 | GPREL relocs, or a GOT_HI16/GOT_LO16 pair, or a | |
12057 | CALL_HI16/CALL_LO16, both of which are being replaced. Let | |
12058 | the second one handle all of them. */ | |
12059 | if (fixp->fx_next != NULL | |
12060 | && fixp->fx_frag == fixp->fx_next->fx_frag) | |
12061 | { | |
12062 | assert ((fixp->fx_r_type == BFD_RELOC_MIPS_GPREL | |
12063 | && fixp->fx_next->fx_r_type == BFD_RELOC_MIPS_GPREL) | |
12064 | || (fixp->fx_r_type == BFD_RELOC_MIPS_GOT_HI16 | |
12065 | && (fixp->fx_next->fx_r_type | |
12066 | == BFD_RELOC_MIPS_GOT_LO16)) | |
12067 | || (fixp->fx_r_type == BFD_RELOC_MIPS_CALL_HI16 | |
12068 | && (fixp->fx_next->fx_r_type | |
12069 | == BFD_RELOC_MIPS_CALL_LO16))); | |
12070 | retval[0] = NULL; | |
12071 | return retval; | |
12072 | } | |
12073 | ||
12074 | fixp->fx_where = fixp->fx_frag->fr_opcode - fixp->fx_frag->fr_literal; | |
12075 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
12076 | reloc2 = retval[1] = (arelent *) xmalloc (sizeof (arelent)); | |
12077 | retval[2] = NULL; | |
49309057 ILT |
12078 | reloc2->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); |
12079 | *reloc2->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
252b5132 RH |
12080 | reloc2->address = (reloc->address |
12081 | + (RELAX_RELOC2 (fixp->fx_frag->fr_subtype) | |
12082 | - RELAX_RELOC1 (fixp->fx_frag->fr_subtype))); | |
12083 | reloc2->addend = fixp->fx_addnumber; | |
12084 | reloc2->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_LO16); | |
12085 | assert (reloc2->howto != NULL); | |
12086 | ||
12087 | if (RELAX_RELOC3 (fixp->fx_frag->fr_subtype)) | |
12088 | { | |
12089 | arelent *reloc3; | |
12090 | ||
12091 | reloc3 = retval[2] = (arelent *) xmalloc (sizeof (arelent)); | |
12092 | retval[3] = NULL; | |
12093 | *reloc3 = *reloc2; | |
12094 | reloc3->address += 4; | |
12095 | } | |
12096 | ||
12097 | if (mips_pic == NO_PIC) | |
12098 | { | |
12099 | assert (fixp->fx_r_type == BFD_RELOC_MIPS_GPREL); | |
12100 | fixp->fx_r_type = BFD_RELOC_HI16_S; | |
12101 | } | |
12102 | else if (mips_pic == SVR4_PIC) | |
12103 | { | |
12104 | switch (fixp->fx_r_type) | |
12105 | { | |
12106 | default: | |
12107 | abort (); | |
12108 | case BFD_RELOC_MIPS_GOT16: | |
12109 | break; | |
12110 | case BFD_RELOC_MIPS_CALL16: | |
12111 | case BFD_RELOC_MIPS_GOT_LO16: | |
12112 | case BFD_RELOC_MIPS_CALL_LO16: | |
12113 | fixp->fx_r_type = BFD_RELOC_MIPS_GOT16; | |
12114 | break; | |
12115 | } | |
12116 | } | |
12117 | else | |
12118 | abort (); | |
12119 | } | |
12120 | ||
12121 | /* Since MIPS ELF uses Rel instead of Rela, encode the vtable entry | |
12122 | to be used in the relocation's section offset. */ | |
12123 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
12124 | { | |
12125 | reloc->address = reloc->addend; | |
12126 | reloc->addend = 0; | |
12127 | } | |
12128 | ||
12129 | /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that | |
12130 | fixup_segment converted a non-PC relative reloc into a PC | |
12131 | relative reloc. In such a case, we need to convert the reloc | |
12132 | code. */ | |
12133 | code = fixp->fx_r_type; | |
12134 | if (fixp->fx_pcrel) | |
12135 | { | |
12136 | switch (code) | |
12137 | { | |
12138 | case BFD_RELOC_8: | |
12139 | code = BFD_RELOC_8_PCREL; | |
12140 | break; | |
12141 | case BFD_RELOC_16: | |
12142 | code = BFD_RELOC_16_PCREL; | |
12143 | break; | |
12144 | case BFD_RELOC_32: | |
12145 | code = BFD_RELOC_32_PCREL; | |
12146 | break; | |
12147 | case BFD_RELOC_64: | |
12148 | code = BFD_RELOC_64_PCREL; | |
12149 | break; | |
12150 | case BFD_RELOC_8_PCREL: | |
12151 | case BFD_RELOC_16_PCREL: | |
12152 | case BFD_RELOC_32_PCREL: | |
12153 | case BFD_RELOC_64_PCREL: | |
12154 | case BFD_RELOC_16_PCREL_S2: | |
12155 | case BFD_RELOC_PCREL_HI16_S: | |
12156 | case BFD_RELOC_PCREL_LO16: | |
12157 | break; | |
12158 | default: | |
12159 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
12160 | _("Cannot make %s relocation PC relative"), | |
12161 | bfd_get_reloc_code_name (code)); | |
12162 | } | |
12163 | } | |
12164 | ||
12165 | /* To support a PC relative reloc when generating embedded PIC code | |
12166 | for ECOFF, we use a Cygnus extension. We check for that here to | |
12167 | make sure that we don't let such a reloc escape normally. */ | |
bb2d6cd7 GK |
12168 | if ((OUTPUT_FLAVOR == bfd_target_ecoff_flavour |
12169 | || OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
252b5132 RH |
12170 | && code == BFD_RELOC_16_PCREL_S2 |
12171 | && mips_pic != EMBEDDED_PIC) | |
12172 | reloc->howto = NULL; | |
12173 | else | |
12174 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); | |
12175 | ||
12176 | if (reloc->howto == NULL) | |
12177 | { | |
12178 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
12179 | _("Can not represent %s relocation in this object file format"), | |
12180 | bfd_get_reloc_code_name (code)); | |
12181 | retval[0] = NULL; | |
12182 | } | |
12183 | ||
12184 | return retval; | |
12185 | } | |
12186 | ||
12187 | /* Relax a machine dependent frag. This returns the amount by which | |
12188 | the current size of the frag should change. */ | |
12189 | ||
12190 | int | |
12191 | mips_relax_frag (fragp, stretch) | |
12192 | fragS *fragp; | |
12193 | long stretch; | |
12194 | { | |
12195 | if (! RELAX_MIPS16_P (fragp->fr_subtype)) | |
12196 | return 0; | |
12197 | ||
12198 | if (mips16_extended_frag (fragp, (asection *) NULL, stretch)) | |
12199 | { | |
12200 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
12201 | return 0; | |
12202 | fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype); | |
12203 | return 2; | |
12204 | } | |
12205 | else | |
12206 | { | |
12207 | if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
12208 | return 0; | |
12209 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype); | |
12210 | return -2; | |
12211 | } | |
12212 | ||
12213 | return 0; | |
12214 | } | |
12215 | ||
12216 | /* Convert a machine dependent frag. */ | |
12217 | ||
12218 | void | |
12219 | md_convert_frag (abfd, asec, fragp) | |
43841e91 | 12220 | bfd *abfd ATTRIBUTE_UNUSED; |
252b5132 RH |
12221 | segT asec; |
12222 | fragS *fragp; | |
12223 | { | |
12224 | int old, new; | |
12225 | char *fixptr; | |
12226 | ||
12227 | if (RELAX_MIPS16_P (fragp->fr_subtype)) | |
12228 | { | |
12229 | int type; | |
12230 | register const struct mips16_immed_operand *op; | |
12231 | boolean small, ext; | |
12232 | offsetT val; | |
12233 | bfd_byte *buf; | |
12234 | unsigned long insn; | |
12235 | boolean use_extend; | |
12236 | unsigned short extend; | |
12237 | ||
12238 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
12239 | op = mips16_immed_operands; | |
12240 | while (op->type != type) | |
12241 | ++op; | |
12242 | ||
12243 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
12244 | { | |
12245 | small = false; | |
12246 | ext = true; | |
12247 | } | |
12248 | else | |
12249 | { | |
12250 | small = true; | |
12251 | ext = false; | |
12252 | } | |
12253 | ||
6386f3a7 | 12254 | resolve_symbol_value (fragp->fr_symbol); |
252b5132 RH |
12255 | val = S_GET_VALUE (fragp->fr_symbol); |
12256 | if (op->pcrel) | |
12257 | { | |
12258 | addressT addr; | |
12259 | ||
12260 | addr = fragp->fr_address + fragp->fr_fix; | |
12261 | ||
12262 | /* The rules for the base address of a PC relative reloc are | |
12263 | complicated; see mips16_extended_frag. */ | |
12264 | if (type == 'p' || type == 'q') | |
12265 | { | |
12266 | addr += 2; | |
12267 | if (ext) | |
12268 | addr += 2; | |
12269 | /* Ignore the low bit in the target, since it will be | |
12270 | set for a text label. */ | |
12271 | if ((val & 1) != 0) | |
12272 | --val; | |
12273 | } | |
12274 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) | |
12275 | addr -= 4; | |
12276 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
12277 | addr -= 2; | |
12278 | ||
12279 | addr &= ~ (addressT) ((1 << op->shift) - 1); | |
12280 | val -= addr; | |
12281 | ||
12282 | /* Make sure the section winds up with the alignment we have | |
12283 | assumed. */ | |
12284 | if (op->shift > 0) | |
12285 | record_alignment (asec, op->shift); | |
12286 | } | |
12287 | ||
12288 | if (ext | |
12289 | && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype) | |
12290 | || RELAX_MIPS16_DSLOT (fragp->fr_subtype))) | |
12291 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
12292 | _("extended instruction in delay slot")); | |
12293 | ||
12294 | buf = (bfd_byte *) (fragp->fr_literal + fragp->fr_fix); | |
12295 | ||
12296 | if (target_big_endian) | |
12297 | insn = bfd_getb16 (buf); | |
12298 | else | |
12299 | insn = bfd_getl16 (buf); | |
12300 | ||
12301 | mips16_immed (fragp->fr_file, fragp->fr_line, type, val, | |
12302 | RELAX_MIPS16_USER_EXT (fragp->fr_subtype), | |
12303 | small, ext, &insn, &use_extend, &extend); | |
12304 | ||
12305 | if (use_extend) | |
12306 | { | |
12307 | md_number_to_chars (buf, 0xf000 | extend, 2); | |
12308 | fragp->fr_fix += 2; | |
12309 | buf += 2; | |
12310 | } | |
12311 | ||
12312 | md_number_to_chars (buf, insn, 2); | |
12313 | fragp->fr_fix += 2; | |
12314 | buf += 2; | |
12315 | } | |
12316 | else | |
12317 | { | |
12318 | if (fragp->fr_opcode == NULL) | |
12319 | return; | |
12320 | ||
12321 | old = RELAX_OLD (fragp->fr_subtype); | |
12322 | new = RELAX_NEW (fragp->fr_subtype); | |
12323 | fixptr = fragp->fr_literal + fragp->fr_fix; | |
12324 | ||
12325 | if (new > 0) | |
12326 | memcpy (fixptr - old, fixptr, new); | |
12327 | ||
12328 | fragp->fr_fix += new - old; | |
12329 | } | |
12330 | } | |
12331 | ||
12332 | #ifdef OBJ_ELF | |
12333 | ||
12334 | /* This function is called after the relocs have been generated. | |
12335 | We've been storing mips16 text labels as odd. Here we convert them | |
12336 | back to even for the convenience of the debugger. */ | |
12337 | ||
12338 | void | |
12339 | mips_frob_file_after_relocs () | |
12340 | { | |
12341 | asymbol **syms; | |
12342 | unsigned int count, i; | |
12343 | ||
12344 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
12345 | return; | |
12346 | ||
12347 | syms = bfd_get_outsymbols (stdoutput); | |
12348 | count = bfd_get_symcount (stdoutput); | |
12349 | for (i = 0; i < count; i++, syms++) | |
12350 | { | |
12351 | if (elf_symbol (*syms)->internal_elf_sym.st_other == STO_MIPS16 | |
12352 | && ((*syms)->value & 1) != 0) | |
12353 | { | |
12354 | (*syms)->value &= ~1; | |
12355 | /* If the symbol has an odd size, it was probably computed | |
12356 | incorrectly, so adjust that as well. */ | |
12357 | if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0) | |
12358 | ++elf_symbol (*syms)->internal_elf_sym.st_size; | |
12359 | } | |
12360 | } | |
12361 | } | |
12362 | ||
12363 | #endif | |
12364 | ||
12365 | /* This function is called whenever a label is defined. It is used | |
12366 | when handling branch delays; if a branch has a label, we assume we | |
12367 | can not move it. */ | |
12368 | ||
12369 | void | |
12370 | mips_define_label (sym) | |
12371 | symbolS *sym; | |
12372 | { | |
12373 | struct insn_label_list *l; | |
12374 | ||
12375 | if (free_insn_labels == NULL) | |
12376 | l = (struct insn_label_list *) xmalloc (sizeof *l); | |
12377 | else | |
12378 | { | |
12379 | l = free_insn_labels; | |
12380 | free_insn_labels = l->next; | |
12381 | } | |
12382 | ||
12383 | l->label = sym; | |
12384 | l->next = insn_labels; | |
12385 | insn_labels = l; | |
12386 | } | |
12387 | \f | |
12388 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
12389 | ||
12390 | /* Some special processing for a MIPS ELF file. */ | |
12391 | ||
12392 | void | |
12393 | mips_elf_final_processing () | |
12394 | { | |
12395 | /* Write out the register information. */ | |
e013f690 | 12396 | if (! HAVE_NEWABI) |
252b5132 RH |
12397 | { |
12398 | Elf32_RegInfo s; | |
12399 | ||
12400 | s.ri_gprmask = mips_gprmask; | |
12401 | s.ri_cprmask[0] = mips_cprmask[0]; | |
12402 | s.ri_cprmask[1] = mips_cprmask[1]; | |
12403 | s.ri_cprmask[2] = mips_cprmask[2]; | |
12404 | s.ri_cprmask[3] = mips_cprmask[3]; | |
12405 | /* The gp_value field is set by the MIPS ELF backend. */ | |
12406 | ||
12407 | bfd_mips_elf32_swap_reginfo_out (stdoutput, &s, | |
12408 | ((Elf32_External_RegInfo *) | |
12409 | mips_regmask_frag)); | |
12410 | } | |
12411 | else | |
12412 | { | |
12413 | Elf64_Internal_RegInfo s; | |
12414 | ||
12415 | s.ri_gprmask = mips_gprmask; | |
12416 | s.ri_pad = 0; | |
12417 | s.ri_cprmask[0] = mips_cprmask[0]; | |
12418 | s.ri_cprmask[1] = mips_cprmask[1]; | |
12419 | s.ri_cprmask[2] = mips_cprmask[2]; | |
12420 | s.ri_cprmask[3] = mips_cprmask[3]; | |
12421 | /* The gp_value field is set by the MIPS ELF backend. */ | |
12422 | ||
12423 | bfd_mips_elf64_swap_reginfo_out (stdoutput, &s, | |
12424 | ((Elf64_External_RegInfo *) | |
12425 | mips_regmask_frag)); | |
12426 | } | |
12427 | ||
12428 | /* Set the MIPS ELF flag bits. FIXME: There should probably be some | |
12429 | sort of BFD interface for this. */ | |
12430 | if (mips_any_noreorder) | |
12431 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER; | |
12432 | if (mips_pic != NO_PIC) | |
12433 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC; | |
12434 | ||
bdaaa2e1 | 12435 | /* Set the MIPS ELF ABI flags. */ |
e013f690 | 12436 | if (mips_abi == NO_ABI) |
252b5132 | 12437 | ; |
e013f690 | 12438 | else if (mips_abi == O32_ABI) |
252b5132 | 12439 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32; |
e013f690 | 12440 | else if (mips_abi == O64_ABI) |
252b5132 | 12441 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64; |
e013f690 | 12442 | else if (mips_abi == EABI_ABI) |
252b5132 RH |
12443 | { |
12444 | if (mips_eabi64) | |
12445 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64; | |
12446 | else | |
12447 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32; | |
12448 | } | |
e013f690 | 12449 | else if (mips_abi == N32_ABI) |
be00bddd TS |
12450 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2; |
12451 | ||
12452 | /* Nothing to do for "64". */ | |
252b5132 RH |
12453 | |
12454 | if (mips_32bitmode) | |
12455 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE; | |
12456 | } | |
12457 | ||
12458 | #endif /* OBJ_ELF || OBJ_MAYBE_ELF */ | |
12459 | \f | |
beae10d5 KH |
12460 | typedef struct proc { |
12461 | symbolS *isym; | |
12462 | unsigned long reg_mask; | |
12463 | unsigned long reg_offset; | |
12464 | unsigned long fpreg_mask; | |
12465 | unsigned long fpreg_offset; | |
12466 | unsigned long frame_offset; | |
12467 | unsigned long frame_reg; | |
12468 | unsigned long pc_reg; | |
12469 | } procS; | |
252b5132 RH |
12470 | |
12471 | static procS cur_proc; | |
12472 | static procS *cur_proc_ptr; | |
12473 | static int numprocs; | |
12474 | ||
0a9ef439 | 12475 | /* Fill in an rs_align_code fragment. */ |
a19d8eb0 | 12476 | |
0a9ef439 RH |
12477 | void |
12478 | mips_handle_align (fragp) | |
12479 | fragS *fragp; | |
a19d8eb0 | 12480 | { |
0a9ef439 RH |
12481 | if (fragp->fr_type != rs_align_code) |
12482 | return; | |
12483 | ||
12484 | if (mips_opts.mips16) | |
a19d8eb0 CP |
12485 | { |
12486 | static const unsigned char be_nop[] = { 0x65, 0x00 }; | |
12487 | static const unsigned char le_nop[] = { 0x00, 0x65 }; | |
12488 | ||
0a9ef439 RH |
12489 | int bytes; |
12490 | char *p; | |
a19d8eb0 | 12491 | |
0a9ef439 RH |
12492 | bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix; |
12493 | p = fragp->fr_literal + fragp->fr_fix; | |
12494 | ||
12495 | if (bytes & 1) | |
12496 | { | |
12497 | *p++ = 0; | |
12498 | fragp->fr_fix += 1; | |
12499 | } | |
12500 | ||
12501 | memcpy (p, (target_big_endian ? be_nop : le_nop), 2); | |
12502 | fragp->fr_var = 2; | |
a19d8eb0 CP |
12503 | } |
12504 | ||
0a9ef439 | 12505 | /* For mips32, a nop is a zero, which we trivially get by doing nothing. */ |
a19d8eb0 CP |
12506 | } |
12507 | ||
252b5132 RH |
12508 | static void |
12509 | md_obj_begin () | |
12510 | { | |
12511 | } | |
12512 | ||
12513 | static void | |
12514 | md_obj_end () | |
12515 | { | |
12516 | /* check for premature end, nesting errors, etc */ | |
12517 | if (cur_proc_ptr) | |
9a41af64 | 12518 | as_warn (_("missing .end at end of assembly")); |
252b5132 RH |
12519 | } |
12520 | ||
12521 | static long | |
12522 | get_number () | |
12523 | { | |
12524 | int negative = 0; | |
12525 | long val = 0; | |
12526 | ||
12527 | if (*input_line_pointer == '-') | |
12528 | { | |
12529 | ++input_line_pointer; | |
12530 | negative = 1; | |
12531 | } | |
3882b010 | 12532 | if (!ISDIGIT (*input_line_pointer)) |
252b5132 RH |
12533 | as_bad (_("Expected simple number.")); |
12534 | if (input_line_pointer[0] == '0') | |
12535 | { | |
12536 | if (input_line_pointer[1] == 'x') | |
12537 | { | |
12538 | input_line_pointer += 2; | |
3882b010 | 12539 | while (ISXDIGIT (*input_line_pointer)) |
252b5132 RH |
12540 | { |
12541 | val <<= 4; | |
12542 | val |= hex_value (*input_line_pointer++); | |
12543 | } | |
12544 | return negative ? -val : val; | |
12545 | } | |
12546 | else | |
12547 | { | |
12548 | ++input_line_pointer; | |
3882b010 | 12549 | while (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
12550 | { |
12551 | val <<= 3; | |
12552 | val |= *input_line_pointer++ - '0'; | |
12553 | } | |
12554 | return negative ? -val : val; | |
12555 | } | |
12556 | } | |
3882b010 | 12557 | if (!ISDIGIT (*input_line_pointer)) |
252b5132 RH |
12558 | { |
12559 | printf (_(" *input_line_pointer == '%c' 0x%02x\n"), | |
12560 | *input_line_pointer, *input_line_pointer); | |
12561 | as_warn (_("Invalid number")); | |
12562 | return -1; | |
12563 | } | |
3882b010 | 12564 | while (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
12565 | { |
12566 | val *= 10; | |
12567 | val += *input_line_pointer++ - '0'; | |
12568 | } | |
12569 | return negative ? -val : val; | |
12570 | } | |
12571 | ||
12572 | /* The .file directive; just like the usual .file directive, but there | |
12573 | is an initial number which is the ECOFF file index. */ | |
12574 | ||
12575 | static void | |
12576 | s_file (x) | |
43841e91 | 12577 | int x ATTRIBUTE_UNUSED; |
252b5132 RH |
12578 | { |
12579 | int line; | |
12580 | ||
12581 | line = get_number (); | |
12582 | s_app_file (0); | |
12583 | } | |
12584 | ||
252b5132 RH |
12585 | /* The .end directive. */ |
12586 | ||
12587 | static void | |
12588 | s_mips_end (x) | |
43841e91 | 12589 | int x ATTRIBUTE_UNUSED; |
252b5132 RH |
12590 | { |
12591 | symbolS *p; | |
12592 | int maybe_text; | |
12593 | ||
12594 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
12595 | { | |
12596 | p = get_symbol (); | |
12597 | demand_empty_rest_of_line (); | |
12598 | } | |
12599 | else | |
12600 | p = NULL; | |
12601 | ||
12602 | #ifdef BFD_ASSEMBLER | |
12603 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0) | |
12604 | maybe_text = 1; | |
12605 | else | |
12606 | maybe_text = 0; | |
12607 | #else | |
12608 | if (now_seg != data_section && now_seg != bss_section) | |
12609 | maybe_text = 1; | |
12610 | else | |
12611 | maybe_text = 0; | |
12612 | #endif | |
12613 | ||
12614 | if (!maybe_text) | |
12615 | as_warn (_(".end not in text section")); | |
12616 | ||
12617 | if (!cur_proc_ptr) | |
12618 | { | |
12619 | as_warn (_(".end directive without a preceding .ent directive.")); | |
12620 | demand_empty_rest_of_line (); | |
12621 | return; | |
12622 | } | |
12623 | ||
12624 | if (p != NULL) | |
12625 | { | |
12626 | assert (S_GET_NAME (p)); | |
12627 | if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->isym))) | |
12628 | as_warn (_(".end symbol does not match .ent symbol.")); | |
12629 | } | |
12630 | else | |
12631 | as_warn (_(".end directive missing or unknown symbol")); | |
12632 | ||
12633 | #ifdef MIPS_STABS_ELF | |
12634 | { | |
12635 | segT saved_seg = now_seg; | |
12636 | subsegT saved_subseg = now_subseg; | |
252b5132 | 12637 | valueT dot; |
252b5132 RH |
12638 | expressionS exp; |
12639 | char *fragp; | |
12640 | ||
12641 | dot = frag_now_fix (); | |
12642 | ||
12643 | #ifdef md_flush_pending_output | |
12644 | md_flush_pending_output (); | |
12645 | #endif | |
12646 | ||
12647 | assert (pdr_seg); | |
12648 | subseg_set (pdr_seg, 0); | |
12649 | ||
beae10d5 | 12650 | /* Write the symbol. */ |
252b5132 RH |
12651 | exp.X_op = O_symbol; |
12652 | exp.X_add_symbol = p; | |
12653 | exp.X_add_number = 0; | |
12654 | emit_expr (&exp, 4); | |
12655 | ||
beae10d5 | 12656 | fragp = frag_more (7 * 4); |
252b5132 | 12657 | |
beae10d5 KH |
12658 | md_number_to_chars (fragp, (valueT) cur_proc_ptr->reg_mask, 4); |
12659 | md_number_to_chars (fragp + 4, (valueT) cur_proc_ptr->reg_offset, 4); | |
12660 | md_number_to_chars (fragp + 8, (valueT) cur_proc_ptr->fpreg_mask, 4); | |
12661 | md_number_to_chars (fragp + 12, (valueT) cur_proc_ptr->fpreg_offset, 4); | |
12662 | md_number_to_chars (fragp + 16, (valueT) cur_proc_ptr->frame_offset, 4); | |
12663 | md_number_to_chars (fragp + 20, (valueT) cur_proc_ptr->frame_reg, 4); | |
12664 | md_number_to_chars (fragp + 24, (valueT) cur_proc_ptr->pc_reg, 4); | |
252b5132 RH |
12665 | |
12666 | subseg_set (saved_seg, saved_subseg); | |
12667 | } | |
12668 | #endif | |
12669 | ||
12670 | cur_proc_ptr = NULL; | |
12671 | } | |
12672 | ||
12673 | /* The .aent and .ent directives. */ | |
12674 | ||
12675 | static void | |
12676 | s_mips_ent (aent) | |
12677 | int aent; | |
12678 | { | |
12679 | int number = 0; | |
12680 | symbolS *symbolP; | |
12681 | int maybe_text; | |
12682 | ||
12683 | symbolP = get_symbol (); | |
12684 | if (*input_line_pointer == ',') | |
12685 | input_line_pointer++; | |
12686 | SKIP_WHITESPACE (); | |
3882b010 | 12687 | if (ISDIGIT (*input_line_pointer) |
d9a62219 | 12688 | || *input_line_pointer == '-') |
252b5132 RH |
12689 | number = get_number (); |
12690 | ||
12691 | #ifdef BFD_ASSEMBLER | |
12692 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0) | |
12693 | maybe_text = 1; | |
12694 | else | |
12695 | maybe_text = 0; | |
12696 | #else | |
12697 | if (now_seg != data_section && now_seg != bss_section) | |
12698 | maybe_text = 1; | |
12699 | else | |
12700 | maybe_text = 0; | |
12701 | #endif | |
12702 | ||
12703 | if (!maybe_text) | |
12704 | as_warn (_(".ent or .aent not in text section.")); | |
12705 | ||
12706 | if (!aent && cur_proc_ptr) | |
9a41af64 | 12707 | as_warn (_("missing .end")); |
252b5132 RH |
12708 | |
12709 | if (!aent) | |
12710 | { | |
12711 | cur_proc_ptr = &cur_proc; | |
12712 | memset (cur_proc_ptr, '\0', sizeof (procS)); | |
12713 | ||
12714 | cur_proc_ptr->isym = symbolP; | |
12715 | ||
49309057 | 12716 | symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION; |
252b5132 RH |
12717 | |
12718 | numprocs++; | |
12719 | } | |
12720 | ||
12721 | demand_empty_rest_of_line (); | |
12722 | } | |
12723 | ||
12724 | /* The .frame directive. If the mdebug section is present (IRIX 5 native) | |
bdaaa2e1 | 12725 | then ecoff.c (ecoff_directive_frame) is used. For embedded targets, |
252b5132 | 12726 | s_mips_frame is used so that we can set the PDR information correctly. |
bdaaa2e1 | 12727 | We can't use the ecoff routines because they make reference to the ecoff |
252b5132 RH |
12728 | symbol table (in the mdebug section). */ |
12729 | ||
12730 | static void | |
12731 | s_mips_frame (ignore) | |
2b3c5a5d | 12732 | int ignore ATTRIBUTE_UNUSED; |
252b5132 RH |
12733 | { |
12734 | #ifdef MIPS_STABS_ELF | |
12735 | ||
12736 | long val; | |
12737 | ||
beae10d5 | 12738 | if (cur_proc_ptr == (procS *) NULL) |
252b5132 RH |
12739 | { |
12740 | as_warn (_(".frame outside of .ent")); | |
12741 | demand_empty_rest_of_line (); | |
12742 | return; | |
12743 | } | |
12744 | ||
12745 | cur_proc_ptr->frame_reg = tc_get_register (1); | |
12746 | ||
12747 | SKIP_WHITESPACE (); | |
12748 | if (*input_line_pointer++ != ',' | |
12749 | || get_absolute_expression_and_terminator (&val) != ',') | |
12750 | { | |
12751 | as_warn (_("Bad .frame directive")); | |
12752 | --input_line_pointer; | |
12753 | demand_empty_rest_of_line (); | |
12754 | return; | |
12755 | } | |
12756 | ||
12757 | cur_proc_ptr->frame_offset = val; | |
12758 | cur_proc_ptr->pc_reg = tc_get_register (0); | |
12759 | ||
12760 | demand_empty_rest_of_line (); | |
12761 | #else | |
12762 | s_ignore (ignore); | |
12763 | #endif /* MIPS_STABS_ELF */ | |
12764 | } | |
12765 | ||
bdaaa2e1 KH |
12766 | /* The .fmask and .mask directives. If the mdebug section is present |
12767 | (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For | |
252b5132 | 12768 | embedded targets, s_mips_mask is used so that we can set the PDR |
bdaaa2e1 | 12769 | information correctly. We can't use the ecoff routines because they |
252b5132 RH |
12770 | make reference to the ecoff symbol table (in the mdebug section). */ |
12771 | ||
12772 | static void | |
12773 | s_mips_mask (reg_type) | |
12774 | char reg_type; | |
12775 | { | |
12776 | #ifdef MIPS_STABS_ELF | |
12777 | long mask, off; | |
bdaaa2e1 | 12778 | |
252b5132 RH |
12779 | if (cur_proc_ptr == (procS *) NULL) |
12780 | { | |
12781 | as_warn (_(".mask/.fmask outside of .ent")); | |
12782 | demand_empty_rest_of_line (); | |
12783 | return; | |
12784 | } | |
12785 | ||
12786 | if (get_absolute_expression_and_terminator (&mask) != ',') | |
12787 | { | |
12788 | as_warn (_("Bad .mask/.fmask directive")); | |
12789 | --input_line_pointer; | |
12790 | demand_empty_rest_of_line (); | |
12791 | return; | |
12792 | } | |
12793 | ||
12794 | off = get_absolute_expression (); | |
12795 | ||
12796 | if (reg_type == 'F') | |
12797 | { | |
12798 | cur_proc_ptr->fpreg_mask = mask; | |
12799 | cur_proc_ptr->fpreg_offset = off; | |
12800 | } | |
12801 | else | |
12802 | { | |
12803 | cur_proc_ptr->reg_mask = mask; | |
12804 | cur_proc_ptr->reg_offset = off; | |
12805 | } | |
12806 | ||
12807 | demand_empty_rest_of_line (); | |
12808 | #else | |
12809 | s_ignore (reg_type); | |
12810 | #endif /* MIPS_STABS_ELF */ | |
12811 | } | |
12812 | ||
12813 | /* The .loc directive. */ | |
12814 | ||
12815 | #if 0 | |
12816 | static void | |
12817 | s_loc (x) | |
12818 | int x; | |
12819 | { | |
12820 | symbolS *symbolP; | |
12821 | int lineno; | |
12822 | int addroff; | |
12823 | ||
12824 | assert (now_seg == text_section); | |
12825 | ||
12826 | lineno = get_number (); | |
12827 | addroff = frag_now_fix (); | |
12828 | ||
12829 | symbolP = symbol_new ("", N_SLINE, addroff, frag_now); | |
12830 | S_SET_TYPE (symbolP, N_SLINE); | |
12831 | S_SET_OTHER (symbolP, 0); | |
12832 | S_SET_DESC (symbolP, lineno); | |
12833 | symbolP->sy_segment = now_seg; | |
12834 | } | |
12835 | #endif | |
e7af610e NC |
12836 | |
12837 | /* CPU name/ISA/number mapping table. | |
12838 | ||
12839 | Entries are grouped by type. The first matching CPU or ISA entry | |
12840 | gets chosen by CPU or ISA, so it should be the 'canonical' name | |
12841 | for that type. Entries after that within the type are sorted | |
12842 | alphabetically. | |
12843 | ||
12844 | Case is ignored in comparison, so put the canonical entry in the | |
12845 | appropriate case but everything else in lower case to ease eye pain. */ | |
e972090a NC |
12846 | static const struct mips_cpu_info mips_cpu_info_table[] = |
12847 | { | |
e7af610e NC |
12848 | /* MIPS1 ISA */ |
12849 | { "MIPS1", 1, ISA_MIPS1, CPU_R3000, }, | |
12850 | { "mips", 1, ISA_MIPS1, CPU_R3000, }, | |
12851 | ||
12852 | /* MIPS2 ISA */ | |
12853 | { "MIPS2", 1, ISA_MIPS2, CPU_R6000, }, | |
12854 | ||
12855 | /* MIPS3 ISA */ | |
12856 | { "MIPS3", 1, ISA_MIPS3, CPU_R4000, }, | |
12857 | ||
12858 | /* MIPS4 ISA */ | |
12859 | { "MIPS4", 1, ISA_MIPS4, CPU_R8000, }, | |
12860 | ||
84ea6cf2 NC |
12861 | /* MIPS5 ISA */ |
12862 | { "MIPS5", 1, ISA_MIPS5, CPU_MIPS5, }, | |
12863 | { "Generic-MIPS5", 0, ISA_MIPS5, CPU_MIPS5, }, | |
12864 | ||
e7af610e NC |
12865 | /* MIPS32 ISA */ |
12866 | { "MIPS32", 1, ISA_MIPS32, CPU_MIPS32, }, | |
3c02b2ab | 12867 | { "mipsisa32", 0, ISA_MIPS32, CPU_MIPS32, }, |
e7af610e | 12868 | { "Generic-MIPS32", 0, ISA_MIPS32, CPU_MIPS32, }, |
3c02b2ab EC |
12869 | { "4kc", 0, ISA_MIPS32, CPU_MIPS32, }, |
12870 | { "4km", 0, ISA_MIPS32, CPU_MIPS32, }, | |
12871 | { "4kp", 0, ISA_MIPS32, CPU_MIPS32, }, | |
12872 | ||
12873 | /* For historical reasons. */ | |
12874 | { "MIPS64", 1, ISA_MIPS3, CPU_R4000, }, | |
e7af610e | 12875 | |
84ea6cf2 | 12876 | /* MIPS64 ISA */ |
3c02b2ab | 12877 | { "mipsisa64", 1, ISA_MIPS64, CPU_MIPS64, }, |
84ea6cf2 | 12878 | { "Generic-MIPS64", 0, ISA_MIPS64, CPU_MIPS64, }, |
3c02b2ab EC |
12879 | { "5kc", 0, ISA_MIPS64, CPU_MIPS64, }, |
12880 | { "20kc", 0, ISA_MIPS64, CPU_MIPS64, }, | |
e7af610e NC |
12881 | |
12882 | /* R2000 CPU */ | |
12883 | { "R2000", 0, ISA_MIPS1, CPU_R2000, }, | |
12884 | { "2000", 0, ISA_MIPS1, CPU_R2000, }, | |
12885 | { "2k", 0, ISA_MIPS1, CPU_R2000, }, | |
12886 | { "r2k", 0, ISA_MIPS1, CPU_R2000, }, | |
12887 | ||
12888 | /* R3000 CPU */ | |
12889 | { "R3000", 0, ISA_MIPS1, CPU_R3000, }, | |
12890 | { "3000", 0, ISA_MIPS1, CPU_R3000, }, | |
12891 | { "3k", 0, ISA_MIPS1, CPU_R3000, }, | |
12892 | { "r3k", 0, ISA_MIPS1, CPU_R3000, }, | |
12893 | ||
12894 | /* TX3900 CPU */ | |
12895 | { "R3900", 0, ISA_MIPS1, CPU_R3900, }, | |
12896 | { "3900", 0, ISA_MIPS1, CPU_R3900, }, | |
e972090a | 12897 | { "mipstx39", 0, ISA_MIPS1, CPU_R3900, }, |
e7af610e NC |
12898 | |
12899 | /* R4000 CPU */ | |
12900 | { "R4000", 0, ISA_MIPS3, CPU_R4000, }, | |
12901 | { "4000", 0, ISA_MIPS3, CPU_R4000, }, | |
12902 | { "4k", 0, ISA_MIPS3, CPU_R4000, }, /* beware */ | |
12903 | { "r4k", 0, ISA_MIPS3, CPU_R4000, }, | |
12904 | ||
12905 | /* R4010 CPU */ | |
12906 | { "R4010", 0, ISA_MIPS2, CPU_R4010, }, | |
12907 | { "4010", 0, ISA_MIPS2, CPU_R4010, }, | |
12908 | ||
12909 | /* R4400 CPU */ | |
12910 | { "R4400", 0, ISA_MIPS3, CPU_R4400, }, | |
12911 | { "4400", 0, ISA_MIPS3, CPU_R4400, }, | |
12912 | ||
12913 | /* R4600 CPU */ | |
12914 | { "R4600", 0, ISA_MIPS3, CPU_R4600, }, | |
12915 | { "4600", 0, ISA_MIPS3, CPU_R4600, }, | |
12916 | { "mips64orion", 0, ISA_MIPS3, CPU_R4600, }, | |
12917 | { "orion", 0, ISA_MIPS3, CPU_R4600, }, | |
12918 | ||
12919 | /* R4650 CPU */ | |
12920 | { "R4650", 0, ISA_MIPS3, CPU_R4650, }, | |
12921 | { "4650", 0, ISA_MIPS3, CPU_R4650, }, | |
12922 | ||
12923 | /* R6000 CPU */ | |
12924 | { "R6000", 0, ISA_MIPS2, CPU_R6000, }, | |
12925 | { "6000", 0, ISA_MIPS2, CPU_R6000, }, | |
12926 | { "6k", 0, ISA_MIPS2, CPU_R6000, }, | |
12927 | { "r6k", 0, ISA_MIPS2, CPU_R6000, }, | |
12928 | ||
12929 | /* R8000 CPU */ | |
12930 | { "R8000", 0, ISA_MIPS4, CPU_R8000, }, | |
12931 | { "8000", 0, ISA_MIPS4, CPU_R8000, }, | |
12932 | { "8k", 0, ISA_MIPS4, CPU_R8000, }, | |
12933 | { "r8k", 0, ISA_MIPS4, CPU_R8000, }, | |
12934 | ||
12935 | /* R10000 CPU */ | |
12936 | { "R10000", 0, ISA_MIPS4, CPU_R10000, }, | |
12937 | { "10000", 0, ISA_MIPS4, CPU_R10000, }, | |
12938 | { "10k", 0, ISA_MIPS4, CPU_R10000, }, | |
12939 | { "r10k", 0, ISA_MIPS4, CPU_R10000, }, | |
12940 | ||
d1cf510e NC |
12941 | /* R12000 CPU */ |
12942 | { "R12000", 0, ISA_MIPS4, CPU_R12000, }, | |
12943 | { "12000", 0, ISA_MIPS4, CPU_R12000, }, | |
12944 | { "12k", 0, ISA_MIPS4, CPU_R12000, }, | |
12945 | { "r12k", 0, ISA_MIPS4, CPU_R12000, }, | |
12946 | ||
e7af610e NC |
12947 | /* VR4100 CPU */ |
12948 | { "VR4100", 0, ISA_MIPS3, CPU_VR4100, }, | |
12949 | { "4100", 0, ISA_MIPS3, CPU_VR4100, }, | |
12950 | { "mips64vr4100", 0, ISA_MIPS3, CPU_VR4100, }, | |
12951 | { "r4100", 0, ISA_MIPS3, CPU_VR4100, }, | |
12952 | ||
12953 | /* VR4111 CPU */ | |
12954 | { "VR4111", 0, ISA_MIPS3, CPU_R4111, }, | |
12955 | { "4111", 0, ISA_MIPS3, CPU_R4111, }, | |
12956 | { "mips64vr4111", 0, ISA_MIPS3, CPU_R4111, }, | |
12957 | { "r4111", 0, ISA_MIPS3, CPU_R4111, }, | |
12958 | ||
12959 | /* VR4300 CPU */ | |
12960 | { "VR4300", 0, ISA_MIPS3, CPU_R4300, }, | |
12961 | { "4300", 0, ISA_MIPS3, CPU_R4300, }, | |
12962 | { "mips64vr4300", 0, ISA_MIPS3, CPU_R4300, }, | |
12963 | { "r4300", 0, ISA_MIPS3, CPU_R4300, }, | |
12964 | ||
12965 | /* VR5000 CPU */ | |
12966 | { "VR5000", 0, ISA_MIPS4, CPU_R5000, }, | |
12967 | { "5000", 0, ISA_MIPS4, CPU_R5000, }, | |
12968 | { "5k", 0, ISA_MIPS4, CPU_R5000, }, | |
12969 | { "mips64vr5000", 0, ISA_MIPS4, CPU_R5000, }, | |
12970 | { "r5000", 0, ISA_MIPS4, CPU_R5000, }, | |
12971 | { "r5200", 0, ISA_MIPS4, CPU_R5000, }, | |
18ae5d72 | 12972 | { "rm5200", 0, ISA_MIPS4, CPU_R5000, }, |
e7af610e | 12973 | { "r5230", 0, ISA_MIPS4, CPU_R5000, }, |
18ae5d72 | 12974 | { "rm5230", 0, ISA_MIPS4, CPU_R5000, }, |
e7af610e | 12975 | { "r5231", 0, ISA_MIPS4, CPU_R5000, }, |
18ae5d72 | 12976 | { "rm5231", 0, ISA_MIPS4, CPU_R5000, }, |
e7af610e | 12977 | { "r5261", 0, ISA_MIPS4, CPU_R5000, }, |
18ae5d72 | 12978 | { "rm5261", 0, ISA_MIPS4, CPU_R5000, }, |
e7af610e | 12979 | { "r5721", 0, ISA_MIPS4, CPU_R5000, }, |
18ae5d72 | 12980 | { "rm5721", 0, ISA_MIPS4, CPU_R5000, }, |
e7af610e NC |
12981 | { "r5k", 0, ISA_MIPS4, CPU_R5000, }, |
12982 | { "r7000", 0, ISA_MIPS4, CPU_R5000, }, | |
12983 | ||
c6c98b38 NC |
12984 | /* SiByte SB-1 CPU */ |
12985 | { "SB-1", 0, ISA_MIPS64, CPU_SB1, }, | |
e972090a | 12986 | { "sb-1250", 0, ISA_MIPS64, CPU_SB1, }, |
c6c98b38 NC |
12987 | { "sb1", 0, ISA_MIPS64, CPU_SB1, }, |
12988 | { "sb1250", 0, ISA_MIPS64, CPU_SB1, }, | |
12989 | ||
beae10d5 | 12990 | /* End marker. */ |
e7af610e NC |
12991 | { NULL, 0, 0, 0, }, |
12992 | }; | |
12993 | ||
12994 | static const struct mips_cpu_info * | |
12995 | mips_cpu_info_from_name (name) | |
12996 | const char *name; | |
12997 | { | |
12998 | int i; | |
12999 | ||
13000 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
beae10d5 | 13001 | if (strcasecmp (name, mips_cpu_info_table[i].name) == 0) |
e7af610e NC |
13002 | return (&mips_cpu_info_table[i]); |
13003 | ||
e972090a | 13004 | return NULL; |
e7af610e NC |
13005 | } |
13006 | ||
13007 | static const struct mips_cpu_info * | |
13008 | mips_cpu_info_from_isa (isa) | |
13009 | int isa; | |
13010 | { | |
13011 | int i; | |
13012 | ||
13013 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
13014 | if (mips_cpu_info_table[i].is_isa | |
13015 | && isa == mips_cpu_info_table[i].isa) | |
13016 | return (&mips_cpu_info_table[i]); | |
13017 | ||
e972090a | 13018 | return NULL; |
e7af610e NC |
13019 | } |
13020 | ||
13021 | static const struct mips_cpu_info * | |
13022 | mips_cpu_info_from_cpu (cpu) | |
13023 | int cpu; | |
13024 | { | |
13025 | int i; | |
13026 | ||
13027 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
13028 | if (!mips_cpu_info_table[i].is_isa | |
13029 | && cpu == mips_cpu_info_table[i].cpu) | |
13030 | return (&mips_cpu_info_table[i]); | |
13031 | ||
e972090a | 13032 | return NULL; |
e7af610e | 13033 | } |