Commit | Line | Data |
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252b5132 | 1 | /* tc-mips.c -- assemble code for a MIPS chip. |
f7e42eb4 | 2 | Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001 |
82efde3a | 3 | Free Software Foundation, Inc. |
252b5132 RH |
4 | Contributed by the OSF and Ralph Campbell. |
5 | Written by Keith Knowles and Ralph Campbell, working independently. | |
6 | Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus | |
7 | Support. | |
8 | ||
9 | This file is part of GAS. | |
10 | ||
11 | GAS is free software; you can redistribute it and/or modify | |
12 | it under the terms of the GNU General Public License as published by | |
13 | the Free Software Foundation; either version 2, or (at your option) | |
14 | any later version. | |
15 | ||
16 | GAS is distributed in the hope that it will be useful, | |
17 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | GNU General Public License for more details. | |
20 | ||
21 | You should have received a copy of the GNU General Public License | |
22 | along with GAS; see the file COPYING. If not, write to the Free | |
23 | Software Foundation, 59 Temple Place - Suite 330, Boston, MA | |
24 | 02111-1307, USA. */ | |
25 | ||
26 | #include "as.h" | |
27 | #include "config.h" | |
28 | #include "subsegs.h" | |
29 | ||
30 | #include <ctype.h> | |
31 | ||
32 | #ifdef USE_STDARG | |
33 | #include <stdarg.h> | |
34 | #endif | |
35 | #ifdef USE_VARARGS | |
36 | #include <varargs.h> | |
37 | #endif | |
38 | ||
39 | #include "opcode/mips.h" | |
40 | #include "itbl-ops.h" | |
41 | ||
42 | #ifdef DEBUG | |
43 | #define DBG(x) printf x | |
44 | #else | |
45 | #define DBG(x) | |
46 | #endif | |
47 | ||
48 | #ifdef OBJ_MAYBE_ELF | |
49 | /* Clean up namespace so we can include obj-elf.h too. */ | |
50 | static int mips_output_flavor PARAMS ((void)); | |
51 | static int mips_output_flavor () { return OUTPUT_FLAVOR; } | |
52 | #undef OBJ_PROCESS_STAB | |
53 | #undef OUTPUT_FLAVOR | |
54 | #undef S_GET_ALIGN | |
55 | #undef S_GET_SIZE | |
56 | #undef S_SET_ALIGN | |
57 | #undef S_SET_SIZE | |
252b5132 RH |
58 | #undef obj_frob_file |
59 | #undef obj_frob_file_after_relocs | |
60 | #undef obj_frob_symbol | |
61 | #undef obj_pop_insert | |
62 | #undef obj_sec_sym_ok_for_reloc | |
63 | #undef OBJ_COPY_SYMBOL_ATTRIBUTES | |
64 | ||
65 | #include "obj-elf.h" | |
66 | /* Fix any of them that we actually care about. */ | |
67 | #undef OUTPUT_FLAVOR | |
68 | #define OUTPUT_FLAVOR mips_output_flavor() | |
69 | #endif | |
70 | ||
71 | #if defined (OBJ_ELF) | |
72 | #include "elf/mips.h" | |
73 | #endif | |
74 | ||
75 | #ifndef ECOFF_DEBUGGING | |
76 | #define NO_ECOFF_DEBUGGING | |
77 | #define ECOFF_DEBUGGING 0 | |
78 | #endif | |
79 | ||
80 | #include "ecoff.h" | |
81 | ||
82 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
83 | static char *mips_regmask_frag; | |
84 | #endif | |
85 | ||
86 | #define AT 1 | |
87 | #define TREG 24 | |
88 | #define PIC_CALL_REG 25 | |
89 | #define KT0 26 | |
90 | #define KT1 27 | |
91 | #define GP 28 | |
92 | #define SP 29 | |
93 | #define FP 30 | |
94 | #define RA 31 | |
95 | ||
96 | #define ILLEGAL_REG (32) | |
97 | ||
98 | /* Allow override of standard little-endian ECOFF format. */ | |
99 | ||
100 | #ifndef ECOFF_LITTLE_FORMAT | |
101 | #define ECOFF_LITTLE_FORMAT "ecoff-littlemips" | |
102 | #endif | |
103 | ||
104 | extern int target_big_endian; | |
105 | ||
106 | /* 1 is we should use the 64 bit MIPS ELF ABI, 0 if we should use the | |
107 | 32 bit ABI. This has no meaning for ECOFF. | |
108 | Note that the default is always 32 bit, even if "configured" for | |
109 | 64 bit [e.g. --target=mips64-elf]. */ | |
110 | static int mips_64; | |
111 | ||
112 | /* The default target format to use. */ | |
beae10d5 | 113 | |
252b5132 RH |
114 | const char * |
115 | mips_target_format () | |
116 | { | |
117 | switch (OUTPUT_FLAVOR) | |
118 | { | |
119 | case bfd_target_aout_flavour: | |
120 | return target_big_endian ? "a.out-mips-big" : "a.out-mips-little"; | |
121 | case bfd_target_ecoff_flavour: | |
122 | return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT; | |
056350c6 NC |
123 | case bfd_target_coff_flavour: |
124 | return "pe-mips"; | |
252b5132 | 125 | case bfd_target_elf_flavour: |
8614eeee UC |
126 | #ifdef TE_TMIPS |
127 | /* This is traditional mips */ | |
128 | return (target_big_endian | |
af9539e4 L |
129 | ? (mips_64 ? "elf64-tradbigmips" : "elf32-tradbigmips") |
130 | : (mips_64 ? "elf64-tradlittlemips" : "elf32-tradlittlemips")); | |
8614eeee | 131 | #else |
252b5132 RH |
132 | return (target_big_endian |
133 | ? (mips_64 ? "elf64-bigmips" : "elf32-bigmips") | |
134 | : (mips_64 ? "elf64-littlemips" : "elf32-littlemips")); | |
8614eeee | 135 | #endif |
252b5132 RH |
136 | default: |
137 | abort (); | |
138 | return NULL; | |
139 | } | |
140 | } | |
141 | ||
142 | /* The name of the readonly data section. */ | |
143 | #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \ | |
144 | ? ".data" \ | |
145 | : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \ | |
146 | ? ".rdata" \ | |
056350c6 NC |
147 | : OUTPUT_FLAVOR == bfd_target_coff_flavour \ |
148 | ? ".rdata" \ | |
252b5132 RH |
149 | : OUTPUT_FLAVOR == bfd_target_elf_flavour \ |
150 | ? ".rodata" \ | |
151 | : (abort (), "")) | |
152 | ||
153 | /* This is the set of options which may be modified by the .set | |
154 | pseudo-op. We use a struct so that .set push and .set pop are more | |
155 | reliable. */ | |
156 | ||
e972090a NC |
157 | struct mips_set_options |
158 | { | |
252b5132 RH |
159 | /* MIPS ISA (Instruction Set Architecture) level. This is set to -1 |
160 | if it has not been initialized. Changed by `.set mipsN', and the | |
161 | -mipsN command line option, and the default CPU. */ | |
162 | int isa; | |
163 | /* Whether we are assembling for the mips16 processor. 0 if we are | |
164 | not, 1 if we are, and -1 if the value has not been initialized. | |
165 | Changed by `.set mips16' and `.set nomips16', and the -mips16 and | |
166 | -nomips16 command line options, and the default CPU. */ | |
167 | int mips16; | |
168 | /* Non-zero if we should not reorder instructions. Changed by `.set | |
169 | reorder' and `.set noreorder'. */ | |
170 | int noreorder; | |
171 | /* Non-zero if we should not permit the $at ($1) register to be used | |
172 | in instructions. Changed by `.set at' and `.set noat'. */ | |
173 | int noat; | |
174 | /* Non-zero if we should warn when a macro instruction expands into | |
175 | more than one machine instruction. Changed by `.set nomacro' and | |
176 | `.set macro'. */ | |
177 | int warn_about_macros; | |
178 | /* Non-zero if we should not move instructions. Changed by `.set | |
179 | move', `.set volatile', `.set nomove', and `.set novolatile'. */ | |
180 | int nomove; | |
181 | /* Non-zero if we should not optimize branches by moving the target | |
182 | of the branch into the delay slot. Actually, we don't perform | |
183 | this optimization anyhow. Changed by `.set bopt' and `.set | |
184 | nobopt'. */ | |
185 | int nobopt; | |
186 | /* Non-zero if we should not autoextend mips16 instructions. | |
187 | Changed by `.set autoextend' and `.set noautoextend'. */ | |
188 | int noautoextend; | |
189 | }; | |
190 | ||
191 | /* This is the struct we use to hold the current set of options. Note | |
e7af610e NC |
192 | that we must set the isa field to ISA_UNKNOWN and the mips16 field to |
193 | -1 to indicate that they have not been initialized. */ | |
252b5132 | 194 | |
e972090a NC |
195 | static struct mips_set_options mips_opts = |
196 | { | |
e7af610e NC |
197 | ISA_UNKNOWN, -1, 0, 0, 0, 0, 0, 0 |
198 | }; | |
252b5132 RH |
199 | |
200 | /* These variables are filled in with the masks of registers used. | |
201 | The object format code reads them and puts them in the appropriate | |
202 | place. */ | |
203 | unsigned long mips_gprmask; | |
204 | unsigned long mips_cprmask[4]; | |
205 | ||
206 | /* MIPS ISA we are using for this output file. */ | |
e7af610e | 207 | static int file_mips_isa = ISA_UNKNOWN; |
252b5132 | 208 | |
ec68c924 | 209 | /* The argument of the -mcpu= flag. Historical for code generation. */ |
e7af610e | 210 | static int mips_cpu = CPU_UNKNOWN; |
252b5132 | 211 | |
ec68c924 EC |
212 | /* The argument of the -march= flag. The architecture we are assembling. */ |
213 | static int mips_arch = CPU_UNKNOWN; | |
214 | ||
215 | /* The argument of the -mtune= flag. The architecture for which we | |
216 | are optimizing. */ | |
217 | static int mips_tune = CPU_UNKNOWN; | |
218 | ||
bdaaa2e1 | 219 | /* The argument of the -mabi= flag. */ |
e972090a | 220 | static char * mips_abi_string = 0; |
252b5132 | 221 | |
bdaaa2e1 | 222 | /* Wether we should mark the file EABI64 or EABI32. */ |
252b5132 RH |
223 | static int mips_eabi64 = 0; |
224 | ||
225 | /* If they asked for mips1 or mips2 and a cpu that is | |
bdaaa2e1 | 226 | mips3 or greater, then mark the object file 32BITMODE. */ |
252b5132 RH |
227 | static int mips_32bitmode = 0; |
228 | ||
bdaaa2e1 | 229 | /* True if -mgp32 was passed. */ |
c97ef257 AH |
230 | static int mips_gp32 = 0; |
231 | ||
9ce8a5dd GRK |
232 | /* Some ISA's have delay slots for instructions which read or write |
233 | from a coprocessor (eg. mips1-mips3); some don't (eg mips4). | |
bdaaa2e1 | 234 | Return true if instructions marked INSN_LOAD_COPROC_DELAY, |
9ce8a5dd GRK |
235 | INSN_COPROC_MOVE_DELAY, or INSN_WRITE_COND_CODE actually have a |
236 | delay slot in this ISA. The uses of this macro assume that any | |
237 | ISA that has delay slots for one of these, has them for all. They | |
238 | also assume that ISAs which don't have delays for these insns, don't | |
bdaaa2e1 | 239 | have delays for the INSN_LOAD_MEMORY_DELAY instructions either. */ |
9ce8a5dd | 240 | #define ISA_HAS_COPROC_DELAYS(ISA) ( \ |
e7af610e NC |
241 | (ISA) == ISA_MIPS1 \ |
242 | || (ISA) == ISA_MIPS2 \ | |
243 | || (ISA) == ISA_MIPS3 \ | |
9ce8a5dd GRK |
244 | ) |
245 | ||
bdaaa2e1 | 246 | /* Return true if ISA supports 64 bit gp register instructions. */ |
9ce8a5dd | 247 | #define ISA_HAS_64BIT_REGS(ISA) ( \ |
e7af610e NC |
248 | (ISA) == ISA_MIPS3 \ |
249 | || (ISA) == ISA_MIPS4 \ | |
84ea6cf2 | 250 | || (ISA) == ISA_MIPS5 \ |
d1cf510e | 251 | || (ISA) == ISA_MIPS64 \ |
9ce8a5dd GRK |
252 | ) |
253 | ||
bdaaa2e1 | 254 | /* Whether the processor uses hardware interlocks to protect |
252b5132 | 255 | reads from the HI and LO registers, and thus does not |
ec68c924 | 256 | require nops to be inserted. */ |
252b5132 | 257 | |
ec68c924 | 258 | #define hilo_interlocks (mips_arch == CPU_R4010 \ |
252b5132 RH |
259 | ) |
260 | ||
261 | /* Whether the processor uses hardware interlocks to protect reads | |
262 | from the GPRs, and thus does not require nops to be inserted. */ | |
263 | #define gpr_interlocks \ | |
e7af610e | 264 | (mips_opts.isa != ISA_MIPS1 \ |
ec68c924 | 265 | || mips_arch == CPU_R3900) |
252b5132 RH |
266 | |
267 | /* As with other "interlocks" this is used by hardware that has FP | |
268 | (co-processor) interlocks. */ | |
bdaaa2e1 | 269 | /* Itbl support may require additional care here. */ |
ec68c924 | 270 | #define cop_interlocks (mips_arch == CPU_R4300 \ |
252b5132 RH |
271 | ) |
272 | ||
6b76fefe CM |
273 | /* Is this a mfhi or mflo instruction? */ |
274 | #define MF_HILO_INSN(PINFO) \ | |
275 | ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO)) | |
276 | ||
252b5132 RH |
277 | /* MIPS PIC level. */ |
278 | ||
e972090a NC |
279 | enum mips_pic_level |
280 | { | |
252b5132 RH |
281 | /* Do not generate PIC code. */ |
282 | NO_PIC, | |
283 | ||
284 | /* Generate PIC code as in Irix 4. This is not implemented, and I'm | |
285 | not sure what it is supposed to do. */ | |
286 | IRIX4_PIC, | |
287 | ||
288 | /* Generate PIC code as in the SVR4 MIPS ABI. */ | |
289 | SVR4_PIC, | |
290 | ||
291 | /* Generate PIC code without using a global offset table: the data | |
292 | segment has a maximum size of 64K, all data references are off | |
293 | the $gp register, and all text references are PC relative. This | |
294 | is used on some embedded systems. */ | |
295 | EMBEDDED_PIC | |
296 | }; | |
297 | ||
298 | static enum mips_pic_level mips_pic; | |
299 | ||
39c0a331 L |
300 | /* Warn about all NOPS that the assembler generates. */ |
301 | static int warn_nops = 0; | |
302 | ||
252b5132 RH |
303 | /* 1 if we should generate 32 bit offsets from the GP register in |
304 | SVR4_PIC mode. Currently has no meaning in other modes. */ | |
305 | static int mips_big_got; | |
306 | ||
307 | /* 1 if trap instructions should used for overflow rather than break | |
308 | instructions. */ | |
309 | static int mips_trap; | |
310 | ||
119d663a NC |
311 | /* 1 if double width floating point constants should not be constructed |
312 | by a assembling two single width halves into two single width floating | |
313 | point registers which just happen to alias the double width destination | |
314 | register. On some architectures this aliasing can be disabled by a bit | |
d547a75e | 315 | in the status register, and the setting of this bit cannot be determined |
119d663a NC |
316 | automatically at assemble time. */ |
317 | static int mips_disable_float_construction; | |
318 | ||
252b5132 RH |
319 | /* Non-zero if any .set noreorder directives were used. */ |
320 | ||
321 | static int mips_any_noreorder; | |
322 | ||
6b76fefe CM |
323 | /* Non-zero if nops should be inserted when the register referenced in |
324 | an mfhi/mflo instruction is read in the next two instructions. */ | |
325 | static int mips_7000_hilo_fix; | |
326 | ||
252b5132 | 327 | /* The size of the small data section. */ |
156c2f8b | 328 | static unsigned int g_switch_value = 8; |
252b5132 RH |
329 | /* Whether the -G option was used. */ |
330 | static int g_switch_seen = 0; | |
331 | ||
332 | #define N_RMASK 0xc4 | |
333 | #define N_VFP 0xd4 | |
334 | ||
335 | /* If we can determine in advance that GP optimization won't be | |
336 | possible, we can skip the relaxation stuff that tries to produce | |
337 | GP-relative references. This makes delay slot optimization work | |
338 | better. | |
339 | ||
340 | This function can only provide a guess, but it seems to work for | |
fba2b7f9 GK |
341 | gcc output. It needs to guess right for gcc, otherwise gcc |
342 | will put what it thinks is a GP-relative instruction in a branch | |
343 | delay slot. | |
252b5132 RH |
344 | |
345 | I don't know if a fix is needed for the SVR4_PIC mode. I've only | |
346 | fixed it for the non-PIC mode. KR 95/04/07 */ | |
347 | static int nopic_need_relax PARAMS ((symbolS *, int)); | |
348 | ||
349 | /* handle of the OPCODE hash table */ | |
350 | static struct hash_control *op_hash = NULL; | |
351 | ||
352 | /* The opcode hash table we use for the mips16. */ | |
353 | static struct hash_control *mips16_op_hash = NULL; | |
354 | ||
355 | /* This array holds the chars that always start a comment. If the | |
356 | pre-processor is disabled, these aren't very useful */ | |
357 | const char comment_chars[] = "#"; | |
358 | ||
359 | /* This array holds the chars that only start a comment at the beginning of | |
360 | a line. If the line seems to have the form '# 123 filename' | |
361 | .line and .file directives will appear in the pre-processed output */ | |
362 | /* Note that input_file.c hand checks for '#' at the beginning of the | |
363 | first line of the input file. This is because the compiler outputs | |
bdaaa2e1 | 364 | #NO_APP at the beginning of its output. */ |
252b5132 RH |
365 | /* Also note that C style comments are always supported. */ |
366 | const char line_comment_chars[] = "#"; | |
367 | ||
bdaaa2e1 | 368 | /* This array holds machine specific line separator characters. */ |
63a0b638 | 369 | const char line_separator_chars[] = ";"; |
252b5132 RH |
370 | |
371 | /* Chars that can be used to separate mant from exp in floating point nums */ | |
372 | const char EXP_CHARS[] = "eE"; | |
373 | ||
374 | /* Chars that mean this number is a floating point constant */ | |
375 | /* As in 0f12.456 */ | |
376 | /* or 0d1.2345e12 */ | |
377 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; | |
378 | ||
379 | /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be | |
380 | changed in read.c . Ideally it shouldn't have to know about it at all, | |
381 | but nothing is ideal around here. | |
382 | */ | |
383 | ||
384 | static char *insn_error; | |
385 | ||
386 | static int auto_align = 1; | |
387 | ||
388 | /* When outputting SVR4 PIC code, the assembler needs to know the | |
389 | offset in the stack frame from which to restore the $gp register. | |
390 | This is set by the .cprestore pseudo-op, and saved in this | |
391 | variable. */ | |
392 | static offsetT mips_cprestore_offset = -1; | |
393 | ||
394 | /* This is the register which holds the stack frame, as set by the | |
395 | .frame pseudo-op. This is needed to implement .cprestore. */ | |
396 | static int mips_frame_reg = SP; | |
397 | ||
398 | /* To output NOP instructions correctly, we need to keep information | |
399 | about the previous two instructions. */ | |
400 | ||
401 | /* Whether we are optimizing. The default value of 2 means to remove | |
402 | unneeded NOPs and swap branch instructions when possible. A value | |
403 | of 1 means to not swap branches. A value of 0 means to always | |
404 | insert NOPs. */ | |
405 | static int mips_optimize = 2; | |
406 | ||
407 | /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is | |
408 | equivalent to seeing no -g option at all. */ | |
409 | static int mips_debug = 0; | |
410 | ||
411 | /* The previous instruction. */ | |
412 | static struct mips_cl_insn prev_insn; | |
413 | ||
414 | /* The instruction before prev_insn. */ | |
415 | static struct mips_cl_insn prev_prev_insn; | |
416 | ||
417 | /* If we don't want information for prev_insn or prev_prev_insn, we | |
418 | point the insn_mo field at this dummy integer. */ | |
43841e91 | 419 | static const struct mips_opcode dummy_opcode = { NULL, NULL, 0, 0, 0, 0 }; |
252b5132 RH |
420 | |
421 | /* Non-zero if prev_insn is valid. */ | |
422 | static int prev_insn_valid; | |
423 | ||
424 | /* The frag for the previous instruction. */ | |
425 | static struct frag *prev_insn_frag; | |
426 | ||
427 | /* The offset into prev_insn_frag for the previous instruction. */ | |
428 | static long prev_insn_where; | |
429 | ||
430 | /* The reloc type for the previous instruction, if any. */ | |
431 | static bfd_reloc_code_real_type prev_insn_reloc_type; | |
432 | ||
433 | /* The reloc for the previous instruction, if any. */ | |
434 | static fixS *prev_insn_fixp; | |
435 | ||
436 | /* Non-zero if the previous instruction was in a delay slot. */ | |
437 | static int prev_insn_is_delay_slot; | |
438 | ||
439 | /* Non-zero if the previous instruction was in a .set noreorder. */ | |
440 | static int prev_insn_unreordered; | |
441 | ||
442 | /* Non-zero if the previous instruction uses an extend opcode (if | |
443 | mips16). */ | |
444 | static int prev_insn_extended; | |
445 | ||
446 | /* Non-zero if the previous previous instruction was in a .set | |
447 | noreorder. */ | |
448 | static int prev_prev_insn_unreordered; | |
449 | ||
450 | /* If this is set, it points to a frag holding nop instructions which | |
451 | were inserted before the start of a noreorder section. If those | |
452 | nops turn out to be unnecessary, the size of the frag can be | |
453 | decreased. */ | |
454 | static fragS *prev_nop_frag; | |
455 | ||
456 | /* The number of nop instructions we created in prev_nop_frag. */ | |
457 | static int prev_nop_frag_holds; | |
458 | ||
459 | /* The number of nop instructions that we know we need in | |
bdaaa2e1 | 460 | prev_nop_frag. */ |
252b5132 RH |
461 | static int prev_nop_frag_required; |
462 | ||
463 | /* The number of instructions we've seen since prev_nop_frag. */ | |
464 | static int prev_nop_frag_since; | |
465 | ||
466 | /* For ECOFF and ELF, relocations against symbols are done in two | |
467 | parts, with a HI relocation and a LO relocation. Each relocation | |
468 | has only 16 bits of space to store an addend. This means that in | |
469 | order for the linker to handle carries correctly, it must be able | |
470 | to locate both the HI and the LO relocation. This means that the | |
471 | relocations must appear in order in the relocation table. | |
472 | ||
473 | In order to implement this, we keep track of each unmatched HI | |
474 | relocation. We then sort them so that they immediately precede the | |
bdaaa2e1 | 475 | corresponding LO relocation. */ |
252b5132 | 476 | |
e972090a NC |
477 | struct mips_hi_fixup |
478 | { | |
252b5132 RH |
479 | /* Next HI fixup. */ |
480 | struct mips_hi_fixup *next; | |
481 | /* This fixup. */ | |
482 | fixS *fixp; | |
483 | /* The section this fixup is in. */ | |
484 | segT seg; | |
485 | }; | |
486 | ||
487 | /* The list of unmatched HI relocs. */ | |
488 | ||
489 | static struct mips_hi_fixup *mips_hi_fixup_list; | |
490 | ||
491 | /* Map normal MIPS register numbers to mips16 register numbers. */ | |
492 | ||
493 | #define X ILLEGAL_REG | |
e972090a NC |
494 | static const int mips32_to_16_reg_map[] = |
495 | { | |
252b5132 RH |
496 | X, X, 2, 3, 4, 5, 6, 7, |
497 | X, X, X, X, X, X, X, X, | |
498 | 0, 1, X, X, X, X, X, X, | |
499 | X, X, X, X, X, X, X, X | |
500 | }; | |
501 | #undef X | |
502 | ||
503 | /* Map mips16 register numbers to normal MIPS register numbers. */ | |
504 | ||
e972090a NC |
505 | static const unsigned int mips16_to_32_reg_map[] = |
506 | { | |
252b5132 RH |
507 | 16, 17, 2, 3, 4, 5, 6, 7 |
508 | }; | |
509 | \f | |
510 | /* Since the MIPS does not have multiple forms of PC relative | |
511 | instructions, we do not have to do relaxing as is done on other | |
512 | platforms. However, we do have to handle GP relative addressing | |
513 | correctly, which turns out to be a similar problem. | |
514 | ||
515 | Every macro that refers to a symbol can occur in (at least) two | |
516 | forms, one with GP relative addressing and one without. For | |
517 | example, loading a global variable into a register generally uses | |
518 | a macro instruction like this: | |
519 | lw $4,i | |
520 | If i can be addressed off the GP register (this is true if it is in | |
521 | the .sbss or .sdata section, or if it is known to be smaller than | |
522 | the -G argument) this will generate the following instruction: | |
523 | lw $4,i($gp) | |
524 | This instruction will use a GPREL reloc. If i can not be addressed | |
525 | off the GP register, the following instruction sequence will be used: | |
526 | lui $at,i | |
527 | lw $4,i($at) | |
528 | In this case the first instruction will have a HI16 reloc, and the | |
529 | second reloc will have a LO16 reloc. Both relocs will be against | |
530 | the symbol i. | |
531 | ||
532 | The issue here is that we may not know whether i is GP addressable | |
533 | until after we see the instruction that uses it. Therefore, we | |
534 | want to be able to choose the final instruction sequence only at | |
535 | the end of the assembly. This is similar to the way other | |
536 | platforms choose the size of a PC relative instruction only at the | |
537 | end of assembly. | |
538 | ||
539 | When generating position independent code we do not use GP | |
540 | addressing in quite the same way, but the issue still arises as | |
541 | external symbols and local symbols must be handled differently. | |
542 | ||
543 | We handle these issues by actually generating both possible | |
544 | instruction sequences. The longer one is put in a frag_var with | |
545 | type rs_machine_dependent. We encode what to do with the frag in | |
546 | the subtype field. We encode (1) the number of existing bytes to | |
547 | replace, (2) the number of new bytes to use, (3) the offset from | |
548 | the start of the existing bytes to the first reloc we must generate | |
549 | (that is, the offset is applied from the start of the existing | |
550 | bytes after they are replaced by the new bytes, if any), (4) the | |
551 | offset from the start of the existing bytes to the second reloc, | |
552 | (5) whether a third reloc is needed (the third reloc is always four | |
553 | bytes after the second reloc), and (6) whether to warn if this | |
554 | variant is used (this is sometimes needed if .set nomacro or .set | |
555 | noat is in effect). All these numbers are reasonably small. | |
556 | ||
557 | Generating two instruction sequences must be handled carefully to | |
558 | ensure that delay slots are handled correctly. Fortunately, there | |
559 | are a limited number of cases. When the second instruction | |
560 | sequence is generated, append_insn is directed to maintain the | |
561 | existing delay slot information, so it continues to apply to any | |
562 | code after the second instruction sequence. This means that the | |
563 | second instruction sequence must not impose any requirements not | |
564 | required by the first instruction sequence. | |
565 | ||
566 | These variant frags are then handled in functions called by the | |
567 | machine independent code. md_estimate_size_before_relax returns | |
568 | the final size of the frag. md_convert_frag sets up the final form | |
569 | of the frag. tc_gen_reloc adjust the first reloc and adds a second | |
570 | one if needed. */ | |
571 | #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \ | |
572 | ((relax_substateT) \ | |
573 | (((old) << 23) \ | |
574 | | ((new) << 16) \ | |
575 | | (((reloc1) + 64) << 9) \ | |
576 | | (((reloc2) + 64) << 2) \ | |
577 | | ((reloc3) ? (1 << 1) : 0) \ | |
578 | | ((warn) ? 1 : 0))) | |
579 | #define RELAX_OLD(i) (((i) >> 23) & 0x7f) | |
580 | #define RELAX_NEW(i) (((i) >> 16) & 0x7f) | |
beae10d5 KH |
581 | #define RELAX_RELOC1(i) ((bfd_vma) (((i) >> 9) & 0x7f) - 64) |
582 | #define RELAX_RELOC2(i) ((bfd_vma) (((i) >> 2) & 0x7f) - 64) | |
252b5132 RH |
583 | #define RELAX_RELOC3(i) (((i) >> 1) & 1) |
584 | #define RELAX_WARN(i) ((i) & 1) | |
585 | ||
586 | /* For mips16 code, we use an entirely different form of relaxation. | |
587 | mips16 supports two versions of most instructions which take | |
588 | immediate values: a small one which takes some small value, and a | |
589 | larger one which takes a 16 bit value. Since branches also follow | |
590 | this pattern, relaxing these values is required. | |
591 | ||
592 | We can assemble both mips16 and normal MIPS code in a single | |
593 | object. Therefore, we need to support this type of relaxation at | |
594 | the same time that we support the relaxation described above. We | |
595 | use the high bit of the subtype field to distinguish these cases. | |
596 | ||
597 | The information we store for this type of relaxation is the | |
598 | argument code found in the opcode file for this relocation, whether | |
599 | the user explicitly requested a small or extended form, and whether | |
600 | the relocation is in a jump or jal delay slot. That tells us the | |
601 | size of the value, and how it should be stored. We also store | |
602 | whether the fragment is considered to be extended or not. We also | |
603 | store whether this is known to be a branch to a different section, | |
604 | whether we have tried to relax this frag yet, and whether we have | |
605 | ever extended a PC relative fragment because of a shift count. */ | |
606 | #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \ | |
607 | (0x80000000 \ | |
608 | | ((type) & 0xff) \ | |
609 | | ((small) ? 0x100 : 0) \ | |
610 | | ((ext) ? 0x200 : 0) \ | |
611 | | ((dslot) ? 0x400 : 0) \ | |
612 | | ((jal_dslot) ? 0x800 : 0)) | |
613 | #define RELAX_MIPS16_P(i) (((i) & 0x80000000) != 0) | |
614 | #define RELAX_MIPS16_TYPE(i) ((i) & 0xff) | |
615 | #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0) | |
616 | #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0) | |
617 | #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0) | |
618 | #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0) | |
619 | #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0) | |
620 | #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000) | |
621 | #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000) | |
622 | #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0) | |
623 | #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000) | |
624 | #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000) | |
625 | \f | |
626 | /* Prototypes for static functions. */ | |
627 | ||
628 | #ifdef __STDC__ | |
629 | #define internalError() \ | |
630 | as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__) | |
631 | #else | |
632 | #define internalError() as_fatal (_("MIPS internal Error")); | |
633 | #endif | |
634 | ||
635 | enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG }; | |
636 | ||
637 | static int insn_uses_reg PARAMS ((struct mips_cl_insn *ip, | |
638 | unsigned int reg, enum mips_regclass class)); | |
156c2f8b | 639 | static int reg_needs_delay PARAMS ((unsigned int)); |
252b5132 RH |
640 | static void mips16_mark_labels PARAMS ((void)); |
641 | static void append_insn PARAMS ((char *place, | |
642 | struct mips_cl_insn * ip, | |
643 | expressionS * p, | |
644 | bfd_reloc_code_real_type r, | |
645 | boolean)); | |
646 | static void mips_no_prev_insn PARAMS ((int)); | |
647 | static void mips_emit_delays PARAMS ((boolean)); | |
648 | #ifdef USE_STDARG | |
649 | static void macro_build PARAMS ((char *place, int *counter, expressionS * ep, | |
650 | const char *name, const char *fmt, | |
651 | ...)); | |
652 | #else | |
653 | static void macro_build (); | |
654 | #endif | |
655 | static void mips16_macro_build PARAMS ((char *, int *, expressionS *, | |
656 | const char *, const char *, | |
657 | va_list)); | |
658 | static void macro_build_lui PARAMS ((char *place, int *counter, | |
659 | expressionS * ep, int regnum)); | |
660 | static void set_at PARAMS ((int *counter, int reg, int unsignedp)); | |
661 | static void check_absolute_expr PARAMS ((struct mips_cl_insn * ip, | |
662 | expressionS *)); | |
663 | static void load_register PARAMS ((int *, int, expressionS *, int)); | |
664 | static void load_address PARAMS ((int *counter, int reg, expressionS *ep)); | |
665 | static void macro PARAMS ((struct mips_cl_insn * ip)); | |
666 | static void mips16_macro PARAMS ((struct mips_cl_insn * ip)); | |
667 | #ifdef LOSING_COMPILER | |
668 | static void macro2 PARAMS ((struct mips_cl_insn * ip)); | |
669 | #endif | |
670 | static void mips_ip PARAMS ((char *str, struct mips_cl_insn * ip)); | |
671 | static void mips16_ip PARAMS ((char *str, struct mips_cl_insn * ip)); | |
672 | static void mips16_immed PARAMS ((char *, unsigned int, int, offsetT, boolean, | |
673 | boolean, boolean, unsigned long *, | |
674 | boolean *, unsigned short *)); | |
675 | static int my_getSmallExpression PARAMS ((expressionS * ep, char *str)); | |
676 | static void my_getExpression PARAMS ((expressionS * ep, char *str)); | |
677 | static symbolS *get_symbol PARAMS ((void)); | |
678 | static void mips_align PARAMS ((int to, int fill, symbolS *label)); | |
679 | static void s_align PARAMS ((int)); | |
680 | static void s_change_sec PARAMS ((int)); | |
681 | static void s_cons PARAMS ((int)); | |
682 | static void s_float_cons PARAMS ((int)); | |
683 | static void s_mips_globl PARAMS ((int)); | |
684 | static void s_option PARAMS ((int)); | |
685 | static void s_mipsset PARAMS ((int)); | |
686 | static void s_abicalls PARAMS ((int)); | |
687 | static void s_cpload PARAMS ((int)); | |
688 | static void s_cprestore PARAMS ((int)); | |
689 | static void s_gpword PARAMS ((int)); | |
690 | static void s_cpadd PARAMS ((int)); | |
691 | static void s_insn PARAMS ((int)); | |
692 | static void md_obj_begin PARAMS ((void)); | |
693 | static void md_obj_end PARAMS ((void)); | |
694 | static long get_number PARAMS ((void)); | |
695 | static void s_mips_ent PARAMS ((int)); | |
696 | static void s_mips_end PARAMS ((int)); | |
697 | static void s_mips_frame PARAMS ((int)); | |
698 | static void s_mips_mask PARAMS ((int)); | |
699 | static void s_mips_stab PARAMS ((int)); | |
700 | static void s_mips_weakext PARAMS ((int)); | |
701 | static void s_file PARAMS ((int)); | |
702 | static int mips16_extended_frag PARAMS ((fragS *, asection *, long)); | |
e7af610e NC |
703 | static const char *mips_isa_to_str PARAMS ((int)); |
704 | static const char *mips_cpu_to_str PARAMS ((int)); | |
252b5132 | 705 | static int validate_mips_insn PARAMS ((const struct mips_opcode *)); |
e7af610e NC |
706 | |
707 | /* Table and functions used to map between CPU/ISA names, and | |
708 | ISA levels, and CPU numbers. */ | |
709 | ||
e972090a NC |
710 | struct mips_cpu_info |
711 | { | |
e7af610e NC |
712 | const char *name; /* CPU or ISA name. */ |
713 | int is_isa; /* Is this an ISA? (If 0, a CPU.) */ | |
714 | int isa; /* ISA level. */ | |
715 | int cpu; /* CPU number (default CPU if ISA). */ | |
716 | }; | |
717 | ||
718 | static const struct mips_cpu_info *mips_cpu_info_from_name PARAMS ((const char *)); | |
719 | static const struct mips_cpu_info *mips_cpu_info_from_isa PARAMS ((int)); | |
720 | static const struct mips_cpu_info *mips_cpu_info_from_cpu PARAMS ((int)); | |
252b5132 RH |
721 | \f |
722 | /* Pseudo-op table. | |
723 | ||
724 | The following pseudo-ops from the Kane and Heinrich MIPS book | |
725 | should be defined here, but are currently unsupported: .alias, | |
726 | .galive, .gjaldef, .gjrlive, .livereg, .noalias. | |
727 | ||
728 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
729 | specific to the type of debugging information being generated, and | |
730 | should be defined by the object format: .aent, .begin, .bend, | |
731 | .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp, | |
732 | .vreg. | |
733 | ||
734 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
735 | not MIPS CPU specific, but are also not specific to the object file | |
736 | format. This file is probably the best place to define them, but | |
737 | they are not currently supported: .asm0, .endr, .lab, .repeat, | |
738 | .struct. */ | |
739 | ||
e972090a NC |
740 | static const pseudo_typeS mips_pseudo_table[] = |
741 | { | |
beae10d5 | 742 | /* MIPS specific pseudo-ops. */ |
252b5132 RH |
743 | {"option", s_option, 0}, |
744 | {"set", s_mipsset, 0}, | |
745 | {"rdata", s_change_sec, 'r'}, | |
746 | {"sdata", s_change_sec, 's'}, | |
747 | {"livereg", s_ignore, 0}, | |
748 | {"abicalls", s_abicalls, 0}, | |
749 | {"cpload", s_cpload, 0}, | |
750 | {"cprestore", s_cprestore, 0}, | |
751 | {"gpword", s_gpword, 0}, | |
752 | {"cpadd", s_cpadd, 0}, | |
753 | {"insn", s_insn, 0}, | |
754 | ||
beae10d5 | 755 | /* Relatively generic pseudo-ops that happen to be used on MIPS |
252b5132 RH |
756 | chips. */ |
757 | {"asciiz", stringer, 1}, | |
758 | {"bss", s_change_sec, 'b'}, | |
759 | {"err", s_err, 0}, | |
760 | {"half", s_cons, 1}, | |
761 | {"dword", s_cons, 3}, | |
762 | {"weakext", s_mips_weakext, 0}, | |
763 | ||
beae10d5 | 764 | /* These pseudo-ops are defined in read.c, but must be overridden |
252b5132 RH |
765 | here for one reason or another. */ |
766 | {"align", s_align, 0}, | |
767 | {"byte", s_cons, 0}, | |
768 | {"data", s_change_sec, 'd'}, | |
769 | {"double", s_float_cons, 'd'}, | |
770 | {"float", s_float_cons, 'f'}, | |
771 | {"globl", s_mips_globl, 0}, | |
772 | {"global", s_mips_globl, 0}, | |
773 | {"hword", s_cons, 1}, | |
774 | {"int", s_cons, 2}, | |
775 | {"long", s_cons, 2}, | |
776 | {"octa", s_cons, 4}, | |
777 | {"quad", s_cons, 3}, | |
778 | {"short", s_cons, 1}, | |
779 | {"single", s_float_cons, 'f'}, | |
780 | {"stabn", s_mips_stab, 'n'}, | |
781 | {"text", s_change_sec, 't'}, | |
782 | {"word", s_cons, 2}, | |
add56521 L |
783 | |
784 | #ifdef MIPS_STABS_ELF | |
785 | { "extern", ecoff_directive_extern, 0}, | |
786 | #endif | |
787 | ||
43841e91 | 788 | { NULL, NULL, 0 }, |
252b5132 RH |
789 | }; |
790 | ||
e972090a NC |
791 | static const pseudo_typeS mips_nonecoff_pseudo_table[] = |
792 | { | |
beae10d5 KH |
793 | /* These pseudo-ops should be defined by the object file format. |
794 | However, a.out doesn't support them, so we have versions here. */ | |
252b5132 RH |
795 | {"aent", s_mips_ent, 1}, |
796 | {"bgnb", s_ignore, 0}, | |
797 | {"end", s_mips_end, 0}, | |
798 | {"endb", s_ignore, 0}, | |
799 | {"ent", s_mips_ent, 0}, | |
800 | {"file", s_file, 0}, | |
801 | {"fmask", s_mips_mask, 'F'}, | |
802 | {"frame", s_mips_frame, 0}, | |
803 | {"loc", s_ignore, 0}, | |
804 | {"mask", s_mips_mask, 'R'}, | |
805 | {"verstamp", s_ignore, 0}, | |
43841e91 | 806 | { NULL, NULL, 0 }, |
252b5132 RH |
807 | }; |
808 | ||
809 | extern void pop_insert PARAMS ((const pseudo_typeS *)); | |
810 | ||
811 | void | |
812 | mips_pop_insert () | |
813 | { | |
814 | pop_insert (mips_pseudo_table); | |
815 | if (! ECOFF_DEBUGGING) | |
816 | pop_insert (mips_nonecoff_pseudo_table); | |
817 | } | |
818 | \f | |
819 | /* Symbols labelling the current insn. */ | |
820 | ||
e972090a NC |
821 | struct insn_label_list |
822 | { | |
252b5132 RH |
823 | struct insn_label_list *next; |
824 | symbolS *label; | |
825 | }; | |
826 | ||
827 | static struct insn_label_list *insn_labels; | |
828 | static struct insn_label_list *free_insn_labels; | |
829 | ||
830 | static void mips_clear_insn_labels PARAMS ((void)); | |
831 | ||
832 | static inline void | |
833 | mips_clear_insn_labels () | |
834 | { | |
835 | register struct insn_label_list **pl; | |
836 | ||
837 | for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next) | |
838 | ; | |
839 | *pl = insn_labels; | |
840 | insn_labels = NULL; | |
841 | } | |
842 | \f | |
843 | static char *expr_end; | |
844 | ||
845 | /* Expressions which appear in instructions. These are set by | |
846 | mips_ip. */ | |
847 | ||
848 | static expressionS imm_expr; | |
849 | static expressionS offset_expr; | |
850 | ||
851 | /* Relocs associated with imm_expr and offset_expr. */ | |
852 | ||
853 | static bfd_reloc_code_real_type imm_reloc; | |
854 | static bfd_reloc_code_real_type offset_reloc; | |
855 | ||
856 | /* This is set by mips_ip if imm_reloc is an unmatched HI16_S reloc. */ | |
857 | ||
858 | static boolean imm_unmatched_hi; | |
859 | ||
860 | /* These are set by mips16_ip if an explicit extension is used. */ | |
861 | ||
862 | static boolean mips16_small, mips16_ext; | |
863 | ||
864 | #ifdef MIPS_STABS_ELF | |
865 | /* The pdr segment for per procedure frame/regmask info */ | |
866 | ||
867 | static segT pdr_seg; | |
868 | #endif | |
869 | ||
e7af610e NC |
870 | static const char * |
871 | mips_isa_to_str (isa) | |
872 | int isa; | |
873 | { | |
874 | const struct mips_cpu_info *ci; | |
875 | static char s[20]; | |
876 | ||
877 | ci = mips_cpu_info_from_isa (isa); | |
878 | if (ci != NULL) | |
879 | return (ci->name); | |
880 | ||
881 | sprintf (s, "ISA#%d", isa); | |
882 | return s; | |
883 | } | |
884 | ||
885 | static const char * | |
156c2f8b NC |
886 | mips_cpu_to_str (cpu) |
887 | int cpu; | |
888 | { | |
e7af610e | 889 | const struct mips_cpu_info *ci; |
156c2f8b | 890 | static char s[16]; |
e7af610e NC |
891 | |
892 | ci = mips_cpu_info_from_cpu (cpu); | |
893 | if (ci != NULL) | |
894 | return (ci->name); | |
895 | ||
896 | sprintf (s, "CPU#%d", cpu); | |
897 | return s; | |
156c2f8b NC |
898 | } |
899 | ||
900 | /* This function is called once, at assembler startup time. It should | |
901 | set up all the tables, etc. that the MD part of the assembler will need. */ | |
902 | ||
252b5132 RH |
903 | void |
904 | md_begin () | |
905 | { | |
252b5132 | 906 | register const char *retval = NULL; |
156c2f8b | 907 | int i = 0; |
252b5132 RH |
908 | const char *cpu; |
909 | char *a = NULL; | |
910 | int broken = 0; | |
911 | int mips_isa_from_cpu; | |
e7af610e NC |
912 | int target_cpu_had_mips16 = 0; |
913 | const struct mips_cpu_info *ci; | |
252b5132 | 914 | |
056350c6 NC |
915 | /* GP relative stuff not working for PE */ |
916 | if (strncmp (TARGET_OS, "pe", 2) == 0 | |
917 | && g_switch_value != 0) | |
918 | { | |
919 | if (g_switch_seen) | |
920 | as_bad (_("-G not supported in this configuration.")); | |
921 | g_switch_value = 0; | |
922 | } | |
923 | ||
252b5132 RH |
924 | cpu = TARGET_CPU; |
925 | if (strcmp (cpu + (sizeof TARGET_CPU) - 3, "el") == 0) | |
926 | { | |
927 | a = xmalloc (sizeof TARGET_CPU); | |
928 | strcpy (a, TARGET_CPU); | |
929 | a[(sizeof TARGET_CPU) - 3] = '\0'; | |
930 | cpu = a; | |
931 | } | |
932 | ||
e7af610e | 933 | if (strncmp (cpu, "mips16", sizeof "mips16" - 1) == 0) |
252b5132 | 934 | { |
e7af610e NC |
935 | target_cpu_had_mips16 = 1; |
936 | cpu += sizeof "mips16" - 1; | |
252b5132 RH |
937 | } |
938 | ||
e7af610e NC |
939 | if (mips_opts.mips16 < 0) |
940 | mips_opts.mips16 = target_cpu_had_mips16; | |
252b5132 | 941 | |
ec68c924 | 942 | /* At this point, mips_arch will either be CPU_UNKNOWN if no ARCH was |
e7af610e NC |
943 | specified on the command line, or some other value if one was. |
944 | Similarly, mips_opts.isa will be ISA_UNKNOWN if not specified on | |
945 | the command line, or will be set otherwise if one was. */ | |
ec68c924 | 946 | if (mips_arch != CPU_UNKNOWN && mips_opts.isa != ISA_UNKNOWN) |
252b5132 | 947 | { |
e7af610e | 948 | /* We have it all. There's nothing to do. */ |
252b5132 | 949 | } |
ec68c924 | 950 | else if (mips_arch != CPU_UNKNOWN && mips_opts.isa == ISA_UNKNOWN) |
252b5132 | 951 | { |
ec68c924 EC |
952 | /* We have ARCH, we need ISA. */ |
953 | ci = mips_cpu_info_from_cpu (mips_arch); | |
e7af610e NC |
954 | assert (ci != NULL); |
955 | mips_opts.isa = ci->isa; | |
956 | } | |
ec68c924 | 957 | else if (mips_arch == CPU_UNKNOWN && mips_opts.isa != ISA_UNKNOWN) |
e7af610e | 958 | { |
ec68c924 | 959 | /* We have ISA, we need default ARCH. */ |
e7af610e NC |
960 | ci = mips_cpu_info_from_isa (mips_opts.isa); |
961 | assert (ci != NULL); | |
ec68c924 EC |
962 | mips_arch = ci->cpu; |
963 | } | |
964 | else if (mips_arch == CPU_UNKNOWN | |
965 | && mips_opts.isa == ISA_UNKNOWN | |
966 | && mips_cpu != CPU_UNKNOWN) | |
967 | { | |
968 | /* Historic -mcpu= option. Warn. */ | |
969 | ci = mips_cpu_info_from_cpu (mips_cpu); | |
970 | assert (ci != NULL); | |
971 | mips_arch = ci->cpu; | |
972 | mips_tune = ci->cpu; | |
973 | mips_opts.isa = ci->isa; | |
974 | as_warn (_("The -mcpu option is deprecated. Please use -march and -mtune instead.")); | |
975 | ||
e7af610e NC |
976 | } |
977 | else | |
978 | { | |
ec68c924 | 979 | /* We need to set both ISA and ARCH from target cpu. */ |
e7af610e NC |
980 | ci = mips_cpu_info_from_name (cpu); |
981 | if (ci == NULL) | |
beae10d5 | 982 | ci = mips_cpu_info_from_cpu (CPU_R3000); |
e7af610e NC |
983 | assert (ci != NULL); |
984 | mips_opts.isa = ci->isa; | |
ec68c924 | 985 | mips_arch = ci->cpu; |
252b5132 RH |
986 | } |
987 | ||
ec68c924 EC |
988 | if (mips_tune == CPU_UNKNOWN) |
989 | mips_tune = mips_arch; | |
990 | ||
991 | ci = mips_cpu_info_from_cpu (mips_arch); | |
e7af610e NC |
992 | assert (ci != NULL); |
993 | mips_isa_from_cpu = ci->isa; | |
994 | ||
252b5132 | 995 | /* End of TARGET_CPU processing, get rid of malloced memory |
bdaaa2e1 | 996 | if necessary. */ |
252b5132 RH |
997 | cpu = NULL; |
998 | if (a != NULL) | |
999 | { | |
156c2f8b NC |
1000 | free (a); |
1001 | a = NULL; | |
252b5132 RH |
1002 | } |
1003 | ||
e7af610e | 1004 | if (mips_opts.isa == ISA_MIPS1 && mips_trap) |
252b5132 RH |
1005 | as_bad (_("trap exception not supported at ISA 1")); |
1006 | ||
1007 | /* Set the EABI kind based on the ISA before the user gets | |
1008 | to change the ISA with directives. This isn't really | |
bdaaa2e1 | 1009 | the best, but then neither is basing the abi on the isa. */ |
9ce8a5dd | 1010 | if (ISA_HAS_64BIT_REGS (mips_opts.isa) |
252b5132 | 1011 | && mips_abi_string |
beae10d5 | 1012 | && 0 == strcmp (mips_abi_string, "eabi")) |
252b5132 RH |
1013 | mips_eabi64 = 1; |
1014 | ||
e7af610e NC |
1015 | /* If they asked for mips1 or mips2 and a cpu that is |
1016 | mips3 or greater, then mark the object file 32BITMODE. */ | |
1017 | if (mips_isa_from_cpu != ISA_UNKNOWN | |
1018 | && ! ISA_HAS_64BIT_REGS (mips_opts.isa) | |
1019 | && ISA_HAS_64BIT_REGS (mips_isa_from_cpu)) | |
1020 | mips_32bitmode = 1; | |
252b5132 | 1021 | |
ec68c924 | 1022 | if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, mips_arch)) |
252b5132 RH |
1023 | as_warn (_("Could not set architecture and machine")); |
1024 | ||
1025 | file_mips_isa = mips_opts.isa; | |
1026 | ||
1027 | op_hash = hash_new (); | |
1028 | ||
1029 | for (i = 0; i < NUMOPCODES;) | |
1030 | { | |
1031 | const char *name = mips_opcodes[i].name; | |
1032 | ||
1033 | retval = hash_insert (op_hash, name, (PTR) &mips_opcodes[i]); | |
1034 | if (retval != NULL) | |
1035 | { | |
1036 | fprintf (stderr, _("internal error: can't hash `%s': %s\n"), | |
1037 | mips_opcodes[i].name, retval); | |
1038 | /* Probably a memory allocation problem? Give up now. */ | |
1039 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
1040 | } | |
1041 | do | |
1042 | { | |
1043 | if (mips_opcodes[i].pinfo != INSN_MACRO) | |
1044 | { | |
1045 | if (!validate_mips_insn (&mips_opcodes[i])) | |
1046 | broken = 1; | |
1047 | } | |
1048 | ++i; | |
1049 | } | |
1050 | while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name)); | |
1051 | } | |
1052 | ||
1053 | mips16_op_hash = hash_new (); | |
1054 | ||
1055 | i = 0; | |
1056 | while (i < bfd_mips16_num_opcodes) | |
1057 | { | |
1058 | const char *name = mips16_opcodes[i].name; | |
1059 | ||
1060 | retval = hash_insert (mips16_op_hash, name, (PTR) &mips16_opcodes[i]); | |
1061 | if (retval != NULL) | |
1062 | as_fatal (_("internal: can't hash `%s': %s"), | |
1063 | mips16_opcodes[i].name, retval); | |
1064 | do | |
1065 | { | |
1066 | if (mips16_opcodes[i].pinfo != INSN_MACRO | |
1067 | && ((mips16_opcodes[i].match & mips16_opcodes[i].mask) | |
1068 | != mips16_opcodes[i].match)) | |
1069 | { | |
1070 | fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"), | |
1071 | mips16_opcodes[i].name, mips16_opcodes[i].args); | |
1072 | broken = 1; | |
1073 | } | |
1074 | ++i; | |
1075 | } | |
1076 | while (i < bfd_mips16_num_opcodes | |
1077 | && strcmp (mips16_opcodes[i].name, name) == 0); | |
1078 | } | |
1079 | ||
1080 | if (broken) | |
1081 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
1082 | ||
1083 | /* We add all the general register names to the symbol table. This | |
1084 | helps us detect invalid uses of them. */ | |
1085 | for (i = 0; i < 32; i++) | |
1086 | { | |
1087 | char buf[5]; | |
1088 | ||
1089 | sprintf (buf, "$%d", i); | |
1090 | symbol_table_insert (symbol_new (buf, reg_section, i, | |
1091 | &zero_address_frag)); | |
1092 | } | |
1093 | symbol_table_insert (symbol_new ("$fp", reg_section, FP, | |
1094 | &zero_address_frag)); | |
1095 | symbol_table_insert (symbol_new ("$sp", reg_section, SP, | |
1096 | &zero_address_frag)); | |
1097 | symbol_table_insert (symbol_new ("$gp", reg_section, GP, | |
1098 | &zero_address_frag)); | |
1099 | symbol_table_insert (symbol_new ("$at", reg_section, AT, | |
1100 | &zero_address_frag)); | |
1101 | symbol_table_insert (symbol_new ("$kt0", reg_section, KT0, | |
1102 | &zero_address_frag)); | |
1103 | symbol_table_insert (symbol_new ("$kt1", reg_section, KT1, | |
1104 | &zero_address_frag)); | |
1105 | symbol_table_insert (symbol_new ("$pc", reg_section, -1, | |
1106 | &zero_address_frag)); | |
1107 | ||
1108 | mips_no_prev_insn (false); | |
1109 | ||
1110 | mips_gprmask = 0; | |
1111 | mips_cprmask[0] = 0; | |
1112 | mips_cprmask[1] = 0; | |
1113 | mips_cprmask[2] = 0; | |
1114 | mips_cprmask[3] = 0; | |
1115 | ||
1116 | /* set the default alignment for the text section (2**2) */ | |
1117 | record_alignment (text_section, 2); | |
1118 | ||
1119 | if (USE_GLOBAL_POINTER_OPT) | |
1120 | bfd_set_gp_size (stdoutput, g_switch_value); | |
1121 | ||
1122 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
1123 | { | |
1124 | /* On a native system, sections must be aligned to 16 byte | |
1125 | boundaries. When configured for an embedded ELF target, we | |
1126 | don't bother. */ | |
1127 | if (strcmp (TARGET_OS, "elf") != 0) | |
1128 | { | |
1129 | (void) bfd_set_section_alignment (stdoutput, text_section, 4); | |
1130 | (void) bfd_set_section_alignment (stdoutput, data_section, 4); | |
1131 | (void) bfd_set_section_alignment (stdoutput, bss_section, 4); | |
1132 | } | |
1133 | ||
1134 | /* Create a .reginfo section for register masks and a .mdebug | |
1135 | section for debugging information. */ | |
1136 | { | |
1137 | segT seg; | |
1138 | subsegT subseg; | |
1139 | flagword flags; | |
1140 | segT sec; | |
1141 | ||
1142 | seg = now_seg; | |
1143 | subseg = now_subseg; | |
1144 | ||
1145 | /* The ABI says this section should be loaded so that the | |
1146 | running program can access it. However, we don't load it | |
1147 | if we are configured for an embedded target */ | |
1148 | flags = SEC_READONLY | SEC_DATA; | |
1149 | if (strcmp (TARGET_OS, "elf") != 0) | |
1150 | flags |= SEC_ALLOC | SEC_LOAD; | |
1151 | ||
1152 | if (! mips_64) | |
1153 | { | |
1154 | sec = subseg_new (".reginfo", (subsegT) 0); | |
1155 | ||
252b5132 RH |
1156 | (void) bfd_set_section_flags (stdoutput, sec, flags); |
1157 | (void) bfd_set_section_alignment (stdoutput, sec, 2); | |
bdaaa2e1 | 1158 | |
252b5132 RH |
1159 | #ifdef OBJ_ELF |
1160 | mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo)); | |
1161 | #endif | |
1162 | } | |
1163 | else | |
1164 | { | |
1165 | /* The 64-bit ABI uses a .MIPS.options section rather than | |
1166 | .reginfo section. */ | |
1167 | sec = subseg_new (".MIPS.options", (subsegT) 0); | |
1168 | (void) bfd_set_section_flags (stdoutput, sec, flags); | |
1169 | (void) bfd_set_section_alignment (stdoutput, sec, 3); | |
1170 | ||
1171 | #ifdef OBJ_ELF | |
1172 | /* Set up the option header. */ | |
1173 | { | |
1174 | Elf_Internal_Options opthdr; | |
1175 | char *f; | |
1176 | ||
1177 | opthdr.kind = ODK_REGINFO; | |
1178 | opthdr.size = (sizeof (Elf_External_Options) | |
1179 | + sizeof (Elf64_External_RegInfo)); | |
1180 | opthdr.section = 0; | |
1181 | opthdr.info = 0; | |
1182 | f = frag_more (sizeof (Elf_External_Options)); | |
1183 | bfd_mips_elf_swap_options_out (stdoutput, &opthdr, | |
1184 | (Elf_External_Options *) f); | |
1185 | ||
1186 | mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo)); | |
1187 | } | |
1188 | #endif | |
1189 | } | |
1190 | ||
1191 | if (ECOFF_DEBUGGING) | |
1192 | { | |
1193 | sec = subseg_new (".mdebug", (subsegT) 0); | |
1194 | (void) bfd_set_section_flags (stdoutput, sec, | |
1195 | SEC_HAS_CONTENTS | SEC_READONLY); | |
1196 | (void) bfd_set_section_alignment (stdoutput, sec, 2); | |
1197 | } | |
1198 | ||
1199 | #ifdef MIPS_STABS_ELF | |
1200 | pdr_seg = subseg_new (".pdr", (subsegT) 0); | |
1201 | (void) bfd_set_section_flags (stdoutput, pdr_seg, | |
1202 | SEC_READONLY | SEC_RELOC | SEC_DEBUGGING); | |
1203 | (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2); | |
1204 | #endif | |
1205 | ||
1206 | subseg_set (seg, subseg); | |
1207 | } | |
1208 | } | |
1209 | ||
1210 | if (! ECOFF_DEBUGGING) | |
1211 | md_obj_begin (); | |
1212 | } | |
1213 | ||
1214 | void | |
1215 | md_mips_end () | |
1216 | { | |
1217 | if (! ECOFF_DEBUGGING) | |
1218 | md_obj_end (); | |
1219 | } | |
1220 | ||
1221 | void | |
1222 | md_assemble (str) | |
1223 | char *str; | |
1224 | { | |
1225 | struct mips_cl_insn insn; | |
1226 | ||
1227 | imm_expr.X_op = O_absent; | |
1228 | imm_reloc = BFD_RELOC_UNUSED; | |
1229 | imm_unmatched_hi = false; | |
1230 | offset_expr.X_op = O_absent; | |
1231 | offset_reloc = BFD_RELOC_UNUSED; | |
1232 | ||
1233 | if (mips_opts.mips16) | |
1234 | mips16_ip (str, &insn); | |
1235 | else | |
1236 | { | |
1237 | mips_ip (str, &insn); | |
beae10d5 KH |
1238 | DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"), |
1239 | str, insn.insn_opcode)); | |
252b5132 RH |
1240 | } |
1241 | ||
1242 | if (insn_error) | |
1243 | { | |
1244 | as_bad ("%s `%s'", insn_error, str); | |
1245 | return; | |
1246 | } | |
1247 | ||
1248 | if (insn.insn_mo->pinfo == INSN_MACRO) | |
1249 | { | |
1250 | if (mips_opts.mips16) | |
1251 | mips16_macro (&insn); | |
1252 | else | |
1253 | macro (&insn); | |
1254 | } | |
1255 | else | |
1256 | { | |
1257 | if (imm_expr.X_op != O_absent) | |
1258 | append_insn ((char *) NULL, &insn, &imm_expr, imm_reloc, | |
1259 | imm_unmatched_hi); | |
1260 | else if (offset_expr.X_op != O_absent) | |
1261 | append_insn ((char *) NULL, &insn, &offset_expr, offset_reloc, false); | |
1262 | else | |
1263 | append_insn ((char *) NULL, &insn, NULL, BFD_RELOC_UNUSED, false); | |
1264 | } | |
1265 | } | |
1266 | ||
1267 | /* See whether instruction IP reads register REG. CLASS is the type | |
1268 | of register. */ | |
1269 | ||
1270 | static int | |
1271 | insn_uses_reg (ip, reg, class) | |
1272 | struct mips_cl_insn *ip; | |
1273 | unsigned int reg; | |
1274 | enum mips_regclass class; | |
1275 | { | |
1276 | if (class == MIPS16_REG) | |
1277 | { | |
1278 | assert (mips_opts.mips16); | |
1279 | reg = mips16_to_32_reg_map[reg]; | |
1280 | class = MIPS_GR_REG; | |
1281 | } | |
1282 | ||
1283 | /* Don't report on general register 0, since it never changes. */ | |
1284 | if (class == MIPS_GR_REG && reg == 0) | |
1285 | return 0; | |
1286 | ||
1287 | if (class == MIPS_FP_REG) | |
1288 | { | |
1289 | assert (! mips_opts.mips16); | |
1290 | /* If we are called with either $f0 or $f1, we must check $f0. | |
1291 | This is not optimal, because it will introduce an unnecessary | |
1292 | NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would | |
1293 | need to distinguish reading both $f0 and $f1 or just one of | |
1294 | them. Note that we don't have to check the other way, | |
1295 | because there is no instruction that sets both $f0 and $f1 | |
1296 | and requires a delay. */ | |
1297 | if ((ip->insn_mo->pinfo & INSN_READ_FPR_S) | |
1298 | && ((((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS) &~(unsigned)1) | |
1299 | == (reg &~ (unsigned) 1))) | |
1300 | return 1; | |
1301 | if ((ip->insn_mo->pinfo & INSN_READ_FPR_T) | |
1302 | && ((((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT) &~(unsigned)1) | |
1303 | == (reg &~ (unsigned) 1))) | |
1304 | return 1; | |
1305 | } | |
1306 | else if (! mips_opts.mips16) | |
1307 | { | |
1308 | if ((ip->insn_mo->pinfo & INSN_READ_GPR_S) | |
1309 | && ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == reg) | |
1310 | return 1; | |
1311 | if ((ip->insn_mo->pinfo & INSN_READ_GPR_T) | |
1312 | && ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT) == reg) | |
1313 | return 1; | |
1314 | } | |
1315 | else | |
1316 | { | |
1317 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_X) | |
1318 | && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_RX) | |
1319 | & MIPS16OP_MASK_RX)] | |
1320 | == reg)) | |
1321 | return 1; | |
1322 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Y) | |
1323 | && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_RY) | |
1324 | & MIPS16OP_MASK_RY)] | |
1325 | == reg)) | |
1326 | return 1; | |
1327 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Z) | |
1328 | && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z) | |
1329 | & MIPS16OP_MASK_MOVE32Z)] | |
1330 | == reg)) | |
1331 | return 1; | |
1332 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_T) && reg == TREG) | |
1333 | return 1; | |
1334 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_SP) && reg == SP) | |
1335 | return 1; | |
1336 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_31) && reg == RA) | |
1337 | return 1; | |
1338 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_GPR_X) | |
1339 | && ((ip->insn_opcode >> MIPS16OP_SH_REGR32) | |
1340 | & MIPS16OP_MASK_REGR32) == reg) | |
1341 | return 1; | |
1342 | } | |
1343 | ||
1344 | return 0; | |
1345 | } | |
1346 | ||
1347 | /* This function returns true if modifying a register requires a | |
1348 | delay. */ | |
1349 | ||
1350 | static int | |
1351 | reg_needs_delay (reg) | |
156c2f8b | 1352 | unsigned int reg; |
252b5132 RH |
1353 | { |
1354 | unsigned long prev_pinfo; | |
1355 | ||
1356 | prev_pinfo = prev_insn.insn_mo->pinfo; | |
1357 | if (! mips_opts.noreorder | |
9ce8a5dd | 1358 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 RH |
1359 | && ((prev_pinfo & INSN_LOAD_COPROC_DELAY) |
1360 | || (! gpr_interlocks | |
1361 | && (prev_pinfo & INSN_LOAD_MEMORY_DELAY)))) | |
1362 | { | |
1363 | /* A load from a coprocessor or from memory. All load | |
1364 | delays delay the use of general register rt for one | |
1365 | instruction on the r3000. The r6000 and r4000 use | |
1366 | interlocks. */ | |
bdaaa2e1 | 1367 | /* Itbl support may require additional care here. */ |
252b5132 RH |
1368 | know (prev_pinfo & INSN_WRITE_GPR_T); |
1369 | if (reg == ((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT)) | |
1370 | return 1; | |
1371 | } | |
1372 | ||
1373 | return 0; | |
1374 | } | |
1375 | ||
1376 | /* Mark instruction labels in mips16 mode. This permits the linker to | |
1377 | handle them specially, such as generating jalx instructions when | |
1378 | needed. We also make them odd for the duration of the assembly, in | |
1379 | order to generate the right sort of code. We will make them even | |
1380 | in the adjust_symtab routine, while leaving them marked. This is | |
1381 | convenient for the debugger and the disassembler. The linker knows | |
1382 | to make them odd again. */ | |
1383 | ||
1384 | static void | |
1385 | mips16_mark_labels () | |
1386 | { | |
1387 | if (mips_opts.mips16) | |
1388 | { | |
1389 | struct insn_label_list *l; | |
98aa84af | 1390 | valueT val; |
252b5132 RH |
1391 | |
1392 | for (l = insn_labels; l != NULL; l = l->next) | |
1393 | { | |
1394 | #ifdef OBJ_ELF | |
1395 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
1396 | S_SET_OTHER (l->label, STO_MIPS16); | |
1397 | #endif | |
98aa84af AM |
1398 | val = S_GET_VALUE (l->label); |
1399 | if ((val & 1) == 0) | |
1400 | S_SET_VALUE (l->label, val + 1); | |
252b5132 RH |
1401 | } |
1402 | } | |
1403 | } | |
1404 | ||
1405 | /* Output an instruction. PLACE is where to put the instruction; if | |
1406 | it is NULL, this uses frag_more to get room. IP is the instruction | |
1407 | information. ADDRESS_EXPR is an operand of the instruction to be | |
1408 | used with RELOC_TYPE. */ | |
1409 | ||
1410 | static void | |
1411 | append_insn (place, ip, address_expr, reloc_type, unmatched_hi) | |
1412 | char *place; | |
1413 | struct mips_cl_insn *ip; | |
1414 | expressionS *address_expr; | |
1415 | bfd_reloc_code_real_type reloc_type; | |
1416 | boolean unmatched_hi; | |
1417 | { | |
1418 | register unsigned long prev_pinfo, pinfo; | |
1419 | char *f; | |
1420 | fixS *fixp; | |
1421 | int nops = 0; | |
1422 | ||
1423 | /* Mark instruction labels in mips16 mode. */ | |
1424 | if (mips_opts.mips16) | |
1425 | mips16_mark_labels (); | |
1426 | ||
1427 | prev_pinfo = prev_insn.insn_mo->pinfo; | |
1428 | pinfo = ip->insn_mo->pinfo; | |
1429 | ||
1430 | if (place == NULL && (! mips_opts.noreorder || prev_nop_frag != NULL)) | |
1431 | { | |
1432 | int prev_prev_nop; | |
1433 | ||
1434 | /* If the previous insn required any delay slots, see if we need | |
1435 | to insert a NOP or two. There are eight kinds of possible | |
1436 | hazards, of which an instruction can have at most one type. | |
1437 | (1) a load from memory delay | |
1438 | (2) a load from a coprocessor delay | |
1439 | (3) an unconditional branch delay | |
1440 | (4) a conditional branch delay | |
1441 | (5) a move to coprocessor register delay | |
1442 | (6) a load coprocessor register from memory delay | |
1443 | (7) a coprocessor condition code delay | |
1444 | (8) a HI/LO special register delay | |
1445 | ||
1446 | There are a lot of optimizations we could do that we don't. | |
1447 | In particular, we do not, in general, reorder instructions. | |
1448 | If you use gcc with optimization, it will reorder | |
1449 | instructions and generally do much more optimization then we | |
1450 | do here; repeating all that work in the assembler would only | |
1451 | benefit hand written assembly code, and does not seem worth | |
1452 | it. */ | |
1453 | ||
1454 | /* This is how a NOP is emitted. */ | |
1455 | #define emit_nop() \ | |
1456 | (mips_opts.mips16 \ | |
1457 | ? md_number_to_chars (frag_more (2), 0x6500, 2) \ | |
1458 | : md_number_to_chars (frag_more (4), 0, 4)) | |
1459 | ||
1460 | /* The previous insn might require a delay slot, depending upon | |
1461 | the contents of the current insn. */ | |
1462 | if (! mips_opts.mips16 | |
9ce8a5dd | 1463 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 RH |
1464 | && (((prev_pinfo & INSN_LOAD_COPROC_DELAY) |
1465 | && ! cop_interlocks) | |
1466 | || (! gpr_interlocks | |
1467 | && (prev_pinfo & INSN_LOAD_MEMORY_DELAY)))) | |
1468 | { | |
1469 | /* A load from a coprocessor or from memory. All load | |
1470 | delays delay the use of general register rt for one | |
1471 | instruction on the r3000. The r6000 and r4000 use | |
1472 | interlocks. */ | |
beae10d5 | 1473 | /* Itbl support may require additional care here. */ |
252b5132 RH |
1474 | know (prev_pinfo & INSN_WRITE_GPR_T); |
1475 | if (mips_optimize == 0 | |
1476 | || insn_uses_reg (ip, | |
1477 | ((prev_insn.insn_opcode >> OP_SH_RT) | |
1478 | & OP_MASK_RT), | |
1479 | MIPS_GR_REG)) | |
1480 | ++nops; | |
1481 | } | |
1482 | else if (! mips_opts.mips16 | |
9ce8a5dd | 1483 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 | 1484 | && (((prev_pinfo & INSN_COPROC_MOVE_DELAY) |
beae10d5 | 1485 | && ! cop_interlocks) |
e7af610e | 1486 | || (mips_opts.isa == ISA_MIPS1 |
252b5132 RH |
1487 | && (prev_pinfo & INSN_COPROC_MEMORY_DELAY)))) |
1488 | { | |
1489 | /* A generic coprocessor delay. The previous instruction | |
1490 | modified a coprocessor general or control register. If | |
1491 | it modified a control register, we need to avoid any | |
1492 | coprocessor instruction (this is probably not always | |
1493 | required, but it sometimes is). If it modified a general | |
1494 | register, we avoid using that register. | |
1495 | ||
1496 | On the r6000 and r4000 loading a coprocessor register | |
1497 | from memory is interlocked, and does not require a delay. | |
1498 | ||
1499 | This case is not handled very well. There is no special | |
1500 | knowledge of CP0 handling, and the coprocessors other | |
1501 | than the floating point unit are not distinguished at | |
1502 | all. */ | |
1503 | /* Itbl support may require additional care here. FIXME! | |
bdaaa2e1 | 1504 | Need to modify this to include knowledge about |
252b5132 RH |
1505 | user specified delays! */ |
1506 | if (prev_pinfo & INSN_WRITE_FPR_T) | |
1507 | { | |
1508 | if (mips_optimize == 0 | |
1509 | || insn_uses_reg (ip, | |
1510 | ((prev_insn.insn_opcode >> OP_SH_FT) | |
1511 | & OP_MASK_FT), | |
1512 | MIPS_FP_REG)) | |
1513 | ++nops; | |
1514 | } | |
1515 | else if (prev_pinfo & INSN_WRITE_FPR_S) | |
1516 | { | |
1517 | if (mips_optimize == 0 | |
1518 | || insn_uses_reg (ip, | |
1519 | ((prev_insn.insn_opcode >> OP_SH_FS) | |
1520 | & OP_MASK_FS), | |
1521 | MIPS_FP_REG)) | |
1522 | ++nops; | |
1523 | } | |
1524 | else | |
1525 | { | |
1526 | /* We don't know exactly what the previous instruction | |
1527 | does. If the current instruction uses a coprocessor | |
1528 | register, we must insert a NOP. If previous | |
1529 | instruction may set the condition codes, and the | |
1530 | current instruction uses them, we must insert two | |
1531 | NOPS. */ | |
bdaaa2e1 | 1532 | /* Itbl support may require additional care here. */ |
252b5132 RH |
1533 | if (mips_optimize == 0 |
1534 | || ((prev_pinfo & INSN_WRITE_COND_CODE) | |
1535 | && (pinfo & INSN_READ_COND_CODE))) | |
1536 | nops += 2; | |
1537 | else if (pinfo & INSN_COP) | |
1538 | ++nops; | |
1539 | } | |
1540 | } | |
1541 | else if (! mips_opts.mips16 | |
9ce8a5dd | 1542 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 RH |
1543 | && (prev_pinfo & INSN_WRITE_COND_CODE) |
1544 | && ! cop_interlocks) | |
1545 | { | |
1546 | /* The previous instruction sets the coprocessor condition | |
1547 | codes, but does not require a general coprocessor delay | |
1548 | (this means it is a floating point comparison | |
1549 | instruction). If this instruction uses the condition | |
1550 | codes, we need to insert a single NOP. */ | |
beae10d5 | 1551 | /* Itbl support may require additional care here. */ |
252b5132 RH |
1552 | if (mips_optimize == 0 |
1553 | || (pinfo & INSN_READ_COND_CODE)) | |
1554 | ++nops; | |
1555 | } | |
6b76fefe CM |
1556 | |
1557 | /* If we're fixing up mfhi/mflo for the r7000 and the | |
1558 | previous insn was an mfhi/mflo and the current insn | |
1559 | reads the register that the mfhi/mflo wrote to, then | |
1560 | insert two nops. */ | |
1561 | ||
1562 | else if (mips_7000_hilo_fix | |
1563 | && MF_HILO_INSN (prev_pinfo) | |
1564 | && insn_uses_reg (ip, ((prev_insn.insn_opcode >> OP_SH_RD) | |
beae10d5 KH |
1565 | & OP_MASK_RD), |
1566 | MIPS_GR_REG)) | |
6b76fefe CM |
1567 | { |
1568 | nops += 2; | |
1569 | } | |
1570 | ||
1571 | /* If we're fixing up mfhi/mflo for the r7000 and the | |
1572 | 2nd previous insn was an mfhi/mflo and the current insn | |
1573 | reads the register that the mfhi/mflo wrote to, then | |
1574 | insert one nop. */ | |
1575 | ||
1576 | else if (mips_7000_hilo_fix | |
1577 | && MF_HILO_INSN (prev_prev_insn.insn_opcode) | |
1578 | && insn_uses_reg (ip, ((prev_prev_insn.insn_opcode >> OP_SH_RD) | |
1579 | & OP_MASK_RD), | |
1580 | MIPS_GR_REG)) | |
bdaaa2e1 | 1581 | |
6b76fefe CM |
1582 | { |
1583 | nops += 1; | |
1584 | } | |
bdaaa2e1 | 1585 | |
252b5132 RH |
1586 | else if (prev_pinfo & INSN_READ_LO) |
1587 | { | |
1588 | /* The previous instruction reads the LO register; if the | |
1589 | current instruction writes to the LO register, we must | |
bdaaa2e1 KH |
1590 | insert two NOPS. Some newer processors have interlocks. |
1591 | Also the tx39's multiply instructions can be exectuted | |
252b5132 | 1592 | immediatly after a read from HI/LO (without the delay), |
bdaaa2e1 KH |
1593 | though the tx39's divide insns still do require the |
1594 | delay. */ | |
252b5132 | 1595 | if (! (hilo_interlocks |
ec68c924 | 1596 | || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT))) |
252b5132 RH |
1597 | && (mips_optimize == 0 |
1598 | || (pinfo & INSN_WRITE_LO))) | |
1599 | nops += 2; | |
1600 | /* Most mips16 branch insns don't have a delay slot. | |
1601 | If a read from LO is immediately followed by a branch | |
1602 | to a write to LO we have a read followed by a write | |
1603 | less than 2 insns away. We assume the target of | |
1604 | a branch might be a write to LO, and insert a nop | |
bdaaa2e1 | 1605 | between a read and an immediately following branch. */ |
252b5132 RH |
1606 | else if (mips_opts.mips16 |
1607 | && (mips_optimize == 0 | |
1608 | || (pinfo & MIPS16_INSN_BRANCH))) | |
1609 | nops += 1; | |
1610 | } | |
1611 | else if (prev_insn.insn_mo->pinfo & INSN_READ_HI) | |
1612 | { | |
1613 | /* The previous instruction reads the HI register; if the | |
1614 | current instruction writes to the HI register, we must | |
1615 | insert a NOP. Some newer processors have interlocks. | |
bdaaa2e1 | 1616 | Also the note tx39's multiply above. */ |
252b5132 | 1617 | if (! (hilo_interlocks |
ec68c924 | 1618 | || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT))) |
252b5132 RH |
1619 | && (mips_optimize == 0 |
1620 | || (pinfo & INSN_WRITE_HI))) | |
1621 | nops += 2; | |
1622 | /* Most mips16 branch insns don't have a delay slot. | |
1623 | If a read from HI is immediately followed by a branch | |
1624 | to a write to HI we have a read followed by a write | |
1625 | less than 2 insns away. We assume the target of | |
1626 | a branch might be a write to HI, and insert a nop | |
bdaaa2e1 | 1627 | between a read and an immediately following branch. */ |
252b5132 RH |
1628 | else if (mips_opts.mips16 |
1629 | && (mips_optimize == 0 | |
1630 | || (pinfo & MIPS16_INSN_BRANCH))) | |
1631 | nops += 1; | |
1632 | } | |
1633 | ||
1634 | /* If the previous instruction was in a noreorder section, then | |
1635 | we don't want to insert the nop after all. */ | |
bdaaa2e1 | 1636 | /* Itbl support may require additional care here. */ |
252b5132 RH |
1637 | if (prev_insn_unreordered) |
1638 | nops = 0; | |
1639 | ||
1640 | /* There are two cases which require two intervening | |
1641 | instructions: 1) setting the condition codes using a move to | |
1642 | coprocessor instruction which requires a general coprocessor | |
1643 | delay and then reading the condition codes 2) reading the HI | |
1644 | or LO register and then writing to it (except on processors | |
1645 | which have interlocks). If we are not already emitting a NOP | |
1646 | instruction, we must check for these cases compared to the | |
1647 | instruction previous to the previous instruction. */ | |
1648 | if ((! mips_opts.mips16 | |
9ce8a5dd | 1649 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 RH |
1650 | && (prev_prev_insn.insn_mo->pinfo & INSN_COPROC_MOVE_DELAY) |
1651 | && (prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE) | |
1652 | && (pinfo & INSN_READ_COND_CODE) | |
1653 | && ! cop_interlocks) | |
1654 | || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_LO) | |
1655 | && (pinfo & INSN_WRITE_LO) | |
1656 | && ! (hilo_interlocks | |
ec68c924 | 1657 | || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT)))) |
252b5132 RH |
1658 | || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI) |
1659 | && (pinfo & INSN_WRITE_HI) | |
1660 | && ! (hilo_interlocks | |
ec68c924 | 1661 | || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT))))) |
252b5132 RH |
1662 | prev_prev_nop = 1; |
1663 | else | |
1664 | prev_prev_nop = 0; | |
1665 | ||
1666 | if (prev_prev_insn_unreordered) | |
1667 | prev_prev_nop = 0; | |
1668 | ||
1669 | if (prev_prev_nop && nops == 0) | |
1670 | ++nops; | |
1671 | ||
1672 | /* If we are being given a nop instruction, don't bother with | |
1673 | one of the nops we would otherwise output. This will only | |
1674 | happen when a nop instruction is used with mips_optimize set | |
1675 | to 0. */ | |
1676 | if (nops > 0 | |
1677 | && ! mips_opts.noreorder | |
156c2f8b | 1678 | && ip->insn_opcode == (unsigned) (mips_opts.mips16 ? 0x6500 : 0)) |
252b5132 RH |
1679 | --nops; |
1680 | ||
1681 | /* Now emit the right number of NOP instructions. */ | |
1682 | if (nops > 0 && ! mips_opts.noreorder) | |
1683 | { | |
1684 | fragS *old_frag; | |
1685 | unsigned long old_frag_offset; | |
1686 | int i; | |
1687 | struct insn_label_list *l; | |
1688 | ||
1689 | old_frag = frag_now; | |
1690 | old_frag_offset = frag_now_fix (); | |
1691 | ||
1692 | for (i = 0; i < nops; i++) | |
1693 | emit_nop (); | |
1694 | ||
1695 | if (listing) | |
1696 | { | |
1697 | listing_prev_line (); | |
1698 | /* We may be at the start of a variant frag. In case we | |
1699 | are, make sure there is enough space for the frag | |
1700 | after the frags created by listing_prev_line. The | |
1701 | argument to frag_grow here must be at least as large | |
1702 | as the argument to all other calls to frag_grow in | |
1703 | this file. We don't have to worry about being in the | |
1704 | middle of a variant frag, because the variants insert | |
1705 | all needed nop instructions themselves. */ | |
1706 | frag_grow (40); | |
1707 | } | |
1708 | ||
1709 | for (l = insn_labels; l != NULL; l = l->next) | |
1710 | { | |
98aa84af AM |
1711 | valueT val; |
1712 | ||
252b5132 | 1713 | assert (S_GET_SEGMENT (l->label) == now_seg); |
49309057 | 1714 | symbol_set_frag (l->label, frag_now); |
98aa84af | 1715 | val = (valueT) frag_now_fix (); |
252b5132 RH |
1716 | /* mips16 text labels are stored as odd. */ |
1717 | if (mips_opts.mips16) | |
98aa84af AM |
1718 | val += 1; |
1719 | S_SET_VALUE (l->label, val); | |
252b5132 RH |
1720 | } |
1721 | ||
1722 | #ifndef NO_ECOFF_DEBUGGING | |
1723 | if (ECOFF_DEBUGGING) | |
1724 | ecoff_fix_loc (old_frag, old_frag_offset); | |
1725 | #endif | |
1726 | } | |
1727 | else if (prev_nop_frag != NULL) | |
1728 | { | |
1729 | /* We have a frag holding nops we may be able to remove. If | |
1730 | we don't need any nops, we can decrease the size of | |
1731 | prev_nop_frag by the size of one instruction. If we do | |
bdaaa2e1 | 1732 | need some nops, we count them in prev_nops_required. */ |
252b5132 RH |
1733 | if (prev_nop_frag_since == 0) |
1734 | { | |
1735 | if (nops == 0) | |
1736 | { | |
1737 | prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4; | |
1738 | --prev_nop_frag_holds; | |
1739 | } | |
1740 | else | |
1741 | prev_nop_frag_required += nops; | |
1742 | } | |
1743 | else | |
1744 | { | |
1745 | if (prev_prev_nop == 0) | |
1746 | { | |
1747 | prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4; | |
1748 | --prev_nop_frag_holds; | |
1749 | } | |
1750 | else | |
1751 | ++prev_nop_frag_required; | |
1752 | } | |
1753 | ||
1754 | if (prev_nop_frag_holds <= prev_nop_frag_required) | |
1755 | prev_nop_frag = NULL; | |
1756 | ||
1757 | ++prev_nop_frag_since; | |
1758 | ||
1759 | /* Sanity check: by the time we reach the second instruction | |
1760 | after prev_nop_frag, we should have used up all the nops | |
1761 | one way or another. */ | |
1762 | assert (prev_nop_frag_since <= 1 || prev_nop_frag == NULL); | |
1763 | } | |
1764 | } | |
1765 | ||
1766 | if (reloc_type > BFD_RELOC_UNUSED) | |
1767 | { | |
1768 | /* We need to set up a variant frag. */ | |
1769 | assert (mips_opts.mips16 && address_expr != NULL); | |
1770 | f = frag_var (rs_machine_dependent, 4, 0, | |
1771 | RELAX_MIPS16_ENCODE (reloc_type - BFD_RELOC_UNUSED, | |
1772 | mips16_small, mips16_ext, | |
1773 | (prev_pinfo | |
1774 | & INSN_UNCOND_BRANCH_DELAY), | |
1775 | (prev_insn_reloc_type | |
1776 | == BFD_RELOC_MIPS16_JMP)), | |
1777 | make_expr_symbol (address_expr), (offsetT) 0, | |
1778 | (char *) NULL); | |
1779 | } | |
1780 | else if (place != NULL) | |
1781 | f = place; | |
1782 | else if (mips_opts.mips16 | |
1783 | && ! ip->use_extend | |
1784 | && reloc_type != BFD_RELOC_MIPS16_JMP) | |
1785 | { | |
1786 | /* Make sure there is enough room to swap this instruction with | |
1787 | a following jump instruction. */ | |
1788 | frag_grow (6); | |
1789 | f = frag_more (2); | |
1790 | } | |
1791 | else | |
1792 | { | |
1793 | if (mips_opts.mips16 | |
1794 | && mips_opts.noreorder | |
1795 | && (prev_pinfo & INSN_UNCOND_BRANCH_DELAY) != 0) | |
1796 | as_warn (_("extended instruction in delay slot")); | |
1797 | ||
1798 | f = frag_more (4); | |
1799 | } | |
1800 | ||
1801 | fixp = NULL; | |
1802 | if (address_expr != NULL && reloc_type < BFD_RELOC_UNUSED) | |
1803 | { | |
1804 | if (address_expr->X_op == O_constant) | |
1805 | { | |
1806 | switch (reloc_type) | |
1807 | { | |
1808 | case BFD_RELOC_32: | |
1809 | ip->insn_opcode |= address_expr->X_add_number; | |
1810 | break; | |
1811 | ||
1812 | case BFD_RELOC_LO16: | |
1813 | ip->insn_opcode |= address_expr->X_add_number & 0xffff; | |
1814 | break; | |
1815 | ||
1816 | case BFD_RELOC_MIPS_JMP: | |
1817 | if ((address_expr->X_add_number & 3) != 0) | |
1818 | as_bad (_("jump to misaligned address (0x%lx)"), | |
1819 | (unsigned long) address_expr->X_add_number); | |
1820 | ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0x3ffffff; | |
1821 | break; | |
1822 | ||
1823 | case BFD_RELOC_MIPS16_JMP: | |
1824 | if ((address_expr->X_add_number & 3) != 0) | |
1825 | as_bad (_("jump to misaligned address (0x%lx)"), | |
1826 | (unsigned long) address_expr->X_add_number); | |
1827 | ip->insn_opcode |= | |
1828 | (((address_expr->X_add_number & 0x7c0000) << 3) | |
1829 | | ((address_expr->X_add_number & 0xf800000) >> 7) | |
1830 | | ((address_expr->X_add_number & 0x3fffc) >> 2)); | |
1831 | break; | |
1832 | ||
252b5132 RH |
1833 | case BFD_RELOC_16_PCREL_S2: |
1834 | goto need_reloc; | |
1835 | ||
1836 | default: | |
1837 | internalError (); | |
1838 | } | |
1839 | } | |
1840 | else | |
1841 | { | |
1842 | need_reloc: | |
1843 | /* Don't generate a reloc if we are writing into a variant | |
1844 | frag. */ | |
1845 | if (place == NULL) | |
1846 | { | |
1847 | fixp = fix_new_exp (frag_now, f - frag_now->fr_literal, 4, | |
1848 | address_expr, | |
1849 | reloc_type == BFD_RELOC_16_PCREL_S2, | |
1850 | reloc_type); | |
1851 | if (unmatched_hi) | |
1852 | { | |
1853 | struct mips_hi_fixup *hi_fixup; | |
1854 | ||
1855 | assert (reloc_type == BFD_RELOC_HI16_S); | |
1856 | hi_fixup = ((struct mips_hi_fixup *) | |
1857 | xmalloc (sizeof (struct mips_hi_fixup))); | |
1858 | hi_fixup->fixp = fixp; | |
1859 | hi_fixup->seg = now_seg; | |
1860 | hi_fixup->next = mips_hi_fixup_list; | |
1861 | mips_hi_fixup_list = hi_fixup; | |
1862 | } | |
1863 | } | |
1864 | } | |
1865 | } | |
1866 | ||
1867 | if (! mips_opts.mips16) | |
1868 | md_number_to_chars (f, ip->insn_opcode, 4); | |
1869 | else if (reloc_type == BFD_RELOC_MIPS16_JMP) | |
1870 | { | |
1871 | md_number_to_chars (f, ip->insn_opcode >> 16, 2); | |
1872 | md_number_to_chars (f + 2, ip->insn_opcode & 0xffff, 2); | |
1873 | } | |
1874 | else | |
1875 | { | |
1876 | if (ip->use_extend) | |
1877 | { | |
1878 | md_number_to_chars (f, 0xf000 | ip->extend, 2); | |
1879 | f += 2; | |
1880 | } | |
1881 | md_number_to_chars (f, ip->insn_opcode, 2); | |
1882 | } | |
1883 | ||
1884 | /* Update the register mask information. */ | |
1885 | if (! mips_opts.mips16) | |
1886 | { | |
1887 | if (pinfo & INSN_WRITE_GPR_D) | |
1888 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD); | |
1889 | if ((pinfo & (INSN_WRITE_GPR_T | INSN_READ_GPR_T)) != 0) | |
1890 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT); | |
1891 | if (pinfo & INSN_READ_GPR_S) | |
1892 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS); | |
1893 | if (pinfo & INSN_WRITE_GPR_31) | |
1894 | mips_gprmask |= 1 << 31; | |
1895 | if (pinfo & INSN_WRITE_FPR_D) | |
1896 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FD) & OP_MASK_FD); | |
1897 | if ((pinfo & (INSN_WRITE_FPR_S | INSN_READ_FPR_S)) != 0) | |
1898 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS); | |
1899 | if ((pinfo & (INSN_WRITE_FPR_T | INSN_READ_FPR_T)) != 0) | |
1900 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT); | |
1901 | if ((pinfo & INSN_READ_FPR_R) != 0) | |
1902 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FR) & OP_MASK_FR); | |
1903 | if (pinfo & INSN_COP) | |
1904 | { | |
bdaaa2e1 KH |
1905 | /* We don't keep enough information to sort these cases out. |
1906 | The itbl support does keep this information however, although | |
1907 | we currently don't support itbl fprmats as part of the cop | |
1908 | instruction. May want to add this support in the future. */ | |
252b5132 RH |
1909 | } |
1910 | /* Never set the bit for $0, which is always zero. */ | |
beae10d5 | 1911 | mips_gprmask &= ~1 << 0; |
252b5132 RH |
1912 | } |
1913 | else | |
1914 | { | |
1915 | if (pinfo & (MIPS16_INSN_WRITE_X | MIPS16_INSN_READ_X)) | |
1916 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RX) | |
1917 | & MIPS16OP_MASK_RX); | |
1918 | if (pinfo & (MIPS16_INSN_WRITE_Y | MIPS16_INSN_READ_Y)) | |
1919 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RY) | |
1920 | & MIPS16OP_MASK_RY); | |
1921 | if (pinfo & MIPS16_INSN_WRITE_Z) | |
1922 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RZ) | |
1923 | & MIPS16OP_MASK_RZ); | |
1924 | if (pinfo & (MIPS16_INSN_WRITE_T | MIPS16_INSN_READ_T)) | |
1925 | mips_gprmask |= 1 << TREG; | |
1926 | if (pinfo & (MIPS16_INSN_WRITE_SP | MIPS16_INSN_READ_SP)) | |
1927 | mips_gprmask |= 1 << SP; | |
1928 | if (pinfo & (MIPS16_INSN_WRITE_31 | MIPS16_INSN_READ_31)) | |
1929 | mips_gprmask |= 1 << RA; | |
1930 | if (pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
1931 | mips_gprmask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode); | |
1932 | if (pinfo & MIPS16_INSN_READ_Z) | |
1933 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z) | |
1934 | & MIPS16OP_MASK_MOVE32Z); | |
1935 | if (pinfo & MIPS16_INSN_READ_GPR_X) | |
1936 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_REGR32) | |
1937 | & MIPS16OP_MASK_REGR32); | |
1938 | } | |
1939 | ||
1940 | if (place == NULL && ! mips_opts.noreorder) | |
1941 | { | |
1942 | /* Filling the branch delay slot is more complex. We try to | |
1943 | switch the branch with the previous instruction, which we can | |
1944 | do if the previous instruction does not set up a condition | |
1945 | that the branch tests and if the branch is not itself the | |
1946 | target of any branch. */ | |
1947 | if ((pinfo & INSN_UNCOND_BRANCH_DELAY) | |
1948 | || (pinfo & INSN_COND_BRANCH_DELAY)) | |
1949 | { | |
1950 | if (mips_optimize < 2 | |
1951 | /* If we have seen .set volatile or .set nomove, don't | |
1952 | optimize. */ | |
1953 | || mips_opts.nomove != 0 | |
1954 | /* If we had to emit any NOP instructions, then we | |
1955 | already know we can not swap. */ | |
1956 | || nops != 0 | |
1957 | /* If we don't even know the previous insn, we can not | |
bdaaa2e1 | 1958 | swap. */ |
252b5132 RH |
1959 | || ! prev_insn_valid |
1960 | /* If the previous insn is already in a branch delay | |
1961 | slot, then we can not swap. */ | |
1962 | || prev_insn_is_delay_slot | |
1963 | /* If the previous previous insn was in a .set | |
1964 | noreorder, we can't swap. Actually, the MIPS | |
1965 | assembler will swap in this situation. However, gcc | |
1966 | configured -with-gnu-as will generate code like | |
1967 | .set noreorder | |
1968 | lw $4,XXX | |
1969 | .set reorder | |
1970 | INSN | |
1971 | bne $4,$0,foo | |
1972 | in which we can not swap the bne and INSN. If gcc is | |
1973 | not configured -with-gnu-as, it does not output the | |
1974 | .set pseudo-ops. We don't have to check | |
1975 | prev_insn_unreordered, because prev_insn_valid will | |
1976 | be 0 in that case. We don't want to use | |
1977 | prev_prev_insn_valid, because we do want to be able | |
1978 | to swap at the start of a function. */ | |
1979 | || prev_prev_insn_unreordered | |
1980 | /* If the branch is itself the target of a branch, we | |
1981 | can not swap. We cheat on this; all we check for is | |
1982 | whether there is a label on this instruction. If | |
1983 | there are any branches to anything other than a | |
1984 | label, users must use .set noreorder. */ | |
1985 | || insn_labels != NULL | |
1986 | /* If the previous instruction is in a variant frag, we | |
1987 | can not do the swap. This does not apply to the | |
1988 | mips16, which uses variant frags for different | |
1989 | purposes. */ | |
1990 | || (! mips_opts.mips16 | |
1991 | && prev_insn_frag->fr_type == rs_machine_dependent) | |
1992 | /* If the branch reads the condition codes, we don't | |
1993 | even try to swap, because in the sequence | |
1994 | ctc1 $X,$31 | |
1995 | INSN | |
1996 | INSN | |
1997 | bc1t LABEL | |
1998 | we can not swap, and I don't feel like handling that | |
1999 | case. */ | |
2000 | || (! mips_opts.mips16 | |
9ce8a5dd | 2001 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 RH |
2002 | && (pinfo & INSN_READ_COND_CODE)) |
2003 | /* We can not swap with an instruction that requires a | |
2004 | delay slot, becase the target of the branch might | |
2005 | interfere with that instruction. */ | |
2006 | || (! mips_opts.mips16 | |
9ce8a5dd | 2007 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 | 2008 | && (prev_pinfo |
bdaaa2e1 | 2009 | /* Itbl support may require additional care here. */ |
252b5132 RH |
2010 | & (INSN_LOAD_COPROC_DELAY |
2011 | | INSN_COPROC_MOVE_DELAY | |
2012 | | INSN_WRITE_COND_CODE))) | |
2013 | || (! (hilo_interlocks | |
ec68c924 | 2014 | || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT))) |
252b5132 RH |
2015 | && (prev_pinfo |
2016 | & (INSN_READ_LO | |
2017 | | INSN_READ_HI))) | |
2018 | || (! mips_opts.mips16 | |
2019 | && ! gpr_interlocks | |
2020 | && (prev_pinfo & INSN_LOAD_MEMORY_DELAY)) | |
2021 | || (! mips_opts.mips16 | |
e7af610e | 2022 | && mips_opts.isa == ISA_MIPS1 |
bdaaa2e1 | 2023 | /* Itbl support may require additional care here. */ |
252b5132 RH |
2024 | && (prev_pinfo & INSN_COPROC_MEMORY_DELAY)) |
2025 | /* We can not swap with a branch instruction. */ | |
2026 | || (prev_pinfo | |
2027 | & (INSN_UNCOND_BRANCH_DELAY | |
2028 | | INSN_COND_BRANCH_DELAY | |
2029 | | INSN_COND_BRANCH_LIKELY)) | |
2030 | /* We do not swap with a trap instruction, since it | |
2031 | complicates trap handlers to have the trap | |
2032 | instruction be in a delay slot. */ | |
2033 | || (prev_pinfo & INSN_TRAP) | |
2034 | /* If the branch reads a register that the previous | |
2035 | instruction sets, we can not swap. */ | |
2036 | || (! mips_opts.mips16 | |
2037 | && (prev_pinfo & INSN_WRITE_GPR_T) | |
2038 | && insn_uses_reg (ip, | |
2039 | ((prev_insn.insn_opcode >> OP_SH_RT) | |
2040 | & OP_MASK_RT), | |
2041 | MIPS_GR_REG)) | |
2042 | || (! mips_opts.mips16 | |
2043 | && (prev_pinfo & INSN_WRITE_GPR_D) | |
2044 | && insn_uses_reg (ip, | |
2045 | ((prev_insn.insn_opcode >> OP_SH_RD) | |
2046 | & OP_MASK_RD), | |
2047 | MIPS_GR_REG)) | |
2048 | || (mips_opts.mips16 | |
2049 | && (((prev_pinfo & MIPS16_INSN_WRITE_X) | |
2050 | && insn_uses_reg (ip, | |
2051 | ((prev_insn.insn_opcode | |
2052 | >> MIPS16OP_SH_RX) | |
2053 | & MIPS16OP_MASK_RX), | |
2054 | MIPS16_REG)) | |
2055 | || ((prev_pinfo & MIPS16_INSN_WRITE_Y) | |
2056 | && insn_uses_reg (ip, | |
2057 | ((prev_insn.insn_opcode | |
2058 | >> MIPS16OP_SH_RY) | |
2059 | & MIPS16OP_MASK_RY), | |
2060 | MIPS16_REG)) | |
2061 | || ((prev_pinfo & MIPS16_INSN_WRITE_Z) | |
2062 | && insn_uses_reg (ip, | |
2063 | ((prev_insn.insn_opcode | |
2064 | >> MIPS16OP_SH_RZ) | |
2065 | & MIPS16OP_MASK_RZ), | |
2066 | MIPS16_REG)) | |
2067 | || ((prev_pinfo & MIPS16_INSN_WRITE_T) | |
2068 | && insn_uses_reg (ip, TREG, MIPS_GR_REG)) | |
2069 | || ((prev_pinfo & MIPS16_INSN_WRITE_31) | |
2070 | && insn_uses_reg (ip, RA, MIPS_GR_REG)) | |
2071 | || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
2072 | && insn_uses_reg (ip, | |
2073 | MIPS16OP_EXTRACT_REG32R (prev_insn. | |
2074 | insn_opcode), | |
2075 | MIPS_GR_REG)))) | |
2076 | /* If the branch writes a register that the previous | |
2077 | instruction sets, we can not swap (we know that | |
2078 | branches write only to RD or to $31). */ | |
2079 | || (! mips_opts.mips16 | |
2080 | && (prev_pinfo & INSN_WRITE_GPR_T) | |
2081 | && (((pinfo & INSN_WRITE_GPR_D) | |
2082 | && (((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT) | |
2083 | == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD))) | |
2084 | || ((pinfo & INSN_WRITE_GPR_31) | |
2085 | && (((prev_insn.insn_opcode >> OP_SH_RT) | |
2086 | & OP_MASK_RT) | |
2087 | == 31)))) | |
2088 | || (! mips_opts.mips16 | |
2089 | && (prev_pinfo & INSN_WRITE_GPR_D) | |
2090 | && (((pinfo & INSN_WRITE_GPR_D) | |
2091 | && (((prev_insn.insn_opcode >> OP_SH_RD) & OP_MASK_RD) | |
2092 | == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD))) | |
2093 | || ((pinfo & INSN_WRITE_GPR_31) | |
2094 | && (((prev_insn.insn_opcode >> OP_SH_RD) | |
2095 | & OP_MASK_RD) | |
2096 | == 31)))) | |
2097 | || (mips_opts.mips16 | |
2098 | && (pinfo & MIPS16_INSN_WRITE_31) | |
2099 | && ((prev_pinfo & MIPS16_INSN_WRITE_31) | |
2100 | || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
2101 | && (MIPS16OP_EXTRACT_REG32R (prev_insn.insn_opcode) | |
2102 | == RA)))) | |
2103 | /* If the branch writes a register that the previous | |
2104 | instruction reads, we can not swap (we know that | |
2105 | branches only write to RD or to $31). */ | |
2106 | || (! mips_opts.mips16 | |
2107 | && (pinfo & INSN_WRITE_GPR_D) | |
2108 | && insn_uses_reg (&prev_insn, | |
2109 | ((ip->insn_opcode >> OP_SH_RD) | |
2110 | & OP_MASK_RD), | |
2111 | MIPS_GR_REG)) | |
2112 | || (! mips_opts.mips16 | |
2113 | && (pinfo & INSN_WRITE_GPR_31) | |
2114 | && insn_uses_reg (&prev_insn, 31, MIPS_GR_REG)) | |
2115 | || (mips_opts.mips16 | |
2116 | && (pinfo & MIPS16_INSN_WRITE_31) | |
2117 | && insn_uses_reg (&prev_insn, RA, MIPS_GR_REG)) | |
2118 | /* If we are generating embedded PIC code, the branch | |
2119 | might be expanded into a sequence which uses $at, so | |
2120 | we can't swap with an instruction which reads it. */ | |
2121 | || (mips_pic == EMBEDDED_PIC | |
2122 | && insn_uses_reg (&prev_insn, AT, MIPS_GR_REG)) | |
2123 | /* If the previous previous instruction has a load | |
2124 | delay, and sets a register that the branch reads, we | |
2125 | can not swap. */ | |
2126 | || (! mips_opts.mips16 | |
9ce8a5dd | 2127 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
bdaaa2e1 | 2128 | /* Itbl support may require additional care here. */ |
252b5132 RH |
2129 | && ((prev_prev_insn.insn_mo->pinfo & INSN_LOAD_COPROC_DELAY) |
2130 | || (! gpr_interlocks | |
2131 | && (prev_prev_insn.insn_mo->pinfo | |
2132 | & INSN_LOAD_MEMORY_DELAY))) | |
2133 | && insn_uses_reg (ip, | |
2134 | ((prev_prev_insn.insn_opcode >> OP_SH_RT) | |
2135 | & OP_MASK_RT), | |
2136 | MIPS_GR_REG)) | |
2137 | /* If one instruction sets a condition code and the | |
2138 | other one uses a condition code, we can not swap. */ | |
2139 | || ((pinfo & INSN_READ_COND_CODE) | |
2140 | && (prev_pinfo & INSN_WRITE_COND_CODE)) | |
2141 | || ((pinfo & INSN_WRITE_COND_CODE) | |
2142 | && (prev_pinfo & INSN_READ_COND_CODE)) | |
2143 | /* If the previous instruction uses the PC, we can not | |
2144 | swap. */ | |
2145 | || (mips_opts.mips16 | |
2146 | && (prev_pinfo & MIPS16_INSN_READ_PC)) | |
2147 | /* If the previous instruction was extended, we can not | |
2148 | swap. */ | |
2149 | || (mips_opts.mips16 && prev_insn_extended) | |
2150 | /* If the previous instruction had a fixup in mips16 | |
2151 | mode, we can not swap. This normally means that the | |
2152 | previous instruction was a 4 byte branch anyhow. */ | |
2153 | || (mips_opts.mips16 && prev_insn_fixp) | |
bdaaa2e1 KH |
2154 | /* If the previous instruction is a sync, sync.l, or |
2155 | sync.p, we can not swap. */ | |
f173e82e | 2156 | || (prev_pinfo & INSN_SYNC)) |
252b5132 RH |
2157 | { |
2158 | /* We could do even better for unconditional branches to | |
2159 | portions of this object file; we could pick up the | |
2160 | instruction at the destination, put it in the delay | |
2161 | slot, and bump the destination address. */ | |
2162 | emit_nop (); | |
2163 | /* Update the previous insn information. */ | |
2164 | prev_prev_insn = *ip; | |
2165 | prev_insn.insn_mo = &dummy_opcode; | |
2166 | } | |
2167 | else | |
2168 | { | |
2169 | /* It looks like we can actually do the swap. */ | |
2170 | if (! mips_opts.mips16) | |
2171 | { | |
2172 | char *prev_f; | |
2173 | char temp[4]; | |
2174 | ||
2175 | prev_f = prev_insn_frag->fr_literal + prev_insn_where; | |
2176 | memcpy (temp, prev_f, 4); | |
2177 | memcpy (prev_f, f, 4); | |
2178 | memcpy (f, temp, 4); | |
2179 | if (prev_insn_fixp) | |
2180 | { | |
2181 | prev_insn_fixp->fx_frag = frag_now; | |
2182 | prev_insn_fixp->fx_where = f - frag_now->fr_literal; | |
2183 | } | |
2184 | if (fixp) | |
2185 | { | |
2186 | fixp->fx_frag = prev_insn_frag; | |
2187 | fixp->fx_where = prev_insn_where; | |
2188 | } | |
2189 | } | |
2190 | else | |
2191 | { | |
2192 | char *prev_f; | |
2193 | char temp[2]; | |
2194 | ||
2195 | assert (prev_insn_fixp == NULL); | |
2196 | prev_f = prev_insn_frag->fr_literal + prev_insn_where; | |
2197 | memcpy (temp, prev_f, 2); | |
2198 | memcpy (prev_f, f, 2); | |
2199 | if (reloc_type != BFD_RELOC_MIPS16_JMP) | |
2200 | { | |
2201 | assert (reloc_type == BFD_RELOC_UNUSED); | |
2202 | memcpy (f, temp, 2); | |
2203 | } | |
2204 | else | |
2205 | { | |
2206 | memcpy (f, f + 2, 2); | |
2207 | memcpy (f + 2, temp, 2); | |
2208 | } | |
2209 | if (fixp) | |
2210 | { | |
2211 | fixp->fx_frag = prev_insn_frag; | |
2212 | fixp->fx_where = prev_insn_where; | |
2213 | } | |
2214 | } | |
2215 | ||
2216 | /* Update the previous insn information; leave prev_insn | |
2217 | unchanged. */ | |
2218 | prev_prev_insn = *ip; | |
2219 | } | |
2220 | prev_insn_is_delay_slot = 1; | |
2221 | ||
2222 | /* If that was an unconditional branch, forget the previous | |
2223 | insn information. */ | |
2224 | if (pinfo & INSN_UNCOND_BRANCH_DELAY) | |
2225 | { | |
2226 | prev_prev_insn.insn_mo = &dummy_opcode; | |
2227 | prev_insn.insn_mo = &dummy_opcode; | |
2228 | } | |
2229 | ||
2230 | prev_insn_fixp = NULL; | |
2231 | prev_insn_reloc_type = BFD_RELOC_UNUSED; | |
2232 | prev_insn_extended = 0; | |
2233 | } | |
2234 | else if (pinfo & INSN_COND_BRANCH_LIKELY) | |
2235 | { | |
2236 | /* We don't yet optimize a branch likely. What we should do | |
2237 | is look at the target, copy the instruction found there | |
2238 | into the delay slot, and increment the branch to jump to | |
2239 | the next instruction. */ | |
2240 | emit_nop (); | |
2241 | /* Update the previous insn information. */ | |
2242 | prev_prev_insn = *ip; | |
2243 | prev_insn.insn_mo = &dummy_opcode; | |
2244 | prev_insn_fixp = NULL; | |
2245 | prev_insn_reloc_type = BFD_RELOC_UNUSED; | |
2246 | prev_insn_extended = 0; | |
2247 | } | |
2248 | else | |
2249 | { | |
2250 | /* Update the previous insn information. */ | |
2251 | if (nops > 0) | |
2252 | prev_prev_insn.insn_mo = &dummy_opcode; | |
2253 | else | |
2254 | prev_prev_insn = prev_insn; | |
2255 | prev_insn = *ip; | |
2256 | ||
2257 | /* Any time we see a branch, we always fill the delay slot | |
2258 | immediately; since this insn is not a branch, we know it | |
2259 | is not in a delay slot. */ | |
2260 | prev_insn_is_delay_slot = 0; | |
2261 | ||
2262 | prev_insn_fixp = fixp; | |
2263 | prev_insn_reloc_type = reloc_type; | |
2264 | if (mips_opts.mips16) | |
2265 | prev_insn_extended = (ip->use_extend | |
2266 | || reloc_type > BFD_RELOC_UNUSED); | |
2267 | } | |
2268 | ||
2269 | prev_prev_insn_unreordered = prev_insn_unreordered; | |
2270 | prev_insn_unreordered = 0; | |
2271 | prev_insn_frag = frag_now; | |
2272 | prev_insn_where = f - frag_now->fr_literal; | |
2273 | prev_insn_valid = 1; | |
2274 | } | |
2275 | else if (place == NULL) | |
2276 | { | |
2277 | /* We need to record a bit of information even when we are not | |
2278 | reordering, in order to determine the base address for mips16 | |
2279 | PC relative relocs. */ | |
2280 | prev_prev_insn = prev_insn; | |
2281 | prev_insn = *ip; | |
2282 | prev_insn_reloc_type = reloc_type; | |
2283 | prev_prev_insn_unreordered = prev_insn_unreordered; | |
2284 | prev_insn_unreordered = 1; | |
2285 | } | |
2286 | ||
2287 | /* We just output an insn, so the next one doesn't have a label. */ | |
2288 | mips_clear_insn_labels (); | |
2289 | ||
2290 | /* We must ensure that a fixup associated with an unmatched %hi | |
2291 | reloc does not become a variant frag. Otherwise, the | |
2292 | rearrangement of %hi relocs in frob_file may confuse | |
2293 | tc_gen_reloc. */ | |
2294 | if (unmatched_hi) | |
2295 | { | |
2296 | frag_wane (frag_now); | |
2297 | frag_new (0); | |
2298 | } | |
2299 | } | |
2300 | ||
2301 | /* This function forgets that there was any previous instruction or | |
2302 | label. If PRESERVE is non-zero, it remembers enough information to | |
bdaaa2e1 | 2303 | know whether nops are needed before a noreorder section. */ |
252b5132 RH |
2304 | |
2305 | static void | |
2306 | mips_no_prev_insn (preserve) | |
2307 | int preserve; | |
2308 | { | |
2309 | if (! preserve) | |
2310 | { | |
2311 | prev_insn.insn_mo = &dummy_opcode; | |
2312 | prev_prev_insn.insn_mo = &dummy_opcode; | |
2313 | prev_nop_frag = NULL; | |
2314 | prev_nop_frag_holds = 0; | |
2315 | prev_nop_frag_required = 0; | |
2316 | prev_nop_frag_since = 0; | |
2317 | } | |
2318 | prev_insn_valid = 0; | |
2319 | prev_insn_is_delay_slot = 0; | |
2320 | prev_insn_unreordered = 0; | |
2321 | prev_insn_extended = 0; | |
2322 | prev_insn_reloc_type = BFD_RELOC_UNUSED; | |
2323 | prev_prev_insn_unreordered = 0; | |
2324 | mips_clear_insn_labels (); | |
2325 | } | |
2326 | ||
2327 | /* This function must be called whenever we turn on noreorder or emit | |
2328 | something other than instructions. It inserts any NOPS which might | |
2329 | be needed by the previous instruction, and clears the information | |
2330 | kept for the previous instructions. The INSNS parameter is true if | |
bdaaa2e1 | 2331 | instructions are to follow. */ |
252b5132 RH |
2332 | |
2333 | static void | |
2334 | mips_emit_delays (insns) | |
2335 | boolean insns; | |
2336 | { | |
2337 | if (! mips_opts.noreorder) | |
2338 | { | |
2339 | int nops; | |
2340 | ||
2341 | nops = 0; | |
2342 | if ((! mips_opts.mips16 | |
9ce8a5dd | 2343 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 RH |
2344 | && (! cop_interlocks |
2345 | && (prev_insn.insn_mo->pinfo | |
2346 | & (INSN_LOAD_COPROC_DELAY | |
2347 | | INSN_COPROC_MOVE_DELAY | |
2348 | | INSN_WRITE_COND_CODE)))) | |
2349 | || (! hilo_interlocks | |
2350 | && (prev_insn.insn_mo->pinfo | |
2351 | & (INSN_READ_LO | |
2352 | | INSN_READ_HI))) | |
2353 | || (! mips_opts.mips16 | |
2354 | && ! gpr_interlocks | |
bdaaa2e1 | 2355 | && (prev_insn.insn_mo->pinfo |
252b5132 RH |
2356 | & INSN_LOAD_MEMORY_DELAY)) |
2357 | || (! mips_opts.mips16 | |
e7af610e | 2358 | && mips_opts.isa == ISA_MIPS1 |
252b5132 RH |
2359 | && (prev_insn.insn_mo->pinfo |
2360 | & INSN_COPROC_MEMORY_DELAY))) | |
2361 | { | |
beae10d5 | 2362 | /* Itbl support may require additional care here. */ |
252b5132 RH |
2363 | ++nops; |
2364 | if ((! mips_opts.mips16 | |
9ce8a5dd | 2365 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 RH |
2366 | && (! cop_interlocks |
2367 | && prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)) | |
2368 | || (! hilo_interlocks | |
2369 | && ((prev_insn.insn_mo->pinfo & INSN_READ_HI) | |
2370 | || (prev_insn.insn_mo->pinfo & INSN_READ_LO)))) | |
2371 | ++nops; | |
2372 | ||
2373 | if (prev_insn_unreordered) | |
2374 | nops = 0; | |
2375 | } | |
2376 | else if ((! mips_opts.mips16 | |
9ce8a5dd | 2377 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 RH |
2378 | && (! cop_interlocks |
2379 | && prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)) | |
2380 | || (! hilo_interlocks | |
2381 | && ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI) | |
2382 | || (prev_prev_insn.insn_mo->pinfo & INSN_READ_LO)))) | |
2383 | { | |
beae10d5 | 2384 | /* Itbl support may require additional care here. */ |
252b5132 RH |
2385 | if (! prev_prev_insn_unreordered) |
2386 | ++nops; | |
2387 | } | |
2388 | ||
2389 | if (nops > 0) | |
2390 | { | |
2391 | struct insn_label_list *l; | |
2392 | ||
2393 | if (insns) | |
2394 | { | |
2395 | /* Record the frag which holds the nop instructions, so | |
2396 | that we can remove them if we don't need them. */ | |
2397 | frag_grow (mips_opts.mips16 ? nops * 2 : nops * 4); | |
2398 | prev_nop_frag = frag_now; | |
2399 | prev_nop_frag_holds = nops; | |
2400 | prev_nop_frag_required = 0; | |
2401 | prev_nop_frag_since = 0; | |
2402 | } | |
2403 | ||
2404 | for (; nops > 0; --nops) | |
2405 | emit_nop (); | |
2406 | ||
2407 | if (insns) | |
2408 | { | |
2409 | /* Move on to a new frag, so that it is safe to simply | |
bdaaa2e1 | 2410 | decrease the size of prev_nop_frag. */ |
252b5132 RH |
2411 | frag_wane (frag_now); |
2412 | frag_new (0); | |
2413 | } | |
2414 | ||
2415 | for (l = insn_labels; l != NULL; l = l->next) | |
2416 | { | |
98aa84af AM |
2417 | valueT val; |
2418 | ||
252b5132 | 2419 | assert (S_GET_SEGMENT (l->label) == now_seg); |
49309057 | 2420 | symbol_set_frag (l->label, frag_now); |
98aa84af | 2421 | val = (valueT) frag_now_fix (); |
252b5132 RH |
2422 | /* mips16 text labels are stored as odd. */ |
2423 | if (mips_opts.mips16) | |
98aa84af AM |
2424 | val += 1; |
2425 | S_SET_VALUE (l->label, val); | |
252b5132 RH |
2426 | } |
2427 | } | |
2428 | } | |
2429 | ||
2430 | /* Mark instruction labels in mips16 mode. */ | |
2431 | if (mips_opts.mips16 && insns) | |
2432 | mips16_mark_labels (); | |
2433 | ||
2434 | mips_no_prev_insn (insns); | |
2435 | } | |
2436 | ||
2437 | /* Build an instruction created by a macro expansion. This is passed | |
2438 | a pointer to the count of instructions created so far, an | |
2439 | expression, the name of the instruction to build, an operand format | |
2440 | string, and corresponding arguments. */ | |
2441 | ||
2442 | #ifdef USE_STDARG | |
2443 | static void | |
2444 | macro_build (char *place, | |
2445 | int *counter, | |
2446 | expressionS * ep, | |
2447 | const char *name, | |
2448 | const char *fmt, | |
2449 | ...) | |
2450 | #else | |
2451 | static void | |
2452 | macro_build (place, counter, ep, name, fmt, va_alist) | |
2453 | char *place; | |
2454 | int *counter; | |
2455 | expressionS *ep; | |
2456 | const char *name; | |
2457 | const char *fmt; | |
2458 | va_dcl | |
2459 | #endif | |
2460 | { | |
2461 | struct mips_cl_insn insn; | |
2462 | bfd_reloc_code_real_type r; | |
2463 | va_list args; | |
252b5132 RH |
2464 | |
2465 | #ifdef USE_STDARG | |
2466 | va_start (args, fmt); | |
2467 | #else | |
2468 | va_start (args); | |
2469 | #endif | |
2470 | ||
2471 | /* | |
2472 | * If the macro is about to expand into a second instruction, | |
2473 | * print a warning if needed. We need to pass ip as a parameter | |
2474 | * to generate a better warning message here... | |
2475 | */ | |
2476 | if (mips_opts.warn_about_macros && place == NULL && *counter == 1) | |
2477 | as_warn (_("Macro instruction expanded into multiple instructions")); | |
2478 | ||
2479 | if (place == NULL) | |
2480 | *counter += 1; /* bump instruction counter */ | |
2481 | ||
2482 | if (mips_opts.mips16) | |
2483 | { | |
2484 | mips16_macro_build (place, counter, ep, name, fmt, args); | |
2485 | va_end (args); | |
2486 | return; | |
2487 | } | |
2488 | ||
2489 | r = BFD_RELOC_UNUSED; | |
2490 | insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name); | |
2491 | assert (insn.insn_mo); | |
2492 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
2493 | ||
2494 | /* Search until we get a match for NAME. */ | |
2495 | while (1) | |
2496 | { | |
252b5132 RH |
2497 | if (strcmp (fmt, insn.insn_mo->args) == 0 |
2498 | && insn.insn_mo->pinfo != INSN_MACRO | |
ec68c924 | 2499 | && OPCODE_IS_MEMBER (insn.insn_mo, mips_opts.isa, mips_arch, |
c97ef257 | 2500 | mips_gp32) |
ec68c924 | 2501 | && (mips_arch != CPU_R4650 || (insn.insn_mo->pinfo & FP_D) == 0)) |
252b5132 RH |
2502 | break; |
2503 | ||
2504 | ++insn.insn_mo; | |
2505 | assert (insn.insn_mo->name); | |
2506 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
2507 | } | |
2508 | ||
2509 | insn.insn_opcode = insn.insn_mo->match; | |
2510 | for (;;) | |
2511 | { | |
2512 | switch (*fmt++) | |
2513 | { | |
2514 | case '\0': | |
2515 | break; | |
2516 | ||
2517 | case ',': | |
2518 | case '(': | |
2519 | case ')': | |
2520 | continue; | |
2521 | ||
2522 | case 't': | |
2523 | case 'w': | |
2524 | case 'E': | |
2525 | insn.insn_opcode |= va_arg (args, int) << 16; | |
2526 | continue; | |
2527 | ||
2528 | case 'c': | |
2529 | case 'T': | |
2530 | case 'W': | |
2531 | insn.insn_opcode |= va_arg (args, int) << 16; | |
2532 | continue; | |
2533 | ||
2534 | case 'd': | |
2535 | case 'G': | |
2536 | insn.insn_opcode |= va_arg (args, int) << 11; | |
2537 | continue; | |
2538 | ||
4372b673 NC |
2539 | case 'U': |
2540 | { | |
2541 | int tmp = va_arg (args, int); | |
2542 | ||
2543 | insn.insn_opcode |= tmp << 16; | |
2544 | insn.insn_opcode |= tmp << 11; | |
beae10d5 | 2545 | continue; |
4372b673 NC |
2546 | } |
2547 | ||
252b5132 RH |
2548 | case 'V': |
2549 | case 'S': | |
2550 | insn.insn_opcode |= va_arg (args, int) << 11; | |
2551 | continue; | |
2552 | ||
2553 | case 'z': | |
2554 | continue; | |
2555 | ||
2556 | case '<': | |
2557 | insn.insn_opcode |= va_arg (args, int) << 6; | |
2558 | continue; | |
2559 | ||
2560 | case 'D': | |
2561 | insn.insn_opcode |= va_arg (args, int) << 6; | |
2562 | continue; | |
2563 | ||
2564 | case 'B': | |
2565 | insn.insn_opcode |= va_arg (args, int) << 6; | |
2566 | continue; | |
2567 | ||
4372b673 NC |
2568 | case 'J': |
2569 | insn.insn_opcode |= va_arg (args, int) << 6; | |
2570 | continue; | |
2571 | ||
252b5132 RH |
2572 | case 'q': |
2573 | insn.insn_opcode |= va_arg (args, int) << 6; | |
2574 | continue; | |
2575 | ||
2576 | case 'b': | |
2577 | case 's': | |
2578 | case 'r': | |
2579 | case 'v': | |
2580 | insn.insn_opcode |= va_arg (args, int) << 21; | |
2581 | continue; | |
2582 | ||
2583 | case 'i': | |
2584 | case 'j': | |
2585 | case 'o': | |
2586 | r = (bfd_reloc_code_real_type) va_arg (args, int); | |
2587 | assert (r == BFD_RELOC_MIPS_GPREL | |
2588 | || r == BFD_RELOC_MIPS_LITERAL | |
2589 | || r == BFD_RELOC_LO16 | |
2590 | || r == BFD_RELOC_MIPS_GOT16 | |
2591 | || r == BFD_RELOC_MIPS_CALL16 | |
2592 | || r == BFD_RELOC_MIPS_GOT_LO16 | |
2593 | || r == BFD_RELOC_MIPS_CALL_LO16 | |
2594 | || (ep->X_op == O_subtract | |
252b5132 RH |
2595 | && r == BFD_RELOC_PCREL_LO16)); |
2596 | continue; | |
2597 | ||
2598 | case 'u': | |
2599 | r = (bfd_reloc_code_real_type) va_arg (args, int); | |
2600 | assert (ep != NULL | |
2601 | && (ep->X_op == O_constant | |
2602 | || (ep->X_op == O_symbol | |
2603 | && (r == BFD_RELOC_HI16_S | |
2604 | || r == BFD_RELOC_HI16 | |
2605 | || r == BFD_RELOC_MIPS_GOT_HI16 | |
2606 | || r == BFD_RELOC_MIPS_CALL_HI16)) | |
2607 | || (ep->X_op == O_subtract | |
252b5132 RH |
2608 | && r == BFD_RELOC_PCREL_HI16_S))); |
2609 | if (ep->X_op == O_constant) | |
2610 | { | |
2611 | insn.insn_opcode |= (ep->X_add_number >> 16) & 0xffff; | |
2612 | ep = NULL; | |
2613 | r = BFD_RELOC_UNUSED; | |
2614 | } | |
2615 | continue; | |
2616 | ||
2617 | case 'p': | |
2618 | assert (ep != NULL); | |
2619 | /* | |
2620 | * This allows macro() to pass an immediate expression for | |
2621 | * creating short branches without creating a symbol. | |
2622 | * Note that the expression still might come from the assembly | |
2623 | * input, in which case the value is not checked for range nor | |
2624 | * is a relocation entry generated (yuck). | |
2625 | */ | |
2626 | if (ep->X_op == O_constant) | |
2627 | { | |
2628 | insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff; | |
2629 | ep = NULL; | |
2630 | } | |
2631 | else | |
2632 | r = BFD_RELOC_16_PCREL_S2; | |
2633 | continue; | |
2634 | ||
2635 | case 'a': | |
2636 | assert (ep != NULL); | |
2637 | r = BFD_RELOC_MIPS_JMP; | |
2638 | continue; | |
2639 | ||
2640 | case 'C': | |
2641 | insn.insn_opcode |= va_arg (args, unsigned long); | |
2642 | continue; | |
2643 | ||
2644 | default: | |
2645 | internalError (); | |
2646 | } | |
2647 | break; | |
2648 | } | |
2649 | va_end (args); | |
2650 | assert (r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); | |
2651 | ||
2652 | append_insn (place, &insn, ep, r, false); | |
2653 | } | |
2654 | ||
2655 | static void | |
2656 | mips16_macro_build (place, counter, ep, name, fmt, args) | |
2657 | char *place; | |
43841e91 | 2658 | int *counter ATTRIBUTE_UNUSED; |
252b5132 RH |
2659 | expressionS *ep; |
2660 | const char *name; | |
2661 | const char *fmt; | |
2662 | va_list args; | |
2663 | { | |
2664 | struct mips_cl_insn insn; | |
2665 | bfd_reloc_code_real_type r; | |
2666 | ||
2667 | r = BFD_RELOC_UNUSED; | |
2668 | insn.insn_mo = (struct mips_opcode *) hash_find (mips16_op_hash, name); | |
2669 | assert (insn.insn_mo); | |
2670 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
2671 | ||
2672 | while (strcmp (fmt, insn.insn_mo->args) != 0 | |
2673 | || insn.insn_mo->pinfo == INSN_MACRO) | |
2674 | { | |
2675 | ++insn.insn_mo; | |
2676 | assert (insn.insn_mo->name); | |
2677 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
2678 | } | |
2679 | ||
2680 | insn.insn_opcode = insn.insn_mo->match; | |
2681 | insn.use_extend = false; | |
2682 | ||
2683 | for (;;) | |
2684 | { | |
2685 | int c; | |
2686 | ||
2687 | c = *fmt++; | |
2688 | switch (c) | |
2689 | { | |
2690 | case '\0': | |
2691 | break; | |
2692 | ||
2693 | case ',': | |
2694 | case '(': | |
2695 | case ')': | |
2696 | continue; | |
2697 | ||
2698 | case 'y': | |
2699 | case 'w': | |
2700 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RY; | |
2701 | continue; | |
2702 | ||
2703 | case 'x': | |
2704 | case 'v': | |
2705 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RX; | |
2706 | continue; | |
2707 | ||
2708 | case 'z': | |
2709 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RZ; | |
2710 | continue; | |
2711 | ||
2712 | case 'Z': | |
2713 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_MOVE32Z; | |
2714 | continue; | |
2715 | ||
2716 | case '0': | |
2717 | case 'S': | |
2718 | case 'P': | |
2719 | case 'R': | |
2720 | continue; | |
2721 | ||
2722 | case 'X': | |
2723 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_REGR32; | |
2724 | continue; | |
2725 | ||
2726 | case 'Y': | |
2727 | { | |
2728 | int regno; | |
2729 | ||
2730 | regno = va_arg (args, int); | |
2731 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); | |
2732 | insn.insn_opcode |= regno << MIPS16OP_SH_REG32R; | |
2733 | } | |
2734 | continue; | |
2735 | ||
2736 | case '<': | |
2737 | case '>': | |
2738 | case '4': | |
2739 | case '5': | |
2740 | case 'H': | |
2741 | case 'W': | |
2742 | case 'D': | |
2743 | case 'j': | |
2744 | case '8': | |
2745 | case 'V': | |
2746 | case 'C': | |
2747 | case 'U': | |
2748 | case 'k': | |
2749 | case 'K': | |
2750 | case 'p': | |
2751 | case 'q': | |
2752 | { | |
2753 | assert (ep != NULL); | |
2754 | ||
2755 | if (ep->X_op != O_constant) | |
2756 | r = BFD_RELOC_UNUSED + c; | |
2757 | else | |
2758 | { | |
2759 | mips16_immed ((char *) NULL, 0, c, ep->X_add_number, false, | |
2760 | false, false, &insn.insn_opcode, | |
2761 | &insn.use_extend, &insn.extend); | |
2762 | ep = NULL; | |
2763 | r = BFD_RELOC_UNUSED; | |
2764 | } | |
2765 | } | |
2766 | continue; | |
2767 | ||
2768 | case '6': | |
2769 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_IMM6; | |
2770 | continue; | |
2771 | } | |
2772 | ||
2773 | break; | |
2774 | } | |
2775 | ||
2776 | assert (r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); | |
2777 | ||
2778 | append_insn (place, &insn, ep, r, false); | |
2779 | } | |
2780 | ||
2781 | /* | |
2782 | * Generate a "lui" instruction. | |
2783 | */ | |
2784 | static void | |
2785 | macro_build_lui (place, counter, ep, regnum) | |
2786 | char *place; | |
2787 | int *counter; | |
2788 | expressionS *ep; | |
2789 | int regnum; | |
2790 | { | |
2791 | expressionS high_expr; | |
2792 | struct mips_cl_insn insn; | |
2793 | bfd_reloc_code_real_type r; | |
2794 | CONST char *name = "lui"; | |
2795 | CONST char *fmt = "t,u"; | |
2796 | ||
2797 | assert (! mips_opts.mips16); | |
2798 | ||
2799 | if (place == NULL) | |
2800 | high_expr = *ep; | |
2801 | else | |
2802 | { | |
2803 | high_expr.X_op = O_constant; | |
2804 | high_expr.X_add_number = ep->X_add_number; | |
2805 | } | |
2806 | ||
2807 | if (high_expr.X_op == O_constant) | |
2808 | { | |
2809 | /* we can compute the instruction now without a relocation entry */ | |
2810 | if (high_expr.X_add_number & 0x8000) | |
2811 | high_expr.X_add_number += 0x10000; | |
2812 | high_expr.X_add_number = | |
2813 | ((unsigned long) high_expr.X_add_number >> 16) & 0xffff; | |
2814 | r = BFD_RELOC_UNUSED; | |
2815 | } | |
2816 | else | |
2817 | { | |
2818 | assert (ep->X_op == O_symbol); | |
2819 | /* _gp_disp is a special case, used from s_cpload. */ | |
2820 | assert (mips_pic == NO_PIC | |
2821 | || strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0); | |
2822 | r = BFD_RELOC_HI16_S; | |
2823 | } | |
2824 | ||
2825 | /* | |
2826 | * If the macro is about to expand into a second instruction, | |
2827 | * print a warning if needed. We need to pass ip as a parameter | |
2828 | * to generate a better warning message here... | |
2829 | */ | |
2830 | if (mips_opts.warn_about_macros && place == NULL && *counter == 1) | |
2831 | as_warn (_("Macro instruction expanded into multiple instructions")); | |
2832 | ||
2833 | if (place == NULL) | |
2834 | *counter += 1; /* bump instruction counter */ | |
2835 | ||
2836 | insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name); | |
2837 | assert (insn.insn_mo); | |
2838 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
2839 | assert (strcmp (fmt, insn.insn_mo->args) == 0); | |
2840 | ||
2841 | insn.insn_opcode = insn.insn_mo->match | (regnum << OP_SH_RT); | |
2842 | if (r == BFD_RELOC_UNUSED) | |
2843 | { | |
2844 | insn.insn_opcode |= high_expr.X_add_number; | |
2845 | append_insn (place, &insn, NULL, r, false); | |
2846 | } | |
2847 | else | |
2848 | append_insn (place, &insn, &high_expr, r, false); | |
2849 | } | |
2850 | ||
2851 | /* set_at() | |
2852 | * Generates code to set the $at register to true (one) | |
2853 | * if reg is less than the immediate expression. | |
2854 | */ | |
2855 | static void | |
2856 | set_at (counter, reg, unsignedp) | |
2857 | int *counter; | |
2858 | int reg; | |
2859 | int unsignedp; | |
2860 | { | |
2861 | if (imm_expr.X_op == O_constant | |
2862 | && imm_expr.X_add_number >= -0x8000 | |
2863 | && imm_expr.X_add_number < 0x8000) | |
2864 | macro_build ((char *) NULL, counter, &imm_expr, | |
2865 | unsignedp ? "sltiu" : "slti", | |
2866 | "t,r,j", AT, reg, (int) BFD_RELOC_LO16); | |
2867 | else | |
2868 | { | |
2869 | load_register (counter, AT, &imm_expr, 0); | |
2870 | macro_build ((char *) NULL, counter, NULL, | |
2871 | unsignedp ? "sltu" : "slt", | |
2872 | "d,v,t", AT, reg, AT); | |
2873 | } | |
2874 | } | |
2875 | ||
2876 | /* Warn if an expression is not a constant. */ | |
2877 | ||
2878 | static void | |
2879 | check_absolute_expr (ip, ex) | |
2880 | struct mips_cl_insn *ip; | |
2881 | expressionS *ex; | |
2882 | { | |
2883 | if (ex->X_op == O_big) | |
2884 | as_bad (_("unsupported large constant")); | |
2885 | else if (ex->X_op != O_constant) | |
2886 | as_bad (_("Instruction %s requires absolute expression"), ip->insn_mo->name); | |
2887 | } | |
2888 | ||
2889 | /* Count the leading zeroes by performing a binary chop. This is a | |
2890 | bulky bit of source, but performance is a LOT better for the | |
2891 | majority of values than a simple loop to count the bits: | |
2892 | for (lcnt = 0; (lcnt < 32); lcnt++) | |
2893 | if ((v) & (1 << (31 - lcnt))) | |
2894 | break; | |
2895 | However it is not code size friendly, and the gain will drop a bit | |
2896 | on certain cached systems. | |
2897 | */ | |
2898 | #define COUNT_TOP_ZEROES(v) \ | |
2899 | (((v) & ~0xffff) == 0 \ | |
2900 | ? ((v) & ~0xff) == 0 \ | |
2901 | ? ((v) & ~0xf) == 0 \ | |
2902 | ? ((v) & ~0x3) == 0 \ | |
2903 | ? ((v) & ~0x1) == 0 \ | |
2904 | ? !(v) \ | |
2905 | ? 32 \ | |
2906 | : 31 \ | |
2907 | : 30 \ | |
2908 | : ((v) & ~0x7) == 0 \ | |
2909 | ? 29 \ | |
2910 | : 28 \ | |
2911 | : ((v) & ~0x3f) == 0 \ | |
2912 | ? ((v) & ~0x1f) == 0 \ | |
2913 | ? 27 \ | |
2914 | : 26 \ | |
2915 | : ((v) & ~0x7f) == 0 \ | |
2916 | ? 25 \ | |
2917 | : 24 \ | |
2918 | : ((v) & ~0xfff) == 0 \ | |
2919 | ? ((v) & ~0x3ff) == 0 \ | |
2920 | ? ((v) & ~0x1ff) == 0 \ | |
2921 | ? 23 \ | |
2922 | : 22 \ | |
2923 | : ((v) & ~0x7ff) == 0 \ | |
2924 | ? 21 \ | |
2925 | : 20 \ | |
2926 | : ((v) & ~0x3fff) == 0 \ | |
2927 | ? ((v) & ~0x1fff) == 0 \ | |
2928 | ? 19 \ | |
2929 | : 18 \ | |
2930 | : ((v) & ~0x7fff) == 0 \ | |
2931 | ? 17 \ | |
2932 | : 16 \ | |
2933 | : ((v) & ~0xffffff) == 0 \ | |
2934 | ? ((v) & ~0xfffff) == 0 \ | |
2935 | ? ((v) & ~0x3ffff) == 0 \ | |
2936 | ? ((v) & ~0x1ffff) == 0 \ | |
2937 | ? 15 \ | |
2938 | : 14 \ | |
2939 | : ((v) & ~0x7ffff) == 0 \ | |
2940 | ? 13 \ | |
2941 | : 12 \ | |
2942 | : ((v) & ~0x3fffff) == 0 \ | |
2943 | ? ((v) & ~0x1fffff) == 0 \ | |
2944 | ? 11 \ | |
2945 | : 10 \ | |
2946 | : ((v) & ~0x7fffff) == 0 \ | |
2947 | ? 9 \ | |
2948 | : 8 \ | |
2949 | : ((v) & ~0xfffffff) == 0 \ | |
2950 | ? ((v) & ~0x3ffffff) == 0 \ | |
2951 | ? ((v) & ~0x1ffffff) == 0 \ | |
2952 | ? 7 \ | |
2953 | : 6 \ | |
2954 | : ((v) & ~0x7ffffff) == 0 \ | |
2955 | ? 5 \ | |
2956 | : 4 \ | |
2957 | : ((v) & ~0x3fffffff) == 0 \ | |
2958 | ? ((v) & ~0x1fffffff) == 0 \ | |
2959 | ? 3 \ | |
2960 | : 2 \ | |
2961 | : ((v) & ~0x7fffffff) == 0 \ | |
2962 | ? 1 \ | |
2963 | : 0) | |
2964 | ||
2965 | /* load_register() | |
2966 | * This routine generates the least number of instructions neccessary to load | |
2967 | * an absolute expression value into a register. | |
2968 | */ | |
2969 | static void | |
2970 | load_register (counter, reg, ep, dbl) | |
2971 | int *counter; | |
2972 | int reg; | |
2973 | expressionS *ep; | |
2974 | int dbl; | |
2975 | { | |
2976 | int freg; | |
2977 | expressionS hi32, lo32; | |
2978 | ||
2979 | if (ep->X_op != O_big) | |
2980 | { | |
2981 | assert (ep->X_op == O_constant); | |
2982 | if (ep->X_add_number < 0x8000 | |
2983 | && (ep->X_add_number >= 0 | |
2984 | || (ep->X_add_number >= -0x8000 | |
2985 | && (! dbl | |
2986 | || ! ep->X_unsigned | |
2987 | || sizeof (ep->X_add_number) > 4)))) | |
2988 | { | |
2989 | /* We can handle 16 bit signed values with an addiu to | |
2990 | $zero. No need to ever use daddiu here, since $zero and | |
2991 | the result are always correct in 32 bit mode. */ | |
2992 | macro_build ((char *) NULL, counter, ep, "addiu", "t,r,j", reg, 0, | |
2993 | (int) BFD_RELOC_LO16); | |
2994 | return; | |
2995 | } | |
2996 | else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000) | |
2997 | { | |
2998 | /* We can handle 16 bit unsigned values with an ori to | |
2999 | $zero. */ | |
3000 | macro_build ((char *) NULL, counter, ep, "ori", "t,r,i", reg, 0, | |
3001 | (int) BFD_RELOC_LO16); | |
3002 | return; | |
3003 | } | |
3004 | else if ((((ep->X_add_number &~ (offsetT) 0x7fffffff) == 0 | |
3005 | || ((ep->X_add_number &~ (offsetT) 0x7fffffff) | |
3006 | == ~ (offsetT) 0x7fffffff)) | |
3007 | && (! dbl | |
3008 | || ! ep->X_unsigned | |
3009 | || sizeof (ep->X_add_number) > 4 | |
3010 | || (ep->X_add_number & 0x80000000) == 0)) | |
9ce8a5dd | 3011 | || ((! ISA_HAS_64BIT_REGS (mips_opts.isa) || ! dbl) |
252b5132 | 3012 | && (ep->X_add_number &~ (offsetT) 0xffffffff) == 0) |
9ce8a5dd | 3013 | || (! ISA_HAS_64BIT_REGS (mips_opts.isa) |
252b5132 RH |
3014 | && ! dbl |
3015 | && ((ep->X_add_number &~ (offsetT) 0xffffffff) | |
3016 | == ~ (offsetT) 0xffffffff))) | |
3017 | { | |
3018 | /* 32 bit values require an lui. */ | |
3019 | macro_build ((char *) NULL, counter, ep, "lui", "t,u", reg, | |
3020 | (int) BFD_RELOC_HI16); | |
3021 | if ((ep->X_add_number & 0xffff) != 0) | |
3022 | macro_build ((char *) NULL, counter, ep, "ori", "t,r,i", reg, reg, | |
3023 | (int) BFD_RELOC_LO16); | |
3024 | return; | |
3025 | } | |
3026 | } | |
3027 | ||
3028 | /* The value is larger than 32 bits. */ | |
3029 | ||
9ce8a5dd | 3030 | if (! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
3031 | { |
3032 | as_bad (_("Number larger than 32 bits")); | |
3033 | macro_build ((char *) NULL, counter, ep, "addiu", "t,r,j", reg, 0, | |
3034 | (int) BFD_RELOC_LO16); | |
3035 | return; | |
3036 | } | |
3037 | ||
3038 | if (ep->X_op != O_big) | |
3039 | { | |
3040 | hi32 = *ep; | |
3041 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
3042 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
3043 | hi32.X_add_number &= 0xffffffff; | |
3044 | lo32 = *ep; | |
3045 | lo32.X_add_number &= 0xffffffff; | |
3046 | } | |
3047 | else | |
3048 | { | |
3049 | assert (ep->X_add_number > 2); | |
3050 | if (ep->X_add_number == 3) | |
3051 | generic_bignum[3] = 0; | |
3052 | else if (ep->X_add_number > 4) | |
3053 | as_bad (_("Number larger than 64 bits")); | |
3054 | lo32.X_op = O_constant; | |
3055 | lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16); | |
3056 | hi32.X_op = O_constant; | |
3057 | hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16); | |
3058 | } | |
3059 | ||
3060 | if (hi32.X_add_number == 0) | |
3061 | freg = 0; | |
3062 | else | |
3063 | { | |
3064 | int shift, bit; | |
3065 | unsigned long hi, lo; | |
3066 | ||
3067 | if (hi32.X_add_number == 0xffffffff) | |
beae10d5 KH |
3068 | { |
3069 | if ((lo32.X_add_number & 0xffff8000) == 0xffff8000) | |
3070 | { | |
3071 | macro_build ((char *) NULL, counter, &lo32, "addiu", "t,r,j", | |
252b5132 | 3072 | reg, 0, (int) BFD_RELOC_LO16); |
beae10d5 KH |
3073 | return; |
3074 | } | |
3075 | if (lo32.X_add_number & 0x80000000) | |
3076 | { | |
3077 | macro_build ((char *) NULL, counter, &lo32, "lui", "t,u", reg, | |
3078 | (int) BFD_RELOC_HI16); | |
252b5132 RH |
3079 | if (lo32.X_add_number & 0xffff) |
3080 | macro_build ((char *) NULL, counter, &lo32, "ori", "t,r,i", | |
3081 | reg, reg, (int) BFD_RELOC_LO16); | |
beae10d5 KH |
3082 | return; |
3083 | } | |
3084 | } | |
252b5132 RH |
3085 | |
3086 | /* Check for 16bit shifted constant. We know that hi32 is | |
3087 | non-zero, so start the mask on the first bit of the hi32 | |
3088 | value. */ | |
3089 | shift = 17; | |
3090 | do | |
beae10d5 KH |
3091 | { |
3092 | unsigned long himask, lomask; | |
3093 | ||
3094 | if (shift < 32) | |
3095 | { | |
3096 | himask = 0xffff >> (32 - shift); | |
3097 | lomask = (0xffff << shift) & 0xffffffff; | |
3098 | } | |
3099 | else | |
3100 | { | |
3101 | himask = 0xffff << (shift - 32); | |
3102 | lomask = 0; | |
3103 | } | |
3104 | if ((hi32.X_add_number & ~(offsetT) himask) == 0 | |
3105 | && (lo32.X_add_number & ~(offsetT) lomask) == 0) | |
3106 | { | |
3107 | expressionS tmp; | |
3108 | ||
3109 | tmp.X_op = O_constant; | |
3110 | if (shift < 32) | |
3111 | tmp.X_add_number = ((hi32.X_add_number << (32 - shift)) | |
3112 | | (lo32.X_add_number >> shift)); | |
3113 | else | |
3114 | tmp.X_add_number = hi32.X_add_number >> (shift - 32); | |
3115 | macro_build ((char *) NULL, counter, &tmp, | |
3116 | "ori", "t,r,i", reg, 0, | |
3117 | (int) BFD_RELOC_LO16); | |
3118 | macro_build ((char *) NULL, counter, NULL, | |
3119 | (shift >= 32) ? "dsll32" : "dsll", | |
3120 | "d,w,<", reg, reg, | |
3121 | (shift >= 32) ? shift - 32 : shift); | |
3122 | return; | |
3123 | } | |
3124 | shift++; | |
3125 | } | |
3126 | while (shift <= (64 - 16)); | |
252b5132 RH |
3127 | |
3128 | /* Find the bit number of the lowest one bit, and store the | |
3129 | shifted value in hi/lo. */ | |
3130 | hi = (unsigned long) (hi32.X_add_number & 0xffffffff); | |
3131 | lo = (unsigned long) (lo32.X_add_number & 0xffffffff); | |
3132 | if (lo != 0) | |
3133 | { | |
3134 | bit = 0; | |
3135 | while ((lo & 1) == 0) | |
3136 | { | |
3137 | lo >>= 1; | |
3138 | ++bit; | |
3139 | } | |
3140 | lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit); | |
3141 | hi >>= bit; | |
3142 | } | |
3143 | else | |
3144 | { | |
3145 | bit = 32; | |
3146 | while ((hi & 1) == 0) | |
3147 | { | |
3148 | hi >>= 1; | |
3149 | ++bit; | |
3150 | } | |
3151 | lo = hi; | |
3152 | hi = 0; | |
3153 | } | |
3154 | ||
3155 | /* Optimize if the shifted value is a (power of 2) - 1. */ | |
3156 | if ((hi == 0 && ((lo + 1) & lo) == 0) | |
3157 | || (lo == 0xffffffff && ((hi + 1) & hi) == 0)) | |
beae10d5 KH |
3158 | { |
3159 | shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number); | |
252b5132 | 3160 | if (shift != 0) |
beae10d5 | 3161 | { |
252b5132 RH |
3162 | expressionS tmp; |
3163 | ||
3164 | /* This instruction will set the register to be all | |
3165 | ones. */ | |
beae10d5 KH |
3166 | tmp.X_op = O_constant; |
3167 | tmp.X_add_number = (offsetT) -1; | |
3168 | macro_build ((char *) NULL, counter, &tmp, "addiu", "t,r,j", | |
252b5132 | 3169 | reg, 0, (int) BFD_RELOC_LO16); |
beae10d5 KH |
3170 | if (bit != 0) |
3171 | { | |
3172 | bit += shift; | |
3173 | macro_build ((char *) NULL, counter, NULL, | |
3174 | (bit >= 32) ? "dsll32" : "dsll", | |
3175 | "d,w,<", reg, reg, | |
3176 | (bit >= 32) ? bit - 32 : bit); | |
3177 | } | |
3178 | macro_build ((char *) NULL, counter, NULL, | |
252b5132 | 3179 | (shift >= 32) ? "dsrl32" : "dsrl", |
beae10d5 | 3180 | "d,w,<", reg, reg, |
252b5132 | 3181 | (shift >= 32) ? shift - 32 : shift); |
beae10d5 KH |
3182 | return; |
3183 | } | |
3184 | } | |
252b5132 RH |
3185 | |
3186 | /* Sign extend hi32 before calling load_register, because we can | |
3187 | generally get better code when we load a sign extended value. */ | |
3188 | if ((hi32.X_add_number & 0x80000000) != 0) | |
beae10d5 | 3189 | hi32.X_add_number |= ~(offsetT) 0xffffffff; |
252b5132 RH |
3190 | load_register (counter, reg, &hi32, 0); |
3191 | freg = reg; | |
3192 | } | |
3193 | if ((lo32.X_add_number & 0xffff0000) == 0) | |
3194 | { | |
3195 | if (freg != 0) | |
3196 | { | |
3197 | macro_build ((char *) NULL, counter, NULL, "dsll32", "d,w,<", reg, | |
3198 | freg, 0); | |
3199 | freg = reg; | |
3200 | } | |
3201 | } | |
3202 | else | |
3203 | { | |
3204 | expressionS mid16; | |
3205 | ||
3206 | if ((freg == 0) && (lo32.X_add_number == 0xffffffff)) | |
beae10d5 | 3207 | { |
252b5132 RH |
3208 | macro_build ((char *) NULL, counter, &lo32, "lui", "t,u", reg, |
3209 | (int) BFD_RELOC_HI16); | |
beae10d5 KH |
3210 | macro_build ((char *) NULL, counter, NULL, "dsrl32", "d,w,<", reg, |
3211 | reg, 0); | |
3212 | return; | |
3213 | } | |
252b5132 RH |
3214 | |
3215 | if (freg != 0) | |
3216 | { | |
3217 | macro_build ((char *) NULL, counter, NULL, "dsll", "d,w,<", reg, | |
3218 | freg, 16); | |
3219 | freg = reg; | |
3220 | } | |
3221 | mid16 = lo32; | |
3222 | mid16.X_add_number >>= 16; | |
3223 | macro_build ((char *) NULL, counter, &mid16, "ori", "t,r,i", reg, | |
3224 | freg, (int) BFD_RELOC_LO16); | |
3225 | macro_build ((char *) NULL, counter, NULL, "dsll", "d,w,<", reg, | |
3226 | reg, 16); | |
3227 | freg = reg; | |
3228 | } | |
3229 | if ((lo32.X_add_number & 0xffff) != 0) | |
3230 | macro_build ((char *) NULL, counter, &lo32, "ori", "t,r,i", reg, freg, | |
3231 | (int) BFD_RELOC_LO16); | |
3232 | } | |
3233 | ||
3234 | /* Load an address into a register. */ | |
3235 | ||
3236 | static void | |
3237 | load_address (counter, reg, ep) | |
3238 | int *counter; | |
3239 | int reg; | |
3240 | expressionS *ep; | |
3241 | { | |
3242 | char *p; | |
3243 | ||
3244 | if (ep->X_op != O_constant | |
3245 | && ep->X_op != O_symbol) | |
3246 | { | |
3247 | as_bad (_("expression too complex")); | |
3248 | ep->X_op = O_constant; | |
3249 | } | |
3250 | ||
3251 | if (ep->X_op == O_constant) | |
3252 | { | |
3253 | load_register (counter, reg, ep, 0); | |
3254 | return; | |
3255 | } | |
3256 | ||
3257 | if (mips_pic == NO_PIC) | |
3258 | { | |
3259 | /* If this is a reference to a GP relative symbol, we want | |
3260 | addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL) | |
3261 | Otherwise we want | |
3262 | lui $reg,<sym> (BFD_RELOC_HI16_S) | |
3263 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
3264 | If we have an addend, we always use the latter form. */ | |
3265 | if ((valueT) ep->X_add_number >= MAX_GPREL_OFFSET | |
beae10d5 | 3266 | || nopic_need_relax (ep->X_add_symbol, 1)) |
252b5132 RH |
3267 | p = NULL; |
3268 | else | |
3269 | { | |
3270 | frag_grow (20); | |
3271 | macro_build ((char *) NULL, counter, ep, | |
3272 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 3273 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
3274 | ? "addiu" : "daddiu"), |
3275 | "t,r,j", reg, GP, (int) BFD_RELOC_MIPS_GPREL); | |
3276 | p = frag_var (rs_machine_dependent, 8, 0, | |
3277 | RELAX_ENCODE (4, 8, 0, 4, 0, | |
3278 | mips_opts.warn_about_macros), | |
3279 | ep->X_add_symbol, (offsetT) 0, (char *) NULL); | |
3280 | } | |
3281 | macro_build_lui (p, counter, ep, reg); | |
3282 | if (p != NULL) | |
3283 | p += 4; | |
3284 | macro_build (p, counter, ep, | |
3285 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 3286 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
3287 | ? "addiu" : "daddiu"), |
3288 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); | |
3289 | } | |
3290 | else if (mips_pic == SVR4_PIC && ! mips_big_got) | |
3291 | { | |
3292 | expressionS ex; | |
3293 | ||
3294 | /* If this is a reference to an external symbol, we want | |
3295 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3296 | Otherwise we want | |
3297 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3298 | nop | |
3299 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
3300 | If there is a constant, it must be added in after. */ | |
3301 | ex.X_add_number = ep->X_add_number; | |
3302 | ep->X_add_number = 0; | |
3303 | frag_grow (20); | |
3304 | macro_build ((char *) NULL, counter, ep, | |
3305 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 3306 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
3307 | ? "lw" : "ld"), |
3308 | "t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT16, GP); | |
3309 | macro_build ((char *) NULL, counter, (expressionS *) NULL, "nop", ""); | |
3310 | p = frag_var (rs_machine_dependent, 4, 0, | |
3311 | RELAX_ENCODE (0, 4, -8, 0, 0, mips_opts.warn_about_macros), | |
3312 | ep->X_add_symbol, (offsetT) 0, (char *) NULL); | |
3313 | macro_build (p, counter, ep, | |
3314 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 3315 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
3316 | ? "addiu" : "daddiu"), |
3317 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); | |
3318 | if (ex.X_add_number != 0) | |
3319 | { | |
3320 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
3321 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
3322 | ex.X_op = O_constant; | |
3323 | macro_build ((char *) NULL, counter, &ex, | |
3324 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 3325 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
3326 | ? "addiu" : "daddiu"), |
3327 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); | |
3328 | } | |
3329 | } | |
3330 | else if (mips_pic == SVR4_PIC) | |
3331 | { | |
3332 | expressionS ex; | |
3333 | int off; | |
3334 | ||
3335 | /* This is the large GOT case. If this is a reference to an | |
3336 | external symbol, we want | |
3337 | lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
3338 | addu $reg,$reg,$gp | |
3339 | lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16) | |
3340 | Otherwise, for a reference to a local symbol, we want | |
3341 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3342 | nop | |
3343 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
3344 | If there is a constant, it must be added in after. */ | |
3345 | ex.X_add_number = ep->X_add_number; | |
3346 | ep->X_add_number = 0; | |
3347 | if (reg_needs_delay (GP)) | |
3348 | off = 4; | |
3349 | else | |
3350 | off = 0; | |
3351 | frag_grow (32); | |
3352 | macro_build ((char *) NULL, counter, ep, "lui", "t,u", reg, | |
3353 | (int) BFD_RELOC_MIPS_GOT_HI16); | |
3354 | macro_build ((char *) NULL, counter, (expressionS *) NULL, | |
3355 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 3356 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
3357 | ? "addu" : "daddu"), |
3358 | "d,v,t", reg, reg, GP); | |
3359 | macro_build ((char *) NULL, counter, ep, | |
3360 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 3361 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
3362 | ? "lw" : "ld"), |
3363 | "t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT_LO16, reg); | |
3364 | p = frag_var (rs_machine_dependent, 12 + off, 0, | |
3365 | RELAX_ENCODE (12, 12 + off, off, 8 + off, 0, | |
3366 | mips_opts.warn_about_macros), | |
3367 | ep->X_add_symbol, (offsetT) 0, (char *) NULL); | |
3368 | if (off > 0) | |
3369 | { | |
3370 | /* We need a nop before loading from $gp. This special | |
3371 | check is required because the lui which starts the main | |
3372 | instruction stream does not refer to $gp, and so will not | |
3373 | insert the nop which may be required. */ | |
3374 | macro_build (p, counter, (expressionS *) NULL, "nop", ""); | |
3375 | p += 4; | |
3376 | } | |
3377 | macro_build (p, counter, ep, | |
3378 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 3379 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
3380 | ? "lw" : "ld"), |
3381 | "t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT16, GP); | |
3382 | p += 4; | |
3383 | macro_build (p, counter, (expressionS *) NULL, "nop", ""); | |
3384 | p += 4; | |
3385 | macro_build (p, counter, ep, | |
3386 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 3387 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
3388 | ? "addiu" : "daddiu"), |
3389 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); | |
3390 | if (ex.X_add_number != 0) | |
3391 | { | |
3392 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
3393 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
3394 | ex.X_op = O_constant; | |
3395 | macro_build ((char *) NULL, counter, &ex, | |
3396 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 3397 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
3398 | ? "addiu" : "daddiu"), |
3399 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); | |
3400 | } | |
3401 | } | |
3402 | else if (mips_pic == EMBEDDED_PIC) | |
3403 | { | |
3404 | /* We always do | |
3405 | addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL) | |
3406 | */ | |
3407 | macro_build ((char *) NULL, counter, ep, | |
3408 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 3409 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
3410 | ? "addiu" : "daddiu"), |
3411 | "t,r,j", reg, GP, (int) BFD_RELOC_MIPS_GPREL); | |
3412 | } | |
3413 | else | |
3414 | abort (); | |
3415 | } | |
3416 | ||
3417 | /* | |
3418 | * Build macros | |
3419 | * This routine implements the seemingly endless macro or synthesized | |
3420 | * instructions and addressing modes in the mips assembly language. Many | |
3421 | * of these macros are simple and are similar to each other. These could | |
3422 | * probably be handled by some kind of table or grammer aproach instead of | |
3423 | * this verbose method. Others are not simple macros but are more like | |
3424 | * optimizing code generation. | |
3425 | * One interesting optimization is when several store macros appear | |
3426 | * consecutivly that would load AT with the upper half of the same address. | |
3427 | * The ensuing load upper instructions are ommited. This implies some kind | |
3428 | * of global optimization. We currently only optimize within a single macro. | |
3429 | * For many of the load and store macros if the address is specified as a | |
3430 | * constant expression in the first 64k of memory (ie ld $2,0x4000c) we | |
3431 | * first load register 'at' with zero and use it as the base register. The | |
3432 | * mips assembler simply uses register $zero. Just one tiny optimization | |
3433 | * we're missing. | |
3434 | */ | |
3435 | static void | |
3436 | macro (ip) | |
3437 | struct mips_cl_insn *ip; | |
3438 | { | |
3439 | register int treg, sreg, dreg, breg; | |
3440 | int tempreg; | |
3441 | int mask; | |
3442 | int icnt = 0; | |
43841e91 | 3443 | int used_at = 0; |
252b5132 RH |
3444 | expressionS expr1; |
3445 | const char *s; | |
3446 | const char *s2; | |
3447 | const char *fmt; | |
3448 | int likely = 0; | |
3449 | int dbl = 0; | |
3450 | int coproc = 0; | |
3451 | int lr = 0; | |
3452 | int imm = 0; | |
3453 | offsetT maxnum; | |
3454 | int off; | |
3455 | bfd_reloc_code_real_type r; | |
3456 | char *p; | |
3457 | int hold_mips_optimize; | |
3458 | ||
3459 | assert (! mips_opts.mips16); | |
3460 | ||
3461 | treg = (ip->insn_opcode >> 16) & 0x1f; | |
3462 | dreg = (ip->insn_opcode >> 11) & 0x1f; | |
3463 | sreg = breg = (ip->insn_opcode >> 21) & 0x1f; | |
3464 | mask = ip->insn_mo->mask; | |
3465 | ||
3466 | expr1.X_op = O_constant; | |
3467 | expr1.X_op_symbol = NULL; | |
3468 | expr1.X_add_symbol = NULL; | |
3469 | expr1.X_add_number = 1; | |
3470 | ||
3471 | switch (mask) | |
3472 | { | |
3473 | case M_DABS: | |
3474 | dbl = 1; | |
3475 | case M_ABS: | |
3476 | /* bgez $a0,.+12 | |
3477 | move v0,$a0 | |
3478 | sub v0,$zero,$a0 | |
3479 | */ | |
3480 | ||
3481 | mips_emit_delays (true); | |
3482 | ++mips_opts.noreorder; | |
3483 | mips_any_noreorder = 1; | |
3484 | ||
3485 | expr1.X_add_number = 8; | |
3486 | macro_build ((char *) NULL, &icnt, &expr1, "bgez", "s,p", sreg); | |
3487 | if (dreg == sreg) | |
3488 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); | |
3489 | else | |
3490 | macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, sreg, 0); | |
3491 | macro_build ((char *) NULL, &icnt, NULL, | |
3492 | dbl ? "dsub" : "sub", | |
3493 | "d,v,t", dreg, 0, sreg); | |
3494 | ||
3495 | --mips_opts.noreorder; | |
3496 | return; | |
3497 | ||
3498 | case M_ADD_I: | |
3499 | s = "addi"; | |
3500 | s2 = "add"; | |
3501 | goto do_addi; | |
3502 | case M_ADDU_I: | |
3503 | s = "addiu"; | |
3504 | s2 = "addu"; | |
3505 | goto do_addi; | |
3506 | case M_DADD_I: | |
3507 | dbl = 1; | |
3508 | s = "daddi"; | |
3509 | s2 = "dadd"; | |
3510 | goto do_addi; | |
3511 | case M_DADDU_I: | |
3512 | dbl = 1; | |
3513 | s = "daddiu"; | |
3514 | s2 = "daddu"; | |
3515 | do_addi: | |
3516 | if (imm_expr.X_op == O_constant | |
3517 | && imm_expr.X_add_number >= -0x8000 | |
3518 | && imm_expr.X_add_number < 0x8000) | |
3519 | { | |
3520 | macro_build ((char *) NULL, &icnt, &imm_expr, s, "t,r,j", treg, sreg, | |
3521 | (int) BFD_RELOC_LO16); | |
3522 | return; | |
3523 | } | |
3524 | load_register (&icnt, AT, &imm_expr, dbl); | |
3525 | macro_build ((char *) NULL, &icnt, NULL, s2, "d,v,t", treg, sreg, AT); | |
3526 | break; | |
3527 | ||
3528 | case M_AND_I: | |
3529 | s = "andi"; | |
3530 | s2 = "and"; | |
3531 | goto do_bit; | |
3532 | case M_OR_I: | |
3533 | s = "ori"; | |
3534 | s2 = "or"; | |
3535 | goto do_bit; | |
3536 | case M_NOR_I: | |
3537 | s = ""; | |
3538 | s2 = "nor"; | |
3539 | goto do_bit; | |
3540 | case M_XOR_I: | |
3541 | s = "xori"; | |
3542 | s2 = "xor"; | |
3543 | do_bit: | |
3544 | if (imm_expr.X_op == O_constant | |
3545 | && imm_expr.X_add_number >= 0 | |
3546 | && imm_expr.X_add_number < 0x10000) | |
3547 | { | |
3548 | if (mask != M_NOR_I) | |
3549 | macro_build ((char *) NULL, &icnt, &imm_expr, s, "t,r,i", treg, | |
3550 | sreg, (int) BFD_RELOC_LO16); | |
3551 | else | |
3552 | { | |
3553 | macro_build ((char *) NULL, &icnt, &imm_expr, "ori", "t,r,i", | |
3554 | treg, sreg, (int) BFD_RELOC_LO16); | |
3555 | macro_build ((char *) NULL, &icnt, NULL, "nor", "d,v,t", | |
3556 | treg, treg, 0); | |
3557 | } | |
3558 | return; | |
3559 | } | |
3560 | ||
3561 | load_register (&icnt, AT, &imm_expr, 0); | |
3562 | macro_build ((char *) NULL, &icnt, NULL, s2, "d,v,t", treg, sreg, AT); | |
3563 | break; | |
3564 | ||
3565 | case M_BEQ_I: | |
3566 | s = "beq"; | |
3567 | goto beq_i; | |
3568 | case M_BEQL_I: | |
3569 | s = "beql"; | |
3570 | likely = 1; | |
3571 | goto beq_i; | |
3572 | case M_BNE_I: | |
3573 | s = "bne"; | |
3574 | goto beq_i; | |
3575 | case M_BNEL_I: | |
3576 | s = "bnel"; | |
3577 | likely = 1; | |
3578 | beq_i: | |
3579 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
3580 | { | |
3581 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "s,t,p", sreg, | |
3582 | 0); | |
3583 | return; | |
3584 | } | |
3585 | load_register (&icnt, AT, &imm_expr, 0); | |
3586 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "s,t,p", sreg, AT); | |
3587 | break; | |
3588 | ||
3589 | case M_BGEL: | |
3590 | likely = 1; | |
3591 | case M_BGE: | |
3592 | if (treg == 0) | |
3593 | { | |
3594 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3595 | likely ? "bgezl" : "bgez", | |
3596 | "s,p", sreg); | |
3597 | return; | |
3598 | } | |
3599 | if (sreg == 0) | |
3600 | { | |
3601 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3602 | likely ? "blezl" : "blez", | |
3603 | "s,p", treg); | |
3604 | return; | |
3605 | } | |
3606 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", AT, sreg, treg); | |
3607 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3608 | likely ? "beql" : "beq", | |
3609 | "s,t,p", AT, 0); | |
3610 | break; | |
3611 | ||
3612 | case M_BGTL_I: | |
3613 | likely = 1; | |
3614 | case M_BGT_I: | |
3615 | /* check for > max integer */ | |
3616 | maxnum = 0x7fffffff; | |
9ce8a5dd | 3617 | if (ISA_HAS_64BIT_REGS (mips_opts.isa) && sizeof (maxnum) > 4) |
252b5132 RH |
3618 | { |
3619 | maxnum <<= 16; | |
3620 | maxnum |= 0xffff; | |
3621 | maxnum <<= 16; | |
3622 | maxnum |= 0xffff; | |
3623 | } | |
3624 | if (imm_expr.X_op == O_constant | |
3625 | && imm_expr.X_add_number >= maxnum | |
9ce8a5dd | 3626 | && (! ISA_HAS_64BIT_REGS (mips_opts.isa) || sizeof (maxnum) > 4)) |
252b5132 RH |
3627 | { |
3628 | do_false: | |
3629 | /* result is always false */ | |
3630 | if (! likely) | |
3631 | { | |
39c0a331 L |
3632 | if (warn_nops) |
3633 | as_warn (_("Branch %s is always false (nop)"), | |
3634 | ip->insn_mo->name); | |
252b5132 RH |
3635 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); |
3636 | } | |
3637 | else | |
3638 | { | |
39c0a331 L |
3639 | if (warn_nops) |
3640 | as_warn (_("Branch likely %s is always false"), | |
3641 | ip->insn_mo->name); | |
252b5132 RH |
3642 | macro_build ((char *) NULL, &icnt, &offset_expr, "bnel", |
3643 | "s,t,p", 0, 0); | |
3644 | } | |
3645 | return; | |
3646 | } | |
3647 | if (imm_expr.X_op != O_constant) | |
3648 | as_bad (_("Unsupported large constant")); | |
3649 | imm_expr.X_add_number++; | |
3650 | /* FALLTHROUGH */ | |
3651 | case M_BGE_I: | |
3652 | case M_BGEL_I: | |
3653 | if (mask == M_BGEL_I) | |
3654 | likely = 1; | |
3655 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
3656 | { | |
3657 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3658 | likely ? "bgezl" : "bgez", | |
3659 | "s,p", sreg); | |
3660 | return; | |
3661 | } | |
3662 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
3663 | { | |
3664 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3665 | likely ? "bgtzl" : "bgtz", | |
3666 | "s,p", sreg); | |
3667 | return; | |
3668 | } | |
3669 | maxnum = 0x7fffffff; | |
9ce8a5dd | 3670 | if (ISA_HAS_64BIT_REGS (mips_opts.isa) && sizeof (maxnum) > 4) |
252b5132 RH |
3671 | { |
3672 | maxnum <<= 16; | |
3673 | maxnum |= 0xffff; | |
3674 | maxnum <<= 16; | |
3675 | maxnum |= 0xffff; | |
3676 | } | |
3677 | maxnum = - maxnum - 1; | |
3678 | if (imm_expr.X_op == O_constant | |
3679 | && imm_expr.X_add_number <= maxnum | |
9ce8a5dd | 3680 | && (! ISA_HAS_64BIT_REGS (mips_opts.isa) || sizeof (maxnum) > 4)) |
252b5132 RH |
3681 | { |
3682 | do_true: | |
3683 | /* result is always true */ | |
3684 | as_warn (_("Branch %s is always true"), ip->insn_mo->name); | |
3685 | macro_build ((char *) NULL, &icnt, &offset_expr, "b", "p"); | |
3686 | return; | |
3687 | } | |
3688 | set_at (&icnt, sreg, 0); | |
3689 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3690 | likely ? "beql" : "beq", | |
3691 | "s,t,p", AT, 0); | |
3692 | break; | |
3693 | ||
3694 | case M_BGEUL: | |
3695 | likely = 1; | |
3696 | case M_BGEU: | |
3697 | if (treg == 0) | |
3698 | goto do_true; | |
3699 | if (sreg == 0) | |
3700 | { | |
3701 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3702 | likely ? "beql" : "beq", | |
3703 | "s,t,p", 0, treg); | |
3704 | return; | |
3705 | } | |
3706 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", AT, sreg, | |
3707 | treg); | |
3708 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3709 | likely ? "beql" : "beq", | |
3710 | "s,t,p", AT, 0); | |
3711 | break; | |
3712 | ||
3713 | case M_BGTUL_I: | |
3714 | likely = 1; | |
3715 | case M_BGTU_I: | |
3716 | if (sreg == 0 | |
9ce8a5dd | 3717 | || (! ISA_HAS_64BIT_REGS (mips_opts.isa) |
252b5132 RH |
3718 | && imm_expr.X_op == O_constant |
3719 | && imm_expr.X_add_number == 0xffffffff)) | |
3720 | goto do_false; | |
3721 | if (imm_expr.X_op != O_constant) | |
3722 | as_bad (_("Unsupported large constant")); | |
3723 | imm_expr.X_add_number++; | |
3724 | /* FALLTHROUGH */ | |
3725 | case M_BGEU_I: | |
3726 | case M_BGEUL_I: | |
3727 | if (mask == M_BGEUL_I) | |
3728 | likely = 1; | |
3729 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
3730 | goto do_true; | |
3731 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
3732 | { | |
3733 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3734 | likely ? "bnel" : "bne", | |
3735 | "s,t,p", sreg, 0); | |
3736 | return; | |
3737 | } | |
3738 | set_at (&icnt, sreg, 1); | |
3739 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3740 | likely ? "beql" : "beq", | |
3741 | "s,t,p", AT, 0); | |
3742 | break; | |
3743 | ||
3744 | case M_BGTL: | |
3745 | likely = 1; | |
3746 | case M_BGT: | |
3747 | if (treg == 0) | |
3748 | { | |
3749 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3750 | likely ? "bgtzl" : "bgtz", | |
3751 | "s,p", sreg); | |
3752 | return; | |
3753 | } | |
3754 | if (sreg == 0) | |
3755 | { | |
3756 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3757 | likely ? "bltzl" : "bltz", | |
3758 | "s,p", treg); | |
3759 | return; | |
3760 | } | |
3761 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", AT, treg, sreg); | |
3762 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3763 | likely ? "bnel" : "bne", | |
3764 | "s,t,p", AT, 0); | |
3765 | break; | |
3766 | ||
3767 | case M_BGTUL: | |
3768 | likely = 1; | |
3769 | case M_BGTU: | |
3770 | if (treg == 0) | |
3771 | { | |
3772 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3773 | likely ? "bnel" : "bne", | |
3774 | "s,t,p", sreg, 0); | |
3775 | return; | |
3776 | } | |
3777 | if (sreg == 0) | |
3778 | goto do_false; | |
3779 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", AT, treg, | |
3780 | sreg); | |
3781 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3782 | likely ? "bnel" : "bne", | |
3783 | "s,t,p", AT, 0); | |
3784 | break; | |
3785 | ||
3786 | case M_BLEL: | |
3787 | likely = 1; | |
3788 | case M_BLE: | |
3789 | if (treg == 0) | |
3790 | { | |
3791 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3792 | likely ? "blezl" : "blez", | |
3793 | "s,p", sreg); | |
3794 | return; | |
3795 | } | |
3796 | if (sreg == 0) | |
3797 | { | |
3798 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3799 | likely ? "bgezl" : "bgez", | |
3800 | "s,p", treg); | |
3801 | return; | |
3802 | } | |
3803 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", AT, treg, sreg); | |
3804 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3805 | likely ? "beql" : "beq", | |
3806 | "s,t,p", AT, 0); | |
3807 | break; | |
3808 | ||
3809 | case M_BLEL_I: | |
3810 | likely = 1; | |
3811 | case M_BLE_I: | |
3812 | maxnum = 0x7fffffff; | |
9ce8a5dd | 3813 | if (ISA_HAS_64BIT_REGS (mips_opts.isa) && sizeof (maxnum) > 4) |
252b5132 RH |
3814 | { |
3815 | maxnum <<= 16; | |
3816 | maxnum |= 0xffff; | |
3817 | maxnum <<= 16; | |
3818 | maxnum |= 0xffff; | |
3819 | } | |
3820 | if (imm_expr.X_op == O_constant | |
3821 | && imm_expr.X_add_number >= maxnum | |
9ce8a5dd | 3822 | && (! ISA_HAS_64BIT_REGS (mips_opts.isa) || sizeof (maxnum) > 4)) |
252b5132 RH |
3823 | goto do_true; |
3824 | if (imm_expr.X_op != O_constant) | |
3825 | as_bad (_("Unsupported large constant")); | |
3826 | imm_expr.X_add_number++; | |
3827 | /* FALLTHROUGH */ | |
3828 | case M_BLT_I: | |
3829 | case M_BLTL_I: | |
3830 | if (mask == M_BLTL_I) | |
3831 | likely = 1; | |
3832 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
3833 | { | |
3834 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3835 | likely ? "bltzl" : "bltz", | |
3836 | "s,p", sreg); | |
3837 | return; | |
3838 | } | |
3839 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
3840 | { | |
3841 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3842 | likely ? "blezl" : "blez", | |
3843 | "s,p", sreg); | |
3844 | return; | |
3845 | } | |
3846 | set_at (&icnt, sreg, 0); | |
3847 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3848 | likely ? "bnel" : "bne", | |
3849 | "s,t,p", AT, 0); | |
3850 | break; | |
3851 | ||
3852 | case M_BLEUL: | |
3853 | likely = 1; | |
3854 | case M_BLEU: | |
3855 | if (treg == 0) | |
3856 | { | |
3857 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3858 | likely ? "beql" : "beq", | |
3859 | "s,t,p", sreg, 0); | |
3860 | return; | |
3861 | } | |
3862 | if (sreg == 0) | |
3863 | goto do_true; | |
3864 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", AT, treg, | |
3865 | sreg); | |
3866 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3867 | likely ? "beql" : "beq", | |
3868 | "s,t,p", AT, 0); | |
3869 | break; | |
3870 | ||
3871 | case M_BLEUL_I: | |
3872 | likely = 1; | |
3873 | case M_BLEU_I: | |
3874 | if (sreg == 0 | |
9ce8a5dd | 3875 | || (! ISA_HAS_64BIT_REGS (mips_opts.isa) |
252b5132 RH |
3876 | && imm_expr.X_op == O_constant |
3877 | && imm_expr.X_add_number == 0xffffffff)) | |
3878 | goto do_true; | |
3879 | if (imm_expr.X_op != O_constant) | |
3880 | as_bad (_("Unsupported large constant")); | |
3881 | imm_expr.X_add_number++; | |
3882 | /* FALLTHROUGH */ | |
3883 | case M_BLTU_I: | |
3884 | case M_BLTUL_I: | |
3885 | if (mask == M_BLTUL_I) | |
3886 | likely = 1; | |
3887 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
3888 | goto do_false; | |
3889 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
3890 | { | |
3891 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3892 | likely ? "beql" : "beq", | |
3893 | "s,t,p", sreg, 0); | |
3894 | return; | |
3895 | } | |
3896 | set_at (&icnt, sreg, 1); | |
3897 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3898 | likely ? "bnel" : "bne", | |
3899 | "s,t,p", AT, 0); | |
3900 | break; | |
3901 | ||
3902 | case M_BLTL: | |
3903 | likely = 1; | |
3904 | case M_BLT: | |
3905 | if (treg == 0) | |
3906 | { | |
3907 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3908 | likely ? "bltzl" : "bltz", | |
3909 | "s,p", sreg); | |
3910 | return; | |
3911 | } | |
3912 | if (sreg == 0) | |
3913 | { | |
3914 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3915 | likely ? "bgtzl" : "bgtz", | |
3916 | "s,p", treg); | |
3917 | return; | |
3918 | } | |
3919 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", AT, sreg, treg); | |
3920 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3921 | likely ? "bnel" : "bne", | |
3922 | "s,t,p", AT, 0); | |
3923 | break; | |
3924 | ||
3925 | case M_BLTUL: | |
3926 | likely = 1; | |
3927 | case M_BLTU: | |
3928 | if (treg == 0) | |
3929 | goto do_false; | |
3930 | if (sreg == 0) | |
3931 | { | |
3932 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3933 | likely ? "bnel" : "bne", | |
3934 | "s,t,p", 0, treg); | |
3935 | return; | |
3936 | } | |
3937 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", AT, sreg, | |
3938 | treg); | |
3939 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3940 | likely ? "bnel" : "bne", | |
3941 | "s,t,p", AT, 0); | |
3942 | break; | |
3943 | ||
3944 | case M_DDIV_3: | |
3945 | dbl = 1; | |
3946 | case M_DIV_3: | |
3947 | s = "mflo"; | |
3948 | goto do_div3; | |
3949 | case M_DREM_3: | |
3950 | dbl = 1; | |
3951 | case M_REM_3: | |
3952 | s = "mfhi"; | |
3953 | do_div3: | |
3954 | if (treg == 0) | |
3955 | { | |
3956 | as_warn (_("Divide by zero.")); | |
3957 | if (mips_trap) | |
3958 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", 0, 0); | |
3959 | else | |
9117d219 | 3960 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 7); |
252b5132 RH |
3961 | return; |
3962 | } | |
3963 | ||
3964 | mips_emit_delays (true); | |
3965 | ++mips_opts.noreorder; | |
3966 | mips_any_noreorder = 1; | |
3967 | if (mips_trap) | |
3968 | { | |
3969 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", treg, 0); | |
3970 | macro_build ((char *) NULL, &icnt, NULL, | |
3971 | dbl ? "ddiv" : "div", | |
3972 | "z,s,t", sreg, treg); | |
3973 | } | |
3974 | else | |
3975 | { | |
3976 | expr1.X_add_number = 8; | |
3977 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, 0); | |
3978 | macro_build ((char *) NULL, &icnt, NULL, | |
3979 | dbl ? "ddiv" : "div", | |
3980 | "z,s,t", sreg, treg); | |
9117d219 | 3981 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 7); |
252b5132 RH |
3982 | } |
3983 | expr1.X_add_number = -1; | |
3984 | macro_build ((char *) NULL, &icnt, &expr1, | |
3985 | dbl ? "daddiu" : "addiu", | |
3986 | "t,r,j", AT, 0, (int) BFD_RELOC_LO16); | |
3987 | expr1.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16); | |
3988 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, AT); | |
3989 | if (dbl) | |
3990 | { | |
3991 | expr1.X_add_number = 1; | |
3992 | macro_build ((char *) NULL, &icnt, &expr1, "daddiu", "t,r,j", AT, 0, | |
3993 | (int) BFD_RELOC_LO16); | |
3994 | macro_build ((char *) NULL, &icnt, NULL, "dsll32", "d,w,<", AT, AT, | |
3995 | 31); | |
3996 | } | |
3997 | else | |
3998 | { | |
3999 | expr1.X_add_number = 0x80000000; | |
4000 | macro_build ((char *) NULL, &icnt, &expr1, "lui", "t,u", AT, | |
4001 | (int) BFD_RELOC_HI16); | |
4002 | } | |
4003 | if (mips_trap) | |
4004 | { | |
4005 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", sreg, AT); | |
4006 | /* We want to close the noreorder block as soon as possible, so | |
4007 | that later insns are available for delay slot filling. */ | |
4008 | --mips_opts.noreorder; | |
4009 | } | |
4010 | else | |
4011 | { | |
4012 | expr1.X_add_number = 8; | |
4013 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", sreg, AT); | |
4014 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); | |
4015 | ||
4016 | /* We want to close the noreorder block as soon as possible, so | |
4017 | that later insns are available for delay slot filling. */ | |
4018 | --mips_opts.noreorder; | |
4019 | ||
9117d219 | 4020 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 6); |
252b5132 RH |
4021 | } |
4022 | macro_build ((char *) NULL, &icnt, NULL, s, "d", dreg); | |
4023 | break; | |
4024 | ||
4025 | case M_DIV_3I: | |
4026 | s = "div"; | |
4027 | s2 = "mflo"; | |
4028 | goto do_divi; | |
4029 | case M_DIVU_3I: | |
4030 | s = "divu"; | |
4031 | s2 = "mflo"; | |
4032 | goto do_divi; | |
4033 | case M_REM_3I: | |
4034 | s = "div"; | |
4035 | s2 = "mfhi"; | |
4036 | goto do_divi; | |
4037 | case M_REMU_3I: | |
4038 | s = "divu"; | |
4039 | s2 = "mfhi"; | |
4040 | goto do_divi; | |
4041 | case M_DDIV_3I: | |
4042 | dbl = 1; | |
4043 | s = "ddiv"; | |
4044 | s2 = "mflo"; | |
4045 | goto do_divi; | |
4046 | case M_DDIVU_3I: | |
4047 | dbl = 1; | |
4048 | s = "ddivu"; | |
4049 | s2 = "mflo"; | |
4050 | goto do_divi; | |
4051 | case M_DREM_3I: | |
4052 | dbl = 1; | |
4053 | s = "ddiv"; | |
4054 | s2 = "mfhi"; | |
4055 | goto do_divi; | |
4056 | case M_DREMU_3I: | |
4057 | dbl = 1; | |
4058 | s = "ddivu"; | |
4059 | s2 = "mfhi"; | |
4060 | do_divi: | |
4061 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4062 | { | |
4063 | as_warn (_("Divide by zero.")); | |
4064 | if (mips_trap) | |
4065 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", 0, 0); | |
4066 | else | |
beae10d5 | 4067 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 7); |
252b5132 RH |
4068 | return; |
4069 | } | |
4070 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4071 | { | |
4072 | if (strcmp (s2, "mflo") == 0) | |
4073 | macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, | |
4074 | sreg); | |
4075 | else | |
4076 | macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, 0); | |
4077 | return; | |
4078 | } | |
4079 | if (imm_expr.X_op == O_constant | |
4080 | && imm_expr.X_add_number == -1 | |
4081 | && s[strlen (s) - 1] != 'u') | |
4082 | { | |
4083 | if (strcmp (s2, "mflo") == 0) | |
4084 | { | |
4085 | if (dbl) | |
4086 | macro_build ((char *) NULL, &icnt, NULL, "dneg", "d,w", dreg, | |
4087 | sreg); | |
4088 | else | |
4089 | macro_build ((char *) NULL, &icnt, NULL, "neg", "d,w", dreg, | |
4090 | sreg); | |
4091 | } | |
4092 | else | |
4093 | macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, 0); | |
4094 | return; | |
4095 | } | |
4096 | ||
4097 | load_register (&icnt, AT, &imm_expr, dbl); | |
4098 | macro_build ((char *) NULL, &icnt, NULL, s, "z,s,t", sreg, AT); | |
4099 | macro_build ((char *) NULL, &icnt, NULL, s2, "d", dreg); | |
4100 | break; | |
4101 | ||
4102 | case M_DIVU_3: | |
4103 | s = "divu"; | |
4104 | s2 = "mflo"; | |
4105 | goto do_divu3; | |
4106 | case M_REMU_3: | |
4107 | s = "divu"; | |
4108 | s2 = "mfhi"; | |
4109 | goto do_divu3; | |
4110 | case M_DDIVU_3: | |
4111 | s = "ddivu"; | |
4112 | s2 = "mflo"; | |
4113 | goto do_divu3; | |
4114 | case M_DREMU_3: | |
4115 | s = "ddivu"; | |
4116 | s2 = "mfhi"; | |
4117 | do_divu3: | |
4118 | mips_emit_delays (true); | |
4119 | ++mips_opts.noreorder; | |
4120 | mips_any_noreorder = 1; | |
4121 | if (mips_trap) | |
4122 | { | |
4123 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", treg, 0); | |
4124 | macro_build ((char *) NULL, &icnt, NULL, s, "z,s,t", sreg, treg); | |
4125 | /* We want to close the noreorder block as soon as possible, so | |
4126 | that later insns are available for delay slot filling. */ | |
4127 | --mips_opts.noreorder; | |
4128 | } | |
4129 | else | |
4130 | { | |
4131 | expr1.X_add_number = 8; | |
4132 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, 0); | |
4133 | macro_build ((char *) NULL, &icnt, NULL, s, "z,s,t", sreg, treg); | |
4134 | ||
4135 | /* We want to close the noreorder block as soon as possible, so | |
4136 | that later insns are available for delay slot filling. */ | |
4137 | --mips_opts.noreorder; | |
beae10d5 | 4138 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 7); |
252b5132 RH |
4139 | } |
4140 | macro_build ((char *) NULL, &icnt, NULL, s2, "d", dreg); | |
4141 | return; | |
4142 | ||
4143 | case M_DLA_AB: | |
4144 | dbl = 1; | |
4145 | case M_LA_AB: | |
4146 | /* Load the address of a symbol into a register. If breg is not | |
4147 | zero, we then add a base register to it. */ | |
4148 | ||
4149 | /* When generating embedded PIC code, we permit expressions of | |
4150 | the form | |
4151 | la $4,foo-bar | |
bb2d6cd7 | 4152 | where bar is an address in the current section. These are used |
252b5132 RH |
4153 | when getting the addresses of functions. We don't permit |
4154 | X_add_number to be non-zero, because if the symbol is | |
4155 | external the relaxing code needs to know that any addend is | |
4156 | purely the offset to X_op_symbol. */ | |
4157 | if (mips_pic == EMBEDDED_PIC | |
4158 | && offset_expr.X_op == O_subtract | |
49309057 | 4159 | && (symbol_constant_p (offset_expr.X_op_symbol) |
bb2d6cd7 | 4160 | ? S_GET_SEGMENT (offset_expr.X_op_symbol) == now_seg |
49309057 ILT |
4161 | : (symbol_equated_p (offset_expr.X_op_symbol) |
4162 | && (S_GET_SEGMENT | |
4163 | (symbol_get_value_expression (offset_expr.X_op_symbol) | |
4164 | ->X_add_symbol) | |
bb2d6cd7 | 4165 | == now_seg))) |
252b5132 | 4166 | && breg == 0 |
bb2d6cd7 GK |
4167 | && (offset_expr.X_add_number == 0 |
4168 | || OUTPUT_FLAVOR == bfd_target_elf_flavour)) | |
252b5132 RH |
4169 | { |
4170 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
4171 | treg, (int) BFD_RELOC_PCREL_HI16_S); | |
4172 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
4173 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 4174 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
4175 | ? "addiu" : "daddiu"), |
4176 | "t,r,j", treg, treg, (int) BFD_RELOC_PCREL_LO16); | |
4177 | return; | |
4178 | } | |
4179 | ||
4180 | if (offset_expr.X_op != O_symbol | |
4181 | && offset_expr.X_op != O_constant) | |
4182 | { | |
4183 | as_bad (_("expression too complex")); | |
4184 | offset_expr.X_op = O_constant; | |
4185 | } | |
4186 | ||
4187 | if (treg == breg) | |
4188 | { | |
4189 | tempreg = AT; | |
4190 | used_at = 1; | |
4191 | } | |
4192 | else | |
4193 | { | |
4194 | tempreg = treg; | |
4195 | used_at = 0; | |
4196 | } | |
4197 | ||
4198 | if (offset_expr.X_op == O_constant) | |
4199 | load_register (&icnt, tempreg, &offset_expr, dbl); | |
4200 | else if (mips_pic == NO_PIC) | |
4201 | { | |
4202 | /* If this is a reference to an GP relative symbol, we want | |
4203 | addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL) | |
4204 | Otherwise we want | |
4205 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
4206 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
4207 | If we have a constant, we need two instructions anyhow, | |
4208 | so we may as well always use the latter form. */ | |
4209 | if ((valueT) offset_expr.X_add_number >= MAX_GPREL_OFFSET | |
4210 | || nopic_need_relax (offset_expr.X_add_symbol, 1)) | |
4211 | p = NULL; | |
4212 | else | |
4213 | { | |
4214 | frag_grow (20); | |
4215 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
4216 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 4217 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
4218 | ? "addiu" : "daddiu"), |
4219 | "t,r,j", tempreg, GP, (int) BFD_RELOC_MIPS_GPREL); | |
4220 | p = frag_var (rs_machine_dependent, 8, 0, | |
4221 | RELAX_ENCODE (4, 8, 0, 4, 0, | |
4222 | mips_opts.warn_about_macros), | |
4223 | offset_expr.X_add_symbol, (offsetT) 0, | |
4224 | (char *) NULL); | |
4225 | } | |
4226 | macro_build_lui (p, &icnt, &offset_expr, tempreg); | |
4227 | if (p != NULL) | |
4228 | p += 4; | |
4229 | macro_build (p, &icnt, &offset_expr, | |
4230 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 4231 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
4232 | ? "addiu" : "daddiu"), |
4233 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); | |
4234 | } | |
4235 | else if (mips_pic == SVR4_PIC && ! mips_big_got) | |
4236 | { | |
9117d219 NC |
4237 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
4238 | ||
252b5132 RH |
4239 | /* If this is a reference to an external symbol, and there |
4240 | is no constant, we want | |
4241 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
9117d219 NC |
4242 | or if tempreg is PIC_CALL_REG |
4243 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) | |
252b5132 RH |
4244 | For a local symbol, we want |
4245 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4246 | nop | |
4247 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
4248 | ||
4249 | If we have a small constant, and this is a reference to | |
4250 | an external symbol, we want | |
4251 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4252 | nop | |
4253 | addiu $tempreg,$tempreg,<constant> | |
4254 | For a local symbol, we want the same instruction | |
4255 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
4256 | addiu instruction. | |
4257 | ||
4258 | If we have a large constant, and this is a reference to | |
4259 | an external symbol, we want | |
4260 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4261 | lui $at,<hiconstant> | |
4262 | addiu $at,$at,<loconstant> | |
4263 | addu $tempreg,$tempreg,$at | |
4264 | For a local symbol, we want the same instruction | |
4265 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
4266 | addiu instruction. */ | |
4267 | expr1.X_add_number = offset_expr.X_add_number; | |
4268 | offset_expr.X_add_number = 0; | |
4269 | frag_grow (32); | |
9117d219 NC |
4270 | if (expr1.X_add_number == 0 && tempreg == PIC_CALL_REG) |
4271 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16; | |
252b5132 RH |
4272 | macro_build ((char *) NULL, &icnt, &offset_expr, |
4273 | dbl ? "ld" : "lw", | |
9117d219 | 4274 | "t,o(b)", tempreg, lw_reloc_type, GP); |
252b5132 RH |
4275 | if (expr1.X_add_number == 0) |
4276 | { | |
4277 | int off; | |
4278 | ||
4279 | if (breg == 0) | |
4280 | off = 0; | |
4281 | else | |
4282 | { | |
4283 | /* We're going to put in an addu instruction using | |
4284 | tempreg, so we may as well insert the nop right | |
4285 | now. */ | |
4286 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4287 | "nop", ""); | |
4288 | off = 4; | |
4289 | } | |
4290 | p = frag_var (rs_machine_dependent, 8 - off, 0, | |
4291 | RELAX_ENCODE (0, 8 - off, -4 - off, 4 - off, 0, | |
4292 | (breg == 0 | |
4293 | ? mips_opts.warn_about_macros | |
4294 | : 0)), | |
4295 | offset_expr.X_add_symbol, (offsetT) 0, | |
4296 | (char *) NULL); | |
4297 | if (breg == 0) | |
4298 | { | |
4299 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4300 | p += 4; | |
4301 | } | |
4302 | macro_build (p, &icnt, &expr1, | |
4303 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 4304 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
4305 | ? "addiu" : "daddiu"), |
4306 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); | |
4307 | /* FIXME: If breg == 0, and the next instruction uses | |
4308 | $tempreg, then if this variant case is used an extra | |
4309 | nop will be generated. */ | |
4310 | } | |
4311 | else if (expr1.X_add_number >= -0x8000 | |
4312 | && expr1.X_add_number < 0x8000) | |
4313 | { | |
4314 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4315 | "nop", ""); | |
4316 | macro_build ((char *) NULL, &icnt, &expr1, | |
4317 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 4318 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
4319 | ? "addiu" : "daddiu"), |
4320 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); | |
4321 | (void) frag_var (rs_machine_dependent, 0, 0, | |
4322 | RELAX_ENCODE (0, 0, -12, -4, 0, 0), | |
4323 | offset_expr.X_add_symbol, (offsetT) 0, | |
4324 | (char *) NULL); | |
4325 | } | |
4326 | else | |
4327 | { | |
4328 | int off1; | |
4329 | ||
4330 | /* If we are going to add in a base register, and the | |
4331 | target register and the base register are the same, | |
4332 | then we are using AT as a temporary register. Since | |
4333 | we want to load the constant into AT, we add our | |
4334 | current AT (from the global offset table) and the | |
4335 | register into the register now, and pretend we were | |
4336 | not using a base register. */ | |
4337 | if (breg != treg) | |
4338 | off1 = 0; | |
4339 | else | |
4340 | { | |
4341 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4342 | "nop", ""); | |
4343 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4344 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 4345 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
4346 | ? "addu" : "daddu"), |
4347 | "d,v,t", treg, AT, breg); | |
4348 | breg = 0; | |
4349 | tempreg = treg; | |
4350 | off1 = -8; | |
4351 | } | |
4352 | ||
4353 | /* Set mips_optimize around the lui instruction to avoid | |
4354 | inserting an unnecessary nop after the lw. */ | |
4355 | hold_mips_optimize = mips_optimize; | |
4356 | mips_optimize = 2; | |
4357 | macro_build_lui ((char *) NULL, &icnt, &expr1, AT); | |
4358 | mips_optimize = hold_mips_optimize; | |
4359 | ||
4360 | macro_build ((char *) NULL, &icnt, &expr1, | |
4361 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 4362 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
4363 | ? "addiu" : "daddiu"), |
4364 | "t,r,j", AT, AT, (int) BFD_RELOC_LO16); | |
4365 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4366 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 4367 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
4368 | ? "addu" : "daddu"), |
4369 | "d,v,t", tempreg, tempreg, AT); | |
4370 | (void) frag_var (rs_machine_dependent, 0, 0, | |
4371 | RELAX_ENCODE (0, 0, -16 + off1, -8, 0, 0), | |
4372 | offset_expr.X_add_symbol, (offsetT) 0, | |
4373 | (char *) NULL); | |
4374 | used_at = 1; | |
4375 | } | |
4376 | } | |
4377 | else if (mips_pic == SVR4_PIC) | |
4378 | { | |
4379 | int gpdel; | |
9117d219 NC |
4380 | int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; |
4381 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; | |
252b5132 RH |
4382 | |
4383 | /* This is the large GOT case. If this is a reference to an | |
4384 | external symbol, and there is no constant, we want | |
4385 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
4386 | addu $tempreg,$tempreg,$gp | |
4387 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
9117d219 NC |
4388 | or if tempreg is PIC_CALL_REG |
4389 | lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) | |
4390 | addu $tempreg,$tempreg,$gp | |
4391 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) | |
252b5132 RH |
4392 | For a local symbol, we want |
4393 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4394 | nop | |
4395 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
4396 | ||
4397 | If we have a small constant, and this is a reference to | |
4398 | an external symbol, we want | |
4399 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
4400 | addu $tempreg,$tempreg,$gp | |
4401 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
4402 | nop | |
4403 | addiu $tempreg,$tempreg,<constant> | |
4404 | For a local symbol, we want | |
4405 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4406 | nop | |
4407 | addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16) | |
4408 | ||
4409 | If we have a large constant, and this is a reference to | |
4410 | an external symbol, we want | |
4411 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
4412 | addu $tempreg,$tempreg,$gp | |
4413 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
4414 | lui $at,<hiconstant> | |
4415 | addiu $at,$at,<loconstant> | |
4416 | addu $tempreg,$tempreg,$at | |
4417 | For a local symbol, we want | |
4418 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4419 | lui $at,<hiconstant> | |
4420 | addiu $at,$at,<loconstant> (BFD_RELOC_LO16) | |
4421 | addu $tempreg,$tempreg,$at | |
4422 | */ | |
4423 | expr1.X_add_number = offset_expr.X_add_number; | |
4424 | offset_expr.X_add_number = 0; | |
4425 | frag_grow (52); | |
4426 | if (reg_needs_delay (GP)) | |
4427 | gpdel = 4; | |
4428 | else | |
4429 | gpdel = 0; | |
9117d219 NC |
4430 | if (expr1.X_add_number == 0 && tempreg == PIC_CALL_REG) |
4431 | { | |
4432 | lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; | |
4433 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; | |
4434 | } | |
252b5132 | 4435 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", |
9117d219 | 4436 | tempreg, lui_reloc_type); |
252b5132 RH |
4437 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
4438 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 4439 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
4440 | ? "addu" : "daddu"), |
4441 | "d,v,t", tempreg, tempreg, GP); | |
4442 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
4443 | dbl ? "ld" : "lw", | |
9117d219 | 4444 | "t,o(b)", tempreg, lw_reloc_type, tempreg); |
252b5132 RH |
4445 | if (expr1.X_add_number == 0) |
4446 | { | |
4447 | int off; | |
4448 | ||
4449 | if (breg == 0) | |
4450 | off = 0; | |
4451 | else | |
4452 | { | |
4453 | /* We're going to put in an addu instruction using | |
4454 | tempreg, so we may as well insert the nop right | |
4455 | now. */ | |
4456 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4457 | "nop", ""); | |
4458 | off = 4; | |
4459 | } | |
4460 | ||
4461 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, | |
4462 | RELAX_ENCODE (12 + off, 12 + gpdel, gpdel, | |
4463 | 8 + gpdel, 0, | |
4464 | (breg == 0 | |
4465 | ? mips_opts.warn_about_macros | |
4466 | : 0)), | |
4467 | offset_expr.X_add_symbol, (offsetT) 0, | |
4468 | (char *) NULL); | |
4469 | } | |
4470 | else if (expr1.X_add_number >= -0x8000 | |
4471 | && expr1.X_add_number < 0x8000) | |
4472 | { | |
4473 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4474 | "nop", ""); | |
4475 | macro_build ((char *) NULL, &icnt, &expr1, | |
4476 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 4477 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
4478 | ? "addiu" : "daddiu"), |
4479 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); | |
4480 | ||
4481 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, | |
4482 | RELAX_ENCODE (20, 12 + gpdel, gpdel, 8 + gpdel, 0, | |
4483 | (breg == 0 | |
4484 | ? mips_opts.warn_about_macros | |
4485 | : 0)), | |
4486 | offset_expr.X_add_symbol, (offsetT) 0, | |
4487 | (char *) NULL); | |
4488 | } | |
4489 | else | |
4490 | { | |
4491 | int adj, dreg; | |
4492 | ||
4493 | /* If we are going to add in a base register, and the | |
4494 | target register and the base register are the same, | |
4495 | then we are using AT as a temporary register. Since | |
4496 | we want to load the constant into AT, we add our | |
4497 | current AT (from the global offset table) and the | |
4498 | register into the register now, and pretend we were | |
4499 | not using a base register. */ | |
4500 | if (breg != treg) | |
4501 | { | |
4502 | adj = 0; | |
4503 | dreg = tempreg; | |
4504 | } | |
4505 | else | |
4506 | { | |
4507 | assert (tempreg == AT); | |
4508 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4509 | "nop", ""); | |
4510 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4511 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 4512 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
4513 | ? "addu" : "daddu"), |
4514 | "d,v,t", treg, AT, breg); | |
4515 | dreg = treg; | |
4516 | adj = 8; | |
4517 | } | |
4518 | ||
4519 | /* Set mips_optimize around the lui instruction to avoid | |
4520 | inserting an unnecessary nop after the lw. */ | |
4521 | hold_mips_optimize = mips_optimize; | |
4522 | mips_optimize = 2; | |
4523 | macro_build_lui ((char *) NULL, &icnt, &expr1, AT); | |
4524 | mips_optimize = hold_mips_optimize; | |
4525 | ||
4526 | macro_build ((char *) NULL, &icnt, &expr1, | |
4527 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 4528 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
4529 | ? "addiu" : "daddiu"), |
4530 | "t,r,j", AT, AT, (int) BFD_RELOC_LO16); | |
4531 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4532 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 4533 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
4534 | ? "addu" : "daddu"), |
4535 | "d,v,t", dreg, dreg, AT); | |
4536 | ||
4537 | p = frag_var (rs_machine_dependent, 16 + gpdel + adj, 0, | |
4538 | RELAX_ENCODE (24 + adj, 16 + gpdel + adj, gpdel, | |
4539 | 8 + gpdel, 0, | |
4540 | (breg == 0 | |
4541 | ? mips_opts.warn_about_macros | |
4542 | : 0)), | |
4543 | offset_expr.X_add_symbol, (offsetT) 0, | |
4544 | (char *) NULL); | |
4545 | ||
4546 | used_at = 1; | |
4547 | } | |
4548 | ||
4549 | if (gpdel > 0) | |
4550 | { | |
4551 | /* This is needed because this instruction uses $gp, but | |
4552 | the first instruction on the main stream does not. */ | |
4553 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4554 | p += 4; | |
4555 | } | |
4556 | macro_build (p, &icnt, &offset_expr, | |
4557 | dbl ? "ld" : "lw", | |
4558 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, GP); | |
4559 | p += 4; | |
4560 | if (expr1.X_add_number >= -0x8000 | |
4561 | && expr1.X_add_number < 0x8000) | |
4562 | { | |
4563 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4564 | p += 4; | |
4565 | macro_build (p, &icnt, &expr1, | |
4566 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 4567 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
4568 | ? "addiu" : "daddiu"), |
4569 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); | |
4570 | /* FIXME: If add_number is 0, and there was no base | |
4571 | register, the external symbol case ended with a load, | |
4572 | so if the symbol turns out to not be external, and | |
4573 | the next instruction uses tempreg, an unnecessary nop | |
4574 | will be inserted. */ | |
4575 | } | |
4576 | else | |
4577 | { | |
4578 | if (breg == treg) | |
4579 | { | |
4580 | /* We must add in the base register now, as in the | |
4581 | external symbol case. */ | |
4582 | assert (tempreg == AT); | |
4583 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4584 | p += 4; | |
4585 | macro_build (p, &icnt, (expressionS *) NULL, | |
4586 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 4587 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
4588 | ? "addu" : "daddu"), |
4589 | "d,v,t", treg, AT, breg); | |
4590 | p += 4; | |
4591 | tempreg = treg; | |
4592 | /* We set breg to 0 because we have arranged to add | |
4593 | it in in both cases. */ | |
4594 | breg = 0; | |
4595 | } | |
4596 | ||
4597 | macro_build_lui (p, &icnt, &expr1, AT); | |
4598 | p += 4; | |
4599 | macro_build (p, &icnt, &expr1, | |
4600 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 4601 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
4602 | ? "addiu" : "daddiu"), |
4603 | "t,r,j", AT, AT, (int) BFD_RELOC_LO16); | |
4604 | p += 4; | |
4605 | macro_build (p, &icnt, (expressionS *) NULL, | |
4606 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 4607 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
4608 | ? "addu" : "daddu"), |
4609 | "d,v,t", tempreg, tempreg, AT); | |
4610 | p += 4; | |
4611 | } | |
4612 | } | |
4613 | else if (mips_pic == EMBEDDED_PIC) | |
4614 | { | |
4615 | /* We use | |
4616 | addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL) | |
4617 | */ | |
4618 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
4619 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 4620 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
4621 | ? "addiu" : "daddiu"), |
4622 | "t,r,j", tempreg, GP, (int) BFD_RELOC_MIPS_GPREL); | |
4623 | } | |
4624 | else | |
4625 | abort (); | |
4626 | ||
4627 | if (breg != 0) | |
4628 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4629 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 4630 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
4631 | ? "addu" : "daddu"), |
4632 | "d,v,t", treg, tempreg, breg); | |
4633 | ||
4634 | if (! used_at) | |
4635 | return; | |
4636 | ||
4637 | break; | |
4638 | ||
4639 | case M_J_A: | |
4640 | /* The j instruction may not be used in PIC code, since it | |
4641 | requires an absolute address. We convert it to a b | |
4642 | instruction. */ | |
4643 | if (mips_pic == NO_PIC) | |
4644 | macro_build ((char *) NULL, &icnt, &offset_expr, "j", "a"); | |
4645 | else | |
4646 | macro_build ((char *) NULL, &icnt, &offset_expr, "b", "p"); | |
4647 | return; | |
4648 | ||
4649 | /* The jal instructions must be handled as macros because when | |
4650 | generating PIC code they expand to multi-instruction | |
4651 | sequences. Normally they are simple instructions. */ | |
4652 | case M_JAL_1: | |
4653 | dreg = RA; | |
4654 | /* Fall through. */ | |
4655 | case M_JAL_2: | |
4656 | if (mips_pic == NO_PIC | |
4657 | || mips_pic == EMBEDDED_PIC) | |
4658 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "jalr", | |
4659 | "d,s", dreg, sreg); | |
4660 | else if (mips_pic == SVR4_PIC) | |
4661 | { | |
4662 | if (sreg != PIC_CALL_REG) | |
4663 | as_warn (_("MIPS PIC call to register other than $25")); | |
bdaaa2e1 | 4664 | |
252b5132 RH |
4665 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "jalr", |
4666 | "d,s", dreg, sreg); | |
4667 | if (mips_cprestore_offset < 0) | |
4668 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
4669 | else | |
4670 | { | |
4671 | expr1.X_add_number = mips_cprestore_offset; | |
4672 | macro_build ((char *) NULL, &icnt, &expr1, | |
4673 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 4674 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
4675 | ? "lw" : "ld"), |
4676 | "t,o(b)", GP, (int) BFD_RELOC_LO16, mips_frame_reg); | |
4677 | } | |
4678 | } | |
4679 | else | |
4680 | abort (); | |
4681 | ||
4682 | return; | |
4683 | ||
4684 | case M_JAL_A: | |
4685 | if (mips_pic == NO_PIC) | |
4686 | macro_build ((char *) NULL, &icnt, &offset_expr, "jal", "a"); | |
4687 | else if (mips_pic == SVR4_PIC) | |
4688 | { | |
4689 | /* If this is a reference to an external symbol, and we are | |
4690 | using a small GOT, we want | |
4691 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16) | |
4692 | nop | |
4693 | jalr $25 | |
4694 | nop | |
4695 | lw $gp,cprestore($sp) | |
4696 | The cprestore value is set using the .cprestore | |
4697 | pseudo-op. If we are using a big GOT, we want | |
4698 | lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16) | |
4699 | addu $25,$25,$gp | |
4700 | lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16) | |
4701 | nop | |
4702 | jalr $25 | |
4703 | nop | |
4704 | lw $gp,cprestore($sp) | |
4705 | If the symbol is not external, we want | |
4706 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4707 | nop | |
4708 | addiu $25,$25,<sym> (BFD_RELOC_LO16) | |
4709 | jalr $25 | |
4710 | nop | |
4711 | lw $gp,cprestore($sp) */ | |
4712 | frag_grow (40); | |
4713 | if (! mips_big_got) | |
4714 | { | |
4715 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
4716 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 4717 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
4718 | ? "lw" : "ld"), |
4719 | "t,o(b)", PIC_CALL_REG, | |
4720 | (int) BFD_RELOC_MIPS_CALL16, GP); | |
4721 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4722 | "nop", ""); | |
4723 | p = frag_var (rs_machine_dependent, 4, 0, | |
4724 | RELAX_ENCODE (0, 4, -8, 0, 0, 0), | |
4725 | offset_expr.X_add_symbol, (offsetT) 0, | |
4726 | (char *) NULL); | |
4727 | } | |
4728 | else | |
4729 | { | |
4730 | int gpdel; | |
4731 | ||
4732 | if (reg_needs_delay (GP)) | |
4733 | gpdel = 4; | |
4734 | else | |
4735 | gpdel = 0; | |
4736 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
4737 | PIC_CALL_REG, (int) BFD_RELOC_MIPS_CALL_HI16); | |
4738 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4739 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 4740 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
4741 | ? "addu" : "daddu"), |
4742 | "d,v,t", PIC_CALL_REG, PIC_CALL_REG, GP); | |
4743 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
4744 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 4745 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
4746 | ? "lw" : "ld"), |
4747 | "t,o(b)", PIC_CALL_REG, | |
4748 | (int) BFD_RELOC_MIPS_CALL_LO16, PIC_CALL_REG); | |
4749 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4750 | "nop", ""); | |
4751 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, | |
4752 | RELAX_ENCODE (16, 12 + gpdel, gpdel, 8 + gpdel, | |
4753 | 0, 0), | |
4754 | offset_expr.X_add_symbol, (offsetT) 0, | |
4755 | (char *) NULL); | |
4756 | if (gpdel > 0) | |
4757 | { | |
4758 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4759 | p += 4; | |
4760 | } | |
4761 | macro_build (p, &icnt, &offset_expr, | |
4762 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 4763 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
4764 | ? "lw" : "ld"), |
4765 | "t,o(b)", PIC_CALL_REG, | |
4766 | (int) BFD_RELOC_MIPS_GOT16, GP); | |
4767 | p += 4; | |
4768 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4769 | p += 4; | |
bdaaa2e1 | 4770 | } |
252b5132 RH |
4771 | macro_build (p, &icnt, &offset_expr, |
4772 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 4773 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
4774 | ? "addiu" : "daddiu"), |
4775 | "t,r,j", PIC_CALL_REG, PIC_CALL_REG, | |
4776 | (int) BFD_RELOC_LO16); | |
4777 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4778 | "jalr", "s", PIC_CALL_REG); | |
4779 | if (mips_cprestore_offset < 0) | |
4780 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
4781 | else | |
4782 | { | |
4783 | if (mips_opts.noreorder) | |
4784 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4785 | "nop", ""); | |
4786 | expr1.X_add_number = mips_cprestore_offset; | |
4787 | macro_build ((char *) NULL, &icnt, &expr1, | |
4788 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 4789 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
4790 | ? "lw" : "ld"), |
4791 | "t,o(b)", GP, (int) BFD_RELOC_LO16, | |
4792 | mips_frame_reg); | |
4793 | } | |
4794 | } | |
4795 | else if (mips_pic == EMBEDDED_PIC) | |
4796 | { | |
4797 | macro_build ((char *) NULL, &icnt, &offset_expr, "bal", "p"); | |
4798 | /* The linker may expand the call to a longer sequence which | |
4799 | uses $at, so we must break rather than return. */ | |
4800 | break; | |
4801 | } | |
4802 | else | |
4803 | abort (); | |
4804 | ||
4805 | return; | |
4806 | ||
4807 | case M_LB_AB: | |
4808 | s = "lb"; | |
4809 | goto ld; | |
4810 | case M_LBU_AB: | |
4811 | s = "lbu"; | |
4812 | goto ld; | |
4813 | case M_LH_AB: | |
4814 | s = "lh"; | |
4815 | goto ld; | |
4816 | case M_LHU_AB: | |
4817 | s = "lhu"; | |
4818 | goto ld; | |
4819 | case M_LW_AB: | |
4820 | s = "lw"; | |
4821 | goto ld; | |
4822 | case M_LWC0_AB: | |
4823 | s = "lwc0"; | |
bdaaa2e1 | 4824 | /* Itbl support may require additional care here. */ |
252b5132 RH |
4825 | coproc = 1; |
4826 | goto ld; | |
4827 | case M_LWC1_AB: | |
4828 | s = "lwc1"; | |
bdaaa2e1 | 4829 | /* Itbl support may require additional care here. */ |
252b5132 RH |
4830 | coproc = 1; |
4831 | goto ld; | |
4832 | case M_LWC2_AB: | |
4833 | s = "lwc2"; | |
bdaaa2e1 | 4834 | /* Itbl support may require additional care here. */ |
252b5132 RH |
4835 | coproc = 1; |
4836 | goto ld; | |
4837 | case M_LWC3_AB: | |
4838 | s = "lwc3"; | |
bdaaa2e1 | 4839 | /* Itbl support may require additional care here. */ |
252b5132 RH |
4840 | coproc = 1; |
4841 | goto ld; | |
4842 | case M_LWL_AB: | |
4843 | s = "lwl"; | |
4844 | lr = 1; | |
4845 | goto ld; | |
4846 | case M_LWR_AB: | |
4847 | s = "lwr"; | |
4848 | lr = 1; | |
4849 | goto ld; | |
4850 | case M_LDC1_AB: | |
ec68c924 | 4851 | if (mips_arch == CPU_R4650) |
252b5132 RH |
4852 | { |
4853 | as_bad (_("opcode not supported on this processor")); | |
4854 | return; | |
4855 | } | |
4856 | s = "ldc1"; | |
bdaaa2e1 | 4857 | /* Itbl support may require additional care here. */ |
252b5132 RH |
4858 | coproc = 1; |
4859 | goto ld; | |
4860 | case M_LDC2_AB: | |
4861 | s = "ldc2"; | |
bdaaa2e1 | 4862 | /* Itbl support may require additional care here. */ |
252b5132 RH |
4863 | coproc = 1; |
4864 | goto ld; | |
4865 | case M_LDC3_AB: | |
4866 | s = "ldc3"; | |
bdaaa2e1 | 4867 | /* Itbl support may require additional care here. */ |
252b5132 RH |
4868 | coproc = 1; |
4869 | goto ld; | |
4870 | case M_LDL_AB: | |
4871 | s = "ldl"; | |
4872 | lr = 1; | |
4873 | goto ld; | |
4874 | case M_LDR_AB: | |
4875 | s = "ldr"; | |
4876 | lr = 1; | |
4877 | goto ld; | |
4878 | case M_LL_AB: | |
4879 | s = "ll"; | |
4880 | goto ld; | |
4881 | case M_LLD_AB: | |
4882 | s = "lld"; | |
4883 | goto ld; | |
4884 | case M_LWU_AB: | |
4885 | s = "lwu"; | |
4886 | ld: | |
4887 | if (breg == treg || coproc || lr) | |
4888 | { | |
4889 | tempreg = AT; | |
4890 | used_at = 1; | |
4891 | } | |
4892 | else | |
4893 | { | |
4894 | tempreg = treg; | |
4895 | used_at = 0; | |
4896 | } | |
4897 | goto ld_st; | |
4898 | case M_SB_AB: | |
4899 | s = "sb"; | |
4900 | goto st; | |
4901 | case M_SH_AB: | |
4902 | s = "sh"; | |
4903 | goto st; | |
4904 | case M_SW_AB: | |
4905 | s = "sw"; | |
4906 | goto st; | |
4907 | case M_SWC0_AB: | |
4908 | s = "swc0"; | |
bdaaa2e1 | 4909 | /* Itbl support may require additional care here. */ |
252b5132 RH |
4910 | coproc = 1; |
4911 | goto st; | |
4912 | case M_SWC1_AB: | |
4913 | s = "swc1"; | |
bdaaa2e1 | 4914 | /* Itbl support may require additional care here. */ |
252b5132 RH |
4915 | coproc = 1; |
4916 | goto st; | |
4917 | case M_SWC2_AB: | |
4918 | s = "swc2"; | |
bdaaa2e1 | 4919 | /* Itbl support may require additional care here. */ |
252b5132 RH |
4920 | coproc = 1; |
4921 | goto st; | |
4922 | case M_SWC3_AB: | |
4923 | s = "swc3"; | |
bdaaa2e1 | 4924 | /* Itbl support may require additional care here. */ |
252b5132 RH |
4925 | coproc = 1; |
4926 | goto st; | |
4927 | case M_SWL_AB: | |
4928 | s = "swl"; | |
4929 | goto st; | |
4930 | case M_SWR_AB: | |
4931 | s = "swr"; | |
4932 | goto st; | |
4933 | case M_SC_AB: | |
4934 | s = "sc"; | |
4935 | goto st; | |
4936 | case M_SCD_AB: | |
4937 | s = "scd"; | |
4938 | goto st; | |
4939 | case M_SDC1_AB: | |
ec68c924 | 4940 | if (mips_arch == CPU_R4650) |
252b5132 RH |
4941 | { |
4942 | as_bad (_("opcode not supported on this processor")); | |
4943 | return; | |
4944 | } | |
4945 | s = "sdc1"; | |
4946 | coproc = 1; | |
bdaaa2e1 | 4947 | /* Itbl support may require additional care here. */ |
252b5132 RH |
4948 | goto st; |
4949 | case M_SDC2_AB: | |
4950 | s = "sdc2"; | |
bdaaa2e1 | 4951 | /* Itbl support may require additional care here. */ |
252b5132 RH |
4952 | coproc = 1; |
4953 | goto st; | |
4954 | case M_SDC3_AB: | |
4955 | s = "sdc3"; | |
bdaaa2e1 | 4956 | /* Itbl support may require additional care here. */ |
252b5132 RH |
4957 | coproc = 1; |
4958 | goto st; | |
4959 | case M_SDL_AB: | |
4960 | s = "sdl"; | |
4961 | goto st; | |
4962 | case M_SDR_AB: | |
4963 | s = "sdr"; | |
4964 | st: | |
4965 | tempreg = AT; | |
4966 | used_at = 1; | |
4967 | ld_st: | |
bdaaa2e1 | 4968 | /* Itbl support may require additional care here. */ |
252b5132 RH |
4969 | if (mask == M_LWC1_AB |
4970 | || mask == M_SWC1_AB | |
4971 | || mask == M_LDC1_AB | |
4972 | || mask == M_SDC1_AB | |
4973 | || mask == M_L_DAB | |
4974 | || mask == M_S_DAB) | |
4975 | fmt = "T,o(b)"; | |
4976 | else if (coproc) | |
4977 | fmt = "E,o(b)"; | |
4978 | else | |
4979 | fmt = "t,o(b)"; | |
4980 | ||
4981 | if (offset_expr.X_op != O_constant | |
4982 | && offset_expr.X_op != O_symbol) | |
4983 | { | |
4984 | as_bad (_("expression too complex")); | |
4985 | offset_expr.X_op = O_constant; | |
4986 | } | |
4987 | ||
4988 | /* A constant expression in PIC code can be handled just as it | |
4989 | is in non PIC code. */ | |
4990 | if (mips_pic == NO_PIC | |
4991 | || offset_expr.X_op == O_constant) | |
4992 | { | |
4993 | /* If this is a reference to a GP relative symbol, and there | |
4994 | is no base register, we want | |
4995 | <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL) | |
4996 | Otherwise, if there is no base register, we want | |
4997 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
4998 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
4999 | If we have a constant, we need two instructions anyhow, | |
5000 | so we always use the latter form. | |
5001 | ||
5002 | If we have a base register, and this is a reference to a | |
5003 | GP relative symbol, we want | |
5004 | addu $tempreg,$breg,$gp | |
5005 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL) | |
5006 | Otherwise we want | |
5007 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
5008 | addu $tempreg,$tempreg,$breg | |
5009 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
5010 | With a constant we always use the latter case. */ | |
5011 | if (breg == 0) | |
5012 | { | |
5013 | if ((valueT) offset_expr.X_add_number >= MAX_GPREL_OFFSET | |
5014 | || nopic_need_relax (offset_expr.X_add_symbol, 1)) | |
5015 | p = NULL; | |
5016 | else | |
5017 | { | |
5018 | frag_grow (20); | |
5019 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
5020 | treg, (int) BFD_RELOC_MIPS_GPREL, GP); | |
5021 | p = frag_var (rs_machine_dependent, 8, 0, | |
5022 | RELAX_ENCODE (4, 8, 0, 4, 0, | |
5023 | (mips_opts.warn_about_macros | |
5024 | || (used_at | |
5025 | && mips_opts.noat))), | |
5026 | offset_expr.X_add_symbol, (offsetT) 0, | |
5027 | (char *) NULL); | |
5028 | used_at = 0; | |
5029 | } | |
5030 | macro_build_lui (p, &icnt, &offset_expr, tempreg); | |
5031 | if (p != NULL) | |
5032 | p += 4; | |
5033 | macro_build (p, &icnt, &offset_expr, s, fmt, treg, | |
5034 | (int) BFD_RELOC_LO16, tempreg); | |
5035 | } | |
5036 | else | |
5037 | { | |
5038 | if ((valueT) offset_expr.X_add_number >= MAX_GPREL_OFFSET | |
5039 | || nopic_need_relax (offset_expr.X_add_symbol, 1)) | |
5040 | p = NULL; | |
5041 | else | |
5042 | { | |
5043 | frag_grow (28); | |
5044 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5045 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 5046 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
5047 | ? "addu" : "daddu"), |
5048 | "d,v,t", tempreg, breg, GP); | |
5049 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
5050 | treg, (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
5051 | p = frag_var (rs_machine_dependent, 12, 0, | |
5052 | RELAX_ENCODE (8, 12, 0, 8, 0, 0), | |
5053 | offset_expr.X_add_symbol, (offsetT) 0, | |
5054 | (char *) NULL); | |
5055 | } | |
5056 | macro_build_lui (p, &icnt, &offset_expr, tempreg); | |
5057 | if (p != NULL) | |
5058 | p += 4; | |
5059 | macro_build (p, &icnt, (expressionS *) NULL, | |
5060 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 5061 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
5062 | ? "addu" : "daddu"), |
5063 | "d,v,t", tempreg, tempreg, breg); | |
5064 | if (p != NULL) | |
5065 | p += 4; | |
5066 | macro_build (p, &icnt, &offset_expr, s, fmt, treg, | |
5067 | (int) BFD_RELOC_LO16, tempreg); | |
5068 | } | |
5069 | } | |
5070 | else if (mips_pic == SVR4_PIC && ! mips_big_got) | |
5071 | { | |
5072 | /* If this is a reference to an external symbol, we want | |
5073 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5074 | nop | |
5075 | <op> $treg,0($tempreg) | |
5076 | Otherwise we want | |
5077 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5078 | nop | |
5079 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
5080 | <op> $treg,0($tempreg) | |
5081 | If there is a base register, we add it to $tempreg before | |
5082 | the <op>. If there is a constant, we stick it in the | |
5083 | <op> instruction. We don't handle constants larger than | |
5084 | 16 bits, because we have no way to load the upper 16 bits | |
5085 | (actually, we could handle them for the subset of cases | |
5086 | in which we are not using $at). */ | |
5087 | assert (offset_expr.X_op == O_symbol); | |
5088 | expr1.X_add_number = offset_expr.X_add_number; | |
5089 | offset_expr.X_add_number = 0; | |
5090 | if (expr1.X_add_number < -0x8000 | |
5091 | || expr1.X_add_number >= 0x8000) | |
5092 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
5093 | frag_grow (20); | |
5094 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
5095 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 5096 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
5097 | ? "lw" : "ld"), |
5098 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, GP); | |
5099 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); | |
bdaaa2e1 | 5100 | p = frag_var (rs_machine_dependent, 4, 0, |
252b5132 RH |
5101 | RELAX_ENCODE (0, 4, -8, 0, 0, 0), |
5102 | offset_expr.X_add_symbol, (offsetT) 0, | |
5103 | (char *) NULL); | |
5104 | macro_build (p, &icnt, &offset_expr, | |
5105 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 5106 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
5107 | ? "addiu" : "daddiu"), |
5108 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); | |
5109 | if (breg != 0) | |
5110 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5111 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 5112 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
5113 | ? "addu" : "daddu"), |
5114 | "d,v,t", tempreg, tempreg, breg); | |
5115 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, treg, | |
5116 | (int) BFD_RELOC_LO16, tempreg); | |
5117 | } | |
5118 | else if (mips_pic == SVR4_PIC) | |
5119 | { | |
5120 | int gpdel; | |
5121 | ||
5122 | /* If this is a reference to an external symbol, we want | |
5123 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5124 | addu $tempreg,$tempreg,$gp | |
5125 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5126 | <op> $treg,0($tempreg) | |
5127 | Otherwise we want | |
5128 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5129 | nop | |
5130 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
5131 | <op> $treg,0($tempreg) | |
5132 | If there is a base register, we add it to $tempreg before | |
5133 | the <op>. If there is a constant, we stick it in the | |
5134 | <op> instruction. We don't handle constants larger than | |
5135 | 16 bits, because we have no way to load the upper 16 bits | |
5136 | (actually, we could handle them for the subset of cases | |
5137 | in which we are not using $at). */ | |
5138 | assert (offset_expr.X_op == O_symbol); | |
5139 | expr1.X_add_number = offset_expr.X_add_number; | |
5140 | offset_expr.X_add_number = 0; | |
5141 | if (expr1.X_add_number < -0x8000 | |
5142 | || expr1.X_add_number >= 0x8000) | |
5143 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
5144 | if (reg_needs_delay (GP)) | |
5145 | gpdel = 4; | |
5146 | else | |
5147 | gpdel = 0; | |
5148 | frag_grow (36); | |
5149 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
5150 | tempreg, (int) BFD_RELOC_MIPS_GOT_HI16); | |
5151 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5152 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 5153 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
5154 | ? "addu" : "daddu"), |
5155 | "d,v,t", tempreg, tempreg, GP); | |
5156 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
5157 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 5158 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
5159 | ? "lw" : "ld"), |
5160 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT_LO16, | |
5161 | tempreg); | |
5162 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, | |
5163 | RELAX_ENCODE (12, 12 + gpdel, gpdel, 8 + gpdel, 0, 0), | |
5164 | offset_expr.X_add_symbol, (offsetT) 0, (char *) NULL); | |
5165 | if (gpdel > 0) | |
5166 | { | |
5167 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
5168 | p += 4; | |
5169 | } | |
5170 | macro_build (p, &icnt, &offset_expr, | |
5171 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 5172 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
5173 | ? "lw" : "ld"), |
5174 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, GP); | |
5175 | p += 4; | |
5176 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
5177 | p += 4; | |
5178 | macro_build (p, &icnt, &offset_expr, | |
5179 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 5180 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
5181 | ? "addiu" : "daddiu"), |
5182 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); | |
5183 | if (breg != 0) | |
5184 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5185 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 5186 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
5187 | ? "addu" : "daddu"), |
5188 | "d,v,t", tempreg, tempreg, breg); | |
5189 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, treg, | |
5190 | (int) BFD_RELOC_LO16, tempreg); | |
5191 | } | |
5192 | else if (mips_pic == EMBEDDED_PIC) | |
5193 | { | |
5194 | /* If there is no base register, we want | |
5195 | <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL) | |
5196 | If there is a base register, we want | |
5197 | addu $tempreg,$breg,$gp | |
5198 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL) | |
5199 | */ | |
5200 | assert (offset_expr.X_op == O_symbol); | |
5201 | if (breg == 0) | |
5202 | { | |
5203 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
5204 | treg, (int) BFD_RELOC_MIPS_GPREL, GP); | |
5205 | used_at = 0; | |
5206 | } | |
5207 | else | |
5208 | { | |
5209 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5210 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 5211 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
5212 | ? "addu" : "daddu"), |
5213 | "d,v,t", tempreg, breg, GP); | |
5214 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
5215 | treg, (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
5216 | } | |
5217 | } | |
5218 | else | |
5219 | abort (); | |
5220 | ||
5221 | if (! used_at) | |
5222 | return; | |
5223 | ||
5224 | break; | |
5225 | ||
5226 | case M_LI: | |
5227 | case M_LI_S: | |
5228 | load_register (&icnt, treg, &imm_expr, 0); | |
5229 | return; | |
5230 | ||
5231 | case M_DLI: | |
5232 | load_register (&icnt, treg, &imm_expr, 1); | |
5233 | return; | |
5234 | ||
5235 | case M_LI_SS: | |
5236 | if (imm_expr.X_op == O_constant) | |
5237 | { | |
5238 | load_register (&icnt, AT, &imm_expr, 0); | |
5239 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5240 | "mtc1", "t,G", AT, treg); | |
5241 | break; | |
5242 | } | |
5243 | else | |
5244 | { | |
5245 | assert (offset_expr.X_op == O_symbol | |
5246 | && strcmp (segment_name (S_GET_SEGMENT | |
5247 | (offset_expr.X_add_symbol)), | |
5248 | ".lit4") == 0 | |
5249 | && offset_expr.X_add_number == 0); | |
5250 | macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)", | |
5251 | treg, (int) BFD_RELOC_MIPS_LITERAL, GP); | |
5252 | return; | |
5253 | } | |
5254 | ||
5255 | case M_LI_D: | |
5256 | /* If we have a constant in IMM_EXPR, then in mips3 mode it is | |
5257 | the entire value, and in mips1 mode it is the high order 32 | |
5258 | bits of the value and the low order 32 bits are either zero | |
5259 | or in offset_expr. */ | |
5260 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) | |
5261 | { | |
9ce8a5dd | 5262 | if (ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
5263 | load_register (&icnt, treg, &imm_expr, 1); |
5264 | else | |
5265 | { | |
5266 | int hreg, lreg; | |
5267 | ||
5268 | if (target_big_endian) | |
5269 | { | |
5270 | hreg = treg; | |
5271 | lreg = treg + 1; | |
5272 | } | |
5273 | else | |
5274 | { | |
5275 | hreg = treg + 1; | |
5276 | lreg = treg; | |
5277 | } | |
5278 | ||
5279 | if (hreg <= 31) | |
5280 | load_register (&icnt, hreg, &imm_expr, 0); | |
5281 | if (lreg <= 31) | |
5282 | { | |
5283 | if (offset_expr.X_op == O_absent) | |
5284 | macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", | |
5285 | lreg, 0); | |
5286 | else | |
5287 | { | |
5288 | assert (offset_expr.X_op == O_constant); | |
5289 | load_register (&icnt, lreg, &offset_expr, 0); | |
5290 | } | |
5291 | } | |
5292 | } | |
5293 | return; | |
5294 | } | |
5295 | ||
5296 | /* We know that sym is in the .rdata section. First we get the | |
5297 | upper 16 bits of the address. */ | |
5298 | if (mips_pic == NO_PIC) | |
5299 | { | |
5300 | /* FIXME: This won't work for a 64 bit address. */ | |
5301 | macro_build_lui ((char *) NULL, &icnt, &offset_expr, AT); | |
5302 | } | |
5303 | else if (mips_pic == SVR4_PIC) | |
5304 | { | |
5305 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
5306 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 5307 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
5308 | ? "lw" : "ld"), |
5309 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP); | |
5310 | } | |
5311 | else if (mips_pic == EMBEDDED_PIC) | |
5312 | { | |
5313 | /* For embedded PIC we pick up the entire address off $gp in | |
5314 | a single instruction. */ | |
5315 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
5316 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 5317 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
5318 | ? "addiu" : "daddiu"), |
5319 | "t,r,j", AT, GP, (int) BFD_RELOC_MIPS_GPREL); | |
5320 | offset_expr.X_op = O_constant; | |
5321 | offset_expr.X_add_number = 0; | |
5322 | } | |
5323 | else | |
5324 | abort (); | |
bdaaa2e1 | 5325 | |
252b5132 | 5326 | /* Now we load the register(s). */ |
9ce8a5dd | 5327 | if (ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
5328 | macro_build ((char *) NULL, &icnt, &offset_expr, "ld", "t,o(b)", |
5329 | treg, (int) BFD_RELOC_LO16, AT); | |
5330 | else | |
5331 | { | |
5332 | macro_build ((char *) NULL, &icnt, &offset_expr, "lw", "t,o(b)", | |
5333 | treg, (int) BFD_RELOC_LO16, AT); | |
5334 | if (treg != 31) | |
5335 | { | |
5336 | /* FIXME: How in the world do we deal with the possible | |
5337 | overflow here? */ | |
5338 | offset_expr.X_add_number += 4; | |
5339 | macro_build ((char *) NULL, &icnt, &offset_expr, "lw", "t,o(b)", | |
5340 | treg + 1, (int) BFD_RELOC_LO16, AT); | |
5341 | } | |
5342 | } | |
5343 | ||
5344 | /* To avoid confusion in tc_gen_reloc, we must ensure that this | |
5345 | does not become a variant frag. */ | |
5346 | frag_wane (frag_now); | |
5347 | frag_new (0); | |
5348 | ||
5349 | break; | |
5350 | ||
5351 | case M_LI_DD: | |
5352 | /* If we have a constant in IMM_EXPR, then in mips3 mode it is | |
5353 | the entire value, and in mips1 mode it is the high order 32 | |
5354 | bits of the value and the low order 32 bits are either zero | |
5355 | or in offset_expr. */ | |
5356 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) | |
5357 | { | |
9ce8a5dd GRK |
5358 | load_register (&icnt, AT, &imm_expr, ISA_HAS_64BIT_REGS (mips_opts.isa)); |
5359 | if (ISA_HAS_64BIT_REGS (mips_opts.isa)) | |
252b5132 RH |
5360 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
5361 | "dmtc1", "t,S", AT, treg); | |
5362 | else | |
5363 | { | |
5364 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5365 | "mtc1", "t,G", AT, treg + 1); | |
5366 | if (offset_expr.X_op == O_absent) | |
5367 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5368 | "mtc1", "t,G", 0, treg); | |
5369 | else | |
5370 | { | |
5371 | assert (offset_expr.X_op == O_constant); | |
5372 | load_register (&icnt, AT, &offset_expr, 0); | |
5373 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5374 | "mtc1", "t,G", AT, treg); | |
5375 | } | |
5376 | } | |
5377 | break; | |
5378 | } | |
5379 | ||
5380 | assert (offset_expr.X_op == O_symbol | |
5381 | && offset_expr.X_add_number == 0); | |
5382 | s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol)); | |
5383 | if (strcmp (s, ".lit8") == 0) | |
5384 | { | |
e7af610e | 5385 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 RH |
5386 | { |
5387 | macro_build ((char *) NULL, &icnt, &offset_expr, "ldc1", | |
5388 | "T,o(b)", treg, (int) BFD_RELOC_MIPS_LITERAL, GP); | |
5389 | return; | |
5390 | } | |
5391 | breg = GP; | |
5392 | r = BFD_RELOC_MIPS_LITERAL; | |
5393 | goto dob; | |
5394 | } | |
5395 | else | |
5396 | { | |
5397 | assert (strcmp (s, RDATA_SECTION_NAME) == 0); | |
5398 | if (mips_pic == SVR4_PIC) | |
5399 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
5400 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 5401 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
5402 | ? "lw" : "ld"), |
5403 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP); | |
5404 | else | |
5405 | { | |
5406 | /* FIXME: This won't work for a 64 bit address. */ | |
5407 | macro_build_lui ((char *) NULL, &icnt, &offset_expr, AT); | |
5408 | } | |
bdaaa2e1 | 5409 | |
e7af610e | 5410 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 RH |
5411 | { |
5412 | macro_build ((char *) NULL, &icnt, &offset_expr, "ldc1", | |
5413 | "T,o(b)", treg, (int) BFD_RELOC_LO16, AT); | |
5414 | ||
5415 | /* To avoid confusion in tc_gen_reloc, we must ensure | |
5416 | that this does not become a variant frag. */ | |
5417 | frag_wane (frag_now); | |
5418 | frag_new (0); | |
5419 | ||
5420 | break; | |
5421 | } | |
5422 | breg = AT; | |
5423 | r = BFD_RELOC_LO16; | |
5424 | goto dob; | |
5425 | } | |
5426 | ||
5427 | case M_L_DOB: | |
ec68c924 | 5428 | if (mips_arch == CPU_R4650) |
252b5132 RH |
5429 | { |
5430 | as_bad (_("opcode not supported on this processor")); | |
5431 | return; | |
5432 | } | |
5433 | /* Even on a big endian machine $fn comes before $fn+1. We have | |
5434 | to adjust when loading from memory. */ | |
5435 | r = BFD_RELOC_LO16; | |
5436 | dob: | |
e7af610e | 5437 | assert (mips_opts.isa == ISA_MIPS1); |
252b5132 RH |
5438 | macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)", |
5439 | target_big_endian ? treg + 1 : treg, | |
5440 | (int) r, breg); | |
5441 | /* FIXME: A possible overflow which I don't know how to deal | |
5442 | with. */ | |
5443 | offset_expr.X_add_number += 4; | |
5444 | macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)", | |
5445 | target_big_endian ? treg : treg + 1, | |
5446 | (int) r, breg); | |
5447 | ||
5448 | /* To avoid confusion in tc_gen_reloc, we must ensure that this | |
5449 | does not become a variant frag. */ | |
5450 | frag_wane (frag_now); | |
5451 | frag_new (0); | |
5452 | ||
5453 | if (breg != AT) | |
5454 | return; | |
5455 | break; | |
5456 | ||
5457 | case M_L_DAB: | |
5458 | /* | |
5459 | * The MIPS assembler seems to check for X_add_number not | |
5460 | * being double aligned and generating: | |
5461 | * lui at,%hi(foo+1) | |
5462 | * addu at,at,v1 | |
5463 | * addiu at,at,%lo(foo+1) | |
5464 | * lwc1 f2,0(at) | |
5465 | * lwc1 f3,4(at) | |
5466 | * But, the resulting address is the same after relocation so why | |
5467 | * generate the extra instruction? | |
5468 | */ | |
ec68c924 | 5469 | if (mips_arch == CPU_R4650) |
252b5132 RH |
5470 | { |
5471 | as_bad (_("opcode not supported on this processor")); | |
5472 | return; | |
5473 | } | |
bdaaa2e1 | 5474 | /* Itbl support may require additional care here. */ |
252b5132 | 5475 | coproc = 1; |
e7af610e | 5476 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 RH |
5477 | { |
5478 | s = "ldc1"; | |
5479 | goto ld; | |
5480 | } | |
5481 | ||
5482 | s = "lwc1"; | |
5483 | fmt = "T,o(b)"; | |
5484 | goto ldd_std; | |
5485 | ||
5486 | case M_S_DAB: | |
ec68c924 | 5487 | if (mips_arch == CPU_R4650) |
252b5132 RH |
5488 | { |
5489 | as_bad (_("opcode not supported on this processor")); | |
5490 | return; | |
5491 | } | |
5492 | ||
e7af610e | 5493 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 RH |
5494 | { |
5495 | s = "sdc1"; | |
5496 | goto st; | |
5497 | } | |
5498 | ||
5499 | s = "swc1"; | |
5500 | fmt = "T,o(b)"; | |
bdaaa2e1 | 5501 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5502 | coproc = 1; |
5503 | goto ldd_std; | |
5504 | ||
5505 | case M_LD_AB: | |
9ce8a5dd | 5506 | if (ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
5507 | { |
5508 | s = "ld"; | |
5509 | goto ld; | |
5510 | } | |
5511 | ||
5512 | s = "lw"; | |
5513 | fmt = "t,o(b)"; | |
5514 | goto ldd_std; | |
5515 | ||
5516 | case M_SD_AB: | |
9ce8a5dd | 5517 | if (ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
5518 | { |
5519 | s = "sd"; | |
5520 | goto st; | |
5521 | } | |
5522 | ||
5523 | s = "sw"; | |
5524 | fmt = "t,o(b)"; | |
5525 | ||
5526 | ldd_std: | |
5527 | if (offset_expr.X_op != O_symbol | |
5528 | && offset_expr.X_op != O_constant) | |
5529 | { | |
5530 | as_bad (_("expression too complex")); | |
5531 | offset_expr.X_op = O_constant; | |
5532 | } | |
5533 | ||
5534 | /* Even on a big endian machine $fn comes before $fn+1. We have | |
5535 | to adjust when loading from memory. We set coproc if we must | |
5536 | load $fn+1 first. */ | |
bdaaa2e1 | 5537 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5538 | if (! target_big_endian) |
5539 | coproc = 0; | |
5540 | ||
5541 | if (mips_pic == NO_PIC | |
5542 | || offset_expr.X_op == O_constant) | |
5543 | { | |
5544 | /* If this is a reference to a GP relative symbol, we want | |
5545 | <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL) | |
5546 | <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL) | |
5547 | If we have a base register, we use this | |
5548 | addu $at,$breg,$gp | |
5549 | <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL) | |
5550 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL) | |
5551 | If this is not a GP relative symbol, we want | |
5552 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
5553 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
5554 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
5555 | If there is a base register, we add it to $at after the | |
5556 | lui instruction. If there is a constant, we always use | |
5557 | the last case. */ | |
5558 | if ((valueT) offset_expr.X_add_number >= MAX_GPREL_OFFSET | |
5559 | || nopic_need_relax (offset_expr.X_add_symbol, 1)) | |
5560 | { | |
5561 | p = NULL; | |
5562 | used_at = 1; | |
5563 | } | |
5564 | else | |
5565 | { | |
5566 | int off; | |
5567 | ||
5568 | if (breg == 0) | |
5569 | { | |
5570 | frag_grow (28); | |
5571 | tempreg = GP; | |
5572 | off = 0; | |
5573 | used_at = 0; | |
5574 | } | |
5575 | else | |
5576 | { | |
5577 | frag_grow (36); | |
5578 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5579 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 5580 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
5581 | ? "addu" : "daddu"), |
5582 | "d,v,t", AT, breg, GP); | |
5583 | tempreg = AT; | |
5584 | off = 4; | |
5585 | used_at = 1; | |
5586 | } | |
5587 | ||
beae10d5 | 5588 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5589 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
5590 | coproc ? treg + 1 : treg, | |
5591 | (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
5592 | offset_expr.X_add_number += 4; | |
5593 | ||
5594 | /* Set mips_optimize to 2 to avoid inserting an | |
5595 | undesired nop. */ | |
5596 | hold_mips_optimize = mips_optimize; | |
5597 | mips_optimize = 2; | |
beae10d5 | 5598 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5599 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
5600 | coproc ? treg : treg + 1, | |
5601 | (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
5602 | mips_optimize = hold_mips_optimize; | |
5603 | ||
5604 | p = frag_var (rs_machine_dependent, 12 + off, 0, | |
5605 | RELAX_ENCODE (8 + off, 12 + off, 0, 4 + off, 1, | |
5606 | used_at && mips_opts.noat), | |
5607 | offset_expr.X_add_symbol, (offsetT) 0, | |
5608 | (char *) NULL); | |
5609 | ||
5610 | /* We just generated two relocs. When tc_gen_reloc | |
5611 | handles this case, it will skip the first reloc and | |
5612 | handle the second. The second reloc already has an | |
5613 | extra addend of 4, which we added above. We must | |
5614 | subtract it out, and then subtract another 4 to make | |
5615 | the first reloc come out right. The second reloc | |
5616 | will come out right because we are going to add 4 to | |
5617 | offset_expr when we build its instruction below. | |
5618 | ||
5619 | If we have a symbol, then we don't want to include | |
5620 | the offset, because it will wind up being included | |
5621 | when we generate the reloc. */ | |
5622 | ||
5623 | if (offset_expr.X_op == O_constant) | |
5624 | offset_expr.X_add_number -= 8; | |
5625 | else | |
5626 | { | |
5627 | offset_expr.X_add_number = -4; | |
5628 | offset_expr.X_op = O_constant; | |
5629 | } | |
5630 | } | |
5631 | macro_build_lui (p, &icnt, &offset_expr, AT); | |
5632 | if (p != NULL) | |
5633 | p += 4; | |
5634 | if (breg != 0) | |
5635 | { | |
5636 | macro_build (p, &icnt, (expressionS *) NULL, | |
5637 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 5638 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
5639 | ? "addu" : "daddu"), |
5640 | "d,v,t", AT, breg, AT); | |
5641 | if (p != NULL) | |
5642 | p += 4; | |
5643 | } | |
beae10d5 | 5644 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5645 | macro_build (p, &icnt, &offset_expr, s, fmt, |
5646 | coproc ? treg + 1 : treg, | |
5647 | (int) BFD_RELOC_LO16, AT); | |
5648 | if (p != NULL) | |
5649 | p += 4; | |
5650 | /* FIXME: How do we handle overflow here? */ | |
5651 | offset_expr.X_add_number += 4; | |
beae10d5 | 5652 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5653 | macro_build (p, &icnt, &offset_expr, s, fmt, |
5654 | coproc ? treg : treg + 1, | |
5655 | (int) BFD_RELOC_LO16, AT); | |
bdaaa2e1 | 5656 | } |
252b5132 RH |
5657 | else if (mips_pic == SVR4_PIC && ! mips_big_got) |
5658 | { | |
5659 | int off; | |
5660 | ||
5661 | /* If this is a reference to an external symbol, we want | |
5662 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5663 | nop | |
5664 | <op> $treg,0($at) | |
5665 | <op> $treg+1,4($at) | |
5666 | Otherwise we want | |
5667 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5668 | nop | |
5669 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
5670 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
5671 | If there is a base register we add it to $at before the | |
5672 | lwc1 instructions. If there is a constant we include it | |
5673 | in the lwc1 instructions. */ | |
5674 | used_at = 1; | |
5675 | expr1.X_add_number = offset_expr.X_add_number; | |
5676 | offset_expr.X_add_number = 0; | |
5677 | if (expr1.X_add_number < -0x8000 | |
5678 | || expr1.X_add_number >= 0x8000 - 4) | |
5679 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
5680 | if (breg == 0) | |
5681 | off = 0; | |
5682 | else | |
5683 | off = 4; | |
5684 | frag_grow (24 + off); | |
5685 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
5686 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 5687 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
5688 | ? "lw" : "ld"), |
5689 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP); | |
5690 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); | |
5691 | if (breg != 0) | |
5692 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5693 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 5694 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
5695 | ? "addu" : "daddu"), |
5696 | "d,v,t", AT, breg, AT); | |
beae10d5 | 5697 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5698 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, |
5699 | coproc ? treg + 1 : treg, | |
5700 | (int) BFD_RELOC_LO16, AT); | |
5701 | expr1.X_add_number += 4; | |
5702 | ||
5703 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
5704 | nop. */ | |
5705 | hold_mips_optimize = mips_optimize; | |
5706 | mips_optimize = 2; | |
beae10d5 | 5707 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5708 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, |
5709 | coproc ? treg : treg + 1, | |
5710 | (int) BFD_RELOC_LO16, AT); | |
5711 | mips_optimize = hold_mips_optimize; | |
5712 | ||
5713 | (void) frag_var (rs_machine_dependent, 0, 0, | |
5714 | RELAX_ENCODE (0, 0, -16 - off, -8, 1, 0), | |
5715 | offset_expr.X_add_symbol, (offsetT) 0, | |
5716 | (char *) NULL); | |
5717 | } | |
5718 | else if (mips_pic == SVR4_PIC) | |
5719 | { | |
5720 | int gpdel, off; | |
5721 | ||
5722 | /* If this is a reference to an external symbol, we want | |
5723 | lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5724 | addu $at,$at,$gp | |
5725 | lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16) | |
5726 | nop | |
5727 | <op> $treg,0($at) | |
5728 | <op> $treg+1,4($at) | |
5729 | Otherwise we want | |
5730 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5731 | nop | |
5732 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
5733 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
5734 | If there is a base register we add it to $at before the | |
5735 | lwc1 instructions. If there is a constant we include it | |
5736 | in the lwc1 instructions. */ | |
5737 | used_at = 1; | |
5738 | expr1.X_add_number = offset_expr.X_add_number; | |
5739 | offset_expr.X_add_number = 0; | |
5740 | if (expr1.X_add_number < -0x8000 | |
5741 | || expr1.X_add_number >= 0x8000 - 4) | |
5742 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
5743 | if (reg_needs_delay (GP)) | |
5744 | gpdel = 4; | |
5745 | else | |
5746 | gpdel = 0; | |
5747 | if (breg == 0) | |
5748 | off = 0; | |
5749 | else | |
5750 | off = 4; | |
5751 | frag_grow (56); | |
5752 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
5753 | AT, (int) BFD_RELOC_MIPS_GOT_HI16); | |
5754 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5755 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 5756 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
5757 | ? "addu" : "daddu"), |
5758 | "d,v,t", AT, AT, GP); | |
5759 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
5760 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 5761 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
5762 | ? "lw" : "ld"), |
5763 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT_LO16, AT); | |
5764 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); | |
5765 | if (breg != 0) | |
5766 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5767 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 5768 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
5769 | ? "addu" : "daddu"), |
5770 | "d,v,t", AT, breg, AT); | |
beae10d5 | 5771 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5772 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, |
5773 | coproc ? treg + 1 : treg, | |
5774 | (int) BFD_RELOC_LO16, AT); | |
5775 | expr1.X_add_number += 4; | |
5776 | ||
5777 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
5778 | nop. */ | |
5779 | hold_mips_optimize = mips_optimize; | |
5780 | mips_optimize = 2; | |
beae10d5 | 5781 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5782 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, |
5783 | coproc ? treg : treg + 1, | |
5784 | (int) BFD_RELOC_LO16, AT); | |
5785 | mips_optimize = hold_mips_optimize; | |
5786 | expr1.X_add_number -= 4; | |
5787 | ||
5788 | p = frag_var (rs_machine_dependent, 16 + gpdel + off, 0, | |
5789 | RELAX_ENCODE (24 + off, 16 + gpdel + off, gpdel, | |
5790 | 8 + gpdel + off, 1, 0), | |
5791 | offset_expr.X_add_symbol, (offsetT) 0, | |
5792 | (char *) NULL); | |
5793 | if (gpdel > 0) | |
5794 | { | |
5795 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
5796 | p += 4; | |
5797 | } | |
5798 | macro_build (p, &icnt, &offset_expr, | |
5799 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 5800 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
5801 | ? "lw" : "ld"), |
5802 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP); | |
5803 | p += 4; | |
5804 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
5805 | p += 4; | |
5806 | if (breg != 0) | |
5807 | { | |
5808 | macro_build (p, &icnt, (expressionS *) NULL, | |
5809 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 5810 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
5811 | ? "addu" : "daddu"), |
5812 | "d,v,t", AT, breg, AT); | |
5813 | p += 4; | |
5814 | } | |
beae10d5 | 5815 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5816 | macro_build (p, &icnt, &expr1, s, fmt, |
5817 | coproc ? treg + 1 : treg, | |
5818 | (int) BFD_RELOC_LO16, AT); | |
5819 | p += 4; | |
5820 | expr1.X_add_number += 4; | |
5821 | ||
5822 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
5823 | nop. */ | |
5824 | hold_mips_optimize = mips_optimize; | |
5825 | mips_optimize = 2; | |
beae10d5 | 5826 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5827 | macro_build (p, &icnt, &expr1, s, fmt, |
5828 | coproc ? treg : treg + 1, | |
5829 | (int) BFD_RELOC_LO16, AT); | |
5830 | mips_optimize = hold_mips_optimize; | |
5831 | } | |
5832 | else if (mips_pic == EMBEDDED_PIC) | |
5833 | { | |
5834 | /* If there is no base register, we use | |
5835 | <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL) | |
5836 | <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL) | |
5837 | If we have a base register, we use | |
5838 | addu $at,$breg,$gp | |
5839 | <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL) | |
5840 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL) | |
5841 | */ | |
5842 | if (breg == 0) | |
5843 | { | |
5844 | tempreg = GP; | |
5845 | used_at = 0; | |
5846 | } | |
5847 | else | |
5848 | { | |
5849 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5850 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 5851 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
5852 | ? "addu" : "daddu"), |
5853 | "d,v,t", AT, breg, GP); | |
5854 | tempreg = AT; | |
5855 | used_at = 1; | |
5856 | } | |
5857 | ||
beae10d5 | 5858 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5859 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
5860 | coproc ? treg + 1 : treg, | |
5861 | (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
5862 | offset_expr.X_add_number += 4; | |
beae10d5 | 5863 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5864 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
5865 | coproc ? treg : treg + 1, | |
5866 | (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
5867 | } | |
5868 | else | |
5869 | abort (); | |
5870 | ||
5871 | if (! used_at) | |
5872 | return; | |
5873 | ||
5874 | break; | |
5875 | ||
5876 | case M_LD_OB: | |
5877 | s = "lw"; | |
5878 | goto sd_ob; | |
5879 | case M_SD_OB: | |
5880 | s = "sw"; | |
5881 | sd_ob: | |
bdaaa2e1 | 5882 | assert (bfd_arch_bits_per_address (stdoutput) == 32 |
9ce8a5dd | 5883 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)); |
252b5132 RH |
5884 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, |
5885 | (int) BFD_RELOC_LO16, breg); | |
5886 | offset_expr.X_add_number += 4; | |
5887 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg + 1, | |
5888 | (int) BFD_RELOC_LO16, breg); | |
5889 | return; | |
5890 | ||
5891 | /* New code added to support COPZ instructions. | |
5892 | This code builds table entries out of the macros in mip_opcodes. | |
5893 | R4000 uses interlocks to handle coproc delays. | |
5894 | Other chips (like the R3000) require nops to be inserted for delays. | |
5895 | ||
5896 | FIXME: Currently, we require that the user handle delays. | |
5897 | In order to fill delay slots for non-interlocked chips, | |
5898 | we must have a way to specify delays based on the coprocessor. | |
5899 | Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc. | |
5900 | What are the side-effects of the cop instruction? | |
5901 | What cache support might we have and what are its effects? | |
5902 | Both coprocessor & memory require delays. how long??? | |
bdaaa2e1 | 5903 | What registers are read/set/modified? |
252b5132 RH |
5904 | |
5905 | If an itbl is provided to interpret cop instructions, | |
bdaaa2e1 | 5906 | this knowledge can be encoded in the itbl spec. */ |
252b5132 RH |
5907 | |
5908 | case M_COP0: | |
5909 | s = "c0"; | |
5910 | goto copz; | |
5911 | case M_COP1: | |
5912 | s = "c1"; | |
5913 | goto copz; | |
5914 | case M_COP2: | |
5915 | s = "c2"; | |
5916 | goto copz; | |
5917 | case M_COP3: | |
5918 | s = "c3"; | |
5919 | copz: | |
5920 | /* For now we just do C (same as Cz). The parameter will be | |
5921 | stored in insn_opcode by mips_ip. */ | |
5922 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "C", | |
5923 | ip->insn_opcode); | |
5924 | return; | |
5925 | ||
5926 | #ifdef LOSING_COMPILER | |
5927 | default: | |
5928 | /* Try and see if this is a new itbl instruction. | |
5929 | This code builds table entries out of the macros in mip_opcodes. | |
5930 | FIXME: For now we just assemble the expression and pass it's | |
5931 | value along as a 32-bit immediate. | |
bdaaa2e1 | 5932 | We may want to have the assembler assemble this value, |
252b5132 RH |
5933 | so that we gain the assembler's knowledge of delay slots, |
5934 | symbols, etc. | |
5935 | Would it be more efficient to use mask (id) here? */ | |
bdaaa2e1 | 5936 | if (itbl_have_entries |
252b5132 | 5937 | && (immed_expr = itbl_assemble (ip->insn_mo->name, ""))) |
beae10d5 | 5938 | { |
252b5132 RH |
5939 | s = ip->insn_mo->name; |
5940 | s2 = "cop3"; | |
5941 | coproc = ITBL_DECODE_PNUM (immed_expr);; | |
5942 | macro_build ((char *) NULL, &icnt, &immed_expr, s, "C"); | |
5943 | return; | |
beae10d5 | 5944 | } |
252b5132 RH |
5945 | macro2 (ip); |
5946 | return; | |
5947 | } | |
5948 | if (mips_opts.noat) | |
5949 | as_warn (_("Macro used $at after \".set noat\"")); | |
5950 | } | |
bdaaa2e1 | 5951 | |
252b5132 RH |
5952 | static void |
5953 | macro2 (ip) | |
5954 | struct mips_cl_insn *ip; | |
5955 | { | |
5956 | register int treg, sreg, dreg, breg; | |
5957 | int tempreg; | |
5958 | int mask; | |
5959 | int icnt = 0; | |
5960 | int used_at; | |
5961 | expressionS expr1; | |
5962 | const char *s; | |
5963 | const char *s2; | |
5964 | const char *fmt; | |
5965 | int likely = 0; | |
5966 | int dbl = 0; | |
5967 | int coproc = 0; | |
5968 | int lr = 0; | |
5969 | int imm = 0; | |
5970 | int off; | |
5971 | offsetT maxnum; | |
5972 | bfd_reloc_code_real_type r; | |
5973 | char *p; | |
bdaaa2e1 | 5974 | |
252b5132 RH |
5975 | treg = (ip->insn_opcode >> 16) & 0x1f; |
5976 | dreg = (ip->insn_opcode >> 11) & 0x1f; | |
5977 | sreg = breg = (ip->insn_opcode >> 21) & 0x1f; | |
5978 | mask = ip->insn_mo->mask; | |
bdaaa2e1 | 5979 | |
252b5132 RH |
5980 | expr1.X_op = O_constant; |
5981 | expr1.X_op_symbol = NULL; | |
5982 | expr1.X_add_symbol = NULL; | |
5983 | expr1.X_add_number = 1; | |
bdaaa2e1 | 5984 | |
252b5132 RH |
5985 | switch (mask) |
5986 | { | |
5987 | #endif /* LOSING_COMPILER */ | |
5988 | ||
5989 | case M_DMUL: | |
5990 | dbl = 1; | |
5991 | case M_MUL: | |
5992 | macro_build ((char *) NULL, &icnt, NULL, | |
5993 | dbl ? "dmultu" : "multu", | |
5994 | "s,t", sreg, treg); | |
5995 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); | |
5996 | return; | |
5997 | ||
5998 | case M_DMUL_I: | |
5999 | dbl = 1; | |
6000 | case M_MUL_I: | |
6001 | /* The MIPS assembler some times generates shifts and adds. I'm | |
6002 | not trying to be that fancy. GCC should do this for us | |
6003 | anyway. */ | |
6004 | load_register (&icnt, AT, &imm_expr, dbl); | |
6005 | macro_build ((char *) NULL, &icnt, NULL, | |
6006 | dbl ? "dmult" : "mult", | |
6007 | "s,t", sreg, AT); | |
6008 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); | |
6009 | break; | |
6010 | ||
6011 | case M_DMULO_I: | |
6012 | dbl = 1; | |
6013 | case M_MULO_I: | |
6014 | imm = 1; | |
6015 | goto do_mulo; | |
6016 | ||
6017 | case M_DMULO: | |
6018 | dbl = 1; | |
6019 | case M_MULO: | |
6020 | do_mulo: | |
6021 | mips_emit_delays (true); | |
6022 | ++mips_opts.noreorder; | |
6023 | mips_any_noreorder = 1; | |
6024 | if (imm) | |
6025 | load_register (&icnt, AT, &imm_expr, dbl); | |
6026 | macro_build ((char *) NULL, &icnt, NULL, | |
6027 | dbl ? "dmult" : "mult", | |
6028 | "s,t", sreg, imm ? AT : treg); | |
6029 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); | |
6030 | macro_build ((char *) NULL, &icnt, NULL, | |
6031 | dbl ? "dsra32" : "sra", | |
6032 | "d,w,<", dreg, dreg, 31); | |
6033 | macro_build ((char *) NULL, &icnt, NULL, "mfhi", "d", AT); | |
6034 | if (mips_trap) | |
6035 | macro_build ((char *) NULL, &icnt, NULL, "tne", "s,t", dreg, AT); | |
6036 | else | |
6037 | { | |
6038 | expr1.X_add_number = 8; | |
6039 | macro_build ((char *) NULL, &icnt, &expr1, "beq", "s,t,p", dreg, AT); | |
6040 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); | |
beae10d5 | 6041 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 6); |
252b5132 RH |
6042 | } |
6043 | --mips_opts.noreorder; | |
6044 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); | |
6045 | break; | |
6046 | ||
6047 | case M_DMULOU_I: | |
6048 | dbl = 1; | |
6049 | case M_MULOU_I: | |
6050 | imm = 1; | |
6051 | goto do_mulou; | |
6052 | ||
6053 | case M_DMULOU: | |
6054 | dbl = 1; | |
6055 | case M_MULOU: | |
6056 | do_mulou: | |
6057 | mips_emit_delays (true); | |
6058 | ++mips_opts.noreorder; | |
6059 | mips_any_noreorder = 1; | |
6060 | if (imm) | |
6061 | load_register (&icnt, AT, &imm_expr, dbl); | |
6062 | macro_build ((char *) NULL, &icnt, NULL, | |
6063 | dbl ? "dmultu" : "multu", | |
6064 | "s,t", sreg, imm ? AT : treg); | |
6065 | macro_build ((char *) NULL, &icnt, NULL, "mfhi", "d", AT); | |
6066 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); | |
6067 | if (mips_trap) | |
6068 | macro_build ((char *) NULL, &icnt, NULL, "tne", "s,t", AT, 0); | |
6069 | else | |
6070 | { | |
6071 | expr1.X_add_number = 8; | |
6072 | macro_build ((char *) NULL, &icnt, &expr1, "beq", "s,t,p", AT, 0); | |
6073 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); | |
beae10d5 | 6074 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 6); |
252b5132 RH |
6075 | } |
6076 | --mips_opts.noreorder; | |
6077 | break; | |
6078 | ||
6079 | case M_ROL: | |
6080 | macro_build ((char *) NULL, &icnt, NULL, "subu", "d,v,t", AT, 0, treg); | |
6081 | macro_build ((char *) NULL, &icnt, NULL, "srlv", "d,t,s", AT, sreg, AT); | |
6082 | macro_build ((char *) NULL, &icnt, NULL, "sllv", "d,t,s", dreg, sreg, | |
6083 | treg); | |
6084 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT); | |
6085 | break; | |
6086 | ||
6087 | case M_ROL_I: | |
6088 | if (imm_expr.X_op != O_constant) | |
6089 | as_bad (_("rotate count too large")); | |
6090 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", AT, sreg, | |
6091 | (int) (imm_expr.X_add_number & 0x1f)); | |
6092 | macro_build ((char *) NULL, &icnt, NULL, "srl", "d,w,<", dreg, sreg, | |
6093 | (int) ((0 - imm_expr.X_add_number) & 0x1f)); | |
6094 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT); | |
6095 | break; | |
6096 | ||
6097 | case M_ROR: | |
6098 | macro_build ((char *) NULL, &icnt, NULL, "subu", "d,v,t", AT, 0, treg); | |
6099 | macro_build ((char *) NULL, &icnt, NULL, "sllv", "d,t,s", AT, sreg, AT); | |
6100 | macro_build ((char *) NULL, &icnt, NULL, "srlv", "d,t,s", dreg, sreg, | |
6101 | treg); | |
6102 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT); | |
6103 | break; | |
6104 | ||
6105 | case M_ROR_I: | |
6106 | if (imm_expr.X_op != O_constant) | |
6107 | as_bad (_("rotate count too large")); | |
6108 | macro_build ((char *) NULL, &icnt, NULL, "srl", "d,w,<", AT, sreg, | |
6109 | (int) (imm_expr.X_add_number & 0x1f)); | |
6110 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", dreg, sreg, | |
6111 | (int) ((0 - imm_expr.X_add_number) & 0x1f)); | |
6112 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT); | |
6113 | break; | |
6114 | ||
6115 | case M_S_DOB: | |
ec68c924 | 6116 | if (mips_arch == CPU_R4650) |
252b5132 RH |
6117 | { |
6118 | as_bad (_("opcode not supported on this processor")); | |
6119 | return; | |
6120 | } | |
e7af610e | 6121 | assert (mips_opts.isa == ISA_MIPS1); |
252b5132 RH |
6122 | /* Even on a big endian machine $fn comes before $fn+1. We have |
6123 | to adjust when storing to memory. */ | |
6124 | macro_build ((char *) NULL, &icnt, &offset_expr, "swc1", "T,o(b)", | |
6125 | target_big_endian ? treg + 1 : treg, | |
6126 | (int) BFD_RELOC_LO16, breg); | |
6127 | offset_expr.X_add_number += 4; | |
6128 | macro_build ((char *) NULL, &icnt, &offset_expr, "swc1", "T,o(b)", | |
6129 | target_big_endian ? treg : treg + 1, | |
6130 | (int) BFD_RELOC_LO16, breg); | |
6131 | return; | |
6132 | ||
6133 | case M_SEQ: | |
6134 | if (sreg == 0) | |
6135 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, | |
6136 | treg, (int) BFD_RELOC_LO16); | |
6137 | else if (treg == 0) | |
6138 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, | |
6139 | sreg, (int) BFD_RELOC_LO16); | |
6140 | else | |
6141 | { | |
6142 | macro_build ((char *) NULL, &icnt, NULL, "xor", "d,v,t", dreg, | |
6143 | sreg, treg); | |
6144 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, | |
6145 | dreg, (int) BFD_RELOC_LO16); | |
6146 | } | |
6147 | return; | |
6148 | ||
6149 | case M_SEQ_I: | |
6150 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
6151 | { | |
6152 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, | |
6153 | sreg, (int) BFD_RELOC_LO16); | |
6154 | return; | |
6155 | } | |
6156 | if (sreg == 0) | |
6157 | { | |
6158 | as_warn (_("Instruction %s: result is always false"), | |
6159 | ip->insn_mo->name); | |
6160 | macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, 0); | |
6161 | return; | |
6162 | } | |
6163 | if (imm_expr.X_op == O_constant | |
6164 | && imm_expr.X_add_number >= 0 | |
6165 | && imm_expr.X_add_number < 0x10000) | |
6166 | { | |
6167 | macro_build ((char *) NULL, &icnt, &imm_expr, "xori", "t,r,i", dreg, | |
6168 | sreg, (int) BFD_RELOC_LO16); | |
6169 | used_at = 0; | |
6170 | } | |
6171 | else if (imm_expr.X_op == O_constant | |
6172 | && imm_expr.X_add_number > -0x8000 | |
6173 | && imm_expr.X_add_number < 0) | |
6174 | { | |
6175 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
6176 | macro_build ((char *) NULL, &icnt, &imm_expr, | |
6177 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 6178 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
6179 | ? "addiu" : "daddiu"), |
6180 | "t,r,j", dreg, sreg, | |
6181 | (int) BFD_RELOC_LO16); | |
6182 | used_at = 0; | |
6183 | } | |
6184 | else | |
6185 | { | |
6186 | load_register (&icnt, AT, &imm_expr, 0); | |
6187 | macro_build ((char *) NULL, &icnt, NULL, "xor", "d,v,t", dreg, | |
6188 | sreg, AT); | |
6189 | used_at = 1; | |
6190 | } | |
6191 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, dreg, | |
6192 | (int) BFD_RELOC_LO16); | |
6193 | if (used_at) | |
6194 | break; | |
6195 | return; | |
6196 | ||
6197 | case M_SGE: /* sreg >= treg <==> not (sreg < treg) */ | |
6198 | s = "slt"; | |
6199 | goto sge; | |
6200 | case M_SGEU: | |
6201 | s = "sltu"; | |
6202 | sge: | |
6203 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, sreg, treg); | |
6204 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, | |
6205 | (int) BFD_RELOC_LO16); | |
6206 | return; | |
6207 | ||
6208 | case M_SGE_I: /* sreg >= I <==> not (sreg < I) */ | |
6209 | case M_SGEU_I: | |
6210 | if (imm_expr.X_op == O_constant | |
6211 | && imm_expr.X_add_number >= -0x8000 | |
6212 | && imm_expr.X_add_number < 0x8000) | |
6213 | { | |
6214 | macro_build ((char *) NULL, &icnt, &imm_expr, | |
6215 | mask == M_SGE_I ? "slti" : "sltiu", | |
6216 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); | |
6217 | used_at = 0; | |
6218 | } | |
6219 | else | |
6220 | { | |
6221 | load_register (&icnt, AT, &imm_expr, 0); | |
6222 | macro_build ((char *) NULL, &icnt, NULL, | |
6223 | mask == M_SGE_I ? "slt" : "sltu", | |
6224 | "d,v,t", dreg, sreg, AT); | |
6225 | used_at = 1; | |
6226 | } | |
6227 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, | |
6228 | (int) BFD_RELOC_LO16); | |
6229 | if (used_at) | |
6230 | break; | |
6231 | return; | |
6232 | ||
6233 | case M_SGT: /* sreg > treg <==> treg < sreg */ | |
6234 | s = "slt"; | |
6235 | goto sgt; | |
6236 | case M_SGTU: | |
6237 | s = "sltu"; | |
6238 | sgt: | |
6239 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, treg, sreg); | |
6240 | return; | |
6241 | ||
6242 | case M_SGT_I: /* sreg > I <==> I < sreg */ | |
6243 | s = "slt"; | |
6244 | goto sgti; | |
6245 | case M_SGTU_I: | |
6246 | s = "sltu"; | |
6247 | sgti: | |
6248 | load_register (&icnt, AT, &imm_expr, 0); | |
6249 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, AT, sreg); | |
6250 | break; | |
6251 | ||
6252 | case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */ | |
6253 | s = "slt"; | |
6254 | goto sle; | |
6255 | case M_SLEU: | |
6256 | s = "sltu"; | |
6257 | sle: | |
6258 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, treg, sreg); | |
6259 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, | |
6260 | (int) BFD_RELOC_LO16); | |
6261 | return; | |
6262 | ||
6263 | case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */ | |
6264 | s = "slt"; | |
6265 | goto slei; | |
6266 | case M_SLEU_I: | |
6267 | s = "sltu"; | |
6268 | slei: | |
6269 | load_register (&icnt, AT, &imm_expr, 0); | |
6270 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, AT, sreg); | |
6271 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, | |
6272 | (int) BFD_RELOC_LO16); | |
6273 | break; | |
6274 | ||
6275 | case M_SLT_I: | |
6276 | if (imm_expr.X_op == O_constant | |
6277 | && imm_expr.X_add_number >= -0x8000 | |
6278 | && imm_expr.X_add_number < 0x8000) | |
6279 | { | |
6280 | macro_build ((char *) NULL, &icnt, &imm_expr, "slti", "t,r,j", | |
6281 | dreg, sreg, (int) BFD_RELOC_LO16); | |
6282 | return; | |
6283 | } | |
6284 | load_register (&icnt, AT, &imm_expr, 0); | |
6285 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", dreg, sreg, AT); | |
6286 | break; | |
6287 | ||
6288 | case M_SLTU_I: | |
6289 | if (imm_expr.X_op == O_constant | |
6290 | && imm_expr.X_add_number >= -0x8000 | |
6291 | && imm_expr.X_add_number < 0x8000) | |
6292 | { | |
6293 | macro_build ((char *) NULL, &icnt, &imm_expr, "sltiu", "t,r,j", | |
6294 | dreg, sreg, (int) BFD_RELOC_LO16); | |
6295 | return; | |
6296 | } | |
6297 | load_register (&icnt, AT, &imm_expr, 0); | |
6298 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, sreg, | |
6299 | AT); | |
6300 | break; | |
6301 | ||
6302 | case M_SNE: | |
6303 | if (sreg == 0) | |
6304 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, | |
6305 | treg); | |
6306 | else if (treg == 0) | |
6307 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, | |
6308 | sreg); | |
6309 | else | |
6310 | { | |
6311 | macro_build ((char *) NULL, &icnt, NULL, "xor", "d,v,t", dreg, | |
6312 | sreg, treg); | |
6313 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, | |
6314 | dreg); | |
6315 | } | |
6316 | return; | |
6317 | ||
6318 | case M_SNE_I: | |
6319 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
6320 | { | |
6321 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, | |
6322 | sreg); | |
6323 | return; | |
6324 | } | |
6325 | if (sreg == 0) | |
6326 | { | |
6327 | as_warn (_("Instruction %s: result is always true"), | |
6328 | ip->insn_mo->name); | |
6329 | macro_build ((char *) NULL, &icnt, &expr1, | |
6330 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 6331 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
6332 | ? "addiu" : "daddiu"), |
6333 | "t,r,j", dreg, 0, (int) BFD_RELOC_LO16); | |
6334 | return; | |
6335 | } | |
6336 | if (imm_expr.X_op == O_constant | |
6337 | && imm_expr.X_add_number >= 0 | |
6338 | && imm_expr.X_add_number < 0x10000) | |
6339 | { | |
6340 | macro_build ((char *) NULL, &icnt, &imm_expr, "xori", "t,r,i", | |
6341 | dreg, sreg, (int) BFD_RELOC_LO16); | |
6342 | used_at = 0; | |
6343 | } | |
6344 | else if (imm_expr.X_op == O_constant | |
6345 | && imm_expr.X_add_number > -0x8000 | |
6346 | && imm_expr.X_add_number < 0) | |
6347 | { | |
6348 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
6349 | macro_build ((char *) NULL, &icnt, &imm_expr, | |
6350 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 6351 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
6352 | ? "addiu" : "daddiu"), |
6353 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); | |
6354 | used_at = 0; | |
6355 | } | |
6356 | else | |
6357 | { | |
6358 | load_register (&icnt, AT, &imm_expr, 0); | |
6359 | macro_build ((char *) NULL, &icnt, NULL, "xor", "d,v,t", dreg, | |
6360 | sreg, AT); | |
6361 | used_at = 1; | |
6362 | } | |
6363 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, dreg); | |
6364 | if (used_at) | |
6365 | break; | |
6366 | return; | |
6367 | ||
6368 | case M_DSUB_I: | |
6369 | dbl = 1; | |
6370 | case M_SUB_I: | |
6371 | if (imm_expr.X_op == O_constant | |
6372 | && imm_expr.X_add_number > -0x8000 | |
6373 | && imm_expr.X_add_number <= 0x8000) | |
6374 | { | |
6375 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
6376 | macro_build ((char *) NULL, &icnt, &imm_expr, | |
6377 | dbl ? "daddi" : "addi", | |
6378 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); | |
6379 | return; | |
6380 | } | |
6381 | load_register (&icnt, AT, &imm_expr, dbl); | |
6382 | macro_build ((char *) NULL, &icnt, NULL, | |
6383 | dbl ? "dsub" : "sub", | |
6384 | "d,v,t", dreg, sreg, AT); | |
6385 | break; | |
6386 | ||
6387 | case M_DSUBU_I: | |
6388 | dbl = 1; | |
6389 | case M_SUBU_I: | |
6390 | if (imm_expr.X_op == O_constant | |
6391 | && imm_expr.X_add_number > -0x8000 | |
6392 | && imm_expr.X_add_number <= 0x8000) | |
6393 | { | |
6394 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
6395 | macro_build ((char *) NULL, &icnt, &imm_expr, | |
6396 | dbl ? "daddiu" : "addiu", | |
6397 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); | |
6398 | return; | |
6399 | } | |
6400 | load_register (&icnt, AT, &imm_expr, dbl); | |
6401 | macro_build ((char *) NULL, &icnt, NULL, | |
6402 | dbl ? "dsubu" : "subu", | |
6403 | "d,v,t", dreg, sreg, AT); | |
6404 | break; | |
6405 | ||
6406 | case M_TEQ_I: | |
6407 | s = "teq"; | |
6408 | goto trap; | |
6409 | case M_TGE_I: | |
6410 | s = "tge"; | |
6411 | goto trap; | |
6412 | case M_TGEU_I: | |
6413 | s = "tgeu"; | |
6414 | goto trap; | |
6415 | case M_TLT_I: | |
6416 | s = "tlt"; | |
6417 | goto trap; | |
6418 | case M_TLTU_I: | |
6419 | s = "tltu"; | |
6420 | goto trap; | |
6421 | case M_TNE_I: | |
6422 | s = "tne"; | |
6423 | trap: | |
6424 | load_register (&icnt, AT, &imm_expr, 0); | |
6425 | macro_build ((char *) NULL, &icnt, NULL, s, "s,t", sreg, AT); | |
6426 | break; | |
6427 | ||
252b5132 | 6428 | case M_TRUNCWS: |
43841e91 | 6429 | case M_TRUNCWD: |
e7af610e | 6430 | assert (mips_opts.isa == ISA_MIPS1); |
252b5132 RH |
6431 | sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */ |
6432 | dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */ | |
6433 | ||
6434 | /* | |
6435 | * Is the double cfc1 instruction a bug in the mips assembler; | |
6436 | * or is there a reason for it? | |
6437 | */ | |
6438 | mips_emit_delays (true); | |
6439 | ++mips_opts.noreorder; | |
6440 | mips_any_noreorder = 1; | |
6441 | macro_build ((char *) NULL, &icnt, NULL, "cfc1", "t,G", treg, 31); | |
6442 | macro_build ((char *) NULL, &icnt, NULL, "cfc1", "t,G", treg, 31); | |
6443 | macro_build ((char *) NULL, &icnt, NULL, "nop", ""); | |
6444 | expr1.X_add_number = 3; | |
6445 | macro_build ((char *) NULL, &icnt, &expr1, "ori", "t,r,i", AT, treg, | |
6446 | (int) BFD_RELOC_LO16); | |
6447 | expr1.X_add_number = 2; | |
6448 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", AT, AT, | |
6449 | (int) BFD_RELOC_LO16); | |
6450 | macro_build ((char *) NULL, &icnt, NULL, "ctc1", "t,G", AT, 31); | |
6451 | macro_build ((char *) NULL, &icnt, NULL, "nop", ""); | |
6452 | macro_build ((char *) NULL, &icnt, NULL, | |
6453 | mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S", dreg, sreg); | |
6454 | macro_build ((char *) NULL, &icnt, NULL, "ctc1", "t,G", treg, 31); | |
6455 | macro_build ((char *) NULL, &icnt, NULL, "nop", ""); | |
6456 | --mips_opts.noreorder; | |
6457 | break; | |
6458 | ||
6459 | case M_ULH: | |
6460 | s = "lb"; | |
6461 | goto ulh; | |
6462 | case M_ULHU: | |
6463 | s = "lbu"; | |
6464 | ulh: | |
6465 | if (offset_expr.X_add_number >= 0x7fff) | |
6466 | as_bad (_("operand overflow")); | |
6467 | /* avoid load delay */ | |
6468 | if (! target_big_endian) | |
6469 | offset_expr.X_add_number += 1; | |
6470 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, | |
6471 | (int) BFD_RELOC_LO16, breg); | |
6472 | if (! target_big_endian) | |
6473 | offset_expr.X_add_number -= 1; | |
6474 | else | |
6475 | offset_expr.X_add_number += 1; | |
6476 | macro_build ((char *) NULL, &icnt, &offset_expr, "lbu", "t,o(b)", AT, | |
6477 | (int) BFD_RELOC_LO16, breg); | |
6478 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", treg, treg, 8); | |
6479 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", treg, treg, AT); | |
6480 | break; | |
6481 | ||
6482 | case M_ULD: | |
6483 | s = "ldl"; | |
6484 | s2 = "ldr"; | |
6485 | off = 7; | |
6486 | goto ulw; | |
6487 | case M_ULW: | |
6488 | s = "lwl"; | |
6489 | s2 = "lwr"; | |
6490 | off = 3; | |
6491 | ulw: | |
6492 | if (offset_expr.X_add_number >= 0x8000 - off) | |
6493 | as_bad (_("operand overflow")); | |
6494 | if (! target_big_endian) | |
6495 | offset_expr.X_add_number += off; | |
6496 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, | |
6497 | (int) BFD_RELOC_LO16, breg); | |
6498 | if (! target_big_endian) | |
6499 | offset_expr.X_add_number -= off; | |
6500 | else | |
6501 | offset_expr.X_add_number += off; | |
6502 | macro_build ((char *) NULL, &icnt, &offset_expr, s2, "t,o(b)", treg, | |
6503 | (int) BFD_RELOC_LO16, breg); | |
6504 | return; | |
6505 | ||
6506 | case M_ULD_A: | |
6507 | s = "ldl"; | |
6508 | s2 = "ldr"; | |
6509 | off = 7; | |
6510 | goto ulwa; | |
6511 | case M_ULW_A: | |
6512 | s = "lwl"; | |
6513 | s2 = "lwr"; | |
6514 | off = 3; | |
6515 | ulwa: | |
6516 | load_address (&icnt, AT, &offset_expr); | |
6517 | if (breg != 0) | |
6518 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
6519 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 6520 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
6521 | ? "addu" : "daddu"), |
6522 | "d,v,t", AT, AT, breg); | |
6523 | if (! target_big_endian) | |
6524 | expr1.X_add_number = off; | |
6525 | else | |
6526 | expr1.X_add_number = 0; | |
6527 | macro_build ((char *) NULL, &icnt, &expr1, s, "t,o(b)", treg, | |
6528 | (int) BFD_RELOC_LO16, AT); | |
6529 | if (! target_big_endian) | |
6530 | expr1.X_add_number = 0; | |
6531 | else | |
6532 | expr1.X_add_number = off; | |
6533 | macro_build ((char *) NULL, &icnt, &expr1, s2, "t,o(b)", treg, | |
6534 | (int) BFD_RELOC_LO16, AT); | |
6535 | break; | |
6536 | ||
6537 | case M_ULH_A: | |
6538 | case M_ULHU_A: | |
6539 | load_address (&icnt, AT, &offset_expr); | |
6540 | if (breg != 0) | |
6541 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
6542 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 6543 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
6544 | ? "addu" : "daddu"), |
6545 | "d,v,t", AT, AT, breg); | |
6546 | if (target_big_endian) | |
6547 | expr1.X_add_number = 0; | |
6548 | macro_build ((char *) NULL, &icnt, &expr1, | |
6549 | mask == M_ULH_A ? "lb" : "lbu", "t,o(b)", treg, | |
6550 | (int) BFD_RELOC_LO16, AT); | |
6551 | if (target_big_endian) | |
6552 | expr1.X_add_number = 1; | |
6553 | else | |
6554 | expr1.X_add_number = 0; | |
6555 | macro_build ((char *) NULL, &icnt, &expr1, "lbu", "t,o(b)", AT, | |
6556 | (int) BFD_RELOC_LO16, AT); | |
6557 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", treg, | |
6558 | treg, 8); | |
6559 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", treg, | |
6560 | treg, AT); | |
6561 | break; | |
6562 | ||
6563 | case M_USH: | |
6564 | if (offset_expr.X_add_number >= 0x7fff) | |
6565 | as_bad (_("operand overflow")); | |
6566 | if (target_big_endian) | |
6567 | offset_expr.X_add_number += 1; | |
6568 | macro_build ((char *) NULL, &icnt, &offset_expr, "sb", "t,o(b)", treg, | |
6569 | (int) BFD_RELOC_LO16, breg); | |
6570 | macro_build ((char *) NULL, &icnt, NULL, "srl", "d,w,<", AT, treg, 8); | |
6571 | if (target_big_endian) | |
6572 | offset_expr.X_add_number -= 1; | |
6573 | else | |
6574 | offset_expr.X_add_number += 1; | |
6575 | macro_build ((char *) NULL, &icnt, &offset_expr, "sb", "t,o(b)", AT, | |
6576 | (int) BFD_RELOC_LO16, breg); | |
6577 | break; | |
6578 | ||
6579 | case M_USD: | |
6580 | s = "sdl"; | |
6581 | s2 = "sdr"; | |
6582 | off = 7; | |
6583 | goto usw; | |
6584 | case M_USW: | |
6585 | s = "swl"; | |
6586 | s2 = "swr"; | |
6587 | off = 3; | |
6588 | usw: | |
6589 | if (offset_expr.X_add_number >= 0x8000 - off) | |
6590 | as_bad (_("operand overflow")); | |
6591 | if (! target_big_endian) | |
6592 | offset_expr.X_add_number += off; | |
6593 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, | |
6594 | (int) BFD_RELOC_LO16, breg); | |
6595 | if (! target_big_endian) | |
6596 | offset_expr.X_add_number -= off; | |
6597 | else | |
6598 | offset_expr.X_add_number += off; | |
6599 | macro_build ((char *) NULL, &icnt, &offset_expr, s2, "t,o(b)", treg, | |
6600 | (int) BFD_RELOC_LO16, breg); | |
6601 | return; | |
6602 | ||
6603 | case M_USD_A: | |
6604 | s = "sdl"; | |
6605 | s2 = "sdr"; | |
6606 | off = 7; | |
6607 | goto uswa; | |
6608 | case M_USW_A: | |
6609 | s = "swl"; | |
6610 | s2 = "swr"; | |
6611 | off = 3; | |
6612 | uswa: | |
6613 | load_address (&icnt, AT, &offset_expr); | |
6614 | if (breg != 0) | |
6615 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
6616 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 6617 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
6618 | ? "addu" : "daddu"), |
6619 | "d,v,t", AT, AT, breg); | |
6620 | if (! target_big_endian) | |
6621 | expr1.X_add_number = off; | |
6622 | else | |
6623 | expr1.X_add_number = 0; | |
6624 | macro_build ((char *) NULL, &icnt, &expr1, s, "t,o(b)", treg, | |
6625 | (int) BFD_RELOC_LO16, AT); | |
6626 | if (! target_big_endian) | |
6627 | expr1.X_add_number = 0; | |
6628 | else | |
6629 | expr1.X_add_number = off; | |
6630 | macro_build ((char *) NULL, &icnt, &expr1, s2, "t,o(b)", treg, | |
6631 | (int) BFD_RELOC_LO16, AT); | |
6632 | break; | |
6633 | ||
6634 | case M_USH_A: | |
6635 | load_address (&icnt, AT, &offset_expr); | |
6636 | if (breg != 0) | |
6637 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
6638 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 6639 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
6640 | ? "addu" : "daddu"), |
6641 | "d,v,t", AT, AT, breg); | |
6642 | if (! target_big_endian) | |
6643 | expr1.X_add_number = 0; | |
6644 | macro_build ((char *) NULL, &icnt, &expr1, "sb", "t,o(b)", treg, | |
6645 | (int) BFD_RELOC_LO16, AT); | |
6646 | macro_build ((char *) NULL, &icnt, NULL, "srl", "d,w,<", treg, | |
6647 | treg, 8); | |
6648 | if (! target_big_endian) | |
6649 | expr1.X_add_number = 1; | |
6650 | else | |
6651 | expr1.X_add_number = 0; | |
6652 | macro_build ((char *) NULL, &icnt, &expr1, "sb", "t,o(b)", treg, | |
6653 | (int) BFD_RELOC_LO16, AT); | |
6654 | if (! target_big_endian) | |
6655 | expr1.X_add_number = 0; | |
6656 | else | |
6657 | expr1.X_add_number = 1; | |
6658 | macro_build ((char *) NULL, &icnt, &expr1, "lbu", "t,o(b)", AT, | |
6659 | (int) BFD_RELOC_LO16, AT); | |
6660 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", treg, | |
6661 | treg, 8); | |
6662 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", treg, | |
6663 | treg, AT); | |
6664 | break; | |
6665 | ||
6666 | default: | |
6667 | /* FIXME: Check if this is one of the itbl macros, since they | |
bdaaa2e1 | 6668 | are added dynamically. */ |
252b5132 RH |
6669 | as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name); |
6670 | break; | |
6671 | } | |
6672 | if (mips_opts.noat) | |
6673 | as_warn (_("Macro used $at after \".set noat\"")); | |
6674 | } | |
6675 | ||
6676 | /* Implement macros in mips16 mode. */ | |
6677 | ||
6678 | static void | |
6679 | mips16_macro (ip) | |
6680 | struct mips_cl_insn *ip; | |
6681 | { | |
6682 | int mask; | |
6683 | int xreg, yreg, zreg, tmp; | |
6684 | int icnt; | |
6685 | expressionS expr1; | |
6686 | int dbl; | |
6687 | const char *s, *s2, *s3; | |
6688 | ||
6689 | mask = ip->insn_mo->mask; | |
6690 | ||
6691 | xreg = (ip->insn_opcode >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX; | |
6692 | yreg = (ip->insn_opcode >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY; | |
6693 | zreg = (ip->insn_opcode >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ; | |
6694 | ||
6695 | icnt = 0; | |
6696 | ||
6697 | expr1.X_op = O_constant; | |
6698 | expr1.X_op_symbol = NULL; | |
6699 | expr1.X_add_symbol = NULL; | |
6700 | expr1.X_add_number = 1; | |
6701 | ||
6702 | dbl = 0; | |
6703 | ||
6704 | switch (mask) | |
6705 | { | |
6706 | default: | |
6707 | internalError (); | |
6708 | ||
6709 | case M_DDIV_3: | |
6710 | dbl = 1; | |
6711 | case M_DIV_3: | |
6712 | s = "mflo"; | |
6713 | goto do_div3; | |
6714 | case M_DREM_3: | |
6715 | dbl = 1; | |
6716 | case M_REM_3: | |
6717 | s = "mfhi"; | |
6718 | do_div3: | |
6719 | mips_emit_delays (true); | |
6720 | ++mips_opts.noreorder; | |
6721 | mips_any_noreorder = 1; | |
6722 | macro_build ((char *) NULL, &icnt, NULL, | |
6723 | dbl ? "ddiv" : "div", | |
6724 | "0,x,y", xreg, yreg); | |
6725 | expr1.X_add_number = 2; | |
6726 | macro_build ((char *) NULL, &icnt, &expr1, "bnez", "x,p", yreg); | |
beae10d5 | 6727 | macro_build ((char *) NULL, &icnt, NULL, "break", "6", 7); |
bdaaa2e1 | 6728 | |
252b5132 RH |
6729 | /* FIXME: The normal code checks for of -1 / -0x80000000 here, |
6730 | since that causes an overflow. We should do that as well, | |
6731 | but I don't see how to do the comparisons without a temporary | |
6732 | register. */ | |
6733 | --mips_opts.noreorder; | |
6734 | macro_build ((char *) NULL, &icnt, NULL, s, "x", zreg); | |
6735 | break; | |
6736 | ||
6737 | case M_DIVU_3: | |
6738 | s = "divu"; | |
6739 | s2 = "mflo"; | |
6740 | goto do_divu3; | |
6741 | case M_REMU_3: | |
6742 | s = "divu"; | |
6743 | s2 = "mfhi"; | |
6744 | goto do_divu3; | |
6745 | case M_DDIVU_3: | |
6746 | s = "ddivu"; | |
6747 | s2 = "mflo"; | |
6748 | goto do_divu3; | |
6749 | case M_DREMU_3: | |
6750 | s = "ddivu"; | |
6751 | s2 = "mfhi"; | |
6752 | do_divu3: | |
6753 | mips_emit_delays (true); | |
6754 | ++mips_opts.noreorder; | |
6755 | mips_any_noreorder = 1; | |
6756 | macro_build ((char *) NULL, &icnt, NULL, s, "0,x,y", xreg, yreg); | |
6757 | expr1.X_add_number = 2; | |
6758 | macro_build ((char *) NULL, &icnt, &expr1, "bnez", "x,p", yreg); | |
6759 | macro_build ((char *) NULL, &icnt, NULL, "break", "6", 7); | |
6760 | --mips_opts.noreorder; | |
6761 | macro_build ((char *) NULL, &icnt, NULL, s2, "x", zreg); | |
6762 | break; | |
6763 | ||
6764 | case M_DMUL: | |
6765 | dbl = 1; | |
6766 | case M_MUL: | |
6767 | macro_build ((char *) NULL, &icnt, NULL, | |
6768 | dbl ? "dmultu" : "multu", | |
6769 | "x,y", xreg, yreg); | |
6770 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "x", zreg); | |
6771 | return; | |
6772 | ||
6773 | case M_DSUBU_I: | |
6774 | dbl = 1; | |
6775 | goto do_subu; | |
6776 | case M_SUBU_I: | |
6777 | do_subu: | |
6778 | if (imm_expr.X_op != O_constant) | |
6779 | as_bad (_("Unsupported large constant")); | |
6780 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
6781 | macro_build ((char *) NULL, &icnt, &imm_expr, | |
6782 | dbl ? "daddiu" : "addiu", | |
6783 | "y,x,4", yreg, xreg); | |
6784 | break; | |
6785 | ||
6786 | case M_SUBU_I_2: | |
6787 | if (imm_expr.X_op != O_constant) | |
6788 | as_bad (_("Unsupported large constant")); | |
6789 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
6790 | macro_build ((char *) NULL, &icnt, &imm_expr, "addiu", | |
6791 | "x,k", xreg); | |
6792 | break; | |
6793 | ||
6794 | case M_DSUBU_I_2: | |
6795 | if (imm_expr.X_op != O_constant) | |
6796 | as_bad (_("Unsupported large constant")); | |
6797 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
6798 | macro_build ((char *) NULL, &icnt, &imm_expr, "daddiu", | |
6799 | "y,j", yreg); | |
6800 | break; | |
6801 | ||
6802 | case M_BEQ: | |
6803 | s = "cmp"; | |
6804 | s2 = "bteqz"; | |
6805 | goto do_branch; | |
6806 | case M_BNE: | |
6807 | s = "cmp"; | |
6808 | s2 = "btnez"; | |
6809 | goto do_branch; | |
6810 | case M_BLT: | |
6811 | s = "slt"; | |
6812 | s2 = "btnez"; | |
6813 | goto do_branch; | |
6814 | case M_BLTU: | |
6815 | s = "sltu"; | |
6816 | s2 = "btnez"; | |
6817 | goto do_branch; | |
6818 | case M_BLE: | |
6819 | s = "slt"; | |
6820 | s2 = "bteqz"; | |
6821 | goto do_reverse_branch; | |
6822 | case M_BLEU: | |
6823 | s = "sltu"; | |
6824 | s2 = "bteqz"; | |
6825 | goto do_reverse_branch; | |
6826 | case M_BGE: | |
6827 | s = "slt"; | |
6828 | s2 = "bteqz"; | |
6829 | goto do_branch; | |
6830 | case M_BGEU: | |
6831 | s = "sltu"; | |
6832 | s2 = "bteqz"; | |
6833 | goto do_branch; | |
6834 | case M_BGT: | |
6835 | s = "slt"; | |
6836 | s2 = "btnez"; | |
6837 | goto do_reverse_branch; | |
6838 | case M_BGTU: | |
6839 | s = "sltu"; | |
6840 | s2 = "btnez"; | |
6841 | ||
6842 | do_reverse_branch: | |
6843 | tmp = xreg; | |
6844 | xreg = yreg; | |
6845 | yreg = tmp; | |
6846 | ||
6847 | do_branch: | |
6848 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "x,y", | |
6849 | xreg, yreg); | |
6850 | macro_build ((char *) NULL, &icnt, &offset_expr, s2, "p"); | |
6851 | break; | |
6852 | ||
6853 | case M_BEQ_I: | |
6854 | s = "cmpi"; | |
6855 | s2 = "bteqz"; | |
6856 | s3 = "x,U"; | |
6857 | goto do_branch_i; | |
6858 | case M_BNE_I: | |
6859 | s = "cmpi"; | |
6860 | s2 = "btnez"; | |
6861 | s3 = "x,U"; | |
6862 | goto do_branch_i; | |
6863 | case M_BLT_I: | |
6864 | s = "slti"; | |
6865 | s2 = "btnez"; | |
6866 | s3 = "x,8"; | |
6867 | goto do_branch_i; | |
6868 | case M_BLTU_I: | |
6869 | s = "sltiu"; | |
6870 | s2 = "btnez"; | |
6871 | s3 = "x,8"; | |
6872 | goto do_branch_i; | |
6873 | case M_BLE_I: | |
6874 | s = "slti"; | |
6875 | s2 = "btnez"; | |
6876 | s3 = "x,8"; | |
6877 | goto do_addone_branch_i; | |
6878 | case M_BLEU_I: | |
6879 | s = "sltiu"; | |
6880 | s2 = "btnez"; | |
6881 | s3 = "x,8"; | |
6882 | goto do_addone_branch_i; | |
6883 | case M_BGE_I: | |
6884 | s = "slti"; | |
6885 | s2 = "bteqz"; | |
6886 | s3 = "x,8"; | |
6887 | goto do_branch_i; | |
6888 | case M_BGEU_I: | |
6889 | s = "sltiu"; | |
6890 | s2 = "bteqz"; | |
6891 | s3 = "x,8"; | |
6892 | goto do_branch_i; | |
6893 | case M_BGT_I: | |
6894 | s = "slti"; | |
6895 | s2 = "bteqz"; | |
6896 | s3 = "x,8"; | |
6897 | goto do_addone_branch_i; | |
6898 | case M_BGTU_I: | |
6899 | s = "sltiu"; | |
6900 | s2 = "bteqz"; | |
6901 | s3 = "x,8"; | |
6902 | ||
6903 | do_addone_branch_i: | |
6904 | if (imm_expr.X_op != O_constant) | |
6905 | as_bad (_("Unsupported large constant")); | |
6906 | ++imm_expr.X_add_number; | |
6907 | ||
6908 | do_branch_i: | |
6909 | macro_build ((char *) NULL, &icnt, &imm_expr, s, s3, xreg); | |
6910 | macro_build ((char *) NULL, &icnt, &offset_expr, s2, "p"); | |
6911 | break; | |
6912 | ||
6913 | case M_ABS: | |
6914 | expr1.X_add_number = 0; | |
6915 | macro_build ((char *) NULL, &icnt, &expr1, "slti", "x,8", yreg); | |
6916 | if (xreg != yreg) | |
6917 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
6918 | "move", "y,X", xreg, yreg); | |
6919 | expr1.X_add_number = 2; | |
6920 | macro_build ((char *) NULL, &icnt, &expr1, "bteqz", "p"); | |
6921 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
6922 | "neg", "x,w", xreg, xreg); | |
6923 | } | |
6924 | } | |
6925 | ||
6926 | /* For consistency checking, verify that all bits are specified either | |
6927 | by the match/mask part of the instruction definition, or by the | |
6928 | operand list. */ | |
6929 | static int | |
6930 | validate_mips_insn (opc) | |
6931 | const struct mips_opcode *opc; | |
6932 | { | |
6933 | const char *p = opc->args; | |
6934 | char c; | |
6935 | unsigned long used_bits = opc->mask; | |
6936 | ||
6937 | if ((used_bits & opc->match) != opc->match) | |
6938 | { | |
6939 | as_bad (_("internal: bad mips opcode (mask error): %s %s"), | |
6940 | opc->name, opc->args); | |
6941 | return 0; | |
6942 | } | |
6943 | #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift))) | |
6944 | while (*p) | |
6945 | switch (c = *p++) | |
6946 | { | |
6947 | case ',': break; | |
6948 | case '(': break; | |
6949 | case ')': break; | |
6950 | case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; | |
6951 | case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; | |
6952 | case 'A': break; | |
4372b673 | 6953 | case 'B': USE_BITS (OP_MASK_CODE20, OP_SH_CODE20); break; |
252b5132 RH |
6954 | case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break; |
6955 | case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break; | |
6956 | case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
6957 | case 'F': break; | |
6958 | case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
156c2f8b | 6959 | case 'H': USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; |
252b5132 | 6960 | case 'I': break; |
e972090a | 6961 | case 'J': USE_BITS (OP_MASK_CODE19, OP_SH_CODE19); break; |
252b5132 RH |
6962 | case 'L': break; |
6963 | case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break; | |
6964 | case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break; | |
6965 | case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break; | |
6966 | case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
6967 | case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
6968 | case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
6969 | case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
6970 | case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break; | |
6971 | case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
6972 | case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break; | |
6973 | case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
6974 | case 'f': break; | |
6975 | case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break; | |
6976 | case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; | |
6977 | case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
6978 | case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break; | |
6979 | case 'l': break; | |
6980 | case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
6981 | case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
6982 | case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break; | |
6983 | case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
6984 | case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
6985 | case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
6986 | case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; | |
6987 | case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
6988 | case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
6989 | case 'x': break; | |
6990 | case 'z': break; | |
6991 | case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break; | |
4372b673 NC |
6992 | case 'U': USE_BITS (OP_MASK_RD, OP_SH_RD); |
6993 | USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
252b5132 RH |
6994 | default: |
6995 | as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"), | |
6996 | c, opc->name, opc->args); | |
6997 | return 0; | |
6998 | } | |
6999 | #undef USE_BITS | |
7000 | if (used_bits != 0xffffffff) | |
7001 | { | |
7002 | as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"), | |
7003 | ~used_bits & 0xffffffff, opc->name, opc->args); | |
7004 | return 0; | |
7005 | } | |
7006 | return 1; | |
7007 | } | |
7008 | ||
7009 | /* This routine assembles an instruction into its binary format. As a | |
7010 | side effect, it sets one of the global variables imm_reloc or | |
7011 | offset_reloc to the type of relocation to do if one of the operands | |
7012 | is an address expression. */ | |
7013 | ||
7014 | static void | |
7015 | mips_ip (str, ip) | |
7016 | char *str; | |
7017 | struct mips_cl_insn *ip; | |
7018 | { | |
7019 | char *s; | |
7020 | const char *args; | |
43841e91 | 7021 | char c = 0; |
252b5132 RH |
7022 | struct mips_opcode *insn; |
7023 | char *argsStart; | |
7024 | unsigned int regno; | |
7025 | unsigned int lastregno = 0; | |
7026 | char *s_reset; | |
7027 | char save_c = 0; | |
7028 | int full_opcode_match = 1; | |
7029 | ||
7030 | insn_error = NULL; | |
7031 | ||
7032 | /* If the instruction contains a '.', we first try to match an instruction | |
7033 | including the '.'. Then we try again without the '.'. */ | |
7034 | insn = NULL; | |
d9a62219 | 7035 | for (s = str; *s != '\0' && !isspace ((unsigned char) *s); ++s) |
252b5132 RH |
7036 | continue; |
7037 | ||
7038 | /* If we stopped on whitespace, then replace the whitespace with null for | |
7039 | the call to hash_find. Save the character we replaced just in case we | |
7040 | have to re-parse the instruction. */ | |
d9a62219 | 7041 | if (isspace ((unsigned char) *s)) |
252b5132 RH |
7042 | { |
7043 | save_c = *s; | |
7044 | *s++ = '\0'; | |
7045 | } | |
bdaaa2e1 | 7046 | |
252b5132 RH |
7047 | insn = (struct mips_opcode *) hash_find (op_hash, str); |
7048 | ||
7049 | /* If we didn't find the instruction in the opcode table, try again, but | |
7050 | this time with just the instruction up to, but not including the | |
7051 | first '.'. */ | |
7052 | if (insn == NULL) | |
7053 | { | |
bdaaa2e1 | 7054 | /* Restore the character we overwrite above (if any). */ |
252b5132 RH |
7055 | if (save_c) |
7056 | *(--s) = save_c; | |
7057 | ||
7058 | /* Scan up to the first '.' or whitespace. */ | |
d9a62219 | 7059 | for (s = str; *s != '\0' && *s != '.' && !isspace ((unsigned char) *s); ++s) |
252b5132 RH |
7060 | continue; |
7061 | ||
7062 | /* If we did not find a '.', then we can quit now. */ | |
7063 | if (*s != '.') | |
7064 | { | |
7065 | insn_error = "unrecognized opcode"; | |
7066 | return; | |
7067 | } | |
7068 | ||
7069 | /* Lookup the instruction in the hash table. */ | |
7070 | *s++ = '\0'; | |
7071 | if ((insn = (struct mips_opcode *) hash_find (op_hash, str)) == NULL) | |
7072 | { | |
7073 | insn_error = "unrecognized opcode"; | |
7074 | return; | |
7075 | } | |
7076 | ||
7077 | full_opcode_match = 0; | |
7078 | } | |
7079 | ||
7080 | argsStart = s; | |
7081 | for (;;) | |
7082 | { | |
252b5132 RH |
7083 | boolean ok; |
7084 | ||
7085 | assert (strcmp (insn->name, str) == 0); | |
7086 | ||
ec68c924 | 7087 | if (OPCODE_IS_MEMBER (insn, mips_opts.isa, mips_arch, mips_gp32)) |
252b5132 | 7088 | ok = true; |
bdaaa2e1 | 7089 | else |
252b5132 | 7090 | ok = false; |
bdaaa2e1 | 7091 | |
252b5132 RH |
7092 | if (insn->pinfo != INSN_MACRO) |
7093 | { | |
ec68c924 | 7094 | if (mips_arch == CPU_R4650 && (insn->pinfo & FP_D) != 0) |
252b5132 RH |
7095 | ok = false; |
7096 | } | |
7097 | ||
7098 | if (! ok) | |
7099 | { | |
7100 | if (insn + 1 < &mips_opcodes[NUMOPCODES] | |
7101 | && strcmp (insn->name, insn[1].name) == 0) | |
7102 | { | |
7103 | ++insn; | |
7104 | continue; | |
7105 | } | |
252b5132 | 7106 | else |
beae10d5 | 7107 | { |
268f6bed L |
7108 | if (!insn_error) |
7109 | { | |
7110 | static char buf[100]; | |
7111 | sprintf (buf, | |
7112 | _("opcode not supported on this processor: %s (%s)"), | |
ec68c924 | 7113 | mips_cpu_to_str (mips_arch), |
268f6bed | 7114 | mips_isa_to_str (mips_opts.isa)); |
bdaaa2e1 | 7115 | |
268f6bed L |
7116 | insn_error = buf; |
7117 | } | |
7118 | if (save_c) | |
7119 | *(--s) = save_c; | |
2bd7f1f3 | 7120 | return; |
252b5132 | 7121 | } |
252b5132 RH |
7122 | } |
7123 | ||
7124 | ip->insn_mo = insn; | |
7125 | ip->insn_opcode = insn->match; | |
268f6bed | 7126 | insn_error = NULL; |
252b5132 RH |
7127 | for (args = insn->args;; ++args) |
7128 | { | |
7129 | if (*s == ' ') | |
7130 | ++s; | |
7131 | switch (*args) | |
7132 | { | |
7133 | case '\0': /* end of args */ | |
7134 | if (*s == '\0') | |
7135 | return; | |
7136 | break; | |
7137 | ||
7138 | case ',': | |
7139 | if (*s++ == *args) | |
7140 | continue; | |
7141 | s--; | |
7142 | switch (*++args) | |
7143 | { | |
7144 | case 'r': | |
7145 | case 'v': | |
7146 | ip->insn_opcode |= lastregno << 21; | |
7147 | continue; | |
7148 | ||
7149 | case 'w': | |
7150 | case 'W': | |
7151 | ip->insn_opcode |= lastregno << 16; | |
7152 | continue; | |
7153 | ||
7154 | case 'V': | |
7155 | ip->insn_opcode |= lastregno << 11; | |
7156 | continue; | |
7157 | } | |
7158 | break; | |
7159 | ||
7160 | case '(': | |
7161 | /* Handle optional base register. | |
7162 | Either the base register is omitted or | |
bdaaa2e1 | 7163 | we must have a left paren. */ |
252b5132 RH |
7164 | /* This is dependent on the next operand specifier |
7165 | is a base register specification. */ | |
7166 | assert (args[1] == 'b' || args[1] == '5' | |
7167 | || args[1] == '-' || args[1] == '4'); | |
7168 | if (*s == '\0') | |
7169 | return; | |
7170 | ||
7171 | case ')': /* these must match exactly */ | |
7172 | if (*s++ == *args) | |
7173 | continue; | |
7174 | break; | |
7175 | ||
7176 | case '<': /* must be at least one digit */ | |
7177 | /* | |
7178 | * According to the manual, if the shift amount is greater | |
7179 | * than 31 or less than 0 the the shift amount should be | |
7180 | * mod 32. In reality the mips assembler issues an error. | |
7181 | * We issue a warning and mask out all but the low 5 bits. | |
7182 | */ | |
7183 | my_getExpression (&imm_expr, s); | |
7184 | check_absolute_expr (ip, &imm_expr); | |
7185 | if ((unsigned long) imm_expr.X_add_number > 31) | |
7186 | { | |
7187 | as_warn (_("Improper shift amount (%ld)"), | |
7188 | (long) imm_expr.X_add_number); | |
7189 | imm_expr.X_add_number = imm_expr.X_add_number & 0x1f; | |
7190 | } | |
7191 | ip->insn_opcode |= imm_expr.X_add_number << 6; | |
7192 | imm_expr.X_op = O_absent; | |
7193 | s = expr_end; | |
7194 | continue; | |
7195 | ||
7196 | case '>': /* shift amount minus 32 */ | |
7197 | my_getExpression (&imm_expr, s); | |
7198 | check_absolute_expr (ip, &imm_expr); | |
7199 | if ((unsigned long) imm_expr.X_add_number < 32 | |
7200 | || (unsigned long) imm_expr.X_add_number > 63) | |
7201 | break; | |
7202 | ip->insn_opcode |= (imm_expr.X_add_number - 32) << 6; | |
7203 | imm_expr.X_op = O_absent; | |
7204 | s = expr_end; | |
7205 | continue; | |
7206 | ||
252b5132 RH |
7207 | case 'k': /* cache code */ |
7208 | case 'h': /* prefx code */ | |
7209 | my_getExpression (&imm_expr, s); | |
7210 | check_absolute_expr (ip, &imm_expr); | |
7211 | if ((unsigned long) imm_expr.X_add_number > 31) | |
7212 | { | |
7213 | as_warn (_("Invalid value for `%s' (%lu)"), | |
7214 | ip->insn_mo->name, | |
7215 | (unsigned long) imm_expr.X_add_number); | |
7216 | imm_expr.X_add_number &= 0x1f; | |
7217 | } | |
7218 | if (*args == 'k') | |
7219 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CACHE; | |
7220 | else | |
7221 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_PREFX; | |
7222 | imm_expr.X_op = O_absent; | |
7223 | s = expr_end; | |
7224 | continue; | |
7225 | ||
7226 | case 'c': /* break code */ | |
7227 | my_getExpression (&imm_expr, s); | |
7228 | check_absolute_expr (ip, &imm_expr); | |
7229 | if ((unsigned) imm_expr.X_add_number > 1023) | |
7230 | { | |
7231 | as_warn (_("Illegal break code (%ld)"), | |
7232 | (long) imm_expr.X_add_number); | |
7233 | imm_expr.X_add_number &= 0x3ff; | |
7234 | } | |
7235 | ip->insn_opcode |= imm_expr.X_add_number << 16; | |
7236 | imm_expr.X_op = O_absent; | |
7237 | s = expr_end; | |
7238 | continue; | |
7239 | ||
7240 | case 'q': /* lower break code */ | |
7241 | my_getExpression (&imm_expr, s); | |
7242 | check_absolute_expr (ip, &imm_expr); | |
7243 | if ((unsigned) imm_expr.X_add_number > 1023) | |
7244 | { | |
7245 | as_warn (_("Illegal lower break code (%ld)"), | |
7246 | (long) imm_expr.X_add_number); | |
7247 | imm_expr.X_add_number &= 0x3ff; | |
7248 | } | |
7249 | ip->insn_opcode |= imm_expr.X_add_number << 6; | |
7250 | imm_expr.X_op = O_absent; | |
7251 | s = expr_end; | |
7252 | continue; | |
7253 | ||
4372b673 | 7254 | case 'B': /* 20-bit syscall/break code. */ |
156c2f8b | 7255 | my_getExpression (&imm_expr, s); |
156c2f8b | 7256 | check_absolute_expr (ip, &imm_expr); |
156c2f8b | 7257 | if ((unsigned) imm_expr.X_add_number > 0xfffff) |
4372b673 | 7258 | as_warn (_("Illegal 20-bit code (%ld)"), |
252b5132 RH |
7259 | (long) imm_expr.X_add_number); |
7260 | ip->insn_opcode |= imm_expr.X_add_number << 6; | |
7261 | imm_expr.X_op = O_absent; | |
7262 | s = expr_end; | |
7263 | continue; | |
7264 | ||
7265 | case 'C': /* Coprocessor code */ | |
beae10d5 | 7266 | my_getExpression (&imm_expr, s); |
252b5132 | 7267 | check_absolute_expr (ip, &imm_expr); |
beae10d5 | 7268 | if ((unsigned long) imm_expr.X_add_number >= (1<<25)) |
252b5132 | 7269 | { |
beae10d5 | 7270 | as_warn (_("Coproccesor code > 25 bits (%ld)"), |
252b5132 | 7271 | (long) imm_expr.X_add_number); |
beae10d5 | 7272 | imm_expr.X_add_number &= ((1<<25) - 1); |
252b5132 | 7273 | } |
beae10d5 KH |
7274 | ip->insn_opcode |= imm_expr.X_add_number; |
7275 | imm_expr.X_op = O_absent; | |
7276 | s = expr_end; | |
7277 | continue; | |
252b5132 | 7278 | |
4372b673 NC |
7279 | case 'J': /* 19-bit wait code. */ |
7280 | my_getExpression (&imm_expr, s); | |
7281 | check_absolute_expr (ip, &imm_expr); | |
7282 | if ((unsigned) imm_expr.X_add_number > 0x7ffff) | |
7283 | as_warn (_("Illegal 19-bit code (%ld)"), | |
7284 | (long) imm_expr.X_add_number); | |
7285 | ip->insn_opcode |= imm_expr.X_add_number << 6; | |
7286 | imm_expr.X_op = O_absent; | |
7287 | s = expr_end; | |
7288 | continue; | |
7289 | ||
252b5132 | 7290 | case 'P': /* Performance register */ |
beae10d5 | 7291 | my_getExpression (&imm_expr, s); |
252b5132 | 7292 | check_absolute_expr (ip, &imm_expr); |
beae10d5 | 7293 | if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1) |
252b5132 | 7294 | { |
beae10d5 | 7295 | as_warn (_("Invalidate performance regster (%ld)"), |
252b5132 | 7296 | (long) imm_expr.X_add_number); |
beae10d5 | 7297 | imm_expr.X_add_number &= 1; |
252b5132 | 7298 | } |
beae10d5 KH |
7299 | ip->insn_opcode |= (imm_expr.X_add_number << 1); |
7300 | imm_expr.X_op = O_absent; | |
7301 | s = expr_end; | |
7302 | continue; | |
252b5132 RH |
7303 | |
7304 | case 'b': /* base register */ | |
7305 | case 'd': /* destination register */ | |
7306 | case 's': /* source register */ | |
7307 | case 't': /* target register */ | |
7308 | case 'r': /* both target and source */ | |
7309 | case 'v': /* both dest and source */ | |
7310 | case 'w': /* both dest and target */ | |
7311 | case 'E': /* coprocessor target register */ | |
7312 | case 'G': /* coprocessor destination register */ | |
7313 | case 'x': /* ignore register name */ | |
7314 | case 'z': /* must be zero register */ | |
4372b673 | 7315 | case 'U': /* destination register (clo/clz). */ |
252b5132 RH |
7316 | s_reset = s; |
7317 | if (s[0] == '$') | |
7318 | { | |
7319 | ||
d9a62219 | 7320 | if (isdigit ((unsigned char) s[1])) |
252b5132 RH |
7321 | { |
7322 | ++s; | |
7323 | regno = 0; | |
7324 | do | |
7325 | { | |
7326 | regno *= 10; | |
7327 | regno += *s - '0'; | |
7328 | ++s; | |
7329 | } | |
d9a62219 | 7330 | while (isdigit ((unsigned char) *s)); |
252b5132 RH |
7331 | if (regno > 31) |
7332 | as_bad (_("Invalid register number (%d)"), regno); | |
7333 | } | |
7334 | else if (*args == 'E' || *args == 'G') | |
7335 | goto notreg; | |
7336 | else | |
7337 | { | |
7338 | if (s[1] == 'f' && s[2] == 'p') | |
7339 | { | |
7340 | s += 3; | |
7341 | regno = FP; | |
7342 | } | |
7343 | else if (s[1] == 's' && s[2] == 'p') | |
7344 | { | |
7345 | s += 3; | |
7346 | regno = SP; | |
7347 | } | |
7348 | else if (s[1] == 'g' && s[2] == 'p') | |
7349 | { | |
7350 | s += 3; | |
7351 | regno = GP; | |
7352 | } | |
7353 | else if (s[1] == 'a' && s[2] == 't') | |
7354 | { | |
7355 | s += 3; | |
7356 | regno = AT; | |
7357 | } | |
7358 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '0') | |
7359 | { | |
7360 | s += 4; | |
7361 | regno = KT0; | |
7362 | } | |
7363 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '1') | |
7364 | { | |
7365 | s += 4; | |
7366 | regno = KT1; | |
7367 | } | |
7368 | else if (itbl_have_entries) | |
7369 | { | |
7370 | char *p, *n; | |
d7ba4a77 | 7371 | unsigned long r; |
252b5132 | 7372 | |
d7ba4a77 | 7373 | p = s + 1; /* advance past '$' */ |
252b5132 RH |
7374 | n = itbl_get_field (&p); /* n is name */ |
7375 | ||
d7ba4a77 ILT |
7376 | /* See if this is a register defined in an |
7377 | itbl entry. */ | |
7378 | if (itbl_get_reg_val (n, &r)) | |
252b5132 RH |
7379 | { |
7380 | /* Get_field advances to the start of | |
7381 | the next field, so we need to back | |
d7ba4a77 | 7382 | rack to the end of the last field. */ |
bdaaa2e1 | 7383 | if (p) |
252b5132 | 7384 | s = p - 1; |
bdaaa2e1 | 7385 | else |
d7ba4a77 | 7386 | s = strchr (s, '\0'); |
252b5132 RH |
7387 | regno = r; |
7388 | } | |
7389 | else | |
7390 | goto notreg; | |
beae10d5 | 7391 | } |
252b5132 RH |
7392 | else |
7393 | goto notreg; | |
7394 | } | |
7395 | if (regno == AT | |
7396 | && ! mips_opts.noat | |
7397 | && *args != 'E' | |
7398 | && *args != 'G') | |
7399 | as_warn (_("Used $at without \".set noat\"")); | |
7400 | c = *args; | |
7401 | if (*s == ' ') | |
7402 | s++; | |
7403 | if (args[1] != *s) | |
7404 | { | |
7405 | if (c == 'r' || c == 'v' || c == 'w') | |
7406 | { | |
7407 | regno = lastregno; | |
7408 | s = s_reset; | |
7409 | args++; | |
7410 | } | |
7411 | } | |
7412 | /* 'z' only matches $0. */ | |
7413 | if (c == 'z' && regno != 0) | |
7414 | break; | |
7415 | ||
bdaaa2e1 KH |
7416 | /* Now that we have assembled one operand, we use the args string |
7417 | * to figure out where it goes in the instruction. */ | |
252b5132 RH |
7418 | switch (c) |
7419 | { | |
7420 | case 'r': | |
7421 | case 's': | |
7422 | case 'v': | |
7423 | case 'b': | |
7424 | ip->insn_opcode |= regno << 21; | |
7425 | break; | |
7426 | case 'd': | |
7427 | case 'G': | |
7428 | ip->insn_opcode |= regno << 11; | |
7429 | break; | |
4372b673 NC |
7430 | case 'U': |
7431 | ip->insn_opcode |= regno << 11; | |
7432 | ip->insn_opcode |= regno << 16; | |
7433 | break; | |
252b5132 RH |
7434 | case 'w': |
7435 | case 't': | |
7436 | case 'E': | |
7437 | ip->insn_opcode |= regno << 16; | |
7438 | break; | |
7439 | case 'x': | |
7440 | /* This case exists because on the r3000 trunc | |
7441 | expands into a macro which requires a gp | |
7442 | register. On the r6000 or r4000 it is | |
7443 | assembled into a single instruction which | |
7444 | ignores the register. Thus the insn version | |
7445 | is MIPS_ISA2 and uses 'x', and the macro | |
7446 | version is MIPS_ISA1 and uses 't'. */ | |
7447 | break; | |
7448 | case 'z': | |
7449 | /* This case is for the div instruction, which | |
7450 | acts differently if the destination argument | |
7451 | is $0. This only matches $0, and is checked | |
7452 | outside the switch. */ | |
7453 | break; | |
7454 | case 'D': | |
7455 | /* Itbl operand; not yet implemented. FIXME ?? */ | |
7456 | break; | |
7457 | /* What about all other operands like 'i', which | |
7458 | can be specified in the opcode table? */ | |
7459 | } | |
7460 | lastregno = regno; | |
7461 | continue; | |
7462 | } | |
7463 | notreg: | |
7464 | switch (*args++) | |
7465 | { | |
7466 | case 'r': | |
7467 | case 'v': | |
7468 | ip->insn_opcode |= lastregno << 21; | |
7469 | continue; | |
7470 | case 'w': | |
7471 | ip->insn_opcode |= lastregno << 16; | |
7472 | continue; | |
7473 | } | |
7474 | break; | |
7475 | ||
7476 | case 'D': /* floating point destination register */ | |
7477 | case 'S': /* floating point source register */ | |
7478 | case 'T': /* floating point target register */ | |
7479 | case 'R': /* floating point source register */ | |
7480 | case 'V': | |
7481 | case 'W': | |
7482 | s_reset = s; | |
d9a62219 | 7483 | if (s[0] == '$' && s[1] == 'f' && isdigit ((unsigned char) s[2])) |
252b5132 RH |
7484 | { |
7485 | s += 2; | |
7486 | regno = 0; | |
7487 | do | |
7488 | { | |
7489 | regno *= 10; | |
7490 | regno += *s - '0'; | |
7491 | ++s; | |
7492 | } | |
d9a62219 | 7493 | while (isdigit ((unsigned char) *s)); |
252b5132 RH |
7494 | |
7495 | if (regno > 31) | |
7496 | as_bad (_("Invalid float register number (%d)"), regno); | |
7497 | ||
7498 | if ((regno & 1) != 0 | |
9ce8a5dd | 7499 | && ! ISA_HAS_64BIT_REGS (mips_opts.isa) |
252b5132 RH |
7500 | && ! (strcmp (str, "mtc1") == 0 |
7501 | || strcmp (str, "mfc1") == 0 | |
7502 | || strcmp (str, "lwc1") == 0 | |
7503 | || strcmp (str, "swc1") == 0 | |
7504 | || strcmp (str, "l.s") == 0 | |
7505 | || strcmp (str, "s.s") == 0)) | |
7506 | as_warn (_("Float register should be even, was %d"), | |
7507 | regno); | |
7508 | ||
7509 | c = *args; | |
7510 | if (*s == ' ') | |
7511 | s++; | |
7512 | if (args[1] != *s) | |
7513 | { | |
7514 | if (c == 'V' || c == 'W') | |
7515 | { | |
7516 | regno = lastregno; | |
7517 | s = s_reset; | |
7518 | args++; | |
7519 | } | |
7520 | } | |
7521 | switch (c) | |
7522 | { | |
7523 | case 'D': | |
7524 | ip->insn_opcode |= regno << 6; | |
7525 | break; | |
7526 | case 'V': | |
7527 | case 'S': | |
7528 | ip->insn_opcode |= regno << 11; | |
7529 | break; | |
7530 | case 'W': | |
7531 | case 'T': | |
7532 | ip->insn_opcode |= regno << 16; | |
7533 | break; | |
7534 | case 'R': | |
7535 | ip->insn_opcode |= regno << 21; | |
7536 | break; | |
7537 | } | |
7538 | lastregno = regno; | |
7539 | continue; | |
7540 | } | |
7541 | ||
252b5132 RH |
7542 | switch (*args++) |
7543 | { | |
7544 | case 'V': | |
7545 | ip->insn_opcode |= lastregno << 11; | |
7546 | continue; | |
7547 | case 'W': | |
7548 | ip->insn_opcode |= lastregno << 16; | |
7549 | continue; | |
7550 | } | |
7551 | break; | |
7552 | ||
7553 | case 'I': | |
7554 | my_getExpression (&imm_expr, s); | |
7555 | if (imm_expr.X_op != O_big | |
7556 | && imm_expr.X_op != O_constant) | |
7557 | insn_error = _("absolute expression required"); | |
7558 | s = expr_end; | |
7559 | continue; | |
7560 | ||
7561 | case 'A': | |
7562 | my_getExpression (&offset_expr, s); | |
7563 | imm_reloc = BFD_RELOC_32; | |
7564 | s = expr_end; | |
7565 | continue; | |
7566 | ||
7567 | case 'F': | |
7568 | case 'L': | |
7569 | case 'f': | |
7570 | case 'l': | |
7571 | { | |
7572 | int f64; | |
7573 | char *save_in; | |
7574 | char *err; | |
7575 | unsigned char temp[8]; | |
7576 | int len; | |
7577 | unsigned int length; | |
7578 | segT seg; | |
7579 | subsegT subseg; | |
7580 | char *p; | |
7581 | ||
7582 | /* These only appear as the last operand in an | |
7583 | instruction, and every instruction that accepts | |
7584 | them in any variant accepts them in all variants. | |
7585 | This means we don't have to worry about backing out | |
7586 | any changes if the instruction does not match. | |
7587 | ||
7588 | The difference between them is the size of the | |
7589 | floating point constant and where it goes. For 'F' | |
7590 | and 'L' the constant is 64 bits; for 'f' and 'l' it | |
7591 | is 32 bits. Where the constant is placed is based | |
7592 | on how the MIPS assembler does things: | |
7593 | F -- .rdata | |
7594 | L -- .lit8 | |
7595 | f -- immediate value | |
7596 | l -- .lit4 | |
7597 | ||
7598 | The .lit4 and .lit8 sections are only used if | |
7599 | permitted by the -G argument. | |
7600 | ||
7601 | When generating embedded PIC code, we use the | |
7602 | .lit8 section but not the .lit4 section (we can do | |
7603 | .lit4 inline easily; we need to put .lit8 | |
7604 | somewhere in the data segment, and using .lit8 | |
7605 | permits the linker to eventually combine identical | |
7606 | .lit8 entries). */ | |
7607 | ||
7608 | f64 = *args == 'F' || *args == 'L'; | |
7609 | ||
7610 | save_in = input_line_pointer; | |
7611 | input_line_pointer = s; | |
7612 | err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len); | |
7613 | length = len; | |
7614 | s = input_line_pointer; | |
7615 | input_line_pointer = save_in; | |
7616 | if (err != NULL && *err != '\0') | |
7617 | { | |
7618 | as_bad (_("Bad floating point constant: %s"), err); | |
7619 | memset (temp, '\0', sizeof temp); | |
7620 | length = f64 ? 8 : 4; | |
7621 | } | |
7622 | ||
156c2f8b | 7623 | assert (length == (unsigned) (f64 ? 8 : 4)); |
252b5132 RH |
7624 | |
7625 | if (*args == 'f' | |
7626 | || (*args == 'l' | |
7627 | && (! USE_GLOBAL_POINTER_OPT | |
7628 | || mips_pic == EMBEDDED_PIC | |
7629 | || g_switch_value < 4 | |
7630 | || (temp[0] == 0 && temp[1] == 0) | |
7631 | || (temp[2] == 0 && temp[3] == 0)))) | |
7632 | { | |
7633 | imm_expr.X_op = O_constant; | |
7634 | if (! target_big_endian) | |
7635 | imm_expr.X_add_number = bfd_getl32 (temp); | |
7636 | else | |
7637 | imm_expr.X_add_number = bfd_getb32 (temp); | |
7638 | } | |
7639 | else if (length > 4 | |
119d663a | 7640 | && ! mips_disable_float_construction |
252b5132 RH |
7641 | && ((temp[0] == 0 && temp[1] == 0) |
7642 | || (temp[2] == 0 && temp[3] == 0)) | |
7643 | && ((temp[4] == 0 && temp[5] == 0) | |
7644 | || (temp[6] == 0 && temp[7] == 0))) | |
7645 | { | |
7646 | /* The value is simple enough to load with a | |
7647 | couple of instructions. In mips1 mode, set | |
7648 | imm_expr to the high order 32 bits and | |
7649 | offset_expr to the low order 32 bits. | |
7650 | Otherwise, set imm_expr to the entire 64 bit | |
7651 | constant. */ | |
9ce8a5dd | 7652 | if (! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
7653 | { |
7654 | imm_expr.X_op = O_constant; | |
7655 | offset_expr.X_op = O_constant; | |
7656 | if (! target_big_endian) | |
7657 | { | |
7658 | imm_expr.X_add_number = bfd_getl32 (temp + 4); | |
7659 | offset_expr.X_add_number = bfd_getl32 (temp); | |
7660 | } | |
7661 | else | |
7662 | { | |
7663 | imm_expr.X_add_number = bfd_getb32 (temp); | |
7664 | offset_expr.X_add_number = bfd_getb32 (temp + 4); | |
7665 | } | |
7666 | if (offset_expr.X_add_number == 0) | |
7667 | offset_expr.X_op = O_absent; | |
7668 | } | |
7669 | else if (sizeof (imm_expr.X_add_number) > 4) | |
7670 | { | |
7671 | imm_expr.X_op = O_constant; | |
7672 | if (! target_big_endian) | |
7673 | imm_expr.X_add_number = bfd_getl64 (temp); | |
7674 | else | |
7675 | imm_expr.X_add_number = bfd_getb64 (temp); | |
7676 | } | |
7677 | else | |
7678 | { | |
7679 | imm_expr.X_op = O_big; | |
7680 | imm_expr.X_add_number = 4; | |
7681 | if (! target_big_endian) | |
7682 | { | |
7683 | generic_bignum[0] = bfd_getl16 (temp); | |
7684 | generic_bignum[1] = bfd_getl16 (temp + 2); | |
7685 | generic_bignum[2] = bfd_getl16 (temp + 4); | |
7686 | generic_bignum[3] = bfd_getl16 (temp + 6); | |
7687 | } | |
7688 | else | |
7689 | { | |
7690 | generic_bignum[0] = bfd_getb16 (temp + 6); | |
7691 | generic_bignum[1] = bfd_getb16 (temp + 4); | |
7692 | generic_bignum[2] = bfd_getb16 (temp + 2); | |
7693 | generic_bignum[3] = bfd_getb16 (temp); | |
7694 | } | |
7695 | } | |
7696 | } | |
7697 | else | |
7698 | { | |
7699 | const char *newname; | |
7700 | segT new_seg; | |
7701 | ||
7702 | /* Switch to the right section. */ | |
7703 | seg = now_seg; | |
7704 | subseg = now_subseg; | |
7705 | switch (*args) | |
7706 | { | |
7707 | default: /* unused default case avoids warnings. */ | |
7708 | case 'L': | |
7709 | newname = RDATA_SECTION_NAME; | |
bb2d6cd7 GK |
7710 | if ((USE_GLOBAL_POINTER_OPT && g_switch_value >= 8) |
7711 | || mips_pic == EMBEDDED_PIC) | |
252b5132 RH |
7712 | newname = ".lit8"; |
7713 | break; | |
7714 | case 'F': | |
bb2d6cd7 GK |
7715 | if (mips_pic == EMBEDDED_PIC) |
7716 | newname = ".lit8"; | |
7717 | else | |
7718 | newname = RDATA_SECTION_NAME; | |
252b5132 RH |
7719 | break; |
7720 | case 'l': | |
7721 | assert (!USE_GLOBAL_POINTER_OPT | |
7722 | || g_switch_value >= 4); | |
7723 | newname = ".lit4"; | |
7724 | break; | |
7725 | } | |
7726 | new_seg = subseg_new (newname, (subsegT) 0); | |
7727 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
7728 | bfd_set_section_flags (stdoutput, new_seg, | |
7729 | (SEC_ALLOC | |
7730 | | SEC_LOAD | |
7731 | | SEC_READONLY | |
7732 | | SEC_DATA)); | |
7733 | frag_align (*args == 'l' ? 2 : 3, 0, 0); | |
7734 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour | |
7735 | && strcmp (TARGET_OS, "elf") != 0) | |
7736 | record_alignment (new_seg, 4); | |
7737 | else | |
7738 | record_alignment (new_seg, *args == 'l' ? 2 : 3); | |
7739 | if (seg == now_seg) | |
7740 | as_bad (_("Can't use floating point insn in this section")); | |
7741 | ||
7742 | /* Set the argument to the current address in the | |
7743 | section. */ | |
7744 | offset_expr.X_op = O_symbol; | |
7745 | offset_expr.X_add_symbol = | |
7746 | symbol_new ("L0\001", now_seg, | |
7747 | (valueT) frag_now_fix (), frag_now); | |
7748 | offset_expr.X_add_number = 0; | |
7749 | ||
7750 | /* Put the floating point number into the section. */ | |
7751 | p = frag_more ((int) length); | |
7752 | memcpy (p, temp, length); | |
7753 | ||
7754 | /* Switch back to the original section. */ | |
7755 | subseg_set (seg, subseg); | |
7756 | } | |
7757 | } | |
7758 | continue; | |
7759 | ||
7760 | case 'i': /* 16 bit unsigned immediate */ | |
7761 | case 'j': /* 16 bit signed immediate */ | |
7762 | imm_reloc = BFD_RELOC_LO16; | |
7763 | c = my_getSmallExpression (&imm_expr, s); | |
7764 | if (c != '\0') | |
7765 | { | |
7766 | if (c != 'l') | |
7767 | { | |
7768 | if (imm_expr.X_op == O_constant) | |
7769 | imm_expr.X_add_number = | |
7770 | (imm_expr.X_add_number >> 16) & 0xffff; | |
7771 | else if (c == 'h') | |
7772 | { | |
7773 | imm_reloc = BFD_RELOC_HI16_S; | |
7774 | imm_unmatched_hi = true; | |
7775 | } | |
7776 | else | |
7777 | imm_reloc = BFD_RELOC_HI16; | |
7778 | } | |
7779 | else if (imm_expr.X_op == O_constant) | |
7780 | imm_expr.X_add_number &= 0xffff; | |
7781 | } | |
7782 | if (*args == 'i') | |
7783 | { | |
7784 | if ((c == '\0' && imm_expr.X_op != O_constant) | |
7785 | || ((imm_expr.X_add_number < 0 | |
beae10d5 KH |
7786 | || imm_expr.X_add_number >= 0x10000) |
7787 | && imm_expr.X_op == O_constant)) | |
252b5132 RH |
7788 | { |
7789 | if (insn + 1 < &mips_opcodes[NUMOPCODES] && | |
7790 | !strcmp (insn->name, insn[1].name)) | |
7791 | break; | |
2ae7e77b AH |
7792 | if (imm_expr.X_op == O_constant |
7793 | || imm_expr.X_op == O_big) | |
252b5132 RH |
7794 | as_bad (_("16 bit expression not in range 0..65535")); |
7795 | } | |
7796 | } | |
7797 | else | |
7798 | { | |
7799 | int more; | |
7800 | offsetT max; | |
7801 | ||
7802 | /* The upper bound should be 0x8000, but | |
7803 | unfortunately the MIPS assembler accepts numbers | |
7804 | from 0x8000 to 0xffff and sign extends them, and | |
7805 | we want to be compatible. We only permit this | |
7806 | extended range for an instruction which does not | |
7807 | provide any further alternates, since those | |
7808 | alternates may handle other cases. People should | |
7809 | use the numbers they mean, rather than relying on | |
7810 | a mysterious sign extension. */ | |
7811 | more = (insn + 1 < &mips_opcodes[NUMOPCODES] && | |
7812 | strcmp (insn->name, insn[1].name) == 0); | |
7813 | if (more) | |
7814 | max = 0x8000; | |
7815 | else | |
7816 | max = 0x10000; | |
7817 | if ((c == '\0' && imm_expr.X_op != O_constant) | |
7818 | || ((imm_expr.X_add_number < -0x8000 | |
beae10d5 KH |
7819 | || imm_expr.X_add_number >= max) |
7820 | && imm_expr.X_op == O_constant) | |
252b5132 RH |
7821 | || (more |
7822 | && imm_expr.X_add_number < 0 | |
9ce8a5dd | 7823 | && ISA_HAS_64BIT_REGS (mips_opts.isa) |
252b5132 RH |
7824 | && imm_expr.X_unsigned |
7825 | && sizeof (imm_expr.X_add_number) <= 4)) | |
7826 | { | |
7827 | if (more) | |
7828 | break; | |
2ae7e77b AH |
7829 | if (imm_expr.X_op == O_constant |
7830 | || imm_expr.X_op == O_big) | |
252b5132 RH |
7831 | as_bad (_("16 bit expression not in range -32768..32767")); |
7832 | } | |
7833 | } | |
7834 | s = expr_end; | |
7835 | continue; | |
7836 | ||
7837 | case 'o': /* 16 bit offset */ | |
7838 | c = my_getSmallExpression (&offset_expr, s); | |
7839 | ||
7840 | /* If this value won't fit into a 16 bit offset, then go | |
7841 | find a macro that will generate the 32 bit offset | |
7842 | code pattern. As a special hack, we accept the | |
7843 | difference of two local symbols as a constant. This | |
7844 | is required to suppose embedded PIC switches, which | |
7845 | use an instruction which looks like | |
7846 | lw $4,$L12-$LS12($4) | |
7847 | The problem with handling this in a more general | |
7848 | fashion is that the macro function doesn't expect to | |
7849 | see anything which can be handled in a single | |
7850 | constant instruction. */ | |
7851 | if (c == 0 | |
7852 | && (offset_expr.X_op != O_constant | |
7853 | || offset_expr.X_add_number >= 0x8000 | |
7854 | || offset_expr.X_add_number < -0x8000) | |
7855 | && (mips_pic != EMBEDDED_PIC | |
7856 | || offset_expr.X_op != O_subtract | |
3dacdf2e NC |
7857 | || (S_GET_SEGMENT (offset_expr.X_add_symbol) |
7858 | != S_GET_SEGMENT (offset_expr.X_op_symbol)))) | |
252b5132 RH |
7859 | break; |
7860 | ||
7861 | if (c == 'h' || c == 'H') | |
7862 | { | |
7863 | if (offset_expr.X_op != O_constant) | |
7864 | break; | |
7865 | offset_expr.X_add_number = | |
7866 | (offset_expr.X_add_number >> 16) & 0xffff; | |
7867 | } | |
7868 | offset_reloc = BFD_RELOC_LO16; | |
7869 | s = expr_end; | |
7870 | continue; | |
7871 | ||
7872 | case 'p': /* pc relative offset */ | |
7873 | offset_reloc = BFD_RELOC_16_PCREL_S2; | |
7874 | my_getExpression (&offset_expr, s); | |
7875 | s = expr_end; | |
7876 | continue; | |
7877 | ||
7878 | case 'u': /* upper 16 bits */ | |
7879 | c = my_getSmallExpression (&imm_expr, s); | |
7880 | imm_reloc = BFD_RELOC_LO16; | |
7881 | if (c) | |
7882 | { | |
7883 | if (c != 'l') | |
7884 | { | |
7885 | if (imm_expr.X_op == O_constant) | |
7886 | imm_expr.X_add_number = | |
7887 | (imm_expr.X_add_number >> 16) & 0xffff; | |
7888 | else if (c == 'h') | |
7889 | { | |
7890 | imm_reloc = BFD_RELOC_HI16_S; | |
7891 | imm_unmatched_hi = true; | |
7892 | } | |
7893 | else | |
7894 | imm_reloc = BFD_RELOC_HI16; | |
7895 | } | |
7896 | else if (imm_expr.X_op == O_constant) | |
7897 | imm_expr.X_add_number &= 0xffff; | |
7898 | } | |
7899 | if (imm_expr.X_op == O_constant | |
7900 | && (imm_expr.X_add_number < 0 | |
7901 | || imm_expr.X_add_number >= 0x10000)) | |
7902 | as_bad (_("lui expression not in range 0..65535")); | |
7903 | s = expr_end; | |
7904 | continue; | |
7905 | ||
7906 | case 'a': /* 26 bit address */ | |
7907 | my_getExpression (&offset_expr, s); | |
7908 | s = expr_end; | |
7909 | offset_reloc = BFD_RELOC_MIPS_JMP; | |
7910 | continue; | |
7911 | ||
7912 | case 'N': /* 3 bit branch condition code */ | |
7913 | case 'M': /* 3 bit compare condition code */ | |
7914 | if (strncmp (s, "$fcc", 4) != 0) | |
7915 | break; | |
7916 | s += 4; | |
7917 | regno = 0; | |
7918 | do | |
7919 | { | |
7920 | regno *= 10; | |
7921 | regno += *s - '0'; | |
7922 | ++s; | |
7923 | } | |
d9a62219 | 7924 | while (isdigit ((unsigned char) *s)); |
252b5132 RH |
7925 | if (regno > 7) |
7926 | as_bad (_("invalid condition code register $fcc%d"), regno); | |
7927 | if (*args == 'N') | |
7928 | ip->insn_opcode |= regno << OP_SH_BCC; | |
7929 | else | |
7930 | ip->insn_opcode |= regno << OP_SH_CCC; | |
beae10d5 | 7931 | continue; |
252b5132 | 7932 | |
156c2f8b NC |
7933 | case 'H': |
7934 | if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X')) | |
7935 | s += 2; | |
7936 | if (isdigit ((unsigned char) *s)) | |
7937 | { | |
7938 | c = 0; | |
7939 | do | |
7940 | { | |
7941 | c *= 10; | |
7942 | c += *s - '0'; | |
7943 | ++s; | |
7944 | } | |
7945 | while (isdigit ((unsigned char) *s)); | |
7946 | } | |
7947 | else | |
7948 | c = 8; /* Invalid sel value. */ | |
7949 | ||
7950 | if (c > 7) | |
7951 | as_bad (_("invalid coprocessor sub-selection value (0-7)")); | |
7952 | ip->insn_opcode |= c; | |
7953 | continue; | |
7954 | ||
252b5132 RH |
7955 | default: |
7956 | as_bad (_("bad char = '%c'\n"), *args); | |
7957 | internalError (); | |
7958 | } | |
7959 | break; | |
7960 | } | |
7961 | /* Args don't match. */ | |
7962 | if (insn + 1 < &mips_opcodes[NUMOPCODES] && | |
7963 | !strcmp (insn->name, insn[1].name)) | |
7964 | { | |
7965 | ++insn; | |
7966 | s = argsStart; | |
268f6bed | 7967 | insn_error = _("illegal operands"); |
252b5132 RH |
7968 | continue; |
7969 | } | |
268f6bed L |
7970 | if (save_c) |
7971 | *(--s) = save_c; | |
252b5132 RH |
7972 | insn_error = _("illegal operands"); |
7973 | return; | |
7974 | } | |
7975 | } | |
7976 | ||
7977 | /* This routine assembles an instruction into its binary format when | |
7978 | assembling for the mips16. As a side effect, it sets one of the | |
7979 | global variables imm_reloc or offset_reloc to the type of | |
7980 | relocation to do if one of the operands is an address expression. | |
7981 | It also sets mips16_small and mips16_ext if the user explicitly | |
7982 | requested a small or extended instruction. */ | |
7983 | ||
7984 | static void | |
7985 | mips16_ip (str, ip) | |
7986 | char *str; | |
7987 | struct mips_cl_insn *ip; | |
7988 | { | |
7989 | char *s; | |
7990 | const char *args; | |
7991 | struct mips_opcode *insn; | |
7992 | char *argsstart; | |
7993 | unsigned int regno; | |
7994 | unsigned int lastregno = 0; | |
7995 | char *s_reset; | |
7996 | ||
7997 | insn_error = NULL; | |
7998 | ||
7999 | mips16_small = false; | |
8000 | mips16_ext = false; | |
8001 | ||
d9a62219 | 8002 | for (s = str; islower ((unsigned char) *s); ++s) |
252b5132 RH |
8003 | ; |
8004 | switch (*s) | |
8005 | { | |
8006 | case '\0': | |
8007 | break; | |
8008 | ||
8009 | case ' ': | |
8010 | *s++ = '\0'; | |
8011 | break; | |
8012 | ||
8013 | case '.': | |
8014 | if (s[1] == 't' && s[2] == ' ') | |
8015 | { | |
8016 | *s = '\0'; | |
8017 | mips16_small = true; | |
8018 | s += 3; | |
8019 | break; | |
8020 | } | |
8021 | else if (s[1] == 'e' && s[2] == ' ') | |
8022 | { | |
8023 | *s = '\0'; | |
8024 | mips16_ext = true; | |
8025 | s += 3; | |
8026 | break; | |
8027 | } | |
8028 | /* Fall through. */ | |
8029 | default: | |
8030 | insn_error = _("unknown opcode"); | |
8031 | return; | |
8032 | } | |
8033 | ||
8034 | if (mips_opts.noautoextend && ! mips16_ext) | |
8035 | mips16_small = true; | |
8036 | ||
8037 | if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL) | |
8038 | { | |
8039 | insn_error = _("unrecognized opcode"); | |
8040 | return; | |
8041 | } | |
8042 | ||
8043 | argsstart = s; | |
8044 | for (;;) | |
8045 | { | |
8046 | assert (strcmp (insn->name, str) == 0); | |
8047 | ||
8048 | ip->insn_mo = insn; | |
8049 | ip->insn_opcode = insn->match; | |
8050 | ip->use_extend = false; | |
8051 | imm_expr.X_op = O_absent; | |
8052 | imm_reloc = BFD_RELOC_UNUSED; | |
8053 | offset_expr.X_op = O_absent; | |
8054 | offset_reloc = BFD_RELOC_UNUSED; | |
8055 | for (args = insn->args; 1; ++args) | |
8056 | { | |
8057 | int c; | |
8058 | ||
8059 | if (*s == ' ') | |
8060 | ++s; | |
8061 | ||
8062 | /* In this switch statement we call break if we did not find | |
8063 | a match, continue if we did find a match, or return if we | |
8064 | are done. */ | |
8065 | ||
8066 | c = *args; | |
8067 | switch (c) | |
8068 | { | |
8069 | case '\0': | |
8070 | if (*s == '\0') | |
8071 | { | |
8072 | /* Stuff the immediate value in now, if we can. */ | |
8073 | if (imm_expr.X_op == O_constant | |
8074 | && imm_reloc > BFD_RELOC_UNUSED | |
8075 | && insn->pinfo != INSN_MACRO) | |
8076 | { | |
8077 | mips16_immed ((char *) NULL, 0, | |
8078 | imm_reloc - BFD_RELOC_UNUSED, | |
8079 | imm_expr.X_add_number, true, mips16_small, | |
8080 | mips16_ext, &ip->insn_opcode, | |
8081 | &ip->use_extend, &ip->extend); | |
8082 | imm_expr.X_op = O_absent; | |
8083 | imm_reloc = BFD_RELOC_UNUSED; | |
8084 | } | |
8085 | ||
8086 | return; | |
8087 | } | |
8088 | break; | |
8089 | ||
8090 | case ',': | |
8091 | if (*s++ == c) | |
8092 | continue; | |
8093 | s--; | |
8094 | switch (*++args) | |
8095 | { | |
8096 | case 'v': | |
8097 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RX; | |
8098 | continue; | |
8099 | case 'w': | |
8100 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RY; | |
8101 | continue; | |
8102 | } | |
8103 | break; | |
8104 | ||
8105 | case '(': | |
8106 | case ')': | |
8107 | if (*s++ == c) | |
8108 | continue; | |
8109 | break; | |
8110 | ||
8111 | case 'v': | |
8112 | case 'w': | |
8113 | if (s[0] != '$') | |
8114 | { | |
8115 | if (c == 'v') | |
8116 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RX; | |
8117 | else | |
8118 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RY; | |
8119 | ++args; | |
8120 | continue; | |
8121 | } | |
8122 | /* Fall through. */ | |
8123 | case 'x': | |
8124 | case 'y': | |
8125 | case 'z': | |
8126 | case 'Z': | |
8127 | case '0': | |
8128 | case 'S': | |
8129 | case 'R': | |
8130 | case 'X': | |
8131 | case 'Y': | |
8132 | if (s[0] != '$') | |
8133 | break; | |
8134 | s_reset = s; | |
d9a62219 | 8135 | if (isdigit ((unsigned char) s[1])) |
252b5132 RH |
8136 | { |
8137 | ++s; | |
8138 | regno = 0; | |
8139 | do | |
8140 | { | |
8141 | regno *= 10; | |
8142 | regno += *s - '0'; | |
8143 | ++s; | |
8144 | } | |
d9a62219 | 8145 | while (isdigit ((unsigned char) *s)); |
252b5132 RH |
8146 | if (regno > 31) |
8147 | { | |
8148 | as_bad (_("invalid register number (%d)"), regno); | |
8149 | regno = 2; | |
8150 | } | |
8151 | } | |
8152 | else | |
8153 | { | |
8154 | if (s[1] == 'f' && s[2] == 'p') | |
8155 | { | |
8156 | s += 3; | |
8157 | regno = FP; | |
8158 | } | |
8159 | else if (s[1] == 's' && s[2] == 'p') | |
8160 | { | |
8161 | s += 3; | |
8162 | regno = SP; | |
8163 | } | |
8164 | else if (s[1] == 'g' && s[2] == 'p') | |
8165 | { | |
8166 | s += 3; | |
8167 | regno = GP; | |
8168 | } | |
8169 | else if (s[1] == 'a' && s[2] == 't') | |
8170 | { | |
8171 | s += 3; | |
8172 | regno = AT; | |
8173 | } | |
8174 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '0') | |
8175 | { | |
8176 | s += 4; | |
8177 | regno = KT0; | |
8178 | } | |
8179 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '1') | |
8180 | { | |
8181 | s += 4; | |
8182 | regno = KT1; | |
8183 | } | |
8184 | else | |
8185 | break; | |
8186 | } | |
8187 | ||
8188 | if (*s == ' ') | |
8189 | ++s; | |
8190 | if (args[1] != *s) | |
8191 | { | |
8192 | if (c == 'v' || c == 'w') | |
8193 | { | |
8194 | regno = mips16_to_32_reg_map[lastregno]; | |
8195 | s = s_reset; | |
8196 | args++; | |
8197 | } | |
8198 | } | |
8199 | ||
8200 | switch (c) | |
8201 | { | |
8202 | case 'x': | |
8203 | case 'y': | |
8204 | case 'z': | |
8205 | case 'v': | |
8206 | case 'w': | |
8207 | case 'Z': | |
8208 | regno = mips32_to_16_reg_map[regno]; | |
8209 | break; | |
8210 | ||
8211 | case '0': | |
8212 | if (regno != 0) | |
8213 | regno = ILLEGAL_REG; | |
8214 | break; | |
8215 | ||
8216 | case 'S': | |
8217 | if (regno != SP) | |
8218 | regno = ILLEGAL_REG; | |
8219 | break; | |
8220 | ||
8221 | case 'R': | |
8222 | if (regno != RA) | |
8223 | regno = ILLEGAL_REG; | |
8224 | break; | |
8225 | ||
8226 | case 'X': | |
8227 | case 'Y': | |
8228 | if (regno == AT && ! mips_opts.noat) | |
8229 | as_warn (_("used $at without \".set noat\"")); | |
8230 | break; | |
8231 | ||
8232 | default: | |
8233 | internalError (); | |
8234 | } | |
8235 | ||
8236 | if (regno == ILLEGAL_REG) | |
8237 | break; | |
8238 | ||
8239 | switch (c) | |
8240 | { | |
8241 | case 'x': | |
8242 | case 'v': | |
8243 | ip->insn_opcode |= regno << MIPS16OP_SH_RX; | |
8244 | break; | |
8245 | case 'y': | |
8246 | case 'w': | |
8247 | ip->insn_opcode |= regno << MIPS16OP_SH_RY; | |
8248 | break; | |
8249 | case 'z': | |
8250 | ip->insn_opcode |= regno << MIPS16OP_SH_RZ; | |
8251 | break; | |
8252 | case 'Z': | |
8253 | ip->insn_opcode |= regno << MIPS16OP_SH_MOVE32Z; | |
8254 | case '0': | |
8255 | case 'S': | |
8256 | case 'R': | |
8257 | break; | |
8258 | case 'X': | |
8259 | ip->insn_opcode |= regno << MIPS16OP_SH_REGR32; | |
8260 | break; | |
8261 | case 'Y': | |
8262 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); | |
8263 | ip->insn_opcode |= regno << MIPS16OP_SH_REG32R; | |
8264 | break; | |
8265 | default: | |
8266 | internalError (); | |
8267 | } | |
8268 | ||
8269 | lastregno = regno; | |
8270 | continue; | |
8271 | ||
8272 | case 'P': | |
8273 | if (strncmp (s, "$pc", 3) == 0) | |
8274 | { | |
8275 | s += 3; | |
8276 | continue; | |
8277 | } | |
8278 | break; | |
8279 | ||
8280 | case '<': | |
8281 | case '>': | |
8282 | case '[': | |
8283 | case ']': | |
8284 | case '4': | |
8285 | case '5': | |
8286 | case 'H': | |
8287 | case 'W': | |
8288 | case 'D': | |
8289 | case 'j': | |
8290 | case '8': | |
8291 | case 'V': | |
8292 | case 'C': | |
8293 | case 'U': | |
8294 | case 'k': | |
8295 | case 'K': | |
8296 | if (s[0] == '%' | |
8297 | && strncmp (s + 1, "gprel(", sizeof "gprel(" - 1) == 0) | |
8298 | { | |
8299 | /* This is %gprel(SYMBOL). We need to read SYMBOL, | |
8300 | and generate the appropriate reloc. If the text | |
8301 | inside %gprel is not a symbol name with an | |
8302 | optional offset, then we generate a normal reloc | |
8303 | and will probably fail later. */ | |
8304 | my_getExpression (&imm_expr, s + sizeof "%gprel" - 1); | |
8305 | if (imm_expr.X_op == O_symbol) | |
8306 | { | |
8307 | mips16_ext = true; | |
8308 | imm_reloc = BFD_RELOC_MIPS16_GPREL; | |
8309 | s = expr_end; | |
8310 | ip->use_extend = true; | |
8311 | ip->extend = 0; | |
8312 | continue; | |
8313 | } | |
8314 | } | |
8315 | else | |
8316 | { | |
8317 | /* Just pick up a normal expression. */ | |
8318 | my_getExpression (&imm_expr, s); | |
8319 | } | |
8320 | ||
8321 | if (imm_expr.X_op == O_register) | |
8322 | { | |
8323 | /* What we thought was an expression turned out to | |
8324 | be a register. */ | |
8325 | ||
8326 | if (s[0] == '(' && args[1] == '(') | |
8327 | { | |
8328 | /* It looks like the expression was omitted | |
8329 | before a register indirection, which means | |
8330 | that the expression is implicitly zero. We | |
8331 | still set up imm_expr, so that we handle | |
8332 | explicit extensions correctly. */ | |
8333 | imm_expr.X_op = O_constant; | |
8334 | imm_expr.X_add_number = 0; | |
8335 | imm_reloc = (int) BFD_RELOC_UNUSED + c; | |
8336 | continue; | |
8337 | } | |
8338 | ||
8339 | break; | |
8340 | } | |
8341 | ||
8342 | /* We need to relax this instruction. */ | |
8343 | imm_reloc = (int) BFD_RELOC_UNUSED + c; | |
8344 | s = expr_end; | |
8345 | continue; | |
8346 | ||
8347 | case 'p': | |
8348 | case 'q': | |
8349 | case 'A': | |
8350 | case 'B': | |
8351 | case 'E': | |
8352 | /* We use offset_reloc rather than imm_reloc for the PC | |
8353 | relative operands. This lets macros with both | |
8354 | immediate and address operands work correctly. */ | |
8355 | my_getExpression (&offset_expr, s); | |
8356 | ||
8357 | if (offset_expr.X_op == O_register) | |
8358 | break; | |
8359 | ||
8360 | /* We need to relax this instruction. */ | |
8361 | offset_reloc = (int) BFD_RELOC_UNUSED + c; | |
8362 | s = expr_end; | |
8363 | continue; | |
8364 | ||
8365 | case '6': /* break code */ | |
8366 | my_getExpression (&imm_expr, s); | |
8367 | check_absolute_expr (ip, &imm_expr); | |
8368 | if ((unsigned long) imm_expr.X_add_number > 63) | |
8369 | { | |
8370 | as_warn (_("Invalid value for `%s' (%lu)"), | |
8371 | ip->insn_mo->name, | |
8372 | (unsigned long) imm_expr.X_add_number); | |
8373 | imm_expr.X_add_number &= 0x3f; | |
8374 | } | |
8375 | ip->insn_opcode |= imm_expr.X_add_number << MIPS16OP_SH_IMM6; | |
8376 | imm_expr.X_op = O_absent; | |
8377 | s = expr_end; | |
8378 | continue; | |
8379 | ||
8380 | case 'a': /* 26 bit address */ | |
8381 | my_getExpression (&offset_expr, s); | |
8382 | s = expr_end; | |
8383 | offset_reloc = BFD_RELOC_MIPS16_JMP; | |
8384 | ip->insn_opcode <<= 16; | |
8385 | continue; | |
8386 | ||
8387 | case 'l': /* register list for entry macro */ | |
8388 | case 'L': /* register list for exit macro */ | |
8389 | { | |
8390 | int mask; | |
8391 | ||
8392 | if (c == 'l') | |
8393 | mask = 0; | |
8394 | else | |
8395 | mask = 7 << 3; | |
8396 | while (*s != '\0') | |
8397 | { | |
8398 | int freg, reg1, reg2; | |
8399 | ||
8400 | while (*s == ' ' || *s == ',') | |
8401 | ++s; | |
8402 | if (*s != '$') | |
8403 | { | |
8404 | as_bad (_("can't parse register list")); | |
8405 | break; | |
8406 | } | |
8407 | ++s; | |
8408 | if (*s != 'f') | |
8409 | freg = 0; | |
8410 | else | |
8411 | { | |
8412 | freg = 1; | |
8413 | ++s; | |
8414 | } | |
8415 | reg1 = 0; | |
d9a62219 | 8416 | while (isdigit ((unsigned char) *s)) |
252b5132 RH |
8417 | { |
8418 | reg1 *= 10; | |
8419 | reg1 += *s - '0'; | |
8420 | ++s; | |
8421 | } | |
8422 | if (*s == ' ') | |
8423 | ++s; | |
8424 | if (*s != '-') | |
8425 | reg2 = reg1; | |
8426 | else | |
8427 | { | |
8428 | ++s; | |
8429 | if (*s != '$') | |
8430 | break; | |
8431 | ++s; | |
8432 | if (freg) | |
8433 | { | |
8434 | if (*s == 'f') | |
8435 | ++s; | |
8436 | else | |
8437 | { | |
8438 | as_bad (_("invalid register list")); | |
8439 | break; | |
8440 | } | |
8441 | } | |
8442 | reg2 = 0; | |
d9a62219 | 8443 | while (isdigit ((unsigned char) *s)) |
252b5132 RH |
8444 | { |
8445 | reg2 *= 10; | |
8446 | reg2 += *s - '0'; | |
8447 | ++s; | |
8448 | } | |
8449 | } | |
8450 | if (freg && reg1 == 0 && reg2 == 0 && c == 'L') | |
8451 | { | |
8452 | mask &= ~ (7 << 3); | |
8453 | mask |= 5 << 3; | |
8454 | } | |
8455 | else if (freg && reg1 == 0 && reg2 == 1 && c == 'L') | |
8456 | { | |
8457 | mask &= ~ (7 << 3); | |
8458 | mask |= 6 << 3; | |
8459 | } | |
8460 | else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L') | |
8461 | mask |= (reg2 - 3) << 3; | |
8462 | else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17) | |
8463 | mask |= (reg2 - 15) << 1; | |
8464 | else if (reg1 == 31 && reg2 == 31) | |
8465 | mask |= 1; | |
8466 | else | |
8467 | { | |
8468 | as_bad (_("invalid register list")); | |
8469 | break; | |
8470 | } | |
8471 | } | |
8472 | /* The mask is filled in in the opcode table for the | |
8473 | benefit of the disassembler. We remove it before | |
8474 | applying the actual mask. */ | |
8475 | ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6); | |
8476 | ip->insn_opcode |= mask << MIPS16OP_SH_IMM6; | |
8477 | } | |
8478 | continue; | |
8479 | ||
8480 | case 'e': /* extend code */ | |
8481 | my_getExpression (&imm_expr, s); | |
8482 | check_absolute_expr (ip, &imm_expr); | |
8483 | if ((unsigned long) imm_expr.X_add_number > 0x7ff) | |
8484 | { | |
8485 | as_warn (_("Invalid value for `%s' (%lu)"), | |
8486 | ip->insn_mo->name, | |
8487 | (unsigned long) imm_expr.X_add_number); | |
8488 | imm_expr.X_add_number &= 0x7ff; | |
8489 | } | |
8490 | ip->insn_opcode |= imm_expr.X_add_number; | |
8491 | imm_expr.X_op = O_absent; | |
8492 | s = expr_end; | |
8493 | continue; | |
8494 | ||
8495 | default: | |
8496 | internalError (); | |
8497 | } | |
8498 | break; | |
8499 | } | |
8500 | ||
8501 | /* Args don't match. */ | |
8502 | if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] && | |
8503 | strcmp (insn->name, insn[1].name) == 0) | |
8504 | { | |
8505 | ++insn; | |
8506 | s = argsstart; | |
8507 | continue; | |
8508 | } | |
8509 | ||
8510 | insn_error = _("illegal operands"); | |
8511 | ||
8512 | return; | |
8513 | } | |
8514 | } | |
8515 | ||
8516 | /* This structure holds information we know about a mips16 immediate | |
8517 | argument type. */ | |
8518 | ||
e972090a NC |
8519 | struct mips16_immed_operand |
8520 | { | |
252b5132 RH |
8521 | /* The type code used in the argument string in the opcode table. */ |
8522 | int type; | |
8523 | /* The number of bits in the short form of the opcode. */ | |
8524 | int nbits; | |
8525 | /* The number of bits in the extended form of the opcode. */ | |
8526 | int extbits; | |
8527 | /* The amount by which the short form is shifted when it is used; | |
8528 | for example, the sw instruction has a shift count of 2. */ | |
8529 | int shift; | |
8530 | /* The amount by which the short form is shifted when it is stored | |
8531 | into the instruction code. */ | |
8532 | int op_shift; | |
8533 | /* Non-zero if the short form is unsigned. */ | |
8534 | int unsp; | |
8535 | /* Non-zero if the extended form is unsigned. */ | |
8536 | int extu; | |
8537 | /* Non-zero if the value is PC relative. */ | |
8538 | int pcrel; | |
8539 | }; | |
8540 | ||
8541 | /* The mips16 immediate operand types. */ | |
8542 | ||
8543 | static const struct mips16_immed_operand mips16_immed_operands[] = | |
8544 | { | |
8545 | { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
8546 | { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
8547 | { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
8548 | { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
8549 | { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 }, | |
8550 | { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
8551 | { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
8552 | { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
8553 | { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
8554 | { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 }, | |
8555 | { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
8556 | { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
8557 | { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
8558 | { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 }, | |
8559 | { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
8560 | { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
8561 | { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
8562 | { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
8563 | { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 }, | |
8564 | { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 }, | |
8565 | { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 } | |
8566 | }; | |
8567 | ||
8568 | #define MIPS16_NUM_IMMED \ | |
8569 | (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0]) | |
8570 | ||
8571 | /* Handle a mips16 instruction with an immediate value. This or's the | |
8572 | small immediate value into *INSN. It sets *USE_EXTEND to indicate | |
8573 | whether an extended value is needed; if one is needed, it sets | |
8574 | *EXTEND to the value. The argument type is TYPE. The value is VAL. | |
8575 | If SMALL is true, an unextended opcode was explicitly requested. | |
8576 | If EXT is true, an extended opcode was explicitly requested. If | |
8577 | WARN is true, warn if EXT does not match reality. */ | |
8578 | ||
8579 | static void | |
8580 | mips16_immed (file, line, type, val, warn, small, ext, insn, use_extend, | |
8581 | extend) | |
8582 | char *file; | |
8583 | unsigned int line; | |
8584 | int type; | |
8585 | offsetT val; | |
8586 | boolean warn; | |
8587 | boolean small; | |
8588 | boolean ext; | |
8589 | unsigned long *insn; | |
8590 | boolean *use_extend; | |
8591 | unsigned short *extend; | |
8592 | { | |
8593 | register const struct mips16_immed_operand *op; | |
8594 | int mintiny, maxtiny; | |
8595 | boolean needext; | |
8596 | ||
8597 | op = mips16_immed_operands; | |
8598 | while (op->type != type) | |
8599 | { | |
8600 | ++op; | |
8601 | assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); | |
8602 | } | |
8603 | ||
8604 | if (op->unsp) | |
8605 | { | |
8606 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
8607 | { | |
8608 | mintiny = 1; | |
8609 | maxtiny = 1 << op->nbits; | |
8610 | } | |
8611 | else | |
8612 | { | |
8613 | mintiny = 0; | |
8614 | maxtiny = (1 << op->nbits) - 1; | |
8615 | } | |
8616 | } | |
8617 | else | |
8618 | { | |
8619 | mintiny = - (1 << (op->nbits - 1)); | |
8620 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
8621 | } | |
8622 | ||
8623 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
8624 | if (type == 'p' || type == 'q') | |
8625 | val /= 2; | |
8626 | ||
8627 | if ((val & ((1 << op->shift) - 1)) != 0 | |
8628 | || val < (mintiny << op->shift) | |
8629 | || val > (maxtiny << op->shift)) | |
8630 | needext = true; | |
8631 | else | |
8632 | needext = false; | |
8633 | ||
8634 | if (warn && ext && ! needext) | |
beae10d5 KH |
8635 | as_warn_where (file, line, |
8636 | _("extended operand requested but not required")); | |
252b5132 RH |
8637 | if (small && needext) |
8638 | as_bad_where (file, line, _("invalid unextended operand value")); | |
8639 | ||
8640 | if (small || (! ext && ! needext)) | |
8641 | { | |
8642 | int insnval; | |
8643 | ||
8644 | *use_extend = false; | |
8645 | insnval = ((val >> op->shift) & ((1 << op->nbits) - 1)); | |
8646 | insnval <<= op->op_shift; | |
8647 | *insn |= insnval; | |
8648 | } | |
8649 | else | |
8650 | { | |
8651 | long minext, maxext; | |
8652 | int extval; | |
8653 | ||
8654 | if (op->extu) | |
8655 | { | |
8656 | minext = 0; | |
8657 | maxext = (1 << op->extbits) - 1; | |
8658 | } | |
8659 | else | |
8660 | { | |
8661 | minext = - (1 << (op->extbits - 1)); | |
8662 | maxext = (1 << (op->extbits - 1)) - 1; | |
8663 | } | |
8664 | if (val < minext || val > maxext) | |
8665 | as_bad_where (file, line, | |
8666 | _("operand value out of range for instruction")); | |
8667 | ||
8668 | *use_extend = true; | |
8669 | if (op->extbits == 16) | |
8670 | { | |
8671 | extval = ((val >> 11) & 0x1f) | (val & 0x7e0); | |
8672 | val &= 0x1f; | |
8673 | } | |
8674 | else if (op->extbits == 15) | |
8675 | { | |
8676 | extval = ((val >> 11) & 0xf) | (val & 0x7f0); | |
8677 | val &= 0xf; | |
8678 | } | |
8679 | else | |
8680 | { | |
8681 | extval = ((val & 0x1f) << 6) | (val & 0x20); | |
8682 | val = 0; | |
8683 | } | |
8684 | ||
8685 | *extend = (unsigned short) extval; | |
8686 | *insn |= val; | |
8687 | } | |
8688 | } | |
8689 | \f | |
8690 | #define LP '(' | |
8691 | #define RP ')' | |
8692 | ||
8693 | static int | |
8694 | my_getSmallExpression (ep, str) | |
8695 | expressionS *ep; | |
8696 | char *str; | |
8697 | { | |
8698 | char *sp; | |
8699 | int c = 0; | |
8700 | ||
8701 | if (*str == ' ') | |
8702 | str++; | |
8703 | if (*str == LP | |
8704 | || (*str == '%' && | |
8705 | ((str[1] == 'h' && str[2] == 'i') | |
8706 | || (str[1] == 'H' && str[2] == 'I') | |
8707 | || (str[1] == 'l' && str[2] == 'o')) | |
8708 | && str[3] == LP)) | |
8709 | { | |
8710 | if (*str == LP) | |
8711 | c = 0; | |
8712 | else | |
8713 | { | |
8714 | c = str[1]; | |
8715 | str += 3; | |
8716 | } | |
8717 | ||
8718 | /* | |
8719 | * A small expression may be followed by a base register. | |
8720 | * Scan to the end of this operand, and then back over a possible | |
8721 | * base register. Then scan the small expression up to that | |
8722 | * point. (Based on code in sparc.c...) | |
8723 | */ | |
8724 | for (sp = str; *sp && *sp != ','; sp++) | |
8725 | ; | |
8726 | if (sp - 4 >= str && sp[-1] == RP) | |
8727 | { | |
d9a62219 | 8728 | if (isdigit ((unsigned char) sp[-2])) |
252b5132 | 8729 | { |
d9a62219 | 8730 | for (sp -= 3; sp >= str && isdigit ((unsigned char) *sp); sp--) |
252b5132 RH |
8731 | ; |
8732 | if (*sp == '$' && sp > str && sp[-1] == LP) | |
8733 | { | |
8734 | sp--; | |
8735 | goto do_it; | |
8736 | } | |
8737 | } | |
8738 | else if (sp - 5 >= str | |
8739 | && sp[-5] == LP | |
8740 | && sp[-4] == '$' | |
8741 | && ((sp[-3] == 'f' && sp[-2] == 'p') | |
8742 | || (sp[-3] == 's' && sp[-2] == 'p') | |
8743 | || (sp[-3] == 'g' && sp[-2] == 'p') | |
8744 | || (sp[-3] == 'a' && sp[-2] == 't'))) | |
8745 | { | |
8746 | sp -= 5; | |
8747 | do_it: | |
8748 | if (sp == str) | |
8749 | { | |
8750 | /* no expression means zero offset */ | |
8751 | if (c) | |
8752 | { | |
8753 | /* %xx(reg) is an error */ | |
8754 | ep->X_op = O_absent; | |
8755 | expr_end = str - 3; | |
8756 | } | |
8757 | else | |
8758 | { | |
8759 | ep->X_op = O_constant; | |
8760 | expr_end = sp; | |
8761 | } | |
8762 | ep->X_add_symbol = NULL; | |
8763 | ep->X_op_symbol = NULL; | |
8764 | ep->X_add_number = 0; | |
8765 | } | |
8766 | else | |
8767 | { | |
8768 | *sp = '\0'; | |
8769 | my_getExpression (ep, str); | |
8770 | *sp = LP; | |
8771 | } | |
8772 | return c; | |
8773 | } | |
8774 | } | |
8775 | } | |
8776 | my_getExpression (ep, str); | |
8777 | return c; /* => %hi or %lo encountered */ | |
8778 | } | |
8779 | ||
8780 | static void | |
8781 | my_getExpression (ep, str) | |
8782 | expressionS *ep; | |
8783 | char *str; | |
8784 | { | |
8785 | char *save_in; | |
98aa84af | 8786 | valueT val; |
252b5132 RH |
8787 | |
8788 | save_in = input_line_pointer; | |
8789 | input_line_pointer = str; | |
8790 | expression (ep); | |
8791 | expr_end = input_line_pointer; | |
8792 | input_line_pointer = save_in; | |
8793 | ||
8794 | /* If we are in mips16 mode, and this is an expression based on `.', | |
8795 | then we bump the value of the symbol by 1 since that is how other | |
8796 | text symbols are handled. We don't bother to handle complex | |
8797 | expressions, just `.' plus or minus a constant. */ | |
8798 | if (mips_opts.mips16 | |
8799 | && ep->X_op == O_symbol | |
8800 | && strcmp (S_GET_NAME (ep->X_add_symbol), FAKE_LABEL_NAME) == 0 | |
8801 | && S_GET_SEGMENT (ep->X_add_symbol) == now_seg | |
49309057 ILT |
8802 | && symbol_get_frag (ep->X_add_symbol) == frag_now |
8803 | && symbol_constant_p (ep->X_add_symbol) | |
98aa84af AM |
8804 | && (val = S_GET_VALUE (ep->X_add_symbol)) == frag_now_fix ()) |
8805 | S_SET_VALUE (ep->X_add_symbol, val + 1); | |
252b5132 RH |
8806 | } |
8807 | ||
8808 | /* Turn a string in input_line_pointer into a floating point constant | |
bc0d738a NC |
8809 | of type TYPE, and store the appropriate bytes in *LITP. The number |
8810 | of LITTLENUMS emitted is stored in *SIZEP. An error message is | |
252b5132 RH |
8811 | returned, or NULL on OK. */ |
8812 | ||
8813 | char * | |
8814 | md_atof (type, litP, sizeP) | |
8815 | int type; | |
8816 | char *litP; | |
8817 | int *sizeP; | |
8818 | { | |
8819 | int prec; | |
8820 | LITTLENUM_TYPE words[4]; | |
8821 | char *t; | |
8822 | int i; | |
8823 | ||
8824 | switch (type) | |
8825 | { | |
8826 | case 'f': | |
8827 | prec = 2; | |
8828 | break; | |
8829 | ||
8830 | case 'd': | |
8831 | prec = 4; | |
8832 | break; | |
8833 | ||
8834 | default: | |
8835 | *sizeP = 0; | |
8836 | return _("bad call to md_atof"); | |
8837 | } | |
8838 | ||
8839 | t = atof_ieee (input_line_pointer, type, words); | |
8840 | if (t) | |
8841 | input_line_pointer = t; | |
8842 | ||
8843 | *sizeP = prec * 2; | |
8844 | ||
8845 | if (! target_big_endian) | |
8846 | { | |
8847 | for (i = prec - 1; i >= 0; i--) | |
8848 | { | |
8849 | md_number_to_chars (litP, (valueT) words[i], 2); | |
8850 | litP += 2; | |
8851 | } | |
8852 | } | |
8853 | else | |
8854 | { | |
8855 | for (i = 0; i < prec; i++) | |
8856 | { | |
8857 | md_number_to_chars (litP, (valueT) words[i], 2); | |
8858 | litP += 2; | |
8859 | } | |
8860 | } | |
bdaaa2e1 | 8861 | |
252b5132 RH |
8862 | return NULL; |
8863 | } | |
8864 | ||
8865 | void | |
8866 | md_number_to_chars (buf, val, n) | |
8867 | char *buf; | |
8868 | valueT val; | |
8869 | int n; | |
8870 | { | |
8871 | if (target_big_endian) | |
8872 | number_to_chars_bigendian (buf, val, n); | |
8873 | else | |
8874 | number_to_chars_littleendian (buf, val, n); | |
8875 | } | |
8876 | \f | |
39c0a331 | 8877 | CONST char *md_shortopts = "nO::g::G:"; |
252b5132 | 8878 | |
e972090a NC |
8879 | struct option md_longopts[] = |
8880 | { | |
252b5132 RH |
8881 | #define OPTION_MIPS1 (OPTION_MD_BASE + 1) |
8882 | {"mips0", no_argument, NULL, OPTION_MIPS1}, | |
8883 | {"mips1", no_argument, NULL, OPTION_MIPS1}, | |
8884 | #define OPTION_MIPS2 (OPTION_MD_BASE + 2) | |
8885 | {"mips2", no_argument, NULL, OPTION_MIPS2}, | |
8886 | #define OPTION_MIPS3 (OPTION_MD_BASE + 3) | |
8887 | {"mips3", no_argument, NULL, OPTION_MIPS3}, | |
8888 | #define OPTION_MIPS4 (OPTION_MD_BASE + 4) | |
8889 | {"mips4", no_argument, NULL, OPTION_MIPS4}, | |
8890 | #define OPTION_MCPU (OPTION_MD_BASE + 5) | |
8891 | {"mcpu", required_argument, NULL, OPTION_MCPU}, | |
8892 | #define OPTION_MEMBEDDED_PIC (OPTION_MD_BASE + 6) | |
8893 | {"membedded-pic", no_argument, NULL, OPTION_MEMBEDDED_PIC}, | |
156c2f8b | 8894 | #define OPTION_TRAP (OPTION_MD_BASE + 7) |
252b5132 RH |
8895 | {"trap", no_argument, NULL, OPTION_TRAP}, |
8896 | {"no-break", no_argument, NULL, OPTION_TRAP}, | |
156c2f8b | 8897 | #define OPTION_BREAK (OPTION_MD_BASE + 8) |
252b5132 RH |
8898 | {"break", no_argument, NULL, OPTION_BREAK}, |
8899 | {"no-trap", no_argument, NULL, OPTION_BREAK}, | |
156c2f8b | 8900 | #define OPTION_EB (OPTION_MD_BASE + 9) |
252b5132 | 8901 | {"EB", no_argument, NULL, OPTION_EB}, |
156c2f8b | 8902 | #define OPTION_EL (OPTION_MD_BASE + 10) |
252b5132 | 8903 | {"EL", no_argument, NULL, OPTION_EL}, |
156c2f8b | 8904 | #define OPTION_M4650 (OPTION_MD_BASE + 11) |
252b5132 | 8905 | {"m4650", no_argument, NULL, OPTION_M4650}, |
156c2f8b | 8906 | #define OPTION_NO_M4650 (OPTION_MD_BASE + 12) |
252b5132 | 8907 | {"no-m4650", no_argument, NULL, OPTION_NO_M4650}, |
156c2f8b | 8908 | #define OPTION_M4010 (OPTION_MD_BASE + 13) |
252b5132 | 8909 | {"m4010", no_argument, NULL, OPTION_M4010}, |
156c2f8b | 8910 | #define OPTION_NO_M4010 (OPTION_MD_BASE + 14) |
252b5132 | 8911 | {"no-m4010", no_argument, NULL, OPTION_NO_M4010}, |
156c2f8b | 8912 | #define OPTION_M4100 (OPTION_MD_BASE + 15) |
252b5132 | 8913 | {"m4100", no_argument, NULL, OPTION_M4100}, |
156c2f8b | 8914 | #define OPTION_NO_M4100 (OPTION_MD_BASE + 16) |
252b5132 | 8915 | {"no-m4100", no_argument, NULL, OPTION_NO_M4100}, |
156c2f8b | 8916 | #define OPTION_MIPS16 (OPTION_MD_BASE + 17) |
252b5132 | 8917 | {"mips16", no_argument, NULL, OPTION_MIPS16}, |
156c2f8b | 8918 | #define OPTION_NO_MIPS16 (OPTION_MD_BASE + 18) |
252b5132 | 8919 | {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16}, |
156c2f8b | 8920 | #define OPTION_M3900 (OPTION_MD_BASE + 19) |
252b5132 | 8921 | {"m3900", no_argument, NULL, OPTION_M3900}, |
156c2f8b | 8922 | #define OPTION_NO_M3900 (OPTION_MD_BASE + 20) |
252b5132 | 8923 | {"no-m3900", no_argument, NULL, OPTION_NO_M3900}, |
156c2f8b | 8924 | #define OPTION_MABI (OPTION_MD_BASE + 21) |
252b5132 | 8925 | {"mabi", required_argument, NULL, OPTION_MABI}, |
156c2f8b | 8926 | #define OPTION_M7000_HILO_FIX (OPTION_MD_BASE + 22) |
6b76fefe | 8927 | {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX}, |
156c2f8b | 8928 | #define OPTION_NO_M7000_HILO_FIX (OPTION_MD_BASE + 23) |
6b76fefe | 8929 | {"no-fix-7000", no_argument, NULL, OPTION_NO_M7000_HILO_FIX}, |
156c2f8b | 8930 | #define OPTION_GP32 (OPTION_MD_BASE + 24) |
c97ef257 | 8931 | {"mgp32", no_argument, NULL, OPTION_GP32}, |
156c2f8b | 8932 | #define OPTION_GP64 (OPTION_MD_BASE + 25) |
c97ef257 | 8933 | {"mgp64", no_argument, NULL, OPTION_GP64}, |
156c2f8b | 8934 | #define OPTION_CONSTRUCT_FLOATS (OPTION_MD_BASE + 26) |
119d663a | 8935 | {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS}, |
156c2f8b | 8936 | #define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MD_BASE + 27) |
119d663a | 8937 | {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS}, |
156c2f8b NC |
8938 | #define OPTION_MIPS32 (OPTION_MD_BASE + 28) |
8939 | {"mips32", no_argument, NULL, OPTION_MIPS32}, | |
84ea6cf2 NC |
8940 | #define OPTION_MIPS5 (OPTION_MD_BASE + 29) |
8941 | {"mips5", no_argument, NULL, OPTION_MIPS5}, | |
8942 | #define OPTION_MIPS64 (OPTION_MD_BASE + 30) | |
8943 | {"mips64", no_argument, NULL, OPTION_MIPS64}, | |
ec68c924 EC |
8944 | #define OPTION_MARCH (OPTION_MD_BASE + 31) |
8945 | {"march", required_argument, NULL, OPTION_MARCH}, | |
8946 | #define OPTION_MTUNE (OPTION_MD_BASE + 32) | |
8947 | {"mtune", required_argument, NULL, OPTION_MTUNE}, | |
156c2f8b NC |
8948 | #ifdef OBJ_ELF |
8949 | #define OPTION_ELF_BASE (OPTION_MD_BASE + 35) | |
8950 | #define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0) | |
8951 | #define OPTION_NON_SHARED (OPTION_ELF_BASE + 1) | |
8952 | #define OPTION_XGOT (OPTION_ELF_BASE + 2) | |
8953 | #define OPTION_32 (OPTION_ELF_BASE + 3) | |
8954 | #define OPTION_64 (OPTION_ELF_BASE + 4) | |
8955 | {"KPIC", no_argument, NULL, OPTION_CALL_SHARED}, | |
8956 | {"call_shared", no_argument, NULL, OPTION_CALL_SHARED}, | |
8957 | {"non_shared", no_argument, NULL, OPTION_NON_SHARED}, | |
8958 | {"xgot", no_argument, NULL, OPTION_XGOT}, | |
8959 | {"32", no_argument, NULL, OPTION_32}, | |
8960 | {"64", no_argument, NULL, OPTION_64}, | |
8961 | #endif | |
119d663a | 8962 | |
252b5132 RH |
8963 | {NULL, no_argument, NULL, 0} |
8964 | }; | |
156c2f8b | 8965 | size_t md_longopts_size = sizeof (md_longopts); |
252b5132 RH |
8966 | |
8967 | int | |
8968 | md_parse_option (c, arg) | |
8969 | int c; | |
8970 | char *arg; | |
8971 | { | |
8972 | switch (c) | |
8973 | { | |
119d663a NC |
8974 | case OPTION_CONSTRUCT_FLOATS: |
8975 | mips_disable_float_construction = 0; | |
8976 | break; | |
bdaaa2e1 | 8977 | |
119d663a NC |
8978 | case OPTION_NO_CONSTRUCT_FLOATS: |
8979 | mips_disable_float_construction = 1; | |
8980 | break; | |
bdaaa2e1 | 8981 | |
252b5132 RH |
8982 | case OPTION_TRAP: |
8983 | mips_trap = 1; | |
8984 | break; | |
8985 | ||
8986 | case OPTION_BREAK: | |
8987 | mips_trap = 0; | |
8988 | break; | |
8989 | ||
8990 | case OPTION_EB: | |
8991 | target_big_endian = 1; | |
8992 | break; | |
8993 | ||
8994 | case OPTION_EL: | |
8995 | target_big_endian = 0; | |
8996 | break; | |
8997 | ||
39c0a331 L |
8998 | case 'n': |
8999 | warn_nops = 1; | |
9000 | break; | |
9001 | ||
252b5132 RH |
9002 | case 'O': |
9003 | if (arg && arg[1] == '0') | |
9004 | mips_optimize = 1; | |
9005 | else | |
9006 | mips_optimize = 2; | |
9007 | break; | |
9008 | ||
9009 | case 'g': | |
9010 | if (arg == NULL) | |
9011 | mips_debug = 2; | |
9012 | else | |
9013 | mips_debug = atoi (arg); | |
9014 | /* When the MIPS assembler sees -g or -g2, it does not do | |
9015 | optimizations which limit full symbolic debugging. We take | |
9016 | that to be equivalent to -O0. */ | |
9017 | if (mips_debug == 2) | |
9018 | mips_optimize = 1; | |
9019 | break; | |
9020 | ||
9021 | case OPTION_MIPS1: | |
e7af610e | 9022 | mips_opts.isa = ISA_MIPS1; |
252b5132 RH |
9023 | break; |
9024 | ||
9025 | case OPTION_MIPS2: | |
e7af610e | 9026 | mips_opts.isa = ISA_MIPS2; |
252b5132 RH |
9027 | break; |
9028 | ||
9029 | case OPTION_MIPS3: | |
e7af610e | 9030 | mips_opts.isa = ISA_MIPS3; |
252b5132 RH |
9031 | break; |
9032 | ||
9033 | case OPTION_MIPS4: | |
e7af610e NC |
9034 | mips_opts.isa = ISA_MIPS4; |
9035 | break; | |
9036 | ||
84ea6cf2 NC |
9037 | case OPTION_MIPS5: |
9038 | mips_opts.isa = ISA_MIPS5; | |
9039 | break; | |
9040 | ||
e7af610e NC |
9041 | case OPTION_MIPS32: |
9042 | mips_opts.isa = ISA_MIPS32; | |
252b5132 RH |
9043 | break; |
9044 | ||
84ea6cf2 NC |
9045 | case OPTION_MIPS64: |
9046 | mips_opts.isa = ISA_MIPS64; | |
9047 | break; | |
9048 | ||
ec68c924 EC |
9049 | case OPTION_MTUNE: |
9050 | case OPTION_MARCH: | |
252b5132 RH |
9051 | case OPTION_MCPU: |
9052 | { | |
ec68c924 EC |
9053 | int cpu = CPU_UNKNOWN; |
9054 | ||
e7af610e | 9055 | /* Identify the processor type. */ |
ec68c924 | 9056 | if (strcasecmp (arg, "default") != 0) |
252b5132 | 9057 | { |
e7af610e | 9058 | const struct mips_cpu_info *ci; |
252b5132 | 9059 | |
e7af610e NC |
9060 | ci = mips_cpu_info_from_name (arg); |
9061 | if (ci == NULL || ci->is_isa) | |
ec68c924 EC |
9062 | { |
9063 | switch (c) | |
9064 | { | |
9065 | case OPTION_MTUNE: | |
9066 | as_fatal (_("invalid architecture -mtune=%s"), arg); | |
9067 | break; | |
9068 | case OPTION_MARCH: | |
9069 | as_fatal (_("invalid architecture -march=%s"), arg); | |
9070 | break; | |
9071 | case OPTION_MCPU: | |
9072 | as_fatal (_("invalid architecture -mcpu=%s"), arg); | |
9073 | break; | |
9074 | } | |
9075 | } | |
e7af610e | 9076 | else |
ec68c924 EC |
9077 | cpu = ci->cpu; |
9078 | } | |
9079 | ||
9080 | switch (c) | |
9081 | { | |
9082 | case OPTION_MTUNE: | |
9083 | mips_tune = cpu; | |
9084 | break; | |
9085 | case OPTION_MARCH: | |
9086 | mips_arch = cpu; | |
9087 | break; | |
9088 | case OPTION_MCPU: | |
9089 | mips_cpu = cpu; | |
252b5132 RH |
9090 | } |
9091 | } | |
9092 | break; | |
9093 | ||
9094 | case OPTION_M4650: | |
ec68c924 EC |
9095 | mips_arch = CPU_R4650; |
9096 | mips_tune = CPU_R4650; | |
252b5132 RH |
9097 | break; |
9098 | ||
9099 | case OPTION_NO_M4650: | |
9100 | break; | |
9101 | ||
9102 | case OPTION_M4010: | |
ec68c924 EC |
9103 | mips_arch = CPU_R4010; |
9104 | mips_tune = CPU_R4010; | |
252b5132 RH |
9105 | break; |
9106 | ||
9107 | case OPTION_NO_M4010: | |
9108 | break; | |
9109 | ||
9110 | case OPTION_M4100: | |
ec68c924 EC |
9111 | mips_arch = CPU_VR4100; |
9112 | mips_tune = CPU_VR4100; | |
252b5132 RH |
9113 | break; |
9114 | ||
9115 | case OPTION_NO_M4100: | |
9116 | break; | |
9117 | ||
252b5132 | 9118 | case OPTION_M3900: |
ec68c924 EC |
9119 | mips_arch = CPU_R3900; |
9120 | mips_tune = CPU_R3900; | |
252b5132 | 9121 | break; |
bdaaa2e1 | 9122 | |
252b5132 RH |
9123 | case OPTION_NO_M3900: |
9124 | break; | |
9125 | ||
9126 | case OPTION_MIPS16: | |
9127 | mips_opts.mips16 = 1; | |
9128 | mips_no_prev_insn (false); | |
9129 | break; | |
9130 | ||
9131 | case OPTION_NO_MIPS16: | |
9132 | mips_opts.mips16 = 0; | |
9133 | mips_no_prev_insn (false); | |
9134 | break; | |
9135 | ||
9136 | case OPTION_MEMBEDDED_PIC: | |
9137 | mips_pic = EMBEDDED_PIC; | |
9138 | if (USE_GLOBAL_POINTER_OPT && g_switch_seen) | |
9139 | { | |
9140 | as_bad (_("-G may not be used with embedded PIC code")); | |
9141 | return 0; | |
9142 | } | |
9143 | g_switch_value = 0x7fffffff; | |
9144 | break; | |
9145 | ||
0f074f60 | 9146 | #ifdef OBJ_ELF |
252b5132 RH |
9147 | /* When generating ELF code, we permit -KPIC and -call_shared to |
9148 | select SVR4_PIC, and -non_shared to select no PIC. This is | |
9149 | intended to be compatible with Irix 5. */ | |
9150 | case OPTION_CALL_SHARED: | |
9151 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
9152 | { | |
9153 | as_bad (_("-call_shared is supported only for ELF format")); | |
9154 | return 0; | |
9155 | } | |
9156 | mips_pic = SVR4_PIC; | |
9157 | if (g_switch_seen && g_switch_value != 0) | |
9158 | { | |
9159 | as_bad (_("-G may not be used with SVR4 PIC code")); | |
9160 | return 0; | |
9161 | } | |
9162 | g_switch_value = 0; | |
9163 | break; | |
9164 | ||
9165 | case OPTION_NON_SHARED: | |
9166 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
9167 | { | |
9168 | as_bad (_("-non_shared is supported only for ELF format")); | |
9169 | return 0; | |
9170 | } | |
9171 | mips_pic = NO_PIC; | |
9172 | break; | |
9173 | ||
9174 | /* The -xgot option tells the assembler to use 32 offsets when | |
9175 | accessing the got in SVR4_PIC mode. It is for Irix | |
9176 | compatibility. */ | |
9177 | case OPTION_XGOT: | |
9178 | mips_big_got = 1; | |
9179 | break; | |
0f074f60 | 9180 | #endif /* OBJ_ELF */ |
252b5132 RH |
9181 | |
9182 | case 'G': | |
9183 | if (! USE_GLOBAL_POINTER_OPT) | |
9184 | { | |
9185 | as_bad (_("-G is not supported for this configuration")); | |
9186 | return 0; | |
9187 | } | |
9188 | else if (mips_pic == SVR4_PIC || mips_pic == EMBEDDED_PIC) | |
9189 | { | |
9190 | as_bad (_("-G may not be used with SVR4 or embedded PIC code")); | |
9191 | return 0; | |
9192 | } | |
9193 | else | |
9194 | g_switch_value = atoi (arg); | |
9195 | g_switch_seen = 1; | |
9196 | break; | |
9197 | ||
0f074f60 | 9198 | #ifdef OBJ_ELF |
252b5132 RH |
9199 | /* The -32 and -64 options tell the assembler to output the 32 |
9200 | bit or the 64 bit MIPS ELF format. */ | |
9201 | case OPTION_32: | |
9202 | mips_64 = 0; | |
9203 | break; | |
9204 | ||
9205 | case OPTION_64: | |
9206 | { | |
9207 | const char **list, **l; | |
9208 | ||
9209 | list = bfd_target_list (); | |
9210 | for (l = list; *l != NULL; l++) | |
9211 | if (strcmp (*l, "elf64-bigmips") == 0 | |
f4ddc5e6 L |
9212 | || strcmp (*l, "elf64-littlemips") == 0 |
9213 | || strcmp (*l, "elf64-tradbigmips") == 0 | |
9214 | || strcmp (*l, "elf64-tradlittlemips") == 0) | |
252b5132 RH |
9215 | break; |
9216 | if (*l == NULL) | |
9217 | as_fatal (_("No compiled in support for 64 bit object file format")); | |
9218 | free (list); | |
9219 | mips_64 = 1; | |
9220 | } | |
9221 | break; | |
0f074f60 | 9222 | #endif /* OBJ_ELF */ |
252b5132 | 9223 | |
c97ef257 AH |
9224 | case OPTION_GP32: |
9225 | mips_gp32 = 1; | |
9226 | mips_64 = 0; | |
9227 | ||
9228 | /* We deliberately don't allow "-gp32" to set the MIPS_32BITMODE | |
9229 | flag in object files because to do so would make it | |
9230 | impossible to link with libraries compiled without "-gp32". | |
bdaaa2e1 | 9231 | This is unnecessarily restrictive. |
c97ef257 AH |
9232 | |
9233 | We could solve this problem by adding "-gp32" multilibs to | |
9234 | gcc, but to set this flag before gcc is built with such | |
bdaaa2e1 | 9235 | multilibs will break too many systems. */ |
c97ef257 | 9236 | |
beae10d5 KH |
9237 | #if 0 |
9238 | mips_32bitmode = 1; | |
9239 | #endif | |
c97ef257 AH |
9240 | break; |
9241 | ||
9242 | case OPTION_GP64: | |
9243 | mips_gp32 = 0; | |
9244 | mips_64 = 1; | |
beae10d5 KH |
9245 | #if 0 |
9246 | mips_32bitmode = 0; | |
9247 | #endif | |
c97ef257 | 9248 | break; |
252b5132 RH |
9249 | |
9250 | case OPTION_MABI: | |
beae10d5 KH |
9251 | if (strcmp (arg, "32") == 0 |
9252 | || strcmp (arg, "n32") == 0 | |
9253 | || strcmp (arg, "64") == 0 | |
9254 | || strcmp (arg, "o64") == 0 | |
9255 | || strcmp (arg, "eabi") == 0) | |
252b5132 RH |
9256 | mips_abi_string = arg; |
9257 | break; | |
9258 | ||
6b76fefe CM |
9259 | case OPTION_M7000_HILO_FIX: |
9260 | mips_7000_hilo_fix = true; | |
9261 | break; | |
9262 | ||
9263 | case OPTION_NO_M7000_HILO_FIX: | |
9264 | mips_7000_hilo_fix = false; | |
9265 | break; | |
9266 | ||
252b5132 RH |
9267 | default: |
9268 | return 0; | |
9269 | } | |
9270 | ||
9271 | return 1; | |
9272 | } | |
9273 | ||
252b5132 RH |
9274 | static void |
9275 | show (stream, string, col_p, first_p) | |
9276 | FILE *stream; | |
9277 | char *string; | |
9278 | int *col_p; | |
9279 | int *first_p; | |
9280 | { | |
9281 | if (*first_p) | |
9282 | { | |
9283 | fprintf (stream, "%24s", ""); | |
9284 | *col_p = 24; | |
9285 | } | |
9286 | else | |
9287 | { | |
9288 | fprintf (stream, ", "); | |
9289 | *col_p += 2; | |
9290 | } | |
9291 | ||
9292 | if (*col_p + strlen (string) > 72) | |
9293 | { | |
9294 | fprintf (stream, "\n%24s", ""); | |
9295 | *col_p = 24; | |
9296 | } | |
9297 | ||
9298 | fprintf (stream, "%s", string); | |
9299 | *col_p += strlen (string); | |
9300 | ||
9301 | *first_p = 0; | |
9302 | } | |
9303 | ||
252b5132 RH |
9304 | void |
9305 | md_show_usage (stream) | |
9306 | FILE *stream; | |
9307 | { | |
9308 | int column, first; | |
9309 | ||
beae10d5 | 9310 | fprintf (stream, _("\ |
252b5132 RH |
9311 | MIPS options:\n\ |
9312 | -membedded-pic generate embedded position independent code\n\ | |
9313 | -EB generate big endian output\n\ | |
9314 | -EL generate little endian output\n\ | |
9315 | -g, -g2 do not remove uneeded NOPs or swap branches\n\ | |
9316 | -G NUM allow referencing objects up to NUM bytes\n\ | |
9317 | implicitly with the gp register [default 8]\n")); | |
beae10d5 | 9318 | fprintf (stream, _("\ |
252b5132 RH |
9319 | -mips1 generate MIPS ISA I instructions\n\ |
9320 | -mips2 generate MIPS ISA II instructions\n\ | |
9321 | -mips3 generate MIPS ISA III instructions\n\ | |
9322 | -mips4 generate MIPS ISA IV instructions\n\ | |
84ea6cf2 | 9323 | -mips5 generate MIPS ISA V instructions\n\ |
e7af610e | 9324 | -mips32 generate MIPS32 ISA instructions\n\ |
84ea6cf2 | 9325 | -mips64 generate MIPS64 ISA instructions\n\ |
ec68c924 | 9326 | -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n")); |
252b5132 RH |
9327 | |
9328 | first = 1; | |
9329 | ||
9330 | show (stream, "2000", &column, &first); | |
9331 | show (stream, "3000", &column, &first); | |
9332 | show (stream, "3900", &column, &first); | |
9333 | show (stream, "4000", &column, &first); | |
9334 | show (stream, "4010", &column, &first); | |
9335 | show (stream, "4100", &column, &first); | |
9336 | show (stream, "4111", &column, &first); | |
9337 | show (stream, "4300", &column, &first); | |
9338 | show (stream, "4400", &column, &first); | |
9339 | show (stream, "4600", &column, &first); | |
9340 | show (stream, "4650", &column, &first); | |
9341 | show (stream, "5000", &column, &first); | |
18ae5d72 EC |
9342 | show (stream, "5200", &column, &first); |
9343 | show (stream, "5230", &column, &first); | |
9344 | show (stream, "5231", &column, &first); | |
9345 | show (stream, "5261", &column, &first); | |
9346 | show (stream, "5721", &column, &first); | |
252b5132 RH |
9347 | show (stream, "6000", &column, &first); |
9348 | show (stream, "8000", &column, &first); | |
9349 | show (stream, "10000", &column, &first); | |
d1cf510e | 9350 | show (stream, "12000", &column, &first); |
e7af610e | 9351 | show (stream, "mips32-4k", &column, &first); |
c6c98b38 | 9352 | show (stream, "sb-1", &column, &first); |
252b5132 RH |
9353 | fputc ('\n', stream); |
9354 | ||
9355 | fprintf (stream, _("\ | |
ec68c924 | 9356 | -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\ |
252b5132 RH |
9357 | -no-mCPU don't generate code specific to CPU.\n\ |
9358 | For -mCPU and -no-mCPU, CPU must be one of:\n")); | |
9359 | ||
9360 | first = 1; | |
9361 | ||
9362 | show (stream, "3900", &column, &first); | |
9363 | show (stream, "4010", &column, &first); | |
9364 | show (stream, "4100", &column, &first); | |
9365 | show (stream, "4650", &column, &first); | |
9366 | fputc ('\n', stream); | |
9367 | ||
beae10d5 | 9368 | fprintf (stream, _("\ |
252b5132 RH |
9369 | -mips16 generate mips16 instructions\n\ |
9370 | -no-mips16 do not generate mips16 instructions\n")); | |
beae10d5 | 9371 | fprintf (stream, _("\ |
252b5132 RH |
9372 | -O0 remove unneeded NOPs, do not swap branches\n\ |
9373 | -O remove unneeded NOPs and swap branches\n\ | |
63486801 | 9374 | -n warn about NOPs generated from macros\n\ |
119d663a | 9375 | --[no-]construct-floats [dis]allow floating point values to be constructed\n\ |
252b5132 RH |
9376 | --trap, --no-break trap exception on div by 0 and mult overflow\n\ |
9377 | --break, --no-trap break exception on div by 0 and mult overflow\n")); | |
9378 | #ifdef OBJ_ELF | |
beae10d5 | 9379 | fprintf (stream, _("\ |
252b5132 RH |
9380 | -KPIC, -call_shared generate SVR4 position independent code\n\ |
9381 | -non_shared do not generate position independent code\n\ | |
9382 | -xgot assume a 32 bit GOT\n\ | |
9383 | -32 create 32 bit object file (default)\n\ | |
9384 | -64 create 64 bit object file\n")); | |
9385 | #endif | |
9386 | } | |
9387 | \f | |
9388 | void | |
9389 | mips_init_after_args () | |
9390 | { | |
9391 | /* initialize opcodes */ | |
9392 | bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes; | |
beae10d5 | 9393 | mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes; |
252b5132 RH |
9394 | } |
9395 | ||
9396 | long | |
9397 | md_pcrel_from (fixP) | |
9398 | fixS *fixP; | |
9399 | { | |
9400 | if (OUTPUT_FLAVOR != bfd_target_aout_flavour | |
9401 | && fixP->fx_addsy != (symbolS *) NULL | |
9402 | && ! S_IS_DEFINED (fixP->fx_addsy)) | |
9403 | { | |
9404 | /* This makes a branch to an undefined symbol be a branch to the | |
9405 | current location. */ | |
9406 | return 4; | |
9407 | } | |
9408 | ||
9409 | /* return the address of the delay slot */ | |
9410 | return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address; | |
9411 | } | |
9412 | ||
9413 | /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a | |
9414 | reloc for a cons. We could use the definition there, except that | |
9415 | we want to handle 64 bit relocs specially. */ | |
9416 | ||
9417 | void | |
9418 | cons_fix_new_mips (frag, where, nbytes, exp) | |
43841e91 | 9419 | fragS *frag ATTRIBUTE_UNUSED; |
252b5132 RH |
9420 | int where; |
9421 | unsigned int nbytes; | |
9422 | expressionS *exp; | |
9423 | { | |
9424 | #ifndef OBJ_ELF | |
9425 | /* If we are assembling in 32 bit mode, turn an 8 byte reloc into a | |
9426 | 4 byte reloc. */ | |
9427 | if (nbytes == 8 && ! mips_64) | |
9428 | { | |
9429 | if (target_big_endian) | |
9430 | where += 4; | |
9431 | nbytes = 4; | |
9432 | } | |
9433 | #endif | |
9434 | ||
9435 | if (nbytes != 2 && nbytes != 4 && nbytes != 8) | |
9436 | as_bad (_("Unsupported reloc size %d"), nbytes); | |
9437 | ||
9438 | fix_new_exp (frag_now, where, (int) nbytes, exp, 0, | |
9439 | (nbytes == 2 | |
9440 | ? BFD_RELOC_16 | |
9441 | : (nbytes == 4 ? BFD_RELOC_32 : BFD_RELOC_64))); | |
9442 | } | |
9443 | ||
9444 | /* This is called before the symbol table is processed. In order to | |
9445 | work with gcc when using mips-tfile, we must keep all local labels. | |
9446 | However, in other cases, we want to discard them. If we were | |
9447 | called with -g, but we didn't see any debugging information, it may | |
9448 | mean that gcc is smuggling debugging information through to | |
9449 | mips-tfile, in which case we must generate all local labels. */ | |
9450 | ||
9451 | void | |
9452 | mips_frob_file_before_adjust () | |
9453 | { | |
9454 | #ifndef NO_ECOFF_DEBUGGING | |
9455 | if (ECOFF_DEBUGGING | |
9456 | && mips_debug != 0 | |
9457 | && ! ecoff_debugging_seen) | |
9458 | flag_keep_locals = 1; | |
9459 | #endif | |
9460 | } | |
9461 | ||
9462 | /* Sort any unmatched HI16_S relocs so that they immediately precede | |
9463 | the corresponding LO reloc. This is called before md_apply_fix and | |
9464 | tc_gen_reloc. Unmatched HI16_S relocs can only be generated by | |
9465 | explicit use of the %hi modifier. */ | |
9466 | ||
9467 | void | |
9468 | mips_frob_file () | |
9469 | { | |
9470 | struct mips_hi_fixup *l; | |
9471 | ||
9472 | for (l = mips_hi_fixup_list; l != NULL; l = l->next) | |
9473 | { | |
9474 | segment_info_type *seginfo; | |
9475 | int pass; | |
9476 | ||
9477 | assert (l->fixp->fx_r_type == BFD_RELOC_HI16_S); | |
9478 | ||
9479 | /* Check quickly whether the next fixup happens to be a matching | |
9480 | %lo. */ | |
9481 | if (l->fixp->fx_next != NULL | |
9482 | && l->fixp->fx_next->fx_r_type == BFD_RELOC_LO16 | |
9483 | && l->fixp->fx_addsy == l->fixp->fx_next->fx_addsy | |
9484 | && l->fixp->fx_offset == l->fixp->fx_next->fx_offset) | |
9485 | continue; | |
9486 | ||
9487 | /* Look through the fixups for this segment for a matching %lo. | |
9488 | When we find one, move the %hi just in front of it. We do | |
9489 | this in two passes. In the first pass, we try to find a | |
9490 | unique %lo. In the second pass, we permit multiple %hi | |
9491 | relocs for a single %lo (this is a GNU extension). */ | |
9492 | seginfo = seg_info (l->seg); | |
9493 | for (pass = 0; pass < 2; pass++) | |
9494 | { | |
9495 | fixS *f, *prev; | |
9496 | ||
9497 | prev = NULL; | |
9498 | for (f = seginfo->fix_root; f != NULL; f = f->fx_next) | |
9499 | { | |
9500 | /* Check whether this is a %lo fixup which matches l->fixp. */ | |
9501 | if (f->fx_r_type == BFD_RELOC_LO16 | |
9502 | && f->fx_addsy == l->fixp->fx_addsy | |
9503 | && f->fx_offset == l->fixp->fx_offset | |
9504 | && (pass == 1 | |
9505 | || prev == NULL | |
9506 | || prev->fx_r_type != BFD_RELOC_HI16_S | |
9507 | || prev->fx_addsy != f->fx_addsy | |
9508 | || prev->fx_offset != f->fx_offset)) | |
9509 | { | |
9510 | fixS **pf; | |
9511 | ||
9512 | /* Move l->fixp before f. */ | |
9513 | for (pf = &seginfo->fix_root; | |
9514 | *pf != l->fixp; | |
9515 | pf = &(*pf)->fx_next) | |
9516 | assert (*pf != NULL); | |
9517 | ||
9518 | *pf = l->fixp->fx_next; | |
9519 | ||
9520 | l->fixp->fx_next = f; | |
9521 | if (prev == NULL) | |
9522 | seginfo->fix_root = l->fixp; | |
9523 | else | |
9524 | prev->fx_next = l->fixp; | |
9525 | ||
9526 | break; | |
9527 | } | |
9528 | ||
9529 | prev = f; | |
9530 | } | |
9531 | ||
9532 | if (f != NULL) | |
9533 | break; | |
9534 | ||
9535 | #if 0 /* GCC code motion plus incomplete dead code elimination | |
9536 | can leave a %hi without a %lo. */ | |
9537 | if (pass == 1) | |
9538 | as_warn_where (l->fixp->fx_file, l->fixp->fx_line, | |
9539 | _("Unmatched %%hi reloc")); | |
9540 | #endif | |
9541 | } | |
9542 | } | |
9543 | } | |
9544 | ||
9545 | /* When generating embedded PIC code we need to use a special | |
9546 | relocation to represent the difference of two symbols in the .text | |
9547 | section (switch tables use a difference of this sort). See | |
9548 | include/coff/mips.h for details. This macro checks whether this | |
9549 | fixup requires the special reloc. */ | |
9550 | #define SWITCH_TABLE(fixp) \ | |
9551 | ((fixp)->fx_r_type == BFD_RELOC_32 \ | |
bb2d6cd7 | 9552 | && OUTPUT_FLAVOR != bfd_target_elf_flavour \ |
252b5132 RH |
9553 | && (fixp)->fx_addsy != NULL \ |
9554 | && (fixp)->fx_subsy != NULL \ | |
9555 | && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \ | |
9556 | && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section) | |
9557 | ||
9558 | /* When generating embedded PIC code we must keep all PC relative | |
9559 | relocations, in case the linker has to relax a call. We also need | |
9560 | to keep relocations for switch table entries. */ | |
9561 | ||
252b5132 RH |
9562 | int |
9563 | mips_force_relocation (fixp) | |
9564 | fixS *fixp; | |
9565 | { | |
9566 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT | |
9567 | || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
9568 | return 1; | |
9569 | ||
9570 | return (mips_pic == EMBEDDED_PIC | |
9571 | && (fixp->fx_pcrel | |
9572 | || SWITCH_TABLE (fixp) | |
9573 | || fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S | |
9574 | || fixp->fx_r_type == BFD_RELOC_PCREL_LO16)); | |
9575 | } | |
9576 | ||
9577 | /* Apply a fixup to the object file. */ | |
9578 | ||
9579 | int | |
9580 | md_apply_fix (fixP, valueP) | |
9581 | fixS *fixP; | |
9582 | valueT *valueP; | |
9583 | { | |
9584 | unsigned char *buf; | |
98aa84af AM |
9585 | long insn; |
9586 | valueT value; | |
252b5132 RH |
9587 | |
9588 | assert (fixP->fx_size == 4 | |
9589 | || fixP->fx_r_type == BFD_RELOC_16 | |
9590 | || fixP->fx_r_type == BFD_RELOC_64 | |
9591 | || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT | |
9592 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY); | |
9593 | ||
9594 | value = *valueP; | |
9595 | ||
9596 | /* If we aren't adjusting this fixup to be against the section | |
9597 | symbol, we need to adjust the value. */ | |
9598 | #ifdef OBJ_ELF | |
9599 | if (fixP->fx_addsy != NULL && OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
bb2d6cd7 | 9600 | { |
98aa84af | 9601 | if (S_GET_OTHER (fixP->fx_addsy) == STO_MIPS16 |
ea4ff978 L |
9602 | || ((S_IS_WEAK (fixP->fx_addsy) |
9603 | || S_IS_EXTERN (fixP->fx_addsy)) | |
9604 | && !S_IS_COMMON (fixP->fx_addsy)) | |
98aa84af AM |
9605 | || (symbol_used_in_reloc_p (fixP->fx_addsy) |
9606 | && (((bfd_get_section_flags (stdoutput, | |
9607 | S_GET_SEGMENT (fixP->fx_addsy)) | |
9608 | & SEC_LINK_ONCE) != 0) | |
9609 | || !strncmp (segment_name (S_GET_SEGMENT (fixP->fx_addsy)), | |
9610 | ".gnu.linkonce", | |
9611 | sizeof (".gnu.linkonce") - 1)))) | |
252b5132 | 9612 | |
98aa84af AM |
9613 | { |
9614 | valueT symval = S_GET_VALUE (fixP->fx_addsy); | |
9615 | value -= symval; | |
9616 | if (value != 0 && ! fixP->fx_pcrel) | |
9617 | { | |
9618 | /* In this case, the bfd_install_relocation routine will | |
9619 | incorrectly add the symbol value back in. We just want | |
7461da6e | 9620 | the addend to appear in the object file. */ |
98aa84af | 9621 | value -= symval; |
7461da6e RS |
9622 | |
9623 | /* Make sure the addend is still non-zero. If it became zero | |
9624 | after the last operation, set it to a spurious value and | |
9625 | subtract the same value from the object file's contents. */ | |
9626 | if (value == 0) | |
9627 | { | |
9628 | value = 8; | |
9629 | ||
9630 | /* The in-place addends for LO16 relocations are signed; | |
9631 | leave the matching HI16 in-place addends as zero. */ | |
9632 | if (fixP->fx_r_type != BFD_RELOC_HI16_S) | |
9633 | { | |
9634 | reloc_howto_type *howto; | |
9635 | bfd_vma contents, mask, field; | |
9636 | ||
9637 | howto = bfd_reloc_type_lookup (stdoutput, | |
9638 | fixP->fx_r_type); | |
9639 | ||
9640 | contents = bfd_get_bits (fixP->fx_frag->fr_literal | |
9641 | + fixP->fx_where, | |
9642 | fixP->fx_size * 8, | |
9643 | target_big_endian); | |
9644 | ||
9645 | /* MASK has bits set where the relocation should go. | |
9646 | FIELD is -value, shifted into the appropriate place | |
9647 | for this relocation. */ | |
9648 | mask = 1 << (howto->bitsize - 1); | |
9649 | mask = (((mask - 1) << 1) | 1) << howto->bitpos; | |
9650 | field = (-value >> howto->rightshift) << howto->bitpos; | |
9651 | ||
9652 | bfd_put_bits ((field & mask) | (contents & ~mask), | |
9653 | fixP->fx_frag->fr_literal + fixP->fx_where, | |
9654 | fixP->fx_size * 8, | |
9655 | target_big_endian); | |
9656 | } | |
9657 | } | |
98aa84af AM |
9658 | } |
9659 | } | |
252b5132 | 9660 | |
bb2d6cd7 GK |
9661 | /* This code was generated using trial and error and so is |
9662 | fragile and not trustworthy. If you change it, you should | |
9663 | rerun the elf-rel, elf-rel2, and empic testcases and ensure | |
9664 | they still pass. */ | |
9665 | if (fixP->fx_pcrel || fixP->fx_subsy != NULL) | |
9666 | { | |
9667 | value += fixP->fx_frag->fr_address + fixP->fx_where; | |
9668 | ||
9669 | /* BFD's REL handling, for MIPS, is _very_ weird. | |
9670 | This gives the right results, but it can't possibly | |
9671 | be the way things are supposed to work. */ | |
9672 | if (fixP->fx_r_type != BFD_RELOC_16_PCREL_S2 | |
9673 | || S_GET_SEGMENT (fixP->fx_addsy) != undefined_section) | |
9674 | value += fixP->fx_frag->fr_address + fixP->fx_where; | |
9675 | } | |
9676 | } | |
9677 | #endif | |
252b5132 RH |
9678 | |
9679 | fixP->fx_addnumber = value; /* Remember value for tc_gen_reloc */ | |
9680 | ||
9681 | if (fixP->fx_addsy == NULL && ! fixP->fx_pcrel) | |
9682 | fixP->fx_done = 1; | |
9683 | ||
9684 | switch (fixP->fx_r_type) | |
9685 | { | |
9686 | case BFD_RELOC_MIPS_JMP: | |
9687 | case BFD_RELOC_HI16: | |
9688 | case BFD_RELOC_HI16_S: | |
9689 | case BFD_RELOC_MIPS_GPREL: | |
9690 | case BFD_RELOC_MIPS_LITERAL: | |
9691 | case BFD_RELOC_MIPS_CALL16: | |
9692 | case BFD_RELOC_MIPS_GOT16: | |
9693 | case BFD_RELOC_MIPS_GPREL32: | |
9694 | case BFD_RELOC_MIPS_GOT_HI16: | |
9695 | case BFD_RELOC_MIPS_GOT_LO16: | |
9696 | case BFD_RELOC_MIPS_CALL_HI16: | |
9697 | case BFD_RELOC_MIPS_CALL_LO16: | |
9698 | case BFD_RELOC_MIPS16_GPREL: | |
9699 | if (fixP->fx_pcrel) | |
9700 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
9701 | _("Invalid PC relative reloc")); | |
9702 | /* Nothing needed to do. The value comes from the reloc entry */ | |
9703 | break; | |
9704 | ||
9705 | case BFD_RELOC_MIPS16_JMP: | |
9706 | /* We currently always generate a reloc against a symbol, which | |
9707 | means that we don't want an addend even if the symbol is | |
9708 | defined. */ | |
9709 | fixP->fx_addnumber = 0; | |
9710 | break; | |
9711 | ||
9712 | case BFD_RELOC_PCREL_HI16_S: | |
9713 | /* The addend for this is tricky if it is internal, so we just | |
9714 | do everything here rather than in bfd_install_relocation. */ | |
bdaaa2e1 | 9715 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour |
bb2d6cd7 GK |
9716 | && !fixP->fx_done |
9717 | && value != 0) | |
9718 | break; | |
9719 | if (fixP->fx_addsy | |
9720 | && (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_SECTION_SYM) == 0) | |
252b5132 RH |
9721 | { |
9722 | /* For an external symbol adjust by the address to make it | |
9723 | pcrel_offset. We use the address of the RELLO reloc | |
9724 | which follows this one. */ | |
9725 | value += (fixP->fx_next->fx_frag->fr_address | |
9726 | + fixP->fx_next->fx_where); | |
9727 | } | |
9728 | if (value & 0x8000) | |
9729 | value += 0x10000; | |
9730 | value >>= 16; | |
9731 | buf = (unsigned char *) fixP->fx_frag->fr_literal + fixP->fx_where; | |
9732 | if (target_big_endian) | |
9733 | buf += 2; | |
9734 | md_number_to_chars (buf, value, 2); | |
9735 | break; | |
9736 | ||
9737 | case BFD_RELOC_PCREL_LO16: | |
9738 | /* The addend for this is tricky if it is internal, so we just | |
9739 | do everything here rather than in bfd_install_relocation. */ | |
bdaaa2e1 | 9740 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour |
bb2d6cd7 GK |
9741 | && !fixP->fx_done |
9742 | && value != 0) | |
9743 | break; | |
9744 | if (fixP->fx_addsy | |
9745 | && (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_SECTION_SYM) == 0) | |
252b5132 RH |
9746 | value += fixP->fx_frag->fr_address + fixP->fx_where; |
9747 | buf = (unsigned char *) fixP->fx_frag->fr_literal + fixP->fx_where; | |
9748 | if (target_big_endian) | |
9749 | buf += 2; | |
9750 | md_number_to_chars (buf, value, 2); | |
9751 | break; | |
9752 | ||
9753 | case BFD_RELOC_64: | |
9754 | /* This is handled like BFD_RELOC_32, but we output a sign | |
9755 | extended value if we are only 32 bits. */ | |
9756 | if (fixP->fx_done | |
9757 | || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP))) | |
9758 | { | |
9759 | if (8 <= sizeof (valueT)) | |
9760 | md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where, | |
9761 | value, 8); | |
9762 | else | |
9763 | { | |
9764 | long w1, w2; | |
9765 | long hiv; | |
9766 | ||
9767 | w1 = w2 = fixP->fx_where; | |
9768 | if (target_big_endian) | |
9769 | w1 += 4; | |
9770 | else | |
9771 | w2 += 4; | |
9772 | md_number_to_chars (fixP->fx_frag->fr_literal + w1, value, 4); | |
9773 | if ((value & 0x80000000) != 0) | |
9774 | hiv = 0xffffffff; | |
9775 | else | |
9776 | hiv = 0; | |
9777 | md_number_to_chars (fixP->fx_frag->fr_literal + w2, hiv, 4); | |
9778 | } | |
9779 | } | |
9780 | break; | |
9781 | ||
056350c6 | 9782 | case BFD_RELOC_RVA: |
252b5132 RH |
9783 | case BFD_RELOC_32: |
9784 | /* If we are deleting this reloc entry, we must fill in the | |
9785 | value now. This can happen if we have a .word which is not | |
9786 | resolved when it appears but is later defined. We also need | |
9787 | to fill in the value if this is an embedded PIC switch table | |
9788 | entry. */ | |
9789 | if (fixP->fx_done | |
9790 | || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP))) | |
9791 | md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where, | |
9792 | value, 4); | |
9793 | break; | |
9794 | ||
9795 | case BFD_RELOC_16: | |
9796 | /* If we are deleting this reloc entry, we must fill in the | |
9797 | value now. */ | |
9798 | assert (fixP->fx_size == 2); | |
9799 | if (fixP->fx_done) | |
9800 | md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where, | |
9801 | value, 2); | |
9802 | break; | |
9803 | ||
9804 | case BFD_RELOC_LO16: | |
9805 | /* When handling an embedded PIC switch statement, we can wind | |
9806 | up deleting a LO16 reloc. See the 'o' case in mips_ip. */ | |
9807 | if (fixP->fx_done) | |
9808 | { | |
98aa84af | 9809 | if (value + 0x8000 > 0xffff) |
252b5132 RH |
9810 | as_bad_where (fixP->fx_file, fixP->fx_line, |
9811 | _("relocation overflow")); | |
9812 | buf = (unsigned char *) fixP->fx_frag->fr_literal + fixP->fx_where; | |
9813 | if (target_big_endian) | |
9814 | buf += 2; | |
9815 | md_number_to_chars (buf, value, 2); | |
9816 | } | |
9817 | break; | |
9818 | ||
9819 | case BFD_RELOC_16_PCREL_S2: | |
9820 | /* | |
9821 | * We need to save the bits in the instruction since fixup_segment() | |
9822 | * might be deleting the relocation entry (i.e., a branch within | |
9823 | * the current segment). | |
9824 | */ | |
9825 | if ((value & 0x3) != 0) | |
9826 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
98aa84af | 9827 | _("Branch to odd address (%lx)"), (long) value); |
bb2d6cd7 GK |
9828 | |
9829 | if (!fixP->fx_done && value != 0) | |
9830 | break; | |
9831 | /* If 'value' is zero, the remaining reloc code won't actually | |
9832 | do the store, so it must be done here. This is probably | |
9833 | a bug somewhere. */ | |
9834 | if (!fixP->fx_done) | |
9835 | value -= fixP->fx_frag->fr_address + fixP->fx_where; | |
bdaaa2e1 | 9836 | |
98aa84af | 9837 | value = (offsetT) value >> 2; |
252b5132 RH |
9838 | |
9839 | /* update old instruction data */ | |
9840 | buf = (unsigned char *) (fixP->fx_where + fixP->fx_frag->fr_literal); | |
9841 | if (target_big_endian) | |
9842 | insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3]; | |
9843 | else | |
9844 | insn = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0]; | |
9845 | ||
98aa84af | 9846 | if (value + 0x8000 <= 0xffff) |
252b5132 RH |
9847 | insn |= value & 0xffff; |
9848 | else | |
9849 | { | |
9850 | /* The branch offset is too large. If this is an | |
9851 | unconditional branch, and we are not generating PIC code, | |
9852 | we can convert it to an absolute jump instruction. */ | |
9853 | if (mips_pic == NO_PIC | |
9854 | && fixP->fx_done | |
9855 | && fixP->fx_frag->fr_address >= text_section->vma | |
9856 | && (fixP->fx_frag->fr_address | |
9857 | < text_section->vma + text_section->_raw_size) | |
9858 | && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */ | |
9859 | || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */ | |
9860 | || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */ | |
9861 | { | |
9862 | if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */ | |
9863 | insn = 0x0c000000; /* jal */ | |
9864 | else | |
9865 | insn = 0x08000000; /* j */ | |
9866 | fixP->fx_r_type = BFD_RELOC_MIPS_JMP; | |
9867 | fixP->fx_done = 0; | |
9868 | fixP->fx_addsy = section_symbol (text_section); | |
9869 | fixP->fx_addnumber = (value << 2) + md_pcrel_from (fixP); | |
9870 | } | |
9871 | else | |
9872 | { | |
9873 | /* FIXME. It would be possible in principle to handle | |
9874 | conditional branches which overflow. They could be | |
9875 | transformed into a branch around a jump. This would | |
9876 | require setting up variant frags for each different | |
9877 | branch type. The native MIPS assembler attempts to | |
9878 | handle these cases, but it appears to do it | |
9879 | incorrectly. */ | |
9880 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
9881 | _("Branch out of range")); | |
9882 | } | |
9883 | } | |
9884 | ||
9885 | md_number_to_chars ((char *) buf, (valueT) insn, 4); | |
9886 | break; | |
9887 | ||
9888 | case BFD_RELOC_VTABLE_INHERIT: | |
9889 | fixP->fx_done = 0; | |
9890 | if (fixP->fx_addsy | |
9891 | && !S_IS_DEFINED (fixP->fx_addsy) | |
9892 | && !S_IS_WEAK (fixP->fx_addsy)) | |
9893 | S_SET_WEAK (fixP->fx_addsy); | |
9894 | break; | |
9895 | ||
9896 | case BFD_RELOC_VTABLE_ENTRY: | |
9897 | fixP->fx_done = 0; | |
9898 | break; | |
9899 | ||
9900 | default: | |
9901 | internalError (); | |
9902 | } | |
9903 | ||
9904 | return 1; | |
9905 | } | |
9906 | ||
9907 | #if 0 | |
9908 | void | |
9909 | printInsn (oc) | |
9910 | unsigned long oc; | |
9911 | { | |
9912 | const struct mips_opcode *p; | |
9913 | int treg, sreg, dreg, shamt; | |
9914 | short imm; | |
9915 | const char *args; | |
9916 | int i; | |
9917 | ||
9918 | for (i = 0; i < NUMOPCODES; ++i) | |
9919 | { | |
9920 | p = &mips_opcodes[i]; | |
9921 | if (((oc & p->mask) == p->match) && (p->pinfo != INSN_MACRO)) | |
9922 | { | |
9923 | printf ("%08lx %s\t", oc, p->name); | |
9924 | treg = (oc >> 16) & 0x1f; | |
9925 | sreg = (oc >> 21) & 0x1f; | |
9926 | dreg = (oc >> 11) & 0x1f; | |
9927 | shamt = (oc >> 6) & 0x1f; | |
9928 | imm = oc; | |
9929 | for (args = p->args;; ++args) | |
9930 | { | |
9931 | switch (*args) | |
9932 | { | |
9933 | case '\0': | |
9934 | printf ("\n"); | |
9935 | break; | |
9936 | ||
9937 | case ',': | |
9938 | case '(': | |
9939 | case ')': | |
9940 | printf ("%c", *args); | |
9941 | continue; | |
9942 | ||
9943 | case 'r': | |
9944 | assert (treg == sreg); | |
9945 | printf ("$%d,$%d", treg, sreg); | |
9946 | continue; | |
9947 | ||
9948 | case 'd': | |
9949 | case 'G': | |
9950 | printf ("$%d", dreg); | |
9951 | continue; | |
9952 | ||
9953 | case 't': | |
9954 | case 'E': | |
9955 | printf ("$%d", treg); | |
9956 | continue; | |
9957 | ||
9958 | case 'k': | |
9959 | printf ("0x%x", treg); | |
9960 | continue; | |
9961 | ||
9962 | case 'b': | |
9963 | case 's': | |
9964 | printf ("$%d", sreg); | |
9965 | continue; | |
9966 | ||
9967 | case 'a': | |
9968 | printf ("0x%08lx", oc & 0x1ffffff); | |
9969 | continue; | |
9970 | ||
9971 | case 'i': | |
9972 | case 'j': | |
9973 | case 'o': | |
9974 | case 'u': | |
9975 | printf ("%d", imm); | |
9976 | continue; | |
9977 | ||
9978 | case '<': | |
9979 | case '>': | |
9980 | printf ("$%d", shamt); | |
9981 | continue; | |
9982 | ||
9983 | default: | |
9984 | internalError (); | |
9985 | } | |
9986 | break; | |
9987 | } | |
9988 | return; | |
9989 | } | |
9990 | } | |
9991 | printf (_("%08lx UNDEFINED\n"), oc); | |
9992 | } | |
9993 | #endif | |
9994 | ||
9995 | static symbolS * | |
9996 | get_symbol () | |
9997 | { | |
9998 | int c; | |
9999 | char *name; | |
10000 | symbolS *p; | |
10001 | ||
10002 | name = input_line_pointer; | |
10003 | c = get_symbol_end (); | |
10004 | p = (symbolS *) symbol_find_or_make (name); | |
10005 | *input_line_pointer = c; | |
10006 | return p; | |
10007 | } | |
10008 | ||
10009 | /* Align the current frag to a given power of two. The MIPS assembler | |
10010 | also automatically adjusts any preceding label. */ | |
10011 | ||
10012 | static void | |
10013 | mips_align (to, fill, label) | |
10014 | int to; | |
10015 | int fill; | |
10016 | symbolS *label; | |
10017 | { | |
10018 | mips_emit_delays (false); | |
10019 | frag_align (to, fill, 0); | |
10020 | record_alignment (now_seg, to); | |
10021 | if (label != NULL) | |
10022 | { | |
10023 | assert (S_GET_SEGMENT (label) == now_seg); | |
49309057 | 10024 | symbol_set_frag (label, frag_now); |
252b5132 RH |
10025 | S_SET_VALUE (label, (valueT) frag_now_fix ()); |
10026 | } | |
10027 | } | |
10028 | ||
10029 | /* Align to a given power of two. .align 0 turns off the automatic | |
10030 | alignment used by the data creating pseudo-ops. */ | |
10031 | ||
10032 | static void | |
10033 | s_align (x) | |
43841e91 | 10034 | int x ATTRIBUTE_UNUSED; |
252b5132 RH |
10035 | { |
10036 | register int temp; | |
10037 | register long temp_fill; | |
10038 | long max_alignment = 15; | |
10039 | ||
10040 | /* | |
10041 | ||
10042 | o Note that the assembler pulls down any immediately preceeding label | |
10043 | to the aligned address. | |
10044 | o It's not documented but auto alignment is reinstated by | |
10045 | a .align pseudo instruction. | |
10046 | o Note also that after auto alignment is turned off the mips assembler | |
10047 | issues an error on attempt to assemble an improperly aligned data item. | |
10048 | We don't. | |
10049 | ||
10050 | */ | |
10051 | ||
10052 | temp = get_absolute_expression (); | |
10053 | if (temp > max_alignment) | |
10054 | as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment); | |
10055 | else if (temp < 0) | |
10056 | { | |
10057 | as_warn (_("Alignment negative: 0 assumed.")); | |
10058 | temp = 0; | |
10059 | } | |
10060 | if (*input_line_pointer == ',') | |
10061 | { | |
10062 | input_line_pointer++; | |
10063 | temp_fill = get_absolute_expression (); | |
10064 | } | |
10065 | else | |
10066 | temp_fill = 0; | |
10067 | if (temp) | |
10068 | { | |
10069 | auto_align = 1; | |
10070 | mips_align (temp, (int) temp_fill, | |
10071 | insn_labels != NULL ? insn_labels->label : NULL); | |
10072 | } | |
10073 | else | |
10074 | { | |
10075 | auto_align = 0; | |
10076 | } | |
10077 | ||
10078 | demand_empty_rest_of_line (); | |
10079 | } | |
10080 | ||
10081 | void | |
10082 | mips_flush_pending_output () | |
10083 | { | |
10084 | mips_emit_delays (false); | |
10085 | mips_clear_insn_labels (); | |
10086 | } | |
10087 | ||
10088 | static void | |
10089 | s_change_sec (sec) | |
10090 | int sec; | |
10091 | { | |
10092 | segT seg; | |
10093 | ||
10094 | /* When generating embedded PIC code, we only use the .text, .lit8, | |
10095 | .sdata and .sbss sections. We change the .data and .rdata | |
10096 | pseudo-ops to use .sdata. */ | |
10097 | if (mips_pic == EMBEDDED_PIC | |
10098 | && (sec == 'd' || sec == 'r')) | |
10099 | sec = 's'; | |
10100 | ||
10101 | #ifdef OBJ_ELF | |
10102 | /* The ELF backend needs to know that we are changing sections, so | |
10103 | that .previous works correctly. We could do something like check | |
10104 | for a obj_section_change_hook macro, but that might be confusing | |
10105 | as it would not be appropriate to use it in the section changing | |
10106 | functions in read.c, since obj-elf.c intercepts those. FIXME: | |
10107 | This should be cleaner, somehow. */ | |
10108 | obj_elf_section_change_hook (); | |
10109 | #endif | |
10110 | ||
10111 | mips_emit_delays (false); | |
10112 | switch (sec) | |
10113 | { | |
10114 | case 't': | |
10115 | s_text (0); | |
10116 | break; | |
10117 | case 'd': | |
10118 | s_data (0); | |
10119 | break; | |
10120 | case 'b': | |
10121 | subseg_set (bss_section, (subsegT) get_absolute_expression ()); | |
10122 | demand_empty_rest_of_line (); | |
10123 | break; | |
10124 | ||
10125 | case 'r': | |
10126 | if (USE_GLOBAL_POINTER_OPT) | |
10127 | { | |
10128 | seg = subseg_new (RDATA_SECTION_NAME, | |
10129 | (subsegT) get_absolute_expression ()); | |
10130 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
10131 | { | |
10132 | bfd_set_section_flags (stdoutput, seg, | |
10133 | (SEC_ALLOC | |
10134 | | SEC_LOAD | |
10135 | | SEC_READONLY | |
10136 | | SEC_RELOC | |
10137 | | SEC_DATA)); | |
10138 | if (strcmp (TARGET_OS, "elf") != 0) | |
e799a695 | 10139 | record_alignment (seg, 4); |
252b5132 RH |
10140 | } |
10141 | demand_empty_rest_of_line (); | |
10142 | } | |
10143 | else | |
10144 | { | |
10145 | as_bad (_("No read only data section in this object file format")); | |
10146 | demand_empty_rest_of_line (); | |
10147 | return; | |
10148 | } | |
10149 | break; | |
10150 | ||
10151 | case 's': | |
10152 | if (USE_GLOBAL_POINTER_OPT) | |
10153 | { | |
10154 | seg = subseg_new (".sdata", (subsegT) get_absolute_expression ()); | |
10155 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
10156 | { | |
10157 | bfd_set_section_flags (stdoutput, seg, | |
10158 | SEC_ALLOC | SEC_LOAD | SEC_RELOC | |
10159 | | SEC_DATA); | |
10160 | if (strcmp (TARGET_OS, "elf") != 0) | |
e799a695 | 10161 | record_alignment (seg, 4); |
252b5132 RH |
10162 | } |
10163 | demand_empty_rest_of_line (); | |
10164 | break; | |
10165 | } | |
10166 | else | |
10167 | { | |
10168 | as_bad (_("Global pointers not supported; recompile -G 0")); | |
10169 | demand_empty_rest_of_line (); | |
10170 | return; | |
10171 | } | |
10172 | } | |
10173 | ||
10174 | auto_align = 1; | |
10175 | } | |
10176 | ||
10177 | void | |
10178 | mips_enable_auto_align () | |
10179 | { | |
10180 | auto_align = 1; | |
10181 | } | |
10182 | ||
10183 | static void | |
10184 | s_cons (log_size) | |
10185 | int log_size; | |
10186 | { | |
10187 | symbolS *label; | |
10188 | ||
10189 | label = insn_labels != NULL ? insn_labels->label : NULL; | |
10190 | mips_emit_delays (false); | |
10191 | if (log_size > 0 && auto_align) | |
10192 | mips_align (log_size, 0, label); | |
10193 | mips_clear_insn_labels (); | |
10194 | cons (1 << log_size); | |
10195 | } | |
10196 | ||
10197 | static void | |
10198 | s_float_cons (type) | |
10199 | int type; | |
10200 | { | |
10201 | symbolS *label; | |
10202 | ||
10203 | label = insn_labels != NULL ? insn_labels->label : NULL; | |
10204 | ||
10205 | mips_emit_delays (false); | |
10206 | ||
10207 | if (auto_align) | |
49309057 ILT |
10208 | { |
10209 | if (type == 'd') | |
10210 | mips_align (3, 0, label); | |
10211 | else | |
10212 | mips_align (2, 0, label); | |
10213 | } | |
252b5132 RH |
10214 | |
10215 | mips_clear_insn_labels (); | |
10216 | ||
10217 | float_cons (type); | |
10218 | } | |
10219 | ||
10220 | /* Handle .globl. We need to override it because on Irix 5 you are | |
10221 | permitted to say | |
10222 | .globl foo .text | |
10223 | where foo is an undefined symbol, to mean that foo should be | |
10224 | considered to be the address of a function. */ | |
10225 | ||
10226 | static void | |
10227 | s_mips_globl (x) | |
43841e91 | 10228 | int x ATTRIBUTE_UNUSED; |
252b5132 RH |
10229 | { |
10230 | char *name; | |
10231 | int c; | |
10232 | symbolS *symbolP; | |
10233 | flagword flag; | |
10234 | ||
10235 | name = input_line_pointer; | |
10236 | c = get_symbol_end (); | |
10237 | symbolP = symbol_find_or_make (name); | |
10238 | *input_line_pointer = c; | |
10239 | SKIP_WHITESPACE (); | |
10240 | ||
10241 | /* On Irix 5, every global symbol that is not explicitly labelled as | |
10242 | being a function is apparently labelled as being an object. */ | |
10243 | flag = BSF_OBJECT; | |
10244 | ||
10245 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
10246 | { | |
10247 | char *secname; | |
10248 | asection *sec; | |
10249 | ||
10250 | secname = input_line_pointer; | |
10251 | c = get_symbol_end (); | |
10252 | sec = bfd_get_section_by_name (stdoutput, secname); | |
10253 | if (sec == NULL) | |
10254 | as_bad (_("%s: no such section"), secname); | |
10255 | *input_line_pointer = c; | |
10256 | ||
10257 | if (sec != NULL && (sec->flags & SEC_CODE) != 0) | |
10258 | flag = BSF_FUNCTION; | |
10259 | } | |
10260 | ||
49309057 | 10261 | symbol_get_bfdsym (symbolP)->flags |= flag; |
252b5132 RH |
10262 | |
10263 | S_SET_EXTERNAL (symbolP); | |
10264 | demand_empty_rest_of_line (); | |
10265 | } | |
10266 | ||
10267 | static void | |
10268 | s_option (x) | |
43841e91 | 10269 | int x ATTRIBUTE_UNUSED; |
252b5132 RH |
10270 | { |
10271 | char *opt; | |
10272 | char c; | |
10273 | ||
10274 | opt = input_line_pointer; | |
10275 | c = get_symbol_end (); | |
10276 | ||
10277 | if (*opt == 'O') | |
10278 | { | |
10279 | /* FIXME: What does this mean? */ | |
10280 | } | |
10281 | else if (strncmp (opt, "pic", 3) == 0) | |
10282 | { | |
10283 | int i; | |
10284 | ||
10285 | i = atoi (opt + 3); | |
10286 | if (i == 0) | |
10287 | mips_pic = NO_PIC; | |
10288 | else if (i == 2) | |
10289 | mips_pic = SVR4_PIC; | |
10290 | else | |
10291 | as_bad (_(".option pic%d not supported"), i); | |
10292 | ||
10293 | if (USE_GLOBAL_POINTER_OPT && mips_pic == SVR4_PIC) | |
10294 | { | |
10295 | if (g_switch_seen && g_switch_value != 0) | |
10296 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
10297 | g_switch_value = 0; | |
10298 | bfd_set_gp_size (stdoutput, 0); | |
10299 | } | |
10300 | } | |
10301 | else | |
10302 | as_warn (_("Unrecognized option \"%s\""), opt); | |
10303 | ||
10304 | *input_line_pointer = c; | |
10305 | demand_empty_rest_of_line (); | |
10306 | } | |
10307 | ||
10308 | /* This structure is used to hold a stack of .set values. */ | |
10309 | ||
e972090a NC |
10310 | struct mips_option_stack |
10311 | { | |
252b5132 RH |
10312 | struct mips_option_stack *next; |
10313 | struct mips_set_options options; | |
10314 | }; | |
10315 | ||
10316 | static struct mips_option_stack *mips_opts_stack; | |
10317 | ||
10318 | /* Handle the .set pseudo-op. */ | |
10319 | ||
10320 | static void | |
10321 | s_mipsset (x) | |
43841e91 | 10322 | int x ATTRIBUTE_UNUSED; |
252b5132 RH |
10323 | { |
10324 | char *name = input_line_pointer, ch; | |
10325 | ||
10326 | while (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
10327 | input_line_pointer++; | |
10328 | ch = *input_line_pointer; | |
10329 | *input_line_pointer = '\0'; | |
10330 | ||
10331 | if (strcmp (name, "reorder") == 0) | |
10332 | { | |
10333 | if (mips_opts.noreorder && prev_nop_frag != NULL) | |
10334 | { | |
10335 | /* If we still have pending nops, we can discard them. The | |
10336 | usual nop handling will insert any that are still | |
bdaaa2e1 | 10337 | needed. */ |
252b5132 RH |
10338 | prev_nop_frag->fr_fix -= (prev_nop_frag_holds |
10339 | * (mips_opts.mips16 ? 2 : 4)); | |
10340 | prev_nop_frag = NULL; | |
10341 | } | |
10342 | mips_opts.noreorder = 0; | |
10343 | } | |
10344 | else if (strcmp (name, "noreorder") == 0) | |
10345 | { | |
10346 | mips_emit_delays (true); | |
10347 | mips_opts.noreorder = 1; | |
10348 | mips_any_noreorder = 1; | |
10349 | } | |
10350 | else if (strcmp (name, "at") == 0) | |
10351 | { | |
10352 | mips_opts.noat = 0; | |
10353 | } | |
10354 | else if (strcmp (name, "noat") == 0) | |
10355 | { | |
10356 | mips_opts.noat = 1; | |
10357 | } | |
10358 | else if (strcmp (name, "macro") == 0) | |
10359 | { | |
10360 | mips_opts.warn_about_macros = 0; | |
10361 | } | |
10362 | else if (strcmp (name, "nomacro") == 0) | |
10363 | { | |
10364 | if (mips_opts.noreorder == 0) | |
10365 | as_bad (_("`noreorder' must be set before `nomacro'")); | |
10366 | mips_opts.warn_about_macros = 1; | |
10367 | } | |
10368 | else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0) | |
10369 | { | |
10370 | mips_opts.nomove = 0; | |
10371 | } | |
10372 | else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0) | |
10373 | { | |
10374 | mips_opts.nomove = 1; | |
10375 | } | |
10376 | else if (strcmp (name, "bopt") == 0) | |
10377 | { | |
10378 | mips_opts.nobopt = 0; | |
10379 | } | |
10380 | else if (strcmp (name, "nobopt") == 0) | |
10381 | { | |
10382 | mips_opts.nobopt = 1; | |
10383 | } | |
10384 | else if (strcmp (name, "mips16") == 0 | |
10385 | || strcmp (name, "MIPS-16") == 0) | |
10386 | mips_opts.mips16 = 1; | |
10387 | else if (strcmp (name, "nomips16") == 0 | |
10388 | || strcmp (name, "noMIPS-16") == 0) | |
10389 | mips_opts.mips16 = 0; | |
10390 | else if (strncmp (name, "mips", 4) == 0) | |
10391 | { | |
10392 | int isa; | |
10393 | ||
10394 | /* Permit the user to change the ISA on the fly. Needless to | |
10395 | say, misuse can cause serious problems. */ | |
10396 | isa = atoi (name + 4); | |
e7af610e NC |
10397 | switch (isa) |
10398 | { | |
84ea6cf2 NC |
10399 | case 0: mips_opts.isa = file_mips_isa; break; |
10400 | case 1: mips_opts.isa = ISA_MIPS1; break; | |
10401 | case 2: mips_opts.isa = ISA_MIPS2; break; | |
10402 | case 3: mips_opts.isa = ISA_MIPS3; break; | |
10403 | case 5: mips_opts.isa = ISA_MIPS5; break; | |
10404 | case 4: mips_opts.isa = ISA_MIPS4; break; | |
10405 | case 32: mips_opts.isa = ISA_MIPS32; break; | |
10406 | case 64: mips_opts.isa = ISA_MIPS64; break; | |
10407 | default: as_bad (_("unknown ISA level")); break; | |
e7af610e | 10408 | } |
252b5132 RH |
10409 | } |
10410 | else if (strcmp (name, "autoextend") == 0) | |
10411 | mips_opts.noautoextend = 0; | |
10412 | else if (strcmp (name, "noautoextend") == 0) | |
10413 | mips_opts.noautoextend = 1; | |
10414 | else if (strcmp (name, "push") == 0) | |
10415 | { | |
10416 | struct mips_option_stack *s; | |
10417 | ||
10418 | s = (struct mips_option_stack *) xmalloc (sizeof *s); | |
10419 | s->next = mips_opts_stack; | |
10420 | s->options = mips_opts; | |
10421 | mips_opts_stack = s; | |
10422 | } | |
10423 | else if (strcmp (name, "pop") == 0) | |
10424 | { | |
10425 | struct mips_option_stack *s; | |
10426 | ||
10427 | s = mips_opts_stack; | |
10428 | if (s == NULL) | |
10429 | as_bad (_(".set pop with no .set push")); | |
10430 | else | |
10431 | { | |
10432 | /* If we're changing the reorder mode we need to handle | |
10433 | delay slots correctly. */ | |
10434 | if (s->options.noreorder && ! mips_opts.noreorder) | |
10435 | mips_emit_delays (true); | |
10436 | else if (! s->options.noreorder && mips_opts.noreorder) | |
10437 | { | |
10438 | if (prev_nop_frag != NULL) | |
10439 | { | |
10440 | prev_nop_frag->fr_fix -= (prev_nop_frag_holds | |
10441 | * (mips_opts.mips16 ? 2 : 4)); | |
10442 | prev_nop_frag = NULL; | |
10443 | } | |
10444 | } | |
10445 | ||
10446 | mips_opts = s->options; | |
10447 | mips_opts_stack = s->next; | |
10448 | free (s); | |
10449 | } | |
10450 | } | |
10451 | else | |
10452 | { | |
10453 | as_warn (_("Tried to set unrecognized symbol: %s\n"), name); | |
10454 | } | |
10455 | *input_line_pointer = ch; | |
10456 | demand_empty_rest_of_line (); | |
10457 | } | |
10458 | ||
10459 | /* Handle the .abicalls pseudo-op. I believe this is equivalent to | |
10460 | .option pic2. It means to generate SVR4 PIC calls. */ | |
10461 | ||
10462 | static void | |
10463 | s_abicalls (ignore) | |
43841e91 | 10464 | int ignore ATTRIBUTE_UNUSED; |
252b5132 RH |
10465 | { |
10466 | mips_pic = SVR4_PIC; | |
10467 | if (USE_GLOBAL_POINTER_OPT) | |
10468 | { | |
10469 | if (g_switch_seen && g_switch_value != 0) | |
10470 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
10471 | g_switch_value = 0; | |
10472 | } | |
10473 | bfd_set_gp_size (stdoutput, 0); | |
10474 | demand_empty_rest_of_line (); | |
10475 | } | |
10476 | ||
10477 | /* Handle the .cpload pseudo-op. This is used when generating SVR4 | |
10478 | PIC code. It sets the $gp register for the function based on the | |
10479 | function address, which is in the register named in the argument. | |
10480 | This uses a relocation against _gp_disp, which is handled specially | |
10481 | by the linker. The result is: | |
10482 | lui $gp,%hi(_gp_disp) | |
10483 | addiu $gp,$gp,%lo(_gp_disp) | |
10484 | addu $gp,$gp,.cpload argument | |
10485 | The .cpload argument is normally $25 == $t9. */ | |
10486 | ||
10487 | static void | |
10488 | s_cpload (ignore) | |
43841e91 | 10489 | int ignore ATTRIBUTE_UNUSED; |
252b5132 RH |
10490 | { |
10491 | expressionS ex; | |
10492 | int icnt = 0; | |
10493 | ||
10494 | /* If we are not generating SVR4 PIC code, .cpload is ignored. */ | |
10495 | if (mips_pic != SVR4_PIC) | |
10496 | { | |
10497 | s_ignore (0); | |
10498 | return; | |
10499 | } | |
10500 | ||
10501 | /* .cpload should be a in .set noreorder section. */ | |
10502 | if (mips_opts.noreorder == 0) | |
10503 | as_warn (_(".cpload not in noreorder section")); | |
10504 | ||
10505 | ex.X_op = O_symbol; | |
10506 | ex.X_add_symbol = symbol_find_or_make ("_gp_disp"); | |
10507 | ex.X_op_symbol = NULL; | |
10508 | ex.X_add_number = 0; | |
10509 | ||
10510 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ | |
49309057 | 10511 | symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; |
252b5132 RH |
10512 | |
10513 | macro_build_lui ((char *) NULL, &icnt, &ex, GP); | |
10514 | macro_build ((char *) NULL, &icnt, &ex, "addiu", "t,r,j", GP, GP, | |
10515 | (int) BFD_RELOC_LO16); | |
10516 | ||
10517 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "addu", "d,v,t", | |
10518 | GP, GP, tc_get_register (0)); | |
10519 | ||
10520 | demand_empty_rest_of_line (); | |
10521 | } | |
10522 | ||
10523 | /* Handle the .cprestore pseudo-op. This stores $gp into a given | |
10524 | offset from $sp. The offset is remembered, and after making a PIC | |
10525 | call $gp is restored from that location. */ | |
10526 | ||
10527 | static void | |
10528 | s_cprestore (ignore) | |
43841e91 | 10529 | int ignore ATTRIBUTE_UNUSED; |
252b5132 RH |
10530 | { |
10531 | expressionS ex; | |
10532 | int icnt = 0; | |
10533 | ||
10534 | /* If we are not generating SVR4 PIC code, .cprestore is ignored. */ | |
10535 | if (mips_pic != SVR4_PIC) | |
10536 | { | |
10537 | s_ignore (0); | |
10538 | return; | |
10539 | } | |
10540 | ||
10541 | mips_cprestore_offset = get_absolute_expression (); | |
10542 | ||
10543 | ex.X_op = O_constant; | |
10544 | ex.X_add_symbol = NULL; | |
10545 | ex.X_op_symbol = NULL; | |
10546 | ex.X_add_number = mips_cprestore_offset; | |
10547 | ||
10548 | macro_build ((char *) NULL, &icnt, &ex, | |
10549 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 10550 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
10551 | ? "sw" : "sd"), |
10552 | "t,o(b)", GP, (int) BFD_RELOC_LO16, SP); | |
10553 | ||
10554 | demand_empty_rest_of_line (); | |
10555 | } | |
10556 | ||
10557 | /* Handle the .gpword pseudo-op. This is used when generating PIC | |
10558 | code. It generates a 32 bit GP relative reloc. */ | |
10559 | ||
10560 | static void | |
10561 | s_gpword (ignore) | |
43841e91 | 10562 | int ignore ATTRIBUTE_UNUSED; |
252b5132 RH |
10563 | { |
10564 | symbolS *label; | |
10565 | expressionS ex; | |
10566 | char *p; | |
10567 | ||
10568 | /* When not generating PIC code, this is treated as .word. */ | |
10569 | if (mips_pic != SVR4_PIC) | |
10570 | { | |
10571 | s_cons (2); | |
10572 | return; | |
10573 | } | |
10574 | ||
10575 | label = insn_labels != NULL ? insn_labels->label : NULL; | |
10576 | mips_emit_delays (true); | |
10577 | if (auto_align) | |
10578 | mips_align (2, 0, label); | |
10579 | mips_clear_insn_labels (); | |
10580 | ||
10581 | expression (&ex); | |
10582 | ||
10583 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
10584 | { | |
10585 | as_bad (_("Unsupported use of .gpword")); | |
10586 | ignore_rest_of_line (); | |
10587 | } | |
10588 | ||
10589 | p = frag_more (4); | |
10590 | md_number_to_chars (p, (valueT) 0, 4); | |
10591 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, 0, | |
10592 | BFD_RELOC_MIPS_GPREL32); | |
10593 | ||
10594 | demand_empty_rest_of_line (); | |
10595 | } | |
10596 | ||
10597 | /* Handle the .cpadd pseudo-op. This is used when dealing with switch | |
10598 | tables in SVR4 PIC code. */ | |
10599 | ||
10600 | static void | |
10601 | s_cpadd (ignore) | |
43841e91 | 10602 | int ignore ATTRIBUTE_UNUSED; |
252b5132 RH |
10603 | { |
10604 | int icnt = 0; | |
10605 | int reg; | |
10606 | ||
10607 | /* This is ignored when not generating SVR4 PIC code. */ | |
10608 | if (mips_pic != SVR4_PIC) | |
10609 | { | |
10610 | s_ignore (0); | |
10611 | return; | |
10612 | } | |
10613 | ||
10614 | /* Add $gp to the register named as an argument. */ | |
10615 | reg = tc_get_register (0); | |
10616 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
10617 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 10618 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
10619 | ? "addu" : "daddu"), |
10620 | "d,v,t", reg, reg, GP); | |
10621 | ||
bdaaa2e1 | 10622 | demand_empty_rest_of_line (); |
252b5132 RH |
10623 | } |
10624 | ||
10625 | /* Handle the .insn pseudo-op. This marks instruction labels in | |
10626 | mips16 mode. This permits the linker to handle them specially, | |
10627 | such as generating jalx instructions when needed. We also make | |
10628 | them odd for the duration of the assembly, in order to generate the | |
10629 | right sort of code. We will make them even in the adjust_symtab | |
10630 | routine, while leaving them marked. This is convenient for the | |
10631 | debugger and the disassembler. The linker knows to make them odd | |
10632 | again. */ | |
10633 | ||
10634 | static void | |
10635 | s_insn (ignore) | |
43841e91 | 10636 | int ignore ATTRIBUTE_UNUSED; |
252b5132 RH |
10637 | { |
10638 | if (mips_opts.mips16) | |
10639 | mips16_mark_labels (); | |
10640 | ||
10641 | demand_empty_rest_of_line (); | |
10642 | } | |
10643 | ||
10644 | /* Handle a .stabn directive. We need these in order to mark a label | |
10645 | as being a mips16 text label correctly. Sometimes the compiler | |
10646 | will emit a label, followed by a .stabn, and then switch sections. | |
10647 | If the label and .stabn are in mips16 mode, then the label is | |
10648 | really a mips16 text label. */ | |
10649 | ||
10650 | static void | |
10651 | s_mips_stab (type) | |
10652 | int type; | |
10653 | { | |
10654 | if (type == 'n' && mips_opts.mips16) | |
10655 | mips16_mark_labels (); | |
10656 | ||
10657 | s_stab (type); | |
10658 | } | |
10659 | ||
10660 | /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. | |
10661 | */ | |
10662 | ||
10663 | static void | |
10664 | s_mips_weakext (ignore) | |
43841e91 | 10665 | int ignore ATTRIBUTE_UNUSED; |
252b5132 RH |
10666 | { |
10667 | char *name; | |
10668 | int c; | |
10669 | symbolS *symbolP; | |
10670 | expressionS exp; | |
10671 | ||
10672 | name = input_line_pointer; | |
10673 | c = get_symbol_end (); | |
10674 | symbolP = symbol_find_or_make (name); | |
10675 | S_SET_WEAK (symbolP); | |
10676 | *input_line_pointer = c; | |
10677 | ||
10678 | SKIP_WHITESPACE (); | |
10679 | ||
10680 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
10681 | { | |
10682 | if (S_IS_DEFINED (symbolP)) | |
10683 | { | |
10684 | as_bad ("Ignoring attempt to redefine symbol `%s'.", | |
10685 | S_GET_NAME (symbolP)); | |
10686 | ignore_rest_of_line (); | |
10687 | return; | |
10688 | } | |
bdaaa2e1 | 10689 | |
252b5132 RH |
10690 | if (*input_line_pointer == ',') |
10691 | { | |
10692 | ++input_line_pointer; | |
10693 | SKIP_WHITESPACE (); | |
10694 | } | |
bdaaa2e1 | 10695 | |
252b5132 RH |
10696 | expression (&exp); |
10697 | if (exp.X_op != O_symbol) | |
10698 | { | |
10699 | as_bad ("bad .weakext directive"); | |
10700 | ignore_rest_of_line(); | |
10701 | return; | |
10702 | } | |
49309057 | 10703 | symbol_set_value_expression (symbolP, &exp); |
252b5132 RH |
10704 | } |
10705 | ||
10706 | demand_empty_rest_of_line (); | |
10707 | } | |
10708 | ||
10709 | /* Parse a register string into a number. Called from the ECOFF code | |
10710 | to parse .frame. The argument is non-zero if this is the frame | |
10711 | register, so that we can record it in mips_frame_reg. */ | |
10712 | ||
10713 | int | |
10714 | tc_get_register (frame) | |
10715 | int frame; | |
10716 | { | |
10717 | int reg; | |
10718 | ||
10719 | SKIP_WHITESPACE (); | |
10720 | if (*input_line_pointer++ != '$') | |
10721 | { | |
10722 | as_warn (_("expected `$'")); | |
10723 | reg = 0; | |
10724 | } | |
10725 | else if (isdigit ((unsigned char) *input_line_pointer)) | |
10726 | { | |
10727 | reg = get_absolute_expression (); | |
10728 | if (reg < 0 || reg >= 32) | |
10729 | { | |
10730 | as_warn (_("Bad register number")); | |
10731 | reg = 0; | |
10732 | } | |
10733 | } | |
10734 | else | |
10735 | { | |
10736 | if (strncmp (input_line_pointer, "fp", 2) == 0) | |
10737 | reg = FP; | |
10738 | else if (strncmp (input_line_pointer, "sp", 2) == 0) | |
10739 | reg = SP; | |
10740 | else if (strncmp (input_line_pointer, "gp", 2) == 0) | |
10741 | reg = GP; | |
10742 | else if (strncmp (input_line_pointer, "at", 2) == 0) | |
10743 | reg = AT; | |
10744 | else | |
10745 | { | |
10746 | as_warn (_("Unrecognized register name")); | |
10747 | reg = 0; | |
10748 | } | |
10749 | input_line_pointer += 2; | |
10750 | } | |
10751 | if (frame) | |
10752 | mips_frame_reg = reg != 0 ? reg : SP; | |
10753 | return reg; | |
10754 | } | |
10755 | ||
10756 | valueT | |
10757 | md_section_align (seg, addr) | |
10758 | asection *seg; | |
10759 | valueT addr; | |
10760 | { | |
10761 | int align = bfd_get_section_alignment (stdoutput, seg); | |
10762 | ||
10763 | #ifdef OBJ_ELF | |
10764 | /* We don't need to align ELF sections to the full alignment. | |
10765 | However, Irix 5 may prefer that we align them at least to a 16 | |
10766 | byte boundary. We don't bother to align the sections if we are | |
10767 | targeted for an embedded system. */ | |
10768 | if (strcmp (TARGET_OS, "elf") == 0) | |
10769 | return addr; | |
10770 | if (align > 4) | |
10771 | align = 4; | |
10772 | #endif | |
10773 | ||
10774 | return ((addr + (1 << align) - 1) & (-1 << align)); | |
10775 | } | |
10776 | ||
10777 | /* Utility routine, called from above as well. If called while the | |
10778 | input file is still being read, it's only an approximation. (For | |
10779 | example, a symbol may later become defined which appeared to be | |
10780 | undefined earlier.) */ | |
10781 | ||
10782 | static int | |
10783 | nopic_need_relax (sym, before_relaxing) | |
10784 | symbolS *sym; | |
10785 | int before_relaxing; | |
10786 | { | |
10787 | if (sym == 0) | |
10788 | return 0; | |
10789 | ||
10790 | if (USE_GLOBAL_POINTER_OPT) | |
10791 | { | |
10792 | const char *symname; | |
10793 | int change; | |
10794 | ||
10795 | /* Find out whether this symbol can be referenced off the GP | |
10796 | register. It can be if it is smaller than the -G size or if | |
10797 | it is in the .sdata or .sbss section. Certain symbols can | |
10798 | not be referenced off the GP, although it appears as though | |
10799 | they can. */ | |
10800 | symname = S_GET_NAME (sym); | |
10801 | if (symname != (const char *) NULL | |
10802 | && (strcmp (symname, "eprol") == 0 | |
10803 | || strcmp (symname, "etext") == 0 | |
10804 | || strcmp (symname, "_gp") == 0 | |
10805 | || strcmp (symname, "edata") == 0 | |
10806 | || strcmp (symname, "_fbss") == 0 | |
10807 | || strcmp (symname, "_fdata") == 0 | |
10808 | || strcmp (symname, "_ftext") == 0 | |
10809 | || strcmp (symname, "end") == 0 | |
10810 | || strcmp (symname, "_gp_disp") == 0)) | |
10811 | change = 1; | |
10812 | else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym)) | |
10813 | && (0 | |
10814 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 ILT |
10815 | || (symbol_get_obj (sym)->ecoff_extern_size != 0 |
10816 | && (symbol_get_obj (sym)->ecoff_extern_size | |
10817 | <= g_switch_value)) | |
252b5132 RH |
10818 | #endif |
10819 | /* We must defer this decision until after the whole | |
10820 | file has been read, since there might be a .extern | |
10821 | after the first use of this symbol. */ | |
10822 | || (before_relaxing | |
10823 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 | 10824 | && symbol_get_obj (sym)->ecoff_extern_size == 0 |
252b5132 RH |
10825 | #endif |
10826 | && S_GET_VALUE (sym) == 0) | |
10827 | || (S_GET_VALUE (sym) != 0 | |
10828 | && S_GET_VALUE (sym) <= g_switch_value))) | |
10829 | change = 0; | |
10830 | else | |
10831 | { | |
10832 | const char *segname; | |
10833 | ||
10834 | segname = segment_name (S_GET_SEGMENT (sym)); | |
10835 | assert (strcmp (segname, ".lit8") != 0 | |
10836 | && strcmp (segname, ".lit4") != 0); | |
10837 | change = (strcmp (segname, ".sdata") != 0 | |
fba2b7f9 GK |
10838 | && strcmp (segname, ".sbss") != 0 |
10839 | && strncmp (segname, ".sdata.", 7) != 0 | |
10840 | && strncmp (segname, ".gnu.linkonce.s.", 16) != 0); | |
252b5132 RH |
10841 | } |
10842 | return change; | |
10843 | } | |
10844 | else | |
10845 | /* We are not optimizing for the GP register. */ | |
10846 | return 1; | |
10847 | } | |
10848 | ||
10849 | /* Given a mips16 variant frag FRAGP, return non-zero if it needs an | |
10850 | extended opcode. SEC is the section the frag is in. */ | |
10851 | ||
10852 | static int | |
10853 | mips16_extended_frag (fragp, sec, stretch) | |
10854 | fragS *fragp; | |
10855 | asection *sec; | |
10856 | long stretch; | |
10857 | { | |
10858 | int type; | |
10859 | register const struct mips16_immed_operand *op; | |
10860 | offsetT val; | |
10861 | int mintiny, maxtiny; | |
10862 | segT symsec; | |
98aa84af | 10863 | fragS *sym_frag; |
252b5132 RH |
10864 | |
10865 | if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype)) | |
10866 | return 0; | |
10867 | if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype)) | |
10868 | return 1; | |
10869 | ||
10870 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
10871 | op = mips16_immed_operands; | |
10872 | while (op->type != type) | |
10873 | { | |
10874 | ++op; | |
10875 | assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); | |
10876 | } | |
10877 | ||
10878 | if (op->unsp) | |
10879 | { | |
10880 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
10881 | { | |
10882 | mintiny = 1; | |
10883 | maxtiny = 1 << op->nbits; | |
10884 | } | |
10885 | else | |
10886 | { | |
10887 | mintiny = 0; | |
10888 | maxtiny = (1 << op->nbits) - 1; | |
10889 | } | |
10890 | } | |
10891 | else | |
10892 | { | |
10893 | mintiny = - (1 << (op->nbits - 1)); | |
10894 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
10895 | } | |
10896 | ||
98aa84af | 10897 | sym_frag = symbol_get_frag (fragp->fr_symbol); |
ac62c346 | 10898 | val = S_GET_VALUE (fragp->fr_symbol); |
98aa84af | 10899 | symsec = S_GET_SEGMENT (fragp->fr_symbol); |
252b5132 RH |
10900 | |
10901 | if (op->pcrel) | |
10902 | { | |
10903 | addressT addr; | |
10904 | ||
10905 | /* We won't have the section when we are called from | |
10906 | mips_relax_frag. However, we will always have been called | |
10907 | from md_estimate_size_before_relax first. If this is a | |
10908 | branch to a different section, we mark it as such. If SEC is | |
10909 | NULL, and the frag is not marked, then it must be a branch to | |
10910 | the same section. */ | |
10911 | if (sec == NULL) | |
10912 | { | |
10913 | if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype)) | |
10914 | return 1; | |
10915 | } | |
10916 | else | |
10917 | { | |
98aa84af | 10918 | /* Must have been called from md_estimate_size_before_relax. */ |
252b5132 RH |
10919 | if (symsec != sec) |
10920 | { | |
10921 | fragp->fr_subtype = | |
10922 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
10923 | ||
10924 | /* FIXME: We should support this, and let the linker | |
10925 | catch branches and loads that are out of range. */ | |
10926 | as_bad_where (fragp->fr_file, fragp->fr_line, | |
10927 | _("unsupported PC relative reference to different section")); | |
10928 | ||
10929 | return 1; | |
10930 | } | |
98aa84af AM |
10931 | if (fragp != sym_frag && sym_frag->fr_address == 0) |
10932 | /* Assume non-extended on the first relaxation pass. | |
10933 | The address we have calculated will be bogus if this is | |
10934 | a forward branch to another frag, as the forward frag | |
10935 | will have fr_address == 0. */ | |
10936 | return 0; | |
252b5132 RH |
10937 | } |
10938 | ||
10939 | /* In this case, we know for sure that the symbol fragment is in | |
98aa84af AM |
10940 | the same section. If the relax_marker of the symbol fragment |
10941 | differs from the relax_marker of this fragment, we have not | |
10942 | yet adjusted the symbol fragment fr_address. We want to add | |
252b5132 RH |
10943 | in STRETCH in order to get a better estimate of the address. |
10944 | This particularly matters because of the shift bits. */ | |
10945 | if (stretch != 0 | |
98aa84af | 10946 | && sym_frag->relax_marker != fragp->relax_marker) |
252b5132 RH |
10947 | { |
10948 | fragS *f; | |
10949 | ||
10950 | /* Adjust stretch for any alignment frag. Note that if have | |
10951 | been expanding the earlier code, the symbol may be | |
10952 | defined in what appears to be an earlier frag. FIXME: | |
10953 | This doesn't handle the fr_subtype field, which specifies | |
10954 | a maximum number of bytes to skip when doing an | |
10955 | alignment. */ | |
98aa84af | 10956 | for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next) |
252b5132 RH |
10957 | { |
10958 | if (f->fr_type == rs_align || f->fr_type == rs_align_code) | |
10959 | { | |
10960 | if (stretch < 0) | |
10961 | stretch = - ((- stretch) | |
10962 | & ~ ((1 << (int) f->fr_offset) - 1)); | |
10963 | else | |
10964 | stretch &= ~ ((1 << (int) f->fr_offset) - 1); | |
10965 | if (stretch == 0) | |
10966 | break; | |
10967 | } | |
10968 | } | |
10969 | if (f != NULL) | |
10970 | val += stretch; | |
10971 | } | |
10972 | ||
10973 | addr = fragp->fr_address + fragp->fr_fix; | |
10974 | ||
10975 | /* The base address rules are complicated. The base address of | |
10976 | a branch is the following instruction. The base address of a | |
10977 | PC relative load or add is the instruction itself, but if it | |
10978 | is in a delay slot (in which case it can not be extended) use | |
10979 | the address of the instruction whose delay slot it is in. */ | |
10980 | if (type == 'p' || type == 'q') | |
10981 | { | |
10982 | addr += 2; | |
10983 | ||
10984 | /* If we are currently assuming that this frag should be | |
10985 | extended, then, the current address is two bytes | |
bdaaa2e1 | 10986 | higher. */ |
252b5132 RH |
10987 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) |
10988 | addr += 2; | |
10989 | ||
10990 | /* Ignore the low bit in the target, since it will be set | |
10991 | for a text label. */ | |
10992 | if ((val & 1) != 0) | |
10993 | --val; | |
10994 | } | |
10995 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) | |
10996 | addr -= 4; | |
10997 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
10998 | addr -= 2; | |
10999 | ||
11000 | val -= addr & ~ ((1 << op->shift) - 1); | |
11001 | ||
11002 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
11003 | if (type == 'p' || type == 'q') | |
11004 | val /= 2; | |
11005 | ||
11006 | /* If any of the shifted bits are set, we must use an extended | |
11007 | opcode. If the address depends on the size of this | |
11008 | instruction, this can lead to a loop, so we arrange to always | |
11009 | use an extended opcode. We only check this when we are in | |
11010 | the main relaxation loop, when SEC is NULL. */ | |
11011 | if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL) | |
11012 | { | |
11013 | fragp->fr_subtype = | |
11014 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
11015 | return 1; | |
11016 | } | |
11017 | ||
11018 | /* If we are about to mark a frag as extended because the value | |
11019 | is precisely maxtiny + 1, then there is a chance of an | |
11020 | infinite loop as in the following code: | |
11021 | la $4,foo | |
11022 | .skip 1020 | |
11023 | .align 2 | |
11024 | foo: | |
11025 | In this case when the la is extended, foo is 0x3fc bytes | |
11026 | away, so the la can be shrunk, but then foo is 0x400 away, so | |
11027 | the la must be extended. To avoid this loop, we mark the | |
11028 | frag as extended if it was small, and is about to become | |
11029 | extended with a value of maxtiny + 1. */ | |
11030 | if (val == ((maxtiny + 1) << op->shift) | |
11031 | && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype) | |
11032 | && sec == NULL) | |
11033 | { | |
11034 | fragp->fr_subtype = | |
11035 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
11036 | return 1; | |
11037 | } | |
11038 | } | |
11039 | else if (symsec != absolute_section && sec != NULL) | |
11040 | as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation")); | |
11041 | ||
11042 | if ((val & ((1 << op->shift) - 1)) != 0 | |
11043 | || val < (mintiny << op->shift) | |
11044 | || val > (maxtiny << op->shift)) | |
11045 | return 1; | |
11046 | else | |
11047 | return 0; | |
11048 | } | |
11049 | ||
11050 | /* Estimate the size of a frag before relaxing. Unless this is the | |
11051 | mips16, we are not really relaxing here, and the final size is | |
11052 | encoded in the subtype information. For the mips16, we have to | |
11053 | decide whether we are using an extended opcode or not. */ | |
11054 | ||
252b5132 RH |
11055 | int |
11056 | md_estimate_size_before_relax (fragp, segtype) | |
11057 | fragS *fragp; | |
11058 | asection *segtype; | |
11059 | { | |
43841e91 | 11060 | int change = 0; |
8614eeee | 11061 | boolean linkonce = false; |
252b5132 RH |
11062 | |
11063 | if (RELAX_MIPS16_P (fragp->fr_subtype)) | |
11064 | { | |
11065 | if (mips16_extended_frag (fragp, segtype, 0)) | |
11066 | { | |
11067 | fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype); | |
11068 | return 4; | |
11069 | } | |
11070 | else | |
11071 | { | |
11072 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype); | |
11073 | return 2; | |
11074 | } | |
11075 | } | |
11076 | ||
11077 | if (mips_pic == NO_PIC) | |
11078 | { | |
11079 | change = nopic_need_relax (fragp->fr_symbol, 0); | |
11080 | } | |
11081 | else if (mips_pic == SVR4_PIC) | |
11082 | { | |
11083 | symbolS *sym; | |
11084 | asection *symsec; | |
11085 | ||
11086 | sym = fragp->fr_symbol; | |
11087 | ||
11088 | /* Handle the case of a symbol equated to another symbol. */ | |
49309057 | 11089 | while (symbol_equated_p (sym) |
252b5132 RH |
11090 | && (! S_IS_DEFINED (sym) || S_IS_COMMON (sym))) |
11091 | { | |
11092 | symbolS *n; | |
11093 | ||
11094 | /* It's possible to get a loop here in a badly written | |
11095 | program. */ | |
49309057 | 11096 | n = symbol_get_value_expression (sym)->X_add_symbol; |
252b5132 RH |
11097 | if (n == sym) |
11098 | break; | |
11099 | sym = n; | |
11100 | } | |
11101 | ||
11102 | symsec = S_GET_SEGMENT (sym); | |
11103 | ||
8614eeee UC |
11104 | /* duplicate the test for LINK_ONCE sections as in adjust_reloc_syms */ |
11105 | if (symsec != segtype && ! S_IS_LOCAL (sym)) | |
beae10d5 KH |
11106 | { |
11107 | if ((bfd_get_section_flags (stdoutput, symsec) & SEC_LINK_ONCE) | |
11108 | != 0) | |
11109 | linkonce = true; | |
11110 | ||
11111 | /* The GNU toolchain uses an extension for ELF: a section | |
11112 | beginning with the magic string .gnu.linkonce is a linkonce | |
11113 | section. */ | |
11114 | if (strncmp (segment_name (symsec), ".gnu.linkonce", | |
11115 | sizeof ".gnu.linkonce" - 1) == 0) | |
11116 | linkonce = true; | |
11117 | } | |
8614eeee | 11118 | |
252b5132 RH |
11119 | /* This must duplicate the test in adjust_reloc_syms. */ |
11120 | change = (symsec != &bfd_und_section | |
11121 | && symsec != &bfd_abs_section | |
426b0403 | 11122 | && ! bfd_is_com_section (symsec) |
8614eeee | 11123 | && !linkonce |
426b0403 | 11124 | #ifdef OBJ_ELF |
ea4ff978 L |
11125 | /* A global or weak symbol is treated as external. */ |
11126 | && ! (S_IS_EXTERN (sym) || S_IS_WEAK (sym)) | |
426b0403 AM |
11127 | #endif |
11128 | ); | |
252b5132 RH |
11129 | } |
11130 | else | |
11131 | abort (); | |
11132 | ||
11133 | if (change) | |
11134 | { | |
11135 | /* Record the offset to the first reloc in the fr_opcode field. | |
11136 | This lets md_convert_frag and tc_gen_reloc know that the code | |
11137 | must be expanded. */ | |
11138 | fragp->fr_opcode = (fragp->fr_literal | |
11139 | + fragp->fr_fix | |
11140 | - RELAX_OLD (fragp->fr_subtype) | |
11141 | + RELAX_RELOC1 (fragp->fr_subtype)); | |
11142 | /* FIXME: This really needs as_warn_where. */ | |
11143 | if (RELAX_WARN (fragp->fr_subtype)) | |
11144 | as_warn (_("AT used after \".set noat\" or macro used after \".set nomacro\"")); | |
11145 | } | |
11146 | ||
11147 | if (! change) | |
11148 | return 0; | |
11149 | else | |
11150 | return RELAX_NEW (fragp->fr_subtype) - RELAX_OLD (fragp->fr_subtype); | |
11151 | } | |
11152 | ||
11153 | /* This is called to see whether a reloc against a defined symbol | |
11154 | should be converted into a reloc against a section. Don't adjust | |
11155 | MIPS16 jump relocations, so we don't have to worry about the format | |
11156 | of the offset in the .o file. Don't adjust relocations against | |
11157 | mips16 symbols, so that the linker can find them if it needs to set | |
11158 | up a stub. */ | |
11159 | ||
11160 | int | |
11161 | mips_fix_adjustable (fixp) | |
11162 | fixS *fixp; | |
11163 | { | |
ea4ff978 L |
11164 | #ifdef OBJ_ELF |
11165 | /* Prevent all adjustments to global symbols. */ | |
11166 | if (S_IS_EXTERN (fixp->fx_addsy) || S_IS_WEAK (fixp->fx_addsy)) | |
11167 | return 0; | |
11168 | #endif | |
252b5132 RH |
11169 | if (fixp->fx_r_type == BFD_RELOC_MIPS16_JMP) |
11170 | return 0; | |
11171 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT | |
11172 | || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
11173 | return 0; | |
11174 | if (fixp->fx_addsy == NULL) | |
11175 | return 1; | |
11176 | #ifdef OBJ_ELF | |
11177 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour | |
11178 | && S_GET_OTHER (fixp->fx_addsy) == STO_MIPS16 | |
11179 | && fixp->fx_subsy == NULL) | |
11180 | return 0; | |
11181 | #endif | |
11182 | return 1; | |
11183 | } | |
11184 | ||
11185 | /* Translate internal representation of relocation info to BFD target | |
11186 | format. */ | |
11187 | ||
11188 | arelent ** | |
11189 | tc_gen_reloc (section, fixp) | |
43841e91 | 11190 | asection *section ATTRIBUTE_UNUSED; |
252b5132 RH |
11191 | fixS *fixp; |
11192 | { | |
11193 | static arelent *retval[4]; | |
11194 | arelent *reloc; | |
11195 | bfd_reloc_code_real_type code; | |
11196 | ||
11197 | reloc = retval[0] = (arelent *) xmalloc (sizeof (arelent)); | |
11198 | retval[1] = NULL; | |
11199 | ||
49309057 ILT |
11200 | reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); |
11201 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
252b5132 RH |
11202 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; |
11203 | ||
11204 | if (mips_pic == EMBEDDED_PIC | |
11205 | && SWITCH_TABLE (fixp)) | |
11206 | { | |
11207 | /* For a switch table entry we use a special reloc. The addend | |
11208 | is actually the difference between the reloc address and the | |
11209 | subtrahend. */ | |
11210 | reloc->addend = reloc->address - S_GET_VALUE (fixp->fx_subsy); | |
11211 | if (OUTPUT_FLAVOR != bfd_target_ecoff_flavour) | |
11212 | as_fatal (_("Double check fx_r_type in tc-mips.c:tc_gen_reloc")); | |
11213 | fixp->fx_r_type = BFD_RELOC_GPREL32; | |
11214 | } | |
bb2d6cd7 GK |
11215 | else if (fixp->fx_pcrel == 0 || OUTPUT_FLAVOR == bfd_target_elf_flavour) |
11216 | reloc->addend = fixp->fx_addnumber; | |
252b5132 RH |
11217 | else if (fixp->fx_r_type == BFD_RELOC_PCREL_LO16) |
11218 | { | |
11219 | /* We use a special addend for an internal RELLO reloc. */ | |
49309057 | 11220 | if (symbol_section_p (fixp->fx_addsy)) |
252b5132 RH |
11221 | reloc->addend = reloc->address - S_GET_VALUE (fixp->fx_subsy); |
11222 | else | |
11223 | reloc->addend = fixp->fx_addnumber + reloc->address; | |
11224 | } | |
11225 | else if (fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S) | |
11226 | { | |
11227 | assert (fixp->fx_next != NULL | |
11228 | && fixp->fx_next->fx_r_type == BFD_RELOC_PCREL_LO16); | |
11229 | /* We use a special addend for an internal RELHI reloc. The | |
11230 | reloc is relative to the RELLO; adjust the addend | |
11231 | accordingly. */ | |
49309057 | 11232 | if (symbol_section_p (fixp->fx_addsy)) |
252b5132 RH |
11233 | reloc->addend = (fixp->fx_next->fx_frag->fr_address |
11234 | + fixp->fx_next->fx_where | |
11235 | - S_GET_VALUE (fixp->fx_subsy)); | |
11236 | else | |
11237 | reloc->addend = (fixp->fx_addnumber | |
11238 | + fixp->fx_next->fx_frag->fr_address | |
11239 | + fixp->fx_next->fx_where); | |
11240 | } | |
252b5132 RH |
11241 | else |
11242 | { | |
11243 | if (OUTPUT_FLAVOR != bfd_target_aout_flavour) | |
11244 | /* A gruesome hack which is a result of the gruesome gas reloc | |
11245 | handling. */ | |
11246 | reloc->addend = reloc->address; | |
11247 | else | |
11248 | reloc->addend = -reloc->address; | |
11249 | } | |
11250 | ||
11251 | /* If this is a variant frag, we may need to adjust the existing | |
11252 | reloc and generate a new one. */ | |
11253 | if (fixp->fx_frag->fr_opcode != NULL | |
11254 | && (fixp->fx_r_type == BFD_RELOC_MIPS_GPREL | |
11255 | || fixp->fx_r_type == BFD_RELOC_MIPS_GOT16 | |
11256 | || fixp->fx_r_type == BFD_RELOC_MIPS_CALL16 | |
11257 | || fixp->fx_r_type == BFD_RELOC_MIPS_GOT_HI16 | |
11258 | || fixp->fx_r_type == BFD_RELOC_MIPS_GOT_LO16 | |
11259 | || fixp->fx_r_type == BFD_RELOC_MIPS_CALL_HI16 | |
11260 | || fixp->fx_r_type == BFD_RELOC_MIPS_CALL_LO16)) | |
11261 | { | |
11262 | arelent *reloc2; | |
11263 | ||
11264 | assert (! RELAX_MIPS16_P (fixp->fx_frag->fr_subtype)); | |
11265 | ||
11266 | /* If this is not the last reloc in this frag, then we have two | |
11267 | GPREL relocs, or a GOT_HI16/GOT_LO16 pair, or a | |
11268 | CALL_HI16/CALL_LO16, both of which are being replaced. Let | |
11269 | the second one handle all of them. */ | |
11270 | if (fixp->fx_next != NULL | |
11271 | && fixp->fx_frag == fixp->fx_next->fx_frag) | |
11272 | { | |
11273 | assert ((fixp->fx_r_type == BFD_RELOC_MIPS_GPREL | |
11274 | && fixp->fx_next->fx_r_type == BFD_RELOC_MIPS_GPREL) | |
11275 | || (fixp->fx_r_type == BFD_RELOC_MIPS_GOT_HI16 | |
11276 | && (fixp->fx_next->fx_r_type | |
11277 | == BFD_RELOC_MIPS_GOT_LO16)) | |
11278 | || (fixp->fx_r_type == BFD_RELOC_MIPS_CALL_HI16 | |
11279 | && (fixp->fx_next->fx_r_type | |
11280 | == BFD_RELOC_MIPS_CALL_LO16))); | |
11281 | retval[0] = NULL; | |
11282 | return retval; | |
11283 | } | |
11284 | ||
11285 | fixp->fx_where = fixp->fx_frag->fr_opcode - fixp->fx_frag->fr_literal; | |
11286 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
11287 | reloc2 = retval[1] = (arelent *) xmalloc (sizeof (arelent)); | |
11288 | retval[2] = NULL; | |
49309057 ILT |
11289 | reloc2->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); |
11290 | *reloc2->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
252b5132 RH |
11291 | reloc2->address = (reloc->address |
11292 | + (RELAX_RELOC2 (fixp->fx_frag->fr_subtype) | |
11293 | - RELAX_RELOC1 (fixp->fx_frag->fr_subtype))); | |
11294 | reloc2->addend = fixp->fx_addnumber; | |
11295 | reloc2->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_LO16); | |
11296 | assert (reloc2->howto != NULL); | |
11297 | ||
11298 | if (RELAX_RELOC3 (fixp->fx_frag->fr_subtype)) | |
11299 | { | |
11300 | arelent *reloc3; | |
11301 | ||
11302 | reloc3 = retval[2] = (arelent *) xmalloc (sizeof (arelent)); | |
11303 | retval[3] = NULL; | |
11304 | *reloc3 = *reloc2; | |
11305 | reloc3->address += 4; | |
11306 | } | |
11307 | ||
11308 | if (mips_pic == NO_PIC) | |
11309 | { | |
11310 | assert (fixp->fx_r_type == BFD_RELOC_MIPS_GPREL); | |
11311 | fixp->fx_r_type = BFD_RELOC_HI16_S; | |
11312 | } | |
11313 | else if (mips_pic == SVR4_PIC) | |
11314 | { | |
11315 | switch (fixp->fx_r_type) | |
11316 | { | |
11317 | default: | |
11318 | abort (); | |
11319 | case BFD_RELOC_MIPS_GOT16: | |
11320 | break; | |
11321 | case BFD_RELOC_MIPS_CALL16: | |
11322 | case BFD_RELOC_MIPS_GOT_LO16: | |
11323 | case BFD_RELOC_MIPS_CALL_LO16: | |
11324 | fixp->fx_r_type = BFD_RELOC_MIPS_GOT16; | |
11325 | break; | |
11326 | } | |
11327 | } | |
11328 | else | |
11329 | abort (); | |
11330 | } | |
11331 | ||
11332 | /* Since MIPS ELF uses Rel instead of Rela, encode the vtable entry | |
11333 | to be used in the relocation's section offset. */ | |
11334 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
11335 | { | |
11336 | reloc->address = reloc->addend; | |
11337 | reloc->addend = 0; | |
11338 | } | |
11339 | ||
11340 | /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that | |
11341 | fixup_segment converted a non-PC relative reloc into a PC | |
11342 | relative reloc. In such a case, we need to convert the reloc | |
11343 | code. */ | |
11344 | code = fixp->fx_r_type; | |
11345 | if (fixp->fx_pcrel) | |
11346 | { | |
11347 | switch (code) | |
11348 | { | |
11349 | case BFD_RELOC_8: | |
11350 | code = BFD_RELOC_8_PCREL; | |
11351 | break; | |
11352 | case BFD_RELOC_16: | |
11353 | code = BFD_RELOC_16_PCREL; | |
11354 | break; | |
11355 | case BFD_RELOC_32: | |
11356 | code = BFD_RELOC_32_PCREL; | |
11357 | break; | |
11358 | case BFD_RELOC_64: | |
11359 | code = BFD_RELOC_64_PCREL; | |
11360 | break; | |
11361 | case BFD_RELOC_8_PCREL: | |
11362 | case BFD_RELOC_16_PCREL: | |
11363 | case BFD_RELOC_32_PCREL: | |
11364 | case BFD_RELOC_64_PCREL: | |
11365 | case BFD_RELOC_16_PCREL_S2: | |
11366 | case BFD_RELOC_PCREL_HI16_S: | |
11367 | case BFD_RELOC_PCREL_LO16: | |
11368 | break; | |
11369 | default: | |
11370 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
11371 | _("Cannot make %s relocation PC relative"), | |
11372 | bfd_get_reloc_code_name (code)); | |
11373 | } | |
11374 | } | |
11375 | ||
11376 | /* To support a PC relative reloc when generating embedded PIC code | |
11377 | for ECOFF, we use a Cygnus extension. We check for that here to | |
11378 | make sure that we don't let such a reloc escape normally. */ | |
bb2d6cd7 GK |
11379 | if ((OUTPUT_FLAVOR == bfd_target_ecoff_flavour |
11380 | || OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
252b5132 RH |
11381 | && code == BFD_RELOC_16_PCREL_S2 |
11382 | && mips_pic != EMBEDDED_PIC) | |
11383 | reloc->howto = NULL; | |
11384 | else | |
11385 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); | |
11386 | ||
11387 | if (reloc->howto == NULL) | |
11388 | { | |
11389 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
11390 | _("Can not represent %s relocation in this object file format"), | |
11391 | bfd_get_reloc_code_name (code)); | |
11392 | retval[0] = NULL; | |
11393 | } | |
11394 | ||
11395 | return retval; | |
11396 | } | |
11397 | ||
11398 | /* Relax a machine dependent frag. This returns the amount by which | |
11399 | the current size of the frag should change. */ | |
11400 | ||
11401 | int | |
11402 | mips_relax_frag (fragp, stretch) | |
11403 | fragS *fragp; | |
11404 | long stretch; | |
11405 | { | |
11406 | if (! RELAX_MIPS16_P (fragp->fr_subtype)) | |
11407 | return 0; | |
11408 | ||
11409 | if (mips16_extended_frag (fragp, (asection *) NULL, stretch)) | |
11410 | { | |
11411 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
11412 | return 0; | |
11413 | fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype); | |
11414 | return 2; | |
11415 | } | |
11416 | else | |
11417 | { | |
11418 | if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
11419 | return 0; | |
11420 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype); | |
11421 | return -2; | |
11422 | } | |
11423 | ||
11424 | return 0; | |
11425 | } | |
11426 | ||
11427 | /* Convert a machine dependent frag. */ | |
11428 | ||
11429 | void | |
11430 | md_convert_frag (abfd, asec, fragp) | |
43841e91 | 11431 | bfd *abfd ATTRIBUTE_UNUSED; |
252b5132 RH |
11432 | segT asec; |
11433 | fragS *fragp; | |
11434 | { | |
11435 | int old, new; | |
11436 | char *fixptr; | |
11437 | ||
11438 | if (RELAX_MIPS16_P (fragp->fr_subtype)) | |
11439 | { | |
11440 | int type; | |
11441 | register const struct mips16_immed_operand *op; | |
11442 | boolean small, ext; | |
11443 | offsetT val; | |
11444 | bfd_byte *buf; | |
11445 | unsigned long insn; | |
11446 | boolean use_extend; | |
11447 | unsigned short extend; | |
11448 | ||
11449 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
11450 | op = mips16_immed_operands; | |
11451 | while (op->type != type) | |
11452 | ++op; | |
11453 | ||
11454 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
11455 | { | |
11456 | small = false; | |
11457 | ext = true; | |
11458 | } | |
11459 | else | |
11460 | { | |
11461 | small = true; | |
11462 | ext = false; | |
11463 | } | |
11464 | ||
6386f3a7 | 11465 | resolve_symbol_value (fragp->fr_symbol); |
252b5132 RH |
11466 | val = S_GET_VALUE (fragp->fr_symbol); |
11467 | if (op->pcrel) | |
11468 | { | |
11469 | addressT addr; | |
11470 | ||
11471 | addr = fragp->fr_address + fragp->fr_fix; | |
11472 | ||
11473 | /* The rules for the base address of a PC relative reloc are | |
11474 | complicated; see mips16_extended_frag. */ | |
11475 | if (type == 'p' || type == 'q') | |
11476 | { | |
11477 | addr += 2; | |
11478 | if (ext) | |
11479 | addr += 2; | |
11480 | /* Ignore the low bit in the target, since it will be | |
11481 | set for a text label. */ | |
11482 | if ((val & 1) != 0) | |
11483 | --val; | |
11484 | } | |
11485 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) | |
11486 | addr -= 4; | |
11487 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
11488 | addr -= 2; | |
11489 | ||
11490 | addr &= ~ (addressT) ((1 << op->shift) - 1); | |
11491 | val -= addr; | |
11492 | ||
11493 | /* Make sure the section winds up with the alignment we have | |
11494 | assumed. */ | |
11495 | if (op->shift > 0) | |
11496 | record_alignment (asec, op->shift); | |
11497 | } | |
11498 | ||
11499 | if (ext | |
11500 | && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype) | |
11501 | || RELAX_MIPS16_DSLOT (fragp->fr_subtype))) | |
11502 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
11503 | _("extended instruction in delay slot")); | |
11504 | ||
11505 | buf = (bfd_byte *) (fragp->fr_literal + fragp->fr_fix); | |
11506 | ||
11507 | if (target_big_endian) | |
11508 | insn = bfd_getb16 (buf); | |
11509 | else | |
11510 | insn = bfd_getl16 (buf); | |
11511 | ||
11512 | mips16_immed (fragp->fr_file, fragp->fr_line, type, val, | |
11513 | RELAX_MIPS16_USER_EXT (fragp->fr_subtype), | |
11514 | small, ext, &insn, &use_extend, &extend); | |
11515 | ||
11516 | if (use_extend) | |
11517 | { | |
11518 | md_number_to_chars (buf, 0xf000 | extend, 2); | |
11519 | fragp->fr_fix += 2; | |
11520 | buf += 2; | |
11521 | } | |
11522 | ||
11523 | md_number_to_chars (buf, insn, 2); | |
11524 | fragp->fr_fix += 2; | |
11525 | buf += 2; | |
11526 | } | |
11527 | else | |
11528 | { | |
11529 | if (fragp->fr_opcode == NULL) | |
11530 | return; | |
11531 | ||
11532 | old = RELAX_OLD (fragp->fr_subtype); | |
11533 | new = RELAX_NEW (fragp->fr_subtype); | |
11534 | fixptr = fragp->fr_literal + fragp->fr_fix; | |
11535 | ||
11536 | if (new > 0) | |
11537 | memcpy (fixptr - old, fixptr, new); | |
11538 | ||
11539 | fragp->fr_fix += new - old; | |
11540 | } | |
11541 | } | |
11542 | ||
11543 | #ifdef OBJ_ELF | |
11544 | ||
11545 | /* This function is called after the relocs have been generated. | |
11546 | We've been storing mips16 text labels as odd. Here we convert them | |
11547 | back to even for the convenience of the debugger. */ | |
11548 | ||
11549 | void | |
11550 | mips_frob_file_after_relocs () | |
11551 | { | |
11552 | asymbol **syms; | |
11553 | unsigned int count, i; | |
11554 | ||
11555 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
11556 | return; | |
11557 | ||
11558 | syms = bfd_get_outsymbols (stdoutput); | |
11559 | count = bfd_get_symcount (stdoutput); | |
11560 | for (i = 0; i < count; i++, syms++) | |
11561 | { | |
11562 | if (elf_symbol (*syms)->internal_elf_sym.st_other == STO_MIPS16 | |
11563 | && ((*syms)->value & 1) != 0) | |
11564 | { | |
11565 | (*syms)->value &= ~1; | |
11566 | /* If the symbol has an odd size, it was probably computed | |
11567 | incorrectly, so adjust that as well. */ | |
11568 | if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0) | |
11569 | ++elf_symbol (*syms)->internal_elf_sym.st_size; | |
11570 | } | |
11571 | } | |
11572 | } | |
11573 | ||
11574 | #endif | |
11575 | ||
11576 | /* This function is called whenever a label is defined. It is used | |
11577 | when handling branch delays; if a branch has a label, we assume we | |
11578 | can not move it. */ | |
11579 | ||
11580 | void | |
11581 | mips_define_label (sym) | |
11582 | symbolS *sym; | |
11583 | { | |
11584 | struct insn_label_list *l; | |
11585 | ||
11586 | if (free_insn_labels == NULL) | |
11587 | l = (struct insn_label_list *) xmalloc (sizeof *l); | |
11588 | else | |
11589 | { | |
11590 | l = free_insn_labels; | |
11591 | free_insn_labels = l->next; | |
11592 | } | |
11593 | ||
11594 | l->label = sym; | |
11595 | l->next = insn_labels; | |
11596 | insn_labels = l; | |
11597 | } | |
11598 | \f | |
11599 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
11600 | ||
11601 | /* Some special processing for a MIPS ELF file. */ | |
11602 | ||
11603 | void | |
11604 | mips_elf_final_processing () | |
11605 | { | |
11606 | /* Write out the register information. */ | |
11607 | if (! mips_64) | |
11608 | { | |
11609 | Elf32_RegInfo s; | |
11610 | ||
11611 | s.ri_gprmask = mips_gprmask; | |
11612 | s.ri_cprmask[0] = mips_cprmask[0]; | |
11613 | s.ri_cprmask[1] = mips_cprmask[1]; | |
11614 | s.ri_cprmask[2] = mips_cprmask[2]; | |
11615 | s.ri_cprmask[3] = mips_cprmask[3]; | |
11616 | /* The gp_value field is set by the MIPS ELF backend. */ | |
11617 | ||
11618 | bfd_mips_elf32_swap_reginfo_out (stdoutput, &s, | |
11619 | ((Elf32_External_RegInfo *) | |
11620 | mips_regmask_frag)); | |
11621 | } | |
11622 | else | |
11623 | { | |
11624 | Elf64_Internal_RegInfo s; | |
11625 | ||
11626 | s.ri_gprmask = mips_gprmask; | |
11627 | s.ri_pad = 0; | |
11628 | s.ri_cprmask[0] = mips_cprmask[0]; | |
11629 | s.ri_cprmask[1] = mips_cprmask[1]; | |
11630 | s.ri_cprmask[2] = mips_cprmask[2]; | |
11631 | s.ri_cprmask[3] = mips_cprmask[3]; | |
11632 | /* The gp_value field is set by the MIPS ELF backend. */ | |
11633 | ||
11634 | bfd_mips_elf64_swap_reginfo_out (stdoutput, &s, | |
11635 | ((Elf64_External_RegInfo *) | |
11636 | mips_regmask_frag)); | |
11637 | } | |
11638 | ||
11639 | /* Set the MIPS ELF flag bits. FIXME: There should probably be some | |
11640 | sort of BFD interface for this. */ | |
11641 | if (mips_any_noreorder) | |
11642 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER; | |
11643 | if (mips_pic != NO_PIC) | |
11644 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC; | |
11645 | ||
bdaaa2e1 | 11646 | /* Set the MIPS ELF ABI flags. */ |
252b5132 RH |
11647 | if (mips_abi_string == 0) |
11648 | ; | |
beae10d5 | 11649 | else if (strcmp (mips_abi_string, "32") == 0) |
252b5132 | 11650 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32; |
beae10d5 | 11651 | else if (strcmp (mips_abi_string, "o64") == 0) |
252b5132 | 11652 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64; |
beae10d5 | 11653 | else if (strcmp (mips_abi_string, "eabi") == 0) |
252b5132 RH |
11654 | { |
11655 | if (mips_eabi64) | |
11656 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64; | |
11657 | else | |
11658 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32; | |
11659 | } | |
11660 | ||
11661 | if (mips_32bitmode) | |
11662 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE; | |
11663 | } | |
11664 | ||
11665 | #endif /* OBJ_ELF || OBJ_MAYBE_ELF */ | |
11666 | \f | |
beae10d5 KH |
11667 | typedef struct proc { |
11668 | symbolS *isym; | |
11669 | unsigned long reg_mask; | |
11670 | unsigned long reg_offset; | |
11671 | unsigned long fpreg_mask; | |
11672 | unsigned long fpreg_offset; | |
11673 | unsigned long frame_offset; | |
11674 | unsigned long frame_reg; | |
11675 | unsigned long pc_reg; | |
11676 | } procS; | |
252b5132 RH |
11677 | |
11678 | static procS cur_proc; | |
11679 | static procS *cur_proc_ptr; | |
11680 | static int numprocs; | |
11681 | ||
0a9ef439 | 11682 | /* Fill in an rs_align_code fragment. */ |
a19d8eb0 | 11683 | |
0a9ef439 RH |
11684 | void |
11685 | mips_handle_align (fragp) | |
11686 | fragS *fragp; | |
a19d8eb0 | 11687 | { |
0a9ef439 RH |
11688 | if (fragp->fr_type != rs_align_code) |
11689 | return; | |
11690 | ||
11691 | if (mips_opts.mips16) | |
a19d8eb0 CP |
11692 | { |
11693 | static const unsigned char be_nop[] = { 0x65, 0x00 }; | |
11694 | static const unsigned char le_nop[] = { 0x00, 0x65 }; | |
11695 | ||
0a9ef439 RH |
11696 | int bytes; |
11697 | char *p; | |
a19d8eb0 | 11698 | |
0a9ef439 RH |
11699 | bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix; |
11700 | p = fragp->fr_literal + fragp->fr_fix; | |
11701 | ||
11702 | if (bytes & 1) | |
11703 | { | |
11704 | *p++ = 0; | |
11705 | fragp->fr_fix += 1; | |
11706 | } | |
11707 | ||
11708 | memcpy (p, (target_big_endian ? be_nop : le_nop), 2); | |
11709 | fragp->fr_var = 2; | |
a19d8eb0 CP |
11710 | } |
11711 | ||
0a9ef439 | 11712 | /* For mips32, a nop is a zero, which we trivially get by doing nothing. */ |
a19d8eb0 CP |
11713 | } |
11714 | ||
252b5132 RH |
11715 | static void |
11716 | md_obj_begin () | |
11717 | { | |
11718 | } | |
11719 | ||
11720 | static void | |
11721 | md_obj_end () | |
11722 | { | |
11723 | /* check for premature end, nesting errors, etc */ | |
11724 | if (cur_proc_ptr) | |
11725 | as_warn (_("missing `.end' at end of assembly")); | |
11726 | } | |
11727 | ||
11728 | static long | |
11729 | get_number () | |
11730 | { | |
11731 | int negative = 0; | |
11732 | long val = 0; | |
11733 | ||
11734 | if (*input_line_pointer == '-') | |
11735 | { | |
11736 | ++input_line_pointer; | |
11737 | negative = 1; | |
11738 | } | |
d9a62219 | 11739 | if (!isdigit ((unsigned char) *input_line_pointer)) |
252b5132 RH |
11740 | as_bad (_("Expected simple number.")); |
11741 | if (input_line_pointer[0] == '0') | |
11742 | { | |
11743 | if (input_line_pointer[1] == 'x') | |
11744 | { | |
11745 | input_line_pointer += 2; | |
d9a62219 | 11746 | while (isxdigit ((unsigned char) *input_line_pointer)) |
252b5132 RH |
11747 | { |
11748 | val <<= 4; | |
11749 | val |= hex_value (*input_line_pointer++); | |
11750 | } | |
11751 | return negative ? -val : val; | |
11752 | } | |
11753 | else | |
11754 | { | |
11755 | ++input_line_pointer; | |
d9a62219 | 11756 | while (isdigit ((unsigned char) *input_line_pointer)) |
252b5132 RH |
11757 | { |
11758 | val <<= 3; | |
11759 | val |= *input_line_pointer++ - '0'; | |
11760 | } | |
11761 | return negative ? -val : val; | |
11762 | } | |
11763 | } | |
d9a62219 | 11764 | if (!isdigit ((unsigned char) *input_line_pointer)) |
252b5132 RH |
11765 | { |
11766 | printf (_(" *input_line_pointer == '%c' 0x%02x\n"), | |
11767 | *input_line_pointer, *input_line_pointer); | |
11768 | as_warn (_("Invalid number")); | |
11769 | return -1; | |
11770 | } | |
d9a62219 | 11771 | while (isdigit ((unsigned char) *input_line_pointer)) |
252b5132 RH |
11772 | { |
11773 | val *= 10; | |
11774 | val += *input_line_pointer++ - '0'; | |
11775 | } | |
11776 | return negative ? -val : val; | |
11777 | } | |
11778 | ||
11779 | /* The .file directive; just like the usual .file directive, but there | |
11780 | is an initial number which is the ECOFF file index. */ | |
11781 | ||
11782 | static void | |
11783 | s_file (x) | |
43841e91 | 11784 | int x ATTRIBUTE_UNUSED; |
252b5132 RH |
11785 | { |
11786 | int line; | |
11787 | ||
11788 | line = get_number (); | |
11789 | s_app_file (0); | |
11790 | } | |
11791 | ||
252b5132 RH |
11792 | /* The .end directive. */ |
11793 | ||
11794 | static void | |
11795 | s_mips_end (x) | |
43841e91 | 11796 | int x ATTRIBUTE_UNUSED; |
252b5132 RH |
11797 | { |
11798 | symbolS *p; | |
11799 | int maybe_text; | |
11800 | ||
11801 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
11802 | { | |
11803 | p = get_symbol (); | |
11804 | demand_empty_rest_of_line (); | |
11805 | } | |
11806 | else | |
11807 | p = NULL; | |
11808 | ||
11809 | #ifdef BFD_ASSEMBLER | |
11810 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0) | |
11811 | maybe_text = 1; | |
11812 | else | |
11813 | maybe_text = 0; | |
11814 | #else | |
11815 | if (now_seg != data_section && now_seg != bss_section) | |
11816 | maybe_text = 1; | |
11817 | else | |
11818 | maybe_text = 0; | |
11819 | #endif | |
11820 | ||
11821 | if (!maybe_text) | |
11822 | as_warn (_(".end not in text section")); | |
11823 | ||
11824 | if (!cur_proc_ptr) | |
11825 | { | |
11826 | as_warn (_(".end directive without a preceding .ent directive.")); | |
11827 | demand_empty_rest_of_line (); | |
11828 | return; | |
11829 | } | |
11830 | ||
11831 | if (p != NULL) | |
11832 | { | |
11833 | assert (S_GET_NAME (p)); | |
11834 | if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->isym))) | |
11835 | as_warn (_(".end symbol does not match .ent symbol.")); | |
11836 | } | |
11837 | else | |
11838 | as_warn (_(".end directive missing or unknown symbol")); | |
11839 | ||
11840 | #ifdef MIPS_STABS_ELF | |
11841 | { | |
11842 | segT saved_seg = now_seg; | |
11843 | subsegT saved_subseg = now_subseg; | |
252b5132 | 11844 | valueT dot; |
252b5132 RH |
11845 | expressionS exp; |
11846 | char *fragp; | |
11847 | ||
11848 | dot = frag_now_fix (); | |
11849 | ||
11850 | #ifdef md_flush_pending_output | |
11851 | md_flush_pending_output (); | |
11852 | #endif | |
11853 | ||
11854 | assert (pdr_seg); | |
11855 | subseg_set (pdr_seg, 0); | |
11856 | ||
beae10d5 | 11857 | /* Write the symbol. */ |
252b5132 RH |
11858 | exp.X_op = O_symbol; |
11859 | exp.X_add_symbol = p; | |
11860 | exp.X_add_number = 0; | |
11861 | emit_expr (&exp, 4); | |
11862 | ||
beae10d5 | 11863 | fragp = frag_more (7 * 4); |
252b5132 | 11864 | |
beae10d5 KH |
11865 | md_number_to_chars (fragp, (valueT) cur_proc_ptr->reg_mask, 4); |
11866 | md_number_to_chars (fragp + 4, (valueT) cur_proc_ptr->reg_offset, 4); | |
11867 | md_number_to_chars (fragp + 8, (valueT) cur_proc_ptr->fpreg_mask, 4); | |
11868 | md_number_to_chars (fragp + 12, (valueT) cur_proc_ptr->fpreg_offset, 4); | |
11869 | md_number_to_chars (fragp + 16, (valueT) cur_proc_ptr->frame_offset, 4); | |
11870 | md_number_to_chars (fragp + 20, (valueT) cur_proc_ptr->frame_reg, 4); | |
11871 | md_number_to_chars (fragp + 24, (valueT) cur_proc_ptr->pc_reg, 4); | |
252b5132 RH |
11872 | |
11873 | subseg_set (saved_seg, saved_subseg); | |
11874 | } | |
11875 | #endif | |
11876 | ||
11877 | cur_proc_ptr = NULL; | |
11878 | } | |
11879 | ||
11880 | /* The .aent and .ent directives. */ | |
11881 | ||
11882 | static void | |
11883 | s_mips_ent (aent) | |
11884 | int aent; | |
11885 | { | |
11886 | int number = 0; | |
11887 | symbolS *symbolP; | |
11888 | int maybe_text; | |
11889 | ||
11890 | symbolP = get_symbol (); | |
11891 | if (*input_line_pointer == ',') | |
11892 | input_line_pointer++; | |
11893 | SKIP_WHITESPACE (); | |
d9a62219 DE |
11894 | if (isdigit ((unsigned char) *input_line_pointer) |
11895 | || *input_line_pointer == '-') | |
252b5132 RH |
11896 | number = get_number (); |
11897 | ||
11898 | #ifdef BFD_ASSEMBLER | |
11899 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0) | |
11900 | maybe_text = 1; | |
11901 | else | |
11902 | maybe_text = 0; | |
11903 | #else | |
11904 | if (now_seg != data_section && now_seg != bss_section) | |
11905 | maybe_text = 1; | |
11906 | else | |
11907 | maybe_text = 0; | |
11908 | #endif | |
11909 | ||
11910 | if (!maybe_text) | |
11911 | as_warn (_(".ent or .aent not in text section.")); | |
11912 | ||
11913 | if (!aent && cur_proc_ptr) | |
11914 | as_warn (_("missing `.end'")); | |
11915 | ||
11916 | if (!aent) | |
11917 | { | |
11918 | cur_proc_ptr = &cur_proc; | |
11919 | memset (cur_proc_ptr, '\0', sizeof (procS)); | |
11920 | ||
11921 | cur_proc_ptr->isym = symbolP; | |
11922 | ||
49309057 | 11923 | symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION; |
252b5132 RH |
11924 | |
11925 | numprocs++; | |
11926 | } | |
11927 | ||
11928 | demand_empty_rest_of_line (); | |
11929 | } | |
11930 | ||
11931 | /* The .frame directive. If the mdebug section is present (IRIX 5 native) | |
bdaaa2e1 | 11932 | then ecoff.c (ecoff_directive_frame) is used. For embedded targets, |
252b5132 | 11933 | s_mips_frame is used so that we can set the PDR information correctly. |
bdaaa2e1 | 11934 | We can't use the ecoff routines because they make reference to the ecoff |
252b5132 RH |
11935 | symbol table (in the mdebug section). */ |
11936 | ||
11937 | static void | |
11938 | s_mips_frame (ignore) | |
2b3c5a5d | 11939 | int ignore ATTRIBUTE_UNUSED; |
252b5132 RH |
11940 | { |
11941 | #ifdef MIPS_STABS_ELF | |
11942 | ||
11943 | long val; | |
11944 | ||
beae10d5 | 11945 | if (cur_proc_ptr == (procS *) NULL) |
252b5132 RH |
11946 | { |
11947 | as_warn (_(".frame outside of .ent")); | |
11948 | demand_empty_rest_of_line (); | |
11949 | return; | |
11950 | } | |
11951 | ||
11952 | cur_proc_ptr->frame_reg = tc_get_register (1); | |
11953 | ||
11954 | SKIP_WHITESPACE (); | |
11955 | if (*input_line_pointer++ != ',' | |
11956 | || get_absolute_expression_and_terminator (&val) != ',') | |
11957 | { | |
11958 | as_warn (_("Bad .frame directive")); | |
11959 | --input_line_pointer; | |
11960 | demand_empty_rest_of_line (); | |
11961 | return; | |
11962 | } | |
11963 | ||
11964 | cur_proc_ptr->frame_offset = val; | |
11965 | cur_proc_ptr->pc_reg = tc_get_register (0); | |
11966 | ||
11967 | demand_empty_rest_of_line (); | |
11968 | #else | |
11969 | s_ignore (ignore); | |
11970 | #endif /* MIPS_STABS_ELF */ | |
11971 | } | |
11972 | ||
bdaaa2e1 KH |
11973 | /* The .fmask and .mask directives. If the mdebug section is present |
11974 | (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For | |
252b5132 | 11975 | embedded targets, s_mips_mask is used so that we can set the PDR |
bdaaa2e1 | 11976 | information correctly. We can't use the ecoff routines because they |
252b5132 RH |
11977 | make reference to the ecoff symbol table (in the mdebug section). */ |
11978 | ||
11979 | static void | |
11980 | s_mips_mask (reg_type) | |
11981 | char reg_type; | |
11982 | { | |
11983 | #ifdef MIPS_STABS_ELF | |
11984 | long mask, off; | |
bdaaa2e1 | 11985 | |
252b5132 RH |
11986 | if (cur_proc_ptr == (procS *) NULL) |
11987 | { | |
11988 | as_warn (_(".mask/.fmask outside of .ent")); | |
11989 | demand_empty_rest_of_line (); | |
11990 | return; | |
11991 | } | |
11992 | ||
11993 | if (get_absolute_expression_and_terminator (&mask) != ',') | |
11994 | { | |
11995 | as_warn (_("Bad .mask/.fmask directive")); | |
11996 | --input_line_pointer; | |
11997 | demand_empty_rest_of_line (); | |
11998 | return; | |
11999 | } | |
12000 | ||
12001 | off = get_absolute_expression (); | |
12002 | ||
12003 | if (reg_type == 'F') | |
12004 | { | |
12005 | cur_proc_ptr->fpreg_mask = mask; | |
12006 | cur_proc_ptr->fpreg_offset = off; | |
12007 | } | |
12008 | else | |
12009 | { | |
12010 | cur_proc_ptr->reg_mask = mask; | |
12011 | cur_proc_ptr->reg_offset = off; | |
12012 | } | |
12013 | ||
12014 | demand_empty_rest_of_line (); | |
12015 | #else | |
12016 | s_ignore (reg_type); | |
12017 | #endif /* MIPS_STABS_ELF */ | |
12018 | } | |
12019 | ||
12020 | /* The .loc directive. */ | |
12021 | ||
12022 | #if 0 | |
12023 | static void | |
12024 | s_loc (x) | |
12025 | int x; | |
12026 | { | |
12027 | symbolS *symbolP; | |
12028 | int lineno; | |
12029 | int addroff; | |
12030 | ||
12031 | assert (now_seg == text_section); | |
12032 | ||
12033 | lineno = get_number (); | |
12034 | addroff = frag_now_fix (); | |
12035 | ||
12036 | symbolP = symbol_new ("", N_SLINE, addroff, frag_now); | |
12037 | S_SET_TYPE (symbolP, N_SLINE); | |
12038 | S_SET_OTHER (symbolP, 0); | |
12039 | S_SET_DESC (symbolP, lineno); | |
12040 | symbolP->sy_segment = now_seg; | |
12041 | } | |
12042 | #endif | |
e7af610e NC |
12043 | |
12044 | /* CPU name/ISA/number mapping table. | |
12045 | ||
12046 | Entries are grouped by type. The first matching CPU or ISA entry | |
12047 | gets chosen by CPU or ISA, so it should be the 'canonical' name | |
12048 | for that type. Entries after that within the type are sorted | |
12049 | alphabetically. | |
12050 | ||
12051 | Case is ignored in comparison, so put the canonical entry in the | |
12052 | appropriate case but everything else in lower case to ease eye pain. */ | |
e972090a NC |
12053 | static const struct mips_cpu_info mips_cpu_info_table[] = |
12054 | { | |
e7af610e NC |
12055 | /* MIPS1 ISA */ |
12056 | { "MIPS1", 1, ISA_MIPS1, CPU_R3000, }, | |
12057 | { "mips", 1, ISA_MIPS1, CPU_R3000, }, | |
12058 | ||
12059 | /* MIPS2 ISA */ | |
12060 | { "MIPS2", 1, ISA_MIPS2, CPU_R6000, }, | |
12061 | ||
12062 | /* MIPS3 ISA */ | |
12063 | { "MIPS3", 1, ISA_MIPS3, CPU_R4000, }, | |
12064 | ||
12065 | /* MIPS4 ISA */ | |
12066 | { "MIPS4", 1, ISA_MIPS4, CPU_R8000, }, | |
12067 | ||
84ea6cf2 NC |
12068 | /* MIPS5 ISA */ |
12069 | { "MIPS5", 1, ISA_MIPS5, CPU_MIPS5, }, | |
12070 | { "Generic-MIPS5", 0, ISA_MIPS5, CPU_MIPS5, }, | |
12071 | ||
e7af610e NC |
12072 | /* MIPS32 ISA */ |
12073 | { "MIPS32", 1, ISA_MIPS32, CPU_MIPS32, }, | |
12074 | { "Generic-MIPS32", 0, ISA_MIPS32, CPU_MIPS32, }, | |
12075 | ||
84ea6cf2 | 12076 | #if 1 |
e7af610e NC |
12077 | /* XXX for now, MIPS64 -> MIPS3 because of history */ |
12078 | { "MIPS64", 1, ISA_MIPS3, CPU_R4000 }, /* XXX! */ | |
84ea6cf2 NC |
12079 | #else |
12080 | /* MIPS64 ISA */ | |
12081 | { "MIPS64", 1, ISA_MIPS64, CPU_MIPS64 }, | |
12082 | #endif | |
12083 | { "mips64isa", 1, ISA_MIPS64, CPU_MIPS64 }, | |
12084 | { "Generic-MIPS64", 0, ISA_MIPS64, CPU_MIPS64, }, | |
e7af610e NC |
12085 | |
12086 | /* R2000 CPU */ | |
12087 | { "R2000", 0, ISA_MIPS1, CPU_R2000, }, | |
12088 | { "2000", 0, ISA_MIPS1, CPU_R2000, }, | |
12089 | { "2k", 0, ISA_MIPS1, CPU_R2000, }, | |
12090 | { "r2k", 0, ISA_MIPS1, CPU_R2000, }, | |
12091 | ||
12092 | /* R3000 CPU */ | |
12093 | { "R3000", 0, ISA_MIPS1, CPU_R3000, }, | |
12094 | { "3000", 0, ISA_MIPS1, CPU_R3000, }, | |
12095 | { "3k", 0, ISA_MIPS1, CPU_R3000, }, | |
12096 | { "r3k", 0, ISA_MIPS1, CPU_R3000, }, | |
12097 | ||
12098 | /* TX3900 CPU */ | |
12099 | { "R3900", 0, ISA_MIPS1, CPU_R3900, }, | |
12100 | { "3900", 0, ISA_MIPS1, CPU_R3900, }, | |
e972090a | 12101 | { "mipstx39", 0, ISA_MIPS1, CPU_R3900, }, |
e7af610e NC |
12102 | |
12103 | /* R4000 CPU */ | |
12104 | { "R4000", 0, ISA_MIPS3, CPU_R4000, }, | |
12105 | { "4000", 0, ISA_MIPS3, CPU_R4000, }, | |
12106 | { "4k", 0, ISA_MIPS3, CPU_R4000, }, /* beware */ | |
12107 | { "r4k", 0, ISA_MIPS3, CPU_R4000, }, | |
12108 | ||
12109 | /* R4010 CPU */ | |
12110 | { "R4010", 0, ISA_MIPS2, CPU_R4010, }, | |
12111 | { "4010", 0, ISA_MIPS2, CPU_R4010, }, | |
12112 | ||
12113 | /* R4400 CPU */ | |
12114 | { "R4400", 0, ISA_MIPS3, CPU_R4400, }, | |
12115 | { "4400", 0, ISA_MIPS3, CPU_R4400, }, | |
12116 | ||
12117 | /* R4600 CPU */ | |
12118 | { "R4600", 0, ISA_MIPS3, CPU_R4600, }, | |
12119 | { "4600", 0, ISA_MIPS3, CPU_R4600, }, | |
12120 | { "mips64orion", 0, ISA_MIPS3, CPU_R4600, }, | |
12121 | { "orion", 0, ISA_MIPS3, CPU_R4600, }, | |
12122 | ||
12123 | /* R4650 CPU */ | |
12124 | { "R4650", 0, ISA_MIPS3, CPU_R4650, }, | |
12125 | { "4650", 0, ISA_MIPS3, CPU_R4650, }, | |
12126 | ||
12127 | /* R6000 CPU */ | |
12128 | { "R6000", 0, ISA_MIPS2, CPU_R6000, }, | |
12129 | { "6000", 0, ISA_MIPS2, CPU_R6000, }, | |
12130 | { "6k", 0, ISA_MIPS2, CPU_R6000, }, | |
12131 | { "r6k", 0, ISA_MIPS2, CPU_R6000, }, | |
12132 | ||
12133 | /* R8000 CPU */ | |
12134 | { "R8000", 0, ISA_MIPS4, CPU_R8000, }, | |
12135 | { "8000", 0, ISA_MIPS4, CPU_R8000, }, | |
12136 | { "8k", 0, ISA_MIPS4, CPU_R8000, }, | |
12137 | { "r8k", 0, ISA_MIPS4, CPU_R8000, }, | |
12138 | ||
12139 | /* R10000 CPU */ | |
12140 | { "R10000", 0, ISA_MIPS4, CPU_R10000, }, | |
12141 | { "10000", 0, ISA_MIPS4, CPU_R10000, }, | |
12142 | { "10k", 0, ISA_MIPS4, CPU_R10000, }, | |
12143 | { "r10k", 0, ISA_MIPS4, CPU_R10000, }, | |
12144 | ||
d1cf510e NC |
12145 | /* R12000 CPU */ |
12146 | { "R12000", 0, ISA_MIPS4, CPU_R12000, }, | |
12147 | { "12000", 0, ISA_MIPS4, CPU_R12000, }, | |
12148 | { "12k", 0, ISA_MIPS4, CPU_R12000, }, | |
12149 | { "r12k", 0, ISA_MIPS4, CPU_R12000, }, | |
12150 | ||
e7af610e NC |
12151 | /* VR4100 CPU */ |
12152 | { "VR4100", 0, ISA_MIPS3, CPU_VR4100, }, | |
12153 | { "4100", 0, ISA_MIPS3, CPU_VR4100, }, | |
12154 | { "mips64vr4100", 0, ISA_MIPS3, CPU_VR4100, }, | |
12155 | { "r4100", 0, ISA_MIPS3, CPU_VR4100, }, | |
12156 | ||
12157 | /* VR4111 CPU */ | |
12158 | { "VR4111", 0, ISA_MIPS3, CPU_R4111, }, | |
12159 | { "4111", 0, ISA_MIPS3, CPU_R4111, }, | |
12160 | { "mips64vr4111", 0, ISA_MIPS3, CPU_R4111, }, | |
12161 | { "r4111", 0, ISA_MIPS3, CPU_R4111, }, | |
12162 | ||
12163 | /* VR4300 CPU */ | |
12164 | { "VR4300", 0, ISA_MIPS3, CPU_R4300, }, | |
12165 | { "4300", 0, ISA_MIPS3, CPU_R4300, }, | |
12166 | { "mips64vr4300", 0, ISA_MIPS3, CPU_R4300, }, | |
12167 | { "r4300", 0, ISA_MIPS3, CPU_R4300, }, | |
12168 | ||
12169 | /* VR5000 CPU */ | |
12170 | { "VR5000", 0, ISA_MIPS4, CPU_R5000, }, | |
12171 | { "5000", 0, ISA_MIPS4, CPU_R5000, }, | |
12172 | { "5k", 0, ISA_MIPS4, CPU_R5000, }, | |
12173 | { "mips64vr5000", 0, ISA_MIPS4, CPU_R5000, }, | |
12174 | { "r5000", 0, ISA_MIPS4, CPU_R5000, }, | |
12175 | { "r5200", 0, ISA_MIPS4, CPU_R5000, }, | |
18ae5d72 | 12176 | { "rm5200", 0, ISA_MIPS4, CPU_R5000, }, |
e7af610e | 12177 | { "r5230", 0, ISA_MIPS4, CPU_R5000, }, |
18ae5d72 | 12178 | { "rm5230", 0, ISA_MIPS4, CPU_R5000, }, |
e7af610e | 12179 | { "r5231", 0, ISA_MIPS4, CPU_R5000, }, |
18ae5d72 | 12180 | { "rm5231", 0, ISA_MIPS4, CPU_R5000, }, |
e7af610e | 12181 | { "r5261", 0, ISA_MIPS4, CPU_R5000, }, |
18ae5d72 | 12182 | { "rm5261", 0, ISA_MIPS4, CPU_R5000, }, |
e7af610e | 12183 | { "r5721", 0, ISA_MIPS4, CPU_R5000, }, |
18ae5d72 | 12184 | { "rm5721", 0, ISA_MIPS4, CPU_R5000, }, |
e7af610e NC |
12185 | { "r5k", 0, ISA_MIPS4, CPU_R5000, }, |
12186 | { "r7000", 0, ISA_MIPS4, CPU_R5000, }, | |
12187 | ||
12188 | /* MIPS32 4K CPU */ | |
12189 | { "MIPS32-4K", 0, ISA_MIPS32, CPU_MIPS32_4K, }, | |
12190 | { "4kc", 0, ISA_MIPS32, CPU_MIPS32_4K, }, | |
12191 | { "4km", 0, ISA_MIPS32, CPU_MIPS32_4K, }, | |
12192 | { "4kp", 0, ISA_MIPS32, CPU_MIPS32_4K, }, | |
12193 | { "mips32-4kc", 0, ISA_MIPS32, CPU_MIPS32_4K, }, | |
12194 | { "mips32-4km", 0, ISA_MIPS32, CPU_MIPS32_4K, }, | |
12195 | { "mips32-4kp", 0, ISA_MIPS32, CPU_MIPS32_4K, }, | |
12196 | ||
c6c98b38 NC |
12197 | /* SiByte SB-1 CPU */ |
12198 | { "SB-1", 0, ISA_MIPS64, CPU_SB1, }, | |
e972090a | 12199 | { "sb-1250", 0, ISA_MIPS64, CPU_SB1, }, |
c6c98b38 NC |
12200 | { "sb1", 0, ISA_MIPS64, CPU_SB1, }, |
12201 | { "sb1250", 0, ISA_MIPS64, CPU_SB1, }, | |
12202 | ||
beae10d5 | 12203 | /* End marker. */ |
e7af610e NC |
12204 | { NULL, 0, 0, 0, }, |
12205 | }; | |
12206 | ||
12207 | static const struct mips_cpu_info * | |
12208 | mips_cpu_info_from_name (name) | |
12209 | const char *name; | |
12210 | { | |
12211 | int i; | |
12212 | ||
12213 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
beae10d5 | 12214 | if (strcasecmp (name, mips_cpu_info_table[i].name) == 0) |
e7af610e NC |
12215 | return (&mips_cpu_info_table[i]); |
12216 | ||
e972090a | 12217 | return NULL; |
e7af610e NC |
12218 | } |
12219 | ||
12220 | static const struct mips_cpu_info * | |
12221 | mips_cpu_info_from_isa (isa) | |
12222 | int isa; | |
12223 | { | |
12224 | int i; | |
12225 | ||
12226 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
12227 | if (mips_cpu_info_table[i].is_isa | |
12228 | && isa == mips_cpu_info_table[i].isa) | |
12229 | return (&mips_cpu_info_table[i]); | |
12230 | ||
e972090a | 12231 | return NULL; |
e7af610e NC |
12232 | } |
12233 | ||
12234 | static const struct mips_cpu_info * | |
12235 | mips_cpu_info_from_cpu (cpu) | |
12236 | int cpu; | |
12237 | { | |
12238 | int i; | |
12239 | ||
12240 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
12241 | if (!mips_cpu_info_table[i].is_isa | |
12242 | && cpu == mips_cpu_info_table[i].cpu) | |
12243 | return (&mips_cpu_info_table[i]); | |
12244 | ||
e972090a | 12245 | return NULL; |
e7af610e | 12246 | } |