Commit | Line | Data |
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252b5132 | 1 | /* tc-mips.c -- assemble code for a MIPS chip. |
81912461 ILT |
2 | Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, |
3 | 2003, 2004 Free Software Foundation, Inc. | |
252b5132 RH |
4 | Contributed by the OSF and Ralph Campbell. |
5 | Written by Keith Knowles and Ralph Campbell, working independently. | |
6 | Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus | |
7 | Support. | |
8 | ||
9 | This file is part of GAS. | |
10 | ||
11 | GAS is free software; you can redistribute it and/or modify | |
12 | it under the terms of the GNU General Public License as published by | |
13 | the Free Software Foundation; either version 2, or (at your option) | |
14 | any later version. | |
15 | ||
16 | GAS is distributed in the hope that it will be useful, | |
17 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | GNU General Public License for more details. | |
20 | ||
21 | You should have received a copy of the GNU General Public License | |
22 | along with GAS; see the file COPYING. If not, write to the Free | |
23 | Software Foundation, 59 Temple Place - Suite 330, Boston, MA | |
24 | 02111-1307, USA. */ | |
25 | ||
26 | #include "as.h" | |
27 | #include "config.h" | |
28 | #include "subsegs.h" | |
3882b010 | 29 | #include "safe-ctype.h" |
252b5132 | 30 | |
252b5132 | 31 | #include <stdarg.h> |
252b5132 RH |
32 | |
33 | #include "opcode/mips.h" | |
34 | #include "itbl-ops.h" | |
c5dd6aab | 35 | #include "dwarf2dbg.h" |
252b5132 RH |
36 | |
37 | #ifdef DEBUG | |
38 | #define DBG(x) printf x | |
39 | #else | |
40 | #define DBG(x) | |
41 | #endif | |
42 | ||
43 | #ifdef OBJ_MAYBE_ELF | |
44 | /* Clean up namespace so we can include obj-elf.h too. */ | |
17a2f251 TS |
45 | static int mips_output_flavor (void); |
46 | static int mips_output_flavor (void) { return OUTPUT_FLAVOR; } | |
252b5132 RH |
47 | #undef OBJ_PROCESS_STAB |
48 | #undef OUTPUT_FLAVOR | |
49 | #undef S_GET_ALIGN | |
50 | #undef S_GET_SIZE | |
51 | #undef S_SET_ALIGN | |
52 | #undef S_SET_SIZE | |
252b5132 RH |
53 | #undef obj_frob_file |
54 | #undef obj_frob_file_after_relocs | |
55 | #undef obj_frob_symbol | |
56 | #undef obj_pop_insert | |
57 | #undef obj_sec_sym_ok_for_reloc | |
58 | #undef OBJ_COPY_SYMBOL_ATTRIBUTES | |
59 | ||
60 | #include "obj-elf.h" | |
61 | /* Fix any of them that we actually care about. */ | |
62 | #undef OUTPUT_FLAVOR | |
63 | #define OUTPUT_FLAVOR mips_output_flavor() | |
64 | #endif | |
65 | ||
66 | #if defined (OBJ_ELF) | |
67 | #include "elf/mips.h" | |
68 | #endif | |
69 | ||
70 | #ifndef ECOFF_DEBUGGING | |
71 | #define NO_ECOFF_DEBUGGING | |
72 | #define ECOFF_DEBUGGING 0 | |
73 | #endif | |
74 | ||
ecb4347a DJ |
75 | int mips_flag_mdebug = -1; |
76 | ||
dcd410fe RO |
77 | /* Control generation of .pdr sections. Off by default on IRIX: the native |
78 | linker doesn't know about and discards them, but relocations against them | |
79 | remain, leading to rld crashes. */ | |
80 | #ifdef TE_IRIX | |
81 | int mips_flag_pdr = FALSE; | |
82 | #else | |
83 | int mips_flag_pdr = TRUE; | |
84 | #endif | |
85 | ||
252b5132 RH |
86 | #include "ecoff.h" |
87 | ||
88 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
89 | static char *mips_regmask_frag; | |
90 | #endif | |
91 | ||
85b51719 | 92 | #define ZERO 0 |
252b5132 RH |
93 | #define AT 1 |
94 | #define TREG 24 | |
95 | #define PIC_CALL_REG 25 | |
96 | #define KT0 26 | |
97 | #define KT1 27 | |
98 | #define GP 28 | |
99 | #define SP 29 | |
100 | #define FP 30 | |
101 | #define RA 31 | |
102 | ||
103 | #define ILLEGAL_REG (32) | |
104 | ||
105 | /* Allow override of standard little-endian ECOFF format. */ | |
106 | ||
107 | #ifndef ECOFF_LITTLE_FORMAT | |
108 | #define ECOFF_LITTLE_FORMAT "ecoff-littlemips" | |
109 | #endif | |
110 | ||
111 | extern int target_big_endian; | |
112 | ||
252b5132 | 113 | /* The name of the readonly data section. */ |
4d0d148d | 114 | #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_ecoff_flavour \ |
252b5132 | 115 | ? ".rdata" \ |
056350c6 NC |
116 | : OUTPUT_FLAVOR == bfd_target_coff_flavour \ |
117 | ? ".rdata" \ | |
252b5132 RH |
118 | : OUTPUT_FLAVOR == bfd_target_elf_flavour \ |
119 | ? ".rodata" \ | |
120 | : (abort (), "")) | |
121 | ||
a325df1d TS |
122 | /* The ABI to use. */ |
123 | enum mips_abi_level | |
124 | { | |
125 | NO_ABI = 0, | |
126 | O32_ABI, | |
127 | O64_ABI, | |
128 | N32_ABI, | |
129 | N64_ABI, | |
130 | EABI_ABI | |
131 | }; | |
132 | ||
133 | /* MIPS ABI we are using for this output file. */ | |
316f5878 | 134 | static enum mips_abi_level mips_abi = NO_ABI; |
a325df1d | 135 | |
143d77c5 EC |
136 | /* Whether or not we have code that can call pic code. */ |
137 | int mips_abicalls = FALSE; | |
138 | ||
aa6975fb ILT |
139 | /* Whether or not we have code which can be put into a shared |
140 | library. */ | |
141 | static bfd_boolean mips_in_shared = TRUE; | |
142 | ||
252b5132 RH |
143 | /* This is the set of options which may be modified by the .set |
144 | pseudo-op. We use a struct so that .set push and .set pop are more | |
145 | reliable. */ | |
146 | ||
e972090a NC |
147 | struct mips_set_options |
148 | { | |
252b5132 RH |
149 | /* MIPS ISA (Instruction Set Architecture) level. This is set to -1 |
150 | if it has not been initialized. Changed by `.set mipsN', and the | |
151 | -mipsN command line option, and the default CPU. */ | |
152 | int isa; | |
1f25f5d3 CD |
153 | /* Enabled Application Specific Extensions (ASEs). These are set to -1 |
154 | if they have not been initialized. Changed by `.set <asename>', by | |
155 | command line options, and based on the default architecture. */ | |
156 | int ase_mips3d; | |
deec1734 | 157 | int ase_mdmx; |
252b5132 RH |
158 | /* Whether we are assembling for the mips16 processor. 0 if we are |
159 | not, 1 if we are, and -1 if the value has not been initialized. | |
160 | Changed by `.set mips16' and `.set nomips16', and the -mips16 and | |
161 | -nomips16 command line options, and the default CPU. */ | |
162 | int mips16; | |
163 | /* Non-zero if we should not reorder instructions. Changed by `.set | |
164 | reorder' and `.set noreorder'. */ | |
165 | int noreorder; | |
166 | /* Non-zero if we should not permit the $at ($1) register to be used | |
167 | in instructions. Changed by `.set at' and `.set noat'. */ | |
168 | int noat; | |
169 | /* Non-zero if we should warn when a macro instruction expands into | |
170 | more than one machine instruction. Changed by `.set nomacro' and | |
171 | `.set macro'. */ | |
172 | int warn_about_macros; | |
173 | /* Non-zero if we should not move instructions. Changed by `.set | |
174 | move', `.set volatile', `.set nomove', and `.set novolatile'. */ | |
175 | int nomove; | |
176 | /* Non-zero if we should not optimize branches by moving the target | |
177 | of the branch into the delay slot. Actually, we don't perform | |
178 | this optimization anyhow. Changed by `.set bopt' and `.set | |
179 | nobopt'. */ | |
180 | int nobopt; | |
181 | /* Non-zero if we should not autoextend mips16 instructions. | |
182 | Changed by `.set autoextend' and `.set noautoextend'. */ | |
183 | int noautoextend; | |
a325df1d TS |
184 | /* Restrict general purpose registers and floating point registers |
185 | to 32 bit. This is initially determined when -mgp32 or -mfp32 | |
186 | is passed but can changed if the assembler code uses .set mipsN. */ | |
187 | int gp32; | |
188 | int fp32; | |
fef14a42 TS |
189 | /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march |
190 | command line option, and the default CPU. */ | |
191 | int arch; | |
252b5132 RH |
192 | }; |
193 | ||
a325df1d | 194 | /* True if -mgp32 was passed. */ |
a8e8e863 | 195 | static int file_mips_gp32 = -1; |
a325df1d TS |
196 | |
197 | /* True if -mfp32 was passed. */ | |
a8e8e863 | 198 | static int file_mips_fp32 = -1; |
a325df1d | 199 | |
252b5132 | 200 | /* This is the struct we use to hold the current set of options. Note |
a4672219 | 201 | that we must set the isa field to ISA_UNKNOWN and the ASE fields to |
e7af610e | 202 | -1 to indicate that they have not been initialized. */ |
252b5132 | 203 | |
e972090a NC |
204 | static struct mips_set_options mips_opts = |
205 | { | |
fef14a42 | 206 | ISA_UNKNOWN, -1, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0, CPU_UNKNOWN |
e7af610e | 207 | }; |
252b5132 RH |
208 | |
209 | /* These variables are filled in with the masks of registers used. | |
210 | The object format code reads them and puts them in the appropriate | |
211 | place. */ | |
212 | unsigned long mips_gprmask; | |
213 | unsigned long mips_cprmask[4]; | |
214 | ||
215 | /* MIPS ISA we are using for this output file. */ | |
e7af610e | 216 | static int file_mips_isa = ISA_UNKNOWN; |
252b5132 | 217 | |
a4672219 TS |
218 | /* True if -mips16 was passed or implied by arguments passed on the |
219 | command line (e.g., by -march). */ | |
220 | static int file_ase_mips16; | |
221 | ||
1f25f5d3 CD |
222 | /* True if -mips3d was passed or implied by arguments passed on the |
223 | command line (e.g., by -march). */ | |
224 | static int file_ase_mips3d; | |
225 | ||
deec1734 CD |
226 | /* True if -mdmx was passed or implied by arguments passed on the |
227 | command line (e.g., by -march). */ | |
228 | static int file_ase_mdmx; | |
229 | ||
ec68c924 | 230 | /* The argument of the -march= flag. The architecture we are assembling. */ |
fef14a42 | 231 | static int file_mips_arch = CPU_UNKNOWN; |
316f5878 | 232 | static const char *mips_arch_string; |
ec68c924 EC |
233 | |
234 | /* The argument of the -mtune= flag. The architecture for which we | |
235 | are optimizing. */ | |
236 | static int mips_tune = CPU_UNKNOWN; | |
316f5878 | 237 | static const char *mips_tune_string; |
ec68c924 | 238 | |
316f5878 | 239 | /* True when generating 32-bit code for a 64-bit processor. */ |
252b5132 RH |
240 | static int mips_32bitmode = 0; |
241 | ||
316f5878 RS |
242 | /* True if the given ABI requires 32-bit registers. */ |
243 | #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI) | |
244 | ||
245 | /* Likewise 64-bit registers. */ | |
246 | #define ABI_NEEDS_64BIT_REGS(ABI) \ | |
247 | ((ABI) == N32_ABI \ | |
248 | || (ABI) == N64_ABI \ | |
249 | || (ABI) == O64_ABI) | |
250 | ||
bdaaa2e1 | 251 | /* Return true if ISA supports 64 bit gp register instructions. */ |
9ce8a5dd | 252 | #define ISA_HAS_64BIT_REGS(ISA) ( \ |
e7af610e NC |
253 | (ISA) == ISA_MIPS3 \ |
254 | || (ISA) == ISA_MIPS4 \ | |
84ea6cf2 | 255 | || (ISA) == ISA_MIPS5 \ |
d1cf510e | 256 | || (ISA) == ISA_MIPS64 \ |
5f74bc13 | 257 | || (ISA) == ISA_MIPS64R2 \ |
9ce8a5dd GRK |
258 | ) |
259 | ||
af7ee8bf CD |
260 | /* Return true if ISA supports 64-bit right rotate (dror et al.) |
261 | instructions. */ | |
262 | #define ISA_HAS_DROR(ISA) ( \ | |
5f74bc13 | 263 | (ISA) == ISA_MIPS64R2 \ |
af7ee8bf CD |
264 | ) |
265 | ||
266 | /* Return true if ISA supports 32-bit right rotate (ror et al.) | |
267 | instructions. */ | |
268 | #define ISA_HAS_ROR(ISA) ( \ | |
269 | (ISA) == ISA_MIPS32R2 \ | |
5f74bc13 | 270 | || (ISA) == ISA_MIPS64R2 \ |
af7ee8bf CD |
271 | ) |
272 | ||
e013f690 | 273 | #define HAVE_32BIT_GPRS \ |
316f5878 | 274 | (mips_opts.gp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
ca4e0257 | 275 | |
e013f690 | 276 | #define HAVE_32BIT_FPRS \ |
316f5878 | 277 | (mips_opts.fp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
ca4e0257 RS |
278 | |
279 | #define HAVE_64BIT_GPRS (! HAVE_32BIT_GPRS) | |
280 | #define HAVE_64BIT_FPRS (! HAVE_32BIT_FPRS) | |
281 | ||
316f5878 | 282 | #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI) |
e013f690 | 283 | |
316f5878 | 284 | #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI) |
e013f690 | 285 | |
3b91255e RS |
286 | /* True if relocations are stored in-place. */ |
287 | #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI) | |
288 | ||
3e722fb5 | 289 | /* We can only have 64bit addresses if the object file format supports it. */ |
afdbd6d0 CD |
290 | #define HAVE_32BIT_ADDRESSES \ |
291 | (HAVE_32BIT_GPRS \ | |
3e722fb5 CD |
292 | || (bfd_arch_bits_per_address (stdoutput) == 32 \ |
293 | || ! HAVE_64BIT_OBJECTS)) \ | |
e013f690 TS |
294 | |
295 | #define HAVE_64BIT_ADDRESSES (! HAVE_32BIT_ADDRESSES) | |
ca4e0257 | 296 | |
b7c7d6c1 TS |
297 | /* Addresses are loaded in different ways, depending on the address size |
298 | in use. The n32 ABI Documentation also mandates the use of additions | |
299 | with overflow checking, but existing implementations don't follow it. */ | |
f899b4b8 | 300 | #define ADDRESS_ADD_INSN \ |
b7c7d6c1 | 301 | (HAVE_32BIT_ADDRESSES ? "addu" : "daddu") |
f899b4b8 TS |
302 | |
303 | #define ADDRESS_ADDI_INSN \ | |
b7c7d6c1 | 304 | (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu") |
f899b4b8 TS |
305 | |
306 | #define ADDRESS_LOAD_INSN \ | |
307 | (HAVE_32BIT_ADDRESSES ? "lw" : "ld") | |
308 | ||
309 | #define ADDRESS_STORE_INSN \ | |
310 | (HAVE_32BIT_ADDRESSES ? "sw" : "sd") | |
311 | ||
a4672219 | 312 | /* Return true if the given CPU supports the MIPS16 ASE. */ |
3396de36 TS |
313 | #define CPU_HAS_MIPS16(cpu) \ |
314 | (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \ | |
315 | || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0) | |
a4672219 | 316 | |
1f25f5d3 CD |
317 | /* Return true if the given CPU supports the MIPS3D ASE. */ |
318 | #define CPU_HAS_MIPS3D(cpu) ((cpu) == CPU_SB1 \ | |
319 | ) | |
320 | ||
deec1734 | 321 | /* Return true if the given CPU supports the MDMX ASE. */ |
b34976b6 | 322 | #define CPU_HAS_MDMX(cpu) (FALSE \ |
deec1734 CD |
323 | ) |
324 | ||
60b63b72 RS |
325 | /* True if CPU has a dror instruction. */ |
326 | #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500) | |
327 | ||
328 | /* True if CPU has a ror instruction. */ | |
329 | #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU) | |
330 | ||
c8978940 CD |
331 | /* True if mflo and mfhi can be immediately followed by instructions |
332 | which write to the HI and LO registers. | |
333 | ||
334 | According to MIPS specifications, MIPS ISAs I, II, and III need | |
335 | (at least) two instructions between the reads of HI/LO and | |
336 | instructions which write them, and later ISAs do not. Contradicting | |
337 | the MIPS specifications, some MIPS IV processor user manuals (e.g. | |
338 | the UM for the NEC Vr5000) document needing the instructions between | |
339 | HI/LO reads and writes, as well. Therefore, we declare only MIPS32, | |
340 | MIPS64 and later ISAs to have the interlocks, plus any specific | |
341 | earlier-ISA CPUs for which CPU documentation declares that the | |
342 | instructions are really interlocked. */ | |
343 | #define hilo_interlocks \ | |
344 | (mips_opts.isa == ISA_MIPS32 \ | |
345 | || mips_opts.isa == ISA_MIPS32R2 \ | |
346 | || mips_opts.isa == ISA_MIPS64 \ | |
347 | || mips_opts.isa == ISA_MIPS64R2 \ | |
348 | || mips_opts.arch == CPU_R4010 \ | |
349 | || mips_opts.arch == CPU_R10000 \ | |
350 | || mips_opts.arch == CPU_R12000 \ | |
351 | || mips_opts.arch == CPU_RM7000 \ | |
c8978940 CD |
352 | || mips_opts.arch == CPU_VR5500 \ |
353 | ) | |
252b5132 RH |
354 | |
355 | /* Whether the processor uses hardware interlocks to protect reads | |
81912461 ILT |
356 | from the GPRs after they are loaded from memory, and thus does not |
357 | require nops to be inserted. This applies to instructions marked | |
358 | INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA | |
359 | level I. */ | |
252b5132 | 360 | #define gpr_interlocks \ |
e7af610e | 361 | (mips_opts.isa != ISA_MIPS1 \ |
fef14a42 | 362 | || mips_opts.arch == CPU_R3900) |
252b5132 | 363 | |
81912461 ILT |
364 | /* Whether the processor uses hardware interlocks to avoid delays |
365 | required by coprocessor instructions, and thus does not require | |
366 | nops to be inserted. This applies to instructions marked | |
367 | INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays | |
368 | between instructions marked INSN_WRITE_COND_CODE and ones marked | |
369 | INSN_READ_COND_CODE. These nops are only required at MIPS ISA | |
370 | levels I, II, and III. */ | |
bdaaa2e1 | 371 | /* Itbl support may require additional care here. */ |
81912461 ILT |
372 | #define cop_interlocks \ |
373 | ((mips_opts.isa != ISA_MIPS1 \ | |
374 | && mips_opts.isa != ISA_MIPS2 \ | |
375 | && mips_opts.isa != ISA_MIPS3) \ | |
376 | || mips_opts.arch == CPU_R4300 \ | |
81912461 ILT |
377 | ) |
378 | ||
379 | /* Whether the processor uses hardware interlocks to protect reads | |
380 | from coprocessor registers after they are loaded from memory, and | |
381 | thus does not require nops to be inserted. This applies to | |
382 | instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only | |
383 | requires at MIPS ISA level I. */ | |
384 | #define cop_mem_interlocks (mips_opts.isa != ISA_MIPS1) | |
252b5132 | 385 | |
6b76fefe CM |
386 | /* Is this a mfhi or mflo instruction? */ |
387 | #define MF_HILO_INSN(PINFO) \ | |
388 | ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO)) | |
389 | ||
252b5132 RH |
390 | /* MIPS PIC level. */ |
391 | ||
a161fe53 | 392 | enum mips_pic_level mips_pic; |
252b5132 | 393 | |
c9914766 | 394 | /* 1 if we should generate 32 bit offsets from the $gp register in |
252b5132 | 395 | SVR4_PIC mode. Currently has no meaning in other modes. */ |
c9914766 | 396 | static int mips_big_got = 0; |
252b5132 RH |
397 | |
398 | /* 1 if trap instructions should used for overflow rather than break | |
399 | instructions. */ | |
c9914766 | 400 | static int mips_trap = 0; |
252b5132 | 401 | |
119d663a | 402 | /* 1 if double width floating point constants should not be constructed |
b6ff326e | 403 | by assembling two single width halves into two single width floating |
119d663a NC |
404 | point registers which just happen to alias the double width destination |
405 | register. On some architectures this aliasing can be disabled by a bit | |
d547a75e | 406 | in the status register, and the setting of this bit cannot be determined |
119d663a NC |
407 | automatically at assemble time. */ |
408 | static int mips_disable_float_construction; | |
409 | ||
252b5132 RH |
410 | /* Non-zero if any .set noreorder directives were used. */ |
411 | ||
412 | static int mips_any_noreorder; | |
413 | ||
6b76fefe CM |
414 | /* Non-zero if nops should be inserted when the register referenced in |
415 | an mfhi/mflo instruction is read in the next two instructions. */ | |
416 | static int mips_7000_hilo_fix; | |
417 | ||
252b5132 | 418 | /* The size of the small data section. */ |
156c2f8b | 419 | static unsigned int g_switch_value = 8; |
252b5132 RH |
420 | /* Whether the -G option was used. */ |
421 | static int g_switch_seen = 0; | |
422 | ||
423 | #define N_RMASK 0xc4 | |
424 | #define N_VFP 0xd4 | |
425 | ||
426 | /* If we can determine in advance that GP optimization won't be | |
427 | possible, we can skip the relaxation stuff that tries to produce | |
428 | GP-relative references. This makes delay slot optimization work | |
429 | better. | |
430 | ||
431 | This function can only provide a guess, but it seems to work for | |
fba2b7f9 GK |
432 | gcc output. It needs to guess right for gcc, otherwise gcc |
433 | will put what it thinks is a GP-relative instruction in a branch | |
434 | delay slot. | |
252b5132 RH |
435 | |
436 | I don't know if a fix is needed for the SVR4_PIC mode. I've only | |
437 | fixed it for the non-PIC mode. KR 95/04/07 */ | |
17a2f251 | 438 | static int nopic_need_relax (symbolS *, int); |
252b5132 RH |
439 | |
440 | /* handle of the OPCODE hash table */ | |
441 | static struct hash_control *op_hash = NULL; | |
442 | ||
443 | /* The opcode hash table we use for the mips16. */ | |
444 | static struct hash_control *mips16_op_hash = NULL; | |
445 | ||
446 | /* This array holds the chars that always start a comment. If the | |
447 | pre-processor is disabled, these aren't very useful */ | |
448 | const char comment_chars[] = "#"; | |
449 | ||
450 | /* This array holds the chars that only start a comment at the beginning of | |
451 | a line. If the line seems to have the form '# 123 filename' | |
452 | .line and .file directives will appear in the pre-processed output */ | |
453 | /* Note that input_file.c hand checks for '#' at the beginning of the | |
454 | first line of the input file. This is because the compiler outputs | |
bdaaa2e1 | 455 | #NO_APP at the beginning of its output. */ |
252b5132 RH |
456 | /* Also note that C style comments are always supported. */ |
457 | const char line_comment_chars[] = "#"; | |
458 | ||
bdaaa2e1 | 459 | /* This array holds machine specific line separator characters. */ |
63a0b638 | 460 | const char line_separator_chars[] = ";"; |
252b5132 RH |
461 | |
462 | /* Chars that can be used to separate mant from exp in floating point nums */ | |
463 | const char EXP_CHARS[] = "eE"; | |
464 | ||
465 | /* Chars that mean this number is a floating point constant */ | |
466 | /* As in 0f12.456 */ | |
467 | /* or 0d1.2345e12 */ | |
468 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; | |
469 | ||
470 | /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be | |
471 | changed in read.c . Ideally it shouldn't have to know about it at all, | |
472 | but nothing is ideal around here. | |
473 | */ | |
474 | ||
475 | static char *insn_error; | |
476 | ||
477 | static int auto_align = 1; | |
478 | ||
479 | /* When outputting SVR4 PIC code, the assembler needs to know the | |
480 | offset in the stack frame from which to restore the $gp register. | |
481 | This is set by the .cprestore pseudo-op, and saved in this | |
482 | variable. */ | |
483 | static offsetT mips_cprestore_offset = -1; | |
484 | ||
67c1ffbe | 485 | /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some |
6478892d | 486 | more optimizations, it can use a register value instead of a memory-saved |
956cd1d6 | 487 | offset and even an other register than $gp as global pointer. */ |
6478892d TS |
488 | static offsetT mips_cpreturn_offset = -1; |
489 | static int mips_cpreturn_register = -1; | |
490 | static int mips_gp_register = GP; | |
def2e0dd | 491 | static int mips_gprel_offset = 0; |
6478892d | 492 | |
7a621144 DJ |
493 | /* Whether mips_cprestore_offset has been set in the current function |
494 | (or whether it has already been warned about, if not). */ | |
495 | static int mips_cprestore_valid = 0; | |
496 | ||
252b5132 RH |
497 | /* This is the register which holds the stack frame, as set by the |
498 | .frame pseudo-op. This is needed to implement .cprestore. */ | |
499 | static int mips_frame_reg = SP; | |
500 | ||
7a621144 DJ |
501 | /* Whether mips_frame_reg has been set in the current function |
502 | (or whether it has already been warned about, if not). */ | |
503 | static int mips_frame_reg_valid = 0; | |
504 | ||
252b5132 RH |
505 | /* To output NOP instructions correctly, we need to keep information |
506 | about the previous two instructions. */ | |
507 | ||
508 | /* Whether we are optimizing. The default value of 2 means to remove | |
509 | unneeded NOPs and swap branch instructions when possible. A value | |
510 | of 1 means to not swap branches. A value of 0 means to always | |
511 | insert NOPs. */ | |
512 | static int mips_optimize = 2; | |
513 | ||
514 | /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is | |
515 | equivalent to seeing no -g option at all. */ | |
516 | static int mips_debug = 0; | |
517 | ||
518 | /* The previous instruction. */ | |
519 | static struct mips_cl_insn prev_insn; | |
520 | ||
521 | /* The instruction before prev_insn. */ | |
522 | static struct mips_cl_insn prev_prev_insn; | |
523 | ||
524 | /* If we don't want information for prev_insn or prev_prev_insn, we | |
525 | point the insn_mo field at this dummy integer. */ | |
9c6ed8e6 | 526 | static const struct mips_opcode dummy_opcode = { NULL, NULL, 0, 0, 0, 0, 0 }; |
252b5132 RH |
527 | |
528 | /* Non-zero if prev_insn is valid. */ | |
529 | static int prev_insn_valid; | |
530 | ||
531 | /* The frag for the previous instruction. */ | |
532 | static struct frag *prev_insn_frag; | |
533 | ||
534 | /* The offset into prev_insn_frag for the previous instruction. */ | |
535 | static long prev_insn_where; | |
536 | ||
537 | /* The reloc type for the previous instruction, if any. */ | |
f6688943 | 538 | static bfd_reloc_code_real_type prev_insn_reloc_type[3]; |
252b5132 RH |
539 | |
540 | /* The reloc for the previous instruction, if any. */ | |
f6688943 | 541 | static fixS *prev_insn_fixp[3]; |
252b5132 RH |
542 | |
543 | /* Non-zero if the previous instruction was in a delay slot. */ | |
544 | static int prev_insn_is_delay_slot; | |
545 | ||
546 | /* Non-zero if the previous instruction was in a .set noreorder. */ | |
547 | static int prev_insn_unreordered; | |
548 | ||
549 | /* Non-zero if the previous instruction uses an extend opcode (if | |
550 | mips16). */ | |
551 | static int prev_insn_extended; | |
552 | ||
553 | /* Non-zero if the previous previous instruction was in a .set | |
554 | noreorder. */ | |
555 | static int prev_prev_insn_unreordered; | |
556 | ||
557 | /* If this is set, it points to a frag holding nop instructions which | |
558 | were inserted before the start of a noreorder section. If those | |
559 | nops turn out to be unnecessary, the size of the frag can be | |
560 | decreased. */ | |
561 | static fragS *prev_nop_frag; | |
562 | ||
563 | /* The number of nop instructions we created in prev_nop_frag. */ | |
564 | static int prev_nop_frag_holds; | |
565 | ||
566 | /* The number of nop instructions that we know we need in | |
bdaaa2e1 | 567 | prev_nop_frag. */ |
252b5132 RH |
568 | static int prev_nop_frag_required; |
569 | ||
570 | /* The number of instructions we've seen since prev_nop_frag. */ | |
571 | static int prev_nop_frag_since; | |
572 | ||
573 | /* For ECOFF and ELF, relocations against symbols are done in two | |
574 | parts, with a HI relocation and a LO relocation. Each relocation | |
575 | has only 16 bits of space to store an addend. This means that in | |
576 | order for the linker to handle carries correctly, it must be able | |
577 | to locate both the HI and the LO relocation. This means that the | |
578 | relocations must appear in order in the relocation table. | |
579 | ||
580 | In order to implement this, we keep track of each unmatched HI | |
581 | relocation. We then sort them so that they immediately precede the | |
bdaaa2e1 | 582 | corresponding LO relocation. */ |
252b5132 | 583 | |
e972090a NC |
584 | struct mips_hi_fixup |
585 | { | |
252b5132 RH |
586 | /* Next HI fixup. */ |
587 | struct mips_hi_fixup *next; | |
588 | /* This fixup. */ | |
589 | fixS *fixp; | |
590 | /* The section this fixup is in. */ | |
591 | segT seg; | |
592 | }; | |
593 | ||
594 | /* The list of unmatched HI relocs. */ | |
595 | ||
596 | static struct mips_hi_fixup *mips_hi_fixup_list; | |
597 | ||
64bdfcaf RS |
598 | /* The frag containing the last explicit relocation operator. |
599 | Null if explicit relocations have not been used. */ | |
600 | ||
601 | static fragS *prev_reloc_op_frag; | |
602 | ||
252b5132 RH |
603 | /* Map normal MIPS register numbers to mips16 register numbers. */ |
604 | ||
605 | #define X ILLEGAL_REG | |
e972090a NC |
606 | static const int mips32_to_16_reg_map[] = |
607 | { | |
252b5132 RH |
608 | X, X, 2, 3, 4, 5, 6, 7, |
609 | X, X, X, X, X, X, X, X, | |
610 | 0, 1, X, X, X, X, X, X, | |
611 | X, X, X, X, X, X, X, X | |
612 | }; | |
613 | #undef X | |
614 | ||
615 | /* Map mips16 register numbers to normal MIPS register numbers. */ | |
616 | ||
e972090a NC |
617 | static const unsigned int mips16_to_32_reg_map[] = |
618 | { | |
252b5132 RH |
619 | 16, 17, 2, 3, 4, 5, 6, 7 |
620 | }; | |
60b63b72 | 621 | |
d766e8ec | 622 | static int mips_fix_vr4120; |
4a6a3df4 AO |
623 | |
624 | /* We don't relax branches by default, since this causes us to expand | |
625 | `la .l2 - .l1' if there's a branch between .l1 and .l2, because we | |
626 | fail to compute the offset before expanding the macro to the most | |
627 | efficient expansion. */ | |
628 | ||
629 | static int mips_relax_branch; | |
252b5132 | 630 | \f |
4d7206a2 RS |
631 | /* The expansion of many macros depends on the type of symbol that |
632 | they refer to. For example, when generating position-dependent code, | |
633 | a macro that refers to a symbol may have two different expansions, | |
634 | one which uses GP-relative addresses and one which uses absolute | |
635 | addresses. When generating SVR4-style PIC, a macro may have | |
636 | different expansions for local and global symbols. | |
637 | ||
638 | We handle these situations by generating both sequences and putting | |
639 | them in variant frags. In position-dependent code, the first sequence | |
640 | will be the GP-relative one and the second sequence will be the | |
641 | absolute one. In SVR4 PIC, the first sequence will be for global | |
642 | symbols and the second will be for local symbols. | |
643 | ||
584892a6 RS |
644 | The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and |
645 | SECOND are the lengths of the two sequences in bytes. These fields | |
646 | can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition, | |
647 | the subtype has the following flags: | |
4d7206a2 | 648 | |
584892a6 RS |
649 | RELAX_USE_SECOND |
650 | Set if it has been decided that we should use the second | |
651 | sequence instead of the first. | |
652 | ||
653 | RELAX_SECOND_LONGER | |
654 | Set in the first variant frag if the macro's second implementation | |
655 | is longer than its first. This refers to the macro as a whole, | |
656 | not an individual relaxation. | |
657 | ||
658 | RELAX_NOMACRO | |
659 | Set in the first variant frag if the macro appeared in a .set nomacro | |
660 | block and if one alternative requires a warning but the other does not. | |
661 | ||
662 | RELAX_DELAY_SLOT | |
663 | Like RELAX_NOMACRO, but indicates that the macro appears in a branch | |
664 | delay slot. | |
4d7206a2 RS |
665 | |
666 | The frag's "opcode" points to the first fixup for relaxable code. | |
667 | ||
668 | Relaxable macros are generated using a sequence such as: | |
669 | ||
670 | relax_start (SYMBOL); | |
671 | ... generate first expansion ... | |
672 | relax_switch (); | |
673 | ... generate second expansion ... | |
674 | relax_end (); | |
675 | ||
676 | The code and fixups for the unwanted alternative are discarded | |
677 | by md_convert_frag. */ | |
584892a6 | 678 | #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND)) |
4d7206a2 | 679 | |
584892a6 RS |
680 | #define RELAX_FIRST(X) (((X) >> 8) & 0xff) |
681 | #define RELAX_SECOND(X) ((X) & 0xff) | |
682 | #define RELAX_USE_SECOND 0x10000 | |
683 | #define RELAX_SECOND_LONGER 0x20000 | |
684 | #define RELAX_NOMACRO 0x40000 | |
685 | #define RELAX_DELAY_SLOT 0x80000 | |
252b5132 | 686 | |
4a6a3df4 AO |
687 | /* Branch without likely bit. If label is out of range, we turn: |
688 | ||
689 | beq reg1, reg2, label | |
690 | delay slot | |
691 | ||
692 | into | |
693 | ||
694 | bne reg1, reg2, 0f | |
695 | nop | |
696 | j label | |
697 | 0: delay slot | |
698 | ||
699 | with the following opcode replacements: | |
700 | ||
701 | beq <-> bne | |
702 | blez <-> bgtz | |
703 | bltz <-> bgez | |
704 | bc1f <-> bc1t | |
705 | ||
706 | bltzal <-> bgezal (with jal label instead of j label) | |
707 | ||
708 | Even though keeping the delay slot instruction in the delay slot of | |
709 | the branch would be more efficient, it would be very tricky to do | |
710 | correctly, because we'd have to introduce a variable frag *after* | |
711 | the delay slot instruction, and expand that instead. Let's do it | |
712 | the easy way for now, even if the branch-not-taken case now costs | |
713 | one additional instruction. Out-of-range branches are not supposed | |
714 | to be common, anyway. | |
715 | ||
716 | Branch likely. If label is out of range, we turn: | |
717 | ||
718 | beql reg1, reg2, label | |
719 | delay slot (annulled if branch not taken) | |
720 | ||
721 | into | |
722 | ||
723 | beql reg1, reg2, 1f | |
724 | nop | |
725 | beql $0, $0, 2f | |
726 | nop | |
727 | 1: j[al] label | |
728 | delay slot (executed only if branch taken) | |
729 | 2: | |
730 | ||
731 | It would be possible to generate a shorter sequence by losing the | |
732 | likely bit, generating something like: | |
b34976b6 | 733 | |
4a6a3df4 AO |
734 | bne reg1, reg2, 0f |
735 | nop | |
736 | j[al] label | |
737 | delay slot (executed only if branch taken) | |
738 | 0: | |
739 | ||
740 | beql -> bne | |
741 | bnel -> beq | |
742 | blezl -> bgtz | |
743 | bgtzl -> blez | |
744 | bltzl -> bgez | |
745 | bgezl -> bltz | |
746 | bc1fl -> bc1t | |
747 | bc1tl -> bc1f | |
748 | ||
749 | bltzall -> bgezal (with jal label instead of j label) | |
750 | bgezall -> bltzal (ditto) | |
751 | ||
752 | ||
753 | but it's not clear that it would actually improve performance. */ | |
af6ae2ad | 754 | #define RELAX_BRANCH_ENCODE(uncond, likely, link, toofar) \ |
4a6a3df4 AO |
755 | ((relax_substateT) \ |
756 | (0xc0000000 \ | |
757 | | ((toofar) ? 1 : 0) \ | |
758 | | ((link) ? 2 : 0) \ | |
759 | | ((likely) ? 4 : 0) \ | |
af6ae2ad | 760 | | ((uncond) ? 8 : 0))) |
4a6a3df4 | 761 | #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000) |
4a6a3df4 AO |
762 | #define RELAX_BRANCH_UNCOND(i) (((i) & 8) != 0) |
763 | #define RELAX_BRANCH_LIKELY(i) (((i) & 4) != 0) | |
764 | #define RELAX_BRANCH_LINK(i) (((i) & 2) != 0) | |
ae6063d4 | 765 | #define RELAX_BRANCH_TOOFAR(i) (((i) & 1) != 0) |
4a6a3df4 | 766 | |
252b5132 RH |
767 | /* For mips16 code, we use an entirely different form of relaxation. |
768 | mips16 supports two versions of most instructions which take | |
769 | immediate values: a small one which takes some small value, and a | |
770 | larger one which takes a 16 bit value. Since branches also follow | |
771 | this pattern, relaxing these values is required. | |
772 | ||
773 | We can assemble both mips16 and normal MIPS code in a single | |
774 | object. Therefore, we need to support this type of relaxation at | |
775 | the same time that we support the relaxation described above. We | |
776 | use the high bit of the subtype field to distinguish these cases. | |
777 | ||
778 | The information we store for this type of relaxation is the | |
779 | argument code found in the opcode file for this relocation, whether | |
780 | the user explicitly requested a small or extended form, and whether | |
781 | the relocation is in a jump or jal delay slot. That tells us the | |
782 | size of the value, and how it should be stored. We also store | |
783 | whether the fragment is considered to be extended or not. We also | |
784 | store whether this is known to be a branch to a different section, | |
785 | whether we have tried to relax this frag yet, and whether we have | |
786 | ever extended a PC relative fragment because of a shift count. */ | |
787 | #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \ | |
788 | (0x80000000 \ | |
789 | | ((type) & 0xff) \ | |
790 | | ((small) ? 0x100 : 0) \ | |
791 | | ((ext) ? 0x200 : 0) \ | |
792 | | ((dslot) ? 0x400 : 0) \ | |
793 | | ((jal_dslot) ? 0x800 : 0)) | |
4a6a3df4 | 794 | #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000) |
252b5132 RH |
795 | #define RELAX_MIPS16_TYPE(i) ((i) & 0xff) |
796 | #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0) | |
797 | #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0) | |
798 | #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0) | |
799 | #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0) | |
800 | #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0) | |
801 | #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000) | |
802 | #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000) | |
803 | #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0) | |
804 | #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000) | |
805 | #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000) | |
885add95 CD |
806 | |
807 | /* Is the given value a sign-extended 32-bit value? */ | |
808 | #define IS_SEXT_32BIT_NUM(x) \ | |
809 | (((x) &~ (offsetT) 0x7fffffff) == 0 \ | |
810 | || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff)) | |
811 | ||
812 | /* Is the given value a sign-extended 16-bit value? */ | |
813 | #define IS_SEXT_16BIT_NUM(x) \ | |
814 | (((x) &~ (offsetT) 0x7fff) == 0 \ | |
815 | || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff)) | |
816 | ||
4d7206a2 RS |
817 | \f |
818 | /* Global variables used when generating relaxable macros. See the | |
819 | comment above RELAX_ENCODE for more details about how relaxation | |
820 | is used. */ | |
821 | static struct { | |
822 | /* 0 if we're not emitting a relaxable macro. | |
823 | 1 if we're emitting the first of the two relaxation alternatives. | |
824 | 2 if we're emitting the second alternative. */ | |
825 | int sequence; | |
826 | ||
827 | /* The first relaxable fixup in the current frag. (In other words, | |
828 | the first fixup that refers to relaxable code.) */ | |
829 | fixS *first_fixup; | |
830 | ||
831 | /* sizes[0] says how many bytes of the first alternative are stored in | |
832 | the current frag. Likewise sizes[1] for the second alternative. */ | |
833 | unsigned int sizes[2]; | |
834 | ||
835 | /* The symbol on which the choice of sequence depends. */ | |
836 | symbolS *symbol; | |
837 | } mips_relax; | |
252b5132 | 838 | \f |
584892a6 RS |
839 | /* Global variables used to decide whether a macro needs a warning. */ |
840 | static struct { | |
841 | /* True if the macro is in a branch delay slot. */ | |
842 | bfd_boolean delay_slot_p; | |
843 | ||
844 | /* For relaxable macros, sizes[0] is the length of the first alternative | |
845 | in bytes and sizes[1] is the length of the second alternative. | |
846 | For non-relaxable macros, both elements give the length of the | |
847 | macro in bytes. */ | |
848 | unsigned int sizes[2]; | |
849 | ||
850 | /* The first variant frag for this macro. */ | |
851 | fragS *first_frag; | |
852 | } mips_macro_warning; | |
853 | \f | |
252b5132 RH |
854 | /* Prototypes for static functions. */ |
855 | ||
17a2f251 | 856 | #define internalError() \ |
252b5132 | 857 | as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__) |
252b5132 RH |
858 | |
859 | enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG }; | |
860 | ||
b34976b6 | 861 | static void append_insn |
4d7206a2 | 862 | (struct mips_cl_insn *ip, expressionS *p, bfd_reloc_code_real_type *r); |
17a2f251 | 863 | static void mips_no_prev_insn (int); |
b34976b6 | 864 | static void mips16_macro_build |
67c0d1eb RS |
865 | (expressionS *, const char *, const char *, va_list); |
866 | static void load_register (int, expressionS *, int); | |
584892a6 RS |
867 | static void macro_start (void); |
868 | static void macro_end (void); | |
17a2f251 TS |
869 | static void macro (struct mips_cl_insn * ip); |
870 | static void mips16_macro (struct mips_cl_insn * ip); | |
252b5132 | 871 | #ifdef LOSING_COMPILER |
17a2f251 | 872 | static void macro2 (struct mips_cl_insn * ip); |
252b5132 | 873 | #endif |
17a2f251 TS |
874 | static void mips_ip (char *str, struct mips_cl_insn * ip); |
875 | static void mips16_ip (char *str, struct mips_cl_insn * ip); | |
b34976b6 | 876 | static void mips16_immed |
17a2f251 TS |
877 | (char *, unsigned int, int, offsetT, bfd_boolean, bfd_boolean, bfd_boolean, |
878 | unsigned long *, bfd_boolean *, unsigned short *); | |
5e0116d5 | 879 | static size_t my_getSmallExpression |
17a2f251 TS |
880 | (expressionS *, bfd_reloc_code_real_type *, char *); |
881 | static void my_getExpression (expressionS *, char *); | |
882 | static void s_align (int); | |
883 | static void s_change_sec (int); | |
884 | static void s_change_section (int); | |
885 | static void s_cons (int); | |
886 | static void s_float_cons (int); | |
887 | static void s_mips_globl (int); | |
888 | static void s_option (int); | |
889 | static void s_mipsset (int); | |
890 | static void s_abicalls (int); | |
891 | static void s_cpload (int); | |
892 | static void s_cpsetup (int); | |
893 | static void s_cplocal (int); | |
894 | static void s_cprestore (int); | |
895 | static void s_cpreturn (int); | |
896 | static void s_gpvalue (int); | |
897 | static void s_gpword (int); | |
898 | static void s_gpdword (int); | |
899 | static void s_cpadd (int); | |
900 | static void s_insn (int); | |
901 | static void md_obj_begin (void); | |
902 | static void md_obj_end (void); | |
903 | static void s_mips_ent (int); | |
904 | static void s_mips_end (int); | |
905 | static void s_mips_frame (int); | |
906 | static void s_mips_mask (int reg_type); | |
907 | static void s_mips_stab (int); | |
908 | static void s_mips_weakext (int); | |
909 | static void s_mips_file (int); | |
910 | static void s_mips_loc (int); | |
911 | static bfd_boolean pic_need_relax (symbolS *, asection *); | |
4a6a3df4 | 912 | static int relaxed_branch_length (fragS *, asection *, int); |
17a2f251 | 913 | static int validate_mips_insn (const struct mips_opcode *); |
e7af610e NC |
914 | |
915 | /* Table and functions used to map between CPU/ISA names, and | |
916 | ISA levels, and CPU numbers. */ | |
917 | ||
e972090a NC |
918 | struct mips_cpu_info |
919 | { | |
e7af610e NC |
920 | const char *name; /* CPU or ISA name. */ |
921 | int is_isa; /* Is this an ISA? (If 0, a CPU.) */ | |
922 | int isa; /* ISA level. */ | |
923 | int cpu; /* CPU number (default CPU if ISA). */ | |
924 | }; | |
925 | ||
17a2f251 TS |
926 | static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *); |
927 | static const struct mips_cpu_info *mips_cpu_info_from_isa (int); | |
928 | static const struct mips_cpu_info *mips_cpu_info_from_arch (int); | |
252b5132 RH |
929 | \f |
930 | /* Pseudo-op table. | |
931 | ||
932 | The following pseudo-ops from the Kane and Heinrich MIPS book | |
933 | should be defined here, but are currently unsupported: .alias, | |
934 | .galive, .gjaldef, .gjrlive, .livereg, .noalias. | |
935 | ||
936 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
937 | specific to the type of debugging information being generated, and | |
938 | should be defined by the object format: .aent, .begin, .bend, | |
939 | .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp, | |
940 | .vreg. | |
941 | ||
942 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
943 | not MIPS CPU specific, but are also not specific to the object file | |
944 | format. This file is probably the best place to define them, but | |
945 | they are not currently supported: .asm0, .endr, .lab, .repeat, | |
946 | .struct. */ | |
947 | ||
e972090a NC |
948 | static const pseudo_typeS mips_pseudo_table[] = |
949 | { | |
beae10d5 | 950 | /* MIPS specific pseudo-ops. */ |
252b5132 RH |
951 | {"option", s_option, 0}, |
952 | {"set", s_mipsset, 0}, | |
953 | {"rdata", s_change_sec, 'r'}, | |
954 | {"sdata", s_change_sec, 's'}, | |
955 | {"livereg", s_ignore, 0}, | |
956 | {"abicalls", s_abicalls, 0}, | |
957 | {"cpload", s_cpload, 0}, | |
6478892d TS |
958 | {"cpsetup", s_cpsetup, 0}, |
959 | {"cplocal", s_cplocal, 0}, | |
252b5132 | 960 | {"cprestore", s_cprestore, 0}, |
6478892d TS |
961 | {"cpreturn", s_cpreturn, 0}, |
962 | {"gpvalue", s_gpvalue, 0}, | |
252b5132 | 963 | {"gpword", s_gpword, 0}, |
10181a0d | 964 | {"gpdword", s_gpdword, 0}, |
252b5132 RH |
965 | {"cpadd", s_cpadd, 0}, |
966 | {"insn", s_insn, 0}, | |
967 | ||
beae10d5 | 968 | /* Relatively generic pseudo-ops that happen to be used on MIPS |
252b5132 RH |
969 | chips. */ |
970 | {"asciiz", stringer, 1}, | |
971 | {"bss", s_change_sec, 'b'}, | |
972 | {"err", s_err, 0}, | |
973 | {"half", s_cons, 1}, | |
974 | {"dword", s_cons, 3}, | |
975 | {"weakext", s_mips_weakext, 0}, | |
976 | ||
beae10d5 | 977 | /* These pseudo-ops are defined in read.c, but must be overridden |
252b5132 RH |
978 | here for one reason or another. */ |
979 | {"align", s_align, 0}, | |
980 | {"byte", s_cons, 0}, | |
981 | {"data", s_change_sec, 'd'}, | |
982 | {"double", s_float_cons, 'd'}, | |
983 | {"float", s_float_cons, 'f'}, | |
984 | {"globl", s_mips_globl, 0}, | |
985 | {"global", s_mips_globl, 0}, | |
986 | {"hword", s_cons, 1}, | |
987 | {"int", s_cons, 2}, | |
988 | {"long", s_cons, 2}, | |
989 | {"octa", s_cons, 4}, | |
990 | {"quad", s_cons, 3}, | |
cca86cc8 | 991 | {"section", s_change_section, 0}, |
252b5132 RH |
992 | {"short", s_cons, 1}, |
993 | {"single", s_float_cons, 'f'}, | |
994 | {"stabn", s_mips_stab, 'n'}, | |
995 | {"text", s_change_sec, 't'}, | |
996 | {"word", s_cons, 2}, | |
add56521 | 997 | |
add56521 | 998 | { "extern", ecoff_directive_extern, 0}, |
add56521 | 999 | |
43841e91 | 1000 | { NULL, NULL, 0 }, |
252b5132 RH |
1001 | }; |
1002 | ||
e972090a NC |
1003 | static const pseudo_typeS mips_nonecoff_pseudo_table[] = |
1004 | { | |
beae10d5 KH |
1005 | /* These pseudo-ops should be defined by the object file format. |
1006 | However, a.out doesn't support them, so we have versions here. */ | |
252b5132 RH |
1007 | {"aent", s_mips_ent, 1}, |
1008 | {"bgnb", s_ignore, 0}, | |
1009 | {"end", s_mips_end, 0}, | |
1010 | {"endb", s_ignore, 0}, | |
1011 | {"ent", s_mips_ent, 0}, | |
c5dd6aab | 1012 | {"file", s_mips_file, 0}, |
252b5132 RH |
1013 | {"fmask", s_mips_mask, 'F'}, |
1014 | {"frame", s_mips_frame, 0}, | |
c5dd6aab | 1015 | {"loc", s_mips_loc, 0}, |
252b5132 RH |
1016 | {"mask", s_mips_mask, 'R'}, |
1017 | {"verstamp", s_ignore, 0}, | |
43841e91 | 1018 | { NULL, NULL, 0 }, |
252b5132 RH |
1019 | }; |
1020 | ||
17a2f251 | 1021 | extern void pop_insert (const pseudo_typeS *); |
252b5132 RH |
1022 | |
1023 | void | |
17a2f251 | 1024 | mips_pop_insert (void) |
252b5132 RH |
1025 | { |
1026 | pop_insert (mips_pseudo_table); | |
1027 | if (! ECOFF_DEBUGGING) | |
1028 | pop_insert (mips_nonecoff_pseudo_table); | |
1029 | } | |
1030 | \f | |
1031 | /* Symbols labelling the current insn. */ | |
1032 | ||
e972090a NC |
1033 | struct insn_label_list |
1034 | { | |
252b5132 RH |
1035 | struct insn_label_list *next; |
1036 | symbolS *label; | |
1037 | }; | |
1038 | ||
1039 | static struct insn_label_list *insn_labels; | |
1040 | static struct insn_label_list *free_insn_labels; | |
1041 | ||
17a2f251 | 1042 | static void mips_clear_insn_labels (void); |
252b5132 RH |
1043 | |
1044 | static inline void | |
17a2f251 | 1045 | mips_clear_insn_labels (void) |
252b5132 RH |
1046 | { |
1047 | register struct insn_label_list **pl; | |
1048 | ||
1049 | for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next) | |
1050 | ; | |
1051 | *pl = insn_labels; | |
1052 | insn_labels = NULL; | |
1053 | } | |
1054 | \f | |
1055 | static char *expr_end; | |
1056 | ||
1057 | /* Expressions which appear in instructions. These are set by | |
1058 | mips_ip. */ | |
1059 | ||
1060 | static expressionS imm_expr; | |
5f74bc13 | 1061 | static expressionS imm2_expr; |
252b5132 RH |
1062 | static expressionS offset_expr; |
1063 | ||
1064 | /* Relocs associated with imm_expr and offset_expr. */ | |
1065 | ||
f6688943 TS |
1066 | static bfd_reloc_code_real_type imm_reloc[3] |
1067 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
1068 | static bfd_reloc_code_real_type offset_reloc[3] | |
1069 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 1070 | |
252b5132 RH |
1071 | /* These are set by mips16_ip if an explicit extension is used. */ |
1072 | ||
b34976b6 | 1073 | static bfd_boolean mips16_small, mips16_ext; |
252b5132 | 1074 | |
7ed4a06a | 1075 | #ifdef OBJ_ELF |
ecb4347a DJ |
1076 | /* The pdr segment for per procedure frame/regmask info. Not used for |
1077 | ECOFF debugging. */ | |
252b5132 RH |
1078 | |
1079 | static segT pdr_seg; | |
7ed4a06a | 1080 | #endif |
252b5132 | 1081 | |
e013f690 TS |
1082 | /* The default target format to use. */ |
1083 | ||
1084 | const char * | |
17a2f251 | 1085 | mips_target_format (void) |
e013f690 TS |
1086 | { |
1087 | switch (OUTPUT_FLAVOR) | |
1088 | { | |
e013f690 TS |
1089 | case bfd_target_ecoff_flavour: |
1090 | return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT; | |
1091 | case bfd_target_coff_flavour: | |
1092 | return "pe-mips"; | |
1093 | case bfd_target_elf_flavour: | |
1094 | #ifdef TE_TMIPS | |
cfe86eaa | 1095 | /* This is traditional mips. */ |
e013f690 | 1096 | return (target_big_endian |
cfe86eaa TS |
1097 | ? (HAVE_64BIT_OBJECTS |
1098 | ? "elf64-tradbigmips" | |
1099 | : (HAVE_NEWABI | |
1100 | ? "elf32-ntradbigmips" : "elf32-tradbigmips")) | |
1101 | : (HAVE_64BIT_OBJECTS | |
1102 | ? "elf64-tradlittlemips" | |
1103 | : (HAVE_NEWABI | |
1104 | ? "elf32-ntradlittlemips" : "elf32-tradlittlemips"))); | |
e013f690 TS |
1105 | #else |
1106 | return (target_big_endian | |
cfe86eaa TS |
1107 | ? (HAVE_64BIT_OBJECTS |
1108 | ? "elf64-bigmips" | |
1109 | : (HAVE_NEWABI | |
1110 | ? "elf32-nbigmips" : "elf32-bigmips")) | |
1111 | : (HAVE_64BIT_OBJECTS | |
1112 | ? "elf64-littlemips" | |
1113 | : (HAVE_NEWABI | |
1114 | ? "elf32-nlittlemips" : "elf32-littlemips"))); | |
e013f690 TS |
1115 | #endif |
1116 | default: | |
1117 | abort (); | |
1118 | return NULL; | |
1119 | } | |
1120 | } | |
1121 | ||
156c2f8b NC |
1122 | /* This function is called once, at assembler startup time. It should |
1123 | set up all the tables, etc. that the MD part of the assembler will need. */ | |
1124 | ||
252b5132 | 1125 | void |
17a2f251 | 1126 | md_begin (void) |
252b5132 | 1127 | { |
252b5132 | 1128 | register const char *retval = NULL; |
156c2f8b | 1129 | int i = 0; |
252b5132 | 1130 | int broken = 0; |
1f25f5d3 | 1131 | |
fef14a42 | 1132 | if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_arch)) |
252b5132 RH |
1133 | as_warn (_("Could not set architecture and machine")); |
1134 | ||
252b5132 RH |
1135 | op_hash = hash_new (); |
1136 | ||
1137 | for (i = 0; i < NUMOPCODES;) | |
1138 | { | |
1139 | const char *name = mips_opcodes[i].name; | |
1140 | ||
17a2f251 | 1141 | retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]); |
252b5132 RH |
1142 | if (retval != NULL) |
1143 | { | |
1144 | fprintf (stderr, _("internal error: can't hash `%s': %s\n"), | |
1145 | mips_opcodes[i].name, retval); | |
1146 | /* Probably a memory allocation problem? Give up now. */ | |
1147 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
1148 | } | |
1149 | do | |
1150 | { | |
1151 | if (mips_opcodes[i].pinfo != INSN_MACRO) | |
1152 | { | |
1153 | if (!validate_mips_insn (&mips_opcodes[i])) | |
1154 | broken = 1; | |
1155 | } | |
1156 | ++i; | |
1157 | } | |
1158 | while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name)); | |
1159 | } | |
1160 | ||
1161 | mips16_op_hash = hash_new (); | |
1162 | ||
1163 | i = 0; | |
1164 | while (i < bfd_mips16_num_opcodes) | |
1165 | { | |
1166 | const char *name = mips16_opcodes[i].name; | |
1167 | ||
17a2f251 | 1168 | retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]); |
252b5132 RH |
1169 | if (retval != NULL) |
1170 | as_fatal (_("internal: can't hash `%s': %s"), | |
1171 | mips16_opcodes[i].name, retval); | |
1172 | do | |
1173 | { | |
1174 | if (mips16_opcodes[i].pinfo != INSN_MACRO | |
1175 | && ((mips16_opcodes[i].match & mips16_opcodes[i].mask) | |
1176 | != mips16_opcodes[i].match)) | |
1177 | { | |
1178 | fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"), | |
1179 | mips16_opcodes[i].name, mips16_opcodes[i].args); | |
1180 | broken = 1; | |
1181 | } | |
1182 | ++i; | |
1183 | } | |
1184 | while (i < bfd_mips16_num_opcodes | |
1185 | && strcmp (mips16_opcodes[i].name, name) == 0); | |
1186 | } | |
1187 | ||
1188 | if (broken) | |
1189 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
1190 | ||
1191 | /* We add all the general register names to the symbol table. This | |
1192 | helps us detect invalid uses of them. */ | |
1193 | for (i = 0; i < 32; i++) | |
1194 | { | |
1195 | char buf[5]; | |
1196 | ||
1197 | sprintf (buf, "$%d", i); | |
1198 | symbol_table_insert (symbol_new (buf, reg_section, i, | |
1199 | &zero_address_frag)); | |
1200 | } | |
76db943d TS |
1201 | symbol_table_insert (symbol_new ("$ra", reg_section, RA, |
1202 | &zero_address_frag)); | |
252b5132 RH |
1203 | symbol_table_insert (symbol_new ("$fp", reg_section, FP, |
1204 | &zero_address_frag)); | |
1205 | symbol_table_insert (symbol_new ("$sp", reg_section, SP, | |
1206 | &zero_address_frag)); | |
1207 | symbol_table_insert (symbol_new ("$gp", reg_section, GP, | |
1208 | &zero_address_frag)); | |
1209 | symbol_table_insert (symbol_new ("$at", reg_section, AT, | |
1210 | &zero_address_frag)); | |
1211 | symbol_table_insert (symbol_new ("$kt0", reg_section, KT0, | |
1212 | &zero_address_frag)); | |
1213 | symbol_table_insert (symbol_new ("$kt1", reg_section, KT1, | |
1214 | &zero_address_frag)); | |
85b51719 TS |
1215 | symbol_table_insert (symbol_new ("$zero", reg_section, ZERO, |
1216 | &zero_address_frag)); | |
252b5132 RH |
1217 | symbol_table_insert (symbol_new ("$pc", reg_section, -1, |
1218 | &zero_address_frag)); | |
1219 | ||
6047c971 AO |
1220 | /* If we don't add these register names to the symbol table, they |
1221 | may end up being added as regular symbols by operand(), and then | |
1222 | make it to the object file as undefined in case they're not | |
1223 | regarded as local symbols. They're local in o32, since `$' is a | |
1224 | local symbol prefix, but not in n32 or n64. */ | |
1225 | for (i = 0; i < 8; i++) | |
1226 | { | |
1227 | char buf[6]; | |
1228 | ||
1229 | sprintf (buf, "$fcc%i", i); | |
1230 | symbol_table_insert (symbol_new (buf, reg_section, -1, | |
1231 | &zero_address_frag)); | |
1232 | } | |
1233 | ||
b34976b6 | 1234 | mips_no_prev_insn (FALSE); |
252b5132 RH |
1235 | |
1236 | mips_gprmask = 0; | |
1237 | mips_cprmask[0] = 0; | |
1238 | mips_cprmask[1] = 0; | |
1239 | mips_cprmask[2] = 0; | |
1240 | mips_cprmask[3] = 0; | |
1241 | ||
1242 | /* set the default alignment for the text section (2**2) */ | |
1243 | record_alignment (text_section, 2); | |
1244 | ||
4d0d148d | 1245 | bfd_set_gp_size (stdoutput, g_switch_value); |
252b5132 RH |
1246 | |
1247 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
1248 | { | |
1249 | /* On a native system, sections must be aligned to 16 byte | |
1250 | boundaries. When configured for an embedded ELF target, we | |
1251 | don't bother. */ | |
1252 | if (strcmp (TARGET_OS, "elf") != 0) | |
1253 | { | |
1254 | (void) bfd_set_section_alignment (stdoutput, text_section, 4); | |
1255 | (void) bfd_set_section_alignment (stdoutput, data_section, 4); | |
1256 | (void) bfd_set_section_alignment (stdoutput, bss_section, 4); | |
1257 | } | |
1258 | ||
1259 | /* Create a .reginfo section for register masks and a .mdebug | |
1260 | section for debugging information. */ | |
1261 | { | |
1262 | segT seg; | |
1263 | subsegT subseg; | |
1264 | flagword flags; | |
1265 | segT sec; | |
1266 | ||
1267 | seg = now_seg; | |
1268 | subseg = now_subseg; | |
1269 | ||
1270 | /* The ABI says this section should be loaded so that the | |
1271 | running program can access it. However, we don't load it | |
1272 | if we are configured for an embedded target */ | |
1273 | flags = SEC_READONLY | SEC_DATA; | |
1274 | if (strcmp (TARGET_OS, "elf") != 0) | |
1275 | flags |= SEC_ALLOC | SEC_LOAD; | |
1276 | ||
316f5878 | 1277 | if (mips_abi != N64_ABI) |
252b5132 RH |
1278 | { |
1279 | sec = subseg_new (".reginfo", (subsegT) 0); | |
1280 | ||
195325d2 TS |
1281 | bfd_set_section_flags (stdoutput, sec, flags); |
1282 | bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2); | |
bdaaa2e1 | 1283 | |
252b5132 RH |
1284 | #ifdef OBJ_ELF |
1285 | mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo)); | |
1286 | #endif | |
1287 | } | |
1288 | else | |
1289 | { | |
1290 | /* The 64-bit ABI uses a .MIPS.options section rather than | |
1291 | .reginfo section. */ | |
1292 | sec = subseg_new (".MIPS.options", (subsegT) 0); | |
195325d2 TS |
1293 | bfd_set_section_flags (stdoutput, sec, flags); |
1294 | bfd_set_section_alignment (stdoutput, sec, 3); | |
252b5132 RH |
1295 | |
1296 | #ifdef OBJ_ELF | |
1297 | /* Set up the option header. */ | |
1298 | { | |
1299 | Elf_Internal_Options opthdr; | |
1300 | char *f; | |
1301 | ||
1302 | opthdr.kind = ODK_REGINFO; | |
1303 | opthdr.size = (sizeof (Elf_External_Options) | |
1304 | + sizeof (Elf64_External_RegInfo)); | |
1305 | opthdr.section = 0; | |
1306 | opthdr.info = 0; | |
1307 | f = frag_more (sizeof (Elf_External_Options)); | |
1308 | bfd_mips_elf_swap_options_out (stdoutput, &opthdr, | |
1309 | (Elf_External_Options *) f); | |
1310 | ||
1311 | mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo)); | |
1312 | } | |
1313 | #endif | |
1314 | } | |
1315 | ||
1316 | if (ECOFF_DEBUGGING) | |
1317 | { | |
1318 | sec = subseg_new (".mdebug", (subsegT) 0); | |
1319 | (void) bfd_set_section_flags (stdoutput, sec, | |
1320 | SEC_HAS_CONTENTS | SEC_READONLY); | |
1321 | (void) bfd_set_section_alignment (stdoutput, sec, 2); | |
1322 | } | |
ecb4347a | 1323 | #ifdef OBJ_ELF |
dcd410fe | 1324 | else if (OUTPUT_FLAVOR == bfd_target_elf_flavour && mips_flag_pdr) |
ecb4347a DJ |
1325 | { |
1326 | pdr_seg = subseg_new (".pdr", (subsegT) 0); | |
1327 | (void) bfd_set_section_flags (stdoutput, pdr_seg, | |
1328 | SEC_READONLY | SEC_RELOC | |
1329 | | SEC_DEBUGGING); | |
1330 | (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2); | |
1331 | } | |
252b5132 RH |
1332 | #endif |
1333 | ||
1334 | subseg_set (seg, subseg); | |
1335 | } | |
1336 | } | |
1337 | ||
1338 | if (! ECOFF_DEBUGGING) | |
1339 | md_obj_begin (); | |
1340 | } | |
1341 | ||
1342 | void | |
17a2f251 | 1343 | md_mips_end (void) |
252b5132 RH |
1344 | { |
1345 | if (! ECOFF_DEBUGGING) | |
1346 | md_obj_end (); | |
1347 | } | |
1348 | ||
1349 | void | |
17a2f251 | 1350 | md_assemble (char *str) |
252b5132 RH |
1351 | { |
1352 | struct mips_cl_insn insn; | |
f6688943 TS |
1353 | bfd_reloc_code_real_type unused_reloc[3] |
1354 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 RH |
1355 | |
1356 | imm_expr.X_op = O_absent; | |
5f74bc13 | 1357 | imm2_expr.X_op = O_absent; |
252b5132 | 1358 | offset_expr.X_op = O_absent; |
f6688943 TS |
1359 | imm_reloc[0] = BFD_RELOC_UNUSED; |
1360 | imm_reloc[1] = BFD_RELOC_UNUSED; | |
1361 | imm_reloc[2] = BFD_RELOC_UNUSED; | |
1362 | offset_reloc[0] = BFD_RELOC_UNUSED; | |
1363 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
1364 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
1365 | |
1366 | if (mips_opts.mips16) | |
1367 | mips16_ip (str, &insn); | |
1368 | else | |
1369 | { | |
1370 | mips_ip (str, &insn); | |
beae10d5 KH |
1371 | DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"), |
1372 | str, insn.insn_opcode)); | |
252b5132 RH |
1373 | } |
1374 | ||
1375 | if (insn_error) | |
1376 | { | |
1377 | as_bad ("%s `%s'", insn_error, str); | |
1378 | return; | |
1379 | } | |
1380 | ||
1381 | if (insn.insn_mo->pinfo == INSN_MACRO) | |
1382 | { | |
584892a6 | 1383 | macro_start (); |
252b5132 RH |
1384 | if (mips_opts.mips16) |
1385 | mips16_macro (&insn); | |
1386 | else | |
1387 | macro (&insn); | |
584892a6 | 1388 | macro_end (); |
252b5132 RH |
1389 | } |
1390 | else | |
1391 | { | |
1392 | if (imm_expr.X_op != O_absent) | |
4d7206a2 | 1393 | append_insn (&insn, &imm_expr, imm_reloc); |
252b5132 | 1394 | else if (offset_expr.X_op != O_absent) |
4d7206a2 | 1395 | append_insn (&insn, &offset_expr, offset_reloc); |
252b5132 | 1396 | else |
4d7206a2 | 1397 | append_insn (&insn, NULL, unused_reloc); |
252b5132 RH |
1398 | } |
1399 | } | |
1400 | ||
5919d012 RS |
1401 | /* Return true if the given relocation might need a matching %lo(). |
1402 | Note that R_MIPS_GOT16 relocations only need a matching %lo() when | |
1403 | applied to local symbols. */ | |
1404 | ||
1405 | static inline bfd_boolean | |
17a2f251 | 1406 | reloc_needs_lo_p (bfd_reloc_code_real_type reloc) |
5919d012 | 1407 | { |
3b91255e RS |
1408 | return (HAVE_IN_PLACE_ADDENDS |
1409 | && (reloc == BFD_RELOC_HI16_S | |
d6f16593 MR |
1410 | || reloc == BFD_RELOC_MIPS_GOT16 |
1411 | || reloc == BFD_RELOC_MIPS16_HI16_S)); | |
5919d012 RS |
1412 | } |
1413 | ||
1414 | /* Return true if the given fixup is followed by a matching R_MIPS_LO16 | |
1415 | relocation. */ | |
1416 | ||
1417 | static inline bfd_boolean | |
17a2f251 | 1418 | fixup_has_matching_lo_p (fixS *fixp) |
5919d012 RS |
1419 | { |
1420 | return (fixp->fx_next != NULL | |
d6f16593 MR |
1421 | && (fixp->fx_next->fx_r_type == BFD_RELOC_LO16 |
1422 | || fixp->fx_next->fx_r_type == BFD_RELOC_MIPS16_LO16) | |
5919d012 RS |
1423 | && fixp->fx_addsy == fixp->fx_next->fx_addsy |
1424 | && fixp->fx_offset == fixp->fx_next->fx_offset); | |
1425 | } | |
1426 | ||
252b5132 RH |
1427 | /* See whether instruction IP reads register REG. CLASS is the type |
1428 | of register. */ | |
1429 | ||
1430 | static int | |
17a2f251 TS |
1431 | insn_uses_reg (struct mips_cl_insn *ip, unsigned int reg, |
1432 | enum mips_regclass class) | |
252b5132 RH |
1433 | { |
1434 | if (class == MIPS16_REG) | |
1435 | { | |
1436 | assert (mips_opts.mips16); | |
1437 | reg = mips16_to_32_reg_map[reg]; | |
1438 | class = MIPS_GR_REG; | |
1439 | } | |
1440 | ||
85b51719 TS |
1441 | /* Don't report on general register ZERO, since it never changes. */ |
1442 | if (class == MIPS_GR_REG && reg == ZERO) | |
252b5132 RH |
1443 | return 0; |
1444 | ||
1445 | if (class == MIPS_FP_REG) | |
1446 | { | |
1447 | assert (! mips_opts.mips16); | |
1448 | /* If we are called with either $f0 or $f1, we must check $f0. | |
1449 | This is not optimal, because it will introduce an unnecessary | |
1450 | NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would | |
1451 | need to distinguish reading both $f0 and $f1 or just one of | |
1452 | them. Note that we don't have to check the other way, | |
1453 | because there is no instruction that sets both $f0 and $f1 | |
1454 | and requires a delay. */ | |
1455 | if ((ip->insn_mo->pinfo & INSN_READ_FPR_S) | |
1456 | && ((((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS) &~(unsigned)1) | |
1457 | == (reg &~ (unsigned) 1))) | |
1458 | return 1; | |
1459 | if ((ip->insn_mo->pinfo & INSN_READ_FPR_T) | |
1460 | && ((((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT) &~(unsigned)1) | |
1461 | == (reg &~ (unsigned) 1))) | |
1462 | return 1; | |
1463 | } | |
1464 | else if (! mips_opts.mips16) | |
1465 | { | |
1466 | if ((ip->insn_mo->pinfo & INSN_READ_GPR_S) | |
1467 | && ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == reg) | |
1468 | return 1; | |
1469 | if ((ip->insn_mo->pinfo & INSN_READ_GPR_T) | |
1470 | && ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT) == reg) | |
1471 | return 1; | |
1472 | } | |
1473 | else | |
1474 | { | |
1475 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_X) | |
1476 | && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_RX) | |
1477 | & MIPS16OP_MASK_RX)] | |
1478 | == reg)) | |
1479 | return 1; | |
1480 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Y) | |
1481 | && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_RY) | |
1482 | & MIPS16OP_MASK_RY)] | |
1483 | == reg)) | |
1484 | return 1; | |
1485 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Z) | |
1486 | && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z) | |
1487 | & MIPS16OP_MASK_MOVE32Z)] | |
1488 | == reg)) | |
1489 | return 1; | |
1490 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_T) && reg == TREG) | |
1491 | return 1; | |
1492 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_SP) && reg == SP) | |
1493 | return 1; | |
1494 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_31) && reg == RA) | |
1495 | return 1; | |
1496 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_GPR_X) | |
1497 | && ((ip->insn_opcode >> MIPS16OP_SH_REGR32) | |
1498 | & MIPS16OP_MASK_REGR32) == reg) | |
1499 | return 1; | |
1500 | } | |
1501 | ||
1502 | return 0; | |
1503 | } | |
1504 | ||
1505 | /* This function returns true if modifying a register requires a | |
1506 | delay. */ | |
1507 | ||
1508 | static int | |
17a2f251 | 1509 | reg_needs_delay (unsigned int reg) |
252b5132 RH |
1510 | { |
1511 | unsigned long prev_pinfo; | |
1512 | ||
1513 | prev_pinfo = prev_insn.insn_mo->pinfo; | |
1514 | if (! mips_opts.noreorder | |
81912461 ILT |
1515 | && (((prev_pinfo & INSN_LOAD_MEMORY_DELAY) |
1516 | && ! gpr_interlocks) | |
1517 | || ((prev_pinfo & INSN_LOAD_COPROC_DELAY) | |
1518 | && ! cop_interlocks))) | |
252b5132 | 1519 | { |
81912461 ILT |
1520 | /* A load from a coprocessor or from memory. All load delays |
1521 | delay the use of general register rt for one instruction. */ | |
bdaaa2e1 | 1522 | /* Itbl support may require additional care here. */ |
252b5132 RH |
1523 | know (prev_pinfo & INSN_WRITE_GPR_T); |
1524 | if (reg == ((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT)) | |
1525 | return 1; | |
1526 | } | |
1527 | ||
1528 | return 0; | |
1529 | } | |
1530 | ||
1531 | /* Mark instruction labels in mips16 mode. This permits the linker to | |
1532 | handle them specially, such as generating jalx instructions when | |
1533 | needed. We also make them odd for the duration of the assembly, in | |
1534 | order to generate the right sort of code. We will make them even | |
1535 | in the adjust_symtab routine, while leaving them marked. This is | |
1536 | convenient for the debugger and the disassembler. The linker knows | |
1537 | to make them odd again. */ | |
1538 | ||
1539 | static void | |
17a2f251 | 1540 | mips16_mark_labels (void) |
252b5132 RH |
1541 | { |
1542 | if (mips_opts.mips16) | |
1543 | { | |
1544 | struct insn_label_list *l; | |
98aa84af | 1545 | valueT val; |
252b5132 RH |
1546 | |
1547 | for (l = insn_labels; l != NULL; l = l->next) | |
1548 | { | |
1549 | #ifdef OBJ_ELF | |
1550 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
1551 | S_SET_OTHER (l->label, STO_MIPS16); | |
1552 | #endif | |
98aa84af AM |
1553 | val = S_GET_VALUE (l->label); |
1554 | if ((val & 1) == 0) | |
1555 | S_SET_VALUE (l->label, val + 1); | |
252b5132 RH |
1556 | } |
1557 | } | |
1558 | } | |
1559 | ||
4d7206a2 RS |
1560 | /* End the current frag. Make it a variant frag and record the |
1561 | relaxation info. */ | |
1562 | ||
1563 | static void | |
1564 | relax_close_frag (void) | |
1565 | { | |
584892a6 | 1566 | mips_macro_warning.first_frag = frag_now; |
4d7206a2 | 1567 | frag_var (rs_machine_dependent, 0, 0, |
584892a6 | 1568 | RELAX_ENCODE (mips_relax.sizes[0], mips_relax.sizes[1]), |
4d7206a2 RS |
1569 | mips_relax.symbol, 0, (char *) mips_relax.first_fixup); |
1570 | ||
1571 | memset (&mips_relax.sizes, 0, sizeof (mips_relax.sizes)); | |
1572 | mips_relax.first_fixup = 0; | |
1573 | } | |
1574 | ||
1575 | /* Start a new relaxation sequence whose expansion depends on SYMBOL. | |
1576 | See the comment above RELAX_ENCODE for more details. */ | |
1577 | ||
1578 | static void | |
1579 | relax_start (symbolS *symbol) | |
1580 | { | |
1581 | assert (mips_relax.sequence == 0); | |
1582 | mips_relax.sequence = 1; | |
1583 | mips_relax.symbol = symbol; | |
1584 | } | |
1585 | ||
1586 | /* Start generating the second version of a relaxable sequence. | |
1587 | See the comment above RELAX_ENCODE for more details. */ | |
252b5132 RH |
1588 | |
1589 | static void | |
4d7206a2 RS |
1590 | relax_switch (void) |
1591 | { | |
1592 | assert (mips_relax.sequence == 1); | |
1593 | mips_relax.sequence = 2; | |
1594 | } | |
1595 | ||
1596 | /* End the current relaxable sequence. */ | |
1597 | ||
1598 | static void | |
1599 | relax_end (void) | |
1600 | { | |
1601 | assert (mips_relax.sequence == 2); | |
1602 | relax_close_frag (); | |
1603 | mips_relax.sequence = 0; | |
1604 | } | |
1605 | ||
1606 | /* Output an instruction. IP is the instruction information. | |
1607 | ADDRESS_EXPR is an operand of the instruction to be used with | |
1608 | RELOC_TYPE. */ | |
1609 | ||
1610 | static void | |
1611 | append_insn (struct mips_cl_insn *ip, expressionS *address_expr, | |
17a2f251 | 1612 | bfd_reloc_code_real_type *reloc_type) |
252b5132 RH |
1613 | { |
1614 | register unsigned long prev_pinfo, pinfo; | |
1615 | char *f; | |
f6688943 | 1616 | fixS *fixp[3]; |
252b5132 | 1617 | int nops = 0; |
895921c9 MR |
1618 | relax_stateT prev_insn_frag_type = 0; |
1619 | bfd_boolean relaxed_branch = FALSE; | |
f5040a92 | 1620 | bfd_boolean force_new_frag = FALSE; |
252b5132 RH |
1621 | |
1622 | /* Mark instruction labels in mips16 mode. */ | |
f9419b05 | 1623 | mips16_mark_labels (); |
252b5132 RH |
1624 | |
1625 | prev_pinfo = prev_insn.insn_mo->pinfo; | |
1626 | pinfo = ip->insn_mo->pinfo; | |
1627 | ||
4d7206a2 RS |
1628 | if (mips_relax.sequence != 2 |
1629 | && (!mips_opts.noreorder || prev_nop_frag != NULL)) | |
252b5132 RH |
1630 | { |
1631 | int prev_prev_nop; | |
1632 | ||
1633 | /* If the previous insn required any delay slots, see if we need | |
1634 | to insert a NOP or two. There are eight kinds of possible | |
1635 | hazards, of which an instruction can have at most one type. | |
1636 | (1) a load from memory delay | |
1637 | (2) a load from a coprocessor delay | |
1638 | (3) an unconditional branch delay | |
1639 | (4) a conditional branch delay | |
1640 | (5) a move to coprocessor register delay | |
1641 | (6) a load coprocessor register from memory delay | |
1642 | (7) a coprocessor condition code delay | |
1643 | (8) a HI/LO special register delay | |
1644 | ||
1645 | There are a lot of optimizations we could do that we don't. | |
1646 | In particular, we do not, in general, reorder instructions. | |
1647 | If you use gcc with optimization, it will reorder | |
1648 | instructions and generally do much more optimization then we | |
1649 | do here; repeating all that work in the assembler would only | |
1650 | benefit hand written assembly code, and does not seem worth | |
1651 | it. */ | |
1652 | ||
1653 | /* This is how a NOP is emitted. */ | |
1654 | #define emit_nop() \ | |
1655 | (mips_opts.mips16 \ | |
1656 | ? md_number_to_chars (frag_more (2), 0x6500, 2) \ | |
1657 | : md_number_to_chars (frag_more (4), 0, 4)) | |
1658 | ||
1659 | /* The previous insn might require a delay slot, depending upon | |
1660 | the contents of the current insn. */ | |
1661 | if (! mips_opts.mips16 | |
81912461 ILT |
1662 | && (((prev_pinfo & INSN_LOAD_MEMORY_DELAY) |
1663 | && ! gpr_interlocks) | |
1664 | || ((prev_pinfo & INSN_LOAD_COPROC_DELAY) | |
1665 | && ! cop_interlocks))) | |
252b5132 RH |
1666 | { |
1667 | /* A load from a coprocessor or from memory. All load | |
1668 | delays delay the use of general register rt for one | |
81912461 | 1669 | instruction. */ |
beae10d5 | 1670 | /* Itbl support may require additional care here. */ |
252b5132 RH |
1671 | know (prev_pinfo & INSN_WRITE_GPR_T); |
1672 | if (mips_optimize == 0 | |
1673 | || insn_uses_reg (ip, | |
1674 | ((prev_insn.insn_opcode >> OP_SH_RT) | |
1675 | & OP_MASK_RT), | |
1676 | MIPS_GR_REG)) | |
1677 | ++nops; | |
1678 | } | |
1679 | else if (! mips_opts.mips16 | |
252b5132 | 1680 | && (((prev_pinfo & INSN_COPROC_MOVE_DELAY) |
beae10d5 | 1681 | && ! cop_interlocks) |
81912461 ILT |
1682 | || ((prev_pinfo & INSN_COPROC_MEMORY_DELAY) |
1683 | && ! cop_mem_interlocks))) | |
252b5132 RH |
1684 | { |
1685 | /* A generic coprocessor delay. The previous instruction | |
1686 | modified a coprocessor general or control register. If | |
1687 | it modified a control register, we need to avoid any | |
1688 | coprocessor instruction (this is probably not always | |
1689 | required, but it sometimes is). If it modified a general | |
1690 | register, we avoid using that register. | |
1691 | ||
252b5132 RH |
1692 | This case is not handled very well. There is no special |
1693 | knowledge of CP0 handling, and the coprocessors other | |
1694 | than the floating point unit are not distinguished at | |
1695 | all. */ | |
1696 | /* Itbl support may require additional care here. FIXME! | |
bdaaa2e1 | 1697 | Need to modify this to include knowledge about |
252b5132 RH |
1698 | user specified delays! */ |
1699 | if (prev_pinfo & INSN_WRITE_FPR_T) | |
1700 | { | |
1701 | if (mips_optimize == 0 | |
1702 | || insn_uses_reg (ip, | |
1703 | ((prev_insn.insn_opcode >> OP_SH_FT) | |
1704 | & OP_MASK_FT), | |
1705 | MIPS_FP_REG)) | |
1706 | ++nops; | |
1707 | } | |
1708 | else if (prev_pinfo & INSN_WRITE_FPR_S) | |
1709 | { | |
1710 | if (mips_optimize == 0 | |
1711 | || insn_uses_reg (ip, | |
1712 | ((prev_insn.insn_opcode >> OP_SH_FS) | |
1713 | & OP_MASK_FS), | |
1714 | MIPS_FP_REG)) | |
1715 | ++nops; | |
1716 | } | |
1717 | else | |
1718 | { | |
1719 | /* We don't know exactly what the previous instruction | |
1720 | does. If the current instruction uses a coprocessor | |
1721 | register, we must insert a NOP. If previous | |
1722 | instruction may set the condition codes, and the | |
1723 | current instruction uses them, we must insert two | |
1724 | NOPS. */ | |
bdaaa2e1 | 1725 | /* Itbl support may require additional care here. */ |
252b5132 RH |
1726 | if (mips_optimize == 0 |
1727 | || ((prev_pinfo & INSN_WRITE_COND_CODE) | |
1728 | && (pinfo & INSN_READ_COND_CODE))) | |
1729 | nops += 2; | |
1730 | else if (pinfo & INSN_COP) | |
1731 | ++nops; | |
1732 | } | |
1733 | } | |
1734 | else if (! mips_opts.mips16 | |
252b5132 RH |
1735 | && (prev_pinfo & INSN_WRITE_COND_CODE) |
1736 | && ! cop_interlocks) | |
1737 | { | |
1738 | /* The previous instruction sets the coprocessor condition | |
1739 | codes, but does not require a general coprocessor delay | |
1740 | (this means it is a floating point comparison | |
1741 | instruction). If this instruction uses the condition | |
1742 | codes, we need to insert a single NOP. */ | |
beae10d5 | 1743 | /* Itbl support may require additional care here. */ |
252b5132 RH |
1744 | if (mips_optimize == 0 |
1745 | || (pinfo & INSN_READ_COND_CODE)) | |
1746 | ++nops; | |
1747 | } | |
6b76fefe CM |
1748 | |
1749 | /* If we're fixing up mfhi/mflo for the r7000 and the | |
1750 | previous insn was an mfhi/mflo and the current insn | |
1751 | reads the register that the mfhi/mflo wrote to, then | |
1752 | insert two nops. */ | |
1753 | ||
1754 | else if (mips_7000_hilo_fix | |
1755 | && MF_HILO_INSN (prev_pinfo) | |
1756 | && insn_uses_reg (ip, ((prev_insn.insn_opcode >> OP_SH_RD) | |
beae10d5 KH |
1757 | & OP_MASK_RD), |
1758 | MIPS_GR_REG)) | |
6b76fefe CM |
1759 | { |
1760 | nops += 2; | |
1761 | } | |
1762 | ||
1763 | /* If we're fixing up mfhi/mflo for the r7000 and the | |
1764 | 2nd previous insn was an mfhi/mflo and the current insn | |
1765 | reads the register that the mfhi/mflo wrote to, then | |
1766 | insert one nop. */ | |
1767 | ||
1768 | else if (mips_7000_hilo_fix | |
1769 | && MF_HILO_INSN (prev_prev_insn.insn_opcode) | |
1770 | && insn_uses_reg (ip, ((prev_prev_insn.insn_opcode >> OP_SH_RD) | |
1771 | & OP_MASK_RD), | |
1772 | MIPS_GR_REG)) | |
bdaaa2e1 | 1773 | |
6b76fefe | 1774 | { |
f9419b05 | 1775 | ++nops; |
6b76fefe | 1776 | } |
bdaaa2e1 | 1777 | |
252b5132 RH |
1778 | else if (prev_pinfo & INSN_READ_LO) |
1779 | { | |
1780 | /* The previous instruction reads the LO register; if the | |
1781 | current instruction writes to the LO register, we must | |
bdaaa2e1 | 1782 | insert two NOPS. Some newer processors have interlocks. |
67c1ffbe KH |
1783 | Also the tx39's multiply instructions can be executed |
1784 | immediately after a read from HI/LO (without the delay), | |
bdaaa2e1 KH |
1785 | though the tx39's divide insns still do require the |
1786 | delay. */ | |
252b5132 | 1787 | if (! (hilo_interlocks |
048cdf86 | 1788 | || (mips_opts.arch == CPU_R3900 && (pinfo & INSN_MULT))) |
252b5132 RH |
1789 | && (mips_optimize == 0 |
1790 | || (pinfo & INSN_WRITE_LO))) | |
1791 | nops += 2; | |
1792 | /* Most mips16 branch insns don't have a delay slot. | |
1793 | If a read from LO is immediately followed by a branch | |
1794 | to a write to LO we have a read followed by a write | |
1795 | less than 2 insns away. We assume the target of | |
1796 | a branch might be a write to LO, and insert a nop | |
bdaaa2e1 | 1797 | between a read and an immediately following branch. */ |
252b5132 RH |
1798 | else if (mips_opts.mips16 |
1799 | && (mips_optimize == 0 | |
1800 | || (pinfo & MIPS16_INSN_BRANCH))) | |
f9419b05 | 1801 | ++nops; |
252b5132 RH |
1802 | } |
1803 | else if (prev_insn.insn_mo->pinfo & INSN_READ_HI) | |
1804 | { | |
1805 | /* The previous instruction reads the HI register; if the | |
1806 | current instruction writes to the HI register, we must | |
1807 | insert a NOP. Some newer processors have interlocks. | |
bdaaa2e1 | 1808 | Also the note tx39's multiply above. */ |
252b5132 | 1809 | if (! (hilo_interlocks |
048cdf86 | 1810 | || (mips_opts.arch == CPU_R3900 && (pinfo & INSN_MULT))) |
252b5132 RH |
1811 | && (mips_optimize == 0 |
1812 | || (pinfo & INSN_WRITE_HI))) | |
1813 | nops += 2; | |
1814 | /* Most mips16 branch insns don't have a delay slot. | |
1815 | If a read from HI is immediately followed by a branch | |
1816 | to a write to HI we have a read followed by a write | |
1817 | less than 2 insns away. We assume the target of | |
1818 | a branch might be a write to HI, and insert a nop | |
bdaaa2e1 | 1819 | between a read and an immediately following branch. */ |
252b5132 RH |
1820 | else if (mips_opts.mips16 |
1821 | && (mips_optimize == 0 | |
1822 | || (pinfo & MIPS16_INSN_BRANCH))) | |
f9419b05 | 1823 | ++nops; |
252b5132 RH |
1824 | } |
1825 | ||
1826 | /* If the previous instruction was in a noreorder section, then | |
1827 | we don't want to insert the nop after all. */ | |
bdaaa2e1 | 1828 | /* Itbl support may require additional care here. */ |
252b5132 RH |
1829 | if (prev_insn_unreordered) |
1830 | nops = 0; | |
1831 | ||
1832 | /* There are two cases which require two intervening | |
1833 | instructions: 1) setting the condition codes using a move to | |
1834 | coprocessor instruction which requires a general coprocessor | |
1835 | delay and then reading the condition codes 2) reading the HI | |
1836 | or LO register and then writing to it (except on processors | |
1837 | which have interlocks). If we are not already emitting a NOP | |
1838 | instruction, we must check for these cases compared to the | |
1839 | instruction previous to the previous instruction. */ | |
1840 | if ((! mips_opts.mips16 | |
252b5132 RH |
1841 | && (prev_prev_insn.insn_mo->pinfo & INSN_COPROC_MOVE_DELAY) |
1842 | && (prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE) | |
1843 | && (pinfo & INSN_READ_COND_CODE) | |
1844 | && ! cop_interlocks) | |
1845 | || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_LO) | |
1846 | && (pinfo & INSN_WRITE_LO) | |
1847 | && ! (hilo_interlocks | |
048cdf86 | 1848 | || (mips_opts.arch == CPU_R3900 && (pinfo & INSN_MULT)))) |
252b5132 RH |
1849 | || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI) |
1850 | && (pinfo & INSN_WRITE_HI) | |
1851 | && ! (hilo_interlocks | |
048cdf86 | 1852 | || (mips_opts.arch == CPU_R3900 && (pinfo & INSN_MULT))))) |
252b5132 RH |
1853 | prev_prev_nop = 1; |
1854 | else | |
1855 | prev_prev_nop = 0; | |
1856 | ||
1857 | if (prev_prev_insn_unreordered) | |
1858 | prev_prev_nop = 0; | |
1859 | ||
1860 | if (prev_prev_nop && nops == 0) | |
1861 | ++nops; | |
1862 | ||
d766e8ec | 1863 | if (mips_fix_vr4120 && prev_insn.insn_mo->name) |
60b63b72 RS |
1864 | { |
1865 | /* We're out of bits in pinfo, so we must resort to string | |
1866 | ops here. Shortcuts are selected based on opcodes being | |
d766e8ec | 1867 | limited to the VR4120 instruction set. */ |
60b63b72 RS |
1868 | int min_nops = 0; |
1869 | const char *pn = prev_insn.insn_mo->name; | |
1870 | const char *tn = ip->insn_mo->name; | |
532c738a RS |
1871 | if (strncmp (pn, "macc", 4) == 0 |
1872 | || strncmp (pn, "dmacc", 5) == 0) | |
60b63b72 RS |
1873 | { |
1874 | /* Errata 21 - [D]DIV[U] after [D]MACC */ | |
1875 | if (strstr (tn, "div")) | |
532c738a | 1876 | min_nops = 1; |
60b63b72 | 1877 | |
532c738a RS |
1878 | /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU |
1879 | instruction is executed immediately after a MACC or | |
1880 | DMACC instruction, the result of [either instruction] | |
1881 | is incorrect." */ | |
1882 | if (strncmp (tn, "mult", 4) == 0 | |
1883 | || strncmp (tn, "dmult", 5) == 0) | |
1884 | min_nops = 1; | |
1885 | ||
1886 | /* Errata 23 - Continuous DMULT[U]/DMACC instructions. | |
1887 | Applies on top of VR4181A MD(1) errata. */ | |
1888 | if (pn[0] == 'd' && strncmp (tn, "dmacc", 5) == 0) | |
1889 | min_nops = 1; | |
60b63b72 RS |
1890 | |
1891 | /* Errata 24 - MT{LO,HI} after [D]MACC */ | |
1892 | if (strcmp (tn, "mtlo") == 0 | |
1893 | || strcmp (tn, "mthi") == 0) | |
532c738a | 1894 | min_nops = 1; |
60b63b72 | 1895 | } |
532c738a RS |
1896 | else if (strncmp (pn, "dmult", 5) == 0 |
1897 | && (strncmp (tn, "dmult", 5) == 0 | |
1898 | || strncmp (tn, "dmacc", 5) == 0)) | |
60b63b72 RS |
1899 | { |
1900 | /* Here is the rest of errata 23. */ | |
1901 | min_nops = 1; | |
1902 | } | |
532c738a RS |
1903 | else if ((strncmp (pn, "dmult", 5) == 0 || strstr (pn, "div")) |
1904 | && (strncmp (tn, "macc", 4) == 0 | |
1905 | || strncmp (tn, "dmacc", 5) == 0)) | |
1906 | { | |
1907 | /* VR4181A errata MD(4): "If a MACC or DMACC instruction is | |
1908 | executed immediately after a DMULT, DMULTU, DIV, DIVU, | |
1909 | DDIV or DDIVU instruction, the result of the MACC or | |
1910 | DMACC instruction is incorrect.". This partly overlaps | |
1911 | the workaround for errata 23. */ | |
1912 | min_nops = 1; | |
1913 | } | |
60b63b72 RS |
1914 | if (nops < min_nops) |
1915 | nops = min_nops; | |
1916 | } | |
1917 | ||
252b5132 RH |
1918 | /* If we are being given a nop instruction, don't bother with |
1919 | one of the nops we would otherwise output. This will only | |
1920 | happen when a nop instruction is used with mips_optimize set | |
1921 | to 0. */ | |
1922 | if (nops > 0 | |
1923 | && ! mips_opts.noreorder | |
156c2f8b | 1924 | && ip->insn_opcode == (unsigned) (mips_opts.mips16 ? 0x6500 : 0)) |
252b5132 RH |
1925 | --nops; |
1926 | ||
1927 | /* Now emit the right number of NOP instructions. */ | |
1928 | if (nops > 0 && ! mips_opts.noreorder) | |
1929 | { | |
1930 | fragS *old_frag; | |
1931 | unsigned long old_frag_offset; | |
1932 | int i; | |
1933 | struct insn_label_list *l; | |
1934 | ||
1935 | old_frag = frag_now; | |
1936 | old_frag_offset = frag_now_fix (); | |
1937 | ||
1938 | for (i = 0; i < nops; i++) | |
1939 | emit_nop (); | |
1940 | ||
1941 | if (listing) | |
1942 | { | |
1943 | listing_prev_line (); | |
1944 | /* We may be at the start of a variant frag. In case we | |
1945 | are, make sure there is enough space for the frag | |
1946 | after the frags created by listing_prev_line. The | |
1947 | argument to frag_grow here must be at least as large | |
1948 | as the argument to all other calls to frag_grow in | |
1949 | this file. We don't have to worry about being in the | |
1950 | middle of a variant frag, because the variants insert | |
1951 | all needed nop instructions themselves. */ | |
1952 | frag_grow (40); | |
1953 | } | |
1954 | ||
1955 | for (l = insn_labels; l != NULL; l = l->next) | |
1956 | { | |
98aa84af AM |
1957 | valueT val; |
1958 | ||
252b5132 | 1959 | assert (S_GET_SEGMENT (l->label) == now_seg); |
49309057 | 1960 | symbol_set_frag (l->label, frag_now); |
98aa84af | 1961 | val = (valueT) frag_now_fix (); |
252b5132 RH |
1962 | /* mips16 text labels are stored as odd. */ |
1963 | if (mips_opts.mips16) | |
f9419b05 | 1964 | ++val; |
98aa84af | 1965 | S_SET_VALUE (l->label, val); |
252b5132 RH |
1966 | } |
1967 | ||
1968 | #ifndef NO_ECOFF_DEBUGGING | |
1969 | if (ECOFF_DEBUGGING) | |
1970 | ecoff_fix_loc (old_frag, old_frag_offset); | |
1971 | #endif | |
1972 | } | |
1973 | else if (prev_nop_frag != NULL) | |
1974 | { | |
1975 | /* We have a frag holding nops we may be able to remove. If | |
1976 | we don't need any nops, we can decrease the size of | |
1977 | prev_nop_frag by the size of one instruction. If we do | |
bdaaa2e1 | 1978 | need some nops, we count them in prev_nops_required. */ |
252b5132 RH |
1979 | if (prev_nop_frag_since == 0) |
1980 | { | |
1981 | if (nops == 0) | |
1982 | { | |
1983 | prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4; | |
1984 | --prev_nop_frag_holds; | |
1985 | } | |
1986 | else | |
1987 | prev_nop_frag_required += nops; | |
1988 | } | |
1989 | else | |
1990 | { | |
1991 | if (prev_prev_nop == 0) | |
1992 | { | |
1993 | prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4; | |
1994 | --prev_nop_frag_holds; | |
1995 | } | |
1996 | else | |
1997 | ++prev_nop_frag_required; | |
1998 | } | |
1999 | ||
2000 | if (prev_nop_frag_holds <= prev_nop_frag_required) | |
2001 | prev_nop_frag = NULL; | |
2002 | ||
2003 | ++prev_nop_frag_since; | |
2004 | ||
2005 | /* Sanity check: by the time we reach the second instruction | |
2006 | after prev_nop_frag, we should have used up all the nops | |
2007 | one way or another. */ | |
2008 | assert (prev_nop_frag_since <= 1 || prev_nop_frag == NULL); | |
2009 | } | |
2010 | } | |
2011 | ||
895921c9 MR |
2012 | /* Record the frag type before frag_var. */ |
2013 | if (prev_insn_frag) | |
2014 | prev_insn_frag_type = prev_insn_frag->fr_type; | |
2015 | ||
4d7206a2 | 2016 | if (address_expr |
0b25d3e6 | 2017 | && *reloc_type == BFD_RELOC_16_PCREL_S2 |
4a6a3df4 AO |
2018 | && (pinfo & INSN_UNCOND_BRANCH_DELAY || pinfo & INSN_COND_BRANCH_DELAY |
2019 | || pinfo & INSN_COND_BRANCH_LIKELY) | |
2020 | && mips_relax_branch | |
2021 | /* Don't try branch relaxation within .set nomacro, or within | |
2022 | .set noat if we use $at for PIC computations. If it turns | |
2023 | out that the branch was out-of-range, we'll get an error. */ | |
2024 | && !mips_opts.warn_about_macros | |
2025 | && !(mips_opts.noat && mips_pic != NO_PIC) | |
2026 | && !mips_opts.mips16) | |
2027 | { | |
895921c9 | 2028 | relaxed_branch = TRUE; |
4a6a3df4 AO |
2029 | f = frag_var (rs_machine_dependent, |
2030 | relaxed_branch_length | |
2031 | (NULL, NULL, | |
2032 | (pinfo & INSN_UNCOND_BRANCH_DELAY) ? -1 | |
2033 | : (pinfo & INSN_COND_BRANCH_LIKELY) ? 1 : 0), 4, | |
2034 | RELAX_BRANCH_ENCODE | |
af6ae2ad | 2035 | (pinfo & INSN_UNCOND_BRANCH_DELAY, |
4a6a3df4 AO |
2036 | pinfo & INSN_COND_BRANCH_LIKELY, |
2037 | pinfo & INSN_WRITE_GPR_31, | |
2038 | 0), | |
2039 | address_expr->X_add_symbol, | |
2040 | address_expr->X_add_number, | |
2041 | 0); | |
2042 | *reloc_type = BFD_RELOC_UNUSED; | |
2043 | } | |
2044 | else if (*reloc_type > BFD_RELOC_UNUSED) | |
252b5132 RH |
2045 | { |
2046 | /* We need to set up a variant frag. */ | |
2047 | assert (mips_opts.mips16 && address_expr != NULL); | |
2048 | f = frag_var (rs_machine_dependent, 4, 0, | |
f6688943 | 2049 | RELAX_MIPS16_ENCODE (*reloc_type - BFD_RELOC_UNUSED, |
252b5132 RH |
2050 | mips16_small, mips16_ext, |
2051 | (prev_pinfo | |
2052 | & INSN_UNCOND_BRANCH_DELAY), | |
f6688943 | 2053 | (*prev_insn_reloc_type |
252b5132 | 2054 | == BFD_RELOC_MIPS16_JMP)), |
c4e7957c | 2055 | make_expr_symbol (address_expr), 0, NULL); |
252b5132 | 2056 | } |
252b5132 RH |
2057 | else if (mips_opts.mips16 |
2058 | && ! ip->use_extend | |
f6688943 | 2059 | && *reloc_type != BFD_RELOC_MIPS16_JMP) |
252b5132 RH |
2060 | { |
2061 | /* Make sure there is enough room to swap this instruction with | |
2062 | a following jump instruction. */ | |
2063 | frag_grow (6); | |
2064 | f = frag_more (2); | |
2065 | } | |
2066 | else | |
2067 | { | |
2068 | if (mips_opts.mips16 | |
2069 | && mips_opts.noreorder | |
2070 | && (prev_pinfo & INSN_UNCOND_BRANCH_DELAY) != 0) | |
2071 | as_warn (_("extended instruction in delay slot")); | |
2072 | ||
4d7206a2 RS |
2073 | if (mips_relax.sequence) |
2074 | { | |
2075 | /* If we've reached the end of this frag, turn it into a variant | |
2076 | frag and record the information for the instructions we've | |
2077 | written so far. */ | |
2078 | if (frag_room () < 4) | |
2079 | relax_close_frag (); | |
2080 | mips_relax.sizes[mips_relax.sequence - 1] += 4; | |
2081 | } | |
2082 | ||
584892a6 RS |
2083 | if (mips_relax.sequence != 2) |
2084 | mips_macro_warning.sizes[0] += 4; | |
2085 | if (mips_relax.sequence != 1) | |
2086 | mips_macro_warning.sizes[1] += 4; | |
2087 | ||
252b5132 RH |
2088 | f = frag_more (4); |
2089 | } | |
2090 | ||
f6688943 | 2091 | fixp[0] = fixp[1] = fixp[2] = NULL; |
01a3f561 | 2092 | if (address_expr != NULL && *reloc_type <= BFD_RELOC_UNUSED) |
252b5132 RH |
2093 | { |
2094 | if (address_expr->X_op == O_constant) | |
2095 | { | |
4db1a35d | 2096 | valueT tmp; |
f6688943 TS |
2097 | |
2098 | switch (*reloc_type) | |
252b5132 RH |
2099 | { |
2100 | case BFD_RELOC_32: | |
2101 | ip->insn_opcode |= address_expr->X_add_number; | |
2102 | break; | |
2103 | ||
f6688943 | 2104 | case BFD_RELOC_MIPS_HIGHEST: |
6344efa4 AM |
2105 | tmp = (address_expr->X_add_number |
2106 | + ((valueT) 0x8000 << 32) + 0x80008000) >> 16; | |
f6688943 TS |
2107 | tmp >>= 16; |
2108 | ip->insn_opcode |= (tmp >> 16) & 0xffff; | |
2109 | break; | |
2110 | ||
2111 | case BFD_RELOC_MIPS_HIGHER: | |
2112 | tmp = (address_expr->X_add_number + 0x80008000) >> 16; | |
2113 | ip->insn_opcode |= (tmp >> 16) & 0xffff; | |
2114 | break; | |
2115 | ||
2116 | case BFD_RELOC_HI16_S: | |
2117 | ip->insn_opcode |= ((address_expr->X_add_number + 0x8000) | |
2118 | >> 16) & 0xffff; | |
2119 | break; | |
2120 | ||
2121 | case BFD_RELOC_HI16: | |
2122 | ip->insn_opcode |= (address_expr->X_add_number >> 16) & 0xffff; | |
2123 | break; | |
2124 | ||
01a3f561 | 2125 | case BFD_RELOC_UNUSED: |
252b5132 | 2126 | case BFD_RELOC_LO16: |
ed6fb7bd | 2127 | case BFD_RELOC_MIPS_GOT_DISP: |
252b5132 RH |
2128 | ip->insn_opcode |= address_expr->X_add_number & 0xffff; |
2129 | break; | |
2130 | ||
2131 | case BFD_RELOC_MIPS_JMP: | |
2132 | if ((address_expr->X_add_number & 3) != 0) | |
2133 | as_bad (_("jump to misaligned address (0x%lx)"), | |
2134 | (unsigned long) address_expr->X_add_number); | |
f3c0ec86 | 2135 | if (address_expr->X_add_number & ~0xfffffff) |
7496292d TS |
2136 | as_bad (_("jump address range overflow (0x%lx)"), |
2137 | (unsigned long) address_expr->X_add_number); | |
252b5132 RH |
2138 | ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0x3ffffff; |
2139 | break; | |
2140 | ||
2141 | case BFD_RELOC_MIPS16_JMP: | |
2142 | if ((address_expr->X_add_number & 3) != 0) | |
2143 | as_bad (_("jump to misaligned address (0x%lx)"), | |
2144 | (unsigned long) address_expr->X_add_number); | |
f3c0ec86 | 2145 | if (address_expr->X_add_number & ~0xfffffff) |
7496292d TS |
2146 | as_bad (_("jump address range overflow (0x%lx)"), |
2147 | (unsigned long) address_expr->X_add_number); | |
252b5132 RH |
2148 | ip->insn_opcode |= |
2149 | (((address_expr->X_add_number & 0x7c0000) << 3) | |
2150 | | ((address_expr->X_add_number & 0xf800000) >> 7) | |
2151 | | ((address_expr->X_add_number & 0x3fffc) >> 2)); | |
2152 | break; | |
2153 | ||
252b5132 RH |
2154 | case BFD_RELOC_16_PCREL_S2: |
2155 | goto need_reloc; | |
2156 | ||
2157 | default: | |
2158 | internalError (); | |
2159 | } | |
2160 | } | |
01a3f561 | 2161 | else if (*reloc_type < BFD_RELOC_UNUSED) |
252b5132 | 2162 | need_reloc: |
4d7206a2 RS |
2163 | { |
2164 | reloc_howto_type *howto; | |
2165 | int i; | |
34ce925e | 2166 | |
4d7206a2 RS |
2167 | /* In a compound relocation, it is the final (outermost) |
2168 | operator that determines the relocated field. */ | |
2169 | for (i = 1; i < 3; i++) | |
2170 | if (reloc_type[i] == BFD_RELOC_UNUSED) | |
2171 | break; | |
34ce925e | 2172 | |
4d7206a2 RS |
2173 | howto = bfd_reloc_type_lookup (stdoutput, reloc_type[i - 1]); |
2174 | fixp[0] = fix_new_exp (frag_now, f - frag_now->fr_literal, | |
2175 | bfd_get_reloc_size(howto), | |
2176 | address_expr, | |
2177 | reloc_type[0] == BFD_RELOC_16_PCREL_S2, | |
2178 | reloc_type[0]); | |
2179 | ||
2180 | /* These relocations can have an addend that won't fit in | |
2181 | 4 octets for 64bit assembly. */ | |
2182 | if (HAVE_64BIT_GPRS | |
2183 | && ! howto->partial_inplace | |
2184 | && (reloc_type[0] == BFD_RELOC_16 | |
2185 | || reloc_type[0] == BFD_RELOC_32 | |
2186 | || reloc_type[0] == BFD_RELOC_MIPS_JMP | |
2187 | || reloc_type[0] == BFD_RELOC_HI16_S | |
2188 | || reloc_type[0] == BFD_RELOC_LO16 | |
2189 | || reloc_type[0] == BFD_RELOC_GPREL16 | |
2190 | || reloc_type[0] == BFD_RELOC_MIPS_LITERAL | |
2191 | || reloc_type[0] == BFD_RELOC_GPREL32 | |
2192 | || reloc_type[0] == BFD_RELOC_64 | |
2193 | || reloc_type[0] == BFD_RELOC_CTOR | |
2194 | || reloc_type[0] == BFD_RELOC_MIPS_SUB | |
2195 | || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST | |
2196 | || reloc_type[0] == BFD_RELOC_MIPS_HIGHER | |
2197 | || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP | |
2198 | || reloc_type[0] == BFD_RELOC_MIPS_REL16 | |
d6f16593 MR |
2199 | || reloc_type[0] == BFD_RELOC_MIPS_RELGOT |
2200 | || reloc_type[0] == BFD_RELOC_MIPS16_GPREL | |
2201 | || reloc_type[0] == BFD_RELOC_MIPS16_HI16_S | |
2202 | || reloc_type[0] == BFD_RELOC_MIPS16_LO16)) | |
4d7206a2 RS |
2203 | fixp[0]->fx_no_overflow = 1; |
2204 | ||
2205 | if (mips_relax.sequence) | |
2206 | { | |
2207 | if (mips_relax.first_fixup == 0) | |
2208 | mips_relax.first_fixup = fixp[0]; | |
2209 | } | |
2210 | else if (reloc_needs_lo_p (*reloc_type)) | |
2211 | { | |
2212 | struct mips_hi_fixup *hi_fixup; | |
252b5132 | 2213 | |
4d7206a2 RS |
2214 | /* Reuse the last entry if it already has a matching %lo. */ |
2215 | hi_fixup = mips_hi_fixup_list; | |
2216 | if (hi_fixup == 0 | |
2217 | || !fixup_has_matching_lo_p (hi_fixup->fixp)) | |
2218 | { | |
2219 | hi_fixup = ((struct mips_hi_fixup *) | |
2220 | xmalloc (sizeof (struct mips_hi_fixup))); | |
2221 | hi_fixup->next = mips_hi_fixup_list; | |
2222 | mips_hi_fixup_list = hi_fixup; | |
252b5132 | 2223 | } |
4d7206a2 RS |
2224 | hi_fixup->fixp = fixp[0]; |
2225 | hi_fixup->seg = now_seg; | |
2226 | } | |
f6688943 | 2227 | |
4d7206a2 RS |
2228 | /* Add fixups for the second and third relocations, if given. |
2229 | Note that the ABI allows the second relocation to be | |
2230 | against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the | |
2231 | moment we only use RSS_UNDEF, but we could add support | |
2232 | for the others if it ever becomes necessary. */ | |
2233 | for (i = 1; i < 3; i++) | |
2234 | if (reloc_type[i] != BFD_RELOC_UNUSED) | |
2235 | { | |
6e1304d8 RS |
2236 | fixp[i] = fix_new (frag_now, fixp[0]->fx_where, |
2237 | fixp[0]->fx_size, NULL, 0, | |
2238 | FALSE, reloc_type[i]); | |
b1dca8ee RS |
2239 | |
2240 | /* Use fx_tcbit to mark compound relocs. */ | |
2241 | fixp[0]->fx_tcbit = 1; | |
2242 | fixp[i]->fx_tcbit = 1; | |
4d7206a2 | 2243 | } |
252b5132 RH |
2244 | } |
2245 | } | |
2246 | ||
2247 | if (! mips_opts.mips16) | |
c5dd6aab DJ |
2248 | { |
2249 | md_number_to_chars (f, ip->insn_opcode, 4); | |
2250 | #ifdef OBJ_ELF | |
2251 | dwarf2_emit_insn (4); | |
2252 | #endif | |
2253 | } | |
f6688943 | 2254 | else if (*reloc_type == BFD_RELOC_MIPS16_JMP) |
252b5132 RH |
2255 | { |
2256 | md_number_to_chars (f, ip->insn_opcode >> 16, 2); | |
2257 | md_number_to_chars (f + 2, ip->insn_opcode & 0xffff, 2); | |
c5dd6aab | 2258 | #ifdef OBJ_ELF |
20e56c33 RS |
2259 | /* The value passed to dwarf2_emit_insn is the distance between |
2260 | the end of the current instruction and the address that should | |
2261 | be recorded in the debug tables. Since we want to use ISA-encoded | |
2262 | addresses in MIPS16 debug info, the value is one byte less than | |
2263 | the real instruction length. */ | |
2264 | dwarf2_emit_insn (3); | |
c5dd6aab | 2265 | #endif |
252b5132 RH |
2266 | } |
2267 | else | |
2268 | { | |
2269 | if (ip->use_extend) | |
2270 | { | |
2271 | md_number_to_chars (f, 0xf000 | ip->extend, 2); | |
2272 | f += 2; | |
2273 | } | |
2274 | md_number_to_chars (f, ip->insn_opcode, 2); | |
c5dd6aab | 2275 | #ifdef OBJ_ELF |
20e56c33 | 2276 | dwarf2_emit_insn (ip->use_extend ? 3 : 1); |
c5dd6aab | 2277 | #endif |
252b5132 RH |
2278 | } |
2279 | ||
2280 | /* Update the register mask information. */ | |
2281 | if (! mips_opts.mips16) | |
2282 | { | |
2283 | if (pinfo & INSN_WRITE_GPR_D) | |
2284 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD); | |
2285 | if ((pinfo & (INSN_WRITE_GPR_T | INSN_READ_GPR_T)) != 0) | |
2286 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT); | |
2287 | if (pinfo & INSN_READ_GPR_S) | |
2288 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS); | |
2289 | if (pinfo & INSN_WRITE_GPR_31) | |
f9419b05 | 2290 | mips_gprmask |= 1 << RA; |
252b5132 RH |
2291 | if (pinfo & INSN_WRITE_FPR_D) |
2292 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FD) & OP_MASK_FD); | |
2293 | if ((pinfo & (INSN_WRITE_FPR_S | INSN_READ_FPR_S)) != 0) | |
2294 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS); | |
2295 | if ((pinfo & (INSN_WRITE_FPR_T | INSN_READ_FPR_T)) != 0) | |
2296 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT); | |
2297 | if ((pinfo & INSN_READ_FPR_R) != 0) | |
2298 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FR) & OP_MASK_FR); | |
2299 | if (pinfo & INSN_COP) | |
2300 | { | |
bdaaa2e1 KH |
2301 | /* We don't keep enough information to sort these cases out. |
2302 | The itbl support does keep this information however, although | |
2303 | we currently don't support itbl fprmats as part of the cop | |
2304 | instruction. May want to add this support in the future. */ | |
252b5132 RH |
2305 | } |
2306 | /* Never set the bit for $0, which is always zero. */ | |
beae10d5 | 2307 | mips_gprmask &= ~1 << 0; |
252b5132 RH |
2308 | } |
2309 | else | |
2310 | { | |
2311 | if (pinfo & (MIPS16_INSN_WRITE_X | MIPS16_INSN_READ_X)) | |
2312 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RX) | |
2313 | & MIPS16OP_MASK_RX); | |
2314 | if (pinfo & (MIPS16_INSN_WRITE_Y | MIPS16_INSN_READ_Y)) | |
2315 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RY) | |
2316 | & MIPS16OP_MASK_RY); | |
2317 | if (pinfo & MIPS16_INSN_WRITE_Z) | |
2318 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RZ) | |
2319 | & MIPS16OP_MASK_RZ); | |
2320 | if (pinfo & (MIPS16_INSN_WRITE_T | MIPS16_INSN_READ_T)) | |
2321 | mips_gprmask |= 1 << TREG; | |
2322 | if (pinfo & (MIPS16_INSN_WRITE_SP | MIPS16_INSN_READ_SP)) | |
2323 | mips_gprmask |= 1 << SP; | |
2324 | if (pinfo & (MIPS16_INSN_WRITE_31 | MIPS16_INSN_READ_31)) | |
2325 | mips_gprmask |= 1 << RA; | |
2326 | if (pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
2327 | mips_gprmask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode); | |
2328 | if (pinfo & MIPS16_INSN_READ_Z) | |
2329 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z) | |
2330 | & MIPS16OP_MASK_MOVE32Z); | |
2331 | if (pinfo & MIPS16_INSN_READ_GPR_X) | |
2332 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_REGR32) | |
2333 | & MIPS16OP_MASK_REGR32); | |
2334 | } | |
2335 | ||
4d7206a2 | 2336 | if (mips_relax.sequence != 2 && !mips_opts.noreorder) |
252b5132 RH |
2337 | { |
2338 | /* Filling the branch delay slot is more complex. We try to | |
2339 | switch the branch with the previous instruction, which we can | |
2340 | do if the previous instruction does not set up a condition | |
2341 | that the branch tests and if the branch is not itself the | |
2342 | target of any branch. */ | |
2343 | if ((pinfo & INSN_UNCOND_BRANCH_DELAY) | |
2344 | || (pinfo & INSN_COND_BRANCH_DELAY)) | |
2345 | { | |
2346 | if (mips_optimize < 2 | |
2347 | /* If we have seen .set volatile or .set nomove, don't | |
2348 | optimize. */ | |
2349 | || mips_opts.nomove != 0 | |
2350 | /* If we had to emit any NOP instructions, then we | |
2351 | already know we can not swap. */ | |
2352 | || nops != 0 | |
2353 | /* If we don't even know the previous insn, we can not | |
bdaaa2e1 | 2354 | swap. */ |
252b5132 RH |
2355 | || ! prev_insn_valid |
2356 | /* If the previous insn is already in a branch delay | |
2357 | slot, then we can not swap. */ | |
2358 | || prev_insn_is_delay_slot | |
2359 | /* If the previous previous insn was in a .set | |
2360 | noreorder, we can't swap. Actually, the MIPS | |
2361 | assembler will swap in this situation. However, gcc | |
2362 | configured -with-gnu-as will generate code like | |
2363 | .set noreorder | |
2364 | lw $4,XXX | |
2365 | .set reorder | |
2366 | INSN | |
2367 | bne $4,$0,foo | |
2368 | in which we can not swap the bne and INSN. If gcc is | |
2369 | not configured -with-gnu-as, it does not output the | |
2370 | .set pseudo-ops. We don't have to check | |
2371 | prev_insn_unreordered, because prev_insn_valid will | |
2372 | be 0 in that case. We don't want to use | |
2373 | prev_prev_insn_valid, because we do want to be able | |
2374 | to swap at the start of a function. */ | |
2375 | || prev_prev_insn_unreordered | |
2376 | /* If the branch is itself the target of a branch, we | |
2377 | can not swap. We cheat on this; all we check for is | |
2378 | whether there is a label on this instruction. If | |
2379 | there are any branches to anything other than a | |
2380 | label, users must use .set noreorder. */ | |
2381 | || insn_labels != NULL | |
895921c9 MR |
2382 | /* If the previous instruction is in a variant frag |
2383 | other than this branch's one, we cannot do the swap. | |
2384 | This does not apply to the mips16, which uses variant | |
2385 | frags for different purposes. */ | |
252b5132 | 2386 | || (! mips_opts.mips16 |
895921c9 | 2387 | && prev_insn_frag_type == rs_machine_dependent) |
252b5132 RH |
2388 | /* If the branch reads the condition codes, we don't |
2389 | even try to swap, because in the sequence | |
2390 | ctc1 $X,$31 | |
2391 | INSN | |
2392 | INSN | |
2393 | bc1t LABEL | |
2394 | we can not swap, and I don't feel like handling that | |
2395 | case. */ | |
2396 | || (! mips_opts.mips16 | |
81912461 ILT |
2397 | && (pinfo & INSN_READ_COND_CODE) |
2398 | && ! cop_interlocks) | |
252b5132 | 2399 | /* We can not swap with an instruction that requires a |
67c1ffbe | 2400 | delay slot, because the target of the branch might |
252b5132 RH |
2401 | interfere with that instruction. */ |
2402 | || (! mips_opts.mips16 | |
252b5132 | 2403 | && (prev_pinfo |
bdaaa2e1 | 2404 | /* Itbl support may require additional care here. */ |
252b5132 RH |
2405 | & (INSN_LOAD_COPROC_DELAY |
2406 | | INSN_COPROC_MOVE_DELAY | |
81912461 ILT |
2407 | | INSN_WRITE_COND_CODE)) |
2408 | && ! cop_interlocks) | |
252b5132 | 2409 | || (! (hilo_interlocks |
048cdf86 | 2410 | || (mips_opts.arch == CPU_R3900 && (pinfo & INSN_MULT))) |
252b5132 RH |
2411 | && (prev_pinfo |
2412 | & (INSN_READ_LO | |
2413 | | INSN_READ_HI))) | |
2414 | || (! mips_opts.mips16 | |
81912461 ILT |
2415 | && (prev_pinfo & INSN_LOAD_MEMORY_DELAY) |
2416 | && ! gpr_interlocks) | |
252b5132 | 2417 | || (! mips_opts.mips16 |
bdaaa2e1 | 2418 | /* Itbl support may require additional care here. */ |
81912461 ILT |
2419 | && (prev_pinfo & INSN_COPROC_MEMORY_DELAY) |
2420 | && ! cop_mem_interlocks) | |
252b5132 RH |
2421 | /* We can not swap with a branch instruction. */ |
2422 | || (prev_pinfo | |
2423 | & (INSN_UNCOND_BRANCH_DELAY | |
2424 | | INSN_COND_BRANCH_DELAY | |
2425 | | INSN_COND_BRANCH_LIKELY)) | |
2426 | /* We do not swap with a trap instruction, since it | |
2427 | complicates trap handlers to have the trap | |
2428 | instruction be in a delay slot. */ | |
2429 | || (prev_pinfo & INSN_TRAP) | |
2430 | /* If the branch reads a register that the previous | |
2431 | instruction sets, we can not swap. */ | |
2432 | || (! mips_opts.mips16 | |
2433 | && (prev_pinfo & INSN_WRITE_GPR_T) | |
2434 | && insn_uses_reg (ip, | |
2435 | ((prev_insn.insn_opcode >> OP_SH_RT) | |
2436 | & OP_MASK_RT), | |
2437 | MIPS_GR_REG)) | |
2438 | || (! mips_opts.mips16 | |
2439 | && (prev_pinfo & INSN_WRITE_GPR_D) | |
2440 | && insn_uses_reg (ip, | |
2441 | ((prev_insn.insn_opcode >> OP_SH_RD) | |
2442 | & OP_MASK_RD), | |
2443 | MIPS_GR_REG)) | |
2444 | || (mips_opts.mips16 | |
2445 | && (((prev_pinfo & MIPS16_INSN_WRITE_X) | |
2446 | && insn_uses_reg (ip, | |
2447 | ((prev_insn.insn_opcode | |
2448 | >> MIPS16OP_SH_RX) | |
2449 | & MIPS16OP_MASK_RX), | |
2450 | MIPS16_REG)) | |
2451 | || ((prev_pinfo & MIPS16_INSN_WRITE_Y) | |
2452 | && insn_uses_reg (ip, | |
2453 | ((prev_insn.insn_opcode | |
2454 | >> MIPS16OP_SH_RY) | |
2455 | & MIPS16OP_MASK_RY), | |
2456 | MIPS16_REG)) | |
2457 | || ((prev_pinfo & MIPS16_INSN_WRITE_Z) | |
2458 | && insn_uses_reg (ip, | |
2459 | ((prev_insn.insn_opcode | |
2460 | >> MIPS16OP_SH_RZ) | |
2461 | & MIPS16OP_MASK_RZ), | |
2462 | MIPS16_REG)) | |
2463 | || ((prev_pinfo & MIPS16_INSN_WRITE_T) | |
2464 | && insn_uses_reg (ip, TREG, MIPS_GR_REG)) | |
2465 | || ((prev_pinfo & MIPS16_INSN_WRITE_31) | |
2466 | && insn_uses_reg (ip, RA, MIPS_GR_REG)) | |
2467 | || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
2468 | && insn_uses_reg (ip, | |
2469 | MIPS16OP_EXTRACT_REG32R (prev_insn. | |
2470 | insn_opcode), | |
2471 | MIPS_GR_REG)))) | |
2472 | /* If the branch writes a register that the previous | |
2473 | instruction sets, we can not swap (we know that | |
2474 | branches write only to RD or to $31). */ | |
2475 | || (! mips_opts.mips16 | |
2476 | && (prev_pinfo & INSN_WRITE_GPR_T) | |
2477 | && (((pinfo & INSN_WRITE_GPR_D) | |
2478 | && (((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT) | |
2479 | == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD))) | |
2480 | || ((pinfo & INSN_WRITE_GPR_31) | |
2481 | && (((prev_insn.insn_opcode >> OP_SH_RT) | |
2482 | & OP_MASK_RT) | |
f9419b05 | 2483 | == RA)))) |
252b5132 RH |
2484 | || (! mips_opts.mips16 |
2485 | && (prev_pinfo & INSN_WRITE_GPR_D) | |
2486 | && (((pinfo & INSN_WRITE_GPR_D) | |
2487 | && (((prev_insn.insn_opcode >> OP_SH_RD) & OP_MASK_RD) | |
2488 | == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD))) | |
2489 | || ((pinfo & INSN_WRITE_GPR_31) | |
2490 | && (((prev_insn.insn_opcode >> OP_SH_RD) | |
2491 | & OP_MASK_RD) | |
f9419b05 | 2492 | == RA)))) |
252b5132 RH |
2493 | || (mips_opts.mips16 |
2494 | && (pinfo & MIPS16_INSN_WRITE_31) | |
2495 | && ((prev_pinfo & MIPS16_INSN_WRITE_31) | |
2496 | || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
2497 | && (MIPS16OP_EXTRACT_REG32R (prev_insn.insn_opcode) | |
2498 | == RA)))) | |
2499 | /* If the branch writes a register that the previous | |
2500 | instruction reads, we can not swap (we know that | |
2501 | branches only write to RD or to $31). */ | |
2502 | || (! mips_opts.mips16 | |
2503 | && (pinfo & INSN_WRITE_GPR_D) | |
2504 | && insn_uses_reg (&prev_insn, | |
2505 | ((ip->insn_opcode >> OP_SH_RD) | |
2506 | & OP_MASK_RD), | |
2507 | MIPS_GR_REG)) | |
2508 | || (! mips_opts.mips16 | |
2509 | && (pinfo & INSN_WRITE_GPR_31) | |
f9419b05 | 2510 | && insn_uses_reg (&prev_insn, RA, MIPS_GR_REG)) |
252b5132 RH |
2511 | || (mips_opts.mips16 |
2512 | && (pinfo & MIPS16_INSN_WRITE_31) | |
2513 | && insn_uses_reg (&prev_insn, RA, MIPS_GR_REG)) | |
252b5132 RH |
2514 | /* If the previous previous instruction has a load |
2515 | delay, and sets a register that the branch reads, we | |
2516 | can not swap. */ | |
2517 | || (! mips_opts.mips16 | |
bdaaa2e1 | 2518 | /* Itbl support may require additional care here. */ |
81912461 ILT |
2519 | && (((prev_prev_insn.insn_mo->pinfo & INSN_LOAD_COPROC_DELAY) |
2520 | && ! cop_interlocks) | |
2521 | || ((prev_prev_insn.insn_mo->pinfo | |
2522 | & INSN_LOAD_MEMORY_DELAY) | |
2523 | && ! gpr_interlocks)) | |
252b5132 RH |
2524 | && insn_uses_reg (ip, |
2525 | ((prev_prev_insn.insn_opcode >> OP_SH_RT) | |
2526 | & OP_MASK_RT), | |
2527 | MIPS_GR_REG)) | |
2528 | /* If one instruction sets a condition code and the | |
2529 | other one uses a condition code, we can not swap. */ | |
2530 | || ((pinfo & INSN_READ_COND_CODE) | |
2531 | && (prev_pinfo & INSN_WRITE_COND_CODE)) | |
2532 | || ((pinfo & INSN_WRITE_COND_CODE) | |
2533 | && (prev_pinfo & INSN_READ_COND_CODE)) | |
2534 | /* If the previous instruction uses the PC, we can not | |
2535 | swap. */ | |
2536 | || (mips_opts.mips16 | |
2537 | && (prev_pinfo & MIPS16_INSN_READ_PC)) | |
2538 | /* If the previous instruction was extended, we can not | |
2539 | swap. */ | |
2540 | || (mips_opts.mips16 && prev_insn_extended) | |
2541 | /* If the previous instruction had a fixup in mips16 | |
2542 | mode, we can not swap. This normally means that the | |
2543 | previous instruction was a 4 byte branch anyhow. */ | |
f6688943 | 2544 | || (mips_opts.mips16 && prev_insn_fixp[0]) |
bdaaa2e1 KH |
2545 | /* If the previous instruction is a sync, sync.l, or |
2546 | sync.p, we can not swap. */ | |
f173e82e | 2547 | || (prev_pinfo & INSN_SYNC)) |
252b5132 RH |
2548 | { |
2549 | /* We could do even better for unconditional branches to | |
2550 | portions of this object file; we could pick up the | |
2551 | instruction at the destination, put it in the delay | |
2552 | slot, and bump the destination address. */ | |
2553 | emit_nop (); | |
dd22970f ILT |
2554 | if (mips_relax.sequence) |
2555 | mips_relax.sizes[mips_relax.sequence - 1] += 4; | |
252b5132 RH |
2556 | /* Update the previous insn information. */ |
2557 | prev_prev_insn = *ip; | |
2558 | prev_insn.insn_mo = &dummy_opcode; | |
2559 | } | |
2560 | else | |
2561 | { | |
2562 | /* It looks like we can actually do the swap. */ | |
2563 | if (! mips_opts.mips16) | |
2564 | { | |
2565 | char *prev_f; | |
2566 | char temp[4]; | |
2567 | ||
2568 | prev_f = prev_insn_frag->fr_literal + prev_insn_where; | |
895921c9 MR |
2569 | if (!relaxed_branch) |
2570 | { | |
2571 | /* If this is not a relaxed branch, then just | |
2572 | swap the instructions. */ | |
2573 | memcpy (temp, prev_f, 4); | |
2574 | memcpy (prev_f, f, 4); | |
2575 | memcpy (f, temp, 4); | |
2576 | } | |
2577 | else | |
2578 | { | |
2579 | /* If this is a relaxed branch, then we move the | |
2580 | instruction to be placed in the delay slot to | |
2581 | the current frag, shrinking the fixed part of | |
2582 | the originating frag. If the branch occupies | |
2583 | the tail of the latter, we move it backwards, | |
2584 | into the space freed by the moved instruction. */ | |
2585 | f = frag_more (4); | |
2586 | memcpy (f, prev_f, 4); | |
2587 | prev_insn_frag->fr_fix -= 4; | |
2588 | if (prev_insn_frag->fr_type == rs_machine_dependent) | |
2589 | memmove (prev_f, prev_f + 4, prev_insn_frag->fr_var); | |
2590 | } | |
2591 | ||
f6688943 TS |
2592 | if (prev_insn_fixp[0]) |
2593 | { | |
2594 | prev_insn_fixp[0]->fx_frag = frag_now; | |
2595 | prev_insn_fixp[0]->fx_where = f - frag_now->fr_literal; | |
2596 | } | |
2597 | if (prev_insn_fixp[1]) | |
2598 | { | |
2599 | prev_insn_fixp[1]->fx_frag = frag_now; | |
2600 | prev_insn_fixp[1]->fx_where = f - frag_now->fr_literal; | |
2601 | } | |
2602 | if (prev_insn_fixp[2]) | |
252b5132 | 2603 | { |
f6688943 TS |
2604 | prev_insn_fixp[2]->fx_frag = frag_now; |
2605 | prev_insn_fixp[2]->fx_where = f - frag_now->fr_literal; | |
252b5132 | 2606 | } |
f5040a92 AO |
2607 | if (prev_insn_fixp[0] && HAVE_NEWABI |
2608 | && prev_insn_frag != frag_now | |
2609 | && (prev_insn_fixp[0]->fx_r_type | |
2610 | == BFD_RELOC_MIPS_GOT_DISP | |
2611 | || (prev_insn_fixp[0]->fx_r_type | |
2612 | == BFD_RELOC_MIPS_CALL16))) | |
2613 | { | |
2614 | /* To avoid confusion in tc_gen_reloc, we must | |
2615 | ensure that this does not become a variant | |
2616 | frag. */ | |
2617 | force_new_frag = TRUE; | |
2618 | } | |
895921c9 MR |
2619 | |
2620 | if (!relaxed_branch) | |
f6688943 | 2621 | { |
895921c9 MR |
2622 | if (fixp[0]) |
2623 | { | |
2624 | fixp[0]->fx_frag = prev_insn_frag; | |
2625 | fixp[0]->fx_where = prev_insn_where; | |
2626 | } | |
2627 | if (fixp[1]) | |
2628 | { | |
2629 | fixp[1]->fx_frag = prev_insn_frag; | |
2630 | fixp[1]->fx_where = prev_insn_where; | |
2631 | } | |
2632 | if (fixp[2]) | |
2633 | { | |
2634 | fixp[2]->fx_frag = prev_insn_frag; | |
2635 | fixp[2]->fx_where = prev_insn_where; | |
2636 | } | |
f6688943 | 2637 | } |
895921c9 | 2638 | else if (prev_insn_frag->fr_type == rs_machine_dependent) |
f6688943 | 2639 | { |
895921c9 MR |
2640 | if (fixp[0]) |
2641 | fixp[0]->fx_where -= 4; | |
2642 | if (fixp[1]) | |
2643 | fixp[1]->fx_where -= 4; | |
2644 | if (fixp[2]) | |
2645 | fixp[2]->fx_where -= 4; | |
252b5132 RH |
2646 | } |
2647 | } | |
2648 | else | |
2649 | { | |
2650 | char *prev_f; | |
2651 | char temp[2]; | |
2652 | ||
f6688943 TS |
2653 | assert (prev_insn_fixp[0] == NULL); |
2654 | assert (prev_insn_fixp[1] == NULL); | |
2655 | assert (prev_insn_fixp[2] == NULL); | |
252b5132 RH |
2656 | prev_f = prev_insn_frag->fr_literal + prev_insn_where; |
2657 | memcpy (temp, prev_f, 2); | |
2658 | memcpy (prev_f, f, 2); | |
f6688943 | 2659 | if (*reloc_type != BFD_RELOC_MIPS16_JMP) |
252b5132 | 2660 | { |
f6688943 | 2661 | assert (*reloc_type == BFD_RELOC_UNUSED); |
252b5132 RH |
2662 | memcpy (f, temp, 2); |
2663 | } | |
2664 | else | |
2665 | { | |
2666 | memcpy (f, f + 2, 2); | |
2667 | memcpy (f + 2, temp, 2); | |
2668 | } | |
f6688943 TS |
2669 | if (fixp[0]) |
2670 | { | |
2671 | fixp[0]->fx_frag = prev_insn_frag; | |
2672 | fixp[0]->fx_where = prev_insn_where; | |
2673 | } | |
2674 | if (fixp[1]) | |
2675 | { | |
2676 | fixp[1]->fx_frag = prev_insn_frag; | |
2677 | fixp[1]->fx_where = prev_insn_where; | |
2678 | } | |
2679 | if (fixp[2]) | |
252b5132 | 2680 | { |
f6688943 TS |
2681 | fixp[2]->fx_frag = prev_insn_frag; |
2682 | fixp[2]->fx_where = prev_insn_where; | |
252b5132 RH |
2683 | } |
2684 | } | |
2685 | ||
2686 | /* Update the previous insn information; leave prev_insn | |
2687 | unchanged. */ | |
2688 | prev_prev_insn = *ip; | |
2689 | } | |
2690 | prev_insn_is_delay_slot = 1; | |
2691 | ||
2692 | /* If that was an unconditional branch, forget the previous | |
2693 | insn information. */ | |
2694 | if (pinfo & INSN_UNCOND_BRANCH_DELAY) | |
2695 | { | |
2696 | prev_prev_insn.insn_mo = &dummy_opcode; | |
2697 | prev_insn.insn_mo = &dummy_opcode; | |
2698 | } | |
2699 | ||
f6688943 TS |
2700 | prev_insn_fixp[0] = NULL; |
2701 | prev_insn_fixp[1] = NULL; | |
2702 | prev_insn_fixp[2] = NULL; | |
2703 | prev_insn_reloc_type[0] = BFD_RELOC_UNUSED; | |
2704 | prev_insn_reloc_type[1] = BFD_RELOC_UNUSED; | |
2705 | prev_insn_reloc_type[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
2706 | prev_insn_extended = 0; |
2707 | } | |
2708 | else if (pinfo & INSN_COND_BRANCH_LIKELY) | |
2709 | { | |
2710 | /* We don't yet optimize a branch likely. What we should do | |
2711 | is look at the target, copy the instruction found there | |
2712 | into the delay slot, and increment the branch to jump to | |
2713 | the next instruction. */ | |
2714 | emit_nop (); | |
2715 | /* Update the previous insn information. */ | |
2716 | prev_prev_insn = *ip; | |
2717 | prev_insn.insn_mo = &dummy_opcode; | |
f6688943 TS |
2718 | prev_insn_fixp[0] = NULL; |
2719 | prev_insn_fixp[1] = NULL; | |
2720 | prev_insn_fixp[2] = NULL; | |
2721 | prev_insn_reloc_type[0] = BFD_RELOC_UNUSED; | |
2722 | prev_insn_reloc_type[1] = BFD_RELOC_UNUSED; | |
2723 | prev_insn_reloc_type[2] = BFD_RELOC_UNUSED; | |
252b5132 | 2724 | prev_insn_extended = 0; |
f7870c8d | 2725 | prev_insn_is_delay_slot = 1; |
252b5132 RH |
2726 | } |
2727 | else | |
2728 | { | |
2729 | /* Update the previous insn information. */ | |
2730 | if (nops > 0) | |
2731 | prev_prev_insn.insn_mo = &dummy_opcode; | |
2732 | else | |
2733 | prev_prev_insn = prev_insn; | |
2734 | prev_insn = *ip; | |
2735 | ||
2736 | /* Any time we see a branch, we always fill the delay slot | |
2737 | immediately; since this insn is not a branch, we know it | |
2738 | is not in a delay slot. */ | |
2739 | prev_insn_is_delay_slot = 0; | |
2740 | ||
f6688943 TS |
2741 | prev_insn_fixp[0] = fixp[0]; |
2742 | prev_insn_fixp[1] = fixp[1]; | |
2743 | prev_insn_fixp[2] = fixp[2]; | |
2744 | prev_insn_reloc_type[0] = reloc_type[0]; | |
2745 | prev_insn_reloc_type[1] = reloc_type[1]; | |
2746 | prev_insn_reloc_type[2] = reloc_type[2]; | |
252b5132 RH |
2747 | if (mips_opts.mips16) |
2748 | prev_insn_extended = (ip->use_extend | |
f6688943 | 2749 | || *reloc_type > BFD_RELOC_UNUSED); |
252b5132 RH |
2750 | } |
2751 | ||
2752 | prev_prev_insn_unreordered = prev_insn_unreordered; | |
2753 | prev_insn_unreordered = 0; | |
2754 | prev_insn_frag = frag_now; | |
2755 | prev_insn_where = f - frag_now->fr_literal; | |
2756 | prev_insn_valid = 1; | |
2757 | } | |
4d7206a2 | 2758 | else if (mips_relax.sequence != 2) |
252b5132 RH |
2759 | { |
2760 | /* We need to record a bit of information even when we are not | |
2761 | reordering, in order to determine the base address for mips16 | |
2762 | PC relative relocs. */ | |
2763 | prev_prev_insn = prev_insn; | |
2764 | prev_insn = *ip; | |
f6688943 TS |
2765 | prev_insn_reloc_type[0] = reloc_type[0]; |
2766 | prev_insn_reloc_type[1] = reloc_type[1]; | |
2767 | prev_insn_reloc_type[2] = reloc_type[2]; | |
252b5132 RH |
2768 | prev_prev_insn_unreordered = prev_insn_unreordered; |
2769 | prev_insn_unreordered = 1; | |
2770 | } | |
2771 | ||
2772 | /* We just output an insn, so the next one doesn't have a label. */ | |
2773 | mips_clear_insn_labels (); | |
252b5132 RH |
2774 | } |
2775 | ||
2776 | /* This function forgets that there was any previous instruction or | |
2777 | label. If PRESERVE is non-zero, it remembers enough information to | |
bdaaa2e1 | 2778 | know whether nops are needed before a noreorder section. */ |
252b5132 RH |
2779 | |
2780 | static void | |
17a2f251 | 2781 | mips_no_prev_insn (int preserve) |
252b5132 RH |
2782 | { |
2783 | if (! preserve) | |
2784 | { | |
2785 | prev_insn.insn_mo = &dummy_opcode; | |
2786 | prev_prev_insn.insn_mo = &dummy_opcode; | |
2787 | prev_nop_frag = NULL; | |
2788 | prev_nop_frag_holds = 0; | |
2789 | prev_nop_frag_required = 0; | |
2790 | prev_nop_frag_since = 0; | |
2791 | } | |
2792 | prev_insn_valid = 0; | |
2793 | prev_insn_is_delay_slot = 0; | |
2794 | prev_insn_unreordered = 0; | |
2795 | prev_insn_extended = 0; | |
f6688943 TS |
2796 | prev_insn_reloc_type[0] = BFD_RELOC_UNUSED; |
2797 | prev_insn_reloc_type[1] = BFD_RELOC_UNUSED; | |
2798 | prev_insn_reloc_type[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
2799 | prev_prev_insn_unreordered = 0; |
2800 | mips_clear_insn_labels (); | |
2801 | } | |
2802 | ||
2803 | /* This function must be called whenever we turn on noreorder or emit | |
2804 | something other than instructions. It inserts any NOPS which might | |
2805 | be needed by the previous instruction, and clears the information | |
2806 | kept for the previous instructions. The INSNS parameter is true if | |
bdaaa2e1 | 2807 | instructions are to follow. */ |
252b5132 RH |
2808 | |
2809 | static void | |
17a2f251 | 2810 | mips_emit_delays (bfd_boolean insns) |
252b5132 RH |
2811 | { |
2812 | if (! mips_opts.noreorder) | |
2813 | { | |
2814 | int nops; | |
2815 | ||
2816 | nops = 0; | |
2817 | if ((! mips_opts.mips16 | |
81912461 ILT |
2818 | && ((prev_insn.insn_mo->pinfo |
2819 | & (INSN_LOAD_COPROC_DELAY | |
2820 | | INSN_COPROC_MOVE_DELAY | |
2821 | | INSN_WRITE_COND_CODE)) | |
2822 | && ! cop_interlocks)) | |
252b5132 RH |
2823 | || (! hilo_interlocks |
2824 | && (prev_insn.insn_mo->pinfo | |
2825 | & (INSN_READ_LO | |
2826 | | INSN_READ_HI))) | |
2827 | || (! mips_opts.mips16 | |
81912461 ILT |
2828 | && (prev_insn.insn_mo->pinfo & INSN_LOAD_MEMORY_DELAY) |
2829 | && ! gpr_interlocks) | |
252b5132 | 2830 | || (! mips_opts.mips16 |
81912461 ILT |
2831 | && (prev_insn.insn_mo->pinfo & INSN_COPROC_MEMORY_DELAY) |
2832 | && ! cop_mem_interlocks)) | |
252b5132 | 2833 | { |
beae10d5 | 2834 | /* Itbl support may require additional care here. */ |
252b5132 RH |
2835 | ++nops; |
2836 | if ((! mips_opts.mips16 | |
81912461 ILT |
2837 | && ((prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE) |
2838 | && ! cop_interlocks)) | |
252b5132 RH |
2839 | || (! hilo_interlocks |
2840 | && ((prev_insn.insn_mo->pinfo & INSN_READ_HI) | |
2841 | || (prev_insn.insn_mo->pinfo & INSN_READ_LO)))) | |
2842 | ++nops; | |
2843 | ||
2844 | if (prev_insn_unreordered) | |
2845 | nops = 0; | |
2846 | } | |
2847 | else if ((! mips_opts.mips16 | |
81912461 ILT |
2848 | && ((prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE) |
2849 | && ! cop_interlocks)) | |
252b5132 RH |
2850 | || (! hilo_interlocks |
2851 | && ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI) | |
2852 | || (prev_prev_insn.insn_mo->pinfo & INSN_READ_LO)))) | |
2853 | { | |
beae10d5 | 2854 | /* Itbl support may require additional care here. */ |
252b5132 RH |
2855 | if (! prev_prev_insn_unreordered) |
2856 | ++nops; | |
2857 | } | |
2858 | ||
d766e8ec | 2859 | if (mips_fix_vr4120 && prev_insn.insn_mo->name) |
60b63b72 RS |
2860 | { |
2861 | int min_nops = 0; | |
2862 | const char *pn = prev_insn.insn_mo->name; | |
532c738a RS |
2863 | if (strncmp (pn, "macc", 4) == 0 |
2864 | || strncmp (pn, "dmacc", 5) == 0 | |
2865 | || strncmp (pn, "dmult", 5) == 0 | |
2866 | || strstr (pn, "div")) | |
2867 | min_nops = 1; | |
60b63b72 RS |
2868 | if (nops < min_nops) |
2869 | nops = min_nops; | |
2870 | } | |
2871 | ||
252b5132 RH |
2872 | if (nops > 0) |
2873 | { | |
2874 | struct insn_label_list *l; | |
2875 | ||
2876 | if (insns) | |
2877 | { | |
2878 | /* Record the frag which holds the nop instructions, so | |
2879 | that we can remove them if we don't need them. */ | |
2880 | frag_grow (mips_opts.mips16 ? nops * 2 : nops * 4); | |
2881 | prev_nop_frag = frag_now; | |
2882 | prev_nop_frag_holds = nops; | |
2883 | prev_nop_frag_required = 0; | |
2884 | prev_nop_frag_since = 0; | |
2885 | } | |
2886 | ||
2887 | for (; nops > 0; --nops) | |
2888 | emit_nop (); | |
2889 | ||
2890 | if (insns) | |
2891 | { | |
2892 | /* Move on to a new frag, so that it is safe to simply | |
bdaaa2e1 | 2893 | decrease the size of prev_nop_frag. */ |
252b5132 RH |
2894 | frag_wane (frag_now); |
2895 | frag_new (0); | |
2896 | } | |
2897 | ||
2898 | for (l = insn_labels; l != NULL; l = l->next) | |
2899 | { | |
98aa84af AM |
2900 | valueT val; |
2901 | ||
252b5132 | 2902 | assert (S_GET_SEGMENT (l->label) == now_seg); |
49309057 | 2903 | symbol_set_frag (l->label, frag_now); |
98aa84af | 2904 | val = (valueT) frag_now_fix (); |
252b5132 RH |
2905 | /* mips16 text labels are stored as odd. */ |
2906 | if (mips_opts.mips16) | |
f9419b05 | 2907 | ++val; |
98aa84af | 2908 | S_SET_VALUE (l->label, val); |
252b5132 RH |
2909 | } |
2910 | } | |
2911 | } | |
2912 | ||
2913 | /* Mark instruction labels in mips16 mode. */ | |
f9419b05 | 2914 | if (insns) |
252b5132 RH |
2915 | mips16_mark_labels (); |
2916 | ||
2917 | mips_no_prev_insn (insns); | |
2918 | } | |
2919 | ||
584892a6 RS |
2920 | /* Set up global variables for the start of a new macro. */ |
2921 | ||
2922 | static void | |
2923 | macro_start (void) | |
2924 | { | |
2925 | memset (&mips_macro_warning.sizes, 0, sizeof (mips_macro_warning.sizes)); | |
2926 | mips_macro_warning.delay_slot_p = (mips_opts.noreorder | |
2927 | && (prev_insn.insn_mo->pinfo | |
2928 | & (INSN_UNCOND_BRANCH_DELAY | |
2929 | | INSN_COND_BRANCH_DELAY | |
2930 | | INSN_COND_BRANCH_LIKELY)) != 0); | |
2931 | } | |
2932 | ||
2933 | /* Given that a macro is longer than 4 bytes, return the appropriate warning | |
2934 | for it. Return null if no warning is needed. SUBTYPE is a bitmask of | |
2935 | RELAX_DELAY_SLOT and RELAX_NOMACRO. */ | |
2936 | ||
2937 | static const char * | |
2938 | macro_warning (relax_substateT subtype) | |
2939 | { | |
2940 | if (subtype & RELAX_DELAY_SLOT) | |
2941 | return _("Macro instruction expanded into multiple instructions" | |
2942 | " in a branch delay slot"); | |
2943 | else if (subtype & RELAX_NOMACRO) | |
2944 | return _("Macro instruction expanded into multiple instructions"); | |
2945 | else | |
2946 | return 0; | |
2947 | } | |
2948 | ||
2949 | /* Finish up a macro. Emit warnings as appropriate. */ | |
2950 | ||
2951 | static void | |
2952 | macro_end (void) | |
2953 | { | |
2954 | if (mips_macro_warning.sizes[0] > 4 || mips_macro_warning.sizes[1] > 4) | |
2955 | { | |
2956 | relax_substateT subtype; | |
2957 | ||
2958 | /* Set up the relaxation warning flags. */ | |
2959 | subtype = 0; | |
2960 | if (mips_macro_warning.sizes[1] > mips_macro_warning.sizes[0]) | |
2961 | subtype |= RELAX_SECOND_LONGER; | |
2962 | if (mips_opts.warn_about_macros) | |
2963 | subtype |= RELAX_NOMACRO; | |
2964 | if (mips_macro_warning.delay_slot_p) | |
2965 | subtype |= RELAX_DELAY_SLOT; | |
2966 | ||
2967 | if (mips_macro_warning.sizes[0] > 4 && mips_macro_warning.sizes[1] > 4) | |
2968 | { | |
2969 | /* Either the macro has a single implementation or both | |
2970 | implementations are longer than 4 bytes. Emit the | |
2971 | warning now. */ | |
2972 | const char *msg = macro_warning (subtype); | |
2973 | if (msg != 0) | |
2974 | as_warn (msg); | |
2975 | } | |
2976 | else | |
2977 | { | |
2978 | /* One implementation might need a warning but the other | |
2979 | definitely doesn't. */ | |
2980 | mips_macro_warning.first_frag->fr_subtype |= subtype; | |
2981 | } | |
2982 | } | |
2983 | } | |
2984 | ||
6e1304d8 RS |
2985 | /* Read a macro's relocation codes from *ARGS and store them in *R. |
2986 | The first argument in *ARGS will be either the code for a single | |
2987 | relocation or -1 followed by the three codes that make up a | |
2988 | composite relocation. */ | |
2989 | ||
2990 | static void | |
2991 | macro_read_relocs (va_list *args, bfd_reloc_code_real_type *r) | |
2992 | { | |
2993 | int i, next; | |
2994 | ||
2995 | next = va_arg (*args, int); | |
2996 | if (next >= 0) | |
2997 | r[0] = (bfd_reloc_code_real_type) next; | |
2998 | else | |
2999 | for (i = 0; i < 3; i++) | |
3000 | r[i] = (bfd_reloc_code_real_type) va_arg (*args, int); | |
3001 | } | |
3002 | ||
252b5132 RH |
3003 | /* Build an instruction created by a macro expansion. This is passed |
3004 | a pointer to the count of instructions created so far, an | |
3005 | expression, the name of the instruction to build, an operand format | |
3006 | string, and corresponding arguments. */ | |
3007 | ||
252b5132 | 3008 | static void |
67c0d1eb | 3009 | macro_build (expressionS *ep, const char *name, const char *fmt, ...) |
252b5132 RH |
3010 | { |
3011 | struct mips_cl_insn insn; | |
f6688943 | 3012 | bfd_reloc_code_real_type r[3]; |
252b5132 | 3013 | va_list args; |
252b5132 | 3014 | |
252b5132 | 3015 | va_start (args, fmt); |
252b5132 | 3016 | |
252b5132 RH |
3017 | if (mips_opts.mips16) |
3018 | { | |
67c0d1eb | 3019 | mips16_macro_build (ep, name, fmt, args); |
252b5132 RH |
3020 | va_end (args); |
3021 | return; | |
3022 | } | |
3023 | ||
f6688943 TS |
3024 | r[0] = BFD_RELOC_UNUSED; |
3025 | r[1] = BFD_RELOC_UNUSED; | |
3026 | r[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
3027 | insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name); |
3028 | assert (insn.insn_mo); | |
3029 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
3030 | ||
3031 | /* Search until we get a match for NAME. */ | |
3032 | while (1) | |
3033 | { | |
b34976b6 | 3034 | /* It is assumed here that macros will never generate |
deec1734 | 3035 | MDMX or MIPS-3D instructions. */ |
252b5132 RH |
3036 | if (strcmp (fmt, insn.insn_mo->args) == 0 |
3037 | && insn.insn_mo->pinfo != INSN_MACRO | |
aec421e0 TS |
3038 | && OPCODE_IS_MEMBER (insn.insn_mo, |
3039 | (mips_opts.isa | |
3396de36 | 3040 | | (file_ase_mips16 ? INSN_MIPS16 : 0)), |
fef14a42 TS |
3041 | mips_opts.arch) |
3042 | && (mips_opts.arch != CPU_R4650 || (insn.insn_mo->pinfo & FP_D) == 0)) | |
252b5132 RH |
3043 | break; |
3044 | ||
3045 | ++insn.insn_mo; | |
3046 | assert (insn.insn_mo->name); | |
3047 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
3048 | } | |
3049 | ||
3050 | insn.insn_opcode = insn.insn_mo->match; | |
3051 | for (;;) | |
3052 | { | |
3053 | switch (*fmt++) | |
3054 | { | |
3055 | case '\0': | |
3056 | break; | |
3057 | ||
3058 | case ',': | |
3059 | case '(': | |
3060 | case ')': | |
3061 | continue; | |
3062 | ||
5f74bc13 CD |
3063 | case '+': |
3064 | switch (*fmt++) | |
3065 | { | |
3066 | case 'A': | |
3067 | case 'E': | |
3068 | insn.insn_opcode |= (va_arg (args, int) | |
3069 | & OP_MASK_SHAMT) << OP_SH_SHAMT; | |
3070 | continue; | |
3071 | ||
3072 | case 'B': | |
3073 | case 'F': | |
3074 | /* Note that in the macro case, these arguments are already | |
3075 | in MSB form. (When handling the instruction in the | |
3076 | non-macro case, these arguments are sizes from which | |
3077 | MSB values must be calculated.) */ | |
3078 | insn.insn_opcode |= (va_arg (args, int) | |
3079 | & OP_MASK_INSMSB) << OP_SH_INSMSB; | |
3080 | continue; | |
3081 | ||
3082 | case 'C': | |
3083 | case 'G': | |
3084 | case 'H': | |
3085 | /* Note that in the macro case, these arguments are already | |
3086 | in MSBD form. (When handling the instruction in the | |
3087 | non-macro case, these arguments are sizes from which | |
3088 | MSBD values must be calculated.) */ | |
3089 | insn.insn_opcode |= (va_arg (args, int) | |
3090 | & OP_MASK_EXTMSBD) << OP_SH_EXTMSBD; | |
3091 | continue; | |
3092 | ||
3093 | default: | |
3094 | internalError (); | |
3095 | } | |
3096 | continue; | |
3097 | ||
252b5132 RH |
3098 | case 't': |
3099 | case 'w': | |
3100 | case 'E': | |
38487616 | 3101 | insn.insn_opcode |= va_arg (args, int) << OP_SH_RT; |
252b5132 RH |
3102 | continue; |
3103 | ||
3104 | case 'c': | |
38487616 TS |
3105 | insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE; |
3106 | continue; | |
3107 | ||
252b5132 RH |
3108 | case 'T': |
3109 | case 'W': | |
38487616 | 3110 | insn.insn_opcode |= va_arg (args, int) << OP_SH_FT; |
252b5132 RH |
3111 | continue; |
3112 | ||
3113 | case 'd': | |
3114 | case 'G': | |
af7ee8bf | 3115 | case 'K': |
38487616 | 3116 | insn.insn_opcode |= va_arg (args, int) << OP_SH_RD; |
252b5132 RH |
3117 | continue; |
3118 | ||
4372b673 NC |
3119 | case 'U': |
3120 | { | |
3121 | int tmp = va_arg (args, int); | |
3122 | ||
38487616 TS |
3123 | insn.insn_opcode |= tmp << OP_SH_RT; |
3124 | insn.insn_opcode |= tmp << OP_SH_RD; | |
beae10d5 | 3125 | continue; |
4372b673 NC |
3126 | } |
3127 | ||
252b5132 RH |
3128 | case 'V': |
3129 | case 'S': | |
38487616 | 3130 | insn.insn_opcode |= va_arg (args, int) << OP_SH_FS; |
252b5132 RH |
3131 | continue; |
3132 | ||
3133 | case 'z': | |
3134 | continue; | |
3135 | ||
3136 | case '<': | |
38487616 | 3137 | insn.insn_opcode |= va_arg (args, int) << OP_SH_SHAMT; |
252b5132 RH |
3138 | continue; |
3139 | ||
3140 | case 'D': | |
38487616 | 3141 | insn.insn_opcode |= va_arg (args, int) << OP_SH_FD; |
252b5132 RH |
3142 | continue; |
3143 | ||
3144 | case 'B': | |
38487616 | 3145 | insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE20; |
252b5132 RH |
3146 | continue; |
3147 | ||
4372b673 | 3148 | case 'J': |
38487616 | 3149 | insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE19; |
4372b673 NC |
3150 | continue; |
3151 | ||
252b5132 | 3152 | case 'q': |
38487616 | 3153 | insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE2; |
252b5132 RH |
3154 | continue; |
3155 | ||
3156 | case 'b': | |
3157 | case 's': | |
3158 | case 'r': | |
3159 | case 'v': | |
38487616 | 3160 | insn.insn_opcode |= va_arg (args, int) << OP_SH_RS; |
252b5132 RH |
3161 | continue; |
3162 | ||
3163 | case 'i': | |
3164 | case 'j': | |
3165 | case 'o': | |
6e1304d8 | 3166 | macro_read_relocs (&args, r); |
cdf6fd85 | 3167 | assert (*r == BFD_RELOC_GPREL16 |
f6688943 TS |
3168 | || *r == BFD_RELOC_MIPS_LITERAL |
3169 | || *r == BFD_RELOC_MIPS_HIGHER | |
3170 | || *r == BFD_RELOC_HI16_S | |
3171 | || *r == BFD_RELOC_LO16 | |
3172 | || *r == BFD_RELOC_MIPS_GOT16 | |
3173 | || *r == BFD_RELOC_MIPS_CALL16 | |
438c16b8 TS |
3174 | || *r == BFD_RELOC_MIPS_GOT_DISP |
3175 | || *r == BFD_RELOC_MIPS_GOT_PAGE | |
3176 | || *r == BFD_RELOC_MIPS_GOT_OFST | |
f6688943 | 3177 | || *r == BFD_RELOC_MIPS_GOT_LO16 |
3e722fb5 | 3178 | || *r == BFD_RELOC_MIPS_CALL_LO16); |
252b5132 RH |
3179 | continue; |
3180 | ||
3181 | case 'u': | |
6e1304d8 | 3182 | macro_read_relocs (&args, r); |
252b5132 RH |
3183 | assert (ep != NULL |
3184 | && (ep->X_op == O_constant | |
3185 | || (ep->X_op == O_symbol | |
f6688943 TS |
3186 | && (*r == BFD_RELOC_MIPS_HIGHEST |
3187 | || *r == BFD_RELOC_HI16_S | |
3188 | || *r == BFD_RELOC_HI16 | |
3189 | || *r == BFD_RELOC_GPREL16 | |
3190 | || *r == BFD_RELOC_MIPS_GOT_HI16 | |
3e722fb5 | 3191 | || *r == BFD_RELOC_MIPS_CALL_HI16)))); |
252b5132 RH |
3192 | continue; |
3193 | ||
3194 | case 'p': | |
3195 | assert (ep != NULL); | |
3196 | /* | |
3197 | * This allows macro() to pass an immediate expression for | |
3198 | * creating short branches without creating a symbol. | |
0b25d3e6 AO |
3199 | * Note that the expression still might come from the assembly |
3200 | * input, in which case the value is not checked for range nor | |
3201 | * is a relocation entry generated (yuck). | |
252b5132 RH |
3202 | */ |
3203 | if (ep->X_op == O_constant) | |
3204 | { | |
3205 | insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff; | |
3206 | ep = NULL; | |
3207 | } | |
3208 | else | |
0b25d3e6 | 3209 | *r = BFD_RELOC_16_PCREL_S2; |
252b5132 RH |
3210 | continue; |
3211 | ||
3212 | case 'a': | |
3213 | assert (ep != NULL); | |
f6688943 | 3214 | *r = BFD_RELOC_MIPS_JMP; |
252b5132 RH |
3215 | continue; |
3216 | ||
3217 | case 'C': | |
3218 | insn.insn_opcode |= va_arg (args, unsigned long); | |
3219 | continue; | |
3220 | ||
3221 | default: | |
3222 | internalError (); | |
3223 | } | |
3224 | break; | |
3225 | } | |
3226 | va_end (args); | |
f6688943 | 3227 | assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
252b5132 | 3228 | |
4d7206a2 | 3229 | append_insn (&insn, ep, r); |
252b5132 RH |
3230 | } |
3231 | ||
3232 | static void | |
67c0d1eb | 3233 | mips16_macro_build (expressionS *ep, const char *name, const char *fmt, |
17a2f251 | 3234 | va_list args) |
252b5132 RH |
3235 | { |
3236 | struct mips_cl_insn insn; | |
f6688943 TS |
3237 | bfd_reloc_code_real_type r[3] |
3238 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 3239 | |
252b5132 RH |
3240 | insn.insn_mo = (struct mips_opcode *) hash_find (mips16_op_hash, name); |
3241 | assert (insn.insn_mo); | |
3242 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
3243 | ||
3244 | while (strcmp (fmt, insn.insn_mo->args) != 0 | |
3245 | || insn.insn_mo->pinfo == INSN_MACRO) | |
3246 | { | |
3247 | ++insn.insn_mo; | |
3248 | assert (insn.insn_mo->name); | |
3249 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
3250 | } | |
3251 | ||
3252 | insn.insn_opcode = insn.insn_mo->match; | |
b34976b6 | 3253 | insn.use_extend = FALSE; |
252b5132 RH |
3254 | |
3255 | for (;;) | |
3256 | { | |
3257 | int c; | |
3258 | ||
3259 | c = *fmt++; | |
3260 | switch (c) | |
3261 | { | |
3262 | case '\0': | |
3263 | break; | |
3264 | ||
3265 | case ',': | |
3266 | case '(': | |
3267 | case ')': | |
3268 | continue; | |
3269 | ||
3270 | case 'y': | |
3271 | case 'w': | |
3272 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RY; | |
3273 | continue; | |
3274 | ||
3275 | case 'x': | |
3276 | case 'v': | |
3277 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RX; | |
3278 | continue; | |
3279 | ||
3280 | case 'z': | |
3281 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RZ; | |
3282 | continue; | |
3283 | ||
3284 | case 'Z': | |
3285 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_MOVE32Z; | |
3286 | continue; | |
3287 | ||
3288 | case '0': | |
3289 | case 'S': | |
3290 | case 'P': | |
3291 | case 'R': | |
3292 | continue; | |
3293 | ||
3294 | case 'X': | |
3295 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_REGR32; | |
3296 | continue; | |
3297 | ||
3298 | case 'Y': | |
3299 | { | |
3300 | int regno; | |
3301 | ||
3302 | regno = va_arg (args, int); | |
3303 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); | |
3304 | insn.insn_opcode |= regno << MIPS16OP_SH_REG32R; | |
3305 | } | |
3306 | continue; | |
3307 | ||
3308 | case '<': | |
3309 | case '>': | |
3310 | case '4': | |
3311 | case '5': | |
3312 | case 'H': | |
3313 | case 'W': | |
3314 | case 'D': | |
3315 | case 'j': | |
3316 | case '8': | |
3317 | case 'V': | |
3318 | case 'C': | |
3319 | case 'U': | |
3320 | case 'k': | |
3321 | case 'K': | |
3322 | case 'p': | |
3323 | case 'q': | |
3324 | { | |
3325 | assert (ep != NULL); | |
3326 | ||
3327 | if (ep->X_op != O_constant) | |
874e8986 | 3328 | *r = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
3329 | else |
3330 | { | |
b34976b6 AM |
3331 | mips16_immed (NULL, 0, c, ep->X_add_number, FALSE, FALSE, |
3332 | FALSE, &insn.insn_opcode, &insn.use_extend, | |
c4e7957c | 3333 | &insn.extend); |
252b5132 | 3334 | ep = NULL; |
f6688943 | 3335 | *r = BFD_RELOC_UNUSED; |
252b5132 RH |
3336 | } |
3337 | } | |
3338 | continue; | |
3339 | ||
3340 | case '6': | |
3341 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_IMM6; | |
3342 | continue; | |
3343 | } | |
3344 | ||
3345 | break; | |
3346 | } | |
3347 | ||
f6688943 | 3348 | assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
252b5132 | 3349 | |
4d7206a2 | 3350 | append_insn (&insn, ep, r); |
252b5132 RH |
3351 | } |
3352 | ||
438c16b8 TS |
3353 | /* |
3354 | * Generate a "jalr" instruction with a relocation hint to the called | |
3355 | * function. This occurs in NewABI PIC code. | |
3356 | */ | |
3357 | static void | |
67c0d1eb | 3358 | macro_build_jalr (expressionS *ep) |
438c16b8 | 3359 | { |
685736be | 3360 | char *f = NULL; |
b34976b6 | 3361 | |
438c16b8 | 3362 | if (HAVE_NEWABI) |
f21f8242 | 3363 | { |
cc3d92a5 | 3364 | frag_grow (8); |
f21f8242 AO |
3365 | f = frag_more (0); |
3366 | } | |
67c0d1eb | 3367 | macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG); |
438c16b8 | 3368 | if (HAVE_NEWABI) |
f21f8242 | 3369 | fix_new_exp (frag_now, f - frag_now->fr_literal, |
a105a300 | 3370 | 4, ep, FALSE, BFD_RELOC_MIPS_JALR); |
438c16b8 TS |
3371 | } |
3372 | ||
252b5132 RH |
3373 | /* |
3374 | * Generate a "lui" instruction. | |
3375 | */ | |
3376 | static void | |
67c0d1eb | 3377 | macro_build_lui (expressionS *ep, int regnum) |
252b5132 RH |
3378 | { |
3379 | expressionS high_expr; | |
3380 | struct mips_cl_insn insn; | |
f6688943 TS |
3381 | bfd_reloc_code_real_type r[3] |
3382 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
5a38dc70 AM |
3383 | const char *name = "lui"; |
3384 | const char *fmt = "t,u"; | |
252b5132 RH |
3385 | |
3386 | assert (! mips_opts.mips16); | |
3387 | ||
4d7206a2 | 3388 | high_expr = *ep; |
252b5132 RH |
3389 | |
3390 | if (high_expr.X_op == O_constant) | |
3391 | { | |
3392 | /* we can compute the instruction now without a relocation entry */ | |
e7d556df TS |
3393 | high_expr.X_add_number = ((high_expr.X_add_number + 0x8000) |
3394 | >> 16) & 0xffff; | |
f6688943 | 3395 | *r = BFD_RELOC_UNUSED; |
252b5132 | 3396 | } |
78e1bb40 | 3397 | else |
252b5132 RH |
3398 | { |
3399 | assert (ep->X_op == O_symbol); | |
aa6975fb ILT |
3400 | /* _gp_disp is a special case, used from s_cpload. _gp is used |
3401 | if mips_no_shared. */ | |
252b5132 | 3402 | assert (mips_pic == NO_PIC |
78e1bb40 | 3403 | || (! HAVE_NEWABI |
aa6975fb ILT |
3404 | && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0) |
3405 | || (! mips_in_shared | |
3406 | && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp") == 0)); | |
f6688943 | 3407 | *r = BFD_RELOC_HI16_S; |
252b5132 RH |
3408 | } |
3409 | ||
252b5132 RH |
3410 | insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name); |
3411 | assert (insn.insn_mo); | |
3412 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
3413 | assert (strcmp (fmt, insn.insn_mo->args) == 0); | |
3414 | ||
3415 | insn.insn_opcode = insn.insn_mo->match | (regnum << OP_SH_RT); | |
f6688943 | 3416 | if (*r == BFD_RELOC_UNUSED) |
252b5132 RH |
3417 | { |
3418 | insn.insn_opcode |= high_expr.X_add_number; | |
4d7206a2 | 3419 | append_insn (&insn, NULL, r); |
252b5132 RH |
3420 | } |
3421 | else | |
4d7206a2 | 3422 | append_insn (&insn, &high_expr, r); |
252b5132 RH |
3423 | } |
3424 | ||
885add95 CD |
3425 | /* Generate a sequence of instructions to do a load or store from a constant |
3426 | offset off of a base register (breg) into/from a target register (treg), | |
3427 | using AT if necessary. */ | |
3428 | static void | |
67c0d1eb RS |
3429 | macro_build_ldst_constoffset (expressionS *ep, const char *op, |
3430 | int treg, int breg, int dbl) | |
885add95 CD |
3431 | { |
3432 | assert (ep->X_op == O_constant); | |
3433 | ||
256ab948 | 3434 | /* Sign-extending 32-bit constants makes their handling easier. */ |
d17e7bce TS |
3435 | if (! dbl && ! ((ep->X_add_number & ~((bfd_vma) 0x7fffffff)) |
3436 | == ~((bfd_vma) 0x7fffffff))) | |
ae826530 | 3437 | { |
d17e7bce | 3438 | if (ep->X_add_number & ~((bfd_vma) 0xffffffff)) |
1b8e29e5 | 3439 | as_bad (_("constant too large")); |
ae826530 | 3440 | |
1b8e29e5 TS |
3441 | ep->X_add_number = (((ep->X_add_number & 0xffffffff) ^ 0x80000000) |
3442 | - 0x80000000); | |
ae826530 | 3443 | } |
256ab948 | 3444 | |
67c1ffbe | 3445 | /* Right now, this routine can only handle signed 32-bit constants. */ |
ecd13cd3 | 3446 | if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000)) |
885add95 CD |
3447 | as_warn (_("operand overflow")); |
3448 | ||
3449 | if (IS_SEXT_16BIT_NUM(ep->X_add_number)) | |
3450 | { | |
3451 | /* Signed 16-bit offset will fit in the op. Easy! */ | |
67c0d1eb | 3452 | macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
885add95 CD |
3453 | } |
3454 | else | |
3455 | { | |
3456 | /* 32-bit offset, need multiple instructions and AT, like: | |
3457 | lui $tempreg,const_hi (BFD_RELOC_HI16_S) | |
3458 | addu $tempreg,$tempreg,$breg | |
3459 | <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16) | |
3460 | to handle the complete offset. */ | |
67c0d1eb RS |
3461 | macro_build_lui (ep, AT); |
3462 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); | |
3463 | macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, AT); | |
885add95 CD |
3464 | |
3465 | if (mips_opts.noat) | |
3466 | as_warn (_("Macro used $at after \".set noat\"")); | |
3467 | } | |
3468 | } | |
3469 | ||
252b5132 RH |
3470 | /* set_at() |
3471 | * Generates code to set the $at register to true (one) | |
3472 | * if reg is less than the immediate expression. | |
3473 | */ | |
3474 | static void | |
67c0d1eb | 3475 | set_at (int reg, int unsignedp) |
252b5132 RH |
3476 | { |
3477 | if (imm_expr.X_op == O_constant | |
3478 | && imm_expr.X_add_number >= -0x8000 | |
3479 | && imm_expr.X_add_number < 0x8000) | |
67c0d1eb RS |
3480 | macro_build (&imm_expr, unsignedp ? "sltiu" : "slti", "t,r,j", |
3481 | AT, reg, BFD_RELOC_LO16); | |
252b5132 RH |
3482 | else |
3483 | { | |
67c0d1eb RS |
3484 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
3485 | macro_build (NULL, unsignedp ? "sltu" : "slt", "d,v,t", AT, reg, AT); | |
252b5132 RH |
3486 | } |
3487 | } | |
3488 | ||
13757d0c TS |
3489 | static void |
3490 | normalize_constant_expr (expressionS *ex) | |
3491 | { | |
3492 | if (ex->X_op == O_constant && HAVE_32BIT_GPRS) | |
3493 | ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000) | |
3494 | - 0x80000000); | |
3495 | } | |
3496 | ||
252b5132 RH |
3497 | /* Warn if an expression is not a constant. */ |
3498 | ||
3499 | static void | |
17a2f251 | 3500 | check_absolute_expr (struct mips_cl_insn *ip, expressionS *ex) |
252b5132 RH |
3501 | { |
3502 | if (ex->X_op == O_big) | |
3503 | as_bad (_("unsupported large constant")); | |
3504 | else if (ex->X_op != O_constant) | |
3505 | as_bad (_("Instruction %s requires absolute expression"), ip->insn_mo->name); | |
13757d0c TS |
3506 | |
3507 | normalize_constant_expr (ex); | |
252b5132 RH |
3508 | } |
3509 | ||
3510 | /* Count the leading zeroes by performing a binary chop. This is a | |
3511 | bulky bit of source, but performance is a LOT better for the | |
3512 | majority of values than a simple loop to count the bits: | |
3513 | for (lcnt = 0; (lcnt < 32); lcnt++) | |
3514 | if ((v) & (1 << (31 - lcnt))) | |
3515 | break; | |
3516 | However it is not code size friendly, and the gain will drop a bit | |
3517 | on certain cached systems. | |
3518 | */ | |
3519 | #define COUNT_TOP_ZEROES(v) \ | |
3520 | (((v) & ~0xffff) == 0 \ | |
3521 | ? ((v) & ~0xff) == 0 \ | |
3522 | ? ((v) & ~0xf) == 0 \ | |
3523 | ? ((v) & ~0x3) == 0 \ | |
3524 | ? ((v) & ~0x1) == 0 \ | |
3525 | ? !(v) \ | |
3526 | ? 32 \ | |
3527 | : 31 \ | |
3528 | : 30 \ | |
3529 | : ((v) & ~0x7) == 0 \ | |
3530 | ? 29 \ | |
3531 | : 28 \ | |
3532 | : ((v) & ~0x3f) == 0 \ | |
3533 | ? ((v) & ~0x1f) == 0 \ | |
3534 | ? 27 \ | |
3535 | : 26 \ | |
3536 | : ((v) & ~0x7f) == 0 \ | |
3537 | ? 25 \ | |
3538 | : 24 \ | |
3539 | : ((v) & ~0xfff) == 0 \ | |
3540 | ? ((v) & ~0x3ff) == 0 \ | |
3541 | ? ((v) & ~0x1ff) == 0 \ | |
3542 | ? 23 \ | |
3543 | : 22 \ | |
3544 | : ((v) & ~0x7ff) == 0 \ | |
3545 | ? 21 \ | |
3546 | : 20 \ | |
3547 | : ((v) & ~0x3fff) == 0 \ | |
3548 | ? ((v) & ~0x1fff) == 0 \ | |
3549 | ? 19 \ | |
3550 | : 18 \ | |
3551 | : ((v) & ~0x7fff) == 0 \ | |
3552 | ? 17 \ | |
3553 | : 16 \ | |
3554 | : ((v) & ~0xffffff) == 0 \ | |
3555 | ? ((v) & ~0xfffff) == 0 \ | |
3556 | ? ((v) & ~0x3ffff) == 0 \ | |
3557 | ? ((v) & ~0x1ffff) == 0 \ | |
3558 | ? 15 \ | |
3559 | : 14 \ | |
3560 | : ((v) & ~0x7ffff) == 0 \ | |
3561 | ? 13 \ | |
3562 | : 12 \ | |
3563 | : ((v) & ~0x3fffff) == 0 \ | |
3564 | ? ((v) & ~0x1fffff) == 0 \ | |
3565 | ? 11 \ | |
3566 | : 10 \ | |
3567 | : ((v) & ~0x7fffff) == 0 \ | |
3568 | ? 9 \ | |
3569 | : 8 \ | |
3570 | : ((v) & ~0xfffffff) == 0 \ | |
3571 | ? ((v) & ~0x3ffffff) == 0 \ | |
3572 | ? ((v) & ~0x1ffffff) == 0 \ | |
3573 | ? 7 \ | |
3574 | : 6 \ | |
3575 | : ((v) & ~0x7ffffff) == 0 \ | |
3576 | ? 5 \ | |
3577 | : 4 \ | |
3578 | : ((v) & ~0x3fffffff) == 0 \ | |
3579 | ? ((v) & ~0x1fffffff) == 0 \ | |
3580 | ? 3 \ | |
3581 | : 2 \ | |
3582 | : ((v) & ~0x7fffffff) == 0 \ | |
3583 | ? 1 \ | |
3584 | : 0) | |
3585 | ||
3586 | /* load_register() | |
67c1ffbe | 3587 | * This routine generates the least number of instructions necessary to load |
252b5132 RH |
3588 | * an absolute expression value into a register. |
3589 | */ | |
3590 | static void | |
67c0d1eb | 3591 | load_register (int reg, expressionS *ep, int dbl) |
252b5132 RH |
3592 | { |
3593 | int freg; | |
3594 | expressionS hi32, lo32; | |
3595 | ||
3596 | if (ep->X_op != O_big) | |
3597 | { | |
3598 | assert (ep->X_op == O_constant); | |
256ab948 TS |
3599 | |
3600 | /* Sign-extending 32-bit constants makes their handling easier. */ | |
d17e7bce TS |
3601 | if (! dbl && ! ((ep->X_add_number & ~((bfd_vma) 0x7fffffff)) |
3602 | == ~((bfd_vma) 0x7fffffff))) | |
ae826530 | 3603 | { |
d17e7bce | 3604 | if (ep->X_add_number & ~((bfd_vma) 0xffffffff)) |
1b8e29e5 | 3605 | as_bad (_("constant too large")); |
ae826530 | 3606 | |
1b8e29e5 TS |
3607 | ep->X_add_number = (((ep->X_add_number & 0xffffffff) ^ 0x80000000) |
3608 | - 0x80000000); | |
ae826530 | 3609 | } |
256ab948 TS |
3610 | |
3611 | if (IS_SEXT_16BIT_NUM (ep->X_add_number)) | |
252b5132 RH |
3612 | { |
3613 | /* We can handle 16 bit signed values with an addiu to | |
3614 | $zero. No need to ever use daddiu here, since $zero and | |
3615 | the result are always correct in 32 bit mode. */ | |
67c0d1eb | 3616 | macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
3617 | return; |
3618 | } | |
3619 | else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000) | |
3620 | { | |
3621 | /* We can handle 16 bit unsigned values with an ori to | |
3622 | $zero. */ | |
67c0d1eb | 3623 | macro_build (ep, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
3624 | return; |
3625 | } | |
256ab948 | 3626 | else if ((IS_SEXT_32BIT_NUM (ep->X_add_number))) |
252b5132 RH |
3627 | { |
3628 | /* 32 bit values require an lui. */ | |
67c0d1eb | 3629 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_HI16); |
252b5132 | 3630 | if ((ep->X_add_number & 0xffff) != 0) |
67c0d1eb | 3631 | macro_build (ep, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16); |
252b5132 RH |
3632 | return; |
3633 | } | |
3634 | } | |
3635 | ||
3636 | /* The value is larger than 32 bits. */ | |
3637 | ||
ca4e0257 | 3638 | if (HAVE_32BIT_GPRS) |
252b5132 | 3639 | { |
956cd1d6 TS |
3640 | as_bad (_("Number (0x%lx) larger than 32 bits"), |
3641 | (unsigned long) ep->X_add_number); | |
67c0d1eb | 3642 | macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
3643 | return; |
3644 | } | |
3645 | ||
3646 | if (ep->X_op != O_big) | |
3647 | { | |
3648 | hi32 = *ep; | |
3649 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
3650 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
3651 | hi32.X_add_number &= 0xffffffff; | |
3652 | lo32 = *ep; | |
3653 | lo32.X_add_number &= 0xffffffff; | |
3654 | } | |
3655 | else | |
3656 | { | |
3657 | assert (ep->X_add_number > 2); | |
3658 | if (ep->X_add_number == 3) | |
3659 | generic_bignum[3] = 0; | |
3660 | else if (ep->X_add_number > 4) | |
3661 | as_bad (_("Number larger than 64 bits")); | |
3662 | lo32.X_op = O_constant; | |
3663 | lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16); | |
3664 | hi32.X_op = O_constant; | |
3665 | hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16); | |
3666 | } | |
3667 | ||
3668 | if (hi32.X_add_number == 0) | |
3669 | freg = 0; | |
3670 | else | |
3671 | { | |
3672 | int shift, bit; | |
3673 | unsigned long hi, lo; | |
3674 | ||
956cd1d6 | 3675 | if (hi32.X_add_number == (offsetT) 0xffffffff) |
beae10d5 KH |
3676 | { |
3677 | if ((lo32.X_add_number & 0xffff8000) == 0xffff8000) | |
3678 | { | |
67c0d1eb | 3679 | macro_build (&lo32, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
beae10d5 KH |
3680 | return; |
3681 | } | |
3682 | if (lo32.X_add_number & 0x80000000) | |
3683 | { | |
67c0d1eb | 3684 | macro_build (&lo32, "lui", "t,u", reg, BFD_RELOC_HI16); |
252b5132 | 3685 | if (lo32.X_add_number & 0xffff) |
67c0d1eb | 3686 | macro_build (&lo32, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16); |
beae10d5 KH |
3687 | return; |
3688 | } | |
3689 | } | |
252b5132 RH |
3690 | |
3691 | /* Check for 16bit shifted constant. We know that hi32 is | |
3692 | non-zero, so start the mask on the first bit of the hi32 | |
3693 | value. */ | |
3694 | shift = 17; | |
3695 | do | |
beae10d5 KH |
3696 | { |
3697 | unsigned long himask, lomask; | |
3698 | ||
3699 | if (shift < 32) | |
3700 | { | |
3701 | himask = 0xffff >> (32 - shift); | |
3702 | lomask = (0xffff << shift) & 0xffffffff; | |
3703 | } | |
3704 | else | |
3705 | { | |
3706 | himask = 0xffff << (shift - 32); | |
3707 | lomask = 0; | |
3708 | } | |
3709 | if ((hi32.X_add_number & ~(offsetT) himask) == 0 | |
3710 | && (lo32.X_add_number & ~(offsetT) lomask) == 0) | |
3711 | { | |
3712 | expressionS tmp; | |
3713 | ||
3714 | tmp.X_op = O_constant; | |
3715 | if (shift < 32) | |
3716 | tmp.X_add_number = ((hi32.X_add_number << (32 - shift)) | |
3717 | | (lo32.X_add_number >> shift)); | |
3718 | else | |
3719 | tmp.X_add_number = hi32.X_add_number >> (shift - 32); | |
67c0d1eb RS |
3720 | macro_build (&tmp, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16); |
3721 | macro_build (NULL, (shift >= 32) ? "dsll32" : "dsll", "d,w,<", | |
3722 | reg, reg, (shift >= 32) ? shift - 32 : shift); | |
beae10d5 KH |
3723 | return; |
3724 | } | |
f9419b05 | 3725 | ++shift; |
beae10d5 KH |
3726 | } |
3727 | while (shift <= (64 - 16)); | |
252b5132 RH |
3728 | |
3729 | /* Find the bit number of the lowest one bit, and store the | |
3730 | shifted value in hi/lo. */ | |
3731 | hi = (unsigned long) (hi32.X_add_number & 0xffffffff); | |
3732 | lo = (unsigned long) (lo32.X_add_number & 0xffffffff); | |
3733 | if (lo != 0) | |
3734 | { | |
3735 | bit = 0; | |
3736 | while ((lo & 1) == 0) | |
3737 | { | |
3738 | lo >>= 1; | |
3739 | ++bit; | |
3740 | } | |
3741 | lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit); | |
3742 | hi >>= bit; | |
3743 | } | |
3744 | else | |
3745 | { | |
3746 | bit = 32; | |
3747 | while ((hi & 1) == 0) | |
3748 | { | |
3749 | hi >>= 1; | |
3750 | ++bit; | |
3751 | } | |
3752 | lo = hi; | |
3753 | hi = 0; | |
3754 | } | |
3755 | ||
3756 | /* Optimize if the shifted value is a (power of 2) - 1. */ | |
3757 | if ((hi == 0 && ((lo + 1) & lo) == 0) | |
3758 | || (lo == 0xffffffff && ((hi + 1) & hi) == 0)) | |
beae10d5 KH |
3759 | { |
3760 | shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number); | |
252b5132 | 3761 | if (shift != 0) |
beae10d5 | 3762 | { |
252b5132 RH |
3763 | expressionS tmp; |
3764 | ||
3765 | /* This instruction will set the register to be all | |
3766 | ones. */ | |
beae10d5 KH |
3767 | tmp.X_op = O_constant; |
3768 | tmp.X_add_number = (offsetT) -1; | |
67c0d1eb | 3769 | macro_build (&tmp, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
beae10d5 KH |
3770 | if (bit != 0) |
3771 | { | |
3772 | bit += shift; | |
67c0d1eb RS |
3773 | macro_build (NULL, (bit >= 32) ? "dsll32" : "dsll", "d,w,<", |
3774 | reg, reg, (bit >= 32) ? bit - 32 : bit); | |
beae10d5 | 3775 | } |
67c0d1eb RS |
3776 | macro_build (NULL, (shift >= 32) ? "dsrl32" : "dsrl", "d,w,<", |
3777 | reg, reg, (shift >= 32) ? shift - 32 : shift); | |
beae10d5 KH |
3778 | return; |
3779 | } | |
3780 | } | |
252b5132 RH |
3781 | |
3782 | /* Sign extend hi32 before calling load_register, because we can | |
3783 | generally get better code when we load a sign extended value. */ | |
3784 | if ((hi32.X_add_number & 0x80000000) != 0) | |
beae10d5 | 3785 | hi32.X_add_number |= ~(offsetT) 0xffffffff; |
67c0d1eb | 3786 | load_register (reg, &hi32, 0); |
252b5132 RH |
3787 | freg = reg; |
3788 | } | |
3789 | if ((lo32.X_add_number & 0xffff0000) == 0) | |
3790 | { | |
3791 | if (freg != 0) | |
3792 | { | |
67c0d1eb | 3793 | macro_build (NULL, "dsll32", "d,w,<", reg, freg, 0); |
252b5132 RH |
3794 | freg = reg; |
3795 | } | |
3796 | } | |
3797 | else | |
3798 | { | |
3799 | expressionS mid16; | |
3800 | ||
956cd1d6 | 3801 | if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff)) |
beae10d5 | 3802 | { |
67c0d1eb RS |
3803 | macro_build (&lo32, "lui", "t,u", reg, BFD_RELOC_HI16); |
3804 | macro_build (NULL, "dsrl32", "d,w,<", reg, reg, 0); | |
beae10d5 KH |
3805 | return; |
3806 | } | |
252b5132 RH |
3807 | |
3808 | if (freg != 0) | |
3809 | { | |
67c0d1eb | 3810 | macro_build (NULL, "dsll", "d,w,<", reg, freg, 16); |
252b5132 RH |
3811 | freg = reg; |
3812 | } | |
3813 | mid16 = lo32; | |
3814 | mid16.X_add_number >>= 16; | |
67c0d1eb RS |
3815 | macro_build (&mid16, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16); |
3816 | macro_build (NULL, "dsll", "d,w,<", reg, reg, 16); | |
252b5132 RH |
3817 | freg = reg; |
3818 | } | |
3819 | if ((lo32.X_add_number & 0xffff) != 0) | |
67c0d1eb | 3820 | macro_build (&lo32, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16); |
252b5132 RH |
3821 | } |
3822 | ||
269137b2 TS |
3823 | static inline void |
3824 | load_delay_nop (void) | |
3825 | { | |
3826 | if (!gpr_interlocks) | |
3827 | macro_build (NULL, "nop", ""); | |
3828 | } | |
3829 | ||
252b5132 RH |
3830 | /* Load an address into a register. */ |
3831 | ||
3832 | static void | |
67c0d1eb | 3833 | load_address (int reg, expressionS *ep, int *used_at) |
252b5132 | 3834 | { |
252b5132 RH |
3835 | if (ep->X_op != O_constant |
3836 | && ep->X_op != O_symbol) | |
3837 | { | |
3838 | as_bad (_("expression too complex")); | |
3839 | ep->X_op = O_constant; | |
3840 | } | |
3841 | ||
3842 | if (ep->X_op == O_constant) | |
3843 | { | |
67c0d1eb | 3844 | load_register (reg, ep, HAVE_64BIT_ADDRESSES); |
252b5132 RH |
3845 | return; |
3846 | } | |
3847 | ||
3848 | if (mips_pic == NO_PIC) | |
3849 | { | |
3850 | /* If this is a reference to a GP relative symbol, we want | |
cdf6fd85 | 3851 | addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
3852 | Otherwise we want |
3853 | lui $reg,<sym> (BFD_RELOC_HI16_S) | |
3854 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
d6bc6245 | 3855 | If we have an addend, we always use the latter form. |
76b3015f | 3856 | |
d6bc6245 TS |
3857 | With 64bit address space and a usable $at we want |
3858 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
3859 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
3860 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
3861 | daddiu $at,<sym> (BFD_RELOC_LO16) | |
3862 | dsll32 $reg,0 | |
3a482fd5 | 3863 | daddu $reg,$reg,$at |
76b3015f | 3864 | |
c03099e6 | 3865 | If $at is already in use, we use a path which is suboptimal |
d6bc6245 TS |
3866 | on superscalar processors. |
3867 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
3868 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
3869 | dsll $reg,16 | |
3870 | daddiu $reg,<sym> (BFD_RELOC_HI16_S) | |
3871 | dsll $reg,16 | |
3872 | daddiu $reg,<sym> (BFD_RELOC_LO16) | |
3873 | */ | |
c9914766 | 3874 | if (HAVE_64BIT_ADDRESSES) |
d6bc6245 | 3875 | { |
e864ceca RS |
3876 | /* ??? We don't provide a GP-relative alternative for these macros. |
3877 | It used not to be possible with the original relaxation code, | |
3878 | but it could be done now. */ | |
d6bc6245 | 3879 | |
b8285c27 | 3880 | if (*used_at == 0 && !mips_opts.noat) |
d6bc6245 | 3881 | { |
67c0d1eb RS |
3882 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_HIGHEST); |
3883 | macro_build (ep, "lui", "t,u", AT, BFD_RELOC_HI16_S); | |
3884 | macro_build (ep, "daddiu", "t,r,j", reg, reg, | |
3885 | BFD_RELOC_MIPS_HIGHER); | |
3886 | macro_build (ep, "daddiu", "t,r,j", AT, AT, BFD_RELOC_LO16); | |
3887 | macro_build (NULL, "dsll32", "d,w,<", reg, reg, 0); | |
3888 | macro_build (NULL, "daddu", "d,v,t", reg, reg, AT); | |
d6bc6245 TS |
3889 | *used_at = 1; |
3890 | } | |
3891 | else | |
3892 | { | |
67c0d1eb RS |
3893 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_HIGHEST); |
3894 | macro_build (ep, "daddiu", "t,r,j", reg, reg, | |
3895 | BFD_RELOC_MIPS_HIGHER); | |
3896 | macro_build (NULL, "dsll", "d,w,<", reg, reg, 16); | |
3897 | macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_HI16_S); | |
3898 | macro_build (NULL, "dsll", "d,w,<", reg, reg, 16); | |
3899 | macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_LO16); | |
d6bc6245 TS |
3900 | } |
3901 | } | |
252b5132 RH |
3902 | else |
3903 | { | |
d6bc6245 TS |
3904 | if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET |
3905 | && ! nopic_need_relax (ep->X_add_symbol, 1)) | |
3906 | { | |
4d7206a2 | 3907 | relax_start (ep->X_add_symbol); |
67c0d1eb | 3908 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, |
17a2f251 | 3909 | mips_gp_register, BFD_RELOC_GPREL16); |
4d7206a2 | 3910 | relax_switch (); |
d6bc6245 | 3911 | } |
67c0d1eb RS |
3912 | macro_build_lui (ep, reg); |
3913 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", | |
3914 | reg, reg, BFD_RELOC_LO16); | |
4d7206a2 RS |
3915 | if (mips_relax.sequence) |
3916 | relax_end (); | |
d6bc6245 | 3917 | } |
252b5132 RH |
3918 | } |
3919 | else if (mips_pic == SVR4_PIC && ! mips_big_got) | |
3920 | { | |
3921 | expressionS ex; | |
3922 | ||
3923 | /* If this is a reference to an external symbol, we want | |
3924 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3925 | Otherwise we want | |
3926 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3927 | nop | |
3928 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
f5040a92 AO |
3929 | If there is a constant, it must be added in after. |
3930 | ||
ed6fb7bd | 3931 | If we have NewABI, we want |
f5040a92 AO |
3932 | lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP) |
3933 | unless we're referencing a global symbol with a non-zero | |
3934 | offset, in which case cst must be added separately. */ | |
ed6fb7bd SC |
3935 | if (HAVE_NEWABI) |
3936 | { | |
f5040a92 AO |
3937 | if (ep->X_add_number) |
3938 | { | |
4d7206a2 | 3939 | ex.X_add_number = ep->X_add_number; |
f5040a92 | 3940 | ep->X_add_number = 0; |
4d7206a2 | 3941 | relax_start (ep->X_add_symbol); |
67c0d1eb RS |
3942 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
3943 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
3944 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) |
3945 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
3946 | ex.X_op = O_constant; | |
67c0d1eb | 3947 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 3948 | reg, reg, BFD_RELOC_LO16); |
f5040a92 | 3949 | ep->X_add_number = ex.X_add_number; |
4d7206a2 | 3950 | relax_switch (); |
f5040a92 | 3951 | } |
67c0d1eb | 3952 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 3953 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); |
4d7206a2 RS |
3954 | if (mips_relax.sequence) |
3955 | relax_end (); | |
ed6fb7bd SC |
3956 | } |
3957 | else | |
3958 | { | |
f5040a92 AO |
3959 | ex.X_add_number = ep->X_add_number; |
3960 | ep->X_add_number = 0; | |
67c0d1eb RS |
3961 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
3962 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 3963 | load_delay_nop (); |
4d7206a2 RS |
3964 | relax_start (ep->X_add_symbol); |
3965 | relax_switch (); | |
67c0d1eb | 3966 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
17a2f251 | 3967 | BFD_RELOC_LO16); |
4d7206a2 | 3968 | relax_end (); |
ed6fb7bd | 3969 | |
f5040a92 AO |
3970 | if (ex.X_add_number != 0) |
3971 | { | |
3972 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
3973 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
3974 | ex.X_op = O_constant; | |
67c0d1eb | 3975 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 3976 | reg, reg, BFD_RELOC_LO16); |
f5040a92 | 3977 | } |
252b5132 RH |
3978 | } |
3979 | } | |
3980 | else if (mips_pic == SVR4_PIC) | |
3981 | { | |
3982 | expressionS ex; | |
252b5132 RH |
3983 | |
3984 | /* This is the large GOT case. If this is a reference to an | |
3985 | external symbol, we want | |
3986 | lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
3987 | addu $reg,$reg,$gp | |
3988 | lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16) | |
f5040a92 AO |
3989 | |
3990 | Otherwise, for a reference to a local symbol in old ABI, we want | |
252b5132 RH |
3991 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) |
3992 | nop | |
3993 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
684022ea | 3994 | If there is a constant, it must be added in after. |
f5040a92 AO |
3995 | |
3996 | In the NewABI, for local symbols, with or without offsets, we want: | |
438c16b8 TS |
3997 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) |
3998 | addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) | |
f5040a92 | 3999 | */ |
438c16b8 TS |
4000 | if (HAVE_NEWABI) |
4001 | { | |
4d7206a2 | 4002 | ex.X_add_number = ep->X_add_number; |
f5040a92 | 4003 | ep->X_add_number = 0; |
4d7206a2 | 4004 | relax_start (ep->X_add_symbol); |
67c0d1eb RS |
4005 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_GOT_HI16); |
4006 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
4007 | reg, reg, mips_gp_register); | |
4008 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", | |
4009 | reg, BFD_RELOC_MIPS_GOT_LO16, reg); | |
f5040a92 AO |
4010 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) |
4011 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4012 | else if (ex.X_add_number) | |
4013 | { | |
4014 | ex.X_op = O_constant; | |
67c0d1eb RS |
4015 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
4016 | BFD_RELOC_LO16); | |
f5040a92 AO |
4017 | } |
4018 | ||
4019 | ep->X_add_number = ex.X_add_number; | |
4d7206a2 | 4020 | relax_switch (); |
67c0d1eb | 4021 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 4022 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); |
67c0d1eb RS |
4023 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
4024 | BFD_RELOC_MIPS_GOT_OFST); | |
4d7206a2 | 4025 | relax_end (); |
438c16b8 | 4026 | } |
252b5132 | 4027 | else |
438c16b8 | 4028 | { |
f5040a92 AO |
4029 | ex.X_add_number = ep->X_add_number; |
4030 | ep->X_add_number = 0; | |
4d7206a2 | 4031 | relax_start (ep->X_add_symbol); |
67c0d1eb RS |
4032 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_GOT_HI16); |
4033 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
4034 | reg, reg, mips_gp_register); | |
4035 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", | |
4036 | reg, BFD_RELOC_MIPS_GOT_LO16, reg); | |
4d7206a2 RS |
4037 | relax_switch (); |
4038 | if (reg_needs_delay (mips_gp_register)) | |
438c16b8 TS |
4039 | { |
4040 | /* We need a nop before loading from $gp. This special | |
4041 | check is required because the lui which starts the main | |
4042 | instruction stream does not refer to $gp, and so will not | |
4043 | insert the nop which may be required. */ | |
67c0d1eb | 4044 | macro_build (NULL, "nop", ""); |
438c16b8 | 4045 | } |
67c0d1eb | 4046 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 4047 | BFD_RELOC_MIPS_GOT16, mips_gp_register); |
269137b2 | 4048 | load_delay_nop (); |
67c0d1eb | 4049 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
17a2f251 | 4050 | BFD_RELOC_LO16); |
4d7206a2 | 4051 | relax_end (); |
438c16b8 | 4052 | |
f5040a92 AO |
4053 | if (ex.X_add_number != 0) |
4054 | { | |
4055 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
4056 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4057 | ex.X_op = O_constant; | |
67c0d1eb RS |
4058 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
4059 | BFD_RELOC_LO16); | |
f5040a92 | 4060 | } |
252b5132 RH |
4061 | } |
4062 | } | |
252b5132 RH |
4063 | else |
4064 | abort (); | |
4065 | } | |
4066 | ||
ea1fb5dc RS |
4067 | /* Move the contents of register SOURCE into register DEST. */ |
4068 | ||
4069 | static void | |
67c0d1eb | 4070 | move_register (int dest, int source) |
ea1fb5dc | 4071 | { |
67c0d1eb RS |
4072 | macro_build (NULL, HAVE_32BIT_GPRS ? "addu" : "daddu", "d,v,t", |
4073 | dest, source, 0); | |
ea1fb5dc RS |
4074 | } |
4075 | ||
4d7206a2 | 4076 | /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where |
f6a22291 MR |
4077 | LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement. |
4078 | The two alternatives are: | |
4d7206a2 RS |
4079 | |
4080 | Global symbol Local sybmol | |
4081 | ------------- ------------ | |
4082 | lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET) | |
4083 | ... ... | |
4084 | addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET) | |
4085 | ||
4086 | load_got_offset emits the first instruction and add_got_offset | |
f6a22291 MR |
4087 | emits the second for a 16-bit offset or add_got_offset_hilo emits |
4088 | a sequence to add a 32-bit offset using a scratch register. */ | |
4d7206a2 RS |
4089 | |
4090 | static void | |
67c0d1eb | 4091 | load_got_offset (int dest, expressionS *local) |
4d7206a2 RS |
4092 | { |
4093 | expressionS global; | |
4094 | ||
4095 | global = *local; | |
4096 | global.X_add_number = 0; | |
4097 | ||
4098 | relax_start (local->X_add_symbol); | |
67c0d1eb RS |
4099 | macro_build (&global, ADDRESS_LOAD_INSN, "t,o(b)", dest, |
4100 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
4d7206a2 | 4101 | relax_switch (); |
67c0d1eb RS |
4102 | macro_build (local, ADDRESS_LOAD_INSN, "t,o(b)", dest, |
4103 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
4d7206a2 RS |
4104 | relax_end (); |
4105 | } | |
4106 | ||
4107 | static void | |
67c0d1eb | 4108 | add_got_offset (int dest, expressionS *local) |
4d7206a2 RS |
4109 | { |
4110 | expressionS global; | |
4111 | ||
4112 | global.X_op = O_constant; | |
4113 | global.X_op_symbol = NULL; | |
4114 | global.X_add_symbol = NULL; | |
4115 | global.X_add_number = local->X_add_number; | |
4116 | ||
4117 | relax_start (local->X_add_symbol); | |
67c0d1eb | 4118 | macro_build (&global, ADDRESS_ADDI_INSN, "t,r,j", |
4d7206a2 RS |
4119 | dest, dest, BFD_RELOC_LO16); |
4120 | relax_switch (); | |
67c0d1eb | 4121 | macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", dest, dest, BFD_RELOC_LO16); |
4d7206a2 RS |
4122 | relax_end (); |
4123 | } | |
4124 | ||
f6a22291 MR |
4125 | static void |
4126 | add_got_offset_hilo (int dest, expressionS *local, int tmp) | |
4127 | { | |
4128 | expressionS global; | |
4129 | int hold_mips_optimize; | |
4130 | ||
4131 | global.X_op = O_constant; | |
4132 | global.X_op_symbol = NULL; | |
4133 | global.X_add_symbol = NULL; | |
4134 | global.X_add_number = local->X_add_number; | |
4135 | ||
4136 | relax_start (local->X_add_symbol); | |
4137 | load_register (tmp, &global, HAVE_64BIT_ADDRESSES); | |
4138 | relax_switch (); | |
4139 | /* Set mips_optimize around the lui instruction to avoid | |
4140 | inserting an unnecessary nop after the lw. */ | |
4141 | hold_mips_optimize = mips_optimize; | |
4142 | mips_optimize = 2; | |
4143 | macro_build_lui (&global, tmp); | |
4144 | mips_optimize = hold_mips_optimize; | |
4145 | macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", tmp, tmp, BFD_RELOC_LO16); | |
4146 | relax_end (); | |
4147 | ||
4148 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dest, dest, tmp); | |
4149 | } | |
4150 | ||
252b5132 RH |
4151 | /* |
4152 | * Build macros | |
4153 | * This routine implements the seemingly endless macro or synthesized | |
4154 | * instructions and addressing modes in the mips assembly language. Many | |
4155 | * of these macros are simple and are similar to each other. These could | |
67c1ffbe | 4156 | * probably be handled by some kind of table or grammar approach instead of |
252b5132 RH |
4157 | * this verbose method. Others are not simple macros but are more like |
4158 | * optimizing code generation. | |
4159 | * One interesting optimization is when several store macros appear | |
67c1ffbe | 4160 | * consecutively that would load AT with the upper half of the same address. |
252b5132 RH |
4161 | * The ensuing load upper instructions are ommited. This implies some kind |
4162 | * of global optimization. We currently only optimize within a single macro. | |
4163 | * For many of the load and store macros if the address is specified as a | |
4164 | * constant expression in the first 64k of memory (ie ld $2,0x4000c) we | |
4165 | * first load register 'at' with zero and use it as the base register. The | |
4166 | * mips assembler simply uses register $zero. Just one tiny optimization | |
4167 | * we're missing. | |
4168 | */ | |
4169 | static void | |
17a2f251 | 4170 | macro (struct mips_cl_insn *ip) |
252b5132 RH |
4171 | { |
4172 | register int treg, sreg, dreg, breg; | |
4173 | int tempreg; | |
4174 | int mask; | |
43841e91 | 4175 | int used_at = 0; |
252b5132 RH |
4176 | expressionS expr1; |
4177 | const char *s; | |
4178 | const char *s2; | |
4179 | const char *fmt; | |
4180 | int likely = 0; | |
4181 | int dbl = 0; | |
4182 | int coproc = 0; | |
4183 | int lr = 0; | |
4184 | int imm = 0; | |
1abe91b1 | 4185 | int call = 0; |
252b5132 | 4186 | int off; |
67c0d1eb | 4187 | offsetT maxnum; |
252b5132 | 4188 | bfd_reloc_code_real_type r; |
252b5132 RH |
4189 | int hold_mips_optimize; |
4190 | ||
4191 | assert (! mips_opts.mips16); | |
4192 | ||
4193 | treg = (ip->insn_opcode >> 16) & 0x1f; | |
4194 | dreg = (ip->insn_opcode >> 11) & 0x1f; | |
4195 | sreg = breg = (ip->insn_opcode >> 21) & 0x1f; | |
4196 | mask = ip->insn_mo->mask; | |
4197 | ||
4198 | expr1.X_op = O_constant; | |
4199 | expr1.X_op_symbol = NULL; | |
4200 | expr1.X_add_symbol = NULL; | |
4201 | expr1.X_add_number = 1; | |
4202 | ||
4203 | switch (mask) | |
4204 | { | |
4205 | case M_DABS: | |
4206 | dbl = 1; | |
4207 | case M_ABS: | |
4208 | /* bgez $a0,.+12 | |
4209 | move v0,$a0 | |
4210 | sub v0,$zero,$a0 | |
4211 | */ | |
4212 | ||
b34976b6 | 4213 | mips_emit_delays (TRUE); |
252b5132 RH |
4214 | ++mips_opts.noreorder; |
4215 | mips_any_noreorder = 1; | |
4216 | ||
4217 | expr1.X_add_number = 8; | |
67c0d1eb | 4218 | macro_build (&expr1, "bgez", "s,p", sreg); |
252b5132 | 4219 | if (dreg == sreg) |
67c0d1eb | 4220 | macro_build (NULL, "nop", "", 0); |
252b5132 | 4221 | else |
67c0d1eb RS |
4222 | move_register (dreg, sreg); |
4223 | macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, 0, sreg); | |
252b5132 RH |
4224 | |
4225 | --mips_opts.noreorder; | |
4226 | return; | |
4227 | ||
4228 | case M_ADD_I: | |
4229 | s = "addi"; | |
4230 | s2 = "add"; | |
4231 | goto do_addi; | |
4232 | case M_ADDU_I: | |
4233 | s = "addiu"; | |
4234 | s2 = "addu"; | |
4235 | goto do_addi; | |
4236 | case M_DADD_I: | |
4237 | dbl = 1; | |
4238 | s = "daddi"; | |
4239 | s2 = "dadd"; | |
4240 | goto do_addi; | |
4241 | case M_DADDU_I: | |
4242 | dbl = 1; | |
4243 | s = "daddiu"; | |
4244 | s2 = "daddu"; | |
4245 | do_addi: | |
4246 | if (imm_expr.X_op == O_constant | |
4247 | && imm_expr.X_add_number >= -0x8000 | |
4248 | && imm_expr.X_add_number < 0x8000) | |
4249 | { | |
67c0d1eb | 4250 | macro_build (&imm_expr, s, "t,r,j", treg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
4251 | return; |
4252 | } | |
67c0d1eb RS |
4253 | load_register (AT, &imm_expr, dbl); |
4254 | macro_build (NULL, s2, "d,v,t", treg, sreg, AT); | |
252b5132 RH |
4255 | break; |
4256 | ||
4257 | case M_AND_I: | |
4258 | s = "andi"; | |
4259 | s2 = "and"; | |
4260 | goto do_bit; | |
4261 | case M_OR_I: | |
4262 | s = "ori"; | |
4263 | s2 = "or"; | |
4264 | goto do_bit; | |
4265 | case M_NOR_I: | |
4266 | s = ""; | |
4267 | s2 = "nor"; | |
4268 | goto do_bit; | |
4269 | case M_XOR_I: | |
4270 | s = "xori"; | |
4271 | s2 = "xor"; | |
4272 | do_bit: | |
4273 | if (imm_expr.X_op == O_constant | |
4274 | && imm_expr.X_add_number >= 0 | |
4275 | && imm_expr.X_add_number < 0x10000) | |
4276 | { | |
4277 | if (mask != M_NOR_I) | |
67c0d1eb | 4278 | macro_build (&imm_expr, s, "t,r,i", treg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
4279 | else |
4280 | { | |
67c0d1eb RS |
4281 | macro_build (&imm_expr, "ori", "t,r,i", |
4282 | treg, sreg, BFD_RELOC_LO16); | |
4283 | macro_build (NULL, "nor", "d,v,t", treg, treg, 0); | |
252b5132 RH |
4284 | } |
4285 | return; | |
4286 | } | |
4287 | ||
67c0d1eb RS |
4288 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
4289 | macro_build (NULL, s2, "d,v,t", treg, sreg, AT); | |
252b5132 RH |
4290 | break; |
4291 | ||
4292 | case M_BEQ_I: | |
4293 | s = "beq"; | |
4294 | goto beq_i; | |
4295 | case M_BEQL_I: | |
4296 | s = "beql"; | |
4297 | likely = 1; | |
4298 | goto beq_i; | |
4299 | case M_BNE_I: | |
4300 | s = "bne"; | |
4301 | goto beq_i; | |
4302 | case M_BNEL_I: | |
4303 | s = "bnel"; | |
4304 | likely = 1; | |
4305 | beq_i: | |
4306 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4307 | { | |
67c0d1eb | 4308 | macro_build (&offset_expr, s, "s,t,p", sreg, 0); |
252b5132 RH |
4309 | return; |
4310 | } | |
67c0d1eb RS |
4311 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
4312 | macro_build (&offset_expr, s, "s,t,p", sreg, AT); | |
252b5132 RH |
4313 | break; |
4314 | ||
4315 | case M_BGEL: | |
4316 | likely = 1; | |
4317 | case M_BGE: | |
4318 | if (treg == 0) | |
4319 | { | |
67c0d1eb | 4320 | macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", sreg); |
252b5132 RH |
4321 | return; |
4322 | } | |
4323 | if (sreg == 0) | |
4324 | { | |
67c0d1eb | 4325 | macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", treg); |
252b5132 RH |
4326 | return; |
4327 | } | |
67c0d1eb RS |
4328 | macro_build (NULL, "slt", "d,v,t", AT, sreg, treg); |
4329 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
4330 | break; |
4331 | ||
4332 | case M_BGTL_I: | |
4333 | likely = 1; | |
4334 | case M_BGT_I: | |
4335 | /* check for > max integer */ | |
4336 | maxnum = 0x7fffffff; | |
ca4e0257 | 4337 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
4338 | { |
4339 | maxnum <<= 16; | |
4340 | maxnum |= 0xffff; | |
4341 | maxnum <<= 16; | |
4342 | maxnum |= 0xffff; | |
4343 | } | |
4344 | if (imm_expr.X_op == O_constant | |
4345 | && imm_expr.X_add_number >= maxnum | |
ca4e0257 | 4346 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
4347 | { |
4348 | do_false: | |
4349 | /* result is always false */ | |
4350 | if (! likely) | |
67c0d1eb | 4351 | macro_build (NULL, "nop", "", 0); |
252b5132 | 4352 | else |
67c0d1eb | 4353 | macro_build (&offset_expr, "bnel", "s,t,p", 0, 0); |
252b5132 RH |
4354 | return; |
4355 | } | |
4356 | if (imm_expr.X_op != O_constant) | |
4357 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 4358 | ++imm_expr.X_add_number; |
252b5132 RH |
4359 | /* FALLTHROUGH */ |
4360 | case M_BGE_I: | |
4361 | case M_BGEL_I: | |
4362 | if (mask == M_BGEL_I) | |
4363 | likely = 1; | |
4364 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4365 | { | |
67c0d1eb | 4366 | macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", sreg); |
252b5132 RH |
4367 | return; |
4368 | } | |
4369 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4370 | { | |
67c0d1eb | 4371 | macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", sreg); |
252b5132 RH |
4372 | return; |
4373 | } | |
4374 | maxnum = 0x7fffffff; | |
ca4e0257 | 4375 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
4376 | { |
4377 | maxnum <<= 16; | |
4378 | maxnum |= 0xffff; | |
4379 | maxnum <<= 16; | |
4380 | maxnum |= 0xffff; | |
4381 | } | |
4382 | maxnum = - maxnum - 1; | |
4383 | if (imm_expr.X_op == O_constant | |
4384 | && imm_expr.X_add_number <= maxnum | |
ca4e0257 | 4385 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
4386 | { |
4387 | do_true: | |
4388 | /* result is always true */ | |
4389 | as_warn (_("Branch %s is always true"), ip->insn_mo->name); | |
67c0d1eb | 4390 | macro_build (&offset_expr, "b", "p"); |
252b5132 RH |
4391 | return; |
4392 | } | |
67c0d1eb RS |
4393 | set_at (sreg, 0); |
4394 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
4395 | break; |
4396 | ||
4397 | case M_BGEUL: | |
4398 | likely = 1; | |
4399 | case M_BGEU: | |
4400 | if (treg == 0) | |
4401 | goto do_true; | |
4402 | if (sreg == 0) | |
4403 | { | |
67c0d1eb | 4404 | macro_build (&offset_expr, likely ? "beql" : "beq", |
17a2f251 | 4405 | "s,t,p", 0, treg); |
252b5132 RH |
4406 | return; |
4407 | } | |
67c0d1eb RS |
4408 | macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg); |
4409 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
4410 | break; |
4411 | ||
4412 | case M_BGTUL_I: | |
4413 | likely = 1; | |
4414 | case M_BGTU_I: | |
4415 | if (sreg == 0 | |
ca4e0257 | 4416 | || (HAVE_32BIT_GPRS |
252b5132 | 4417 | && imm_expr.X_op == O_constant |
956cd1d6 | 4418 | && imm_expr.X_add_number == (offsetT) 0xffffffff)) |
252b5132 RH |
4419 | goto do_false; |
4420 | if (imm_expr.X_op != O_constant) | |
4421 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 4422 | ++imm_expr.X_add_number; |
252b5132 RH |
4423 | /* FALLTHROUGH */ |
4424 | case M_BGEU_I: | |
4425 | case M_BGEUL_I: | |
4426 | if (mask == M_BGEUL_I) | |
4427 | likely = 1; | |
4428 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4429 | goto do_true; | |
4430 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4431 | { | |
67c0d1eb | 4432 | macro_build (&offset_expr, likely ? "bnel" : "bne", |
17a2f251 | 4433 | "s,t,p", sreg, 0); |
252b5132 RH |
4434 | return; |
4435 | } | |
67c0d1eb RS |
4436 | set_at (sreg, 1); |
4437 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
4438 | break; |
4439 | ||
4440 | case M_BGTL: | |
4441 | likely = 1; | |
4442 | case M_BGT: | |
4443 | if (treg == 0) | |
4444 | { | |
67c0d1eb | 4445 | macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", sreg); |
252b5132 RH |
4446 | return; |
4447 | } | |
4448 | if (sreg == 0) | |
4449 | { | |
67c0d1eb | 4450 | macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", treg); |
252b5132 RH |
4451 | return; |
4452 | } | |
67c0d1eb RS |
4453 | macro_build (NULL, "slt", "d,v,t", AT, treg, sreg); |
4454 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
4455 | break; |
4456 | ||
4457 | case M_BGTUL: | |
4458 | likely = 1; | |
4459 | case M_BGTU: | |
4460 | if (treg == 0) | |
4461 | { | |
67c0d1eb | 4462 | macro_build (&offset_expr, likely ? "bnel" : "bne", |
17a2f251 | 4463 | "s,t,p", sreg, 0); |
252b5132 RH |
4464 | return; |
4465 | } | |
4466 | if (sreg == 0) | |
4467 | goto do_false; | |
67c0d1eb RS |
4468 | macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg); |
4469 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
4470 | break; |
4471 | ||
4472 | case M_BLEL: | |
4473 | likely = 1; | |
4474 | case M_BLE: | |
4475 | if (treg == 0) | |
4476 | { | |
67c0d1eb | 4477 | macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", sreg); |
252b5132 RH |
4478 | return; |
4479 | } | |
4480 | if (sreg == 0) | |
4481 | { | |
67c0d1eb | 4482 | macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", treg); |
252b5132 RH |
4483 | return; |
4484 | } | |
67c0d1eb RS |
4485 | macro_build (NULL, "slt", "d,v,t", AT, treg, sreg); |
4486 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
4487 | break; |
4488 | ||
4489 | case M_BLEL_I: | |
4490 | likely = 1; | |
4491 | case M_BLE_I: | |
4492 | maxnum = 0x7fffffff; | |
ca4e0257 | 4493 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
4494 | { |
4495 | maxnum <<= 16; | |
4496 | maxnum |= 0xffff; | |
4497 | maxnum <<= 16; | |
4498 | maxnum |= 0xffff; | |
4499 | } | |
4500 | if (imm_expr.X_op == O_constant | |
4501 | && imm_expr.X_add_number >= maxnum | |
ca4e0257 | 4502 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
4503 | goto do_true; |
4504 | if (imm_expr.X_op != O_constant) | |
4505 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 4506 | ++imm_expr.X_add_number; |
252b5132 RH |
4507 | /* FALLTHROUGH */ |
4508 | case M_BLT_I: | |
4509 | case M_BLTL_I: | |
4510 | if (mask == M_BLTL_I) | |
4511 | likely = 1; | |
4512 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4513 | { | |
67c0d1eb | 4514 | macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", sreg); |
252b5132 RH |
4515 | return; |
4516 | } | |
4517 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4518 | { | |
67c0d1eb | 4519 | macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", sreg); |
252b5132 RH |
4520 | return; |
4521 | } | |
67c0d1eb RS |
4522 | set_at (sreg, 0); |
4523 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
4524 | break; |
4525 | ||
4526 | case M_BLEUL: | |
4527 | likely = 1; | |
4528 | case M_BLEU: | |
4529 | if (treg == 0) | |
4530 | { | |
67c0d1eb | 4531 | macro_build (&offset_expr, likely ? "beql" : "beq", |
17a2f251 | 4532 | "s,t,p", sreg, 0); |
252b5132 RH |
4533 | return; |
4534 | } | |
4535 | if (sreg == 0) | |
4536 | goto do_true; | |
67c0d1eb RS |
4537 | macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg); |
4538 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
4539 | break; |
4540 | ||
4541 | case M_BLEUL_I: | |
4542 | likely = 1; | |
4543 | case M_BLEU_I: | |
4544 | if (sreg == 0 | |
ca4e0257 | 4545 | || (HAVE_32BIT_GPRS |
252b5132 | 4546 | && imm_expr.X_op == O_constant |
956cd1d6 | 4547 | && imm_expr.X_add_number == (offsetT) 0xffffffff)) |
252b5132 RH |
4548 | goto do_true; |
4549 | if (imm_expr.X_op != O_constant) | |
4550 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 4551 | ++imm_expr.X_add_number; |
252b5132 RH |
4552 | /* FALLTHROUGH */ |
4553 | case M_BLTU_I: | |
4554 | case M_BLTUL_I: | |
4555 | if (mask == M_BLTUL_I) | |
4556 | likely = 1; | |
4557 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4558 | goto do_false; | |
4559 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4560 | { | |
67c0d1eb | 4561 | macro_build (&offset_expr, likely ? "beql" : "beq", |
252b5132 RH |
4562 | "s,t,p", sreg, 0); |
4563 | return; | |
4564 | } | |
67c0d1eb RS |
4565 | set_at (sreg, 1); |
4566 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
4567 | break; |
4568 | ||
4569 | case M_BLTL: | |
4570 | likely = 1; | |
4571 | case M_BLT: | |
4572 | if (treg == 0) | |
4573 | { | |
67c0d1eb | 4574 | macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", sreg); |
252b5132 RH |
4575 | return; |
4576 | } | |
4577 | if (sreg == 0) | |
4578 | { | |
67c0d1eb | 4579 | macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", treg); |
252b5132 RH |
4580 | return; |
4581 | } | |
67c0d1eb RS |
4582 | macro_build (NULL, "slt", "d,v,t", AT, sreg, treg); |
4583 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
4584 | break; |
4585 | ||
4586 | case M_BLTUL: | |
4587 | likely = 1; | |
4588 | case M_BLTU: | |
4589 | if (treg == 0) | |
4590 | goto do_false; | |
4591 | if (sreg == 0) | |
4592 | { | |
67c0d1eb | 4593 | macro_build (&offset_expr, likely ? "bnel" : "bne", |
17a2f251 | 4594 | "s,t,p", 0, treg); |
252b5132 RH |
4595 | return; |
4596 | } | |
67c0d1eb RS |
4597 | macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg); |
4598 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
4599 | break; |
4600 | ||
5f74bc13 CD |
4601 | case M_DEXT: |
4602 | { | |
4603 | unsigned long pos; | |
4604 | unsigned long size; | |
4605 | ||
4606 | if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant) | |
4607 | { | |
4608 | as_bad (_("Unsupported large constant")); | |
4609 | pos = size = 1; | |
4610 | } | |
4611 | else | |
4612 | { | |
4613 | pos = (unsigned long) imm_expr.X_add_number; | |
4614 | size = (unsigned long) imm2_expr.X_add_number; | |
4615 | } | |
4616 | ||
4617 | if (pos > 63) | |
4618 | { | |
4619 | as_bad (_("Improper position (%lu)"), pos); | |
4620 | pos = 1; | |
4621 | } | |
4622 | if (size == 0 || size > 64 | |
4623 | || (pos + size - 1) > 63) | |
4624 | { | |
4625 | as_bad (_("Improper extract size (%lu, position %lu)"), | |
4626 | size, pos); | |
4627 | size = 1; | |
4628 | } | |
4629 | ||
4630 | if (size <= 32 && pos < 32) | |
4631 | { | |
4632 | s = "dext"; | |
4633 | fmt = "t,r,+A,+C"; | |
4634 | } | |
4635 | else if (size <= 32) | |
4636 | { | |
4637 | s = "dextu"; | |
4638 | fmt = "t,r,+E,+H"; | |
4639 | } | |
4640 | else | |
4641 | { | |
4642 | s = "dextm"; | |
4643 | fmt = "t,r,+A,+G"; | |
4644 | } | |
67c0d1eb | 4645 | macro_build ((expressionS *) NULL, s, fmt, treg, sreg, pos, size - 1); |
5f74bc13 CD |
4646 | } |
4647 | return; | |
4648 | ||
4649 | case M_DINS: | |
4650 | { | |
4651 | unsigned long pos; | |
4652 | unsigned long size; | |
4653 | ||
4654 | if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant) | |
4655 | { | |
4656 | as_bad (_("Unsupported large constant")); | |
4657 | pos = size = 1; | |
4658 | } | |
4659 | else | |
4660 | { | |
4661 | pos = (unsigned long) imm_expr.X_add_number; | |
4662 | size = (unsigned long) imm2_expr.X_add_number; | |
4663 | } | |
4664 | ||
4665 | if (pos > 63) | |
4666 | { | |
4667 | as_bad (_("Improper position (%lu)"), pos); | |
4668 | pos = 1; | |
4669 | } | |
4670 | if (size == 0 || size > 64 | |
4671 | || (pos + size - 1) > 63) | |
4672 | { | |
4673 | as_bad (_("Improper insert size (%lu, position %lu)"), | |
4674 | size, pos); | |
4675 | size = 1; | |
4676 | } | |
4677 | ||
4678 | if (pos < 32 && (pos + size - 1) < 32) | |
4679 | { | |
4680 | s = "dins"; | |
4681 | fmt = "t,r,+A,+B"; | |
4682 | } | |
4683 | else if (pos >= 32) | |
4684 | { | |
4685 | s = "dinsu"; | |
4686 | fmt = "t,r,+E,+F"; | |
4687 | } | |
4688 | else | |
4689 | { | |
4690 | s = "dinsm"; | |
4691 | fmt = "t,r,+A,+F"; | |
4692 | } | |
67c0d1eb RS |
4693 | macro_build ((expressionS *) NULL, s, fmt, treg, sreg, pos, |
4694 | pos + size - 1); | |
5f74bc13 CD |
4695 | } |
4696 | return; | |
4697 | ||
252b5132 RH |
4698 | case M_DDIV_3: |
4699 | dbl = 1; | |
4700 | case M_DIV_3: | |
4701 | s = "mflo"; | |
4702 | goto do_div3; | |
4703 | case M_DREM_3: | |
4704 | dbl = 1; | |
4705 | case M_REM_3: | |
4706 | s = "mfhi"; | |
4707 | do_div3: | |
4708 | if (treg == 0) | |
4709 | { | |
4710 | as_warn (_("Divide by zero.")); | |
4711 | if (mips_trap) | |
67c0d1eb | 4712 | macro_build (NULL, "teq", "s,t,q", 0, 0, 7); |
252b5132 | 4713 | else |
67c0d1eb | 4714 | macro_build (NULL, "break", "c", 7); |
252b5132 RH |
4715 | return; |
4716 | } | |
4717 | ||
b34976b6 | 4718 | mips_emit_delays (TRUE); |
252b5132 RH |
4719 | ++mips_opts.noreorder; |
4720 | mips_any_noreorder = 1; | |
4721 | if (mips_trap) | |
4722 | { | |
67c0d1eb RS |
4723 | macro_build (NULL, "teq", "s,t,q", treg, 0, 7); |
4724 | macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg); | |
252b5132 RH |
4725 | } |
4726 | else | |
4727 | { | |
4728 | expr1.X_add_number = 8; | |
67c0d1eb RS |
4729 | macro_build (&expr1, "bne", "s,t,p", treg, 0); |
4730 | macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg); | |
4731 | macro_build (NULL, "break", "c", 7); | |
252b5132 RH |
4732 | } |
4733 | expr1.X_add_number = -1; | |
f6a22291 | 4734 | load_register (AT, &expr1, dbl); |
252b5132 | 4735 | expr1.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16); |
67c0d1eb | 4736 | macro_build (&expr1, "bne", "s,t,p", treg, AT); |
252b5132 RH |
4737 | if (dbl) |
4738 | { | |
4739 | expr1.X_add_number = 1; | |
f6a22291 | 4740 | load_register (AT, &expr1, dbl); |
67c0d1eb | 4741 | macro_build (NULL, "dsll32", "d,w,<", AT, AT, 31); |
252b5132 RH |
4742 | } |
4743 | else | |
4744 | { | |
4745 | expr1.X_add_number = 0x80000000; | |
67c0d1eb | 4746 | macro_build (&expr1, "lui", "t,u", AT, BFD_RELOC_HI16); |
252b5132 RH |
4747 | } |
4748 | if (mips_trap) | |
4749 | { | |
67c0d1eb | 4750 | macro_build (NULL, "teq", "s,t,q", sreg, AT, 6); |
252b5132 RH |
4751 | /* We want to close the noreorder block as soon as possible, so |
4752 | that later insns are available for delay slot filling. */ | |
4753 | --mips_opts.noreorder; | |
4754 | } | |
4755 | else | |
4756 | { | |
4757 | expr1.X_add_number = 8; | |
67c0d1eb RS |
4758 | macro_build (&expr1, "bne", "s,t,p", sreg, AT); |
4759 | macro_build (NULL, "nop", "", 0); | |
252b5132 RH |
4760 | |
4761 | /* We want to close the noreorder block as soon as possible, so | |
4762 | that later insns are available for delay slot filling. */ | |
4763 | --mips_opts.noreorder; | |
4764 | ||
67c0d1eb | 4765 | macro_build (NULL, "break", "c", 6); |
252b5132 | 4766 | } |
67c0d1eb | 4767 | macro_build (NULL, s, "d", dreg); |
252b5132 RH |
4768 | break; |
4769 | ||
4770 | case M_DIV_3I: | |
4771 | s = "div"; | |
4772 | s2 = "mflo"; | |
4773 | goto do_divi; | |
4774 | case M_DIVU_3I: | |
4775 | s = "divu"; | |
4776 | s2 = "mflo"; | |
4777 | goto do_divi; | |
4778 | case M_REM_3I: | |
4779 | s = "div"; | |
4780 | s2 = "mfhi"; | |
4781 | goto do_divi; | |
4782 | case M_REMU_3I: | |
4783 | s = "divu"; | |
4784 | s2 = "mfhi"; | |
4785 | goto do_divi; | |
4786 | case M_DDIV_3I: | |
4787 | dbl = 1; | |
4788 | s = "ddiv"; | |
4789 | s2 = "mflo"; | |
4790 | goto do_divi; | |
4791 | case M_DDIVU_3I: | |
4792 | dbl = 1; | |
4793 | s = "ddivu"; | |
4794 | s2 = "mflo"; | |
4795 | goto do_divi; | |
4796 | case M_DREM_3I: | |
4797 | dbl = 1; | |
4798 | s = "ddiv"; | |
4799 | s2 = "mfhi"; | |
4800 | goto do_divi; | |
4801 | case M_DREMU_3I: | |
4802 | dbl = 1; | |
4803 | s = "ddivu"; | |
4804 | s2 = "mfhi"; | |
4805 | do_divi: | |
4806 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4807 | { | |
4808 | as_warn (_("Divide by zero.")); | |
4809 | if (mips_trap) | |
67c0d1eb | 4810 | macro_build (NULL, "teq", "s,t,q", 0, 0, 7); |
252b5132 | 4811 | else |
67c0d1eb | 4812 | macro_build (NULL, "break", "c", 7); |
252b5132 RH |
4813 | return; |
4814 | } | |
4815 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4816 | { | |
4817 | if (strcmp (s2, "mflo") == 0) | |
67c0d1eb | 4818 | move_register (dreg, sreg); |
252b5132 | 4819 | else |
67c0d1eb | 4820 | move_register (dreg, 0); |
252b5132 RH |
4821 | return; |
4822 | } | |
4823 | if (imm_expr.X_op == O_constant | |
4824 | && imm_expr.X_add_number == -1 | |
4825 | && s[strlen (s) - 1] != 'u') | |
4826 | { | |
4827 | if (strcmp (s2, "mflo") == 0) | |
4828 | { | |
67c0d1eb | 4829 | macro_build (NULL, dbl ? "dneg" : "neg", "d,w", dreg, sreg); |
252b5132 RH |
4830 | } |
4831 | else | |
67c0d1eb | 4832 | move_register (dreg, 0); |
252b5132 RH |
4833 | return; |
4834 | } | |
4835 | ||
67c0d1eb RS |
4836 | load_register (AT, &imm_expr, dbl); |
4837 | macro_build (NULL, s, "z,s,t", sreg, AT); | |
4838 | macro_build (NULL, s2, "d", dreg); | |
252b5132 RH |
4839 | break; |
4840 | ||
4841 | case M_DIVU_3: | |
4842 | s = "divu"; | |
4843 | s2 = "mflo"; | |
4844 | goto do_divu3; | |
4845 | case M_REMU_3: | |
4846 | s = "divu"; | |
4847 | s2 = "mfhi"; | |
4848 | goto do_divu3; | |
4849 | case M_DDIVU_3: | |
4850 | s = "ddivu"; | |
4851 | s2 = "mflo"; | |
4852 | goto do_divu3; | |
4853 | case M_DREMU_3: | |
4854 | s = "ddivu"; | |
4855 | s2 = "mfhi"; | |
4856 | do_divu3: | |
b34976b6 | 4857 | mips_emit_delays (TRUE); |
252b5132 RH |
4858 | ++mips_opts.noreorder; |
4859 | mips_any_noreorder = 1; | |
4860 | if (mips_trap) | |
4861 | { | |
67c0d1eb RS |
4862 | macro_build (NULL, "teq", "s,t,q", treg, 0, 7); |
4863 | macro_build (NULL, s, "z,s,t", sreg, treg); | |
252b5132 RH |
4864 | /* We want to close the noreorder block as soon as possible, so |
4865 | that later insns are available for delay slot filling. */ | |
4866 | --mips_opts.noreorder; | |
4867 | } | |
4868 | else | |
4869 | { | |
4870 | expr1.X_add_number = 8; | |
67c0d1eb RS |
4871 | macro_build (&expr1, "bne", "s,t,p", treg, 0); |
4872 | macro_build (NULL, s, "z,s,t", sreg, treg); | |
252b5132 RH |
4873 | |
4874 | /* We want to close the noreorder block as soon as possible, so | |
4875 | that later insns are available for delay slot filling. */ | |
4876 | --mips_opts.noreorder; | |
67c0d1eb | 4877 | macro_build (NULL, "break", "c", 7); |
252b5132 | 4878 | } |
67c0d1eb | 4879 | macro_build (NULL, s2, "d", dreg); |
252b5132 RH |
4880 | return; |
4881 | ||
1abe91b1 MR |
4882 | case M_DLCA_AB: |
4883 | dbl = 1; | |
4884 | case M_LCA_AB: | |
4885 | call = 1; | |
4886 | goto do_la; | |
252b5132 RH |
4887 | case M_DLA_AB: |
4888 | dbl = 1; | |
4889 | case M_LA_AB: | |
1abe91b1 | 4890 | do_la: |
252b5132 RH |
4891 | /* Load the address of a symbol into a register. If breg is not |
4892 | zero, we then add a base register to it. */ | |
4893 | ||
3bec30a8 TS |
4894 | if (dbl && HAVE_32BIT_GPRS) |
4895 | as_warn (_("dla used to load 32-bit register")); | |
4896 | ||
c90bbe5b | 4897 | if (! dbl && HAVE_64BIT_OBJECTS) |
3bec30a8 TS |
4898 | as_warn (_("la used to load 64-bit address")); |
4899 | ||
0c11417f MR |
4900 | if (offset_expr.X_op == O_constant |
4901 | && offset_expr.X_add_number >= -0x8000 | |
4902 | && offset_expr.X_add_number < 0x8000) | |
4903 | { | |
67c0d1eb | 4904 | macro_build (&offset_expr, |
b7c7d6c1 | 4905 | (dbl || HAVE_64BIT_ADDRESSES) ? "daddiu" : "addiu", |
17a2f251 | 4906 | "t,r,j", treg, sreg, BFD_RELOC_LO16); |
0c11417f MR |
4907 | return; |
4908 | } | |
4909 | ||
b8285c27 | 4910 | if (!mips_opts.noat && (treg == breg)) |
afdbd6d0 CD |
4911 | { |
4912 | tempreg = AT; | |
4913 | used_at = 1; | |
4914 | } | |
4915 | else | |
4916 | { | |
4917 | tempreg = treg; | |
afdbd6d0 CD |
4918 | } |
4919 | ||
252b5132 RH |
4920 | if (offset_expr.X_op != O_symbol |
4921 | && offset_expr.X_op != O_constant) | |
4922 | { | |
4923 | as_bad (_("expression too complex")); | |
4924 | offset_expr.X_op = O_constant; | |
4925 | } | |
4926 | ||
252b5132 | 4927 | if (offset_expr.X_op == O_constant) |
67c0d1eb | 4928 | load_register (tempreg, &offset_expr, |
3e722fb5 | 4929 | (mips_pic == NO_PIC |
4d34fb5f TS |
4930 | ? (dbl || HAVE_64BIT_ADDRESSES) |
4931 | : HAVE_64BIT_ADDRESSES)); | |
252b5132 RH |
4932 | else if (mips_pic == NO_PIC) |
4933 | { | |
d6bc6245 | 4934 | /* If this is a reference to a GP relative symbol, we want |
cdf6fd85 | 4935 | addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
4936 | Otherwise we want |
4937 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
4938 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
4939 | If we have a constant, we need two instructions anyhow, | |
d6bc6245 | 4940 | so we may as well always use the latter form. |
76b3015f | 4941 | |
d6bc6245 TS |
4942 | With 64bit address space and a usable $at we want |
4943 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
4944 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
4945 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
4946 | daddiu $at,<sym> (BFD_RELOC_LO16) | |
4947 | dsll32 $tempreg,0 | |
3a482fd5 | 4948 | daddu $tempreg,$tempreg,$at |
76b3015f | 4949 | |
c03099e6 | 4950 | If $at is already in use, we use a path which is suboptimal |
d6bc6245 TS |
4951 | on superscalar processors. |
4952 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
4953 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
4954 | dsll $tempreg,16 | |
4955 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
4956 | dsll $tempreg,16 | |
4957 | daddiu $tempreg,<sym> (BFD_RELOC_LO16) | |
4958 | */ | |
d6bc6245 | 4959 | if (HAVE_64BIT_ADDRESSES) |
252b5132 | 4960 | { |
e864ceca RS |
4961 | /* ??? We don't provide a GP-relative alternative for |
4962 | these macros. It used not to be possible with the | |
4963 | original relaxation code, but it could be done now. */ | |
d6bc6245 | 4964 | |
b8285c27 | 4965 | if (used_at == 0 && !mips_opts.noat) |
98d3f06f | 4966 | { |
67c0d1eb | 4967 | macro_build (&offset_expr, "lui", "t,u", |
17a2f251 | 4968 | tempreg, BFD_RELOC_MIPS_HIGHEST); |
67c0d1eb | 4969 | macro_build (&offset_expr, "lui", "t,u", |
17a2f251 | 4970 | AT, BFD_RELOC_HI16_S); |
67c0d1eb | 4971 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 4972 | tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); |
67c0d1eb | 4973 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 4974 | AT, AT, BFD_RELOC_LO16); |
67c0d1eb RS |
4975 | macro_build (NULL, "dsll32", "d,w,<", tempreg, tempreg, 0); |
4976 | macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT); | |
98d3f06f KH |
4977 | used_at = 1; |
4978 | } | |
4979 | else | |
4980 | { | |
67c0d1eb | 4981 | macro_build (&offset_expr, "lui", "t,u", |
17a2f251 | 4982 | tempreg, BFD_RELOC_MIPS_HIGHEST); |
67c0d1eb | 4983 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 4984 | tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); |
67c0d1eb RS |
4985 | macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16); |
4986 | macro_build (&offset_expr, "daddiu", "t,r,j", | |
17a2f251 | 4987 | tempreg, tempreg, BFD_RELOC_HI16_S); |
67c0d1eb RS |
4988 | macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16); |
4989 | macro_build (&offset_expr, "daddiu", "t,r,j", | |
17a2f251 | 4990 | tempreg, tempreg, BFD_RELOC_LO16); |
98d3f06f KH |
4991 | } |
4992 | } | |
4993 | else | |
4994 | { | |
4995 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET | |
4996 | && ! nopic_need_relax (offset_expr.X_add_symbol, 1)) | |
4997 | { | |
4d7206a2 | 4998 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
4999 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
5000 | tempreg, mips_gp_register, BFD_RELOC_GPREL16); | |
4d7206a2 | 5001 | relax_switch (); |
98d3f06f | 5002 | } |
6943caf0 ILT |
5003 | if (!IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) |
5004 | as_bad (_("offset too large")); | |
67c0d1eb RS |
5005 | macro_build_lui (&offset_expr, tempreg); |
5006 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
5007 | tempreg, tempreg, BFD_RELOC_LO16); | |
4d7206a2 RS |
5008 | if (mips_relax.sequence) |
5009 | relax_end (); | |
98d3f06f | 5010 | } |
252b5132 | 5011 | } |
f5040a92 | 5012 | else if (mips_pic == SVR4_PIC && ! mips_big_got && ! HAVE_NEWABI) |
252b5132 | 5013 | { |
9117d219 NC |
5014 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
5015 | ||
252b5132 RH |
5016 | /* If this is a reference to an external symbol, and there |
5017 | is no constant, we want | |
5018 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
1abe91b1 | 5019 | or for lca or if tempreg is PIC_CALL_REG |
9117d219 | 5020 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
252b5132 RH |
5021 | For a local symbol, we want |
5022 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5023 | nop | |
5024 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
5025 | ||
5026 | If we have a small constant, and this is a reference to | |
5027 | an external symbol, we want | |
5028 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5029 | nop | |
5030 | addiu $tempreg,$tempreg,<constant> | |
5031 | For a local symbol, we want the same instruction | |
5032 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
5033 | addiu instruction. | |
5034 | ||
5035 | If we have a large constant, and this is a reference to | |
5036 | an external symbol, we want | |
5037 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5038 | lui $at,<hiconstant> | |
5039 | addiu $at,$at,<loconstant> | |
5040 | addu $tempreg,$tempreg,$at | |
5041 | For a local symbol, we want the same instruction | |
5042 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
ed6fb7bd | 5043 | addiu instruction. |
ed6fb7bd SC |
5044 | */ |
5045 | ||
4d7206a2 | 5046 | if (offset_expr.X_add_number == 0) |
252b5132 | 5047 | { |
4d7206a2 RS |
5048 | if (breg == 0 && (call || tempreg == PIC_CALL_REG)) |
5049 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16; | |
5050 | ||
5051 | relax_start (offset_expr.X_add_symbol); | |
67c0d1eb RS |
5052 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5053 | lw_reloc_type, mips_gp_register); | |
4d7206a2 | 5054 | if (breg != 0) |
252b5132 RH |
5055 | { |
5056 | /* We're going to put in an addu instruction using | |
5057 | tempreg, so we may as well insert the nop right | |
5058 | now. */ | |
269137b2 | 5059 | load_delay_nop (); |
252b5132 | 5060 | } |
4d7206a2 | 5061 | relax_switch (); |
67c0d1eb RS |
5062 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5063 | tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 5064 | load_delay_nop (); |
67c0d1eb RS |
5065 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
5066 | tempreg, tempreg, BFD_RELOC_LO16); | |
4d7206a2 | 5067 | relax_end (); |
252b5132 RH |
5068 | /* FIXME: If breg == 0, and the next instruction uses |
5069 | $tempreg, then if this variant case is used an extra | |
5070 | nop will be generated. */ | |
5071 | } | |
4d7206a2 RS |
5072 | else if (offset_expr.X_add_number >= -0x8000 |
5073 | && offset_expr.X_add_number < 0x8000) | |
252b5132 | 5074 | { |
67c0d1eb | 5075 | load_got_offset (tempreg, &offset_expr); |
269137b2 | 5076 | load_delay_nop (); |
67c0d1eb | 5077 | add_got_offset (tempreg, &offset_expr); |
252b5132 RH |
5078 | } |
5079 | else | |
5080 | { | |
4d7206a2 RS |
5081 | expr1.X_add_number = offset_expr.X_add_number; |
5082 | offset_expr.X_add_number = | |
5083 | ((offset_expr.X_add_number + 0x8000) & 0xffff) - 0x8000; | |
67c0d1eb | 5084 | load_got_offset (tempreg, &offset_expr); |
f6a22291 | 5085 | offset_expr.X_add_number = expr1.X_add_number; |
252b5132 RH |
5086 | /* If we are going to add in a base register, and the |
5087 | target register and the base register are the same, | |
5088 | then we are using AT as a temporary register. Since | |
5089 | we want to load the constant into AT, we add our | |
5090 | current AT (from the global offset table) and the | |
5091 | register into the register now, and pretend we were | |
5092 | not using a base register. */ | |
67c0d1eb | 5093 | if (breg == treg) |
252b5132 | 5094 | { |
269137b2 | 5095 | load_delay_nop (); |
67c0d1eb | 5096 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5097 | treg, AT, breg); |
252b5132 RH |
5098 | breg = 0; |
5099 | tempreg = treg; | |
252b5132 | 5100 | } |
f6a22291 | 5101 | add_got_offset_hilo (tempreg, &offset_expr, AT); |
252b5132 RH |
5102 | used_at = 1; |
5103 | } | |
5104 | } | |
f5040a92 AO |
5105 | else if (mips_pic == SVR4_PIC && ! mips_big_got && HAVE_NEWABI) |
5106 | { | |
67c0d1eb | 5107 | int add_breg_early = 0; |
f5040a92 AO |
5108 | |
5109 | /* If this is a reference to an external, and there is no | |
5110 | constant, or local symbol (*), with or without a | |
5111 | constant, we want | |
5112 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
1abe91b1 | 5113 | or for lca or if tempreg is PIC_CALL_REG |
f5040a92 AO |
5114 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
5115 | ||
5116 | If we have a small constant, and this is a reference to | |
5117 | an external symbol, we want | |
5118 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
5119 | addiu $tempreg,$tempreg,<constant> | |
5120 | ||
5121 | If we have a large constant, and this is a reference to | |
5122 | an external symbol, we want | |
5123 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
5124 | lui $at,<hiconstant> | |
5125 | addiu $at,$at,<loconstant> | |
5126 | addu $tempreg,$tempreg,$at | |
5127 | ||
5128 | (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for | |
5129 | local symbols, even though it introduces an additional | |
5130 | instruction. */ | |
5131 | ||
f5040a92 AO |
5132 | if (offset_expr.X_add_number) |
5133 | { | |
4d7206a2 | 5134 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
5135 | offset_expr.X_add_number = 0; |
5136 | ||
4d7206a2 | 5137 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
5138 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5139 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
5140 | |
5141 | if (expr1.X_add_number >= -0x8000 | |
5142 | && expr1.X_add_number < 0x8000) | |
5143 | { | |
67c0d1eb RS |
5144 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
5145 | tempreg, tempreg, BFD_RELOC_LO16); | |
f5040a92 | 5146 | } |
ecd13cd3 | 5147 | else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000)) |
f5040a92 AO |
5148 | { |
5149 | int dreg; | |
5150 | ||
5151 | /* If we are going to add in a base register, and the | |
5152 | target register and the base register are the same, | |
5153 | then we are using AT as a temporary register. Since | |
5154 | we want to load the constant into AT, we add our | |
5155 | current AT (from the global offset table) and the | |
5156 | register into the register now, and pretend we were | |
5157 | not using a base register. */ | |
5158 | if (breg != treg) | |
5159 | dreg = tempreg; | |
5160 | else | |
5161 | { | |
5162 | assert (tempreg == AT); | |
67c0d1eb RS |
5163 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
5164 | treg, AT, breg); | |
f5040a92 | 5165 | dreg = treg; |
67c0d1eb | 5166 | add_breg_early = 1; |
f5040a92 AO |
5167 | } |
5168 | ||
f6a22291 | 5169 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 5170 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5171 | dreg, dreg, AT); |
f5040a92 | 5172 | |
f5040a92 AO |
5173 | used_at = 1; |
5174 | } | |
5175 | else | |
5176 | as_bad (_("PIC code offset overflow (max 32 signed bits)")); | |
5177 | ||
4d7206a2 | 5178 | relax_switch (); |
f5040a92 AO |
5179 | offset_expr.X_add_number = expr1.X_add_number; |
5180 | ||
67c0d1eb RS |
5181 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5182 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
5183 | if (add_breg_early) | |
f5040a92 | 5184 | { |
67c0d1eb | 5185 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
f899b4b8 | 5186 | treg, tempreg, breg); |
f5040a92 AO |
5187 | breg = 0; |
5188 | tempreg = treg; | |
5189 | } | |
4d7206a2 | 5190 | relax_end (); |
f5040a92 | 5191 | } |
4d7206a2 | 5192 | else if (breg == 0 && (call || tempreg == PIC_CALL_REG)) |
f5040a92 | 5193 | { |
4d7206a2 | 5194 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
5195 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5196 | BFD_RELOC_MIPS_CALL16, mips_gp_register); | |
4d7206a2 | 5197 | relax_switch (); |
67c0d1eb RS |
5198 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5199 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
4d7206a2 | 5200 | relax_end (); |
f5040a92 | 5201 | } |
4d7206a2 | 5202 | else |
f5040a92 | 5203 | { |
67c0d1eb RS |
5204 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5205 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
5206 | } |
5207 | } | |
5208 | else if (mips_pic == SVR4_PIC && ! HAVE_NEWABI) | |
252b5132 | 5209 | { |
67c0d1eb | 5210 | int gpdelay; |
9117d219 NC |
5211 | int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; |
5212 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; | |
ed6fb7bd | 5213 | int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
252b5132 RH |
5214 | |
5215 | /* This is the large GOT case. If this is a reference to an | |
5216 | external symbol, and there is no constant, we want | |
5217 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5218 | addu $tempreg,$tempreg,$gp | |
5219 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
1abe91b1 | 5220 | or for lca or if tempreg is PIC_CALL_REG |
9117d219 NC |
5221 | lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) |
5222 | addu $tempreg,$tempreg,$gp | |
5223 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) | |
252b5132 RH |
5224 | For a local symbol, we want |
5225 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5226 | nop | |
5227 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
5228 | ||
5229 | If we have a small constant, and this is a reference to | |
5230 | an external symbol, we want | |
5231 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5232 | addu $tempreg,$tempreg,$gp | |
5233 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5234 | nop | |
5235 | addiu $tempreg,$tempreg,<constant> | |
5236 | For a local symbol, we want | |
5237 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5238 | nop | |
5239 | addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16) | |
5240 | ||
5241 | If we have a large constant, and this is a reference to | |
5242 | an external symbol, we want | |
5243 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5244 | addu $tempreg,$tempreg,$gp | |
5245 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5246 | lui $at,<hiconstant> | |
5247 | addiu $at,$at,<loconstant> | |
5248 | addu $tempreg,$tempreg,$at | |
5249 | For a local symbol, we want | |
5250 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5251 | lui $at,<hiconstant> | |
5252 | addiu $at,$at,<loconstant> (BFD_RELOC_LO16) | |
5253 | addu $tempreg,$tempreg,$at | |
f5040a92 | 5254 | */ |
438c16b8 | 5255 | |
252b5132 RH |
5256 | expr1.X_add_number = offset_expr.X_add_number; |
5257 | offset_expr.X_add_number = 0; | |
4d7206a2 | 5258 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 5259 | gpdelay = reg_needs_delay (mips_gp_register); |
1abe91b1 MR |
5260 | if (expr1.X_add_number == 0 && breg == 0 |
5261 | && (call || tempreg == PIC_CALL_REG)) | |
9117d219 NC |
5262 | { |
5263 | lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; | |
5264 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; | |
5265 | } | |
67c0d1eb RS |
5266 | macro_build (&offset_expr, "lui", "t,u", tempreg, lui_reloc_type); |
5267 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 5268 | tempreg, tempreg, mips_gp_register); |
67c0d1eb | 5269 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
17a2f251 | 5270 | tempreg, lw_reloc_type, tempreg); |
252b5132 RH |
5271 | if (expr1.X_add_number == 0) |
5272 | { | |
67c0d1eb | 5273 | if (breg != 0) |
252b5132 RH |
5274 | { |
5275 | /* We're going to put in an addu instruction using | |
5276 | tempreg, so we may as well insert the nop right | |
5277 | now. */ | |
269137b2 | 5278 | load_delay_nop (); |
252b5132 | 5279 | } |
252b5132 RH |
5280 | } |
5281 | else if (expr1.X_add_number >= -0x8000 | |
5282 | && expr1.X_add_number < 0x8000) | |
5283 | { | |
269137b2 | 5284 | load_delay_nop (); |
67c0d1eb | 5285 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 5286 | tempreg, tempreg, BFD_RELOC_LO16); |
252b5132 RH |
5287 | } |
5288 | else | |
5289 | { | |
67c0d1eb | 5290 | int dreg; |
252b5132 RH |
5291 | |
5292 | /* If we are going to add in a base register, and the | |
5293 | target register and the base register are the same, | |
5294 | then we are using AT as a temporary register. Since | |
5295 | we want to load the constant into AT, we add our | |
5296 | current AT (from the global offset table) and the | |
5297 | register into the register now, and pretend we were | |
5298 | not using a base register. */ | |
5299 | if (breg != treg) | |
67c0d1eb | 5300 | dreg = tempreg; |
252b5132 RH |
5301 | else |
5302 | { | |
5303 | assert (tempreg == AT); | |
269137b2 | 5304 | load_delay_nop (); |
67c0d1eb | 5305 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5306 | treg, AT, breg); |
252b5132 | 5307 | dreg = treg; |
252b5132 RH |
5308 | } |
5309 | ||
f6a22291 | 5310 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 5311 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT); |
252b5132 | 5312 | |
252b5132 RH |
5313 | used_at = 1; |
5314 | } | |
4d7206a2 RS |
5315 | offset_expr.X_add_number = |
5316 | ((expr1.X_add_number + 0x8000) & 0xffff) - 0x8000; | |
5317 | relax_switch (); | |
252b5132 | 5318 | |
67c0d1eb | 5319 | if (gpdelay) |
252b5132 RH |
5320 | { |
5321 | /* This is needed because this instruction uses $gp, but | |
f5040a92 | 5322 | the first instruction on the main stream does not. */ |
67c0d1eb | 5323 | macro_build (NULL, "nop", ""); |
252b5132 | 5324 | } |
ed6fb7bd | 5325 | |
67c0d1eb RS |
5326 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5327 | local_reloc_type, mips_gp_register); | |
f5040a92 | 5328 | if (expr1.X_add_number >= -0x8000 |
252b5132 RH |
5329 | && expr1.X_add_number < 0x8000) |
5330 | { | |
269137b2 | 5331 | load_delay_nop (); |
67c0d1eb RS |
5332 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
5333 | tempreg, tempreg, BFD_RELOC_LO16); | |
252b5132 | 5334 | /* FIXME: If add_number is 0, and there was no base |
f5040a92 AO |
5335 | register, the external symbol case ended with a load, |
5336 | so if the symbol turns out to not be external, and | |
5337 | the next instruction uses tempreg, an unnecessary nop | |
5338 | will be inserted. */ | |
252b5132 RH |
5339 | } |
5340 | else | |
5341 | { | |
5342 | if (breg == treg) | |
5343 | { | |
5344 | /* We must add in the base register now, as in the | |
f5040a92 | 5345 | external symbol case. */ |
252b5132 | 5346 | assert (tempreg == AT); |
269137b2 | 5347 | load_delay_nop (); |
67c0d1eb | 5348 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5349 | treg, AT, breg); |
252b5132 RH |
5350 | tempreg = treg; |
5351 | /* We set breg to 0 because we have arranged to add | |
f5040a92 | 5352 | it in in both cases. */ |
252b5132 RH |
5353 | breg = 0; |
5354 | } | |
5355 | ||
67c0d1eb RS |
5356 | macro_build_lui (&expr1, AT); |
5357 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
17a2f251 | 5358 | AT, AT, BFD_RELOC_LO16); |
67c0d1eb | 5359 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5360 | tempreg, tempreg, AT); |
252b5132 | 5361 | } |
4d7206a2 | 5362 | relax_end (); |
252b5132 | 5363 | } |
f5040a92 AO |
5364 | else if (mips_pic == SVR4_PIC && HAVE_NEWABI) |
5365 | { | |
f5040a92 AO |
5366 | int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; |
5367 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; | |
67c0d1eb | 5368 | int add_breg_early = 0; |
f5040a92 AO |
5369 | |
5370 | /* This is the large GOT case. If this is a reference to an | |
5371 | external symbol, and there is no constant, we want | |
5372 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5373 | add $tempreg,$tempreg,$gp | |
5374 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
1abe91b1 | 5375 | or for lca or if tempreg is PIC_CALL_REG |
f5040a92 AO |
5376 | lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) |
5377 | add $tempreg,$tempreg,$gp | |
5378 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) | |
5379 | ||
5380 | If we have a small constant, and this is a reference to | |
5381 | an external symbol, we want | |
5382 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5383 | add $tempreg,$tempreg,$gp | |
5384 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5385 | addi $tempreg,$tempreg,<constant> | |
5386 | ||
5387 | If we have a large constant, and this is a reference to | |
5388 | an external symbol, we want | |
5389 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5390 | addu $tempreg,$tempreg,$gp | |
5391 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5392 | lui $at,<hiconstant> | |
5393 | addi $at,$at,<loconstant> | |
5394 | add $tempreg,$tempreg,$at | |
5395 | ||
5396 | If we have NewABI, and we know it's a local symbol, we want | |
5397 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
5398 | addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) | |
5399 | otherwise we have to resort to GOT_HI16/GOT_LO16. */ | |
5400 | ||
4d7206a2 | 5401 | relax_start (offset_expr.X_add_symbol); |
f5040a92 | 5402 | |
4d7206a2 | 5403 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
5404 | offset_expr.X_add_number = 0; |
5405 | ||
1abe91b1 MR |
5406 | if (expr1.X_add_number == 0 && breg == 0 |
5407 | && (call || tempreg == PIC_CALL_REG)) | |
f5040a92 AO |
5408 | { |
5409 | lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; | |
5410 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; | |
5411 | } | |
67c0d1eb RS |
5412 | macro_build (&offset_expr, "lui", "t,u", tempreg, lui_reloc_type); |
5413 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 5414 | tempreg, tempreg, mips_gp_register); |
67c0d1eb RS |
5415 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5416 | tempreg, lw_reloc_type, tempreg); | |
f5040a92 AO |
5417 | |
5418 | if (expr1.X_add_number == 0) | |
4d7206a2 | 5419 | ; |
f5040a92 AO |
5420 | else if (expr1.X_add_number >= -0x8000 |
5421 | && expr1.X_add_number < 0x8000) | |
5422 | { | |
67c0d1eb | 5423 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 5424 | tempreg, tempreg, BFD_RELOC_LO16); |
f5040a92 | 5425 | } |
ecd13cd3 | 5426 | else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000)) |
f5040a92 AO |
5427 | { |
5428 | int dreg; | |
5429 | ||
5430 | /* If we are going to add in a base register, and the | |
5431 | target register and the base register are the same, | |
5432 | then we are using AT as a temporary register. Since | |
5433 | we want to load the constant into AT, we add our | |
5434 | current AT (from the global offset table) and the | |
5435 | register into the register now, and pretend we were | |
5436 | not using a base register. */ | |
5437 | if (breg != treg) | |
5438 | dreg = tempreg; | |
5439 | else | |
5440 | { | |
5441 | assert (tempreg == AT); | |
67c0d1eb | 5442 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5443 | treg, AT, breg); |
f5040a92 | 5444 | dreg = treg; |
67c0d1eb | 5445 | add_breg_early = 1; |
f5040a92 AO |
5446 | } |
5447 | ||
f6a22291 | 5448 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 5449 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT); |
f5040a92 | 5450 | |
f5040a92 AO |
5451 | used_at = 1; |
5452 | } | |
5453 | else | |
5454 | as_bad (_("PIC code offset overflow (max 32 signed bits)")); | |
5455 | ||
4d7206a2 | 5456 | relax_switch (); |
f5040a92 | 5457 | offset_expr.X_add_number = expr1.X_add_number; |
67c0d1eb RS |
5458 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5459 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
5460 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, | |
5461 | tempreg, BFD_RELOC_MIPS_GOT_OFST); | |
5462 | if (add_breg_early) | |
f5040a92 | 5463 | { |
67c0d1eb | 5464 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5465 | treg, tempreg, breg); |
f5040a92 AO |
5466 | breg = 0; |
5467 | tempreg = treg; | |
5468 | } | |
4d7206a2 | 5469 | relax_end (); |
f5040a92 | 5470 | } |
252b5132 RH |
5471 | else |
5472 | abort (); | |
5473 | ||
5474 | if (breg != 0) | |
4d34fb5f TS |
5475 | { |
5476 | char *s; | |
5477 | ||
3e722fb5 | 5478 | if (mips_pic == NO_PIC) |
b7c7d6c1 | 5479 | s = (dbl || HAVE_64BIT_ADDRESSES) ? "daddu" : "addu"; |
4d34fb5f | 5480 | else |
f899b4b8 | 5481 | s = ADDRESS_ADD_INSN; |
4d34fb5f | 5482 | |
67c0d1eb | 5483 | macro_build (NULL, s, "d,v,t", treg, tempreg, breg); |
4d34fb5f | 5484 | } |
252b5132 | 5485 | |
b8285c27 | 5486 | if (!used_at) |
252b5132 RH |
5487 | return; |
5488 | ||
5489 | break; | |
5490 | ||
5491 | case M_J_A: | |
5492 | /* The j instruction may not be used in PIC code, since it | |
5493 | requires an absolute address. We convert it to a b | |
5494 | instruction. */ | |
5495 | if (mips_pic == NO_PIC) | |
67c0d1eb | 5496 | macro_build (&offset_expr, "j", "a"); |
252b5132 | 5497 | else |
67c0d1eb | 5498 | macro_build (&offset_expr, "b", "p"); |
252b5132 RH |
5499 | return; |
5500 | ||
5501 | /* The jal instructions must be handled as macros because when | |
5502 | generating PIC code they expand to multi-instruction | |
5503 | sequences. Normally they are simple instructions. */ | |
5504 | case M_JAL_1: | |
5505 | dreg = RA; | |
5506 | /* Fall through. */ | |
5507 | case M_JAL_2: | |
3e722fb5 | 5508 | if (mips_pic == NO_PIC) |
67c0d1eb | 5509 | macro_build (NULL, "jalr", "d,s", dreg, sreg); |
252b5132 RH |
5510 | else if (mips_pic == SVR4_PIC) |
5511 | { | |
5512 | if (sreg != PIC_CALL_REG) | |
5513 | as_warn (_("MIPS PIC call to register other than $25")); | |
bdaaa2e1 | 5514 | |
67c0d1eb | 5515 | macro_build (NULL, "jalr", "d,s", dreg, sreg); |
6478892d | 5516 | if (! HAVE_NEWABI) |
252b5132 | 5517 | { |
6478892d TS |
5518 | if (mips_cprestore_offset < 0) |
5519 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
5520 | else | |
5521 | { | |
7a621144 DJ |
5522 | if (! mips_frame_reg_valid) |
5523 | { | |
5524 | as_warn (_("No .frame pseudo-op used in PIC code")); | |
5525 | /* Quiet this warning. */ | |
5526 | mips_frame_reg_valid = 1; | |
5527 | } | |
5528 | if (! mips_cprestore_valid) | |
5529 | { | |
5530 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
5531 | /* Quiet this warning. */ | |
5532 | mips_cprestore_valid = 1; | |
5533 | } | |
6478892d | 5534 | expr1.X_add_number = mips_cprestore_offset; |
67c0d1eb | 5535 | macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN, |
f899b4b8 | 5536 | mips_gp_register, |
256ab948 TS |
5537 | mips_frame_reg, |
5538 | HAVE_64BIT_ADDRESSES); | |
6478892d | 5539 | } |
252b5132 RH |
5540 | } |
5541 | } | |
5542 | else | |
5543 | abort (); | |
5544 | ||
5545 | return; | |
5546 | ||
5547 | case M_JAL_A: | |
5548 | if (mips_pic == NO_PIC) | |
67c0d1eb | 5549 | macro_build (&offset_expr, "jal", "a"); |
252b5132 RH |
5550 | else if (mips_pic == SVR4_PIC) |
5551 | { | |
5552 | /* If this is a reference to an external symbol, and we are | |
5553 | using a small GOT, we want | |
5554 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16) | |
5555 | nop | |
f9419b05 | 5556 | jalr $ra,$25 |
252b5132 RH |
5557 | nop |
5558 | lw $gp,cprestore($sp) | |
5559 | The cprestore value is set using the .cprestore | |
5560 | pseudo-op. If we are using a big GOT, we want | |
5561 | lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16) | |
5562 | addu $25,$25,$gp | |
5563 | lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16) | |
5564 | nop | |
f9419b05 | 5565 | jalr $ra,$25 |
252b5132 RH |
5566 | nop |
5567 | lw $gp,cprestore($sp) | |
5568 | If the symbol is not external, we want | |
5569 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5570 | nop | |
5571 | addiu $25,$25,<sym> (BFD_RELOC_LO16) | |
f9419b05 | 5572 | jalr $ra,$25 |
252b5132 | 5573 | nop |
438c16b8 | 5574 | lw $gp,cprestore($sp) |
f5040a92 AO |
5575 | |
5576 | For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16 | |
5577 | sequences above, minus nops, unless the symbol is local, | |
5578 | which enables us to use GOT_PAGE/GOT_OFST (big got) or | |
5579 | GOT_DISP. */ | |
438c16b8 | 5580 | if (HAVE_NEWABI) |
252b5132 | 5581 | { |
f5040a92 AO |
5582 | if (! mips_big_got) |
5583 | { | |
4d7206a2 | 5584 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
5585 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5586 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL16, | |
f5040a92 | 5587 | mips_gp_register); |
4d7206a2 | 5588 | relax_switch (); |
67c0d1eb RS |
5589 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5590 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT_DISP, | |
4d7206a2 RS |
5591 | mips_gp_register); |
5592 | relax_end (); | |
f5040a92 AO |
5593 | } |
5594 | else | |
5595 | { | |
4d7206a2 | 5596 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
5597 | macro_build (&offset_expr, "lui", "t,u", PIC_CALL_REG, |
5598 | BFD_RELOC_MIPS_CALL_HI16); | |
5599 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG, | |
5600 | PIC_CALL_REG, mips_gp_register); | |
5601 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", | |
5602 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16, | |
5603 | PIC_CALL_REG); | |
4d7206a2 | 5604 | relax_switch (); |
67c0d1eb RS |
5605 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5606 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT_PAGE, | |
5607 | mips_gp_register); | |
5608 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
5609 | PIC_CALL_REG, PIC_CALL_REG, | |
17a2f251 | 5610 | BFD_RELOC_MIPS_GOT_OFST); |
4d7206a2 | 5611 | relax_end (); |
f5040a92 | 5612 | } |
684022ea | 5613 | |
67c0d1eb | 5614 | macro_build_jalr (&offset_expr); |
252b5132 RH |
5615 | } |
5616 | else | |
5617 | { | |
4d7206a2 | 5618 | relax_start (offset_expr.X_add_symbol); |
438c16b8 TS |
5619 | if (! mips_big_got) |
5620 | { | |
67c0d1eb RS |
5621 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5622 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL16, | |
17a2f251 | 5623 | mips_gp_register); |
269137b2 | 5624 | load_delay_nop (); |
4d7206a2 | 5625 | relax_switch (); |
438c16b8 | 5626 | } |
252b5132 | 5627 | else |
252b5132 | 5628 | { |
67c0d1eb RS |
5629 | int gpdelay; |
5630 | ||
5631 | gpdelay = reg_needs_delay (mips_gp_register); | |
5632 | macro_build (&offset_expr, "lui", "t,u", PIC_CALL_REG, | |
5633 | BFD_RELOC_MIPS_CALL_HI16); | |
5634 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG, | |
5635 | PIC_CALL_REG, mips_gp_register); | |
5636 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", | |
5637 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16, | |
5638 | PIC_CALL_REG); | |
269137b2 | 5639 | load_delay_nop (); |
4d7206a2 | 5640 | relax_switch (); |
67c0d1eb RS |
5641 | if (gpdelay) |
5642 | macro_build (NULL, "nop", ""); | |
252b5132 | 5643 | } |
67c0d1eb RS |
5644 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5645 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT16, | |
4d7206a2 | 5646 | mips_gp_register); |
269137b2 | 5647 | load_delay_nop (); |
67c0d1eb RS |
5648 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
5649 | PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16); | |
4d7206a2 | 5650 | relax_end (); |
67c0d1eb | 5651 | macro_build_jalr (&offset_expr); |
438c16b8 | 5652 | |
6478892d TS |
5653 | if (mips_cprestore_offset < 0) |
5654 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
5655 | else | |
5656 | { | |
7a621144 DJ |
5657 | if (! mips_frame_reg_valid) |
5658 | { | |
5659 | as_warn (_("No .frame pseudo-op used in PIC code")); | |
5660 | /* Quiet this warning. */ | |
5661 | mips_frame_reg_valid = 1; | |
5662 | } | |
5663 | if (! mips_cprestore_valid) | |
5664 | { | |
5665 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
5666 | /* Quiet this warning. */ | |
5667 | mips_cprestore_valid = 1; | |
5668 | } | |
6478892d | 5669 | if (mips_opts.noreorder) |
67c0d1eb | 5670 | macro_build (NULL, "nop", ""); |
6478892d | 5671 | expr1.X_add_number = mips_cprestore_offset; |
67c0d1eb | 5672 | macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN, |
f899b4b8 | 5673 | mips_gp_register, |
256ab948 TS |
5674 | mips_frame_reg, |
5675 | HAVE_64BIT_ADDRESSES); | |
6478892d | 5676 | } |
252b5132 RH |
5677 | } |
5678 | } | |
252b5132 RH |
5679 | else |
5680 | abort (); | |
5681 | ||
5682 | return; | |
5683 | ||
5684 | case M_LB_AB: | |
5685 | s = "lb"; | |
5686 | goto ld; | |
5687 | case M_LBU_AB: | |
5688 | s = "lbu"; | |
5689 | goto ld; | |
5690 | case M_LH_AB: | |
5691 | s = "lh"; | |
5692 | goto ld; | |
5693 | case M_LHU_AB: | |
5694 | s = "lhu"; | |
5695 | goto ld; | |
5696 | case M_LW_AB: | |
5697 | s = "lw"; | |
5698 | goto ld; | |
5699 | case M_LWC0_AB: | |
5700 | s = "lwc0"; | |
bdaaa2e1 | 5701 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5702 | coproc = 1; |
5703 | goto ld; | |
5704 | case M_LWC1_AB: | |
5705 | s = "lwc1"; | |
bdaaa2e1 | 5706 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5707 | coproc = 1; |
5708 | goto ld; | |
5709 | case M_LWC2_AB: | |
5710 | s = "lwc2"; | |
bdaaa2e1 | 5711 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5712 | coproc = 1; |
5713 | goto ld; | |
5714 | case M_LWC3_AB: | |
5715 | s = "lwc3"; | |
bdaaa2e1 | 5716 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5717 | coproc = 1; |
5718 | goto ld; | |
5719 | case M_LWL_AB: | |
5720 | s = "lwl"; | |
5721 | lr = 1; | |
5722 | goto ld; | |
5723 | case M_LWR_AB: | |
5724 | s = "lwr"; | |
5725 | lr = 1; | |
5726 | goto ld; | |
5727 | case M_LDC1_AB: | |
fef14a42 | 5728 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
5729 | { |
5730 | as_bad (_("opcode not supported on this processor")); | |
5731 | return; | |
5732 | } | |
5733 | s = "ldc1"; | |
bdaaa2e1 | 5734 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5735 | coproc = 1; |
5736 | goto ld; | |
5737 | case M_LDC2_AB: | |
5738 | s = "ldc2"; | |
bdaaa2e1 | 5739 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5740 | coproc = 1; |
5741 | goto ld; | |
5742 | case M_LDC3_AB: | |
5743 | s = "ldc3"; | |
bdaaa2e1 | 5744 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5745 | coproc = 1; |
5746 | goto ld; | |
5747 | case M_LDL_AB: | |
5748 | s = "ldl"; | |
5749 | lr = 1; | |
5750 | goto ld; | |
5751 | case M_LDR_AB: | |
5752 | s = "ldr"; | |
5753 | lr = 1; | |
5754 | goto ld; | |
5755 | case M_LL_AB: | |
5756 | s = "ll"; | |
5757 | goto ld; | |
5758 | case M_LLD_AB: | |
5759 | s = "lld"; | |
5760 | goto ld; | |
5761 | case M_LWU_AB: | |
5762 | s = "lwu"; | |
5763 | ld: | |
b8285c27 TS |
5764 | /* XXX Why don't we try to use AT for all expansions? */ |
5765 | if (!mips_opts.noat && (breg == treg || coproc || lr)) | |
252b5132 RH |
5766 | { |
5767 | tempreg = AT; | |
5768 | used_at = 1; | |
5769 | } | |
b8285c27 TS |
5770 | else if (breg == treg |
5771 | && (offset_expr.X_op != O_constant | |
5772 | || (offset_expr.X_add_number > 0x7fff | |
5773 | || offset_expr.X_add_number < -0x8000))) | |
5774 | { | |
5775 | as_bad(_("load expansion needs $at register")); | |
5776 | } | |
252b5132 RH |
5777 | else |
5778 | { | |
5779 | tempreg = treg; | |
5780 | used_at = 0; | |
5781 | } | |
5782 | goto ld_st; | |
5783 | case M_SB_AB: | |
5784 | s = "sb"; | |
5785 | goto st; | |
5786 | case M_SH_AB: | |
5787 | s = "sh"; | |
5788 | goto st; | |
5789 | case M_SW_AB: | |
5790 | s = "sw"; | |
5791 | goto st; | |
5792 | case M_SWC0_AB: | |
5793 | s = "swc0"; | |
bdaaa2e1 | 5794 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5795 | coproc = 1; |
5796 | goto st; | |
5797 | case M_SWC1_AB: | |
5798 | s = "swc1"; | |
bdaaa2e1 | 5799 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5800 | coproc = 1; |
5801 | goto st; | |
5802 | case M_SWC2_AB: | |
5803 | s = "swc2"; | |
bdaaa2e1 | 5804 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5805 | coproc = 1; |
5806 | goto st; | |
5807 | case M_SWC3_AB: | |
5808 | s = "swc3"; | |
bdaaa2e1 | 5809 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5810 | coproc = 1; |
5811 | goto st; | |
5812 | case M_SWL_AB: | |
5813 | s = "swl"; | |
5814 | goto st; | |
5815 | case M_SWR_AB: | |
5816 | s = "swr"; | |
5817 | goto st; | |
5818 | case M_SC_AB: | |
5819 | s = "sc"; | |
5820 | goto st; | |
5821 | case M_SCD_AB: | |
5822 | s = "scd"; | |
5823 | goto st; | |
5824 | case M_SDC1_AB: | |
fef14a42 | 5825 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
5826 | { |
5827 | as_bad (_("opcode not supported on this processor")); | |
5828 | return; | |
5829 | } | |
5830 | s = "sdc1"; | |
5831 | coproc = 1; | |
bdaaa2e1 | 5832 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5833 | goto st; |
5834 | case M_SDC2_AB: | |
5835 | s = "sdc2"; | |
bdaaa2e1 | 5836 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5837 | coproc = 1; |
5838 | goto st; | |
5839 | case M_SDC3_AB: | |
5840 | s = "sdc3"; | |
bdaaa2e1 | 5841 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5842 | coproc = 1; |
5843 | goto st; | |
5844 | case M_SDL_AB: | |
5845 | s = "sdl"; | |
5846 | goto st; | |
5847 | case M_SDR_AB: | |
5848 | s = "sdr"; | |
5849 | st: | |
b8285c27 TS |
5850 | if (!mips_opts.noat) |
5851 | { | |
5852 | tempreg = AT; | |
5853 | used_at = 1; | |
5854 | } | |
5855 | else if (breg == treg | |
5856 | && (offset_expr.X_op != O_constant | |
5857 | || (offset_expr.X_add_number > 0x7fff | |
5858 | || offset_expr.X_add_number < -0x8000))) | |
5859 | { | |
5860 | as_bad(_("store expansion needs $at register")); | |
5861 | } | |
5862 | else | |
5863 | { | |
5864 | tempreg = treg; | |
5865 | used_at = 0; | |
5866 | } | |
252b5132 | 5867 | ld_st: |
bdaaa2e1 | 5868 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5869 | if (mask == M_LWC1_AB |
5870 | || mask == M_SWC1_AB | |
5871 | || mask == M_LDC1_AB | |
5872 | || mask == M_SDC1_AB | |
5873 | || mask == M_L_DAB | |
5874 | || mask == M_S_DAB) | |
5875 | fmt = "T,o(b)"; | |
5876 | else if (coproc) | |
5877 | fmt = "E,o(b)"; | |
5878 | else | |
5879 | fmt = "t,o(b)"; | |
5880 | ||
256ab948 TS |
5881 | /* Sign-extending 32-bit constants makes their handling easier. |
5882 | The HAVE_64BIT_GPRS... part is due to the linux kernel hack | |
5883 | described below. */ | |
5884 | if ((! HAVE_64BIT_ADDRESSES | |
5885 | && (! HAVE_64BIT_GPRS && offset_expr.X_op == O_constant)) | |
d17e7bce TS |
5886 | && (offset_expr.X_op == O_constant) |
5887 | && ! ((offset_expr.X_add_number & ~((bfd_vma) 0x7fffffff)) | |
5888 | == ~((bfd_vma) 0x7fffffff))) | |
ae826530 | 5889 | { |
d17e7bce | 5890 | if (offset_expr.X_add_number & ~((bfd_vma) 0xffffffff)) |
1b8e29e5 | 5891 | as_bad (_("constant too large")); |
ae826530 | 5892 | |
1b8e29e5 TS |
5893 | offset_expr.X_add_number = (((offset_expr.X_add_number & 0xffffffff) |
5894 | ^ 0x80000000) - 0x80000000); | |
ae826530 | 5895 | } |
256ab948 | 5896 | |
252b5132 RH |
5897 | if (offset_expr.X_op != O_constant |
5898 | && offset_expr.X_op != O_symbol) | |
5899 | { | |
5900 | as_bad (_("expression too complex")); | |
5901 | offset_expr.X_op = O_constant; | |
5902 | } | |
5903 | ||
5904 | /* A constant expression in PIC code can be handled just as it | |
5905 | is in non PIC code. */ | |
5906 | if (mips_pic == NO_PIC | |
5907 | || offset_expr.X_op == O_constant) | |
5908 | { | |
5909 | /* If this is a reference to a GP relative symbol, and there | |
5910 | is no base register, we want | |
cdf6fd85 | 5911 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
252b5132 RH |
5912 | Otherwise, if there is no base register, we want |
5913 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
5914 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
5915 | If we have a constant, we need two instructions anyhow, | |
5916 | so we always use the latter form. | |
5917 | ||
5918 | If we have a base register, and this is a reference to a | |
5919 | GP relative symbol, we want | |
5920 | addu $tempreg,$breg,$gp | |
cdf6fd85 | 5921 | <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16) |
252b5132 RH |
5922 | Otherwise we want |
5923 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
5924 | addu $tempreg,$tempreg,$breg | |
5925 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
d6bc6245 | 5926 | With a constant we always use the latter case. |
76b3015f | 5927 | |
d6bc6245 TS |
5928 | With 64bit address space and no base register and $at usable, |
5929 | we want | |
5930 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5931 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
5932 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5933 | dsll32 $tempreg,0 | |
5934 | daddu $tempreg,$at | |
5935 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
5936 | If we have a base register, we want | |
5937 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5938 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
5939 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5940 | daddu $at,$breg | |
5941 | dsll32 $tempreg,0 | |
5942 | daddu $tempreg,$at | |
5943 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
5944 | ||
5945 | Without $at we can't generate the optimal path for superscalar | |
5946 | processors here since this would require two temporary registers. | |
5947 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5948 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5949 | dsll $tempreg,16 | |
5950 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
5951 | dsll $tempreg,16 | |
5952 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
5953 | If we have a base register, we want | |
5954 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5955 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5956 | dsll $tempreg,16 | |
5957 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
5958 | dsll $tempreg,16 | |
5959 | daddu $tempreg,$tempreg,$breg | |
5960 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
6373ee54 CD |
5961 | |
5962 | If we have 64-bit addresses, as an optimization, for | |
5963 | addresses which are 32-bit constants (e.g. kseg0/kseg1 | |
5964 | addresses) we fall back to the 32-bit address generation | |
78d32a17 MR |
5965 | mechanism since it is more efficient. Note that due to |
5966 | the signed offset used by memory operations, the 32-bit | |
5967 | range is shifted down by 32768 here. This code should | |
6373ee54 CD |
5968 | probably attempt to generate 64-bit constants more |
5969 | efficiently in general. | |
9214dd3b AO |
5970 | |
5971 | As an extension for architectures with 64-bit registers, | |
5972 | we don't truncate 64-bit addresses given as literal | |
5973 | constants down to 32 bits, to support existing practice | |
5974 | in the mips64 Linux (the kernel), that compiles source | |
5975 | files with -mabi=64, assembling them as o32 or n32 (with | |
5976 | -Wa,-32 or -Wa,-n32). This is not beautiful, but since | |
5977 | the whole kernel is loaded into a memory region that is | |
67c1ffbe | 5978 | addressable with sign-extended 32-bit addresses, it is |
9214dd3b AO |
5979 | wasteful to compute the upper 32 bits of every |
5980 | non-literal address, that takes more space and time. | |
5981 | Some day this should probably be implemented as an | |
5982 | assembler option, such that the kernel doesn't have to | |
5983 | use such ugly hacks, even though it will still have to | |
5984 | end up converting the binary to ELF32 for a number of | |
5985 | platforms whose boot loaders don't support ELF64 | |
5986 | binaries. */ | |
256ab948 TS |
5987 | if ((HAVE_64BIT_ADDRESSES |
5988 | && ! (offset_expr.X_op == O_constant | |
5989 | && IS_SEXT_32BIT_NUM (offset_expr.X_add_number + 0x8000))) | |
5990 | || (HAVE_64BIT_GPRS | |
5991 | && offset_expr.X_op == O_constant | |
5992 | && ! IS_SEXT_32BIT_NUM (offset_expr.X_add_number + 0x8000))) | |
d6bc6245 | 5993 | { |
e864ceca RS |
5994 | /* ??? We don't provide a GP-relative alternative for |
5995 | these macros. It used not to be possible with the | |
5996 | original relaxation code, but it could be done now. */ | |
d6bc6245 | 5997 | |
b8285c27 | 5998 | if (used_at == 0 && !mips_opts.noat) |
d6bc6245 | 5999 | { |
67c0d1eb RS |
6000 | macro_build (&offset_expr, "lui", "t,u", tempreg, |
6001 | BFD_RELOC_MIPS_HIGHEST); | |
6002 | macro_build (&offset_expr, "lui", "t,u", AT, | |
6003 | BFD_RELOC_HI16_S); | |
6004 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
6005 | tempreg, BFD_RELOC_MIPS_HIGHER); | |
d6bc6245 | 6006 | if (breg != 0) |
67c0d1eb RS |
6007 | macro_build (NULL, "daddu", "d,v,t", AT, AT, breg); |
6008 | macro_build (NULL, "dsll32", "d,w,<", tempreg, tempreg, 0); | |
6009 | macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT); | |
6010 | macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, | |
6011 | tempreg); | |
d6bc6245 TS |
6012 | used_at = 1; |
6013 | } | |
6014 | else | |
6015 | { | |
67c0d1eb RS |
6016 | macro_build (&offset_expr, "lui", "t,u", tempreg, |
6017 | BFD_RELOC_MIPS_HIGHEST); | |
6018 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
6019 | tempreg, BFD_RELOC_MIPS_HIGHER); | |
6020 | macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16); | |
6021 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
6022 | tempreg, BFD_RELOC_HI16_S); | |
6023 | macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16); | |
d6bc6245 | 6024 | if (breg != 0) |
67c0d1eb | 6025 | macro_build (NULL, "daddu", "d,v,t", |
17a2f251 | 6026 | tempreg, tempreg, breg); |
67c0d1eb | 6027 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 6028 | BFD_RELOC_LO16, tempreg); |
d6bc6245 TS |
6029 | } |
6030 | ||
b8285c27 TS |
6031 | if (used_at) |
6032 | break; | |
6033 | ||
d6bc6245 TS |
6034 | return; |
6035 | } | |
256ab948 TS |
6036 | |
6037 | if (offset_expr.X_op == O_constant | |
ecd13cd3 | 6038 | && ! IS_SEXT_32BIT_NUM (offset_expr.X_add_number + 0x8000)) |
5a7a0b7b | 6039 | as_bad (_("load/store address overflow (max 32 bits)")); |
76b3015f | 6040 | |
252b5132 RH |
6041 | if (breg == 0) |
6042 | { | |
67c0d1eb RS |
6043 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6044 | && ! nopic_need_relax (offset_expr.X_add_symbol, 1)) | |
252b5132 | 6045 | { |
4d7206a2 | 6046 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
6047 | macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_GPREL16, |
6048 | mips_gp_register); | |
4d7206a2 | 6049 | relax_switch (); |
252b5132 | 6050 | } |
67c0d1eb RS |
6051 | macro_build_lui (&offset_expr, tempreg); |
6052 | macro_build (&offset_expr, s, fmt, treg, | |
17a2f251 | 6053 | BFD_RELOC_LO16, tempreg); |
4d7206a2 RS |
6054 | if (mips_relax.sequence) |
6055 | relax_end (); | |
252b5132 RH |
6056 | } |
6057 | else | |
6058 | { | |
67c0d1eb RS |
6059 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6060 | && ! nopic_need_relax (offset_expr.X_add_symbol, 1)) | |
252b5132 | 6061 | { |
4d7206a2 | 6062 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 6063 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6064 | tempreg, breg, mips_gp_register); |
67c0d1eb | 6065 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 6066 | BFD_RELOC_GPREL16, tempreg); |
4d7206a2 | 6067 | relax_switch (); |
252b5132 | 6068 | } |
67c0d1eb RS |
6069 | macro_build_lui (&offset_expr, tempreg); |
6070 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 6071 | tempreg, tempreg, breg); |
67c0d1eb | 6072 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 6073 | BFD_RELOC_LO16, tempreg); |
4d7206a2 RS |
6074 | if (mips_relax.sequence) |
6075 | relax_end (); | |
252b5132 RH |
6076 | } |
6077 | } | |
6078 | else if (mips_pic == SVR4_PIC && ! mips_big_got) | |
6079 | { | |
ed6fb7bd | 6080 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
f9419b05 | 6081 | |
252b5132 RH |
6082 | /* If this is a reference to an external symbol, we want |
6083 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6084 | nop | |
6085 | <op> $treg,0($tempreg) | |
6086 | Otherwise we want | |
6087 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6088 | nop | |
6089 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
6090 | <op> $treg,0($tempreg) | |
f5040a92 AO |
6091 | |
6092 | For NewABI, we want | |
6093 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
6094 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) | |
6095 | ||
252b5132 RH |
6096 | If there is a base register, we add it to $tempreg before |
6097 | the <op>. If there is a constant, we stick it in the | |
6098 | <op> instruction. We don't handle constants larger than | |
6099 | 16 bits, because we have no way to load the upper 16 bits | |
6100 | (actually, we could handle them for the subset of cases | |
6101 | in which we are not using $at). */ | |
6102 | assert (offset_expr.X_op == O_symbol); | |
f5040a92 AO |
6103 | if (HAVE_NEWABI) |
6104 | { | |
67c0d1eb RS |
6105 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
6106 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
f5040a92 | 6107 | if (breg != 0) |
67c0d1eb | 6108 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6109 | tempreg, tempreg, breg); |
67c0d1eb | 6110 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 6111 | BFD_RELOC_MIPS_GOT_OFST, tempreg); |
f5040a92 | 6112 | |
b8285c27 | 6113 | if (!used_at) |
f5040a92 AO |
6114 | return; |
6115 | ||
6116 | break; | |
6117 | } | |
252b5132 RH |
6118 | expr1.X_add_number = offset_expr.X_add_number; |
6119 | offset_expr.X_add_number = 0; | |
6120 | if (expr1.X_add_number < -0x8000 | |
6121 | || expr1.X_add_number >= 0x8000) | |
6122 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb RS |
6123 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
6124 | lw_reloc_type, mips_gp_register); | |
269137b2 | 6125 | load_delay_nop (); |
4d7206a2 RS |
6126 | relax_start (offset_expr.X_add_symbol); |
6127 | relax_switch (); | |
67c0d1eb RS |
6128 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, |
6129 | tempreg, BFD_RELOC_LO16); | |
4d7206a2 | 6130 | relax_end (); |
252b5132 | 6131 | if (breg != 0) |
67c0d1eb | 6132 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6133 | tempreg, tempreg, breg); |
67c0d1eb | 6134 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
252b5132 | 6135 | } |
f5040a92 | 6136 | else if (mips_pic == SVR4_PIC && ! HAVE_NEWABI) |
252b5132 | 6137 | { |
67c0d1eb | 6138 | int gpdelay; |
252b5132 RH |
6139 | |
6140 | /* If this is a reference to an external symbol, we want | |
6141 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
6142 | addu $tempreg,$tempreg,$gp | |
6143 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
6144 | <op> $treg,0($tempreg) | |
6145 | Otherwise we want | |
6146 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6147 | nop | |
6148 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
6149 | <op> $treg,0($tempreg) | |
6150 | If there is a base register, we add it to $tempreg before | |
6151 | the <op>. If there is a constant, we stick it in the | |
6152 | <op> instruction. We don't handle constants larger than | |
6153 | 16 bits, because we have no way to load the upper 16 bits | |
6154 | (actually, we could handle them for the subset of cases | |
f5040a92 | 6155 | in which we are not using $at). */ |
252b5132 RH |
6156 | assert (offset_expr.X_op == O_symbol); |
6157 | expr1.X_add_number = offset_expr.X_add_number; | |
6158 | offset_expr.X_add_number = 0; | |
6159 | if (expr1.X_add_number < -0x8000 | |
6160 | || expr1.X_add_number >= 0x8000) | |
6161 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 6162 | gpdelay = reg_needs_delay (mips_gp_register); |
4d7206a2 | 6163 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 6164 | macro_build (&offset_expr, "lui", "t,u", tempreg, |
17a2f251 | 6165 | BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
6166 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, |
6167 | mips_gp_register); | |
6168 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
6169 | BFD_RELOC_MIPS_GOT_LO16, tempreg); | |
4d7206a2 | 6170 | relax_switch (); |
67c0d1eb RS |
6171 | if (gpdelay) |
6172 | macro_build (NULL, "nop", ""); | |
6173 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
6174 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 6175 | load_delay_nop (); |
67c0d1eb RS |
6176 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, |
6177 | tempreg, BFD_RELOC_LO16); | |
4d7206a2 RS |
6178 | relax_end (); |
6179 | ||
252b5132 | 6180 | if (breg != 0) |
67c0d1eb | 6181 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6182 | tempreg, tempreg, breg); |
67c0d1eb | 6183 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
252b5132 | 6184 | } |
f5040a92 AO |
6185 | else if (mips_pic == SVR4_PIC && HAVE_NEWABI) |
6186 | { | |
f5040a92 AO |
6187 | /* If this is a reference to an external symbol, we want |
6188 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
6189 | add $tempreg,$tempreg,$gp | |
6190 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
6191 | <op> $treg,<ofst>($tempreg) | |
6192 | Otherwise, for local symbols, we want: | |
6193 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
6194 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */ | |
6195 | assert (offset_expr.X_op == O_symbol); | |
4d7206a2 | 6196 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
6197 | offset_expr.X_add_number = 0; |
6198 | if (expr1.X_add_number < -0x8000 | |
6199 | || expr1.X_add_number >= 0x8000) | |
6200 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4d7206a2 | 6201 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 6202 | macro_build (&offset_expr, "lui", "t,u", tempreg, |
17a2f251 | 6203 | BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
6204 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, |
6205 | mips_gp_register); | |
6206 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
6207 | BFD_RELOC_MIPS_GOT_LO16, tempreg); | |
f5040a92 | 6208 | if (breg != 0) |
67c0d1eb | 6209 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6210 | tempreg, tempreg, breg); |
67c0d1eb | 6211 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
684022ea | 6212 | |
4d7206a2 | 6213 | relax_switch (); |
f5040a92 | 6214 | offset_expr.X_add_number = expr1.X_add_number; |
67c0d1eb RS |
6215 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
6216 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
f5040a92 | 6217 | if (breg != 0) |
67c0d1eb | 6218 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6219 | tempreg, tempreg, breg); |
67c0d1eb | 6220 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 6221 | BFD_RELOC_MIPS_GOT_OFST, tempreg); |
4d7206a2 | 6222 | relax_end (); |
f5040a92 | 6223 | } |
252b5132 RH |
6224 | else |
6225 | abort (); | |
6226 | ||
b8285c27 | 6227 | if (!used_at) |
252b5132 RH |
6228 | return; |
6229 | ||
6230 | break; | |
6231 | ||
6232 | case M_LI: | |
6233 | case M_LI_S: | |
67c0d1eb | 6234 | load_register (treg, &imm_expr, 0); |
252b5132 RH |
6235 | return; |
6236 | ||
6237 | case M_DLI: | |
67c0d1eb | 6238 | load_register (treg, &imm_expr, 1); |
252b5132 RH |
6239 | return; |
6240 | ||
6241 | case M_LI_SS: | |
6242 | if (imm_expr.X_op == O_constant) | |
6243 | { | |
67c0d1eb RS |
6244 | load_register (AT, &imm_expr, 0); |
6245 | macro_build (NULL, "mtc1", "t,G", AT, treg); | |
252b5132 RH |
6246 | break; |
6247 | } | |
6248 | else | |
6249 | { | |
6250 | assert (offset_expr.X_op == O_symbol | |
6251 | && strcmp (segment_name (S_GET_SEGMENT | |
6252 | (offset_expr.X_add_symbol)), | |
6253 | ".lit4") == 0 | |
6254 | && offset_expr.X_add_number == 0); | |
67c0d1eb | 6255 | macro_build (&offset_expr, "lwc1", "T,o(b)", treg, |
17a2f251 | 6256 | BFD_RELOC_MIPS_LITERAL, mips_gp_register); |
252b5132 RH |
6257 | return; |
6258 | } | |
6259 | ||
6260 | case M_LI_D: | |
ca4e0257 RS |
6261 | /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits |
6262 | wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high | |
6263 | order 32 bits of the value and the low order 32 bits are either | |
6264 | zero or in OFFSET_EXPR. */ | |
252b5132 RH |
6265 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) |
6266 | { | |
ca4e0257 | 6267 | if (HAVE_64BIT_GPRS) |
67c0d1eb | 6268 | load_register (treg, &imm_expr, 1); |
252b5132 RH |
6269 | else |
6270 | { | |
6271 | int hreg, lreg; | |
6272 | ||
6273 | if (target_big_endian) | |
6274 | { | |
6275 | hreg = treg; | |
6276 | lreg = treg + 1; | |
6277 | } | |
6278 | else | |
6279 | { | |
6280 | hreg = treg + 1; | |
6281 | lreg = treg; | |
6282 | } | |
6283 | ||
6284 | if (hreg <= 31) | |
67c0d1eb | 6285 | load_register (hreg, &imm_expr, 0); |
252b5132 RH |
6286 | if (lreg <= 31) |
6287 | { | |
6288 | if (offset_expr.X_op == O_absent) | |
67c0d1eb | 6289 | move_register (lreg, 0); |
252b5132 RH |
6290 | else |
6291 | { | |
6292 | assert (offset_expr.X_op == O_constant); | |
67c0d1eb | 6293 | load_register (lreg, &offset_expr, 0); |
252b5132 RH |
6294 | } |
6295 | } | |
6296 | } | |
6297 | return; | |
6298 | } | |
6299 | ||
6300 | /* We know that sym is in the .rdata section. First we get the | |
6301 | upper 16 bits of the address. */ | |
6302 | if (mips_pic == NO_PIC) | |
6303 | { | |
67c0d1eb | 6304 | macro_build_lui (&offset_expr, AT); |
252b5132 RH |
6305 | } |
6306 | else if (mips_pic == SVR4_PIC) | |
6307 | { | |
67c0d1eb RS |
6308 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, |
6309 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
252b5132 | 6310 | } |
252b5132 RH |
6311 | else |
6312 | abort (); | |
bdaaa2e1 | 6313 | |
252b5132 | 6314 | /* Now we load the register(s). */ |
ca4e0257 | 6315 | if (HAVE_64BIT_GPRS) |
67c0d1eb | 6316 | macro_build (&offset_expr, "ld", "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
6317 | else |
6318 | { | |
67c0d1eb | 6319 | macro_build (&offset_expr, "lw", "t,o(b)", treg, BFD_RELOC_LO16, AT); |
f9419b05 | 6320 | if (treg != RA) |
252b5132 RH |
6321 | { |
6322 | /* FIXME: How in the world do we deal with the possible | |
6323 | overflow here? */ | |
6324 | offset_expr.X_add_number += 4; | |
67c0d1eb | 6325 | macro_build (&offset_expr, "lw", "t,o(b)", |
17a2f251 | 6326 | treg + 1, BFD_RELOC_LO16, AT); |
252b5132 RH |
6327 | } |
6328 | } | |
252b5132 RH |
6329 | break; |
6330 | ||
6331 | case M_LI_DD: | |
ca4e0257 RS |
6332 | /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits |
6333 | wide, IMM_EXPR is the entire value and the GPRs are known to be 64 | |
6334 | bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of | |
6335 | the value and the low order 32 bits are either zero or in | |
6336 | OFFSET_EXPR. */ | |
252b5132 RH |
6337 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) |
6338 | { | |
67c0d1eb | 6339 | load_register (AT, &imm_expr, HAVE_64BIT_FPRS); |
ca4e0257 RS |
6340 | if (HAVE_64BIT_FPRS) |
6341 | { | |
6342 | assert (HAVE_64BIT_GPRS); | |
67c0d1eb | 6343 | macro_build (NULL, "dmtc1", "t,S", AT, treg); |
ca4e0257 | 6344 | } |
252b5132 RH |
6345 | else |
6346 | { | |
67c0d1eb | 6347 | macro_build (NULL, "mtc1", "t,G", AT, treg + 1); |
252b5132 | 6348 | if (offset_expr.X_op == O_absent) |
67c0d1eb | 6349 | macro_build (NULL, "mtc1", "t,G", 0, treg); |
252b5132 RH |
6350 | else |
6351 | { | |
6352 | assert (offset_expr.X_op == O_constant); | |
67c0d1eb RS |
6353 | load_register (AT, &offset_expr, 0); |
6354 | macro_build (NULL, "mtc1", "t,G", AT, treg); | |
252b5132 RH |
6355 | } |
6356 | } | |
6357 | break; | |
6358 | } | |
6359 | ||
6360 | assert (offset_expr.X_op == O_symbol | |
6361 | && offset_expr.X_add_number == 0); | |
6362 | s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol)); | |
6363 | if (strcmp (s, ".lit8") == 0) | |
6364 | { | |
e7af610e | 6365 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 | 6366 | { |
67c0d1eb | 6367 | macro_build (&offset_expr, "ldc1", "T,o(b)", treg, |
17a2f251 | 6368 | BFD_RELOC_MIPS_LITERAL, mips_gp_register); |
252b5132 RH |
6369 | return; |
6370 | } | |
c9914766 | 6371 | breg = mips_gp_register; |
252b5132 RH |
6372 | r = BFD_RELOC_MIPS_LITERAL; |
6373 | goto dob; | |
6374 | } | |
6375 | else | |
6376 | { | |
6377 | assert (strcmp (s, RDATA_SECTION_NAME) == 0); | |
6378 | if (mips_pic == SVR4_PIC) | |
67c0d1eb RS |
6379 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, |
6380 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
252b5132 RH |
6381 | else |
6382 | { | |
6383 | /* FIXME: This won't work for a 64 bit address. */ | |
67c0d1eb | 6384 | macro_build_lui (&offset_expr, AT); |
252b5132 | 6385 | } |
bdaaa2e1 | 6386 | |
e7af610e | 6387 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 | 6388 | { |
67c0d1eb RS |
6389 | macro_build (&offset_expr, "ldc1", "T,o(b)", |
6390 | treg, BFD_RELOC_LO16, AT); | |
252b5132 RH |
6391 | break; |
6392 | } | |
6393 | breg = AT; | |
6394 | r = BFD_RELOC_LO16; | |
6395 | goto dob; | |
6396 | } | |
6397 | ||
6398 | case M_L_DOB: | |
fef14a42 | 6399 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
6400 | { |
6401 | as_bad (_("opcode not supported on this processor")); | |
6402 | return; | |
6403 | } | |
6404 | /* Even on a big endian machine $fn comes before $fn+1. We have | |
6405 | to adjust when loading from memory. */ | |
6406 | r = BFD_RELOC_LO16; | |
6407 | dob: | |
e7af610e | 6408 | assert (mips_opts.isa == ISA_MIPS1); |
67c0d1eb | 6409 | macro_build (&offset_expr, "lwc1", "T,o(b)", |
17a2f251 | 6410 | target_big_endian ? treg + 1 : treg, r, breg); |
252b5132 RH |
6411 | /* FIXME: A possible overflow which I don't know how to deal |
6412 | with. */ | |
6413 | offset_expr.X_add_number += 4; | |
67c0d1eb | 6414 | macro_build (&offset_expr, "lwc1", "T,o(b)", |
17a2f251 | 6415 | target_big_endian ? treg : treg + 1, r, breg); |
252b5132 | 6416 | |
252b5132 RH |
6417 | if (breg != AT) |
6418 | return; | |
6419 | break; | |
6420 | ||
6421 | case M_L_DAB: | |
6422 | /* | |
6423 | * The MIPS assembler seems to check for X_add_number not | |
6424 | * being double aligned and generating: | |
6425 | * lui at,%hi(foo+1) | |
6426 | * addu at,at,v1 | |
6427 | * addiu at,at,%lo(foo+1) | |
6428 | * lwc1 f2,0(at) | |
6429 | * lwc1 f3,4(at) | |
6430 | * But, the resulting address is the same after relocation so why | |
6431 | * generate the extra instruction? | |
6432 | */ | |
fef14a42 | 6433 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
6434 | { |
6435 | as_bad (_("opcode not supported on this processor")); | |
6436 | return; | |
6437 | } | |
bdaaa2e1 | 6438 | /* Itbl support may require additional care here. */ |
252b5132 | 6439 | coproc = 1; |
e7af610e | 6440 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 RH |
6441 | { |
6442 | s = "ldc1"; | |
6443 | goto ld; | |
6444 | } | |
6445 | ||
6446 | s = "lwc1"; | |
6447 | fmt = "T,o(b)"; | |
6448 | goto ldd_std; | |
6449 | ||
6450 | case M_S_DAB: | |
fef14a42 | 6451 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
6452 | { |
6453 | as_bad (_("opcode not supported on this processor")); | |
6454 | return; | |
6455 | } | |
6456 | ||
e7af610e | 6457 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 RH |
6458 | { |
6459 | s = "sdc1"; | |
6460 | goto st; | |
6461 | } | |
6462 | ||
6463 | s = "swc1"; | |
6464 | fmt = "T,o(b)"; | |
bdaaa2e1 | 6465 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6466 | coproc = 1; |
6467 | goto ldd_std; | |
6468 | ||
6469 | case M_LD_AB: | |
ca4e0257 | 6470 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
6471 | { |
6472 | s = "ld"; | |
6473 | goto ld; | |
6474 | } | |
6475 | ||
6476 | s = "lw"; | |
6477 | fmt = "t,o(b)"; | |
6478 | goto ldd_std; | |
6479 | ||
6480 | case M_SD_AB: | |
ca4e0257 | 6481 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
6482 | { |
6483 | s = "sd"; | |
6484 | goto st; | |
6485 | } | |
6486 | ||
6487 | s = "sw"; | |
6488 | fmt = "t,o(b)"; | |
6489 | ||
6490 | ldd_std: | |
6491 | if (offset_expr.X_op != O_symbol | |
6492 | && offset_expr.X_op != O_constant) | |
6493 | { | |
6494 | as_bad (_("expression too complex")); | |
6495 | offset_expr.X_op = O_constant; | |
6496 | } | |
6497 | ||
6498 | /* Even on a big endian machine $fn comes before $fn+1. We have | |
6499 | to adjust when loading from memory. We set coproc if we must | |
6500 | load $fn+1 first. */ | |
bdaaa2e1 | 6501 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6502 | if (! target_big_endian) |
6503 | coproc = 0; | |
6504 | ||
6505 | if (mips_pic == NO_PIC | |
6506 | || offset_expr.X_op == O_constant) | |
6507 | { | |
6508 | /* If this is a reference to a GP relative symbol, we want | |
cdf6fd85 TS |
6509 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
6510 | <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16) | |
252b5132 RH |
6511 | If we have a base register, we use this |
6512 | addu $at,$breg,$gp | |
cdf6fd85 TS |
6513 | <op> $treg,<sym>($at) (BFD_RELOC_GPREL16) |
6514 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16) | |
252b5132 RH |
6515 | If this is not a GP relative symbol, we want |
6516 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
6517 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
6518 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
6519 | If there is a base register, we add it to $at after the | |
6520 | lui instruction. If there is a constant, we always use | |
6521 | the last case. */ | |
e7d556df | 6522 | if ((valueT) offset_expr.X_add_number > MAX_GPREL_OFFSET |
252b5132 | 6523 | || nopic_need_relax (offset_expr.X_add_symbol, 1)) |
67c0d1eb | 6524 | used_at = 1; |
252b5132 RH |
6525 | else |
6526 | { | |
4d7206a2 | 6527 | relax_start (offset_expr.X_add_symbol); |
252b5132 RH |
6528 | if (breg == 0) |
6529 | { | |
c9914766 | 6530 | tempreg = mips_gp_register; |
252b5132 RH |
6531 | } |
6532 | else | |
6533 | { | |
67c0d1eb | 6534 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6535 | AT, breg, mips_gp_register); |
252b5132 | 6536 | tempreg = AT; |
252b5132 RH |
6537 | used_at = 1; |
6538 | } | |
6539 | ||
beae10d5 | 6540 | /* Itbl support may require additional care here. */ |
67c0d1eb | 6541 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 6542 | BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
6543 | offset_expr.X_add_number += 4; |
6544 | ||
6545 | /* Set mips_optimize to 2 to avoid inserting an | |
6546 | undesired nop. */ | |
6547 | hold_mips_optimize = mips_optimize; | |
6548 | mips_optimize = 2; | |
beae10d5 | 6549 | /* Itbl support may require additional care here. */ |
67c0d1eb | 6550 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 6551 | BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
6552 | mips_optimize = hold_mips_optimize; |
6553 | ||
4d7206a2 | 6554 | relax_switch (); |
252b5132 RH |
6555 | |
6556 | /* We just generated two relocs. When tc_gen_reloc | |
6557 | handles this case, it will skip the first reloc and | |
6558 | handle the second. The second reloc already has an | |
6559 | extra addend of 4, which we added above. We must | |
6560 | subtract it out, and then subtract another 4 to make | |
6561 | the first reloc come out right. The second reloc | |
6562 | will come out right because we are going to add 4 to | |
6563 | offset_expr when we build its instruction below. | |
6564 | ||
6565 | If we have a symbol, then we don't want to include | |
6566 | the offset, because it will wind up being included | |
6567 | when we generate the reloc. */ | |
6568 | ||
6569 | if (offset_expr.X_op == O_constant) | |
6570 | offset_expr.X_add_number -= 8; | |
6571 | else | |
6572 | { | |
6573 | offset_expr.X_add_number = -4; | |
6574 | offset_expr.X_op = O_constant; | |
6575 | } | |
6576 | } | |
67c0d1eb | 6577 | macro_build_lui (&offset_expr, AT); |
252b5132 | 6578 | if (breg != 0) |
67c0d1eb | 6579 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 6580 | /* Itbl support may require additional care here. */ |
67c0d1eb | 6581 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 6582 | BFD_RELOC_LO16, AT); |
252b5132 RH |
6583 | /* FIXME: How do we handle overflow here? */ |
6584 | offset_expr.X_add_number += 4; | |
beae10d5 | 6585 | /* Itbl support may require additional care here. */ |
67c0d1eb | 6586 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 6587 | BFD_RELOC_LO16, AT); |
4d7206a2 RS |
6588 | if (mips_relax.sequence) |
6589 | relax_end (); | |
bdaaa2e1 | 6590 | } |
252b5132 RH |
6591 | else if (mips_pic == SVR4_PIC && ! mips_big_got) |
6592 | { | |
252b5132 RH |
6593 | /* If this is a reference to an external symbol, we want |
6594 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6595 | nop | |
6596 | <op> $treg,0($at) | |
6597 | <op> $treg+1,4($at) | |
6598 | Otherwise we want | |
6599 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6600 | nop | |
6601 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
6602 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
6603 | If there is a base register we add it to $at before the | |
6604 | lwc1 instructions. If there is a constant we include it | |
6605 | in the lwc1 instructions. */ | |
6606 | used_at = 1; | |
6607 | expr1.X_add_number = offset_expr.X_add_number; | |
252b5132 RH |
6608 | if (expr1.X_add_number < -0x8000 |
6609 | || expr1.X_add_number >= 0x8000 - 4) | |
6610 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 6611 | load_got_offset (AT, &offset_expr); |
269137b2 | 6612 | load_delay_nop (); |
252b5132 | 6613 | if (breg != 0) |
67c0d1eb | 6614 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
252b5132 RH |
6615 | |
6616 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
6617 | nop. */ | |
6618 | hold_mips_optimize = mips_optimize; | |
6619 | mips_optimize = 2; | |
4d7206a2 | 6620 | |
beae10d5 | 6621 | /* Itbl support may require additional care here. */ |
4d7206a2 | 6622 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
6623 | macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg, |
6624 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 6625 | expr1.X_add_number += 4; |
67c0d1eb RS |
6626 | macro_build (&expr1, s, fmt, coproc ? treg : treg + 1, |
6627 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 6628 | relax_switch (); |
67c0d1eb RS |
6629 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
6630 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 6631 | offset_expr.X_add_number += 4; |
67c0d1eb RS |
6632 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
6633 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 6634 | relax_end (); |
252b5132 | 6635 | |
4d7206a2 | 6636 | mips_optimize = hold_mips_optimize; |
252b5132 RH |
6637 | } |
6638 | else if (mips_pic == SVR4_PIC) | |
6639 | { | |
67c0d1eb | 6640 | int gpdelay; |
252b5132 RH |
6641 | |
6642 | /* If this is a reference to an external symbol, we want | |
6643 | lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
6644 | addu $at,$at,$gp | |
6645 | lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16) | |
6646 | nop | |
6647 | <op> $treg,0($at) | |
6648 | <op> $treg+1,4($at) | |
6649 | Otherwise we want | |
6650 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6651 | nop | |
6652 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
6653 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
6654 | If there is a base register we add it to $at before the | |
6655 | lwc1 instructions. If there is a constant we include it | |
6656 | in the lwc1 instructions. */ | |
6657 | used_at = 1; | |
6658 | expr1.X_add_number = offset_expr.X_add_number; | |
6659 | offset_expr.X_add_number = 0; | |
6660 | if (expr1.X_add_number < -0x8000 | |
6661 | || expr1.X_add_number >= 0x8000 - 4) | |
6662 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 6663 | gpdelay = reg_needs_delay (mips_gp_register); |
4d7206a2 | 6664 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
6665 | macro_build (&offset_expr, "lui", "t,u", |
6666 | AT, BFD_RELOC_MIPS_GOT_HI16); | |
6667 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 6668 | AT, AT, mips_gp_register); |
67c0d1eb | 6669 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
17a2f251 | 6670 | AT, BFD_RELOC_MIPS_GOT_LO16, AT); |
269137b2 | 6671 | load_delay_nop (); |
252b5132 | 6672 | if (breg != 0) |
67c0d1eb | 6673 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 6674 | /* Itbl support may require additional care here. */ |
67c0d1eb | 6675 | macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 6676 | BFD_RELOC_LO16, AT); |
252b5132 RH |
6677 | expr1.X_add_number += 4; |
6678 | ||
6679 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
6680 | nop. */ | |
6681 | hold_mips_optimize = mips_optimize; | |
6682 | mips_optimize = 2; | |
beae10d5 | 6683 | /* Itbl support may require additional care here. */ |
67c0d1eb | 6684 | macro_build (&expr1, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 6685 | BFD_RELOC_LO16, AT); |
252b5132 RH |
6686 | mips_optimize = hold_mips_optimize; |
6687 | expr1.X_add_number -= 4; | |
6688 | ||
4d7206a2 RS |
6689 | relax_switch (); |
6690 | offset_expr.X_add_number = expr1.X_add_number; | |
67c0d1eb RS |
6691 | if (gpdelay) |
6692 | macro_build (NULL, "nop", ""); | |
6693 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, | |
6694 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 6695 | load_delay_nop (); |
252b5132 | 6696 | if (breg != 0) |
67c0d1eb | 6697 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 6698 | /* Itbl support may require additional care here. */ |
67c0d1eb RS |
6699 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
6700 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 6701 | offset_expr.X_add_number += 4; |
252b5132 RH |
6702 | |
6703 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
6704 | nop. */ | |
6705 | hold_mips_optimize = mips_optimize; | |
6706 | mips_optimize = 2; | |
beae10d5 | 6707 | /* Itbl support may require additional care here. */ |
67c0d1eb RS |
6708 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
6709 | BFD_RELOC_LO16, AT); | |
252b5132 | 6710 | mips_optimize = hold_mips_optimize; |
4d7206a2 | 6711 | relax_end (); |
252b5132 | 6712 | } |
252b5132 RH |
6713 | else |
6714 | abort (); | |
6715 | ||
b8285c27 | 6716 | if (!used_at) |
252b5132 RH |
6717 | return; |
6718 | ||
6719 | break; | |
6720 | ||
6721 | case M_LD_OB: | |
6722 | s = "lw"; | |
6723 | goto sd_ob; | |
6724 | case M_SD_OB: | |
6725 | s = "sw"; | |
6726 | sd_ob: | |
ca4e0257 | 6727 | assert (HAVE_32BIT_ADDRESSES); |
67c0d1eb | 6728 | macro_build (&offset_expr, s, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
252b5132 | 6729 | offset_expr.X_add_number += 4; |
67c0d1eb | 6730 | macro_build (&offset_expr, s, "t,o(b)", treg + 1, BFD_RELOC_LO16, breg); |
252b5132 RH |
6731 | return; |
6732 | ||
6733 | /* New code added to support COPZ instructions. | |
6734 | This code builds table entries out of the macros in mip_opcodes. | |
6735 | R4000 uses interlocks to handle coproc delays. | |
6736 | Other chips (like the R3000) require nops to be inserted for delays. | |
6737 | ||
f72c8c98 | 6738 | FIXME: Currently, we require that the user handle delays. |
252b5132 RH |
6739 | In order to fill delay slots for non-interlocked chips, |
6740 | we must have a way to specify delays based on the coprocessor. | |
6741 | Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc. | |
6742 | What are the side-effects of the cop instruction? | |
6743 | What cache support might we have and what are its effects? | |
6744 | Both coprocessor & memory require delays. how long??? | |
bdaaa2e1 | 6745 | What registers are read/set/modified? |
252b5132 RH |
6746 | |
6747 | If an itbl is provided to interpret cop instructions, | |
bdaaa2e1 | 6748 | this knowledge can be encoded in the itbl spec. */ |
252b5132 RH |
6749 | |
6750 | case M_COP0: | |
6751 | s = "c0"; | |
6752 | goto copz; | |
6753 | case M_COP1: | |
6754 | s = "c1"; | |
6755 | goto copz; | |
6756 | case M_COP2: | |
6757 | s = "c2"; | |
6758 | goto copz; | |
6759 | case M_COP3: | |
6760 | s = "c3"; | |
6761 | copz: | |
6762 | /* For now we just do C (same as Cz). The parameter will be | |
6763 | stored in insn_opcode by mips_ip. */ | |
67c0d1eb | 6764 | macro_build (NULL, s, "C", ip->insn_opcode); |
252b5132 RH |
6765 | return; |
6766 | ||
ea1fb5dc | 6767 | case M_MOVE: |
67c0d1eb | 6768 | move_register (dreg, sreg); |
ea1fb5dc RS |
6769 | return; |
6770 | ||
252b5132 RH |
6771 | #ifdef LOSING_COMPILER |
6772 | default: | |
6773 | /* Try and see if this is a new itbl instruction. | |
6774 | This code builds table entries out of the macros in mip_opcodes. | |
6775 | FIXME: For now we just assemble the expression and pass it's | |
6776 | value along as a 32-bit immediate. | |
bdaaa2e1 | 6777 | We may want to have the assembler assemble this value, |
252b5132 RH |
6778 | so that we gain the assembler's knowledge of delay slots, |
6779 | symbols, etc. | |
6780 | Would it be more efficient to use mask (id) here? */ | |
bdaaa2e1 | 6781 | if (itbl_have_entries |
252b5132 | 6782 | && (immed_expr = itbl_assemble (ip->insn_mo->name, ""))) |
beae10d5 | 6783 | { |
252b5132 RH |
6784 | s = ip->insn_mo->name; |
6785 | s2 = "cop3"; | |
6786 | coproc = ITBL_DECODE_PNUM (immed_expr);; | |
67c0d1eb | 6787 | macro_build (&immed_expr, s, "C"); |
252b5132 | 6788 | return; |
beae10d5 | 6789 | } |
252b5132 RH |
6790 | macro2 (ip); |
6791 | return; | |
6792 | } | |
6793 | if (mips_opts.noat) | |
6794 | as_warn (_("Macro used $at after \".set noat\"")); | |
6795 | } | |
bdaaa2e1 | 6796 | |
252b5132 | 6797 | static void |
17a2f251 | 6798 | macro2 (struct mips_cl_insn *ip) |
252b5132 RH |
6799 | { |
6800 | register int treg, sreg, dreg, breg; | |
6801 | int tempreg; | |
6802 | int mask; | |
252b5132 RH |
6803 | int used_at; |
6804 | expressionS expr1; | |
6805 | const char *s; | |
6806 | const char *s2; | |
6807 | const char *fmt; | |
6808 | int likely = 0; | |
6809 | int dbl = 0; | |
6810 | int coproc = 0; | |
6811 | int lr = 0; | |
6812 | int imm = 0; | |
6813 | int off; | |
6814 | offsetT maxnum; | |
6815 | bfd_reloc_code_real_type r; | |
bdaaa2e1 | 6816 | |
252b5132 RH |
6817 | treg = (ip->insn_opcode >> 16) & 0x1f; |
6818 | dreg = (ip->insn_opcode >> 11) & 0x1f; | |
6819 | sreg = breg = (ip->insn_opcode >> 21) & 0x1f; | |
6820 | mask = ip->insn_mo->mask; | |
bdaaa2e1 | 6821 | |
252b5132 RH |
6822 | expr1.X_op = O_constant; |
6823 | expr1.X_op_symbol = NULL; | |
6824 | expr1.X_add_symbol = NULL; | |
6825 | expr1.X_add_number = 1; | |
bdaaa2e1 | 6826 | |
252b5132 RH |
6827 | switch (mask) |
6828 | { | |
6829 | #endif /* LOSING_COMPILER */ | |
6830 | ||
6831 | case M_DMUL: | |
6832 | dbl = 1; | |
6833 | case M_MUL: | |
67c0d1eb RS |
6834 | macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", sreg, treg); |
6835 | macro_build (NULL, "mflo", "d", dreg); | |
252b5132 RH |
6836 | return; |
6837 | ||
6838 | case M_DMUL_I: | |
6839 | dbl = 1; | |
6840 | case M_MUL_I: | |
6841 | /* The MIPS assembler some times generates shifts and adds. I'm | |
6842 | not trying to be that fancy. GCC should do this for us | |
6843 | anyway. */ | |
67c0d1eb RS |
6844 | load_register (AT, &imm_expr, dbl); |
6845 | macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, AT); | |
6846 | macro_build (NULL, "mflo", "d", dreg); | |
252b5132 RH |
6847 | break; |
6848 | ||
6849 | case M_DMULO_I: | |
6850 | dbl = 1; | |
6851 | case M_MULO_I: | |
6852 | imm = 1; | |
6853 | goto do_mulo; | |
6854 | ||
6855 | case M_DMULO: | |
6856 | dbl = 1; | |
6857 | case M_MULO: | |
6858 | do_mulo: | |
b34976b6 | 6859 | mips_emit_delays (TRUE); |
252b5132 RH |
6860 | ++mips_opts.noreorder; |
6861 | mips_any_noreorder = 1; | |
6862 | if (imm) | |
67c0d1eb RS |
6863 | load_register (AT, &imm_expr, dbl); |
6864 | macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, imm ? AT : treg); | |
6865 | macro_build (NULL, "mflo", "d", dreg); | |
6866 | macro_build (NULL, dbl ? "dsra32" : "sra", "d,w,<", dreg, dreg, RA); | |
6867 | macro_build (NULL, "mfhi", "d", AT); | |
252b5132 | 6868 | if (mips_trap) |
67c0d1eb | 6869 | macro_build (NULL, "tne", "s,t,q", dreg, AT, 6); |
252b5132 RH |
6870 | else |
6871 | { | |
6872 | expr1.X_add_number = 8; | |
67c0d1eb RS |
6873 | macro_build (&expr1, "beq", "s,t,p", dreg, AT); |
6874 | macro_build (NULL, "nop", "", 0); | |
6875 | macro_build (NULL, "break", "c", 6); | |
252b5132 RH |
6876 | } |
6877 | --mips_opts.noreorder; | |
67c0d1eb | 6878 | macro_build (NULL, "mflo", "d", dreg); |
252b5132 RH |
6879 | break; |
6880 | ||
6881 | case M_DMULOU_I: | |
6882 | dbl = 1; | |
6883 | case M_MULOU_I: | |
6884 | imm = 1; | |
6885 | goto do_mulou; | |
6886 | ||
6887 | case M_DMULOU: | |
6888 | dbl = 1; | |
6889 | case M_MULOU: | |
6890 | do_mulou: | |
b34976b6 | 6891 | mips_emit_delays (TRUE); |
252b5132 RH |
6892 | ++mips_opts.noreorder; |
6893 | mips_any_noreorder = 1; | |
6894 | if (imm) | |
67c0d1eb RS |
6895 | load_register (AT, &imm_expr, dbl); |
6896 | macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", | |
17a2f251 | 6897 | sreg, imm ? AT : treg); |
67c0d1eb RS |
6898 | macro_build (NULL, "mfhi", "d", AT); |
6899 | macro_build (NULL, "mflo", "d", dreg); | |
252b5132 | 6900 | if (mips_trap) |
67c0d1eb | 6901 | macro_build (NULL, "tne", "s,t,q", AT, 0, 6); |
252b5132 RH |
6902 | else |
6903 | { | |
6904 | expr1.X_add_number = 8; | |
67c0d1eb RS |
6905 | macro_build (&expr1, "beq", "s,t,p", AT, 0); |
6906 | macro_build (NULL, "nop", "", 0); | |
6907 | macro_build (NULL, "break", "c", 6); | |
252b5132 RH |
6908 | } |
6909 | --mips_opts.noreorder; | |
6910 | break; | |
6911 | ||
771c7ce4 | 6912 | case M_DROL: |
fef14a42 | 6913 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 CD |
6914 | { |
6915 | if (dreg == sreg) | |
6916 | { | |
6917 | tempreg = AT; | |
6918 | used_at = 1; | |
6919 | } | |
6920 | else | |
6921 | { | |
6922 | tempreg = dreg; | |
82dd0097 | 6923 | } |
67c0d1eb RS |
6924 | macro_build (NULL, "dnegu", "d,w", tempreg, treg); |
6925 | macro_build (NULL, "drorv", "d,t,s", dreg, sreg, tempreg); | |
82dd0097 CD |
6926 | if (used_at) |
6927 | break; | |
6928 | return; | |
6929 | } | |
67c0d1eb RS |
6930 | macro_build (NULL, "dsubu", "d,v,t", AT, 0, treg); |
6931 | macro_build (NULL, "dsrlv", "d,t,s", AT, sreg, AT); | |
6932 | macro_build (NULL, "dsllv", "d,t,s", dreg, sreg, treg); | |
6933 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
6934 | break; |
6935 | ||
252b5132 | 6936 | case M_ROL: |
fef14a42 | 6937 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 CD |
6938 | { |
6939 | if (dreg == sreg) | |
6940 | { | |
6941 | tempreg = AT; | |
6942 | used_at = 1; | |
6943 | } | |
6944 | else | |
6945 | { | |
6946 | tempreg = dreg; | |
82dd0097 | 6947 | } |
67c0d1eb RS |
6948 | macro_build (NULL, "negu", "d,w", tempreg, treg); |
6949 | macro_build (NULL, "rorv", "d,t,s", dreg, sreg, tempreg); | |
82dd0097 CD |
6950 | if (used_at) |
6951 | break; | |
6952 | return; | |
6953 | } | |
67c0d1eb RS |
6954 | macro_build (NULL, "subu", "d,v,t", AT, 0, treg); |
6955 | macro_build (NULL, "srlv", "d,t,s", AT, sreg, AT); | |
6956 | macro_build (NULL, "sllv", "d,t,s", dreg, sreg, treg); | |
6957 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
6958 | break; |
6959 | ||
771c7ce4 TS |
6960 | case M_DROL_I: |
6961 | { | |
6962 | unsigned int rot; | |
82dd0097 | 6963 | char *l, *r; |
771c7ce4 TS |
6964 | |
6965 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 6966 | as_bad (_("Improper rotate count")); |
771c7ce4 | 6967 | rot = imm_expr.X_add_number & 0x3f; |
fef14a42 | 6968 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
60b63b72 RS |
6969 | { |
6970 | rot = (64 - rot) & 0x3f; | |
6971 | if (rot >= 32) | |
67c0d1eb | 6972 | macro_build (NULL, "dror32", "d,w,<", dreg, sreg, rot - 32); |
60b63b72 | 6973 | else |
67c0d1eb | 6974 | macro_build (NULL, "dror", "d,w,<", dreg, sreg, rot); |
82dd0097 | 6975 | return; |
60b63b72 | 6976 | } |
483fc7cd | 6977 | if (rot == 0) |
483fc7cd | 6978 | { |
67c0d1eb | 6979 | macro_build (NULL, "dsrl", "d,w,<", dreg, sreg, 0); |
82dd0097 | 6980 | return; |
483fc7cd | 6981 | } |
82dd0097 CD |
6982 | l = (rot < 0x20) ? "dsll" : "dsll32"; |
6983 | r = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32"; | |
6984 | rot &= 0x1f; | |
67c0d1eb RS |
6985 | macro_build (NULL, l, "d,w,<", AT, sreg, rot); |
6986 | macro_build (NULL, r, "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); | |
6987 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
6988 | } |
6989 | break; | |
6990 | ||
252b5132 | 6991 | case M_ROL_I: |
771c7ce4 TS |
6992 | { |
6993 | unsigned int rot; | |
6994 | ||
6995 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 6996 | as_bad (_("Improper rotate count")); |
771c7ce4 | 6997 | rot = imm_expr.X_add_number & 0x1f; |
fef14a42 | 6998 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
60b63b72 | 6999 | { |
67c0d1eb | 7000 | macro_build (NULL, "ror", "d,w,<", dreg, sreg, (32 - rot) & 0x1f); |
82dd0097 | 7001 | return; |
60b63b72 | 7002 | } |
483fc7cd | 7003 | if (rot == 0) |
483fc7cd | 7004 | { |
67c0d1eb | 7005 | macro_build (NULL, "srl", "d,w,<", dreg, sreg, 0); |
82dd0097 | 7006 | return; |
483fc7cd | 7007 | } |
67c0d1eb RS |
7008 | macro_build (NULL, "sll", "d,w,<", AT, sreg, rot); |
7009 | macro_build (NULL, "srl", "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); | |
7010 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
7011 | } |
7012 | break; | |
7013 | ||
7014 | case M_DROR: | |
fef14a42 | 7015 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 | 7016 | { |
67c0d1eb | 7017 | macro_build (NULL, "drorv", "d,t,s", dreg, sreg, treg); |
82dd0097 CD |
7018 | return; |
7019 | } | |
67c0d1eb RS |
7020 | macro_build (NULL, "dsubu", "d,v,t", AT, 0, treg); |
7021 | macro_build (NULL, "dsllv", "d,t,s", AT, sreg, AT); | |
7022 | macro_build (NULL, "dsrlv", "d,t,s", dreg, sreg, treg); | |
7023 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
7024 | break; |
7025 | ||
7026 | case M_ROR: | |
fef14a42 | 7027 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 | 7028 | { |
67c0d1eb | 7029 | macro_build (NULL, "rorv", "d,t,s", dreg, sreg, treg); |
82dd0097 CD |
7030 | return; |
7031 | } | |
67c0d1eb RS |
7032 | macro_build (NULL, "subu", "d,v,t", AT, 0, treg); |
7033 | macro_build (NULL, "sllv", "d,t,s", AT, sreg, AT); | |
7034 | macro_build (NULL, "srlv", "d,t,s", dreg, sreg, treg); | |
7035 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
7036 | break; |
7037 | ||
771c7ce4 TS |
7038 | case M_DROR_I: |
7039 | { | |
7040 | unsigned int rot; | |
82dd0097 | 7041 | char *l, *r; |
771c7ce4 TS |
7042 | |
7043 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 7044 | as_bad (_("Improper rotate count")); |
771c7ce4 | 7045 | rot = imm_expr.X_add_number & 0x3f; |
fef14a42 | 7046 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 CD |
7047 | { |
7048 | if (rot >= 32) | |
67c0d1eb | 7049 | macro_build (NULL, "dror32", "d,w,<", dreg, sreg, rot - 32); |
82dd0097 | 7050 | else |
67c0d1eb | 7051 | macro_build (NULL, "dror", "d,w,<", dreg, sreg, rot); |
82dd0097 CD |
7052 | return; |
7053 | } | |
483fc7cd | 7054 | if (rot == 0) |
483fc7cd | 7055 | { |
67c0d1eb | 7056 | macro_build (NULL, "dsrl", "d,w,<", dreg, sreg, 0); |
82dd0097 | 7057 | return; |
483fc7cd | 7058 | } |
82dd0097 CD |
7059 | r = (rot < 0x20) ? "dsrl" : "dsrl32"; |
7060 | l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32"; | |
7061 | rot &= 0x1f; | |
67c0d1eb RS |
7062 | macro_build (NULL, r, "d,w,<", AT, sreg, rot); |
7063 | macro_build (NULL, l, "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); | |
7064 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
7065 | } |
7066 | break; | |
7067 | ||
252b5132 | 7068 | case M_ROR_I: |
771c7ce4 TS |
7069 | { |
7070 | unsigned int rot; | |
7071 | ||
7072 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 7073 | as_bad (_("Improper rotate count")); |
771c7ce4 | 7074 | rot = imm_expr.X_add_number & 0x1f; |
fef14a42 | 7075 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 | 7076 | { |
67c0d1eb | 7077 | macro_build (NULL, "ror", "d,w,<", dreg, sreg, rot); |
82dd0097 CD |
7078 | return; |
7079 | } | |
483fc7cd | 7080 | if (rot == 0) |
483fc7cd | 7081 | { |
67c0d1eb | 7082 | macro_build (NULL, "srl", "d,w,<", dreg, sreg, 0); |
82dd0097 | 7083 | return; |
483fc7cd | 7084 | } |
67c0d1eb RS |
7085 | macro_build (NULL, "srl", "d,w,<", AT, sreg, rot); |
7086 | macro_build (NULL, "sll", "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); | |
7087 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 | 7088 | } |
252b5132 RH |
7089 | break; |
7090 | ||
7091 | case M_S_DOB: | |
fef14a42 | 7092 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
7093 | { |
7094 | as_bad (_("opcode not supported on this processor")); | |
7095 | return; | |
7096 | } | |
e7af610e | 7097 | assert (mips_opts.isa == ISA_MIPS1); |
252b5132 RH |
7098 | /* Even on a big endian machine $fn comes before $fn+1. We have |
7099 | to adjust when storing to memory. */ | |
67c0d1eb RS |
7100 | macro_build (&offset_expr, "swc1", "T,o(b)", |
7101 | target_big_endian ? treg + 1 : treg, BFD_RELOC_LO16, breg); | |
252b5132 | 7102 | offset_expr.X_add_number += 4; |
67c0d1eb RS |
7103 | macro_build (&offset_expr, "swc1", "T,o(b)", |
7104 | target_big_endian ? treg : treg + 1, BFD_RELOC_LO16, breg); | |
252b5132 RH |
7105 | return; |
7106 | ||
7107 | case M_SEQ: | |
7108 | if (sreg == 0) | |
67c0d1eb | 7109 | macro_build (&expr1, "sltiu", "t,r,j", dreg, treg, BFD_RELOC_LO16); |
252b5132 | 7110 | else if (treg == 0) |
67c0d1eb | 7111 | macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7112 | else |
7113 | { | |
67c0d1eb RS |
7114 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg); |
7115 | macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16); | |
252b5132 RH |
7116 | } |
7117 | return; | |
7118 | ||
7119 | case M_SEQ_I: | |
7120 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
7121 | { | |
67c0d1eb | 7122 | macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7123 | return; |
7124 | } | |
7125 | if (sreg == 0) | |
7126 | { | |
7127 | as_warn (_("Instruction %s: result is always false"), | |
7128 | ip->insn_mo->name); | |
67c0d1eb | 7129 | move_register (dreg, 0); |
252b5132 RH |
7130 | return; |
7131 | } | |
7132 | if (imm_expr.X_op == O_constant | |
7133 | && imm_expr.X_add_number >= 0 | |
7134 | && imm_expr.X_add_number < 0x10000) | |
7135 | { | |
67c0d1eb | 7136 | macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7137 | } |
7138 | else if (imm_expr.X_op == O_constant | |
7139 | && imm_expr.X_add_number > -0x8000 | |
7140 | && imm_expr.X_add_number < 0) | |
7141 | { | |
7142 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 7143 | macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu", |
17a2f251 | 7144 | "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7145 | } |
7146 | else | |
7147 | { | |
67c0d1eb RS |
7148 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7149 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7150 | used_at = 1; |
7151 | } | |
67c0d1eb | 7152 | macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16); |
252b5132 RH |
7153 | if (used_at) |
7154 | break; | |
7155 | return; | |
7156 | ||
7157 | case M_SGE: /* sreg >= treg <==> not (sreg < treg) */ | |
7158 | s = "slt"; | |
7159 | goto sge; | |
7160 | case M_SGEU: | |
7161 | s = "sltu"; | |
7162 | sge: | |
67c0d1eb RS |
7163 | macro_build (NULL, s, "d,v,t", dreg, sreg, treg); |
7164 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
252b5132 RH |
7165 | return; |
7166 | ||
7167 | case M_SGE_I: /* sreg >= I <==> not (sreg < I) */ | |
7168 | case M_SGEU_I: | |
7169 | if (imm_expr.X_op == O_constant | |
7170 | && imm_expr.X_add_number >= -0x8000 | |
7171 | && imm_expr.X_add_number < 0x8000) | |
7172 | { | |
67c0d1eb RS |
7173 | macro_build (&imm_expr, mask == M_SGE_I ? "slti" : "sltiu", "t,r,j", |
7174 | dreg, sreg, BFD_RELOC_LO16); | |
252b5132 RH |
7175 | } |
7176 | else | |
7177 | { | |
67c0d1eb RS |
7178 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7179 | macro_build (NULL, mask == M_SGE_I ? "slt" : "sltu", "d,v,t", | |
7180 | dreg, sreg, AT); | |
252b5132 RH |
7181 | used_at = 1; |
7182 | } | |
67c0d1eb | 7183 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); |
252b5132 RH |
7184 | if (used_at) |
7185 | break; | |
7186 | return; | |
7187 | ||
7188 | case M_SGT: /* sreg > treg <==> treg < sreg */ | |
7189 | s = "slt"; | |
7190 | goto sgt; | |
7191 | case M_SGTU: | |
7192 | s = "sltu"; | |
7193 | sgt: | |
67c0d1eb | 7194 | macro_build (NULL, s, "d,v,t", dreg, treg, sreg); |
252b5132 RH |
7195 | return; |
7196 | ||
7197 | case M_SGT_I: /* sreg > I <==> I < sreg */ | |
7198 | s = "slt"; | |
7199 | goto sgti; | |
7200 | case M_SGTU_I: | |
7201 | s = "sltu"; | |
7202 | sgti: | |
67c0d1eb RS |
7203 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7204 | macro_build (NULL, s, "d,v,t", dreg, AT, sreg); | |
252b5132 RH |
7205 | break; |
7206 | ||
2396cfb9 | 7207 | case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */ |
252b5132 RH |
7208 | s = "slt"; |
7209 | goto sle; | |
7210 | case M_SLEU: | |
7211 | s = "sltu"; | |
7212 | sle: | |
67c0d1eb RS |
7213 | macro_build (NULL, s, "d,v,t", dreg, treg, sreg); |
7214 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
252b5132 RH |
7215 | return; |
7216 | ||
2396cfb9 | 7217 | case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */ |
252b5132 RH |
7218 | s = "slt"; |
7219 | goto slei; | |
7220 | case M_SLEU_I: | |
7221 | s = "sltu"; | |
7222 | slei: | |
67c0d1eb RS |
7223 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7224 | macro_build (NULL, s, "d,v,t", dreg, AT, sreg); | |
7225 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
252b5132 RH |
7226 | break; |
7227 | ||
7228 | case M_SLT_I: | |
7229 | if (imm_expr.X_op == O_constant | |
7230 | && imm_expr.X_add_number >= -0x8000 | |
7231 | && imm_expr.X_add_number < 0x8000) | |
7232 | { | |
67c0d1eb | 7233 | macro_build (&imm_expr, "slti", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7234 | return; |
7235 | } | |
67c0d1eb RS |
7236 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7237 | macro_build (NULL, "slt", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7238 | break; |
7239 | ||
7240 | case M_SLTU_I: | |
7241 | if (imm_expr.X_op == O_constant | |
7242 | && imm_expr.X_add_number >= -0x8000 | |
7243 | && imm_expr.X_add_number < 0x8000) | |
7244 | { | |
67c0d1eb | 7245 | macro_build (&imm_expr, "sltiu", "t,r,j", dreg, sreg, |
17a2f251 | 7246 | BFD_RELOC_LO16); |
252b5132 RH |
7247 | return; |
7248 | } | |
67c0d1eb RS |
7249 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7250 | macro_build (NULL, "sltu", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7251 | break; |
7252 | ||
7253 | case M_SNE: | |
7254 | if (sreg == 0) | |
67c0d1eb | 7255 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, treg); |
252b5132 | 7256 | else if (treg == 0) |
67c0d1eb | 7257 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg); |
252b5132 RH |
7258 | else |
7259 | { | |
67c0d1eb RS |
7260 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg); |
7261 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg); | |
252b5132 RH |
7262 | } |
7263 | return; | |
7264 | ||
7265 | case M_SNE_I: | |
7266 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
7267 | { | |
67c0d1eb | 7268 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg); |
252b5132 RH |
7269 | return; |
7270 | } | |
7271 | if (sreg == 0) | |
7272 | { | |
7273 | as_warn (_("Instruction %s: result is always true"), | |
7274 | ip->insn_mo->name); | |
67c0d1eb RS |
7275 | macro_build (&expr1, HAVE_32BIT_GPRS ? "addiu" : "daddiu", "t,r,j", |
7276 | dreg, 0, BFD_RELOC_LO16); | |
252b5132 RH |
7277 | return; |
7278 | } | |
7279 | if (imm_expr.X_op == O_constant | |
7280 | && imm_expr.X_add_number >= 0 | |
7281 | && imm_expr.X_add_number < 0x10000) | |
7282 | { | |
67c0d1eb | 7283 | macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7284 | } |
7285 | else if (imm_expr.X_op == O_constant | |
7286 | && imm_expr.X_add_number > -0x8000 | |
7287 | && imm_expr.X_add_number < 0) | |
7288 | { | |
7289 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 7290 | macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu", |
17a2f251 | 7291 | "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7292 | } |
7293 | else | |
7294 | { | |
67c0d1eb RS |
7295 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7296 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7297 | used_at = 1; |
7298 | } | |
67c0d1eb | 7299 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg); |
252b5132 RH |
7300 | if (used_at) |
7301 | break; | |
7302 | return; | |
7303 | ||
7304 | case M_DSUB_I: | |
7305 | dbl = 1; | |
7306 | case M_SUB_I: | |
7307 | if (imm_expr.X_op == O_constant | |
7308 | && imm_expr.X_add_number > -0x8000 | |
7309 | && imm_expr.X_add_number <= 0x8000) | |
7310 | { | |
7311 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb RS |
7312 | macro_build (&imm_expr, dbl ? "daddi" : "addi", "t,r,j", |
7313 | dreg, sreg, BFD_RELOC_LO16); | |
252b5132 RH |
7314 | return; |
7315 | } | |
67c0d1eb RS |
7316 | load_register (AT, &imm_expr, dbl); |
7317 | macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7318 | break; |
7319 | ||
7320 | case M_DSUBU_I: | |
7321 | dbl = 1; | |
7322 | case M_SUBU_I: | |
7323 | if (imm_expr.X_op == O_constant | |
7324 | && imm_expr.X_add_number > -0x8000 | |
7325 | && imm_expr.X_add_number <= 0x8000) | |
7326 | { | |
7327 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb RS |
7328 | macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "t,r,j", |
7329 | dreg, sreg, BFD_RELOC_LO16); | |
252b5132 RH |
7330 | return; |
7331 | } | |
67c0d1eb RS |
7332 | load_register (AT, &imm_expr, dbl); |
7333 | macro_build (NULL, dbl ? "dsubu" : "subu", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7334 | break; |
7335 | ||
7336 | case M_TEQ_I: | |
7337 | s = "teq"; | |
7338 | goto trap; | |
7339 | case M_TGE_I: | |
7340 | s = "tge"; | |
7341 | goto trap; | |
7342 | case M_TGEU_I: | |
7343 | s = "tgeu"; | |
7344 | goto trap; | |
7345 | case M_TLT_I: | |
7346 | s = "tlt"; | |
7347 | goto trap; | |
7348 | case M_TLTU_I: | |
7349 | s = "tltu"; | |
7350 | goto trap; | |
7351 | case M_TNE_I: | |
7352 | s = "tne"; | |
7353 | trap: | |
67c0d1eb RS |
7354 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7355 | macro_build (NULL, s, "s,t", sreg, AT); | |
252b5132 RH |
7356 | break; |
7357 | ||
252b5132 | 7358 | case M_TRUNCWS: |
43841e91 | 7359 | case M_TRUNCWD: |
e7af610e | 7360 | assert (mips_opts.isa == ISA_MIPS1); |
252b5132 RH |
7361 | sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */ |
7362 | dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */ | |
7363 | ||
7364 | /* | |
7365 | * Is the double cfc1 instruction a bug in the mips assembler; | |
7366 | * or is there a reason for it? | |
7367 | */ | |
b34976b6 | 7368 | mips_emit_delays (TRUE); |
252b5132 RH |
7369 | ++mips_opts.noreorder; |
7370 | mips_any_noreorder = 1; | |
67c0d1eb RS |
7371 | macro_build (NULL, "cfc1", "t,G", treg, RA); |
7372 | macro_build (NULL, "cfc1", "t,G", treg, RA); | |
7373 | macro_build (NULL, "nop", ""); | |
252b5132 | 7374 | expr1.X_add_number = 3; |
67c0d1eb | 7375 | macro_build (&expr1, "ori", "t,r,i", AT, treg, BFD_RELOC_LO16); |
252b5132 | 7376 | expr1.X_add_number = 2; |
67c0d1eb RS |
7377 | macro_build (&expr1, "xori", "t,r,i", AT, AT, BFD_RELOC_LO16); |
7378 | macro_build (NULL, "ctc1", "t,G", AT, RA); | |
7379 | macro_build (NULL, "nop", ""); | |
7380 | macro_build (NULL, mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S", | |
7381 | dreg, sreg); | |
7382 | macro_build (NULL, "ctc1", "t,G", treg, RA); | |
7383 | macro_build (NULL, "nop", ""); | |
252b5132 RH |
7384 | --mips_opts.noreorder; |
7385 | break; | |
7386 | ||
7387 | case M_ULH: | |
7388 | s = "lb"; | |
7389 | goto ulh; | |
7390 | case M_ULHU: | |
7391 | s = "lbu"; | |
7392 | ulh: | |
7393 | if (offset_expr.X_add_number >= 0x7fff) | |
7394 | as_bad (_("operand overflow")); | |
252b5132 | 7395 | if (! target_big_endian) |
f9419b05 | 7396 | ++offset_expr.X_add_number; |
67c0d1eb | 7397 | macro_build (&offset_expr, s, "t,o(b)", AT, BFD_RELOC_LO16, breg); |
252b5132 | 7398 | if (! target_big_endian) |
f9419b05 | 7399 | --offset_expr.X_add_number; |
252b5132 | 7400 | else |
f9419b05 | 7401 | ++offset_expr.X_add_number; |
67c0d1eb RS |
7402 | macro_build (&offset_expr, "lbu", "t,o(b)", treg, BFD_RELOC_LO16, breg); |
7403 | macro_build (NULL, "sll", "d,w,<", AT, AT, 8); | |
7404 | macro_build (NULL, "or", "d,v,t", treg, treg, AT); | |
252b5132 RH |
7405 | break; |
7406 | ||
7407 | case M_ULD: | |
7408 | s = "ldl"; | |
7409 | s2 = "ldr"; | |
7410 | off = 7; | |
7411 | goto ulw; | |
7412 | case M_ULW: | |
7413 | s = "lwl"; | |
7414 | s2 = "lwr"; | |
7415 | off = 3; | |
7416 | ulw: | |
7417 | if (offset_expr.X_add_number >= 0x8000 - off) | |
7418 | as_bad (_("operand overflow")); | |
af22f5b2 CD |
7419 | if (treg != breg) |
7420 | tempreg = treg; | |
7421 | else | |
7422 | tempreg = AT; | |
252b5132 RH |
7423 | if (! target_big_endian) |
7424 | offset_expr.X_add_number += off; | |
67c0d1eb | 7425 | macro_build (&offset_expr, s, "t,o(b)", tempreg, BFD_RELOC_LO16, breg); |
252b5132 RH |
7426 | if (! target_big_endian) |
7427 | offset_expr.X_add_number -= off; | |
7428 | else | |
7429 | offset_expr.X_add_number += off; | |
67c0d1eb | 7430 | macro_build (&offset_expr, s2, "t,o(b)", tempreg, BFD_RELOC_LO16, breg); |
af22f5b2 CD |
7431 | |
7432 | /* If necessary, move the result in tempreg the final destination. */ | |
7433 | if (treg == tempreg) | |
7434 | return; | |
7435 | /* Protect second load's delay slot. */ | |
017315e4 | 7436 | load_delay_nop (); |
67c0d1eb | 7437 | move_register (treg, tempreg); |
af22f5b2 | 7438 | break; |
252b5132 RH |
7439 | |
7440 | case M_ULD_A: | |
7441 | s = "ldl"; | |
7442 | s2 = "ldr"; | |
7443 | off = 7; | |
7444 | goto ulwa; | |
7445 | case M_ULW_A: | |
7446 | s = "lwl"; | |
7447 | s2 = "lwr"; | |
7448 | off = 3; | |
7449 | ulwa: | |
d6bc6245 | 7450 | used_at = 1; |
67c0d1eb | 7451 | load_address (AT, &offset_expr, &used_at); |
252b5132 | 7452 | if (breg != 0) |
67c0d1eb | 7453 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); |
252b5132 RH |
7454 | if (! target_big_endian) |
7455 | expr1.X_add_number = off; | |
7456 | else | |
7457 | expr1.X_add_number = 0; | |
67c0d1eb | 7458 | macro_build (&expr1, s, "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
7459 | if (! target_big_endian) |
7460 | expr1.X_add_number = 0; | |
7461 | else | |
7462 | expr1.X_add_number = off; | |
67c0d1eb | 7463 | macro_build (&expr1, s2, "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
7464 | break; |
7465 | ||
7466 | case M_ULH_A: | |
7467 | case M_ULHU_A: | |
d6bc6245 | 7468 | used_at = 1; |
67c0d1eb | 7469 | load_address (AT, &offset_expr, &used_at); |
252b5132 | 7470 | if (breg != 0) |
67c0d1eb | 7471 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); |
252b5132 RH |
7472 | if (target_big_endian) |
7473 | expr1.X_add_number = 0; | |
67c0d1eb | 7474 | macro_build (&expr1, mask == M_ULH_A ? "lb" : "lbu", "t,o(b)", |
17a2f251 | 7475 | treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
7476 | if (target_big_endian) |
7477 | expr1.X_add_number = 1; | |
7478 | else | |
7479 | expr1.X_add_number = 0; | |
67c0d1eb RS |
7480 | macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT); |
7481 | macro_build (NULL, "sll", "d,w,<", treg, treg, 8); | |
7482 | macro_build (NULL, "or", "d,v,t", treg, treg, AT); | |
252b5132 RH |
7483 | break; |
7484 | ||
7485 | case M_USH: | |
7486 | if (offset_expr.X_add_number >= 0x7fff) | |
7487 | as_bad (_("operand overflow")); | |
7488 | if (target_big_endian) | |
f9419b05 | 7489 | ++offset_expr.X_add_number; |
67c0d1eb RS |
7490 | macro_build (&offset_expr, "sb", "t,o(b)", treg, BFD_RELOC_LO16, breg); |
7491 | macro_build (NULL, "srl", "d,w,<", AT, treg, 8); | |
252b5132 | 7492 | if (target_big_endian) |
f9419b05 | 7493 | --offset_expr.X_add_number; |
252b5132 | 7494 | else |
f9419b05 | 7495 | ++offset_expr.X_add_number; |
67c0d1eb | 7496 | macro_build (&offset_expr, "sb", "t,o(b)", AT, BFD_RELOC_LO16, breg); |
252b5132 RH |
7497 | break; |
7498 | ||
7499 | case M_USD: | |
7500 | s = "sdl"; | |
7501 | s2 = "sdr"; | |
7502 | off = 7; | |
7503 | goto usw; | |
7504 | case M_USW: | |
7505 | s = "swl"; | |
7506 | s2 = "swr"; | |
7507 | off = 3; | |
7508 | usw: | |
7509 | if (offset_expr.X_add_number >= 0x8000 - off) | |
7510 | as_bad (_("operand overflow")); | |
7511 | if (! target_big_endian) | |
7512 | offset_expr.X_add_number += off; | |
67c0d1eb | 7513 | macro_build (&offset_expr, s, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
252b5132 RH |
7514 | if (! target_big_endian) |
7515 | offset_expr.X_add_number -= off; | |
7516 | else | |
7517 | offset_expr.X_add_number += off; | |
67c0d1eb | 7518 | macro_build (&offset_expr, s2, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
252b5132 RH |
7519 | return; |
7520 | ||
7521 | case M_USD_A: | |
7522 | s = "sdl"; | |
7523 | s2 = "sdr"; | |
7524 | off = 7; | |
7525 | goto uswa; | |
7526 | case M_USW_A: | |
7527 | s = "swl"; | |
7528 | s2 = "swr"; | |
7529 | off = 3; | |
7530 | uswa: | |
d6bc6245 | 7531 | used_at = 1; |
67c0d1eb | 7532 | load_address (AT, &offset_expr, &used_at); |
252b5132 | 7533 | if (breg != 0) |
67c0d1eb | 7534 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); |
252b5132 RH |
7535 | if (! target_big_endian) |
7536 | expr1.X_add_number = off; | |
7537 | else | |
7538 | expr1.X_add_number = 0; | |
67c0d1eb | 7539 | macro_build (&expr1, s, "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
7540 | if (! target_big_endian) |
7541 | expr1.X_add_number = 0; | |
7542 | else | |
7543 | expr1.X_add_number = off; | |
67c0d1eb | 7544 | macro_build (&expr1, s2, "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
7545 | break; |
7546 | ||
7547 | case M_USH_A: | |
d6bc6245 | 7548 | used_at = 1; |
67c0d1eb | 7549 | load_address (AT, &offset_expr, &used_at); |
252b5132 | 7550 | if (breg != 0) |
67c0d1eb | 7551 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); |
252b5132 RH |
7552 | if (! target_big_endian) |
7553 | expr1.X_add_number = 0; | |
67c0d1eb RS |
7554 | macro_build (&expr1, "sb", "t,o(b)", treg, BFD_RELOC_LO16, AT); |
7555 | macro_build (NULL, "srl", "d,w,<", treg, treg, 8); | |
252b5132 RH |
7556 | if (! target_big_endian) |
7557 | expr1.X_add_number = 1; | |
7558 | else | |
7559 | expr1.X_add_number = 0; | |
67c0d1eb | 7560 | macro_build (&expr1, "sb", "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
7561 | if (! target_big_endian) |
7562 | expr1.X_add_number = 0; | |
7563 | else | |
7564 | expr1.X_add_number = 1; | |
67c0d1eb RS |
7565 | macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT); |
7566 | macro_build (NULL, "sll", "d,w,<", treg, treg, 8); | |
7567 | macro_build (NULL, "or", "d,v,t", treg, treg, AT); | |
252b5132 RH |
7568 | break; |
7569 | ||
7570 | default: | |
7571 | /* FIXME: Check if this is one of the itbl macros, since they | |
bdaaa2e1 | 7572 | are added dynamically. */ |
252b5132 RH |
7573 | as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name); |
7574 | break; | |
7575 | } | |
7576 | if (mips_opts.noat) | |
7577 | as_warn (_("Macro used $at after \".set noat\"")); | |
7578 | } | |
7579 | ||
7580 | /* Implement macros in mips16 mode. */ | |
7581 | ||
7582 | static void | |
17a2f251 | 7583 | mips16_macro (struct mips_cl_insn *ip) |
252b5132 RH |
7584 | { |
7585 | int mask; | |
7586 | int xreg, yreg, zreg, tmp; | |
252b5132 RH |
7587 | expressionS expr1; |
7588 | int dbl; | |
7589 | const char *s, *s2, *s3; | |
7590 | ||
7591 | mask = ip->insn_mo->mask; | |
7592 | ||
7593 | xreg = (ip->insn_opcode >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX; | |
7594 | yreg = (ip->insn_opcode >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY; | |
7595 | zreg = (ip->insn_opcode >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ; | |
7596 | ||
252b5132 RH |
7597 | expr1.X_op = O_constant; |
7598 | expr1.X_op_symbol = NULL; | |
7599 | expr1.X_add_symbol = NULL; | |
7600 | expr1.X_add_number = 1; | |
7601 | ||
7602 | dbl = 0; | |
7603 | ||
7604 | switch (mask) | |
7605 | { | |
7606 | default: | |
7607 | internalError (); | |
7608 | ||
7609 | case M_DDIV_3: | |
7610 | dbl = 1; | |
7611 | case M_DIV_3: | |
7612 | s = "mflo"; | |
7613 | goto do_div3; | |
7614 | case M_DREM_3: | |
7615 | dbl = 1; | |
7616 | case M_REM_3: | |
7617 | s = "mfhi"; | |
7618 | do_div3: | |
b34976b6 | 7619 | mips_emit_delays (TRUE); |
252b5132 RH |
7620 | ++mips_opts.noreorder; |
7621 | mips_any_noreorder = 1; | |
67c0d1eb | 7622 | macro_build (NULL, dbl ? "ddiv" : "div", "0,x,y", xreg, yreg); |
252b5132 | 7623 | expr1.X_add_number = 2; |
67c0d1eb RS |
7624 | macro_build (&expr1, "bnez", "x,p", yreg); |
7625 | macro_build (NULL, "break", "6", 7); | |
bdaaa2e1 | 7626 | |
252b5132 RH |
7627 | /* FIXME: The normal code checks for of -1 / -0x80000000 here, |
7628 | since that causes an overflow. We should do that as well, | |
7629 | but I don't see how to do the comparisons without a temporary | |
7630 | register. */ | |
7631 | --mips_opts.noreorder; | |
67c0d1eb | 7632 | macro_build (NULL, s, "x", zreg); |
252b5132 RH |
7633 | break; |
7634 | ||
7635 | case M_DIVU_3: | |
7636 | s = "divu"; | |
7637 | s2 = "mflo"; | |
7638 | goto do_divu3; | |
7639 | case M_REMU_3: | |
7640 | s = "divu"; | |
7641 | s2 = "mfhi"; | |
7642 | goto do_divu3; | |
7643 | case M_DDIVU_3: | |
7644 | s = "ddivu"; | |
7645 | s2 = "mflo"; | |
7646 | goto do_divu3; | |
7647 | case M_DREMU_3: | |
7648 | s = "ddivu"; | |
7649 | s2 = "mfhi"; | |
7650 | do_divu3: | |
b34976b6 | 7651 | mips_emit_delays (TRUE); |
252b5132 RH |
7652 | ++mips_opts.noreorder; |
7653 | mips_any_noreorder = 1; | |
67c0d1eb | 7654 | macro_build (NULL, s, "0,x,y", xreg, yreg); |
252b5132 | 7655 | expr1.X_add_number = 2; |
67c0d1eb RS |
7656 | macro_build (&expr1, "bnez", "x,p", yreg); |
7657 | macro_build (NULL, "break", "6", 7); | |
252b5132 | 7658 | --mips_opts.noreorder; |
67c0d1eb | 7659 | macro_build (NULL, s2, "x", zreg); |
252b5132 RH |
7660 | break; |
7661 | ||
7662 | case M_DMUL: | |
7663 | dbl = 1; | |
7664 | case M_MUL: | |
67c0d1eb RS |
7665 | macro_build (NULL, dbl ? "dmultu" : "multu", "x,y", xreg, yreg); |
7666 | macro_build (NULL, "mflo", "x", zreg); | |
252b5132 RH |
7667 | return; |
7668 | ||
7669 | case M_DSUBU_I: | |
7670 | dbl = 1; | |
7671 | goto do_subu; | |
7672 | case M_SUBU_I: | |
7673 | do_subu: | |
7674 | if (imm_expr.X_op != O_constant) | |
7675 | as_bad (_("Unsupported large constant")); | |
7676 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 7677 | macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "y,x,4", yreg, xreg); |
252b5132 RH |
7678 | break; |
7679 | ||
7680 | case M_SUBU_I_2: | |
7681 | if (imm_expr.X_op != O_constant) | |
7682 | as_bad (_("Unsupported large constant")); | |
7683 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 7684 | macro_build (&imm_expr, "addiu", "x,k", xreg); |
252b5132 RH |
7685 | break; |
7686 | ||
7687 | case M_DSUBU_I_2: | |
7688 | if (imm_expr.X_op != O_constant) | |
7689 | as_bad (_("Unsupported large constant")); | |
7690 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 7691 | macro_build (&imm_expr, "daddiu", "y,j", yreg); |
252b5132 RH |
7692 | break; |
7693 | ||
7694 | case M_BEQ: | |
7695 | s = "cmp"; | |
7696 | s2 = "bteqz"; | |
7697 | goto do_branch; | |
7698 | case M_BNE: | |
7699 | s = "cmp"; | |
7700 | s2 = "btnez"; | |
7701 | goto do_branch; | |
7702 | case M_BLT: | |
7703 | s = "slt"; | |
7704 | s2 = "btnez"; | |
7705 | goto do_branch; | |
7706 | case M_BLTU: | |
7707 | s = "sltu"; | |
7708 | s2 = "btnez"; | |
7709 | goto do_branch; | |
7710 | case M_BLE: | |
7711 | s = "slt"; | |
7712 | s2 = "bteqz"; | |
7713 | goto do_reverse_branch; | |
7714 | case M_BLEU: | |
7715 | s = "sltu"; | |
7716 | s2 = "bteqz"; | |
7717 | goto do_reverse_branch; | |
7718 | case M_BGE: | |
7719 | s = "slt"; | |
7720 | s2 = "bteqz"; | |
7721 | goto do_branch; | |
7722 | case M_BGEU: | |
7723 | s = "sltu"; | |
7724 | s2 = "bteqz"; | |
7725 | goto do_branch; | |
7726 | case M_BGT: | |
7727 | s = "slt"; | |
7728 | s2 = "btnez"; | |
7729 | goto do_reverse_branch; | |
7730 | case M_BGTU: | |
7731 | s = "sltu"; | |
7732 | s2 = "btnez"; | |
7733 | ||
7734 | do_reverse_branch: | |
7735 | tmp = xreg; | |
7736 | xreg = yreg; | |
7737 | yreg = tmp; | |
7738 | ||
7739 | do_branch: | |
67c0d1eb RS |
7740 | macro_build (NULL, s, "x,y", xreg, yreg); |
7741 | macro_build (&offset_expr, s2, "p"); | |
252b5132 RH |
7742 | break; |
7743 | ||
7744 | case M_BEQ_I: | |
7745 | s = "cmpi"; | |
7746 | s2 = "bteqz"; | |
7747 | s3 = "x,U"; | |
7748 | goto do_branch_i; | |
7749 | case M_BNE_I: | |
7750 | s = "cmpi"; | |
7751 | s2 = "btnez"; | |
7752 | s3 = "x,U"; | |
7753 | goto do_branch_i; | |
7754 | case M_BLT_I: | |
7755 | s = "slti"; | |
7756 | s2 = "btnez"; | |
7757 | s3 = "x,8"; | |
7758 | goto do_branch_i; | |
7759 | case M_BLTU_I: | |
7760 | s = "sltiu"; | |
7761 | s2 = "btnez"; | |
7762 | s3 = "x,8"; | |
7763 | goto do_branch_i; | |
7764 | case M_BLE_I: | |
7765 | s = "slti"; | |
7766 | s2 = "btnez"; | |
7767 | s3 = "x,8"; | |
7768 | goto do_addone_branch_i; | |
7769 | case M_BLEU_I: | |
7770 | s = "sltiu"; | |
7771 | s2 = "btnez"; | |
7772 | s3 = "x,8"; | |
7773 | goto do_addone_branch_i; | |
7774 | case M_BGE_I: | |
7775 | s = "slti"; | |
7776 | s2 = "bteqz"; | |
7777 | s3 = "x,8"; | |
7778 | goto do_branch_i; | |
7779 | case M_BGEU_I: | |
7780 | s = "sltiu"; | |
7781 | s2 = "bteqz"; | |
7782 | s3 = "x,8"; | |
7783 | goto do_branch_i; | |
7784 | case M_BGT_I: | |
7785 | s = "slti"; | |
7786 | s2 = "bteqz"; | |
7787 | s3 = "x,8"; | |
7788 | goto do_addone_branch_i; | |
7789 | case M_BGTU_I: | |
7790 | s = "sltiu"; | |
7791 | s2 = "bteqz"; | |
7792 | s3 = "x,8"; | |
7793 | ||
7794 | do_addone_branch_i: | |
7795 | if (imm_expr.X_op != O_constant) | |
7796 | as_bad (_("Unsupported large constant")); | |
7797 | ++imm_expr.X_add_number; | |
7798 | ||
7799 | do_branch_i: | |
67c0d1eb RS |
7800 | macro_build (&imm_expr, s, s3, xreg); |
7801 | macro_build (&offset_expr, s2, "p"); | |
252b5132 RH |
7802 | break; |
7803 | ||
7804 | case M_ABS: | |
7805 | expr1.X_add_number = 0; | |
67c0d1eb | 7806 | macro_build (&expr1, "slti", "x,8", yreg); |
252b5132 | 7807 | if (xreg != yreg) |
67c0d1eb | 7808 | move_register (xreg, yreg); |
252b5132 | 7809 | expr1.X_add_number = 2; |
67c0d1eb RS |
7810 | macro_build (&expr1, "bteqz", "p"); |
7811 | macro_build (NULL, "neg", "x,w", xreg, xreg); | |
252b5132 RH |
7812 | } |
7813 | } | |
7814 | ||
7815 | /* For consistency checking, verify that all bits are specified either | |
7816 | by the match/mask part of the instruction definition, or by the | |
7817 | operand list. */ | |
7818 | static int | |
17a2f251 | 7819 | validate_mips_insn (const struct mips_opcode *opc) |
252b5132 RH |
7820 | { |
7821 | const char *p = opc->args; | |
7822 | char c; | |
7823 | unsigned long used_bits = opc->mask; | |
7824 | ||
7825 | if ((used_bits & opc->match) != opc->match) | |
7826 | { | |
7827 | as_bad (_("internal: bad mips opcode (mask error): %s %s"), | |
7828 | opc->name, opc->args); | |
7829 | return 0; | |
7830 | } | |
7831 | #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift))) | |
7832 | while (*p) | |
7833 | switch (c = *p++) | |
7834 | { | |
7835 | case ',': break; | |
7836 | case '(': break; | |
7837 | case ')': break; | |
af7ee8bf CD |
7838 | case '+': |
7839 | switch (c = *p++) | |
7840 | { | |
7841 | case 'A': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; | |
7842 | case 'B': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break; | |
7843 | case 'C': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
bbcc0807 CD |
7844 | case 'D': USE_BITS (OP_MASK_RD, OP_SH_RD); |
7845 | USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; | |
5f74bc13 CD |
7846 | case 'E': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
7847 | case 'F': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break; | |
7848 | case 'G': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
7849 | case 'H': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
7850 | case 'I': break; | |
af7ee8bf CD |
7851 | default: |
7852 | as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"), | |
7853 | c, opc->name, opc->args); | |
7854 | return 0; | |
7855 | } | |
7856 | break; | |
252b5132 RH |
7857 | case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
7858 | case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; | |
7859 | case 'A': break; | |
4372b673 | 7860 | case 'B': USE_BITS (OP_MASK_CODE20, OP_SH_CODE20); break; |
252b5132 RH |
7861 | case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break; |
7862 | case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break; | |
7863 | case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
7864 | case 'F': break; | |
7865 | case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
156c2f8b | 7866 | case 'H': USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; |
252b5132 | 7867 | case 'I': break; |
e972090a | 7868 | case 'J': USE_BITS (OP_MASK_CODE19, OP_SH_CODE19); break; |
af7ee8bf | 7869 | case 'K': USE_BITS (OP_MASK_RD, OP_SH_RD); break; |
252b5132 RH |
7870 | case 'L': break; |
7871 | case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break; | |
7872 | case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break; | |
deec1734 CD |
7873 | case 'O': USE_BITS (OP_MASK_ALN, OP_SH_ALN); break; |
7874 | case 'Q': USE_BITS (OP_MASK_VSEL, OP_SH_VSEL); | |
7875 | USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
252b5132 RH |
7876 | case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break; |
7877 | case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
7878 | case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
7879 | case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
7880 | case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
deec1734 CD |
7881 | case 'X': USE_BITS (OP_MASK_FD, OP_SH_FD); break; |
7882 | case 'Y': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
7883 | case 'Z': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
252b5132 RH |
7884 | case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break; |
7885 | case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
7886 | case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break; | |
7887 | case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
7888 | case 'f': break; | |
7889 | case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break; | |
7890 | case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; | |
7891 | case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
7892 | case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break; | |
7893 | case 'l': break; | |
7894 | case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
7895 | case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
7896 | case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break; | |
7897 | case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
7898 | case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
7899 | case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
7900 | case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; | |
7901 | case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
7902 | case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
7903 | case 'x': break; | |
7904 | case 'z': break; | |
7905 | case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break; | |
4372b673 NC |
7906 | case 'U': USE_BITS (OP_MASK_RD, OP_SH_RD); |
7907 | USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
60b63b72 RS |
7908 | case 'e': USE_BITS (OP_MASK_VECBYTE, OP_SH_VECBYTE); break; |
7909 | case '%': USE_BITS (OP_MASK_VECALIGN, OP_SH_VECALIGN); break; | |
7910 | case '[': break; | |
7911 | case ']': break; | |
252b5132 RH |
7912 | default: |
7913 | as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"), | |
7914 | c, opc->name, opc->args); | |
7915 | return 0; | |
7916 | } | |
7917 | #undef USE_BITS | |
7918 | if (used_bits != 0xffffffff) | |
7919 | { | |
7920 | as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"), | |
7921 | ~used_bits & 0xffffffff, opc->name, opc->args); | |
7922 | return 0; | |
7923 | } | |
7924 | return 1; | |
7925 | } | |
7926 | ||
7927 | /* This routine assembles an instruction into its binary format. As a | |
7928 | side effect, it sets one of the global variables imm_reloc or | |
7929 | offset_reloc to the type of relocation to do if one of the operands | |
7930 | is an address expression. */ | |
7931 | ||
7932 | static void | |
17a2f251 | 7933 | mips_ip (char *str, struct mips_cl_insn *ip) |
252b5132 RH |
7934 | { |
7935 | char *s; | |
7936 | const char *args; | |
43841e91 | 7937 | char c = 0; |
252b5132 RH |
7938 | struct mips_opcode *insn; |
7939 | char *argsStart; | |
7940 | unsigned int regno; | |
7941 | unsigned int lastregno = 0; | |
af7ee8bf | 7942 | unsigned int lastpos = 0; |
071742cf | 7943 | unsigned int limlo, limhi; |
252b5132 RH |
7944 | char *s_reset; |
7945 | char save_c = 0; | |
252b5132 RH |
7946 | |
7947 | insn_error = NULL; | |
7948 | ||
7949 | /* If the instruction contains a '.', we first try to match an instruction | |
7950 | including the '.'. Then we try again without the '.'. */ | |
7951 | insn = NULL; | |
3882b010 | 7952 | for (s = str; *s != '\0' && !ISSPACE (*s); ++s) |
252b5132 RH |
7953 | continue; |
7954 | ||
7955 | /* If we stopped on whitespace, then replace the whitespace with null for | |
7956 | the call to hash_find. Save the character we replaced just in case we | |
7957 | have to re-parse the instruction. */ | |
3882b010 | 7958 | if (ISSPACE (*s)) |
252b5132 RH |
7959 | { |
7960 | save_c = *s; | |
7961 | *s++ = '\0'; | |
7962 | } | |
bdaaa2e1 | 7963 | |
252b5132 RH |
7964 | insn = (struct mips_opcode *) hash_find (op_hash, str); |
7965 | ||
7966 | /* If we didn't find the instruction in the opcode table, try again, but | |
7967 | this time with just the instruction up to, but not including the | |
7968 | first '.'. */ | |
7969 | if (insn == NULL) | |
7970 | { | |
bdaaa2e1 | 7971 | /* Restore the character we overwrite above (if any). */ |
252b5132 RH |
7972 | if (save_c) |
7973 | *(--s) = save_c; | |
7974 | ||
7975 | /* Scan up to the first '.' or whitespace. */ | |
3882b010 L |
7976 | for (s = str; |
7977 | *s != '\0' && *s != '.' && !ISSPACE (*s); | |
7978 | ++s) | |
252b5132 RH |
7979 | continue; |
7980 | ||
7981 | /* If we did not find a '.', then we can quit now. */ | |
7982 | if (*s != '.') | |
7983 | { | |
7984 | insn_error = "unrecognized opcode"; | |
7985 | return; | |
7986 | } | |
7987 | ||
7988 | /* Lookup the instruction in the hash table. */ | |
7989 | *s++ = '\0'; | |
7990 | if ((insn = (struct mips_opcode *) hash_find (op_hash, str)) == NULL) | |
7991 | { | |
7992 | insn_error = "unrecognized opcode"; | |
7993 | return; | |
7994 | } | |
252b5132 RH |
7995 | } |
7996 | ||
7997 | argsStart = s; | |
7998 | for (;;) | |
7999 | { | |
b34976b6 | 8000 | bfd_boolean ok; |
252b5132 RH |
8001 | |
8002 | assert (strcmp (insn->name, str) == 0); | |
8003 | ||
1f25f5d3 CD |
8004 | if (OPCODE_IS_MEMBER (insn, |
8005 | (mips_opts.isa | |
3396de36 | 8006 | | (file_ase_mips16 ? INSN_MIPS16 : 0) |
deec1734 | 8007 | | (mips_opts.ase_mdmx ? INSN_MDMX : 0) |
98d3f06f | 8008 | | (mips_opts.ase_mips3d ? INSN_MIPS3D : 0)), |
fef14a42 | 8009 | mips_opts.arch)) |
b34976b6 | 8010 | ok = TRUE; |
bdaaa2e1 | 8011 | else |
b34976b6 | 8012 | ok = FALSE; |
bdaaa2e1 | 8013 | |
252b5132 RH |
8014 | if (insn->pinfo != INSN_MACRO) |
8015 | { | |
fef14a42 | 8016 | if (mips_opts.arch == CPU_R4650 && (insn->pinfo & FP_D) != 0) |
b34976b6 | 8017 | ok = FALSE; |
252b5132 RH |
8018 | } |
8019 | ||
8020 | if (! ok) | |
8021 | { | |
8022 | if (insn + 1 < &mips_opcodes[NUMOPCODES] | |
8023 | && strcmp (insn->name, insn[1].name) == 0) | |
8024 | { | |
8025 | ++insn; | |
8026 | continue; | |
8027 | } | |
252b5132 | 8028 | else |
beae10d5 | 8029 | { |
268f6bed L |
8030 | if (!insn_error) |
8031 | { | |
8032 | static char buf[100]; | |
fef14a42 TS |
8033 | sprintf (buf, |
8034 | _("opcode not supported on this processor: %s (%s)"), | |
8035 | mips_cpu_info_from_arch (mips_opts.arch)->name, | |
8036 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
268f6bed L |
8037 | insn_error = buf; |
8038 | } | |
8039 | if (save_c) | |
8040 | *(--s) = save_c; | |
2bd7f1f3 | 8041 | return; |
252b5132 | 8042 | } |
252b5132 RH |
8043 | } |
8044 | ||
8045 | ip->insn_mo = insn; | |
8046 | ip->insn_opcode = insn->match; | |
268f6bed | 8047 | insn_error = NULL; |
252b5132 RH |
8048 | for (args = insn->args;; ++args) |
8049 | { | |
deec1734 CD |
8050 | int is_mdmx; |
8051 | ||
ad8d3bb3 | 8052 | s += strspn (s, " \t"); |
deec1734 | 8053 | is_mdmx = 0; |
252b5132 RH |
8054 | switch (*args) |
8055 | { | |
8056 | case '\0': /* end of args */ | |
8057 | if (*s == '\0') | |
8058 | return; | |
8059 | break; | |
8060 | ||
8061 | case ',': | |
8062 | if (*s++ == *args) | |
8063 | continue; | |
8064 | s--; | |
8065 | switch (*++args) | |
8066 | { | |
8067 | case 'r': | |
8068 | case 'v': | |
38487616 | 8069 | ip->insn_opcode |= lastregno << OP_SH_RS; |
252b5132 RH |
8070 | continue; |
8071 | ||
8072 | case 'w': | |
38487616 TS |
8073 | ip->insn_opcode |= lastregno << OP_SH_RT; |
8074 | continue; | |
8075 | ||
252b5132 | 8076 | case 'W': |
38487616 | 8077 | ip->insn_opcode |= lastregno << OP_SH_FT; |
252b5132 RH |
8078 | continue; |
8079 | ||
8080 | case 'V': | |
38487616 | 8081 | ip->insn_opcode |= lastregno << OP_SH_FS; |
252b5132 RH |
8082 | continue; |
8083 | } | |
8084 | break; | |
8085 | ||
8086 | case '(': | |
8087 | /* Handle optional base register. | |
8088 | Either the base register is omitted or | |
bdaaa2e1 | 8089 | we must have a left paren. */ |
252b5132 RH |
8090 | /* This is dependent on the next operand specifier |
8091 | is a base register specification. */ | |
8092 | assert (args[1] == 'b' || args[1] == '5' | |
8093 | || args[1] == '-' || args[1] == '4'); | |
8094 | if (*s == '\0') | |
8095 | return; | |
8096 | ||
8097 | case ')': /* these must match exactly */ | |
60b63b72 RS |
8098 | case '[': |
8099 | case ']': | |
252b5132 RH |
8100 | if (*s++ == *args) |
8101 | continue; | |
8102 | break; | |
8103 | ||
af7ee8bf CD |
8104 | case '+': /* Opcode extension character. */ |
8105 | switch (*++args) | |
8106 | { | |
071742cf CD |
8107 | case 'A': /* ins/ext position, becomes LSB. */ |
8108 | limlo = 0; | |
8109 | limhi = 31; | |
5f74bc13 CD |
8110 | goto do_lsb; |
8111 | case 'E': | |
8112 | limlo = 32; | |
8113 | limhi = 63; | |
8114 | goto do_lsb; | |
8115 | do_lsb: | |
071742cf CD |
8116 | my_getExpression (&imm_expr, s); |
8117 | check_absolute_expr (ip, &imm_expr); | |
8118 | if ((unsigned long) imm_expr.X_add_number < limlo | |
8119 | || (unsigned long) imm_expr.X_add_number > limhi) | |
8120 | { | |
8121 | as_bad (_("Improper position (%lu)"), | |
8122 | (unsigned long) imm_expr.X_add_number); | |
8123 | imm_expr.X_add_number = limlo; | |
8124 | } | |
8125 | lastpos = imm_expr.X_add_number; | |
8126 | ip->insn_opcode |= (imm_expr.X_add_number | |
8127 | & OP_MASK_SHAMT) << OP_SH_SHAMT; | |
8128 | imm_expr.X_op = O_absent; | |
8129 | s = expr_end; | |
8130 | continue; | |
8131 | ||
8132 | case 'B': /* ins size, becomes MSB. */ | |
8133 | limlo = 1; | |
8134 | limhi = 32; | |
5f74bc13 CD |
8135 | goto do_msb; |
8136 | case 'F': | |
8137 | limlo = 33; | |
8138 | limhi = 64; | |
8139 | goto do_msb; | |
8140 | do_msb: | |
071742cf CD |
8141 | my_getExpression (&imm_expr, s); |
8142 | check_absolute_expr (ip, &imm_expr); | |
8143 | /* Check for negative input so that small negative numbers | |
8144 | will not succeed incorrectly. The checks against | |
8145 | (pos+size) transitively check "size" itself, | |
8146 | assuming that "pos" is reasonable. */ | |
8147 | if ((long) imm_expr.X_add_number < 0 | |
8148 | || ((unsigned long) imm_expr.X_add_number | |
8149 | + lastpos) < limlo | |
8150 | || ((unsigned long) imm_expr.X_add_number | |
8151 | + lastpos) > limhi) | |
8152 | { | |
8153 | as_bad (_("Improper insert size (%lu, position %lu)"), | |
8154 | (unsigned long) imm_expr.X_add_number, | |
8155 | (unsigned long) lastpos); | |
8156 | imm_expr.X_add_number = limlo - lastpos; | |
8157 | } | |
8158 | ip->insn_opcode |= ((lastpos + imm_expr.X_add_number - 1) | |
8159 | & OP_MASK_INSMSB) << OP_SH_INSMSB; | |
8160 | imm_expr.X_op = O_absent; | |
8161 | s = expr_end; | |
8162 | continue; | |
8163 | ||
8164 | case 'C': /* ext size, becomes MSBD. */ | |
8165 | limlo = 1; | |
8166 | limhi = 32; | |
5f74bc13 CD |
8167 | goto do_msbd; |
8168 | case 'G': | |
8169 | limlo = 33; | |
8170 | limhi = 64; | |
8171 | goto do_msbd; | |
8172 | case 'H': | |
8173 | limlo = 33; | |
8174 | limhi = 64; | |
8175 | goto do_msbd; | |
8176 | do_msbd: | |
071742cf CD |
8177 | my_getExpression (&imm_expr, s); |
8178 | check_absolute_expr (ip, &imm_expr); | |
8179 | /* Check for negative input so that small negative numbers | |
8180 | will not succeed incorrectly. The checks against | |
8181 | (pos+size) transitively check "size" itself, | |
8182 | assuming that "pos" is reasonable. */ | |
8183 | if ((long) imm_expr.X_add_number < 0 | |
8184 | || ((unsigned long) imm_expr.X_add_number | |
8185 | + lastpos) < limlo | |
8186 | || ((unsigned long) imm_expr.X_add_number | |
8187 | + lastpos) > limhi) | |
8188 | { | |
8189 | as_bad (_("Improper extract size (%lu, position %lu)"), | |
8190 | (unsigned long) imm_expr.X_add_number, | |
8191 | (unsigned long) lastpos); | |
8192 | imm_expr.X_add_number = limlo - lastpos; | |
8193 | } | |
8194 | ip->insn_opcode |= ((imm_expr.X_add_number - 1) | |
8195 | & OP_MASK_EXTMSBD) << OP_SH_EXTMSBD; | |
8196 | imm_expr.X_op = O_absent; | |
8197 | s = expr_end; | |
8198 | continue; | |
af7ee8bf | 8199 | |
bbcc0807 CD |
8200 | case 'D': |
8201 | /* +D is for disassembly only; never match. */ | |
8202 | break; | |
8203 | ||
5f74bc13 CD |
8204 | case 'I': |
8205 | /* "+I" is like "I", except that imm2_expr is used. */ | |
8206 | my_getExpression (&imm2_expr, s); | |
8207 | if (imm2_expr.X_op != O_big | |
8208 | && imm2_expr.X_op != O_constant) | |
8209 | insn_error = _("absolute expression required"); | |
13757d0c | 8210 | normalize_constant_expr (&imm2_expr); |
5f74bc13 CD |
8211 | s = expr_end; |
8212 | continue; | |
8213 | ||
af7ee8bf CD |
8214 | default: |
8215 | as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"), | |
8216 | *args, insn->name, insn->args); | |
8217 | /* Further processing is fruitless. */ | |
8218 | return; | |
8219 | } | |
8220 | break; | |
8221 | ||
252b5132 RH |
8222 | case '<': /* must be at least one digit */ |
8223 | /* | |
8224 | * According to the manual, if the shift amount is greater | |
b6ff326e KH |
8225 | * than 31 or less than 0, then the shift amount should be |
8226 | * mod 32. In reality the mips assembler issues an error. | |
252b5132 RH |
8227 | * We issue a warning and mask out all but the low 5 bits. |
8228 | */ | |
8229 | my_getExpression (&imm_expr, s); | |
8230 | check_absolute_expr (ip, &imm_expr); | |
8231 | if ((unsigned long) imm_expr.X_add_number > 31) | |
8232 | { | |
793b27f4 TS |
8233 | as_warn (_("Improper shift amount (%lu)"), |
8234 | (unsigned long) imm_expr.X_add_number); | |
38487616 | 8235 | imm_expr.X_add_number &= OP_MASK_SHAMT; |
252b5132 | 8236 | } |
38487616 | 8237 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_SHAMT; |
252b5132 RH |
8238 | imm_expr.X_op = O_absent; |
8239 | s = expr_end; | |
8240 | continue; | |
8241 | ||
8242 | case '>': /* shift amount minus 32 */ | |
8243 | my_getExpression (&imm_expr, s); | |
8244 | check_absolute_expr (ip, &imm_expr); | |
8245 | if ((unsigned long) imm_expr.X_add_number < 32 | |
8246 | || (unsigned long) imm_expr.X_add_number > 63) | |
8247 | break; | |
38487616 | 8248 | ip->insn_opcode |= (imm_expr.X_add_number - 32) << OP_SH_SHAMT; |
252b5132 RH |
8249 | imm_expr.X_op = O_absent; |
8250 | s = expr_end; | |
8251 | continue; | |
8252 | ||
252b5132 RH |
8253 | case 'k': /* cache code */ |
8254 | case 'h': /* prefx code */ | |
8255 | my_getExpression (&imm_expr, s); | |
8256 | check_absolute_expr (ip, &imm_expr); | |
8257 | if ((unsigned long) imm_expr.X_add_number > 31) | |
8258 | { | |
8259 | as_warn (_("Invalid value for `%s' (%lu)"), | |
8260 | ip->insn_mo->name, | |
8261 | (unsigned long) imm_expr.X_add_number); | |
8262 | imm_expr.X_add_number &= 0x1f; | |
8263 | } | |
8264 | if (*args == 'k') | |
8265 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CACHE; | |
8266 | else | |
8267 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_PREFX; | |
8268 | imm_expr.X_op = O_absent; | |
8269 | s = expr_end; | |
8270 | continue; | |
8271 | ||
8272 | case 'c': /* break code */ | |
8273 | my_getExpression (&imm_expr, s); | |
8274 | check_absolute_expr (ip, &imm_expr); | |
793b27f4 | 8275 | if ((unsigned long) imm_expr.X_add_number > 1023) |
252b5132 | 8276 | { |
793b27f4 TS |
8277 | as_warn (_("Illegal break code (%lu)"), |
8278 | (unsigned long) imm_expr.X_add_number); | |
38487616 | 8279 | imm_expr.X_add_number &= OP_MASK_CODE; |
252b5132 | 8280 | } |
38487616 | 8281 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE; |
252b5132 RH |
8282 | imm_expr.X_op = O_absent; |
8283 | s = expr_end; | |
8284 | continue; | |
8285 | ||
8286 | case 'q': /* lower break code */ | |
8287 | my_getExpression (&imm_expr, s); | |
8288 | check_absolute_expr (ip, &imm_expr); | |
793b27f4 | 8289 | if ((unsigned long) imm_expr.X_add_number > 1023) |
252b5132 | 8290 | { |
793b27f4 TS |
8291 | as_warn (_("Illegal lower break code (%lu)"), |
8292 | (unsigned long) imm_expr.X_add_number); | |
38487616 | 8293 | imm_expr.X_add_number &= OP_MASK_CODE2; |
252b5132 | 8294 | } |
38487616 | 8295 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE2; |
252b5132 RH |
8296 | imm_expr.X_op = O_absent; |
8297 | s = expr_end; | |
8298 | continue; | |
8299 | ||
4372b673 | 8300 | case 'B': /* 20-bit syscall/break code. */ |
156c2f8b | 8301 | my_getExpression (&imm_expr, s); |
156c2f8b | 8302 | check_absolute_expr (ip, &imm_expr); |
793b27f4 TS |
8303 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE20) |
8304 | as_warn (_("Illegal 20-bit code (%lu)"), | |
8305 | (unsigned long) imm_expr.X_add_number); | |
38487616 | 8306 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE20; |
252b5132 RH |
8307 | imm_expr.X_op = O_absent; |
8308 | s = expr_end; | |
8309 | continue; | |
8310 | ||
98d3f06f | 8311 | case 'C': /* Coprocessor code */ |
beae10d5 | 8312 | my_getExpression (&imm_expr, s); |
252b5132 | 8313 | check_absolute_expr (ip, &imm_expr); |
98d3f06f | 8314 | if ((unsigned long) imm_expr.X_add_number >= (1 << 25)) |
252b5132 | 8315 | { |
793b27f4 TS |
8316 | as_warn (_("Coproccesor code > 25 bits (%lu)"), |
8317 | (unsigned long) imm_expr.X_add_number); | |
98d3f06f | 8318 | imm_expr.X_add_number &= ((1 << 25) - 1); |
252b5132 | 8319 | } |
beae10d5 KH |
8320 | ip->insn_opcode |= imm_expr.X_add_number; |
8321 | imm_expr.X_op = O_absent; | |
8322 | s = expr_end; | |
8323 | continue; | |
252b5132 | 8324 | |
4372b673 NC |
8325 | case 'J': /* 19-bit wait code. */ |
8326 | my_getExpression (&imm_expr, s); | |
8327 | check_absolute_expr (ip, &imm_expr); | |
793b27f4 TS |
8328 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE19) |
8329 | as_warn (_("Illegal 19-bit code (%lu)"), | |
8330 | (unsigned long) imm_expr.X_add_number); | |
38487616 | 8331 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE19; |
4372b673 NC |
8332 | imm_expr.X_op = O_absent; |
8333 | s = expr_end; | |
8334 | continue; | |
8335 | ||
252b5132 | 8336 | case 'P': /* Performance register */ |
beae10d5 | 8337 | my_getExpression (&imm_expr, s); |
252b5132 | 8338 | check_absolute_expr (ip, &imm_expr); |
beae10d5 | 8339 | if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1) |
252b5132 | 8340 | { |
793b27f4 TS |
8341 | as_warn (_("Invalid performance register (%lu)"), |
8342 | (unsigned long) imm_expr.X_add_number); | |
38487616 | 8343 | imm_expr.X_add_number &= OP_MASK_PERFREG; |
252b5132 | 8344 | } |
38487616 | 8345 | ip->insn_opcode |= (imm_expr.X_add_number << OP_SH_PERFREG); |
beae10d5 KH |
8346 | imm_expr.X_op = O_absent; |
8347 | s = expr_end; | |
8348 | continue; | |
252b5132 RH |
8349 | |
8350 | case 'b': /* base register */ | |
8351 | case 'd': /* destination register */ | |
8352 | case 's': /* source register */ | |
8353 | case 't': /* target register */ | |
8354 | case 'r': /* both target and source */ | |
8355 | case 'v': /* both dest and source */ | |
8356 | case 'w': /* both dest and target */ | |
8357 | case 'E': /* coprocessor target register */ | |
8358 | case 'G': /* coprocessor destination register */ | |
af7ee8bf | 8359 | case 'K': /* 'rdhwr' destination register */ |
252b5132 RH |
8360 | case 'x': /* ignore register name */ |
8361 | case 'z': /* must be zero register */ | |
4372b673 | 8362 | case 'U': /* destination register (clo/clz). */ |
252b5132 RH |
8363 | s_reset = s; |
8364 | if (s[0] == '$') | |
8365 | { | |
8366 | ||
3882b010 | 8367 | if (ISDIGIT (s[1])) |
252b5132 RH |
8368 | { |
8369 | ++s; | |
8370 | regno = 0; | |
8371 | do | |
8372 | { | |
8373 | regno *= 10; | |
8374 | regno += *s - '0'; | |
8375 | ++s; | |
8376 | } | |
3882b010 | 8377 | while (ISDIGIT (*s)); |
252b5132 RH |
8378 | if (regno > 31) |
8379 | as_bad (_("Invalid register number (%d)"), regno); | |
8380 | } | |
af7ee8bf | 8381 | else if (*args == 'E' || *args == 'G' || *args == 'K') |
252b5132 RH |
8382 | goto notreg; |
8383 | else | |
8384 | { | |
76db943d TS |
8385 | if (s[1] == 'r' && s[2] == 'a') |
8386 | { | |
8387 | s += 3; | |
8388 | regno = RA; | |
8389 | } | |
8390 | else if (s[1] == 'f' && s[2] == 'p') | |
252b5132 RH |
8391 | { |
8392 | s += 3; | |
8393 | regno = FP; | |
8394 | } | |
8395 | else if (s[1] == 's' && s[2] == 'p') | |
8396 | { | |
8397 | s += 3; | |
8398 | regno = SP; | |
8399 | } | |
8400 | else if (s[1] == 'g' && s[2] == 'p') | |
8401 | { | |
8402 | s += 3; | |
8403 | regno = GP; | |
8404 | } | |
8405 | else if (s[1] == 'a' && s[2] == 't') | |
8406 | { | |
8407 | s += 3; | |
8408 | regno = AT; | |
8409 | } | |
8410 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '0') | |
8411 | { | |
8412 | s += 4; | |
8413 | regno = KT0; | |
8414 | } | |
8415 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '1') | |
8416 | { | |
8417 | s += 4; | |
8418 | regno = KT1; | |
8419 | } | |
85b51719 TS |
8420 | else if (s[1] == 'z' && s[2] == 'e' && s[3] == 'r' && s[4] == 'o') |
8421 | { | |
8422 | s += 5; | |
8423 | regno = ZERO; | |
8424 | } | |
252b5132 RH |
8425 | else if (itbl_have_entries) |
8426 | { | |
8427 | char *p, *n; | |
d7ba4a77 | 8428 | unsigned long r; |
252b5132 | 8429 | |
d7ba4a77 | 8430 | p = s + 1; /* advance past '$' */ |
252b5132 RH |
8431 | n = itbl_get_field (&p); /* n is name */ |
8432 | ||
d7ba4a77 ILT |
8433 | /* See if this is a register defined in an |
8434 | itbl entry. */ | |
8435 | if (itbl_get_reg_val (n, &r)) | |
252b5132 RH |
8436 | { |
8437 | /* Get_field advances to the start of | |
8438 | the next field, so we need to back | |
d7ba4a77 | 8439 | rack to the end of the last field. */ |
bdaaa2e1 | 8440 | if (p) |
252b5132 | 8441 | s = p - 1; |
bdaaa2e1 | 8442 | else |
d7ba4a77 | 8443 | s = strchr (s, '\0'); |
252b5132 RH |
8444 | regno = r; |
8445 | } | |
8446 | else | |
8447 | goto notreg; | |
beae10d5 | 8448 | } |
252b5132 RH |
8449 | else |
8450 | goto notreg; | |
8451 | } | |
8452 | if (regno == AT | |
8453 | && ! mips_opts.noat | |
8454 | && *args != 'E' | |
af7ee8bf CD |
8455 | && *args != 'G' |
8456 | && *args != 'K') | |
252b5132 RH |
8457 | as_warn (_("Used $at without \".set noat\"")); |
8458 | c = *args; | |
8459 | if (*s == ' ') | |
f9419b05 | 8460 | ++s; |
252b5132 RH |
8461 | if (args[1] != *s) |
8462 | { | |
8463 | if (c == 'r' || c == 'v' || c == 'w') | |
8464 | { | |
8465 | regno = lastregno; | |
8466 | s = s_reset; | |
f9419b05 | 8467 | ++args; |
252b5132 RH |
8468 | } |
8469 | } | |
8470 | /* 'z' only matches $0. */ | |
8471 | if (c == 'z' && regno != 0) | |
8472 | break; | |
8473 | ||
bdaaa2e1 KH |
8474 | /* Now that we have assembled one operand, we use the args string |
8475 | * to figure out where it goes in the instruction. */ | |
252b5132 RH |
8476 | switch (c) |
8477 | { | |
8478 | case 'r': | |
8479 | case 's': | |
8480 | case 'v': | |
8481 | case 'b': | |
38487616 | 8482 | ip->insn_opcode |= regno << OP_SH_RS; |
252b5132 RH |
8483 | break; |
8484 | case 'd': | |
8485 | case 'G': | |
af7ee8bf | 8486 | case 'K': |
38487616 | 8487 | ip->insn_opcode |= regno << OP_SH_RD; |
252b5132 | 8488 | break; |
4372b673 | 8489 | case 'U': |
38487616 TS |
8490 | ip->insn_opcode |= regno << OP_SH_RD; |
8491 | ip->insn_opcode |= regno << OP_SH_RT; | |
4372b673 | 8492 | break; |
252b5132 RH |
8493 | case 'w': |
8494 | case 't': | |
8495 | case 'E': | |
38487616 | 8496 | ip->insn_opcode |= regno << OP_SH_RT; |
252b5132 RH |
8497 | break; |
8498 | case 'x': | |
8499 | /* This case exists because on the r3000 trunc | |
8500 | expands into a macro which requires a gp | |
8501 | register. On the r6000 or r4000 it is | |
8502 | assembled into a single instruction which | |
8503 | ignores the register. Thus the insn version | |
8504 | is MIPS_ISA2 and uses 'x', and the macro | |
8505 | version is MIPS_ISA1 and uses 't'. */ | |
8506 | break; | |
8507 | case 'z': | |
8508 | /* This case is for the div instruction, which | |
8509 | acts differently if the destination argument | |
8510 | is $0. This only matches $0, and is checked | |
8511 | outside the switch. */ | |
8512 | break; | |
8513 | case 'D': | |
8514 | /* Itbl operand; not yet implemented. FIXME ?? */ | |
8515 | break; | |
8516 | /* What about all other operands like 'i', which | |
8517 | can be specified in the opcode table? */ | |
8518 | } | |
8519 | lastregno = regno; | |
8520 | continue; | |
8521 | } | |
8522 | notreg: | |
8523 | switch (*args++) | |
8524 | { | |
8525 | case 'r': | |
8526 | case 'v': | |
38487616 | 8527 | ip->insn_opcode |= lastregno << OP_SH_RS; |
252b5132 RH |
8528 | continue; |
8529 | case 'w': | |
38487616 | 8530 | ip->insn_opcode |= lastregno << OP_SH_RT; |
252b5132 RH |
8531 | continue; |
8532 | } | |
8533 | break; | |
8534 | ||
deec1734 CD |
8535 | case 'O': /* MDMX alignment immediate constant. */ |
8536 | my_getExpression (&imm_expr, s); | |
8537 | check_absolute_expr (ip, &imm_expr); | |
8538 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_ALN) | |
8539 | { | |
8540 | as_warn ("Improper align amount (%ld), using low bits", | |
8541 | (long) imm_expr.X_add_number); | |
8542 | imm_expr.X_add_number &= OP_MASK_ALN; | |
8543 | } | |
8544 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_ALN; | |
8545 | imm_expr.X_op = O_absent; | |
8546 | s = expr_end; | |
8547 | continue; | |
8548 | ||
8549 | case 'Q': /* MDMX vector, element sel, or const. */ | |
8550 | if (s[0] != '$') | |
8551 | { | |
8552 | /* MDMX Immediate. */ | |
8553 | my_getExpression (&imm_expr, s); | |
8554 | check_absolute_expr (ip, &imm_expr); | |
8555 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_FT) | |
8556 | { | |
8557 | as_warn (_("Invalid MDMX Immediate (%ld)"), | |
8558 | (long) imm_expr.X_add_number); | |
8559 | imm_expr.X_add_number &= OP_MASK_FT; | |
8560 | } | |
8561 | imm_expr.X_add_number &= OP_MASK_FT; | |
8562 | if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL)) | |
8563 | ip->insn_opcode |= MDMX_FMTSEL_IMM_QH << OP_SH_VSEL; | |
8564 | else | |
8565 | ip->insn_opcode |= MDMX_FMTSEL_IMM_OB << OP_SH_VSEL; | |
8566 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_FT; | |
8567 | imm_expr.X_op = O_absent; | |
8568 | s = expr_end; | |
8569 | continue; | |
8570 | } | |
8571 | /* Not MDMX Immediate. Fall through. */ | |
8572 | case 'X': /* MDMX destination register. */ | |
8573 | case 'Y': /* MDMX source register. */ | |
8574 | case 'Z': /* MDMX target register. */ | |
8575 | is_mdmx = 1; | |
252b5132 RH |
8576 | case 'D': /* floating point destination register */ |
8577 | case 'S': /* floating point source register */ | |
8578 | case 'T': /* floating point target register */ | |
8579 | case 'R': /* floating point source register */ | |
8580 | case 'V': | |
8581 | case 'W': | |
8582 | s_reset = s; | |
deec1734 CD |
8583 | /* Accept $fN for FP and MDMX register numbers, and in |
8584 | addition accept $vN for MDMX register numbers. */ | |
8585 | if ((s[0] == '$' && s[1] == 'f' && ISDIGIT (s[2])) | |
8586 | || (is_mdmx != 0 && s[0] == '$' && s[1] == 'v' | |
8587 | && ISDIGIT (s[2]))) | |
252b5132 RH |
8588 | { |
8589 | s += 2; | |
8590 | regno = 0; | |
8591 | do | |
8592 | { | |
8593 | regno *= 10; | |
8594 | regno += *s - '0'; | |
8595 | ++s; | |
8596 | } | |
3882b010 | 8597 | while (ISDIGIT (*s)); |
252b5132 RH |
8598 | |
8599 | if (regno > 31) | |
8600 | as_bad (_("Invalid float register number (%d)"), regno); | |
8601 | ||
8602 | if ((regno & 1) != 0 | |
ca4e0257 | 8603 | && HAVE_32BIT_FPRS |
252b5132 RH |
8604 | && ! (strcmp (str, "mtc1") == 0 |
8605 | || strcmp (str, "mfc1") == 0 | |
8606 | || strcmp (str, "lwc1") == 0 | |
8607 | || strcmp (str, "swc1") == 0 | |
8608 | || strcmp (str, "l.s") == 0 | |
8609 | || strcmp (str, "s.s") == 0)) | |
8610 | as_warn (_("Float register should be even, was %d"), | |
8611 | regno); | |
8612 | ||
8613 | c = *args; | |
8614 | if (*s == ' ') | |
f9419b05 | 8615 | ++s; |
252b5132 RH |
8616 | if (args[1] != *s) |
8617 | { | |
8618 | if (c == 'V' || c == 'W') | |
8619 | { | |
8620 | regno = lastregno; | |
8621 | s = s_reset; | |
f9419b05 | 8622 | ++args; |
252b5132 RH |
8623 | } |
8624 | } | |
8625 | switch (c) | |
8626 | { | |
8627 | case 'D': | |
deec1734 | 8628 | case 'X': |
38487616 | 8629 | ip->insn_opcode |= regno << OP_SH_FD; |
252b5132 RH |
8630 | break; |
8631 | case 'V': | |
8632 | case 'S': | |
deec1734 | 8633 | case 'Y': |
38487616 | 8634 | ip->insn_opcode |= regno << OP_SH_FS; |
252b5132 | 8635 | break; |
deec1734 CD |
8636 | case 'Q': |
8637 | /* This is like 'Z', but also needs to fix the MDMX | |
8638 | vector/scalar select bits. Note that the | |
8639 | scalar immediate case is handled above. */ | |
8640 | if (*s == '[') | |
8641 | { | |
8642 | int is_qh = (ip->insn_opcode & (1 << OP_SH_VSEL)); | |
8643 | int max_el = (is_qh ? 3 : 7); | |
8644 | s++; | |
8645 | my_getExpression(&imm_expr, s); | |
8646 | check_absolute_expr (ip, &imm_expr); | |
8647 | s = expr_end; | |
8648 | if (imm_expr.X_add_number > max_el) | |
8649 | as_bad(_("Bad element selector %ld"), | |
8650 | (long) imm_expr.X_add_number); | |
8651 | imm_expr.X_add_number &= max_el; | |
8652 | ip->insn_opcode |= (imm_expr.X_add_number | |
8653 | << (OP_SH_VSEL + | |
8654 | (is_qh ? 2 : 1))); | |
01a3f561 | 8655 | imm_expr.X_op = O_absent; |
deec1734 CD |
8656 | if (*s != ']') |
8657 | as_warn(_("Expecting ']' found '%s'"), s); | |
8658 | else | |
8659 | s++; | |
8660 | } | |
8661 | else | |
8662 | { | |
8663 | if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL)) | |
8664 | ip->insn_opcode |= (MDMX_FMTSEL_VEC_QH | |
8665 | << OP_SH_VSEL); | |
8666 | else | |
8667 | ip->insn_opcode |= (MDMX_FMTSEL_VEC_OB << | |
8668 | OP_SH_VSEL); | |
8669 | } | |
8670 | /* Fall through */ | |
252b5132 RH |
8671 | case 'W': |
8672 | case 'T': | |
deec1734 | 8673 | case 'Z': |
38487616 | 8674 | ip->insn_opcode |= regno << OP_SH_FT; |
252b5132 RH |
8675 | break; |
8676 | case 'R': | |
38487616 | 8677 | ip->insn_opcode |= regno << OP_SH_FR; |
252b5132 RH |
8678 | break; |
8679 | } | |
8680 | lastregno = regno; | |
8681 | continue; | |
8682 | } | |
8683 | ||
252b5132 RH |
8684 | switch (*args++) |
8685 | { | |
8686 | case 'V': | |
38487616 | 8687 | ip->insn_opcode |= lastregno << OP_SH_FS; |
252b5132 RH |
8688 | continue; |
8689 | case 'W': | |
38487616 | 8690 | ip->insn_opcode |= lastregno << OP_SH_FT; |
252b5132 RH |
8691 | continue; |
8692 | } | |
8693 | break; | |
8694 | ||
8695 | case 'I': | |
8696 | my_getExpression (&imm_expr, s); | |
8697 | if (imm_expr.X_op != O_big | |
8698 | && imm_expr.X_op != O_constant) | |
8699 | insn_error = _("absolute expression required"); | |
13757d0c | 8700 | normalize_constant_expr (&imm_expr); |
252b5132 RH |
8701 | s = expr_end; |
8702 | continue; | |
8703 | ||
8704 | case 'A': | |
8705 | my_getExpression (&offset_expr, s); | |
f6688943 | 8706 | *imm_reloc = BFD_RELOC_32; |
252b5132 RH |
8707 | s = expr_end; |
8708 | continue; | |
8709 | ||
8710 | case 'F': | |
8711 | case 'L': | |
8712 | case 'f': | |
8713 | case 'l': | |
8714 | { | |
8715 | int f64; | |
ca4e0257 | 8716 | int using_gprs; |
252b5132 RH |
8717 | char *save_in; |
8718 | char *err; | |
8719 | unsigned char temp[8]; | |
8720 | int len; | |
8721 | unsigned int length; | |
8722 | segT seg; | |
8723 | subsegT subseg; | |
8724 | char *p; | |
8725 | ||
8726 | /* These only appear as the last operand in an | |
8727 | instruction, and every instruction that accepts | |
8728 | them in any variant accepts them in all variants. | |
8729 | This means we don't have to worry about backing out | |
8730 | any changes if the instruction does not match. | |
8731 | ||
8732 | The difference between them is the size of the | |
8733 | floating point constant and where it goes. For 'F' | |
8734 | and 'L' the constant is 64 bits; for 'f' and 'l' it | |
8735 | is 32 bits. Where the constant is placed is based | |
8736 | on how the MIPS assembler does things: | |
8737 | F -- .rdata | |
8738 | L -- .lit8 | |
8739 | f -- immediate value | |
8740 | l -- .lit4 | |
8741 | ||
8742 | The .lit4 and .lit8 sections are only used if | |
8743 | permitted by the -G argument. | |
8744 | ||
ca4e0257 RS |
8745 | The code below needs to know whether the target register |
8746 | is 32 or 64 bits wide. It relies on the fact 'f' and | |
8747 | 'F' are used with GPR-based instructions and 'l' and | |
8748 | 'L' are used with FPR-based instructions. */ | |
252b5132 RH |
8749 | |
8750 | f64 = *args == 'F' || *args == 'L'; | |
ca4e0257 | 8751 | using_gprs = *args == 'F' || *args == 'f'; |
252b5132 RH |
8752 | |
8753 | save_in = input_line_pointer; | |
8754 | input_line_pointer = s; | |
8755 | err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len); | |
8756 | length = len; | |
8757 | s = input_line_pointer; | |
8758 | input_line_pointer = save_in; | |
8759 | if (err != NULL && *err != '\0') | |
8760 | { | |
8761 | as_bad (_("Bad floating point constant: %s"), err); | |
8762 | memset (temp, '\0', sizeof temp); | |
8763 | length = f64 ? 8 : 4; | |
8764 | } | |
8765 | ||
156c2f8b | 8766 | assert (length == (unsigned) (f64 ? 8 : 4)); |
252b5132 RH |
8767 | |
8768 | if (*args == 'f' | |
8769 | || (*args == 'l' | |
3e722fb5 | 8770 | && (g_switch_value < 4 |
252b5132 RH |
8771 | || (temp[0] == 0 && temp[1] == 0) |
8772 | || (temp[2] == 0 && temp[3] == 0)))) | |
8773 | { | |
8774 | imm_expr.X_op = O_constant; | |
8775 | if (! target_big_endian) | |
8776 | imm_expr.X_add_number = bfd_getl32 (temp); | |
8777 | else | |
8778 | imm_expr.X_add_number = bfd_getb32 (temp); | |
8779 | } | |
8780 | else if (length > 4 | |
119d663a | 8781 | && ! mips_disable_float_construction |
ca4e0257 RS |
8782 | /* Constants can only be constructed in GPRs and |
8783 | copied to FPRs if the GPRs are at least as wide | |
8784 | as the FPRs. Force the constant into memory if | |
8785 | we are using 64-bit FPRs but the GPRs are only | |
8786 | 32 bits wide. */ | |
8787 | && (using_gprs | |
8788 | || ! (HAVE_64BIT_FPRS && HAVE_32BIT_GPRS)) | |
252b5132 RH |
8789 | && ((temp[0] == 0 && temp[1] == 0) |
8790 | || (temp[2] == 0 && temp[3] == 0)) | |
8791 | && ((temp[4] == 0 && temp[5] == 0) | |
8792 | || (temp[6] == 0 && temp[7] == 0))) | |
8793 | { | |
ca4e0257 RS |
8794 | /* The value is simple enough to load with a couple of |
8795 | instructions. If using 32-bit registers, set | |
8796 | imm_expr to the high order 32 bits and offset_expr to | |
8797 | the low order 32 bits. Otherwise, set imm_expr to | |
8798 | the entire 64 bit constant. */ | |
8799 | if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS) | |
252b5132 RH |
8800 | { |
8801 | imm_expr.X_op = O_constant; | |
8802 | offset_expr.X_op = O_constant; | |
8803 | if (! target_big_endian) | |
8804 | { | |
8805 | imm_expr.X_add_number = bfd_getl32 (temp + 4); | |
8806 | offset_expr.X_add_number = bfd_getl32 (temp); | |
8807 | } | |
8808 | else | |
8809 | { | |
8810 | imm_expr.X_add_number = bfd_getb32 (temp); | |
8811 | offset_expr.X_add_number = bfd_getb32 (temp + 4); | |
8812 | } | |
8813 | if (offset_expr.X_add_number == 0) | |
8814 | offset_expr.X_op = O_absent; | |
8815 | } | |
8816 | else if (sizeof (imm_expr.X_add_number) > 4) | |
8817 | { | |
8818 | imm_expr.X_op = O_constant; | |
8819 | if (! target_big_endian) | |
8820 | imm_expr.X_add_number = bfd_getl64 (temp); | |
8821 | else | |
8822 | imm_expr.X_add_number = bfd_getb64 (temp); | |
8823 | } | |
8824 | else | |
8825 | { | |
8826 | imm_expr.X_op = O_big; | |
8827 | imm_expr.X_add_number = 4; | |
8828 | if (! target_big_endian) | |
8829 | { | |
8830 | generic_bignum[0] = bfd_getl16 (temp); | |
8831 | generic_bignum[1] = bfd_getl16 (temp + 2); | |
8832 | generic_bignum[2] = bfd_getl16 (temp + 4); | |
8833 | generic_bignum[3] = bfd_getl16 (temp + 6); | |
8834 | } | |
8835 | else | |
8836 | { | |
8837 | generic_bignum[0] = bfd_getb16 (temp + 6); | |
8838 | generic_bignum[1] = bfd_getb16 (temp + 4); | |
8839 | generic_bignum[2] = bfd_getb16 (temp + 2); | |
8840 | generic_bignum[3] = bfd_getb16 (temp); | |
8841 | } | |
8842 | } | |
8843 | } | |
8844 | else | |
8845 | { | |
8846 | const char *newname; | |
8847 | segT new_seg; | |
8848 | ||
8849 | /* Switch to the right section. */ | |
8850 | seg = now_seg; | |
8851 | subseg = now_subseg; | |
8852 | switch (*args) | |
8853 | { | |
8854 | default: /* unused default case avoids warnings. */ | |
8855 | case 'L': | |
8856 | newname = RDATA_SECTION_NAME; | |
3e722fb5 | 8857 | if (g_switch_value >= 8) |
252b5132 RH |
8858 | newname = ".lit8"; |
8859 | break; | |
8860 | case 'F': | |
3e722fb5 | 8861 | newname = RDATA_SECTION_NAME; |
252b5132 RH |
8862 | break; |
8863 | case 'l': | |
4d0d148d | 8864 | assert (g_switch_value >= 4); |
252b5132 RH |
8865 | newname = ".lit4"; |
8866 | break; | |
8867 | } | |
8868 | new_seg = subseg_new (newname, (subsegT) 0); | |
8869 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
8870 | bfd_set_section_flags (stdoutput, new_seg, | |
8871 | (SEC_ALLOC | |
8872 | | SEC_LOAD | |
8873 | | SEC_READONLY | |
8874 | | SEC_DATA)); | |
8875 | frag_align (*args == 'l' ? 2 : 3, 0, 0); | |
8876 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour | |
8877 | && strcmp (TARGET_OS, "elf") != 0) | |
8878 | record_alignment (new_seg, 4); | |
8879 | else | |
8880 | record_alignment (new_seg, *args == 'l' ? 2 : 3); | |
8881 | if (seg == now_seg) | |
8882 | as_bad (_("Can't use floating point insn in this section")); | |
8883 | ||
8884 | /* Set the argument to the current address in the | |
8885 | section. */ | |
8886 | offset_expr.X_op = O_symbol; | |
8887 | offset_expr.X_add_symbol = | |
8888 | symbol_new ("L0\001", now_seg, | |
8889 | (valueT) frag_now_fix (), frag_now); | |
8890 | offset_expr.X_add_number = 0; | |
8891 | ||
8892 | /* Put the floating point number into the section. */ | |
8893 | p = frag_more ((int) length); | |
8894 | memcpy (p, temp, length); | |
8895 | ||
8896 | /* Switch back to the original section. */ | |
8897 | subseg_set (seg, subseg); | |
8898 | } | |
8899 | } | |
8900 | continue; | |
8901 | ||
8902 | case 'i': /* 16 bit unsigned immediate */ | |
8903 | case 'j': /* 16 bit signed immediate */ | |
f6688943 | 8904 | *imm_reloc = BFD_RELOC_LO16; |
5e0116d5 | 8905 | if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0) |
252b5132 RH |
8906 | { |
8907 | int more; | |
5e0116d5 RS |
8908 | offsetT minval, maxval; |
8909 | ||
8910 | more = (insn + 1 < &mips_opcodes[NUMOPCODES] | |
8911 | && strcmp (insn->name, insn[1].name) == 0); | |
8912 | ||
8913 | /* If the expression was written as an unsigned number, | |
8914 | only treat it as signed if there are no more | |
8915 | alternatives. */ | |
8916 | if (more | |
8917 | && *args == 'j' | |
8918 | && sizeof (imm_expr.X_add_number) <= 4 | |
8919 | && imm_expr.X_op == O_constant | |
8920 | && imm_expr.X_add_number < 0 | |
8921 | && imm_expr.X_unsigned | |
8922 | && HAVE_64BIT_GPRS) | |
8923 | break; | |
8924 | ||
8925 | /* For compatibility with older assemblers, we accept | |
8926 | 0x8000-0xffff as signed 16-bit numbers when only | |
8927 | signed numbers are allowed. */ | |
8928 | if (*args == 'i') | |
8929 | minval = 0, maxval = 0xffff; | |
8930 | else if (more) | |
8931 | minval = -0x8000, maxval = 0x7fff; | |
252b5132 | 8932 | else |
5e0116d5 RS |
8933 | minval = -0x8000, maxval = 0xffff; |
8934 | ||
8935 | if (imm_expr.X_op != O_constant | |
8936 | || imm_expr.X_add_number < minval | |
8937 | || imm_expr.X_add_number > maxval) | |
252b5132 RH |
8938 | { |
8939 | if (more) | |
8940 | break; | |
2ae7e77b AH |
8941 | if (imm_expr.X_op == O_constant |
8942 | || imm_expr.X_op == O_big) | |
5e0116d5 | 8943 | as_bad (_("expression out of range")); |
252b5132 RH |
8944 | } |
8945 | } | |
8946 | s = expr_end; | |
8947 | continue; | |
8948 | ||
8949 | case 'o': /* 16 bit offset */ | |
5e0116d5 RS |
8950 | /* Check whether there is only a single bracketed expression |
8951 | left. If so, it must be the base register and the | |
8952 | constant must be zero. */ | |
8953 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
8954 | { | |
8955 | offset_expr.X_op = O_constant; | |
8956 | offset_expr.X_add_number = 0; | |
8957 | continue; | |
8958 | } | |
252b5132 RH |
8959 | |
8960 | /* If this value won't fit into a 16 bit offset, then go | |
8961 | find a macro that will generate the 32 bit offset | |
afdbd6d0 | 8962 | code pattern. */ |
5e0116d5 | 8963 | if (my_getSmallExpression (&offset_expr, offset_reloc, s) == 0 |
252b5132 RH |
8964 | && (offset_expr.X_op != O_constant |
8965 | || offset_expr.X_add_number >= 0x8000 | |
afdbd6d0 | 8966 | || offset_expr.X_add_number < -0x8000)) |
252b5132 RH |
8967 | break; |
8968 | ||
252b5132 RH |
8969 | s = expr_end; |
8970 | continue; | |
8971 | ||
8972 | case 'p': /* pc relative offset */ | |
0b25d3e6 | 8973 | *offset_reloc = BFD_RELOC_16_PCREL_S2; |
252b5132 RH |
8974 | my_getExpression (&offset_expr, s); |
8975 | s = expr_end; | |
8976 | continue; | |
8977 | ||
8978 | case 'u': /* upper 16 bits */ | |
5e0116d5 RS |
8979 | if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0 |
8980 | && imm_expr.X_op == O_constant | |
8981 | && (imm_expr.X_add_number < 0 | |
8982 | || imm_expr.X_add_number >= 0x10000)) | |
252b5132 RH |
8983 | as_bad (_("lui expression not in range 0..65535")); |
8984 | s = expr_end; | |
8985 | continue; | |
8986 | ||
8987 | case 'a': /* 26 bit address */ | |
8988 | my_getExpression (&offset_expr, s); | |
8989 | s = expr_end; | |
f6688943 | 8990 | *offset_reloc = BFD_RELOC_MIPS_JMP; |
252b5132 RH |
8991 | continue; |
8992 | ||
8993 | case 'N': /* 3 bit branch condition code */ | |
8994 | case 'M': /* 3 bit compare condition code */ | |
8995 | if (strncmp (s, "$fcc", 4) != 0) | |
8996 | break; | |
8997 | s += 4; | |
8998 | regno = 0; | |
8999 | do | |
9000 | { | |
9001 | regno *= 10; | |
9002 | regno += *s - '0'; | |
9003 | ++s; | |
9004 | } | |
3882b010 | 9005 | while (ISDIGIT (*s)); |
252b5132 | 9006 | if (regno > 7) |
30c378fd CD |
9007 | as_bad (_("Invalid condition code register $fcc%d"), regno); |
9008 | if ((strcmp(str + strlen(str) - 3, ".ps") == 0 | |
9009 | || strcmp(str + strlen(str) - 5, "any2f") == 0 | |
9010 | || strcmp(str + strlen(str) - 5, "any2t") == 0) | |
9011 | && (regno & 1) != 0) | |
9012 | as_warn(_("Condition code register should be even for %s, was %d"), | |
9013 | str, regno); | |
9014 | if ((strcmp(str + strlen(str) - 5, "any4f") == 0 | |
9015 | || strcmp(str + strlen(str) - 5, "any4t") == 0) | |
9016 | && (regno & 3) != 0) | |
9017 | as_warn(_("Condition code register should be 0 or 4 for %s, was %d"), | |
9018 | str, regno); | |
252b5132 RH |
9019 | if (*args == 'N') |
9020 | ip->insn_opcode |= regno << OP_SH_BCC; | |
9021 | else | |
9022 | ip->insn_opcode |= regno << OP_SH_CCC; | |
beae10d5 | 9023 | continue; |
252b5132 | 9024 | |
156c2f8b NC |
9025 | case 'H': |
9026 | if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X')) | |
9027 | s += 2; | |
3882b010 | 9028 | if (ISDIGIT (*s)) |
156c2f8b NC |
9029 | { |
9030 | c = 0; | |
9031 | do | |
9032 | { | |
9033 | c *= 10; | |
9034 | c += *s - '0'; | |
9035 | ++s; | |
9036 | } | |
3882b010 | 9037 | while (ISDIGIT (*s)); |
156c2f8b NC |
9038 | } |
9039 | else | |
9040 | c = 8; /* Invalid sel value. */ | |
9041 | ||
9042 | if (c > 7) | |
9043 | as_bad (_("invalid coprocessor sub-selection value (0-7)")); | |
9044 | ip->insn_opcode |= c; | |
9045 | continue; | |
9046 | ||
60b63b72 RS |
9047 | case 'e': |
9048 | /* Must be at least one digit. */ | |
9049 | my_getExpression (&imm_expr, s); | |
9050 | check_absolute_expr (ip, &imm_expr); | |
9051 | ||
9052 | if ((unsigned long) imm_expr.X_add_number | |
9053 | > (unsigned long) OP_MASK_VECBYTE) | |
9054 | { | |
9055 | as_bad (_("bad byte vector index (%ld)"), | |
9056 | (long) imm_expr.X_add_number); | |
9057 | imm_expr.X_add_number = 0; | |
9058 | } | |
9059 | ||
9060 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_VECBYTE; | |
9061 | imm_expr.X_op = O_absent; | |
9062 | s = expr_end; | |
9063 | continue; | |
9064 | ||
9065 | case '%': | |
9066 | my_getExpression (&imm_expr, s); | |
9067 | check_absolute_expr (ip, &imm_expr); | |
9068 | ||
9069 | if ((unsigned long) imm_expr.X_add_number | |
9070 | > (unsigned long) OP_MASK_VECALIGN) | |
9071 | { | |
9072 | as_bad (_("bad byte vector index (%ld)"), | |
9073 | (long) imm_expr.X_add_number); | |
9074 | imm_expr.X_add_number = 0; | |
9075 | } | |
9076 | ||
9077 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_VECALIGN; | |
9078 | imm_expr.X_op = O_absent; | |
9079 | s = expr_end; | |
9080 | continue; | |
9081 | ||
252b5132 RH |
9082 | default: |
9083 | as_bad (_("bad char = '%c'\n"), *args); | |
9084 | internalError (); | |
9085 | } | |
9086 | break; | |
9087 | } | |
9088 | /* Args don't match. */ | |
9089 | if (insn + 1 < &mips_opcodes[NUMOPCODES] && | |
9090 | !strcmp (insn->name, insn[1].name)) | |
9091 | { | |
9092 | ++insn; | |
9093 | s = argsStart; | |
268f6bed | 9094 | insn_error = _("illegal operands"); |
252b5132 RH |
9095 | continue; |
9096 | } | |
268f6bed L |
9097 | if (save_c) |
9098 | *(--s) = save_c; | |
252b5132 RH |
9099 | insn_error = _("illegal operands"); |
9100 | return; | |
9101 | } | |
9102 | } | |
9103 | ||
9104 | /* This routine assembles an instruction into its binary format when | |
9105 | assembling for the mips16. As a side effect, it sets one of the | |
9106 | global variables imm_reloc or offset_reloc to the type of | |
9107 | relocation to do if one of the operands is an address expression. | |
9108 | It also sets mips16_small and mips16_ext if the user explicitly | |
9109 | requested a small or extended instruction. */ | |
9110 | ||
9111 | static void | |
17a2f251 | 9112 | mips16_ip (char *str, struct mips_cl_insn *ip) |
252b5132 RH |
9113 | { |
9114 | char *s; | |
9115 | const char *args; | |
9116 | struct mips_opcode *insn; | |
9117 | char *argsstart; | |
9118 | unsigned int regno; | |
9119 | unsigned int lastregno = 0; | |
9120 | char *s_reset; | |
d6f16593 | 9121 | size_t i; |
252b5132 RH |
9122 | |
9123 | insn_error = NULL; | |
9124 | ||
b34976b6 AM |
9125 | mips16_small = FALSE; |
9126 | mips16_ext = FALSE; | |
252b5132 | 9127 | |
3882b010 | 9128 | for (s = str; ISLOWER (*s); ++s) |
252b5132 RH |
9129 | ; |
9130 | switch (*s) | |
9131 | { | |
9132 | case '\0': | |
9133 | break; | |
9134 | ||
9135 | case ' ': | |
9136 | *s++ = '\0'; | |
9137 | break; | |
9138 | ||
9139 | case '.': | |
9140 | if (s[1] == 't' && s[2] == ' ') | |
9141 | { | |
9142 | *s = '\0'; | |
b34976b6 | 9143 | mips16_small = TRUE; |
252b5132 RH |
9144 | s += 3; |
9145 | break; | |
9146 | } | |
9147 | else if (s[1] == 'e' && s[2] == ' ') | |
9148 | { | |
9149 | *s = '\0'; | |
b34976b6 | 9150 | mips16_ext = TRUE; |
252b5132 RH |
9151 | s += 3; |
9152 | break; | |
9153 | } | |
9154 | /* Fall through. */ | |
9155 | default: | |
9156 | insn_error = _("unknown opcode"); | |
9157 | return; | |
9158 | } | |
9159 | ||
9160 | if (mips_opts.noautoextend && ! mips16_ext) | |
b34976b6 | 9161 | mips16_small = TRUE; |
252b5132 RH |
9162 | |
9163 | if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL) | |
9164 | { | |
9165 | insn_error = _("unrecognized opcode"); | |
9166 | return; | |
9167 | } | |
9168 | ||
9169 | argsstart = s; | |
9170 | for (;;) | |
9171 | { | |
9172 | assert (strcmp (insn->name, str) == 0); | |
9173 | ||
9174 | ip->insn_mo = insn; | |
9175 | ip->insn_opcode = insn->match; | |
b34976b6 | 9176 | ip->use_extend = FALSE; |
252b5132 | 9177 | imm_expr.X_op = O_absent; |
f6688943 TS |
9178 | imm_reloc[0] = BFD_RELOC_UNUSED; |
9179 | imm_reloc[1] = BFD_RELOC_UNUSED; | |
9180 | imm_reloc[2] = BFD_RELOC_UNUSED; | |
5f74bc13 | 9181 | imm2_expr.X_op = O_absent; |
252b5132 | 9182 | offset_expr.X_op = O_absent; |
f6688943 TS |
9183 | offset_reloc[0] = BFD_RELOC_UNUSED; |
9184 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
9185 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
9186 | for (args = insn->args; 1; ++args) |
9187 | { | |
9188 | int c; | |
9189 | ||
9190 | if (*s == ' ') | |
9191 | ++s; | |
9192 | ||
9193 | /* In this switch statement we call break if we did not find | |
9194 | a match, continue if we did find a match, or return if we | |
9195 | are done. */ | |
9196 | ||
9197 | c = *args; | |
9198 | switch (c) | |
9199 | { | |
9200 | case '\0': | |
9201 | if (*s == '\0') | |
9202 | { | |
9203 | /* Stuff the immediate value in now, if we can. */ | |
9204 | if (imm_expr.X_op == O_constant | |
f6688943 | 9205 | && *imm_reloc > BFD_RELOC_UNUSED |
252b5132 RH |
9206 | && insn->pinfo != INSN_MACRO) |
9207 | { | |
d6f16593 MR |
9208 | valueT tmp; |
9209 | ||
9210 | switch (*offset_reloc) | |
9211 | { | |
9212 | case BFD_RELOC_MIPS16_HI16_S: | |
9213 | tmp = (imm_expr.X_add_number + 0x8000) >> 16; | |
9214 | break; | |
9215 | ||
9216 | case BFD_RELOC_MIPS16_HI16: | |
9217 | tmp = imm_expr.X_add_number >> 16; | |
9218 | break; | |
9219 | ||
9220 | case BFD_RELOC_MIPS16_LO16: | |
9221 | tmp = ((imm_expr.X_add_number + 0x8000) & 0xffff) | |
9222 | - 0x8000; | |
9223 | break; | |
9224 | ||
9225 | case BFD_RELOC_UNUSED: | |
9226 | tmp = imm_expr.X_add_number; | |
9227 | break; | |
9228 | ||
9229 | default: | |
9230 | internalError (); | |
9231 | } | |
9232 | *offset_reloc = BFD_RELOC_UNUSED; | |
9233 | ||
c4e7957c | 9234 | mips16_immed (NULL, 0, *imm_reloc - BFD_RELOC_UNUSED, |
d6f16593 | 9235 | tmp, TRUE, mips16_small, |
252b5132 RH |
9236 | mips16_ext, &ip->insn_opcode, |
9237 | &ip->use_extend, &ip->extend); | |
9238 | imm_expr.X_op = O_absent; | |
f6688943 | 9239 | *imm_reloc = BFD_RELOC_UNUSED; |
252b5132 RH |
9240 | } |
9241 | ||
9242 | return; | |
9243 | } | |
9244 | break; | |
9245 | ||
9246 | case ',': | |
9247 | if (*s++ == c) | |
9248 | continue; | |
9249 | s--; | |
9250 | switch (*++args) | |
9251 | { | |
9252 | case 'v': | |
9253 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RX; | |
9254 | continue; | |
9255 | case 'w': | |
9256 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RY; | |
9257 | continue; | |
9258 | } | |
9259 | break; | |
9260 | ||
9261 | case '(': | |
9262 | case ')': | |
9263 | if (*s++ == c) | |
9264 | continue; | |
9265 | break; | |
9266 | ||
9267 | case 'v': | |
9268 | case 'w': | |
9269 | if (s[0] != '$') | |
9270 | { | |
9271 | if (c == 'v') | |
9272 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RX; | |
9273 | else | |
9274 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RY; | |
9275 | ++args; | |
9276 | continue; | |
9277 | } | |
9278 | /* Fall through. */ | |
9279 | case 'x': | |
9280 | case 'y': | |
9281 | case 'z': | |
9282 | case 'Z': | |
9283 | case '0': | |
9284 | case 'S': | |
9285 | case 'R': | |
9286 | case 'X': | |
9287 | case 'Y': | |
9288 | if (s[0] != '$') | |
9289 | break; | |
9290 | s_reset = s; | |
3882b010 | 9291 | if (ISDIGIT (s[1])) |
252b5132 RH |
9292 | { |
9293 | ++s; | |
9294 | regno = 0; | |
9295 | do | |
9296 | { | |
9297 | regno *= 10; | |
9298 | regno += *s - '0'; | |
9299 | ++s; | |
9300 | } | |
3882b010 | 9301 | while (ISDIGIT (*s)); |
252b5132 RH |
9302 | if (regno > 31) |
9303 | { | |
9304 | as_bad (_("invalid register number (%d)"), regno); | |
9305 | regno = 2; | |
9306 | } | |
9307 | } | |
9308 | else | |
9309 | { | |
76db943d TS |
9310 | if (s[1] == 'r' && s[2] == 'a') |
9311 | { | |
9312 | s += 3; | |
9313 | regno = RA; | |
9314 | } | |
9315 | else if (s[1] == 'f' && s[2] == 'p') | |
252b5132 RH |
9316 | { |
9317 | s += 3; | |
9318 | regno = FP; | |
9319 | } | |
9320 | else if (s[1] == 's' && s[2] == 'p') | |
9321 | { | |
9322 | s += 3; | |
9323 | regno = SP; | |
9324 | } | |
9325 | else if (s[1] == 'g' && s[2] == 'p') | |
9326 | { | |
9327 | s += 3; | |
9328 | regno = GP; | |
9329 | } | |
9330 | else if (s[1] == 'a' && s[2] == 't') | |
9331 | { | |
9332 | s += 3; | |
9333 | regno = AT; | |
9334 | } | |
9335 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '0') | |
9336 | { | |
9337 | s += 4; | |
9338 | regno = KT0; | |
9339 | } | |
9340 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '1') | |
9341 | { | |
9342 | s += 4; | |
9343 | regno = KT1; | |
9344 | } | |
85b51719 TS |
9345 | else if (s[1] == 'z' && s[2] == 'e' && s[3] == 'r' && s[4] == 'o') |
9346 | { | |
9347 | s += 5; | |
9348 | regno = ZERO; | |
9349 | } | |
252b5132 RH |
9350 | else |
9351 | break; | |
9352 | } | |
9353 | ||
9354 | if (*s == ' ') | |
9355 | ++s; | |
9356 | if (args[1] != *s) | |
9357 | { | |
9358 | if (c == 'v' || c == 'w') | |
9359 | { | |
9360 | regno = mips16_to_32_reg_map[lastregno]; | |
9361 | s = s_reset; | |
f9419b05 | 9362 | ++args; |
252b5132 RH |
9363 | } |
9364 | } | |
9365 | ||
9366 | switch (c) | |
9367 | { | |
9368 | case 'x': | |
9369 | case 'y': | |
9370 | case 'z': | |
9371 | case 'v': | |
9372 | case 'w': | |
9373 | case 'Z': | |
9374 | regno = mips32_to_16_reg_map[regno]; | |
9375 | break; | |
9376 | ||
9377 | case '0': | |
9378 | if (regno != 0) | |
9379 | regno = ILLEGAL_REG; | |
9380 | break; | |
9381 | ||
9382 | case 'S': | |
9383 | if (regno != SP) | |
9384 | regno = ILLEGAL_REG; | |
9385 | break; | |
9386 | ||
9387 | case 'R': | |
9388 | if (regno != RA) | |
9389 | regno = ILLEGAL_REG; | |
9390 | break; | |
9391 | ||
9392 | case 'X': | |
9393 | case 'Y': | |
9394 | if (regno == AT && ! mips_opts.noat) | |
9395 | as_warn (_("used $at without \".set noat\"")); | |
9396 | break; | |
9397 | ||
9398 | default: | |
9399 | internalError (); | |
9400 | } | |
9401 | ||
9402 | if (regno == ILLEGAL_REG) | |
9403 | break; | |
9404 | ||
9405 | switch (c) | |
9406 | { | |
9407 | case 'x': | |
9408 | case 'v': | |
9409 | ip->insn_opcode |= regno << MIPS16OP_SH_RX; | |
9410 | break; | |
9411 | case 'y': | |
9412 | case 'w': | |
9413 | ip->insn_opcode |= regno << MIPS16OP_SH_RY; | |
9414 | break; | |
9415 | case 'z': | |
9416 | ip->insn_opcode |= regno << MIPS16OP_SH_RZ; | |
9417 | break; | |
9418 | case 'Z': | |
9419 | ip->insn_opcode |= regno << MIPS16OP_SH_MOVE32Z; | |
9420 | case '0': | |
9421 | case 'S': | |
9422 | case 'R': | |
9423 | break; | |
9424 | case 'X': | |
9425 | ip->insn_opcode |= regno << MIPS16OP_SH_REGR32; | |
9426 | break; | |
9427 | case 'Y': | |
9428 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); | |
9429 | ip->insn_opcode |= regno << MIPS16OP_SH_REG32R; | |
9430 | break; | |
9431 | default: | |
9432 | internalError (); | |
9433 | } | |
9434 | ||
9435 | lastregno = regno; | |
9436 | continue; | |
9437 | ||
9438 | case 'P': | |
9439 | if (strncmp (s, "$pc", 3) == 0) | |
9440 | { | |
9441 | s += 3; | |
9442 | continue; | |
9443 | } | |
9444 | break; | |
9445 | ||
252b5132 RH |
9446 | case '5': |
9447 | case 'H': | |
9448 | case 'W': | |
9449 | case 'D': | |
9450 | case 'j': | |
252b5132 RH |
9451 | case 'V': |
9452 | case 'C': | |
9453 | case 'U': | |
9454 | case 'k': | |
9455 | case 'K': | |
d6f16593 MR |
9456 | i = my_getSmallExpression (&imm_expr, imm_reloc, s); |
9457 | if (i > 0) | |
252b5132 | 9458 | { |
d6f16593 | 9459 | if (imm_expr.X_op != O_constant) |
252b5132 | 9460 | { |
b34976b6 | 9461 | mips16_ext = TRUE; |
b34976b6 | 9462 | ip->use_extend = TRUE; |
252b5132 | 9463 | ip->extend = 0; |
252b5132 | 9464 | } |
d6f16593 MR |
9465 | else |
9466 | { | |
9467 | /* We need to relax this instruction. */ | |
9468 | *offset_reloc = *imm_reloc; | |
9469 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; | |
9470 | } | |
9471 | s = expr_end; | |
9472 | continue; | |
252b5132 | 9473 | } |
d6f16593 MR |
9474 | *imm_reloc = BFD_RELOC_UNUSED; |
9475 | /* Fall through. */ | |
9476 | case '<': | |
9477 | case '>': | |
9478 | case '[': | |
9479 | case ']': | |
9480 | case '4': | |
9481 | case '8': | |
9482 | my_getExpression (&imm_expr, s); | |
252b5132 RH |
9483 | if (imm_expr.X_op == O_register) |
9484 | { | |
9485 | /* What we thought was an expression turned out to | |
9486 | be a register. */ | |
9487 | ||
9488 | if (s[0] == '(' && args[1] == '(') | |
9489 | { | |
9490 | /* It looks like the expression was omitted | |
9491 | before a register indirection, which means | |
9492 | that the expression is implicitly zero. We | |
9493 | still set up imm_expr, so that we handle | |
9494 | explicit extensions correctly. */ | |
9495 | imm_expr.X_op = O_constant; | |
9496 | imm_expr.X_add_number = 0; | |
f6688943 | 9497 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
9498 | continue; |
9499 | } | |
9500 | ||
9501 | break; | |
9502 | } | |
9503 | ||
9504 | /* We need to relax this instruction. */ | |
f6688943 | 9505 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
9506 | s = expr_end; |
9507 | continue; | |
9508 | ||
9509 | case 'p': | |
9510 | case 'q': | |
9511 | case 'A': | |
9512 | case 'B': | |
9513 | case 'E': | |
9514 | /* We use offset_reloc rather than imm_reloc for the PC | |
9515 | relative operands. This lets macros with both | |
9516 | immediate and address operands work correctly. */ | |
9517 | my_getExpression (&offset_expr, s); | |
9518 | ||
9519 | if (offset_expr.X_op == O_register) | |
9520 | break; | |
9521 | ||
9522 | /* We need to relax this instruction. */ | |
f6688943 | 9523 | *offset_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
9524 | s = expr_end; |
9525 | continue; | |
9526 | ||
9527 | case '6': /* break code */ | |
9528 | my_getExpression (&imm_expr, s); | |
9529 | check_absolute_expr (ip, &imm_expr); | |
9530 | if ((unsigned long) imm_expr.X_add_number > 63) | |
9531 | { | |
9532 | as_warn (_("Invalid value for `%s' (%lu)"), | |
9533 | ip->insn_mo->name, | |
9534 | (unsigned long) imm_expr.X_add_number); | |
9535 | imm_expr.X_add_number &= 0x3f; | |
9536 | } | |
9537 | ip->insn_opcode |= imm_expr.X_add_number << MIPS16OP_SH_IMM6; | |
9538 | imm_expr.X_op = O_absent; | |
9539 | s = expr_end; | |
9540 | continue; | |
9541 | ||
9542 | case 'a': /* 26 bit address */ | |
9543 | my_getExpression (&offset_expr, s); | |
9544 | s = expr_end; | |
f6688943 | 9545 | *offset_reloc = BFD_RELOC_MIPS16_JMP; |
252b5132 RH |
9546 | ip->insn_opcode <<= 16; |
9547 | continue; | |
9548 | ||
9549 | case 'l': /* register list for entry macro */ | |
9550 | case 'L': /* register list for exit macro */ | |
9551 | { | |
9552 | int mask; | |
9553 | ||
9554 | if (c == 'l') | |
9555 | mask = 0; | |
9556 | else | |
9557 | mask = 7 << 3; | |
9558 | while (*s != '\0') | |
9559 | { | |
9560 | int freg, reg1, reg2; | |
9561 | ||
9562 | while (*s == ' ' || *s == ',') | |
9563 | ++s; | |
9564 | if (*s != '$') | |
9565 | { | |
9566 | as_bad (_("can't parse register list")); | |
9567 | break; | |
9568 | } | |
9569 | ++s; | |
9570 | if (*s != 'f') | |
9571 | freg = 0; | |
9572 | else | |
9573 | { | |
9574 | freg = 1; | |
9575 | ++s; | |
9576 | } | |
9577 | reg1 = 0; | |
3882b010 | 9578 | while (ISDIGIT (*s)) |
252b5132 RH |
9579 | { |
9580 | reg1 *= 10; | |
9581 | reg1 += *s - '0'; | |
9582 | ++s; | |
9583 | } | |
9584 | if (*s == ' ') | |
9585 | ++s; | |
9586 | if (*s != '-') | |
9587 | reg2 = reg1; | |
9588 | else | |
9589 | { | |
9590 | ++s; | |
9591 | if (*s != '$') | |
9592 | break; | |
9593 | ++s; | |
9594 | if (freg) | |
9595 | { | |
9596 | if (*s == 'f') | |
9597 | ++s; | |
9598 | else | |
9599 | { | |
9600 | as_bad (_("invalid register list")); | |
9601 | break; | |
9602 | } | |
9603 | } | |
9604 | reg2 = 0; | |
3882b010 | 9605 | while (ISDIGIT (*s)) |
252b5132 RH |
9606 | { |
9607 | reg2 *= 10; | |
9608 | reg2 += *s - '0'; | |
9609 | ++s; | |
9610 | } | |
9611 | } | |
9612 | if (freg && reg1 == 0 && reg2 == 0 && c == 'L') | |
9613 | { | |
9614 | mask &= ~ (7 << 3); | |
9615 | mask |= 5 << 3; | |
9616 | } | |
9617 | else if (freg && reg1 == 0 && reg2 == 1 && c == 'L') | |
9618 | { | |
9619 | mask &= ~ (7 << 3); | |
9620 | mask |= 6 << 3; | |
9621 | } | |
9622 | else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L') | |
9623 | mask |= (reg2 - 3) << 3; | |
9624 | else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17) | |
9625 | mask |= (reg2 - 15) << 1; | |
f9419b05 | 9626 | else if (reg1 == RA && reg2 == RA) |
252b5132 RH |
9627 | mask |= 1; |
9628 | else | |
9629 | { | |
9630 | as_bad (_("invalid register list")); | |
9631 | break; | |
9632 | } | |
9633 | } | |
9634 | /* The mask is filled in in the opcode table for the | |
9635 | benefit of the disassembler. We remove it before | |
9636 | applying the actual mask. */ | |
9637 | ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6); | |
9638 | ip->insn_opcode |= mask << MIPS16OP_SH_IMM6; | |
9639 | } | |
9640 | continue; | |
9641 | ||
9642 | case 'e': /* extend code */ | |
9643 | my_getExpression (&imm_expr, s); | |
9644 | check_absolute_expr (ip, &imm_expr); | |
9645 | if ((unsigned long) imm_expr.X_add_number > 0x7ff) | |
9646 | { | |
9647 | as_warn (_("Invalid value for `%s' (%lu)"), | |
9648 | ip->insn_mo->name, | |
9649 | (unsigned long) imm_expr.X_add_number); | |
9650 | imm_expr.X_add_number &= 0x7ff; | |
9651 | } | |
9652 | ip->insn_opcode |= imm_expr.X_add_number; | |
9653 | imm_expr.X_op = O_absent; | |
9654 | s = expr_end; | |
9655 | continue; | |
9656 | ||
9657 | default: | |
9658 | internalError (); | |
9659 | } | |
9660 | break; | |
9661 | } | |
9662 | ||
9663 | /* Args don't match. */ | |
9664 | if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] && | |
9665 | strcmp (insn->name, insn[1].name) == 0) | |
9666 | { | |
9667 | ++insn; | |
9668 | s = argsstart; | |
9669 | continue; | |
9670 | } | |
9671 | ||
9672 | insn_error = _("illegal operands"); | |
9673 | ||
9674 | return; | |
9675 | } | |
9676 | } | |
9677 | ||
9678 | /* This structure holds information we know about a mips16 immediate | |
9679 | argument type. */ | |
9680 | ||
e972090a NC |
9681 | struct mips16_immed_operand |
9682 | { | |
252b5132 RH |
9683 | /* The type code used in the argument string in the opcode table. */ |
9684 | int type; | |
9685 | /* The number of bits in the short form of the opcode. */ | |
9686 | int nbits; | |
9687 | /* The number of bits in the extended form of the opcode. */ | |
9688 | int extbits; | |
9689 | /* The amount by which the short form is shifted when it is used; | |
9690 | for example, the sw instruction has a shift count of 2. */ | |
9691 | int shift; | |
9692 | /* The amount by which the short form is shifted when it is stored | |
9693 | into the instruction code. */ | |
9694 | int op_shift; | |
9695 | /* Non-zero if the short form is unsigned. */ | |
9696 | int unsp; | |
9697 | /* Non-zero if the extended form is unsigned. */ | |
9698 | int extu; | |
9699 | /* Non-zero if the value is PC relative. */ | |
9700 | int pcrel; | |
9701 | }; | |
9702 | ||
9703 | /* The mips16 immediate operand types. */ | |
9704 | ||
9705 | static const struct mips16_immed_operand mips16_immed_operands[] = | |
9706 | { | |
9707 | { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
9708 | { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
9709 | { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
9710 | { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
9711 | { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 }, | |
9712 | { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
9713 | { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
9714 | { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
9715 | { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
9716 | { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 }, | |
9717 | { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
9718 | { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
9719 | { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
9720 | { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 }, | |
9721 | { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
9722 | { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
9723 | { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
9724 | { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
9725 | { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 }, | |
9726 | { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 }, | |
9727 | { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 } | |
9728 | }; | |
9729 | ||
9730 | #define MIPS16_NUM_IMMED \ | |
9731 | (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0]) | |
9732 | ||
9733 | /* Handle a mips16 instruction with an immediate value. This or's the | |
9734 | small immediate value into *INSN. It sets *USE_EXTEND to indicate | |
9735 | whether an extended value is needed; if one is needed, it sets | |
9736 | *EXTEND to the value. The argument type is TYPE. The value is VAL. | |
9737 | If SMALL is true, an unextended opcode was explicitly requested. | |
9738 | If EXT is true, an extended opcode was explicitly requested. If | |
9739 | WARN is true, warn if EXT does not match reality. */ | |
9740 | ||
9741 | static void | |
17a2f251 TS |
9742 | mips16_immed (char *file, unsigned int line, int type, offsetT val, |
9743 | bfd_boolean warn, bfd_boolean small, bfd_boolean ext, | |
9744 | unsigned long *insn, bfd_boolean *use_extend, | |
9745 | unsigned short *extend) | |
252b5132 RH |
9746 | { |
9747 | register const struct mips16_immed_operand *op; | |
9748 | int mintiny, maxtiny; | |
b34976b6 | 9749 | bfd_boolean needext; |
252b5132 RH |
9750 | |
9751 | op = mips16_immed_operands; | |
9752 | while (op->type != type) | |
9753 | { | |
9754 | ++op; | |
9755 | assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); | |
9756 | } | |
9757 | ||
9758 | if (op->unsp) | |
9759 | { | |
9760 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
9761 | { | |
9762 | mintiny = 1; | |
9763 | maxtiny = 1 << op->nbits; | |
9764 | } | |
9765 | else | |
9766 | { | |
9767 | mintiny = 0; | |
9768 | maxtiny = (1 << op->nbits) - 1; | |
9769 | } | |
9770 | } | |
9771 | else | |
9772 | { | |
9773 | mintiny = - (1 << (op->nbits - 1)); | |
9774 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
9775 | } | |
9776 | ||
9777 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
9778 | if (type == 'p' || type == 'q') | |
9779 | val /= 2; | |
9780 | ||
9781 | if ((val & ((1 << op->shift) - 1)) != 0 | |
9782 | || val < (mintiny << op->shift) | |
9783 | || val > (maxtiny << op->shift)) | |
b34976b6 | 9784 | needext = TRUE; |
252b5132 | 9785 | else |
b34976b6 | 9786 | needext = FALSE; |
252b5132 RH |
9787 | |
9788 | if (warn && ext && ! needext) | |
beae10d5 KH |
9789 | as_warn_where (file, line, |
9790 | _("extended operand requested but not required")); | |
252b5132 RH |
9791 | if (small && needext) |
9792 | as_bad_where (file, line, _("invalid unextended operand value")); | |
9793 | ||
9794 | if (small || (! ext && ! needext)) | |
9795 | { | |
9796 | int insnval; | |
9797 | ||
b34976b6 | 9798 | *use_extend = FALSE; |
252b5132 RH |
9799 | insnval = ((val >> op->shift) & ((1 << op->nbits) - 1)); |
9800 | insnval <<= op->op_shift; | |
9801 | *insn |= insnval; | |
9802 | } | |
9803 | else | |
9804 | { | |
9805 | long minext, maxext; | |
9806 | int extval; | |
9807 | ||
9808 | if (op->extu) | |
9809 | { | |
9810 | minext = 0; | |
9811 | maxext = (1 << op->extbits) - 1; | |
9812 | } | |
9813 | else | |
9814 | { | |
9815 | minext = - (1 << (op->extbits - 1)); | |
9816 | maxext = (1 << (op->extbits - 1)) - 1; | |
9817 | } | |
9818 | if (val < minext || val > maxext) | |
9819 | as_bad_where (file, line, | |
9820 | _("operand value out of range for instruction")); | |
9821 | ||
b34976b6 | 9822 | *use_extend = TRUE; |
252b5132 RH |
9823 | if (op->extbits == 16) |
9824 | { | |
9825 | extval = ((val >> 11) & 0x1f) | (val & 0x7e0); | |
9826 | val &= 0x1f; | |
9827 | } | |
9828 | else if (op->extbits == 15) | |
9829 | { | |
9830 | extval = ((val >> 11) & 0xf) | (val & 0x7f0); | |
9831 | val &= 0xf; | |
9832 | } | |
9833 | else | |
9834 | { | |
9835 | extval = ((val & 0x1f) << 6) | (val & 0x20); | |
9836 | val = 0; | |
9837 | } | |
9838 | ||
9839 | *extend = (unsigned short) extval; | |
9840 | *insn |= val; | |
9841 | } | |
9842 | } | |
9843 | \f | |
d6f16593 | 9844 | struct percent_op_match |
ad8d3bb3 | 9845 | { |
5e0116d5 RS |
9846 | const char *str; |
9847 | bfd_reloc_code_real_type reloc; | |
d6f16593 MR |
9848 | }; |
9849 | ||
9850 | static const struct percent_op_match mips_percent_op[] = | |
ad8d3bb3 | 9851 | { |
5e0116d5 | 9852 | {"%lo", BFD_RELOC_LO16}, |
ad8d3bb3 | 9853 | #ifdef OBJ_ELF |
5e0116d5 RS |
9854 | {"%call_hi", BFD_RELOC_MIPS_CALL_HI16}, |
9855 | {"%call_lo", BFD_RELOC_MIPS_CALL_LO16}, | |
9856 | {"%call16", BFD_RELOC_MIPS_CALL16}, | |
9857 | {"%got_disp", BFD_RELOC_MIPS_GOT_DISP}, | |
9858 | {"%got_page", BFD_RELOC_MIPS_GOT_PAGE}, | |
9859 | {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST}, | |
9860 | {"%got_hi", BFD_RELOC_MIPS_GOT_HI16}, | |
9861 | {"%got_lo", BFD_RELOC_MIPS_GOT_LO16}, | |
9862 | {"%got", BFD_RELOC_MIPS_GOT16}, | |
9863 | {"%gp_rel", BFD_RELOC_GPREL16}, | |
9864 | {"%half", BFD_RELOC_16}, | |
9865 | {"%highest", BFD_RELOC_MIPS_HIGHEST}, | |
9866 | {"%higher", BFD_RELOC_MIPS_HIGHER}, | |
9867 | {"%neg", BFD_RELOC_MIPS_SUB}, | |
ad8d3bb3 | 9868 | #endif |
5e0116d5 | 9869 | {"%hi", BFD_RELOC_HI16_S} |
ad8d3bb3 TS |
9870 | }; |
9871 | ||
d6f16593 MR |
9872 | static const struct percent_op_match mips16_percent_op[] = |
9873 | { | |
9874 | {"%lo", BFD_RELOC_MIPS16_LO16}, | |
9875 | {"%gprel", BFD_RELOC_MIPS16_GPREL}, | |
9876 | {"%hi", BFD_RELOC_MIPS16_HI16_S} | |
9877 | }; | |
9878 | ||
252b5132 | 9879 | |
5e0116d5 RS |
9880 | /* Return true if *STR points to a relocation operator. When returning true, |
9881 | move *STR over the operator and store its relocation code in *RELOC. | |
9882 | Leave both *STR and *RELOC alone when returning false. */ | |
9883 | ||
9884 | static bfd_boolean | |
17a2f251 | 9885 | parse_relocation (char **str, bfd_reloc_code_real_type *reloc) |
252b5132 | 9886 | { |
d6f16593 MR |
9887 | const struct percent_op_match *percent_op; |
9888 | size_t limit, i; | |
9889 | ||
9890 | if (mips_opts.mips16) | |
9891 | { | |
9892 | percent_op = mips16_percent_op; | |
9893 | limit = ARRAY_SIZE (mips16_percent_op); | |
9894 | } | |
9895 | else | |
9896 | { | |
9897 | percent_op = mips_percent_op; | |
9898 | limit = ARRAY_SIZE (mips_percent_op); | |
9899 | } | |
76b3015f | 9900 | |
d6f16593 | 9901 | for (i = 0; i < limit; i++) |
5e0116d5 | 9902 | if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0) |
394f9b3a | 9903 | { |
5e0116d5 RS |
9904 | *str += strlen (percent_op[i].str); |
9905 | *reloc = percent_op[i].reloc; | |
394f9b3a | 9906 | |
5e0116d5 RS |
9907 | /* Check whether the output BFD supports this relocation. |
9908 | If not, issue an error and fall back on something safe. */ | |
9909 | if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc)) | |
394f9b3a | 9910 | { |
5e0116d5 RS |
9911 | as_bad ("relocation %s isn't supported by the current ABI", |
9912 | percent_op[i].str); | |
01a3f561 | 9913 | *reloc = BFD_RELOC_UNUSED; |
394f9b3a | 9914 | } |
5e0116d5 | 9915 | return TRUE; |
394f9b3a | 9916 | } |
5e0116d5 | 9917 | return FALSE; |
394f9b3a | 9918 | } |
ad8d3bb3 | 9919 | |
ad8d3bb3 | 9920 | |
5e0116d5 RS |
9921 | /* Parse string STR as a 16-bit relocatable operand. Store the |
9922 | expression in *EP and the relocations in the array starting | |
9923 | at RELOC. Return the number of relocation operators used. | |
ad8d3bb3 | 9924 | |
01a3f561 | 9925 | On exit, EXPR_END points to the first character after the expression. */ |
ad8d3bb3 | 9926 | |
5e0116d5 | 9927 | static size_t |
17a2f251 TS |
9928 | my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc, |
9929 | char *str) | |
ad8d3bb3 | 9930 | { |
5e0116d5 RS |
9931 | bfd_reloc_code_real_type reversed_reloc[3]; |
9932 | size_t reloc_index, i; | |
09b8f35a RS |
9933 | int crux_depth, str_depth; |
9934 | char *crux; | |
5e0116d5 RS |
9935 | |
9936 | /* Search for the start of the main expression, recoding relocations | |
09b8f35a RS |
9937 | in REVERSED_RELOC. End the loop with CRUX pointing to the start |
9938 | of the main expression and with CRUX_DEPTH containing the number | |
9939 | of open brackets at that point. */ | |
9940 | reloc_index = -1; | |
9941 | str_depth = 0; | |
9942 | do | |
fb1b3232 | 9943 | { |
09b8f35a RS |
9944 | reloc_index++; |
9945 | crux = str; | |
9946 | crux_depth = str_depth; | |
9947 | ||
9948 | /* Skip over whitespace and brackets, keeping count of the number | |
9949 | of brackets. */ | |
9950 | while (*str == ' ' || *str == '\t' || *str == '(') | |
9951 | if (*str++ == '(') | |
9952 | str_depth++; | |
5e0116d5 | 9953 | } |
09b8f35a RS |
9954 | while (*str == '%' |
9955 | && reloc_index < (HAVE_NEWABI ? 3 : 1) | |
9956 | && parse_relocation (&str, &reversed_reloc[reloc_index])); | |
ad8d3bb3 | 9957 | |
09b8f35a | 9958 | my_getExpression (ep, crux); |
5e0116d5 | 9959 | str = expr_end; |
394f9b3a | 9960 | |
5e0116d5 | 9961 | /* Match every open bracket. */ |
09b8f35a | 9962 | while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t')) |
5e0116d5 | 9963 | if (*str++ == ')') |
09b8f35a | 9964 | crux_depth--; |
394f9b3a | 9965 | |
09b8f35a | 9966 | if (crux_depth > 0) |
5e0116d5 | 9967 | as_bad ("unclosed '('"); |
394f9b3a | 9968 | |
5e0116d5 | 9969 | expr_end = str; |
252b5132 | 9970 | |
01a3f561 | 9971 | if (reloc_index != 0) |
64bdfcaf RS |
9972 | { |
9973 | prev_reloc_op_frag = frag_now; | |
9974 | for (i = 0; i < reloc_index; i++) | |
9975 | reloc[i] = reversed_reloc[reloc_index - 1 - i]; | |
9976 | } | |
fb1b3232 | 9977 | |
5e0116d5 | 9978 | return reloc_index; |
252b5132 RH |
9979 | } |
9980 | ||
9981 | static void | |
17a2f251 | 9982 | my_getExpression (expressionS *ep, char *str) |
252b5132 RH |
9983 | { |
9984 | char *save_in; | |
98aa84af | 9985 | valueT val; |
252b5132 RH |
9986 | |
9987 | save_in = input_line_pointer; | |
9988 | input_line_pointer = str; | |
9989 | expression (ep); | |
9990 | expr_end = input_line_pointer; | |
9991 | input_line_pointer = save_in; | |
9992 | ||
9993 | /* If we are in mips16 mode, and this is an expression based on `.', | |
9994 | then we bump the value of the symbol by 1 since that is how other | |
9995 | text symbols are handled. We don't bother to handle complex | |
9996 | expressions, just `.' plus or minus a constant. */ | |
9997 | if (mips_opts.mips16 | |
9998 | && ep->X_op == O_symbol | |
9999 | && strcmp (S_GET_NAME (ep->X_add_symbol), FAKE_LABEL_NAME) == 0 | |
10000 | && S_GET_SEGMENT (ep->X_add_symbol) == now_seg | |
49309057 ILT |
10001 | && symbol_get_frag (ep->X_add_symbol) == frag_now |
10002 | && symbol_constant_p (ep->X_add_symbol) | |
98aa84af AM |
10003 | && (val = S_GET_VALUE (ep->X_add_symbol)) == frag_now_fix ()) |
10004 | S_SET_VALUE (ep->X_add_symbol, val + 1); | |
252b5132 RH |
10005 | } |
10006 | ||
10007 | /* Turn a string in input_line_pointer into a floating point constant | |
bc0d738a NC |
10008 | of type TYPE, and store the appropriate bytes in *LITP. The number |
10009 | of LITTLENUMS emitted is stored in *SIZEP. An error message is | |
252b5132 RH |
10010 | returned, or NULL on OK. */ |
10011 | ||
10012 | char * | |
17a2f251 | 10013 | md_atof (int type, char *litP, int *sizeP) |
252b5132 RH |
10014 | { |
10015 | int prec; | |
10016 | LITTLENUM_TYPE words[4]; | |
10017 | char *t; | |
10018 | int i; | |
10019 | ||
10020 | switch (type) | |
10021 | { | |
10022 | case 'f': | |
10023 | prec = 2; | |
10024 | break; | |
10025 | ||
10026 | case 'd': | |
10027 | prec = 4; | |
10028 | break; | |
10029 | ||
10030 | default: | |
10031 | *sizeP = 0; | |
10032 | return _("bad call to md_atof"); | |
10033 | } | |
10034 | ||
10035 | t = atof_ieee (input_line_pointer, type, words); | |
10036 | if (t) | |
10037 | input_line_pointer = t; | |
10038 | ||
10039 | *sizeP = prec * 2; | |
10040 | ||
10041 | if (! target_big_endian) | |
10042 | { | |
10043 | for (i = prec - 1; i >= 0; i--) | |
10044 | { | |
17a2f251 | 10045 | md_number_to_chars (litP, words[i], 2); |
252b5132 RH |
10046 | litP += 2; |
10047 | } | |
10048 | } | |
10049 | else | |
10050 | { | |
10051 | for (i = 0; i < prec; i++) | |
10052 | { | |
17a2f251 | 10053 | md_number_to_chars (litP, words[i], 2); |
252b5132 RH |
10054 | litP += 2; |
10055 | } | |
10056 | } | |
bdaaa2e1 | 10057 | |
252b5132 RH |
10058 | return NULL; |
10059 | } | |
10060 | ||
10061 | void | |
17a2f251 | 10062 | md_number_to_chars (char *buf, valueT val, int n) |
252b5132 RH |
10063 | { |
10064 | if (target_big_endian) | |
10065 | number_to_chars_bigendian (buf, val, n); | |
10066 | else | |
10067 | number_to_chars_littleendian (buf, val, n); | |
10068 | } | |
10069 | \f | |
ae948b86 | 10070 | #ifdef OBJ_ELF |
e013f690 TS |
10071 | static int support_64bit_objects(void) |
10072 | { | |
10073 | const char **list, **l; | |
aa3d8fdf | 10074 | int yes; |
e013f690 TS |
10075 | |
10076 | list = bfd_target_list (); | |
10077 | for (l = list; *l != NULL; l++) | |
10078 | #ifdef TE_TMIPS | |
10079 | /* This is traditional mips */ | |
10080 | if (strcmp (*l, "elf64-tradbigmips") == 0 | |
10081 | || strcmp (*l, "elf64-tradlittlemips") == 0) | |
10082 | #else | |
10083 | if (strcmp (*l, "elf64-bigmips") == 0 | |
10084 | || strcmp (*l, "elf64-littlemips") == 0) | |
10085 | #endif | |
10086 | break; | |
aa3d8fdf | 10087 | yes = (*l != NULL); |
e013f690 | 10088 | free (list); |
aa3d8fdf | 10089 | return yes; |
e013f690 | 10090 | } |
ae948b86 | 10091 | #endif /* OBJ_ELF */ |
e013f690 | 10092 | |
78849248 | 10093 | const char *md_shortopts = "O::g::G:"; |
252b5132 | 10094 | |
e972090a NC |
10095 | struct option md_longopts[] = |
10096 | { | |
f9b4148d CD |
10097 | /* Options which specify architecture. */ |
10098 | #define OPTION_ARCH_BASE (OPTION_MD_BASE) | |
10099 | #define OPTION_MARCH (OPTION_ARCH_BASE + 0) | |
10100 | {"march", required_argument, NULL, OPTION_MARCH}, | |
10101 | #define OPTION_MTUNE (OPTION_ARCH_BASE + 1) | |
10102 | {"mtune", required_argument, NULL, OPTION_MTUNE}, | |
10103 | #define OPTION_MIPS1 (OPTION_ARCH_BASE + 2) | |
252b5132 RH |
10104 | {"mips0", no_argument, NULL, OPTION_MIPS1}, |
10105 | {"mips1", no_argument, NULL, OPTION_MIPS1}, | |
f9b4148d | 10106 | #define OPTION_MIPS2 (OPTION_ARCH_BASE + 3) |
252b5132 | 10107 | {"mips2", no_argument, NULL, OPTION_MIPS2}, |
f9b4148d | 10108 | #define OPTION_MIPS3 (OPTION_ARCH_BASE + 4) |
252b5132 | 10109 | {"mips3", no_argument, NULL, OPTION_MIPS3}, |
f9b4148d | 10110 | #define OPTION_MIPS4 (OPTION_ARCH_BASE + 5) |
252b5132 | 10111 | {"mips4", no_argument, NULL, OPTION_MIPS4}, |
f9b4148d | 10112 | #define OPTION_MIPS5 (OPTION_ARCH_BASE + 6) |
ae948b86 | 10113 | {"mips5", no_argument, NULL, OPTION_MIPS5}, |
f9b4148d | 10114 | #define OPTION_MIPS32 (OPTION_ARCH_BASE + 7) |
ae948b86 | 10115 | {"mips32", no_argument, NULL, OPTION_MIPS32}, |
f9b4148d | 10116 | #define OPTION_MIPS64 (OPTION_ARCH_BASE + 8) |
ae948b86 | 10117 | {"mips64", no_argument, NULL, OPTION_MIPS64}, |
f9b4148d CD |
10118 | #define OPTION_MIPS32R2 (OPTION_ARCH_BASE + 9) |
10119 | {"mips32r2", no_argument, NULL, OPTION_MIPS32R2}, | |
5f74bc13 CD |
10120 | #define OPTION_MIPS64R2 (OPTION_ARCH_BASE + 10) |
10121 | {"mips64r2", no_argument, NULL, OPTION_MIPS64R2}, | |
f9b4148d CD |
10122 | |
10123 | /* Options which specify Application Specific Extensions (ASEs). */ | |
5f74bc13 | 10124 | #define OPTION_ASE_BASE (OPTION_ARCH_BASE + 11) |
f9b4148d CD |
10125 | #define OPTION_MIPS16 (OPTION_ASE_BASE + 0) |
10126 | {"mips16", no_argument, NULL, OPTION_MIPS16}, | |
10127 | #define OPTION_NO_MIPS16 (OPTION_ASE_BASE + 1) | |
10128 | {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16}, | |
10129 | #define OPTION_MIPS3D (OPTION_ASE_BASE + 2) | |
10130 | {"mips3d", no_argument, NULL, OPTION_MIPS3D}, | |
10131 | #define OPTION_NO_MIPS3D (OPTION_ASE_BASE + 3) | |
10132 | {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D}, | |
10133 | #define OPTION_MDMX (OPTION_ASE_BASE + 4) | |
10134 | {"mdmx", no_argument, NULL, OPTION_MDMX}, | |
10135 | #define OPTION_NO_MDMX (OPTION_ASE_BASE + 5) | |
10136 | {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX}, | |
10137 | ||
10138 | /* Old-style architecture options. Don't add more of these. */ | |
10139 | #define OPTION_COMPAT_ARCH_BASE (OPTION_ASE_BASE + 6) | |
10140 | #define OPTION_M4650 (OPTION_COMPAT_ARCH_BASE + 0) | |
10141 | {"m4650", no_argument, NULL, OPTION_M4650}, | |
10142 | #define OPTION_NO_M4650 (OPTION_COMPAT_ARCH_BASE + 1) | |
10143 | {"no-m4650", no_argument, NULL, OPTION_NO_M4650}, | |
10144 | #define OPTION_M4010 (OPTION_COMPAT_ARCH_BASE + 2) | |
10145 | {"m4010", no_argument, NULL, OPTION_M4010}, | |
10146 | #define OPTION_NO_M4010 (OPTION_COMPAT_ARCH_BASE + 3) | |
10147 | {"no-m4010", no_argument, NULL, OPTION_NO_M4010}, | |
10148 | #define OPTION_M4100 (OPTION_COMPAT_ARCH_BASE + 4) | |
10149 | {"m4100", no_argument, NULL, OPTION_M4100}, | |
10150 | #define OPTION_NO_M4100 (OPTION_COMPAT_ARCH_BASE + 5) | |
10151 | {"no-m4100", no_argument, NULL, OPTION_NO_M4100}, | |
10152 | #define OPTION_M3900 (OPTION_COMPAT_ARCH_BASE + 6) | |
10153 | {"m3900", no_argument, NULL, OPTION_M3900}, | |
10154 | #define OPTION_NO_M3900 (OPTION_COMPAT_ARCH_BASE + 7) | |
10155 | {"no-m3900", no_argument, NULL, OPTION_NO_M3900}, | |
10156 | ||
10157 | /* Options which enable bug fixes. */ | |
10158 | #define OPTION_FIX_BASE (OPTION_COMPAT_ARCH_BASE + 8) | |
10159 | #define OPTION_M7000_HILO_FIX (OPTION_FIX_BASE + 0) | |
10160 | {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX}, | |
10161 | #define OPTION_MNO_7000_HILO_FIX (OPTION_FIX_BASE + 1) | |
10162 | {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, | |
10163 | {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, | |
d766e8ec RS |
10164 | #define OPTION_FIX_VR4120 (OPTION_FIX_BASE + 2) |
10165 | #define OPTION_NO_FIX_VR4120 (OPTION_FIX_BASE + 3) | |
10166 | {"mfix-vr4120", no_argument, NULL, OPTION_FIX_VR4120}, | |
10167 | {"mno-fix-vr4120", no_argument, NULL, OPTION_NO_FIX_VR4120}, | |
f9b4148d CD |
10168 | |
10169 | /* Miscellaneous options. */ | |
10170 | #define OPTION_MISC_BASE (OPTION_FIX_BASE + 4) | |
1ffcab4b | 10171 | #define OPTION_TRAP (OPTION_MISC_BASE + 0) |
252b5132 RH |
10172 | {"trap", no_argument, NULL, OPTION_TRAP}, |
10173 | {"no-break", no_argument, NULL, OPTION_TRAP}, | |
1ffcab4b | 10174 | #define OPTION_BREAK (OPTION_MISC_BASE + 1) |
252b5132 RH |
10175 | {"break", no_argument, NULL, OPTION_BREAK}, |
10176 | {"no-trap", no_argument, NULL, OPTION_BREAK}, | |
1ffcab4b | 10177 | #define OPTION_EB (OPTION_MISC_BASE + 2) |
252b5132 | 10178 | {"EB", no_argument, NULL, OPTION_EB}, |
1ffcab4b | 10179 | #define OPTION_EL (OPTION_MISC_BASE + 3) |
252b5132 | 10180 | {"EL", no_argument, NULL, OPTION_EL}, |
1ffcab4b | 10181 | #define OPTION_FP32 (OPTION_MISC_BASE + 4) |
ae948b86 | 10182 | {"mfp32", no_argument, NULL, OPTION_FP32}, |
1ffcab4b | 10183 | #define OPTION_GP32 (OPTION_MISC_BASE + 5) |
c97ef257 | 10184 | {"mgp32", no_argument, NULL, OPTION_GP32}, |
1ffcab4b | 10185 | #define OPTION_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 6) |
119d663a | 10186 | {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS}, |
1ffcab4b | 10187 | #define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 7) |
119d663a | 10188 | {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS}, |
1ffcab4b | 10189 | #define OPTION_FP64 (OPTION_MISC_BASE + 8) |
316f5878 | 10190 | {"mfp64", no_argument, NULL, OPTION_FP64}, |
1ffcab4b | 10191 | #define OPTION_GP64 (OPTION_MISC_BASE + 9) |
ae948b86 | 10192 | {"mgp64", no_argument, NULL, OPTION_GP64}, |
1ffcab4b CD |
10193 | #define OPTION_RELAX_BRANCH (OPTION_MISC_BASE + 10) |
10194 | #define OPTION_NO_RELAX_BRANCH (OPTION_MISC_BASE + 11) | |
4a6a3df4 AO |
10195 | {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH}, |
10196 | {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH}, | |
aa6975fb ILT |
10197 | #define OPTION_MSHARED (OPTION_MISC_BASE + 12) |
10198 | #define OPTION_MNO_SHARED (OPTION_MISC_BASE + 13) | |
10199 | {"mshared", no_argument, NULL, OPTION_MSHARED}, | |
10200 | {"mno-shared", no_argument, NULL, OPTION_MNO_SHARED}, | |
f9b4148d CD |
10201 | |
10202 | /* ELF-specific options. */ | |
156c2f8b | 10203 | #ifdef OBJ_ELF |
aa6975fb | 10204 | #define OPTION_ELF_BASE (OPTION_MISC_BASE + 14) |
156c2f8b | 10205 | #define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0) |
156c2f8b NC |
10206 | {"KPIC", no_argument, NULL, OPTION_CALL_SHARED}, |
10207 | {"call_shared", no_argument, NULL, OPTION_CALL_SHARED}, | |
ae948b86 | 10208 | #define OPTION_NON_SHARED (OPTION_ELF_BASE + 1) |
156c2f8b | 10209 | {"non_shared", no_argument, NULL, OPTION_NON_SHARED}, |
ae948b86 | 10210 | #define OPTION_XGOT (OPTION_ELF_BASE + 2) |
156c2f8b | 10211 | {"xgot", no_argument, NULL, OPTION_XGOT}, |
ae948b86 TS |
10212 | #define OPTION_MABI (OPTION_ELF_BASE + 3) |
10213 | {"mabi", required_argument, NULL, OPTION_MABI}, | |
10214 | #define OPTION_32 (OPTION_ELF_BASE + 4) | |
156c2f8b | 10215 | {"32", no_argument, NULL, OPTION_32}, |
ae948b86 | 10216 | #define OPTION_N32 (OPTION_ELF_BASE + 5) |
e013f690 | 10217 | {"n32", no_argument, NULL, OPTION_N32}, |
ae948b86 | 10218 | #define OPTION_64 (OPTION_ELF_BASE + 6) |
156c2f8b | 10219 | {"64", no_argument, NULL, OPTION_64}, |
ecb4347a DJ |
10220 | #define OPTION_MDEBUG (OPTION_ELF_BASE + 7) |
10221 | {"mdebug", no_argument, NULL, OPTION_MDEBUG}, | |
10222 | #define OPTION_NO_MDEBUG (OPTION_ELF_BASE + 8) | |
10223 | {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG}, | |
dcd410fe RO |
10224 | #define OPTION_PDR (OPTION_ELF_BASE + 9) |
10225 | {"mpdr", no_argument, NULL, OPTION_PDR}, | |
10226 | #define OPTION_NO_PDR (OPTION_ELF_BASE + 10) | |
10227 | {"mno-pdr", no_argument, NULL, OPTION_NO_PDR}, | |
ae948b86 | 10228 | #endif /* OBJ_ELF */ |
f9b4148d | 10229 | |
252b5132 RH |
10230 | {NULL, no_argument, NULL, 0} |
10231 | }; | |
156c2f8b | 10232 | size_t md_longopts_size = sizeof (md_longopts); |
252b5132 | 10233 | |
316f5878 RS |
10234 | /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to |
10235 | NEW_VALUE. Warn if another value was already specified. Note: | |
10236 | we have to defer parsing the -march and -mtune arguments in order | |
10237 | to handle 'from-abi' correctly, since the ABI might be specified | |
10238 | in a later argument. */ | |
10239 | ||
10240 | static void | |
17a2f251 | 10241 | mips_set_option_string (const char **string_ptr, const char *new_value) |
316f5878 RS |
10242 | { |
10243 | if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0) | |
10244 | as_warn (_("A different %s was already specified, is now %s"), | |
10245 | string_ptr == &mips_arch_string ? "-march" : "-mtune", | |
10246 | new_value); | |
10247 | ||
10248 | *string_ptr = new_value; | |
10249 | } | |
10250 | ||
252b5132 | 10251 | int |
17a2f251 | 10252 | md_parse_option (int c, char *arg) |
252b5132 RH |
10253 | { |
10254 | switch (c) | |
10255 | { | |
119d663a NC |
10256 | case OPTION_CONSTRUCT_FLOATS: |
10257 | mips_disable_float_construction = 0; | |
10258 | break; | |
bdaaa2e1 | 10259 | |
119d663a NC |
10260 | case OPTION_NO_CONSTRUCT_FLOATS: |
10261 | mips_disable_float_construction = 1; | |
10262 | break; | |
bdaaa2e1 | 10263 | |
252b5132 RH |
10264 | case OPTION_TRAP: |
10265 | mips_trap = 1; | |
10266 | break; | |
10267 | ||
10268 | case OPTION_BREAK: | |
10269 | mips_trap = 0; | |
10270 | break; | |
10271 | ||
10272 | case OPTION_EB: | |
10273 | target_big_endian = 1; | |
10274 | break; | |
10275 | ||
10276 | case OPTION_EL: | |
10277 | target_big_endian = 0; | |
10278 | break; | |
10279 | ||
10280 | case 'O': | |
10281 | if (arg && arg[1] == '0') | |
10282 | mips_optimize = 1; | |
10283 | else | |
10284 | mips_optimize = 2; | |
10285 | break; | |
10286 | ||
10287 | case 'g': | |
10288 | if (arg == NULL) | |
10289 | mips_debug = 2; | |
10290 | else | |
10291 | mips_debug = atoi (arg); | |
10292 | /* When the MIPS assembler sees -g or -g2, it does not do | |
10293 | optimizations which limit full symbolic debugging. We take | |
10294 | that to be equivalent to -O0. */ | |
10295 | if (mips_debug == 2) | |
10296 | mips_optimize = 1; | |
10297 | break; | |
10298 | ||
10299 | case OPTION_MIPS1: | |
316f5878 | 10300 | file_mips_isa = ISA_MIPS1; |
252b5132 RH |
10301 | break; |
10302 | ||
10303 | case OPTION_MIPS2: | |
316f5878 | 10304 | file_mips_isa = ISA_MIPS2; |
252b5132 RH |
10305 | break; |
10306 | ||
10307 | case OPTION_MIPS3: | |
316f5878 | 10308 | file_mips_isa = ISA_MIPS3; |
252b5132 RH |
10309 | break; |
10310 | ||
10311 | case OPTION_MIPS4: | |
316f5878 | 10312 | file_mips_isa = ISA_MIPS4; |
e7af610e NC |
10313 | break; |
10314 | ||
84ea6cf2 | 10315 | case OPTION_MIPS5: |
316f5878 | 10316 | file_mips_isa = ISA_MIPS5; |
84ea6cf2 NC |
10317 | break; |
10318 | ||
e7af610e | 10319 | case OPTION_MIPS32: |
316f5878 | 10320 | file_mips_isa = ISA_MIPS32; |
252b5132 RH |
10321 | break; |
10322 | ||
af7ee8bf CD |
10323 | case OPTION_MIPS32R2: |
10324 | file_mips_isa = ISA_MIPS32R2; | |
10325 | break; | |
10326 | ||
5f74bc13 CD |
10327 | case OPTION_MIPS64R2: |
10328 | file_mips_isa = ISA_MIPS64R2; | |
10329 | break; | |
10330 | ||
84ea6cf2 | 10331 | case OPTION_MIPS64: |
316f5878 | 10332 | file_mips_isa = ISA_MIPS64; |
84ea6cf2 NC |
10333 | break; |
10334 | ||
ec68c924 | 10335 | case OPTION_MTUNE: |
316f5878 RS |
10336 | mips_set_option_string (&mips_tune_string, arg); |
10337 | break; | |
ec68c924 | 10338 | |
316f5878 RS |
10339 | case OPTION_MARCH: |
10340 | mips_set_option_string (&mips_arch_string, arg); | |
252b5132 RH |
10341 | break; |
10342 | ||
10343 | case OPTION_M4650: | |
316f5878 RS |
10344 | mips_set_option_string (&mips_arch_string, "4650"); |
10345 | mips_set_option_string (&mips_tune_string, "4650"); | |
252b5132 RH |
10346 | break; |
10347 | ||
10348 | case OPTION_NO_M4650: | |
10349 | break; | |
10350 | ||
10351 | case OPTION_M4010: | |
316f5878 RS |
10352 | mips_set_option_string (&mips_arch_string, "4010"); |
10353 | mips_set_option_string (&mips_tune_string, "4010"); | |
252b5132 RH |
10354 | break; |
10355 | ||
10356 | case OPTION_NO_M4010: | |
10357 | break; | |
10358 | ||
10359 | case OPTION_M4100: | |
316f5878 RS |
10360 | mips_set_option_string (&mips_arch_string, "4100"); |
10361 | mips_set_option_string (&mips_tune_string, "4100"); | |
252b5132 RH |
10362 | break; |
10363 | ||
10364 | case OPTION_NO_M4100: | |
10365 | break; | |
10366 | ||
252b5132 | 10367 | case OPTION_M3900: |
316f5878 RS |
10368 | mips_set_option_string (&mips_arch_string, "3900"); |
10369 | mips_set_option_string (&mips_tune_string, "3900"); | |
252b5132 | 10370 | break; |
bdaaa2e1 | 10371 | |
252b5132 RH |
10372 | case OPTION_NO_M3900: |
10373 | break; | |
10374 | ||
deec1734 CD |
10375 | case OPTION_MDMX: |
10376 | mips_opts.ase_mdmx = 1; | |
10377 | break; | |
10378 | ||
10379 | case OPTION_NO_MDMX: | |
10380 | mips_opts.ase_mdmx = 0; | |
10381 | break; | |
10382 | ||
252b5132 RH |
10383 | case OPTION_MIPS16: |
10384 | mips_opts.mips16 = 1; | |
b34976b6 | 10385 | mips_no_prev_insn (FALSE); |
252b5132 RH |
10386 | break; |
10387 | ||
10388 | case OPTION_NO_MIPS16: | |
10389 | mips_opts.mips16 = 0; | |
b34976b6 | 10390 | mips_no_prev_insn (FALSE); |
252b5132 RH |
10391 | break; |
10392 | ||
1f25f5d3 CD |
10393 | case OPTION_MIPS3D: |
10394 | mips_opts.ase_mips3d = 1; | |
10395 | break; | |
10396 | ||
10397 | case OPTION_NO_MIPS3D: | |
10398 | mips_opts.ase_mips3d = 0; | |
10399 | break; | |
10400 | ||
d766e8ec RS |
10401 | case OPTION_FIX_VR4120: |
10402 | mips_fix_vr4120 = 1; | |
60b63b72 RS |
10403 | break; |
10404 | ||
d766e8ec RS |
10405 | case OPTION_NO_FIX_VR4120: |
10406 | mips_fix_vr4120 = 0; | |
60b63b72 RS |
10407 | break; |
10408 | ||
4a6a3df4 AO |
10409 | case OPTION_RELAX_BRANCH: |
10410 | mips_relax_branch = 1; | |
10411 | break; | |
10412 | ||
10413 | case OPTION_NO_RELAX_BRANCH: | |
10414 | mips_relax_branch = 0; | |
10415 | break; | |
10416 | ||
aa6975fb ILT |
10417 | case OPTION_MSHARED: |
10418 | mips_in_shared = TRUE; | |
10419 | break; | |
10420 | ||
10421 | case OPTION_MNO_SHARED: | |
10422 | mips_in_shared = FALSE; | |
10423 | break; | |
10424 | ||
0f074f60 | 10425 | #ifdef OBJ_ELF |
252b5132 RH |
10426 | /* When generating ELF code, we permit -KPIC and -call_shared to |
10427 | select SVR4_PIC, and -non_shared to select no PIC. This is | |
10428 | intended to be compatible with Irix 5. */ | |
10429 | case OPTION_CALL_SHARED: | |
10430 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
10431 | { | |
10432 | as_bad (_("-call_shared is supported only for ELF format")); | |
10433 | return 0; | |
10434 | } | |
10435 | mips_pic = SVR4_PIC; | |
143d77c5 | 10436 | mips_abicalls = TRUE; |
252b5132 RH |
10437 | if (g_switch_seen && g_switch_value != 0) |
10438 | { | |
10439 | as_bad (_("-G may not be used with SVR4 PIC code")); | |
10440 | return 0; | |
10441 | } | |
10442 | g_switch_value = 0; | |
10443 | break; | |
10444 | ||
10445 | case OPTION_NON_SHARED: | |
10446 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
10447 | { | |
10448 | as_bad (_("-non_shared is supported only for ELF format")); | |
10449 | return 0; | |
10450 | } | |
10451 | mips_pic = NO_PIC; | |
143d77c5 | 10452 | mips_abicalls = FALSE; |
252b5132 RH |
10453 | break; |
10454 | ||
10455 | /* The -xgot option tells the assembler to use 32 offsets when | |
10456 | accessing the got in SVR4_PIC mode. It is for Irix | |
10457 | compatibility. */ | |
10458 | case OPTION_XGOT: | |
10459 | mips_big_got = 1; | |
10460 | break; | |
0f074f60 | 10461 | #endif /* OBJ_ELF */ |
252b5132 RH |
10462 | |
10463 | case 'G': | |
3e722fb5 | 10464 | if (mips_pic == SVR4_PIC) |
252b5132 | 10465 | { |
3e722fb5 | 10466 | as_bad (_("-G may not be used with SVR4 PIC code")); |
252b5132 RH |
10467 | return 0; |
10468 | } | |
10469 | else | |
10470 | g_switch_value = atoi (arg); | |
10471 | g_switch_seen = 1; | |
10472 | break; | |
10473 | ||
0f074f60 | 10474 | #ifdef OBJ_ELF |
34ba82a8 TS |
10475 | /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32 |
10476 | and -mabi=64. */ | |
252b5132 | 10477 | case OPTION_32: |
34ba82a8 TS |
10478 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
10479 | { | |
10480 | as_bad (_("-32 is supported for ELF format only")); | |
10481 | return 0; | |
10482 | } | |
316f5878 | 10483 | mips_abi = O32_ABI; |
252b5132 RH |
10484 | break; |
10485 | ||
e013f690 | 10486 | case OPTION_N32: |
34ba82a8 TS |
10487 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
10488 | { | |
10489 | as_bad (_("-n32 is supported for ELF format only")); | |
10490 | return 0; | |
10491 | } | |
316f5878 | 10492 | mips_abi = N32_ABI; |
e013f690 | 10493 | break; |
252b5132 | 10494 | |
e013f690 | 10495 | case OPTION_64: |
34ba82a8 TS |
10496 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
10497 | { | |
10498 | as_bad (_("-64 is supported for ELF format only")); | |
10499 | return 0; | |
10500 | } | |
316f5878 | 10501 | mips_abi = N64_ABI; |
e013f690 TS |
10502 | if (! support_64bit_objects()) |
10503 | as_fatal (_("No compiled in support for 64 bit object file format")); | |
252b5132 | 10504 | break; |
ae948b86 | 10505 | #endif /* OBJ_ELF */ |
252b5132 | 10506 | |
c97ef257 | 10507 | case OPTION_GP32: |
a325df1d | 10508 | file_mips_gp32 = 1; |
c97ef257 AH |
10509 | break; |
10510 | ||
10511 | case OPTION_GP64: | |
a325df1d | 10512 | file_mips_gp32 = 0; |
c97ef257 | 10513 | break; |
252b5132 | 10514 | |
ca4e0257 | 10515 | case OPTION_FP32: |
a325df1d | 10516 | file_mips_fp32 = 1; |
316f5878 RS |
10517 | break; |
10518 | ||
10519 | case OPTION_FP64: | |
10520 | file_mips_fp32 = 0; | |
ca4e0257 RS |
10521 | break; |
10522 | ||
ae948b86 | 10523 | #ifdef OBJ_ELF |
252b5132 | 10524 | case OPTION_MABI: |
34ba82a8 TS |
10525 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
10526 | { | |
10527 | as_bad (_("-mabi is supported for ELF format only")); | |
10528 | return 0; | |
10529 | } | |
e013f690 | 10530 | if (strcmp (arg, "32") == 0) |
316f5878 | 10531 | mips_abi = O32_ABI; |
e013f690 | 10532 | else if (strcmp (arg, "o64") == 0) |
316f5878 | 10533 | mips_abi = O64_ABI; |
e013f690 | 10534 | else if (strcmp (arg, "n32") == 0) |
316f5878 | 10535 | mips_abi = N32_ABI; |
e013f690 TS |
10536 | else if (strcmp (arg, "64") == 0) |
10537 | { | |
316f5878 | 10538 | mips_abi = N64_ABI; |
e013f690 TS |
10539 | if (! support_64bit_objects()) |
10540 | as_fatal (_("No compiled in support for 64 bit object file " | |
10541 | "format")); | |
10542 | } | |
10543 | else if (strcmp (arg, "eabi") == 0) | |
316f5878 | 10544 | mips_abi = EABI_ABI; |
e013f690 | 10545 | else |
da0e507f TS |
10546 | { |
10547 | as_fatal (_("invalid abi -mabi=%s"), arg); | |
10548 | return 0; | |
10549 | } | |
252b5132 | 10550 | break; |
e013f690 | 10551 | #endif /* OBJ_ELF */ |
252b5132 | 10552 | |
6b76fefe | 10553 | case OPTION_M7000_HILO_FIX: |
b34976b6 | 10554 | mips_7000_hilo_fix = TRUE; |
6b76fefe CM |
10555 | break; |
10556 | ||
9ee72ff1 | 10557 | case OPTION_MNO_7000_HILO_FIX: |
b34976b6 | 10558 | mips_7000_hilo_fix = FALSE; |
6b76fefe CM |
10559 | break; |
10560 | ||
ecb4347a DJ |
10561 | #ifdef OBJ_ELF |
10562 | case OPTION_MDEBUG: | |
b34976b6 | 10563 | mips_flag_mdebug = TRUE; |
ecb4347a DJ |
10564 | break; |
10565 | ||
10566 | case OPTION_NO_MDEBUG: | |
b34976b6 | 10567 | mips_flag_mdebug = FALSE; |
ecb4347a | 10568 | break; |
dcd410fe RO |
10569 | |
10570 | case OPTION_PDR: | |
10571 | mips_flag_pdr = TRUE; | |
10572 | break; | |
10573 | ||
10574 | case OPTION_NO_PDR: | |
10575 | mips_flag_pdr = FALSE; | |
10576 | break; | |
ecb4347a DJ |
10577 | #endif /* OBJ_ELF */ |
10578 | ||
252b5132 RH |
10579 | default: |
10580 | return 0; | |
10581 | } | |
10582 | ||
10583 | return 1; | |
10584 | } | |
316f5878 RS |
10585 | \f |
10586 | /* Set up globals to generate code for the ISA or processor | |
10587 | described by INFO. */ | |
252b5132 | 10588 | |
252b5132 | 10589 | static void |
17a2f251 | 10590 | mips_set_architecture (const struct mips_cpu_info *info) |
252b5132 | 10591 | { |
316f5878 | 10592 | if (info != 0) |
252b5132 | 10593 | { |
fef14a42 TS |
10594 | file_mips_arch = info->cpu; |
10595 | mips_opts.arch = info->cpu; | |
316f5878 | 10596 | mips_opts.isa = info->isa; |
252b5132 | 10597 | } |
252b5132 RH |
10598 | } |
10599 | ||
252b5132 | 10600 | |
316f5878 | 10601 | /* Likewise for tuning. */ |
252b5132 | 10602 | |
316f5878 | 10603 | static void |
17a2f251 | 10604 | mips_set_tune (const struct mips_cpu_info *info) |
316f5878 RS |
10605 | { |
10606 | if (info != 0) | |
fef14a42 | 10607 | mips_tune = info->cpu; |
316f5878 | 10608 | } |
80cc45a5 | 10609 | |
34ba82a8 | 10610 | |
252b5132 | 10611 | void |
17a2f251 | 10612 | mips_after_parse_args (void) |
e9670677 | 10613 | { |
fef14a42 TS |
10614 | const struct mips_cpu_info *arch_info = 0; |
10615 | const struct mips_cpu_info *tune_info = 0; | |
10616 | ||
e9670677 MR |
10617 | /* GP relative stuff not working for PE */ |
10618 | if (strncmp (TARGET_OS, "pe", 2) == 0 | |
10619 | && g_switch_value != 0) | |
10620 | { | |
10621 | if (g_switch_seen) | |
10622 | as_bad (_("-G not supported in this configuration.")); | |
10623 | g_switch_value = 0; | |
10624 | } | |
10625 | ||
cac012d6 AO |
10626 | if (mips_abi == NO_ABI) |
10627 | mips_abi = MIPS_DEFAULT_ABI; | |
10628 | ||
22923709 RS |
10629 | /* The following code determines the architecture and register size. |
10630 | Similar code was added to GCC 3.3 (see override_options() in | |
10631 | config/mips/mips.c). The GAS and GCC code should be kept in sync | |
10632 | as much as possible. */ | |
e9670677 | 10633 | |
316f5878 | 10634 | if (mips_arch_string != 0) |
fef14a42 | 10635 | arch_info = mips_parse_cpu ("-march", mips_arch_string); |
e9670677 | 10636 | |
316f5878 | 10637 | if (file_mips_isa != ISA_UNKNOWN) |
e9670677 | 10638 | { |
316f5878 | 10639 | /* Handle -mipsN. At this point, file_mips_isa contains the |
fef14a42 | 10640 | ISA level specified by -mipsN, while arch_info->isa contains |
316f5878 | 10641 | the -march selection (if any). */ |
fef14a42 | 10642 | if (arch_info != 0) |
e9670677 | 10643 | { |
316f5878 RS |
10644 | /* -march takes precedence over -mipsN, since it is more descriptive. |
10645 | There's no harm in specifying both as long as the ISA levels | |
10646 | are the same. */ | |
fef14a42 | 10647 | if (file_mips_isa != arch_info->isa) |
316f5878 RS |
10648 | as_bad (_("-%s conflicts with the other architecture options, which imply -%s"), |
10649 | mips_cpu_info_from_isa (file_mips_isa)->name, | |
fef14a42 | 10650 | mips_cpu_info_from_isa (arch_info->isa)->name); |
e9670677 | 10651 | } |
316f5878 | 10652 | else |
fef14a42 | 10653 | arch_info = mips_cpu_info_from_isa (file_mips_isa); |
e9670677 MR |
10654 | } |
10655 | ||
fef14a42 TS |
10656 | if (arch_info == 0) |
10657 | arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT); | |
e9670677 | 10658 | |
fef14a42 | 10659 | if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa)) |
316f5878 | 10660 | as_bad ("-march=%s is not compatible with the selected ABI", |
fef14a42 TS |
10661 | arch_info->name); |
10662 | ||
10663 | mips_set_architecture (arch_info); | |
10664 | ||
10665 | /* Optimize for file_mips_arch, unless -mtune selects a different processor. */ | |
10666 | if (mips_tune_string != 0) | |
10667 | tune_info = mips_parse_cpu ("-mtune", mips_tune_string); | |
e9670677 | 10668 | |
fef14a42 TS |
10669 | if (tune_info == 0) |
10670 | mips_set_tune (arch_info); | |
10671 | else | |
10672 | mips_set_tune (tune_info); | |
e9670677 | 10673 | |
316f5878 | 10674 | if (file_mips_gp32 >= 0) |
e9670677 | 10675 | { |
316f5878 RS |
10676 | /* The user specified the size of the integer registers. Make sure |
10677 | it agrees with the ABI and ISA. */ | |
10678 | if (file_mips_gp32 == 0 && !ISA_HAS_64BIT_REGS (mips_opts.isa)) | |
10679 | as_bad (_("-mgp64 used with a 32-bit processor")); | |
10680 | else if (file_mips_gp32 == 1 && ABI_NEEDS_64BIT_REGS (mips_abi)) | |
10681 | as_bad (_("-mgp32 used with a 64-bit ABI")); | |
10682 | else if (file_mips_gp32 == 0 && ABI_NEEDS_32BIT_REGS (mips_abi)) | |
10683 | as_bad (_("-mgp64 used with a 32-bit ABI")); | |
e9670677 MR |
10684 | } |
10685 | else | |
10686 | { | |
316f5878 RS |
10687 | /* Infer the integer register size from the ABI and processor. |
10688 | Restrict ourselves to 32-bit registers if that's all the | |
10689 | processor has, or if the ABI cannot handle 64-bit registers. */ | |
10690 | file_mips_gp32 = (ABI_NEEDS_32BIT_REGS (mips_abi) | |
10691 | || !ISA_HAS_64BIT_REGS (mips_opts.isa)); | |
e9670677 MR |
10692 | } |
10693 | ||
316f5878 RS |
10694 | /* ??? GAS treats single-float processors as though they had 64-bit |
10695 | float registers (although it complains when double-precision | |
10696 | instructions are used). As things stand, saying they have 32-bit | |
10697 | registers would lead to spurious "register must be even" messages. | |
10698 | So here we assume float registers are always the same size as | |
10699 | integer ones, unless the user says otherwise. */ | |
10700 | if (file_mips_fp32 < 0) | |
10701 | file_mips_fp32 = file_mips_gp32; | |
e9670677 | 10702 | |
316f5878 | 10703 | /* End of GCC-shared inference code. */ |
e9670677 | 10704 | |
17a2f251 TS |
10705 | /* This flag is set when we have a 64-bit capable CPU but use only |
10706 | 32-bit wide registers. Note that EABI does not use it. */ | |
10707 | if (ISA_HAS_64BIT_REGS (mips_opts.isa) | |
10708 | && ((mips_abi == NO_ABI && file_mips_gp32 == 1) | |
10709 | || mips_abi == O32_ABI)) | |
316f5878 | 10710 | mips_32bitmode = 1; |
e9670677 MR |
10711 | |
10712 | if (mips_opts.isa == ISA_MIPS1 && mips_trap) | |
10713 | as_bad (_("trap exception not supported at ISA 1")); | |
10714 | ||
e9670677 MR |
10715 | /* If the selected architecture includes support for ASEs, enable |
10716 | generation of code for them. */ | |
a4672219 | 10717 | if (mips_opts.mips16 == -1) |
fef14a42 | 10718 | mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_arch)) ? 1 : 0; |
ffdefa66 | 10719 | if (mips_opts.ase_mips3d == -1) |
fef14a42 | 10720 | mips_opts.ase_mips3d = (CPU_HAS_MIPS3D (file_mips_arch)) ? 1 : 0; |
ffdefa66 | 10721 | if (mips_opts.ase_mdmx == -1) |
fef14a42 | 10722 | mips_opts.ase_mdmx = (CPU_HAS_MDMX (file_mips_arch)) ? 1 : 0; |
e9670677 | 10723 | |
e9670677 | 10724 | file_mips_isa = mips_opts.isa; |
a4672219 | 10725 | file_ase_mips16 = mips_opts.mips16; |
e9670677 MR |
10726 | file_ase_mips3d = mips_opts.ase_mips3d; |
10727 | file_ase_mdmx = mips_opts.ase_mdmx; | |
10728 | mips_opts.gp32 = file_mips_gp32; | |
10729 | mips_opts.fp32 = file_mips_fp32; | |
10730 | ||
ecb4347a DJ |
10731 | if (mips_flag_mdebug < 0) |
10732 | { | |
10733 | #ifdef OBJ_MAYBE_ECOFF | |
10734 | if (OUTPUT_FLAVOR == bfd_target_ecoff_flavour) | |
10735 | mips_flag_mdebug = 1; | |
10736 | else | |
10737 | #endif /* OBJ_MAYBE_ECOFF */ | |
10738 | mips_flag_mdebug = 0; | |
10739 | } | |
e9670677 MR |
10740 | } |
10741 | \f | |
10742 | void | |
17a2f251 | 10743 | mips_init_after_args (void) |
252b5132 RH |
10744 | { |
10745 | /* initialize opcodes */ | |
10746 | bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes; | |
beae10d5 | 10747 | mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes; |
252b5132 RH |
10748 | } |
10749 | ||
10750 | long | |
17a2f251 | 10751 | md_pcrel_from (fixS *fixP) |
252b5132 | 10752 | { |
a7ebbfdf TS |
10753 | valueT addr = fixP->fx_where + fixP->fx_frag->fr_address; |
10754 | switch (fixP->fx_r_type) | |
10755 | { | |
10756 | case BFD_RELOC_16_PCREL_S2: | |
10757 | case BFD_RELOC_MIPS_JMP: | |
10758 | /* Return the address of the delay slot. */ | |
10759 | return addr + 4; | |
10760 | default: | |
10761 | return addr; | |
10762 | } | |
252b5132 RH |
10763 | } |
10764 | ||
252b5132 RH |
10765 | /* This is called before the symbol table is processed. In order to |
10766 | work with gcc when using mips-tfile, we must keep all local labels. | |
10767 | However, in other cases, we want to discard them. If we were | |
10768 | called with -g, but we didn't see any debugging information, it may | |
10769 | mean that gcc is smuggling debugging information through to | |
10770 | mips-tfile, in which case we must generate all local labels. */ | |
10771 | ||
10772 | void | |
17a2f251 | 10773 | mips_frob_file_before_adjust (void) |
252b5132 RH |
10774 | { |
10775 | #ifndef NO_ECOFF_DEBUGGING | |
10776 | if (ECOFF_DEBUGGING | |
10777 | && mips_debug != 0 | |
10778 | && ! ecoff_debugging_seen) | |
10779 | flag_keep_locals = 1; | |
10780 | #endif | |
10781 | } | |
10782 | ||
3b91255e RS |
10783 | /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede |
10784 | the corresponding LO16 reloc. This is called before md_apply_fix3 and | |
10785 | tc_gen_reloc. Unmatched relocs can only be generated by use of explicit | |
10786 | relocation operators. | |
10787 | ||
10788 | For our purposes, a %lo() expression matches a %got() or %hi() | |
10789 | expression if: | |
10790 | ||
10791 | (a) it refers to the same symbol; and | |
10792 | (b) the offset applied in the %lo() expression is no lower than | |
10793 | the offset applied in the %got() or %hi(). | |
10794 | ||
10795 | (b) allows us to cope with code like: | |
10796 | ||
10797 | lui $4,%hi(foo) | |
10798 | lh $4,%lo(foo+2)($4) | |
10799 | ||
10800 | ...which is legal on RELA targets, and has a well-defined behaviour | |
10801 | if the user knows that adding 2 to "foo" will not induce a carry to | |
10802 | the high 16 bits. | |
10803 | ||
10804 | When several %lo()s match a particular %got() or %hi(), we use the | |
10805 | following rules to distinguish them: | |
10806 | ||
10807 | (1) %lo()s with smaller offsets are a better match than %lo()s with | |
10808 | higher offsets. | |
10809 | ||
10810 | (2) %lo()s with no matching %got() or %hi() are better than those | |
10811 | that already have a matching %got() or %hi(). | |
10812 | ||
10813 | (3) later %lo()s are better than earlier %lo()s. | |
10814 | ||
10815 | These rules are applied in order. | |
10816 | ||
10817 | (1) means, among other things, that %lo()s with identical offsets are | |
10818 | chosen if they exist. | |
10819 | ||
10820 | (2) means that we won't associate several high-part relocations with | |
10821 | the same low-part relocation unless there's no alternative. Having | |
10822 | several high parts for the same low part is a GNU extension; this rule | |
10823 | allows careful users to avoid it. | |
10824 | ||
10825 | (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order, | |
10826 | with the last high-part relocation being at the front of the list. | |
10827 | It therefore makes sense to choose the last matching low-part | |
10828 | relocation, all other things being equal. It's also easier | |
10829 | to code that way. */ | |
252b5132 RH |
10830 | |
10831 | void | |
17a2f251 | 10832 | mips_frob_file (void) |
252b5132 RH |
10833 | { |
10834 | struct mips_hi_fixup *l; | |
10835 | ||
10836 | for (l = mips_hi_fixup_list; l != NULL; l = l->next) | |
10837 | { | |
10838 | segment_info_type *seginfo; | |
3b91255e RS |
10839 | bfd_boolean matched_lo_p; |
10840 | fixS **hi_pos, **lo_pos, **pos; | |
252b5132 | 10841 | |
5919d012 | 10842 | assert (reloc_needs_lo_p (l->fixp->fx_r_type)); |
252b5132 | 10843 | |
5919d012 RS |
10844 | /* If a GOT16 relocation turns out to be against a global symbol, |
10845 | there isn't supposed to be a matching LO. */ | |
10846 | if (l->fixp->fx_r_type == BFD_RELOC_MIPS_GOT16 | |
10847 | && !pic_need_relax (l->fixp->fx_addsy, l->seg)) | |
10848 | continue; | |
10849 | ||
10850 | /* Check quickly whether the next fixup happens to be a matching %lo. */ | |
10851 | if (fixup_has_matching_lo_p (l->fixp)) | |
252b5132 RH |
10852 | continue; |
10853 | ||
252b5132 | 10854 | seginfo = seg_info (l->seg); |
252b5132 | 10855 | |
3b91255e RS |
10856 | /* Set HI_POS to the position of this relocation in the chain. |
10857 | Set LO_POS to the position of the chosen low-part relocation. | |
10858 | MATCHED_LO_P is true on entry to the loop if *POS is a low-part | |
10859 | relocation that matches an immediately-preceding high-part | |
10860 | relocation. */ | |
10861 | hi_pos = NULL; | |
10862 | lo_pos = NULL; | |
10863 | matched_lo_p = FALSE; | |
10864 | for (pos = &seginfo->fix_root; *pos != NULL; pos = &(*pos)->fx_next) | |
10865 | { | |
10866 | if (*pos == l->fixp) | |
10867 | hi_pos = pos; | |
10868 | ||
10869 | if ((*pos)->fx_r_type == BFD_RELOC_LO16 | |
10870 | && (*pos)->fx_addsy == l->fixp->fx_addsy | |
10871 | && (*pos)->fx_offset >= l->fixp->fx_offset | |
10872 | && (lo_pos == NULL | |
10873 | || (*pos)->fx_offset < (*lo_pos)->fx_offset | |
10874 | || (!matched_lo_p | |
10875 | && (*pos)->fx_offset == (*lo_pos)->fx_offset))) | |
10876 | lo_pos = pos; | |
10877 | ||
10878 | matched_lo_p = (reloc_needs_lo_p ((*pos)->fx_r_type) | |
10879 | && fixup_has_matching_lo_p (*pos)); | |
10880 | } | |
10881 | ||
10882 | /* If we found a match, remove the high-part relocation from its | |
10883 | current position and insert it before the low-part relocation. | |
10884 | Make the offsets match so that fixup_has_matching_lo_p() | |
10885 | will return true. | |
10886 | ||
10887 | We don't warn about unmatched high-part relocations since some | |
10888 | versions of gcc have been known to emit dead "lui ...%hi(...)" | |
10889 | instructions. */ | |
10890 | if (lo_pos != NULL) | |
10891 | { | |
10892 | l->fixp->fx_offset = (*lo_pos)->fx_offset; | |
10893 | if (l->fixp->fx_next != *lo_pos) | |
252b5132 | 10894 | { |
3b91255e RS |
10895 | *hi_pos = l->fixp->fx_next; |
10896 | l->fixp->fx_next = *lo_pos; | |
10897 | *lo_pos = l->fixp; | |
252b5132 | 10898 | } |
252b5132 RH |
10899 | } |
10900 | } | |
10901 | } | |
10902 | ||
3e722fb5 | 10903 | /* We may have combined relocations without symbols in the N32/N64 ABI. |
f6688943 | 10904 | We have to prevent gas from dropping them. */ |
252b5132 | 10905 | |
252b5132 | 10906 | int |
17a2f251 | 10907 | mips_force_relocation (fixS *fixp) |
252b5132 | 10908 | { |
ae6063d4 | 10909 | if (generic_force_reloc (fixp)) |
252b5132 RH |
10910 | return 1; |
10911 | ||
f6688943 TS |
10912 | if (HAVE_NEWABI |
10913 | && S_GET_SEGMENT (fixp->fx_addsy) == bfd_abs_section_ptr | |
10914 | && (fixp->fx_r_type == BFD_RELOC_MIPS_SUB | |
10915 | || fixp->fx_r_type == BFD_RELOC_HI16_S | |
10916 | || fixp->fx_r_type == BFD_RELOC_LO16)) | |
10917 | return 1; | |
10918 | ||
3e722fb5 | 10919 | return 0; |
252b5132 RH |
10920 | } |
10921 | ||
45f8dfe8 AO |
10922 | /* This hook is called before a fix is simplified. We don't really |
10923 | decide whether to skip a fix here. Rather, we turn global symbols | |
10924 | used as branch targets into local symbols, such that they undergo | |
10925 | simplification. We can only do this if the symbol is defined and | |
10926 | it is in the same section as the branch. If this doesn't hold, we | |
10927 | emit a better error message than just saying the relocation is not | |
10928 | valid for the selected object format. | |
10929 | ||
10930 | FIXP is the fix-up we're going to try to simplify, SEG is the | |
10931 | segment in which the fix up occurs. The return value should be | |
10932 | non-zero to indicate the fix-up is valid for further | |
10933 | simplifications. */ | |
10934 | ||
10935 | int | |
17a2f251 | 10936 | mips_validate_fix (struct fix *fixP, asection *seg) |
45f8dfe8 AO |
10937 | { |
10938 | /* There's a lot of discussion on whether it should be possible to | |
10939 | use R_MIPS_PC16 to represent branch relocations. The outcome | |
10940 | seems to be that it can, but gas/bfd are very broken in creating | |
10941 | RELA relocations for this, so for now we only accept branches to | |
10942 | symbols in the same section. Anything else is of dubious value, | |
10943 | since there's no guarantee that at link time the symbol would be | |
10944 | in range. Even for branches to local symbols this is arguably | |
10945 | wrong, since it we assume the symbol is not going to be | |
10946 | overridden, which should be possible per ELF library semantics, | |
10947 | but then, there isn't a dynamic relocation that could be used to | |
10948 | this effect, and the target would likely be out of range as well. | |
10949 | ||
10950 | Unfortunately, it seems that there is too much code out there | |
10951 | that relies on branches to symbols that are global to be resolved | |
10952 | as if they were local, like the IRIX tools do, so we do it as | |
10953 | well, but with a warning so that people are reminded to fix their | |
10954 | code. If we ever get back to using R_MIPS_PC16 for branch | |
10955 | targets, this entire block should go away (and probably the | |
10956 | whole function). */ | |
10957 | ||
10958 | if (fixP->fx_r_type == BFD_RELOC_16_PCREL_S2 | |
3e722fb5 CD |
10959 | && ((OUTPUT_FLAVOR == bfd_target_ecoff_flavour |
10960 | || OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
45f8dfe8 AO |
10961 | || bfd_reloc_type_lookup (stdoutput, BFD_RELOC_16_PCREL_S2) == NULL) |
10962 | && fixP->fx_addsy) | |
10963 | { | |
10964 | if (! S_IS_DEFINED (fixP->fx_addsy)) | |
10965 | { | |
10966 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
10967 | _("Cannot branch to undefined symbol.")); | |
10968 | /* Avoid any further errors about this fixup. */ | |
10969 | fixP->fx_done = 1; | |
10970 | } | |
10971 | else if (S_GET_SEGMENT (fixP->fx_addsy) != seg) | |
10972 | { | |
10973 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
10974 | _("Cannot branch to symbol in another section.")); | |
10975 | fixP->fx_done = 1; | |
10976 | } | |
10977 | else if (S_IS_EXTERNAL (fixP->fx_addsy)) | |
10978 | { | |
10979 | symbolS *sym = fixP->fx_addsy; | |
10980 | ||
115695a8 CD |
10981 | if (mips_pic == SVR4_PIC) |
10982 | as_warn_where (fixP->fx_file, fixP->fx_line, | |
10983 | _("Pretending global symbol used as branch target is local.")); | |
45f8dfe8 AO |
10984 | |
10985 | fixP->fx_addsy = symbol_create (S_GET_NAME (sym), | |
10986 | S_GET_SEGMENT (sym), | |
10987 | S_GET_VALUE (sym), | |
10988 | symbol_get_frag (sym)); | |
10989 | copy_symbol_attributes (fixP->fx_addsy, sym); | |
10990 | S_CLEAR_EXTERNAL (fixP->fx_addsy); | |
10991 | assert (symbol_resolved_p (sym)); | |
10992 | symbol_mark_resolved (fixP->fx_addsy); | |
10993 | } | |
10994 | } | |
10995 | ||
10996 | return 1; | |
10997 | } | |
10998 | ||
252b5132 RH |
10999 | /* Apply a fixup to the object file. */ |
11000 | ||
94f592af | 11001 | void |
17a2f251 | 11002 | md_apply_fix3 (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) |
252b5132 | 11003 | { |
874e8986 | 11004 | bfd_byte *buf; |
98aa84af | 11005 | long insn; |
a7ebbfdf | 11006 | reloc_howto_type *howto; |
252b5132 | 11007 | |
a7ebbfdf TS |
11008 | /* We ignore generic BFD relocations we don't know about. */ |
11009 | howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type); | |
11010 | if (! howto) | |
11011 | return; | |
65551fa4 | 11012 | |
252b5132 RH |
11013 | assert (fixP->fx_size == 4 |
11014 | || fixP->fx_r_type == BFD_RELOC_16 | |
11015 | || fixP->fx_r_type == BFD_RELOC_64 | |
f6688943 TS |
11016 | || fixP->fx_r_type == BFD_RELOC_CTOR |
11017 | || fixP->fx_r_type == BFD_RELOC_MIPS_SUB | |
252b5132 | 11018 | || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
a7ebbfdf | 11019 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY); |
252b5132 | 11020 | |
a7ebbfdf | 11021 | buf = (bfd_byte *) (fixP->fx_frag->fr_literal + fixP->fx_where); |
252b5132 | 11022 | |
3e722fb5 | 11023 | assert (! fixP->fx_pcrel); |
b1dca8ee RS |
11024 | |
11025 | /* Don't treat parts of a composite relocation as done. There are two | |
11026 | reasons for this: | |
11027 | ||
11028 | (1) The second and third parts will be against 0 (RSS_UNDEF) but | |
11029 | should nevertheless be emitted if the first part is. | |
11030 | ||
11031 | (2) In normal usage, composite relocations are never assembly-time | |
11032 | constants. The easiest way of dealing with the pathological | |
11033 | exceptions is to generate a relocation against STN_UNDEF and | |
11034 | leave everything up to the linker. */ | |
11035 | if (fixP->fx_addsy == NULL && fixP->fx_tcbit == 0) | |
252b5132 RH |
11036 | fixP->fx_done = 1; |
11037 | ||
11038 | switch (fixP->fx_r_type) | |
11039 | { | |
11040 | case BFD_RELOC_MIPS_JMP: | |
e369bcce TS |
11041 | case BFD_RELOC_MIPS_SHIFT5: |
11042 | case BFD_RELOC_MIPS_SHIFT6: | |
11043 | case BFD_RELOC_MIPS_GOT_DISP: | |
11044 | case BFD_RELOC_MIPS_GOT_PAGE: | |
11045 | case BFD_RELOC_MIPS_GOT_OFST: | |
11046 | case BFD_RELOC_MIPS_SUB: | |
11047 | case BFD_RELOC_MIPS_INSERT_A: | |
11048 | case BFD_RELOC_MIPS_INSERT_B: | |
11049 | case BFD_RELOC_MIPS_DELETE: | |
11050 | case BFD_RELOC_MIPS_HIGHEST: | |
11051 | case BFD_RELOC_MIPS_HIGHER: | |
11052 | case BFD_RELOC_MIPS_SCN_DISP: | |
11053 | case BFD_RELOC_MIPS_REL16: | |
11054 | case BFD_RELOC_MIPS_RELGOT: | |
11055 | case BFD_RELOC_MIPS_JALR: | |
252b5132 RH |
11056 | case BFD_RELOC_HI16: |
11057 | case BFD_RELOC_HI16_S: | |
cdf6fd85 | 11058 | case BFD_RELOC_GPREL16: |
252b5132 RH |
11059 | case BFD_RELOC_MIPS_LITERAL: |
11060 | case BFD_RELOC_MIPS_CALL16: | |
11061 | case BFD_RELOC_MIPS_GOT16: | |
cdf6fd85 | 11062 | case BFD_RELOC_GPREL32: |
252b5132 RH |
11063 | case BFD_RELOC_MIPS_GOT_HI16: |
11064 | case BFD_RELOC_MIPS_GOT_LO16: | |
11065 | case BFD_RELOC_MIPS_CALL_HI16: | |
11066 | case BFD_RELOC_MIPS_CALL_LO16: | |
11067 | case BFD_RELOC_MIPS16_GPREL: | |
d6f16593 MR |
11068 | case BFD_RELOC_MIPS16_HI16: |
11069 | case BFD_RELOC_MIPS16_HI16_S: | |
3e722fb5 | 11070 | assert (! fixP->fx_pcrel); |
252b5132 RH |
11071 | /* Nothing needed to do. The value comes from the reloc entry */ |
11072 | break; | |
11073 | ||
11074 | case BFD_RELOC_MIPS16_JMP: | |
11075 | /* We currently always generate a reloc against a symbol, which | |
11076 | means that we don't want an addend even if the symbol is | |
11077 | defined. */ | |
a7ebbfdf | 11078 | *valP = 0; |
252b5132 RH |
11079 | break; |
11080 | ||
252b5132 RH |
11081 | case BFD_RELOC_64: |
11082 | /* This is handled like BFD_RELOC_32, but we output a sign | |
11083 | extended value if we are only 32 bits. */ | |
3e722fb5 | 11084 | if (fixP->fx_done) |
252b5132 RH |
11085 | { |
11086 | if (8 <= sizeof (valueT)) | |
a7ebbfdf | 11087 | md_number_to_chars (buf, *valP, 8); |
252b5132 RH |
11088 | else |
11089 | { | |
a7ebbfdf | 11090 | valueT hiv; |
252b5132 | 11091 | |
a7ebbfdf | 11092 | if ((*valP & 0x80000000) != 0) |
252b5132 RH |
11093 | hiv = 0xffffffff; |
11094 | else | |
11095 | hiv = 0; | |
a7ebbfdf TS |
11096 | md_number_to_chars ((char *)(buf + target_big_endian ? 4 : 0), |
11097 | *valP, 4); | |
11098 | md_number_to_chars ((char *)(buf + target_big_endian ? 0 : 4), | |
11099 | hiv, 4); | |
252b5132 RH |
11100 | } |
11101 | } | |
11102 | break; | |
11103 | ||
056350c6 | 11104 | case BFD_RELOC_RVA: |
252b5132 RH |
11105 | case BFD_RELOC_32: |
11106 | /* If we are deleting this reloc entry, we must fill in the | |
11107 | value now. This can happen if we have a .word which is not | |
3e722fb5 CD |
11108 | resolved when it appears but is later defined. */ |
11109 | if (fixP->fx_done) | |
a7ebbfdf | 11110 | md_number_to_chars (buf, *valP, 4); |
252b5132 RH |
11111 | break; |
11112 | ||
11113 | case BFD_RELOC_16: | |
11114 | /* If we are deleting this reloc entry, we must fill in the | |
11115 | value now. */ | |
252b5132 | 11116 | if (fixP->fx_done) |
a7ebbfdf | 11117 | md_number_to_chars (buf, *valP, 2); |
252b5132 RH |
11118 | break; |
11119 | ||
11120 | case BFD_RELOC_LO16: | |
d6f16593 | 11121 | case BFD_RELOC_MIPS16_LO16: |
3e722fb5 CD |
11122 | /* FIXME: Now that embedded-PIC is gone, some of this code/comment |
11123 | may be safe to remove, but if so it's not obvious. */ | |
252b5132 RH |
11124 | /* When handling an embedded PIC switch statement, we can wind |
11125 | up deleting a LO16 reloc. See the 'o' case in mips_ip. */ | |
11126 | if (fixP->fx_done) | |
11127 | { | |
a7ebbfdf | 11128 | if (*valP + 0x8000 > 0xffff) |
252b5132 RH |
11129 | as_bad_where (fixP->fx_file, fixP->fx_line, |
11130 | _("relocation overflow")); | |
252b5132 RH |
11131 | if (target_big_endian) |
11132 | buf += 2; | |
17a2f251 | 11133 | md_number_to_chars (buf, *valP, 2); |
252b5132 RH |
11134 | } |
11135 | break; | |
11136 | ||
11137 | case BFD_RELOC_16_PCREL_S2: | |
a7ebbfdf | 11138 | if ((*valP & 0x3) != 0) |
cb56d3d3 | 11139 | as_bad_where (fixP->fx_file, fixP->fx_line, |
a7ebbfdf | 11140 | _("Branch to odd address (%lx)"), (long) *valP); |
cb56d3d3 | 11141 | |
252b5132 RH |
11142 | /* |
11143 | * We need to save the bits in the instruction since fixup_segment() | |
11144 | * might be deleting the relocation entry (i.e., a branch within | |
11145 | * the current segment). | |
11146 | */ | |
a7ebbfdf | 11147 | if (! fixP->fx_done) |
bb2d6cd7 | 11148 | break; |
252b5132 RH |
11149 | |
11150 | /* update old instruction data */ | |
252b5132 RH |
11151 | if (target_big_endian) |
11152 | insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3]; | |
11153 | else | |
11154 | insn = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0]; | |
11155 | ||
a7ebbfdf TS |
11156 | if (*valP + 0x20000 <= 0x3ffff) |
11157 | { | |
11158 | insn |= (*valP >> 2) & 0xffff; | |
17a2f251 | 11159 | md_number_to_chars (buf, insn, 4); |
a7ebbfdf TS |
11160 | } |
11161 | else if (mips_pic == NO_PIC | |
11162 | && fixP->fx_done | |
11163 | && fixP->fx_frag->fr_address >= text_section->vma | |
11164 | && (fixP->fx_frag->fr_address | |
587aac4e | 11165 | < text_section->vma + bfd_get_section_size (text_section)) |
a7ebbfdf TS |
11166 | && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */ |
11167 | || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */ | |
11168 | || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */ | |
252b5132 RH |
11169 | { |
11170 | /* The branch offset is too large. If this is an | |
11171 | unconditional branch, and we are not generating PIC code, | |
11172 | we can convert it to an absolute jump instruction. */ | |
a7ebbfdf TS |
11173 | if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */ |
11174 | insn = 0x0c000000; /* jal */ | |
252b5132 | 11175 | else |
a7ebbfdf TS |
11176 | insn = 0x08000000; /* j */ |
11177 | fixP->fx_r_type = BFD_RELOC_MIPS_JMP; | |
11178 | fixP->fx_done = 0; | |
11179 | fixP->fx_addsy = section_symbol (text_section); | |
11180 | *valP += md_pcrel_from (fixP); | |
17a2f251 | 11181 | md_number_to_chars (buf, insn, 4); |
a7ebbfdf TS |
11182 | } |
11183 | else | |
11184 | { | |
11185 | /* If we got here, we have branch-relaxation disabled, | |
11186 | and there's nothing we can do to fix this instruction | |
11187 | without turning it into a longer sequence. */ | |
11188 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11189 | _("Branch out of range")); | |
252b5132 | 11190 | } |
252b5132 RH |
11191 | break; |
11192 | ||
11193 | case BFD_RELOC_VTABLE_INHERIT: | |
11194 | fixP->fx_done = 0; | |
11195 | if (fixP->fx_addsy | |
11196 | && !S_IS_DEFINED (fixP->fx_addsy) | |
11197 | && !S_IS_WEAK (fixP->fx_addsy)) | |
11198 | S_SET_WEAK (fixP->fx_addsy); | |
11199 | break; | |
11200 | ||
11201 | case BFD_RELOC_VTABLE_ENTRY: | |
11202 | fixP->fx_done = 0; | |
11203 | break; | |
11204 | ||
11205 | default: | |
11206 | internalError (); | |
11207 | } | |
a7ebbfdf TS |
11208 | |
11209 | /* Remember value for tc_gen_reloc. */ | |
11210 | fixP->fx_addnumber = *valP; | |
252b5132 RH |
11211 | } |
11212 | ||
252b5132 | 11213 | static symbolS * |
17a2f251 | 11214 | get_symbol (void) |
252b5132 RH |
11215 | { |
11216 | int c; | |
11217 | char *name; | |
11218 | symbolS *p; | |
11219 | ||
11220 | name = input_line_pointer; | |
11221 | c = get_symbol_end (); | |
11222 | p = (symbolS *) symbol_find_or_make (name); | |
11223 | *input_line_pointer = c; | |
11224 | return p; | |
11225 | } | |
11226 | ||
11227 | /* Align the current frag to a given power of two. The MIPS assembler | |
11228 | also automatically adjusts any preceding label. */ | |
11229 | ||
11230 | static void | |
17a2f251 | 11231 | mips_align (int to, int fill, symbolS *label) |
252b5132 | 11232 | { |
b34976b6 | 11233 | mips_emit_delays (FALSE); |
252b5132 RH |
11234 | frag_align (to, fill, 0); |
11235 | record_alignment (now_seg, to); | |
11236 | if (label != NULL) | |
11237 | { | |
11238 | assert (S_GET_SEGMENT (label) == now_seg); | |
49309057 | 11239 | symbol_set_frag (label, frag_now); |
252b5132 RH |
11240 | S_SET_VALUE (label, (valueT) frag_now_fix ()); |
11241 | } | |
11242 | } | |
11243 | ||
11244 | /* Align to a given power of two. .align 0 turns off the automatic | |
11245 | alignment used by the data creating pseudo-ops. */ | |
11246 | ||
11247 | static void | |
17a2f251 | 11248 | s_align (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
11249 | { |
11250 | register int temp; | |
11251 | register long temp_fill; | |
11252 | long max_alignment = 15; | |
11253 | ||
11254 | /* | |
11255 | ||
67c1ffbe | 11256 | o Note that the assembler pulls down any immediately preceding label |
252b5132 RH |
11257 | to the aligned address. |
11258 | o It's not documented but auto alignment is reinstated by | |
11259 | a .align pseudo instruction. | |
11260 | o Note also that after auto alignment is turned off the mips assembler | |
11261 | issues an error on attempt to assemble an improperly aligned data item. | |
11262 | We don't. | |
11263 | ||
11264 | */ | |
11265 | ||
11266 | temp = get_absolute_expression (); | |
11267 | if (temp > max_alignment) | |
11268 | as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment); | |
11269 | else if (temp < 0) | |
11270 | { | |
11271 | as_warn (_("Alignment negative: 0 assumed.")); | |
11272 | temp = 0; | |
11273 | } | |
11274 | if (*input_line_pointer == ',') | |
11275 | { | |
f9419b05 | 11276 | ++input_line_pointer; |
252b5132 RH |
11277 | temp_fill = get_absolute_expression (); |
11278 | } | |
11279 | else | |
11280 | temp_fill = 0; | |
11281 | if (temp) | |
11282 | { | |
11283 | auto_align = 1; | |
11284 | mips_align (temp, (int) temp_fill, | |
11285 | insn_labels != NULL ? insn_labels->label : NULL); | |
11286 | } | |
11287 | else | |
11288 | { | |
11289 | auto_align = 0; | |
11290 | } | |
11291 | ||
11292 | demand_empty_rest_of_line (); | |
11293 | } | |
11294 | ||
11295 | void | |
17a2f251 | 11296 | mips_flush_pending_output (void) |
252b5132 | 11297 | { |
b34976b6 | 11298 | mips_emit_delays (FALSE); |
252b5132 RH |
11299 | mips_clear_insn_labels (); |
11300 | } | |
11301 | ||
11302 | static void | |
17a2f251 | 11303 | s_change_sec (int sec) |
252b5132 RH |
11304 | { |
11305 | segT seg; | |
11306 | ||
252b5132 RH |
11307 | #ifdef OBJ_ELF |
11308 | /* The ELF backend needs to know that we are changing sections, so | |
11309 | that .previous works correctly. We could do something like check | |
b6ff326e | 11310 | for an obj_section_change_hook macro, but that might be confusing |
252b5132 RH |
11311 | as it would not be appropriate to use it in the section changing |
11312 | functions in read.c, since obj-elf.c intercepts those. FIXME: | |
11313 | This should be cleaner, somehow. */ | |
11314 | obj_elf_section_change_hook (); | |
11315 | #endif | |
11316 | ||
b34976b6 | 11317 | mips_emit_delays (FALSE); |
252b5132 RH |
11318 | switch (sec) |
11319 | { | |
11320 | case 't': | |
11321 | s_text (0); | |
11322 | break; | |
11323 | case 'd': | |
11324 | s_data (0); | |
11325 | break; | |
11326 | case 'b': | |
11327 | subseg_set (bss_section, (subsegT) get_absolute_expression ()); | |
11328 | demand_empty_rest_of_line (); | |
11329 | break; | |
11330 | ||
11331 | case 'r': | |
4d0d148d TS |
11332 | seg = subseg_new (RDATA_SECTION_NAME, |
11333 | (subsegT) get_absolute_expression ()); | |
11334 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
252b5132 | 11335 | { |
4d0d148d TS |
11336 | bfd_set_section_flags (stdoutput, seg, (SEC_ALLOC | SEC_LOAD |
11337 | | SEC_READONLY | SEC_RELOC | |
11338 | | SEC_DATA)); | |
11339 | if (strcmp (TARGET_OS, "elf") != 0) | |
11340 | record_alignment (seg, 4); | |
252b5132 | 11341 | } |
4d0d148d | 11342 | demand_empty_rest_of_line (); |
252b5132 RH |
11343 | break; |
11344 | ||
11345 | case 's': | |
4d0d148d TS |
11346 | seg = subseg_new (".sdata", (subsegT) get_absolute_expression ()); |
11347 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
252b5132 | 11348 | { |
4d0d148d TS |
11349 | bfd_set_section_flags (stdoutput, seg, |
11350 | SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA); | |
11351 | if (strcmp (TARGET_OS, "elf") != 0) | |
11352 | record_alignment (seg, 4); | |
252b5132 | 11353 | } |
4d0d148d TS |
11354 | demand_empty_rest_of_line (); |
11355 | break; | |
252b5132 RH |
11356 | } |
11357 | ||
11358 | auto_align = 1; | |
11359 | } | |
b34976b6 | 11360 | |
cca86cc8 | 11361 | void |
17a2f251 | 11362 | s_change_section (int ignore ATTRIBUTE_UNUSED) |
cca86cc8 | 11363 | { |
7ed4a06a | 11364 | #ifdef OBJ_ELF |
cca86cc8 SC |
11365 | char *section_name; |
11366 | char c; | |
684022ea | 11367 | char next_c = 0; |
cca86cc8 SC |
11368 | int section_type; |
11369 | int section_flag; | |
11370 | int section_entry_size; | |
11371 | int section_alignment; | |
b34976b6 | 11372 | |
7ed4a06a TS |
11373 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
11374 | return; | |
11375 | ||
cca86cc8 SC |
11376 | section_name = input_line_pointer; |
11377 | c = get_symbol_end (); | |
a816d1ed AO |
11378 | if (c) |
11379 | next_c = *(input_line_pointer + 1); | |
cca86cc8 | 11380 | |
4cf0dd0d TS |
11381 | /* Do we have .section Name<,"flags">? */ |
11382 | if (c != ',' || (c == ',' && next_c == '"')) | |
cca86cc8 | 11383 | { |
4cf0dd0d TS |
11384 | /* just after name is now '\0'. */ |
11385 | *input_line_pointer = c; | |
cca86cc8 SC |
11386 | input_line_pointer = section_name; |
11387 | obj_elf_section (ignore); | |
11388 | return; | |
11389 | } | |
11390 | input_line_pointer++; | |
11391 | ||
11392 | /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */ | |
11393 | if (c == ',') | |
11394 | section_type = get_absolute_expression (); | |
11395 | else | |
11396 | section_type = 0; | |
11397 | if (*input_line_pointer++ == ',') | |
11398 | section_flag = get_absolute_expression (); | |
11399 | else | |
11400 | section_flag = 0; | |
11401 | if (*input_line_pointer++ == ',') | |
11402 | section_entry_size = get_absolute_expression (); | |
11403 | else | |
11404 | section_entry_size = 0; | |
11405 | if (*input_line_pointer++ == ',') | |
11406 | section_alignment = get_absolute_expression (); | |
11407 | else | |
11408 | section_alignment = 0; | |
11409 | ||
a816d1ed AO |
11410 | section_name = xstrdup (section_name); |
11411 | ||
8ab8a5c8 RS |
11412 | /* When using the generic form of .section (as implemented by obj-elf.c), |
11413 | there's no way to set the section type to SHT_MIPS_DWARF. Users have | |
11414 | traditionally had to fall back on the more common @progbits instead. | |
11415 | ||
11416 | There's nothing really harmful in this, since bfd will correct | |
11417 | SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it | |
11418 | means that, for backwards compatibiltiy, the special_section entries | |
11419 | for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF. | |
11420 | ||
11421 | Even so, we shouldn't force users of the MIPS .section syntax to | |
11422 | incorrectly label the sections as SHT_PROGBITS. The best compromise | |
11423 | seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the | |
11424 | generic type-checking code. */ | |
11425 | if (section_type == SHT_MIPS_DWARF) | |
11426 | section_type = SHT_PROGBITS; | |
11427 | ||
cca86cc8 SC |
11428 | obj_elf_change_section (section_name, section_type, section_flag, |
11429 | section_entry_size, 0, 0, 0); | |
a816d1ed AO |
11430 | |
11431 | if (now_seg->name != section_name) | |
11432 | free (section_name); | |
7ed4a06a | 11433 | #endif /* OBJ_ELF */ |
cca86cc8 | 11434 | } |
252b5132 RH |
11435 | |
11436 | void | |
17a2f251 | 11437 | mips_enable_auto_align (void) |
252b5132 RH |
11438 | { |
11439 | auto_align = 1; | |
11440 | } | |
11441 | ||
11442 | static void | |
17a2f251 | 11443 | s_cons (int log_size) |
252b5132 RH |
11444 | { |
11445 | symbolS *label; | |
11446 | ||
11447 | label = insn_labels != NULL ? insn_labels->label : NULL; | |
b34976b6 | 11448 | mips_emit_delays (FALSE); |
252b5132 RH |
11449 | if (log_size > 0 && auto_align) |
11450 | mips_align (log_size, 0, label); | |
11451 | mips_clear_insn_labels (); | |
11452 | cons (1 << log_size); | |
11453 | } | |
11454 | ||
11455 | static void | |
17a2f251 | 11456 | s_float_cons (int type) |
252b5132 RH |
11457 | { |
11458 | symbolS *label; | |
11459 | ||
11460 | label = insn_labels != NULL ? insn_labels->label : NULL; | |
11461 | ||
b34976b6 | 11462 | mips_emit_delays (FALSE); |
252b5132 RH |
11463 | |
11464 | if (auto_align) | |
49309057 ILT |
11465 | { |
11466 | if (type == 'd') | |
11467 | mips_align (3, 0, label); | |
11468 | else | |
11469 | mips_align (2, 0, label); | |
11470 | } | |
252b5132 RH |
11471 | |
11472 | mips_clear_insn_labels (); | |
11473 | ||
11474 | float_cons (type); | |
11475 | } | |
11476 | ||
11477 | /* Handle .globl. We need to override it because on Irix 5 you are | |
11478 | permitted to say | |
11479 | .globl foo .text | |
11480 | where foo is an undefined symbol, to mean that foo should be | |
11481 | considered to be the address of a function. */ | |
11482 | ||
11483 | static void | |
17a2f251 | 11484 | s_mips_globl (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
11485 | { |
11486 | char *name; | |
11487 | int c; | |
11488 | symbolS *symbolP; | |
11489 | flagword flag; | |
11490 | ||
11491 | name = input_line_pointer; | |
11492 | c = get_symbol_end (); | |
11493 | symbolP = symbol_find_or_make (name); | |
11494 | *input_line_pointer = c; | |
11495 | SKIP_WHITESPACE (); | |
11496 | ||
11497 | /* On Irix 5, every global symbol that is not explicitly labelled as | |
11498 | being a function is apparently labelled as being an object. */ | |
11499 | flag = BSF_OBJECT; | |
11500 | ||
11501 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
11502 | { | |
11503 | char *secname; | |
11504 | asection *sec; | |
11505 | ||
11506 | secname = input_line_pointer; | |
11507 | c = get_symbol_end (); | |
11508 | sec = bfd_get_section_by_name (stdoutput, secname); | |
11509 | if (sec == NULL) | |
11510 | as_bad (_("%s: no such section"), secname); | |
11511 | *input_line_pointer = c; | |
11512 | ||
11513 | if (sec != NULL && (sec->flags & SEC_CODE) != 0) | |
11514 | flag = BSF_FUNCTION; | |
11515 | } | |
11516 | ||
49309057 | 11517 | symbol_get_bfdsym (symbolP)->flags |= flag; |
252b5132 RH |
11518 | |
11519 | S_SET_EXTERNAL (symbolP); | |
11520 | demand_empty_rest_of_line (); | |
11521 | } | |
11522 | ||
11523 | static void | |
17a2f251 | 11524 | s_option (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
11525 | { |
11526 | char *opt; | |
11527 | char c; | |
11528 | ||
11529 | opt = input_line_pointer; | |
11530 | c = get_symbol_end (); | |
11531 | ||
11532 | if (*opt == 'O') | |
11533 | { | |
11534 | /* FIXME: What does this mean? */ | |
11535 | } | |
11536 | else if (strncmp (opt, "pic", 3) == 0) | |
11537 | { | |
11538 | int i; | |
11539 | ||
11540 | i = atoi (opt + 3); | |
11541 | if (i == 0) | |
11542 | mips_pic = NO_PIC; | |
11543 | else if (i == 2) | |
143d77c5 | 11544 | { |
252b5132 | 11545 | mips_pic = SVR4_PIC; |
143d77c5 EC |
11546 | mips_abicalls = TRUE; |
11547 | } | |
252b5132 RH |
11548 | else |
11549 | as_bad (_(".option pic%d not supported"), i); | |
11550 | ||
4d0d148d | 11551 | if (mips_pic == SVR4_PIC) |
252b5132 RH |
11552 | { |
11553 | if (g_switch_seen && g_switch_value != 0) | |
11554 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
11555 | g_switch_value = 0; | |
11556 | bfd_set_gp_size (stdoutput, 0); | |
11557 | } | |
11558 | } | |
11559 | else | |
11560 | as_warn (_("Unrecognized option \"%s\""), opt); | |
11561 | ||
11562 | *input_line_pointer = c; | |
11563 | demand_empty_rest_of_line (); | |
11564 | } | |
11565 | ||
11566 | /* This structure is used to hold a stack of .set values. */ | |
11567 | ||
e972090a NC |
11568 | struct mips_option_stack |
11569 | { | |
252b5132 RH |
11570 | struct mips_option_stack *next; |
11571 | struct mips_set_options options; | |
11572 | }; | |
11573 | ||
11574 | static struct mips_option_stack *mips_opts_stack; | |
11575 | ||
11576 | /* Handle the .set pseudo-op. */ | |
11577 | ||
11578 | static void | |
17a2f251 | 11579 | s_mipsset (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
11580 | { |
11581 | char *name = input_line_pointer, ch; | |
11582 | ||
11583 | while (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
f9419b05 | 11584 | ++input_line_pointer; |
252b5132 RH |
11585 | ch = *input_line_pointer; |
11586 | *input_line_pointer = '\0'; | |
11587 | ||
11588 | if (strcmp (name, "reorder") == 0) | |
11589 | { | |
11590 | if (mips_opts.noreorder && prev_nop_frag != NULL) | |
11591 | { | |
11592 | /* If we still have pending nops, we can discard them. The | |
11593 | usual nop handling will insert any that are still | |
bdaaa2e1 | 11594 | needed. */ |
252b5132 RH |
11595 | prev_nop_frag->fr_fix -= (prev_nop_frag_holds |
11596 | * (mips_opts.mips16 ? 2 : 4)); | |
11597 | prev_nop_frag = NULL; | |
11598 | } | |
11599 | mips_opts.noreorder = 0; | |
11600 | } | |
11601 | else if (strcmp (name, "noreorder") == 0) | |
11602 | { | |
b34976b6 | 11603 | mips_emit_delays (TRUE); |
252b5132 RH |
11604 | mips_opts.noreorder = 1; |
11605 | mips_any_noreorder = 1; | |
11606 | } | |
11607 | else if (strcmp (name, "at") == 0) | |
11608 | { | |
11609 | mips_opts.noat = 0; | |
11610 | } | |
11611 | else if (strcmp (name, "noat") == 0) | |
11612 | { | |
11613 | mips_opts.noat = 1; | |
11614 | } | |
11615 | else if (strcmp (name, "macro") == 0) | |
11616 | { | |
11617 | mips_opts.warn_about_macros = 0; | |
11618 | } | |
11619 | else if (strcmp (name, "nomacro") == 0) | |
11620 | { | |
11621 | if (mips_opts.noreorder == 0) | |
11622 | as_bad (_("`noreorder' must be set before `nomacro'")); | |
11623 | mips_opts.warn_about_macros = 1; | |
11624 | } | |
11625 | else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0) | |
11626 | { | |
11627 | mips_opts.nomove = 0; | |
11628 | } | |
11629 | else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0) | |
11630 | { | |
11631 | mips_opts.nomove = 1; | |
11632 | } | |
11633 | else if (strcmp (name, "bopt") == 0) | |
11634 | { | |
11635 | mips_opts.nobopt = 0; | |
11636 | } | |
11637 | else if (strcmp (name, "nobopt") == 0) | |
11638 | { | |
11639 | mips_opts.nobopt = 1; | |
11640 | } | |
11641 | else if (strcmp (name, "mips16") == 0 | |
11642 | || strcmp (name, "MIPS-16") == 0) | |
11643 | mips_opts.mips16 = 1; | |
11644 | else if (strcmp (name, "nomips16") == 0 | |
11645 | || strcmp (name, "noMIPS-16") == 0) | |
11646 | mips_opts.mips16 = 0; | |
1f25f5d3 CD |
11647 | else if (strcmp (name, "mips3d") == 0) |
11648 | mips_opts.ase_mips3d = 1; | |
11649 | else if (strcmp (name, "nomips3d") == 0) | |
11650 | mips_opts.ase_mips3d = 0; | |
a4672219 TS |
11651 | else if (strcmp (name, "mdmx") == 0) |
11652 | mips_opts.ase_mdmx = 1; | |
11653 | else if (strcmp (name, "nomdmx") == 0) | |
11654 | mips_opts.ase_mdmx = 0; | |
1a2c1fad | 11655 | else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0) |
252b5132 | 11656 | { |
af7ee8bf | 11657 | int reset = 0; |
252b5132 | 11658 | |
1a2c1fad CD |
11659 | /* Permit the user to change the ISA and architecture on the fly. |
11660 | Needless to say, misuse can cause serious problems. */ | |
81a21e38 | 11661 | if (strcmp (name, "mips0") == 0 || strcmp (name, "arch=default") == 0) |
af7ee8bf CD |
11662 | { |
11663 | reset = 1; | |
11664 | mips_opts.isa = file_mips_isa; | |
1a2c1fad | 11665 | mips_opts.arch = file_mips_arch; |
1a2c1fad CD |
11666 | } |
11667 | else if (strncmp (name, "arch=", 5) == 0) | |
11668 | { | |
11669 | const struct mips_cpu_info *p; | |
11670 | ||
11671 | p = mips_parse_cpu("internal use", name + 5); | |
11672 | if (!p) | |
11673 | as_bad (_("unknown architecture %s"), name + 5); | |
11674 | else | |
11675 | { | |
11676 | mips_opts.arch = p->cpu; | |
11677 | mips_opts.isa = p->isa; | |
11678 | } | |
11679 | } | |
81a21e38 TS |
11680 | else if (strncmp (name, "mips", 4) == 0) |
11681 | { | |
11682 | const struct mips_cpu_info *p; | |
11683 | ||
11684 | p = mips_parse_cpu("internal use", name); | |
11685 | if (!p) | |
11686 | as_bad (_("unknown ISA level %s"), name + 4); | |
11687 | else | |
11688 | { | |
11689 | mips_opts.arch = p->cpu; | |
11690 | mips_opts.isa = p->isa; | |
11691 | } | |
11692 | } | |
af7ee8bf | 11693 | else |
81a21e38 | 11694 | as_bad (_("unknown ISA or architecture %s"), name); |
af7ee8bf CD |
11695 | |
11696 | switch (mips_opts.isa) | |
98d3f06f KH |
11697 | { |
11698 | case 0: | |
98d3f06f | 11699 | break; |
af7ee8bf CD |
11700 | case ISA_MIPS1: |
11701 | case ISA_MIPS2: | |
11702 | case ISA_MIPS32: | |
11703 | case ISA_MIPS32R2: | |
98d3f06f KH |
11704 | mips_opts.gp32 = 1; |
11705 | mips_opts.fp32 = 1; | |
11706 | break; | |
af7ee8bf CD |
11707 | case ISA_MIPS3: |
11708 | case ISA_MIPS4: | |
11709 | case ISA_MIPS5: | |
11710 | case ISA_MIPS64: | |
5f74bc13 | 11711 | case ISA_MIPS64R2: |
98d3f06f KH |
11712 | mips_opts.gp32 = 0; |
11713 | mips_opts.fp32 = 0; | |
11714 | break; | |
11715 | default: | |
11716 | as_bad (_("unknown ISA level %s"), name + 4); | |
11717 | break; | |
11718 | } | |
af7ee8bf | 11719 | if (reset) |
98d3f06f | 11720 | { |
af7ee8bf CD |
11721 | mips_opts.gp32 = file_mips_gp32; |
11722 | mips_opts.fp32 = file_mips_fp32; | |
98d3f06f | 11723 | } |
252b5132 RH |
11724 | } |
11725 | else if (strcmp (name, "autoextend") == 0) | |
11726 | mips_opts.noautoextend = 0; | |
11727 | else if (strcmp (name, "noautoextend") == 0) | |
11728 | mips_opts.noautoextend = 1; | |
11729 | else if (strcmp (name, "push") == 0) | |
11730 | { | |
11731 | struct mips_option_stack *s; | |
11732 | ||
11733 | s = (struct mips_option_stack *) xmalloc (sizeof *s); | |
11734 | s->next = mips_opts_stack; | |
11735 | s->options = mips_opts; | |
11736 | mips_opts_stack = s; | |
11737 | } | |
11738 | else if (strcmp (name, "pop") == 0) | |
11739 | { | |
11740 | struct mips_option_stack *s; | |
11741 | ||
11742 | s = mips_opts_stack; | |
11743 | if (s == NULL) | |
11744 | as_bad (_(".set pop with no .set push")); | |
11745 | else | |
11746 | { | |
11747 | /* If we're changing the reorder mode we need to handle | |
11748 | delay slots correctly. */ | |
11749 | if (s->options.noreorder && ! mips_opts.noreorder) | |
b34976b6 | 11750 | mips_emit_delays (TRUE); |
252b5132 RH |
11751 | else if (! s->options.noreorder && mips_opts.noreorder) |
11752 | { | |
11753 | if (prev_nop_frag != NULL) | |
11754 | { | |
11755 | prev_nop_frag->fr_fix -= (prev_nop_frag_holds | |
11756 | * (mips_opts.mips16 ? 2 : 4)); | |
11757 | prev_nop_frag = NULL; | |
11758 | } | |
11759 | } | |
11760 | ||
11761 | mips_opts = s->options; | |
11762 | mips_opts_stack = s->next; | |
11763 | free (s); | |
11764 | } | |
11765 | } | |
11766 | else | |
11767 | { | |
11768 | as_warn (_("Tried to set unrecognized symbol: %s\n"), name); | |
11769 | } | |
11770 | *input_line_pointer = ch; | |
11771 | demand_empty_rest_of_line (); | |
11772 | } | |
11773 | ||
11774 | /* Handle the .abicalls pseudo-op. I believe this is equivalent to | |
11775 | .option pic2. It means to generate SVR4 PIC calls. */ | |
11776 | ||
11777 | static void | |
17a2f251 | 11778 | s_abicalls (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
11779 | { |
11780 | mips_pic = SVR4_PIC; | |
143d77c5 | 11781 | mips_abicalls = TRUE; |
4d0d148d TS |
11782 | |
11783 | if (g_switch_seen && g_switch_value != 0) | |
11784 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
11785 | g_switch_value = 0; | |
11786 | ||
252b5132 RH |
11787 | bfd_set_gp_size (stdoutput, 0); |
11788 | demand_empty_rest_of_line (); | |
11789 | } | |
11790 | ||
11791 | /* Handle the .cpload pseudo-op. This is used when generating SVR4 | |
11792 | PIC code. It sets the $gp register for the function based on the | |
11793 | function address, which is in the register named in the argument. | |
11794 | This uses a relocation against _gp_disp, which is handled specially | |
11795 | by the linker. The result is: | |
11796 | lui $gp,%hi(_gp_disp) | |
11797 | addiu $gp,$gp,%lo(_gp_disp) | |
11798 | addu $gp,$gp,.cpload argument | |
aa6975fb ILT |
11799 | The .cpload argument is normally $25 == $t9. |
11800 | ||
11801 | The -mno-shared option changes this to: | |
11802 | lui $gp,%hi(_gp) | |
11803 | addiu $gp,$gp,%lo(_gp) | |
11804 | and the argument is ignored. This saves an instruction, but the | |
11805 | resulting code is not position independent; it uses an absolute | |
11806 | address for _gp. Thus code assembled with -mno-shared can go into | |
11807 | an ordinary executable, but not into a shared library. */ | |
252b5132 RH |
11808 | |
11809 | static void | |
17a2f251 | 11810 | s_cpload (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
11811 | { |
11812 | expressionS ex; | |
aa6975fb ILT |
11813 | int reg; |
11814 | int in_shared; | |
252b5132 | 11815 | |
6478892d TS |
11816 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
11817 | .cpload is ignored. */ | |
11818 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) | |
252b5132 RH |
11819 | { |
11820 | s_ignore (0); | |
11821 | return; | |
11822 | } | |
11823 | ||
d3ecfc59 | 11824 | /* .cpload should be in a .set noreorder section. */ |
252b5132 RH |
11825 | if (mips_opts.noreorder == 0) |
11826 | as_warn (_(".cpload not in noreorder section")); | |
11827 | ||
aa6975fb ILT |
11828 | reg = tc_get_register (0); |
11829 | ||
11830 | /* If we need to produce a 64-bit address, we are better off using | |
11831 | the default instruction sequence. */ | |
11832 | in_shared = mips_in_shared || HAVE_64BIT_ADDRESSES; | |
11833 | ||
252b5132 | 11834 | ex.X_op = O_symbol; |
aa6975fb | 11835 | ex.X_add_symbol = symbol_find_or_make (in_shared ? "_gp_disp" : "_gp"); |
252b5132 RH |
11836 | ex.X_op_symbol = NULL; |
11837 | ex.X_add_number = 0; | |
11838 | ||
11839 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ | |
49309057 | 11840 | symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; |
252b5132 | 11841 | |
584892a6 | 11842 | macro_start (); |
67c0d1eb RS |
11843 | macro_build_lui (&ex, mips_gp_register); |
11844 | macro_build (&ex, "addiu", "t,r,j", mips_gp_register, | |
17a2f251 | 11845 | mips_gp_register, BFD_RELOC_LO16); |
aa6975fb ILT |
11846 | if (in_shared) |
11847 | macro_build (NULL, "addu", "d,v,t", mips_gp_register, | |
11848 | mips_gp_register, reg); | |
584892a6 | 11849 | macro_end (); |
252b5132 RH |
11850 | |
11851 | demand_empty_rest_of_line (); | |
11852 | } | |
11853 | ||
6478892d TS |
11854 | /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is: |
11855 | .cpsetup $reg1, offset|$reg2, label | |
11856 | ||
11857 | If offset is given, this results in: | |
11858 | sd $gp, offset($sp) | |
956cd1d6 | 11859 | lui $gp, %hi(%neg(%gp_rel(label))) |
698b7d9d TS |
11860 | addiu $gp, $gp, %lo(%neg(%gp_rel(label))) |
11861 | daddu $gp, $gp, $reg1 | |
6478892d TS |
11862 | |
11863 | If $reg2 is given, this results in: | |
11864 | daddu $reg2, $gp, $0 | |
956cd1d6 | 11865 | lui $gp, %hi(%neg(%gp_rel(label))) |
698b7d9d TS |
11866 | addiu $gp, $gp, %lo(%neg(%gp_rel(label))) |
11867 | daddu $gp, $gp, $reg1 | |
aa6975fb ILT |
11868 | $reg1 is normally $25 == $t9. |
11869 | ||
11870 | The -mno-shared option replaces the last three instructions with | |
11871 | lui $gp,%hi(_gp) | |
11872 | addiu $gp,$gp,%lo(_gp) | |
11873 | */ | |
11874 | ||
6478892d | 11875 | static void |
17a2f251 | 11876 | s_cpsetup (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
11877 | { |
11878 | expressionS ex_off; | |
11879 | expressionS ex_sym; | |
11880 | int reg1; | |
6478892d | 11881 | |
8586fc66 | 11882 | /* If we are not generating SVR4 PIC code, .cpsetup is ignored. |
6478892d TS |
11883 | We also need NewABI support. */ |
11884 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
11885 | { | |
11886 | s_ignore (0); | |
11887 | return; | |
11888 | } | |
11889 | ||
11890 | reg1 = tc_get_register (0); | |
11891 | SKIP_WHITESPACE (); | |
11892 | if (*input_line_pointer != ',') | |
11893 | { | |
11894 | as_bad (_("missing argument separator ',' for .cpsetup")); | |
11895 | return; | |
11896 | } | |
11897 | else | |
80245285 | 11898 | ++input_line_pointer; |
6478892d TS |
11899 | SKIP_WHITESPACE (); |
11900 | if (*input_line_pointer == '$') | |
80245285 TS |
11901 | { |
11902 | mips_cpreturn_register = tc_get_register (0); | |
11903 | mips_cpreturn_offset = -1; | |
11904 | } | |
6478892d | 11905 | else |
80245285 TS |
11906 | { |
11907 | mips_cpreturn_offset = get_absolute_expression (); | |
11908 | mips_cpreturn_register = -1; | |
11909 | } | |
6478892d TS |
11910 | SKIP_WHITESPACE (); |
11911 | if (*input_line_pointer != ',') | |
11912 | { | |
11913 | as_bad (_("missing argument separator ',' for .cpsetup")); | |
11914 | return; | |
11915 | } | |
11916 | else | |
f9419b05 | 11917 | ++input_line_pointer; |
6478892d | 11918 | SKIP_WHITESPACE (); |
f21f8242 | 11919 | expression (&ex_sym); |
6478892d | 11920 | |
584892a6 | 11921 | macro_start (); |
6478892d TS |
11922 | if (mips_cpreturn_register == -1) |
11923 | { | |
11924 | ex_off.X_op = O_constant; | |
11925 | ex_off.X_add_symbol = NULL; | |
11926 | ex_off.X_op_symbol = NULL; | |
11927 | ex_off.X_add_number = mips_cpreturn_offset; | |
11928 | ||
67c0d1eb | 11929 | macro_build (&ex_off, "sd", "t,o(b)", mips_gp_register, |
17a2f251 | 11930 | BFD_RELOC_LO16, SP); |
6478892d TS |
11931 | } |
11932 | else | |
67c0d1eb | 11933 | macro_build (NULL, "daddu", "d,v,t", mips_cpreturn_register, |
17a2f251 | 11934 | mips_gp_register, 0); |
6478892d | 11935 | |
aa6975fb ILT |
11936 | if (mips_in_shared || HAVE_64BIT_ADDRESSES) |
11937 | { | |
11938 | macro_build (&ex_sym, "lui", "t,u", mips_gp_register, | |
11939 | -1, BFD_RELOC_GPREL16, BFD_RELOC_MIPS_SUB, | |
11940 | BFD_RELOC_HI16_S); | |
11941 | ||
11942 | macro_build (&ex_sym, "addiu", "t,r,j", mips_gp_register, | |
11943 | mips_gp_register, -1, BFD_RELOC_GPREL16, | |
11944 | BFD_RELOC_MIPS_SUB, BFD_RELOC_LO16); | |
11945 | ||
11946 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register, | |
11947 | mips_gp_register, reg1); | |
11948 | } | |
11949 | else | |
11950 | { | |
11951 | expressionS ex; | |
11952 | ||
11953 | ex.X_op = O_symbol; | |
11954 | ex.X_add_symbol = symbol_find_or_make ("_gp"); | |
11955 | ex.X_op_symbol = NULL; | |
11956 | ex.X_add_number = 0; | |
6e1304d8 | 11957 | |
aa6975fb ILT |
11958 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ |
11959 | symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; | |
11960 | ||
11961 | macro_build_lui (&ex, mips_gp_register); | |
11962 | macro_build (&ex, "addiu", "t,r,j", mips_gp_register, | |
11963 | mips_gp_register, BFD_RELOC_LO16); | |
11964 | } | |
f21f8242 | 11965 | |
584892a6 | 11966 | macro_end (); |
6478892d TS |
11967 | |
11968 | demand_empty_rest_of_line (); | |
11969 | } | |
11970 | ||
11971 | static void | |
17a2f251 | 11972 | s_cplocal (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
11973 | { |
11974 | /* If we are not generating SVR4 PIC code, or if this is not NewABI code, | |
11975 | .cplocal is ignored. */ | |
11976 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
11977 | { | |
11978 | s_ignore (0); | |
11979 | return; | |
11980 | } | |
11981 | ||
11982 | mips_gp_register = tc_get_register (0); | |
85b51719 | 11983 | demand_empty_rest_of_line (); |
6478892d TS |
11984 | } |
11985 | ||
252b5132 RH |
11986 | /* Handle the .cprestore pseudo-op. This stores $gp into a given |
11987 | offset from $sp. The offset is remembered, and after making a PIC | |
11988 | call $gp is restored from that location. */ | |
11989 | ||
11990 | static void | |
17a2f251 | 11991 | s_cprestore (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
11992 | { |
11993 | expressionS ex; | |
252b5132 | 11994 | |
6478892d | 11995 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
c9914766 | 11996 | .cprestore is ignored. */ |
6478892d | 11997 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) |
252b5132 RH |
11998 | { |
11999 | s_ignore (0); | |
12000 | return; | |
12001 | } | |
12002 | ||
12003 | mips_cprestore_offset = get_absolute_expression (); | |
7a621144 | 12004 | mips_cprestore_valid = 1; |
252b5132 RH |
12005 | |
12006 | ex.X_op = O_constant; | |
12007 | ex.X_add_symbol = NULL; | |
12008 | ex.X_op_symbol = NULL; | |
12009 | ex.X_add_number = mips_cprestore_offset; | |
12010 | ||
584892a6 | 12011 | macro_start (); |
67c0d1eb RS |
12012 | macro_build_ldst_constoffset (&ex, ADDRESS_STORE_INSN, mips_gp_register, |
12013 | SP, HAVE_64BIT_ADDRESSES); | |
584892a6 | 12014 | macro_end (); |
252b5132 RH |
12015 | |
12016 | demand_empty_rest_of_line (); | |
12017 | } | |
12018 | ||
6478892d | 12019 | /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset |
67c1ffbe | 12020 | was given in the preceding .cpsetup, it results in: |
6478892d | 12021 | ld $gp, offset($sp) |
76b3015f | 12022 | |
6478892d | 12023 | If a register $reg2 was given there, it results in: |
609f23f4 | 12024 | daddu $gp, $reg2, $0 |
6478892d TS |
12025 | */ |
12026 | static void | |
17a2f251 | 12027 | s_cpreturn (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
12028 | { |
12029 | expressionS ex; | |
6478892d TS |
12030 | |
12031 | /* If we are not generating SVR4 PIC code, .cpreturn is ignored. | |
12032 | We also need NewABI support. */ | |
12033 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
12034 | { | |
12035 | s_ignore (0); | |
12036 | return; | |
12037 | } | |
12038 | ||
584892a6 | 12039 | macro_start (); |
6478892d TS |
12040 | if (mips_cpreturn_register == -1) |
12041 | { | |
12042 | ex.X_op = O_constant; | |
12043 | ex.X_add_symbol = NULL; | |
12044 | ex.X_op_symbol = NULL; | |
12045 | ex.X_add_number = mips_cpreturn_offset; | |
12046 | ||
67c0d1eb | 12047 | macro_build (&ex, "ld", "t,o(b)", mips_gp_register, BFD_RELOC_LO16, SP); |
6478892d TS |
12048 | } |
12049 | else | |
67c0d1eb | 12050 | macro_build (NULL, "daddu", "d,v,t", mips_gp_register, |
17a2f251 | 12051 | mips_cpreturn_register, 0); |
584892a6 | 12052 | macro_end (); |
6478892d TS |
12053 | |
12054 | demand_empty_rest_of_line (); | |
12055 | } | |
12056 | ||
12057 | /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC | |
12058 | code. It sets the offset to use in gp_rel relocations. */ | |
12059 | ||
12060 | static void | |
17a2f251 | 12061 | s_gpvalue (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
12062 | { |
12063 | /* If we are not generating SVR4 PIC code, .gpvalue is ignored. | |
12064 | We also need NewABI support. */ | |
12065 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
12066 | { | |
12067 | s_ignore (0); | |
12068 | return; | |
12069 | } | |
12070 | ||
def2e0dd | 12071 | mips_gprel_offset = get_absolute_expression (); |
6478892d TS |
12072 | |
12073 | demand_empty_rest_of_line (); | |
12074 | } | |
12075 | ||
252b5132 RH |
12076 | /* Handle the .gpword pseudo-op. This is used when generating PIC |
12077 | code. It generates a 32 bit GP relative reloc. */ | |
12078 | ||
12079 | static void | |
17a2f251 | 12080 | s_gpword (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
12081 | { |
12082 | symbolS *label; | |
12083 | expressionS ex; | |
12084 | char *p; | |
12085 | ||
12086 | /* When not generating PIC code, this is treated as .word. */ | |
12087 | if (mips_pic != SVR4_PIC) | |
12088 | { | |
12089 | s_cons (2); | |
12090 | return; | |
12091 | } | |
12092 | ||
12093 | label = insn_labels != NULL ? insn_labels->label : NULL; | |
b34976b6 | 12094 | mips_emit_delays (TRUE); |
252b5132 RH |
12095 | if (auto_align) |
12096 | mips_align (2, 0, label); | |
12097 | mips_clear_insn_labels (); | |
12098 | ||
12099 | expression (&ex); | |
12100 | ||
12101 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
12102 | { | |
12103 | as_bad (_("Unsupported use of .gpword")); | |
12104 | ignore_rest_of_line (); | |
12105 | } | |
12106 | ||
12107 | p = frag_more (4); | |
17a2f251 | 12108 | md_number_to_chars (p, 0, 4); |
b34976b6 | 12109 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, |
cdf6fd85 | 12110 | BFD_RELOC_GPREL32); |
252b5132 RH |
12111 | |
12112 | demand_empty_rest_of_line (); | |
12113 | } | |
12114 | ||
10181a0d | 12115 | static void |
17a2f251 | 12116 | s_gpdword (int ignore ATTRIBUTE_UNUSED) |
10181a0d AO |
12117 | { |
12118 | symbolS *label; | |
12119 | expressionS ex; | |
12120 | char *p; | |
12121 | ||
12122 | /* When not generating PIC code, this is treated as .dword. */ | |
12123 | if (mips_pic != SVR4_PIC) | |
12124 | { | |
12125 | s_cons (3); | |
12126 | return; | |
12127 | } | |
12128 | ||
12129 | label = insn_labels != NULL ? insn_labels->label : NULL; | |
b34976b6 | 12130 | mips_emit_delays (TRUE); |
10181a0d AO |
12131 | if (auto_align) |
12132 | mips_align (3, 0, label); | |
12133 | mips_clear_insn_labels (); | |
12134 | ||
12135 | expression (&ex); | |
12136 | ||
12137 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
12138 | { | |
12139 | as_bad (_("Unsupported use of .gpdword")); | |
12140 | ignore_rest_of_line (); | |
12141 | } | |
12142 | ||
12143 | p = frag_more (8); | |
17a2f251 | 12144 | md_number_to_chars (p, 0, 8); |
a105a300 | 12145 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, |
6e1304d8 | 12146 | BFD_RELOC_GPREL32)->fx_tcbit = 1; |
10181a0d AO |
12147 | |
12148 | /* GPREL32 composed with 64 gives a 64-bit GP offset. */ | |
6e1304d8 RS |
12149 | fix_new (frag_now, p - frag_now->fr_literal, 8, NULL, 0, |
12150 | FALSE, BFD_RELOC_64)->fx_tcbit = 1; | |
10181a0d AO |
12151 | |
12152 | demand_empty_rest_of_line (); | |
12153 | } | |
12154 | ||
252b5132 RH |
12155 | /* Handle the .cpadd pseudo-op. This is used when dealing with switch |
12156 | tables in SVR4 PIC code. */ | |
12157 | ||
12158 | static void | |
17a2f251 | 12159 | s_cpadd (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 12160 | { |
252b5132 RH |
12161 | int reg; |
12162 | ||
10181a0d AO |
12163 | /* This is ignored when not generating SVR4 PIC code. */ |
12164 | if (mips_pic != SVR4_PIC) | |
252b5132 RH |
12165 | { |
12166 | s_ignore (0); | |
12167 | return; | |
12168 | } | |
12169 | ||
12170 | /* Add $gp to the register named as an argument. */ | |
584892a6 | 12171 | macro_start (); |
252b5132 | 12172 | reg = tc_get_register (0); |
67c0d1eb | 12173 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register); |
584892a6 | 12174 | macro_end (); |
252b5132 | 12175 | |
bdaaa2e1 | 12176 | demand_empty_rest_of_line (); |
252b5132 RH |
12177 | } |
12178 | ||
12179 | /* Handle the .insn pseudo-op. This marks instruction labels in | |
12180 | mips16 mode. This permits the linker to handle them specially, | |
12181 | such as generating jalx instructions when needed. We also make | |
12182 | them odd for the duration of the assembly, in order to generate the | |
12183 | right sort of code. We will make them even in the adjust_symtab | |
12184 | routine, while leaving them marked. This is convenient for the | |
12185 | debugger and the disassembler. The linker knows to make them odd | |
12186 | again. */ | |
12187 | ||
12188 | static void | |
17a2f251 | 12189 | s_insn (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 12190 | { |
f9419b05 | 12191 | mips16_mark_labels (); |
252b5132 RH |
12192 | |
12193 | demand_empty_rest_of_line (); | |
12194 | } | |
12195 | ||
12196 | /* Handle a .stabn directive. We need these in order to mark a label | |
12197 | as being a mips16 text label correctly. Sometimes the compiler | |
12198 | will emit a label, followed by a .stabn, and then switch sections. | |
12199 | If the label and .stabn are in mips16 mode, then the label is | |
12200 | really a mips16 text label. */ | |
12201 | ||
12202 | static void | |
17a2f251 | 12203 | s_mips_stab (int type) |
252b5132 | 12204 | { |
f9419b05 | 12205 | if (type == 'n') |
252b5132 RH |
12206 | mips16_mark_labels (); |
12207 | ||
12208 | s_stab (type); | |
12209 | } | |
12210 | ||
12211 | /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. | |
12212 | */ | |
12213 | ||
12214 | static void | |
17a2f251 | 12215 | s_mips_weakext (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
12216 | { |
12217 | char *name; | |
12218 | int c; | |
12219 | symbolS *symbolP; | |
12220 | expressionS exp; | |
12221 | ||
12222 | name = input_line_pointer; | |
12223 | c = get_symbol_end (); | |
12224 | symbolP = symbol_find_or_make (name); | |
12225 | S_SET_WEAK (symbolP); | |
12226 | *input_line_pointer = c; | |
12227 | ||
12228 | SKIP_WHITESPACE (); | |
12229 | ||
12230 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
12231 | { | |
12232 | if (S_IS_DEFINED (symbolP)) | |
12233 | { | |
956cd1d6 | 12234 | as_bad ("ignoring attempt to redefine symbol %s", |
252b5132 RH |
12235 | S_GET_NAME (symbolP)); |
12236 | ignore_rest_of_line (); | |
12237 | return; | |
12238 | } | |
bdaaa2e1 | 12239 | |
252b5132 RH |
12240 | if (*input_line_pointer == ',') |
12241 | { | |
12242 | ++input_line_pointer; | |
12243 | SKIP_WHITESPACE (); | |
12244 | } | |
bdaaa2e1 | 12245 | |
252b5132 RH |
12246 | expression (&exp); |
12247 | if (exp.X_op != O_symbol) | |
12248 | { | |
12249 | as_bad ("bad .weakext directive"); | |
98d3f06f | 12250 | ignore_rest_of_line (); |
252b5132 RH |
12251 | return; |
12252 | } | |
49309057 | 12253 | symbol_set_value_expression (symbolP, &exp); |
252b5132 RH |
12254 | } |
12255 | ||
12256 | demand_empty_rest_of_line (); | |
12257 | } | |
12258 | ||
12259 | /* Parse a register string into a number. Called from the ECOFF code | |
12260 | to parse .frame. The argument is non-zero if this is the frame | |
12261 | register, so that we can record it in mips_frame_reg. */ | |
12262 | ||
12263 | int | |
17a2f251 | 12264 | tc_get_register (int frame) |
252b5132 RH |
12265 | { |
12266 | int reg; | |
12267 | ||
12268 | SKIP_WHITESPACE (); | |
12269 | if (*input_line_pointer++ != '$') | |
12270 | { | |
12271 | as_warn (_("expected `$'")); | |
85b51719 | 12272 | reg = ZERO; |
252b5132 | 12273 | } |
3882b010 | 12274 | else if (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
12275 | { |
12276 | reg = get_absolute_expression (); | |
12277 | if (reg < 0 || reg >= 32) | |
12278 | { | |
12279 | as_warn (_("Bad register number")); | |
85b51719 | 12280 | reg = ZERO; |
252b5132 RH |
12281 | } |
12282 | } | |
12283 | else | |
12284 | { | |
76db943d | 12285 | if (strncmp (input_line_pointer, "ra", 2) == 0) |
85b51719 TS |
12286 | { |
12287 | reg = RA; | |
12288 | input_line_pointer += 2; | |
12289 | } | |
76db943d | 12290 | else if (strncmp (input_line_pointer, "fp", 2) == 0) |
85b51719 TS |
12291 | { |
12292 | reg = FP; | |
12293 | input_line_pointer += 2; | |
12294 | } | |
252b5132 | 12295 | else if (strncmp (input_line_pointer, "sp", 2) == 0) |
85b51719 TS |
12296 | { |
12297 | reg = SP; | |
12298 | input_line_pointer += 2; | |
12299 | } | |
252b5132 | 12300 | else if (strncmp (input_line_pointer, "gp", 2) == 0) |
85b51719 TS |
12301 | { |
12302 | reg = GP; | |
12303 | input_line_pointer += 2; | |
12304 | } | |
252b5132 | 12305 | else if (strncmp (input_line_pointer, "at", 2) == 0) |
85b51719 TS |
12306 | { |
12307 | reg = AT; | |
12308 | input_line_pointer += 2; | |
12309 | } | |
12310 | else if (strncmp (input_line_pointer, "kt0", 3) == 0) | |
12311 | { | |
12312 | reg = KT0; | |
12313 | input_line_pointer += 3; | |
12314 | } | |
12315 | else if (strncmp (input_line_pointer, "kt1", 3) == 0) | |
12316 | { | |
12317 | reg = KT1; | |
12318 | input_line_pointer += 3; | |
12319 | } | |
12320 | else if (strncmp (input_line_pointer, "zero", 4) == 0) | |
12321 | { | |
12322 | reg = ZERO; | |
12323 | input_line_pointer += 4; | |
12324 | } | |
252b5132 RH |
12325 | else |
12326 | { | |
12327 | as_warn (_("Unrecognized register name")); | |
85b51719 TS |
12328 | reg = ZERO; |
12329 | while (ISALNUM(*input_line_pointer)) | |
12330 | input_line_pointer++; | |
252b5132 | 12331 | } |
252b5132 RH |
12332 | } |
12333 | if (frame) | |
7a621144 DJ |
12334 | { |
12335 | mips_frame_reg = reg != 0 ? reg : SP; | |
12336 | mips_frame_reg_valid = 1; | |
12337 | mips_cprestore_valid = 0; | |
12338 | } | |
252b5132 RH |
12339 | return reg; |
12340 | } | |
12341 | ||
12342 | valueT | |
17a2f251 | 12343 | md_section_align (asection *seg, valueT addr) |
252b5132 RH |
12344 | { |
12345 | int align = bfd_get_section_alignment (stdoutput, seg); | |
12346 | ||
12347 | #ifdef OBJ_ELF | |
12348 | /* We don't need to align ELF sections to the full alignment. | |
12349 | However, Irix 5 may prefer that we align them at least to a 16 | |
12350 | byte boundary. We don't bother to align the sections if we are | |
12351 | targeted for an embedded system. */ | |
12352 | if (strcmp (TARGET_OS, "elf") == 0) | |
12353 | return addr; | |
12354 | if (align > 4) | |
12355 | align = 4; | |
12356 | #endif | |
12357 | ||
12358 | return ((addr + (1 << align) - 1) & (-1 << align)); | |
12359 | } | |
12360 | ||
12361 | /* Utility routine, called from above as well. If called while the | |
12362 | input file is still being read, it's only an approximation. (For | |
12363 | example, a symbol may later become defined which appeared to be | |
12364 | undefined earlier.) */ | |
12365 | ||
12366 | static int | |
17a2f251 | 12367 | nopic_need_relax (symbolS *sym, int before_relaxing) |
252b5132 RH |
12368 | { |
12369 | if (sym == 0) | |
12370 | return 0; | |
12371 | ||
4d0d148d | 12372 | if (g_switch_value > 0) |
252b5132 RH |
12373 | { |
12374 | const char *symname; | |
12375 | int change; | |
12376 | ||
c9914766 | 12377 | /* Find out whether this symbol can be referenced off the $gp |
252b5132 RH |
12378 | register. It can be if it is smaller than the -G size or if |
12379 | it is in the .sdata or .sbss section. Certain symbols can | |
c9914766 | 12380 | not be referenced off the $gp, although it appears as though |
252b5132 RH |
12381 | they can. */ |
12382 | symname = S_GET_NAME (sym); | |
12383 | if (symname != (const char *) NULL | |
12384 | && (strcmp (symname, "eprol") == 0 | |
12385 | || strcmp (symname, "etext") == 0 | |
12386 | || strcmp (symname, "_gp") == 0 | |
12387 | || strcmp (symname, "edata") == 0 | |
12388 | || strcmp (symname, "_fbss") == 0 | |
12389 | || strcmp (symname, "_fdata") == 0 | |
12390 | || strcmp (symname, "_ftext") == 0 | |
12391 | || strcmp (symname, "end") == 0 | |
12392 | || strcmp (symname, "_gp_disp") == 0)) | |
12393 | change = 1; | |
12394 | else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym)) | |
12395 | && (0 | |
12396 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 ILT |
12397 | || (symbol_get_obj (sym)->ecoff_extern_size != 0 |
12398 | && (symbol_get_obj (sym)->ecoff_extern_size | |
12399 | <= g_switch_value)) | |
252b5132 RH |
12400 | #endif |
12401 | /* We must defer this decision until after the whole | |
12402 | file has been read, since there might be a .extern | |
12403 | after the first use of this symbol. */ | |
12404 | || (before_relaxing | |
12405 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 | 12406 | && symbol_get_obj (sym)->ecoff_extern_size == 0 |
252b5132 RH |
12407 | #endif |
12408 | && S_GET_VALUE (sym) == 0) | |
12409 | || (S_GET_VALUE (sym) != 0 | |
12410 | && S_GET_VALUE (sym) <= g_switch_value))) | |
12411 | change = 0; | |
12412 | else | |
12413 | { | |
12414 | const char *segname; | |
12415 | ||
12416 | segname = segment_name (S_GET_SEGMENT (sym)); | |
12417 | assert (strcmp (segname, ".lit8") != 0 | |
12418 | && strcmp (segname, ".lit4") != 0); | |
12419 | change = (strcmp (segname, ".sdata") != 0 | |
fba2b7f9 GK |
12420 | && strcmp (segname, ".sbss") != 0 |
12421 | && strncmp (segname, ".sdata.", 7) != 0 | |
12422 | && strncmp (segname, ".gnu.linkonce.s.", 16) != 0); | |
252b5132 RH |
12423 | } |
12424 | return change; | |
12425 | } | |
12426 | else | |
c9914766 | 12427 | /* We are not optimizing for the $gp register. */ |
252b5132 RH |
12428 | return 1; |
12429 | } | |
12430 | ||
5919d012 RS |
12431 | |
12432 | /* Return true if the given symbol should be considered local for SVR4 PIC. */ | |
12433 | ||
12434 | static bfd_boolean | |
17a2f251 | 12435 | pic_need_relax (symbolS *sym, asection *segtype) |
5919d012 RS |
12436 | { |
12437 | asection *symsec; | |
12438 | bfd_boolean linkonce; | |
12439 | ||
12440 | /* Handle the case of a symbol equated to another symbol. */ | |
12441 | while (symbol_equated_reloc_p (sym)) | |
12442 | { | |
12443 | symbolS *n; | |
12444 | ||
12445 | /* It's possible to get a loop here in a badly written | |
12446 | program. */ | |
12447 | n = symbol_get_value_expression (sym)->X_add_symbol; | |
12448 | if (n == sym) | |
12449 | break; | |
12450 | sym = n; | |
12451 | } | |
12452 | ||
12453 | symsec = S_GET_SEGMENT (sym); | |
12454 | ||
12455 | /* duplicate the test for LINK_ONCE sections as in adjust_reloc_syms */ | |
12456 | linkonce = FALSE; | |
12457 | if (symsec != segtype && ! S_IS_LOCAL (sym)) | |
12458 | { | |
12459 | if ((bfd_get_section_flags (stdoutput, symsec) & SEC_LINK_ONCE) | |
12460 | != 0) | |
12461 | linkonce = TRUE; | |
12462 | ||
12463 | /* The GNU toolchain uses an extension for ELF: a section | |
12464 | beginning with the magic string .gnu.linkonce is a linkonce | |
12465 | section. */ | |
12466 | if (strncmp (segment_name (symsec), ".gnu.linkonce", | |
12467 | sizeof ".gnu.linkonce" - 1) == 0) | |
12468 | linkonce = TRUE; | |
12469 | } | |
12470 | ||
12471 | /* This must duplicate the test in adjust_reloc_syms. */ | |
12472 | return (symsec != &bfd_und_section | |
12473 | && symsec != &bfd_abs_section | |
12474 | && ! bfd_is_com_section (symsec) | |
12475 | && !linkonce | |
12476 | #ifdef OBJ_ELF | |
12477 | /* A global or weak symbol is treated as external. */ | |
12478 | && (OUTPUT_FLAVOR != bfd_target_elf_flavour | |
3e722fb5 | 12479 | || (! S_IS_WEAK (sym) && ! S_IS_EXTERNAL (sym))) |
5919d012 RS |
12480 | #endif |
12481 | ); | |
12482 | } | |
12483 | ||
12484 | ||
252b5132 RH |
12485 | /* Given a mips16 variant frag FRAGP, return non-zero if it needs an |
12486 | extended opcode. SEC is the section the frag is in. */ | |
12487 | ||
12488 | static int | |
17a2f251 | 12489 | mips16_extended_frag (fragS *fragp, asection *sec, long stretch) |
252b5132 RH |
12490 | { |
12491 | int type; | |
12492 | register const struct mips16_immed_operand *op; | |
12493 | offsetT val; | |
12494 | int mintiny, maxtiny; | |
12495 | segT symsec; | |
98aa84af | 12496 | fragS *sym_frag; |
252b5132 RH |
12497 | |
12498 | if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype)) | |
12499 | return 0; | |
12500 | if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype)) | |
12501 | return 1; | |
12502 | ||
12503 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
12504 | op = mips16_immed_operands; | |
12505 | while (op->type != type) | |
12506 | { | |
12507 | ++op; | |
12508 | assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); | |
12509 | } | |
12510 | ||
12511 | if (op->unsp) | |
12512 | { | |
12513 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
12514 | { | |
12515 | mintiny = 1; | |
12516 | maxtiny = 1 << op->nbits; | |
12517 | } | |
12518 | else | |
12519 | { | |
12520 | mintiny = 0; | |
12521 | maxtiny = (1 << op->nbits) - 1; | |
12522 | } | |
12523 | } | |
12524 | else | |
12525 | { | |
12526 | mintiny = - (1 << (op->nbits - 1)); | |
12527 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
12528 | } | |
12529 | ||
98aa84af | 12530 | sym_frag = symbol_get_frag (fragp->fr_symbol); |
ac62c346 | 12531 | val = S_GET_VALUE (fragp->fr_symbol); |
98aa84af | 12532 | symsec = S_GET_SEGMENT (fragp->fr_symbol); |
252b5132 RH |
12533 | |
12534 | if (op->pcrel) | |
12535 | { | |
12536 | addressT addr; | |
12537 | ||
12538 | /* We won't have the section when we are called from | |
12539 | mips_relax_frag. However, we will always have been called | |
12540 | from md_estimate_size_before_relax first. If this is a | |
12541 | branch to a different section, we mark it as such. If SEC is | |
12542 | NULL, and the frag is not marked, then it must be a branch to | |
12543 | the same section. */ | |
12544 | if (sec == NULL) | |
12545 | { | |
12546 | if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype)) | |
12547 | return 1; | |
12548 | } | |
12549 | else | |
12550 | { | |
98aa84af | 12551 | /* Must have been called from md_estimate_size_before_relax. */ |
252b5132 RH |
12552 | if (symsec != sec) |
12553 | { | |
12554 | fragp->fr_subtype = | |
12555 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
12556 | ||
12557 | /* FIXME: We should support this, and let the linker | |
12558 | catch branches and loads that are out of range. */ | |
12559 | as_bad_where (fragp->fr_file, fragp->fr_line, | |
12560 | _("unsupported PC relative reference to different section")); | |
12561 | ||
12562 | return 1; | |
12563 | } | |
98aa84af AM |
12564 | if (fragp != sym_frag && sym_frag->fr_address == 0) |
12565 | /* Assume non-extended on the first relaxation pass. | |
12566 | The address we have calculated will be bogus if this is | |
12567 | a forward branch to another frag, as the forward frag | |
12568 | will have fr_address == 0. */ | |
12569 | return 0; | |
252b5132 RH |
12570 | } |
12571 | ||
12572 | /* In this case, we know for sure that the symbol fragment is in | |
98aa84af AM |
12573 | the same section. If the relax_marker of the symbol fragment |
12574 | differs from the relax_marker of this fragment, we have not | |
12575 | yet adjusted the symbol fragment fr_address. We want to add | |
252b5132 RH |
12576 | in STRETCH in order to get a better estimate of the address. |
12577 | This particularly matters because of the shift bits. */ | |
12578 | if (stretch != 0 | |
98aa84af | 12579 | && sym_frag->relax_marker != fragp->relax_marker) |
252b5132 RH |
12580 | { |
12581 | fragS *f; | |
12582 | ||
12583 | /* Adjust stretch for any alignment frag. Note that if have | |
12584 | been expanding the earlier code, the symbol may be | |
12585 | defined in what appears to be an earlier frag. FIXME: | |
12586 | This doesn't handle the fr_subtype field, which specifies | |
12587 | a maximum number of bytes to skip when doing an | |
12588 | alignment. */ | |
98aa84af | 12589 | for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next) |
252b5132 RH |
12590 | { |
12591 | if (f->fr_type == rs_align || f->fr_type == rs_align_code) | |
12592 | { | |
12593 | if (stretch < 0) | |
12594 | stretch = - ((- stretch) | |
12595 | & ~ ((1 << (int) f->fr_offset) - 1)); | |
12596 | else | |
12597 | stretch &= ~ ((1 << (int) f->fr_offset) - 1); | |
12598 | if (stretch == 0) | |
12599 | break; | |
12600 | } | |
12601 | } | |
12602 | if (f != NULL) | |
12603 | val += stretch; | |
12604 | } | |
12605 | ||
12606 | addr = fragp->fr_address + fragp->fr_fix; | |
12607 | ||
12608 | /* The base address rules are complicated. The base address of | |
12609 | a branch is the following instruction. The base address of a | |
12610 | PC relative load or add is the instruction itself, but if it | |
12611 | is in a delay slot (in which case it can not be extended) use | |
12612 | the address of the instruction whose delay slot it is in. */ | |
12613 | if (type == 'p' || type == 'q') | |
12614 | { | |
12615 | addr += 2; | |
12616 | ||
12617 | /* If we are currently assuming that this frag should be | |
12618 | extended, then, the current address is two bytes | |
bdaaa2e1 | 12619 | higher. */ |
252b5132 RH |
12620 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) |
12621 | addr += 2; | |
12622 | ||
12623 | /* Ignore the low bit in the target, since it will be set | |
12624 | for a text label. */ | |
12625 | if ((val & 1) != 0) | |
12626 | --val; | |
12627 | } | |
12628 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) | |
12629 | addr -= 4; | |
12630 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
12631 | addr -= 2; | |
12632 | ||
12633 | val -= addr & ~ ((1 << op->shift) - 1); | |
12634 | ||
12635 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
12636 | if (type == 'p' || type == 'q') | |
12637 | val /= 2; | |
12638 | ||
12639 | /* If any of the shifted bits are set, we must use an extended | |
12640 | opcode. If the address depends on the size of this | |
12641 | instruction, this can lead to a loop, so we arrange to always | |
12642 | use an extended opcode. We only check this when we are in | |
12643 | the main relaxation loop, when SEC is NULL. */ | |
12644 | if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL) | |
12645 | { | |
12646 | fragp->fr_subtype = | |
12647 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
12648 | return 1; | |
12649 | } | |
12650 | ||
12651 | /* If we are about to mark a frag as extended because the value | |
12652 | is precisely maxtiny + 1, then there is a chance of an | |
12653 | infinite loop as in the following code: | |
12654 | la $4,foo | |
12655 | .skip 1020 | |
12656 | .align 2 | |
12657 | foo: | |
12658 | In this case when the la is extended, foo is 0x3fc bytes | |
12659 | away, so the la can be shrunk, but then foo is 0x400 away, so | |
12660 | the la must be extended. To avoid this loop, we mark the | |
12661 | frag as extended if it was small, and is about to become | |
12662 | extended with a value of maxtiny + 1. */ | |
12663 | if (val == ((maxtiny + 1) << op->shift) | |
12664 | && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype) | |
12665 | && sec == NULL) | |
12666 | { | |
12667 | fragp->fr_subtype = | |
12668 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
12669 | return 1; | |
12670 | } | |
12671 | } | |
12672 | else if (symsec != absolute_section && sec != NULL) | |
12673 | as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation")); | |
12674 | ||
12675 | if ((val & ((1 << op->shift) - 1)) != 0 | |
12676 | || val < (mintiny << op->shift) | |
12677 | || val > (maxtiny << op->shift)) | |
12678 | return 1; | |
12679 | else | |
12680 | return 0; | |
12681 | } | |
12682 | ||
4a6a3df4 AO |
12683 | /* Compute the length of a branch sequence, and adjust the |
12684 | RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the | |
12685 | worst-case length is computed, with UPDATE being used to indicate | |
12686 | whether an unconditional (-1), branch-likely (+1) or regular (0) | |
12687 | branch is to be computed. */ | |
12688 | static int | |
17a2f251 | 12689 | relaxed_branch_length (fragS *fragp, asection *sec, int update) |
4a6a3df4 | 12690 | { |
b34976b6 | 12691 | bfd_boolean toofar; |
4a6a3df4 AO |
12692 | int length; |
12693 | ||
12694 | if (fragp | |
12695 | && S_IS_DEFINED (fragp->fr_symbol) | |
12696 | && sec == S_GET_SEGMENT (fragp->fr_symbol)) | |
12697 | { | |
12698 | addressT addr; | |
12699 | offsetT val; | |
12700 | ||
12701 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; | |
12702 | ||
12703 | addr = fragp->fr_address + fragp->fr_fix + 4; | |
12704 | ||
12705 | val -= addr; | |
12706 | ||
12707 | toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2); | |
12708 | } | |
12709 | else if (fragp) | |
12710 | /* If the symbol is not defined or it's in a different segment, | |
12711 | assume the user knows what's going on and emit a short | |
12712 | branch. */ | |
b34976b6 | 12713 | toofar = FALSE; |
4a6a3df4 | 12714 | else |
b34976b6 | 12715 | toofar = TRUE; |
4a6a3df4 AO |
12716 | |
12717 | if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) | |
12718 | fragp->fr_subtype | |
af6ae2ad | 12719 | = RELAX_BRANCH_ENCODE (RELAX_BRANCH_UNCOND (fragp->fr_subtype), |
4a6a3df4 AO |
12720 | RELAX_BRANCH_LIKELY (fragp->fr_subtype), |
12721 | RELAX_BRANCH_LINK (fragp->fr_subtype), | |
12722 | toofar); | |
12723 | ||
12724 | length = 4; | |
12725 | if (toofar) | |
12726 | { | |
12727 | if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0)) | |
12728 | length += 8; | |
12729 | ||
12730 | if (mips_pic != NO_PIC) | |
12731 | { | |
12732 | /* Additional space for PIC loading of target address. */ | |
12733 | length += 8; | |
12734 | if (mips_opts.isa == ISA_MIPS1) | |
12735 | /* Additional space for $at-stabilizing nop. */ | |
12736 | length += 4; | |
12737 | } | |
12738 | ||
12739 | /* If branch is conditional. */ | |
12740 | if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0)) | |
12741 | length += 8; | |
12742 | } | |
b34976b6 | 12743 | |
4a6a3df4 AO |
12744 | return length; |
12745 | } | |
12746 | ||
252b5132 RH |
12747 | /* Estimate the size of a frag before relaxing. Unless this is the |
12748 | mips16, we are not really relaxing here, and the final size is | |
12749 | encoded in the subtype information. For the mips16, we have to | |
12750 | decide whether we are using an extended opcode or not. */ | |
12751 | ||
252b5132 | 12752 | int |
17a2f251 | 12753 | md_estimate_size_before_relax (fragS *fragp, asection *segtype) |
252b5132 | 12754 | { |
5919d012 | 12755 | int change; |
252b5132 | 12756 | |
4a6a3df4 AO |
12757 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
12758 | { | |
12759 | ||
b34976b6 AM |
12760 | fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE); |
12761 | ||
4a6a3df4 AO |
12762 | return fragp->fr_var; |
12763 | } | |
12764 | ||
252b5132 | 12765 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
177b4a6a AO |
12766 | /* We don't want to modify the EXTENDED bit here; it might get us |
12767 | into infinite loops. We change it only in mips_relax_frag(). */ | |
12768 | return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2); | |
252b5132 RH |
12769 | |
12770 | if (mips_pic == NO_PIC) | |
5919d012 | 12771 | change = nopic_need_relax (fragp->fr_symbol, 0); |
252b5132 | 12772 | else if (mips_pic == SVR4_PIC) |
5919d012 | 12773 | change = pic_need_relax (fragp->fr_symbol, segtype); |
252b5132 RH |
12774 | else |
12775 | abort (); | |
12776 | ||
12777 | if (change) | |
12778 | { | |
4d7206a2 | 12779 | fragp->fr_subtype |= RELAX_USE_SECOND; |
4d7206a2 | 12780 | return -RELAX_FIRST (fragp->fr_subtype); |
252b5132 | 12781 | } |
4d7206a2 RS |
12782 | else |
12783 | return -RELAX_SECOND (fragp->fr_subtype); | |
252b5132 RH |
12784 | } |
12785 | ||
12786 | /* This is called to see whether a reloc against a defined symbol | |
de7e6852 | 12787 | should be converted into a reloc against a section. */ |
252b5132 RH |
12788 | |
12789 | int | |
17a2f251 | 12790 | mips_fix_adjustable (fixS *fixp) |
252b5132 | 12791 | { |
de7e6852 RS |
12792 | /* Don't adjust MIPS16 jump relocations, so we don't have to worry |
12793 | about the format of the offset in the .o file. */ | |
252b5132 RH |
12794 | if (fixp->fx_r_type == BFD_RELOC_MIPS16_JMP) |
12795 | return 0; | |
a161fe53 | 12796 | |
252b5132 RH |
12797 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
12798 | || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
12799 | return 0; | |
a161fe53 | 12800 | |
252b5132 RH |
12801 | if (fixp->fx_addsy == NULL) |
12802 | return 1; | |
a161fe53 | 12803 | |
de7e6852 RS |
12804 | /* If symbol SYM is in a mergeable section, relocations of the form |
12805 | SYM + 0 can usually be made section-relative. The mergeable data | |
12806 | is then identified by the section offset rather than by the symbol. | |
12807 | ||
12808 | However, if we're generating REL LO16 relocations, the offset is split | |
12809 | between the LO16 and parterning high part relocation. The linker will | |
12810 | need to recalculate the complete offset in order to correctly identify | |
12811 | the merge data. | |
12812 | ||
12813 | The linker has traditionally not looked for the parterning high part | |
12814 | relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be | |
12815 | placed anywhere. Rather than break backwards compatibility by changing | |
12816 | this, it seems better not to force the issue, and instead keep the | |
12817 | original symbol. This will work with either linker behavior. */ | |
12818 | if ((fixp->fx_r_type == BFD_RELOC_LO16 || reloc_needs_lo_p (fixp->fx_r_type)) | |
12819 | && HAVE_IN_PLACE_ADDENDS | |
12820 | && (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_MERGE) != 0) | |
12821 | return 0; | |
12822 | ||
252b5132 | 12823 | #ifdef OBJ_ELF |
de7e6852 RS |
12824 | /* Don't adjust relocations against mips16 symbols, so that the linker |
12825 | can find them if it needs to set up a stub. */ | |
252b5132 RH |
12826 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour |
12827 | && S_GET_OTHER (fixp->fx_addsy) == STO_MIPS16 | |
12828 | && fixp->fx_subsy == NULL) | |
12829 | return 0; | |
12830 | #endif | |
a161fe53 | 12831 | |
252b5132 RH |
12832 | return 1; |
12833 | } | |
12834 | ||
12835 | /* Translate internal representation of relocation info to BFD target | |
12836 | format. */ | |
12837 | ||
12838 | arelent ** | |
17a2f251 | 12839 | tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) |
252b5132 RH |
12840 | { |
12841 | static arelent *retval[4]; | |
12842 | arelent *reloc; | |
12843 | bfd_reloc_code_real_type code; | |
12844 | ||
4b0cff4e TS |
12845 | memset (retval, 0, sizeof(retval)); |
12846 | reloc = retval[0] = (arelent *) xcalloc (1, sizeof (arelent)); | |
49309057 ILT |
12847 | reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); |
12848 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
252b5132 RH |
12849 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; |
12850 | ||
3e722fb5 CD |
12851 | assert (! fixp->fx_pcrel); |
12852 | reloc->addend = fixp->fx_addnumber; | |
252b5132 | 12853 | |
438c16b8 TS |
12854 | /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable |
12855 | entry to be used in the relocation's section offset. */ | |
12856 | if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
252b5132 RH |
12857 | { |
12858 | reloc->address = reloc->addend; | |
12859 | reloc->addend = 0; | |
12860 | } | |
12861 | ||
252b5132 | 12862 | code = fixp->fx_r_type; |
252b5132 | 12863 | |
3e722fb5 CD |
12864 | /* To support a PC relative reloc, we used a Cygnus extension. |
12865 | We check for that here to make sure that we don't let such a | |
12866 | reloc escape normally. (FIXME: This was formerly used by | |
12867 | embedded-PIC support, but is now used by branch handling in | |
12868 | general. That probably should be fixed.) */ | |
0b25d3e6 AO |
12869 | if ((OUTPUT_FLAVOR == bfd_target_ecoff_flavour |
12870 | || OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
3e722fb5 | 12871 | && code == BFD_RELOC_16_PCREL_S2) |
0b25d3e6 AO |
12872 | reloc->howto = NULL; |
12873 | else | |
12874 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); | |
12875 | ||
252b5132 RH |
12876 | if (reloc->howto == NULL) |
12877 | { | |
12878 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
12879 | _("Can not represent %s relocation in this object file format"), | |
12880 | bfd_get_reloc_code_name (code)); | |
12881 | retval[0] = NULL; | |
12882 | } | |
12883 | ||
12884 | return retval; | |
12885 | } | |
12886 | ||
12887 | /* Relax a machine dependent frag. This returns the amount by which | |
12888 | the current size of the frag should change. */ | |
12889 | ||
12890 | int | |
17a2f251 | 12891 | mips_relax_frag (asection *sec, fragS *fragp, long stretch) |
252b5132 | 12892 | { |
4a6a3df4 AO |
12893 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
12894 | { | |
12895 | offsetT old_var = fragp->fr_var; | |
b34976b6 AM |
12896 | |
12897 | fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE); | |
4a6a3df4 AO |
12898 | |
12899 | return fragp->fr_var - old_var; | |
12900 | } | |
12901 | ||
252b5132 RH |
12902 | if (! RELAX_MIPS16_P (fragp->fr_subtype)) |
12903 | return 0; | |
12904 | ||
c4e7957c | 12905 | if (mips16_extended_frag (fragp, NULL, stretch)) |
252b5132 RH |
12906 | { |
12907 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
12908 | return 0; | |
12909 | fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype); | |
12910 | return 2; | |
12911 | } | |
12912 | else | |
12913 | { | |
12914 | if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
12915 | return 0; | |
12916 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype); | |
12917 | return -2; | |
12918 | } | |
12919 | ||
12920 | return 0; | |
12921 | } | |
12922 | ||
12923 | /* Convert a machine dependent frag. */ | |
12924 | ||
12925 | void | |
17a2f251 | 12926 | md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp) |
252b5132 | 12927 | { |
4a6a3df4 AO |
12928 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
12929 | { | |
12930 | bfd_byte *buf; | |
12931 | unsigned long insn; | |
12932 | expressionS exp; | |
12933 | fixS *fixp; | |
b34976b6 | 12934 | |
4a6a3df4 AO |
12935 | buf = (bfd_byte *)fragp->fr_literal + fragp->fr_fix; |
12936 | ||
12937 | if (target_big_endian) | |
12938 | insn = bfd_getb32 (buf); | |
12939 | else | |
12940 | insn = bfd_getl32 (buf); | |
b34976b6 | 12941 | |
4a6a3df4 AO |
12942 | if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) |
12943 | { | |
12944 | /* We generate a fixup instead of applying it right now | |
12945 | because, if there are linker relaxations, we're going to | |
12946 | need the relocations. */ | |
12947 | exp.X_op = O_symbol; | |
12948 | exp.X_add_symbol = fragp->fr_symbol; | |
12949 | exp.X_add_number = fragp->fr_offset; | |
12950 | ||
12951 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
0b25d3e6 AO |
12952 | 4, &exp, 1, |
12953 | BFD_RELOC_16_PCREL_S2); | |
4a6a3df4 AO |
12954 | fixp->fx_file = fragp->fr_file; |
12955 | fixp->fx_line = fragp->fr_line; | |
b34976b6 | 12956 | |
17a2f251 | 12957 | md_number_to_chars (buf, insn, 4); |
4a6a3df4 AO |
12958 | buf += 4; |
12959 | } | |
12960 | else | |
12961 | { | |
12962 | int i; | |
12963 | ||
12964 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
12965 | _("relaxed out-of-range branch into a jump")); | |
12966 | ||
12967 | if (RELAX_BRANCH_UNCOND (fragp->fr_subtype)) | |
12968 | goto uncond; | |
12969 | ||
12970 | if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
12971 | { | |
12972 | /* Reverse the branch. */ | |
12973 | switch ((insn >> 28) & 0xf) | |
12974 | { | |
12975 | case 4: | |
12976 | /* bc[0-3][tf]l? and bc1any[24][ft] instructions can | |
12977 | have the condition reversed by tweaking a single | |
12978 | bit, and their opcodes all have 0x4???????. */ | |
12979 | assert ((insn & 0xf1000000) == 0x41000000); | |
12980 | insn ^= 0x00010000; | |
12981 | break; | |
12982 | ||
12983 | case 0: | |
12984 | /* bltz 0x04000000 bgez 0x04010000 | |
12985 | bltzal 0x04100000 bgezal 0x04110000 */ | |
12986 | assert ((insn & 0xfc0e0000) == 0x04000000); | |
12987 | insn ^= 0x00010000; | |
12988 | break; | |
b34976b6 | 12989 | |
4a6a3df4 AO |
12990 | case 1: |
12991 | /* beq 0x10000000 bne 0x14000000 | |
12992 | blez 0x18000000 bgtz 0x1c000000 */ | |
12993 | insn ^= 0x04000000; | |
12994 | break; | |
12995 | ||
12996 | default: | |
12997 | abort (); | |
12998 | } | |
12999 | } | |
13000 | ||
13001 | if (RELAX_BRANCH_LINK (fragp->fr_subtype)) | |
13002 | { | |
13003 | /* Clear the and-link bit. */ | |
13004 | assert ((insn & 0xfc1c0000) == 0x04100000); | |
13005 | ||
13006 | /* bltzal 0x04100000 bgezal 0x04110000 | |
13007 | bltzall 0x04120000 bgezall 0x04130000 */ | |
13008 | insn &= ~0x00100000; | |
13009 | } | |
13010 | ||
13011 | /* Branch over the branch (if the branch was likely) or the | |
13012 | full jump (not likely case). Compute the offset from the | |
13013 | current instruction to branch to. */ | |
13014 | if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
13015 | i = 16; | |
13016 | else | |
13017 | { | |
13018 | /* How many bytes in instructions we've already emitted? */ | |
13019 | i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix; | |
13020 | /* How many bytes in instructions from here to the end? */ | |
13021 | i = fragp->fr_var - i; | |
13022 | } | |
13023 | /* Convert to instruction count. */ | |
13024 | i >>= 2; | |
13025 | /* Branch counts from the next instruction. */ | |
b34976b6 | 13026 | i--; |
4a6a3df4 AO |
13027 | insn |= i; |
13028 | /* Branch over the jump. */ | |
17a2f251 | 13029 | md_number_to_chars (buf, insn, 4); |
4a6a3df4 AO |
13030 | buf += 4; |
13031 | ||
13032 | /* Nop */ | |
17a2f251 | 13033 | md_number_to_chars (buf, 0, 4); |
4a6a3df4 AO |
13034 | buf += 4; |
13035 | ||
13036 | if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
13037 | { | |
13038 | /* beql $0, $0, 2f */ | |
13039 | insn = 0x50000000; | |
13040 | /* Compute the PC offset from the current instruction to | |
13041 | the end of the variable frag. */ | |
13042 | /* How many bytes in instructions we've already emitted? */ | |
13043 | i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix; | |
13044 | /* How many bytes in instructions from here to the end? */ | |
13045 | i = fragp->fr_var - i; | |
13046 | /* Convert to instruction count. */ | |
13047 | i >>= 2; | |
13048 | /* Don't decrement i, because we want to branch over the | |
13049 | delay slot. */ | |
13050 | ||
13051 | insn |= i; | |
17a2f251 | 13052 | md_number_to_chars (buf, insn, 4); |
4a6a3df4 AO |
13053 | buf += 4; |
13054 | ||
17a2f251 | 13055 | md_number_to_chars (buf, 0, 4); |
4a6a3df4 AO |
13056 | buf += 4; |
13057 | } | |
13058 | ||
13059 | uncond: | |
13060 | if (mips_pic == NO_PIC) | |
13061 | { | |
13062 | /* j or jal. */ | |
13063 | insn = (RELAX_BRANCH_LINK (fragp->fr_subtype) | |
13064 | ? 0x0c000000 : 0x08000000); | |
13065 | exp.X_op = O_symbol; | |
13066 | exp.X_add_symbol = fragp->fr_symbol; | |
13067 | exp.X_add_number = fragp->fr_offset; | |
13068 | ||
13069 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
13070 | 4, &exp, 0, BFD_RELOC_MIPS_JMP); | |
13071 | fixp->fx_file = fragp->fr_file; | |
13072 | fixp->fx_line = fragp->fr_line; | |
13073 | ||
17a2f251 | 13074 | md_number_to_chars (buf, insn, 4); |
4a6a3df4 AO |
13075 | buf += 4; |
13076 | } | |
13077 | else | |
13078 | { | |
13079 | /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */ | |
13080 | insn = HAVE_64BIT_ADDRESSES ? 0xdf810000 : 0x8f810000; | |
13081 | exp.X_op = O_symbol; | |
13082 | exp.X_add_symbol = fragp->fr_symbol; | |
13083 | exp.X_add_number = fragp->fr_offset; | |
13084 | ||
13085 | if (fragp->fr_offset) | |
13086 | { | |
13087 | exp.X_add_symbol = make_expr_symbol (&exp); | |
13088 | exp.X_add_number = 0; | |
13089 | } | |
13090 | ||
13091 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
13092 | 4, &exp, 0, BFD_RELOC_MIPS_GOT16); | |
13093 | fixp->fx_file = fragp->fr_file; | |
13094 | fixp->fx_line = fragp->fr_line; | |
13095 | ||
17a2f251 | 13096 | md_number_to_chars (buf, insn, 4); |
4a6a3df4 | 13097 | buf += 4; |
b34976b6 | 13098 | |
4a6a3df4 AO |
13099 | if (mips_opts.isa == ISA_MIPS1) |
13100 | { | |
13101 | /* nop */ | |
17a2f251 | 13102 | md_number_to_chars (buf, 0, 4); |
4a6a3df4 AO |
13103 | buf += 4; |
13104 | } | |
13105 | ||
13106 | /* d/addiu $at, $at, <sym> R_MIPS_LO16 */ | |
13107 | insn = HAVE_64BIT_ADDRESSES ? 0x64210000 : 0x24210000; | |
13108 | ||
13109 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
13110 | 4, &exp, 0, BFD_RELOC_LO16); | |
13111 | fixp->fx_file = fragp->fr_file; | |
13112 | fixp->fx_line = fragp->fr_line; | |
b34976b6 | 13113 | |
17a2f251 | 13114 | md_number_to_chars (buf, insn, 4); |
4a6a3df4 AO |
13115 | buf += 4; |
13116 | ||
13117 | /* j(al)r $at. */ | |
13118 | if (RELAX_BRANCH_LINK (fragp->fr_subtype)) | |
13119 | insn = 0x0020f809; | |
13120 | else | |
13121 | insn = 0x00200008; | |
13122 | ||
17a2f251 | 13123 | md_number_to_chars (buf, insn, 4); |
4a6a3df4 AO |
13124 | buf += 4; |
13125 | } | |
13126 | } | |
13127 | ||
13128 | assert (buf == (bfd_byte *)fragp->fr_literal | |
13129 | + fragp->fr_fix + fragp->fr_var); | |
13130 | ||
13131 | fragp->fr_fix += fragp->fr_var; | |
13132 | ||
13133 | return; | |
13134 | } | |
13135 | ||
252b5132 RH |
13136 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
13137 | { | |
13138 | int type; | |
13139 | register const struct mips16_immed_operand *op; | |
b34976b6 | 13140 | bfd_boolean small, ext; |
252b5132 RH |
13141 | offsetT val; |
13142 | bfd_byte *buf; | |
13143 | unsigned long insn; | |
b34976b6 | 13144 | bfd_boolean use_extend; |
252b5132 RH |
13145 | unsigned short extend; |
13146 | ||
13147 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
13148 | op = mips16_immed_operands; | |
13149 | while (op->type != type) | |
13150 | ++op; | |
13151 | ||
13152 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
13153 | { | |
b34976b6 AM |
13154 | small = FALSE; |
13155 | ext = TRUE; | |
252b5132 RH |
13156 | } |
13157 | else | |
13158 | { | |
b34976b6 AM |
13159 | small = TRUE; |
13160 | ext = FALSE; | |
252b5132 RH |
13161 | } |
13162 | ||
6386f3a7 | 13163 | resolve_symbol_value (fragp->fr_symbol); |
252b5132 RH |
13164 | val = S_GET_VALUE (fragp->fr_symbol); |
13165 | if (op->pcrel) | |
13166 | { | |
13167 | addressT addr; | |
13168 | ||
13169 | addr = fragp->fr_address + fragp->fr_fix; | |
13170 | ||
13171 | /* The rules for the base address of a PC relative reloc are | |
13172 | complicated; see mips16_extended_frag. */ | |
13173 | if (type == 'p' || type == 'q') | |
13174 | { | |
13175 | addr += 2; | |
13176 | if (ext) | |
13177 | addr += 2; | |
13178 | /* Ignore the low bit in the target, since it will be | |
13179 | set for a text label. */ | |
13180 | if ((val & 1) != 0) | |
13181 | --val; | |
13182 | } | |
13183 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) | |
13184 | addr -= 4; | |
13185 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
13186 | addr -= 2; | |
13187 | ||
13188 | addr &= ~ (addressT) ((1 << op->shift) - 1); | |
13189 | val -= addr; | |
13190 | ||
13191 | /* Make sure the section winds up with the alignment we have | |
13192 | assumed. */ | |
13193 | if (op->shift > 0) | |
13194 | record_alignment (asec, op->shift); | |
13195 | } | |
13196 | ||
13197 | if (ext | |
13198 | && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype) | |
13199 | || RELAX_MIPS16_DSLOT (fragp->fr_subtype))) | |
13200 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
13201 | _("extended instruction in delay slot")); | |
13202 | ||
13203 | buf = (bfd_byte *) (fragp->fr_literal + fragp->fr_fix); | |
13204 | ||
13205 | if (target_big_endian) | |
13206 | insn = bfd_getb16 (buf); | |
13207 | else | |
13208 | insn = bfd_getl16 (buf); | |
13209 | ||
13210 | mips16_immed (fragp->fr_file, fragp->fr_line, type, val, | |
13211 | RELAX_MIPS16_USER_EXT (fragp->fr_subtype), | |
13212 | small, ext, &insn, &use_extend, &extend); | |
13213 | ||
13214 | if (use_extend) | |
13215 | { | |
17a2f251 | 13216 | md_number_to_chars (buf, 0xf000 | extend, 2); |
252b5132 RH |
13217 | fragp->fr_fix += 2; |
13218 | buf += 2; | |
13219 | } | |
13220 | ||
17a2f251 | 13221 | md_number_to_chars (buf, insn, 2); |
252b5132 RH |
13222 | fragp->fr_fix += 2; |
13223 | buf += 2; | |
13224 | } | |
13225 | else | |
13226 | { | |
4d7206a2 RS |
13227 | int first, second; |
13228 | fixS *fixp; | |
252b5132 | 13229 | |
4d7206a2 RS |
13230 | first = RELAX_FIRST (fragp->fr_subtype); |
13231 | second = RELAX_SECOND (fragp->fr_subtype); | |
13232 | fixp = (fixS *) fragp->fr_opcode; | |
252b5132 | 13233 | |
584892a6 RS |
13234 | /* Possibly emit a warning if we've chosen the longer option. */ |
13235 | if (((fragp->fr_subtype & RELAX_USE_SECOND) != 0) | |
13236 | == ((fragp->fr_subtype & RELAX_SECOND_LONGER) != 0)) | |
13237 | { | |
13238 | const char *msg = macro_warning (fragp->fr_subtype); | |
13239 | if (msg != 0) | |
13240 | as_warn_where (fragp->fr_file, fragp->fr_line, msg); | |
13241 | } | |
13242 | ||
4d7206a2 RS |
13243 | /* Go through all the fixups for the first sequence. Disable them |
13244 | (by marking them as done) if we're going to use the second | |
13245 | sequence instead. */ | |
13246 | while (fixp | |
13247 | && fixp->fx_frag == fragp | |
13248 | && fixp->fx_where < fragp->fr_fix - second) | |
13249 | { | |
13250 | if (fragp->fr_subtype & RELAX_USE_SECOND) | |
13251 | fixp->fx_done = 1; | |
13252 | fixp = fixp->fx_next; | |
13253 | } | |
252b5132 | 13254 | |
4d7206a2 RS |
13255 | /* Go through the fixups for the second sequence. Disable them if |
13256 | we're going to use the first sequence, otherwise adjust their | |
13257 | addresses to account for the relaxation. */ | |
13258 | while (fixp && fixp->fx_frag == fragp) | |
13259 | { | |
13260 | if (fragp->fr_subtype & RELAX_USE_SECOND) | |
13261 | fixp->fx_where -= first; | |
13262 | else | |
13263 | fixp->fx_done = 1; | |
13264 | fixp = fixp->fx_next; | |
13265 | } | |
13266 | ||
13267 | /* Now modify the frag contents. */ | |
13268 | if (fragp->fr_subtype & RELAX_USE_SECOND) | |
13269 | { | |
13270 | char *start; | |
13271 | ||
13272 | start = fragp->fr_literal + fragp->fr_fix - first - second; | |
13273 | memmove (start, start + first, second); | |
13274 | fragp->fr_fix -= first; | |
13275 | } | |
13276 | else | |
13277 | fragp->fr_fix -= second; | |
252b5132 RH |
13278 | } |
13279 | } | |
13280 | ||
13281 | #ifdef OBJ_ELF | |
13282 | ||
13283 | /* This function is called after the relocs have been generated. | |
13284 | We've been storing mips16 text labels as odd. Here we convert them | |
13285 | back to even for the convenience of the debugger. */ | |
13286 | ||
13287 | void | |
17a2f251 | 13288 | mips_frob_file_after_relocs (void) |
252b5132 RH |
13289 | { |
13290 | asymbol **syms; | |
13291 | unsigned int count, i; | |
13292 | ||
13293 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
13294 | return; | |
13295 | ||
13296 | syms = bfd_get_outsymbols (stdoutput); | |
13297 | count = bfd_get_symcount (stdoutput); | |
13298 | for (i = 0; i < count; i++, syms++) | |
13299 | { | |
13300 | if (elf_symbol (*syms)->internal_elf_sym.st_other == STO_MIPS16 | |
13301 | && ((*syms)->value & 1) != 0) | |
13302 | { | |
13303 | (*syms)->value &= ~1; | |
13304 | /* If the symbol has an odd size, it was probably computed | |
13305 | incorrectly, so adjust that as well. */ | |
13306 | if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0) | |
13307 | ++elf_symbol (*syms)->internal_elf_sym.st_size; | |
13308 | } | |
13309 | } | |
13310 | } | |
13311 | ||
13312 | #endif | |
13313 | ||
13314 | /* This function is called whenever a label is defined. It is used | |
13315 | when handling branch delays; if a branch has a label, we assume we | |
13316 | can not move it. */ | |
13317 | ||
13318 | void | |
17a2f251 | 13319 | mips_define_label (symbolS *sym) |
252b5132 RH |
13320 | { |
13321 | struct insn_label_list *l; | |
13322 | ||
13323 | if (free_insn_labels == NULL) | |
13324 | l = (struct insn_label_list *) xmalloc (sizeof *l); | |
13325 | else | |
13326 | { | |
13327 | l = free_insn_labels; | |
13328 | free_insn_labels = l->next; | |
13329 | } | |
13330 | ||
13331 | l->label = sym; | |
13332 | l->next = insn_labels; | |
13333 | insn_labels = l; | |
13334 | } | |
13335 | \f | |
13336 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
13337 | ||
13338 | /* Some special processing for a MIPS ELF file. */ | |
13339 | ||
13340 | void | |
17a2f251 | 13341 | mips_elf_final_processing (void) |
252b5132 RH |
13342 | { |
13343 | /* Write out the register information. */ | |
316f5878 | 13344 | if (mips_abi != N64_ABI) |
252b5132 RH |
13345 | { |
13346 | Elf32_RegInfo s; | |
13347 | ||
13348 | s.ri_gprmask = mips_gprmask; | |
13349 | s.ri_cprmask[0] = mips_cprmask[0]; | |
13350 | s.ri_cprmask[1] = mips_cprmask[1]; | |
13351 | s.ri_cprmask[2] = mips_cprmask[2]; | |
13352 | s.ri_cprmask[3] = mips_cprmask[3]; | |
13353 | /* The gp_value field is set by the MIPS ELF backend. */ | |
13354 | ||
13355 | bfd_mips_elf32_swap_reginfo_out (stdoutput, &s, | |
13356 | ((Elf32_External_RegInfo *) | |
13357 | mips_regmask_frag)); | |
13358 | } | |
13359 | else | |
13360 | { | |
13361 | Elf64_Internal_RegInfo s; | |
13362 | ||
13363 | s.ri_gprmask = mips_gprmask; | |
13364 | s.ri_pad = 0; | |
13365 | s.ri_cprmask[0] = mips_cprmask[0]; | |
13366 | s.ri_cprmask[1] = mips_cprmask[1]; | |
13367 | s.ri_cprmask[2] = mips_cprmask[2]; | |
13368 | s.ri_cprmask[3] = mips_cprmask[3]; | |
13369 | /* The gp_value field is set by the MIPS ELF backend. */ | |
13370 | ||
13371 | bfd_mips_elf64_swap_reginfo_out (stdoutput, &s, | |
13372 | ((Elf64_External_RegInfo *) | |
13373 | mips_regmask_frag)); | |
13374 | } | |
13375 | ||
13376 | /* Set the MIPS ELF flag bits. FIXME: There should probably be some | |
13377 | sort of BFD interface for this. */ | |
13378 | if (mips_any_noreorder) | |
13379 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER; | |
13380 | if (mips_pic != NO_PIC) | |
143d77c5 | 13381 | { |
252b5132 | 13382 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC; |
143d77c5 EC |
13383 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC; |
13384 | } | |
13385 | if (mips_abicalls) | |
13386 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC; | |
252b5132 | 13387 | |
98d3f06f | 13388 | /* Set MIPS ELF flags for ASEs. */ |
a4672219 TS |
13389 | if (file_ase_mips16) |
13390 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16; | |
1f25f5d3 CD |
13391 | #if 0 /* XXX FIXME */ |
13392 | if (file_ase_mips3d) | |
13393 | elf_elfheader (stdoutput)->e_flags |= ???; | |
13394 | #endif | |
deec1734 CD |
13395 | if (file_ase_mdmx) |
13396 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX; | |
1f25f5d3 | 13397 | |
bdaaa2e1 | 13398 | /* Set the MIPS ELF ABI flags. */ |
316f5878 | 13399 | if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32) |
252b5132 | 13400 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32; |
316f5878 | 13401 | else if (mips_abi == O64_ABI) |
252b5132 | 13402 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64; |
316f5878 | 13403 | else if (mips_abi == EABI_ABI) |
252b5132 | 13404 | { |
316f5878 | 13405 | if (!file_mips_gp32) |
252b5132 RH |
13406 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64; |
13407 | else | |
13408 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32; | |
13409 | } | |
316f5878 | 13410 | else if (mips_abi == N32_ABI) |
be00bddd TS |
13411 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2; |
13412 | ||
c9914766 | 13413 | /* Nothing to do for N64_ABI. */ |
252b5132 RH |
13414 | |
13415 | if (mips_32bitmode) | |
13416 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE; | |
13417 | } | |
13418 | ||
13419 | #endif /* OBJ_ELF || OBJ_MAYBE_ELF */ | |
13420 | \f | |
beae10d5 KH |
13421 | typedef struct proc { |
13422 | symbolS *isym; | |
13423 | unsigned long reg_mask; | |
13424 | unsigned long reg_offset; | |
13425 | unsigned long fpreg_mask; | |
13426 | unsigned long fpreg_offset; | |
13427 | unsigned long frame_offset; | |
13428 | unsigned long frame_reg; | |
13429 | unsigned long pc_reg; | |
13430 | } procS; | |
252b5132 RH |
13431 | |
13432 | static procS cur_proc; | |
13433 | static procS *cur_proc_ptr; | |
13434 | static int numprocs; | |
13435 | ||
0a9ef439 | 13436 | /* Fill in an rs_align_code fragment. */ |
a19d8eb0 | 13437 | |
0a9ef439 | 13438 | void |
17a2f251 | 13439 | mips_handle_align (fragS *fragp) |
a19d8eb0 | 13440 | { |
0a9ef439 RH |
13441 | if (fragp->fr_type != rs_align_code) |
13442 | return; | |
13443 | ||
13444 | if (mips_opts.mips16) | |
a19d8eb0 CP |
13445 | { |
13446 | static const unsigned char be_nop[] = { 0x65, 0x00 }; | |
13447 | static const unsigned char le_nop[] = { 0x00, 0x65 }; | |
13448 | ||
0a9ef439 RH |
13449 | int bytes; |
13450 | char *p; | |
a19d8eb0 | 13451 | |
0a9ef439 RH |
13452 | bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix; |
13453 | p = fragp->fr_literal + fragp->fr_fix; | |
13454 | ||
13455 | if (bytes & 1) | |
13456 | { | |
13457 | *p++ = 0; | |
f9419b05 | 13458 | fragp->fr_fix++; |
0a9ef439 RH |
13459 | } |
13460 | ||
13461 | memcpy (p, (target_big_endian ? be_nop : le_nop), 2); | |
13462 | fragp->fr_var = 2; | |
a19d8eb0 CP |
13463 | } |
13464 | ||
0a9ef439 | 13465 | /* For mips32, a nop is a zero, which we trivially get by doing nothing. */ |
a19d8eb0 CP |
13466 | } |
13467 | ||
252b5132 | 13468 | static void |
17a2f251 | 13469 | md_obj_begin (void) |
252b5132 RH |
13470 | { |
13471 | } | |
13472 | ||
13473 | static void | |
17a2f251 | 13474 | md_obj_end (void) |
252b5132 RH |
13475 | { |
13476 | /* check for premature end, nesting errors, etc */ | |
13477 | if (cur_proc_ptr) | |
9a41af64 | 13478 | as_warn (_("missing .end at end of assembly")); |
252b5132 RH |
13479 | } |
13480 | ||
13481 | static long | |
17a2f251 | 13482 | get_number (void) |
252b5132 RH |
13483 | { |
13484 | int negative = 0; | |
13485 | long val = 0; | |
13486 | ||
13487 | if (*input_line_pointer == '-') | |
13488 | { | |
13489 | ++input_line_pointer; | |
13490 | negative = 1; | |
13491 | } | |
3882b010 | 13492 | if (!ISDIGIT (*input_line_pointer)) |
956cd1d6 | 13493 | as_bad (_("expected simple number")); |
252b5132 RH |
13494 | if (input_line_pointer[0] == '0') |
13495 | { | |
13496 | if (input_line_pointer[1] == 'x') | |
13497 | { | |
13498 | input_line_pointer += 2; | |
3882b010 | 13499 | while (ISXDIGIT (*input_line_pointer)) |
252b5132 RH |
13500 | { |
13501 | val <<= 4; | |
13502 | val |= hex_value (*input_line_pointer++); | |
13503 | } | |
13504 | return negative ? -val : val; | |
13505 | } | |
13506 | else | |
13507 | { | |
13508 | ++input_line_pointer; | |
3882b010 | 13509 | while (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
13510 | { |
13511 | val <<= 3; | |
13512 | val |= *input_line_pointer++ - '0'; | |
13513 | } | |
13514 | return negative ? -val : val; | |
13515 | } | |
13516 | } | |
3882b010 | 13517 | if (!ISDIGIT (*input_line_pointer)) |
252b5132 RH |
13518 | { |
13519 | printf (_(" *input_line_pointer == '%c' 0x%02x\n"), | |
13520 | *input_line_pointer, *input_line_pointer); | |
956cd1d6 | 13521 | as_warn (_("invalid number")); |
252b5132 RH |
13522 | return -1; |
13523 | } | |
3882b010 | 13524 | while (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
13525 | { |
13526 | val *= 10; | |
13527 | val += *input_line_pointer++ - '0'; | |
13528 | } | |
13529 | return negative ? -val : val; | |
13530 | } | |
13531 | ||
13532 | /* The .file directive; just like the usual .file directive, but there | |
c5dd6aab DJ |
13533 | is an initial number which is the ECOFF file index. In the non-ECOFF |
13534 | case .file implies DWARF-2. */ | |
13535 | ||
13536 | static void | |
17a2f251 | 13537 | s_mips_file (int x ATTRIBUTE_UNUSED) |
c5dd6aab | 13538 | { |
ecb4347a DJ |
13539 | static int first_file_directive = 0; |
13540 | ||
c5dd6aab DJ |
13541 | if (ECOFF_DEBUGGING) |
13542 | { | |
13543 | get_number (); | |
13544 | s_app_file (0); | |
13545 | } | |
13546 | else | |
ecb4347a DJ |
13547 | { |
13548 | char *filename; | |
13549 | ||
13550 | filename = dwarf2_directive_file (0); | |
13551 | ||
13552 | /* Versions of GCC up to 3.1 start files with a ".file" | |
13553 | directive even for stabs output. Make sure that this | |
13554 | ".file" is handled. Note that you need a version of GCC | |
13555 | after 3.1 in order to support DWARF-2 on MIPS. */ | |
13556 | if (filename != NULL && ! first_file_directive) | |
13557 | { | |
13558 | (void) new_logical_line (filename, -1); | |
c04f5787 | 13559 | s_app_file_string (filename, 0); |
ecb4347a DJ |
13560 | } |
13561 | first_file_directive = 1; | |
13562 | } | |
c5dd6aab DJ |
13563 | } |
13564 | ||
13565 | /* The .loc directive, implying DWARF-2. */ | |
252b5132 RH |
13566 | |
13567 | static void | |
17a2f251 | 13568 | s_mips_loc (int x ATTRIBUTE_UNUSED) |
252b5132 | 13569 | { |
c5dd6aab DJ |
13570 | if (!ECOFF_DEBUGGING) |
13571 | dwarf2_directive_loc (0); | |
252b5132 RH |
13572 | } |
13573 | ||
252b5132 RH |
13574 | /* The .end directive. */ |
13575 | ||
13576 | static void | |
17a2f251 | 13577 | s_mips_end (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
13578 | { |
13579 | symbolS *p; | |
252b5132 | 13580 | |
7a621144 DJ |
13581 | /* Following functions need their own .frame and .cprestore directives. */ |
13582 | mips_frame_reg_valid = 0; | |
13583 | mips_cprestore_valid = 0; | |
13584 | ||
252b5132 RH |
13585 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
13586 | { | |
13587 | p = get_symbol (); | |
13588 | demand_empty_rest_of_line (); | |
13589 | } | |
13590 | else | |
13591 | p = NULL; | |
13592 | ||
14949570 | 13593 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0) |
252b5132 RH |
13594 | as_warn (_(".end not in text section")); |
13595 | ||
13596 | if (!cur_proc_ptr) | |
13597 | { | |
13598 | as_warn (_(".end directive without a preceding .ent directive.")); | |
13599 | demand_empty_rest_of_line (); | |
13600 | return; | |
13601 | } | |
13602 | ||
13603 | if (p != NULL) | |
13604 | { | |
13605 | assert (S_GET_NAME (p)); | |
13606 | if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->isym))) | |
13607 | as_warn (_(".end symbol does not match .ent symbol.")); | |
ecb4347a DJ |
13608 | |
13609 | if (debug_type == DEBUG_STABS) | |
13610 | stabs_generate_asm_endfunc (S_GET_NAME (p), | |
13611 | S_GET_NAME (p)); | |
252b5132 RH |
13612 | } |
13613 | else | |
13614 | as_warn (_(".end directive missing or unknown symbol")); | |
13615 | ||
ecb4347a DJ |
13616 | #ifdef OBJ_ELF |
13617 | /* Generate a .pdr section. */ | |
dcd410fe RO |
13618 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING |
13619 | && mips_flag_pdr) | |
ecb4347a DJ |
13620 | { |
13621 | segT saved_seg = now_seg; | |
13622 | subsegT saved_subseg = now_subseg; | |
13623 | valueT dot; | |
13624 | expressionS exp; | |
13625 | char *fragp; | |
252b5132 | 13626 | |
ecb4347a | 13627 | dot = frag_now_fix (); |
252b5132 RH |
13628 | |
13629 | #ifdef md_flush_pending_output | |
ecb4347a | 13630 | md_flush_pending_output (); |
252b5132 RH |
13631 | #endif |
13632 | ||
ecb4347a DJ |
13633 | assert (pdr_seg); |
13634 | subseg_set (pdr_seg, 0); | |
252b5132 | 13635 | |
ecb4347a DJ |
13636 | /* Write the symbol. */ |
13637 | exp.X_op = O_symbol; | |
13638 | exp.X_add_symbol = p; | |
13639 | exp.X_add_number = 0; | |
13640 | emit_expr (&exp, 4); | |
252b5132 | 13641 | |
ecb4347a | 13642 | fragp = frag_more (7 * 4); |
252b5132 | 13643 | |
17a2f251 TS |
13644 | md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4); |
13645 | md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4); | |
13646 | md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4); | |
13647 | md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4); | |
13648 | md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4); | |
13649 | md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4); | |
13650 | md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4); | |
252b5132 | 13651 | |
ecb4347a DJ |
13652 | subseg_set (saved_seg, saved_subseg); |
13653 | } | |
13654 | #endif /* OBJ_ELF */ | |
252b5132 RH |
13655 | |
13656 | cur_proc_ptr = NULL; | |
13657 | } | |
13658 | ||
13659 | /* The .aent and .ent directives. */ | |
13660 | ||
13661 | static void | |
17a2f251 | 13662 | s_mips_ent (int aent) |
252b5132 | 13663 | { |
252b5132 | 13664 | symbolS *symbolP; |
252b5132 RH |
13665 | |
13666 | symbolP = get_symbol (); | |
13667 | if (*input_line_pointer == ',') | |
f9419b05 | 13668 | ++input_line_pointer; |
252b5132 | 13669 | SKIP_WHITESPACE (); |
3882b010 | 13670 | if (ISDIGIT (*input_line_pointer) |
d9a62219 | 13671 | || *input_line_pointer == '-') |
874e8986 | 13672 | get_number (); |
252b5132 | 13673 | |
14949570 | 13674 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0) |
252b5132 RH |
13675 | as_warn (_(".ent or .aent not in text section.")); |
13676 | ||
13677 | if (!aent && cur_proc_ptr) | |
9a41af64 | 13678 | as_warn (_("missing .end")); |
252b5132 RH |
13679 | |
13680 | if (!aent) | |
13681 | { | |
7a621144 DJ |
13682 | /* This function needs its own .frame and .cprestore directives. */ |
13683 | mips_frame_reg_valid = 0; | |
13684 | mips_cprestore_valid = 0; | |
13685 | ||
252b5132 RH |
13686 | cur_proc_ptr = &cur_proc; |
13687 | memset (cur_proc_ptr, '\0', sizeof (procS)); | |
13688 | ||
13689 | cur_proc_ptr->isym = symbolP; | |
13690 | ||
49309057 | 13691 | symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION; |
252b5132 | 13692 | |
f9419b05 | 13693 | ++numprocs; |
ecb4347a DJ |
13694 | |
13695 | if (debug_type == DEBUG_STABS) | |
13696 | stabs_generate_asm_func (S_GET_NAME (symbolP), | |
13697 | S_GET_NAME (symbolP)); | |
252b5132 RH |
13698 | } |
13699 | ||
13700 | demand_empty_rest_of_line (); | |
13701 | } | |
13702 | ||
13703 | /* The .frame directive. If the mdebug section is present (IRIX 5 native) | |
bdaaa2e1 | 13704 | then ecoff.c (ecoff_directive_frame) is used. For embedded targets, |
252b5132 | 13705 | s_mips_frame is used so that we can set the PDR information correctly. |
bdaaa2e1 | 13706 | We can't use the ecoff routines because they make reference to the ecoff |
252b5132 RH |
13707 | symbol table (in the mdebug section). */ |
13708 | ||
13709 | static void | |
17a2f251 | 13710 | s_mips_frame (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 13711 | { |
ecb4347a DJ |
13712 | #ifdef OBJ_ELF |
13713 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING) | |
13714 | { | |
13715 | long val; | |
252b5132 | 13716 | |
ecb4347a DJ |
13717 | if (cur_proc_ptr == (procS *) NULL) |
13718 | { | |
13719 | as_warn (_(".frame outside of .ent")); | |
13720 | demand_empty_rest_of_line (); | |
13721 | return; | |
13722 | } | |
252b5132 | 13723 | |
ecb4347a DJ |
13724 | cur_proc_ptr->frame_reg = tc_get_register (1); |
13725 | ||
13726 | SKIP_WHITESPACE (); | |
13727 | if (*input_line_pointer++ != ',' | |
13728 | || get_absolute_expression_and_terminator (&val) != ',') | |
13729 | { | |
13730 | as_warn (_("Bad .frame directive")); | |
13731 | --input_line_pointer; | |
13732 | demand_empty_rest_of_line (); | |
13733 | return; | |
13734 | } | |
252b5132 | 13735 | |
ecb4347a DJ |
13736 | cur_proc_ptr->frame_offset = val; |
13737 | cur_proc_ptr->pc_reg = tc_get_register (0); | |
252b5132 | 13738 | |
252b5132 | 13739 | demand_empty_rest_of_line (); |
252b5132 | 13740 | } |
ecb4347a DJ |
13741 | else |
13742 | #endif /* OBJ_ELF */ | |
13743 | s_ignore (ignore); | |
252b5132 RH |
13744 | } |
13745 | ||
bdaaa2e1 KH |
13746 | /* The .fmask and .mask directives. If the mdebug section is present |
13747 | (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For | |
252b5132 | 13748 | embedded targets, s_mips_mask is used so that we can set the PDR |
bdaaa2e1 | 13749 | information correctly. We can't use the ecoff routines because they |
252b5132 RH |
13750 | make reference to the ecoff symbol table (in the mdebug section). */ |
13751 | ||
13752 | static void | |
17a2f251 | 13753 | s_mips_mask (int reg_type) |
252b5132 | 13754 | { |
ecb4347a DJ |
13755 | #ifdef OBJ_ELF |
13756 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING) | |
252b5132 | 13757 | { |
ecb4347a | 13758 | long mask, off; |
252b5132 | 13759 | |
ecb4347a DJ |
13760 | if (cur_proc_ptr == (procS *) NULL) |
13761 | { | |
13762 | as_warn (_(".mask/.fmask outside of .ent")); | |
13763 | demand_empty_rest_of_line (); | |
13764 | return; | |
13765 | } | |
252b5132 | 13766 | |
ecb4347a DJ |
13767 | if (get_absolute_expression_and_terminator (&mask) != ',') |
13768 | { | |
13769 | as_warn (_("Bad .mask/.fmask directive")); | |
13770 | --input_line_pointer; | |
13771 | demand_empty_rest_of_line (); | |
13772 | return; | |
13773 | } | |
252b5132 | 13774 | |
ecb4347a DJ |
13775 | off = get_absolute_expression (); |
13776 | ||
13777 | if (reg_type == 'F') | |
13778 | { | |
13779 | cur_proc_ptr->fpreg_mask = mask; | |
13780 | cur_proc_ptr->fpreg_offset = off; | |
13781 | } | |
13782 | else | |
13783 | { | |
13784 | cur_proc_ptr->reg_mask = mask; | |
13785 | cur_proc_ptr->reg_offset = off; | |
13786 | } | |
13787 | ||
13788 | demand_empty_rest_of_line (); | |
252b5132 RH |
13789 | } |
13790 | else | |
ecb4347a DJ |
13791 | #endif /* OBJ_ELF */ |
13792 | s_ignore (reg_type); | |
252b5132 RH |
13793 | } |
13794 | ||
316f5878 RS |
13795 | /* A table describing all the processors gas knows about. Names are |
13796 | matched in the order listed. | |
e7af610e | 13797 | |
316f5878 RS |
13798 | To ease comparison, please keep this table in the same order as |
13799 | gcc's mips_cpu_info_table[]. */ | |
e972090a NC |
13800 | static const struct mips_cpu_info mips_cpu_info_table[] = |
13801 | { | |
316f5878 RS |
13802 | /* Entries for generic ISAs */ |
13803 | { "mips1", 1, ISA_MIPS1, CPU_R3000 }, | |
13804 | { "mips2", 1, ISA_MIPS2, CPU_R6000 }, | |
13805 | { "mips3", 1, ISA_MIPS3, CPU_R4000 }, | |
13806 | { "mips4", 1, ISA_MIPS4, CPU_R8000 }, | |
13807 | { "mips5", 1, ISA_MIPS5, CPU_MIPS5 }, | |
13808 | { "mips32", 1, ISA_MIPS32, CPU_MIPS32 }, | |
af7ee8bf | 13809 | { "mips32r2", 1, ISA_MIPS32R2, CPU_MIPS32R2 }, |
316f5878 | 13810 | { "mips64", 1, ISA_MIPS64, CPU_MIPS64 }, |
5f74bc13 | 13811 | { "mips64r2", 1, ISA_MIPS64R2, CPU_MIPS64R2 }, |
316f5878 RS |
13812 | |
13813 | /* MIPS I */ | |
13814 | { "r3000", 0, ISA_MIPS1, CPU_R3000 }, | |
13815 | { "r2000", 0, ISA_MIPS1, CPU_R3000 }, | |
13816 | { "r3900", 0, ISA_MIPS1, CPU_R3900 }, | |
13817 | ||
13818 | /* MIPS II */ | |
13819 | { "r6000", 0, ISA_MIPS2, CPU_R6000 }, | |
13820 | ||
13821 | /* MIPS III */ | |
13822 | { "r4000", 0, ISA_MIPS3, CPU_R4000 }, | |
13823 | { "r4010", 0, ISA_MIPS2, CPU_R4010 }, | |
13824 | { "vr4100", 0, ISA_MIPS3, CPU_VR4100 }, | |
13825 | { "vr4111", 0, ISA_MIPS3, CPU_R4111 }, | |
60b63b72 RS |
13826 | { "vr4120", 0, ISA_MIPS3, CPU_VR4120 }, |
13827 | { "vr4130", 0, ISA_MIPS3, CPU_VR4120 }, | |
13828 | { "vr4181", 0, ISA_MIPS3, CPU_R4111 }, | |
316f5878 RS |
13829 | { "vr4300", 0, ISA_MIPS3, CPU_R4300 }, |
13830 | { "r4400", 0, ISA_MIPS3, CPU_R4400 }, | |
13831 | { "r4600", 0, ISA_MIPS3, CPU_R4600 }, | |
13832 | { "orion", 0, ISA_MIPS3, CPU_R4600 }, | |
13833 | { "r4650", 0, ISA_MIPS3, CPU_R4650 }, | |
13834 | ||
13835 | /* MIPS IV */ | |
13836 | { "r8000", 0, ISA_MIPS4, CPU_R8000 }, | |
13837 | { "r10000", 0, ISA_MIPS4, CPU_R10000 }, | |
13838 | { "r12000", 0, ISA_MIPS4, CPU_R12000 }, | |
13839 | { "vr5000", 0, ISA_MIPS4, CPU_R5000 }, | |
60b63b72 RS |
13840 | { "vr5400", 0, ISA_MIPS4, CPU_VR5400 }, |
13841 | { "vr5500", 0, ISA_MIPS4, CPU_VR5500 }, | |
316f5878 RS |
13842 | { "rm5200", 0, ISA_MIPS4, CPU_R5000 }, |
13843 | { "rm5230", 0, ISA_MIPS4, CPU_R5000 }, | |
13844 | { "rm5231", 0, ISA_MIPS4, CPU_R5000 }, | |
13845 | { "rm5261", 0, ISA_MIPS4, CPU_R5000 }, | |
13846 | { "rm5721", 0, ISA_MIPS4, CPU_R5000 }, | |
5a7ea749 | 13847 | { "rm7000", 0, ISA_MIPS4, CPU_RM7000 }, |
9a92f48d | 13848 | { "rm9000", 0, ISA_MIPS4, CPU_RM9000 }, |
316f5878 RS |
13849 | |
13850 | /* MIPS 32 */ | |
fef14a42 | 13851 | { "4kc", 0, ISA_MIPS32, CPU_MIPS32 }, |
316f5878 RS |
13852 | { "4km", 0, ISA_MIPS32, CPU_MIPS32 }, |
13853 | { "4kp", 0, ISA_MIPS32, CPU_MIPS32 }, | |
e7af610e | 13854 | |
316f5878 RS |
13855 | /* MIPS 64 */ |
13856 | { "5kc", 0, ISA_MIPS64, CPU_MIPS64 }, | |
13857 | { "20kc", 0, ISA_MIPS64, CPU_MIPS64 }, | |
e7af610e | 13858 | |
c7a23324 | 13859 | /* Broadcom SB-1 CPU core */ |
316f5878 | 13860 | { "sb1", 0, ISA_MIPS64, CPU_SB1 }, |
e7af610e | 13861 | |
316f5878 RS |
13862 | /* End marker */ |
13863 | { NULL, 0, 0, 0 } | |
13864 | }; | |
e7af610e | 13865 | |
84ea6cf2 | 13866 | |
316f5878 RS |
13867 | /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL |
13868 | with a final "000" replaced by "k". Ignore case. | |
e7af610e | 13869 | |
316f5878 | 13870 | Note: this function is shared between GCC and GAS. */ |
c6c98b38 | 13871 | |
b34976b6 | 13872 | static bfd_boolean |
17a2f251 | 13873 | mips_strict_matching_cpu_name_p (const char *canonical, const char *given) |
316f5878 RS |
13874 | { |
13875 | while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical)) | |
13876 | given++, canonical++; | |
13877 | ||
13878 | return ((*given == 0 && *canonical == 0) | |
13879 | || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0)); | |
13880 | } | |
13881 | ||
13882 | ||
13883 | /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied | |
13884 | CPU name. We've traditionally allowed a lot of variation here. | |
13885 | ||
13886 | Note: this function is shared between GCC and GAS. */ | |
13887 | ||
b34976b6 | 13888 | static bfd_boolean |
17a2f251 | 13889 | mips_matching_cpu_name_p (const char *canonical, const char *given) |
316f5878 RS |
13890 | { |
13891 | /* First see if the name matches exactly, or with a final "000" | |
13892 | turned into "k". */ | |
13893 | if (mips_strict_matching_cpu_name_p (canonical, given)) | |
b34976b6 | 13894 | return TRUE; |
316f5878 RS |
13895 | |
13896 | /* If not, try comparing based on numerical designation alone. | |
13897 | See if GIVEN is an unadorned number, or 'r' followed by a number. */ | |
13898 | if (TOLOWER (*given) == 'r') | |
13899 | given++; | |
13900 | if (!ISDIGIT (*given)) | |
b34976b6 | 13901 | return FALSE; |
316f5878 RS |
13902 | |
13903 | /* Skip over some well-known prefixes in the canonical name, | |
13904 | hoping to find a number there too. */ | |
13905 | if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r') | |
13906 | canonical += 2; | |
13907 | else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm') | |
13908 | canonical += 2; | |
13909 | else if (TOLOWER (canonical[0]) == 'r') | |
13910 | canonical += 1; | |
13911 | ||
13912 | return mips_strict_matching_cpu_name_p (canonical, given); | |
13913 | } | |
13914 | ||
13915 | ||
13916 | /* Parse an option that takes the name of a processor as its argument. | |
13917 | OPTION is the name of the option and CPU_STRING is the argument. | |
13918 | Return the corresponding processor enumeration if the CPU_STRING is | |
13919 | recognized, otherwise report an error and return null. | |
13920 | ||
13921 | A similar function exists in GCC. */ | |
e7af610e NC |
13922 | |
13923 | static const struct mips_cpu_info * | |
17a2f251 | 13924 | mips_parse_cpu (const char *option, const char *cpu_string) |
e7af610e | 13925 | { |
316f5878 | 13926 | const struct mips_cpu_info *p; |
e7af610e | 13927 | |
316f5878 RS |
13928 | /* 'from-abi' selects the most compatible architecture for the given |
13929 | ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the | |
13930 | EABIs, we have to decide whether we're using the 32-bit or 64-bit | |
13931 | version. Look first at the -mgp options, if given, otherwise base | |
13932 | the choice on MIPS_DEFAULT_64BIT. | |
e7af610e | 13933 | |
316f5878 RS |
13934 | Treat NO_ABI like the EABIs. One reason to do this is that the |
13935 | plain 'mips' and 'mips64' configs have 'from-abi' as their default | |
13936 | architecture. This code picks MIPS I for 'mips' and MIPS III for | |
13937 | 'mips64', just as we did in the days before 'from-abi'. */ | |
13938 | if (strcasecmp (cpu_string, "from-abi") == 0) | |
13939 | { | |
13940 | if (ABI_NEEDS_32BIT_REGS (mips_abi)) | |
13941 | return mips_cpu_info_from_isa (ISA_MIPS1); | |
13942 | ||
13943 | if (ABI_NEEDS_64BIT_REGS (mips_abi)) | |
13944 | return mips_cpu_info_from_isa (ISA_MIPS3); | |
13945 | ||
13946 | if (file_mips_gp32 >= 0) | |
13947 | return mips_cpu_info_from_isa (file_mips_gp32 ? ISA_MIPS1 : ISA_MIPS3); | |
13948 | ||
13949 | return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT | |
13950 | ? ISA_MIPS3 | |
13951 | : ISA_MIPS1); | |
13952 | } | |
13953 | ||
13954 | /* 'default' has traditionally been a no-op. Probably not very useful. */ | |
13955 | if (strcasecmp (cpu_string, "default") == 0) | |
13956 | return 0; | |
13957 | ||
13958 | for (p = mips_cpu_info_table; p->name != 0; p++) | |
13959 | if (mips_matching_cpu_name_p (p->name, cpu_string)) | |
13960 | return p; | |
13961 | ||
13962 | as_bad ("Bad value (%s) for %s", cpu_string, option); | |
13963 | return 0; | |
e7af610e NC |
13964 | } |
13965 | ||
316f5878 RS |
13966 | /* Return the canonical processor information for ISA (a member of the |
13967 | ISA_MIPS* enumeration). */ | |
13968 | ||
e7af610e | 13969 | static const struct mips_cpu_info * |
17a2f251 | 13970 | mips_cpu_info_from_isa (int isa) |
e7af610e NC |
13971 | { |
13972 | int i; | |
13973 | ||
13974 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
13975 | if (mips_cpu_info_table[i].is_isa | |
316f5878 | 13976 | && isa == mips_cpu_info_table[i].isa) |
e7af610e NC |
13977 | return (&mips_cpu_info_table[i]); |
13978 | ||
e972090a | 13979 | return NULL; |
e7af610e | 13980 | } |
fef14a42 TS |
13981 | |
13982 | static const struct mips_cpu_info * | |
17a2f251 | 13983 | mips_cpu_info_from_arch (int arch) |
fef14a42 TS |
13984 | { |
13985 | int i; | |
13986 | ||
13987 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
13988 | if (arch == mips_cpu_info_table[i].cpu) | |
13989 | return (&mips_cpu_info_table[i]); | |
13990 | ||
13991 | return NULL; | |
13992 | } | |
316f5878 RS |
13993 | \f |
13994 | static void | |
17a2f251 | 13995 | show (FILE *stream, const char *string, int *col_p, int *first_p) |
316f5878 RS |
13996 | { |
13997 | if (*first_p) | |
13998 | { | |
13999 | fprintf (stream, "%24s", ""); | |
14000 | *col_p = 24; | |
14001 | } | |
14002 | else | |
14003 | { | |
14004 | fprintf (stream, ", "); | |
14005 | *col_p += 2; | |
14006 | } | |
e7af610e | 14007 | |
316f5878 RS |
14008 | if (*col_p + strlen (string) > 72) |
14009 | { | |
14010 | fprintf (stream, "\n%24s", ""); | |
14011 | *col_p = 24; | |
14012 | } | |
14013 | ||
14014 | fprintf (stream, "%s", string); | |
14015 | *col_p += strlen (string); | |
14016 | ||
14017 | *first_p = 0; | |
14018 | } | |
14019 | ||
14020 | void | |
17a2f251 | 14021 | md_show_usage (FILE *stream) |
e7af610e | 14022 | { |
316f5878 RS |
14023 | int column, first; |
14024 | size_t i; | |
14025 | ||
14026 | fprintf (stream, _("\ | |
14027 | MIPS options:\n\ | |
316f5878 RS |
14028 | -EB generate big endian output\n\ |
14029 | -EL generate little endian output\n\ | |
14030 | -g, -g2 do not remove unneeded NOPs or swap branches\n\ | |
14031 | -G NUM allow referencing objects up to NUM bytes\n\ | |
14032 | implicitly with the gp register [default 8]\n")); | |
14033 | fprintf (stream, _("\ | |
14034 | -mips1 generate MIPS ISA I instructions\n\ | |
14035 | -mips2 generate MIPS ISA II instructions\n\ | |
14036 | -mips3 generate MIPS ISA III instructions\n\ | |
14037 | -mips4 generate MIPS ISA IV instructions\n\ | |
14038 | -mips5 generate MIPS ISA V instructions\n\ | |
14039 | -mips32 generate MIPS32 ISA instructions\n\ | |
af7ee8bf | 14040 | -mips32r2 generate MIPS32 release 2 ISA instructions\n\ |
316f5878 | 14041 | -mips64 generate MIPS64 ISA instructions\n\ |
5f74bc13 | 14042 | -mips64r2 generate MIPS64 release 2 ISA instructions\n\ |
316f5878 RS |
14043 | -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n")); |
14044 | ||
14045 | first = 1; | |
e7af610e NC |
14046 | |
14047 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
316f5878 RS |
14048 | show (stream, mips_cpu_info_table[i].name, &column, &first); |
14049 | show (stream, "from-abi", &column, &first); | |
14050 | fputc ('\n', stream); | |
e7af610e | 14051 | |
316f5878 RS |
14052 | fprintf (stream, _("\ |
14053 | -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\ | |
14054 | -no-mCPU don't generate code specific to CPU.\n\ | |
14055 | For -mCPU and -no-mCPU, CPU must be one of:\n")); | |
14056 | ||
14057 | first = 1; | |
14058 | ||
14059 | show (stream, "3900", &column, &first); | |
14060 | show (stream, "4010", &column, &first); | |
14061 | show (stream, "4100", &column, &first); | |
14062 | show (stream, "4650", &column, &first); | |
14063 | fputc ('\n', stream); | |
14064 | ||
14065 | fprintf (stream, _("\ | |
14066 | -mips16 generate mips16 instructions\n\ | |
14067 | -no-mips16 do not generate mips16 instructions\n")); | |
14068 | fprintf (stream, _("\ | |
d766e8ec | 14069 | -mfix-vr4120 work around certain VR4120 errata\n\ |
316f5878 RS |
14070 | -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\ |
14071 | -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\ | |
14072 | -O0 remove unneeded NOPs, do not swap branches\n\ | |
14073 | -O remove unneeded NOPs and swap branches\n\ | |
316f5878 RS |
14074 | --[no-]construct-floats [dis]allow floating point values to be constructed\n\ |
14075 | --trap, --no-break trap exception on div by 0 and mult overflow\n\ | |
14076 | --break, --no-trap break exception on div by 0 and mult overflow\n")); | |
14077 | #ifdef OBJ_ELF | |
14078 | fprintf (stream, _("\ | |
14079 | -KPIC, -call_shared generate SVR4 position independent code\n\ | |
14080 | -non_shared do not generate position independent code\n\ | |
14081 | -xgot assume a 32 bit GOT\n\ | |
dcd410fe | 14082 | -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\ |
316f5878 RS |
14083 | -mabi=ABI create ABI conformant object file for:\n")); |
14084 | ||
14085 | first = 1; | |
14086 | ||
14087 | show (stream, "32", &column, &first); | |
14088 | show (stream, "o64", &column, &first); | |
14089 | show (stream, "n32", &column, &first); | |
14090 | show (stream, "64", &column, &first); | |
14091 | show (stream, "eabi", &column, &first); | |
14092 | ||
14093 | fputc ('\n', stream); | |
14094 | ||
14095 | fprintf (stream, _("\ | |
14096 | -32 create o32 ABI object file (default)\n\ | |
14097 | -n32 create n32 ABI object file\n\ | |
14098 | -64 create 64 ABI object file\n")); | |
14099 | #endif | |
e7af610e | 14100 | } |
14e777e0 KB |
14101 | |
14102 | enum dwarf2_format | |
17a2f251 | 14103 | mips_dwarf2_format (void) |
14e777e0 KB |
14104 | { |
14105 | if (mips_abi == N64_ABI) | |
1de5b6a1 AO |
14106 | { |
14107 | #ifdef TE_IRIX | |
14108 | return dwarf2_format_64bit_irix; | |
14109 | #else | |
14110 | return dwarf2_format_64bit; | |
14111 | #endif | |
14112 | } | |
14e777e0 KB |
14113 | else |
14114 | return dwarf2_format_32bit; | |
14115 | } | |
73369e65 EC |
14116 | |
14117 | int | |
14118 | mips_dwarf2_addr_size (void) | |
14119 | { | |
14120 | if (mips_abi == N64_ABI) | |
14121 | return 8; | |
73369e65 EC |
14122 | else |
14123 | return 4; | |
14124 | } |