* lib/gdb.exp (build_executable_from_specs): Remove duplicate set
[deliverable/binutils-gdb.git] / gas / config / tc-mips.c
CommitLineData
252b5132 1/* tc-mips.c -- assemble code for a MIPS chip.
81912461 2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
e407c74b 3 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012, 2013
c67a084a 4 Free Software Foundation, Inc.
252b5132
RH
5 Contributed by the OSF and Ralph Campbell.
6 Written by Keith Knowles and Ralph Campbell, working independently.
7 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
8 Support.
9
10 This file is part of GAS.
11
12 GAS is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
ec2655a6 14 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH
15 any later version.
16
17 GAS is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
21
22 You should have received a copy of the GNU General Public License
23 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC
24 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
25 02110-1301, USA. */
252b5132
RH
26
27#include "as.h"
28#include "config.h"
29#include "subsegs.h"
3882b010 30#include "safe-ctype.h"
252b5132 31
252b5132
RH
32#include "opcode/mips.h"
33#include "itbl-ops.h"
c5dd6aab 34#include "dwarf2dbg.h"
5862107c 35#include "dw2gencfi.h"
252b5132 36
42429eac
RS
37/* Check assumptions made in this file. */
38typedef char static_assert1[sizeof (offsetT) < 8 ? -1 : 1];
39typedef char static_assert2[sizeof (valueT) < 8 ? -1 : 1];
40
252b5132
RH
41#ifdef DEBUG
42#define DBG(x) printf x
43#else
44#define DBG(x)
45#endif
46
9e12b7a2
RS
47#define SKIP_SPACE_TABS(S) \
48 do { while (*(S) == ' ' || *(S) == '\t') ++(S); } while (0)
49
252b5132 50/* Clean up namespace so we can include obj-elf.h too. */
17a2f251
TS
51static int mips_output_flavor (void);
52static int mips_output_flavor (void) { return OUTPUT_FLAVOR; }
252b5132
RH
53#undef OBJ_PROCESS_STAB
54#undef OUTPUT_FLAVOR
55#undef S_GET_ALIGN
56#undef S_GET_SIZE
57#undef S_SET_ALIGN
58#undef S_SET_SIZE
252b5132
RH
59#undef obj_frob_file
60#undef obj_frob_file_after_relocs
61#undef obj_frob_symbol
62#undef obj_pop_insert
63#undef obj_sec_sym_ok_for_reloc
64#undef OBJ_COPY_SYMBOL_ATTRIBUTES
65
66#include "obj-elf.h"
67/* Fix any of them that we actually care about. */
68#undef OUTPUT_FLAVOR
69#define OUTPUT_FLAVOR mips_output_flavor()
252b5132 70
252b5132 71#include "elf/mips.h"
252b5132
RH
72
73#ifndef ECOFF_DEBUGGING
74#define NO_ECOFF_DEBUGGING
75#define ECOFF_DEBUGGING 0
76#endif
77
ecb4347a
DJ
78int mips_flag_mdebug = -1;
79
dcd410fe
RO
80/* Control generation of .pdr sections. Off by default on IRIX: the native
81 linker doesn't know about and discards them, but relocations against them
82 remain, leading to rld crashes. */
83#ifdef TE_IRIX
84int mips_flag_pdr = FALSE;
85#else
86int mips_flag_pdr = TRUE;
87#endif
88
252b5132
RH
89#include "ecoff.h"
90
252b5132 91static char *mips_regmask_frag;
252b5132 92
85b51719 93#define ZERO 0
741fe287 94#define ATREG 1
df58fc94
RS
95#define S0 16
96#define S7 23
252b5132
RH
97#define TREG 24
98#define PIC_CALL_REG 25
99#define KT0 26
100#define KT1 27
101#define GP 28
102#define SP 29
103#define FP 30
104#define RA 31
105
106#define ILLEGAL_REG (32)
107
741fe287
MR
108#define AT mips_opts.at
109
252b5132
RH
110extern int target_big_endian;
111
252b5132 112/* The name of the readonly data section. */
e8044f35 113#define RDATA_SECTION_NAME ".rodata"
252b5132 114
a4e06468
RS
115/* Ways in which an instruction can be "appended" to the output. */
116enum append_method {
117 /* Just add it normally. */
118 APPEND_ADD,
119
120 /* Add it normally and then add a nop. */
121 APPEND_ADD_WITH_NOP,
122
123 /* Turn an instruction with a delay slot into a "compact" version. */
124 APPEND_ADD_COMPACT,
125
126 /* Insert the instruction before the last one. */
127 APPEND_SWAP
128};
129
47e39b9d
RS
130/* Information about an instruction, including its format, operands
131 and fixups. */
132struct mips_cl_insn
133{
134 /* The opcode's entry in mips_opcodes or mips16_opcodes. */
135 const struct mips_opcode *insn_mo;
136
47e39b9d 137 /* The 16-bit or 32-bit bitstring of the instruction itself. This is
5c04167a
RS
138 a copy of INSN_MO->match with the operands filled in. If we have
139 decided to use an extended MIPS16 instruction, this includes the
140 extension. */
47e39b9d
RS
141 unsigned long insn_opcode;
142
143 /* The frag that contains the instruction. */
144 struct frag *frag;
145
146 /* The offset into FRAG of the first instruction byte. */
147 long where;
148
149 /* The relocs associated with the instruction, if any. */
150 fixS *fixp[3];
151
a38419a5
RS
152 /* True if this entry cannot be moved from its current position. */
153 unsigned int fixed_p : 1;
47e39b9d 154
708587a4 155 /* True if this instruction occurred in a .set noreorder block. */
47e39b9d
RS
156 unsigned int noreorder_p : 1;
157
2fa15973
RS
158 /* True for mips16 instructions that jump to an absolute address. */
159 unsigned int mips16_absolute_jump_p : 1;
15be625d
CM
160
161 /* True if this instruction is complete. */
162 unsigned int complete_p : 1;
e407c74b
NC
163
164 /* True if this instruction is cleared from history by unconditional
165 branch. */
166 unsigned int cleared_p : 1;
47e39b9d
RS
167};
168
a325df1d
TS
169/* The ABI to use. */
170enum mips_abi_level
171{
172 NO_ABI = 0,
173 O32_ABI,
174 O64_ABI,
175 N32_ABI,
176 N64_ABI,
177 EABI_ABI
178};
179
180/* MIPS ABI we are using for this output file. */
316f5878 181static enum mips_abi_level mips_abi = NO_ABI;
a325df1d 182
143d77c5
EC
183/* Whether or not we have code that can call pic code. */
184int mips_abicalls = FALSE;
185
aa6975fb
ILT
186/* Whether or not we have code which can be put into a shared
187 library. */
188static bfd_boolean mips_in_shared = TRUE;
189
252b5132
RH
190/* This is the set of options which may be modified by the .set
191 pseudo-op. We use a struct so that .set push and .set pop are more
192 reliable. */
193
e972090a
NC
194struct mips_set_options
195{
252b5132
RH
196 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
197 if it has not been initialized. Changed by `.set mipsN', and the
198 -mipsN command line option, and the default CPU. */
199 int isa;
846ef2d0
RS
200 /* Enabled Application Specific Extensions (ASEs). Changed by `.set
201 <asename>', by command line options, and based on the default
202 architecture. */
203 int ase;
252b5132
RH
204 /* Whether we are assembling for the mips16 processor. 0 if we are
205 not, 1 if we are, and -1 if the value has not been initialized.
206 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
207 -nomips16 command line options, and the default CPU. */
208 int mips16;
df58fc94
RS
209 /* Whether we are assembling for the mipsMIPS ASE. 0 if we are not,
210 1 if we are, and -1 if the value has not been initialized. Changed
211 by `.set micromips' and `.set nomicromips', and the -mmicromips
212 and -mno-micromips command line options, and the default CPU. */
213 int micromips;
252b5132
RH
214 /* Non-zero if we should not reorder instructions. Changed by `.set
215 reorder' and `.set noreorder'. */
216 int noreorder;
741fe287
MR
217 /* Non-zero if we should not permit the register designated "assembler
218 temporary" to be used in instructions. The value is the register
219 number, normally $at ($1). Changed by `.set at=REG', `.set noat'
220 (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */
221 unsigned int at;
252b5132
RH
222 /* Non-zero if we should warn when a macro instruction expands into
223 more than one machine instruction. Changed by `.set nomacro' and
224 `.set macro'. */
225 int warn_about_macros;
226 /* Non-zero if we should not move instructions. Changed by `.set
227 move', `.set volatile', `.set nomove', and `.set novolatile'. */
228 int nomove;
229 /* Non-zero if we should not optimize branches by moving the target
230 of the branch into the delay slot. Actually, we don't perform
231 this optimization anyhow. Changed by `.set bopt' and `.set
232 nobopt'. */
233 int nobopt;
234 /* Non-zero if we should not autoextend mips16 instructions.
235 Changed by `.set autoextend' and `.set noautoextend'. */
236 int noautoextend;
833794fc
MR
237 /* True if we should only emit 32-bit microMIPS instructions.
238 Changed by `.set insn32' and `.set noinsn32', and the -minsn32
239 and -mno-insn32 command line options. */
240 bfd_boolean insn32;
a325df1d
TS
241 /* Restrict general purpose registers and floating point registers
242 to 32 bit. This is initially determined when -mgp32 or -mfp32
243 is passed but can changed if the assembler code uses .set mipsN. */
244 int gp32;
245 int fp32;
fef14a42
TS
246 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
247 command line option, and the default CPU. */
248 int arch;
aed1a261
RS
249 /* True if ".set sym32" is in effect. */
250 bfd_boolean sym32;
037b32b9
AN
251 /* True if floating-point operations are not allowed. Changed by .set
252 softfloat or .set hardfloat, by command line options -msoft-float or
253 -mhard-float. The default is false. */
254 bfd_boolean soft_float;
255
256 /* True if only single-precision floating-point operations are allowed.
257 Changed by .set singlefloat or .set doublefloat, command-line options
258 -msingle-float or -mdouble-float. The default is false. */
259 bfd_boolean single_float;
252b5132
RH
260};
261
037b32b9
AN
262/* This is the struct we use to hold the current set of options. Note
263 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
264 -1 to indicate that they have not been initialized. */
265
a325df1d 266/* True if -mgp32 was passed. */
a8e8e863 267static int file_mips_gp32 = -1;
a325df1d
TS
268
269/* True if -mfp32 was passed. */
a8e8e863 270static int file_mips_fp32 = -1;
a325df1d 271
037b32b9
AN
272/* 1 if -msoft-float, 0 if -mhard-float. The default is 0. */
273static int file_mips_soft_float = 0;
274
275/* 1 if -msingle-float, 0 if -mdouble-float. The default is 0. */
276static int file_mips_single_float = 0;
252b5132 277
ba92f887
MR
278/* True if -mnan=2008, false if -mnan=legacy. */
279static bfd_boolean mips_flag_nan2008 = FALSE;
280
e972090a
NC
281static struct mips_set_options mips_opts =
282{
846ef2d0 283 /* isa */ ISA_UNKNOWN, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1,
b015e599 284 /* noreorder */ 0, /* at */ ATREG, /* warn_about_macros */ 0,
833794fc
MR
285 /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE,
286 /* gp32 */ 0, /* fp32 */ 0, /* arch */ CPU_UNKNOWN, /* sym32 */ FALSE,
b015e599 287 /* soft_float */ FALSE, /* single_float */ FALSE
e7af610e 288};
252b5132 289
846ef2d0
RS
290/* The set of ASEs that were selected on the command line, either
291 explicitly via ASE options or implicitly through things like -march. */
292static unsigned int file_ase;
293
294/* Which bits of file_ase were explicitly set or cleared by ASE options. */
295static unsigned int file_ase_explicit;
296
252b5132
RH
297/* These variables are filled in with the masks of registers used.
298 The object format code reads them and puts them in the appropriate
299 place. */
300unsigned long mips_gprmask;
301unsigned long mips_cprmask[4];
302
303/* MIPS ISA we are using for this output file. */
e7af610e 304static int file_mips_isa = ISA_UNKNOWN;
252b5132 305
738f4d98 306/* True if any MIPS16 code was produced. */
a4672219
TS
307static int file_ase_mips16;
308
3994f87e
TS
309#define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \
310 || mips_opts.isa == ISA_MIPS32R2 \
311 || mips_opts.isa == ISA_MIPS64 \
312 || mips_opts.isa == ISA_MIPS64R2)
313
df58fc94
RS
314/* True if any microMIPS code was produced. */
315static int file_ase_micromips;
316
b12dd2e4
CF
317/* True if we want to create R_MIPS_JALR for jalr $25. */
318#ifdef TE_IRIX
1180b5a4 319#define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI
b12dd2e4 320#else
1180b5a4
RS
321/* As a GNU extension, we use R_MIPS_JALR for o32 too. However,
322 because there's no place for any addend, the only acceptable
323 expression is a bare symbol. */
324#define MIPS_JALR_HINT_P(EXPR) \
325 (!HAVE_IN_PLACE_ADDENDS \
326 || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0))
b12dd2e4
CF
327#endif
328
ec68c924 329/* The argument of the -march= flag. The architecture we are assembling. */
fef14a42 330static int file_mips_arch = CPU_UNKNOWN;
316f5878 331static const char *mips_arch_string;
ec68c924
EC
332
333/* The argument of the -mtune= flag. The architecture for which we
334 are optimizing. */
335static int mips_tune = CPU_UNKNOWN;
316f5878 336static const char *mips_tune_string;
ec68c924 337
316f5878 338/* True when generating 32-bit code for a 64-bit processor. */
252b5132
RH
339static int mips_32bitmode = 0;
340
316f5878
RS
341/* True if the given ABI requires 32-bit registers. */
342#define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
343
344/* Likewise 64-bit registers. */
707bfff6
TS
345#define ABI_NEEDS_64BIT_REGS(ABI) \
346 ((ABI) == N32_ABI \
347 || (ABI) == N64_ABI \
316f5878
RS
348 || (ABI) == O64_ABI)
349
ad3fea08 350/* Return true if ISA supports 64 bit wide gp registers. */
707bfff6
TS
351#define ISA_HAS_64BIT_REGS(ISA) \
352 ((ISA) == ISA_MIPS3 \
353 || (ISA) == ISA_MIPS4 \
354 || (ISA) == ISA_MIPS5 \
355 || (ISA) == ISA_MIPS64 \
356 || (ISA) == ISA_MIPS64R2)
9ce8a5dd 357
ad3fea08
TS
358/* Return true if ISA supports 64 bit wide float registers. */
359#define ISA_HAS_64BIT_FPRS(ISA) \
360 ((ISA) == ISA_MIPS3 \
361 || (ISA) == ISA_MIPS4 \
362 || (ISA) == ISA_MIPS5 \
363 || (ISA) == ISA_MIPS32R2 \
364 || (ISA) == ISA_MIPS64 \
365 || (ISA) == ISA_MIPS64R2)
366
af7ee8bf
CD
367/* Return true if ISA supports 64-bit right rotate (dror et al.)
368 instructions. */
707bfff6 369#define ISA_HAS_DROR(ISA) \
df58fc94
RS
370 ((ISA) == ISA_MIPS64R2 \
371 || (mips_opts.micromips \
372 && ISA_HAS_64BIT_REGS (ISA)) \
373 )
af7ee8bf
CD
374
375/* Return true if ISA supports 32-bit right rotate (ror et al.)
376 instructions. */
707bfff6
TS
377#define ISA_HAS_ROR(ISA) \
378 ((ISA) == ISA_MIPS32R2 \
379 || (ISA) == ISA_MIPS64R2 \
846ef2d0 380 || (mips_opts.ase & ASE_SMARTMIPS) \
df58fc94
RS
381 || mips_opts.micromips \
382 )
707bfff6 383
7455baf8
TS
384/* Return true if ISA supports single-precision floats in odd registers. */
385#define ISA_HAS_ODD_SINGLE_FPR(ISA) \
386 ((ISA) == ISA_MIPS32 \
387 || (ISA) == ISA_MIPS32R2 \
388 || (ISA) == ISA_MIPS64 \
389 || (ISA) == ISA_MIPS64R2)
af7ee8bf 390
ad3fea08
TS
391/* Return true if ISA supports move to/from high part of a 64-bit
392 floating-point register. */
393#define ISA_HAS_MXHC1(ISA) \
394 ((ISA) == ISA_MIPS32R2 \
395 || (ISA) == ISA_MIPS64R2)
396
e013f690 397#define HAVE_32BIT_GPRS \
ad3fea08 398 (mips_opts.gp32 || !ISA_HAS_64BIT_REGS (mips_opts.isa))
ca4e0257 399
e013f690 400#define HAVE_32BIT_FPRS \
ad3fea08 401 (mips_opts.fp32 || !ISA_HAS_64BIT_FPRS (mips_opts.isa))
ca4e0257 402
ad3fea08
TS
403#define HAVE_64BIT_GPRS (!HAVE_32BIT_GPRS)
404#define HAVE_64BIT_FPRS (!HAVE_32BIT_FPRS)
ca4e0257 405
316f5878 406#define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
e013f690 407
316f5878 408#define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
e013f690 409
3b91255e
RS
410/* True if relocations are stored in-place. */
411#define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
412
aed1a261
RS
413/* The ABI-derived address size. */
414#define HAVE_64BIT_ADDRESSES \
415 (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
416#define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
e013f690 417
aed1a261
RS
418/* The size of symbolic constants (i.e., expressions of the form
419 "SYMBOL" or "SYMBOL + OFFSET"). */
420#define HAVE_32BIT_SYMBOLS \
421 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
422#define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
ca4e0257 423
b7c7d6c1
TS
424/* Addresses are loaded in different ways, depending on the address size
425 in use. The n32 ABI Documentation also mandates the use of additions
426 with overflow checking, but existing implementations don't follow it. */
f899b4b8 427#define ADDRESS_ADD_INSN \
b7c7d6c1 428 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
f899b4b8
TS
429
430#define ADDRESS_ADDI_INSN \
b7c7d6c1 431 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
f899b4b8
TS
432
433#define ADDRESS_LOAD_INSN \
434 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
435
436#define ADDRESS_STORE_INSN \
437 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
438
a4672219 439/* Return true if the given CPU supports the MIPS16 ASE. */
3396de36
TS
440#define CPU_HAS_MIPS16(cpu) \
441 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
442 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
a4672219 443
2309ddf2 444/* Return true if the given CPU supports the microMIPS ASE. */
df58fc94
RS
445#define CPU_HAS_MICROMIPS(cpu) 0
446
60b63b72
RS
447/* True if CPU has a dror instruction. */
448#define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
449
450/* True if CPU has a ror instruction. */
451#define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
452
dd6a37e7 453/* True if CPU is in the Octeon family */
432233b3 454#define CPU_IS_OCTEON(CPU) ((CPU) == CPU_OCTEON || (CPU) == CPU_OCTEONP || (CPU) == CPU_OCTEON2)
dd6a37e7 455
dd3cbb7e 456/* True if CPU has seq/sne and seqi/snei instructions. */
dd6a37e7 457#define CPU_HAS_SEQ(CPU) (CPU_IS_OCTEON (CPU))
dd3cbb7e 458
0aa27725
RS
459/* True, if CPU has support for ldc1 and sdc1. */
460#define CPU_HAS_LDC1_SDC1(CPU) \
461 ((mips_opts.isa != ISA_MIPS1) && ((CPU) != CPU_R5900))
462
c8978940
CD
463/* True if mflo and mfhi can be immediately followed by instructions
464 which write to the HI and LO registers.
465
466 According to MIPS specifications, MIPS ISAs I, II, and III need
467 (at least) two instructions between the reads of HI/LO and
468 instructions which write them, and later ISAs do not. Contradicting
469 the MIPS specifications, some MIPS IV processor user manuals (e.g.
470 the UM for the NEC Vr5000) document needing the instructions between
471 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
472 MIPS64 and later ISAs to have the interlocks, plus any specific
473 earlier-ISA CPUs for which CPU documentation declares that the
474 instructions are really interlocked. */
475#define hilo_interlocks \
476 (mips_opts.isa == ISA_MIPS32 \
477 || mips_opts.isa == ISA_MIPS32R2 \
478 || mips_opts.isa == ISA_MIPS64 \
479 || mips_opts.isa == ISA_MIPS64R2 \
480 || mips_opts.arch == CPU_R4010 \
e407c74b 481 || mips_opts.arch == CPU_R5900 \
c8978940
CD
482 || mips_opts.arch == CPU_R10000 \
483 || mips_opts.arch == CPU_R12000 \
3aa3176b
TS
484 || mips_opts.arch == CPU_R14000 \
485 || mips_opts.arch == CPU_R16000 \
c8978940 486 || mips_opts.arch == CPU_RM7000 \
c8978940 487 || mips_opts.arch == CPU_VR5500 \
df58fc94 488 || mips_opts.micromips \
c8978940 489 )
252b5132
RH
490
491/* Whether the processor uses hardware interlocks to protect reads
81912461
ILT
492 from the GPRs after they are loaded from memory, and thus does not
493 require nops to be inserted. This applies to instructions marked
494 INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA
df58fc94
RS
495 level I and microMIPS mode instructions are always interlocked. */
496#define gpr_interlocks \
497 (mips_opts.isa != ISA_MIPS1 \
498 || mips_opts.arch == CPU_R3900 \
e407c74b 499 || mips_opts.arch == CPU_R5900 \
df58fc94
RS
500 || mips_opts.micromips \
501 )
252b5132 502
81912461
ILT
503/* Whether the processor uses hardware interlocks to avoid delays
504 required by coprocessor instructions, and thus does not require
505 nops to be inserted. This applies to instructions marked
506 INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays
507 between instructions marked INSN_WRITE_COND_CODE and ones marked
508 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
df58fc94
RS
509 levels I, II, and III and microMIPS mode instructions are always
510 interlocked. */
bdaaa2e1 511/* Itbl support may require additional care here. */
81912461
ILT
512#define cop_interlocks \
513 ((mips_opts.isa != ISA_MIPS1 \
514 && mips_opts.isa != ISA_MIPS2 \
515 && mips_opts.isa != ISA_MIPS3) \
516 || mips_opts.arch == CPU_R4300 \
df58fc94 517 || mips_opts.micromips \
81912461
ILT
518 )
519
520/* Whether the processor uses hardware interlocks to protect reads
521 from coprocessor registers after they are loaded from memory, and
522 thus does not require nops to be inserted. This applies to
523 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
df58fc94
RS
524 requires at MIPS ISA level I and microMIPS mode instructions are
525 always interlocked. */
526#define cop_mem_interlocks \
527 (mips_opts.isa != ISA_MIPS1 \
528 || mips_opts.micromips \
529 )
252b5132 530
6b76fefe
CM
531/* Is this a mfhi or mflo instruction? */
532#define MF_HILO_INSN(PINFO) \
b19e8a9b
AN
533 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
534
df58fc94
RS
535/* Whether code compression (either of the MIPS16 or the microMIPS ASEs)
536 has been selected. This implies, in particular, that addresses of text
537 labels have their LSB set. */
538#define HAVE_CODE_COMPRESSION \
539 ((mips_opts.mips16 | mips_opts.micromips) != 0)
540
42429eac
RS
541/* The minimum and maximum signed values that can be stored in a GPR. */
542#define GPR_SMAX ((offsetT) (((valueT) 1 << (HAVE_64BIT_GPRS ? 63 : 31)) - 1))
543#define GPR_SMIN (-GPR_SMAX - 1)
544
252b5132
RH
545/* MIPS PIC level. */
546
a161fe53 547enum mips_pic_level mips_pic;
252b5132 548
c9914766 549/* 1 if we should generate 32 bit offsets from the $gp register in
252b5132 550 SVR4_PIC mode. Currently has no meaning in other modes. */
c9914766 551static int mips_big_got = 0;
252b5132
RH
552
553/* 1 if trap instructions should used for overflow rather than break
554 instructions. */
c9914766 555static int mips_trap = 0;
252b5132 556
119d663a 557/* 1 if double width floating point constants should not be constructed
b6ff326e 558 by assembling two single width halves into two single width floating
119d663a
NC
559 point registers which just happen to alias the double width destination
560 register. On some architectures this aliasing can be disabled by a bit
d547a75e 561 in the status register, and the setting of this bit cannot be determined
119d663a
NC
562 automatically at assemble time. */
563static int mips_disable_float_construction;
564
252b5132
RH
565/* Non-zero if any .set noreorder directives were used. */
566
567static int mips_any_noreorder;
568
6b76fefe
CM
569/* Non-zero if nops should be inserted when the register referenced in
570 an mfhi/mflo instruction is read in the next two instructions. */
571static int mips_7000_hilo_fix;
572
02ffd3e4 573/* The size of objects in the small data section. */
156c2f8b 574static unsigned int g_switch_value = 8;
252b5132
RH
575/* Whether the -G option was used. */
576static int g_switch_seen = 0;
577
578#define N_RMASK 0xc4
579#define N_VFP 0xd4
580
581/* If we can determine in advance that GP optimization won't be
582 possible, we can skip the relaxation stuff that tries to produce
583 GP-relative references. This makes delay slot optimization work
584 better.
585
586 This function can only provide a guess, but it seems to work for
fba2b7f9
GK
587 gcc output. It needs to guess right for gcc, otherwise gcc
588 will put what it thinks is a GP-relative instruction in a branch
589 delay slot.
252b5132
RH
590
591 I don't know if a fix is needed for the SVR4_PIC mode. I've only
592 fixed it for the non-PIC mode. KR 95/04/07 */
17a2f251 593static int nopic_need_relax (symbolS *, int);
252b5132
RH
594
595/* handle of the OPCODE hash table */
596static struct hash_control *op_hash = NULL;
597
598/* The opcode hash table we use for the mips16. */
599static struct hash_control *mips16_op_hash = NULL;
600
df58fc94
RS
601/* The opcode hash table we use for the microMIPS ASE. */
602static struct hash_control *micromips_op_hash = NULL;
603
252b5132
RH
604/* This array holds the chars that always start a comment. If the
605 pre-processor is disabled, these aren't very useful */
606const char comment_chars[] = "#";
607
608/* This array holds the chars that only start a comment at the beginning of
609 a line. If the line seems to have the form '# 123 filename'
610 .line and .file directives will appear in the pre-processed output */
611/* Note that input_file.c hand checks for '#' at the beginning of the
612 first line of the input file. This is because the compiler outputs
bdaaa2e1 613 #NO_APP at the beginning of its output. */
252b5132
RH
614/* Also note that C style comments are always supported. */
615const char line_comment_chars[] = "#";
616
bdaaa2e1 617/* This array holds machine specific line separator characters. */
63a0b638 618const char line_separator_chars[] = ";";
252b5132
RH
619
620/* Chars that can be used to separate mant from exp in floating point nums */
621const char EXP_CHARS[] = "eE";
622
623/* Chars that mean this number is a floating point constant */
624/* As in 0f12.456 */
625/* or 0d1.2345e12 */
626const char FLT_CHARS[] = "rRsSfFdDxXpP";
627
628/* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
629 changed in read.c . Ideally it shouldn't have to know about it at all,
630 but nothing is ideal around here.
631 */
632
e3de51ce
RS
633/* Types of printf format used for instruction-related error messages.
634 "I" means int ("%d") and "S" means string ("%s"). */
635enum mips_insn_error_format {
636 ERR_FMT_PLAIN,
637 ERR_FMT_I,
638 ERR_FMT_SS,
639};
640
641/* Information about an error that was found while assembling the current
642 instruction. */
643struct mips_insn_error {
644 /* We sometimes need to match an instruction against more than one
645 opcode table entry. Errors found during this matching are reported
646 against a particular syntactic argument rather than against the
647 instruction as a whole. We grade these messages so that errors
648 against argument N have a greater priority than an error against
649 any argument < N, since the former implies that arguments up to N
650 were acceptable and that the opcode entry was therefore a closer match.
651 If several matches report an error against the same argument,
652 we only use that error if it is the same in all cases.
653
654 min_argnum is the minimum argument number for which an error message
655 should be accepted. It is 0 if MSG is against the instruction as
656 a whole. */
657 int min_argnum;
658
659 /* The printf()-style message, including its format and arguments. */
660 enum mips_insn_error_format format;
661 const char *msg;
662 union {
663 int i;
664 const char *ss[2];
665 } u;
666};
667
668/* The error that should be reported for the current instruction. */
669static struct mips_insn_error insn_error;
252b5132
RH
670
671static int auto_align = 1;
672
673/* When outputting SVR4 PIC code, the assembler needs to know the
674 offset in the stack frame from which to restore the $gp register.
675 This is set by the .cprestore pseudo-op, and saved in this
676 variable. */
677static offsetT mips_cprestore_offset = -1;
678
67c1ffbe 679/* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
6478892d 680 more optimizations, it can use a register value instead of a memory-saved
956cd1d6 681 offset and even an other register than $gp as global pointer. */
6478892d
TS
682static offsetT mips_cpreturn_offset = -1;
683static int mips_cpreturn_register = -1;
684static int mips_gp_register = GP;
def2e0dd 685static int mips_gprel_offset = 0;
6478892d 686
7a621144
DJ
687/* Whether mips_cprestore_offset has been set in the current function
688 (or whether it has already been warned about, if not). */
689static int mips_cprestore_valid = 0;
690
252b5132
RH
691/* This is the register which holds the stack frame, as set by the
692 .frame pseudo-op. This is needed to implement .cprestore. */
693static int mips_frame_reg = SP;
694
7a621144
DJ
695/* Whether mips_frame_reg has been set in the current function
696 (or whether it has already been warned about, if not). */
697static int mips_frame_reg_valid = 0;
698
252b5132
RH
699/* To output NOP instructions correctly, we need to keep information
700 about the previous two instructions. */
701
702/* Whether we are optimizing. The default value of 2 means to remove
703 unneeded NOPs and swap branch instructions when possible. A value
704 of 1 means to not swap branches. A value of 0 means to always
705 insert NOPs. */
706static int mips_optimize = 2;
707
708/* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
709 equivalent to seeing no -g option at all. */
710static int mips_debug = 0;
711
7d8e00cf
RS
712/* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */
713#define MAX_VR4130_NOPS 4
714
715/* The maximum number of NOPs needed to fill delay slots. */
716#define MAX_DELAY_NOPS 2
717
718/* The maximum number of NOPs needed for any purpose. */
719#define MAX_NOPS 4
71400594
RS
720
721/* A list of previous instructions, with index 0 being the most recent.
722 We need to look back MAX_NOPS instructions when filling delay slots
723 or working around processor errata. We need to look back one
724 instruction further if we're thinking about using history[0] to
725 fill a branch delay slot. */
726static struct mips_cl_insn history[1 + MAX_NOPS];
252b5132 727
fc76e730 728/* Arrays of operands for each instruction. */
14daeee3 729#define MAX_OPERANDS 6
fc76e730
RS
730struct mips_operand_array {
731 const struct mips_operand *operand[MAX_OPERANDS];
732};
733static struct mips_operand_array *mips_operands;
734static struct mips_operand_array *mips16_operands;
735static struct mips_operand_array *micromips_operands;
736
1e915849 737/* Nop instructions used by emit_nop. */
df58fc94
RS
738static struct mips_cl_insn nop_insn;
739static struct mips_cl_insn mips16_nop_insn;
740static struct mips_cl_insn micromips_nop16_insn;
741static struct mips_cl_insn micromips_nop32_insn;
1e915849
RS
742
743/* The appropriate nop for the current mode. */
833794fc
MR
744#define NOP_INSN (mips_opts.mips16 \
745 ? &mips16_nop_insn \
746 : (mips_opts.micromips \
747 ? (mips_opts.insn32 \
748 ? &micromips_nop32_insn \
749 : &micromips_nop16_insn) \
750 : &nop_insn))
df58fc94
RS
751
752/* The size of NOP_INSN in bytes. */
833794fc
MR
753#define NOP_INSN_SIZE ((mips_opts.mips16 \
754 || (mips_opts.micromips && !mips_opts.insn32)) \
755 ? 2 : 4)
252b5132 756
252b5132
RH
757/* If this is set, it points to a frag holding nop instructions which
758 were inserted before the start of a noreorder section. If those
759 nops turn out to be unnecessary, the size of the frag can be
760 decreased. */
761static fragS *prev_nop_frag;
762
763/* The number of nop instructions we created in prev_nop_frag. */
764static int prev_nop_frag_holds;
765
766/* The number of nop instructions that we know we need in
bdaaa2e1 767 prev_nop_frag. */
252b5132
RH
768static int prev_nop_frag_required;
769
770/* The number of instructions we've seen since prev_nop_frag. */
771static int prev_nop_frag_since;
772
e8044f35
RS
773/* Relocations against symbols are sometimes done in two parts, with a HI
774 relocation and a LO relocation. Each relocation has only 16 bits of
775 space to store an addend. This means that in order for the linker to
776 handle carries correctly, it must be able to locate both the HI and
777 the LO relocation. This means that the relocations must appear in
778 order in the relocation table.
252b5132
RH
779
780 In order to implement this, we keep track of each unmatched HI
781 relocation. We then sort them so that they immediately precede the
bdaaa2e1 782 corresponding LO relocation. */
252b5132 783
e972090a
NC
784struct mips_hi_fixup
785{
252b5132
RH
786 /* Next HI fixup. */
787 struct mips_hi_fixup *next;
788 /* This fixup. */
789 fixS *fixp;
790 /* The section this fixup is in. */
791 segT seg;
792};
793
794/* The list of unmatched HI relocs. */
795
796static struct mips_hi_fixup *mips_hi_fixup_list;
797
64bdfcaf
RS
798/* The frag containing the last explicit relocation operator.
799 Null if explicit relocations have not been used. */
800
801static fragS *prev_reloc_op_frag;
802
252b5132
RH
803/* Map mips16 register numbers to normal MIPS register numbers. */
804
e972090a
NC
805static const unsigned int mips16_to_32_reg_map[] =
806{
252b5132
RH
807 16, 17, 2, 3, 4, 5, 6, 7
808};
60b63b72 809
df58fc94
RS
810/* Map microMIPS register numbers to normal MIPS register numbers. */
811
df58fc94 812#define micromips_to_32_reg_d_map mips16_to_32_reg_map
df58fc94
RS
813
814/* The microMIPS registers with type h. */
e76ff5ab 815static const unsigned int micromips_to_32_reg_h_map1[] =
df58fc94
RS
816{
817 5, 5, 6, 4, 4, 4, 4, 4
818};
e76ff5ab 819static const unsigned int micromips_to_32_reg_h_map2[] =
df58fc94
RS
820{
821 6, 7, 7, 21, 22, 5, 6, 7
822};
823
df58fc94
RS
824/* The microMIPS registers with type m. */
825static const unsigned int micromips_to_32_reg_m_map[] =
826{
827 0, 17, 2, 3, 16, 18, 19, 20
828};
829
830#define micromips_to_32_reg_n_map micromips_to_32_reg_m_map
831
71400594
RS
832/* Classifies the kind of instructions we're interested in when
833 implementing -mfix-vr4120. */
c67a084a
NC
834enum fix_vr4120_class
835{
71400594
RS
836 FIX_VR4120_MACC,
837 FIX_VR4120_DMACC,
838 FIX_VR4120_MULT,
839 FIX_VR4120_DMULT,
840 FIX_VR4120_DIV,
841 FIX_VR4120_MTHILO,
842 NUM_FIX_VR4120_CLASSES
843};
844
c67a084a
NC
845/* ...likewise -mfix-loongson2f-jump. */
846static bfd_boolean mips_fix_loongson2f_jump;
847
848/* ...likewise -mfix-loongson2f-nop. */
849static bfd_boolean mips_fix_loongson2f_nop;
850
851/* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */
852static bfd_boolean mips_fix_loongson2f;
853
71400594
RS
854/* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if
855 there must be at least one other instruction between an instruction
856 of type X and an instruction of type Y. */
857static unsigned int vr4120_conflicts[NUM_FIX_VR4120_CLASSES];
858
859/* True if -mfix-vr4120 is in force. */
d766e8ec 860static int mips_fix_vr4120;
4a6a3df4 861
7d8e00cf
RS
862/* ...likewise -mfix-vr4130. */
863static int mips_fix_vr4130;
864
6a32d874
CM
865/* ...likewise -mfix-24k. */
866static int mips_fix_24k;
867
d954098f
DD
868/* ...likewise -mfix-cn63xxp1 */
869static bfd_boolean mips_fix_cn63xxp1;
870
4a6a3df4
AO
871/* We don't relax branches by default, since this causes us to expand
872 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
873 fail to compute the offset before expanding the macro to the most
874 efficient expansion. */
875
876static int mips_relax_branch;
252b5132 877\f
4d7206a2
RS
878/* The expansion of many macros depends on the type of symbol that
879 they refer to. For example, when generating position-dependent code,
880 a macro that refers to a symbol may have two different expansions,
881 one which uses GP-relative addresses and one which uses absolute
882 addresses. When generating SVR4-style PIC, a macro may have
883 different expansions for local and global symbols.
884
885 We handle these situations by generating both sequences and putting
886 them in variant frags. In position-dependent code, the first sequence
887 will be the GP-relative one and the second sequence will be the
888 absolute one. In SVR4 PIC, the first sequence will be for global
889 symbols and the second will be for local symbols.
890
584892a6
RS
891 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
892 SECOND are the lengths of the two sequences in bytes. These fields
893 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
894 the subtype has the following flags:
4d7206a2 895
584892a6
RS
896 RELAX_USE_SECOND
897 Set if it has been decided that we should use the second
898 sequence instead of the first.
899
900 RELAX_SECOND_LONGER
901 Set in the first variant frag if the macro's second implementation
902 is longer than its first. This refers to the macro as a whole,
903 not an individual relaxation.
904
905 RELAX_NOMACRO
906 Set in the first variant frag if the macro appeared in a .set nomacro
907 block and if one alternative requires a warning but the other does not.
908
909 RELAX_DELAY_SLOT
910 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
911 delay slot.
4d7206a2 912
df58fc94
RS
913 RELAX_DELAY_SLOT_16BIT
914 Like RELAX_DELAY_SLOT, but indicates that the delay slot requires a
915 16-bit instruction.
916
917 RELAX_DELAY_SLOT_SIZE_FIRST
918 Like RELAX_DELAY_SLOT, but indicates that the first implementation of
919 the macro is of the wrong size for the branch delay slot.
920
921 RELAX_DELAY_SLOT_SIZE_SECOND
922 Like RELAX_DELAY_SLOT, but indicates that the second implementation of
923 the macro is of the wrong size for the branch delay slot.
924
4d7206a2
RS
925 The frag's "opcode" points to the first fixup for relaxable code.
926
927 Relaxable macros are generated using a sequence such as:
928
929 relax_start (SYMBOL);
930 ... generate first expansion ...
931 relax_switch ();
932 ... generate second expansion ...
933 relax_end ();
934
935 The code and fixups for the unwanted alternative are discarded
936 by md_convert_frag. */
584892a6 937#define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND))
4d7206a2 938
584892a6
RS
939#define RELAX_FIRST(X) (((X) >> 8) & 0xff)
940#define RELAX_SECOND(X) ((X) & 0xff)
941#define RELAX_USE_SECOND 0x10000
942#define RELAX_SECOND_LONGER 0x20000
943#define RELAX_NOMACRO 0x40000
944#define RELAX_DELAY_SLOT 0x80000
df58fc94
RS
945#define RELAX_DELAY_SLOT_16BIT 0x100000
946#define RELAX_DELAY_SLOT_SIZE_FIRST 0x200000
947#define RELAX_DELAY_SLOT_SIZE_SECOND 0x400000
252b5132 948
4a6a3df4
AO
949/* Branch without likely bit. If label is out of range, we turn:
950
951 beq reg1, reg2, label
952 delay slot
953
954 into
955
956 bne reg1, reg2, 0f
957 nop
958 j label
959 0: delay slot
960
961 with the following opcode replacements:
962
963 beq <-> bne
964 blez <-> bgtz
965 bltz <-> bgez
966 bc1f <-> bc1t
967
968 bltzal <-> bgezal (with jal label instead of j label)
969
970 Even though keeping the delay slot instruction in the delay slot of
971 the branch would be more efficient, it would be very tricky to do
972 correctly, because we'd have to introduce a variable frag *after*
973 the delay slot instruction, and expand that instead. Let's do it
974 the easy way for now, even if the branch-not-taken case now costs
975 one additional instruction. Out-of-range branches are not supposed
976 to be common, anyway.
977
978 Branch likely. If label is out of range, we turn:
979
980 beql reg1, reg2, label
981 delay slot (annulled if branch not taken)
982
983 into
984
985 beql reg1, reg2, 1f
986 nop
987 beql $0, $0, 2f
988 nop
989 1: j[al] label
990 delay slot (executed only if branch taken)
991 2:
992
993 It would be possible to generate a shorter sequence by losing the
994 likely bit, generating something like:
b34976b6 995
4a6a3df4
AO
996 bne reg1, reg2, 0f
997 nop
998 j[al] label
999 delay slot (executed only if branch taken)
1000 0:
1001
1002 beql -> bne
1003 bnel -> beq
1004 blezl -> bgtz
1005 bgtzl -> blez
1006 bltzl -> bgez
1007 bgezl -> bltz
1008 bc1fl -> bc1t
1009 bc1tl -> bc1f
1010
1011 bltzall -> bgezal (with jal label instead of j label)
1012 bgezall -> bltzal (ditto)
1013
1014
1015 but it's not clear that it would actually improve performance. */
66b3e8da
MR
1016#define RELAX_BRANCH_ENCODE(at, uncond, likely, link, toofar) \
1017 ((relax_substateT) \
1018 (0xc0000000 \
1019 | ((at) & 0x1f) \
1020 | ((toofar) ? 0x20 : 0) \
1021 | ((link) ? 0x40 : 0) \
1022 | ((likely) ? 0x80 : 0) \
1023 | ((uncond) ? 0x100 : 0)))
4a6a3df4 1024#define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
66b3e8da
MR
1025#define RELAX_BRANCH_UNCOND(i) (((i) & 0x100) != 0)
1026#define RELAX_BRANCH_LIKELY(i) (((i) & 0x80) != 0)
1027#define RELAX_BRANCH_LINK(i) (((i) & 0x40) != 0)
1028#define RELAX_BRANCH_TOOFAR(i) (((i) & 0x20) != 0)
1029#define RELAX_BRANCH_AT(i) ((i) & 0x1f)
4a6a3df4 1030
252b5132
RH
1031/* For mips16 code, we use an entirely different form of relaxation.
1032 mips16 supports two versions of most instructions which take
1033 immediate values: a small one which takes some small value, and a
1034 larger one which takes a 16 bit value. Since branches also follow
1035 this pattern, relaxing these values is required.
1036
1037 We can assemble both mips16 and normal MIPS code in a single
1038 object. Therefore, we need to support this type of relaxation at
1039 the same time that we support the relaxation described above. We
1040 use the high bit of the subtype field to distinguish these cases.
1041
1042 The information we store for this type of relaxation is the
1043 argument code found in the opcode file for this relocation, whether
1044 the user explicitly requested a small or extended form, and whether
1045 the relocation is in a jump or jal delay slot. That tells us the
1046 size of the value, and how it should be stored. We also store
1047 whether the fragment is considered to be extended or not. We also
1048 store whether this is known to be a branch to a different section,
1049 whether we have tried to relax this frag yet, and whether we have
1050 ever extended a PC relative fragment because of a shift count. */
1051#define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
1052 (0x80000000 \
1053 | ((type) & 0xff) \
1054 | ((small) ? 0x100 : 0) \
1055 | ((ext) ? 0x200 : 0) \
1056 | ((dslot) ? 0x400 : 0) \
1057 | ((jal_dslot) ? 0x800 : 0))
4a6a3df4 1058#define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
252b5132
RH
1059#define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
1060#define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
1061#define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
1062#define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
1063#define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
1064#define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
1065#define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
1066#define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
1067#define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
1068#define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
1069#define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
885add95 1070
df58fc94
RS
1071/* For microMIPS code, we use relaxation similar to one we use for
1072 MIPS16 code. Some instructions that take immediate values support
1073 two encodings: a small one which takes some small value, and a
1074 larger one which takes a 16 bit value. As some branches also follow
1075 this pattern, relaxing these values is required.
1076
1077 We can assemble both microMIPS and normal MIPS code in a single
1078 object. Therefore, we need to support this type of relaxation at
1079 the same time that we support the relaxation described above. We
1080 use one of the high bits of the subtype field to distinguish these
1081 cases.
1082
1083 The information we store for this type of relaxation is the argument
1084 code found in the opcode file for this relocation, the register
40209cad
MR
1085 selected as the assembler temporary, whether the branch is
1086 unconditional, whether it is compact, whether it stores the link
1087 address implicitly in $ra, whether relaxation of out-of-range 32-bit
1088 branches to a sequence of instructions is enabled, and whether the
1089 displacement of a branch is too large to fit as an immediate argument
1090 of a 16-bit and a 32-bit branch, respectively. */
1091#define RELAX_MICROMIPS_ENCODE(type, at, uncond, compact, link, \
1092 relax32, toofar16, toofar32) \
1093 (0x40000000 \
1094 | ((type) & 0xff) \
1095 | (((at) & 0x1f) << 8) \
1096 | ((uncond) ? 0x2000 : 0) \
1097 | ((compact) ? 0x4000 : 0) \
1098 | ((link) ? 0x8000 : 0) \
1099 | ((relax32) ? 0x10000 : 0) \
1100 | ((toofar16) ? 0x20000 : 0) \
1101 | ((toofar32) ? 0x40000 : 0))
df58fc94
RS
1102#define RELAX_MICROMIPS_P(i) (((i) & 0xc0000000) == 0x40000000)
1103#define RELAX_MICROMIPS_TYPE(i) ((i) & 0xff)
1104#define RELAX_MICROMIPS_AT(i) (((i) >> 8) & 0x1f)
40209cad
MR
1105#define RELAX_MICROMIPS_UNCOND(i) (((i) & 0x2000) != 0)
1106#define RELAX_MICROMIPS_COMPACT(i) (((i) & 0x4000) != 0)
1107#define RELAX_MICROMIPS_LINK(i) (((i) & 0x8000) != 0)
1108#define RELAX_MICROMIPS_RELAX32(i) (((i) & 0x10000) != 0)
1109
1110#define RELAX_MICROMIPS_TOOFAR16(i) (((i) & 0x20000) != 0)
1111#define RELAX_MICROMIPS_MARK_TOOFAR16(i) ((i) | 0x20000)
1112#define RELAX_MICROMIPS_CLEAR_TOOFAR16(i) ((i) & ~0x20000)
1113#define RELAX_MICROMIPS_TOOFAR32(i) (((i) & 0x40000) != 0)
1114#define RELAX_MICROMIPS_MARK_TOOFAR32(i) ((i) | 0x40000)
1115#define RELAX_MICROMIPS_CLEAR_TOOFAR32(i) ((i) & ~0x40000)
df58fc94 1116
43c0598f
RS
1117/* Sign-extend 16-bit value X. */
1118#define SEXT_16BIT(X) ((((X) + 0x8000) & 0xffff) - 0x8000)
1119
885add95
CD
1120/* Is the given value a sign-extended 32-bit value? */
1121#define IS_SEXT_32BIT_NUM(x) \
1122 (((x) &~ (offsetT) 0x7fffffff) == 0 \
1123 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
1124
1125/* Is the given value a sign-extended 16-bit value? */
1126#define IS_SEXT_16BIT_NUM(x) \
1127 (((x) &~ (offsetT) 0x7fff) == 0 \
1128 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
1129
df58fc94
RS
1130/* Is the given value a sign-extended 12-bit value? */
1131#define IS_SEXT_12BIT_NUM(x) \
1132 (((((x) & 0xfff) ^ 0x800LL) - 0x800LL) == (x))
1133
7f3c4072
CM
1134/* Is the given value a sign-extended 9-bit value? */
1135#define IS_SEXT_9BIT_NUM(x) \
1136 (((((x) & 0x1ff) ^ 0x100LL) - 0x100LL) == (x))
1137
2051e8c4
MR
1138/* Is the given value a zero-extended 32-bit value? Or a negated one? */
1139#define IS_ZEXT_32BIT_NUM(x) \
1140 (((x) &~ (offsetT) 0xffffffff) == 0 \
1141 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
1142
bf12938e
RS
1143/* Extract bits MASK << SHIFT from STRUCT and shift them right
1144 SHIFT places. */
1145#define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
1146 (((STRUCT) >> (SHIFT)) & (MASK))
1147
bf12938e 1148/* Extract the operand given by FIELD from mips_cl_insn INSN. */
df58fc94
RS
1149#define EXTRACT_OPERAND(MICROMIPS, FIELD, INSN) \
1150 (!(MICROMIPS) \
1151 ? EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) \
1152 : EXTRACT_BITS ((INSN).insn_opcode, \
1153 MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD))
bf12938e
RS
1154#define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \
1155 EXTRACT_BITS ((INSN).insn_opcode, \
1156 MIPS16OP_MASK_##FIELD, \
1157 MIPS16OP_SH_##FIELD)
5c04167a
RS
1158
1159/* The MIPS16 EXTEND opcode, shifted left 16 places. */
1160#define MIPS16_EXTEND (0xf000U << 16)
4d7206a2 1161\f
df58fc94
RS
1162/* Whether or not we are emitting a branch-likely macro. */
1163static bfd_boolean emit_branch_likely_macro = FALSE;
1164
4d7206a2
RS
1165/* Global variables used when generating relaxable macros. See the
1166 comment above RELAX_ENCODE for more details about how relaxation
1167 is used. */
1168static struct {
1169 /* 0 if we're not emitting a relaxable macro.
1170 1 if we're emitting the first of the two relaxation alternatives.
1171 2 if we're emitting the second alternative. */
1172 int sequence;
1173
1174 /* The first relaxable fixup in the current frag. (In other words,
1175 the first fixup that refers to relaxable code.) */
1176 fixS *first_fixup;
1177
1178 /* sizes[0] says how many bytes of the first alternative are stored in
1179 the current frag. Likewise sizes[1] for the second alternative. */
1180 unsigned int sizes[2];
1181
1182 /* The symbol on which the choice of sequence depends. */
1183 symbolS *symbol;
1184} mips_relax;
252b5132 1185\f
584892a6
RS
1186/* Global variables used to decide whether a macro needs a warning. */
1187static struct {
1188 /* True if the macro is in a branch delay slot. */
1189 bfd_boolean delay_slot_p;
1190
df58fc94
RS
1191 /* Set to the length in bytes required if the macro is in a delay slot
1192 that requires a specific length of instruction, otherwise zero. */
1193 unsigned int delay_slot_length;
1194
584892a6
RS
1195 /* For relaxable macros, sizes[0] is the length of the first alternative
1196 in bytes and sizes[1] is the length of the second alternative.
1197 For non-relaxable macros, both elements give the length of the
1198 macro in bytes. */
1199 unsigned int sizes[2];
1200
df58fc94
RS
1201 /* For relaxable macros, first_insn_sizes[0] is the length of the first
1202 instruction of the first alternative in bytes and first_insn_sizes[1]
1203 is the length of the first instruction of the second alternative.
1204 For non-relaxable macros, both elements give the length of the first
1205 instruction in bytes.
1206
1207 Set to zero if we haven't yet seen the first instruction. */
1208 unsigned int first_insn_sizes[2];
1209
1210 /* For relaxable macros, insns[0] is the number of instructions for the
1211 first alternative and insns[1] is the number of instructions for the
1212 second alternative.
1213
1214 For non-relaxable macros, both elements give the number of
1215 instructions for the macro. */
1216 unsigned int insns[2];
1217
584892a6
RS
1218 /* The first variant frag for this macro. */
1219 fragS *first_frag;
1220} mips_macro_warning;
1221\f
252b5132
RH
1222/* Prototypes for static functions. */
1223
252b5132
RH
1224enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG };
1225
b34976b6 1226static void append_insn
df58fc94
RS
1227 (struct mips_cl_insn *, expressionS *, bfd_reloc_code_real_type *,
1228 bfd_boolean expansionp);
7d10b47d 1229static void mips_no_prev_insn (void);
c67a084a 1230static void macro_build (expressionS *, const char *, const char *, ...);
b34976b6 1231static void mips16_macro_build
03ea81db 1232 (expressionS *, const char *, const char *, va_list *);
67c0d1eb 1233static void load_register (int, expressionS *, int);
584892a6
RS
1234static void macro_start (void);
1235static void macro_end (void);
833794fc 1236static void macro (struct mips_cl_insn *ip, char *str);
17a2f251 1237static void mips16_macro (struct mips_cl_insn * ip);
17a2f251
TS
1238static void mips_ip (char *str, struct mips_cl_insn * ip);
1239static void mips16_ip (char *str, struct mips_cl_insn * ip);
b34976b6 1240static void mips16_immed
43c0598f
RS
1241 (char *, unsigned int, int, bfd_reloc_code_real_type, offsetT,
1242 unsigned int, unsigned long *);
5e0116d5 1243static size_t my_getSmallExpression
17a2f251
TS
1244 (expressionS *, bfd_reloc_code_real_type *, char *);
1245static void my_getExpression (expressionS *, char *);
1246static void s_align (int);
1247static void s_change_sec (int);
1248static void s_change_section (int);
1249static void s_cons (int);
1250static void s_float_cons (int);
1251static void s_mips_globl (int);
1252static void s_option (int);
1253static void s_mipsset (int);
1254static void s_abicalls (int);
1255static void s_cpload (int);
1256static void s_cpsetup (int);
1257static void s_cplocal (int);
1258static void s_cprestore (int);
1259static void s_cpreturn (int);
741d6ea8
JM
1260static void s_dtprelword (int);
1261static void s_dtpreldword (int);
d0f13682
CLT
1262static void s_tprelword (int);
1263static void s_tpreldword (int);
17a2f251
TS
1264static void s_gpvalue (int);
1265static void s_gpword (int);
1266static void s_gpdword (int);
a3f278e2 1267static void s_ehword (int);
17a2f251
TS
1268static void s_cpadd (int);
1269static void s_insn (int);
ba92f887 1270static void s_nan (int);
17a2f251
TS
1271static void md_obj_begin (void);
1272static void md_obj_end (void);
1273static void s_mips_ent (int);
1274static void s_mips_end (int);
1275static void s_mips_frame (int);
1276static void s_mips_mask (int reg_type);
1277static void s_mips_stab (int);
1278static void s_mips_weakext (int);
1279static void s_mips_file (int);
1280static void s_mips_loc (int);
1281static bfd_boolean pic_need_relax (symbolS *, asection *);
4a6a3df4 1282static int relaxed_branch_length (fragS *, asection *, int);
df58fc94
RS
1283static int relaxed_micromips_16bit_branch_length (fragS *, asection *, int);
1284static int relaxed_micromips_32bit_branch_length (fragS *, asection *, int);
e7af610e
NC
1285
1286/* Table and functions used to map between CPU/ISA names, and
1287 ISA levels, and CPU numbers. */
1288
e972090a
NC
1289struct mips_cpu_info
1290{
e7af610e 1291 const char *name; /* CPU or ISA name. */
d16afab6
RS
1292 int flags; /* MIPS_CPU_* flags. */
1293 int ase; /* Set of ASEs implemented by the CPU. */
e7af610e
NC
1294 int isa; /* ISA level. */
1295 int cpu; /* CPU number (default CPU if ISA). */
1296};
1297
ad3fea08 1298#define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */
ad3fea08 1299
17a2f251
TS
1300static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *);
1301static const struct mips_cpu_info *mips_cpu_info_from_isa (int);
1302static const struct mips_cpu_info *mips_cpu_info_from_arch (int);
252b5132 1303\f
c31f3936
RS
1304/* Command-line options. */
1305const char *md_shortopts = "O::g::G:";
1306
1307enum options
1308 {
1309 OPTION_MARCH = OPTION_MD_BASE,
1310 OPTION_MTUNE,
1311 OPTION_MIPS1,
1312 OPTION_MIPS2,
1313 OPTION_MIPS3,
1314 OPTION_MIPS4,
1315 OPTION_MIPS5,
1316 OPTION_MIPS32,
1317 OPTION_MIPS64,
1318 OPTION_MIPS32R2,
1319 OPTION_MIPS64R2,
1320 OPTION_MIPS16,
1321 OPTION_NO_MIPS16,
1322 OPTION_MIPS3D,
1323 OPTION_NO_MIPS3D,
1324 OPTION_MDMX,
1325 OPTION_NO_MDMX,
1326 OPTION_DSP,
1327 OPTION_NO_DSP,
1328 OPTION_MT,
1329 OPTION_NO_MT,
1330 OPTION_VIRT,
1331 OPTION_NO_VIRT,
56d438b1
CF
1332 OPTION_MSA,
1333 OPTION_NO_MSA,
c31f3936
RS
1334 OPTION_SMARTMIPS,
1335 OPTION_NO_SMARTMIPS,
1336 OPTION_DSPR2,
1337 OPTION_NO_DSPR2,
1338 OPTION_EVA,
1339 OPTION_NO_EVA,
1340 OPTION_MICROMIPS,
1341 OPTION_NO_MICROMIPS,
1342 OPTION_MCU,
1343 OPTION_NO_MCU,
1344 OPTION_COMPAT_ARCH_BASE,
1345 OPTION_M4650,
1346 OPTION_NO_M4650,
1347 OPTION_M4010,
1348 OPTION_NO_M4010,
1349 OPTION_M4100,
1350 OPTION_NO_M4100,
1351 OPTION_M3900,
1352 OPTION_NO_M3900,
1353 OPTION_M7000_HILO_FIX,
1354 OPTION_MNO_7000_HILO_FIX,
1355 OPTION_FIX_24K,
1356 OPTION_NO_FIX_24K,
1357 OPTION_FIX_LOONGSON2F_JUMP,
1358 OPTION_NO_FIX_LOONGSON2F_JUMP,
1359 OPTION_FIX_LOONGSON2F_NOP,
1360 OPTION_NO_FIX_LOONGSON2F_NOP,
1361 OPTION_FIX_VR4120,
1362 OPTION_NO_FIX_VR4120,
1363 OPTION_FIX_VR4130,
1364 OPTION_NO_FIX_VR4130,
1365 OPTION_FIX_CN63XXP1,
1366 OPTION_NO_FIX_CN63XXP1,
1367 OPTION_TRAP,
1368 OPTION_BREAK,
1369 OPTION_EB,
1370 OPTION_EL,
1371 OPTION_FP32,
1372 OPTION_GP32,
1373 OPTION_CONSTRUCT_FLOATS,
1374 OPTION_NO_CONSTRUCT_FLOATS,
1375 OPTION_FP64,
1376 OPTION_GP64,
1377 OPTION_RELAX_BRANCH,
1378 OPTION_NO_RELAX_BRANCH,
833794fc
MR
1379 OPTION_INSN32,
1380 OPTION_NO_INSN32,
c31f3936
RS
1381 OPTION_MSHARED,
1382 OPTION_MNO_SHARED,
1383 OPTION_MSYM32,
1384 OPTION_MNO_SYM32,
1385 OPTION_SOFT_FLOAT,
1386 OPTION_HARD_FLOAT,
1387 OPTION_SINGLE_FLOAT,
1388 OPTION_DOUBLE_FLOAT,
1389 OPTION_32,
c31f3936
RS
1390 OPTION_CALL_SHARED,
1391 OPTION_CALL_NONPIC,
1392 OPTION_NON_SHARED,
1393 OPTION_XGOT,
1394 OPTION_MABI,
1395 OPTION_N32,
1396 OPTION_64,
1397 OPTION_MDEBUG,
1398 OPTION_NO_MDEBUG,
1399 OPTION_PDR,
1400 OPTION_NO_PDR,
1401 OPTION_MVXWORKS_PIC,
ba92f887 1402 OPTION_NAN,
c31f3936
RS
1403 OPTION_END_OF_ENUM
1404 };
1405
1406struct option md_longopts[] =
1407{
1408 /* Options which specify architecture. */
1409 {"march", required_argument, NULL, OPTION_MARCH},
1410 {"mtune", required_argument, NULL, OPTION_MTUNE},
1411 {"mips0", no_argument, NULL, OPTION_MIPS1},
1412 {"mips1", no_argument, NULL, OPTION_MIPS1},
1413 {"mips2", no_argument, NULL, OPTION_MIPS2},
1414 {"mips3", no_argument, NULL, OPTION_MIPS3},
1415 {"mips4", no_argument, NULL, OPTION_MIPS4},
1416 {"mips5", no_argument, NULL, OPTION_MIPS5},
1417 {"mips32", no_argument, NULL, OPTION_MIPS32},
1418 {"mips64", no_argument, NULL, OPTION_MIPS64},
1419 {"mips32r2", no_argument, NULL, OPTION_MIPS32R2},
1420 {"mips64r2", no_argument, NULL, OPTION_MIPS64R2},
1421
1422 /* Options which specify Application Specific Extensions (ASEs). */
1423 {"mips16", no_argument, NULL, OPTION_MIPS16},
1424 {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16},
1425 {"mips3d", no_argument, NULL, OPTION_MIPS3D},
1426 {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D},
1427 {"mdmx", no_argument, NULL, OPTION_MDMX},
1428 {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX},
1429 {"mdsp", no_argument, NULL, OPTION_DSP},
1430 {"mno-dsp", no_argument, NULL, OPTION_NO_DSP},
1431 {"mmt", no_argument, NULL, OPTION_MT},
1432 {"mno-mt", no_argument, NULL, OPTION_NO_MT},
1433 {"msmartmips", no_argument, NULL, OPTION_SMARTMIPS},
1434 {"mno-smartmips", no_argument, NULL, OPTION_NO_SMARTMIPS},
1435 {"mdspr2", no_argument, NULL, OPTION_DSPR2},
1436 {"mno-dspr2", no_argument, NULL, OPTION_NO_DSPR2},
1437 {"meva", no_argument, NULL, OPTION_EVA},
1438 {"mno-eva", no_argument, NULL, OPTION_NO_EVA},
1439 {"mmicromips", no_argument, NULL, OPTION_MICROMIPS},
1440 {"mno-micromips", no_argument, NULL, OPTION_NO_MICROMIPS},
1441 {"mmcu", no_argument, NULL, OPTION_MCU},
1442 {"mno-mcu", no_argument, NULL, OPTION_NO_MCU},
1443 {"mvirt", no_argument, NULL, OPTION_VIRT},
1444 {"mno-virt", no_argument, NULL, OPTION_NO_VIRT},
56d438b1
CF
1445 {"mmsa", no_argument, NULL, OPTION_MSA},
1446 {"mno-msa", no_argument, NULL, OPTION_NO_MSA},
c31f3936
RS
1447
1448 /* Old-style architecture options. Don't add more of these. */
1449 {"m4650", no_argument, NULL, OPTION_M4650},
1450 {"no-m4650", no_argument, NULL, OPTION_NO_M4650},
1451 {"m4010", no_argument, NULL, OPTION_M4010},
1452 {"no-m4010", no_argument, NULL, OPTION_NO_M4010},
1453 {"m4100", no_argument, NULL, OPTION_M4100},
1454 {"no-m4100", no_argument, NULL, OPTION_NO_M4100},
1455 {"m3900", no_argument, NULL, OPTION_M3900},
1456 {"no-m3900", no_argument, NULL, OPTION_NO_M3900},
1457
1458 /* Options which enable bug fixes. */
1459 {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX},
1460 {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
1461 {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
1462 {"mfix-loongson2f-jump", no_argument, NULL, OPTION_FIX_LOONGSON2F_JUMP},
1463 {"mno-fix-loongson2f-jump", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_JUMP},
1464 {"mfix-loongson2f-nop", no_argument, NULL, OPTION_FIX_LOONGSON2F_NOP},
1465 {"mno-fix-loongson2f-nop", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_NOP},
1466 {"mfix-vr4120", no_argument, NULL, OPTION_FIX_VR4120},
1467 {"mno-fix-vr4120", no_argument, NULL, OPTION_NO_FIX_VR4120},
1468 {"mfix-vr4130", no_argument, NULL, OPTION_FIX_VR4130},
1469 {"mno-fix-vr4130", no_argument, NULL, OPTION_NO_FIX_VR4130},
1470 {"mfix-24k", no_argument, NULL, OPTION_FIX_24K},
1471 {"mno-fix-24k", no_argument, NULL, OPTION_NO_FIX_24K},
1472 {"mfix-cn63xxp1", no_argument, NULL, OPTION_FIX_CN63XXP1},
1473 {"mno-fix-cn63xxp1", no_argument, NULL, OPTION_NO_FIX_CN63XXP1},
1474
1475 /* Miscellaneous options. */
1476 {"trap", no_argument, NULL, OPTION_TRAP},
1477 {"no-break", no_argument, NULL, OPTION_TRAP},
1478 {"break", no_argument, NULL, OPTION_BREAK},
1479 {"no-trap", no_argument, NULL, OPTION_BREAK},
1480 {"EB", no_argument, NULL, OPTION_EB},
1481 {"EL", no_argument, NULL, OPTION_EL},
1482 {"mfp32", no_argument, NULL, OPTION_FP32},
1483 {"mgp32", no_argument, NULL, OPTION_GP32},
1484 {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS},
1485 {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS},
1486 {"mfp64", no_argument, NULL, OPTION_FP64},
1487 {"mgp64", no_argument, NULL, OPTION_GP64},
1488 {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH},
1489 {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH},
833794fc
MR
1490 {"minsn32", no_argument, NULL, OPTION_INSN32},
1491 {"mno-insn32", no_argument, NULL, OPTION_NO_INSN32},
c31f3936
RS
1492 {"mshared", no_argument, NULL, OPTION_MSHARED},
1493 {"mno-shared", no_argument, NULL, OPTION_MNO_SHARED},
1494 {"msym32", no_argument, NULL, OPTION_MSYM32},
1495 {"mno-sym32", no_argument, NULL, OPTION_MNO_SYM32},
1496 {"msoft-float", no_argument, NULL, OPTION_SOFT_FLOAT},
1497 {"mhard-float", no_argument, NULL, OPTION_HARD_FLOAT},
1498 {"msingle-float", no_argument, NULL, OPTION_SINGLE_FLOAT},
1499 {"mdouble-float", no_argument, NULL, OPTION_DOUBLE_FLOAT},
1500
1501 /* Strictly speaking this next option is ELF specific,
1502 but we allow it for other ports as well in order to
1503 make testing easier. */
1504 {"32", no_argument, NULL, OPTION_32},
1505
1506 /* ELF-specific options. */
c31f3936
RS
1507 {"KPIC", no_argument, NULL, OPTION_CALL_SHARED},
1508 {"call_shared", no_argument, NULL, OPTION_CALL_SHARED},
1509 {"call_nonpic", no_argument, NULL, OPTION_CALL_NONPIC},
1510 {"non_shared", no_argument, NULL, OPTION_NON_SHARED},
1511 {"xgot", no_argument, NULL, OPTION_XGOT},
1512 {"mabi", required_argument, NULL, OPTION_MABI},
1513 {"n32", no_argument, NULL, OPTION_N32},
1514 {"64", no_argument, NULL, OPTION_64},
1515 {"mdebug", no_argument, NULL, OPTION_MDEBUG},
1516 {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG},
1517 {"mpdr", no_argument, NULL, OPTION_PDR},
1518 {"mno-pdr", no_argument, NULL, OPTION_NO_PDR},
1519 {"mvxworks-pic", no_argument, NULL, OPTION_MVXWORKS_PIC},
ba92f887 1520 {"mnan", required_argument, NULL, OPTION_NAN},
c31f3936
RS
1521
1522 {NULL, no_argument, NULL, 0}
1523};
1524size_t md_longopts_size = sizeof (md_longopts);
1525\f
c6278170
RS
1526/* Information about either an Application Specific Extension or an
1527 optional architecture feature that, for simplicity, we treat in the
1528 same way as an ASE. */
1529struct mips_ase
1530{
1531 /* The name of the ASE, used in both the command-line and .set options. */
1532 const char *name;
1533
1534 /* The associated ASE_* flags. If the ASE is available on both 32-bit
1535 and 64-bit architectures, the flags here refer to the subset that
1536 is available on both. */
1537 unsigned int flags;
1538
1539 /* The ASE_* flag used for instructions that are available on 64-bit
1540 architectures but that are not included in FLAGS. */
1541 unsigned int flags64;
1542
1543 /* The command-line options that turn the ASE on and off. */
1544 int option_on;
1545 int option_off;
1546
1547 /* The minimum required architecture revisions for MIPS32, MIPS64,
1548 microMIPS32 and microMIPS64, or -1 if the extension isn't supported. */
1549 int mips32_rev;
1550 int mips64_rev;
1551 int micromips32_rev;
1552 int micromips64_rev;
1553};
1554
1555/* A table of all supported ASEs. */
1556static const struct mips_ase mips_ases[] = {
1557 { "dsp", ASE_DSP, ASE_DSP64,
1558 OPTION_DSP, OPTION_NO_DSP,
1559 2, 2, 2, 2 },
1560
1561 { "dspr2", ASE_DSP | ASE_DSPR2, 0,
1562 OPTION_DSPR2, OPTION_NO_DSPR2,
1563 2, 2, 2, 2 },
1564
1565 { "eva", ASE_EVA, 0,
1566 OPTION_EVA, OPTION_NO_EVA,
1567 2, 2, 2, 2 },
1568
1569 { "mcu", ASE_MCU, 0,
1570 OPTION_MCU, OPTION_NO_MCU,
1571 2, 2, 2, 2 },
1572
1573 /* Deprecated in MIPS64r5, but we don't implement that yet. */
1574 { "mdmx", ASE_MDMX, 0,
1575 OPTION_MDMX, OPTION_NO_MDMX,
1576 -1, 1, -1, -1 },
1577
1578 /* Requires 64-bit FPRs, so the minimum MIPS32 revision is 2. */
1579 { "mips3d", ASE_MIPS3D, 0,
1580 OPTION_MIPS3D, OPTION_NO_MIPS3D,
1581 2, 1, -1, -1 },
1582
1583 { "mt", ASE_MT, 0,
1584 OPTION_MT, OPTION_NO_MT,
1585 2, 2, -1, -1 },
1586
1587 { "smartmips", ASE_SMARTMIPS, 0,
1588 OPTION_SMARTMIPS, OPTION_NO_SMARTMIPS,
1589 1, -1, -1, -1 },
1590
1591 { "virt", ASE_VIRT, ASE_VIRT64,
1592 OPTION_VIRT, OPTION_NO_VIRT,
56d438b1
CF
1593 2, 2, 2, 2 },
1594
1595 { "msa", ASE_MSA, ASE_MSA64,
1596 OPTION_MSA, OPTION_NO_MSA,
c6278170
RS
1597 2, 2, 2, 2 }
1598};
1599
1600/* The set of ASEs that require -mfp64. */
1601#define FP64_ASES (ASE_MIPS3D | ASE_MDMX)
1602
1603/* Groups of ASE_* flags that represent different revisions of an ASE. */
1604static const unsigned int mips_ase_groups[] = {
1605 ASE_DSP | ASE_DSPR2
1606};
1607\f
252b5132
RH
1608/* Pseudo-op table.
1609
1610 The following pseudo-ops from the Kane and Heinrich MIPS book
1611 should be defined here, but are currently unsupported: .alias,
1612 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
1613
1614 The following pseudo-ops from the Kane and Heinrich MIPS book are
1615 specific to the type of debugging information being generated, and
1616 should be defined by the object format: .aent, .begin, .bend,
1617 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
1618 .vreg.
1619
1620 The following pseudo-ops from the Kane and Heinrich MIPS book are
1621 not MIPS CPU specific, but are also not specific to the object file
1622 format. This file is probably the best place to define them, but
d84bcf09 1623 they are not currently supported: .asm0, .endr, .lab, .struct. */
252b5132 1624
e972090a
NC
1625static const pseudo_typeS mips_pseudo_table[] =
1626{
beae10d5 1627 /* MIPS specific pseudo-ops. */
252b5132
RH
1628 {"option", s_option, 0},
1629 {"set", s_mipsset, 0},
1630 {"rdata", s_change_sec, 'r'},
1631 {"sdata", s_change_sec, 's'},
1632 {"livereg", s_ignore, 0},
1633 {"abicalls", s_abicalls, 0},
1634 {"cpload", s_cpload, 0},
6478892d
TS
1635 {"cpsetup", s_cpsetup, 0},
1636 {"cplocal", s_cplocal, 0},
252b5132 1637 {"cprestore", s_cprestore, 0},
6478892d 1638 {"cpreturn", s_cpreturn, 0},
741d6ea8
JM
1639 {"dtprelword", s_dtprelword, 0},
1640 {"dtpreldword", s_dtpreldword, 0},
d0f13682
CLT
1641 {"tprelword", s_tprelword, 0},
1642 {"tpreldword", s_tpreldword, 0},
6478892d 1643 {"gpvalue", s_gpvalue, 0},
252b5132 1644 {"gpword", s_gpword, 0},
10181a0d 1645 {"gpdword", s_gpdword, 0},
a3f278e2 1646 {"ehword", s_ehword, 0},
252b5132
RH
1647 {"cpadd", s_cpadd, 0},
1648 {"insn", s_insn, 0},
ba92f887 1649 {"nan", s_nan, 0},
252b5132 1650
beae10d5 1651 /* Relatively generic pseudo-ops that happen to be used on MIPS
252b5132 1652 chips. */
38a57ae7 1653 {"asciiz", stringer, 8 + 1},
252b5132
RH
1654 {"bss", s_change_sec, 'b'},
1655 {"err", s_err, 0},
1656 {"half", s_cons, 1},
1657 {"dword", s_cons, 3},
1658 {"weakext", s_mips_weakext, 0},
7c752c2a
TS
1659 {"origin", s_org, 0},
1660 {"repeat", s_rept, 0},
252b5132 1661
998b3c36
MR
1662 /* For MIPS this is non-standard, but we define it for consistency. */
1663 {"sbss", s_change_sec, 'B'},
1664
beae10d5 1665 /* These pseudo-ops are defined in read.c, but must be overridden
252b5132
RH
1666 here for one reason or another. */
1667 {"align", s_align, 0},
1668 {"byte", s_cons, 0},
1669 {"data", s_change_sec, 'd'},
1670 {"double", s_float_cons, 'd'},
1671 {"float", s_float_cons, 'f'},
1672 {"globl", s_mips_globl, 0},
1673 {"global", s_mips_globl, 0},
1674 {"hword", s_cons, 1},
1675 {"int", s_cons, 2},
1676 {"long", s_cons, 2},
1677 {"octa", s_cons, 4},
1678 {"quad", s_cons, 3},
cca86cc8 1679 {"section", s_change_section, 0},
252b5132
RH
1680 {"short", s_cons, 1},
1681 {"single", s_float_cons, 'f'},
754e2bb9 1682 {"stabd", s_mips_stab, 'd'},
252b5132 1683 {"stabn", s_mips_stab, 'n'},
754e2bb9 1684 {"stabs", s_mips_stab, 's'},
252b5132
RH
1685 {"text", s_change_sec, 't'},
1686 {"word", s_cons, 2},
add56521 1687
add56521 1688 { "extern", ecoff_directive_extern, 0},
add56521 1689
43841e91 1690 { NULL, NULL, 0 },
252b5132
RH
1691};
1692
e972090a
NC
1693static const pseudo_typeS mips_nonecoff_pseudo_table[] =
1694{
beae10d5
KH
1695 /* These pseudo-ops should be defined by the object file format.
1696 However, a.out doesn't support them, so we have versions here. */
252b5132
RH
1697 {"aent", s_mips_ent, 1},
1698 {"bgnb", s_ignore, 0},
1699 {"end", s_mips_end, 0},
1700 {"endb", s_ignore, 0},
1701 {"ent", s_mips_ent, 0},
c5dd6aab 1702 {"file", s_mips_file, 0},
252b5132
RH
1703 {"fmask", s_mips_mask, 'F'},
1704 {"frame", s_mips_frame, 0},
c5dd6aab 1705 {"loc", s_mips_loc, 0},
252b5132
RH
1706 {"mask", s_mips_mask, 'R'},
1707 {"verstamp", s_ignore, 0},
43841e91 1708 { NULL, NULL, 0 },
252b5132
RH
1709};
1710
3ae8dd8d
MR
1711/* Export the ABI address size for use by TC_ADDRESS_BYTES for the
1712 purpose of the `.dc.a' internal pseudo-op. */
1713
1714int
1715mips_address_bytes (void)
1716{
1717 return HAVE_64BIT_ADDRESSES ? 8 : 4;
1718}
1719
17a2f251 1720extern void pop_insert (const pseudo_typeS *);
252b5132
RH
1721
1722void
17a2f251 1723mips_pop_insert (void)
252b5132
RH
1724{
1725 pop_insert (mips_pseudo_table);
1726 if (! ECOFF_DEBUGGING)
1727 pop_insert (mips_nonecoff_pseudo_table);
1728}
1729\f
1730/* Symbols labelling the current insn. */
1731
e972090a
NC
1732struct insn_label_list
1733{
252b5132
RH
1734 struct insn_label_list *next;
1735 symbolS *label;
1736};
1737
252b5132 1738static struct insn_label_list *free_insn_labels;
742a56fe 1739#define label_list tc_segment_info_data.labels
252b5132 1740
17a2f251 1741static void mips_clear_insn_labels (void);
df58fc94
RS
1742static void mips_mark_labels (void);
1743static void mips_compressed_mark_labels (void);
252b5132
RH
1744
1745static inline void
17a2f251 1746mips_clear_insn_labels (void)
252b5132
RH
1747{
1748 register struct insn_label_list **pl;
a8dbcb85 1749 segment_info_type *si;
252b5132 1750
a8dbcb85
TS
1751 if (now_seg)
1752 {
1753 for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next)
1754 ;
1755
1756 si = seg_info (now_seg);
1757 *pl = si->label_list;
1758 si->label_list = NULL;
1759 }
252b5132 1760}
a8dbcb85 1761
df58fc94
RS
1762/* Mark instruction labels in MIPS16/microMIPS mode. */
1763
1764static inline void
1765mips_mark_labels (void)
1766{
1767 if (HAVE_CODE_COMPRESSION)
1768 mips_compressed_mark_labels ();
1769}
252b5132
RH
1770\f
1771static char *expr_end;
1772
e423441d 1773/* An expression in a macro instruction. This is set by mips_ip and
b0e6f033 1774 mips16_ip and when populated is always an O_constant. */
252b5132
RH
1775
1776static expressionS imm_expr;
252b5132 1777
77bd4346
RS
1778/* The relocatable field in an instruction and the relocs associated
1779 with it. These variables are used for instructions like LUI and
1780 JAL as well as true offsets. They are also used for address
1781 operands in macros. */
252b5132 1782
77bd4346 1783static expressionS offset_expr;
f6688943
TS
1784static bfd_reloc_code_real_type offset_reloc[3]
1785 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
252b5132 1786
df58fc94
RS
1787/* This is set to the resulting size of the instruction to be produced
1788 by mips16_ip if an explicit extension is used or by mips_ip if an
1789 explicit size is supplied. */
252b5132 1790
df58fc94 1791static unsigned int forced_insn_length;
252b5132 1792
e1b47bd5
RS
1793/* True if we are assembling an instruction. All dot symbols defined during
1794 this time should be treated as code labels. */
1795
1796static bfd_boolean mips_assembling_insn;
1797
ecb4347a
DJ
1798/* The pdr segment for per procedure frame/regmask info. Not used for
1799 ECOFF debugging. */
252b5132
RH
1800
1801static segT pdr_seg;
252b5132 1802
e013f690
TS
1803/* The default target format to use. */
1804
aeffff67
RS
1805#if defined (TE_FreeBSD)
1806#define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd"
1807#elif defined (TE_TMIPS)
1808#define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips"
1809#else
1810#define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips"
1811#endif
1812
e013f690 1813const char *
17a2f251 1814mips_target_format (void)
e013f690
TS
1815{
1816 switch (OUTPUT_FLAVOR)
1817 {
e013f690 1818 case bfd_target_elf_flavour:
0a44bf69
RS
1819#ifdef TE_VXWORKS
1820 if (!HAVE_64BIT_OBJECTS && !HAVE_NEWABI)
1821 return (target_big_endian
1822 ? "elf32-bigmips-vxworks"
1823 : "elf32-littlemips-vxworks");
1824#endif
e013f690 1825 return (target_big_endian
cfe86eaa 1826 ? (HAVE_64BIT_OBJECTS
aeffff67 1827 ? ELF_TARGET ("elf64-", "big")
cfe86eaa 1828 : (HAVE_NEWABI
aeffff67
RS
1829 ? ELF_TARGET ("elf32-n", "big")
1830 : ELF_TARGET ("elf32-", "big")))
cfe86eaa 1831 : (HAVE_64BIT_OBJECTS
aeffff67 1832 ? ELF_TARGET ("elf64-", "little")
cfe86eaa 1833 : (HAVE_NEWABI
aeffff67
RS
1834 ? ELF_TARGET ("elf32-n", "little")
1835 : ELF_TARGET ("elf32-", "little"))));
e013f690
TS
1836 default:
1837 abort ();
1838 return NULL;
1839 }
1840}
1841
c6278170
RS
1842/* Return the ISA revision that is currently in use, or 0 if we are
1843 generating code for MIPS V or below. */
1844
1845static int
1846mips_isa_rev (void)
1847{
1848 if (mips_opts.isa == ISA_MIPS32R2 || mips_opts.isa == ISA_MIPS64R2)
1849 return 2;
1850
1851 /* microMIPS implies revision 2 or above. */
1852 if (mips_opts.micromips)
1853 return 2;
1854
1855 if (mips_opts.isa == ISA_MIPS32 || mips_opts.isa == ISA_MIPS64)
1856 return 1;
1857
1858 return 0;
1859}
1860
1861/* Return the mask of all ASEs that are revisions of those in FLAGS. */
1862
1863static unsigned int
1864mips_ase_mask (unsigned int flags)
1865{
1866 unsigned int i;
1867
1868 for (i = 0; i < ARRAY_SIZE (mips_ase_groups); i++)
1869 if (flags & mips_ase_groups[i])
1870 flags |= mips_ase_groups[i];
1871 return flags;
1872}
1873
1874/* Check whether the current ISA supports ASE. Issue a warning if
1875 appropriate. */
1876
1877static void
1878mips_check_isa_supports_ase (const struct mips_ase *ase)
1879{
1880 const char *base;
1881 int min_rev, size;
1882 static unsigned int warned_isa;
1883 static unsigned int warned_fp32;
1884
1885 if (ISA_HAS_64BIT_REGS (mips_opts.isa))
1886 min_rev = mips_opts.micromips ? ase->micromips64_rev : ase->mips64_rev;
1887 else
1888 min_rev = mips_opts.micromips ? ase->micromips32_rev : ase->mips32_rev;
1889 if ((min_rev < 0 || mips_isa_rev () < min_rev)
1890 && (warned_isa & ase->flags) != ase->flags)
1891 {
1892 warned_isa |= ase->flags;
1893 base = mips_opts.micromips ? "microMIPS" : "MIPS";
1894 size = ISA_HAS_64BIT_REGS (mips_opts.isa) ? 64 : 32;
1895 if (min_rev < 0)
1661c76c 1896 as_warn (_("the %d-bit %s architecture does not support the"
c6278170
RS
1897 " `%s' extension"), size, base, ase->name);
1898 else
1661c76c 1899 as_warn (_("the `%s' extension requires %s%d revision %d or greater"),
c6278170
RS
1900 ase->name, base, size, min_rev);
1901 }
1902 if ((ase->flags & FP64_ASES)
1903 && mips_opts.fp32
1904 && (warned_fp32 & ase->flags) != ase->flags)
1905 {
1906 warned_fp32 |= ase->flags;
1661c76c 1907 as_warn (_("the `%s' extension requires 64-bit FPRs"), ase->name);
c6278170
RS
1908 }
1909}
1910
1911/* Check all enabled ASEs to see whether they are supported by the
1912 chosen architecture. */
1913
1914static void
1915mips_check_isa_supports_ases (void)
1916{
1917 unsigned int i, mask;
1918
1919 for (i = 0; i < ARRAY_SIZE (mips_ases); i++)
1920 {
1921 mask = mips_ase_mask (mips_ases[i].flags);
1922 if ((mips_opts.ase & mask) == mips_ases[i].flags)
1923 mips_check_isa_supports_ase (&mips_ases[i]);
1924 }
1925}
1926
1927/* Set the state of ASE to ENABLED_P. Return the mask of ASE_* flags
1928 that were affected. */
1929
1930static unsigned int
1931mips_set_ase (const struct mips_ase *ase, bfd_boolean enabled_p)
1932{
1933 unsigned int mask;
1934
1935 mask = mips_ase_mask (ase->flags);
1936 mips_opts.ase &= ~mask;
1937 if (enabled_p)
1938 mips_opts.ase |= ase->flags;
1939 return mask;
1940}
1941
1942/* Return the ASE called NAME, or null if none. */
1943
1944static const struct mips_ase *
1945mips_lookup_ase (const char *name)
1946{
1947 unsigned int i;
1948
1949 for (i = 0; i < ARRAY_SIZE (mips_ases); i++)
1950 if (strcmp (name, mips_ases[i].name) == 0)
1951 return &mips_ases[i];
1952 return NULL;
1953}
1954
df58fc94
RS
1955/* Return the length of a microMIPS instruction in bytes. If bits of
1956 the mask beyond the low 16 are 0, then it is a 16-bit instruction.
1957 Otherwise assume a 32-bit instruction; 48-bit instructions (0x1f
1958 major opcode) will require further modifications to the opcode
1959 table. */
1960
1961static inline unsigned int
1962micromips_insn_length (const struct mips_opcode *mo)
1963{
1964 return (mo->mask >> 16) == 0 ? 2 : 4;
1965}
1966
5c04167a
RS
1967/* Return the length of MIPS16 instruction OPCODE. */
1968
1969static inline unsigned int
1970mips16_opcode_length (unsigned long opcode)
1971{
1972 return (opcode >> 16) == 0 ? 2 : 4;
1973}
1974
1e915849
RS
1975/* Return the length of instruction INSN. */
1976
1977static inline unsigned int
1978insn_length (const struct mips_cl_insn *insn)
1979{
df58fc94
RS
1980 if (mips_opts.micromips)
1981 return micromips_insn_length (insn->insn_mo);
1982 else if (mips_opts.mips16)
5c04167a 1983 return mips16_opcode_length (insn->insn_opcode);
df58fc94 1984 else
1e915849 1985 return 4;
1e915849
RS
1986}
1987
1988/* Initialise INSN from opcode entry MO. Leave its position unspecified. */
1989
1990static void
1991create_insn (struct mips_cl_insn *insn, const struct mips_opcode *mo)
1992{
1993 size_t i;
1994
1995 insn->insn_mo = mo;
1e915849
RS
1996 insn->insn_opcode = mo->match;
1997 insn->frag = NULL;
1998 insn->where = 0;
1999 for (i = 0; i < ARRAY_SIZE (insn->fixp); i++)
2000 insn->fixp[i] = NULL;
2001 insn->fixed_p = (mips_opts.noreorder > 0);
2002 insn->noreorder_p = (mips_opts.noreorder > 0);
2003 insn->mips16_absolute_jump_p = 0;
15be625d 2004 insn->complete_p = 0;
e407c74b 2005 insn->cleared_p = 0;
1e915849
RS
2006}
2007
fc76e730
RS
2008/* Get a list of all the operands in INSN. */
2009
2010static const struct mips_operand_array *
2011insn_operands (const struct mips_cl_insn *insn)
2012{
2013 if (insn->insn_mo >= &mips_opcodes[0]
2014 && insn->insn_mo < &mips_opcodes[NUMOPCODES])
2015 return &mips_operands[insn->insn_mo - &mips_opcodes[0]];
2016
2017 if (insn->insn_mo >= &mips16_opcodes[0]
2018 && insn->insn_mo < &mips16_opcodes[bfd_mips16_num_opcodes])
2019 return &mips16_operands[insn->insn_mo - &mips16_opcodes[0]];
2020
2021 if (insn->insn_mo >= &micromips_opcodes[0]
2022 && insn->insn_mo < &micromips_opcodes[bfd_micromips_num_opcodes])
2023 return &micromips_operands[insn->insn_mo - &micromips_opcodes[0]];
2024
2025 abort ();
2026}
2027
2028/* Get a description of operand OPNO of INSN. */
2029
2030static const struct mips_operand *
2031insn_opno (const struct mips_cl_insn *insn, unsigned opno)
2032{
2033 const struct mips_operand_array *operands;
2034
2035 operands = insn_operands (insn);
2036 if (opno >= MAX_OPERANDS || !operands->operand[opno])
2037 abort ();
2038 return operands->operand[opno];
2039}
2040
e077a1c8
RS
2041/* Install UVAL as the value of OPERAND in INSN. */
2042
2043static inline void
2044insn_insert_operand (struct mips_cl_insn *insn,
2045 const struct mips_operand *operand, unsigned int uval)
2046{
2047 insn->insn_opcode = mips_insert_operand (operand, insn->insn_opcode, uval);
2048}
2049
fc76e730
RS
2050/* Extract the value of OPERAND from INSN. */
2051
2052static inline unsigned
2053insn_extract_operand (const struct mips_cl_insn *insn,
2054 const struct mips_operand *operand)
2055{
2056 return mips_extract_operand (operand, insn->insn_opcode);
2057}
2058
df58fc94 2059/* Record the current MIPS16/microMIPS mode in now_seg. */
742a56fe
RS
2060
2061static void
df58fc94 2062mips_record_compressed_mode (void)
742a56fe
RS
2063{
2064 segment_info_type *si;
2065
2066 si = seg_info (now_seg);
2067 if (si->tc_segment_info_data.mips16 != mips_opts.mips16)
2068 si->tc_segment_info_data.mips16 = mips_opts.mips16;
df58fc94
RS
2069 if (si->tc_segment_info_data.micromips != mips_opts.micromips)
2070 si->tc_segment_info_data.micromips = mips_opts.micromips;
742a56fe
RS
2071}
2072
4d68580a
RS
2073/* Read a standard MIPS instruction from BUF. */
2074
2075static unsigned long
2076read_insn (char *buf)
2077{
2078 if (target_big_endian)
2079 return bfd_getb32 ((bfd_byte *) buf);
2080 else
2081 return bfd_getl32 ((bfd_byte *) buf);
2082}
2083
2084/* Write standard MIPS instruction INSN to BUF. Return a pointer to
2085 the next byte. */
2086
2087static char *
2088write_insn (char *buf, unsigned int insn)
2089{
2090 md_number_to_chars (buf, insn, 4);
2091 return buf + 4;
2092}
2093
2094/* Read a microMIPS or MIPS16 opcode from BUF, given that it
2095 has length LENGTH. */
2096
2097static unsigned long
2098read_compressed_insn (char *buf, unsigned int length)
2099{
2100 unsigned long insn;
2101 unsigned int i;
2102
2103 insn = 0;
2104 for (i = 0; i < length; i += 2)
2105 {
2106 insn <<= 16;
2107 if (target_big_endian)
2108 insn |= bfd_getb16 ((char *) buf);
2109 else
2110 insn |= bfd_getl16 ((char *) buf);
2111 buf += 2;
2112 }
2113 return insn;
2114}
2115
5c04167a
RS
2116/* Write microMIPS or MIPS16 instruction INSN to BUF, given that the
2117 instruction is LENGTH bytes long. Return a pointer to the next byte. */
2118
2119static char *
2120write_compressed_insn (char *buf, unsigned int insn, unsigned int length)
2121{
2122 unsigned int i;
2123
2124 for (i = 0; i < length; i += 2)
2125 md_number_to_chars (buf + i, insn >> ((length - i - 2) * 8), 2);
2126 return buf + length;
2127}
2128
1e915849
RS
2129/* Install INSN at the location specified by its "frag" and "where" fields. */
2130
2131static void
2132install_insn (const struct mips_cl_insn *insn)
2133{
2134 char *f = insn->frag->fr_literal + insn->where;
5c04167a
RS
2135 if (HAVE_CODE_COMPRESSION)
2136 write_compressed_insn (f, insn->insn_opcode, insn_length (insn));
1e915849 2137 else
4d68580a 2138 write_insn (f, insn->insn_opcode);
df58fc94 2139 mips_record_compressed_mode ();
1e915849
RS
2140}
2141
2142/* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
2143 and install the opcode in the new location. */
2144
2145static void
2146move_insn (struct mips_cl_insn *insn, fragS *frag, long where)
2147{
2148 size_t i;
2149
2150 insn->frag = frag;
2151 insn->where = where;
2152 for (i = 0; i < ARRAY_SIZE (insn->fixp); i++)
2153 if (insn->fixp[i] != NULL)
2154 {
2155 insn->fixp[i]->fx_frag = frag;
2156 insn->fixp[i]->fx_where = where;
2157 }
2158 install_insn (insn);
2159}
2160
2161/* Add INSN to the end of the output. */
2162
2163static void
2164add_fixed_insn (struct mips_cl_insn *insn)
2165{
2166 char *f = frag_more (insn_length (insn));
2167 move_insn (insn, frag_now, f - frag_now->fr_literal);
2168}
2169
2170/* Start a variant frag and move INSN to the start of the variant part,
2171 marking it as fixed. The other arguments are as for frag_var. */
2172
2173static void
2174add_relaxed_insn (struct mips_cl_insn *insn, int max_chars, int var,
2175 relax_substateT subtype, symbolS *symbol, offsetT offset)
2176{
2177 frag_grow (max_chars);
2178 move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal);
2179 insn->fixed_p = 1;
2180 frag_var (rs_machine_dependent, max_chars, var,
2181 subtype, symbol, offset, NULL);
2182}
2183
2184/* Insert N copies of INSN into the history buffer, starting at
2185 position FIRST. Neither FIRST nor N need to be clipped. */
2186
2187static void
2188insert_into_history (unsigned int first, unsigned int n,
2189 const struct mips_cl_insn *insn)
2190{
2191 if (mips_relax.sequence != 2)
2192 {
2193 unsigned int i;
2194
2195 for (i = ARRAY_SIZE (history); i-- > first;)
2196 if (i >= first + n)
2197 history[i] = history[i - n];
2198 else
2199 history[i] = *insn;
2200 }
2201}
2202
e3de51ce
RS
2203/* Clear the error in insn_error. */
2204
2205static void
2206clear_insn_error (void)
2207{
2208 memset (&insn_error, 0, sizeof (insn_error));
2209}
2210
2211/* Possibly record error message MSG for the current instruction.
2212 If the error is about a particular argument, ARGNUM is the 1-based
2213 number of that argument, otherwise it is 0. FORMAT is the format
2214 of MSG. Return true if MSG was used, false if the current message
2215 was kept. */
2216
2217static bfd_boolean
2218set_insn_error_format (int argnum, enum mips_insn_error_format format,
2219 const char *msg)
2220{
2221 if (argnum == 0)
2222 {
2223 /* Give priority to errors against specific arguments, and to
2224 the first whole-instruction message. */
2225 if (insn_error.msg)
2226 return FALSE;
2227 }
2228 else
2229 {
2230 /* Keep insn_error if it is against a later argument. */
2231 if (argnum < insn_error.min_argnum)
2232 return FALSE;
2233
2234 /* If both errors are against the same argument but are different,
2235 give up on reporting a specific error for this argument.
2236 See the comment about mips_insn_error for details. */
2237 if (argnum == insn_error.min_argnum
2238 && insn_error.msg
2239 && strcmp (insn_error.msg, msg) != 0)
2240 {
2241 insn_error.msg = 0;
2242 insn_error.min_argnum += 1;
2243 return FALSE;
2244 }
2245 }
2246 insn_error.min_argnum = argnum;
2247 insn_error.format = format;
2248 insn_error.msg = msg;
2249 return TRUE;
2250}
2251
2252/* Record an instruction error with no % format fields. ARGNUM and MSG are
2253 as for set_insn_error_format. */
2254
2255static void
2256set_insn_error (int argnum, const char *msg)
2257{
2258 set_insn_error_format (argnum, ERR_FMT_PLAIN, msg);
2259}
2260
2261/* Record an instruction error with one %d field I. ARGNUM and MSG are
2262 as for set_insn_error_format. */
2263
2264static void
2265set_insn_error_i (int argnum, const char *msg, int i)
2266{
2267 if (set_insn_error_format (argnum, ERR_FMT_I, msg))
2268 insn_error.u.i = i;
2269}
2270
2271/* Record an instruction error with two %s fields S1 and S2. ARGNUM and MSG
2272 are as for set_insn_error_format. */
2273
2274static void
2275set_insn_error_ss (int argnum, const char *msg, const char *s1, const char *s2)
2276{
2277 if (set_insn_error_format (argnum, ERR_FMT_SS, msg))
2278 {
2279 insn_error.u.ss[0] = s1;
2280 insn_error.u.ss[1] = s2;
2281 }
2282}
2283
2284/* Report the error in insn_error, which is against assembly code STR. */
2285
2286static void
2287report_insn_error (const char *str)
2288{
2289 const char *msg;
2290
2291 msg = ACONCAT ((insn_error.msg, " `%s'", NULL));
2292 switch (insn_error.format)
2293 {
2294 case ERR_FMT_PLAIN:
2295 as_bad (msg, str);
2296 break;
2297
2298 case ERR_FMT_I:
2299 as_bad (msg, insn_error.u.i, str);
2300 break;
2301
2302 case ERR_FMT_SS:
2303 as_bad (msg, insn_error.u.ss[0], insn_error.u.ss[1], str);
2304 break;
2305 }
2306}
2307
71400594
RS
2308/* Initialize vr4120_conflicts. There is a bit of duplication here:
2309 the idea is to make it obvious at a glance that each errata is
2310 included. */
2311
2312static void
2313init_vr4120_conflicts (void)
2314{
2315#define CONFLICT(FIRST, SECOND) \
2316 vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND
2317
2318 /* Errata 21 - [D]DIV[U] after [D]MACC */
2319 CONFLICT (MACC, DIV);
2320 CONFLICT (DMACC, DIV);
2321
2322 /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */
2323 CONFLICT (DMULT, DMULT);
2324 CONFLICT (DMULT, DMACC);
2325 CONFLICT (DMACC, DMULT);
2326 CONFLICT (DMACC, DMACC);
2327
2328 /* Errata 24 - MT{LO,HI} after [D]MACC */
2329 CONFLICT (MACC, MTHILO);
2330 CONFLICT (DMACC, MTHILO);
2331
2332 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
2333 instruction is executed immediately after a MACC or DMACC
2334 instruction, the result of [either instruction] is incorrect." */
2335 CONFLICT (MACC, MULT);
2336 CONFLICT (MACC, DMULT);
2337 CONFLICT (DMACC, MULT);
2338 CONFLICT (DMACC, DMULT);
2339
2340 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
2341 executed immediately after a DMULT, DMULTU, DIV, DIVU,
2342 DDIV or DDIVU instruction, the result of the MACC or
2343 DMACC instruction is incorrect.". */
2344 CONFLICT (DMULT, MACC);
2345 CONFLICT (DMULT, DMACC);
2346 CONFLICT (DIV, MACC);
2347 CONFLICT (DIV, DMACC);
2348
2349#undef CONFLICT
2350}
2351
707bfff6
TS
2352struct regname {
2353 const char *name;
2354 unsigned int num;
2355};
2356
14daeee3 2357#define RNUM_MASK 0x00000ff
56d438b1 2358#define RTYPE_MASK 0x0ffff00
14daeee3
RS
2359#define RTYPE_NUM 0x0000100
2360#define RTYPE_FPU 0x0000200
2361#define RTYPE_FCC 0x0000400
2362#define RTYPE_VEC 0x0000800
2363#define RTYPE_GP 0x0001000
2364#define RTYPE_CP0 0x0002000
2365#define RTYPE_PC 0x0004000
2366#define RTYPE_ACC 0x0008000
2367#define RTYPE_CCC 0x0010000
2368#define RTYPE_VI 0x0020000
2369#define RTYPE_VF 0x0040000
2370#define RTYPE_R5900_I 0x0080000
2371#define RTYPE_R5900_Q 0x0100000
2372#define RTYPE_R5900_R 0x0200000
2373#define RTYPE_R5900_ACC 0x0400000
56d438b1 2374#define RTYPE_MSA 0x0800000
14daeee3 2375#define RWARN 0x8000000
707bfff6
TS
2376
2377#define GENERIC_REGISTER_NUMBERS \
2378 {"$0", RTYPE_NUM | 0}, \
2379 {"$1", RTYPE_NUM | 1}, \
2380 {"$2", RTYPE_NUM | 2}, \
2381 {"$3", RTYPE_NUM | 3}, \
2382 {"$4", RTYPE_NUM | 4}, \
2383 {"$5", RTYPE_NUM | 5}, \
2384 {"$6", RTYPE_NUM | 6}, \
2385 {"$7", RTYPE_NUM | 7}, \
2386 {"$8", RTYPE_NUM | 8}, \
2387 {"$9", RTYPE_NUM | 9}, \
2388 {"$10", RTYPE_NUM | 10}, \
2389 {"$11", RTYPE_NUM | 11}, \
2390 {"$12", RTYPE_NUM | 12}, \
2391 {"$13", RTYPE_NUM | 13}, \
2392 {"$14", RTYPE_NUM | 14}, \
2393 {"$15", RTYPE_NUM | 15}, \
2394 {"$16", RTYPE_NUM | 16}, \
2395 {"$17", RTYPE_NUM | 17}, \
2396 {"$18", RTYPE_NUM | 18}, \
2397 {"$19", RTYPE_NUM | 19}, \
2398 {"$20", RTYPE_NUM | 20}, \
2399 {"$21", RTYPE_NUM | 21}, \
2400 {"$22", RTYPE_NUM | 22}, \
2401 {"$23", RTYPE_NUM | 23}, \
2402 {"$24", RTYPE_NUM | 24}, \
2403 {"$25", RTYPE_NUM | 25}, \
2404 {"$26", RTYPE_NUM | 26}, \
2405 {"$27", RTYPE_NUM | 27}, \
2406 {"$28", RTYPE_NUM | 28}, \
2407 {"$29", RTYPE_NUM | 29}, \
2408 {"$30", RTYPE_NUM | 30}, \
2409 {"$31", RTYPE_NUM | 31}
2410
2411#define FPU_REGISTER_NAMES \
2412 {"$f0", RTYPE_FPU | 0}, \
2413 {"$f1", RTYPE_FPU | 1}, \
2414 {"$f2", RTYPE_FPU | 2}, \
2415 {"$f3", RTYPE_FPU | 3}, \
2416 {"$f4", RTYPE_FPU | 4}, \
2417 {"$f5", RTYPE_FPU | 5}, \
2418 {"$f6", RTYPE_FPU | 6}, \
2419 {"$f7", RTYPE_FPU | 7}, \
2420 {"$f8", RTYPE_FPU | 8}, \
2421 {"$f9", RTYPE_FPU | 9}, \
2422 {"$f10", RTYPE_FPU | 10}, \
2423 {"$f11", RTYPE_FPU | 11}, \
2424 {"$f12", RTYPE_FPU | 12}, \
2425 {"$f13", RTYPE_FPU | 13}, \
2426 {"$f14", RTYPE_FPU | 14}, \
2427 {"$f15", RTYPE_FPU | 15}, \
2428 {"$f16", RTYPE_FPU | 16}, \
2429 {"$f17", RTYPE_FPU | 17}, \
2430 {"$f18", RTYPE_FPU | 18}, \
2431 {"$f19", RTYPE_FPU | 19}, \
2432 {"$f20", RTYPE_FPU | 20}, \
2433 {"$f21", RTYPE_FPU | 21}, \
2434 {"$f22", RTYPE_FPU | 22}, \
2435 {"$f23", RTYPE_FPU | 23}, \
2436 {"$f24", RTYPE_FPU | 24}, \
2437 {"$f25", RTYPE_FPU | 25}, \
2438 {"$f26", RTYPE_FPU | 26}, \
2439 {"$f27", RTYPE_FPU | 27}, \
2440 {"$f28", RTYPE_FPU | 28}, \
2441 {"$f29", RTYPE_FPU | 29}, \
2442 {"$f30", RTYPE_FPU | 30}, \
2443 {"$f31", RTYPE_FPU | 31}
2444
2445#define FPU_CONDITION_CODE_NAMES \
2446 {"$fcc0", RTYPE_FCC | 0}, \
2447 {"$fcc1", RTYPE_FCC | 1}, \
2448 {"$fcc2", RTYPE_FCC | 2}, \
2449 {"$fcc3", RTYPE_FCC | 3}, \
2450 {"$fcc4", RTYPE_FCC | 4}, \
2451 {"$fcc5", RTYPE_FCC | 5}, \
2452 {"$fcc6", RTYPE_FCC | 6}, \
2453 {"$fcc7", RTYPE_FCC | 7}
2454
2455#define COPROC_CONDITION_CODE_NAMES \
2456 {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \
2457 {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \
2458 {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \
2459 {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \
2460 {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \
2461 {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \
2462 {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \
2463 {"$cc7", RTYPE_FCC | RTYPE_CCC | 7}
2464
2465#define N32N64_SYMBOLIC_REGISTER_NAMES \
2466 {"$a4", RTYPE_GP | 8}, \
2467 {"$a5", RTYPE_GP | 9}, \
2468 {"$a6", RTYPE_GP | 10}, \
2469 {"$a7", RTYPE_GP | 11}, \
2470 {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \
2471 {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \
2472 {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \
2473 {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \
2474 {"$t0", RTYPE_GP | 12}, \
2475 {"$t1", RTYPE_GP | 13}, \
2476 {"$t2", RTYPE_GP | 14}, \
2477 {"$t3", RTYPE_GP | 15}
2478
2479#define O32_SYMBOLIC_REGISTER_NAMES \
2480 {"$t0", RTYPE_GP | 8}, \
2481 {"$t1", RTYPE_GP | 9}, \
2482 {"$t2", RTYPE_GP | 10}, \
2483 {"$t3", RTYPE_GP | 11}, \
2484 {"$t4", RTYPE_GP | 12}, \
2485 {"$t5", RTYPE_GP | 13}, \
2486 {"$t6", RTYPE_GP | 14}, \
2487 {"$t7", RTYPE_GP | 15}, \
2488 {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \
2489 {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \
2490 {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \
2491 {"$ta3", RTYPE_GP | 15} /* alias for $t7 */
2492
2493/* Remaining symbolic register names */
2494#define SYMBOLIC_REGISTER_NAMES \
2495 {"$zero", RTYPE_GP | 0}, \
2496 {"$at", RTYPE_GP | 1}, \
2497 {"$AT", RTYPE_GP | 1}, \
2498 {"$v0", RTYPE_GP | 2}, \
2499 {"$v1", RTYPE_GP | 3}, \
2500 {"$a0", RTYPE_GP | 4}, \
2501 {"$a1", RTYPE_GP | 5}, \
2502 {"$a2", RTYPE_GP | 6}, \
2503 {"$a3", RTYPE_GP | 7}, \
2504 {"$s0", RTYPE_GP | 16}, \
2505 {"$s1", RTYPE_GP | 17}, \
2506 {"$s2", RTYPE_GP | 18}, \
2507 {"$s3", RTYPE_GP | 19}, \
2508 {"$s4", RTYPE_GP | 20}, \
2509 {"$s5", RTYPE_GP | 21}, \
2510 {"$s6", RTYPE_GP | 22}, \
2511 {"$s7", RTYPE_GP | 23}, \
2512 {"$t8", RTYPE_GP | 24}, \
2513 {"$t9", RTYPE_GP | 25}, \
2514 {"$k0", RTYPE_GP | 26}, \
2515 {"$kt0", RTYPE_GP | 26}, \
2516 {"$k1", RTYPE_GP | 27}, \
2517 {"$kt1", RTYPE_GP | 27}, \
2518 {"$gp", RTYPE_GP | 28}, \
2519 {"$sp", RTYPE_GP | 29}, \
2520 {"$s8", RTYPE_GP | 30}, \
2521 {"$fp", RTYPE_GP | 30}, \
2522 {"$ra", RTYPE_GP | 31}
2523
2524#define MIPS16_SPECIAL_REGISTER_NAMES \
2525 {"$pc", RTYPE_PC | 0}
2526
2527#define MDMX_VECTOR_REGISTER_NAMES \
2528 /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \
2529 /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \
2530 {"$v2", RTYPE_VEC | 2}, \
2531 {"$v3", RTYPE_VEC | 3}, \
2532 {"$v4", RTYPE_VEC | 4}, \
2533 {"$v5", RTYPE_VEC | 5}, \
2534 {"$v6", RTYPE_VEC | 6}, \
2535 {"$v7", RTYPE_VEC | 7}, \
2536 {"$v8", RTYPE_VEC | 8}, \
2537 {"$v9", RTYPE_VEC | 9}, \
2538 {"$v10", RTYPE_VEC | 10}, \
2539 {"$v11", RTYPE_VEC | 11}, \
2540 {"$v12", RTYPE_VEC | 12}, \
2541 {"$v13", RTYPE_VEC | 13}, \
2542 {"$v14", RTYPE_VEC | 14}, \
2543 {"$v15", RTYPE_VEC | 15}, \
2544 {"$v16", RTYPE_VEC | 16}, \
2545 {"$v17", RTYPE_VEC | 17}, \
2546 {"$v18", RTYPE_VEC | 18}, \
2547 {"$v19", RTYPE_VEC | 19}, \
2548 {"$v20", RTYPE_VEC | 20}, \
2549 {"$v21", RTYPE_VEC | 21}, \
2550 {"$v22", RTYPE_VEC | 22}, \
2551 {"$v23", RTYPE_VEC | 23}, \
2552 {"$v24", RTYPE_VEC | 24}, \
2553 {"$v25", RTYPE_VEC | 25}, \
2554 {"$v26", RTYPE_VEC | 26}, \
2555 {"$v27", RTYPE_VEC | 27}, \
2556 {"$v28", RTYPE_VEC | 28}, \
2557 {"$v29", RTYPE_VEC | 29}, \
2558 {"$v30", RTYPE_VEC | 30}, \
2559 {"$v31", RTYPE_VEC | 31}
2560
14daeee3
RS
2561#define R5900_I_NAMES \
2562 {"$I", RTYPE_R5900_I | 0}
2563
2564#define R5900_Q_NAMES \
2565 {"$Q", RTYPE_R5900_Q | 0}
2566
2567#define R5900_R_NAMES \
2568 {"$R", RTYPE_R5900_R | 0}
2569
2570#define R5900_ACC_NAMES \
2571 {"$ACC", RTYPE_R5900_ACC | 0 }
2572
707bfff6
TS
2573#define MIPS_DSP_ACCUMULATOR_NAMES \
2574 {"$ac0", RTYPE_ACC | 0}, \
2575 {"$ac1", RTYPE_ACC | 1}, \
2576 {"$ac2", RTYPE_ACC | 2}, \
2577 {"$ac3", RTYPE_ACC | 3}
2578
2579static const struct regname reg_names[] = {
2580 GENERIC_REGISTER_NUMBERS,
2581 FPU_REGISTER_NAMES,
2582 FPU_CONDITION_CODE_NAMES,
2583 COPROC_CONDITION_CODE_NAMES,
2584
2585 /* The $txx registers depends on the abi,
2586 these will be added later into the symbol table from
2587 one of the tables below once mips_abi is set after
2588 parsing of arguments from the command line. */
2589 SYMBOLIC_REGISTER_NAMES,
2590
2591 MIPS16_SPECIAL_REGISTER_NAMES,
2592 MDMX_VECTOR_REGISTER_NAMES,
14daeee3
RS
2593 R5900_I_NAMES,
2594 R5900_Q_NAMES,
2595 R5900_R_NAMES,
2596 R5900_ACC_NAMES,
707bfff6
TS
2597 MIPS_DSP_ACCUMULATOR_NAMES,
2598 {0, 0}
2599};
2600
2601static const struct regname reg_names_o32[] = {
2602 O32_SYMBOLIC_REGISTER_NAMES,
2603 {0, 0}
2604};
2605
2606static const struct regname reg_names_n32n64[] = {
2607 N32N64_SYMBOLIC_REGISTER_NAMES,
2608 {0, 0}
2609};
2610
a92713e6
RS
2611/* Register symbols $v0 and $v1 map to GPRs 2 and 3, but they can also be
2612 interpreted as vector registers 0 and 1. If SYMVAL is the value of one
2613 of these register symbols, return the associated vector register,
2614 otherwise return SYMVAL itself. */
df58fc94 2615
a92713e6
RS
2616static unsigned int
2617mips_prefer_vec_regno (unsigned int symval)
707bfff6 2618{
a92713e6
RS
2619 if ((symval & -2) == (RTYPE_GP | 2))
2620 return RTYPE_VEC | (symval & 1);
2621 return symval;
2622}
2623
14daeee3
RS
2624/* Return true if string [S, E) is a valid register name, storing its
2625 symbol value in *SYMVAL_PTR if so. */
a92713e6
RS
2626
2627static bfd_boolean
14daeee3 2628mips_parse_register_1 (char *s, char *e, unsigned int *symval_ptr)
a92713e6 2629{
707bfff6 2630 char save_c;
14daeee3 2631 symbolS *symbol;
707bfff6
TS
2632
2633 /* Terminate name. */
2634 save_c = *e;
2635 *e = '\0';
2636
a92713e6
RS
2637 /* Look up the name. */
2638 symbol = symbol_find (s);
2639 *e = save_c;
2640
2641 if (!symbol || S_GET_SEGMENT (symbol) != reg_section)
2642 return FALSE;
2643
14daeee3
RS
2644 *symval_ptr = S_GET_VALUE (symbol);
2645 return TRUE;
2646}
2647
2648/* Return true if the string at *SPTR is a valid register name. Allow it
2649 to have a VU0-style channel suffix of the form x?y?z?w? if CHANNELS_PTR
2650 is nonnull.
2651
2652 When returning true, move *SPTR past the register, store the
2653 register's symbol value in *SYMVAL_PTR and the channel mask in
2654 *CHANNELS_PTR (if nonnull). The symbol value includes the register
2655 number (RNUM_MASK) and register type (RTYPE_MASK). The channel mask
2656 is a 4-bit value of the form XYZW and is 0 if no suffix was given. */
2657
2658static bfd_boolean
2659mips_parse_register (char **sptr, unsigned int *symval_ptr,
2660 unsigned int *channels_ptr)
2661{
2662 char *s, *e, *m;
2663 const char *q;
2664 unsigned int channels, symval, bit;
2665
2666 /* Find end of name. */
2667 s = e = *sptr;
2668 if (is_name_beginner (*e))
2669 ++e;
2670 while (is_part_of_name (*e))
2671 ++e;
2672
2673 channels = 0;
2674 if (!mips_parse_register_1 (s, e, &symval))
2675 {
2676 if (!channels_ptr)
2677 return FALSE;
2678
2679 /* Eat characters from the end of the string that are valid
2680 channel suffixes. The preceding register must be $ACC or
2681 end with a digit, so there is no ambiguity. */
2682 bit = 1;
2683 m = e;
2684 for (q = "wzyx"; *q; q++, bit <<= 1)
2685 if (m > s && m[-1] == *q)
2686 {
2687 --m;
2688 channels |= bit;
2689 }
2690
2691 if (channels == 0
2692 || !mips_parse_register_1 (s, m, &symval)
2693 || (symval & (RTYPE_VI | RTYPE_VF | RTYPE_R5900_ACC)) == 0)
2694 return FALSE;
2695 }
2696
a92713e6 2697 *sptr = e;
14daeee3
RS
2698 *symval_ptr = symval;
2699 if (channels_ptr)
2700 *channels_ptr = channels;
a92713e6
RS
2701 return TRUE;
2702}
2703
2704/* Check if SPTR points at a valid register specifier according to TYPES.
2705 If so, then return 1, advance S to consume the specifier and store
2706 the register's number in REGNOP, otherwise return 0. */
2707
2708static int
2709reg_lookup (char **s, unsigned int types, unsigned int *regnop)
2710{
2711 unsigned int regno;
2712
14daeee3 2713 if (mips_parse_register (s, &regno, NULL))
707bfff6 2714 {
a92713e6
RS
2715 if (types & RTYPE_VEC)
2716 regno = mips_prefer_vec_regno (regno);
2717 if (regno & types)
2718 regno &= RNUM_MASK;
2719 else
2720 regno = ~0;
707bfff6 2721 }
a92713e6 2722 else
707bfff6 2723 {
a92713e6 2724 if (types & RWARN)
1661c76c 2725 as_warn (_("unrecognized register name `%s'"), *s);
a92713e6 2726 regno = ~0;
707bfff6 2727 }
707bfff6 2728 if (regnop)
a92713e6
RS
2729 *regnop = regno;
2730 return regno <= RNUM_MASK;
707bfff6
TS
2731}
2732
14daeee3
RS
2733/* Parse a VU0 "x?y?z?w?" channel mask at S and store the associated
2734 mask in *CHANNELS. Return a pointer to the first unconsumed character. */
2735
2736static char *
2737mips_parse_vu0_channels (char *s, unsigned int *channels)
2738{
2739 unsigned int i;
2740
2741 *channels = 0;
2742 for (i = 0; i < 4; i++)
2743 if (*s == "xyzw"[i])
2744 {
2745 *channels |= 1 << (3 - i);
2746 ++s;
2747 }
2748 return s;
2749}
2750
a92713e6
RS
2751/* Token types for parsed operand lists. */
2752enum mips_operand_token_type {
2753 /* A plain register, e.g. $f2. */
2754 OT_REG,
df58fc94 2755
14daeee3
RS
2756 /* A 4-bit XYZW channel mask. */
2757 OT_CHANNELS,
2758
56d438b1
CF
2759 /* A constant vector index, e.g. [1]. */
2760 OT_INTEGER_INDEX,
2761
2762 /* A register vector index, e.g. [$2]. */
2763 OT_REG_INDEX,
df58fc94 2764
a92713e6
RS
2765 /* A continuous range of registers, e.g. $s0-$s4. */
2766 OT_REG_RANGE,
2767
2768 /* A (possibly relocated) expression. */
2769 OT_INTEGER,
2770
2771 /* A floating-point value. */
2772 OT_FLOAT,
2773
2774 /* A single character. This can be '(', ')' or ',', but '(' only appears
2775 before OT_REGs. */
2776 OT_CHAR,
2777
14daeee3
RS
2778 /* A doubled character, either "--" or "++". */
2779 OT_DOUBLE_CHAR,
2780
a92713e6
RS
2781 /* The end of the operand list. */
2782 OT_END
2783};
2784
2785/* A parsed operand token. */
2786struct mips_operand_token
2787{
2788 /* The type of token. */
2789 enum mips_operand_token_type type;
2790 union
2791 {
56d438b1 2792 /* The register symbol value for an OT_REG or OT_REG_INDEX. */
a92713e6
RS
2793 unsigned int regno;
2794
14daeee3
RS
2795 /* The 4-bit channel mask for an OT_CHANNEL_SUFFIX. */
2796 unsigned int channels;
2797
56d438b1
CF
2798 /* The integer value of an OT_INTEGER_INDEX. */
2799 addressT index;
a92713e6
RS
2800
2801 /* The two register symbol values involved in an OT_REG_RANGE. */
2802 struct {
2803 unsigned int regno1;
2804 unsigned int regno2;
2805 } reg_range;
2806
2807 /* The value of an OT_INTEGER. The value is represented as an
2808 expression and the relocation operators that were applied to
2809 that expression. The reloc entries are BFD_RELOC_UNUSED if no
2810 relocation operators were used. */
2811 struct {
2812 expressionS value;
2813 bfd_reloc_code_real_type relocs[3];
2814 } integer;
2815
2816 /* The binary data for an OT_FLOAT constant, and the number of bytes
2817 in the constant. */
2818 struct {
2819 unsigned char data[8];
2820 int length;
2821 } flt;
2822
14daeee3 2823 /* The character represented by an OT_CHAR or OT_DOUBLE_CHAR. */
a92713e6
RS
2824 char ch;
2825 } u;
2826};
2827
2828/* An obstack used to construct lists of mips_operand_tokens. */
2829static struct obstack mips_operand_tokens;
2830
2831/* Give TOKEN type TYPE and add it to mips_operand_tokens. */
2832
2833static void
2834mips_add_token (struct mips_operand_token *token,
2835 enum mips_operand_token_type type)
2836{
2837 token->type = type;
2838 obstack_grow (&mips_operand_tokens, token, sizeof (*token));
2839}
2840
2841/* Check whether S is '(' followed by a register name. Add OT_CHAR
2842 and OT_REG tokens for them if so, and return a pointer to the first
2843 unconsumed character. Return null otherwise. */
2844
2845static char *
2846mips_parse_base_start (char *s)
2847{
2848 struct mips_operand_token token;
14daeee3
RS
2849 unsigned int regno, channels;
2850 bfd_boolean decrement_p;
df58fc94 2851
a92713e6
RS
2852 if (*s != '(')
2853 return 0;
2854
2855 ++s;
2856 SKIP_SPACE_TABS (s);
14daeee3
RS
2857
2858 /* Only match "--" as part of a base expression. In other contexts "--X"
2859 is a double negative. */
2860 decrement_p = (s[0] == '-' && s[1] == '-');
2861 if (decrement_p)
2862 {
2863 s += 2;
2864 SKIP_SPACE_TABS (s);
2865 }
2866
2867 /* Allow a channel specifier because that leads to better error messages
2868 than treating something like "$vf0x++" as an expression. */
2869 if (!mips_parse_register (&s, &regno, &channels))
a92713e6
RS
2870 return 0;
2871
2872 token.u.ch = '(';
2873 mips_add_token (&token, OT_CHAR);
2874
14daeee3
RS
2875 if (decrement_p)
2876 {
2877 token.u.ch = '-';
2878 mips_add_token (&token, OT_DOUBLE_CHAR);
2879 }
2880
a92713e6
RS
2881 token.u.regno = regno;
2882 mips_add_token (&token, OT_REG);
2883
14daeee3
RS
2884 if (channels)
2885 {
2886 token.u.channels = channels;
2887 mips_add_token (&token, OT_CHANNELS);
2888 }
2889
2890 /* For consistency, only match "++" as part of base expressions too. */
2891 SKIP_SPACE_TABS (s);
2892 if (s[0] == '+' && s[1] == '+')
2893 {
2894 s += 2;
2895 token.u.ch = '+';
2896 mips_add_token (&token, OT_DOUBLE_CHAR);
2897 }
2898
a92713e6
RS
2899 return s;
2900}
2901
2902/* Parse one or more tokens from S. Return a pointer to the first
2903 unconsumed character on success. Return null if an error was found
2904 and store the error text in insn_error. FLOAT_FORMAT is as for
2905 mips_parse_arguments. */
2906
2907static char *
2908mips_parse_argument_token (char *s, char float_format)
2909{
2910 char *end, *save_in, *err;
14daeee3 2911 unsigned int regno1, regno2, channels;
a92713e6
RS
2912 struct mips_operand_token token;
2913
2914 /* First look for "($reg", since we want to treat that as an
2915 OT_CHAR and OT_REG rather than an expression. */
2916 end = mips_parse_base_start (s);
2917 if (end)
2918 return end;
2919
2920 /* Handle other characters that end up as OT_CHARs. */
2921 if (*s == ')' || *s == ',')
2922 {
2923 token.u.ch = *s;
2924 mips_add_token (&token, OT_CHAR);
2925 ++s;
2926 return s;
2927 }
2928
2929 /* Handle tokens that start with a register. */
14daeee3 2930 if (mips_parse_register (&s, &regno1, &channels))
df58fc94 2931 {
14daeee3
RS
2932 if (channels)
2933 {
2934 /* A register and a VU0 channel suffix. */
2935 token.u.regno = regno1;
2936 mips_add_token (&token, OT_REG);
2937
2938 token.u.channels = channels;
2939 mips_add_token (&token, OT_CHANNELS);
2940 return s;
2941 }
2942
a92713e6
RS
2943 SKIP_SPACE_TABS (s);
2944 if (*s == '-')
df58fc94 2945 {
a92713e6
RS
2946 /* A register range. */
2947 ++s;
2948 SKIP_SPACE_TABS (s);
14daeee3 2949 if (!mips_parse_register (&s, &regno2, NULL))
a92713e6 2950 {
1661c76c 2951 set_insn_error (0, _("invalid register range"));
a92713e6
RS
2952 return 0;
2953 }
df58fc94 2954
a92713e6
RS
2955 token.u.reg_range.regno1 = regno1;
2956 token.u.reg_range.regno2 = regno2;
2957 mips_add_token (&token, OT_REG_RANGE);
2958 return s;
2959 }
a92713e6 2960
56d438b1
CF
2961 /* Add the register itself. */
2962 token.u.regno = regno1;
2963 mips_add_token (&token, OT_REG);
2964
2965 /* Check for a vector index. */
2966 if (*s == '[')
2967 {
a92713e6
RS
2968 ++s;
2969 SKIP_SPACE_TABS (s);
56d438b1
CF
2970 if (mips_parse_register (&s, &token.u.regno, NULL))
2971 mips_add_token (&token, OT_REG_INDEX);
2972 else
a92713e6 2973 {
56d438b1
CF
2974 expressionS element;
2975
2976 my_getExpression (&element, s);
2977 if (element.X_op != O_constant)
2978 {
2979 set_insn_error (0, _("vector element must be constant"));
2980 return 0;
2981 }
2982 s = expr_end;
2983 token.u.index = element.X_add_number;
2984 mips_add_token (&token, OT_INTEGER_INDEX);
a92713e6 2985 }
a92713e6
RS
2986 SKIP_SPACE_TABS (s);
2987 if (*s != ']')
2988 {
1661c76c 2989 set_insn_error (0, _("missing `]'"));
a92713e6
RS
2990 return 0;
2991 }
2992 ++s;
df58fc94 2993 }
a92713e6 2994 return s;
df58fc94
RS
2995 }
2996
a92713e6
RS
2997 if (float_format)
2998 {
2999 /* First try to treat expressions as floats. */
3000 save_in = input_line_pointer;
3001 input_line_pointer = s;
3002 err = md_atof (float_format, (char *) token.u.flt.data,
3003 &token.u.flt.length);
3004 end = input_line_pointer;
3005 input_line_pointer = save_in;
3006 if (err && *err)
3007 {
e3de51ce 3008 set_insn_error (0, err);
a92713e6
RS
3009 return 0;
3010 }
3011 if (s != end)
3012 {
3013 mips_add_token (&token, OT_FLOAT);
3014 return end;
3015 }
3016 }
3017
3018 /* Treat everything else as an integer expression. */
3019 token.u.integer.relocs[0] = BFD_RELOC_UNUSED;
3020 token.u.integer.relocs[1] = BFD_RELOC_UNUSED;
3021 token.u.integer.relocs[2] = BFD_RELOC_UNUSED;
3022 my_getSmallExpression (&token.u.integer.value, token.u.integer.relocs, s);
3023 s = expr_end;
3024 mips_add_token (&token, OT_INTEGER);
3025 return s;
3026}
3027
3028/* S points to the operand list for an instruction. FLOAT_FORMAT is 'f'
3029 if expressions should be treated as 32-bit floating-point constants,
3030 'd' if they should be treated as 64-bit floating-point constants,
3031 or 0 if they should be treated as integer expressions (the usual case).
3032
3033 Return a list of tokens on success, otherwise return 0. The caller
3034 must obstack_free the list after use. */
3035
3036static struct mips_operand_token *
3037mips_parse_arguments (char *s, char float_format)
3038{
3039 struct mips_operand_token token;
3040
3041 SKIP_SPACE_TABS (s);
3042 while (*s)
3043 {
3044 s = mips_parse_argument_token (s, float_format);
3045 if (!s)
3046 {
3047 obstack_free (&mips_operand_tokens,
3048 obstack_finish (&mips_operand_tokens));
3049 return 0;
3050 }
3051 SKIP_SPACE_TABS (s);
3052 }
3053 mips_add_token (&token, OT_END);
3054 return (struct mips_operand_token *) obstack_finish (&mips_operand_tokens);
df58fc94
RS
3055}
3056
d301a56b
RS
3057/* Return TRUE if opcode MO is valid on the currently selected ISA, ASE
3058 and architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */
037b32b9
AN
3059
3060static bfd_boolean
f79e2745 3061is_opcode_valid (const struct mips_opcode *mo)
037b32b9
AN
3062{
3063 int isa = mips_opts.isa;
846ef2d0 3064 int ase = mips_opts.ase;
037b32b9 3065 int fp_s, fp_d;
c6278170 3066 unsigned int i;
037b32b9 3067
c6278170
RS
3068 if (ISA_HAS_64BIT_REGS (mips_opts.isa))
3069 for (i = 0; i < ARRAY_SIZE (mips_ases); i++)
3070 if ((ase & mips_ases[i].flags) == mips_ases[i].flags)
3071 ase |= mips_ases[i].flags64;
037b32b9 3072
d301a56b 3073 if (!opcode_is_member (mo, isa, ase, mips_opts.arch))
037b32b9
AN
3074 return FALSE;
3075
3076 /* Check whether the instruction or macro requires single-precision or
3077 double-precision floating-point support. Note that this information is
3078 stored differently in the opcode table for insns and macros. */
3079 if (mo->pinfo == INSN_MACRO)
3080 {
3081 fp_s = mo->pinfo2 & INSN2_M_FP_S;
3082 fp_d = mo->pinfo2 & INSN2_M_FP_D;
3083 }
3084 else
3085 {
3086 fp_s = mo->pinfo & FP_S;
3087 fp_d = mo->pinfo & FP_D;
3088 }
3089
3090 if (fp_d && (mips_opts.soft_float || mips_opts.single_float))
3091 return FALSE;
3092
3093 if (fp_s && mips_opts.soft_float)
3094 return FALSE;
3095
3096 return TRUE;
3097}
3098
3099/* Return TRUE if the MIPS16 opcode MO is valid on the currently
3100 selected ISA and architecture. */
3101
3102static bfd_boolean
3103is_opcode_valid_16 (const struct mips_opcode *mo)
3104{
d301a56b 3105 return opcode_is_member (mo, mips_opts.isa, 0, mips_opts.arch);
037b32b9
AN
3106}
3107
df58fc94
RS
3108/* Return TRUE if the size of the microMIPS opcode MO matches one
3109 explicitly requested. Always TRUE in the standard MIPS mode. */
3110
3111static bfd_boolean
3112is_size_valid (const struct mips_opcode *mo)
3113{
3114 if (!mips_opts.micromips)
3115 return TRUE;
3116
833794fc
MR
3117 if (mips_opts.insn32)
3118 {
3119 if (mo->pinfo != INSN_MACRO && micromips_insn_length (mo) != 4)
3120 return FALSE;
3121 if ((mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0)
3122 return FALSE;
3123 }
df58fc94
RS
3124 if (!forced_insn_length)
3125 return TRUE;
3126 if (mo->pinfo == INSN_MACRO)
3127 return FALSE;
3128 return forced_insn_length == micromips_insn_length (mo);
3129}
3130
3131/* Return TRUE if the microMIPS opcode MO is valid for the delay slot
e64af278
MR
3132 of the preceding instruction. Always TRUE in the standard MIPS mode.
3133
3134 We don't accept macros in 16-bit delay slots to avoid a case where
3135 a macro expansion fails because it relies on a preceding 32-bit real
3136 instruction to have matched and does not handle the operands correctly.
3137 The only macros that may expand to 16-bit instructions are JAL that
3138 cannot be placed in a delay slot anyway, and corner cases of BALIGN
3139 and BGT (that likewise cannot be placed in a delay slot) that decay to
3140 a NOP. In all these cases the macros precede any corresponding real
3141 instruction definitions in the opcode table, so they will match in the
3142 second pass where the size of the delay slot is ignored and therefore
3143 produce correct code. */
df58fc94
RS
3144
3145static bfd_boolean
3146is_delay_slot_valid (const struct mips_opcode *mo)
3147{
3148 if (!mips_opts.micromips)
3149 return TRUE;
3150
3151 if (mo->pinfo == INSN_MACRO)
c06dec14 3152 return (history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) == 0;
df58fc94
RS
3153 if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0
3154 && micromips_insn_length (mo) != 4)
3155 return FALSE;
3156 if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0
3157 && micromips_insn_length (mo) != 2)
3158 return FALSE;
3159
3160 return TRUE;
3161}
3162
fc76e730
RS
3163/* For consistency checking, verify that all bits of OPCODE are specified
3164 either by the match/mask part of the instruction definition, or by the
3165 operand list. Also build up a list of operands in OPERANDS.
3166
3167 INSN_BITS says which bits of the instruction are significant.
3168 If OPCODE is a standard or microMIPS instruction, DECODE_OPERAND
3169 provides the mips_operand description of each operand. DECODE_OPERAND
3170 is null for MIPS16 instructions. */
ab902481
RS
3171
3172static int
3173validate_mips_insn (const struct mips_opcode *opcode,
3174 unsigned long insn_bits,
fc76e730
RS
3175 const struct mips_operand *(*decode_operand) (const char *),
3176 struct mips_operand_array *operands)
ab902481
RS
3177{
3178 const char *s;
fc76e730 3179 unsigned long used_bits, doubled, undefined, opno, mask;
ab902481
RS
3180 const struct mips_operand *operand;
3181
fc76e730
RS
3182 mask = (opcode->pinfo == INSN_MACRO ? 0 : opcode->mask);
3183 if ((mask & opcode->match) != opcode->match)
ab902481
RS
3184 {
3185 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
3186 opcode->name, opcode->args);
3187 return 0;
3188 }
3189 used_bits = 0;
fc76e730 3190 opno = 0;
14daeee3
RS
3191 if (opcode->pinfo2 & INSN2_VU0_CHANNEL_SUFFIX)
3192 used_bits = mips_insert_operand (&mips_vu0_channel_mask, used_bits, -1);
ab902481
RS
3193 for (s = opcode->args; *s; ++s)
3194 switch (*s)
3195 {
3196 case ',':
3197 case '(':
3198 case ')':
3199 break;
3200
14daeee3
RS
3201 case '#':
3202 s++;
3203 break;
3204
ab902481 3205 default:
fc76e730
RS
3206 if (!decode_operand)
3207 operand = decode_mips16_operand (*s, FALSE);
3208 else
3209 operand = decode_operand (s);
3210 if (!operand && opcode->pinfo != INSN_MACRO)
ab902481
RS
3211 {
3212 as_bad (_("internal: unknown operand type: %s %s"),
3213 opcode->name, opcode->args);
3214 return 0;
3215 }
fc76e730
RS
3216 gas_assert (opno < MAX_OPERANDS);
3217 operands->operand[opno] = operand;
14daeee3 3218 if (operand && operand->type != OP_VU0_MATCH_SUFFIX)
fc76e730 3219 {
14daeee3 3220 used_bits = mips_insert_operand (operand, used_bits, -1);
fc76e730
RS
3221 if (operand->type == OP_MDMX_IMM_REG)
3222 /* Bit 5 is the format selector (OB vs QH). The opcode table
3223 has separate entries for each format. */
3224 used_bits &= ~(1 << (operand->lsb + 5));
3225 if (operand->type == OP_ENTRY_EXIT_LIST)
3226 used_bits &= ~(mask & 0x700);
3227 }
ab902481 3228 /* Skip prefix characters. */
fc76e730 3229 if (decode_operand && (*s == '+' || *s == 'm'))
ab902481 3230 ++s;
fc76e730 3231 opno += 1;
ab902481
RS
3232 break;
3233 }
fc76e730 3234 doubled = used_bits & mask & insn_bits;
ab902481
RS
3235 if (doubled)
3236 {
3237 as_bad (_("internal: bad mips opcode (bits 0x%08lx doubly defined):"
3238 " %s %s"), doubled, opcode->name, opcode->args);
3239 return 0;
3240 }
fc76e730 3241 used_bits |= mask;
ab902481 3242 undefined = ~used_bits & insn_bits;
fc76e730 3243 if (opcode->pinfo != INSN_MACRO && undefined)
ab902481
RS
3244 {
3245 as_bad (_("internal: bad mips opcode (bits 0x%08lx undefined): %s %s"),
3246 undefined, opcode->name, opcode->args);
3247 return 0;
3248 }
3249 used_bits &= ~insn_bits;
3250 if (used_bits)
3251 {
3252 as_bad (_("internal: bad mips opcode (bits 0x%08lx defined): %s %s"),
3253 used_bits, opcode->name, opcode->args);
3254 return 0;
3255 }
3256 return 1;
3257}
3258
fc76e730
RS
3259/* The MIPS16 version of validate_mips_insn. */
3260
3261static int
3262validate_mips16_insn (const struct mips_opcode *opcode,
3263 struct mips_operand_array *operands)
3264{
3265 if (opcode->args[0] == 'a' || opcode->args[0] == 'i')
3266 {
3267 /* In this case OPCODE defines the first 16 bits in a 32-bit jump
3268 instruction. Use TMP to describe the full instruction. */
3269 struct mips_opcode tmp;
3270
3271 tmp = *opcode;
3272 tmp.match <<= 16;
3273 tmp.mask <<= 16;
3274 return validate_mips_insn (&tmp, 0xffffffff, 0, operands);
3275 }
3276 return validate_mips_insn (opcode, 0xffff, 0, operands);
3277}
3278
ab902481
RS
3279/* The microMIPS version of validate_mips_insn. */
3280
3281static int
fc76e730
RS
3282validate_micromips_insn (const struct mips_opcode *opc,
3283 struct mips_operand_array *operands)
ab902481
RS
3284{
3285 unsigned long insn_bits;
3286 unsigned long major;
3287 unsigned int length;
3288
fc76e730
RS
3289 if (opc->pinfo == INSN_MACRO)
3290 return validate_mips_insn (opc, 0xffffffff, decode_micromips_operand,
3291 operands);
3292
ab902481
RS
3293 length = micromips_insn_length (opc);
3294 if (length != 2 && length != 4)
3295 {
1661c76c 3296 as_bad (_("internal error: bad microMIPS opcode (incorrect length: %u): "
ab902481
RS
3297 "%s %s"), length, opc->name, opc->args);
3298 return 0;
3299 }
3300 major = opc->match >> (10 + 8 * (length - 2));
3301 if ((length == 2 && (major & 7) != 1 && (major & 6) != 2)
3302 || (length == 4 && (major & 7) != 0 && (major & 4) != 4))
3303 {
1661c76c 3304 as_bad (_("internal error: bad microMIPS opcode "
ab902481
RS
3305 "(opcode/length mismatch): %s %s"), opc->name, opc->args);
3306 return 0;
3307 }
3308
3309 /* Shift piecewise to avoid an overflow where unsigned long is 32-bit. */
3310 insn_bits = 1 << 4 * length;
3311 insn_bits <<= 4 * length;
3312 insn_bits -= 1;
fc76e730
RS
3313 return validate_mips_insn (opc, insn_bits, decode_micromips_operand,
3314 operands);
ab902481
RS
3315}
3316
707bfff6
TS
3317/* This function is called once, at assembler startup time. It should set up
3318 all the tables, etc. that the MD part of the assembler will need. */
156c2f8b 3319
252b5132 3320void
17a2f251 3321md_begin (void)
252b5132 3322{
3994f87e 3323 const char *retval = NULL;
156c2f8b 3324 int i = 0;
252b5132 3325 int broken = 0;
1f25f5d3 3326
0a44bf69
RS
3327 if (mips_pic != NO_PIC)
3328 {
3329 if (g_switch_seen && g_switch_value != 0)
3330 as_bad (_("-G may not be used in position-independent code"));
3331 g_switch_value = 0;
3332 }
3333
fef14a42 3334 if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_arch))
1661c76c 3335 as_warn (_("could not set architecture and machine"));
252b5132 3336
252b5132
RH
3337 op_hash = hash_new ();
3338
fc76e730 3339 mips_operands = XCNEWVEC (struct mips_operand_array, NUMOPCODES);
252b5132
RH
3340 for (i = 0; i < NUMOPCODES;)
3341 {
3342 const char *name = mips_opcodes[i].name;
3343
17a2f251 3344 retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]);
252b5132
RH
3345 if (retval != NULL)
3346 {
3347 fprintf (stderr, _("internal error: can't hash `%s': %s\n"),
3348 mips_opcodes[i].name, retval);
3349 /* Probably a memory allocation problem? Give up now. */
1661c76c 3350 as_fatal (_("broken assembler, no assembly attempted"));
252b5132
RH
3351 }
3352 do
3353 {
fc76e730
RS
3354 if (!validate_mips_insn (&mips_opcodes[i], 0xffffffff,
3355 decode_mips_operand, &mips_operands[i]))
3356 broken = 1;
3357 if (nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0)
252b5132 3358 {
fc76e730
RS
3359 create_insn (&nop_insn, mips_opcodes + i);
3360 if (mips_fix_loongson2f_nop)
3361 nop_insn.insn_opcode = LOONGSON2F_NOP_INSN;
3362 nop_insn.fixed_p = 1;
252b5132
RH
3363 }
3364 ++i;
3365 }
3366 while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name));
3367 }
3368
3369 mips16_op_hash = hash_new ();
fc76e730
RS
3370 mips16_operands = XCNEWVEC (struct mips_operand_array,
3371 bfd_mips16_num_opcodes);
252b5132
RH
3372
3373 i = 0;
3374 while (i < bfd_mips16_num_opcodes)
3375 {
3376 const char *name = mips16_opcodes[i].name;
3377
17a2f251 3378 retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]);
252b5132
RH
3379 if (retval != NULL)
3380 as_fatal (_("internal: can't hash `%s': %s"),
3381 mips16_opcodes[i].name, retval);
3382 do
3383 {
fc76e730
RS
3384 if (!validate_mips16_insn (&mips16_opcodes[i], &mips16_operands[i]))
3385 broken = 1;
1e915849
RS
3386 if (mips16_nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0)
3387 {
3388 create_insn (&mips16_nop_insn, mips16_opcodes + i);
3389 mips16_nop_insn.fixed_p = 1;
3390 }
252b5132
RH
3391 ++i;
3392 }
3393 while (i < bfd_mips16_num_opcodes
3394 && strcmp (mips16_opcodes[i].name, name) == 0);
3395 }
3396
df58fc94 3397 micromips_op_hash = hash_new ();
fc76e730
RS
3398 micromips_operands = XCNEWVEC (struct mips_operand_array,
3399 bfd_micromips_num_opcodes);
df58fc94
RS
3400
3401 i = 0;
3402 while (i < bfd_micromips_num_opcodes)
3403 {
3404 const char *name = micromips_opcodes[i].name;
3405
3406 retval = hash_insert (micromips_op_hash, name,
3407 (void *) &micromips_opcodes[i]);
3408 if (retval != NULL)
3409 as_fatal (_("internal: can't hash `%s': %s"),
3410 micromips_opcodes[i].name, retval);
3411 do
fc76e730
RS
3412 {
3413 struct mips_cl_insn *micromips_nop_insn;
3414
3415 if (!validate_micromips_insn (&micromips_opcodes[i],
3416 &micromips_operands[i]))
3417 broken = 1;
3418
3419 if (micromips_opcodes[i].pinfo != INSN_MACRO)
3420 {
3421 if (micromips_insn_length (micromips_opcodes + i) == 2)
3422 micromips_nop_insn = &micromips_nop16_insn;
3423 else if (micromips_insn_length (micromips_opcodes + i) == 4)
3424 micromips_nop_insn = &micromips_nop32_insn;
3425 else
3426 continue;
3427
3428 if (micromips_nop_insn->insn_mo == NULL
3429 && strcmp (name, "nop") == 0)
3430 {
3431 create_insn (micromips_nop_insn, micromips_opcodes + i);
3432 micromips_nop_insn->fixed_p = 1;
3433 }
3434 }
3435 }
df58fc94
RS
3436 while (++i < bfd_micromips_num_opcodes
3437 && strcmp (micromips_opcodes[i].name, name) == 0);
3438 }
3439
252b5132 3440 if (broken)
1661c76c 3441 as_fatal (_("broken assembler, no assembly attempted"));
252b5132
RH
3442
3443 /* We add all the general register names to the symbol table. This
3444 helps us detect invalid uses of them. */
707bfff6
TS
3445 for (i = 0; reg_names[i].name; i++)
3446 symbol_table_insert (symbol_new (reg_names[i].name, reg_section,
8fc4ee9b 3447 reg_names[i].num, /* & RNUM_MASK, */
707bfff6
TS
3448 &zero_address_frag));
3449 if (HAVE_NEWABI)
3450 for (i = 0; reg_names_n32n64[i].name; i++)
3451 symbol_table_insert (symbol_new (reg_names_n32n64[i].name, reg_section,
8fc4ee9b 3452 reg_names_n32n64[i].num, /* & RNUM_MASK, */
252b5132 3453 &zero_address_frag));
707bfff6
TS
3454 else
3455 for (i = 0; reg_names_o32[i].name; i++)
3456 symbol_table_insert (symbol_new (reg_names_o32[i].name, reg_section,
8fc4ee9b 3457 reg_names_o32[i].num, /* & RNUM_MASK, */
6047c971 3458 &zero_address_frag));
6047c971 3459
14daeee3
RS
3460 for (i = 0; i < 32; i++)
3461 {
3462 char regname[7];
3463
3464 /* R5900 VU0 floating-point register. */
3465 regname[sizeof (rename) - 1] = 0;
3466 snprintf (regname, sizeof (regname) - 1, "$vf%d", i);
3467 symbol_table_insert (symbol_new (regname, reg_section,
3468 RTYPE_VF | i, &zero_address_frag));
3469
3470 /* R5900 VU0 integer register. */
3471 snprintf (regname, sizeof (regname) - 1, "$vi%d", i);
3472 symbol_table_insert (symbol_new (regname, reg_section,
3473 RTYPE_VI | i, &zero_address_frag));
3474
56d438b1
CF
3475 /* MSA register. */
3476 snprintf (regname, sizeof (regname) - 1, "$w%d", i);
3477 symbol_table_insert (symbol_new (regname, reg_section,
3478 RTYPE_MSA | i, &zero_address_frag));
14daeee3
RS
3479 }
3480
a92713e6
RS
3481 obstack_init (&mips_operand_tokens);
3482
7d10b47d 3483 mips_no_prev_insn ();
252b5132
RH
3484
3485 mips_gprmask = 0;
3486 mips_cprmask[0] = 0;
3487 mips_cprmask[1] = 0;
3488 mips_cprmask[2] = 0;
3489 mips_cprmask[3] = 0;
3490
3491 /* set the default alignment for the text section (2**2) */
3492 record_alignment (text_section, 2);
3493
4d0d148d 3494 bfd_set_gp_size (stdoutput, g_switch_value);
252b5132 3495
f3ded42a
RS
3496 /* On a native system other than VxWorks, sections must be aligned
3497 to 16 byte boundaries. When configured for an embedded ELF
3498 target, we don't bother. */
3499 if (strncmp (TARGET_OS, "elf", 3) != 0
3500 && strncmp (TARGET_OS, "vxworks", 7) != 0)
252b5132 3501 {
f3ded42a
RS
3502 (void) bfd_set_section_alignment (stdoutput, text_section, 4);
3503 (void) bfd_set_section_alignment (stdoutput, data_section, 4);
3504 (void) bfd_set_section_alignment (stdoutput, bss_section, 4);
3505 }
252b5132 3506
f3ded42a
RS
3507 /* Create a .reginfo section for register masks and a .mdebug
3508 section for debugging information. */
3509 {
3510 segT seg;
3511 subsegT subseg;
3512 flagword flags;
3513 segT sec;
3514
3515 seg = now_seg;
3516 subseg = now_subseg;
3517
3518 /* The ABI says this section should be loaded so that the
3519 running program can access it. However, we don't load it
3520 if we are configured for an embedded target */
3521 flags = SEC_READONLY | SEC_DATA;
3522 if (strncmp (TARGET_OS, "elf", 3) != 0)
3523 flags |= SEC_ALLOC | SEC_LOAD;
3524
3525 if (mips_abi != N64_ABI)
252b5132 3526 {
f3ded42a 3527 sec = subseg_new (".reginfo", (subsegT) 0);
bdaaa2e1 3528
f3ded42a
RS
3529 bfd_set_section_flags (stdoutput, sec, flags);
3530 bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2);
252b5132 3531
f3ded42a
RS
3532 mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo));
3533 }
3534 else
3535 {
3536 /* The 64-bit ABI uses a .MIPS.options section rather than
3537 .reginfo section. */
3538 sec = subseg_new (".MIPS.options", (subsegT) 0);
3539 bfd_set_section_flags (stdoutput, sec, flags);
3540 bfd_set_section_alignment (stdoutput, sec, 3);
252b5132 3541
f3ded42a
RS
3542 /* Set up the option header. */
3543 {
3544 Elf_Internal_Options opthdr;
3545 char *f;
3546
3547 opthdr.kind = ODK_REGINFO;
3548 opthdr.size = (sizeof (Elf_External_Options)
3549 + sizeof (Elf64_External_RegInfo));
3550 opthdr.section = 0;
3551 opthdr.info = 0;
3552 f = frag_more (sizeof (Elf_External_Options));
3553 bfd_mips_elf_swap_options_out (stdoutput, &opthdr,
3554 (Elf_External_Options *) f);
3555
3556 mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo));
3557 }
3558 }
252b5132 3559
f3ded42a
RS
3560 if (ECOFF_DEBUGGING)
3561 {
3562 sec = subseg_new (".mdebug", (subsegT) 0);
3563 (void) bfd_set_section_flags (stdoutput, sec,
3564 SEC_HAS_CONTENTS | SEC_READONLY);
3565 (void) bfd_set_section_alignment (stdoutput, sec, 2);
252b5132 3566 }
f3ded42a
RS
3567 else if (mips_flag_pdr)
3568 {
3569 pdr_seg = subseg_new (".pdr", (subsegT) 0);
3570 (void) bfd_set_section_flags (stdoutput, pdr_seg,
3571 SEC_READONLY | SEC_RELOC
3572 | SEC_DEBUGGING);
3573 (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2);
3574 }
3575
3576 subseg_set (seg, subseg);
3577 }
252b5132
RH
3578
3579 if (! ECOFF_DEBUGGING)
3580 md_obj_begin ();
71400594
RS
3581
3582 if (mips_fix_vr4120)
3583 init_vr4120_conflicts ();
252b5132
RH
3584}
3585
3586void
17a2f251 3587md_mips_end (void)
252b5132 3588{
02b1ab82 3589 mips_emit_delays ();
252b5132
RH
3590 if (! ECOFF_DEBUGGING)
3591 md_obj_end ();
3592}
3593
3594void
17a2f251 3595md_assemble (char *str)
252b5132
RH
3596{
3597 struct mips_cl_insn insn;
f6688943
TS
3598 bfd_reloc_code_real_type unused_reloc[3]
3599 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
252b5132
RH
3600
3601 imm_expr.X_op = O_absent;
252b5132 3602 offset_expr.X_op = O_absent;
f6688943
TS
3603 offset_reloc[0] = BFD_RELOC_UNUSED;
3604 offset_reloc[1] = BFD_RELOC_UNUSED;
3605 offset_reloc[2] = BFD_RELOC_UNUSED;
252b5132 3606
e1b47bd5
RS
3607 mips_mark_labels ();
3608 mips_assembling_insn = TRUE;
e3de51ce 3609 clear_insn_error ();
e1b47bd5 3610
252b5132
RH
3611 if (mips_opts.mips16)
3612 mips16_ip (str, &insn);
3613 else
3614 {
3615 mips_ip (str, &insn);
beae10d5
KH
3616 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
3617 str, insn.insn_opcode));
252b5132
RH
3618 }
3619
e3de51ce
RS
3620 if (insn_error.msg)
3621 report_insn_error (str);
e1b47bd5 3622 else if (insn.insn_mo->pinfo == INSN_MACRO)
252b5132 3623 {
584892a6 3624 macro_start ();
252b5132
RH
3625 if (mips_opts.mips16)
3626 mips16_macro (&insn);
3627 else
833794fc 3628 macro (&insn, str);
584892a6 3629 macro_end ();
252b5132
RH
3630 }
3631 else
3632 {
77bd4346 3633 if (offset_expr.X_op != O_absent)
df58fc94 3634 append_insn (&insn, &offset_expr, offset_reloc, FALSE);
252b5132 3635 else
df58fc94 3636 append_insn (&insn, NULL, unused_reloc, FALSE);
252b5132 3637 }
e1b47bd5
RS
3638
3639 mips_assembling_insn = FALSE;
252b5132
RH
3640}
3641
738e5348
RS
3642/* Convenience functions for abstracting away the differences between
3643 MIPS16 and non-MIPS16 relocations. */
3644
3645static inline bfd_boolean
3646mips16_reloc_p (bfd_reloc_code_real_type reloc)
3647{
3648 switch (reloc)
3649 {
3650 case BFD_RELOC_MIPS16_JMP:
3651 case BFD_RELOC_MIPS16_GPREL:
3652 case BFD_RELOC_MIPS16_GOT16:
3653 case BFD_RELOC_MIPS16_CALL16:
3654 case BFD_RELOC_MIPS16_HI16_S:
3655 case BFD_RELOC_MIPS16_HI16:
3656 case BFD_RELOC_MIPS16_LO16:
3657 return TRUE;
3658
3659 default:
3660 return FALSE;
3661 }
3662}
3663
df58fc94
RS
3664static inline bfd_boolean
3665micromips_reloc_p (bfd_reloc_code_real_type reloc)
3666{
3667 switch (reloc)
3668 {
3669 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
3670 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
3671 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
3672 case BFD_RELOC_MICROMIPS_GPREL16:
3673 case BFD_RELOC_MICROMIPS_JMP:
3674 case BFD_RELOC_MICROMIPS_HI16:
3675 case BFD_RELOC_MICROMIPS_HI16_S:
3676 case BFD_RELOC_MICROMIPS_LO16:
3677 case BFD_RELOC_MICROMIPS_LITERAL:
3678 case BFD_RELOC_MICROMIPS_GOT16:
3679 case BFD_RELOC_MICROMIPS_CALL16:
3680 case BFD_RELOC_MICROMIPS_GOT_HI16:
3681 case BFD_RELOC_MICROMIPS_GOT_LO16:
3682 case BFD_RELOC_MICROMIPS_CALL_HI16:
3683 case BFD_RELOC_MICROMIPS_CALL_LO16:
3684 case BFD_RELOC_MICROMIPS_SUB:
3685 case BFD_RELOC_MICROMIPS_GOT_PAGE:
3686 case BFD_RELOC_MICROMIPS_GOT_OFST:
3687 case BFD_RELOC_MICROMIPS_GOT_DISP:
3688 case BFD_RELOC_MICROMIPS_HIGHEST:
3689 case BFD_RELOC_MICROMIPS_HIGHER:
3690 case BFD_RELOC_MICROMIPS_SCN_DISP:
3691 case BFD_RELOC_MICROMIPS_JALR:
3692 return TRUE;
3693
3694 default:
3695 return FALSE;
3696 }
3697}
3698
2309ddf2
MR
3699static inline bfd_boolean
3700jmp_reloc_p (bfd_reloc_code_real_type reloc)
3701{
3702 return reloc == BFD_RELOC_MIPS_JMP || reloc == BFD_RELOC_MICROMIPS_JMP;
3703}
3704
738e5348
RS
3705static inline bfd_boolean
3706got16_reloc_p (bfd_reloc_code_real_type reloc)
3707{
2309ddf2 3708 return (reloc == BFD_RELOC_MIPS_GOT16 || reloc == BFD_RELOC_MIPS16_GOT16
df58fc94 3709 || reloc == BFD_RELOC_MICROMIPS_GOT16);
738e5348
RS
3710}
3711
3712static inline bfd_boolean
3713hi16_reloc_p (bfd_reloc_code_real_type reloc)
3714{
2309ddf2 3715 return (reloc == BFD_RELOC_HI16_S || reloc == BFD_RELOC_MIPS16_HI16_S
df58fc94 3716 || reloc == BFD_RELOC_MICROMIPS_HI16_S);
738e5348
RS
3717}
3718
3719static inline bfd_boolean
3720lo16_reloc_p (bfd_reloc_code_real_type reloc)
3721{
2309ddf2 3722 return (reloc == BFD_RELOC_LO16 || reloc == BFD_RELOC_MIPS16_LO16
df58fc94
RS
3723 || reloc == BFD_RELOC_MICROMIPS_LO16);
3724}
3725
df58fc94
RS
3726static inline bfd_boolean
3727jalr_reloc_p (bfd_reloc_code_real_type reloc)
3728{
2309ddf2 3729 return reloc == BFD_RELOC_MIPS_JALR || reloc == BFD_RELOC_MICROMIPS_JALR;
738e5348
RS
3730}
3731
f2ae14a1
RS
3732static inline bfd_boolean
3733gprel16_reloc_p (bfd_reloc_code_real_type reloc)
3734{
3735 return (reloc == BFD_RELOC_GPREL16 || reloc == BFD_RELOC_MIPS16_GPREL
3736 || reloc == BFD_RELOC_MICROMIPS_GPREL16);
3737}
3738
2de39019
CM
3739/* Return true if RELOC is a PC-relative relocation that does not have
3740 full address range. */
3741
3742static inline bfd_boolean
3743limited_pcrel_reloc_p (bfd_reloc_code_real_type reloc)
3744{
3745 switch (reloc)
3746 {
3747 case BFD_RELOC_16_PCREL_S2:
3748 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
3749 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
3750 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
3751 return TRUE;
3752
b47468a6
CM
3753 case BFD_RELOC_32_PCREL:
3754 return HAVE_64BIT_ADDRESSES;
3755
2de39019
CM
3756 default:
3757 return FALSE;
3758 }
3759}
b47468a6 3760
5919d012 3761/* Return true if the given relocation might need a matching %lo().
0a44bf69
RS
3762 This is only "might" because SVR4 R_MIPS_GOT16 relocations only
3763 need a matching %lo() when applied to local symbols. */
5919d012
RS
3764
3765static inline bfd_boolean
17a2f251 3766reloc_needs_lo_p (bfd_reloc_code_real_type reloc)
5919d012 3767{
3b91255e 3768 return (HAVE_IN_PLACE_ADDENDS
738e5348 3769 && (hi16_reloc_p (reloc)
0a44bf69
RS
3770 /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo();
3771 all GOT16 relocations evaluate to "G". */
738e5348
RS
3772 || (got16_reloc_p (reloc) && mips_pic != VXWORKS_PIC)));
3773}
3774
3775/* Return the type of %lo() reloc needed by RELOC, given that
3776 reloc_needs_lo_p. */
3777
3778static inline bfd_reloc_code_real_type
3779matching_lo_reloc (bfd_reloc_code_real_type reloc)
3780{
df58fc94
RS
3781 return (mips16_reloc_p (reloc) ? BFD_RELOC_MIPS16_LO16
3782 : (micromips_reloc_p (reloc) ? BFD_RELOC_MICROMIPS_LO16
3783 : BFD_RELOC_LO16));
5919d012
RS
3784}
3785
3786/* Return true if the given fixup is followed by a matching R_MIPS_LO16
3787 relocation. */
3788
3789static inline bfd_boolean
17a2f251 3790fixup_has_matching_lo_p (fixS *fixp)
5919d012
RS
3791{
3792 return (fixp->fx_next != NULL
738e5348 3793 && fixp->fx_next->fx_r_type == matching_lo_reloc (fixp->fx_r_type)
5919d012
RS
3794 && fixp->fx_addsy == fixp->fx_next->fx_addsy
3795 && fixp->fx_offset == fixp->fx_next->fx_offset);
3796}
3797
462427c4
RS
3798/* Move all labels in LABELS to the current insertion point. TEXT_P
3799 says whether the labels refer to text or data. */
404a8071
RS
3800
3801static void
462427c4 3802mips_move_labels (struct insn_label_list *labels, bfd_boolean text_p)
404a8071
RS
3803{
3804 struct insn_label_list *l;
3805 valueT val;
3806
462427c4 3807 for (l = labels; l != NULL; l = l->next)
404a8071 3808 {
9c2799c2 3809 gas_assert (S_GET_SEGMENT (l->label) == now_seg);
404a8071
RS
3810 symbol_set_frag (l->label, frag_now);
3811 val = (valueT) frag_now_fix ();
df58fc94 3812 /* MIPS16/microMIPS text labels are stored as odd. */
462427c4 3813 if (text_p && HAVE_CODE_COMPRESSION)
404a8071
RS
3814 ++val;
3815 S_SET_VALUE (l->label, val);
3816 }
3817}
3818
462427c4
RS
3819/* Move all labels in insn_labels to the current insertion point
3820 and treat them as text labels. */
3821
3822static void
3823mips_move_text_labels (void)
3824{
3825 mips_move_labels (seg_info (now_seg)->label_list, TRUE);
3826}
3827
5f0fe04b
TS
3828static bfd_boolean
3829s_is_linkonce (symbolS *sym, segT from_seg)
3830{
3831 bfd_boolean linkonce = FALSE;
3832 segT symseg = S_GET_SEGMENT (sym);
3833
3834 if (symseg != from_seg && !S_IS_LOCAL (sym))
3835 {
3836 if ((bfd_get_section_flags (stdoutput, symseg) & SEC_LINK_ONCE))
3837 linkonce = TRUE;
5f0fe04b
TS
3838 /* The GNU toolchain uses an extension for ELF: a section
3839 beginning with the magic string .gnu.linkonce is a
3840 linkonce section. */
3841 if (strncmp (segment_name (symseg), ".gnu.linkonce",
3842 sizeof ".gnu.linkonce" - 1) == 0)
3843 linkonce = TRUE;
5f0fe04b
TS
3844 }
3845 return linkonce;
3846}
3847
e1b47bd5 3848/* Mark MIPS16 or microMIPS instruction label LABEL. This permits the
df58fc94
RS
3849 linker to handle them specially, such as generating jalx instructions
3850 when needed. We also make them odd for the duration of the assembly,
3851 in order to generate the right sort of code. We will make them even
252b5132
RH
3852 in the adjust_symtab routine, while leaving them marked. This is
3853 convenient for the debugger and the disassembler. The linker knows
3854 to make them odd again. */
3855
3856static void
e1b47bd5 3857mips_compressed_mark_label (symbolS *label)
252b5132 3858{
df58fc94 3859 gas_assert (HAVE_CODE_COMPRESSION);
a8dbcb85 3860
f3ded42a
RS
3861 if (mips_opts.mips16)
3862 S_SET_OTHER (label, ELF_ST_SET_MIPS16 (S_GET_OTHER (label)));
3863 else
3864 S_SET_OTHER (label, ELF_ST_SET_MICROMIPS (S_GET_OTHER (label)));
e1b47bd5
RS
3865 if ((S_GET_VALUE (label) & 1) == 0
3866 /* Don't adjust the address if the label is global or weak, or
3867 in a link-once section, since we'll be emitting symbol reloc
3868 references to it which will be patched up by the linker, and
3869 the final value of the symbol may or may not be MIPS16/microMIPS. */
3870 && !S_IS_WEAK (label)
3871 && !S_IS_EXTERNAL (label)
3872 && !s_is_linkonce (label, now_seg))
3873 S_SET_VALUE (label, S_GET_VALUE (label) | 1);
3874}
3875
3876/* Mark preceding MIPS16 or microMIPS instruction labels. */
3877
3878static void
3879mips_compressed_mark_labels (void)
3880{
3881 struct insn_label_list *l;
3882
3883 for (l = seg_info (now_seg)->label_list; l != NULL; l = l->next)
3884 mips_compressed_mark_label (l->label);
252b5132
RH
3885}
3886
4d7206a2
RS
3887/* End the current frag. Make it a variant frag and record the
3888 relaxation info. */
3889
3890static void
3891relax_close_frag (void)
3892{
584892a6 3893 mips_macro_warning.first_frag = frag_now;
4d7206a2 3894 frag_var (rs_machine_dependent, 0, 0,
584892a6 3895 RELAX_ENCODE (mips_relax.sizes[0], mips_relax.sizes[1]),
4d7206a2
RS
3896 mips_relax.symbol, 0, (char *) mips_relax.first_fixup);
3897
3898 memset (&mips_relax.sizes, 0, sizeof (mips_relax.sizes));
3899 mips_relax.first_fixup = 0;
3900}
3901
3902/* Start a new relaxation sequence whose expansion depends on SYMBOL.
3903 See the comment above RELAX_ENCODE for more details. */
3904
3905static void
3906relax_start (symbolS *symbol)
3907{
9c2799c2 3908 gas_assert (mips_relax.sequence == 0);
4d7206a2
RS
3909 mips_relax.sequence = 1;
3910 mips_relax.symbol = symbol;
3911}
3912
3913/* Start generating the second version of a relaxable sequence.
3914 See the comment above RELAX_ENCODE for more details. */
252b5132
RH
3915
3916static void
4d7206a2
RS
3917relax_switch (void)
3918{
9c2799c2 3919 gas_assert (mips_relax.sequence == 1);
4d7206a2
RS
3920 mips_relax.sequence = 2;
3921}
3922
3923/* End the current relaxable sequence. */
3924
3925static void
3926relax_end (void)
3927{
9c2799c2 3928 gas_assert (mips_relax.sequence == 2);
4d7206a2
RS
3929 relax_close_frag ();
3930 mips_relax.sequence = 0;
3931}
3932
11625dd8
RS
3933/* Return true if IP is a delayed branch or jump. */
3934
3935static inline bfd_boolean
3936delayed_branch_p (const struct mips_cl_insn *ip)
3937{
3938 return (ip->insn_mo->pinfo & (INSN_UNCOND_BRANCH_DELAY
3939 | INSN_COND_BRANCH_DELAY
3940 | INSN_COND_BRANCH_LIKELY)) != 0;
3941}
3942
3943/* Return true if IP is a compact branch or jump. */
3944
3945static inline bfd_boolean
3946compact_branch_p (const struct mips_cl_insn *ip)
3947{
26545944
RS
3948 return (ip->insn_mo->pinfo2 & (INSN2_UNCOND_BRANCH
3949 | INSN2_COND_BRANCH)) != 0;
11625dd8
RS
3950}
3951
3952/* Return true if IP is an unconditional branch or jump. */
3953
3954static inline bfd_boolean
3955uncond_branch_p (const struct mips_cl_insn *ip)
3956{
3957 return ((ip->insn_mo->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0
26545944 3958 || (ip->insn_mo->pinfo2 & INSN2_UNCOND_BRANCH) != 0);
11625dd8
RS
3959}
3960
3961/* Return true if IP is a branch-likely instruction. */
3962
3963static inline bfd_boolean
3964branch_likely_p (const struct mips_cl_insn *ip)
3965{
3966 return (ip->insn_mo->pinfo & INSN_COND_BRANCH_LIKELY) != 0;
3967}
3968
14fe068b
RS
3969/* Return the type of nop that should be used to fill the delay slot
3970 of delayed branch IP. */
3971
3972static struct mips_cl_insn *
3973get_delay_slot_nop (const struct mips_cl_insn *ip)
3974{
3975 if (mips_opts.micromips
3976 && (ip->insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
3977 return &micromips_nop32_insn;
3978 return NOP_INSN;
3979}
3980
fc76e730
RS
3981/* Return a mask that has bit N set if OPCODE reads the register(s)
3982 in operand N. */
df58fc94
RS
3983
3984static unsigned int
fc76e730 3985insn_read_mask (const struct mips_opcode *opcode)
df58fc94 3986{
fc76e730
RS
3987 return (opcode->pinfo & INSN_READ_ALL) >> INSN_READ_SHIFT;
3988}
df58fc94 3989
fc76e730
RS
3990/* Return a mask that has bit N set if OPCODE writes to the register(s)
3991 in operand N. */
3992
3993static unsigned int
3994insn_write_mask (const struct mips_opcode *opcode)
3995{
3996 return (opcode->pinfo & INSN_WRITE_ALL) >> INSN_WRITE_SHIFT;
3997}
3998
3999/* Return a mask of the registers specified by operand OPERAND of INSN.
4000 Ignore registers of type OP_REG_<t> unless bit OP_REG_<t> of TYPE_MASK
4001 is set. */
4002
4003static unsigned int
4004operand_reg_mask (const struct mips_cl_insn *insn,
4005 const struct mips_operand *operand,
4006 unsigned int type_mask)
4007{
4008 unsigned int uval, vsel;
4009
4010 switch (operand->type)
df58fc94 4011 {
fc76e730
RS
4012 case OP_INT:
4013 case OP_MAPPED_INT:
4014 case OP_MSB:
4015 case OP_PCREL:
4016 case OP_PERF_REG:
4017 case OP_ADDIUSP_INT:
4018 case OP_ENTRY_EXIT_LIST:
4019 case OP_REPEAT_DEST_REG:
4020 case OP_REPEAT_PREV_REG:
4021 case OP_PC:
14daeee3
RS
4022 case OP_VU0_SUFFIX:
4023 case OP_VU0_MATCH_SUFFIX:
56d438b1 4024 case OP_IMM_INDEX:
fc76e730
RS
4025 abort ();
4026
4027 case OP_REG:
0f35dbc4 4028 case OP_OPTIONAL_REG:
fc76e730
RS
4029 {
4030 const struct mips_reg_operand *reg_op;
4031
4032 reg_op = (const struct mips_reg_operand *) operand;
4033 if (!(type_mask & (1 << reg_op->reg_type)))
4034 return 0;
4035 uval = insn_extract_operand (insn, operand);
4036 return 1 << mips_decode_reg_operand (reg_op, uval);
4037 }
4038
4039 case OP_REG_PAIR:
4040 {
4041 const struct mips_reg_pair_operand *pair_op;
4042
4043 pair_op = (const struct mips_reg_pair_operand *) operand;
4044 if (!(type_mask & (1 << pair_op->reg_type)))
4045 return 0;
4046 uval = insn_extract_operand (insn, operand);
4047 return (1 << pair_op->reg1_map[uval]) | (1 << pair_op->reg2_map[uval]);
4048 }
4049
4050 case OP_CLO_CLZ_DEST:
4051 if (!(type_mask & (1 << OP_REG_GP)))
4052 return 0;
4053 uval = insn_extract_operand (insn, operand);
4054 return (1 << (uval & 31)) | (1 << (uval >> 5));
4055
4056 case OP_LWM_SWM_LIST:
4057 abort ();
4058
4059 case OP_SAVE_RESTORE_LIST:
4060 abort ();
4061
4062 case OP_MDMX_IMM_REG:
4063 if (!(type_mask & (1 << OP_REG_VEC)))
4064 return 0;
4065 uval = insn_extract_operand (insn, operand);
4066 vsel = uval >> 5;
4067 if ((vsel & 0x18) == 0x18)
4068 return 0;
4069 return 1 << (uval & 31);
56d438b1
CF
4070
4071 case OP_REG_INDEX:
4072 if (!(type_mask & (1 << OP_REG_GP)))
4073 return 0;
4074 return 1 << insn_extract_operand (insn, operand);
df58fc94 4075 }
fc76e730
RS
4076 abort ();
4077}
4078
4079/* Return a mask of the registers specified by operands OPNO_MASK of INSN,
4080 where bit N of OPNO_MASK is set if operand N should be included.
4081 Ignore registers of type OP_REG_<t> unless bit OP_REG_<t> of TYPE_MASK
4082 is set. */
4083
4084static unsigned int
4085insn_reg_mask (const struct mips_cl_insn *insn,
4086 unsigned int type_mask, unsigned int opno_mask)
4087{
4088 unsigned int opno, reg_mask;
4089
4090 opno = 0;
4091 reg_mask = 0;
4092 while (opno_mask != 0)
4093 {
4094 if (opno_mask & 1)
4095 reg_mask |= operand_reg_mask (insn, insn_opno (insn, opno), type_mask);
4096 opno_mask >>= 1;
4097 opno += 1;
4098 }
4099 return reg_mask;
df58fc94
RS
4100}
4101
4c260379
RS
4102/* Return the mask of core registers that IP reads. */
4103
4104static unsigned int
4105gpr_read_mask (const struct mips_cl_insn *ip)
4106{
4107 unsigned long pinfo, pinfo2;
4108 unsigned int mask;
4109
fc76e730 4110 mask = insn_reg_mask (ip, 1 << OP_REG_GP, insn_read_mask (ip->insn_mo));
4c260379
RS
4111 pinfo = ip->insn_mo->pinfo;
4112 pinfo2 = ip->insn_mo->pinfo2;
fc76e730 4113 if (pinfo & INSN_UDI)
4c260379 4114 {
fc76e730
RS
4115 /* UDI instructions have traditionally been assumed to read RS
4116 and RT. */
4117 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RT, *ip);
4118 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RS, *ip);
4c260379 4119 }
fc76e730
RS
4120 if (pinfo & INSN_READ_GPR_24)
4121 mask |= 1 << 24;
4122 if (pinfo2 & INSN2_READ_GPR_16)
4123 mask |= 1 << 16;
4124 if (pinfo2 & INSN2_READ_SP)
4125 mask |= 1 << SP;
26545944 4126 if (pinfo2 & INSN2_READ_GPR_31)
fc76e730 4127 mask |= 1 << 31;
fe35f09f
RS
4128 /* Don't include register 0. */
4129 return mask & ~1;
4c260379
RS
4130}
4131
4132/* Return the mask of core registers that IP writes. */
4133
4134static unsigned int
4135gpr_write_mask (const struct mips_cl_insn *ip)
4136{
4137 unsigned long pinfo, pinfo2;
4138 unsigned int mask;
4139
fc76e730 4140 mask = insn_reg_mask (ip, 1 << OP_REG_GP, insn_write_mask (ip->insn_mo));
4c260379
RS
4141 pinfo = ip->insn_mo->pinfo;
4142 pinfo2 = ip->insn_mo->pinfo2;
fc76e730
RS
4143 if (pinfo & INSN_WRITE_GPR_24)
4144 mask |= 1 << 24;
4145 if (pinfo & INSN_WRITE_GPR_31)
4146 mask |= 1 << 31;
4147 if (pinfo & INSN_UDI)
4148 /* UDI instructions have traditionally been assumed to write to RD. */
4149 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RD, *ip);
4150 if (pinfo2 & INSN2_WRITE_SP)
4151 mask |= 1 << SP;
fe35f09f
RS
4152 /* Don't include register 0. */
4153 return mask & ~1;
4c260379
RS
4154}
4155
4156/* Return the mask of floating-point registers that IP reads. */
4157
4158static unsigned int
4159fpr_read_mask (const struct mips_cl_insn *ip)
4160{
fc76e730 4161 unsigned long pinfo;
4c260379
RS
4162 unsigned int mask;
4163
fc76e730
RS
4164 mask = insn_reg_mask (ip, (1 << OP_REG_FP) | (1 << OP_REG_VEC),
4165 insn_read_mask (ip->insn_mo));
4c260379 4166 pinfo = ip->insn_mo->pinfo;
4c260379
RS
4167 /* Conservatively treat all operands to an FP_D instruction are doubles.
4168 (This is overly pessimistic for things like cvt.d.s.) */
4169 if (HAVE_32BIT_FPRS && (pinfo & FP_D))
4170 mask |= mask << 1;
4171 return mask;
4172}
4173
4174/* Return the mask of floating-point registers that IP writes. */
4175
4176static unsigned int
4177fpr_write_mask (const struct mips_cl_insn *ip)
4178{
fc76e730 4179 unsigned long pinfo;
4c260379
RS
4180 unsigned int mask;
4181
fc76e730
RS
4182 mask = insn_reg_mask (ip, (1 << OP_REG_FP) | (1 << OP_REG_VEC),
4183 insn_write_mask (ip->insn_mo));
4c260379 4184 pinfo = ip->insn_mo->pinfo;
4c260379
RS
4185 /* Conservatively treat all operands to an FP_D instruction are doubles.
4186 (This is overly pessimistic for things like cvt.s.d.) */
4187 if (HAVE_32BIT_FPRS && (pinfo & FP_D))
4188 mask |= mask << 1;
4189 return mask;
4190}
4191
a1d78564
RS
4192/* Operand OPNUM of INSN is an odd-numbered floating-point register.
4193 Check whether that is allowed. */
4194
4195static bfd_boolean
4196mips_oddfpreg_ok (const struct mips_opcode *insn, int opnum)
4197{
4198 const char *s = insn->name;
4199
4200 if (insn->pinfo == INSN_MACRO)
4201 /* Let a macro pass, we'll catch it later when it is expanded. */
4202 return TRUE;
4203
4204 if (ISA_HAS_ODD_SINGLE_FPR (mips_opts.isa) || mips_opts.arch == CPU_R5900)
4205 {
4206 /* Allow odd registers for single-precision ops. */
4207 switch (insn->pinfo & (FP_S | FP_D))
4208 {
4209 case FP_S:
4210 case 0:
4211 return TRUE;
4212 case FP_D:
4213 return FALSE;
4214 default:
4215 break;
4216 }
4217
4218 /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */
4219 s = strchr (insn->name, '.');
4220 if (s != NULL && opnum == 2)
4221 s = strchr (s + 1, '.');
4222 return (s != NULL && (s[1] == 'w' || s[1] == 's'));
4223 }
4224
4225 /* Single-precision coprocessor loads and moves are OK too. */
4226 if ((insn->pinfo & FP_S)
4227 && (insn->pinfo & (INSN_COPROC_MEMORY_DELAY | INSN_STORE_MEMORY
4228 | INSN_LOAD_COPROC_DELAY | INSN_COPROC_MOVE_DELAY)))
4229 return TRUE;
4230
4231 return FALSE;
4232}
4233
a1d78564
RS
4234/* Information about an instruction argument that we're trying to match. */
4235struct mips_arg_info
4236{
4237 /* The instruction so far. */
4238 struct mips_cl_insn *insn;
4239
a92713e6
RS
4240 /* The first unconsumed operand token. */
4241 struct mips_operand_token *token;
4242
a1d78564
RS
4243 /* The 1-based operand number, in terms of insn->insn_mo->args. */
4244 int opnum;
4245
4246 /* The 1-based argument number, for error reporting. This does not
4247 count elided optional registers, etc.. */
4248 int argnum;
4249
4250 /* The last OP_REG operand seen, or ILLEGAL_REG if none. */
4251 unsigned int last_regno;
4252
4253 /* If the first operand was an OP_REG, this is the register that it
4254 specified, otherwise it is ILLEGAL_REG. */
4255 unsigned int dest_regno;
4256
4257 /* The value of the last OP_INT operand. Only used for OP_MSB,
4258 where it gives the lsb position. */
4259 unsigned int last_op_int;
4260
60f20e8b
RS
4261 /* If true, match routines should assume that no later instruction
4262 alternative matches and should therefore be as accomodating as
4263 possible. Match routines should not report errors if something
4264 is only invalid for !LAX_MATCH. */
4265 bfd_boolean lax_match;
a1d78564 4266
a1d78564
RS
4267 /* True if a reference to the current AT register was seen. */
4268 bfd_boolean seen_at;
4269};
4270
1a00e612
RS
4271/* Record that the argument is out of range. */
4272
4273static void
4274match_out_of_range (struct mips_arg_info *arg)
4275{
4276 set_insn_error_i (arg->argnum, _("operand %d out of range"), arg->argnum);
4277}
4278
4279/* Record that the argument isn't constant but needs to be. */
4280
4281static void
4282match_not_constant (struct mips_arg_info *arg)
4283{
4284 set_insn_error_i (arg->argnum, _("operand %d must be constant"),
4285 arg->argnum);
4286}
4287
a92713e6
RS
4288/* Try to match an OT_CHAR token for character CH. Consume the token
4289 and return true on success, otherwise return false. */
a1d78564 4290
a92713e6
RS
4291static bfd_boolean
4292match_char (struct mips_arg_info *arg, char ch)
a1d78564 4293{
a92713e6
RS
4294 if (arg->token->type == OT_CHAR && arg->token->u.ch == ch)
4295 {
4296 ++arg->token;
4297 if (ch == ',')
4298 arg->argnum += 1;
4299 return TRUE;
4300 }
4301 return FALSE;
4302}
a1d78564 4303
a92713e6
RS
4304/* Try to get an expression from the next tokens in ARG. Consume the
4305 tokens and return true on success, storing the expression value in
4306 VALUE and relocation types in R. */
4307
4308static bfd_boolean
4309match_expression (struct mips_arg_info *arg, expressionS *value,
4310 bfd_reloc_code_real_type *r)
4311{
d436c1c2
RS
4312 /* If the next token is a '(' that was parsed as being part of a base
4313 expression, assume we have an elided offset. The later match will fail
4314 if this turns out to be wrong. */
4315 if (arg->token->type == OT_CHAR && arg->token->u.ch == '(')
a1d78564 4316 {
d436c1c2
RS
4317 value->X_op = O_constant;
4318 value->X_add_number = 0;
4319 r[0] = r[1] = r[2] = BFD_RELOC_UNUSED;
a92713e6
RS
4320 return TRUE;
4321 }
4322
d436c1c2
RS
4323 /* Reject register-based expressions such as "0+$2" and "(($2))".
4324 For plain registers the default error seems more appropriate. */
4325 if (arg->token->type == OT_INTEGER
4326 && arg->token->u.integer.value.X_op == O_register)
a92713e6 4327 {
d436c1c2
RS
4328 set_insn_error (arg->argnum, _("register value used as expression"));
4329 return FALSE;
a1d78564 4330 }
d436c1c2
RS
4331
4332 if (arg->token->type == OT_INTEGER)
a92713e6 4333 {
d436c1c2
RS
4334 *value = arg->token->u.integer.value;
4335 memcpy (r, arg->token->u.integer.relocs, 3 * sizeof (*r));
4336 ++arg->token;
4337 return TRUE;
a92713e6 4338 }
a92713e6 4339
d436c1c2
RS
4340 set_insn_error_i
4341 (arg->argnum, _("operand %d must be an immediate expression"),
4342 arg->argnum);
4343 return FALSE;
a92713e6
RS
4344}
4345
4346/* Try to get a constant expression from the next tokens in ARG. Consume
4347 the tokens and return return true on success, storing the constant value
4348 in *VALUE. Use FALLBACK as the value if the match succeeded with an
4349 error. */
4350
4351static bfd_boolean
1a00e612 4352match_const_int (struct mips_arg_info *arg, offsetT *value)
a92713e6
RS
4353{
4354 expressionS ex;
4355 bfd_reloc_code_real_type r[3];
a1d78564 4356
a92713e6
RS
4357 if (!match_expression (arg, &ex, r))
4358 return FALSE;
4359
4360 if (r[0] == BFD_RELOC_UNUSED && ex.X_op == O_constant)
a1d78564
RS
4361 *value = ex.X_add_number;
4362 else
4363 {
1a00e612
RS
4364 match_not_constant (arg);
4365 return FALSE;
a1d78564 4366 }
a92713e6 4367 return TRUE;
a1d78564
RS
4368}
4369
4370/* Return the RTYPE_* flags for a register operand of type TYPE that
4371 appears in instruction OPCODE. */
4372
4373static unsigned int
4374convert_reg_type (const struct mips_opcode *opcode,
4375 enum mips_reg_operand_type type)
4376{
4377 switch (type)
4378 {
4379 case OP_REG_GP:
4380 return RTYPE_NUM | RTYPE_GP;
4381
4382 case OP_REG_FP:
4383 /* Allow vector register names for MDMX if the instruction is a 64-bit
4384 FPR load, store or move (including moves to and from GPRs). */
4385 if ((mips_opts.ase & ASE_MDMX)
4386 && (opcode->pinfo & FP_D)
4387 && (opcode->pinfo & (INSN_COPROC_MOVE_DELAY
4388 | INSN_COPROC_MEMORY_DELAY
4389 | INSN_LOAD_COPROC_DELAY
4390 | INSN_LOAD_MEMORY_DELAY
4391 | INSN_STORE_MEMORY)))
4392 return RTYPE_FPU | RTYPE_VEC;
4393 return RTYPE_FPU;
4394
4395 case OP_REG_CCC:
4396 if (opcode->pinfo & (FP_D | FP_S))
4397 return RTYPE_CCC | RTYPE_FCC;
4398 return RTYPE_CCC;
4399
4400 case OP_REG_VEC:
4401 if (opcode->membership & INSN_5400)
4402 return RTYPE_FPU;
4403 return RTYPE_FPU | RTYPE_VEC;
4404
4405 case OP_REG_ACC:
4406 return RTYPE_ACC;
4407
4408 case OP_REG_COPRO:
4409 if (opcode->name[strlen (opcode->name) - 1] == '0')
4410 return RTYPE_NUM | RTYPE_CP0;
4411 return RTYPE_NUM;
4412
4413 case OP_REG_HW:
4414 return RTYPE_NUM;
14daeee3
RS
4415
4416 case OP_REG_VI:
4417 return RTYPE_NUM | RTYPE_VI;
4418
4419 case OP_REG_VF:
4420 return RTYPE_NUM | RTYPE_VF;
4421
4422 case OP_REG_R5900_I:
4423 return RTYPE_R5900_I;
4424
4425 case OP_REG_R5900_Q:
4426 return RTYPE_R5900_Q;
4427
4428 case OP_REG_R5900_R:
4429 return RTYPE_R5900_R;
4430
4431 case OP_REG_R5900_ACC:
4432 return RTYPE_R5900_ACC;
56d438b1
CF
4433
4434 case OP_REG_MSA:
4435 return RTYPE_MSA;
4436
4437 case OP_REG_MSA_CTRL:
4438 return RTYPE_NUM;
a1d78564
RS
4439 }
4440 abort ();
4441}
4442
4443/* ARG is register REGNO, of type TYPE. Warn about any dubious registers. */
4444
4445static void
4446check_regno (struct mips_arg_info *arg,
4447 enum mips_reg_operand_type type, unsigned int regno)
4448{
4449 if (AT && type == OP_REG_GP && regno == AT)
4450 arg->seen_at = TRUE;
4451
4452 if (type == OP_REG_FP
4453 && (regno & 1) != 0
4454 && HAVE_32BIT_FPRS
4455 && !mips_oddfpreg_ok (arg->insn->insn_mo, arg->opnum))
1661c76c 4456 as_warn (_("float register should be even, was %d"), regno);
a1d78564
RS
4457
4458 if (type == OP_REG_CCC)
4459 {
4460 const char *name;
4461 size_t length;
4462
4463 name = arg->insn->insn_mo->name;
4464 length = strlen (name);
4465 if ((regno & 1) != 0
4466 && ((length >= 3 && strcmp (name + length - 3, ".ps") == 0)
4467 || (length >= 5 && strncmp (name + length - 5, "any2", 4) == 0)))
1661c76c 4468 as_warn (_("condition code register should be even for %s, was %d"),
a1d78564
RS
4469 name, regno);
4470
4471 if ((regno & 3) != 0
4472 && (length >= 5 && strncmp (name + length - 5, "any4", 4) == 0))
1661c76c 4473 as_warn (_("condition code register should be 0 or 4 for %s, was %d"),
a1d78564
RS
4474 name, regno);
4475 }
4476}
4477
a92713e6
RS
4478/* ARG is a register with symbol value SYMVAL. Try to interpret it as
4479 a register of type TYPE. Return true on success, storing the register
4480 number in *REGNO and warning about any dubious uses. */
4481
4482static bfd_boolean
4483match_regno (struct mips_arg_info *arg, enum mips_reg_operand_type type,
4484 unsigned int symval, unsigned int *regno)
4485{
4486 if (type == OP_REG_VEC)
4487 symval = mips_prefer_vec_regno (symval);
4488 if (!(symval & convert_reg_type (arg->insn->insn_mo, type)))
4489 return FALSE;
4490
4491 *regno = symval & RNUM_MASK;
4492 check_regno (arg, type, *regno);
4493 return TRUE;
4494}
4495
4496/* Try to interpret the next token in ARG as a register of type TYPE.
4497 Consume the token and return true on success, storing the register
4498 number in *REGNO. Return false on failure. */
4499
4500static bfd_boolean
4501match_reg (struct mips_arg_info *arg, enum mips_reg_operand_type type,
4502 unsigned int *regno)
4503{
4504 if (arg->token->type == OT_REG
4505 && match_regno (arg, type, arg->token->u.regno, regno))
4506 {
4507 ++arg->token;
4508 return TRUE;
4509 }
4510 return FALSE;
4511}
4512
4513/* Try to interpret the next token in ARG as a range of registers of type TYPE.
4514 Consume the token and return true on success, storing the register numbers
4515 in *REGNO1 and *REGNO2. Return false on failure. */
4516
4517static bfd_boolean
4518match_reg_range (struct mips_arg_info *arg, enum mips_reg_operand_type type,
4519 unsigned int *regno1, unsigned int *regno2)
4520{
4521 if (match_reg (arg, type, regno1))
4522 {
4523 *regno2 = *regno1;
4524 return TRUE;
4525 }
4526 if (arg->token->type == OT_REG_RANGE
4527 && match_regno (arg, type, arg->token->u.reg_range.regno1, regno1)
4528 && match_regno (arg, type, arg->token->u.reg_range.regno2, regno2)
4529 && *regno1 <= *regno2)
4530 {
4531 ++arg->token;
4532 return TRUE;
4533 }
4534 return FALSE;
4535}
4536
a1d78564
RS
4537/* OP_INT matcher. */
4538
a92713e6 4539static bfd_boolean
a1d78564 4540match_int_operand (struct mips_arg_info *arg,
a92713e6 4541 const struct mips_operand *operand_base)
a1d78564
RS
4542{
4543 const struct mips_int_operand *operand;
3ccad066 4544 unsigned int uval;
a1d78564
RS
4545 int min_val, max_val, factor;
4546 offsetT sval;
a1d78564
RS
4547
4548 operand = (const struct mips_int_operand *) operand_base;
4549 factor = 1 << operand->shift;
3ccad066
RS
4550 min_val = mips_int_operand_min (operand);
4551 max_val = mips_int_operand_max (operand);
a1d78564 4552
d436c1c2
RS
4553 if (operand_base->lsb == 0
4554 && operand_base->size == 16
4555 && operand->shift == 0
4556 && operand->bias == 0
4557 && (operand->max_val == 32767 || operand->max_val == 65535))
a1d78564
RS
4558 {
4559 /* The operand can be relocated. */
a92713e6
RS
4560 if (!match_expression (arg, &offset_expr, offset_reloc))
4561 return FALSE;
4562
4563 if (offset_reloc[0] != BFD_RELOC_UNUSED)
a1d78564
RS
4564 /* Relocation operators were used. Accept the arguent and
4565 leave the relocation value in offset_expr and offset_relocs
4566 for the caller to process. */
a92713e6
RS
4567 return TRUE;
4568
4569 if (offset_expr.X_op != O_constant)
a1d78564 4570 {
60f20e8b
RS
4571 /* Accept non-constant operands if no later alternative matches,
4572 leaving it for the caller to process. */
4573 if (!arg->lax_match)
4574 return FALSE;
a92713e6
RS
4575 offset_reloc[0] = BFD_RELOC_LO16;
4576 return TRUE;
a1d78564 4577 }
a92713e6 4578
a1d78564
RS
4579 /* Clear the global state; we're going to install the operand
4580 ourselves. */
a92713e6 4581 sval = offset_expr.X_add_number;
a1d78564 4582 offset_expr.X_op = O_absent;
60f20e8b
RS
4583
4584 /* For compatibility with older assemblers, we accept
4585 0x8000-0xffff as signed 16-bit numbers when only
4586 signed numbers are allowed. */
4587 if (sval > max_val)
4588 {
4589 max_val = ((1 << operand_base->size) - 1) << operand->shift;
4590 if (!arg->lax_match && sval <= max_val)
4591 return FALSE;
4592 }
a1d78564
RS
4593 }
4594 else
4595 {
1a00e612 4596 if (!match_const_int (arg, &sval))
a92713e6 4597 return FALSE;
a1d78564
RS
4598 }
4599
4600 arg->last_op_int = sval;
4601
1a00e612 4602 if (sval < min_val || sval > max_val || sval % factor)
a1d78564 4603 {
1a00e612
RS
4604 match_out_of_range (arg);
4605 return FALSE;
a1d78564
RS
4606 }
4607
4608 uval = (unsigned int) sval >> operand->shift;
4609 uval -= operand->bias;
4610
4611 /* Handle -mfix-cn63xxp1. */
4612 if (arg->opnum == 1
4613 && mips_fix_cn63xxp1
4614 && !mips_opts.micromips
4615 && strcmp ("pref", arg->insn->insn_mo->name) == 0)
4616 switch (uval)
4617 {
4618 case 5:
4619 case 25:
4620 case 26:
4621 case 27:
4622 case 28:
4623 case 29:
4624 case 30:
4625 case 31:
4626 /* These are ok. */
4627 break;
4628
4629 default:
4630 /* The rest must be changed to 28. */
4631 uval = 28;
4632 break;
4633 }
4634
4635 insn_insert_operand (arg->insn, operand_base, uval);
a92713e6 4636 return TRUE;
a1d78564
RS
4637}
4638
4639/* OP_MAPPED_INT matcher. */
4640
a92713e6 4641static bfd_boolean
a1d78564 4642match_mapped_int_operand (struct mips_arg_info *arg,
a92713e6 4643 const struct mips_operand *operand_base)
a1d78564
RS
4644{
4645 const struct mips_mapped_int_operand *operand;
4646 unsigned int uval, num_vals;
4647 offsetT sval;
4648
4649 operand = (const struct mips_mapped_int_operand *) operand_base;
1a00e612 4650 if (!match_const_int (arg, &sval))
a92713e6 4651 return FALSE;
a1d78564
RS
4652
4653 num_vals = 1 << operand_base->size;
4654 for (uval = 0; uval < num_vals; uval++)
4655 if (operand->int_map[uval] == sval)
4656 break;
4657 if (uval == num_vals)
1a00e612
RS
4658 {
4659 match_out_of_range (arg);
4660 return FALSE;
4661 }
a1d78564
RS
4662
4663 insn_insert_operand (arg->insn, operand_base, uval);
a92713e6 4664 return TRUE;
a1d78564
RS
4665}
4666
4667/* OP_MSB matcher. */
4668
a92713e6 4669static bfd_boolean
a1d78564 4670match_msb_operand (struct mips_arg_info *arg,
a92713e6 4671 const struct mips_operand *operand_base)
a1d78564
RS
4672{
4673 const struct mips_msb_operand *operand;
4674 int min_val, max_val, max_high;
4675 offsetT size, sval, high;
4676
4677 operand = (const struct mips_msb_operand *) operand_base;
4678 min_val = operand->bias;
4679 max_val = min_val + (1 << operand_base->size) - 1;
4680 max_high = operand->opsize;
4681
1a00e612 4682 if (!match_const_int (arg, &size))
a92713e6 4683 return FALSE;
a1d78564
RS
4684
4685 high = size + arg->last_op_int;
4686 sval = operand->add_lsb ? high : size;
4687
4688 if (size < 0 || high > max_high || sval < min_val || sval > max_val)
4689 {
1a00e612
RS
4690 match_out_of_range (arg);
4691 return FALSE;
a1d78564
RS
4692 }
4693 insn_insert_operand (arg->insn, operand_base, sval - min_val);
a92713e6 4694 return TRUE;
a1d78564
RS
4695}
4696
4697/* OP_REG matcher. */
4698
a92713e6 4699static bfd_boolean
a1d78564 4700match_reg_operand (struct mips_arg_info *arg,
a92713e6 4701 const struct mips_operand *operand_base)
a1d78564
RS
4702{
4703 const struct mips_reg_operand *operand;
a92713e6 4704 unsigned int regno, uval, num_vals;
a1d78564
RS
4705
4706 operand = (const struct mips_reg_operand *) operand_base;
a92713e6
RS
4707 if (!match_reg (arg, operand->reg_type, &regno))
4708 return FALSE;
a1d78564
RS
4709
4710 if (operand->reg_map)
4711 {
4712 num_vals = 1 << operand->root.size;
4713 for (uval = 0; uval < num_vals; uval++)
4714 if (operand->reg_map[uval] == regno)
4715 break;
4716 if (num_vals == uval)
a92713e6 4717 return FALSE;
a1d78564
RS
4718 }
4719 else
4720 uval = regno;
4721
a1d78564
RS
4722 arg->last_regno = regno;
4723 if (arg->opnum == 1)
4724 arg->dest_regno = regno;
4725 insn_insert_operand (arg->insn, operand_base, uval);
a92713e6 4726 return TRUE;
a1d78564
RS
4727}
4728
4729/* OP_REG_PAIR matcher. */
4730
a92713e6 4731static bfd_boolean
a1d78564 4732match_reg_pair_operand (struct mips_arg_info *arg,
a92713e6 4733 const struct mips_operand *operand_base)
a1d78564
RS
4734{
4735 const struct mips_reg_pair_operand *operand;
a92713e6 4736 unsigned int regno1, regno2, uval, num_vals;
a1d78564
RS
4737
4738 operand = (const struct mips_reg_pair_operand *) operand_base;
a92713e6
RS
4739 if (!match_reg (arg, operand->reg_type, &regno1)
4740 || !match_char (arg, ',')
4741 || !match_reg (arg, operand->reg_type, &regno2))
4742 return FALSE;
a1d78564
RS
4743
4744 num_vals = 1 << operand_base->size;
4745 for (uval = 0; uval < num_vals; uval++)
4746 if (operand->reg1_map[uval] == regno1 && operand->reg2_map[uval] == regno2)
4747 break;
4748 if (uval == num_vals)
a92713e6 4749 return FALSE;
a1d78564 4750
a1d78564 4751 insn_insert_operand (arg->insn, operand_base, uval);
a92713e6 4752 return TRUE;
a1d78564
RS
4753}
4754
4755/* OP_PCREL matcher. The caller chooses the relocation type. */
4756
a92713e6
RS
4757static bfd_boolean
4758match_pcrel_operand (struct mips_arg_info *arg)
a1d78564 4759{
a92713e6
RS
4760 bfd_reloc_code_real_type r[3];
4761
4762 return match_expression (arg, &offset_expr, r) && r[0] == BFD_RELOC_UNUSED;
a1d78564
RS
4763}
4764
4765/* OP_PERF_REG matcher. */
4766
a92713e6 4767static bfd_boolean
a1d78564 4768match_perf_reg_operand (struct mips_arg_info *arg,
a92713e6 4769 const struct mips_operand *operand)
a1d78564
RS
4770{
4771 offsetT sval;
4772
1a00e612 4773 if (!match_const_int (arg, &sval))
a92713e6 4774 return FALSE;
a1d78564
RS
4775
4776 if (sval != 0
4777 && (sval != 1
4778 || (mips_opts.arch == CPU_R5900
4779 && (strcmp (arg->insn->insn_mo->name, "mfps") == 0
4780 || strcmp (arg->insn->insn_mo->name, "mtps") == 0))))
4781 {
1a00e612
RS
4782 set_insn_error (arg->argnum, _("invalid performance register"));
4783 return FALSE;
a1d78564
RS
4784 }
4785
4786 insn_insert_operand (arg->insn, operand, sval);
a92713e6 4787 return TRUE;
a1d78564
RS
4788}
4789
4790/* OP_ADDIUSP matcher. */
4791
a92713e6 4792static bfd_boolean
a1d78564 4793match_addiusp_operand (struct mips_arg_info *arg,
a92713e6 4794 const struct mips_operand *operand)
a1d78564
RS
4795{
4796 offsetT sval;
4797 unsigned int uval;
4798
1a00e612 4799 if (!match_const_int (arg, &sval))
a92713e6 4800 return FALSE;
a1d78564
RS
4801
4802 if (sval % 4)
1a00e612
RS
4803 {
4804 match_out_of_range (arg);
4805 return FALSE;
4806 }
a1d78564
RS
4807
4808 sval /= 4;
4809 if (!(sval >= -258 && sval <= 257) || (sval >= -2 && sval <= 1))
1a00e612
RS
4810 {
4811 match_out_of_range (arg);
4812 return FALSE;
4813 }
a1d78564
RS
4814
4815 uval = (unsigned int) sval;
4816 uval = ((uval >> 1) & ~0xff) | (uval & 0xff);
4817 insn_insert_operand (arg->insn, operand, uval);
a92713e6 4818 return TRUE;
a1d78564
RS
4819}
4820
4821/* OP_CLO_CLZ_DEST matcher. */
4822
a92713e6 4823static bfd_boolean
a1d78564 4824match_clo_clz_dest_operand (struct mips_arg_info *arg,
a92713e6 4825 const struct mips_operand *operand)
a1d78564
RS
4826{
4827 unsigned int regno;
4828
a92713e6
RS
4829 if (!match_reg (arg, OP_REG_GP, &regno))
4830 return FALSE;
a1d78564 4831
a1d78564 4832 insn_insert_operand (arg->insn, operand, regno | (regno << 5));
a92713e6 4833 return TRUE;
a1d78564
RS
4834}
4835
4836/* OP_LWM_SWM_LIST matcher. */
4837
a92713e6 4838static bfd_boolean
a1d78564 4839match_lwm_swm_list_operand (struct mips_arg_info *arg,
a92713e6 4840 const struct mips_operand *operand)
a1d78564 4841{
a92713e6
RS
4842 unsigned int reglist, sregs, ra, regno1, regno2;
4843 struct mips_arg_info reset;
a1d78564 4844
a92713e6
RS
4845 reglist = 0;
4846 if (!match_reg_range (arg, OP_REG_GP, &regno1, &regno2))
4847 return FALSE;
4848 do
4849 {
4850 if (regno2 == FP && regno1 >= S0 && regno1 <= S7)
4851 {
4852 reglist |= 1 << FP;
4853 regno2 = S7;
4854 }
4855 reglist |= ((1U << regno2 << 1) - 1) & -(1U << regno1);
4856 reset = *arg;
4857 }
4858 while (match_char (arg, ',')
4859 && match_reg_range (arg, OP_REG_GP, &regno1, &regno2));
4860 *arg = reset;
a1d78564
RS
4861
4862 if (operand->size == 2)
4863 {
4864 /* The list must include both ra and s0-sN, for 0 <= N <= 3. E.g.:
4865
4866 s0, ra
4867 s0, s1, ra, s2, s3
4868 s0-s2, ra
4869
4870 and any permutations of these. */
4871 if ((reglist & 0xfff1ffff) != 0x80010000)
a92713e6 4872 return FALSE;
a1d78564
RS
4873
4874 sregs = (reglist >> 17) & 7;
4875 ra = 0;
4876 }
4877 else
4878 {
4879 /* The list must include at least one of ra and s0-sN,
4880 for 0 <= N <= 8. (Note that there is a gap between s7 and s8,
4881 which are $23 and $30 respectively.) E.g.:
4882
4883 ra
4884 s0
4885 ra, s0, s1, s2
4886 s0-s8
4887 s0-s5, ra
4888
4889 and any permutations of these. */
4890 if ((reglist & 0x3f00ffff) != 0)
a92713e6 4891 return FALSE;
a1d78564
RS
4892
4893 ra = (reglist >> 27) & 0x10;
4894 sregs = ((reglist >> 22) & 0x100) | ((reglist >> 16) & 0xff);
4895 }
4896 sregs += 1;
4897 if ((sregs & -sregs) != sregs)
a92713e6 4898 return FALSE;
a1d78564
RS
4899
4900 insn_insert_operand (arg->insn, operand, (ffs (sregs) - 1) | ra);
a92713e6 4901 return TRUE;
a1d78564
RS
4902}
4903
364215c8
RS
4904/* OP_ENTRY_EXIT_LIST matcher. */
4905
a92713e6 4906static unsigned int
364215c8 4907match_entry_exit_operand (struct mips_arg_info *arg,
a92713e6 4908 const struct mips_operand *operand)
364215c8
RS
4909{
4910 unsigned int mask;
4911 bfd_boolean is_exit;
4912
4913 /* The format is the same for both ENTRY and EXIT, but the constraints
4914 are different. */
4915 is_exit = strcmp (arg->insn->insn_mo->name, "exit") == 0;
4916 mask = (is_exit ? 7 << 3 : 0);
a92713e6 4917 do
364215c8
RS
4918 {
4919 unsigned int regno1, regno2;
4920 bfd_boolean is_freg;
4921
a92713e6 4922 if (match_reg_range (arg, OP_REG_GP, &regno1, &regno2))
364215c8 4923 is_freg = FALSE;
a92713e6 4924 else if (match_reg_range (arg, OP_REG_FP, &regno1, &regno2))
364215c8
RS
4925 is_freg = TRUE;
4926 else
a92713e6 4927 return FALSE;
364215c8
RS
4928
4929 if (is_exit && is_freg && regno1 == 0 && regno2 < 2)
4930 {
4931 mask &= ~(7 << 3);
4932 mask |= (5 + regno2) << 3;
4933 }
4934 else if (!is_exit && regno1 == 4 && regno2 >= 4 && regno2 <= 7)
4935 mask |= (regno2 - 3) << 3;
4936 else if (regno1 == 16 && regno2 >= 16 && regno2 <= 17)
4937 mask |= (regno2 - 15) << 1;
4938 else if (regno1 == RA && regno2 == RA)
4939 mask |= 1;
4940 else
a92713e6 4941 return FALSE;
364215c8 4942 }
a92713e6
RS
4943 while (match_char (arg, ','));
4944
364215c8 4945 insn_insert_operand (arg->insn, operand, mask);
a92713e6 4946 return TRUE;
364215c8
RS
4947}
4948
4949/* OP_SAVE_RESTORE_LIST matcher. */
4950
a92713e6
RS
4951static bfd_boolean
4952match_save_restore_list_operand (struct mips_arg_info *arg)
364215c8
RS
4953{
4954 unsigned int opcode, args, statics, sregs;
4955 unsigned int num_frame_sizes, num_args, num_statics, num_sregs;
364215c8 4956 offsetT frame_size;
364215c8 4957
364215c8
RS
4958 opcode = arg->insn->insn_opcode;
4959 frame_size = 0;
4960 num_frame_sizes = 0;
4961 args = 0;
4962 statics = 0;
4963 sregs = 0;
a92713e6 4964 do
364215c8
RS
4965 {
4966 unsigned int regno1, regno2;
4967
a92713e6 4968 if (arg->token->type == OT_INTEGER)
364215c8
RS
4969 {
4970 /* Handle the frame size. */
1a00e612 4971 if (!match_const_int (arg, &frame_size))
a92713e6 4972 return FALSE;
364215c8 4973 num_frame_sizes += 1;
364215c8
RS
4974 }
4975 else
4976 {
a92713e6
RS
4977 if (!match_reg_range (arg, OP_REG_GP, &regno1, &regno2))
4978 return FALSE;
364215c8
RS
4979
4980 while (regno1 <= regno2)
4981 {
4982 if (regno1 >= 4 && regno1 <= 7)
4983 {
4984 if (num_frame_sizes == 0)
4985 /* args $a0-$a3 */
4986 args |= 1 << (regno1 - 4);
4987 else
4988 /* statics $a0-$a3 */
4989 statics |= 1 << (regno1 - 4);
4990 }
4991 else if (regno1 >= 16 && regno1 <= 23)
4992 /* $s0-$s7 */
4993 sregs |= 1 << (regno1 - 16);
4994 else if (regno1 == 30)
4995 /* $s8 */
4996 sregs |= 1 << 8;
4997 else if (regno1 == 31)
4998 /* Add $ra to insn. */
4999 opcode |= 0x40;
5000 else
a92713e6 5001 return FALSE;
364215c8
RS
5002 regno1 += 1;
5003 if (regno1 == 24)
5004 regno1 = 30;
5005 }
5006 }
364215c8 5007 }
a92713e6 5008 while (match_char (arg, ','));
364215c8
RS
5009
5010 /* Encode args/statics combination. */
5011 if (args & statics)
a92713e6 5012 return FALSE;
364215c8
RS
5013 else if (args == 0xf)
5014 /* All $a0-$a3 are args. */
5015 opcode |= MIPS16_ALL_ARGS << 16;
5016 else if (statics == 0xf)
5017 /* All $a0-$a3 are statics. */
5018 opcode |= MIPS16_ALL_STATICS << 16;
5019 else
5020 {
5021 /* Count arg registers. */
5022 num_args = 0;
5023 while (args & 0x1)
5024 {
5025 args >>= 1;
5026 num_args += 1;
5027 }
5028 if (args != 0)
a92713e6 5029 return FALSE;
364215c8
RS
5030
5031 /* Count static registers. */
5032 num_statics = 0;
5033 while (statics & 0x8)
5034 {
5035 statics = (statics << 1) & 0xf;
5036 num_statics += 1;
5037 }
5038 if (statics != 0)
a92713e6 5039 return FALSE;
364215c8
RS
5040
5041 /* Encode args/statics. */
5042 opcode |= ((num_args << 2) | num_statics) << 16;
5043 }
5044
5045 /* Encode $s0/$s1. */
5046 if (sregs & (1 << 0)) /* $s0 */
5047 opcode |= 0x20;
5048 if (sregs & (1 << 1)) /* $s1 */
5049 opcode |= 0x10;
5050 sregs >>= 2;
5051
5052 /* Encode $s2-$s8. */
5053 num_sregs = 0;
5054 while (sregs & 1)
5055 {
5056 sregs >>= 1;
5057 num_sregs += 1;
5058 }
5059 if (sregs != 0)
a92713e6 5060 return FALSE;
364215c8
RS
5061 opcode |= num_sregs << 24;
5062
5063 /* Encode frame size. */
5064 if (num_frame_sizes == 0)
1a00e612
RS
5065 {
5066 set_insn_error (arg->argnum, _("missing frame size"));
5067 return FALSE;
5068 }
5069 if (num_frame_sizes > 1)
5070 {
5071 set_insn_error (arg->argnum, _("frame size specified twice"));
5072 return FALSE;
5073 }
5074 if ((frame_size & 7) != 0 || frame_size < 0 || frame_size > 0xff * 8)
5075 {
5076 set_insn_error (arg->argnum, _("invalid frame size"));
5077 return FALSE;
5078 }
5079 if (frame_size != 128 || (opcode >> 16) != 0)
364215c8
RS
5080 {
5081 frame_size /= 8;
5082 opcode |= (((frame_size & 0xf0) << 16)
5083 | (frame_size & 0x0f));
5084 }
5085
364215c8
RS
5086 /* Finally build the instruction. */
5087 if ((opcode >> 16) != 0 || frame_size == 0)
5088 opcode |= MIPS16_EXTEND;
5089 arg->insn->insn_opcode = opcode;
a92713e6 5090 return TRUE;
364215c8
RS
5091}
5092
a1d78564
RS
5093/* OP_MDMX_IMM_REG matcher. */
5094
a92713e6 5095static bfd_boolean
a1d78564 5096match_mdmx_imm_reg_operand (struct mips_arg_info *arg,
a92713e6 5097 const struct mips_operand *operand)
a1d78564 5098{
a92713e6 5099 unsigned int regno, uval;
a1d78564
RS
5100 bfd_boolean is_qh;
5101 const struct mips_opcode *opcode;
5102
5103 /* The mips_opcode records whether this is an octobyte or quadhalf
5104 instruction. Start out with that bit in place. */
5105 opcode = arg->insn->insn_mo;
5106 uval = mips_extract_operand (operand, opcode->match);
5107 is_qh = (uval != 0);
5108
56d438b1 5109 if (arg->token->type == OT_REG)
a1d78564
RS
5110 {
5111 if ((opcode->membership & INSN_5400)
5112 && strcmp (opcode->name, "rzu.ob") == 0)
5113 {
1a00e612
RS
5114 set_insn_error_i (arg->argnum, _("operand %d must be an immediate"),
5115 arg->argnum);
5116 return FALSE;
a1d78564
RS
5117 }
5118
56d438b1
CF
5119 if (!match_regno (arg, OP_REG_VEC, arg->token->u.regno, &regno))
5120 return FALSE;
5121 ++arg->token;
5122
a1d78564
RS
5123 /* Check whether this is a vector register or a broadcast of
5124 a single element. */
56d438b1 5125 if (arg->token->type == OT_INTEGER_INDEX)
a1d78564 5126 {
56d438b1 5127 if (arg->token->u.index > (is_qh ? 3 : 7))
a1d78564 5128 {
1a00e612
RS
5129 set_insn_error (arg->argnum, _("invalid element selector"));
5130 return FALSE;
a1d78564 5131 }
56d438b1
CF
5132 uval |= arg->token->u.index << (is_qh ? 2 : 1) << 5;
5133 ++arg->token;
a1d78564
RS
5134 }
5135 else
5136 {
5137 /* A full vector. */
5138 if ((opcode->membership & INSN_5400)
5139 && (strcmp (opcode->name, "sll.ob") == 0
5140 || strcmp (opcode->name, "srl.ob") == 0))
5141 {
1a00e612
RS
5142 set_insn_error_i (arg->argnum, _("operand %d must be scalar"),
5143 arg->argnum);
5144 return FALSE;
a1d78564
RS
5145 }
5146
5147 if (is_qh)
5148 uval |= MDMX_FMTSEL_VEC_QH << 5;
5149 else
5150 uval |= MDMX_FMTSEL_VEC_OB << 5;
5151 }
a1d78564
RS
5152 uval |= regno;
5153 }
5154 else
5155 {
5156 offsetT sval;
5157
1a00e612 5158 if (!match_const_int (arg, &sval))
a92713e6 5159 return FALSE;
a1d78564
RS
5160 if (sval < 0 || sval > 31)
5161 {
1a00e612
RS
5162 match_out_of_range (arg);
5163 return FALSE;
a1d78564
RS
5164 }
5165 uval |= (sval & 31);
5166 if (is_qh)
5167 uval |= MDMX_FMTSEL_IMM_QH << 5;
5168 else
5169 uval |= MDMX_FMTSEL_IMM_OB << 5;
5170 }
5171 insn_insert_operand (arg->insn, operand, uval);
a92713e6 5172 return TRUE;
a1d78564
RS
5173}
5174
56d438b1
CF
5175/* OP_IMM_INDEX matcher. */
5176
5177static bfd_boolean
5178match_imm_index_operand (struct mips_arg_info *arg,
5179 const struct mips_operand *operand)
5180{
5181 unsigned int max_val;
5182
5183 if (arg->token->type != OT_INTEGER_INDEX)
5184 return FALSE;
5185
5186 max_val = (1 << operand->size) - 1;
5187 if (arg->token->u.index > max_val)
5188 {
5189 match_out_of_range (arg);
5190 return FALSE;
5191 }
5192 insn_insert_operand (arg->insn, operand, arg->token->u.index);
5193 ++arg->token;
5194 return TRUE;
5195}
5196
5197/* OP_REG_INDEX matcher. */
5198
5199static bfd_boolean
5200match_reg_index_operand (struct mips_arg_info *arg,
5201 const struct mips_operand *operand)
5202{
5203 unsigned int regno;
5204
5205 if (arg->token->type != OT_REG_INDEX)
5206 return FALSE;
5207
5208 if (!match_regno (arg, OP_REG_GP, arg->token->u.regno, &regno))
5209 return FALSE;
5210
5211 insn_insert_operand (arg->insn, operand, regno);
5212 ++arg->token;
5213 return TRUE;
5214}
5215
a1d78564
RS
5216/* OP_PC matcher. */
5217
a92713e6
RS
5218static bfd_boolean
5219match_pc_operand (struct mips_arg_info *arg)
a1d78564 5220{
a92713e6
RS
5221 if (arg->token->type == OT_REG && (arg->token->u.regno & RTYPE_PC))
5222 {
5223 ++arg->token;
5224 return TRUE;
5225 }
5226 return FALSE;
a1d78564
RS
5227}
5228
5229/* OP_REPEAT_DEST_REG and OP_REPEAT_PREV_REG matcher. OTHER_REGNO is the
5230 register that we need to match. */
5231
a92713e6
RS
5232static bfd_boolean
5233match_tied_reg_operand (struct mips_arg_info *arg, unsigned int other_regno)
a1d78564
RS
5234{
5235 unsigned int regno;
5236
a92713e6 5237 return match_reg (arg, OP_REG_GP, &regno) && regno == other_regno;
a1d78564
RS
5238}
5239
89565f1b
RS
5240/* Read a floating-point constant from S for LI.S or LI.D. LENGTH is
5241 the length of the value in bytes (4 for float, 8 for double) and
5242 USING_GPRS says whether the destination is a GPR rather than an FPR.
5243
5244 Return the constant in IMM and OFFSET as follows:
5245
5246 - If the constant should be loaded via memory, set IMM to O_absent and
5247 OFFSET to the memory address.
5248
5249 - Otherwise, if the constant should be loaded into two 32-bit registers,
5250 set IMM to the O_constant to load into the high register and OFFSET
5251 to the corresponding value for the low register.
5252
5253 - Otherwise, set IMM to the full O_constant and set OFFSET to O_absent.
5254
5255 These constants only appear as the last operand in an instruction,
5256 and every instruction that accepts them in any variant accepts them
5257 in all variants. This means we don't have to worry about backing out
5258 any changes if the instruction does not match. We just match
5259 unconditionally and report an error if the constant is invalid. */
5260
a92713e6
RS
5261static bfd_boolean
5262match_float_constant (struct mips_arg_info *arg, expressionS *imm,
5263 expressionS *offset, int length, bfd_boolean using_gprs)
89565f1b 5264{
a92713e6 5265 char *p;
89565f1b
RS
5266 segT seg, new_seg;
5267 subsegT subseg;
5268 const char *newname;
a92713e6 5269 unsigned char *data;
89565f1b
RS
5270
5271 /* Where the constant is placed is based on how the MIPS assembler
5272 does things:
5273
5274 length == 4 && using_gprs -- immediate value only
5275 length == 8 && using_gprs -- .rdata or immediate value
5276 length == 4 && !using_gprs -- .lit4 or immediate value
5277 length == 8 && !using_gprs -- .lit8 or immediate value
5278
5279 The .lit4 and .lit8 sections are only used if permitted by the
5280 -G argument. */
a92713e6 5281 if (arg->token->type != OT_FLOAT)
1a00e612
RS
5282 {
5283 set_insn_error (arg->argnum, _("floating-point expression required"));
5284 return FALSE;
5285 }
a92713e6
RS
5286
5287 gas_assert (arg->token->u.flt.length == length);
5288 data = arg->token->u.flt.data;
5289 ++arg->token;
89565f1b
RS
5290
5291 /* Handle 32-bit constants for which an immediate value is best. */
5292 if (length == 4
5293 && (using_gprs
5294 || g_switch_value < 4
5295 || (data[0] == 0 && data[1] == 0)
5296 || (data[2] == 0 && data[3] == 0)))
5297 {
5298 imm->X_op = O_constant;
5299 if (!target_big_endian)
5300 imm->X_add_number = bfd_getl32 (data);
5301 else
5302 imm->X_add_number = bfd_getb32 (data);
5303 offset->X_op = O_absent;
a92713e6 5304 return TRUE;
89565f1b
RS
5305 }
5306
5307 /* Handle 64-bit constants for which an immediate value is best. */
5308 if (length == 8
5309 && !mips_disable_float_construction
5310 /* Constants can only be constructed in GPRs and copied
5311 to FPRs if the GPRs are at least as wide as the FPRs.
5312 Force the constant into memory if we are using 64-bit FPRs
5313 but the GPRs are only 32 bits wide. */
5314 /* ??? No longer true with the addition of MTHC1, but this
5315 is legacy code... */
5316 && (using_gprs || !(HAVE_64BIT_FPRS && HAVE_32BIT_GPRS))
5317 && ((data[0] == 0 && data[1] == 0)
5318 || (data[2] == 0 && data[3] == 0))
5319 && ((data[4] == 0 && data[5] == 0)
5320 || (data[6] == 0 && data[7] == 0)))
5321 {
5322 /* The value is simple enough to load with a couple of instructions.
5323 If using 32-bit registers, set IMM to the high order 32 bits and
5324 OFFSET to the low order 32 bits. Otherwise, set IMM to the entire
5325 64 bit constant. */
5326 if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS)
5327 {
5328 imm->X_op = O_constant;
5329 offset->X_op = O_constant;
5330 if (!target_big_endian)
5331 {
5332 imm->X_add_number = bfd_getl32 (data + 4);
5333 offset->X_add_number = bfd_getl32 (data);
5334 }
5335 else
5336 {
5337 imm->X_add_number = bfd_getb32 (data);
5338 offset->X_add_number = bfd_getb32 (data + 4);
5339 }
5340 if (offset->X_add_number == 0)
5341 offset->X_op = O_absent;
5342 }
5343 else
5344 {
5345 imm->X_op = O_constant;
5346 if (!target_big_endian)
5347 imm->X_add_number = bfd_getl64 (data);
5348 else
5349 imm->X_add_number = bfd_getb64 (data);
5350 offset->X_op = O_absent;
5351 }
a92713e6 5352 return TRUE;
89565f1b
RS
5353 }
5354
5355 /* Switch to the right section. */
5356 seg = now_seg;
5357 subseg = now_subseg;
5358 if (length == 4)
5359 {
5360 gas_assert (!using_gprs && g_switch_value >= 4);
5361 newname = ".lit4";
5362 }
5363 else
5364 {
5365 if (using_gprs || g_switch_value < 8)
5366 newname = RDATA_SECTION_NAME;
5367 else
5368 newname = ".lit8";
5369 }
5370
5371 new_seg = subseg_new (newname, (subsegT) 0);
5372 bfd_set_section_flags (stdoutput, new_seg,
5373 SEC_ALLOC | SEC_LOAD | SEC_READONLY | SEC_DATA);
5374 frag_align (length == 4 ? 2 : 3, 0, 0);
5375 if (strncmp (TARGET_OS, "elf", 3) != 0)
5376 record_alignment (new_seg, 4);
5377 else
5378 record_alignment (new_seg, length == 4 ? 2 : 3);
5379 if (seg == now_seg)
1661c76c 5380 as_bad (_("cannot use `%s' in this section"), arg->insn->insn_mo->name);
89565f1b
RS
5381
5382 /* Set the argument to the current address in the section. */
5383 imm->X_op = O_absent;
5384 offset->X_op = O_symbol;
5385 offset->X_add_symbol = symbol_temp_new_now ();
5386 offset->X_add_number = 0;
5387
5388 /* Put the floating point number into the section. */
5389 p = frag_more (length);
5390 memcpy (p, data, length);
5391
5392 /* Switch back to the original section. */
5393 subseg_set (seg, subseg);
a92713e6 5394 return TRUE;
89565f1b
RS
5395}
5396
14daeee3
RS
5397/* OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX matcher; MATCH_P selects between
5398 them. */
5399
5400static bfd_boolean
5401match_vu0_suffix_operand (struct mips_arg_info *arg,
5402 const struct mips_operand *operand,
5403 bfd_boolean match_p)
5404{
5405 unsigned int uval;
5406
5407 /* The operand can be an XYZW mask or a single 2-bit channel index
5408 (with X being 0). */
5409 gas_assert (operand->size == 2 || operand->size == 4);
5410
ee5734f0 5411 /* The suffix can be omitted when it is already part of the opcode. */
14daeee3 5412 if (arg->token->type != OT_CHANNELS)
ee5734f0 5413 return match_p;
14daeee3
RS
5414
5415 uval = arg->token->u.channels;
5416 if (operand->size == 2)
5417 {
5418 /* Check that a single bit is set and convert it into a 2-bit index. */
5419 if ((uval & -uval) != uval)
5420 return FALSE;
5421 uval = 4 - ffs (uval);
5422 }
5423
5424 if (match_p && insn_extract_operand (arg->insn, operand) != uval)
5425 return FALSE;
5426
5427 ++arg->token;
5428 if (!match_p)
5429 insn_insert_operand (arg->insn, operand, uval);
5430 return TRUE;
5431}
5432
a1d78564
RS
5433/* S is the text seen for ARG. Match it against OPERAND. Return the end
5434 of the argument text if the match is successful, otherwise return null. */
5435
a92713e6 5436static bfd_boolean
a1d78564 5437match_operand (struct mips_arg_info *arg,
a92713e6 5438 const struct mips_operand *operand)
a1d78564
RS
5439{
5440 switch (operand->type)
5441 {
5442 case OP_INT:
a92713e6 5443 return match_int_operand (arg, operand);
a1d78564
RS
5444
5445 case OP_MAPPED_INT:
a92713e6 5446 return match_mapped_int_operand (arg, operand);
a1d78564
RS
5447
5448 case OP_MSB:
a92713e6 5449 return match_msb_operand (arg, operand);
a1d78564
RS
5450
5451 case OP_REG:
0f35dbc4 5452 case OP_OPTIONAL_REG:
a92713e6 5453 return match_reg_operand (arg, operand);
a1d78564
RS
5454
5455 case OP_REG_PAIR:
a92713e6 5456 return match_reg_pair_operand (arg, operand);
a1d78564
RS
5457
5458 case OP_PCREL:
a92713e6 5459 return match_pcrel_operand (arg);
a1d78564
RS
5460
5461 case OP_PERF_REG:
a92713e6 5462 return match_perf_reg_operand (arg, operand);
a1d78564
RS
5463
5464 case OP_ADDIUSP_INT:
a92713e6 5465 return match_addiusp_operand (arg, operand);
a1d78564
RS
5466
5467 case OP_CLO_CLZ_DEST:
a92713e6 5468 return match_clo_clz_dest_operand (arg, operand);
a1d78564
RS
5469
5470 case OP_LWM_SWM_LIST:
a92713e6 5471 return match_lwm_swm_list_operand (arg, operand);
a1d78564
RS
5472
5473 case OP_ENTRY_EXIT_LIST:
a92713e6 5474 return match_entry_exit_operand (arg, operand);
364215c8 5475
a1d78564 5476 case OP_SAVE_RESTORE_LIST:
a92713e6 5477 return match_save_restore_list_operand (arg);
a1d78564
RS
5478
5479 case OP_MDMX_IMM_REG:
a92713e6 5480 return match_mdmx_imm_reg_operand (arg, operand);
a1d78564
RS
5481
5482 case OP_REPEAT_DEST_REG:
a92713e6 5483 return match_tied_reg_operand (arg, arg->dest_regno);
a1d78564
RS
5484
5485 case OP_REPEAT_PREV_REG:
a92713e6 5486 return match_tied_reg_operand (arg, arg->last_regno);
a1d78564
RS
5487
5488 case OP_PC:
a92713e6 5489 return match_pc_operand (arg);
14daeee3
RS
5490
5491 case OP_VU0_SUFFIX:
5492 return match_vu0_suffix_operand (arg, operand, FALSE);
5493
5494 case OP_VU0_MATCH_SUFFIX:
5495 return match_vu0_suffix_operand (arg, operand, TRUE);
56d438b1
CF
5496
5497 case OP_IMM_INDEX:
5498 return match_imm_index_operand (arg, operand);
5499
5500 case OP_REG_INDEX:
5501 return match_reg_index_operand (arg, operand);
a1d78564
RS
5502 }
5503 abort ();
5504}
5505
5506/* ARG is the state after successfully matching an instruction.
5507 Issue any queued-up warnings. */
5508
5509static void
5510check_completed_insn (struct mips_arg_info *arg)
5511{
5512 if (arg->seen_at)
5513 {
5514 if (AT == ATREG)
1661c76c 5515 as_warn (_("used $at without \".set noat\""));
a1d78564 5516 else
1661c76c 5517 as_warn (_("used $%u with \".set at=$%u\""), AT, AT);
a1d78564
RS
5518 }
5519}
a1d78564 5520
85fcb30f
RS
5521/* Return true if modifying general-purpose register REG needs a delay. */
5522
5523static bfd_boolean
5524reg_needs_delay (unsigned int reg)
5525{
5526 unsigned long prev_pinfo;
5527
5528 prev_pinfo = history[0].insn_mo->pinfo;
5529 if (!mips_opts.noreorder
5530 && (((prev_pinfo & INSN_LOAD_MEMORY_DELAY) && !gpr_interlocks)
5531 || ((prev_pinfo & INSN_LOAD_COPROC_DELAY) && !cop_interlocks))
5532 && (gpr_write_mask (&history[0]) & (1 << reg)))
5533 return TRUE;
5534
5535 return FALSE;
5536}
5537
71400594
RS
5538/* Classify an instruction according to the FIX_VR4120_* enumeration.
5539 Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected
5540 by VR4120 errata. */
4d7206a2 5541
71400594
RS
5542static unsigned int
5543classify_vr4120_insn (const char *name)
252b5132 5544{
71400594
RS
5545 if (strncmp (name, "macc", 4) == 0)
5546 return FIX_VR4120_MACC;
5547 if (strncmp (name, "dmacc", 5) == 0)
5548 return FIX_VR4120_DMACC;
5549 if (strncmp (name, "mult", 4) == 0)
5550 return FIX_VR4120_MULT;
5551 if (strncmp (name, "dmult", 5) == 0)
5552 return FIX_VR4120_DMULT;
5553 if (strstr (name, "div"))
5554 return FIX_VR4120_DIV;
5555 if (strcmp (name, "mtlo") == 0 || strcmp (name, "mthi") == 0)
5556 return FIX_VR4120_MTHILO;
5557 return NUM_FIX_VR4120_CLASSES;
5558}
252b5132 5559
ff239038
CM
5560#define INSN_ERET 0x42000018
5561#define INSN_DERET 0x4200001f
5562
71400594
RS
5563/* Return the number of instructions that must separate INSN1 and INSN2,
5564 where INSN1 is the earlier instruction. Return the worst-case value
5565 for any INSN2 if INSN2 is null. */
252b5132 5566
71400594
RS
5567static unsigned int
5568insns_between (const struct mips_cl_insn *insn1,
5569 const struct mips_cl_insn *insn2)
5570{
5571 unsigned long pinfo1, pinfo2;
4c260379 5572 unsigned int mask;
71400594 5573
85fcb30f
RS
5574 /* If INFO2 is null, pessimistically assume that all flags are set for
5575 the second instruction. */
71400594
RS
5576 pinfo1 = insn1->insn_mo->pinfo;
5577 pinfo2 = insn2 ? insn2->insn_mo->pinfo : ~0U;
252b5132 5578
71400594
RS
5579 /* For most targets, write-after-read dependencies on the HI and LO
5580 registers must be separated by at least two instructions. */
5581 if (!hilo_interlocks)
252b5132 5582 {
71400594
RS
5583 if ((pinfo1 & INSN_READ_LO) && (pinfo2 & INSN_WRITE_LO))
5584 return 2;
5585 if ((pinfo1 & INSN_READ_HI) && (pinfo2 & INSN_WRITE_HI))
5586 return 2;
5587 }
5588
5589 /* If we're working around r7000 errata, there must be two instructions
5590 between an mfhi or mflo and any instruction that uses the result. */
5591 if (mips_7000_hilo_fix
df58fc94 5592 && !mips_opts.micromips
71400594 5593 && MF_HILO_INSN (pinfo1)
85fcb30f 5594 && (insn2 == NULL || (gpr_read_mask (insn2) & gpr_write_mask (insn1))))
71400594
RS
5595 return 2;
5596
ff239038
CM
5597 /* If we're working around 24K errata, one instruction is required
5598 if an ERET or DERET is followed by a branch instruction. */
df58fc94 5599 if (mips_fix_24k && !mips_opts.micromips)
ff239038
CM
5600 {
5601 if (insn1->insn_opcode == INSN_ERET
5602 || insn1->insn_opcode == INSN_DERET)
5603 {
5604 if (insn2 == NULL
5605 || insn2->insn_opcode == INSN_ERET
5606 || insn2->insn_opcode == INSN_DERET
11625dd8 5607 || delayed_branch_p (insn2))
ff239038
CM
5608 return 1;
5609 }
5610 }
5611
71400594
RS
5612 /* If working around VR4120 errata, check for combinations that need
5613 a single intervening instruction. */
df58fc94 5614 if (mips_fix_vr4120 && !mips_opts.micromips)
71400594
RS
5615 {
5616 unsigned int class1, class2;
252b5132 5617
71400594
RS
5618 class1 = classify_vr4120_insn (insn1->insn_mo->name);
5619 if (class1 != NUM_FIX_VR4120_CLASSES && vr4120_conflicts[class1] != 0)
252b5132 5620 {
71400594
RS
5621 if (insn2 == NULL)
5622 return 1;
5623 class2 = classify_vr4120_insn (insn2->insn_mo->name);
5624 if (vr4120_conflicts[class1] & (1 << class2))
5625 return 1;
252b5132 5626 }
71400594
RS
5627 }
5628
df58fc94 5629 if (!HAVE_CODE_COMPRESSION)
71400594
RS
5630 {
5631 /* Check for GPR or coprocessor load delays. All such delays
5632 are on the RT register. */
5633 /* Itbl support may require additional care here. */
5634 if ((!gpr_interlocks && (pinfo1 & INSN_LOAD_MEMORY_DELAY))
5635 || (!cop_interlocks && (pinfo1 & INSN_LOAD_COPROC_DELAY)))
252b5132 5636 {
85fcb30f 5637 if (insn2 == NULL || (gpr_read_mask (insn2) & gpr_write_mask (insn1)))
71400594
RS
5638 return 1;
5639 }
5640
5641 /* Check for generic coprocessor hazards.
5642
5643 This case is not handled very well. There is no special
5644 knowledge of CP0 handling, and the coprocessors other than
5645 the floating point unit are not distinguished at all. */
5646 /* Itbl support may require additional care here. FIXME!
5647 Need to modify this to include knowledge about
5648 user specified delays! */
5649 else if ((!cop_interlocks && (pinfo1 & INSN_COPROC_MOVE_DELAY))
5650 || (!cop_mem_interlocks && (pinfo1 & INSN_COPROC_MEMORY_DELAY)))
5651 {
5652 /* Handle cases where INSN1 writes to a known general coprocessor
5653 register. There must be a one instruction delay before INSN2
5654 if INSN2 reads that register, otherwise no delay is needed. */
4c260379
RS
5655 mask = fpr_write_mask (insn1);
5656 if (mask != 0)
252b5132 5657 {
4c260379 5658 if (!insn2 || (mask & fpr_read_mask (insn2)) != 0)
71400594 5659 return 1;
252b5132
RH
5660 }
5661 else
5662 {
71400594
RS
5663 /* Read-after-write dependencies on the control registers
5664 require a two-instruction gap. */
5665 if ((pinfo1 & INSN_WRITE_COND_CODE)
5666 && (pinfo2 & INSN_READ_COND_CODE))
5667 return 2;
5668
5669 /* We don't know exactly what INSN1 does. If INSN2 is
5670 also a coprocessor instruction, assume there must be
5671 a one instruction gap. */
5672 if (pinfo2 & INSN_COP)
5673 return 1;
252b5132
RH
5674 }
5675 }
6b76fefe 5676
71400594
RS
5677 /* Check for read-after-write dependencies on the coprocessor
5678 control registers in cases where INSN1 does not need a general
5679 coprocessor delay. This means that INSN1 is a floating point
5680 comparison instruction. */
5681 /* Itbl support may require additional care here. */
5682 else if (!cop_interlocks
5683 && (pinfo1 & INSN_WRITE_COND_CODE)
5684 && (pinfo2 & INSN_READ_COND_CODE))
5685 return 1;
5686 }
6b76fefe 5687
71400594
RS
5688 return 0;
5689}
6b76fefe 5690
7d8e00cf
RS
5691/* Return the number of nops that would be needed to work around the
5692 VR4130 mflo/mfhi errata if instruction INSN immediately followed
932d1a1b
RS
5693 the MAX_VR4130_NOPS instructions described by HIST. Ignore hazards
5694 that are contained within the first IGNORE instructions of HIST. */
7d8e00cf
RS
5695
5696static int
932d1a1b 5697nops_for_vr4130 (int ignore, const struct mips_cl_insn *hist,
7d8e00cf
RS
5698 const struct mips_cl_insn *insn)
5699{
4c260379
RS
5700 int i, j;
5701 unsigned int mask;
7d8e00cf
RS
5702
5703 /* Check if the instruction writes to HI or LO. MTHI and MTLO
5704 are not affected by the errata. */
5705 if (insn != 0
5706 && ((insn->insn_mo->pinfo & (INSN_WRITE_HI | INSN_WRITE_LO)) == 0
5707 || strcmp (insn->insn_mo->name, "mtlo") == 0
5708 || strcmp (insn->insn_mo->name, "mthi") == 0))
5709 return 0;
5710
5711 /* Search for the first MFLO or MFHI. */
5712 for (i = 0; i < MAX_VR4130_NOPS; i++)
91d6fa6a 5713 if (MF_HILO_INSN (hist[i].insn_mo->pinfo))
7d8e00cf
RS
5714 {
5715 /* Extract the destination register. */
4c260379 5716 mask = gpr_write_mask (&hist[i]);
7d8e00cf
RS
5717
5718 /* No nops are needed if INSN reads that register. */
4c260379 5719 if (insn != NULL && (gpr_read_mask (insn) & mask) != 0)
7d8e00cf
RS
5720 return 0;
5721
5722 /* ...or if any of the intervening instructions do. */
5723 for (j = 0; j < i; j++)
4c260379 5724 if (gpr_read_mask (&hist[j]) & mask)
7d8e00cf
RS
5725 return 0;
5726
932d1a1b
RS
5727 if (i >= ignore)
5728 return MAX_VR4130_NOPS - i;
7d8e00cf
RS
5729 }
5730 return 0;
5731}
5732
15be625d
CM
5733#define BASE_REG_EQ(INSN1, INSN2) \
5734 ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \
5735 == (((INSN2) >> OP_SH_RS) & OP_MASK_RS))
5736
5737/* Return the minimum alignment for this store instruction. */
5738
5739static int
5740fix_24k_align_to (const struct mips_opcode *mo)
5741{
5742 if (strcmp (mo->name, "sh") == 0)
5743 return 2;
5744
5745 if (strcmp (mo->name, "swc1") == 0
5746 || strcmp (mo->name, "swc2") == 0
5747 || strcmp (mo->name, "sw") == 0
5748 || strcmp (mo->name, "sc") == 0
5749 || strcmp (mo->name, "s.s") == 0)
5750 return 4;
5751
5752 if (strcmp (mo->name, "sdc1") == 0
5753 || strcmp (mo->name, "sdc2") == 0
5754 || strcmp (mo->name, "s.d") == 0)
5755 return 8;
5756
5757 /* sb, swl, swr */
5758 return 1;
5759}
5760
5761struct fix_24k_store_info
5762 {
5763 /* Immediate offset, if any, for this store instruction. */
5764 short off;
5765 /* Alignment required by this store instruction. */
5766 int align_to;
5767 /* True for register offsets. */
5768 int register_offset;
5769 };
5770
5771/* Comparison function used by qsort. */
5772
5773static int
5774fix_24k_sort (const void *a, const void *b)
5775{
5776 const struct fix_24k_store_info *pos1 = a;
5777 const struct fix_24k_store_info *pos2 = b;
5778
5779 return (pos1->off - pos2->off);
5780}
5781
5782/* INSN is a store instruction. Try to record the store information
5783 in STINFO. Return false if the information isn't known. */
5784
5785static bfd_boolean
5786fix_24k_record_store_info (struct fix_24k_store_info *stinfo,
ab9794cf 5787 const struct mips_cl_insn *insn)
15be625d
CM
5788{
5789 /* The instruction must have a known offset. */
5790 if (!insn->complete_p || !strstr (insn->insn_mo->args, "o("))
5791 return FALSE;
5792
5793 stinfo->off = (insn->insn_opcode >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE;
5794 stinfo->align_to = fix_24k_align_to (insn->insn_mo);
5795 return TRUE;
5796}
5797
932d1a1b
RS
5798/* Return the number of nops that would be needed to work around the 24k
5799 "lost data on stores during refill" errata if instruction INSN
5800 immediately followed the 2 instructions described by HIST.
5801 Ignore hazards that are contained within the first IGNORE
5802 instructions of HIST.
5803
5804 Problem: The FSB (fetch store buffer) acts as an intermediate buffer
5805 for the data cache refills and store data. The following describes
5806 the scenario where the store data could be lost.
5807
5808 * A data cache miss, due to either a load or a store, causing fill
5809 data to be supplied by the memory subsystem
5810 * The first three doublewords of fill data are returned and written
5811 into the cache
5812 * A sequence of four stores occurs in consecutive cycles around the
5813 final doubleword of the fill:
5814 * Store A
5815 * Store B
5816 * Store C
5817 * Zero, One or more instructions
5818 * Store D
5819
5820 The four stores A-D must be to different doublewords of the line that
5821 is being filled. The fourth instruction in the sequence above permits
5822 the fill of the final doubleword to be transferred from the FSB into
5823 the cache. In the sequence above, the stores may be either integer
5824 (sb, sh, sw, swr, swl, sc) or coprocessor (swc1/swc2, sdc1/sdc2,
5825 swxc1, sdxc1, suxc1) stores, as long as the four stores are to
5826 different doublewords on the line. If the floating point unit is
5827 running in 1:2 mode, it is not possible to create the sequence above
5828 using only floating point store instructions.
15be625d
CM
5829
5830 In this case, the cache line being filled is incorrectly marked
5831 invalid, thereby losing the data from any store to the line that
5832 occurs between the original miss and the completion of the five
5833 cycle sequence shown above.
5834
932d1a1b 5835 The workarounds are:
15be625d 5836
932d1a1b
RS
5837 * Run the data cache in write-through mode.
5838 * Insert a non-store instruction between
5839 Store A and Store B or Store B and Store C. */
15be625d
CM
5840
5841static int
932d1a1b 5842nops_for_24k (int ignore, const struct mips_cl_insn *hist,
15be625d
CM
5843 const struct mips_cl_insn *insn)
5844{
5845 struct fix_24k_store_info pos[3];
5846 int align, i, base_offset;
5847
932d1a1b
RS
5848 if (ignore >= 2)
5849 return 0;
5850
ab9794cf
RS
5851 /* If the previous instruction wasn't a store, there's nothing to
5852 worry about. */
15be625d
CM
5853 if ((hist[0].insn_mo->pinfo & INSN_STORE_MEMORY) == 0)
5854 return 0;
5855
ab9794cf
RS
5856 /* If the instructions after the previous one are unknown, we have
5857 to assume the worst. */
5858 if (!insn)
15be625d
CM
5859 return 1;
5860
ab9794cf
RS
5861 /* Check whether we are dealing with three consecutive stores. */
5862 if ((insn->insn_mo->pinfo & INSN_STORE_MEMORY) == 0
5863 || (hist[1].insn_mo->pinfo & INSN_STORE_MEMORY) == 0)
15be625d
CM
5864 return 0;
5865
5866 /* If we don't know the relationship between the store addresses,
5867 assume the worst. */
ab9794cf 5868 if (!BASE_REG_EQ (insn->insn_opcode, hist[0].insn_opcode)
15be625d
CM
5869 || !BASE_REG_EQ (insn->insn_opcode, hist[1].insn_opcode))
5870 return 1;
5871
5872 if (!fix_24k_record_store_info (&pos[0], insn)
5873 || !fix_24k_record_store_info (&pos[1], &hist[0])
5874 || !fix_24k_record_store_info (&pos[2], &hist[1]))
5875 return 1;
5876
5877 qsort (&pos, 3, sizeof (struct fix_24k_store_info), fix_24k_sort);
5878
5879 /* Pick a value of ALIGN and X such that all offsets are adjusted by
5880 X bytes and such that the base register + X is known to be aligned
5881 to align bytes. */
5882
5883 if (((insn->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == SP)
5884 align = 8;
5885 else
5886 {
5887 align = pos[0].align_to;
5888 base_offset = pos[0].off;
5889 for (i = 1; i < 3; i++)
5890 if (align < pos[i].align_to)
5891 {
5892 align = pos[i].align_to;
5893 base_offset = pos[i].off;
5894 }
5895 for (i = 0; i < 3; i++)
5896 pos[i].off -= base_offset;
5897 }
5898
5899 pos[0].off &= ~align + 1;
5900 pos[1].off &= ~align + 1;
5901 pos[2].off &= ~align + 1;
5902
5903 /* If any two stores write to the same chunk, they also write to the
5904 same doubleword. The offsets are still sorted at this point. */
5905 if (pos[0].off == pos[1].off || pos[1].off == pos[2].off)
5906 return 0;
5907
5908 /* A range of at least 9 bytes is needed for the stores to be in
5909 non-overlapping doublewords. */
5910 if (pos[2].off - pos[0].off <= 8)
5911 return 0;
5912
5913 if (pos[2].off - pos[1].off >= 24
5914 || pos[1].off - pos[0].off >= 24
5915 || pos[2].off - pos[0].off >= 32)
5916 return 0;
5917
5918 return 1;
5919}
5920
71400594 5921/* Return the number of nops that would be needed if instruction INSN
91d6fa6a 5922 immediately followed the MAX_NOPS instructions given by HIST,
932d1a1b
RS
5923 where HIST[0] is the most recent instruction. Ignore hazards
5924 between INSN and the first IGNORE instructions in HIST.
5925
5926 If INSN is null, return the worse-case number of nops for any
5927 instruction. */
bdaaa2e1 5928
71400594 5929static int
932d1a1b 5930nops_for_insn (int ignore, const struct mips_cl_insn *hist,
71400594
RS
5931 const struct mips_cl_insn *insn)
5932{
5933 int i, nops, tmp_nops;
bdaaa2e1 5934
71400594 5935 nops = 0;
932d1a1b 5936 for (i = ignore; i < MAX_DELAY_NOPS; i++)
65b02341 5937 {
91d6fa6a 5938 tmp_nops = insns_between (hist + i, insn) - i;
65b02341
RS
5939 if (tmp_nops > nops)
5940 nops = tmp_nops;
5941 }
7d8e00cf 5942
df58fc94 5943 if (mips_fix_vr4130 && !mips_opts.micromips)
7d8e00cf 5944 {
932d1a1b 5945 tmp_nops = nops_for_vr4130 (ignore, hist, insn);
7d8e00cf
RS
5946 if (tmp_nops > nops)
5947 nops = tmp_nops;
5948 }
5949
df58fc94 5950 if (mips_fix_24k && !mips_opts.micromips)
15be625d 5951 {
932d1a1b 5952 tmp_nops = nops_for_24k (ignore, hist, insn);
15be625d
CM
5953 if (tmp_nops > nops)
5954 nops = tmp_nops;
5955 }
5956
71400594
RS
5957 return nops;
5958}
252b5132 5959
71400594 5960/* The variable arguments provide NUM_INSNS extra instructions that
91d6fa6a 5961 might be added to HIST. Return the largest number of nops that
932d1a1b
RS
5962 would be needed after the extended sequence, ignoring hazards
5963 in the first IGNORE instructions. */
252b5132 5964
71400594 5965static int
932d1a1b
RS
5966nops_for_sequence (int num_insns, int ignore,
5967 const struct mips_cl_insn *hist, ...)
71400594
RS
5968{
5969 va_list args;
5970 struct mips_cl_insn buffer[MAX_NOPS];
5971 struct mips_cl_insn *cursor;
5972 int nops;
5973
91d6fa6a 5974 va_start (args, hist);
71400594 5975 cursor = buffer + num_insns;
91d6fa6a 5976 memcpy (cursor, hist, (MAX_NOPS - num_insns) * sizeof (*cursor));
71400594
RS
5977 while (cursor > buffer)
5978 *--cursor = *va_arg (args, const struct mips_cl_insn *);
5979
932d1a1b 5980 nops = nops_for_insn (ignore, buffer, NULL);
71400594
RS
5981 va_end (args);
5982 return nops;
5983}
252b5132 5984
71400594
RS
5985/* Like nops_for_insn, but if INSN is a branch, take into account the
5986 worst-case delay for the branch target. */
252b5132 5987
71400594 5988static int
932d1a1b 5989nops_for_insn_or_target (int ignore, const struct mips_cl_insn *hist,
71400594
RS
5990 const struct mips_cl_insn *insn)
5991{
5992 int nops, tmp_nops;
60b63b72 5993
932d1a1b 5994 nops = nops_for_insn (ignore, hist, insn);
11625dd8 5995 if (delayed_branch_p (insn))
71400594 5996 {
932d1a1b 5997 tmp_nops = nops_for_sequence (2, ignore ? ignore + 2 : 0,
14fe068b 5998 hist, insn, get_delay_slot_nop (insn));
71400594
RS
5999 if (tmp_nops > nops)
6000 nops = tmp_nops;
6001 }
11625dd8 6002 else if (compact_branch_p (insn))
71400594 6003 {
932d1a1b 6004 tmp_nops = nops_for_sequence (1, ignore ? ignore + 1 : 0, hist, insn);
71400594
RS
6005 if (tmp_nops > nops)
6006 nops = tmp_nops;
6007 }
6008 return nops;
6009}
6010
c67a084a
NC
6011/* Fix NOP issue: Replace nops by "or at,at,zero". */
6012
6013static void
6014fix_loongson2f_nop (struct mips_cl_insn * ip)
6015{
df58fc94 6016 gas_assert (!HAVE_CODE_COMPRESSION);
c67a084a
NC
6017 if (strcmp (ip->insn_mo->name, "nop") == 0)
6018 ip->insn_opcode = LOONGSON2F_NOP_INSN;
6019}
6020
6021/* Fix Jump Issue: Eliminate instruction fetch from outside 256M region
6022 jr target pc &= 'hffff_ffff_cfff_ffff. */
6023
6024static void
6025fix_loongson2f_jump (struct mips_cl_insn * ip)
6026{
df58fc94 6027 gas_assert (!HAVE_CODE_COMPRESSION);
c67a084a
NC
6028 if (strcmp (ip->insn_mo->name, "j") == 0
6029 || strcmp (ip->insn_mo->name, "jr") == 0
6030 || strcmp (ip->insn_mo->name, "jalr") == 0)
6031 {
6032 int sreg;
6033 expressionS ep;
6034
6035 if (! mips_opts.at)
6036 return;
6037
df58fc94 6038 sreg = EXTRACT_OPERAND (0, RS, *ip);
c67a084a
NC
6039 if (sreg == ZERO || sreg == KT0 || sreg == KT1 || sreg == ATREG)
6040 return;
6041
6042 ep.X_op = O_constant;
6043 ep.X_add_number = 0xcfff0000;
6044 macro_build (&ep, "lui", "t,u", ATREG, BFD_RELOC_HI16);
6045 ep.X_add_number = 0xffff;
6046 macro_build (&ep, "ori", "t,r,i", ATREG, ATREG, BFD_RELOC_LO16);
6047 macro_build (NULL, "and", "d,v,t", sreg, sreg, ATREG);
6048 }
6049}
6050
6051static void
6052fix_loongson2f (struct mips_cl_insn * ip)
6053{
6054 if (mips_fix_loongson2f_nop)
6055 fix_loongson2f_nop (ip);
6056
6057 if (mips_fix_loongson2f_jump)
6058 fix_loongson2f_jump (ip);
6059}
6060
a4e06468
RS
6061/* IP is a branch that has a delay slot, and we need to fill it
6062 automatically. Return true if we can do that by swapping IP
e407c74b
NC
6063 with the previous instruction.
6064 ADDRESS_EXPR is an operand of the instruction to be used with
6065 RELOC_TYPE. */
a4e06468
RS
6066
6067static bfd_boolean
e407c74b 6068can_swap_branch_p (struct mips_cl_insn *ip, expressionS *address_expr,
26545944 6069 bfd_reloc_code_real_type *reloc_type)
a4e06468 6070{
2b0c8b40 6071 unsigned long pinfo, pinfo2, prev_pinfo, prev_pinfo2;
a4e06468
RS
6072 unsigned int gpr_read, gpr_write, prev_gpr_read, prev_gpr_write;
6073
6074 /* -O2 and above is required for this optimization. */
6075 if (mips_optimize < 2)
6076 return FALSE;
6077
6078 /* If we have seen .set volatile or .set nomove, don't optimize. */
6079 if (mips_opts.nomove)
6080 return FALSE;
6081
6082 /* We can't swap if the previous instruction's position is fixed. */
6083 if (history[0].fixed_p)
6084 return FALSE;
6085
6086 /* If the previous previous insn was in a .set noreorder, we can't
6087 swap. Actually, the MIPS assembler will swap in this situation.
6088 However, gcc configured -with-gnu-as will generate code like
6089
6090 .set noreorder
6091 lw $4,XXX
6092 .set reorder
6093 INSN
6094 bne $4,$0,foo
6095
6096 in which we can not swap the bne and INSN. If gcc is not configured
6097 -with-gnu-as, it does not output the .set pseudo-ops. */
6098 if (history[1].noreorder_p)
6099 return FALSE;
6100
87333bb7
MR
6101 /* If the previous instruction had a fixup in mips16 mode, we can not swap.
6102 This means that the previous instruction was a 4-byte one anyhow. */
a4e06468
RS
6103 if (mips_opts.mips16 && history[0].fixp[0])
6104 return FALSE;
6105
6106 /* If the branch is itself the target of a branch, we can not swap.
6107 We cheat on this; all we check for is whether there is a label on
6108 this instruction. If there are any branches to anything other than
6109 a label, users must use .set noreorder. */
6110 if (seg_info (now_seg)->label_list)
6111 return FALSE;
6112
6113 /* If the previous instruction is in a variant frag other than this
2309ddf2 6114 branch's one, we cannot do the swap. This does not apply to
9301f9c3
MR
6115 MIPS16 code, which uses variant frags for different purposes. */
6116 if (!mips_opts.mips16
a4e06468
RS
6117 && history[0].frag
6118 && history[0].frag->fr_type == rs_machine_dependent)
6119 return FALSE;
6120
bcd530a7
RS
6121 /* We do not swap with instructions that cannot architecturally
6122 be placed in a branch delay slot, such as SYNC or ERET. We
6123 also refrain from swapping with a trap instruction, since it
6124 complicates trap handlers to have the trap instruction be in
6125 a delay slot. */
a4e06468 6126 prev_pinfo = history[0].insn_mo->pinfo;
bcd530a7 6127 if (prev_pinfo & INSN_NO_DELAY_SLOT)
a4e06468
RS
6128 return FALSE;
6129
6130 /* Check for conflicts between the branch and the instructions
6131 before the candidate delay slot. */
6132 if (nops_for_insn (0, history + 1, ip) > 0)
6133 return FALSE;
6134
6135 /* Check for conflicts between the swapped sequence and the
6136 target of the branch. */
6137 if (nops_for_sequence (2, 0, history + 1, ip, history) > 0)
6138 return FALSE;
6139
6140 /* If the branch reads a register that the previous
6141 instruction sets, we can not swap. */
6142 gpr_read = gpr_read_mask (ip);
6143 prev_gpr_write = gpr_write_mask (&history[0]);
6144 if (gpr_read & prev_gpr_write)
6145 return FALSE;
6146
6147 /* If the branch writes a register that the previous
6148 instruction sets, we can not swap. */
6149 gpr_write = gpr_write_mask (ip);
6150 if (gpr_write & prev_gpr_write)
6151 return FALSE;
6152
6153 /* If the branch writes a register that the previous
6154 instruction reads, we can not swap. */
6155 prev_gpr_read = gpr_read_mask (&history[0]);
6156 if (gpr_write & prev_gpr_read)
6157 return FALSE;
6158
6159 /* If one instruction sets a condition code and the
6160 other one uses a condition code, we can not swap. */
6161 pinfo = ip->insn_mo->pinfo;
6162 if ((pinfo & INSN_READ_COND_CODE)
6163 && (prev_pinfo & INSN_WRITE_COND_CODE))
6164 return FALSE;
6165 if ((pinfo & INSN_WRITE_COND_CODE)
6166 && (prev_pinfo & INSN_READ_COND_CODE))
6167 return FALSE;
6168
6169 /* If the previous instruction uses the PC, we can not swap. */
2b0c8b40 6170 prev_pinfo2 = history[0].insn_mo->pinfo2;
26545944 6171 if (prev_pinfo2 & INSN2_READ_PC)
2b0c8b40 6172 return FALSE;
a4e06468 6173
df58fc94
RS
6174 /* If the previous instruction has an incorrect size for a fixed
6175 branch delay slot in microMIPS mode, we cannot swap. */
2309ddf2
MR
6176 pinfo2 = ip->insn_mo->pinfo2;
6177 if (mips_opts.micromips
6178 && (pinfo2 & INSN2_BRANCH_DELAY_16BIT)
6179 && insn_length (history) != 2)
6180 return FALSE;
6181 if (mips_opts.micromips
6182 && (pinfo2 & INSN2_BRANCH_DELAY_32BIT)
6183 && insn_length (history) != 4)
6184 return FALSE;
6185
e407c74b
NC
6186 /* On R5900 short loops need to be fixed by inserting a nop in
6187 the branch delay slots.
6188 A short loop can be terminated too early. */
6189 if (mips_opts.arch == CPU_R5900
6190 /* Check if instruction has a parameter, ignore "j $31". */
6191 && (address_expr != NULL)
6192 /* Parameter must be 16 bit. */
6193 && (*reloc_type == BFD_RELOC_16_PCREL_S2)
6194 /* Branch to same segment. */
6195 && (S_GET_SEGMENT(address_expr->X_add_symbol) == now_seg)
6196 /* Branch to same code fragment. */
6197 && (symbol_get_frag(address_expr->X_add_symbol) == frag_now)
6198 /* Can only calculate branch offset if value is known. */
6199 && symbol_constant_p(address_expr->X_add_symbol)
6200 /* Check if branch is really conditional. */
6201 && !((ip->insn_opcode & 0xffff0000) == 0x10000000 /* beq $0,$0 */
6202 || (ip->insn_opcode & 0xffff0000) == 0x04010000 /* bgez $0 */
6203 || (ip->insn_opcode & 0xffff0000) == 0x04110000)) /* bgezal $0 */
6204 {
6205 int distance;
6206 /* Check if loop is shorter than 6 instructions including
6207 branch and delay slot. */
6208 distance = frag_now_fix() - S_GET_VALUE(address_expr->X_add_symbol);
6209 if (distance <= 20)
6210 {
6211 int i;
6212 int rv;
6213
6214 rv = FALSE;
6215 /* When the loop includes branches or jumps,
6216 it is not a short loop. */
6217 for (i = 0; i < (distance / 4); i++)
6218 {
6219 if ((history[i].cleared_p)
6220 || delayed_branch_p(&history[i]))
6221 {
6222 rv = TRUE;
6223 break;
6224 }
6225 }
6226 if (rv == FALSE)
6227 {
6228 /* Insert nop after branch to fix short loop. */
6229 return FALSE;
6230 }
6231 }
6232 }
6233
a4e06468
RS
6234 return TRUE;
6235}
6236
e407c74b
NC
6237/* Decide how we should add IP to the instruction stream.
6238 ADDRESS_EXPR is an operand of the instruction to be used with
6239 RELOC_TYPE. */
a4e06468
RS
6240
6241static enum append_method
e407c74b 6242get_append_method (struct mips_cl_insn *ip, expressionS *address_expr,
26545944 6243 bfd_reloc_code_real_type *reloc_type)
a4e06468 6244{
a4e06468
RS
6245 /* The relaxed version of a macro sequence must be inherently
6246 hazard-free. */
6247 if (mips_relax.sequence == 2)
6248 return APPEND_ADD;
6249
6250 /* We must not dabble with instructions in a ".set norerorder" block. */
6251 if (mips_opts.noreorder)
6252 return APPEND_ADD;
6253
6254 /* Otherwise, it's our responsibility to fill branch delay slots. */
11625dd8 6255 if (delayed_branch_p (ip))
a4e06468 6256 {
e407c74b
NC
6257 if (!branch_likely_p (ip)
6258 && can_swap_branch_p (ip, address_expr, reloc_type))
a4e06468
RS
6259 return APPEND_SWAP;
6260
6261 if (mips_opts.mips16
6262 && ISA_SUPPORTS_MIPS16E
fc76e730 6263 && gpr_read_mask (ip) != 0)
a4e06468
RS
6264 return APPEND_ADD_COMPACT;
6265
6266 return APPEND_ADD_WITH_NOP;
6267 }
6268
a4e06468
RS
6269 return APPEND_ADD;
6270}
6271
ceb94aa5
RS
6272/* IP is a MIPS16 instruction whose opcode we have just changed.
6273 Point IP->insn_mo to the new opcode's definition. */
6274
6275static void
6276find_altered_mips16_opcode (struct mips_cl_insn *ip)
6277{
6278 const struct mips_opcode *mo, *end;
6279
6280 end = &mips16_opcodes[bfd_mips16_num_opcodes];
6281 for (mo = ip->insn_mo; mo < end; mo++)
6282 if ((ip->insn_opcode & mo->mask) == mo->match)
6283 {
6284 ip->insn_mo = mo;
6285 return;
6286 }
6287 abort ();
6288}
6289
df58fc94
RS
6290/* For microMIPS macros, we need to generate a local number label
6291 as the target of branches. */
6292#define MICROMIPS_LABEL_CHAR '\037'
6293static unsigned long micromips_target_label;
6294static char micromips_target_name[32];
6295
6296static char *
6297micromips_label_name (void)
6298{
6299 char *p = micromips_target_name;
6300 char symbol_name_temporary[24];
6301 unsigned long l;
6302 int i;
6303
6304 if (*p)
6305 return p;
6306
6307 i = 0;
6308 l = micromips_target_label;
6309#ifdef LOCAL_LABEL_PREFIX
6310 *p++ = LOCAL_LABEL_PREFIX;
6311#endif
6312 *p++ = 'L';
6313 *p++ = MICROMIPS_LABEL_CHAR;
6314 do
6315 {
6316 symbol_name_temporary[i++] = l % 10 + '0';
6317 l /= 10;
6318 }
6319 while (l != 0);
6320 while (i > 0)
6321 *p++ = symbol_name_temporary[--i];
6322 *p = '\0';
6323
6324 return micromips_target_name;
6325}
6326
6327static void
6328micromips_label_expr (expressionS *label_expr)
6329{
6330 label_expr->X_op = O_symbol;
6331 label_expr->X_add_symbol = symbol_find_or_make (micromips_label_name ());
6332 label_expr->X_add_number = 0;
6333}
6334
6335static void
6336micromips_label_inc (void)
6337{
6338 micromips_target_label++;
6339 *micromips_target_name = '\0';
6340}
6341
6342static void
6343micromips_add_label (void)
6344{
6345 symbolS *s;
6346
6347 s = colon (micromips_label_name ());
6348 micromips_label_inc ();
f3ded42a 6349 S_SET_OTHER (s, ELF_ST_SET_MICROMIPS (S_GET_OTHER (s)));
df58fc94
RS
6350}
6351
6352/* If assembling microMIPS code, then return the microMIPS reloc
6353 corresponding to the requested one if any. Otherwise return
6354 the reloc unchanged. */
6355
6356static bfd_reloc_code_real_type
6357micromips_map_reloc (bfd_reloc_code_real_type reloc)
6358{
6359 static const bfd_reloc_code_real_type relocs[][2] =
6360 {
6361 /* Keep sorted incrementally by the left-hand key. */
6362 { BFD_RELOC_16_PCREL_S2, BFD_RELOC_MICROMIPS_16_PCREL_S1 },
6363 { BFD_RELOC_GPREL16, BFD_RELOC_MICROMIPS_GPREL16 },
6364 { BFD_RELOC_MIPS_JMP, BFD_RELOC_MICROMIPS_JMP },
6365 { BFD_RELOC_HI16, BFD_RELOC_MICROMIPS_HI16 },
6366 { BFD_RELOC_HI16_S, BFD_RELOC_MICROMIPS_HI16_S },
6367 { BFD_RELOC_LO16, BFD_RELOC_MICROMIPS_LO16 },
6368 { BFD_RELOC_MIPS_LITERAL, BFD_RELOC_MICROMIPS_LITERAL },
6369 { BFD_RELOC_MIPS_GOT16, BFD_RELOC_MICROMIPS_GOT16 },
6370 { BFD_RELOC_MIPS_CALL16, BFD_RELOC_MICROMIPS_CALL16 },
6371 { BFD_RELOC_MIPS_GOT_HI16, BFD_RELOC_MICROMIPS_GOT_HI16 },
6372 { BFD_RELOC_MIPS_GOT_LO16, BFD_RELOC_MICROMIPS_GOT_LO16 },
6373 { BFD_RELOC_MIPS_CALL_HI16, BFD_RELOC_MICROMIPS_CALL_HI16 },
6374 { BFD_RELOC_MIPS_CALL_LO16, BFD_RELOC_MICROMIPS_CALL_LO16 },
6375 { BFD_RELOC_MIPS_SUB, BFD_RELOC_MICROMIPS_SUB },
6376 { BFD_RELOC_MIPS_GOT_PAGE, BFD_RELOC_MICROMIPS_GOT_PAGE },
6377 { BFD_RELOC_MIPS_GOT_OFST, BFD_RELOC_MICROMIPS_GOT_OFST },
6378 { BFD_RELOC_MIPS_GOT_DISP, BFD_RELOC_MICROMIPS_GOT_DISP },
6379 { BFD_RELOC_MIPS_HIGHEST, BFD_RELOC_MICROMIPS_HIGHEST },
6380 { BFD_RELOC_MIPS_HIGHER, BFD_RELOC_MICROMIPS_HIGHER },
6381 { BFD_RELOC_MIPS_SCN_DISP, BFD_RELOC_MICROMIPS_SCN_DISP },
6382 { BFD_RELOC_MIPS_TLS_GD, BFD_RELOC_MICROMIPS_TLS_GD },
6383 { BFD_RELOC_MIPS_TLS_LDM, BFD_RELOC_MICROMIPS_TLS_LDM },
6384 { BFD_RELOC_MIPS_TLS_DTPREL_HI16, BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16 },
6385 { BFD_RELOC_MIPS_TLS_DTPREL_LO16, BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16 },
6386 { BFD_RELOC_MIPS_TLS_GOTTPREL, BFD_RELOC_MICROMIPS_TLS_GOTTPREL },
6387 { BFD_RELOC_MIPS_TLS_TPREL_HI16, BFD_RELOC_MICROMIPS_TLS_TPREL_HI16 },
6388 { BFD_RELOC_MIPS_TLS_TPREL_LO16, BFD_RELOC_MICROMIPS_TLS_TPREL_LO16 }
6389 };
6390 bfd_reloc_code_real_type r;
6391 size_t i;
6392
6393 if (!mips_opts.micromips)
6394 return reloc;
6395 for (i = 0; i < ARRAY_SIZE (relocs); i++)
6396 {
6397 r = relocs[i][0];
6398 if (r > reloc)
6399 return reloc;
6400 if (r == reloc)
6401 return relocs[i][1];
6402 }
6403 return reloc;
6404}
6405
b886a2ab
RS
6406/* Try to resolve relocation RELOC against constant OPERAND at assembly time.
6407 Return true on success, storing the resolved value in RESULT. */
6408
6409static bfd_boolean
6410calculate_reloc (bfd_reloc_code_real_type reloc, offsetT operand,
6411 offsetT *result)
6412{
6413 switch (reloc)
6414 {
6415 case BFD_RELOC_MIPS_HIGHEST:
6416 case BFD_RELOC_MICROMIPS_HIGHEST:
6417 *result = ((operand + 0x800080008000ull) >> 48) & 0xffff;
6418 return TRUE;
6419
6420 case BFD_RELOC_MIPS_HIGHER:
6421 case BFD_RELOC_MICROMIPS_HIGHER:
6422 *result = ((operand + 0x80008000ull) >> 32) & 0xffff;
6423 return TRUE;
6424
6425 case BFD_RELOC_HI16_S:
6426 case BFD_RELOC_MICROMIPS_HI16_S:
6427 case BFD_RELOC_MIPS16_HI16_S:
6428 *result = ((operand + 0x8000) >> 16) & 0xffff;
6429 return TRUE;
6430
6431 case BFD_RELOC_HI16:
6432 case BFD_RELOC_MICROMIPS_HI16:
6433 case BFD_RELOC_MIPS16_HI16:
6434 *result = (operand >> 16) & 0xffff;
6435 return TRUE;
6436
6437 case BFD_RELOC_LO16:
6438 case BFD_RELOC_MICROMIPS_LO16:
6439 case BFD_RELOC_MIPS16_LO16:
6440 *result = operand & 0xffff;
6441 return TRUE;
6442
6443 case BFD_RELOC_UNUSED:
6444 *result = operand;
6445 return TRUE;
6446
6447 default:
6448 return FALSE;
6449 }
6450}
6451
71400594
RS
6452/* Output an instruction. IP is the instruction information.
6453 ADDRESS_EXPR is an operand of the instruction to be used with
df58fc94
RS
6454 RELOC_TYPE. EXPANSIONP is true if the instruction is part of
6455 a macro expansion. */
71400594
RS
6456
6457static void
6458append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
df58fc94 6459 bfd_reloc_code_real_type *reloc_type, bfd_boolean expansionp)
71400594 6460{
14fe068b 6461 unsigned long prev_pinfo2, pinfo;
71400594 6462 bfd_boolean relaxed_branch = FALSE;
a4e06468 6463 enum append_method method;
2309ddf2 6464 bfd_boolean relax32;
2b0c8b40 6465 int branch_disp;
71400594 6466
2309ddf2 6467 if (mips_fix_loongson2f && !HAVE_CODE_COMPRESSION)
c67a084a
NC
6468 fix_loongson2f (ip);
6469
738f4d98 6470 file_ase_mips16 |= mips_opts.mips16;
df58fc94 6471 file_ase_micromips |= mips_opts.micromips;
738f4d98 6472
df58fc94 6473 prev_pinfo2 = history[0].insn_mo->pinfo2;
71400594 6474 pinfo = ip->insn_mo->pinfo;
df58fc94
RS
6475
6476 if (mips_opts.micromips
6477 && !expansionp
6478 && (((prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0
6479 && micromips_insn_length (ip->insn_mo) != 2)
6480 || ((prev_pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0
6481 && micromips_insn_length (ip->insn_mo) != 4)))
1661c76c 6482 as_warn (_("wrong size instruction in a %u-bit branch delay slot"),
df58fc94 6483 (prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 ? 16 : 32);
71400594 6484
15be625d
CM
6485 if (address_expr == NULL)
6486 ip->complete_p = 1;
b886a2ab
RS
6487 else if (reloc_type[0] <= BFD_RELOC_UNUSED
6488 && reloc_type[1] == BFD_RELOC_UNUSED
6489 && reloc_type[2] == BFD_RELOC_UNUSED
15be625d
CM
6490 && address_expr->X_op == O_constant)
6491 {
15be625d
CM
6492 switch (*reloc_type)
6493 {
15be625d 6494 case BFD_RELOC_MIPS_JMP:
df58fc94
RS
6495 {
6496 int shift;
6497
6498 shift = mips_opts.micromips ? 1 : 2;
6499 if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0)
6500 as_bad (_("jump to misaligned address (0x%lx)"),
6501 (unsigned long) address_expr->X_add_number);
6502 ip->insn_opcode |= ((address_expr->X_add_number >> shift)
6503 & 0x3ffffff);
335574df 6504 ip->complete_p = 1;
df58fc94 6505 }
15be625d
CM
6506 break;
6507
6508 case BFD_RELOC_MIPS16_JMP:
6509 if ((address_expr->X_add_number & 3) != 0)
6510 as_bad (_("jump to misaligned address (0x%lx)"),
6511 (unsigned long) address_expr->X_add_number);
6512 ip->insn_opcode |=
6513 (((address_expr->X_add_number & 0x7c0000) << 3)
6514 | ((address_expr->X_add_number & 0xf800000) >> 7)
6515 | ((address_expr->X_add_number & 0x3fffc) >> 2));
335574df 6516 ip->complete_p = 1;
15be625d
CM
6517 break;
6518
6519 case BFD_RELOC_16_PCREL_S2:
df58fc94
RS
6520 {
6521 int shift;
6522
6523 shift = mips_opts.micromips ? 1 : 2;
6524 if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0)
6525 as_bad (_("branch to misaligned address (0x%lx)"),
6526 (unsigned long) address_expr->X_add_number);
6527 if (!mips_relax_branch)
6528 {
6529 if ((address_expr->X_add_number + (1 << (shift + 15)))
6530 & ~((1 << (shift + 16)) - 1))
6531 as_bad (_("branch address range overflow (0x%lx)"),
6532 (unsigned long) address_expr->X_add_number);
6533 ip->insn_opcode |= ((address_expr->X_add_number >> shift)
6534 & 0xffff);
6535 }
df58fc94 6536 }
15be625d
CM
6537 break;
6538
6539 default:
b886a2ab
RS
6540 {
6541 offsetT value;
6542
6543 if (calculate_reloc (*reloc_type, address_expr->X_add_number,
6544 &value))
6545 {
6546 ip->insn_opcode |= value & 0xffff;
6547 ip->complete_p = 1;
6548 }
6549 }
6550 break;
6551 }
15be625d
CM
6552 }
6553
71400594
RS
6554 if (mips_relax.sequence != 2 && !mips_opts.noreorder)
6555 {
6556 /* There are a lot of optimizations we could do that we don't.
6557 In particular, we do not, in general, reorder instructions.
6558 If you use gcc with optimization, it will reorder
6559 instructions and generally do much more optimization then we
6560 do here; repeating all that work in the assembler would only
6561 benefit hand written assembly code, and does not seem worth
6562 it. */
6563 int nops = (mips_optimize == 0
932d1a1b
RS
6564 ? nops_for_insn (0, history, NULL)
6565 : nops_for_insn_or_target (0, history, ip));
71400594 6566 if (nops > 0)
252b5132
RH
6567 {
6568 fragS *old_frag;
6569 unsigned long old_frag_offset;
6570 int i;
252b5132
RH
6571
6572 old_frag = frag_now;
6573 old_frag_offset = frag_now_fix ();
6574
6575 for (i = 0; i < nops; i++)
14fe068b
RS
6576 add_fixed_insn (NOP_INSN);
6577 insert_into_history (0, nops, NOP_INSN);
252b5132
RH
6578
6579 if (listing)
6580 {
6581 listing_prev_line ();
6582 /* We may be at the start of a variant frag. In case we
6583 are, make sure there is enough space for the frag
6584 after the frags created by listing_prev_line. The
6585 argument to frag_grow here must be at least as large
6586 as the argument to all other calls to frag_grow in
6587 this file. We don't have to worry about being in the
6588 middle of a variant frag, because the variants insert
6589 all needed nop instructions themselves. */
6590 frag_grow (40);
6591 }
6592
462427c4 6593 mips_move_text_labels ();
252b5132
RH
6594
6595#ifndef NO_ECOFF_DEBUGGING
6596 if (ECOFF_DEBUGGING)
6597 ecoff_fix_loc (old_frag, old_frag_offset);
6598#endif
6599 }
71400594
RS
6600 }
6601 else if (mips_relax.sequence != 2 && prev_nop_frag != NULL)
6602 {
932d1a1b
RS
6603 int nops;
6604
6605 /* Work out how many nops in prev_nop_frag are needed by IP,
6606 ignoring hazards generated by the first prev_nop_frag_since
6607 instructions. */
6608 nops = nops_for_insn_or_target (prev_nop_frag_since, history, ip);
9c2799c2 6609 gas_assert (nops <= prev_nop_frag_holds);
252b5132 6610
71400594
RS
6611 /* Enforce NOPS as a minimum. */
6612 if (nops > prev_nop_frag_required)
6613 prev_nop_frag_required = nops;
252b5132 6614
71400594
RS
6615 if (prev_nop_frag_holds == prev_nop_frag_required)
6616 {
6617 /* Settle for the current number of nops. Update the history
6618 accordingly (for the benefit of any future .set reorder code). */
6619 prev_nop_frag = NULL;
6620 insert_into_history (prev_nop_frag_since,
6621 prev_nop_frag_holds, NOP_INSN);
6622 }
6623 else
6624 {
6625 /* Allow this instruction to replace one of the nops that was
6626 tentatively added to prev_nop_frag. */
df58fc94 6627 prev_nop_frag->fr_fix -= NOP_INSN_SIZE;
71400594
RS
6628 prev_nop_frag_holds--;
6629 prev_nop_frag_since++;
252b5132
RH
6630 }
6631 }
6632
e407c74b 6633 method = get_append_method (ip, address_expr, reloc_type);
2b0c8b40 6634 branch_disp = method == APPEND_SWAP ? insn_length (history) : 0;
a4e06468 6635
e410add4
RS
6636 dwarf2_emit_insn (0);
6637 /* We want MIPS16 and microMIPS debug info to use ISA-encoded addresses,
6638 so "move" the instruction address accordingly.
6639
6640 Also, it doesn't seem appropriate for the assembler to reorder .loc
6641 entries. If this instruction is a branch that we are going to swap
6642 with the previous instruction, the two instructions should be
6643 treated as a unit, and the debug information for both instructions
6644 should refer to the start of the branch sequence. Using the
6645 current position is certainly wrong when swapping a 32-bit branch
6646 and a 16-bit delay slot, since the current position would then be
6647 in the middle of a branch. */
6648 dwarf2_move_insn ((HAVE_CODE_COMPRESSION ? 1 : 0) - branch_disp);
58e2ea4d 6649
df58fc94
RS
6650 relax32 = (mips_relax_branch
6651 /* Don't try branch relaxation within .set nomacro, or within
6652 .set noat if we use $at for PIC computations. If it turns
6653 out that the branch was out-of-range, we'll get an error. */
6654 && !mips_opts.warn_about_macros
6655 && (mips_opts.at || mips_pic == NO_PIC)
3bf0dbfb
MR
6656 /* Don't relax BPOSGE32/64 or BC1ANY2T/F and BC1ANY4T/F
6657 as they have no complementing branches. */
6658 && !(ip->insn_mo->ase & (ASE_MIPS3D | ASE_DSP64 | ASE_DSP)));
df58fc94
RS
6659
6660 if (!HAVE_CODE_COMPRESSION
6661 && address_expr
6662 && relax32
0b25d3e6 6663 && *reloc_type == BFD_RELOC_16_PCREL_S2
11625dd8 6664 && delayed_branch_p (ip))
4a6a3df4 6665 {
895921c9 6666 relaxed_branch = TRUE;
1e915849
RS
6667 add_relaxed_insn (ip, (relaxed_branch_length
6668 (NULL, NULL,
11625dd8
RS
6669 uncond_branch_p (ip) ? -1
6670 : branch_likely_p (ip) ? 1
1e915849
RS
6671 : 0)), 4,
6672 RELAX_BRANCH_ENCODE
66b3e8da 6673 (AT,
11625dd8
RS
6674 uncond_branch_p (ip),
6675 branch_likely_p (ip),
1e915849
RS
6676 pinfo & INSN_WRITE_GPR_31,
6677 0),
6678 address_expr->X_add_symbol,
6679 address_expr->X_add_number);
4a6a3df4
AO
6680 *reloc_type = BFD_RELOC_UNUSED;
6681 }
df58fc94
RS
6682 else if (mips_opts.micromips
6683 && address_expr
6684 && ((relax32 && *reloc_type == BFD_RELOC_16_PCREL_S2)
6685 || *reloc_type > BFD_RELOC_UNUSED)
40209cad
MR
6686 && (delayed_branch_p (ip) || compact_branch_p (ip))
6687 /* Don't try branch relaxation when users specify
6688 16-bit/32-bit instructions. */
6689 && !forced_insn_length)
df58fc94
RS
6690 {
6691 bfd_boolean relax16 = *reloc_type > BFD_RELOC_UNUSED;
6692 int type = relax16 ? *reloc_type - BFD_RELOC_UNUSED : 0;
11625dd8
RS
6693 int uncond = uncond_branch_p (ip) ? -1 : 0;
6694 int compact = compact_branch_p (ip);
df58fc94
RS
6695 int al = pinfo & INSN_WRITE_GPR_31;
6696 int length32;
6697
6698 gas_assert (address_expr != NULL);
6699 gas_assert (!mips_relax.sequence);
6700
2b0c8b40 6701 relaxed_branch = TRUE;
df58fc94
RS
6702 length32 = relaxed_micromips_32bit_branch_length (NULL, NULL, uncond);
6703 add_relaxed_insn (ip, relax32 ? length32 : 4, relax16 ? 2 : 4,
40209cad
MR
6704 RELAX_MICROMIPS_ENCODE (type, AT, uncond, compact, al,
6705 relax32, 0, 0),
df58fc94
RS
6706 address_expr->X_add_symbol,
6707 address_expr->X_add_number);
6708 *reloc_type = BFD_RELOC_UNUSED;
6709 }
6710 else if (mips_opts.mips16 && *reloc_type > BFD_RELOC_UNUSED)
252b5132
RH
6711 {
6712 /* We need to set up a variant frag. */
df58fc94 6713 gas_assert (address_expr != NULL);
1e915849
RS
6714 add_relaxed_insn (ip, 4, 0,
6715 RELAX_MIPS16_ENCODE
6716 (*reloc_type - BFD_RELOC_UNUSED,
df58fc94 6717 forced_insn_length == 2, forced_insn_length == 4,
11625dd8 6718 delayed_branch_p (&history[0]),
1e915849
RS
6719 history[0].mips16_absolute_jump_p),
6720 make_expr_symbol (address_expr), 0);
252b5132 6721 }
5c04167a 6722 else if (mips_opts.mips16 && insn_length (ip) == 2)
9497f5ac 6723 {
11625dd8 6724 if (!delayed_branch_p (ip))
b8ee1a6e
DU
6725 /* Make sure there is enough room to swap this instruction with
6726 a following jump instruction. */
6727 frag_grow (6);
1e915849 6728 add_fixed_insn (ip);
252b5132
RH
6729 }
6730 else
6731 {
6732 if (mips_opts.mips16
6733 && mips_opts.noreorder
11625dd8 6734 && delayed_branch_p (&history[0]))
252b5132
RH
6735 as_warn (_("extended instruction in delay slot"));
6736
4d7206a2
RS
6737 if (mips_relax.sequence)
6738 {
6739 /* If we've reached the end of this frag, turn it into a variant
6740 frag and record the information for the instructions we've
6741 written so far. */
6742 if (frag_room () < 4)
6743 relax_close_frag ();
df58fc94 6744 mips_relax.sizes[mips_relax.sequence - 1] += insn_length (ip);
4d7206a2
RS
6745 }
6746
584892a6 6747 if (mips_relax.sequence != 2)
df58fc94
RS
6748 {
6749 if (mips_macro_warning.first_insn_sizes[0] == 0)
6750 mips_macro_warning.first_insn_sizes[0] = insn_length (ip);
6751 mips_macro_warning.sizes[0] += insn_length (ip);
6752 mips_macro_warning.insns[0]++;
6753 }
584892a6 6754 if (mips_relax.sequence != 1)
df58fc94
RS
6755 {
6756 if (mips_macro_warning.first_insn_sizes[1] == 0)
6757 mips_macro_warning.first_insn_sizes[1] = insn_length (ip);
6758 mips_macro_warning.sizes[1] += insn_length (ip);
6759 mips_macro_warning.insns[1]++;
6760 }
584892a6 6761
1e915849
RS
6762 if (mips_opts.mips16)
6763 {
6764 ip->fixed_p = 1;
6765 ip->mips16_absolute_jump_p = (*reloc_type == BFD_RELOC_MIPS16_JMP);
6766 }
6767 add_fixed_insn (ip);
252b5132
RH
6768 }
6769
9fe77896 6770 if (!ip->complete_p && *reloc_type < BFD_RELOC_UNUSED)
252b5132 6771 {
df58fc94 6772 bfd_reloc_code_real_type final_type[3];
2309ddf2 6773 reloc_howto_type *howto0;
9fe77896
RS
6774 reloc_howto_type *howto;
6775 int i;
34ce925e 6776
df58fc94
RS
6777 /* Perform any necessary conversion to microMIPS relocations
6778 and find out how many relocations there actually are. */
6779 for (i = 0; i < 3 && reloc_type[i] != BFD_RELOC_UNUSED; i++)
6780 final_type[i] = micromips_map_reloc (reloc_type[i]);
6781
9fe77896
RS
6782 /* In a compound relocation, it is the final (outermost)
6783 operator that determines the relocated field. */
2309ddf2 6784 howto = howto0 = bfd_reloc_type_lookup (stdoutput, final_type[i - 1]);
e8044f35
RS
6785 if (!howto)
6786 abort ();
2309ddf2
MR
6787
6788 if (i > 1)
6789 howto0 = bfd_reloc_type_lookup (stdoutput, final_type[0]);
9fe77896
RS
6790 ip->fixp[0] = fix_new_exp (ip->frag, ip->where,
6791 bfd_get_reloc_size (howto),
6792 address_expr,
2309ddf2
MR
6793 howto0 && howto0->pc_relative,
6794 final_type[0]);
9fe77896
RS
6795
6796 /* Tag symbols that have a R_MIPS16_26 relocation against them. */
2309ddf2 6797 if (final_type[0] == BFD_RELOC_MIPS16_JMP && ip->fixp[0]->fx_addsy)
9fe77896
RS
6798 *symbol_get_tc (ip->fixp[0]->fx_addsy) = 1;
6799
6800 /* These relocations can have an addend that won't fit in
6801 4 octets for 64bit assembly. */
6802 if (HAVE_64BIT_GPRS
6803 && ! howto->partial_inplace
6804 && (reloc_type[0] == BFD_RELOC_16
6805 || reloc_type[0] == BFD_RELOC_32
6806 || reloc_type[0] == BFD_RELOC_MIPS_JMP
6807 || reloc_type[0] == BFD_RELOC_GPREL16
6808 || reloc_type[0] == BFD_RELOC_MIPS_LITERAL
6809 || reloc_type[0] == BFD_RELOC_GPREL32
6810 || reloc_type[0] == BFD_RELOC_64
6811 || reloc_type[0] == BFD_RELOC_CTOR
6812 || reloc_type[0] == BFD_RELOC_MIPS_SUB
6813 || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST
6814 || reloc_type[0] == BFD_RELOC_MIPS_HIGHER
6815 || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP
6816 || reloc_type[0] == BFD_RELOC_MIPS_REL16
6817 || reloc_type[0] == BFD_RELOC_MIPS_RELGOT
6818 || reloc_type[0] == BFD_RELOC_MIPS16_GPREL
6819 || hi16_reloc_p (reloc_type[0])
6820 || lo16_reloc_p (reloc_type[0])))
6821 ip->fixp[0]->fx_no_overflow = 1;
6822
ddaf2c41
MR
6823 /* These relocations can have an addend that won't fit in 2 octets. */
6824 if (reloc_type[0] == BFD_RELOC_MICROMIPS_7_PCREL_S1
6825 || reloc_type[0] == BFD_RELOC_MICROMIPS_10_PCREL_S1)
6826 ip->fixp[0]->fx_no_overflow = 1;
6827
9fe77896
RS
6828 if (mips_relax.sequence)
6829 {
6830 if (mips_relax.first_fixup == 0)
6831 mips_relax.first_fixup = ip->fixp[0];
6832 }
6833 else if (reloc_needs_lo_p (*reloc_type))
6834 {
6835 struct mips_hi_fixup *hi_fixup;
6836
6837 /* Reuse the last entry if it already has a matching %lo. */
6838 hi_fixup = mips_hi_fixup_list;
6839 if (hi_fixup == 0
6840 || !fixup_has_matching_lo_p (hi_fixup->fixp))
4d7206a2 6841 {
9fe77896
RS
6842 hi_fixup = ((struct mips_hi_fixup *)
6843 xmalloc (sizeof (struct mips_hi_fixup)));
6844 hi_fixup->next = mips_hi_fixup_list;
6845 mips_hi_fixup_list = hi_fixup;
4d7206a2 6846 }
9fe77896
RS
6847 hi_fixup->fixp = ip->fixp[0];
6848 hi_fixup->seg = now_seg;
6849 }
252b5132 6850
9fe77896
RS
6851 /* Add fixups for the second and third relocations, if given.
6852 Note that the ABI allows the second relocation to be
6853 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
6854 moment we only use RSS_UNDEF, but we could add support
6855 for the others if it ever becomes necessary. */
6856 for (i = 1; i < 3; i++)
6857 if (reloc_type[i] != BFD_RELOC_UNUSED)
6858 {
6859 ip->fixp[i] = fix_new (ip->frag, ip->where,
6860 ip->fixp[0]->fx_size, NULL, 0,
df58fc94 6861 FALSE, final_type[i]);
f6688943 6862
9fe77896
RS
6863 /* Use fx_tcbit to mark compound relocs. */
6864 ip->fixp[0]->fx_tcbit = 1;
6865 ip->fixp[i]->fx_tcbit = 1;
6866 }
252b5132 6867 }
1e915849 6868 install_insn (ip);
252b5132
RH
6869
6870 /* Update the register mask information. */
4c260379
RS
6871 mips_gprmask |= gpr_read_mask (ip) | gpr_write_mask (ip);
6872 mips_cprmask[1] |= fpr_read_mask (ip) | fpr_write_mask (ip);
252b5132 6873
a4e06468 6874 switch (method)
252b5132 6875 {
a4e06468
RS
6876 case APPEND_ADD:
6877 insert_into_history (0, 1, ip);
6878 break;
6879
6880 case APPEND_ADD_WITH_NOP:
14fe068b
RS
6881 {
6882 struct mips_cl_insn *nop;
6883
6884 insert_into_history (0, 1, ip);
6885 nop = get_delay_slot_nop (ip);
6886 add_fixed_insn (nop);
6887 insert_into_history (0, 1, nop);
6888 if (mips_relax.sequence)
6889 mips_relax.sizes[mips_relax.sequence - 1] += insn_length (nop);
6890 }
a4e06468
RS
6891 break;
6892
6893 case APPEND_ADD_COMPACT:
6894 /* Convert MIPS16 jr/jalr into a "compact" jump. */
6895 gas_assert (mips_opts.mips16);
6896 ip->insn_opcode |= 0x0080;
6897 find_altered_mips16_opcode (ip);
6898 install_insn (ip);
6899 insert_into_history (0, 1, ip);
6900 break;
6901
6902 case APPEND_SWAP:
6903 {
6904 struct mips_cl_insn delay = history[0];
6905 if (mips_opts.mips16)
6906 {
6907 know (delay.frag == ip->frag);
6908 move_insn (ip, delay.frag, delay.where);
6909 move_insn (&delay, ip->frag, ip->where + insn_length (ip));
6910 }
464ab0e5 6911 else if (relaxed_branch || delay.frag != ip->frag)
a4e06468
RS
6912 {
6913 /* Add the delay slot instruction to the end of the
6914 current frag and shrink the fixed part of the
6915 original frag. If the branch occupies the tail of
6916 the latter, move it backwards to cover the gap. */
2b0c8b40 6917 delay.frag->fr_fix -= branch_disp;
a4e06468 6918 if (delay.frag == ip->frag)
2b0c8b40 6919 move_insn (ip, ip->frag, ip->where - branch_disp);
a4e06468
RS
6920 add_fixed_insn (&delay);
6921 }
6922 else
6923 {
2b0c8b40
MR
6924 move_insn (&delay, ip->frag,
6925 ip->where - branch_disp + insn_length (ip));
a4e06468
RS
6926 move_insn (ip, history[0].frag, history[0].where);
6927 }
6928 history[0] = *ip;
6929 delay.fixed_p = 1;
6930 insert_into_history (0, 1, &delay);
6931 }
6932 break;
252b5132
RH
6933 }
6934
13408f1e 6935 /* If we have just completed an unconditional branch, clear the history. */
11625dd8
RS
6936 if ((delayed_branch_p (&history[1]) && uncond_branch_p (&history[1]))
6937 || (compact_branch_p (&history[0]) && uncond_branch_p (&history[0])))
e407c74b
NC
6938 {
6939 unsigned int i;
6940
79850f26 6941 mips_no_prev_insn ();
13408f1e 6942
e407c74b 6943 for (i = 0; i < ARRAY_SIZE (history); i++)
79850f26 6944 history[i].cleared_p = 1;
e407c74b
NC
6945 }
6946
df58fc94
RS
6947 /* We need to emit a label at the end of branch-likely macros. */
6948 if (emit_branch_likely_macro)
6949 {
6950 emit_branch_likely_macro = FALSE;
6951 micromips_add_label ();
6952 }
6953
252b5132
RH
6954 /* We just output an insn, so the next one doesn't have a label. */
6955 mips_clear_insn_labels ();
252b5132
RH
6956}
6957
e407c74b
NC
6958/* Forget that there was any previous instruction or label.
6959 When BRANCH is true, the branch history is also flushed. */
252b5132
RH
6960
6961static void
7d10b47d 6962mips_no_prev_insn (void)
252b5132 6963{
7d10b47d
RS
6964 prev_nop_frag = NULL;
6965 insert_into_history (0, ARRAY_SIZE (history), NOP_INSN);
252b5132
RH
6966 mips_clear_insn_labels ();
6967}
6968
7d10b47d
RS
6969/* This function must be called before we emit something other than
6970 instructions. It is like mips_no_prev_insn except that it inserts
6971 any NOPS that might be needed by previous instructions. */
252b5132 6972
7d10b47d
RS
6973void
6974mips_emit_delays (void)
252b5132
RH
6975{
6976 if (! mips_opts.noreorder)
6977 {
932d1a1b 6978 int nops = nops_for_insn (0, history, NULL);
252b5132
RH
6979 if (nops > 0)
6980 {
7d10b47d
RS
6981 while (nops-- > 0)
6982 add_fixed_insn (NOP_INSN);
462427c4 6983 mips_move_text_labels ();
7d10b47d
RS
6984 }
6985 }
6986 mips_no_prev_insn ();
6987}
6988
6989/* Start a (possibly nested) noreorder block. */
6990
6991static void
6992start_noreorder (void)
6993{
6994 if (mips_opts.noreorder == 0)
6995 {
6996 unsigned int i;
6997 int nops;
6998
6999 /* None of the instructions before the .set noreorder can be moved. */
7000 for (i = 0; i < ARRAY_SIZE (history); i++)
7001 history[i].fixed_p = 1;
7002
7003 /* Insert any nops that might be needed between the .set noreorder
7004 block and the previous instructions. We will later remove any
7005 nops that turn out not to be needed. */
932d1a1b 7006 nops = nops_for_insn (0, history, NULL);
7d10b47d
RS
7007 if (nops > 0)
7008 {
7009 if (mips_optimize != 0)
252b5132
RH
7010 {
7011 /* Record the frag which holds the nop instructions, so
7012 that we can remove them if we don't need them. */
df58fc94 7013 frag_grow (nops * NOP_INSN_SIZE);
252b5132
RH
7014 prev_nop_frag = frag_now;
7015 prev_nop_frag_holds = nops;
7016 prev_nop_frag_required = 0;
7017 prev_nop_frag_since = 0;
7018 }
7019
7020 for (; nops > 0; --nops)
1e915849 7021 add_fixed_insn (NOP_INSN);
252b5132 7022
7d10b47d
RS
7023 /* Move on to a new frag, so that it is safe to simply
7024 decrease the size of prev_nop_frag. */
7025 frag_wane (frag_now);
7026 frag_new (0);
462427c4 7027 mips_move_text_labels ();
252b5132 7028 }
df58fc94 7029 mips_mark_labels ();
7d10b47d 7030 mips_clear_insn_labels ();
252b5132 7031 }
7d10b47d
RS
7032 mips_opts.noreorder++;
7033 mips_any_noreorder = 1;
7034}
252b5132 7035
7d10b47d 7036/* End a nested noreorder block. */
252b5132 7037
7d10b47d
RS
7038static void
7039end_noreorder (void)
7040{
7041 mips_opts.noreorder--;
7042 if (mips_opts.noreorder == 0 && prev_nop_frag != NULL)
7043 {
7044 /* Commit to inserting prev_nop_frag_required nops and go back to
7045 handling nop insertion the .set reorder way. */
7046 prev_nop_frag->fr_fix -= ((prev_nop_frag_holds - prev_nop_frag_required)
df58fc94 7047 * NOP_INSN_SIZE);
7d10b47d
RS
7048 insert_into_history (prev_nop_frag_since,
7049 prev_nop_frag_required, NOP_INSN);
7050 prev_nop_frag = NULL;
7051 }
252b5132
RH
7052}
7053
97d87491
RS
7054/* Sign-extend 32-bit mode constants that have bit 31 set and all
7055 higher bits unset. */
7056
7057static void
7058normalize_constant_expr (expressionS *ex)
7059{
7060 if (ex->X_op == O_constant
7061 && IS_ZEXT_32BIT_NUM (ex->X_add_number))
7062 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
7063 - 0x80000000);
7064}
7065
7066/* Sign-extend 32-bit mode address offsets that have bit 31 set and
7067 all higher bits unset. */
7068
7069static void
7070normalize_address_expr (expressionS *ex)
7071{
7072 if (((ex->X_op == O_constant && HAVE_32BIT_ADDRESSES)
7073 || (ex->X_op == O_symbol && HAVE_32BIT_SYMBOLS))
7074 && IS_ZEXT_32BIT_NUM (ex->X_add_number))
7075 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
7076 - 0x80000000);
7077}
7078
7079/* Try to match TOKENS against OPCODE, storing the result in INSN.
7080 Return true if the match was successful.
7081
7082 OPCODE_EXTRA is a value that should be ORed into the opcode
7083 (used for VU0 channel suffixes, etc.). MORE_ALTS is true if
7084 there are more alternatives after OPCODE and SOFT_MATCH is
7085 as for mips_arg_info. */
7086
7087static bfd_boolean
7088match_insn (struct mips_cl_insn *insn, const struct mips_opcode *opcode,
7089 struct mips_operand_token *tokens, unsigned int opcode_extra,
60f20e8b 7090 bfd_boolean lax_match, bfd_boolean complete_p)
97d87491
RS
7091{
7092 const char *args;
7093 struct mips_arg_info arg;
7094 const struct mips_operand *operand;
7095 char c;
7096
7097 imm_expr.X_op = O_absent;
97d87491
RS
7098 offset_expr.X_op = O_absent;
7099 offset_reloc[0] = BFD_RELOC_UNUSED;
7100 offset_reloc[1] = BFD_RELOC_UNUSED;
7101 offset_reloc[2] = BFD_RELOC_UNUSED;
7102
7103 create_insn (insn, opcode);
60f20e8b
RS
7104 /* When no opcode suffix is specified, assume ".xyzw". */
7105 if ((opcode->pinfo2 & INSN2_VU0_CHANNEL_SUFFIX) != 0 && opcode_extra == 0)
7106 insn->insn_opcode |= 0xf << mips_vu0_channel_mask.lsb;
7107 else
7108 insn->insn_opcode |= opcode_extra;
97d87491
RS
7109 memset (&arg, 0, sizeof (arg));
7110 arg.insn = insn;
7111 arg.token = tokens;
7112 arg.argnum = 1;
7113 arg.last_regno = ILLEGAL_REG;
7114 arg.dest_regno = ILLEGAL_REG;
60f20e8b 7115 arg.lax_match = lax_match;
97d87491
RS
7116 for (args = opcode->args;; ++args)
7117 {
7118 if (arg.token->type == OT_END)
7119 {
7120 /* Handle unary instructions in which only one operand is given.
7121 The source is then the same as the destination. */
7122 if (arg.opnum == 1 && *args == ',')
7123 {
7124 operand = (mips_opts.micromips
7125 ? decode_micromips_operand (args + 1)
7126 : decode_mips_operand (args + 1));
7127 if (operand && mips_optional_operand_p (operand))
7128 {
7129 arg.token = tokens;
7130 arg.argnum = 1;
7131 continue;
7132 }
7133 }
7134
7135 /* Treat elided base registers as $0. */
7136 if (strcmp (args, "(b)") == 0)
7137 args += 3;
7138
7139 if (args[0] == '+')
7140 switch (args[1])
7141 {
7142 case 'K':
7143 case 'N':
7144 /* The register suffix is optional. */
7145 args += 2;
7146 break;
7147 }
7148
7149 /* Fail the match if there were too few operands. */
7150 if (*args)
7151 return FALSE;
7152
7153 /* Successful match. */
60f20e8b
RS
7154 if (!complete_p)
7155 return TRUE;
e3de51ce 7156 clear_insn_error ();
97d87491
RS
7157 if (arg.dest_regno == arg.last_regno
7158 && strncmp (insn->insn_mo->name, "jalr", 4) == 0)
7159 {
7160 if (arg.opnum == 2)
e3de51ce 7161 set_insn_error
1661c76c 7162 (0, _("source and destination must be different"));
97d87491 7163 else if (arg.last_regno == 31)
e3de51ce 7164 set_insn_error
1661c76c 7165 (0, _("a destination register must be supplied"));
97d87491 7166 }
173d3447
CF
7167 else if (arg.last_regno == 31
7168 && (strncmp (insn->insn_mo->name, "bltzal", 6) == 0
7169 || strncmp (insn->insn_mo->name, "bgezal", 6) == 0))
7170 set_insn_error (0, _("the source register must not be $31"));
97d87491
RS
7171 check_completed_insn (&arg);
7172 return TRUE;
7173 }
7174
7175 /* Fail the match if the line has too many operands. */
7176 if (*args == 0)
7177 return FALSE;
7178
7179 /* Handle characters that need to match exactly. */
7180 if (*args == '(' || *args == ')' || *args == ',')
7181 {
7182 if (match_char (&arg, *args))
7183 continue;
7184 return FALSE;
7185 }
7186 if (*args == '#')
7187 {
7188 ++args;
7189 if (arg.token->type == OT_DOUBLE_CHAR
7190 && arg.token->u.ch == *args)
7191 {
7192 ++arg.token;
7193 continue;
7194 }
7195 return FALSE;
7196 }
7197
7198 /* Handle special macro operands. Work out the properties of
7199 other operands. */
7200 arg.opnum += 1;
97d87491
RS
7201 switch (*args)
7202 {
7203 case '+':
7204 switch (args[1])
7205 {
97d87491
RS
7206 case 'i':
7207 *offset_reloc = BFD_RELOC_MIPS_JMP;
7208 break;
7209 }
7210 break;
7211
97d87491 7212 case 'I':
1a00e612
RS
7213 if (!match_const_int (&arg, &imm_expr.X_add_number))
7214 return FALSE;
7215 imm_expr.X_op = O_constant;
97d87491
RS
7216 if (HAVE_32BIT_GPRS)
7217 normalize_constant_expr (&imm_expr);
7218 continue;
7219
7220 case 'A':
7221 if (arg.token->type == OT_CHAR && arg.token->u.ch == '(')
7222 {
7223 /* Assume that the offset has been elided and that what
7224 we saw was a base register. The match will fail later
7225 if that assumption turns out to be wrong. */
7226 offset_expr.X_op = O_constant;
7227 offset_expr.X_add_number = 0;
7228 }
97d87491 7229 else
1a00e612
RS
7230 {
7231 if (!match_expression (&arg, &offset_expr, offset_reloc))
7232 return FALSE;
7233 normalize_address_expr (&offset_expr);
7234 }
97d87491
RS
7235 continue;
7236
7237 case 'F':
7238 if (!match_float_constant (&arg, &imm_expr, &offset_expr,
7239 8, TRUE))
1a00e612 7240 return FALSE;
97d87491
RS
7241 continue;
7242
7243 case 'L':
7244 if (!match_float_constant (&arg, &imm_expr, &offset_expr,
7245 8, FALSE))
1a00e612 7246 return FALSE;
97d87491
RS
7247 continue;
7248
7249 case 'f':
7250 if (!match_float_constant (&arg, &imm_expr, &offset_expr,
7251 4, TRUE))
1a00e612 7252 return FALSE;
97d87491
RS
7253 continue;
7254
7255 case 'l':
7256 if (!match_float_constant (&arg, &imm_expr, &offset_expr,
7257 4, FALSE))
1a00e612 7258 return FALSE;
97d87491
RS
7259 continue;
7260
97d87491
RS
7261 case 'p':
7262 *offset_reloc = BFD_RELOC_16_PCREL_S2;
7263 break;
7264
7265 case 'a':
7266 *offset_reloc = BFD_RELOC_MIPS_JMP;
7267 break;
7268
7269 case 'm':
7270 gas_assert (mips_opts.micromips);
7271 c = args[1];
7272 switch (c)
7273 {
7274 case 'D':
7275 case 'E':
7276 if (!forced_insn_length)
7277 *offset_reloc = (int) BFD_RELOC_UNUSED + c;
7278 else if (c == 'D')
7279 *offset_reloc = BFD_RELOC_MICROMIPS_10_PCREL_S1;
7280 else
7281 *offset_reloc = BFD_RELOC_MICROMIPS_7_PCREL_S1;
7282 break;
7283 }
7284 break;
7285 }
7286
7287 operand = (mips_opts.micromips
7288 ? decode_micromips_operand (args)
7289 : decode_mips_operand (args));
7290 if (!operand)
7291 abort ();
7292
7293 /* Skip prefixes. */
7294 if (*args == '+' || *args == 'm')
7295 args++;
7296
7297 if (mips_optional_operand_p (operand)
7298 && args[1] == ','
7299 && (arg.token[0].type != OT_REG
7300 || arg.token[1].type == OT_END))
7301 {
7302 /* Assume that the register has been elided and is the
7303 same as the first operand. */
7304 arg.token = tokens;
7305 arg.argnum = 1;
7306 }
7307
7308 if (!match_operand (&arg, operand))
7309 return FALSE;
7310 }
7311}
7312
7313/* Like match_insn, but for MIPS16. */
7314
7315static bfd_boolean
7316match_mips16_insn (struct mips_cl_insn *insn, const struct mips_opcode *opcode,
1a00e612 7317 struct mips_operand_token *tokens)
97d87491
RS
7318{
7319 const char *args;
7320 const struct mips_operand *operand;
7321 const struct mips_operand *ext_operand;
7322 struct mips_arg_info arg;
7323 int relax_char;
7324
7325 create_insn (insn, opcode);
7326 imm_expr.X_op = O_absent;
97d87491
RS
7327 offset_expr.X_op = O_absent;
7328 offset_reloc[0] = BFD_RELOC_UNUSED;
7329 offset_reloc[1] = BFD_RELOC_UNUSED;
7330 offset_reloc[2] = BFD_RELOC_UNUSED;
7331 relax_char = 0;
7332
7333 memset (&arg, 0, sizeof (arg));
7334 arg.insn = insn;
7335 arg.token = tokens;
7336 arg.argnum = 1;
7337 arg.last_regno = ILLEGAL_REG;
7338 arg.dest_regno = ILLEGAL_REG;
97d87491
RS
7339 relax_char = 0;
7340 for (args = opcode->args;; ++args)
7341 {
7342 int c;
7343
7344 if (arg.token->type == OT_END)
7345 {
7346 offsetT value;
7347
7348 /* Handle unary instructions in which only one operand is given.
7349 The source is then the same as the destination. */
7350 if (arg.opnum == 1 && *args == ',')
7351 {
7352 operand = decode_mips16_operand (args[1], FALSE);
7353 if (operand && mips_optional_operand_p (operand))
7354 {
7355 arg.token = tokens;
7356 arg.argnum = 1;
7357 continue;
7358 }
7359 }
7360
7361 /* Fail the match if there were too few operands. */
7362 if (*args)
7363 return FALSE;
7364
7365 /* Successful match. Stuff the immediate value in now, if
7366 we can. */
e3de51ce 7367 clear_insn_error ();
97d87491
RS
7368 if (opcode->pinfo == INSN_MACRO)
7369 {
7370 gas_assert (relax_char == 0 || relax_char == 'p');
7371 gas_assert (*offset_reloc == BFD_RELOC_UNUSED);
7372 }
7373 else if (relax_char
7374 && offset_expr.X_op == O_constant
7375 && calculate_reloc (*offset_reloc,
7376 offset_expr.X_add_number,
7377 &value))
7378 {
7379 mips16_immed (NULL, 0, relax_char, *offset_reloc, value,
7380 forced_insn_length, &insn->insn_opcode);
7381 offset_expr.X_op = O_absent;
7382 *offset_reloc = BFD_RELOC_UNUSED;
7383 }
7384 else if (relax_char && *offset_reloc != BFD_RELOC_UNUSED)
7385 {
7386 if (forced_insn_length == 2)
e3de51ce 7387 set_insn_error (0, _("invalid unextended operand value"));
97d87491
RS
7388 forced_insn_length = 4;
7389 insn->insn_opcode |= MIPS16_EXTEND;
7390 }
7391 else if (relax_char)
7392 *offset_reloc = (int) BFD_RELOC_UNUSED + relax_char;
7393
7394 check_completed_insn (&arg);
7395 return TRUE;
7396 }
7397
7398 /* Fail the match if the line has too many operands. */
7399 if (*args == 0)
7400 return FALSE;
7401
7402 /* Handle characters that need to match exactly. */
7403 if (*args == '(' || *args == ')' || *args == ',')
7404 {
7405 if (match_char (&arg, *args))
7406 continue;
7407 return FALSE;
7408 }
7409
7410 arg.opnum += 1;
7411 c = *args;
7412 switch (c)
7413 {
7414 case 'p':
7415 case 'q':
7416 case 'A':
7417 case 'B':
7418 case 'E':
7419 relax_char = c;
7420 break;
7421
7422 case 'I':
1a00e612
RS
7423 if (!match_const_int (&arg, &imm_expr.X_add_number))
7424 return FALSE;
7425 imm_expr.X_op = O_constant;
97d87491
RS
7426 if (HAVE_32BIT_GPRS)
7427 normalize_constant_expr (&imm_expr);
7428 continue;
7429
7430 case 'a':
7431 case 'i':
7432 *offset_reloc = BFD_RELOC_MIPS16_JMP;
7433 insn->insn_opcode <<= 16;
7434 break;
7435 }
7436
7437 operand = decode_mips16_operand (c, FALSE);
7438 if (!operand)
7439 abort ();
7440
7441 /* '6' is a special case. It is used for BREAK and SDBBP,
7442 whose operands are only meaningful to the software that decodes
7443 them. This means that there is no architectural reason why
7444 they cannot be prefixed by EXTEND, but in practice,
7445 exception handlers will only look at the instruction
7446 itself. We therefore allow '6' to be extended when
7447 disassembling but not when assembling. */
7448 if (operand->type != OP_PCREL && c != '6')
7449 {
7450 ext_operand = decode_mips16_operand (c, TRUE);
7451 if (operand != ext_operand)
7452 {
7453 if (arg.token->type == OT_CHAR && arg.token->u.ch == '(')
7454 {
7455 offset_expr.X_op = O_constant;
7456 offset_expr.X_add_number = 0;
7457 relax_char = c;
7458 continue;
7459 }
7460
7461 /* We need the OT_INTEGER check because some MIPS16
7462 immediate variants are listed before the register ones. */
7463 if (arg.token->type != OT_INTEGER
7464 || !match_expression (&arg, &offset_expr, offset_reloc))
7465 return FALSE;
7466
7467 /* '8' is used for SLTI(U) and has traditionally not
7468 been allowed to take relocation operators. */
7469 if (offset_reloc[0] != BFD_RELOC_UNUSED
7470 && (ext_operand->size != 16 || c == '8'))
7471 return FALSE;
7472
7473 relax_char = c;
7474 continue;
7475 }
7476 }
7477
7478 if (mips_optional_operand_p (operand)
7479 && args[1] == ','
7480 && (arg.token[0].type != OT_REG
7481 || arg.token[1].type == OT_END))
7482 {
7483 /* Assume that the register has been elided and is the
7484 same as the first operand. */
7485 arg.token = tokens;
7486 arg.argnum = 1;
7487 }
7488
7489 if (!match_operand (&arg, operand))
7490 return FALSE;
7491 }
7492}
7493
60f20e8b
RS
7494/* Record that the current instruction is invalid for the current ISA. */
7495
7496static void
7497match_invalid_for_isa (void)
7498{
7499 set_insn_error_ss
1661c76c 7500 (0, _("opcode not supported on this processor: %s (%s)"),
60f20e8b
RS
7501 mips_cpu_info_from_arch (mips_opts.arch)->name,
7502 mips_cpu_info_from_isa (mips_opts.isa)->name);
7503}
7504
7505/* Try to match TOKENS against a series of opcode entries, starting at FIRST.
7506 Return true if a definite match or failure was found, storing any match
7507 in INSN. OPCODE_EXTRA is a value that should be ORed into the opcode
7508 (to handle things like VU0 suffixes). LAX_MATCH is true if we have already
7509 tried and failed to match under normal conditions and now want to try a
7510 more relaxed match. */
7511
7512static bfd_boolean
7513match_insns (struct mips_cl_insn *insn, const struct mips_opcode *first,
7514 const struct mips_opcode *past, struct mips_operand_token *tokens,
7515 int opcode_extra, bfd_boolean lax_match)
7516{
7517 const struct mips_opcode *opcode;
7518 const struct mips_opcode *invalid_delay_slot;
7519 bfd_boolean seen_valid_for_isa, seen_valid_for_size;
7520
7521 /* Search for a match, ignoring alternatives that don't satisfy the
7522 current ISA or forced_length. */
7523 invalid_delay_slot = 0;
7524 seen_valid_for_isa = FALSE;
7525 seen_valid_for_size = FALSE;
7526 opcode = first;
7527 do
7528 {
7529 gas_assert (strcmp (opcode->name, first->name) == 0);
7530 if (is_opcode_valid (opcode))
7531 {
7532 seen_valid_for_isa = TRUE;
7533 if (is_size_valid (opcode))
7534 {
7535 bfd_boolean delay_slot_ok;
7536
7537 seen_valid_for_size = TRUE;
7538 delay_slot_ok = is_delay_slot_valid (opcode);
7539 if (match_insn (insn, opcode, tokens, opcode_extra,
7540 lax_match, delay_slot_ok))
7541 {
7542 if (!delay_slot_ok)
7543 {
7544 if (!invalid_delay_slot)
7545 invalid_delay_slot = opcode;
7546 }
7547 else
7548 return TRUE;
7549 }
7550 }
7551 }
7552 ++opcode;
7553 }
7554 while (opcode < past && strcmp (opcode->name, first->name) == 0);
7555
7556 /* If the only matches we found had the wrong length for the delay slot,
7557 pick the first such match. We'll issue an appropriate warning later. */
7558 if (invalid_delay_slot)
7559 {
7560 if (match_insn (insn, invalid_delay_slot, tokens, opcode_extra,
7561 lax_match, TRUE))
7562 return TRUE;
7563 abort ();
7564 }
7565
7566 /* Handle the case where we didn't try to match an instruction because
7567 all the alternatives were incompatible with the current ISA. */
7568 if (!seen_valid_for_isa)
7569 {
7570 match_invalid_for_isa ();
7571 return TRUE;
7572 }
7573
7574 /* Handle the case where we didn't try to match an instruction because
7575 all the alternatives were of the wrong size. */
7576 if (!seen_valid_for_size)
7577 {
7578 if (mips_opts.insn32)
1661c76c 7579 set_insn_error (0, _("opcode not supported in the `insn32' mode"));
60f20e8b
RS
7580 else
7581 set_insn_error_i
1661c76c 7582 (0, _("unrecognized %d-bit version of microMIPS opcode"),
60f20e8b
RS
7583 8 * forced_insn_length);
7584 return TRUE;
7585 }
7586
7587 return FALSE;
7588}
7589
7590/* Like match_insns, but for MIPS16. */
7591
7592static bfd_boolean
7593match_mips16_insns (struct mips_cl_insn *insn, const struct mips_opcode *first,
7594 struct mips_operand_token *tokens)
7595{
7596 const struct mips_opcode *opcode;
7597 bfd_boolean seen_valid_for_isa;
7598
7599 /* Search for a match, ignoring alternatives that don't satisfy the
7600 current ISA. There are no separate entries for extended forms so
7601 we deal with forced_length later. */
7602 seen_valid_for_isa = FALSE;
7603 opcode = first;
7604 do
7605 {
7606 gas_assert (strcmp (opcode->name, first->name) == 0);
7607 if (is_opcode_valid_16 (opcode))
7608 {
7609 seen_valid_for_isa = TRUE;
7610 if (match_mips16_insn (insn, opcode, tokens))
7611 return TRUE;
7612 }
7613 ++opcode;
7614 }
7615 while (opcode < &mips16_opcodes[bfd_mips16_num_opcodes]
7616 && strcmp (opcode->name, first->name) == 0);
7617
7618 /* Handle the case where we didn't try to match an instruction because
7619 all the alternatives were incompatible with the current ISA. */
7620 if (!seen_valid_for_isa)
7621 {
7622 match_invalid_for_isa ();
7623 return TRUE;
7624 }
7625
7626 return FALSE;
7627}
7628
584892a6
RS
7629/* Set up global variables for the start of a new macro. */
7630
7631static void
7632macro_start (void)
7633{
7634 memset (&mips_macro_warning.sizes, 0, sizeof (mips_macro_warning.sizes));
df58fc94
RS
7635 memset (&mips_macro_warning.first_insn_sizes, 0,
7636 sizeof (mips_macro_warning.first_insn_sizes));
7637 memset (&mips_macro_warning.insns, 0, sizeof (mips_macro_warning.insns));
584892a6 7638 mips_macro_warning.delay_slot_p = (mips_opts.noreorder
11625dd8 7639 && delayed_branch_p (&history[0]));
df58fc94
RS
7640 switch (history[0].insn_mo->pinfo2
7641 & (INSN2_BRANCH_DELAY_32BIT | INSN2_BRANCH_DELAY_16BIT))
7642 {
7643 case INSN2_BRANCH_DELAY_32BIT:
7644 mips_macro_warning.delay_slot_length = 4;
7645 break;
7646 case INSN2_BRANCH_DELAY_16BIT:
7647 mips_macro_warning.delay_slot_length = 2;
7648 break;
7649 default:
7650 mips_macro_warning.delay_slot_length = 0;
7651 break;
7652 }
7653 mips_macro_warning.first_frag = NULL;
584892a6
RS
7654}
7655
df58fc94
RS
7656/* Given that a macro is longer than one instruction or of the wrong size,
7657 return the appropriate warning for it. Return null if no warning is
7658 needed. SUBTYPE is a bitmask of RELAX_DELAY_SLOT, RELAX_DELAY_SLOT_16BIT,
7659 RELAX_DELAY_SLOT_SIZE_FIRST, RELAX_DELAY_SLOT_SIZE_SECOND,
7660 and RELAX_NOMACRO. */
584892a6
RS
7661
7662static const char *
7663macro_warning (relax_substateT subtype)
7664{
7665 if (subtype & RELAX_DELAY_SLOT)
1661c76c 7666 return _("macro instruction expanded into multiple instructions"
584892a6
RS
7667 " in a branch delay slot");
7668 else if (subtype & RELAX_NOMACRO)
1661c76c 7669 return _("macro instruction expanded into multiple instructions");
df58fc94
RS
7670 else if (subtype & (RELAX_DELAY_SLOT_SIZE_FIRST
7671 | RELAX_DELAY_SLOT_SIZE_SECOND))
7672 return ((subtype & RELAX_DELAY_SLOT_16BIT)
1661c76c 7673 ? _("macro instruction expanded into a wrong size instruction"
df58fc94 7674 " in a 16-bit branch delay slot")
1661c76c 7675 : _("macro instruction expanded into a wrong size instruction"
df58fc94 7676 " in a 32-bit branch delay slot"));
584892a6
RS
7677 else
7678 return 0;
7679}
7680
7681/* Finish up a macro. Emit warnings as appropriate. */
7682
7683static void
7684macro_end (void)
7685{
df58fc94
RS
7686 /* Relaxation warning flags. */
7687 relax_substateT subtype = 0;
7688
7689 /* Check delay slot size requirements. */
7690 if (mips_macro_warning.delay_slot_length == 2)
7691 subtype |= RELAX_DELAY_SLOT_16BIT;
7692 if (mips_macro_warning.delay_slot_length != 0)
584892a6 7693 {
df58fc94
RS
7694 if (mips_macro_warning.delay_slot_length
7695 != mips_macro_warning.first_insn_sizes[0])
7696 subtype |= RELAX_DELAY_SLOT_SIZE_FIRST;
7697 if (mips_macro_warning.delay_slot_length
7698 != mips_macro_warning.first_insn_sizes[1])
7699 subtype |= RELAX_DELAY_SLOT_SIZE_SECOND;
7700 }
584892a6 7701
df58fc94
RS
7702 /* Check instruction count requirements. */
7703 if (mips_macro_warning.insns[0] > 1 || mips_macro_warning.insns[1] > 1)
7704 {
7705 if (mips_macro_warning.insns[1] > mips_macro_warning.insns[0])
584892a6
RS
7706 subtype |= RELAX_SECOND_LONGER;
7707 if (mips_opts.warn_about_macros)
7708 subtype |= RELAX_NOMACRO;
7709 if (mips_macro_warning.delay_slot_p)
7710 subtype |= RELAX_DELAY_SLOT;
df58fc94 7711 }
584892a6 7712
df58fc94
RS
7713 /* If both alternatives fail to fill a delay slot correctly,
7714 emit the warning now. */
7715 if ((subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0
7716 && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0)
7717 {
7718 relax_substateT s;
7719 const char *msg;
7720
7721 s = subtype & (RELAX_DELAY_SLOT_16BIT
7722 | RELAX_DELAY_SLOT_SIZE_FIRST
7723 | RELAX_DELAY_SLOT_SIZE_SECOND);
7724 msg = macro_warning (s);
7725 if (msg != NULL)
7726 as_warn ("%s", msg);
7727 subtype &= ~s;
7728 }
7729
7730 /* If both implementations are longer than 1 instruction, then emit the
7731 warning now. */
7732 if (mips_macro_warning.insns[0] > 1 && mips_macro_warning.insns[1] > 1)
7733 {
7734 relax_substateT s;
7735 const char *msg;
7736
7737 s = subtype & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT);
7738 msg = macro_warning (s);
7739 if (msg != NULL)
7740 as_warn ("%s", msg);
7741 subtype &= ~s;
584892a6 7742 }
df58fc94
RS
7743
7744 /* If any flags still set, then one implementation might need a warning
7745 and the other either will need one of a different kind or none at all.
7746 Pass any remaining flags over to relaxation. */
7747 if (mips_macro_warning.first_frag != NULL)
7748 mips_macro_warning.first_frag->fr_subtype |= subtype;
584892a6
RS
7749}
7750
df58fc94
RS
7751/* Instruction operand formats used in macros that vary between
7752 standard MIPS and microMIPS code. */
7753
833794fc 7754static const char * const brk_fmt[2][2] = { { "c", "c" }, { "mF", "c" } };
df58fc94
RS
7755static const char * const cop12_fmt[2] = { "E,o(b)", "E,~(b)" };
7756static const char * const jalr_fmt[2] = { "d,s", "t,s" };
7757static const char * const lui_fmt[2] = { "t,u", "s,u" };
7758static const char * const mem12_fmt[2] = { "t,o(b)", "t,~(b)" };
833794fc 7759static const char * const mfhl_fmt[2][2] = { { "d", "d" }, { "mj", "s" } };
df58fc94
RS
7760static const char * const shft_fmt[2] = { "d,w,<", "t,r,<" };
7761static const char * const trap_fmt[2] = { "s,t,q", "s,t,|" };
7762
833794fc 7763#define BRK_FMT (brk_fmt[mips_opts.micromips][mips_opts.insn32])
df58fc94
RS
7764#define COP12_FMT (cop12_fmt[mips_opts.micromips])
7765#define JALR_FMT (jalr_fmt[mips_opts.micromips])
7766#define LUI_FMT (lui_fmt[mips_opts.micromips])
7767#define MEM12_FMT (mem12_fmt[mips_opts.micromips])
833794fc 7768#define MFHL_FMT (mfhl_fmt[mips_opts.micromips][mips_opts.insn32])
df58fc94
RS
7769#define SHFT_FMT (shft_fmt[mips_opts.micromips])
7770#define TRAP_FMT (trap_fmt[mips_opts.micromips])
7771
6e1304d8
RS
7772/* Read a macro's relocation codes from *ARGS and store them in *R.
7773 The first argument in *ARGS will be either the code for a single
7774 relocation or -1 followed by the three codes that make up a
7775 composite relocation. */
7776
7777static void
7778macro_read_relocs (va_list *args, bfd_reloc_code_real_type *r)
7779{
7780 int i, next;
7781
7782 next = va_arg (*args, int);
7783 if (next >= 0)
7784 r[0] = (bfd_reloc_code_real_type) next;
7785 else
f2ae14a1
RS
7786 {
7787 for (i = 0; i < 3; i++)
7788 r[i] = (bfd_reloc_code_real_type) va_arg (*args, int);
7789 /* This function is only used for 16-bit relocation fields.
7790 To make the macro code simpler, treat an unrelocated value
7791 in the same way as BFD_RELOC_LO16. */
7792 if (r[0] == BFD_RELOC_UNUSED)
7793 r[0] = BFD_RELOC_LO16;
7794 }
6e1304d8
RS
7795}
7796
252b5132
RH
7797/* Build an instruction created by a macro expansion. This is passed
7798 a pointer to the count of instructions created so far, an
7799 expression, the name of the instruction to build, an operand format
7800 string, and corresponding arguments. */
7801
252b5132 7802static void
67c0d1eb 7803macro_build (expressionS *ep, const char *name, const char *fmt, ...)
252b5132 7804{
df58fc94 7805 const struct mips_opcode *mo = NULL;
f6688943 7806 bfd_reloc_code_real_type r[3];
df58fc94 7807 const struct mips_opcode *amo;
e077a1c8 7808 const struct mips_operand *operand;
df58fc94
RS
7809 struct hash_control *hash;
7810 struct mips_cl_insn insn;
252b5132 7811 va_list args;
e077a1c8 7812 unsigned int uval;
252b5132 7813
252b5132 7814 va_start (args, fmt);
252b5132 7815
252b5132
RH
7816 if (mips_opts.mips16)
7817 {
03ea81db 7818 mips16_macro_build (ep, name, fmt, &args);
252b5132
RH
7819 va_end (args);
7820 return;
7821 }
7822
f6688943
TS
7823 r[0] = BFD_RELOC_UNUSED;
7824 r[1] = BFD_RELOC_UNUSED;
7825 r[2] = BFD_RELOC_UNUSED;
df58fc94
RS
7826 hash = mips_opts.micromips ? micromips_op_hash : op_hash;
7827 amo = (struct mips_opcode *) hash_find (hash, name);
7828 gas_assert (amo);
7829 gas_assert (strcmp (name, amo->name) == 0);
1e915849 7830
df58fc94 7831 do
8b082fb1
TS
7832 {
7833 /* Search until we get a match for NAME. It is assumed here that
df58fc94
RS
7834 macros will never generate MDMX, MIPS-3D, or MT instructions.
7835 We try to match an instruction that fulfils the branch delay
7836 slot instruction length requirement (if any) of the previous
7837 instruction. While doing this we record the first instruction
7838 seen that matches all the other conditions and use it anyway
7839 if the requirement cannot be met; we will issue an appropriate
7840 warning later on. */
7841 if (strcmp (fmt, amo->args) == 0
7842 && amo->pinfo != INSN_MACRO
7843 && is_opcode_valid (amo)
7844 && is_size_valid (amo))
7845 {
7846 if (is_delay_slot_valid (amo))
7847 {
7848 mo = amo;
7849 break;
7850 }
7851 else if (!mo)
7852 mo = amo;
7853 }
8b082fb1 7854
df58fc94
RS
7855 ++amo;
7856 gas_assert (amo->name);
252b5132 7857 }
df58fc94 7858 while (strcmp (name, amo->name) == 0);
252b5132 7859
df58fc94 7860 gas_assert (mo);
1e915849 7861 create_insn (&insn, mo);
e077a1c8 7862 for (; *fmt; ++fmt)
252b5132 7863 {
e077a1c8 7864 switch (*fmt)
252b5132 7865 {
252b5132
RH
7866 case ',':
7867 case '(':
7868 case ')':
252b5132 7869 case 'z':
e077a1c8 7870 break;
252b5132
RH
7871
7872 case 'i':
7873 case 'j':
6e1304d8 7874 macro_read_relocs (&args, r);
9c2799c2 7875 gas_assert (*r == BFD_RELOC_GPREL16
e391c024
RS
7876 || *r == BFD_RELOC_MIPS_HIGHER
7877 || *r == BFD_RELOC_HI16_S
7878 || *r == BFD_RELOC_LO16
7879 || *r == BFD_RELOC_MIPS_GOT_OFST);
e077a1c8 7880 break;
e391c024
RS
7881
7882 case 'o':
7883 macro_read_relocs (&args, r);
e077a1c8 7884 break;
252b5132
RH
7885
7886 case 'u':
6e1304d8 7887 macro_read_relocs (&args, r);
9c2799c2 7888 gas_assert (ep != NULL
90ecf173
MR
7889 && (ep->X_op == O_constant
7890 || (ep->X_op == O_symbol
7891 && (*r == BFD_RELOC_MIPS_HIGHEST
7892 || *r == BFD_RELOC_HI16_S
7893 || *r == BFD_RELOC_HI16
7894 || *r == BFD_RELOC_GPREL16
7895 || *r == BFD_RELOC_MIPS_GOT_HI16
7896 || *r == BFD_RELOC_MIPS_CALL_HI16))));
e077a1c8 7897 break;
252b5132
RH
7898
7899 case 'p':
9c2799c2 7900 gas_assert (ep != NULL);
bad36eac 7901
252b5132
RH
7902 /*
7903 * This allows macro() to pass an immediate expression for
7904 * creating short branches without creating a symbol.
bad36eac
DJ
7905 *
7906 * We don't allow branch relaxation for these branches, as
7907 * they should only appear in ".set nomacro" anyway.
252b5132
RH
7908 */
7909 if (ep->X_op == O_constant)
7910 {
df58fc94
RS
7911 /* For microMIPS we always use relocations for branches.
7912 So we should not resolve immediate values. */
7913 gas_assert (!mips_opts.micromips);
7914
bad36eac
DJ
7915 if ((ep->X_add_number & 3) != 0)
7916 as_bad (_("branch to misaligned address (0x%lx)"),
7917 (unsigned long) ep->X_add_number);
7918 if ((ep->X_add_number + 0x20000) & ~0x3ffff)
7919 as_bad (_("branch address range overflow (0x%lx)"),
7920 (unsigned long) ep->X_add_number);
252b5132
RH
7921 insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff;
7922 ep = NULL;
7923 }
7924 else
0b25d3e6 7925 *r = BFD_RELOC_16_PCREL_S2;
e077a1c8 7926 break;
252b5132
RH
7927
7928 case 'a':
9c2799c2 7929 gas_assert (ep != NULL);
f6688943 7930 *r = BFD_RELOC_MIPS_JMP;
e077a1c8 7931 break;
d43b4baf 7932
252b5132 7933 default:
e077a1c8
RS
7934 operand = (mips_opts.micromips
7935 ? decode_micromips_operand (fmt)
7936 : decode_mips_operand (fmt));
7937 if (!operand)
7938 abort ();
7939
7940 uval = va_arg (args, int);
7941 if (operand->type == OP_CLO_CLZ_DEST)
7942 uval |= (uval << 5);
7943 insn_insert_operand (&insn, operand, uval);
7944
7945 if (*fmt == '+' || *fmt == 'm')
7946 ++fmt;
7947 break;
252b5132 7948 }
252b5132
RH
7949 }
7950 va_end (args);
9c2799c2 7951 gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
252b5132 7952
df58fc94 7953 append_insn (&insn, ep, r, TRUE);
252b5132
RH
7954}
7955
7956static void
67c0d1eb 7957mips16_macro_build (expressionS *ep, const char *name, const char *fmt,
03ea81db 7958 va_list *args)
252b5132 7959{
1e915849 7960 struct mips_opcode *mo;
252b5132 7961 struct mips_cl_insn insn;
e077a1c8 7962 const struct mips_operand *operand;
f6688943
TS
7963 bfd_reloc_code_real_type r[3]
7964 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
252b5132 7965
1e915849 7966 mo = (struct mips_opcode *) hash_find (mips16_op_hash, name);
9c2799c2
NC
7967 gas_assert (mo);
7968 gas_assert (strcmp (name, mo->name) == 0);
252b5132 7969
1e915849 7970 while (strcmp (fmt, mo->args) != 0 || mo->pinfo == INSN_MACRO)
252b5132 7971 {
1e915849 7972 ++mo;
9c2799c2
NC
7973 gas_assert (mo->name);
7974 gas_assert (strcmp (name, mo->name) == 0);
252b5132
RH
7975 }
7976
1e915849 7977 create_insn (&insn, mo);
e077a1c8 7978 for (; *fmt; ++fmt)
252b5132
RH
7979 {
7980 int c;
7981
e077a1c8 7982 c = *fmt;
252b5132
RH
7983 switch (c)
7984 {
252b5132
RH
7985 case ',':
7986 case '(':
7987 case ')':
e077a1c8 7988 break;
252b5132
RH
7989
7990 case '0':
7991 case 'S':
7992 case 'P':
7993 case 'R':
e077a1c8 7994 break;
252b5132
RH
7995
7996 case '<':
7997 case '>':
7998 case '4':
7999 case '5':
8000 case 'H':
8001 case 'W':
8002 case 'D':
8003 case 'j':
8004 case '8':
8005 case 'V':
8006 case 'C':
8007 case 'U':
8008 case 'k':
8009 case 'K':
8010 case 'p':
8011 case 'q':
8012 {
b886a2ab
RS
8013 offsetT value;
8014
9c2799c2 8015 gas_assert (ep != NULL);
252b5132
RH
8016
8017 if (ep->X_op != O_constant)
874e8986 8018 *r = (int) BFD_RELOC_UNUSED + c;
b886a2ab 8019 else if (calculate_reloc (*r, ep->X_add_number, &value))
252b5132 8020 {
b886a2ab 8021 mips16_immed (NULL, 0, c, *r, value, 0, &insn.insn_opcode);
252b5132 8022 ep = NULL;
f6688943 8023 *r = BFD_RELOC_UNUSED;
252b5132
RH
8024 }
8025 }
e077a1c8 8026 break;
252b5132 8027
e077a1c8
RS
8028 default:
8029 operand = decode_mips16_operand (c, FALSE);
8030 if (!operand)
8031 abort ();
252b5132 8032
4a06e5a2 8033 insn_insert_operand (&insn, operand, va_arg (*args, int));
e077a1c8
RS
8034 break;
8035 }
252b5132
RH
8036 }
8037
9c2799c2 8038 gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
252b5132 8039
df58fc94 8040 append_insn (&insn, ep, r, TRUE);
252b5132
RH
8041}
8042
438c16b8
TS
8043/*
8044 * Generate a "jalr" instruction with a relocation hint to the called
8045 * function. This occurs in NewABI PIC code.
8046 */
8047static void
df58fc94 8048macro_build_jalr (expressionS *ep, int cprestore)
438c16b8 8049{
df58fc94
RS
8050 static const bfd_reloc_code_real_type jalr_relocs[2]
8051 = { BFD_RELOC_MIPS_JALR, BFD_RELOC_MICROMIPS_JALR };
8052 bfd_reloc_code_real_type jalr_reloc = jalr_relocs[mips_opts.micromips];
8053 const char *jalr;
685736be 8054 char *f = NULL;
b34976b6 8055
1180b5a4 8056 if (MIPS_JALR_HINT_P (ep))
f21f8242 8057 {
cc3d92a5 8058 frag_grow (8);
f21f8242
AO
8059 f = frag_more (0);
8060 }
2906b037 8061 if (mips_opts.micromips)
df58fc94 8062 {
833794fc
MR
8063 jalr = ((mips_opts.noreorder && !cprestore) || mips_opts.insn32
8064 ? "jalr" : "jalrs");
e64af278 8065 if (MIPS_JALR_HINT_P (ep)
833794fc 8066 || mips_opts.insn32
e64af278 8067 || (history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
df58fc94
RS
8068 macro_build (NULL, jalr, "t,s", RA, PIC_CALL_REG);
8069 else
8070 macro_build (NULL, jalr, "mj", PIC_CALL_REG);
8071 }
2906b037
MR
8072 else
8073 macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG);
1180b5a4 8074 if (MIPS_JALR_HINT_P (ep))
df58fc94 8075 fix_new_exp (frag_now, f - frag_now->fr_literal, 4, ep, FALSE, jalr_reloc);
438c16b8
TS
8076}
8077
252b5132
RH
8078/*
8079 * Generate a "lui" instruction.
8080 */
8081static void
67c0d1eb 8082macro_build_lui (expressionS *ep, int regnum)
252b5132 8083{
9c2799c2 8084 gas_assert (! mips_opts.mips16);
252b5132 8085
df58fc94 8086 if (ep->X_op != O_constant)
252b5132 8087 {
9c2799c2 8088 gas_assert (ep->X_op == O_symbol);
bbe506e8
TS
8089 /* _gp_disp is a special case, used from s_cpload.
8090 __gnu_local_gp is used if mips_no_shared. */
9c2799c2 8091 gas_assert (mips_pic == NO_PIC
78e1bb40 8092 || (! HAVE_NEWABI
aa6975fb
ILT
8093 && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0)
8094 || (! mips_in_shared
bbe506e8
TS
8095 && strcmp (S_GET_NAME (ep->X_add_symbol),
8096 "__gnu_local_gp") == 0));
252b5132
RH
8097 }
8098
df58fc94 8099 macro_build (ep, "lui", LUI_FMT, regnum, BFD_RELOC_HI16_S);
252b5132
RH
8100}
8101
885add95
CD
8102/* Generate a sequence of instructions to do a load or store from a constant
8103 offset off of a base register (breg) into/from a target register (treg),
8104 using AT if necessary. */
8105static void
67c0d1eb
RS
8106macro_build_ldst_constoffset (expressionS *ep, const char *op,
8107 int treg, int breg, int dbl)
885add95 8108{
9c2799c2 8109 gas_assert (ep->X_op == O_constant);
885add95 8110
256ab948 8111 /* Sign-extending 32-bit constants makes their handling easier. */
2051e8c4
MR
8112 if (!dbl)
8113 normalize_constant_expr (ep);
256ab948 8114
67c1ffbe 8115 /* Right now, this routine can only handle signed 32-bit constants. */
ecd13cd3 8116 if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000))
885add95
CD
8117 as_warn (_("operand overflow"));
8118
8119 if (IS_SEXT_16BIT_NUM(ep->X_add_number))
8120 {
8121 /* Signed 16-bit offset will fit in the op. Easy! */
67c0d1eb 8122 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, breg);
885add95
CD
8123 }
8124 else
8125 {
8126 /* 32-bit offset, need multiple instructions and AT, like:
8127 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
8128 addu $tempreg,$tempreg,$breg
8129 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
8130 to handle the complete offset. */
67c0d1eb
RS
8131 macro_build_lui (ep, AT);
8132 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
8133 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, AT);
885add95 8134
741fe287 8135 if (!mips_opts.at)
1661c76c 8136 as_bad (_("macro used $at after \".set noat\""));
885add95
CD
8137 }
8138}
8139
252b5132
RH
8140/* set_at()
8141 * Generates code to set the $at register to true (one)
8142 * if reg is less than the immediate expression.
8143 */
8144static void
67c0d1eb 8145set_at (int reg, int unsignedp)
252b5132 8146{
b0e6f033 8147 if (imm_expr.X_add_number >= -0x8000
252b5132 8148 && imm_expr.X_add_number < 0x8000)
67c0d1eb
RS
8149 macro_build (&imm_expr, unsignedp ? "sltiu" : "slti", "t,r,j",
8150 AT, reg, BFD_RELOC_LO16);
252b5132
RH
8151 else
8152 {
67c0d1eb
RS
8153 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
8154 macro_build (NULL, unsignedp ? "sltu" : "slt", "d,v,t", AT, reg, AT);
252b5132
RH
8155 }
8156}
8157
252b5132
RH
8158/* Count the leading zeroes by performing a binary chop. This is a
8159 bulky bit of source, but performance is a LOT better for the
8160 majority of values than a simple loop to count the bits:
8161 for (lcnt = 0; (lcnt < 32); lcnt++)
8162 if ((v) & (1 << (31 - lcnt)))
8163 break;
8164 However it is not code size friendly, and the gain will drop a bit
8165 on certain cached systems.
8166*/
8167#define COUNT_TOP_ZEROES(v) \
8168 (((v) & ~0xffff) == 0 \
8169 ? ((v) & ~0xff) == 0 \
8170 ? ((v) & ~0xf) == 0 \
8171 ? ((v) & ~0x3) == 0 \
8172 ? ((v) & ~0x1) == 0 \
8173 ? !(v) \
8174 ? 32 \
8175 : 31 \
8176 : 30 \
8177 : ((v) & ~0x7) == 0 \
8178 ? 29 \
8179 : 28 \
8180 : ((v) & ~0x3f) == 0 \
8181 ? ((v) & ~0x1f) == 0 \
8182 ? 27 \
8183 : 26 \
8184 : ((v) & ~0x7f) == 0 \
8185 ? 25 \
8186 : 24 \
8187 : ((v) & ~0xfff) == 0 \
8188 ? ((v) & ~0x3ff) == 0 \
8189 ? ((v) & ~0x1ff) == 0 \
8190 ? 23 \
8191 : 22 \
8192 : ((v) & ~0x7ff) == 0 \
8193 ? 21 \
8194 : 20 \
8195 : ((v) & ~0x3fff) == 0 \
8196 ? ((v) & ~0x1fff) == 0 \
8197 ? 19 \
8198 : 18 \
8199 : ((v) & ~0x7fff) == 0 \
8200 ? 17 \
8201 : 16 \
8202 : ((v) & ~0xffffff) == 0 \
8203 ? ((v) & ~0xfffff) == 0 \
8204 ? ((v) & ~0x3ffff) == 0 \
8205 ? ((v) & ~0x1ffff) == 0 \
8206 ? 15 \
8207 : 14 \
8208 : ((v) & ~0x7ffff) == 0 \
8209 ? 13 \
8210 : 12 \
8211 : ((v) & ~0x3fffff) == 0 \
8212 ? ((v) & ~0x1fffff) == 0 \
8213 ? 11 \
8214 : 10 \
8215 : ((v) & ~0x7fffff) == 0 \
8216 ? 9 \
8217 : 8 \
8218 : ((v) & ~0xfffffff) == 0 \
8219 ? ((v) & ~0x3ffffff) == 0 \
8220 ? ((v) & ~0x1ffffff) == 0 \
8221 ? 7 \
8222 : 6 \
8223 : ((v) & ~0x7ffffff) == 0 \
8224 ? 5 \
8225 : 4 \
8226 : ((v) & ~0x3fffffff) == 0 \
8227 ? ((v) & ~0x1fffffff) == 0 \
8228 ? 3 \
8229 : 2 \
8230 : ((v) & ~0x7fffffff) == 0 \
8231 ? 1 \
8232 : 0)
8233
8234/* load_register()
67c1ffbe 8235 * This routine generates the least number of instructions necessary to load
252b5132
RH
8236 * an absolute expression value into a register.
8237 */
8238static void
67c0d1eb 8239load_register (int reg, expressionS *ep, int dbl)
252b5132
RH
8240{
8241 int freg;
8242 expressionS hi32, lo32;
8243
8244 if (ep->X_op != O_big)
8245 {
9c2799c2 8246 gas_assert (ep->X_op == O_constant);
256ab948
TS
8247
8248 /* Sign-extending 32-bit constants makes their handling easier. */
2051e8c4
MR
8249 if (!dbl)
8250 normalize_constant_expr (ep);
256ab948
TS
8251
8252 if (IS_SEXT_16BIT_NUM (ep->X_add_number))
252b5132
RH
8253 {
8254 /* We can handle 16 bit signed values with an addiu to
8255 $zero. No need to ever use daddiu here, since $zero and
8256 the result are always correct in 32 bit mode. */
67c0d1eb 8257 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
252b5132
RH
8258 return;
8259 }
8260 else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000)
8261 {
8262 /* We can handle 16 bit unsigned values with an ori to
8263 $zero. */
67c0d1eb 8264 macro_build (ep, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16);
252b5132
RH
8265 return;
8266 }
256ab948 8267 else if ((IS_SEXT_32BIT_NUM (ep->X_add_number)))
252b5132
RH
8268 {
8269 /* 32 bit values require an lui. */
df58fc94 8270 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_HI16);
252b5132 8271 if ((ep->X_add_number & 0xffff) != 0)
67c0d1eb 8272 macro_build (ep, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
252b5132
RH
8273 return;
8274 }
8275 }
8276
8277 /* The value is larger than 32 bits. */
8278
2051e8c4 8279 if (!dbl || HAVE_32BIT_GPRS)
252b5132 8280 {
55e08f71
NC
8281 char value[32];
8282
8283 sprintf_vma (value, ep->X_add_number);
1661c76c 8284 as_bad (_("number (0x%s) larger than 32 bits"), value);
67c0d1eb 8285 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
252b5132
RH
8286 return;
8287 }
8288
8289 if (ep->X_op != O_big)
8290 {
8291 hi32 = *ep;
8292 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
8293 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
8294 hi32.X_add_number &= 0xffffffff;
8295 lo32 = *ep;
8296 lo32.X_add_number &= 0xffffffff;
8297 }
8298 else
8299 {
9c2799c2 8300 gas_assert (ep->X_add_number > 2);
252b5132
RH
8301 if (ep->X_add_number == 3)
8302 generic_bignum[3] = 0;
8303 else if (ep->X_add_number > 4)
1661c76c 8304 as_bad (_("number larger than 64 bits"));
252b5132
RH
8305 lo32.X_op = O_constant;
8306 lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16);
8307 hi32.X_op = O_constant;
8308 hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16);
8309 }
8310
8311 if (hi32.X_add_number == 0)
8312 freg = 0;
8313 else
8314 {
8315 int shift, bit;
8316 unsigned long hi, lo;
8317
956cd1d6 8318 if (hi32.X_add_number == (offsetT) 0xffffffff)
beae10d5
KH
8319 {
8320 if ((lo32.X_add_number & 0xffff8000) == 0xffff8000)
8321 {
67c0d1eb 8322 macro_build (&lo32, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
beae10d5
KH
8323 return;
8324 }
8325 if (lo32.X_add_number & 0x80000000)
8326 {
df58fc94 8327 macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16);
252b5132 8328 if (lo32.X_add_number & 0xffff)
67c0d1eb 8329 macro_build (&lo32, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
beae10d5
KH
8330 return;
8331 }
8332 }
252b5132
RH
8333
8334 /* Check for 16bit shifted constant. We know that hi32 is
8335 non-zero, so start the mask on the first bit of the hi32
8336 value. */
8337 shift = 17;
8338 do
beae10d5
KH
8339 {
8340 unsigned long himask, lomask;
8341
8342 if (shift < 32)
8343 {
8344 himask = 0xffff >> (32 - shift);
8345 lomask = (0xffff << shift) & 0xffffffff;
8346 }
8347 else
8348 {
8349 himask = 0xffff << (shift - 32);
8350 lomask = 0;
8351 }
8352 if ((hi32.X_add_number & ~(offsetT) himask) == 0
8353 && (lo32.X_add_number & ~(offsetT) lomask) == 0)
8354 {
8355 expressionS tmp;
8356
8357 tmp.X_op = O_constant;
8358 if (shift < 32)
8359 tmp.X_add_number = ((hi32.X_add_number << (32 - shift))
8360 | (lo32.X_add_number >> shift));
8361 else
8362 tmp.X_add_number = hi32.X_add_number >> (shift - 32);
67c0d1eb 8363 macro_build (&tmp, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16);
df58fc94 8364 macro_build (NULL, (shift >= 32) ? "dsll32" : "dsll", SHFT_FMT,
67c0d1eb 8365 reg, reg, (shift >= 32) ? shift - 32 : shift);
beae10d5
KH
8366 return;
8367 }
f9419b05 8368 ++shift;
beae10d5
KH
8369 }
8370 while (shift <= (64 - 16));
252b5132
RH
8371
8372 /* Find the bit number of the lowest one bit, and store the
8373 shifted value in hi/lo. */
8374 hi = (unsigned long) (hi32.X_add_number & 0xffffffff);
8375 lo = (unsigned long) (lo32.X_add_number & 0xffffffff);
8376 if (lo != 0)
8377 {
8378 bit = 0;
8379 while ((lo & 1) == 0)
8380 {
8381 lo >>= 1;
8382 ++bit;
8383 }
8384 lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit);
8385 hi >>= bit;
8386 }
8387 else
8388 {
8389 bit = 32;
8390 while ((hi & 1) == 0)
8391 {
8392 hi >>= 1;
8393 ++bit;
8394 }
8395 lo = hi;
8396 hi = 0;
8397 }
8398
8399 /* Optimize if the shifted value is a (power of 2) - 1. */
8400 if ((hi == 0 && ((lo + 1) & lo) == 0)
8401 || (lo == 0xffffffff && ((hi + 1) & hi) == 0))
beae10d5
KH
8402 {
8403 shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number);
252b5132 8404 if (shift != 0)
beae10d5 8405 {
252b5132
RH
8406 expressionS tmp;
8407
8408 /* This instruction will set the register to be all
8409 ones. */
beae10d5
KH
8410 tmp.X_op = O_constant;
8411 tmp.X_add_number = (offsetT) -1;
67c0d1eb 8412 macro_build (&tmp, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
beae10d5
KH
8413 if (bit != 0)
8414 {
8415 bit += shift;
df58fc94 8416 macro_build (NULL, (bit >= 32) ? "dsll32" : "dsll", SHFT_FMT,
67c0d1eb 8417 reg, reg, (bit >= 32) ? bit - 32 : bit);
beae10d5 8418 }
df58fc94 8419 macro_build (NULL, (shift >= 32) ? "dsrl32" : "dsrl", SHFT_FMT,
67c0d1eb 8420 reg, reg, (shift >= 32) ? shift - 32 : shift);
beae10d5
KH
8421 return;
8422 }
8423 }
252b5132
RH
8424
8425 /* Sign extend hi32 before calling load_register, because we can
8426 generally get better code when we load a sign extended value. */
8427 if ((hi32.X_add_number & 0x80000000) != 0)
beae10d5 8428 hi32.X_add_number |= ~(offsetT) 0xffffffff;
67c0d1eb 8429 load_register (reg, &hi32, 0);
252b5132
RH
8430 freg = reg;
8431 }
8432 if ((lo32.X_add_number & 0xffff0000) == 0)
8433 {
8434 if (freg != 0)
8435 {
df58fc94 8436 macro_build (NULL, "dsll32", SHFT_FMT, reg, freg, 0);
252b5132
RH
8437 freg = reg;
8438 }
8439 }
8440 else
8441 {
8442 expressionS mid16;
8443
956cd1d6 8444 if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff))
beae10d5 8445 {
df58fc94
RS
8446 macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16);
8447 macro_build (NULL, "dsrl32", SHFT_FMT, reg, reg, 0);
beae10d5
KH
8448 return;
8449 }
252b5132
RH
8450
8451 if (freg != 0)
8452 {
df58fc94 8453 macro_build (NULL, "dsll", SHFT_FMT, reg, freg, 16);
252b5132
RH
8454 freg = reg;
8455 }
8456 mid16 = lo32;
8457 mid16.X_add_number >>= 16;
67c0d1eb 8458 macro_build (&mid16, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
df58fc94 8459 macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16);
252b5132
RH
8460 freg = reg;
8461 }
8462 if ((lo32.X_add_number & 0xffff) != 0)
67c0d1eb 8463 macro_build (&lo32, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
252b5132
RH
8464}
8465
269137b2
TS
8466static inline void
8467load_delay_nop (void)
8468{
8469 if (!gpr_interlocks)
8470 macro_build (NULL, "nop", "");
8471}
8472
252b5132
RH
8473/* Load an address into a register. */
8474
8475static void
67c0d1eb 8476load_address (int reg, expressionS *ep, int *used_at)
252b5132 8477{
252b5132
RH
8478 if (ep->X_op != O_constant
8479 && ep->X_op != O_symbol)
8480 {
8481 as_bad (_("expression too complex"));
8482 ep->X_op = O_constant;
8483 }
8484
8485 if (ep->X_op == O_constant)
8486 {
67c0d1eb 8487 load_register (reg, ep, HAVE_64BIT_ADDRESSES);
252b5132
RH
8488 return;
8489 }
8490
8491 if (mips_pic == NO_PIC)
8492 {
8493 /* If this is a reference to a GP relative symbol, we want
cdf6fd85 8494 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
252b5132
RH
8495 Otherwise we want
8496 lui $reg,<sym> (BFD_RELOC_HI16_S)
8497 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
d6bc6245 8498 If we have an addend, we always use the latter form.
76b3015f 8499
d6bc6245
TS
8500 With 64bit address space and a usable $at we want
8501 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8502 lui $at,<sym> (BFD_RELOC_HI16_S)
8503 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
8504 daddiu $at,<sym> (BFD_RELOC_LO16)
8505 dsll32 $reg,0
3a482fd5 8506 daddu $reg,$reg,$at
76b3015f 8507
c03099e6 8508 If $at is already in use, we use a path which is suboptimal
d6bc6245
TS
8509 on superscalar processors.
8510 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8511 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
8512 dsll $reg,16
8513 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
8514 dsll $reg,16
8515 daddiu $reg,<sym> (BFD_RELOC_LO16)
6caf9ef4
TS
8516
8517 For GP relative symbols in 64bit address space we can use
8518 the same sequence as in 32bit address space. */
aed1a261 8519 if (HAVE_64BIT_SYMBOLS)
d6bc6245 8520 {
6caf9ef4
TS
8521 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
8522 && !nopic_need_relax (ep->X_add_symbol, 1))
8523 {
8524 relax_start (ep->X_add_symbol);
8525 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
8526 mips_gp_register, BFD_RELOC_GPREL16);
8527 relax_switch ();
8528 }
d6bc6245 8529
741fe287 8530 if (*used_at == 0 && mips_opts.at)
d6bc6245 8531 {
df58fc94
RS
8532 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST);
8533 macro_build (ep, "lui", LUI_FMT, AT, BFD_RELOC_HI16_S);
67c0d1eb
RS
8534 macro_build (ep, "daddiu", "t,r,j", reg, reg,
8535 BFD_RELOC_MIPS_HIGHER);
8536 macro_build (ep, "daddiu", "t,r,j", AT, AT, BFD_RELOC_LO16);
df58fc94 8537 macro_build (NULL, "dsll32", SHFT_FMT, reg, reg, 0);
67c0d1eb 8538 macro_build (NULL, "daddu", "d,v,t", reg, reg, AT);
d6bc6245
TS
8539 *used_at = 1;
8540 }
8541 else
8542 {
df58fc94 8543 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST);
67c0d1eb
RS
8544 macro_build (ep, "daddiu", "t,r,j", reg, reg,
8545 BFD_RELOC_MIPS_HIGHER);
df58fc94 8546 macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16);
67c0d1eb 8547 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_HI16_S);
df58fc94 8548 macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16);
67c0d1eb 8549 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_LO16);
d6bc6245 8550 }
6caf9ef4
TS
8551
8552 if (mips_relax.sequence)
8553 relax_end ();
d6bc6245 8554 }
252b5132
RH
8555 else
8556 {
d6bc6245 8557 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
6caf9ef4 8558 && !nopic_need_relax (ep->X_add_symbol, 1))
d6bc6245 8559 {
4d7206a2 8560 relax_start (ep->X_add_symbol);
67c0d1eb 8561 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
17a2f251 8562 mips_gp_register, BFD_RELOC_GPREL16);
4d7206a2 8563 relax_switch ();
d6bc6245 8564 }
67c0d1eb
RS
8565 macro_build_lui (ep, reg);
8566 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j",
8567 reg, reg, BFD_RELOC_LO16);
4d7206a2
RS
8568 if (mips_relax.sequence)
8569 relax_end ();
d6bc6245 8570 }
252b5132 8571 }
0a44bf69 8572 else if (!mips_big_got)
252b5132
RH
8573 {
8574 expressionS ex;
8575
8576 /* If this is a reference to an external symbol, we want
8577 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8578 Otherwise we want
8579 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8580 nop
8581 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
f5040a92
AO
8582 If there is a constant, it must be added in after.
8583
ed6fb7bd 8584 If we have NewABI, we want
f5040a92
AO
8585 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
8586 unless we're referencing a global symbol with a non-zero
8587 offset, in which case cst must be added separately. */
ed6fb7bd
SC
8588 if (HAVE_NEWABI)
8589 {
f5040a92
AO
8590 if (ep->X_add_number)
8591 {
4d7206a2 8592 ex.X_add_number = ep->X_add_number;
f5040a92 8593 ep->X_add_number = 0;
4d7206a2 8594 relax_start (ep->X_add_symbol);
67c0d1eb
RS
8595 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
8596 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
f5040a92
AO
8597 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
8598 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
8599 ex.X_op = O_constant;
67c0d1eb 8600 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j",
17a2f251 8601 reg, reg, BFD_RELOC_LO16);
f5040a92 8602 ep->X_add_number = ex.X_add_number;
4d7206a2 8603 relax_switch ();
f5040a92 8604 }
67c0d1eb 8605 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
17a2f251 8606 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
4d7206a2
RS
8607 if (mips_relax.sequence)
8608 relax_end ();
ed6fb7bd
SC
8609 }
8610 else
8611 {
f5040a92
AO
8612 ex.X_add_number = ep->X_add_number;
8613 ep->X_add_number = 0;
67c0d1eb
RS
8614 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
8615 BFD_RELOC_MIPS_GOT16, mips_gp_register);
269137b2 8616 load_delay_nop ();
4d7206a2
RS
8617 relax_start (ep->X_add_symbol);
8618 relax_switch ();
67c0d1eb 8619 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
17a2f251 8620 BFD_RELOC_LO16);
4d7206a2 8621 relax_end ();
ed6fb7bd 8622
f5040a92
AO
8623 if (ex.X_add_number != 0)
8624 {
8625 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
8626 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
8627 ex.X_op = O_constant;
67c0d1eb 8628 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j",
17a2f251 8629 reg, reg, BFD_RELOC_LO16);
f5040a92 8630 }
252b5132
RH
8631 }
8632 }
0a44bf69 8633 else if (mips_big_got)
252b5132
RH
8634 {
8635 expressionS ex;
252b5132
RH
8636
8637 /* This is the large GOT case. If this is a reference to an
8638 external symbol, we want
8639 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
8640 addu $reg,$reg,$gp
8641 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
f5040a92
AO
8642
8643 Otherwise, for a reference to a local symbol in old ABI, we want
252b5132
RH
8644 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8645 nop
8646 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
684022ea 8647 If there is a constant, it must be added in after.
f5040a92
AO
8648
8649 In the NewABI, for local symbols, with or without offsets, we want:
438c16b8
TS
8650 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
8651 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
f5040a92 8652 */
438c16b8
TS
8653 if (HAVE_NEWABI)
8654 {
4d7206a2 8655 ex.X_add_number = ep->X_add_number;
f5040a92 8656 ep->X_add_number = 0;
4d7206a2 8657 relax_start (ep->X_add_symbol);
df58fc94 8658 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16);
67c0d1eb
RS
8659 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8660 reg, reg, mips_gp_register);
8661 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)",
8662 reg, BFD_RELOC_MIPS_GOT_LO16, reg);
f5040a92
AO
8663 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
8664 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
8665 else if (ex.X_add_number)
8666 {
8667 ex.X_op = O_constant;
67c0d1eb
RS
8668 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
8669 BFD_RELOC_LO16);
f5040a92
AO
8670 }
8671
8672 ep->X_add_number = ex.X_add_number;
4d7206a2 8673 relax_switch ();
67c0d1eb 8674 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
17a2f251 8675 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
67c0d1eb
RS
8676 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
8677 BFD_RELOC_MIPS_GOT_OFST);
4d7206a2 8678 relax_end ();
438c16b8 8679 }
252b5132 8680 else
438c16b8 8681 {
f5040a92
AO
8682 ex.X_add_number = ep->X_add_number;
8683 ep->X_add_number = 0;
4d7206a2 8684 relax_start (ep->X_add_symbol);
df58fc94 8685 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16);
67c0d1eb
RS
8686 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8687 reg, reg, mips_gp_register);
8688 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)",
8689 reg, BFD_RELOC_MIPS_GOT_LO16, reg);
4d7206a2
RS
8690 relax_switch ();
8691 if (reg_needs_delay (mips_gp_register))
438c16b8
TS
8692 {
8693 /* We need a nop before loading from $gp. This special
8694 check is required because the lui which starts the main
8695 instruction stream does not refer to $gp, and so will not
8696 insert the nop which may be required. */
67c0d1eb 8697 macro_build (NULL, "nop", "");
438c16b8 8698 }
67c0d1eb 8699 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
17a2f251 8700 BFD_RELOC_MIPS_GOT16, mips_gp_register);
269137b2 8701 load_delay_nop ();
67c0d1eb 8702 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
17a2f251 8703 BFD_RELOC_LO16);
4d7206a2 8704 relax_end ();
438c16b8 8705
f5040a92
AO
8706 if (ex.X_add_number != 0)
8707 {
8708 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
8709 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
8710 ex.X_op = O_constant;
67c0d1eb
RS
8711 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
8712 BFD_RELOC_LO16);
f5040a92 8713 }
252b5132
RH
8714 }
8715 }
252b5132
RH
8716 else
8717 abort ();
8fc2e39e 8718
741fe287 8719 if (!mips_opts.at && *used_at == 1)
1661c76c 8720 as_bad (_("macro used $at after \".set noat\""));
252b5132
RH
8721}
8722
ea1fb5dc
RS
8723/* Move the contents of register SOURCE into register DEST. */
8724
8725static void
67c0d1eb 8726move_register (int dest, int source)
ea1fb5dc 8727{
df58fc94
RS
8728 /* Prefer to use a 16-bit microMIPS instruction unless the previous
8729 instruction specifically requires a 32-bit one. */
8730 if (mips_opts.micromips
833794fc 8731 && !mips_opts.insn32
df58fc94 8732 && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
7951ca42 8733 macro_build (NULL, "move", "mp,mj", dest, source);
df58fc94
RS
8734 else
8735 macro_build (NULL, HAVE_32BIT_GPRS ? "addu" : "daddu", "d,v,t",
8736 dest, source, 0);
ea1fb5dc
RS
8737}
8738
4d7206a2 8739/* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
f6a22291
MR
8740 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
8741 The two alternatives are:
4d7206a2
RS
8742
8743 Global symbol Local sybmol
8744 ------------- ------------
8745 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
8746 ... ...
8747 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
8748
8749 load_got_offset emits the first instruction and add_got_offset
f6a22291
MR
8750 emits the second for a 16-bit offset or add_got_offset_hilo emits
8751 a sequence to add a 32-bit offset using a scratch register. */
4d7206a2
RS
8752
8753static void
67c0d1eb 8754load_got_offset (int dest, expressionS *local)
4d7206a2
RS
8755{
8756 expressionS global;
8757
8758 global = *local;
8759 global.X_add_number = 0;
8760
8761 relax_start (local->X_add_symbol);
67c0d1eb
RS
8762 macro_build (&global, ADDRESS_LOAD_INSN, "t,o(b)", dest,
8763 BFD_RELOC_MIPS_GOT16, mips_gp_register);
4d7206a2 8764 relax_switch ();
67c0d1eb
RS
8765 macro_build (local, ADDRESS_LOAD_INSN, "t,o(b)", dest,
8766 BFD_RELOC_MIPS_GOT16, mips_gp_register);
4d7206a2
RS
8767 relax_end ();
8768}
8769
8770static void
67c0d1eb 8771add_got_offset (int dest, expressionS *local)
4d7206a2
RS
8772{
8773 expressionS global;
8774
8775 global.X_op = O_constant;
8776 global.X_op_symbol = NULL;
8777 global.X_add_symbol = NULL;
8778 global.X_add_number = local->X_add_number;
8779
8780 relax_start (local->X_add_symbol);
67c0d1eb 8781 macro_build (&global, ADDRESS_ADDI_INSN, "t,r,j",
4d7206a2
RS
8782 dest, dest, BFD_RELOC_LO16);
8783 relax_switch ();
67c0d1eb 8784 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", dest, dest, BFD_RELOC_LO16);
4d7206a2
RS
8785 relax_end ();
8786}
8787
f6a22291
MR
8788static void
8789add_got_offset_hilo (int dest, expressionS *local, int tmp)
8790{
8791 expressionS global;
8792 int hold_mips_optimize;
8793
8794 global.X_op = O_constant;
8795 global.X_op_symbol = NULL;
8796 global.X_add_symbol = NULL;
8797 global.X_add_number = local->X_add_number;
8798
8799 relax_start (local->X_add_symbol);
8800 load_register (tmp, &global, HAVE_64BIT_ADDRESSES);
8801 relax_switch ();
8802 /* Set mips_optimize around the lui instruction to avoid
8803 inserting an unnecessary nop after the lw. */
8804 hold_mips_optimize = mips_optimize;
8805 mips_optimize = 2;
8806 macro_build_lui (&global, tmp);
8807 mips_optimize = hold_mips_optimize;
8808 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", tmp, tmp, BFD_RELOC_LO16);
8809 relax_end ();
8810
8811 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dest, dest, tmp);
8812}
8813
df58fc94
RS
8814/* Emit a sequence of instructions to emulate a branch likely operation.
8815 BR is an ordinary branch corresponding to one to be emulated. BRNEG
8816 is its complementing branch with the original condition negated.
8817 CALL is set if the original branch specified the link operation.
8818 EP, FMT, SREG and TREG specify the usual macro_build() parameters.
8819
8820 Code like this is produced in the noreorder mode:
8821
8822 BRNEG <args>, 1f
8823 nop
8824 b <sym>
8825 delay slot (executed only if branch taken)
8826 1:
8827
8828 or, if CALL is set:
8829
8830 BRNEG <args>, 1f
8831 nop
8832 bal <sym>
8833 delay slot (executed only if branch taken)
8834 1:
8835
8836 In the reorder mode the delay slot would be filled with a nop anyway,
8837 so code produced is simply:
8838
8839 BR <args>, <sym>
8840 nop
8841
8842 This function is used when producing code for the microMIPS ASE that
8843 does not implement branch likely instructions in hardware. */
8844
8845static void
8846macro_build_branch_likely (const char *br, const char *brneg,
8847 int call, expressionS *ep, const char *fmt,
8848 unsigned int sreg, unsigned int treg)
8849{
8850 int noreorder = mips_opts.noreorder;
8851 expressionS expr1;
8852
8853 gas_assert (mips_opts.micromips);
8854 start_noreorder ();
8855 if (noreorder)
8856 {
8857 micromips_label_expr (&expr1);
8858 macro_build (&expr1, brneg, fmt, sreg, treg);
8859 macro_build (NULL, "nop", "");
8860 macro_build (ep, call ? "bal" : "b", "p");
8861
8862 /* Set to true so that append_insn adds a label. */
8863 emit_branch_likely_macro = TRUE;
8864 }
8865 else
8866 {
8867 macro_build (ep, br, fmt, sreg, treg);
8868 macro_build (NULL, "nop", "");
8869 }
8870 end_noreorder ();
8871}
8872
8873/* Emit a coprocessor branch-likely macro specified by TYPE, using CC as
8874 the condition code tested. EP specifies the branch target. */
8875
8876static void
8877macro_build_branch_ccl (int type, expressionS *ep, unsigned int cc)
8878{
8879 const int call = 0;
8880 const char *brneg;
8881 const char *br;
8882
8883 switch (type)
8884 {
8885 case M_BC1FL:
8886 br = "bc1f";
8887 brneg = "bc1t";
8888 break;
8889 case M_BC1TL:
8890 br = "bc1t";
8891 brneg = "bc1f";
8892 break;
8893 case M_BC2FL:
8894 br = "bc2f";
8895 brneg = "bc2t";
8896 break;
8897 case M_BC2TL:
8898 br = "bc2t";
8899 brneg = "bc2f";
8900 break;
8901 default:
8902 abort ();
8903 }
8904 macro_build_branch_likely (br, brneg, call, ep, "N,p", cc, ZERO);
8905}
8906
8907/* Emit a two-argument branch macro specified by TYPE, using SREG as
8908 the register tested. EP specifies the branch target. */
8909
8910static void
8911macro_build_branch_rs (int type, expressionS *ep, unsigned int sreg)
8912{
8913 const char *brneg = NULL;
8914 const char *br;
8915 int call = 0;
8916
8917 switch (type)
8918 {
8919 case M_BGEZ:
8920 br = "bgez";
8921 break;
8922 case M_BGEZL:
8923 br = mips_opts.micromips ? "bgez" : "bgezl";
8924 brneg = "bltz";
8925 break;
8926 case M_BGEZALL:
8927 gas_assert (mips_opts.micromips);
833794fc 8928 br = mips_opts.insn32 ? "bgezal" : "bgezals";
df58fc94
RS
8929 brneg = "bltz";
8930 call = 1;
8931 break;
8932 case M_BGTZ:
8933 br = "bgtz";
8934 break;
8935 case M_BGTZL:
8936 br = mips_opts.micromips ? "bgtz" : "bgtzl";
8937 brneg = "blez";
8938 break;
8939 case M_BLEZ:
8940 br = "blez";
8941 break;
8942 case M_BLEZL:
8943 br = mips_opts.micromips ? "blez" : "blezl";
8944 brneg = "bgtz";
8945 break;
8946 case M_BLTZ:
8947 br = "bltz";
8948 break;
8949 case M_BLTZL:
8950 br = mips_opts.micromips ? "bltz" : "bltzl";
8951 brneg = "bgez";
8952 break;
8953 case M_BLTZALL:
8954 gas_assert (mips_opts.micromips);
833794fc 8955 br = mips_opts.insn32 ? "bltzal" : "bltzals";
df58fc94
RS
8956 brneg = "bgez";
8957 call = 1;
8958 break;
8959 default:
8960 abort ();
8961 }
8962 if (mips_opts.micromips && brneg)
8963 macro_build_branch_likely (br, brneg, call, ep, "s,p", sreg, ZERO);
8964 else
8965 macro_build (ep, br, "s,p", sreg);
8966}
8967
8968/* Emit a three-argument branch macro specified by TYPE, using SREG and
8969 TREG as the registers tested. EP specifies the branch target. */
8970
8971static void
8972macro_build_branch_rsrt (int type, expressionS *ep,
8973 unsigned int sreg, unsigned int treg)
8974{
8975 const char *brneg = NULL;
8976 const int call = 0;
8977 const char *br;
8978
8979 switch (type)
8980 {
8981 case M_BEQ:
8982 case M_BEQ_I:
8983 br = "beq";
8984 break;
8985 case M_BEQL:
8986 case M_BEQL_I:
8987 br = mips_opts.micromips ? "beq" : "beql";
8988 brneg = "bne";
8989 break;
8990 case M_BNE:
8991 case M_BNE_I:
8992 br = "bne";
8993 break;
8994 case M_BNEL:
8995 case M_BNEL_I:
8996 br = mips_opts.micromips ? "bne" : "bnel";
8997 brneg = "beq";
8998 break;
8999 default:
9000 abort ();
9001 }
9002 if (mips_opts.micromips && brneg)
9003 macro_build_branch_likely (br, brneg, call, ep, "s,t,p", sreg, treg);
9004 else
9005 macro_build (ep, br, "s,t,p", sreg, treg);
9006}
9007
f2ae14a1
RS
9008/* Return the high part that should be loaded in order to make the low
9009 part of VALUE accessible using an offset of OFFBITS bits. */
9010
9011static offsetT
9012offset_high_part (offsetT value, unsigned int offbits)
9013{
9014 offsetT bias;
9015 addressT low_mask;
9016
9017 if (offbits == 0)
9018 return value;
9019 bias = 1 << (offbits - 1);
9020 low_mask = bias * 2 - 1;
9021 return (value + bias) & ~low_mask;
9022}
9023
9024/* Return true if the value stored in offset_expr and offset_reloc
9025 fits into a signed offset of OFFBITS bits. RANGE is the maximum
9026 amount that the caller wants to add without inducing overflow
9027 and ALIGN is the known alignment of the value in bytes. */
9028
9029static bfd_boolean
9030small_offset_p (unsigned int range, unsigned int align, unsigned int offbits)
9031{
9032 if (offbits == 16)
9033 {
9034 /* Accept any relocation operator if overflow isn't a concern. */
9035 if (range < align && *offset_reloc != BFD_RELOC_UNUSED)
9036 return TRUE;
9037
9038 /* These relocations are guaranteed not to overflow in correct links. */
9039 if (*offset_reloc == BFD_RELOC_MIPS_LITERAL
9040 || gprel16_reloc_p (*offset_reloc))
9041 return TRUE;
9042 }
9043 if (offset_expr.X_op == O_constant
9044 && offset_high_part (offset_expr.X_add_number, offbits) == 0
9045 && offset_high_part (offset_expr.X_add_number + range, offbits) == 0)
9046 return TRUE;
9047 return FALSE;
9048}
9049
252b5132
RH
9050/*
9051 * Build macros
9052 * This routine implements the seemingly endless macro or synthesized
9053 * instructions and addressing modes in the mips assembly language. Many
9054 * of these macros are simple and are similar to each other. These could
67c1ffbe 9055 * probably be handled by some kind of table or grammar approach instead of
252b5132
RH
9056 * this verbose method. Others are not simple macros but are more like
9057 * optimizing code generation.
9058 * One interesting optimization is when several store macros appear
67c1ffbe 9059 * consecutively that would load AT with the upper half of the same address.
252b5132
RH
9060 * The ensuing load upper instructions are ommited. This implies some kind
9061 * of global optimization. We currently only optimize within a single macro.
9062 * For many of the load and store macros if the address is specified as a
9063 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
9064 * first load register 'at' with zero and use it as the base register. The
9065 * mips assembler simply uses register $zero. Just one tiny optimization
9066 * we're missing.
9067 */
9068static void
833794fc 9069macro (struct mips_cl_insn *ip, char *str)
252b5132 9070{
c0ebe874
RS
9071 const struct mips_operand_array *operands;
9072 unsigned int breg, i;
741fe287 9073 unsigned int tempreg;
252b5132 9074 int mask;
43841e91 9075 int used_at = 0;
df58fc94 9076 expressionS label_expr;
252b5132 9077 expressionS expr1;
df58fc94 9078 expressionS *ep;
252b5132
RH
9079 const char *s;
9080 const char *s2;
9081 const char *fmt;
9082 int likely = 0;
252b5132 9083 int coproc = 0;
7f3c4072 9084 int offbits = 16;
1abe91b1 9085 int call = 0;
df58fc94
RS
9086 int jals = 0;
9087 int dbl = 0;
9088 int imm = 0;
9089 int ust = 0;
9090 int lp = 0;
f2ae14a1 9091 bfd_boolean large_offset;
252b5132 9092 int off;
252b5132 9093 int hold_mips_optimize;
f2ae14a1 9094 unsigned int align;
c0ebe874 9095 unsigned int op[MAX_OPERANDS];
252b5132 9096
9c2799c2 9097 gas_assert (! mips_opts.mips16);
252b5132 9098
c0ebe874
RS
9099 operands = insn_operands (ip);
9100 for (i = 0; i < MAX_OPERANDS; i++)
9101 if (operands->operand[i])
9102 op[i] = insn_extract_operand (ip, operands->operand[i]);
9103 else
9104 op[i] = -1;
9105
252b5132
RH
9106 mask = ip->insn_mo->mask;
9107
df58fc94
RS
9108 label_expr.X_op = O_constant;
9109 label_expr.X_op_symbol = NULL;
9110 label_expr.X_add_symbol = NULL;
9111 label_expr.X_add_number = 0;
9112
252b5132
RH
9113 expr1.X_op = O_constant;
9114 expr1.X_op_symbol = NULL;
9115 expr1.X_add_symbol = NULL;
9116 expr1.X_add_number = 1;
f2ae14a1 9117 align = 1;
252b5132
RH
9118
9119 switch (mask)
9120 {
9121 case M_DABS:
9122 dbl = 1;
9123 case M_ABS:
df58fc94
RS
9124 /* bgez $a0,1f
9125 move v0,$a0
9126 sub v0,$zero,$a0
9127 1:
9128 */
252b5132 9129
7d10b47d 9130 start_noreorder ();
252b5132 9131
df58fc94
RS
9132 if (mips_opts.micromips)
9133 micromips_label_expr (&label_expr);
9134 else
9135 label_expr.X_add_number = 8;
c0ebe874
RS
9136 macro_build (&label_expr, "bgez", "s,p", op[1]);
9137 if (op[0] == op[1])
a605d2b3 9138 macro_build (NULL, "nop", "");
252b5132 9139 else
c0ebe874
RS
9140 move_register (op[0], op[1]);
9141 macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", op[0], 0, op[1]);
df58fc94
RS
9142 if (mips_opts.micromips)
9143 micromips_add_label ();
252b5132 9144
7d10b47d 9145 end_noreorder ();
8fc2e39e 9146 break;
252b5132
RH
9147
9148 case M_ADD_I:
9149 s = "addi";
9150 s2 = "add";
9151 goto do_addi;
9152 case M_ADDU_I:
9153 s = "addiu";
9154 s2 = "addu";
9155 goto do_addi;
9156 case M_DADD_I:
9157 dbl = 1;
9158 s = "daddi";
9159 s2 = "dadd";
df58fc94
RS
9160 if (!mips_opts.micromips)
9161 goto do_addi;
b0e6f033 9162 if (imm_expr.X_add_number >= -0x200
df58fc94
RS
9163 && imm_expr.X_add_number < 0x200)
9164 {
b0e6f033
RS
9165 macro_build (NULL, s, "t,r,.", op[0], op[1],
9166 (int) imm_expr.X_add_number);
df58fc94
RS
9167 break;
9168 }
9169 goto do_addi_i;
252b5132
RH
9170 case M_DADDU_I:
9171 dbl = 1;
9172 s = "daddiu";
9173 s2 = "daddu";
9174 do_addi:
b0e6f033 9175 if (imm_expr.X_add_number >= -0x8000
252b5132
RH
9176 && imm_expr.X_add_number < 0x8000)
9177 {
c0ebe874 9178 macro_build (&imm_expr, s, "t,r,j", op[0], op[1], BFD_RELOC_LO16);
8fc2e39e 9179 break;
252b5132 9180 }
df58fc94 9181 do_addi_i:
8fc2e39e 9182 used_at = 1;
67c0d1eb 9183 load_register (AT, &imm_expr, dbl);
c0ebe874 9184 macro_build (NULL, s2, "d,v,t", op[0], op[1], AT);
252b5132
RH
9185 break;
9186
9187 case M_AND_I:
9188 s = "andi";
9189 s2 = "and";
9190 goto do_bit;
9191 case M_OR_I:
9192 s = "ori";
9193 s2 = "or";
9194 goto do_bit;
9195 case M_NOR_I:
9196 s = "";
9197 s2 = "nor";
9198 goto do_bit;
9199 case M_XOR_I:
9200 s = "xori";
9201 s2 = "xor";
9202 do_bit:
b0e6f033 9203 if (imm_expr.X_add_number >= 0
252b5132
RH
9204 && imm_expr.X_add_number < 0x10000)
9205 {
9206 if (mask != M_NOR_I)
c0ebe874 9207 macro_build (&imm_expr, s, "t,r,i", op[0], op[1], BFD_RELOC_LO16);
252b5132
RH
9208 else
9209 {
67c0d1eb 9210 macro_build (&imm_expr, "ori", "t,r,i",
c0ebe874
RS
9211 op[0], op[1], BFD_RELOC_LO16);
9212 macro_build (NULL, "nor", "d,v,t", op[0], op[0], 0);
252b5132 9213 }
8fc2e39e 9214 break;
252b5132
RH
9215 }
9216
8fc2e39e 9217 used_at = 1;
67c0d1eb 9218 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
c0ebe874 9219 macro_build (NULL, s2, "d,v,t", op[0], op[1], AT);
252b5132
RH
9220 break;
9221
8b082fb1
TS
9222 case M_BALIGN:
9223 switch (imm_expr.X_add_number)
9224 {
9225 case 0:
9226 macro_build (NULL, "nop", "");
9227 break;
9228 case 2:
c0ebe874 9229 macro_build (NULL, "packrl.ph", "d,s,t", op[0], op[0], op[1]);
8b082fb1 9230 break;
03f66e8a
MR
9231 case 1:
9232 case 3:
c0ebe874 9233 macro_build (NULL, "balign", "t,s,2", op[0], op[1],
90ecf173 9234 (int) imm_expr.X_add_number);
8b082fb1 9235 break;
03f66e8a
MR
9236 default:
9237 as_bad (_("BALIGN immediate not 0, 1, 2 or 3 (%lu)"),
9238 (unsigned long) imm_expr.X_add_number);
9239 break;
8b082fb1
TS
9240 }
9241 break;
9242
df58fc94
RS
9243 case M_BC1FL:
9244 case M_BC1TL:
9245 case M_BC2FL:
9246 case M_BC2TL:
9247 gas_assert (mips_opts.micromips);
9248 macro_build_branch_ccl (mask, &offset_expr,
9249 EXTRACT_OPERAND (1, BCC, *ip));
9250 break;
9251
252b5132 9252 case M_BEQ_I:
252b5132 9253 case M_BEQL_I:
252b5132 9254 case M_BNE_I:
252b5132 9255 case M_BNEL_I:
b0e6f033 9256 if (imm_expr.X_add_number == 0)
c0ebe874 9257 op[1] = 0;
df58fc94 9258 else
252b5132 9259 {
c0ebe874 9260 op[1] = AT;
df58fc94 9261 used_at = 1;
c0ebe874 9262 load_register (op[1], &imm_expr, HAVE_64BIT_GPRS);
252b5132 9263 }
df58fc94
RS
9264 /* Fall through. */
9265 case M_BEQL:
9266 case M_BNEL:
c0ebe874 9267 macro_build_branch_rsrt (mask, &offset_expr, op[0], op[1]);
252b5132
RH
9268 break;
9269
9270 case M_BGEL:
9271 likely = 1;
9272 case M_BGE:
c0ebe874
RS
9273 if (op[1] == 0)
9274 macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, op[0]);
9275 else if (op[0] == 0)
9276 macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, op[1]);
df58fc94 9277 else
252b5132 9278 {
df58fc94 9279 used_at = 1;
c0ebe874 9280 macro_build (NULL, "slt", "d,v,t", AT, op[0], op[1]);
df58fc94
RS
9281 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
9282 &offset_expr, AT, ZERO);
252b5132 9283 }
df58fc94
RS
9284 break;
9285
9286 case M_BGEZL:
9287 case M_BGEZALL:
9288 case M_BGTZL:
9289 case M_BLEZL:
9290 case M_BLTZL:
9291 case M_BLTZALL:
c0ebe874 9292 macro_build_branch_rs (mask, &offset_expr, op[0]);
252b5132
RH
9293 break;
9294
9295 case M_BGTL_I:
9296 likely = 1;
9297 case M_BGT_I:
90ecf173 9298 /* Check for > max integer. */
b0e6f033 9299 if (imm_expr.X_add_number >= GPR_SMAX)
252b5132
RH
9300 {
9301 do_false:
90ecf173 9302 /* Result is always false. */
252b5132 9303 if (! likely)
a605d2b3 9304 macro_build (NULL, "nop", "");
252b5132 9305 else
df58fc94 9306 macro_build_branch_rsrt (M_BNEL, &offset_expr, ZERO, ZERO);
8fc2e39e 9307 break;
252b5132 9308 }
f9419b05 9309 ++imm_expr.X_add_number;
252b5132
RH
9310 /* FALLTHROUGH */
9311 case M_BGE_I:
9312 case M_BGEL_I:
9313 if (mask == M_BGEL_I)
9314 likely = 1;
b0e6f033 9315 if (imm_expr.X_add_number == 0)
252b5132 9316 {
df58fc94 9317 macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ,
c0ebe874 9318 &offset_expr, op[0]);
8fc2e39e 9319 break;
252b5132 9320 }
b0e6f033 9321 if (imm_expr.X_add_number == 1)
252b5132 9322 {
df58fc94 9323 macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ,
c0ebe874 9324 &offset_expr, op[0]);
8fc2e39e 9325 break;
252b5132 9326 }
b0e6f033 9327 if (imm_expr.X_add_number <= GPR_SMIN)
252b5132
RH
9328 {
9329 do_true:
9330 /* result is always true */
1661c76c 9331 as_warn (_("branch %s is always true"), ip->insn_mo->name);
67c0d1eb 9332 macro_build (&offset_expr, "b", "p");
8fc2e39e 9333 break;
252b5132 9334 }
8fc2e39e 9335 used_at = 1;
c0ebe874 9336 set_at (op[0], 0);
df58fc94
RS
9337 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
9338 &offset_expr, AT, ZERO);
252b5132
RH
9339 break;
9340
9341 case M_BGEUL:
9342 likely = 1;
9343 case M_BGEU:
c0ebe874 9344 if (op[1] == 0)
252b5132 9345 goto do_true;
c0ebe874 9346 else if (op[0] == 0)
df58fc94 9347 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
c0ebe874 9348 &offset_expr, ZERO, op[1]);
df58fc94 9349 else
252b5132 9350 {
df58fc94 9351 used_at = 1;
c0ebe874 9352 macro_build (NULL, "sltu", "d,v,t", AT, op[0], op[1]);
df58fc94
RS
9353 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
9354 &offset_expr, AT, ZERO);
252b5132 9355 }
252b5132
RH
9356 break;
9357
9358 case M_BGTUL_I:
9359 likely = 1;
9360 case M_BGTU_I:
c0ebe874 9361 if (op[0] == 0
ca4e0257 9362 || (HAVE_32BIT_GPRS
f01dc953 9363 && imm_expr.X_add_number == -1))
252b5132 9364 goto do_false;
f9419b05 9365 ++imm_expr.X_add_number;
252b5132
RH
9366 /* FALLTHROUGH */
9367 case M_BGEU_I:
9368 case M_BGEUL_I:
9369 if (mask == M_BGEUL_I)
9370 likely = 1;
b0e6f033 9371 if (imm_expr.X_add_number == 0)
252b5132 9372 goto do_true;
b0e6f033 9373 else if (imm_expr.X_add_number == 1)
df58fc94 9374 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
c0ebe874 9375 &offset_expr, op[0], ZERO);
df58fc94 9376 else
252b5132 9377 {
df58fc94 9378 used_at = 1;
c0ebe874 9379 set_at (op[0], 1);
df58fc94
RS
9380 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
9381 &offset_expr, AT, ZERO);
252b5132 9382 }
252b5132
RH
9383 break;
9384
9385 case M_BGTL:
9386 likely = 1;
9387 case M_BGT:
c0ebe874
RS
9388 if (op[1] == 0)
9389 macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, op[0]);
9390 else if (op[0] == 0)
9391 macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, op[1]);
df58fc94 9392 else
252b5132 9393 {
df58fc94 9394 used_at = 1;
c0ebe874 9395 macro_build (NULL, "slt", "d,v,t", AT, op[1], op[0]);
df58fc94
RS
9396 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
9397 &offset_expr, AT, ZERO);
252b5132 9398 }
252b5132
RH
9399 break;
9400
9401 case M_BGTUL:
9402 likely = 1;
9403 case M_BGTU:
c0ebe874 9404 if (op[1] == 0)
df58fc94 9405 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
c0ebe874
RS
9406 &offset_expr, op[0], ZERO);
9407 else if (op[0] == 0)
df58fc94
RS
9408 goto do_false;
9409 else
252b5132 9410 {
df58fc94 9411 used_at = 1;
c0ebe874 9412 macro_build (NULL, "sltu", "d,v,t", AT, op[1], op[0]);
df58fc94
RS
9413 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
9414 &offset_expr, AT, ZERO);
252b5132 9415 }
252b5132
RH
9416 break;
9417
9418 case M_BLEL:
9419 likely = 1;
9420 case M_BLE:
c0ebe874
RS
9421 if (op[1] == 0)
9422 macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, op[0]);
9423 else if (op[0] == 0)
9424 macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, op[1]);
df58fc94 9425 else
252b5132 9426 {
df58fc94 9427 used_at = 1;
c0ebe874 9428 macro_build (NULL, "slt", "d,v,t", AT, op[1], op[0]);
df58fc94
RS
9429 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
9430 &offset_expr, AT, ZERO);
252b5132 9431 }
252b5132
RH
9432 break;
9433
9434 case M_BLEL_I:
9435 likely = 1;
9436 case M_BLE_I:
b0e6f033 9437 if (imm_expr.X_add_number >= GPR_SMAX)
252b5132 9438 goto do_true;
f9419b05 9439 ++imm_expr.X_add_number;
252b5132
RH
9440 /* FALLTHROUGH */
9441 case M_BLT_I:
9442 case M_BLTL_I:
9443 if (mask == M_BLTL_I)
9444 likely = 1;
b0e6f033 9445 if (imm_expr.X_add_number == 0)
c0ebe874 9446 macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, op[0]);
b0e6f033 9447 else if (imm_expr.X_add_number == 1)
c0ebe874 9448 macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, op[0]);
df58fc94 9449 else
252b5132 9450 {
df58fc94 9451 used_at = 1;
c0ebe874 9452 set_at (op[0], 0);
df58fc94
RS
9453 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
9454 &offset_expr, AT, ZERO);
252b5132 9455 }
252b5132
RH
9456 break;
9457
9458 case M_BLEUL:
9459 likely = 1;
9460 case M_BLEU:
c0ebe874 9461 if (op[1] == 0)
df58fc94 9462 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
c0ebe874
RS
9463 &offset_expr, op[0], ZERO);
9464 else if (op[0] == 0)
df58fc94
RS
9465 goto do_true;
9466 else
252b5132 9467 {
df58fc94 9468 used_at = 1;
c0ebe874 9469 macro_build (NULL, "sltu", "d,v,t", AT, op[1], op[0]);
df58fc94
RS
9470 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
9471 &offset_expr, AT, ZERO);
252b5132 9472 }
252b5132
RH
9473 break;
9474
9475 case M_BLEUL_I:
9476 likely = 1;
9477 case M_BLEU_I:
c0ebe874 9478 if (op[0] == 0
ca4e0257 9479 || (HAVE_32BIT_GPRS
f01dc953 9480 && imm_expr.X_add_number == -1))
252b5132 9481 goto do_true;
f9419b05 9482 ++imm_expr.X_add_number;
252b5132
RH
9483 /* FALLTHROUGH */
9484 case M_BLTU_I:
9485 case M_BLTUL_I:
9486 if (mask == M_BLTUL_I)
9487 likely = 1;
b0e6f033 9488 if (imm_expr.X_add_number == 0)
252b5132 9489 goto do_false;
b0e6f033 9490 else if (imm_expr.X_add_number == 1)
df58fc94 9491 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
c0ebe874 9492 &offset_expr, op[0], ZERO);
df58fc94 9493 else
252b5132 9494 {
df58fc94 9495 used_at = 1;
c0ebe874 9496 set_at (op[0], 1);
df58fc94
RS
9497 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
9498 &offset_expr, AT, ZERO);
252b5132 9499 }
252b5132
RH
9500 break;
9501
9502 case M_BLTL:
9503 likely = 1;
9504 case M_BLT:
c0ebe874
RS
9505 if (op[1] == 0)
9506 macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, op[0]);
9507 else if (op[0] == 0)
9508 macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, op[1]);
df58fc94 9509 else
252b5132 9510 {
df58fc94 9511 used_at = 1;
c0ebe874 9512 macro_build (NULL, "slt", "d,v,t", AT, op[0], op[1]);
df58fc94
RS
9513 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
9514 &offset_expr, AT, ZERO);
252b5132 9515 }
252b5132
RH
9516 break;
9517
9518 case M_BLTUL:
9519 likely = 1;
9520 case M_BLTU:
c0ebe874 9521 if (op[1] == 0)
252b5132 9522 goto do_false;
c0ebe874 9523 else if (op[0] == 0)
df58fc94 9524 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
c0ebe874 9525 &offset_expr, ZERO, op[1]);
df58fc94 9526 else
252b5132 9527 {
df58fc94 9528 used_at = 1;
c0ebe874 9529 macro_build (NULL, "sltu", "d,v,t", AT, op[0], op[1]);
df58fc94
RS
9530 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
9531 &offset_expr, AT, ZERO);
252b5132 9532 }
252b5132
RH
9533 break;
9534
9535 case M_DDIV_3:
9536 dbl = 1;
9537 case M_DIV_3:
9538 s = "mflo";
9539 goto do_div3;
9540 case M_DREM_3:
9541 dbl = 1;
9542 case M_REM_3:
9543 s = "mfhi";
9544 do_div3:
c0ebe874 9545 if (op[2] == 0)
252b5132 9546 {
1661c76c 9547 as_warn (_("divide by zero"));
252b5132 9548 if (mips_trap)
df58fc94 9549 macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7);
252b5132 9550 else
df58fc94 9551 macro_build (NULL, "break", BRK_FMT, 7);
8fc2e39e 9552 break;
252b5132
RH
9553 }
9554
7d10b47d 9555 start_noreorder ();
252b5132
RH
9556 if (mips_trap)
9557 {
c0ebe874
RS
9558 macro_build (NULL, "teq", TRAP_FMT, op[2], ZERO, 7);
9559 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", op[1], op[2]);
252b5132
RH
9560 }
9561 else
9562 {
df58fc94
RS
9563 if (mips_opts.micromips)
9564 micromips_label_expr (&label_expr);
9565 else
9566 label_expr.X_add_number = 8;
c0ebe874
RS
9567 macro_build (&label_expr, "bne", "s,t,p", op[2], ZERO);
9568 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", op[1], op[2]);
df58fc94
RS
9569 macro_build (NULL, "break", BRK_FMT, 7);
9570 if (mips_opts.micromips)
9571 micromips_add_label ();
252b5132
RH
9572 }
9573 expr1.X_add_number = -1;
8fc2e39e 9574 used_at = 1;
f6a22291 9575 load_register (AT, &expr1, dbl);
df58fc94
RS
9576 if (mips_opts.micromips)
9577 micromips_label_expr (&label_expr);
9578 else
9579 label_expr.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16);
c0ebe874 9580 macro_build (&label_expr, "bne", "s,t,p", op[2], AT);
252b5132
RH
9581 if (dbl)
9582 {
9583 expr1.X_add_number = 1;
f6a22291 9584 load_register (AT, &expr1, dbl);
df58fc94 9585 macro_build (NULL, "dsll32", SHFT_FMT, AT, AT, 31);
252b5132
RH
9586 }
9587 else
9588 {
9589 expr1.X_add_number = 0x80000000;
df58fc94 9590 macro_build (&expr1, "lui", LUI_FMT, AT, BFD_RELOC_HI16);
252b5132
RH
9591 }
9592 if (mips_trap)
9593 {
c0ebe874 9594 macro_build (NULL, "teq", TRAP_FMT, op[1], AT, 6);
252b5132
RH
9595 /* We want to close the noreorder block as soon as possible, so
9596 that later insns are available for delay slot filling. */
7d10b47d 9597 end_noreorder ();
252b5132
RH
9598 }
9599 else
9600 {
df58fc94
RS
9601 if (mips_opts.micromips)
9602 micromips_label_expr (&label_expr);
9603 else
9604 label_expr.X_add_number = 8;
c0ebe874 9605 macro_build (&label_expr, "bne", "s,t,p", op[1], AT);
a605d2b3 9606 macro_build (NULL, "nop", "");
252b5132
RH
9607
9608 /* We want to close the noreorder block as soon as possible, so
9609 that later insns are available for delay slot filling. */
7d10b47d 9610 end_noreorder ();
252b5132 9611
df58fc94 9612 macro_build (NULL, "break", BRK_FMT, 6);
252b5132 9613 }
df58fc94
RS
9614 if (mips_opts.micromips)
9615 micromips_add_label ();
c0ebe874 9616 macro_build (NULL, s, MFHL_FMT, op[0]);
252b5132
RH
9617 break;
9618
9619 case M_DIV_3I:
9620 s = "div";
9621 s2 = "mflo";
9622 goto do_divi;
9623 case M_DIVU_3I:
9624 s = "divu";
9625 s2 = "mflo";
9626 goto do_divi;
9627 case M_REM_3I:
9628 s = "div";
9629 s2 = "mfhi";
9630 goto do_divi;
9631 case M_REMU_3I:
9632 s = "divu";
9633 s2 = "mfhi";
9634 goto do_divi;
9635 case M_DDIV_3I:
9636 dbl = 1;
9637 s = "ddiv";
9638 s2 = "mflo";
9639 goto do_divi;
9640 case M_DDIVU_3I:
9641 dbl = 1;
9642 s = "ddivu";
9643 s2 = "mflo";
9644 goto do_divi;
9645 case M_DREM_3I:
9646 dbl = 1;
9647 s = "ddiv";
9648 s2 = "mfhi";
9649 goto do_divi;
9650 case M_DREMU_3I:
9651 dbl = 1;
9652 s = "ddivu";
9653 s2 = "mfhi";
9654 do_divi:
b0e6f033 9655 if (imm_expr.X_add_number == 0)
252b5132 9656 {
1661c76c 9657 as_warn (_("divide by zero"));
252b5132 9658 if (mips_trap)
df58fc94 9659 macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7);
252b5132 9660 else
df58fc94 9661 macro_build (NULL, "break", BRK_FMT, 7);
8fc2e39e 9662 break;
252b5132 9663 }
b0e6f033 9664 if (imm_expr.X_add_number == 1)
252b5132
RH
9665 {
9666 if (strcmp (s2, "mflo") == 0)
c0ebe874 9667 move_register (op[0], op[1]);
252b5132 9668 else
c0ebe874 9669 move_register (op[0], ZERO);
8fc2e39e 9670 break;
252b5132 9671 }
b0e6f033 9672 if (imm_expr.X_add_number == -1 && s[strlen (s) - 1] != 'u')
252b5132
RH
9673 {
9674 if (strcmp (s2, "mflo") == 0)
c0ebe874 9675 macro_build (NULL, dbl ? "dneg" : "neg", "d,w", op[0], op[1]);
252b5132 9676 else
c0ebe874 9677 move_register (op[0], ZERO);
8fc2e39e 9678 break;
252b5132
RH
9679 }
9680
8fc2e39e 9681 used_at = 1;
67c0d1eb 9682 load_register (AT, &imm_expr, dbl);
c0ebe874
RS
9683 macro_build (NULL, s, "z,s,t", op[1], AT);
9684 macro_build (NULL, s2, MFHL_FMT, op[0]);
252b5132
RH
9685 break;
9686
9687 case M_DIVU_3:
9688 s = "divu";
9689 s2 = "mflo";
9690 goto do_divu3;
9691 case M_REMU_3:
9692 s = "divu";
9693 s2 = "mfhi";
9694 goto do_divu3;
9695 case M_DDIVU_3:
9696 s = "ddivu";
9697 s2 = "mflo";
9698 goto do_divu3;
9699 case M_DREMU_3:
9700 s = "ddivu";
9701 s2 = "mfhi";
9702 do_divu3:
7d10b47d 9703 start_noreorder ();
252b5132
RH
9704 if (mips_trap)
9705 {
c0ebe874
RS
9706 macro_build (NULL, "teq", TRAP_FMT, op[2], ZERO, 7);
9707 macro_build (NULL, s, "z,s,t", op[1], op[2]);
252b5132
RH
9708 /* We want to close the noreorder block as soon as possible, so
9709 that later insns are available for delay slot filling. */
7d10b47d 9710 end_noreorder ();
252b5132
RH
9711 }
9712 else
9713 {
df58fc94
RS
9714 if (mips_opts.micromips)
9715 micromips_label_expr (&label_expr);
9716 else
9717 label_expr.X_add_number = 8;
c0ebe874
RS
9718 macro_build (&label_expr, "bne", "s,t,p", op[2], ZERO);
9719 macro_build (NULL, s, "z,s,t", op[1], op[2]);
252b5132
RH
9720
9721 /* We want to close the noreorder block as soon as possible, so
9722 that later insns are available for delay slot filling. */
7d10b47d 9723 end_noreorder ();
df58fc94
RS
9724 macro_build (NULL, "break", BRK_FMT, 7);
9725 if (mips_opts.micromips)
9726 micromips_add_label ();
252b5132 9727 }
c0ebe874 9728 macro_build (NULL, s2, MFHL_FMT, op[0]);
8fc2e39e 9729 break;
252b5132 9730
1abe91b1
MR
9731 case M_DLCA_AB:
9732 dbl = 1;
9733 case M_LCA_AB:
9734 call = 1;
9735 goto do_la;
252b5132
RH
9736 case M_DLA_AB:
9737 dbl = 1;
9738 case M_LA_AB:
1abe91b1 9739 do_la:
252b5132
RH
9740 /* Load the address of a symbol into a register. If breg is not
9741 zero, we then add a base register to it. */
9742
c0ebe874 9743 breg = op[2];
3bec30a8
TS
9744 if (dbl && HAVE_32BIT_GPRS)
9745 as_warn (_("dla used to load 32-bit register"));
9746
90ecf173 9747 if (!dbl && HAVE_64BIT_OBJECTS)
3bec30a8
TS
9748 as_warn (_("la used to load 64-bit address"));
9749
f2ae14a1 9750 if (small_offset_p (0, align, 16))
0c11417f 9751 {
c0ebe874 9752 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", op[0], breg,
f2ae14a1 9753 -1, offset_reloc[0], offset_reloc[1], offset_reloc[2]);
8fc2e39e 9754 break;
0c11417f
MR
9755 }
9756
c0ebe874 9757 if (mips_opts.at && (op[0] == breg))
afdbd6d0
CD
9758 {
9759 tempreg = AT;
9760 used_at = 1;
9761 }
9762 else
c0ebe874 9763 tempreg = op[0];
afdbd6d0 9764
252b5132
RH
9765 if (offset_expr.X_op != O_symbol
9766 && offset_expr.X_op != O_constant)
9767 {
1661c76c 9768 as_bad (_("expression too complex"));
252b5132
RH
9769 offset_expr.X_op = O_constant;
9770 }
9771
252b5132 9772 if (offset_expr.X_op == O_constant)
aed1a261 9773 load_register (tempreg, &offset_expr, HAVE_64BIT_ADDRESSES);
252b5132
RH
9774 else if (mips_pic == NO_PIC)
9775 {
d6bc6245 9776 /* If this is a reference to a GP relative symbol, we want
cdf6fd85 9777 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
252b5132
RH
9778 Otherwise we want
9779 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
9780 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
9781 If we have a constant, we need two instructions anyhow,
d6bc6245 9782 so we may as well always use the latter form.
76b3015f 9783
6caf9ef4
TS
9784 With 64bit address space and a usable $at we want
9785 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
9786 lui $at,<sym> (BFD_RELOC_HI16_S)
9787 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
9788 daddiu $at,<sym> (BFD_RELOC_LO16)
9789 dsll32 $tempreg,0
9790 daddu $tempreg,$tempreg,$at
9791
9792 If $at is already in use, we use a path which is suboptimal
9793 on superscalar processors.
9794 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
9795 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
9796 dsll $tempreg,16
9797 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
9798 dsll $tempreg,16
9799 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
9800
9801 For GP relative symbols in 64bit address space we can use
9802 the same sequence as in 32bit address space. */
aed1a261 9803 if (HAVE_64BIT_SYMBOLS)
252b5132 9804 {
6caf9ef4
TS
9805 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
9806 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
9807 {
9808 relax_start (offset_expr.X_add_symbol);
9809 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
9810 tempreg, mips_gp_register, BFD_RELOC_GPREL16);
9811 relax_switch ();
9812 }
d6bc6245 9813
741fe287 9814 if (used_at == 0 && mips_opts.at)
98d3f06f 9815 {
df58fc94 9816 macro_build (&offset_expr, "lui", LUI_FMT,
17a2f251 9817 tempreg, BFD_RELOC_MIPS_HIGHEST);
df58fc94 9818 macro_build (&offset_expr, "lui", LUI_FMT,
17a2f251 9819 AT, BFD_RELOC_HI16_S);
67c0d1eb 9820 macro_build (&offset_expr, "daddiu", "t,r,j",
17a2f251 9821 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
67c0d1eb 9822 macro_build (&offset_expr, "daddiu", "t,r,j",
17a2f251 9823 AT, AT, BFD_RELOC_LO16);
df58fc94 9824 macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0);
67c0d1eb 9825 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT);
98d3f06f
KH
9826 used_at = 1;
9827 }
9828 else
9829 {
df58fc94 9830 macro_build (&offset_expr, "lui", LUI_FMT,
17a2f251 9831 tempreg, BFD_RELOC_MIPS_HIGHEST);
67c0d1eb 9832 macro_build (&offset_expr, "daddiu", "t,r,j",
17a2f251 9833 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
df58fc94 9834 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
67c0d1eb 9835 macro_build (&offset_expr, "daddiu", "t,r,j",
17a2f251 9836 tempreg, tempreg, BFD_RELOC_HI16_S);
df58fc94 9837 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
67c0d1eb 9838 macro_build (&offset_expr, "daddiu", "t,r,j",
17a2f251 9839 tempreg, tempreg, BFD_RELOC_LO16);
98d3f06f 9840 }
6caf9ef4
TS
9841
9842 if (mips_relax.sequence)
9843 relax_end ();
98d3f06f
KH
9844 }
9845 else
9846 {
9847 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
6caf9ef4 9848 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
98d3f06f 9849 {
4d7206a2 9850 relax_start (offset_expr.X_add_symbol);
67c0d1eb
RS
9851 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
9852 tempreg, mips_gp_register, BFD_RELOC_GPREL16);
4d7206a2 9853 relax_switch ();
98d3f06f 9854 }
6943caf0 9855 if (!IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
1661c76c 9856 as_bad (_("offset too large"));
67c0d1eb
RS
9857 macro_build_lui (&offset_expr, tempreg);
9858 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
9859 tempreg, tempreg, BFD_RELOC_LO16);
4d7206a2
RS
9860 if (mips_relax.sequence)
9861 relax_end ();
98d3f06f 9862 }
252b5132 9863 }
0a44bf69 9864 else if (!mips_big_got && !HAVE_NEWABI)
252b5132 9865 {
9117d219
NC
9866 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
9867
252b5132
RH
9868 /* If this is a reference to an external symbol, and there
9869 is no constant, we want
9870 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
1abe91b1 9871 or for lca or if tempreg is PIC_CALL_REG
9117d219 9872 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
252b5132
RH
9873 For a local symbol, we want
9874 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9875 nop
9876 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
9877
9878 If we have a small constant, and this is a reference to
9879 an external symbol, we want
9880 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9881 nop
9882 addiu $tempreg,$tempreg,<constant>
9883 For a local symbol, we want the same instruction
9884 sequence, but we output a BFD_RELOC_LO16 reloc on the
9885 addiu instruction.
9886
9887 If we have a large constant, and this is a reference to
9888 an external symbol, we want
9889 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9890 lui $at,<hiconstant>
9891 addiu $at,$at,<loconstant>
9892 addu $tempreg,$tempreg,$at
9893 For a local symbol, we want the same instruction
9894 sequence, but we output a BFD_RELOC_LO16 reloc on the
ed6fb7bd 9895 addiu instruction.
ed6fb7bd
SC
9896 */
9897
4d7206a2 9898 if (offset_expr.X_add_number == 0)
252b5132 9899 {
0a44bf69
RS
9900 if (mips_pic == SVR4_PIC
9901 && breg == 0
9902 && (call || tempreg == PIC_CALL_REG))
4d7206a2
RS
9903 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16;
9904
9905 relax_start (offset_expr.X_add_symbol);
67c0d1eb
RS
9906 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
9907 lw_reloc_type, mips_gp_register);
4d7206a2 9908 if (breg != 0)
252b5132
RH
9909 {
9910 /* We're going to put in an addu instruction using
9911 tempreg, so we may as well insert the nop right
9912 now. */
269137b2 9913 load_delay_nop ();
252b5132 9914 }
4d7206a2 9915 relax_switch ();
67c0d1eb
RS
9916 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
9917 tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register);
269137b2 9918 load_delay_nop ();
67c0d1eb
RS
9919 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
9920 tempreg, tempreg, BFD_RELOC_LO16);
4d7206a2 9921 relax_end ();
252b5132
RH
9922 /* FIXME: If breg == 0, and the next instruction uses
9923 $tempreg, then if this variant case is used an extra
9924 nop will be generated. */
9925 }
4d7206a2
RS
9926 else if (offset_expr.X_add_number >= -0x8000
9927 && offset_expr.X_add_number < 0x8000)
252b5132 9928 {
67c0d1eb 9929 load_got_offset (tempreg, &offset_expr);
269137b2 9930 load_delay_nop ();
67c0d1eb 9931 add_got_offset (tempreg, &offset_expr);
252b5132
RH
9932 }
9933 else
9934 {
4d7206a2
RS
9935 expr1.X_add_number = offset_expr.X_add_number;
9936 offset_expr.X_add_number =
43c0598f 9937 SEXT_16BIT (offset_expr.X_add_number);
67c0d1eb 9938 load_got_offset (tempreg, &offset_expr);
f6a22291 9939 offset_expr.X_add_number = expr1.X_add_number;
252b5132
RH
9940 /* If we are going to add in a base register, and the
9941 target register and the base register are the same,
9942 then we are using AT as a temporary register. Since
9943 we want to load the constant into AT, we add our
9944 current AT (from the global offset table) and the
9945 register into the register now, and pretend we were
9946 not using a base register. */
c0ebe874 9947 if (breg == op[0])
252b5132 9948 {
269137b2 9949 load_delay_nop ();
67c0d1eb 9950 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
c0ebe874 9951 op[0], AT, breg);
252b5132 9952 breg = 0;
c0ebe874 9953 tempreg = op[0];
252b5132 9954 }
f6a22291 9955 add_got_offset_hilo (tempreg, &offset_expr, AT);
252b5132
RH
9956 used_at = 1;
9957 }
9958 }
0a44bf69 9959 else if (!mips_big_got && HAVE_NEWABI)
f5040a92 9960 {
67c0d1eb 9961 int add_breg_early = 0;
f5040a92
AO
9962
9963 /* If this is a reference to an external, and there is no
9964 constant, or local symbol (*), with or without a
9965 constant, we want
9966 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
1abe91b1 9967 or for lca or if tempreg is PIC_CALL_REG
f5040a92
AO
9968 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
9969
9970 If we have a small constant, and this is a reference to
9971 an external symbol, we want
9972 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
9973 addiu $tempreg,$tempreg,<constant>
9974
9975 If we have a large constant, and this is a reference to
9976 an external symbol, we want
9977 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
9978 lui $at,<hiconstant>
9979 addiu $at,$at,<loconstant>
9980 addu $tempreg,$tempreg,$at
9981
9982 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
9983 local symbols, even though it introduces an additional
9984 instruction. */
9985
f5040a92
AO
9986 if (offset_expr.X_add_number)
9987 {
4d7206a2 9988 expr1.X_add_number = offset_expr.X_add_number;
f5040a92
AO
9989 offset_expr.X_add_number = 0;
9990
4d7206a2 9991 relax_start (offset_expr.X_add_symbol);
67c0d1eb
RS
9992 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
9993 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
f5040a92
AO
9994
9995 if (expr1.X_add_number >= -0x8000
9996 && expr1.X_add_number < 0x8000)
9997 {
67c0d1eb
RS
9998 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
9999 tempreg, tempreg, BFD_RELOC_LO16);
f5040a92 10000 }
ecd13cd3 10001 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
f5040a92 10002 {
c0ebe874
RS
10003 unsigned int dreg;
10004
f5040a92
AO
10005 /* If we are going to add in a base register, and the
10006 target register and the base register are the same,
10007 then we are using AT as a temporary register. Since
10008 we want to load the constant into AT, we add our
10009 current AT (from the global offset table) and the
10010 register into the register now, and pretend we were
10011 not using a base register. */
c0ebe874 10012 if (breg != op[0])
f5040a92
AO
10013 dreg = tempreg;
10014 else
10015 {
9c2799c2 10016 gas_assert (tempreg == AT);
67c0d1eb 10017 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
c0ebe874
RS
10018 op[0], AT, breg);
10019 dreg = op[0];
67c0d1eb 10020 add_breg_early = 1;
f5040a92
AO
10021 }
10022
f6a22291 10023 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
67c0d1eb 10024 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
17a2f251 10025 dreg, dreg, AT);
f5040a92 10026
f5040a92
AO
10027 used_at = 1;
10028 }
10029 else
10030 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
10031
4d7206a2 10032 relax_switch ();
f5040a92
AO
10033 offset_expr.X_add_number = expr1.X_add_number;
10034
67c0d1eb
RS
10035 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
10036 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
10037 if (add_breg_early)
f5040a92 10038 {
67c0d1eb 10039 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
c0ebe874 10040 op[0], tempreg, breg);
f5040a92 10041 breg = 0;
c0ebe874 10042 tempreg = op[0];
f5040a92 10043 }
4d7206a2 10044 relax_end ();
f5040a92 10045 }
4d7206a2 10046 else if (breg == 0 && (call || tempreg == PIC_CALL_REG))
f5040a92 10047 {
4d7206a2 10048 relax_start (offset_expr.X_add_symbol);
67c0d1eb
RS
10049 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
10050 BFD_RELOC_MIPS_CALL16, mips_gp_register);
4d7206a2 10051 relax_switch ();
67c0d1eb
RS
10052 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
10053 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
4d7206a2 10054 relax_end ();
f5040a92 10055 }
4d7206a2 10056 else
f5040a92 10057 {
67c0d1eb
RS
10058 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
10059 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
f5040a92
AO
10060 }
10061 }
0a44bf69 10062 else if (mips_big_got && !HAVE_NEWABI)
252b5132 10063 {
67c0d1eb 10064 int gpdelay;
9117d219
NC
10065 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
10066 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
ed6fb7bd 10067 int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
252b5132
RH
10068
10069 /* This is the large GOT case. If this is a reference to an
10070 external symbol, and there is no constant, we want
10071 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10072 addu $tempreg,$tempreg,$gp
10073 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
1abe91b1 10074 or for lca or if tempreg is PIC_CALL_REG
9117d219
NC
10075 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
10076 addu $tempreg,$tempreg,$gp
10077 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
252b5132
RH
10078 For a local symbol, we want
10079 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10080 nop
10081 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
10082
10083 If we have a small constant, and this is a reference to
10084 an external symbol, we want
10085 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10086 addu $tempreg,$tempreg,$gp
10087 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10088 nop
10089 addiu $tempreg,$tempreg,<constant>
10090 For a local symbol, we want
10091 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10092 nop
10093 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
10094
10095 If we have a large constant, and this is a reference to
10096 an external symbol, we want
10097 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10098 addu $tempreg,$tempreg,$gp
10099 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10100 lui $at,<hiconstant>
10101 addiu $at,$at,<loconstant>
10102 addu $tempreg,$tempreg,$at
10103 For a local symbol, we want
10104 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10105 lui $at,<hiconstant>
10106 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
10107 addu $tempreg,$tempreg,$at
f5040a92 10108 */
438c16b8 10109
252b5132
RH
10110 expr1.X_add_number = offset_expr.X_add_number;
10111 offset_expr.X_add_number = 0;
4d7206a2 10112 relax_start (offset_expr.X_add_symbol);
67c0d1eb 10113 gpdelay = reg_needs_delay (mips_gp_register);
1abe91b1
MR
10114 if (expr1.X_add_number == 0 && breg == 0
10115 && (call || tempreg == PIC_CALL_REG))
9117d219
NC
10116 {
10117 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
10118 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
10119 }
df58fc94 10120 macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type);
67c0d1eb 10121 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
17a2f251 10122 tempreg, tempreg, mips_gp_register);
67c0d1eb 10123 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
17a2f251 10124 tempreg, lw_reloc_type, tempreg);
252b5132
RH
10125 if (expr1.X_add_number == 0)
10126 {
67c0d1eb 10127 if (breg != 0)
252b5132
RH
10128 {
10129 /* We're going to put in an addu instruction using
10130 tempreg, so we may as well insert the nop right
10131 now. */
269137b2 10132 load_delay_nop ();
252b5132 10133 }
252b5132
RH
10134 }
10135 else if (expr1.X_add_number >= -0x8000
10136 && expr1.X_add_number < 0x8000)
10137 {
269137b2 10138 load_delay_nop ();
67c0d1eb 10139 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
17a2f251 10140 tempreg, tempreg, BFD_RELOC_LO16);
252b5132
RH
10141 }
10142 else
10143 {
c0ebe874
RS
10144 unsigned int dreg;
10145
252b5132
RH
10146 /* If we are going to add in a base register, and the
10147 target register and the base register are the same,
10148 then we are using AT as a temporary register. Since
10149 we want to load the constant into AT, we add our
10150 current AT (from the global offset table) and the
10151 register into the register now, and pretend we were
10152 not using a base register. */
c0ebe874 10153 if (breg != op[0])
67c0d1eb 10154 dreg = tempreg;
252b5132
RH
10155 else
10156 {
9c2799c2 10157 gas_assert (tempreg == AT);
269137b2 10158 load_delay_nop ();
67c0d1eb 10159 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
c0ebe874
RS
10160 op[0], AT, breg);
10161 dreg = op[0];
252b5132
RH
10162 }
10163
f6a22291 10164 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
67c0d1eb 10165 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
252b5132 10166
252b5132
RH
10167 used_at = 1;
10168 }
43c0598f 10169 offset_expr.X_add_number = SEXT_16BIT (expr1.X_add_number);
4d7206a2 10170 relax_switch ();
252b5132 10171
67c0d1eb 10172 if (gpdelay)
252b5132
RH
10173 {
10174 /* This is needed because this instruction uses $gp, but
f5040a92 10175 the first instruction on the main stream does not. */
67c0d1eb 10176 macro_build (NULL, "nop", "");
252b5132 10177 }
ed6fb7bd 10178
67c0d1eb
RS
10179 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
10180 local_reloc_type, mips_gp_register);
f5040a92 10181 if (expr1.X_add_number >= -0x8000
252b5132
RH
10182 && expr1.X_add_number < 0x8000)
10183 {
269137b2 10184 load_delay_nop ();
67c0d1eb
RS
10185 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
10186 tempreg, tempreg, BFD_RELOC_LO16);
252b5132 10187 /* FIXME: If add_number is 0, and there was no base
f5040a92
AO
10188 register, the external symbol case ended with a load,
10189 so if the symbol turns out to not be external, and
10190 the next instruction uses tempreg, an unnecessary nop
10191 will be inserted. */
252b5132
RH
10192 }
10193 else
10194 {
c0ebe874 10195 if (breg == op[0])
252b5132
RH
10196 {
10197 /* We must add in the base register now, as in the
f5040a92 10198 external symbol case. */
9c2799c2 10199 gas_assert (tempreg == AT);
269137b2 10200 load_delay_nop ();
67c0d1eb 10201 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
c0ebe874
RS
10202 op[0], AT, breg);
10203 tempreg = op[0];
252b5132 10204 /* We set breg to 0 because we have arranged to add
f5040a92 10205 it in in both cases. */
252b5132
RH
10206 breg = 0;
10207 }
10208
67c0d1eb
RS
10209 macro_build_lui (&expr1, AT);
10210 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
17a2f251 10211 AT, AT, BFD_RELOC_LO16);
67c0d1eb 10212 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
17a2f251 10213 tempreg, tempreg, AT);
8fc2e39e 10214 used_at = 1;
252b5132 10215 }
4d7206a2 10216 relax_end ();
252b5132 10217 }
0a44bf69 10218 else if (mips_big_got && HAVE_NEWABI)
f5040a92 10219 {
f5040a92
AO
10220 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
10221 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
67c0d1eb 10222 int add_breg_early = 0;
f5040a92
AO
10223
10224 /* This is the large GOT case. If this is a reference to an
10225 external symbol, and there is no constant, we want
10226 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10227 add $tempreg,$tempreg,$gp
10228 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
1abe91b1 10229 or for lca or if tempreg is PIC_CALL_REG
f5040a92
AO
10230 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
10231 add $tempreg,$tempreg,$gp
10232 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
10233
10234 If we have a small constant, and this is a reference to
10235 an external symbol, we want
10236 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10237 add $tempreg,$tempreg,$gp
10238 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10239 addi $tempreg,$tempreg,<constant>
10240
10241 If we have a large constant, and this is a reference to
10242 an external symbol, we want
10243 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10244 addu $tempreg,$tempreg,$gp
10245 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10246 lui $at,<hiconstant>
10247 addi $at,$at,<loconstant>
10248 add $tempreg,$tempreg,$at
10249
10250 If we have NewABI, and we know it's a local symbol, we want
10251 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
10252 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
10253 otherwise we have to resort to GOT_HI16/GOT_LO16. */
10254
4d7206a2 10255 relax_start (offset_expr.X_add_symbol);
f5040a92 10256
4d7206a2 10257 expr1.X_add_number = offset_expr.X_add_number;
f5040a92
AO
10258 offset_expr.X_add_number = 0;
10259
1abe91b1
MR
10260 if (expr1.X_add_number == 0 && breg == 0
10261 && (call || tempreg == PIC_CALL_REG))
f5040a92
AO
10262 {
10263 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
10264 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
10265 }
df58fc94 10266 macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type);
67c0d1eb 10267 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
17a2f251 10268 tempreg, tempreg, mips_gp_register);
67c0d1eb
RS
10269 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
10270 tempreg, lw_reloc_type, tempreg);
f5040a92
AO
10271
10272 if (expr1.X_add_number == 0)
4d7206a2 10273 ;
f5040a92
AO
10274 else if (expr1.X_add_number >= -0x8000
10275 && expr1.X_add_number < 0x8000)
10276 {
67c0d1eb 10277 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
17a2f251 10278 tempreg, tempreg, BFD_RELOC_LO16);
f5040a92 10279 }
ecd13cd3 10280 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
f5040a92 10281 {
c0ebe874
RS
10282 unsigned int dreg;
10283
f5040a92
AO
10284 /* If we are going to add in a base register, and the
10285 target register and the base register are the same,
10286 then we are using AT as a temporary register. Since
10287 we want to load the constant into AT, we add our
10288 current AT (from the global offset table) and the
10289 register into the register now, and pretend we were
10290 not using a base register. */
c0ebe874 10291 if (breg != op[0])
f5040a92
AO
10292 dreg = tempreg;
10293 else
10294 {
9c2799c2 10295 gas_assert (tempreg == AT);
67c0d1eb 10296 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
c0ebe874
RS
10297 op[0], AT, breg);
10298 dreg = op[0];
67c0d1eb 10299 add_breg_early = 1;
f5040a92
AO
10300 }
10301
f6a22291 10302 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
67c0d1eb 10303 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
f5040a92 10304
f5040a92
AO
10305 used_at = 1;
10306 }
10307 else
10308 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
10309
4d7206a2 10310 relax_switch ();
f5040a92 10311 offset_expr.X_add_number = expr1.X_add_number;
67c0d1eb
RS
10312 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
10313 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
10314 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
10315 tempreg, BFD_RELOC_MIPS_GOT_OFST);
10316 if (add_breg_early)
f5040a92 10317 {
67c0d1eb 10318 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
c0ebe874 10319 op[0], tempreg, breg);
f5040a92 10320 breg = 0;
c0ebe874 10321 tempreg = op[0];
f5040a92 10322 }
4d7206a2 10323 relax_end ();
f5040a92 10324 }
252b5132
RH
10325 else
10326 abort ();
10327
10328 if (breg != 0)
c0ebe874 10329 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", op[0], tempreg, breg);
252b5132
RH
10330 break;
10331
52b6b6b9 10332 case M_MSGSND:
df58fc94 10333 gas_assert (!mips_opts.micromips);
c0ebe874 10334 macro_build (NULL, "c2", "C", (op[0] << 16) | 0x01);
c7af4273 10335 break;
52b6b6b9
JM
10336
10337 case M_MSGLD:
df58fc94 10338 gas_assert (!mips_opts.micromips);
c8276761 10339 macro_build (NULL, "c2", "C", 0x02);
c7af4273 10340 break;
52b6b6b9
JM
10341
10342 case M_MSGLD_T:
df58fc94 10343 gas_assert (!mips_opts.micromips);
c0ebe874 10344 macro_build (NULL, "c2", "C", (op[0] << 16) | 0x02);
c7af4273 10345 break;
52b6b6b9
JM
10346
10347 case M_MSGWAIT:
df58fc94 10348 gas_assert (!mips_opts.micromips);
52b6b6b9 10349 macro_build (NULL, "c2", "C", 3);
c7af4273 10350 break;
52b6b6b9
JM
10351
10352 case M_MSGWAIT_T:
df58fc94 10353 gas_assert (!mips_opts.micromips);
c0ebe874 10354 macro_build (NULL, "c2", "C", (op[0] << 16) | 0x03);
c7af4273 10355 break;
52b6b6b9 10356
252b5132
RH
10357 case M_J_A:
10358 /* The j instruction may not be used in PIC code, since it
10359 requires an absolute address. We convert it to a b
10360 instruction. */
10361 if (mips_pic == NO_PIC)
67c0d1eb 10362 macro_build (&offset_expr, "j", "a");
252b5132 10363 else
67c0d1eb 10364 macro_build (&offset_expr, "b", "p");
8fc2e39e 10365 break;
252b5132
RH
10366
10367 /* The jal instructions must be handled as macros because when
10368 generating PIC code they expand to multi-instruction
10369 sequences. Normally they are simple instructions. */
df58fc94 10370 case M_JALS_1:
c0ebe874
RS
10371 op[1] = op[0];
10372 op[0] = RA;
df58fc94
RS
10373 /* Fall through. */
10374 case M_JALS_2:
10375 gas_assert (mips_opts.micromips);
833794fc
MR
10376 if (mips_opts.insn32)
10377 {
1661c76c 10378 as_bad (_("opcode not supported in the `insn32' mode `%s'"), str);
833794fc
MR
10379 break;
10380 }
df58fc94
RS
10381 jals = 1;
10382 goto jal;
252b5132 10383 case M_JAL_1:
c0ebe874
RS
10384 op[1] = op[0];
10385 op[0] = RA;
252b5132
RH
10386 /* Fall through. */
10387 case M_JAL_2:
df58fc94 10388 jal:
3e722fb5 10389 if (mips_pic == NO_PIC)
df58fc94
RS
10390 {
10391 s = jals ? "jalrs" : "jalr";
e64af278 10392 if (mips_opts.micromips
833794fc 10393 && !mips_opts.insn32
c0ebe874 10394 && op[0] == RA
e64af278 10395 && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
c0ebe874 10396 macro_build (NULL, s, "mj", op[1]);
df58fc94 10397 else
c0ebe874 10398 macro_build (NULL, s, JALR_FMT, op[0], op[1]);
df58fc94 10399 }
0a44bf69 10400 else
252b5132 10401 {
df58fc94
RS
10402 int cprestore = (mips_pic == SVR4_PIC && !HAVE_NEWABI
10403 && mips_cprestore_offset >= 0);
10404
c0ebe874 10405 if (op[1] != PIC_CALL_REG)
252b5132 10406 as_warn (_("MIPS PIC call to register other than $25"));
bdaaa2e1 10407
833794fc
MR
10408 s = ((mips_opts.micromips
10409 && !mips_opts.insn32
10410 && (!mips_opts.noreorder || cprestore))
df58fc94 10411 ? "jalrs" : "jalr");
e64af278 10412 if (mips_opts.micromips
833794fc 10413 && !mips_opts.insn32
c0ebe874 10414 && op[0] == RA
e64af278 10415 && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
c0ebe874 10416 macro_build (NULL, s, "mj", op[1]);
df58fc94 10417 else
c0ebe874 10418 macro_build (NULL, s, JALR_FMT, op[0], op[1]);
0a44bf69 10419 if (mips_pic == SVR4_PIC && !HAVE_NEWABI)
252b5132 10420 {
6478892d 10421 if (mips_cprestore_offset < 0)
1661c76c 10422 as_warn (_("no .cprestore pseudo-op used in PIC code"));
6478892d
TS
10423 else
10424 {
90ecf173 10425 if (!mips_frame_reg_valid)
7a621144 10426 {
1661c76c 10427 as_warn (_("no .frame pseudo-op used in PIC code"));
7a621144
DJ
10428 /* Quiet this warning. */
10429 mips_frame_reg_valid = 1;
10430 }
90ecf173 10431 if (!mips_cprestore_valid)
7a621144 10432 {
1661c76c 10433 as_warn (_("no .cprestore pseudo-op used in PIC code"));
7a621144
DJ
10434 /* Quiet this warning. */
10435 mips_cprestore_valid = 1;
10436 }
d3fca0b5
MR
10437 if (mips_opts.noreorder)
10438 macro_build (NULL, "nop", "");
6478892d 10439 expr1.X_add_number = mips_cprestore_offset;
67c0d1eb 10440 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
f899b4b8 10441 mips_gp_register,
256ab948
TS
10442 mips_frame_reg,
10443 HAVE_64BIT_ADDRESSES);
6478892d 10444 }
252b5132
RH
10445 }
10446 }
252b5132 10447
8fc2e39e 10448 break;
252b5132 10449
df58fc94
RS
10450 case M_JALS_A:
10451 gas_assert (mips_opts.micromips);
833794fc
MR
10452 if (mips_opts.insn32)
10453 {
1661c76c 10454 as_bad (_("opcode not supported in the `insn32' mode `%s'"), str);
833794fc
MR
10455 break;
10456 }
df58fc94
RS
10457 jals = 1;
10458 /* Fall through. */
252b5132
RH
10459 case M_JAL_A:
10460 if (mips_pic == NO_PIC)
df58fc94 10461 macro_build (&offset_expr, jals ? "jals" : "jal", "a");
252b5132
RH
10462 else if (mips_pic == SVR4_PIC)
10463 {
10464 /* If this is a reference to an external symbol, and we are
10465 using a small GOT, we want
10466 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
10467 nop
f9419b05 10468 jalr $ra,$25
252b5132
RH
10469 nop
10470 lw $gp,cprestore($sp)
10471 The cprestore value is set using the .cprestore
10472 pseudo-op. If we are using a big GOT, we want
10473 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
10474 addu $25,$25,$gp
10475 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
10476 nop
f9419b05 10477 jalr $ra,$25
252b5132
RH
10478 nop
10479 lw $gp,cprestore($sp)
10480 If the symbol is not external, we want
10481 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10482 nop
10483 addiu $25,$25,<sym> (BFD_RELOC_LO16)
f9419b05 10484 jalr $ra,$25
252b5132 10485 nop
438c16b8 10486 lw $gp,cprestore($sp)
f5040a92
AO
10487
10488 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
10489 sequences above, minus nops, unless the symbol is local,
10490 which enables us to use GOT_PAGE/GOT_OFST (big got) or
10491 GOT_DISP. */
438c16b8 10492 if (HAVE_NEWABI)
252b5132 10493 {
90ecf173 10494 if (!mips_big_got)
f5040a92 10495 {
4d7206a2 10496 relax_start (offset_expr.X_add_symbol);
67c0d1eb
RS
10497 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
10498 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
f5040a92 10499 mips_gp_register);
4d7206a2 10500 relax_switch ();
67c0d1eb
RS
10501 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
10502 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_DISP,
4d7206a2
RS
10503 mips_gp_register);
10504 relax_end ();
f5040a92
AO
10505 }
10506 else
10507 {
4d7206a2 10508 relax_start (offset_expr.X_add_symbol);
df58fc94 10509 macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG,
67c0d1eb
RS
10510 BFD_RELOC_MIPS_CALL_HI16);
10511 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
10512 PIC_CALL_REG, mips_gp_register);
10513 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
10514 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
10515 PIC_CALL_REG);
4d7206a2 10516 relax_switch ();
67c0d1eb
RS
10517 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
10518 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_PAGE,
10519 mips_gp_register);
10520 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
10521 PIC_CALL_REG, PIC_CALL_REG,
17a2f251 10522 BFD_RELOC_MIPS_GOT_OFST);
4d7206a2 10523 relax_end ();
f5040a92 10524 }
684022ea 10525
df58fc94 10526 macro_build_jalr (&offset_expr, 0);
252b5132
RH
10527 }
10528 else
10529 {
4d7206a2 10530 relax_start (offset_expr.X_add_symbol);
90ecf173 10531 if (!mips_big_got)
438c16b8 10532 {
67c0d1eb
RS
10533 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
10534 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
17a2f251 10535 mips_gp_register);
269137b2 10536 load_delay_nop ();
4d7206a2 10537 relax_switch ();
438c16b8 10538 }
252b5132 10539 else
252b5132 10540 {
67c0d1eb
RS
10541 int gpdelay;
10542
10543 gpdelay = reg_needs_delay (mips_gp_register);
df58fc94 10544 macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG,
67c0d1eb
RS
10545 BFD_RELOC_MIPS_CALL_HI16);
10546 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
10547 PIC_CALL_REG, mips_gp_register);
10548 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
10549 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
10550 PIC_CALL_REG);
269137b2 10551 load_delay_nop ();
4d7206a2 10552 relax_switch ();
67c0d1eb
RS
10553 if (gpdelay)
10554 macro_build (NULL, "nop", "");
252b5132 10555 }
67c0d1eb
RS
10556 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
10557 PIC_CALL_REG, BFD_RELOC_MIPS_GOT16,
4d7206a2 10558 mips_gp_register);
269137b2 10559 load_delay_nop ();
67c0d1eb
RS
10560 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
10561 PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16);
4d7206a2 10562 relax_end ();
df58fc94 10563 macro_build_jalr (&offset_expr, mips_cprestore_offset >= 0);
438c16b8 10564
6478892d 10565 if (mips_cprestore_offset < 0)
1661c76c 10566 as_warn (_("no .cprestore pseudo-op used in PIC code"));
6478892d
TS
10567 else
10568 {
90ecf173 10569 if (!mips_frame_reg_valid)
7a621144 10570 {
1661c76c 10571 as_warn (_("no .frame pseudo-op used in PIC code"));
7a621144
DJ
10572 /* Quiet this warning. */
10573 mips_frame_reg_valid = 1;
10574 }
90ecf173 10575 if (!mips_cprestore_valid)
7a621144 10576 {
1661c76c 10577 as_warn (_("no .cprestore pseudo-op used in PIC code"));
7a621144
DJ
10578 /* Quiet this warning. */
10579 mips_cprestore_valid = 1;
10580 }
6478892d 10581 if (mips_opts.noreorder)
67c0d1eb 10582 macro_build (NULL, "nop", "");
6478892d 10583 expr1.X_add_number = mips_cprestore_offset;
67c0d1eb 10584 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
f899b4b8 10585 mips_gp_register,
256ab948
TS
10586 mips_frame_reg,
10587 HAVE_64BIT_ADDRESSES);
6478892d 10588 }
252b5132
RH
10589 }
10590 }
0a44bf69 10591 else if (mips_pic == VXWORKS_PIC)
1661c76c 10592 as_bad (_("non-PIC jump used in PIC library"));
252b5132
RH
10593 else
10594 abort ();
10595
8fc2e39e 10596 break;
252b5132 10597
7f3c4072 10598 case M_LBUE_AB:
7f3c4072
CM
10599 s = "lbue";
10600 fmt = "t,+j(b)";
10601 offbits = 9;
10602 goto ld_st;
10603 case M_LHUE_AB:
7f3c4072
CM
10604 s = "lhue";
10605 fmt = "t,+j(b)";
10606 offbits = 9;
10607 goto ld_st;
10608 case M_LBE_AB:
7f3c4072
CM
10609 s = "lbe";
10610 fmt = "t,+j(b)";
10611 offbits = 9;
10612 goto ld_st;
10613 case M_LHE_AB:
7f3c4072
CM
10614 s = "lhe";
10615 fmt = "t,+j(b)";
10616 offbits = 9;
10617 goto ld_st;
10618 case M_LLE_AB:
7f3c4072
CM
10619 s = "lle";
10620 fmt = "t,+j(b)";
10621 offbits = 9;
10622 goto ld_st;
10623 case M_LWE_AB:
7f3c4072
CM
10624 s = "lwe";
10625 fmt = "t,+j(b)";
10626 offbits = 9;
10627 goto ld_st;
10628 case M_LWLE_AB:
7f3c4072
CM
10629 s = "lwle";
10630 fmt = "t,+j(b)";
10631 offbits = 9;
10632 goto ld_st;
10633 case M_LWRE_AB:
7f3c4072
CM
10634 s = "lwre";
10635 fmt = "t,+j(b)";
10636 offbits = 9;
10637 goto ld_st;
10638 case M_SBE_AB:
7f3c4072
CM
10639 s = "sbe";
10640 fmt = "t,+j(b)";
10641 offbits = 9;
10642 goto ld_st;
10643 case M_SCE_AB:
7f3c4072
CM
10644 s = "sce";
10645 fmt = "t,+j(b)";
10646 offbits = 9;
10647 goto ld_st;
10648 case M_SHE_AB:
7f3c4072
CM
10649 s = "she";
10650 fmt = "t,+j(b)";
10651 offbits = 9;
10652 goto ld_st;
10653 case M_SWE_AB:
7f3c4072
CM
10654 s = "swe";
10655 fmt = "t,+j(b)";
10656 offbits = 9;
10657 goto ld_st;
10658 case M_SWLE_AB:
7f3c4072
CM
10659 s = "swle";
10660 fmt = "t,+j(b)";
10661 offbits = 9;
10662 goto ld_st;
10663 case M_SWRE_AB:
7f3c4072
CM
10664 s = "swre";
10665 fmt = "t,+j(b)";
10666 offbits = 9;
10667 goto ld_st;
dec0624d 10668 case M_ACLR_AB:
dec0624d 10669 s = "aclr";
dec0624d 10670 fmt = "\\,~(b)";
7f3c4072 10671 offbits = 12;
dec0624d
MR
10672 goto ld_st;
10673 case M_ASET_AB:
dec0624d 10674 s = "aset";
dec0624d 10675 fmt = "\\,~(b)";
7f3c4072 10676 offbits = 12;
dec0624d 10677 goto ld_st;
252b5132
RH
10678 case M_LB_AB:
10679 s = "lb";
df58fc94 10680 fmt = "t,o(b)";
252b5132
RH
10681 goto ld;
10682 case M_LBU_AB:
10683 s = "lbu";
df58fc94 10684 fmt = "t,o(b)";
252b5132
RH
10685 goto ld;
10686 case M_LH_AB:
10687 s = "lh";
df58fc94 10688 fmt = "t,o(b)";
252b5132
RH
10689 goto ld;
10690 case M_LHU_AB:
10691 s = "lhu";
df58fc94 10692 fmt = "t,o(b)";
252b5132
RH
10693 goto ld;
10694 case M_LW_AB:
10695 s = "lw";
df58fc94 10696 fmt = "t,o(b)";
252b5132
RH
10697 goto ld;
10698 case M_LWC0_AB:
df58fc94 10699 gas_assert (!mips_opts.micromips);
252b5132 10700 s = "lwc0";
df58fc94 10701 fmt = "E,o(b)";
bdaaa2e1 10702 /* Itbl support may require additional care here. */
252b5132 10703 coproc = 1;
df58fc94 10704 goto ld_st;
252b5132
RH
10705 case M_LWC1_AB:
10706 s = "lwc1";
df58fc94 10707 fmt = "T,o(b)";
bdaaa2e1 10708 /* Itbl support may require additional care here. */
252b5132 10709 coproc = 1;
df58fc94 10710 goto ld_st;
252b5132
RH
10711 case M_LWC2_AB:
10712 s = "lwc2";
df58fc94 10713 fmt = COP12_FMT;
7f3c4072 10714 offbits = (mips_opts.micromips ? 12 : 16);
bdaaa2e1 10715 /* Itbl support may require additional care here. */
252b5132 10716 coproc = 1;
df58fc94 10717 goto ld_st;
252b5132 10718 case M_LWC3_AB:
df58fc94 10719 gas_assert (!mips_opts.micromips);
252b5132 10720 s = "lwc3";
df58fc94 10721 fmt = "E,o(b)";
bdaaa2e1 10722 /* Itbl support may require additional care here. */
252b5132 10723 coproc = 1;
df58fc94 10724 goto ld_st;
252b5132
RH
10725 case M_LWL_AB:
10726 s = "lwl";
df58fc94 10727 fmt = MEM12_FMT;
7f3c4072 10728 offbits = (mips_opts.micromips ? 12 : 16);
df58fc94 10729 goto ld_st;
252b5132
RH
10730 case M_LWR_AB:
10731 s = "lwr";
df58fc94 10732 fmt = MEM12_FMT;
7f3c4072 10733 offbits = (mips_opts.micromips ? 12 : 16);
df58fc94 10734 goto ld_st;
252b5132 10735 case M_LDC1_AB:
252b5132 10736 s = "ldc1";
df58fc94 10737 fmt = "T,o(b)";
bdaaa2e1 10738 /* Itbl support may require additional care here. */
252b5132 10739 coproc = 1;
df58fc94 10740 goto ld_st;
252b5132
RH
10741 case M_LDC2_AB:
10742 s = "ldc2";
df58fc94 10743 fmt = COP12_FMT;
7f3c4072 10744 offbits = (mips_opts.micromips ? 12 : 16);
bdaaa2e1 10745 /* Itbl support may require additional care here. */
252b5132 10746 coproc = 1;
df58fc94 10747 goto ld_st;
c77c0862 10748 case M_LQC2_AB:
c77c0862 10749 s = "lqc2";
14daeee3 10750 fmt = "+7,o(b)";
c77c0862
RS
10751 /* Itbl support may require additional care here. */
10752 coproc = 1;
10753 goto ld_st;
252b5132
RH
10754 case M_LDC3_AB:
10755 s = "ldc3";
df58fc94 10756 fmt = "E,o(b)";
bdaaa2e1 10757 /* Itbl support may require additional care here. */
252b5132 10758 coproc = 1;
df58fc94 10759 goto ld_st;
252b5132
RH
10760 case M_LDL_AB:
10761 s = "ldl";
df58fc94 10762 fmt = MEM12_FMT;
7f3c4072 10763 offbits = (mips_opts.micromips ? 12 : 16);
df58fc94 10764 goto ld_st;
252b5132
RH
10765 case M_LDR_AB:
10766 s = "ldr";
df58fc94 10767 fmt = MEM12_FMT;
7f3c4072 10768 offbits = (mips_opts.micromips ? 12 : 16);
df58fc94 10769 goto ld_st;
252b5132
RH
10770 case M_LL_AB:
10771 s = "ll";
df58fc94 10772 fmt = MEM12_FMT;
7f3c4072 10773 offbits = (mips_opts.micromips ? 12 : 16);
252b5132
RH
10774 goto ld;
10775 case M_LLD_AB:
10776 s = "lld";
df58fc94 10777 fmt = MEM12_FMT;
7f3c4072 10778 offbits = (mips_opts.micromips ? 12 : 16);
252b5132
RH
10779 goto ld;
10780 case M_LWU_AB:
10781 s = "lwu";
df58fc94 10782 fmt = MEM12_FMT;
7f3c4072 10783 offbits = (mips_opts.micromips ? 12 : 16);
df58fc94
RS
10784 goto ld;
10785 case M_LWP_AB:
df58fc94
RS
10786 gas_assert (mips_opts.micromips);
10787 s = "lwp";
10788 fmt = "t,~(b)";
7f3c4072 10789 offbits = 12;
df58fc94
RS
10790 lp = 1;
10791 goto ld;
10792 case M_LDP_AB:
df58fc94
RS
10793 gas_assert (mips_opts.micromips);
10794 s = "ldp";
10795 fmt = "t,~(b)";
7f3c4072 10796 offbits = 12;
df58fc94
RS
10797 lp = 1;
10798 goto ld;
10799 case M_LWM_AB:
df58fc94
RS
10800 gas_assert (mips_opts.micromips);
10801 s = "lwm";
10802 fmt = "n,~(b)";
7f3c4072 10803 offbits = 12;
df58fc94
RS
10804 goto ld_st;
10805 case M_LDM_AB:
df58fc94
RS
10806 gas_assert (mips_opts.micromips);
10807 s = "ldm";
10808 fmt = "n,~(b)";
7f3c4072 10809 offbits = 12;
df58fc94
RS
10810 goto ld_st;
10811
252b5132 10812 ld:
f19ccbda 10813 /* We don't want to use $0 as tempreg. */
c0ebe874 10814 if (op[2] == op[0] + lp || op[0] + lp == ZERO)
df58fc94 10815 goto ld_st;
252b5132 10816 else
c0ebe874 10817 tempreg = op[0] + lp;
df58fc94
RS
10818 goto ld_noat;
10819
252b5132
RH
10820 case M_SB_AB:
10821 s = "sb";
df58fc94
RS
10822 fmt = "t,o(b)";
10823 goto ld_st;
252b5132
RH
10824 case M_SH_AB:
10825 s = "sh";
df58fc94
RS
10826 fmt = "t,o(b)";
10827 goto ld_st;
252b5132
RH
10828 case M_SW_AB:
10829 s = "sw";
df58fc94
RS
10830 fmt = "t,o(b)";
10831 goto ld_st;
252b5132 10832 case M_SWC0_AB:
df58fc94 10833 gas_assert (!mips_opts.micromips);
252b5132 10834 s = "swc0";
df58fc94 10835 fmt = "E,o(b)";
bdaaa2e1 10836 /* Itbl support may require additional care here. */
252b5132 10837 coproc = 1;
df58fc94 10838 goto ld_st;
252b5132
RH
10839 case M_SWC1_AB:
10840 s = "swc1";
df58fc94 10841 fmt = "T,o(b)";
bdaaa2e1 10842 /* Itbl support may require additional care here. */
252b5132 10843 coproc = 1;
df58fc94 10844 goto ld_st;
252b5132
RH
10845 case M_SWC2_AB:
10846 s = "swc2";
df58fc94 10847 fmt = COP12_FMT;
7f3c4072 10848 offbits = (mips_opts.micromips ? 12 : 16);
bdaaa2e1 10849 /* Itbl support may require additional care here. */
252b5132 10850 coproc = 1;
df58fc94 10851 goto ld_st;
252b5132 10852 case M_SWC3_AB:
df58fc94 10853 gas_assert (!mips_opts.micromips);
252b5132 10854 s = "swc3";
df58fc94 10855 fmt = "E,o(b)";
bdaaa2e1 10856 /* Itbl support may require additional care here. */
252b5132 10857 coproc = 1;
df58fc94 10858 goto ld_st;
252b5132
RH
10859 case M_SWL_AB:
10860 s = "swl";
df58fc94 10861 fmt = MEM12_FMT;
7f3c4072 10862 offbits = (mips_opts.micromips ? 12 : 16);
df58fc94 10863 goto ld_st;
252b5132
RH
10864 case M_SWR_AB:
10865 s = "swr";
df58fc94 10866 fmt = MEM12_FMT;
7f3c4072 10867 offbits = (mips_opts.micromips ? 12 : 16);
df58fc94 10868 goto ld_st;
252b5132
RH
10869 case M_SC_AB:
10870 s = "sc";
df58fc94 10871 fmt = MEM12_FMT;
7f3c4072 10872 offbits = (mips_opts.micromips ? 12 : 16);
df58fc94 10873 goto ld_st;
252b5132
RH
10874 case M_SCD_AB:
10875 s = "scd";
df58fc94 10876 fmt = MEM12_FMT;
7f3c4072 10877 offbits = (mips_opts.micromips ? 12 : 16);
df58fc94 10878 goto ld_st;
d43b4baf
TS
10879 case M_CACHE_AB:
10880 s = "cache";
df58fc94 10881 fmt = mips_opts.micromips ? "k,~(b)" : "k,o(b)";
7f3c4072
CM
10882 offbits = (mips_opts.micromips ? 12 : 16);
10883 goto ld_st;
10884 case M_CACHEE_AB:
7f3c4072
CM
10885 s = "cachee";
10886 fmt = "k,+j(b)";
10887 offbits = 9;
df58fc94 10888 goto ld_st;
3eebd5eb
MR
10889 case M_PREF_AB:
10890 s = "pref";
df58fc94 10891 fmt = !mips_opts.micromips ? "k,o(b)" : "k,~(b)";
7f3c4072
CM
10892 offbits = (mips_opts.micromips ? 12 : 16);
10893 goto ld_st;
10894 case M_PREFE_AB:
7f3c4072
CM
10895 s = "prefe";
10896 fmt = "k,+j(b)";
10897 offbits = 9;
df58fc94 10898 goto ld_st;
252b5132 10899 case M_SDC1_AB:
252b5132 10900 s = "sdc1";
df58fc94 10901 fmt = "T,o(b)";
252b5132 10902 coproc = 1;
bdaaa2e1 10903 /* Itbl support may require additional care here. */
df58fc94 10904 goto ld_st;
252b5132
RH
10905 case M_SDC2_AB:
10906 s = "sdc2";
df58fc94 10907 fmt = COP12_FMT;
7f3c4072 10908 offbits = (mips_opts.micromips ? 12 : 16);
c77c0862
RS
10909 /* Itbl support may require additional care here. */
10910 coproc = 1;
10911 goto ld_st;
10912 case M_SQC2_AB:
c77c0862 10913 s = "sqc2";
14daeee3 10914 fmt = "+7,o(b)";
bdaaa2e1 10915 /* Itbl support may require additional care here. */
252b5132 10916 coproc = 1;
df58fc94 10917 goto ld_st;
252b5132 10918 case M_SDC3_AB:
df58fc94 10919 gas_assert (!mips_opts.micromips);
252b5132 10920 s = "sdc3";
df58fc94 10921 fmt = "E,o(b)";
bdaaa2e1 10922 /* Itbl support may require additional care here. */
252b5132 10923 coproc = 1;
df58fc94 10924 goto ld_st;
252b5132
RH
10925 case M_SDL_AB:
10926 s = "sdl";
df58fc94 10927 fmt = MEM12_FMT;
7f3c4072 10928 offbits = (mips_opts.micromips ? 12 : 16);
df58fc94 10929 goto ld_st;
252b5132
RH
10930 case M_SDR_AB:
10931 s = "sdr";
df58fc94 10932 fmt = MEM12_FMT;
7f3c4072 10933 offbits = (mips_opts.micromips ? 12 : 16);
df58fc94
RS
10934 goto ld_st;
10935 case M_SWP_AB:
df58fc94
RS
10936 gas_assert (mips_opts.micromips);
10937 s = "swp";
10938 fmt = "t,~(b)";
7f3c4072 10939 offbits = 12;
df58fc94
RS
10940 goto ld_st;
10941 case M_SDP_AB:
df58fc94
RS
10942 gas_assert (mips_opts.micromips);
10943 s = "sdp";
10944 fmt = "t,~(b)";
7f3c4072 10945 offbits = 12;
df58fc94
RS
10946 goto ld_st;
10947 case M_SWM_AB:
df58fc94
RS
10948 gas_assert (mips_opts.micromips);
10949 s = "swm";
10950 fmt = "n,~(b)";
7f3c4072 10951 offbits = 12;
df58fc94
RS
10952 goto ld_st;
10953 case M_SDM_AB:
df58fc94
RS
10954 gas_assert (mips_opts.micromips);
10955 s = "sdm";
10956 fmt = "n,~(b)";
7f3c4072 10957 offbits = 12;
df58fc94
RS
10958
10959 ld_st:
8fc2e39e 10960 tempreg = AT;
df58fc94 10961 ld_noat:
c0ebe874 10962 breg = op[2];
f2ae14a1
RS
10963 if (small_offset_p (0, align, 16))
10964 {
10965 /* The first case exists for M_LD_AB and M_SD_AB, which are
10966 macros for o32 but which should act like normal instructions
10967 otherwise. */
10968 if (offbits == 16)
c0ebe874 10969 macro_build (&offset_expr, s, fmt, op[0], -1, offset_reloc[0],
f2ae14a1
RS
10970 offset_reloc[1], offset_reloc[2], breg);
10971 else if (small_offset_p (0, align, offbits))
10972 {
10973 if (offbits == 0)
c0ebe874 10974 macro_build (NULL, s, fmt, op[0], breg);
f2ae14a1 10975 else
c0ebe874 10976 macro_build (NULL, s, fmt, op[0],
c8276761 10977 (int) offset_expr.X_add_number, breg);
f2ae14a1
RS
10978 }
10979 else
10980 {
10981 if (tempreg == AT)
10982 used_at = 1;
10983 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
10984 tempreg, breg, -1, offset_reloc[0],
10985 offset_reloc[1], offset_reloc[2]);
10986 if (offbits == 0)
c0ebe874 10987 macro_build (NULL, s, fmt, op[0], tempreg);
f2ae14a1 10988 else
c0ebe874 10989 macro_build (NULL, s, fmt, op[0], 0, tempreg);
f2ae14a1
RS
10990 }
10991 break;
10992 }
10993
10994 if (tempreg == AT)
10995 used_at = 1;
10996
252b5132
RH
10997 if (offset_expr.X_op != O_constant
10998 && offset_expr.X_op != O_symbol)
10999 {
1661c76c 11000 as_bad (_("expression too complex"));
252b5132
RH
11001 offset_expr.X_op = O_constant;
11002 }
11003
2051e8c4
MR
11004 if (HAVE_32BIT_ADDRESSES
11005 && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
55e08f71
NC
11006 {
11007 char value [32];
11008
11009 sprintf_vma (value, offset_expr.X_add_number);
1661c76c 11010 as_bad (_("number (0x%s) larger than 32 bits"), value);
55e08f71 11011 }
2051e8c4 11012
252b5132
RH
11013 /* A constant expression in PIC code can be handled just as it
11014 is in non PIC code. */
aed1a261
RS
11015 if (offset_expr.X_op == O_constant)
11016 {
f2ae14a1
RS
11017 expr1.X_add_number = offset_high_part (offset_expr.X_add_number,
11018 offbits == 0 ? 16 : offbits);
11019 offset_expr.X_add_number -= expr1.X_add_number;
df58fc94 11020
f2ae14a1
RS
11021 load_register (tempreg, &expr1, HAVE_64BIT_ADDRESSES);
11022 if (breg != 0)
11023 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11024 tempreg, tempreg, breg);
7f3c4072 11025 if (offbits == 0)
dd6a37e7 11026 {
f2ae14a1 11027 if (offset_expr.X_add_number != 0)
dd6a37e7 11028 macro_build (&offset_expr, ADDRESS_ADDI_INSN,
f2ae14a1 11029 "t,r,j", tempreg, tempreg, BFD_RELOC_LO16);
c0ebe874 11030 macro_build (NULL, s, fmt, op[0], tempreg);
dd6a37e7 11031 }
7f3c4072 11032 else if (offbits == 16)
c0ebe874 11033 macro_build (&offset_expr, s, fmt, op[0], BFD_RELOC_LO16, tempreg);
df58fc94 11034 else
c0ebe874 11035 macro_build (NULL, s, fmt, op[0],
c8276761 11036 (int) offset_expr.X_add_number, tempreg);
df58fc94 11037 }
7f3c4072 11038 else if (offbits != 16)
df58fc94 11039 {
7f3c4072
CM
11040 /* The offset field is too narrow to be used for a low-part
11041 relocation, so load the whole address into the auxillary
f2ae14a1
RS
11042 register. */
11043 load_address (tempreg, &offset_expr, &used_at);
11044 if (breg != 0)
11045 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11046 tempreg, tempreg, breg);
7f3c4072 11047 if (offbits == 0)
c0ebe874 11048 macro_build (NULL, s, fmt, op[0], tempreg);
dd6a37e7 11049 else
c0ebe874 11050 macro_build (NULL, s, fmt, op[0], 0, tempreg);
aed1a261
RS
11051 }
11052 else if (mips_pic == NO_PIC)
252b5132
RH
11053 {
11054 /* If this is a reference to a GP relative symbol, and there
11055 is no base register, we want
c0ebe874 11056 <op> op[0],<sym>($gp) (BFD_RELOC_GPREL16)
252b5132
RH
11057 Otherwise, if there is no base register, we want
11058 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
c0ebe874 11059 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
252b5132
RH
11060 If we have a constant, we need two instructions anyhow,
11061 so we always use the latter form.
11062
11063 If we have a base register, and this is a reference to a
11064 GP relative symbol, we want
11065 addu $tempreg,$breg,$gp
c0ebe874 11066 <op> op[0],<sym>($tempreg) (BFD_RELOC_GPREL16)
252b5132
RH
11067 Otherwise we want
11068 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
11069 addu $tempreg,$tempreg,$breg
c0ebe874 11070 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
d6bc6245 11071 With a constant we always use the latter case.
76b3015f 11072
d6bc6245
TS
11073 With 64bit address space and no base register and $at usable,
11074 we want
11075 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
11076 lui $at,<sym> (BFD_RELOC_HI16_S)
11077 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
11078 dsll32 $tempreg,0
11079 daddu $tempreg,$at
c0ebe874 11080 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
d6bc6245
TS
11081 If we have a base register, we want
11082 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
11083 lui $at,<sym> (BFD_RELOC_HI16_S)
11084 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
11085 daddu $at,$breg
11086 dsll32 $tempreg,0
11087 daddu $tempreg,$at
c0ebe874 11088 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
d6bc6245
TS
11089
11090 Without $at we can't generate the optimal path for superscalar
11091 processors here since this would require two temporary registers.
11092 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
11093 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
11094 dsll $tempreg,16
11095 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
11096 dsll $tempreg,16
c0ebe874 11097 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
d6bc6245
TS
11098 If we have a base register, we want
11099 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
11100 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
11101 dsll $tempreg,16
11102 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
11103 dsll $tempreg,16
11104 daddu $tempreg,$tempreg,$breg
c0ebe874 11105 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
6373ee54 11106
6caf9ef4 11107 For GP relative symbols in 64bit address space we can use
aed1a261
RS
11108 the same sequence as in 32bit address space. */
11109 if (HAVE_64BIT_SYMBOLS)
d6bc6245 11110 {
aed1a261 11111 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
6caf9ef4
TS
11112 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
11113 {
11114 relax_start (offset_expr.X_add_symbol);
11115 if (breg == 0)
11116 {
c0ebe874 11117 macro_build (&offset_expr, s, fmt, op[0],
6caf9ef4
TS
11118 BFD_RELOC_GPREL16, mips_gp_register);
11119 }
11120 else
11121 {
11122 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11123 tempreg, breg, mips_gp_register);
c0ebe874 11124 macro_build (&offset_expr, s, fmt, op[0],
6caf9ef4
TS
11125 BFD_RELOC_GPREL16, tempreg);
11126 }
11127 relax_switch ();
11128 }
d6bc6245 11129
741fe287 11130 if (used_at == 0 && mips_opts.at)
d6bc6245 11131 {
df58fc94 11132 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
67c0d1eb 11133 BFD_RELOC_MIPS_HIGHEST);
df58fc94 11134 macro_build (&offset_expr, "lui", LUI_FMT, AT,
67c0d1eb
RS
11135 BFD_RELOC_HI16_S);
11136 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
11137 tempreg, BFD_RELOC_MIPS_HIGHER);
d6bc6245 11138 if (breg != 0)
67c0d1eb 11139 macro_build (NULL, "daddu", "d,v,t", AT, AT, breg);
df58fc94 11140 macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0);
67c0d1eb 11141 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT);
c0ebe874 11142 macro_build (&offset_expr, s, fmt, op[0], BFD_RELOC_LO16,
67c0d1eb 11143 tempreg);
d6bc6245
TS
11144 used_at = 1;
11145 }
11146 else
11147 {
df58fc94 11148 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
67c0d1eb
RS
11149 BFD_RELOC_MIPS_HIGHEST);
11150 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
11151 tempreg, BFD_RELOC_MIPS_HIGHER);
df58fc94 11152 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
67c0d1eb
RS
11153 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
11154 tempreg, BFD_RELOC_HI16_S);
df58fc94 11155 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
d6bc6245 11156 if (breg != 0)
67c0d1eb 11157 macro_build (NULL, "daddu", "d,v,t",
17a2f251 11158 tempreg, tempreg, breg);
c0ebe874 11159 macro_build (&offset_expr, s, fmt, op[0],
17a2f251 11160 BFD_RELOC_LO16, tempreg);
d6bc6245 11161 }
6caf9ef4
TS
11162
11163 if (mips_relax.sequence)
11164 relax_end ();
8fc2e39e 11165 break;
d6bc6245 11166 }
256ab948 11167
252b5132
RH
11168 if (breg == 0)
11169 {
67c0d1eb 11170 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
6caf9ef4 11171 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
252b5132 11172 {
4d7206a2 11173 relax_start (offset_expr.X_add_symbol);
c0ebe874 11174 macro_build (&offset_expr, s, fmt, op[0], BFD_RELOC_GPREL16,
67c0d1eb 11175 mips_gp_register);
4d7206a2 11176 relax_switch ();
252b5132 11177 }
67c0d1eb 11178 macro_build_lui (&offset_expr, tempreg);
c0ebe874 11179 macro_build (&offset_expr, s, fmt, op[0],
17a2f251 11180 BFD_RELOC_LO16, tempreg);
4d7206a2
RS
11181 if (mips_relax.sequence)
11182 relax_end ();
252b5132
RH
11183 }
11184 else
11185 {
67c0d1eb 11186 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
6caf9ef4 11187 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
252b5132 11188 {
4d7206a2 11189 relax_start (offset_expr.X_add_symbol);
67c0d1eb 11190 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
17a2f251 11191 tempreg, breg, mips_gp_register);
c0ebe874 11192 macro_build (&offset_expr, s, fmt, op[0],
17a2f251 11193 BFD_RELOC_GPREL16, tempreg);
4d7206a2 11194 relax_switch ();
252b5132 11195 }
67c0d1eb
RS
11196 macro_build_lui (&offset_expr, tempreg);
11197 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
17a2f251 11198 tempreg, tempreg, breg);
c0ebe874 11199 macro_build (&offset_expr, s, fmt, op[0],
17a2f251 11200 BFD_RELOC_LO16, tempreg);
4d7206a2
RS
11201 if (mips_relax.sequence)
11202 relax_end ();
252b5132
RH
11203 }
11204 }
0a44bf69 11205 else if (!mips_big_got)
252b5132 11206 {
ed6fb7bd 11207 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
f9419b05 11208
252b5132
RH
11209 /* If this is a reference to an external symbol, we want
11210 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11211 nop
c0ebe874 11212 <op> op[0],0($tempreg)
252b5132
RH
11213 Otherwise we want
11214 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11215 nop
11216 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
c0ebe874 11217 <op> op[0],0($tempreg)
f5040a92
AO
11218
11219 For NewABI, we want
11220 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
c0ebe874 11221 <op> op[0],<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
f5040a92 11222
252b5132
RH
11223 If there is a base register, we add it to $tempreg before
11224 the <op>. If there is a constant, we stick it in the
11225 <op> instruction. We don't handle constants larger than
11226 16 bits, because we have no way to load the upper 16 bits
11227 (actually, we could handle them for the subset of cases
11228 in which we are not using $at). */
9c2799c2 11229 gas_assert (offset_expr.X_op == O_symbol);
f5040a92
AO
11230 if (HAVE_NEWABI)
11231 {
67c0d1eb
RS
11232 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
11233 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
f5040a92 11234 if (breg != 0)
67c0d1eb 11235 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
17a2f251 11236 tempreg, tempreg, breg);
c0ebe874 11237 macro_build (&offset_expr, s, fmt, op[0],
17a2f251 11238 BFD_RELOC_MIPS_GOT_OFST, tempreg);
f5040a92
AO
11239 break;
11240 }
252b5132
RH
11241 expr1.X_add_number = offset_expr.X_add_number;
11242 offset_expr.X_add_number = 0;
11243 if (expr1.X_add_number < -0x8000
11244 || expr1.X_add_number >= 0x8000)
11245 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
67c0d1eb
RS
11246 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
11247 lw_reloc_type, mips_gp_register);
269137b2 11248 load_delay_nop ();
4d7206a2
RS
11249 relax_start (offset_expr.X_add_symbol);
11250 relax_switch ();
67c0d1eb
RS
11251 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
11252 tempreg, BFD_RELOC_LO16);
4d7206a2 11253 relax_end ();
252b5132 11254 if (breg != 0)
67c0d1eb 11255 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
17a2f251 11256 tempreg, tempreg, breg);
c0ebe874 11257 macro_build (&expr1, s, fmt, op[0], BFD_RELOC_LO16, tempreg);
252b5132 11258 }
0a44bf69 11259 else if (mips_big_got && !HAVE_NEWABI)
252b5132 11260 {
67c0d1eb 11261 int gpdelay;
252b5132
RH
11262
11263 /* If this is a reference to an external symbol, we want
11264 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11265 addu $tempreg,$tempreg,$gp
11266 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
c0ebe874 11267 <op> op[0],0($tempreg)
252b5132
RH
11268 Otherwise we want
11269 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11270 nop
11271 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
c0ebe874 11272 <op> op[0],0($tempreg)
252b5132
RH
11273 If there is a base register, we add it to $tempreg before
11274 the <op>. If there is a constant, we stick it in the
11275 <op> instruction. We don't handle constants larger than
11276 16 bits, because we have no way to load the upper 16 bits
11277 (actually, we could handle them for the subset of cases
f5040a92 11278 in which we are not using $at). */
9c2799c2 11279 gas_assert (offset_expr.X_op == O_symbol);
252b5132
RH
11280 expr1.X_add_number = offset_expr.X_add_number;
11281 offset_expr.X_add_number = 0;
11282 if (expr1.X_add_number < -0x8000
11283 || expr1.X_add_number >= 0x8000)
11284 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
67c0d1eb 11285 gpdelay = reg_needs_delay (mips_gp_register);
4d7206a2 11286 relax_start (offset_expr.X_add_symbol);
df58fc94 11287 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
17a2f251 11288 BFD_RELOC_MIPS_GOT_HI16);
67c0d1eb
RS
11289 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
11290 mips_gp_register);
11291 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
11292 BFD_RELOC_MIPS_GOT_LO16, tempreg);
4d7206a2 11293 relax_switch ();
67c0d1eb
RS
11294 if (gpdelay)
11295 macro_build (NULL, "nop", "");
11296 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
11297 BFD_RELOC_MIPS_GOT16, mips_gp_register);
269137b2 11298 load_delay_nop ();
67c0d1eb
RS
11299 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
11300 tempreg, BFD_RELOC_LO16);
4d7206a2
RS
11301 relax_end ();
11302
252b5132 11303 if (breg != 0)
67c0d1eb 11304 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
17a2f251 11305 tempreg, tempreg, breg);
c0ebe874 11306 macro_build (&expr1, s, fmt, op[0], BFD_RELOC_LO16, tempreg);
252b5132 11307 }
0a44bf69 11308 else if (mips_big_got && HAVE_NEWABI)
f5040a92 11309 {
f5040a92
AO
11310 /* If this is a reference to an external symbol, we want
11311 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11312 add $tempreg,$tempreg,$gp
11313 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
c0ebe874 11314 <op> op[0],<ofst>($tempreg)
f5040a92
AO
11315 Otherwise, for local symbols, we want:
11316 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
c0ebe874 11317 <op> op[0],<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
9c2799c2 11318 gas_assert (offset_expr.X_op == O_symbol);
4d7206a2 11319 expr1.X_add_number = offset_expr.X_add_number;
f5040a92
AO
11320 offset_expr.X_add_number = 0;
11321 if (expr1.X_add_number < -0x8000
11322 || expr1.X_add_number >= 0x8000)
11323 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4d7206a2 11324 relax_start (offset_expr.X_add_symbol);
df58fc94 11325 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
17a2f251 11326 BFD_RELOC_MIPS_GOT_HI16);
67c0d1eb
RS
11327 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
11328 mips_gp_register);
11329 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
11330 BFD_RELOC_MIPS_GOT_LO16, tempreg);
f5040a92 11331 if (breg != 0)
67c0d1eb 11332 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
17a2f251 11333 tempreg, tempreg, breg);
c0ebe874 11334 macro_build (&expr1, s, fmt, op[0], BFD_RELOC_LO16, tempreg);
684022ea 11335
4d7206a2 11336 relax_switch ();
f5040a92 11337 offset_expr.X_add_number = expr1.X_add_number;
67c0d1eb
RS
11338 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
11339 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
f5040a92 11340 if (breg != 0)
67c0d1eb 11341 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
17a2f251 11342 tempreg, tempreg, breg);
c0ebe874 11343 macro_build (&offset_expr, s, fmt, op[0],
17a2f251 11344 BFD_RELOC_MIPS_GOT_OFST, tempreg);
4d7206a2 11345 relax_end ();
f5040a92 11346 }
252b5132
RH
11347 else
11348 abort ();
11349
252b5132
RH
11350 break;
11351
833794fc
MR
11352 case M_JRADDIUSP:
11353 gas_assert (mips_opts.micromips);
11354 gas_assert (mips_opts.insn32);
11355 start_noreorder ();
11356 macro_build (NULL, "jr", "s", RA);
c0ebe874 11357 expr1.X_add_number = op[0] << 2;
833794fc
MR
11358 macro_build (&expr1, "addiu", "t,r,j", SP, SP, BFD_RELOC_LO16);
11359 end_noreorder ();
11360 break;
11361
11362 case M_JRC:
11363 gas_assert (mips_opts.micromips);
11364 gas_assert (mips_opts.insn32);
c0ebe874 11365 macro_build (NULL, "jr", "s", op[0]);
833794fc
MR
11366 if (mips_opts.noreorder)
11367 macro_build (NULL, "nop", "");
11368 break;
11369
252b5132
RH
11370 case M_LI:
11371 case M_LI_S:
c0ebe874 11372 load_register (op[0], &imm_expr, 0);
8fc2e39e 11373 break;
252b5132
RH
11374
11375 case M_DLI:
c0ebe874 11376 load_register (op[0], &imm_expr, 1);
8fc2e39e 11377 break;
252b5132
RH
11378
11379 case M_LI_SS:
11380 if (imm_expr.X_op == O_constant)
11381 {
8fc2e39e 11382 used_at = 1;
67c0d1eb 11383 load_register (AT, &imm_expr, 0);
c0ebe874 11384 macro_build (NULL, "mtc1", "t,G", AT, op[0]);
252b5132
RH
11385 break;
11386 }
11387 else
11388 {
b0e6f033
RS
11389 gas_assert (imm_expr.X_op == O_absent
11390 && offset_expr.X_op == O_symbol
90ecf173
MR
11391 && strcmp (segment_name (S_GET_SEGMENT
11392 (offset_expr.X_add_symbol)),
11393 ".lit4") == 0
11394 && offset_expr.X_add_number == 0);
c0ebe874 11395 macro_build (&offset_expr, "lwc1", "T,o(b)", op[0],
17a2f251 11396 BFD_RELOC_MIPS_LITERAL, mips_gp_register);
8fc2e39e 11397 break;
252b5132
RH
11398 }
11399
11400 case M_LI_D:
ca4e0257
RS
11401 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
11402 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
11403 order 32 bits of the value and the low order 32 bits are either
11404 zero or in OFFSET_EXPR. */
b0e6f033 11405 if (imm_expr.X_op == O_constant)
252b5132 11406 {
ca4e0257 11407 if (HAVE_64BIT_GPRS)
c0ebe874 11408 load_register (op[0], &imm_expr, 1);
252b5132
RH
11409 else
11410 {
11411 int hreg, lreg;
11412
11413 if (target_big_endian)
11414 {
c0ebe874
RS
11415 hreg = op[0];
11416 lreg = op[0] + 1;
252b5132
RH
11417 }
11418 else
11419 {
c0ebe874
RS
11420 hreg = op[0] + 1;
11421 lreg = op[0];
252b5132
RH
11422 }
11423
11424 if (hreg <= 31)
67c0d1eb 11425 load_register (hreg, &imm_expr, 0);
252b5132
RH
11426 if (lreg <= 31)
11427 {
11428 if (offset_expr.X_op == O_absent)
67c0d1eb 11429 move_register (lreg, 0);
252b5132
RH
11430 else
11431 {
9c2799c2 11432 gas_assert (offset_expr.X_op == O_constant);
67c0d1eb 11433 load_register (lreg, &offset_expr, 0);
252b5132
RH
11434 }
11435 }
11436 }
8fc2e39e 11437 break;
252b5132 11438 }
b0e6f033 11439 gas_assert (imm_expr.X_op == O_absent);
252b5132
RH
11440
11441 /* We know that sym is in the .rdata section. First we get the
11442 upper 16 bits of the address. */
11443 if (mips_pic == NO_PIC)
11444 {
67c0d1eb 11445 macro_build_lui (&offset_expr, AT);
8fc2e39e 11446 used_at = 1;
252b5132 11447 }
0a44bf69 11448 else
252b5132 11449 {
67c0d1eb
RS
11450 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
11451 BFD_RELOC_MIPS_GOT16, mips_gp_register);
8fc2e39e 11452 used_at = 1;
252b5132 11453 }
bdaaa2e1 11454
252b5132 11455 /* Now we load the register(s). */
ca4e0257 11456 if (HAVE_64BIT_GPRS)
8fc2e39e
TS
11457 {
11458 used_at = 1;
c0ebe874
RS
11459 macro_build (&offset_expr, "ld", "t,o(b)", op[0],
11460 BFD_RELOC_LO16, AT);
8fc2e39e 11461 }
252b5132
RH
11462 else
11463 {
8fc2e39e 11464 used_at = 1;
c0ebe874
RS
11465 macro_build (&offset_expr, "lw", "t,o(b)", op[0],
11466 BFD_RELOC_LO16, AT);
11467 if (op[0] != RA)
252b5132
RH
11468 {
11469 /* FIXME: How in the world do we deal with the possible
11470 overflow here? */
11471 offset_expr.X_add_number += 4;
67c0d1eb 11472 macro_build (&offset_expr, "lw", "t,o(b)",
c0ebe874 11473 op[0] + 1, BFD_RELOC_LO16, AT);
252b5132
RH
11474 }
11475 }
252b5132
RH
11476 break;
11477
11478 case M_LI_DD:
ca4e0257
RS
11479 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
11480 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
11481 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
11482 the value and the low order 32 bits are either zero or in
11483 OFFSET_EXPR. */
b0e6f033 11484 if (imm_expr.X_op == O_constant)
252b5132 11485 {
8fc2e39e 11486 used_at = 1;
67c0d1eb 11487 load_register (AT, &imm_expr, HAVE_64BIT_FPRS);
ca4e0257
RS
11488 if (HAVE_64BIT_FPRS)
11489 {
9c2799c2 11490 gas_assert (HAVE_64BIT_GPRS);
c0ebe874 11491 macro_build (NULL, "dmtc1", "t,S", AT, op[0]);
ca4e0257 11492 }
252b5132
RH
11493 else
11494 {
c0ebe874 11495 macro_build (NULL, "mtc1", "t,G", AT, op[0] + 1);
252b5132 11496 if (offset_expr.X_op == O_absent)
c0ebe874 11497 macro_build (NULL, "mtc1", "t,G", 0, op[0]);
252b5132
RH
11498 else
11499 {
9c2799c2 11500 gas_assert (offset_expr.X_op == O_constant);
67c0d1eb 11501 load_register (AT, &offset_expr, 0);
c0ebe874 11502 macro_build (NULL, "mtc1", "t,G", AT, op[0]);
252b5132
RH
11503 }
11504 }
11505 break;
11506 }
11507
b0e6f033
RS
11508 gas_assert (imm_expr.X_op == O_absent
11509 && offset_expr.X_op == O_symbol
90ecf173 11510 && offset_expr.X_add_number == 0);
252b5132
RH
11511 s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol));
11512 if (strcmp (s, ".lit8") == 0)
f2ae14a1 11513 {
c0ebe874 11514 op[2] = mips_gp_register;
f2ae14a1
RS
11515 offset_reloc[0] = BFD_RELOC_MIPS_LITERAL;
11516 offset_reloc[1] = BFD_RELOC_UNUSED;
11517 offset_reloc[2] = BFD_RELOC_UNUSED;
252b5132
RH
11518 }
11519 else
11520 {
9c2799c2 11521 gas_assert (strcmp (s, RDATA_SECTION_NAME) == 0);
8fc2e39e 11522 used_at = 1;
0a44bf69 11523 if (mips_pic != NO_PIC)
67c0d1eb
RS
11524 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
11525 BFD_RELOC_MIPS_GOT16, mips_gp_register);
252b5132
RH
11526 else
11527 {
11528 /* FIXME: This won't work for a 64 bit address. */
67c0d1eb 11529 macro_build_lui (&offset_expr, AT);
252b5132 11530 }
bdaaa2e1 11531
c0ebe874 11532 op[2] = AT;
f2ae14a1
RS
11533 offset_reloc[0] = BFD_RELOC_LO16;
11534 offset_reloc[1] = BFD_RELOC_UNUSED;
11535 offset_reloc[2] = BFD_RELOC_UNUSED;
11536 }
11537 align = 8;
11538 /* Fall through */
c4a68bea 11539
252b5132
RH
11540 case M_L_DAB:
11541 /*
11542 * The MIPS assembler seems to check for X_add_number not
11543 * being double aligned and generating:
11544 * lui at,%hi(foo+1)
11545 * addu at,at,v1
11546 * addiu at,at,%lo(foo+1)
11547 * lwc1 f2,0(at)
11548 * lwc1 f3,4(at)
11549 * But, the resulting address is the same after relocation so why
11550 * generate the extra instruction?
11551 */
bdaaa2e1 11552 /* Itbl support may require additional care here. */
252b5132 11553 coproc = 1;
df58fc94 11554 fmt = "T,o(b)";
0aa27725 11555 if (CPU_HAS_LDC1_SDC1 (mips_opts.arch))
252b5132
RH
11556 {
11557 s = "ldc1";
df58fc94 11558 goto ld_st;
252b5132 11559 }
252b5132 11560 s = "lwc1";
252b5132
RH
11561 goto ldd_std;
11562
11563 case M_S_DAB:
df58fc94
RS
11564 gas_assert (!mips_opts.micromips);
11565 /* Itbl support may require additional care here. */
11566 coproc = 1;
11567 fmt = "T,o(b)";
0aa27725 11568 if (CPU_HAS_LDC1_SDC1 (mips_opts.arch))
252b5132
RH
11569 {
11570 s = "sdc1";
df58fc94 11571 goto ld_st;
252b5132 11572 }
252b5132 11573 s = "swc1";
252b5132
RH
11574 goto ldd_std;
11575
e407c74b
NC
11576 case M_LQ_AB:
11577 fmt = "t,o(b)";
11578 s = "lq";
11579 goto ld;
11580
11581 case M_SQ_AB:
11582 fmt = "t,o(b)";
11583 s = "sq";
11584 goto ld_st;
11585
252b5132 11586 case M_LD_AB:
df58fc94 11587 fmt = "t,o(b)";
ca4e0257 11588 if (HAVE_64BIT_GPRS)
252b5132
RH
11589 {
11590 s = "ld";
11591 goto ld;
11592 }
252b5132 11593 s = "lw";
252b5132
RH
11594 goto ldd_std;
11595
11596 case M_SD_AB:
df58fc94 11597 fmt = "t,o(b)";
ca4e0257 11598 if (HAVE_64BIT_GPRS)
252b5132
RH
11599 {
11600 s = "sd";
df58fc94 11601 goto ld_st;
252b5132 11602 }
252b5132 11603 s = "sw";
252b5132
RH
11604
11605 ldd_std:
f2ae14a1
RS
11606 /* Even on a big endian machine $fn comes before $fn+1. We have
11607 to adjust when loading from memory. We set coproc if we must
11608 load $fn+1 first. */
11609 /* Itbl support may require additional care here. */
11610 if (!target_big_endian)
11611 coproc = 0;
11612
c0ebe874 11613 breg = op[2];
f2ae14a1
RS
11614 if (small_offset_p (0, align, 16))
11615 {
11616 ep = &offset_expr;
11617 if (!small_offset_p (4, align, 16))
11618 {
11619 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", AT, breg,
11620 -1, offset_reloc[0], offset_reloc[1],
11621 offset_reloc[2]);
11622 expr1.X_add_number = 0;
11623 ep = &expr1;
11624 breg = AT;
11625 used_at = 1;
11626 offset_reloc[0] = BFD_RELOC_LO16;
11627 offset_reloc[1] = BFD_RELOC_UNUSED;
11628 offset_reloc[2] = BFD_RELOC_UNUSED;
11629 }
c0ebe874 11630 if (strcmp (s, "lw") == 0 && op[0] == breg)
f2ae14a1
RS
11631 {
11632 ep->X_add_number += 4;
c0ebe874 11633 macro_build (ep, s, fmt, op[0] + 1, -1, offset_reloc[0],
f2ae14a1
RS
11634 offset_reloc[1], offset_reloc[2], breg);
11635 ep->X_add_number -= 4;
c0ebe874 11636 macro_build (ep, s, fmt, op[0], -1, offset_reloc[0],
f2ae14a1
RS
11637 offset_reloc[1], offset_reloc[2], breg);
11638 }
11639 else
11640 {
c0ebe874 11641 macro_build (ep, s, fmt, coproc ? op[0] + 1 : op[0], -1,
f2ae14a1
RS
11642 offset_reloc[0], offset_reloc[1], offset_reloc[2],
11643 breg);
11644 ep->X_add_number += 4;
c0ebe874 11645 macro_build (ep, s, fmt, coproc ? op[0] : op[0] + 1, -1,
f2ae14a1
RS
11646 offset_reloc[0], offset_reloc[1], offset_reloc[2],
11647 breg);
11648 }
11649 break;
11650 }
11651
252b5132
RH
11652 if (offset_expr.X_op != O_symbol
11653 && offset_expr.X_op != O_constant)
11654 {
1661c76c 11655 as_bad (_("expression too complex"));
252b5132
RH
11656 offset_expr.X_op = O_constant;
11657 }
11658
2051e8c4
MR
11659 if (HAVE_32BIT_ADDRESSES
11660 && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
55e08f71
NC
11661 {
11662 char value [32];
11663
11664 sprintf_vma (value, offset_expr.X_add_number);
1661c76c 11665 as_bad (_("number (0x%s) larger than 32 bits"), value);
55e08f71 11666 }
2051e8c4 11667
90ecf173 11668 if (mips_pic == NO_PIC || offset_expr.X_op == O_constant)
252b5132
RH
11669 {
11670 /* If this is a reference to a GP relative symbol, we want
c0ebe874
RS
11671 <op> op[0],<sym>($gp) (BFD_RELOC_GPREL16)
11672 <op> op[0]+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
252b5132
RH
11673 If we have a base register, we use this
11674 addu $at,$breg,$gp
c0ebe874
RS
11675 <op> op[0],<sym>($at) (BFD_RELOC_GPREL16)
11676 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_GPREL16)
252b5132
RH
11677 If this is not a GP relative symbol, we want
11678 lui $at,<sym> (BFD_RELOC_HI16_S)
c0ebe874
RS
11679 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
11680 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
252b5132
RH
11681 If there is a base register, we add it to $at after the
11682 lui instruction. If there is a constant, we always use
11683 the last case. */
39a59cf8
MR
11684 if (offset_expr.X_op == O_symbol
11685 && (valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
6caf9ef4 11686 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
252b5132 11687 {
4d7206a2 11688 relax_start (offset_expr.X_add_symbol);
252b5132
RH
11689 if (breg == 0)
11690 {
c9914766 11691 tempreg = mips_gp_register;
252b5132
RH
11692 }
11693 else
11694 {
67c0d1eb 11695 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
17a2f251 11696 AT, breg, mips_gp_register);
252b5132 11697 tempreg = AT;
252b5132
RH
11698 used_at = 1;
11699 }
11700
beae10d5 11701 /* Itbl support may require additional care here. */
c0ebe874 11702 macro_build (&offset_expr, s, fmt, coproc ? op[0] + 1 : op[0],
17a2f251 11703 BFD_RELOC_GPREL16, tempreg);
252b5132
RH
11704 offset_expr.X_add_number += 4;
11705
11706 /* Set mips_optimize to 2 to avoid inserting an
11707 undesired nop. */
11708 hold_mips_optimize = mips_optimize;
11709 mips_optimize = 2;
beae10d5 11710 /* Itbl support may require additional care here. */
c0ebe874 11711 macro_build (&offset_expr, s, fmt, coproc ? op[0] : op[0] + 1,
17a2f251 11712 BFD_RELOC_GPREL16, tempreg);
252b5132
RH
11713 mips_optimize = hold_mips_optimize;
11714
4d7206a2 11715 relax_switch ();
252b5132 11716
0970e49e 11717 offset_expr.X_add_number -= 4;
252b5132 11718 }
8fc2e39e 11719 used_at = 1;
f2ae14a1
RS
11720 if (offset_high_part (offset_expr.X_add_number, 16)
11721 != offset_high_part (offset_expr.X_add_number + 4, 16))
11722 {
11723 load_address (AT, &offset_expr, &used_at);
11724 offset_expr.X_op = O_constant;
11725 offset_expr.X_add_number = 0;
11726 }
11727 else
11728 macro_build_lui (&offset_expr, AT);
252b5132 11729 if (breg != 0)
67c0d1eb 11730 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
beae10d5 11731 /* Itbl support may require additional care here. */
c0ebe874 11732 macro_build (&offset_expr, s, fmt, coproc ? op[0] + 1 : op[0],
17a2f251 11733 BFD_RELOC_LO16, AT);
252b5132
RH
11734 /* FIXME: How do we handle overflow here? */
11735 offset_expr.X_add_number += 4;
beae10d5 11736 /* Itbl support may require additional care here. */
c0ebe874 11737 macro_build (&offset_expr, s, fmt, coproc ? op[0] : op[0] + 1,
17a2f251 11738 BFD_RELOC_LO16, AT);
4d7206a2
RS
11739 if (mips_relax.sequence)
11740 relax_end ();
bdaaa2e1 11741 }
0a44bf69 11742 else if (!mips_big_got)
252b5132 11743 {
252b5132
RH
11744 /* If this is a reference to an external symbol, we want
11745 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11746 nop
c0ebe874
RS
11747 <op> op[0],0($at)
11748 <op> op[0]+1,4($at)
252b5132
RH
11749 Otherwise we want
11750 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11751 nop
c0ebe874
RS
11752 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
11753 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
252b5132
RH
11754 If there is a base register we add it to $at before the
11755 lwc1 instructions. If there is a constant we include it
11756 in the lwc1 instructions. */
11757 used_at = 1;
11758 expr1.X_add_number = offset_expr.X_add_number;
252b5132
RH
11759 if (expr1.X_add_number < -0x8000
11760 || expr1.X_add_number >= 0x8000 - 4)
11761 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
67c0d1eb 11762 load_got_offset (AT, &offset_expr);
269137b2 11763 load_delay_nop ();
252b5132 11764 if (breg != 0)
67c0d1eb 11765 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
252b5132
RH
11766
11767 /* Set mips_optimize to 2 to avoid inserting an undesired
11768 nop. */
11769 hold_mips_optimize = mips_optimize;
11770 mips_optimize = 2;
4d7206a2 11771
beae10d5 11772 /* Itbl support may require additional care here. */
4d7206a2 11773 relax_start (offset_expr.X_add_symbol);
c0ebe874 11774 macro_build (&expr1, s, fmt, coproc ? op[0] + 1 : op[0],
67c0d1eb 11775 BFD_RELOC_LO16, AT);
4d7206a2 11776 expr1.X_add_number += 4;
c0ebe874 11777 macro_build (&expr1, s, fmt, coproc ? op[0] : op[0] + 1,
67c0d1eb 11778 BFD_RELOC_LO16, AT);
4d7206a2 11779 relax_switch ();
c0ebe874 11780 macro_build (&offset_expr, s, fmt, coproc ? op[0] + 1 : op[0],
67c0d1eb 11781 BFD_RELOC_LO16, AT);
4d7206a2 11782 offset_expr.X_add_number += 4;
c0ebe874 11783 macro_build (&offset_expr, s, fmt, coproc ? op[0] : op[0] + 1,
67c0d1eb 11784 BFD_RELOC_LO16, AT);
4d7206a2 11785 relax_end ();
252b5132 11786
4d7206a2 11787 mips_optimize = hold_mips_optimize;
252b5132 11788 }
0a44bf69 11789 else if (mips_big_got)
252b5132 11790 {
67c0d1eb 11791 int gpdelay;
252b5132
RH
11792
11793 /* If this is a reference to an external symbol, we want
11794 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11795 addu $at,$at,$gp
11796 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
11797 nop
c0ebe874
RS
11798 <op> op[0],0($at)
11799 <op> op[0]+1,4($at)
252b5132
RH
11800 Otherwise we want
11801 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11802 nop
c0ebe874
RS
11803 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
11804 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
252b5132
RH
11805 If there is a base register we add it to $at before the
11806 lwc1 instructions. If there is a constant we include it
11807 in the lwc1 instructions. */
11808 used_at = 1;
11809 expr1.X_add_number = offset_expr.X_add_number;
11810 offset_expr.X_add_number = 0;
11811 if (expr1.X_add_number < -0x8000
11812 || expr1.X_add_number >= 0x8000 - 4)
11813 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
67c0d1eb 11814 gpdelay = reg_needs_delay (mips_gp_register);
4d7206a2 11815 relax_start (offset_expr.X_add_symbol);
df58fc94 11816 macro_build (&offset_expr, "lui", LUI_FMT,
67c0d1eb
RS
11817 AT, BFD_RELOC_MIPS_GOT_HI16);
11818 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
17a2f251 11819 AT, AT, mips_gp_register);
67c0d1eb 11820 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
17a2f251 11821 AT, BFD_RELOC_MIPS_GOT_LO16, AT);
269137b2 11822 load_delay_nop ();
252b5132 11823 if (breg != 0)
67c0d1eb 11824 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
beae10d5 11825 /* Itbl support may require additional care here. */
c0ebe874 11826 macro_build (&expr1, s, fmt, coproc ? op[0] + 1 : op[0],
17a2f251 11827 BFD_RELOC_LO16, AT);
252b5132
RH
11828 expr1.X_add_number += 4;
11829
11830 /* Set mips_optimize to 2 to avoid inserting an undesired
11831 nop. */
11832 hold_mips_optimize = mips_optimize;
11833 mips_optimize = 2;
beae10d5 11834 /* Itbl support may require additional care here. */
c0ebe874 11835 macro_build (&expr1, s, fmt, coproc ? op[0] : op[0] + 1,
17a2f251 11836 BFD_RELOC_LO16, AT);
252b5132
RH
11837 mips_optimize = hold_mips_optimize;
11838 expr1.X_add_number -= 4;
11839
4d7206a2
RS
11840 relax_switch ();
11841 offset_expr.X_add_number = expr1.X_add_number;
67c0d1eb
RS
11842 if (gpdelay)
11843 macro_build (NULL, "nop", "");
11844 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
11845 BFD_RELOC_MIPS_GOT16, mips_gp_register);
269137b2 11846 load_delay_nop ();
252b5132 11847 if (breg != 0)
67c0d1eb 11848 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
beae10d5 11849 /* Itbl support may require additional care here. */
c0ebe874 11850 macro_build (&offset_expr, s, fmt, coproc ? op[0] + 1 : op[0],
67c0d1eb 11851 BFD_RELOC_LO16, AT);
4d7206a2 11852 offset_expr.X_add_number += 4;
252b5132
RH
11853
11854 /* Set mips_optimize to 2 to avoid inserting an undesired
11855 nop. */
11856 hold_mips_optimize = mips_optimize;
11857 mips_optimize = 2;
beae10d5 11858 /* Itbl support may require additional care here. */
c0ebe874 11859 macro_build (&offset_expr, s, fmt, coproc ? op[0] : op[0] + 1,
67c0d1eb 11860 BFD_RELOC_LO16, AT);
252b5132 11861 mips_optimize = hold_mips_optimize;
4d7206a2 11862 relax_end ();
252b5132 11863 }
252b5132
RH
11864 else
11865 abort ();
11866
252b5132 11867 break;
dd6a37e7
AP
11868
11869 case M_SAA_AB:
dd6a37e7 11870 s = "saa";
7f3c4072 11871 offbits = 0;
dd6a37e7
AP
11872 fmt = "t,(b)";
11873 goto ld_st;
11874 case M_SAAD_AB:
dd6a37e7 11875 s = "saad";
7f3c4072 11876 offbits = 0;
dd6a37e7
AP
11877 fmt = "t,(b)";
11878 goto ld_st;
11879
252b5132
RH
11880 /* New code added to support COPZ instructions.
11881 This code builds table entries out of the macros in mip_opcodes.
11882 R4000 uses interlocks to handle coproc delays.
11883 Other chips (like the R3000) require nops to be inserted for delays.
11884
f72c8c98 11885 FIXME: Currently, we require that the user handle delays.
252b5132
RH
11886 In order to fill delay slots for non-interlocked chips,
11887 we must have a way to specify delays based on the coprocessor.
11888 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
11889 What are the side-effects of the cop instruction?
11890 What cache support might we have and what are its effects?
11891 Both coprocessor & memory require delays. how long???
bdaaa2e1 11892 What registers are read/set/modified?
252b5132
RH
11893
11894 If an itbl is provided to interpret cop instructions,
bdaaa2e1 11895 this knowledge can be encoded in the itbl spec. */
252b5132
RH
11896
11897 case M_COP0:
11898 s = "c0";
11899 goto copz;
11900 case M_COP1:
11901 s = "c1";
11902 goto copz;
11903 case M_COP2:
11904 s = "c2";
11905 goto copz;
11906 case M_COP3:
11907 s = "c3";
11908 copz:
df58fc94 11909 gas_assert (!mips_opts.micromips);
252b5132
RH
11910 /* For now we just do C (same as Cz). The parameter will be
11911 stored in insn_opcode by mips_ip. */
c8276761 11912 macro_build (NULL, s, "C", (int) ip->insn_opcode);
8fc2e39e 11913 break;
252b5132 11914
ea1fb5dc 11915 case M_MOVE:
c0ebe874 11916 move_register (op[0], op[1]);
8fc2e39e 11917 break;
ea1fb5dc 11918
833794fc
MR
11919 case M_MOVEP:
11920 gas_assert (mips_opts.micromips);
11921 gas_assert (mips_opts.insn32);
c0ebe874
RS
11922 move_register (micromips_to_32_reg_h_map1[op[0]],
11923 micromips_to_32_reg_m_map[op[1]]);
11924 move_register (micromips_to_32_reg_h_map2[op[0]],
11925 micromips_to_32_reg_n_map[op[2]]);
833794fc
MR
11926 break;
11927
252b5132
RH
11928 case M_DMUL:
11929 dbl = 1;
11930 case M_MUL:
e407c74b 11931 if (mips_opts.arch == CPU_R5900)
c0ebe874
RS
11932 macro_build (NULL, dbl ? "dmultu" : "multu", "d,s,t", op[0], op[1],
11933 op[2]);
e407c74b
NC
11934 else
11935 {
c0ebe874
RS
11936 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", op[1], op[2]);
11937 macro_build (NULL, "mflo", MFHL_FMT, op[0]);
e407c74b 11938 }
8fc2e39e 11939 break;
252b5132
RH
11940
11941 case M_DMUL_I:
11942 dbl = 1;
11943 case M_MUL_I:
11944 /* The MIPS assembler some times generates shifts and adds. I'm
11945 not trying to be that fancy. GCC should do this for us
11946 anyway. */
8fc2e39e 11947 used_at = 1;
67c0d1eb 11948 load_register (AT, &imm_expr, dbl);
c0ebe874
RS
11949 macro_build (NULL, dbl ? "dmult" : "mult", "s,t", op[1], AT);
11950 macro_build (NULL, "mflo", MFHL_FMT, op[0]);
252b5132
RH
11951 break;
11952
11953 case M_DMULO_I:
11954 dbl = 1;
11955 case M_MULO_I:
11956 imm = 1;
11957 goto do_mulo;
11958
11959 case M_DMULO:
11960 dbl = 1;
11961 case M_MULO:
11962 do_mulo:
7d10b47d 11963 start_noreorder ();
8fc2e39e 11964 used_at = 1;
252b5132 11965 if (imm)
67c0d1eb 11966 load_register (AT, &imm_expr, dbl);
c0ebe874
RS
11967 macro_build (NULL, dbl ? "dmult" : "mult", "s,t",
11968 op[1], imm ? AT : op[2]);
11969 macro_build (NULL, "mflo", MFHL_FMT, op[0]);
11970 macro_build (NULL, dbl ? "dsra32" : "sra", SHFT_FMT, op[0], op[0], 31);
df58fc94 11971 macro_build (NULL, "mfhi", MFHL_FMT, AT);
252b5132 11972 if (mips_trap)
c0ebe874 11973 macro_build (NULL, "tne", TRAP_FMT, op[0], AT, 6);
252b5132
RH
11974 else
11975 {
df58fc94
RS
11976 if (mips_opts.micromips)
11977 micromips_label_expr (&label_expr);
11978 else
11979 label_expr.X_add_number = 8;
c0ebe874 11980 macro_build (&label_expr, "beq", "s,t,p", op[0], AT);
a605d2b3 11981 macro_build (NULL, "nop", "");
df58fc94
RS
11982 macro_build (NULL, "break", BRK_FMT, 6);
11983 if (mips_opts.micromips)
11984 micromips_add_label ();
252b5132 11985 }
7d10b47d 11986 end_noreorder ();
c0ebe874 11987 macro_build (NULL, "mflo", MFHL_FMT, op[0]);
252b5132
RH
11988 break;
11989
11990 case M_DMULOU_I:
11991 dbl = 1;
11992 case M_MULOU_I:
11993 imm = 1;
11994 goto do_mulou;
11995
11996 case M_DMULOU:
11997 dbl = 1;
11998 case M_MULOU:
11999 do_mulou:
7d10b47d 12000 start_noreorder ();
8fc2e39e 12001 used_at = 1;
252b5132 12002 if (imm)
67c0d1eb
RS
12003 load_register (AT, &imm_expr, dbl);
12004 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t",
c0ebe874 12005 op[1], imm ? AT : op[2]);
df58fc94 12006 macro_build (NULL, "mfhi", MFHL_FMT, AT);
c0ebe874 12007 macro_build (NULL, "mflo", MFHL_FMT, op[0]);
252b5132 12008 if (mips_trap)
df58fc94 12009 macro_build (NULL, "tne", TRAP_FMT, AT, ZERO, 6);
252b5132
RH
12010 else
12011 {
df58fc94
RS
12012 if (mips_opts.micromips)
12013 micromips_label_expr (&label_expr);
12014 else
12015 label_expr.X_add_number = 8;
12016 macro_build (&label_expr, "beq", "s,t,p", AT, ZERO);
a605d2b3 12017 macro_build (NULL, "nop", "");
df58fc94
RS
12018 macro_build (NULL, "break", BRK_FMT, 6);
12019 if (mips_opts.micromips)
12020 micromips_add_label ();
252b5132 12021 }
7d10b47d 12022 end_noreorder ();
252b5132
RH
12023 break;
12024
771c7ce4 12025 case M_DROL:
fef14a42 12026 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
82dd0097 12027 {
c0ebe874 12028 if (op[0] == op[1])
82dd0097
CD
12029 {
12030 tempreg = AT;
12031 used_at = 1;
12032 }
12033 else
c0ebe874
RS
12034 tempreg = op[0];
12035 macro_build (NULL, "dnegu", "d,w", tempreg, op[2]);
12036 macro_build (NULL, "drorv", "d,t,s", op[0], op[1], tempreg);
8fc2e39e 12037 break;
82dd0097 12038 }
8fc2e39e 12039 used_at = 1;
c0ebe874
RS
12040 macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, op[2]);
12041 macro_build (NULL, "dsrlv", "d,t,s", AT, op[1], AT);
12042 macro_build (NULL, "dsllv", "d,t,s", op[0], op[1], op[2]);
12043 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
771c7ce4
TS
12044 break;
12045
252b5132 12046 case M_ROL:
fef14a42 12047 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
82dd0097 12048 {
c0ebe874 12049 if (op[0] == op[1])
82dd0097
CD
12050 {
12051 tempreg = AT;
12052 used_at = 1;
12053 }
12054 else
c0ebe874
RS
12055 tempreg = op[0];
12056 macro_build (NULL, "negu", "d,w", tempreg, op[2]);
12057 macro_build (NULL, "rorv", "d,t,s", op[0], op[1], tempreg);
8fc2e39e 12058 break;
82dd0097 12059 }
8fc2e39e 12060 used_at = 1;
c0ebe874
RS
12061 macro_build (NULL, "subu", "d,v,t", AT, ZERO, op[2]);
12062 macro_build (NULL, "srlv", "d,t,s", AT, op[1], AT);
12063 macro_build (NULL, "sllv", "d,t,s", op[0], op[1], op[2]);
12064 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
252b5132
RH
12065 break;
12066
771c7ce4
TS
12067 case M_DROL_I:
12068 {
12069 unsigned int rot;
91d6fa6a
NC
12070 char *l;
12071 char *rr;
771c7ce4 12072
771c7ce4 12073 rot = imm_expr.X_add_number & 0x3f;
fef14a42 12074 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
60b63b72
RS
12075 {
12076 rot = (64 - rot) & 0x3f;
12077 if (rot >= 32)
c0ebe874 12078 macro_build (NULL, "dror32", SHFT_FMT, op[0], op[1], rot - 32);
60b63b72 12079 else
c0ebe874 12080 macro_build (NULL, "dror", SHFT_FMT, op[0], op[1], rot);
8fc2e39e 12081 break;
60b63b72 12082 }
483fc7cd 12083 if (rot == 0)
483fc7cd 12084 {
c0ebe874 12085 macro_build (NULL, "dsrl", SHFT_FMT, op[0], op[1], 0);
8fc2e39e 12086 break;
483fc7cd 12087 }
82dd0097 12088 l = (rot < 0x20) ? "dsll" : "dsll32";
91d6fa6a 12089 rr = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32";
82dd0097 12090 rot &= 0x1f;
8fc2e39e 12091 used_at = 1;
c0ebe874
RS
12092 macro_build (NULL, l, SHFT_FMT, AT, op[1], rot);
12093 macro_build (NULL, rr, SHFT_FMT, op[0], op[1], (0x20 - rot) & 0x1f);
12094 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
771c7ce4
TS
12095 }
12096 break;
12097
252b5132 12098 case M_ROL_I:
771c7ce4
TS
12099 {
12100 unsigned int rot;
12101
771c7ce4 12102 rot = imm_expr.X_add_number & 0x1f;
fef14a42 12103 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
60b63b72 12104 {
c0ebe874
RS
12105 macro_build (NULL, "ror", SHFT_FMT, op[0], op[1],
12106 (32 - rot) & 0x1f);
8fc2e39e 12107 break;
60b63b72 12108 }
483fc7cd 12109 if (rot == 0)
483fc7cd 12110 {
c0ebe874 12111 macro_build (NULL, "srl", SHFT_FMT, op[0], op[1], 0);
8fc2e39e 12112 break;
483fc7cd 12113 }
8fc2e39e 12114 used_at = 1;
c0ebe874
RS
12115 macro_build (NULL, "sll", SHFT_FMT, AT, op[1], rot);
12116 macro_build (NULL, "srl", SHFT_FMT, op[0], op[1], (0x20 - rot) & 0x1f);
12117 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
771c7ce4
TS
12118 }
12119 break;
12120
12121 case M_DROR:
fef14a42 12122 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
82dd0097 12123 {
c0ebe874 12124 macro_build (NULL, "drorv", "d,t,s", op[0], op[1], op[2]);
8fc2e39e 12125 break;
82dd0097 12126 }
8fc2e39e 12127 used_at = 1;
c0ebe874
RS
12128 macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, op[2]);
12129 macro_build (NULL, "dsllv", "d,t,s", AT, op[1], AT);
12130 macro_build (NULL, "dsrlv", "d,t,s", op[0], op[1], op[2]);
12131 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
252b5132
RH
12132 break;
12133
12134 case M_ROR:
fef14a42 12135 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
82dd0097 12136 {
c0ebe874 12137 macro_build (NULL, "rorv", "d,t,s", op[0], op[1], op[2]);
8fc2e39e 12138 break;
82dd0097 12139 }
8fc2e39e 12140 used_at = 1;
c0ebe874
RS
12141 macro_build (NULL, "subu", "d,v,t", AT, ZERO, op[2]);
12142 macro_build (NULL, "sllv", "d,t,s", AT, op[1], AT);
12143 macro_build (NULL, "srlv", "d,t,s", op[0], op[1], op[2]);
12144 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
252b5132
RH
12145 break;
12146
771c7ce4
TS
12147 case M_DROR_I:
12148 {
12149 unsigned int rot;
91d6fa6a
NC
12150 char *l;
12151 char *rr;
771c7ce4 12152
771c7ce4 12153 rot = imm_expr.X_add_number & 0x3f;
fef14a42 12154 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
82dd0097
CD
12155 {
12156 if (rot >= 32)
c0ebe874 12157 macro_build (NULL, "dror32", SHFT_FMT, op[0], op[1], rot - 32);
82dd0097 12158 else
c0ebe874 12159 macro_build (NULL, "dror", SHFT_FMT, op[0], op[1], rot);
8fc2e39e 12160 break;
82dd0097 12161 }
483fc7cd 12162 if (rot == 0)
483fc7cd 12163 {
c0ebe874 12164 macro_build (NULL, "dsrl", SHFT_FMT, op[0], op[1], 0);
8fc2e39e 12165 break;
483fc7cd 12166 }
91d6fa6a 12167 rr = (rot < 0x20) ? "dsrl" : "dsrl32";
82dd0097
CD
12168 l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32";
12169 rot &= 0x1f;
8fc2e39e 12170 used_at = 1;
c0ebe874
RS
12171 macro_build (NULL, rr, SHFT_FMT, AT, op[1], rot);
12172 macro_build (NULL, l, SHFT_FMT, op[0], op[1], (0x20 - rot) & 0x1f);
12173 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
771c7ce4
TS
12174 }
12175 break;
12176
252b5132 12177 case M_ROR_I:
771c7ce4
TS
12178 {
12179 unsigned int rot;
12180
771c7ce4 12181 rot = imm_expr.X_add_number & 0x1f;
fef14a42 12182 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
82dd0097 12183 {
c0ebe874 12184 macro_build (NULL, "ror", SHFT_FMT, op[0], op[1], rot);
8fc2e39e 12185 break;
82dd0097 12186 }
483fc7cd 12187 if (rot == 0)
483fc7cd 12188 {
c0ebe874 12189 macro_build (NULL, "srl", SHFT_FMT, op[0], op[1], 0);
8fc2e39e 12190 break;
483fc7cd 12191 }
8fc2e39e 12192 used_at = 1;
c0ebe874
RS
12193 macro_build (NULL, "srl", SHFT_FMT, AT, op[1], rot);
12194 macro_build (NULL, "sll", SHFT_FMT, op[0], op[1], (0x20 - rot) & 0x1f);
12195 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
771c7ce4 12196 }
252b5132
RH
12197 break;
12198
252b5132 12199 case M_SEQ:
c0ebe874
RS
12200 if (op[1] == 0)
12201 macro_build (&expr1, "sltiu", "t,r,j", op[0], op[2], BFD_RELOC_LO16);
12202 else if (op[2] == 0)
12203 macro_build (&expr1, "sltiu", "t,r,j", op[0], op[1], BFD_RELOC_LO16);
252b5132
RH
12204 else
12205 {
c0ebe874
RS
12206 macro_build (NULL, "xor", "d,v,t", op[0], op[1], op[2]);
12207 macro_build (&expr1, "sltiu", "t,r,j", op[0], op[0], BFD_RELOC_LO16);
252b5132 12208 }
8fc2e39e 12209 break;
252b5132
RH
12210
12211 case M_SEQ_I:
b0e6f033 12212 if (imm_expr.X_add_number == 0)
252b5132 12213 {
c0ebe874 12214 macro_build (&expr1, "sltiu", "t,r,j", op[0], op[1], BFD_RELOC_LO16);
8fc2e39e 12215 break;
252b5132 12216 }
c0ebe874 12217 if (op[1] == 0)
252b5132 12218 {
1661c76c 12219 as_warn (_("instruction %s: result is always false"),
252b5132 12220 ip->insn_mo->name);
c0ebe874 12221 move_register (op[0], 0);
8fc2e39e 12222 break;
252b5132 12223 }
dd3cbb7e
NC
12224 if (CPU_HAS_SEQ (mips_opts.arch)
12225 && -512 <= imm_expr.X_add_number
12226 && imm_expr.X_add_number < 512)
12227 {
c0ebe874 12228 macro_build (NULL, "seqi", "t,r,+Q", op[0], op[1],
750bdd57 12229 (int) imm_expr.X_add_number);
dd3cbb7e
NC
12230 break;
12231 }
b0e6f033 12232 if (imm_expr.X_add_number >= 0
252b5132 12233 && imm_expr.X_add_number < 0x10000)
c0ebe874 12234 macro_build (&imm_expr, "xori", "t,r,i", op[0], op[1], BFD_RELOC_LO16);
b0e6f033 12235 else if (imm_expr.X_add_number > -0x8000
252b5132
RH
12236 && imm_expr.X_add_number < 0)
12237 {
12238 imm_expr.X_add_number = -imm_expr.X_add_number;
67c0d1eb 12239 macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu",
c0ebe874 12240 "t,r,j", op[0], op[1], BFD_RELOC_LO16);
252b5132 12241 }
dd3cbb7e
NC
12242 else if (CPU_HAS_SEQ (mips_opts.arch))
12243 {
12244 used_at = 1;
12245 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
c0ebe874 12246 macro_build (NULL, "seq", "d,v,t", op[0], op[1], AT);
dd3cbb7e
NC
12247 break;
12248 }
252b5132
RH
12249 else
12250 {
67c0d1eb 12251 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
c0ebe874 12252 macro_build (NULL, "xor", "d,v,t", op[0], op[1], AT);
252b5132
RH
12253 used_at = 1;
12254 }
c0ebe874 12255 macro_build (&expr1, "sltiu", "t,r,j", op[0], op[0], BFD_RELOC_LO16);
8fc2e39e 12256 break;
252b5132 12257
c0ebe874 12258 case M_SGE: /* X >= Y <==> not (X < Y) */
252b5132
RH
12259 s = "slt";
12260 goto sge;
12261 case M_SGEU:
12262 s = "sltu";
12263 sge:
c0ebe874
RS
12264 macro_build (NULL, s, "d,v,t", op[0], op[1], op[2]);
12265 macro_build (&expr1, "xori", "t,r,i", op[0], op[0], BFD_RELOC_LO16);
8fc2e39e 12266 break;
252b5132 12267
c0ebe874 12268 case M_SGE_I: /* X >= I <==> not (X < I) */
252b5132 12269 case M_SGEU_I:
b0e6f033 12270 if (imm_expr.X_add_number >= -0x8000
252b5132 12271 && imm_expr.X_add_number < 0x8000)
c0ebe874
RS
12272 macro_build (&imm_expr, mask == M_SGE_I ? "slti" : "sltiu", "t,r,j",
12273 op[0], op[1], BFD_RELOC_LO16);
252b5132
RH
12274 else
12275 {
67c0d1eb
RS
12276 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
12277 macro_build (NULL, mask == M_SGE_I ? "slt" : "sltu", "d,v,t",
c0ebe874 12278 op[0], op[1], AT);
252b5132
RH
12279 used_at = 1;
12280 }
c0ebe874 12281 macro_build (&expr1, "xori", "t,r,i", op[0], op[0], BFD_RELOC_LO16);
8fc2e39e 12282 break;
252b5132 12283
c0ebe874 12284 case M_SGT: /* X > Y <==> Y < X */
252b5132
RH
12285 s = "slt";
12286 goto sgt;
12287 case M_SGTU:
12288 s = "sltu";
12289 sgt:
c0ebe874 12290 macro_build (NULL, s, "d,v,t", op[0], op[2], op[1]);
8fc2e39e 12291 break;
252b5132 12292
c0ebe874 12293 case M_SGT_I: /* X > I <==> I < X */
252b5132
RH
12294 s = "slt";
12295 goto sgti;
12296 case M_SGTU_I:
12297 s = "sltu";
12298 sgti:
8fc2e39e 12299 used_at = 1;
67c0d1eb 12300 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
c0ebe874 12301 macro_build (NULL, s, "d,v,t", op[0], AT, op[1]);
252b5132
RH
12302 break;
12303
c0ebe874 12304 case M_SLE: /* X <= Y <==> Y >= X <==> not (Y < X) */
252b5132
RH
12305 s = "slt";
12306 goto sle;
12307 case M_SLEU:
12308 s = "sltu";
12309 sle:
c0ebe874
RS
12310 macro_build (NULL, s, "d,v,t", op[0], op[2], op[1]);
12311 macro_build (&expr1, "xori", "t,r,i", op[0], op[0], BFD_RELOC_LO16);
8fc2e39e 12312 break;
252b5132 12313
c0ebe874 12314 case M_SLE_I: /* X <= I <==> I >= X <==> not (I < X) */
252b5132
RH
12315 s = "slt";
12316 goto slei;
12317 case M_SLEU_I:
12318 s = "sltu";
12319 slei:
8fc2e39e 12320 used_at = 1;
67c0d1eb 12321 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
c0ebe874
RS
12322 macro_build (NULL, s, "d,v,t", op[0], AT, op[1]);
12323 macro_build (&expr1, "xori", "t,r,i", op[0], op[0], BFD_RELOC_LO16);
252b5132
RH
12324 break;
12325
12326 case M_SLT_I:
b0e6f033 12327 if (imm_expr.X_add_number >= -0x8000
252b5132
RH
12328 && imm_expr.X_add_number < 0x8000)
12329 {
c0ebe874
RS
12330 macro_build (&imm_expr, "slti", "t,r,j", op[0], op[1],
12331 BFD_RELOC_LO16);
8fc2e39e 12332 break;
252b5132 12333 }
8fc2e39e 12334 used_at = 1;
67c0d1eb 12335 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
c0ebe874 12336 macro_build (NULL, "slt", "d,v,t", op[0], op[1], AT);
252b5132
RH
12337 break;
12338
12339 case M_SLTU_I:
b0e6f033 12340 if (imm_expr.X_add_number >= -0x8000
252b5132
RH
12341 && imm_expr.X_add_number < 0x8000)
12342 {
c0ebe874 12343 macro_build (&imm_expr, "sltiu", "t,r,j", op[0], op[1],
17a2f251 12344 BFD_RELOC_LO16);
8fc2e39e 12345 break;
252b5132 12346 }
8fc2e39e 12347 used_at = 1;
67c0d1eb 12348 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
c0ebe874 12349 macro_build (NULL, "sltu", "d,v,t", op[0], op[1], AT);
252b5132
RH
12350 break;
12351
12352 case M_SNE:
c0ebe874
RS
12353 if (op[1] == 0)
12354 macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[2]);
12355 else if (op[2] == 0)
12356 macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[1]);
252b5132
RH
12357 else
12358 {
c0ebe874
RS
12359 macro_build (NULL, "xor", "d,v,t", op[0], op[1], op[2]);
12360 macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[0]);
252b5132 12361 }
8fc2e39e 12362 break;
252b5132
RH
12363
12364 case M_SNE_I:
b0e6f033 12365 if (imm_expr.X_add_number == 0)
252b5132 12366 {
c0ebe874 12367 macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[1]);
8fc2e39e 12368 break;
252b5132 12369 }
c0ebe874 12370 if (op[1] == 0)
252b5132 12371 {
1661c76c 12372 as_warn (_("instruction %s: result is always true"),
252b5132 12373 ip->insn_mo->name);
67c0d1eb 12374 macro_build (&expr1, HAVE_32BIT_GPRS ? "addiu" : "daddiu", "t,r,j",
c0ebe874 12375 op[0], 0, BFD_RELOC_LO16);
8fc2e39e 12376 break;
252b5132 12377 }
dd3cbb7e
NC
12378 if (CPU_HAS_SEQ (mips_opts.arch)
12379 && -512 <= imm_expr.X_add_number
12380 && imm_expr.X_add_number < 512)
12381 {
c0ebe874 12382 macro_build (NULL, "snei", "t,r,+Q", op[0], op[1],
750bdd57 12383 (int) imm_expr.X_add_number);
dd3cbb7e
NC
12384 break;
12385 }
b0e6f033 12386 if (imm_expr.X_add_number >= 0
252b5132
RH
12387 && imm_expr.X_add_number < 0x10000)
12388 {
c0ebe874
RS
12389 macro_build (&imm_expr, "xori", "t,r,i", op[0], op[1],
12390 BFD_RELOC_LO16);
252b5132 12391 }
b0e6f033 12392 else if (imm_expr.X_add_number > -0x8000
252b5132
RH
12393 && imm_expr.X_add_number < 0)
12394 {
12395 imm_expr.X_add_number = -imm_expr.X_add_number;
67c0d1eb 12396 macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu",
c0ebe874 12397 "t,r,j", op[0], op[1], BFD_RELOC_LO16);
252b5132 12398 }
dd3cbb7e
NC
12399 else if (CPU_HAS_SEQ (mips_opts.arch))
12400 {
12401 used_at = 1;
12402 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
c0ebe874 12403 macro_build (NULL, "sne", "d,v,t", op[0], op[1], AT);
dd3cbb7e
NC
12404 break;
12405 }
252b5132
RH
12406 else
12407 {
67c0d1eb 12408 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
c0ebe874 12409 macro_build (NULL, "xor", "d,v,t", op[0], op[1], AT);
252b5132
RH
12410 used_at = 1;
12411 }
c0ebe874 12412 macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[0]);
8fc2e39e 12413 break;
252b5132 12414
df58fc94
RS
12415 case M_SUB_I:
12416 s = "addi";
12417 s2 = "sub";
12418 goto do_subi;
12419 case M_SUBU_I:
12420 s = "addiu";
12421 s2 = "subu";
12422 goto do_subi;
252b5132
RH
12423 case M_DSUB_I:
12424 dbl = 1;
df58fc94
RS
12425 s = "daddi";
12426 s2 = "dsub";
12427 if (!mips_opts.micromips)
12428 goto do_subi;
b0e6f033 12429 if (imm_expr.X_add_number > -0x200
df58fc94 12430 && imm_expr.X_add_number <= 0x200)
252b5132 12431 {
b0e6f033
RS
12432 macro_build (NULL, s, "t,r,.", op[0], op[1],
12433 (int) -imm_expr.X_add_number);
8fc2e39e 12434 break;
252b5132 12435 }
df58fc94 12436 goto do_subi_i;
252b5132
RH
12437 case M_DSUBU_I:
12438 dbl = 1;
df58fc94
RS
12439 s = "daddiu";
12440 s2 = "dsubu";
12441 do_subi:
b0e6f033 12442 if (imm_expr.X_add_number > -0x8000
252b5132
RH
12443 && imm_expr.X_add_number <= 0x8000)
12444 {
12445 imm_expr.X_add_number = -imm_expr.X_add_number;
c0ebe874 12446 macro_build (&imm_expr, s, "t,r,j", op[0], op[1], BFD_RELOC_LO16);
8fc2e39e 12447 break;
252b5132 12448 }
df58fc94 12449 do_subi_i:
8fc2e39e 12450 used_at = 1;
67c0d1eb 12451 load_register (AT, &imm_expr, dbl);
c0ebe874 12452 macro_build (NULL, s2, "d,v,t", op[0], op[1], AT);
252b5132
RH
12453 break;
12454
12455 case M_TEQ_I:
12456 s = "teq";
12457 goto trap;
12458 case M_TGE_I:
12459 s = "tge";
12460 goto trap;
12461 case M_TGEU_I:
12462 s = "tgeu";
12463 goto trap;
12464 case M_TLT_I:
12465 s = "tlt";
12466 goto trap;
12467 case M_TLTU_I:
12468 s = "tltu";
12469 goto trap;
12470 case M_TNE_I:
12471 s = "tne";
12472 trap:
8fc2e39e 12473 used_at = 1;
67c0d1eb 12474 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
c0ebe874 12475 macro_build (NULL, s, "s,t", op[0], AT);
252b5132
RH
12476 break;
12477
252b5132 12478 case M_TRUNCWS:
43841e91 12479 case M_TRUNCWD:
df58fc94 12480 gas_assert (!mips_opts.micromips);
0aa27725 12481 gas_assert (mips_opts.isa == ISA_MIPS1);
8fc2e39e 12482 used_at = 1;
252b5132
RH
12483
12484 /*
12485 * Is the double cfc1 instruction a bug in the mips assembler;
12486 * or is there a reason for it?
12487 */
7d10b47d 12488 start_noreorder ();
c0ebe874
RS
12489 macro_build (NULL, "cfc1", "t,G", op[2], RA);
12490 macro_build (NULL, "cfc1", "t,G", op[2], RA);
67c0d1eb 12491 macro_build (NULL, "nop", "");
252b5132 12492 expr1.X_add_number = 3;
c0ebe874 12493 macro_build (&expr1, "ori", "t,r,i", AT, op[2], BFD_RELOC_LO16);
252b5132 12494 expr1.X_add_number = 2;
67c0d1eb
RS
12495 macro_build (&expr1, "xori", "t,r,i", AT, AT, BFD_RELOC_LO16);
12496 macro_build (NULL, "ctc1", "t,G", AT, RA);
12497 macro_build (NULL, "nop", "");
12498 macro_build (NULL, mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S",
c0ebe874
RS
12499 op[0], op[1]);
12500 macro_build (NULL, "ctc1", "t,G", op[2], RA);
67c0d1eb 12501 macro_build (NULL, "nop", "");
7d10b47d 12502 end_noreorder ();
252b5132
RH
12503 break;
12504
f2ae14a1 12505 case M_ULH_AB:
252b5132 12506 s = "lb";
df58fc94
RS
12507 s2 = "lbu";
12508 off = 1;
12509 goto uld_st;
f2ae14a1 12510 case M_ULHU_AB:
252b5132 12511 s = "lbu";
df58fc94
RS
12512 s2 = "lbu";
12513 off = 1;
12514 goto uld_st;
f2ae14a1 12515 case M_ULW_AB:
df58fc94
RS
12516 s = "lwl";
12517 s2 = "lwr";
7f3c4072 12518 offbits = (mips_opts.micromips ? 12 : 16);
df58fc94
RS
12519 off = 3;
12520 goto uld_st;
f2ae14a1 12521 case M_ULD_AB:
252b5132
RH
12522 s = "ldl";
12523 s2 = "ldr";
7f3c4072 12524 offbits = (mips_opts.micromips ? 12 : 16);
252b5132 12525 off = 7;
df58fc94 12526 goto uld_st;
f2ae14a1 12527 case M_USH_AB:
df58fc94
RS
12528 s = "sb";
12529 s2 = "sb";
12530 off = 1;
12531 ust = 1;
12532 goto uld_st;
f2ae14a1 12533 case M_USW_AB:
df58fc94
RS
12534 s = "swl";
12535 s2 = "swr";
7f3c4072 12536 offbits = (mips_opts.micromips ? 12 : 16);
252b5132 12537 off = 3;
df58fc94
RS
12538 ust = 1;
12539 goto uld_st;
f2ae14a1 12540 case M_USD_AB:
df58fc94
RS
12541 s = "sdl";
12542 s2 = "sdr";
7f3c4072 12543 offbits = (mips_opts.micromips ? 12 : 16);
df58fc94
RS
12544 off = 7;
12545 ust = 1;
12546
12547 uld_st:
c0ebe874 12548 breg = op[2];
f2ae14a1 12549 large_offset = !small_offset_p (off, align, offbits);
df58fc94
RS
12550 ep = &offset_expr;
12551 expr1.X_add_number = 0;
f2ae14a1 12552 if (large_offset)
df58fc94
RS
12553 {
12554 used_at = 1;
12555 tempreg = AT;
f2ae14a1
RS
12556 if (small_offset_p (0, align, 16))
12557 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", tempreg, breg, -1,
12558 offset_reloc[0], offset_reloc[1], offset_reloc[2]);
12559 else
12560 {
12561 load_address (tempreg, ep, &used_at);
12562 if (breg != 0)
12563 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
12564 tempreg, tempreg, breg);
12565 }
12566 offset_reloc[0] = BFD_RELOC_LO16;
12567 offset_reloc[1] = BFD_RELOC_UNUSED;
12568 offset_reloc[2] = BFD_RELOC_UNUSED;
df58fc94 12569 breg = tempreg;
c0ebe874 12570 tempreg = op[0];
df58fc94
RS
12571 ep = &expr1;
12572 }
c0ebe874 12573 else if (!ust && op[0] == breg)
8fc2e39e
TS
12574 {
12575 used_at = 1;
12576 tempreg = AT;
12577 }
252b5132 12578 else
c0ebe874 12579 tempreg = op[0];
af22f5b2 12580
df58fc94
RS
12581 if (off == 1)
12582 goto ulh_sh;
252b5132 12583
90ecf173 12584 if (!target_big_endian)
df58fc94 12585 ep->X_add_number += off;
f2ae14a1 12586 if (offbits == 12)
c8276761 12587 macro_build (NULL, s, "t,~(b)", tempreg, (int) ep->X_add_number, breg);
f2ae14a1
RS
12588 else
12589 macro_build (ep, s, "t,o(b)", tempreg, -1,
12590 offset_reloc[0], offset_reloc[1], offset_reloc[2], breg);
df58fc94 12591
90ecf173 12592 if (!target_big_endian)
df58fc94 12593 ep->X_add_number -= off;
252b5132 12594 else
df58fc94 12595 ep->X_add_number += off;
f2ae14a1 12596 if (offbits == 12)
df58fc94 12597 macro_build (NULL, s2, "t,~(b)",
c8276761 12598 tempreg, (int) ep->X_add_number, breg);
f2ae14a1
RS
12599 else
12600 macro_build (ep, s2, "t,o(b)", tempreg, -1,
12601 offset_reloc[0], offset_reloc[1], offset_reloc[2], breg);
252b5132 12602
df58fc94 12603 /* If necessary, move the result in tempreg to the final destination. */
c0ebe874 12604 if (!ust && op[0] != tempreg)
df58fc94
RS
12605 {
12606 /* Protect second load's delay slot. */
12607 load_delay_nop ();
c0ebe874 12608 move_register (op[0], tempreg);
df58fc94 12609 }
8fc2e39e 12610 break;
252b5132 12611
df58fc94 12612 ulh_sh:
d6bc6245 12613 used_at = 1;
df58fc94
RS
12614 if (target_big_endian == ust)
12615 ep->X_add_number += off;
c0ebe874 12616 tempreg = ust || large_offset ? op[0] : AT;
f2ae14a1
RS
12617 macro_build (ep, s, "t,o(b)", tempreg, -1,
12618 offset_reloc[0], offset_reloc[1], offset_reloc[2], breg);
df58fc94
RS
12619
12620 /* For halfword transfers we need a temporary register to shuffle
12621 bytes. Unfortunately for M_USH_A we have none available before
12622 the next store as AT holds the base address. We deal with this
12623 case by clobbering TREG and then restoring it as with ULH. */
c0ebe874 12624 tempreg = ust == large_offset ? op[0] : AT;
df58fc94 12625 if (ust)
c0ebe874 12626 macro_build (NULL, "srl", SHFT_FMT, tempreg, op[0], 8);
df58fc94
RS
12627
12628 if (target_big_endian == ust)
12629 ep->X_add_number -= off;
252b5132 12630 else
df58fc94 12631 ep->X_add_number += off;
f2ae14a1
RS
12632 macro_build (ep, s2, "t,o(b)", tempreg, -1,
12633 offset_reloc[0], offset_reloc[1], offset_reloc[2], breg);
252b5132 12634
df58fc94 12635 /* For M_USH_A re-retrieve the LSB. */
f2ae14a1 12636 if (ust && large_offset)
df58fc94
RS
12637 {
12638 if (target_big_endian)
12639 ep->X_add_number += off;
12640 else
12641 ep->X_add_number -= off;
f2ae14a1
RS
12642 macro_build (&expr1, "lbu", "t,o(b)", AT, -1,
12643 offset_reloc[0], offset_reloc[1], offset_reloc[2], AT);
df58fc94
RS
12644 }
12645 /* For ULH and M_USH_A OR the LSB in. */
f2ae14a1 12646 if (!ust || large_offset)
df58fc94 12647 {
c0ebe874 12648 tempreg = !large_offset ? AT : op[0];
df58fc94 12649 macro_build (NULL, "sll", SHFT_FMT, tempreg, tempreg, 8);
c0ebe874 12650 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
df58fc94 12651 }
252b5132
RH
12652 break;
12653
12654 default:
12655 /* FIXME: Check if this is one of the itbl macros, since they
bdaaa2e1 12656 are added dynamically. */
1661c76c 12657 as_bad (_("macro %s not implemented yet"), ip->insn_mo->name);
252b5132
RH
12658 break;
12659 }
741fe287 12660 if (!mips_opts.at && used_at)
1661c76c 12661 as_bad (_("macro used $at after \".set noat\""));
252b5132
RH
12662}
12663
12664/* Implement macros in mips16 mode. */
12665
12666static void
17a2f251 12667mips16_macro (struct mips_cl_insn *ip)
252b5132 12668{
c0ebe874 12669 const struct mips_operand_array *operands;
252b5132 12670 int mask;
c0ebe874 12671 int tmp;
252b5132
RH
12672 expressionS expr1;
12673 int dbl;
12674 const char *s, *s2, *s3;
c0ebe874
RS
12675 unsigned int op[MAX_OPERANDS];
12676 unsigned int i;
252b5132
RH
12677
12678 mask = ip->insn_mo->mask;
12679
c0ebe874
RS
12680 operands = insn_operands (ip);
12681 for (i = 0; i < MAX_OPERANDS; i++)
12682 if (operands->operand[i])
12683 op[i] = insn_extract_operand (ip, operands->operand[i]);
12684 else
12685 op[i] = -1;
252b5132 12686
252b5132
RH
12687 expr1.X_op = O_constant;
12688 expr1.X_op_symbol = NULL;
12689 expr1.X_add_symbol = NULL;
12690 expr1.X_add_number = 1;
12691
12692 dbl = 0;
12693
12694 switch (mask)
12695 {
12696 default:
b37df7c4 12697 abort ();
252b5132
RH
12698
12699 case M_DDIV_3:
12700 dbl = 1;
12701 case M_DIV_3:
12702 s = "mflo";
12703 goto do_div3;
12704 case M_DREM_3:
12705 dbl = 1;
12706 case M_REM_3:
12707 s = "mfhi";
12708 do_div3:
7d10b47d 12709 start_noreorder ();
c0ebe874 12710 macro_build (NULL, dbl ? "ddiv" : "div", "0,x,y", op[1], op[2]);
252b5132 12711 expr1.X_add_number = 2;
c0ebe874 12712 macro_build (&expr1, "bnez", "x,p", op[2]);
67c0d1eb 12713 macro_build (NULL, "break", "6", 7);
bdaaa2e1 12714
252b5132
RH
12715 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
12716 since that causes an overflow. We should do that as well,
12717 but I don't see how to do the comparisons without a temporary
12718 register. */
7d10b47d 12719 end_noreorder ();
c0ebe874 12720 macro_build (NULL, s, "x", op[0]);
252b5132
RH
12721 break;
12722
12723 case M_DIVU_3:
12724 s = "divu";
12725 s2 = "mflo";
12726 goto do_divu3;
12727 case M_REMU_3:
12728 s = "divu";
12729 s2 = "mfhi";
12730 goto do_divu3;
12731 case M_DDIVU_3:
12732 s = "ddivu";
12733 s2 = "mflo";
12734 goto do_divu3;
12735 case M_DREMU_3:
12736 s = "ddivu";
12737 s2 = "mfhi";
12738 do_divu3:
7d10b47d 12739 start_noreorder ();
c0ebe874 12740 macro_build (NULL, s, "0,x,y", op[1], op[2]);
252b5132 12741 expr1.X_add_number = 2;
c0ebe874 12742 macro_build (&expr1, "bnez", "x,p", op[2]);
67c0d1eb 12743 macro_build (NULL, "break", "6", 7);
7d10b47d 12744 end_noreorder ();
c0ebe874 12745 macro_build (NULL, s2, "x", op[0]);
252b5132
RH
12746 break;
12747
12748 case M_DMUL:
12749 dbl = 1;
12750 case M_MUL:
c0ebe874
RS
12751 macro_build (NULL, dbl ? "dmultu" : "multu", "x,y", op[1], op[2]);
12752 macro_build (NULL, "mflo", "x", op[0]);
8fc2e39e 12753 break;
252b5132
RH
12754
12755 case M_DSUBU_I:
12756 dbl = 1;
12757 goto do_subu;
12758 case M_SUBU_I:
12759 do_subu:
252b5132 12760 imm_expr.X_add_number = -imm_expr.X_add_number;
c0ebe874 12761 macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "y,x,4", op[0], op[1]);
252b5132
RH
12762 break;
12763
12764 case M_SUBU_I_2:
252b5132 12765 imm_expr.X_add_number = -imm_expr.X_add_number;
c0ebe874 12766 macro_build (&imm_expr, "addiu", "x,k", op[0]);
252b5132
RH
12767 break;
12768
12769 case M_DSUBU_I_2:
252b5132 12770 imm_expr.X_add_number = -imm_expr.X_add_number;
c0ebe874 12771 macro_build (&imm_expr, "daddiu", "y,j", op[0]);
252b5132
RH
12772 break;
12773
12774 case M_BEQ:
12775 s = "cmp";
12776 s2 = "bteqz";
12777 goto do_branch;
12778 case M_BNE:
12779 s = "cmp";
12780 s2 = "btnez";
12781 goto do_branch;
12782 case M_BLT:
12783 s = "slt";
12784 s2 = "btnez";
12785 goto do_branch;
12786 case M_BLTU:
12787 s = "sltu";
12788 s2 = "btnez";
12789 goto do_branch;
12790 case M_BLE:
12791 s = "slt";
12792 s2 = "bteqz";
12793 goto do_reverse_branch;
12794 case M_BLEU:
12795 s = "sltu";
12796 s2 = "bteqz";
12797 goto do_reverse_branch;
12798 case M_BGE:
12799 s = "slt";
12800 s2 = "bteqz";
12801 goto do_branch;
12802 case M_BGEU:
12803 s = "sltu";
12804 s2 = "bteqz";
12805 goto do_branch;
12806 case M_BGT:
12807 s = "slt";
12808 s2 = "btnez";
12809 goto do_reverse_branch;
12810 case M_BGTU:
12811 s = "sltu";
12812 s2 = "btnez";
12813
12814 do_reverse_branch:
c0ebe874
RS
12815 tmp = op[1];
12816 op[1] = op[0];
12817 op[0] = tmp;
252b5132
RH
12818
12819 do_branch:
c0ebe874 12820 macro_build (NULL, s, "x,y", op[0], op[1]);
67c0d1eb 12821 macro_build (&offset_expr, s2, "p");
252b5132
RH
12822 break;
12823
12824 case M_BEQ_I:
12825 s = "cmpi";
12826 s2 = "bteqz";
12827 s3 = "x,U";
12828 goto do_branch_i;
12829 case M_BNE_I:
12830 s = "cmpi";
12831 s2 = "btnez";
12832 s3 = "x,U";
12833 goto do_branch_i;
12834 case M_BLT_I:
12835 s = "slti";
12836 s2 = "btnez";
12837 s3 = "x,8";
12838 goto do_branch_i;
12839 case M_BLTU_I:
12840 s = "sltiu";
12841 s2 = "btnez";
12842 s3 = "x,8";
12843 goto do_branch_i;
12844 case M_BLE_I:
12845 s = "slti";
12846 s2 = "btnez";
12847 s3 = "x,8";
12848 goto do_addone_branch_i;
12849 case M_BLEU_I:
12850 s = "sltiu";
12851 s2 = "btnez";
12852 s3 = "x,8";
12853 goto do_addone_branch_i;
12854 case M_BGE_I:
12855 s = "slti";
12856 s2 = "bteqz";
12857 s3 = "x,8";
12858 goto do_branch_i;
12859 case M_BGEU_I:
12860 s = "sltiu";
12861 s2 = "bteqz";
12862 s3 = "x,8";
12863 goto do_branch_i;
12864 case M_BGT_I:
12865 s = "slti";
12866 s2 = "bteqz";
12867 s3 = "x,8";
12868 goto do_addone_branch_i;
12869 case M_BGTU_I:
12870 s = "sltiu";
12871 s2 = "bteqz";
12872 s3 = "x,8";
12873
12874 do_addone_branch_i:
252b5132
RH
12875 ++imm_expr.X_add_number;
12876
12877 do_branch_i:
c0ebe874 12878 macro_build (&imm_expr, s, s3, op[0]);
67c0d1eb 12879 macro_build (&offset_expr, s2, "p");
252b5132
RH
12880 break;
12881
12882 case M_ABS:
12883 expr1.X_add_number = 0;
c0ebe874
RS
12884 macro_build (&expr1, "slti", "x,8", op[1]);
12885 if (op[0] != op[1])
12886 macro_build (NULL, "move", "y,X", op[0], mips16_to_32_reg_map[op[1]]);
252b5132 12887 expr1.X_add_number = 2;
67c0d1eb 12888 macro_build (&expr1, "bteqz", "p");
c0ebe874 12889 macro_build (NULL, "neg", "x,w", op[0], op[0]);
0acfaea6 12890 break;
252b5132
RH
12891 }
12892}
12893
14daeee3
RS
12894/* Look up instruction [START, START + LENGTH) in HASH. Record any extra
12895 opcode bits in *OPCODE_EXTRA. */
12896
12897static struct mips_opcode *
12898mips_lookup_insn (struct hash_control *hash, const char *start,
da8bca91 12899 ssize_t length, unsigned int *opcode_extra)
14daeee3
RS
12900{
12901 char *name, *dot, *p;
12902 unsigned int mask, suffix;
da8bca91 12903 ssize_t opend;
14daeee3
RS
12904 struct mips_opcode *insn;
12905
12906 /* Make a copy of the instruction so that we can fiddle with it. */
12907 name = alloca (length + 1);
12908 memcpy (name, start, length);
12909 name[length] = '\0';
12910
12911 /* Look up the instruction as-is. */
12912 insn = (struct mips_opcode *) hash_find (hash, name);
ee5734f0 12913 if (insn)
14daeee3
RS
12914 return insn;
12915
12916 dot = strchr (name, '.');
12917 if (dot && dot[1])
12918 {
12919 /* Try to interpret the text after the dot as a VU0 channel suffix. */
12920 p = mips_parse_vu0_channels (dot + 1, &mask);
12921 if (*p == 0 && mask != 0)
12922 {
12923 *dot = 0;
12924 insn = (struct mips_opcode *) hash_find (hash, name);
12925 *dot = '.';
12926 if (insn && (insn->pinfo2 & INSN2_VU0_CHANNEL_SUFFIX) != 0)
12927 {
12928 *opcode_extra |= mask << mips_vu0_channel_mask.lsb;
12929 return insn;
12930 }
12931 }
12932 }
12933
12934 if (mips_opts.micromips)
12935 {
12936 /* See if there's an instruction size override suffix,
12937 either `16' or `32', at the end of the mnemonic proper,
12938 that defines the operation, i.e. before the first `.'
12939 character if any. Strip it and retry. */
12940 opend = dot != NULL ? dot - name : length;
12941 if (opend >= 3 && name[opend - 2] == '1' && name[opend - 1] == '6')
12942 suffix = 2;
12943 else if (name[opend - 2] == '3' && name[opend - 1] == '2')
12944 suffix = 4;
12945 else
12946 suffix = 0;
12947 if (suffix)
12948 {
12949 memcpy (name + opend - 2, name + opend, length - opend + 1);
12950 insn = (struct mips_opcode *) hash_find (hash, name);
ee5734f0 12951 if (insn)
14daeee3
RS
12952 {
12953 forced_insn_length = suffix;
12954 return insn;
12955 }
12956 }
12957 }
12958
12959 return NULL;
12960}
12961
77bd4346 12962/* Assemble an instruction into its binary format. If the instruction
e423441d
RS
12963 is a macro, set imm_expr and offset_expr to the values associated
12964 with "I" and "A" operands respectively. Otherwise store the value
12965 of the relocatable field (if any) in offset_expr. In both cases
12966 set offset_reloc to the relocation operators applied to offset_expr. */
252b5132
RH
12967
12968static void
60f20e8b 12969mips_ip (char *str, struct mips_cl_insn *insn)
252b5132 12970{
60f20e8b 12971 const struct mips_opcode *first, *past;
df58fc94 12972 struct hash_control *hash;
a92713e6 12973 char format;
14daeee3 12974 size_t end;
a92713e6 12975 struct mips_operand_token *tokens;
14daeee3 12976 unsigned int opcode_extra;
252b5132 12977
df58fc94
RS
12978 if (mips_opts.micromips)
12979 {
12980 hash = micromips_op_hash;
12981 past = &micromips_opcodes[bfd_micromips_num_opcodes];
12982 }
12983 else
12984 {
12985 hash = op_hash;
12986 past = &mips_opcodes[NUMOPCODES];
12987 }
12988 forced_insn_length = 0;
14daeee3 12989 opcode_extra = 0;
252b5132 12990
df58fc94 12991 /* We first try to match an instruction up to a space or to the end. */
a40bc9dd
RS
12992 for (end = 0; str[end] != '\0' && !ISSPACE (str[end]); end++)
12993 continue;
bdaaa2e1 12994
60f20e8b
RS
12995 first = mips_lookup_insn (hash, str, end, &opcode_extra);
12996 if (first == NULL)
252b5132 12997 {
1661c76c 12998 set_insn_error (0, _("unrecognized opcode"));
a40bc9dd 12999 return;
252b5132
RH
13000 }
13001
60f20e8b 13002 if (strcmp (first->name, "li.s") == 0)
a92713e6 13003 format = 'f';
60f20e8b 13004 else if (strcmp (first->name, "li.d") == 0)
a92713e6
RS
13005 format = 'd';
13006 else
13007 format = 0;
13008 tokens = mips_parse_arguments (str + end, format);
13009 if (!tokens)
13010 return;
13011
60f20e8b
RS
13012 if (!match_insns (insn, first, past, tokens, opcode_extra, FALSE)
13013 && !match_insns (insn, first, past, tokens, opcode_extra, TRUE))
1661c76c 13014 set_insn_error (0, _("invalid operands"));
df58fc94 13015
e3de51ce 13016 obstack_free (&mips_operand_tokens, tokens);
252b5132
RH
13017}
13018
77bd4346
RS
13019/* As for mips_ip, but used when assembling MIPS16 code.
13020 Also set forced_insn_length to the resulting instruction size in
13021 bytes if the user explicitly requested a small or extended instruction. */
252b5132
RH
13022
13023static void
60f20e8b 13024mips16_ip (char *str, struct mips_cl_insn *insn)
252b5132 13025{
1a00e612 13026 char *end, *s, c;
60f20e8b 13027 struct mips_opcode *first;
a92713e6 13028 struct mips_operand_token *tokens;
252b5132 13029
df58fc94 13030 forced_insn_length = 0;
252b5132 13031
3882b010 13032 for (s = str; ISLOWER (*s); ++s)
252b5132 13033 ;
1a00e612
RS
13034 end = s;
13035 c = *end;
13036 switch (c)
252b5132
RH
13037 {
13038 case '\0':
13039 break;
13040
13041 case ' ':
1a00e612 13042 s++;
252b5132
RH
13043 break;
13044
13045 case '.':
13046 if (s[1] == 't' && s[2] == ' ')
13047 {
df58fc94 13048 forced_insn_length = 2;
252b5132
RH
13049 s += 3;
13050 break;
13051 }
13052 else if (s[1] == 'e' && s[2] == ' ')
13053 {
df58fc94 13054 forced_insn_length = 4;
252b5132
RH
13055 s += 3;
13056 break;
13057 }
13058 /* Fall through. */
13059 default:
1661c76c 13060 set_insn_error (0, _("unrecognized opcode"));
252b5132
RH
13061 return;
13062 }
13063
df58fc94
RS
13064 if (mips_opts.noautoextend && !forced_insn_length)
13065 forced_insn_length = 2;
252b5132 13066
1a00e612 13067 *end = 0;
60f20e8b 13068 first = (struct mips_opcode *) hash_find (mips16_op_hash, str);
1a00e612
RS
13069 *end = c;
13070
60f20e8b 13071 if (!first)
252b5132 13072 {
1661c76c 13073 set_insn_error (0, _("unrecognized opcode"));
252b5132
RH
13074 return;
13075 }
13076
a92713e6
RS
13077 tokens = mips_parse_arguments (s, 0);
13078 if (!tokens)
13079 return;
13080
60f20e8b 13081 if (!match_mips16_insns (insn, first, tokens))
1661c76c 13082 set_insn_error (0, _("invalid operands"));
252b5132 13083
e3de51ce 13084 obstack_free (&mips_operand_tokens, tokens);
252b5132
RH
13085}
13086
b886a2ab
RS
13087/* Marshal immediate value VAL for an extended MIPS16 instruction.
13088 NBITS is the number of significant bits in VAL. */
13089
13090static unsigned long
13091mips16_immed_extend (offsetT val, unsigned int nbits)
13092{
13093 int extval;
13094 if (nbits == 16)
13095 {
13096 extval = ((val >> 11) & 0x1f) | (val & 0x7e0);
13097 val &= 0x1f;
13098 }
13099 else if (nbits == 15)
13100 {
13101 extval = ((val >> 11) & 0xf) | (val & 0x7f0);
13102 val &= 0xf;
13103 }
13104 else
13105 {
13106 extval = ((val & 0x1f) << 6) | (val & 0x20);
13107 val = 0;
13108 }
13109 return (extval << 16) | val;
13110}
13111
3ccad066
RS
13112/* Like decode_mips16_operand, but require the operand to be defined and
13113 require it to be an integer. */
13114
13115static const struct mips_int_operand *
13116mips16_immed_operand (int type, bfd_boolean extended_p)
13117{
13118 const struct mips_operand *operand;
13119
13120 operand = decode_mips16_operand (type, extended_p);
13121 if (!operand || (operand->type != OP_INT && operand->type != OP_PCREL))
13122 abort ();
13123 return (const struct mips_int_operand *) operand;
13124}
13125
13126/* Return true if SVAL fits OPERAND. RELOC is as for mips16_immed. */
13127
13128static bfd_boolean
13129mips16_immed_in_range_p (const struct mips_int_operand *operand,
13130 bfd_reloc_code_real_type reloc, offsetT sval)
13131{
13132 int min_val, max_val;
13133
13134 min_val = mips_int_operand_min (operand);
13135 max_val = mips_int_operand_max (operand);
13136 if (reloc != BFD_RELOC_UNUSED)
13137 {
13138 if (min_val < 0)
13139 sval = SEXT_16BIT (sval);
13140 else
13141 sval &= 0xffff;
13142 }
13143
13144 return (sval >= min_val
13145 && sval <= max_val
13146 && (sval & ((1 << operand->shift) - 1)) == 0);
13147}
13148
5c04167a
RS
13149/* Install immediate value VAL into MIPS16 instruction *INSN,
13150 extending it if necessary. The instruction in *INSN may
13151 already be extended.
13152
43c0598f
RS
13153 RELOC is the relocation that produced VAL, or BFD_RELOC_UNUSED
13154 if none. In the former case, VAL is a 16-bit number with no
13155 defined signedness.
13156
13157 TYPE is the type of the immediate field. USER_INSN_LENGTH
13158 is the length that the user requested, or 0 if none. */
252b5132
RH
13159
13160static void
43c0598f
RS
13161mips16_immed (char *file, unsigned int line, int type,
13162 bfd_reloc_code_real_type reloc, offsetT val,
5c04167a 13163 unsigned int user_insn_length, unsigned long *insn)
252b5132 13164{
3ccad066
RS
13165 const struct mips_int_operand *operand;
13166 unsigned int uval, length;
252b5132 13167
3ccad066
RS
13168 operand = mips16_immed_operand (type, FALSE);
13169 if (!mips16_immed_in_range_p (operand, reloc, val))
5c04167a
RS
13170 {
13171 /* We need an extended instruction. */
13172 if (user_insn_length == 2)
13173 as_bad_where (file, line, _("invalid unextended operand value"));
13174 else
13175 *insn |= MIPS16_EXTEND;
13176 }
13177 else if (user_insn_length == 4)
13178 {
13179 /* The operand doesn't force an unextended instruction to be extended.
13180 Warn if the user wanted an extended instruction anyway. */
13181 *insn |= MIPS16_EXTEND;
13182 as_warn_where (file, line,
13183 _("extended operand requested but not required"));
13184 }
252b5132 13185
3ccad066
RS
13186 length = mips16_opcode_length (*insn);
13187 if (length == 4)
252b5132 13188 {
3ccad066
RS
13189 operand = mips16_immed_operand (type, TRUE);
13190 if (!mips16_immed_in_range_p (operand, reloc, val))
13191 as_bad_where (file, line,
13192 _("operand value out of range for instruction"));
252b5132 13193 }
3ccad066
RS
13194 uval = ((unsigned int) val >> operand->shift) - operand->bias;
13195 if (length == 2)
13196 *insn = mips_insert_operand (&operand->root, *insn, uval);
252b5132 13197 else
3ccad066 13198 *insn |= mips16_immed_extend (uval, operand->root.size);
252b5132
RH
13199}
13200\f
d6f16593 13201struct percent_op_match
ad8d3bb3 13202{
5e0116d5
RS
13203 const char *str;
13204 bfd_reloc_code_real_type reloc;
d6f16593
MR
13205};
13206
13207static const struct percent_op_match mips_percent_op[] =
ad8d3bb3 13208{
5e0116d5 13209 {"%lo", BFD_RELOC_LO16},
5e0116d5
RS
13210 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16},
13211 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16},
13212 {"%call16", BFD_RELOC_MIPS_CALL16},
13213 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP},
13214 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE},
13215 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST},
13216 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16},
13217 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16},
13218 {"%got", BFD_RELOC_MIPS_GOT16},
13219 {"%gp_rel", BFD_RELOC_GPREL16},
13220 {"%half", BFD_RELOC_16},
13221 {"%highest", BFD_RELOC_MIPS_HIGHEST},
13222 {"%higher", BFD_RELOC_MIPS_HIGHER},
13223 {"%neg", BFD_RELOC_MIPS_SUB},
3f98094e
DJ
13224 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD},
13225 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM},
13226 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16},
13227 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16},
13228 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16},
13229 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16},
13230 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL},
5e0116d5 13231 {"%hi", BFD_RELOC_HI16_S}
ad8d3bb3
TS
13232};
13233
d6f16593
MR
13234static const struct percent_op_match mips16_percent_op[] =
13235{
13236 {"%lo", BFD_RELOC_MIPS16_LO16},
13237 {"%gprel", BFD_RELOC_MIPS16_GPREL},
738e5348
RS
13238 {"%got", BFD_RELOC_MIPS16_GOT16},
13239 {"%call16", BFD_RELOC_MIPS16_CALL16},
d0f13682
CLT
13240 {"%hi", BFD_RELOC_MIPS16_HI16_S},
13241 {"%tlsgd", BFD_RELOC_MIPS16_TLS_GD},
13242 {"%tlsldm", BFD_RELOC_MIPS16_TLS_LDM},
13243 {"%dtprel_hi", BFD_RELOC_MIPS16_TLS_DTPREL_HI16},
13244 {"%dtprel_lo", BFD_RELOC_MIPS16_TLS_DTPREL_LO16},
13245 {"%tprel_hi", BFD_RELOC_MIPS16_TLS_TPREL_HI16},
13246 {"%tprel_lo", BFD_RELOC_MIPS16_TLS_TPREL_LO16},
13247 {"%gottprel", BFD_RELOC_MIPS16_TLS_GOTTPREL}
d6f16593
MR
13248};
13249
252b5132 13250
5e0116d5
RS
13251/* Return true if *STR points to a relocation operator. When returning true,
13252 move *STR over the operator and store its relocation code in *RELOC.
13253 Leave both *STR and *RELOC alone when returning false. */
13254
13255static bfd_boolean
17a2f251 13256parse_relocation (char **str, bfd_reloc_code_real_type *reloc)
252b5132 13257{
d6f16593
MR
13258 const struct percent_op_match *percent_op;
13259 size_t limit, i;
13260
13261 if (mips_opts.mips16)
13262 {
13263 percent_op = mips16_percent_op;
13264 limit = ARRAY_SIZE (mips16_percent_op);
13265 }
13266 else
13267 {
13268 percent_op = mips_percent_op;
13269 limit = ARRAY_SIZE (mips_percent_op);
13270 }
76b3015f 13271
d6f16593 13272 for (i = 0; i < limit; i++)
5e0116d5 13273 if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0)
394f9b3a 13274 {
3f98094e
DJ
13275 int len = strlen (percent_op[i].str);
13276
13277 if (!ISSPACE ((*str)[len]) && (*str)[len] != '(')
13278 continue;
13279
5e0116d5
RS
13280 *str += strlen (percent_op[i].str);
13281 *reloc = percent_op[i].reloc;
394f9b3a 13282
5e0116d5
RS
13283 /* Check whether the output BFD supports this relocation.
13284 If not, issue an error and fall back on something safe. */
13285 if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc))
394f9b3a 13286 {
20203fb9 13287 as_bad (_("relocation %s isn't supported by the current ABI"),
5e0116d5 13288 percent_op[i].str);
01a3f561 13289 *reloc = BFD_RELOC_UNUSED;
394f9b3a 13290 }
5e0116d5 13291 return TRUE;
394f9b3a 13292 }
5e0116d5 13293 return FALSE;
394f9b3a 13294}
ad8d3bb3 13295
ad8d3bb3 13296
5e0116d5
RS
13297/* Parse string STR as a 16-bit relocatable operand. Store the
13298 expression in *EP and the relocations in the array starting
13299 at RELOC. Return the number of relocation operators used.
ad8d3bb3 13300
01a3f561 13301 On exit, EXPR_END points to the first character after the expression. */
ad8d3bb3 13302
5e0116d5 13303static size_t
17a2f251
TS
13304my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc,
13305 char *str)
ad8d3bb3 13306{
5e0116d5
RS
13307 bfd_reloc_code_real_type reversed_reloc[3];
13308 size_t reloc_index, i;
09b8f35a
RS
13309 int crux_depth, str_depth;
13310 char *crux;
5e0116d5
RS
13311
13312 /* Search for the start of the main expression, recoding relocations
09b8f35a
RS
13313 in REVERSED_RELOC. End the loop with CRUX pointing to the start
13314 of the main expression and with CRUX_DEPTH containing the number
13315 of open brackets at that point. */
13316 reloc_index = -1;
13317 str_depth = 0;
13318 do
fb1b3232 13319 {
09b8f35a
RS
13320 reloc_index++;
13321 crux = str;
13322 crux_depth = str_depth;
13323
13324 /* Skip over whitespace and brackets, keeping count of the number
13325 of brackets. */
13326 while (*str == ' ' || *str == '\t' || *str == '(')
13327 if (*str++ == '(')
13328 str_depth++;
5e0116d5 13329 }
09b8f35a
RS
13330 while (*str == '%'
13331 && reloc_index < (HAVE_NEWABI ? 3 : 1)
13332 && parse_relocation (&str, &reversed_reloc[reloc_index]));
ad8d3bb3 13333
09b8f35a 13334 my_getExpression (ep, crux);
5e0116d5 13335 str = expr_end;
394f9b3a 13336
5e0116d5 13337 /* Match every open bracket. */
09b8f35a 13338 while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t'))
5e0116d5 13339 if (*str++ == ')')
09b8f35a 13340 crux_depth--;
394f9b3a 13341
09b8f35a 13342 if (crux_depth > 0)
20203fb9 13343 as_bad (_("unclosed '('"));
394f9b3a 13344
5e0116d5 13345 expr_end = str;
252b5132 13346
01a3f561 13347 if (reloc_index != 0)
64bdfcaf
RS
13348 {
13349 prev_reloc_op_frag = frag_now;
13350 for (i = 0; i < reloc_index; i++)
13351 reloc[i] = reversed_reloc[reloc_index - 1 - i];
13352 }
fb1b3232 13353
5e0116d5 13354 return reloc_index;
252b5132
RH
13355}
13356
13357static void
17a2f251 13358my_getExpression (expressionS *ep, char *str)
252b5132
RH
13359{
13360 char *save_in;
13361
13362 save_in = input_line_pointer;
13363 input_line_pointer = str;
13364 expression (ep);
13365 expr_end = input_line_pointer;
13366 input_line_pointer = save_in;
252b5132
RH
13367}
13368
252b5132 13369char *
17a2f251 13370md_atof (int type, char *litP, int *sizeP)
252b5132 13371{
499ac353 13372 return ieee_md_atof (type, litP, sizeP, target_big_endian);
252b5132
RH
13373}
13374
13375void
17a2f251 13376md_number_to_chars (char *buf, valueT val, int n)
252b5132
RH
13377{
13378 if (target_big_endian)
13379 number_to_chars_bigendian (buf, val, n);
13380 else
13381 number_to_chars_littleendian (buf, val, n);
13382}
13383\f
e013f690
TS
13384static int support_64bit_objects(void)
13385{
13386 const char **list, **l;
aa3d8fdf 13387 int yes;
e013f690
TS
13388
13389 list = bfd_target_list ();
13390 for (l = list; *l != NULL; l++)
aeffff67
RS
13391 if (strcmp (*l, ELF_TARGET ("elf64-", "big")) == 0
13392 || strcmp (*l, ELF_TARGET ("elf64-", "little")) == 0)
e013f690 13393 break;
aa3d8fdf 13394 yes = (*l != NULL);
e013f690 13395 free (list);
aa3d8fdf 13396 return yes;
e013f690
TS
13397}
13398
316f5878
RS
13399/* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
13400 NEW_VALUE. Warn if another value was already specified. Note:
13401 we have to defer parsing the -march and -mtune arguments in order
13402 to handle 'from-abi' correctly, since the ABI might be specified
13403 in a later argument. */
13404
13405static void
17a2f251 13406mips_set_option_string (const char **string_ptr, const char *new_value)
316f5878
RS
13407{
13408 if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0)
1661c76c 13409 as_warn (_("a different %s was already specified, is now %s"),
316f5878
RS
13410 string_ptr == &mips_arch_string ? "-march" : "-mtune",
13411 new_value);
13412
13413 *string_ptr = new_value;
13414}
13415
252b5132 13416int
17a2f251 13417md_parse_option (int c, char *arg)
252b5132 13418{
c6278170
RS
13419 unsigned int i;
13420
13421 for (i = 0; i < ARRAY_SIZE (mips_ases); i++)
13422 if (c == mips_ases[i].option_on || c == mips_ases[i].option_off)
13423 {
13424 file_ase_explicit |= mips_set_ase (&mips_ases[i],
13425 c == mips_ases[i].option_on);
13426 return 1;
13427 }
13428
252b5132
RH
13429 switch (c)
13430 {
119d663a
NC
13431 case OPTION_CONSTRUCT_FLOATS:
13432 mips_disable_float_construction = 0;
13433 break;
bdaaa2e1 13434
119d663a
NC
13435 case OPTION_NO_CONSTRUCT_FLOATS:
13436 mips_disable_float_construction = 1;
13437 break;
bdaaa2e1 13438
252b5132
RH
13439 case OPTION_TRAP:
13440 mips_trap = 1;
13441 break;
13442
13443 case OPTION_BREAK:
13444 mips_trap = 0;
13445 break;
13446
13447 case OPTION_EB:
13448 target_big_endian = 1;
13449 break;
13450
13451 case OPTION_EL:
13452 target_big_endian = 0;
13453 break;
13454
13455 case 'O':
4ffff32f
TS
13456 if (arg == NULL)
13457 mips_optimize = 1;
13458 else if (arg[0] == '0')
13459 mips_optimize = 0;
13460 else if (arg[0] == '1')
252b5132
RH
13461 mips_optimize = 1;
13462 else
13463 mips_optimize = 2;
13464 break;
13465
13466 case 'g':
13467 if (arg == NULL)
13468 mips_debug = 2;
13469 else
13470 mips_debug = atoi (arg);
252b5132
RH
13471 break;
13472
13473 case OPTION_MIPS1:
316f5878 13474 file_mips_isa = ISA_MIPS1;
252b5132
RH
13475 break;
13476
13477 case OPTION_MIPS2:
316f5878 13478 file_mips_isa = ISA_MIPS2;
252b5132
RH
13479 break;
13480
13481 case OPTION_MIPS3:
316f5878 13482 file_mips_isa = ISA_MIPS3;
252b5132
RH
13483 break;
13484
13485 case OPTION_MIPS4:
316f5878 13486 file_mips_isa = ISA_MIPS4;
e7af610e
NC
13487 break;
13488
84ea6cf2 13489 case OPTION_MIPS5:
316f5878 13490 file_mips_isa = ISA_MIPS5;
84ea6cf2
NC
13491 break;
13492
e7af610e 13493 case OPTION_MIPS32:
316f5878 13494 file_mips_isa = ISA_MIPS32;
252b5132
RH
13495 break;
13496
af7ee8bf
CD
13497 case OPTION_MIPS32R2:
13498 file_mips_isa = ISA_MIPS32R2;
13499 break;
13500
5f74bc13
CD
13501 case OPTION_MIPS64R2:
13502 file_mips_isa = ISA_MIPS64R2;
13503 break;
13504
84ea6cf2 13505 case OPTION_MIPS64:
316f5878 13506 file_mips_isa = ISA_MIPS64;
84ea6cf2
NC
13507 break;
13508
ec68c924 13509 case OPTION_MTUNE:
316f5878
RS
13510 mips_set_option_string (&mips_tune_string, arg);
13511 break;
ec68c924 13512
316f5878
RS
13513 case OPTION_MARCH:
13514 mips_set_option_string (&mips_arch_string, arg);
252b5132
RH
13515 break;
13516
13517 case OPTION_M4650:
316f5878
RS
13518 mips_set_option_string (&mips_arch_string, "4650");
13519 mips_set_option_string (&mips_tune_string, "4650");
252b5132
RH
13520 break;
13521
13522 case OPTION_NO_M4650:
13523 break;
13524
13525 case OPTION_M4010:
316f5878
RS
13526 mips_set_option_string (&mips_arch_string, "4010");
13527 mips_set_option_string (&mips_tune_string, "4010");
252b5132
RH
13528 break;
13529
13530 case OPTION_NO_M4010:
13531 break;
13532
13533 case OPTION_M4100:
316f5878
RS
13534 mips_set_option_string (&mips_arch_string, "4100");
13535 mips_set_option_string (&mips_tune_string, "4100");
252b5132
RH
13536 break;
13537
13538 case OPTION_NO_M4100:
13539 break;
13540
252b5132 13541 case OPTION_M3900:
316f5878
RS
13542 mips_set_option_string (&mips_arch_string, "3900");
13543 mips_set_option_string (&mips_tune_string, "3900");
252b5132 13544 break;
bdaaa2e1 13545
252b5132
RH
13546 case OPTION_NO_M3900:
13547 break;
13548
df58fc94
RS
13549 case OPTION_MICROMIPS:
13550 if (mips_opts.mips16 == 1)
13551 {
13552 as_bad (_("-mmicromips cannot be used with -mips16"));
13553 return 0;
13554 }
13555 mips_opts.micromips = 1;
13556 mips_no_prev_insn ();
13557 break;
13558
13559 case OPTION_NO_MICROMIPS:
13560 mips_opts.micromips = 0;
13561 mips_no_prev_insn ();
13562 break;
13563
252b5132 13564 case OPTION_MIPS16:
df58fc94
RS
13565 if (mips_opts.micromips == 1)
13566 {
13567 as_bad (_("-mips16 cannot be used with -micromips"));
13568 return 0;
13569 }
252b5132 13570 mips_opts.mips16 = 1;
7d10b47d 13571 mips_no_prev_insn ();
252b5132
RH
13572 break;
13573
13574 case OPTION_NO_MIPS16:
13575 mips_opts.mips16 = 0;
7d10b47d 13576 mips_no_prev_insn ();
252b5132
RH
13577 break;
13578
6a32d874
CM
13579 case OPTION_FIX_24K:
13580 mips_fix_24k = 1;
13581 break;
13582
13583 case OPTION_NO_FIX_24K:
13584 mips_fix_24k = 0;
13585 break;
13586
c67a084a
NC
13587 case OPTION_FIX_LOONGSON2F_JUMP:
13588 mips_fix_loongson2f_jump = TRUE;
13589 break;
13590
13591 case OPTION_NO_FIX_LOONGSON2F_JUMP:
13592 mips_fix_loongson2f_jump = FALSE;
13593 break;
13594
13595 case OPTION_FIX_LOONGSON2F_NOP:
13596 mips_fix_loongson2f_nop = TRUE;
13597 break;
13598
13599 case OPTION_NO_FIX_LOONGSON2F_NOP:
13600 mips_fix_loongson2f_nop = FALSE;
13601 break;
13602
d766e8ec
RS
13603 case OPTION_FIX_VR4120:
13604 mips_fix_vr4120 = 1;
60b63b72
RS
13605 break;
13606
d766e8ec
RS
13607 case OPTION_NO_FIX_VR4120:
13608 mips_fix_vr4120 = 0;
60b63b72
RS
13609 break;
13610
7d8e00cf
RS
13611 case OPTION_FIX_VR4130:
13612 mips_fix_vr4130 = 1;
13613 break;
13614
13615 case OPTION_NO_FIX_VR4130:
13616 mips_fix_vr4130 = 0;
13617 break;
13618
d954098f
DD
13619 case OPTION_FIX_CN63XXP1:
13620 mips_fix_cn63xxp1 = TRUE;
13621 break;
13622
13623 case OPTION_NO_FIX_CN63XXP1:
13624 mips_fix_cn63xxp1 = FALSE;
13625 break;
13626
4a6a3df4
AO
13627 case OPTION_RELAX_BRANCH:
13628 mips_relax_branch = 1;
13629 break;
13630
13631 case OPTION_NO_RELAX_BRANCH:
13632 mips_relax_branch = 0;
13633 break;
13634
833794fc
MR
13635 case OPTION_INSN32:
13636 mips_opts.insn32 = TRUE;
13637 break;
13638
13639 case OPTION_NO_INSN32:
13640 mips_opts.insn32 = FALSE;
13641 break;
13642
aa6975fb
ILT
13643 case OPTION_MSHARED:
13644 mips_in_shared = TRUE;
13645 break;
13646
13647 case OPTION_MNO_SHARED:
13648 mips_in_shared = FALSE;
13649 break;
13650
aed1a261
RS
13651 case OPTION_MSYM32:
13652 mips_opts.sym32 = TRUE;
13653 break;
13654
13655 case OPTION_MNO_SYM32:
13656 mips_opts.sym32 = FALSE;
13657 break;
13658
252b5132
RH
13659 /* When generating ELF code, we permit -KPIC and -call_shared to
13660 select SVR4_PIC, and -non_shared to select no PIC. This is
13661 intended to be compatible with Irix 5. */
13662 case OPTION_CALL_SHARED:
252b5132 13663 mips_pic = SVR4_PIC;
143d77c5 13664 mips_abicalls = TRUE;
252b5132
RH
13665 break;
13666
861fb55a 13667 case OPTION_CALL_NONPIC:
861fb55a
DJ
13668 mips_pic = NO_PIC;
13669 mips_abicalls = TRUE;
13670 break;
13671
252b5132 13672 case OPTION_NON_SHARED:
252b5132 13673 mips_pic = NO_PIC;
143d77c5 13674 mips_abicalls = FALSE;
252b5132
RH
13675 break;
13676
44075ae2
TS
13677 /* The -xgot option tells the assembler to use 32 bit offsets
13678 when accessing the got in SVR4_PIC mode. It is for Irix
252b5132
RH
13679 compatibility. */
13680 case OPTION_XGOT:
13681 mips_big_got = 1;
13682 break;
13683
13684 case 'G':
6caf9ef4
TS
13685 g_switch_value = atoi (arg);
13686 g_switch_seen = 1;
252b5132
RH
13687 break;
13688
34ba82a8
TS
13689 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
13690 and -mabi=64. */
252b5132 13691 case OPTION_32:
f3ded42a 13692 mips_abi = O32_ABI;
252b5132
RH
13693 break;
13694
e013f690 13695 case OPTION_N32:
316f5878 13696 mips_abi = N32_ABI;
e013f690 13697 break;
252b5132 13698
e013f690 13699 case OPTION_64:
316f5878 13700 mips_abi = N64_ABI;
f43abd2b 13701 if (!support_64bit_objects())
1661c76c 13702 as_fatal (_("no compiled in support for 64 bit object file format"));
252b5132
RH
13703 break;
13704
c97ef257 13705 case OPTION_GP32:
a325df1d 13706 file_mips_gp32 = 1;
c97ef257
AH
13707 break;
13708
13709 case OPTION_GP64:
a325df1d 13710 file_mips_gp32 = 0;
c97ef257 13711 break;
252b5132 13712
ca4e0257 13713 case OPTION_FP32:
a325df1d 13714 file_mips_fp32 = 1;
316f5878
RS
13715 break;
13716
13717 case OPTION_FP64:
13718 file_mips_fp32 = 0;
ca4e0257
RS
13719 break;
13720
037b32b9
AN
13721 case OPTION_SINGLE_FLOAT:
13722 file_mips_single_float = 1;
13723 break;
13724
13725 case OPTION_DOUBLE_FLOAT:
13726 file_mips_single_float = 0;
13727 break;
13728
13729 case OPTION_SOFT_FLOAT:
13730 file_mips_soft_float = 1;
13731 break;
13732
13733 case OPTION_HARD_FLOAT:
13734 file_mips_soft_float = 0;
13735 break;
13736
252b5132 13737 case OPTION_MABI:
e013f690 13738 if (strcmp (arg, "32") == 0)
316f5878 13739 mips_abi = O32_ABI;
e013f690 13740 else if (strcmp (arg, "o64") == 0)
316f5878 13741 mips_abi = O64_ABI;
e013f690 13742 else if (strcmp (arg, "n32") == 0)
316f5878 13743 mips_abi = N32_ABI;
e013f690
TS
13744 else if (strcmp (arg, "64") == 0)
13745 {
316f5878 13746 mips_abi = N64_ABI;
e013f690 13747 if (! support_64bit_objects())
1661c76c 13748 as_fatal (_("no compiled in support for 64 bit object file "
e013f690
TS
13749 "format"));
13750 }
13751 else if (strcmp (arg, "eabi") == 0)
316f5878 13752 mips_abi = EABI_ABI;
e013f690 13753 else
da0e507f
TS
13754 {
13755 as_fatal (_("invalid abi -mabi=%s"), arg);
13756 return 0;
13757 }
252b5132
RH
13758 break;
13759
6b76fefe 13760 case OPTION_M7000_HILO_FIX:
b34976b6 13761 mips_7000_hilo_fix = TRUE;
6b76fefe
CM
13762 break;
13763
9ee72ff1 13764 case OPTION_MNO_7000_HILO_FIX:
b34976b6 13765 mips_7000_hilo_fix = FALSE;
6b76fefe
CM
13766 break;
13767
ecb4347a 13768 case OPTION_MDEBUG:
b34976b6 13769 mips_flag_mdebug = TRUE;
ecb4347a
DJ
13770 break;
13771
13772 case OPTION_NO_MDEBUG:
b34976b6 13773 mips_flag_mdebug = FALSE;
ecb4347a 13774 break;
dcd410fe
RO
13775
13776 case OPTION_PDR:
13777 mips_flag_pdr = TRUE;
13778 break;
13779
13780 case OPTION_NO_PDR:
13781 mips_flag_pdr = FALSE;
13782 break;
0a44bf69
RS
13783
13784 case OPTION_MVXWORKS_PIC:
13785 mips_pic = VXWORKS_PIC;
13786 break;
ecb4347a 13787
ba92f887
MR
13788 case OPTION_NAN:
13789 if (strcmp (arg, "2008") == 0)
13790 mips_flag_nan2008 = TRUE;
13791 else if (strcmp (arg, "legacy") == 0)
13792 mips_flag_nan2008 = FALSE;
13793 else
13794 {
1661c76c 13795 as_fatal (_("invalid NaN setting -mnan=%s"), arg);
ba92f887
MR
13796 return 0;
13797 }
13798 break;
13799
252b5132
RH
13800 default:
13801 return 0;
13802 }
13803
c67a084a
NC
13804 mips_fix_loongson2f = mips_fix_loongson2f_nop || mips_fix_loongson2f_jump;
13805
252b5132
RH
13806 return 1;
13807}
316f5878
RS
13808\f
13809/* Set up globals to generate code for the ISA or processor
13810 described by INFO. */
252b5132 13811
252b5132 13812static void
17a2f251 13813mips_set_architecture (const struct mips_cpu_info *info)
252b5132 13814{
316f5878 13815 if (info != 0)
252b5132 13816 {
fef14a42
TS
13817 file_mips_arch = info->cpu;
13818 mips_opts.arch = info->cpu;
316f5878 13819 mips_opts.isa = info->isa;
252b5132 13820 }
252b5132
RH
13821}
13822
252b5132 13823
316f5878 13824/* Likewise for tuning. */
252b5132 13825
316f5878 13826static void
17a2f251 13827mips_set_tune (const struct mips_cpu_info *info)
316f5878
RS
13828{
13829 if (info != 0)
fef14a42 13830 mips_tune = info->cpu;
316f5878 13831}
80cc45a5 13832
34ba82a8 13833
252b5132 13834void
17a2f251 13835mips_after_parse_args (void)
e9670677 13836{
fef14a42
TS
13837 const struct mips_cpu_info *arch_info = 0;
13838 const struct mips_cpu_info *tune_info = 0;
13839
e9670677 13840 /* GP relative stuff not working for PE */
6caf9ef4 13841 if (strncmp (TARGET_OS, "pe", 2) == 0)
e9670677 13842 {
6caf9ef4 13843 if (g_switch_seen && g_switch_value != 0)
1661c76c 13844 as_bad (_("-G not supported in this configuration"));
e9670677
MR
13845 g_switch_value = 0;
13846 }
13847
cac012d6
AO
13848 if (mips_abi == NO_ABI)
13849 mips_abi = MIPS_DEFAULT_ABI;
13850
22923709
RS
13851 /* The following code determines the architecture and register size.
13852 Similar code was added to GCC 3.3 (see override_options() in
13853 config/mips/mips.c). The GAS and GCC code should be kept in sync
13854 as much as possible. */
e9670677 13855
316f5878 13856 if (mips_arch_string != 0)
fef14a42 13857 arch_info = mips_parse_cpu ("-march", mips_arch_string);
e9670677 13858
316f5878 13859 if (file_mips_isa != ISA_UNKNOWN)
e9670677 13860 {
316f5878 13861 /* Handle -mipsN. At this point, file_mips_isa contains the
fef14a42 13862 ISA level specified by -mipsN, while arch_info->isa contains
316f5878 13863 the -march selection (if any). */
fef14a42 13864 if (arch_info != 0)
e9670677 13865 {
316f5878
RS
13866 /* -march takes precedence over -mipsN, since it is more descriptive.
13867 There's no harm in specifying both as long as the ISA levels
13868 are the same. */
fef14a42 13869 if (file_mips_isa != arch_info->isa)
1661c76c
RS
13870 as_bad (_("-%s conflicts with the other architecture options,"
13871 " which imply -%s"),
316f5878 13872 mips_cpu_info_from_isa (file_mips_isa)->name,
fef14a42 13873 mips_cpu_info_from_isa (arch_info->isa)->name);
e9670677 13874 }
316f5878 13875 else
fef14a42 13876 arch_info = mips_cpu_info_from_isa (file_mips_isa);
e9670677
MR
13877 }
13878
fef14a42 13879 if (arch_info == 0)
95bfe26e
MF
13880 {
13881 arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT);
13882 gas_assert (arch_info);
13883 }
e9670677 13884
fef14a42 13885 if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa))
20203fb9 13886 as_bad (_("-march=%s is not compatible with the selected ABI"),
fef14a42
TS
13887 arch_info->name);
13888
13889 mips_set_architecture (arch_info);
13890
13891 /* Optimize for file_mips_arch, unless -mtune selects a different processor. */
13892 if (mips_tune_string != 0)
13893 tune_info = mips_parse_cpu ("-mtune", mips_tune_string);
e9670677 13894
fef14a42
TS
13895 if (tune_info == 0)
13896 mips_set_tune (arch_info);
13897 else
13898 mips_set_tune (tune_info);
e9670677 13899
316f5878 13900 if (file_mips_gp32 >= 0)
e9670677 13901 {
316f5878
RS
13902 /* The user specified the size of the integer registers. Make sure
13903 it agrees with the ABI and ISA. */
13904 if (file_mips_gp32 == 0 && !ISA_HAS_64BIT_REGS (mips_opts.isa))
13905 as_bad (_("-mgp64 used with a 32-bit processor"));
13906 else if (file_mips_gp32 == 1 && ABI_NEEDS_64BIT_REGS (mips_abi))
13907 as_bad (_("-mgp32 used with a 64-bit ABI"));
13908 else if (file_mips_gp32 == 0 && ABI_NEEDS_32BIT_REGS (mips_abi))
13909 as_bad (_("-mgp64 used with a 32-bit ABI"));
e9670677
MR
13910 }
13911 else
13912 {
316f5878
RS
13913 /* Infer the integer register size from the ABI and processor.
13914 Restrict ourselves to 32-bit registers if that's all the
13915 processor has, or if the ABI cannot handle 64-bit registers. */
13916 file_mips_gp32 = (ABI_NEEDS_32BIT_REGS (mips_abi)
13917 || !ISA_HAS_64BIT_REGS (mips_opts.isa));
e9670677
MR
13918 }
13919
ad3fea08
TS
13920 switch (file_mips_fp32)
13921 {
13922 default:
13923 case -1:
13924 /* No user specified float register size.
13925 ??? GAS treats single-float processors as though they had 64-bit
13926 float registers (although it complains when double-precision
13927 instructions are used). As things stand, saying they have 32-bit
13928 registers would lead to spurious "register must be even" messages.
13929 So here we assume float registers are never smaller than the
13930 integer ones. */
13931 if (file_mips_gp32 == 0)
13932 /* 64-bit integer registers implies 64-bit float registers. */
13933 file_mips_fp32 = 0;
c6278170 13934 else if ((mips_opts.ase & FP64_ASES)
ad3fea08
TS
13935 && ISA_HAS_64BIT_FPRS (mips_opts.isa))
13936 /* -mips3d and -mdmx imply 64-bit float registers, if possible. */
13937 file_mips_fp32 = 0;
13938 else
13939 /* 32-bit float registers. */
13940 file_mips_fp32 = 1;
13941 break;
13942
13943 /* The user specified the size of the float registers. Check if it
13944 agrees with the ABI and ISA. */
13945 case 0:
13946 if (!ISA_HAS_64BIT_FPRS (mips_opts.isa))
13947 as_bad (_("-mfp64 used with a 32-bit fpu"));
13948 else if (ABI_NEEDS_32BIT_REGS (mips_abi)
13949 && !ISA_HAS_MXHC1 (mips_opts.isa))
13950 as_warn (_("-mfp64 used with a 32-bit ABI"));
13951 break;
13952 case 1:
13953 if (ABI_NEEDS_64BIT_REGS (mips_abi))
13954 as_warn (_("-mfp32 used with a 64-bit ABI"));
13955 break;
13956 }
e9670677 13957
316f5878 13958 /* End of GCC-shared inference code. */
e9670677 13959
17a2f251
TS
13960 /* This flag is set when we have a 64-bit capable CPU but use only
13961 32-bit wide registers. Note that EABI does not use it. */
13962 if (ISA_HAS_64BIT_REGS (mips_opts.isa)
13963 && ((mips_abi == NO_ABI && file_mips_gp32 == 1)
13964 || mips_abi == O32_ABI))
316f5878 13965 mips_32bitmode = 1;
e9670677
MR
13966
13967 if (mips_opts.isa == ISA_MIPS1 && mips_trap)
13968 as_bad (_("trap exception not supported at ISA 1"));
13969
e9670677
MR
13970 /* If the selected architecture includes support for ASEs, enable
13971 generation of code for them. */
a4672219 13972 if (mips_opts.mips16 == -1)
fef14a42 13973 mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_arch)) ? 1 : 0;
df58fc94
RS
13974 if (mips_opts.micromips == -1)
13975 mips_opts.micromips = (CPU_HAS_MICROMIPS (file_mips_arch)) ? 1 : 0;
846ef2d0
RS
13976
13977 /* MIPS3D and MDMX require 64-bit FPRs, so -mfp32 should stop those
13978 ASEs from being selected implicitly. */
13979 if (file_mips_fp32 == 1)
13980 file_ase_explicit |= ASE_MIPS3D | ASE_MDMX;
13981
13982 /* If the user didn't explicitly select or deselect a particular ASE,
13983 use the default setting for the CPU. */
13984 mips_opts.ase |= (arch_info->ase & ~file_ase_explicit);
13985
e9670677 13986 file_mips_isa = mips_opts.isa;
846ef2d0 13987 file_ase = mips_opts.ase;
e9670677
MR
13988 mips_opts.gp32 = file_mips_gp32;
13989 mips_opts.fp32 = file_mips_fp32;
037b32b9
AN
13990 mips_opts.soft_float = file_mips_soft_float;
13991 mips_opts.single_float = file_mips_single_float;
e9670677 13992
c6278170
RS
13993 mips_check_isa_supports_ases ();
13994
ecb4347a 13995 if (mips_flag_mdebug < 0)
e8044f35 13996 mips_flag_mdebug = 0;
e9670677
MR
13997}
13998\f
13999void
17a2f251 14000mips_init_after_args (void)
252b5132
RH
14001{
14002 /* initialize opcodes */
14003 bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes;
beae10d5 14004 mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes;
252b5132
RH
14005}
14006
14007long
17a2f251 14008md_pcrel_from (fixS *fixP)
252b5132 14009{
a7ebbfdf
TS
14010 valueT addr = fixP->fx_where + fixP->fx_frag->fr_address;
14011 switch (fixP->fx_r_type)
14012 {
df58fc94
RS
14013 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
14014 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
14015 /* Return the address of the delay slot. */
14016 return addr + 2;
14017
14018 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
14019 case BFD_RELOC_MICROMIPS_JMP:
a7ebbfdf
TS
14020 case BFD_RELOC_16_PCREL_S2:
14021 case BFD_RELOC_MIPS_JMP:
14022 /* Return the address of the delay slot. */
14023 return addr + 4;
df58fc94 14024
b47468a6
CM
14025 case BFD_RELOC_32_PCREL:
14026 return addr;
14027
a7ebbfdf 14028 default:
58ea3d6a 14029 /* We have no relocation type for PC relative MIPS16 instructions. */
64817874
TS
14030 if (fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != now_seg)
14031 as_bad_where (fixP->fx_file, fixP->fx_line,
1661c76c
RS
14032 _("PC relative MIPS16 instruction references"
14033 " a different section"));
a7ebbfdf
TS
14034 return addr;
14035 }
252b5132
RH
14036}
14037
252b5132
RH
14038/* This is called before the symbol table is processed. In order to
14039 work with gcc when using mips-tfile, we must keep all local labels.
14040 However, in other cases, we want to discard them. If we were
14041 called with -g, but we didn't see any debugging information, it may
14042 mean that gcc is smuggling debugging information through to
14043 mips-tfile, in which case we must generate all local labels. */
14044
14045void
17a2f251 14046mips_frob_file_before_adjust (void)
252b5132
RH
14047{
14048#ifndef NO_ECOFF_DEBUGGING
14049 if (ECOFF_DEBUGGING
14050 && mips_debug != 0
14051 && ! ecoff_debugging_seen)
14052 flag_keep_locals = 1;
14053#endif
14054}
14055
3b91255e 14056/* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
55cf6793 14057 the corresponding LO16 reloc. This is called before md_apply_fix and
3b91255e
RS
14058 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
14059 relocation operators.
14060
14061 For our purposes, a %lo() expression matches a %got() or %hi()
14062 expression if:
14063
14064 (a) it refers to the same symbol; and
14065 (b) the offset applied in the %lo() expression is no lower than
14066 the offset applied in the %got() or %hi().
14067
14068 (b) allows us to cope with code like:
14069
14070 lui $4,%hi(foo)
14071 lh $4,%lo(foo+2)($4)
14072
14073 ...which is legal on RELA targets, and has a well-defined behaviour
14074 if the user knows that adding 2 to "foo" will not induce a carry to
14075 the high 16 bits.
14076
14077 When several %lo()s match a particular %got() or %hi(), we use the
14078 following rules to distinguish them:
14079
14080 (1) %lo()s with smaller offsets are a better match than %lo()s with
14081 higher offsets.
14082
14083 (2) %lo()s with no matching %got() or %hi() are better than those
14084 that already have a matching %got() or %hi().
14085
14086 (3) later %lo()s are better than earlier %lo()s.
14087
14088 These rules are applied in order.
14089
14090 (1) means, among other things, that %lo()s with identical offsets are
14091 chosen if they exist.
14092
14093 (2) means that we won't associate several high-part relocations with
14094 the same low-part relocation unless there's no alternative. Having
14095 several high parts for the same low part is a GNU extension; this rule
14096 allows careful users to avoid it.
14097
14098 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
14099 with the last high-part relocation being at the front of the list.
14100 It therefore makes sense to choose the last matching low-part
14101 relocation, all other things being equal. It's also easier
14102 to code that way. */
252b5132
RH
14103
14104void
17a2f251 14105mips_frob_file (void)
252b5132
RH
14106{
14107 struct mips_hi_fixup *l;
35903be0 14108 bfd_reloc_code_real_type looking_for_rtype = BFD_RELOC_UNUSED;
252b5132
RH
14109
14110 for (l = mips_hi_fixup_list; l != NULL; l = l->next)
14111 {
14112 segment_info_type *seginfo;
3b91255e
RS
14113 bfd_boolean matched_lo_p;
14114 fixS **hi_pos, **lo_pos, **pos;
252b5132 14115
9c2799c2 14116 gas_assert (reloc_needs_lo_p (l->fixp->fx_r_type));
252b5132 14117
5919d012 14118 /* If a GOT16 relocation turns out to be against a global symbol,
b886a2ab
RS
14119 there isn't supposed to be a matching LO. Ignore %gots against
14120 constants; we'll report an error for those later. */
738e5348 14121 if (got16_reloc_p (l->fixp->fx_r_type)
b886a2ab
RS
14122 && !(l->fixp->fx_addsy
14123 && pic_need_relax (l->fixp->fx_addsy, l->seg)))
5919d012
RS
14124 continue;
14125
14126 /* Check quickly whether the next fixup happens to be a matching %lo. */
14127 if (fixup_has_matching_lo_p (l->fixp))
252b5132
RH
14128 continue;
14129
252b5132 14130 seginfo = seg_info (l->seg);
252b5132 14131
3b91255e
RS
14132 /* Set HI_POS to the position of this relocation in the chain.
14133 Set LO_POS to the position of the chosen low-part relocation.
14134 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
14135 relocation that matches an immediately-preceding high-part
14136 relocation. */
14137 hi_pos = NULL;
14138 lo_pos = NULL;
14139 matched_lo_p = FALSE;
738e5348 14140 looking_for_rtype = matching_lo_reloc (l->fixp->fx_r_type);
35903be0 14141
3b91255e
RS
14142 for (pos = &seginfo->fix_root; *pos != NULL; pos = &(*pos)->fx_next)
14143 {
14144 if (*pos == l->fixp)
14145 hi_pos = pos;
14146
35903be0 14147 if ((*pos)->fx_r_type == looking_for_rtype
30cfc97a 14148 && symbol_same_p ((*pos)->fx_addsy, l->fixp->fx_addsy)
3b91255e
RS
14149 && (*pos)->fx_offset >= l->fixp->fx_offset
14150 && (lo_pos == NULL
14151 || (*pos)->fx_offset < (*lo_pos)->fx_offset
14152 || (!matched_lo_p
14153 && (*pos)->fx_offset == (*lo_pos)->fx_offset)))
14154 lo_pos = pos;
14155
14156 matched_lo_p = (reloc_needs_lo_p ((*pos)->fx_r_type)
14157 && fixup_has_matching_lo_p (*pos));
14158 }
14159
14160 /* If we found a match, remove the high-part relocation from its
14161 current position and insert it before the low-part relocation.
14162 Make the offsets match so that fixup_has_matching_lo_p()
14163 will return true.
14164
14165 We don't warn about unmatched high-part relocations since some
14166 versions of gcc have been known to emit dead "lui ...%hi(...)"
14167 instructions. */
14168 if (lo_pos != NULL)
14169 {
14170 l->fixp->fx_offset = (*lo_pos)->fx_offset;
14171 if (l->fixp->fx_next != *lo_pos)
252b5132 14172 {
3b91255e
RS
14173 *hi_pos = l->fixp->fx_next;
14174 l->fixp->fx_next = *lo_pos;
14175 *lo_pos = l->fixp;
252b5132 14176 }
252b5132
RH
14177 }
14178 }
14179}
14180
252b5132 14181int
17a2f251 14182mips_force_relocation (fixS *fixp)
252b5132 14183{
ae6063d4 14184 if (generic_force_reloc (fixp))
252b5132
RH
14185 return 1;
14186
df58fc94
RS
14187 /* We want to keep BFD_RELOC_MICROMIPS_*_PCREL_S1 relocation,
14188 so that the linker relaxation can update targets. */
14189 if (fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1
14190 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1
14191 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1)
14192 return 1;
14193
3e722fb5 14194 return 0;
252b5132
RH
14195}
14196
b886a2ab
RS
14197/* Read the instruction associated with RELOC from BUF. */
14198
14199static unsigned int
14200read_reloc_insn (char *buf, bfd_reloc_code_real_type reloc)
14201{
14202 if (mips16_reloc_p (reloc) || micromips_reloc_p (reloc))
14203 return read_compressed_insn (buf, 4);
14204 else
14205 return read_insn (buf);
14206}
14207
14208/* Write instruction INSN to BUF, given that it has been relocated
14209 by RELOC. */
14210
14211static void
14212write_reloc_insn (char *buf, bfd_reloc_code_real_type reloc,
14213 unsigned long insn)
14214{
14215 if (mips16_reloc_p (reloc) || micromips_reloc_p (reloc))
14216 write_compressed_insn (buf, insn, 4);
14217 else
14218 write_insn (buf, insn);
14219}
14220
252b5132
RH
14221/* Apply a fixup to the object file. */
14222
94f592af 14223void
55cf6793 14224md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
252b5132 14225{
4d68580a 14226 char *buf;
b886a2ab 14227 unsigned long insn;
a7ebbfdf 14228 reloc_howto_type *howto;
252b5132 14229
a7ebbfdf
TS
14230 /* We ignore generic BFD relocations we don't know about. */
14231 howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type);
14232 if (! howto)
14233 return;
65551fa4 14234
df58fc94
RS
14235 gas_assert (fixP->fx_size == 2
14236 || fixP->fx_size == 4
90ecf173
MR
14237 || fixP->fx_r_type == BFD_RELOC_16
14238 || fixP->fx_r_type == BFD_RELOC_64
14239 || fixP->fx_r_type == BFD_RELOC_CTOR
14240 || fixP->fx_r_type == BFD_RELOC_MIPS_SUB
df58fc94 14241 || fixP->fx_r_type == BFD_RELOC_MICROMIPS_SUB
90ecf173
MR
14242 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
14243 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY
14244 || fixP->fx_r_type == BFD_RELOC_MIPS_TLS_DTPREL64);
252b5132 14245
4d68580a 14246 buf = fixP->fx_frag->fr_literal + fixP->fx_where;
252b5132 14247
df58fc94
RS
14248 gas_assert (!fixP->fx_pcrel || fixP->fx_r_type == BFD_RELOC_16_PCREL_S2
14249 || fixP->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1
14250 || fixP->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1
b47468a6
CM
14251 || fixP->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1
14252 || fixP->fx_r_type == BFD_RELOC_32_PCREL);
b1dca8ee
RS
14253
14254 /* Don't treat parts of a composite relocation as done. There are two
14255 reasons for this:
14256
14257 (1) The second and third parts will be against 0 (RSS_UNDEF) but
14258 should nevertheless be emitted if the first part is.
14259
14260 (2) In normal usage, composite relocations are never assembly-time
14261 constants. The easiest way of dealing with the pathological
14262 exceptions is to generate a relocation against STN_UNDEF and
14263 leave everything up to the linker. */
3994f87e 14264 if (fixP->fx_addsy == NULL && !fixP->fx_pcrel && fixP->fx_tcbit == 0)
252b5132
RH
14265 fixP->fx_done = 1;
14266
14267 switch (fixP->fx_r_type)
14268 {
3f98094e
DJ
14269 case BFD_RELOC_MIPS_TLS_GD:
14270 case BFD_RELOC_MIPS_TLS_LDM:
741d6ea8
JM
14271 case BFD_RELOC_MIPS_TLS_DTPREL32:
14272 case BFD_RELOC_MIPS_TLS_DTPREL64:
3f98094e
DJ
14273 case BFD_RELOC_MIPS_TLS_DTPREL_HI16:
14274 case BFD_RELOC_MIPS_TLS_DTPREL_LO16:
14275 case BFD_RELOC_MIPS_TLS_GOTTPREL:
d0f13682
CLT
14276 case BFD_RELOC_MIPS_TLS_TPREL32:
14277 case BFD_RELOC_MIPS_TLS_TPREL64:
3f98094e
DJ
14278 case BFD_RELOC_MIPS_TLS_TPREL_HI16:
14279 case BFD_RELOC_MIPS_TLS_TPREL_LO16:
df58fc94
RS
14280 case BFD_RELOC_MICROMIPS_TLS_GD:
14281 case BFD_RELOC_MICROMIPS_TLS_LDM:
14282 case BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16:
14283 case BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16:
14284 case BFD_RELOC_MICROMIPS_TLS_GOTTPREL:
14285 case BFD_RELOC_MICROMIPS_TLS_TPREL_HI16:
14286 case BFD_RELOC_MICROMIPS_TLS_TPREL_LO16:
d0f13682
CLT
14287 case BFD_RELOC_MIPS16_TLS_GD:
14288 case BFD_RELOC_MIPS16_TLS_LDM:
14289 case BFD_RELOC_MIPS16_TLS_DTPREL_HI16:
14290 case BFD_RELOC_MIPS16_TLS_DTPREL_LO16:
14291 case BFD_RELOC_MIPS16_TLS_GOTTPREL:
14292 case BFD_RELOC_MIPS16_TLS_TPREL_HI16:
14293 case BFD_RELOC_MIPS16_TLS_TPREL_LO16:
b886a2ab
RS
14294 if (!fixP->fx_addsy)
14295 {
14296 as_bad_where (fixP->fx_file, fixP->fx_line,
14297 _("TLS relocation against a constant"));
14298 break;
14299 }
3f98094e
DJ
14300 S_SET_THREAD_LOCAL (fixP->fx_addsy);
14301 /* fall through */
14302
252b5132 14303 case BFD_RELOC_MIPS_JMP:
e369bcce
TS
14304 case BFD_RELOC_MIPS_SHIFT5:
14305 case BFD_RELOC_MIPS_SHIFT6:
14306 case BFD_RELOC_MIPS_GOT_DISP:
14307 case BFD_RELOC_MIPS_GOT_PAGE:
14308 case BFD_RELOC_MIPS_GOT_OFST:
14309 case BFD_RELOC_MIPS_SUB:
14310 case BFD_RELOC_MIPS_INSERT_A:
14311 case BFD_RELOC_MIPS_INSERT_B:
14312 case BFD_RELOC_MIPS_DELETE:
14313 case BFD_RELOC_MIPS_HIGHEST:
14314 case BFD_RELOC_MIPS_HIGHER:
14315 case BFD_RELOC_MIPS_SCN_DISP:
14316 case BFD_RELOC_MIPS_REL16:
14317 case BFD_RELOC_MIPS_RELGOT:
14318 case BFD_RELOC_MIPS_JALR:
252b5132
RH
14319 case BFD_RELOC_HI16:
14320 case BFD_RELOC_HI16_S:
b886a2ab 14321 case BFD_RELOC_LO16:
cdf6fd85 14322 case BFD_RELOC_GPREL16:
252b5132
RH
14323 case BFD_RELOC_MIPS_LITERAL:
14324 case BFD_RELOC_MIPS_CALL16:
14325 case BFD_RELOC_MIPS_GOT16:
cdf6fd85 14326 case BFD_RELOC_GPREL32:
252b5132
RH
14327 case BFD_RELOC_MIPS_GOT_HI16:
14328 case BFD_RELOC_MIPS_GOT_LO16:
14329 case BFD_RELOC_MIPS_CALL_HI16:
14330 case BFD_RELOC_MIPS_CALL_LO16:
14331 case BFD_RELOC_MIPS16_GPREL:
738e5348
RS
14332 case BFD_RELOC_MIPS16_GOT16:
14333 case BFD_RELOC_MIPS16_CALL16:
d6f16593
MR
14334 case BFD_RELOC_MIPS16_HI16:
14335 case BFD_RELOC_MIPS16_HI16_S:
b886a2ab 14336 case BFD_RELOC_MIPS16_LO16:
252b5132 14337 case BFD_RELOC_MIPS16_JMP:
df58fc94
RS
14338 case BFD_RELOC_MICROMIPS_JMP:
14339 case BFD_RELOC_MICROMIPS_GOT_DISP:
14340 case BFD_RELOC_MICROMIPS_GOT_PAGE:
14341 case BFD_RELOC_MICROMIPS_GOT_OFST:
14342 case BFD_RELOC_MICROMIPS_SUB:
14343 case BFD_RELOC_MICROMIPS_HIGHEST:
14344 case BFD_RELOC_MICROMIPS_HIGHER:
14345 case BFD_RELOC_MICROMIPS_SCN_DISP:
14346 case BFD_RELOC_MICROMIPS_JALR:
14347 case BFD_RELOC_MICROMIPS_HI16:
14348 case BFD_RELOC_MICROMIPS_HI16_S:
b886a2ab 14349 case BFD_RELOC_MICROMIPS_LO16:
df58fc94
RS
14350 case BFD_RELOC_MICROMIPS_GPREL16:
14351 case BFD_RELOC_MICROMIPS_LITERAL:
14352 case BFD_RELOC_MICROMIPS_CALL16:
14353 case BFD_RELOC_MICROMIPS_GOT16:
14354 case BFD_RELOC_MICROMIPS_GOT_HI16:
14355 case BFD_RELOC_MICROMIPS_GOT_LO16:
14356 case BFD_RELOC_MICROMIPS_CALL_HI16:
14357 case BFD_RELOC_MICROMIPS_CALL_LO16:
067ec077 14358 case BFD_RELOC_MIPS_EH:
b886a2ab
RS
14359 if (fixP->fx_done)
14360 {
14361 offsetT value;
14362
14363 if (calculate_reloc (fixP->fx_r_type, *valP, &value))
14364 {
14365 insn = read_reloc_insn (buf, fixP->fx_r_type);
14366 if (mips16_reloc_p (fixP->fx_r_type))
14367 insn |= mips16_immed_extend (value, 16);
14368 else
14369 insn |= (value & 0xffff);
14370 write_reloc_insn (buf, fixP->fx_r_type, insn);
14371 }
14372 else
14373 as_bad_where (fixP->fx_file, fixP->fx_line,
1661c76c 14374 _("unsupported constant in relocation"));
b886a2ab 14375 }
252b5132
RH
14376 break;
14377
252b5132
RH
14378 case BFD_RELOC_64:
14379 /* This is handled like BFD_RELOC_32, but we output a sign
14380 extended value if we are only 32 bits. */
3e722fb5 14381 if (fixP->fx_done)
252b5132
RH
14382 {
14383 if (8 <= sizeof (valueT))
4d68580a 14384 md_number_to_chars (buf, *valP, 8);
252b5132
RH
14385 else
14386 {
a7ebbfdf 14387 valueT hiv;
252b5132 14388
a7ebbfdf 14389 if ((*valP & 0x80000000) != 0)
252b5132
RH
14390 hiv = 0xffffffff;
14391 else
14392 hiv = 0;
4d68580a
RS
14393 md_number_to_chars (buf + (target_big_endian ? 4 : 0), *valP, 4);
14394 md_number_to_chars (buf + (target_big_endian ? 0 : 4), hiv, 4);
252b5132
RH
14395 }
14396 }
14397 break;
14398
056350c6 14399 case BFD_RELOC_RVA:
252b5132 14400 case BFD_RELOC_32:
b47468a6 14401 case BFD_RELOC_32_PCREL:
252b5132
RH
14402 case BFD_RELOC_16:
14403 /* If we are deleting this reloc entry, we must fill in the
54f4ddb3
TS
14404 value now. This can happen if we have a .word which is not
14405 resolved when it appears but is later defined. */
252b5132 14406 if (fixP->fx_done)
4d68580a 14407 md_number_to_chars (buf, *valP, fixP->fx_size);
252b5132
RH
14408 break;
14409
252b5132 14410 case BFD_RELOC_16_PCREL_S2:
a7ebbfdf 14411 if ((*valP & 0x3) != 0)
cb56d3d3 14412 as_bad_where (fixP->fx_file, fixP->fx_line,
1661c76c 14413 _("branch to misaligned address (%lx)"), (long) *valP);
cb56d3d3 14414
54f4ddb3
TS
14415 /* We need to save the bits in the instruction since fixup_segment()
14416 might be deleting the relocation entry (i.e., a branch within
14417 the current segment). */
a7ebbfdf 14418 if (! fixP->fx_done)
bb2d6cd7 14419 break;
252b5132 14420
54f4ddb3 14421 /* Update old instruction data. */
4d68580a 14422 insn = read_insn (buf);
252b5132 14423
a7ebbfdf
TS
14424 if (*valP + 0x20000 <= 0x3ffff)
14425 {
14426 insn |= (*valP >> 2) & 0xffff;
4d68580a 14427 write_insn (buf, insn);
a7ebbfdf
TS
14428 }
14429 else if (mips_pic == NO_PIC
14430 && fixP->fx_done
14431 && fixP->fx_frag->fr_address >= text_section->vma
14432 && (fixP->fx_frag->fr_address
587aac4e 14433 < text_section->vma + bfd_get_section_size (text_section))
a7ebbfdf
TS
14434 && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */
14435 || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */
14436 || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */
252b5132
RH
14437 {
14438 /* The branch offset is too large. If this is an
14439 unconditional branch, and we are not generating PIC code,
14440 we can convert it to an absolute jump instruction. */
a7ebbfdf
TS
14441 if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */
14442 insn = 0x0c000000; /* jal */
252b5132 14443 else
a7ebbfdf
TS
14444 insn = 0x08000000; /* j */
14445 fixP->fx_r_type = BFD_RELOC_MIPS_JMP;
14446 fixP->fx_done = 0;
14447 fixP->fx_addsy = section_symbol (text_section);
14448 *valP += md_pcrel_from (fixP);
4d68580a 14449 write_insn (buf, insn);
a7ebbfdf
TS
14450 }
14451 else
14452 {
14453 /* If we got here, we have branch-relaxation disabled,
14454 and there's nothing we can do to fix this instruction
14455 without turning it into a longer sequence. */
14456 as_bad_where (fixP->fx_file, fixP->fx_line,
1661c76c 14457 _("branch out of range"));
252b5132 14458 }
252b5132
RH
14459 break;
14460
df58fc94
RS
14461 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
14462 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
14463 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
14464 /* We adjust the offset back to even. */
14465 if ((*valP & 0x1) != 0)
14466 --(*valP);
14467
14468 if (! fixP->fx_done)
14469 break;
14470
14471 /* Should never visit here, because we keep the relocation. */
14472 abort ();
14473 break;
14474
252b5132
RH
14475 case BFD_RELOC_VTABLE_INHERIT:
14476 fixP->fx_done = 0;
14477 if (fixP->fx_addsy
14478 && !S_IS_DEFINED (fixP->fx_addsy)
14479 && !S_IS_WEAK (fixP->fx_addsy))
14480 S_SET_WEAK (fixP->fx_addsy);
14481 break;
14482
14483 case BFD_RELOC_VTABLE_ENTRY:
14484 fixP->fx_done = 0;
14485 break;
14486
14487 default:
b37df7c4 14488 abort ();
252b5132 14489 }
a7ebbfdf
TS
14490
14491 /* Remember value for tc_gen_reloc. */
14492 fixP->fx_addnumber = *valP;
252b5132
RH
14493}
14494
252b5132 14495static symbolS *
17a2f251 14496get_symbol (void)
252b5132
RH
14497{
14498 int c;
14499 char *name;
14500 symbolS *p;
14501
14502 name = input_line_pointer;
14503 c = get_symbol_end ();
14504 p = (symbolS *) symbol_find_or_make (name);
14505 *input_line_pointer = c;
14506 return p;
14507}
14508
742a56fe
RS
14509/* Align the current frag to a given power of two. If a particular
14510 fill byte should be used, FILL points to an integer that contains
14511 that byte, otherwise FILL is null.
14512
462427c4
RS
14513 This function used to have the comment:
14514
14515 The MIPS assembler also automatically adjusts any preceding label.
14516
14517 The implementation therefore applied the adjustment to a maximum of
14518 one label. However, other label adjustments are applied to batches
14519 of labels, and adjusting just one caused problems when new labels
14520 were added for the sake of debugging or unwind information.
14521 We therefore adjust all preceding labels (given as LABELS) instead. */
252b5132
RH
14522
14523static void
462427c4 14524mips_align (int to, int *fill, struct insn_label_list *labels)
252b5132 14525{
7d10b47d 14526 mips_emit_delays ();
df58fc94 14527 mips_record_compressed_mode ();
742a56fe
RS
14528 if (fill == NULL && subseg_text_p (now_seg))
14529 frag_align_code (to, 0);
14530 else
14531 frag_align (to, fill ? *fill : 0, 0);
252b5132 14532 record_alignment (now_seg, to);
462427c4 14533 mips_move_labels (labels, FALSE);
252b5132
RH
14534}
14535
14536/* Align to a given power of two. .align 0 turns off the automatic
14537 alignment used by the data creating pseudo-ops. */
14538
14539static void
17a2f251 14540s_align (int x ATTRIBUTE_UNUSED)
252b5132 14541{
742a56fe 14542 int temp, fill_value, *fill_ptr;
49954fb4 14543 long max_alignment = 28;
252b5132 14544
54f4ddb3 14545 /* o Note that the assembler pulls down any immediately preceding label
252b5132 14546 to the aligned address.
54f4ddb3 14547 o It's not documented but auto alignment is reinstated by
252b5132 14548 a .align pseudo instruction.
54f4ddb3 14549 o Note also that after auto alignment is turned off the mips assembler
252b5132 14550 issues an error on attempt to assemble an improperly aligned data item.
54f4ddb3 14551 We don't. */
252b5132
RH
14552
14553 temp = get_absolute_expression ();
14554 if (temp > max_alignment)
1661c76c 14555 as_bad (_("alignment too large, %d assumed"), temp = max_alignment);
252b5132
RH
14556 else if (temp < 0)
14557 {
1661c76c 14558 as_warn (_("alignment negative, 0 assumed"));
252b5132
RH
14559 temp = 0;
14560 }
14561 if (*input_line_pointer == ',')
14562 {
f9419b05 14563 ++input_line_pointer;
742a56fe
RS
14564 fill_value = get_absolute_expression ();
14565 fill_ptr = &fill_value;
252b5132
RH
14566 }
14567 else
742a56fe 14568 fill_ptr = 0;
252b5132
RH
14569 if (temp)
14570 {
a8dbcb85
TS
14571 segment_info_type *si = seg_info (now_seg);
14572 struct insn_label_list *l = si->label_list;
54f4ddb3 14573 /* Auto alignment should be switched on by next section change. */
252b5132 14574 auto_align = 1;
462427c4 14575 mips_align (temp, fill_ptr, l);
252b5132
RH
14576 }
14577 else
14578 {
14579 auto_align = 0;
14580 }
14581
14582 demand_empty_rest_of_line ();
14583}
14584
252b5132 14585static void
17a2f251 14586s_change_sec (int sec)
252b5132
RH
14587{
14588 segT seg;
14589
252b5132
RH
14590 /* The ELF backend needs to know that we are changing sections, so
14591 that .previous works correctly. We could do something like check
b6ff326e 14592 for an obj_section_change_hook macro, but that might be confusing
252b5132
RH
14593 as it would not be appropriate to use it in the section changing
14594 functions in read.c, since obj-elf.c intercepts those. FIXME:
14595 This should be cleaner, somehow. */
f3ded42a 14596 obj_elf_section_change_hook ();
252b5132 14597
7d10b47d 14598 mips_emit_delays ();
6a32d874 14599
252b5132
RH
14600 switch (sec)
14601 {
14602 case 't':
14603 s_text (0);
14604 break;
14605 case 'd':
14606 s_data (0);
14607 break;
14608 case 'b':
14609 subseg_set (bss_section, (subsegT) get_absolute_expression ());
14610 demand_empty_rest_of_line ();
14611 break;
14612
14613 case 'r':
4d0d148d
TS
14614 seg = subseg_new (RDATA_SECTION_NAME,
14615 (subsegT) get_absolute_expression ());
f3ded42a
RS
14616 bfd_set_section_flags (stdoutput, seg, (SEC_ALLOC | SEC_LOAD
14617 | SEC_READONLY | SEC_RELOC
14618 | SEC_DATA));
14619 if (strncmp (TARGET_OS, "elf", 3) != 0)
14620 record_alignment (seg, 4);
4d0d148d 14621 demand_empty_rest_of_line ();
252b5132
RH
14622 break;
14623
14624 case 's':
4d0d148d 14625 seg = subseg_new (".sdata", (subsegT) get_absolute_expression ());
f3ded42a
RS
14626 bfd_set_section_flags (stdoutput, seg,
14627 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA);
14628 if (strncmp (TARGET_OS, "elf", 3) != 0)
14629 record_alignment (seg, 4);
4d0d148d
TS
14630 demand_empty_rest_of_line ();
14631 break;
998b3c36
MR
14632
14633 case 'B':
14634 seg = subseg_new (".sbss", (subsegT) get_absolute_expression ());
f3ded42a
RS
14635 bfd_set_section_flags (stdoutput, seg, SEC_ALLOC);
14636 if (strncmp (TARGET_OS, "elf", 3) != 0)
14637 record_alignment (seg, 4);
998b3c36
MR
14638 demand_empty_rest_of_line ();
14639 break;
252b5132
RH
14640 }
14641
14642 auto_align = 1;
14643}
b34976b6 14644
cca86cc8 14645void
17a2f251 14646s_change_section (int ignore ATTRIBUTE_UNUSED)
cca86cc8 14647{
cca86cc8
SC
14648 char *section_name;
14649 char c;
684022ea 14650 char next_c = 0;
cca86cc8
SC
14651 int section_type;
14652 int section_flag;
14653 int section_entry_size;
14654 int section_alignment;
b34976b6 14655
cca86cc8
SC
14656 section_name = input_line_pointer;
14657 c = get_symbol_end ();
a816d1ed
AO
14658 if (c)
14659 next_c = *(input_line_pointer + 1);
cca86cc8 14660
4cf0dd0d
TS
14661 /* Do we have .section Name<,"flags">? */
14662 if (c != ',' || (c == ',' && next_c == '"'))
cca86cc8 14663 {
4cf0dd0d
TS
14664 /* just after name is now '\0'. */
14665 *input_line_pointer = c;
cca86cc8
SC
14666 input_line_pointer = section_name;
14667 obj_elf_section (ignore);
14668 return;
14669 }
14670 input_line_pointer++;
14671
14672 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
14673 if (c == ',')
14674 section_type = get_absolute_expression ();
14675 else
14676 section_type = 0;
14677 if (*input_line_pointer++ == ',')
14678 section_flag = get_absolute_expression ();
14679 else
14680 section_flag = 0;
14681 if (*input_line_pointer++ == ',')
14682 section_entry_size = get_absolute_expression ();
14683 else
14684 section_entry_size = 0;
14685 if (*input_line_pointer++ == ',')
14686 section_alignment = get_absolute_expression ();
14687 else
14688 section_alignment = 0;
87975d2a
AM
14689 /* FIXME: really ignore? */
14690 (void) section_alignment;
cca86cc8 14691
a816d1ed
AO
14692 section_name = xstrdup (section_name);
14693
8ab8a5c8
RS
14694 /* When using the generic form of .section (as implemented by obj-elf.c),
14695 there's no way to set the section type to SHT_MIPS_DWARF. Users have
14696 traditionally had to fall back on the more common @progbits instead.
14697
14698 There's nothing really harmful in this, since bfd will correct
14699 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
708587a4 14700 means that, for backwards compatibility, the special_section entries
8ab8a5c8
RS
14701 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
14702
14703 Even so, we shouldn't force users of the MIPS .section syntax to
14704 incorrectly label the sections as SHT_PROGBITS. The best compromise
14705 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
14706 generic type-checking code. */
14707 if (section_type == SHT_MIPS_DWARF)
14708 section_type = SHT_PROGBITS;
14709
cca86cc8
SC
14710 obj_elf_change_section (section_name, section_type, section_flag,
14711 section_entry_size, 0, 0, 0);
a816d1ed
AO
14712
14713 if (now_seg->name != section_name)
14714 free (section_name);
cca86cc8 14715}
252b5132
RH
14716
14717void
17a2f251 14718mips_enable_auto_align (void)
252b5132
RH
14719{
14720 auto_align = 1;
14721}
14722
14723static void
17a2f251 14724s_cons (int log_size)
252b5132 14725{
a8dbcb85
TS
14726 segment_info_type *si = seg_info (now_seg);
14727 struct insn_label_list *l = si->label_list;
252b5132 14728
7d10b47d 14729 mips_emit_delays ();
252b5132 14730 if (log_size > 0 && auto_align)
462427c4 14731 mips_align (log_size, 0, l);
252b5132 14732 cons (1 << log_size);
a1facbec 14733 mips_clear_insn_labels ();
252b5132
RH
14734}
14735
14736static void
17a2f251 14737s_float_cons (int type)
252b5132 14738{
a8dbcb85
TS
14739 segment_info_type *si = seg_info (now_seg);
14740 struct insn_label_list *l = si->label_list;
252b5132 14741
7d10b47d 14742 mips_emit_delays ();
252b5132
RH
14743
14744 if (auto_align)
49309057
ILT
14745 {
14746 if (type == 'd')
462427c4 14747 mips_align (3, 0, l);
49309057 14748 else
462427c4 14749 mips_align (2, 0, l);
49309057 14750 }
252b5132 14751
252b5132 14752 float_cons (type);
a1facbec 14753 mips_clear_insn_labels ();
252b5132
RH
14754}
14755
14756/* Handle .globl. We need to override it because on Irix 5 you are
14757 permitted to say
14758 .globl foo .text
14759 where foo is an undefined symbol, to mean that foo should be
14760 considered to be the address of a function. */
14761
14762static void
17a2f251 14763s_mips_globl (int x ATTRIBUTE_UNUSED)
252b5132
RH
14764{
14765 char *name;
14766 int c;
14767 symbolS *symbolP;
14768 flagword flag;
14769
8a06b769 14770 do
252b5132 14771 {
8a06b769 14772 name = input_line_pointer;
252b5132 14773 c = get_symbol_end ();
8a06b769
TS
14774 symbolP = symbol_find_or_make (name);
14775 S_SET_EXTERNAL (symbolP);
14776
252b5132 14777 *input_line_pointer = c;
8a06b769 14778 SKIP_WHITESPACE ();
252b5132 14779
8a06b769
TS
14780 /* On Irix 5, every global symbol that is not explicitly labelled as
14781 being a function is apparently labelled as being an object. */
14782 flag = BSF_OBJECT;
252b5132 14783
8a06b769
TS
14784 if (!is_end_of_line[(unsigned char) *input_line_pointer]
14785 && (*input_line_pointer != ','))
14786 {
14787 char *secname;
14788 asection *sec;
14789
14790 secname = input_line_pointer;
14791 c = get_symbol_end ();
14792 sec = bfd_get_section_by_name (stdoutput, secname);
14793 if (sec == NULL)
14794 as_bad (_("%s: no such section"), secname);
14795 *input_line_pointer = c;
14796
14797 if (sec != NULL && (sec->flags & SEC_CODE) != 0)
14798 flag = BSF_FUNCTION;
14799 }
14800
14801 symbol_get_bfdsym (symbolP)->flags |= flag;
14802
14803 c = *input_line_pointer;
14804 if (c == ',')
14805 {
14806 input_line_pointer++;
14807 SKIP_WHITESPACE ();
14808 if (is_end_of_line[(unsigned char) *input_line_pointer])
14809 c = '\n';
14810 }
14811 }
14812 while (c == ',');
252b5132 14813
252b5132
RH
14814 demand_empty_rest_of_line ();
14815}
14816
14817static void
17a2f251 14818s_option (int x ATTRIBUTE_UNUSED)
252b5132
RH
14819{
14820 char *opt;
14821 char c;
14822
14823 opt = input_line_pointer;
14824 c = get_symbol_end ();
14825
14826 if (*opt == 'O')
14827 {
14828 /* FIXME: What does this mean? */
14829 }
14830 else if (strncmp (opt, "pic", 3) == 0)
14831 {
14832 int i;
14833
14834 i = atoi (opt + 3);
14835 if (i == 0)
14836 mips_pic = NO_PIC;
14837 else if (i == 2)
143d77c5 14838 {
8b828383 14839 mips_pic = SVR4_PIC;
143d77c5
EC
14840 mips_abicalls = TRUE;
14841 }
252b5132
RH
14842 else
14843 as_bad (_(".option pic%d not supported"), i);
14844
4d0d148d 14845 if (mips_pic == SVR4_PIC)
252b5132
RH
14846 {
14847 if (g_switch_seen && g_switch_value != 0)
14848 as_warn (_("-G may not be used with SVR4 PIC code"));
14849 g_switch_value = 0;
14850 bfd_set_gp_size (stdoutput, 0);
14851 }
14852 }
14853 else
1661c76c 14854 as_warn (_("unrecognized option \"%s\""), opt);
252b5132
RH
14855
14856 *input_line_pointer = c;
14857 demand_empty_rest_of_line ();
14858}
14859
14860/* This structure is used to hold a stack of .set values. */
14861
e972090a
NC
14862struct mips_option_stack
14863{
252b5132
RH
14864 struct mips_option_stack *next;
14865 struct mips_set_options options;
14866};
14867
14868static struct mips_option_stack *mips_opts_stack;
14869
14870/* Handle the .set pseudo-op. */
14871
14872static void
17a2f251 14873s_mipsset (int x ATTRIBUTE_UNUSED)
252b5132
RH
14874{
14875 char *name = input_line_pointer, ch;
c6278170 14876 const struct mips_ase *ase;
252b5132
RH
14877
14878 while (!is_end_of_line[(unsigned char) *input_line_pointer])
f9419b05 14879 ++input_line_pointer;
252b5132
RH
14880 ch = *input_line_pointer;
14881 *input_line_pointer = '\0';
14882
14883 if (strcmp (name, "reorder") == 0)
14884 {
7d10b47d
RS
14885 if (mips_opts.noreorder)
14886 end_noreorder ();
252b5132
RH
14887 }
14888 else if (strcmp (name, "noreorder") == 0)
14889 {
7d10b47d
RS
14890 if (!mips_opts.noreorder)
14891 start_noreorder ();
252b5132 14892 }
741fe287
MR
14893 else if (strncmp (name, "at=", 3) == 0)
14894 {
14895 char *s = name + 3;
14896
14897 if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, &mips_opts.at))
1661c76c 14898 as_bad (_("unrecognized register name `%s'"), s);
741fe287 14899 }
252b5132
RH
14900 else if (strcmp (name, "at") == 0)
14901 {
741fe287 14902 mips_opts.at = ATREG;
252b5132
RH
14903 }
14904 else if (strcmp (name, "noat") == 0)
14905 {
741fe287 14906 mips_opts.at = ZERO;
252b5132
RH
14907 }
14908 else if (strcmp (name, "macro") == 0)
14909 {
14910 mips_opts.warn_about_macros = 0;
14911 }
14912 else if (strcmp (name, "nomacro") == 0)
14913 {
14914 if (mips_opts.noreorder == 0)
14915 as_bad (_("`noreorder' must be set before `nomacro'"));
14916 mips_opts.warn_about_macros = 1;
14917 }
14918 else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0)
14919 {
14920 mips_opts.nomove = 0;
14921 }
14922 else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0)
14923 {
14924 mips_opts.nomove = 1;
14925 }
14926 else if (strcmp (name, "bopt") == 0)
14927 {
14928 mips_opts.nobopt = 0;
14929 }
14930 else if (strcmp (name, "nobopt") == 0)
14931 {
14932 mips_opts.nobopt = 1;
14933 }
ad3fea08
TS
14934 else if (strcmp (name, "gp=default") == 0)
14935 mips_opts.gp32 = file_mips_gp32;
14936 else if (strcmp (name, "gp=32") == 0)
14937 mips_opts.gp32 = 1;
14938 else if (strcmp (name, "gp=64") == 0)
14939 {
14940 if (!ISA_HAS_64BIT_REGS (mips_opts.isa))
20203fb9 14941 as_warn (_("%s isa does not support 64-bit registers"),
ad3fea08
TS
14942 mips_cpu_info_from_isa (mips_opts.isa)->name);
14943 mips_opts.gp32 = 0;
14944 }
14945 else if (strcmp (name, "fp=default") == 0)
14946 mips_opts.fp32 = file_mips_fp32;
14947 else if (strcmp (name, "fp=32") == 0)
14948 mips_opts.fp32 = 1;
14949 else if (strcmp (name, "fp=64") == 0)
14950 {
14951 if (!ISA_HAS_64BIT_FPRS (mips_opts.isa))
20203fb9 14952 as_warn (_("%s isa does not support 64-bit floating point registers"),
ad3fea08
TS
14953 mips_cpu_info_from_isa (mips_opts.isa)->name);
14954 mips_opts.fp32 = 0;
14955 }
037b32b9
AN
14956 else if (strcmp (name, "softfloat") == 0)
14957 mips_opts.soft_float = 1;
14958 else if (strcmp (name, "hardfloat") == 0)
14959 mips_opts.soft_float = 0;
14960 else if (strcmp (name, "singlefloat") == 0)
14961 mips_opts.single_float = 1;
14962 else if (strcmp (name, "doublefloat") == 0)
14963 mips_opts.single_float = 0;
252b5132
RH
14964 else if (strcmp (name, "mips16") == 0
14965 || strcmp (name, "MIPS-16") == 0)
df58fc94
RS
14966 {
14967 if (mips_opts.micromips == 1)
14968 as_fatal (_("`mips16' cannot be used with `micromips'"));
14969 mips_opts.mips16 = 1;
14970 }
252b5132
RH
14971 else if (strcmp (name, "nomips16") == 0
14972 || strcmp (name, "noMIPS-16") == 0)
14973 mips_opts.mips16 = 0;
df58fc94
RS
14974 else if (strcmp (name, "micromips") == 0)
14975 {
14976 if (mips_opts.mips16 == 1)
14977 as_fatal (_("`micromips' cannot be used with `mips16'"));
14978 mips_opts.micromips = 1;
14979 }
14980 else if (strcmp (name, "nomicromips") == 0)
14981 mips_opts.micromips = 0;
c6278170
RS
14982 else if (name[0] == 'n'
14983 && name[1] == 'o'
14984 && (ase = mips_lookup_ase (name + 2)))
14985 mips_set_ase (ase, FALSE);
14986 else if ((ase = mips_lookup_ase (name)))
14987 mips_set_ase (ase, TRUE);
1a2c1fad 14988 else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0)
252b5132 14989 {
af7ee8bf 14990 int reset = 0;
252b5132 14991
1a2c1fad
CD
14992 /* Permit the user to change the ISA and architecture on the fly.
14993 Needless to say, misuse can cause serious problems. */
81a21e38 14994 if (strcmp (name, "mips0") == 0 || strcmp (name, "arch=default") == 0)
af7ee8bf
CD
14995 {
14996 reset = 1;
14997 mips_opts.isa = file_mips_isa;
1a2c1fad 14998 mips_opts.arch = file_mips_arch;
1a2c1fad
CD
14999 }
15000 else if (strncmp (name, "arch=", 5) == 0)
15001 {
15002 const struct mips_cpu_info *p;
15003
15004 p = mips_parse_cpu("internal use", name + 5);
15005 if (!p)
15006 as_bad (_("unknown architecture %s"), name + 5);
15007 else
15008 {
15009 mips_opts.arch = p->cpu;
15010 mips_opts.isa = p->isa;
15011 }
15012 }
81a21e38
TS
15013 else if (strncmp (name, "mips", 4) == 0)
15014 {
15015 const struct mips_cpu_info *p;
15016
15017 p = mips_parse_cpu("internal use", name);
15018 if (!p)
15019 as_bad (_("unknown ISA level %s"), name + 4);
15020 else
15021 {
15022 mips_opts.arch = p->cpu;
15023 mips_opts.isa = p->isa;
15024 }
15025 }
af7ee8bf 15026 else
81a21e38 15027 as_bad (_("unknown ISA or architecture %s"), name);
af7ee8bf
CD
15028
15029 switch (mips_opts.isa)
98d3f06f
KH
15030 {
15031 case 0:
98d3f06f 15032 break;
af7ee8bf
CD
15033 case ISA_MIPS1:
15034 case ISA_MIPS2:
15035 case ISA_MIPS32:
15036 case ISA_MIPS32R2:
98d3f06f
KH
15037 mips_opts.gp32 = 1;
15038 mips_opts.fp32 = 1;
15039 break;
af7ee8bf
CD
15040 case ISA_MIPS3:
15041 case ISA_MIPS4:
15042 case ISA_MIPS5:
15043 case ISA_MIPS64:
5f74bc13 15044 case ISA_MIPS64R2:
98d3f06f 15045 mips_opts.gp32 = 0;
e407c74b
NC
15046 if (mips_opts.arch == CPU_R5900)
15047 {
15048 mips_opts.fp32 = 1;
15049 }
15050 else
15051 {
98d3f06f 15052 mips_opts.fp32 = 0;
e407c74b 15053 }
98d3f06f
KH
15054 break;
15055 default:
15056 as_bad (_("unknown ISA level %s"), name + 4);
15057 break;
15058 }
af7ee8bf 15059 if (reset)
98d3f06f 15060 {
af7ee8bf
CD
15061 mips_opts.gp32 = file_mips_gp32;
15062 mips_opts.fp32 = file_mips_fp32;
98d3f06f 15063 }
252b5132
RH
15064 }
15065 else if (strcmp (name, "autoextend") == 0)
15066 mips_opts.noautoextend = 0;
15067 else if (strcmp (name, "noautoextend") == 0)
15068 mips_opts.noautoextend = 1;
833794fc
MR
15069 else if (strcmp (name, "insn32") == 0)
15070 mips_opts.insn32 = TRUE;
15071 else if (strcmp (name, "noinsn32") == 0)
15072 mips_opts.insn32 = FALSE;
252b5132
RH
15073 else if (strcmp (name, "push") == 0)
15074 {
15075 struct mips_option_stack *s;
15076
15077 s = (struct mips_option_stack *) xmalloc (sizeof *s);
15078 s->next = mips_opts_stack;
15079 s->options = mips_opts;
15080 mips_opts_stack = s;
15081 }
15082 else if (strcmp (name, "pop") == 0)
15083 {
15084 struct mips_option_stack *s;
15085
15086 s = mips_opts_stack;
15087 if (s == NULL)
15088 as_bad (_(".set pop with no .set push"));
15089 else
15090 {
15091 /* If we're changing the reorder mode we need to handle
15092 delay slots correctly. */
15093 if (s->options.noreorder && ! mips_opts.noreorder)
7d10b47d 15094 start_noreorder ();
252b5132 15095 else if (! s->options.noreorder && mips_opts.noreorder)
7d10b47d 15096 end_noreorder ();
252b5132
RH
15097
15098 mips_opts = s->options;
15099 mips_opts_stack = s->next;
15100 free (s);
15101 }
15102 }
aed1a261
RS
15103 else if (strcmp (name, "sym32") == 0)
15104 mips_opts.sym32 = TRUE;
15105 else if (strcmp (name, "nosym32") == 0)
15106 mips_opts.sym32 = FALSE;
e6559e01
JM
15107 else if (strchr (name, ','))
15108 {
15109 /* Generic ".set" directive; use the generic handler. */
15110 *input_line_pointer = ch;
15111 input_line_pointer = name;
15112 s_set (0);
15113 return;
15114 }
252b5132
RH
15115 else
15116 {
1661c76c 15117 as_warn (_("tried to set unrecognized symbol: %s\n"), name);
252b5132 15118 }
c6278170 15119 mips_check_isa_supports_ases ();
252b5132
RH
15120 *input_line_pointer = ch;
15121 demand_empty_rest_of_line ();
15122}
15123
15124/* Handle the .abicalls pseudo-op. I believe this is equivalent to
15125 .option pic2. It means to generate SVR4 PIC calls. */
15126
15127static void
17a2f251 15128s_abicalls (int ignore ATTRIBUTE_UNUSED)
252b5132
RH
15129{
15130 mips_pic = SVR4_PIC;
143d77c5 15131 mips_abicalls = TRUE;
4d0d148d
TS
15132
15133 if (g_switch_seen && g_switch_value != 0)
15134 as_warn (_("-G may not be used with SVR4 PIC code"));
15135 g_switch_value = 0;
15136
252b5132
RH
15137 bfd_set_gp_size (stdoutput, 0);
15138 demand_empty_rest_of_line ();
15139}
15140
15141/* Handle the .cpload pseudo-op. This is used when generating SVR4
15142 PIC code. It sets the $gp register for the function based on the
15143 function address, which is in the register named in the argument.
15144 This uses a relocation against _gp_disp, which is handled specially
15145 by the linker. The result is:
15146 lui $gp,%hi(_gp_disp)
15147 addiu $gp,$gp,%lo(_gp_disp)
15148 addu $gp,$gp,.cpload argument
aa6975fb
ILT
15149 The .cpload argument is normally $25 == $t9.
15150
15151 The -mno-shared option changes this to:
bbe506e8
TS
15152 lui $gp,%hi(__gnu_local_gp)
15153 addiu $gp,$gp,%lo(__gnu_local_gp)
aa6975fb
ILT
15154 and the argument is ignored. This saves an instruction, but the
15155 resulting code is not position independent; it uses an absolute
bbe506e8
TS
15156 address for __gnu_local_gp. Thus code assembled with -mno-shared
15157 can go into an ordinary executable, but not into a shared library. */
252b5132
RH
15158
15159static void
17a2f251 15160s_cpload (int ignore ATTRIBUTE_UNUSED)
252b5132
RH
15161{
15162 expressionS ex;
aa6975fb
ILT
15163 int reg;
15164 int in_shared;
252b5132 15165
6478892d
TS
15166 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
15167 .cpload is ignored. */
15168 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
252b5132
RH
15169 {
15170 s_ignore (0);
15171 return;
15172 }
15173
a276b80c
MR
15174 if (mips_opts.mips16)
15175 {
15176 as_bad (_("%s not supported in MIPS16 mode"), ".cpload");
15177 ignore_rest_of_line ();
15178 return;
15179 }
15180
d3ecfc59 15181 /* .cpload should be in a .set noreorder section. */
252b5132
RH
15182 if (mips_opts.noreorder == 0)
15183 as_warn (_(".cpload not in noreorder section"));
15184
aa6975fb
ILT
15185 reg = tc_get_register (0);
15186
15187 /* If we need to produce a 64-bit address, we are better off using
15188 the default instruction sequence. */
aed1a261 15189 in_shared = mips_in_shared || HAVE_64BIT_SYMBOLS;
aa6975fb 15190
252b5132 15191 ex.X_op = O_symbol;
bbe506e8
TS
15192 ex.X_add_symbol = symbol_find_or_make (in_shared ? "_gp_disp" :
15193 "__gnu_local_gp");
252b5132
RH
15194 ex.X_op_symbol = NULL;
15195 ex.X_add_number = 0;
15196
15197 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
49309057 15198 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
252b5132 15199
8a75745d
MR
15200 mips_mark_labels ();
15201 mips_assembling_insn = TRUE;
15202
584892a6 15203 macro_start ();
67c0d1eb
RS
15204 macro_build_lui (&ex, mips_gp_register);
15205 macro_build (&ex, "addiu", "t,r,j", mips_gp_register,
17a2f251 15206 mips_gp_register, BFD_RELOC_LO16);
aa6975fb
ILT
15207 if (in_shared)
15208 macro_build (NULL, "addu", "d,v,t", mips_gp_register,
15209 mips_gp_register, reg);
584892a6 15210 macro_end ();
252b5132 15211
8a75745d 15212 mips_assembling_insn = FALSE;
252b5132
RH
15213 demand_empty_rest_of_line ();
15214}
15215
6478892d
TS
15216/* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
15217 .cpsetup $reg1, offset|$reg2, label
15218
15219 If offset is given, this results in:
15220 sd $gp, offset($sp)
956cd1d6 15221 lui $gp, %hi(%neg(%gp_rel(label)))
698b7d9d
TS
15222 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
15223 daddu $gp, $gp, $reg1
6478892d
TS
15224
15225 If $reg2 is given, this results in:
15226 daddu $reg2, $gp, $0
956cd1d6 15227 lui $gp, %hi(%neg(%gp_rel(label)))
698b7d9d
TS
15228 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
15229 daddu $gp, $gp, $reg1
aa6975fb
ILT
15230 $reg1 is normally $25 == $t9.
15231
15232 The -mno-shared option replaces the last three instructions with
15233 lui $gp,%hi(_gp)
54f4ddb3 15234 addiu $gp,$gp,%lo(_gp) */
aa6975fb 15235
6478892d 15236static void
17a2f251 15237s_cpsetup (int ignore ATTRIBUTE_UNUSED)
6478892d
TS
15238{
15239 expressionS ex_off;
15240 expressionS ex_sym;
15241 int reg1;
6478892d 15242
8586fc66 15243 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
6478892d
TS
15244 We also need NewABI support. */
15245 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
15246 {
15247 s_ignore (0);
15248 return;
15249 }
15250
a276b80c
MR
15251 if (mips_opts.mips16)
15252 {
15253 as_bad (_("%s not supported in MIPS16 mode"), ".cpsetup");
15254 ignore_rest_of_line ();
15255 return;
15256 }
15257
6478892d
TS
15258 reg1 = tc_get_register (0);
15259 SKIP_WHITESPACE ();
15260 if (*input_line_pointer != ',')
15261 {
15262 as_bad (_("missing argument separator ',' for .cpsetup"));
15263 return;
15264 }
15265 else
80245285 15266 ++input_line_pointer;
6478892d
TS
15267 SKIP_WHITESPACE ();
15268 if (*input_line_pointer == '$')
80245285
TS
15269 {
15270 mips_cpreturn_register = tc_get_register (0);
15271 mips_cpreturn_offset = -1;
15272 }
6478892d 15273 else
80245285
TS
15274 {
15275 mips_cpreturn_offset = get_absolute_expression ();
15276 mips_cpreturn_register = -1;
15277 }
6478892d
TS
15278 SKIP_WHITESPACE ();
15279 if (*input_line_pointer != ',')
15280 {
15281 as_bad (_("missing argument separator ',' for .cpsetup"));
15282 return;
15283 }
15284 else
f9419b05 15285 ++input_line_pointer;
6478892d 15286 SKIP_WHITESPACE ();
f21f8242 15287 expression (&ex_sym);
6478892d 15288
8a75745d
MR
15289 mips_mark_labels ();
15290 mips_assembling_insn = TRUE;
15291
584892a6 15292 macro_start ();
6478892d
TS
15293 if (mips_cpreturn_register == -1)
15294 {
15295 ex_off.X_op = O_constant;
15296 ex_off.X_add_symbol = NULL;
15297 ex_off.X_op_symbol = NULL;
15298 ex_off.X_add_number = mips_cpreturn_offset;
15299
67c0d1eb 15300 macro_build (&ex_off, "sd", "t,o(b)", mips_gp_register,
17a2f251 15301 BFD_RELOC_LO16, SP);
6478892d
TS
15302 }
15303 else
67c0d1eb 15304 macro_build (NULL, "daddu", "d,v,t", mips_cpreturn_register,
17a2f251 15305 mips_gp_register, 0);
6478892d 15306
aed1a261 15307 if (mips_in_shared || HAVE_64BIT_SYMBOLS)
aa6975fb 15308 {
df58fc94 15309 macro_build (&ex_sym, "lui", LUI_FMT, mips_gp_register,
aa6975fb
ILT
15310 -1, BFD_RELOC_GPREL16, BFD_RELOC_MIPS_SUB,
15311 BFD_RELOC_HI16_S);
15312
15313 macro_build (&ex_sym, "addiu", "t,r,j", mips_gp_register,
15314 mips_gp_register, -1, BFD_RELOC_GPREL16,
15315 BFD_RELOC_MIPS_SUB, BFD_RELOC_LO16);
15316
15317 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register,
15318 mips_gp_register, reg1);
15319 }
15320 else
15321 {
15322 expressionS ex;
15323
15324 ex.X_op = O_symbol;
4184909a 15325 ex.X_add_symbol = symbol_find_or_make ("__gnu_local_gp");
aa6975fb
ILT
15326 ex.X_op_symbol = NULL;
15327 ex.X_add_number = 0;
6e1304d8 15328
aa6975fb
ILT
15329 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
15330 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
15331
15332 macro_build_lui (&ex, mips_gp_register);
15333 macro_build (&ex, "addiu", "t,r,j", mips_gp_register,
15334 mips_gp_register, BFD_RELOC_LO16);
15335 }
f21f8242 15336
584892a6 15337 macro_end ();
6478892d 15338
8a75745d 15339 mips_assembling_insn = FALSE;
6478892d
TS
15340 demand_empty_rest_of_line ();
15341}
15342
15343static void
17a2f251 15344s_cplocal (int ignore ATTRIBUTE_UNUSED)
6478892d
TS
15345{
15346 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
54f4ddb3 15347 .cplocal is ignored. */
6478892d
TS
15348 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
15349 {
15350 s_ignore (0);
15351 return;
15352 }
15353
a276b80c
MR
15354 if (mips_opts.mips16)
15355 {
15356 as_bad (_("%s not supported in MIPS16 mode"), ".cplocal");
15357 ignore_rest_of_line ();
15358 return;
15359 }
15360
6478892d 15361 mips_gp_register = tc_get_register (0);
85b51719 15362 demand_empty_rest_of_line ();
6478892d
TS
15363}
15364
252b5132
RH
15365/* Handle the .cprestore pseudo-op. This stores $gp into a given
15366 offset from $sp. The offset is remembered, and after making a PIC
15367 call $gp is restored from that location. */
15368
15369static void
17a2f251 15370s_cprestore (int ignore ATTRIBUTE_UNUSED)
252b5132
RH
15371{
15372 expressionS ex;
252b5132 15373
6478892d 15374 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
c9914766 15375 .cprestore is ignored. */
6478892d 15376 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
252b5132
RH
15377 {
15378 s_ignore (0);
15379 return;
15380 }
15381
a276b80c
MR
15382 if (mips_opts.mips16)
15383 {
15384 as_bad (_("%s not supported in MIPS16 mode"), ".cprestore");
15385 ignore_rest_of_line ();
15386 return;
15387 }
15388
252b5132 15389 mips_cprestore_offset = get_absolute_expression ();
7a621144 15390 mips_cprestore_valid = 1;
252b5132
RH
15391
15392 ex.X_op = O_constant;
15393 ex.X_add_symbol = NULL;
15394 ex.X_op_symbol = NULL;
15395 ex.X_add_number = mips_cprestore_offset;
15396
8a75745d
MR
15397 mips_mark_labels ();
15398 mips_assembling_insn = TRUE;
15399
584892a6 15400 macro_start ();
67c0d1eb
RS
15401 macro_build_ldst_constoffset (&ex, ADDRESS_STORE_INSN, mips_gp_register,
15402 SP, HAVE_64BIT_ADDRESSES);
584892a6 15403 macro_end ();
252b5132 15404
8a75745d 15405 mips_assembling_insn = FALSE;
252b5132
RH
15406 demand_empty_rest_of_line ();
15407}
15408
6478892d 15409/* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
67c1ffbe 15410 was given in the preceding .cpsetup, it results in:
6478892d 15411 ld $gp, offset($sp)
76b3015f 15412
6478892d 15413 If a register $reg2 was given there, it results in:
54f4ddb3
TS
15414 daddu $gp, $reg2, $0 */
15415
6478892d 15416static void
17a2f251 15417s_cpreturn (int ignore ATTRIBUTE_UNUSED)
6478892d
TS
15418{
15419 expressionS ex;
6478892d
TS
15420
15421 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
15422 We also need NewABI support. */
15423 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
15424 {
15425 s_ignore (0);
15426 return;
15427 }
15428
a276b80c
MR
15429 if (mips_opts.mips16)
15430 {
15431 as_bad (_("%s not supported in MIPS16 mode"), ".cpreturn");
15432 ignore_rest_of_line ();
15433 return;
15434 }
15435
8a75745d
MR
15436 mips_mark_labels ();
15437 mips_assembling_insn = TRUE;
15438
584892a6 15439 macro_start ();
6478892d
TS
15440 if (mips_cpreturn_register == -1)
15441 {
15442 ex.X_op = O_constant;
15443 ex.X_add_symbol = NULL;
15444 ex.X_op_symbol = NULL;
15445 ex.X_add_number = mips_cpreturn_offset;
15446
67c0d1eb 15447 macro_build (&ex, "ld", "t,o(b)", mips_gp_register, BFD_RELOC_LO16, SP);
6478892d
TS
15448 }
15449 else
67c0d1eb 15450 macro_build (NULL, "daddu", "d,v,t", mips_gp_register,
17a2f251 15451 mips_cpreturn_register, 0);
584892a6 15452 macro_end ();
6478892d 15453
8a75745d 15454 mips_assembling_insn = FALSE;
6478892d
TS
15455 demand_empty_rest_of_line ();
15456}
15457
d0f13682
CLT
15458/* Handle a .dtprelword, .dtpreldword, .tprelword, or .tpreldword
15459 pseudo-op; DIRSTR says which. The pseudo-op generates a BYTES-size
15460 DTP- or TP-relative relocation of type RTYPE, for use in either DWARF
15461 debug information or MIPS16 TLS. */
741d6ea8
JM
15462
15463static void
d0f13682
CLT
15464s_tls_rel_directive (const size_t bytes, const char *dirstr,
15465 bfd_reloc_code_real_type rtype)
741d6ea8
JM
15466{
15467 expressionS ex;
15468 char *p;
15469
15470 expression (&ex);
15471
15472 if (ex.X_op != O_symbol)
15473 {
1661c76c 15474 as_bad (_("unsupported use of %s"), dirstr);
741d6ea8
JM
15475 ignore_rest_of_line ();
15476 }
15477
15478 p = frag_more (bytes);
15479 md_number_to_chars (p, 0, bytes);
d0f13682 15480 fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, FALSE, rtype);
741d6ea8 15481 demand_empty_rest_of_line ();
de64cffd 15482 mips_clear_insn_labels ();
741d6ea8
JM
15483}
15484
15485/* Handle .dtprelword. */
15486
15487static void
15488s_dtprelword (int ignore ATTRIBUTE_UNUSED)
15489{
d0f13682 15490 s_tls_rel_directive (4, ".dtprelword", BFD_RELOC_MIPS_TLS_DTPREL32);
741d6ea8
JM
15491}
15492
15493/* Handle .dtpreldword. */
15494
15495static void
15496s_dtpreldword (int ignore ATTRIBUTE_UNUSED)
15497{
d0f13682
CLT
15498 s_tls_rel_directive (8, ".dtpreldword", BFD_RELOC_MIPS_TLS_DTPREL64);
15499}
15500
15501/* Handle .tprelword. */
15502
15503static void
15504s_tprelword (int ignore ATTRIBUTE_UNUSED)
15505{
15506 s_tls_rel_directive (4, ".tprelword", BFD_RELOC_MIPS_TLS_TPREL32);
15507}
15508
15509/* Handle .tpreldword. */
15510
15511static void
15512s_tpreldword (int ignore ATTRIBUTE_UNUSED)
15513{
15514 s_tls_rel_directive (8, ".tpreldword", BFD_RELOC_MIPS_TLS_TPREL64);
741d6ea8
JM
15515}
15516
6478892d
TS
15517/* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
15518 code. It sets the offset to use in gp_rel relocations. */
15519
15520static void
17a2f251 15521s_gpvalue (int ignore ATTRIBUTE_UNUSED)
6478892d
TS
15522{
15523 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
15524 We also need NewABI support. */
15525 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
15526 {
15527 s_ignore (0);
15528 return;
15529 }
15530
def2e0dd 15531 mips_gprel_offset = get_absolute_expression ();
6478892d
TS
15532
15533 demand_empty_rest_of_line ();
15534}
15535
252b5132
RH
15536/* Handle the .gpword pseudo-op. This is used when generating PIC
15537 code. It generates a 32 bit GP relative reloc. */
15538
15539static void
17a2f251 15540s_gpword (int ignore ATTRIBUTE_UNUSED)
252b5132 15541{
a8dbcb85
TS
15542 segment_info_type *si;
15543 struct insn_label_list *l;
252b5132
RH
15544 expressionS ex;
15545 char *p;
15546
15547 /* When not generating PIC code, this is treated as .word. */
15548 if (mips_pic != SVR4_PIC)
15549 {
15550 s_cons (2);
15551 return;
15552 }
15553
a8dbcb85
TS
15554 si = seg_info (now_seg);
15555 l = si->label_list;
7d10b47d 15556 mips_emit_delays ();
252b5132 15557 if (auto_align)
462427c4 15558 mips_align (2, 0, l);
252b5132
RH
15559
15560 expression (&ex);
a1facbec 15561 mips_clear_insn_labels ();
252b5132
RH
15562
15563 if (ex.X_op != O_symbol || ex.X_add_number != 0)
15564 {
1661c76c 15565 as_bad (_("unsupported use of .gpword"));
252b5132
RH
15566 ignore_rest_of_line ();
15567 }
15568
15569 p = frag_more (4);
17a2f251 15570 md_number_to_chars (p, 0, 4);
b34976b6 15571 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
cdf6fd85 15572 BFD_RELOC_GPREL32);
252b5132
RH
15573
15574 demand_empty_rest_of_line ();
15575}
15576
10181a0d 15577static void
17a2f251 15578s_gpdword (int ignore ATTRIBUTE_UNUSED)
10181a0d 15579{
a8dbcb85
TS
15580 segment_info_type *si;
15581 struct insn_label_list *l;
10181a0d
AO
15582 expressionS ex;
15583 char *p;
15584
15585 /* When not generating PIC code, this is treated as .dword. */
15586 if (mips_pic != SVR4_PIC)
15587 {
15588 s_cons (3);
15589 return;
15590 }
15591
a8dbcb85
TS
15592 si = seg_info (now_seg);
15593 l = si->label_list;
7d10b47d 15594 mips_emit_delays ();
10181a0d 15595 if (auto_align)
462427c4 15596 mips_align (3, 0, l);
10181a0d
AO
15597
15598 expression (&ex);
a1facbec 15599 mips_clear_insn_labels ();
10181a0d
AO
15600
15601 if (ex.X_op != O_symbol || ex.X_add_number != 0)
15602 {
1661c76c 15603 as_bad (_("unsupported use of .gpdword"));
10181a0d
AO
15604 ignore_rest_of_line ();
15605 }
15606
15607 p = frag_more (8);
17a2f251 15608 md_number_to_chars (p, 0, 8);
a105a300 15609 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
6e1304d8 15610 BFD_RELOC_GPREL32)->fx_tcbit = 1;
10181a0d
AO
15611
15612 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
6e1304d8
RS
15613 fix_new (frag_now, p - frag_now->fr_literal, 8, NULL, 0,
15614 FALSE, BFD_RELOC_64)->fx_tcbit = 1;
10181a0d
AO
15615
15616 demand_empty_rest_of_line ();
15617}
15618
a3f278e2
CM
15619/* Handle the .ehword pseudo-op. This is used when generating unwinding
15620 tables. It generates a R_MIPS_EH reloc. */
15621
15622static void
15623s_ehword (int ignore ATTRIBUTE_UNUSED)
15624{
15625 expressionS ex;
15626 char *p;
15627
15628 mips_emit_delays ();
15629
15630 expression (&ex);
15631 mips_clear_insn_labels ();
15632
15633 if (ex.X_op != O_symbol || ex.X_add_number != 0)
15634 {
1661c76c 15635 as_bad (_("unsupported use of .ehword"));
a3f278e2
CM
15636 ignore_rest_of_line ();
15637 }
15638
15639 p = frag_more (4);
15640 md_number_to_chars (p, 0, 4);
15641 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
15642 BFD_RELOC_MIPS_EH);
15643
15644 demand_empty_rest_of_line ();
15645}
15646
252b5132
RH
15647/* Handle the .cpadd pseudo-op. This is used when dealing with switch
15648 tables in SVR4 PIC code. */
15649
15650static void
17a2f251 15651s_cpadd (int ignore ATTRIBUTE_UNUSED)
252b5132 15652{
252b5132
RH
15653 int reg;
15654
10181a0d
AO
15655 /* This is ignored when not generating SVR4 PIC code. */
15656 if (mips_pic != SVR4_PIC)
252b5132
RH
15657 {
15658 s_ignore (0);
15659 return;
15660 }
15661
8a75745d
MR
15662 mips_mark_labels ();
15663 mips_assembling_insn = TRUE;
15664
252b5132 15665 /* Add $gp to the register named as an argument. */
584892a6 15666 macro_start ();
252b5132 15667 reg = tc_get_register (0);
67c0d1eb 15668 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register);
584892a6 15669 macro_end ();
252b5132 15670
8a75745d 15671 mips_assembling_insn = FALSE;
bdaaa2e1 15672 demand_empty_rest_of_line ();
252b5132
RH
15673}
15674
15675/* Handle the .insn pseudo-op. This marks instruction labels in
df58fc94 15676 mips16/micromips mode. This permits the linker to handle them specially,
252b5132
RH
15677 such as generating jalx instructions when needed. We also make
15678 them odd for the duration of the assembly, in order to generate the
15679 right sort of code. We will make them even in the adjust_symtab
15680 routine, while leaving them marked. This is convenient for the
15681 debugger and the disassembler. The linker knows to make them odd
15682 again. */
15683
15684static void
17a2f251 15685s_insn (int ignore ATTRIBUTE_UNUSED)
252b5132 15686{
df58fc94 15687 mips_mark_labels ();
252b5132
RH
15688
15689 demand_empty_rest_of_line ();
15690}
15691
ba92f887
MR
15692/* Handle the .nan pseudo-op. */
15693
15694static void
15695s_nan (int ignore ATTRIBUTE_UNUSED)
15696{
15697 static const char str_legacy[] = "legacy";
15698 static const char str_2008[] = "2008";
15699 size_t i;
15700
15701 for (i = 0; !is_end_of_line[(unsigned char) input_line_pointer[i]]; i++);
15702
15703 if (i == sizeof (str_2008) - 1
15704 && memcmp (input_line_pointer, str_2008, i) == 0)
15705 mips_flag_nan2008 = TRUE;
15706 else if (i == sizeof (str_legacy) - 1
15707 && memcmp (input_line_pointer, str_legacy, i) == 0)
15708 mips_flag_nan2008 = FALSE;
15709 else
1661c76c 15710 as_bad (_("bad .nan directive"));
ba92f887
MR
15711
15712 input_line_pointer += i;
15713 demand_empty_rest_of_line ();
15714}
15715
754e2bb9
RS
15716/* Handle a .stab[snd] directive. Ideally these directives would be
15717 implemented in a transparent way, so that removing them would not
15718 have any effect on the generated instructions. However, s_stab
15719 internally changes the section, so in practice we need to decide
15720 now whether the preceding label marks compressed code. We do not
15721 support changing the compression mode of a label after a .stab*
15722 directive, such as in:
15723
15724 foo:
15725 .stabs ...
15726 .set mips16
15727
15728 so the current mode wins. */
252b5132
RH
15729
15730static void
17a2f251 15731s_mips_stab (int type)
252b5132 15732{
754e2bb9 15733 mips_mark_labels ();
252b5132
RH
15734 s_stab (type);
15735}
15736
54f4ddb3 15737/* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */
252b5132
RH
15738
15739static void
17a2f251 15740s_mips_weakext (int ignore ATTRIBUTE_UNUSED)
252b5132
RH
15741{
15742 char *name;
15743 int c;
15744 symbolS *symbolP;
15745 expressionS exp;
15746
15747 name = input_line_pointer;
15748 c = get_symbol_end ();
15749 symbolP = symbol_find_or_make (name);
15750 S_SET_WEAK (symbolP);
15751 *input_line_pointer = c;
15752
15753 SKIP_WHITESPACE ();
15754
15755 if (! is_end_of_line[(unsigned char) *input_line_pointer])
15756 {
15757 if (S_IS_DEFINED (symbolP))
15758 {
20203fb9 15759 as_bad (_("ignoring attempt to redefine symbol %s"),
252b5132
RH
15760 S_GET_NAME (symbolP));
15761 ignore_rest_of_line ();
15762 return;
15763 }
bdaaa2e1 15764
252b5132
RH
15765 if (*input_line_pointer == ',')
15766 {
15767 ++input_line_pointer;
15768 SKIP_WHITESPACE ();
15769 }
bdaaa2e1 15770
252b5132
RH
15771 expression (&exp);
15772 if (exp.X_op != O_symbol)
15773 {
20203fb9 15774 as_bad (_("bad .weakext directive"));
98d3f06f 15775 ignore_rest_of_line ();
252b5132
RH
15776 return;
15777 }
49309057 15778 symbol_set_value_expression (symbolP, &exp);
252b5132
RH
15779 }
15780
15781 demand_empty_rest_of_line ();
15782}
15783
15784/* Parse a register string into a number. Called from the ECOFF code
15785 to parse .frame. The argument is non-zero if this is the frame
15786 register, so that we can record it in mips_frame_reg. */
15787
15788int
17a2f251 15789tc_get_register (int frame)
252b5132 15790{
707bfff6 15791 unsigned int reg;
252b5132
RH
15792
15793 SKIP_WHITESPACE ();
707bfff6
TS
15794 if (! reg_lookup (&input_line_pointer, RWARN | RTYPE_NUM | RTYPE_GP, &reg))
15795 reg = 0;
252b5132 15796 if (frame)
7a621144
DJ
15797 {
15798 mips_frame_reg = reg != 0 ? reg : SP;
15799 mips_frame_reg_valid = 1;
15800 mips_cprestore_valid = 0;
15801 }
252b5132
RH
15802 return reg;
15803}
15804
15805valueT
17a2f251 15806md_section_align (asection *seg, valueT addr)
252b5132
RH
15807{
15808 int align = bfd_get_section_alignment (stdoutput, seg);
15809
f3ded42a
RS
15810 /* We don't need to align ELF sections to the full alignment.
15811 However, Irix 5 may prefer that we align them at least to a 16
15812 byte boundary. We don't bother to align the sections if we
15813 are targeted for an embedded system. */
15814 if (strncmp (TARGET_OS, "elf", 3) == 0)
15815 return addr;
15816 if (align > 4)
15817 align = 4;
252b5132
RH
15818
15819 return ((addr + (1 << align) - 1) & (-1 << align));
15820}
15821
15822/* Utility routine, called from above as well. If called while the
15823 input file is still being read, it's only an approximation. (For
15824 example, a symbol may later become defined which appeared to be
15825 undefined earlier.) */
15826
15827static int
17a2f251 15828nopic_need_relax (symbolS *sym, int before_relaxing)
252b5132
RH
15829{
15830 if (sym == 0)
15831 return 0;
15832
4d0d148d 15833 if (g_switch_value > 0)
252b5132
RH
15834 {
15835 const char *symname;
15836 int change;
15837
c9914766 15838 /* Find out whether this symbol can be referenced off the $gp
252b5132
RH
15839 register. It can be if it is smaller than the -G size or if
15840 it is in the .sdata or .sbss section. Certain symbols can
c9914766 15841 not be referenced off the $gp, although it appears as though
252b5132
RH
15842 they can. */
15843 symname = S_GET_NAME (sym);
15844 if (symname != (const char *) NULL
15845 && (strcmp (symname, "eprol") == 0
15846 || strcmp (symname, "etext") == 0
15847 || strcmp (symname, "_gp") == 0
15848 || strcmp (symname, "edata") == 0
15849 || strcmp (symname, "_fbss") == 0
15850 || strcmp (symname, "_fdata") == 0
15851 || strcmp (symname, "_ftext") == 0
15852 || strcmp (symname, "end") == 0
15853 || strcmp (symname, "_gp_disp") == 0))
15854 change = 1;
15855 else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym))
15856 && (0
15857#ifndef NO_ECOFF_DEBUGGING
49309057
ILT
15858 || (symbol_get_obj (sym)->ecoff_extern_size != 0
15859 && (symbol_get_obj (sym)->ecoff_extern_size
15860 <= g_switch_value))
252b5132
RH
15861#endif
15862 /* We must defer this decision until after the whole
15863 file has been read, since there might be a .extern
15864 after the first use of this symbol. */
15865 || (before_relaxing
15866#ifndef NO_ECOFF_DEBUGGING
49309057 15867 && symbol_get_obj (sym)->ecoff_extern_size == 0
252b5132
RH
15868#endif
15869 && S_GET_VALUE (sym) == 0)
15870 || (S_GET_VALUE (sym) != 0
15871 && S_GET_VALUE (sym) <= g_switch_value)))
15872 change = 0;
15873 else
15874 {
15875 const char *segname;
15876
15877 segname = segment_name (S_GET_SEGMENT (sym));
9c2799c2 15878 gas_assert (strcmp (segname, ".lit8") != 0
252b5132
RH
15879 && strcmp (segname, ".lit4") != 0);
15880 change = (strcmp (segname, ".sdata") != 0
fba2b7f9
GK
15881 && strcmp (segname, ".sbss") != 0
15882 && strncmp (segname, ".sdata.", 7) != 0
d4dc2f22
TS
15883 && strncmp (segname, ".sbss.", 6) != 0
15884 && strncmp (segname, ".gnu.linkonce.sb.", 17) != 0
fba2b7f9 15885 && strncmp (segname, ".gnu.linkonce.s.", 16) != 0);
252b5132
RH
15886 }
15887 return change;
15888 }
15889 else
c9914766 15890 /* We are not optimizing for the $gp register. */
252b5132
RH
15891 return 1;
15892}
15893
5919d012
RS
15894
15895/* Return true if the given symbol should be considered local for SVR4 PIC. */
15896
15897static bfd_boolean
17a2f251 15898pic_need_relax (symbolS *sym, asection *segtype)
5919d012
RS
15899{
15900 asection *symsec;
5919d012
RS
15901
15902 /* Handle the case of a symbol equated to another symbol. */
15903 while (symbol_equated_reloc_p (sym))
15904 {
15905 symbolS *n;
15906
5f0fe04b 15907 /* It's possible to get a loop here in a badly written program. */
5919d012
RS
15908 n = symbol_get_value_expression (sym)->X_add_symbol;
15909 if (n == sym)
15910 break;
15911 sym = n;
15912 }
15913
df1f3cda
DD
15914 if (symbol_section_p (sym))
15915 return TRUE;
15916
5919d012
RS
15917 symsec = S_GET_SEGMENT (sym);
15918
5919d012 15919 /* This must duplicate the test in adjust_reloc_syms. */
45dfa85a
AM
15920 return (!bfd_is_und_section (symsec)
15921 && !bfd_is_abs_section (symsec)
5f0fe04b
TS
15922 && !bfd_is_com_section (symsec)
15923 && !s_is_linkonce (sym, segtype)
5919d012 15924 /* A global or weak symbol is treated as external. */
f3ded42a 15925 && (!S_IS_WEAK (sym) && !S_IS_EXTERNAL (sym)));
5919d012
RS
15926}
15927
15928
252b5132
RH
15929/* Given a mips16 variant frag FRAGP, return non-zero if it needs an
15930 extended opcode. SEC is the section the frag is in. */
15931
15932static int
17a2f251 15933mips16_extended_frag (fragS *fragp, asection *sec, long stretch)
252b5132
RH
15934{
15935 int type;
3ccad066 15936 const struct mips_int_operand *operand;
252b5132 15937 offsetT val;
252b5132 15938 segT symsec;
98aa84af 15939 fragS *sym_frag;
252b5132
RH
15940
15941 if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype))
15942 return 0;
15943 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype))
15944 return 1;
15945
15946 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
3ccad066 15947 operand = mips16_immed_operand (type, FALSE);
252b5132 15948
98aa84af 15949 sym_frag = symbol_get_frag (fragp->fr_symbol);
ac62c346 15950 val = S_GET_VALUE (fragp->fr_symbol);
98aa84af 15951 symsec = S_GET_SEGMENT (fragp->fr_symbol);
252b5132 15952
3ccad066 15953 if (operand->root.type == OP_PCREL)
252b5132 15954 {
3ccad066 15955 const struct mips_pcrel_operand *pcrel_op;
252b5132 15956 addressT addr;
3ccad066 15957 offsetT maxtiny;
252b5132
RH
15958
15959 /* We won't have the section when we are called from
15960 mips_relax_frag. However, we will always have been called
15961 from md_estimate_size_before_relax first. If this is a
15962 branch to a different section, we mark it as such. If SEC is
15963 NULL, and the frag is not marked, then it must be a branch to
15964 the same section. */
3ccad066 15965 pcrel_op = (const struct mips_pcrel_operand *) operand;
252b5132
RH
15966 if (sec == NULL)
15967 {
15968 if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype))
15969 return 1;
15970 }
15971 else
15972 {
98aa84af 15973 /* Must have been called from md_estimate_size_before_relax. */
252b5132
RH
15974 if (symsec != sec)
15975 {
15976 fragp->fr_subtype =
15977 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
15978
15979 /* FIXME: We should support this, and let the linker
15980 catch branches and loads that are out of range. */
15981 as_bad_where (fragp->fr_file, fragp->fr_line,
15982 _("unsupported PC relative reference to different section"));
15983
15984 return 1;
15985 }
98aa84af
AM
15986 if (fragp != sym_frag && sym_frag->fr_address == 0)
15987 /* Assume non-extended on the first relaxation pass.
15988 The address we have calculated will be bogus if this is
15989 a forward branch to another frag, as the forward frag
15990 will have fr_address == 0. */
15991 return 0;
252b5132
RH
15992 }
15993
15994 /* In this case, we know for sure that the symbol fragment is in
98aa84af
AM
15995 the same section. If the relax_marker of the symbol fragment
15996 differs from the relax_marker of this fragment, we have not
15997 yet adjusted the symbol fragment fr_address. We want to add
252b5132
RH
15998 in STRETCH in order to get a better estimate of the address.
15999 This particularly matters because of the shift bits. */
16000 if (stretch != 0
98aa84af 16001 && sym_frag->relax_marker != fragp->relax_marker)
252b5132
RH
16002 {
16003 fragS *f;
16004
16005 /* Adjust stretch for any alignment frag. Note that if have
16006 been expanding the earlier code, the symbol may be
16007 defined in what appears to be an earlier frag. FIXME:
16008 This doesn't handle the fr_subtype field, which specifies
16009 a maximum number of bytes to skip when doing an
16010 alignment. */
98aa84af 16011 for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next)
252b5132
RH
16012 {
16013 if (f->fr_type == rs_align || f->fr_type == rs_align_code)
16014 {
16015 if (stretch < 0)
16016 stretch = - ((- stretch)
16017 & ~ ((1 << (int) f->fr_offset) - 1));
16018 else
16019 stretch &= ~ ((1 << (int) f->fr_offset) - 1);
16020 if (stretch == 0)
16021 break;
16022 }
16023 }
16024 if (f != NULL)
16025 val += stretch;
16026 }
16027
16028 addr = fragp->fr_address + fragp->fr_fix;
16029
16030 /* The base address rules are complicated. The base address of
16031 a branch is the following instruction. The base address of a
16032 PC relative load or add is the instruction itself, but if it
16033 is in a delay slot (in which case it can not be extended) use
16034 the address of the instruction whose delay slot it is in. */
3ccad066 16035 if (pcrel_op->include_isa_bit)
252b5132
RH
16036 {
16037 addr += 2;
16038
16039 /* If we are currently assuming that this frag should be
16040 extended, then, the current address is two bytes
bdaaa2e1 16041 higher. */
252b5132
RH
16042 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
16043 addr += 2;
16044
16045 /* Ignore the low bit in the target, since it will be set
16046 for a text label. */
3ccad066 16047 val &= -2;
252b5132
RH
16048 }
16049 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
16050 addr -= 4;
16051 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
16052 addr -= 2;
16053
3ccad066 16054 val -= addr & -(1 << pcrel_op->align_log2);
252b5132
RH
16055
16056 /* If any of the shifted bits are set, we must use an extended
16057 opcode. If the address depends on the size of this
16058 instruction, this can lead to a loop, so we arrange to always
16059 use an extended opcode. We only check this when we are in
16060 the main relaxation loop, when SEC is NULL. */
3ccad066 16061 if ((val & ((1 << operand->shift) - 1)) != 0 && sec == NULL)
252b5132
RH
16062 {
16063 fragp->fr_subtype =
16064 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
16065 return 1;
16066 }
16067
16068 /* If we are about to mark a frag as extended because the value
3ccad066
RS
16069 is precisely the next value above maxtiny, then there is a
16070 chance of an infinite loop as in the following code:
252b5132
RH
16071 la $4,foo
16072 .skip 1020
16073 .align 2
16074 foo:
16075 In this case when the la is extended, foo is 0x3fc bytes
16076 away, so the la can be shrunk, but then foo is 0x400 away, so
16077 the la must be extended. To avoid this loop, we mark the
16078 frag as extended if it was small, and is about to become
3ccad066
RS
16079 extended with the next value above maxtiny. */
16080 maxtiny = mips_int_operand_max (operand);
16081 if (val == maxtiny + (1 << operand->shift)
252b5132
RH
16082 && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)
16083 && sec == NULL)
16084 {
16085 fragp->fr_subtype =
16086 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
16087 return 1;
16088 }
16089 }
16090 else if (symsec != absolute_section && sec != NULL)
16091 as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation"));
16092
3ccad066 16093 return !mips16_immed_in_range_p (operand, BFD_RELOC_UNUSED, val);
252b5132
RH
16094}
16095
4a6a3df4
AO
16096/* Compute the length of a branch sequence, and adjust the
16097 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
16098 worst-case length is computed, with UPDATE being used to indicate
16099 whether an unconditional (-1), branch-likely (+1) or regular (0)
16100 branch is to be computed. */
16101static int
17a2f251 16102relaxed_branch_length (fragS *fragp, asection *sec, int update)
4a6a3df4 16103{
b34976b6 16104 bfd_boolean toofar;
4a6a3df4
AO
16105 int length;
16106
16107 if (fragp
16108 && S_IS_DEFINED (fragp->fr_symbol)
16109 && sec == S_GET_SEGMENT (fragp->fr_symbol))
16110 {
16111 addressT addr;
16112 offsetT val;
16113
16114 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
16115
16116 addr = fragp->fr_address + fragp->fr_fix + 4;
16117
16118 val -= addr;
16119
16120 toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2);
16121 }
16122 else if (fragp)
16123 /* If the symbol is not defined or it's in a different segment,
16124 assume the user knows what's going on and emit a short
16125 branch. */
b34976b6 16126 toofar = FALSE;
4a6a3df4 16127 else
b34976b6 16128 toofar = TRUE;
4a6a3df4
AO
16129
16130 if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
16131 fragp->fr_subtype
66b3e8da
MR
16132 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp->fr_subtype),
16133 RELAX_BRANCH_UNCOND (fragp->fr_subtype),
4a6a3df4
AO
16134 RELAX_BRANCH_LIKELY (fragp->fr_subtype),
16135 RELAX_BRANCH_LINK (fragp->fr_subtype),
16136 toofar);
16137
16138 length = 4;
16139 if (toofar)
16140 {
16141 if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0))
16142 length += 8;
16143
16144 if (mips_pic != NO_PIC)
16145 {
16146 /* Additional space for PIC loading of target address. */
16147 length += 8;
16148 if (mips_opts.isa == ISA_MIPS1)
16149 /* Additional space for $at-stabilizing nop. */
16150 length += 4;
16151 }
16152
16153 /* If branch is conditional. */
16154 if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0))
16155 length += 8;
16156 }
b34976b6 16157
4a6a3df4
AO
16158 return length;
16159}
16160
df58fc94
RS
16161/* Compute the length of a branch sequence, and adjust the
16162 RELAX_MICROMIPS_TOOFAR32 bit accordingly. If FRAGP is NULL, the
16163 worst-case length is computed, with UPDATE being used to indicate
16164 whether an unconditional (-1), or regular (0) branch is to be
16165 computed. */
16166
16167static int
16168relaxed_micromips_32bit_branch_length (fragS *fragp, asection *sec, int update)
16169{
16170 bfd_boolean toofar;
16171 int length;
16172
16173 if (fragp
16174 && S_IS_DEFINED (fragp->fr_symbol)
16175 && sec == S_GET_SEGMENT (fragp->fr_symbol))
16176 {
16177 addressT addr;
16178 offsetT val;
16179
16180 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
16181 /* Ignore the low bit in the target, since it will be set
16182 for a text label. */
16183 if ((val & 1) != 0)
16184 --val;
16185
16186 addr = fragp->fr_address + fragp->fr_fix + 4;
16187
16188 val -= addr;
16189
16190 toofar = val < - (0x8000 << 1) || val >= (0x8000 << 1);
16191 }
16192 else if (fragp)
16193 /* If the symbol is not defined or it's in a different segment,
16194 assume the user knows what's going on and emit a short
16195 branch. */
16196 toofar = FALSE;
16197 else
16198 toofar = TRUE;
16199
16200 if (fragp && update
16201 && toofar != RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype))
16202 fragp->fr_subtype = (toofar
16203 ? RELAX_MICROMIPS_MARK_TOOFAR32 (fragp->fr_subtype)
16204 : RELAX_MICROMIPS_CLEAR_TOOFAR32 (fragp->fr_subtype));
16205
16206 length = 4;
16207 if (toofar)
16208 {
16209 bfd_boolean compact_known = fragp != NULL;
16210 bfd_boolean compact = FALSE;
16211 bfd_boolean uncond;
16212
16213 if (compact_known)
16214 compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype);
16215 if (fragp)
16216 uncond = RELAX_MICROMIPS_UNCOND (fragp->fr_subtype);
16217 else
16218 uncond = update < 0;
16219
16220 /* If label is out of range, we turn branch <br>:
16221
16222 <br> label # 4 bytes
16223 0:
16224
16225 into:
16226
16227 j label # 4 bytes
16228 nop # 2 bytes if compact && !PIC
16229 0:
16230 */
16231 if (mips_pic == NO_PIC && (!compact_known || compact))
16232 length += 2;
16233
16234 /* If assembling PIC code, we further turn:
16235
16236 j label # 4 bytes
16237
16238 into:
16239
16240 lw/ld at, %got(label)(gp) # 4 bytes
16241 d/addiu at, %lo(label) # 4 bytes
16242 jr/c at # 2 bytes
16243 */
16244 if (mips_pic != NO_PIC)
16245 length += 6;
16246
16247 /* If branch <br> is conditional, we prepend negated branch <brneg>:
16248
16249 <brneg> 0f # 4 bytes
16250 nop # 2 bytes if !compact
16251 */
16252 if (!uncond)
16253 length += (compact_known && compact) ? 4 : 6;
16254 }
16255
16256 return length;
16257}
16258
16259/* Compute the length of a branch, and adjust the RELAX_MICROMIPS_TOOFAR16
16260 bit accordingly. */
16261
16262static int
16263relaxed_micromips_16bit_branch_length (fragS *fragp, asection *sec, int update)
16264{
16265 bfd_boolean toofar;
16266
df58fc94
RS
16267 if (fragp
16268 && S_IS_DEFINED (fragp->fr_symbol)
16269 && sec == S_GET_SEGMENT (fragp->fr_symbol))
16270 {
16271 addressT addr;
16272 offsetT val;
16273 int type;
16274
16275 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
16276 /* Ignore the low bit in the target, since it will be set
16277 for a text label. */
16278 if ((val & 1) != 0)
16279 --val;
16280
16281 /* Assume this is a 2-byte branch. */
16282 addr = fragp->fr_address + fragp->fr_fix + 2;
16283
16284 /* We try to avoid the infinite loop by not adding 2 more bytes for
16285 long branches. */
16286
16287 val -= addr;
16288
16289 type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype);
16290 if (type == 'D')
16291 toofar = val < - (0x200 << 1) || val >= (0x200 << 1);
16292 else if (type == 'E')
16293 toofar = val < - (0x40 << 1) || val >= (0x40 << 1);
16294 else
16295 abort ();
16296 }
16297 else
16298 /* If the symbol is not defined or it's in a different segment,
16299 we emit a normal 32-bit branch. */
16300 toofar = TRUE;
16301
16302 if (fragp && update
16303 && toofar != RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype))
16304 fragp->fr_subtype
16305 = toofar ? RELAX_MICROMIPS_MARK_TOOFAR16 (fragp->fr_subtype)
16306 : RELAX_MICROMIPS_CLEAR_TOOFAR16 (fragp->fr_subtype);
16307
16308 if (toofar)
16309 return 4;
16310
16311 return 2;
16312}
16313
252b5132
RH
16314/* Estimate the size of a frag before relaxing. Unless this is the
16315 mips16, we are not really relaxing here, and the final size is
16316 encoded in the subtype information. For the mips16, we have to
16317 decide whether we are using an extended opcode or not. */
16318
252b5132 16319int
17a2f251 16320md_estimate_size_before_relax (fragS *fragp, asection *segtype)
252b5132 16321{
5919d012 16322 int change;
252b5132 16323
4a6a3df4
AO
16324 if (RELAX_BRANCH_P (fragp->fr_subtype))
16325 {
16326
b34976b6
AM
16327 fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE);
16328
4a6a3df4
AO
16329 return fragp->fr_var;
16330 }
16331
252b5132 16332 if (RELAX_MIPS16_P (fragp->fr_subtype))
177b4a6a
AO
16333 /* We don't want to modify the EXTENDED bit here; it might get us
16334 into infinite loops. We change it only in mips_relax_frag(). */
16335 return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2);
252b5132 16336
df58fc94
RS
16337 if (RELAX_MICROMIPS_P (fragp->fr_subtype))
16338 {
16339 int length = 4;
16340
16341 if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0)
16342 length = relaxed_micromips_16bit_branch_length (fragp, segtype, FALSE);
16343 if (length == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype))
16344 length = relaxed_micromips_32bit_branch_length (fragp, segtype, FALSE);
16345 fragp->fr_var = length;
16346
16347 return length;
16348 }
16349
252b5132 16350 if (mips_pic == NO_PIC)
5919d012 16351 change = nopic_need_relax (fragp->fr_symbol, 0);
252b5132 16352 else if (mips_pic == SVR4_PIC)
5919d012 16353 change = pic_need_relax (fragp->fr_symbol, segtype);
0a44bf69
RS
16354 else if (mips_pic == VXWORKS_PIC)
16355 /* For vxworks, GOT16 relocations never have a corresponding LO16. */
16356 change = 0;
252b5132
RH
16357 else
16358 abort ();
16359
16360 if (change)
16361 {
4d7206a2 16362 fragp->fr_subtype |= RELAX_USE_SECOND;
4d7206a2 16363 return -RELAX_FIRST (fragp->fr_subtype);
252b5132 16364 }
4d7206a2
RS
16365 else
16366 return -RELAX_SECOND (fragp->fr_subtype);
252b5132
RH
16367}
16368
16369/* This is called to see whether a reloc against a defined symbol
de7e6852 16370 should be converted into a reloc against a section. */
252b5132
RH
16371
16372int
17a2f251 16373mips_fix_adjustable (fixS *fixp)
252b5132 16374{
252b5132
RH
16375 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
16376 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
16377 return 0;
a161fe53 16378
252b5132
RH
16379 if (fixp->fx_addsy == NULL)
16380 return 1;
a161fe53 16381
de7e6852
RS
16382 /* If symbol SYM is in a mergeable section, relocations of the form
16383 SYM + 0 can usually be made section-relative. The mergeable data
16384 is then identified by the section offset rather than by the symbol.
16385
16386 However, if we're generating REL LO16 relocations, the offset is split
16387 between the LO16 and parterning high part relocation. The linker will
16388 need to recalculate the complete offset in order to correctly identify
16389 the merge data.
16390
16391 The linker has traditionally not looked for the parterning high part
16392 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
16393 placed anywhere. Rather than break backwards compatibility by changing
16394 this, it seems better not to force the issue, and instead keep the
16395 original symbol. This will work with either linker behavior. */
738e5348 16396 if ((lo16_reloc_p (fixp->fx_r_type)
704803a9 16397 || reloc_needs_lo_p (fixp->fx_r_type))
de7e6852
RS
16398 && HAVE_IN_PLACE_ADDENDS
16399 && (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_MERGE) != 0)
16400 return 0;
16401
ce70d90a 16402 /* There is no place to store an in-place offset for JALR relocations.
2de39019
CM
16403 Likewise an in-range offset of limited PC-relative relocations may
16404 overflow the in-place relocatable field if recalculated against the
16405 start address of the symbol's containing section. */
ce70d90a 16406 if (HAVE_IN_PLACE_ADDENDS
2de39019
CM
16407 && (limited_pcrel_reloc_p (fixp->fx_r_type)
16408 || jalr_reloc_p (fixp->fx_r_type)))
1180b5a4
RS
16409 return 0;
16410
b314ec0e
RS
16411 /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve
16412 to a floating-point stub. The same is true for non-R_MIPS16_26
16413 relocations against MIPS16 functions; in this case, the stub becomes
16414 the function's canonical address.
16415
16416 Floating-point stubs are stored in unique .mips16.call.* or
16417 .mips16.fn.* sections. If a stub T for function F is in section S,
16418 the first relocation in section S must be against F; this is how the
16419 linker determines the target function. All relocations that might
16420 resolve to T must also be against F. We therefore have the following
16421 restrictions, which are given in an intentionally-redundant way:
16422
16423 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16
16424 symbols.
16425
16426 2. We cannot reduce a stub's relocations against non-MIPS16 symbols
16427 if that stub might be used.
16428
16429 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16
16430 symbols.
16431
16432 4. We cannot reduce a stub's relocations against MIPS16 symbols if
16433 that stub might be used.
16434
16435 There is a further restriction:
16436
df58fc94
RS
16437 5. We cannot reduce jump relocations (R_MIPS_26, R_MIPS16_26 or
16438 R_MICROMIPS_26_S1) against MIPS16 or microMIPS symbols on
16439 targets with in-place addends; the relocation field cannot
b314ec0e
RS
16440 encode the low bit.
16441
df58fc94
RS
16442 For simplicity, we deal with (3)-(4) by not reducing _any_ relocation
16443 against a MIPS16 symbol. We deal with (5) by by not reducing any
16444 such relocations on REL targets.
b314ec0e
RS
16445
16446 We deal with (1)-(2) by saying that, if there's a R_MIPS16_26
16447 relocation against some symbol R, no relocation against R may be
16448 reduced. (Note that this deals with (2) as well as (1) because
16449 relocations against global symbols will never be reduced on ELF
16450 targets.) This approach is a little simpler than trying to detect
16451 stub sections, and gives the "all or nothing" per-symbol consistency
16452 that we have for MIPS16 symbols. */
f3ded42a 16453 if (fixp->fx_subsy == NULL
30c09090 16454 && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp->fx_addsy))
df58fc94
RS
16455 || *symbol_get_tc (fixp->fx_addsy)
16456 || (HAVE_IN_PLACE_ADDENDS
16457 && ELF_ST_IS_MICROMIPS (S_GET_OTHER (fixp->fx_addsy))
16458 && jmp_reloc_p (fixp->fx_r_type))))
252b5132 16459 return 0;
a161fe53 16460
252b5132
RH
16461 return 1;
16462}
16463
16464/* Translate internal representation of relocation info to BFD target
16465 format. */
16466
16467arelent **
17a2f251 16468tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
252b5132
RH
16469{
16470 static arelent *retval[4];
16471 arelent *reloc;
16472 bfd_reloc_code_real_type code;
16473
4b0cff4e
TS
16474 memset (retval, 0, sizeof(retval));
16475 reloc = retval[0] = (arelent *) xcalloc (1, sizeof (arelent));
49309057
ILT
16476 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
16477 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH
16478 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
16479
bad36eac
DJ
16480 if (fixp->fx_pcrel)
16481 {
df58fc94
RS
16482 gas_assert (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2
16483 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1
16484 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1
b47468a6
CM
16485 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1
16486 || fixp->fx_r_type == BFD_RELOC_32_PCREL);
bad36eac
DJ
16487
16488 /* At this point, fx_addnumber is "symbol offset - pcrel address".
16489 Relocations want only the symbol offset. */
16490 reloc->addend = fixp->fx_addnumber + reloc->address;
bad36eac
DJ
16491 }
16492 else
16493 reloc->addend = fixp->fx_addnumber;
252b5132 16494
438c16b8
TS
16495 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
16496 entry to be used in the relocation's section offset. */
16497 if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
252b5132
RH
16498 {
16499 reloc->address = reloc->addend;
16500 reloc->addend = 0;
16501 }
16502
252b5132 16503 code = fixp->fx_r_type;
252b5132 16504
bad36eac 16505 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
252b5132
RH
16506 if (reloc->howto == NULL)
16507 {
16508 as_bad_where (fixp->fx_file, fixp->fx_line,
1661c76c
RS
16509 _("cannot represent %s relocation in this object file"
16510 " format"),
252b5132
RH
16511 bfd_get_reloc_code_name (code));
16512 retval[0] = NULL;
16513 }
16514
16515 return retval;
16516}
16517
16518/* Relax a machine dependent frag. This returns the amount by which
16519 the current size of the frag should change. */
16520
16521int
17a2f251 16522mips_relax_frag (asection *sec, fragS *fragp, long stretch)
252b5132 16523{
4a6a3df4
AO
16524 if (RELAX_BRANCH_P (fragp->fr_subtype))
16525 {
16526 offsetT old_var = fragp->fr_var;
b34976b6
AM
16527
16528 fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE);
4a6a3df4
AO
16529
16530 return fragp->fr_var - old_var;
16531 }
16532
df58fc94
RS
16533 if (RELAX_MICROMIPS_P (fragp->fr_subtype))
16534 {
16535 offsetT old_var = fragp->fr_var;
16536 offsetT new_var = 4;
16537
16538 if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0)
16539 new_var = relaxed_micromips_16bit_branch_length (fragp, sec, TRUE);
16540 if (new_var == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype))
16541 new_var = relaxed_micromips_32bit_branch_length (fragp, sec, TRUE);
16542 fragp->fr_var = new_var;
16543
16544 return new_var - old_var;
16545 }
16546
252b5132
RH
16547 if (! RELAX_MIPS16_P (fragp->fr_subtype))
16548 return 0;
16549
c4e7957c 16550 if (mips16_extended_frag (fragp, NULL, stretch))
252b5132
RH
16551 {
16552 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
16553 return 0;
16554 fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype);
16555 return 2;
16556 }
16557 else
16558 {
16559 if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
16560 return 0;
16561 fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype);
16562 return -2;
16563 }
16564
16565 return 0;
16566}
16567
16568/* Convert a machine dependent frag. */
16569
16570void
17a2f251 16571md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp)
252b5132 16572{
4a6a3df4
AO
16573 if (RELAX_BRANCH_P (fragp->fr_subtype))
16574 {
4d68580a 16575 char *buf;
4a6a3df4
AO
16576 unsigned long insn;
16577 expressionS exp;
16578 fixS *fixp;
b34976b6 16579
4d68580a
RS
16580 buf = fragp->fr_literal + fragp->fr_fix;
16581 insn = read_insn (buf);
b34976b6 16582
4a6a3df4
AO
16583 if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
16584 {
16585 /* We generate a fixup instead of applying it right now
16586 because, if there are linker relaxations, we're going to
16587 need the relocations. */
16588 exp.X_op = O_symbol;
16589 exp.X_add_symbol = fragp->fr_symbol;
16590 exp.X_add_number = fragp->fr_offset;
16591
4d68580a
RS
16592 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, TRUE,
16593 BFD_RELOC_16_PCREL_S2);
4a6a3df4
AO
16594 fixp->fx_file = fragp->fr_file;
16595 fixp->fx_line = fragp->fr_line;
b34976b6 16596
4d68580a 16597 buf = write_insn (buf, insn);
4a6a3df4
AO
16598 }
16599 else
16600 {
16601 int i;
16602
16603 as_warn_where (fragp->fr_file, fragp->fr_line,
1661c76c 16604 _("relaxed out-of-range branch into a jump"));
4a6a3df4
AO
16605
16606 if (RELAX_BRANCH_UNCOND (fragp->fr_subtype))
16607 goto uncond;
16608
16609 if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype))
16610 {
16611 /* Reverse the branch. */
16612 switch ((insn >> 28) & 0xf)
16613 {
16614 case 4:
56d438b1
CF
16615 if ((insn & 0xff000000) == 0x47000000
16616 || (insn & 0xff600000) == 0x45600000)
16617 {
16618 /* BZ.df/BNZ.df, BZ.V/BNZ.V can have the condition
16619 reversed by tweaking bit 23. */
16620 insn ^= 0x00800000;
16621 }
16622 else
16623 {
16624 /* bc[0-3][tf]l? instructions can have the condition
16625 reversed by tweaking a single TF bit, and their
16626 opcodes all have 0x4???????. */
16627 gas_assert ((insn & 0xf3e00000) == 0x41000000);
16628 insn ^= 0x00010000;
16629 }
4a6a3df4
AO
16630 break;
16631
16632 case 0:
16633 /* bltz 0x04000000 bgez 0x04010000
54f4ddb3 16634 bltzal 0x04100000 bgezal 0x04110000 */
9c2799c2 16635 gas_assert ((insn & 0xfc0e0000) == 0x04000000);
4a6a3df4
AO
16636 insn ^= 0x00010000;
16637 break;
b34976b6 16638
4a6a3df4
AO
16639 case 1:
16640 /* beq 0x10000000 bne 0x14000000
54f4ddb3 16641 blez 0x18000000 bgtz 0x1c000000 */
4a6a3df4
AO
16642 insn ^= 0x04000000;
16643 break;
16644
16645 default:
16646 abort ();
16647 }
16648 }
16649
16650 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
16651 {
16652 /* Clear the and-link bit. */
9c2799c2 16653 gas_assert ((insn & 0xfc1c0000) == 0x04100000);
4a6a3df4 16654
54f4ddb3
TS
16655 /* bltzal 0x04100000 bgezal 0x04110000
16656 bltzall 0x04120000 bgezall 0x04130000 */
4a6a3df4
AO
16657 insn &= ~0x00100000;
16658 }
16659
16660 /* Branch over the branch (if the branch was likely) or the
16661 full jump (not likely case). Compute the offset from the
16662 current instruction to branch to. */
16663 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
16664 i = 16;
16665 else
16666 {
16667 /* How many bytes in instructions we've already emitted? */
4d68580a 16668 i = buf - fragp->fr_literal - fragp->fr_fix;
4a6a3df4
AO
16669 /* How many bytes in instructions from here to the end? */
16670 i = fragp->fr_var - i;
16671 }
16672 /* Convert to instruction count. */
16673 i >>= 2;
16674 /* Branch counts from the next instruction. */
b34976b6 16675 i--;
4a6a3df4
AO
16676 insn |= i;
16677 /* Branch over the jump. */
4d68580a 16678 buf = write_insn (buf, insn);
4a6a3df4 16679
54f4ddb3 16680 /* nop */
4d68580a 16681 buf = write_insn (buf, 0);
4a6a3df4
AO
16682
16683 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
16684 {
16685 /* beql $0, $0, 2f */
16686 insn = 0x50000000;
16687 /* Compute the PC offset from the current instruction to
16688 the end of the variable frag. */
16689 /* How many bytes in instructions we've already emitted? */
4d68580a 16690 i = buf - fragp->fr_literal - fragp->fr_fix;
4a6a3df4
AO
16691 /* How many bytes in instructions from here to the end? */
16692 i = fragp->fr_var - i;
16693 /* Convert to instruction count. */
16694 i >>= 2;
16695 /* Don't decrement i, because we want to branch over the
16696 delay slot. */
4a6a3df4 16697 insn |= i;
4a6a3df4 16698
4d68580a
RS
16699 buf = write_insn (buf, insn);
16700 buf = write_insn (buf, 0);
4a6a3df4
AO
16701 }
16702
16703 uncond:
16704 if (mips_pic == NO_PIC)
16705 {
16706 /* j or jal. */
16707 insn = (RELAX_BRANCH_LINK (fragp->fr_subtype)
16708 ? 0x0c000000 : 0x08000000);
16709 exp.X_op = O_symbol;
16710 exp.X_add_symbol = fragp->fr_symbol;
16711 exp.X_add_number = fragp->fr_offset;
16712
4d68580a
RS
16713 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp,
16714 FALSE, BFD_RELOC_MIPS_JMP);
4a6a3df4
AO
16715 fixp->fx_file = fragp->fr_file;
16716 fixp->fx_line = fragp->fr_line;
16717
4d68580a 16718 buf = write_insn (buf, insn);
4a6a3df4
AO
16719 }
16720 else
16721 {
66b3e8da
MR
16722 unsigned long at = RELAX_BRANCH_AT (fragp->fr_subtype);
16723
4a6a3df4 16724 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
66b3e8da
MR
16725 insn = HAVE_64BIT_ADDRESSES ? 0xdf800000 : 0x8f800000;
16726 insn |= at << OP_SH_RT;
4a6a3df4
AO
16727 exp.X_op = O_symbol;
16728 exp.X_add_symbol = fragp->fr_symbol;
16729 exp.X_add_number = fragp->fr_offset;
16730
16731 if (fragp->fr_offset)
16732 {
16733 exp.X_add_symbol = make_expr_symbol (&exp);
16734 exp.X_add_number = 0;
16735 }
16736
4d68580a
RS
16737 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp,
16738 FALSE, BFD_RELOC_MIPS_GOT16);
4a6a3df4
AO
16739 fixp->fx_file = fragp->fr_file;
16740 fixp->fx_line = fragp->fr_line;
16741
4d68580a 16742 buf = write_insn (buf, insn);
b34976b6 16743
4a6a3df4 16744 if (mips_opts.isa == ISA_MIPS1)
4d68580a
RS
16745 /* nop */
16746 buf = write_insn (buf, 0);
4a6a3df4
AO
16747
16748 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
66b3e8da
MR
16749 insn = HAVE_64BIT_ADDRESSES ? 0x64000000 : 0x24000000;
16750 insn |= at << OP_SH_RS | at << OP_SH_RT;
4a6a3df4 16751
4d68580a
RS
16752 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp,
16753 FALSE, BFD_RELOC_LO16);
4a6a3df4
AO
16754 fixp->fx_file = fragp->fr_file;
16755 fixp->fx_line = fragp->fr_line;
b34976b6 16756
4d68580a 16757 buf = write_insn (buf, insn);
4a6a3df4
AO
16758
16759 /* j(al)r $at. */
16760 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
66b3e8da 16761 insn = 0x0000f809;
4a6a3df4 16762 else
66b3e8da
MR
16763 insn = 0x00000008;
16764 insn |= at << OP_SH_RS;
4a6a3df4 16765
4d68580a 16766 buf = write_insn (buf, insn);
4a6a3df4
AO
16767 }
16768 }
16769
4a6a3df4 16770 fragp->fr_fix += fragp->fr_var;
4d68580a 16771 gas_assert (buf == fragp->fr_literal + fragp->fr_fix);
4a6a3df4
AO
16772 return;
16773 }
16774
df58fc94
RS
16775 /* Relax microMIPS branches. */
16776 if (RELAX_MICROMIPS_P (fragp->fr_subtype))
16777 {
4d68580a 16778 char *buf = fragp->fr_literal + fragp->fr_fix;
df58fc94
RS
16779 bfd_boolean compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype);
16780 bfd_boolean al = RELAX_MICROMIPS_LINK (fragp->fr_subtype);
16781 int type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype);
2309ddf2 16782 bfd_boolean short_ds;
df58fc94
RS
16783 unsigned long insn;
16784 expressionS exp;
16785 fixS *fixp;
16786
16787 exp.X_op = O_symbol;
16788 exp.X_add_symbol = fragp->fr_symbol;
16789 exp.X_add_number = fragp->fr_offset;
16790
16791 fragp->fr_fix += fragp->fr_var;
16792
16793 /* Handle 16-bit branches that fit or are forced to fit. */
16794 if (type != 0 && !RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype))
16795 {
16796 /* We generate a fixup instead of applying it right now,
16797 because if there is linker relaxation, we're going to
16798 need the relocations. */
16799 if (type == 'D')
4d68580a 16800 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 2, &exp, TRUE,
df58fc94
RS
16801 BFD_RELOC_MICROMIPS_10_PCREL_S1);
16802 else if (type == 'E')
4d68580a 16803 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 2, &exp, TRUE,
df58fc94
RS
16804 BFD_RELOC_MICROMIPS_7_PCREL_S1);
16805 else
16806 abort ();
16807
16808 fixp->fx_file = fragp->fr_file;
16809 fixp->fx_line = fragp->fr_line;
16810
16811 /* These relocations can have an addend that won't fit in
16812 2 octets. */
16813 fixp->fx_no_overflow = 1;
16814
16815 return;
16816 }
16817
2309ddf2 16818 /* Handle 32-bit branches that fit or are forced to fit. */
df58fc94
RS
16819 if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)
16820 || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype))
16821 {
16822 /* We generate a fixup instead of applying it right now,
16823 because if there is linker relaxation, we're going to
16824 need the relocations. */
4d68580a
RS
16825 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, TRUE,
16826 BFD_RELOC_MICROMIPS_16_PCREL_S1);
df58fc94
RS
16827 fixp->fx_file = fragp->fr_file;
16828 fixp->fx_line = fragp->fr_line;
16829
16830 if (type == 0)
16831 return;
16832 }
16833
16834 /* Relax 16-bit branches to 32-bit branches. */
16835 if (type != 0)
16836 {
4d68580a 16837 insn = read_compressed_insn (buf, 2);
df58fc94
RS
16838
16839 if ((insn & 0xfc00) == 0xcc00) /* b16 */
16840 insn = 0x94000000; /* beq */
16841 else if ((insn & 0xdc00) == 0x8c00) /* beqz16/bnez16 */
16842 {
16843 unsigned long regno;
16844
16845 regno = (insn >> MICROMIPSOP_SH_MD) & MICROMIPSOP_MASK_MD;
16846 regno = micromips_to_32_reg_d_map [regno];
16847 insn = ((insn & 0x2000) << 16) | 0x94000000; /* beq/bne */
16848 insn |= regno << MICROMIPSOP_SH_RS;
16849 }
16850 else
16851 abort ();
16852
16853 /* Nothing else to do, just write it out. */
16854 if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)
16855 || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype))
16856 {
4d68580a
RS
16857 buf = write_compressed_insn (buf, insn, 4);
16858 gas_assert (buf == fragp->fr_literal + fragp->fr_fix);
df58fc94
RS
16859 return;
16860 }
16861 }
16862 else
4d68580a 16863 insn = read_compressed_insn (buf, 4);
df58fc94
RS
16864
16865 /* Relax 32-bit branches to a sequence of instructions. */
16866 as_warn_where (fragp->fr_file, fragp->fr_line,
1661c76c 16867 _("relaxed out-of-range branch into a jump"));
df58fc94 16868
2309ddf2
MR
16869 /* Set the short-delay-slot bit. */
16870 short_ds = al && (insn & 0x02000000) != 0;
df58fc94
RS
16871
16872 if (!RELAX_MICROMIPS_UNCOND (fragp->fr_subtype))
16873 {
16874 symbolS *l;
16875
16876 /* Reverse the branch. */
16877 if ((insn & 0xfc000000) == 0x94000000 /* beq */
16878 || (insn & 0xfc000000) == 0xb4000000) /* bne */
16879 insn ^= 0x20000000;
16880 else if ((insn & 0xffe00000) == 0x40000000 /* bltz */
16881 || (insn & 0xffe00000) == 0x40400000 /* bgez */
16882 || (insn & 0xffe00000) == 0x40800000 /* blez */
16883 || (insn & 0xffe00000) == 0x40c00000 /* bgtz */
16884 || (insn & 0xffe00000) == 0x40a00000 /* bnezc */
16885 || (insn & 0xffe00000) == 0x40e00000 /* beqzc */
16886 || (insn & 0xffe00000) == 0x40200000 /* bltzal */
16887 || (insn & 0xffe00000) == 0x40600000 /* bgezal */
16888 || (insn & 0xffe00000) == 0x42200000 /* bltzals */
16889 || (insn & 0xffe00000) == 0x42600000) /* bgezals */
16890 insn ^= 0x00400000;
16891 else if ((insn & 0xffe30000) == 0x43800000 /* bc1f */
16892 || (insn & 0xffe30000) == 0x43a00000 /* bc1t */
16893 || (insn & 0xffe30000) == 0x42800000 /* bc2f */
16894 || (insn & 0xffe30000) == 0x42a00000) /* bc2t */
16895 insn ^= 0x00200000;
56d438b1
CF
16896 else if ((insn & 0xff000000) == 0x83000000 /* BZ.df
16897 BNZ.df */
16898 || (insn & 0xff600000) == 0x81600000) /* BZ.V
16899 BNZ.V */
16900 insn ^= 0x00800000;
df58fc94
RS
16901 else
16902 abort ();
16903
16904 if (al)
16905 {
16906 /* Clear the and-link and short-delay-slot bits. */
16907 gas_assert ((insn & 0xfda00000) == 0x40200000);
16908
16909 /* bltzal 0x40200000 bgezal 0x40600000 */
16910 /* bltzals 0x42200000 bgezals 0x42600000 */
16911 insn &= ~0x02200000;
16912 }
16913
16914 /* Make a label at the end for use with the branch. */
16915 l = symbol_new (micromips_label_name (), asec, fragp->fr_fix, fragp);
16916 micromips_label_inc ();
f3ded42a 16917 S_SET_OTHER (l, ELF_ST_SET_MICROMIPS (S_GET_OTHER (l)));
df58fc94
RS
16918
16919 /* Refer to it. */
4d68580a
RS
16920 fixp = fix_new (fragp, buf - fragp->fr_literal, 4, l, 0, TRUE,
16921 BFD_RELOC_MICROMIPS_16_PCREL_S1);
df58fc94
RS
16922 fixp->fx_file = fragp->fr_file;
16923 fixp->fx_line = fragp->fr_line;
16924
16925 /* Branch over the jump. */
4d68580a 16926 buf = write_compressed_insn (buf, insn, 4);
df58fc94 16927 if (!compact)
4d68580a
RS
16928 /* nop */
16929 buf = write_compressed_insn (buf, 0x0c00, 2);
df58fc94
RS
16930 }
16931
16932 if (mips_pic == NO_PIC)
16933 {
2309ddf2
MR
16934 unsigned long jal = short_ds ? 0x74000000 : 0xf4000000; /* jal/s */
16935
df58fc94
RS
16936 /* j/jal/jals <sym> R_MICROMIPS_26_S1 */
16937 insn = al ? jal : 0xd4000000;
16938
4d68580a
RS
16939 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE,
16940 BFD_RELOC_MICROMIPS_JMP);
df58fc94
RS
16941 fixp->fx_file = fragp->fr_file;
16942 fixp->fx_line = fragp->fr_line;
16943
4d68580a 16944 buf = write_compressed_insn (buf, insn, 4);
df58fc94 16945 if (compact)
4d68580a
RS
16946 /* nop */
16947 buf = write_compressed_insn (buf, 0x0c00, 2);
df58fc94
RS
16948 }
16949 else
16950 {
16951 unsigned long at = RELAX_MICROMIPS_AT (fragp->fr_subtype);
2309ddf2
MR
16952 unsigned long jalr = short_ds ? 0x45e0 : 0x45c0; /* jalr/s */
16953 unsigned long jr = compact ? 0x45a0 : 0x4580; /* jr/c */
df58fc94
RS
16954
16955 /* lw/ld $at, <sym>($gp) R_MICROMIPS_GOT16 */
16956 insn = HAVE_64BIT_ADDRESSES ? 0xdc1c0000 : 0xfc1c0000;
16957 insn |= at << MICROMIPSOP_SH_RT;
16958
16959 if (exp.X_add_number)
16960 {
16961 exp.X_add_symbol = make_expr_symbol (&exp);
16962 exp.X_add_number = 0;
16963 }
16964
4d68580a
RS
16965 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE,
16966 BFD_RELOC_MICROMIPS_GOT16);
df58fc94
RS
16967 fixp->fx_file = fragp->fr_file;
16968 fixp->fx_line = fragp->fr_line;
16969
4d68580a 16970 buf = write_compressed_insn (buf, insn, 4);
df58fc94
RS
16971
16972 /* d/addiu $at, $at, <sym> R_MICROMIPS_LO16 */
16973 insn = HAVE_64BIT_ADDRESSES ? 0x5c000000 : 0x30000000;
16974 insn |= at << MICROMIPSOP_SH_RT | at << MICROMIPSOP_SH_RS;
16975
4d68580a
RS
16976 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE,
16977 BFD_RELOC_MICROMIPS_LO16);
df58fc94
RS
16978 fixp->fx_file = fragp->fr_file;
16979 fixp->fx_line = fragp->fr_line;
16980
4d68580a 16981 buf = write_compressed_insn (buf, insn, 4);
df58fc94
RS
16982
16983 /* jr/jrc/jalr/jalrs $at */
16984 insn = al ? jalr : jr;
16985 insn |= at << MICROMIPSOP_SH_MJ;
16986
4d68580a 16987 buf = write_compressed_insn (buf, insn, 2);
df58fc94
RS
16988 }
16989
4d68580a 16990 gas_assert (buf == fragp->fr_literal + fragp->fr_fix);
df58fc94
RS
16991 return;
16992 }
16993
252b5132
RH
16994 if (RELAX_MIPS16_P (fragp->fr_subtype))
16995 {
16996 int type;
3ccad066 16997 const struct mips_int_operand *operand;
252b5132 16998 offsetT val;
5c04167a
RS
16999 char *buf;
17000 unsigned int user_length, length;
252b5132 17001 unsigned long insn;
5c04167a 17002 bfd_boolean ext;
252b5132
RH
17003
17004 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
3ccad066 17005 operand = mips16_immed_operand (type, FALSE);
252b5132 17006
5c04167a 17007 ext = RELAX_MIPS16_EXTENDED (fragp->fr_subtype);
5f5f22c0 17008 val = resolve_symbol_value (fragp->fr_symbol);
3ccad066 17009 if (operand->root.type == OP_PCREL)
252b5132 17010 {
3ccad066 17011 const struct mips_pcrel_operand *pcrel_op;
252b5132
RH
17012 addressT addr;
17013
3ccad066 17014 pcrel_op = (const struct mips_pcrel_operand *) operand;
252b5132
RH
17015 addr = fragp->fr_address + fragp->fr_fix;
17016
17017 /* The rules for the base address of a PC relative reloc are
17018 complicated; see mips16_extended_frag. */
3ccad066 17019 if (pcrel_op->include_isa_bit)
252b5132
RH
17020 {
17021 addr += 2;
17022 if (ext)
17023 addr += 2;
17024 /* Ignore the low bit in the target, since it will be
17025 set for a text label. */
3ccad066 17026 val &= -2;
252b5132
RH
17027 }
17028 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
17029 addr -= 4;
17030 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
17031 addr -= 2;
17032
3ccad066 17033 addr &= -(1 << pcrel_op->align_log2);
252b5132
RH
17034 val -= addr;
17035
17036 /* Make sure the section winds up with the alignment we have
17037 assumed. */
3ccad066
RS
17038 if (operand->shift > 0)
17039 record_alignment (asec, operand->shift);
252b5132
RH
17040 }
17041
17042 if (ext
17043 && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)
17044 || RELAX_MIPS16_DSLOT (fragp->fr_subtype)))
17045 as_warn_where (fragp->fr_file, fragp->fr_line,
17046 _("extended instruction in delay slot"));
17047
5c04167a 17048 buf = fragp->fr_literal + fragp->fr_fix;
252b5132 17049
4d68580a 17050 insn = read_compressed_insn (buf, 2);
5c04167a
RS
17051 if (ext)
17052 insn |= MIPS16_EXTEND;
252b5132 17053
5c04167a
RS
17054 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype))
17055 user_length = 4;
17056 else if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype))
17057 user_length = 2;
17058 else
17059 user_length = 0;
17060
43c0598f 17061 mips16_immed (fragp->fr_file, fragp->fr_line, type,
c150d1d2 17062 BFD_RELOC_UNUSED, val, user_length, &insn);
252b5132 17063
5c04167a
RS
17064 length = (ext ? 4 : 2);
17065 gas_assert (mips16_opcode_length (insn) == length);
17066 write_compressed_insn (buf, insn, length);
17067 fragp->fr_fix += length;
252b5132
RH
17068 }
17069 else
17070 {
df58fc94
RS
17071 relax_substateT subtype = fragp->fr_subtype;
17072 bfd_boolean second_longer = (subtype & RELAX_SECOND_LONGER) != 0;
17073 bfd_boolean use_second = (subtype & RELAX_USE_SECOND) != 0;
4d7206a2
RS
17074 int first, second;
17075 fixS *fixp;
252b5132 17076
df58fc94
RS
17077 first = RELAX_FIRST (subtype);
17078 second = RELAX_SECOND (subtype);
4d7206a2 17079 fixp = (fixS *) fragp->fr_opcode;
252b5132 17080
df58fc94
RS
17081 /* If the delay slot chosen does not match the size of the instruction,
17082 then emit a warning. */
17083 if ((!use_second && (subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0)
17084 || (use_second && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0))
17085 {
17086 relax_substateT s;
17087 const char *msg;
17088
17089 s = subtype & (RELAX_DELAY_SLOT_16BIT
17090 | RELAX_DELAY_SLOT_SIZE_FIRST
17091 | RELAX_DELAY_SLOT_SIZE_SECOND);
17092 msg = macro_warning (s);
17093 if (msg != NULL)
db9b2be4 17094 as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg);
df58fc94
RS
17095 subtype &= ~s;
17096 }
17097
584892a6 17098 /* Possibly emit a warning if we've chosen the longer option. */
df58fc94 17099 if (use_second == second_longer)
584892a6 17100 {
df58fc94
RS
17101 relax_substateT s;
17102 const char *msg;
17103
17104 s = (subtype
17105 & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT));
17106 msg = macro_warning (s);
17107 if (msg != NULL)
db9b2be4 17108 as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg);
df58fc94 17109 subtype &= ~s;
584892a6
RS
17110 }
17111
4d7206a2
RS
17112 /* Go through all the fixups for the first sequence. Disable them
17113 (by marking them as done) if we're going to use the second
17114 sequence instead. */
17115 while (fixp
17116 && fixp->fx_frag == fragp
17117 && fixp->fx_where < fragp->fr_fix - second)
17118 {
df58fc94 17119 if (subtype & RELAX_USE_SECOND)
4d7206a2
RS
17120 fixp->fx_done = 1;
17121 fixp = fixp->fx_next;
17122 }
252b5132 17123
4d7206a2
RS
17124 /* Go through the fixups for the second sequence. Disable them if
17125 we're going to use the first sequence, otherwise adjust their
17126 addresses to account for the relaxation. */
17127 while (fixp && fixp->fx_frag == fragp)
17128 {
df58fc94 17129 if (subtype & RELAX_USE_SECOND)
4d7206a2
RS
17130 fixp->fx_where -= first;
17131 else
17132 fixp->fx_done = 1;
17133 fixp = fixp->fx_next;
17134 }
17135
17136 /* Now modify the frag contents. */
df58fc94 17137 if (subtype & RELAX_USE_SECOND)
4d7206a2
RS
17138 {
17139 char *start;
17140
17141 start = fragp->fr_literal + fragp->fr_fix - first - second;
17142 memmove (start, start + first, second);
17143 fragp->fr_fix -= first;
17144 }
17145 else
17146 fragp->fr_fix -= second;
252b5132
RH
17147 }
17148}
17149
252b5132
RH
17150/* This function is called after the relocs have been generated.
17151 We've been storing mips16 text labels as odd. Here we convert them
17152 back to even for the convenience of the debugger. */
17153
17154void
17a2f251 17155mips_frob_file_after_relocs (void)
252b5132
RH
17156{
17157 asymbol **syms;
17158 unsigned int count, i;
17159
252b5132
RH
17160 syms = bfd_get_outsymbols (stdoutput);
17161 count = bfd_get_symcount (stdoutput);
17162 for (i = 0; i < count; i++, syms++)
df58fc94
RS
17163 if (ELF_ST_IS_COMPRESSED (elf_symbol (*syms)->internal_elf_sym.st_other)
17164 && ((*syms)->value & 1) != 0)
17165 {
17166 (*syms)->value &= ~1;
17167 /* If the symbol has an odd size, it was probably computed
17168 incorrectly, so adjust that as well. */
17169 if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0)
17170 ++elf_symbol (*syms)->internal_elf_sym.st_size;
17171 }
252b5132
RH
17172}
17173
a1facbec
MR
17174/* This function is called whenever a label is defined, including fake
17175 labels instantiated off the dot special symbol. It is used when
17176 handling branch delays; if a branch has a label, we assume we cannot
17177 move it. This also bumps the value of the symbol by 1 in compressed
17178 code. */
252b5132 17179
e1b47bd5 17180static void
a1facbec 17181mips_record_label (symbolS *sym)
252b5132 17182{
a8dbcb85 17183 segment_info_type *si = seg_info (now_seg);
252b5132
RH
17184 struct insn_label_list *l;
17185
17186 if (free_insn_labels == NULL)
17187 l = (struct insn_label_list *) xmalloc (sizeof *l);
17188 else
17189 {
17190 l = free_insn_labels;
17191 free_insn_labels = l->next;
17192 }
17193
17194 l->label = sym;
a8dbcb85
TS
17195 l->next = si->label_list;
17196 si->label_list = l;
a1facbec 17197}
07a53e5c 17198
a1facbec
MR
17199/* This function is called as tc_frob_label() whenever a label is defined
17200 and adds a DWARF-2 record we only want for true labels. */
17201
17202void
17203mips_define_label (symbolS *sym)
17204{
17205 mips_record_label (sym);
07a53e5c 17206 dwarf2_emit_label (sym);
252b5132 17207}
e1b47bd5
RS
17208
17209/* This function is called by tc_new_dot_label whenever a new dot symbol
17210 is defined. */
17211
17212void
17213mips_add_dot_label (symbolS *sym)
17214{
17215 mips_record_label (sym);
17216 if (mips_assembling_insn && HAVE_CODE_COMPRESSION)
17217 mips_compressed_mark_label (sym);
17218}
252b5132 17219\f
252b5132
RH
17220/* Some special processing for a MIPS ELF file. */
17221
17222void
17a2f251 17223mips_elf_final_processing (void)
252b5132
RH
17224{
17225 /* Write out the register information. */
316f5878 17226 if (mips_abi != N64_ABI)
252b5132
RH
17227 {
17228 Elf32_RegInfo s;
17229
17230 s.ri_gprmask = mips_gprmask;
17231 s.ri_cprmask[0] = mips_cprmask[0];
17232 s.ri_cprmask[1] = mips_cprmask[1];
17233 s.ri_cprmask[2] = mips_cprmask[2];
17234 s.ri_cprmask[3] = mips_cprmask[3];
17235 /* The gp_value field is set by the MIPS ELF backend. */
17236
17237 bfd_mips_elf32_swap_reginfo_out (stdoutput, &s,
17238 ((Elf32_External_RegInfo *)
17239 mips_regmask_frag));
17240 }
17241 else
17242 {
17243 Elf64_Internal_RegInfo s;
17244
17245 s.ri_gprmask = mips_gprmask;
17246 s.ri_pad = 0;
17247 s.ri_cprmask[0] = mips_cprmask[0];
17248 s.ri_cprmask[1] = mips_cprmask[1];
17249 s.ri_cprmask[2] = mips_cprmask[2];
17250 s.ri_cprmask[3] = mips_cprmask[3];
17251 /* The gp_value field is set by the MIPS ELF backend. */
17252
17253 bfd_mips_elf64_swap_reginfo_out (stdoutput, &s,
17254 ((Elf64_External_RegInfo *)
17255 mips_regmask_frag));
17256 }
17257
17258 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
17259 sort of BFD interface for this. */
17260 if (mips_any_noreorder)
17261 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER;
17262 if (mips_pic != NO_PIC)
143d77c5 17263 {
8b828383 17264 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC;
143d77c5
EC
17265 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
17266 }
17267 if (mips_abicalls)
17268 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
252b5132 17269
b015e599
AP
17270 /* Set MIPS ELF flags for ASEs. Note that not all ASEs have flags
17271 defined at present; this might need to change in future. */
a4672219
TS
17272 if (file_ase_mips16)
17273 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16;
df58fc94
RS
17274 if (file_ase_micromips)
17275 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MICROMIPS;
846ef2d0 17276 if (file_ase & ASE_MDMX)
deec1734 17277 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX;
1f25f5d3 17278
bdaaa2e1 17279 /* Set the MIPS ELF ABI flags. */
316f5878 17280 if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32)
252b5132 17281 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32;
316f5878 17282 else if (mips_abi == O64_ABI)
252b5132 17283 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64;
316f5878 17284 else if (mips_abi == EABI_ABI)
252b5132 17285 {
316f5878 17286 if (!file_mips_gp32)
252b5132
RH
17287 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64;
17288 else
17289 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32;
17290 }
316f5878 17291 else if (mips_abi == N32_ABI)
be00bddd
TS
17292 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2;
17293
c9914766 17294 /* Nothing to do for N64_ABI. */
252b5132
RH
17295
17296 if (mips_32bitmode)
17297 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE;
ad3fea08 17298
ba92f887
MR
17299 if (mips_flag_nan2008)
17300 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NAN2008;
17301
ad3fea08
TS
17302 /* 32 bit code with 64 bit FP registers. */
17303 if (!file_mips_fp32 && ABI_NEEDS_32BIT_REGS (mips_abi))
f1c38003 17304 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_FP64;
252b5132 17305}
252b5132 17306\f
beae10d5 17307typedef struct proc {
9b2f1d35
EC
17308 symbolS *func_sym;
17309 symbolS *func_end_sym;
beae10d5
KH
17310 unsigned long reg_mask;
17311 unsigned long reg_offset;
17312 unsigned long fpreg_mask;
17313 unsigned long fpreg_offset;
17314 unsigned long frame_offset;
17315 unsigned long frame_reg;
17316 unsigned long pc_reg;
17317} procS;
252b5132
RH
17318
17319static procS cur_proc;
17320static procS *cur_proc_ptr;
17321static int numprocs;
17322
df58fc94
RS
17323/* Implement NOP_OPCODE. We encode a MIPS16 nop as "1", a microMIPS nop
17324 as "2", and a normal nop as "0". */
17325
17326#define NOP_OPCODE_MIPS 0
17327#define NOP_OPCODE_MIPS16 1
17328#define NOP_OPCODE_MICROMIPS 2
742a56fe
RS
17329
17330char
17331mips_nop_opcode (void)
17332{
df58fc94
RS
17333 if (seg_info (now_seg)->tc_segment_info_data.micromips)
17334 return NOP_OPCODE_MICROMIPS;
17335 else if (seg_info (now_seg)->tc_segment_info_data.mips16)
17336 return NOP_OPCODE_MIPS16;
17337 else
17338 return NOP_OPCODE_MIPS;
742a56fe
RS
17339}
17340
df58fc94
RS
17341/* Fill in an rs_align_code fragment. Unlike elsewhere we want to use
17342 32-bit microMIPS NOPs here (if applicable). */
a19d8eb0 17343
0a9ef439 17344void
17a2f251 17345mips_handle_align (fragS *fragp)
a19d8eb0 17346{
df58fc94 17347 char nop_opcode;
742a56fe 17348 char *p;
c67a084a
NC
17349 int bytes, size, excess;
17350 valueT opcode;
742a56fe 17351
0a9ef439
RH
17352 if (fragp->fr_type != rs_align_code)
17353 return;
17354
742a56fe 17355 p = fragp->fr_literal + fragp->fr_fix;
df58fc94
RS
17356 nop_opcode = *p;
17357 switch (nop_opcode)
a19d8eb0 17358 {
df58fc94
RS
17359 case NOP_OPCODE_MICROMIPS:
17360 opcode = micromips_nop32_insn.insn_opcode;
17361 size = 4;
17362 break;
17363 case NOP_OPCODE_MIPS16:
c67a084a
NC
17364 opcode = mips16_nop_insn.insn_opcode;
17365 size = 2;
df58fc94
RS
17366 break;
17367 case NOP_OPCODE_MIPS:
17368 default:
c67a084a
NC
17369 opcode = nop_insn.insn_opcode;
17370 size = 4;
df58fc94 17371 break;
c67a084a 17372 }
a19d8eb0 17373
c67a084a
NC
17374 bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
17375 excess = bytes % size;
df58fc94
RS
17376
17377 /* Handle the leading part if we're not inserting a whole number of
17378 instructions, and make it the end of the fixed part of the frag.
17379 Try to fit in a short microMIPS NOP if applicable and possible,
17380 and use zeroes otherwise. */
17381 gas_assert (excess < 4);
17382 fragp->fr_fix += excess;
17383 switch (excess)
c67a084a 17384 {
df58fc94
RS
17385 case 3:
17386 *p++ = '\0';
17387 /* Fall through. */
17388 case 2:
833794fc 17389 if (nop_opcode == NOP_OPCODE_MICROMIPS && !mips_opts.insn32)
df58fc94 17390 {
4d68580a 17391 p = write_compressed_insn (p, micromips_nop16_insn.insn_opcode, 2);
df58fc94
RS
17392 break;
17393 }
17394 *p++ = '\0';
17395 /* Fall through. */
17396 case 1:
17397 *p++ = '\0';
17398 /* Fall through. */
17399 case 0:
17400 break;
a19d8eb0 17401 }
c67a084a
NC
17402
17403 md_number_to_chars (p, opcode, size);
17404 fragp->fr_var = size;
a19d8eb0
CP
17405}
17406
252b5132 17407static void
17a2f251 17408md_obj_begin (void)
252b5132
RH
17409{
17410}
17411
17412static void
17a2f251 17413md_obj_end (void)
252b5132 17414{
54f4ddb3 17415 /* Check for premature end, nesting errors, etc. */
252b5132 17416 if (cur_proc_ptr)
9a41af64 17417 as_warn (_("missing .end at end of assembly"));
252b5132
RH
17418}
17419
17420static long
17a2f251 17421get_number (void)
252b5132
RH
17422{
17423 int negative = 0;
17424 long val = 0;
17425
17426 if (*input_line_pointer == '-')
17427 {
17428 ++input_line_pointer;
17429 negative = 1;
17430 }
3882b010 17431 if (!ISDIGIT (*input_line_pointer))
956cd1d6 17432 as_bad (_("expected simple number"));
252b5132
RH
17433 if (input_line_pointer[0] == '0')
17434 {
17435 if (input_line_pointer[1] == 'x')
17436 {
17437 input_line_pointer += 2;
3882b010 17438 while (ISXDIGIT (*input_line_pointer))
252b5132
RH
17439 {
17440 val <<= 4;
17441 val |= hex_value (*input_line_pointer++);
17442 }
17443 return negative ? -val : val;
17444 }
17445 else
17446 {
17447 ++input_line_pointer;
3882b010 17448 while (ISDIGIT (*input_line_pointer))
252b5132
RH
17449 {
17450 val <<= 3;
17451 val |= *input_line_pointer++ - '0';
17452 }
17453 return negative ? -val : val;
17454 }
17455 }
3882b010 17456 if (!ISDIGIT (*input_line_pointer))
252b5132
RH
17457 {
17458 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
17459 *input_line_pointer, *input_line_pointer);
956cd1d6 17460 as_warn (_("invalid number"));
252b5132
RH
17461 return -1;
17462 }
3882b010 17463 while (ISDIGIT (*input_line_pointer))
252b5132
RH
17464 {
17465 val *= 10;
17466 val += *input_line_pointer++ - '0';
17467 }
17468 return negative ? -val : val;
17469}
17470
17471/* The .file directive; just like the usual .file directive, but there
c5dd6aab
DJ
17472 is an initial number which is the ECOFF file index. In the non-ECOFF
17473 case .file implies DWARF-2. */
17474
17475static void
17a2f251 17476s_mips_file (int x ATTRIBUTE_UNUSED)
c5dd6aab 17477{
ecb4347a
DJ
17478 static int first_file_directive = 0;
17479
c5dd6aab
DJ
17480 if (ECOFF_DEBUGGING)
17481 {
17482 get_number ();
17483 s_app_file (0);
17484 }
17485 else
ecb4347a
DJ
17486 {
17487 char *filename;
17488
17489 filename = dwarf2_directive_file (0);
17490
17491 /* Versions of GCC up to 3.1 start files with a ".file"
17492 directive even for stabs output. Make sure that this
17493 ".file" is handled. Note that you need a version of GCC
17494 after 3.1 in order to support DWARF-2 on MIPS. */
17495 if (filename != NULL && ! first_file_directive)
17496 {
17497 (void) new_logical_line (filename, -1);
c04f5787 17498 s_app_file_string (filename, 0);
ecb4347a
DJ
17499 }
17500 first_file_directive = 1;
17501 }
c5dd6aab
DJ
17502}
17503
17504/* The .loc directive, implying DWARF-2. */
252b5132
RH
17505
17506static void
17a2f251 17507s_mips_loc (int x ATTRIBUTE_UNUSED)
252b5132 17508{
c5dd6aab
DJ
17509 if (!ECOFF_DEBUGGING)
17510 dwarf2_directive_loc (0);
252b5132
RH
17511}
17512
252b5132
RH
17513/* The .end directive. */
17514
17515static void
17a2f251 17516s_mips_end (int x ATTRIBUTE_UNUSED)
252b5132
RH
17517{
17518 symbolS *p;
252b5132 17519
7a621144
DJ
17520 /* Following functions need their own .frame and .cprestore directives. */
17521 mips_frame_reg_valid = 0;
17522 mips_cprestore_valid = 0;
17523
252b5132
RH
17524 if (!is_end_of_line[(unsigned char) *input_line_pointer])
17525 {
17526 p = get_symbol ();
17527 demand_empty_rest_of_line ();
17528 }
17529 else
17530 p = NULL;
17531
14949570 17532 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
252b5132
RH
17533 as_warn (_(".end not in text section"));
17534
17535 if (!cur_proc_ptr)
17536 {
1661c76c 17537 as_warn (_(".end directive without a preceding .ent directive"));
252b5132
RH
17538 demand_empty_rest_of_line ();
17539 return;
17540 }
17541
17542 if (p != NULL)
17543 {
9c2799c2 17544 gas_assert (S_GET_NAME (p));
9b2f1d35 17545 if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->func_sym)))
1661c76c 17546 as_warn (_(".end symbol does not match .ent symbol"));
ecb4347a
DJ
17547
17548 if (debug_type == DEBUG_STABS)
17549 stabs_generate_asm_endfunc (S_GET_NAME (p),
17550 S_GET_NAME (p));
252b5132
RH
17551 }
17552 else
17553 as_warn (_(".end directive missing or unknown symbol"));
17554
9b2f1d35
EC
17555 /* Create an expression to calculate the size of the function. */
17556 if (p && cur_proc_ptr)
17557 {
17558 OBJ_SYMFIELD_TYPE *obj = symbol_get_obj (p);
17559 expressionS *exp = xmalloc (sizeof (expressionS));
17560
17561 obj->size = exp;
17562 exp->X_op = O_subtract;
17563 exp->X_add_symbol = symbol_temp_new_now ();
17564 exp->X_op_symbol = p;
17565 exp->X_add_number = 0;
17566
17567 cur_proc_ptr->func_end_sym = exp->X_add_symbol;
17568 }
17569
ecb4347a 17570 /* Generate a .pdr section. */
f3ded42a 17571 if (!ECOFF_DEBUGGING && mips_flag_pdr)
ecb4347a
DJ
17572 {
17573 segT saved_seg = now_seg;
17574 subsegT saved_subseg = now_subseg;
ecb4347a
DJ
17575 expressionS exp;
17576 char *fragp;
252b5132 17577
252b5132 17578#ifdef md_flush_pending_output
ecb4347a 17579 md_flush_pending_output ();
252b5132
RH
17580#endif
17581
9c2799c2 17582 gas_assert (pdr_seg);
ecb4347a 17583 subseg_set (pdr_seg, 0);
252b5132 17584
ecb4347a
DJ
17585 /* Write the symbol. */
17586 exp.X_op = O_symbol;
17587 exp.X_add_symbol = p;
17588 exp.X_add_number = 0;
17589 emit_expr (&exp, 4);
252b5132 17590
ecb4347a 17591 fragp = frag_more (7 * 4);
252b5132 17592
17a2f251
TS
17593 md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4);
17594 md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4);
17595 md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4);
17596 md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4);
17597 md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4);
17598 md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4);
17599 md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4);
252b5132 17600
ecb4347a
DJ
17601 subseg_set (saved_seg, saved_subseg);
17602 }
252b5132
RH
17603
17604 cur_proc_ptr = NULL;
17605}
17606
17607/* The .aent and .ent directives. */
17608
17609static void
17a2f251 17610s_mips_ent (int aent)
252b5132 17611{
252b5132 17612 symbolS *symbolP;
252b5132
RH
17613
17614 symbolP = get_symbol ();
17615 if (*input_line_pointer == ',')
f9419b05 17616 ++input_line_pointer;
252b5132 17617 SKIP_WHITESPACE ();
3882b010 17618 if (ISDIGIT (*input_line_pointer)
d9a62219 17619 || *input_line_pointer == '-')
874e8986 17620 get_number ();
252b5132 17621
14949570 17622 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
1661c76c 17623 as_warn (_(".ent or .aent not in text section"));
252b5132
RH
17624
17625 if (!aent && cur_proc_ptr)
9a41af64 17626 as_warn (_("missing .end"));
252b5132
RH
17627
17628 if (!aent)
17629 {
7a621144
DJ
17630 /* This function needs its own .frame and .cprestore directives. */
17631 mips_frame_reg_valid = 0;
17632 mips_cprestore_valid = 0;
17633
252b5132
RH
17634 cur_proc_ptr = &cur_proc;
17635 memset (cur_proc_ptr, '\0', sizeof (procS));
17636
9b2f1d35 17637 cur_proc_ptr->func_sym = symbolP;
252b5132 17638
f9419b05 17639 ++numprocs;
ecb4347a
DJ
17640
17641 if (debug_type == DEBUG_STABS)
17642 stabs_generate_asm_func (S_GET_NAME (symbolP),
17643 S_GET_NAME (symbolP));
252b5132
RH
17644 }
17645
7c0fc524
MR
17646 symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION;
17647
252b5132
RH
17648 demand_empty_rest_of_line ();
17649}
17650
17651/* The .frame directive. If the mdebug section is present (IRIX 5 native)
bdaaa2e1 17652 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
252b5132 17653 s_mips_frame is used so that we can set the PDR information correctly.
bdaaa2e1 17654 We can't use the ecoff routines because they make reference to the ecoff
252b5132
RH
17655 symbol table (in the mdebug section). */
17656
17657static void
17a2f251 17658s_mips_frame (int ignore ATTRIBUTE_UNUSED)
252b5132 17659{
f3ded42a
RS
17660 if (ECOFF_DEBUGGING)
17661 s_ignore (ignore);
17662 else
ecb4347a
DJ
17663 {
17664 long val;
252b5132 17665
ecb4347a
DJ
17666 if (cur_proc_ptr == (procS *) NULL)
17667 {
17668 as_warn (_(".frame outside of .ent"));
17669 demand_empty_rest_of_line ();
17670 return;
17671 }
252b5132 17672
ecb4347a
DJ
17673 cur_proc_ptr->frame_reg = tc_get_register (1);
17674
17675 SKIP_WHITESPACE ();
17676 if (*input_line_pointer++ != ','
17677 || get_absolute_expression_and_terminator (&val) != ',')
17678 {
1661c76c 17679 as_warn (_("bad .frame directive"));
ecb4347a
DJ
17680 --input_line_pointer;
17681 demand_empty_rest_of_line ();
17682 return;
17683 }
252b5132 17684
ecb4347a
DJ
17685 cur_proc_ptr->frame_offset = val;
17686 cur_proc_ptr->pc_reg = tc_get_register (0);
252b5132 17687
252b5132 17688 demand_empty_rest_of_line ();
252b5132 17689 }
252b5132
RH
17690}
17691
bdaaa2e1
KH
17692/* The .fmask and .mask directives. If the mdebug section is present
17693 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
252b5132 17694 embedded targets, s_mips_mask is used so that we can set the PDR
bdaaa2e1 17695 information correctly. We can't use the ecoff routines because they
252b5132
RH
17696 make reference to the ecoff symbol table (in the mdebug section). */
17697
17698static void
17a2f251 17699s_mips_mask (int reg_type)
252b5132 17700{
f3ded42a
RS
17701 if (ECOFF_DEBUGGING)
17702 s_ignore (reg_type);
17703 else
252b5132 17704 {
ecb4347a 17705 long mask, off;
252b5132 17706
ecb4347a
DJ
17707 if (cur_proc_ptr == (procS *) NULL)
17708 {
17709 as_warn (_(".mask/.fmask outside of .ent"));
17710 demand_empty_rest_of_line ();
17711 return;
17712 }
252b5132 17713
ecb4347a
DJ
17714 if (get_absolute_expression_and_terminator (&mask) != ',')
17715 {
1661c76c 17716 as_warn (_("bad .mask/.fmask directive"));
ecb4347a
DJ
17717 --input_line_pointer;
17718 demand_empty_rest_of_line ();
17719 return;
17720 }
252b5132 17721
ecb4347a
DJ
17722 off = get_absolute_expression ();
17723
17724 if (reg_type == 'F')
17725 {
17726 cur_proc_ptr->fpreg_mask = mask;
17727 cur_proc_ptr->fpreg_offset = off;
17728 }
17729 else
17730 {
17731 cur_proc_ptr->reg_mask = mask;
17732 cur_proc_ptr->reg_offset = off;
17733 }
17734
17735 demand_empty_rest_of_line ();
252b5132 17736 }
252b5132
RH
17737}
17738
316f5878
RS
17739/* A table describing all the processors gas knows about. Names are
17740 matched in the order listed.
e7af610e 17741
316f5878
RS
17742 To ease comparison, please keep this table in the same order as
17743 gcc's mips_cpu_info_table[]. */
e972090a
NC
17744static const struct mips_cpu_info mips_cpu_info_table[] =
17745{
316f5878 17746 /* Entries for generic ISAs */
d16afab6
RS
17747 { "mips1", MIPS_CPU_IS_ISA, 0, ISA_MIPS1, CPU_R3000 },
17748 { "mips2", MIPS_CPU_IS_ISA, 0, ISA_MIPS2, CPU_R6000 },
17749 { "mips3", MIPS_CPU_IS_ISA, 0, ISA_MIPS3, CPU_R4000 },
17750 { "mips4", MIPS_CPU_IS_ISA, 0, ISA_MIPS4, CPU_R8000 },
17751 { "mips5", MIPS_CPU_IS_ISA, 0, ISA_MIPS5, CPU_MIPS5 },
17752 { "mips32", MIPS_CPU_IS_ISA, 0, ISA_MIPS32, CPU_MIPS32 },
17753 { "mips32r2", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
17754 { "mips64", MIPS_CPU_IS_ISA, 0, ISA_MIPS64, CPU_MIPS64 },
17755 { "mips64r2", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R2, CPU_MIPS64R2 },
316f5878
RS
17756
17757 /* MIPS I */
d16afab6
RS
17758 { "r3000", 0, 0, ISA_MIPS1, CPU_R3000 },
17759 { "r2000", 0, 0, ISA_MIPS1, CPU_R3000 },
17760 { "r3900", 0, 0, ISA_MIPS1, CPU_R3900 },
316f5878
RS
17761
17762 /* MIPS II */
d16afab6 17763 { "r6000", 0, 0, ISA_MIPS2, CPU_R6000 },
316f5878
RS
17764
17765 /* MIPS III */
d16afab6
RS
17766 { "r4000", 0, 0, ISA_MIPS3, CPU_R4000 },
17767 { "r4010", 0, 0, ISA_MIPS2, CPU_R4010 },
17768 { "vr4100", 0, 0, ISA_MIPS3, CPU_VR4100 },
17769 { "vr4111", 0, 0, ISA_MIPS3, CPU_R4111 },
17770 { "vr4120", 0, 0, ISA_MIPS3, CPU_VR4120 },
17771 { "vr4130", 0, 0, ISA_MIPS3, CPU_VR4120 },
17772 { "vr4181", 0, 0, ISA_MIPS3, CPU_R4111 },
17773 { "vr4300", 0, 0, ISA_MIPS3, CPU_R4300 },
17774 { "r4400", 0, 0, ISA_MIPS3, CPU_R4400 },
17775 { "r4600", 0, 0, ISA_MIPS3, CPU_R4600 },
17776 { "orion", 0, 0, ISA_MIPS3, CPU_R4600 },
17777 { "r4650", 0, 0, ISA_MIPS3, CPU_R4650 },
17778 { "r5900", 0, 0, ISA_MIPS3, CPU_R5900 },
b15591bb 17779 /* ST Microelectronics Loongson 2E and 2F cores */
d16afab6
RS
17780 { "loongson2e", 0, 0, ISA_MIPS3, CPU_LOONGSON_2E },
17781 { "loongson2f", 0, 0, ISA_MIPS3, CPU_LOONGSON_2F },
316f5878
RS
17782
17783 /* MIPS IV */
d16afab6
RS
17784 { "r8000", 0, 0, ISA_MIPS4, CPU_R8000 },
17785 { "r10000", 0, 0, ISA_MIPS4, CPU_R10000 },
17786 { "r12000", 0, 0, ISA_MIPS4, CPU_R12000 },
17787 { "r14000", 0, 0, ISA_MIPS4, CPU_R14000 },
17788 { "r16000", 0, 0, ISA_MIPS4, CPU_R16000 },
17789 { "vr5000", 0, 0, ISA_MIPS4, CPU_R5000 },
17790 { "vr5400", 0, 0, ISA_MIPS4, CPU_VR5400 },
17791 { "vr5500", 0, 0, ISA_MIPS4, CPU_VR5500 },
17792 { "rm5200", 0, 0, ISA_MIPS4, CPU_R5000 },
17793 { "rm5230", 0, 0, ISA_MIPS4, CPU_R5000 },
17794 { "rm5231", 0, 0, ISA_MIPS4, CPU_R5000 },
17795 { "rm5261", 0, 0, ISA_MIPS4, CPU_R5000 },
17796 { "rm5721", 0, 0, ISA_MIPS4, CPU_R5000 },
17797 { "rm7000", 0, 0, ISA_MIPS4, CPU_RM7000 },
17798 { "rm9000", 0, 0, ISA_MIPS4, CPU_RM9000 },
316f5878
RS
17799
17800 /* MIPS 32 */
d16afab6
RS
17801 { "4kc", 0, 0, ISA_MIPS32, CPU_MIPS32 },
17802 { "4km", 0, 0, ISA_MIPS32, CPU_MIPS32 },
17803 { "4kp", 0, 0, ISA_MIPS32, CPU_MIPS32 },
17804 { "4ksc", 0, ASE_SMARTMIPS, ISA_MIPS32, CPU_MIPS32 },
ad3fea08
TS
17805
17806 /* MIPS 32 Release 2 */
d16afab6
RS
17807 { "4kec", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
17808 { "4kem", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
17809 { "4kep", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
17810 { "4ksd", 0, ASE_SMARTMIPS, ISA_MIPS32R2, CPU_MIPS32R2 },
17811 { "m4k", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
17812 { "m4kp", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
17813 { "m14k", 0, ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 },
17814 { "m14kc", 0, ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 },
17815 { "m14ke", 0, ASE_DSP | ASE_DSPR2 | ASE_MCU,
17816 ISA_MIPS32R2, CPU_MIPS32R2 },
17817 { "m14kec", 0, ASE_DSP | ASE_DSPR2 | ASE_MCU,
17818 ISA_MIPS32R2, CPU_MIPS32R2 },
17819 { "24kc", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
17820 { "24kf2_1", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
17821 { "24kf", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
17822 { "24kf1_1", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
0fdf1951 17823 /* Deprecated forms of the above. */
d16afab6
RS
17824 { "24kfx", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
17825 { "24kx", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
01fd108f 17826 /* 24KE is a 24K with DSP ASE, other ASEs are optional. */
d16afab6
RS
17827 { "24kec", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
17828 { "24kef2_1", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
17829 { "24kef", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
17830 { "24kef1_1", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
0fdf1951 17831 /* Deprecated forms of the above. */
d16afab6
RS
17832 { "24kefx", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
17833 { "24kex", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
01fd108f 17834 /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */
d16afab6
RS
17835 { "34kc", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
17836 { "34kf2_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
17837 { "34kf", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
17838 { "34kf1_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
0fdf1951 17839 /* Deprecated forms of the above. */
d16afab6
RS
17840 { "34kfx", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
17841 { "34kx", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
711eefe4 17842 /* 34Kn is a 34kc without DSP. */
d16afab6 17843 { "34kn", 0, ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
01fd108f 17844 /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */
d16afab6
RS
17845 { "74kc", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
17846 { "74kf2_1", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
17847 { "74kf", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
17848 { "74kf1_1", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
17849 { "74kf3_2", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
0fdf1951 17850 /* Deprecated forms of the above. */
d16afab6
RS
17851 { "74kfx", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
17852 { "74kx", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
30f8113a 17853 /* 1004K cores are multiprocessor versions of the 34K. */
d16afab6
RS
17854 { "1004kc", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
17855 { "1004kf2_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
17856 { "1004kf", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
17857 { "1004kf1_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
32b26a03 17858
316f5878 17859 /* MIPS 64 */
d16afab6
RS
17860 { "5kc", 0, 0, ISA_MIPS64, CPU_MIPS64 },
17861 { "5kf", 0, 0, ISA_MIPS64, CPU_MIPS64 },
17862 { "20kc", 0, ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 },
17863 { "25kf", 0, ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 },
ad3fea08 17864
c7a23324 17865 /* Broadcom SB-1 CPU core */
d16afab6 17866 { "sb1", 0, ASE_MIPS3D | ASE_MDMX, ISA_MIPS64, CPU_SB1 },
1e85aad8 17867 /* Broadcom SB-1A CPU core */
d16afab6 17868 { "sb1a", 0, ASE_MIPS3D | ASE_MDMX, ISA_MIPS64, CPU_SB1 },
d051516a 17869
d16afab6 17870 { "loongson3a", 0, 0, ISA_MIPS64, CPU_LOONGSON_3A },
e7af610e 17871
ed163775
MR
17872 /* MIPS 64 Release 2 */
17873
967344c6 17874 /* Cavium Networks Octeon CPU core */
d16afab6
RS
17875 { "octeon", 0, 0, ISA_MIPS64R2, CPU_OCTEON },
17876 { "octeon+", 0, 0, ISA_MIPS64R2, CPU_OCTEONP },
17877 { "octeon2", 0, 0, ISA_MIPS64R2, CPU_OCTEON2 },
967344c6 17878
52b6b6b9 17879 /* RMI Xlr */
d16afab6 17880 { "xlr", 0, 0, ISA_MIPS64, CPU_XLR },
52b6b6b9 17881
55a36193
MK
17882 /* Broadcom XLP.
17883 XLP is mostly like XLR, with the prominent exception that it is
17884 MIPS64R2 rather than MIPS64. */
d16afab6 17885 { "xlp", 0, 0, ISA_MIPS64R2, CPU_XLR },
55a36193 17886
316f5878 17887 /* End marker */
d16afab6 17888 { NULL, 0, 0, 0, 0 }
316f5878 17889};
e7af610e 17890
84ea6cf2 17891
316f5878
RS
17892/* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
17893 with a final "000" replaced by "k". Ignore case.
e7af610e 17894
316f5878 17895 Note: this function is shared between GCC and GAS. */
c6c98b38 17896
b34976b6 17897static bfd_boolean
17a2f251 17898mips_strict_matching_cpu_name_p (const char *canonical, const char *given)
316f5878
RS
17899{
17900 while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical))
17901 given++, canonical++;
17902
17903 return ((*given == 0 && *canonical == 0)
17904 || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0));
17905}
17906
17907
17908/* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
17909 CPU name. We've traditionally allowed a lot of variation here.
17910
17911 Note: this function is shared between GCC and GAS. */
17912
b34976b6 17913static bfd_boolean
17a2f251 17914mips_matching_cpu_name_p (const char *canonical, const char *given)
316f5878
RS
17915{
17916 /* First see if the name matches exactly, or with a final "000"
17917 turned into "k". */
17918 if (mips_strict_matching_cpu_name_p (canonical, given))
b34976b6 17919 return TRUE;
316f5878
RS
17920
17921 /* If not, try comparing based on numerical designation alone.
17922 See if GIVEN is an unadorned number, or 'r' followed by a number. */
17923 if (TOLOWER (*given) == 'r')
17924 given++;
17925 if (!ISDIGIT (*given))
b34976b6 17926 return FALSE;
316f5878
RS
17927
17928 /* Skip over some well-known prefixes in the canonical name,
17929 hoping to find a number there too. */
17930 if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r')
17931 canonical += 2;
17932 else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm')
17933 canonical += 2;
17934 else if (TOLOWER (canonical[0]) == 'r')
17935 canonical += 1;
17936
17937 return mips_strict_matching_cpu_name_p (canonical, given);
17938}
17939
17940
17941/* Parse an option that takes the name of a processor as its argument.
17942 OPTION is the name of the option and CPU_STRING is the argument.
17943 Return the corresponding processor enumeration if the CPU_STRING is
17944 recognized, otherwise report an error and return null.
17945
17946 A similar function exists in GCC. */
e7af610e
NC
17947
17948static const struct mips_cpu_info *
17a2f251 17949mips_parse_cpu (const char *option, const char *cpu_string)
e7af610e 17950{
316f5878 17951 const struct mips_cpu_info *p;
e7af610e 17952
316f5878
RS
17953 /* 'from-abi' selects the most compatible architecture for the given
17954 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
17955 EABIs, we have to decide whether we're using the 32-bit or 64-bit
17956 version. Look first at the -mgp options, if given, otherwise base
17957 the choice on MIPS_DEFAULT_64BIT.
e7af610e 17958
316f5878
RS
17959 Treat NO_ABI like the EABIs. One reason to do this is that the
17960 plain 'mips' and 'mips64' configs have 'from-abi' as their default
17961 architecture. This code picks MIPS I for 'mips' and MIPS III for
17962 'mips64', just as we did in the days before 'from-abi'. */
17963 if (strcasecmp (cpu_string, "from-abi") == 0)
17964 {
17965 if (ABI_NEEDS_32BIT_REGS (mips_abi))
17966 return mips_cpu_info_from_isa (ISA_MIPS1);
17967
17968 if (ABI_NEEDS_64BIT_REGS (mips_abi))
17969 return mips_cpu_info_from_isa (ISA_MIPS3);
17970
17971 if (file_mips_gp32 >= 0)
17972 return mips_cpu_info_from_isa (file_mips_gp32 ? ISA_MIPS1 : ISA_MIPS3);
17973
17974 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
17975 ? ISA_MIPS3
17976 : ISA_MIPS1);
17977 }
17978
17979 /* 'default' has traditionally been a no-op. Probably not very useful. */
17980 if (strcasecmp (cpu_string, "default") == 0)
17981 return 0;
17982
17983 for (p = mips_cpu_info_table; p->name != 0; p++)
17984 if (mips_matching_cpu_name_p (p->name, cpu_string))
17985 return p;
17986
1661c76c 17987 as_bad (_("bad value (%s) for %s"), cpu_string, option);
316f5878 17988 return 0;
e7af610e
NC
17989}
17990
316f5878
RS
17991/* Return the canonical processor information for ISA (a member of the
17992 ISA_MIPS* enumeration). */
17993
e7af610e 17994static const struct mips_cpu_info *
17a2f251 17995mips_cpu_info_from_isa (int isa)
e7af610e
NC
17996{
17997 int i;
17998
17999 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
ad3fea08 18000 if ((mips_cpu_info_table[i].flags & MIPS_CPU_IS_ISA)
316f5878 18001 && isa == mips_cpu_info_table[i].isa)
e7af610e
NC
18002 return (&mips_cpu_info_table[i]);
18003
e972090a 18004 return NULL;
e7af610e 18005}
fef14a42
TS
18006
18007static const struct mips_cpu_info *
17a2f251 18008mips_cpu_info_from_arch (int arch)
fef14a42
TS
18009{
18010 int i;
18011
18012 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
18013 if (arch == mips_cpu_info_table[i].cpu)
18014 return (&mips_cpu_info_table[i]);
18015
18016 return NULL;
18017}
316f5878
RS
18018\f
18019static void
17a2f251 18020show (FILE *stream, const char *string, int *col_p, int *first_p)
316f5878
RS
18021{
18022 if (*first_p)
18023 {
18024 fprintf (stream, "%24s", "");
18025 *col_p = 24;
18026 }
18027 else
18028 {
18029 fprintf (stream, ", ");
18030 *col_p += 2;
18031 }
e7af610e 18032
316f5878
RS
18033 if (*col_p + strlen (string) > 72)
18034 {
18035 fprintf (stream, "\n%24s", "");
18036 *col_p = 24;
18037 }
18038
18039 fprintf (stream, "%s", string);
18040 *col_p += strlen (string);
18041
18042 *first_p = 0;
18043}
18044
18045void
17a2f251 18046md_show_usage (FILE *stream)
e7af610e 18047{
316f5878
RS
18048 int column, first;
18049 size_t i;
18050
18051 fprintf (stream, _("\
18052MIPS options:\n\
316f5878
RS
18053-EB generate big endian output\n\
18054-EL generate little endian output\n\
18055-g, -g2 do not remove unneeded NOPs or swap branches\n\
18056-G NUM allow referencing objects up to NUM bytes\n\
18057 implicitly with the gp register [default 8]\n"));
18058 fprintf (stream, _("\
18059-mips1 generate MIPS ISA I instructions\n\
18060-mips2 generate MIPS ISA II instructions\n\
18061-mips3 generate MIPS ISA III instructions\n\
18062-mips4 generate MIPS ISA IV instructions\n\
18063-mips5 generate MIPS ISA V instructions\n\
18064-mips32 generate MIPS32 ISA instructions\n\
af7ee8bf 18065-mips32r2 generate MIPS32 release 2 ISA instructions\n\
316f5878 18066-mips64 generate MIPS64 ISA instructions\n\
5f74bc13 18067-mips64r2 generate MIPS64 release 2 ISA instructions\n\
316f5878
RS
18068-march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
18069
18070 first = 1;
e7af610e
NC
18071
18072 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
316f5878
RS
18073 show (stream, mips_cpu_info_table[i].name, &column, &first);
18074 show (stream, "from-abi", &column, &first);
18075 fputc ('\n', stream);
e7af610e 18076
316f5878
RS
18077 fprintf (stream, _("\
18078-mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
18079-no-mCPU don't generate code specific to CPU.\n\
18080 For -mCPU and -no-mCPU, CPU must be one of:\n"));
18081
18082 first = 1;
18083
18084 show (stream, "3900", &column, &first);
18085 show (stream, "4010", &column, &first);
18086 show (stream, "4100", &column, &first);
18087 show (stream, "4650", &column, &first);
18088 fputc ('\n', stream);
18089
18090 fprintf (stream, _("\
18091-mips16 generate mips16 instructions\n\
18092-no-mips16 do not generate mips16 instructions\n"));
18093 fprintf (stream, _("\
df58fc94
RS
18094-mmicromips generate microMIPS instructions\n\
18095-mno-micromips do not generate microMIPS instructions\n"));
18096 fprintf (stream, _("\
e16bfa71
TS
18097-msmartmips generate smartmips instructions\n\
18098-mno-smartmips do not generate smartmips instructions\n"));
18099 fprintf (stream, _("\
74cd071d
CF
18100-mdsp generate DSP instructions\n\
18101-mno-dsp do not generate DSP instructions\n"));
18102 fprintf (stream, _("\
8b082fb1
TS
18103-mdspr2 generate DSP R2 instructions\n\
18104-mno-dspr2 do not generate DSP R2 instructions\n"));
18105 fprintf (stream, _("\
ef2e4d86
CF
18106-mmt generate MT instructions\n\
18107-mno-mt do not generate MT instructions\n"));
18108 fprintf (stream, _("\
dec0624d
MR
18109-mmcu generate MCU instructions\n\
18110-mno-mcu do not generate MCU instructions\n"));
18111 fprintf (stream, _("\
56d438b1
CF
18112-mmsa generate MSA instructions\n\
18113-mno-msa do not generate MSA instructions\n"));
18114 fprintf (stream, _("\
b015e599
AP
18115-mvirt generate Virtualization instructions\n\
18116-mno-virt do not generate Virtualization instructions\n"));
18117 fprintf (stream, _("\
833794fc
MR
18118-minsn32 only generate 32-bit microMIPS instructions\n\
18119-mno-insn32 generate all microMIPS instructions\n"));
18120 fprintf (stream, _("\
c67a084a
NC
18121-mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\
18122-mfix-loongson2f-nop work around Loongson2F NOP errata\n\
d766e8ec 18123-mfix-vr4120 work around certain VR4120 errata\n\
7d8e00cf 18124-mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
6a32d874 18125-mfix-24k insert a nop after ERET and DERET instructions\n\
d954098f 18126-mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\
316f5878
RS
18127-mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
18128-mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
aed1a261 18129-msym32 assume all symbols have 32-bit values\n\
316f5878
RS
18130-O0 remove unneeded NOPs, do not swap branches\n\
18131-O remove unneeded NOPs and swap branches\n\
316f5878
RS
18132--trap, --no-break trap exception on div by 0 and mult overflow\n\
18133--break, --no-trap break exception on div by 0 and mult overflow\n"));
037b32b9
AN
18134 fprintf (stream, _("\
18135-mhard-float allow floating-point instructions\n\
18136-msoft-float do not allow floating-point instructions\n\
18137-msingle-float only allow 32-bit floating-point operations\n\
18138-mdouble-float allow 32-bit and 64-bit floating-point operations\n\
3bf0dbfb 18139--[no-]construct-floats [dis]allow floating point values to be constructed\n\
ba92f887
MR
18140--[no-]relax-branch [dis]allow out-of-range branches to be relaxed\n\
18141-mnan=ENCODING select an IEEE 754 NaN encoding convention, either of:\n"));
18142
18143 first = 1;
18144
18145 show (stream, "legacy", &column, &first);
18146 show (stream, "2008", &column, &first);
18147
18148 fputc ('\n', stream);
18149
316f5878
RS
18150 fprintf (stream, _("\
18151-KPIC, -call_shared generate SVR4 position independent code\n\
861fb55a 18152-call_nonpic generate non-PIC code that can operate with DSOs\n\
0c000745 18153-mvxworks-pic generate VxWorks position independent code\n\
861fb55a 18154-non_shared do not generate code that can operate with DSOs\n\
316f5878 18155-xgot assume a 32 bit GOT\n\
dcd410fe 18156-mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
bbe506e8 18157-mshared, -mno-shared disable/enable .cpload optimization for\n\
d821e36b 18158 position dependent (non shared) code\n\
316f5878
RS
18159-mabi=ABI create ABI conformant object file for:\n"));
18160
18161 first = 1;
18162
18163 show (stream, "32", &column, &first);
18164 show (stream, "o64", &column, &first);
18165 show (stream, "n32", &column, &first);
18166 show (stream, "64", &column, &first);
18167 show (stream, "eabi", &column, &first);
18168
18169 fputc ('\n', stream);
18170
18171 fprintf (stream, _("\
18172-32 create o32 ABI object file (default)\n\
18173-n32 create n32 ABI object file\n\
18174-64 create 64 ABI object file\n"));
e7af610e 18175}
14e777e0 18176
1575952e 18177#ifdef TE_IRIX
14e777e0 18178enum dwarf2_format
413a266c 18179mips_dwarf2_format (asection *sec ATTRIBUTE_UNUSED)
14e777e0 18180{
369943fe 18181 if (HAVE_64BIT_SYMBOLS)
1575952e 18182 return dwarf2_format_64bit_irix;
14e777e0
KB
18183 else
18184 return dwarf2_format_32bit;
18185}
1575952e 18186#endif
73369e65
EC
18187
18188int
18189mips_dwarf2_addr_size (void)
18190{
6b6b3450 18191 if (HAVE_64BIT_OBJECTS)
73369e65 18192 return 8;
73369e65
EC
18193 else
18194 return 4;
18195}
5862107c
EC
18196
18197/* Standard calling conventions leave the CFA at SP on entry. */
18198void
18199mips_cfi_frame_initial_instructions (void)
18200{
18201 cfi_add_CFA_def_cfa_register (SP);
18202}
18203
707bfff6
TS
18204int
18205tc_mips_regname_to_dw2regnum (char *regname)
18206{
18207 unsigned int regnum = -1;
18208 unsigned int reg;
18209
18210 if (reg_lookup (&regname, RTYPE_GP | RTYPE_NUM, &reg))
18211 regnum = reg;
18212
18213 return regnum;
18214}
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