Commit | Line | Data |
---|---|---|
252b5132 | 1 | /* tc-mips.c -- assemble code for a MIPS chip. |
81912461 | 2 | Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, |
f17c130b | 3 | 2003, 2004, 2005 Free Software Foundation, Inc. |
252b5132 RH |
4 | Contributed by the OSF and Ralph Campbell. |
5 | Written by Keith Knowles and Ralph Campbell, working independently. | |
6 | Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus | |
7 | Support. | |
8 | ||
9 | This file is part of GAS. | |
10 | ||
11 | GAS is free software; you can redistribute it and/or modify | |
12 | it under the terms of the GNU General Public License as published by | |
13 | the Free Software Foundation; either version 2, or (at your option) | |
14 | any later version. | |
15 | ||
16 | GAS is distributed in the hope that it will be useful, | |
17 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | GNU General Public License for more details. | |
20 | ||
21 | You should have received a copy of the GNU General Public License | |
22 | along with GAS; see the file COPYING. If not, write to the Free | |
23 | Software Foundation, 59 Temple Place - Suite 330, Boston, MA | |
24 | 02111-1307, USA. */ | |
25 | ||
26 | #include "as.h" | |
27 | #include "config.h" | |
28 | #include "subsegs.h" | |
3882b010 | 29 | #include "safe-ctype.h" |
252b5132 | 30 | |
252b5132 | 31 | #include <stdarg.h> |
252b5132 RH |
32 | |
33 | #include "opcode/mips.h" | |
34 | #include "itbl-ops.h" | |
c5dd6aab | 35 | #include "dwarf2dbg.h" |
252b5132 RH |
36 | |
37 | #ifdef DEBUG | |
38 | #define DBG(x) printf x | |
39 | #else | |
40 | #define DBG(x) | |
41 | #endif | |
42 | ||
43 | #ifdef OBJ_MAYBE_ELF | |
44 | /* Clean up namespace so we can include obj-elf.h too. */ | |
17a2f251 TS |
45 | static int mips_output_flavor (void); |
46 | static int mips_output_flavor (void) { return OUTPUT_FLAVOR; } | |
252b5132 RH |
47 | #undef OBJ_PROCESS_STAB |
48 | #undef OUTPUT_FLAVOR | |
49 | #undef S_GET_ALIGN | |
50 | #undef S_GET_SIZE | |
51 | #undef S_SET_ALIGN | |
52 | #undef S_SET_SIZE | |
252b5132 RH |
53 | #undef obj_frob_file |
54 | #undef obj_frob_file_after_relocs | |
55 | #undef obj_frob_symbol | |
56 | #undef obj_pop_insert | |
57 | #undef obj_sec_sym_ok_for_reloc | |
58 | #undef OBJ_COPY_SYMBOL_ATTRIBUTES | |
59 | ||
60 | #include "obj-elf.h" | |
61 | /* Fix any of them that we actually care about. */ | |
62 | #undef OUTPUT_FLAVOR | |
63 | #define OUTPUT_FLAVOR mips_output_flavor() | |
64 | #endif | |
65 | ||
66 | #if defined (OBJ_ELF) | |
67 | #include "elf/mips.h" | |
68 | #endif | |
69 | ||
70 | #ifndef ECOFF_DEBUGGING | |
71 | #define NO_ECOFF_DEBUGGING | |
72 | #define ECOFF_DEBUGGING 0 | |
73 | #endif | |
74 | ||
ecb4347a DJ |
75 | int mips_flag_mdebug = -1; |
76 | ||
dcd410fe RO |
77 | /* Control generation of .pdr sections. Off by default on IRIX: the native |
78 | linker doesn't know about and discards them, but relocations against them | |
79 | remain, leading to rld crashes. */ | |
80 | #ifdef TE_IRIX | |
81 | int mips_flag_pdr = FALSE; | |
82 | #else | |
83 | int mips_flag_pdr = TRUE; | |
84 | #endif | |
85 | ||
252b5132 RH |
86 | #include "ecoff.h" |
87 | ||
88 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
89 | static char *mips_regmask_frag; | |
90 | #endif | |
91 | ||
85b51719 | 92 | #define ZERO 0 |
252b5132 RH |
93 | #define AT 1 |
94 | #define TREG 24 | |
95 | #define PIC_CALL_REG 25 | |
96 | #define KT0 26 | |
97 | #define KT1 27 | |
98 | #define GP 28 | |
99 | #define SP 29 | |
100 | #define FP 30 | |
101 | #define RA 31 | |
102 | ||
103 | #define ILLEGAL_REG (32) | |
104 | ||
105 | /* Allow override of standard little-endian ECOFF format. */ | |
106 | ||
107 | #ifndef ECOFF_LITTLE_FORMAT | |
108 | #define ECOFF_LITTLE_FORMAT "ecoff-littlemips" | |
109 | #endif | |
110 | ||
111 | extern int target_big_endian; | |
112 | ||
252b5132 | 113 | /* The name of the readonly data section. */ |
4d0d148d | 114 | #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_ecoff_flavour \ |
252b5132 | 115 | ? ".rdata" \ |
056350c6 NC |
116 | : OUTPUT_FLAVOR == bfd_target_coff_flavour \ |
117 | ? ".rdata" \ | |
252b5132 RH |
118 | : OUTPUT_FLAVOR == bfd_target_elf_flavour \ |
119 | ? ".rodata" \ | |
120 | : (abort (), "")) | |
121 | ||
a325df1d TS |
122 | /* The ABI to use. */ |
123 | enum mips_abi_level | |
124 | { | |
125 | NO_ABI = 0, | |
126 | O32_ABI, | |
127 | O64_ABI, | |
128 | N32_ABI, | |
129 | N64_ABI, | |
130 | EABI_ABI | |
131 | }; | |
132 | ||
133 | /* MIPS ABI we are using for this output file. */ | |
316f5878 | 134 | static enum mips_abi_level mips_abi = NO_ABI; |
a325df1d | 135 | |
143d77c5 EC |
136 | /* Whether or not we have code that can call pic code. */ |
137 | int mips_abicalls = FALSE; | |
138 | ||
aa6975fb ILT |
139 | /* Whether or not we have code which can be put into a shared |
140 | library. */ | |
141 | static bfd_boolean mips_in_shared = TRUE; | |
142 | ||
252b5132 RH |
143 | /* This is the set of options which may be modified by the .set |
144 | pseudo-op. We use a struct so that .set push and .set pop are more | |
145 | reliable. */ | |
146 | ||
e972090a NC |
147 | struct mips_set_options |
148 | { | |
252b5132 RH |
149 | /* MIPS ISA (Instruction Set Architecture) level. This is set to -1 |
150 | if it has not been initialized. Changed by `.set mipsN', and the | |
151 | -mipsN command line option, and the default CPU. */ | |
152 | int isa; | |
1f25f5d3 CD |
153 | /* Enabled Application Specific Extensions (ASEs). These are set to -1 |
154 | if they have not been initialized. Changed by `.set <asename>', by | |
155 | command line options, and based on the default architecture. */ | |
156 | int ase_mips3d; | |
deec1734 | 157 | int ase_mdmx; |
252b5132 RH |
158 | /* Whether we are assembling for the mips16 processor. 0 if we are |
159 | not, 1 if we are, and -1 if the value has not been initialized. | |
160 | Changed by `.set mips16' and `.set nomips16', and the -mips16 and | |
161 | -nomips16 command line options, and the default CPU. */ | |
162 | int mips16; | |
163 | /* Non-zero if we should not reorder instructions. Changed by `.set | |
164 | reorder' and `.set noreorder'. */ | |
165 | int noreorder; | |
166 | /* Non-zero if we should not permit the $at ($1) register to be used | |
167 | in instructions. Changed by `.set at' and `.set noat'. */ | |
168 | int noat; | |
169 | /* Non-zero if we should warn when a macro instruction expands into | |
170 | more than one machine instruction. Changed by `.set nomacro' and | |
171 | `.set macro'. */ | |
172 | int warn_about_macros; | |
173 | /* Non-zero if we should not move instructions. Changed by `.set | |
174 | move', `.set volatile', `.set nomove', and `.set novolatile'. */ | |
175 | int nomove; | |
176 | /* Non-zero if we should not optimize branches by moving the target | |
177 | of the branch into the delay slot. Actually, we don't perform | |
178 | this optimization anyhow. Changed by `.set bopt' and `.set | |
179 | nobopt'. */ | |
180 | int nobopt; | |
181 | /* Non-zero if we should not autoextend mips16 instructions. | |
182 | Changed by `.set autoextend' and `.set noautoextend'. */ | |
183 | int noautoextend; | |
a325df1d TS |
184 | /* Restrict general purpose registers and floating point registers |
185 | to 32 bit. This is initially determined when -mgp32 or -mfp32 | |
186 | is passed but can changed if the assembler code uses .set mipsN. */ | |
187 | int gp32; | |
188 | int fp32; | |
fef14a42 TS |
189 | /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march |
190 | command line option, and the default CPU. */ | |
191 | int arch; | |
252b5132 RH |
192 | }; |
193 | ||
a325df1d | 194 | /* True if -mgp32 was passed. */ |
a8e8e863 | 195 | static int file_mips_gp32 = -1; |
a325df1d TS |
196 | |
197 | /* True if -mfp32 was passed. */ | |
a8e8e863 | 198 | static int file_mips_fp32 = -1; |
a325df1d | 199 | |
252b5132 | 200 | /* This is the struct we use to hold the current set of options. Note |
a4672219 | 201 | that we must set the isa field to ISA_UNKNOWN and the ASE fields to |
e7af610e | 202 | -1 to indicate that they have not been initialized. */ |
252b5132 | 203 | |
e972090a NC |
204 | static struct mips_set_options mips_opts = |
205 | { | |
fef14a42 | 206 | ISA_UNKNOWN, -1, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0, CPU_UNKNOWN |
e7af610e | 207 | }; |
252b5132 RH |
208 | |
209 | /* These variables are filled in with the masks of registers used. | |
210 | The object format code reads them and puts them in the appropriate | |
211 | place. */ | |
212 | unsigned long mips_gprmask; | |
213 | unsigned long mips_cprmask[4]; | |
214 | ||
215 | /* MIPS ISA we are using for this output file. */ | |
e7af610e | 216 | static int file_mips_isa = ISA_UNKNOWN; |
252b5132 | 217 | |
a4672219 TS |
218 | /* True if -mips16 was passed or implied by arguments passed on the |
219 | command line (e.g., by -march). */ | |
220 | static int file_ase_mips16; | |
221 | ||
1f25f5d3 CD |
222 | /* True if -mips3d was passed or implied by arguments passed on the |
223 | command line (e.g., by -march). */ | |
224 | static int file_ase_mips3d; | |
225 | ||
deec1734 CD |
226 | /* True if -mdmx was passed or implied by arguments passed on the |
227 | command line (e.g., by -march). */ | |
228 | static int file_ase_mdmx; | |
229 | ||
ec68c924 | 230 | /* The argument of the -march= flag. The architecture we are assembling. */ |
fef14a42 | 231 | static int file_mips_arch = CPU_UNKNOWN; |
316f5878 | 232 | static const char *mips_arch_string; |
ec68c924 EC |
233 | |
234 | /* The argument of the -mtune= flag. The architecture for which we | |
235 | are optimizing. */ | |
236 | static int mips_tune = CPU_UNKNOWN; | |
316f5878 | 237 | static const char *mips_tune_string; |
ec68c924 | 238 | |
316f5878 | 239 | /* True when generating 32-bit code for a 64-bit processor. */ |
252b5132 RH |
240 | static int mips_32bitmode = 0; |
241 | ||
316f5878 RS |
242 | /* True if the given ABI requires 32-bit registers. */ |
243 | #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI) | |
244 | ||
245 | /* Likewise 64-bit registers. */ | |
246 | #define ABI_NEEDS_64BIT_REGS(ABI) \ | |
247 | ((ABI) == N32_ABI \ | |
248 | || (ABI) == N64_ABI \ | |
249 | || (ABI) == O64_ABI) | |
250 | ||
bdaaa2e1 | 251 | /* Return true if ISA supports 64 bit gp register instructions. */ |
9ce8a5dd | 252 | #define ISA_HAS_64BIT_REGS(ISA) ( \ |
e7af610e NC |
253 | (ISA) == ISA_MIPS3 \ |
254 | || (ISA) == ISA_MIPS4 \ | |
84ea6cf2 | 255 | || (ISA) == ISA_MIPS5 \ |
d1cf510e | 256 | || (ISA) == ISA_MIPS64 \ |
5f74bc13 | 257 | || (ISA) == ISA_MIPS64R2 \ |
9ce8a5dd GRK |
258 | ) |
259 | ||
af7ee8bf CD |
260 | /* Return true if ISA supports 64-bit right rotate (dror et al.) |
261 | instructions. */ | |
262 | #define ISA_HAS_DROR(ISA) ( \ | |
5f74bc13 | 263 | (ISA) == ISA_MIPS64R2 \ |
af7ee8bf CD |
264 | ) |
265 | ||
266 | /* Return true if ISA supports 32-bit right rotate (ror et al.) | |
267 | instructions. */ | |
268 | #define ISA_HAS_ROR(ISA) ( \ | |
269 | (ISA) == ISA_MIPS32R2 \ | |
5f74bc13 | 270 | || (ISA) == ISA_MIPS64R2 \ |
af7ee8bf CD |
271 | ) |
272 | ||
e013f690 | 273 | #define HAVE_32BIT_GPRS \ |
316f5878 | 274 | (mips_opts.gp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
ca4e0257 | 275 | |
e013f690 | 276 | #define HAVE_32BIT_FPRS \ |
316f5878 | 277 | (mips_opts.fp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
ca4e0257 RS |
278 | |
279 | #define HAVE_64BIT_GPRS (! HAVE_32BIT_GPRS) | |
280 | #define HAVE_64BIT_FPRS (! HAVE_32BIT_FPRS) | |
281 | ||
316f5878 | 282 | #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI) |
e013f690 | 283 | |
316f5878 | 284 | #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI) |
e013f690 | 285 | |
3b91255e RS |
286 | /* True if relocations are stored in-place. */ |
287 | #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI) | |
288 | ||
3e722fb5 | 289 | /* We can only have 64bit addresses if the object file format supports it. */ |
afdbd6d0 CD |
290 | #define HAVE_32BIT_ADDRESSES \ |
291 | (HAVE_32BIT_GPRS \ | |
3e722fb5 CD |
292 | || (bfd_arch_bits_per_address (stdoutput) == 32 \ |
293 | || ! HAVE_64BIT_OBJECTS)) \ | |
e013f690 TS |
294 | |
295 | #define HAVE_64BIT_ADDRESSES (! HAVE_32BIT_ADDRESSES) | |
ca4e0257 | 296 | |
b7c7d6c1 TS |
297 | /* Addresses are loaded in different ways, depending on the address size |
298 | in use. The n32 ABI Documentation also mandates the use of additions | |
299 | with overflow checking, but existing implementations don't follow it. */ | |
f899b4b8 | 300 | #define ADDRESS_ADD_INSN \ |
b7c7d6c1 | 301 | (HAVE_32BIT_ADDRESSES ? "addu" : "daddu") |
f899b4b8 TS |
302 | |
303 | #define ADDRESS_ADDI_INSN \ | |
b7c7d6c1 | 304 | (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu") |
f899b4b8 TS |
305 | |
306 | #define ADDRESS_LOAD_INSN \ | |
307 | (HAVE_32BIT_ADDRESSES ? "lw" : "ld") | |
308 | ||
309 | #define ADDRESS_STORE_INSN \ | |
310 | (HAVE_32BIT_ADDRESSES ? "sw" : "sd") | |
311 | ||
a4672219 | 312 | /* Return true if the given CPU supports the MIPS16 ASE. */ |
3396de36 TS |
313 | #define CPU_HAS_MIPS16(cpu) \ |
314 | (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \ | |
315 | || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0) | |
a4672219 | 316 | |
1f25f5d3 CD |
317 | /* Return true if the given CPU supports the MIPS3D ASE. */ |
318 | #define CPU_HAS_MIPS3D(cpu) ((cpu) == CPU_SB1 \ | |
319 | ) | |
320 | ||
deec1734 | 321 | /* Return true if the given CPU supports the MDMX ASE. */ |
b34976b6 | 322 | #define CPU_HAS_MDMX(cpu) (FALSE \ |
deec1734 CD |
323 | ) |
324 | ||
60b63b72 RS |
325 | /* True if CPU has a dror instruction. */ |
326 | #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500) | |
327 | ||
328 | /* True if CPU has a ror instruction. */ | |
329 | #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU) | |
330 | ||
c8978940 CD |
331 | /* True if mflo and mfhi can be immediately followed by instructions |
332 | which write to the HI and LO registers. | |
333 | ||
334 | According to MIPS specifications, MIPS ISAs I, II, and III need | |
335 | (at least) two instructions between the reads of HI/LO and | |
336 | instructions which write them, and later ISAs do not. Contradicting | |
337 | the MIPS specifications, some MIPS IV processor user manuals (e.g. | |
338 | the UM for the NEC Vr5000) document needing the instructions between | |
339 | HI/LO reads and writes, as well. Therefore, we declare only MIPS32, | |
340 | MIPS64 and later ISAs to have the interlocks, plus any specific | |
341 | earlier-ISA CPUs for which CPU documentation declares that the | |
342 | instructions are really interlocked. */ | |
343 | #define hilo_interlocks \ | |
344 | (mips_opts.isa == ISA_MIPS32 \ | |
345 | || mips_opts.isa == ISA_MIPS32R2 \ | |
346 | || mips_opts.isa == ISA_MIPS64 \ | |
347 | || mips_opts.isa == ISA_MIPS64R2 \ | |
348 | || mips_opts.arch == CPU_R4010 \ | |
349 | || mips_opts.arch == CPU_R10000 \ | |
350 | || mips_opts.arch == CPU_R12000 \ | |
351 | || mips_opts.arch == CPU_RM7000 \ | |
c8978940 CD |
352 | || mips_opts.arch == CPU_VR5500 \ |
353 | ) | |
252b5132 RH |
354 | |
355 | /* Whether the processor uses hardware interlocks to protect reads | |
81912461 ILT |
356 | from the GPRs after they are loaded from memory, and thus does not |
357 | require nops to be inserted. This applies to instructions marked | |
358 | INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA | |
359 | level I. */ | |
252b5132 | 360 | #define gpr_interlocks \ |
e7af610e | 361 | (mips_opts.isa != ISA_MIPS1 \ |
fef14a42 | 362 | || mips_opts.arch == CPU_R3900) |
252b5132 | 363 | |
81912461 ILT |
364 | /* Whether the processor uses hardware interlocks to avoid delays |
365 | required by coprocessor instructions, and thus does not require | |
366 | nops to be inserted. This applies to instructions marked | |
367 | INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays | |
368 | between instructions marked INSN_WRITE_COND_CODE and ones marked | |
369 | INSN_READ_COND_CODE. These nops are only required at MIPS ISA | |
370 | levels I, II, and III. */ | |
bdaaa2e1 | 371 | /* Itbl support may require additional care here. */ |
81912461 ILT |
372 | #define cop_interlocks \ |
373 | ((mips_opts.isa != ISA_MIPS1 \ | |
374 | && mips_opts.isa != ISA_MIPS2 \ | |
375 | && mips_opts.isa != ISA_MIPS3) \ | |
376 | || mips_opts.arch == CPU_R4300 \ | |
81912461 ILT |
377 | ) |
378 | ||
379 | /* Whether the processor uses hardware interlocks to protect reads | |
380 | from coprocessor registers after they are loaded from memory, and | |
381 | thus does not require nops to be inserted. This applies to | |
382 | instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only | |
383 | requires at MIPS ISA level I. */ | |
384 | #define cop_mem_interlocks (mips_opts.isa != ISA_MIPS1) | |
252b5132 | 385 | |
6b76fefe CM |
386 | /* Is this a mfhi or mflo instruction? */ |
387 | #define MF_HILO_INSN(PINFO) \ | |
388 | ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO)) | |
389 | ||
252b5132 RH |
390 | /* MIPS PIC level. */ |
391 | ||
a161fe53 | 392 | enum mips_pic_level mips_pic; |
252b5132 | 393 | |
c9914766 | 394 | /* 1 if we should generate 32 bit offsets from the $gp register in |
252b5132 | 395 | SVR4_PIC mode. Currently has no meaning in other modes. */ |
c9914766 | 396 | static int mips_big_got = 0; |
252b5132 RH |
397 | |
398 | /* 1 if trap instructions should used for overflow rather than break | |
399 | instructions. */ | |
c9914766 | 400 | static int mips_trap = 0; |
252b5132 | 401 | |
119d663a | 402 | /* 1 if double width floating point constants should not be constructed |
b6ff326e | 403 | by assembling two single width halves into two single width floating |
119d663a NC |
404 | point registers which just happen to alias the double width destination |
405 | register. On some architectures this aliasing can be disabled by a bit | |
d547a75e | 406 | in the status register, and the setting of this bit cannot be determined |
119d663a NC |
407 | automatically at assemble time. */ |
408 | static int mips_disable_float_construction; | |
409 | ||
252b5132 RH |
410 | /* Non-zero if any .set noreorder directives were used. */ |
411 | ||
412 | static int mips_any_noreorder; | |
413 | ||
6b76fefe CM |
414 | /* Non-zero if nops should be inserted when the register referenced in |
415 | an mfhi/mflo instruction is read in the next two instructions. */ | |
416 | static int mips_7000_hilo_fix; | |
417 | ||
252b5132 | 418 | /* The size of the small data section. */ |
156c2f8b | 419 | static unsigned int g_switch_value = 8; |
252b5132 RH |
420 | /* Whether the -G option was used. */ |
421 | static int g_switch_seen = 0; | |
422 | ||
423 | #define N_RMASK 0xc4 | |
424 | #define N_VFP 0xd4 | |
425 | ||
426 | /* If we can determine in advance that GP optimization won't be | |
427 | possible, we can skip the relaxation stuff that tries to produce | |
428 | GP-relative references. This makes delay slot optimization work | |
429 | better. | |
430 | ||
431 | This function can only provide a guess, but it seems to work for | |
fba2b7f9 GK |
432 | gcc output. It needs to guess right for gcc, otherwise gcc |
433 | will put what it thinks is a GP-relative instruction in a branch | |
434 | delay slot. | |
252b5132 RH |
435 | |
436 | I don't know if a fix is needed for the SVR4_PIC mode. I've only | |
437 | fixed it for the non-PIC mode. KR 95/04/07 */ | |
17a2f251 | 438 | static int nopic_need_relax (symbolS *, int); |
252b5132 RH |
439 | |
440 | /* handle of the OPCODE hash table */ | |
441 | static struct hash_control *op_hash = NULL; | |
442 | ||
443 | /* The opcode hash table we use for the mips16. */ | |
444 | static struct hash_control *mips16_op_hash = NULL; | |
445 | ||
446 | /* This array holds the chars that always start a comment. If the | |
447 | pre-processor is disabled, these aren't very useful */ | |
448 | const char comment_chars[] = "#"; | |
449 | ||
450 | /* This array holds the chars that only start a comment at the beginning of | |
451 | a line. If the line seems to have the form '# 123 filename' | |
452 | .line and .file directives will appear in the pre-processed output */ | |
453 | /* Note that input_file.c hand checks for '#' at the beginning of the | |
454 | first line of the input file. This is because the compiler outputs | |
bdaaa2e1 | 455 | #NO_APP at the beginning of its output. */ |
252b5132 RH |
456 | /* Also note that C style comments are always supported. */ |
457 | const char line_comment_chars[] = "#"; | |
458 | ||
bdaaa2e1 | 459 | /* This array holds machine specific line separator characters. */ |
63a0b638 | 460 | const char line_separator_chars[] = ";"; |
252b5132 RH |
461 | |
462 | /* Chars that can be used to separate mant from exp in floating point nums */ | |
463 | const char EXP_CHARS[] = "eE"; | |
464 | ||
465 | /* Chars that mean this number is a floating point constant */ | |
466 | /* As in 0f12.456 */ | |
467 | /* or 0d1.2345e12 */ | |
468 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; | |
469 | ||
470 | /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be | |
471 | changed in read.c . Ideally it shouldn't have to know about it at all, | |
472 | but nothing is ideal around here. | |
473 | */ | |
474 | ||
475 | static char *insn_error; | |
476 | ||
477 | static int auto_align = 1; | |
478 | ||
479 | /* When outputting SVR4 PIC code, the assembler needs to know the | |
480 | offset in the stack frame from which to restore the $gp register. | |
481 | This is set by the .cprestore pseudo-op, and saved in this | |
482 | variable. */ | |
483 | static offsetT mips_cprestore_offset = -1; | |
484 | ||
67c1ffbe | 485 | /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some |
6478892d | 486 | more optimizations, it can use a register value instead of a memory-saved |
956cd1d6 | 487 | offset and even an other register than $gp as global pointer. */ |
6478892d TS |
488 | static offsetT mips_cpreturn_offset = -1; |
489 | static int mips_cpreturn_register = -1; | |
490 | static int mips_gp_register = GP; | |
def2e0dd | 491 | static int mips_gprel_offset = 0; |
6478892d | 492 | |
7a621144 DJ |
493 | /* Whether mips_cprestore_offset has been set in the current function |
494 | (or whether it has already been warned about, if not). */ | |
495 | static int mips_cprestore_valid = 0; | |
496 | ||
252b5132 RH |
497 | /* This is the register which holds the stack frame, as set by the |
498 | .frame pseudo-op. This is needed to implement .cprestore. */ | |
499 | static int mips_frame_reg = SP; | |
500 | ||
7a621144 DJ |
501 | /* Whether mips_frame_reg has been set in the current function |
502 | (or whether it has already been warned about, if not). */ | |
503 | static int mips_frame_reg_valid = 0; | |
504 | ||
252b5132 RH |
505 | /* To output NOP instructions correctly, we need to keep information |
506 | about the previous two instructions. */ | |
507 | ||
508 | /* Whether we are optimizing. The default value of 2 means to remove | |
509 | unneeded NOPs and swap branch instructions when possible. A value | |
510 | of 1 means to not swap branches. A value of 0 means to always | |
511 | insert NOPs. */ | |
512 | static int mips_optimize = 2; | |
513 | ||
514 | /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is | |
515 | equivalent to seeing no -g option at all. */ | |
516 | static int mips_debug = 0; | |
517 | ||
518 | /* The previous instruction. */ | |
519 | static struct mips_cl_insn prev_insn; | |
520 | ||
521 | /* The instruction before prev_insn. */ | |
522 | static struct mips_cl_insn prev_prev_insn; | |
523 | ||
524 | /* If we don't want information for prev_insn or prev_prev_insn, we | |
525 | point the insn_mo field at this dummy integer. */ | |
9c6ed8e6 | 526 | static const struct mips_opcode dummy_opcode = { NULL, NULL, 0, 0, 0, 0, 0 }; |
252b5132 RH |
527 | |
528 | /* Non-zero if prev_insn is valid. */ | |
529 | static int prev_insn_valid; | |
530 | ||
531 | /* The frag for the previous instruction. */ | |
532 | static struct frag *prev_insn_frag; | |
533 | ||
534 | /* The offset into prev_insn_frag for the previous instruction. */ | |
535 | static long prev_insn_where; | |
536 | ||
537 | /* The reloc type for the previous instruction, if any. */ | |
f6688943 | 538 | static bfd_reloc_code_real_type prev_insn_reloc_type[3]; |
252b5132 RH |
539 | |
540 | /* The reloc for the previous instruction, if any. */ | |
f6688943 | 541 | static fixS *prev_insn_fixp[3]; |
252b5132 RH |
542 | |
543 | /* Non-zero if the previous instruction was in a delay slot. */ | |
544 | static int prev_insn_is_delay_slot; | |
545 | ||
546 | /* Non-zero if the previous instruction was in a .set noreorder. */ | |
547 | static int prev_insn_unreordered; | |
548 | ||
549 | /* Non-zero if the previous instruction uses an extend opcode (if | |
550 | mips16). */ | |
551 | static int prev_insn_extended; | |
552 | ||
553 | /* Non-zero if the previous previous instruction was in a .set | |
554 | noreorder. */ | |
555 | static int prev_prev_insn_unreordered; | |
556 | ||
557 | /* If this is set, it points to a frag holding nop instructions which | |
558 | were inserted before the start of a noreorder section. If those | |
559 | nops turn out to be unnecessary, the size of the frag can be | |
560 | decreased. */ | |
561 | static fragS *prev_nop_frag; | |
562 | ||
563 | /* The number of nop instructions we created in prev_nop_frag. */ | |
564 | static int prev_nop_frag_holds; | |
565 | ||
566 | /* The number of nop instructions that we know we need in | |
bdaaa2e1 | 567 | prev_nop_frag. */ |
252b5132 RH |
568 | static int prev_nop_frag_required; |
569 | ||
570 | /* The number of instructions we've seen since prev_nop_frag. */ | |
571 | static int prev_nop_frag_since; | |
572 | ||
573 | /* For ECOFF and ELF, relocations against symbols are done in two | |
574 | parts, with a HI relocation and a LO relocation. Each relocation | |
575 | has only 16 bits of space to store an addend. This means that in | |
576 | order for the linker to handle carries correctly, it must be able | |
577 | to locate both the HI and the LO relocation. This means that the | |
578 | relocations must appear in order in the relocation table. | |
579 | ||
580 | In order to implement this, we keep track of each unmatched HI | |
581 | relocation. We then sort them so that they immediately precede the | |
bdaaa2e1 | 582 | corresponding LO relocation. */ |
252b5132 | 583 | |
e972090a NC |
584 | struct mips_hi_fixup |
585 | { | |
252b5132 RH |
586 | /* Next HI fixup. */ |
587 | struct mips_hi_fixup *next; | |
588 | /* This fixup. */ | |
589 | fixS *fixp; | |
590 | /* The section this fixup is in. */ | |
591 | segT seg; | |
592 | }; | |
593 | ||
594 | /* The list of unmatched HI relocs. */ | |
595 | ||
596 | static struct mips_hi_fixup *mips_hi_fixup_list; | |
597 | ||
64bdfcaf RS |
598 | /* The frag containing the last explicit relocation operator. |
599 | Null if explicit relocations have not been used. */ | |
600 | ||
601 | static fragS *prev_reloc_op_frag; | |
602 | ||
252b5132 RH |
603 | /* Map normal MIPS register numbers to mips16 register numbers. */ |
604 | ||
605 | #define X ILLEGAL_REG | |
e972090a NC |
606 | static const int mips32_to_16_reg_map[] = |
607 | { | |
252b5132 RH |
608 | X, X, 2, 3, 4, 5, 6, 7, |
609 | X, X, X, X, X, X, X, X, | |
610 | 0, 1, X, X, X, X, X, X, | |
611 | X, X, X, X, X, X, X, X | |
612 | }; | |
613 | #undef X | |
614 | ||
615 | /* Map mips16 register numbers to normal MIPS register numbers. */ | |
616 | ||
e972090a NC |
617 | static const unsigned int mips16_to_32_reg_map[] = |
618 | { | |
252b5132 RH |
619 | 16, 17, 2, 3, 4, 5, 6, 7 |
620 | }; | |
60b63b72 | 621 | |
d766e8ec | 622 | static int mips_fix_vr4120; |
4a6a3df4 AO |
623 | |
624 | /* We don't relax branches by default, since this causes us to expand | |
625 | `la .l2 - .l1' if there's a branch between .l1 and .l2, because we | |
626 | fail to compute the offset before expanding the macro to the most | |
627 | efficient expansion. */ | |
628 | ||
629 | static int mips_relax_branch; | |
252b5132 | 630 | \f |
4d7206a2 RS |
631 | /* The expansion of many macros depends on the type of symbol that |
632 | they refer to. For example, when generating position-dependent code, | |
633 | a macro that refers to a symbol may have two different expansions, | |
634 | one which uses GP-relative addresses and one which uses absolute | |
635 | addresses. When generating SVR4-style PIC, a macro may have | |
636 | different expansions for local and global symbols. | |
637 | ||
638 | We handle these situations by generating both sequences and putting | |
639 | them in variant frags. In position-dependent code, the first sequence | |
640 | will be the GP-relative one and the second sequence will be the | |
641 | absolute one. In SVR4 PIC, the first sequence will be for global | |
642 | symbols and the second will be for local symbols. | |
643 | ||
584892a6 RS |
644 | The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and |
645 | SECOND are the lengths of the two sequences in bytes. These fields | |
646 | can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition, | |
647 | the subtype has the following flags: | |
4d7206a2 | 648 | |
584892a6 RS |
649 | RELAX_USE_SECOND |
650 | Set if it has been decided that we should use the second | |
651 | sequence instead of the first. | |
652 | ||
653 | RELAX_SECOND_LONGER | |
654 | Set in the first variant frag if the macro's second implementation | |
655 | is longer than its first. This refers to the macro as a whole, | |
656 | not an individual relaxation. | |
657 | ||
658 | RELAX_NOMACRO | |
659 | Set in the first variant frag if the macro appeared in a .set nomacro | |
660 | block and if one alternative requires a warning but the other does not. | |
661 | ||
662 | RELAX_DELAY_SLOT | |
663 | Like RELAX_NOMACRO, but indicates that the macro appears in a branch | |
664 | delay slot. | |
4d7206a2 RS |
665 | |
666 | The frag's "opcode" points to the first fixup for relaxable code. | |
667 | ||
668 | Relaxable macros are generated using a sequence such as: | |
669 | ||
670 | relax_start (SYMBOL); | |
671 | ... generate first expansion ... | |
672 | relax_switch (); | |
673 | ... generate second expansion ... | |
674 | relax_end (); | |
675 | ||
676 | The code and fixups for the unwanted alternative are discarded | |
677 | by md_convert_frag. */ | |
584892a6 | 678 | #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND)) |
4d7206a2 | 679 | |
584892a6 RS |
680 | #define RELAX_FIRST(X) (((X) >> 8) & 0xff) |
681 | #define RELAX_SECOND(X) ((X) & 0xff) | |
682 | #define RELAX_USE_SECOND 0x10000 | |
683 | #define RELAX_SECOND_LONGER 0x20000 | |
684 | #define RELAX_NOMACRO 0x40000 | |
685 | #define RELAX_DELAY_SLOT 0x80000 | |
252b5132 | 686 | |
4a6a3df4 AO |
687 | /* Branch without likely bit. If label is out of range, we turn: |
688 | ||
689 | beq reg1, reg2, label | |
690 | delay slot | |
691 | ||
692 | into | |
693 | ||
694 | bne reg1, reg2, 0f | |
695 | nop | |
696 | j label | |
697 | 0: delay slot | |
698 | ||
699 | with the following opcode replacements: | |
700 | ||
701 | beq <-> bne | |
702 | blez <-> bgtz | |
703 | bltz <-> bgez | |
704 | bc1f <-> bc1t | |
705 | ||
706 | bltzal <-> bgezal (with jal label instead of j label) | |
707 | ||
708 | Even though keeping the delay slot instruction in the delay slot of | |
709 | the branch would be more efficient, it would be very tricky to do | |
710 | correctly, because we'd have to introduce a variable frag *after* | |
711 | the delay slot instruction, and expand that instead. Let's do it | |
712 | the easy way for now, even if the branch-not-taken case now costs | |
713 | one additional instruction. Out-of-range branches are not supposed | |
714 | to be common, anyway. | |
715 | ||
716 | Branch likely. If label is out of range, we turn: | |
717 | ||
718 | beql reg1, reg2, label | |
719 | delay slot (annulled if branch not taken) | |
720 | ||
721 | into | |
722 | ||
723 | beql reg1, reg2, 1f | |
724 | nop | |
725 | beql $0, $0, 2f | |
726 | nop | |
727 | 1: j[al] label | |
728 | delay slot (executed only if branch taken) | |
729 | 2: | |
730 | ||
731 | It would be possible to generate a shorter sequence by losing the | |
732 | likely bit, generating something like: | |
b34976b6 | 733 | |
4a6a3df4 AO |
734 | bne reg1, reg2, 0f |
735 | nop | |
736 | j[al] label | |
737 | delay slot (executed only if branch taken) | |
738 | 0: | |
739 | ||
740 | beql -> bne | |
741 | bnel -> beq | |
742 | blezl -> bgtz | |
743 | bgtzl -> blez | |
744 | bltzl -> bgez | |
745 | bgezl -> bltz | |
746 | bc1fl -> bc1t | |
747 | bc1tl -> bc1f | |
748 | ||
749 | bltzall -> bgezal (with jal label instead of j label) | |
750 | bgezall -> bltzal (ditto) | |
751 | ||
752 | ||
753 | but it's not clear that it would actually improve performance. */ | |
af6ae2ad | 754 | #define RELAX_BRANCH_ENCODE(uncond, likely, link, toofar) \ |
4a6a3df4 AO |
755 | ((relax_substateT) \ |
756 | (0xc0000000 \ | |
757 | | ((toofar) ? 1 : 0) \ | |
758 | | ((link) ? 2 : 0) \ | |
759 | | ((likely) ? 4 : 0) \ | |
af6ae2ad | 760 | | ((uncond) ? 8 : 0))) |
4a6a3df4 | 761 | #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000) |
4a6a3df4 AO |
762 | #define RELAX_BRANCH_UNCOND(i) (((i) & 8) != 0) |
763 | #define RELAX_BRANCH_LIKELY(i) (((i) & 4) != 0) | |
764 | #define RELAX_BRANCH_LINK(i) (((i) & 2) != 0) | |
ae6063d4 | 765 | #define RELAX_BRANCH_TOOFAR(i) (((i) & 1) != 0) |
4a6a3df4 | 766 | |
252b5132 RH |
767 | /* For mips16 code, we use an entirely different form of relaxation. |
768 | mips16 supports two versions of most instructions which take | |
769 | immediate values: a small one which takes some small value, and a | |
770 | larger one which takes a 16 bit value. Since branches also follow | |
771 | this pattern, relaxing these values is required. | |
772 | ||
773 | We can assemble both mips16 and normal MIPS code in a single | |
774 | object. Therefore, we need to support this type of relaxation at | |
775 | the same time that we support the relaxation described above. We | |
776 | use the high bit of the subtype field to distinguish these cases. | |
777 | ||
778 | The information we store for this type of relaxation is the | |
779 | argument code found in the opcode file for this relocation, whether | |
780 | the user explicitly requested a small or extended form, and whether | |
781 | the relocation is in a jump or jal delay slot. That tells us the | |
782 | size of the value, and how it should be stored. We also store | |
783 | whether the fragment is considered to be extended or not. We also | |
784 | store whether this is known to be a branch to a different section, | |
785 | whether we have tried to relax this frag yet, and whether we have | |
786 | ever extended a PC relative fragment because of a shift count. */ | |
787 | #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \ | |
788 | (0x80000000 \ | |
789 | | ((type) & 0xff) \ | |
790 | | ((small) ? 0x100 : 0) \ | |
791 | | ((ext) ? 0x200 : 0) \ | |
792 | | ((dslot) ? 0x400 : 0) \ | |
793 | | ((jal_dslot) ? 0x800 : 0)) | |
4a6a3df4 | 794 | #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000) |
252b5132 RH |
795 | #define RELAX_MIPS16_TYPE(i) ((i) & 0xff) |
796 | #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0) | |
797 | #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0) | |
798 | #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0) | |
799 | #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0) | |
800 | #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0) | |
801 | #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000) | |
802 | #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000) | |
803 | #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0) | |
804 | #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000) | |
805 | #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000) | |
885add95 CD |
806 | |
807 | /* Is the given value a sign-extended 32-bit value? */ | |
808 | #define IS_SEXT_32BIT_NUM(x) \ | |
809 | (((x) &~ (offsetT) 0x7fffffff) == 0 \ | |
810 | || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff)) | |
811 | ||
812 | /* Is the given value a sign-extended 16-bit value? */ | |
813 | #define IS_SEXT_16BIT_NUM(x) \ | |
814 | (((x) &~ (offsetT) 0x7fff) == 0 \ | |
815 | || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff)) | |
816 | ||
4d7206a2 RS |
817 | \f |
818 | /* Global variables used when generating relaxable macros. See the | |
819 | comment above RELAX_ENCODE for more details about how relaxation | |
820 | is used. */ | |
821 | static struct { | |
822 | /* 0 if we're not emitting a relaxable macro. | |
823 | 1 if we're emitting the first of the two relaxation alternatives. | |
824 | 2 if we're emitting the second alternative. */ | |
825 | int sequence; | |
826 | ||
827 | /* The first relaxable fixup in the current frag. (In other words, | |
828 | the first fixup that refers to relaxable code.) */ | |
829 | fixS *first_fixup; | |
830 | ||
831 | /* sizes[0] says how many bytes of the first alternative are stored in | |
832 | the current frag. Likewise sizes[1] for the second alternative. */ | |
833 | unsigned int sizes[2]; | |
834 | ||
835 | /* The symbol on which the choice of sequence depends. */ | |
836 | symbolS *symbol; | |
837 | } mips_relax; | |
252b5132 | 838 | \f |
584892a6 RS |
839 | /* Global variables used to decide whether a macro needs a warning. */ |
840 | static struct { | |
841 | /* True if the macro is in a branch delay slot. */ | |
842 | bfd_boolean delay_slot_p; | |
843 | ||
844 | /* For relaxable macros, sizes[0] is the length of the first alternative | |
845 | in bytes and sizes[1] is the length of the second alternative. | |
846 | For non-relaxable macros, both elements give the length of the | |
847 | macro in bytes. */ | |
848 | unsigned int sizes[2]; | |
849 | ||
850 | /* The first variant frag for this macro. */ | |
851 | fragS *first_frag; | |
852 | } mips_macro_warning; | |
853 | \f | |
252b5132 RH |
854 | /* Prototypes for static functions. */ |
855 | ||
17a2f251 | 856 | #define internalError() \ |
252b5132 | 857 | as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__) |
252b5132 RH |
858 | |
859 | enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG }; | |
860 | ||
b34976b6 | 861 | static void append_insn |
4d7206a2 | 862 | (struct mips_cl_insn *ip, expressionS *p, bfd_reloc_code_real_type *r); |
17a2f251 | 863 | static void mips_no_prev_insn (int); |
b34976b6 | 864 | static void mips16_macro_build |
67c0d1eb RS |
865 | (expressionS *, const char *, const char *, va_list); |
866 | static void load_register (int, expressionS *, int); | |
584892a6 RS |
867 | static void macro_start (void); |
868 | static void macro_end (void); | |
17a2f251 TS |
869 | static void macro (struct mips_cl_insn * ip); |
870 | static void mips16_macro (struct mips_cl_insn * ip); | |
252b5132 | 871 | #ifdef LOSING_COMPILER |
17a2f251 | 872 | static void macro2 (struct mips_cl_insn * ip); |
252b5132 | 873 | #endif |
17a2f251 TS |
874 | static void mips_ip (char *str, struct mips_cl_insn * ip); |
875 | static void mips16_ip (char *str, struct mips_cl_insn * ip); | |
b34976b6 | 876 | static void mips16_immed |
17a2f251 TS |
877 | (char *, unsigned int, int, offsetT, bfd_boolean, bfd_boolean, bfd_boolean, |
878 | unsigned long *, bfd_boolean *, unsigned short *); | |
5e0116d5 | 879 | static size_t my_getSmallExpression |
17a2f251 TS |
880 | (expressionS *, bfd_reloc_code_real_type *, char *); |
881 | static void my_getExpression (expressionS *, char *); | |
882 | static void s_align (int); | |
883 | static void s_change_sec (int); | |
884 | static void s_change_section (int); | |
885 | static void s_cons (int); | |
886 | static void s_float_cons (int); | |
887 | static void s_mips_globl (int); | |
888 | static void s_option (int); | |
889 | static void s_mipsset (int); | |
890 | static void s_abicalls (int); | |
891 | static void s_cpload (int); | |
892 | static void s_cpsetup (int); | |
893 | static void s_cplocal (int); | |
894 | static void s_cprestore (int); | |
895 | static void s_cpreturn (int); | |
896 | static void s_gpvalue (int); | |
897 | static void s_gpword (int); | |
898 | static void s_gpdword (int); | |
899 | static void s_cpadd (int); | |
900 | static void s_insn (int); | |
901 | static void md_obj_begin (void); | |
902 | static void md_obj_end (void); | |
903 | static void s_mips_ent (int); | |
904 | static void s_mips_end (int); | |
905 | static void s_mips_frame (int); | |
906 | static void s_mips_mask (int reg_type); | |
907 | static void s_mips_stab (int); | |
908 | static void s_mips_weakext (int); | |
909 | static void s_mips_file (int); | |
910 | static void s_mips_loc (int); | |
911 | static bfd_boolean pic_need_relax (symbolS *, asection *); | |
4a6a3df4 | 912 | static int relaxed_branch_length (fragS *, asection *, int); |
17a2f251 | 913 | static int validate_mips_insn (const struct mips_opcode *); |
e7af610e NC |
914 | |
915 | /* Table and functions used to map between CPU/ISA names, and | |
916 | ISA levels, and CPU numbers. */ | |
917 | ||
e972090a NC |
918 | struct mips_cpu_info |
919 | { | |
e7af610e NC |
920 | const char *name; /* CPU or ISA name. */ |
921 | int is_isa; /* Is this an ISA? (If 0, a CPU.) */ | |
922 | int isa; /* ISA level. */ | |
923 | int cpu; /* CPU number (default CPU if ISA). */ | |
924 | }; | |
925 | ||
17a2f251 TS |
926 | static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *); |
927 | static const struct mips_cpu_info *mips_cpu_info_from_isa (int); | |
928 | static const struct mips_cpu_info *mips_cpu_info_from_arch (int); | |
252b5132 RH |
929 | \f |
930 | /* Pseudo-op table. | |
931 | ||
932 | The following pseudo-ops from the Kane and Heinrich MIPS book | |
933 | should be defined here, but are currently unsupported: .alias, | |
934 | .galive, .gjaldef, .gjrlive, .livereg, .noalias. | |
935 | ||
936 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
937 | specific to the type of debugging information being generated, and | |
938 | should be defined by the object format: .aent, .begin, .bend, | |
939 | .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp, | |
940 | .vreg. | |
941 | ||
942 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
943 | not MIPS CPU specific, but are also not specific to the object file | |
944 | format. This file is probably the best place to define them, but | |
945 | they are not currently supported: .asm0, .endr, .lab, .repeat, | |
946 | .struct. */ | |
947 | ||
e972090a NC |
948 | static const pseudo_typeS mips_pseudo_table[] = |
949 | { | |
beae10d5 | 950 | /* MIPS specific pseudo-ops. */ |
252b5132 RH |
951 | {"option", s_option, 0}, |
952 | {"set", s_mipsset, 0}, | |
953 | {"rdata", s_change_sec, 'r'}, | |
954 | {"sdata", s_change_sec, 's'}, | |
955 | {"livereg", s_ignore, 0}, | |
956 | {"abicalls", s_abicalls, 0}, | |
957 | {"cpload", s_cpload, 0}, | |
6478892d TS |
958 | {"cpsetup", s_cpsetup, 0}, |
959 | {"cplocal", s_cplocal, 0}, | |
252b5132 | 960 | {"cprestore", s_cprestore, 0}, |
6478892d TS |
961 | {"cpreturn", s_cpreturn, 0}, |
962 | {"gpvalue", s_gpvalue, 0}, | |
252b5132 | 963 | {"gpword", s_gpword, 0}, |
10181a0d | 964 | {"gpdword", s_gpdword, 0}, |
252b5132 RH |
965 | {"cpadd", s_cpadd, 0}, |
966 | {"insn", s_insn, 0}, | |
967 | ||
beae10d5 | 968 | /* Relatively generic pseudo-ops that happen to be used on MIPS |
252b5132 RH |
969 | chips. */ |
970 | {"asciiz", stringer, 1}, | |
971 | {"bss", s_change_sec, 'b'}, | |
972 | {"err", s_err, 0}, | |
973 | {"half", s_cons, 1}, | |
974 | {"dword", s_cons, 3}, | |
975 | {"weakext", s_mips_weakext, 0}, | |
976 | ||
beae10d5 | 977 | /* These pseudo-ops are defined in read.c, but must be overridden |
252b5132 RH |
978 | here for one reason or another. */ |
979 | {"align", s_align, 0}, | |
980 | {"byte", s_cons, 0}, | |
981 | {"data", s_change_sec, 'd'}, | |
982 | {"double", s_float_cons, 'd'}, | |
983 | {"float", s_float_cons, 'f'}, | |
984 | {"globl", s_mips_globl, 0}, | |
985 | {"global", s_mips_globl, 0}, | |
986 | {"hword", s_cons, 1}, | |
987 | {"int", s_cons, 2}, | |
988 | {"long", s_cons, 2}, | |
989 | {"octa", s_cons, 4}, | |
990 | {"quad", s_cons, 3}, | |
cca86cc8 | 991 | {"section", s_change_section, 0}, |
252b5132 RH |
992 | {"short", s_cons, 1}, |
993 | {"single", s_float_cons, 'f'}, | |
994 | {"stabn", s_mips_stab, 'n'}, | |
995 | {"text", s_change_sec, 't'}, | |
996 | {"word", s_cons, 2}, | |
add56521 | 997 | |
add56521 | 998 | { "extern", ecoff_directive_extern, 0}, |
add56521 | 999 | |
43841e91 | 1000 | { NULL, NULL, 0 }, |
252b5132 RH |
1001 | }; |
1002 | ||
e972090a NC |
1003 | static const pseudo_typeS mips_nonecoff_pseudo_table[] = |
1004 | { | |
beae10d5 KH |
1005 | /* These pseudo-ops should be defined by the object file format. |
1006 | However, a.out doesn't support them, so we have versions here. */ | |
252b5132 RH |
1007 | {"aent", s_mips_ent, 1}, |
1008 | {"bgnb", s_ignore, 0}, | |
1009 | {"end", s_mips_end, 0}, | |
1010 | {"endb", s_ignore, 0}, | |
1011 | {"ent", s_mips_ent, 0}, | |
c5dd6aab | 1012 | {"file", s_mips_file, 0}, |
252b5132 RH |
1013 | {"fmask", s_mips_mask, 'F'}, |
1014 | {"frame", s_mips_frame, 0}, | |
c5dd6aab | 1015 | {"loc", s_mips_loc, 0}, |
252b5132 RH |
1016 | {"mask", s_mips_mask, 'R'}, |
1017 | {"verstamp", s_ignore, 0}, | |
43841e91 | 1018 | { NULL, NULL, 0 }, |
252b5132 RH |
1019 | }; |
1020 | ||
17a2f251 | 1021 | extern void pop_insert (const pseudo_typeS *); |
252b5132 RH |
1022 | |
1023 | void | |
17a2f251 | 1024 | mips_pop_insert (void) |
252b5132 RH |
1025 | { |
1026 | pop_insert (mips_pseudo_table); | |
1027 | if (! ECOFF_DEBUGGING) | |
1028 | pop_insert (mips_nonecoff_pseudo_table); | |
1029 | } | |
1030 | \f | |
1031 | /* Symbols labelling the current insn. */ | |
1032 | ||
e972090a NC |
1033 | struct insn_label_list |
1034 | { | |
252b5132 RH |
1035 | struct insn_label_list *next; |
1036 | symbolS *label; | |
1037 | }; | |
1038 | ||
1039 | static struct insn_label_list *insn_labels; | |
1040 | static struct insn_label_list *free_insn_labels; | |
1041 | ||
17a2f251 | 1042 | static void mips_clear_insn_labels (void); |
252b5132 RH |
1043 | |
1044 | static inline void | |
17a2f251 | 1045 | mips_clear_insn_labels (void) |
252b5132 RH |
1046 | { |
1047 | register struct insn_label_list **pl; | |
1048 | ||
1049 | for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next) | |
1050 | ; | |
1051 | *pl = insn_labels; | |
1052 | insn_labels = NULL; | |
1053 | } | |
1054 | \f | |
1055 | static char *expr_end; | |
1056 | ||
1057 | /* Expressions which appear in instructions. These are set by | |
1058 | mips_ip. */ | |
1059 | ||
1060 | static expressionS imm_expr; | |
5f74bc13 | 1061 | static expressionS imm2_expr; |
252b5132 RH |
1062 | static expressionS offset_expr; |
1063 | ||
1064 | /* Relocs associated with imm_expr and offset_expr. */ | |
1065 | ||
f6688943 TS |
1066 | static bfd_reloc_code_real_type imm_reloc[3] |
1067 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
1068 | static bfd_reloc_code_real_type offset_reloc[3] | |
1069 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 1070 | |
252b5132 RH |
1071 | /* These are set by mips16_ip if an explicit extension is used. */ |
1072 | ||
b34976b6 | 1073 | static bfd_boolean mips16_small, mips16_ext; |
252b5132 | 1074 | |
7ed4a06a | 1075 | #ifdef OBJ_ELF |
ecb4347a DJ |
1076 | /* The pdr segment for per procedure frame/regmask info. Not used for |
1077 | ECOFF debugging. */ | |
252b5132 RH |
1078 | |
1079 | static segT pdr_seg; | |
7ed4a06a | 1080 | #endif |
252b5132 | 1081 | |
e013f690 TS |
1082 | /* The default target format to use. */ |
1083 | ||
1084 | const char * | |
17a2f251 | 1085 | mips_target_format (void) |
e013f690 TS |
1086 | { |
1087 | switch (OUTPUT_FLAVOR) | |
1088 | { | |
e013f690 TS |
1089 | case bfd_target_ecoff_flavour: |
1090 | return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT; | |
1091 | case bfd_target_coff_flavour: | |
1092 | return "pe-mips"; | |
1093 | case bfd_target_elf_flavour: | |
1094 | #ifdef TE_TMIPS | |
cfe86eaa | 1095 | /* This is traditional mips. */ |
e013f690 | 1096 | return (target_big_endian |
cfe86eaa TS |
1097 | ? (HAVE_64BIT_OBJECTS |
1098 | ? "elf64-tradbigmips" | |
1099 | : (HAVE_NEWABI | |
1100 | ? "elf32-ntradbigmips" : "elf32-tradbigmips")) | |
1101 | : (HAVE_64BIT_OBJECTS | |
1102 | ? "elf64-tradlittlemips" | |
1103 | : (HAVE_NEWABI | |
1104 | ? "elf32-ntradlittlemips" : "elf32-tradlittlemips"))); | |
e013f690 TS |
1105 | #else |
1106 | return (target_big_endian | |
cfe86eaa TS |
1107 | ? (HAVE_64BIT_OBJECTS |
1108 | ? "elf64-bigmips" | |
1109 | : (HAVE_NEWABI | |
1110 | ? "elf32-nbigmips" : "elf32-bigmips")) | |
1111 | : (HAVE_64BIT_OBJECTS | |
1112 | ? "elf64-littlemips" | |
1113 | : (HAVE_NEWABI | |
1114 | ? "elf32-nlittlemips" : "elf32-littlemips"))); | |
e013f690 TS |
1115 | #endif |
1116 | default: | |
1117 | abort (); | |
1118 | return NULL; | |
1119 | } | |
1120 | } | |
1121 | ||
156c2f8b NC |
1122 | /* This function is called once, at assembler startup time. It should |
1123 | set up all the tables, etc. that the MD part of the assembler will need. */ | |
1124 | ||
252b5132 | 1125 | void |
17a2f251 | 1126 | md_begin (void) |
252b5132 | 1127 | { |
252b5132 | 1128 | register const char *retval = NULL; |
156c2f8b | 1129 | int i = 0; |
252b5132 | 1130 | int broken = 0; |
1f25f5d3 | 1131 | |
fef14a42 | 1132 | if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_arch)) |
252b5132 RH |
1133 | as_warn (_("Could not set architecture and machine")); |
1134 | ||
252b5132 RH |
1135 | op_hash = hash_new (); |
1136 | ||
1137 | for (i = 0; i < NUMOPCODES;) | |
1138 | { | |
1139 | const char *name = mips_opcodes[i].name; | |
1140 | ||
17a2f251 | 1141 | retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]); |
252b5132 RH |
1142 | if (retval != NULL) |
1143 | { | |
1144 | fprintf (stderr, _("internal error: can't hash `%s': %s\n"), | |
1145 | mips_opcodes[i].name, retval); | |
1146 | /* Probably a memory allocation problem? Give up now. */ | |
1147 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
1148 | } | |
1149 | do | |
1150 | { | |
1151 | if (mips_opcodes[i].pinfo != INSN_MACRO) | |
1152 | { | |
1153 | if (!validate_mips_insn (&mips_opcodes[i])) | |
1154 | broken = 1; | |
1155 | } | |
1156 | ++i; | |
1157 | } | |
1158 | while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name)); | |
1159 | } | |
1160 | ||
1161 | mips16_op_hash = hash_new (); | |
1162 | ||
1163 | i = 0; | |
1164 | while (i < bfd_mips16_num_opcodes) | |
1165 | { | |
1166 | const char *name = mips16_opcodes[i].name; | |
1167 | ||
17a2f251 | 1168 | retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]); |
252b5132 RH |
1169 | if (retval != NULL) |
1170 | as_fatal (_("internal: can't hash `%s': %s"), | |
1171 | mips16_opcodes[i].name, retval); | |
1172 | do | |
1173 | { | |
1174 | if (mips16_opcodes[i].pinfo != INSN_MACRO | |
1175 | && ((mips16_opcodes[i].match & mips16_opcodes[i].mask) | |
1176 | != mips16_opcodes[i].match)) | |
1177 | { | |
1178 | fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"), | |
1179 | mips16_opcodes[i].name, mips16_opcodes[i].args); | |
1180 | broken = 1; | |
1181 | } | |
1182 | ++i; | |
1183 | } | |
1184 | while (i < bfd_mips16_num_opcodes | |
1185 | && strcmp (mips16_opcodes[i].name, name) == 0); | |
1186 | } | |
1187 | ||
1188 | if (broken) | |
1189 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
1190 | ||
1191 | /* We add all the general register names to the symbol table. This | |
1192 | helps us detect invalid uses of them. */ | |
1193 | for (i = 0; i < 32; i++) | |
1194 | { | |
1195 | char buf[5]; | |
1196 | ||
1197 | sprintf (buf, "$%d", i); | |
1198 | symbol_table_insert (symbol_new (buf, reg_section, i, | |
1199 | &zero_address_frag)); | |
1200 | } | |
76db943d TS |
1201 | symbol_table_insert (symbol_new ("$ra", reg_section, RA, |
1202 | &zero_address_frag)); | |
252b5132 RH |
1203 | symbol_table_insert (symbol_new ("$fp", reg_section, FP, |
1204 | &zero_address_frag)); | |
1205 | symbol_table_insert (symbol_new ("$sp", reg_section, SP, | |
1206 | &zero_address_frag)); | |
1207 | symbol_table_insert (symbol_new ("$gp", reg_section, GP, | |
1208 | &zero_address_frag)); | |
1209 | symbol_table_insert (symbol_new ("$at", reg_section, AT, | |
1210 | &zero_address_frag)); | |
1211 | symbol_table_insert (symbol_new ("$kt0", reg_section, KT0, | |
1212 | &zero_address_frag)); | |
1213 | symbol_table_insert (symbol_new ("$kt1", reg_section, KT1, | |
1214 | &zero_address_frag)); | |
85b51719 TS |
1215 | symbol_table_insert (symbol_new ("$zero", reg_section, ZERO, |
1216 | &zero_address_frag)); | |
252b5132 RH |
1217 | symbol_table_insert (symbol_new ("$pc", reg_section, -1, |
1218 | &zero_address_frag)); | |
1219 | ||
6047c971 AO |
1220 | /* If we don't add these register names to the symbol table, they |
1221 | may end up being added as regular symbols by operand(), and then | |
1222 | make it to the object file as undefined in case they're not | |
1223 | regarded as local symbols. They're local in o32, since `$' is a | |
1224 | local symbol prefix, but not in n32 or n64. */ | |
1225 | for (i = 0; i < 8; i++) | |
1226 | { | |
1227 | char buf[6]; | |
1228 | ||
1229 | sprintf (buf, "$fcc%i", i); | |
1230 | symbol_table_insert (symbol_new (buf, reg_section, -1, | |
1231 | &zero_address_frag)); | |
1232 | } | |
1233 | ||
b34976b6 | 1234 | mips_no_prev_insn (FALSE); |
252b5132 RH |
1235 | |
1236 | mips_gprmask = 0; | |
1237 | mips_cprmask[0] = 0; | |
1238 | mips_cprmask[1] = 0; | |
1239 | mips_cprmask[2] = 0; | |
1240 | mips_cprmask[3] = 0; | |
1241 | ||
1242 | /* set the default alignment for the text section (2**2) */ | |
1243 | record_alignment (text_section, 2); | |
1244 | ||
4d0d148d | 1245 | bfd_set_gp_size (stdoutput, g_switch_value); |
252b5132 RH |
1246 | |
1247 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
1248 | { | |
1249 | /* On a native system, sections must be aligned to 16 byte | |
1250 | boundaries. When configured for an embedded ELF target, we | |
1251 | don't bother. */ | |
1252 | if (strcmp (TARGET_OS, "elf") != 0) | |
1253 | { | |
1254 | (void) bfd_set_section_alignment (stdoutput, text_section, 4); | |
1255 | (void) bfd_set_section_alignment (stdoutput, data_section, 4); | |
1256 | (void) bfd_set_section_alignment (stdoutput, bss_section, 4); | |
1257 | } | |
1258 | ||
1259 | /* Create a .reginfo section for register masks and a .mdebug | |
1260 | section for debugging information. */ | |
1261 | { | |
1262 | segT seg; | |
1263 | subsegT subseg; | |
1264 | flagword flags; | |
1265 | segT sec; | |
1266 | ||
1267 | seg = now_seg; | |
1268 | subseg = now_subseg; | |
1269 | ||
1270 | /* The ABI says this section should be loaded so that the | |
1271 | running program can access it. However, we don't load it | |
1272 | if we are configured for an embedded target */ | |
1273 | flags = SEC_READONLY | SEC_DATA; | |
1274 | if (strcmp (TARGET_OS, "elf") != 0) | |
1275 | flags |= SEC_ALLOC | SEC_LOAD; | |
1276 | ||
316f5878 | 1277 | if (mips_abi != N64_ABI) |
252b5132 RH |
1278 | { |
1279 | sec = subseg_new (".reginfo", (subsegT) 0); | |
1280 | ||
195325d2 TS |
1281 | bfd_set_section_flags (stdoutput, sec, flags); |
1282 | bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2); | |
bdaaa2e1 | 1283 | |
252b5132 RH |
1284 | #ifdef OBJ_ELF |
1285 | mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo)); | |
1286 | #endif | |
1287 | } | |
1288 | else | |
1289 | { | |
1290 | /* The 64-bit ABI uses a .MIPS.options section rather than | |
1291 | .reginfo section. */ | |
1292 | sec = subseg_new (".MIPS.options", (subsegT) 0); | |
195325d2 TS |
1293 | bfd_set_section_flags (stdoutput, sec, flags); |
1294 | bfd_set_section_alignment (stdoutput, sec, 3); | |
252b5132 RH |
1295 | |
1296 | #ifdef OBJ_ELF | |
1297 | /* Set up the option header. */ | |
1298 | { | |
1299 | Elf_Internal_Options opthdr; | |
1300 | char *f; | |
1301 | ||
1302 | opthdr.kind = ODK_REGINFO; | |
1303 | opthdr.size = (sizeof (Elf_External_Options) | |
1304 | + sizeof (Elf64_External_RegInfo)); | |
1305 | opthdr.section = 0; | |
1306 | opthdr.info = 0; | |
1307 | f = frag_more (sizeof (Elf_External_Options)); | |
1308 | bfd_mips_elf_swap_options_out (stdoutput, &opthdr, | |
1309 | (Elf_External_Options *) f); | |
1310 | ||
1311 | mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo)); | |
1312 | } | |
1313 | #endif | |
1314 | } | |
1315 | ||
1316 | if (ECOFF_DEBUGGING) | |
1317 | { | |
1318 | sec = subseg_new (".mdebug", (subsegT) 0); | |
1319 | (void) bfd_set_section_flags (stdoutput, sec, | |
1320 | SEC_HAS_CONTENTS | SEC_READONLY); | |
1321 | (void) bfd_set_section_alignment (stdoutput, sec, 2); | |
1322 | } | |
ecb4347a | 1323 | #ifdef OBJ_ELF |
dcd410fe | 1324 | else if (OUTPUT_FLAVOR == bfd_target_elf_flavour && mips_flag_pdr) |
ecb4347a DJ |
1325 | { |
1326 | pdr_seg = subseg_new (".pdr", (subsegT) 0); | |
1327 | (void) bfd_set_section_flags (stdoutput, pdr_seg, | |
1328 | SEC_READONLY | SEC_RELOC | |
1329 | | SEC_DEBUGGING); | |
1330 | (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2); | |
1331 | } | |
252b5132 RH |
1332 | #endif |
1333 | ||
1334 | subseg_set (seg, subseg); | |
1335 | } | |
1336 | } | |
1337 | ||
1338 | if (! ECOFF_DEBUGGING) | |
1339 | md_obj_begin (); | |
1340 | } | |
1341 | ||
1342 | void | |
17a2f251 | 1343 | md_mips_end (void) |
252b5132 RH |
1344 | { |
1345 | if (! ECOFF_DEBUGGING) | |
1346 | md_obj_end (); | |
1347 | } | |
1348 | ||
1349 | void | |
17a2f251 | 1350 | md_assemble (char *str) |
252b5132 RH |
1351 | { |
1352 | struct mips_cl_insn insn; | |
f6688943 TS |
1353 | bfd_reloc_code_real_type unused_reloc[3] |
1354 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 RH |
1355 | |
1356 | imm_expr.X_op = O_absent; | |
5f74bc13 | 1357 | imm2_expr.X_op = O_absent; |
252b5132 | 1358 | offset_expr.X_op = O_absent; |
f6688943 TS |
1359 | imm_reloc[0] = BFD_RELOC_UNUSED; |
1360 | imm_reloc[1] = BFD_RELOC_UNUSED; | |
1361 | imm_reloc[2] = BFD_RELOC_UNUSED; | |
1362 | offset_reloc[0] = BFD_RELOC_UNUSED; | |
1363 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
1364 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
1365 | |
1366 | if (mips_opts.mips16) | |
1367 | mips16_ip (str, &insn); | |
1368 | else | |
1369 | { | |
1370 | mips_ip (str, &insn); | |
beae10d5 KH |
1371 | DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"), |
1372 | str, insn.insn_opcode)); | |
252b5132 RH |
1373 | } |
1374 | ||
1375 | if (insn_error) | |
1376 | { | |
1377 | as_bad ("%s `%s'", insn_error, str); | |
1378 | return; | |
1379 | } | |
1380 | ||
1381 | if (insn.insn_mo->pinfo == INSN_MACRO) | |
1382 | { | |
584892a6 | 1383 | macro_start (); |
252b5132 RH |
1384 | if (mips_opts.mips16) |
1385 | mips16_macro (&insn); | |
1386 | else | |
1387 | macro (&insn); | |
584892a6 | 1388 | macro_end (); |
252b5132 RH |
1389 | } |
1390 | else | |
1391 | { | |
1392 | if (imm_expr.X_op != O_absent) | |
4d7206a2 | 1393 | append_insn (&insn, &imm_expr, imm_reloc); |
252b5132 | 1394 | else if (offset_expr.X_op != O_absent) |
4d7206a2 | 1395 | append_insn (&insn, &offset_expr, offset_reloc); |
252b5132 | 1396 | else |
4d7206a2 | 1397 | append_insn (&insn, NULL, unused_reloc); |
252b5132 RH |
1398 | } |
1399 | } | |
1400 | ||
5919d012 RS |
1401 | /* Return true if the given relocation might need a matching %lo(). |
1402 | Note that R_MIPS_GOT16 relocations only need a matching %lo() when | |
1403 | applied to local symbols. */ | |
1404 | ||
1405 | static inline bfd_boolean | |
17a2f251 | 1406 | reloc_needs_lo_p (bfd_reloc_code_real_type reloc) |
5919d012 | 1407 | { |
3b91255e RS |
1408 | return (HAVE_IN_PLACE_ADDENDS |
1409 | && (reloc == BFD_RELOC_HI16_S | |
d6f16593 MR |
1410 | || reloc == BFD_RELOC_MIPS_GOT16 |
1411 | || reloc == BFD_RELOC_MIPS16_HI16_S)); | |
5919d012 RS |
1412 | } |
1413 | ||
1414 | /* Return true if the given fixup is followed by a matching R_MIPS_LO16 | |
1415 | relocation. */ | |
1416 | ||
1417 | static inline bfd_boolean | |
17a2f251 | 1418 | fixup_has_matching_lo_p (fixS *fixp) |
5919d012 RS |
1419 | { |
1420 | return (fixp->fx_next != NULL | |
d6f16593 MR |
1421 | && (fixp->fx_next->fx_r_type == BFD_RELOC_LO16 |
1422 | || fixp->fx_next->fx_r_type == BFD_RELOC_MIPS16_LO16) | |
5919d012 RS |
1423 | && fixp->fx_addsy == fixp->fx_next->fx_addsy |
1424 | && fixp->fx_offset == fixp->fx_next->fx_offset); | |
1425 | } | |
1426 | ||
252b5132 RH |
1427 | /* See whether instruction IP reads register REG. CLASS is the type |
1428 | of register. */ | |
1429 | ||
1430 | static int | |
17a2f251 TS |
1431 | insn_uses_reg (struct mips_cl_insn *ip, unsigned int reg, |
1432 | enum mips_regclass class) | |
252b5132 RH |
1433 | { |
1434 | if (class == MIPS16_REG) | |
1435 | { | |
1436 | assert (mips_opts.mips16); | |
1437 | reg = mips16_to_32_reg_map[reg]; | |
1438 | class = MIPS_GR_REG; | |
1439 | } | |
1440 | ||
85b51719 TS |
1441 | /* Don't report on general register ZERO, since it never changes. */ |
1442 | if (class == MIPS_GR_REG && reg == ZERO) | |
252b5132 RH |
1443 | return 0; |
1444 | ||
1445 | if (class == MIPS_FP_REG) | |
1446 | { | |
1447 | assert (! mips_opts.mips16); | |
1448 | /* If we are called with either $f0 or $f1, we must check $f0. | |
1449 | This is not optimal, because it will introduce an unnecessary | |
1450 | NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would | |
1451 | need to distinguish reading both $f0 and $f1 or just one of | |
1452 | them. Note that we don't have to check the other way, | |
1453 | because there is no instruction that sets both $f0 and $f1 | |
1454 | and requires a delay. */ | |
1455 | if ((ip->insn_mo->pinfo & INSN_READ_FPR_S) | |
1456 | && ((((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS) &~(unsigned)1) | |
1457 | == (reg &~ (unsigned) 1))) | |
1458 | return 1; | |
1459 | if ((ip->insn_mo->pinfo & INSN_READ_FPR_T) | |
1460 | && ((((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT) &~(unsigned)1) | |
1461 | == (reg &~ (unsigned) 1))) | |
1462 | return 1; | |
1463 | } | |
1464 | else if (! mips_opts.mips16) | |
1465 | { | |
1466 | if ((ip->insn_mo->pinfo & INSN_READ_GPR_S) | |
1467 | && ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == reg) | |
1468 | return 1; | |
1469 | if ((ip->insn_mo->pinfo & INSN_READ_GPR_T) | |
1470 | && ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT) == reg) | |
1471 | return 1; | |
1472 | } | |
1473 | else | |
1474 | { | |
1475 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_X) | |
1476 | && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_RX) | |
1477 | & MIPS16OP_MASK_RX)] | |
1478 | == reg)) | |
1479 | return 1; | |
1480 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Y) | |
1481 | && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_RY) | |
1482 | & MIPS16OP_MASK_RY)] | |
1483 | == reg)) | |
1484 | return 1; | |
1485 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Z) | |
1486 | && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z) | |
1487 | & MIPS16OP_MASK_MOVE32Z)] | |
1488 | == reg)) | |
1489 | return 1; | |
1490 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_T) && reg == TREG) | |
1491 | return 1; | |
1492 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_SP) && reg == SP) | |
1493 | return 1; | |
1494 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_31) && reg == RA) | |
1495 | return 1; | |
1496 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_GPR_X) | |
1497 | && ((ip->insn_opcode >> MIPS16OP_SH_REGR32) | |
1498 | & MIPS16OP_MASK_REGR32) == reg) | |
1499 | return 1; | |
1500 | } | |
1501 | ||
1502 | return 0; | |
1503 | } | |
1504 | ||
1505 | /* This function returns true if modifying a register requires a | |
1506 | delay. */ | |
1507 | ||
1508 | static int | |
17a2f251 | 1509 | reg_needs_delay (unsigned int reg) |
252b5132 RH |
1510 | { |
1511 | unsigned long prev_pinfo; | |
1512 | ||
1513 | prev_pinfo = prev_insn.insn_mo->pinfo; | |
1514 | if (! mips_opts.noreorder | |
81912461 ILT |
1515 | && (((prev_pinfo & INSN_LOAD_MEMORY_DELAY) |
1516 | && ! gpr_interlocks) | |
1517 | || ((prev_pinfo & INSN_LOAD_COPROC_DELAY) | |
1518 | && ! cop_interlocks))) | |
252b5132 | 1519 | { |
81912461 ILT |
1520 | /* A load from a coprocessor or from memory. All load delays |
1521 | delay the use of general register rt for one instruction. */ | |
bdaaa2e1 | 1522 | /* Itbl support may require additional care here. */ |
252b5132 RH |
1523 | know (prev_pinfo & INSN_WRITE_GPR_T); |
1524 | if (reg == ((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT)) | |
1525 | return 1; | |
1526 | } | |
1527 | ||
1528 | return 0; | |
1529 | } | |
1530 | ||
1531 | /* Mark instruction labels in mips16 mode. This permits the linker to | |
1532 | handle them specially, such as generating jalx instructions when | |
1533 | needed. We also make them odd for the duration of the assembly, in | |
1534 | order to generate the right sort of code. We will make them even | |
1535 | in the adjust_symtab routine, while leaving them marked. This is | |
1536 | convenient for the debugger and the disassembler. The linker knows | |
1537 | to make them odd again. */ | |
1538 | ||
1539 | static void | |
17a2f251 | 1540 | mips16_mark_labels (void) |
252b5132 RH |
1541 | { |
1542 | if (mips_opts.mips16) | |
1543 | { | |
1544 | struct insn_label_list *l; | |
98aa84af | 1545 | valueT val; |
252b5132 RH |
1546 | |
1547 | for (l = insn_labels; l != NULL; l = l->next) | |
1548 | { | |
1549 | #ifdef OBJ_ELF | |
1550 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
1551 | S_SET_OTHER (l->label, STO_MIPS16); | |
1552 | #endif | |
98aa84af AM |
1553 | val = S_GET_VALUE (l->label); |
1554 | if ((val & 1) == 0) | |
1555 | S_SET_VALUE (l->label, val + 1); | |
252b5132 RH |
1556 | } |
1557 | } | |
1558 | } | |
1559 | ||
4d7206a2 RS |
1560 | /* End the current frag. Make it a variant frag and record the |
1561 | relaxation info. */ | |
1562 | ||
1563 | static void | |
1564 | relax_close_frag (void) | |
1565 | { | |
584892a6 | 1566 | mips_macro_warning.first_frag = frag_now; |
4d7206a2 | 1567 | frag_var (rs_machine_dependent, 0, 0, |
584892a6 | 1568 | RELAX_ENCODE (mips_relax.sizes[0], mips_relax.sizes[1]), |
4d7206a2 RS |
1569 | mips_relax.symbol, 0, (char *) mips_relax.first_fixup); |
1570 | ||
1571 | memset (&mips_relax.sizes, 0, sizeof (mips_relax.sizes)); | |
1572 | mips_relax.first_fixup = 0; | |
1573 | } | |
1574 | ||
1575 | /* Start a new relaxation sequence whose expansion depends on SYMBOL. | |
1576 | See the comment above RELAX_ENCODE for more details. */ | |
1577 | ||
1578 | static void | |
1579 | relax_start (symbolS *symbol) | |
1580 | { | |
1581 | assert (mips_relax.sequence == 0); | |
1582 | mips_relax.sequence = 1; | |
1583 | mips_relax.symbol = symbol; | |
1584 | } | |
1585 | ||
1586 | /* Start generating the second version of a relaxable sequence. | |
1587 | See the comment above RELAX_ENCODE for more details. */ | |
252b5132 RH |
1588 | |
1589 | static void | |
4d7206a2 RS |
1590 | relax_switch (void) |
1591 | { | |
1592 | assert (mips_relax.sequence == 1); | |
1593 | mips_relax.sequence = 2; | |
1594 | } | |
1595 | ||
1596 | /* End the current relaxable sequence. */ | |
1597 | ||
1598 | static void | |
1599 | relax_end (void) | |
1600 | { | |
1601 | assert (mips_relax.sequence == 2); | |
1602 | relax_close_frag (); | |
1603 | mips_relax.sequence = 0; | |
1604 | } | |
1605 | ||
1606 | /* Output an instruction. IP is the instruction information. | |
1607 | ADDRESS_EXPR is an operand of the instruction to be used with | |
1608 | RELOC_TYPE. */ | |
1609 | ||
1610 | static void | |
1611 | append_insn (struct mips_cl_insn *ip, expressionS *address_expr, | |
17a2f251 | 1612 | bfd_reloc_code_real_type *reloc_type) |
252b5132 RH |
1613 | { |
1614 | register unsigned long prev_pinfo, pinfo; | |
1615 | char *f; | |
f6688943 | 1616 | fixS *fixp[3]; |
252b5132 | 1617 | int nops = 0; |
895921c9 MR |
1618 | relax_stateT prev_insn_frag_type = 0; |
1619 | bfd_boolean relaxed_branch = FALSE; | |
f5040a92 | 1620 | bfd_boolean force_new_frag = FALSE; |
252b5132 RH |
1621 | |
1622 | /* Mark instruction labels in mips16 mode. */ | |
f9419b05 | 1623 | mips16_mark_labels (); |
252b5132 RH |
1624 | |
1625 | prev_pinfo = prev_insn.insn_mo->pinfo; | |
1626 | pinfo = ip->insn_mo->pinfo; | |
1627 | ||
4d7206a2 RS |
1628 | if (mips_relax.sequence != 2 |
1629 | && (!mips_opts.noreorder || prev_nop_frag != NULL)) | |
252b5132 RH |
1630 | { |
1631 | int prev_prev_nop; | |
1632 | ||
1633 | /* If the previous insn required any delay slots, see if we need | |
1634 | to insert a NOP or two. There are eight kinds of possible | |
1635 | hazards, of which an instruction can have at most one type. | |
1636 | (1) a load from memory delay | |
1637 | (2) a load from a coprocessor delay | |
1638 | (3) an unconditional branch delay | |
1639 | (4) a conditional branch delay | |
1640 | (5) a move to coprocessor register delay | |
1641 | (6) a load coprocessor register from memory delay | |
1642 | (7) a coprocessor condition code delay | |
1643 | (8) a HI/LO special register delay | |
1644 | ||
1645 | There are a lot of optimizations we could do that we don't. | |
1646 | In particular, we do not, in general, reorder instructions. | |
1647 | If you use gcc with optimization, it will reorder | |
1648 | instructions and generally do much more optimization then we | |
1649 | do here; repeating all that work in the assembler would only | |
1650 | benefit hand written assembly code, and does not seem worth | |
1651 | it. */ | |
1652 | ||
1653 | /* This is how a NOP is emitted. */ | |
1654 | #define emit_nop() \ | |
1655 | (mips_opts.mips16 \ | |
1656 | ? md_number_to_chars (frag_more (2), 0x6500, 2) \ | |
1657 | : md_number_to_chars (frag_more (4), 0, 4)) | |
1658 | ||
1659 | /* The previous insn might require a delay slot, depending upon | |
1660 | the contents of the current insn. */ | |
1661 | if (! mips_opts.mips16 | |
81912461 ILT |
1662 | && (((prev_pinfo & INSN_LOAD_MEMORY_DELAY) |
1663 | && ! gpr_interlocks) | |
1664 | || ((prev_pinfo & INSN_LOAD_COPROC_DELAY) | |
1665 | && ! cop_interlocks))) | |
252b5132 RH |
1666 | { |
1667 | /* A load from a coprocessor or from memory. All load | |
1668 | delays delay the use of general register rt for one | |
81912461 | 1669 | instruction. */ |
beae10d5 | 1670 | /* Itbl support may require additional care here. */ |
252b5132 RH |
1671 | know (prev_pinfo & INSN_WRITE_GPR_T); |
1672 | if (mips_optimize == 0 | |
1673 | || insn_uses_reg (ip, | |
1674 | ((prev_insn.insn_opcode >> OP_SH_RT) | |
1675 | & OP_MASK_RT), | |
1676 | MIPS_GR_REG)) | |
1677 | ++nops; | |
1678 | } | |
1679 | else if (! mips_opts.mips16 | |
252b5132 | 1680 | && (((prev_pinfo & INSN_COPROC_MOVE_DELAY) |
beae10d5 | 1681 | && ! cop_interlocks) |
81912461 ILT |
1682 | || ((prev_pinfo & INSN_COPROC_MEMORY_DELAY) |
1683 | && ! cop_mem_interlocks))) | |
252b5132 RH |
1684 | { |
1685 | /* A generic coprocessor delay. The previous instruction | |
1686 | modified a coprocessor general or control register. If | |
1687 | it modified a control register, we need to avoid any | |
1688 | coprocessor instruction (this is probably not always | |
1689 | required, but it sometimes is). If it modified a general | |
1690 | register, we avoid using that register. | |
1691 | ||
252b5132 RH |
1692 | This case is not handled very well. There is no special |
1693 | knowledge of CP0 handling, and the coprocessors other | |
1694 | than the floating point unit are not distinguished at | |
1695 | all. */ | |
1696 | /* Itbl support may require additional care here. FIXME! | |
bdaaa2e1 | 1697 | Need to modify this to include knowledge about |
252b5132 RH |
1698 | user specified delays! */ |
1699 | if (prev_pinfo & INSN_WRITE_FPR_T) | |
1700 | { | |
1701 | if (mips_optimize == 0 | |
1702 | || insn_uses_reg (ip, | |
1703 | ((prev_insn.insn_opcode >> OP_SH_FT) | |
1704 | & OP_MASK_FT), | |
1705 | MIPS_FP_REG)) | |
1706 | ++nops; | |
1707 | } | |
1708 | else if (prev_pinfo & INSN_WRITE_FPR_S) | |
1709 | { | |
1710 | if (mips_optimize == 0 | |
1711 | || insn_uses_reg (ip, | |
1712 | ((prev_insn.insn_opcode >> OP_SH_FS) | |
1713 | & OP_MASK_FS), | |
1714 | MIPS_FP_REG)) | |
1715 | ++nops; | |
1716 | } | |
1717 | else | |
1718 | { | |
1719 | /* We don't know exactly what the previous instruction | |
1720 | does. If the current instruction uses a coprocessor | |
1721 | register, we must insert a NOP. If previous | |
1722 | instruction may set the condition codes, and the | |
1723 | current instruction uses them, we must insert two | |
1724 | NOPS. */ | |
bdaaa2e1 | 1725 | /* Itbl support may require additional care here. */ |
252b5132 RH |
1726 | if (mips_optimize == 0 |
1727 | || ((prev_pinfo & INSN_WRITE_COND_CODE) | |
1728 | && (pinfo & INSN_READ_COND_CODE))) | |
1729 | nops += 2; | |
1730 | else if (pinfo & INSN_COP) | |
1731 | ++nops; | |
1732 | } | |
1733 | } | |
1734 | else if (! mips_opts.mips16 | |
252b5132 RH |
1735 | && (prev_pinfo & INSN_WRITE_COND_CODE) |
1736 | && ! cop_interlocks) | |
1737 | { | |
1738 | /* The previous instruction sets the coprocessor condition | |
1739 | codes, but does not require a general coprocessor delay | |
1740 | (this means it is a floating point comparison | |
1741 | instruction). If this instruction uses the condition | |
1742 | codes, we need to insert a single NOP. */ | |
beae10d5 | 1743 | /* Itbl support may require additional care here. */ |
252b5132 RH |
1744 | if (mips_optimize == 0 |
1745 | || (pinfo & INSN_READ_COND_CODE)) | |
1746 | ++nops; | |
1747 | } | |
6b76fefe CM |
1748 | |
1749 | /* If we're fixing up mfhi/mflo for the r7000 and the | |
1750 | previous insn was an mfhi/mflo and the current insn | |
1751 | reads the register that the mfhi/mflo wrote to, then | |
1752 | insert two nops. */ | |
1753 | ||
1754 | else if (mips_7000_hilo_fix | |
1755 | && MF_HILO_INSN (prev_pinfo) | |
1756 | && insn_uses_reg (ip, ((prev_insn.insn_opcode >> OP_SH_RD) | |
beae10d5 KH |
1757 | & OP_MASK_RD), |
1758 | MIPS_GR_REG)) | |
6b76fefe CM |
1759 | { |
1760 | nops += 2; | |
1761 | } | |
1762 | ||
1763 | /* If we're fixing up mfhi/mflo for the r7000 and the | |
1764 | 2nd previous insn was an mfhi/mflo and the current insn | |
1765 | reads the register that the mfhi/mflo wrote to, then | |
1766 | insert one nop. */ | |
1767 | ||
1768 | else if (mips_7000_hilo_fix | |
1769 | && MF_HILO_INSN (prev_prev_insn.insn_opcode) | |
1770 | && insn_uses_reg (ip, ((prev_prev_insn.insn_opcode >> OP_SH_RD) | |
1771 | & OP_MASK_RD), | |
1772 | MIPS_GR_REG)) | |
bdaaa2e1 | 1773 | |
6b76fefe | 1774 | { |
f9419b05 | 1775 | ++nops; |
6b76fefe | 1776 | } |
bdaaa2e1 | 1777 | |
252b5132 RH |
1778 | else if (prev_pinfo & INSN_READ_LO) |
1779 | { | |
1780 | /* The previous instruction reads the LO register; if the | |
1781 | current instruction writes to the LO register, we must | |
bdaaa2e1 | 1782 | insert two NOPS. Some newer processors have interlocks. |
67c1ffbe KH |
1783 | Also the tx39's multiply instructions can be executed |
1784 | immediately after a read from HI/LO (without the delay), | |
bdaaa2e1 KH |
1785 | though the tx39's divide insns still do require the |
1786 | delay. */ | |
252b5132 | 1787 | if (! (hilo_interlocks |
048cdf86 | 1788 | || (mips_opts.arch == CPU_R3900 && (pinfo & INSN_MULT))) |
252b5132 RH |
1789 | && (mips_optimize == 0 |
1790 | || (pinfo & INSN_WRITE_LO))) | |
1791 | nops += 2; | |
1792 | /* Most mips16 branch insns don't have a delay slot. | |
1793 | If a read from LO is immediately followed by a branch | |
1794 | to a write to LO we have a read followed by a write | |
1795 | less than 2 insns away. We assume the target of | |
1796 | a branch might be a write to LO, and insert a nop | |
bdaaa2e1 | 1797 | between a read and an immediately following branch. */ |
252b5132 RH |
1798 | else if (mips_opts.mips16 |
1799 | && (mips_optimize == 0 | |
1800 | || (pinfo & MIPS16_INSN_BRANCH))) | |
f9419b05 | 1801 | ++nops; |
252b5132 RH |
1802 | } |
1803 | else if (prev_insn.insn_mo->pinfo & INSN_READ_HI) | |
1804 | { | |
1805 | /* The previous instruction reads the HI register; if the | |
1806 | current instruction writes to the HI register, we must | |
1807 | insert a NOP. Some newer processors have interlocks. | |
bdaaa2e1 | 1808 | Also the note tx39's multiply above. */ |
252b5132 | 1809 | if (! (hilo_interlocks |
048cdf86 | 1810 | || (mips_opts.arch == CPU_R3900 && (pinfo & INSN_MULT))) |
252b5132 RH |
1811 | && (mips_optimize == 0 |
1812 | || (pinfo & INSN_WRITE_HI))) | |
1813 | nops += 2; | |
1814 | /* Most mips16 branch insns don't have a delay slot. | |
1815 | If a read from HI is immediately followed by a branch | |
1816 | to a write to HI we have a read followed by a write | |
1817 | less than 2 insns away. We assume the target of | |
1818 | a branch might be a write to HI, and insert a nop | |
bdaaa2e1 | 1819 | between a read and an immediately following branch. */ |
252b5132 RH |
1820 | else if (mips_opts.mips16 |
1821 | && (mips_optimize == 0 | |
1822 | || (pinfo & MIPS16_INSN_BRANCH))) | |
f9419b05 | 1823 | ++nops; |
252b5132 RH |
1824 | } |
1825 | ||
1826 | /* If the previous instruction was in a noreorder section, then | |
1827 | we don't want to insert the nop after all. */ | |
bdaaa2e1 | 1828 | /* Itbl support may require additional care here. */ |
252b5132 RH |
1829 | if (prev_insn_unreordered) |
1830 | nops = 0; | |
1831 | ||
1832 | /* There are two cases which require two intervening | |
1833 | instructions: 1) setting the condition codes using a move to | |
1834 | coprocessor instruction which requires a general coprocessor | |
1835 | delay and then reading the condition codes 2) reading the HI | |
1836 | or LO register and then writing to it (except on processors | |
1837 | which have interlocks). If we are not already emitting a NOP | |
1838 | instruction, we must check for these cases compared to the | |
1839 | instruction previous to the previous instruction. */ | |
1840 | if ((! mips_opts.mips16 | |
252b5132 RH |
1841 | && (prev_prev_insn.insn_mo->pinfo & INSN_COPROC_MOVE_DELAY) |
1842 | && (prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE) | |
1843 | && (pinfo & INSN_READ_COND_CODE) | |
1844 | && ! cop_interlocks) | |
1845 | || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_LO) | |
1846 | && (pinfo & INSN_WRITE_LO) | |
1847 | && ! (hilo_interlocks | |
048cdf86 | 1848 | || (mips_opts.arch == CPU_R3900 && (pinfo & INSN_MULT)))) |
252b5132 RH |
1849 | || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI) |
1850 | && (pinfo & INSN_WRITE_HI) | |
1851 | && ! (hilo_interlocks | |
048cdf86 | 1852 | || (mips_opts.arch == CPU_R3900 && (pinfo & INSN_MULT))))) |
252b5132 RH |
1853 | prev_prev_nop = 1; |
1854 | else | |
1855 | prev_prev_nop = 0; | |
1856 | ||
1857 | if (prev_prev_insn_unreordered) | |
1858 | prev_prev_nop = 0; | |
1859 | ||
1860 | if (prev_prev_nop && nops == 0) | |
1861 | ++nops; | |
1862 | ||
d766e8ec | 1863 | if (mips_fix_vr4120 && prev_insn.insn_mo->name) |
60b63b72 RS |
1864 | { |
1865 | /* We're out of bits in pinfo, so we must resort to string | |
1866 | ops here. Shortcuts are selected based on opcodes being | |
d766e8ec | 1867 | limited to the VR4120 instruction set. */ |
60b63b72 RS |
1868 | int min_nops = 0; |
1869 | const char *pn = prev_insn.insn_mo->name; | |
1870 | const char *tn = ip->insn_mo->name; | |
532c738a RS |
1871 | if (strncmp (pn, "macc", 4) == 0 |
1872 | || strncmp (pn, "dmacc", 5) == 0) | |
60b63b72 RS |
1873 | { |
1874 | /* Errata 21 - [D]DIV[U] after [D]MACC */ | |
1875 | if (strstr (tn, "div")) | |
532c738a | 1876 | min_nops = 1; |
60b63b72 | 1877 | |
532c738a RS |
1878 | /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU |
1879 | instruction is executed immediately after a MACC or | |
1880 | DMACC instruction, the result of [either instruction] | |
1881 | is incorrect." */ | |
1882 | if (strncmp (tn, "mult", 4) == 0 | |
1883 | || strncmp (tn, "dmult", 5) == 0) | |
1884 | min_nops = 1; | |
1885 | ||
1886 | /* Errata 23 - Continuous DMULT[U]/DMACC instructions. | |
1887 | Applies on top of VR4181A MD(1) errata. */ | |
1888 | if (pn[0] == 'd' && strncmp (tn, "dmacc", 5) == 0) | |
1889 | min_nops = 1; | |
60b63b72 RS |
1890 | |
1891 | /* Errata 24 - MT{LO,HI} after [D]MACC */ | |
1892 | if (strcmp (tn, "mtlo") == 0 | |
1893 | || strcmp (tn, "mthi") == 0) | |
532c738a | 1894 | min_nops = 1; |
60b63b72 | 1895 | } |
532c738a RS |
1896 | else if (strncmp (pn, "dmult", 5) == 0 |
1897 | && (strncmp (tn, "dmult", 5) == 0 | |
1898 | || strncmp (tn, "dmacc", 5) == 0)) | |
60b63b72 RS |
1899 | { |
1900 | /* Here is the rest of errata 23. */ | |
1901 | min_nops = 1; | |
1902 | } | |
532c738a RS |
1903 | else if ((strncmp (pn, "dmult", 5) == 0 || strstr (pn, "div")) |
1904 | && (strncmp (tn, "macc", 4) == 0 | |
1905 | || strncmp (tn, "dmacc", 5) == 0)) | |
1906 | { | |
1907 | /* VR4181A errata MD(4): "If a MACC or DMACC instruction is | |
1908 | executed immediately after a DMULT, DMULTU, DIV, DIVU, | |
1909 | DDIV or DDIVU instruction, the result of the MACC or | |
1910 | DMACC instruction is incorrect.". This partly overlaps | |
1911 | the workaround for errata 23. */ | |
1912 | min_nops = 1; | |
1913 | } | |
60b63b72 RS |
1914 | if (nops < min_nops) |
1915 | nops = min_nops; | |
1916 | } | |
1917 | ||
252b5132 RH |
1918 | /* If we are being given a nop instruction, don't bother with |
1919 | one of the nops we would otherwise output. This will only | |
1920 | happen when a nop instruction is used with mips_optimize set | |
1921 | to 0. */ | |
1922 | if (nops > 0 | |
1923 | && ! mips_opts.noreorder | |
156c2f8b | 1924 | && ip->insn_opcode == (unsigned) (mips_opts.mips16 ? 0x6500 : 0)) |
252b5132 RH |
1925 | --nops; |
1926 | ||
1927 | /* Now emit the right number of NOP instructions. */ | |
1928 | if (nops > 0 && ! mips_opts.noreorder) | |
1929 | { | |
1930 | fragS *old_frag; | |
1931 | unsigned long old_frag_offset; | |
1932 | int i; | |
1933 | struct insn_label_list *l; | |
1934 | ||
1935 | old_frag = frag_now; | |
1936 | old_frag_offset = frag_now_fix (); | |
1937 | ||
1938 | for (i = 0; i < nops; i++) | |
1939 | emit_nop (); | |
1940 | ||
1941 | if (listing) | |
1942 | { | |
1943 | listing_prev_line (); | |
1944 | /* We may be at the start of a variant frag. In case we | |
1945 | are, make sure there is enough space for the frag | |
1946 | after the frags created by listing_prev_line. The | |
1947 | argument to frag_grow here must be at least as large | |
1948 | as the argument to all other calls to frag_grow in | |
1949 | this file. We don't have to worry about being in the | |
1950 | middle of a variant frag, because the variants insert | |
1951 | all needed nop instructions themselves. */ | |
1952 | frag_grow (40); | |
1953 | } | |
1954 | ||
1955 | for (l = insn_labels; l != NULL; l = l->next) | |
1956 | { | |
98aa84af AM |
1957 | valueT val; |
1958 | ||
252b5132 | 1959 | assert (S_GET_SEGMENT (l->label) == now_seg); |
49309057 | 1960 | symbol_set_frag (l->label, frag_now); |
98aa84af | 1961 | val = (valueT) frag_now_fix (); |
252b5132 RH |
1962 | /* mips16 text labels are stored as odd. */ |
1963 | if (mips_opts.mips16) | |
f9419b05 | 1964 | ++val; |
98aa84af | 1965 | S_SET_VALUE (l->label, val); |
252b5132 RH |
1966 | } |
1967 | ||
1968 | #ifndef NO_ECOFF_DEBUGGING | |
1969 | if (ECOFF_DEBUGGING) | |
1970 | ecoff_fix_loc (old_frag, old_frag_offset); | |
1971 | #endif | |
1972 | } | |
1973 | else if (prev_nop_frag != NULL) | |
1974 | { | |
1975 | /* We have a frag holding nops we may be able to remove. If | |
1976 | we don't need any nops, we can decrease the size of | |
1977 | prev_nop_frag by the size of one instruction. If we do | |
bdaaa2e1 | 1978 | need some nops, we count them in prev_nops_required. */ |
252b5132 RH |
1979 | if (prev_nop_frag_since == 0) |
1980 | { | |
1981 | if (nops == 0) | |
1982 | { | |
1983 | prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4; | |
1984 | --prev_nop_frag_holds; | |
1985 | } | |
1986 | else | |
1987 | prev_nop_frag_required += nops; | |
1988 | } | |
1989 | else | |
1990 | { | |
1991 | if (prev_prev_nop == 0) | |
1992 | { | |
1993 | prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4; | |
1994 | --prev_nop_frag_holds; | |
1995 | } | |
1996 | else | |
1997 | ++prev_nop_frag_required; | |
1998 | } | |
1999 | ||
2000 | if (prev_nop_frag_holds <= prev_nop_frag_required) | |
2001 | prev_nop_frag = NULL; | |
2002 | ||
2003 | ++prev_nop_frag_since; | |
2004 | ||
2005 | /* Sanity check: by the time we reach the second instruction | |
2006 | after prev_nop_frag, we should have used up all the nops | |
2007 | one way or another. */ | |
2008 | assert (prev_nop_frag_since <= 1 || prev_nop_frag == NULL); | |
2009 | } | |
2010 | } | |
2011 | ||
58e2ea4d MR |
2012 | #ifdef OBJ_ELF |
2013 | /* The value passed to dwarf2_emit_insn is the distance between | |
2014 | the beginning of the current instruction and the address that | |
2015 | should be recorded in the debug tables. For MIPS16 debug info | |
2016 | we want to use ISA-encoded addresses, so we pass -1 for an | |
2017 | address higher by one than the current. */ | |
2018 | dwarf2_emit_insn (mips_opts.mips16 ? -1 : 0); | |
2019 | #endif | |
2020 | ||
895921c9 MR |
2021 | /* Record the frag type before frag_var. */ |
2022 | if (prev_insn_frag) | |
2023 | prev_insn_frag_type = prev_insn_frag->fr_type; | |
2024 | ||
4d7206a2 | 2025 | if (address_expr |
0b25d3e6 | 2026 | && *reloc_type == BFD_RELOC_16_PCREL_S2 |
4a6a3df4 AO |
2027 | && (pinfo & INSN_UNCOND_BRANCH_DELAY || pinfo & INSN_COND_BRANCH_DELAY |
2028 | || pinfo & INSN_COND_BRANCH_LIKELY) | |
2029 | && mips_relax_branch | |
2030 | /* Don't try branch relaxation within .set nomacro, or within | |
2031 | .set noat if we use $at for PIC computations. If it turns | |
2032 | out that the branch was out-of-range, we'll get an error. */ | |
2033 | && !mips_opts.warn_about_macros | |
2034 | && !(mips_opts.noat && mips_pic != NO_PIC) | |
2035 | && !mips_opts.mips16) | |
2036 | { | |
895921c9 | 2037 | relaxed_branch = TRUE; |
4a6a3df4 AO |
2038 | f = frag_var (rs_machine_dependent, |
2039 | relaxed_branch_length | |
2040 | (NULL, NULL, | |
2041 | (pinfo & INSN_UNCOND_BRANCH_DELAY) ? -1 | |
2042 | : (pinfo & INSN_COND_BRANCH_LIKELY) ? 1 : 0), 4, | |
2043 | RELAX_BRANCH_ENCODE | |
af6ae2ad | 2044 | (pinfo & INSN_UNCOND_BRANCH_DELAY, |
4a6a3df4 AO |
2045 | pinfo & INSN_COND_BRANCH_LIKELY, |
2046 | pinfo & INSN_WRITE_GPR_31, | |
2047 | 0), | |
2048 | address_expr->X_add_symbol, | |
2049 | address_expr->X_add_number, | |
2050 | 0); | |
2051 | *reloc_type = BFD_RELOC_UNUSED; | |
2052 | } | |
2053 | else if (*reloc_type > BFD_RELOC_UNUSED) | |
252b5132 RH |
2054 | { |
2055 | /* We need to set up a variant frag. */ | |
2056 | assert (mips_opts.mips16 && address_expr != NULL); | |
2057 | f = frag_var (rs_machine_dependent, 4, 0, | |
f6688943 | 2058 | RELAX_MIPS16_ENCODE (*reloc_type - BFD_RELOC_UNUSED, |
252b5132 RH |
2059 | mips16_small, mips16_ext, |
2060 | (prev_pinfo | |
2061 | & INSN_UNCOND_BRANCH_DELAY), | |
f6688943 | 2062 | (*prev_insn_reloc_type |
252b5132 | 2063 | == BFD_RELOC_MIPS16_JMP)), |
c4e7957c | 2064 | make_expr_symbol (address_expr), 0, NULL); |
252b5132 | 2065 | } |
252b5132 RH |
2066 | else if (mips_opts.mips16 |
2067 | && ! ip->use_extend | |
f6688943 | 2068 | && *reloc_type != BFD_RELOC_MIPS16_JMP) |
252b5132 RH |
2069 | { |
2070 | /* Make sure there is enough room to swap this instruction with | |
2071 | a following jump instruction. */ | |
2072 | frag_grow (6); | |
2073 | f = frag_more (2); | |
2074 | } | |
2075 | else | |
2076 | { | |
2077 | if (mips_opts.mips16 | |
2078 | && mips_opts.noreorder | |
2079 | && (prev_pinfo & INSN_UNCOND_BRANCH_DELAY) != 0) | |
2080 | as_warn (_("extended instruction in delay slot")); | |
2081 | ||
4d7206a2 RS |
2082 | if (mips_relax.sequence) |
2083 | { | |
2084 | /* If we've reached the end of this frag, turn it into a variant | |
2085 | frag and record the information for the instructions we've | |
2086 | written so far. */ | |
2087 | if (frag_room () < 4) | |
2088 | relax_close_frag (); | |
2089 | mips_relax.sizes[mips_relax.sequence - 1] += 4; | |
2090 | } | |
2091 | ||
584892a6 RS |
2092 | if (mips_relax.sequence != 2) |
2093 | mips_macro_warning.sizes[0] += 4; | |
2094 | if (mips_relax.sequence != 1) | |
2095 | mips_macro_warning.sizes[1] += 4; | |
2096 | ||
252b5132 RH |
2097 | f = frag_more (4); |
2098 | } | |
2099 | ||
f6688943 | 2100 | fixp[0] = fixp[1] = fixp[2] = NULL; |
01a3f561 | 2101 | if (address_expr != NULL && *reloc_type <= BFD_RELOC_UNUSED) |
252b5132 RH |
2102 | { |
2103 | if (address_expr->X_op == O_constant) | |
2104 | { | |
f17c130b | 2105 | unsigned int tmp; |
f6688943 TS |
2106 | |
2107 | switch (*reloc_type) | |
252b5132 RH |
2108 | { |
2109 | case BFD_RELOC_32: | |
2110 | ip->insn_opcode |= address_expr->X_add_number; | |
2111 | break; | |
2112 | ||
f6688943 | 2113 | case BFD_RELOC_MIPS_HIGHEST: |
f17c130b AM |
2114 | tmp = (address_expr->X_add_number + 0x800080008000ull) >> 48; |
2115 | ip->insn_opcode |= tmp & 0xffff; | |
f6688943 TS |
2116 | break; |
2117 | ||
2118 | case BFD_RELOC_MIPS_HIGHER: | |
f17c130b AM |
2119 | tmp = (address_expr->X_add_number + 0x80008000ull) >> 32; |
2120 | ip->insn_opcode |= tmp & 0xffff; | |
f6688943 TS |
2121 | break; |
2122 | ||
2123 | case BFD_RELOC_HI16_S: | |
f17c130b AM |
2124 | tmp = (address_expr->X_add_number + 0x8000) >> 16; |
2125 | ip->insn_opcode |= tmp & 0xffff; | |
f6688943 TS |
2126 | break; |
2127 | ||
2128 | case BFD_RELOC_HI16: | |
2129 | ip->insn_opcode |= (address_expr->X_add_number >> 16) & 0xffff; | |
2130 | break; | |
2131 | ||
01a3f561 | 2132 | case BFD_RELOC_UNUSED: |
252b5132 | 2133 | case BFD_RELOC_LO16: |
ed6fb7bd | 2134 | case BFD_RELOC_MIPS_GOT_DISP: |
252b5132 RH |
2135 | ip->insn_opcode |= address_expr->X_add_number & 0xffff; |
2136 | break; | |
2137 | ||
2138 | case BFD_RELOC_MIPS_JMP: | |
2139 | if ((address_expr->X_add_number & 3) != 0) | |
2140 | as_bad (_("jump to misaligned address (0x%lx)"), | |
2141 | (unsigned long) address_expr->X_add_number); | |
f3c0ec86 | 2142 | if (address_expr->X_add_number & ~0xfffffff) |
7496292d TS |
2143 | as_bad (_("jump address range overflow (0x%lx)"), |
2144 | (unsigned long) address_expr->X_add_number); | |
252b5132 RH |
2145 | ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0x3ffffff; |
2146 | break; | |
2147 | ||
2148 | case BFD_RELOC_MIPS16_JMP: | |
2149 | if ((address_expr->X_add_number & 3) != 0) | |
2150 | as_bad (_("jump to misaligned address (0x%lx)"), | |
2151 | (unsigned long) address_expr->X_add_number); | |
f3c0ec86 | 2152 | if (address_expr->X_add_number & ~0xfffffff) |
7496292d TS |
2153 | as_bad (_("jump address range overflow (0x%lx)"), |
2154 | (unsigned long) address_expr->X_add_number); | |
252b5132 RH |
2155 | ip->insn_opcode |= |
2156 | (((address_expr->X_add_number & 0x7c0000) << 3) | |
2157 | | ((address_expr->X_add_number & 0xf800000) >> 7) | |
2158 | | ((address_expr->X_add_number & 0x3fffc) >> 2)); | |
2159 | break; | |
2160 | ||
252b5132 RH |
2161 | case BFD_RELOC_16_PCREL_S2: |
2162 | goto need_reloc; | |
2163 | ||
2164 | default: | |
2165 | internalError (); | |
2166 | } | |
2167 | } | |
01a3f561 | 2168 | else if (*reloc_type < BFD_RELOC_UNUSED) |
252b5132 | 2169 | need_reloc: |
4d7206a2 RS |
2170 | { |
2171 | reloc_howto_type *howto; | |
2172 | int i; | |
34ce925e | 2173 | |
4d7206a2 RS |
2174 | /* In a compound relocation, it is the final (outermost) |
2175 | operator that determines the relocated field. */ | |
2176 | for (i = 1; i < 3; i++) | |
2177 | if (reloc_type[i] == BFD_RELOC_UNUSED) | |
2178 | break; | |
34ce925e | 2179 | |
4d7206a2 RS |
2180 | howto = bfd_reloc_type_lookup (stdoutput, reloc_type[i - 1]); |
2181 | fixp[0] = fix_new_exp (frag_now, f - frag_now->fr_literal, | |
2182 | bfd_get_reloc_size(howto), | |
2183 | address_expr, | |
2184 | reloc_type[0] == BFD_RELOC_16_PCREL_S2, | |
2185 | reloc_type[0]); | |
2186 | ||
2187 | /* These relocations can have an addend that won't fit in | |
2188 | 4 octets for 64bit assembly. */ | |
2189 | if (HAVE_64BIT_GPRS | |
2190 | && ! howto->partial_inplace | |
2191 | && (reloc_type[0] == BFD_RELOC_16 | |
2192 | || reloc_type[0] == BFD_RELOC_32 | |
2193 | || reloc_type[0] == BFD_RELOC_MIPS_JMP | |
2194 | || reloc_type[0] == BFD_RELOC_HI16_S | |
2195 | || reloc_type[0] == BFD_RELOC_LO16 | |
2196 | || reloc_type[0] == BFD_RELOC_GPREL16 | |
2197 | || reloc_type[0] == BFD_RELOC_MIPS_LITERAL | |
2198 | || reloc_type[0] == BFD_RELOC_GPREL32 | |
2199 | || reloc_type[0] == BFD_RELOC_64 | |
2200 | || reloc_type[0] == BFD_RELOC_CTOR | |
2201 | || reloc_type[0] == BFD_RELOC_MIPS_SUB | |
2202 | || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST | |
2203 | || reloc_type[0] == BFD_RELOC_MIPS_HIGHER | |
2204 | || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP | |
2205 | || reloc_type[0] == BFD_RELOC_MIPS_REL16 | |
d6f16593 MR |
2206 | || reloc_type[0] == BFD_RELOC_MIPS_RELGOT |
2207 | || reloc_type[0] == BFD_RELOC_MIPS16_GPREL | |
2208 | || reloc_type[0] == BFD_RELOC_MIPS16_HI16_S | |
2209 | || reloc_type[0] == BFD_RELOC_MIPS16_LO16)) | |
4d7206a2 RS |
2210 | fixp[0]->fx_no_overflow = 1; |
2211 | ||
2212 | if (mips_relax.sequence) | |
2213 | { | |
2214 | if (mips_relax.first_fixup == 0) | |
2215 | mips_relax.first_fixup = fixp[0]; | |
2216 | } | |
2217 | else if (reloc_needs_lo_p (*reloc_type)) | |
2218 | { | |
2219 | struct mips_hi_fixup *hi_fixup; | |
252b5132 | 2220 | |
4d7206a2 RS |
2221 | /* Reuse the last entry if it already has a matching %lo. */ |
2222 | hi_fixup = mips_hi_fixup_list; | |
2223 | if (hi_fixup == 0 | |
2224 | || !fixup_has_matching_lo_p (hi_fixup->fixp)) | |
2225 | { | |
2226 | hi_fixup = ((struct mips_hi_fixup *) | |
2227 | xmalloc (sizeof (struct mips_hi_fixup))); | |
2228 | hi_fixup->next = mips_hi_fixup_list; | |
2229 | mips_hi_fixup_list = hi_fixup; | |
252b5132 | 2230 | } |
4d7206a2 RS |
2231 | hi_fixup->fixp = fixp[0]; |
2232 | hi_fixup->seg = now_seg; | |
2233 | } | |
f6688943 | 2234 | |
4d7206a2 RS |
2235 | /* Add fixups for the second and third relocations, if given. |
2236 | Note that the ABI allows the second relocation to be | |
2237 | against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the | |
2238 | moment we only use RSS_UNDEF, but we could add support | |
2239 | for the others if it ever becomes necessary. */ | |
2240 | for (i = 1; i < 3; i++) | |
2241 | if (reloc_type[i] != BFD_RELOC_UNUSED) | |
2242 | { | |
6e1304d8 RS |
2243 | fixp[i] = fix_new (frag_now, fixp[0]->fx_where, |
2244 | fixp[0]->fx_size, NULL, 0, | |
2245 | FALSE, reloc_type[i]); | |
b1dca8ee RS |
2246 | |
2247 | /* Use fx_tcbit to mark compound relocs. */ | |
2248 | fixp[0]->fx_tcbit = 1; | |
2249 | fixp[i]->fx_tcbit = 1; | |
4d7206a2 | 2250 | } |
252b5132 RH |
2251 | } |
2252 | } | |
2253 | ||
2254 | if (! mips_opts.mips16) | |
58e2ea4d | 2255 | md_number_to_chars (f, ip->insn_opcode, 4); |
f6688943 | 2256 | else if (*reloc_type == BFD_RELOC_MIPS16_JMP) |
252b5132 RH |
2257 | { |
2258 | md_number_to_chars (f, ip->insn_opcode >> 16, 2); | |
2259 | md_number_to_chars (f + 2, ip->insn_opcode & 0xffff, 2); | |
2260 | } | |
2261 | else | |
2262 | { | |
2263 | if (ip->use_extend) | |
2264 | { | |
2265 | md_number_to_chars (f, 0xf000 | ip->extend, 2); | |
2266 | f += 2; | |
2267 | } | |
2268 | md_number_to_chars (f, ip->insn_opcode, 2); | |
2269 | } | |
2270 | ||
2271 | /* Update the register mask information. */ | |
2272 | if (! mips_opts.mips16) | |
2273 | { | |
2274 | if (pinfo & INSN_WRITE_GPR_D) | |
2275 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD); | |
2276 | if ((pinfo & (INSN_WRITE_GPR_T | INSN_READ_GPR_T)) != 0) | |
2277 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT); | |
2278 | if (pinfo & INSN_READ_GPR_S) | |
2279 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS); | |
2280 | if (pinfo & INSN_WRITE_GPR_31) | |
f9419b05 | 2281 | mips_gprmask |= 1 << RA; |
252b5132 RH |
2282 | if (pinfo & INSN_WRITE_FPR_D) |
2283 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FD) & OP_MASK_FD); | |
2284 | if ((pinfo & (INSN_WRITE_FPR_S | INSN_READ_FPR_S)) != 0) | |
2285 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS); | |
2286 | if ((pinfo & (INSN_WRITE_FPR_T | INSN_READ_FPR_T)) != 0) | |
2287 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT); | |
2288 | if ((pinfo & INSN_READ_FPR_R) != 0) | |
2289 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FR) & OP_MASK_FR); | |
2290 | if (pinfo & INSN_COP) | |
2291 | { | |
bdaaa2e1 KH |
2292 | /* We don't keep enough information to sort these cases out. |
2293 | The itbl support does keep this information however, although | |
2294 | we currently don't support itbl fprmats as part of the cop | |
2295 | instruction. May want to add this support in the future. */ | |
252b5132 RH |
2296 | } |
2297 | /* Never set the bit for $0, which is always zero. */ | |
beae10d5 | 2298 | mips_gprmask &= ~1 << 0; |
252b5132 RH |
2299 | } |
2300 | else | |
2301 | { | |
2302 | if (pinfo & (MIPS16_INSN_WRITE_X | MIPS16_INSN_READ_X)) | |
2303 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RX) | |
2304 | & MIPS16OP_MASK_RX); | |
2305 | if (pinfo & (MIPS16_INSN_WRITE_Y | MIPS16_INSN_READ_Y)) | |
2306 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RY) | |
2307 | & MIPS16OP_MASK_RY); | |
2308 | if (pinfo & MIPS16_INSN_WRITE_Z) | |
2309 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RZ) | |
2310 | & MIPS16OP_MASK_RZ); | |
2311 | if (pinfo & (MIPS16_INSN_WRITE_T | MIPS16_INSN_READ_T)) | |
2312 | mips_gprmask |= 1 << TREG; | |
2313 | if (pinfo & (MIPS16_INSN_WRITE_SP | MIPS16_INSN_READ_SP)) | |
2314 | mips_gprmask |= 1 << SP; | |
2315 | if (pinfo & (MIPS16_INSN_WRITE_31 | MIPS16_INSN_READ_31)) | |
2316 | mips_gprmask |= 1 << RA; | |
2317 | if (pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
2318 | mips_gprmask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode); | |
2319 | if (pinfo & MIPS16_INSN_READ_Z) | |
2320 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z) | |
2321 | & MIPS16OP_MASK_MOVE32Z); | |
2322 | if (pinfo & MIPS16_INSN_READ_GPR_X) | |
2323 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_REGR32) | |
2324 | & MIPS16OP_MASK_REGR32); | |
2325 | } | |
2326 | ||
4d7206a2 | 2327 | if (mips_relax.sequence != 2 && !mips_opts.noreorder) |
252b5132 RH |
2328 | { |
2329 | /* Filling the branch delay slot is more complex. We try to | |
2330 | switch the branch with the previous instruction, which we can | |
2331 | do if the previous instruction does not set up a condition | |
2332 | that the branch tests and if the branch is not itself the | |
2333 | target of any branch. */ | |
2334 | if ((pinfo & INSN_UNCOND_BRANCH_DELAY) | |
2335 | || (pinfo & INSN_COND_BRANCH_DELAY)) | |
2336 | { | |
2337 | if (mips_optimize < 2 | |
2338 | /* If we have seen .set volatile or .set nomove, don't | |
2339 | optimize. */ | |
2340 | || mips_opts.nomove != 0 | |
2341 | /* If we had to emit any NOP instructions, then we | |
2342 | already know we can not swap. */ | |
2343 | || nops != 0 | |
2344 | /* If we don't even know the previous insn, we can not | |
bdaaa2e1 | 2345 | swap. */ |
252b5132 RH |
2346 | || ! prev_insn_valid |
2347 | /* If the previous insn is already in a branch delay | |
2348 | slot, then we can not swap. */ | |
2349 | || prev_insn_is_delay_slot | |
2350 | /* If the previous previous insn was in a .set | |
2351 | noreorder, we can't swap. Actually, the MIPS | |
2352 | assembler will swap in this situation. However, gcc | |
2353 | configured -with-gnu-as will generate code like | |
2354 | .set noreorder | |
2355 | lw $4,XXX | |
2356 | .set reorder | |
2357 | INSN | |
2358 | bne $4,$0,foo | |
2359 | in which we can not swap the bne and INSN. If gcc is | |
2360 | not configured -with-gnu-as, it does not output the | |
2361 | .set pseudo-ops. We don't have to check | |
2362 | prev_insn_unreordered, because prev_insn_valid will | |
2363 | be 0 in that case. We don't want to use | |
2364 | prev_prev_insn_valid, because we do want to be able | |
2365 | to swap at the start of a function. */ | |
2366 | || prev_prev_insn_unreordered | |
2367 | /* If the branch is itself the target of a branch, we | |
2368 | can not swap. We cheat on this; all we check for is | |
2369 | whether there is a label on this instruction. If | |
2370 | there are any branches to anything other than a | |
2371 | label, users must use .set noreorder. */ | |
2372 | || insn_labels != NULL | |
895921c9 MR |
2373 | /* If the previous instruction is in a variant frag |
2374 | other than this branch's one, we cannot do the swap. | |
2375 | This does not apply to the mips16, which uses variant | |
2376 | frags for different purposes. */ | |
252b5132 | 2377 | || (! mips_opts.mips16 |
895921c9 | 2378 | && prev_insn_frag_type == rs_machine_dependent) |
252b5132 RH |
2379 | /* If the branch reads the condition codes, we don't |
2380 | even try to swap, because in the sequence | |
2381 | ctc1 $X,$31 | |
2382 | INSN | |
2383 | INSN | |
2384 | bc1t LABEL | |
2385 | we can not swap, and I don't feel like handling that | |
2386 | case. */ | |
2387 | || (! mips_opts.mips16 | |
81912461 ILT |
2388 | && (pinfo & INSN_READ_COND_CODE) |
2389 | && ! cop_interlocks) | |
252b5132 | 2390 | /* We can not swap with an instruction that requires a |
67c1ffbe | 2391 | delay slot, because the target of the branch might |
252b5132 RH |
2392 | interfere with that instruction. */ |
2393 | || (! mips_opts.mips16 | |
252b5132 | 2394 | && (prev_pinfo |
bdaaa2e1 | 2395 | /* Itbl support may require additional care here. */ |
252b5132 RH |
2396 | & (INSN_LOAD_COPROC_DELAY |
2397 | | INSN_COPROC_MOVE_DELAY | |
81912461 ILT |
2398 | | INSN_WRITE_COND_CODE)) |
2399 | && ! cop_interlocks) | |
252b5132 | 2400 | || (! (hilo_interlocks |
048cdf86 | 2401 | || (mips_opts.arch == CPU_R3900 && (pinfo & INSN_MULT))) |
252b5132 RH |
2402 | && (prev_pinfo |
2403 | & (INSN_READ_LO | |
2404 | | INSN_READ_HI))) | |
2405 | || (! mips_opts.mips16 | |
81912461 ILT |
2406 | && (prev_pinfo & INSN_LOAD_MEMORY_DELAY) |
2407 | && ! gpr_interlocks) | |
252b5132 | 2408 | || (! mips_opts.mips16 |
bdaaa2e1 | 2409 | /* Itbl support may require additional care here. */ |
81912461 ILT |
2410 | && (prev_pinfo & INSN_COPROC_MEMORY_DELAY) |
2411 | && ! cop_mem_interlocks) | |
252b5132 RH |
2412 | /* We can not swap with a branch instruction. */ |
2413 | || (prev_pinfo | |
2414 | & (INSN_UNCOND_BRANCH_DELAY | |
2415 | | INSN_COND_BRANCH_DELAY | |
2416 | | INSN_COND_BRANCH_LIKELY)) | |
2417 | /* We do not swap with a trap instruction, since it | |
2418 | complicates trap handlers to have the trap | |
2419 | instruction be in a delay slot. */ | |
2420 | || (prev_pinfo & INSN_TRAP) | |
2421 | /* If the branch reads a register that the previous | |
2422 | instruction sets, we can not swap. */ | |
2423 | || (! mips_opts.mips16 | |
2424 | && (prev_pinfo & INSN_WRITE_GPR_T) | |
2425 | && insn_uses_reg (ip, | |
2426 | ((prev_insn.insn_opcode >> OP_SH_RT) | |
2427 | & OP_MASK_RT), | |
2428 | MIPS_GR_REG)) | |
2429 | || (! mips_opts.mips16 | |
2430 | && (prev_pinfo & INSN_WRITE_GPR_D) | |
2431 | && insn_uses_reg (ip, | |
2432 | ((prev_insn.insn_opcode >> OP_SH_RD) | |
2433 | & OP_MASK_RD), | |
2434 | MIPS_GR_REG)) | |
2435 | || (mips_opts.mips16 | |
2436 | && (((prev_pinfo & MIPS16_INSN_WRITE_X) | |
2437 | && insn_uses_reg (ip, | |
2438 | ((prev_insn.insn_opcode | |
2439 | >> MIPS16OP_SH_RX) | |
2440 | & MIPS16OP_MASK_RX), | |
2441 | MIPS16_REG)) | |
2442 | || ((prev_pinfo & MIPS16_INSN_WRITE_Y) | |
2443 | && insn_uses_reg (ip, | |
2444 | ((prev_insn.insn_opcode | |
2445 | >> MIPS16OP_SH_RY) | |
2446 | & MIPS16OP_MASK_RY), | |
2447 | MIPS16_REG)) | |
2448 | || ((prev_pinfo & MIPS16_INSN_WRITE_Z) | |
2449 | && insn_uses_reg (ip, | |
2450 | ((prev_insn.insn_opcode | |
2451 | >> MIPS16OP_SH_RZ) | |
2452 | & MIPS16OP_MASK_RZ), | |
2453 | MIPS16_REG)) | |
2454 | || ((prev_pinfo & MIPS16_INSN_WRITE_T) | |
2455 | && insn_uses_reg (ip, TREG, MIPS_GR_REG)) | |
2456 | || ((prev_pinfo & MIPS16_INSN_WRITE_31) | |
2457 | && insn_uses_reg (ip, RA, MIPS_GR_REG)) | |
2458 | || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
2459 | && insn_uses_reg (ip, | |
2460 | MIPS16OP_EXTRACT_REG32R (prev_insn. | |
2461 | insn_opcode), | |
2462 | MIPS_GR_REG)))) | |
2463 | /* If the branch writes a register that the previous | |
2464 | instruction sets, we can not swap (we know that | |
2465 | branches write only to RD or to $31). */ | |
2466 | || (! mips_opts.mips16 | |
2467 | && (prev_pinfo & INSN_WRITE_GPR_T) | |
2468 | && (((pinfo & INSN_WRITE_GPR_D) | |
2469 | && (((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT) | |
2470 | == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD))) | |
2471 | || ((pinfo & INSN_WRITE_GPR_31) | |
2472 | && (((prev_insn.insn_opcode >> OP_SH_RT) | |
2473 | & OP_MASK_RT) | |
f9419b05 | 2474 | == RA)))) |
252b5132 RH |
2475 | || (! mips_opts.mips16 |
2476 | && (prev_pinfo & INSN_WRITE_GPR_D) | |
2477 | && (((pinfo & INSN_WRITE_GPR_D) | |
2478 | && (((prev_insn.insn_opcode >> OP_SH_RD) & OP_MASK_RD) | |
2479 | == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD))) | |
2480 | || ((pinfo & INSN_WRITE_GPR_31) | |
2481 | && (((prev_insn.insn_opcode >> OP_SH_RD) | |
2482 | & OP_MASK_RD) | |
f9419b05 | 2483 | == RA)))) |
252b5132 RH |
2484 | || (mips_opts.mips16 |
2485 | && (pinfo & MIPS16_INSN_WRITE_31) | |
2486 | && ((prev_pinfo & MIPS16_INSN_WRITE_31) | |
2487 | || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
2488 | && (MIPS16OP_EXTRACT_REG32R (prev_insn.insn_opcode) | |
2489 | == RA)))) | |
2490 | /* If the branch writes a register that the previous | |
2491 | instruction reads, we can not swap (we know that | |
2492 | branches only write to RD or to $31). */ | |
2493 | || (! mips_opts.mips16 | |
2494 | && (pinfo & INSN_WRITE_GPR_D) | |
2495 | && insn_uses_reg (&prev_insn, | |
2496 | ((ip->insn_opcode >> OP_SH_RD) | |
2497 | & OP_MASK_RD), | |
2498 | MIPS_GR_REG)) | |
2499 | || (! mips_opts.mips16 | |
2500 | && (pinfo & INSN_WRITE_GPR_31) | |
f9419b05 | 2501 | && insn_uses_reg (&prev_insn, RA, MIPS_GR_REG)) |
252b5132 RH |
2502 | || (mips_opts.mips16 |
2503 | && (pinfo & MIPS16_INSN_WRITE_31) | |
2504 | && insn_uses_reg (&prev_insn, RA, MIPS_GR_REG)) | |
252b5132 RH |
2505 | /* If the previous previous instruction has a load |
2506 | delay, and sets a register that the branch reads, we | |
2507 | can not swap. */ | |
2508 | || (! mips_opts.mips16 | |
bdaaa2e1 | 2509 | /* Itbl support may require additional care here. */ |
81912461 ILT |
2510 | && (((prev_prev_insn.insn_mo->pinfo & INSN_LOAD_COPROC_DELAY) |
2511 | && ! cop_interlocks) | |
2512 | || ((prev_prev_insn.insn_mo->pinfo | |
2513 | & INSN_LOAD_MEMORY_DELAY) | |
2514 | && ! gpr_interlocks)) | |
252b5132 RH |
2515 | && insn_uses_reg (ip, |
2516 | ((prev_prev_insn.insn_opcode >> OP_SH_RT) | |
2517 | & OP_MASK_RT), | |
2518 | MIPS_GR_REG)) | |
2519 | /* If one instruction sets a condition code and the | |
2520 | other one uses a condition code, we can not swap. */ | |
2521 | || ((pinfo & INSN_READ_COND_CODE) | |
2522 | && (prev_pinfo & INSN_WRITE_COND_CODE)) | |
2523 | || ((pinfo & INSN_WRITE_COND_CODE) | |
2524 | && (prev_pinfo & INSN_READ_COND_CODE)) | |
2525 | /* If the previous instruction uses the PC, we can not | |
2526 | swap. */ | |
2527 | || (mips_opts.mips16 | |
2528 | && (prev_pinfo & MIPS16_INSN_READ_PC)) | |
2529 | /* If the previous instruction was extended, we can not | |
2530 | swap. */ | |
2531 | || (mips_opts.mips16 && prev_insn_extended) | |
2532 | /* If the previous instruction had a fixup in mips16 | |
2533 | mode, we can not swap. This normally means that the | |
2534 | previous instruction was a 4 byte branch anyhow. */ | |
f6688943 | 2535 | || (mips_opts.mips16 && prev_insn_fixp[0]) |
bdaaa2e1 KH |
2536 | /* If the previous instruction is a sync, sync.l, or |
2537 | sync.p, we can not swap. */ | |
f173e82e | 2538 | || (prev_pinfo & INSN_SYNC)) |
252b5132 RH |
2539 | { |
2540 | /* We could do even better for unconditional branches to | |
2541 | portions of this object file; we could pick up the | |
2542 | instruction at the destination, put it in the delay | |
2543 | slot, and bump the destination address. */ | |
2544 | emit_nop (); | |
dd22970f ILT |
2545 | if (mips_relax.sequence) |
2546 | mips_relax.sizes[mips_relax.sequence - 1] += 4; | |
252b5132 RH |
2547 | /* Update the previous insn information. */ |
2548 | prev_prev_insn = *ip; | |
2549 | prev_insn.insn_mo = &dummy_opcode; | |
2550 | } | |
2551 | else | |
2552 | { | |
2553 | /* It looks like we can actually do the swap. */ | |
2554 | if (! mips_opts.mips16) | |
2555 | { | |
2556 | char *prev_f; | |
2557 | char temp[4]; | |
2558 | ||
2559 | prev_f = prev_insn_frag->fr_literal + prev_insn_where; | |
895921c9 MR |
2560 | if (!relaxed_branch) |
2561 | { | |
2562 | /* If this is not a relaxed branch, then just | |
2563 | swap the instructions. */ | |
2564 | memcpy (temp, prev_f, 4); | |
2565 | memcpy (prev_f, f, 4); | |
2566 | memcpy (f, temp, 4); | |
2567 | } | |
2568 | else | |
2569 | { | |
2570 | /* If this is a relaxed branch, then we move the | |
2571 | instruction to be placed in the delay slot to | |
2572 | the current frag, shrinking the fixed part of | |
2573 | the originating frag. If the branch occupies | |
2574 | the tail of the latter, we move it backwards, | |
2575 | into the space freed by the moved instruction. */ | |
2576 | f = frag_more (4); | |
2577 | memcpy (f, prev_f, 4); | |
2578 | prev_insn_frag->fr_fix -= 4; | |
2579 | if (prev_insn_frag->fr_type == rs_machine_dependent) | |
2580 | memmove (prev_f, prev_f + 4, prev_insn_frag->fr_var); | |
2581 | } | |
2582 | ||
f6688943 TS |
2583 | if (prev_insn_fixp[0]) |
2584 | { | |
2585 | prev_insn_fixp[0]->fx_frag = frag_now; | |
2586 | prev_insn_fixp[0]->fx_where = f - frag_now->fr_literal; | |
2587 | } | |
2588 | if (prev_insn_fixp[1]) | |
2589 | { | |
2590 | prev_insn_fixp[1]->fx_frag = frag_now; | |
2591 | prev_insn_fixp[1]->fx_where = f - frag_now->fr_literal; | |
2592 | } | |
2593 | if (prev_insn_fixp[2]) | |
252b5132 | 2594 | { |
f6688943 TS |
2595 | prev_insn_fixp[2]->fx_frag = frag_now; |
2596 | prev_insn_fixp[2]->fx_where = f - frag_now->fr_literal; | |
252b5132 | 2597 | } |
f5040a92 AO |
2598 | if (prev_insn_fixp[0] && HAVE_NEWABI |
2599 | && prev_insn_frag != frag_now | |
2600 | && (prev_insn_fixp[0]->fx_r_type | |
2601 | == BFD_RELOC_MIPS_GOT_DISP | |
2602 | || (prev_insn_fixp[0]->fx_r_type | |
2603 | == BFD_RELOC_MIPS_CALL16))) | |
2604 | { | |
2605 | /* To avoid confusion in tc_gen_reloc, we must | |
2606 | ensure that this does not become a variant | |
2607 | frag. */ | |
2608 | force_new_frag = TRUE; | |
2609 | } | |
895921c9 MR |
2610 | |
2611 | if (!relaxed_branch) | |
f6688943 | 2612 | { |
895921c9 MR |
2613 | if (fixp[0]) |
2614 | { | |
2615 | fixp[0]->fx_frag = prev_insn_frag; | |
2616 | fixp[0]->fx_where = prev_insn_where; | |
2617 | } | |
2618 | if (fixp[1]) | |
2619 | { | |
2620 | fixp[1]->fx_frag = prev_insn_frag; | |
2621 | fixp[1]->fx_where = prev_insn_where; | |
2622 | } | |
2623 | if (fixp[2]) | |
2624 | { | |
2625 | fixp[2]->fx_frag = prev_insn_frag; | |
2626 | fixp[2]->fx_where = prev_insn_where; | |
2627 | } | |
f6688943 | 2628 | } |
895921c9 | 2629 | else if (prev_insn_frag->fr_type == rs_machine_dependent) |
f6688943 | 2630 | { |
895921c9 MR |
2631 | if (fixp[0]) |
2632 | fixp[0]->fx_where -= 4; | |
2633 | if (fixp[1]) | |
2634 | fixp[1]->fx_where -= 4; | |
2635 | if (fixp[2]) | |
2636 | fixp[2]->fx_where -= 4; | |
252b5132 RH |
2637 | } |
2638 | } | |
2639 | else | |
2640 | { | |
2641 | char *prev_f; | |
2642 | char temp[2]; | |
2643 | ||
f6688943 TS |
2644 | assert (prev_insn_fixp[0] == NULL); |
2645 | assert (prev_insn_fixp[1] == NULL); | |
2646 | assert (prev_insn_fixp[2] == NULL); | |
252b5132 RH |
2647 | prev_f = prev_insn_frag->fr_literal + prev_insn_where; |
2648 | memcpy (temp, prev_f, 2); | |
2649 | memcpy (prev_f, f, 2); | |
f6688943 | 2650 | if (*reloc_type != BFD_RELOC_MIPS16_JMP) |
252b5132 | 2651 | { |
f6688943 | 2652 | assert (*reloc_type == BFD_RELOC_UNUSED); |
252b5132 RH |
2653 | memcpy (f, temp, 2); |
2654 | } | |
2655 | else | |
2656 | { | |
2657 | memcpy (f, f + 2, 2); | |
2658 | memcpy (f + 2, temp, 2); | |
2659 | } | |
f6688943 TS |
2660 | if (fixp[0]) |
2661 | { | |
2662 | fixp[0]->fx_frag = prev_insn_frag; | |
2663 | fixp[0]->fx_where = prev_insn_where; | |
2664 | } | |
2665 | if (fixp[1]) | |
2666 | { | |
2667 | fixp[1]->fx_frag = prev_insn_frag; | |
2668 | fixp[1]->fx_where = prev_insn_where; | |
2669 | } | |
2670 | if (fixp[2]) | |
252b5132 | 2671 | { |
f6688943 TS |
2672 | fixp[2]->fx_frag = prev_insn_frag; |
2673 | fixp[2]->fx_where = prev_insn_where; | |
252b5132 RH |
2674 | } |
2675 | } | |
2676 | ||
2677 | /* Update the previous insn information; leave prev_insn | |
2678 | unchanged. */ | |
2679 | prev_prev_insn = *ip; | |
2680 | } | |
2681 | prev_insn_is_delay_slot = 1; | |
2682 | ||
2683 | /* If that was an unconditional branch, forget the previous | |
2684 | insn information. */ | |
2685 | if (pinfo & INSN_UNCOND_BRANCH_DELAY) | |
2686 | { | |
2687 | prev_prev_insn.insn_mo = &dummy_opcode; | |
2688 | prev_insn.insn_mo = &dummy_opcode; | |
2689 | } | |
2690 | ||
f6688943 TS |
2691 | prev_insn_fixp[0] = NULL; |
2692 | prev_insn_fixp[1] = NULL; | |
2693 | prev_insn_fixp[2] = NULL; | |
2694 | prev_insn_reloc_type[0] = BFD_RELOC_UNUSED; | |
2695 | prev_insn_reloc_type[1] = BFD_RELOC_UNUSED; | |
2696 | prev_insn_reloc_type[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
2697 | prev_insn_extended = 0; |
2698 | } | |
2699 | else if (pinfo & INSN_COND_BRANCH_LIKELY) | |
2700 | { | |
2701 | /* We don't yet optimize a branch likely. What we should do | |
2702 | is look at the target, copy the instruction found there | |
2703 | into the delay slot, and increment the branch to jump to | |
2704 | the next instruction. */ | |
2705 | emit_nop (); | |
2706 | /* Update the previous insn information. */ | |
2707 | prev_prev_insn = *ip; | |
2708 | prev_insn.insn_mo = &dummy_opcode; | |
f6688943 TS |
2709 | prev_insn_fixp[0] = NULL; |
2710 | prev_insn_fixp[1] = NULL; | |
2711 | prev_insn_fixp[2] = NULL; | |
2712 | prev_insn_reloc_type[0] = BFD_RELOC_UNUSED; | |
2713 | prev_insn_reloc_type[1] = BFD_RELOC_UNUSED; | |
2714 | prev_insn_reloc_type[2] = BFD_RELOC_UNUSED; | |
252b5132 | 2715 | prev_insn_extended = 0; |
f7870c8d | 2716 | prev_insn_is_delay_slot = 1; |
252b5132 RH |
2717 | } |
2718 | else | |
2719 | { | |
2720 | /* Update the previous insn information. */ | |
2721 | if (nops > 0) | |
2722 | prev_prev_insn.insn_mo = &dummy_opcode; | |
2723 | else | |
2724 | prev_prev_insn = prev_insn; | |
2725 | prev_insn = *ip; | |
2726 | ||
2727 | /* Any time we see a branch, we always fill the delay slot | |
2728 | immediately; since this insn is not a branch, we know it | |
2729 | is not in a delay slot. */ | |
2730 | prev_insn_is_delay_slot = 0; | |
2731 | ||
f6688943 TS |
2732 | prev_insn_fixp[0] = fixp[0]; |
2733 | prev_insn_fixp[1] = fixp[1]; | |
2734 | prev_insn_fixp[2] = fixp[2]; | |
2735 | prev_insn_reloc_type[0] = reloc_type[0]; | |
2736 | prev_insn_reloc_type[1] = reloc_type[1]; | |
2737 | prev_insn_reloc_type[2] = reloc_type[2]; | |
252b5132 RH |
2738 | if (mips_opts.mips16) |
2739 | prev_insn_extended = (ip->use_extend | |
f6688943 | 2740 | || *reloc_type > BFD_RELOC_UNUSED); |
252b5132 RH |
2741 | } |
2742 | ||
2743 | prev_prev_insn_unreordered = prev_insn_unreordered; | |
2744 | prev_insn_unreordered = 0; | |
2745 | prev_insn_frag = frag_now; | |
2746 | prev_insn_where = f - frag_now->fr_literal; | |
2747 | prev_insn_valid = 1; | |
2748 | } | |
4d7206a2 | 2749 | else if (mips_relax.sequence != 2) |
252b5132 RH |
2750 | { |
2751 | /* We need to record a bit of information even when we are not | |
2752 | reordering, in order to determine the base address for mips16 | |
2753 | PC relative relocs. */ | |
2754 | prev_prev_insn = prev_insn; | |
2755 | prev_insn = *ip; | |
f6688943 TS |
2756 | prev_insn_reloc_type[0] = reloc_type[0]; |
2757 | prev_insn_reloc_type[1] = reloc_type[1]; | |
2758 | prev_insn_reloc_type[2] = reloc_type[2]; | |
252b5132 RH |
2759 | prev_prev_insn_unreordered = prev_insn_unreordered; |
2760 | prev_insn_unreordered = 1; | |
2761 | } | |
2762 | ||
2763 | /* We just output an insn, so the next one doesn't have a label. */ | |
2764 | mips_clear_insn_labels (); | |
252b5132 RH |
2765 | } |
2766 | ||
2767 | /* This function forgets that there was any previous instruction or | |
2768 | label. If PRESERVE is non-zero, it remembers enough information to | |
bdaaa2e1 | 2769 | know whether nops are needed before a noreorder section. */ |
252b5132 RH |
2770 | |
2771 | static void | |
17a2f251 | 2772 | mips_no_prev_insn (int preserve) |
252b5132 RH |
2773 | { |
2774 | if (! preserve) | |
2775 | { | |
2776 | prev_insn.insn_mo = &dummy_opcode; | |
2777 | prev_prev_insn.insn_mo = &dummy_opcode; | |
2778 | prev_nop_frag = NULL; | |
2779 | prev_nop_frag_holds = 0; | |
2780 | prev_nop_frag_required = 0; | |
2781 | prev_nop_frag_since = 0; | |
2782 | } | |
2783 | prev_insn_valid = 0; | |
2784 | prev_insn_is_delay_slot = 0; | |
2785 | prev_insn_unreordered = 0; | |
2786 | prev_insn_extended = 0; | |
f6688943 TS |
2787 | prev_insn_reloc_type[0] = BFD_RELOC_UNUSED; |
2788 | prev_insn_reloc_type[1] = BFD_RELOC_UNUSED; | |
2789 | prev_insn_reloc_type[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
2790 | prev_prev_insn_unreordered = 0; |
2791 | mips_clear_insn_labels (); | |
2792 | } | |
2793 | ||
2794 | /* This function must be called whenever we turn on noreorder or emit | |
2795 | something other than instructions. It inserts any NOPS which might | |
2796 | be needed by the previous instruction, and clears the information | |
2797 | kept for the previous instructions. The INSNS parameter is true if | |
bdaaa2e1 | 2798 | instructions are to follow. */ |
252b5132 RH |
2799 | |
2800 | static void | |
17a2f251 | 2801 | mips_emit_delays (bfd_boolean insns) |
252b5132 RH |
2802 | { |
2803 | if (! mips_opts.noreorder) | |
2804 | { | |
2805 | int nops; | |
2806 | ||
2807 | nops = 0; | |
2808 | if ((! mips_opts.mips16 | |
81912461 ILT |
2809 | && ((prev_insn.insn_mo->pinfo |
2810 | & (INSN_LOAD_COPROC_DELAY | |
2811 | | INSN_COPROC_MOVE_DELAY | |
2812 | | INSN_WRITE_COND_CODE)) | |
2813 | && ! cop_interlocks)) | |
252b5132 RH |
2814 | || (! hilo_interlocks |
2815 | && (prev_insn.insn_mo->pinfo | |
2816 | & (INSN_READ_LO | |
2817 | | INSN_READ_HI))) | |
2818 | || (! mips_opts.mips16 | |
81912461 ILT |
2819 | && (prev_insn.insn_mo->pinfo & INSN_LOAD_MEMORY_DELAY) |
2820 | && ! gpr_interlocks) | |
252b5132 | 2821 | || (! mips_opts.mips16 |
81912461 ILT |
2822 | && (prev_insn.insn_mo->pinfo & INSN_COPROC_MEMORY_DELAY) |
2823 | && ! cop_mem_interlocks)) | |
252b5132 | 2824 | { |
beae10d5 | 2825 | /* Itbl support may require additional care here. */ |
252b5132 RH |
2826 | ++nops; |
2827 | if ((! mips_opts.mips16 | |
81912461 ILT |
2828 | && ((prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE) |
2829 | && ! cop_interlocks)) | |
252b5132 RH |
2830 | || (! hilo_interlocks |
2831 | && ((prev_insn.insn_mo->pinfo & INSN_READ_HI) | |
2832 | || (prev_insn.insn_mo->pinfo & INSN_READ_LO)))) | |
2833 | ++nops; | |
2834 | ||
2835 | if (prev_insn_unreordered) | |
2836 | nops = 0; | |
2837 | } | |
2838 | else if ((! mips_opts.mips16 | |
81912461 ILT |
2839 | && ((prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE) |
2840 | && ! cop_interlocks)) | |
252b5132 RH |
2841 | || (! hilo_interlocks |
2842 | && ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI) | |
2843 | || (prev_prev_insn.insn_mo->pinfo & INSN_READ_LO)))) | |
2844 | { | |
beae10d5 | 2845 | /* Itbl support may require additional care here. */ |
252b5132 RH |
2846 | if (! prev_prev_insn_unreordered) |
2847 | ++nops; | |
2848 | } | |
2849 | ||
d766e8ec | 2850 | if (mips_fix_vr4120 && prev_insn.insn_mo->name) |
60b63b72 RS |
2851 | { |
2852 | int min_nops = 0; | |
2853 | const char *pn = prev_insn.insn_mo->name; | |
532c738a RS |
2854 | if (strncmp (pn, "macc", 4) == 0 |
2855 | || strncmp (pn, "dmacc", 5) == 0 | |
2856 | || strncmp (pn, "dmult", 5) == 0 | |
2857 | || strstr (pn, "div")) | |
2858 | min_nops = 1; | |
60b63b72 RS |
2859 | if (nops < min_nops) |
2860 | nops = min_nops; | |
2861 | } | |
2862 | ||
252b5132 RH |
2863 | if (nops > 0) |
2864 | { | |
2865 | struct insn_label_list *l; | |
2866 | ||
2867 | if (insns) | |
2868 | { | |
2869 | /* Record the frag which holds the nop instructions, so | |
2870 | that we can remove them if we don't need them. */ | |
2871 | frag_grow (mips_opts.mips16 ? nops * 2 : nops * 4); | |
2872 | prev_nop_frag = frag_now; | |
2873 | prev_nop_frag_holds = nops; | |
2874 | prev_nop_frag_required = 0; | |
2875 | prev_nop_frag_since = 0; | |
2876 | } | |
2877 | ||
2878 | for (; nops > 0; --nops) | |
2879 | emit_nop (); | |
2880 | ||
2881 | if (insns) | |
2882 | { | |
2883 | /* Move on to a new frag, so that it is safe to simply | |
bdaaa2e1 | 2884 | decrease the size of prev_nop_frag. */ |
252b5132 RH |
2885 | frag_wane (frag_now); |
2886 | frag_new (0); | |
2887 | } | |
2888 | ||
2889 | for (l = insn_labels; l != NULL; l = l->next) | |
2890 | { | |
98aa84af AM |
2891 | valueT val; |
2892 | ||
252b5132 | 2893 | assert (S_GET_SEGMENT (l->label) == now_seg); |
49309057 | 2894 | symbol_set_frag (l->label, frag_now); |
98aa84af | 2895 | val = (valueT) frag_now_fix (); |
252b5132 RH |
2896 | /* mips16 text labels are stored as odd. */ |
2897 | if (mips_opts.mips16) | |
f9419b05 | 2898 | ++val; |
98aa84af | 2899 | S_SET_VALUE (l->label, val); |
252b5132 RH |
2900 | } |
2901 | } | |
2902 | } | |
2903 | ||
2904 | /* Mark instruction labels in mips16 mode. */ | |
f9419b05 | 2905 | if (insns) |
252b5132 RH |
2906 | mips16_mark_labels (); |
2907 | ||
2908 | mips_no_prev_insn (insns); | |
2909 | } | |
2910 | ||
584892a6 RS |
2911 | /* Set up global variables for the start of a new macro. */ |
2912 | ||
2913 | static void | |
2914 | macro_start (void) | |
2915 | { | |
2916 | memset (&mips_macro_warning.sizes, 0, sizeof (mips_macro_warning.sizes)); | |
2917 | mips_macro_warning.delay_slot_p = (mips_opts.noreorder | |
2918 | && (prev_insn.insn_mo->pinfo | |
2919 | & (INSN_UNCOND_BRANCH_DELAY | |
2920 | | INSN_COND_BRANCH_DELAY | |
2921 | | INSN_COND_BRANCH_LIKELY)) != 0); | |
2922 | } | |
2923 | ||
2924 | /* Given that a macro is longer than 4 bytes, return the appropriate warning | |
2925 | for it. Return null if no warning is needed. SUBTYPE is a bitmask of | |
2926 | RELAX_DELAY_SLOT and RELAX_NOMACRO. */ | |
2927 | ||
2928 | static const char * | |
2929 | macro_warning (relax_substateT subtype) | |
2930 | { | |
2931 | if (subtype & RELAX_DELAY_SLOT) | |
2932 | return _("Macro instruction expanded into multiple instructions" | |
2933 | " in a branch delay slot"); | |
2934 | else if (subtype & RELAX_NOMACRO) | |
2935 | return _("Macro instruction expanded into multiple instructions"); | |
2936 | else | |
2937 | return 0; | |
2938 | } | |
2939 | ||
2940 | /* Finish up a macro. Emit warnings as appropriate. */ | |
2941 | ||
2942 | static void | |
2943 | macro_end (void) | |
2944 | { | |
2945 | if (mips_macro_warning.sizes[0] > 4 || mips_macro_warning.sizes[1] > 4) | |
2946 | { | |
2947 | relax_substateT subtype; | |
2948 | ||
2949 | /* Set up the relaxation warning flags. */ | |
2950 | subtype = 0; | |
2951 | if (mips_macro_warning.sizes[1] > mips_macro_warning.sizes[0]) | |
2952 | subtype |= RELAX_SECOND_LONGER; | |
2953 | if (mips_opts.warn_about_macros) | |
2954 | subtype |= RELAX_NOMACRO; | |
2955 | if (mips_macro_warning.delay_slot_p) | |
2956 | subtype |= RELAX_DELAY_SLOT; | |
2957 | ||
2958 | if (mips_macro_warning.sizes[0] > 4 && mips_macro_warning.sizes[1] > 4) | |
2959 | { | |
2960 | /* Either the macro has a single implementation or both | |
2961 | implementations are longer than 4 bytes. Emit the | |
2962 | warning now. */ | |
2963 | const char *msg = macro_warning (subtype); | |
2964 | if (msg != 0) | |
2965 | as_warn (msg); | |
2966 | } | |
2967 | else | |
2968 | { | |
2969 | /* One implementation might need a warning but the other | |
2970 | definitely doesn't. */ | |
2971 | mips_macro_warning.first_frag->fr_subtype |= subtype; | |
2972 | } | |
2973 | } | |
2974 | } | |
2975 | ||
6e1304d8 RS |
2976 | /* Read a macro's relocation codes from *ARGS and store them in *R. |
2977 | The first argument in *ARGS will be either the code for a single | |
2978 | relocation or -1 followed by the three codes that make up a | |
2979 | composite relocation. */ | |
2980 | ||
2981 | static void | |
2982 | macro_read_relocs (va_list *args, bfd_reloc_code_real_type *r) | |
2983 | { | |
2984 | int i, next; | |
2985 | ||
2986 | next = va_arg (*args, int); | |
2987 | if (next >= 0) | |
2988 | r[0] = (bfd_reloc_code_real_type) next; | |
2989 | else | |
2990 | for (i = 0; i < 3; i++) | |
2991 | r[i] = (bfd_reloc_code_real_type) va_arg (*args, int); | |
2992 | } | |
2993 | ||
252b5132 RH |
2994 | /* Build an instruction created by a macro expansion. This is passed |
2995 | a pointer to the count of instructions created so far, an | |
2996 | expression, the name of the instruction to build, an operand format | |
2997 | string, and corresponding arguments. */ | |
2998 | ||
252b5132 | 2999 | static void |
67c0d1eb | 3000 | macro_build (expressionS *ep, const char *name, const char *fmt, ...) |
252b5132 RH |
3001 | { |
3002 | struct mips_cl_insn insn; | |
f6688943 | 3003 | bfd_reloc_code_real_type r[3]; |
252b5132 | 3004 | va_list args; |
252b5132 | 3005 | |
252b5132 | 3006 | va_start (args, fmt); |
252b5132 | 3007 | |
252b5132 RH |
3008 | if (mips_opts.mips16) |
3009 | { | |
67c0d1eb | 3010 | mips16_macro_build (ep, name, fmt, args); |
252b5132 RH |
3011 | va_end (args); |
3012 | return; | |
3013 | } | |
3014 | ||
f6688943 TS |
3015 | r[0] = BFD_RELOC_UNUSED; |
3016 | r[1] = BFD_RELOC_UNUSED; | |
3017 | r[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
3018 | insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name); |
3019 | assert (insn.insn_mo); | |
3020 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
3021 | ||
3022 | /* Search until we get a match for NAME. */ | |
3023 | while (1) | |
3024 | { | |
b34976b6 | 3025 | /* It is assumed here that macros will never generate |
deec1734 | 3026 | MDMX or MIPS-3D instructions. */ |
252b5132 RH |
3027 | if (strcmp (fmt, insn.insn_mo->args) == 0 |
3028 | && insn.insn_mo->pinfo != INSN_MACRO | |
aec421e0 TS |
3029 | && OPCODE_IS_MEMBER (insn.insn_mo, |
3030 | (mips_opts.isa | |
3396de36 | 3031 | | (file_ase_mips16 ? INSN_MIPS16 : 0)), |
fef14a42 TS |
3032 | mips_opts.arch) |
3033 | && (mips_opts.arch != CPU_R4650 || (insn.insn_mo->pinfo & FP_D) == 0)) | |
252b5132 RH |
3034 | break; |
3035 | ||
3036 | ++insn.insn_mo; | |
3037 | assert (insn.insn_mo->name); | |
3038 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
3039 | } | |
3040 | ||
3041 | insn.insn_opcode = insn.insn_mo->match; | |
3042 | for (;;) | |
3043 | { | |
3044 | switch (*fmt++) | |
3045 | { | |
3046 | case '\0': | |
3047 | break; | |
3048 | ||
3049 | case ',': | |
3050 | case '(': | |
3051 | case ')': | |
3052 | continue; | |
3053 | ||
5f74bc13 CD |
3054 | case '+': |
3055 | switch (*fmt++) | |
3056 | { | |
3057 | case 'A': | |
3058 | case 'E': | |
3059 | insn.insn_opcode |= (va_arg (args, int) | |
3060 | & OP_MASK_SHAMT) << OP_SH_SHAMT; | |
3061 | continue; | |
3062 | ||
3063 | case 'B': | |
3064 | case 'F': | |
3065 | /* Note that in the macro case, these arguments are already | |
3066 | in MSB form. (When handling the instruction in the | |
3067 | non-macro case, these arguments are sizes from which | |
3068 | MSB values must be calculated.) */ | |
3069 | insn.insn_opcode |= (va_arg (args, int) | |
3070 | & OP_MASK_INSMSB) << OP_SH_INSMSB; | |
3071 | continue; | |
3072 | ||
3073 | case 'C': | |
3074 | case 'G': | |
3075 | case 'H': | |
3076 | /* Note that in the macro case, these arguments are already | |
3077 | in MSBD form. (When handling the instruction in the | |
3078 | non-macro case, these arguments are sizes from which | |
3079 | MSBD values must be calculated.) */ | |
3080 | insn.insn_opcode |= (va_arg (args, int) | |
3081 | & OP_MASK_EXTMSBD) << OP_SH_EXTMSBD; | |
3082 | continue; | |
3083 | ||
3084 | default: | |
3085 | internalError (); | |
3086 | } | |
3087 | continue; | |
3088 | ||
252b5132 RH |
3089 | case 't': |
3090 | case 'w': | |
3091 | case 'E': | |
38487616 | 3092 | insn.insn_opcode |= va_arg (args, int) << OP_SH_RT; |
252b5132 RH |
3093 | continue; |
3094 | ||
3095 | case 'c': | |
38487616 TS |
3096 | insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE; |
3097 | continue; | |
3098 | ||
252b5132 RH |
3099 | case 'T': |
3100 | case 'W': | |
38487616 | 3101 | insn.insn_opcode |= va_arg (args, int) << OP_SH_FT; |
252b5132 RH |
3102 | continue; |
3103 | ||
3104 | case 'd': | |
3105 | case 'G': | |
af7ee8bf | 3106 | case 'K': |
38487616 | 3107 | insn.insn_opcode |= va_arg (args, int) << OP_SH_RD; |
252b5132 RH |
3108 | continue; |
3109 | ||
4372b673 NC |
3110 | case 'U': |
3111 | { | |
3112 | int tmp = va_arg (args, int); | |
3113 | ||
38487616 TS |
3114 | insn.insn_opcode |= tmp << OP_SH_RT; |
3115 | insn.insn_opcode |= tmp << OP_SH_RD; | |
beae10d5 | 3116 | continue; |
4372b673 NC |
3117 | } |
3118 | ||
252b5132 RH |
3119 | case 'V': |
3120 | case 'S': | |
38487616 | 3121 | insn.insn_opcode |= va_arg (args, int) << OP_SH_FS; |
252b5132 RH |
3122 | continue; |
3123 | ||
3124 | case 'z': | |
3125 | continue; | |
3126 | ||
3127 | case '<': | |
38487616 | 3128 | insn.insn_opcode |= va_arg (args, int) << OP_SH_SHAMT; |
252b5132 RH |
3129 | continue; |
3130 | ||
3131 | case 'D': | |
38487616 | 3132 | insn.insn_opcode |= va_arg (args, int) << OP_SH_FD; |
252b5132 RH |
3133 | continue; |
3134 | ||
3135 | case 'B': | |
38487616 | 3136 | insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE20; |
252b5132 RH |
3137 | continue; |
3138 | ||
4372b673 | 3139 | case 'J': |
38487616 | 3140 | insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE19; |
4372b673 NC |
3141 | continue; |
3142 | ||
252b5132 | 3143 | case 'q': |
38487616 | 3144 | insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE2; |
252b5132 RH |
3145 | continue; |
3146 | ||
3147 | case 'b': | |
3148 | case 's': | |
3149 | case 'r': | |
3150 | case 'v': | |
38487616 | 3151 | insn.insn_opcode |= va_arg (args, int) << OP_SH_RS; |
252b5132 RH |
3152 | continue; |
3153 | ||
3154 | case 'i': | |
3155 | case 'j': | |
3156 | case 'o': | |
6e1304d8 | 3157 | macro_read_relocs (&args, r); |
cdf6fd85 | 3158 | assert (*r == BFD_RELOC_GPREL16 |
f6688943 TS |
3159 | || *r == BFD_RELOC_MIPS_LITERAL |
3160 | || *r == BFD_RELOC_MIPS_HIGHER | |
3161 | || *r == BFD_RELOC_HI16_S | |
3162 | || *r == BFD_RELOC_LO16 | |
3163 | || *r == BFD_RELOC_MIPS_GOT16 | |
3164 | || *r == BFD_RELOC_MIPS_CALL16 | |
438c16b8 TS |
3165 | || *r == BFD_RELOC_MIPS_GOT_DISP |
3166 | || *r == BFD_RELOC_MIPS_GOT_PAGE | |
3167 | || *r == BFD_RELOC_MIPS_GOT_OFST | |
f6688943 | 3168 | || *r == BFD_RELOC_MIPS_GOT_LO16 |
3e722fb5 | 3169 | || *r == BFD_RELOC_MIPS_CALL_LO16); |
252b5132 RH |
3170 | continue; |
3171 | ||
3172 | case 'u': | |
6e1304d8 | 3173 | macro_read_relocs (&args, r); |
252b5132 RH |
3174 | assert (ep != NULL |
3175 | && (ep->X_op == O_constant | |
3176 | || (ep->X_op == O_symbol | |
f6688943 TS |
3177 | && (*r == BFD_RELOC_MIPS_HIGHEST |
3178 | || *r == BFD_RELOC_HI16_S | |
3179 | || *r == BFD_RELOC_HI16 | |
3180 | || *r == BFD_RELOC_GPREL16 | |
3181 | || *r == BFD_RELOC_MIPS_GOT_HI16 | |
3e722fb5 | 3182 | || *r == BFD_RELOC_MIPS_CALL_HI16)))); |
252b5132 RH |
3183 | continue; |
3184 | ||
3185 | case 'p': | |
3186 | assert (ep != NULL); | |
3187 | /* | |
3188 | * This allows macro() to pass an immediate expression for | |
3189 | * creating short branches without creating a symbol. | |
0b25d3e6 AO |
3190 | * Note that the expression still might come from the assembly |
3191 | * input, in which case the value is not checked for range nor | |
3192 | * is a relocation entry generated (yuck). | |
252b5132 RH |
3193 | */ |
3194 | if (ep->X_op == O_constant) | |
3195 | { | |
3196 | insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff; | |
3197 | ep = NULL; | |
3198 | } | |
3199 | else | |
0b25d3e6 | 3200 | *r = BFD_RELOC_16_PCREL_S2; |
252b5132 RH |
3201 | continue; |
3202 | ||
3203 | case 'a': | |
3204 | assert (ep != NULL); | |
f6688943 | 3205 | *r = BFD_RELOC_MIPS_JMP; |
252b5132 RH |
3206 | continue; |
3207 | ||
3208 | case 'C': | |
3209 | insn.insn_opcode |= va_arg (args, unsigned long); | |
3210 | continue; | |
3211 | ||
3212 | default: | |
3213 | internalError (); | |
3214 | } | |
3215 | break; | |
3216 | } | |
3217 | va_end (args); | |
f6688943 | 3218 | assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
252b5132 | 3219 | |
4d7206a2 | 3220 | append_insn (&insn, ep, r); |
252b5132 RH |
3221 | } |
3222 | ||
3223 | static void | |
67c0d1eb | 3224 | mips16_macro_build (expressionS *ep, const char *name, const char *fmt, |
17a2f251 | 3225 | va_list args) |
252b5132 RH |
3226 | { |
3227 | struct mips_cl_insn insn; | |
f6688943 TS |
3228 | bfd_reloc_code_real_type r[3] |
3229 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 3230 | |
252b5132 RH |
3231 | insn.insn_mo = (struct mips_opcode *) hash_find (mips16_op_hash, name); |
3232 | assert (insn.insn_mo); | |
3233 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
3234 | ||
3235 | while (strcmp (fmt, insn.insn_mo->args) != 0 | |
3236 | || insn.insn_mo->pinfo == INSN_MACRO) | |
3237 | { | |
3238 | ++insn.insn_mo; | |
3239 | assert (insn.insn_mo->name); | |
3240 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
3241 | } | |
3242 | ||
3243 | insn.insn_opcode = insn.insn_mo->match; | |
b34976b6 | 3244 | insn.use_extend = FALSE; |
252b5132 RH |
3245 | |
3246 | for (;;) | |
3247 | { | |
3248 | int c; | |
3249 | ||
3250 | c = *fmt++; | |
3251 | switch (c) | |
3252 | { | |
3253 | case '\0': | |
3254 | break; | |
3255 | ||
3256 | case ',': | |
3257 | case '(': | |
3258 | case ')': | |
3259 | continue; | |
3260 | ||
3261 | case 'y': | |
3262 | case 'w': | |
3263 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RY; | |
3264 | continue; | |
3265 | ||
3266 | case 'x': | |
3267 | case 'v': | |
3268 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RX; | |
3269 | continue; | |
3270 | ||
3271 | case 'z': | |
3272 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RZ; | |
3273 | continue; | |
3274 | ||
3275 | case 'Z': | |
3276 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_MOVE32Z; | |
3277 | continue; | |
3278 | ||
3279 | case '0': | |
3280 | case 'S': | |
3281 | case 'P': | |
3282 | case 'R': | |
3283 | continue; | |
3284 | ||
3285 | case 'X': | |
3286 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_REGR32; | |
3287 | continue; | |
3288 | ||
3289 | case 'Y': | |
3290 | { | |
3291 | int regno; | |
3292 | ||
3293 | regno = va_arg (args, int); | |
3294 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); | |
3295 | insn.insn_opcode |= regno << MIPS16OP_SH_REG32R; | |
3296 | } | |
3297 | continue; | |
3298 | ||
3299 | case '<': | |
3300 | case '>': | |
3301 | case '4': | |
3302 | case '5': | |
3303 | case 'H': | |
3304 | case 'W': | |
3305 | case 'D': | |
3306 | case 'j': | |
3307 | case '8': | |
3308 | case 'V': | |
3309 | case 'C': | |
3310 | case 'U': | |
3311 | case 'k': | |
3312 | case 'K': | |
3313 | case 'p': | |
3314 | case 'q': | |
3315 | { | |
3316 | assert (ep != NULL); | |
3317 | ||
3318 | if (ep->X_op != O_constant) | |
874e8986 | 3319 | *r = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
3320 | else |
3321 | { | |
b34976b6 AM |
3322 | mips16_immed (NULL, 0, c, ep->X_add_number, FALSE, FALSE, |
3323 | FALSE, &insn.insn_opcode, &insn.use_extend, | |
c4e7957c | 3324 | &insn.extend); |
252b5132 | 3325 | ep = NULL; |
f6688943 | 3326 | *r = BFD_RELOC_UNUSED; |
252b5132 RH |
3327 | } |
3328 | } | |
3329 | continue; | |
3330 | ||
3331 | case '6': | |
3332 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_IMM6; | |
3333 | continue; | |
3334 | } | |
3335 | ||
3336 | break; | |
3337 | } | |
3338 | ||
f6688943 | 3339 | assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
252b5132 | 3340 | |
4d7206a2 | 3341 | append_insn (&insn, ep, r); |
252b5132 RH |
3342 | } |
3343 | ||
438c16b8 TS |
3344 | /* |
3345 | * Generate a "jalr" instruction with a relocation hint to the called | |
3346 | * function. This occurs in NewABI PIC code. | |
3347 | */ | |
3348 | static void | |
67c0d1eb | 3349 | macro_build_jalr (expressionS *ep) |
438c16b8 | 3350 | { |
685736be | 3351 | char *f = NULL; |
b34976b6 | 3352 | |
438c16b8 | 3353 | if (HAVE_NEWABI) |
f21f8242 | 3354 | { |
cc3d92a5 | 3355 | frag_grow (8); |
f21f8242 AO |
3356 | f = frag_more (0); |
3357 | } | |
67c0d1eb | 3358 | macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG); |
438c16b8 | 3359 | if (HAVE_NEWABI) |
f21f8242 | 3360 | fix_new_exp (frag_now, f - frag_now->fr_literal, |
a105a300 | 3361 | 4, ep, FALSE, BFD_RELOC_MIPS_JALR); |
438c16b8 TS |
3362 | } |
3363 | ||
252b5132 RH |
3364 | /* |
3365 | * Generate a "lui" instruction. | |
3366 | */ | |
3367 | static void | |
67c0d1eb | 3368 | macro_build_lui (expressionS *ep, int regnum) |
252b5132 RH |
3369 | { |
3370 | expressionS high_expr; | |
3371 | struct mips_cl_insn insn; | |
f6688943 TS |
3372 | bfd_reloc_code_real_type r[3] |
3373 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
5a38dc70 AM |
3374 | const char *name = "lui"; |
3375 | const char *fmt = "t,u"; | |
252b5132 RH |
3376 | |
3377 | assert (! mips_opts.mips16); | |
3378 | ||
4d7206a2 | 3379 | high_expr = *ep; |
252b5132 RH |
3380 | |
3381 | if (high_expr.X_op == O_constant) | |
3382 | { | |
3383 | /* we can compute the instruction now without a relocation entry */ | |
e7d556df TS |
3384 | high_expr.X_add_number = ((high_expr.X_add_number + 0x8000) |
3385 | >> 16) & 0xffff; | |
f6688943 | 3386 | *r = BFD_RELOC_UNUSED; |
252b5132 | 3387 | } |
78e1bb40 | 3388 | else |
252b5132 RH |
3389 | { |
3390 | assert (ep->X_op == O_symbol); | |
aa6975fb ILT |
3391 | /* _gp_disp is a special case, used from s_cpload. _gp is used |
3392 | if mips_no_shared. */ | |
252b5132 | 3393 | assert (mips_pic == NO_PIC |
78e1bb40 | 3394 | || (! HAVE_NEWABI |
aa6975fb ILT |
3395 | && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0) |
3396 | || (! mips_in_shared | |
3397 | && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp") == 0)); | |
f6688943 | 3398 | *r = BFD_RELOC_HI16_S; |
252b5132 RH |
3399 | } |
3400 | ||
252b5132 RH |
3401 | insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name); |
3402 | assert (insn.insn_mo); | |
3403 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
3404 | assert (strcmp (fmt, insn.insn_mo->args) == 0); | |
3405 | ||
3406 | insn.insn_opcode = insn.insn_mo->match | (regnum << OP_SH_RT); | |
f6688943 | 3407 | if (*r == BFD_RELOC_UNUSED) |
252b5132 RH |
3408 | { |
3409 | insn.insn_opcode |= high_expr.X_add_number; | |
4d7206a2 | 3410 | append_insn (&insn, NULL, r); |
252b5132 RH |
3411 | } |
3412 | else | |
4d7206a2 | 3413 | append_insn (&insn, &high_expr, r); |
252b5132 RH |
3414 | } |
3415 | ||
885add95 CD |
3416 | /* Generate a sequence of instructions to do a load or store from a constant |
3417 | offset off of a base register (breg) into/from a target register (treg), | |
3418 | using AT if necessary. */ | |
3419 | static void | |
67c0d1eb RS |
3420 | macro_build_ldst_constoffset (expressionS *ep, const char *op, |
3421 | int treg, int breg, int dbl) | |
885add95 CD |
3422 | { |
3423 | assert (ep->X_op == O_constant); | |
3424 | ||
256ab948 | 3425 | /* Sign-extending 32-bit constants makes their handling easier. */ |
d17e7bce TS |
3426 | if (! dbl && ! ((ep->X_add_number & ~((bfd_vma) 0x7fffffff)) |
3427 | == ~((bfd_vma) 0x7fffffff))) | |
ae826530 | 3428 | { |
d17e7bce | 3429 | if (ep->X_add_number & ~((bfd_vma) 0xffffffff)) |
1b8e29e5 | 3430 | as_bad (_("constant too large")); |
ae826530 | 3431 | |
1b8e29e5 TS |
3432 | ep->X_add_number = (((ep->X_add_number & 0xffffffff) ^ 0x80000000) |
3433 | - 0x80000000); | |
ae826530 | 3434 | } |
256ab948 | 3435 | |
67c1ffbe | 3436 | /* Right now, this routine can only handle signed 32-bit constants. */ |
ecd13cd3 | 3437 | if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000)) |
885add95 CD |
3438 | as_warn (_("operand overflow")); |
3439 | ||
3440 | if (IS_SEXT_16BIT_NUM(ep->X_add_number)) | |
3441 | { | |
3442 | /* Signed 16-bit offset will fit in the op. Easy! */ | |
67c0d1eb | 3443 | macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
885add95 CD |
3444 | } |
3445 | else | |
3446 | { | |
3447 | /* 32-bit offset, need multiple instructions and AT, like: | |
3448 | lui $tempreg,const_hi (BFD_RELOC_HI16_S) | |
3449 | addu $tempreg,$tempreg,$breg | |
3450 | <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16) | |
3451 | to handle the complete offset. */ | |
67c0d1eb RS |
3452 | macro_build_lui (ep, AT); |
3453 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); | |
3454 | macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, AT); | |
885add95 CD |
3455 | |
3456 | if (mips_opts.noat) | |
8fc2e39e | 3457 | as_bad (_("Macro used $at after \".set noat\"")); |
885add95 CD |
3458 | } |
3459 | } | |
3460 | ||
252b5132 RH |
3461 | /* set_at() |
3462 | * Generates code to set the $at register to true (one) | |
3463 | * if reg is less than the immediate expression. | |
3464 | */ | |
3465 | static void | |
67c0d1eb | 3466 | set_at (int reg, int unsignedp) |
252b5132 RH |
3467 | { |
3468 | if (imm_expr.X_op == O_constant | |
3469 | && imm_expr.X_add_number >= -0x8000 | |
3470 | && imm_expr.X_add_number < 0x8000) | |
67c0d1eb RS |
3471 | macro_build (&imm_expr, unsignedp ? "sltiu" : "slti", "t,r,j", |
3472 | AT, reg, BFD_RELOC_LO16); | |
252b5132 RH |
3473 | else |
3474 | { | |
67c0d1eb RS |
3475 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
3476 | macro_build (NULL, unsignedp ? "sltu" : "slt", "d,v,t", AT, reg, AT); | |
252b5132 RH |
3477 | } |
3478 | } | |
3479 | ||
13757d0c TS |
3480 | static void |
3481 | normalize_constant_expr (expressionS *ex) | |
3482 | { | |
3483 | if (ex->X_op == O_constant && HAVE_32BIT_GPRS) | |
3484 | ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000) | |
3485 | - 0x80000000); | |
3486 | } | |
3487 | ||
252b5132 RH |
3488 | /* Warn if an expression is not a constant. */ |
3489 | ||
3490 | static void | |
17a2f251 | 3491 | check_absolute_expr (struct mips_cl_insn *ip, expressionS *ex) |
252b5132 RH |
3492 | { |
3493 | if (ex->X_op == O_big) | |
3494 | as_bad (_("unsupported large constant")); | |
3495 | else if (ex->X_op != O_constant) | |
3496 | as_bad (_("Instruction %s requires absolute expression"), ip->insn_mo->name); | |
13757d0c TS |
3497 | |
3498 | normalize_constant_expr (ex); | |
252b5132 RH |
3499 | } |
3500 | ||
3501 | /* Count the leading zeroes by performing a binary chop. This is a | |
3502 | bulky bit of source, but performance is a LOT better for the | |
3503 | majority of values than a simple loop to count the bits: | |
3504 | for (lcnt = 0; (lcnt < 32); lcnt++) | |
3505 | if ((v) & (1 << (31 - lcnt))) | |
3506 | break; | |
3507 | However it is not code size friendly, and the gain will drop a bit | |
3508 | on certain cached systems. | |
3509 | */ | |
3510 | #define COUNT_TOP_ZEROES(v) \ | |
3511 | (((v) & ~0xffff) == 0 \ | |
3512 | ? ((v) & ~0xff) == 0 \ | |
3513 | ? ((v) & ~0xf) == 0 \ | |
3514 | ? ((v) & ~0x3) == 0 \ | |
3515 | ? ((v) & ~0x1) == 0 \ | |
3516 | ? !(v) \ | |
3517 | ? 32 \ | |
3518 | : 31 \ | |
3519 | : 30 \ | |
3520 | : ((v) & ~0x7) == 0 \ | |
3521 | ? 29 \ | |
3522 | : 28 \ | |
3523 | : ((v) & ~0x3f) == 0 \ | |
3524 | ? ((v) & ~0x1f) == 0 \ | |
3525 | ? 27 \ | |
3526 | : 26 \ | |
3527 | : ((v) & ~0x7f) == 0 \ | |
3528 | ? 25 \ | |
3529 | : 24 \ | |
3530 | : ((v) & ~0xfff) == 0 \ | |
3531 | ? ((v) & ~0x3ff) == 0 \ | |
3532 | ? ((v) & ~0x1ff) == 0 \ | |
3533 | ? 23 \ | |
3534 | : 22 \ | |
3535 | : ((v) & ~0x7ff) == 0 \ | |
3536 | ? 21 \ | |
3537 | : 20 \ | |
3538 | : ((v) & ~0x3fff) == 0 \ | |
3539 | ? ((v) & ~0x1fff) == 0 \ | |
3540 | ? 19 \ | |
3541 | : 18 \ | |
3542 | : ((v) & ~0x7fff) == 0 \ | |
3543 | ? 17 \ | |
3544 | : 16 \ | |
3545 | : ((v) & ~0xffffff) == 0 \ | |
3546 | ? ((v) & ~0xfffff) == 0 \ | |
3547 | ? ((v) & ~0x3ffff) == 0 \ | |
3548 | ? ((v) & ~0x1ffff) == 0 \ | |
3549 | ? 15 \ | |
3550 | : 14 \ | |
3551 | : ((v) & ~0x7ffff) == 0 \ | |
3552 | ? 13 \ | |
3553 | : 12 \ | |
3554 | : ((v) & ~0x3fffff) == 0 \ | |
3555 | ? ((v) & ~0x1fffff) == 0 \ | |
3556 | ? 11 \ | |
3557 | : 10 \ | |
3558 | : ((v) & ~0x7fffff) == 0 \ | |
3559 | ? 9 \ | |
3560 | : 8 \ | |
3561 | : ((v) & ~0xfffffff) == 0 \ | |
3562 | ? ((v) & ~0x3ffffff) == 0 \ | |
3563 | ? ((v) & ~0x1ffffff) == 0 \ | |
3564 | ? 7 \ | |
3565 | : 6 \ | |
3566 | : ((v) & ~0x7ffffff) == 0 \ | |
3567 | ? 5 \ | |
3568 | : 4 \ | |
3569 | : ((v) & ~0x3fffffff) == 0 \ | |
3570 | ? ((v) & ~0x1fffffff) == 0 \ | |
3571 | ? 3 \ | |
3572 | : 2 \ | |
3573 | : ((v) & ~0x7fffffff) == 0 \ | |
3574 | ? 1 \ | |
3575 | : 0) | |
3576 | ||
3577 | /* load_register() | |
67c1ffbe | 3578 | * This routine generates the least number of instructions necessary to load |
252b5132 RH |
3579 | * an absolute expression value into a register. |
3580 | */ | |
3581 | static void | |
67c0d1eb | 3582 | load_register (int reg, expressionS *ep, int dbl) |
252b5132 RH |
3583 | { |
3584 | int freg; | |
3585 | expressionS hi32, lo32; | |
3586 | ||
3587 | if (ep->X_op != O_big) | |
3588 | { | |
3589 | assert (ep->X_op == O_constant); | |
256ab948 TS |
3590 | |
3591 | /* Sign-extending 32-bit constants makes their handling easier. */ | |
d17e7bce TS |
3592 | if (! dbl && ! ((ep->X_add_number & ~((bfd_vma) 0x7fffffff)) |
3593 | == ~((bfd_vma) 0x7fffffff))) | |
ae826530 | 3594 | { |
d17e7bce | 3595 | if (ep->X_add_number & ~((bfd_vma) 0xffffffff)) |
1b8e29e5 | 3596 | as_bad (_("constant too large")); |
ae826530 | 3597 | |
1b8e29e5 TS |
3598 | ep->X_add_number = (((ep->X_add_number & 0xffffffff) ^ 0x80000000) |
3599 | - 0x80000000); | |
ae826530 | 3600 | } |
256ab948 TS |
3601 | |
3602 | if (IS_SEXT_16BIT_NUM (ep->X_add_number)) | |
252b5132 RH |
3603 | { |
3604 | /* We can handle 16 bit signed values with an addiu to | |
3605 | $zero. No need to ever use daddiu here, since $zero and | |
3606 | the result are always correct in 32 bit mode. */ | |
67c0d1eb | 3607 | macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
3608 | return; |
3609 | } | |
3610 | else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000) | |
3611 | { | |
3612 | /* We can handle 16 bit unsigned values with an ori to | |
3613 | $zero. */ | |
67c0d1eb | 3614 | macro_build (ep, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
3615 | return; |
3616 | } | |
256ab948 | 3617 | else if ((IS_SEXT_32BIT_NUM (ep->X_add_number))) |
252b5132 RH |
3618 | { |
3619 | /* 32 bit values require an lui. */ | |
67c0d1eb | 3620 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_HI16); |
252b5132 | 3621 | if ((ep->X_add_number & 0xffff) != 0) |
67c0d1eb | 3622 | macro_build (ep, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16); |
252b5132 RH |
3623 | return; |
3624 | } | |
3625 | } | |
3626 | ||
3627 | /* The value is larger than 32 bits. */ | |
3628 | ||
ca4e0257 | 3629 | if (HAVE_32BIT_GPRS) |
252b5132 | 3630 | { |
956cd1d6 TS |
3631 | as_bad (_("Number (0x%lx) larger than 32 bits"), |
3632 | (unsigned long) ep->X_add_number); | |
67c0d1eb | 3633 | macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
3634 | return; |
3635 | } | |
3636 | ||
3637 | if (ep->X_op != O_big) | |
3638 | { | |
3639 | hi32 = *ep; | |
3640 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
3641 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
3642 | hi32.X_add_number &= 0xffffffff; | |
3643 | lo32 = *ep; | |
3644 | lo32.X_add_number &= 0xffffffff; | |
3645 | } | |
3646 | else | |
3647 | { | |
3648 | assert (ep->X_add_number > 2); | |
3649 | if (ep->X_add_number == 3) | |
3650 | generic_bignum[3] = 0; | |
3651 | else if (ep->X_add_number > 4) | |
3652 | as_bad (_("Number larger than 64 bits")); | |
3653 | lo32.X_op = O_constant; | |
3654 | lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16); | |
3655 | hi32.X_op = O_constant; | |
3656 | hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16); | |
3657 | } | |
3658 | ||
3659 | if (hi32.X_add_number == 0) | |
3660 | freg = 0; | |
3661 | else | |
3662 | { | |
3663 | int shift, bit; | |
3664 | unsigned long hi, lo; | |
3665 | ||
956cd1d6 | 3666 | if (hi32.X_add_number == (offsetT) 0xffffffff) |
beae10d5 KH |
3667 | { |
3668 | if ((lo32.X_add_number & 0xffff8000) == 0xffff8000) | |
3669 | { | |
67c0d1eb | 3670 | macro_build (&lo32, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
beae10d5 KH |
3671 | return; |
3672 | } | |
3673 | if (lo32.X_add_number & 0x80000000) | |
3674 | { | |
67c0d1eb | 3675 | macro_build (&lo32, "lui", "t,u", reg, BFD_RELOC_HI16); |
252b5132 | 3676 | if (lo32.X_add_number & 0xffff) |
67c0d1eb | 3677 | macro_build (&lo32, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16); |
beae10d5 KH |
3678 | return; |
3679 | } | |
3680 | } | |
252b5132 RH |
3681 | |
3682 | /* Check for 16bit shifted constant. We know that hi32 is | |
3683 | non-zero, so start the mask on the first bit of the hi32 | |
3684 | value. */ | |
3685 | shift = 17; | |
3686 | do | |
beae10d5 KH |
3687 | { |
3688 | unsigned long himask, lomask; | |
3689 | ||
3690 | if (shift < 32) | |
3691 | { | |
3692 | himask = 0xffff >> (32 - shift); | |
3693 | lomask = (0xffff << shift) & 0xffffffff; | |
3694 | } | |
3695 | else | |
3696 | { | |
3697 | himask = 0xffff << (shift - 32); | |
3698 | lomask = 0; | |
3699 | } | |
3700 | if ((hi32.X_add_number & ~(offsetT) himask) == 0 | |
3701 | && (lo32.X_add_number & ~(offsetT) lomask) == 0) | |
3702 | { | |
3703 | expressionS tmp; | |
3704 | ||
3705 | tmp.X_op = O_constant; | |
3706 | if (shift < 32) | |
3707 | tmp.X_add_number = ((hi32.X_add_number << (32 - shift)) | |
3708 | | (lo32.X_add_number >> shift)); | |
3709 | else | |
3710 | tmp.X_add_number = hi32.X_add_number >> (shift - 32); | |
67c0d1eb RS |
3711 | macro_build (&tmp, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16); |
3712 | macro_build (NULL, (shift >= 32) ? "dsll32" : "dsll", "d,w,<", | |
3713 | reg, reg, (shift >= 32) ? shift - 32 : shift); | |
beae10d5 KH |
3714 | return; |
3715 | } | |
f9419b05 | 3716 | ++shift; |
beae10d5 KH |
3717 | } |
3718 | while (shift <= (64 - 16)); | |
252b5132 RH |
3719 | |
3720 | /* Find the bit number of the lowest one bit, and store the | |
3721 | shifted value in hi/lo. */ | |
3722 | hi = (unsigned long) (hi32.X_add_number & 0xffffffff); | |
3723 | lo = (unsigned long) (lo32.X_add_number & 0xffffffff); | |
3724 | if (lo != 0) | |
3725 | { | |
3726 | bit = 0; | |
3727 | while ((lo & 1) == 0) | |
3728 | { | |
3729 | lo >>= 1; | |
3730 | ++bit; | |
3731 | } | |
3732 | lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit); | |
3733 | hi >>= bit; | |
3734 | } | |
3735 | else | |
3736 | { | |
3737 | bit = 32; | |
3738 | while ((hi & 1) == 0) | |
3739 | { | |
3740 | hi >>= 1; | |
3741 | ++bit; | |
3742 | } | |
3743 | lo = hi; | |
3744 | hi = 0; | |
3745 | } | |
3746 | ||
3747 | /* Optimize if the shifted value is a (power of 2) - 1. */ | |
3748 | if ((hi == 0 && ((lo + 1) & lo) == 0) | |
3749 | || (lo == 0xffffffff && ((hi + 1) & hi) == 0)) | |
beae10d5 KH |
3750 | { |
3751 | shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number); | |
252b5132 | 3752 | if (shift != 0) |
beae10d5 | 3753 | { |
252b5132 RH |
3754 | expressionS tmp; |
3755 | ||
3756 | /* This instruction will set the register to be all | |
3757 | ones. */ | |
beae10d5 KH |
3758 | tmp.X_op = O_constant; |
3759 | tmp.X_add_number = (offsetT) -1; | |
67c0d1eb | 3760 | macro_build (&tmp, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
beae10d5 KH |
3761 | if (bit != 0) |
3762 | { | |
3763 | bit += shift; | |
67c0d1eb RS |
3764 | macro_build (NULL, (bit >= 32) ? "dsll32" : "dsll", "d,w,<", |
3765 | reg, reg, (bit >= 32) ? bit - 32 : bit); | |
beae10d5 | 3766 | } |
67c0d1eb RS |
3767 | macro_build (NULL, (shift >= 32) ? "dsrl32" : "dsrl", "d,w,<", |
3768 | reg, reg, (shift >= 32) ? shift - 32 : shift); | |
beae10d5 KH |
3769 | return; |
3770 | } | |
3771 | } | |
252b5132 RH |
3772 | |
3773 | /* Sign extend hi32 before calling load_register, because we can | |
3774 | generally get better code when we load a sign extended value. */ | |
3775 | if ((hi32.X_add_number & 0x80000000) != 0) | |
beae10d5 | 3776 | hi32.X_add_number |= ~(offsetT) 0xffffffff; |
67c0d1eb | 3777 | load_register (reg, &hi32, 0); |
252b5132 RH |
3778 | freg = reg; |
3779 | } | |
3780 | if ((lo32.X_add_number & 0xffff0000) == 0) | |
3781 | { | |
3782 | if (freg != 0) | |
3783 | { | |
67c0d1eb | 3784 | macro_build (NULL, "dsll32", "d,w,<", reg, freg, 0); |
252b5132 RH |
3785 | freg = reg; |
3786 | } | |
3787 | } | |
3788 | else | |
3789 | { | |
3790 | expressionS mid16; | |
3791 | ||
956cd1d6 | 3792 | if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff)) |
beae10d5 | 3793 | { |
67c0d1eb RS |
3794 | macro_build (&lo32, "lui", "t,u", reg, BFD_RELOC_HI16); |
3795 | macro_build (NULL, "dsrl32", "d,w,<", reg, reg, 0); | |
beae10d5 KH |
3796 | return; |
3797 | } | |
252b5132 RH |
3798 | |
3799 | if (freg != 0) | |
3800 | { | |
67c0d1eb | 3801 | macro_build (NULL, "dsll", "d,w,<", reg, freg, 16); |
252b5132 RH |
3802 | freg = reg; |
3803 | } | |
3804 | mid16 = lo32; | |
3805 | mid16.X_add_number >>= 16; | |
67c0d1eb RS |
3806 | macro_build (&mid16, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16); |
3807 | macro_build (NULL, "dsll", "d,w,<", reg, reg, 16); | |
252b5132 RH |
3808 | freg = reg; |
3809 | } | |
3810 | if ((lo32.X_add_number & 0xffff) != 0) | |
67c0d1eb | 3811 | macro_build (&lo32, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16); |
252b5132 RH |
3812 | } |
3813 | ||
269137b2 TS |
3814 | static inline void |
3815 | load_delay_nop (void) | |
3816 | { | |
3817 | if (!gpr_interlocks) | |
3818 | macro_build (NULL, "nop", ""); | |
3819 | } | |
3820 | ||
252b5132 RH |
3821 | /* Load an address into a register. */ |
3822 | ||
3823 | static void | |
67c0d1eb | 3824 | load_address (int reg, expressionS *ep, int *used_at) |
252b5132 | 3825 | { |
252b5132 RH |
3826 | if (ep->X_op != O_constant |
3827 | && ep->X_op != O_symbol) | |
3828 | { | |
3829 | as_bad (_("expression too complex")); | |
3830 | ep->X_op = O_constant; | |
3831 | } | |
3832 | ||
3833 | if (ep->X_op == O_constant) | |
3834 | { | |
67c0d1eb | 3835 | load_register (reg, ep, HAVE_64BIT_ADDRESSES); |
252b5132 RH |
3836 | return; |
3837 | } | |
3838 | ||
3839 | if (mips_pic == NO_PIC) | |
3840 | { | |
3841 | /* If this is a reference to a GP relative symbol, we want | |
cdf6fd85 | 3842 | addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
3843 | Otherwise we want |
3844 | lui $reg,<sym> (BFD_RELOC_HI16_S) | |
3845 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
d6bc6245 | 3846 | If we have an addend, we always use the latter form. |
76b3015f | 3847 | |
d6bc6245 TS |
3848 | With 64bit address space and a usable $at we want |
3849 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
3850 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
3851 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
3852 | daddiu $at,<sym> (BFD_RELOC_LO16) | |
3853 | dsll32 $reg,0 | |
3a482fd5 | 3854 | daddu $reg,$reg,$at |
76b3015f | 3855 | |
c03099e6 | 3856 | If $at is already in use, we use a path which is suboptimal |
d6bc6245 TS |
3857 | on superscalar processors. |
3858 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
3859 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
3860 | dsll $reg,16 | |
3861 | daddiu $reg,<sym> (BFD_RELOC_HI16_S) | |
3862 | dsll $reg,16 | |
3863 | daddiu $reg,<sym> (BFD_RELOC_LO16) | |
3864 | */ | |
c9914766 | 3865 | if (HAVE_64BIT_ADDRESSES) |
d6bc6245 | 3866 | { |
e864ceca RS |
3867 | /* ??? We don't provide a GP-relative alternative for these macros. |
3868 | It used not to be possible with the original relaxation code, | |
3869 | but it could be done now. */ | |
d6bc6245 | 3870 | |
b8285c27 | 3871 | if (*used_at == 0 && !mips_opts.noat) |
d6bc6245 | 3872 | { |
67c0d1eb RS |
3873 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_HIGHEST); |
3874 | macro_build (ep, "lui", "t,u", AT, BFD_RELOC_HI16_S); | |
3875 | macro_build (ep, "daddiu", "t,r,j", reg, reg, | |
3876 | BFD_RELOC_MIPS_HIGHER); | |
3877 | macro_build (ep, "daddiu", "t,r,j", AT, AT, BFD_RELOC_LO16); | |
3878 | macro_build (NULL, "dsll32", "d,w,<", reg, reg, 0); | |
3879 | macro_build (NULL, "daddu", "d,v,t", reg, reg, AT); | |
d6bc6245 TS |
3880 | *used_at = 1; |
3881 | } | |
3882 | else | |
3883 | { | |
67c0d1eb RS |
3884 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_HIGHEST); |
3885 | macro_build (ep, "daddiu", "t,r,j", reg, reg, | |
3886 | BFD_RELOC_MIPS_HIGHER); | |
3887 | macro_build (NULL, "dsll", "d,w,<", reg, reg, 16); | |
3888 | macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_HI16_S); | |
3889 | macro_build (NULL, "dsll", "d,w,<", reg, reg, 16); | |
3890 | macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_LO16); | |
d6bc6245 TS |
3891 | } |
3892 | } | |
252b5132 RH |
3893 | else |
3894 | { | |
d6bc6245 TS |
3895 | if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET |
3896 | && ! nopic_need_relax (ep->X_add_symbol, 1)) | |
3897 | { | |
4d7206a2 | 3898 | relax_start (ep->X_add_symbol); |
67c0d1eb | 3899 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, |
17a2f251 | 3900 | mips_gp_register, BFD_RELOC_GPREL16); |
4d7206a2 | 3901 | relax_switch (); |
d6bc6245 | 3902 | } |
67c0d1eb RS |
3903 | macro_build_lui (ep, reg); |
3904 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", | |
3905 | reg, reg, BFD_RELOC_LO16); | |
4d7206a2 RS |
3906 | if (mips_relax.sequence) |
3907 | relax_end (); | |
d6bc6245 | 3908 | } |
252b5132 RH |
3909 | } |
3910 | else if (mips_pic == SVR4_PIC && ! mips_big_got) | |
3911 | { | |
3912 | expressionS ex; | |
3913 | ||
3914 | /* If this is a reference to an external symbol, we want | |
3915 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3916 | Otherwise we want | |
3917 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3918 | nop | |
3919 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
f5040a92 AO |
3920 | If there is a constant, it must be added in after. |
3921 | ||
ed6fb7bd | 3922 | If we have NewABI, we want |
f5040a92 AO |
3923 | lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP) |
3924 | unless we're referencing a global symbol with a non-zero | |
3925 | offset, in which case cst must be added separately. */ | |
ed6fb7bd SC |
3926 | if (HAVE_NEWABI) |
3927 | { | |
f5040a92 AO |
3928 | if (ep->X_add_number) |
3929 | { | |
4d7206a2 | 3930 | ex.X_add_number = ep->X_add_number; |
f5040a92 | 3931 | ep->X_add_number = 0; |
4d7206a2 | 3932 | relax_start (ep->X_add_symbol); |
67c0d1eb RS |
3933 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
3934 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
3935 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) |
3936 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
3937 | ex.X_op = O_constant; | |
67c0d1eb | 3938 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 3939 | reg, reg, BFD_RELOC_LO16); |
f5040a92 | 3940 | ep->X_add_number = ex.X_add_number; |
4d7206a2 | 3941 | relax_switch (); |
f5040a92 | 3942 | } |
67c0d1eb | 3943 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 3944 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); |
4d7206a2 RS |
3945 | if (mips_relax.sequence) |
3946 | relax_end (); | |
ed6fb7bd SC |
3947 | } |
3948 | else | |
3949 | { | |
f5040a92 AO |
3950 | ex.X_add_number = ep->X_add_number; |
3951 | ep->X_add_number = 0; | |
67c0d1eb RS |
3952 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
3953 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 3954 | load_delay_nop (); |
4d7206a2 RS |
3955 | relax_start (ep->X_add_symbol); |
3956 | relax_switch (); | |
67c0d1eb | 3957 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
17a2f251 | 3958 | BFD_RELOC_LO16); |
4d7206a2 | 3959 | relax_end (); |
ed6fb7bd | 3960 | |
f5040a92 AO |
3961 | if (ex.X_add_number != 0) |
3962 | { | |
3963 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
3964 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
3965 | ex.X_op = O_constant; | |
67c0d1eb | 3966 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 3967 | reg, reg, BFD_RELOC_LO16); |
f5040a92 | 3968 | } |
252b5132 RH |
3969 | } |
3970 | } | |
3971 | else if (mips_pic == SVR4_PIC) | |
3972 | { | |
3973 | expressionS ex; | |
252b5132 RH |
3974 | |
3975 | /* This is the large GOT case. If this is a reference to an | |
3976 | external symbol, we want | |
3977 | lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
3978 | addu $reg,$reg,$gp | |
3979 | lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16) | |
f5040a92 AO |
3980 | |
3981 | Otherwise, for a reference to a local symbol in old ABI, we want | |
252b5132 RH |
3982 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) |
3983 | nop | |
3984 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
684022ea | 3985 | If there is a constant, it must be added in after. |
f5040a92 AO |
3986 | |
3987 | In the NewABI, for local symbols, with or without offsets, we want: | |
438c16b8 TS |
3988 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) |
3989 | addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) | |
f5040a92 | 3990 | */ |
438c16b8 TS |
3991 | if (HAVE_NEWABI) |
3992 | { | |
4d7206a2 | 3993 | ex.X_add_number = ep->X_add_number; |
f5040a92 | 3994 | ep->X_add_number = 0; |
4d7206a2 | 3995 | relax_start (ep->X_add_symbol); |
67c0d1eb RS |
3996 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_GOT_HI16); |
3997 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
3998 | reg, reg, mips_gp_register); | |
3999 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", | |
4000 | reg, BFD_RELOC_MIPS_GOT_LO16, reg); | |
f5040a92 AO |
4001 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) |
4002 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4003 | else if (ex.X_add_number) | |
4004 | { | |
4005 | ex.X_op = O_constant; | |
67c0d1eb RS |
4006 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
4007 | BFD_RELOC_LO16); | |
f5040a92 AO |
4008 | } |
4009 | ||
4010 | ep->X_add_number = ex.X_add_number; | |
4d7206a2 | 4011 | relax_switch (); |
67c0d1eb | 4012 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 4013 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); |
67c0d1eb RS |
4014 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
4015 | BFD_RELOC_MIPS_GOT_OFST); | |
4d7206a2 | 4016 | relax_end (); |
438c16b8 | 4017 | } |
252b5132 | 4018 | else |
438c16b8 | 4019 | { |
f5040a92 AO |
4020 | ex.X_add_number = ep->X_add_number; |
4021 | ep->X_add_number = 0; | |
4d7206a2 | 4022 | relax_start (ep->X_add_symbol); |
67c0d1eb RS |
4023 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_GOT_HI16); |
4024 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
4025 | reg, reg, mips_gp_register); | |
4026 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", | |
4027 | reg, BFD_RELOC_MIPS_GOT_LO16, reg); | |
4d7206a2 RS |
4028 | relax_switch (); |
4029 | if (reg_needs_delay (mips_gp_register)) | |
438c16b8 TS |
4030 | { |
4031 | /* We need a nop before loading from $gp. This special | |
4032 | check is required because the lui which starts the main | |
4033 | instruction stream does not refer to $gp, and so will not | |
4034 | insert the nop which may be required. */ | |
67c0d1eb | 4035 | macro_build (NULL, "nop", ""); |
438c16b8 | 4036 | } |
67c0d1eb | 4037 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 4038 | BFD_RELOC_MIPS_GOT16, mips_gp_register); |
269137b2 | 4039 | load_delay_nop (); |
67c0d1eb | 4040 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
17a2f251 | 4041 | BFD_RELOC_LO16); |
4d7206a2 | 4042 | relax_end (); |
438c16b8 | 4043 | |
f5040a92 AO |
4044 | if (ex.X_add_number != 0) |
4045 | { | |
4046 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
4047 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4048 | ex.X_op = O_constant; | |
67c0d1eb RS |
4049 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
4050 | BFD_RELOC_LO16); | |
f5040a92 | 4051 | } |
252b5132 RH |
4052 | } |
4053 | } | |
252b5132 RH |
4054 | else |
4055 | abort (); | |
8fc2e39e TS |
4056 | |
4057 | if (mips_opts.noat && *used_at == 1) | |
4058 | as_bad (_("Macro used $at after \".set noat\"")); | |
252b5132 RH |
4059 | } |
4060 | ||
ea1fb5dc RS |
4061 | /* Move the contents of register SOURCE into register DEST. */ |
4062 | ||
4063 | static void | |
67c0d1eb | 4064 | move_register (int dest, int source) |
ea1fb5dc | 4065 | { |
67c0d1eb RS |
4066 | macro_build (NULL, HAVE_32BIT_GPRS ? "addu" : "daddu", "d,v,t", |
4067 | dest, source, 0); | |
ea1fb5dc RS |
4068 | } |
4069 | ||
4d7206a2 | 4070 | /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where |
f6a22291 MR |
4071 | LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement. |
4072 | The two alternatives are: | |
4d7206a2 RS |
4073 | |
4074 | Global symbol Local sybmol | |
4075 | ------------- ------------ | |
4076 | lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET) | |
4077 | ... ... | |
4078 | addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET) | |
4079 | ||
4080 | load_got_offset emits the first instruction and add_got_offset | |
f6a22291 MR |
4081 | emits the second for a 16-bit offset or add_got_offset_hilo emits |
4082 | a sequence to add a 32-bit offset using a scratch register. */ | |
4d7206a2 RS |
4083 | |
4084 | static void | |
67c0d1eb | 4085 | load_got_offset (int dest, expressionS *local) |
4d7206a2 RS |
4086 | { |
4087 | expressionS global; | |
4088 | ||
4089 | global = *local; | |
4090 | global.X_add_number = 0; | |
4091 | ||
4092 | relax_start (local->X_add_symbol); | |
67c0d1eb RS |
4093 | macro_build (&global, ADDRESS_LOAD_INSN, "t,o(b)", dest, |
4094 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
4d7206a2 | 4095 | relax_switch (); |
67c0d1eb RS |
4096 | macro_build (local, ADDRESS_LOAD_INSN, "t,o(b)", dest, |
4097 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
4d7206a2 RS |
4098 | relax_end (); |
4099 | } | |
4100 | ||
4101 | static void | |
67c0d1eb | 4102 | add_got_offset (int dest, expressionS *local) |
4d7206a2 RS |
4103 | { |
4104 | expressionS global; | |
4105 | ||
4106 | global.X_op = O_constant; | |
4107 | global.X_op_symbol = NULL; | |
4108 | global.X_add_symbol = NULL; | |
4109 | global.X_add_number = local->X_add_number; | |
4110 | ||
4111 | relax_start (local->X_add_symbol); | |
67c0d1eb | 4112 | macro_build (&global, ADDRESS_ADDI_INSN, "t,r,j", |
4d7206a2 RS |
4113 | dest, dest, BFD_RELOC_LO16); |
4114 | relax_switch (); | |
67c0d1eb | 4115 | macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", dest, dest, BFD_RELOC_LO16); |
4d7206a2 RS |
4116 | relax_end (); |
4117 | } | |
4118 | ||
f6a22291 MR |
4119 | static void |
4120 | add_got_offset_hilo (int dest, expressionS *local, int tmp) | |
4121 | { | |
4122 | expressionS global; | |
4123 | int hold_mips_optimize; | |
4124 | ||
4125 | global.X_op = O_constant; | |
4126 | global.X_op_symbol = NULL; | |
4127 | global.X_add_symbol = NULL; | |
4128 | global.X_add_number = local->X_add_number; | |
4129 | ||
4130 | relax_start (local->X_add_symbol); | |
4131 | load_register (tmp, &global, HAVE_64BIT_ADDRESSES); | |
4132 | relax_switch (); | |
4133 | /* Set mips_optimize around the lui instruction to avoid | |
4134 | inserting an unnecessary nop after the lw. */ | |
4135 | hold_mips_optimize = mips_optimize; | |
4136 | mips_optimize = 2; | |
4137 | macro_build_lui (&global, tmp); | |
4138 | mips_optimize = hold_mips_optimize; | |
4139 | macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", tmp, tmp, BFD_RELOC_LO16); | |
4140 | relax_end (); | |
4141 | ||
4142 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dest, dest, tmp); | |
4143 | } | |
4144 | ||
252b5132 RH |
4145 | /* |
4146 | * Build macros | |
4147 | * This routine implements the seemingly endless macro or synthesized | |
4148 | * instructions and addressing modes in the mips assembly language. Many | |
4149 | * of these macros are simple and are similar to each other. These could | |
67c1ffbe | 4150 | * probably be handled by some kind of table or grammar approach instead of |
252b5132 RH |
4151 | * this verbose method. Others are not simple macros but are more like |
4152 | * optimizing code generation. | |
4153 | * One interesting optimization is when several store macros appear | |
67c1ffbe | 4154 | * consecutively that would load AT with the upper half of the same address. |
252b5132 RH |
4155 | * The ensuing load upper instructions are ommited. This implies some kind |
4156 | * of global optimization. We currently only optimize within a single macro. | |
4157 | * For many of the load and store macros if the address is specified as a | |
4158 | * constant expression in the first 64k of memory (ie ld $2,0x4000c) we | |
4159 | * first load register 'at' with zero and use it as the base register. The | |
4160 | * mips assembler simply uses register $zero. Just one tiny optimization | |
4161 | * we're missing. | |
4162 | */ | |
4163 | static void | |
17a2f251 | 4164 | macro (struct mips_cl_insn *ip) |
252b5132 RH |
4165 | { |
4166 | register int treg, sreg, dreg, breg; | |
4167 | int tempreg; | |
4168 | int mask; | |
43841e91 | 4169 | int used_at = 0; |
252b5132 RH |
4170 | expressionS expr1; |
4171 | const char *s; | |
4172 | const char *s2; | |
4173 | const char *fmt; | |
4174 | int likely = 0; | |
4175 | int dbl = 0; | |
4176 | int coproc = 0; | |
4177 | int lr = 0; | |
4178 | int imm = 0; | |
1abe91b1 | 4179 | int call = 0; |
252b5132 | 4180 | int off; |
67c0d1eb | 4181 | offsetT maxnum; |
252b5132 | 4182 | bfd_reloc_code_real_type r; |
252b5132 RH |
4183 | int hold_mips_optimize; |
4184 | ||
4185 | assert (! mips_opts.mips16); | |
4186 | ||
4187 | treg = (ip->insn_opcode >> 16) & 0x1f; | |
4188 | dreg = (ip->insn_opcode >> 11) & 0x1f; | |
4189 | sreg = breg = (ip->insn_opcode >> 21) & 0x1f; | |
4190 | mask = ip->insn_mo->mask; | |
4191 | ||
4192 | expr1.X_op = O_constant; | |
4193 | expr1.X_op_symbol = NULL; | |
4194 | expr1.X_add_symbol = NULL; | |
4195 | expr1.X_add_number = 1; | |
4196 | ||
4197 | switch (mask) | |
4198 | { | |
4199 | case M_DABS: | |
4200 | dbl = 1; | |
4201 | case M_ABS: | |
4202 | /* bgez $a0,.+12 | |
4203 | move v0,$a0 | |
4204 | sub v0,$zero,$a0 | |
4205 | */ | |
4206 | ||
b34976b6 | 4207 | mips_emit_delays (TRUE); |
252b5132 RH |
4208 | ++mips_opts.noreorder; |
4209 | mips_any_noreorder = 1; | |
4210 | ||
4211 | expr1.X_add_number = 8; | |
67c0d1eb | 4212 | macro_build (&expr1, "bgez", "s,p", sreg); |
252b5132 | 4213 | if (dreg == sreg) |
67c0d1eb | 4214 | macro_build (NULL, "nop", "", 0); |
252b5132 | 4215 | else |
67c0d1eb RS |
4216 | move_register (dreg, sreg); |
4217 | macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, 0, sreg); | |
252b5132 RH |
4218 | |
4219 | --mips_opts.noreorder; | |
8fc2e39e | 4220 | break; |
252b5132 RH |
4221 | |
4222 | case M_ADD_I: | |
4223 | s = "addi"; | |
4224 | s2 = "add"; | |
4225 | goto do_addi; | |
4226 | case M_ADDU_I: | |
4227 | s = "addiu"; | |
4228 | s2 = "addu"; | |
4229 | goto do_addi; | |
4230 | case M_DADD_I: | |
4231 | dbl = 1; | |
4232 | s = "daddi"; | |
4233 | s2 = "dadd"; | |
4234 | goto do_addi; | |
4235 | case M_DADDU_I: | |
4236 | dbl = 1; | |
4237 | s = "daddiu"; | |
4238 | s2 = "daddu"; | |
4239 | do_addi: | |
4240 | if (imm_expr.X_op == O_constant | |
4241 | && imm_expr.X_add_number >= -0x8000 | |
4242 | && imm_expr.X_add_number < 0x8000) | |
4243 | { | |
67c0d1eb | 4244 | macro_build (&imm_expr, s, "t,r,j", treg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 4245 | break; |
252b5132 | 4246 | } |
8fc2e39e | 4247 | used_at = 1; |
67c0d1eb RS |
4248 | load_register (AT, &imm_expr, dbl); |
4249 | macro_build (NULL, s2, "d,v,t", treg, sreg, AT); | |
252b5132 RH |
4250 | break; |
4251 | ||
4252 | case M_AND_I: | |
4253 | s = "andi"; | |
4254 | s2 = "and"; | |
4255 | goto do_bit; | |
4256 | case M_OR_I: | |
4257 | s = "ori"; | |
4258 | s2 = "or"; | |
4259 | goto do_bit; | |
4260 | case M_NOR_I: | |
4261 | s = ""; | |
4262 | s2 = "nor"; | |
4263 | goto do_bit; | |
4264 | case M_XOR_I: | |
4265 | s = "xori"; | |
4266 | s2 = "xor"; | |
4267 | do_bit: | |
4268 | if (imm_expr.X_op == O_constant | |
4269 | && imm_expr.X_add_number >= 0 | |
4270 | && imm_expr.X_add_number < 0x10000) | |
4271 | { | |
4272 | if (mask != M_NOR_I) | |
67c0d1eb | 4273 | macro_build (&imm_expr, s, "t,r,i", treg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
4274 | else |
4275 | { | |
67c0d1eb RS |
4276 | macro_build (&imm_expr, "ori", "t,r,i", |
4277 | treg, sreg, BFD_RELOC_LO16); | |
4278 | macro_build (NULL, "nor", "d,v,t", treg, treg, 0); | |
252b5132 | 4279 | } |
8fc2e39e | 4280 | break; |
252b5132 RH |
4281 | } |
4282 | ||
8fc2e39e | 4283 | used_at = 1; |
67c0d1eb RS |
4284 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
4285 | macro_build (NULL, s2, "d,v,t", treg, sreg, AT); | |
252b5132 RH |
4286 | break; |
4287 | ||
4288 | case M_BEQ_I: | |
4289 | s = "beq"; | |
4290 | goto beq_i; | |
4291 | case M_BEQL_I: | |
4292 | s = "beql"; | |
4293 | likely = 1; | |
4294 | goto beq_i; | |
4295 | case M_BNE_I: | |
4296 | s = "bne"; | |
4297 | goto beq_i; | |
4298 | case M_BNEL_I: | |
4299 | s = "bnel"; | |
4300 | likely = 1; | |
4301 | beq_i: | |
4302 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4303 | { | |
67c0d1eb | 4304 | macro_build (&offset_expr, s, "s,t,p", sreg, 0); |
8fc2e39e | 4305 | break; |
252b5132 | 4306 | } |
8fc2e39e | 4307 | used_at = 1; |
67c0d1eb RS |
4308 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
4309 | macro_build (&offset_expr, s, "s,t,p", sreg, AT); | |
252b5132 RH |
4310 | break; |
4311 | ||
4312 | case M_BGEL: | |
4313 | likely = 1; | |
4314 | case M_BGE: | |
4315 | if (treg == 0) | |
4316 | { | |
67c0d1eb | 4317 | macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", sreg); |
8fc2e39e | 4318 | break; |
252b5132 RH |
4319 | } |
4320 | if (sreg == 0) | |
4321 | { | |
67c0d1eb | 4322 | macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", treg); |
8fc2e39e | 4323 | break; |
252b5132 | 4324 | } |
8fc2e39e | 4325 | used_at = 1; |
67c0d1eb RS |
4326 | macro_build (NULL, "slt", "d,v,t", AT, sreg, treg); |
4327 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
4328 | break; |
4329 | ||
4330 | case M_BGTL_I: | |
4331 | likely = 1; | |
4332 | case M_BGT_I: | |
4333 | /* check for > max integer */ | |
4334 | maxnum = 0x7fffffff; | |
ca4e0257 | 4335 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
4336 | { |
4337 | maxnum <<= 16; | |
4338 | maxnum |= 0xffff; | |
4339 | maxnum <<= 16; | |
4340 | maxnum |= 0xffff; | |
4341 | } | |
4342 | if (imm_expr.X_op == O_constant | |
4343 | && imm_expr.X_add_number >= maxnum | |
ca4e0257 | 4344 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
4345 | { |
4346 | do_false: | |
4347 | /* result is always false */ | |
4348 | if (! likely) | |
67c0d1eb | 4349 | macro_build (NULL, "nop", "", 0); |
252b5132 | 4350 | else |
67c0d1eb | 4351 | macro_build (&offset_expr, "bnel", "s,t,p", 0, 0); |
8fc2e39e | 4352 | break; |
252b5132 RH |
4353 | } |
4354 | if (imm_expr.X_op != O_constant) | |
4355 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 4356 | ++imm_expr.X_add_number; |
252b5132 RH |
4357 | /* FALLTHROUGH */ |
4358 | case M_BGE_I: | |
4359 | case M_BGEL_I: | |
4360 | if (mask == M_BGEL_I) | |
4361 | likely = 1; | |
4362 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4363 | { | |
67c0d1eb | 4364 | macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", sreg); |
8fc2e39e | 4365 | break; |
252b5132 RH |
4366 | } |
4367 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4368 | { | |
67c0d1eb | 4369 | macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", sreg); |
8fc2e39e | 4370 | break; |
252b5132 RH |
4371 | } |
4372 | maxnum = 0x7fffffff; | |
ca4e0257 | 4373 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
4374 | { |
4375 | maxnum <<= 16; | |
4376 | maxnum |= 0xffff; | |
4377 | maxnum <<= 16; | |
4378 | maxnum |= 0xffff; | |
4379 | } | |
4380 | maxnum = - maxnum - 1; | |
4381 | if (imm_expr.X_op == O_constant | |
4382 | && imm_expr.X_add_number <= maxnum | |
ca4e0257 | 4383 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
4384 | { |
4385 | do_true: | |
4386 | /* result is always true */ | |
4387 | as_warn (_("Branch %s is always true"), ip->insn_mo->name); | |
67c0d1eb | 4388 | macro_build (&offset_expr, "b", "p"); |
8fc2e39e | 4389 | break; |
252b5132 | 4390 | } |
8fc2e39e | 4391 | used_at = 1; |
67c0d1eb RS |
4392 | set_at (sreg, 0); |
4393 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
4394 | break; |
4395 | ||
4396 | case M_BGEUL: | |
4397 | likely = 1; | |
4398 | case M_BGEU: | |
4399 | if (treg == 0) | |
4400 | goto do_true; | |
4401 | if (sreg == 0) | |
4402 | { | |
67c0d1eb | 4403 | macro_build (&offset_expr, likely ? "beql" : "beq", |
17a2f251 | 4404 | "s,t,p", 0, treg); |
8fc2e39e | 4405 | break; |
252b5132 | 4406 | } |
8fc2e39e | 4407 | used_at = 1; |
67c0d1eb RS |
4408 | macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg); |
4409 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
4410 | break; |
4411 | ||
4412 | case M_BGTUL_I: | |
4413 | likely = 1; | |
4414 | case M_BGTU_I: | |
4415 | if (sreg == 0 | |
ca4e0257 | 4416 | || (HAVE_32BIT_GPRS |
252b5132 | 4417 | && imm_expr.X_op == O_constant |
956cd1d6 | 4418 | && imm_expr.X_add_number == (offsetT) 0xffffffff)) |
252b5132 RH |
4419 | goto do_false; |
4420 | if (imm_expr.X_op != O_constant) | |
4421 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 4422 | ++imm_expr.X_add_number; |
252b5132 RH |
4423 | /* FALLTHROUGH */ |
4424 | case M_BGEU_I: | |
4425 | case M_BGEUL_I: | |
4426 | if (mask == M_BGEUL_I) | |
4427 | likely = 1; | |
4428 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4429 | goto do_true; | |
4430 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4431 | { | |
67c0d1eb | 4432 | macro_build (&offset_expr, likely ? "bnel" : "bne", |
17a2f251 | 4433 | "s,t,p", sreg, 0); |
8fc2e39e | 4434 | break; |
252b5132 | 4435 | } |
8fc2e39e | 4436 | used_at = 1; |
67c0d1eb RS |
4437 | set_at (sreg, 1); |
4438 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
4439 | break; |
4440 | ||
4441 | case M_BGTL: | |
4442 | likely = 1; | |
4443 | case M_BGT: | |
4444 | if (treg == 0) | |
4445 | { | |
67c0d1eb | 4446 | macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", sreg); |
8fc2e39e | 4447 | break; |
252b5132 RH |
4448 | } |
4449 | if (sreg == 0) | |
4450 | { | |
67c0d1eb | 4451 | macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", treg); |
8fc2e39e | 4452 | break; |
252b5132 | 4453 | } |
8fc2e39e | 4454 | used_at = 1; |
67c0d1eb RS |
4455 | macro_build (NULL, "slt", "d,v,t", AT, treg, sreg); |
4456 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
4457 | break; |
4458 | ||
4459 | case M_BGTUL: | |
4460 | likely = 1; | |
4461 | case M_BGTU: | |
4462 | if (treg == 0) | |
4463 | { | |
67c0d1eb | 4464 | macro_build (&offset_expr, likely ? "bnel" : "bne", |
17a2f251 | 4465 | "s,t,p", sreg, 0); |
8fc2e39e | 4466 | break; |
252b5132 RH |
4467 | } |
4468 | if (sreg == 0) | |
4469 | goto do_false; | |
8fc2e39e | 4470 | used_at = 1; |
67c0d1eb RS |
4471 | macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg); |
4472 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
4473 | break; |
4474 | ||
4475 | case M_BLEL: | |
4476 | likely = 1; | |
4477 | case M_BLE: | |
4478 | if (treg == 0) | |
4479 | { | |
67c0d1eb | 4480 | macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", sreg); |
8fc2e39e | 4481 | break; |
252b5132 RH |
4482 | } |
4483 | if (sreg == 0) | |
4484 | { | |
67c0d1eb | 4485 | macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", treg); |
8fc2e39e | 4486 | break; |
252b5132 | 4487 | } |
8fc2e39e | 4488 | used_at = 1; |
67c0d1eb RS |
4489 | macro_build (NULL, "slt", "d,v,t", AT, treg, sreg); |
4490 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
4491 | break; |
4492 | ||
4493 | case M_BLEL_I: | |
4494 | likely = 1; | |
4495 | case M_BLE_I: | |
4496 | maxnum = 0x7fffffff; | |
ca4e0257 | 4497 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
4498 | { |
4499 | maxnum <<= 16; | |
4500 | maxnum |= 0xffff; | |
4501 | maxnum <<= 16; | |
4502 | maxnum |= 0xffff; | |
4503 | } | |
4504 | if (imm_expr.X_op == O_constant | |
4505 | && imm_expr.X_add_number >= maxnum | |
ca4e0257 | 4506 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
4507 | goto do_true; |
4508 | if (imm_expr.X_op != O_constant) | |
4509 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 4510 | ++imm_expr.X_add_number; |
252b5132 RH |
4511 | /* FALLTHROUGH */ |
4512 | case M_BLT_I: | |
4513 | case M_BLTL_I: | |
4514 | if (mask == M_BLTL_I) | |
4515 | likely = 1; | |
4516 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4517 | { | |
67c0d1eb | 4518 | macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", sreg); |
8fc2e39e | 4519 | break; |
252b5132 RH |
4520 | } |
4521 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4522 | { | |
67c0d1eb | 4523 | macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", sreg); |
8fc2e39e | 4524 | break; |
252b5132 | 4525 | } |
8fc2e39e | 4526 | used_at = 1; |
67c0d1eb RS |
4527 | set_at (sreg, 0); |
4528 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
4529 | break; |
4530 | ||
4531 | case M_BLEUL: | |
4532 | likely = 1; | |
4533 | case M_BLEU: | |
4534 | if (treg == 0) | |
4535 | { | |
67c0d1eb | 4536 | macro_build (&offset_expr, likely ? "beql" : "beq", |
17a2f251 | 4537 | "s,t,p", sreg, 0); |
8fc2e39e | 4538 | break; |
252b5132 RH |
4539 | } |
4540 | if (sreg == 0) | |
4541 | goto do_true; | |
8fc2e39e | 4542 | used_at = 1; |
67c0d1eb RS |
4543 | macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg); |
4544 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
4545 | break; |
4546 | ||
4547 | case M_BLEUL_I: | |
4548 | likely = 1; | |
4549 | case M_BLEU_I: | |
4550 | if (sreg == 0 | |
ca4e0257 | 4551 | || (HAVE_32BIT_GPRS |
252b5132 | 4552 | && imm_expr.X_op == O_constant |
956cd1d6 | 4553 | && imm_expr.X_add_number == (offsetT) 0xffffffff)) |
252b5132 RH |
4554 | goto do_true; |
4555 | if (imm_expr.X_op != O_constant) | |
4556 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 4557 | ++imm_expr.X_add_number; |
252b5132 RH |
4558 | /* FALLTHROUGH */ |
4559 | case M_BLTU_I: | |
4560 | case M_BLTUL_I: | |
4561 | if (mask == M_BLTUL_I) | |
4562 | likely = 1; | |
4563 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4564 | goto do_false; | |
4565 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4566 | { | |
67c0d1eb | 4567 | macro_build (&offset_expr, likely ? "beql" : "beq", |
252b5132 | 4568 | "s,t,p", sreg, 0); |
8fc2e39e | 4569 | break; |
252b5132 | 4570 | } |
8fc2e39e | 4571 | used_at = 1; |
67c0d1eb RS |
4572 | set_at (sreg, 1); |
4573 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
4574 | break; |
4575 | ||
4576 | case M_BLTL: | |
4577 | likely = 1; | |
4578 | case M_BLT: | |
4579 | if (treg == 0) | |
4580 | { | |
67c0d1eb | 4581 | macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", sreg); |
8fc2e39e | 4582 | break; |
252b5132 RH |
4583 | } |
4584 | if (sreg == 0) | |
4585 | { | |
67c0d1eb | 4586 | macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", treg); |
8fc2e39e | 4587 | break; |
252b5132 | 4588 | } |
8fc2e39e | 4589 | used_at = 1; |
67c0d1eb RS |
4590 | macro_build (NULL, "slt", "d,v,t", AT, sreg, treg); |
4591 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
4592 | break; |
4593 | ||
4594 | case M_BLTUL: | |
4595 | likely = 1; | |
4596 | case M_BLTU: | |
4597 | if (treg == 0) | |
4598 | goto do_false; | |
4599 | if (sreg == 0) | |
4600 | { | |
67c0d1eb | 4601 | macro_build (&offset_expr, likely ? "bnel" : "bne", |
17a2f251 | 4602 | "s,t,p", 0, treg); |
8fc2e39e | 4603 | break; |
252b5132 | 4604 | } |
8fc2e39e | 4605 | used_at = 1; |
67c0d1eb RS |
4606 | macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg); |
4607 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
4608 | break; |
4609 | ||
5f74bc13 CD |
4610 | case M_DEXT: |
4611 | { | |
4612 | unsigned long pos; | |
4613 | unsigned long size; | |
4614 | ||
4615 | if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant) | |
4616 | { | |
4617 | as_bad (_("Unsupported large constant")); | |
4618 | pos = size = 1; | |
4619 | } | |
4620 | else | |
4621 | { | |
4622 | pos = (unsigned long) imm_expr.X_add_number; | |
4623 | size = (unsigned long) imm2_expr.X_add_number; | |
4624 | } | |
4625 | ||
4626 | if (pos > 63) | |
4627 | { | |
4628 | as_bad (_("Improper position (%lu)"), pos); | |
4629 | pos = 1; | |
4630 | } | |
4631 | if (size == 0 || size > 64 | |
4632 | || (pos + size - 1) > 63) | |
4633 | { | |
4634 | as_bad (_("Improper extract size (%lu, position %lu)"), | |
4635 | size, pos); | |
4636 | size = 1; | |
4637 | } | |
4638 | ||
4639 | if (size <= 32 && pos < 32) | |
4640 | { | |
4641 | s = "dext"; | |
4642 | fmt = "t,r,+A,+C"; | |
4643 | } | |
4644 | else if (size <= 32) | |
4645 | { | |
4646 | s = "dextu"; | |
4647 | fmt = "t,r,+E,+H"; | |
4648 | } | |
4649 | else | |
4650 | { | |
4651 | s = "dextm"; | |
4652 | fmt = "t,r,+A,+G"; | |
4653 | } | |
67c0d1eb | 4654 | macro_build ((expressionS *) NULL, s, fmt, treg, sreg, pos, size - 1); |
5f74bc13 | 4655 | } |
8fc2e39e | 4656 | break; |
5f74bc13 CD |
4657 | |
4658 | case M_DINS: | |
4659 | { | |
4660 | unsigned long pos; | |
4661 | unsigned long size; | |
4662 | ||
4663 | if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant) | |
4664 | { | |
4665 | as_bad (_("Unsupported large constant")); | |
4666 | pos = size = 1; | |
4667 | } | |
4668 | else | |
4669 | { | |
4670 | pos = (unsigned long) imm_expr.X_add_number; | |
4671 | size = (unsigned long) imm2_expr.X_add_number; | |
4672 | } | |
4673 | ||
4674 | if (pos > 63) | |
4675 | { | |
4676 | as_bad (_("Improper position (%lu)"), pos); | |
4677 | pos = 1; | |
4678 | } | |
4679 | if (size == 0 || size > 64 | |
4680 | || (pos + size - 1) > 63) | |
4681 | { | |
4682 | as_bad (_("Improper insert size (%lu, position %lu)"), | |
4683 | size, pos); | |
4684 | size = 1; | |
4685 | } | |
4686 | ||
4687 | if (pos < 32 && (pos + size - 1) < 32) | |
4688 | { | |
4689 | s = "dins"; | |
4690 | fmt = "t,r,+A,+B"; | |
4691 | } | |
4692 | else if (pos >= 32) | |
4693 | { | |
4694 | s = "dinsu"; | |
4695 | fmt = "t,r,+E,+F"; | |
4696 | } | |
4697 | else | |
4698 | { | |
4699 | s = "dinsm"; | |
4700 | fmt = "t,r,+A,+F"; | |
4701 | } | |
67c0d1eb RS |
4702 | macro_build ((expressionS *) NULL, s, fmt, treg, sreg, pos, |
4703 | pos + size - 1); | |
5f74bc13 | 4704 | } |
8fc2e39e | 4705 | break; |
5f74bc13 | 4706 | |
252b5132 RH |
4707 | case M_DDIV_3: |
4708 | dbl = 1; | |
4709 | case M_DIV_3: | |
4710 | s = "mflo"; | |
4711 | goto do_div3; | |
4712 | case M_DREM_3: | |
4713 | dbl = 1; | |
4714 | case M_REM_3: | |
4715 | s = "mfhi"; | |
4716 | do_div3: | |
4717 | if (treg == 0) | |
4718 | { | |
4719 | as_warn (_("Divide by zero.")); | |
4720 | if (mips_trap) | |
67c0d1eb | 4721 | macro_build (NULL, "teq", "s,t,q", 0, 0, 7); |
252b5132 | 4722 | else |
67c0d1eb | 4723 | macro_build (NULL, "break", "c", 7); |
8fc2e39e | 4724 | break; |
252b5132 RH |
4725 | } |
4726 | ||
b34976b6 | 4727 | mips_emit_delays (TRUE); |
252b5132 RH |
4728 | ++mips_opts.noreorder; |
4729 | mips_any_noreorder = 1; | |
4730 | if (mips_trap) | |
4731 | { | |
67c0d1eb RS |
4732 | macro_build (NULL, "teq", "s,t,q", treg, 0, 7); |
4733 | macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg); | |
252b5132 RH |
4734 | } |
4735 | else | |
4736 | { | |
4737 | expr1.X_add_number = 8; | |
67c0d1eb RS |
4738 | macro_build (&expr1, "bne", "s,t,p", treg, 0); |
4739 | macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg); | |
4740 | macro_build (NULL, "break", "c", 7); | |
252b5132 RH |
4741 | } |
4742 | expr1.X_add_number = -1; | |
8fc2e39e | 4743 | used_at = 1; |
f6a22291 | 4744 | load_register (AT, &expr1, dbl); |
252b5132 | 4745 | expr1.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16); |
67c0d1eb | 4746 | macro_build (&expr1, "bne", "s,t,p", treg, AT); |
252b5132 RH |
4747 | if (dbl) |
4748 | { | |
4749 | expr1.X_add_number = 1; | |
f6a22291 | 4750 | load_register (AT, &expr1, dbl); |
67c0d1eb | 4751 | macro_build (NULL, "dsll32", "d,w,<", AT, AT, 31); |
252b5132 RH |
4752 | } |
4753 | else | |
4754 | { | |
4755 | expr1.X_add_number = 0x80000000; | |
67c0d1eb | 4756 | macro_build (&expr1, "lui", "t,u", AT, BFD_RELOC_HI16); |
252b5132 RH |
4757 | } |
4758 | if (mips_trap) | |
4759 | { | |
67c0d1eb | 4760 | macro_build (NULL, "teq", "s,t,q", sreg, AT, 6); |
252b5132 RH |
4761 | /* We want to close the noreorder block as soon as possible, so |
4762 | that later insns are available for delay slot filling. */ | |
4763 | --mips_opts.noreorder; | |
4764 | } | |
4765 | else | |
4766 | { | |
4767 | expr1.X_add_number = 8; | |
67c0d1eb RS |
4768 | macro_build (&expr1, "bne", "s,t,p", sreg, AT); |
4769 | macro_build (NULL, "nop", "", 0); | |
252b5132 RH |
4770 | |
4771 | /* We want to close the noreorder block as soon as possible, so | |
4772 | that later insns are available for delay slot filling. */ | |
4773 | --mips_opts.noreorder; | |
4774 | ||
67c0d1eb | 4775 | macro_build (NULL, "break", "c", 6); |
252b5132 | 4776 | } |
67c0d1eb | 4777 | macro_build (NULL, s, "d", dreg); |
252b5132 RH |
4778 | break; |
4779 | ||
4780 | case M_DIV_3I: | |
4781 | s = "div"; | |
4782 | s2 = "mflo"; | |
4783 | goto do_divi; | |
4784 | case M_DIVU_3I: | |
4785 | s = "divu"; | |
4786 | s2 = "mflo"; | |
4787 | goto do_divi; | |
4788 | case M_REM_3I: | |
4789 | s = "div"; | |
4790 | s2 = "mfhi"; | |
4791 | goto do_divi; | |
4792 | case M_REMU_3I: | |
4793 | s = "divu"; | |
4794 | s2 = "mfhi"; | |
4795 | goto do_divi; | |
4796 | case M_DDIV_3I: | |
4797 | dbl = 1; | |
4798 | s = "ddiv"; | |
4799 | s2 = "mflo"; | |
4800 | goto do_divi; | |
4801 | case M_DDIVU_3I: | |
4802 | dbl = 1; | |
4803 | s = "ddivu"; | |
4804 | s2 = "mflo"; | |
4805 | goto do_divi; | |
4806 | case M_DREM_3I: | |
4807 | dbl = 1; | |
4808 | s = "ddiv"; | |
4809 | s2 = "mfhi"; | |
4810 | goto do_divi; | |
4811 | case M_DREMU_3I: | |
4812 | dbl = 1; | |
4813 | s = "ddivu"; | |
4814 | s2 = "mfhi"; | |
4815 | do_divi: | |
4816 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4817 | { | |
4818 | as_warn (_("Divide by zero.")); | |
4819 | if (mips_trap) | |
67c0d1eb | 4820 | macro_build (NULL, "teq", "s,t,q", 0, 0, 7); |
252b5132 | 4821 | else |
67c0d1eb | 4822 | macro_build (NULL, "break", "c", 7); |
8fc2e39e | 4823 | break; |
252b5132 RH |
4824 | } |
4825 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4826 | { | |
4827 | if (strcmp (s2, "mflo") == 0) | |
67c0d1eb | 4828 | move_register (dreg, sreg); |
252b5132 | 4829 | else |
67c0d1eb | 4830 | move_register (dreg, 0); |
8fc2e39e | 4831 | break; |
252b5132 RH |
4832 | } |
4833 | if (imm_expr.X_op == O_constant | |
4834 | && imm_expr.X_add_number == -1 | |
4835 | && s[strlen (s) - 1] != 'u') | |
4836 | { | |
4837 | if (strcmp (s2, "mflo") == 0) | |
4838 | { | |
67c0d1eb | 4839 | macro_build (NULL, dbl ? "dneg" : "neg", "d,w", dreg, sreg); |
252b5132 RH |
4840 | } |
4841 | else | |
67c0d1eb | 4842 | move_register (dreg, 0); |
8fc2e39e | 4843 | break; |
252b5132 RH |
4844 | } |
4845 | ||
8fc2e39e | 4846 | used_at = 1; |
67c0d1eb RS |
4847 | load_register (AT, &imm_expr, dbl); |
4848 | macro_build (NULL, s, "z,s,t", sreg, AT); | |
4849 | macro_build (NULL, s2, "d", dreg); | |
252b5132 RH |
4850 | break; |
4851 | ||
4852 | case M_DIVU_3: | |
4853 | s = "divu"; | |
4854 | s2 = "mflo"; | |
4855 | goto do_divu3; | |
4856 | case M_REMU_3: | |
4857 | s = "divu"; | |
4858 | s2 = "mfhi"; | |
4859 | goto do_divu3; | |
4860 | case M_DDIVU_3: | |
4861 | s = "ddivu"; | |
4862 | s2 = "mflo"; | |
4863 | goto do_divu3; | |
4864 | case M_DREMU_3: | |
4865 | s = "ddivu"; | |
4866 | s2 = "mfhi"; | |
4867 | do_divu3: | |
b34976b6 | 4868 | mips_emit_delays (TRUE); |
252b5132 RH |
4869 | ++mips_opts.noreorder; |
4870 | mips_any_noreorder = 1; | |
4871 | if (mips_trap) | |
4872 | { | |
67c0d1eb RS |
4873 | macro_build (NULL, "teq", "s,t,q", treg, 0, 7); |
4874 | macro_build (NULL, s, "z,s,t", sreg, treg); | |
252b5132 RH |
4875 | /* We want to close the noreorder block as soon as possible, so |
4876 | that later insns are available for delay slot filling. */ | |
4877 | --mips_opts.noreorder; | |
4878 | } | |
4879 | else | |
4880 | { | |
4881 | expr1.X_add_number = 8; | |
67c0d1eb RS |
4882 | macro_build (&expr1, "bne", "s,t,p", treg, 0); |
4883 | macro_build (NULL, s, "z,s,t", sreg, treg); | |
252b5132 RH |
4884 | |
4885 | /* We want to close the noreorder block as soon as possible, so | |
4886 | that later insns are available for delay slot filling. */ | |
4887 | --mips_opts.noreorder; | |
67c0d1eb | 4888 | macro_build (NULL, "break", "c", 7); |
252b5132 | 4889 | } |
67c0d1eb | 4890 | macro_build (NULL, s2, "d", dreg); |
8fc2e39e | 4891 | break; |
252b5132 | 4892 | |
1abe91b1 MR |
4893 | case M_DLCA_AB: |
4894 | dbl = 1; | |
4895 | case M_LCA_AB: | |
4896 | call = 1; | |
4897 | goto do_la; | |
252b5132 RH |
4898 | case M_DLA_AB: |
4899 | dbl = 1; | |
4900 | case M_LA_AB: | |
1abe91b1 | 4901 | do_la: |
252b5132 RH |
4902 | /* Load the address of a symbol into a register. If breg is not |
4903 | zero, we then add a base register to it. */ | |
4904 | ||
3bec30a8 TS |
4905 | if (dbl && HAVE_32BIT_GPRS) |
4906 | as_warn (_("dla used to load 32-bit register")); | |
4907 | ||
c90bbe5b | 4908 | if (! dbl && HAVE_64BIT_OBJECTS) |
3bec30a8 TS |
4909 | as_warn (_("la used to load 64-bit address")); |
4910 | ||
0c11417f MR |
4911 | if (offset_expr.X_op == O_constant |
4912 | && offset_expr.X_add_number >= -0x8000 | |
4913 | && offset_expr.X_add_number < 0x8000) | |
4914 | { | |
67c0d1eb | 4915 | macro_build (&offset_expr, |
b7c7d6c1 | 4916 | (dbl || HAVE_64BIT_ADDRESSES) ? "daddiu" : "addiu", |
17a2f251 | 4917 | "t,r,j", treg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 4918 | break; |
0c11417f MR |
4919 | } |
4920 | ||
b8285c27 | 4921 | if (!mips_opts.noat && (treg == breg)) |
afdbd6d0 CD |
4922 | { |
4923 | tempreg = AT; | |
4924 | used_at = 1; | |
4925 | } | |
4926 | else | |
4927 | { | |
4928 | tempreg = treg; | |
afdbd6d0 CD |
4929 | } |
4930 | ||
252b5132 RH |
4931 | if (offset_expr.X_op != O_symbol |
4932 | && offset_expr.X_op != O_constant) | |
4933 | { | |
4934 | as_bad (_("expression too complex")); | |
4935 | offset_expr.X_op = O_constant; | |
4936 | } | |
4937 | ||
252b5132 | 4938 | if (offset_expr.X_op == O_constant) |
67c0d1eb | 4939 | load_register (tempreg, &offset_expr, |
3e722fb5 | 4940 | (mips_pic == NO_PIC |
4d34fb5f TS |
4941 | ? (dbl || HAVE_64BIT_ADDRESSES) |
4942 | : HAVE_64BIT_ADDRESSES)); | |
252b5132 RH |
4943 | else if (mips_pic == NO_PIC) |
4944 | { | |
d6bc6245 | 4945 | /* If this is a reference to a GP relative symbol, we want |
cdf6fd85 | 4946 | addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
4947 | Otherwise we want |
4948 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
4949 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
4950 | If we have a constant, we need two instructions anyhow, | |
d6bc6245 | 4951 | so we may as well always use the latter form. |
76b3015f | 4952 | |
d6bc6245 TS |
4953 | With 64bit address space and a usable $at we want |
4954 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
4955 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
4956 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
4957 | daddiu $at,<sym> (BFD_RELOC_LO16) | |
4958 | dsll32 $tempreg,0 | |
3a482fd5 | 4959 | daddu $tempreg,$tempreg,$at |
76b3015f | 4960 | |
c03099e6 | 4961 | If $at is already in use, we use a path which is suboptimal |
d6bc6245 TS |
4962 | on superscalar processors. |
4963 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
4964 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
4965 | dsll $tempreg,16 | |
4966 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
4967 | dsll $tempreg,16 | |
4968 | daddiu $tempreg,<sym> (BFD_RELOC_LO16) | |
4969 | */ | |
d6bc6245 | 4970 | if (HAVE_64BIT_ADDRESSES) |
252b5132 | 4971 | { |
e864ceca RS |
4972 | /* ??? We don't provide a GP-relative alternative for |
4973 | these macros. It used not to be possible with the | |
4974 | original relaxation code, but it could be done now. */ | |
d6bc6245 | 4975 | |
b8285c27 | 4976 | if (used_at == 0 && !mips_opts.noat) |
98d3f06f | 4977 | { |
67c0d1eb | 4978 | macro_build (&offset_expr, "lui", "t,u", |
17a2f251 | 4979 | tempreg, BFD_RELOC_MIPS_HIGHEST); |
67c0d1eb | 4980 | macro_build (&offset_expr, "lui", "t,u", |
17a2f251 | 4981 | AT, BFD_RELOC_HI16_S); |
67c0d1eb | 4982 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 4983 | tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); |
67c0d1eb | 4984 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 4985 | AT, AT, BFD_RELOC_LO16); |
67c0d1eb RS |
4986 | macro_build (NULL, "dsll32", "d,w,<", tempreg, tempreg, 0); |
4987 | macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT); | |
98d3f06f KH |
4988 | used_at = 1; |
4989 | } | |
4990 | else | |
4991 | { | |
67c0d1eb | 4992 | macro_build (&offset_expr, "lui", "t,u", |
17a2f251 | 4993 | tempreg, BFD_RELOC_MIPS_HIGHEST); |
67c0d1eb | 4994 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 4995 | tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); |
67c0d1eb RS |
4996 | macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16); |
4997 | macro_build (&offset_expr, "daddiu", "t,r,j", | |
17a2f251 | 4998 | tempreg, tempreg, BFD_RELOC_HI16_S); |
67c0d1eb RS |
4999 | macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16); |
5000 | macro_build (&offset_expr, "daddiu", "t,r,j", | |
17a2f251 | 5001 | tempreg, tempreg, BFD_RELOC_LO16); |
98d3f06f KH |
5002 | } |
5003 | } | |
5004 | else | |
5005 | { | |
5006 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET | |
5007 | && ! nopic_need_relax (offset_expr.X_add_symbol, 1)) | |
5008 | { | |
4d7206a2 | 5009 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
5010 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
5011 | tempreg, mips_gp_register, BFD_RELOC_GPREL16); | |
4d7206a2 | 5012 | relax_switch (); |
98d3f06f | 5013 | } |
6943caf0 ILT |
5014 | if (!IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) |
5015 | as_bad (_("offset too large")); | |
67c0d1eb RS |
5016 | macro_build_lui (&offset_expr, tempreg); |
5017 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
5018 | tempreg, tempreg, BFD_RELOC_LO16); | |
4d7206a2 RS |
5019 | if (mips_relax.sequence) |
5020 | relax_end (); | |
98d3f06f | 5021 | } |
252b5132 | 5022 | } |
f5040a92 | 5023 | else if (mips_pic == SVR4_PIC && ! mips_big_got && ! HAVE_NEWABI) |
252b5132 | 5024 | { |
9117d219 NC |
5025 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
5026 | ||
252b5132 RH |
5027 | /* If this is a reference to an external symbol, and there |
5028 | is no constant, we want | |
5029 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
1abe91b1 | 5030 | or for lca or if tempreg is PIC_CALL_REG |
9117d219 | 5031 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
252b5132 RH |
5032 | For a local symbol, we want |
5033 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5034 | nop | |
5035 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
5036 | ||
5037 | If we have a small constant, and this is a reference to | |
5038 | an external symbol, we want | |
5039 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5040 | nop | |
5041 | addiu $tempreg,$tempreg,<constant> | |
5042 | For a local symbol, we want the same instruction | |
5043 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
5044 | addiu instruction. | |
5045 | ||
5046 | If we have a large constant, and this is a reference to | |
5047 | an external symbol, we want | |
5048 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5049 | lui $at,<hiconstant> | |
5050 | addiu $at,$at,<loconstant> | |
5051 | addu $tempreg,$tempreg,$at | |
5052 | For a local symbol, we want the same instruction | |
5053 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
ed6fb7bd | 5054 | addiu instruction. |
ed6fb7bd SC |
5055 | */ |
5056 | ||
4d7206a2 | 5057 | if (offset_expr.X_add_number == 0) |
252b5132 | 5058 | { |
4d7206a2 RS |
5059 | if (breg == 0 && (call || tempreg == PIC_CALL_REG)) |
5060 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16; | |
5061 | ||
5062 | relax_start (offset_expr.X_add_symbol); | |
67c0d1eb RS |
5063 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5064 | lw_reloc_type, mips_gp_register); | |
4d7206a2 | 5065 | if (breg != 0) |
252b5132 RH |
5066 | { |
5067 | /* We're going to put in an addu instruction using | |
5068 | tempreg, so we may as well insert the nop right | |
5069 | now. */ | |
269137b2 | 5070 | load_delay_nop (); |
252b5132 | 5071 | } |
4d7206a2 | 5072 | relax_switch (); |
67c0d1eb RS |
5073 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5074 | tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 5075 | load_delay_nop (); |
67c0d1eb RS |
5076 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
5077 | tempreg, tempreg, BFD_RELOC_LO16); | |
4d7206a2 | 5078 | relax_end (); |
252b5132 RH |
5079 | /* FIXME: If breg == 0, and the next instruction uses |
5080 | $tempreg, then if this variant case is used an extra | |
5081 | nop will be generated. */ | |
5082 | } | |
4d7206a2 RS |
5083 | else if (offset_expr.X_add_number >= -0x8000 |
5084 | && offset_expr.X_add_number < 0x8000) | |
252b5132 | 5085 | { |
67c0d1eb | 5086 | load_got_offset (tempreg, &offset_expr); |
269137b2 | 5087 | load_delay_nop (); |
67c0d1eb | 5088 | add_got_offset (tempreg, &offset_expr); |
252b5132 RH |
5089 | } |
5090 | else | |
5091 | { | |
4d7206a2 RS |
5092 | expr1.X_add_number = offset_expr.X_add_number; |
5093 | offset_expr.X_add_number = | |
5094 | ((offset_expr.X_add_number + 0x8000) & 0xffff) - 0x8000; | |
67c0d1eb | 5095 | load_got_offset (tempreg, &offset_expr); |
f6a22291 | 5096 | offset_expr.X_add_number = expr1.X_add_number; |
252b5132 RH |
5097 | /* If we are going to add in a base register, and the |
5098 | target register and the base register are the same, | |
5099 | then we are using AT as a temporary register. Since | |
5100 | we want to load the constant into AT, we add our | |
5101 | current AT (from the global offset table) and the | |
5102 | register into the register now, and pretend we were | |
5103 | not using a base register. */ | |
67c0d1eb | 5104 | if (breg == treg) |
252b5132 | 5105 | { |
269137b2 | 5106 | load_delay_nop (); |
67c0d1eb | 5107 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5108 | treg, AT, breg); |
252b5132 RH |
5109 | breg = 0; |
5110 | tempreg = treg; | |
252b5132 | 5111 | } |
f6a22291 | 5112 | add_got_offset_hilo (tempreg, &offset_expr, AT); |
252b5132 RH |
5113 | used_at = 1; |
5114 | } | |
5115 | } | |
f5040a92 AO |
5116 | else if (mips_pic == SVR4_PIC && ! mips_big_got && HAVE_NEWABI) |
5117 | { | |
67c0d1eb | 5118 | int add_breg_early = 0; |
f5040a92 AO |
5119 | |
5120 | /* If this is a reference to an external, and there is no | |
5121 | constant, or local symbol (*), with or without a | |
5122 | constant, we want | |
5123 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
1abe91b1 | 5124 | or for lca or if tempreg is PIC_CALL_REG |
f5040a92 AO |
5125 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
5126 | ||
5127 | If we have a small constant, and this is a reference to | |
5128 | an external symbol, we want | |
5129 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
5130 | addiu $tempreg,$tempreg,<constant> | |
5131 | ||
5132 | If we have a large constant, and this is a reference to | |
5133 | an external symbol, we want | |
5134 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
5135 | lui $at,<hiconstant> | |
5136 | addiu $at,$at,<loconstant> | |
5137 | addu $tempreg,$tempreg,$at | |
5138 | ||
5139 | (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for | |
5140 | local symbols, even though it introduces an additional | |
5141 | instruction. */ | |
5142 | ||
f5040a92 AO |
5143 | if (offset_expr.X_add_number) |
5144 | { | |
4d7206a2 | 5145 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
5146 | offset_expr.X_add_number = 0; |
5147 | ||
4d7206a2 | 5148 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
5149 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5150 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
5151 | |
5152 | if (expr1.X_add_number >= -0x8000 | |
5153 | && expr1.X_add_number < 0x8000) | |
5154 | { | |
67c0d1eb RS |
5155 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
5156 | tempreg, tempreg, BFD_RELOC_LO16); | |
f5040a92 | 5157 | } |
ecd13cd3 | 5158 | else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000)) |
f5040a92 AO |
5159 | { |
5160 | int dreg; | |
5161 | ||
5162 | /* If we are going to add in a base register, and the | |
5163 | target register and the base register are the same, | |
5164 | then we are using AT as a temporary register. Since | |
5165 | we want to load the constant into AT, we add our | |
5166 | current AT (from the global offset table) and the | |
5167 | register into the register now, and pretend we were | |
5168 | not using a base register. */ | |
5169 | if (breg != treg) | |
5170 | dreg = tempreg; | |
5171 | else | |
5172 | { | |
5173 | assert (tempreg == AT); | |
67c0d1eb RS |
5174 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
5175 | treg, AT, breg); | |
f5040a92 | 5176 | dreg = treg; |
67c0d1eb | 5177 | add_breg_early = 1; |
f5040a92 AO |
5178 | } |
5179 | ||
f6a22291 | 5180 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 5181 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5182 | dreg, dreg, AT); |
f5040a92 | 5183 | |
f5040a92 AO |
5184 | used_at = 1; |
5185 | } | |
5186 | else | |
5187 | as_bad (_("PIC code offset overflow (max 32 signed bits)")); | |
5188 | ||
4d7206a2 | 5189 | relax_switch (); |
f5040a92 AO |
5190 | offset_expr.X_add_number = expr1.X_add_number; |
5191 | ||
67c0d1eb RS |
5192 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5193 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
5194 | if (add_breg_early) | |
f5040a92 | 5195 | { |
67c0d1eb | 5196 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
f899b4b8 | 5197 | treg, tempreg, breg); |
f5040a92 AO |
5198 | breg = 0; |
5199 | tempreg = treg; | |
5200 | } | |
4d7206a2 | 5201 | relax_end (); |
f5040a92 | 5202 | } |
4d7206a2 | 5203 | else if (breg == 0 && (call || tempreg == PIC_CALL_REG)) |
f5040a92 | 5204 | { |
4d7206a2 | 5205 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
5206 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5207 | BFD_RELOC_MIPS_CALL16, mips_gp_register); | |
4d7206a2 | 5208 | relax_switch (); |
67c0d1eb RS |
5209 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5210 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
4d7206a2 | 5211 | relax_end (); |
f5040a92 | 5212 | } |
4d7206a2 | 5213 | else |
f5040a92 | 5214 | { |
67c0d1eb RS |
5215 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5216 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
5217 | } |
5218 | } | |
5219 | else if (mips_pic == SVR4_PIC && ! HAVE_NEWABI) | |
252b5132 | 5220 | { |
67c0d1eb | 5221 | int gpdelay; |
9117d219 NC |
5222 | int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; |
5223 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; | |
ed6fb7bd | 5224 | int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
252b5132 RH |
5225 | |
5226 | /* This is the large GOT case. If this is a reference to an | |
5227 | external symbol, and there is no constant, we want | |
5228 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5229 | addu $tempreg,$tempreg,$gp | |
5230 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
1abe91b1 | 5231 | or for lca or if tempreg is PIC_CALL_REG |
9117d219 NC |
5232 | lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) |
5233 | addu $tempreg,$tempreg,$gp | |
5234 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) | |
252b5132 RH |
5235 | For a local symbol, we want |
5236 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5237 | nop | |
5238 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
5239 | ||
5240 | If we have a small constant, and this is a reference to | |
5241 | an external symbol, we want | |
5242 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5243 | addu $tempreg,$tempreg,$gp | |
5244 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5245 | nop | |
5246 | addiu $tempreg,$tempreg,<constant> | |
5247 | For a local symbol, we want | |
5248 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5249 | nop | |
5250 | addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16) | |
5251 | ||
5252 | If we have a large constant, and this is a reference to | |
5253 | an external symbol, we want | |
5254 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5255 | addu $tempreg,$tempreg,$gp | |
5256 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5257 | lui $at,<hiconstant> | |
5258 | addiu $at,$at,<loconstant> | |
5259 | addu $tempreg,$tempreg,$at | |
5260 | For a local symbol, we want | |
5261 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5262 | lui $at,<hiconstant> | |
5263 | addiu $at,$at,<loconstant> (BFD_RELOC_LO16) | |
5264 | addu $tempreg,$tempreg,$at | |
f5040a92 | 5265 | */ |
438c16b8 | 5266 | |
252b5132 RH |
5267 | expr1.X_add_number = offset_expr.X_add_number; |
5268 | offset_expr.X_add_number = 0; | |
4d7206a2 | 5269 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 5270 | gpdelay = reg_needs_delay (mips_gp_register); |
1abe91b1 MR |
5271 | if (expr1.X_add_number == 0 && breg == 0 |
5272 | && (call || tempreg == PIC_CALL_REG)) | |
9117d219 NC |
5273 | { |
5274 | lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; | |
5275 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; | |
5276 | } | |
67c0d1eb RS |
5277 | macro_build (&offset_expr, "lui", "t,u", tempreg, lui_reloc_type); |
5278 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 5279 | tempreg, tempreg, mips_gp_register); |
67c0d1eb | 5280 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
17a2f251 | 5281 | tempreg, lw_reloc_type, tempreg); |
252b5132 RH |
5282 | if (expr1.X_add_number == 0) |
5283 | { | |
67c0d1eb | 5284 | if (breg != 0) |
252b5132 RH |
5285 | { |
5286 | /* We're going to put in an addu instruction using | |
5287 | tempreg, so we may as well insert the nop right | |
5288 | now. */ | |
269137b2 | 5289 | load_delay_nop (); |
252b5132 | 5290 | } |
252b5132 RH |
5291 | } |
5292 | else if (expr1.X_add_number >= -0x8000 | |
5293 | && expr1.X_add_number < 0x8000) | |
5294 | { | |
269137b2 | 5295 | load_delay_nop (); |
67c0d1eb | 5296 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 5297 | tempreg, tempreg, BFD_RELOC_LO16); |
252b5132 RH |
5298 | } |
5299 | else | |
5300 | { | |
67c0d1eb | 5301 | int dreg; |
252b5132 RH |
5302 | |
5303 | /* If we are going to add in a base register, and the | |
5304 | target register and the base register are the same, | |
5305 | then we are using AT as a temporary register. Since | |
5306 | we want to load the constant into AT, we add our | |
5307 | current AT (from the global offset table) and the | |
5308 | register into the register now, and pretend we were | |
5309 | not using a base register. */ | |
5310 | if (breg != treg) | |
67c0d1eb | 5311 | dreg = tempreg; |
252b5132 RH |
5312 | else |
5313 | { | |
5314 | assert (tempreg == AT); | |
269137b2 | 5315 | load_delay_nop (); |
67c0d1eb | 5316 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5317 | treg, AT, breg); |
252b5132 | 5318 | dreg = treg; |
252b5132 RH |
5319 | } |
5320 | ||
f6a22291 | 5321 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 5322 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT); |
252b5132 | 5323 | |
252b5132 RH |
5324 | used_at = 1; |
5325 | } | |
4d7206a2 RS |
5326 | offset_expr.X_add_number = |
5327 | ((expr1.X_add_number + 0x8000) & 0xffff) - 0x8000; | |
5328 | relax_switch (); | |
252b5132 | 5329 | |
67c0d1eb | 5330 | if (gpdelay) |
252b5132 RH |
5331 | { |
5332 | /* This is needed because this instruction uses $gp, but | |
f5040a92 | 5333 | the first instruction on the main stream does not. */ |
67c0d1eb | 5334 | macro_build (NULL, "nop", ""); |
252b5132 | 5335 | } |
ed6fb7bd | 5336 | |
67c0d1eb RS |
5337 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5338 | local_reloc_type, mips_gp_register); | |
f5040a92 | 5339 | if (expr1.X_add_number >= -0x8000 |
252b5132 RH |
5340 | && expr1.X_add_number < 0x8000) |
5341 | { | |
269137b2 | 5342 | load_delay_nop (); |
67c0d1eb RS |
5343 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
5344 | tempreg, tempreg, BFD_RELOC_LO16); | |
252b5132 | 5345 | /* FIXME: If add_number is 0, and there was no base |
f5040a92 AO |
5346 | register, the external symbol case ended with a load, |
5347 | so if the symbol turns out to not be external, and | |
5348 | the next instruction uses tempreg, an unnecessary nop | |
5349 | will be inserted. */ | |
252b5132 RH |
5350 | } |
5351 | else | |
5352 | { | |
5353 | if (breg == treg) | |
5354 | { | |
5355 | /* We must add in the base register now, as in the | |
f5040a92 | 5356 | external symbol case. */ |
252b5132 | 5357 | assert (tempreg == AT); |
269137b2 | 5358 | load_delay_nop (); |
67c0d1eb | 5359 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5360 | treg, AT, breg); |
252b5132 RH |
5361 | tempreg = treg; |
5362 | /* We set breg to 0 because we have arranged to add | |
f5040a92 | 5363 | it in in both cases. */ |
252b5132 RH |
5364 | breg = 0; |
5365 | } | |
5366 | ||
67c0d1eb RS |
5367 | macro_build_lui (&expr1, AT); |
5368 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
17a2f251 | 5369 | AT, AT, BFD_RELOC_LO16); |
67c0d1eb | 5370 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5371 | tempreg, tempreg, AT); |
8fc2e39e | 5372 | used_at = 1; |
252b5132 | 5373 | } |
4d7206a2 | 5374 | relax_end (); |
252b5132 | 5375 | } |
f5040a92 AO |
5376 | else if (mips_pic == SVR4_PIC && HAVE_NEWABI) |
5377 | { | |
f5040a92 AO |
5378 | int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; |
5379 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; | |
67c0d1eb | 5380 | int add_breg_early = 0; |
f5040a92 AO |
5381 | |
5382 | /* This is the large GOT case. If this is a reference to an | |
5383 | external symbol, and there is no constant, we want | |
5384 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5385 | add $tempreg,$tempreg,$gp | |
5386 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
1abe91b1 | 5387 | or for lca or if tempreg is PIC_CALL_REG |
f5040a92 AO |
5388 | lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) |
5389 | add $tempreg,$tempreg,$gp | |
5390 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) | |
5391 | ||
5392 | If we have a small constant, and this is a reference to | |
5393 | an external symbol, we want | |
5394 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5395 | add $tempreg,$tempreg,$gp | |
5396 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5397 | addi $tempreg,$tempreg,<constant> | |
5398 | ||
5399 | If we have a large constant, and this is a reference to | |
5400 | an external symbol, we want | |
5401 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5402 | addu $tempreg,$tempreg,$gp | |
5403 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5404 | lui $at,<hiconstant> | |
5405 | addi $at,$at,<loconstant> | |
5406 | add $tempreg,$tempreg,$at | |
5407 | ||
5408 | If we have NewABI, and we know it's a local symbol, we want | |
5409 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
5410 | addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) | |
5411 | otherwise we have to resort to GOT_HI16/GOT_LO16. */ | |
5412 | ||
4d7206a2 | 5413 | relax_start (offset_expr.X_add_symbol); |
f5040a92 | 5414 | |
4d7206a2 | 5415 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
5416 | offset_expr.X_add_number = 0; |
5417 | ||
1abe91b1 MR |
5418 | if (expr1.X_add_number == 0 && breg == 0 |
5419 | && (call || tempreg == PIC_CALL_REG)) | |
f5040a92 AO |
5420 | { |
5421 | lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; | |
5422 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; | |
5423 | } | |
67c0d1eb RS |
5424 | macro_build (&offset_expr, "lui", "t,u", tempreg, lui_reloc_type); |
5425 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 5426 | tempreg, tempreg, mips_gp_register); |
67c0d1eb RS |
5427 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5428 | tempreg, lw_reloc_type, tempreg); | |
f5040a92 AO |
5429 | |
5430 | if (expr1.X_add_number == 0) | |
4d7206a2 | 5431 | ; |
f5040a92 AO |
5432 | else if (expr1.X_add_number >= -0x8000 |
5433 | && expr1.X_add_number < 0x8000) | |
5434 | { | |
67c0d1eb | 5435 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 5436 | tempreg, tempreg, BFD_RELOC_LO16); |
f5040a92 | 5437 | } |
ecd13cd3 | 5438 | else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000)) |
f5040a92 AO |
5439 | { |
5440 | int dreg; | |
5441 | ||
5442 | /* If we are going to add in a base register, and the | |
5443 | target register and the base register are the same, | |
5444 | then we are using AT as a temporary register. Since | |
5445 | we want to load the constant into AT, we add our | |
5446 | current AT (from the global offset table) and the | |
5447 | register into the register now, and pretend we were | |
5448 | not using a base register. */ | |
5449 | if (breg != treg) | |
5450 | dreg = tempreg; | |
5451 | else | |
5452 | { | |
5453 | assert (tempreg == AT); | |
67c0d1eb | 5454 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5455 | treg, AT, breg); |
f5040a92 | 5456 | dreg = treg; |
67c0d1eb | 5457 | add_breg_early = 1; |
f5040a92 AO |
5458 | } |
5459 | ||
f6a22291 | 5460 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 5461 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT); |
f5040a92 | 5462 | |
f5040a92 AO |
5463 | used_at = 1; |
5464 | } | |
5465 | else | |
5466 | as_bad (_("PIC code offset overflow (max 32 signed bits)")); | |
5467 | ||
4d7206a2 | 5468 | relax_switch (); |
f5040a92 | 5469 | offset_expr.X_add_number = expr1.X_add_number; |
67c0d1eb RS |
5470 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5471 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
5472 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, | |
5473 | tempreg, BFD_RELOC_MIPS_GOT_OFST); | |
5474 | if (add_breg_early) | |
f5040a92 | 5475 | { |
67c0d1eb | 5476 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5477 | treg, tempreg, breg); |
f5040a92 AO |
5478 | breg = 0; |
5479 | tempreg = treg; | |
5480 | } | |
4d7206a2 | 5481 | relax_end (); |
f5040a92 | 5482 | } |
252b5132 RH |
5483 | else |
5484 | abort (); | |
5485 | ||
5486 | if (breg != 0) | |
4d34fb5f TS |
5487 | { |
5488 | char *s; | |
5489 | ||
3e722fb5 | 5490 | if (mips_pic == NO_PIC) |
b7c7d6c1 | 5491 | s = (dbl || HAVE_64BIT_ADDRESSES) ? "daddu" : "addu"; |
4d34fb5f | 5492 | else |
f899b4b8 | 5493 | s = ADDRESS_ADD_INSN; |
4d34fb5f | 5494 | |
67c0d1eb | 5495 | macro_build (NULL, s, "d,v,t", treg, tempreg, breg); |
4d34fb5f | 5496 | } |
252b5132 RH |
5497 | break; |
5498 | ||
5499 | case M_J_A: | |
5500 | /* The j instruction may not be used in PIC code, since it | |
5501 | requires an absolute address. We convert it to a b | |
5502 | instruction. */ | |
5503 | if (mips_pic == NO_PIC) | |
67c0d1eb | 5504 | macro_build (&offset_expr, "j", "a"); |
252b5132 | 5505 | else |
67c0d1eb | 5506 | macro_build (&offset_expr, "b", "p"); |
8fc2e39e | 5507 | break; |
252b5132 RH |
5508 | |
5509 | /* The jal instructions must be handled as macros because when | |
5510 | generating PIC code they expand to multi-instruction | |
5511 | sequences. Normally they are simple instructions. */ | |
5512 | case M_JAL_1: | |
5513 | dreg = RA; | |
5514 | /* Fall through. */ | |
5515 | case M_JAL_2: | |
3e722fb5 | 5516 | if (mips_pic == NO_PIC) |
67c0d1eb | 5517 | macro_build (NULL, "jalr", "d,s", dreg, sreg); |
252b5132 RH |
5518 | else if (mips_pic == SVR4_PIC) |
5519 | { | |
5520 | if (sreg != PIC_CALL_REG) | |
5521 | as_warn (_("MIPS PIC call to register other than $25")); | |
bdaaa2e1 | 5522 | |
67c0d1eb | 5523 | macro_build (NULL, "jalr", "d,s", dreg, sreg); |
6478892d | 5524 | if (! HAVE_NEWABI) |
252b5132 | 5525 | { |
6478892d TS |
5526 | if (mips_cprestore_offset < 0) |
5527 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
5528 | else | |
5529 | { | |
7a621144 DJ |
5530 | if (! mips_frame_reg_valid) |
5531 | { | |
5532 | as_warn (_("No .frame pseudo-op used in PIC code")); | |
5533 | /* Quiet this warning. */ | |
5534 | mips_frame_reg_valid = 1; | |
5535 | } | |
5536 | if (! mips_cprestore_valid) | |
5537 | { | |
5538 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
5539 | /* Quiet this warning. */ | |
5540 | mips_cprestore_valid = 1; | |
5541 | } | |
6478892d | 5542 | expr1.X_add_number = mips_cprestore_offset; |
67c0d1eb | 5543 | macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN, |
f899b4b8 | 5544 | mips_gp_register, |
256ab948 TS |
5545 | mips_frame_reg, |
5546 | HAVE_64BIT_ADDRESSES); | |
6478892d | 5547 | } |
252b5132 RH |
5548 | } |
5549 | } | |
5550 | else | |
5551 | abort (); | |
5552 | ||
8fc2e39e | 5553 | break; |
252b5132 RH |
5554 | |
5555 | case M_JAL_A: | |
5556 | if (mips_pic == NO_PIC) | |
67c0d1eb | 5557 | macro_build (&offset_expr, "jal", "a"); |
252b5132 RH |
5558 | else if (mips_pic == SVR4_PIC) |
5559 | { | |
5560 | /* If this is a reference to an external symbol, and we are | |
5561 | using a small GOT, we want | |
5562 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16) | |
5563 | nop | |
f9419b05 | 5564 | jalr $ra,$25 |
252b5132 RH |
5565 | nop |
5566 | lw $gp,cprestore($sp) | |
5567 | The cprestore value is set using the .cprestore | |
5568 | pseudo-op. If we are using a big GOT, we want | |
5569 | lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16) | |
5570 | addu $25,$25,$gp | |
5571 | lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16) | |
5572 | nop | |
f9419b05 | 5573 | jalr $ra,$25 |
252b5132 RH |
5574 | nop |
5575 | lw $gp,cprestore($sp) | |
5576 | If the symbol is not external, we want | |
5577 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5578 | nop | |
5579 | addiu $25,$25,<sym> (BFD_RELOC_LO16) | |
f9419b05 | 5580 | jalr $ra,$25 |
252b5132 | 5581 | nop |
438c16b8 | 5582 | lw $gp,cprestore($sp) |
f5040a92 AO |
5583 | |
5584 | For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16 | |
5585 | sequences above, minus nops, unless the symbol is local, | |
5586 | which enables us to use GOT_PAGE/GOT_OFST (big got) or | |
5587 | GOT_DISP. */ | |
438c16b8 | 5588 | if (HAVE_NEWABI) |
252b5132 | 5589 | { |
f5040a92 AO |
5590 | if (! mips_big_got) |
5591 | { | |
4d7206a2 | 5592 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
5593 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5594 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL16, | |
f5040a92 | 5595 | mips_gp_register); |
4d7206a2 | 5596 | relax_switch (); |
67c0d1eb RS |
5597 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5598 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT_DISP, | |
4d7206a2 RS |
5599 | mips_gp_register); |
5600 | relax_end (); | |
f5040a92 AO |
5601 | } |
5602 | else | |
5603 | { | |
4d7206a2 | 5604 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
5605 | macro_build (&offset_expr, "lui", "t,u", PIC_CALL_REG, |
5606 | BFD_RELOC_MIPS_CALL_HI16); | |
5607 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG, | |
5608 | PIC_CALL_REG, mips_gp_register); | |
5609 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", | |
5610 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16, | |
5611 | PIC_CALL_REG); | |
4d7206a2 | 5612 | relax_switch (); |
67c0d1eb RS |
5613 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5614 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT_PAGE, | |
5615 | mips_gp_register); | |
5616 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
5617 | PIC_CALL_REG, PIC_CALL_REG, | |
17a2f251 | 5618 | BFD_RELOC_MIPS_GOT_OFST); |
4d7206a2 | 5619 | relax_end (); |
f5040a92 | 5620 | } |
684022ea | 5621 | |
67c0d1eb | 5622 | macro_build_jalr (&offset_expr); |
252b5132 RH |
5623 | } |
5624 | else | |
5625 | { | |
4d7206a2 | 5626 | relax_start (offset_expr.X_add_symbol); |
438c16b8 TS |
5627 | if (! mips_big_got) |
5628 | { | |
67c0d1eb RS |
5629 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5630 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL16, | |
17a2f251 | 5631 | mips_gp_register); |
269137b2 | 5632 | load_delay_nop (); |
4d7206a2 | 5633 | relax_switch (); |
438c16b8 | 5634 | } |
252b5132 | 5635 | else |
252b5132 | 5636 | { |
67c0d1eb RS |
5637 | int gpdelay; |
5638 | ||
5639 | gpdelay = reg_needs_delay (mips_gp_register); | |
5640 | macro_build (&offset_expr, "lui", "t,u", PIC_CALL_REG, | |
5641 | BFD_RELOC_MIPS_CALL_HI16); | |
5642 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG, | |
5643 | PIC_CALL_REG, mips_gp_register); | |
5644 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", | |
5645 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16, | |
5646 | PIC_CALL_REG); | |
269137b2 | 5647 | load_delay_nop (); |
4d7206a2 | 5648 | relax_switch (); |
67c0d1eb RS |
5649 | if (gpdelay) |
5650 | macro_build (NULL, "nop", ""); | |
252b5132 | 5651 | } |
67c0d1eb RS |
5652 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5653 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT16, | |
4d7206a2 | 5654 | mips_gp_register); |
269137b2 | 5655 | load_delay_nop (); |
67c0d1eb RS |
5656 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
5657 | PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16); | |
4d7206a2 | 5658 | relax_end (); |
67c0d1eb | 5659 | macro_build_jalr (&offset_expr); |
438c16b8 | 5660 | |
6478892d TS |
5661 | if (mips_cprestore_offset < 0) |
5662 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
5663 | else | |
5664 | { | |
7a621144 DJ |
5665 | if (! mips_frame_reg_valid) |
5666 | { | |
5667 | as_warn (_("No .frame pseudo-op used in PIC code")); | |
5668 | /* Quiet this warning. */ | |
5669 | mips_frame_reg_valid = 1; | |
5670 | } | |
5671 | if (! mips_cprestore_valid) | |
5672 | { | |
5673 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
5674 | /* Quiet this warning. */ | |
5675 | mips_cprestore_valid = 1; | |
5676 | } | |
6478892d | 5677 | if (mips_opts.noreorder) |
67c0d1eb | 5678 | macro_build (NULL, "nop", ""); |
6478892d | 5679 | expr1.X_add_number = mips_cprestore_offset; |
67c0d1eb | 5680 | macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN, |
f899b4b8 | 5681 | mips_gp_register, |
256ab948 TS |
5682 | mips_frame_reg, |
5683 | HAVE_64BIT_ADDRESSES); | |
6478892d | 5684 | } |
252b5132 RH |
5685 | } |
5686 | } | |
252b5132 RH |
5687 | else |
5688 | abort (); | |
5689 | ||
8fc2e39e | 5690 | break; |
252b5132 RH |
5691 | |
5692 | case M_LB_AB: | |
5693 | s = "lb"; | |
5694 | goto ld; | |
5695 | case M_LBU_AB: | |
5696 | s = "lbu"; | |
5697 | goto ld; | |
5698 | case M_LH_AB: | |
5699 | s = "lh"; | |
5700 | goto ld; | |
5701 | case M_LHU_AB: | |
5702 | s = "lhu"; | |
5703 | goto ld; | |
5704 | case M_LW_AB: | |
5705 | s = "lw"; | |
5706 | goto ld; | |
5707 | case M_LWC0_AB: | |
5708 | s = "lwc0"; | |
bdaaa2e1 | 5709 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5710 | coproc = 1; |
5711 | goto ld; | |
5712 | case M_LWC1_AB: | |
5713 | s = "lwc1"; | |
bdaaa2e1 | 5714 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5715 | coproc = 1; |
5716 | goto ld; | |
5717 | case M_LWC2_AB: | |
5718 | s = "lwc2"; | |
bdaaa2e1 | 5719 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5720 | coproc = 1; |
5721 | goto ld; | |
5722 | case M_LWC3_AB: | |
5723 | s = "lwc3"; | |
bdaaa2e1 | 5724 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5725 | coproc = 1; |
5726 | goto ld; | |
5727 | case M_LWL_AB: | |
5728 | s = "lwl"; | |
5729 | lr = 1; | |
5730 | goto ld; | |
5731 | case M_LWR_AB: | |
5732 | s = "lwr"; | |
5733 | lr = 1; | |
5734 | goto ld; | |
5735 | case M_LDC1_AB: | |
fef14a42 | 5736 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
5737 | { |
5738 | as_bad (_("opcode not supported on this processor")); | |
8fc2e39e | 5739 | break; |
252b5132 RH |
5740 | } |
5741 | s = "ldc1"; | |
bdaaa2e1 | 5742 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5743 | coproc = 1; |
5744 | goto ld; | |
5745 | case M_LDC2_AB: | |
5746 | s = "ldc2"; | |
bdaaa2e1 | 5747 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5748 | coproc = 1; |
5749 | goto ld; | |
5750 | case M_LDC3_AB: | |
5751 | s = "ldc3"; | |
bdaaa2e1 | 5752 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5753 | coproc = 1; |
5754 | goto ld; | |
5755 | case M_LDL_AB: | |
5756 | s = "ldl"; | |
5757 | lr = 1; | |
5758 | goto ld; | |
5759 | case M_LDR_AB: | |
5760 | s = "ldr"; | |
5761 | lr = 1; | |
5762 | goto ld; | |
5763 | case M_LL_AB: | |
5764 | s = "ll"; | |
5765 | goto ld; | |
5766 | case M_LLD_AB: | |
5767 | s = "lld"; | |
5768 | goto ld; | |
5769 | case M_LWU_AB: | |
5770 | s = "lwu"; | |
5771 | ld: | |
8fc2e39e | 5772 | if (breg == treg || coproc || lr) |
252b5132 RH |
5773 | { |
5774 | tempreg = AT; | |
5775 | used_at = 1; | |
5776 | } | |
5777 | else | |
5778 | { | |
5779 | tempreg = treg; | |
252b5132 RH |
5780 | } |
5781 | goto ld_st; | |
5782 | case M_SB_AB: | |
5783 | s = "sb"; | |
5784 | goto st; | |
5785 | case M_SH_AB: | |
5786 | s = "sh"; | |
5787 | goto st; | |
5788 | case M_SW_AB: | |
5789 | s = "sw"; | |
5790 | goto st; | |
5791 | case M_SWC0_AB: | |
5792 | s = "swc0"; | |
bdaaa2e1 | 5793 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5794 | coproc = 1; |
5795 | goto st; | |
5796 | case M_SWC1_AB: | |
5797 | s = "swc1"; | |
bdaaa2e1 | 5798 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5799 | coproc = 1; |
5800 | goto st; | |
5801 | case M_SWC2_AB: | |
5802 | s = "swc2"; | |
bdaaa2e1 | 5803 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5804 | coproc = 1; |
5805 | goto st; | |
5806 | case M_SWC3_AB: | |
5807 | s = "swc3"; | |
bdaaa2e1 | 5808 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5809 | coproc = 1; |
5810 | goto st; | |
5811 | case M_SWL_AB: | |
5812 | s = "swl"; | |
5813 | goto st; | |
5814 | case M_SWR_AB: | |
5815 | s = "swr"; | |
5816 | goto st; | |
5817 | case M_SC_AB: | |
5818 | s = "sc"; | |
5819 | goto st; | |
5820 | case M_SCD_AB: | |
5821 | s = "scd"; | |
5822 | goto st; | |
5823 | case M_SDC1_AB: | |
fef14a42 | 5824 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
5825 | { |
5826 | as_bad (_("opcode not supported on this processor")); | |
8fc2e39e | 5827 | break; |
252b5132 RH |
5828 | } |
5829 | s = "sdc1"; | |
5830 | coproc = 1; | |
bdaaa2e1 | 5831 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5832 | goto st; |
5833 | case M_SDC2_AB: | |
5834 | s = "sdc2"; | |
bdaaa2e1 | 5835 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5836 | coproc = 1; |
5837 | goto st; | |
5838 | case M_SDC3_AB: | |
5839 | s = "sdc3"; | |
bdaaa2e1 | 5840 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5841 | coproc = 1; |
5842 | goto st; | |
5843 | case M_SDL_AB: | |
5844 | s = "sdl"; | |
5845 | goto st; | |
5846 | case M_SDR_AB: | |
5847 | s = "sdr"; | |
5848 | st: | |
8fc2e39e TS |
5849 | tempreg = AT; |
5850 | used_at = 1; | |
252b5132 | 5851 | ld_st: |
bdaaa2e1 | 5852 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5853 | if (mask == M_LWC1_AB |
5854 | || mask == M_SWC1_AB | |
5855 | || mask == M_LDC1_AB | |
5856 | || mask == M_SDC1_AB | |
5857 | || mask == M_L_DAB | |
5858 | || mask == M_S_DAB) | |
5859 | fmt = "T,o(b)"; | |
5860 | else if (coproc) | |
5861 | fmt = "E,o(b)"; | |
5862 | else | |
5863 | fmt = "t,o(b)"; | |
5864 | ||
256ab948 TS |
5865 | /* Sign-extending 32-bit constants makes their handling easier. |
5866 | The HAVE_64BIT_GPRS... part is due to the linux kernel hack | |
5867 | described below. */ | |
5868 | if ((! HAVE_64BIT_ADDRESSES | |
5869 | && (! HAVE_64BIT_GPRS && offset_expr.X_op == O_constant)) | |
d17e7bce TS |
5870 | && (offset_expr.X_op == O_constant) |
5871 | && ! ((offset_expr.X_add_number & ~((bfd_vma) 0x7fffffff)) | |
5872 | == ~((bfd_vma) 0x7fffffff))) | |
ae826530 | 5873 | { |
d17e7bce | 5874 | if (offset_expr.X_add_number & ~((bfd_vma) 0xffffffff)) |
1b8e29e5 | 5875 | as_bad (_("constant too large")); |
ae826530 | 5876 | |
1b8e29e5 TS |
5877 | offset_expr.X_add_number = (((offset_expr.X_add_number & 0xffffffff) |
5878 | ^ 0x80000000) - 0x80000000); | |
ae826530 | 5879 | } |
256ab948 | 5880 | |
252b5132 RH |
5881 | if (offset_expr.X_op != O_constant |
5882 | && offset_expr.X_op != O_symbol) | |
5883 | { | |
5884 | as_bad (_("expression too complex")); | |
5885 | offset_expr.X_op = O_constant; | |
5886 | } | |
5887 | ||
5888 | /* A constant expression in PIC code can be handled just as it | |
5889 | is in non PIC code. */ | |
5890 | if (mips_pic == NO_PIC | |
5891 | || offset_expr.X_op == O_constant) | |
5892 | { | |
5893 | /* If this is a reference to a GP relative symbol, and there | |
5894 | is no base register, we want | |
cdf6fd85 | 5895 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
252b5132 RH |
5896 | Otherwise, if there is no base register, we want |
5897 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
5898 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
5899 | If we have a constant, we need two instructions anyhow, | |
5900 | so we always use the latter form. | |
5901 | ||
5902 | If we have a base register, and this is a reference to a | |
5903 | GP relative symbol, we want | |
5904 | addu $tempreg,$breg,$gp | |
cdf6fd85 | 5905 | <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16) |
252b5132 RH |
5906 | Otherwise we want |
5907 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
5908 | addu $tempreg,$tempreg,$breg | |
5909 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
d6bc6245 | 5910 | With a constant we always use the latter case. |
76b3015f | 5911 | |
d6bc6245 TS |
5912 | With 64bit address space and no base register and $at usable, |
5913 | we want | |
5914 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5915 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
5916 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5917 | dsll32 $tempreg,0 | |
5918 | daddu $tempreg,$at | |
5919 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
5920 | If we have a base register, we want | |
5921 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5922 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
5923 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5924 | daddu $at,$breg | |
5925 | dsll32 $tempreg,0 | |
5926 | daddu $tempreg,$at | |
5927 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
5928 | ||
5929 | Without $at we can't generate the optimal path for superscalar | |
5930 | processors here since this would require two temporary registers. | |
5931 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5932 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5933 | dsll $tempreg,16 | |
5934 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
5935 | dsll $tempreg,16 | |
5936 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
5937 | If we have a base register, we want | |
5938 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5939 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5940 | dsll $tempreg,16 | |
5941 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
5942 | dsll $tempreg,16 | |
5943 | daddu $tempreg,$tempreg,$breg | |
5944 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
6373ee54 CD |
5945 | |
5946 | If we have 64-bit addresses, as an optimization, for | |
5947 | addresses which are 32-bit constants (e.g. kseg0/kseg1 | |
5948 | addresses) we fall back to the 32-bit address generation | |
78d32a17 MR |
5949 | mechanism since it is more efficient. Note that due to |
5950 | the signed offset used by memory operations, the 32-bit | |
5951 | range is shifted down by 32768 here. This code should | |
6373ee54 CD |
5952 | probably attempt to generate 64-bit constants more |
5953 | efficiently in general. | |
9214dd3b AO |
5954 | |
5955 | As an extension for architectures with 64-bit registers, | |
5956 | we don't truncate 64-bit addresses given as literal | |
5957 | constants down to 32 bits, to support existing practice | |
5958 | in the mips64 Linux (the kernel), that compiles source | |
5959 | files with -mabi=64, assembling them as o32 or n32 (with | |
5960 | -Wa,-32 or -Wa,-n32). This is not beautiful, but since | |
5961 | the whole kernel is loaded into a memory region that is | |
67c1ffbe | 5962 | addressable with sign-extended 32-bit addresses, it is |
9214dd3b AO |
5963 | wasteful to compute the upper 32 bits of every |
5964 | non-literal address, that takes more space and time. | |
5965 | Some day this should probably be implemented as an | |
5966 | assembler option, such that the kernel doesn't have to | |
5967 | use such ugly hacks, even though it will still have to | |
5968 | end up converting the binary to ELF32 for a number of | |
5969 | platforms whose boot loaders don't support ELF64 | |
5970 | binaries. */ | |
256ab948 TS |
5971 | if ((HAVE_64BIT_ADDRESSES |
5972 | && ! (offset_expr.X_op == O_constant | |
5973 | && IS_SEXT_32BIT_NUM (offset_expr.X_add_number + 0x8000))) | |
5974 | || (HAVE_64BIT_GPRS | |
5975 | && offset_expr.X_op == O_constant | |
5976 | && ! IS_SEXT_32BIT_NUM (offset_expr.X_add_number + 0x8000))) | |
d6bc6245 | 5977 | { |
e864ceca RS |
5978 | /* ??? We don't provide a GP-relative alternative for |
5979 | these macros. It used not to be possible with the | |
5980 | original relaxation code, but it could be done now. */ | |
d6bc6245 | 5981 | |
b8285c27 | 5982 | if (used_at == 0 && !mips_opts.noat) |
d6bc6245 | 5983 | { |
67c0d1eb RS |
5984 | macro_build (&offset_expr, "lui", "t,u", tempreg, |
5985 | BFD_RELOC_MIPS_HIGHEST); | |
5986 | macro_build (&offset_expr, "lui", "t,u", AT, | |
5987 | BFD_RELOC_HI16_S); | |
5988 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
5989 | tempreg, BFD_RELOC_MIPS_HIGHER); | |
d6bc6245 | 5990 | if (breg != 0) |
67c0d1eb RS |
5991 | macro_build (NULL, "daddu", "d,v,t", AT, AT, breg); |
5992 | macro_build (NULL, "dsll32", "d,w,<", tempreg, tempreg, 0); | |
5993 | macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT); | |
5994 | macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, | |
5995 | tempreg); | |
d6bc6245 TS |
5996 | used_at = 1; |
5997 | } | |
5998 | else | |
5999 | { | |
67c0d1eb RS |
6000 | macro_build (&offset_expr, "lui", "t,u", tempreg, |
6001 | BFD_RELOC_MIPS_HIGHEST); | |
6002 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
6003 | tempreg, BFD_RELOC_MIPS_HIGHER); | |
6004 | macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16); | |
6005 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
6006 | tempreg, BFD_RELOC_HI16_S); | |
6007 | macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16); | |
d6bc6245 | 6008 | if (breg != 0) |
67c0d1eb | 6009 | macro_build (NULL, "daddu", "d,v,t", |
17a2f251 | 6010 | tempreg, tempreg, breg); |
67c0d1eb | 6011 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 6012 | BFD_RELOC_LO16, tempreg); |
d6bc6245 | 6013 | } |
8fc2e39e | 6014 | break; |
d6bc6245 | 6015 | } |
256ab948 TS |
6016 | |
6017 | if (offset_expr.X_op == O_constant | |
ecd13cd3 | 6018 | && ! IS_SEXT_32BIT_NUM (offset_expr.X_add_number + 0x8000)) |
5a7a0b7b | 6019 | as_bad (_("load/store address overflow (max 32 bits)")); |
76b3015f | 6020 | |
252b5132 RH |
6021 | if (breg == 0) |
6022 | { | |
67c0d1eb RS |
6023 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6024 | && ! nopic_need_relax (offset_expr.X_add_symbol, 1)) | |
252b5132 | 6025 | { |
4d7206a2 | 6026 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
6027 | macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_GPREL16, |
6028 | mips_gp_register); | |
4d7206a2 | 6029 | relax_switch (); |
252b5132 | 6030 | } |
67c0d1eb RS |
6031 | macro_build_lui (&offset_expr, tempreg); |
6032 | macro_build (&offset_expr, s, fmt, treg, | |
17a2f251 | 6033 | BFD_RELOC_LO16, tempreg); |
4d7206a2 RS |
6034 | if (mips_relax.sequence) |
6035 | relax_end (); | |
252b5132 RH |
6036 | } |
6037 | else | |
6038 | { | |
67c0d1eb RS |
6039 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6040 | && ! nopic_need_relax (offset_expr.X_add_symbol, 1)) | |
252b5132 | 6041 | { |
4d7206a2 | 6042 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 6043 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6044 | tempreg, breg, mips_gp_register); |
67c0d1eb | 6045 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 6046 | BFD_RELOC_GPREL16, tempreg); |
4d7206a2 | 6047 | relax_switch (); |
252b5132 | 6048 | } |
67c0d1eb RS |
6049 | macro_build_lui (&offset_expr, tempreg); |
6050 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 6051 | tempreg, tempreg, breg); |
67c0d1eb | 6052 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 6053 | BFD_RELOC_LO16, tempreg); |
4d7206a2 RS |
6054 | if (mips_relax.sequence) |
6055 | relax_end (); | |
252b5132 RH |
6056 | } |
6057 | } | |
6058 | else if (mips_pic == SVR4_PIC && ! mips_big_got) | |
6059 | { | |
ed6fb7bd | 6060 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
f9419b05 | 6061 | |
252b5132 RH |
6062 | /* If this is a reference to an external symbol, we want |
6063 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6064 | nop | |
6065 | <op> $treg,0($tempreg) | |
6066 | Otherwise we want | |
6067 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6068 | nop | |
6069 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
6070 | <op> $treg,0($tempreg) | |
f5040a92 AO |
6071 | |
6072 | For NewABI, we want | |
6073 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
6074 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) | |
6075 | ||
252b5132 RH |
6076 | If there is a base register, we add it to $tempreg before |
6077 | the <op>. If there is a constant, we stick it in the | |
6078 | <op> instruction. We don't handle constants larger than | |
6079 | 16 bits, because we have no way to load the upper 16 bits | |
6080 | (actually, we could handle them for the subset of cases | |
6081 | in which we are not using $at). */ | |
6082 | assert (offset_expr.X_op == O_symbol); | |
f5040a92 AO |
6083 | if (HAVE_NEWABI) |
6084 | { | |
67c0d1eb RS |
6085 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
6086 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
f5040a92 | 6087 | if (breg != 0) |
67c0d1eb | 6088 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6089 | tempreg, tempreg, breg); |
67c0d1eb | 6090 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 6091 | BFD_RELOC_MIPS_GOT_OFST, tempreg); |
f5040a92 AO |
6092 | break; |
6093 | } | |
252b5132 RH |
6094 | expr1.X_add_number = offset_expr.X_add_number; |
6095 | offset_expr.X_add_number = 0; | |
6096 | if (expr1.X_add_number < -0x8000 | |
6097 | || expr1.X_add_number >= 0x8000) | |
6098 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb RS |
6099 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
6100 | lw_reloc_type, mips_gp_register); | |
269137b2 | 6101 | load_delay_nop (); |
4d7206a2 RS |
6102 | relax_start (offset_expr.X_add_symbol); |
6103 | relax_switch (); | |
67c0d1eb RS |
6104 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, |
6105 | tempreg, BFD_RELOC_LO16); | |
4d7206a2 | 6106 | relax_end (); |
252b5132 | 6107 | if (breg != 0) |
67c0d1eb | 6108 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6109 | tempreg, tempreg, breg); |
67c0d1eb | 6110 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
252b5132 | 6111 | } |
f5040a92 | 6112 | else if (mips_pic == SVR4_PIC && ! HAVE_NEWABI) |
252b5132 | 6113 | { |
67c0d1eb | 6114 | int gpdelay; |
252b5132 RH |
6115 | |
6116 | /* If this is a reference to an external symbol, we want | |
6117 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
6118 | addu $tempreg,$tempreg,$gp | |
6119 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
6120 | <op> $treg,0($tempreg) | |
6121 | Otherwise we want | |
6122 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6123 | nop | |
6124 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
6125 | <op> $treg,0($tempreg) | |
6126 | If there is a base register, we add it to $tempreg before | |
6127 | the <op>. If there is a constant, we stick it in the | |
6128 | <op> instruction. We don't handle constants larger than | |
6129 | 16 bits, because we have no way to load the upper 16 bits | |
6130 | (actually, we could handle them for the subset of cases | |
f5040a92 | 6131 | in which we are not using $at). */ |
252b5132 RH |
6132 | assert (offset_expr.X_op == O_symbol); |
6133 | expr1.X_add_number = offset_expr.X_add_number; | |
6134 | offset_expr.X_add_number = 0; | |
6135 | if (expr1.X_add_number < -0x8000 | |
6136 | || expr1.X_add_number >= 0x8000) | |
6137 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 6138 | gpdelay = reg_needs_delay (mips_gp_register); |
4d7206a2 | 6139 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 6140 | macro_build (&offset_expr, "lui", "t,u", tempreg, |
17a2f251 | 6141 | BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
6142 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, |
6143 | mips_gp_register); | |
6144 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
6145 | BFD_RELOC_MIPS_GOT_LO16, tempreg); | |
4d7206a2 | 6146 | relax_switch (); |
67c0d1eb RS |
6147 | if (gpdelay) |
6148 | macro_build (NULL, "nop", ""); | |
6149 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
6150 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 6151 | load_delay_nop (); |
67c0d1eb RS |
6152 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, |
6153 | tempreg, BFD_RELOC_LO16); | |
4d7206a2 RS |
6154 | relax_end (); |
6155 | ||
252b5132 | 6156 | if (breg != 0) |
67c0d1eb | 6157 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6158 | tempreg, tempreg, breg); |
67c0d1eb | 6159 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
252b5132 | 6160 | } |
f5040a92 AO |
6161 | else if (mips_pic == SVR4_PIC && HAVE_NEWABI) |
6162 | { | |
f5040a92 AO |
6163 | /* If this is a reference to an external symbol, we want |
6164 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
6165 | add $tempreg,$tempreg,$gp | |
6166 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
6167 | <op> $treg,<ofst>($tempreg) | |
6168 | Otherwise, for local symbols, we want: | |
6169 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
6170 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */ | |
6171 | assert (offset_expr.X_op == O_symbol); | |
4d7206a2 | 6172 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
6173 | offset_expr.X_add_number = 0; |
6174 | if (expr1.X_add_number < -0x8000 | |
6175 | || expr1.X_add_number >= 0x8000) | |
6176 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4d7206a2 | 6177 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 6178 | macro_build (&offset_expr, "lui", "t,u", tempreg, |
17a2f251 | 6179 | BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
6180 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, |
6181 | mips_gp_register); | |
6182 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
6183 | BFD_RELOC_MIPS_GOT_LO16, tempreg); | |
f5040a92 | 6184 | if (breg != 0) |
67c0d1eb | 6185 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6186 | tempreg, tempreg, breg); |
67c0d1eb | 6187 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
684022ea | 6188 | |
4d7206a2 | 6189 | relax_switch (); |
f5040a92 | 6190 | offset_expr.X_add_number = expr1.X_add_number; |
67c0d1eb RS |
6191 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
6192 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
f5040a92 | 6193 | if (breg != 0) |
67c0d1eb | 6194 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6195 | tempreg, tempreg, breg); |
67c0d1eb | 6196 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 6197 | BFD_RELOC_MIPS_GOT_OFST, tempreg); |
4d7206a2 | 6198 | relax_end (); |
f5040a92 | 6199 | } |
252b5132 RH |
6200 | else |
6201 | abort (); | |
6202 | ||
252b5132 RH |
6203 | break; |
6204 | ||
6205 | case M_LI: | |
6206 | case M_LI_S: | |
67c0d1eb | 6207 | load_register (treg, &imm_expr, 0); |
8fc2e39e | 6208 | break; |
252b5132 RH |
6209 | |
6210 | case M_DLI: | |
67c0d1eb | 6211 | load_register (treg, &imm_expr, 1); |
8fc2e39e | 6212 | break; |
252b5132 RH |
6213 | |
6214 | case M_LI_SS: | |
6215 | if (imm_expr.X_op == O_constant) | |
6216 | { | |
8fc2e39e | 6217 | used_at = 1; |
67c0d1eb RS |
6218 | load_register (AT, &imm_expr, 0); |
6219 | macro_build (NULL, "mtc1", "t,G", AT, treg); | |
252b5132 RH |
6220 | break; |
6221 | } | |
6222 | else | |
6223 | { | |
6224 | assert (offset_expr.X_op == O_symbol | |
6225 | && strcmp (segment_name (S_GET_SEGMENT | |
6226 | (offset_expr.X_add_symbol)), | |
6227 | ".lit4") == 0 | |
6228 | && offset_expr.X_add_number == 0); | |
67c0d1eb | 6229 | macro_build (&offset_expr, "lwc1", "T,o(b)", treg, |
17a2f251 | 6230 | BFD_RELOC_MIPS_LITERAL, mips_gp_register); |
8fc2e39e | 6231 | break; |
252b5132 RH |
6232 | } |
6233 | ||
6234 | case M_LI_D: | |
ca4e0257 RS |
6235 | /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits |
6236 | wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high | |
6237 | order 32 bits of the value and the low order 32 bits are either | |
6238 | zero or in OFFSET_EXPR. */ | |
252b5132 RH |
6239 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) |
6240 | { | |
ca4e0257 | 6241 | if (HAVE_64BIT_GPRS) |
67c0d1eb | 6242 | load_register (treg, &imm_expr, 1); |
252b5132 RH |
6243 | else |
6244 | { | |
6245 | int hreg, lreg; | |
6246 | ||
6247 | if (target_big_endian) | |
6248 | { | |
6249 | hreg = treg; | |
6250 | lreg = treg + 1; | |
6251 | } | |
6252 | else | |
6253 | { | |
6254 | hreg = treg + 1; | |
6255 | lreg = treg; | |
6256 | } | |
6257 | ||
6258 | if (hreg <= 31) | |
67c0d1eb | 6259 | load_register (hreg, &imm_expr, 0); |
252b5132 RH |
6260 | if (lreg <= 31) |
6261 | { | |
6262 | if (offset_expr.X_op == O_absent) | |
67c0d1eb | 6263 | move_register (lreg, 0); |
252b5132 RH |
6264 | else |
6265 | { | |
6266 | assert (offset_expr.X_op == O_constant); | |
67c0d1eb | 6267 | load_register (lreg, &offset_expr, 0); |
252b5132 RH |
6268 | } |
6269 | } | |
6270 | } | |
8fc2e39e | 6271 | break; |
252b5132 RH |
6272 | } |
6273 | ||
6274 | /* We know that sym is in the .rdata section. First we get the | |
6275 | upper 16 bits of the address. */ | |
6276 | if (mips_pic == NO_PIC) | |
6277 | { | |
67c0d1eb | 6278 | macro_build_lui (&offset_expr, AT); |
8fc2e39e | 6279 | used_at = 1; |
252b5132 RH |
6280 | } |
6281 | else if (mips_pic == SVR4_PIC) | |
6282 | { | |
67c0d1eb RS |
6283 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, |
6284 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
8fc2e39e | 6285 | used_at = 1; |
252b5132 | 6286 | } |
252b5132 RH |
6287 | else |
6288 | abort (); | |
bdaaa2e1 | 6289 | |
252b5132 | 6290 | /* Now we load the register(s). */ |
ca4e0257 | 6291 | if (HAVE_64BIT_GPRS) |
8fc2e39e TS |
6292 | { |
6293 | used_at = 1; | |
6294 | macro_build (&offset_expr, "ld", "t,o(b)", treg, BFD_RELOC_LO16, AT); | |
6295 | } | |
252b5132 RH |
6296 | else |
6297 | { | |
8fc2e39e | 6298 | used_at = 1; |
67c0d1eb | 6299 | macro_build (&offset_expr, "lw", "t,o(b)", treg, BFD_RELOC_LO16, AT); |
f9419b05 | 6300 | if (treg != RA) |
252b5132 RH |
6301 | { |
6302 | /* FIXME: How in the world do we deal with the possible | |
6303 | overflow here? */ | |
6304 | offset_expr.X_add_number += 4; | |
67c0d1eb | 6305 | macro_build (&offset_expr, "lw", "t,o(b)", |
17a2f251 | 6306 | treg + 1, BFD_RELOC_LO16, AT); |
252b5132 RH |
6307 | } |
6308 | } | |
252b5132 RH |
6309 | break; |
6310 | ||
6311 | case M_LI_DD: | |
ca4e0257 RS |
6312 | /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits |
6313 | wide, IMM_EXPR is the entire value and the GPRs are known to be 64 | |
6314 | bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of | |
6315 | the value and the low order 32 bits are either zero or in | |
6316 | OFFSET_EXPR. */ | |
252b5132 RH |
6317 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) |
6318 | { | |
8fc2e39e | 6319 | used_at = 1; |
67c0d1eb | 6320 | load_register (AT, &imm_expr, HAVE_64BIT_FPRS); |
ca4e0257 RS |
6321 | if (HAVE_64BIT_FPRS) |
6322 | { | |
6323 | assert (HAVE_64BIT_GPRS); | |
67c0d1eb | 6324 | macro_build (NULL, "dmtc1", "t,S", AT, treg); |
ca4e0257 | 6325 | } |
252b5132 RH |
6326 | else |
6327 | { | |
67c0d1eb | 6328 | macro_build (NULL, "mtc1", "t,G", AT, treg + 1); |
252b5132 | 6329 | if (offset_expr.X_op == O_absent) |
67c0d1eb | 6330 | macro_build (NULL, "mtc1", "t,G", 0, treg); |
252b5132 RH |
6331 | else |
6332 | { | |
6333 | assert (offset_expr.X_op == O_constant); | |
67c0d1eb RS |
6334 | load_register (AT, &offset_expr, 0); |
6335 | macro_build (NULL, "mtc1", "t,G", AT, treg); | |
252b5132 RH |
6336 | } |
6337 | } | |
6338 | break; | |
6339 | } | |
6340 | ||
6341 | assert (offset_expr.X_op == O_symbol | |
6342 | && offset_expr.X_add_number == 0); | |
6343 | s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol)); | |
6344 | if (strcmp (s, ".lit8") == 0) | |
6345 | { | |
e7af610e | 6346 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 | 6347 | { |
67c0d1eb | 6348 | macro_build (&offset_expr, "ldc1", "T,o(b)", treg, |
17a2f251 | 6349 | BFD_RELOC_MIPS_LITERAL, mips_gp_register); |
8fc2e39e | 6350 | break; |
252b5132 | 6351 | } |
c9914766 | 6352 | breg = mips_gp_register; |
252b5132 RH |
6353 | r = BFD_RELOC_MIPS_LITERAL; |
6354 | goto dob; | |
6355 | } | |
6356 | else | |
6357 | { | |
6358 | assert (strcmp (s, RDATA_SECTION_NAME) == 0); | |
8fc2e39e | 6359 | used_at = 1; |
252b5132 | 6360 | if (mips_pic == SVR4_PIC) |
67c0d1eb RS |
6361 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, |
6362 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
252b5132 RH |
6363 | else |
6364 | { | |
6365 | /* FIXME: This won't work for a 64 bit address. */ | |
67c0d1eb | 6366 | macro_build_lui (&offset_expr, AT); |
252b5132 | 6367 | } |
bdaaa2e1 | 6368 | |
e7af610e | 6369 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 | 6370 | { |
67c0d1eb RS |
6371 | macro_build (&offset_expr, "ldc1", "T,o(b)", |
6372 | treg, BFD_RELOC_LO16, AT); | |
252b5132 RH |
6373 | break; |
6374 | } | |
6375 | breg = AT; | |
6376 | r = BFD_RELOC_LO16; | |
6377 | goto dob; | |
6378 | } | |
6379 | ||
6380 | case M_L_DOB: | |
fef14a42 | 6381 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
6382 | { |
6383 | as_bad (_("opcode not supported on this processor")); | |
8fc2e39e | 6384 | break; |
252b5132 RH |
6385 | } |
6386 | /* Even on a big endian machine $fn comes before $fn+1. We have | |
6387 | to adjust when loading from memory. */ | |
6388 | r = BFD_RELOC_LO16; | |
6389 | dob: | |
e7af610e | 6390 | assert (mips_opts.isa == ISA_MIPS1); |
67c0d1eb | 6391 | macro_build (&offset_expr, "lwc1", "T,o(b)", |
17a2f251 | 6392 | target_big_endian ? treg + 1 : treg, r, breg); |
252b5132 RH |
6393 | /* FIXME: A possible overflow which I don't know how to deal |
6394 | with. */ | |
6395 | offset_expr.X_add_number += 4; | |
67c0d1eb | 6396 | macro_build (&offset_expr, "lwc1", "T,o(b)", |
17a2f251 | 6397 | target_big_endian ? treg : treg + 1, r, breg); |
252b5132 RH |
6398 | break; |
6399 | ||
6400 | case M_L_DAB: | |
6401 | /* | |
6402 | * The MIPS assembler seems to check for X_add_number not | |
6403 | * being double aligned and generating: | |
6404 | * lui at,%hi(foo+1) | |
6405 | * addu at,at,v1 | |
6406 | * addiu at,at,%lo(foo+1) | |
6407 | * lwc1 f2,0(at) | |
6408 | * lwc1 f3,4(at) | |
6409 | * But, the resulting address is the same after relocation so why | |
6410 | * generate the extra instruction? | |
6411 | */ | |
fef14a42 | 6412 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
6413 | { |
6414 | as_bad (_("opcode not supported on this processor")); | |
8fc2e39e | 6415 | break; |
252b5132 | 6416 | } |
bdaaa2e1 | 6417 | /* Itbl support may require additional care here. */ |
252b5132 | 6418 | coproc = 1; |
e7af610e | 6419 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 RH |
6420 | { |
6421 | s = "ldc1"; | |
6422 | goto ld; | |
6423 | } | |
6424 | ||
6425 | s = "lwc1"; | |
6426 | fmt = "T,o(b)"; | |
6427 | goto ldd_std; | |
6428 | ||
6429 | case M_S_DAB: | |
fef14a42 | 6430 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
6431 | { |
6432 | as_bad (_("opcode not supported on this processor")); | |
8fc2e39e | 6433 | break; |
252b5132 RH |
6434 | } |
6435 | ||
e7af610e | 6436 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 RH |
6437 | { |
6438 | s = "sdc1"; | |
6439 | goto st; | |
6440 | } | |
6441 | ||
6442 | s = "swc1"; | |
6443 | fmt = "T,o(b)"; | |
bdaaa2e1 | 6444 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6445 | coproc = 1; |
6446 | goto ldd_std; | |
6447 | ||
6448 | case M_LD_AB: | |
ca4e0257 | 6449 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
6450 | { |
6451 | s = "ld"; | |
6452 | goto ld; | |
6453 | } | |
6454 | ||
6455 | s = "lw"; | |
6456 | fmt = "t,o(b)"; | |
6457 | goto ldd_std; | |
6458 | ||
6459 | case M_SD_AB: | |
ca4e0257 | 6460 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
6461 | { |
6462 | s = "sd"; | |
6463 | goto st; | |
6464 | } | |
6465 | ||
6466 | s = "sw"; | |
6467 | fmt = "t,o(b)"; | |
6468 | ||
6469 | ldd_std: | |
6470 | if (offset_expr.X_op != O_symbol | |
6471 | && offset_expr.X_op != O_constant) | |
6472 | { | |
6473 | as_bad (_("expression too complex")); | |
6474 | offset_expr.X_op = O_constant; | |
6475 | } | |
6476 | ||
6477 | /* Even on a big endian machine $fn comes before $fn+1. We have | |
6478 | to adjust when loading from memory. We set coproc if we must | |
6479 | load $fn+1 first. */ | |
bdaaa2e1 | 6480 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6481 | if (! target_big_endian) |
6482 | coproc = 0; | |
6483 | ||
6484 | if (mips_pic == NO_PIC | |
6485 | || offset_expr.X_op == O_constant) | |
6486 | { | |
6487 | /* If this is a reference to a GP relative symbol, we want | |
cdf6fd85 TS |
6488 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
6489 | <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16) | |
252b5132 RH |
6490 | If we have a base register, we use this |
6491 | addu $at,$breg,$gp | |
cdf6fd85 TS |
6492 | <op> $treg,<sym>($at) (BFD_RELOC_GPREL16) |
6493 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16) | |
252b5132 RH |
6494 | If this is not a GP relative symbol, we want |
6495 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
6496 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
6497 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
6498 | If there is a base register, we add it to $at after the | |
6499 | lui instruction. If there is a constant, we always use | |
6500 | the last case. */ | |
e7d556df | 6501 | if ((valueT) offset_expr.X_add_number > MAX_GPREL_OFFSET |
252b5132 | 6502 | || nopic_need_relax (offset_expr.X_add_symbol, 1)) |
67c0d1eb | 6503 | used_at = 1; |
252b5132 RH |
6504 | else |
6505 | { | |
4d7206a2 | 6506 | relax_start (offset_expr.X_add_symbol); |
252b5132 RH |
6507 | if (breg == 0) |
6508 | { | |
c9914766 | 6509 | tempreg = mips_gp_register; |
252b5132 RH |
6510 | } |
6511 | else | |
6512 | { | |
67c0d1eb | 6513 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6514 | AT, breg, mips_gp_register); |
252b5132 | 6515 | tempreg = AT; |
252b5132 RH |
6516 | used_at = 1; |
6517 | } | |
6518 | ||
beae10d5 | 6519 | /* Itbl support may require additional care here. */ |
67c0d1eb | 6520 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 6521 | BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
6522 | offset_expr.X_add_number += 4; |
6523 | ||
6524 | /* Set mips_optimize to 2 to avoid inserting an | |
6525 | undesired nop. */ | |
6526 | hold_mips_optimize = mips_optimize; | |
6527 | mips_optimize = 2; | |
beae10d5 | 6528 | /* Itbl support may require additional care here. */ |
67c0d1eb | 6529 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 6530 | BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
6531 | mips_optimize = hold_mips_optimize; |
6532 | ||
4d7206a2 | 6533 | relax_switch (); |
252b5132 RH |
6534 | |
6535 | /* We just generated two relocs. When tc_gen_reloc | |
6536 | handles this case, it will skip the first reloc and | |
6537 | handle the second. The second reloc already has an | |
6538 | extra addend of 4, which we added above. We must | |
6539 | subtract it out, and then subtract another 4 to make | |
6540 | the first reloc come out right. The second reloc | |
6541 | will come out right because we are going to add 4 to | |
6542 | offset_expr when we build its instruction below. | |
6543 | ||
6544 | If we have a symbol, then we don't want to include | |
6545 | the offset, because it will wind up being included | |
6546 | when we generate the reloc. */ | |
6547 | ||
6548 | if (offset_expr.X_op == O_constant) | |
6549 | offset_expr.X_add_number -= 8; | |
6550 | else | |
6551 | { | |
6552 | offset_expr.X_add_number = -4; | |
6553 | offset_expr.X_op = O_constant; | |
6554 | } | |
6555 | } | |
8fc2e39e | 6556 | used_at = 1; |
67c0d1eb | 6557 | macro_build_lui (&offset_expr, AT); |
252b5132 | 6558 | if (breg != 0) |
67c0d1eb | 6559 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 6560 | /* Itbl support may require additional care here. */ |
67c0d1eb | 6561 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 6562 | BFD_RELOC_LO16, AT); |
252b5132 RH |
6563 | /* FIXME: How do we handle overflow here? */ |
6564 | offset_expr.X_add_number += 4; | |
beae10d5 | 6565 | /* Itbl support may require additional care here. */ |
67c0d1eb | 6566 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 6567 | BFD_RELOC_LO16, AT); |
4d7206a2 RS |
6568 | if (mips_relax.sequence) |
6569 | relax_end (); | |
bdaaa2e1 | 6570 | } |
252b5132 RH |
6571 | else if (mips_pic == SVR4_PIC && ! mips_big_got) |
6572 | { | |
252b5132 RH |
6573 | /* If this is a reference to an external symbol, we want |
6574 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6575 | nop | |
6576 | <op> $treg,0($at) | |
6577 | <op> $treg+1,4($at) | |
6578 | Otherwise we want | |
6579 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6580 | nop | |
6581 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
6582 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
6583 | If there is a base register we add it to $at before the | |
6584 | lwc1 instructions. If there is a constant we include it | |
6585 | in the lwc1 instructions. */ | |
6586 | used_at = 1; | |
6587 | expr1.X_add_number = offset_expr.X_add_number; | |
252b5132 RH |
6588 | if (expr1.X_add_number < -0x8000 |
6589 | || expr1.X_add_number >= 0x8000 - 4) | |
6590 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 6591 | load_got_offset (AT, &offset_expr); |
269137b2 | 6592 | load_delay_nop (); |
252b5132 | 6593 | if (breg != 0) |
67c0d1eb | 6594 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
252b5132 RH |
6595 | |
6596 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
6597 | nop. */ | |
6598 | hold_mips_optimize = mips_optimize; | |
6599 | mips_optimize = 2; | |
4d7206a2 | 6600 | |
beae10d5 | 6601 | /* Itbl support may require additional care here. */ |
4d7206a2 | 6602 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
6603 | macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg, |
6604 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 6605 | expr1.X_add_number += 4; |
67c0d1eb RS |
6606 | macro_build (&expr1, s, fmt, coproc ? treg : treg + 1, |
6607 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 6608 | relax_switch (); |
67c0d1eb RS |
6609 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
6610 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 6611 | offset_expr.X_add_number += 4; |
67c0d1eb RS |
6612 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
6613 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 6614 | relax_end (); |
252b5132 | 6615 | |
4d7206a2 | 6616 | mips_optimize = hold_mips_optimize; |
252b5132 RH |
6617 | } |
6618 | else if (mips_pic == SVR4_PIC) | |
6619 | { | |
67c0d1eb | 6620 | int gpdelay; |
252b5132 RH |
6621 | |
6622 | /* If this is a reference to an external symbol, we want | |
6623 | lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
6624 | addu $at,$at,$gp | |
6625 | lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16) | |
6626 | nop | |
6627 | <op> $treg,0($at) | |
6628 | <op> $treg+1,4($at) | |
6629 | Otherwise we want | |
6630 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6631 | nop | |
6632 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
6633 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
6634 | If there is a base register we add it to $at before the | |
6635 | lwc1 instructions. If there is a constant we include it | |
6636 | in the lwc1 instructions. */ | |
6637 | used_at = 1; | |
6638 | expr1.X_add_number = offset_expr.X_add_number; | |
6639 | offset_expr.X_add_number = 0; | |
6640 | if (expr1.X_add_number < -0x8000 | |
6641 | || expr1.X_add_number >= 0x8000 - 4) | |
6642 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 6643 | gpdelay = reg_needs_delay (mips_gp_register); |
4d7206a2 | 6644 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
6645 | macro_build (&offset_expr, "lui", "t,u", |
6646 | AT, BFD_RELOC_MIPS_GOT_HI16); | |
6647 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 6648 | AT, AT, mips_gp_register); |
67c0d1eb | 6649 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
17a2f251 | 6650 | AT, BFD_RELOC_MIPS_GOT_LO16, AT); |
269137b2 | 6651 | load_delay_nop (); |
252b5132 | 6652 | if (breg != 0) |
67c0d1eb | 6653 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 6654 | /* Itbl support may require additional care here. */ |
67c0d1eb | 6655 | macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 6656 | BFD_RELOC_LO16, AT); |
252b5132 RH |
6657 | expr1.X_add_number += 4; |
6658 | ||
6659 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
6660 | nop. */ | |
6661 | hold_mips_optimize = mips_optimize; | |
6662 | mips_optimize = 2; | |
beae10d5 | 6663 | /* Itbl support may require additional care here. */ |
67c0d1eb | 6664 | macro_build (&expr1, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 6665 | BFD_RELOC_LO16, AT); |
252b5132 RH |
6666 | mips_optimize = hold_mips_optimize; |
6667 | expr1.X_add_number -= 4; | |
6668 | ||
4d7206a2 RS |
6669 | relax_switch (); |
6670 | offset_expr.X_add_number = expr1.X_add_number; | |
67c0d1eb RS |
6671 | if (gpdelay) |
6672 | macro_build (NULL, "nop", ""); | |
6673 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, | |
6674 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 6675 | load_delay_nop (); |
252b5132 | 6676 | if (breg != 0) |
67c0d1eb | 6677 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 6678 | /* Itbl support may require additional care here. */ |
67c0d1eb RS |
6679 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
6680 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 6681 | offset_expr.X_add_number += 4; |
252b5132 RH |
6682 | |
6683 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
6684 | nop. */ | |
6685 | hold_mips_optimize = mips_optimize; | |
6686 | mips_optimize = 2; | |
beae10d5 | 6687 | /* Itbl support may require additional care here. */ |
67c0d1eb RS |
6688 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
6689 | BFD_RELOC_LO16, AT); | |
252b5132 | 6690 | mips_optimize = hold_mips_optimize; |
4d7206a2 | 6691 | relax_end (); |
252b5132 | 6692 | } |
252b5132 RH |
6693 | else |
6694 | abort (); | |
6695 | ||
252b5132 RH |
6696 | break; |
6697 | ||
6698 | case M_LD_OB: | |
6699 | s = "lw"; | |
6700 | goto sd_ob; | |
6701 | case M_SD_OB: | |
6702 | s = "sw"; | |
6703 | sd_ob: | |
ca4e0257 | 6704 | assert (HAVE_32BIT_ADDRESSES); |
67c0d1eb | 6705 | macro_build (&offset_expr, s, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
252b5132 | 6706 | offset_expr.X_add_number += 4; |
67c0d1eb | 6707 | macro_build (&offset_expr, s, "t,o(b)", treg + 1, BFD_RELOC_LO16, breg); |
8fc2e39e | 6708 | break; |
252b5132 RH |
6709 | |
6710 | /* New code added to support COPZ instructions. | |
6711 | This code builds table entries out of the macros in mip_opcodes. | |
6712 | R4000 uses interlocks to handle coproc delays. | |
6713 | Other chips (like the R3000) require nops to be inserted for delays. | |
6714 | ||
f72c8c98 | 6715 | FIXME: Currently, we require that the user handle delays. |
252b5132 RH |
6716 | In order to fill delay slots for non-interlocked chips, |
6717 | we must have a way to specify delays based on the coprocessor. | |
6718 | Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc. | |
6719 | What are the side-effects of the cop instruction? | |
6720 | What cache support might we have and what are its effects? | |
6721 | Both coprocessor & memory require delays. how long??? | |
bdaaa2e1 | 6722 | What registers are read/set/modified? |
252b5132 RH |
6723 | |
6724 | If an itbl is provided to interpret cop instructions, | |
bdaaa2e1 | 6725 | this knowledge can be encoded in the itbl spec. */ |
252b5132 RH |
6726 | |
6727 | case M_COP0: | |
6728 | s = "c0"; | |
6729 | goto copz; | |
6730 | case M_COP1: | |
6731 | s = "c1"; | |
6732 | goto copz; | |
6733 | case M_COP2: | |
6734 | s = "c2"; | |
6735 | goto copz; | |
6736 | case M_COP3: | |
6737 | s = "c3"; | |
6738 | copz: | |
6739 | /* For now we just do C (same as Cz). The parameter will be | |
6740 | stored in insn_opcode by mips_ip. */ | |
67c0d1eb | 6741 | macro_build (NULL, s, "C", ip->insn_opcode); |
8fc2e39e | 6742 | break; |
252b5132 | 6743 | |
ea1fb5dc | 6744 | case M_MOVE: |
67c0d1eb | 6745 | move_register (dreg, sreg); |
8fc2e39e | 6746 | break; |
ea1fb5dc | 6747 | |
252b5132 RH |
6748 | #ifdef LOSING_COMPILER |
6749 | default: | |
6750 | /* Try and see if this is a new itbl instruction. | |
6751 | This code builds table entries out of the macros in mip_opcodes. | |
6752 | FIXME: For now we just assemble the expression and pass it's | |
6753 | value along as a 32-bit immediate. | |
bdaaa2e1 | 6754 | We may want to have the assembler assemble this value, |
252b5132 RH |
6755 | so that we gain the assembler's knowledge of delay slots, |
6756 | symbols, etc. | |
6757 | Would it be more efficient to use mask (id) here? */ | |
bdaaa2e1 | 6758 | if (itbl_have_entries |
252b5132 | 6759 | && (immed_expr = itbl_assemble (ip->insn_mo->name, ""))) |
beae10d5 | 6760 | { |
252b5132 RH |
6761 | s = ip->insn_mo->name; |
6762 | s2 = "cop3"; | |
6763 | coproc = ITBL_DECODE_PNUM (immed_expr);; | |
67c0d1eb | 6764 | macro_build (&immed_expr, s, "C"); |
8fc2e39e | 6765 | break; |
beae10d5 | 6766 | } |
252b5132 | 6767 | macro2 (ip); |
8fc2e39e | 6768 | break; |
252b5132 | 6769 | } |
8fc2e39e TS |
6770 | if (mips_opts.noat && used_at) |
6771 | as_bad (_("Macro used $at after \".set noat\"")); | |
252b5132 | 6772 | } |
bdaaa2e1 | 6773 | |
252b5132 | 6774 | static void |
17a2f251 | 6775 | macro2 (struct mips_cl_insn *ip) |
252b5132 RH |
6776 | { |
6777 | register int treg, sreg, dreg, breg; | |
6778 | int tempreg; | |
6779 | int mask; | |
252b5132 RH |
6780 | int used_at; |
6781 | expressionS expr1; | |
6782 | const char *s; | |
6783 | const char *s2; | |
6784 | const char *fmt; | |
6785 | int likely = 0; | |
6786 | int dbl = 0; | |
6787 | int coproc = 0; | |
6788 | int lr = 0; | |
6789 | int imm = 0; | |
6790 | int off; | |
6791 | offsetT maxnum; | |
6792 | bfd_reloc_code_real_type r; | |
bdaaa2e1 | 6793 | |
252b5132 RH |
6794 | treg = (ip->insn_opcode >> 16) & 0x1f; |
6795 | dreg = (ip->insn_opcode >> 11) & 0x1f; | |
6796 | sreg = breg = (ip->insn_opcode >> 21) & 0x1f; | |
6797 | mask = ip->insn_mo->mask; | |
bdaaa2e1 | 6798 | |
252b5132 RH |
6799 | expr1.X_op = O_constant; |
6800 | expr1.X_op_symbol = NULL; | |
6801 | expr1.X_add_symbol = NULL; | |
6802 | expr1.X_add_number = 1; | |
bdaaa2e1 | 6803 | |
252b5132 RH |
6804 | switch (mask) |
6805 | { | |
6806 | #endif /* LOSING_COMPILER */ | |
6807 | ||
6808 | case M_DMUL: | |
6809 | dbl = 1; | |
6810 | case M_MUL: | |
67c0d1eb RS |
6811 | macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", sreg, treg); |
6812 | macro_build (NULL, "mflo", "d", dreg); | |
8fc2e39e | 6813 | break; |
252b5132 RH |
6814 | |
6815 | case M_DMUL_I: | |
6816 | dbl = 1; | |
6817 | case M_MUL_I: | |
6818 | /* The MIPS assembler some times generates shifts and adds. I'm | |
6819 | not trying to be that fancy. GCC should do this for us | |
6820 | anyway. */ | |
8fc2e39e | 6821 | used_at = 1; |
67c0d1eb RS |
6822 | load_register (AT, &imm_expr, dbl); |
6823 | macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, AT); | |
6824 | macro_build (NULL, "mflo", "d", dreg); | |
252b5132 RH |
6825 | break; |
6826 | ||
6827 | case M_DMULO_I: | |
6828 | dbl = 1; | |
6829 | case M_MULO_I: | |
6830 | imm = 1; | |
6831 | goto do_mulo; | |
6832 | ||
6833 | case M_DMULO: | |
6834 | dbl = 1; | |
6835 | case M_MULO: | |
6836 | do_mulo: | |
b34976b6 | 6837 | mips_emit_delays (TRUE); |
252b5132 RH |
6838 | ++mips_opts.noreorder; |
6839 | mips_any_noreorder = 1; | |
8fc2e39e | 6840 | used_at = 1; |
252b5132 | 6841 | if (imm) |
67c0d1eb RS |
6842 | load_register (AT, &imm_expr, dbl); |
6843 | macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, imm ? AT : treg); | |
6844 | macro_build (NULL, "mflo", "d", dreg); | |
6845 | macro_build (NULL, dbl ? "dsra32" : "sra", "d,w,<", dreg, dreg, RA); | |
6846 | macro_build (NULL, "mfhi", "d", AT); | |
252b5132 | 6847 | if (mips_trap) |
67c0d1eb | 6848 | macro_build (NULL, "tne", "s,t,q", dreg, AT, 6); |
252b5132 RH |
6849 | else |
6850 | { | |
6851 | expr1.X_add_number = 8; | |
67c0d1eb RS |
6852 | macro_build (&expr1, "beq", "s,t,p", dreg, AT); |
6853 | macro_build (NULL, "nop", "", 0); | |
6854 | macro_build (NULL, "break", "c", 6); | |
252b5132 RH |
6855 | } |
6856 | --mips_opts.noreorder; | |
67c0d1eb | 6857 | macro_build (NULL, "mflo", "d", dreg); |
252b5132 RH |
6858 | break; |
6859 | ||
6860 | case M_DMULOU_I: | |
6861 | dbl = 1; | |
6862 | case M_MULOU_I: | |
6863 | imm = 1; | |
6864 | goto do_mulou; | |
6865 | ||
6866 | case M_DMULOU: | |
6867 | dbl = 1; | |
6868 | case M_MULOU: | |
6869 | do_mulou: | |
b34976b6 | 6870 | mips_emit_delays (TRUE); |
252b5132 RH |
6871 | ++mips_opts.noreorder; |
6872 | mips_any_noreorder = 1; | |
8fc2e39e | 6873 | used_at = 1; |
252b5132 | 6874 | if (imm) |
67c0d1eb RS |
6875 | load_register (AT, &imm_expr, dbl); |
6876 | macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", | |
17a2f251 | 6877 | sreg, imm ? AT : treg); |
67c0d1eb RS |
6878 | macro_build (NULL, "mfhi", "d", AT); |
6879 | macro_build (NULL, "mflo", "d", dreg); | |
252b5132 | 6880 | if (mips_trap) |
67c0d1eb | 6881 | macro_build (NULL, "tne", "s,t,q", AT, 0, 6); |
252b5132 RH |
6882 | else |
6883 | { | |
6884 | expr1.X_add_number = 8; | |
67c0d1eb RS |
6885 | macro_build (&expr1, "beq", "s,t,p", AT, 0); |
6886 | macro_build (NULL, "nop", "", 0); | |
6887 | macro_build (NULL, "break", "c", 6); | |
252b5132 RH |
6888 | } |
6889 | --mips_opts.noreorder; | |
6890 | break; | |
6891 | ||
771c7ce4 | 6892 | case M_DROL: |
fef14a42 | 6893 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 CD |
6894 | { |
6895 | if (dreg == sreg) | |
6896 | { | |
6897 | tempreg = AT; | |
6898 | used_at = 1; | |
6899 | } | |
6900 | else | |
6901 | { | |
6902 | tempreg = dreg; | |
82dd0097 | 6903 | } |
67c0d1eb RS |
6904 | macro_build (NULL, "dnegu", "d,w", tempreg, treg); |
6905 | macro_build (NULL, "drorv", "d,t,s", dreg, sreg, tempreg); | |
8fc2e39e | 6906 | break; |
82dd0097 | 6907 | } |
8fc2e39e | 6908 | used_at = 1; |
67c0d1eb RS |
6909 | macro_build (NULL, "dsubu", "d,v,t", AT, 0, treg); |
6910 | macro_build (NULL, "dsrlv", "d,t,s", AT, sreg, AT); | |
6911 | macro_build (NULL, "dsllv", "d,t,s", dreg, sreg, treg); | |
6912 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
6913 | break; |
6914 | ||
252b5132 | 6915 | case M_ROL: |
fef14a42 | 6916 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 CD |
6917 | { |
6918 | if (dreg == sreg) | |
6919 | { | |
6920 | tempreg = AT; | |
6921 | used_at = 1; | |
6922 | } | |
6923 | else | |
6924 | { | |
6925 | tempreg = dreg; | |
82dd0097 | 6926 | } |
67c0d1eb RS |
6927 | macro_build (NULL, "negu", "d,w", tempreg, treg); |
6928 | macro_build (NULL, "rorv", "d,t,s", dreg, sreg, tempreg); | |
8fc2e39e | 6929 | break; |
82dd0097 | 6930 | } |
8fc2e39e | 6931 | used_at = 1; |
67c0d1eb RS |
6932 | macro_build (NULL, "subu", "d,v,t", AT, 0, treg); |
6933 | macro_build (NULL, "srlv", "d,t,s", AT, sreg, AT); | |
6934 | macro_build (NULL, "sllv", "d,t,s", dreg, sreg, treg); | |
6935 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
6936 | break; |
6937 | ||
771c7ce4 TS |
6938 | case M_DROL_I: |
6939 | { | |
6940 | unsigned int rot; | |
82dd0097 | 6941 | char *l, *r; |
771c7ce4 TS |
6942 | |
6943 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 6944 | as_bad (_("Improper rotate count")); |
771c7ce4 | 6945 | rot = imm_expr.X_add_number & 0x3f; |
fef14a42 | 6946 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
60b63b72 RS |
6947 | { |
6948 | rot = (64 - rot) & 0x3f; | |
6949 | if (rot >= 32) | |
67c0d1eb | 6950 | macro_build (NULL, "dror32", "d,w,<", dreg, sreg, rot - 32); |
60b63b72 | 6951 | else |
67c0d1eb | 6952 | macro_build (NULL, "dror", "d,w,<", dreg, sreg, rot); |
8fc2e39e | 6953 | break; |
60b63b72 | 6954 | } |
483fc7cd | 6955 | if (rot == 0) |
483fc7cd | 6956 | { |
67c0d1eb | 6957 | macro_build (NULL, "dsrl", "d,w,<", dreg, sreg, 0); |
8fc2e39e | 6958 | break; |
483fc7cd | 6959 | } |
82dd0097 CD |
6960 | l = (rot < 0x20) ? "dsll" : "dsll32"; |
6961 | r = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32"; | |
6962 | rot &= 0x1f; | |
8fc2e39e | 6963 | used_at = 1; |
67c0d1eb RS |
6964 | macro_build (NULL, l, "d,w,<", AT, sreg, rot); |
6965 | macro_build (NULL, r, "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); | |
6966 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
6967 | } |
6968 | break; | |
6969 | ||
252b5132 | 6970 | case M_ROL_I: |
771c7ce4 TS |
6971 | { |
6972 | unsigned int rot; | |
6973 | ||
6974 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 6975 | as_bad (_("Improper rotate count")); |
771c7ce4 | 6976 | rot = imm_expr.X_add_number & 0x1f; |
fef14a42 | 6977 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
60b63b72 | 6978 | { |
67c0d1eb | 6979 | macro_build (NULL, "ror", "d,w,<", dreg, sreg, (32 - rot) & 0x1f); |
8fc2e39e | 6980 | break; |
60b63b72 | 6981 | } |
483fc7cd | 6982 | if (rot == 0) |
483fc7cd | 6983 | { |
67c0d1eb | 6984 | macro_build (NULL, "srl", "d,w,<", dreg, sreg, 0); |
8fc2e39e | 6985 | break; |
483fc7cd | 6986 | } |
8fc2e39e | 6987 | used_at = 1; |
67c0d1eb RS |
6988 | macro_build (NULL, "sll", "d,w,<", AT, sreg, rot); |
6989 | macro_build (NULL, "srl", "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); | |
6990 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
6991 | } |
6992 | break; | |
6993 | ||
6994 | case M_DROR: | |
fef14a42 | 6995 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 | 6996 | { |
67c0d1eb | 6997 | macro_build (NULL, "drorv", "d,t,s", dreg, sreg, treg); |
8fc2e39e | 6998 | break; |
82dd0097 | 6999 | } |
8fc2e39e | 7000 | used_at = 1; |
67c0d1eb RS |
7001 | macro_build (NULL, "dsubu", "d,v,t", AT, 0, treg); |
7002 | macro_build (NULL, "dsllv", "d,t,s", AT, sreg, AT); | |
7003 | macro_build (NULL, "dsrlv", "d,t,s", dreg, sreg, treg); | |
7004 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
7005 | break; |
7006 | ||
7007 | case M_ROR: | |
fef14a42 | 7008 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 | 7009 | { |
67c0d1eb | 7010 | macro_build (NULL, "rorv", "d,t,s", dreg, sreg, treg); |
8fc2e39e | 7011 | break; |
82dd0097 | 7012 | } |
8fc2e39e | 7013 | used_at = 1; |
67c0d1eb RS |
7014 | macro_build (NULL, "subu", "d,v,t", AT, 0, treg); |
7015 | macro_build (NULL, "sllv", "d,t,s", AT, sreg, AT); | |
7016 | macro_build (NULL, "srlv", "d,t,s", dreg, sreg, treg); | |
7017 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
7018 | break; |
7019 | ||
771c7ce4 TS |
7020 | case M_DROR_I: |
7021 | { | |
7022 | unsigned int rot; | |
82dd0097 | 7023 | char *l, *r; |
771c7ce4 TS |
7024 | |
7025 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 7026 | as_bad (_("Improper rotate count")); |
771c7ce4 | 7027 | rot = imm_expr.X_add_number & 0x3f; |
fef14a42 | 7028 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 CD |
7029 | { |
7030 | if (rot >= 32) | |
67c0d1eb | 7031 | macro_build (NULL, "dror32", "d,w,<", dreg, sreg, rot - 32); |
82dd0097 | 7032 | else |
67c0d1eb | 7033 | macro_build (NULL, "dror", "d,w,<", dreg, sreg, rot); |
8fc2e39e | 7034 | break; |
82dd0097 | 7035 | } |
483fc7cd | 7036 | if (rot == 0) |
483fc7cd | 7037 | { |
67c0d1eb | 7038 | macro_build (NULL, "dsrl", "d,w,<", dreg, sreg, 0); |
8fc2e39e | 7039 | break; |
483fc7cd | 7040 | } |
82dd0097 CD |
7041 | r = (rot < 0x20) ? "dsrl" : "dsrl32"; |
7042 | l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32"; | |
7043 | rot &= 0x1f; | |
8fc2e39e | 7044 | used_at = 1; |
67c0d1eb RS |
7045 | macro_build (NULL, r, "d,w,<", AT, sreg, rot); |
7046 | macro_build (NULL, l, "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); | |
7047 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
7048 | } |
7049 | break; | |
7050 | ||
252b5132 | 7051 | case M_ROR_I: |
771c7ce4 TS |
7052 | { |
7053 | unsigned int rot; | |
7054 | ||
7055 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 7056 | as_bad (_("Improper rotate count")); |
771c7ce4 | 7057 | rot = imm_expr.X_add_number & 0x1f; |
fef14a42 | 7058 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 | 7059 | { |
67c0d1eb | 7060 | macro_build (NULL, "ror", "d,w,<", dreg, sreg, rot); |
8fc2e39e | 7061 | break; |
82dd0097 | 7062 | } |
483fc7cd | 7063 | if (rot == 0) |
483fc7cd | 7064 | { |
67c0d1eb | 7065 | macro_build (NULL, "srl", "d,w,<", dreg, sreg, 0); |
8fc2e39e | 7066 | break; |
483fc7cd | 7067 | } |
8fc2e39e | 7068 | used_at = 1; |
67c0d1eb RS |
7069 | macro_build (NULL, "srl", "d,w,<", AT, sreg, rot); |
7070 | macro_build (NULL, "sll", "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); | |
7071 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 | 7072 | } |
252b5132 RH |
7073 | break; |
7074 | ||
7075 | case M_S_DOB: | |
fef14a42 | 7076 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
7077 | { |
7078 | as_bad (_("opcode not supported on this processor")); | |
8fc2e39e | 7079 | break; |
252b5132 | 7080 | } |
e7af610e | 7081 | assert (mips_opts.isa == ISA_MIPS1); |
252b5132 RH |
7082 | /* Even on a big endian machine $fn comes before $fn+1. We have |
7083 | to adjust when storing to memory. */ | |
67c0d1eb RS |
7084 | macro_build (&offset_expr, "swc1", "T,o(b)", |
7085 | target_big_endian ? treg + 1 : treg, BFD_RELOC_LO16, breg); | |
252b5132 | 7086 | offset_expr.X_add_number += 4; |
67c0d1eb RS |
7087 | macro_build (&offset_expr, "swc1", "T,o(b)", |
7088 | target_big_endian ? treg : treg + 1, BFD_RELOC_LO16, breg); | |
8fc2e39e | 7089 | break; |
252b5132 RH |
7090 | |
7091 | case M_SEQ: | |
7092 | if (sreg == 0) | |
67c0d1eb | 7093 | macro_build (&expr1, "sltiu", "t,r,j", dreg, treg, BFD_RELOC_LO16); |
252b5132 | 7094 | else if (treg == 0) |
67c0d1eb | 7095 | macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7096 | else |
7097 | { | |
67c0d1eb RS |
7098 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg); |
7099 | macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16); | |
252b5132 | 7100 | } |
8fc2e39e | 7101 | break; |
252b5132 RH |
7102 | |
7103 | case M_SEQ_I: | |
7104 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
7105 | { | |
67c0d1eb | 7106 | macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 7107 | break; |
252b5132 RH |
7108 | } |
7109 | if (sreg == 0) | |
7110 | { | |
7111 | as_warn (_("Instruction %s: result is always false"), | |
7112 | ip->insn_mo->name); | |
67c0d1eb | 7113 | move_register (dreg, 0); |
8fc2e39e | 7114 | break; |
252b5132 RH |
7115 | } |
7116 | if (imm_expr.X_op == O_constant | |
7117 | && imm_expr.X_add_number >= 0 | |
7118 | && imm_expr.X_add_number < 0x10000) | |
7119 | { | |
67c0d1eb | 7120 | macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7121 | } |
7122 | else if (imm_expr.X_op == O_constant | |
7123 | && imm_expr.X_add_number > -0x8000 | |
7124 | && imm_expr.X_add_number < 0) | |
7125 | { | |
7126 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 7127 | macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu", |
17a2f251 | 7128 | "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7129 | } |
7130 | else | |
7131 | { | |
67c0d1eb RS |
7132 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7133 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7134 | used_at = 1; |
7135 | } | |
67c0d1eb | 7136 | macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16); |
8fc2e39e | 7137 | break; |
252b5132 RH |
7138 | |
7139 | case M_SGE: /* sreg >= treg <==> not (sreg < treg) */ | |
7140 | s = "slt"; | |
7141 | goto sge; | |
7142 | case M_SGEU: | |
7143 | s = "sltu"; | |
7144 | sge: | |
67c0d1eb RS |
7145 | macro_build (NULL, s, "d,v,t", dreg, sreg, treg); |
7146 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
8fc2e39e | 7147 | break; |
252b5132 RH |
7148 | |
7149 | case M_SGE_I: /* sreg >= I <==> not (sreg < I) */ | |
7150 | case M_SGEU_I: | |
7151 | if (imm_expr.X_op == O_constant | |
7152 | && imm_expr.X_add_number >= -0x8000 | |
7153 | && imm_expr.X_add_number < 0x8000) | |
7154 | { | |
67c0d1eb RS |
7155 | macro_build (&imm_expr, mask == M_SGE_I ? "slti" : "sltiu", "t,r,j", |
7156 | dreg, sreg, BFD_RELOC_LO16); | |
252b5132 RH |
7157 | } |
7158 | else | |
7159 | { | |
67c0d1eb RS |
7160 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7161 | macro_build (NULL, mask == M_SGE_I ? "slt" : "sltu", "d,v,t", | |
7162 | dreg, sreg, AT); | |
252b5132 RH |
7163 | used_at = 1; |
7164 | } | |
67c0d1eb | 7165 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); |
8fc2e39e | 7166 | break; |
252b5132 RH |
7167 | |
7168 | case M_SGT: /* sreg > treg <==> treg < sreg */ | |
7169 | s = "slt"; | |
7170 | goto sgt; | |
7171 | case M_SGTU: | |
7172 | s = "sltu"; | |
7173 | sgt: | |
67c0d1eb | 7174 | macro_build (NULL, s, "d,v,t", dreg, treg, sreg); |
8fc2e39e | 7175 | break; |
252b5132 RH |
7176 | |
7177 | case M_SGT_I: /* sreg > I <==> I < sreg */ | |
7178 | s = "slt"; | |
7179 | goto sgti; | |
7180 | case M_SGTU_I: | |
7181 | s = "sltu"; | |
7182 | sgti: | |
8fc2e39e | 7183 | used_at = 1; |
67c0d1eb RS |
7184 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7185 | macro_build (NULL, s, "d,v,t", dreg, AT, sreg); | |
252b5132 RH |
7186 | break; |
7187 | ||
2396cfb9 | 7188 | case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */ |
252b5132 RH |
7189 | s = "slt"; |
7190 | goto sle; | |
7191 | case M_SLEU: | |
7192 | s = "sltu"; | |
7193 | sle: | |
67c0d1eb RS |
7194 | macro_build (NULL, s, "d,v,t", dreg, treg, sreg); |
7195 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
8fc2e39e | 7196 | break; |
252b5132 | 7197 | |
2396cfb9 | 7198 | case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */ |
252b5132 RH |
7199 | s = "slt"; |
7200 | goto slei; | |
7201 | case M_SLEU_I: | |
7202 | s = "sltu"; | |
7203 | slei: | |
8fc2e39e | 7204 | used_at = 1; |
67c0d1eb RS |
7205 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7206 | macro_build (NULL, s, "d,v,t", dreg, AT, sreg); | |
7207 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
252b5132 RH |
7208 | break; |
7209 | ||
7210 | case M_SLT_I: | |
7211 | if (imm_expr.X_op == O_constant | |
7212 | && imm_expr.X_add_number >= -0x8000 | |
7213 | && imm_expr.X_add_number < 0x8000) | |
7214 | { | |
67c0d1eb | 7215 | macro_build (&imm_expr, "slti", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 7216 | break; |
252b5132 | 7217 | } |
8fc2e39e | 7218 | used_at = 1; |
67c0d1eb RS |
7219 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7220 | macro_build (NULL, "slt", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7221 | break; |
7222 | ||
7223 | case M_SLTU_I: | |
7224 | if (imm_expr.X_op == O_constant | |
7225 | && imm_expr.X_add_number >= -0x8000 | |
7226 | && imm_expr.X_add_number < 0x8000) | |
7227 | { | |
67c0d1eb | 7228 | macro_build (&imm_expr, "sltiu", "t,r,j", dreg, sreg, |
17a2f251 | 7229 | BFD_RELOC_LO16); |
8fc2e39e | 7230 | break; |
252b5132 | 7231 | } |
8fc2e39e | 7232 | used_at = 1; |
67c0d1eb RS |
7233 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7234 | macro_build (NULL, "sltu", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7235 | break; |
7236 | ||
7237 | case M_SNE: | |
7238 | if (sreg == 0) | |
67c0d1eb | 7239 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, treg); |
252b5132 | 7240 | else if (treg == 0) |
67c0d1eb | 7241 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg); |
252b5132 RH |
7242 | else |
7243 | { | |
67c0d1eb RS |
7244 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg); |
7245 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg); | |
252b5132 | 7246 | } |
8fc2e39e | 7247 | break; |
252b5132 RH |
7248 | |
7249 | case M_SNE_I: | |
7250 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
7251 | { | |
67c0d1eb | 7252 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg); |
8fc2e39e | 7253 | break; |
252b5132 RH |
7254 | } |
7255 | if (sreg == 0) | |
7256 | { | |
7257 | as_warn (_("Instruction %s: result is always true"), | |
7258 | ip->insn_mo->name); | |
67c0d1eb RS |
7259 | macro_build (&expr1, HAVE_32BIT_GPRS ? "addiu" : "daddiu", "t,r,j", |
7260 | dreg, 0, BFD_RELOC_LO16); | |
8fc2e39e | 7261 | break; |
252b5132 RH |
7262 | } |
7263 | if (imm_expr.X_op == O_constant | |
7264 | && imm_expr.X_add_number >= 0 | |
7265 | && imm_expr.X_add_number < 0x10000) | |
7266 | { | |
67c0d1eb | 7267 | macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7268 | } |
7269 | else if (imm_expr.X_op == O_constant | |
7270 | && imm_expr.X_add_number > -0x8000 | |
7271 | && imm_expr.X_add_number < 0) | |
7272 | { | |
7273 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 7274 | macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu", |
17a2f251 | 7275 | "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7276 | } |
7277 | else | |
7278 | { | |
67c0d1eb RS |
7279 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7280 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7281 | used_at = 1; |
7282 | } | |
67c0d1eb | 7283 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg); |
8fc2e39e | 7284 | break; |
252b5132 RH |
7285 | |
7286 | case M_DSUB_I: | |
7287 | dbl = 1; | |
7288 | case M_SUB_I: | |
7289 | if (imm_expr.X_op == O_constant | |
7290 | && imm_expr.X_add_number > -0x8000 | |
7291 | && imm_expr.X_add_number <= 0x8000) | |
7292 | { | |
7293 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb RS |
7294 | macro_build (&imm_expr, dbl ? "daddi" : "addi", "t,r,j", |
7295 | dreg, sreg, BFD_RELOC_LO16); | |
8fc2e39e | 7296 | break; |
252b5132 | 7297 | } |
8fc2e39e | 7298 | used_at = 1; |
67c0d1eb RS |
7299 | load_register (AT, &imm_expr, dbl); |
7300 | macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7301 | break; |
7302 | ||
7303 | case M_DSUBU_I: | |
7304 | dbl = 1; | |
7305 | case M_SUBU_I: | |
7306 | if (imm_expr.X_op == O_constant | |
7307 | && imm_expr.X_add_number > -0x8000 | |
7308 | && imm_expr.X_add_number <= 0x8000) | |
7309 | { | |
7310 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb RS |
7311 | macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "t,r,j", |
7312 | dreg, sreg, BFD_RELOC_LO16); | |
8fc2e39e | 7313 | break; |
252b5132 | 7314 | } |
8fc2e39e | 7315 | used_at = 1; |
67c0d1eb RS |
7316 | load_register (AT, &imm_expr, dbl); |
7317 | macro_build (NULL, dbl ? "dsubu" : "subu", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7318 | break; |
7319 | ||
7320 | case M_TEQ_I: | |
7321 | s = "teq"; | |
7322 | goto trap; | |
7323 | case M_TGE_I: | |
7324 | s = "tge"; | |
7325 | goto trap; | |
7326 | case M_TGEU_I: | |
7327 | s = "tgeu"; | |
7328 | goto trap; | |
7329 | case M_TLT_I: | |
7330 | s = "tlt"; | |
7331 | goto trap; | |
7332 | case M_TLTU_I: | |
7333 | s = "tltu"; | |
7334 | goto trap; | |
7335 | case M_TNE_I: | |
7336 | s = "tne"; | |
7337 | trap: | |
8fc2e39e | 7338 | used_at = 1; |
67c0d1eb RS |
7339 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7340 | macro_build (NULL, s, "s,t", sreg, AT); | |
252b5132 RH |
7341 | break; |
7342 | ||
252b5132 | 7343 | case M_TRUNCWS: |
43841e91 | 7344 | case M_TRUNCWD: |
e7af610e | 7345 | assert (mips_opts.isa == ISA_MIPS1); |
8fc2e39e | 7346 | used_at = 1; |
252b5132 RH |
7347 | sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */ |
7348 | dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */ | |
7349 | ||
7350 | /* | |
7351 | * Is the double cfc1 instruction a bug in the mips assembler; | |
7352 | * or is there a reason for it? | |
7353 | */ | |
b34976b6 | 7354 | mips_emit_delays (TRUE); |
252b5132 RH |
7355 | ++mips_opts.noreorder; |
7356 | mips_any_noreorder = 1; | |
67c0d1eb RS |
7357 | macro_build (NULL, "cfc1", "t,G", treg, RA); |
7358 | macro_build (NULL, "cfc1", "t,G", treg, RA); | |
7359 | macro_build (NULL, "nop", ""); | |
252b5132 | 7360 | expr1.X_add_number = 3; |
67c0d1eb | 7361 | macro_build (&expr1, "ori", "t,r,i", AT, treg, BFD_RELOC_LO16); |
252b5132 | 7362 | expr1.X_add_number = 2; |
67c0d1eb RS |
7363 | macro_build (&expr1, "xori", "t,r,i", AT, AT, BFD_RELOC_LO16); |
7364 | macro_build (NULL, "ctc1", "t,G", AT, RA); | |
7365 | macro_build (NULL, "nop", ""); | |
7366 | macro_build (NULL, mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S", | |
7367 | dreg, sreg); | |
7368 | macro_build (NULL, "ctc1", "t,G", treg, RA); | |
7369 | macro_build (NULL, "nop", ""); | |
252b5132 RH |
7370 | --mips_opts.noreorder; |
7371 | break; | |
7372 | ||
7373 | case M_ULH: | |
7374 | s = "lb"; | |
7375 | goto ulh; | |
7376 | case M_ULHU: | |
7377 | s = "lbu"; | |
7378 | ulh: | |
8fc2e39e | 7379 | used_at = 1; |
252b5132 RH |
7380 | if (offset_expr.X_add_number >= 0x7fff) |
7381 | as_bad (_("operand overflow")); | |
252b5132 | 7382 | if (! target_big_endian) |
f9419b05 | 7383 | ++offset_expr.X_add_number; |
67c0d1eb | 7384 | macro_build (&offset_expr, s, "t,o(b)", AT, BFD_RELOC_LO16, breg); |
252b5132 | 7385 | if (! target_big_endian) |
f9419b05 | 7386 | --offset_expr.X_add_number; |
252b5132 | 7387 | else |
f9419b05 | 7388 | ++offset_expr.X_add_number; |
67c0d1eb RS |
7389 | macro_build (&offset_expr, "lbu", "t,o(b)", treg, BFD_RELOC_LO16, breg); |
7390 | macro_build (NULL, "sll", "d,w,<", AT, AT, 8); | |
7391 | macro_build (NULL, "or", "d,v,t", treg, treg, AT); | |
252b5132 RH |
7392 | break; |
7393 | ||
7394 | case M_ULD: | |
7395 | s = "ldl"; | |
7396 | s2 = "ldr"; | |
7397 | off = 7; | |
7398 | goto ulw; | |
7399 | case M_ULW: | |
7400 | s = "lwl"; | |
7401 | s2 = "lwr"; | |
7402 | off = 3; | |
7403 | ulw: | |
7404 | if (offset_expr.X_add_number >= 0x8000 - off) | |
7405 | as_bad (_("operand overflow")); | |
af22f5b2 CD |
7406 | if (treg != breg) |
7407 | tempreg = treg; | |
7408 | else | |
8fc2e39e TS |
7409 | { |
7410 | used_at = 1; | |
7411 | tempreg = AT; | |
7412 | } | |
252b5132 RH |
7413 | if (! target_big_endian) |
7414 | offset_expr.X_add_number += off; | |
67c0d1eb | 7415 | macro_build (&offset_expr, s, "t,o(b)", tempreg, BFD_RELOC_LO16, breg); |
252b5132 RH |
7416 | if (! target_big_endian) |
7417 | offset_expr.X_add_number -= off; | |
7418 | else | |
7419 | offset_expr.X_add_number += off; | |
67c0d1eb | 7420 | macro_build (&offset_expr, s2, "t,o(b)", tempreg, BFD_RELOC_LO16, breg); |
af22f5b2 CD |
7421 | |
7422 | /* If necessary, move the result in tempreg the final destination. */ | |
7423 | if (treg == tempreg) | |
8fc2e39e | 7424 | break; |
af22f5b2 | 7425 | /* Protect second load's delay slot. */ |
017315e4 | 7426 | load_delay_nop (); |
67c0d1eb | 7427 | move_register (treg, tempreg); |
af22f5b2 | 7428 | break; |
252b5132 RH |
7429 | |
7430 | case M_ULD_A: | |
7431 | s = "ldl"; | |
7432 | s2 = "ldr"; | |
7433 | off = 7; | |
7434 | goto ulwa; | |
7435 | case M_ULW_A: | |
7436 | s = "lwl"; | |
7437 | s2 = "lwr"; | |
7438 | off = 3; | |
7439 | ulwa: | |
d6bc6245 | 7440 | used_at = 1; |
67c0d1eb | 7441 | load_address (AT, &offset_expr, &used_at); |
252b5132 | 7442 | if (breg != 0) |
67c0d1eb | 7443 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); |
252b5132 RH |
7444 | if (! target_big_endian) |
7445 | expr1.X_add_number = off; | |
7446 | else | |
7447 | expr1.X_add_number = 0; | |
67c0d1eb | 7448 | macro_build (&expr1, s, "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
7449 | if (! target_big_endian) |
7450 | expr1.X_add_number = 0; | |
7451 | else | |
7452 | expr1.X_add_number = off; | |
67c0d1eb | 7453 | macro_build (&expr1, s2, "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
7454 | break; |
7455 | ||
7456 | case M_ULH_A: | |
7457 | case M_ULHU_A: | |
d6bc6245 | 7458 | used_at = 1; |
67c0d1eb | 7459 | load_address (AT, &offset_expr, &used_at); |
252b5132 | 7460 | if (breg != 0) |
67c0d1eb | 7461 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); |
252b5132 RH |
7462 | if (target_big_endian) |
7463 | expr1.X_add_number = 0; | |
67c0d1eb | 7464 | macro_build (&expr1, mask == M_ULH_A ? "lb" : "lbu", "t,o(b)", |
17a2f251 | 7465 | treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
7466 | if (target_big_endian) |
7467 | expr1.X_add_number = 1; | |
7468 | else | |
7469 | expr1.X_add_number = 0; | |
67c0d1eb RS |
7470 | macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT); |
7471 | macro_build (NULL, "sll", "d,w,<", treg, treg, 8); | |
7472 | macro_build (NULL, "or", "d,v,t", treg, treg, AT); | |
252b5132 RH |
7473 | break; |
7474 | ||
7475 | case M_USH: | |
8fc2e39e | 7476 | used_at = 1; |
252b5132 RH |
7477 | if (offset_expr.X_add_number >= 0x7fff) |
7478 | as_bad (_("operand overflow")); | |
7479 | if (target_big_endian) | |
f9419b05 | 7480 | ++offset_expr.X_add_number; |
67c0d1eb RS |
7481 | macro_build (&offset_expr, "sb", "t,o(b)", treg, BFD_RELOC_LO16, breg); |
7482 | macro_build (NULL, "srl", "d,w,<", AT, treg, 8); | |
252b5132 | 7483 | if (target_big_endian) |
f9419b05 | 7484 | --offset_expr.X_add_number; |
252b5132 | 7485 | else |
f9419b05 | 7486 | ++offset_expr.X_add_number; |
67c0d1eb | 7487 | macro_build (&offset_expr, "sb", "t,o(b)", AT, BFD_RELOC_LO16, breg); |
252b5132 RH |
7488 | break; |
7489 | ||
7490 | case M_USD: | |
7491 | s = "sdl"; | |
7492 | s2 = "sdr"; | |
7493 | off = 7; | |
7494 | goto usw; | |
7495 | case M_USW: | |
7496 | s = "swl"; | |
7497 | s2 = "swr"; | |
7498 | off = 3; | |
7499 | usw: | |
7500 | if (offset_expr.X_add_number >= 0x8000 - off) | |
7501 | as_bad (_("operand overflow")); | |
7502 | if (! target_big_endian) | |
7503 | offset_expr.X_add_number += off; | |
67c0d1eb | 7504 | macro_build (&offset_expr, s, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
252b5132 RH |
7505 | if (! target_big_endian) |
7506 | offset_expr.X_add_number -= off; | |
7507 | else | |
7508 | offset_expr.X_add_number += off; | |
67c0d1eb | 7509 | macro_build (&offset_expr, s2, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
8fc2e39e | 7510 | break; |
252b5132 RH |
7511 | |
7512 | case M_USD_A: | |
7513 | s = "sdl"; | |
7514 | s2 = "sdr"; | |
7515 | off = 7; | |
7516 | goto uswa; | |
7517 | case M_USW_A: | |
7518 | s = "swl"; | |
7519 | s2 = "swr"; | |
7520 | off = 3; | |
7521 | uswa: | |
d6bc6245 | 7522 | used_at = 1; |
67c0d1eb | 7523 | load_address (AT, &offset_expr, &used_at); |
252b5132 | 7524 | if (breg != 0) |
67c0d1eb | 7525 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); |
252b5132 RH |
7526 | if (! target_big_endian) |
7527 | expr1.X_add_number = off; | |
7528 | else | |
7529 | expr1.X_add_number = 0; | |
67c0d1eb | 7530 | macro_build (&expr1, s, "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
7531 | if (! target_big_endian) |
7532 | expr1.X_add_number = 0; | |
7533 | else | |
7534 | expr1.X_add_number = off; | |
67c0d1eb | 7535 | macro_build (&expr1, s2, "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
7536 | break; |
7537 | ||
7538 | case M_USH_A: | |
d6bc6245 | 7539 | used_at = 1; |
67c0d1eb | 7540 | load_address (AT, &offset_expr, &used_at); |
252b5132 | 7541 | if (breg != 0) |
67c0d1eb | 7542 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); |
252b5132 RH |
7543 | if (! target_big_endian) |
7544 | expr1.X_add_number = 0; | |
67c0d1eb RS |
7545 | macro_build (&expr1, "sb", "t,o(b)", treg, BFD_RELOC_LO16, AT); |
7546 | macro_build (NULL, "srl", "d,w,<", treg, treg, 8); | |
252b5132 RH |
7547 | if (! target_big_endian) |
7548 | expr1.X_add_number = 1; | |
7549 | else | |
7550 | expr1.X_add_number = 0; | |
67c0d1eb | 7551 | macro_build (&expr1, "sb", "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
7552 | if (! target_big_endian) |
7553 | expr1.X_add_number = 0; | |
7554 | else | |
7555 | expr1.X_add_number = 1; | |
67c0d1eb RS |
7556 | macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT); |
7557 | macro_build (NULL, "sll", "d,w,<", treg, treg, 8); | |
7558 | macro_build (NULL, "or", "d,v,t", treg, treg, AT); | |
252b5132 RH |
7559 | break; |
7560 | ||
7561 | default: | |
7562 | /* FIXME: Check if this is one of the itbl macros, since they | |
bdaaa2e1 | 7563 | are added dynamically. */ |
252b5132 RH |
7564 | as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name); |
7565 | break; | |
7566 | } | |
8fc2e39e TS |
7567 | if (mips_opts.noat && used_at) |
7568 | as_bad (_("Macro used $at after \".set noat\"")); | |
252b5132 RH |
7569 | } |
7570 | ||
7571 | /* Implement macros in mips16 mode. */ | |
7572 | ||
7573 | static void | |
17a2f251 | 7574 | mips16_macro (struct mips_cl_insn *ip) |
252b5132 RH |
7575 | { |
7576 | int mask; | |
7577 | int xreg, yreg, zreg, tmp; | |
252b5132 RH |
7578 | expressionS expr1; |
7579 | int dbl; | |
7580 | const char *s, *s2, *s3; | |
7581 | ||
7582 | mask = ip->insn_mo->mask; | |
7583 | ||
7584 | xreg = (ip->insn_opcode >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX; | |
7585 | yreg = (ip->insn_opcode >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY; | |
7586 | zreg = (ip->insn_opcode >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ; | |
7587 | ||
252b5132 RH |
7588 | expr1.X_op = O_constant; |
7589 | expr1.X_op_symbol = NULL; | |
7590 | expr1.X_add_symbol = NULL; | |
7591 | expr1.X_add_number = 1; | |
7592 | ||
7593 | dbl = 0; | |
7594 | ||
7595 | switch (mask) | |
7596 | { | |
7597 | default: | |
7598 | internalError (); | |
7599 | ||
7600 | case M_DDIV_3: | |
7601 | dbl = 1; | |
7602 | case M_DIV_3: | |
7603 | s = "mflo"; | |
7604 | goto do_div3; | |
7605 | case M_DREM_3: | |
7606 | dbl = 1; | |
7607 | case M_REM_3: | |
7608 | s = "mfhi"; | |
7609 | do_div3: | |
b34976b6 | 7610 | mips_emit_delays (TRUE); |
252b5132 RH |
7611 | ++mips_opts.noreorder; |
7612 | mips_any_noreorder = 1; | |
67c0d1eb | 7613 | macro_build (NULL, dbl ? "ddiv" : "div", "0,x,y", xreg, yreg); |
252b5132 | 7614 | expr1.X_add_number = 2; |
67c0d1eb RS |
7615 | macro_build (&expr1, "bnez", "x,p", yreg); |
7616 | macro_build (NULL, "break", "6", 7); | |
bdaaa2e1 | 7617 | |
252b5132 RH |
7618 | /* FIXME: The normal code checks for of -1 / -0x80000000 here, |
7619 | since that causes an overflow. We should do that as well, | |
7620 | but I don't see how to do the comparisons without a temporary | |
7621 | register. */ | |
7622 | --mips_opts.noreorder; | |
67c0d1eb | 7623 | macro_build (NULL, s, "x", zreg); |
252b5132 RH |
7624 | break; |
7625 | ||
7626 | case M_DIVU_3: | |
7627 | s = "divu"; | |
7628 | s2 = "mflo"; | |
7629 | goto do_divu3; | |
7630 | case M_REMU_3: | |
7631 | s = "divu"; | |
7632 | s2 = "mfhi"; | |
7633 | goto do_divu3; | |
7634 | case M_DDIVU_3: | |
7635 | s = "ddivu"; | |
7636 | s2 = "mflo"; | |
7637 | goto do_divu3; | |
7638 | case M_DREMU_3: | |
7639 | s = "ddivu"; | |
7640 | s2 = "mfhi"; | |
7641 | do_divu3: | |
b34976b6 | 7642 | mips_emit_delays (TRUE); |
252b5132 RH |
7643 | ++mips_opts.noreorder; |
7644 | mips_any_noreorder = 1; | |
67c0d1eb | 7645 | macro_build (NULL, s, "0,x,y", xreg, yreg); |
252b5132 | 7646 | expr1.X_add_number = 2; |
67c0d1eb RS |
7647 | macro_build (&expr1, "bnez", "x,p", yreg); |
7648 | macro_build (NULL, "break", "6", 7); | |
252b5132 | 7649 | --mips_opts.noreorder; |
67c0d1eb | 7650 | macro_build (NULL, s2, "x", zreg); |
252b5132 RH |
7651 | break; |
7652 | ||
7653 | case M_DMUL: | |
7654 | dbl = 1; | |
7655 | case M_MUL: | |
67c0d1eb RS |
7656 | macro_build (NULL, dbl ? "dmultu" : "multu", "x,y", xreg, yreg); |
7657 | macro_build (NULL, "mflo", "x", zreg); | |
8fc2e39e | 7658 | break; |
252b5132 RH |
7659 | |
7660 | case M_DSUBU_I: | |
7661 | dbl = 1; | |
7662 | goto do_subu; | |
7663 | case M_SUBU_I: | |
7664 | do_subu: | |
7665 | if (imm_expr.X_op != O_constant) | |
7666 | as_bad (_("Unsupported large constant")); | |
7667 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 7668 | macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "y,x,4", yreg, xreg); |
252b5132 RH |
7669 | break; |
7670 | ||
7671 | case M_SUBU_I_2: | |
7672 | if (imm_expr.X_op != O_constant) | |
7673 | as_bad (_("Unsupported large constant")); | |
7674 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 7675 | macro_build (&imm_expr, "addiu", "x,k", xreg); |
252b5132 RH |
7676 | break; |
7677 | ||
7678 | case M_DSUBU_I_2: | |
7679 | if (imm_expr.X_op != O_constant) | |
7680 | as_bad (_("Unsupported large constant")); | |
7681 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 7682 | macro_build (&imm_expr, "daddiu", "y,j", yreg); |
252b5132 RH |
7683 | break; |
7684 | ||
7685 | case M_BEQ: | |
7686 | s = "cmp"; | |
7687 | s2 = "bteqz"; | |
7688 | goto do_branch; | |
7689 | case M_BNE: | |
7690 | s = "cmp"; | |
7691 | s2 = "btnez"; | |
7692 | goto do_branch; | |
7693 | case M_BLT: | |
7694 | s = "slt"; | |
7695 | s2 = "btnez"; | |
7696 | goto do_branch; | |
7697 | case M_BLTU: | |
7698 | s = "sltu"; | |
7699 | s2 = "btnez"; | |
7700 | goto do_branch; | |
7701 | case M_BLE: | |
7702 | s = "slt"; | |
7703 | s2 = "bteqz"; | |
7704 | goto do_reverse_branch; | |
7705 | case M_BLEU: | |
7706 | s = "sltu"; | |
7707 | s2 = "bteqz"; | |
7708 | goto do_reverse_branch; | |
7709 | case M_BGE: | |
7710 | s = "slt"; | |
7711 | s2 = "bteqz"; | |
7712 | goto do_branch; | |
7713 | case M_BGEU: | |
7714 | s = "sltu"; | |
7715 | s2 = "bteqz"; | |
7716 | goto do_branch; | |
7717 | case M_BGT: | |
7718 | s = "slt"; | |
7719 | s2 = "btnez"; | |
7720 | goto do_reverse_branch; | |
7721 | case M_BGTU: | |
7722 | s = "sltu"; | |
7723 | s2 = "btnez"; | |
7724 | ||
7725 | do_reverse_branch: | |
7726 | tmp = xreg; | |
7727 | xreg = yreg; | |
7728 | yreg = tmp; | |
7729 | ||
7730 | do_branch: | |
67c0d1eb RS |
7731 | macro_build (NULL, s, "x,y", xreg, yreg); |
7732 | macro_build (&offset_expr, s2, "p"); | |
252b5132 RH |
7733 | break; |
7734 | ||
7735 | case M_BEQ_I: | |
7736 | s = "cmpi"; | |
7737 | s2 = "bteqz"; | |
7738 | s3 = "x,U"; | |
7739 | goto do_branch_i; | |
7740 | case M_BNE_I: | |
7741 | s = "cmpi"; | |
7742 | s2 = "btnez"; | |
7743 | s3 = "x,U"; | |
7744 | goto do_branch_i; | |
7745 | case M_BLT_I: | |
7746 | s = "slti"; | |
7747 | s2 = "btnez"; | |
7748 | s3 = "x,8"; | |
7749 | goto do_branch_i; | |
7750 | case M_BLTU_I: | |
7751 | s = "sltiu"; | |
7752 | s2 = "btnez"; | |
7753 | s3 = "x,8"; | |
7754 | goto do_branch_i; | |
7755 | case M_BLE_I: | |
7756 | s = "slti"; | |
7757 | s2 = "btnez"; | |
7758 | s3 = "x,8"; | |
7759 | goto do_addone_branch_i; | |
7760 | case M_BLEU_I: | |
7761 | s = "sltiu"; | |
7762 | s2 = "btnez"; | |
7763 | s3 = "x,8"; | |
7764 | goto do_addone_branch_i; | |
7765 | case M_BGE_I: | |
7766 | s = "slti"; | |
7767 | s2 = "bteqz"; | |
7768 | s3 = "x,8"; | |
7769 | goto do_branch_i; | |
7770 | case M_BGEU_I: | |
7771 | s = "sltiu"; | |
7772 | s2 = "bteqz"; | |
7773 | s3 = "x,8"; | |
7774 | goto do_branch_i; | |
7775 | case M_BGT_I: | |
7776 | s = "slti"; | |
7777 | s2 = "bteqz"; | |
7778 | s3 = "x,8"; | |
7779 | goto do_addone_branch_i; | |
7780 | case M_BGTU_I: | |
7781 | s = "sltiu"; | |
7782 | s2 = "bteqz"; | |
7783 | s3 = "x,8"; | |
7784 | ||
7785 | do_addone_branch_i: | |
7786 | if (imm_expr.X_op != O_constant) | |
7787 | as_bad (_("Unsupported large constant")); | |
7788 | ++imm_expr.X_add_number; | |
7789 | ||
7790 | do_branch_i: | |
67c0d1eb RS |
7791 | macro_build (&imm_expr, s, s3, xreg); |
7792 | macro_build (&offset_expr, s2, "p"); | |
252b5132 RH |
7793 | break; |
7794 | ||
7795 | case M_ABS: | |
7796 | expr1.X_add_number = 0; | |
67c0d1eb | 7797 | macro_build (&expr1, "slti", "x,8", yreg); |
252b5132 | 7798 | if (xreg != yreg) |
67c0d1eb | 7799 | move_register (xreg, yreg); |
252b5132 | 7800 | expr1.X_add_number = 2; |
67c0d1eb RS |
7801 | macro_build (&expr1, "bteqz", "p"); |
7802 | macro_build (NULL, "neg", "x,w", xreg, xreg); | |
252b5132 RH |
7803 | } |
7804 | } | |
7805 | ||
7806 | /* For consistency checking, verify that all bits are specified either | |
7807 | by the match/mask part of the instruction definition, or by the | |
7808 | operand list. */ | |
7809 | static int | |
17a2f251 | 7810 | validate_mips_insn (const struct mips_opcode *opc) |
252b5132 RH |
7811 | { |
7812 | const char *p = opc->args; | |
7813 | char c; | |
7814 | unsigned long used_bits = opc->mask; | |
7815 | ||
7816 | if ((used_bits & opc->match) != opc->match) | |
7817 | { | |
7818 | as_bad (_("internal: bad mips opcode (mask error): %s %s"), | |
7819 | opc->name, opc->args); | |
7820 | return 0; | |
7821 | } | |
7822 | #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift))) | |
7823 | while (*p) | |
7824 | switch (c = *p++) | |
7825 | { | |
7826 | case ',': break; | |
7827 | case '(': break; | |
7828 | case ')': break; | |
af7ee8bf CD |
7829 | case '+': |
7830 | switch (c = *p++) | |
7831 | { | |
7832 | case 'A': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; | |
7833 | case 'B': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break; | |
7834 | case 'C': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
bbcc0807 CD |
7835 | case 'D': USE_BITS (OP_MASK_RD, OP_SH_RD); |
7836 | USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; | |
5f74bc13 CD |
7837 | case 'E': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
7838 | case 'F': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break; | |
7839 | case 'G': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
7840 | case 'H': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
7841 | case 'I': break; | |
af7ee8bf CD |
7842 | default: |
7843 | as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"), | |
7844 | c, opc->name, opc->args); | |
7845 | return 0; | |
7846 | } | |
7847 | break; | |
252b5132 RH |
7848 | case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
7849 | case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; | |
7850 | case 'A': break; | |
4372b673 | 7851 | case 'B': USE_BITS (OP_MASK_CODE20, OP_SH_CODE20); break; |
252b5132 RH |
7852 | case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break; |
7853 | case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break; | |
7854 | case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
7855 | case 'F': break; | |
7856 | case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
156c2f8b | 7857 | case 'H': USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; |
252b5132 | 7858 | case 'I': break; |
e972090a | 7859 | case 'J': USE_BITS (OP_MASK_CODE19, OP_SH_CODE19); break; |
af7ee8bf | 7860 | case 'K': USE_BITS (OP_MASK_RD, OP_SH_RD); break; |
252b5132 RH |
7861 | case 'L': break; |
7862 | case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break; | |
7863 | case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break; | |
deec1734 CD |
7864 | case 'O': USE_BITS (OP_MASK_ALN, OP_SH_ALN); break; |
7865 | case 'Q': USE_BITS (OP_MASK_VSEL, OP_SH_VSEL); | |
7866 | USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
252b5132 RH |
7867 | case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break; |
7868 | case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
7869 | case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
7870 | case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
7871 | case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
deec1734 CD |
7872 | case 'X': USE_BITS (OP_MASK_FD, OP_SH_FD); break; |
7873 | case 'Y': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
7874 | case 'Z': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
252b5132 RH |
7875 | case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break; |
7876 | case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
7877 | case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break; | |
7878 | case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
7879 | case 'f': break; | |
7880 | case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break; | |
7881 | case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; | |
7882 | case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
7883 | case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break; | |
7884 | case 'l': break; | |
7885 | case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
7886 | case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
7887 | case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break; | |
7888 | case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
7889 | case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
7890 | case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
7891 | case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; | |
7892 | case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
7893 | case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
7894 | case 'x': break; | |
7895 | case 'z': break; | |
7896 | case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break; | |
4372b673 NC |
7897 | case 'U': USE_BITS (OP_MASK_RD, OP_SH_RD); |
7898 | USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
60b63b72 RS |
7899 | case 'e': USE_BITS (OP_MASK_VECBYTE, OP_SH_VECBYTE); break; |
7900 | case '%': USE_BITS (OP_MASK_VECALIGN, OP_SH_VECALIGN); break; | |
7901 | case '[': break; | |
7902 | case ']': break; | |
252b5132 RH |
7903 | default: |
7904 | as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"), | |
7905 | c, opc->name, opc->args); | |
7906 | return 0; | |
7907 | } | |
7908 | #undef USE_BITS | |
7909 | if (used_bits != 0xffffffff) | |
7910 | { | |
7911 | as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"), | |
7912 | ~used_bits & 0xffffffff, opc->name, opc->args); | |
7913 | return 0; | |
7914 | } | |
7915 | return 1; | |
7916 | } | |
7917 | ||
7918 | /* This routine assembles an instruction into its binary format. As a | |
7919 | side effect, it sets one of the global variables imm_reloc or | |
7920 | offset_reloc to the type of relocation to do if one of the operands | |
7921 | is an address expression. */ | |
7922 | ||
7923 | static void | |
17a2f251 | 7924 | mips_ip (char *str, struct mips_cl_insn *ip) |
252b5132 RH |
7925 | { |
7926 | char *s; | |
7927 | const char *args; | |
43841e91 | 7928 | char c = 0; |
252b5132 RH |
7929 | struct mips_opcode *insn; |
7930 | char *argsStart; | |
7931 | unsigned int regno; | |
7932 | unsigned int lastregno = 0; | |
af7ee8bf | 7933 | unsigned int lastpos = 0; |
071742cf | 7934 | unsigned int limlo, limhi; |
252b5132 RH |
7935 | char *s_reset; |
7936 | char save_c = 0; | |
252b5132 RH |
7937 | |
7938 | insn_error = NULL; | |
7939 | ||
7940 | /* If the instruction contains a '.', we first try to match an instruction | |
7941 | including the '.'. Then we try again without the '.'. */ | |
7942 | insn = NULL; | |
3882b010 | 7943 | for (s = str; *s != '\0' && !ISSPACE (*s); ++s) |
252b5132 RH |
7944 | continue; |
7945 | ||
7946 | /* If we stopped on whitespace, then replace the whitespace with null for | |
7947 | the call to hash_find. Save the character we replaced just in case we | |
7948 | have to re-parse the instruction. */ | |
3882b010 | 7949 | if (ISSPACE (*s)) |
252b5132 RH |
7950 | { |
7951 | save_c = *s; | |
7952 | *s++ = '\0'; | |
7953 | } | |
bdaaa2e1 | 7954 | |
252b5132 RH |
7955 | insn = (struct mips_opcode *) hash_find (op_hash, str); |
7956 | ||
7957 | /* If we didn't find the instruction in the opcode table, try again, but | |
7958 | this time with just the instruction up to, but not including the | |
7959 | first '.'. */ | |
7960 | if (insn == NULL) | |
7961 | { | |
bdaaa2e1 | 7962 | /* Restore the character we overwrite above (if any). */ |
252b5132 RH |
7963 | if (save_c) |
7964 | *(--s) = save_c; | |
7965 | ||
7966 | /* Scan up to the first '.' or whitespace. */ | |
3882b010 L |
7967 | for (s = str; |
7968 | *s != '\0' && *s != '.' && !ISSPACE (*s); | |
7969 | ++s) | |
252b5132 RH |
7970 | continue; |
7971 | ||
7972 | /* If we did not find a '.', then we can quit now. */ | |
7973 | if (*s != '.') | |
7974 | { | |
7975 | insn_error = "unrecognized opcode"; | |
7976 | return; | |
7977 | } | |
7978 | ||
7979 | /* Lookup the instruction in the hash table. */ | |
7980 | *s++ = '\0'; | |
7981 | if ((insn = (struct mips_opcode *) hash_find (op_hash, str)) == NULL) | |
7982 | { | |
7983 | insn_error = "unrecognized opcode"; | |
7984 | return; | |
7985 | } | |
252b5132 RH |
7986 | } |
7987 | ||
7988 | argsStart = s; | |
7989 | for (;;) | |
7990 | { | |
b34976b6 | 7991 | bfd_boolean ok; |
252b5132 RH |
7992 | |
7993 | assert (strcmp (insn->name, str) == 0); | |
7994 | ||
1f25f5d3 CD |
7995 | if (OPCODE_IS_MEMBER (insn, |
7996 | (mips_opts.isa | |
3396de36 | 7997 | | (file_ase_mips16 ? INSN_MIPS16 : 0) |
deec1734 | 7998 | | (mips_opts.ase_mdmx ? INSN_MDMX : 0) |
98d3f06f | 7999 | | (mips_opts.ase_mips3d ? INSN_MIPS3D : 0)), |
fef14a42 | 8000 | mips_opts.arch)) |
b34976b6 | 8001 | ok = TRUE; |
bdaaa2e1 | 8002 | else |
b34976b6 | 8003 | ok = FALSE; |
bdaaa2e1 | 8004 | |
252b5132 RH |
8005 | if (insn->pinfo != INSN_MACRO) |
8006 | { | |
fef14a42 | 8007 | if (mips_opts.arch == CPU_R4650 && (insn->pinfo & FP_D) != 0) |
b34976b6 | 8008 | ok = FALSE; |
252b5132 RH |
8009 | } |
8010 | ||
8011 | if (! ok) | |
8012 | { | |
8013 | if (insn + 1 < &mips_opcodes[NUMOPCODES] | |
8014 | && strcmp (insn->name, insn[1].name) == 0) | |
8015 | { | |
8016 | ++insn; | |
8017 | continue; | |
8018 | } | |
252b5132 | 8019 | else |
beae10d5 | 8020 | { |
268f6bed L |
8021 | if (!insn_error) |
8022 | { | |
8023 | static char buf[100]; | |
fef14a42 TS |
8024 | sprintf (buf, |
8025 | _("opcode not supported on this processor: %s (%s)"), | |
8026 | mips_cpu_info_from_arch (mips_opts.arch)->name, | |
8027 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
268f6bed L |
8028 | insn_error = buf; |
8029 | } | |
8030 | if (save_c) | |
8031 | *(--s) = save_c; | |
2bd7f1f3 | 8032 | return; |
252b5132 | 8033 | } |
252b5132 RH |
8034 | } |
8035 | ||
8036 | ip->insn_mo = insn; | |
8037 | ip->insn_opcode = insn->match; | |
268f6bed | 8038 | insn_error = NULL; |
252b5132 RH |
8039 | for (args = insn->args;; ++args) |
8040 | { | |
deec1734 CD |
8041 | int is_mdmx; |
8042 | ||
ad8d3bb3 | 8043 | s += strspn (s, " \t"); |
deec1734 | 8044 | is_mdmx = 0; |
252b5132 RH |
8045 | switch (*args) |
8046 | { | |
8047 | case '\0': /* end of args */ | |
8048 | if (*s == '\0') | |
8049 | return; | |
8050 | break; | |
8051 | ||
8052 | case ',': | |
8053 | if (*s++ == *args) | |
8054 | continue; | |
8055 | s--; | |
8056 | switch (*++args) | |
8057 | { | |
8058 | case 'r': | |
8059 | case 'v': | |
38487616 | 8060 | ip->insn_opcode |= lastregno << OP_SH_RS; |
252b5132 RH |
8061 | continue; |
8062 | ||
8063 | case 'w': | |
38487616 TS |
8064 | ip->insn_opcode |= lastregno << OP_SH_RT; |
8065 | continue; | |
8066 | ||
252b5132 | 8067 | case 'W': |
38487616 | 8068 | ip->insn_opcode |= lastregno << OP_SH_FT; |
252b5132 RH |
8069 | continue; |
8070 | ||
8071 | case 'V': | |
38487616 | 8072 | ip->insn_opcode |= lastregno << OP_SH_FS; |
252b5132 RH |
8073 | continue; |
8074 | } | |
8075 | break; | |
8076 | ||
8077 | case '(': | |
8078 | /* Handle optional base register. | |
8079 | Either the base register is omitted or | |
bdaaa2e1 | 8080 | we must have a left paren. */ |
252b5132 RH |
8081 | /* This is dependent on the next operand specifier |
8082 | is a base register specification. */ | |
8083 | assert (args[1] == 'b' || args[1] == '5' | |
8084 | || args[1] == '-' || args[1] == '4'); | |
8085 | if (*s == '\0') | |
8086 | return; | |
8087 | ||
8088 | case ')': /* these must match exactly */ | |
60b63b72 RS |
8089 | case '[': |
8090 | case ']': | |
252b5132 RH |
8091 | if (*s++ == *args) |
8092 | continue; | |
8093 | break; | |
8094 | ||
af7ee8bf CD |
8095 | case '+': /* Opcode extension character. */ |
8096 | switch (*++args) | |
8097 | { | |
071742cf CD |
8098 | case 'A': /* ins/ext position, becomes LSB. */ |
8099 | limlo = 0; | |
8100 | limhi = 31; | |
5f74bc13 CD |
8101 | goto do_lsb; |
8102 | case 'E': | |
8103 | limlo = 32; | |
8104 | limhi = 63; | |
8105 | goto do_lsb; | |
8106 | do_lsb: | |
071742cf CD |
8107 | my_getExpression (&imm_expr, s); |
8108 | check_absolute_expr (ip, &imm_expr); | |
8109 | if ((unsigned long) imm_expr.X_add_number < limlo | |
8110 | || (unsigned long) imm_expr.X_add_number > limhi) | |
8111 | { | |
8112 | as_bad (_("Improper position (%lu)"), | |
8113 | (unsigned long) imm_expr.X_add_number); | |
8114 | imm_expr.X_add_number = limlo; | |
8115 | } | |
8116 | lastpos = imm_expr.X_add_number; | |
8117 | ip->insn_opcode |= (imm_expr.X_add_number | |
8118 | & OP_MASK_SHAMT) << OP_SH_SHAMT; | |
8119 | imm_expr.X_op = O_absent; | |
8120 | s = expr_end; | |
8121 | continue; | |
8122 | ||
8123 | case 'B': /* ins size, becomes MSB. */ | |
8124 | limlo = 1; | |
8125 | limhi = 32; | |
5f74bc13 CD |
8126 | goto do_msb; |
8127 | case 'F': | |
8128 | limlo = 33; | |
8129 | limhi = 64; | |
8130 | goto do_msb; | |
8131 | do_msb: | |
071742cf CD |
8132 | my_getExpression (&imm_expr, s); |
8133 | check_absolute_expr (ip, &imm_expr); | |
8134 | /* Check for negative input so that small negative numbers | |
8135 | will not succeed incorrectly. The checks against | |
8136 | (pos+size) transitively check "size" itself, | |
8137 | assuming that "pos" is reasonable. */ | |
8138 | if ((long) imm_expr.X_add_number < 0 | |
8139 | || ((unsigned long) imm_expr.X_add_number | |
8140 | + lastpos) < limlo | |
8141 | || ((unsigned long) imm_expr.X_add_number | |
8142 | + lastpos) > limhi) | |
8143 | { | |
8144 | as_bad (_("Improper insert size (%lu, position %lu)"), | |
8145 | (unsigned long) imm_expr.X_add_number, | |
8146 | (unsigned long) lastpos); | |
8147 | imm_expr.X_add_number = limlo - lastpos; | |
8148 | } | |
8149 | ip->insn_opcode |= ((lastpos + imm_expr.X_add_number - 1) | |
8150 | & OP_MASK_INSMSB) << OP_SH_INSMSB; | |
8151 | imm_expr.X_op = O_absent; | |
8152 | s = expr_end; | |
8153 | continue; | |
8154 | ||
8155 | case 'C': /* ext size, becomes MSBD. */ | |
8156 | limlo = 1; | |
8157 | limhi = 32; | |
5f74bc13 CD |
8158 | goto do_msbd; |
8159 | case 'G': | |
8160 | limlo = 33; | |
8161 | limhi = 64; | |
8162 | goto do_msbd; | |
8163 | case 'H': | |
8164 | limlo = 33; | |
8165 | limhi = 64; | |
8166 | goto do_msbd; | |
8167 | do_msbd: | |
071742cf CD |
8168 | my_getExpression (&imm_expr, s); |
8169 | check_absolute_expr (ip, &imm_expr); | |
8170 | /* Check for negative input so that small negative numbers | |
8171 | will not succeed incorrectly. The checks against | |
8172 | (pos+size) transitively check "size" itself, | |
8173 | assuming that "pos" is reasonable. */ | |
8174 | if ((long) imm_expr.X_add_number < 0 | |
8175 | || ((unsigned long) imm_expr.X_add_number | |
8176 | + lastpos) < limlo | |
8177 | || ((unsigned long) imm_expr.X_add_number | |
8178 | + lastpos) > limhi) | |
8179 | { | |
8180 | as_bad (_("Improper extract size (%lu, position %lu)"), | |
8181 | (unsigned long) imm_expr.X_add_number, | |
8182 | (unsigned long) lastpos); | |
8183 | imm_expr.X_add_number = limlo - lastpos; | |
8184 | } | |
8185 | ip->insn_opcode |= ((imm_expr.X_add_number - 1) | |
8186 | & OP_MASK_EXTMSBD) << OP_SH_EXTMSBD; | |
8187 | imm_expr.X_op = O_absent; | |
8188 | s = expr_end; | |
8189 | continue; | |
af7ee8bf | 8190 | |
bbcc0807 CD |
8191 | case 'D': |
8192 | /* +D is for disassembly only; never match. */ | |
8193 | break; | |
8194 | ||
5f74bc13 CD |
8195 | case 'I': |
8196 | /* "+I" is like "I", except that imm2_expr is used. */ | |
8197 | my_getExpression (&imm2_expr, s); | |
8198 | if (imm2_expr.X_op != O_big | |
8199 | && imm2_expr.X_op != O_constant) | |
8200 | insn_error = _("absolute expression required"); | |
13757d0c | 8201 | normalize_constant_expr (&imm2_expr); |
5f74bc13 CD |
8202 | s = expr_end; |
8203 | continue; | |
8204 | ||
af7ee8bf CD |
8205 | default: |
8206 | as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"), | |
8207 | *args, insn->name, insn->args); | |
8208 | /* Further processing is fruitless. */ | |
8209 | return; | |
8210 | } | |
8211 | break; | |
8212 | ||
252b5132 RH |
8213 | case '<': /* must be at least one digit */ |
8214 | /* | |
8215 | * According to the manual, if the shift amount is greater | |
b6ff326e KH |
8216 | * than 31 or less than 0, then the shift amount should be |
8217 | * mod 32. In reality the mips assembler issues an error. | |
252b5132 RH |
8218 | * We issue a warning and mask out all but the low 5 bits. |
8219 | */ | |
8220 | my_getExpression (&imm_expr, s); | |
8221 | check_absolute_expr (ip, &imm_expr); | |
8222 | if ((unsigned long) imm_expr.X_add_number > 31) | |
8223 | { | |
793b27f4 TS |
8224 | as_warn (_("Improper shift amount (%lu)"), |
8225 | (unsigned long) imm_expr.X_add_number); | |
38487616 | 8226 | imm_expr.X_add_number &= OP_MASK_SHAMT; |
252b5132 | 8227 | } |
38487616 | 8228 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_SHAMT; |
252b5132 RH |
8229 | imm_expr.X_op = O_absent; |
8230 | s = expr_end; | |
8231 | continue; | |
8232 | ||
8233 | case '>': /* shift amount minus 32 */ | |
8234 | my_getExpression (&imm_expr, s); | |
8235 | check_absolute_expr (ip, &imm_expr); | |
8236 | if ((unsigned long) imm_expr.X_add_number < 32 | |
8237 | || (unsigned long) imm_expr.X_add_number > 63) | |
8238 | break; | |
38487616 | 8239 | ip->insn_opcode |= (imm_expr.X_add_number - 32) << OP_SH_SHAMT; |
252b5132 RH |
8240 | imm_expr.X_op = O_absent; |
8241 | s = expr_end; | |
8242 | continue; | |
8243 | ||
252b5132 RH |
8244 | case 'k': /* cache code */ |
8245 | case 'h': /* prefx code */ | |
8246 | my_getExpression (&imm_expr, s); | |
8247 | check_absolute_expr (ip, &imm_expr); | |
8248 | if ((unsigned long) imm_expr.X_add_number > 31) | |
8249 | { | |
8250 | as_warn (_("Invalid value for `%s' (%lu)"), | |
8251 | ip->insn_mo->name, | |
8252 | (unsigned long) imm_expr.X_add_number); | |
8253 | imm_expr.X_add_number &= 0x1f; | |
8254 | } | |
8255 | if (*args == 'k') | |
8256 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CACHE; | |
8257 | else | |
8258 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_PREFX; | |
8259 | imm_expr.X_op = O_absent; | |
8260 | s = expr_end; | |
8261 | continue; | |
8262 | ||
8263 | case 'c': /* break code */ | |
8264 | my_getExpression (&imm_expr, s); | |
8265 | check_absolute_expr (ip, &imm_expr); | |
793b27f4 | 8266 | if ((unsigned long) imm_expr.X_add_number > 1023) |
252b5132 | 8267 | { |
793b27f4 TS |
8268 | as_warn (_("Illegal break code (%lu)"), |
8269 | (unsigned long) imm_expr.X_add_number); | |
38487616 | 8270 | imm_expr.X_add_number &= OP_MASK_CODE; |
252b5132 | 8271 | } |
38487616 | 8272 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE; |
252b5132 RH |
8273 | imm_expr.X_op = O_absent; |
8274 | s = expr_end; | |
8275 | continue; | |
8276 | ||
8277 | case 'q': /* lower break code */ | |
8278 | my_getExpression (&imm_expr, s); | |
8279 | check_absolute_expr (ip, &imm_expr); | |
793b27f4 | 8280 | if ((unsigned long) imm_expr.X_add_number > 1023) |
252b5132 | 8281 | { |
793b27f4 TS |
8282 | as_warn (_("Illegal lower break code (%lu)"), |
8283 | (unsigned long) imm_expr.X_add_number); | |
38487616 | 8284 | imm_expr.X_add_number &= OP_MASK_CODE2; |
252b5132 | 8285 | } |
38487616 | 8286 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE2; |
252b5132 RH |
8287 | imm_expr.X_op = O_absent; |
8288 | s = expr_end; | |
8289 | continue; | |
8290 | ||
4372b673 | 8291 | case 'B': /* 20-bit syscall/break code. */ |
156c2f8b | 8292 | my_getExpression (&imm_expr, s); |
156c2f8b | 8293 | check_absolute_expr (ip, &imm_expr); |
793b27f4 TS |
8294 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE20) |
8295 | as_warn (_("Illegal 20-bit code (%lu)"), | |
8296 | (unsigned long) imm_expr.X_add_number); | |
38487616 | 8297 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE20; |
252b5132 RH |
8298 | imm_expr.X_op = O_absent; |
8299 | s = expr_end; | |
8300 | continue; | |
8301 | ||
98d3f06f | 8302 | case 'C': /* Coprocessor code */ |
beae10d5 | 8303 | my_getExpression (&imm_expr, s); |
252b5132 | 8304 | check_absolute_expr (ip, &imm_expr); |
98d3f06f | 8305 | if ((unsigned long) imm_expr.X_add_number >= (1 << 25)) |
252b5132 | 8306 | { |
793b27f4 TS |
8307 | as_warn (_("Coproccesor code > 25 bits (%lu)"), |
8308 | (unsigned long) imm_expr.X_add_number); | |
98d3f06f | 8309 | imm_expr.X_add_number &= ((1 << 25) - 1); |
252b5132 | 8310 | } |
beae10d5 KH |
8311 | ip->insn_opcode |= imm_expr.X_add_number; |
8312 | imm_expr.X_op = O_absent; | |
8313 | s = expr_end; | |
8314 | continue; | |
252b5132 | 8315 | |
4372b673 NC |
8316 | case 'J': /* 19-bit wait code. */ |
8317 | my_getExpression (&imm_expr, s); | |
8318 | check_absolute_expr (ip, &imm_expr); | |
793b27f4 TS |
8319 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE19) |
8320 | as_warn (_("Illegal 19-bit code (%lu)"), | |
8321 | (unsigned long) imm_expr.X_add_number); | |
38487616 | 8322 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE19; |
4372b673 NC |
8323 | imm_expr.X_op = O_absent; |
8324 | s = expr_end; | |
8325 | continue; | |
8326 | ||
252b5132 | 8327 | case 'P': /* Performance register */ |
beae10d5 | 8328 | my_getExpression (&imm_expr, s); |
252b5132 | 8329 | check_absolute_expr (ip, &imm_expr); |
beae10d5 | 8330 | if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1) |
252b5132 | 8331 | { |
793b27f4 TS |
8332 | as_warn (_("Invalid performance register (%lu)"), |
8333 | (unsigned long) imm_expr.X_add_number); | |
38487616 | 8334 | imm_expr.X_add_number &= OP_MASK_PERFREG; |
252b5132 | 8335 | } |
38487616 | 8336 | ip->insn_opcode |= (imm_expr.X_add_number << OP_SH_PERFREG); |
beae10d5 KH |
8337 | imm_expr.X_op = O_absent; |
8338 | s = expr_end; | |
8339 | continue; | |
252b5132 RH |
8340 | |
8341 | case 'b': /* base register */ | |
8342 | case 'd': /* destination register */ | |
8343 | case 's': /* source register */ | |
8344 | case 't': /* target register */ | |
8345 | case 'r': /* both target and source */ | |
8346 | case 'v': /* both dest and source */ | |
8347 | case 'w': /* both dest and target */ | |
8348 | case 'E': /* coprocessor target register */ | |
8349 | case 'G': /* coprocessor destination register */ | |
af7ee8bf | 8350 | case 'K': /* 'rdhwr' destination register */ |
252b5132 RH |
8351 | case 'x': /* ignore register name */ |
8352 | case 'z': /* must be zero register */ | |
4372b673 | 8353 | case 'U': /* destination register (clo/clz). */ |
252b5132 RH |
8354 | s_reset = s; |
8355 | if (s[0] == '$') | |
8356 | { | |
8357 | ||
3882b010 | 8358 | if (ISDIGIT (s[1])) |
252b5132 RH |
8359 | { |
8360 | ++s; | |
8361 | regno = 0; | |
8362 | do | |
8363 | { | |
8364 | regno *= 10; | |
8365 | regno += *s - '0'; | |
8366 | ++s; | |
8367 | } | |
3882b010 | 8368 | while (ISDIGIT (*s)); |
252b5132 RH |
8369 | if (regno > 31) |
8370 | as_bad (_("Invalid register number (%d)"), regno); | |
8371 | } | |
af7ee8bf | 8372 | else if (*args == 'E' || *args == 'G' || *args == 'K') |
252b5132 RH |
8373 | goto notreg; |
8374 | else | |
8375 | { | |
76db943d TS |
8376 | if (s[1] == 'r' && s[2] == 'a') |
8377 | { | |
8378 | s += 3; | |
8379 | regno = RA; | |
8380 | } | |
8381 | else if (s[1] == 'f' && s[2] == 'p') | |
252b5132 RH |
8382 | { |
8383 | s += 3; | |
8384 | regno = FP; | |
8385 | } | |
8386 | else if (s[1] == 's' && s[2] == 'p') | |
8387 | { | |
8388 | s += 3; | |
8389 | regno = SP; | |
8390 | } | |
8391 | else if (s[1] == 'g' && s[2] == 'p') | |
8392 | { | |
8393 | s += 3; | |
8394 | regno = GP; | |
8395 | } | |
8396 | else if (s[1] == 'a' && s[2] == 't') | |
8397 | { | |
8398 | s += 3; | |
8399 | regno = AT; | |
8400 | } | |
8401 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '0') | |
8402 | { | |
8403 | s += 4; | |
8404 | regno = KT0; | |
8405 | } | |
8406 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '1') | |
8407 | { | |
8408 | s += 4; | |
8409 | regno = KT1; | |
8410 | } | |
85b51719 TS |
8411 | else if (s[1] == 'z' && s[2] == 'e' && s[3] == 'r' && s[4] == 'o') |
8412 | { | |
8413 | s += 5; | |
8414 | regno = ZERO; | |
8415 | } | |
252b5132 RH |
8416 | else if (itbl_have_entries) |
8417 | { | |
8418 | char *p, *n; | |
d7ba4a77 | 8419 | unsigned long r; |
252b5132 | 8420 | |
d7ba4a77 | 8421 | p = s + 1; /* advance past '$' */ |
252b5132 RH |
8422 | n = itbl_get_field (&p); /* n is name */ |
8423 | ||
d7ba4a77 ILT |
8424 | /* See if this is a register defined in an |
8425 | itbl entry. */ | |
8426 | if (itbl_get_reg_val (n, &r)) | |
252b5132 RH |
8427 | { |
8428 | /* Get_field advances to the start of | |
8429 | the next field, so we need to back | |
d7ba4a77 | 8430 | rack to the end of the last field. */ |
bdaaa2e1 | 8431 | if (p) |
252b5132 | 8432 | s = p - 1; |
bdaaa2e1 | 8433 | else |
d7ba4a77 | 8434 | s = strchr (s, '\0'); |
252b5132 RH |
8435 | regno = r; |
8436 | } | |
8437 | else | |
8438 | goto notreg; | |
beae10d5 | 8439 | } |
252b5132 RH |
8440 | else |
8441 | goto notreg; | |
8442 | } | |
8443 | if (regno == AT | |
8444 | && ! mips_opts.noat | |
8445 | && *args != 'E' | |
af7ee8bf CD |
8446 | && *args != 'G' |
8447 | && *args != 'K') | |
252b5132 RH |
8448 | as_warn (_("Used $at without \".set noat\"")); |
8449 | c = *args; | |
8450 | if (*s == ' ') | |
f9419b05 | 8451 | ++s; |
252b5132 RH |
8452 | if (args[1] != *s) |
8453 | { | |
8454 | if (c == 'r' || c == 'v' || c == 'w') | |
8455 | { | |
8456 | regno = lastregno; | |
8457 | s = s_reset; | |
f9419b05 | 8458 | ++args; |
252b5132 RH |
8459 | } |
8460 | } | |
8461 | /* 'z' only matches $0. */ | |
8462 | if (c == 'z' && regno != 0) | |
8463 | break; | |
8464 | ||
bdaaa2e1 KH |
8465 | /* Now that we have assembled one operand, we use the args string |
8466 | * to figure out where it goes in the instruction. */ | |
252b5132 RH |
8467 | switch (c) |
8468 | { | |
8469 | case 'r': | |
8470 | case 's': | |
8471 | case 'v': | |
8472 | case 'b': | |
38487616 | 8473 | ip->insn_opcode |= regno << OP_SH_RS; |
252b5132 RH |
8474 | break; |
8475 | case 'd': | |
8476 | case 'G': | |
af7ee8bf | 8477 | case 'K': |
38487616 | 8478 | ip->insn_opcode |= regno << OP_SH_RD; |
252b5132 | 8479 | break; |
4372b673 | 8480 | case 'U': |
38487616 TS |
8481 | ip->insn_opcode |= regno << OP_SH_RD; |
8482 | ip->insn_opcode |= regno << OP_SH_RT; | |
4372b673 | 8483 | break; |
252b5132 RH |
8484 | case 'w': |
8485 | case 't': | |
8486 | case 'E': | |
38487616 | 8487 | ip->insn_opcode |= regno << OP_SH_RT; |
252b5132 RH |
8488 | break; |
8489 | case 'x': | |
8490 | /* This case exists because on the r3000 trunc | |
8491 | expands into a macro which requires a gp | |
8492 | register. On the r6000 or r4000 it is | |
8493 | assembled into a single instruction which | |
8494 | ignores the register. Thus the insn version | |
8495 | is MIPS_ISA2 and uses 'x', and the macro | |
8496 | version is MIPS_ISA1 and uses 't'. */ | |
8497 | break; | |
8498 | case 'z': | |
8499 | /* This case is for the div instruction, which | |
8500 | acts differently if the destination argument | |
8501 | is $0. This only matches $0, and is checked | |
8502 | outside the switch. */ | |
8503 | break; | |
8504 | case 'D': | |
8505 | /* Itbl operand; not yet implemented. FIXME ?? */ | |
8506 | break; | |
8507 | /* What about all other operands like 'i', which | |
8508 | can be specified in the opcode table? */ | |
8509 | } | |
8510 | lastregno = regno; | |
8511 | continue; | |
8512 | } | |
8513 | notreg: | |
8514 | switch (*args++) | |
8515 | { | |
8516 | case 'r': | |
8517 | case 'v': | |
38487616 | 8518 | ip->insn_opcode |= lastregno << OP_SH_RS; |
252b5132 RH |
8519 | continue; |
8520 | case 'w': | |
38487616 | 8521 | ip->insn_opcode |= lastregno << OP_SH_RT; |
252b5132 RH |
8522 | continue; |
8523 | } | |
8524 | break; | |
8525 | ||
deec1734 CD |
8526 | case 'O': /* MDMX alignment immediate constant. */ |
8527 | my_getExpression (&imm_expr, s); | |
8528 | check_absolute_expr (ip, &imm_expr); | |
8529 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_ALN) | |
8530 | { | |
8531 | as_warn ("Improper align amount (%ld), using low bits", | |
8532 | (long) imm_expr.X_add_number); | |
8533 | imm_expr.X_add_number &= OP_MASK_ALN; | |
8534 | } | |
8535 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_ALN; | |
8536 | imm_expr.X_op = O_absent; | |
8537 | s = expr_end; | |
8538 | continue; | |
8539 | ||
8540 | case 'Q': /* MDMX vector, element sel, or const. */ | |
8541 | if (s[0] != '$') | |
8542 | { | |
8543 | /* MDMX Immediate. */ | |
8544 | my_getExpression (&imm_expr, s); | |
8545 | check_absolute_expr (ip, &imm_expr); | |
8546 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_FT) | |
8547 | { | |
8548 | as_warn (_("Invalid MDMX Immediate (%ld)"), | |
8549 | (long) imm_expr.X_add_number); | |
8550 | imm_expr.X_add_number &= OP_MASK_FT; | |
8551 | } | |
8552 | imm_expr.X_add_number &= OP_MASK_FT; | |
8553 | if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL)) | |
8554 | ip->insn_opcode |= MDMX_FMTSEL_IMM_QH << OP_SH_VSEL; | |
8555 | else | |
8556 | ip->insn_opcode |= MDMX_FMTSEL_IMM_OB << OP_SH_VSEL; | |
8557 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_FT; | |
8558 | imm_expr.X_op = O_absent; | |
8559 | s = expr_end; | |
8560 | continue; | |
8561 | } | |
8562 | /* Not MDMX Immediate. Fall through. */ | |
8563 | case 'X': /* MDMX destination register. */ | |
8564 | case 'Y': /* MDMX source register. */ | |
8565 | case 'Z': /* MDMX target register. */ | |
8566 | is_mdmx = 1; | |
252b5132 RH |
8567 | case 'D': /* floating point destination register */ |
8568 | case 'S': /* floating point source register */ | |
8569 | case 'T': /* floating point target register */ | |
8570 | case 'R': /* floating point source register */ | |
8571 | case 'V': | |
8572 | case 'W': | |
8573 | s_reset = s; | |
deec1734 CD |
8574 | /* Accept $fN for FP and MDMX register numbers, and in |
8575 | addition accept $vN for MDMX register numbers. */ | |
8576 | if ((s[0] == '$' && s[1] == 'f' && ISDIGIT (s[2])) | |
8577 | || (is_mdmx != 0 && s[0] == '$' && s[1] == 'v' | |
8578 | && ISDIGIT (s[2]))) | |
252b5132 RH |
8579 | { |
8580 | s += 2; | |
8581 | regno = 0; | |
8582 | do | |
8583 | { | |
8584 | regno *= 10; | |
8585 | regno += *s - '0'; | |
8586 | ++s; | |
8587 | } | |
3882b010 | 8588 | while (ISDIGIT (*s)); |
252b5132 RH |
8589 | |
8590 | if (regno > 31) | |
8591 | as_bad (_("Invalid float register number (%d)"), regno); | |
8592 | ||
8593 | if ((regno & 1) != 0 | |
ca4e0257 | 8594 | && HAVE_32BIT_FPRS |
252b5132 RH |
8595 | && ! (strcmp (str, "mtc1") == 0 |
8596 | || strcmp (str, "mfc1") == 0 | |
8597 | || strcmp (str, "lwc1") == 0 | |
8598 | || strcmp (str, "swc1") == 0 | |
8599 | || strcmp (str, "l.s") == 0 | |
8600 | || strcmp (str, "s.s") == 0)) | |
8601 | as_warn (_("Float register should be even, was %d"), | |
8602 | regno); | |
8603 | ||
8604 | c = *args; | |
8605 | if (*s == ' ') | |
f9419b05 | 8606 | ++s; |
252b5132 RH |
8607 | if (args[1] != *s) |
8608 | { | |
8609 | if (c == 'V' || c == 'W') | |
8610 | { | |
8611 | regno = lastregno; | |
8612 | s = s_reset; | |
f9419b05 | 8613 | ++args; |
252b5132 RH |
8614 | } |
8615 | } | |
8616 | switch (c) | |
8617 | { | |
8618 | case 'D': | |
deec1734 | 8619 | case 'X': |
38487616 | 8620 | ip->insn_opcode |= regno << OP_SH_FD; |
252b5132 RH |
8621 | break; |
8622 | case 'V': | |
8623 | case 'S': | |
deec1734 | 8624 | case 'Y': |
38487616 | 8625 | ip->insn_opcode |= regno << OP_SH_FS; |
252b5132 | 8626 | break; |
deec1734 CD |
8627 | case 'Q': |
8628 | /* This is like 'Z', but also needs to fix the MDMX | |
8629 | vector/scalar select bits. Note that the | |
8630 | scalar immediate case is handled above. */ | |
8631 | if (*s == '[') | |
8632 | { | |
8633 | int is_qh = (ip->insn_opcode & (1 << OP_SH_VSEL)); | |
8634 | int max_el = (is_qh ? 3 : 7); | |
8635 | s++; | |
8636 | my_getExpression(&imm_expr, s); | |
8637 | check_absolute_expr (ip, &imm_expr); | |
8638 | s = expr_end; | |
8639 | if (imm_expr.X_add_number > max_el) | |
8640 | as_bad(_("Bad element selector %ld"), | |
8641 | (long) imm_expr.X_add_number); | |
8642 | imm_expr.X_add_number &= max_el; | |
8643 | ip->insn_opcode |= (imm_expr.X_add_number | |
8644 | << (OP_SH_VSEL + | |
8645 | (is_qh ? 2 : 1))); | |
01a3f561 | 8646 | imm_expr.X_op = O_absent; |
deec1734 CD |
8647 | if (*s != ']') |
8648 | as_warn(_("Expecting ']' found '%s'"), s); | |
8649 | else | |
8650 | s++; | |
8651 | } | |
8652 | else | |
8653 | { | |
8654 | if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL)) | |
8655 | ip->insn_opcode |= (MDMX_FMTSEL_VEC_QH | |
8656 | << OP_SH_VSEL); | |
8657 | else | |
8658 | ip->insn_opcode |= (MDMX_FMTSEL_VEC_OB << | |
8659 | OP_SH_VSEL); | |
8660 | } | |
8661 | /* Fall through */ | |
252b5132 RH |
8662 | case 'W': |
8663 | case 'T': | |
deec1734 | 8664 | case 'Z': |
38487616 | 8665 | ip->insn_opcode |= regno << OP_SH_FT; |
252b5132 RH |
8666 | break; |
8667 | case 'R': | |
38487616 | 8668 | ip->insn_opcode |= regno << OP_SH_FR; |
252b5132 RH |
8669 | break; |
8670 | } | |
8671 | lastregno = regno; | |
8672 | continue; | |
8673 | } | |
8674 | ||
252b5132 RH |
8675 | switch (*args++) |
8676 | { | |
8677 | case 'V': | |
38487616 | 8678 | ip->insn_opcode |= lastregno << OP_SH_FS; |
252b5132 RH |
8679 | continue; |
8680 | case 'W': | |
38487616 | 8681 | ip->insn_opcode |= lastregno << OP_SH_FT; |
252b5132 RH |
8682 | continue; |
8683 | } | |
8684 | break; | |
8685 | ||
8686 | case 'I': | |
8687 | my_getExpression (&imm_expr, s); | |
8688 | if (imm_expr.X_op != O_big | |
8689 | && imm_expr.X_op != O_constant) | |
8690 | insn_error = _("absolute expression required"); | |
13757d0c | 8691 | normalize_constant_expr (&imm_expr); |
252b5132 RH |
8692 | s = expr_end; |
8693 | continue; | |
8694 | ||
8695 | case 'A': | |
8696 | my_getExpression (&offset_expr, s); | |
f6688943 | 8697 | *imm_reloc = BFD_RELOC_32; |
252b5132 RH |
8698 | s = expr_end; |
8699 | continue; | |
8700 | ||
8701 | case 'F': | |
8702 | case 'L': | |
8703 | case 'f': | |
8704 | case 'l': | |
8705 | { | |
8706 | int f64; | |
ca4e0257 | 8707 | int using_gprs; |
252b5132 RH |
8708 | char *save_in; |
8709 | char *err; | |
8710 | unsigned char temp[8]; | |
8711 | int len; | |
8712 | unsigned int length; | |
8713 | segT seg; | |
8714 | subsegT subseg; | |
8715 | char *p; | |
8716 | ||
8717 | /* These only appear as the last operand in an | |
8718 | instruction, and every instruction that accepts | |
8719 | them in any variant accepts them in all variants. | |
8720 | This means we don't have to worry about backing out | |
8721 | any changes if the instruction does not match. | |
8722 | ||
8723 | The difference between them is the size of the | |
8724 | floating point constant and where it goes. For 'F' | |
8725 | and 'L' the constant is 64 bits; for 'f' and 'l' it | |
8726 | is 32 bits. Where the constant is placed is based | |
8727 | on how the MIPS assembler does things: | |
8728 | F -- .rdata | |
8729 | L -- .lit8 | |
8730 | f -- immediate value | |
8731 | l -- .lit4 | |
8732 | ||
8733 | The .lit4 and .lit8 sections are only used if | |
8734 | permitted by the -G argument. | |
8735 | ||
ca4e0257 RS |
8736 | The code below needs to know whether the target register |
8737 | is 32 or 64 bits wide. It relies on the fact 'f' and | |
8738 | 'F' are used with GPR-based instructions and 'l' and | |
8739 | 'L' are used with FPR-based instructions. */ | |
252b5132 RH |
8740 | |
8741 | f64 = *args == 'F' || *args == 'L'; | |
ca4e0257 | 8742 | using_gprs = *args == 'F' || *args == 'f'; |
252b5132 RH |
8743 | |
8744 | save_in = input_line_pointer; | |
8745 | input_line_pointer = s; | |
8746 | err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len); | |
8747 | length = len; | |
8748 | s = input_line_pointer; | |
8749 | input_line_pointer = save_in; | |
8750 | if (err != NULL && *err != '\0') | |
8751 | { | |
8752 | as_bad (_("Bad floating point constant: %s"), err); | |
8753 | memset (temp, '\0', sizeof temp); | |
8754 | length = f64 ? 8 : 4; | |
8755 | } | |
8756 | ||
156c2f8b | 8757 | assert (length == (unsigned) (f64 ? 8 : 4)); |
252b5132 RH |
8758 | |
8759 | if (*args == 'f' | |
8760 | || (*args == 'l' | |
3e722fb5 | 8761 | && (g_switch_value < 4 |
252b5132 RH |
8762 | || (temp[0] == 0 && temp[1] == 0) |
8763 | || (temp[2] == 0 && temp[3] == 0)))) | |
8764 | { | |
8765 | imm_expr.X_op = O_constant; | |
8766 | if (! target_big_endian) | |
8767 | imm_expr.X_add_number = bfd_getl32 (temp); | |
8768 | else | |
8769 | imm_expr.X_add_number = bfd_getb32 (temp); | |
8770 | } | |
8771 | else if (length > 4 | |
119d663a | 8772 | && ! mips_disable_float_construction |
ca4e0257 RS |
8773 | /* Constants can only be constructed in GPRs and |
8774 | copied to FPRs if the GPRs are at least as wide | |
8775 | as the FPRs. Force the constant into memory if | |
8776 | we are using 64-bit FPRs but the GPRs are only | |
8777 | 32 bits wide. */ | |
8778 | && (using_gprs | |
8779 | || ! (HAVE_64BIT_FPRS && HAVE_32BIT_GPRS)) | |
252b5132 RH |
8780 | && ((temp[0] == 0 && temp[1] == 0) |
8781 | || (temp[2] == 0 && temp[3] == 0)) | |
8782 | && ((temp[4] == 0 && temp[5] == 0) | |
8783 | || (temp[6] == 0 && temp[7] == 0))) | |
8784 | { | |
ca4e0257 RS |
8785 | /* The value is simple enough to load with a couple of |
8786 | instructions. If using 32-bit registers, set | |
8787 | imm_expr to the high order 32 bits and offset_expr to | |
8788 | the low order 32 bits. Otherwise, set imm_expr to | |
8789 | the entire 64 bit constant. */ | |
8790 | if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS) | |
252b5132 RH |
8791 | { |
8792 | imm_expr.X_op = O_constant; | |
8793 | offset_expr.X_op = O_constant; | |
8794 | if (! target_big_endian) | |
8795 | { | |
8796 | imm_expr.X_add_number = bfd_getl32 (temp + 4); | |
8797 | offset_expr.X_add_number = bfd_getl32 (temp); | |
8798 | } | |
8799 | else | |
8800 | { | |
8801 | imm_expr.X_add_number = bfd_getb32 (temp); | |
8802 | offset_expr.X_add_number = bfd_getb32 (temp + 4); | |
8803 | } | |
8804 | if (offset_expr.X_add_number == 0) | |
8805 | offset_expr.X_op = O_absent; | |
8806 | } | |
8807 | else if (sizeof (imm_expr.X_add_number) > 4) | |
8808 | { | |
8809 | imm_expr.X_op = O_constant; | |
8810 | if (! target_big_endian) | |
8811 | imm_expr.X_add_number = bfd_getl64 (temp); | |
8812 | else | |
8813 | imm_expr.X_add_number = bfd_getb64 (temp); | |
8814 | } | |
8815 | else | |
8816 | { | |
8817 | imm_expr.X_op = O_big; | |
8818 | imm_expr.X_add_number = 4; | |
8819 | if (! target_big_endian) | |
8820 | { | |
8821 | generic_bignum[0] = bfd_getl16 (temp); | |
8822 | generic_bignum[1] = bfd_getl16 (temp + 2); | |
8823 | generic_bignum[2] = bfd_getl16 (temp + 4); | |
8824 | generic_bignum[3] = bfd_getl16 (temp + 6); | |
8825 | } | |
8826 | else | |
8827 | { | |
8828 | generic_bignum[0] = bfd_getb16 (temp + 6); | |
8829 | generic_bignum[1] = bfd_getb16 (temp + 4); | |
8830 | generic_bignum[2] = bfd_getb16 (temp + 2); | |
8831 | generic_bignum[3] = bfd_getb16 (temp); | |
8832 | } | |
8833 | } | |
8834 | } | |
8835 | else | |
8836 | { | |
8837 | const char *newname; | |
8838 | segT new_seg; | |
8839 | ||
8840 | /* Switch to the right section. */ | |
8841 | seg = now_seg; | |
8842 | subseg = now_subseg; | |
8843 | switch (*args) | |
8844 | { | |
8845 | default: /* unused default case avoids warnings. */ | |
8846 | case 'L': | |
8847 | newname = RDATA_SECTION_NAME; | |
3e722fb5 | 8848 | if (g_switch_value >= 8) |
252b5132 RH |
8849 | newname = ".lit8"; |
8850 | break; | |
8851 | case 'F': | |
3e722fb5 | 8852 | newname = RDATA_SECTION_NAME; |
252b5132 RH |
8853 | break; |
8854 | case 'l': | |
4d0d148d | 8855 | assert (g_switch_value >= 4); |
252b5132 RH |
8856 | newname = ".lit4"; |
8857 | break; | |
8858 | } | |
8859 | new_seg = subseg_new (newname, (subsegT) 0); | |
8860 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
8861 | bfd_set_section_flags (stdoutput, new_seg, | |
8862 | (SEC_ALLOC | |
8863 | | SEC_LOAD | |
8864 | | SEC_READONLY | |
8865 | | SEC_DATA)); | |
8866 | frag_align (*args == 'l' ? 2 : 3, 0, 0); | |
8867 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour | |
8868 | && strcmp (TARGET_OS, "elf") != 0) | |
8869 | record_alignment (new_seg, 4); | |
8870 | else | |
8871 | record_alignment (new_seg, *args == 'l' ? 2 : 3); | |
8872 | if (seg == now_seg) | |
8873 | as_bad (_("Can't use floating point insn in this section")); | |
8874 | ||
8875 | /* Set the argument to the current address in the | |
8876 | section. */ | |
8877 | offset_expr.X_op = O_symbol; | |
8878 | offset_expr.X_add_symbol = | |
8879 | symbol_new ("L0\001", now_seg, | |
8880 | (valueT) frag_now_fix (), frag_now); | |
8881 | offset_expr.X_add_number = 0; | |
8882 | ||
8883 | /* Put the floating point number into the section. */ | |
8884 | p = frag_more ((int) length); | |
8885 | memcpy (p, temp, length); | |
8886 | ||
8887 | /* Switch back to the original section. */ | |
8888 | subseg_set (seg, subseg); | |
8889 | } | |
8890 | } | |
8891 | continue; | |
8892 | ||
8893 | case 'i': /* 16 bit unsigned immediate */ | |
8894 | case 'j': /* 16 bit signed immediate */ | |
f6688943 | 8895 | *imm_reloc = BFD_RELOC_LO16; |
5e0116d5 | 8896 | if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0) |
252b5132 RH |
8897 | { |
8898 | int more; | |
5e0116d5 RS |
8899 | offsetT minval, maxval; |
8900 | ||
8901 | more = (insn + 1 < &mips_opcodes[NUMOPCODES] | |
8902 | && strcmp (insn->name, insn[1].name) == 0); | |
8903 | ||
8904 | /* If the expression was written as an unsigned number, | |
8905 | only treat it as signed if there are no more | |
8906 | alternatives. */ | |
8907 | if (more | |
8908 | && *args == 'j' | |
8909 | && sizeof (imm_expr.X_add_number) <= 4 | |
8910 | && imm_expr.X_op == O_constant | |
8911 | && imm_expr.X_add_number < 0 | |
8912 | && imm_expr.X_unsigned | |
8913 | && HAVE_64BIT_GPRS) | |
8914 | break; | |
8915 | ||
8916 | /* For compatibility with older assemblers, we accept | |
8917 | 0x8000-0xffff as signed 16-bit numbers when only | |
8918 | signed numbers are allowed. */ | |
8919 | if (*args == 'i') | |
8920 | minval = 0, maxval = 0xffff; | |
8921 | else if (more) | |
8922 | minval = -0x8000, maxval = 0x7fff; | |
252b5132 | 8923 | else |
5e0116d5 RS |
8924 | minval = -0x8000, maxval = 0xffff; |
8925 | ||
8926 | if (imm_expr.X_op != O_constant | |
8927 | || imm_expr.X_add_number < minval | |
8928 | || imm_expr.X_add_number > maxval) | |
252b5132 RH |
8929 | { |
8930 | if (more) | |
8931 | break; | |
2ae7e77b AH |
8932 | if (imm_expr.X_op == O_constant |
8933 | || imm_expr.X_op == O_big) | |
5e0116d5 | 8934 | as_bad (_("expression out of range")); |
252b5132 RH |
8935 | } |
8936 | } | |
8937 | s = expr_end; | |
8938 | continue; | |
8939 | ||
8940 | case 'o': /* 16 bit offset */ | |
5e0116d5 RS |
8941 | /* Check whether there is only a single bracketed expression |
8942 | left. If so, it must be the base register and the | |
8943 | constant must be zero. */ | |
8944 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
8945 | { | |
8946 | offset_expr.X_op = O_constant; | |
8947 | offset_expr.X_add_number = 0; | |
8948 | continue; | |
8949 | } | |
252b5132 RH |
8950 | |
8951 | /* If this value won't fit into a 16 bit offset, then go | |
8952 | find a macro that will generate the 32 bit offset | |
afdbd6d0 | 8953 | code pattern. */ |
5e0116d5 | 8954 | if (my_getSmallExpression (&offset_expr, offset_reloc, s) == 0 |
252b5132 RH |
8955 | && (offset_expr.X_op != O_constant |
8956 | || offset_expr.X_add_number >= 0x8000 | |
afdbd6d0 | 8957 | || offset_expr.X_add_number < -0x8000)) |
252b5132 RH |
8958 | break; |
8959 | ||
252b5132 RH |
8960 | s = expr_end; |
8961 | continue; | |
8962 | ||
8963 | case 'p': /* pc relative offset */ | |
0b25d3e6 | 8964 | *offset_reloc = BFD_RELOC_16_PCREL_S2; |
252b5132 RH |
8965 | my_getExpression (&offset_expr, s); |
8966 | s = expr_end; | |
8967 | continue; | |
8968 | ||
8969 | case 'u': /* upper 16 bits */ | |
5e0116d5 RS |
8970 | if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0 |
8971 | && imm_expr.X_op == O_constant | |
8972 | && (imm_expr.X_add_number < 0 | |
8973 | || imm_expr.X_add_number >= 0x10000)) | |
252b5132 RH |
8974 | as_bad (_("lui expression not in range 0..65535")); |
8975 | s = expr_end; | |
8976 | continue; | |
8977 | ||
8978 | case 'a': /* 26 bit address */ | |
8979 | my_getExpression (&offset_expr, s); | |
8980 | s = expr_end; | |
f6688943 | 8981 | *offset_reloc = BFD_RELOC_MIPS_JMP; |
252b5132 RH |
8982 | continue; |
8983 | ||
8984 | case 'N': /* 3 bit branch condition code */ | |
8985 | case 'M': /* 3 bit compare condition code */ | |
8986 | if (strncmp (s, "$fcc", 4) != 0) | |
8987 | break; | |
8988 | s += 4; | |
8989 | regno = 0; | |
8990 | do | |
8991 | { | |
8992 | regno *= 10; | |
8993 | regno += *s - '0'; | |
8994 | ++s; | |
8995 | } | |
3882b010 | 8996 | while (ISDIGIT (*s)); |
252b5132 | 8997 | if (regno > 7) |
30c378fd CD |
8998 | as_bad (_("Invalid condition code register $fcc%d"), regno); |
8999 | if ((strcmp(str + strlen(str) - 3, ".ps") == 0 | |
9000 | || strcmp(str + strlen(str) - 5, "any2f") == 0 | |
9001 | || strcmp(str + strlen(str) - 5, "any2t") == 0) | |
9002 | && (regno & 1) != 0) | |
9003 | as_warn(_("Condition code register should be even for %s, was %d"), | |
9004 | str, regno); | |
9005 | if ((strcmp(str + strlen(str) - 5, "any4f") == 0 | |
9006 | || strcmp(str + strlen(str) - 5, "any4t") == 0) | |
9007 | && (regno & 3) != 0) | |
9008 | as_warn(_("Condition code register should be 0 or 4 for %s, was %d"), | |
9009 | str, regno); | |
252b5132 RH |
9010 | if (*args == 'N') |
9011 | ip->insn_opcode |= regno << OP_SH_BCC; | |
9012 | else | |
9013 | ip->insn_opcode |= regno << OP_SH_CCC; | |
beae10d5 | 9014 | continue; |
252b5132 | 9015 | |
156c2f8b NC |
9016 | case 'H': |
9017 | if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X')) | |
9018 | s += 2; | |
3882b010 | 9019 | if (ISDIGIT (*s)) |
156c2f8b NC |
9020 | { |
9021 | c = 0; | |
9022 | do | |
9023 | { | |
9024 | c *= 10; | |
9025 | c += *s - '0'; | |
9026 | ++s; | |
9027 | } | |
3882b010 | 9028 | while (ISDIGIT (*s)); |
156c2f8b NC |
9029 | } |
9030 | else | |
9031 | c = 8; /* Invalid sel value. */ | |
9032 | ||
9033 | if (c > 7) | |
9034 | as_bad (_("invalid coprocessor sub-selection value (0-7)")); | |
9035 | ip->insn_opcode |= c; | |
9036 | continue; | |
9037 | ||
60b63b72 RS |
9038 | case 'e': |
9039 | /* Must be at least one digit. */ | |
9040 | my_getExpression (&imm_expr, s); | |
9041 | check_absolute_expr (ip, &imm_expr); | |
9042 | ||
9043 | if ((unsigned long) imm_expr.X_add_number | |
9044 | > (unsigned long) OP_MASK_VECBYTE) | |
9045 | { | |
9046 | as_bad (_("bad byte vector index (%ld)"), | |
9047 | (long) imm_expr.X_add_number); | |
9048 | imm_expr.X_add_number = 0; | |
9049 | } | |
9050 | ||
9051 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_VECBYTE; | |
9052 | imm_expr.X_op = O_absent; | |
9053 | s = expr_end; | |
9054 | continue; | |
9055 | ||
9056 | case '%': | |
9057 | my_getExpression (&imm_expr, s); | |
9058 | check_absolute_expr (ip, &imm_expr); | |
9059 | ||
9060 | if ((unsigned long) imm_expr.X_add_number | |
9061 | > (unsigned long) OP_MASK_VECALIGN) | |
9062 | { | |
9063 | as_bad (_("bad byte vector index (%ld)"), | |
9064 | (long) imm_expr.X_add_number); | |
9065 | imm_expr.X_add_number = 0; | |
9066 | } | |
9067 | ||
9068 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_VECALIGN; | |
9069 | imm_expr.X_op = O_absent; | |
9070 | s = expr_end; | |
9071 | continue; | |
9072 | ||
252b5132 RH |
9073 | default: |
9074 | as_bad (_("bad char = '%c'\n"), *args); | |
9075 | internalError (); | |
9076 | } | |
9077 | break; | |
9078 | } | |
9079 | /* Args don't match. */ | |
9080 | if (insn + 1 < &mips_opcodes[NUMOPCODES] && | |
9081 | !strcmp (insn->name, insn[1].name)) | |
9082 | { | |
9083 | ++insn; | |
9084 | s = argsStart; | |
268f6bed | 9085 | insn_error = _("illegal operands"); |
252b5132 RH |
9086 | continue; |
9087 | } | |
268f6bed L |
9088 | if (save_c) |
9089 | *(--s) = save_c; | |
252b5132 RH |
9090 | insn_error = _("illegal operands"); |
9091 | return; | |
9092 | } | |
9093 | } | |
9094 | ||
9095 | /* This routine assembles an instruction into its binary format when | |
9096 | assembling for the mips16. As a side effect, it sets one of the | |
9097 | global variables imm_reloc or offset_reloc to the type of | |
9098 | relocation to do if one of the operands is an address expression. | |
9099 | It also sets mips16_small and mips16_ext if the user explicitly | |
9100 | requested a small or extended instruction. */ | |
9101 | ||
9102 | static void | |
17a2f251 | 9103 | mips16_ip (char *str, struct mips_cl_insn *ip) |
252b5132 RH |
9104 | { |
9105 | char *s; | |
9106 | const char *args; | |
9107 | struct mips_opcode *insn; | |
9108 | char *argsstart; | |
9109 | unsigned int regno; | |
9110 | unsigned int lastregno = 0; | |
9111 | char *s_reset; | |
d6f16593 | 9112 | size_t i; |
252b5132 RH |
9113 | |
9114 | insn_error = NULL; | |
9115 | ||
b34976b6 AM |
9116 | mips16_small = FALSE; |
9117 | mips16_ext = FALSE; | |
252b5132 | 9118 | |
3882b010 | 9119 | for (s = str; ISLOWER (*s); ++s) |
252b5132 RH |
9120 | ; |
9121 | switch (*s) | |
9122 | { | |
9123 | case '\0': | |
9124 | break; | |
9125 | ||
9126 | case ' ': | |
9127 | *s++ = '\0'; | |
9128 | break; | |
9129 | ||
9130 | case '.': | |
9131 | if (s[1] == 't' && s[2] == ' ') | |
9132 | { | |
9133 | *s = '\0'; | |
b34976b6 | 9134 | mips16_small = TRUE; |
252b5132 RH |
9135 | s += 3; |
9136 | break; | |
9137 | } | |
9138 | else if (s[1] == 'e' && s[2] == ' ') | |
9139 | { | |
9140 | *s = '\0'; | |
b34976b6 | 9141 | mips16_ext = TRUE; |
252b5132 RH |
9142 | s += 3; |
9143 | break; | |
9144 | } | |
9145 | /* Fall through. */ | |
9146 | default: | |
9147 | insn_error = _("unknown opcode"); | |
9148 | return; | |
9149 | } | |
9150 | ||
9151 | if (mips_opts.noautoextend && ! mips16_ext) | |
b34976b6 | 9152 | mips16_small = TRUE; |
252b5132 RH |
9153 | |
9154 | if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL) | |
9155 | { | |
9156 | insn_error = _("unrecognized opcode"); | |
9157 | return; | |
9158 | } | |
9159 | ||
9160 | argsstart = s; | |
9161 | for (;;) | |
9162 | { | |
9163 | assert (strcmp (insn->name, str) == 0); | |
9164 | ||
9165 | ip->insn_mo = insn; | |
9166 | ip->insn_opcode = insn->match; | |
b34976b6 | 9167 | ip->use_extend = FALSE; |
252b5132 | 9168 | imm_expr.X_op = O_absent; |
f6688943 TS |
9169 | imm_reloc[0] = BFD_RELOC_UNUSED; |
9170 | imm_reloc[1] = BFD_RELOC_UNUSED; | |
9171 | imm_reloc[2] = BFD_RELOC_UNUSED; | |
5f74bc13 | 9172 | imm2_expr.X_op = O_absent; |
252b5132 | 9173 | offset_expr.X_op = O_absent; |
f6688943 TS |
9174 | offset_reloc[0] = BFD_RELOC_UNUSED; |
9175 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
9176 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
9177 | for (args = insn->args; 1; ++args) |
9178 | { | |
9179 | int c; | |
9180 | ||
9181 | if (*s == ' ') | |
9182 | ++s; | |
9183 | ||
9184 | /* In this switch statement we call break if we did not find | |
9185 | a match, continue if we did find a match, or return if we | |
9186 | are done. */ | |
9187 | ||
9188 | c = *args; | |
9189 | switch (c) | |
9190 | { | |
9191 | case '\0': | |
9192 | if (*s == '\0') | |
9193 | { | |
9194 | /* Stuff the immediate value in now, if we can. */ | |
9195 | if (imm_expr.X_op == O_constant | |
f6688943 | 9196 | && *imm_reloc > BFD_RELOC_UNUSED |
252b5132 RH |
9197 | && insn->pinfo != INSN_MACRO) |
9198 | { | |
d6f16593 MR |
9199 | valueT tmp; |
9200 | ||
9201 | switch (*offset_reloc) | |
9202 | { | |
9203 | case BFD_RELOC_MIPS16_HI16_S: | |
9204 | tmp = (imm_expr.X_add_number + 0x8000) >> 16; | |
9205 | break; | |
9206 | ||
9207 | case BFD_RELOC_MIPS16_HI16: | |
9208 | tmp = imm_expr.X_add_number >> 16; | |
9209 | break; | |
9210 | ||
9211 | case BFD_RELOC_MIPS16_LO16: | |
9212 | tmp = ((imm_expr.X_add_number + 0x8000) & 0xffff) | |
9213 | - 0x8000; | |
9214 | break; | |
9215 | ||
9216 | case BFD_RELOC_UNUSED: | |
9217 | tmp = imm_expr.X_add_number; | |
9218 | break; | |
9219 | ||
9220 | default: | |
9221 | internalError (); | |
9222 | } | |
9223 | *offset_reloc = BFD_RELOC_UNUSED; | |
9224 | ||
c4e7957c | 9225 | mips16_immed (NULL, 0, *imm_reloc - BFD_RELOC_UNUSED, |
d6f16593 | 9226 | tmp, TRUE, mips16_small, |
252b5132 RH |
9227 | mips16_ext, &ip->insn_opcode, |
9228 | &ip->use_extend, &ip->extend); | |
9229 | imm_expr.X_op = O_absent; | |
f6688943 | 9230 | *imm_reloc = BFD_RELOC_UNUSED; |
252b5132 RH |
9231 | } |
9232 | ||
9233 | return; | |
9234 | } | |
9235 | break; | |
9236 | ||
9237 | case ',': | |
9238 | if (*s++ == c) | |
9239 | continue; | |
9240 | s--; | |
9241 | switch (*++args) | |
9242 | { | |
9243 | case 'v': | |
9244 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RX; | |
9245 | continue; | |
9246 | case 'w': | |
9247 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RY; | |
9248 | continue; | |
9249 | } | |
9250 | break; | |
9251 | ||
9252 | case '(': | |
9253 | case ')': | |
9254 | if (*s++ == c) | |
9255 | continue; | |
9256 | break; | |
9257 | ||
9258 | case 'v': | |
9259 | case 'w': | |
9260 | if (s[0] != '$') | |
9261 | { | |
9262 | if (c == 'v') | |
9263 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RX; | |
9264 | else | |
9265 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RY; | |
9266 | ++args; | |
9267 | continue; | |
9268 | } | |
9269 | /* Fall through. */ | |
9270 | case 'x': | |
9271 | case 'y': | |
9272 | case 'z': | |
9273 | case 'Z': | |
9274 | case '0': | |
9275 | case 'S': | |
9276 | case 'R': | |
9277 | case 'X': | |
9278 | case 'Y': | |
9279 | if (s[0] != '$') | |
9280 | break; | |
9281 | s_reset = s; | |
3882b010 | 9282 | if (ISDIGIT (s[1])) |
252b5132 RH |
9283 | { |
9284 | ++s; | |
9285 | regno = 0; | |
9286 | do | |
9287 | { | |
9288 | regno *= 10; | |
9289 | regno += *s - '0'; | |
9290 | ++s; | |
9291 | } | |
3882b010 | 9292 | while (ISDIGIT (*s)); |
252b5132 RH |
9293 | if (regno > 31) |
9294 | { | |
9295 | as_bad (_("invalid register number (%d)"), regno); | |
9296 | regno = 2; | |
9297 | } | |
9298 | } | |
9299 | else | |
9300 | { | |
76db943d TS |
9301 | if (s[1] == 'r' && s[2] == 'a') |
9302 | { | |
9303 | s += 3; | |
9304 | regno = RA; | |
9305 | } | |
9306 | else if (s[1] == 'f' && s[2] == 'p') | |
252b5132 RH |
9307 | { |
9308 | s += 3; | |
9309 | regno = FP; | |
9310 | } | |
9311 | else if (s[1] == 's' && s[2] == 'p') | |
9312 | { | |
9313 | s += 3; | |
9314 | regno = SP; | |
9315 | } | |
9316 | else if (s[1] == 'g' && s[2] == 'p') | |
9317 | { | |
9318 | s += 3; | |
9319 | regno = GP; | |
9320 | } | |
9321 | else if (s[1] == 'a' && s[2] == 't') | |
9322 | { | |
9323 | s += 3; | |
9324 | regno = AT; | |
9325 | } | |
9326 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '0') | |
9327 | { | |
9328 | s += 4; | |
9329 | regno = KT0; | |
9330 | } | |
9331 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '1') | |
9332 | { | |
9333 | s += 4; | |
9334 | regno = KT1; | |
9335 | } | |
85b51719 TS |
9336 | else if (s[1] == 'z' && s[2] == 'e' && s[3] == 'r' && s[4] == 'o') |
9337 | { | |
9338 | s += 5; | |
9339 | regno = ZERO; | |
9340 | } | |
252b5132 RH |
9341 | else |
9342 | break; | |
9343 | } | |
9344 | ||
9345 | if (*s == ' ') | |
9346 | ++s; | |
9347 | if (args[1] != *s) | |
9348 | { | |
9349 | if (c == 'v' || c == 'w') | |
9350 | { | |
9351 | regno = mips16_to_32_reg_map[lastregno]; | |
9352 | s = s_reset; | |
f9419b05 | 9353 | ++args; |
252b5132 RH |
9354 | } |
9355 | } | |
9356 | ||
9357 | switch (c) | |
9358 | { | |
9359 | case 'x': | |
9360 | case 'y': | |
9361 | case 'z': | |
9362 | case 'v': | |
9363 | case 'w': | |
9364 | case 'Z': | |
9365 | regno = mips32_to_16_reg_map[regno]; | |
9366 | break; | |
9367 | ||
9368 | case '0': | |
9369 | if (regno != 0) | |
9370 | regno = ILLEGAL_REG; | |
9371 | break; | |
9372 | ||
9373 | case 'S': | |
9374 | if (regno != SP) | |
9375 | regno = ILLEGAL_REG; | |
9376 | break; | |
9377 | ||
9378 | case 'R': | |
9379 | if (regno != RA) | |
9380 | regno = ILLEGAL_REG; | |
9381 | break; | |
9382 | ||
9383 | case 'X': | |
9384 | case 'Y': | |
9385 | if (regno == AT && ! mips_opts.noat) | |
9386 | as_warn (_("used $at without \".set noat\"")); | |
9387 | break; | |
9388 | ||
9389 | default: | |
9390 | internalError (); | |
9391 | } | |
9392 | ||
9393 | if (regno == ILLEGAL_REG) | |
9394 | break; | |
9395 | ||
9396 | switch (c) | |
9397 | { | |
9398 | case 'x': | |
9399 | case 'v': | |
9400 | ip->insn_opcode |= regno << MIPS16OP_SH_RX; | |
9401 | break; | |
9402 | case 'y': | |
9403 | case 'w': | |
9404 | ip->insn_opcode |= regno << MIPS16OP_SH_RY; | |
9405 | break; | |
9406 | case 'z': | |
9407 | ip->insn_opcode |= regno << MIPS16OP_SH_RZ; | |
9408 | break; | |
9409 | case 'Z': | |
9410 | ip->insn_opcode |= regno << MIPS16OP_SH_MOVE32Z; | |
9411 | case '0': | |
9412 | case 'S': | |
9413 | case 'R': | |
9414 | break; | |
9415 | case 'X': | |
9416 | ip->insn_opcode |= regno << MIPS16OP_SH_REGR32; | |
9417 | break; | |
9418 | case 'Y': | |
9419 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); | |
9420 | ip->insn_opcode |= regno << MIPS16OP_SH_REG32R; | |
9421 | break; | |
9422 | default: | |
9423 | internalError (); | |
9424 | } | |
9425 | ||
9426 | lastregno = regno; | |
9427 | continue; | |
9428 | ||
9429 | case 'P': | |
9430 | if (strncmp (s, "$pc", 3) == 0) | |
9431 | { | |
9432 | s += 3; | |
9433 | continue; | |
9434 | } | |
9435 | break; | |
9436 | ||
252b5132 RH |
9437 | case '5': |
9438 | case 'H': | |
9439 | case 'W': | |
9440 | case 'D': | |
9441 | case 'j': | |
252b5132 RH |
9442 | case 'V': |
9443 | case 'C': | |
9444 | case 'U': | |
9445 | case 'k': | |
9446 | case 'K': | |
d6f16593 MR |
9447 | i = my_getSmallExpression (&imm_expr, imm_reloc, s); |
9448 | if (i > 0) | |
252b5132 | 9449 | { |
d6f16593 | 9450 | if (imm_expr.X_op != O_constant) |
252b5132 | 9451 | { |
b34976b6 | 9452 | mips16_ext = TRUE; |
b34976b6 | 9453 | ip->use_extend = TRUE; |
252b5132 | 9454 | ip->extend = 0; |
252b5132 | 9455 | } |
d6f16593 MR |
9456 | else |
9457 | { | |
9458 | /* We need to relax this instruction. */ | |
9459 | *offset_reloc = *imm_reloc; | |
9460 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; | |
9461 | } | |
9462 | s = expr_end; | |
9463 | continue; | |
252b5132 | 9464 | } |
d6f16593 MR |
9465 | *imm_reloc = BFD_RELOC_UNUSED; |
9466 | /* Fall through. */ | |
9467 | case '<': | |
9468 | case '>': | |
9469 | case '[': | |
9470 | case ']': | |
9471 | case '4': | |
9472 | case '8': | |
9473 | my_getExpression (&imm_expr, s); | |
252b5132 RH |
9474 | if (imm_expr.X_op == O_register) |
9475 | { | |
9476 | /* What we thought was an expression turned out to | |
9477 | be a register. */ | |
9478 | ||
9479 | if (s[0] == '(' && args[1] == '(') | |
9480 | { | |
9481 | /* It looks like the expression was omitted | |
9482 | before a register indirection, which means | |
9483 | that the expression is implicitly zero. We | |
9484 | still set up imm_expr, so that we handle | |
9485 | explicit extensions correctly. */ | |
9486 | imm_expr.X_op = O_constant; | |
9487 | imm_expr.X_add_number = 0; | |
f6688943 | 9488 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
9489 | continue; |
9490 | } | |
9491 | ||
9492 | break; | |
9493 | } | |
9494 | ||
9495 | /* We need to relax this instruction. */ | |
f6688943 | 9496 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
9497 | s = expr_end; |
9498 | continue; | |
9499 | ||
9500 | case 'p': | |
9501 | case 'q': | |
9502 | case 'A': | |
9503 | case 'B': | |
9504 | case 'E': | |
9505 | /* We use offset_reloc rather than imm_reloc for the PC | |
9506 | relative operands. This lets macros with both | |
9507 | immediate and address operands work correctly. */ | |
9508 | my_getExpression (&offset_expr, s); | |
9509 | ||
9510 | if (offset_expr.X_op == O_register) | |
9511 | break; | |
9512 | ||
9513 | /* We need to relax this instruction. */ | |
f6688943 | 9514 | *offset_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
9515 | s = expr_end; |
9516 | continue; | |
9517 | ||
9518 | case '6': /* break code */ | |
9519 | my_getExpression (&imm_expr, s); | |
9520 | check_absolute_expr (ip, &imm_expr); | |
9521 | if ((unsigned long) imm_expr.X_add_number > 63) | |
9522 | { | |
9523 | as_warn (_("Invalid value for `%s' (%lu)"), | |
9524 | ip->insn_mo->name, | |
9525 | (unsigned long) imm_expr.X_add_number); | |
9526 | imm_expr.X_add_number &= 0x3f; | |
9527 | } | |
9528 | ip->insn_opcode |= imm_expr.X_add_number << MIPS16OP_SH_IMM6; | |
9529 | imm_expr.X_op = O_absent; | |
9530 | s = expr_end; | |
9531 | continue; | |
9532 | ||
9533 | case 'a': /* 26 bit address */ | |
9534 | my_getExpression (&offset_expr, s); | |
9535 | s = expr_end; | |
f6688943 | 9536 | *offset_reloc = BFD_RELOC_MIPS16_JMP; |
252b5132 RH |
9537 | ip->insn_opcode <<= 16; |
9538 | continue; | |
9539 | ||
9540 | case 'l': /* register list for entry macro */ | |
9541 | case 'L': /* register list for exit macro */ | |
9542 | { | |
9543 | int mask; | |
9544 | ||
9545 | if (c == 'l') | |
9546 | mask = 0; | |
9547 | else | |
9548 | mask = 7 << 3; | |
9549 | while (*s != '\0') | |
9550 | { | |
9551 | int freg, reg1, reg2; | |
9552 | ||
9553 | while (*s == ' ' || *s == ',') | |
9554 | ++s; | |
9555 | if (*s != '$') | |
9556 | { | |
9557 | as_bad (_("can't parse register list")); | |
9558 | break; | |
9559 | } | |
9560 | ++s; | |
9561 | if (*s != 'f') | |
9562 | freg = 0; | |
9563 | else | |
9564 | { | |
9565 | freg = 1; | |
9566 | ++s; | |
9567 | } | |
9568 | reg1 = 0; | |
3882b010 | 9569 | while (ISDIGIT (*s)) |
252b5132 RH |
9570 | { |
9571 | reg1 *= 10; | |
9572 | reg1 += *s - '0'; | |
9573 | ++s; | |
9574 | } | |
9575 | if (*s == ' ') | |
9576 | ++s; | |
9577 | if (*s != '-') | |
9578 | reg2 = reg1; | |
9579 | else | |
9580 | { | |
9581 | ++s; | |
9582 | if (*s != '$') | |
9583 | break; | |
9584 | ++s; | |
9585 | if (freg) | |
9586 | { | |
9587 | if (*s == 'f') | |
9588 | ++s; | |
9589 | else | |
9590 | { | |
9591 | as_bad (_("invalid register list")); | |
9592 | break; | |
9593 | } | |
9594 | } | |
9595 | reg2 = 0; | |
3882b010 | 9596 | while (ISDIGIT (*s)) |
252b5132 RH |
9597 | { |
9598 | reg2 *= 10; | |
9599 | reg2 += *s - '0'; | |
9600 | ++s; | |
9601 | } | |
9602 | } | |
9603 | if (freg && reg1 == 0 && reg2 == 0 && c == 'L') | |
9604 | { | |
9605 | mask &= ~ (7 << 3); | |
9606 | mask |= 5 << 3; | |
9607 | } | |
9608 | else if (freg && reg1 == 0 && reg2 == 1 && c == 'L') | |
9609 | { | |
9610 | mask &= ~ (7 << 3); | |
9611 | mask |= 6 << 3; | |
9612 | } | |
9613 | else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L') | |
9614 | mask |= (reg2 - 3) << 3; | |
9615 | else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17) | |
9616 | mask |= (reg2 - 15) << 1; | |
f9419b05 | 9617 | else if (reg1 == RA && reg2 == RA) |
252b5132 RH |
9618 | mask |= 1; |
9619 | else | |
9620 | { | |
9621 | as_bad (_("invalid register list")); | |
9622 | break; | |
9623 | } | |
9624 | } | |
9625 | /* The mask is filled in in the opcode table for the | |
9626 | benefit of the disassembler. We remove it before | |
9627 | applying the actual mask. */ | |
9628 | ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6); | |
9629 | ip->insn_opcode |= mask << MIPS16OP_SH_IMM6; | |
9630 | } | |
9631 | continue; | |
9632 | ||
9633 | case 'e': /* extend code */ | |
9634 | my_getExpression (&imm_expr, s); | |
9635 | check_absolute_expr (ip, &imm_expr); | |
9636 | if ((unsigned long) imm_expr.X_add_number > 0x7ff) | |
9637 | { | |
9638 | as_warn (_("Invalid value for `%s' (%lu)"), | |
9639 | ip->insn_mo->name, | |
9640 | (unsigned long) imm_expr.X_add_number); | |
9641 | imm_expr.X_add_number &= 0x7ff; | |
9642 | } | |
9643 | ip->insn_opcode |= imm_expr.X_add_number; | |
9644 | imm_expr.X_op = O_absent; | |
9645 | s = expr_end; | |
9646 | continue; | |
9647 | ||
9648 | default: | |
9649 | internalError (); | |
9650 | } | |
9651 | break; | |
9652 | } | |
9653 | ||
9654 | /* Args don't match. */ | |
9655 | if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] && | |
9656 | strcmp (insn->name, insn[1].name) == 0) | |
9657 | { | |
9658 | ++insn; | |
9659 | s = argsstart; | |
9660 | continue; | |
9661 | } | |
9662 | ||
9663 | insn_error = _("illegal operands"); | |
9664 | ||
9665 | return; | |
9666 | } | |
9667 | } | |
9668 | ||
9669 | /* This structure holds information we know about a mips16 immediate | |
9670 | argument type. */ | |
9671 | ||
e972090a NC |
9672 | struct mips16_immed_operand |
9673 | { | |
252b5132 RH |
9674 | /* The type code used in the argument string in the opcode table. */ |
9675 | int type; | |
9676 | /* The number of bits in the short form of the opcode. */ | |
9677 | int nbits; | |
9678 | /* The number of bits in the extended form of the opcode. */ | |
9679 | int extbits; | |
9680 | /* The amount by which the short form is shifted when it is used; | |
9681 | for example, the sw instruction has a shift count of 2. */ | |
9682 | int shift; | |
9683 | /* The amount by which the short form is shifted when it is stored | |
9684 | into the instruction code. */ | |
9685 | int op_shift; | |
9686 | /* Non-zero if the short form is unsigned. */ | |
9687 | int unsp; | |
9688 | /* Non-zero if the extended form is unsigned. */ | |
9689 | int extu; | |
9690 | /* Non-zero if the value is PC relative. */ | |
9691 | int pcrel; | |
9692 | }; | |
9693 | ||
9694 | /* The mips16 immediate operand types. */ | |
9695 | ||
9696 | static const struct mips16_immed_operand mips16_immed_operands[] = | |
9697 | { | |
9698 | { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
9699 | { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
9700 | { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
9701 | { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
9702 | { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 }, | |
9703 | { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
9704 | { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
9705 | { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
9706 | { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
9707 | { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 }, | |
9708 | { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
9709 | { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
9710 | { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
9711 | { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 }, | |
9712 | { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
9713 | { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
9714 | { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
9715 | { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
9716 | { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 }, | |
9717 | { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 }, | |
9718 | { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 } | |
9719 | }; | |
9720 | ||
9721 | #define MIPS16_NUM_IMMED \ | |
9722 | (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0]) | |
9723 | ||
9724 | /* Handle a mips16 instruction with an immediate value. This or's the | |
9725 | small immediate value into *INSN. It sets *USE_EXTEND to indicate | |
9726 | whether an extended value is needed; if one is needed, it sets | |
9727 | *EXTEND to the value. The argument type is TYPE. The value is VAL. | |
9728 | If SMALL is true, an unextended opcode was explicitly requested. | |
9729 | If EXT is true, an extended opcode was explicitly requested. If | |
9730 | WARN is true, warn if EXT does not match reality. */ | |
9731 | ||
9732 | static void | |
17a2f251 TS |
9733 | mips16_immed (char *file, unsigned int line, int type, offsetT val, |
9734 | bfd_boolean warn, bfd_boolean small, bfd_boolean ext, | |
9735 | unsigned long *insn, bfd_boolean *use_extend, | |
9736 | unsigned short *extend) | |
252b5132 RH |
9737 | { |
9738 | register const struct mips16_immed_operand *op; | |
9739 | int mintiny, maxtiny; | |
b34976b6 | 9740 | bfd_boolean needext; |
252b5132 RH |
9741 | |
9742 | op = mips16_immed_operands; | |
9743 | while (op->type != type) | |
9744 | { | |
9745 | ++op; | |
9746 | assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); | |
9747 | } | |
9748 | ||
9749 | if (op->unsp) | |
9750 | { | |
9751 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
9752 | { | |
9753 | mintiny = 1; | |
9754 | maxtiny = 1 << op->nbits; | |
9755 | } | |
9756 | else | |
9757 | { | |
9758 | mintiny = 0; | |
9759 | maxtiny = (1 << op->nbits) - 1; | |
9760 | } | |
9761 | } | |
9762 | else | |
9763 | { | |
9764 | mintiny = - (1 << (op->nbits - 1)); | |
9765 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
9766 | } | |
9767 | ||
9768 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
9769 | if (type == 'p' || type == 'q') | |
9770 | val /= 2; | |
9771 | ||
9772 | if ((val & ((1 << op->shift) - 1)) != 0 | |
9773 | || val < (mintiny << op->shift) | |
9774 | || val > (maxtiny << op->shift)) | |
b34976b6 | 9775 | needext = TRUE; |
252b5132 | 9776 | else |
b34976b6 | 9777 | needext = FALSE; |
252b5132 RH |
9778 | |
9779 | if (warn && ext && ! needext) | |
beae10d5 KH |
9780 | as_warn_where (file, line, |
9781 | _("extended operand requested but not required")); | |
252b5132 RH |
9782 | if (small && needext) |
9783 | as_bad_where (file, line, _("invalid unextended operand value")); | |
9784 | ||
9785 | if (small || (! ext && ! needext)) | |
9786 | { | |
9787 | int insnval; | |
9788 | ||
b34976b6 | 9789 | *use_extend = FALSE; |
252b5132 RH |
9790 | insnval = ((val >> op->shift) & ((1 << op->nbits) - 1)); |
9791 | insnval <<= op->op_shift; | |
9792 | *insn |= insnval; | |
9793 | } | |
9794 | else | |
9795 | { | |
9796 | long minext, maxext; | |
9797 | int extval; | |
9798 | ||
9799 | if (op->extu) | |
9800 | { | |
9801 | minext = 0; | |
9802 | maxext = (1 << op->extbits) - 1; | |
9803 | } | |
9804 | else | |
9805 | { | |
9806 | minext = - (1 << (op->extbits - 1)); | |
9807 | maxext = (1 << (op->extbits - 1)) - 1; | |
9808 | } | |
9809 | if (val < minext || val > maxext) | |
9810 | as_bad_where (file, line, | |
9811 | _("operand value out of range for instruction")); | |
9812 | ||
b34976b6 | 9813 | *use_extend = TRUE; |
252b5132 RH |
9814 | if (op->extbits == 16) |
9815 | { | |
9816 | extval = ((val >> 11) & 0x1f) | (val & 0x7e0); | |
9817 | val &= 0x1f; | |
9818 | } | |
9819 | else if (op->extbits == 15) | |
9820 | { | |
9821 | extval = ((val >> 11) & 0xf) | (val & 0x7f0); | |
9822 | val &= 0xf; | |
9823 | } | |
9824 | else | |
9825 | { | |
9826 | extval = ((val & 0x1f) << 6) | (val & 0x20); | |
9827 | val = 0; | |
9828 | } | |
9829 | ||
9830 | *extend = (unsigned short) extval; | |
9831 | *insn |= val; | |
9832 | } | |
9833 | } | |
9834 | \f | |
d6f16593 | 9835 | struct percent_op_match |
ad8d3bb3 | 9836 | { |
5e0116d5 RS |
9837 | const char *str; |
9838 | bfd_reloc_code_real_type reloc; | |
d6f16593 MR |
9839 | }; |
9840 | ||
9841 | static const struct percent_op_match mips_percent_op[] = | |
ad8d3bb3 | 9842 | { |
5e0116d5 | 9843 | {"%lo", BFD_RELOC_LO16}, |
ad8d3bb3 | 9844 | #ifdef OBJ_ELF |
5e0116d5 RS |
9845 | {"%call_hi", BFD_RELOC_MIPS_CALL_HI16}, |
9846 | {"%call_lo", BFD_RELOC_MIPS_CALL_LO16}, | |
9847 | {"%call16", BFD_RELOC_MIPS_CALL16}, | |
9848 | {"%got_disp", BFD_RELOC_MIPS_GOT_DISP}, | |
9849 | {"%got_page", BFD_RELOC_MIPS_GOT_PAGE}, | |
9850 | {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST}, | |
9851 | {"%got_hi", BFD_RELOC_MIPS_GOT_HI16}, | |
9852 | {"%got_lo", BFD_RELOC_MIPS_GOT_LO16}, | |
9853 | {"%got", BFD_RELOC_MIPS_GOT16}, | |
9854 | {"%gp_rel", BFD_RELOC_GPREL16}, | |
9855 | {"%half", BFD_RELOC_16}, | |
9856 | {"%highest", BFD_RELOC_MIPS_HIGHEST}, | |
9857 | {"%higher", BFD_RELOC_MIPS_HIGHER}, | |
9858 | {"%neg", BFD_RELOC_MIPS_SUB}, | |
3f98094e DJ |
9859 | {"%tlsgd", BFD_RELOC_MIPS_TLS_GD}, |
9860 | {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM}, | |
9861 | {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16}, | |
9862 | {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16}, | |
9863 | {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16}, | |
9864 | {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16}, | |
9865 | {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL}, | |
ad8d3bb3 | 9866 | #endif |
5e0116d5 | 9867 | {"%hi", BFD_RELOC_HI16_S} |
ad8d3bb3 TS |
9868 | }; |
9869 | ||
d6f16593 MR |
9870 | static const struct percent_op_match mips16_percent_op[] = |
9871 | { | |
9872 | {"%lo", BFD_RELOC_MIPS16_LO16}, | |
9873 | {"%gprel", BFD_RELOC_MIPS16_GPREL}, | |
9874 | {"%hi", BFD_RELOC_MIPS16_HI16_S} | |
9875 | }; | |
9876 | ||
252b5132 | 9877 | |
5e0116d5 RS |
9878 | /* Return true if *STR points to a relocation operator. When returning true, |
9879 | move *STR over the operator and store its relocation code in *RELOC. | |
9880 | Leave both *STR and *RELOC alone when returning false. */ | |
9881 | ||
9882 | static bfd_boolean | |
17a2f251 | 9883 | parse_relocation (char **str, bfd_reloc_code_real_type *reloc) |
252b5132 | 9884 | { |
d6f16593 MR |
9885 | const struct percent_op_match *percent_op; |
9886 | size_t limit, i; | |
9887 | ||
9888 | if (mips_opts.mips16) | |
9889 | { | |
9890 | percent_op = mips16_percent_op; | |
9891 | limit = ARRAY_SIZE (mips16_percent_op); | |
9892 | } | |
9893 | else | |
9894 | { | |
9895 | percent_op = mips_percent_op; | |
9896 | limit = ARRAY_SIZE (mips_percent_op); | |
9897 | } | |
76b3015f | 9898 | |
d6f16593 | 9899 | for (i = 0; i < limit; i++) |
5e0116d5 | 9900 | if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0) |
394f9b3a | 9901 | { |
3f98094e DJ |
9902 | int len = strlen (percent_op[i].str); |
9903 | ||
9904 | if (!ISSPACE ((*str)[len]) && (*str)[len] != '(') | |
9905 | continue; | |
9906 | ||
5e0116d5 RS |
9907 | *str += strlen (percent_op[i].str); |
9908 | *reloc = percent_op[i].reloc; | |
394f9b3a | 9909 | |
5e0116d5 RS |
9910 | /* Check whether the output BFD supports this relocation. |
9911 | If not, issue an error and fall back on something safe. */ | |
9912 | if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc)) | |
394f9b3a | 9913 | { |
5e0116d5 RS |
9914 | as_bad ("relocation %s isn't supported by the current ABI", |
9915 | percent_op[i].str); | |
01a3f561 | 9916 | *reloc = BFD_RELOC_UNUSED; |
394f9b3a | 9917 | } |
5e0116d5 | 9918 | return TRUE; |
394f9b3a | 9919 | } |
5e0116d5 | 9920 | return FALSE; |
394f9b3a | 9921 | } |
ad8d3bb3 | 9922 | |
ad8d3bb3 | 9923 | |
5e0116d5 RS |
9924 | /* Parse string STR as a 16-bit relocatable operand. Store the |
9925 | expression in *EP and the relocations in the array starting | |
9926 | at RELOC. Return the number of relocation operators used. | |
ad8d3bb3 | 9927 | |
01a3f561 | 9928 | On exit, EXPR_END points to the first character after the expression. */ |
ad8d3bb3 | 9929 | |
5e0116d5 | 9930 | static size_t |
17a2f251 TS |
9931 | my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc, |
9932 | char *str) | |
ad8d3bb3 | 9933 | { |
5e0116d5 RS |
9934 | bfd_reloc_code_real_type reversed_reloc[3]; |
9935 | size_t reloc_index, i; | |
09b8f35a RS |
9936 | int crux_depth, str_depth; |
9937 | char *crux; | |
5e0116d5 RS |
9938 | |
9939 | /* Search for the start of the main expression, recoding relocations | |
09b8f35a RS |
9940 | in REVERSED_RELOC. End the loop with CRUX pointing to the start |
9941 | of the main expression and with CRUX_DEPTH containing the number | |
9942 | of open brackets at that point. */ | |
9943 | reloc_index = -1; | |
9944 | str_depth = 0; | |
9945 | do | |
fb1b3232 | 9946 | { |
09b8f35a RS |
9947 | reloc_index++; |
9948 | crux = str; | |
9949 | crux_depth = str_depth; | |
9950 | ||
9951 | /* Skip over whitespace and brackets, keeping count of the number | |
9952 | of brackets. */ | |
9953 | while (*str == ' ' || *str == '\t' || *str == '(') | |
9954 | if (*str++ == '(') | |
9955 | str_depth++; | |
5e0116d5 | 9956 | } |
09b8f35a RS |
9957 | while (*str == '%' |
9958 | && reloc_index < (HAVE_NEWABI ? 3 : 1) | |
9959 | && parse_relocation (&str, &reversed_reloc[reloc_index])); | |
ad8d3bb3 | 9960 | |
09b8f35a | 9961 | my_getExpression (ep, crux); |
5e0116d5 | 9962 | str = expr_end; |
394f9b3a | 9963 | |
5e0116d5 | 9964 | /* Match every open bracket. */ |
09b8f35a | 9965 | while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t')) |
5e0116d5 | 9966 | if (*str++ == ')') |
09b8f35a | 9967 | crux_depth--; |
394f9b3a | 9968 | |
09b8f35a | 9969 | if (crux_depth > 0) |
5e0116d5 | 9970 | as_bad ("unclosed '('"); |
394f9b3a | 9971 | |
5e0116d5 | 9972 | expr_end = str; |
252b5132 | 9973 | |
01a3f561 | 9974 | if (reloc_index != 0) |
64bdfcaf RS |
9975 | { |
9976 | prev_reloc_op_frag = frag_now; | |
9977 | for (i = 0; i < reloc_index; i++) | |
9978 | reloc[i] = reversed_reloc[reloc_index - 1 - i]; | |
9979 | } | |
fb1b3232 | 9980 | |
5e0116d5 | 9981 | return reloc_index; |
252b5132 RH |
9982 | } |
9983 | ||
9984 | static void | |
17a2f251 | 9985 | my_getExpression (expressionS *ep, char *str) |
252b5132 RH |
9986 | { |
9987 | char *save_in; | |
98aa84af | 9988 | valueT val; |
252b5132 RH |
9989 | |
9990 | save_in = input_line_pointer; | |
9991 | input_line_pointer = str; | |
9992 | expression (ep); | |
9993 | expr_end = input_line_pointer; | |
9994 | input_line_pointer = save_in; | |
9995 | ||
9996 | /* If we are in mips16 mode, and this is an expression based on `.', | |
9997 | then we bump the value of the symbol by 1 since that is how other | |
9998 | text symbols are handled. We don't bother to handle complex | |
9999 | expressions, just `.' plus or minus a constant. */ | |
10000 | if (mips_opts.mips16 | |
10001 | && ep->X_op == O_symbol | |
10002 | && strcmp (S_GET_NAME (ep->X_add_symbol), FAKE_LABEL_NAME) == 0 | |
10003 | && S_GET_SEGMENT (ep->X_add_symbol) == now_seg | |
49309057 ILT |
10004 | && symbol_get_frag (ep->X_add_symbol) == frag_now |
10005 | && symbol_constant_p (ep->X_add_symbol) | |
98aa84af AM |
10006 | && (val = S_GET_VALUE (ep->X_add_symbol)) == frag_now_fix ()) |
10007 | S_SET_VALUE (ep->X_add_symbol, val + 1); | |
252b5132 RH |
10008 | } |
10009 | ||
10010 | /* Turn a string in input_line_pointer into a floating point constant | |
bc0d738a NC |
10011 | of type TYPE, and store the appropriate bytes in *LITP. The number |
10012 | of LITTLENUMS emitted is stored in *SIZEP. An error message is | |
252b5132 RH |
10013 | returned, or NULL on OK. */ |
10014 | ||
10015 | char * | |
17a2f251 | 10016 | md_atof (int type, char *litP, int *sizeP) |
252b5132 RH |
10017 | { |
10018 | int prec; | |
10019 | LITTLENUM_TYPE words[4]; | |
10020 | char *t; | |
10021 | int i; | |
10022 | ||
10023 | switch (type) | |
10024 | { | |
10025 | case 'f': | |
10026 | prec = 2; | |
10027 | break; | |
10028 | ||
10029 | case 'd': | |
10030 | prec = 4; | |
10031 | break; | |
10032 | ||
10033 | default: | |
10034 | *sizeP = 0; | |
10035 | return _("bad call to md_atof"); | |
10036 | } | |
10037 | ||
10038 | t = atof_ieee (input_line_pointer, type, words); | |
10039 | if (t) | |
10040 | input_line_pointer = t; | |
10041 | ||
10042 | *sizeP = prec * 2; | |
10043 | ||
10044 | if (! target_big_endian) | |
10045 | { | |
10046 | for (i = prec - 1; i >= 0; i--) | |
10047 | { | |
17a2f251 | 10048 | md_number_to_chars (litP, words[i], 2); |
252b5132 RH |
10049 | litP += 2; |
10050 | } | |
10051 | } | |
10052 | else | |
10053 | { | |
10054 | for (i = 0; i < prec; i++) | |
10055 | { | |
17a2f251 | 10056 | md_number_to_chars (litP, words[i], 2); |
252b5132 RH |
10057 | litP += 2; |
10058 | } | |
10059 | } | |
bdaaa2e1 | 10060 | |
252b5132 RH |
10061 | return NULL; |
10062 | } | |
10063 | ||
10064 | void | |
17a2f251 | 10065 | md_number_to_chars (char *buf, valueT val, int n) |
252b5132 RH |
10066 | { |
10067 | if (target_big_endian) | |
10068 | number_to_chars_bigendian (buf, val, n); | |
10069 | else | |
10070 | number_to_chars_littleendian (buf, val, n); | |
10071 | } | |
10072 | \f | |
ae948b86 | 10073 | #ifdef OBJ_ELF |
e013f690 TS |
10074 | static int support_64bit_objects(void) |
10075 | { | |
10076 | const char **list, **l; | |
aa3d8fdf | 10077 | int yes; |
e013f690 TS |
10078 | |
10079 | list = bfd_target_list (); | |
10080 | for (l = list; *l != NULL; l++) | |
10081 | #ifdef TE_TMIPS | |
10082 | /* This is traditional mips */ | |
10083 | if (strcmp (*l, "elf64-tradbigmips") == 0 | |
10084 | || strcmp (*l, "elf64-tradlittlemips") == 0) | |
10085 | #else | |
10086 | if (strcmp (*l, "elf64-bigmips") == 0 | |
10087 | || strcmp (*l, "elf64-littlemips") == 0) | |
10088 | #endif | |
10089 | break; | |
aa3d8fdf | 10090 | yes = (*l != NULL); |
e013f690 | 10091 | free (list); |
aa3d8fdf | 10092 | return yes; |
e013f690 | 10093 | } |
ae948b86 | 10094 | #endif /* OBJ_ELF */ |
e013f690 | 10095 | |
78849248 | 10096 | const char *md_shortopts = "O::g::G:"; |
252b5132 | 10097 | |
e972090a NC |
10098 | struct option md_longopts[] = |
10099 | { | |
f9b4148d CD |
10100 | /* Options which specify architecture. */ |
10101 | #define OPTION_ARCH_BASE (OPTION_MD_BASE) | |
10102 | #define OPTION_MARCH (OPTION_ARCH_BASE + 0) | |
10103 | {"march", required_argument, NULL, OPTION_MARCH}, | |
10104 | #define OPTION_MTUNE (OPTION_ARCH_BASE + 1) | |
10105 | {"mtune", required_argument, NULL, OPTION_MTUNE}, | |
10106 | #define OPTION_MIPS1 (OPTION_ARCH_BASE + 2) | |
252b5132 RH |
10107 | {"mips0", no_argument, NULL, OPTION_MIPS1}, |
10108 | {"mips1", no_argument, NULL, OPTION_MIPS1}, | |
f9b4148d | 10109 | #define OPTION_MIPS2 (OPTION_ARCH_BASE + 3) |
252b5132 | 10110 | {"mips2", no_argument, NULL, OPTION_MIPS2}, |
f9b4148d | 10111 | #define OPTION_MIPS3 (OPTION_ARCH_BASE + 4) |
252b5132 | 10112 | {"mips3", no_argument, NULL, OPTION_MIPS3}, |
f9b4148d | 10113 | #define OPTION_MIPS4 (OPTION_ARCH_BASE + 5) |
252b5132 | 10114 | {"mips4", no_argument, NULL, OPTION_MIPS4}, |
f9b4148d | 10115 | #define OPTION_MIPS5 (OPTION_ARCH_BASE + 6) |
ae948b86 | 10116 | {"mips5", no_argument, NULL, OPTION_MIPS5}, |
f9b4148d | 10117 | #define OPTION_MIPS32 (OPTION_ARCH_BASE + 7) |
ae948b86 | 10118 | {"mips32", no_argument, NULL, OPTION_MIPS32}, |
f9b4148d | 10119 | #define OPTION_MIPS64 (OPTION_ARCH_BASE + 8) |
ae948b86 | 10120 | {"mips64", no_argument, NULL, OPTION_MIPS64}, |
f9b4148d CD |
10121 | #define OPTION_MIPS32R2 (OPTION_ARCH_BASE + 9) |
10122 | {"mips32r2", no_argument, NULL, OPTION_MIPS32R2}, | |
5f74bc13 CD |
10123 | #define OPTION_MIPS64R2 (OPTION_ARCH_BASE + 10) |
10124 | {"mips64r2", no_argument, NULL, OPTION_MIPS64R2}, | |
f9b4148d CD |
10125 | |
10126 | /* Options which specify Application Specific Extensions (ASEs). */ | |
5f74bc13 | 10127 | #define OPTION_ASE_BASE (OPTION_ARCH_BASE + 11) |
f9b4148d CD |
10128 | #define OPTION_MIPS16 (OPTION_ASE_BASE + 0) |
10129 | {"mips16", no_argument, NULL, OPTION_MIPS16}, | |
10130 | #define OPTION_NO_MIPS16 (OPTION_ASE_BASE + 1) | |
10131 | {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16}, | |
10132 | #define OPTION_MIPS3D (OPTION_ASE_BASE + 2) | |
10133 | {"mips3d", no_argument, NULL, OPTION_MIPS3D}, | |
10134 | #define OPTION_NO_MIPS3D (OPTION_ASE_BASE + 3) | |
10135 | {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D}, | |
10136 | #define OPTION_MDMX (OPTION_ASE_BASE + 4) | |
10137 | {"mdmx", no_argument, NULL, OPTION_MDMX}, | |
10138 | #define OPTION_NO_MDMX (OPTION_ASE_BASE + 5) | |
10139 | {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX}, | |
10140 | ||
10141 | /* Old-style architecture options. Don't add more of these. */ | |
10142 | #define OPTION_COMPAT_ARCH_BASE (OPTION_ASE_BASE + 6) | |
10143 | #define OPTION_M4650 (OPTION_COMPAT_ARCH_BASE + 0) | |
10144 | {"m4650", no_argument, NULL, OPTION_M4650}, | |
10145 | #define OPTION_NO_M4650 (OPTION_COMPAT_ARCH_BASE + 1) | |
10146 | {"no-m4650", no_argument, NULL, OPTION_NO_M4650}, | |
10147 | #define OPTION_M4010 (OPTION_COMPAT_ARCH_BASE + 2) | |
10148 | {"m4010", no_argument, NULL, OPTION_M4010}, | |
10149 | #define OPTION_NO_M4010 (OPTION_COMPAT_ARCH_BASE + 3) | |
10150 | {"no-m4010", no_argument, NULL, OPTION_NO_M4010}, | |
10151 | #define OPTION_M4100 (OPTION_COMPAT_ARCH_BASE + 4) | |
10152 | {"m4100", no_argument, NULL, OPTION_M4100}, | |
10153 | #define OPTION_NO_M4100 (OPTION_COMPAT_ARCH_BASE + 5) | |
10154 | {"no-m4100", no_argument, NULL, OPTION_NO_M4100}, | |
10155 | #define OPTION_M3900 (OPTION_COMPAT_ARCH_BASE + 6) | |
10156 | {"m3900", no_argument, NULL, OPTION_M3900}, | |
10157 | #define OPTION_NO_M3900 (OPTION_COMPAT_ARCH_BASE + 7) | |
10158 | {"no-m3900", no_argument, NULL, OPTION_NO_M3900}, | |
10159 | ||
10160 | /* Options which enable bug fixes. */ | |
10161 | #define OPTION_FIX_BASE (OPTION_COMPAT_ARCH_BASE + 8) | |
10162 | #define OPTION_M7000_HILO_FIX (OPTION_FIX_BASE + 0) | |
10163 | {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX}, | |
10164 | #define OPTION_MNO_7000_HILO_FIX (OPTION_FIX_BASE + 1) | |
10165 | {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, | |
10166 | {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, | |
d766e8ec RS |
10167 | #define OPTION_FIX_VR4120 (OPTION_FIX_BASE + 2) |
10168 | #define OPTION_NO_FIX_VR4120 (OPTION_FIX_BASE + 3) | |
10169 | {"mfix-vr4120", no_argument, NULL, OPTION_FIX_VR4120}, | |
10170 | {"mno-fix-vr4120", no_argument, NULL, OPTION_NO_FIX_VR4120}, | |
f9b4148d CD |
10171 | |
10172 | /* Miscellaneous options. */ | |
10173 | #define OPTION_MISC_BASE (OPTION_FIX_BASE + 4) | |
1ffcab4b | 10174 | #define OPTION_TRAP (OPTION_MISC_BASE + 0) |
252b5132 RH |
10175 | {"trap", no_argument, NULL, OPTION_TRAP}, |
10176 | {"no-break", no_argument, NULL, OPTION_TRAP}, | |
1ffcab4b | 10177 | #define OPTION_BREAK (OPTION_MISC_BASE + 1) |
252b5132 RH |
10178 | {"break", no_argument, NULL, OPTION_BREAK}, |
10179 | {"no-trap", no_argument, NULL, OPTION_BREAK}, | |
1ffcab4b | 10180 | #define OPTION_EB (OPTION_MISC_BASE + 2) |
252b5132 | 10181 | {"EB", no_argument, NULL, OPTION_EB}, |
1ffcab4b | 10182 | #define OPTION_EL (OPTION_MISC_BASE + 3) |
252b5132 | 10183 | {"EL", no_argument, NULL, OPTION_EL}, |
1ffcab4b | 10184 | #define OPTION_FP32 (OPTION_MISC_BASE + 4) |
ae948b86 | 10185 | {"mfp32", no_argument, NULL, OPTION_FP32}, |
1ffcab4b | 10186 | #define OPTION_GP32 (OPTION_MISC_BASE + 5) |
c97ef257 | 10187 | {"mgp32", no_argument, NULL, OPTION_GP32}, |
1ffcab4b | 10188 | #define OPTION_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 6) |
119d663a | 10189 | {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS}, |
1ffcab4b | 10190 | #define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 7) |
119d663a | 10191 | {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS}, |
1ffcab4b | 10192 | #define OPTION_FP64 (OPTION_MISC_BASE + 8) |
316f5878 | 10193 | {"mfp64", no_argument, NULL, OPTION_FP64}, |
1ffcab4b | 10194 | #define OPTION_GP64 (OPTION_MISC_BASE + 9) |
ae948b86 | 10195 | {"mgp64", no_argument, NULL, OPTION_GP64}, |
1ffcab4b CD |
10196 | #define OPTION_RELAX_BRANCH (OPTION_MISC_BASE + 10) |
10197 | #define OPTION_NO_RELAX_BRANCH (OPTION_MISC_BASE + 11) | |
4a6a3df4 AO |
10198 | {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH}, |
10199 | {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH}, | |
aa6975fb ILT |
10200 | #define OPTION_MSHARED (OPTION_MISC_BASE + 12) |
10201 | #define OPTION_MNO_SHARED (OPTION_MISC_BASE + 13) | |
10202 | {"mshared", no_argument, NULL, OPTION_MSHARED}, | |
10203 | {"mno-shared", no_argument, NULL, OPTION_MNO_SHARED}, | |
f9b4148d CD |
10204 | |
10205 | /* ELF-specific options. */ | |
156c2f8b | 10206 | #ifdef OBJ_ELF |
aa6975fb | 10207 | #define OPTION_ELF_BASE (OPTION_MISC_BASE + 14) |
156c2f8b | 10208 | #define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0) |
156c2f8b NC |
10209 | {"KPIC", no_argument, NULL, OPTION_CALL_SHARED}, |
10210 | {"call_shared", no_argument, NULL, OPTION_CALL_SHARED}, | |
ae948b86 | 10211 | #define OPTION_NON_SHARED (OPTION_ELF_BASE + 1) |
156c2f8b | 10212 | {"non_shared", no_argument, NULL, OPTION_NON_SHARED}, |
ae948b86 | 10213 | #define OPTION_XGOT (OPTION_ELF_BASE + 2) |
156c2f8b | 10214 | {"xgot", no_argument, NULL, OPTION_XGOT}, |
ae948b86 TS |
10215 | #define OPTION_MABI (OPTION_ELF_BASE + 3) |
10216 | {"mabi", required_argument, NULL, OPTION_MABI}, | |
10217 | #define OPTION_32 (OPTION_ELF_BASE + 4) | |
156c2f8b | 10218 | {"32", no_argument, NULL, OPTION_32}, |
ae948b86 | 10219 | #define OPTION_N32 (OPTION_ELF_BASE + 5) |
e013f690 | 10220 | {"n32", no_argument, NULL, OPTION_N32}, |
ae948b86 | 10221 | #define OPTION_64 (OPTION_ELF_BASE + 6) |
156c2f8b | 10222 | {"64", no_argument, NULL, OPTION_64}, |
ecb4347a DJ |
10223 | #define OPTION_MDEBUG (OPTION_ELF_BASE + 7) |
10224 | {"mdebug", no_argument, NULL, OPTION_MDEBUG}, | |
10225 | #define OPTION_NO_MDEBUG (OPTION_ELF_BASE + 8) | |
10226 | {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG}, | |
dcd410fe RO |
10227 | #define OPTION_PDR (OPTION_ELF_BASE + 9) |
10228 | {"mpdr", no_argument, NULL, OPTION_PDR}, | |
10229 | #define OPTION_NO_PDR (OPTION_ELF_BASE + 10) | |
10230 | {"mno-pdr", no_argument, NULL, OPTION_NO_PDR}, | |
ae948b86 | 10231 | #endif /* OBJ_ELF */ |
f9b4148d | 10232 | |
252b5132 RH |
10233 | {NULL, no_argument, NULL, 0} |
10234 | }; | |
156c2f8b | 10235 | size_t md_longopts_size = sizeof (md_longopts); |
252b5132 | 10236 | |
316f5878 RS |
10237 | /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to |
10238 | NEW_VALUE. Warn if another value was already specified. Note: | |
10239 | we have to defer parsing the -march and -mtune arguments in order | |
10240 | to handle 'from-abi' correctly, since the ABI might be specified | |
10241 | in a later argument. */ | |
10242 | ||
10243 | static void | |
17a2f251 | 10244 | mips_set_option_string (const char **string_ptr, const char *new_value) |
316f5878 RS |
10245 | { |
10246 | if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0) | |
10247 | as_warn (_("A different %s was already specified, is now %s"), | |
10248 | string_ptr == &mips_arch_string ? "-march" : "-mtune", | |
10249 | new_value); | |
10250 | ||
10251 | *string_ptr = new_value; | |
10252 | } | |
10253 | ||
252b5132 | 10254 | int |
17a2f251 | 10255 | md_parse_option (int c, char *arg) |
252b5132 RH |
10256 | { |
10257 | switch (c) | |
10258 | { | |
119d663a NC |
10259 | case OPTION_CONSTRUCT_FLOATS: |
10260 | mips_disable_float_construction = 0; | |
10261 | break; | |
bdaaa2e1 | 10262 | |
119d663a NC |
10263 | case OPTION_NO_CONSTRUCT_FLOATS: |
10264 | mips_disable_float_construction = 1; | |
10265 | break; | |
bdaaa2e1 | 10266 | |
252b5132 RH |
10267 | case OPTION_TRAP: |
10268 | mips_trap = 1; | |
10269 | break; | |
10270 | ||
10271 | case OPTION_BREAK: | |
10272 | mips_trap = 0; | |
10273 | break; | |
10274 | ||
10275 | case OPTION_EB: | |
10276 | target_big_endian = 1; | |
10277 | break; | |
10278 | ||
10279 | case OPTION_EL: | |
10280 | target_big_endian = 0; | |
10281 | break; | |
10282 | ||
10283 | case 'O': | |
10284 | if (arg && arg[1] == '0') | |
10285 | mips_optimize = 1; | |
10286 | else | |
10287 | mips_optimize = 2; | |
10288 | break; | |
10289 | ||
10290 | case 'g': | |
10291 | if (arg == NULL) | |
10292 | mips_debug = 2; | |
10293 | else | |
10294 | mips_debug = atoi (arg); | |
10295 | /* When the MIPS assembler sees -g or -g2, it does not do | |
10296 | optimizations which limit full symbolic debugging. We take | |
10297 | that to be equivalent to -O0. */ | |
10298 | if (mips_debug == 2) | |
10299 | mips_optimize = 1; | |
10300 | break; | |
10301 | ||
10302 | case OPTION_MIPS1: | |
316f5878 | 10303 | file_mips_isa = ISA_MIPS1; |
252b5132 RH |
10304 | break; |
10305 | ||
10306 | case OPTION_MIPS2: | |
316f5878 | 10307 | file_mips_isa = ISA_MIPS2; |
252b5132 RH |
10308 | break; |
10309 | ||
10310 | case OPTION_MIPS3: | |
316f5878 | 10311 | file_mips_isa = ISA_MIPS3; |
252b5132 RH |
10312 | break; |
10313 | ||
10314 | case OPTION_MIPS4: | |
316f5878 | 10315 | file_mips_isa = ISA_MIPS4; |
e7af610e NC |
10316 | break; |
10317 | ||
84ea6cf2 | 10318 | case OPTION_MIPS5: |
316f5878 | 10319 | file_mips_isa = ISA_MIPS5; |
84ea6cf2 NC |
10320 | break; |
10321 | ||
e7af610e | 10322 | case OPTION_MIPS32: |
316f5878 | 10323 | file_mips_isa = ISA_MIPS32; |
252b5132 RH |
10324 | break; |
10325 | ||
af7ee8bf CD |
10326 | case OPTION_MIPS32R2: |
10327 | file_mips_isa = ISA_MIPS32R2; | |
10328 | break; | |
10329 | ||
5f74bc13 CD |
10330 | case OPTION_MIPS64R2: |
10331 | file_mips_isa = ISA_MIPS64R2; | |
10332 | break; | |
10333 | ||
84ea6cf2 | 10334 | case OPTION_MIPS64: |
316f5878 | 10335 | file_mips_isa = ISA_MIPS64; |
84ea6cf2 NC |
10336 | break; |
10337 | ||
ec68c924 | 10338 | case OPTION_MTUNE: |
316f5878 RS |
10339 | mips_set_option_string (&mips_tune_string, arg); |
10340 | break; | |
ec68c924 | 10341 | |
316f5878 RS |
10342 | case OPTION_MARCH: |
10343 | mips_set_option_string (&mips_arch_string, arg); | |
252b5132 RH |
10344 | break; |
10345 | ||
10346 | case OPTION_M4650: | |
316f5878 RS |
10347 | mips_set_option_string (&mips_arch_string, "4650"); |
10348 | mips_set_option_string (&mips_tune_string, "4650"); | |
252b5132 RH |
10349 | break; |
10350 | ||
10351 | case OPTION_NO_M4650: | |
10352 | break; | |
10353 | ||
10354 | case OPTION_M4010: | |
316f5878 RS |
10355 | mips_set_option_string (&mips_arch_string, "4010"); |
10356 | mips_set_option_string (&mips_tune_string, "4010"); | |
252b5132 RH |
10357 | break; |
10358 | ||
10359 | case OPTION_NO_M4010: | |
10360 | break; | |
10361 | ||
10362 | case OPTION_M4100: | |
316f5878 RS |
10363 | mips_set_option_string (&mips_arch_string, "4100"); |
10364 | mips_set_option_string (&mips_tune_string, "4100"); | |
252b5132 RH |
10365 | break; |
10366 | ||
10367 | case OPTION_NO_M4100: | |
10368 | break; | |
10369 | ||
252b5132 | 10370 | case OPTION_M3900: |
316f5878 RS |
10371 | mips_set_option_string (&mips_arch_string, "3900"); |
10372 | mips_set_option_string (&mips_tune_string, "3900"); | |
252b5132 | 10373 | break; |
bdaaa2e1 | 10374 | |
252b5132 RH |
10375 | case OPTION_NO_M3900: |
10376 | break; | |
10377 | ||
deec1734 CD |
10378 | case OPTION_MDMX: |
10379 | mips_opts.ase_mdmx = 1; | |
10380 | break; | |
10381 | ||
10382 | case OPTION_NO_MDMX: | |
10383 | mips_opts.ase_mdmx = 0; | |
10384 | break; | |
10385 | ||
252b5132 RH |
10386 | case OPTION_MIPS16: |
10387 | mips_opts.mips16 = 1; | |
b34976b6 | 10388 | mips_no_prev_insn (FALSE); |
252b5132 RH |
10389 | break; |
10390 | ||
10391 | case OPTION_NO_MIPS16: | |
10392 | mips_opts.mips16 = 0; | |
b34976b6 | 10393 | mips_no_prev_insn (FALSE); |
252b5132 RH |
10394 | break; |
10395 | ||
1f25f5d3 CD |
10396 | case OPTION_MIPS3D: |
10397 | mips_opts.ase_mips3d = 1; | |
10398 | break; | |
10399 | ||
10400 | case OPTION_NO_MIPS3D: | |
10401 | mips_opts.ase_mips3d = 0; | |
10402 | break; | |
10403 | ||
d766e8ec RS |
10404 | case OPTION_FIX_VR4120: |
10405 | mips_fix_vr4120 = 1; | |
60b63b72 RS |
10406 | break; |
10407 | ||
d766e8ec RS |
10408 | case OPTION_NO_FIX_VR4120: |
10409 | mips_fix_vr4120 = 0; | |
60b63b72 RS |
10410 | break; |
10411 | ||
4a6a3df4 AO |
10412 | case OPTION_RELAX_BRANCH: |
10413 | mips_relax_branch = 1; | |
10414 | break; | |
10415 | ||
10416 | case OPTION_NO_RELAX_BRANCH: | |
10417 | mips_relax_branch = 0; | |
10418 | break; | |
10419 | ||
aa6975fb ILT |
10420 | case OPTION_MSHARED: |
10421 | mips_in_shared = TRUE; | |
10422 | break; | |
10423 | ||
10424 | case OPTION_MNO_SHARED: | |
10425 | mips_in_shared = FALSE; | |
10426 | break; | |
10427 | ||
0f074f60 | 10428 | #ifdef OBJ_ELF |
252b5132 RH |
10429 | /* When generating ELF code, we permit -KPIC and -call_shared to |
10430 | select SVR4_PIC, and -non_shared to select no PIC. This is | |
10431 | intended to be compatible with Irix 5. */ | |
10432 | case OPTION_CALL_SHARED: | |
10433 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
10434 | { | |
10435 | as_bad (_("-call_shared is supported only for ELF format")); | |
10436 | return 0; | |
10437 | } | |
10438 | mips_pic = SVR4_PIC; | |
143d77c5 | 10439 | mips_abicalls = TRUE; |
252b5132 RH |
10440 | if (g_switch_seen && g_switch_value != 0) |
10441 | { | |
10442 | as_bad (_("-G may not be used with SVR4 PIC code")); | |
10443 | return 0; | |
10444 | } | |
10445 | g_switch_value = 0; | |
10446 | break; | |
10447 | ||
10448 | case OPTION_NON_SHARED: | |
10449 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
10450 | { | |
10451 | as_bad (_("-non_shared is supported only for ELF format")); | |
10452 | return 0; | |
10453 | } | |
10454 | mips_pic = NO_PIC; | |
143d77c5 | 10455 | mips_abicalls = FALSE; |
252b5132 RH |
10456 | break; |
10457 | ||
10458 | /* The -xgot option tells the assembler to use 32 offsets when | |
10459 | accessing the got in SVR4_PIC mode. It is for Irix | |
10460 | compatibility. */ | |
10461 | case OPTION_XGOT: | |
10462 | mips_big_got = 1; | |
10463 | break; | |
0f074f60 | 10464 | #endif /* OBJ_ELF */ |
252b5132 RH |
10465 | |
10466 | case 'G': | |
3e722fb5 | 10467 | if (mips_pic == SVR4_PIC) |
252b5132 | 10468 | { |
3e722fb5 | 10469 | as_bad (_("-G may not be used with SVR4 PIC code")); |
252b5132 RH |
10470 | return 0; |
10471 | } | |
10472 | else | |
10473 | g_switch_value = atoi (arg); | |
10474 | g_switch_seen = 1; | |
10475 | break; | |
10476 | ||
0f074f60 | 10477 | #ifdef OBJ_ELF |
34ba82a8 TS |
10478 | /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32 |
10479 | and -mabi=64. */ | |
252b5132 | 10480 | case OPTION_32: |
34ba82a8 TS |
10481 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
10482 | { | |
10483 | as_bad (_("-32 is supported for ELF format only")); | |
10484 | return 0; | |
10485 | } | |
316f5878 | 10486 | mips_abi = O32_ABI; |
252b5132 RH |
10487 | break; |
10488 | ||
e013f690 | 10489 | case OPTION_N32: |
34ba82a8 TS |
10490 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
10491 | { | |
10492 | as_bad (_("-n32 is supported for ELF format only")); | |
10493 | return 0; | |
10494 | } | |
316f5878 | 10495 | mips_abi = N32_ABI; |
e013f690 | 10496 | break; |
252b5132 | 10497 | |
e013f690 | 10498 | case OPTION_64: |
34ba82a8 TS |
10499 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
10500 | { | |
10501 | as_bad (_("-64 is supported for ELF format only")); | |
10502 | return 0; | |
10503 | } | |
316f5878 | 10504 | mips_abi = N64_ABI; |
e013f690 TS |
10505 | if (! support_64bit_objects()) |
10506 | as_fatal (_("No compiled in support for 64 bit object file format")); | |
252b5132 | 10507 | break; |
ae948b86 | 10508 | #endif /* OBJ_ELF */ |
252b5132 | 10509 | |
c97ef257 | 10510 | case OPTION_GP32: |
a325df1d | 10511 | file_mips_gp32 = 1; |
c97ef257 AH |
10512 | break; |
10513 | ||
10514 | case OPTION_GP64: | |
a325df1d | 10515 | file_mips_gp32 = 0; |
c97ef257 | 10516 | break; |
252b5132 | 10517 | |
ca4e0257 | 10518 | case OPTION_FP32: |
a325df1d | 10519 | file_mips_fp32 = 1; |
316f5878 RS |
10520 | break; |
10521 | ||
10522 | case OPTION_FP64: | |
10523 | file_mips_fp32 = 0; | |
ca4e0257 RS |
10524 | break; |
10525 | ||
ae948b86 | 10526 | #ifdef OBJ_ELF |
252b5132 | 10527 | case OPTION_MABI: |
34ba82a8 TS |
10528 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
10529 | { | |
10530 | as_bad (_("-mabi is supported for ELF format only")); | |
10531 | return 0; | |
10532 | } | |
e013f690 | 10533 | if (strcmp (arg, "32") == 0) |
316f5878 | 10534 | mips_abi = O32_ABI; |
e013f690 | 10535 | else if (strcmp (arg, "o64") == 0) |
316f5878 | 10536 | mips_abi = O64_ABI; |
e013f690 | 10537 | else if (strcmp (arg, "n32") == 0) |
316f5878 | 10538 | mips_abi = N32_ABI; |
e013f690 TS |
10539 | else if (strcmp (arg, "64") == 0) |
10540 | { | |
316f5878 | 10541 | mips_abi = N64_ABI; |
e013f690 TS |
10542 | if (! support_64bit_objects()) |
10543 | as_fatal (_("No compiled in support for 64 bit object file " | |
10544 | "format")); | |
10545 | } | |
10546 | else if (strcmp (arg, "eabi") == 0) | |
316f5878 | 10547 | mips_abi = EABI_ABI; |
e013f690 | 10548 | else |
da0e507f TS |
10549 | { |
10550 | as_fatal (_("invalid abi -mabi=%s"), arg); | |
10551 | return 0; | |
10552 | } | |
252b5132 | 10553 | break; |
e013f690 | 10554 | #endif /* OBJ_ELF */ |
252b5132 | 10555 | |
6b76fefe | 10556 | case OPTION_M7000_HILO_FIX: |
b34976b6 | 10557 | mips_7000_hilo_fix = TRUE; |
6b76fefe CM |
10558 | break; |
10559 | ||
9ee72ff1 | 10560 | case OPTION_MNO_7000_HILO_FIX: |
b34976b6 | 10561 | mips_7000_hilo_fix = FALSE; |
6b76fefe CM |
10562 | break; |
10563 | ||
ecb4347a DJ |
10564 | #ifdef OBJ_ELF |
10565 | case OPTION_MDEBUG: | |
b34976b6 | 10566 | mips_flag_mdebug = TRUE; |
ecb4347a DJ |
10567 | break; |
10568 | ||
10569 | case OPTION_NO_MDEBUG: | |
b34976b6 | 10570 | mips_flag_mdebug = FALSE; |
ecb4347a | 10571 | break; |
dcd410fe RO |
10572 | |
10573 | case OPTION_PDR: | |
10574 | mips_flag_pdr = TRUE; | |
10575 | break; | |
10576 | ||
10577 | case OPTION_NO_PDR: | |
10578 | mips_flag_pdr = FALSE; | |
10579 | break; | |
ecb4347a DJ |
10580 | #endif /* OBJ_ELF */ |
10581 | ||
252b5132 RH |
10582 | default: |
10583 | return 0; | |
10584 | } | |
10585 | ||
10586 | return 1; | |
10587 | } | |
316f5878 RS |
10588 | \f |
10589 | /* Set up globals to generate code for the ISA or processor | |
10590 | described by INFO. */ | |
252b5132 | 10591 | |
252b5132 | 10592 | static void |
17a2f251 | 10593 | mips_set_architecture (const struct mips_cpu_info *info) |
252b5132 | 10594 | { |
316f5878 | 10595 | if (info != 0) |
252b5132 | 10596 | { |
fef14a42 TS |
10597 | file_mips_arch = info->cpu; |
10598 | mips_opts.arch = info->cpu; | |
316f5878 | 10599 | mips_opts.isa = info->isa; |
252b5132 | 10600 | } |
252b5132 RH |
10601 | } |
10602 | ||
252b5132 | 10603 | |
316f5878 | 10604 | /* Likewise for tuning. */ |
252b5132 | 10605 | |
316f5878 | 10606 | static void |
17a2f251 | 10607 | mips_set_tune (const struct mips_cpu_info *info) |
316f5878 RS |
10608 | { |
10609 | if (info != 0) | |
fef14a42 | 10610 | mips_tune = info->cpu; |
316f5878 | 10611 | } |
80cc45a5 | 10612 | |
34ba82a8 | 10613 | |
252b5132 | 10614 | void |
17a2f251 | 10615 | mips_after_parse_args (void) |
e9670677 | 10616 | { |
fef14a42 TS |
10617 | const struct mips_cpu_info *arch_info = 0; |
10618 | const struct mips_cpu_info *tune_info = 0; | |
10619 | ||
e9670677 MR |
10620 | /* GP relative stuff not working for PE */ |
10621 | if (strncmp (TARGET_OS, "pe", 2) == 0 | |
10622 | && g_switch_value != 0) | |
10623 | { | |
10624 | if (g_switch_seen) | |
10625 | as_bad (_("-G not supported in this configuration.")); | |
10626 | g_switch_value = 0; | |
10627 | } | |
10628 | ||
cac012d6 AO |
10629 | if (mips_abi == NO_ABI) |
10630 | mips_abi = MIPS_DEFAULT_ABI; | |
10631 | ||
22923709 RS |
10632 | /* The following code determines the architecture and register size. |
10633 | Similar code was added to GCC 3.3 (see override_options() in | |
10634 | config/mips/mips.c). The GAS and GCC code should be kept in sync | |
10635 | as much as possible. */ | |
e9670677 | 10636 | |
316f5878 | 10637 | if (mips_arch_string != 0) |
fef14a42 | 10638 | arch_info = mips_parse_cpu ("-march", mips_arch_string); |
e9670677 | 10639 | |
316f5878 | 10640 | if (file_mips_isa != ISA_UNKNOWN) |
e9670677 | 10641 | { |
316f5878 | 10642 | /* Handle -mipsN. At this point, file_mips_isa contains the |
fef14a42 | 10643 | ISA level specified by -mipsN, while arch_info->isa contains |
316f5878 | 10644 | the -march selection (if any). */ |
fef14a42 | 10645 | if (arch_info != 0) |
e9670677 | 10646 | { |
316f5878 RS |
10647 | /* -march takes precedence over -mipsN, since it is more descriptive. |
10648 | There's no harm in specifying both as long as the ISA levels | |
10649 | are the same. */ | |
fef14a42 | 10650 | if (file_mips_isa != arch_info->isa) |
316f5878 RS |
10651 | as_bad (_("-%s conflicts with the other architecture options, which imply -%s"), |
10652 | mips_cpu_info_from_isa (file_mips_isa)->name, | |
fef14a42 | 10653 | mips_cpu_info_from_isa (arch_info->isa)->name); |
e9670677 | 10654 | } |
316f5878 | 10655 | else |
fef14a42 | 10656 | arch_info = mips_cpu_info_from_isa (file_mips_isa); |
e9670677 MR |
10657 | } |
10658 | ||
fef14a42 TS |
10659 | if (arch_info == 0) |
10660 | arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT); | |
e9670677 | 10661 | |
fef14a42 | 10662 | if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa)) |
316f5878 | 10663 | as_bad ("-march=%s is not compatible with the selected ABI", |
fef14a42 TS |
10664 | arch_info->name); |
10665 | ||
10666 | mips_set_architecture (arch_info); | |
10667 | ||
10668 | /* Optimize for file_mips_arch, unless -mtune selects a different processor. */ | |
10669 | if (mips_tune_string != 0) | |
10670 | tune_info = mips_parse_cpu ("-mtune", mips_tune_string); | |
e9670677 | 10671 | |
fef14a42 TS |
10672 | if (tune_info == 0) |
10673 | mips_set_tune (arch_info); | |
10674 | else | |
10675 | mips_set_tune (tune_info); | |
e9670677 | 10676 | |
316f5878 | 10677 | if (file_mips_gp32 >= 0) |
e9670677 | 10678 | { |
316f5878 RS |
10679 | /* The user specified the size of the integer registers. Make sure |
10680 | it agrees with the ABI and ISA. */ | |
10681 | if (file_mips_gp32 == 0 && !ISA_HAS_64BIT_REGS (mips_opts.isa)) | |
10682 | as_bad (_("-mgp64 used with a 32-bit processor")); | |
10683 | else if (file_mips_gp32 == 1 && ABI_NEEDS_64BIT_REGS (mips_abi)) | |
10684 | as_bad (_("-mgp32 used with a 64-bit ABI")); | |
10685 | else if (file_mips_gp32 == 0 && ABI_NEEDS_32BIT_REGS (mips_abi)) | |
10686 | as_bad (_("-mgp64 used with a 32-bit ABI")); | |
e9670677 MR |
10687 | } |
10688 | else | |
10689 | { | |
316f5878 RS |
10690 | /* Infer the integer register size from the ABI and processor. |
10691 | Restrict ourselves to 32-bit registers if that's all the | |
10692 | processor has, or if the ABI cannot handle 64-bit registers. */ | |
10693 | file_mips_gp32 = (ABI_NEEDS_32BIT_REGS (mips_abi) | |
10694 | || !ISA_HAS_64BIT_REGS (mips_opts.isa)); | |
e9670677 MR |
10695 | } |
10696 | ||
316f5878 RS |
10697 | /* ??? GAS treats single-float processors as though they had 64-bit |
10698 | float registers (although it complains when double-precision | |
10699 | instructions are used). As things stand, saying they have 32-bit | |
10700 | registers would lead to spurious "register must be even" messages. | |
10701 | So here we assume float registers are always the same size as | |
10702 | integer ones, unless the user says otherwise. */ | |
10703 | if (file_mips_fp32 < 0) | |
10704 | file_mips_fp32 = file_mips_gp32; | |
e9670677 | 10705 | |
316f5878 | 10706 | /* End of GCC-shared inference code. */ |
e9670677 | 10707 | |
17a2f251 TS |
10708 | /* This flag is set when we have a 64-bit capable CPU but use only |
10709 | 32-bit wide registers. Note that EABI does not use it. */ | |
10710 | if (ISA_HAS_64BIT_REGS (mips_opts.isa) | |
10711 | && ((mips_abi == NO_ABI && file_mips_gp32 == 1) | |
10712 | || mips_abi == O32_ABI)) | |
316f5878 | 10713 | mips_32bitmode = 1; |
e9670677 MR |
10714 | |
10715 | if (mips_opts.isa == ISA_MIPS1 && mips_trap) | |
10716 | as_bad (_("trap exception not supported at ISA 1")); | |
10717 | ||
e9670677 MR |
10718 | /* If the selected architecture includes support for ASEs, enable |
10719 | generation of code for them. */ | |
a4672219 | 10720 | if (mips_opts.mips16 == -1) |
fef14a42 | 10721 | mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_arch)) ? 1 : 0; |
ffdefa66 | 10722 | if (mips_opts.ase_mips3d == -1) |
fef14a42 | 10723 | mips_opts.ase_mips3d = (CPU_HAS_MIPS3D (file_mips_arch)) ? 1 : 0; |
ffdefa66 | 10724 | if (mips_opts.ase_mdmx == -1) |
fef14a42 | 10725 | mips_opts.ase_mdmx = (CPU_HAS_MDMX (file_mips_arch)) ? 1 : 0; |
e9670677 | 10726 | |
e9670677 | 10727 | file_mips_isa = mips_opts.isa; |
a4672219 | 10728 | file_ase_mips16 = mips_opts.mips16; |
e9670677 MR |
10729 | file_ase_mips3d = mips_opts.ase_mips3d; |
10730 | file_ase_mdmx = mips_opts.ase_mdmx; | |
10731 | mips_opts.gp32 = file_mips_gp32; | |
10732 | mips_opts.fp32 = file_mips_fp32; | |
10733 | ||
ecb4347a DJ |
10734 | if (mips_flag_mdebug < 0) |
10735 | { | |
10736 | #ifdef OBJ_MAYBE_ECOFF | |
10737 | if (OUTPUT_FLAVOR == bfd_target_ecoff_flavour) | |
10738 | mips_flag_mdebug = 1; | |
10739 | else | |
10740 | #endif /* OBJ_MAYBE_ECOFF */ | |
10741 | mips_flag_mdebug = 0; | |
10742 | } | |
e9670677 MR |
10743 | } |
10744 | \f | |
10745 | void | |
17a2f251 | 10746 | mips_init_after_args (void) |
252b5132 RH |
10747 | { |
10748 | /* initialize opcodes */ | |
10749 | bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes; | |
beae10d5 | 10750 | mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes; |
252b5132 RH |
10751 | } |
10752 | ||
10753 | long | |
17a2f251 | 10754 | md_pcrel_from (fixS *fixP) |
252b5132 | 10755 | { |
a7ebbfdf TS |
10756 | valueT addr = fixP->fx_where + fixP->fx_frag->fr_address; |
10757 | switch (fixP->fx_r_type) | |
10758 | { | |
10759 | case BFD_RELOC_16_PCREL_S2: | |
10760 | case BFD_RELOC_MIPS_JMP: | |
10761 | /* Return the address of the delay slot. */ | |
10762 | return addr + 4; | |
10763 | default: | |
10764 | return addr; | |
10765 | } | |
252b5132 RH |
10766 | } |
10767 | ||
252b5132 RH |
10768 | /* This is called before the symbol table is processed. In order to |
10769 | work with gcc when using mips-tfile, we must keep all local labels. | |
10770 | However, in other cases, we want to discard them. If we were | |
10771 | called with -g, but we didn't see any debugging information, it may | |
10772 | mean that gcc is smuggling debugging information through to | |
10773 | mips-tfile, in which case we must generate all local labels. */ | |
10774 | ||
10775 | void | |
17a2f251 | 10776 | mips_frob_file_before_adjust (void) |
252b5132 RH |
10777 | { |
10778 | #ifndef NO_ECOFF_DEBUGGING | |
10779 | if (ECOFF_DEBUGGING | |
10780 | && mips_debug != 0 | |
10781 | && ! ecoff_debugging_seen) | |
10782 | flag_keep_locals = 1; | |
10783 | #endif | |
10784 | } | |
10785 | ||
3b91255e RS |
10786 | /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede |
10787 | the corresponding LO16 reloc. This is called before md_apply_fix3 and | |
10788 | tc_gen_reloc. Unmatched relocs can only be generated by use of explicit | |
10789 | relocation operators. | |
10790 | ||
10791 | For our purposes, a %lo() expression matches a %got() or %hi() | |
10792 | expression if: | |
10793 | ||
10794 | (a) it refers to the same symbol; and | |
10795 | (b) the offset applied in the %lo() expression is no lower than | |
10796 | the offset applied in the %got() or %hi(). | |
10797 | ||
10798 | (b) allows us to cope with code like: | |
10799 | ||
10800 | lui $4,%hi(foo) | |
10801 | lh $4,%lo(foo+2)($4) | |
10802 | ||
10803 | ...which is legal on RELA targets, and has a well-defined behaviour | |
10804 | if the user knows that adding 2 to "foo" will not induce a carry to | |
10805 | the high 16 bits. | |
10806 | ||
10807 | When several %lo()s match a particular %got() or %hi(), we use the | |
10808 | following rules to distinguish them: | |
10809 | ||
10810 | (1) %lo()s with smaller offsets are a better match than %lo()s with | |
10811 | higher offsets. | |
10812 | ||
10813 | (2) %lo()s with no matching %got() or %hi() are better than those | |
10814 | that already have a matching %got() or %hi(). | |
10815 | ||
10816 | (3) later %lo()s are better than earlier %lo()s. | |
10817 | ||
10818 | These rules are applied in order. | |
10819 | ||
10820 | (1) means, among other things, that %lo()s with identical offsets are | |
10821 | chosen if they exist. | |
10822 | ||
10823 | (2) means that we won't associate several high-part relocations with | |
10824 | the same low-part relocation unless there's no alternative. Having | |
10825 | several high parts for the same low part is a GNU extension; this rule | |
10826 | allows careful users to avoid it. | |
10827 | ||
10828 | (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order, | |
10829 | with the last high-part relocation being at the front of the list. | |
10830 | It therefore makes sense to choose the last matching low-part | |
10831 | relocation, all other things being equal. It's also easier | |
10832 | to code that way. */ | |
252b5132 RH |
10833 | |
10834 | void | |
17a2f251 | 10835 | mips_frob_file (void) |
252b5132 RH |
10836 | { |
10837 | struct mips_hi_fixup *l; | |
10838 | ||
10839 | for (l = mips_hi_fixup_list; l != NULL; l = l->next) | |
10840 | { | |
10841 | segment_info_type *seginfo; | |
3b91255e RS |
10842 | bfd_boolean matched_lo_p; |
10843 | fixS **hi_pos, **lo_pos, **pos; | |
252b5132 | 10844 | |
5919d012 | 10845 | assert (reloc_needs_lo_p (l->fixp->fx_r_type)); |
252b5132 | 10846 | |
5919d012 RS |
10847 | /* If a GOT16 relocation turns out to be against a global symbol, |
10848 | there isn't supposed to be a matching LO. */ | |
10849 | if (l->fixp->fx_r_type == BFD_RELOC_MIPS_GOT16 | |
10850 | && !pic_need_relax (l->fixp->fx_addsy, l->seg)) | |
10851 | continue; | |
10852 | ||
10853 | /* Check quickly whether the next fixup happens to be a matching %lo. */ | |
10854 | if (fixup_has_matching_lo_p (l->fixp)) | |
252b5132 RH |
10855 | continue; |
10856 | ||
252b5132 | 10857 | seginfo = seg_info (l->seg); |
252b5132 | 10858 | |
3b91255e RS |
10859 | /* Set HI_POS to the position of this relocation in the chain. |
10860 | Set LO_POS to the position of the chosen low-part relocation. | |
10861 | MATCHED_LO_P is true on entry to the loop if *POS is a low-part | |
10862 | relocation that matches an immediately-preceding high-part | |
10863 | relocation. */ | |
10864 | hi_pos = NULL; | |
10865 | lo_pos = NULL; | |
10866 | matched_lo_p = FALSE; | |
10867 | for (pos = &seginfo->fix_root; *pos != NULL; pos = &(*pos)->fx_next) | |
10868 | { | |
10869 | if (*pos == l->fixp) | |
10870 | hi_pos = pos; | |
10871 | ||
10872 | if ((*pos)->fx_r_type == BFD_RELOC_LO16 | |
10873 | && (*pos)->fx_addsy == l->fixp->fx_addsy | |
10874 | && (*pos)->fx_offset >= l->fixp->fx_offset | |
10875 | && (lo_pos == NULL | |
10876 | || (*pos)->fx_offset < (*lo_pos)->fx_offset | |
10877 | || (!matched_lo_p | |
10878 | && (*pos)->fx_offset == (*lo_pos)->fx_offset))) | |
10879 | lo_pos = pos; | |
10880 | ||
10881 | matched_lo_p = (reloc_needs_lo_p ((*pos)->fx_r_type) | |
10882 | && fixup_has_matching_lo_p (*pos)); | |
10883 | } | |
10884 | ||
10885 | /* If we found a match, remove the high-part relocation from its | |
10886 | current position and insert it before the low-part relocation. | |
10887 | Make the offsets match so that fixup_has_matching_lo_p() | |
10888 | will return true. | |
10889 | ||
10890 | We don't warn about unmatched high-part relocations since some | |
10891 | versions of gcc have been known to emit dead "lui ...%hi(...)" | |
10892 | instructions. */ | |
10893 | if (lo_pos != NULL) | |
10894 | { | |
10895 | l->fixp->fx_offset = (*lo_pos)->fx_offset; | |
10896 | if (l->fixp->fx_next != *lo_pos) | |
252b5132 | 10897 | { |
3b91255e RS |
10898 | *hi_pos = l->fixp->fx_next; |
10899 | l->fixp->fx_next = *lo_pos; | |
10900 | *lo_pos = l->fixp; | |
252b5132 | 10901 | } |
252b5132 RH |
10902 | } |
10903 | } | |
10904 | } | |
10905 | ||
3e722fb5 | 10906 | /* We may have combined relocations without symbols in the N32/N64 ABI. |
f6688943 | 10907 | We have to prevent gas from dropping them. */ |
252b5132 | 10908 | |
252b5132 | 10909 | int |
17a2f251 | 10910 | mips_force_relocation (fixS *fixp) |
252b5132 | 10911 | { |
ae6063d4 | 10912 | if (generic_force_reloc (fixp)) |
252b5132 RH |
10913 | return 1; |
10914 | ||
f6688943 TS |
10915 | if (HAVE_NEWABI |
10916 | && S_GET_SEGMENT (fixp->fx_addsy) == bfd_abs_section_ptr | |
10917 | && (fixp->fx_r_type == BFD_RELOC_MIPS_SUB | |
10918 | || fixp->fx_r_type == BFD_RELOC_HI16_S | |
10919 | || fixp->fx_r_type == BFD_RELOC_LO16)) | |
10920 | return 1; | |
10921 | ||
3e722fb5 | 10922 | return 0; |
252b5132 RH |
10923 | } |
10924 | ||
45f8dfe8 AO |
10925 | /* This hook is called before a fix is simplified. We don't really |
10926 | decide whether to skip a fix here. Rather, we turn global symbols | |
10927 | used as branch targets into local symbols, such that they undergo | |
10928 | simplification. We can only do this if the symbol is defined and | |
10929 | it is in the same section as the branch. If this doesn't hold, we | |
10930 | emit a better error message than just saying the relocation is not | |
10931 | valid for the selected object format. | |
10932 | ||
10933 | FIXP is the fix-up we're going to try to simplify, SEG is the | |
10934 | segment in which the fix up occurs. The return value should be | |
10935 | non-zero to indicate the fix-up is valid for further | |
10936 | simplifications. */ | |
10937 | ||
10938 | int | |
17a2f251 | 10939 | mips_validate_fix (struct fix *fixP, asection *seg) |
45f8dfe8 AO |
10940 | { |
10941 | /* There's a lot of discussion on whether it should be possible to | |
10942 | use R_MIPS_PC16 to represent branch relocations. The outcome | |
10943 | seems to be that it can, but gas/bfd are very broken in creating | |
10944 | RELA relocations for this, so for now we only accept branches to | |
10945 | symbols in the same section. Anything else is of dubious value, | |
10946 | since there's no guarantee that at link time the symbol would be | |
10947 | in range. Even for branches to local symbols this is arguably | |
10948 | wrong, since it we assume the symbol is not going to be | |
10949 | overridden, which should be possible per ELF library semantics, | |
10950 | but then, there isn't a dynamic relocation that could be used to | |
10951 | this effect, and the target would likely be out of range as well. | |
10952 | ||
10953 | Unfortunately, it seems that there is too much code out there | |
10954 | that relies on branches to symbols that are global to be resolved | |
10955 | as if they were local, like the IRIX tools do, so we do it as | |
10956 | well, but with a warning so that people are reminded to fix their | |
10957 | code. If we ever get back to using R_MIPS_PC16 for branch | |
10958 | targets, this entire block should go away (and probably the | |
10959 | whole function). */ | |
10960 | ||
10961 | if (fixP->fx_r_type == BFD_RELOC_16_PCREL_S2 | |
3e722fb5 CD |
10962 | && ((OUTPUT_FLAVOR == bfd_target_ecoff_flavour |
10963 | || OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
45f8dfe8 AO |
10964 | || bfd_reloc_type_lookup (stdoutput, BFD_RELOC_16_PCREL_S2) == NULL) |
10965 | && fixP->fx_addsy) | |
10966 | { | |
10967 | if (! S_IS_DEFINED (fixP->fx_addsy)) | |
10968 | { | |
10969 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
10970 | _("Cannot branch to undefined symbol.")); | |
10971 | /* Avoid any further errors about this fixup. */ | |
10972 | fixP->fx_done = 1; | |
10973 | } | |
10974 | else if (S_GET_SEGMENT (fixP->fx_addsy) != seg) | |
10975 | { | |
10976 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
10977 | _("Cannot branch to symbol in another section.")); | |
10978 | fixP->fx_done = 1; | |
10979 | } | |
10980 | else if (S_IS_EXTERNAL (fixP->fx_addsy)) | |
10981 | { | |
10982 | symbolS *sym = fixP->fx_addsy; | |
10983 | ||
115695a8 CD |
10984 | if (mips_pic == SVR4_PIC) |
10985 | as_warn_where (fixP->fx_file, fixP->fx_line, | |
10986 | _("Pretending global symbol used as branch target is local.")); | |
45f8dfe8 AO |
10987 | |
10988 | fixP->fx_addsy = symbol_create (S_GET_NAME (sym), | |
10989 | S_GET_SEGMENT (sym), | |
10990 | S_GET_VALUE (sym), | |
10991 | symbol_get_frag (sym)); | |
10992 | copy_symbol_attributes (fixP->fx_addsy, sym); | |
10993 | S_CLEAR_EXTERNAL (fixP->fx_addsy); | |
10994 | assert (symbol_resolved_p (sym)); | |
10995 | symbol_mark_resolved (fixP->fx_addsy); | |
10996 | } | |
10997 | } | |
10998 | ||
10999 | return 1; | |
11000 | } | |
11001 | ||
252b5132 RH |
11002 | /* Apply a fixup to the object file. */ |
11003 | ||
94f592af | 11004 | void |
17a2f251 | 11005 | md_apply_fix3 (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) |
252b5132 | 11006 | { |
874e8986 | 11007 | bfd_byte *buf; |
98aa84af | 11008 | long insn; |
a7ebbfdf | 11009 | reloc_howto_type *howto; |
252b5132 | 11010 | |
a7ebbfdf TS |
11011 | /* We ignore generic BFD relocations we don't know about. */ |
11012 | howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type); | |
11013 | if (! howto) | |
11014 | return; | |
65551fa4 | 11015 | |
252b5132 RH |
11016 | assert (fixP->fx_size == 4 |
11017 | || fixP->fx_r_type == BFD_RELOC_16 | |
11018 | || fixP->fx_r_type == BFD_RELOC_64 | |
f6688943 TS |
11019 | || fixP->fx_r_type == BFD_RELOC_CTOR |
11020 | || fixP->fx_r_type == BFD_RELOC_MIPS_SUB | |
252b5132 | 11021 | || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
a7ebbfdf | 11022 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY); |
252b5132 | 11023 | |
a7ebbfdf | 11024 | buf = (bfd_byte *) (fixP->fx_frag->fr_literal + fixP->fx_where); |
252b5132 | 11025 | |
3e722fb5 | 11026 | assert (! fixP->fx_pcrel); |
b1dca8ee RS |
11027 | |
11028 | /* Don't treat parts of a composite relocation as done. There are two | |
11029 | reasons for this: | |
11030 | ||
11031 | (1) The second and third parts will be against 0 (RSS_UNDEF) but | |
11032 | should nevertheless be emitted if the first part is. | |
11033 | ||
11034 | (2) In normal usage, composite relocations are never assembly-time | |
11035 | constants. The easiest way of dealing with the pathological | |
11036 | exceptions is to generate a relocation against STN_UNDEF and | |
11037 | leave everything up to the linker. */ | |
11038 | if (fixP->fx_addsy == NULL && fixP->fx_tcbit == 0) | |
252b5132 RH |
11039 | fixP->fx_done = 1; |
11040 | ||
11041 | switch (fixP->fx_r_type) | |
11042 | { | |
3f98094e DJ |
11043 | case BFD_RELOC_MIPS_TLS_GD: |
11044 | case BFD_RELOC_MIPS_TLS_LDM: | |
11045 | case BFD_RELOC_MIPS_TLS_DTPREL_HI16: | |
11046 | case BFD_RELOC_MIPS_TLS_DTPREL_LO16: | |
11047 | case BFD_RELOC_MIPS_TLS_GOTTPREL: | |
11048 | case BFD_RELOC_MIPS_TLS_TPREL_HI16: | |
11049 | case BFD_RELOC_MIPS_TLS_TPREL_LO16: | |
11050 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
11051 | /* fall through */ | |
11052 | ||
252b5132 | 11053 | case BFD_RELOC_MIPS_JMP: |
e369bcce TS |
11054 | case BFD_RELOC_MIPS_SHIFT5: |
11055 | case BFD_RELOC_MIPS_SHIFT6: | |
11056 | case BFD_RELOC_MIPS_GOT_DISP: | |
11057 | case BFD_RELOC_MIPS_GOT_PAGE: | |
11058 | case BFD_RELOC_MIPS_GOT_OFST: | |
11059 | case BFD_RELOC_MIPS_SUB: | |
11060 | case BFD_RELOC_MIPS_INSERT_A: | |
11061 | case BFD_RELOC_MIPS_INSERT_B: | |
11062 | case BFD_RELOC_MIPS_DELETE: | |
11063 | case BFD_RELOC_MIPS_HIGHEST: | |
11064 | case BFD_RELOC_MIPS_HIGHER: | |
11065 | case BFD_RELOC_MIPS_SCN_DISP: | |
11066 | case BFD_RELOC_MIPS_REL16: | |
11067 | case BFD_RELOC_MIPS_RELGOT: | |
11068 | case BFD_RELOC_MIPS_JALR: | |
252b5132 RH |
11069 | case BFD_RELOC_HI16: |
11070 | case BFD_RELOC_HI16_S: | |
cdf6fd85 | 11071 | case BFD_RELOC_GPREL16: |
252b5132 RH |
11072 | case BFD_RELOC_MIPS_LITERAL: |
11073 | case BFD_RELOC_MIPS_CALL16: | |
11074 | case BFD_RELOC_MIPS_GOT16: | |
cdf6fd85 | 11075 | case BFD_RELOC_GPREL32: |
252b5132 RH |
11076 | case BFD_RELOC_MIPS_GOT_HI16: |
11077 | case BFD_RELOC_MIPS_GOT_LO16: | |
11078 | case BFD_RELOC_MIPS_CALL_HI16: | |
11079 | case BFD_RELOC_MIPS_CALL_LO16: | |
11080 | case BFD_RELOC_MIPS16_GPREL: | |
d6f16593 MR |
11081 | case BFD_RELOC_MIPS16_HI16: |
11082 | case BFD_RELOC_MIPS16_HI16_S: | |
3e722fb5 | 11083 | assert (! fixP->fx_pcrel); |
252b5132 RH |
11084 | /* Nothing needed to do. The value comes from the reloc entry */ |
11085 | break; | |
11086 | ||
11087 | case BFD_RELOC_MIPS16_JMP: | |
11088 | /* We currently always generate a reloc against a symbol, which | |
11089 | means that we don't want an addend even if the symbol is | |
11090 | defined. */ | |
a7ebbfdf | 11091 | *valP = 0; |
252b5132 RH |
11092 | break; |
11093 | ||
252b5132 RH |
11094 | case BFD_RELOC_64: |
11095 | /* This is handled like BFD_RELOC_32, but we output a sign | |
11096 | extended value if we are only 32 bits. */ | |
3e722fb5 | 11097 | if (fixP->fx_done) |
252b5132 RH |
11098 | { |
11099 | if (8 <= sizeof (valueT)) | |
2132e3a3 | 11100 | md_number_to_chars ((char *) buf, *valP, 8); |
252b5132 RH |
11101 | else |
11102 | { | |
a7ebbfdf | 11103 | valueT hiv; |
252b5132 | 11104 | |
a7ebbfdf | 11105 | if ((*valP & 0x80000000) != 0) |
252b5132 RH |
11106 | hiv = 0xffffffff; |
11107 | else | |
11108 | hiv = 0; | |
a7ebbfdf TS |
11109 | md_number_to_chars ((char *)(buf + target_big_endian ? 4 : 0), |
11110 | *valP, 4); | |
11111 | md_number_to_chars ((char *)(buf + target_big_endian ? 0 : 4), | |
11112 | hiv, 4); | |
252b5132 RH |
11113 | } |
11114 | } | |
11115 | break; | |
11116 | ||
056350c6 | 11117 | case BFD_RELOC_RVA: |
252b5132 RH |
11118 | case BFD_RELOC_32: |
11119 | /* If we are deleting this reloc entry, we must fill in the | |
11120 | value now. This can happen if we have a .word which is not | |
3e722fb5 CD |
11121 | resolved when it appears but is later defined. */ |
11122 | if (fixP->fx_done) | |
2132e3a3 | 11123 | md_number_to_chars ((char *) buf, *valP, 4); |
252b5132 RH |
11124 | break; |
11125 | ||
11126 | case BFD_RELOC_16: | |
11127 | /* If we are deleting this reloc entry, we must fill in the | |
11128 | value now. */ | |
252b5132 | 11129 | if (fixP->fx_done) |
2132e3a3 | 11130 | md_number_to_chars ((char *) buf, *valP, 2); |
252b5132 RH |
11131 | break; |
11132 | ||
11133 | case BFD_RELOC_LO16: | |
d6f16593 | 11134 | case BFD_RELOC_MIPS16_LO16: |
3e722fb5 CD |
11135 | /* FIXME: Now that embedded-PIC is gone, some of this code/comment |
11136 | may be safe to remove, but if so it's not obvious. */ | |
252b5132 RH |
11137 | /* When handling an embedded PIC switch statement, we can wind |
11138 | up deleting a LO16 reloc. See the 'o' case in mips_ip. */ | |
11139 | if (fixP->fx_done) | |
11140 | { | |
a7ebbfdf | 11141 | if (*valP + 0x8000 > 0xffff) |
252b5132 RH |
11142 | as_bad_where (fixP->fx_file, fixP->fx_line, |
11143 | _("relocation overflow")); | |
252b5132 RH |
11144 | if (target_big_endian) |
11145 | buf += 2; | |
2132e3a3 | 11146 | md_number_to_chars ((char *) buf, *valP, 2); |
252b5132 RH |
11147 | } |
11148 | break; | |
11149 | ||
11150 | case BFD_RELOC_16_PCREL_S2: | |
a7ebbfdf | 11151 | if ((*valP & 0x3) != 0) |
cb56d3d3 | 11152 | as_bad_where (fixP->fx_file, fixP->fx_line, |
a7ebbfdf | 11153 | _("Branch to odd address (%lx)"), (long) *valP); |
cb56d3d3 | 11154 | |
252b5132 RH |
11155 | /* |
11156 | * We need to save the bits in the instruction since fixup_segment() | |
11157 | * might be deleting the relocation entry (i.e., a branch within | |
11158 | * the current segment). | |
11159 | */ | |
a7ebbfdf | 11160 | if (! fixP->fx_done) |
bb2d6cd7 | 11161 | break; |
252b5132 RH |
11162 | |
11163 | /* update old instruction data */ | |
252b5132 RH |
11164 | if (target_big_endian) |
11165 | insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3]; | |
11166 | else | |
11167 | insn = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0]; | |
11168 | ||
a7ebbfdf TS |
11169 | if (*valP + 0x20000 <= 0x3ffff) |
11170 | { | |
11171 | insn |= (*valP >> 2) & 0xffff; | |
2132e3a3 | 11172 | md_number_to_chars ((char *) buf, insn, 4); |
a7ebbfdf TS |
11173 | } |
11174 | else if (mips_pic == NO_PIC | |
11175 | && fixP->fx_done | |
11176 | && fixP->fx_frag->fr_address >= text_section->vma | |
11177 | && (fixP->fx_frag->fr_address | |
587aac4e | 11178 | < text_section->vma + bfd_get_section_size (text_section)) |
a7ebbfdf TS |
11179 | && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */ |
11180 | || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */ | |
11181 | || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */ | |
252b5132 RH |
11182 | { |
11183 | /* The branch offset is too large. If this is an | |
11184 | unconditional branch, and we are not generating PIC code, | |
11185 | we can convert it to an absolute jump instruction. */ | |
a7ebbfdf TS |
11186 | if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */ |
11187 | insn = 0x0c000000; /* jal */ | |
252b5132 | 11188 | else |
a7ebbfdf TS |
11189 | insn = 0x08000000; /* j */ |
11190 | fixP->fx_r_type = BFD_RELOC_MIPS_JMP; | |
11191 | fixP->fx_done = 0; | |
11192 | fixP->fx_addsy = section_symbol (text_section); | |
11193 | *valP += md_pcrel_from (fixP); | |
2132e3a3 | 11194 | md_number_to_chars ((char *) buf, insn, 4); |
a7ebbfdf TS |
11195 | } |
11196 | else | |
11197 | { | |
11198 | /* If we got here, we have branch-relaxation disabled, | |
11199 | and there's nothing we can do to fix this instruction | |
11200 | without turning it into a longer sequence. */ | |
11201 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11202 | _("Branch out of range")); | |
252b5132 | 11203 | } |
252b5132 RH |
11204 | break; |
11205 | ||
11206 | case BFD_RELOC_VTABLE_INHERIT: | |
11207 | fixP->fx_done = 0; | |
11208 | if (fixP->fx_addsy | |
11209 | && !S_IS_DEFINED (fixP->fx_addsy) | |
11210 | && !S_IS_WEAK (fixP->fx_addsy)) | |
11211 | S_SET_WEAK (fixP->fx_addsy); | |
11212 | break; | |
11213 | ||
11214 | case BFD_RELOC_VTABLE_ENTRY: | |
11215 | fixP->fx_done = 0; | |
11216 | break; | |
11217 | ||
11218 | default: | |
11219 | internalError (); | |
11220 | } | |
a7ebbfdf TS |
11221 | |
11222 | /* Remember value for tc_gen_reloc. */ | |
11223 | fixP->fx_addnumber = *valP; | |
252b5132 RH |
11224 | } |
11225 | ||
252b5132 | 11226 | static symbolS * |
17a2f251 | 11227 | get_symbol (void) |
252b5132 RH |
11228 | { |
11229 | int c; | |
11230 | char *name; | |
11231 | symbolS *p; | |
11232 | ||
11233 | name = input_line_pointer; | |
11234 | c = get_symbol_end (); | |
11235 | p = (symbolS *) symbol_find_or_make (name); | |
11236 | *input_line_pointer = c; | |
11237 | return p; | |
11238 | } | |
11239 | ||
11240 | /* Align the current frag to a given power of two. The MIPS assembler | |
11241 | also automatically adjusts any preceding label. */ | |
11242 | ||
11243 | static void | |
17a2f251 | 11244 | mips_align (int to, int fill, symbolS *label) |
252b5132 | 11245 | { |
b34976b6 | 11246 | mips_emit_delays (FALSE); |
252b5132 RH |
11247 | frag_align (to, fill, 0); |
11248 | record_alignment (now_seg, to); | |
11249 | if (label != NULL) | |
11250 | { | |
11251 | assert (S_GET_SEGMENT (label) == now_seg); | |
49309057 | 11252 | symbol_set_frag (label, frag_now); |
252b5132 RH |
11253 | S_SET_VALUE (label, (valueT) frag_now_fix ()); |
11254 | } | |
11255 | } | |
11256 | ||
11257 | /* Align to a given power of two. .align 0 turns off the automatic | |
11258 | alignment used by the data creating pseudo-ops. */ | |
11259 | ||
11260 | static void | |
17a2f251 | 11261 | s_align (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
11262 | { |
11263 | register int temp; | |
11264 | register long temp_fill; | |
11265 | long max_alignment = 15; | |
11266 | ||
11267 | /* | |
11268 | ||
67c1ffbe | 11269 | o Note that the assembler pulls down any immediately preceding label |
252b5132 RH |
11270 | to the aligned address. |
11271 | o It's not documented but auto alignment is reinstated by | |
11272 | a .align pseudo instruction. | |
11273 | o Note also that after auto alignment is turned off the mips assembler | |
11274 | issues an error on attempt to assemble an improperly aligned data item. | |
11275 | We don't. | |
11276 | ||
11277 | */ | |
11278 | ||
11279 | temp = get_absolute_expression (); | |
11280 | if (temp > max_alignment) | |
11281 | as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment); | |
11282 | else if (temp < 0) | |
11283 | { | |
11284 | as_warn (_("Alignment negative: 0 assumed.")); | |
11285 | temp = 0; | |
11286 | } | |
11287 | if (*input_line_pointer == ',') | |
11288 | { | |
f9419b05 | 11289 | ++input_line_pointer; |
252b5132 RH |
11290 | temp_fill = get_absolute_expression (); |
11291 | } | |
11292 | else | |
11293 | temp_fill = 0; | |
11294 | if (temp) | |
11295 | { | |
11296 | auto_align = 1; | |
11297 | mips_align (temp, (int) temp_fill, | |
11298 | insn_labels != NULL ? insn_labels->label : NULL); | |
11299 | } | |
11300 | else | |
11301 | { | |
11302 | auto_align = 0; | |
11303 | } | |
11304 | ||
11305 | demand_empty_rest_of_line (); | |
11306 | } | |
11307 | ||
11308 | void | |
17a2f251 | 11309 | mips_flush_pending_output (void) |
252b5132 | 11310 | { |
b34976b6 | 11311 | mips_emit_delays (FALSE); |
252b5132 RH |
11312 | mips_clear_insn_labels (); |
11313 | } | |
11314 | ||
11315 | static void | |
17a2f251 | 11316 | s_change_sec (int sec) |
252b5132 RH |
11317 | { |
11318 | segT seg; | |
11319 | ||
252b5132 RH |
11320 | #ifdef OBJ_ELF |
11321 | /* The ELF backend needs to know that we are changing sections, so | |
11322 | that .previous works correctly. We could do something like check | |
b6ff326e | 11323 | for an obj_section_change_hook macro, but that might be confusing |
252b5132 RH |
11324 | as it would not be appropriate to use it in the section changing |
11325 | functions in read.c, since obj-elf.c intercepts those. FIXME: | |
11326 | This should be cleaner, somehow. */ | |
11327 | obj_elf_section_change_hook (); | |
11328 | #endif | |
11329 | ||
b34976b6 | 11330 | mips_emit_delays (FALSE); |
252b5132 RH |
11331 | switch (sec) |
11332 | { | |
11333 | case 't': | |
11334 | s_text (0); | |
11335 | break; | |
11336 | case 'd': | |
11337 | s_data (0); | |
11338 | break; | |
11339 | case 'b': | |
11340 | subseg_set (bss_section, (subsegT) get_absolute_expression ()); | |
11341 | demand_empty_rest_of_line (); | |
11342 | break; | |
11343 | ||
11344 | case 'r': | |
4d0d148d TS |
11345 | seg = subseg_new (RDATA_SECTION_NAME, |
11346 | (subsegT) get_absolute_expression ()); | |
11347 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
252b5132 | 11348 | { |
4d0d148d TS |
11349 | bfd_set_section_flags (stdoutput, seg, (SEC_ALLOC | SEC_LOAD |
11350 | | SEC_READONLY | SEC_RELOC | |
11351 | | SEC_DATA)); | |
11352 | if (strcmp (TARGET_OS, "elf") != 0) | |
11353 | record_alignment (seg, 4); | |
252b5132 | 11354 | } |
4d0d148d | 11355 | demand_empty_rest_of_line (); |
252b5132 RH |
11356 | break; |
11357 | ||
11358 | case 's': | |
4d0d148d TS |
11359 | seg = subseg_new (".sdata", (subsegT) get_absolute_expression ()); |
11360 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
252b5132 | 11361 | { |
4d0d148d TS |
11362 | bfd_set_section_flags (stdoutput, seg, |
11363 | SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA); | |
11364 | if (strcmp (TARGET_OS, "elf") != 0) | |
11365 | record_alignment (seg, 4); | |
252b5132 | 11366 | } |
4d0d148d TS |
11367 | demand_empty_rest_of_line (); |
11368 | break; | |
252b5132 RH |
11369 | } |
11370 | ||
11371 | auto_align = 1; | |
11372 | } | |
b34976b6 | 11373 | |
cca86cc8 | 11374 | void |
17a2f251 | 11375 | s_change_section (int ignore ATTRIBUTE_UNUSED) |
cca86cc8 | 11376 | { |
7ed4a06a | 11377 | #ifdef OBJ_ELF |
cca86cc8 SC |
11378 | char *section_name; |
11379 | char c; | |
684022ea | 11380 | char next_c = 0; |
cca86cc8 SC |
11381 | int section_type; |
11382 | int section_flag; | |
11383 | int section_entry_size; | |
11384 | int section_alignment; | |
b34976b6 | 11385 | |
7ed4a06a TS |
11386 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
11387 | return; | |
11388 | ||
cca86cc8 SC |
11389 | section_name = input_line_pointer; |
11390 | c = get_symbol_end (); | |
a816d1ed AO |
11391 | if (c) |
11392 | next_c = *(input_line_pointer + 1); | |
cca86cc8 | 11393 | |
4cf0dd0d TS |
11394 | /* Do we have .section Name<,"flags">? */ |
11395 | if (c != ',' || (c == ',' && next_c == '"')) | |
cca86cc8 | 11396 | { |
4cf0dd0d TS |
11397 | /* just after name is now '\0'. */ |
11398 | *input_line_pointer = c; | |
cca86cc8 SC |
11399 | input_line_pointer = section_name; |
11400 | obj_elf_section (ignore); | |
11401 | return; | |
11402 | } | |
11403 | input_line_pointer++; | |
11404 | ||
11405 | /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */ | |
11406 | if (c == ',') | |
11407 | section_type = get_absolute_expression (); | |
11408 | else | |
11409 | section_type = 0; | |
11410 | if (*input_line_pointer++ == ',') | |
11411 | section_flag = get_absolute_expression (); | |
11412 | else | |
11413 | section_flag = 0; | |
11414 | if (*input_line_pointer++ == ',') | |
11415 | section_entry_size = get_absolute_expression (); | |
11416 | else | |
11417 | section_entry_size = 0; | |
11418 | if (*input_line_pointer++ == ',') | |
11419 | section_alignment = get_absolute_expression (); | |
11420 | else | |
11421 | section_alignment = 0; | |
11422 | ||
a816d1ed AO |
11423 | section_name = xstrdup (section_name); |
11424 | ||
8ab8a5c8 RS |
11425 | /* When using the generic form of .section (as implemented by obj-elf.c), |
11426 | there's no way to set the section type to SHT_MIPS_DWARF. Users have | |
11427 | traditionally had to fall back on the more common @progbits instead. | |
11428 | ||
11429 | There's nothing really harmful in this, since bfd will correct | |
11430 | SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it | |
11431 | means that, for backwards compatibiltiy, the special_section entries | |
11432 | for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF. | |
11433 | ||
11434 | Even so, we shouldn't force users of the MIPS .section syntax to | |
11435 | incorrectly label the sections as SHT_PROGBITS. The best compromise | |
11436 | seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the | |
11437 | generic type-checking code. */ | |
11438 | if (section_type == SHT_MIPS_DWARF) | |
11439 | section_type = SHT_PROGBITS; | |
11440 | ||
cca86cc8 SC |
11441 | obj_elf_change_section (section_name, section_type, section_flag, |
11442 | section_entry_size, 0, 0, 0); | |
a816d1ed AO |
11443 | |
11444 | if (now_seg->name != section_name) | |
11445 | free (section_name); | |
7ed4a06a | 11446 | #endif /* OBJ_ELF */ |
cca86cc8 | 11447 | } |
252b5132 RH |
11448 | |
11449 | void | |
17a2f251 | 11450 | mips_enable_auto_align (void) |
252b5132 RH |
11451 | { |
11452 | auto_align = 1; | |
11453 | } | |
11454 | ||
11455 | static void | |
17a2f251 | 11456 | s_cons (int log_size) |
252b5132 RH |
11457 | { |
11458 | symbolS *label; | |
11459 | ||
11460 | label = insn_labels != NULL ? insn_labels->label : NULL; | |
b34976b6 | 11461 | mips_emit_delays (FALSE); |
252b5132 RH |
11462 | if (log_size > 0 && auto_align) |
11463 | mips_align (log_size, 0, label); | |
11464 | mips_clear_insn_labels (); | |
11465 | cons (1 << log_size); | |
11466 | } | |
11467 | ||
11468 | static void | |
17a2f251 | 11469 | s_float_cons (int type) |
252b5132 RH |
11470 | { |
11471 | symbolS *label; | |
11472 | ||
11473 | label = insn_labels != NULL ? insn_labels->label : NULL; | |
11474 | ||
b34976b6 | 11475 | mips_emit_delays (FALSE); |
252b5132 RH |
11476 | |
11477 | if (auto_align) | |
49309057 ILT |
11478 | { |
11479 | if (type == 'd') | |
11480 | mips_align (3, 0, label); | |
11481 | else | |
11482 | mips_align (2, 0, label); | |
11483 | } | |
252b5132 RH |
11484 | |
11485 | mips_clear_insn_labels (); | |
11486 | ||
11487 | float_cons (type); | |
11488 | } | |
11489 | ||
11490 | /* Handle .globl. We need to override it because on Irix 5 you are | |
11491 | permitted to say | |
11492 | .globl foo .text | |
11493 | where foo is an undefined symbol, to mean that foo should be | |
11494 | considered to be the address of a function. */ | |
11495 | ||
11496 | static void | |
17a2f251 | 11497 | s_mips_globl (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
11498 | { |
11499 | char *name; | |
11500 | int c; | |
11501 | symbolS *symbolP; | |
11502 | flagword flag; | |
11503 | ||
11504 | name = input_line_pointer; | |
11505 | c = get_symbol_end (); | |
11506 | symbolP = symbol_find_or_make (name); | |
11507 | *input_line_pointer = c; | |
11508 | SKIP_WHITESPACE (); | |
11509 | ||
11510 | /* On Irix 5, every global symbol that is not explicitly labelled as | |
11511 | being a function is apparently labelled as being an object. */ | |
11512 | flag = BSF_OBJECT; | |
11513 | ||
11514 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
11515 | { | |
11516 | char *secname; | |
11517 | asection *sec; | |
11518 | ||
11519 | secname = input_line_pointer; | |
11520 | c = get_symbol_end (); | |
11521 | sec = bfd_get_section_by_name (stdoutput, secname); | |
11522 | if (sec == NULL) | |
11523 | as_bad (_("%s: no such section"), secname); | |
11524 | *input_line_pointer = c; | |
11525 | ||
11526 | if (sec != NULL && (sec->flags & SEC_CODE) != 0) | |
11527 | flag = BSF_FUNCTION; | |
11528 | } | |
11529 | ||
49309057 | 11530 | symbol_get_bfdsym (symbolP)->flags |= flag; |
252b5132 RH |
11531 | |
11532 | S_SET_EXTERNAL (symbolP); | |
11533 | demand_empty_rest_of_line (); | |
11534 | } | |
11535 | ||
11536 | static void | |
17a2f251 | 11537 | s_option (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
11538 | { |
11539 | char *opt; | |
11540 | char c; | |
11541 | ||
11542 | opt = input_line_pointer; | |
11543 | c = get_symbol_end (); | |
11544 | ||
11545 | if (*opt == 'O') | |
11546 | { | |
11547 | /* FIXME: What does this mean? */ | |
11548 | } | |
11549 | else if (strncmp (opt, "pic", 3) == 0) | |
11550 | { | |
11551 | int i; | |
11552 | ||
11553 | i = atoi (opt + 3); | |
11554 | if (i == 0) | |
11555 | mips_pic = NO_PIC; | |
11556 | else if (i == 2) | |
143d77c5 | 11557 | { |
252b5132 | 11558 | mips_pic = SVR4_PIC; |
143d77c5 EC |
11559 | mips_abicalls = TRUE; |
11560 | } | |
252b5132 RH |
11561 | else |
11562 | as_bad (_(".option pic%d not supported"), i); | |
11563 | ||
4d0d148d | 11564 | if (mips_pic == SVR4_PIC) |
252b5132 RH |
11565 | { |
11566 | if (g_switch_seen && g_switch_value != 0) | |
11567 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
11568 | g_switch_value = 0; | |
11569 | bfd_set_gp_size (stdoutput, 0); | |
11570 | } | |
11571 | } | |
11572 | else | |
11573 | as_warn (_("Unrecognized option \"%s\""), opt); | |
11574 | ||
11575 | *input_line_pointer = c; | |
11576 | demand_empty_rest_of_line (); | |
11577 | } | |
11578 | ||
11579 | /* This structure is used to hold a stack of .set values. */ | |
11580 | ||
e972090a NC |
11581 | struct mips_option_stack |
11582 | { | |
252b5132 RH |
11583 | struct mips_option_stack *next; |
11584 | struct mips_set_options options; | |
11585 | }; | |
11586 | ||
11587 | static struct mips_option_stack *mips_opts_stack; | |
11588 | ||
11589 | /* Handle the .set pseudo-op. */ | |
11590 | ||
11591 | static void | |
17a2f251 | 11592 | s_mipsset (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
11593 | { |
11594 | char *name = input_line_pointer, ch; | |
11595 | ||
11596 | while (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
f9419b05 | 11597 | ++input_line_pointer; |
252b5132 RH |
11598 | ch = *input_line_pointer; |
11599 | *input_line_pointer = '\0'; | |
11600 | ||
11601 | if (strcmp (name, "reorder") == 0) | |
11602 | { | |
11603 | if (mips_opts.noreorder && prev_nop_frag != NULL) | |
11604 | { | |
11605 | /* If we still have pending nops, we can discard them. The | |
11606 | usual nop handling will insert any that are still | |
bdaaa2e1 | 11607 | needed. */ |
252b5132 RH |
11608 | prev_nop_frag->fr_fix -= (prev_nop_frag_holds |
11609 | * (mips_opts.mips16 ? 2 : 4)); | |
11610 | prev_nop_frag = NULL; | |
11611 | } | |
11612 | mips_opts.noreorder = 0; | |
11613 | } | |
11614 | else if (strcmp (name, "noreorder") == 0) | |
11615 | { | |
b34976b6 | 11616 | mips_emit_delays (TRUE); |
252b5132 RH |
11617 | mips_opts.noreorder = 1; |
11618 | mips_any_noreorder = 1; | |
11619 | } | |
11620 | else if (strcmp (name, "at") == 0) | |
11621 | { | |
11622 | mips_opts.noat = 0; | |
11623 | } | |
11624 | else if (strcmp (name, "noat") == 0) | |
11625 | { | |
11626 | mips_opts.noat = 1; | |
11627 | } | |
11628 | else if (strcmp (name, "macro") == 0) | |
11629 | { | |
11630 | mips_opts.warn_about_macros = 0; | |
11631 | } | |
11632 | else if (strcmp (name, "nomacro") == 0) | |
11633 | { | |
11634 | if (mips_opts.noreorder == 0) | |
11635 | as_bad (_("`noreorder' must be set before `nomacro'")); | |
11636 | mips_opts.warn_about_macros = 1; | |
11637 | } | |
11638 | else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0) | |
11639 | { | |
11640 | mips_opts.nomove = 0; | |
11641 | } | |
11642 | else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0) | |
11643 | { | |
11644 | mips_opts.nomove = 1; | |
11645 | } | |
11646 | else if (strcmp (name, "bopt") == 0) | |
11647 | { | |
11648 | mips_opts.nobopt = 0; | |
11649 | } | |
11650 | else if (strcmp (name, "nobopt") == 0) | |
11651 | { | |
11652 | mips_opts.nobopt = 1; | |
11653 | } | |
11654 | else if (strcmp (name, "mips16") == 0 | |
11655 | || strcmp (name, "MIPS-16") == 0) | |
11656 | mips_opts.mips16 = 1; | |
11657 | else if (strcmp (name, "nomips16") == 0 | |
11658 | || strcmp (name, "noMIPS-16") == 0) | |
11659 | mips_opts.mips16 = 0; | |
1f25f5d3 CD |
11660 | else if (strcmp (name, "mips3d") == 0) |
11661 | mips_opts.ase_mips3d = 1; | |
11662 | else if (strcmp (name, "nomips3d") == 0) | |
11663 | mips_opts.ase_mips3d = 0; | |
a4672219 TS |
11664 | else if (strcmp (name, "mdmx") == 0) |
11665 | mips_opts.ase_mdmx = 1; | |
11666 | else if (strcmp (name, "nomdmx") == 0) | |
11667 | mips_opts.ase_mdmx = 0; | |
1a2c1fad | 11668 | else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0) |
252b5132 | 11669 | { |
af7ee8bf | 11670 | int reset = 0; |
252b5132 | 11671 | |
1a2c1fad CD |
11672 | /* Permit the user to change the ISA and architecture on the fly. |
11673 | Needless to say, misuse can cause serious problems. */ | |
81a21e38 | 11674 | if (strcmp (name, "mips0") == 0 || strcmp (name, "arch=default") == 0) |
af7ee8bf CD |
11675 | { |
11676 | reset = 1; | |
11677 | mips_opts.isa = file_mips_isa; | |
1a2c1fad | 11678 | mips_opts.arch = file_mips_arch; |
1a2c1fad CD |
11679 | } |
11680 | else if (strncmp (name, "arch=", 5) == 0) | |
11681 | { | |
11682 | const struct mips_cpu_info *p; | |
11683 | ||
11684 | p = mips_parse_cpu("internal use", name + 5); | |
11685 | if (!p) | |
11686 | as_bad (_("unknown architecture %s"), name + 5); | |
11687 | else | |
11688 | { | |
11689 | mips_opts.arch = p->cpu; | |
11690 | mips_opts.isa = p->isa; | |
11691 | } | |
11692 | } | |
81a21e38 TS |
11693 | else if (strncmp (name, "mips", 4) == 0) |
11694 | { | |
11695 | const struct mips_cpu_info *p; | |
11696 | ||
11697 | p = mips_parse_cpu("internal use", name); | |
11698 | if (!p) | |
11699 | as_bad (_("unknown ISA level %s"), name + 4); | |
11700 | else | |
11701 | { | |
11702 | mips_opts.arch = p->cpu; | |
11703 | mips_opts.isa = p->isa; | |
11704 | } | |
11705 | } | |
af7ee8bf | 11706 | else |
81a21e38 | 11707 | as_bad (_("unknown ISA or architecture %s"), name); |
af7ee8bf CD |
11708 | |
11709 | switch (mips_opts.isa) | |
98d3f06f KH |
11710 | { |
11711 | case 0: | |
98d3f06f | 11712 | break; |
af7ee8bf CD |
11713 | case ISA_MIPS1: |
11714 | case ISA_MIPS2: | |
11715 | case ISA_MIPS32: | |
11716 | case ISA_MIPS32R2: | |
98d3f06f KH |
11717 | mips_opts.gp32 = 1; |
11718 | mips_opts.fp32 = 1; | |
11719 | break; | |
af7ee8bf CD |
11720 | case ISA_MIPS3: |
11721 | case ISA_MIPS4: | |
11722 | case ISA_MIPS5: | |
11723 | case ISA_MIPS64: | |
5f74bc13 | 11724 | case ISA_MIPS64R2: |
98d3f06f KH |
11725 | mips_opts.gp32 = 0; |
11726 | mips_opts.fp32 = 0; | |
11727 | break; | |
11728 | default: | |
11729 | as_bad (_("unknown ISA level %s"), name + 4); | |
11730 | break; | |
11731 | } | |
af7ee8bf | 11732 | if (reset) |
98d3f06f | 11733 | { |
af7ee8bf CD |
11734 | mips_opts.gp32 = file_mips_gp32; |
11735 | mips_opts.fp32 = file_mips_fp32; | |
98d3f06f | 11736 | } |
252b5132 RH |
11737 | } |
11738 | else if (strcmp (name, "autoextend") == 0) | |
11739 | mips_opts.noautoextend = 0; | |
11740 | else if (strcmp (name, "noautoextend") == 0) | |
11741 | mips_opts.noautoextend = 1; | |
11742 | else if (strcmp (name, "push") == 0) | |
11743 | { | |
11744 | struct mips_option_stack *s; | |
11745 | ||
11746 | s = (struct mips_option_stack *) xmalloc (sizeof *s); | |
11747 | s->next = mips_opts_stack; | |
11748 | s->options = mips_opts; | |
11749 | mips_opts_stack = s; | |
11750 | } | |
11751 | else if (strcmp (name, "pop") == 0) | |
11752 | { | |
11753 | struct mips_option_stack *s; | |
11754 | ||
11755 | s = mips_opts_stack; | |
11756 | if (s == NULL) | |
11757 | as_bad (_(".set pop with no .set push")); | |
11758 | else | |
11759 | { | |
11760 | /* If we're changing the reorder mode we need to handle | |
11761 | delay slots correctly. */ | |
11762 | if (s->options.noreorder && ! mips_opts.noreorder) | |
b34976b6 | 11763 | mips_emit_delays (TRUE); |
252b5132 RH |
11764 | else if (! s->options.noreorder && mips_opts.noreorder) |
11765 | { | |
11766 | if (prev_nop_frag != NULL) | |
11767 | { | |
11768 | prev_nop_frag->fr_fix -= (prev_nop_frag_holds | |
11769 | * (mips_opts.mips16 ? 2 : 4)); | |
11770 | prev_nop_frag = NULL; | |
11771 | } | |
11772 | } | |
11773 | ||
11774 | mips_opts = s->options; | |
11775 | mips_opts_stack = s->next; | |
11776 | free (s); | |
11777 | } | |
11778 | } | |
11779 | else | |
11780 | { | |
11781 | as_warn (_("Tried to set unrecognized symbol: %s\n"), name); | |
11782 | } | |
11783 | *input_line_pointer = ch; | |
11784 | demand_empty_rest_of_line (); | |
11785 | } | |
11786 | ||
11787 | /* Handle the .abicalls pseudo-op. I believe this is equivalent to | |
11788 | .option pic2. It means to generate SVR4 PIC calls. */ | |
11789 | ||
11790 | static void | |
17a2f251 | 11791 | s_abicalls (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
11792 | { |
11793 | mips_pic = SVR4_PIC; | |
143d77c5 | 11794 | mips_abicalls = TRUE; |
4d0d148d TS |
11795 | |
11796 | if (g_switch_seen && g_switch_value != 0) | |
11797 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
11798 | g_switch_value = 0; | |
11799 | ||
252b5132 RH |
11800 | bfd_set_gp_size (stdoutput, 0); |
11801 | demand_empty_rest_of_line (); | |
11802 | } | |
11803 | ||
11804 | /* Handle the .cpload pseudo-op. This is used when generating SVR4 | |
11805 | PIC code. It sets the $gp register for the function based on the | |
11806 | function address, which is in the register named in the argument. | |
11807 | This uses a relocation against _gp_disp, which is handled specially | |
11808 | by the linker. The result is: | |
11809 | lui $gp,%hi(_gp_disp) | |
11810 | addiu $gp,$gp,%lo(_gp_disp) | |
11811 | addu $gp,$gp,.cpload argument | |
aa6975fb ILT |
11812 | The .cpload argument is normally $25 == $t9. |
11813 | ||
11814 | The -mno-shared option changes this to: | |
11815 | lui $gp,%hi(_gp) | |
11816 | addiu $gp,$gp,%lo(_gp) | |
11817 | and the argument is ignored. This saves an instruction, but the | |
11818 | resulting code is not position independent; it uses an absolute | |
11819 | address for _gp. Thus code assembled with -mno-shared can go into | |
11820 | an ordinary executable, but not into a shared library. */ | |
252b5132 RH |
11821 | |
11822 | static void | |
17a2f251 | 11823 | s_cpload (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
11824 | { |
11825 | expressionS ex; | |
aa6975fb ILT |
11826 | int reg; |
11827 | int in_shared; | |
252b5132 | 11828 | |
6478892d TS |
11829 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
11830 | .cpload is ignored. */ | |
11831 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) | |
252b5132 RH |
11832 | { |
11833 | s_ignore (0); | |
11834 | return; | |
11835 | } | |
11836 | ||
d3ecfc59 | 11837 | /* .cpload should be in a .set noreorder section. */ |
252b5132 RH |
11838 | if (mips_opts.noreorder == 0) |
11839 | as_warn (_(".cpload not in noreorder section")); | |
11840 | ||
aa6975fb ILT |
11841 | reg = tc_get_register (0); |
11842 | ||
11843 | /* If we need to produce a 64-bit address, we are better off using | |
11844 | the default instruction sequence. */ | |
11845 | in_shared = mips_in_shared || HAVE_64BIT_ADDRESSES; | |
11846 | ||
252b5132 | 11847 | ex.X_op = O_symbol; |
aa6975fb | 11848 | ex.X_add_symbol = symbol_find_or_make (in_shared ? "_gp_disp" : "_gp"); |
252b5132 RH |
11849 | ex.X_op_symbol = NULL; |
11850 | ex.X_add_number = 0; | |
11851 | ||
11852 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ | |
49309057 | 11853 | symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; |
252b5132 | 11854 | |
584892a6 | 11855 | macro_start (); |
67c0d1eb RS |
11856 | macro_build_lui (&ex, mips_gp_register); |
11857 | macro_build (&ex, "addiu", "t,r,j", mips_gp_register, | |
17a2f251 | 11858 | mips_gp_register, BFD_RELOC_LO16); |
aa6975fb ILT |
11859 | if (in_shared) |
11860 | macro_build (NULL, "addu", "d,v,t", mips_gp_register, | |
11861 | mips_gp_register, reg); | |
584892a6 | 11862 | macro_end (); |
252b5132 RH |
11863 | |
11864 | demand_empty_rest_of_line (); | |
11865 | } | |
11866 | ||
6478892d TS |
11867 | /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is: |
11868 | .cpsetup $reg1, offset|$reg2, label | |
11869 | ||
11870 | If offset is given, this results in: | |
11871 | sd $gp, offset($sp) | |
956cd1d6 | 11872 | lui $gp, %hi(%neg(%gp_rel(label))) |
698b7d9d TS |
11873 | addiu $gp, $gp, %lo(%neg(%gp_rel(label))) |
11874 | daddu $gp, $gp, $reg1 | |
6478892d TS |
11875 | |
11876 | If $reg2 is given, this results in: | |
11877 | daddu $reg2, $gp, $0 | |
956cd1d6 | 11878 | lui $gp, %hi(%neg(%gp_rel(label))) |
698b7d9d TS |
11879 | addiu $gp, $gp, %lo(%neg(%gp_rel(label))) |
11880 | daddu $gp, $gp, $reg1 | |
aa6975fb ILT |
11881 | $reg1 is normally $25 == $t9. |
11882 | ||
11883 | The -mno-shared option replaces the last three instructions with | |
11884 | lui $gp,%hi(_gp) | |
11885 | addiu $gp,$gp,%lo(_gp) | |
11886 | */ | |
11887 | ||
6478892d | 11888 | static void |
17a2f251 | 11889 | s_cpsetup (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
11890 | { |
11891 | expressionS ex_off; | |
11892 | expressionS ex_sym; | |
11893 | int reg1; | |
6478892d | 11894 | |
8586fc66 | 11895 | /* If we are not generating SVR4 PIC code, .cpsetup is ignored. |
6478892d TS |
11896 | We also need NewABI support. */ |
11897 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
11898 | { | |
11899 | s_ignore (0); | |
11900 | return; | |
11901 | } | |
11902 | ||
11903 | reg1 = tc_get_register (0); | |
11904 | SKIP_WHITESPACE (); | |
11905 | if (*input_line_pointer != ',') | |
11906 | { | |
11907 | as_bad (_("missing argument separator ',' for .cpsetup")); | |
11908 | return; | |
11909 | } | |
11910 | else | |
80245285 | 11911 | ++input_line_pointer; |
6478892d TS |
11912 | SKIP_WHITESPACE (); |
11913 | if (*input_line_pointer == '$') | |
80245285 TS |
11914 | { |
11915 | mips_cpreturn_register = tc_get_register (0); | |
11916 | mips_cpreturn_offset = -1; | |
11917 | } | |
6478892d | 11918 | else |
80245285 TS |
11919 | { |
11920 | mips_cpreturn_offset = get_absolute_expression (); | |
11921 | mips_cpreturn_register = -1; | |
11922 | } | |
6478892d TS |
11923 | SKIP_WHITESPACE (); |
11924 | if (*input_line_pointer != ',') | |
11925 | { | |
11926 | as_bad (_("missing argument separator ',' for .cpsetup")); | |
11927 | return; | |
11928 | } | |
11929 | else | |
f9419b05 | 11930 | ++input_line_pointer; |
6478892d | 11931 | SKIP_WHITESPACE (); |
f21f8242 | 11932 | expression (&ex_sym); |
6478892d | 11933 | |
584892a6 | 11934 | macro_start (); |
6478892d TS |
11935 | if (mips_cpreturn_register == -1) |
11936 | { | |
11937 | ex_off.X_op = O_constant; | |
11938 | ex_off.X_add_symbol = NULL; | |
11939 | ex_off.X_op_symbol = NULL; | |
11940 | ex_off.X_add_number = mips_cpreturn_offset; | |
11941 | ||
67c0d1eb | 11942 | macro_build (&ex_off, "sd", "t,o(b)", mips_gp_register, |
17a2f251 | 11943 | BFD_RELOC_LO16, SP); |
6478892d TS |
11944 | } |
11945 | else | |
67c0d1eb | 11946 | macro_build (NULL, "daddu", "d,v,t", mips_cpreturn_register, |
17a2f251 | 11947 | mips_gp_register, 0); |
6478892d | 11948 | |
aa6975fb ILT |
11949 | if (mips_in_shared || HAVE_64BIT_ADDRESSES) |
11950 | { | |
11951 | macro_build (&ex_sym, "lui", "t,u", mips_gp_register, | |
11952 | -1, BFD_RELOC_GPREL16, BFD_RELOC_MIPS_SUB, | |
11953 | BFD_RELOC_HI16_S); | |
11954 | ||
11955 | macro_build (&ex_sym, "addiu", "t,r,j", mips_gp_register, | |
11956 | mips_gp_register, -1, BFD_RELOC_GPREL16, | |
11957 | BFD_RELOC_MIPS_SUB, BFD_RELOC_LO16); | |
11958 | ||
11959 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register, | |
11960 | mips_gp_register, reg1); | |
11961 | } | |
11962 | else | |
11963 | { | |
11964 | expressionS ex; | |
11965 | ||
11966 | ex.X_op = O_symbol; | |
11967 | ex.X_add_symbol = symbol_find_or_make ("_gp"); | |
11968 | ex.X_op_symbol = NULL; | |
11969 | ex.X_add_number = 0; | |
6e1304d8 | 11970 | |
aa6975fb ILT |
11971 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ |
11972 | symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; | |
11973 | ||
11974 | macro_build_lui (&ex, mips_gp_register); | |
11975 | macro_build (&ex, "addiu", "t,r,j", mips_gp_register, | |
11976 | mips_gp_register, BFD_RELOC_LO16); | |
11977 | } | |
f21f8242 | 11978 | |
584892a6 | 11979 | macro_end (); |
6478892d TS |
11980 | |
11981 | demand_empty_rest_of_line (); | |
11982 | } | |
11983 | ||
11984 | static void | |
17a2f251 | 11985 | s_cplocal (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
11986 | { |
11987 | /* If we are not generating SVR4 PIC code, or if this is not NewABI code, | |
11988 | .cplocal is ignored. */ | |
11989 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
11990 | { | |
11991 | s_ignore (0); | |
11992 | return; | |
11993 | } | |
11994 | ||
11995 | mips_gp_register = tc_get_register (0); | |
85b51719 | 11996 | demand_empty_rest_of_line (); |
6478892d TS |
11997 | } |
11998 | ||
252b5132 RH |
11999 | /* Handle the .cprestore pseudo-op. This stores $gp into a given |
12000 | offset from $sp. The offset is remembered, and after making a PIC | |
12001 | call $gp is restored from that location. */ | |
12002 | ||
12003 | static void | |
17a2f251 | 12004 | s_cprestore (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
12005 | { |
12006 | expressionS ex; | |
252b5132 | 12007 | |
6478892d | 12008 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
c9914766 | 12009 | .cprestore is ignored. */ |
6478892d | 12010 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) |
252b5132 RH |
12011 | { |
12012 | s_ignore (0); | |
12013 | return; | |
12014 | } | |
12015 | ||
12016 | mips_cprestore_offset = get_absolute_expression (); | |
7a621144 | 12017 | mips_cprestore_valid = 1; |
252b5132 RH |
12018 | |
12019 | ex.X_op = O_constant; | |
12020 | ex.X_add_symbol = NULL; | |
12021 | ex.X_op_symbol = NULL; | |
12022 | ex.X_add_number = mips_cprestore_offset; | |
12023 | ||
584892a6 | 12024 | macro_start (); |
67c0d1eb RS |
12025 | macro_build_ldst_constoffset (&ex, ADDRESS_STORE_INSN, mips_gp_register, |
12026 | SP, HAVE_64BIT_ADDRESSES); | |
584892a6 | 12027 | macro_end (); |
252b5132 RH |
12028 | |
12029 | demand_empty_rest_of_line (); | |
12030 | } | |
12031 | ||
6478892d | 12032 | /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset |
67c1ffbe | 12033 | was given in the preceding .cpsetup, it results in: |
6478892d | 12034 | ld $gp, offset($sp) |
76b3015f | 12035 | |
6478892d | 12036 | If a register $reg2 was given there, it results in: |
609f23f4 | 12037 | daddu $gp, $reg2, $0 |
6478892d TS |
12038 | */ |
12039 | static void | |
17a2f251 | 12040 | s_cpreturn (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
12041 | { |
12042 | expressionS ex; | |
6478892d TS |
12043 | |
12044 | /* If we are not generating SVR4 PIC code, .cpreturn is ignored. | |
12045 | We also need NewABI support. */ | |
12046 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
12047 | { | |
12048 | s_ignore (0); | |
12049 | return; | |
12050 | } | |
12051 | ||
584892a6 | 12052 | macro_start (); |
6478892d TS |
12053 | if (mips_cpreturn_register == -1) |
12054 | { | |
12055 | ex.X_op = O_constant; | |
12056 | ex.X_add_symbol = NULL; | |
12057 | ex.X_op_symbol = NULL; | |
12058 | ex.X_add_number = mips_cpreturn_offset; | |
12059 | ||
67c0d1eb | 12060 | macro_build (&ex, "ld", "t,o(b)", mips_gp_register, BFD_RELOC_LO16, SP); |
6478892d TS |
12061 | } |
12062 | else | |
67c0d1eb | 12063 | macro_build (NULL, "daddu", "d,v,t", mips_gp_register, |
17a2f251 | 12064 | mips_cpreturn_register, 0); |
584892a6 | 12065 | macro_end (); |
6478892d TS |
12066 | |
12067 | demand_empty_rest_of_line (); | |
12068 | } | |
12069 | ||
12070 | /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC | |
12071 | code. It sets the offset to use in gp_rel relocations. */ | |
12072 | ||
12073 | static void | |
17a2f251 | 12074 | s_gpvalue (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
12075 | { |
12076 | /* If we are not generating SVR4 PIC code, .gpvalue is ignored. | |
12077 | We also need NewABI support. */ | |
12078 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
12079 | { | |
12080 | s_ignore (0); | |
12081 | return; | |
12082 | } | |
12083 | ||
def2e0dd | 12084 | mips_gprel_offset = get_absolute_expression (); |
6478892d TS |
12085 | |
12086 | demand_empty_rest_of_line (); | |
12087 | } | |
12088 | ||
252b5132 RH |
12089 | /* Handle the .gpword pseudo-op. This is used when generating PIC |
12090 | code. It generates a 32 bit GP relative reloc. */ | |
12091 | ||
12092 | static void | |
17a2f251 | 12093 | s_gpword (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
12094 | { |
12095 | symbolS *label; | |
12096 | expressionS ex; | |
12097 | char *p; | |
12098 | ||
12099 | /* When not generating PIC code, this is treated as .word. */ | |
12100 | if (mips_pic != SVR4_PIC) | |
12101 | { | |
12102 | s_cons (2); | |
12103 | return; | |
12104 | } | |
12105 | ||
12106 | label = insn_labels != NULL ? insn_labels->label : NULL; | |
b34976b6 | 12107 | mips_emit_delays (TRUE); |
252b5132 RH |
12108 | if (auto_align) |
12109 | mips_align (2, 0, label); | |
12110 | mips_clear_insn_labels (); | |
12111 | ||
12112 | expression (&ex); | |
12113 | ||
12114 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
12115 | { | |
12116 | as_bad (_("Unsupported use of .gpword")); | |
12117 | ignore_rest_of_line (); | |
12118 | } | |
12119 | ||
12120 | p = frag_more (4); | |
17a2f251 | 12121 | md_number_to_chars (p, 0, 4); |
b34976b6 | 12122 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, |
cdf6fd85 | 12123 | BFD_RELOC_GPREL32); |
252b5132 RH |
12124 | |
12125 | demand_empty_rest_of_line (); | |
12126 | } | |
12127 | ||
10181a0d | 12128 | static void |
17a2f251 | 12129 | s_gpdword (int ignore ATTRIBUTE_UNUSED) |
10181a0d AO |
12130 | { |
12131 | symbolS *label; | |
12132 | expressionS ex; | |
12133 | char *p; | |
12134 | ||
12135 | /* When not generating PIC code, this is treated as .dword. */ | |
12136 | if (mips_pic != SVR4_PIC) | |
12137 | { | |
12138 | s_cons (3); | |
12139 | return; | |
12140 | } | |
12141 | ||
12142 | label = insn_labels != NULL ? insn_labels->label : NULL; | |
b34976b6 | 12143 | mips_emit_delays (TRUE); |
10181a0d AO |
12144 | if (auto_align) |
12145 | mips_align (3, 0, label); | |
12146 | mips_clear_insn_labels (); | |
12147 | ||
12148 | expression (&ex); | |
12149 | ||
12150 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
12151 | { | |
12152 | as_bad (_("Unsupported use of .gpdword")); | |
12153 | ignore_rest_of_line (); | |
12154 | } | |
12155 | ||
12156 | p = frag_more (8); | |
17a2f251 | 12157 | md_number_to_chars (p, 0, 8); |
a105a300 | 12158 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, |
6e1304d8 | 12159 | BFD_RELOC_GPREL32)->fx_tcbit = 1; |
10181a0d AO |
12160 | |
12161 | /* GPREL32 composed with 64 gives a 64-bit GP offset. */ | |
6e1304d8 RS |
12162 | fix_new (frag_now, p - frag_now->fr_literal, 8, NULL, 0, |
12163 | FALSE, BFD_RELOC_64)->fx_tcbit = 1; | |
10181a0d AO |
12164 | |
12165 | demand_empty_rest_of_line (); | |
12166 | } | |
12167 | ||
252b5132 RH |
12168 | /* Handle the .cpadd pseudo-op. This is used when dealing with switch |
12169 | tables in SVR4 PIC code. */ | |
12170 | ||
12171 | static void | |
17a2f251 | 12172 | s_cpadd (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 12173 | { |
252b5132 RH |
12174 | int reg; |
12175 | ||
10181a0d AO |
12176 | /* This is ignored when not generating SVR4 PIC code. */ |
12177 | if (mips_pic != SVR4_PIC) | |
252b5132 RH |
12178 | { |
12179 | s_ignore (0); | |
12180 | return; | |
12181 | } | |
12182 | ||
12183 | /* Add $gp to the register named as an argument. */ | |
584892a6 | 12184 | macro_start (); |
252b5132 | 12185 | reg = tc_get_register (0); |
67c0d1eb | 12186 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register); |
584892a6 | 12187 | macro_end (); |
252b5132 | 12188 | |
bdaaa2e1 | 12189 | demand_empty_rest_of_line (); |
252b5132 RH |
12190 | } |
12191 | ||
12192 | /* Handle the .insn pseudo-op. This marks instruction labels in | |
12193 | mips16 mode. This permits the linker to handle them specially, | |
12194 | such as generating jalx instructions when needed. We also make | |
12195 | them odd for the duration of the assembly, in order to generate the | |
12196 | right sort of code. We will make them even in the adjust_symtab | |
12197 | routine, while leaving them marked. This is convenient for the | |
12198 | debugger and the disassembler. The linker knows to make them odd | |
12199 | again. */ | |
12200 | ||
12201 | static void | |
17a2f251 | 12202 | s_insn (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 12203 | { |
f9419b05 | 12204 | mips16_mark_labels (); |
252b5132 RH |
12205 | |
12206 | demand_empty_rest_of_line (); | |
12207 | } | |
12208 | ||
12209 | /* Handle a .stabn directive. We need these in order to mark a label | |
12210 | as being a mips16 text label correctly. Sometimes the compiler | |
12211 | will emit a label, followed by a .stabn, and then switch sections. | |
12212 | If the label and .stabn are in mips16 mode, then the label is | |
12213 | really a mips16 text label. */ | |
12214 | ||
12215 | static void | |
17a2f251 | 12216 | s_mips_stab (int type) |
252b5132 | 12217 | { |
f9419b05 | 12218 | if (type == 'n') |
252b5132 RH |
12219 | mips16_mark_labels (); |
12220 | ||
12221 | s_stab (type); | |
12222 | } | |
12223 | ||
12224 | /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. | |
12225 | */ | |
12226 | ||
12227 | static void | |
17a2f251 | 12228 | s_mips_weakext (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
12229 | { |
12230 | char *name; | |
12231 | int c; | |
12232 | symbolS *symbolP; | |
12233 | expressionS exp; | |
12234 | ||
12235 | name = input_line_pointer; | |
12236 | c = get_symbol_end (); | |
12237 | symbolP = symbol_find_or_make (name); | |
12238 | S_SET_WEAK (symbolP); | |
12239 | *input_line_pointer = c; | |
12240 | ||
12241 | SKIP_WHITESPACE (); | |
12242 | ||
12243 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
12244 | { | |
12245 | if (S_IS_DEFINED (symbolP)) | |
12246 | { | |
956cd1d6 | 12247 | as_bad ("ignoring attempt to redefine symbol %s", |
252b5132 RH |
12248 | S_GET_NAME (symbolP)); |
12249 | ignore_rest_of_line (); | |
12250 | return; | |
12251 | } | |
bdaaa2e1 | 12252 | |
252b5132 RH |
12253 | if (*input_line_pointer == ',') |
12254 | { | |
12255 | ++input_line_pointer; | |
12256 | SKIP_WHITESPACE (); | |
12257 | } | |
bdaaa2e1 | 12258 | |
252b5132 RH |
12259 | expression (&exp); |
12260 | if (exp.X_op != O_symbol) | |
12261 | { | |
12262 | as_bad ("bad .weakext directive"); | |
98d3f06f | 12263 | ignore_rest_of_line (); |
252b5132 RH |
12264 | return; |
12265 | } | |
49309057 | 12266 | symbol_set_value_expression (symbolP, &exp); |
252b5132 RH |
12267 | } |
12268 | ||
12269 | demand_empty_rest_of_line (); | |
12270 | } | |
12271 | ||
12272 | /* Parse a register string into a number. Called from the ECOFF code | |
12273 | to parse .frame. The argument is non-zero if this is the frame | |
12274 | register, so that we can record it in mips_frame_reg. */ | |
12275 | ||
12276 | int | |
17a2f251 | 12277 | tc_get_register (int frame) |
252b5132 RH |
12278 | { |
12279 | int reg; | |
12280 | ||
12281 | SKIP_WHITESPACE (); | |
12282 | if (*input_line_pointer++ != '$') | |
12283 | { | |
12284 | as_warn (_("expected `$'")); | |
85b51719 | 12285 | reg = ZERO; |
252b5132 | 12286 | } |
3882b010 | 12287 | else if (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
12288 | { |
12289 | reg = get_absolute_expression (); | |
12290 | if (reg < 0 || reg >= 32) | |
12291 | { | |
12292 | as_warn (_("Bad register number")); | |
85b51719 | 12293 | reg = ZERO; |
252b5132 RH |
12294 | } |
12295 | } | |
12296 | else | |
12297 | { | |
76db943d | 12298 | if (strncmp (input_line_pointer, "ra", 2) == 0) |
85b51719 TS |
12299 | { |
12300 | reg = RA; | |
12301 | input_line_pointer += 2; | |
12302 | } | |
76db943d | 12303 | else if (strncmp (input_line_pointer, "fp", 2) == 0) |
85b51719 TS |
12304 | { |
12305 | reg = FP; | |
12306 | input_line_pointer += 2; | |
12307 | } | |
252b5132 | 12308 | else if (strncmp (input_line_pointer, "sp", 2) == 0) |
85b51719 TS |
12309 | { |
12310 | reg = SP; | |
12311 | input_line_pointer += 2; | |
12312 | } | |
252b5132 | 12313 | else if (strncmp (input_line_pointer, "gp", 2) == 0) |
85b51719 TS |
12314 | { |
12315 | reg = GP; | |
12316 | input_line_pointer += 2; | |
12317 | } | |
252b5132 | 12318 | else if (strncmp (input_line_pointer, "at", 2) == 0) |
85b51719 TS |
12319 | { |
12320 | reg = AT; | |
12321 | input_line_pointer += 2; | |
12322 | } | |
12323 | else if (strncmp (input_line_pointer, "kt0", 3) == 0) | |
12324 | { | |
12325 | reg = KT0; | |
12326 | input_line_pointer += 3; | |
12327 | } | |
12328 | else if (strncmp (input_line_pointer, "kt1", 3) == 0) | |
12329 | { | |
12330 | reg = KT1; | |
12331 | input_line_pointer += 3; | |
12332 | } | |
12333 | else if (strncmp (input_line_pointer, "zero", 4) == 0) | |
12334 | { | |
12335 | reg = ZERO; | |
12336 | input_line_pointer += 4; | |
12337 | } | |
252b5132 RH |
12338 | else |
12339 | { | |
12340 | as_warn (_("Unrecognized register name")); | |
85b51719 TS |
12341 | reg = ZERO; |
12342 | while (ISALNUM(*input_line_pointer)) | |
12343 | input_line_pointer++; | |
252b5132 | 12344 | } |
252b5132 RH |
12345 | } |
12346 | if (frame) | |
7a621144 DJ |
12347 | { |
12348 | mips_frame_reg = reg != 0 ? reg : SP; | |
12349 | mips_frame_reg_valid = 1; | |
12350 | mips_cprestore_valid = 0; | |
12351 | } | |
252b5132 RH |
12352 | return reg; |
12353 | } | |
12354 | ||
12355 | valueT | |
17a2f251 | 12356 | md_section_align (asection *seg, valueT addr) |
252b5132 RH |
12357 | { |
12358 | int align = bfd_get_section_alignment (stdoutput, seg); | |
12359 | ||
12360 | #ifdef OBJ_ELF | |
12361 | /* We don't need to align ELF sections to the full alignment. | |
12362 | However, Irix 5 may prefer that we align them at least to a 16 | |
12363 | byte boundary. We don't bother to align the sections if we are | |
12364 | targeted for an embedded system. */ | |
12365 | if (strcmp (TARGET_OS, "elf") == 0) | |
12366 | return addr; | |
12367 | if (align > 4) | |
12368 | align = 4; | |
12369 | #endif | |
12370 | ||
12371 | return ((addr + (1 << align) - 1) & (-1 << align)); | |
12372 | } | |
12373 | ||
12374 | /* Utility routine, called from above as well. If called while the | |
12375 | input file is still being read, it's only an approximation. (For | |
12376 | example, a symbol may later become defined which appeared to be | |
12377 | undefined earlier.) */ | |
12378 | ||
12379 | static int | |
17a2f251 | 12380 | nopic_need_relax (symbolS *sym, int before_relaxing) |
252b5132 RH |
12381 | { |
12382 | if (sym == 0) | |
12383 | return 0; | |
12384 | ||
4d0d148d | 12385 | if (g_switch_value > 0) |
252b5132 RH |
12386 | { |
12387 | const char *symname; | |
12388 | int change; | |
12389 | ||
c9914766 | 12390 | /* Find out whether this symbol can be referenced off the $gp |
252b5132 RH |
12391 | register. It can be if it is smaller than the -G size or if |
12392 | it is in the .sdata or .sbss section. Certain symbols can | |
c9914766 | 12393 | not be referenced off the $gp, although it appears as though |
252b5132 RH |
12394 | they can. */ |
12395 | symname = S_GET_NAME (sym); | |
12396 | if (symname != (const char *) NULL | |
12397 | && (strcmp (symname, "eprol") == 0 | |
12398 | || strcmp (symname, "etext") == 0 | |
12399 | || strcmp (symname, "_gp") == 0 | |
12400 | || strcmp (symname, "edata") == 0 | |
12401 | || strcmp (symname, "_fbss") == 0 | |
12402 | || strcmp (symname, "_fdata") == 0 | |
12403 | || strcmp (symname, "_ftext") == 0 | |
12404 | || strcmp (symname, "end") == 0 | |
12405 | || strcmp (symname, "_gp_disp") == 0)) | |
12406 | change = 1; | |
12407 | else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym)) | |
12408 | && (0 | |
12409 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 ILT |
12410 | || (symbol_get_obj (sym)->ecoff_extern_size != 0 |
12411 | && (symbol_get_obj (sym)->ecoff_extern_size | |
12412 | <= g_switch_value)) | |
252b5132 RH |
12413 | #endif |
12414 | /* We must defer this decision until after the whole | |
12415 | file has been read, since there might be a .extern | |
12416 | after the first use of this symbol. */ | |
12417 | || (before_relaxing | |
12418 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 | 12419 | && symbol_get_obj (sym)->ecoff_extern_size == 0 |
252b5132 RH |
12420 | #endif |
12421 | && S_GET_VALUE (sym) == 0) | |
12422 | || (S_GET_VALUE (sym) != 0 | |
12423 | && S_GET_VALUE (sym) <= g_switch_value))) | |
12424 | change = 0; | |
12425 | else | |
12426 | { | |
12427 | const char *segname; | |
12428 | ||
12429 | segname = segment_name (S_GET_SEGMENT (sym)); | |
12430 | assert (strcmp (segname, ".lit8") != 0 | |
12431 | && strcmp (segname, ".lit4") != 0); | |
12432 | change = (strcmp (segname, ".sdata") != 0 | |
fba2b7f9 GK |
12433 | && strcmp (segname, ".sbss") != 0 |
12434 | && strncmp (segname, ".sdata.", 7) != 0 | |
12435 | && strncmp (segname, ".gnu.linkonce.s.", 16) != 0); | |
252b5132 RH |
12436 | } |
12437 | return change; | |
12438 | } | |
12439 | else | |
c9914766 | 12440 | /* We are not optimizing for the $gp register. */ |
252b5132 RH |
12441 | return 1; |
12442 | } | |
12443 | ||
5919d012 RS |
12444 | |
12445 | /* Return true if the given symbol should be considered local for SVR4 PIC. */ | |
12446 | ||
12447 | static bfd_boolean | |
17a2f251 | 12448 | pic_need_relax (symbolS *sym, asection *segtype) |
5919d012 RS |
12449 | { |
12450 | asection *symsec; | |
12451 | bfd_boolean linkonce; | |
12452 | ||
12453 | /* Handle the case of a symbol equated to another symbol. */ | |
12454 | while (symbol_equated_reloc_p (sym)) | |
12455 | { | |
12456 | symbolS *n; | |
12457 | ||
12458 | /* It's possible to get a loop here in a badly written | |
12459 | program. */ | |
12460 | n = symbol_get_value_expression (sym)->X_add_symbol; | |
12461 | if (n == sym) | |
12462 | break; | |
12463 | sym = n; | |
12464 | } | |
12465 | ||
12466 | symsec = S_GET_SEGMENT (sym); | |
12467 | ||
12468 | /* duplicate the test for LINK_ONCE sections as in adjust_reloc_syms */ | |
12469 | linkonce = FALSE; | |
12470 | if (symsec != segtype && ! S_IS_LOCAL (sym)) | |
12471 | { | |
12472 | if ((bfd_get_section_flags (stdoutput, symsec) & SEC_LINK_ONCE) | |
12473 | != 0) | |
12474 | linkonce = TRUE; | |
12475 | ||
12476 | /* The GNU toolchain uses an extension for ELF: a section | |
12477 | beginning with the magic string .gnu.linkonce is a linkonce | |
12478 | section. */ | |
12479 | if (strncmp (segment_name (symsec), ".gnu.linkonce", | |
12480 | sizeof ".gnu.linkonce" - 1) == 0) | |
12481 | linkonce = TRUE; | |
12482 | } | |
12483 | ||
12484 | /* This must duplicate the test in adjust_reloc_syms. */ | |
12485 | return (symsec != &bfd_und_section | |
12486 | && symsec != &bfd_abs_section | |
12487 | && ! bfd_is_com_section (symsec) | |
12488 | && !linkonce | |
12489 | #ifdef OBJ_ELF | |
12490 | /* A global or weak symbol is treated as external. */ | |
12491 | && (OUTPUT_FLAVOR != bfd_target_elf_flavour | |
3e722fb5 | 12492 | || (! S_IS_WEAK (sym) && ! S_IS_EXTERNAL (sym))) |
5919d012 RS |
12493 | #endif |
12494 | ); | |
12495 | } | |
12496 | ||
12497 | ||
252b5132 RH |
12498 | /* Given a mips16 variant frag FRAGP, return non-zero if it needs an |
12499 | extended opcode. SEC is the section the frag is in. */ | |
12500 | ||
12501 | static int | |
17a2f251 | 12502 | mips16_extended_frag (fragS *fragp, asection *sec, long stretch) |
252b5132 RH |
12503 | { |
12504 | int type; | |
12505 | register const struct mips16_immed_operand *op; | |
12506 | offsetT val; | |
12507 | int mintiny, maxtiny; | |
12508 | segT symsec; | |
98aa84af | 12509 | fragS *sym_frag; |
252b5132 RH |
12510 | |
12511 | if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype)) | |
12512 | return 0; | |
12513 | if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype)) | |
12514 | return 1; | |
12515 | ||
12516 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
12517 | op = mips16_immed_operands; | |
12518 | while (op->type != type) | |
12519 | { | |
12520 | ++op; | |
12521 | assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); | |
12522 | } | |
12523 | ||
12524 | if (op->unsp) | |
12525 | { | |
12526 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
12527 | { | |
12528 | mintiny = 1; | |
12529 | maxtiny = 1 << op->nbits; | |
12530 | } | |
12531 | else | |
12532 | { | |
12533 | mintiny = 0; | |
12534 | maxtiny = (1 << op->nbits) - 1; | |
12535 | } | |
12536 | } | |
12537 | else | |
12538 | { | |
12539 | mintiny = - (1 << (op->nbits - 1)); | |
12540 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
12541 | } | |
12542 | ||
98aa84af | 12543 | sym_frag = symbol_get_frag (fragp->fr_symbol); |
ac62c346 | 12544 | val = S_GET_VALUE (fragp->fr_symbol); |
98aa84af | 12545 | symsec = S_GET_SEGMENT (fragp->fr_symbol); |
252b5132 RH |
12546 | |
12547 | if (op->pcrel) | |
12548 | { | |
12549 | addressT addr; | |
12550 | ||
12551 | /* We won't have the section when we are called from | |
12552 | mips_relax_frag. However, we will always have been called | |
12553 | from md_estimate_size_before_relax first. If this is a | |
12554 | branch to a different section, we mark it as such. If SEC is | |
12555 | NULL, and the frag is not marked, then it must be a branch to | |
12556 | the same section. */ | |
12557 | if (sec == NULL) | |
12558 | { | |
12559 | if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype)) | |
12560 | return 1; | |
12561 | } | |
12562 | else | |
12563 | { | |
98aa84af | 12564 | /* Must have been called from md_estimate_size_before_relax. */ |
252b5132 RH |
12565 | if (symsec != sec) |
12566 | { | |
12567 | fragp->fr_subtype = | |
12568 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
12569 | ||
12570 | /* FIXME: We should support this, and let the linker | |
12571 | catch branches and loads that are out of range. */ | |
12572 | as_bad_where (fragp->fr_file, fragp->fr_line, | |
12573 | _("unsupported PC relative reference to different section")); | |
12574 | ||
12575 | return 1; | |
12576 | } | |
98aa84af AM |
12577 | if (fragp != sym_frag && sym_frag->fr_address == 0) |
12578 | /* Assume non-extended on the first relaxation pass. | |
12579 | The address we have calculated will be bogus if this is | |
12580 | a forward branch to another frag, as the forward frag | |
12581 | will have fr_address == 0. */ | |
12582 | return 0; | |
252b5132 RH |
12583 | } |
12584 | ||
12585 | /* In this case, we know for sure that the symbol fragment is in | |
98aa84af AM |
12586 | the same section. If the relax_marker of the symbol fragment |
12587 | differs from the relax_marker of this fragment, we have not | |
12588 | yet adjusted the symbol fragment fr_address. We want to add | |
252b5132 RH |
12589 | in STRETCH in order to get a better estimate of the address. |
12590 | This particularly matters because of the shift bits. */ | |
12591 | if (stretch != 0 | |
98aa84af | 12592 | && sym_frag->relax_marker != fragp->relax_marker) |
252b5132 RH |
12593 | { |
12594 | fragS *f; | |
12595 | ||
12596 | /* Adjust stretch for any alignment frag. Note that if have | |
12597 | been expanding the earlier code, the symbol may be | |
12598 | defined in what appears to be an earlier frag. FIXME: | |
12599 | This doesn't handle the fr_subtype field, which specifies | |
12600 | a maximum number of bytes to skip when doing an | |
12601 | alignment. */ | |
98aa84af | 12602 | for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next) |
252b5132 RH |
12603 | { |
12604 | if (f->fr_type == rs_align || f->fr_type == rs_align_code) | |
12605 | { | |
12606 | if (stretch < 0) | |
12607 | stretch = - ((- stretch) | |
12608 | & ~ ((1 << (int) f->fr_offset) - 1)); | |
12609 | else | |
12610 | stretch &= ~ ((1 << (int) f->fr_offset) - 1); | |
12611 | if (stretch == 0) | |
12612 | break; | |
12613 | } | |
12614 | } | |
12615 | if (f != NULL) | |
12616 | val += stretch; | |
12617 | } | |
12618 | ||
12619 | addr = fragp->fr_address + fragp->fr_fix; | |
12620 | ||
12621 | /* The base address rules are complicated. The base address of | |
12622 | a branch is the following instruction. The base address of a | |
12623 | PC relative load or add is the instruction itself, but if it | |
12624 | is in a delay slot (in which case it can not be extended) use | |
12625 | the address of the instruction whose delay slot it is in. */ | |
12626 | if (type == 'p' || type == 'q') | |
12627 | { | |
12628 | addr += 2; | |
12629 | ||
12630 | /* If we are currently assuming that this frag should be | |
12631 | extended, then, the current address is two bytes | |
bdaaa2e1 | 12632 | higher. */ |
252b5132 RH |
12633 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) |
12634 | addr += 2; | |
12635 | ||
12636 | /* Ignore the low bit in the target, since it will be set | |
12637 | for a text label. */ | |
12638 | if ((val & 1) != 0) | |
12639 | --val; | |
12640 | } | |
12641 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) | |
12642 | addr -= 4; | |
12643 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
12644 | addr -= 2; | |
12645 | ||
12646 | val -= addr & ~ ((1 << op->shift) - 1); | |
12647 | ||
12648 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
12649 | if (type == 'p' || type == 'q') | |
12650 | val /= 2; | |
12651 | ||
12652 | /* If any of the shifted bits are set, we must use an extended | |
12653 | opcode. If the address depends on the size of this | |
12654 | instruction, this can lead to a loop, so we arrange to always | |
12655 | use an extended opcode. We only check this when we are in | |
12656 | the main relaxation loop, when SEC is NULL. */ | |
12657 | if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL) | |
12658 | { | |
12659 | fragp->fr_subtype = | |
12660 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
12661 | return 1; | |
12662 | } | |
12663 | ||
12664 | /* If we are about to mark a frag as extended because the value | |
12665 | is precisely maxtiny + 1, then there is a chance of an | |
12666 | infinite loop as in the following code: | |
12667 | la $4,foo | |
12668 | .skip 1020 | |
12669 | .align 2 | |
12670 | foo: | |
12671 | In this case when the la is extended, foo is 0x3fc bytes | |
12672 | away, so the la can be shrunk, but then foo is 0x400 away, so | |
12673 | the la must be extended. To avoid this loop, we mark the | |
12674 | frag as extended if it was small, and is about to become | |
12675 | extended with a value of maxtiny + 1. */ | |
12676 | if (val == ((maxtiny + 1) << op->shift) | |
12677 | && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype) | |
12678 | && sec == NULL) | |
12679 | { | |
12680 | fragp->fr_subtype = | |
12681 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
12682 | return 1; | |
12683 | } | |
12684 | } | |
12685 | else if (symsec != absolute_section && sec != NULL) | |
12686 | as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation")); | |
12687 | ||
12688 | if ((val & ((1 << op->shift) - 1)) != 0 | |
12689 | || val < (mintiny << op->shift) | |
12690 | || val > (maxtiny << op->shift)) | |
12691 | return 1; | |
12692 | else | |
12693 | return 0; | |
12694 | } | |
12695 | ||
4a6a3df4 AO |
12696 | /* Compute the length of a branch sequence, and adjust the |
12697 | RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the | |
12698 | worst-case length is computed, with UPDATE being used to indicate | |
12699 | whether an unconditional (-1), branch-likely (+1) or regular (0) | |
12700 | branch is to be computed. */ | |
12701 | static int | |
17a2f251 | 12702 | relaxed_branch_length (fragS *fragp, asection *sec, int update) |
4a6a3df4 | 12703 | { |
b34976b6 | 12704 | bfd_boolean toofar; |
4a6a3df4 AO |
12705 | int length; |
12706 | ||
12707 | if (fragp | |
12708 | && S_IS_DEFINED (fragp->fr_symbol) | |
12709 | && sec == S_GET_SEGMENT (fragp->fr_symbol)) | |
12710 | { | |
12711 | addressT addr; | |
12712 | offsetT val; | |
12713 | ||
12714 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; | |
12715 | ||
12716 | addr = fragp->fr_address + fragp->fr_fix + 4; | |
12717 | ||
12718 | val -= addr; | |
12719 | ||
12720 | toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2); | |
12721 | } | |
12722 | else if (fragp) | |
12723 | /* If the symbol is not defined or it's in a different segment, | |
12724 | assume the user knows what's going on and emit a short | |
12725 | branch. */ | |
b34976b6 | 12726 | toofar = FALSE; |
4a6a3df4 | 12727 | else |
b34976b6 | 12728 | toofar = TRUE; |
4a6a3df4 AO |
12729 | |
12730 | if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) | |
12731 | fragp->fr_subtype | |
af6ae2ad | 12732 | = RELAX_BRANCH_ENCODE (RELAX_BRANCH_UNCOND (fragp->fr_subtype), |
4a6a3df4 AO |
12733 | RELAX_BRANCH_LIKELY (fragp->fr_subtype), |
12734 | RELAX_BRANCH_LINK (fragp->fr_subtype), | |
12735 | toofar); | |
12736 | ||
12737 | length = 4; | |
12738 | if (toofar) | |
12739 | { | |
12740 | if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0)) | |
12741 | length += 8; | |
12742 | ||
12743 | if (mips_pic != NO_PIC) | |
12744 | { | |
12745 | /* Additional space for PIC loading of target address. */ | |
12746 | length += 8; | |
12747 | if (mips_opts.isa == ISA_MIPS1) | |
12748 | /* Additional space for $at-stabilizing nop. */ | |
12749 | length += 4; | |
12750 | } | |
12751 | ||
12752 | /* If branch is conditional. */ | |
12753 | if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0)) | |
12754 | length += 8; | |
12755 | } | |
b34976b6 | 12756 | |
4a6a3df4 AO |
12757 | return length; |
12758 | } | |
12759 | ||
252b5132 RH |
12760 | /* Estimate the size of a frag before relaxing. Unless this is the |
12761 | mips16, we are not really relaxing here, and the final size is | |
12762 | encoded in the subtype information. For the mips16, we have to | |
12763 | decide whether we are using an extended opcode or not. */ | |
12764 | ||
252b5132 | 12765 | int |
17a2f251 | 12766 | md_estimate_size_before_relax (fragS *fragp, asection *segtype) |
252b5132 | 12767 | { |
5919d012 | 12768 | int change; |
252b5132 | 12769 | |
4a6a3df4 AO |
12770 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
12771 | { | |
12772 | ||
b34976b6 AM |
12773 | fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE); |
12774 | ||
4a6a3df4 AO |
12775 | return fragp->fr_var; |
12776 | } | |
12777 | ||
252b5132 | 12778 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
177b4a6a AO |
12779 | /* We don't want to modify the EXTENDED bit here; it might get us |
12780 | into infinite loops. We change it only in mips_relax_frag(). */ | |
12781 | return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2); | |
252b5132 RH |
12782 | |
12783 | if (mips_pic == NO_PIC) | |
5919d012 | 12784 | change = nopic_need_relax (fragp->fr_symbol, 0); |
252b5132 | 12785 | else if (mips_pic == SVR4_PIC) |
5919d012 | 12786 | change = pic_need_relax (fragp->fr_symbol, segtype); |
252b5132 RH |
12787 | else |
12788 | abort (); | |
12789 | ||
12790 | if (change) | |
12791 | { | |
4d7206a2 | 12792 | fragp->fr_subtype |= RELAX_USE_SECOND; |
4d7206a2 | 12793 | return -RELAX_FIRST (fragp->fr_subtype); |
252b5132 | 12794 | } |
4d7206a2 RS |
12795 | else |
12796 | return -RELAX_SECOND (fragp->fr_subtype); | |
252b5132 RH |
12797 | } |
12798 | ||
12799 | /* This is called to see whether a reloc against a defined symbol | |
de7e6852 | 12800 | should be converted into a reloc against a section. */ |
252b5132 RH |
12801 | |
12802 | int | |
17a2f251 | 12803 | mips_fix_adjustable (fixS *fixp) |
252b5132 | 12804 | { |
de7e6852 RS |
12805 | /* Don't adjust MIPS16 jump relocations, so we don't have to worry |
12806 | about the format of the offset in the .o file. */ | |
252b5132 RH |
12807 | if (fixp->fx_r_type == BFD_RELOC_MIPS16_JMP) |
12808 | return 0; | |
a161fe53 | 12809 | |
252b5132 RH |
12810 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
12811 | || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
12812 | return 0; | |
a161fe53 | 12813 | |
252b5132 RH |
12814 | if (fixp->fx_addsy == NULL) |
12815 | return 1; | |
a161fe53 | 12816 | |
de7e6852 RS |
12817 | /* If symbol SYM is in a mergeable section, relocations of the form |
12818 | SYM + 0 can usually be made section-relative. The mergeable data | |
12819 | is then identified by the section offset rather than by the symbol. | |
12820 | ||
12821 | However, if we're generating REL LO16 relocations, the offset is split | |
12822 | between the LO16 and parterning high part relocation. The linker will | |
12823 | need to recalculate the complete offset in order to correctly identify | |
12824 | the merge data. | |
12825 | ||
12826 | The linker has traditionally not looked for the parterning high part | |
12827 | relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be | |
12828 | placed anywhere. Rather than break backwards compatibility by changing | |
12829 | this, it seems better not to force the issue, and instead keep the | |
12830 | original symbol. This will work with either linker behavior. */ | |
12831 | if ((fixp->fx_r_type == BFD_RELOC_LO16 || reloc_needs_lo_p (fixp->fx_r_type)) | |
12832 | && HAVE_IN_PLACE_ADDENDS | |
12833 | && (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_MERGE) != 0) | |
12834 | return 0; | |
12835 | ||
252b5132 | 12836 | #ifdef OBJ_ELF |
de7e6852 RS |
12837 | /* Don't adjust relocations against mips16 symbols, so that the linker |
12838 | can find them if it needs to set up a stub. */ | |
252b5132 RH |
12839 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour |
12840 | && S_GET_OTHER (fixp->fx_addsy) == STO_MIPS16 | |
12841 | && fixp->fx_subsy == NULL) | |
12842 | return 0; | |
12843 | #endif | |
a161fe53 | 12844 | |
252b5132 RH |
12845 | return 1; |
12846 | } | |
12847 | ||
12848 | /* Translate internal representation of relocation info to BFD target | |
12849 | format. */ | |
12850 | ||
12851 | arelent ** | |
17a2f251 | 12852 | tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) |
252b5132 RH |
12853 | { |
12854 | static arelent *retval[4]; | |
12855 | arelent *reloc; | |
12856 | bfd_reloc_code_real_type code; | |
12857 | ||
4b0cff4e TS |
12858 | memset (retval, 0, sizeof(retval)); |
12859 | reloc = retval[0] = (arelent *) xcalloc (1, sizeof (arelent)); | |
49309057 ILT |
12860 | reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); |
12861 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
252b5132 RH |
12862 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; |
12863 | ||
3e722fb5 CD |
12864 | assert (! fixp->fx_pcrel); |
12865 | reloc->addend = fixp->fx_addnumber; | |
252b5132 | 12866 | |
438c16b8 TS |
12867 | /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable |
12868 | entry to be used in the relocation's section offset. */ | |
12869 | if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
252b5132 RH |
12870 | { |
12871 | reloc->address = reloc->addend; | |
12872 | reloc->addend = 0; | |
12873 | } | |
12874 | ||
252b5132 | 12875 | code = fixp->fx_r_type; |
252b5132 | 12876 | |
3e722fb5 CD |
12877 | /* To support a PC relative reloc, we used a Cygnus extension. |
12878 | We check for that here to make sure that we don't let such a | |
12879 | reloc escape normally. (FIXME: This was formerly used by | |
12880 | embedded-PIC support, but is now used by branch handling in | |
12881 | general. That probably should be fixed.) */ | |
0b25d3e6 AO |
12882 | if ((OUTPUT_FLAVOR == bfd_target_ecoff_flavour |
12883 | || OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
3e722fb5 | 12884 | && code == BFD_RELOC_16_PCREL_S2) |
0b25d3e6 AO |
12885 | reloc->howto = NULL; |
12886 | else | |
12887 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); | |
12888 | ||
252b5132 RH |
12889 | if (reloc->howto == NULL) |
12890 | { | |
12891 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
12892 | _("Can not represent %s relocation in this object file format"), | |
12893 | bfd_get_reloc_code_name (code)); | |
12894 | retval[0] = NULL; | |
12895 | } | |
12896 | ||
12897 | return retval; | |
12898 | } | |
12899 | ||
12900 | /* Relax a machine dependent frag. This returns the amount by which | |
12901 | the current size of the frag should change. */ | |
12902 | ||
12903 | int | |
17a2f251 | 12904 | mips_relax_frag (asection *sec, fragS *fragp, long stretch) |
252b5132 | 12905 | { |
4a6a3df4 AO |
12906 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
12907 | { | |
12908 | offsetT old_var = fragp->fr_var; | |
b34976b6 AM |
12909 | |
12910 | fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE); | |
4a6a3df4 AO |
12911 | |
12912 | return fragp->fr_var - old_var; | |
12913 | } | |
12914 | ||
252b5132 RH |
12915 | if (! RELAX_MIPS16_P (fragp->fr_subtype)) |
12916 | return 0; | |
12917 | ||
c4e7957c | 12918 | if (mips16_extended_frag (fragp, NULL, stretch)) |
252b5132 RH |
12919 | { |
12920 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
12921 | return 0; | |
12922 | fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype); | |
12923 | return 2; | |
12924 | } | |
12925 | else | |
12926 | { | |
12927 | if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
12928 | return 0; | |
12929 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype); | |
12930 | return -2; | |
12931 | } | |
12932 | ||
12933 | return 0; | |
12934 | } | |
12935 | ||
12936 | /* Convert a machine dependent frag. */ | |
12937 | ||
12938 | void | |
17a2f251 | 12939 | md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp) |
252b5132 | 12940 | { |
4a6a3df4 AO |
12941 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
12942 | { | |
12943 | bfd_byte *buf; | |
12944 | unsigned long insn; | |
12945 | expressionS exp; | |
12946 | fixS *fixp; | |
b34976b6 | 12947 | |
4a6a3df4 AO |
12948 | buf = (bfd_byte *)fragp->fr_literal + fragp->fr_fix; |
12949 | ||
12950 | if (target_big_endian) | |
12951 | insn = bfd_getb32 (buf); | |
12952 | else | |
12953 | insn = bfd_getl32 (buf); | |
b34976b6 | 12954 | |
4a6a3df4 AO |
12955 | if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) |
12956 | { | |
12957 | /* We generate a fixup instead of applying it right now | |
12958 | because, if there are linker relaxations, we're going to | |
12959 | need the relocations. */ | |
12960 | exp.X_op = O_symbol; | |
12961 | exp.X_add_symbol = fragp->fr_symbol; | |
12962 | exp.X_add_number = fragp->fr_offset; | |
12963 | ||
12964 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
0b25d3e6 AO |
12965 | 4, &exp, 1, |
12966 | BFD_RELOC_16_PCREL_S2); | |
4a6a3df4 AO |
12967 | fixp->fx_file = fragp->fr_file; |
12968 | fixp->fx_line = fragp->fr_line; | |
b34976b6 | 12969 | |
2132e3a3 | 12970 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
12971 | buf += 4; |
12972 | } | |
12973 | else | |
12974 | { | |
12975 | int i; | |
12976 | ||
12977 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
12978 | _("relaxed out-of-range branch into a jump")); | |
12979 | ||
12980 | if (RELAX_BRANCH_UNCOND (fragp->fr_subtype)) | |
12981 | goto uncond; | |
12982 | ||
12983 | if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
12984 | { | |
12985 | /* Reverse the branch. */ | |
12986 | switch ((insn >> 28) & 0xf) | |
12987 | { | |
12988 | case 4: | |
12989 | /* bc[0-3][tf]l? and bc1any[24][ft] instructions can | |
12990 | have the condition reversed by tweaking a single | |
12991 | bit, and their opcodes all have 0x4???????. */ | |
12992 | assert ((insn & 0xf1000000) == 0x41000000); | |
12993 | insn ^= 0x00010000; | |
12994 | break; | |
12995 | ||
12996 | case 0: | |
12997 | /* bltz 0x04000000 bgez 0x04010000 | |
12998 | bltzal 0x04100000 bgezal 0x04110000 */ | |
12999 | assert ((insn & 0xfc0e0000) == 0x04000000); | |
13000 | insn ^= 0x00010000; | |
13001 | break; | |
b34976b6 | 13002 | |
4a6a3df4 AO |
13003 | case 1: |
13004 | /* beq 0x10000000 bne 0x14000000 | |
13005 | blez 0x18000000 bgtz 0x1c000000 */ | |
13006 | insn ^= 0x04000000; | |
13007 | break; | |
13008 | ||
13009 | default: | |
13010 | abort (); | |
13011 | } | |
13012 | } | |
13013 | ||
13014 | if (RELAX_BRANCH_LINK (fragp->fr_subtype)) | |
13015 | { | |
13016 | /* Clear the and-link bit. */ | |
13017 | assert ((insn & 0xfc1c0000) == 0x04100000); | |
13018 | ||
13019 | /* bltzal 0x04100000 bgezal 0x04110000 | |
13020 | bltzall 0x04120000 bgezall 0x04130000 */ | |
13021 | insn &= ~0x00100000; | |
13022 | } | |
13023 | ||
13024 | /* Branch over the branch (if the branch was likely) or the | |
13025 | full jump (not likely case). Compute the offset from the | |
13026 | current instruction to branch to. */ | |
13027 | if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
13028 | i = 16; | |
13029 | else | |
13030 | { | |
13031 | /* How many bytes in instructions we've already emitted? */ | |
13032 | i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix; | |
13033 | /* How many bytes in instructions from here to the end? */ | |
13034 | i = fragp->fr_var - i; | |
13035 | } | |
13036 | /* Convert to instruction count. */ | |
13037 | i >>= 2; | |
13038 | /* Branch counts from the next instruction. */ | |
b34976b6 | 13039 | i--; |
4a6a3df4 AO |
13040 | insn |= i; |
13041 | /* Branch over the jump. */ | |
2132e3a3 | 13042 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
13043 | buf += 4; |
13044 | ||
13045 | /* Nop */ | |
2132e3a3 | 13046 | md_number_to_chars ((char *) buf, 0, 4); |
4a6a3df4 AO |
13047 | buf += 4; |
13048 | ||
13049 | if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
13050 | { | |
13051 | /* beql $0, $0, 2f */ | |
13052 | insn = 0x50000000; | |
13053 | /* Compute the PC offset from the current instruction to | |
13054 | the end of the variable frag. */ | |
13055 | /* How many bytes in instructions we've already emitted? */ | |
13056 | i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix; | |
13057 | /* How many bytes in instructions from here to the end? */ | |
13058 | i = fragp->fr_var - i; | |
13059 | /* Convert to instruction count. */ | |
13060 | i >>= 2; | |
13061 | /* Don't decrement i, because we want to branch over the | |
13062 | delay slot. */ | |
13063 | ||
13064 | insn |= i; | |
2132e3a3 | 13065 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
13066 | buf += 4; |
13067 | ||
2132e3a3 | 13068 | md_number_to_chars ((char *) buf, 0, 4); |
4a6a3df4 AO |
13069 | buf += 4; |
13070 | } | |
13071 | ||
13072 | uncond: | |
13073 | if (mips_pic == NO_PIC) | |
13074 | { | |
13075 | /* j or jal. */ | |
13076 | insn = (RELAX_BRANCH_LINK (fragp->fr_subtype) | |
13077 | ? 0x0c000000 : 0x08000000); | |
13078 | exp.X_op = O_symbol; | |
13079 | exp.X_add_symbol = fragp->fr_symbol; | |
13080 | exp.X_add_number = fragp->fr_offset; | |
13081 | ||
13082 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
13083 | 4, &exp, 0, BFD_RELOC_MIPS_JMP); | |
13084 | fixp->fx_file = fragp->fr_file; | |
13085 | fixp->fx_line = fragp->fr_line; | |
13086 | ||
2132e3a3 | 13087 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
13088 | buf += 4; |
13089 | } | |
13090 | else | |
13091 | { | |
13092 | /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */ | |
13093 | insn = HAVE_64BIT_ADDRESSES ? 0xdf810000 : 0x8f810000; | |
13094 | exp.X_op = O_symbol; | |
13095 | exp.X_add_symbol = fragp->fr_symbol; | |
13096 | exp.X_add_number = fragp->fr_offset; | |
13097 | ||
13098 | if (fragp->fr_offset) | |
13099 | { | |
13100 | exp.X_add_symbol = make_expr_symbol (&exp); | |
13101 | exp.X_add_number = 0; | |
13102 | } | |
13103 | ||
13104 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
13105 | 4, &exp, 0, BFD_RELOC_MIPS_GOT16); | |
13106 | fixp->fx_file = fragp->fr_file; | |
13107 | fixp->fx_line = fragp->fr_line; | |
13108 | ||
2132e3a3 | 13109 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 | 13110 | buf += 4; |
b34976b6 | 13111 | |
4a6a3df4 AO |
13112 | if (mips_opts.isa == ISA_MIPS1) |
13113 | { | |
13114 | /* nop */ | |
2132e3a3 | 13115 | md_number_to_chars ((char *) buf, 0, 4); |
4a6a3df4 AO |
13116 | buf += 4; |
13117 | } | |
13118 | ||
13119 | /* d/addiu $at, $at, <sym> R_MIPS_LO16 */ | |
13120 | insn = HAVE_64BIT_ADDRESSES ? 0x64210000 : 0x24210000; | |
13121 | ||
13122 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
13123 | 4, &exp, 0, BFD_RELOC_LO16); | |
13124 | fixp->fx_file = fragp->fr_file; | |
13125 | fixp->fx_line = fragp->fr_line; | |
b34976b6 | 13126 | |
2132e3a3 | 13127 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
13128 | buf += 4; |
13129 | ||
13130 | /* j(al)r $at. */ | |
13131 | if (RELAX_BRANCH_LINK (fragp->fr_subtype)) | |
13132 | insn = 0x0020f809; | |
13133 | else | |
13134 | insn = 0x00200008; | |
13135 | ||
2132e3a3 | 13136 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
13137 | buf += 4; |
13138 | } | |
13139 | } | |
13140 | ||
13141 | assert (buf == (bfd_byte *)fragp->fr_literal | |
13142 | + fragp->fr_fix + fragp->fr_var); | |
13143 | ||
13144 | fragp->fr_fix += fragp->fr_var; | |
13145 | ||
13146 | return; | |
13147 | } | |
13148 | ||
252b5132 RH |
13149 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
13150 | { | |
13151 | int type; | |
13152 | register const struct mips16_immed_operand *op; | |
b34976b6 | 13153 | bfd_boolean small, ext; |
252b5132 RH |
13154 | offsetT val; |
13155 | bfd_byte *buf; | |
13156 | unsigned long insn; | |
b34976b6 | 13157 | bfd_boolean use_extend; |
252b5132 RH |
13158 | unsigned short extend; |
13159 | ||
13160 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
13161 | op = mips16_immed_operands; | |
13162 | while (op->type != type) | |
13163 | ++op; | |
13164 | ||
13165 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
13166 | { | |
b34976b6 AM |
13167 | small = FALSE; |
13168 | ext = TRUE; | |
252b5132 RH |
13169 | } |
13170 | else | |
13171 | { | |
b34976b6 AM |
13172 | small = TRUE; |
13173 | ext = FALSE; | |
252b5132 RH |
13174 | } |
13175 | ||
6386f3a7 | 13176 | resolve_symbol_value (fragp->fr_symbol); |
252b5132 RH |
13177 | val = S_GET_VALUE (fragp->fr_symbol); |
13178 | if (op->pcrel) | |
13179 | { | |
13180 | addressT addr; | |
13181 | ||
13182 | addr = fragp->fr_address + fragp->fr_fix; | |
13183 | ||
13184 | /* The rules for the base address of a PC relative reloc are | |
13185 | complicated; see mips16_extended_frag. */ | |
13186 | if (type == 'p' || type == 'q') | |
13187 | { | |
13188 | addr += 2; | |
13189 | if (ext) | |
13190 | addr += 2; | |
13191 | /* Ignore the low bit in the target, since it will be | |
13192 | set for a text label. */ | |
13193 | if ((val & 1) != 0) | |
13194 | --val; | |
13195 | } | |
13196 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) | |
13197 | addr -= 4; | |
13198 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
13199 | addr -= 2; | |
13200 | ||
13201 | addr &= ~ (addressT) ((1 << op->shift) - 1); | |
13202 | val -= addr; | |
13203 | ||
13204 | /* Make sure the section winds up with the alignment we have | |
13205 | assumed. */ | |
13206 | if (op->shift > 0) | |
13207 | record_alignment (asec, op->shift); | |
13208 | } | |
13209 | ||
13210 | if (ext | |
13211 | && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype) | |
13212 | || RELAX_MIPS16_DSLOT (fragp->fr_subtype))) | |
13213 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
13214 | _("extended instruction in delay slot")); | |
13215 | ||
13216 | buf = (bfd_byte *) (fragp->fr_literal + fragp->fr_fix); | |
13217 | ||
13218 | if (target_big_endian) | |
13219 | insn = bfd_getb16 (buf); | |
13220 | else | |
13221 | insn = bfd_getl16 (buf); | |
13222 | ||
13223 | mips16_immed (fragp->fr_file, fragp->fr_line, type, val, | |
13224 | RELAX_MIPS16_USER_EXT (fragp->fr_subtype), | |
13225 | small, ext, &insn, &use_extend, &extend); | |
13226 | ||
13227 | if (use_extend) | |
13228 | { | |
2132e3a3 | 13229 | md_number_to_chars ((char *) buf, 0xf000 | extend, 2); |
252b5132 RH |
13230 | fragp->fr_fix += 2; |
13231 | buf += 2; | |
13232 | } | |
13233 | ||
2132e3a3 | 13234 | md_number_to_chars ((char *) buf, insn, 2); |
252b5132 RH |
13235 | fragp->fr_fix += 2; |
13236 | buf += 2; | |
13237 | } | |
13238 | else | |
13239 | { | |
4d7206a2 RS |
13240 | int first, second; |
13241 | fixS *fixp; | |
252b5132 | 13242 | |
4d7206a2 RS |
13243 | first = RELAX_FIRST (fragp->fr_subtype); |
13244 | second = RELAX_SECOND (fragp->fr_subtype); | |
13245 | fixp = (fixS *) fragp->fr_opcode; | |
252b5132 | 13246 | |
584892a6 RS |
13247 | /* Possibly emit a warning if we've chosen the longer option. */ |
13248 | if (((fragp->fr_subtype & RELAX_USE_SECOND) != 0) | |
13249 | == ((fragp->fr_subtype & RELAX_SECOND_LONGER) != 0)) | |
13250 | { | |
13251 | const char *msg = macro_warning (fragp->fr_subtype); | |
13252 | if (msg != 0) | |
13253 | as_warn_where (fragp->fr_file, fragp->fr_line, msg); | |
13254 | } | |
13255 | ||
4d7206a2 RS |
13256 | /* Go through all the fixups for the first sequence. Disable them |
13257 | (by marking them as done) if we're going to use the second | |
13258 | sequence instead. */ | |
13259 | while (fixp | |
13260 | && fixp->fx_frag == fragp | |
13261 | && fixp->fx_where < fragp->fr_fix - second) | |
13262 | { | |
13263 | if (fragp->fr_subtype & RELAX_USE_SECOND) | |
13264 | fixp->fx_done = 1; | |
13265 | fixp = fixp->fx_next; | |
13266 | } | |
252b5132 | 13267 | |
4d7206a2 RS |
13268 | /* Go through the fixups for the second sequence. Disable them if |
13269 | we're going to use the first sequence, otherwise adjust their | |
13270 | addresses to account for the relaxation. */ | |
13271 | while (fixp && fixp->fx_frag == fragp) | |
13272 | { | |
13273 | if (fragp->fr_subtype & RELAX_USE_SECOND) | |
13274 | fixp->fx_where -= first; | |
13275 | else | |
13276 | fixp->fx_done = 1; | |
13277 | fixp = fixp->fx_next; | |
13278 | } | |
13279 | ||
13280 | /* Now modify the frag contents. */ | |
13281 | if (fragp->fr_subtype & RELAX_USE_SECOND) | |
13282 | { | |
13283 | char *start; | |
13284 | ||
13285 | start = fragp->fr_literal + fragp->fr_fix - first - second; | |
13286 | memmove (start, start + first, second); | |
13287 | fragp->fr_fix -= first; | |
13288 | } | |
13289 | else | |
13290 | fragp->fr_fix -= second; | |
252b5132 RH |
13291 | } |
13292 | } | |
13293 | ||
13294 | #ifdef OBJ_ELF | |
13295 | ||
13296 | /* This function is called after the relocs have been generated. | |
13297 | We've been storing mips16 text labels as odd. Here we convert them | |
13298 | back to even for the convenience of the debugger. */ | |
13299 | ||
13300 | void | |
17a2f251 | 13301 | mips_frob_file_after_relocs (void) |
252b5132 RH |
13302 | { |
13303 | asymbol **syms; | |
13304 | unsigned int count, i; | |
13305 | ||
13306 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
13307 | return; | |
13308 | ||
13309 | syms = bfd_get_outsymbols (stdoutput); | |
13310 | count = bfd_get_symcount (stdoutput); | |
13311 | for (i = 0; i < count; i++, syms++) | |
13312 | { | |
13313 | if (elf_symbol (*syms)->internal_elf_sym.st_other == STO_MIPS16 | |
13314 | && ((*syms)->value & 1) != 0) | |
13315 | { | |
13316 | (*syms)->value &= ~1; | |
13317 | /* If the symbol has an odd size, it was probably computed | |
13318 | incorrectly, so adjust that as well. */ | |
13319 | if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0) | |
13320 | ++elf_symbol (*syms)->internal_elf_sym.st_size; | |
13321 | } | |
13322 | } | |
13323 | } | |
13324 | ||
13325 | #endif | |
13326 | ||
13327 | /* This function is called whenever a label is defined. It is used | |
13328 | when handling branch delays; if a branch has a label, we assume we | |
13329 | can not move it. */ | |
13330 | ||
13331 | void | |
17a2f251 | 13332 | mips_define_label (symbolS *sym) |
252b5132 RH |
13333 | { |
13334 | struct insn_label_list *l; | |
13335 | ||
13336 | if (free_insn_labels == NULL) | |
13337 | l = (struct insn_label_list *) xmalloc (sizeof *l); | |
13338 | else | |
13339 | { | |
13340 | l = free_insn_labels; | |
13341 | free_insn_labels = l->next; | |
13342 | } | |
13343 | ||
13344 | l->label = sym; | |
13345 | l->next = insn_labels; | |
13346 | insn_labels = l; | |
13347 | } | |
13348 | \f | |
13349 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
13350 | ||
13351 | /* Some special processing for a MIPS ELF file. */ | |
13352 | ||
13353 | void | |
17a2f251 | 13354 | mips_elf_final_processing (void) |
252b5132 RH |
13355 | { |
13356 | /* Write out the register information. */ | |
316f5878 | 13357 | if (mips_abi != N64_ABI) |
252b5132 RH |
13358 | { |
13359 | Elf32_RegInfo s; | |
13360 | ||
13361 | s.ri_gprmask = mips_gprmask; | |
13362 | s.ri_cprmask[0] = mips_cprmask[0]; | |
13363 | s.ri_cprmask[1] = mips_cprmask[1]; | |
13364 | s.ri_cprmask[2] = mips_cprmask[2]; | |
13365 | s.ri_cprmask[3] = mips_cprmask[3]; | |
13366 | /* The gp_value field is set by the MIPS ELF backend. */ | |
13367 | ||
13368 | bfd_mips_elf32_swap_reginfo_out (stdoutput, &s, | |
13369 | ((Elf32_External_RegInfo *) | |
13370 | mips_regmask_frag)); | |
13371 | } | |
13372 | else | |
13373 | { | |
13374 | Elf64_Internal_RegInfo s; | |
13375 | ||
13376 | s.ri_gprmask = mips_gprmask; | |
13377 | s.ri_pad = 0; | |
13378 | s.ri_cprmask[0] = mips_cprmask[0]; | |
13379 | s.ri_cprmask[1] = mips_cprmask[1]; | |
13380 | s.ri_cprmask[2] = mips_cprmask[2]; | |
13381 | s.ri_cprmask[3] = mips_cprmask[3]; | |
13382 | /* The gp_value field is set by the MIPS ELF backend. */ | |
13383 | ||
13384 | bfd_mips_elf64_swap_reginfo_out (stdoutput, &s, | |
13385 | ((Elf64_External_RegInfo *) | |
13386 | mips_regmask_frag)); | |
13387 | } | |
13388 | ||
13389 | /* Set the MIPS ELF flag bits. FIXME: There should probably be some | |
13390 | sort of BFD interface for this. */ | |
13391 | if (mips_any_noreorder) | |
13392 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER; | |
13393 | if (mips_pic != NO_PIC) | |
143d77c5 | 13394 | { |
252b5132 | 13395 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC; |
143d77c5 EC |
13396 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC; |
13397 | } | |
13398 | if (mips_abicalls) | |
13399 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC; | |
252b5132 | 13400 | |
98d3f06f | 13401 | /* Set MIPS ELF flags for ASEs. */ |
a4672219 TS |
13402 | if (file_ase_mips16) |
13403 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16; | |
1f25f5d3 CD |
13404 | #if 0 /* XXX FIXME */ |
13405 | if (file_ase_mips3d) | |
13406 | elf_elfheader (stdoutput)->e_flags |= ???; | |
13407 | #endif | |
deec1734 CD |
13408 | if (file_ase_mdmx) |
13409 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX; | |
1f25f5d3 | 13410 | |
bdaaa2e1 | 13411 | /* Set the MIPS ELF ABI flags. */ |
316f5878 | 13412 | if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32) |
252b5132 | 13413 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32; |
316f5878 | 13414 | else if (mips_abi == O64_ABI) |
252b5132 | 13415 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64; |
316f5878 | 13416 | else if (mips_abi == EABI_ABI) |
252b5132 | 13417 | { |
316f5878 | 13418 | if (!file_mips_gp32) |
252b5132 RH |
13419 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64; |
13420 | else | |
13421 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32; | |
13422 | } | |
316f5878 | 13423 | else if (mips_abi == N32_ABI) |
be00bddd TS |
13424 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2; |
13425 | ||
c9914766 | 13426 | /* Nothing to do for N64_ABI. */ |
252b5132 RH |
13427 | |
13428 | if (mips_32bitmode) | |
13429 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE; | |
13430 | } | |
13431 | ||
13432 | #endif /* OBJ_ELF || OBJ_MAYBE_ELF */ | |
13433 | \f | |
beae10d5 | 13434 | typedef struct proc { |
9b2f1d35 EC |
13435 | symbolS *func_sym; |
13436 | symbolS *func_end_sym; | |
beae10d5 KH |
13437 | unsigned long reg_mask; |
13438 | unsigned long reg_offset; | |
13439 | unsigned long fpreg_mask; | |
13440 | unsigned long fpreg_offset; | |
13441 | unsigned long frame_offset; | |
13442 | unsigned long frame_reg; | |
13443 | unsigned long pc_reg; | |
13444 | } procS; | |
252b5132 RH |
13445 | |
13446 | static procS cur_proc; | |
13447 | static procS *cur_proc_ptr; | |
13448 | static int numprocs; | |
13449 | ||
0a9ef439 | 13450 | /* Fill in an rs_align_code fragment. */ |
a19d8eb0 | 13451 | |
0a9ef439 | 13452 | void |
17a2f251 | 13453 | mips_handle_align (fragS *fragp) |
a19d8eb0 | 13454 | { |
0a9ef439 RH |
13455 | if (fragp->fr_type != rs_align_code) |
13456 | return; | |
13457 | ||
13458 | if (mips_opts.mips16) | |
a19d8eb0 CP |
13459 | { |
13460 | static const unsigned char be_nop[] = { 0x65, 0x00 }; | |
13461 | static const unsigned char le_nop[] = { 0x00, 0x65 }; | |
13462 | ||
0a9ef439 RH |
13463 | int bytes; |
13464 | char *p; | |
a19d8eb0 | 13465 | |
0a9ef439 RH |
13466 | bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix; |
13467 | p = fragp->fr_literal + fragp->fr_fix; | |
13468 | ||
13469 | if (bytes & 1) | |
13470 | { | |
13471 | *p++ = 0; | |
f9419b05 | 13472 | fragp->fr_fix++; |
0a9ef439 RH |
13473 | } |
13474 | ||
13475 | memcpy (p, (target_big_endian ? be_nop : le_nop), 2); | |
13476 | fragp->fr_var = 2; | |
a19d8eb0 CP |
13477 | } |
13478 | ||
0a9ef439 | 13479 | /* For mips32, a nop is a zero, which we trivially get by doing nothing. */ |
a19d8eb0 CP |
13480 | } |
13481 | ||
252b5132 | 13482 | static void |
17a2f251 | 13483 | md_obj_begin (void) |
252b5132 RH |
13484 | { |
13485 | } | |
13486 | ||
13487 | static void | |
17a2f251 | 13488 | md_obj_end (void) |
252b5132 RH |
13489 | { |
13490 | /* check for premature end, nesting errors, etc */ | |
13491 | if (cur_proc_ptr) | |
9a41af64 | 13492 | as_warn (_("missing .end at end of assembly")); |
252b5132 RH |
13493 | } |
13494 | ||
13495 | static long | |
17a2f251 | 13496 | get_number (void) |
252b5132 RH |
13497 | { |
13498 | int negative = 0; | |
13499 | long val = 0; | |
13500 | ||
13501 | if (*input_line_pointer == '-') | |
13502 | { | |
13503 | ++input_line_pointer; | |
13504 | negative = 1; | |
13505 | } | |
3882b010 | 13506 | if (!ISDIGIT (*input_line_pointer)) |
956cd1d6 | 13507 | as_bad (_("expected simple number")); |
252b5132 RH |
13508 | if (input_line_pointer[0] == '0') |
13509 | { | |
13510 | if (input_line_pointer[1] == 'x') | |
13511 | { | |
13512 | input_line_pointer += 2; | |
3882b010 | 13513 | while (ISXDIGIT (*input_line_pointer)) |
252b5132 RH |
13514 | { |
13515 | val <<= 4; | |
13516 | val |= hex_value (*input_line_pointer++); | |
13517 | } | |
13518 | return negative ? -val : val; | |
13519 | } | |
13520 | else | |
13521 | { | |
13522 | ++input_line_pointer; | |
3882b010 | 13523 | while (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
13524 | { |
13525 | val <<= 3; | |
13526 | val |= *input_line_pointer++ - '0'; | |
13527 | } | |
13528 | return negative ? -val : val; | |
13529 | } | |
13530 | } | |
3882b010 | 13531 | if (!ISDIGIT (*input_line_pointer)) |
252b5132 RH |
13532 | { |
13533 | printf (_(" *input_line_pointer == '%c' 0x%02x\n"), | |
13534 | *input_line_pointer, *input_line_pointer); | |
956cd1d6 | 13535 | as_warn (_("invalid number")); |
252b5132 RH |
13536 | return -1; |
13537 | } | |
3882b010 | 13538 | while (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
13539 | { |
13540 | val *= 10; | |
13541 | val += *input_line_pointer++ - '0'; | |
13542 | } | |
13543 | return negative ? -val : val; | |
13544 | } | |
13545 | ||
13546 | /* The .file directive; just like the usual .file directive, but there | |
c5dd6aab DJ |
13547 | is an initial number which is the ECOFF file index. In the non-ECOFF |
13548 | case .file implies DWARF-2. */ | |
13549 | ||
13550 | static void | |
17a2f251 | 13551 | s_mips_file (int x ATTRIBUTE_UNUSED) |
c5dd6aab | 13552 | { |
ecb4347a DJ |
13553 | static int first_file_directive = 0; |
13554 | ||
c5dd6aab DJ |
13555 | if (ECOFF_DEBUGGING) |
13556 | { | |
13557 | get_number (); | |
13558 | s_app_file (0); | |
13559 | } | |
13560 | else | |
ecb4347a DJ |
13561 | { |
13562 | char *filename; | |
13563 | ||
13564 | filename = dwarf2_directive_file (0); | |
13565 | ||
13566 | /* Versions of GCC up to 3.1 start files with a ".file" | |
13567 | directive even for stabs output. Make sure that this | |
13568 | ".file" is handled. Note that you need a version of GCC | |
13569 | after 3.1 in order to support DWARF-2 on MIPS. */ | |
13570 | if (filename != NULL && ! first_file_directive) | |
13571 | { | |
13572 | (void) new_logical_line (filename, -1); | |
c04f5787 | 13573 | s_app_file_string (filename, 0); |
ecb4347a DJ |
13574 | } |
13575 | first_file_directive = 1; | |
13576 | } | |
c5dd6aab DJ |
13577 | } |
13578 | ||
13579 | /* The .loc directive, implying DWARF-2. */ | |
252b5132 RH |
13580 | |
13581 | static void | |
17a2f251 | 13582 | s_mips_loc (int x ATTRIBUTE_UNUSED) |
252b5132 | 13583 | { |
c5dd6aab DJ |
13584 | if (!ECOFF_DEBUGGING) |
13585 | dwarf2_directive_loc (0); | |
252b5132 RH |
13586 | } |
13587 | ||
252b5132 RH |
13588 | /* The .end directive. */ |
13589 | ||
13590 | static void | |
17a2f251 | 13591 | s_mips_end (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
13592 | { |
13593 | symbolS *p; | |
252b5132 | 13594 | |
7a621144 DJ |
13595 | /* Following functions need their own .frame and .cprestore directives. */ |
13596 | mips_frame_reg_valid = 0; | |
13597 | mips_cprestore_valid = 0; | |
13598 | ||
252b5132 RH |
13599 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
13600 | { | |
13601 | p = get_symbol (); | |
13602 | demand_empty_rest_of_line (); | |
13603 | } | |
13604 | else | |
13605 | p = NULL; | |
13606 | ||
14949570 | 13607 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0) |
252b5132 RH |
13608 | as_warn (_(".end not in text section")); |
13609 | ||
13610 | if (!cur_proc_ptr) | |
13611 | { | |
13612 | as_warn (_(".end directive without a preceding .ent directive.")); | |
13613 | demand_empty_rest_of_line (); | |
13614 | return; | |
13615 | } | |
13616 | ||
13617 | if (p != NULL) | |
13618 | { | |
13619 | assert (S_GET_NAME (p)); | |
9b2f1d35 | 13620 | if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->func_sym))) |
252b5132 | 13621 | as_warn (_(".end symbol does not match .ent symbol.")); |
ecb4347a DJ |
13622 | |
13623 | if (debug_type == DEBUG_STABS) | |
13624 | stabs_generate_asm_endfunc (S_GET_NAME (p), | |
13625 | S_GET_NAME (p)); | |
252b5132 RH |
13626 | } |
13627 | else | |
13628 | as_warn (_(".end directive missing or unknown symbol")); | |
13629 | ||
2132e3a3 | 13630 | #ifdef OBJ_ELF |
9b2f1d35 EC |
13631 | /* Create an expression to calculate the size of the function. */ |
13632 | if (p && cur_proc_ptr) | |
13633 | { | |
13634 | OBJ_SYMFIELD_TYPE *obj = symbol_get_obj (p); | |
13635 | expressionS *exp = xmalloc (sizeof (expressionS)); | |
13636 | ||
13637 | obj->size = exp; | |
13638 | exp->X_op = O_subtract; | |
13639 | exp->X_add_symbol = symbol_temp_new_now (); | |
13640 | exp->X_op_symbol = p; | |
13641 | exp->X_add_number = 0; | |
13642 | ||
13643 | cur_proc_ptr->func_end_sym = exp->X_add_symbol; | |
13644 | } | |
13645 | ||
ecb4347a | 13646 | /* Generate a .pdr section. */ |
dcd410fe RO |
13647 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING |
13648 | && mips_flag_pdr) | |
ecb4347a DJ |
13649 | { |
13650 | segT saved_seg = now_seg; | |
13651 | subsegT saved_subseg = now_subseg; | |
13652 | valueT dot; | |
13653 | expressionS exp; | |
13654 | char *fragp; | |
252b5132 | 13655 | |
ecb4347a | 13656 | dot = frag_now_fix (); |
252b5132 RH |
13657 | |
13658 | #ifdef md_flush_pending_output | |
ecb4347a | 13659 | md_flush_pending_output (); |
252b5132 RH |
13660 | #endif |
13661 | ||
ecb4347a DJ |
13662 | assert (pdr_seg); |
13663 | subseg_set (pdr_seg, 0); | |
252b5132 | 13664 | |
ecb4347a DJ |
13665 | /* Write the symbol. */ |
13666 | exp.X_op = O_symbol; | |
13667 | exp.X_add_symbol = p; | |
13668 | exp.X_add_number = 0; | |
13669 | emit_expr (&exp, 4); | |
252b5132 | 13670 | |
ecb4347a | 13671 | fragp = frag_more (7 * 4); |
252b5132 | 13672 | |
17a2f251 TS |
13673 | md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4); |
13674 | md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4); | |
13675 | md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4); | |
13676 | md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4); | |
13677 | md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4); | |
13678 | md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4); | |
13679 | md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4); | |
252b5132 | 13680 | |
ecb4347a DJ |
13681 | subseg_set (saved_seg, saved_subseg); |
13682 | } | |
13683 | #endif /* OBJ_ELF */ | |
252b5132 RH |
13684 | |
13685 | cur_proc_ptr = NULL; | |
13686 | } | |
13687 | ||
13688 | /* The .aent and .ent directives. */ | |
13689 | ||
13690 | static void | |
17a2f251 | 13691 | s_mips_ent (int aent) |
252b5132 | 13692 | { |
252b5132 | 13693 | symbolS *symbolP; |
252b5132 RH |
13694 | |
13695 | symbolP = get_symbol (); | |
13696 | if (*input_line_pointer == ',') | |
f9419b05 | 13697 | ++input_line_pointer; |
252b5132 | 13698 | SKIP_WHITESPACE (); |
3882b010 | 13699 | if (ISDIGIT (*input_line_pointer) |
d9a62219 | 13700 | || *input_line_pointer == '-') |
874e8986 | 13701 | get_number (); |
252b5132 | 13702 | |
14949570 | 13703 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0) |
252b5132 RH |
13704 | as_warn (_(".ent or .aent not in text section.")); |
13705 | ||
13706 | if (!aent && cur_proc_ptr) | |
9a41af64 | 13707 | as_warn (_("missing .end")); |
252b5132 RH |
13708 | |
13709 | if (!aent) | |
13710 | { | |
7a621144 DJ |
13711 | /* This function needs its own .frame and .cprestore directives. */ |
13712 | mips_frame_reg_valid = 0; | |
13713 | mips_cprestore_valid = 0; | |
13714 | ||
252b5132 RH |
13715 | cur_proc_ptr = &cur_proc; |
13716 | memset (cur_proc_ptr, '\0', sizeof (procS)); | |
13717 | ||
9b2f1d35 | 13718 | cur_proc_ptr->func_sym = symbolP; |
252b5132 | 13719 | |
49309057 | 13720 | symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION; |
252b5132 | 13721 | |
f9419b05 | 13722 | ++numprocs; |
ecb4347a DJ |
13723 | |
13724 | if (debug_type == DEBUG_STABS) | |
13725 | stabs_generate_asm_func (S_GET_NAME (symbolP), | |
13726 | S_GET_NAME (symbolP)); | |
252b5132 RH |
13727 | } |
13728 | ||
13729 | demand_empty_rest_of_line (); | |
13730 | } | |
13731 | ||
13732 | /* The .frame directive. If the mdebug section is present (IRIX 5 native) | |
bdaaa2e1 | 13733 | then ecoff.c (ecoff_directive_frame) is used. For embedded targets, |
252b5132 | 13734 | s_mips_frame is used so that we can set the PDR information correctly. |
bdaaa2e1 | 13735 | We can't use the ecoff routines because they make reference to the ecoff |
252b5132 RH |
13736 | symbol table (in the mdebug section). */ |
13737 | ||
13738 | static void | |
17a2f251 | 13739 | s_mips_frame (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 13740 | { |
ecb4347a DJ |
13741 | #ifdef OBJ_ELF |
13742 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING) | |
13743 | { | |
13744 | long val; | |
252b5132 | 13745 | |
ecb4347a DJ |
13746 | if (cur_proc_ptr == (procS *) NULL) |
13747 | { | |
13748 | as_warn (_(".frame outside of .ent")); | |
13749 | demand_empty_rest_of_line (); | |
13750 | return; | |
13751 | } | |
252b5132 | 13752 | |
ecb4347a DJ |
13753 | cur_proc_ptr->frame_reg = tc_get_register (1); |
13754 | ||
13755 | SKIP_WHITESPACE (); | |
13756 | if (*input_line_pointer++ != ',' | |
13757 | || get_absolute_expression_and_terminator (&val) != ',') | |
13758 | { | |
13759 | as_warn (_("Bad .frame directive")); | |
13760 | --input_line_pointer; | |
13761 | demand_empty_rest_of_line (); | |
13762 | return; | |
13763 | } | |
252b5132 | 13764 | |
ecb4347a DJ |
13765 | cur_proc_ptr->frame_offset = val; |
13766 | cur_proc_ptr->pc_reg = tc_get_register (0); | |
252b5132 | 13767 | |
252b5132 | 13768 | demand_empty_rest_of_line (); |
252b5132 | 13769 | } |
ecb4347a DJ |
13770 | else |
13771 | #endif /* OBJ_ELF */ | |
13772 | s_ignore (ignore); | |
252b5132 RH |
13773 | } |
13774 | ||
bdaaa2e1 KH |
13775 | /* The .fmask and .mask directives. If the mdebug section is present |
13776 | (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For | |
252b5132 | 13777 | embedded targets, s_mips_mask is used so that we can set the PDR |
bdaaa2e1 | 13778 | information correctly. We can't use the ecoff routines because they |
252b5132 RH |
13779 | make reference to the ecoff symbol table (in the mdebug section). */ |
13780 | ||
13781 | static void | |
17a2f251 | 13782 | s_mips_mask (int reg_type) |
252b5132 | 13783 | { |
ecb4347a DJ |
13784 | #ifdef OBJ_ELF |
13785 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING) | |
252b5132 | 13786 | { |
ecb4347a | 13787 | long mask, off; |
252b5132 | 13788 | |
ecb4347a DJ |
13789 | if (cur_proc_ptr == (procS *) NULL) |
13790 | { | |
13791 | as_warn (_(".mask/.fmask outside of .ent")); | |
13792 | demand_empty_rest_of_line (); | |
13793 | return; | |
13794 | } | |
252b5132 | 13795 | |
ecb4347a DJ |
13796 | if (get_absolute_expression_and_terminator (&mask) != ',') |
13797 | { | |
13798 | as_warn (_("Bad .mask/.fmask directive")); | |
13799 | --input_line_pointer; | |
13800 | demand_empty_rest_of_line (); | |
13801 | return; | |
13802 | } | |
252b5132 | 13803 | |
ecb4347a DJ |
13804 | off = get_absolute_expression (); |
13805 | ||
13806 | if (reg_type == 'F') | |
13807 | { | |
13808 | cur_proc_ptr->fpreg_mask = mask; | |
13809 | cur_proc_ptr->fpreg_offset = off; | |
13810 | } | |
13811 | else | |
13812 | { | |
13813 | cur_proc_ptr->reg_mask = mask; | |
13814 | cur_proc_ptr->reg_offset = off; | |
13815 | } | |
13816 | ||
13817 | demand_empty_rest_of_line (); | |
252b5132 RH |
13818 | } |
13819 | else | |
ecb4347a DJ |
13820 | #endif /* OBJ_ELF */ |
13821 | s_ignore (reg_type); | |
252b5132 RH |
13822 | } |
13823 | ||
316f5878 RS |
13824 | /* A table describing all the processors gas knows about. Names are |
13825 | matched in the order listed. | |
e7af610e | 13826 | |
316f5878 RS |
13827 | To ease comparison, please keep this table in the same order as |
13828 | gcc's mips_cpu_info_table[]. */ | |
e972090a NC |
13829 | static const struct mips_cpu_info mips_cpu_info_table[] = |
13830 | { | |
316f5878 RS |
13831 | /* Entries for generic ISAs */ |
13832 | { "mips1", 1, ISA_MIPS1, CPU_R3000 }, | |
13833 | { "mips2", 1, ISA_MIPS2, CPU_R6000 }, | |
13834 | { "mips3", 1, ISA_MIPS3, CPU_R4000 }, | |
13835 | { "mips4", 1, ISA_MIPS4, CPU_R8000 }, | |
13836 | { "mips5", 1, ISA_MIPS5, CPU_MIPS5 }, | |
13837 | { "mips32", 1, ISA_MIPS32, CPU_MIPS32 }, | |
af7ee8bf | 13838 | { "mips32r2", 1, ISA_MIPS32R2, CPU_MIPS32R2 }, |
316f5878 | 13839 | { "mips64", 1, ISA_MIPS64, CPU_MIPS64 }, |
5f74bc13 | 13840 | { "mips64r2", 1, ISA_MIPS64R2, CPU_MIPS64R2 }, |
316f5878 RS |
13841 | |
13842 | /* MIPS I */ | |
13843 | { "r3000", 0, ISA_MIPS1, CPU_R3000 }, | |
13844 | { "r2000", 0, ISA_MIPS1, CPU_R3000 }, | |
13845 | { "r3900", 0, ISA_MIPS1, CPU_R3900 }, | |
13846 | ||
13847 | /* MIPS II */ | |
13848 | { "r6000", 0, ISA_MIPS2, CPU_R6000 }, | |
13849 | ||
13850 | /* MIPS III */ | |
13851 | { "r4000", 0, ISA_MIPS3, CPU_R4000 }, | |
13852 | { "r4010", 0, ISA_MIPS2, CPU_R4010 }, | |
13853 | { "vr4100", 0, ISA_MIPS3, CPU_VR4100 }, | |
13854 | { "vr4111", 0, ISA_MIPS3, CPU_R4111 }, | |
60b63b72 RS |
13855 | { "vr4120", 0, ISA_MIPS3, CPU_VR4120 }, |
13856 | { "vr4130", 0, ISA_MIPS3, CPU_VR4120 }, | |
13857 | { "vr4181", 0, ISA_MIPS3, CPU_R4111 }, | |
316f5878 RS |
13858 | { "vr4300", 0, ISA_MIPS3, CPU_R4300 }, |
13859 | { "r4400", 0, ISA_MIPS3, CPU_R4400 }, | |
13860 | { "r4600", 0, ISA_MIPS3, CPU_R4600 }, | |
13861 | { "orion", 0, ISA_MIPS3, CPU_R4600 }, | |
13862 | { "r4650", 0, ISA_MIPS3, CPU_R4650 }, | |
13863 | ||
13864 | /* MIPS IV */ | |
13865 | { "r8000", 0, ISA_MIPS4, CPU_R8000 }, | |
13866 | { "r10000", 0, ISA_MIPS4, CPU_R10000 }, | |
13867 | { "r12000", 0, ISA_MIPS4, CPU_R12000 }, | |
13868 | { "vr5000", 0, ISA_MIPS4, CPU_R5000 }, | |
60b63b72 RS |
13869 | { "vr5400", 0, ISA_MIPS4, CPU_VR5400 }, |
13870 | { "vr5500", 0, ISA_MIPS4, CPU_VR5500 }, | |
316f5878 RS |
13871 | { "rm5200", 0, ISA_MIPS4, CPU_R5000 }, |
13872 | { "rm5230", 0, ISA_MIPS4, CPU_R5000 }, | |
13873 | { "rm5231", 0, ISA_MIPS4, CPU_R5000 }, | |
13874 | { "rm5261", 0, ISA_MIPS4, CPU_R5000 }, | |
13875 | { "rm5721", 0, ISA_MIPS4, CPU_R5000 }, | |
5a7ea749 | 13876 | { "rm7000", 0, ISA_MIPS4, CPU_RM7000 }, |
9a92f48d | 13877 | { "rm9000", 0, ISA_MIPS4, CPU_RM9000 }, |
316f5878 RS |
13878 | |
13879 | /* MIPS 32 */ | |
fef14a42 | 13880 | { "4kc", 0, ISA_MIPS32, CPU_MIPS32 }, |
316f5878 RS |
13881 | { "4km", 0, ISA_MIPS32, CPU_MIPS32 }, |
13882 | { "4kp", 0, ISA_MIPS32, CPU_MIPS32 }, | |
e7af610e | 13883 | |
316f5878 RS |
13884 | /* MIPS 64 */ |
13885 | { "5kc", 0, ISA_MIPS64, CPU_MIPS64 }, | |
13886 | { "20kc", 0, ISA_MIPS64, CPU_MIPS64 }, | |
e7af610e | 13887 | |
c7a23324 | 13888 | /* Broadcom SB-1 CPU core */ |
316f5878 | 13889 | { "sb1", 0, ISA_MIPS64, CPU_SB1 }, |
e7af610e | 13890 | |
316f5878 RS |
13891 | /* End marker */ |
13892 | { NULL, 0, 0, 0 } | |
13893 | }; | |
e7af610e | 13894 | |
84ea6cf2 | 13895 | |
316f5878 RS |
13896 | /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL |
13897 | with a final "000" replaced by "k". Ignore case. | |
e7af610e | 13898 | |
316f5878 | 13899 | Note: this function is shared between GCC and GAS. */ |
c6c98b38 | 13900 | |
b34976b6 | 13901 | static bfd_boolean |
17a2f251 | 13902 | mips_strict_matching_cpu_name_p (const char *canonical, const char *given) |
316f5878 RS |
13903 | { |
13904 | while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical)) | |
13905 | given++, canonical++; | |
13906 | ||
13907 | return ((*given == 0 && *canonical == 0) | |
13908 | || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0)); | |
13909 | } | |
13910 | ||
13911 | ||
13912 | /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied | |
13913 | CPU name. We've traditionally allowed a lot of variation here. | |
13914 | ||
13915 | Note: this function is shared between GCC and GAS. */ | |
13916 | ||
b34976b6 | 13917 | static bfd_boolean |
17a2f251 | 13918 | mips_matching_cpu_name_p (const char *canonical, const char *given) |
316f5878 RS |
13919 | { |
13920 | /* First see if the name matches exactly, or with a final "000" | |
13921 | turned into "k". */ | |
13922 | if (mips_strict_matching_cpu_name_p (canonical, given)) | |
b34976b6 | 13923 | return TRUE; |
316f5878 RS |
13924 | |
13925 | /* If not, try comparing based on numerical designation alone. | |
13926 | See if GIVEN is an unadorned number, or 'r' followed by a number. */ | |
13927 | if (TOLOWER (*given) == 'r') | |
13928 | given++; | |
13929 | if (!ISDIGIT (*given)) | |
b34976b6 | 13930 | return FALSE; |
316f5878 RS |
13931 | |
13932 | /* Skip over some well-known prefixes in the canonical name, | |
13933 | hoping to find a number there too. */ | |
13934 | if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r') | |
13935 | canonical += 2; | |
13936 | else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm') | |
13937 | canonical += 2; | |
13938 | else if (TOLOWER (canonical[0]) == 'r') | |
13939 | canonical += 1; | |
13940 | ||
13941 | return mips_strict_matching_cpu_name_p (canonical, given); | |
13942 | } | |
13943 | ||
13944 | ||
13945 | /* Parse an option that takes the name of a processor as its argument. | |
13946 | OPTION is the name of the option and CPU_STRING is the argument. | |
13947 | Return the corresponding processor enumeration if the CPU_STRING is | |
13948 | recognized, otherwise report an error and return null. | |
13949 | ||
13950 | A similar function exists in GCC. */ | |
e7af610e NC |
13951 | |
13952 | static const struct mips_cpu_info * | |
17a2f251 | 13953 | mips_parse_cpu (const char *option, const char *cpu_string) |
e7af610e | 13954 | { |
316f5878 | 13955 | const struct mips_cpu_info *p; |
e7af610e | 13956 | |
316f5878 RS |
13957 | /* 'from-abi' selects the most compatible architecture for the given |
13958 | ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the | |
13959 | EABIs, we have to decide whether we're using the 32-bit or 64-bit | |
13960 | version. Look first at the -mgp options, if given, otherwise base | |
13961 | the choice on MIPS_DEFAULT_64BIT. | |
e7af610e | 13962 | |
316f5878 RS |
13963 | Treat NO_ABI like the EABIs. One reason to do this is that the |
13964 | plain 'mips' and 'mips64' configs have 'from-abi' as their default | |
13965 | architecture. This code picks MIPS I for 'mips' and MIPS III for | |
13966 | 'mips64', just as we did in the days before 'from-abi'. */ | |
13967 | if (strcasecmp (cpu_string, "from-abi") == 0) | |
13968 | { | |
13969 | if (ABI_NEEDS_32BIT_REGS (mips_abi)) | |
13970 | return mips_cpu_info_from_isa (ISA_MIPS1); | |
13971 | ||
13972 | if (ABI_NEEDS_64BIT_REGS (mips_abi)) | |
13973 | return mips_cpu_info_from_isa (ISA_MIPS3); | |
13974 | ||
13975 | if (file_mips_gp32 >= 0) | |
13976 | return mips_cpu_info_from_isa (file_mips_gp32 ? ISA_MIPS1 : ISA_MIPS3); | |
13977 | ||
13978 | return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT | |
13979 | ? ISA_MIPS3 | |
13980 | : ISA_MIPS1); | |
13981 | } | |
13982 | ||
13983 | /* 'default' has traditionally been a no-op. Probably not very useful. */ | |
13984 | if (strcasecmp (cpu_string, "default") == 0) | |
13985 | return 0; | |
13986 | ||
13987 | for (p = mips_cpu_info_table; p->name != 0; p++) | |
13988 | if (mips_matching_cpu_name_p (p->name, cpu_string)) | |
13989 | return p; | |
13990 | ||
13991 | as_bad ("Bad value (%s) for %s", cpu_string, option); | |
13992 | return 0; | |
e7af610e NC |
13993 | } |
13994 | ||
316f5878 RS |
13995 | /* Return the canonical processor information for ISA (a member of the |
13996 | ISA_MIPS* enumeration). */ | |
13997 | ||
e7af610e | 13998 | static const struct mips_cpu_info * |
17a2f251 | 13999 | mips_cpu_info_from_isa (int isa) |
e7af610e NC |
14000 | { |
14001 | int i; | |
14002 | ||
14003 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
14004 | if (mips_cpu_info_table[i].is_isa | |
316f5878 | 14005 | && isa == mips_cpu_info_table[i].isa) |
e7af610e NC |
14006 | return (&mips_cpu_info_table[i]); |
14007 | ||
e972090a | 14008 | return NULL; |
e7af610e | 14009 | } |
fef14a42 TS |
14010 | |
14011 | static const struct mips_cpu_info * | |
17a2f251 | 14012 | mips_cpu_info_from_arch (int arch) |
fef14a42 TS |
14013 | { |
14014 | int i; | |
14015 | ||
14016 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
14017 | if (arch == mips_cpu_info_table[i].cpu) | |
14018 | return (&mips_cpu_info_table[i]); | |
14019 | ||
14020 | return NULL; | |
14021 | } | |
316f5878 RS |
14022 | \f |
14023 | static void | |
17a2f251 | 14024 | show (FILE *stream, const char *string, int *col_p, int *first_p) |
316f5878 RS |
14025 | { |
14026 | if (*first_p) | |
14027 | { | |
14028 | fprintf (stream, "%24s", ""); | |
14029 | *col_p = 24; | |
14030 | } | |
14031 | else | |
14032 | { | |
14033 | fprintf (stream, ", "); | |
14034 | *col_p += 2; | |
14035 | } | |
e7af610e | 14036 | |
316f5878 RS |
14037 | if (*col_p + strlen (string) > 72) |
14038 | { | |
14039 | fprintf (stream, "\n%24s", ""); | |
14040 | *col_p = 24; | |
14041 | } | |
14042 | ||
14043 | fprintf (stream, "%s", string); | |
14044 | *col_p += strlen (string); | |
14045 | ||
14046 | *first_p = 0; | |
14047 | } | |
14048 | ||
14049 | void | |
17a2f251 | 14050 | md_show_usage (FILE *stream) |
e7af610e | 14051 | { |
316f5878 RS |
14052 | int column, first; |
14053 | size_t i; | |
14054 | ||
14055 | fprintf (stream, _("\ | |
14056 | MIPS options:\n\ | |
316f5878 RS |
14057 | -EB generate big endian output\n\ |
14058 | -EL generate little endian output\n\ | |
14059 | -g, -g2 do not remove unneeded NOPs or swap branches\n\ | |
14060 | -G NUM allow referencing objects up to NUM bytes\n\ | |
14061 | implicitly with the gp register [default 8]\n")); | |
14062 | fprintf (stream, _("\ | |
14063 | -mips1 generate MIPS ISA I instructions\n\ | |
14064 | -mips2 generate MIPS ISA II instructions\n\ | |
14065 | -mips3 generate MIPS ISA III instructions\n\ | |
14066 | -mips4 generate MIPS ISA IV instructions\n\ | |
14067 | -mips5 generate MIPS ISA V instructions\n\ | |
14068 | -mips32 generate MIPS32 ISA instructions\n\ | |
af7ee8bf | 14069 | -mips32r2 generate MIPS32 release 2 ISA instructions\n\ |
316f5878 | 14070 | -mips64 generate MIPS64 ISA instructions\n\ |
5f74bc13 | 14071 | -mips64r2 generate MIPS64 release 2 ISA instructions\n\ |
316f5878 RS |
14072 | -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n")); |
14073 | ||
14074 | first = 1; | |
e7af610e NC |
14075 | |
14076 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
316f5878 RS |
14077 | show (stream, mips_cpu_info_table[i].name, &column, &first); |
14078 | show (stream, "from-abi", &column, &first); | |
14079 | fputc ('\n', stream); | |
e7af610e | 14080 | |
316f5878 RS |
14081 | fprintf (stream, _("\ |
14082 | -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\ | |
14083 | -no-mCPU don't generate code specific to CPU.\n\ | |
14084 | For -mCPU and -no-mCPU, CPU must be one of:\n")); | |
14085 | ||
14086 | first = 1; | |
14087 | ||
14088 | show (stream, "3900", &column, &first); | |
14089 | show (stream, "4010", &column, &first); | |
14090 | show (stream, "4100", &column, &first); | |
14091 | show (stream, "4650", &column, &first); | |
14092 | fputc ('\n', stream); | |
14093 | ||
14094 | fprintf (stream, _("\ | |
14095 | -mips16 generate mips16 instructions\n\ | |
14096 | -no-mips16 do not generate mips16 instructions\n")); | |
14097 | fprintf (stream, _("\ | |
d766e8ec | 14098 | -mfix-vr4120 work around certain VR4120 errata\n\ |
316f5878 RS |
14099 | -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\ |
14100 | -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\ | |
14101 | -O0 remove unneeded NOPs, do not swap branches\n\ | |
14102 | -O remove unneeded NOPs and swap branches\n\ | |
316f5878 RS |
14103 | --[no-]construct-floats [dis]allow floating point values to be constructed\n\ |
14104 | --trap, --no-break trap exception on div by 0 and mult overflow\n\ | |
14105 | --break, --no-trap break exception on div by 0 and mult overflow\n")); | |
14106 | #ifdef OBJ_ELF | |
14107 | fprintf (stream, _("\ | |
14108 | -KPIC, -call_shared generate SVR4 position independent code\n\ | |
14109 | -non_shared do not generate position independent code\n\ | |
14110 | -xgot assume a 32 bit GOT\n\ | |
dcd410fe | 14111 | -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\ |
316f5878 RS |
14112 | -mabi=ABI create ABI conformant object file for:\n")); |
14113 | ||
14114 | first = 1; | |
14115 | ||
14116 | show (stream, "32", &column, &first); | |
14117 | show (stream, "o64", &column, &first); | |
14118 | show (stream, "n32", &column, &first); | |
14119 | show (stream, "64", &column, &first); | |
14120 | show (stream, "eabi", &column, &first); | |
14121 | ||
14122 | fputc ('\n', stream); | |
14123 | ||
14124 | fprintf (stream, _("\ | |
14125 | -32 create o32 ABI object file (default)\n\ | |
14126 | -n32 create n32 ABI object file\n\ | |
14127 | -64 create 64 ABI object file\n")); | |
14128 | #endif | |
e7af610e | 14129 | } |
14e777e0 KB |
14130 | |
14131 | enum dwarf2_format | |
17a2f251 | 14132 | mips_dwarf2_format (void) |
14e777e0 KB |
14133 | { |
14134 | if (mips_abi == N64_ABI) | |
1de5b6a1 AO |
14135 | { |
14136 | #ifdef TE_IRIX | |
14137 | return dwarf2_format_64bit_irix; | |
14138 | #else | |
14139 | return dwarf2_format_64bit; | |
14140 | #endif | |
14141 | } | |
14e777e0 KB |
14142 | else |
14143 | return dwarf2_format_32bit; | |
14144 | } | |
73369e65 EC |
14145 | |
14146 | int | |
14147 | mips_dwarf2_addr_size (void) | |
14148 | { | |
14149 | if (mips_abi == N64_ABI) | |
14150 | return 8; | |
73369e65 EC |
14151 | else |
14152 | return 4; | |
14153 | } |