Commit | Line | Data |
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252b5132 | 1 | /* tc-mips.c -- assemble code for a MIPS chip. |
2571583a | 2 | Copyright (C) 1993-2017 Free Software Foundation, Inc. |
252b5132 RH |
3 | Contributed by the OSF and Ralph Campbell. |
4 | Written by Keith Knowles and Ralph Campbell, working independently. | |
5 | Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus | |
6 | Support. | |
7 | ||
8 | This file is part of GAS. | |
9 | ||
10 | GAS is free software; you can redistribute it and/or modify | |
11 | it under the terms of the GNU General Public License as published by | |
ec2655a6 | 12 | the Free Software Foundation; either version 3, or (at your option) |
252b5132 RH |
13 | any later version. |
14 | ||
15 | GAS is distributed in the hope that it will be useful, | |
16 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | GNU General Public License for more details. | |
19 | ||
20 | You should have received a copy of the GNU General Public License | |
21 | along with GAS; see the file COPYING. If not, write to the Free | |
4b4da160 NC |
22 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
23 | 02110-1301, USA. */ | |
252b5132 RH |
24 | |
25 | #include "as.h" | |
26 | #include "config.h" | |
27 | #include "subsegs.h" | |
3882b010 | 28 | #include "safe-ctype.h" |
252b5132 | 29 | |
252b5132 RH |
30 | #include "opcode/mips.h" |
31 | #include "itbl-ops.h" | |
c5dd6aab | 32 | #include "dwarf2dbg.h" |
5862107c | 33 | #include "dw2gencfi.h" |
252b5132 | 34 | |
42429eac RS |
35 | /* Check assumptions made in this file. */ |
36 | typedef char static_assert1[sizeof (offsetT) < 8 ? -1 : 1]; | |
37 | typedef char static_assert2[sizeof (valueT) < 8 ? -1 : 1]; | |
38 | ||
252b5132 RH |
39 | #ifdef DEBUG |
40 | #define DBG(x) printf x | |
41 | #else | |
42 | #define DBG(x) | |
43 | #endif | |
44 | ||
263b2574 | 45 | #define streq(a, b) (strcmp (a, b) == 0) |
46 | ||
9e12b7a2 RS |
47 | #define SKIP_SPACE_TABS(S) \ |
48 | do { while (*(S) == ' ' || *(S) == '\t') ++(S); } while (0) | |
49 | ||
252b5132 | 50 | /* Clean up namespace so we can include obj-elf.h too. */ |
17a2f251 TS |
51 | static int mips_output_flavor (void); |
52 | static int mips_output_flavor (void) { return OUTPUT_FLAVOR; } | |
252b5132 RH |
53 | #undef OBJ_PROCESS_STAB |
54 | #undef OUTPUT_FLAVOR | |
55 | #undef S_GET_ALIGN | |
56 | #undef S_GET_SIZE | |
57 | #undef S_SET_ALIGN | |
58 | #undef S_SET_SIZE | |
252b5132 RH |
59 | #undef obj_frob_file |
60 | #undef obj_frob_file_after_relocs | |
61 | #undef obj_frob_symbol | |
62 | #undef obj_pop_insert | |
63 | #undef obj_sec_sym_ok_for_reloc | |
64 | #undef OBJ_COPY_SYMBOL_ATTRIBUTES | |
65 | ||
66 | #include "obj-elf.h" | |
67 | /* Fix any of them that we actually care about. */ | |
68 | #undef OUTPUT_FLAVOR | |
69 | #define OUTPUT_FLAVOR mips_output_flavor() | |
252b5132 | 70 | |
252b5132 | 71 | #include "elf/mips.h" |
252b5132 RH |
72 | |
73 | #ifndef ECOFF_DEBUGGING | |
74 | #define NO_ECOFF_DEBUGGING | |
75 | #define ECOFF_DEBUGGING 0 | |
76 | #endif | |
77 | ||
ecb4347a DJ |
78 | int mips_flag_mdebug = -1; |
79 | ||
dcd410fe RO |
80 | /* Control generation of .pdr sections. Off by default on IRIX: the native |
81 | linker doesn't know about and discards them, but relocations against them | |
82 | remain, leading to rld crashes. */ | |
83 | #ifdef TE_IRIX | |
84 | int mips_flag_pdr = FALSE; | |
85 | #else | |
86 | int mips_flag_pdr = TRUE; | |
87 | #endif | |
88 | ||
252b5132 RH |
89 | #include "ecoff.h" |
90 | ||
252b5132 | 91 | static char *mips_regmask_frag; |
351cdf24 | 92 | static char *mips_flags_frag; |
252b5132 | 93 | |
85b51719 | 94 | #define ZERO 0 |
741fe287 | 95 | #define ATREG 1 |
df58fc94 RS |
96 | #define S0 16 |
97 | #define S7 23 | |
252b5132 RH |
98 | #define TREG 24 |
99 | #define PIC_CALL_REG 25 | |
100 | #define KT0 26 | |
101 | #define KT1 27 | |
102 | #define GP 28 | |
103 | #define SP 29 | |
104 | #define FP 30 | |
105 | #define RA 31 | |
106 | ||
107 | #define ILLEGAL_REG (32) | |
108 | ||
741fe287 MR |
109 | #define AT mips_opts.at |
110 | ||
252b5132 RH |
111 | extern int target_big_endian; |
112 | ||
252b5132 | 113 | /* The name of the readonly data section. */ |
e8044f35 | 114 | #define RDATA_SECTION_NAME ".rodata" |
252b5132 | 115 | |
a4e06468 RS |
116 | /* Ways in which an instruction can be "appended" to the output. */ |
117 | enum append_method { | |
118 | /* Just add it normally. */ | |
119 | APPEND_ADD, | |
120 | ||
121 | /* Add it normally and then add a nop. */ | |
122 | APPEND_ADD_WITH_NOP, | |
123 | ||
124 | /* Turn an instruction with a delay slot into a "compact" version. */ | |
125 | APPEND_ADD_COMPACT, | |
126 | ||
127 | /* Insert the instruction before the last one. */ | |
128 | APPEND_SWAP | |
129 | }; | |
130 | ||
47e39b9d RS |
131 | /* Information about an instruction, including its format, operands |
132 | and fixups. */ | |
133 | struct mips_cl_insn | |
134 | { | |
135 | /* The opcode's entry in mips_opcodes or mips16_opcodes. */ | |
136 | const struct mips_opcode *insn_mo; | |
137 | ||
47e39b9d | 138 | /* The 16-bit or 32-bit bitstring of the instruction itself. This is |
5c04167a RS |
139 | a copy of INSN_MO->match with the operands filled in. If we have |
140 | decided to use an extended MIPS16 instruction, this includes the | |
141 | extension. */ | |
47e39b9d RS |
142 | unsigned long insn_opcode; |
143 | ||
144 | /* The frag that contains the instruction. */ | |
145 | struct frag *frag; | |
146 | ||
147 | /* The offset into FRAG of the first instruction byte. */ | |
148 | long where; | |
149 | ||
150 | /* The relocs associated with the instruction, if any. */ | |
151 | fixS *fixp[3]; | |
152 | ||
a38419a5 RS |
153 | /* True if this entry cannot be moved from its current position. */ |
154 | unsigned int fixed_p : 1; | |
47e39b9d | 155 | |
708587a4 | 156 | /* True if this instruction occurred in a .set noreorder block. */ |
47e39b9d RS |
157 | unsigned int noreorder_p : 1; |
158 | ||
2fa15973 RS |
159 | /* True for mips16 instructions that jump to an absolute address. */ |
160 | unsigned int mips16_absolute_jump_p : 1; | |
15be625d CM |
161 | |
162 | /* True if this instruction is complete. */ | |
163 | unsigned int complete_p : 1; | |
e407c74b NC |
164 | |
165 | /* True if this instruction is cleared from history by unconditional | |
166 | branch. */ | |
167 | unsigned int cleared_p : 1; | |
47e39b9d RS |
168 | }; |
169 | ||
a325df1d TS |
170 | /* The ABI to use. */ |
171 | enum mips_abi_level | |
172 | { | |
173 | NO_ABI = 0, | |
174 | O32_ABI, | |
175 | O64_ABI, | |
176 | N32_ABI, | |
177 | N64_ABI, | |
178 | EABI_ABI | |
179 | }; | |
180 | ||
181 | /* MIPS ABI we are using for this output file. */ | |
316f5878 | 182 | static enum mips_abi_level mips_abi = NO_ABI; |
a325df1d | 183 | |
143d77c5 EC |
184 | /* Whether or not we have code that can call pic code. */ |
185 | int mips_abicalls = FALSE; | |
186 | ||
aa6975fb ILT |
187 | /* Whether or not we have code which can be put into a shared |
188 | library. */ | |
189 | static bfd_boolean mips_in_shared = TRUE; | |
190 | ||
252b5132 RH |
191 | /* This is the set of options which may be modified by the .set |
192 | pseudo-op. We use a struct so that .set push and .set pop are more | |
193 | reliable. */ | |
194 | ||
e972090a NC |
195 | struct mips_set_options |
196 | { | |
252b5132 RH |
197 | /* MIPS ISA (Instruction Set Architecture) level. This is set to -1 |
198 | if it has not been initialized. Changed by `.set mipsN', and the | |
199 | -mipsN command line option, and the default CPU. */ | |
200 | int isa; | |
846ef2d0 RS |
201 | /* Enabled Application Specific Extensions (ASEs). Changed by `.set |
202 | <asename>', by command line options, and based on the default | |
203 | architecture. */ | |
204 | int ase; | |
252b5132 RH |
205 | /* Whether we are assembling for the mips16 processor. 0 if we are |
206 | not, 1 if we are, and -1 if the value has not been initialized. | |
207 | Changed by `.set mips16' and `.set nomips16', and the -mips16 and | |
208 | -nomips16 command line options, and the default CPU. */ | |
209 | int mips16; | |
df58fc94 RS |
210 | /* Whether we are assembling for the mipsMIPS ASE. 0 if we are not, |
211 | 1 if we are, and -1 if the value has not been initialized. Changed | |
212 | by `.set micromips' and `.set nomicromips', and the -mmicromips | |
213 | and -mno-micromips command line options, and the default CPU. */ | |
214 | int micromips; | |
252b5132 RH |
215 | /* Non-zero if we should not reorder instructions. Changed by `.set |
216 | reorder' and `.set noreorder'. */ | |
217 | int noreorder; | |
741fe287 MR |
218 | /* Non-zero if we should not permit the register designated "assembler |
219 | temporary" to be used in instructions. The value is the register | |
220 | number, normally $at ($1). Changed by `.set at=REG', `.set noat' | |
221 | (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */ | |
222 | unsigned int at; | |
252b5132 RH |
223 | /* Non-zero if we should warn when a macro instruction expands into |
224 | more than one machine instruction. Changed by `.set nomacro' and | |
225 | `.set macro'. */ | |
226 | int warn_about_macros; | |
227 | /* Non-zero if we should not move instructions. Changed by `.set | |
228 | move', `.set volatile', `.set nomove', and `.set novolatile'. */ | |
229 | int nomove; | |
230 | /* Non-zero if we should not optimize branches by moving the target | |
231 | of the branch into the delay slot. Actually, we don't perform | |
232 | this optimization anyhow. Changed by `.set bopt' and `.set | |
233 | nobopt'. */ | |
234 | int nobopt; | |
235 | /* Non-zero if we should not autoextend mips16 instructions. | |
236 | Changed by `.set autoextend' and `.set noautoextend'. */ | |
237 | int noautoextend; | |
833794fc MR |
238 | /* True if we should only emit 32-bit microMIPS instructions. |
239 | Changed by `.set insn32' and `.set noinsn32', and the -minsn32 | |
240 | and -mno-insn32 command line options. */ | |
241 | bfd_boolean insn32; | |
a325df1d TS |
242 | /* Restrict general purpose registers and floating point registers |
243 | to 32 bit. This is initially determined when -mgp32 or -mfp32 | |
244 | is passed but can changed if the assembler code uses .set mipsN. */ | |
bad1aba3 | 245 | int gp; |
0b35dfee | 246 | int fp; |
fef14a42 TS |
247 | /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march |
248 | command line option, and the default CPU. */ | |
249 | int arch; | |
aed1a261 RS |
250 | /* True if ".set sym32" is in effect. */ |
251 | bfd_boolean sym32; | |
037b32b9 AN |
252 | /* True if floating-point operations are not allowed. Changed by .set |
253 | softfloat or .set hardfloat, by command line options -msoft-float or | |
254 | -mhard-float. The default is false. */ | |
255 | bfd_boolean soft_float; | |
256 | ||
257 | /* True if only single-precision floating-point operations are allowed. | |
258 | Changed by .set singlefloat or .set doublefloat, command-line options | |
259 | -msingle-float or -mdouble-float. The default is false. */ | |
260 | bfd_boolean single_float; | |
351cdf24 MF |
261 | |
262 | /* 1 if single-precision operations on odd-numbered registers are | |
263 | allowed. */ | |
264 | int oddspreg; | |
252b5132 RH |
265 | }; |
266 | ||
919731af | 267 | /* Specifies whether module level options have been checked yet. */ |
268 | static bfd_boolean file_mips_opts_checked = FALSE; | |
269 | ||
7361da2c AB |
270 | /* Do we support nan2008? 0 if we don't, 1 if we do, and -1 if the |
271 | value has not been initialized. Changed by `.nan legacy' and | |
272 | `.nan 2008', and the -mnan=legacy and -mnan=2008 command line | |
273 | options, and the default CPU. */ | |
274 | static int mips_nan2008 = -1; | |
a325df1d | 275 | |
0b35dfee | 276 | /* This is the struct we use to hold the module level set of options. |
bad1aba3 | 277 | Note that we must set the isa field to ISA_UNKNOWN and the ASE, gp and |
0b35dfee | 278 | fp fields to -1 to indicate that they have not been initialized. */ |
037b32b9 | 279 | |
0b35dfee | 280 | static struct mips_set_options file_mips_opts = |
281 | { | |
282 | /* isa */ ISA_UNKNOWN, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1, | |
283 | /* noreorder */ 0, /* at */ ATREG, /* warn_about_macros */ 0, | |
284 | /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE, | |
bad1aba3 | 285 | /* gp */ -1, /* fp */ -1, /* arch */ CPU_UNKNOWN, /* sym32 */ FALSE, |
351cdf24 | 286 | /* soft_float */ FALSE, /* single_float */ FALSE, /* oddspreg */ -1 |
0b35dfee | 287 | }; |
252b5132 | 288 | |
0b35dfee | 289 | /* This is similar to file_mips_opts, but for the current set of options. */ |
ba92f887 | 290 | |
e972090a NC |
291 | static struct mips_set_options mips_opts = |
292 | { | |
846ef2d0 | 293 | /* isa */ ISA_UNKNOWN, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1, |
b015e599 | 294 | /* noreorder */ 0, /* at */ ATREG, /* warn_about_macros */ 0, |
833794fc | 295 | /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE, |
bad1aba3 | 296 | /* gp */ -1, /* fp */ -1, /* arch */ CPU_UNKNOWN, /* sym32 */ FALSE, |
351cdf24 | 297 | /* soft_float */ FALSE, /* single_float */ FALSE, /* oddspreg */ -1 |
e7af610e | 298 | }; |
252b5132 | 299 | |
846ef2d0 RS |
300 | /* Which bits of file_ase were explicitly set or cleared by ASE options. */ |
301 | static unsigned int file_ase_explicit; | |
302 | ||
252b5132 RH |
303 | /* These variables are filled in with the masks of registers used. |
304 | The object format code reads them and puts them in the appropriate | |
305 | place. */ | |
306 | unsigned long mips_gprmask; | |
307 | unsigned long mips_cprmask[4]; | |
308 | ||
738f4d98 | 309 | /* True if any MIPS16 code was produced. */ |
a4672219 TS |
310 | static int file_ase_mips16; |
311 | ||
3994f87e TS |
312 | #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \ |
313 | || mips_opts.isa == ISA_MIPS32R2 \ | |
ae52f483 AB |
314 | || mips_opts.isa == ISA_MIPS32R3 \ |
315 | || mips_opts.isa == ISA_MIPS32R5 \ | |
3994f87e | 316 | || mips_opts.isa == ISA_MIPS64 \ |
ae52f483 AB |
317 | || mips_opts.isa == ISA_MIPS64R2 \ |
318 | || mips_opts.isa == ISA_MIPS64R3 \ | |
319 | || mips_opts.isa == ISA_MIPS64R5) | |
3994f87e | 320 | |
df58fc94 RS |
321 | /* True if any microMIPS code was produced. */ |
322 | static int file_ase_micromips; | |
323 | ||
b12dd2e4 CF |
324 | /* True if we want to create R_MIPS_JALR for jalr $25. */ |
325 | #ifdef TE_IRIX | |
1180b5a4 | 326 | #define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI |
b12dd2e4 | 327 | #else |
1180b5a4 RS |
328 | /* As a GNU extension, we use R_MIPS_JALR for o32 too. However, |
329 | because there's no place for any addend, the only acceptable | |
330 | expression is a bare symbol. */ | |
331 | #define MIPS_JALR_HINT_P(EXPR) \ | |
332 | (!HAVE_IN_PLACE_ADDENDS \ | |
333 | || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0)) | |
b12dd2e4 CF |
334 | #endif |
335 | ||
ec68c924 | 336 | /* The argument of the -march= flag. The architecture we are assembling. */ |
316f5878 | 337 | static const char *mips_arch_string; |
ec68c924 EC |
338 | |
339 | /* The argument of the -mtune= flag. The architecture for which we | |
340 | are optimizing. */ | |
341 | static int mips_tune = CPU_UNKNOWN; | |
316f5878 | 342 | static const char *mips_tune_string; |
ec68c924 | 343 | |
316f5878 | 344 | /* True when generating 32-bit code for a 64-bit processor. */ |
252b5132 RH |
345 | static int mips_32bitmode = 0; |
346 | ||
316f5878 RS |
347 | /* True if the given ABI requires 32-bit registers. */ |
348 | #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI) | |
349 | ||
350 | /* Likewise 64-bit registers. */ | |
707bfff6 | 351 | #define ABI_NEEDS_64BIT_REGS(ABI) \ |
134c0c8b | 352 | ((ABI) == N32_ABI \ |
707bfff6 | 353 | || (ABI) == N64_ABI \ |
316f5878 RS |
354 | || (ABI) == O64_ABI) |
355 | ||
7361da2c AB |
356 | #define ISA_IS_R6(ISA) \ |
357 | ((ISA) == ISA_MIPS32R6 \ | |
358 | || (ISA) == ISA_MIPS64R6) | |
359 | ||
ad3fea08 | 360 | /* Return true if ISA supports 64 bit wide gp registers. */ |
707bfff6 TS |
361 | #define ISA_HAS_64BIT_REGS(ISA) \ |
362 | ((ISA) == ISA_MIPS3 \ | |
363 | || (ISA) == ISA_MIPS4 \ | |
364 | || (ISA) == ISA_MIPS5 \ | |
365 | || (ISA) == ISA_MIPS64 \ | |
ae52f483 AB |
366 | || (ISA) == ISA_MIPS64R2 \ |
367 | || (ISA) == ISA_MIPS64R3 \ | |
7361da2c AB |
368 | || (ISA) == ISA_MIPS64R5 \ |
369 | || (ISA) == ISA_MIPS64R6) | |
9ce8a5dd | 370 | |
ad3fea08 TS |
371 | /* Return true if ISA supports 64 bit wide float registers. */ |
372 | #define ISA_HAS_64BIT_FPRS(ISA) \ | |
373 | ((ISA) == ISA_MIPS3 \ | |
374 | || (ISA) == ISA_MIPS4 \ | |
375 | || (ISA) == ISA_MIPS5 \ | |
376 | || (ISA) == ISA_MIPS32R2 \ | |
ae52f483 AB |
377 | || (ISA) == ISA_MIPS32R3 \ |
378 | || (ISA) == ISA_MIPS32R5 \ | |
7361da2c | 379 | || (ISA) == ISA_MIPS32R6 \ |
ad3fea08 | 380 | || (ISA) == ISA_MIPS64 \ |
ae52f483 AB |
381 | || (ISA) == ISA_MIPS64R2 \ |
382 | || (ISA) == ISA_MIPS64R3 \ | |
7361da2c AB |
383 | || (ISA) == ISA_MIPS64R5 \ |
384 | || (ISA) == ISA_MIPS64R6) | |
ad3fea08 | 385 | |
af7ee8bf CD |
386 | /* Return true if ISA supports 64-bit right rotate (dror et al.) |
387 | instructions. */ | |
707bfff6 | 388 | #define ISA_HAS_DROR(ISA) \ |
df58fc94 | 389 | ((ISA) == ISA_MIPS64R2 \ |
ae52f483 AB |
390 | || (ISA) == ISA_MIPS64R3 \ |
391 | || (ISA) == ISA_MIPS64R5 \ | |
7361da2c | 392 | || (ISA) == ISA_MIPS64R6 \ |
df58fc94 RS |
393 | || (mips_opts.micromips \ |
394 | && ISA_HAS_64BIT_REGS (ISA)) \ | |
395 | ) | |
af7ee8bf CD |
396 | |
397 | /* Return true if ISA supports 32-bit right rotate (ror et al.) | |
398 | instructions. */ | |
707bfff6 TS |
399 | #define ISA_HAS_ROR(ISA) \ |
400 | ((ISA) == ISA_MIPS32R2 \ | |
ae52f483 AB |
401 | || (ISA) == ISA_MIPS32R3 \ |
402 | || (ISA) == ISA_MIPS32R5 \ | |
7361da2c | 403 | || (ISA) == ISA_MIPS32R6 \ |
707bfff6 | 404 | || (ISA) == ISA_MIPS64R2 \ |
ae52f483 AB |
405 | || (ISA) == ISA_MIPS64R3 \ |
406 | || (ISA) == ISA_MIPS64R5 \ | |
7361da2c | 407 | || (ISA) == ISA_MIPS64R6 \ |
846ef2d0 | 408 | || (mips_opts.ase & ASE_SMARTMIPS) \ |
df58fc94 RS |
409 | || mips_opts.micromips \ |
410 | ) | |
707bfff6 | 411 | |
7455baf8 | 412 | /* Return true if ISA supports single-precision floats in odd registers. */ |
351cdf24 MF |
413 | #define ISA_HAS_ODD_SINGLE_FPR(ISA, CPU)\ |
414 | (((ISA) == ISA_MIPS32 \ | |
415 | || (ISA) == ISA_MIPS32R2 \ | |
416 | || (ISA) == ISA_MIPS32R3 \ | |
417 | || (ISA) == ISA_MIPS32R5 \ | |
7361da2c | 418 | || (ISA) == ISA_MIPS32R6 \ |
351cdf24 MF |
419 | || (ISA) == ISA_MIPS64 \ |
420 | || (ISA) == ISA_MIPS64R2 \ | |
421 | || (ISA) == ISA_MIPS64R3 \ | |
422 | || (ISA) == ISA_MIPS64R5 \ | |
7361da2c | 423 | || (ISA) == ISA_MIPS64R6 \ |
351cdf24 MF |
424 | || (CPU) == CPU_R5900) \ |
425 | && (CPU) != CPU_LOONGSON_3A) | |
af7ee8bf | 426 | |
ad3fea08 TS |
427 | /* Return true if ISA supports move to/from high part of a 64-bit |
428 | floating-point register. */ | |
429 | #define ISA_HAS_MXHC1(ISA) \ | |
430 | ((ISA) == ISA_MIPS32R2 \ | |
ae52f483 AB |
431 | || (ISA) == ISA_MIPS32R3 \ |
432 | || (ISA) == ISA_MIPS32R5 \ | |
7361da2c AB |
433 | || (ISA) == ISA_MIPS32R6 \ |
434 | || (ISA) == ISA_MIPS64R2 \ | |
435 | || (ISA) == ISA_MIPS64R3 \ | |
436 | || (ISA) == ISA_MIPS64R5 \ | |
437 | || (ISA) == ISA_MIPS64R6) | |
438 | ||
439 | /* Return true if ISA supports legacy NAN. */ | |
440 | #define ISA_HAS_LEGACY_NAN(ISA) \ | |
441 | ((ISA) == ISA_MIPS1 \ | |
442 | || (ISA) == ISA_MIPS2 \ | |
443 | || (ISA) == ISA_MIPS3 \ | |
444 | || (ISA) == ISA_MIPS4 \ | |
445 | || (ISA) == ISA_MIPS5 \ | |
446 | || (ISA) == ISA_MIPS32 \ | |
447 | || (ISA) == ISA_MIPS32R2 \ | |
448 | || (ISA) == ISA_MIPS32R3 \ | |
449 | || (ISA) == ISA_MIPS32R5 \ | |
450 | || (ISA) == ISA_MIPS64 \ | |
ae52f483 AB |
451 | || (ISA) == ISA_MIPS64R2 \ |
452 | || (ISA) == ISA_MIPS64R3 \ | |
453 | || (ISA) == ISA_MIPS64R5) | |
ad3fea08 | 454 | |
bad1aba3 | 455 | #define GPR_SIZE \ |
456 | (mips_opts.gp == 64 && !ISA_HAS_64BIT_REGS (mips_opts.isa) \ | |
457 | ? 32 \ | |
458 | : mips_opts.gp) | |
ca4e0257 | 459 | |
bad1aba3 | 460 | #define FPR_SIZE \ |
461 | (mips_opts.fp == 64 && !ISA_HAS_64BIT_FPRS (mips_opts.isa) \ | |
462 | ? 32 \ | |
463 | : mips_opts.fp) | |
ca4e0257 | 464 | |
316f5878 | 465 | #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI) |
e013f690 | 466 | |
316f5878 | 467 | #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI) |
e013f690 | 468 | |
3b91255e RS |
469 | /* True if relocations are stored in-place. */ |
470 | #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI) | |
471 | ||
aed1a261 RS |
472 | /* The ABI-derived address size. */ |
473 | #define HAVE_64BIT_ADDRESSES \ | |
bad1aba3 | 474 | (GPR_SIZE == 64 && (mips_abi == EABI_ABI || mips_abi == N64_ABI)) |
aed1a261 | 475 | #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES) |
e013f690 | 476 | |
aed1a261 RS |
477 | /* The size of symbolic constants (i.e., expressions of the form |
478 | "SYMBOL" or "SYMBOL + OFFSET"). */ | |
479 | #define HAVE_32BIT_SYMBOLS \ | |
480 | (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32) | |
481 | #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS) | |
ca4e0257 | 482 | |
b7c7d6c1 TS |
483 | /* Addresses are loaded in different ways, depending on the address size |
484 | in use. The n32 ABI Documentation also mandates the use of additions | |
485 | with overflow checking, but existing implementations don't follow it. */ | |
f899b4b8 | 486 | #define ADDRESS_ADD_INSN \ |
b7c7d6c1 | 487 | (HAVE_32BIT_ADDRESSES ? "addu" : "daddu") |
f899b4b8 TS |
488 | |
489 | #define ADDRESS_ADDI_INSN \ | |
b7c7d6c1 | 490 | (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu") |
f899b4b8 TS |
491 | |
492 | #define ADDRESS_LOAD_INSN \ | |
493 | (HAVE_32BIT_ADDRESSES ? "lw" : "ld") | |
494 | ||
495 | #define ADDRESS_STORE_INSN \ | |
496 | (HAVE_32BIT_ADDRESSES ? "sw" : "sd") | |
497 | ||
a4672219 | 498 | /* Return true if the given CPU supports the MIPS16 ASE. */ |
3396de36 TS |
499 | #define CPU_HAS_MIPS16(cpu) \ |
500 | (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \ | |
501 | || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0) | |
a4672219 | 502 | |
2309ddf2 | 503 | /* Return true if the given CPU supports the microMIPS ASE. */ |
df58fc94 RS |
504 | #define CPU_HAS_MICROMIPS(cpu) 0 |
505 | ||
60b63b72 RS |
506 | /* True if CPU has a dror instruction. */ |
507 | #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500) | |
508 | ||
509 | /* True if CPU has a ror instruction. */ | |
510 | #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU) | |
511 | ||
dd6a37e7 | 512 | /* True if CPU is in the Octeon family */ |
2c629856 N |
513 | #define CPU_IS_OCTEON(CPU) ((CPU) == CPU_OCTEON || (CPU) == CPU_OCTEONP \ |
514 | || (CPU) == CPU_OCTEON2 || (CPU) == CPU_OCTEON3) | |
dd6a37e7 | 515 | |
dd3cbb7e | 516 | /* True if CPU has seq/sne and seqi/snei instructions. */ |
dd6a37e7 | 517 | #define CPU_HAS_SEQ(CPU) (CPU_IS_OCTEON (CPU)) |
dd3cbb7e | 518 | |
0aa27725 RS |
519 | /* True, if CPU has support for ldc1 and sdc1. */ |
520 | #define CPU_HAS_LDC1_SDC1(CPU) \ | |
521 | ((mips_opts.isa != ISA_MIPS1) && ((CPU) != CPU_R5900)) | |
522 | ||
c8978940 CD |
523 | /* True if mflo and mfhi can be immediately followed by instructions |
524 | which write to the HI and LO registers. | |
525 | ||
526 | According to MIPS specifications, MIPS ISAs I, II, and III need | |
527 | (at least) two instructions between the reads of HI/LO and | |
528 | instructions which write them, and later ISAs do not. Contradicting | |
529 | the MIPS specifications, some MIPS IV processor user manuals (e.g. | |
530 | the UM for the NEC Vr5000) document needing the instructions between | |
531 | HI/LO reads and writes, as well. Therefore, we declare only MIPS32, | |
532 | MIPS64 and later ISAs to have the interlocks, plus any specific | |
533 | earlier-ISA CPUs for which CPU documentation declares that the | |
534 | instructions are really interlocked. */ | |
535 | #define hilo_interlocks \ | |
536 | (mips_opts.isa == ISA_MIPS32 \ | |
537 | || mips_opts.isa == ISA_MIPS32R2 \ | |
ae52f483 AB |
538 | || mips_opts.isa == ISA_MIPS32R3 \ |
539 | || mips_opts.isa == ISA_MIPS32R5 \ | |
7361da2c | 540 | || mips_opts.isa == ISA_MIPS32R6 \ |
c8978940 CD |
541 | || mips_opts.isa == ISA_MIPS64 \ |
542 | || mips_opts.isa == ISA_MIPS64R2 \ | |
ae52f483 AB |
543 | || mips_opts.isa == ISA_MIPS64R3 \ |
544 | || mips_opts.isa == ISA_MIPS64R5 \ | |
7361da2c | 545 | || mips_opts.isa == ISA_MIPS64R6 \ |
c8978940 | 546 | || mips_opts.arch == CPU_R4010 \ |
e407c74b | 547 | || mips_opts.arch == CPU_R5900 \ |
c8978940 CD |
548 | || mips_opts.arch == CPU_R10000 \ |
549 | || mips_opts.arch == CPU_R12000 \ | |
3aa3176b TS |
550 | || mips_opts.arch == CPU_R14000 \ |
551 | || mips_opts.arch == CPU_R16000 \ | |
c8978940 | 552 | || mips_opts.arch == CPU_RM7000 \ |
c8978940 | 553 | || mips_opts.arch == CPU_VR5500 \ |
df58fc94 | 554 | || mips_opts.micromips \ |
c8978940 | 555 | ) |
252b5132 RH |
556 | |
557 | /* Whether the processor uses hardware interlocks to protect reads | |
81912461 ILT |
558 | from the GPRs after they are loaded from memory, and thus does not |
559 | require nops to be inserted. This applies to instructions marked | |
67dc82bc | 560 | INSN_LOAD_MEMORY. These nops are only required at MIPS ISA |
df58fc94 RS |
561 | level I and microMIPS mode instructions are always interlocked. */ |
562 | #define gpr_interlocks \ | |
563 | (mips_opts.isa != ISA_MIPS1 \ | |
564 | || mips_opts.arch == CPU_R3900 \ | |
e407c74b | 565 | || mips_opts.arch == CPU_R5900 \ |
df58fc94 RS |
566 | || mips_opts.micromips \ |
567 | ) | |
252b5132 | 568 | |
81912461 ILT |
569 | /* Whether the processor uses hardware interlocks to avoid delays |
570 | required by coprocessor instructions, and thus does not require | |
571 | nops to be inserted. This applies to instructions marked | |
43885403 MF |
572 | INSN_LOAD_COPROC, INSN_COPROC_MOVE, and to delays between |
573 | instructions marked INSN_WRITE_COND_CODE and ones marked | |
81912461 | 574 | INSN_READ_COND_CODE. These nops are only required at MIPS ISA |
df58fc94 RS |
575 | levels I, II, and III and microMIPS mode instructions are always |
576 | interlocked. */ | |
bdaaa2e1 | 577 | /* Itbl support may require additional care here. */ |
81912461 ILT |
578 | #define cop_interlocks \ |
579 | ((mips_opts.isa != ISA_MIPS1 \ | |
580 | && mips_opts.isa != ISA_MIPS2 \ | |
581 | && mips_opts.isa != ISA_MIPS3) \ | |
582 | || mips_opts.arch == CPU_R4300 \ | |
df58fc94 | 583 | || mips_opts.micromips \ |
81912461 ILT |
584 | ) |
585 | ||
586 | /* Whether the processor uses hardware interlocks to protect reads | |
587 | from coprocessor registers after they are loaded from memory, and | |
588 | thus does not require nops to be inserted. This applies to | |
589 | instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only | |
df58fc94 RS |
590 | requires at MIPS ISA level I and microMIPS mode instructions are |
591 | always interlocked. */ | |
592 | #define cop_mem_interlocks \ | |
593 | (mips_opts.isa != ISA_MIPS1 \ | |
594 | || mips_opts.micromips \ | |
595 | ) | |
252b5132 | 596 | |
6b76fefe CM |
597 | /* Is this a mfhi or mflo instruction? */ |
598 | #define MF_HILO_INSN(PINFO) \ | |
b19e8a9b AN |
599 | ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO)) |
600 | ||
df58fc94 RS |
601 | /* Whether code compression (either of the MIPS16 or the microMIPS ASEs) |
602 | has been selected. This implies, in particular, that addresses of text | |
603 | labels have their LSB set. */ | |
604 | #define HAVE_CODE_COMPRESSION \ | |
605 | ((mips_opts.mips16 | mips_opts.micromips) != 0) | |
606 | ||
42429eac | 607 | /* The minimum and maximum signed values that can be stored in a GPR. */ |
bad1aba3 | 608 | #define GPR_SMAX ((offsetT) (((valueT) 1 << (GPR_SIZE - 1)) - 1)) |
42429eac RS |
609 | #define GPR_SMIN (-GPR_SMAX - 1) |
610 | ||
252b5132 RH |
611 | /* MIPS PIC level. */ |
612 | ||
a161fe53 | 613 | enum mips_pic_level mips_pic; |
252b5132 | 614 | |
c9914766 | 615 | /* 1 if we should generate 32 bit offsets from the $gp register in |
252b5132 | 616 | SVR4_PIC mode. Currently has no meaning in other modes. */ |
c9914766 | 617 | static int mips_big_got = 0; |
252b5132 RH |
618 | |
619 | /* 1 if trap instructions should used for overflow rather than break | |
620 | instructions. */ | |
c9914766 | 621 | static int mips_trap = 0; |
252b5132 | 622 | |
119d663a | 623 | /* 1 if double width floating point constants should not be constructed |
b6ff326e | 624 | by assembling two single width halves into two single width floating |
119d663a NC |
625 | point registers which just happen to alias the double width destination |
626 | register. On some architectures this aliasing can be disabled by a bit | |
d547a75e | 627 | in the status register, and the setting of this bit cannot be determined |
119d663a NC |
628 | automatically at assemble time. */ |
629 | static int mips_disable_float_construction; | |
630 | ||
252b5132 RH |
631 | /* Non-zero if any .set noreorder directives were used. */ |
632 | ||
633 | static int mips_any_noreorder; | |
634 | ||
6b76fefe CM |
635 | /* Non-zero if nops should be inserted when the register referenced in |
636 | an mfhi/mflo instruction is read in the next two instructions. */ | |
637 | static int mips_7000_hilo_fix; | |
638 | ||
02ffd3e4 | 639 | /* The size of objects in the small data section. */ |
156c2f8b | 640 | static unsigned int g_switch_value = 8; |
252b5132 RH |
641 | /* Whether the -G option was used. */ |
642 | static int g_switch_seen = 0; | |
643 | ||
644 | #define N_RMASK 0xc4 | |
645 | #define N_VFP 0xd4 | |
646 | ||
647 | /* If we can determine in advance that GP optimization won't be | |
648 | possible, we can skip the relaxation stuff that tries to produce | |
649 | GP-relative references. This makes delay slot optimization work | |
650 | better. | |
651 | ||
652 | This function can only provide a guess, but it seems to work for | |
fba2b7f9 GK |
653 | gcc output. It needs to guess right for gcc, otherwise gcc |
654 | will put what it thinks is a GP-relative instruction in a branch | |
655 | delay slot. | |
252b5132 RH |
656 | |
657 | I don't know if a fix is needed for the SVR4_PIC mode. I've only | |
658 | fixed it for the non-PIC mode. KR 95/04/07 */ | |
17a2f251 | 659 | static int nopic_need_relax (symbolS *, int); |
252b5132 RH |
660 | |
661 | /* handle of the OPCODE hash table */ | |
662 | static struct hash_control *op_hash = NULL; | |
663 | ||
664 | /* The opcode hash table we use for the mips16. */ | |
665 | static struct hash_control *mips16_op_hash = NULL; | |
666 | ||
df58fc94 RS |
667 | /* The opcode hash table we use for the microMIPS ASE. */ |
668 | static struct hash_control *micromips_op_hash = NULL; | |
669 | ||
252b5132 RH |
670 | /* This array holds the chars that always start a comment. If the |
671 | pre-processor is disabled, these aren't very useful */ | |
672 | const char comment_chars[] = "#"; | |
673 | ||
674 | /* This array holds the chars that only start a comment at the beginning of | |
675 | a line. If the line seems to have the form '# 123 filename' | |
676 | .line and .file directives will appear in the pre-processed output */ | |
677 | /* Note that input_file.c hand checks for '#' at the beginning of the | |
678 | first line of the input file. This is because the compiler outputs | |
bdaaa2e1 | 679 | #NO_APP at the beginning of its output. */ |
252b5132 RH |
680 | /* Also note that C style comments are always supported. */ |
681 | const char line_comment_chars[] = "#"; | |
682 | ||
bdaaa2e1 | 683 | /* This array holds machine specific line separator characters. */ |
63a0b638 | 684 | const char line_separator_chars[] = ";"; |
252b5132 RH |
685 | |
686 | /* Chars that can be used to separate mant from exp in floating point nums */ | |
687 | const char EXP_CHARS[] = "eE"; | |
688 | ||
689 | /* Chars that mean this number is a floating point constant */ | |
690 | /* As in 0f12.456 */ | |
691 | /* or 0d1.2345e12 */ | |
692 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; | |
693 | ||
694 | /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be | |
695 | changed in read.c . Ideally it shouldn't have to know about it at all, | |
696 | but nothing is ideal around here. | |
697 | */ | |
698 | ||
e3de51ce RS |
699 | /* Types of printf format used for instruction-related error messages. |
700 | "I" means int ("%d") and "S" means string ("%s"). */ | |
701 | enum mips_insn_error_format { | |
702 | ERR_FMT_PLAIN, | |
703 | ERR_FMT_I, | |
704 | ERR_FMT_SS, | |
705 | }; | |
706 | ||
707 | /* Information about an error that was found while assembling the current | |
708 | instruction. */ | |
709 | struct mips_insn_error { | |
710 | /* We sometimes need to match an instruction against more than one | |
711 | opcode table entry. Errors found during this matching are reported | |
712 | against a particular syntactic argument rather than against the | |
713 | instruction as a whole. We grade these messages so that errors | |
714 | against argument N have a greater priority than an error against | |
715 | any argument < N, since the former implies that arguments up to N | |
716 | were acceptable and that the opcode entry was therefore a closer match. | |
717 | If several matches report an error against the same argument, | |
718 | we only use that error if it is the same in all cases. | |
719 | ||
720 | min_argnum is the minimum argument number for which an error message | |
721 | should be accepted. It is 0 if MSG is against the instruction as | |
722 | a whole. */ | |
723 | int min_argnum; | |
724 | ||
725 | /* The printf()-style message, including its format and arguments. */ | |
726 | enum mips_insn_error_format format; | |
727 | const char *msg; | |
728 | union { | |
729 | int i; | |
730 | const char *ss[2]; | |
731 | } u; | |
732 | }; | |
733 | ||
734 | /* The error that should be reported for the current instruction. */ | |
735 | static struct mips_insn_error insn_error; | |
252b5132 RH |
736 | |
737 | static int auto_align = 1; | |
738 | ||
739 | /* When outputting SVR4 PIC code, the assembler needs to know the | |
740 | offset in the stack frame from which to restore the $gp register. | |
741 | This is set by the .cprestore pseudo-op, and saved in this | |
742 | variable. */ | |
743 | static offsetT mips_cprestore_offset = -1; | |
744 | ||
67c1ffbe | 745 | /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some |
6478892d | 746 | more optimizations, it can use a register value instead of a memory-saved |
956cd1d6 | 747 | offset and even an other register than $gp as global pointer. */ |
6478892d TS |
748 | static offsetT mips_cpreturn_offset = -1; |
749 | static int mips_cpreturn_register = -1; | |
750 | static int mips_gp_register = GP; | |
def2e0dd | 751 | static int mips_gprel_offset = 0; |
6478892d | 752 | |
7a621144 DJ |
753 | /* Whether mips_cprestore_offset has been set in the current function |
754 | (or whether it has already been warned about, if not). */ | |
755 | static int mips_cprestore_valid = 0; | |
756 | ||
252b5132 RH |
757 | /* This is the register which holds the stack frame, as set by the |
758 | .frame pseudo-op. This is needed to implement .cprestore. */ | |
759 | static int mips_frame_reg = SP; | |
760 | ||
7a621144 DJ |
761 | /* Whether mips_frame_reg has been set in the current function |
762 | (or whether it has already been warned about, if not). */ | |
763 | static int mips_frame_reg_valid = 0; | |
764 | ||
252b5132 RH |
765 | /* To output NOP instructions correctly, we need to keep information |
766 | about the previous two instructions. */ | |
767 | ||
768 | /* Whether we are optimizing. The default value of 2 means to remove | |
769 | unneeded NOPs and swap branch instructions when possible. A value | |
770 | of 1 means to not swap branches. A value of 0 means to always | |
771 | insert NOPs. */ | |
772 | static int mips_optimize = 2; | |
773 | ||
774 | /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is | |
775 | equivalent to seeing no -g option at all. */ | |
776 | static int mips_debug = 0; | |
777 | ||
7d8e00cf RS |
778 | /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */ |
779 | #define MAX_VR4130_NOPS 4 | |
780 | ||
781 | /* The maximum number of NOPs needed to fill delay slots. */ | |
782 | #define MAX_DELAY_NOPS 2 | |
783 | ||
784 | /* The maximum number of NOPs needed for any purpose. */ | |
785 | #define MAX_NOPS 4 | |
71400594 RS |
786 | |
787 | /* A list of previous instructions, with index 0 being the most recent. | |
788 | We need to look back MAX_NOPS instructions when filling delay slots | |
789 | or working around processor errata. We need to look back one | |
790 | instruction further if we're thinking about using history[0] to | |
791 | fill a branch delay slot. */ | |
792 | static struct mips_cl_insn history[1 + MAX_NOPS]; | |
252b5132 | 793 | |
fc76e730 | 794 | /* Arrays of operands for each instruction. */ |
14daeee3 | 795 | #define MAX_OPERANDS 6 |
fc76e730 RS |
796 | struct mips_operand_array { |
797 | const struct mips_operand *operand[MAX_OPERANDS]; | |
798 | }; | |
799 | static struct mips_operand_array *mips_operands; | |
800 | static struct mips_operand_array *mips16_operands; | |
801 | static struct mips_operand_array *micromips_operands; | |
802 | ||
1e915849 | 803 | /* Nop instructions used by emit_nop. */ |
df58fc94 RS |
804 | static struct mips_cl_insn nop_insn; |
805 | static struct mips_cl_insn mips16_nop_insn; | |
806 | static struct mips_cl_insn micromips_nop16_insn; | |
807 | static struct mips_cl_insn micromips_nop32_insn; | |
1e915849 RS |
808 | |
809 | /* The appropriate nop for the current mode. */ | |
833794fc MR |
810 | #define NOP_INSN (mips_opts.mips16 \ |
811 | ? &mips16_nop_insn \ | |
812 | : (mips_opts.micromips \ | |
813 | ? (mips_opts.insn32 \ | |
814 | ? µmips_nop32_insn \ | |
815 | : µmips_nop16_insn) \ | |
816 | : &nop_insn)) | |
df58fc94 RS |
817 | |
818 | /* The size of NOP_INSN in bytes. */ | |
833794fc MR |
819 | #define NOP_INSN_SIZE ((mips_opts.mips16 \ |
820 | || (mips_opts.micromips && !mips_opts.insn32)) \ | |
821 | ? 2 : 4) | |
252b5132 | 822 | |
252b5132 RH |
823 | /* If this is set, it points to a frag holding nop instructions which |
824 | were inserted before the start of a noreorder section. If those | |
825 | nops turn out to be unnecessary, the size of the frag can be | |
826 | decreased. */ | |
827 | static fragS *prev_nop_frag; | |
828 | ||
829 | /* The number of nop instructions we created in prev_nop_frag. */ | |
830 | static int prev_nop_frag_holds; | |
831 | ||
832 | /* The number of nop instructions that we know we need in | |
bdaaa2e1 | 833 | prev_nop_frag. */ |
252b5132 RH |
834 | static int prev_nop_frag_required; |
835 | ||
836 | /* The number of instructions we've seen since prev_nop_frag. */ | |
837 | static int prev_nop_frag_since; | |
838 | ||
e8044f35 RS |
839 | /* Relocations against symbols are sometimes done in two parts, with a HI |
840 | relocation and a LO relocation. Each relocation has only 16 bits of | |
841 | space to store an addend. This means that in order for the linker to | |
842 | handle carries correctly, it must be able to locate both the HI and | |
843 | the LO relocation. This means that the relocations must appear in | |
844 | order in the relocation table. | |
252b5132 RH |
845 | |
846 | In order to implement this, we keep track of each unmatched HI | |
847 | relocation. We then sort them so that they immediately precede the | |
bdaaa2e1 | 848 | corresponding LO relocation. */ |
252b5132 | 849 | |
e972090a NC |
850 | struct mips_hi_fixup |
851 | { | |
252b5132 RH |
852 | /* Next HI fixup. */ |
853 | struct mips_hi_fixup *next; | |
854 | /* This fixup. */ | |
855 | fixS *fixp; | |
856 | /* The section this fixup is in. */ | |
857 | segT seg; | |
858 | }; | |
859 | ||
860 | /* The list of unmatched HI relocs. */ | |
861 | ||
862 | static struct mips_hi_fixup *mips_hi_fixup_list; | |
863 | ||
64bdfcaf RS |
864 | /* The frag containing the last explicit relocation operator. |
865 | Null if explicit relocations have not been used. */ | |
866 | ||
867 | static fragS *prev_reloc_op_frag; | |
868 | ||
252b5132 RH |
869 | /* Map mips16 register numbers to normal MIPS register numbers. */ |
870 | ||
e972090a NC |
871 | static const unsigned int mips16_to_32_reg_map[] = |
872 | { | |
252b5132 RH |
873 | 16, 17, 2, 3, 4, 5, 6, 7 |
874 | }; | |
60b63b72 | 875 | |
df58fc94 RS |
876 | /* Map microMIPS register numbers to normal MIPS register numbers. */ |
877 | ||
df58fc94 | 878 | #define micromips_to_32_reg_d_map mips16_to_32_reg_map |
df58fc94 RS |
879 | |
880 | /* The microMIPS registers with type h. */ | |
e76ff5ab | 881 | static const unsigned int micromips_to_32_reg_h_map1[] = |
df58fc94 RS |
882 | { |
883 | 5, 5, 6, 4, 4, 4, 4, 4 | |
884 | }; | |
e76ff5ab | 885 | static const unsigned int micromips_to_32_reg_h_map2[] = |
df58fc94 RS |
886 | { |
887 | 6, 7, 7, 21, 22, 5, 6, 7 | |
888 | }; | |
889 | ||
df58fc94 RS |
890 | /* The microMIPS registers with type m. */ |
891 | static const unsigned int micromips_to_32_reg_m_map[] = | |
892 | { | |
893 | 0, 17, 2, 3, 16, 18, 19, 20 | |
894 | }; | |
895 | ||
896 | #define micromips_to_32_reg_n_map micromips_to_32_reg_m_map | |
897 | ||
71400594 RS |
898 | /* Classifies the kind of instructions we're interested in when |
899 | implementing -mfix-vr4120. */ | |
c67a084a NC |
900 | enum fix_vr4120_class |
901 | { | |
71400594 RS |
902 | FIX_VR4120_MACC, |
903 | FIX_VR4120_DMACC, | |
904 | FIX_VR4120_MULT, | |
905 | FIX_VR4120_DMULT, | |
906 | FIX_VR4120_DIV, | |
907 | FIX_VR4120_MTHILO, | |
908 | NUM_FIX_VR4120_CLASSES | |
909 | }; | |
910 | ||
c67a084a NC |
911 | /* ...likewise -mfix-loongson2f-jump. */ |
912 | static bfd_boolean mips_fix_loongson2f_jump; | |
913 | ||
914 | /* ...likewise -mfix-loongson2f-nop. */ | |
915 | static bfd_boolean mips_fix_loongson2f_nop; | |
916 | ||
917 | /* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */ | |
918 | static bfd_boolean mips_fix_loongson2f; | |
919 | ||
71400594 RS |
920 | /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if |
921 | there must be at least one other instruction between an instruction | |
922 | of type X and an instruction of type Y. */ | |
923 | static unsigned int vr4120_conflicts[NUM_FIX_VR4120_CLASSES]; | |
924 | ||
925 | /* True if -mfix-vr4120 is in force. */ | |
d766e8ec | 926 | static int mips_fix_vr4120; |
4a6a3df4 | 927 | |
7d8e00cf RS |
928 | /* ...likewise -mfix-vr4130. */ |
929 | static int mips_fix_vr4130; | |
930 | ||
6a32d874 CM |
931 | /* ...likewise -mfix-24k. */ |
932 | static int mips_fix_24k; | |
933 | ||
a8d14a88 CM |
934 | /* ...likewise -mfix-rm7000 */ |
935 | static int mips_fix_rm7000; | |
936 | ||
d954098f DD |
937 | /* ...likewise -mfix-cn63xxp1 */ |
938 | static bfd_boolean mips_fix_cn63xxp1; | |
939 | ||
4a6a3df4 AO |
940 | /* We don't relax branches by default, since this causes us to expand |
941 | `la .l2 - .l1' if there's a branch between .l1 and .l2, because we | |
942 | fail to compute the offset before expanding the macro to the most | |
943 | efficient expansion. */ | |
944 | ||
945 | static int mips_relax_branch; | |
8b10b0b3 MR |
946 | |
947 | /* TRUE if checks are suppressed for invalid branches between ISA modes. | |
948 | Needed for broken assembly produced by some GCC versions and some | |
949 | sloppy code out there, where branches to data labels are present. */ | |
950 | static bfd_boolean mips_ignore_branch_isa; | |
252b5132 | 951 | \f |
4d7206a2 RS |
952 | /* The expansion of many macros depends on the type of symbol that |
953 | they refer to. For example, when generating position-dependent code, | |
954 | a macro that refers to a symbol may have two different expansions, | |
955 | one which uses GP-relative addresses and one which uses absolute | |
956 | addresses. When generating SVR4-style PIC, a macro may have | |
957 | different expansions for local and global symbols. | |
958 | ||
959 | We handle these situations by generating both sequences and putting | |
960 | them in variant frags. In position-dependent code, the first sequence | |
961 | will be the GP-relative one and the second sequence will be the | |
962 | absolute one. In SVR4 PIC, the first sequence will be for global | |
963 | symbols and the second will be for local symbols. | |
964 | ||
584892a6 RS |
965 | The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and |
966 | SECOND are the lengths of the two sequences in bytes. These fields | |
967 | can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition, | |
968 | the subtype has the following flags: | |
4d7206a2 | 969 | |
ce8ad872 MR |
970 | RELAX_PIC |
971 | Set if generating PIC code. | |
972 | ||
584892a6 RS |
973 | RELAX_USE_SECOND |
974 | Set if it has been decided that we should use the second | |
975 | sequence instead of the first. | |
976 | ||
977 | RELAX_SECOND_LONGER | |
978 | Set in the first variant frag if the macro's second implementation | |
979 | is longer than its first. This refers to the macro as a whole, | |
980 | not an individual relaxation. | |
981 | ||
982 | RELAX_NOMACRO | |
983 | Set in the first variant frag if the macro appeared in a .set nomacro | |
984 | block and if one alternative requires a warning but the other does not. | |
985 | ||
986 | RELAX_DELAY_SLOT | |
987 | Like RELAX_NOMACRO, but indicates that the macro appears in a branch | |
988 | delay slot. | |
4d7206a2 | 989 | |
df58fc94 RS |
990 | RELAX_DELAY_SLOT_16BIT |
991 | Like RELAX_DELAY_SLOT, but indicates that the delay slot requires a | |
992 | 16-bit instruction. | |
993 | ||
994 | RELAX_DELAY_SLOT_SIZE_FIRST | |
995 | Like RELAX_DELAY_SLOT, but indicates that the first implementation of | |
996 | the macro is of the wrong size for the branch delay slot. | |
997 | ||
998 | RELAX_DELAY_SLOT_SIZE_SECOND | |
999 | Like RELAX_DELAY_SLOT, but indicates that the second implementation of | |
1000 | the macro is of the wrong size for the branch delay slot. | |
1001 | ||
4d7206a2 RS |
1002 | The frag's "opcode" points to the first fixup for relaxable code. |
1003 | ||
1004 | Relaxable macros are generated using a sequence such as: | |
1005 | ||
1006 | relax_start (SYMBOL); | |
1007 | ... generate first expansion ... | |
1008 | relax_switch (); | |
1009 | ... generate second expansion ... | |
1010 | relax_end (); | |
1011 | ||
1012 | The code and fixups for the unwanted alternative are discarded | |
1013 | by md_convert_frag. */ | |
ce8ad872 MR |
1014 | #define RELAX_ENCODE(FIRST, SECOND, PIC) \ |
1015 | (((FIRST) << 8) | (SECOND) | ((PIC) ? 0x10000 : 0)) | |
4d7206a2 | 1016 | |
584892a6 RS |
1017 | #define RELAX_FIRST(X) (((X) >> 8) & 0xff) |
1018 | #define RELAX_SECOND(X) ((X) & 0xff) | |
ce8ad872 MR |
1019 | #define RELAX_PIC(X) (((X) & 0x10000) != 0) |
1020 | #define RELAX_USE_SECOND 0x20000 | |
1021 | #define RELAX_SECOND_LONGER 0x40000 | |
1022 | #define RELAX_NOMACRO 0x80000 | |
1023 | #define RELAX_DELAY_SLOT 0x100000 | |
1024 | #define RELAX_DELAY_SLOT_16BIT 0x200000 | |
1025 | #define RELAX_DELAY_SLOT_SIZE_FIRST 0x400000 | |
1026 | #define RELAX_DELAY_SLOT_SIZE_SECOND 0x800000 | |
252b5132 | 1027 | |
4a6a3df4 AO |
1028 | /* Branch without likely bit. If label is out of range, we turn: |
1029 | ||
134c0c8b | 1030 | beq reg1, reg2, label |
4a6a3df4 AO |
1031 | delay slot |
1032 | ||
1033 | into | |
1034 | ||
1035 | bne reg1, reg2, 0f | |
1036 | nop | |
1037 | j label | |
1038 | 0: delay slot | |
1039 | ||
1040 | with the following opcode replacements: | |
1041 | ||
1042 | beq <-> bne | |
1043 | blez <-> bgtz | |
1044 | bltz <-> bgez | |
1045 | bc1f <-> bc1t | |
1046 | ||
1047 | bltzal <-> bgezal (with jal label instead of j label) | |
1048 | ||
1049 | Even though keeping the delay slot instruction in the delay slot of | |
1050 | the branch would be more efficient, it would be very tricky to do | |
1051 | correctly, because we'd have to introduce a variable frag *after* | |
1052 | the delay slot instruction, and expand that instead. Let's do it | |
1053 | the easy way for now, even if the branch-not-taken case now costs | |
1054 | one additional instruction. Out-of-range branches are not supposed | |
1055 | to be common, anyway. | |
1056 | ||
1057 | Branch likely. If label is out of range, we turn: | |
1058 | ||
1059 | beql reg1, reg2, label | |
1060 | delay slot (annulled if branch not taken) | |
1061 | ||
1062 | into | |
1063 | ||
1064 | beql reg1, reg2, 1f | |
1065 | nop | |
1066 | beql $0, $0, 2f | |
1067 | nop | |
1068 | 1: j[al] label | |
1069 | delay slot (executed only if branch taken) | |
1070 | 2: | |
1071 | ||
1072 | It would be possible to generate a shorter sequence by losing the | |
1073 | likely bit, generating something like: | |
b34976b6 | 1074 | |
4a6a3df4 AO |
1075 | bne reg1, reg2, 0f |
1076 | nop | |
1077 | j[al] label | |
1078 | delay slot (executed only if branch taken) | |
1079 | 0: | |
1080 | ||
1081 | beql -> bne | |
1082 | bnel -> beq | |
1083 | blezl -> bgtz | |
1084 | bgtzl -> blez | |
1085 | bltzl -> bgez | |
1086 | bgezl -> bltz | |
1087 | bc1fl -> bc1t | |
1088 | bc1tl -> bc1f | |
1089 | ||
1090 | bltzall -> bgezal (with jal label instead of j label) | |
1091 | bgezall -> bltzal (ditto) | |
1092 | ||
1093 | ||
1094 | but it's not clear that it would actually improve performance. */ | |
ce8ad872 MR |
1095 | #define RELAX_BRANCH_ENCODE(at, pic, \ |
1096 | uncond, likely, link, toofar) \ | |
66b3e8da MR |
1097 | ((relax_substateT) \ |
1098 | (0xc0000000 \ | |
1099 | | ((at) & 0x1f) \ | |
ce8ad872 MR |
1100 | | ((pic) ? 0x20 : 0) \ |
1101 | | ((toofar) ? 0x40 : 0) \ | |
1102 | | ((link) ? 0x80 : 0) \ | |
1103 | | ((likely) ? 0x100 : 0) \ | |
1104 | | ((uncond) ? 0x200 : 0))) | |
4a6a3df4 | 1105 | #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000) |
ce8ad872 MR |
1106 | #define RELAX_BRANCH_UNCOND(i) (((i) & 0x200) != 0) |
1107 | #define RELAX_BRANCH_LIKELY(i) (((i) & 0x100) != 0) | |
1108 | #define RELAX_BRANCH_LINK(i) (((i) & 0x80) != 0) | |
1109 | #define RELAX_BRANCH_TOOFAR(i) (((i) & 0x40) != 0) | |
1110 | #define RELAX_BRANCH_PIC(i) (((i) & 0x20) != 0) | |
66b3e8da | 1111 | #define RELAX_BRANCH_AT(i) ((i) & 0x1f) |
4a6a3df4 | 1112 | |
252b5132 RH |
1113 | /* For mips16 code, we use an entirely different form of relaxation. |
1114 | mips16 supports two versions of most instructions which take | |
1115 | immediate values: a small one which takes some small value, and a | |
1116 | larger one which takes a 16 bit value. Since branches also follow | |
1117 | this pattern, relaxing these values is required. | |
1118 | ||
1119 | We can assemble both mips16 and normal MIPS code in a single | |
1120 | object. Therefore, we need to support this type of relaxation at | |
1121 | the same time that we support the relaxation described above. We | |
1122 | use the high bit of the subtype field to distinguish these cases. | |
1123 | ||
1124 | The information we store for this type of relaxation is the | |
1125 | argument code found in the opcode file for this relocation, whether | |
1126 | the user explicitly requested a small or extended form, and whether | |
1127 | the relocation is in a jump or jal delay slot. That tells us the | |
1128 | size of the value, and how it should be stored. We also store | |
1129 | whether the fragment is considered to be extended or not. We also | |
1130 | store whether this is known to be a branch to a different section, | |
1131 | whether we have tried to relax this frag yet, and whether we have | |
1132 | ever extended a PC relative fragment because of a shift count. */ | |
8507b6e7 MR |
1133 | #define RELAX_MIPS16_ENCODE(type, pic, sym32, nomacro, \ |
1134 | small, ext, \ | |
1135 | dslot, jal_dslot) \ | |
252b5132 RH |
1136 | (0x80000000 \ |
1137 | | ((type) & 0xff) \ | |
8507b6e7 MR |
1138 | | ((pic) ? 0x100 : 0) \ |
1139 | | ((sym32) ? 0x200 : 0) \ | |
1140 | | ((nomacro) ? 0x400 : 0) \ | |
1141 | | ((small) ? 0x800 : 0) \ | |
1142 | | ((ext) ? 0x1000 : 0) \ | |
1143 | | ((dslot) ? 0x2000 : 0) \ | |
1144 | | ((jal_dslot) ? 0x4000 : 0)) | |
1145 | ||
4a6a3df4 | 1146 | #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000) |
252b5132 | 1147 | #define RELAX_MIPS16_TYPE(i) ((i) & 0xff) |
8507b6e7 MR |
1148 | #define RELAX_MIPS16_PIC(i) (((i) & 0x100) != 0) |
1149 | #define RELAX_MIPS16_SYM32(i) (((i) & 0x200) != 0) | |
1150 | #define RELAX_MIPS16_NOMACRO(i) (((i) & 0x400) != 0) | |
1151 | #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x800) != 0) | |
1152 | #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x1000) != 0) | |
1153 | #define RELAX_MIPS16_DSLOT(i) (((i) & 0x2000) != 0) | |
1154 | #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x4000) != 0) | |
1155 | ||
1156 | #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x8000) != 0) | |
1157 | #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x8000) | |
1158 | #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) & ~0x8000) | |
1159 | #define RELAX_MIPS16_ALWAYS_EXTENDED(i) (((i) & 0x10000) != 0) | |
1160 | #define RELAX_MIPS16_MARK_ALWAYS_EXTENDED(i) ((i) | 0x10000) | |
1161 | #define RELAX_MIPS16_CLEAR_ALWAYS_EXTENDED(i) ((i) & ~0x10000) | |
1162 | #define RELAX_MIPS16_MACRO(i) (((i) & 0x20000) != 0) | |
1163 | #define RELAX_MIPS16_MARK_MACRO(i) ((i) | 0x20000) | |
1164 | #define RELAX_MIPS16_CLEAR_MACRO(i) ((i) & ~0x20000) | |
885add95 | 1165 | |
df58fc94 RS |
1166 | /* For microMIPS code, we use relaxation similar to one we use for |
1167 | MIPS16 code. Some instructions that take immediate values support | |
1168 | two encodings: a small one which takes some small value, and a | |
1169 | larger one which takes a 16 bit value. As some branches also follow | |
1170 | this pattern, relaxing these values is required. | |
1171 | ||
1172 | We can assemble both microMIPS and normal MIPS code in a single | |
1173 | object. Therefore, we need to support this type of relaxation at | |
1174 | the same time that we support the relaxation described above. We | |
1175 | use one of the high bits of the subtype field to distinguish these | |
1176 | cases. | |
1177 | ||
1178 | The information we store for this type of relaxation is the argument | |
1179 | code found in the opcode file for this relocation, the register | |
8484fb75 MR |
1180 | selected as the assembler temporary, whether in the 32-bit |
1181 | instruction mode, whether the branch is unconditional, whether it is | |
7bd374a4 MR |
1182 | compact, whether there is no delay-slot instruction available to fill |
1183 | in, whether it stores the link address implicitly in $ra, whether | |
1184 | relaxation of out-of-range 32-bit branches to a sequence of | |
8484fb75 MR |
1185 | instructions is enabled, and whether the displacement of a branch is |
1186 | too large to fit as an immediate argument of a 16-bit and a 32-bit | |
1187 | branch, respectively. */ | |
ce8ad872 | 1188 | #define RELAX_MICROMIPS_ENCODE(type, at, insn32, pic, \ |
7bd374a4 | 1189 | uncond, compact, link, nods, \ |
40209cad MR |
1190 | relax32, toofar16, toofar32) \ |
1191 | (0x40000000 \ | |
1192 | | ((type) & 0xff) \ | |
1193 | | (((at) & 0x1f) << 8) \ | |
8484fb75 | 1194 | | ((insn32) ? 0x2000 : 0) \ |
ce8ad872 MR |
1195 | | ((pic) ? 0x4000 : 0) \ |
1196 | | ((uncond) ? 0x8000 : 0) \ | |
1197 | | ((compact) ? 0x10000 : 0) \ | |
1198 | | ((link) ? 0x20000 : 0) \ | |
1199 | | ((nods) ? 0x40000 : 0) \ | |
1200 | | ((relax32) ? 0x80000 : 0) \ | |
1201 | | ((toofar16) ? 0x100000 : 0) \ | |
1202 | | ((toofar32) ? 0x200000 : 0)) | |
df58fc94 RS |
1203 | #define RELAX_MICROMIPS_P(i) (((i) & 0xc0000000) == 0x40000000) |
1204 | #define RELAX_MICROMIPS_TYPE(i) ((i) & 0xff) | |
1205 | #define RELAX_MICROMIPS_AT(i) (((i) >> 8) & 0x1f) | |
8484fb75 | 1206 | #define RELAX_MICROMIPS_INSN32(i) (((i) & 0x2000) != 0) |
ce8ad872 MR |
1207 | #define RELAX_MICROMIPS_PIC(i) (((i) & 0x4000) != 0) |
1208 | #define RELAX_MICROMIPS_UNCOND(i) (((i) & 0x8000) != 0) | |
1209 | #define RELAX_MICROMIPS_COMPACT(i) (((i) & 0x10000) != 0) | |
1210 | #define RELAX_MICROMIPS_LINK(i) (((i) & 0x20000) != 0) | |
1211 | #define RELAX_MICROMIPS_NODS(i) (((i) & 0x40000) != 0) | |
1212 | #define RELAX_MICROMIPS_RELAX32(i) (((i) & 0x80000) != 0) | |
1213 | ||
1214 | #define RELAX_MICROMIPS_TOOFAR16(i) (((i) & 0x100000) != 0) | |
1215 | #define RELAX_MICROMIPS_MARK_TOOFAR16(i) ((i) | 0x100000) | |
1216 | #define RELAX_MICROMIPS_CLEAR_TOOFAR16(i) ((i) & ~0x100000) | |
1217 | #define RELAX_MICROMIPS_TOOFAR32(i) (((i) & 0x200000) != 0) | |
1218 | #define RELAX_MICROMIPS_MARK_TOOFAR32(i) ((i) | 0x200000) | |
1219 | #define RELAX_MICROMIPS_CLEAR_TOOFAR32(i) ((i) & ~0x200000) | |
df58fc94 | 1220 | |
43c0598f RS |
1221 | /* Sign-extend 16-bit value X. */ |
1222 | #define SEXT_16BIT(X) ((((X) + 0x8000) & 0xffff) - 0x8000) | |
1223 | ||
885add95 CD |
1224 | /* Is the given value a sign-extended 32-bit value? */ |
1225 | #define IS_SEXT_32BIT_NUM(x) \ | |
1226 | (((x) &~ (offsetT) 0x7fffffff) == 0 \ | |
1227 | || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff)) | |
1228 | ||
1229 | /* Is the given value a sign-extended 16-bit value? */ | |
1230 | #define IS_SEXT_16BIT_NUM(x) \ | |
1231 | (((x) &~ (offsetT) 0x7fff) == 0 \ | |
1232 | || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff)) | |
1233 | ||
df58fc94 RS |
1234 | /* Is the given value a sign-extended 12-bit value? */ |
1235 | #define IS_SEXT_12BIT_NUM(x) \ | |
1236 | (((((x) & 0xfff) ^ 0x800LL) - 0x800LL) == (x)) | |
1237 | ||
7f3c4072 CM |
1238 | /* Is the given value a sign-extended 9-bit value? */ |
1239 | #define IS_SEXT_9BIT_NUM(x) \ | |
1240 | (((((x) & 0x1ff) ^ 0x100LL) - 0x100LL) == (x)) | |
1241 | ||
2051e8c4 MR |
1242 | /* Is the given value a zero-extended 32-bit value? Or a negated one? */ |
1243 | #define IS_ZEXT_32BIT_NUM(x) \ | |
1244 | (((x) &~ (offsetT) 0xffffffff) == 0 \ | |
1245 | || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff)) | |
1246 | ||
bf12938e RS |
1247 | /* Extract bits MASK << SHIFT from STRUCT and shift them right |
1248 | SHIFT places. */ | |
1249 | #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \ | |
1250 | (((STRUCT) >> (SHIFT)) & (MASK)) | |
1251 | ||
bf12938e | 1252 | /* Extract the operand given by FIELD from mips_cl_insn INSN. */ |
df58fc94 RS |
1253 | #define EXTRACT_OPERAND(MICROMIPS, FIELD, INSN) \ |
1254 | (!(MICROMIPS) \ | |
1255 | ? EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) \ | |
1256 | : EXTRACT_BITS ((INSN).insn_opcode, \ | |
1257 | MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD)) | |
bf12938e RS |
1258 | #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \ |
1259 | EXTRACT_BITS ((INSN).insn_opcode, \ | |
1260 | MIPS16OP_MASK_##FIELD, \ | |
1261 | MIPS16OP_SH_##FIELD) | |
5c04167a RS |
1262 | |
1263 | /* The MIPS16 EXTEND opcode, shifted left 16 places. */ | |
1264 | #define MIPS16_EXTEND (0xf000U << 16) | |
4d7206a2 | 1265 | \f |
df58fc94 RS |
1266 | /* Whether or not we are emitting a branch-likely macro. */ |
1267 | static bfd_boolean emit_branch_likely_macro = FALSE; | |
1268 | ||
4d7206a2 RS |
1269 | /* Global variables used when generating relaxable macros. See the |
1270 | comment above RELAX_ENCODE for more details about how relaxation | |
1271 | is used. */ | |
1272 | static struct { | |
1273 | /* 0 if we're not emitting a relaxable macro. | |
1274 | 1 if we're emitting the first of the two relaxation alternatives. | |
1275 | 2 if we're emitting the second alternative. */ | |
1276 | int sequence; | |
1277 | ||
1278 | /* The first relaxable fixup in the current frag. (In other words, | |
1279 | the first fixup that refers to relaxable code.) */ | |
1280 | fixS *first_fixup; | |
1281 | ||
1282 | /* sizes[0] says how many bytes of the first alternative are stored in | |
1283 | the current frag. Likewise sizes[1] for the second alternative. */ | |
1284 | unsigned int sizes[2]; | |
1285 | ||
1286 | /* The symbol on which the choice of sequence depends. */ | |
1287 | symbolS *symbol; | |
1288 | } mips_relax; | |
252b5132 | 1289 | \f |
584892a6 RS |
1290 | /* Global variables used to decide whether a macro needs a warning. */ |
1291 | static struct { | |
1292 | /* True if the macro is in a branch delay slot. */ | |
1293 | bfd_boolean delay_slot_p; | |
1294 | ||
df58fc94 RS |
1295 | /* Set to the length in bytes required if the macro is in a delay slot |
1296 | that requires a specific length of instruction, otherwise zero. */ | |
1297 | unsigned int delay_slot_length; | |
1298 | ||
584892a6 RS |
1299 | /* For relaxable macros, sizes[0] is the length of the first alternative |
1300 | in bytes and sizes[1] is the length of the second alternative. | |
1301 | For non-relaxable macros, both elements give the length of the | |
1302 | macro in bytes. */ | |
1303 | unsigned int sizes[2]; | |
1304 | ||
df58fc94 RS |
1305 | /* For relaxable macros, first_insn_sizes[0] is the length of the first |
1306 | instruction of the first alternative in bytes and first_insn_sizes[1] | |
1307 | is the length of the first instruction of the second alternative. | |
1308 | For non-relaxable macros, both elements give the length of the first | |
1309 | instruction in bytes. | |
1310 | ||
1311 | Set to zero if we haven't yet seen the first instruction. */ | |
1312 | unsigned int first_insn_sizes[2]; | |
1313 | ||
1314 | /* For relaxable macros, insns[0] is the number of instructions for the | |
1315 | first alternative and insns[1] is the number of instructions for the | |
1316 | second alternative. | |
1317 | ||
1318 | For non-relaxable macros, both elements give the number of | |
1319 | instructions for the macro. */ | |
1320 | unsigned int insns[2]; | |
1321 | ||
584892a6 RS |
1322 | /* The first variant frag for this macro. */ |
1323 | fragS *first_frag; | |
1324 | } mips_macro_warning; | |
1325 | \f | |
252b5132 RH |
1326 | /* Prototypes for static functions. */ |
1327 | ||
252b5132 RH |
1328 | enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG }; |
1329 | ||
b34976b6 | 1330 | static void append_insn |
df58fc94 RS |
1331 | (struct mips_cl_insn *, expressionS *, bfd_reloc_code_real_type *, |
1332 | bfd_boolean expansionp); | |
7d10b47d | 1333 | static void mips_no_prev_insn (void); |
c67a084a | 1334 | static void macro_build (expressionS *, const char *, const char *, ...); |
b34976b6 | 1335 | static void mips16_macro_build |
03ea81db | 1336 | (expressionS *, const char *, const char *, va_list *); |
67c0d1eb | 1337 | static void load_register (int, expressionS *, int); |
584892a6 RS |
1338 | static void macro_start (void); |
1339 | static void macro_end (void); | |
833794fc | 1340 | static void macro (struct mips_cl_insn *ip, char *str); |
17a2f251 | 1341 | static void mips16_macro (struct mips_cl_insn * ip); |
17a2f251 TS |
1342 | static void mips_ip (char *str, struct mips_cl_insn * ip); |
1343 | static void mips16_ip (char *str, struct mips_cl_insn * ip); | |
b34976b6 | 1344 | static void mips16_immed |
3b4dbbbf | 1345 | (const char *, unsigned int, int, bfd_reloc_code_real_type, offsetT, |
43c0598f | 1346 | unsigned int, unsigned long *); |
5e0116d5 | 1347 | static size_t my_getSmallExpression |
17a2f251 TS |
1348 | (expressionS *, bfd_reloc_code_real_type *, char *); |
1349 | static void my_getExpression (expressionS *, char *); | |
1350 | static void s_align (int); | |
1351 | static void s_change_sec (int); | |
1352 | static void s_change_section (int); | |
1353 | static void s_cons (int); | |
1354 | static void s_float_cons (int); | |
1355 | static void s_mips_globl (int); | |
1356 | static void s_option (int); | |
1357 | static void s_mipsset (int); | |
1358 | static void s_abicalls (int); | |
1359 | static void s_cpload (int); | |
1360 | static void s_cpsetup (int); | |
1361 | static void s_cplocal (int); | |
1362 | static void s_cprestore (int); | |
1363 | static void s_cpreturn (int); | |
741d6ea8 JM |
1364 | static void s_dtprelword (int); |
1365 | static void s_dtpreldword (int); | |
d0f13682 CLT |
1366 | static void s_tprelword (int); |
1367 | static void s_tpreldword (int); | |
17a2f251 TS |
1368 | static void s_gpvalue (int); |
1369 | static void s_gpword (int); | |
1370 | static void s_gpdword (int); | |
a3f278e2 | 1371 | static void s_ehword (int); |
17a2f251 TS |
1372 | static void s_cpadd (int); |
1373 | static void s_insn (int); | |
ba92f887 | 1374 | static void s_nan (int); |
919731af | 1375 | static void s_module (int); |
17a2f251 TS |
1376 | static void s_mips_ent (int); |
1377 | static void s_mips_end (int); | |
1378 | static void s_mips_frame (int); | |
1379 | static void s_mips_mask (int reg_type); | |
1380 | static void s_mips_stab (int); | |
1381 | static void s_mips_weakext (int); | |
1382 | static void s_mips_file (int); | |
1383 | static void s_mips_loc (int); | |
9e009953 | 1384 | static bfd_boolean pic_need_relax (symbolS *); |
4a6a3df4 | 1385 | static int relaxed_branch_length (fragS *, asection *, int); |
df58fc94 RS |
1386 | static int relaxed_micromips_16bit_branch_length (fragS *, asection *, int); |
1387 | static int relaxed_micromips_32bit_branch_length (fragS *, asection *, int); | |
919731af | 1388 | static void file_mips_check_options (void); |
e7af610e NC |
1389 | |
1390 | /* Table and functions used to map between CPU/ISA names, and | |
1391 | ISA levels, and CPU numbers. */ | |
1392 | ||
e972090a NC |
1393 | struct mips_cpu_info |
1394 | { | |
e7af610e | 1395 | const char *name; /* CPU or ISA name. */ |
d16afab6 RS |
1396 | int flags; /* MIPS_CPU_* flags. */ |
1397 | int ase; /* Set of ASEs implemented by the CPU. */ | |
e7af610e NC |
1398 | int isa; /* ISA level. */ |
1399 | int cpu; /* CPU number (default CPU if ISA). */ | |
1400 | }; | |
1401 | ||
ad3fea08 | 1402 | #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */ |
ad3fea08 | 1403 | |
17a2f251 TS |
1404 | static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *); |
1405 | static const struct mips_cpu_info *mips_cpu_info_from_isa (int); | |
1406 | static const struct mips_cpu_info *mips_cpu_info_from_arch (int); | |
252b5132 | 1407 | \f |
c31f3936 RS |
1408 | /* Command-line options. */ |
1409 | const char *md_shortopts = "O::g::G:"; | |
1410 | ||
1411 | enum options | |
1412 | { | |
1413 | OPTION_MARCH = OPTION_MD_BASE, | |
1414 | OPTION_MTUNE, | |
1415 | OPTION_MIPS1, | |
1416 | OPTION_MIPS2, | |
1417 | OPTION_MIPS3, | |
1418 | OPTION_MIPS4, | |
1419 | OPTION_MIPS5, | |
1420 | OPTION_MIPS32, | |
1421 | OPTION_MIPS64, | |
1422 | OPTION_MIPS32R2, | |
ae52f483 AB |
1423 | OPTION_MIPS32R3, |
1424 | OPTION_MIPS32R5, | |
7361da2c | 1425 | OPTION_MIPS32R6, |
c31f3936 | 1426 | OPTION_MIPS64R2, |
ae52f483 AB |
1427 | OPTION_MIPS64R3, |
1428 | OPTION_MIPS64R5, | |
7361da2c | 1429 | OPTION_MIPS64R6, |
c31f3936 RS |
1430 | OPTION_MIPS16, |
1431 | OPTION_NO_MIPS16, | |
1432 | OPTION_MIPS3D, | |
1433 | OPTION_NO_MIPS3D, | |
1434 | OPTION_MDMX, | |
1435 | OPTION_NO_MDMX, | |
1436 | OPTION_DSP, | |
1437 | OPTION_NO_DSP, | |
1438 | OPTION_MT, | |
1439 | OPTION_NO_MT, | |
1440 | OPTION_VIRT, | |
1441 | OPTION_NO_VIRT, | |
56d438b1 CF |
1442 | OPTION_MSA, |
1443 | OPTION_NO_MSA, | |
c31f3936 RS |
1444 | OPTION_SMARTMIPS, |
1445 | OPTION_NO_SMARTMIPS, | |
1446 | OPTION_DSPR2, | |
1447 | OPTION_NO_DSPR2, | |
8f4f9071 MF |
1448 | OPTION_DSPR3, |
1449 | OPTION_NO_DSPR3, | |
c31f3936 RS |
1450 | OPTION_EVA, |
1451 | OPTION_NO_EVA, | |
7d64c587 AB |
1452 | OPTION_XPA, |
1453 | OPTION_NO_XPA, | |
c31f3936 RS |
1454 | OPTION_MICROMIPS, |
1455 | OPTION_NO_MICROMIPS, | |
1456 | OPTION_MCU, | |
1457 | OPTION_NO_MCU, | |
1458 | OPTION_COMPAT_ARCH_BASE, | |
1459 | OPTION_M4650, | |
1460 | OPTION_NO_M4650, | |
1461 | OPTION_M4010, | |
1462 | OPTION_NO_M4010, | |
1463 | OPTION_M4100, | |
1464 | OPTION_NO_M4100, | |
1465 | OPTION_M3900, | |
1466 | OPTION_NO_M3900, | |
1467 | OPTION_M7000_HILO_FIX, | |
1468 | OPTION_MNO_7000_HILO_FIX, | |
1469 | OPTION_FIX_24K, | |
1470 | OPTION_NO_FIX_24K, | |
a8d14a88 CM |
1471 | OPTION_FIX_RM7000, |
1472 | OPTION_NO_FIX_RM7000, | |
c31f3936 RS |
1473 | OPTION_FIX_LOONGSON2F_JUMP, |
1474 | OPTION_NO_FIX_LOONGSON2F_JUMP, | |
1475 | OPTION_FIX_LOONGSON2F_NOP, | |
1476 | OPTION_NO_FIX_LOONGSON2F_NOP, | |
1477 | OPTION_FIX_VR4120, | |
1478 | OPTION_NO_FIX_VR4120, | |
1479 | OPTION_FIX_VR4130, | |
1480 | OPTION_NO_FIX_VR4130, | |
1481 | OPTION_FIX_CN63XXP1, | |
1482 | OPTION_NO_FIX_CN63XXP1, | |
1483 | OPTION_TRAP, | |
1484 | OPTION_BREAK, | |
1485 | OPTION_EB, | |
1486 | OPTION_EL, | |
1487 | OPTION_FP32, | |
1488 | OPTION_GP32, | |
1489 | OPTION_CONSTRUCT_FLOATS, | |
1490 | OPTION_NO_CONSTRUCT_FLOATS, | |
1491 | OPTION_FP64, | |
351cdf24 | 1492 | OPTION_FPXX, |
c31f3936 RS |
1493 | OPTION_GP64, |
1494 | OPTION_RELAX_BRANCH, | |
1495 | OPTION_NO_RELAX_BRANCH, | |
8b10b0b3 MR |
1496 | OPTION_IGNORE_BRANCH_ISA, |
1497 | OPTION_NO_IGNORE_BRANCH_ISA, | |
833794fc MR |
1498 | OPTION_INSN32, |
1499 | OPTION_NO_INSN32, | |
c31f3936 RS |
1500 | OPTION_MSHARED, |
1501 | OPTION_MNO_SHARED, | |
1502 | OPTION_MSYM32, | |
1503 | OPTION_MNO_SYM32, | |
1504 | OPTION_SOFT_FLOAT, | |
1505 | OPTION_HARD_FLOAT, | |
1506 | OPTION_SINGLE_FLOAT, | |
1507 | OPTION_DOUBLE_FLOAT, | |
1508 | OPTION_32, | |
c31f3936 RS |
1509 | OPTION_CALL_SHARED, |
1510 | OPTION_CALL_NONPIC, | |
1511 | OPTION_NON_SHARED, | |
1512 | OPTION_XGOT, | |
1513 | OPTION_MABI, | |
1514 | OPTION_N32, | |
1515 | OPTION_64, | |
1516 | OPTION_MDEBUG, | |
1517 | OPTION_NO_MDEBUG, | |
1518 | OPTION_PDR, | |
1519 | OPTION_NO_PDR, | |
1520 | OPTION_MVXWORKS_PIC, | |
ba92f887 | 1521 | OPTION_NAN, |
351cdf24 MF |
1522 | OPTION_ODD_SPREG, |
1523 | OPTION_NO_ODD_SPREG, | |
c31f3936 RS |
1524 | OPTION_END_OF_ENUM |
1525 | }; | |
1526 | ||
1527 | struct option md_longopts[] = | |
1528 | { | |
1529 | /* Options which specify architecture. */ | |
1530 | {"march", required_argument, NULL, OPTION_MARCH}, | |
1531 | {"mtune", required_argument, NULL, OPTION_MTUNE}, | |
1532 | {"mips0", no_argument, NULL, OPTION_MIPS1}, | |
1533 | {"mips1", no_argument, NULL, OPTION_MIPS1}, | |
1534 | {"mips2", no_argument, NULL, OPTION_MIPS2}, | |
1535 | {"mips3", no_argument, NULL, OPTION_MIPS3}, | |
1536 | {"mips4", no_argument, NULL, OPTION_MIPS4}, | |
1537 | {"mips5", no_argument, NULL, OPTION_MIPS5}, | |
1538 | {"mips32", no_argument, NULL, OPTION_MIPS32}, | |
1539 | {"mips64", no_argument, NULL, OPTION_MIPS64}, | |
1540 | {"mips32r2", no_argument, NULL, OPTION_MIPS32R2}, | |
ae52f483 AB |
1541 | {"mips32r3", no_argument, NULL, OPTION_MIPS32R3}, |
1542 | {"mips32r5", no_argument, NULL, OPTION_MIPS32R5}, | |
7361da2c | 1543 | {"mips32r6", no_argument, NULL, OPTION_MIPS32R6}, |
c31f3936 | 1544 | {"mips64r2", no_argument, NULL, OPTION_MIPS64R2}, |
ae52f483 AB |
1545 | {"mips64r3", no_argument, NULL, OPTION_MIPS64R3}, |
1546 | {"mips64r5", no_argument, NULL, OPTION_MIPS64R5}, | |
7361da2c | 1547 | {"mips64r6", no_argument, NULL, OPTION_MIPS64R6}, |
c31f3936 RS |
1548 | |
1549 | /* Options which specify Application Specific Extensions (ASEs). */ | |
1550 | {"mips16", no_argument, NULL, OPTION_MIPS16}, | |
1551 | {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16}, | |
1552 | {"mips3d", no_argument, NULL, OPTION_MIPS3D}, | |
1553 | {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D}, | |
1554 | {"mdmx", no_argument, NULL, OPTION_MDMX}, | |
1555 | {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX}, | |
1556 | {"mdsp", no_argument, NULL, OPTION_DSP}, | |
1557 | {"mno-dsp", no_argument, NULL, OPTION_NO_DSP}, | |
1558 | {"mmt", no_argument, NULL, OPTION_MT}, | |
1559 | {"mno-mt", no_argument, NULL, OPTION_NO_MT}, | |
1560 | {"msmartmips", no_argument, NULL, OPTION_SMARTMIPS}, | |
1561 | {"mno-smartmips", no_argument, NULL, OPTION_NO_SMARTMIPS}, | |
1562 | {"mdspr2", no_argument, NULL, OPTION_DSPR2}, | |
1563 | {"mno-dspr2", no_argument, NULL, OPTION_NO_DSPR2}, | |
8f4f9071 MF |
1564 | {"mdspr3", no_argument, NULL, OPTION_DSPR3}, |
1565 | {"mno-dspr3", no_argument, NULL, OPTION_NO_DSPR3}, | |
c31f3936 RS |
1566 | {"meva", no_argument, NULL, OPTION_EVA}, |
1567 | {"mno-eva", no_argument, NULL, OPTION_NO_EVA}, | |
1568 | {"mmicromips", no_argument, NULL, OPTION_MICROMIPS}, | |
1569 | {"mno-micromips", no_argument, NULL, OPTION_NO_MICROMIPS}, | |
1570 | {"mmcu", no_argument, NULL, OPTION_MCU}, | |
1571 | {"mno-mcu", no_argument, NULL, OPTION_NO_MCU}, | |
1572 | {"mvirt", no_argument, NULL, OPTION_VIRT}, | |
1573 | {"mno-virt", no_argument, NULL, OPTION_NO_VIRT}, | |
56d438b1 CF |
1574 | {"mmsa", no_argument, NULL, OPTION_MSA}, |
1575 | {"mno-msa", no_argument, NULL, OPTION_NO_MSA}, | |
7d64c587 AB |
1576 | {"mxpa", no_argument, NULL, OPTION_XPA}, |
1577 | {"mno-xpa", no_argument, NULL, OPTION_NO_XPA}, | |
c31f3936 RS |
1578 | |
1579 | /* Old-style architecture options. Don't add more of these. */ | |
1580 | {"m4650", no_argument, NULL, OPTION_M4650}, | |
1581 | {"no-m4650", no_argument, NULL, OPTION_NO_M4650}, | |
1582 | {"m4010", no_argument, NULL, OPTION_M4010}, | |
1583 | {"no-m4010", no_argument, NULL, OPTION_NO_M4010}, | |
1584 | {"m4100", no_argument, NULL, OPTION_M4100}, | |
1585 | {"no-m4100", no_argument, NULL, OPTION_NO_M4100}, | |
1586 | {"m3900", no_argument, NULL, OPTION_M3900}, | |
1587 | {"no-m3900", no_argument, NULL, OPTION_NO_M3900}, | |
1588 | ||
1589 | /* Options which enable bug fixes. */ | |
1590 | {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX}, | |
1591 | {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, | |
1592 | {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, | |
1593 | {"mfix-loongson2f-jump", no_argument, NULL, OPTION_FIX_LOONGSON2F_JUMP}, | |
1594 | {"mno-fix-loongson2f-jump", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_JUMP}, | |
1595 | {"mfix-loongson2f-nop", no_argument, NULL, OPTION_FIX_LOONGSON2F_NOP}, | |
1596 | {"mno-fix-loongson2f-nop", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_NOP}, | |
1597 | {"mfix-vr4120", no_argument, NULL, OPTION_FIX_VR4120}, | |
1598 | {"mno-fix-vr4120", no_argument, NULL, OPTION_NO_FIX_VR4120}, | |
1599 | {"mfix-vr4130", no_argument, NULL, OPTION_FIX_VR4130}, | |
1600 | {"mno-fix-vr4130", no_argument, NULL, OPTION_NO_FIX_VR4130}, | |
1601 | {"mfix-24k", no_argument, NULL, OPTION_FIX_24K}, | |
1602 | {"mno-fix-24k", no_argument, NULL, OPTION_NO_FIX_24K}, | |
a8d14a88 CM |
1603 | {"mfix-rm7000", no_argument, NULL, OPTION_FIX_RM7000}, |
1604 | {"mno-fix-rm7000", no_argument, NULL, OPTION_NO_FIX_RM7000}, | |
c31f3936 RS |
1605 | {"mfix-cn63xxp1", no_argument, NULL, OPTION_FIX_CN63XXP1}, |
1606 | {"mno-fix-cn63xxp1", no_argument, NULL, OPTION_NO_FIX_CN63XXP1}, | |
1607 | ||
1608 | /* Miscellaneous options. */ | |
1609 | {"trap", no_argument, NULL, OPTION_TRAP}, | |
1610 | {"no-break", no_argument, NULL, OPTION_TRAP}, | |
1611 | {"break", no_argument, NULL, OPTION_BREAK}, | |
1612 | {"no-trap", no_argument, NULL, OPTION_BREAK}, | |
1613 | {"EB", no_argument, NULL, OPTION_EB}, | |
1614 | {"EL", no_argument, NULL, OPTION_EL}, | |
1615 | {"mfp32", no_argument, NULL, OPTION_FP32}, | |
1616 | {"mgp32", no_argument, NULL, OPTION_GP32}, | |
1617 | {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS}, | |
1618 | {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS}, | |
1619 | {"mfp64", no_argument, NULL, OPTION_FP64}, | |
351cdf24 | 1620 | {"mfpxx", no_argument, NULL, OPTION_FPXX}, |
c31f3936 RS |
1621 | {"mgp64", no_argument, NULL, OPTION_GP64}, |
1622 | {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH}, | |
1623 | {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH}, | |
8b10b0b3 MR |
1624 | {"mignore-branch-isa", no_argument, NULL, OPTION_IGNORE_BRANCH_ISA}, |
1625 | {"mno-ignore-branch-isa", no_argument, NULL, OPTION_NO_IGNORE_BRANCH_ISA}, | |
833794fc MR |
1626 | {"minsn32", no_argument, NULL, OPTION_INSN32}, |
1627 | {"mno-insn32", no_argument, NULL, OPTION_NO_INSN32}, | |
c31f3936 RS |
1628 | {"mshared", no_argument, NULL, OPTION_MSHARED}, |
1629 | {"mno-shared", no_argument, NULL, OPTION_MNO_SHARED}, | |
1630 | {"msym32", no_argument, NULL, OPTION_MSYM32}, | |
1631 | {"mno-sym32", no_argument, NULL, OPTION_MNO_SYM32}, | |
1632 | {"msoft-float", no_argument, NULL, OPTION_SOFT_FLOAT}, | |
1633 | {"mhard-float", no_argument, NULL, OPTION_HARD_FLOAT}, | |
1634 | {"msingle-float", no_argument, NULL, OPTION_SINGLE_FLOAT}, | |
1635 | {"mdouble-float", no_argument, NULL, OPTION_DOUBLE_FLOAT}, | |
351cdf24 MF |
1636 | {"modd-spreg", no_argument, NULL, OPTION_ODD_SPREG}, |
1637 | {"mno-odd-spreg", no_argument, NULL, OPTION_NO_ODD_SPREG}, | |
c31f3936 RS |
1638 | |
1639 | /* Strictly speaking this next option is ELF specific, | |
1640 | but we allow it for other ports as well in order to | |
1641 | make testing easier. */ | |
1642 | {"32", no_argument, NULL, OPTION_32}, | |
1643 | ||
1644 | /* ELF-specific options. */ | |
c31f3936 RS |
1645 | {"KPIC", no_argument, NULL, OPTION_CALL_SHARED}, |
1646 | {"call_shared", no_argument, NULL, OPTION_CALL_SHARED}, | |
1647 | {"call_nonpic", no_argument, NULL, OPTION_CALL_NONPIC}, | |
1648 | {"non_shared", no_argument, NULL, OPTION_NON_SHARED}, | |
1649 | {"xgot", no_argument, NULL, OPTION_XGOT}, | |
1650 | {"mabi", required_argument, NULL, OPTION_MABI}, | |
1651 | {"n32", no_argument, NULL, OPTION_N32}, | |
1652 | {"64", no_argument, NULL, OPTION_64}, | |
1653 | {"mdebug", no_argument, NULL, OPTION_MDEBUG}, | |
1654 | {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG}, | |
1655 | {"mpdr", no_argument, NULL, OPTION_PDR}, | |
1656 | {"mno-pdr", no_argument, NULL, OPTION_NO_PDR}, | |
1657 | {"mvxworks-pic", no_argument, NULL, OPTION_MVXWORKS_PIC}, | |
ba92f887 | 1658 | {"mnan", required_argument, NULL, OPTION_NAN}, |
c31f3936 RS |
1659 | |
1660 | {NULL, no_argument, NULL, 0} | |
1661 | }; | |
1662 | size_t md_longopts_size = sizeof (md_longopts); | |
1663 | \f | |
c6278170 RS |
1664 | /* Information about either an Application Specific Extension or an |
1665 | optional architecture feature that, for simplicity, we treat in the | |
1666 | same way as an ASE. */ | |
1667 | struct mips_ase | |
1668 | { | |
1669 | /* The name of the ASE, used in both the command-line and .set options. */ | |
1670 | const char *name; | |
1671 | ||
1672 | /* The associated ASE_* flags. If the ASE is available on both 32-bit | |
1673 | and 64-bit architectures, the flags here refer to the subset that | |
1674 | is available on both. */ | |
1675 | unsigned int flags; | |
1676 | ||
1677 | /* The ASE_* flag used for instructions that are available on 64-bit | |
1678 | architectures but that are not included in FLAGS. */ | |
1679 | unsigned int flags64; | |
1680 | ||
1681 | /* The command-line options that turn the ASE on and off. */ | |
1682 | int option_on; | |
1683 | int option_off; | |
1684 | ||
1685 | /* The minimum required architecture revisions for MIPS32, MIPS64, | |
1686 | microMIPS32 and microMIPS64, or -1 if the extension isn't supported. */ | |
1687 | int mips32_rev; | |
1688 | int mips64_rev; | |
1689 | int micromips32_rev; | |
1690 | int micromips64_rev; | |
7361da2c AB |
1691 | |
1692 | /* The architecture where the ASE was removed or -1 if the extension has not | |
1693 | been removed. */ | |
1694 | int rem_rev; | |
c6278170 RS |
1695 | }; |
1696 | ||
1697 | /* A table of all supported ASEs. */ | |
1698 | static const struct mips_ase mips_ases[] = { | |
1699 | { "dsp", ASE_DSP, ASE_DSP64, | |
1700 | OPTION_DSP, OPTION_NO_DSP, | |
7361da2c AB |
1701 | 2, 2, 2, 2, |
1702 | -1 }, | |
c6278170 RS |
1703 | |
1704 | { "dspr2", ASE_DSP | ASE_DSPR2, 0, | |
1705 | OPTION_DSPR2, OPTION_NO_DSPR2, | |
7361da2c AB |
1706 | 2, 2, 2, 2, |
1707 | -1 }, | |
c6278170 | 1708 | |
8f4f9071 MF |
1709 | { "dspr3", ASE_DSP | ASE_DSPR2 | ASE_DSPR3, 0, |
1710 | OPTION_DSPR3, OPTION_NO_DSPR3, | |
1711 | 6, 6, -1, -1, | |
1712 | -1 }, | |
1713 | ||
c6278170 RS |
1714 | { "eva", ASE_EVA, 0, |
1715 | OPTION_EVA, OPTION_NO_EVA, | |
7361da2c AB |
1716 | 2, 2, 2, 2, |
1717 | -1 }, | |
c6278170 RS |
1718 | |
1719 | { "mcu", ASE_MCU, 0, | |
1720 | OPTION_MCU, OPTION_NO_MCU, | |
7361da2c AB |
1721 | 2, 2, 2, 2, |
1722 | -1 }, | |
c6278170 RS |
1723 | |
1724 | /* Deprecated in MIPS64r5, but we don't implement that yet. */ | |
1725 | { "mdmx", ASE_MDMX, 0, | |
1726 | OPTION_MDMX, OPTION_NO_MDMX, | |
7361da2c AB |
1727 | -1, 1, -1, -1, |
1728 | 6 }, | |
c6278170 RS |
1729 | |
1730 | /* Requires 64-bit FPRs, so the minimum MIPS32 revision is 2. */ | |
1731 | { "mips3d", ASE_MIPS3D, 0, | |
1732 | OPTION_MIPS3D, OPTION_NO_MIPS3D, | |
7361da2c AB |
1733 | 2, 1, -1, -1, |
1734 | 6 }, | |
c6278170 RS |
1735 | |
1736 | { "mt", ASE_MT, 0, | |
1737 | OPTION_MT, OPTION_NO_MT, | |
7361da2c AB |
1738 | 2, 2, -1, -1, |
1739 | -1 }, | |
c6278170 RS |
1740 | |
1741 | { "smartmips", ASE_SMARTMIPS, 0, | |
1742 | OPTION_SMARTMIPS, OPTION_NO_SMARTMIPS, | |
7361da2c AB |
1743 | 1, -1, -1, -1, |
1744 | 6 }, | |
c6278170 RS |
1745 | |
1746 | { "virt", ASE_VIRT, ASE_VIRT64, | |
1747 | OPTION_VIRT, OPTION_NO_VIRT, | |
7361da2c AB |
1748 | 2, 2, 2, 2, |
1749 | -1 }, | |
56d438b1 CF |
1750 | |
1751 | { "msa", ASE_MSA, ASE_MSA64, | |
1752 | OPTION_MSA, OPTION_NO_MSA, | |
7361da2c AB |
1753 | 2, 2, 2, 2, |
1754 | -1 }, | |
7d64c587 AB |
1755 | |
1756 | { "xpa", ASE_XPA, 0, | |
1757 | OPTION_XPA, OPTION_NO_XPA, | |
7361da2c AB |
1758 | 2, 2, -1, -1, |
1759 | -1 }, | |
c6278170 RS |
1760 | }; |
1761 | ||
1762 | /* The set of ASEs that require -mfp64. */ | |
82bda27b | 1763 | #define FP64_ASES (ASE_MIPS3D | ASE_MDMX | ASE_MSA) |
c6278170 RS |
1764 | |
1765 | /* Groups of ASE_* flags that represent different revisions of an ASE. */ | |
1766 | static const unsigned int mips_ase_groups[] = { | |
8f4f9071 | 1767 | ASE_DSP | ASE_DSPR2 | ASE_DSPR3 |
c6278170 RS |
1768 | }; |
1769 | \f | |
252b5132 RH |
1770 | /* Pseudo-op table. |
1771 | ||
1772 | The following pseudo-ops from the Kane and Heinrich MIPS book | |
1773 | should be defined here, but are currently unsupported: .alias, | |
1774 | .galive, .gjaldef, .gjrlive, .livereg, .noalias. | |
1775 | ||
1776 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
1777 | specific to the type of debugging information being generated, and | |
1778 | should be defined by the object format: .aent, .begin, .bend, | |
1779 | .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp, | |
1780 | .vreg. | |
1781 | ||
1782 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
1783 | not MIPS CPU specific, but are also not specific to the object file | |
1784 | format. This file is probably the best place to define them, but | |
d84bcf09 | 1785 | they are not currently supported: .asm0, .endr, .lab, .struct. */ |
252b5132 | 1786 | |
e972090a NC |
1787 | static const pseudo_typeS mips_pseudo_table[] = |
1788 | { | |
beae10d5 | 1789 | /* MIPS specific pseudo-ops. */ |
252b5132 RH |
1790 | {"option", s_option, 0}, |
1791 | {"set", s_mipsset, 0}, | |
1792 | {"rdata", s_change_sec, 'r'}, | |
1793 | {"sdata", s_change_sec, 's'}, | |
1794 | {"livereg", s_ignore, 0}, | |
1795 | {"abicalls", s_abicalls, 0}, | |
1796 | {"cpload", s_cpload, 0}, | |
6478892d TS |
1797 | {"cpsetup", s_cpsetup, 0}, |
1798 | {"cplocal", s_cplocal, 0}, | |
252b5132 | 1799 | {"cprestore", s_cprestore, 0}, |
6478892d | 1800 | {"cpreturn", s_cpreturn, 0}, |
741d6ea8 JM |
1801 | {"dtprelword", s_dtprelword, 0}, |
1802 | {"dtpreldword", s_dtpreldword, 0}, | |
d0f13682 CLT |
1803 | {"tprelword", s_tprelword, 0}, |
1804 | {"tpreldword", s_tpreldword, 0}, | |
6478892d | 1805 | {"gpvalue", s_gpvalue, 0}, |
252b5132 | 1806 | {"gpword", s_gpword, 0}, |
10181a0d | 1807 | {"gpdword", s_gpdword, 0}, |
a3f278e2 | 1808 | {"ehword", s_ehword, 0}, |
252b5132 RH |
1809 | {"cpadd", s_cpadd, 0}, |
1810 | {"insn", s_insn, 0}, | |
ba92f887 | 1811 | {"nan", s_nan, 0}, |
919731af | 1812 | {"module", s_module, 0}, |
252b5132 | 1813 | |
beae10d5 | 1814 | /* Relatively generic pseudo-ops that happen to be used on MIPS |
252b5132 | 1815 | chips. */ |
38a57ae7 | 1816 | {"asciiz", stringer, 8 + 1}, |
252b5132 RH |
1817 | {"bss", s_change_sec, 'b'}, |
1818 | {"err", s_err, 0}, | |
1819 | {"half", s_cons, 1}, | |
1820 | {"dword", s_cons, 3}, | |
1821 | {"weakext", s_mips_weakext, 0}, | |
7c752c2a TS |
1822 | {"origin", s_org, 0}, |
1823 | {"repeat", s_rept, 0}, | |
252b5132 | 1824 | |
998b3c36 MR |
1825 | /* For MIPS this is non-standard, but we define it for consistency. */ |
1826 | {"sbss", s_change_sec, 'B'}, | |
1827 | ||
beae10d5 | 1828 | /* These pseudo-ops are defined in read.c, but must be overridden |
252b5132 RH |
1829 | here for one reason or another. */ |
1830 | {"align", s_align, 0}, | |
1831 | {"byte", s_cons, 0}, | |
1832 | {"data", s_change_sec, 'd'}, | |
1833 | {"double", s_float_cons, 'd'}, | |
1834 | {"float", s_float_cons, 'f'}, | |
1835 | {"globl", s_mips_globl, 0}, | |
1836 | {"global", s_mips_globl, 0}, | |
1837 | {"hword", s_cons, 1}, | |
1838 | {"int", s_cons, 2}, | |
1839 | {"long", s_cons, 2}, | |
1840 | {"octa", s_cons, 4}, | |
1841 | {"quad", s_cons, 3}, | |
cca86cc8 | 1842 | {"section", s_change_section, 0}, |
252b5132 RH |
1843 | {"short", s_cons, 1}, |
1844 | {"single", s_float_cons, 'f'}, | |
754e2bb9 | 1845 | {"stabd", s_mips_stab, 'd'}, |
252b5132 | 1846 | {"stabn", s_mips_stab, 'n'}, |
754e2bb9 | 1847 | {"stabs", s_mips_stab, 's'}, |
252b5132 RH |
1848 | {"text", s_change_sec, 't'}, |
1849 | {"word", s_cons, 2}, | |
add56521 | 1850 | |
add56521 | 1851 | { "extern", ecoff_directive_extern, 0}, |
add56521 | 1852 | |
43841e91 | 1853 | { NULL, NULL, 0 }, |
252b5132 RH |
1854 | }; |
1855 | ||
e972090a NC |
1856 | static const pseudo_typeS mips_nonecoff_pseudo_table[] = |
1857 | { | |
beae10d5 KH |
1858 | /* These pseudo-ops should be defined by the object file format. |
1859 | However, a.out doesn't support them, so we have versions here. */ | |
252b5132 RH |
1860 | {"aent", s_mips_ent, 1}, |
1861 | {"bgnb", s_ignore, 0}, | |
1862 | {"end", s_mips_end, 0}, | |
1863 | {"endb", s_ignore, 0}, | |
1864 | {"ent", s_mips_ent, 0}, | |
c5dd6aab | 1865 | {"file", s_mips_file, 0}, |
252b5132 RH |
1866 | {"fmask", s_mips_mask, 'F'}, |
1867 | {"frame", s_mips_frame, 0}, | |
c5dd6aab | 1868 | {"loc", s_mips_loc, 0}, |
252b5132 RH |
1869 | {"mask", s_mips_mask, 'R'}, |
1870 | {"verstamp", s_ignore, 0}, | |
43841e91 | 1871 | { NULL, NULL, 0 }, |
252b5132 RH |
1872 | }; |
1873 | ||
3ae8dd8d MR |
1874 | /* Export the ABI address size for use by TC_ADDRESS_BYTES for the |
1875 | purpose of the `.dc.a' internal pseudo-op. */ | |
1876 | ||
1877 | int | |
1878 | mips_address_bytes (void) | |
1879 | { | |
919731af | 1880 | file_mips_check_options (); |
3ae8dd8d MR |
1881 | return HAVE_64BIT_ADDRESSES ? 8 : 4; |
1882 | } | |
1883 | ||
17a2f251 | 1884 | extern void pop_insert (const pseudo_typeS *); |
252b5132 RH |
1885 | |
1886 | void | |
17a2f251 | 1887 | mips_pop_insert (void) |
252b5132 RH |
1888 | { |
1889 | pop_insert (mips_pseudo_table); | |
1890 | if (! ECOFF_DEBUGGING) | |
1891 | pop_insert (mips_nonecoff_pseudo_table); | |
1892 | } | |
1893 | \f | |
1894 | /* Symbols labelling the current insn. */ | |
1895 | ||
e972090a NC |
1896 | struct insn_label_list |
1897 | { | |
252b5132 RH |
1898 | struct insn_label_list *next; |
1899 | symbolS *label; | |
1900 | }; | |
1901 | ||
252b5132 | 1902 | static struct insn_label_list *free_insn_labels; |
742a56fe | 1903 | #define label_list tc_segment_info_data.labels |
252b5132 | 1904 | |
17a2f251 | 1905 | static void mips_clear_insn_labels (void); |
df58fc94 RS |
1906 | static void mips_mark_labels (void); |
1907 | static void mips_compressed_mark_labels (void); | |
252b5132 RH |
1908 | |
1909 | static inline void | |
17a2f251 | 1910 | mips_clear_insn_labels (void) |
252b5132 | 1911 | { |
ed9e98c2 | 1912 | struct insn_label_list **pl; |
a8dbcb85 | 1913 | segment_info_type *si; |
252b5132 | 1914 | |
a8dbcb85 TS |
1915 | if (now_seg) |
1916 | { | |
1917 | for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next) | |
1918 | ; | |
3739860c | 1919 | |
a8dbcb85 TS |
1920 | si = seg_info (now_seg); |
1921 | *pl = si->label_list; | |
1922 | si->label_list = NULL; | |
1923 | } | |
252b5132 | 1924 | } |
a8dbcb85 | 1925 | |
df58fc94 RS |
1926 | /* Mark instruction labels in MIPS16/microMIPS mode. */ |
1927 | ||
1928 | static inline void | |
1929 | mips_mark_labels (void) | |
1930 | { | |
1931 | if (HAVE_CODE_COMPRESSION) | |
1932 | mips_compressed_mark_labels (); | |
1933 | } | |
252b5132 RH |
1934 | \f |
1935 | static char *expr_end; | |
1936 | ||
e423441d | 1937 | /* An expression in a macro instruction. This is set by mips_ip and |
b0e6f033 | 1938 | mips16_ip and when populated is always an O_constant. */ |
252b5132 RH |
1939 | |
1940 | static expressionS imm_expr; | |
252b5132 | 1941 | |
77bd4346 RS |
1942 | /* The relocatable field in an instruction and the relocs associated |
1943 | with it. These variables are used for instructions like LUI and | |
1944 | JAL as well as true offsets. They are also used for address | |
1945 | operands in macros. */ | |
252b5132 | 1946 | |
77bd4346 | 1947 | static expressionS offset_expr; |
f6688943 TS |
1948 | static bfd_reloc_code_real_type offset_reloc[3] |
1949 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 1950 | |
df58fc94 RS |
1951 | /* This is set to the resulting size of the instruction to be produced |
1952 | by mips16_ip if an explicit extension is used or by mips_ip if an | |
1953 | explicit size is supplied. */ | |
252b5132 | 1954 | |
df58fc94 | 1955 | static unsigned int forced_insn_length; |
252b5132 | 1956 | |
e1b47bd5 RS |
1957 | /* True if we are assembling an instruction. All dot symbols defined during |
1958 | this time should be treated as code labels. */ | |
1959 | ||
1960 | static bfd_boolean mips_assembling_insn; | |
1961 | ||
ecb4347a DJ |
1962 | /* The pdr segment for per procedure frame/regmask info. Not used for |
1963 | ECOFF debugging. */ | |
252b5132 RH |
1964 | |
1965 | static segT pdr_seg; | |
252b5132 | 1966 | |
e013f690 TS |
1967 | /* The default target format to use. */ |
1968 | ||
aeffff67 RS |
1969 | #if defined (TE_FreeBSD) |
1970 | #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd" | |
1971 | #elif defined (TE_TMIPS) | |
1972 | #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips" | |
1973 | #else | |
1974 | #define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips" | |
1975 | #endif | |
1976 | ||
e013f690 | 1977 | const char * |
17a2f251 | 1978 | mips_target_format (void) |
e013f690 TS |
1979 | { |
1980 | switch (OUTPUT_FLAVOR) | |
1981 | { | |
e013f690 | 1982 | case bfd_target_elf_flavour: |
0a44bf69 RS |
1983 | #ifdef TE_VXWORKS |
1984 | if (!HAVE_64BIT_OBJECTS && !HAVE_NEWABI) | |
1985 | return (target_big_endian | |
1986 | ? "elf32-bigmips-vxworks" | |
1987 | : "elf32-littlemips-vxworks"); | |
1988 | #endif | |
e013f690 | 1989 | return (target_big_endian |
cfe86eaa | 1990 | ? (HAVE_64BIT_OBJECTS |
aeffff67 | 1991 | ? ELF_TARGET ("elf64-", "big") |
cfe86eaa | 1992 | : (HAVE_NEWABI |
aeffff67 RS |
1993 | ? ELF_TARGET ("elf32-n", "big") |
1994 | : ELF_TARGET ("elf32-", "big"))) | |
cfe86eaa | 1995 | : (HAVE_64BIT_OBJECTS |
aeffff67 | 1996 | ? ELF_TARGET ("elf64-", "little") |
cfe86eaa | 1997 | : (HAVE_NEWABI |
aeffff67 RS |
1998 | ? ELF_TARGET ("elf32-n", "little") |
1999 | : ELF_TARGET ("elf32-", "little")))); | |
e013f690 TS |
2000 | default: |
2001 | abort (); | |
2002 | return NULL; | |
2003 | } | |
2004 | } | |
2005 | ||
c6278170 RS |
2006 | /* Return the ISA revision that is currently in use, or 0 if we are |
2007 | generating code for MIPS V or below. */ | |
2008 | ||
2009 | static int | |
2010 | mips_isa_rev (void) | |
2011 | { | |
2012 | if (mips_opts.isa == ISA_MIPS32R2 || mips_opts.isa == ISA_MIPS64R2) | |
2013 | return 2; | |
2014 | ||
ae52f483 AB |
2015 | if (mips_opts.isa == ISA_MIPS32R3 || mips_opts.isa == ISA_MIPS64R3) |
2016 | return 3; | |
2017 | ||
2018 | if (mips_opts.isa == ISA_MIPS32R5 || mips_opts.isa == ISA_MIPS64R5) | |
2019 | return 5; | |
2020 | ||
7361da2c AB |
2021 | if (mips_opts.isa == ISA_MIPS32R6 || mips_opts.isa == ISA_MIPS64R6) |
2022 | return 6; | |
2023 | ||
c6278170 RS |
2024 | /* microMIPS implies revision 2 or above. */ |
2025 | if (mips_opts.micromips) | |
2026 | return 2; | |
2027 | ||
2028 | if (mips_opts.isa == ISA_MIPS32 || mips_opts.isa == ISA_MIPS64) | |
2029 | return 1; | |
2030 | ||
2031 | return 0; | |
2032 | } | |
2033 | ||
2034 | /* Return the mask of all ASEs that are revisions of those in FLAGS. */ | |
2035 | ||
2036 | static unsigned int | |
2037 | mips_ase_mask (unsigned int flags) | |
2038 | { | |
2039 | unsigned int i; | |
2040 | ||
2041 | for (i = 0; i < ARRAY_SIZE (mips_ase_groups); i++) | |
2042 | if (flags & mips_ase_groups[i]) | |
2043 | flags |= mips_ase_groups[i]; | |
2044 | return flags; | |
2045 | } | |
2046 | ||
2047 | /* Check whether the current ISA supports ASE. Issue a warning if | |
2048 | appropriate. */ | |
2049 | ||
2050 | static void | |
2051 | mips_check_isa_supports_ase (const struct mips_ase *ase) | |
2052 | { | |
2053 | const char *base; | |
2054 | int min_rev, size; | |
2055 | static unsigned int warned_isa; | |
2056 | static unsigned int warned_fp32; | |
2057 | ||
2058 | if (ISA_HAS_64BIT_REGS (mips_opts.isa)) | |
2059 | min_rev = mips_opts.micromips ? ase->micromips64_rev : ase->mips64_rev; | |
2060 | else | |
2061 | min_rev = mips_opts.micromips ? ase->micromips32_rev : ase->mips32_rev; | |
2062 | if ((min_rev < 0 || mips_isa_rev () < min_rev) | |
2063 | && (warned_isa & ase->flags) != ase->flags) | |
2064 | { | |
2065 | warned_isa |= ase->flags; | |
2066 | base = mips_opts.micromips ? "microMIPS" : "MIPS"; | |
2067 | size = ISA_HAS_64BIT_REGS (mips_opts.isa) ? 64 : 32; | |
2068 | if (min_rev < 0) | |
1661c76c | 2069 | as_warn (_("the %d-bit %s architecture does not support the" |
c6278170 RS |
2070 | " `%s' extension"), size, base, ase->name); |
2071 | else | |
1661c76c | 2072 | as_warn (_("the `%s' extension requires %s%d revision %d or greater"), |
c6278170 RS |
2073 | ase->name, base, size, min_rev); |
2074 | } | |
7361da2c AB |
2075 | else if ((ase->rem_rev > 0 && mips_isa_rev () >= ase->rem_rev) |
2076 | && (warned_isa & ase->flags) != ase->flags) | |
2077 | { | |
2078 | warned_isa |= ase->flags; | |
2079 | base = mips_opts.micromips ? "microMIPS" : "MIPS"; | |
2080 | size = ISA_HAS_64BIT_REGS (mips_opts.isa) ? 64 : 32; | |
2081 | as_warn (_("the `%s' extension was removed in %s%d revision %d"), | |
2082 | ase->name, base, size, ase->rem_rev); | |
2083 | } | |
2084 | ||
c6278170 | 2085 | if ((ase->flags & FP64_ASES) |
0b35dfee | 2086 | && mips_opts.fp != 64 |
c6278170 RS |
2087 | && (warned_fp32 & ase->flags) != ase->flags) |
2088 | { | |
2089 | warned_fp32 |= ase->flags; | |
1661c76c | 2090 | as_warn (_("the `%s' extension requires 64-bit FPRs"), ase->name); |
c6278170 RS |
2091 | } |
2092 | } | |
2093 | ||
2094 | /* Check all enabled ASEs to see whether they are supported by the | |
2095 | chosen architecture. */ | |
2096 | ||
2097 | static void | |
2098 | mips_check_isa_supports_ases (void) | |
2099 | { | |
2100 | unsigned int i, mask; | |
2101 | ||
2102 | for (i = 0; i < ARRAY_SIZE (mips_ases); i++) | |
2103 | { | |
2104 | mask = mips_ase_mask (mips_ases[i].flags); | |
2105 | if ((mips_opts.ase & mask) == mips_ases[i].flags) | |
2106 | mips_check_isa_supports_ase (&mips_ases[i]); | |
2107 | } | |
2108 | } | |
2109 | ||
2110 | /* Set the state of ASE to ENABLED_P. Return the mask of ASE_* flags | |
2111 | that were affected. */ | |
2112 | ||
2113 | static unsigned int | |
919731af | 2114 | mips_set_ase (const struct mips_ase *ase, struct mips_set_options *opts, |
2115 | bfd_boolean enabled_p) | |
c6278170 RS |
2116 | { |
2117 | unsigned int mask; | |
2118 | ||
2119 | mask = mips_ase_mask (ase->flags); | |
919731af | 2120 | opts->ase &= ~mask; |
c6278170 | 2121 | if (enabled_p) |
919731af | 2122 | opts->ase |= ase->flags; |
c6278170 RS |
2123 | return mask; |
2124 | } | |
2125 | ||
2126 | /* Return the ASE called NAME, or null if none. */ | |
2127 | ||
2128 | static const struct mips_ase * | |
2129 | mips_lookup_ase (const char *name) | |
2130 | { | |
2131 | unsigned int i; | |
2132 | ||
2133 | for (i = 0; i < ARRAY_SIZE (mips_ases); i++) | |
2134 | if (strcmp (name, mips_ases[i].name) == 0) | |
2135 | return &mips_ases[i]; | |
2136 | return NULL; | |
2137 | } | |
2138 | ||
df58fc94 | 2139 | /* Return the length of a microMIPS instruction in bytes. If bits of |
100b4f2e MR |
2140 | the mask beyond the low 16 are 0, then it is a 16-bit instruction, |
2141 | otherwise it is a 32-bit instruction. */ | |
df58fc94 RS |
2142 | |
2143 | static inline unsigned int | |
2144 | micromips_insn_length (const struct mips_opcode *mo) | |
2145 | { | |
7fd53920 | 2146 | return mips_opcode_32bit_p (mo) ? 4 : 2; |
df58fc94 RS |
2147 | } |
2148 | ||
5c04167a RS |
2149 | /* Return the length of MIPS16 instruction OPCODE. */ |
2150 | ||
2151 | static inline unsigned int | |
2152 | mips16_opcode_length (unsigned long opcode) | |
2153 | { | |
2154 | return (opcode >> 16) == 0 ? 2 : 4; | |
2155 | } | |
2156 | ||
1e915849 RS |
2157 | /* Return the length of instruction INSN. */ |
2158 | ||
2159 | static inline unsigned int | |
2160 | insn_length (const struct mips_cl_insn *insn) | |
2161 | { | |
df58fc94 RS |
2162 | if (mips_opts.micromips) |
2163 | return micromips_insn_length (insn->insn_mo); | |
2164 | else if (mips_opts.mips16) | |
5c04167a | 2165 | return mips16_opcode_length (insn->insn_opcode); |
df58fc94 | 2166 | else |
1e915849 | 2167 | return 4; |
1e915849 RS |
2168 | } |
2169 | ||
2170 | /* Initialise INSN from opcode entry MO. Leave its position unspecified. */ | |
2171 | ||
2172 | static void | |
2173 | create_insn (struct mips_cl_insn *insn, const struct mips_opcode *mo) | |
2174 | { | |
2175 | size_t i; | |
2176 | ||
2177 | insn->insn_mo = mo; | |
1e915849 RS |
2178 | insn->insn_opcode = mo->match; |
2179 | insn->frag = NULL; | |
2180 | insn->where = 0; | |
2181 | for (i = 0; i < ARRAY_SIZE (insn->fixp); i++) | |
2182 | insn->fixp[i] = NULL; | |
2183 | insn->fixed_p = (mips_opts.noreorder > 0); | |
2184 | insn->noreorder_p = (mips_opts.noreorder > 0); | |
2185 | insn->mips16_absolute_jump_p = 0; | |
15be625d | 2186 | insn->complete_p = 0; |
e407c74b | 2187 | insn->cleared_p = 0; |
1e915849 RS |
2188 | } |
2189 | ||
fc76e730 RS |
2190 | /* Get a list of all the operands in INSN. */ |
2191 | ||
2192 | static const struct mips_operand_array * | |
2193 | insn_operands (const struct mips_cl_insn *insn) | |
2194 | { | |
2195 | if (insn->insn_mo >= &mips_opcodes[0] | |
2196 | && insn->insn_mo < &mips_opcodes[NUMOPCODES]) | |
2197 | return &mips_operands[insn->insn_mo - &mips_opcodes[0]]; | |
2198 | ||
2199 | if (insn->insn_mo >= &mips16_opcodes[0] | |
2200 | && insn->insn_mo < &mips16_opcodes[bfd_mips16_num_opcodes]) | |
2201 | return &mips16_operands[insn->insn_mo - &mips16_opcodes[0]]; | |
2202 | ||
2203 | if (insn->insn_mo >= µmips_opcodes[0] | |
2204 | && insn->insn_mo < µmips_opcodes[bfd_micromips_num_opcodes]) | |
2205 | return µmips_operands[insn->insn_mo - µmips_opcodes[0]]; | |
2206 | ||
2207 | abort (); | |
2208 | } | |
2209 | ||
2210 | /* Get a description of operand OPNO of INSN. */ | |
2211 | ||
2212 | static const struct mips_operand * | |
2213 | insn_opno (const struct mips_cl_insn *insn, unsigned opno) | |
2214 | { | |
2215 | const struct mips_operand_array *operands; | |
2216 | ||
2217 | operands = insn_operands (insn); | |
2218 | if (opno >= MAX_OPERANDS || !operands->operand[opno]) | |
2219 | abort (); | |
2220 | return operands->operand[opno]; | |
2221 | } | |
2222 | ||
e077a1c8 RS |
2223 | /* Install UVAL as the value of OPERAND in INSN. */ |
2224 | ||
2225 | static inline void | |
2226 | insn_insert_operand (struct mips_cl_insn *insn, | |
2227 | const struct mips_operand *operand, unsigned int uval) | |
2228 | { | |
2229 | insn->insn_opcode = mips_insert_operand (operand, insn->insn_opcode, uval); | |
2230 | } | |
2231 | ||
fc76e730 RS |
2232 | /* Extract the value of OPERAND from INSN. */ |
2233 | ||
2234 | static inline unsigned | |
2235 | insn_extract_operand (const struct mips_cl_insn *insn, | |
2236 | const struct mips_operand *operand) | |
2237 | { | |
2238 | return mips_extract_operand (operand, insn->insn_opcode); | |
2239 | } | |
2240 | ||
df58fc94 | 2241 | /* Record the current MIPS16/microMIPS mode in now_seg. */ |
742a56fe RS |
2242 | |
2243 | static void | |
df58fc94 | 2244 | mips_record_compressed_mode (void) |
742a56fe RS |
2245 | { |
2246 | segment_info_type *si; | |
2247 | ||
2248 | si = seg_info (now_seg); | |
2249 | if (si->tc_segment_info_data.mips16 != mips_opts.mips16) | |
2250 | si->tc_segment_info_data.mips16 = mips_opts.mips16; | |
df58fc94 RS |
2251 | if (si->tc_segment_info_data.micromips != mips_opts.micromips) |
2252 | si->tc_segment_info_data.micromips = mips_opts.micromips; | |
742a56fe RS |
2253 | } |
2254 | ||
4d68580a RS |
2255 | /* Read a standard MIPS instruction from BUF. */ |
2256 | ||
2257 | static unsigned long | |
2258 | read_insn (char *buf) | |
2259 | { | |
2260 | if (target_big_endian) | |
2261 | return bfd_getb32 ((bfd_byte *) buf); | |
2262 | else | |
2263 | return bfd_getl32 ((bfd_byte *) buf); | |
2264 | } | |
2265 | ||
2266 | /* Write standard MIPS instruction INSN to BUF. Return a pointer to | |
2267 | the next byte. */ | |
2268 | ||
2269 | static char * | |
2270 | write_insn (char *buf, unsigned int insn) | |
2271 | { | |
2272 | md_number_to_chars (buf, insn, 4); | |
2273 | return buf + 4; | |
2274 | } | |
2275 | ||
2276 | /* Read a microMIPS or MIPS16 opcode from BUF, given that it | |
2277 | has length LENGTH. */ | |
2278 | ||
2279 | static unsigned long | |
2280 | read_compressed_insn (char *buf, unsigned int length) | |
2281 | { | |
2282 | unsigned long insn; | |
2283 | unsigned int i; | |
2284 | ||
2285 | insn = 0; | |
2286 | for (i = 0; i < length; i += 2) | |
2287 | { | |
2288 | insn <<= 16; | |
2289 | if (target_big_endian) | |
2290 | insn |= bfd_getb16 ((char *) buf); | |
2291 | else | |
2292 | insn |= bfd_getl16 ((char *) buf); | |
2293 | buf += 2; | |
2294 | } | |
2295 | return insn; | |
2296 | } | |
2297 | ||
5c04167a RS |
2298 | /* Write microMIPS or MIPS16 instruction INSN to BUF, given that the |
2299 | instruction is LENGTH bytes long. Return a pointer to the next byte. */ | |
2300 | ||
2301 | static char * | |
2302 | write_compressed_insn (char *buf, unsigned int insn, unsigned int length) | |
2303 | { | |
2304 | unsigned int i; | |
2305 | ||
2306 | for (i = 0; i < length; i += 2) | |
2307 | md_number_to_chars (buf + i, insn >> ((length - i - 2) * 8), 2); | |
2308 | return buf + length; | |
2309 | } | |
2310 | ||
1e915849 RS |
2311 | /* Install INSN at the location specified by its "frag" and "where" fields. */ |
2312 | ||
2313 | static void | |
2314 | install_insn (const struct mips_cl_insn *insn) | |
2315 | { | |
2316 | char *f = insn->frag->fr_literal + insn->where; | |
5c04167a RS |
2317 | if (HAVE_CODE_COMPRESSION) |
2318 | write_compressed_insn (f, insn->insn_opcode, insn_length (insn)); | |
1e915849 | 2319 | else |
4d68580a | 2320 | write_insn (f, insn->insn_opcode); |
df58fc94 | 2321 | mips_record_compressed_mode (); |
1e915849 RS |
2322 | } |
2323 | ||
2324 | /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly | |
2325 | and install the opcode in the new location. */ | |
2326 | ||
2327 | static void | |
2328 | move_insn (struct mips_cl_insn *insn, fragS *frag, long where) | |
2329 | { | |
2330 | size_t i; | |
2331 | ||
2332 | insn->frag = frag; | |
2333 | insn->where = where; | |
2334 | for (i = 0; i < ARRAY_SIZE (insn->fixp); i++) | |
2335 | if (insn->fixp[i] != NULL) | |
2336 | { | |
2337 | insn->fixp[i]->fx_frag = frag; | |
2338 | insn->fixp[i]->fx_where = where; | |
2339 | } | |
2340 | install_insn (insn); | |
2341 | } | |
2342 | ||
2343 | /* Add INSN to the end of the output. */ | |
2344 | ||
2345 | static void | |
2346 | add_fixed_insn (struct mips_cl_insn *insn) | |
2347 | { | |
2348 | char *f = frag_more (insn_length (insn)); | |
2349 | move_insn (insn, frag_now, f - frag_now->fr_literal); | |
2350 | } | |
2351 | ||
2352 | /* Start a variant frag and move INSN to the start of the variant part, | |
2353 | marking it as fixed. The other arguments are as for frag_var. */ | |
2354 | ||
2355 | static void | |
2356 | add_relaxed_insn (struct mips_cl_insn *insn, int max_chars, int var, | |
2357 | relax_substateT subtype, symbolS *symbol, offsetT offset) | |
2358 | { | |
2359 | frag_grow (max_chars); | |
2360 | move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal); | |
2361 | insn->fixed_p = 1; | |
2362 | frag_var (rs_machine_dependent, max_chars, var, | |
2363 | subtype, symbol, offset, NULL); | |
2364 | } | |
2365 | ||
2366 | /* Insert N copies of INSN into the history buffer, starting at | |
2367 | position FIRST. Neither FIRST nor N need to be clipped. */ | |
2368 | ||
2369 | static void | |
2370 | insert_into_history (unsigned int first, unsigned int n, | |
2371 | const struct mips_cl_insn *insn) | |
2372 | { | |
2373 | if (mips_relax.sequence != 2) | |
2374 | { | |
2375 | unsigned int i; | |
2376 | ||
2377 | for (i = ARRAY_SIZE (history); i-- > first;) | |
2378 | if (i >= first + n) | |
2379 | history[i] = history[i - n]; | |
2380 | else | |
2381 | history[i] = *insn; | |
2382 | } | |
2383 | } | |
2384 | ||
e3de51ce RS |
2385 | /* Clear the error in insn_error. */ |
2386 | ||
2387 | static void | |
2388 | clear_insn_error (void) | |
2389 | { | |
2390 | memset (&insn_error, 0, sizeof (insn_error)); | |
2391 | } | |
2392 | ||
2393 | /* Possibly record error message MSG for the current instruction. | |
2394 | If the error is about a particular argument, ARGNUM is the 1-based | |
2395 | number of that argument, otherwise it is 0. FORMAT is the format | |
2396 | of MSG. Return true if MSG was used, false if the current message | |
2397 | was kept. */ | |
2398 | ||
2399 | static bfd_boolean | |
2400 | set_insn_error_format (int argnum, enum mips_insn_error_format format, | |
2401 | const char *msg) | |
2402 | { | |
2403 | if (argnum == 0) | |
2404 | { | |
2405 | /* Give priority to errors against specific arguments, and to | |
2406 | the first whole-instruction message. */ | |
2407 | if (insn_error.msg) | |
2408 | return FALSE; | |
2409 | } | |
2410 | else | |
2411 | { | |
2412 | /* Keep insn_error if it is against a later argument. */ | |
2413 | if (argnum < insn_error.min_argnum) | |
2414 | return FALSE; | |
2415 | ||
2416 | /* If both errors are against the same argument but are different, | |
2417 | give up on reporting a specific error for this argument. | |
2418 | See the comment about mips_insn_error for details. */ | |
2419 | if (argnum == insn_error.min_argnum | |
2420 | && insn_error.msg | |
2421 | && strcmp (insn_error.msg, msg) != 0) | |
2422 | { | |
2423 | insn_error.msg = 0; | |
2424 | insn_error.min_argnum += 1; | |
2425 | return FALSE; | |
2426 | } | |
2427 | } | |
2428 | insn_error.min_argnum = argnum; | |
2429 | insn_error.format = format; | |
2430 | insn_error.msg = msg; | |
2431 | return TRUE; | |
2432 | } | |
2433 | ||
2434 | /* Record an instruction error with no % format fields. ARGNUM and MSG are | |
2435 | as for set_insn_error_format. */ | |
2436 | ||
2437 | static void | |
2438 | set_insn_error (int argnum, const char *msg) | |
2439 | { | |
2440 | set_insn_error_format (argnum, ERR_FMT_PLAIN, msg); | |
2441 | } | |
2442 | ||
2443 | /* Record an instruction error with one %d field I. ARGNUM and MSG are | |
2444 | as for set_insn_error_format. */ | |
2445 | ||
2446 | static void | |
2447 | set_insn_error_i (int argnum, const char *msg, int i) | |
2448 | { | |
2449 | if (set_insn_error_format (argnum, ERR_FMT_I, msg)) | |
2450 | insn_error.u.i = i; | |
2451 | } | |
2452 | ||
2453 | /* Record an instruction error with two %s fields S1 and S2. ARGNUM and MSG | |
2454 | are as for set_insn_error_format. */ | |
2455 | ||
2456 | static void | |
2457 | set_insn_error_ss (int argnum, const char *msg, const char *s1, const char *s2) | |
2458 | { | |
2459 | if (set_insn_error_format (argnum, ERR_FMT_SS, msg)) | |
2460 | { | |
2461 | insn_error.u.ss[0] = s1; | |
2462 | insn_error.u.ss[1] = s2; | |
2463 | } | |
2464 | } | |
2465 | ||
2466 | /* Report the error in insn_error, which is against assembly code STR. */ | |
2467 | ||
2468 | static void | |
2469 | report_insn_error (const char *str) | |
2470 | { | |
e1fa0163 | 2471 | const char *msg = concat (insn_error.msg, " `%s'", NULL); |
e3de51ce | 2472 | |
e3de51ce RS |
2473 | switch (insn_error.format) |
2474 | { | |
2475 | case ERR_FMT_PLAIN: | |
2476 | as_bad (msg, str); | |
2477 | break; | |
2478 | ||
2479 | case ERR_FMT_I: | |
2480 | as_bad (msg, insn_error.u.i, str); | |
2481 | break; | |
2482 | ||
2483 | case ERR_FMT_SS: | |
2484 | as_bad (msg, insn_error.u.ss[0], insn_error.u.ss[1], str); | |
2485 | break; | |
2486 | } | |
e1fa0163 NC |
2487 | |
2488 | free ((char *) msg); | |
e3de51ce RS |
2489 | } |
2490 | ||
71400594 RS |
2491 | /* Initialize vr4120_conflicts. There is a bit of duplication here: |
2492 | the idea is to make it obvious at a glance that each errata is | |
2493 | included. */ | |
2494 | ||
2495 | static void | |
2496 | init_vr4120_conflicts (void) | |
2497 | { | |
2498 | #define CONFLICT(FIRST, SECOND) \ | |
2499 | vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND | |
2500 | ||
2501 | /* Errata 21 - [D]DIV[U] after [D]MACC */ | |
2502 | CONFLICT (MACC, DIV); | |
2503 | CONFLICT (DMACC, DIV); | |
2504 | ||
2505 | /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */ | |
2506 | CONFLICT (DMULT, DMULT); | |
2507 | CONFLICT (DMULT, DMACC); | |
2508 | CONFLICT (DMACC, DMULT); | |
2509 | CONFLICT (DMACC, DMACC); | |
2510 | ||
2511 | /* Errata 24 - MT{LO,HI} after [D]MACC */ | |
2512 | CONFLICT (MACC, MTHILO); | |
2513 | CONFLICT (DMACC, MTHILO); | |
2514 | ||
2515 | /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU | |
2516 | instruction is executed immediately after a MACC or DMACC | |
2517 | instruction, the result of [either instruction] is incorrect." */ | |
2518 | CONFLICT (MACC, MULT); | |
2519 | CONFLICT (MACC, DMULT); | |
2520 | CONFLICT (DMACC, MULT); | |
2521 | CONFLICT (DMACC, DMULT); | |
2522 | ||
2523 | /* VR4181A errata MD(4): "If a MACC or DMACC instruction is | |
2524 | executed immediately after a DMULT, DMULTU, DIV, DIVU, | |
2525 | DDIV or DDIVU instruction, the result of the MACC or | |
2526 | DMACC instruction is incorrect.". */ | |
2527 | CONFLICT (DMULT, MACC); | |
2528 | CONFLICT (DMULT, DMACC); | |
2529 | CONFLICT (DIV, MACC); | |
2530 | CONFLICT (DIV, DMACC); | |
2531 | ||
2532 | #undef CONFLICT | |
2533 | } | |
2534 | ||
707bfff6 TS |
2535 | struct regname { |
2536 | const char *name; | |
2537 | unsigned int num; | |
2538 | }; | |
2539 | ||
14daeee3 | 2540 | #define RNUM_MASK 0x00000ff |
56d438b1 | 2541 | #define RTYPE_MASK 0x0ffff00 |
14daeee3 RS |
2542 | #define RTYPE_NUM 0x0000100 |
2543 | #define RTYPE_FPU 0x0000200 | |
2544 | #define RTYPE_FCC 0x0000400 | |
2545 | #define RTYPE_VEC 0x0000800 | |
2546 | #define RTYPE_GP 0x0001000 | |
2547 | #define RTYPE_CP0 0x0002000 | |
2548 | #define RTYPE_PC 0x0004000 | |
2549 | #define RTYPE_ACC 0x0008000 | |
2550 | #define RTYPE_CCC 0x0010000 | |
2551 | #define RTYPE_VI 0x0020000 | |
2552 | #define RTYPE_VF 0x0040000 | |
2553 | #define RTYPE_R5900_I 0x0080000 | |
2554 | #define RTYPE_R5900_Q 0x0100000 | |
2555 | #define RTYPE_R5900_R 0x0200000 | |
2556 | #define RTYPE_R5900_ACC 0x0400000 | |
56d438b1 | 2557 | #define RTYPE_MSA 0x0800000 |
14daeee3 | 2558 | #define RWARN 0x8000000 |
707bfff6 TS |
2559 | |
2560 | #define GENERIC_REGISTER_NUMBERS \ | |
2561 | {"$0", RTYPE_NUM | 0}, \ | |
2562 | {"$1", RTYPE_NUM | 1}, \ | |
2563 | {"$2", RTYPE_NUM | 2}, \ | |
2564 | {"$3", RTYPE_NUM | 3}, \ | |
2565 | {"$4", RTYPE_NUM | 4}, \ | |
2566 | {"$5", RTYPE_NUM | 5}, \ | |
2567 | {"$6", RTYPE_NUM | 6}, \ | |
2568 | {"$7", RTYPE_NUM | 7}, \ | |
2569 | {"$8", RTYPE_NUM | 8}, \ | |
2570 | {"$9", RTYPE_NUM | 9}, \ | |
2571 | {"$10", RTYPE_NUM | 10}, \ | |
2572 | {"$11", RTYPE_NUM | 11}, \ | |
2573 | {"$12", RTYPE_NUM | 12}, \ | |
2574 | {"$13", RTYPE_NUM | 13}, \ | |
2575 | {"$14", RTYPE_NUM | 14}, \ | |
2576 | {"$15", RTYPE_NUM | 15}, \ | |
2577 | {"$16", RTYPE_NUM | 16}, \ | |
2578 | {"$17", RTYPE_NUM | 17}, \ | |
2579 | {"$18", RTYPE_NUM | 18}, \ | |
2580 | {"$19", RTYPE_NUM | 19}, \ | |
2581 | {"$20", RTYPE_NUM | 20}, \ | |
2582 | {"$21", RTYPE_NUM | 21}, \ | |
2583 | {"$22", RTYPE_NUM | 22}, \ | |
2584 | {"$23", RTYPE_NUM | 23}, \ | |
2585 | {"$24", RTYPE_NUM | 24}, \ | |
2586 | {"$25", RTYPE_NUM | 25}, \ | |
2587 | {"$26", RTYPE_NUM | 26}, \ | |
2588 | {"$27", RTYPE_NUM | 27}, \ | |
2589 | {"$28", RTYPE_NUM | 28}, \ | |
2590 | {"$29", RTYPE_NUM | 29}, \ | |
2591 | {"$30", RTYPE_NUM | 30}, \ | |
3739860c | 2592 | {"$31", RTYPE_NUM | 31} |
707bfff6 TS |
2593 | |
2594 | #define FPU_REGISTER_NAMES \ | |
2595 | {"$f0", RTYPE_FPU | 0}, \ | |
2596 | {"$f1", RTYPE_FPU | 1}, \ | |
2597 | {"$f2", RTYPE_FPU | 2}, \ | |
2598 | {"$f3", RTYPE_FPU | 3}, \ | |
2599 | {"$f4", RTYPE_FPU | 4}, \ | |
2600 | {"$f5", RTYPE_FPU | 5}, \ | |
2601 | {"$f6", RTYPE_FPU | 6}, \ | |
2602 | {"$f7", RTYPE_FPU | 7}, \ | |
2603 | {"$f8", RTYPE_FPU | 8}, \ | |
2604 | {"$f9", RTYPE_FPU | 9}, \ | |
2605 | {"$f10", RTYPE_FPU | 10}, \ | |
2606 | {"$f11", RTYPE_FPU | 11}, \ | |
2607 | {"$f12", RTYPE_FPU | 12}, \ | |
2608 | {"$f13", RTYPE_FPU | 13}, \ | |
2609 | {"$f14", RTYPE_FPU | 14}, \ | |
2610 | {"$f15", RTYPE_FPU | 15}, \ | |
2611 | {"$f16", RTYPE_FPU | 16}, \ | |
2612 | {"$f17", RTYPE_FPU | 17}, \ | |
2613 | {"$f18", RTYPE_FPU | 18}, \ | |
2614 | {"$f19", RTYPE_FPU | 19}, \ | |
2615 | {"$f20", RTYPE_FPU | 20}, \ | |
2616 | {"$f21", RTYPE_FPU | 21}, \ | |
2617 | {"$f22", RTYPE_FPU | 22}, \ | |
2618 | {"$f23", RTYPE_FPU | 23}, \ | |
2619 | {"$f24", RTYPE_FPU | 24}, \ | |
2620 | {"$f25", RTYPE_FPU | 25}, \ | |
2621 | {"$f26", RTYPE_FPU | 26}, \ | |
2622 | {"$f27", RTYPE_FPU | 27}, \ | |
2623 | {"$f28", RTYPE_FPU | 28}, \ | |
2624 | {"$f29", RTYPE_FPU | 29}, \ | |
2625 | {"$f30", RTYPE_FPU | 30}, \ | |
2626 | {"$f31", RTYPE_FPU | 31} | |
2627 | ||
2628 | #define FPU_CONDITION_CODE_NAMES \ | |
2629 | {"$fcc0", RTYPE_FCC | 0}, \ | |
2630 | {"$fcc1", RTYPE_FCC | 1}, \ | |
2631 | {"$fcc2", RTYPE_FCC | 2}, \ | |
2632 | {"$fcc3", RTYPE_FCC | 3}, \ | |
2633 | {"$fcc4", RTYPE_FCC | 4}, \ | |
2634 | {"$fcc5", RTYPE_FCC | 5}, \ | |
2635 | {"$fcc6", RTYPE_FCC | 6}, \ | |
2636 | {"$fcc7", RTYPE_FCC | 7} | |
2637 | ||
2638 | #define COPROC_CONDITION_CODE_NAMES \ | |
2639 | {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \ | |
2640 | {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \ | |
2641 | {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \ | |
2642 | {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \ | |
2643 | {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \ | |
2644 | {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \ | |
2645 | {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \ | |
2646 | {"$cc7", RTYPE_FCC | RTYPE_CCC | 7} | |
2647 | ||
2648 | #define N32N64_SYMBOLIC_REGISTER_NAMES \ | |
2649 | {"$a4", RTYPE_GP | 8}, \ | |
2650 | {"$a5", RTYPE_GP | 9}, \ | |
2651 | {"$a6", RTYPE_GP | 10}, \ | |
2652 | {"$a7", RTYPE_GP | 11}, \ | |
2653 | {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \ | |
2654 | {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \ | |
2655 | {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \ | |
2656 | {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \ | |
2657 | {"$t0", RTYPE_GP | 12}, \ | |
2658 | {"$t1", RTYPE_GP | 13}, \ | |
2659 | {"$t2", RTYPE_GP | 14}, \ | |
2660 | {"$t3", RTYPE_GP | 15} | |
2661 | ||
2662 | #define O32_SYMBOLIC_REGISTER_NAMES \ | |
2663 | {"$t0", RTYPE_GP | 8}, \ | |
2664 | {"$t1", RTYPE_GP | 9}, \ | |
2665 | {"$t2", RTYPE_GP | 10}, \ | |
2666 | {"$t3", RTYPE_GP | 11}, \ | |
2667 | {"$t4", RTYPE_GP | 12}, \ | |
2668 | {"$t5", RTYPE_GP | 13}, \ | |
2669 | {"$t6", RTYPE_GP | 14}, \ | |
2670 | {"$t7", RTYPE_GP | 15}, \ | |
2671 | {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \ | |
2672 | {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \ | |
2673 | {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \ | |
3739860c | 2674 | {"$ta3", RTYPE_GP | 15} /* alias for $t7 */ |
707bfff6 TS |
2675 | |
2676 | /* Remaining symbolic register names */ | |
2677 | #define SYMBOLIC_REGISTER_NAMES \ | |
2678 | {"$zero", RTYPE_GP | 0}, \ | |
2679 | {"$at", RTYPE_GP | 1}, \ | |
2680 | {"$AT", RTYPE_GP | 1}, \ | |
2681 | {"$v0", RTYPE_GP | 2}, \ | |
2682 | {"$v1", RTYPE_GP | 3}, \ | |
2683 | {"$a0", RTYPE_GP | 4}, \ | |
2684 | {"$a1", RTYPE_GP | 5}, \ | |
2685 | {"$a2", RTYPE_GP | 6}, \ | |
2686 | {"$a3", RTYPE_GP | 7}, \ | |
2687 | {"$s0", RTYPE_GP | 16}, \ | |
2688 | {"$s1", RTYPE_GP | 17}, \ | |
2689 | {"$s2", RTYPE_GP | 18}, \ | |
2690 | {"$s3", RTYPE_GP | 19}, \ | |
2691 | {"$s4", RTYPE_GP | 20}, \ | |
2692 | {"$s5", RTYPE_GP | 21}, \ | |
2693 | {"$s6", RTYPE_GP | 22}, \ | |
2694 | {"$s7", RTYPE_GP | 23}, \ | |
2695 | {"$t8", RTYPE_GP | 24}, \ | |
2696 | {"$t9", RTYPE_GP | 25}, \ | |
2697 | {"$k0", RTYPE_GP | 26}, \ | |
2698 | {"$kt0", RTYPE_GP | 26}, \ | |
2699 | {"$k1", RTYPE_GP | 27}, \ | |
2700 | {"$kt1", RTYPE_GP | 27}, \ | |
2701 | {"$gp", RTYPE_GP | 28}, \ | |
2702 | {"$sp", RTYPE_GP | 29}, \ | |
2703 | {"$s8", RTYPE_GP | 30}, \ | |
2704 | {"$fp", RTYPE_GP | 30}, \ | |
2705 | {"$ra", RTYPE_GP | 31} | |
2706 | ||
2707 | #define MIPS16_SPECIAL_REGISTER_NAMES \ | |
2708 | {"$pc", RTYPE_PC | 0} | |
2709 | ||
2710 | #define MDMX_VECTOR_REGISTER_NAMES \ | |
2711 | /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \ | |
2712 | /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \ | |
2713 | {"$v2", RTYPE_VEC | 2}, \ | |
2714 | {"$v3", RTYPE_VEC | 3}, \ | |
2715 | {"$v4", RTYPE_VEC | 4}, \ | |
2716 | {"$v5", RTYPE_VEC | 5}, \ | |
2717 | {"$v6", RTYPE_VEC | 6}, \ | |
2718 | {"$v7", RTYPE_VEC | 7}, \ | |
2719 | {"$v8", RTYPE_VEC | 8}, \ | |
2720 | {"$v9", RTYPE_VEC | 9}, \ | |
2721 | {"$v10", RTYPE_VEC | 10}, \ | |
2722 | {"$v11", RTYPE_VEC | 11}, \ | |
2723 | {"$v12", RTYPE_VEC | 12}, \ | |
2724 | {"$v13", RTYPE_VEC | 13}, \ | |
2725 | {"$v14", RTYPE_VEC | 14}, \ | |
2726 | {"$v15", RTYPE_VEC | 15}, \ | |
2727 | {"$v16", RTYPE_VEC | 16}, \ | |
2728 | {"$v17", RTYPE_VEC | 17}, \ | |
2729 | {"$v18", RTYPE_VEC | 18}, \ | |
2730 | {"$v19", RTYPE_VEC | 19}, \ | |
2731 | {"$v20", RTYPE_VEC | 20}, \ | |
2732 | {"$v21", RTYPE_VEC | 21}, \ | |
2733 | {"$v22", RTYPE_VEC | 22}, \ | |
2734 | {"$v23", RTYPE_VEC | 23}, \ | |
2735 | {"$v24", RTYPE_VEC | 24}, \ | |
2736 | {"$v25", RTYPE_VEC | 25}, \ | |
2737 | {"$v26", RTYPE_VEC | 26}, \ | |
2738 | {"$v27", RTYPE_VEC | 27}, \ | |
2739 | {"$v28", RTYPE_VEC | 28}, \ | |
2740 | {"$v29", RTYPE_VEC | 29}, \ | |
2741 | {"$v30", RTYPE_VEC | 30}, \ | |
2742 | {"$v31", RTYPE_VEC | 31} | |
2743 | ||
14daeee3 RS |
2744 | #define R5900_I_NAMES \ |
2745 | {"$I", RTYPE_R5900_I | 0} | |
2746 | ||
2747 | #define R5900_Q_NAMES \ | |
2748 | {"$Q", RTYPE_R5900_Q | 0} | |
2749 | ||
2750 | #define R5900_R_NAMES \ | |
2751 | {"$R", RTYPE_R5900_R | 0} | |
2752 | ||
2753 | #define R5900_ACC_NAMES \ | |
2754 | {"$ACC", RTYPE_R5900_ACC | 0 } | |
2755 | ||
707bfff6 TS |
2756 | #define MIPS_DSP_ACCUMULATOR_NAMES \ |
2757 | {"$ac0", RTYPE_ACC | 0}, \ | |
2758 | {"$ac1", RTYPE_ACC | 1}, \ | |
2759 | {"$ac2", RTYPE_ACC | 2}, \ | |
2760 | {"$ac3", RTYPE_ACC | 3} | |
2761 | ||
2762 | static const struct regname reg_names[] = { | |
2763 | GENERIC_REGISTER_NUMBERS, | |
2764 | FPU_REGISTER_NAMES, | |
2765 | FPU_CONDITION_CODE_NAMES, | |
2766 | COPROC_CONDITION_CODE_NAMES, | |
2767 | ||
2768 | /* The $txx registers depends on the abi, | |
2769 | these will be added later into the symbol table from | |
3739860c | 2770 | one of the tables below once mips_abi is set after |
707bfff6 TS |
2771 | parsing of arguments from the command line. */ |
2772 | SYMBOLIC_REGISTER_NAMES, | |
2773 | ||
2774 | MIPS16_SPECIAL_REGISTER_NAMES, | |
2775 | MDMX_VECTOR_REGISTER_NAMES, | |
14daeee3 RS |
2776 | R5900_I_NAMES, |
2777 | R5900_Q_NAMES, | |
2778 | R5900_R_NAMES, | |
2779 | R5900_ACC_NAMES, | |
707bfff6 TS |
2780 | MIPS_DSP_ACCUMULATOR_NAMES, |
2781 | {0, 0} | |
2782 | }; | |
2783 | ||
2784 | static const struct regname reg_names_o32[] = { | |
2785 | O32_SYMBOLIC_REGISTER_NAMES, | |
2786 | {0, 0} | |
2787 | }; | |
2788 | ||
2789 | static const struct regname reg_names_n32n64[] = { | |
2790 | N32N64_SYMBOLIC_REGISTER_NAMES, | |
2791 | {0, 0} | |
2792 | }; | |
2793 | ||
a92713e6 RS |
2794 | /* Register symbols $v0 and $v1 map to GPRs 2 and 3, but they can also be |
2795 | interpreted as vector registers 0 and 1. If SYMVAL is the value of one | |
2796 | of these register symbols, return the associated vector register, | |
2797 | otherwise return SYMVAL itself. */ | |
df58fc94 | 2798 | |
a92713e6 RS |
2799 | static unsigned int |
2800 | mips_prefer_vec_regno (unsigned int symval) | |
707bfff6 | 2801 | { |
a92713e6 RS |
2802 | if ((symval & -2) == (RTYPE_GP | 2)) |
2803 | return RTYPE_VEC | (symval & 1); | |
2804 | return symval; | |
2805 | } | |
2806 | ||
14daeee3 RS |
2807 | /* Return true if string [S, E) is a valid register name, storing its |
2808 | symbol value in *SYMVAL_PTR if so. */ | |
a92713e6 RS |
2809 | |
2810 | static bfd_boolean | |
14daeee3 | 2811 | mips_parse_register_1 (char *s, char *e, unsigned int *symval_ptr) |
a92713e6 | 2812 | { |
707bfff6 | 2813 | char save_c; |
14daeee3 | 2814 | symbolS *symbol; |
707bfff6 TS |
2815 | |
2816 | /* Terminate name. */ | |
2817 | save_c = *e; | |
2818 | *e = '\0'; | |
2819 | ||
a92713e6 RS |
2820 | /* Look up the name. */ |
2821 | symbol = symbol_find (s); | |
2822 | *e = save_c; | |
2823 | ||
2824 | if (!symbol || S_GET_SEGMENT (symbol) != reg_section) | |
2825 | return FALSE; | |
2826 | ||
14daeee3 RS |
2827 | *symval_ptr = S_GET_VALUE (symbol); |
2828 | return TRUE; | |
2829 | } | |
2830 | ||
2831 | /* Return true if the string at *SPTR is a valid register name. Allow it | |
2832 | to have a VU0-style channel suffix of the form x?y?z?w? if CHANNELS_PTR | |
2833 | is nonnull. | |
2834 | ||
2835 | When returning true, move *SPTR past the register, store the | |
2836 | register's symbol value in *SYMVAL_PTR and the channel mask in | |
2837 | *CHANNELS_PTR (if nonnull). The symbol value includes the register | |
2838 | number (RNUM_MASK) and register type (RTYPE_MASK). The channel mask | |
2839 | is a 4-bit value of the form XYZW and is 0 if no suffix was given. */ | |
2840 | ||
2841 | static bfd_boolean | |
2842 | mips_parse_register (char **sptr, unsigned int *symval_ptr, | |
2843 | unsigned int *channels_ptr) | |
2844 | { | |
2845 | char *s, *e, *m; | |
2846 | const char *q; | |
2847 | unsigned int channels, symval, bit; | |
2848 | ||
2849 | /* Find end of name. */ | |
2850 | s = e = *sptr; | |
2851 | if (is_name_beginner (*e)) | |
2852 | ++e; | |
2853 | while (is_part_of_name (*e)) | |
2854 | ++e; | |
2855 | ||
2856 | channels = 0; | |
2857 | if (!mips_parse_register_1 (s, e, &symval)) | |
2858 | { | |
2859 | if (!channels_ptr) | |
2860 | return FALSE; | |
2861 | ||
2862 | /* Eat characters from the end of the string that are valid | |
2863 | channel suffixes. The preceding register must be $ACC or | |
2864 | end with a digit, so there is no ambiguity. */ | |
2865 | bit = 1; | |
2866 | m = e; | |
2867 | for (q = "wzyx"; *q; q++, bit <<= 1) | |
2868 | if (m > s && m[-1] == *q) | |
2869 | { | |
2870 | --m; | |
2871 | channels |= bit; | |
2872 | } | |
2873 | ||
2874 | if (channels == 0 | |
2875 | || !mips_parse_register_1 (s, m, &symval) | |
2876 | || (symval & (RTYPE_VI | RTYPE_VF | RTYPE_R5900_ACC)) == 0) | |
2877 | return FALSE; | |
2878 | } | |
2879 | ||
a92713e6 | 2880 | *sptr = e; |
14daeee3 RS |
2881 | *symval_ptr = symval; |
2882 | if (channels_ptr) | |
2883 | *channels_ptr = channels; | |
a92713e6 RS |
2884 | return TRUE; |
2885 | } | |
2886 | ||
2887 | /* Check if SPTR points at a valid register specifier according to TYPES. | |
2888 | If so, then return 1, advance S to consume the specifier and store | |
2889 | the register's number in REGNOP, otherwise return 0. */ | |
2890 | ||
2891 | static int | |
2892 | reg_lookup (char **s, unsigned int types, unsigned int *regnop) | |
2893 | { | |
2894 | unsigned int regno; | |
2895 | ||
14daeee3 | 2896 | if (mips_parse_register (s, ®no, NULL)) |
707bfff6 | 2897 | { |
a92713e6 RS |
2898 | if (types & RTYPE_VEC) |
2899 | regno = mips_prefer_vec_regno (regno); | |
2900 | if (regno & types) | |
2901 | regno &= RNUM_MASK; | |
2902 | else | |
2903 | regno = ~0; | |
707bfff6 | 2904 | } |
a92713e6 | 2905 | else |
707bfff6 | 2906 | { |
a92713e6 | 2907 | if (types & RWARN) |
1661c76c | 2908 | as_warn (_("unrecognized register name `%s'"), *s); |
a92713e6 | 2909 | regno = ~0; |
707bfff6 | 2910 | } |
707bfff6 | 2911 | if (regnop) |
a92713e6 RS |
2912 | *regnop = regno; |
2913 | return regno <= RNUM_MASK; | |
707bfff6 TS |
2914 | } |
2915 | ||
14daeee3 RS |
2916 | /* Parse a VU0 "x?y?z?w?" channel mask at S and store the associated |
2917 | mask in *CHANNELS. Return a pointer to the first unconsumed character. */ | |
2918 | ||
2919 | static char * | |
2920 | mips_parse_vu0_channels (char *s, unsigned int *channels) | |
2921 | { | |
2922 | unsigned int i; | |
2923 | ||
2924 | *channels = 0; | |
2925 | for (i = 0; i < 4; i++) | |
2926 | if (*s == "xyzw"[i]) | |
2927 | { | |
2928 | *channels |= 1 << (3 - i); | |
2929 | ++s; | |
2930 | } | |
2931 | return s; | |
2932 | } | |
2933 | ||
a92713e6 RS |
2934 | /* Token types for parsed operand lists. */ |
2935 | enum mips_operand_token_type { | |
2936 | /* A plain register, e.g. $f2. */ | |
2937 | OT_REG, | |
df58fc94 | 2938 | |
14daeee3 RS |
2939 | /* A 4-bit XYZW channel mask. */ |
2940 | OT_CHANNELS, | |
2941 | ||
56d438b1 CF |
2942 | /* A constant vector index, e.g. [1]. */ |
2943 | OT_INTEGER_INDEX, | |
2944 | ||
2945 | /* A register vector index, e.g. [$2]. */ | |
2946 | OT_REG_INDEX, | |
df58fc94 | 2947 | |
a92713e6 RS |
2948 | /* A continuous range of registers, e.g. $s0-$s4. */ |
2949 | OT_REG_RANGE, | |
2950 | ||
2951 | /* A (possibly relocated) expression. */ | |
2952 | OT_INTEGER, | |
2953 | ||
2954 | /* A floating-point value. */ | |
2955 | OT_FLOAT, | |
2956 | ||
2957 | /* A single character. This can be '(', ')' or ',', but '(' only appears | |
2958 | before OT_REGs. */ | |
2959 | OT_CHAR, | |
2960 | ||
14daeee3 RS |
2961 | /* A doubled character, either "--" or "++". */ |
2962 | OT_DOUBLE_CHAR, | |
2963 | ||
a92713e6 RS |
2964 | /* The end of the operand list. */ |
2965 | OT_END | |
2966 | }; | |
2967 | ||
2968 | /* A parsed operand token. */ | |
2969 | struct mips_operand_token | |
2970 | { | |
2971 | /* The type of token. */ | |
2972 | enum mips_operand_token_type type; | |
2973 | union | |
2974 | { | |
56d438b1 | 2975 | /* The register symbol value for an OT_REG or OT_REG_INDEX. */ |
a92713e6 RS |
2976 | unsigned int regno; |
2977 | ||
14daeee3 RS |
2978 | /* The 4-bit channel mask for an OT_CHANNEL_SUFFIX. */ |
2979 | unsigned int channels; | |
2980 | ||
56d438b1 CF |
2981 | /* The integer value of an OT_INTEGER_INDEX. */ |
2982 | addressT index; | |
a92713e6 RS |
2983 | |
2984 | /* The two register symbol values involved in an OT_REG_RANGE. */ | |
2985 | struct { | |
2986 | unsigned int regno1; | |
2987 | unsigned int regno2; | |
2988 | } reg_range; | |
2989 | ||
2990 | /* The value of an OT_INTEGER. The value is represented as an | |
2991 | expression and the relocation operators that were applied to | |
2992 | that expression. The reloc entries are BFD_RELOC_UNUSED if no | |
2993 | relocation operators were used. */ | |
2994 | struct { | |
2995 | expressionS value; | |
2996 | bfd_reloc_code_real_type relocs[3]; | |
2997 | } integer; | |
2998 | ||
2999 | /* The binary data for an OT_FLOAT constant, and the number of bytes | |
3000 | in the constant. */ | |
3001 | struct { | |
3002 | unsigned char data[8]; | |
3003 | int length; | |
3004 | } flt; | |
3005 | ||
14daeee3 | 3006 | /* The character represented by an OT_CHAR or OT_DOUBLE_CHAR. */ |
a92713e6 RS |
3007 | char ch; |
3008 | } u; | |
3009 | }; | |
3010 | ||
3011 | /* An obstack used to construct lists of mips_operand_tokens. */ | |
3012 | static struct obstack mips_operand_tokens; | |
3013 | ||
3014 | /* Give TOKEN type TYPE and add it to mips_operand_tokens. */ | |
3015 | ||
3016 | static void | |
3017 | mips_add_token (struct mips_operand_token *token, | |
3018 | enum mips_operand_token_type type) | |
3019 | { | |
3020 | token->type = type; | |
3021 | obstack_grow (&mips_operand_tokens, token, sizeof (*token)); | |
3022 | } | |
3023 | ||
3024 | /* Check whether S is '(' followed by a register name. Add OT_CHAR | |
3025 | and OT_REG tokens for them if so, and return a pointer to the first | |
3026 | unconsumed character. Return null otherwise. */ | |
3027 | ||
3028 | static char * | |
3029 | mips_parse_base_start (char *s) | |
3030 | { | |
3031 | struct mips_operand_token token; | |
14daeee3 RS |
3032 | unsigned int regno, channels; |
3033 | bfd_boolean decrement_p; | |
df58fc94 | 3034 | |
a92713e6 RS |
3035 | if (*s != '(') |
3036 | return 0; | |
3037 | ||
3038 | ++s; | |
3039 | SKIP_SPACE_TABS (s); | |
14daeee3 RS |
3040 | |
3041 | /* Only match "--" as part of a base expression. In other contexts "--X" | |
3042 | is a double negative. */ | |
3043 | decrement_p = (s[0] == '-' && s[1] == '-'); | |
3044 | if (decrement_p) | |
3045 | { | |
3046 | s += 2; | |
3047 | SKIP_SPACE_TABS (s); | |
3048 | } | |
3049 | ||
3050 | /* Allow a channel specifier because that leads to better error messages | |
3051 | than treating something like "$vf0x++" as an expression. */ | |
3052 | if (!mips_parse_register (&s, ®no, &channels)) | |
a92713e6 RS |
3053 | return 0; |
3054 | ||
3055 | token.u.ch = '('; | |
3056 | mips_add_token (&token, OT_CHAR); | |
3057 | ||
14daeee3 RS |
3058 | if (decrement_p) |
3059 | { | |
3060 | token.u.ch = '-'; | |
3061 | mips_add_token (&token, OT_DOUBLE_CHAR); | |
3062 | } | |
3063 | ||
a92713e6 RS |
3064 | token.u.regno = regno; |
3065 | mips_add_token (&token, OT_REG); | |
3066 | ||
14daeee3 RS |
3067 | if (channels) |
3068 | { | |
3069 | token.u.channels = channels; | |
3070 | mips_add_token (&token, OT_CHANNELS); | |
3071 | } | |
3072 | ||
3073 | /* For consistency, only match "++" as part of base expressions too. */ | |
3074 | SKIP_SPACE_TABS (s); | |
3075 | if (s[0] == '+' && s[1] == '+') | |
3076 | { | |
3077 | s += 2; | |
3078 | token.u.ch = '+'; | |
3079 | mips_add_token (&token, OT_DOUBLE_CHAR); | |
3080 | } | |
3081 | ||
a92713e6 RS |
3082 | return s; |
3083 | } | |
3084 | ||
3085 | /* Parse one or more tokens from S. Return a pointer to the first | |
3086 | unconsumed character on success. Return null if an error was found | |
3087 | and store the error text in insn_error. FLOAT_FORMAT is as for | |
3088 | mips_parse_arguments. */ | |
3089 | ||
3090 | static char * | |
3091 | mips_parse_argument_token (char *s, char float_format) | |
3092 | { | |
6d4af3c2 AM |
3093 | char *end, *save_in; |
3094 | const char *err; | |
14daeee3 | 3095 | unsigned int regno1, regno2, channels; |
a92713e6 RS |
3096 | struct mips_operand_token token; |
3097 | ||
3098 | /* First look for "($reg", since we want to treat that as an | |
3099 | OT_CHAR and OT_REG rather than an expression. */ | |
3100 | end = mips_parse_base_start (s); | |
3101 | if (end) | |
3102 | return end; | |
3103 | ||
3104 | /* Handle other characters that end up as OT_CHARs. */ | |
3105 | if (*s == ')' || *s == ',') | |
3106 | { | |
3107 | token.u.ch = *s; | |
3108 | mips_add_token (&token, OT_CHAR); | |
3109 | ++s; | |
3110 | return s; | |
3111 | } | |
3112 | ||
3113 | /* Handle tokens that start with a register. */ | |
14daeee3 | 3114 | if (mips_parse_register (&s, ®no1, &channels)) |
df58fc94 | 3115 | { |
14daeee3 RS |
3116 | if (channels) |
3117 | { | |
3118 | /* A register and a VU0 channel suffix. */ | |
3119 | token.u.regno = regno1; | |
3120 | mips_add_token (&token, OT_REG); | |
3121 | ||
3122 | token.u.channels = channels; | |
3123 | mips_add_token (&token, OT_CHANNELS); | |
3124 | return s; | |
3125 | } | |
3126 | ||
a92713e6 RS |
3127 | SKIP_SPACE_TABS (s); |
3128 | if (*s == '-') | |
df58fc94 | 3129 | { |
a92713e6 RS |
3130 | /* A register range. */ |
3131 | ++s; | |
3132 | SKIP_SPACE_TABS (s); | |
14daeee3 | 3133 | if (!mips_parse_register (&s, ®no2, NULL)) |
a92713e6 | 3134 | { |
1661c76c | 3135 | set_insn_error (0, _("invalid register range")); |
a92713e6 RS |
3136 | return 0; |
3137 | } | |
df58fc94 | 3138 | |
a92713e6 RS |
3139 | token.u.reg_range.regno1 = regno1; |
3140 | token.u.reg_range.regno2 = regno2; | |
3141 | mips_add_token (&token, OT_REG_RANGE); | |
3142 | return s; | |
3143 | } | |
a92713e6 | 3144 | |
56d438b1 CF |
3145 | /* Add the register itself. */ |
3146 | token.u.regno = regno1; | |
3147 | mips_add_token (&token, OT_REG); | |
3148 | ||
3149 | /* Check for a vector index. */ | |
3150 | if (*s == '[') | |
3151 | { | |
a92713e6 RS |
3152 | ++s; |
3153 | SKIP_SPACE_TABS (s); | |
56d438b1 CF |
3154 | if (mips_parse_register (&s, &token.u.regno, NULL)) |
3155 | mips_add_token (&token, OT_REG_INDEX); | |
3156 | else | |
a92713e6 | 3157 | { |
56d438b1 CF |
3158 | expressionS element; |
3159 | ||
3160 | my_getExpression (&element, s); | |
3161 | if (element.X_op != O_constant) | |
3162 | { | |
3163 | set_insn_error (0, _("vector element must be constant")); | |
3164 | return 0; | |
3165 | } | |
3166 | s = expr_end; | |
3167 | token.u.index = element.X_add_number; | |
3168 | mips_add_token (&token, OT_INTEGER_INDEX); | |
a92713e6 | 3169 | } |
a92713e6 RS |
3170 | SKIP_SPACE_TABS (s); |
3171 | if (*s != ']') | |
3172 | { | |
1661c76c | 3173 | set_insn_error (0, _("missing `]'")); |
a92713e6 RS |
3174 | return 0; |
3175 | } | |
3176 | ++s; | |
df58fc94 | 3177 | } |
a92713e6 | 3178 | return s; |
df58fc94 RS |
3179 | } |
3180 | ||
a92713e6 RS |
3181 | if (float_format) |
3182 | { | |
3183 | /* First try to treat expressions as floats. */ | |
3184 | save_in = input_line_pointer; | |
3185 | input_line_pointer = s; | |
3186 | err = md_atof (float_format, (char *) token.u.flt.data, | |
3187 | &token.u.flt.length); | |
3188 | end = input_line_pointer; | |
3189 | input_line_pointer = save_in; | |
3190 | if (err && *err) | |
3191 | { | |
e3de51ce | 3192 | set_insn_error (0, err); |
a92713e6 RS |
3193 | return 0; |
3194 | } | |
3195 | if (s != end) | |
3196 | { | |
3197 | mips_add_token (&token, OT_FLOAT); | |
3198 | return end; | |
3199 | } | |
3200 | } | |
3201 | ||
3202 | /* Treat everything else as an integer expression. */ | |
3203 | token.u.integer.relocs[0] = BFD_RELOC_UNUSED; | |
3204 | token.u.integer.relocs[1] = BFD_RELOC_UNUSED; | |
3205 | token.u.integer.relocs[2] = BFD_RELOC_UNUSED; | |
3206 | my_getSmallExpression (&token.u.integer.value, token.u.integer.relocs, s); | |
3207 | s = expr_end; | |
3208 | mips_add_token (&token, OT_INTEGER); | |
3209 | return s; | |
3210 | } | |
3211 | ||
3212 | /* S points to the operand list for an instruction. FLOAT_FORMAT is 'f' | |
3213 | if expressions should be treated as 32-bit floating-point constants, | |
3214 | 'd' if they should be treated as 64-bit floating-point constants, | |
3215 | or 0 if they should be treated as integer expressions (the usual case). | |
3216 | ||
3217 | Return a list of tokens on success, otherwise return 0. The caller | |
3218 | must obstack_free the list after use. */ | |
3219 | ||
3220 | static struct mips_operand_token * | |
3221 | mips_parse_arguments (char *s, char float_format) | |
3222 | { | |
3223 | struct mips_operand_token token; | |
3224 | ||
3225 | SKIP_SPACE_TABS (s); | |
3226 | while (*s) | |
3227 | { | |
3228 | s = mips_parse_argument_token (s, float_format); | |
3229 | if (!s) | |
3230 | { | |
3231 | obstack_free (&mips_operand_tokens, | |
3232 | obstack_finish (&mips_operand_tokens)); | |
3233 | return 0; | |
3234 | } | |
3235 | SKIP_SPACE_TABS (s); | |
3236 | } | |
3237 | mips_add_token (&token, OT_END); | |
3238 | return (struct mips_operand_token *) obstack_finish (&mips_operand_tokens); | |
df58fc94 RS |
3239 | } |
3240 | ||
d301a56b RS |
3241 | /* Return TRUE if opcode MO is valid on the currently selected ISA, ASE |
3242 | and architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */ | |
037b32b9 AN |
3243 | |
3244 | static bfd_boolean | |
f79e2745 | 3245 | is_opcode_valid (const struct mips_opcode *mo) |
037b32b9 AN |
3246 | { |
3247 | int isa = mips_opts.isa; | |
846ef2d0 | 3248 | int ase = mips_opts.ase; |
037b32b9 | 3249 | int fp_s, fp_d; |
c6278170 | 3250 | unsigned int i; |
037b32b9 | 3251 | |
be0fcbee | 3252 | if (ISA_HAS_64BIT_REGS (isa)) |
c6278170 RS |
3253 | for (i = 0; i < ARRAY_SIZE (mips_ases); i++) |
3254 | if ((ase & mips_ases[i].flags) == mips_ases[i].flags) | |
3255 | ase |= mips_ases[i].flags64; | |
037b32b9 | 3256 | |
d301a56b | 3257 | if (!opcode_is_member (mo, isa, ase, mips_opts.arch)) |
037b32b9 AN |
3258 | return FALSE; |
3259 | ||
3260 | /* Check whether the instruction or macro requires single-precision or | |
3261 | double-precision floating-point support. Note that this information is | |
3262 | stored differently in the opcode table for insns and macros. */ | |
3263 | if (mo->pinfo == INSN_MACRO) | |
3264 | { | |
3265 | fp_s = mo->pinfo2 & INSN2_M_FP_S; | |
3266 | fp_d = mo->pinfo2 & INSN2_M_FP_D; | |
3267 | } | |
3268 | else | |
3269 | { | |
3270 | fp_s = mo->pinfo & FP_S; | |
3271 | fp_d = mo->pinfo & FP_D; | |
3272 | } | |
3273 | ||
3274 | if (fp_d && (mips_opts.soft_float || mips_opts.single_float)) | |
3275 | return FALSE; | |
3276 | ||
3277 | if (fp_s && mips_opts.soft_float) | |
3278 | return FALSE; | |
3279 | ||
3280 | return TRUE; | |
3281 | } | |
3282 | ||
3283 | /* Return TRUE if the MIPS16 opcode MO is valid on the currently | |
3284 | selected ISA and architecture. */ | |
3285 | ||
3286 | static bfd_boolean | |
3287 | is_opcode_valid_16 (const struct mips_opcode *mo) | |
3288 | { | |
d301a56b | 3289 | return opcode_is_member (mo, mips_opts.isa, 0, mips_opts.arch); |
037b32b9 AN |
3290 | } |
3291 | ||
df58fc94 | 3292 | /* Return TRUE if the size of the microMIPS opcode MO matches one |
7fd53920 MR |
3293 | explicitly requested. Always TRUE in the standard MIPS mode. |
3294 | Use is_size_valid_16 for MIPS16 opcodes. */ | |
df58fc94 RS |
3295 | |
3296 | static bfd_boolean | |
3297 | is_size_valid (const struct mips_opcode *mo) | |
3298 | { | |
3299 | if (!mips_opts.micromips) | |
3300 | return TRUE; | |
3301 | ||
833794fc MR |
3302 | if (mips_opts.insn32) |
3303 | { | |
3304 | if (mo->pinfo != INSN_MACRO && micromips_insn_length (mo) != 4) | |
3305 | return FALSE; | |
3306 | if ((mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0) | |
3307 | return FALSE; | |
3308 | } | |
df58fc94 RS |
3309 | if (!forced_insn_length) |
3310 | return TRUE; | |
3311 | if (mo->pinfo == INSN_MACRO) | |
3312 | return FALSE; | |
3313 | return forced_insn_length == micromips_insn_length (mo); | |
3314 | } | |
3315 | ||
7fd53920 MR |
3316 | /* Return TRUE if the size of the MIPS16 opcode MO matches one |
3317 | explicitly requested. */ | |
3318 | ||
3319 | static bfd_boolean | |
3320 | is_size_valid_16 (const struct mips_opcode *mo) | |
3321 | { | |
3322 | if (!forced_insn_length) | |
3323 | return TRUE; | |
3324 | if (mo->pinfo == INSN_MACRO) | |
3325 | return FALSE; | |
3326 | if (forced_insn_length == 2 && mips_opcode_32bit_p (mo)) | |
3327 | return FALSE; | |
0674ee5d MR |
3328 | if (forced_insn_length == 4 && (mo->pinfo2 & INSN2_SHORT_ONLY)) |
3329 | return FALSE; | |
7fd53920 MR |
3330 | return TRUE; |
3331 | } | |
3332 | ||
df58fc94 | 3333 | /* Return TRUE if the microMIPS opcode MO is valid for the delay slot |
e64af278 MR |
3334 | of the preceding instruction. Always TRUE in the standard MIPS mode. |
3335 | ||
3336 | We don't accept macros in 16-bit delay slots to avoid a case where | |
3337 | a macro expansion fails because it relies on a preceding 32-bit real | |
3338 | instruction to have matched and does not handle the operands correctly. | |
3339 | The only macros that may expand to 16-bit instructions are JAL that | |
3340 | cannot be placed in a delay slot anyway, and corner cases of BALIGN | |
3341 | and BGT (that likewise cannot be placed in a delay slot) that decay to | |
3342 | a NOP. In all these cases the macros precede any corresponding real | |
3343 | instruction definitions in the opcode table, so they will match in the | |
3344 | second pass where the size of the delay slot is ignored and therefore | |
3345 | produce correct code. */ | |
df58fc94 RS |
3346 | |
3347 | static bfd_boolean | |
3348 | is_delay_slot_valid (const struct mips_opcode *mo) | |
3349 | { | |
3350 | if (!mips_opts.micromips) | |
3351 | return TRUE; | |
3352 | ||
3353 | if (mo->pinfo == INSN_MACRO) | |
c06dec14 | 3354 | return (history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) == 0; |
df58fc94 RS |
3355 | if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0 |
3356 | && micromips_insn_length (mo) != 4) | |
3357 | return FALSE; | |
3358 | if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 | |
3359 | && micromips_insn_length (mo) != 2) | |
3360 | return FALSE; | |
3361 | ||
3362 | return TRUE; | |
3363 | } | |
3364 | ||
fc76e730 RS |
3365 | /* For consistency checking, verify that all bits of OPCODE are specified |
3366 | either by the match/mask part of the instruction definition, or by the | |
3367 | operand list. Also build up a list of operands in OPERANDS. | |
3368 | ||
3369 | INSN_BITS says which bits of the instruction are significant. | |
3370 | If OPCODE is a standard or microMIPS instruction, DECODE_OPERAND | |
3371 | provides the mips_operand description of each operand. DECODE_OPERAND | |
3372 | is null for MIPS16 instructions. */ | |
ab902481 RS |
3373 | |
3374 | static int | |
3375 | validate_mips_insn (const struct mips_opcode *opcode, | |
3376 | unsigned long insn_bits, | |
fc76e730 RS |
3377 | const struct mips_operand *(*decode_operand) (const char *), |
3378 | struct mips_operand_array *operands) | |
ab902481 RS |
3379 | { |
3380 | const char *s; | |
fc76e730 | 3381 | unsigned long used_bits, doubled, undefined, opno, mask; |
ab902481 RS |
3382 | const struct mips_operand *operand; |
3383 | ||
fc76e730 RS |
3384 | mask = (opcode->pinfo == INSN_MACRO ? 0 : opcode->mask); |
3385 | if ((mask & opcode->match) != opcode->match) | |
ab902481 RS |
3386 | { |
3387 | as_bad (_("internal: bad mips opcode (mask error): %s %s"), | |
3388 | opcode->name, opcode->args); | |
3389 | return 0; | |
3390 | } | |
3391 | used_bits = 0; | |
fc76e730 | 3392 | opno = 0; |
14daeee3 RS |
3393 | if (opcode->pinfo2 & INSN2_VU0_CHANNEL_SUFFIX) |
3394 | used_bits = mips_insert_operand (&mips_vu0_channel_mask, used_bits, -1); | |
ab902481 RS |
3395 | for (s = opcode->args; *s; ++s) |
3396 | switch (*s) | |
3397 | { | |
3398 | case ',': | |
3399 | case '(': | |
3400 | case ')': | |
3401 | break; | |
3402 | ||
14daeee3 RS |
3403 | case '#': |
3404 | s++; | |
3405 | break; | |
3406 | ||
ab902481 | 3407 | default: |
fc76e730 | 3408 | if (!decode_operand) |
7fd53920 | 3409 | operand = decode_mips16_operand (*s, mips_opcode_32bit_p (opcode)); |
fc76e730 RS |
3410 | else |
3411 | operand = decode_operand (s); | |
3412 | if (!operand && opcode->pinfo != INSN_MACRO) | |
ab902481 RS |
3413 | { |
3414 | as_bad (_("internal: unknown operand type: %s %s"), | |
3415 | opcode->name, opcode->args); | |
3416 | return 0; | |
3417 | } | |
fc76e730 RS |
3418 | gas_assert (opno < MAX_OPERANDS); |
3419 | operands->operand[opno] = operand; | |
14daeee3 | 3420 | if (operand && operand->type != OP_VU0_MATCH_SUFFIX) |
fc76e730 | 3421 | { |
14daeee3 | 3422 | used_bits = mips_insert_operand (operand, used_bits, -1); |
fc76e730 RS |
3423 | if (operand->type == OP_MDMX_IMM_REG) |
3424 | /* Bit 5 is the format selector (OB vs QH). The opcode table | |
3425 | has separate entries for each format. */ | |
3426 | used_bits &= ~(1 << (operand->lsb + 5)); | |
3427 | if (operand->type == OP_ENTRY_EXIT_LIST) | |
3428 | used_bits &= ~(mask & 0x700); | |
3429 | } | |
ab902481 | 3430 | /* Skip prefix characters. */ |
7361da2c | 3431 | if (decode_operand && (*s == '+' || *s == 'm' || *s == '-')) |
ab902481 | 3432 | ++s; |
fc76e730 | 3433 | opno += 1; |
ab902481 RS |
3434 | break; |
3435 | } | |
fc76e730 | 3436 | doubled = used_bits & mask & insn_bits; |
ab902481 RS |
3437 | if (doubled) |
3438 | { | |
3439 | as_bad (_("internal: bad mips opcode (bits 0x%08lx doubly defined):" | |
3440 | " %s %s"), doubled, opcode->name, opcode->args); | |
3441 | return 0; | |
3442 | } | |
fc76e730 | 3443 | used_bits |= mask; |
ab902481 | 3444 | undefined = ~used_bits & insn_bits; |
fc76e730 | 3445 | if (opcode->pinfo != INSN_MACRO && undefined) |
ab902481 RS |
3446 | { |
3447 | as_bad (_("internal: bad mips opcode (bits 0x%08lx undefined): %s %s"), | |
3448 | undefined, opcode->name, opcode->args); | |
3449 | return 0; | |
3450 | } | |
3451 | used_bits &= ~insn_bits; | |
3452 | if (used_bits) | |
3453 | { | |
3454 | as_bad (_("internal: bad mips opcode (bits 0x%08lx defined): %s %s"), | |
3455 | used_bits, opcode->name, opcode->args); | |
3456 | return 0; | |
3457 | } | |
3458 | return 1; | |
3459 | } | |
3460 | ||
fc76e730 RS |
3461 | /* The MIPS16 version of validate_mips_insn. */ |
3462 | ||
3463 | static int | |
3464 | validate_mips16_insn (const struct mips_opcode *opcode, | |
3465 | struct mips_operand_array *operands) | |
3466 | { | |
7fd53920 | 3467 | unsigned long insn_bits = mips_opcode_32bit_p (opcode) ? 0xffffffff : 0xffff; |
fc76e730 | 3468 | |
7fd53920 | 3469 | return validate_mips_insn (opcode, insn_bits, 0, operands); |
fc76e730 RS |
3470 | } |
3471 | ||
ab902481 RS |
3472 | /* The microMIPS version of validate_mips_insn. */ |
3473 | ||
3474 | static int | |
fc76e730 RS |
3475 | validate_micromips_insn (const struct mips_opcode *opc, |
3476 | struct mips_operand_array *operands) | |
ab902481 RS |
3477 | { |
3478 | unsigned long insn_bits; | |
3479 | unsigned long major; | |
3480 | unsigned int length; | |
3481 | ||
fc76e730 RS |
3482 | if (opc->pinfo == INSN_MACRO) |
3483 | return validate_mips_insn (opc, 0xffffffff, decode_micromips_operand, | |
3484 | operands); | |
3485 | ||
ab902481 RS |
3486 | length = micromips_insn_length (opc); |
3487 | if (length != 2 && length != 4) | |
3488 | { | |
1661c76c | 3489 | as_bad (_("internal error: bad microMIPS opcode (incorrect length: %u): " |
ab902481 RS |
3490 | "%s %s"), length, opc->name, opc->args); |
3491 | return 0; | |
3492 | } | |
3493 | major = opc->match >> (10 + 8 * (length - 2)); | |
3494 | if ((length == 2 && (major & 7) != 1 && (major & 6) != 2) | |
3495 | || (length == 4 && (major & 7) != 0 && (major & 4) != 4)) | |
3496 | { | |
1661c76c | 3497 | as_bad (_("internal error: bad microMIPS opcode " |
ab902481 RS |
3498 | "(opcode/length mismatch): %s %s"), opc->name, opc->args); |
3499 | return 0; | |
3500 | } | |
3501 | ||
3502 | /* Shift piecewise to avoid an overflow where unsigned long is 32-bit. */ | |
3503 | insn_bits = 1 << 4 * length; | |
3504 | insn_bits <<= 4 * length; | |
3505 | insn_bits -= 1; | |
fc76e730 RS |
3506 | return validate_mips_insn (opc, insn_bits, decode_micromips_operand, |
3507 | operands); | |
ab902481 RS |
3508 | } |
3509 | ||
707bfff6 TS |
3510 | /* This function is called once, at assembler startup time. It should set up |
3511 | all the tables, etc. that the MD part of the assembler will need. */ | |
156c2f8b | 3512 | |
252b5132 | 3513 | void |
17a2f251 | 3514 | md_begin (void) |
252b5132 | 3515 | { |
3994f87e | 3516 | const char *retval = NULL; |
156c2f8b | 3517 | int i = 0; |
252b5132 | 3518 | int broken = 0; |
1f25f5d3 | 3519 | |
0a44bf69 RS |
3520 | if (mips_pic != NO_PIC) |
3521 | { | |
3522 | if (g_switch_seen && g_switch_value != 0) | |
3523 | as_bad (_("-G may not be used in position-independent code")); | |
3524 | g_switch_value = 0; | |
3525 | } | |
00acd688 CM |
3526 | else if (mips_abicalls) |
3527 | { | |
3528 | if (g_switch_seen && g_switch_value != 0) | |
3529 | as_bad (_("-G may not be used with abicalls")); | |
3530 | g_switch_value = 0; | |
3531 | } | |
0a44bf69 | 3532 | |
0b35dfee | 3533 | if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_opts.arch)) |
1661c76c | 3534 | as_warn (_("could not set architecture and machine")); |
252b5132 | 3535 | |
252b5132 RH |
3536 | op_hash = hash_new (); |
3537 | ||
fc76e730 | 3538 | mips_operands = XCNEWVEC (struct mips_operand_array, NUMOPCODES); |
252b5132 RH |
3539 | for (i = 0; i < NUMOPCODES;) |
3540 | { | |
3541 | const char *name = mips_opcodes[i].name; | |
3542 | ||
17a2f251 | 3543 | retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]); |
252b5132 RH |
3544 | if (retval != NULL) |
3545 | { | |
3546 | fprintf (stderr, _("internal error: can't hash `%s': %s\n"), | |
3547 | mips_opcodes[i].name, retval); | |
3548 | /* Probably a memory allocation problem? Give up now. */ | |
1661c76c | 3549 | as_fatal (_("broken assembler, no assembly attempted")); |
252b5132 RH |
3550 | } |
3551 | do | |
3552 | { | |
fc76e730 RS |
3553 | if (!validate_mips_insn (&mips_opcodes[i], 0xffffffff, |
3554 | decode_mips_operand, &mips_operands[i])) | |
3555 | broken = 1; | |
3556 | if (nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0) | |
252b5132 | 3557 | { |
fc76e730 RS |
3558 | create_insn (&nop_insn, mips_opcodes + i); |
3559 | if (mips_fix_loongson2f_nop) | |
3560 | nop_insn.insn_opcode = LOONGSON2F_NOP_INSN; | |
3561 | nop_insn.fixed_p = 1; | |
252b5132 RH |
3562 | } |
3563 | ++i; | |
3564 | } | |
3565 | while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name)); | |
3566 | } | |
3567 | ||
3568 | mips16_op_hash = hash_new (); | |
fc76e730 RS |
3569 | mips16_operands = XCNEWVEC (struct mips_operand_array, |
3570 | bfd_mips16_num_opcodes); | |
252b5132 RH |
3571 | |
3572 | i = 0; | |
3573 | while (i < bfd_mips16_num_opcodes) | |
3574 | { | |
3575 | const char *name = mips16_opcodes[i].name; | |
3576 | ||
17a2f251 | 3577 | retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]); |
252b5132 RH |
3578 | if (retval != NULL) |
3579 | as_fatal (_("internal: can't hash `%s': %s"), | |
3580 | mips16_opcodes[i].name, retval); | |
3581 | do | |
3582 | { | |
fc76e730 RS |
3583 | if (!validate_mips16_insn (&mips16_opcodes[i], &mips16_operands[i])) |
3584 | broken = 1; | |
1e915849 RS |
3585 | if (mips16_nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0) |
3586 | { | |
3587 | create_insn (&mips16_nop_insn, mips16_opcodes + i); | |
3588 | mips16_nop_insn.fixed_p = 1; | |
3589 | } | |
252b5132 RH |
3590 | ++i; |
3591 | } | |
3592 | while (i < bfd_mips16_num_opcodes | |
3593 | && strcmp (mips16_opcodes[i].name, name) == 0); | |
3594 | } | |
3595 | ||
df58fc94 | 3596 | micromips_op_hash = hash_new (); |
fc76e730 RS |
3597 | micromips_operands = XCNEWVEC (struct mips_operand_array, |
3598 | bfd_micromips_num_opcodes); | |
df58fc94 RS |
3599 | |
3600 | i = 0; | |
3601 | while (i < bfd_micromips_num_opcodes) | |
3602 | { | |
3603 | const char *name = micromips_opcodes[i].name; | |
3604 | ||
3605 | retval = hash_insert (micromips_op_hash, name, | |
3606 | (void *) µmips_opcodes[i]); | |
3607 | if (retval != NULL) | |
3608 | as_fatal (_("internal: can't hash `%s': %s"), | |
3609 | micromips_opcodes[i].name, retval); | |
3610 | do | |
fc76e730 RS |
3611 | { |
3612 | struct mips_cl_insn *micromips_nop_insn; | |
3613 | ||
3614 | if (!validate_micromips_insn (µmips_opcodes[i], | |
3615 | µmips_operands[i])) | |
3616 | broken = 1; | |
3617 | ||
3618 | if (micromips_opcodes[i].pinfo != INSN_MACRO) | |
3619 | { | |
3620 | if (micromips_insn_length (micromips_opcodes + i) == 2) | |
3621 | micromips_nop_insn = µmips_nop16_insn; | |
3622 | else if (micromips_insn_length (micromips_opcodes + i) == 4) | |
3623 | micromips_nop_insn = µmips_nop32_insn; | |
3624 | else | |
3625 | continue; | |
3626 | ||
3627 | if (micromips_nop_insn->insn_mo == NULL | |
3628 | && strcmp (name, "nop") == 0) | |
3629 | { | |
3630 | create_insn (micromips_nop_insn, micromips_opcodes + i); | |
3631 | micromips_nop_insn->fixed_p = 1; | |
3632 | } | |
3633 | } | |
3634 | } | |
df58fc94 RS |
3635 | while (++i < bfd_micromips_num_opcodes |
3636 | && strcmp (micromips_opcodes[i].name, name) == 0); | |
3637 | } | |
3638 | ||
252b5132 | 3639 | if (broken) |
1661c76c | 3640 | as_fatal (_("broken assembler, no assembly attempted")); |
252b5132 RH |
3641 | |
3642 | /* We add all the general register names to the symbol table. This | |
3643 | helps us detect invalid uses of them. */ | |
3739860c | 3644 | for (i = 0; reg_names[i].name; i++) |
707bfff6 | 3645 | symbol_table_insert (symbol_new (reg_names[i].name, reg_section, |
8fc4ee9b | 3646 | reg_names[i].num, /* & RNUM_MASK, */ |
707bfff6 TS |
3647 | &zero_address_frag)); |
3648 | if (HAVE_NEWABI) | |
3739860c | 3649 | for (i = 0; reg_names_n32n64[i].name; i++) |
707bfff6 | 3650 | symbol_table_insert (symbol_new (reg_names_n32n64[i].name, reg_section, |
8fc4ee9b | 3651 | reg_names_n32n64[i].num, /* & RNUM_MASK, */ |
252b5132 | 3652 | &zero_address_frag)); |
707bfff6 | 3653 | else |
3739860c | 3654 | for (i = 0; reg_names_o32[i].name; i++) |
707bfff6 | 3655 | symbol_table_insert (symbol_new (reg_names_o32[i].name, reg_section, |
8fc4ee9b | 3656 | reg_names_o32[i].num, /* & RNUM_MASK, */ |
6047c971 | 3657 | &zero_address_frag)); |
6047c971 | 3658 | |
14daeee3 RS |
3659 | for (i = 0; i < 32; i++) |
3660 | { | |
92fce9bd | 3661 | char regname[6]; |
14daeee3 RS |
3662 | |
3663 | /* R5900 VU0 floating-point register. */ | |
92fce9bd | 3664 | sprintf (regname, "$vf%d", i); |
14daeee3 RS |
3665 | symbol_table_insert (symbol_new (regname, reg_section, |
3666 | RTYPE_VF | i, &zero_address_frag)); | |
3667 | ||
3668 | /* R5900 VU0 integer register. */ | |
92fce9bd | 3669 | sprintf (regname, "$vi%d", i); |
14daeee3 RS |
3670 | symbol_table_insert (symbol_new (regname, reg_section, |
3671 | RTYPE_VI | i, &zero_address_frag)); | |
3672 | ||
56d438b1 | 3673 | /* MSA register. */ |
92fce9bd | 3674 | sprintf (regname, "$w%d", i); |
56d438b1 CF |
3675 | symbol_table_insert (symbol_new (regname, reg_section, |
3676 | RTYPE_MSA | i, &zero_address_frag)); | |
14daeee3 RS |
3677 | } |
3678 | ||
a92713e6 RS |
3679 | obstack_init (&mips_operand_tokens); |
3680 | ||
7d10b47d | 3681 | mips_no_prev_insn (); |
252b5132 RH |
3682 | |
3683 | mips_gprmask = 0; | |
3684 | mips_cprmask[0] = 0; | |
3685 | mips_cprmask[1] = 0; | |
3686 | mips_cprmask[2] = 0; | |
3687 | mips_cprmask[3] = 0; | |
3688 | ||
3689 | /* set the default alignment for the text section (2**2) */ | |
3690 | record_alignment (text_section, 2); | |
3691 | ||
4d0d148d | 3692 | bfd_set_gp_size (stdoutput, g_switch_value); |
252b5132 | 3693 | |
f3ded42a RS |
3694 | /* On a native system other than VxWorks, sections must be aligned |
3695 | to 16 byte boundaries. When configured for an embedded ELF | |
3696 | target, we don't bother. */ | |
3697 | if (strncmp (TARGET_OS, "elf", 3) != 0 | |
3698 | && strncmp (TARGET_OS, "vxworks", 7) != 0) | |
252b5132 | 3699 | { |
f3ded42a RS |
3700 | (void) bfd_set_section_alignment (stdoutput, text_section, 4); |
3701 | (void) bfd_set_section_alignment (stdoutput, data_section, 4); | |
3702 | (void) bfd_set_section_alignment (stdoutput, bss_section, 4); | |
3703 | } | |
252b5132 | 3704 | |
f3ded42a RS |
3705 | /* Create a .reginfo section for register masks and a .mdebug |
3706 | section for debugging information. */ | |
3707 | { | |
3708 | segT seg; | |
3709 | subsegT subseg; | |
3710 | flagword flags; | |
3711 | segT sec; | |
3712 | ||
3713 | seg = now_seg; | |
3714 | subseg = now_subseg; | |
3715 | ||
3716 | /* The ABI says this section should be loaded so that the | |
3717 | running program can access it. However, we don't load it | |
3718 | if we are configured for an embedded target */ | |
3719 | flags = SEC_READONLY | SEC_DATA; | |
3720 | if (strncmp (TARGET_OS, "elf", 3) != 0) | |
3721 | flags |= SEC_ALLOC | SEC_LOAD; | |
3722 | ||
3723 | if (mips_abi != N64_ABI) | |
252b5132 | 3724 | { |
f3ded42a | 3725 | sec = subseg_new (".reginfo", (subsegT) 0); |
bdaaa2e1 | 3726 | |
f3ded42a RS |
3727 | bfd_set_section_flags (stdoutput, sec, flags); |
3728 | bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2); | |
252b5132 | 3729 | |
f3ded42a RS |
3730 | mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo)); |
3731 | } | |
3732 | else | |
3733 | { | |
3734 | /* The 64-bit ABI uses a .MIPS.options section rather than | |
3735 | .reginfo section. */ | |
3736 | sec = subseg_new (".MIPS.options", (subsegT) 0); | |
3737 | bfd_set_section_flags (stdoutput, sec, flags); | |
3738 | bfd_set_section_alignment (stdoutput, sec, 3); | |
252b5132 | 3739 | |
f3ded42a RS |
3740 | /* Set up the option header. */ |
3741 | { | |
3742 | Elf_Internal_Options opthdr; | |
3743 | char *f; | |
3744 | ||
3745 | opthdr.kind = ODK_REGINFO; | |
3746 | opthdr.size = (sizeof (Elf_External_Options) | |
3747 | + sizeof (Elf64_External_RegInfo)); | |
3748 | opthdr.section = 0; | |
3749 | opthdr.info = 0; | |
3750 | f = frag_more (sizeof (Elf_External_Options)); | |
3751 | bfd_mips_elf_swap_options_out (stdoutput, &opthdr, | |
3752 | (Elf_External_Options *) f); | |
3753 | ||
3754 | mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo)); | |
3755 | } | |
3756 | } | |
252b5132 | 3757 | |
351cdf24 MF |
3758 | sec = subseg_new (".MIPS.abiflags", (subsegT) 0); |
3759 | bfd_set_section_flags (stdoutput, sec, | |
3760 | SEC_READONLY | SEC_DATA | SEC_ALLOC | SEC_LOAD); | |
3761 | bfd_set_section_alignment (stdoutput, sec, 3); | |
3762 | mips_flags_frag = frag_more (sizeof (Elf_External_ABIFlags_v0)); | |
3763 | ||
f3ded42a RS |
3764 | if (ECOFF_DEBUGGING) |
3765 | { | |
3766 | sec = subseg_new (".mdebug", (subsegT) 0); | |
3767 | (void) bfd_set_section_flags (stdoutput, sec, | |
3768 | SEC_HAS_CONTENTS | SEC_READONLY); | |
3769 | (void) bfd_set_section_alignment (stdoutput, sec, 2); | |
252b5132 | 3770 | } |
f3ded42a RS |
3771 | else if (mips_flag_pdr) |
3772 | { | |
3773 | pdr_seg = subseg_new (".pdr", (subsegT) 0); | |
3774 | (void) bfd_set_section_flags (stdoutput, pdr_seg, | |
3775 | SEC_READONLY | SEC_RELOC | |
3776 | | SEC_DEBUGGING); | |
3777 | (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2); | |
3778 | } | |
3779 | ||
3780 | subseg_set (seg, subseg); | |
3781 | } | |
252b5132 | 3782 | |
71400594 RS |
3783 | if (mips_fix_vr4120) |
3784 | init_vr4120_conflicts (); | |
252b5132 RH |
3785 | } |
3786 | ||
351cdf24 MF |
3787 | static inline void |
3788 | fpabi_incompatible_with (int fpabi, const char *what) | |
3789 | { | |
3790 | as_warn (_(".gnu_attribute %d,%d is incompatible with `%s'"), | |
3791 | Tag_GNU_MIPS_ABI_FP, fpabi, what); | |
3792 | } | |
3793 | ||
3794 | static inline void | |
3795 | fpabi_requires (int fpabi, const char *what) | |
3796 | { | |
3797 | as_warn (_(".gnu_attribute %d,%d requires `%s'"), | |
3798 | Tag_GNU_MIPS_ABI_FP, fpabi, what); | |
3799 | } | |
3800 | ||
3801 | /* Check -mabi and register sizes against the specified FP ABI. */ | |
3802 | static void | |
3803 | check_fpabi (int fpabi) | |
3804 | { | |
351cdf24 MF |
3805 | switch (fpabi) |
3806 | { | |
3807 | case Val_GNU_MIPS_ABI_FP_DOUBLE: | |
ea79f94a MF |
3808 | if (file_mips_opts.soft_float) |
3809 | fpabi_incompatible_with (fpabi, "softfloat"); | |
3810 | else if (file_mips_opts.single_float) | |
3811 | fpabi_incompatible_with (fpabi, "singlefloat"); | |
351cdf24 MF |
3812 | if (file_mips_opts.gp == 64 && file_mips_opts.fp == 32) |
3813 | fpabi_incompatible_with (fpabi, "gp=64 fp=32"); | |
3814 | else if (file_mips_opts.gp == 32 && file_mips_opts.fp == 64) | |
3815 | fpabi_incompatible_with (fpabi, "gp=32 fp=64"); | |
351cdf24 MF |
3816 | break; |
3817 | ||
3818 | case Val_GNU_MIPS_ABI_FP_XX: | |
3819 | if (mips_abi != O32_ABI) | |
3820 | fpabi_requires (fpabi, "-mabi=32"); | |
ea79f94a MF |
3821 | else if (file_mips_opts.soft_float) |
3822 | fpabi_incompatible_with (fpabi, "softfloat"); | |
3823 | else if (file_mips_opts.single_float) | |
3824 | fpabi_incompatible_with (fpabi, "singlefloat"); | |
351cdf24 MF |
3825 | else if (file_mips_opts.fp != 0) |
3826 | fpabi_requires (fpabi, "fp=xx"); | |
351cdf24 MF |
3827 | break; |
3828 | ||
3829 | case Val_GNU_MIPS_ABI_FP_64A: | |
3830 | case Val_GNU_MIPS_ABI_FP_64: | |
3831 | if (mips_abi != O32_ABI) | |
3832 | fpabi_requires (fpabi, "-mabi=32"); | |
ea79f94a MF |
3833 | else if (file_mips_opts.soft_float) |
3834 | fpabi_incompatible_with (fpabi, "softfloat"); | |
3835 | else if (file_mips_opts.single_float) | |
3836 | fpabi_incompatible_with (fpabi, "singlefloat"); | |
351cdf24 MF |
3837 | else if (file_mips_opts.fp != 64) |
3838 | fpabi_requires (fpabi, "fp=64"); | |
3839 | else if (fpabi == Val_GNU_MIPS_ABI_FP_64 && !file_mips_opts.oddspreg) | |
3840 | fpabi_incompatible_with (fpabi, "nooddspreg"); | |
3841 | else if (fpabi == Val_GNU_MIPS_ABI_FP_64A && file_mips_opts.oddspreg) | |
3842 | fpabi_requires (fpabi, "nooddspreg"); | |
351cdf24 MF |
3843 | break; |
3844 | ||
3845 | case Val_GNU_MIPS_ABI_FP_SINGLE: | |
3846 | if (file_mips_opts.soft_float) | |
3847 | fpabi_incompatible_with (fpabi, "softfloat"); | |
3848 | else if (!file_mips_opts.single_float) | |
3849 | fpabi_requires (fpabi, "singlefloat"); | |
3850 | break; | |
3851 | ||
3852 | case Val_GNU_MIPS_ABI_FP_SOFT: | |
3853 | if (!file_mips_opts.soft_float) | |
3854 | fpabi_requires (fpabi, "softfloat"); | |
3855 | break; | |
3856 | ||
3857 | case Val_GNU_MIPS_ABI_FP_OLD_64: | |
3858 | as_warn (_(".gnu_attribute %d,%d is no longer supported"), | |
3859 | Tag_GNU_MIPS_ABI_FP, fpabi); | |
3860 | break; | |
3861 | ||
3350cc01 CM |
3862 | case Val_GNU_MIPS_ABI_FP_NAN2008: |
3863 | /* Silently ignore compatibility value. */ | |
3864 | break; | |
3865 | ||
351cdf24 MF |
3866 | default: |
3867 | as_warn (_(".gnu_attribute %d,%d is not a recognized" | |
3868 | " floating-point ABI"), Tag_GNU_MIPS_ABI_FP, fpabi); | |
3869 | break; | |
3870 | } | |
351cdf24 MF |
3871 | } |
3872 | ||
919731af | 3873 | /* Perform consistency checks on the current options. */ |
3874 | ||
3875 | static void | |
3876 | mips_check_options (struct mips_set_options *opts, bfd_boolean abi_checks) | |
3877 | { | |
3878 | /* Check the size of integer registers agrees with the ABI and ISA. */ | |
3879 | if (opts->gp == 64 && !ISA_HAS_64BIT_REGS (opts->isa)) | |
3880 | as_bad (_("`gp=64' used with a 32-bit processor")); | |
3881 | else if (abi_checks | |
3882 | && opts->gp == 32 && ABI_NEEDS_64BIT_REGS (mips_abi)) | |
3883 | as_bad (_("`gp=32' used with a 64-bit ABI")); | |
3884 | else if (abi_checks | |
3885 | && opts->gp == 64 && ABI_NEEDS_32BIT_REGS (mips_abi)) | |
3886 | as_bad (_("`gp=64' used with a 32-bit ABI")); | |
3887 | ||
3888 | /* Check the size of the float registers agrees with the ABI and ISA. */ | |
3889 | switch (opts->fp) | |
3890 | { | |
351cdf24 MF |
3891 | case 0: |
3892 | if (!CPU_HAS_LDC1_SDC1 (opts->arch)) | |
3893 | as_bad (_("`fp=xx' used with a cpu lacking ldc1/sdc1 instructions")); | |
3894 | else if (opts->single_float == 1) | |
3895 | as_bad (_("`fp=xx' cannot be used with `singlefloat'")); | |
3896 | break; | |
919731af | 3897 | case 64: |
3898 | if (!ISA_HAS_64BIT_FPRS (opts->isa)) | |
3899 | as_bad (_("`fp=64' used with a 32-bit fpu")); | |
3900 | else if (abi_checks | |
3901 | && ABI_NEEDS_32BIT_REGS (mips_abi) | |
3902 | && !ISA_HAS_MXHC1 (opts->isa)) | |
3903 | as_warn (_("`fp=64' used with a 32-bit ABI")); | |
3904 | break; | |
3905 | case 32: | |
3906 | if (abi_checks | |
3907 | && ABI_NEEDS_64BIT_REGS (mips_abi)) | |
3908 | as_warn (_("`fp=32' used with a 64-bit ABI")); | |
5f4678bb | 3909 | if (ISA_IS_R6 (opts->isa) && opts->single_float == 0) |
7361da2c | 3910 | as_bad (_("`fp=32' used with a MIPS R6 cpu")); |
919731af | 3911 | break; |
3912 | default: | |
3913 | as_bad (_("Unknown size of floating point registers")); | |
3914 | break; | |
3915 | } | |
3916 | ||
351cdf24 MF |
3917 | if (ABI_NEEDS_64BIT_REGS (mips_abi) && !opts->oddspreg) |
3918 | as_bad (_("`nooddspreg` cannot be used with a 64-bit ABI")); | |
3919 | ||
919731af | 3920 | if (opts->micromips == 1 && opts->mips16 == 1) |
1357373c | 3921 | as_bad (_("`%s' cannot be used with `%s'"), "mips16", "micromips"); |
5f4678bb | 3922 | else if (ISA_IS_R6 (opts->isa) |
7361da2c AB |
3923 | && (opts->micromips == 1 |
3924 | || opts->mips16 == 1)) | |
1357373c | 3925 | as_fatal (_("`%s' cannot be used with `%s'"), |
7361da2c | 3926 | opts->micromips ? "micromips" : "mips16", |
5f4678bb | 3927 | mips_cpu_info_from_isa (opts->isa)->name); |
7361da2c AB |
3928 | |
3929 | if (ISA_IS_R6 (opts->isa) && mips_relax_branch) | |
3930 | as_fatal (_("branch relaxation is not supported in `%s'"), | |
3931 | mips_cpu_info_from_isa (opts->isa)->name); | |
919731af | 3932 | } |
3933 | ||
3934 | /* Perform consistency checks on the module level options exactly once. | |
3935 | This is a deferred check that happens: | |
3936 | at the first .set directive | |
3937 | or, at the first pseudo op that generates code (inc .dc.a) | |
3938 | or, at the first instruction | |
3939 | or, at the end. */ | |
3940 | ||
3941 | static void | |
3942 | file_mips_check_options (void) | |
3943 | { | |
3944 | const struct mips_cpu_info *arch_info = 0; | |
3945 | ||
3946 | if (file_mips_opts_checked) | |
3947 | return; | |
3948 | ||
3949 | /* The following code determines the register size. | |
3950 | Similar code was added to GCC 3.3 (see override_options() in | |
3951 | config/mips/mips.c). The GAS and GCC code should be kept in sync | |
3952 | as much as possible. */ | |
3953 | ||
3954 | if (file_mips_opts.gp < 0) | |
3955 | { | |
3956 | /* Infer the integer register size from the ABI and processor. | |
3957 | Restrict ourselves to 32-bit registers if that's all the | |
3958 | processor has, or if the ABI cannot handle 64-bit registers. */ | |
3959 | file_mips_opts.gp = (ABI_NEEDS_32BIT_REGS (mips_abi) | |
3960 | || !ISA_HAS_64BIT_REGS (file_mips_opts.isa)) | |
3961 | ? 32 : 64; | |
3962 | } | |
3963 | ||
3964 | if (file_mips_opts.fp < 0) | |
3965 | { | |
3966 | /* No user specified float register size. | |
3967 | ??? GAS treats single-float processors as though they had 64-bit | |
3968 | float registers (although it complains when double-precision | |
3969 | instructions are used). As things stand, saying they have 32-bit | |
3970 | registers would lead to spurious "register must be even" messages. | |
3971 | So here we assume float registers are never smaller than the | |
3972 | integer ones. */ | |
3973 | if (file_mips_opts.gp == 64) | |
3974 | /* 64-bit integer registers implies 64-bit float registers. */ | |
3975 | file_mips_opts.fp = 64; | |
3976 | else if ((file_mips_opts.ase & FP64_ASES) | |
3977 | && ISA_HAS_64BIT_FPRS (file_mips_opts.isa)) | |
3978 | /* Handle ASEs that require 64-bit float registers, if possible. */ | |
3979 | file_mips_opts.fp = 64; | |
7361da2c AB |
3980 | else if (ISA_IS_R6 (mips_opts.isa)) |
3981 | /* R6 implies 64-bit float registers. */ | |
3982 | file_mips_opts.fp = 64; | |
919731af | 3983 | else |
3984 | /* 32-bit float registers. */ | |
3985 | file_mips_opts.fp = 32; | |
3986 | } | |
3987 | ||
3988 | arch_info = mips_cpu_info_from_arch (file_mips_opts.arch); | |
3989 | ||
351cdf24 MF |
3990 | /* Disable operations on odd-numbered floating-point registers by default |
3991 | when using the FPXX ABI. */ | |
3992 | if (file_mips_opts.oddspreg < 0) | |
3993 | { | |
3994 | if (file_mips_opts.fp == 0) | |
3995 | file_mips_opts.oddspreg = 0; | |
3996 | else | |
3997 | file_mips_opts.oddspreg = 1; | |
3998 | } | |
3999 | ||
919731af | 4000 | /* End of GCC-shared inference code. */ |
4001 | ||
4002 | /* This flag is set when we have a 64-bit capable CPU but use only | |
4003 | 32-bit wide registers. Note that EABI does not use it. */ | |
4004 | if (ISA_HAS_64BIT_REGS (file_mips_opts.isa) | |
4005 | && ((mips_abi == NO_ABI && file_mips_opts.gp == 32) | |
4006 | || mips_abi == O32_ABI)) | |
4007 | mips_32bitmode = 1; | |
4008 | ||
4009 | if (file_mips_opts.isa == ISA_MIPS1 && mips_trap) | |
4010 | as_bad (_("trap exception not supported at ISA 1")); | |
4011 | ||
4012 | /* If the selected architecture includes support for ASEs, enable | |
4013 | generation of code for them. */ | |
4014 | if (file_mips_opts.mips16 == -1) | |
4015 | file_mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_opts.arch)) ? 1 : 0; | |
4016 | if (file_mips_opts.micromips == -1) | |
4017 | file_mips_opts.micromips = (CPU_HAS_MICROMIPS (file_mips_opts.arch)) | |
4018 | ? 1 : 0; | |
4019 | ||
7361da2c AB |
4020 | if (mips_nan2008 == -1) |
4021 | mips_nan2008 = (ISA_HAS_LEGACY_NAN (file_mips_opts.isa)) ? 0 : 1; | |
4022 | else if (!ISA_HAS_LEGACY_NAN (file_mips_opts.isa) && mips_nan2008 == 0) | |
4023 | as_fatal (_("`%s' does not support legacy NaN"), | |
4024 | mips_cpu_info_from_arch (file_mips_opts.arch)->name); | |
4025 | ||
919731af | 4026 | /* Some ASEs require 64-bit FPRs, so -mfp32 should stop those ASEs from |
4027 | being selected implicitly. */ | |
4028 | if (file_mips_opts.fp != 64) | |
4029 | file_ase_explicit |= ASE_MIPS3D | ASE_MDMX | ASE_MSA; | |
4030 | ||
4031 | /* If the user didn't explicitly select or deselect a particular ASE, | |
4032 | use the default setting for the CPU. */ | |
4033 | file_mips_opts.ase |= (arch_info->ase & ~file_ase_explicit); | |
4034 | ||
4035 | /* Set up the current options. These may change throughout assembly. */ | |
4036 | mips_opts = file_mips_opts; | |
4037 | ||
4038 | mips_check_isa_supports_ases (); | |
4039 | mips_check_options (&file_mips_opts, TRUE); | |
4040 | file_mips_opts_checked = TRUE; | |
4041 | ||
4042 | if (!bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_opts.arch)) | |
4043 | as_warn (_("could not set architecture and machine")); | |
4044 | } | |
4045 | ||
252b5132 | 4046 | void |
17a2f251 | 4047 | md_assemble (char *str) |
252b5132 RH |
4048 | { |
4049 | struct mips_cl_insn insn; | |
f6688943 TS |
4050 | bfd_reloc_code_real_type unused_reloc[3] |
4051 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 4052 | |
919731af | 4053 | file_mips_check_options (); |
4054 | ||
252b5132 | 4055 | imm_expr.X_op = O_absent; |
252b5132 | 4056 | offset_expr.X_op = O_absent; |
f6688943 TS |
4057 | offset_reloc[0] = BFD_RELOC_UNUSED; |
4058 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
4059 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 | 4060 | |
e1b47bd5 RS |
4061 | mips_mark_labels (); |
4062 | mips_assembling_insn = TRUE; | |
e3de51ce | 4063 | clear_insn_error (); |
e1b47bd5 | 4064 | |
252b5132 RH |
4065 | if (mips_opts.mips16) |
4066 | mips16_ip (str, &insn); | |
4067 | else | |
4068 | { | |
4069 | mips_ip (str, &insn); | |
beae10d5 KH |
4070 | DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"), |
4071 | str, insn.insn_opcode)); | |
252b5132 RH |
4072 | } |
4073 | ||
e3de51ce RS |
4074 | if (insn_error.msg) |
4075 | report_insn_error (str); | |
e1b47bd5 | 4076 | else if (insn.insn_mo->pinfo == INSN_MACRO) |
252b5132 | 4077 | { |
584892a6 | 4078 | macro_start (); |
252b5132 RH |
4079 | if (mips_opts.mips16) |
4080 | mips16_macro (&insn); | |
4081 | else | |
833794fc | 4082 | macro (&insn, str); |
584892a6 | 4083 | macro_end (); |
252b5132 RH |
4084 | } |
4085 | else | |
4086 | { | |
77bd4346 | 4087 | if (offset_expr.X_op != O_absent) |
df58fc94 | 4088 | append_insn (&insn, &offset_expr, offset_reloc, FALSE); |
252b5132 | 4089 | else |
df58fc94 | 4090 | append_insn (&insn, NULL, unused_reloc, FALSE); |
252b5132 | 4091 | } |
e1b47bd5 RS |
4092 | |
4093 | mips_assembling_insn = FALSE; | |
252b5132 RH |
4094 | } |
4095 | ||
738e5348 RS |
4096 | /* Convenience functions for abstracting away the differences between |
4097 | MIPS16 and non-MIPS16 relocations. */ | |
4098 | ||
4099 | static inline bfd_boolean | |
4100 | mips16_reloc_p (bfd_reloc_code_real_type reloc) | |
4101 | { | |
4102 | switch (reloc) | |
4103 | { | |
4104 | case BFD_RELOC_MIPS16_JMP: | |
4105 | case BFD_RELOC_MIPS16_GPREL: | |
4106 | case BFD_RELOC_MIPS16_GOT16: | |
4107 | case BFD_RELOC_MIPS16_CALL16: | |
4108 | case BFD_RELOC_MIPS16_HI16_S: | |
4109 | case BFD_RELOC_MIPS16_HI16: | |
4110 | case BFD_RELOC_MIPS16_LO16: | |
c9775dde | 4111 | case BFD_RELOC_MIPS16_16_PCREL_S1: |
738e5348 RS |
4112 | return TRUE; |
4113 | ||
4114 | default: | |
4115 | return FALSE; | |
4116 | } | |
4117 | } | |
4118 | ||
df58fc94 RS |
4119 | static inline bfd_boolean |
4120 | micromips_reloc_p (bfd_reloc_code_real_type reloc) | |
4121 | { | |
4122 | switch (reloc) | |
4123 | { | |
4124 | case BFD_RELOC_MICROMIPS_7_PCREL_S1: | |
4125 | case BFD_RELOC_MICROMIPS_10_PCREL_S1: | |
4126 | case BFD_RELOC_MICROMIPS_16_PCREL_S1: | |
4127 | case BFD_RELOC_MICROMIPS_GPREL16: | |
4128 | case BFD_RELOC_MICROMIPS_JMP: | |
4129 | case BFD_RELOC_MICROMIPS_HI16: | |
4130 | case BFD_RELOC_MICROMIPS_HI16_S: | |
4131 | case BFD_RELOC_MICROMIPS_LO16: | |
4132 | case BFD_RELOC_MICROMIPS_LITERAL: | |
4133 | case BFD_RELOC_MICROMIPS_GOT16: | |
4134 | case BFD_RELOC_MICROMIPS_CALL16: | |
4135 | case BFD_RELOC_MICROMIPS_GOT_HI16: | |
4136 | case BFD_RELOC_MICROMIPS_GOT_LO16: | |
4137 | case BFD_RELOC_MICROMIPS_CALL_HI16: | |
4138 | case BFD_RELOC_MICROMIPS_CALL_LO16: | |
4139 | case BFD_RELOC_MICROMIPS_SUB: | |
4140 | case BFD_RELOC_MICROMIPS_GOT_PAGE: | |
4141 | case BFD_RELOC_MICROMIPS_GOT_OFST: | |
4142 | case BFD_RELOC_MICROMIPS_GOT_DISP: | |
4143 | case BFD_RELOC_MICROMIPS_HIGHEST: | |
4144 | case BFD_RELOC_MICROMIPS_HIGHER: | |
4145 | case BFD_RELOC_MICROMIPS_SCN_DISP: | |
4146 | case BFD_RELOC_MICROMIPS_JALR: | |
4147 | return TRUE; | |
4148 | ||
4149 | default: | |
4150 | return FALSE; | |
4151 | } | |
4152 | } | |
4153 | ||
2309ddf2 MR |
4154 | static inline bfd_boolean |
4155 | jmp_reloc_p (bfd_reloc_code_real_type reloc) | |
4156 | { | |
4157 | return reloc == BFD_RELOC_MIPS_JMP || reloc == BFD_RELOC_MICROMIPS_JMP; | |
4158 | } | |
4159 | ||
0e9c5a5c MR |
4160 | static inline bfd_boolean |
4161 | b_reloc_p (bfd_reloc_code_real_type reloc) | |
4162 | { | |
4163 | return (reloc == BFD_RELOC_MIPS_26_PCREL_S2 | |
4164 | || reloc == BFD_RELOC_MIPS_21_PCREL_S2 | |
4165 | || reloc == BFD_RELOC_16_PCREL_S2 | |
c9775dde | 4166 | || reloc == BFD_RELOC_MIPS16_16_PCREL_S1 |
0e9c5a5c MR |
4167 | || reloc == BFD_RELOC_MICROMIPS_16_PCREL_S1 |
4168 | || reloc == BFD_RELOC_MICROMIPS_10_PCREL_S1 | |
4169 | || reloc == BFD_RELOC_MICROMIPS_7_PCREL_S1); | |
4170 | } | |
4171 | ||
738e5348 RS |
4172 | static inline bfd_boolean |
4173 | got16_reloc_p (bfd_reloc_code_real_type reloc) | |
4174 | { | |
2309ddf2 | 4175 | return (reloc == BFD_RELOC_MIPS_GOT16 || reloc == BFD_RELOC_MIPS16_GOT16 |
df58fc94 | 4176 | || reloc == BFD_RELOC_MICROMIPS_GOT16); |
738e5348 RS |
4177 | } |
4178 | ||
4179 | static inline bfd_boolean | |
4180 | hi16_reloc_p (bfd_reloc_code_real_type reloc) | |
4181 | { | |
2309ddf2 | 4182 | return (reloc == BFD_RELOC_HI16_S || reloc == BFD_RELOC_MIPS16_HI16_S |
df58fc94 | 4183 | || reloc == BFD_RELOC_MICROMIPS_HI16_S); |
738e5348 RS |
4184 | } |
4185 | ||
4186 | static inline bfd_boolean | |
4187 | lo16_reloc_p (bfd_reloc_code_real_type reloc) | |
4188 | { | |
2309ddf2 | 4189 | return (reloc == BFD_RELOC_LO16 || reloc == BFD_RELOC_MIPS16_LO16 |
df58fc94 RS |
4190 | || reloc == BFD_RELOC_MICROMIPS_LO16); |
4191 | } | |
4192 | ||
df58fc94 RS |
4193 | static inline bfd_boolean |
4194 | jalr_reloc_p (bfd_reloc_code_real_type reloc) | |
4195 | { | |
2309ddf2 | 4196 | return reloc == BFD_RELOC_MIPS_JALR || reloc == BFD_RELOC_MICROMIPS_JALR; |
738e5348 RS |
4197 | } |
4198 | ||
f2ae14a1 RS |
4199 | static inline bfd_boolean |
4200 | gprel16_reloc_p (bfd_reloc_code_real_type reloc) | |
4201 | { | |
4202 | return (reloc == BFD_RELOC_GPREL16 || reloc == BFD_RELOC_MIPS16_GPREL | |
4203 | || reloc == BFD_RELOC_MICROMIPS_GPREL16); | |
4204 | } | |
4205 | ||
2de39019 CM |
4206 | /* Return true if RELOC is a PC-relative relocation that does not have |
4207 | full address range. */ | |
4208 | ||
4209 | static inline bfd_boolean | |
4210 | limited_pcrel_reloc_p (bfd_reloc_code_real_type reloc) | |
4211 | { | |
4212 | switch (reloc) | |
4213 | { | |
4214 | case BFD_RELOC_16_PCREL_S2: | |
c9775dde | 4215 | case BFD_RELOC_MIPS16_16_PCREL_S1: |
2de39019 CM |
4216 | case BFD_RELOC_MICROMIPS_7_PCREL_S1: |
4217 | case BFD_RELOC_MICROMIPS_10_PCREL_S1: | |
4218 | case BFD_RELOC_MICROMIPS_16_PCREL_S1: | |
7361da2c AB |
4219 | case BFD_RELOC_MIPS_21_PCREL_S2: |
4220 | case BFD_RELOC_MIPS_26_PCREL_S2: | |
4221 | case BFD_RELOC_MIPS_18_PCREL_S3: | |
4222 | case BFD_RELOC_MIPS_19_PCREL_S2: | |
2de39019 CM |
4223 | return TRUE; |
4224 | ||
b47468a6 | 4225 | case BFD_RELOC_32_PCREL: |
7361da2c AB |
4226 | case BFD_RELOC_HI16_S_PCREL: |
4227 | case BFD_RELOC_LO16_PCREL: | |
b47468a6 CM |
4228 | return HAVE_64BIT_ADDRESSES; |
4229 | ||
2de39019 CM |
4230 | default: |
4231 | return FALSE; | |
4232 | } | |
4233 | } | |
b47468a6 | 4234 | |
5919d012 | 4235 | /* Return true if the given relocation might need a matching %lo(). |
0a44bf69 RS |
4236 | This is only "might" because SVR4 R_MIPS_GOT16 relocations only |
4237 | need a matching %lo() when applied to local symbols. */ | |
5919d012 RS |
4238 | |
4239 | static inline bfd_boolean | |
17a2f251 | 4240 | reloc_needs_lo_p (bfd_reloc_code_real_type reloc) |
5919d012 | 4241 | { |
3b91255e | 4242 | return (HAVE_IN_PLACE_ADDENDS |
738e5348 | 4243 | && (hi16_reloc_p (reloc) |
0a44bf69 RS |
4244 | /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo(); |
4245 | all GOT16 relocations evaluate to "G". */ | |
738e5348 RS |
4246 | || (got16_reloc_p (reloc) && mips_pic != VXWORKS_PIC))); |
4247 | } | |
4248 | ||
4249 | /* Return the type of %lo() reloc needed by RELOC, given that | |
4250 | reloc_needs_lo_p. */ | |
4251 | ||
4252 | static inline bfd_reloc_code_real_type | |
4253 | matching_lo_reloc (bfd_reloc_code_real_type reloc) | |
4254 | { | |
df58fc94 RS |
4255 | return (mips16_reloc_p (reloc) ? BFD_RELOC_MIPS16_LO16 |
4256 | : (micromips_reloc_p (reloc) ? BFD_RELOC_MICROMIPS_LO16 | |
4257 | : BFD_RELOC_LO16)); | |
5919d012 RS |
4258 | } |
4259 | ||
4260 | /* Return true if the given fixup is followed by a matching R_MIPS_LO16 | |
4261 | relocation. */ | |
4262 | ||
4263 | static inline bfd_boolean | |
17a2f251 | 4264 | fixup_has_matching_lo_p (fixS *fixp) |
5919d012 RS |
4265 | { |
4266 | return (fixp->fx_next != NULL | |
738e5348 | 4267 | && fixp->fx_next->fx_r_type == matching_lo_reloc (fixp->fx_r_type) |
5919d012 RS |
4268 | && fixp->fx_addsy == fixp->fx_next->fx_addsy |
4269 | && fixp->fx_offset == fixp->fx_next->fx_offset); | |
4270 | } | |
4271 | ||
462427c4 RS |
4272 | /* Move all labels in LABELS to the current insertion point. TEXT_P |
4273 | says whether the labels refer to text or data. */ | |
404a8071 RS |
4274 | |
4275 | static void | |
462427c4 | 4276 | mips_move_labels (struct insn_label_list *labels, bfd_boolean text_p) |
404a8071 RS |
4277 | { |
4278 | struct insn_label_list *l; | |
4279 | valueT val; | |
4280 | ||
462427c4 | 4281 | for (l = labels; l != NULL; l = l->next) |
404a8071 | 4282 | { |
9c2799c2 | 4283 | gas_assert (S_GET_SEGMENT (l->label) == now_seg); |
404a8071 RS |
4284 | symbol_set_frag (l->label, frag_now); |
4285 | val = (valueT) frag_now_fix (); | |
df58fc94 | 4286 | /* MIPS16/microMIPS text labels are stored as odd. */ |
462427c4 | 4287 | if (text_p && HAVE_CODE_COMPRESSION) |
404a8071 RS |
4288 | ++val; |
4289 | S_SET_VALUE (l->label, val); | |
4290 | } | |
4291 | } | |
4292 | ||
462427c4 RS |
4293 | /* Move all labels in insn_labels to the current insertion point |
4294 | and treat them as text labels. */ | |
4295 | ||
4296 | static void | |
4297 | mips_move_text_labels (void) | |
4298 | { | |
4299 | mips_move_labels (seg_info (now_seg)->label_list, TRUE); | |
4300 | } | |
4301 | ||
9e009953 MR |
4302 | /* Duplicate the test for LINK_ONCE sections as in `adjust_reloc_syms'. */ |
4303 | ||
5f0fe04b TS |
4304 | static bfd_boolean |
4305 | s_is_linkonce (symbolS *sym, segT from_seg) | |
4306 | { | |
4307 | bfd_boolean linkonce = FALSE; | |
4308 | segT symseg = S_GET_SEGMENT (sym); | |
4309 | ||
4310 | if (symseg != from_seg && !S_IS_LOCAL (sym)) | |
4311 | { | |
4312 | if ((bfd_get_section_flags (stdoutput, symseg) & SEC_LINK_ONCE)) | |
4313 | linkonce = TRUE; | |
5f0fe04b TS |
4314 | /* The GNU toolchain uses an extension for ELF: a section |
4315 | beginning with the magic string .gnu.linkonce is a | |
4316 | linkonce section. */ | |
4317 | if (strncmp (segment_name (symseg), ".gnu.linkonce", | |
4318 | sizeof ".gnu.linkonce" - 1) == 0) | |
4319 | linkonce = TRUE; | |
5f0fe04b TS |
4320 | } |
4321 | return linkonce; | |
4322 | } | |
4323 | ||
e1b47bd5 | 4324 | /* Mark MIPS16 or microMIPS instruction label LABEL. This permits the |
df58fc94 RS |
4325 | linker to handle them specially, such as generating jalx instructions |
4326 | when needed. We also make them odd for the duration of the assembly, | |
4327 | in order to generate the right sort of code. We will make them even | |
252b5132 RH |
4328 | in the adjust_symtab routine, while leaving them marked. This is |
4329 | convenient for the debugger and the disassembler. The linker knows | |
4330 | to make them odd again. */ | |
4331 | ||
4332 | static void | |
e1b47bd5 | 4333 | mips_compressed_mark_label (symbolS *label) |
252b5132 | 4334 | { |
df58fc94 | 4335 | gas_assert (HAVE_CODE_COMPRESSION); |
a8dbcb85 | 4336 | |
f3ded42a RS |
4337 | if (mips_opts.mips16) |
4338 | S_SET_OTHER (label, ELF_ST_SET_MIPS16 (S_GET_OTHER (label))); | |
4339 | else | |
4340 | S_SET_OTHER (label, ELF_ST_SET_MICROMIPS (S_GET_OTHER (label))); | |
e1b47bd5 RS |
4341 | if ((S_GET_VALUE (label) & 1) == 0 |
4342 | /* Don't adjust the address if the label is global or weak, or | |
4343 | in a link-once section, since we'll be emitting symbol reloc | |
4344 | references to it which will be patched up by the linker, and | |
4345 | the final value of the symbol may or may not be MIPS16/microMIPS. */ | |
4346 | && !S_IS_WEAK (label) | |
4347 | && !S_IS_EXTERNAL (label) | |
4348 | && !s_is_linkonce (label, now_seg)) | |
4349 | S_SET_VALUE (label, S_GET_VALUE (label) | 1); | |
4350 | } | |
4351 | ||
4352 | /* Mark preceding MIPS16 or microMIPS instruction labels. */ | |
4353 | ||
4354 | static void | |
4355 | mips_compressed_mark_labels (void) | |
4356 | { | |
4357 | struct insn_label_list *l; | |
4358 | ||
4359 | for (l = seg_info (now_seg)->label_list; l != NULL; l = l->next) | |
4360 | mips_compressed_mark_label (l->label); | |
252b5132 RH |
4361 | } |
4362 | ||
4d7206a2 RS |
4363 | /* End the current frag. Make it a variant frag and record the |
4364 | relaxation info. */ | |
4365 | ||
4366 | static void | |
4367 | relax_close_frag (void) | |
4368 | { | |
584892a6 | 4369 | mips_macro_warning.first_frag = frag_now; |
4d7206a2 | 4370 | frag_var (rs_machine_dependent, 0, 0, |
ce8ad872 MR |
4371 | RELAX_ENCODE (mips_relax.sizes[0], mips_relax.sizes[1], |
4372 | mips_pic != NO_PIC), | |
4d7206a2 RS |
4373 | mips_relax.symbol, 0, (char *) mips_relax.first_fixup); |
4374 | ||
4375 | memset (&mips_relax.sizes, 0, sizeof (mips_relax.sizes)); | |
4376 | mips_relax.first_fixup = 0; | |
4377 | } | |
4378 | ||
4379 | /* Start a new relaxation sequence whose expansion depends on SYMBOL. | |
4380 | See the comment above RELAX_ENCODE for more details. */ | |
4381 | ||
4382 | static void | |
4383 | relax_start (symbolS *symbol) | |
4384 | { | |
9c2799c2 | 4385 | gas_assert (mips_relax.sequence == 0); |
4d7206a2 RS |
4386 | mips_relax.sequence = 1; |
4387 | mips_relax.symbol = symbol; | |
4388 | } | |
4389 | ||
4390 | /* Start generating the second version of a relaxable sequence. | |
4391 | See the comment above RELAX_ENCODE for more details. */ | |
252b5132 RH |
4392 | |
4393 | static void | |
4d7206a2 RS |
4394 | relax_switch (void) |
4395 | { | |
9c2799c2 | 4396 | gas_assert (mips_relax.sequence == 1); |
4d7206a2 RS |
4397 | mips_relax.sequence = 2; |
4398 | } | |
4399 | ||
4400 | /* End the current relaxable sequence. */ | |
4401 | ||
4402 | static void | |
4403 | relax_end (void) | |
4404 | { | |
9c2799c2 | 4405 | gas_assert (mips_relax.sequence == 2); |
4d7206a2 RS |
4406 | relax_close_frag (); |
4407 | mips_relax.sequence = 0; | |
4408 | } | |
4409 | ||
11625dd8 RS |
4410 | /* Return true if IP is a delayed branch or jump. */ |
4411 | ||
4412 | static inline bfd_boolean | |
4413 | delayed_branch_p (const struct mips_cl_insn *ip) | |
4414 | { | |
4415 | return (ip->insn_mo->pinfo & (INSN_UNCOND_BRANCH_DELAY | |
4416 | | INSN_COND_BRANCH_DELAY | |
4417 | | INSN_COND_BRANCH_LIKELY)) != 0; | |
4418 | } | |
4419 | ||
4420 | /* Return true if IP is a compact branch or jump. */ | |
4421 | ||
4422 | static inline bfd_boolean | |
4423 | compact_branch_p (const struct mips_cl_insn *ip) | |
4424 | { | |
26545944 RS |
4425 | return (ip->insn_mo->pinfo2 & (INSN2_UNCOND_BRANCH |
4426 | | INSN2_COND_BRANCH)) != 0; | |
11625dd8 RS |
4427 | } |
4428 | ||
4429 | /* Return true if IP is an unconditional branch or jump. */ | |
4430 | ||
4431 | static inline bfd_boolean | |
4432 | uncond_branch_p (const struct mips_cl_insn *ip) | |
4433 | { | |
4434 | return ((ip->insn_mo->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0 | |
26545944 | 4435 | || (ip->insn_mo->pinfo2 & INSN2_UNCOND_BRANCH) != 0); |
11625dd8 RS |
4436 | } |
4437 | ||
4438 | /* Return true if IP is a branch-likely instruction. */ | |
4439 | ||
4440 | static inline bfd_boolean | |
4441 | branch_likely_p (const struct mips_cl_insn *ip) | |
4442 | { | |
4443 | return (ip->insn_mo->pinfo & INSN_COND_BRANCH_LIKELY) != 0; | |
4444 | } | |
4445 | ||
14fe068b RS |
4446 | /* Return the type of nop that should be used to fill the delay slot |
4447 | of delayed branch IP. */ | |
4448 | ||
4449 | static struct mips_cl_insn * | |
4450 | get_delay_slot_nop (const struct mips_cl_insn *ip) | |
4451 | { | |
4452 | if (mips_opts.micromips | |
4453 | && (ip->insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) | |
4454 | return µmips_nop32_insn; | |
4455 | return NOP_INSN; | |
4456 | } | |
4457 | ||
fc76e730 RS |
4458 | /* Return a mask that has bit N set if OPCODE reads the register(s) |
4459 | in operand N. */ | |
df58fc94 RS |
4460 | |
4461 | static unsigned int | |
fc76e730 | 4462 | insn_read_mask (const struct mips_opcode *opcode) |
df58fc94 | 4463 | { |
fc76e730 RS |
4464 | return (opcode->pinfo & INSN_READ_ALL) >> INSN_READ_SHIFT; |
4465 | } | |
df58fc94 | 4466 | |
fc76e730 RS |
4467 | /* Return a mask that has bit N set if OPCODE writes to the register(s) |
4468 | in operand N. */ | |
4469 | ||
4470 | static unsigned int | |
4471 | insn_write_mask (const struct mips_opcode *opcode) | |
4472 | { | |
4473 | return (opcode->pinfo & INSN_WRITE_ALL) >> INSN_WRITE_SHIFT; | |
4474 | } | |
4475 | ||
4476 | /* Return a mask of the registers specified by operand OPERAND of INSN. | |
4477 | Ignore registers of type OP_REG_<t> unless bit OP_REG_<t> of TYPE_MASK | |
4478 | is set. */ | |
4479 | ||
4480 | static unsigned int | |
4481 | operand_reg_mask (const struct mips_cl_insn *insn, | |
4482 | const struct mips_operand *operand, | |
4483 | unsigned int type_mask) | |
4484 | { | |
4485 | unsigned int uval, vsel; | |
4486 | ||
4487 | switch (operand->type) | |
df58fc94 | 4488 | { |
fc76e730 RS |
4489 | case OP_INT: |
4490 | case OP_MAPPED_INT: | |
4491 | case OP_MSB: | |
4492 | case OP_PCREL: | |
4493 | case OP_PERF_REG: | |
4494 | case OP_ADDIUSP_INT: | |
4495 | case OP_ENTRY_EXIT_LIST: | |
4496 | case OP_REPEAT_DEST_REG: | |
4497 | case OP_REPEAT_PREV_REG: | |
4498 | case OP_PC: | |
14daeee3 RS |
4499 | case OP_VU0_SUFFIX: |
4500 | case OP_VU0_MATCH_SUFFIX: | |
56d438b1 | 4501 | case OP_IMM_INDEX: |
fc76e730 RS |
4502 | abort (); |
4503 | ||
4504 | case OP_REG: | |
0f35dbc4 | 4505 | case OP_OPTIONAL_REG: |
fc76e730 RS |
4506 | { |
4507 | const struct mips_reg_operand *reg_op; | |
4508 | ||
4509 | reg_op = (const struct mips_reg_operand *) operand; | |
4510 | if (!(type_mask & (1 << reg_op->reg_type))) | |
4511 | return 0; | |
4512 | uval = insn_extract_operand (insn, operand); | |
4513 | return 1 << mips_decode_reg_operand (reg_op, uval); | |
4514 | } | |
4515 | ||
4516 | case OP_REG_PAIR: | |
4517 | { | |
4518 | const struct mips_reg_pair_operand *pair_op; | |
4519 | ||
4520 | pair_op = (const struct mips_reg_pair_operand *) operand; | |
4521 | if (!(type_mask & (1 << pair_op->reg_type))) | |
4522 | return 0; | |
4523 | uval = insn_extract_operand (insn, operand); | |
4524 | return (1 << pair_op->reg1_map[uval]) | (1 << pair_op->reg2_map[uval]); | |
4525 | } | |
4526 | ||
4527 | case OP_CLO_CLZ_DEST: | |
4528 | if (!(type_mask & (1 << OP_REG_GP))) | |
4529 | return 0; | |
4530 | uval = insn_extract_operand (insn, operand); | |
4531 | return (1 << (uval & 31)) | (1 << (uval >> 5)); | |
4532 | ||
7361da2c AB |
4533 | case OP_SAME_RS_RT: |
4534 | if (!(type_mask & (1 << OP_REG_GP))) | |
4535 | return 0; | |
4536 | uval = insn_extract_operand (insn, operand); | |
4537 | gas_assert ((uval & 31) == (uval >> 5)); | |
4538 | return 1 << (uval & 31); | |
4539 | ||
4540 | case OP_CHECK_PREV: | |
4541 | case OP_NON_ZERO_REG: | |
4542 | if (!(type_mask & (1 << OP_REG_GP))) | |
4543 | return 0; | |
4544 | uval = insn_extract_operand (insn, operand); | |
4545 | return 1 << (uval & 31); | |
4546 | ||
fc76e730 RS |
4547 | case OP_LWM_SWM_LIST: |
4548 | abort (); | |
4549 | ||
4550 | case OP_SAVE_RESTORE_LIST: | |
4551 | abort (); | |
4552 | ||
4553 | case OP_MDMX_IMM_REG: | |
4554 | if (!(type_mask & (1 << OP_REG_VEC))) | |
4555 | return 0; | |
4556 | uval = insn_extract_operand (insn, operand); | |
4557 | vsel = uval >> 5; | |
4558 | if ((vsel & 0x18) == 0x18) | |
4559 | return 0; | |
4560 | return 1 << (uval & 31); | |
56d438b1 CF |
4561 | |
4562 | case OP_REG_INDEX: | |
4563 | if (!(type_mask & (1 << OP_REG_GP))) | |
4564 | return 0; | |
4565 | return 1 << insn_extract_operand (insn, operand); | |
df58fc94 | 4566 | } |
fc76e730 RS |
4567 | abort (); |
4568 | } | |
4569 | ||
4570 | /* Return a mask of the registers specified by operands OPNO_MASK of INSN, | |
4571 | where bit N of OPNO_MASK is set if operand N should be included. | |
4572 | Ignore registers of type OP_REG_<t> unless bit OP_REG_<t> of TYPE_MASK | |
4573 | is set. */ | |
4574 | ||
4575 | static unsigned int | |
4576 | insn_reg_mask (const struct mips_cl_insn *insn, | |
4577 | unsigned int type_mask, unsigned int opno_mask) | |
4578 | { | |
4579 | unsigned int opno, reg_mask; | |
4580 | ||
4581 | opno = 0; | |
4582 | reg_mask = 0; | |
4583 | while (opno_mask != 0) | |
4584 | { | |
4585 | if (opno_mask & 1) | |
4586 | reg_mask |= operand_reg_mask (insn, insn_opno (insn, opno), type_mask); | |
4587 | opno_mask >>= 1; | |
4588 | opno += 1; | |
4589 | } | |
4590 | return reg_mask; | |
df58fc94 RS |
4591 | } |
4592 | ||
4c260379 RS |
4593 | /* Return the mask of core registers that IP reads. */ |
4594 | ||
4595 | static unsigned int | |
4596 | gpr_read_mask (const struct mips_cl_insn *ip) | |
4597 | { | |
4598 | unsigned long pinfo, pinfo2; | |
4599 | unsigned int mask; | |
4600 | ||
fc76e730 | 4601 | mask = insn_reg_mask (ip, 1 << OP_REG_GP, insn_read_mask (ip->insn_mo)); |
4c260379 RS |
4602 | pinfo = ip->insn_mo->pinfo; |
4603 | pinfo2 = ip->insn_mo->pinfo2; | |
fc76e730 | 4604 | if (pinfo & INSN_UDI) |
4c260379 | 4605 | { |
fc76e730 RS |
4606 | /* UDI instructions have traditionally been assumed to read RS |
4607 | and RT. */ | |
4608 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RT, *ip); | |
4609 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RS, *ip); | |
4c260379 | 4610 | } |
fc76e730 RS |
4611 | if (pinfo & INSN_READ_GPR_24) |
4612 | mask |= 1 << 24; | |
4613 | if (pinfo2 & INSN2_READ_GPR_16) | |
4614 | mask |= 1 << 16; | |
4615 | if (pinfo2 & INSN2_READ_SP) | |
4616 | mask |= 1 << SP; | |
26545944 | 4617 | if (pinfo2 & INSN2_READ_GPR_31) |
fc76e730 | 4618 | mask |= 1 << 31; |
fe35f09f RS |
4619 | /* Don't include register 0. */ |
4620 | return mask & ~1; | |
4c260379 RS |
4621 | } |
4622 | ||
4623 | /* Return the mask of core registers that IP writes. */ | |
4624 | ||
4625 | static unsigned int | |
4626 | gpr_write_mask (const struct mips_cl_insn *ip) | |
4627 | { | |
4628 | unsigned long pinfo, pinfo2; | |
4629 | unsigned int mask; | |
4630 | ||
fc76e730 | 4631 | mask = insn_reg_mask (ip, 1 << OP_REG_GP, insn_write_mask (ip->insn_mo)); |
4c260379 RS |
4632 | pinfo = ip->insn_mo->pinfo; |
4633 | pinfo2 = ip->insn_mo->pinfo2; | |
fc76e730 RS |
4634 | if (pinfo & INSN_WRITE_GPR_24) |
4635 | mask |= 1 << 24; | |
4636 | if (pinfo & INSN_WRITE_GPR_31) | |
4637 | mask |= 1 << 31; | |
4638 | if (pinfo & INSN_UDI) | |
4639 | /* UDI instructions have traditionally been assumed to write to RD. */ | |
4640 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RD, *ip); | |
4641 | if (pinfo2 & INSN2_WRITE_SP) | |
4642 | mask |= 1 << SP; | |
fe35f09f RS |
4643 | /* Don't include register 0. */ |
4644 | return mask & ~1; | |
4c260379 RS |
4645 | } |
4646 | ||
4647 | /* Return the mask of floating-point registers that IP reads. */ | |
4648 | ||
4649 | static unsigned int | |
4650 | fpr_read_mask (const struct mips_cl_insn *ip) | |
4651 | { | |
fc76e730 | 4652 | unsigned long pinfo; |
4c260379 RS |
4653 | unsigned int mask; |
4654 | ||
9d5de888 CF |
4655 | mask = insn_reg_mask (ip, ((1 << OP_REG_FP) | (1 << OP_REG_VEC) |
4656 | | (1 << OP_REG_MSA)), | |
fc76e730 | 4657 | insn_read_mask (ip->insn_mo)); |
4c260379 | 4658 | pinfo = ip->insn_mo->pinfo; |
4c260379 RS |
4659 | /* Conservatively treat all operands to an FP_D instruction are doubles. |
4660 | (This is overly pessimistic for things like cvt.d.s.) */ | |
bad1aba3 | 4661 | if (FPR_SIZE != 64 && (pinfo & FP_D)) |
4c260379 RS |
4662 | mask |= mask << 1; |
4663 | return mask; | |
4664 | } | |
4665 | ||
4666 | /* Return the mask of floating-point registers that IP writes. */ | |
4667 | ||
4668 | static unsigned int | |
4669 | fpr_write_mask (const struct mips_cl_insn *ip) | |
4670 | { | |
fc76e730 | 4671 | unsigned long pinfo; |
4c260379 RS |
4672 | unsigned int mask; |
4673 | ||
9d5de888 CF |
4674 | mask = insn_reg_mask (ip, ((1 << OP_REG_FP) | (1 << OP_REG_VEC) |
4675 | | (1 << OP_REG_MSA)), | |
fc76e730 | 4676 | insn_write_mask (ip->insn_mo)); |
4c260379 | 4677 | pinfo = ip->insn_mo->pinfo; |
4c260379 RS |
4678 | /* Conservatively treat all operands to an FP_D instruction are doubles. |
4679 | (This is overly pessimistic for things like cvt.s.d.) */ | |
bad1aba3 | 4680 | if (FPR_SIZE != 64 && (pinfo & FP_D)) |
4c260379 RS |
4681 | mask |= mask << 1; |
4682 | return mask; | |
4683 | } | |
4684 | ||
a1d78564 RS |
4685 | /* Operand OPNUM of INSN is an odd-numbered floating-point register. |
4686 | Check whether that is allowed. */ | |
4687 | ||
4688 | static bfd_boolean | |
4689 | mips_oddfpreg_ok (const struct mips_opcode *insn, int opnum) | |
4690 | { | |
4691 | const char *s = insn->name; | |
351cdf24 MF |
4692 | bfd_boolean oddspreg = (ISA_HAS_ODD_SINGLE_FPR (mips_opts.isa, mips_opts.arch) |
4693 | || FPR_SIZE == 64) | |
4694 | && mips_opts.oddspreg; | |
a1d78564 RS |
4695 | |
4696 | if (insn->pinfo == INSN_MACRO) | |
4697 | /* Let a macro pass, we'll catch it later when it is expanded. */ | |
4698 | return TRUE; | |
4699 | ||
351cdf24 MF |
4700 | /* Single-precision coprocessor loads and moves are OK for 32-bit registers, |
4701 | otherwise it depends on oddspreg. */ | |
4702 | if ((insn->pinfo & FP_S) | |
4703 | && (insn->pinfo & (INSN_LOAD_MEMORY | INSN_STORE_MEMORY | |
43885403 | 4704 | | INSN_LOAD_COPROC | INSN_COPROC_MOVE))) |
351cdf24 | 4705 | return FPR_SIZE == 32 || oddspreg; |
a1d78564 | 4706 | |
351cdf24 MF |
4707 | /* Allow odd registers for single-precision ops and double-precision if the |
4708 | floating-point registers are 64-bit wide. */ | |
4709 | switch (insn->pinfo & (FP_S | FP_D)) | |
4710 | { | |
4711 | case FP_S: | |
4712 | case 0: | |
4713 | return oddspreg; | |
4714 | case FP_D: | |
4715 | return FPR_SIZE == 64; | |
4716 | default: | |
4717 | break; | |
a1d78564 RS |
4718 | } |
4719 | ||
351cdf24 MF |
4720 | /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */ |
4721 | s = strchr (insn->name, '.'); | |
4722 | if (s != NULL && opnum == 2) | |
4723 | s = strchr (s + 1, '.'); | |
4724 | if (s != NULL && (s[1] == 'w' || s[1] == 's')) | |
4725 | return oddspreg; | |
a1d78564 | 4726 | |
351cdf24 | 4727 | return FPR_SIZE == 64; |
a1d78564 RS |
4728 | } |
4729 | ||
a1d78564 RS |
4730 | /* Information about an instruction argument that we're trying to match. */ |
4731 | struct mips_arg_info | |
4732 | { | |
4733 | /* The instruction so far. */ | |
4734 | struct mips_cl_insn *insn; | |
4735 | ||
a92713e6 RS |
4736 | /* The first unconsumed operand token. */ |
4737 | struct mips_operand_token *token; | |
4738 | ||
a1d78564 RS |
4739 | /* The 1-based operand number, in terms of insn->insn_mo->args. */ |
4740 | int opnum; | |
4741 | ||
4742 | /* The 1-based argument number, for error reporting. This does not | |
4743 | count elided optional registers, etc.. */ | |
4744 | int argnum; | |
4745 | ||
4746 | /* The last OP_REG operand seen, or ILLEGAL_REG if none. */ | |
4747 | unsigned int last_regno; | |
4748 | ||
4749 | /* If the first operand was an OP_REG, this is the register that it | |
4750 | specified, otherwise it is ILLEGAL_REG. */ | |
4751 | unsigned int dest_regno; | |
4752 | ||
4753 | /* The value of the last OP_INT operand. Only used for OP_MSB, | |
4754 | where it gives the lsb position. */ | |
4755 | unsigned int last_op_int; | |
4756 | ||
60f20e8b | 4757 | /* If true, match routines should assume that no later instruction |
2b0f3761 | 4758 | alternative matches and should therefore be as accommodating as |
60f20e8b RS |
4759 | possible. Match routines should not report errors if something |
4760 | is only invalid for !LAX_MATCH. */ | |
4761 | bfd_boolean lax_match; | |
a1d78564 | 4762 | |
a1d78564 RS |
4763 | /* True if a reference to the current AT register was seen. */ |
4764 | bfd_boolean seen_at; | |
4765 | }; | |
4766 | ||
1a00e612 RS |
4767 | /* Record that the argument is out of range. */ |
4768 | ||
4769 | static void | |
4770 | match_out_of_range (struct mips_arg_info *arg) | |
4771 | { | |
4772 | set_insn_error_i (arg->argnum, _("operand %d out of range"), arg->argnum); | |
4773 | } | |
4774 | ||
4775 | /* Record that the argument isn't constant but needs to be. */ | |
4776 | ||
4777 | static void | |
4778 | match_not_constant (struct mips_arg_info *arg) | |
4779 | { | |
4780 | set_insn_error_i (arg->argnum, _("operand %d must be constant"), | |
4781 | arg->argnum); | |
4782 | } | |
4783 | ||
a92713e6 RS |
4784 | /* Try to match an OT_CHAR token for character CH. Consume the token |
4785 | and return true on success, otherwise return false. */ | |
a1d78564 | 4786 | |
a92713e6 RS |
4787 | static bfd_boolean |
4788 | match_char (struct mips_arg_info *arg, char ch) | |
a1d78564 | 4789 | { |
a92713e6 RS |
4790 | if (arg->token->type == OT_CHAR && arg->token->u.ch == ch) |
4791 | { | |
4792 | ++arg->token; | |
4793 | if (ch == ',') | |
4794 | arg->argnum += 1; | |
4795 | return TRUE; | |
4796 | } | |
4797 | return FALSE; | |
4798 | } | |
a1d78564 | 4799 | |
a92713e6 RS |
4800 | /* Try to get an expression from the next tokens in ARG. Consume the |
4801 | tokens and return true on success, storing the expression value in | |
4802 | VALUE and relocation types in R. */ | |
4803 | ||
4804 | static bfd_boolean | |
4805 | match_expression (struct mips_arg_info *arg, expressionS *value, | |
4806 | bfd_reloc_code_real_type *r) | |
4807 | { | |
d436c1c2 RS |
4808 | /* If the next token is a '(' that was parsed as being part of a base |
4809 | expression, assume we have an elided offset. The later match will fail | |
4810 | if this turns out to be wrong. */ | |
4811 | if (arg->token->type == OT_CHAR && arg->token->u.ch == '(') | |
a1d78564 | 4812 | { |
d436c1c2 RS |
4813 | value->X_op = O_constant; |
4814 | value->X_add_number = 0; | |
4815 | r[0] = r[1] = r[2] = BFD_RELOC_UNUSED; | |
a92713e6 RS |
4816 | return TRUE; |
4817 | } | |
4818 | ||
d436c1c2 RS |
4819 | /* Reject register-based expressions such as "0+$2" and "(($2))". |
4820 | For plain registers the default error seems more appropriate. */ | |
4821 | if (arg->token->type == OT_INTEGER | |
4822 | && arg->token->u.integer.value.X_op == O_register) | |
a92713e6 | 4823 | { |
d436c1c2 RS |
4824 | set_insn_error (arg->argnum, _("register value used as expression")); |
4825 | return FALSE; | |
a1d78564 | 4826 | } |
d436c1c2 RS |
4827 | |
4828 | if (arg->token->type == OT_INTEGER) | |
a92713e6 | 4829 | { |
d436c1c2 RS |
4830 | *value = arg->token->u.integer.value; |
4831 | memcpy (r, arg->token->u.integer.relocs, 3 * sizeof (*r)); | |
4832 | ++arg->token; | |
4833 | return TRUE; | |
a92713e6 | 4834 | } |
a92713e6 | 4835 | |
d436c1c2 RS |
4836 | set_insn_error_i |
4837 | (arg->argnum, _("operand %d must be an immediate expression"), | |
4838 | arg->argnum); | |
4839 | return FALSE; | |
a92713e6 RS |
4840 | } |
4841 | ||
4842 | /* Try to get a constant expression from the next tokens in ARG. Consume | |
4843 | the tokens and return return true on success, storing the constant value | |
a54d5f8b | 4844 | in *VALUE. */ |
a92713e6 RS |
4845 | |
4846 | static bfd_boolean | |
1a00e612 | 4847 | match_const_int (struct mips_arg_info *arg, offsetT *value) |
a92713e6 RS |
4848 | { |
4849 | expressionS ex; | |
4850 | bfd_reloc_code_real_type r[3]; | |
a1d78564 | 4851 | |
a92713e6 RS |
4852 | if (!match_expression (arg, &ex, r)) |
4853 | return FALSE; | |
4854 | ||
4855 | if (r[0] == BFD_RELOC_UNUSED && ex.X_op == O_constant) | |
a1d78564 RS |
4856 | *value = ex.X_add_number; |
4857 | else | |
4858 | { | |
1a00e612 RS |
4859 | match_not_constant (arg); |
4860 | return FALSE; | |
a1d78564 | 4861 | } |
a92713e6 | 4862 | return TRUE; |
a1d78564 RS |
4863 | } |
4864 | ||
4865 | /* Return the RTYPE_* flags for a register operand of type TYPE that | |
4866 | appears in instruction OPCODE. */ | |
4867 | ||
4868 | static unsigned int | |
4869 | convert_reg_type (const struct mips_opcode *opcode, | |
4870 | enum mips_reg_operand_type type) | |
4871 | { | |
4872 | switch (type) | |
4873 | { | |
4874 | case OP_REG_GP: | |
4875 | return RTYPE_NUM | RTYPE_GP; | |
4876 | ||
4877 | case OP_REG_FP: | |
4878 | /* Allow vector register names for MDMX if the instruction is a 64-bit | |
4879 | FPR load, store or move (including moves to and from GPRs). */ | |
4880 | if ((mips_opts.ase & ASE_MDMX) | |
4881 | && (opcode->pinfo & FP_D) | |
43885403 | 4882 | && (opcode->pinfo & (INSN_COPROC_MOVE |
a1d78564 | 4883 | | INSN_COPROC_MEMORY_DELAY |
43885403 | 4884 | | INSN_LOAD_COPROC |
67dc82bc | 4885 | | INSN_LOAD_MEMORY |
a1d78564 RS |
4886 | | INSN_STORE_MEMORY))) |
4887 | return RTYPE_FPU | RTYPE_VEC; | |
4888 | return RTYPE_FPU; | |
4889 | ||
4890 | case OP_REG_CCC: | |
4891 | if (opcode->pinfo & (FP_D | FP_S)) | |
4892 | return RTYPE_CCC | RTYPE_FCC; | |
4893 | return RTYPE_CCC; | |
4894 | ||
4895 | case OP_REG_VEC: | |
4896 | if (opcode->membership & INSN_5400) | |
4897 | return RTYPE_FPU; | |
4898 | return RTYPE_FPU | RTYPE_VEC; | |
4899 | ||
4900 | case OP_REG_ACC: | |
4901 | return RTYPE_ACC; | |
4902 | ||
4903 | case OP_REG_COPRO: | |
4904 | if (opcode->name[strlen (opcode->name) - 1] == '0') | |
4905 | return RTYPE_NUM | RTYPE_CP0; | |
4906 | return RTYPE_NUM; | |
4907 | ||
4908 | case OP_REG_HW: | |
4909 | return RTYPE_NUM; | |
14daeee3 RS |
4910 | |
4911 | case OP_REG_VI: | |
4912 | return RTYPE_NUM | RTYPE_VI; | |
4913 | ||
4914 | case OP_REG_VF: | |
4915 | return RTYPE_NUM | RTYPE_VF; | |
4916 | ||
4917 | case OP_REG_R5900_I: | |
4918 | return RTYPE_R5900_I; | |
4919 | ||
4920 | case OP_REG_R5900_Q: | |
4921 | return RTYPE_R5900_Q; | |
4922 | ||
4923 | case OP_REG_R5900_R: | |
4924 | return RTYPE_R5900_R; | |
4925 | ||
4926 | case OP_REG_R5900_ACC: | |
4927 | return RTYPE_R5900_ACC; | |
56d438b1 CF |
4928 | |
4929 | case OP_REG_MSA: | |
4930 | return RTYPE_MSA; | |
4931 | ||
4932 | case OP_REG_MSA_CTRL: | |
4933 | return RTYPE_NUM; | |
a1d78564 RS |
4934 | } |
4935 | abort (); | |
4936 | } | |
4937 | ||
4938 | /* ARG is register REGNO, of type TYPE. Warn about any dubious registers. */ | |
4939 | ||
4940 | static void | |
4941 | check_regno (struct mips_arg_info *arg, | |
4942 | enum mips_reg_operand_type type, unsigned int regno) | |
4943 | { | |
4944 | if (AT && type == OP_REG_GP && regno == AT) | |
4945 | arg->seen_at = TRUE; | |
4946 | ||
4947 | if (type == OP_REG_FP | |
4948 | && (regno & 1) != 0 | |
a1d78564 | 4949 | && !mips_oddfpreg_ok (arg->insn->insn_mo, arg->opnum)) |
351cdf24 MF |
4950 | { |
4951 | /* This was a warning prior to introducing O32 FPXX and FP64 support | |
4952 | so maintain a warning for FP32 but raise an error for the new | |
4953 | cases. */ | |
4954 | if (FPR_SIZE == 32) | |
4955 | as_warn (_("float register should be even, was %d"), regno); | |
4956 | else | |
4957 | as_bad (_("float register should be even, was %d"), regno); | |
4958 | } | |
a1d78564 RS |
4959 | |
4960 | if (type == OP_REG_CCC) | |
4961 | { | |
4962 | const char *name; | |
4963 | size_t length; | |
4964 | ||
4965 | name = arg->insn->insn_mo->name; | |
4966 | length = strlen (name); | |
4967 | if ((regno & 1) != 0 | |
4968 | && ((length >= 3 && strcmp (name + length - 3, ".ps") == 0) | |
4969 | || (length >= 5 && strncmp (name + length - 5, "any2", 4) == 0))) | |
1661c76c | 4970 | as_warn (_("condition code register should be even for %s, was %d"), |
a1d78564 RS |
4971 | name, regno); |
4972 | ||
4973 | if ((regno & 3) != 0 | |
4974 | && (length >= 5 && strncmp (name + length - 5, "any4", 4) == 0)) | |
1661c76c | 4975 | as_warn (_("condition code register should be 0 or 4 for %s, was %d"), |
a1d78564 RS |
4976 | name, regno); |
4977 | } | |
4978 | } | |
4979 | ||
a92713e6 RS |
4980 | /* ARG is a register with symbol value SYMVAL. Try to interpret it as |
4981 | a register of type TYPE. Return true on success, storing the register | |
4982 | number in *REGNO and warning about any dubious uses. */ | |
4983 | ||
4984 | static bfd_boolean | |
4985 | match_regno (struct mips_arg_info *arg, enum mips_reg_operand_type type, | |
4986 | unsigned int symval, unsigned int *regno) | |
4987 | { | |
4988 | if (type == OP_REG_VEC) | |
4989 | symval = mips_prefer_vec_regno (symval); | |
4990 | if (!(symval & convert_reg_type (arg->insn->insn_mo, type))) | |
4991 | return FALSE; | |
4992 | ||
4993 | *regno = symval & RNUM_MASK; | |
4994 | check_regno (arg, type, *regno); | |
4995 | return TRUE; | |
4996 | } | |
4997 | ||
4998 | /* Try to interpret the next token in ARG as a register of type TYPE. | |
4999 | Consume the token and return true on success, storing the register | |
5000 | number in *REGNO. Return false on failure. */ | |
5001 | ||
5002 | static bfd_boolean | |
5003 | match_reg (struct mips_arg_info *arg, enum mips_reg_operand_type type, | |
5004 | unsigned int *regno) | |
5005 | { | |
5006 | if (arg->token->type == OT_REG | |
5007 | && match_regno (arg, type, arg->token->u.regno, regno)) | |
5008 | { | |
5009 | ++arg->token; | |
5010 | return TRUE; | |
5011 | } | |
5012 | return FALSE; | |
5013 | } | |
5014 | ||
5015 | /* Try to interpret the next token in ARG as a range of registers of type TYPE. | |
5016 | Consume the token and return true on success, storing the register numbers | |
5017 | in *REGNO1 and *REGNO2. Return false on failure. */ | |
5018 | ||
5019 | static bfd_boolean | |
5020 | match_reg_range (struct mips_arg_info *arg, enum mips_reg_operand_type type, | |
5021 | unsigned int *regno1, unsigned int *regno2) | |
5022 | { | |
5023 | if (match_reg (arg, type, regno1)) | |
5024 | { | |
5025 | *regno2 = *regno1; | |
5026 | return TRUE; | |
5027 | } | |
5028 | if (arg->token->type == OT_REG_RANGE | |
5029 | && match_regno (arg, type, arg->token->u.reg_range.regno1, regno1) | |
5030 | && match_regno (arg, type, arg->token->u.reg_range.regno2, regno2) | |
5031 | && *regno1 <= *regno2) | |
5032 | { | |
5033 | ++arg->token; | |
5034 | return TRUE; | |
5035 | } | |
5036 | return FALSE; | |
5037 | } | |
5038 | ||
a1d78564 RS |
5039 | /* OP_INT matcher. */ |
5040 | ||
a92713e6 | 5041 | static bfd_boolean |
a1d78564 | 5042 | match_int_operand (struct mips_arg_info *arg, |
a92713e6 | 5043 | const struct mips_operand *operand_base) |
a1d78564 RS |
5044 | { |
5045 | const struct mips_int_operand *operand; | |
3ccad066 | 5046 | unsigned int uval; |
a1d78564 RS |
5047 | int min_val, max_val, factor; |
5048 | offsetT sval; | |
a1d78564 RS |
5049 | |
5050 | operand = (const struct mips_int_operand *) operand_base; | |
5051 | factor = 1 << operand->shift; | |
3ccad066 RS |
5052 | min_val = mips_int_operand_min (operand); |
5053 | max_val = mips_int_operand_max (operand); | |
a1d78564 | 5054 | |
d436c1c2 RS |
5055 | if (operand_base->lsb == 0 |
5056 | && operand_base->size == 16 | |
5057 | && operand->shift == 0 | |
5058 | && operand->bias == 0 | |
5059 | && (operand->max_val == 32767 || operand->max_val == 65535)) | |
a1d78564 RS |
5060 | { |
5061 | /* The operand can be relocated. */ | |
a92713e6 RS |
5062 | if (!match_expression (arg, &offset_expr, offset_reloc)) |
5063 | return FALSE; | |
5064 | ||
5065 | if (offset_reloc[0] != BFD_RELOC_UNUSED) | |
33eaf5de | 5066 | /* Relocation operators were used. Accept the argument and |
a1d78564 RS |
5067 | leave the relocation value in offset_expr and offset_relocs |
5068 | for the caller to process. */ | |
a92713e6 RS |
5069 | return TRUE; |
5070 | ||
5071 | if (offset_expr.X_op != O_constant) | |
a1d78564 | 5072 | { |
60f20e8b RS |
5073 | /* Accept non-constant operands if no later alternative matches, |
5074 | leaving it for the caller to process. */ | |
5075 | if (!arg->lax_match) | |
5076 | return FALSE; | |
a92713e6 RS |
5077 | offset_reloc[0] = BFD_RELOC_LO16; |
5078 | return TRUE; | |
a1d78564 | 5079 | } |
a92713e6 | 5080 | |
a1d78564 RS |
5081 | /* Clear the global state; we're going to install the operand |
5082 | ourselves. */ | |
a92713e6 | 5083 | sval = offset_expr.X_add_number; |
a1d78564 | 5084 | offset_expr.X_op = O_absent; |
60f20e8b RS |
5085 | |
5086 | /* For compatibility with older assemblers, we accept | |
5087 | 0x8000-0xffff as signed 16-bit numbers when only | |
5088 | signed numbers are allowed. */ | |
5089 | if (sval > max_val) | |
5090 | { | |
5091 | max_val = ((1 << operand_base->size) - 1) << operand->shift; | |
5092 | if (!arg->lax_match && sval <= max_val) | |
5093 | return FALSE; | |
5094 | } | |
a1d78564 RS |
5095 | } |
5096 | else | |
5097 | { | |
1a00e612 | 5098 | if (!match_const_int (arg, &sval)) |
a92713e6 | 5099 | return FALSE; |
a1d78564 RS |
5100 | } |
5101 | ||
5102 | arg->last_op_int = sval; | |
5103 | ||
1a00e612 | 5104 | if (sval < min_val || sval > max_val || sval % factor) |
a1d78564 | 5105 | { |
1a00e612 RS |
5106 | match_out_of_range (arg); |
5107 | return FALSE; | |
a1d78564 RS |
5108 | } |
5109 | ||
5110 | uval = (unsigned int) sval >> operand->shift; | |
5111 | uval -= operand->bias; | |
5112 | ||
5113 | /* Handle -mfix-cn63xxp1. */ | |
5114 | if (arg->opnum == 1 | |
5115 | && mips_fix_cn63xxp1 | |
5116 | && !mips_opts.micromips | |
5117 | && strcmp ("pref", arg->insn->insn_mo->name) == 0) | |
5118 | switch (uval) | |
5119 | { | |
5120 | case 5: | |
5121 | case 25: | |
5122 | case 26: | |
5123 | case 27: | |
5124 | case 28: | |
5125 | case 29: | |
5126 | case 30: | |
5127 | case 31: | |
5128 | /* These are ok. */ | |
5129 | break; | |
5130 | ||
5131 | default: | |
5132 | /* The rest must be changed to 28. */ | |
5133 | uval = 28; | |
5134 | break; | |
5135 | } | |
5136 | ||
5137 | insn_insert_operand (arg->insn, operand_base, uval); | |
a92713e6 | 5138 | return TRUE; |
a1d78564 RS |
5139 | } |
5140 | ||
5141 | /* OP_MAPPED_INT matcher. */ | |
5142 | ||
a92713e6 | 5143 | static bfd_boolean |
a1d78564 | 5144 | match_mapped_int_operand (struct mips_arg_info *arg, |
a92713e6 | 5145 | const struct mips_operand *operand_base) |
a1d78564 RS |
5146 | { |
5147 | const struct mips_mapped_int_operand *operand; | |
5148 | unsigned int uval, num_vals; | |
5149 | offsetT sval; | |
5150 | ||
5151 | operand = (const struct mips_mapped_int_operand *) operand_base; | |
1a00e612 | 5152 | if (!match_const_int (arg, &sval)) |
a92713e6 | 5153 | return FALSE; |
a1d78564 RS |
5154 | |
5155 | num_vals = 1 << operand_base->size; | |
5156 | for (uval = 0; uval < num_vals; uval++) | |
5157 | if (operand->int_map[uval] == sval) | |
5158 | break; | |
5159 | if (uval == num_vals) | |
1a00e612 RS |
5160 | { |
5161 | match_out_of_range (arg); | |
5162 | return FALSE; | |
5163 | } | |
a1d78564 RS |
5164 | |
5165 | insn_insert_operand (arg->insn, operand_base, uval); | |
a92713e6 | 5166 | return TRUE; |
a1d78564 RS |
5167 | } |
5168 | ||
5169 | /* OP_MSB matcher. */ | |
5170 | ||
a92713e6 | 5171 | static bfd_boolean |
a1d78564 | 5172 | match_msb_operand (struct mips_arg_info *arg, |
a92713e6 | 5173 | const struct mips_operand *operand_base) |
a1d78564 RS |
5174 | { |
5175 | const struct mips_msb_operand *operand; | |
5176 | int min_val, max_val, max_high; | |
5177 | offsetT size, sval, high; | |
5178 | ||
5179 | operand = (const struct mips_msb_operand *) operand_base; | |
5180 | min_val = operand->bias; | |
5181 | max_val = min_val + (1 << operand_base->size) - 1; | |
5182 | max_high = operand->opsize; | |
5183 | ||
1a00e612 | 5184 | if (!match_const_int (arg, &size)) |
a92713e6 | 5185 | return FALSE; |
a1d78564 RS |
5186 | |
5187 | high = size + arg->last_op_int; | |
5188 | sval = operand->add_lsb ? high : size; | |
5189 | ||
5190 | if (size < 0 || high > max_high || sval < min_val || sval > max_val) | |
5191 | { | |
1a00e612 RS |
5192 | match_out_of_range (arg); |
5193 | return FALSE; | |
a1d78564 RS |
5194 | } |
5195 | insn_insert_operand (arg->insn, operand_base, sval - min_val); | |
a92713e6 | 5196 | return TRUE; |
a1d78564 RS |
5197 | } |
5198 | ||
5199 | /* OP_REG matcher. */ | |
5200 | ||
a92713e6 | 5201 | static bfd_boolean |
a1d78564 | 5202 | match_reg_operand (struct mips_arg_info *arg, |
a92713e6 | 5203 | const struct mips_operand *operand_base) |
a1d78564 RS |
5204 | { |
5205 | const struct mips_reg_operand *operand; | |
a92713e6 | 5206 | unsigned int regno, uval, num_vals; |
a1d78564 RS |
5207 | |
5208 | operand = (const struct mips_reg_operand *) operand_base; | |
a92713e6 RS |
5209 | if (!match_reg (arg, operand->reg_type, ®no)) |
5210 | return FALSE; | |
a1d78564 RS |
5211 | |
5212 | if (operand->reg_map) | |
5213 | { | |
5214 | num_vals = 1 << operand->root.size; | |
5215 | for (uval = 0; uval < num_vals; uval++) | |
5216 | if (operand->reg_map[uval] == regno) | |
5217 | break; | |
5218 | if (num_vals == uval) | |
a92713e6 | 5219 | return FALSE; |
a1d78564 RS |
5220 | } |
5221 | else | |
5222 | uval = regno; | |
5223 | ||
a1d78564 RS |
5224 | arg->last_regno = regno; |
5225 | if (arg->opnum == 1) | |
5226 | arg->dest_regno = regno; | |
5227 | insn_insert_operand (arg->insn, operand_base, uval); | |
a92713e6 | 5228 | return TRUE; |
a1d78564 RS |
5229 | } |
5230 | ||
5231 | /* OP_REG_PAIR matcher. */ | |
5232 | ||
a92713e6 | 5233 | static bfd_boolean |
a1d78564 | 5234 | match_reg_pair_operand (struct mips_arg_info *arg, |
a92713e6 | 5235 | const struct mips_operand *operand_base) |
a1d78564 RS |
5236 | { |
5237 | const struct mips_reg_pair_operand *operand; | |
a92713e6 | 5238 | unsigned int regno1, regno2, uval, num_vals; |
a1d78564 RS |
5239 | |
5240 | operand = (const struct mips_reg_pair_operand *) operand_base; | |
a92713e6 RS |
5241 | if (!match_reg (arg, operand->reg_type, ®no1) |
5242 | || !match_char (arg, ',') | |
5243 | || !match_reg (arg, operand->reg_type, ®no2)) | |
5244 | return FALSE; | |
a1d78564 RS |
5245 | |
5246 | num_vals = 1 << operand_base->size; | |
5247 | for (uval = 0; uval < num_vals; uval++) | |
5248 | if (operand->reg1_map[uval] == regno1 && operand->reg2_map[uval] == regno2) | |
5249 | break; | |
5250 | if (uval == num_vals) | |
a92713e6 | 5251 | return FALSE; |
a1d78564 | 5252 | |
a1d78564 | 5253 | insn_insert_operand (arg->insn, operand_base, uval); |
a92713e6 | 5254 | return TRUE; |
a1d78564 RS |
5255 | } |
5256 | ||
5257 | /* OP_PCREL matcher. The caller chooses the relocation type. */ | |
5258 | ||
a92713e6 RS |
5259 | static bfd_boolean |
5260 | match_pcrel_operand (struct mips_arg_info *arg) | |
a1d78564 | 5261 | { |
a92713e6 RS |
5262 | bfd_reloc_code_real_type r[3]; |
5263 | ||
5264 | return match_expression (arg, &offset_expr, r) && r[0] == BFD_RELOC_UNUSED; | |
a1d78564 RS |
5265 | } |
5266 | ||
5267 | /* OP_PERF_REG matcher. */ | |
5268 | ||
a92713e6 | 5269 | static bfd_boolean |
a1d78564 | 5270 | match_perf_reg_operand (struct mips_arg_info *arg, |
a92713e6 | 5271 | const struct mips_operand *operand) |
a1d78564 RS |
5272 | { |
5273 | offsetT sval; | |
5274 | ||
1a00e612 | 5275 | if (!match_const_int (arg, &sval)) |
a92713e6 | 5276 | return FALSE; |
a1d78564 RS |
5277 | |
5278 | if (sval != 0 | |
5279 | && (sval != 1 | |
5280 | || (mips_opts.arch == CPU_R5900 | |
5281 | && (strcmp (arg->insn->insn_mo->name, "mfps") == 0 | |
5282 | || strcmp (arg->insn->insn_mo->name, "mtps") == 0)))) | |
5283 | { | |
1a00e612 RS |
5284 | set_insn_error (arg->argnum, _("invalid performance register")); |
5285 | return FALSE; | |
a1d78564 RS |
5286 | } |
5287 | ||
5288 | insn_insert_operand (arg->insn, operand, sval); | |
a92713e6 | 5289 | return TRUE; |
a1d78564 RS |
5290 | } |
5291 | ||
5292 | /* OP_ADDIUSP matcher. */ | |
5293 | ||
a92713e6 | 5294 | static bfd_boolean |
a1d78564 | 5295 | match_addiusp_operand (struct mips_arg_info *arg, |
a92713e6 | 5296 | const struct mips_operand *operand) |
a1d78564 RS |
5297 | { |
5298 | offsetT sval; | |
5299 | unsigned int uval; | |
5300 | ||
1a00e612 | 5301 | if (!match_const_int (arg, &sval)) |
a92713e6 | 5302 | return FALSE; |
a1d78564 RS |
5303 | |
5304 | if (sval % 4) | |
1a00e612 RS |
5305 | { |
5306 | match_out_of_range (arg); | |
5307 | return FALSE; | |
5308 | } | |
a1d78564 RS |
5309 | |
5310 | sval /= 4; | |
5311 | if (!(sval >= -258 && sval <= 257) || (sval >= -2 && sval <= 1)) | |
1a00e612 RS |
5312 | { |
5313 | match_out_of_range (arg); | |
5314 | return FALSE; | |
5315 | } | |
a1d78564 RS |
5316 | |
5317 | uval = (unsigned int) sval; | |
5318 | uval = ((uval >> 1) & ~0xff) | (uval & 0xff); | |
5319 | insn_insert_operand (arg->insn, operand, uval); | |
a92713e6 | 5320 | return TRUE; |
a1d78564 RS |
5321 | } |
5322 | ||
5323 | /* OP_CLO_CLZ_DEST matcher. */ | |
5324 | ||
a92713e6 | 5325 | static bfd_boolean |
a1d78564 | 5326 | match_clo_clz_dest_operand (struct mips_arg_info *arg, |
a92713e6 | 5327 | const struct mips_operand *operand) |
a1d78564 RS |
5328 | { |
5329 | unsigned int regno; | |
5330 | ||
a92713e6 RS |
5331 | if (!match_reg (arg, OP_REG_GP, ®no)) |
5332 | return FALSE; | |
a1d78564 | 5333 | |
a1d78564 | 5334 | insn_insert_operand (arg->insn, operand, regno | (regno << 5)); |
a92713e6 | 5335 | return TRUE; |
a1d78564 RS |
5336 | } |
5337 | ||
7361da2c AB |
5338 | /* OP_CHECK_PREV matcher. */ |
5339 | ||
5340 | static bfd_boolean | |
5341 | match_check_prev_operand (struct mips_arg_info *arg, | |
5342 | const struct mips_operand *operand_base) | |
5343 | { | |
5344 | const struct mips_check_prev_operand *operand; | |
5345 | unsigned int regno; | |
5346 | ||
5347 | operand = (const struct mips_check_prev_operand *) operand_base; | |
5348 | ||
5349 | if (!match_reg (arg, OP_REG_GP, ®no)) | |
5350 | return FALSE; | |
5351 | ||
5352 | if (!operand->zero_ok && regno == 0) | |
5353 | return FALSE; | |
5354 | ||
5355 | if ((operand->less_than_ok && regno < arg->last_regno) | |
5356 | || (operand->greater_than_ok && regno > arg->last_regno) | |
5357 | || (operand->equal_ok && regno == arg->last_regno)) | |
5358 | { | |
5359 | arg->last_regno = regno; | |
5360 | insn_insert_operand (arg->insn, operand_base, regno); | |
5361 | return TRUE; | |
5362 | } | |
5363 | ||
5364 | return FALSE; | |
5365 | } | |
5366 | ||
5367 | /* OP_SAME_RS_RT matcher. */ | |
5368 | ||
5369 | static bfd_boolean | |
5370 | match_same_rs_rt_operand (struct mips_arg_info *arg, | |
5371 | const struct mips_operand *operand) | |
5372 | { | |
5373 | unsigned int regno; | |
5374 | ||
5375 | if (!match_reg (arg, OP_REG_GP, ®no)) | |
5376 | return FALSE; | |
5377 | ||
5378 | if (regno == 0) | |
5379 | { | |
5380 | set_insn_error (arg->argnum, _("the source register must not be $0")); | |
5381 | return FALSE; | |
5382 | } | |
5383 | ||
5384 | arg->last_regno = regno; | |
5385 | ||
5386 | insn_insert_operand (arg->insn, operand, regno | (regno << 5)); | |
5387 | return TRUE; | |
5388 | } | |
5389 | ||
a1d78564 RS |
5390 | /* OP_LWM_SWM_LIST matcher. */ |
5391 | ||
a92713e6 | 5392 | static bfd_boolean |
a1d78564 | 5393 | match_lwm_swm_list_operand (struct mips_arg_info *arg, |
a92713e6 | 5394 | const struct mips_operand *operand) |
a1d78564 | 5395 | { |
a92713e6 RS |
5396 | unsigned int reglist, sregs, ra, regno1, regno2; |
5397 | struct mips_arg_info reset; | |
a1d78564 | 5398 | |
a92713e6 RS |
5399 | reglist = 0; |
5400 | if (!match_reg_range (arg, OP_REG_GP, ®no1, ®no2)) | |
5401 | return FALSE; | |
5402 | do | |
5403 | { | |
5404 | if (regno2 == FP && regno1 >= S0 && regno1 <= S7) | |
5405 | { | |
5406 | reglist |= 1 << FP; | |
5407 | regno2 = S7; | |
5408 | } | |
5409 | reglist |= ((1U << regno2 << 1) - 1) & -(1U << regno1); | |
5410 | reset = *arg; | |
5411 | } | |
5412 | while (match_char (arg, ',') | |
5413 | && match_reg_range (arg, OP_REG_GP, ®no1, ®no2)); | |
5414 | *arg = reset; | |
a1d78564 RS |
5415 | |
5416 | if (operand->size == 2) | |
5417 | { | |
5418 | /* The list must include both ra and s0-sN, for 0 <= N <= 3. E.g.: | |
5419 | ||
5420 | s0, ra | |
5421 | s0, s1, ra, s2, s3 | |
5422 | s0-s2, ra | |
5423 | ||
5424 | and any permutations of these. */ | |
5425 | if ((reglist & 0xfff1ffff) != 0x80010000) | |
a92713e6 | 5426 | return FALSE; |
a1d78564 RS |
5427 | |
5428 | sregs = (reglist >> 17) & 7; | |
5429 | ra = 0; | |
5430 | } | |
5431 | else | |
5432 | { | |
5433 | /* The list must include at least one of ra and s0-sN, | |
5434 | for 0 <= N <= 8. (Note that there is a gap between s7 and s8, | |
5435 | which are $23 and $30 respectively.) E.g.: | |
5436 | ||
5437 | ra | |
5438 | s0 | |
5439 | ra, s0, s1, s2 | |
5440 | s0-s8 | |
5441 | s0-s5, ra | |
5442 | ||
5443 | and any permutations of these. */ | |
5444 | if ((reglist & 0x3f00ffff) != 0) | |
a92713e6 | 5445 | return FALSE; |
a1d78564 RS |
5446 | |
5447 | ra = (reglist >> 27) & 0x10; | |
5448 | sregs = ((reglist >> 22) & 0x100) | ((reglist >> 16) & 0xff); | |
5449 | } | |
5450 | sregs += 1; | |
5451 | if ((sregs & -sregs) != sregs) | |
a92713e6 | 5452 | return FALSE; |
a1d78564 RS |
5453 | |
5454 | insn_insert_operand (arg->insn, operand, (ffs (sregs) - 1) | ra); | |
a92713e6 | 5455 | return TRUE; |
a1d78564 RS |
5456 | } |
5457 | ||
364215c8 RS |
5458 | /* OP_ENTRY_EXIT_LIST matcher. */ |
5459 | ||
a92713e6 | 5460 | static unsigned int |
364215c8 | 5461 | match_entry_exit_operand (struct mips_arg_info *arg, |
a92713e6 | 5462 | const struct mips_operand *operand) |
364215c8 RS |
5463 | { |
5464 | unsigned int mask; | |
5465 | bfd_boolean is_exit; | |
5466 | ||
5467 | /* The format is the same for both ENTRY and EXIT, but the constraints | |
5468 | are different. */ | |
5469 | is_exit = strcmp (arg->insn->insn_mo->name, "exit") == 0; | |
5470 | mask = (is_exit ? 7 << 3 : 0); | |
a92713e6 | 5471 | do |
364215c8 RS |
5472 | { |
5473 | unsigned int regno1, regno2; | |
5474 | bfd_boolean is_freg; | |
5475 | ||
a92713e6 | 5476 | if (match_reg_range (arg, OP_REG_GP, ®no1, ®no2)) |
364215c8 | 5477 | is_freg = FALSE; |
a92713e6 | 5478 | else if (match_reg_range (arg, OP_REG_FP, ®no1, ®no2)) |
364215c8 RS |
5479 | is_freg = TRUE; |
5480 | else | |
a92713e6 | 5481 | return FALSE; |
364215c8 RS |
5482 | |
5483 | if (is_exit && is_freg && regno1 == 0 && regno2 < 2) | |
5484 | { | |
5485 | mask &= ~(7 << 3); | |
5486 | mask |= (5 + regno2) << 3; | |
5487 | } | |
5488 | else if (!is_exit && regno1 == 4 && regno2 >= 4 && regno2 <= 7) | |
5489 | mask |= (regno2 - 3) << 3; | |
5490 | else if (regno1 == 16 && regno2 >= 16 && regno2 <= 17) | |
5491 | mask |= (regno2 - 15) << 1; | |
5492 | else if (regno1 == RA && regno2 == RA) | |
5493 | mask |= 1; | |
5494 | else | |
a92713e6 | 5495 | return FALSE; |
364215c8 | 5496 | } |
a92713e6 RS |
5497 | while (match_char (arg, ',')); |
5498 | ||
364215c8 | 5499 | insn_insert_operand (arg->insn, operand, mask); |
a92713e6 | 5500 | return TRUE; |
364215c8 RS |
5501 | } |
5502 | ||
5503 | /* OP_SAVE_RESTORE_LIST matcher. */ | |
5504 | ||
a92713e6 RS |
5505 | static bfd_boolean |
5506 | match_save_restore_list_operand (struct mips_arg_info *arg) | |
364215c8 RS |
5507 | { |
5508 | unsigned int opcode, args, statics, sregs; | |
5509 | unsigned int num_frame_sizes, num_args, num_statics, num_sregs; | |
364215c8 | 5510 | offsetT frame_size; |
364215c8 | 5511 | |
364215c8 RS |
5512 | opcode = arg->insn->insn_opcode; |
5513 | frame_size = 0; | |
5514 | num_frame_sizes = 0; | |
5515 | args = 0; | |
5516 | statics = 0; | |
5517 | sregs = 0; | |
a92713e6 | 5518 | do |
364215c8 RS |
5519 | { |
5520 | unsigned int regno1, regno2; | |
5521 | ||
a92713e6 | 5522 | if (arg->token->type == OT_INTEGER) |
364215c8 RS |
5523 | { |
5524 | /* Handle the frame size. */ | |
1a00e612 | 5525 | if (!match_const_int (arg, &frame_size)) |
a92713e6 | 5526 | return FALSE; |
364215c8 | 5527 | num_frame_sizes += 1; |
364215c8 RS |
5528 | } |
5529 | else | |
5530 | { | |
a92713e6 RS |
5531 | if (!match_reg_range (arg, OP_REG_GP, ®no1, ®no2)) |
5532 | return FALSE; | |
364215c8 RS |
5533 | |
5534 | while (regno1 <= regno2) | |
5535 | { | |
5536 | if (regno1 >= 4 && regno1 <= 7) | |
5537 | { | |
5538 | if (num_frame_sizes == 0) | |
5539 | /* args $a0-$a3 */ | |
5540 | args |= 1 << (regno1 - 4); | |
5541 | else | |
5542 | /* statics $a0-$a3 */ | |
5543 | statics |= 1 << (regno1 - 4); | |
5544 | } | |
5545 | else if (regno1 >= 16 && regno1 <= 23) | |
5546 | /* $s0-$s7 */ | |
5547 | sregs |= 1 << (regno1 - 16); | |
5548 | else if (regno1 == 30) | |
5549 | /* $s8 */ | |
5550 | sregs |= 1 << 8; | |
5551 | else if (regno1 == 31) | |
5552 | /* Add $ra to insn. */ | |
5553 | opcode |= 0x40; | |
5554 | else | |
a92713e6 | 5555 | return FALSE; |
364215c8 RS |
5556 | regno1 += 1; |
5557 | if (regno1 == 24) | |
5558 | regno1 = 30; | |
5559 | } | |
5560 | } | |
364215c8 | 5561 | } |
a92713e6 | 5562 | while (match_char (arg, ',')); |
364215c8 RS |
5563 | |
5564 | /* Encode args/statics combination. */ | |
5565 | if (args & statics) | |
a92713e6 | 5566 | return FALSE; |
364215c8 RS |
5567 | else if (args == 0xf) |
5568 | /* All $a0-$a3 are args. */ | |
5569 | opcode |= MIPS16_ALL_ARGS << 16; | |
5570 | else if (statics == 0xf) | |
5571 | /* All $a0-$a3 are statics. */ | |
5572 | opcode |= MIPS16_ALL_STATICS << 16; | |
5573 | else | |
5574 | { | |
5575 | /* Count arg registers. */ | |
5576 | num_args = 0; | |
5577 | while (args & 0x1) | |
5578 | { | |
5579 | args >>= 1; | |
5580 | num_args += 1; | |
5581 | } | |
5582 | if (args != 0) | |
a92713e6 | 5583 | return FALSE; |
364215c8 RS |
5584 | |
5585 | /* Count static registers. */ | |
5586 | num_statics = 0; | |
5587 | while (statics & 0x8) | |
5588 | { | |
5589 | statics = (statics << 1) & 0xf; | |
5590 | num_statics += 1; | |
5591 | } | |
5592 | if (statics != 0) | |
a92713e6 | 5593 | return FALSE; |
364215c8 RS |
5594 | |
5595 | /* Encode args/statics. */ | |
5596 | opcode |= ((num_args << 2) | num_statics) << 16; | |
5597 | } | |
5598 | ||
5599 | /* Encode $s0/$s1. */ | |
5600 | if (sregs & (1 << 0)) /* $s0 */ | |
5601 | opcode |= 0x20; | |
5602 | if (sregs & (1 << 1)) /* $s1 */ | |
5603 | opcode |= 0x10; | |
5604 | sregs >>= 2; | |
5605 | ||
5606 | /* Encode $s2-$s8. */ | |
5607 | num_sregs = 0; | |
5608 | while (sregs & 1) | |
5609 | { | |
5610 | sregs >>= 1; | |
5611 | num_sregs += 1; | |
5612 | } | |
5613 | if (sregs != 0) | |
a92713e6 | 5614 | return FALSE; |
364215c8 RS |
5615 | opcode |= num_sregs << 24; |
5616 | ||
5617 | /* Encode frame size. */ | |
5618 | if (num_frame_sizes == 0) | |
1a00e612 RS |
5619 | { |
5620 | set_insn_error (arg->argnum, _("missing frame size")); | |
5621 | return FALSE; | |
5622 | } | |
5623 | if (num_frame_sizes > 1) | |
5624 | { | |
5625 | set_insn_error (arg->argnum, _("frame size specified twice")); | |
5626 | return FALSE; | |
5627 | } | |
5628 | if ((frame_size & 7) != 0 || frame_size < 0 || frame_size > 0xff * 8) | |
5629 | { | |
5630 | set_insn_error (arg->argnum, _("invalid frame size")); | |
5631 | return FALSE; | |
5632 | } | |
5633 | if (frame_size != 128 || (opcode >> 16) != 0) | |
364215c8 RS |
5634 | { |
5635 | frame_size /= 8; | |
5636 | opcode |= (((frame_size & 0xf0) << 16) | |
5637 | | (frame_size & 0x0f)); | |
5638 | } | |
5639 | ||
364215c8 RS |
5640 | /* Finally build the instruction. */ |
5641 | if ((opcode >> 16) != 0 || frame_size == 0) | |
5642 | opcode |= MIPS16_EXTEND; | |
5643 | arg->insn->insn_opcode = opcode; | |
a92713e6 | 5644 | return TRUE; |
364215c8 RS |
5645 | } |
5646 | ||
a1d78564 RS |
5647 | /* OP_MDMX_IMM_REG matcher. */ |
5648 | ||
a92713e6 | 5649 | static bfd_boolean |
a1d78564 | 5650 | match_mdmx_imm_reg_operand (struct mips_arg_info *arg, |
a92713e6 | 5651 | const struct mips_operand *operand) |
a1d78564 | 5652 | { |
a92713e6 | 5653 | unsigned int regno, uval; |
a1d78564 RS |
5654 | bfd_boolean is_qh; |
5655 | const struct mips_opcode *opcode; | |
5656 | ||
5657 | /* The mips_opcode records whether this is an octobyte or quadhalf | |
5658 | instruction. Start out with that bit in place. */ | |
5659 | opcode = arg->insn->insn_mo; | |
5660 | uval = mips_extract_operand (operand, opcode->match); | |
5661 | is_qh = (uval != 0); | |
5662 | ||
56d438b1 | 5663 | if (arg->token->type == OT_REG) |
a1d78564 RS |
5664 | { |
5665 | if ((opcode->membership & INSN_5400) | |
5666 | && strcmp (opcode->name, "rzu.ob") == 0) | |
5667 | { | |
1a00e612 RS |
5668 | set_insn_error_i (arg->argnum, _("operand %d must be an immediate"), |
5669 | arg->argnum); | |
5670 | return FALSE; | |
a1d78564 RS |
5671 | } |
5672 | ||
56d438b1 CF |
5673 | if (!match_regno (arg, OP_REG_VEC, arg->token->u.regno, ®no)) |
5674 | return FALSE; | |
5675 | ++arg->token; | |
5676 | ||
a1d78564 RS |
5677 | /* Check whether this is a vector register or a broadcast of |
5678 | a single element. */ | |
56d438b1 | 5679 | if (arg->token->type == OT_INTEGER_INDEX) |
a1d78564 | 5680 | { |
56d438b1 | 5681 | if (arg->token->u.index > (is_qh ? 3 : 7)) |
a1d78564 | 5682 | { |
1a00e612 RS |
5683 | set_insn_error (arg->argnum, _("invalid element selector")); |
5684 | return FALSE; | |
a1d78564 | 5685 | } |
56d438b1 CF |
5686 | uval |= arg->token->u.index << (is_qh ? 2 : 1) << 5; |
5687 | ++arg->token; | |
a1d78564 RS |
5688 | } |
5689 | else | |
5690 | { | |
5691 | /* A full vector. */ | |
5692 | if ((opcode->membership & INSN_5400) | |
5693 | && (strcmp (opcode->name, "sll.ob") == 0 | |
5694 | || strcmp (opcode->name, "srl.ob") == 0)) | |
5695 | { | |
1a00e612 RS |
5696 | set_insn_error_i (arg->argnum, _("operand %d must be scalar"), |
5697 | arg->argnum); | |
5698 | return FALSE; | |
a1d78564 RS |
5699 | } |
5700 | ||
5701 | if (is_qh) | |
5702 | uval |= MDMX_FMTSEL_VEC_QH << 5; | |
5703 | else | |
5704 | uval |= MDMX_FMTSEL_VEC_OB << 5; | |
5705 | } | |
a1d78564 RS |
5706 | uval |= regno; |
5707 | } | |
5708 | else | |
5709 | { | |
5710 | offsetT sval; | |
5711 | ||
1a00e612 | 5712 | if (!match_const_int (arg, &sval)) |
a92713e6 | 5713 | return FALSE; |
a1d78564 RS |
5714 | if (sval < 0 || sval > 31) |
5715 | { | |
1a00e612 RS |
5716 | match_out_of_range (arg); |
5717 | return FALSE; | |
a1d78564 RS |
5718 | } |
5719 | uval |= (sval & 31); | |
5720 | if (is_qh) | |
5721 | uval |= MDMX_FMTSEL_IMM_QH << 5; | |
5722 | else | |
5723 | uval |= MDMX_FMTSEL_IMM_OB << 5; | |
5724 | } | |
5725 | insn_insert_operand (arg->insn, operand, uval); | |
a92713e6 | 5726 | return TRUE; |
a1d78564 RS |
5727 | } |
5728 | ||
56d438b1 CF |
5729 | /* OP_IMM_INDEX matcher. */ |
5730 | ||
5731 | static bfd_boolean | |
5732 | match_imm_index_operand (struct mips_arg_info *arg, | |
5733 | const struct mips_operand *operand) | |
5734 | { | |
5735 | unsigned int max_val; | |
5736 | ||
5737 | if (arg->token->type != OT_INTEGER_INDEX) | |
5738 | return FALSE; | |
5739 | ||
5740 | max_val = (1 << operand->size) - 1; | |
5741 | if (arg->token->u.index > max_val) | |
5742 | { | |
5743 | match_out_of_range (arg); | |
5744 | return FALSE; | |
5745 | } | |
5746 | insn_insert_operand (arg->insn, operand, arg->token->u.index); | |
5747 | ++arg->token; | |
5748 | return TRUE; | |
5749 | } | |
5750 | ||
5751 | /* OP_REG_INDEX matcher. */ | |
5752 | ||
5753 | static bfd_boolean | |
5754 | match_reg_index_operand (struct mips_arg_info *arg, | |
5755 | const struct mips_operand *operand) | |
5756 | { | |
5757 | unsigned int regno; | |
5758 | ||
5759 | if (arg->token->type != OT_REG_INDEX) | |
5760 | return FALSE; | |
5761 | ||
5762 | if (!match_regno (arg, OP_REG_GP, arg->token->u.regno, ®no)) | |
5763 | return FALSE; | |
5764 | ||
5765 | insn_insert_operand (arg->insn, operand, regno); | |
5766 | ++arg->token; | |
5767 | return TRUE; | |
5768 | } | |
5769 | ||
a1d78564 RS |
5770 | /* OP_PC matcher. */ |
5771 | ||
a92713e6 RS |
5772 | static bfd_boolean |
5773 | match_pc_operand (struct mips_arg_info *arg) | |
a1d78564 | 5774 | { |
a92713e6 RS |
5775 | if (arg->token->type == OT_REG && (arg->token->u.regno & RTYPE_PC)) |
5776 | { | |
5777 | ++arg->token; | |
5778 | return TRUE; | |
5779 | } | |
5780 | return FALSE; | |
a1d78564 RS |
5781 | } |
5782 | ||
7361da2c AB |
5783 | /* OP_NON_ZERO_REG matcher. */ |
5784 | ||
5785 | static bfd_boolean | |
5786 | match_non_zero_reg_operand (struct mips_arg_info *arg, | |
5787 | const struct mips_operand *operand) | |
5788 | { | |
5789 | unsigned int regno; | |
5790 | ||
5791 | if (!match_reg (arg, OP_REG_GP, ®no)) | |
5792 | return FALSE; | |
5793 | ||
5794 | if (regno == 0) | |
5795 | return FALSE; | |
5796 | ||
5797 | arg->last_regno = regno; | |
5798 | insn_insert_operand (arg->insn, operand, regno); | |
5799 | return TRUE; | |
5800 | } | |
5801 | ||
a1d78564 RS |
5802 | /* OP_REPEAT_DEST_REG and OP_REPEAT_PREV_REG matcher. OTHER_REGNO is the |
5803 | register that we need to match. */ | |
5804 | ||
a92713e6 RS |
5805 | static bfd_boolean |
5806 | match_tied_reg_operand (struct mips_arg_info *arg, unsigned int other_regno) | |
a1d78564 RS |
5807 | { |
5808 | unsigned int regno; | |
5809 | ||
a92713e6 | 5810 | return match_reg (arg, OP_REG_GP, ®no) && regno == other_regno; |
a1d78564 RS |
5811 | } |
5812 | ||
89565f1b RS |
5813 | /* Read a floating-point constant from S for LI.S or LI.D. LENGTH is |
5814 | the length of the value in bytes (4 for float, 8 for double) and | |
5815 | USING_GPRS says whether the destination is a GPR rather than an FPR. | |
5816 | ||
5817 | Return the constant in IMM and OFFSET as follows: | |
5818 | ||
5819 | - If the constant should be loaded via memory, set IMM to O_absent and | |
5820 | OFFSET to the memory address. | |
5821 | ||
5822 | - Otherwise, if the constant should be loaded into two 32-bit registers, | |
5823 | set IMM to the O_constant to load into the high register and OFFSET | |
5824 | to the corresponding value for the low register. | |
5825 | ||
5826 | - Otherwise, set IMM to the full O_constant and set OFFSET to O_absent. | |
5827 | ||
5828 | These constants only appear as the last operand in an instruction, | |
5829 | and every instruction that accepts them in any variant accepts them | |
5830 | in all variants. This means we don't have to worry about backing out | |
5831 | any changes if the instruction does not match. We just match | |
5832 | unconditionally and report an error if the constant is invalid. */ | |
5833 | ||
a92713e6 RS |
5834 | static bfd_boolean |
5835 | match_float_constant (struct mips_arg_info *arg, expressionS *imm, | |
5836 | expressionS *offset, int length, bfd_boolean using_gprs) | |
89565f1b | 5837 | { |
a92713e6 | 5838 | char *p; |
89565f1b RS |
5839 | segT seg, new_seg; |
5840 | subsegT subseg; | |
5841 | const char *newname; | |
a92713e6 | 5842 | unsigned char *data; |
89565f1b RS |
5843 | |
5844 | /* Where the constant is placed is based on how the MIPS assembler | |
5845 | does things: | |
5846 | ||
5847 | length == 4 && using_gprs -- immediate value only | |
5848 | length == 8 && using_gprs -- .rdata or immediate value | |
5849 | length == 4 && !using_gprs -- .lit4 or immediate value | |
5850 | length == 8 && !using_gprs -- .lit8 or immediate value | |
5851 | ||
5852 | The .lit4 and .lit8 sections are only used if permitted by the | |
5853 | -G argument. */ | |
a92713e6 | 5854 | if (arg->token->type != OT_FLOAT) |
1a00e612 RS |
5855 | { |
5856 | set_insn_error (arg->argnum, _("floating-point expression required")); | |
5857 | return FALSE; | |
5858 | } | |
a92713e6 RS |
5859 | |
5860 | gas_assert (arg->token->u.flt.length == length); | |
5861 | data = arg->token->u.flt.data; | |
5862 | ++arg->token; | |
89565f1b RS |
5863 | |
5864 | /* Handle 32-bit constants for which an immediate value is best. */ | |
5865 | if (length == 4 | |
5866 | && (using_gprs | |
5867 | || g_switch_value < 4 | |
5868 | || (data[0] == 0 && data[1] == 0) | |
5869 | || (data[2] == 0 && data[3] == 0))) | |
5870 | { | |
5871 | imm->X_op = O_constant; | |
5872 | if (!target_big_endian) | |
5873 | imm->X_add_number = bfd_getl32 (data); | |
5874 | else | |
5875 | imm->X_add_number = bfd_getb32 (data); | |
5876 | offset->X_op = O_absent; | |
a92713e6 | 5877 | return TRUE; |
89565f1b RS |
5878 | } |
5879 | ||
5880 | /* Handle 64-bit constants for which an immediate value is best. */ | |
5881 | if (length == 8 | |
5882 | && !mips_disable_float_construction | |
351cdf24 MF |
5883 | /* Constants can only be constructed in GPRs and copied to FPRs if the |
5884 | GPRs are at least as wide as the FPRs or MTHC1 is available. | |
5885 | Unlike most tests for 32-bit floating-point registers this check | |
5886 | specifically looks for GPR_SIZE == 32 as the FPXX ABI does not | |
5887 | permit 64-bit moves without MXHC1. | |
5888 | Force the constant into memory otherwise. */ | |
5889 | && (using_gprs | |
5890 | || GPR_SIZE == 64 | |
5891 | || ISA_HAS_MXHC1 (mips_opts.isa) | |
5892 | || FPR_SIZE == 32) | |
89565f1b RS |
5893 | && ((data[0] == 0 && data[1] == 0) |
5894 | || (data[2] == 0 && data[3] == 0)) | |
5895 | && ((data[4] == 0 && data[5] == 0) | |
5896 | || (data[6] == 0 && data[7] == 0))) | |
5897 | { | |
5898 | /* The value is simple enough to load with a couple of instructions. | |
5899 | If using 32-bit registers, set IMM to the high order 32 bits and | |
5900 | OFFSET to the low order 32 bits. Otherwise, set IMM to the entire | |
5901 | 64 bit constant. */ | |
351cdf24 | 5902 | if (GPR_SIZE == 32 || (!using_gprs && FPR_SIZE != 64)) |
89565f1b RS |
5903 | { |
5904 | imm->X_op = O_constant; | |
5905 | offset->X_op = O_constant; | |
5906 | if (!target_big_endian) | |
5907 | { | |
5908 | imm->X_add_number = bfd_getl32 (data + 4); | |
5909 | offset->X_add_number = bfd_getl32 (data); | |
5910 | } | |
5911 | else | |
5912 | { | |
5913 | imm->X_add_number = bfd_getb32 (data); | |
5914 | offset->X_add_number = bfd_getb32 (data + 4); | |
5915 | } | |
5916 | if (offset->X_add_number == 0) | |
5917 | offset->X_op = O_absent; | |
5918 | } | |
5919 | else | |
5920 | { | |
5921 | imm->X_op = O_constant; | |
5922 | if (!target_big_endian) | |
5923 | imm->X_add_number = bfd_getl64 (data); | |
5924 | else | |
5925 | imm->X_add_number = bfd_getb64 (data); | |
5926 | offset->X_op = O_absent; | |
5927 | } | |
a92713e6 | 5928 | return TRUE; |
89565f1b RS |
5929 | } |
5930 | ||
5931 | /* Switch to the right section. */ | |
5932 | seg = now_seg; | |
5933 | subseg = now_subseg; | |
5934 | if (length == 4) | |
5935 | { | |
5936 | gas_assert (!using_gprs && g_switch_value >= 4); | |
5937 | newname = ".lit4"; | |
5938 | } | |
5939 | else | |
5940 | { | |
5941 | if (using_gprs || g_switch_value < 8) | |
5942 | newname = RDATA_SECTION_NAME; | |
5943 | else | |
5944 | newname = ".lit8"; | |
5945 | } | |
5946 | ||
5947 | new_seg = subseg_new (newname, (subsegT) 0); | |
5948 | bfd_set_section_flags (stdoutput, new_seg, | |
5949 | SEC_ALLOC | SEC_LOAD | SEC_READONLY | SEC_DATA); | |
5950 | frag_align (length == 4 ? 2 : 3, 0, 0); | |
5951 | if (strncmp (TARGET_OS, "elf", 3) != 0) | |
5952 | record_alignment (new_seg, 4); | |
5953 | else | |
5954 | record_alignment (new_seg, length == 4 ? 2 : 3); | |
5955 | if (seg == now_seg) | |
1661c76c | 5956 | as_bad (_("cannot use `%s' in this section"), arg->insn->insn_mo->name); |
89565f1b RS |
5957 | |
5958 | /* Set the argument to the current address in the section. */ | |
5959 | imm->X_op = O_absent; | |
5960 | offset->X_op = O_symbol; | |
5961 | offset->X_add_symbol = symbol_temp_new_now (); | |
5962 | offset->X_add_number = 0; | |
5963 | ||
5964 | /* Put the floating point number into the section. */ | |
5965 | p = frag_more (length); | |
5966 | memcpy (p, data, length); | |
5967 | ||
5968 | /* Switch back to the original section. */ | |
5969 | subseg_set (seg, subseg); | |
a92713e6 | 5970 | return TRUE; |
89565f1b RS |
5971 | } |
5972 | ||
14daeee3 RS |
5973 | /* OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX matcher; MATCH_P selects between |
5974 | them. */ | |
5975 | ||
5976 | static bfd_boolean | |
5977 | match_vu0_suffix_operand (struct mips_arg_info *arg, | |
5978 | const struct mips_operand *operand, | |
5979 | bfd_boolean match_p) | |
5980 | { | |
5981 | unsigned int uval; | |
5982 | ||
5983 | /* The operand can be an XYZW mask or a single 2-bit channel index | |
5984 | (with X being 0). */ | |
5985 | gas_assert (operand->size == 2 || operand->size == 4); | |
5986 | ||
ee5734f0 | 5987 | /* The suffix can be omitted when it is already part of the opcode. */ |
14daeee3 | 5988 | if (arg->token->type != OT_CHANNELS) |
ee5734f0 | 5989 | return match_p; |
14daeee3 RS |
5990 | |
5991 | uval = arg->token->u.channels; | |
5992 | if (operand->size == 2) | |
5993 | { | |
5994 | /* Check that a single bit is set and convert it into a 2-bit index. */ | |
5995 | if ((uval & -uval) != uval) | |
5996 | return FALSE; | |
5997 | uval = 4 - ffs (uval); | |
5998 | } | |
5999 | ||
6000 | if (match_p && insn_extract_operand (arg->insn, operand) != uval) | |
6001 | return FALSE; | |
6002 | ||
6003 | ++arg->token; | |
6004 | if (!match_p) | |
6005 | insn_insert_operand (arg->insn, operand, uval); | |
6006 | return TRUE; | |
6007 | } | |
6008 | ||
a1d78564 RS |
6009 | /* S is the text seen for ARG. Match it against OPERAND. Return the end |
6010 | of the argument text if the match is successful, otherwise return null. */ | |
6011 | ||
a92713e6 | 6012 | static bfd_boolean |
a1d78564 | 6013 | match_operand (struct mips_arg_info *arg, |
a92713e6 | 6014 | const struct mips_operand *operand) |
a1d78564 RS |
6015 | { |
6016 | switch (operand->type) | |
6017 | { | |
6018 | case OP_INT: | |
a92713e6 | 6019 | return match_int_operand (arg, operand); |
a1d78564 RS |
6020 | |
6021 | case OP_MAPPED_INT: | |
a92713e6 | 6022 | return match_mapped_int_operand (arg, operand); |
a1d78564 RS |
6023 | |
6024 | case OP_MSB: | |
a92713e6 | 6025 | return match_msb_operand (arg, operand); |
a1d78564 RS |
6026 | |
6027 | case OP_REG: | |
0f35dbc4 | 6028 | case OP_OPTIONAL_REG: |
a92713e6 | 6029 | return match_reg_operand (arg, operand); |
a1d78564 RS |
6030 | |
6031 | case OP_REG_PAIR: | |
a92713e6 | 6032 | return match_reg_pair_operand (arg, operand); |
a1d78564 RS |
6033 | |
6034 | case OP_PCREL: | |
a92713e6 | 6035 | return match_pcrel_operand (arg); |
a1d78564 RS |
6036 | |
6037 | case OP_PERF_REG: | |
a92713e6 | 6038 | return match_perf_reg_operand (arg, operand); |
a1d78564 RS |
6039 | |
6040 | case OP_ADDIUSP_INT: | |
a92713e6 | 6041 | return match_addiusp_operand (arg, operand); |
a1d78564 RS |
6042 | |
6043 | case OP_CLO_CLZ_DEST: | |
a92713e6 | 6044 | return match_clo_clz_dest_operand (arg, operand); |
a1d78564 RS |
6045 | |
6046 | case OP_LWM_SWM_LIST: | |
a92713e6 | 6047 | return match_lwm_swm_list_operand (arg, operand); |
a1d78564 RS |
6048 | |
6049 | case OP_ENTRY_EXIT_LIST: | |
a92713e6 | 6050 | return match_entry_exit_operand (arg, operand); |
364215c8 | 6051 | |
a1d78564 | 6052 | case OP_SAVE_RESTORE_LIST: |
a92713e6 | 6053 | return match_save_restore_list_operand (arg); |
a1d78564 RS |
6054 | |
6055 | case OP_MDMX_IMM_REG: | |
a92713e6 | 6056 | return match_mdmx_imm_reg_operand (arg, operand); |
a1d78564 RS |
6057 | |
6058 | case OP_REPEAT_DEST_REG: | |
a92713e6 | 6059 | return match_tied_reg_operand (arg, arg->dest_regno); |
a1d78564 RS |
6060 | |
6061 | case OP_REPEAT_PREV_REG: | |
a92713e6 | 6062 | return match_tied_reg_operand (arg, arg->last_regno); |
a1d78564 RS |
6063 | |
6064 | case OP_PC: | |
a92713e6 | 6065 | return match_pc_operand (arg); |
14daeee3 RS |
6066 | |
6067 | case OP_VU0_SUFFIX: | |
6068 | return match_vu0_suffix_operand (arg, operand, FALSE); | |
6069 | ||
6070 | case OP_VU0_MATCH_SUFFIX: | |
6071 | return match_vu0_suffix_operand (arg, operand, TRUE); | |
56d438b1 CF |
6072 | |
6073 | case OP_IMM_INDEX: | |
6074 | return match_imm_index_operand (arg, operand); | |
6075 | ||
6076 | case OP_REG_INDEX: | |
6077 | return match_reg_index_operand (arg, operand); | |
7361da2c AB |
6078 | |
6079 | case OP_SAME_RS_RT: | |
6080 | return match_same_rs_rt_operand (arg, operand); | |
6081 | ||
6082 | case OP_CHECK_PREV: | |
6083 | return match_check_prev_operand (arg, operand); | |
6084 | ||
6085 | case OP_NON_ZERO_REG: | |
6086 | return match_non_zero_reg_operand (arg, operand); | |
a1d78564 RS |
6087 | } |
6088 | abort (); | |
6089 | } | |
6090 | ||
6091 | /* ARG is the state after successfully matching an instruction. | |
6092 | Issue any queued-up warnings. */ | |
6093 | ||
6094 | static void | |
6095 | check_completed_insn (struct mips_arg_info *arg) | |
6096 | { | |
6097 | if (arg->seen_at) | |
6098 | { | |
6099 | if (AT == ATREG) | |
1661c76c | 6100 | as_warn (_("used $at without \".set noat\"")); |
a1d78564 | 6101 | else |
1661c76c | 6102 | as_warn (_("used $%u with \".set at=$%u\""), AT, AT); |
a1d78564 RS |
6103 | } |
6104 | } | |
a1d78564 | 6105 | |
85fcb30f RS |
6106 | /* Return true if modifying general-purpose register REG needs a delay. */ |
6107 | ||
6108 | static bfd_boolean | |
6109 | reg_needs_delay (unsigned int reg) | |
6110 | { | |
6111 | unsigned long prev_pinfo; | |
6112 | ||
6113 | prev_pinfo = history[0].insn_mo->pinfo; | |
6114 | if (!mips_opts.noreorder | |
67dc82bc | 6115 | && (((prev_pinfo & INSN_LOAD_MEMORY) && !gpr_interlocks) |
43885403 | 6116 | || ((prev_pinfo & INSN_LOAD_COPROC) && !cop_interlocks)) |
85fcb30f RS |
6117 | && (gpr_write_mask (&history[0]) & (1 << reg))) |
6118 | return TRUE; | |
6119 | ||
6120 | return FALSE; | |
6121 | } | |
6122 | ||
71400594 RS |
6123 | /* Classify an instruction according to the FIX_VR4120_* enumeration. |
6124 | Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected | |
6125 | by VR4120 errata. */ | |
4d7206a2 | 6126 | |
71400594 RS |
6127 | static unsigned int |
6128 | classify_vr4120_insn (const char *name) | |
252b5132 | 6129 | { |
71400594 RS |
6130 | if (strncmp (name, "macc", 4) == 0) |
6131 | return FIX_VR4120_MACC; | |
6132 | if (strncmp (name, "dmacc", 5) == 0) | |
6133 | return FIX_VR4120_DMACC; | |
6134 | if (strncmp (name, "mult", 4) == 0) | |
6135 | return FIX_VR4120_MULT; | |
6136 | if (strncmp (name, "dmult", 5) == 0) | |
6137 | return FIX_VR4120_DMULT; | |
6138 | if (strstr (name, "div")) | |
6139 | return FIX_VR4120_DIV; | |
6140 | if (strcmp (name, "mtlo") == 0 || strcmp (name, "mthi") == 0) | |
6141 | return FIX_VR4120_MTHILO; | |
6142 | return NUM_FIX_VR4120_CLASSES; | |
6143 | } | |
252b5132 | 6144 | |
a8d14a88 CM |
6145 | #define INSN_ERET 0x42000018 |
6146 | #define INSN_DERET 0x4200001f | |
6147 | #define INSN_DMULT 0x1c | |
6148 | #define INSN_DMULTU 0x1d | |
ff239038 | 6149 | |
71400594 RS |
6150 | /* Return the number of instructions that must separate INSN1 and INSN2, |
6151 | where INSN1 is the earlier instruction. Return the worst-case value | |
6152 | for any INSN2 if INSN2 is null. */ | |
252b5132 | 6153 | |
71400594 RS |
6154 | static unsigned int |
6155 | insns_between (const struct mips_cl_insn *insn1, | |
6156 | const struct mips_cl_insn *insn2) | |
6157 | { | |
6158 | unsigned long pinfo1, pinfo2; | |
4c260379 | 6159 | unsigned int mask; |
71400594 | 6160 | |
85fcb30f RS |
6161 | /* If INFO2 is null, pessimistically assume that all flags are set for |
6162 | the second instruction. */ | |
71400594 RS |
6163 | pinfo1 = insn1->insn_mo->pinfo; |
6164 | pinfo2 = insn2 ? insn2->insn_mo->pinfo : ~0U; | |
252b5132 | 6165 | |
71400594 RS |
6166 | /* For most targets, write-after-read dependencies on the HI and LO |
6167 | registers must be separated by at least two instructions. */ | |
6168 | if (!hilo_interlocks) | |
252b5132 | 6169 | { |
71400594 RS |
6170 | if ((pinfo1 & INSN_READ_LO) && (pinfo2 & INSN_WRITE_LO)) |
6171 | return 2; | |
6172 | if ((pinfo1 & INSN_READ_HI) && (pinfo2 & INSN_WRITE_HI)) | |
6173 | return 2; | |
6174 | } | |
6175 | ||
6176 | /* If we're working around r7000 errata, there must be two instructions | |
6177 | between an mfhi or mflo and any instruction that uses the result. */ | |
6178 | if (mips_7000_hilo_fix | |
df58fc94 | 6179 | && !mips_opts.micromips |
71400594 | 6180 | && MF_HILO_INSN (pinfo1) |
85fcb30f | 6181 | && (insn2 == NULL || (gpr_read_mask (insn2) & gpr_write_mask (insn1)))) |
71400594 RS |
6182 | return 2; |
6183 | ||
ff239038 CM |
6184 | /* If we're working around 24K errata, one instruction is required |
6185 | if an ERET or DERET is followed by a branch instruction. */ | |
df58fc94 | 6186 | if (mips_fix_24k && !mips_opts.micromips) |
ff239038 CM |
6187 | { |
6188 | if (insn1->insn_opcode == INSN_ERET | |
6189 | || insn1->insn_opcode == INSN_DERET) | |
6190 | { | |
6191 | if (insn2 == NULL | |
6192 | || insn2->insn_opcode == INSN_ERET | |
6193 | || insn2->insn_opcode == INSN_DERET | |
11625dd8 | 6194 | || delayed_branch_p (insn2)) |
ff239038 CM |
6195 | return 1; |
6196 | } | |
6197 | } | |
6198 | ||
a8d14a88 CM |
6199 | /* If we're working around PMC RM7000 errata, there must be three |
6200 | nops between a dmult and a load instruction. */ | |
6201 | if (mips_fix_rm7000 && !mips_opts.micromips) | |
6202 | { | |
6203 | if ((insn1->insn_opcode & insn1->insn_mo->mask) == INSN_DMULT | |
6204 | || (insn1->insn_opcode & insn1->insn_mo->mask) == INSN_DMULTU) | |
6205 | { | |
6206 | if (pinfo2 & INSN_LOAD_MEMORY) | |
6207 | return 3; | |
6208 | } | |
6209 | } | |
6210 | ||
71400594 RS |
6211 | /* If working around VR4120 errata, check for combinations that need |
6212 | a single intervening instruction. */ | |
df58fc94 | 6213 | if (mips_fix_vr4120 && !mips_opts.micromips) |
71400594 RS |
6214 | { |
6215 | unsigned int class1, class2; | |
252b5132 | 6216 | |
71400594 RS |
6217 | class1 = classify_vr4120_insn (insn1->insn_mo->name); |
6218 | if (class1 != NUM_FIX_VR4120_CLASSES && vr4120_conflicts[class1] != 0) | |
252b5132 | 6219 | { |
71400594 RS |
6220 | if (insn2 == NULL) |
6221 | return 1; | |
6222 | class2 = classify_vr4120_insn (insn2->insn_mo->name); | |
6223 | if (vr4120_conflicts[class1] & (1 << class2)) | |
6224 | return 1; | |
252b5132 | 6225 | } |
71400594 RS |
6226 | } |
6227 | ||
df58fc94 | 6228 | if (!HAVE_CODE_COMPRESSION) |
71400594 RS |
6229 | { |
6230 | /* Check for GPR or coprocessor load delays. All such delays | |
6231 | are on the RT register. */ | |
6232 | /* Itbl support may require additional care here. */ | |
67dc82bc | 6233 | if ((!gpr_interlocks && (pinfo1 & INSN_LOAD_MEMORY)) |
43885403 | 6234 | || (!cop_interlocks && (pinfo1 & INSN_LOAD_COPROC))) |
252b5132 | 6235 | { |
85fcb30f | 6236 | if (insn2 == NULL || (gpr_read_mask (insn2) & gpr_write_mask (insn1))) |
71400594 RS |
6237 | return 1; |
6238 | } | |
6239 | ||
6240 | /* Check for generic coprocessor hazards. | |
6241 | ||
6242 | This case is not handled very well. There is no special | |
6243 | knowledge of CP0 handling, and the coprocessors other than | |
6244 | the floating point unit are not distinguished at all. */ | |
6245 | /* Itbl support may require additional care here. FIXME! | |
6246 | Need to modify this to include knowledge about | |
6247 | user specified delays! */ | |
43885403 | 6248 | else if ((!cop_interlocks && (pinfo1 & INSN_COPROC_MOVE)) |
71400594 RS |
6249 | || (!cop_mem_interlocks && (pinfo1 & INSN_COPROC_MEMORY_DELAY))) |
6250 | { | |
6251 | /* Handle cases where INSN1 writes to a known general coprocessor | |
6252 | register. There must be a one instruction delay before INSN2 | |
6253 | if INSN2 reads that register, otherwise no delay is needed. */ | |
4c260379 RS |
6254 | mask = fpr_write_mask (insn1); |
6255 | if (mask != 0) | |
252b5132 | 6256 | { |
4c260379 | 6257 | if (!insn2 || (mask & fpr_read_mask (insn2)) != 0) |
71400594 | 6258 | return 1; |
252b5132 RH |
6259 | } |
6260 | else | |
6261 | { | |
71400594 RS |
6262 | /* Read-after-write dependencies on the control registers |
6263 | require a two-instruction gap. */ | |
6264 | if ((pinfo1 & INSN_WRITE_COND_CODE) | |
6265 | && (pinfo2 & INSN_READ_COND_CODE)) | |
6266 | return 2; | |
6267 | ||
6268 | /* We don't know exactly what INSN1 does. If INSN2 is | |
6269 | also a coprocessor instruction, assume there must be | |
6270 | a one instruction gap. */ | |
6271 | if (pinfo2 & INSN_COP) | |
6272 | return 1; | |
252b5132 RH |
6273 | } |
6274 | } | |
6b76fefe | 6275 | |
71400594 RS |
6276 | /* Check for read-after-write dependencies on the coprocessor |
6277 | control registers in cases where INSN1 does not need a general | |
6278 | coprocessor delay. This means that INSN1 is a floating point | |
6279 | comparison instruction. */ | |
6280 | /* Itbl support may require additional care here. */ | |
6281 | else if (!cop_interlocks | |
6282 | && (pinfo1 & INSN_WRITE_COND_CODE) | |
6283 | && (pinfo2 & INSN_READ_COND_CODE)) | |
6284 | return 1; | |
6285 | } | |
6b76fefe | 6286 | |
7361da2c AB |
6287 | /* Forbidden slots can not contain Control Transfer Instructions (CTIs) |
6288 | CTIs include all branches and jumps, nal, eret, eretnc, deret, wait | |
6289 | and pause. */ | |
6290 | if ((insn1->insn_mo->pinfo2 & INSN2_FORBIDDEN_SLOT) | |
6291 | && ((pinfo2 & INSN_NO_DELAY_SLOT) | |
6292 | || (insn2 && delayed_branch_p (insn2)))) | |
6293 | return 1; | |
6294 | ||
71400594 RS |
6295 | return 0; |
6296 | } | |
6b76fefe | 6297 | |
7d8e00cf RS |
6298 | /* Return the number of nops that would be needed to work around the |
6299 | VR4130 mflo/mfhi errata if instruction INSN immediately followed | |
932d1a1b RS |
6300 | the MAX_VR4130_NOPS instructions described by HIST. Ignore hazards |
6301 | that are contained within the first IGNORE instructions of HIST. */ | |
7d8e00cf RS |
6302 | |
6303 | static int | |
932d1a1b | 6304 | nops_for_vr4130 (int ignore, const struct mips_cl_insn *hist, |
7d8e00cf RS |
6305 | const struct mips_cl_insn *insn) |
6306 | { | |
4c260379 RS |
6307 | int i, j; |
6308 | unsigned int mask; | |
7d8e00cf RS |
6309 | |
6310 | /* Check if the instruction writes to HI or LO. MTHI and MTLO | |
6311 | are not affected by the errata. */ | |
6312 | if (insn != 0 | |
6313 | && ((insn->insn_mo->pinfo & (INSN_WRITE_HI | INSN_WRITE_LO)) == 0 | |
6314 | || strcmp (insn->insn_mo->name, "mtlo") == 0 | |
6315 | || strcmp (insn->insn_mo->name, "mthi") == 0)) | |
6316 | return 0; | |
6317 | ||
6318 | /* Search for the first MFLO or MFHI. */ | |
6319 | for (i = 0; i < MAX_VR4130_NOPS; i++) | |
91d6fa6a | 6320 | if (MF_HILO_INSN (hist[i].insn_mo->pinfo)) |
7d8e00cf RS |
6321 | { |
6322 | /* Extract the destination register. */ | |
4c260379 | 6323 | mask = gpr_write_mask (&hist[i]); |
7d8e00cf RS |
6324 | |
6325 | /* No nops are needed if INSN reads that register. */ | |
4c260379 | 6326 | if (insn != NULL && (gpr_read_mask (insn) & mask) != 0) |
7d8e00cf RS |
6327 | return 0; |
6328 | ||
6329 | /* ...or if any of the intervening instructions do. */ | |
6330 | for (j = 0; j < i; j++) | |
4c260379 | 6331 | if (gpr_read_mask (&hist[j]) & mask) |
7d8e00cf RS |
6332 | return 0; |
6333 | ||
932d1a1b RS |
6334 | if (i >= ignore) |
6335 | return MAX_VR4130_NOPS - i; | |
7d8e00cf RS |
6336 | } |
6337 | return 0; | |
6338 | } | |
6339 | ||
134c0c8b MR |
6340 | #define BASE_REG_EQ(INSN1, INSN2) \ |
6341 | ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \ | |
15be625d CM |
6342 | == (((INSN2) >> OP_SH_RS) & OP_MASK_RS)) |
6343 | ||
6344 | /* Return the minimum alignment for this store instruction. */ | |
6345 | ||
6346 | static int | |
6347 | fix_24k_align_to (const struct mips_opcode *mo) | |
6348 | { | |
6349 | if (strcmp (mo->name, "sh") == 0) | |
6350 | return 2; | |
6351 | ||
6352 | if (strcmp (mo->name, "swc1") == 0 | |
6353 | || strcmp (mo->name, "swc2") == 0 | |
6354 | || strcmp (mo->name, "sw") == 0 | |
6355 | || strcmp (mo->name, "sc") == 0 | |
6356 | || strcmp (mo->name, "s.s") == 0) | |
6357 | return 4; | |
6358 | ||
6359 | if (strcmp (mo->name, "sdc1") == 0 | |
6360 | || strcmp (mo->name, "sdc2") == 0 | |
6361 | || strcmp (mo->name, "s.d") == 0) | |
6362 | return 8; | |
6363 | ||
6364 | /* sb, swl, swr */ | |
6365 | return 1; | |
6366 | } | |
6367 | ||
6368 | struct fix_24k_store_info | |
6369 | { | |
6370 | /* Immediate offset, if any, for this store instruction. */ | |
6371 | short off; | |
6372 | /* Alignment required by this store instruction. */ | |
6373 | int align_to; | |
6374 | /* True for register offsets. */ | |
6375 | int register_offset; | |
6376 | }; | |
6377 | ||
6378 | /* Comparison function used by qsort. */ | |
6379 | ||
6380 | static int | |
6381 | fix_24k_sort (const void *a, const void *b) | |
6382 | { | |
6383 | const struct fix_24k_store_info *pos1 = a; | |
6384 | const struct fix_24k_store_info *pos2 = b; | |
6385 | ||
6386 | return (pos1->off - pos2->off); | |
6387 | } | |
6388 | ||
6389 | /* INSN is a store instruction. Try to record the store information | |
6390 | in STINFO. Return false if the information isn't known. */ | |
6391 | ||
6392 | static bfd_boolean | |
6393 | fix_24k_record_store_info (struct fix_24k_store_info *stinfo, | |
ab9794cf | 6394 | const struct mips_cl_insn *insn) |
15be625d CM |
6395 | { |
6396 | /* The instruction must have a known offset. */ | |
6397 | if (!insn->complete_p || !strstr (insn->insn_mo->args, "o(")) | |
6398 | return FALSE; | |
6399 | ||
6400 | stinfo->off = (insn->insn_opcode >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE; | |
6401 | stinfo->align_to = fix_24k_align_to (insn->insn_mo); | |
6402 | return TRUE; | |
6403 | } | |
6404 | ||
932d1a1b RS |
6405 | /* Return the number of nops that would be needed to work around the 24k |
6406 | "lost data on stores during refill" errata if instruction INSN | |
6407 | immediately followed the 2 instructions described by HIST. | |
6408 | Ignore hazards that are contained within the first IGNORE | |
6409 | instructions of HIST. | |
6410 | ||
6411 | Problem: The FSB (fetch store buffer) acts as an intermediate buffer | |
6412 | for the data cache refills and store data. The following describes | |
6413 | the scenario where the store data could be lost. | |
6414 | ||
6415 | * A data cache miss, due to either a load or a store, causing fill | |
6416 | data to be supplied by the memory subsystem | |
6417 | * The first three doublewords of fill data are returned and written | |
6418 | into the cache | |
6419 | * A sequence of four stores occurs in consecutive cycles around the | |
6420 | final doubleword of the fill: | |
6421 | * Store A | |
6422 | * Store B | |
6423 | * Store C | |
6424 | * Zero, One or more instructions | |
6425 | * Store D | |
6426 | ||
6427 | The four stores A-D must be to different doublewords of the line that | |
6428 | is being filled. The fourth instruction in the sequence above permits | |
6429 | the fill of the final doubleword to be transferred from the FSB into | |
6430 | the cache. In the sequence above, the stores may be either integer | |
6431 | (sb, sh, sw, swr, swl, sc) or coprocessor (swc1/swc2, sdc1/sdc2, | |
6432 | swxc1, sdxc1, suxc1) stores, as long as the four stores are to | |
6433 | different doublewords on the line. If the floating point unit is | |
6434 | running in 1:2 mode, it is not possible to create the sequence above | |
6435 | using only floating point store instructions. | |
15be625d CM |
6436 | |
6437 | In this case, the cache line being filled is incorrectly marked | |
6438 | invalid, thereby losing the data from any store to the line that | |
6439 | occurs between the original miss and the completion of the five | |
6440 | cycle sequence shown above. | |
6441 | ||
932d1a1b | 6442 | The workarounds are: |
15be625d | 6443 | |
932d1a1b RS |
6444 | * Run the data cache in write-through mode. |
6445 | * Insert a non-store instruction between | |
6446 | Store A and Store B or Store B and Store C. */ | |
3739860c | 6447 | |
15be625d | 6448 | static int |
932d1a1b | 6449 | nops_for_24k (int ignore, const struct mips_cl_insn *hist, |
15be625d CM |
6450 | const struct mips_cl_insn *insn) |
6451 | { | |
6452 | struct fix_24k_store_info pos[3]; | |
6453 | int align, i, base_offset; | |
6454 | ||
932d1a1b RS |
6455 | if (ignore >= 2) |
6456 | return 0; | |
6457 | ||
ab9794cf RS |
6458 | /* If the previous instruction wasn't a store, there's nothing to |
6459 | worry about. */ | |
15be625d CM |
6460 | if ((hist[0].insn_mo->pinfo & INSN_STORE_MEMORY) == 0) |
6461 | return 0; | |
6462 | ||
ab9794cf RS |
6463 | /* If the instructions after the previous one are unknown, we have |
6464 | to assume the worst. */ | |
6465 | if (!insn) | |
15be625d CM |
6466 | return 1; |
6467 | ||
ab9794cf RS |
6468 | /* Check whether we are dealing with three consecutive stores. */ |
6469 | if ((insn->insn_mo->pinfo & INSN_STORE_MEMORY) == 0 | |
6470 | || (hist[1].insn_mo->pinfo & INSN_STORE_MEMORY) == 0) | |
15be625d CM |
6471 | return 0; |
6472 | ||
6473 | /* If we don't know the relationship between the store addresses, | |
6474 | assume the worst. */ | |
ab9794cf | 6475 | if (!BASE_REG_EQ (insn->insn_opcode, hist[0].insn_opcode) |
15be625d CM |
6476 | || !BASE_REG_EQ (insn->insn_opcode, hist[1].insn_opcode)) |
6477 | return 1; | |
6478 | ||
6479 | if (!fix_24k_record_store_info (&pos[0], insn) | |
6480 | || !fix_24k_record_store_info (&pos[1], &hist[0]) | |
6481 | || !fix_24k_record_store_info (&pos[2], &hist[1])) | |
6482 | return 1; | |
6483 | ||
6484 | qsort (&pos, 3, sizeof (struct fix_24k_store_info), fix_24k_sort); | |
6485 | ||
6486 | /* Pick a value of ALIGN and X such that all offsets are adjusted by | |
6487 | X bytes and such that the base register + X is known to be aligned | |
6488 | to align bytes. */ | |
6489 | ||
6490 | if (((insn->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == SP) | |
6491 | align = 8; | |
6492 | else | |
6493 | { | |
6494 | align = pos[0].align_to; | |
6495 | base_offset = pos[0].off; | |
6496 | for (i = 1; i < 3; i++) | |
6497 | if (align < pos[i].align_to) | |
6498 | { | |
6499 | align = pos[i].align_to; | |
6500 | base_offset = pos[i].off; | |
6501 | } | |
6502 | for (i = 0; i < 3; i++) | |
6503 | pos[i].off -= base_offset; | |
6504 | } | |
6505 | ||
6506 | pos[0].off &= ~align + 1; | |
6507 | pos[1].off &= ~align + 1; | |
6508 | pos[2].off &= ~align + 1; | |
6509 | ||
6510 | /* If any two stores write to the same chunk, they also write to the | |
6511 | same doubleword. The offsets are still sorted at this point. */ | |
6512 | if (pos[0].off == pos[1].off || pos[1].off == pos[2].off) | |
6513 | return 0; | |
6514 | ||
6515 | /* A range of at least 9 bytes is needed for the stores to be in | |
6516 | non-overlapping doublewords. */ | |
6517 | if (pos[2].off - pos[0].off <= 8) | |
6518 | return 0; | |
6519 | ||
6520 | if (pos[2].off - pos[1].off >= 24 | |
6521 | || pos[1].off - pos[0].off >= 24 | |
6522 | || pos[2].off - pos[0].off >= 32) | |
6523 | return 0; | |
6524 | ||
6525 | return 1; | |
6526 | } | |
6527 | ||
71400594 | 6528 | /* Return the number of nops that would be needed if instruction INSN |
91d6fa6a | 6529 | immediately followed the MAX_NOPS instructions given by HIST, |
932d1a1b RS |
6530 | where HIST[0] is the most recent instruction. Ignore hazards |
6531 | between INSN and the first IGNORE instructions in HIST. | |
6532 | ||
6533 | If INSN is null, return the worse-case number of nops for any | |
6534 | instruction. */ | |
bdaaa2e1 | 6535 | |
71400594 | 6536 | static int |
932d1a1b | 6537 | nops_for_insn (int ignore, const struct mips_cl_insn *hist, |
71400594 RS |
6538 | const struct mips_cl_insn *insn) |
6539 | { | |
6540 | int i, nops, tmp_nops; | |
bdaaa2e1 | 6541 | |
71400594 | 6542 | nops = 0; |
932d1a1b | 6543 | for (i = ignore; i < MAX_DELAY_NOPS; i++) |
65b02341 | 6544 | { |
91d6fa6a | 6545 | tmp_nops = insns_between (hist + i, insn) - i; |
65b02341 RS |
6546 | if (tmp_nops > nops) |
6547 | nops = tmp_nops; | |
6548 | } | |
7d8e00cf | 6549 | |
df58fc94 | 6550 | if (mips_fix_vr4130 && !mips_opts.micromips) |
7d8e00cf | 6551 | { |
932d1a1b | 6552 | tmp_nops = nops_for_vr4130 (ignore, hist, insn); |
7d8e00cf RS |
6553 | if (tmp_nops > nops) |
6554 | nops = tmp_nops; | |
6555 | } | |
6556 | ||
df58fc94 | 6557 | if (mips_fix_24k && !mips_opts.micromips) |
15be625d | 6558 | { |
932d1a1b | 6559 | tmp_nops = nops_for_24k (ignore, hist, insn); |
15be625d CM |
6560 | if (tmp_nops > nops) |
6561 | nops = tmp_nops; | |
6562 | } | |
6563 | ||
71400594 RS |
6564 | return nops; |
6565 | } | |
252b5132 | 6566 | |
71400594 | 6567 | /* The variable arguments provide NUM_INSNS extra instructions that |
91d6fa6a | 6568 | might be added to HIST. Return the largest number of nops that |
932d1a1b RS |
6569 | would be needed after the extended sequence, ignoring hazards |
6570 | in the first IGNORE instructions. */ | |
252b5132 | 6571 | |
71400594 | 6572 | static int |
932d1a1b RS |
6573 | nops_for_sequence (int num_insns, int ignore, |
6574 | const struct mips_cl_insn *hist, ...) | |
71400594 RS |
6575 | { |
6576 | va_list args; | |
6577 | struct mips_cl_insn buffer[MAX_NOPS]; | |
6578 | struct mips_cl_insn *cursor; | |
6579 | int nops; | |
6580 | ||
91d6fa6a | 6581 | va_start (args, hist); |
71400594 | 6582 | cursor = buffer + num_insns; |
91d6fa6a | 6583 | memcpy (cursor, hist, (MAX_NOPS - num_insns) * sizeof (*cursor)); |
71400594 RS |
6584 | while (cursor > buffer) |
6585 | *--cursor = *va_arg (args, const struct mips_cl_insn *); | |
6586 | ||
932d1a1b | 6587 | nops = nops_for_insn (ignore, buffer, NULL); |
71400594 RS |
6588 | va_end (args); |
6589 | return nops; | |
6590 | } | |
252b5132 | 6591 | |
71400594 RS |
6592 | /* Like nops_for_insn, but if INSN is a branch, take into account the |
6593 | worst-case delay for the branch target. */ | |
252b5132 | 6594 | |
71400594 | 6595 | static int |
932d1a1b | 6596 | nops_for_insn_or_target (int ignore, const struct mips_cl_insn *hist, |
71400594 RS |
6597 | const struct mips_cl_insn *insn) |
6598 | { | |
6599 | int nops, tmp_nops; | |
60b63b72 | 6600 | |
932d1a1b | 6601 | nops = nops_for_insn (ignore, hist, insn); |
11625dd8 | 6602 | if (delayed_branch_p (insn)) |
71400594 | 6603 | { |
932d1a1b | 6604 | tmp_nops = nops_for_sequence (2, ignore ? ignore + 2 : 0, |
14fe068b | 6605 | hist, insn, get_delay_slot_nop (insn)); |
71400594 RS |
6606 | if (tmp_nops > nops) |
6607 | nops = tmp_nops; | |
6608 | } | |
11625dd8 | 6609 | else if (compact_branch_p (insn)) |
71400594 | 6610 | { |
932d1a1b | 6611 | tmp_nops = nops_for_sequence (1, ignore ? ignore + 1 : 0, hist, insn); |
71400594 RS |
6612 | if (tmp_nops > nops) |
6613 | nops = tmp_nops; | |
6614 | } | |
6615 | return nops; | |
6616 | } | |
6617 | ||
c67a084a NC |
6618 | /* Fix NOP issue: Replace nops by "or at,at,zero". */ |
6619 | ||
6620 | static void | |
6621 | fix_loongson2f_nop (struct mips_cl_insn * ip) | |
6622 | { | |
df58fc94 | 6623 | gas_assert (!HAVE_CODE_COMPRESSION); |
c67a084a NC |
6624 | if (strcmp (ip->insn_mo->name, "nop") == 0) |
6625 | ip->insn_opcode = LOONGSON2F_NOP_INSN; | |
6626 | } | |
6627 | ||
6628 | /* Fix Jump Issue: Eliminate instruction fetch from outside 256M region | |
6629 | jr target pc &= 'hffff_ffff_cfff_ffff. */ | |
6630 | ||
6631 | static void | |
6632 | fix_loongson2f_jump (struct mips_cl_insn * ip) | |
6633 | { | |
df58fc94 | 6634 | gas_assert (!HAVE_CODE_COMPRESSION); |
c67a084a NC |
6635 | if (strcmp (ip->insn_mo->name, "j") == 0 |
6636 | || strcmp (ip->insn_mo->name, "jr") == 0 | |
6637 | || strcmp (ip->insn_mo->name, "jalr") == 0) | |
6638 | { | |
6639 | int sreg; | |
6640 | expressionS ep; | |
6641 | ||
6642 | if (! mips_opts.at) | |
6643 | return; | |
6644 | ||
df58fc94 | 6645 | sreg = EXTRACT_OPERAND (0, RS, *ip); |
c67a084a NC |
6646 | if (sreg == ZERO || sreg == KT0 || sreg == KT1 || sreg == ATREG) |
6647 | return; | |
6648 | ||
6649 | ep.X_op = O_constant; | |
6650 | ep.X_add_number = 0xcfff0000; | |
6651 | macro_build (&ep, "lui", "t,u", ATREG, BFD_RELOC_HI16); | |
6652 | ep.X_add_number = 0xffff; | |
6653 | macro_build (&ep, "ori", "t,r,i", ATREG, ATREG, BFD_RELOC_LO16); | |
6654 | macro_build (NULL, "and", "d,v,t", sreg, sreg, ATREG); | |
6655 | } | |
6656 | } | |
6657 | ||
6658 | static void | |
6659 | fix_loongson2f (struct mips_cl_insn * ip) | |
6660 | { | |
6661 | if (mips_fix_loongson2f_nop) | |
6662 | fix_loongson2f_nop (ip); | |
6663 | ||
6664 | if (mips_fix_loongson2f_jump) | |
6665 | fix_loongson2f_jump (ip); | |
6666 | } | |
6667 | ||
a4e06468 RS |
6668 | /* IP is a branch that has a delay slot, and we need to fill it |
6669 | automatically. Return true if we can do that by swapping IP | |
e407c74b NC |
6670 | with the previous instruction. |
6671 | ADDRESS_EXPR is an operand of the instruction to be used with | |
6672 | RELOC_TYPE. */ | |
a4e06468 RS |
6673 | |
6674 | static bfd_boolean | |
e407c74b | 6675 | can_swap_branch_p (struct mips_cl_insn *ip, expressionS *address_expr, |
26545944 | 6676 | bfd_reloc_code_real_type *reloc_type) |
a4e06468 | 6677 | { |
2b0c8b40 | 6678 | unsigned long pinfo, pinfo2, prev_pinfo, prev_pinfo2; |
a4e06468 | 6679 | unsigned int gpr_read, gpr_write, prev_gpr_read, prev_gpr_write; |
9d5de888 | 6680 | unsigned int fpr_read, prev_fpr_write; |
a4e06468 RS |
6681 | |
6682 | /* -O2 and above is required for this optimization. */ | |
6683 | if (mips_optimize < 2) | |
6684 | return FALSE; | |
6685 | ||
6686 | /* If we have seen .set volatile or .set nomove, don't optimize. */ | |
6687 | if (mips_opts.nomove) | |
6688 | return FALSE; | |
6689 | ||
6690 | /* We can't swap if the previous instruction's position is fixed. */ | |
6691 | if (history[0].fixed_p) | |
6692 | return FALSE; | |
6693 | ||
6694 | /* If the previous previous insn was in a .set noreorder, we can't | |
6695 | swap. Actually, the MIPS assembler will swap in this situation. | |
6696 | However, gcc configured -with-gnu-as will generate code like | |
6697 | ||
6698 | .set noreorder | |
6699 | lw $4,XXX | |
6700 | .set reorder | |
6701 | INSN | |
6702 | bne $4,$0,foo | |
6703 | ||
6704 | in which we can not swap the bne and INSN. If gcc is not configured | |
6705 | -with-gnu-as, it does not output the .set pseudo-ops. */ | |
6706 | if (history[1].noreorder_p) | |
6707 | return FALSE; | |
6708 | ||
87333bb7 MR |
6709 | /* If the previous instruction had a fixup in mips16 mode, we can not swap. |
6710 | This means that the previous instruction was a 4-byte one anyhow. */ | |
a4e06468 RS |
6711 | if (mips_opts.mips16 && history[0].fixp[0]) |
6712 | return FALSE; | |
6713 | ||
6714 | /* If the branch is itself the target of a branch, we can not swap. | |
6715 | We cheat on this; all we check for is whether there is a label on | |
6716 | this instruction. If there are any branches to anything other than | |
6717 | a label, users must use .set noreorder. */ | |
6718 | if (seg_info (now_seg)->label_list) | |
6719 | return FALSE; | |
6720 | ||
6721 | /* If the previous instruction is in a variant frag other than this | |
2309ddf2 | 6722 | branch's one, we cannot do the swap. This does not apply to |
9301f9c3 MR |
6723 | MIPS16 code, which uses variant frags for different purposes. */ |
6724 | if (!mips_opts.mips16 | |
a4e06468 RS |
6725 | && history[0].frag |
6726 | && history[0].frag->fr_type == rs_machine_dependent) | |
6727 | return FALSE; | |
6728 | ||
bcd530a7 RS |
6729 | /* We do not swap with instructions that cannot architecturally |
6730 | be placed in a branch delay slot, such as SYNC or ERET. We | |
6731 | also refrain from swapping with a trap instruction, since it | |
6732 | complicates trap handlers to have the trap instruction be in | |
6733 | a delay slot. */ | |
a4e06468 | 6734 | prev_pinfo = history[0].insn_mo->pinfo; |
bcd530a7 | 6735 | if (prev_pinfo & INSN_NO_DELAY_SLOT) |
a4e06468 RS |
6736 | return FALSE; |
6737 | ||
6738 | /* Check for conflicts between the branch and the instructions | |
6739 | before the candidate delay slot. */ | |
6740 | if (nops_for_insn (0, history + 1, ip) > 0) | |
6741 | return FALSE; | |
6742 | ||
6743 | /* Check for conflicts between the swapped sequence and the | |
6744 | target of the branch. */ | |
6745 | if (nops_for_sequence (2, 0, history + 1, ip, history) > 0) | |
6746 | return FALSE; | |
6747 | ||
6748 | /* If the branch reads a register that the previous | |
6749 | instruction sets, we can not swap. */ | |
6750 | gpr_read = gpr_read_mask (ip); | |
6751 | prev_gpr_write = gpr_write_mask (&history[0]); | |
6752 | if (gpr_read & prev_gpr_write) | |
6753 | return FALSE; | |
6754 | ||
9d5de888 CF |
6755 | fpr_read = fpr_read_mask (ip); |
6756 | prev_fpr_write = fpr_write_mask (&history[0]); | |
6757 | if (fpr_read & prev_fpr_write) | |
6758 | return FALSE; | |
6759 | ||
a4e06468 RS |
6760 | /* If the branch writes a register that the previous |
6761 | instruction sets, we can not swap. */ | |
6762 | gpr_write = gpr_write_mask (ip); | |
6763 | if (gpr_write & prev_gpr_write) | |
6764 | return FALSE; | |
6765 | ||
6766 | /* If the branch writes a register that the previous | |
6767 | instruction reads, we can not swap. */ | |
6768 | prev_gpr_read = gpr_read_mask (&history[0]); | |
6769 | if (gpr_write & prev_gpr_read) | |
6770 | return FALSE; | |
6771 | ||
6772 | /* If one instruction sets a condition code and the | |
6773 | other one uses a condition code, we can not swap. */ | |
6774 | pinfo = ip->insn_mo->pinfo; | |
6775 | if ((pinfo & INSN_READ_COND_CODE) | |
6776 | && (prev_pinfo & INSN_WRITE_COND_CODE)) | |
6777 | return FALSE; | |
6778 | if ((pinfo & INSN_WRITE_COND_CODE) | |
6779 | && (prev_pinfo & INSN_READ_COND_CODE)) | |
6780 | return FALSE; | |
6781 | ||
6782 | /* If the previous instruction uses the PC, we can not swap. */ | |
2b0c8b40 | 6783 | prev_pinfo2 = history[0].insn_mo->pinfo2; |
26545944 | 6784 | if (prev_pinfo2 & INSN2_READ_PC) |
2b0c8b40 | 6785 | return FALSE; |
a4e06468 | 6786 | |
df58fc94 RS |
6787 | /* If the previous instruction has an incorrect size for a fixed |
6788 | branch delay slot in microMIPS mode, we cannot swap. */ | |
2309ddf2 MR |
6789 | pinfo2 = ip->insn_mo->pinfo2; |
6790 | if (mips_opts.micromips | |
6791 | && (pinfo2 & INSN2_BRANCH_DELAY_16BIT) | |
6792 | && insn_length (history) != 2) | |
6793 | return FALSE; | |
6794 | if (mips_opts.micromips | |
6795 | && (pinfo2 & INSN2_BRANCH_DELAY_32BIT) | |
6796 | && insn_length (history) != 4) | |
6797 | return FALSE; | |
6798 | ||
e407c74b NC |
6799 | /* On R5900 short loops need to be fixed by inserting a nop in |
6800 | the branch delay slots. | |
6801 | A short loop can be terminated too early. */ | |
6802 | if (mips_opts.arch == CPU_R5900 | |
6803 | /* Check if instruction has a parameter, ignore "j $31". */ | |
6804 | && (address_expr != NULL) | |
6805 | /* Parameter must be 16 bit. */ | |
6806 | && (*reloc_type == BFD_RELOC_16_PCREL_S2) | |
6807 | /* Branch to same segment. */ | |
41065f5e | 6808 | && (S_GET_SEGMENT (address_expr->X_add_symbol) == now_seg) |
e407c74b | 6809 | /* Branch to same code fragment. */ |
41065f5e | 6810 | && (symbol_get_frag (address_expr->X_add_symbol) == frag_now) |
e407c74b | 6811 | /* Can only calculate branch offset if value is known. */ |
41065f5e | 6812 | && symbol_constant_p (address_expr->X_add_symbol) |
e407c74b NC |
6813 | /* Check if branch is really conditional. */ |
6814 | && !((ip->insn_opcode & 0xffff0000) == 0x10000000 /* beq $0,$0 */ | |
6815 | || (ip->insn_opcode & 0xffff0000) == 0x04010000 /* bgez $0 */ | |
6816 | || (ip->insn_opcode & 0xffff0000) == 0x04110000)) /* bgezal $0 */ | |
6817 | { | |
6818 | int distance; | |
6819 | /* Check if loop is shorter than 6 instructions including | |
6820 | branch and delay slot. */ | |
41065f5e | 6821 | distance = frag_now_fix () - S_GET_VALUE (address_expr->X_add_symbol); |
e407c74b NC |
6822 | if (distance <= 20) |
6823 | { | |
6824 | int i; | |
6825 | int rv; | |
6826 | ||
6827 | rv = FALSE; | |
6828 | /* When the loop includes branches or jumps, | |
6829 | it is not a short loop. */ | |
6830 | for (i = 0; i < (distance / 4); i++) | |
6831 | { | |
6832 | if ((history[i].cleared_p) | |
41065f5e | 6833 | || delayed_branch_p (&history[i])) |
e407c74b NC |
6834 | { |
6835 | rv = TRUE; | |
6836 | break; | |
6837 | } | |
6838 | } | |
6839 | if (rv == FALSE) | |
6840 | { | |
6841 | /* Insert nop after branch to fix short loop. */ | |
6842 | return FALSE; | |
6843 | } | |
6844 | } | |
6845 | } | |
6846 | ||
a4e06468 RS |
6847 | return TRUE; |
6848 | } | |
6849 | ||
e407c74b NC |
6850 | /* Decide how we should add IP to the instruction stream. |
6851 | ADDRESS_EXPR is an operand of the instruction to be used with | |
6852 | RELOC_TYPE. */ | |
a4e06468 RS |
6853 | |
6854 | static enum append_method | |
e407c74b | 6855 | get_append_method (struct mips_cl_insn *ip, expressionS *address_expr, |
26545944 | 6856 | bfd_reloc_code_real_type *reloc_type) |
a4e06468 | 6857 | { |
a4e06468 RS |
6858 | /* The relaxed version of a macro sequence must be inherently |
6859 | hazard-free. */ | |
6860 | if (mips_relax.sequence == 2) | |
6861 | return APPEND_ADD; | |
6862 | ||
3b821a28 | 6863 | /* We must not dabble with instructions in a ".set noreorder" block. */ |
a4e06468 RS |
6864 | if (mips_opts.noreorder) |
6865 | return APPEND_ADD; | |
6866 | ||
6867 | /* Otherwise, it's our responsibility to fill branch delay slots. */ | |
11625dd8 | 6868 | if (delayed_branch_p (ip)) |
a4e06468 | 6869 | { |
e407c74b NC |
6870 | if (!branch_likely_p (ip) |
6871 | && can_swap_branch_p (ip, address_expr, reloc_type)) | |
a4e06468 RS |
6872 | return APPEND_SWAP; |
6873 | ||
6874 | if (mips_opts.mips16 | |
6875 | && ISA_SUPPORTS_MIPS16E | |
fc76e730 | 6876 | && gpr_read_mask (ip) != 0) |
a4e06468 RS |
6877 | return APPEND_ADD_COMPACT; |
6878 | ||
7bd374a4 MR |
6879 | if (mips_opts.micromips |
6880 | && ((ip->insn_opcode & 0xffe0) == 0x4580 | |
6881 | || (!forced_insn_length | |
6882 | && ((ip->insn_opcode & 0xfc00) == 0xcc00 | |
6883 | || (ip->insn_opcode & 0xdc00) == 0x8c00)) | |
6884 | || (ip->insn_opcode & 0xdfe00000) == 0x94000000 | |
6885 | || (ip->insn_opcode & 0xdc1f0000) == 0x94000000)) | |
6886 | return APPEND_ADD_COMPACT; | |
6887 | ||
a4e06468 RS |
6888 | return APPEND_ADD_WITH_NOP; |
6889 | } | |
6890 | ||
a4e06468 RS |
6891 | return APPEND_ADD; |
6892 | } | |
6893 | ||
7bd374a4 MR |
6894 | /* IP is an instruction whose opcode we have just changed, END points |
6895 | to the end of the opcode table processed. Point IP->insn_mo to the | |
6896 | new opcode's definition. */ | |
ceb94aa5 RS |
6897 | |
6898 | static void | |
7bd374a4 | 6899 | find_altered_opcode (struct mips_cl_insn *ip, const struct mips_opcode *end) |
ceb94aa5 | 6900 | { |
7bd374a4 | 6901 | const struct mips_opcode *mo; |
ceb94aa5 | 6902 | |
ceb94aa5 | 6903 | for (mo = ip->insn_mo; mo < end; mo++) |
7bd374a4 MR |
6904 | if (mo->pinfo != INSN_MACRO |
6905 | && (ip->insn_opcode & mo->mask) == mo->match) | |
ceb94aa5 RS |
6906 | { |
6907 | ip->insn_mo = mo; | |
6908 | return; | |
6909 | } | |
6910 | abort (); | |
6911 | } | |
6912 | ||
7bd374a4 MR |
6913 | /* IP is a MIPS16 instruction whose opcode we have just changed. |
6914 | Point IP->insn_mo to the new opcode's definition. */ | |
6915 | ||
6916 | static void | |
6917 | find_altered_mips16_opcode (struct mips_cl_insn *ip) | |
6918 | { | |
6919 | find_altered_opcode (ip, &mips16_opcodes[bfd_mips16_num_opcodes]); | |
6920 | } | |
6921 | ||
6922 | /* IP is a microMIPS instruction whose opcode we have just changed. | |
6923 | Point IP->insn_mo to the new opcode's definition. */ | |
6924 | ||
6925 | static void | |
6926 | find_altered_micromips_opcode (struct mips_cl_insn *ip) | |
6927 | { | |
6928 | find_altered_opcode (ip, µmips_opcodes[bfd_micromips_num_opcodes]); | |
6929 | } | |
6930 | ||
df58fc94 RS |
6931 | /* For microMIPS macros, we need to generate a local number label |
6932 | as the target of branches. */ | |
6933 | #define MICROMIPS_LABEL_CHAR '\037' | |
6934 | static unsigned long micromips_target_label; | |
6935 | static char micromips_target_name[32]; | |
6936 | ||
6937 | static char * | |
6938 | micromips_label_name (void) | |
6939 | { | |
6940 | char *p = micromips_target_name; | |
6941 | char symbol_name_temporary[24]; | |
6942 | unsigned long l; | |
6943 | int i; | |
6944 | ||
6945 | if (*p) | |
6946 | return p; | |
6947 | ||
6948 | i = 0; | |
6949 | l = micromips_target_label; | |
6950 | #ifdef LOCAL_LABEL_PREFIX | |
6951 | *p++ = LOCAL_LABEL_PREFIX; | |
6952 | #endif | |
6953 | *p++ = 'L'; | |
6954 | *p++ = MICROMIPS_LABEL_CHAR; | |
6955 | do | |
6956 | { | |
6957 | symbol_name_temporary[i++] = l % 10 + '0'; | |
6958 | l /= 10; | |
6959 | } | |
6960 | while (l != 0); | |
6961 | while (i > 0) | |
6962 | *p++ = symbol_name_temporary[--i]; | |
6963 | *p = '\0'; | |
6964 | ||
6965 | return micromips_target_name; | |
6966 | } | |
6967 | ||
6968 | static void | |
6969 | micromips_label_expr (expressionS *label_expr) | |
6970 | { | |
6971 | label_expr->X_op = O_symbol; | |
6972 | label_expr->X_add_symbol = symbol_find_or_make (micromips_label_name ()); | |
6973 | label_expr->X_add_number = 0; | |
6974 | } | |
6975 | ||
6976 | static void | |
6977 | micromips_label_inc (void) | |
6978 | { | |
6979 | micromips_target_label++; | |
6980 | *micromips_target_name = '\0'; | |
6981 | } | |
6982 | ||
6983 | static void | |
6984 | micromips_add_label (void) | |
6985 | { | |
6986 | symbolS *s; | |
6987 | ||
6988 | s = colon (micromips_label_name ()); | |
6989 | micromips_label_inc (); | |
f3ded42a | 6990 | S_SET_OTHER (s, ELF_ST_SET_MICROMIPS (S_GET_OTHER (s))); |
df58fc94 RS |
6991 | } |
6992 | ||
6993 | /* If assembling microMIPS code, then return the microMIPS reloc | |
6994 | corresponding to the requested one if any. Otherwise return | |
6995 | the reloc unchanged. */ | |
6996 | ||
6997 | static bfd_reloc_code_real_type | |
6998 | micromips_map_reloc (bfd_reloc_code_real_type reloc) | |
6999 | { | |
7000 | static const bfd_reloc_code_real_type relocs[][2] = | |
7001 | { | |
7002 | /* Keep sorted incrementally by the left-hand key. */ | |
7003 | { BFD_RELOC_16_PCREL_S2, BFD_RELOC_MICROMIPS_16_PCREL_S1 }, | |
7004 | { BFD_RELOC_GPREL16, BFD_RELOC_MICROMIPS_GPREL16 }, | |
7005 | { BFD_RELOC_MIPS_JMP, BFD_RELOC_MICROMIPS_JMP }, | |
7006 | { BFD_RELOC_HI16, BFD_RELOC_MICROMIPS_HI16 }, | |
7007 | { BFD_RELOC_HI16_S, BFD_RELOC_MICROMIPS_HI16_S }, | |
7008 | { BFD_RELOC_LO16, BFD_RELOC_MICROMIPS_LO16 }, | |
7009 | { BFD_RELOC_MIPS_LITERAL, BFD_RELOC_MICROMIPS_LITERAL }, | |
7010 | { BFD_RELOC_MIPS_GOT16, BFD_RELOC_MICROMIPS_GOT16 }, | |
7011 | { BFD_RELOC_MIPS_CALL16, BFD_RELOC_MICROMIPS_CALL16 }, | |
7012 | { BFD_RELOC_MIPS_GOT_HI16, BFD_RELOC_MICROMIPS_GOT_HI16 }, | |
7013 | { BFD_RELOC_MIPS_GOT_LO16, BFD_RELOC_MICROMIPS_GOT_LO16 }, | |
7014 | { BFD_RELOC_MIPS_CALL_HI16, BFD_RELOC_MICROMIPS_CALL_HI16 }, | |
7015 | { BFD_RELOC_MIPS_CALL_LO16, BFD_RELOC_MICROMIPS_CALL_LO16 }, | |
7016 | { BFD_RELOC_MIPS_SUB, BFD_RELOC_MICROMIPS_SUB }, | |
7017 | { BFD_RELOC_MIPS_GOT_PAGE, BFD_RELOC_MICROMIPS_GOT_PAGE }, | |
7018 | { BFD_RELOC_MIPS_GOT_OFST, BFD_RELOC_MICROMIPS_GOT_OFST }, | |
7019 | { BFD_RELOC_MIPS_GOT_DISP, BFD_RELOC_MICROMIPS_GOT_DISP }, | |
7020 | { BFD_RELOC_MIPS_HIGHEST, BFD_RELOC_MICROMIPS_HIGHEST }, | |
7021 | { BFD_RELOC_MIPS_HIGHER, BFD_RELOC_MICROMIPS_HIGHER }, | |
7022 | { BFD_RELOC_MIPS_SCN_DISP, BFD_RELOC_MICROMIPS_SCN_DISP }, | |
7023 | { BFD_RELOC_MIPS_TLS_GD, BFD_RELOC_MICROMIPS_TLS_GD }, | |
7024 | { BFD_RELOC_MIPS_TLS_LDM, BFD_RELOC_MICROMIPS_TLS_LDM }, | |
7025 | { BFD_RELOC_MIPS_TLS_DTPREL_HI16, BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16 }, | |
7026 | { BFD_RELOC_MIPS_TLS_DTPREL_LO16, BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16 }, | |
7027 | { BFD_RELOC_MIPS_TLS_GOTTPREL, BFD_RELOC_MICROMIPS_TLS_GOTTPREL }, | |
7028 | { BFD_RELOC_MIPS_TLS_TPREL_HI16, BFD_RELOC_MICROMIPS_TLS_TPREL_HI16 }, | |
7029 | { BFD_RELOC_MIPS_TLS_TPREL_LO16, BFD_RELOC_MICROMIPS_TLS_TPREL_LO16 } | |
7030 | }; | |
7031 | bfd_reloc_code_real_type r; | |
7032 | size_t i; | |
7033 | ||
7034 | if (!mips_opts.micromips) | |
7035 | return reloc; | |
7036 | for (i = 0; i < ARRAY_SIZE (relocs); i++) | |
7037 | { | |
7038 | r = relocs[i][0]; | |
7039 | if (r > reloc) | |
7040 | return reloc; | |
7041 | if (r == reloc) | |
7042 | return relocs[i][1]; | |
7043 | } | |
7044 | return reloc; | |
7045 | } | |
7046 | ||
b886a2ab RS |
7047 | /* Try to resolve relocation RELOC against constant OPERAND at assembly time. |
7048 | Return true on success, storing the resolved value in RESULT. */ | |
7049 | ||
7050 | static bfd_boolean | |
7051 | calculate_reloc (bfd_reloc_code_real_type reloc, offsetT operand, | |
7052 | offsetT *result) | |
7053 | { | |
7054 | switch (reloc) | |
7055 | { | |
7056 | case BFD_RELOC_MIPS_HIGHEST: | |
7057 | case BFD_RELOC_MICROMIPS_HIGHEST: | |
7058 | *result = ((operand + 0x800080008000ull) >> 48) & 0xffff; | |
7059 | return TRUE; | |
7060 | ||
7061 | case BFD_RELOC_MIPS_HIGHER: | |
7062 | case BFD_RELOC_MICROMIPS_HIGHER: | |
7063 | *result = ((operand + 0x80008000ull) >> 32) & 0xffff; | |
7064 | return TRUE; | |
7065 | ||
7066 | case BFD_RELOC_HI16_S: | |
41947d9e | 7067 | case BFD_RELOC_HI16_S_PCREL: |
b886a2ab RS |
7068 | case BFD_RELOC_MICROMIPS_HI16_S: |
7069 | case BFD_RELOC_MIPS16_HI16_S: | |
7070 | *result = ((operand + 0x8000) >> 16) & 0xffff; | |
7071 | return TRUE; | |
7072 | ||
7073 | case BFD_RELOC_HI16: | |
7074 | case BFD_RELOC_MICROMIPS_HI16: | |
7075 | case BFD_RELOC_MIPS16_HI16: | |
7076 | *result = (operand >> 16) & 0xffff; | |
7077 | return TRUE; | |
7078 | ||
7079 | case BFD_RELOC_LO16: | |
41947d9e | 7080 | case BFD_RELOC_LO16_PCREL: |
b886a2ab RS |
7081 | case BFD_RELOC_MICROMIPS_LO16: |
7082 | case BFD_RELOC_MIPS16_LO16: | |
7083 | *result = operand & 0xffff; | |
7084 | return TRUE; | |
7085 | ||
7086 | case BFD_RELOC_UNUSED: | |
7087 | *result = operand; | |
7088 | return TRUE; | |
7089 | ||
7090 | default: | |
7091 | return FALSE; | |
7092 | } | |
7093 | } | |
7094 | ||
71400594 RS |
7095 | /* Output an instruction. IP is the instruction information. |
7096 | ADDRESS_EXPR is an operand of the instruction to be used with | |
df58fc94 RS |
7097 | RELOC_TYPE. EXPANSIONP is true if the instruction is part of |
7098 | a macro expansion. */ | |
71400594 RS |
7099 | |
7100 | static void | |
7101 | append_insn (struct mips_cl_insn *ip, expressionS *address_expr, | |
df58fc94 | 7102 | bfd_reloc_code_real_type *reloc_type, bfd_boolean expansionp) |
71400594 | 7103 | { |
14fe068b | 7104 | unsigned long prev_pinfo2, pinfo; |
71400594 | 7105 | bfd_boolean relaxed_branch = FALSE; |
a4e06468 | 7106 | enum append_method method; |
2309ddf2 | 7107 | bfd_boolean relax32; |
2b0c8b40 | 7108 | int branch_disp; |
71400594 | 7109 | |
2309ddf2 | 7110 | if (mips_fix_loongson2f && !HAVE_CODE_COMPRESSION) |
c67a084a NC |
7111 | fix_loongson2f (ip); |
7112 | ||
738f4d98 | 7113 | file_ase_mips16 |= mips_opts.mips16; |
df58fc94 | 7114 | file_ase_micromips |= mips_opts.micromips; |
738f4d98 | 7115 | |
df58fc94 | 7116 | prev_pinfo2 = history[0].insn_mo->pinfo2; |
71400594 | 7117 | pinfo = ip->insn_mo->pinfo; |
df58fc94 | 7118 | |
7bd374a4 MR |
7119 | /* Don't raise alarm about `nods' frags as they'll fill in the right |
7120 | kind of nop in relaxation if required. */ | |
df58fc94 RS |
7121 | if (mips_opts.micromips |
7122 | && !expansionp | |
7bd374a4 MR |
7123 | && !(history[0].frag |
7124 | && history[0].frag->fr_type == rs_machine_dependent | |
7125 | && RELAX_MICROMIPS_P (history[0].frag->fr_subtype) | |
7126 | && RELAX_MICROMIPS_NODS (history[0].frag->fr_subtype)) | |
df58fc94 RS |
7127 | && (((prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 |
7128 | && micromips_insn_length (ip->insn_mo) != 2) | |
7129 | || ((prev_pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0 | |
7130 | && micromips_insn_length (ip->insn_mo) != 4))) | |
1661c76c | 7131 | as_warn (_("wrong size instruction in a %u-bit branch delay slot"), |
df58fc94 | 7132 | (prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 ? 16 : 32); |
71400594 | 7133 | |
15be625d CM |
7134 | if (address_expr == NULL) |
7135 | ip->complete_p = 1; | |
b886a2ab RS |
7136 | else if (reloc_type[0] <= BFD_RELOC_UNUSED |
7137 | && reloc_type[1] == BFD_RELOC_UNUSED | |
7138 | && reloc_type[2] == BFD_RELOC_UNUSED | |
15be625d CM |
7139 | && address_expr->X_op == O_constant) |
7140 | { | |
15be625d CM |
7141 | switch (*reloc_type) |
7142 | { | |
15be625d | 7143 | case BFD_RELOC_MIPS_JMP: |
df58fc94 RS |
7144 | { |
7145 | int shift; | |
7146 | ||
17c6c9d9 MR |
7147 | /* Shift is 2, unusually, for microMIPS JALX. */ |
7148 | shift = (mips_opts.micromips | |
7149 | && strcmp (ip->insn_mo->name, "jalx") != 0) ? 1 : 2; | |
df58fc94 RS |
7150 | if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0) |
7151 | as_bad (_("jump to misaligned address (0x%lx)"), | |
7152 | (unsigned long) address_expr->X_add_number); | |
7153 | ip->insn_opcode |= ((address_expr->X_add_number >> shift) | |
7154 | & 0x3ffffff); | |
335574df | 7155 | ip->complete_p = 1; |
df58fc94 | 7156 | } |
15be625d CM |
7157 | break; |
7158 | ||
7159 | case BFD_RELOC_MIPS16_JMP: | |
7160 | if ((address_expr->X_add_number & 3) != 0) | |
7161 | as_bad (_("jump to misaligned address (0x%lx)"), | |
7162 | (unsigned long) address_expr->X_add_number); | |
7163 | ip->insn_opcode |= | |
7164 | (((address_expr->X_add_number & 0x7c0000) << 3) | |
7165 | | ((address_expr->X_add_number & 0xf800000) >> 7) | |
7166 | | ((address_expr->X_add_number & 0x3fffc) >> 2)); | |
335574df | 7167 | ip->complete_p = 1; |
15be625d CM |
7168 | break; |
7169 | ||
7170 | case BFD_RELOC_16_PCREL_S2: | |
df58fc94 RS |
7171 | { |
7172 | int shift; | |
7173 | ||
7174 | shift = mips_opts.micromips ? 1 : 2; | |
7175 | if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0) | |
7176 | as_bad (_("branch to misaligned address (0x%lx)"), | |
7177 | (unsigned long) address_expr->X_add_number); | |
7178 | if (!mips_relax_branch) | |
7179 | { | |
7180 | if ((address_expr->X_add_number + (1 << (shift + 15))) | |
7181 | & ~((1 << (shift + 16)) - 1)) | |
7182 | as_bad (_("branch address range overflow (0x%lx)"), | |
7183 | (unsigned long) address_expr->X_add_number); | |
7184 | ip->insn_opcode |= ((address_expr->X_add_number >> shift) | |
7185 | & 0xffff); | |
7186 | } | |
df58fc94 | 7187 | } |
15be625d CM |
7188 | break; |
7189 | ||
7361da2c AB |
7190 | case BFD_RELOC_MIPS_21_PCREL_S2: |
7191 | { | |
7192 | int shift; | |
7193 | ||
7194 | shift = 2; | |
7195 | if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0) | |
7196 | as_bad (_("branch to misaligned address (0x%lx)"), | |
7197 | (unsigned long) address_expr->X_add_number); | |
7198 | if ((address_expr->X_add_number + (1 << (shift + 20))) | |
7199 | & ~((1 << (shift + 21)) - 1)) | |
7200 | as_bad (_("branch address range overflow (0x%lx)"), | |
7201 | (unsigned long) address_expr->X_add_number); | |
7202 | ip->insn_opcode |= ((address_expr->X_add_number >> shift) | |
7203 | & 0x1fffff); | |
7204 | } | |
7205 | break; | |
7206 | ||
7207 | case BFD_RELOC_MIPS_26_PCREL_S2: | |
7208 | { | |
7209 | int shift; | |
7210 | ||
7211 | shift = 2; | |
7212 | if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0) | |
7213 | as_bad (_("branch to misaligned address (0x%lx)"), | |
7214 | (unsigned long) address_expr->X_add_number); | |
7215 | if ((address_expr->X_add_number + (1 << (shift + 25))) | |
7216 | & ~((1 << (shift + 26)) - 1)) | |
7217 | as_bad (_("branch address range overflow (0x%lx)"), | |
7218 | (unsigned long) address_expr->X_add_number); | |
7219 | ip->insn_opcode |= ((address_expr->X_add_number >> shift) | |
7220 | & 0x3ffffff); | |
7221 | } | |
7222 | break; | |
7223 | ||
15be625d | 7224 | default: |
b886a2ab RS |
7225 | { |
7226 | offsetT value; | |
7227 | ||
7228 | if (calculate_reloc (*reloc_type, address_expr->X_add_number, | |
7229 | &value)) | |
7230 | { | |
7231 | ip->insn_opcode |= value & 0xffff; | |
7232 | ip->complete_p = 1; | |
7233 | } | |
7234 | } | |
7235 | break; | |
7236 | } | |
15be625d CM |
7237 | } |
7238 | ||
71400594 RS |
7239 | if (mips_relax.sequence != 2 && !mips_opts.noreorder) |
7240 | { | |
7241 | /* There are a lot of optimizations we could do that we don't. | |
7242 | In particular, we do not, in general, reorder instructions. | |
7243 | If you use gcc with optimization, it will reorder | |
7244 | instructions and generally do much more optimization then we | |
7245 | do here; repeating all that work in the assembler would only | |
7246 | benefit hand written assembly code, and does not seem worth | |
7247 | it. */ | |
7248 | int nops = (mips_optimize == 0 | |
932d1a1b RS |
7249 | ? nops_for_insn (0, history, NULL) |
7250 | : nops_for_insn_or_target (0, history, ip)); | |
71400594 | 7251 | if (nops > 0) |
252b5132 RH |
7252 | { |
7253 | fragS *old_frag; | |
7254 | unsigned long old_frag_offset; | |
7255 | int i; | |
252b5132 RH |
7256 | |
7257 | old_frag = frag_now; | |
7258 | old_frag_offset = frag_now_fix (); | |
7259 | ||
7260 | for (i = 0; i < nops; i++) | |
14fe068b RS |
7261 | add_fixed_insn (NOP_INSN); |
7262 | insert_into_history (0, nops, NOP_INSN); | |
252b5132 RH |
7263 | |
7264 | if (listing) | |
7265 | { | |
7266 | listing_prev_line (); | |
7267 | /* We may be at the start of a variant frag. In case we | |
7268 | are, make sure there is enough space for the frag | |
7269 | after the frags created by listing_prev_line. The | |
7270 | argument to frag_grow here must be at least as large | |
7271 | as the argument to all other calls to frag_grow in | |
7272 | this file. We don't have to worry about being in the | |
7273 | middle of a variant frag, because the variants insert | |
7274 | all needed nop instructions themselves. */ | |
7275 | frag_grow (40); | |
7276 | } | |
7277 | ||
462427c4 | 7278 | mips_move_text_labels (); |
252b5132 RH |
7279 | |
7280 | #ifndef NO_ECOFF_DEBUGGING | |
7281 | if (ECOFF_DEBUGGING) | |
7282 | ecoff_fix_loc (old_frag, old_frag_offset); | |
7283 | #endif | |
7284 | } | |
71400594 RS |
7285 | } |
7286 | else if (mips_relax.sequence != 2 && prev_nop_frag != NULL) | |
7287 | { | |
932d1a1b RS |
7288 | int nops; |
7289 | ||
7290 | /* Work out how many nops in prev_nop_frag are needed by IP, | |
7291 | ignoring hazards generated by the first prev_nop_frag_since | |
7292 | instructions. */ | |
7293 | nops = nops_for_insn_or_target (prev_nop_frag_since, history, ip); | |
9c2799c2 | 7294 | gas_assert (nops <= prev_nop_frag_holds); |
252b5132 | 7295 | |
71400594 RS |
7296 | /* Enforce NOPS as a minimum. */ |
7297 | if (nops > prev_nop_frag_required) | |
7298 | prev_nop_frag_required = nops; | |
252b5132 | 7299 | |
71400594 RS |
7300 | if (prev_nop_frag_holds == prev_nop_frag_required) |
7301 | { | |
7302 | /* Settle for the current number of nops. Update the history | |
7303 | accordingly (for the benefit of any future .set reorder code). */ | |
7304 | prev_nop_frag = NULL; | |
7305 | insert_into_history (prev_nop_frag_since, | |
7306 | prev_nop_frag_holds, NOP_INSN); | |
7307 | } | |
7308 | else | |
7309 | { | |
7310 | /* Allow this instruction to replace one of the nops that was | |
7311 | tentatively added to prev_nop_frag. */ | |
df58fc94 | 7312 | prev_nop_frag->fr_fix -= NOP_INSN_SIZE; |
71400594 RS |
7313 | prev_nop_frag_holds--; |
7314 | prev_nop_frag_since++; | |
252b5132 RH |
7315 | } |
7316 | } | |
7317 | ||
e407c74b | 7318 | method = get_append_method (ip, address_expr, reloc_type); |
2b0c8b40 | 7319 | branch_disp = method == APPEND_SWAP ? insn_length (history) : 0; |
a4e06468 | 7320 | |
e410add4 RS |
7321 | dwarf2_emit_insn (0); |
7322 | /* We want MIPS16 and microMIPS debug info to use ISA-encoded addresses, | |
7323 | so "move" the instruction address accordingly. | |
7324 | ||
7325 | Also, it doesn't seem appropriate for the assembler to reorder .loc | |
7326 | entries. If this instruction is a branch that we are going to swap | |
7327 | with the previous instruction, the two instructions should be | |
7328 | treated as a unit, and the debug information for both instructions | |
7329 | should refer to the start of the branch sequence. Using the | |
7330 | current position is certainly wrong when swapping a 32-bit branch | |
7331 | and a 16-bit delay slot, since the current position would then be | |
7332 | in the middle of a branch. */ | |
7333 | dwarf2_move_insn ((HAVE_CODE_COMPRESSION ? 1 : 0) - branch_disp); | |
58e2ea4d | 7334 | |
df58fc94 RS |
7335 | relax32 = (mips_relax_branch |
7336 | /* Don't try branch relaxation within .set nomacro, or within | |
7337 | .set noat if we use $at for PIC computations. If it turns | |
7338 | out that the branch was out-of-range, we'll get an error. */ | |
7339 | && !mips_opts.warn_about_macros | |
7340 | && (mips_opts.at || mips_pic == NO_PIC) | |
3bf0dbfb MR |
7341 | /* Don't relax BPOSGE32/64 or BC1ANY2T/F and BC1ANY4T/F |
7342 | as they have no complementing branches. */ | |
7343 | && !(ip->insn_mo->ase & (ASE_MIPS3D | ASE_DSP64 | ASE_DSP))); | |
df58fc94 RS |
7344 | |
7345 | if (!HAVE_CODE_COMPRESSION | |
7346 | && address_expr | |
7347 | && relax32 | |
0b25d3e6 | 7348 | && *reloc_type == BFD_RELOC_16_PCREL_S2 |
11625dd8 | 7349 | && delayed_branch_p (ip)) |
4a6a3df4 | 7350 | { |
895921c9 | 7351 | relaxed_branch = TRUE; |
1e915849 RS |
7352 | add_relaxed_insn (ip, (relaxed_branch_length |
7353 | (NULL, NULL, | |
11625dd8 RS |
7354 | uncond_branch_p (ip) ? -1 |
7355 | : branch_likely_p (ip) ? 1 | |
1e915849 RS |
7356 | : 0)), 4, |
7357 | RELAX_BRANCH_ENCODE | |
ce8ad872 | 7358 | (AT, mips_pic != NO_PIC, |
11625dd8 RS |
7359 | uncond_branch_p (ip), |
7360 | branch_likely_p (ip), | |
1e915849 RS |
7361 | pinfo & INSN_WRITE_GPR_31, |
7362 | 0), | |
7363 | address_expr->X_add_symbol, | |
7364 | address_expr->X_add_number); | |
4a6a3df4 AO |
7365 | *reloc_type = BFD_RELOC_UNUSED; |
7366 | } | |
df58fc94 RS |
7367 | else if (mips_opts.micromips |
7368 | && address_expr | |
7369 | && ((relax32 && *reloc_type == BFD_RELOC_16_PCREL_S2) | |
7370 | || *reloc_type > BFD_RELOC_UNUSED) | |
40209cad MR |
7371 | && (delayed_branch_p (ip) || compact_branch_p (ip)) |
7372 | /* Don't try branch relaxation when users specify | |
7373 | 16-bit/32-bit instructions. */ | |
7374 | && !forced_insn_length) | |
df58fc94 | 7375 | { |
7bd374a4 MR |
7376 | bfd_boolean relax16 = (method != APPEND_ADD_COMPACT |
7377 | && *reloc_type > BFD_RELOC_UNUSED); | |
df58fc94 | 7378 | int type = relax16 ? *reloc_type - BFD_RELOC_UNUSED : 0; |
11625dd8 | 7379 | int uncond = uncond_branch_p (ip) ? -1 : 0; |
7bd374a4 MR |
7380 | int compact = compact_branch_p (ip) || method == APPEND_ADD_COMPACT; |
7381 | int nods = method == APPEND_ADD_WITH_NOP; | |
df58fc94 | 7382 | int al = pinfo & INSN_WRITE_GPR_31; |
7bd374a4 | 7383 | int length32 = nods ? 8 : 4; |
df58fc94 RS |
7384 | |
7385 | gas_assert (address_expr != NULL); | |
7386 | gas_assert (!mips_relax.sequence); | |
7387 | ||
2b0c8b40 | 7388 | relaxed_branch = TRUE; |
7bd374a4 MR |
7389 | if (nods) |
7390 | method = APPEND_ADD; | |
7391 | if (relax32) | |
7392 | length32 = relaxed_micromips_32bit_branch_length (NULL, NULL, uncond); | |
7393 | add_relaxed_insn (ip, length32, relax16 ? 2 : 4, | |
8484fb75 | 7394 | RELAX_MICROMIPS_ENCODE (type, AT, mips_opts.insn32, |
ce8ad872 | 7395 | mips_pic != NO_PIC, |
7bd374a4 | 7396 | uncond, compact, al, nods, |
40209cad | 7397 | relax32, 0, 0), |
df58fc94 RS |
7398 | address_expr->X_add_symbol, |
7399 | address_expr->X_add_number); | |
7400 | *reloc_type = BFD_RELOC_UNUSED; | |
7401 | } | |
7402 | else if (mips_opts.mips16 && *reloc_type > BFD_RELOC_UNUSED) | |
252b5132 | 7403 | { |
7fd53920 MR |
7404 | bfd_boolean require_unextended; |
7405 | bfd_boolean require_extended; | |
88a7ef16 MR |
7406 | symbolS *symbol; |
7407 | offsetT offset; | |
7408 | ||
7fd53920 MR |
7409 | if (forced_insn_length != 0) |
7410 | { | |
7411 | require_unextended = forced_insn_length == 2; | |
7412 | require_extended = forced_insn_length == 4; | |
7413 | } | |
7414 | else | |
7415 | { | |
7416 | require_unextended = (mips_opts.noautoextend | |
7417 | && !mips_opcode_32bit_p (ip->insn_mo)); | |
7418 | require_extended = 0; | |
7419 | } | |
7420 | ||
252b5132 | 7421 | /* We need to set up a variant frag. */ |
df58fc94 | 7422 | gas_assert (address_expr != NULL); |
88a7ef16 MR |
7423 | /* Pass any `O_symbol' expression unchanged as an `expr_section' |
7424 | symbol created by `make_expr_symbol' may not get a necessary | |
7425 | external relocation produced. */ | |
7426 | if (address_expr->X_op == O_symbol) | |
7427 | { | |
7428 | symbol = address_expr->X_add_symbol; | |
7429 | offset = address_expr->X_add_number; | |
7430 | } | |
7431 | else | |
7432 | { | |
7433 | symbol = make_expr_symbol (address_expr); | |
82d808ed | 7434 | symbol_append (symbol, symbol_lastP, &symbol_rootP, &symbol_lastP); |
88a7ef16 MR |
7435 | offset = 0; |
7436 | } | |
8507b6e7 | 7437 | add_relaxed_insn (ip, 12, 0, |
1e915849 RS |
7438 | RELAX_MIPS16_ENCODE |
7439 | (*reloc_type - BFD_RELOC_UNUSED, | |
8507b6e7 MR |
7440 | mips_pic != NO_PIC, |
7441 | HAVE_32BIT_SYMBOLS, | |
7442 | mips_opts.warn_about_macros, | |
7fd53920 | 7443 | require_unextended, require_extended, |
11625dd8 | 7444 | delayed_branch_p (&history[0]), |
1e915849 | 7445 | history[0].mips16_absolute_jump_p), |
88a7ef16 | 7446 | symbol, offset); |
252b5132 | 7447 | } |
5c04167a | 7448 | else if (mips_opts.mips16 && insn_length (ip) == 2) |
9497f5ac | 7449 | { |
11625dd8 | 7450 | if (!delayed_branch_p (ip)) |
b8ee1a6e DU |
7451 | /* Make sure there is enough room to swap this instruction with |
7452 | a following jump instruction. */ | |
7453 | frag_grow (6); | |
1e915849 | 7454 | add_fixed_insn (ip); |
252b5132 RH |
7455 | } |
7456 | else | |
7457 | { | |
7458 | if (mips_opts.mips16 | |
7459 | && mips_opts.noreorder | |
11625dd8 | 7460 | && delayed_branch_p (&history[0])) |
252b5132 RH |
7461 | as_warn (_("extended instruction in delay slot")); |
7462 | ||
4d7206a2 RS |
7463 | if (mips_relax.sequence) |
7464 | { | |
7465 | /* If we've reached the end of this frag, turn it into a variant | |
7466 | frag and record the information for the instructions we've | |
7467 | written so far. */ | |
7468 | if (frag_room () < 4) | |
7469 | relax_close_frag (); | |
df58fc94 | 7470 | mips_relax.sizes[mips_relax.sequence - 1] += insn_length (ip); |
4d7206a2 RS |
7471 | } |
7472 | ||
584892a6 | 7473 | if (mips_relax.sequence != 2) |
df58fc94 RS |
7474 | { |
7475 | if (mips_macro_warning.first_insn_sizes[0] == 0) | |
7476 | mips_macro_warning.first_insn_sizes[0] = insn_length (ip); | |
7477 | mips_macro_warning.sizes[0] += insn_length (ip); | |
7478 | mips_macro_warning.insns[0]++; | |
7479 | } | |
584892a6 | 7480 | if (mips_relax.sequence != 1) |
df58fc94 RS |
7481 | { |
7482 | if (mips_macro_warning.first_insn_sizes[1] == 0) | |
7483 | mips_macro_warning.first_insn_sizes[1] = insn_length (ip); | |
7484 | mips_macro_warning.sizes[1] += insn_length (ip); | |
7485 | mips_macro_warning.insns[1]++; | |
7486 | } | |
584892a6 | 7487 | |
1e915849 RS |
7488 | if (mips_opts.mips16) |
7489 | { | |
7490 | ip->fixed_p = 1; | |
7491 | ip->mips16_absolute_jump_p = (*reloc_type == BFD_RELOC_MIPS16_JMP); | |
7492 | } | |
7493 | add_fixed_insn (ip); | |
252b5132 RH |
7494 | } |
7495 | ||
9fe77896 | 7496 | if (!ip->complete_p && *reloc_type < BFD_RELOC_UNUSED) |
252b5132 | 7497 | { |
df58fc94 | 7498 | bfd_reloc_code_real_type final_type[3]; |
2309ddf2 | 7499 | reloc_howto_type *howto0; |
9fe77896 RS |
7500 | reloc_howto_type *howto; |
7501 | int i; | |
34ce925e | 7502 | |
df58fc94 RS |
7503 | /* Perform any necessary conversion to microMIPS relocations |
7504 | and find out how many relocations there actually are. */ | |
7505 | for (i = 0; i < 3 && reloc_type[i] != BFD_RELOC_UNUSED; i++) | |
7506 | final_type[i] = micromips_map_reloc (reloc_type[i]); | |
7507 | ||
9fe77896 RS |
7508 | /* In a compound relocation, it is the final (outermost) |
7509 | operator that determines the relocated field. */ | |
2309ddf2 | 7510 | howto = howto0 = bfd_reloc_type_lookup (stdoutput, final_type[i - 1]); |
e8044f35 RS |
7511 | if (!howto) |
7512 | abort (); | |
2309ddf2 MR |
7513 | |
7514 | if (i > 1) | |
7515 | howto0 = bfd_reloc_type_lookup (stdoutput, final_type[0]); | |
9fe77896 RS |
7516 | ip->fixp[0] = fix_new_exp (ip->frag, ip->where, |
7517 | bfd_get_reloc_size (howto), | |
7518 | address_expr, | |
2309ddf2 MR |
7519 | howto0 && howto0->pc_relative, |
7520 | final_type[0]); | |
ce8ad872 MR |
7521 | /* Record non-PIC mode in `fx_tcbit2' for `md_apply_fix'. */ |
7522 | ip->fixp[0]->fx_tcbit2 = mips_pic == NO_PIC; | |
9fe77896 RS |
7523 | |
7524 | /* Tag symbols that have a R_MIPS16_26 relocation against them. */ | |
2309ddf2 | 7525 | if (final_type[0] == BFD_RELOC_MIPS16_JMP && ip->fixp[0]->fx_addsy) |
9fe77896 RS |
7526 | *symbol_get_tc (ip->fixp[0]->fx_addsy) = 1; |
7527 | ||
7528 | /* These relocations can have an addend that won't fit in | |
7529 | 4 octets for 64bit assembly. */ | |
bad1aba3 | 7530 | if (GPR_SIZE == 64 |
9fe77896 RS |
7531 | && ! howto->partial_inplace |
7532 | && (reloc_type[0] == BFD_RELOC_16 | |
7533 | || reloc_type[0] == BFD_RELOC_32 | |
7534 | || reloc_type[0] == BFD_RELOC_MIPS_JMP | |
7535 | || reloc_type[0] == BFD_RELOC_GPREL16 | |
7536 | || reloc_type[0] == BFD_RELOC_MIPS_LITERAL | |
7537 | || reloc_type[0] == BFD_RELOC_GPREL32 | |
7538 | || reloc_type[0] == BFD_RELOC_64 | |
7539 | || reloc_type[0] == BFD_RELOC_CTOR | |
7540 | || reloc_type[0] == BFD_RELOC_MIPS_SUB | |
7541 | || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST | |
7542 | || reloc_type[0] == BFD_RELOC_MIPS_HIGHER | |
7543 | || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP | |
7544 | || reloc_type[0] == BFD_RELOC_MIPS_REL16 | |
7545 | || reloc_type[0] == BFD_RELOC_MIPS_RELGOT | |
7546 | || reloc_type[0] == BFD_RELOC_MIPS16_GPREL | |
7547 | || hi16_reloc_p (reloc_type[0]) | |
7548 | || lo16_reloc_p (reloc_type[0]))) | |
7549 | ip->fixp[0]->fx_no_overflow = 1; | |
7550 | ||
ddaf2c41 MR |
7551 | /* These relocations can have an addend that won't fit in 2 octets. */ |
7552 | if (reloc_type[0] == BFD_RELOC_MICROMIPS_7_PCREL_S1 | |
7553 | || reloc_type[0] == BFD_RELOC_MICROMIPS_10_PCREL_S1) | |
7554 | ip->fixp[0]->fx_no_overflow = 1; | |
7555 | ||
9fe77896 RS |
7556 | if (mips_relax.sequence) |
7557 | { | |
7558 | if (mips_relax.first_fixup == 0) | |
7559 | mips_relax.first_fixup = ip->fixp[0]; | |
7560 | } | |
7561 | else if (reloc_needs_lo_p (*reloc_type)) | |
7562 | { | |
7563 | struct mips_hi_fixup *hi_fixup; | |
7564 | ||
7565 | /* Reuse the last entry if it already has a matching %lo. */ | |
7566 | hi_fixup = mips_hi_fixup_list; | |
7567 | if (hi_fixup == 0 | |
7568 | || !fixup_has_matching_lo_p (hi_fixup->fixp)) | |
4d7206a2 | 7569 | { |
325801bd | 7570 | hi_fixup = XNEW (struct mips_hi_fixup); |
9fe77896 RS |
7571 | hi_fixup->next = mips_hi_fixup_list; |
7572 | mips_hi_fixup_list = hi_fixup; | |
4d7206a2 | 7573 | } |
9fe77896 RS |
7574 | hi_fixup->fixp = ip->fixp[0]; |
7575 | hi_fixup->seg = now_seg; | |
7576 | } | |
252b5132 | 7577 | |
9fe77896 RS |
7578 | /* Add fixups for the second and third relocations, if given. |
7579 | Note that the ABI allows the second relocation to be | |
7580 | against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the | |
7581 | moment we only use RSS_UNDEF, but we could add support | |
7582 | for the others if it ever becomes necessary. */ | |
7583 | for (i = 1; i < 3; i++) | |
7584 | if (reloc_type[i] != BFD_RELOC_UNUSED) | |
7585 | { | |
7586 | ip->fixp[i] = fix_new (ip->frag, ip->where, | |
7587 | ip->fixp[0]->fx_size, NULL, 0, | |
df58fc94 | 7588 | FALSE, final_type[i]); |
f6688943 | 7589 | |
9fe77896 RS |
7590 | /* Use fx_tcbit to mark compound relocs. */ |
7591 | ip->fixp[0]->fx_tcbit = 1; | |
7592 | ip->fixp[i]->fx_tcbit = 1; | |
7593 | } | |
252b5132 | 7594 | } |
252b5132 RH |
7595 | |
7596 | /* Update the register mask information. */ | |
4c260379 RS |
7597 | mips_gprmask |= gpr_read_mask (ip) | gpr_write_mask (ip); |
7598 | mips_cprmask[1] |= fpr_read_mask (ip) | fpr_write_mask (ip); | |
252b5132 | 7599 | |
a4e06468 | 7600 | switch (method) |
252b5132 | 7601 | { |
a4e06468 RS |
7602 | case APPEND_ADD: |
7603 | insert_into_history (0, 1, ip); | |
7604 | break; | |
7605 | ||
7606 | case APPEND_ADD_WITH_NOP: | |
14fe068b RS |
7607 | { |
7608 | struct mips_cl_insn *nop; | |
7609 | ||
7610 | insert_into_history (0, 1, ip); | |
7611 | nop = get_delay_slot_nop (ip); | |
7612 | add_fixed_insn (nop); | |
7613 | insert_into_history (0, 1, nop); | |
7614 | if (mips_relax.sequence) | |
7615 | mips_relax.sizes[mips_relax.sequence - 1] += insn_length (nop); | |
7616 | } | |
a4e06468 RS |
7617 | break; |
7618 | ||
7619 | case APPEND_ADD_COMPACT: | |
7620 | /* Convert MIPS16 jr/jalr into a "compact" jump. */ | |
7bd374a4 MR |
7621 | if (mips_opts.mips16) |
7622 | { | |
7623 | ip->insn_opcode |= 0x0080; | |
7624 | find_altered_mips16_opcode (ip); | |
7625 | } | |
7626 | /* Convert microMIPS instructions. */ | |
7627 | else if (mips_opts.micromips) | |
7628 | { | |
7629 | /* jr16->jrc */ | |
7630 | if ((ip->insn_opcode & 0xffe0) == 0x4580) | |
7631 | ip->insn_opcode |= 0x0020; | |
7632 | /* b16->bc */ | |
7633 | else if ((ip->insn_opcode & 0xfc00) == 0xcc00) | |
7634 | ip->insn_opcode = 0x40e00000; | |
7635 | /* beqz16->beqzc, bnez16->bnezc */ | |
7636 | else if ((ip->insn_opcode & 0xdc00) == 0x8c00) | |
7637 | { | |
7638 | unsigned long regno; | |
7639 | ||
7640 | regno = ip->insn_opcode >> MICROMIPSOP_SH_MD; | |
7641 | regno &= MICROMIPSOP_MASK_MD; | |
7642 | regno = micromips_to_32_reg_d_map[regno]; | |
7643 | ip->insn_opcode = (((ip->insn_opcode << 9) & 0x00400000) | |
7644 | | (regno << MICROMIPSOP_SH_RS) | |
7645 | | 0x40a00000) ^ 0x00400000; | |
7646 | } | |
7647 | /* beqz->beqzc, bnez->bnezc */ | |
7648 | else if ((ip->insn_opcode & 0xdfe00000) == 0x94000000) | |
7649 | ip->insn_opcode = ((ip->insn_opcode & 0x001f0000) | |
7650 | | ((ip->insn_opcode >> 7) & 0x00400000) | |
7651 | | 0x40a00000) ^ 0x00400000; | |
7652 | /* beq $0->beqzc, bne $0->bnezc */ | |
7653 | else if ((ip->insn_opcode & 0xdc1f0000) == 0x94000000) | |
7654 | ip->insn_opcode = (((ip->insn_opcode >> | |
7655 | (MICROMIPSOP_SH_RT - MICROMIPSOP_SH_RS)) | |
7656 | & (MICROMIPSOP_MASK_RS << MICROMIPSOP_SH_RS)) | |
7657 | | ((ip->insn_opcode >> 7) & 0x00400000) | |
7658 | | 0x40a00000) ^ 0x00400000; | |
7659 | else | |
7660 | abort (); | |
7661 | find_altered_micromips_opcode (ip); | |
7662 | } | |
7663 | else | |
7664 | abort (); | |
a4e06468 RS |
7665 | install_insn (ip); |
7666 | insert_into_history (0, 1, ip); | |
7667 | break; | |
7668 | ||
7669 | case APPEND_SWAP: | |
7670 | { | |
7671 | struct mips_cl_insn delay = history[0]; | |
99e7978b MF |
7672 | |
7673 | if (relaxed_branch || delay.frag != ip->frag) | |
a4e06468 RS |
7674 | { |
7675 | /* Add the delay slot instruction to the end of the | |
7676 | current frag and shrink the fixed part of the | |
7677 | original frag. If the branch occupies the tail of | |
7678 | the latter, move it backwards to cover the gap. */ | |
2b0c8b40 | 7679 | delay.frag->fr_fix -= branch_disp; |
a4e06468 | 7680 | if (delay.frag == ip->frag) |
2b0c8b40 | 7681 | move_insn (ip, ip->frag, ip->where - branch_disp); |
a4e06468 RS |
7682 | add_fixed_insn (&delay); |
7683 | } | |
7684 | else | |
7685 | { | |
5e35670b MR |
7686 | /* If this is not a relaxed branch and we are in the |
7687 | same frag, then just swap the instructions. */ | |
7688 | move_insn (ip, delay.frag, delay.where); | |
7689 | move_insn (&delay, ip->frag, ip->where + insn_length (ip)); | |
a4e06468 RS |
7690 | } |
7691 | history[0] = *ip; | |
7692 | delay.fixed_p = 1; | |
7693 | insert_into_history (0, 1, &delay); | |
7694 | } | |
7695 | break; | |
252b5132 RH |
7696 | } |
7697 | ||
13408f1e | 7698 | /* If we have just completed an unconditional branch, clear the history. */ |
11625dd8 RS |
7699 | if ((delayed_branch_p (&history[1]) && uncond_branch_p (&history[1])) |
7700 | || (compact_branch_p (&history[0]) && uncond_branch_p (&history[0]))) | |
e407c74b NC |
7701 | { |
7702 | unsigned int i; | |
7703 | ||
79850f26 | 7704 | mips_no_prev_insn (); |
13408f1e | 7705 | |
e407c74b | 7706 | for (i = 0; i < ARRAY_SIZE (history); i++) |
79850f26 | 7707 | history[i].cleared_p = 1; |
e407c74b NC |
7708 | } |
7709 | ||
df58fc94 RS |
7710 | /* We need to emit a label at the end of branch-likely macros. */ |
7711 | if (emit_branch_likely_macro) | |
7712 | { | |
7713 | emit_branch_likely_macro = FALSE; | |
7714 | micromips_add_label (); | |
7715 | } | |
7716 | ||
252b5132 RH |
7717 | /* We just output an insn, so the next one doesn't have a label. */ |
7718 | mips_clear_insn_labels (); | |
252b5132 RH |
7719 | } |
7720 | ||
e407c74b NC |
7721 | /* Forget that there was any previous instruction or label. |
7722 | When BRANCH is true, the branch history is also flushed. */ | |
252b5132 RH |
7723 | |
7724 | static void | |
7d10b47d | 7725 | mips_no_prev_insn (void) |
252b5132 | 7726 | { |
7d10b47d RS |
7727 | prev_nop_frag = NULL; |
7728 | insert_into_history (0, ARRAY_SIZE (history), NOP_INSN); | |
252b5132 RH |
7729 | mips_clear_insn_labels (); |
7730 | } | |
7731 | ||
7d10b47d RS |
7732 | /* This function must be called before we emit something other than |
7733 | instructions. It is like mips_no_prev_insn except that it inserts | |
7734 | any NOPS that might be needed by previous instructions. */ | |
252b5132 | 7735 | |
7d10b47d RS |
7736 | void |
7737 | mips_emit_delays (void) | |
252b5132 RH |
7738 | { |
7739 | if (! mips_opts.noreorder) | |
7740 | { | |
932d1a1b | 7741 | int nops = nops_for_insn (0, history, NULL); |
252b5132 RH |
7742 | if (nops > 0) |
7743 | { | |
7d10b47d RS |
7744 | while (nops-- > 0) |
7745 | add_fixed_insn (NOP_INSN); | |
462427c4 | 7746 | mips_move_text_labels (); |
7d10b47d RS |
7747 | } |
7748 | } | |
7749 | mips_no_prev_insn (); | |
7750 | } | |
7751 | ||
7752 | /* Start a (possibly nested) noreorder block. */ | |
7753 | ||
7754 | static void | |
7755 | start_noreorder (void) | |
7756 | { | |
7757 | if (mips_opts.noreorder == 0) | |
7758 | { | |
7759 | unsigned int i; | |
7760 | int nops; | |
7761 | ||
7762 | /* None of the instructions before the .set noreorder can be moved. */ | |
7763 | for (i = 0; i < ARRAY_SIZE (history); i++) | |
7764 | history[i].fixed_p = 1; | |
7765 | ||
7766 | /* Insert any nops that might be needed between the .set noreorder | |
7767 | block and the previous instructions. We will later remove any | |
7768 | nops that turn out not to be needed. */ | |
932d1a1b | 7769 | nops = nops_for_insn (0, history, NULL); |
7d10b47d RS |
7770 | if (nops > 0) |
7771 | { | |
7772 | if (mips_optimize != 0) | |
252b5132 RH |
7773 | { |
7774 | /* Record the frag which holds the nop instructions, so | |
7775 | that we can remove them if we don't need them. */ | |
df58fc94 | 7776 | frag_grow (nops * NOP_INSN_SIZE); |
252b5132 RH |
7777 | prev_nop_frag = frag_now; |
7778 | prev_nop_frag_holds = nops; | |
7779 | prev_nop_frag_required = 0; | |
7780 | prev_nop_frag_since = 0; | |
7781 | } | |
7782 | ||
7783 | for (; nops > 0; --nops) | |
1e915849 | 7784 | add_fixed_insn (NOP_INSN); |
252b5132 | 7785 | |
7d10b47d RS |
7786 | /* Move on to a new frag, so that it is safe to simply |
7787 | decrease the size of prev_nop_frag. */ | |
7788 | frag_wane (frag_now); | |
7789 | frag_new (0); | |
462427c4 | 7790 | mips_move_text_labels (); |
252b5132 | 7791 | } |
df58fc94 | 7792 | mips_mark_labels (); |
7d10b47d | 7793 | mips_clear_insn_labels (); |
252b5132 | 7794 | } |
7d10b47d RS |
7795 | mips_opts.noreorder++; |
7796 | mips_any_noreorder = 1; | |
7797 | } | |
252b5132 | 7798 | |
7d10b47d | 7799 | /* End a nested noreorder block. */ |
252b5132 | 7800 | |
7d10b47d RS |
7801 | static void |
7802 | end_noreorder (void) | |
7803 | { | |
7804 | mips_opts.noreorder--; | |
7805 | if (mips_opts.noreorder == 0 && prev_nop_frag != NULL) | |
7806 | { | |
7807 | /* Commit to inserting prev_nop_frag_required nops and go back to | |
7808 | handling nop insertion the .set reorder way. */ | |
7809 | prev_nop_frag->fr_fix -= ((prev_nop_frag_holds - prev_nop_frag_required) | |
df58fc94 | 7810 | * NOP_INSN_SIZE); |
7d10b47d RS |
7811 | insert_into_history (prev_nop_frag_since, |
7812 | prev_nop_frag_required, NOP_INSN); | |
7813 | prev_nop_frag = NULL; | |
7814 | } | |
252b5132 RH |
7815 | } |
7816 | ||
97d87491 RS |
7817 | /* Sign-extend 32-bit mode constants that have bit 31 set and all |
7818 | higher bits unset. */ | |
7819 | ||
7820 | static void | |
7821 | normalize_constant_expr (expressionS *ex) | |
7822 | { | |
7823 | if (ex->X_op == O_constant | |
7824 | && IS_ZEXT_32BIT_NUM (ex->X_add_number)) | |
7825 | ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000) | |
7826 | - 0x80000000); | |
7827 | } | |
7828 | ||
7829 | /* Sign-extend 32-bit mode address offsets that have bit 31 set and | |
7830 | all higher bits unset. */ | |
7831 | ||
7832 | static void | |
7833 | normalize_address_expr (expressionS *ex) | |
7834 | { | |
7835 | if (((ex->X_op == O_constant && HAVE_32BIT_ADDRESSES) | |
7836 | || (ex->X_op == O_symbol && HAVE_32BIT_SYMBOLS)) | |
7837 | && IS_ZEXT_32BIT_NUM (ex->X_add_number)) | |
7838 | ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000) | |
7839 | - 0x80000000); | |
7840 | } | |
7841 | ||
7842 | /* Try to match TOKENS against OPCODE, storing the result in INSN. | |
7843 | Return true if the match was successful. | |
7844 | ||
7845 | OPCODE_EXTRA is a value that should be ORed into the opcode | |
7846 | (used for VU0 channel suffixes, etc.). MORE_ALTS is true if | |
7847 | there are more alternatives after OPCODE and SOFT_MATCH is | |
7848 | as for mips_arg_info. */ | |
7849 | ||
7850 | static bfd_boolean | |
7851 | match_insn (struct mips_cl_insn *insn, const struct mips_opcode *opcode, | |
7852 | struct mips_operand_token *tokens, unsigned int opcode_extra, | |
60f20e8b | 7853 | bfd_boolean lax_match, bfd_boolean complete_p) |
97d87491 RS |
7854 | { |
7855 | const char *args; | |
7856 | struct mips_arg_info arg; | |
7857 | const struct mips_operand *operand; | |
7858 | char c; | |
7859 | ||
7860 | imm_expr.X_op = O_absent; | |
97d87491 RS |
7861 | offset_expr.X_op = O_absent; |
7862 | offset_reloc[0] = BFD_RELOC_UNUSED; | |
7863 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
7864 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
7865 | ||
7866 | create_insn (insn, opcode); | |
60f20e8b RS |
7867 | /* When no opcode suffix is specified, assume ".xyzw". */ |
7868 | if ((opcode->pinfo2 & INSN2_VU0_CHANNEL_SUFFIX) != 0 && opcode_extra == 0) | |
7869 | insn->insn_opcode |= 0xf << mips_vu0_channel_mask.lsb; | |
7870 | else | |
7871 | insn->insn_opcode |= opcode_extra; | |
97d87491 RS |
7872 | memset (&arg, 0, sizeof (arg)); |
7873 | arg.insn = insn; | |
7874 | arg.token = tokens; | |
7875 | arg.argnum = 1; | |
7876 | arg.last_regno = ILLEGAL_REG; | |
7877 | arg.dest_regno = ILLEGAL_REG; | |
60f20e8b | 7878 | arg.lax_match = lax_match; |
97d87491 RS |
7879 | for (args = opcode->args;; ++args) |
7880 | { | |
7881 | if (arg.token->type == OT_END) | |
7882 | { | |
7883 | /* Handle unary instructions in which only one operand is given. | |
7884 | The source is then the same as the destination. */ | |
7885 | if (arg.opnum == 1 && *args == ',') | |
7886 | { | |
7887 | operand = (mips_opts.micromips | |
7888 | ? decode_micromips_operand (args + 1) | |
7889 | : decode_mips_operand (args + 1)); | |
7890 | if (operand && mips_optional_operand_p (operand)) | |
7891 | { | |
7892 | arg.token = tokens; | |
7893 | arg.argnum = 1; | |
7894 | continue; | |
7895 | } | |
7896 | } | |
7897 | ||
7898 | /* Treat elided base registers as $0. */ | |
7899 | if (strcmp (args, "(b)") == 0) | |
7900 | args += 3; | |
7901 | ||
7902 | if (args[0] == '+') | |
7903 | switch (args[1]) | |
7904 | { | |
7905 | case 'K': | |
7906 | case 'N': | |
7907 | /* The register suffix is optional. */ | |
7908 | args += 2; | |
7909 | break; | |
7910 | } | |
7911 | ||
7912 | /* Fail the match if there were too few operands. */ | |
7913 | if (*args) | |
7914 | return FALSE; | |
7915 | ||
7916 | /* Successful match. */ | |
60f20e8b RS |
7917 | if (!complete_p) |
7918 | return TRUE; | |
e3de51ce | 7919 | clear_insn_error (); |
97d87491 RS |
7920 | if (arg.dest_regno == arg.last_regno |
7921 | && strncmp (insn->insn_mo->name, "jalr", 4) == 0) | |
7922 | { | |
7923 | if (arg.opnum == 2) | |
e3de51ce | 7924 | set_insn_error |
1661c76c | 7925 | (0, _("source and destination must be different")); |
97d87491 | 7926 | else if (arg.last_regno == 31) |
e3de51ce | 7927 | set_insn_error |
1661c76c | 7928 | (0, _("a destination register must be supplied")); |
97d87491 | 7929 | } |
173d3447 CF |
7930 | else if (arg.last_regno == 31 |
7931 | && (strncmp (insn->insn_mo->name, "bltzal", 6) == 0 | |
7932 | || strncmp (insn->insn_mo->name, "bgezal", 6) == 0)) | |
7933 | set_insn_error (0, _("the source register must not be $31")); | |
97d87491 RS |
7934 | check_completed_insn (&arg); |
7935 | return TRUE; | |
7936 | } | |
7937 | ||
7938 | /* Fail the match if the line has too many operands. */ | |
7939 | if (*args == 0) | |
7940 | return FALSE; | |
7941 | ||
7942 | /* Handle characters that need to match exactly. */ | |
7943 | if (*args == '(' || *args == ')' || *args == ',') | |
7944 | { | |
7945 | if (match_char (&arg, *args)) | |
7946 | continue; | |
7947 | return FALSE; | |
7948 | } | |
7949 | if (*args == '#') | |
7950 | { | |
7951 | ++args; | |
7952 | if (arg.token->type == OT_DOUBLE_CHAR | |
7953 | && arg.token->u.ch == *args) | |
7954 | { | |
7955 | ++arg.token; | |
7956 | continue; | |
7957 | } | |
7958 | return FALSE; | |
7959 | } | |
7960 | ||
7961 | /* Handle special macro operands. Work out the properties of | |
7962 | other operands. */ | |
7963 | arg.opnum += 1; | |
97d87491 RS |
7964 | switch (*args) |
7965 | { | |
7361da2c AB |
7966 | case '-': |
7967 | switch (args[1]) | |
7968 | { | |
7969 | case 'A': | |
7970 | *offset_reloc = BFD_RELOC_MIPS_19_PCREL_S2; | |
7971 | break; | |
7972 | ||
7973 | case 'B': | |
7974 | *offset_reloc = BFD_RELOC_MIPS_18_PCREL_S3; | |
7975 | break; | |
7976 | } | |
7977 | break; | |
7978 | ||
97d87491 RS |
7979 | case '+': |
7980 | switch (args[1]) | |
7981 | { | |
97d87491 RS |
7982 | case 'i': |
7983 | *offset_reloc = BFD_RELOC_MIPS_JMP; | |
7984 | break; | |
7361da2c AB |
7985 | |
7986 | case '\'': | |
7987 | *offset_reloc = BFD_RELOC_MIPS_26_PCREL_S2; | |
7988 | break; | |
7989 | ||
7990 | case '\"': | |
7991 | *offset_reloc = BFD_RELOC_MIPS_21_PCREL_S2; | |
7992 | break; | |
97d87491 RS |
7993 | } |
7994 | break; | |
7995 | ||
97d87491 | 7996 | case 'I': |
1a00e612 RS |
7997 | if (!match_const_int (&arg, &imm_expr.X_add_number)) |
7998 | return FALSE; | |
7999 | imm_expr.X_op = O_constant; | |
bad1aba3 | 8000 | if (GPR_SIZE == 32) |
97d87491 RS |
8001 | normalize_constant_expr (&imm_expr); |
8002 | continue; | |
8003 | ||
8004 | case 'A': | |
8005 | if (arg.token->type == OT_CHAR && arg.token->u.ch == '(') | |
8006 | { | |
8007 | /* Assume that the offset has been elided and that what | |
8008 | we saw was a base register. The match will fail later | |
8009 | if that assumption turns out to be wrong. */ | |
8010 | offset_expr.X_op = O_constant; | |
8011 | offset_expr.X_add_number = 0; | |
8012 | } | |
97d87491 | 8013 | else |
1a00e612 RS |
8014 | { |
8015 | if (!match_expression (&arg, &offset_expr, offset_reloc)) | |
8016 | return FALSE; | |
8017 | normalize_address_expr (&offset_expr); | |
8018 | } | |
97d87491 RS |
8019 | continue; |
8020 | ||
8021 | case 'F': | |
8022 | if (!match_float_constant (&arg, &imm_expr, &offset_expr, | |
8023 | 8, TRUE)) | |
1a00e612 | 8024 | return FALSE; |
97d87491 RS |
8025 | continue; |
8026 | ||
8027 | case 'L': | |
8028 | if (!match_float_constant (&arg, &imm_expr, &offset_expr, | |
8029 | 8, FALSE)) | |
1a00e612 | 8030 | return FALSE; |
97d87491 RS |
8031 | continue; |
8032 | ||
8033 | case 'f': | |
8034 | if (!match_float_constant (&arg, &imm_expr, &offset_expr, | |
8035 | 4, TRUE)) | |
1a00e612 | 8036 | return FALSE; |
97d87491 RS |
8037 | continue; |
8038 | ||
8039 | case 'l': | |
8040 | if (!match_float_constant (&arg, &imm_expr, &offset_expr, | |
8041 | 4, FALSE)) | |
1a00e612 | 8042 | return FALSE; |
97d87491 RS |
8043 | continue; |
8044 | ||
97d87491 RS |
8045 | case 'p': |
8046 | *offset_reloc = BFD_RELOC_16_PCREL_S2; | |
8047 | break; | |
8048 | ||
8049 | case 'a': | |
8050 | *offset_reloc = BFD_RELOC_MIPS_JMP; | |
8051 | break; | |
8052 | ||
8053 | case 'm': | |
8054 | gas_assert (mips_opts.micromips); | |
8055 | c = args[1]; | |
8056 | switch (c) | |
8057 | { | |
8058 | case 'D': | |
8059 | case 'E': | |
8060 | if (!forced_insn_length) | |
8061 | *offset_reloc = (int) BFD_RELOC_UNUSED + c; | |
8062 | else if (c == 'D') | |
8063 | *offset_reloc = BFD_RELOC_MICROMIPS_10_PCREL_S1; | |
8064 | else | |
8065 | *offset_reloc = BFD_RELOC_MICROMIPS_7_PCREL_S1; | |
8066 | break; | |
8067 | } | |
8068 | break; | |
8069 | } | |
8070 | ||
8071 | operand = (mips_opts.micromips | |
8072 | ? decode_micromips_operand (args) | |
8073 | : decode_mips_operand (args)); | |
8074 | if (!operand) | |
8075 | abort (); | |
8076 | ||
8077 | /* Skip prefixes. */ | |
7361da2c | 8078 | if (*args == '+' || *args == 'm' || *args == '-') |
97d87491 RS |
8079 | args++; |
8080 | ||
8081 | if (mips_optional_operand_p (operand) | |
8082 | && args[1] == ',' | |
8083 | && (arg.token[0].type != OT_REG | |
8084 | || arg.token[1].type == OT_END)) | |
8085 | { | |
8086 | /* Assume that the register has been elided and is the | |
8087 | same as the first operand. */ | |
8088 | arg.token = tokens; | |
8089 | arg.argnum = 1; | |
8090 | } | |
8091 | ||
8092 | if (!match_operand (&arg, operand)) | |
8093 | return FALSE; | |
8094 | } | |
8095 | } | |
8096 | ||
8097 | /* Like match_insn, but for MIPS16. */ | |
8098 | ||
8099 | static bfd_boolean | |
8100 | match_mips16_insn (struct mips_cl_insn *insn, const struct mips_opcode *opcode, | |
1a00e612 | 8101 | struct mips_operand_token *tokens) |
97d87491 RS |
8102 | { |
8103 | const char *args; | |
8104 | const struct mips_operand *operand; | |
8105 | const struct mips_operand *ext_operand; | |
82d808ed | 8106 | bfd_boolean pcrel = FALSE; |
7fd53920 | 8107 | int required_insn_length; |
97d87491 RS |
8108 | struct mips_arg_info arg; |
8109 | int relax_char; | |
8110 | ||
7fd53920 MR |
8111 | if (forced_insn_length) |
8112 | required_insn_length = forced_insn_length; | |
8113 | else if (mips_opts.noautoextend && !mips_opcode_32bit_p (opcode)) | |
8114 | required_insn_length = 2; | |
8115 | else | |
8116 | required_insn_length = 0; | |
8117 | ||
97d87491 RS |
8118 | create_insn (insn, opcode); |
8119 | imm_expr.X_op = O_absent; | |
97d87491 RS |
8120 | offset_expr.X_op = O_absent; |
8121 | offset_reloc[0] = BFD_RELOC_UNUSED; | |
8122 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
8123 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
8124 | relax_char = 0; | |
8125 | ||
8126 | memset (&arg, 0, sizeof (arg)); | |
8127 | arg.insn = insn; | |
8128 | arg.token = tokens; | |
8129 | arg.argnum = 1; | |
8130 | arg.last_regno = ILLEGAL_REG; | |
8131 | arg.dest_regno = ILLEGAL_REG; | |
97d87491 RS |
8132 | relax_char = 0; |
8133 | for (args = opcode->args;; ++args) | |
8134 | { | |
8135 | int c; | |
8136 | ||
8137 | if (arg.token->type == OT_END) | |
8138 | { | |
8139 | offsetT value; | |
8140 | ||
8141 | /* Handle unary instructions in which only one operand is given. | |
8142 | The source is then the same as the destination. */ | |
8143 | if (arg.opnum == 1 && *args == ',') | |
8144 | { | |
8145 | operand = decode_mips16_operand (args[1], FALSE); | |
8146 | if (operand && mips_optional_operand_p (operand)) | |
8147 | { | |
8148 | arg.token = tokens; | |
8149 | arg.argnum = 1; | |
8150 | continue; | |
8151 | } | |
8152 | } | |
8153 | ||
8154 | /* Fail the match if there were too few operands. */ | |
8155 | if (*args) | |
8156 | return FALSE; | |
8157 | ||
8158 | /* Successful match. Stuff the immediate value in now, if | |
8159 | we can. */ | |
e3de51ce | 8160 | clear_insn_error (); |
97d87491 RS |
8161 | if (opcode->pinfo == INSN_MACRO) |
8162 | { | |
8163 | gas_assert (relax_char == 0 || relax_char == 'p'); | |
8164 | gas_assert (*offset_reloc == BFD_RELOC_UNUSED); | |
8165 | } | |
8166 | else if (relax_char | |
8167 | && offset_expr.X_op == O_constant | |
82d808ed | 8168 | && !pcrel |
97d87491 RS |
8169 | && calculate_reloc (*offset_reloc, |
8170 | offset_expr.X_add_number, | |
8171 | &value)) | |
8172 | { | |
8173 | mips16_immed (NULL, 0, relax_char, *offset_reloc, value, | |
7fd53920 | 8174 | required_insn_length, &insn->insn_opcode); |
97d87491 RS |
8175 | offset_expr.X_op = O_absent; |
8176 | *offset_reloc = BFD_RELOC_UNUSED; | |
8177 | } | |
8178 | else if (relax_char && *offset_reloc != BFD_RELOC_UNUSED) | |
8179 | { | |
7fd53920 | 8180 | if (required_insn_length == 2) |
e3de51ce | 8181 | set_insn_error (0, _("invalid unextended operand value")); |
1da43acc MR |
8182 | else |
8183 | { | |
8184 | forced_insn_length = 4; | |
8185 | insn->insn_opcode |= MIPS16_EXTEND; | |
8186 | } | |
97d87491 RS |
8187 | } |
8188 | else if (relax_char) | |
8189 | *offset_reloc = (int) BFD_RELOC_UNUSED + relax_char; | |
8190 | ||
8191 | check_completed_insn (&arg); | |
8192 | return TRUE; | |
8193 | } | |
8194 | ||
8195 | /* Fail the match if the line has too many operands. */ | |
8196 | if (*args == 0) | |
8197 | return FALSE; | |
8198 | ||
8199 | /* Handle characters that need to match exactly. */ | |
8200 | if (*args == '(' || *args == ')' || *args == ',') | |
8201 | { | |
8202 | if (match_char (&arg, *args)) | |
8203 | continue; | |
8204 | return FALSE; | |
8205 | } | |
8206 | ||
8207 | arg.opnum += 1; | |
8208 | c = *args; | |
8209 | switch (c) | |
8210 | { | |
8211 | case 'p': | |
8212 | case 'q': | |
8213 | case 'A': | |
8214 | case 'B': | |
8215 | case 'E': | |
8216 | relax_char = c; | |
8217 | break; | |
8218 | ||
8219 | case 'I': | |
1a00e612 RS |
8220 | if (!match_const_int (&arg, &imm_expr.X_add_number)) |
8221 | return FALSE; | |
8222 | imm_expr.X_op = O_constant; | |
bad1aba3 | 8223 | if (GPR_SIZE == 32) |
97d87491 RS |
8224 | normalize_constant_expr (&imm_expr); |
8225 | continue; | |
8226 | ||
8227 | case 'a': | |
8228 | case 'i': | |
8229 | *offset_reloc = BFD_RELOC_MIPS16_JMP; | |
97d87491 RS |
8230 | break; |
8231 | } | |
8232 | ||
7fd53920 | 8233 | operand = decode_mips16_operand (c, mips_opcode_32bit_p (opcode)); |
97d87491 RS |
8234 | if (!operand) |
8235 | abort (); | |
8236 | ||
82d808ed MR |
8237 | if (operand->type == OP_PCREL) |
8238 | pcrel = TRUE; | |
8239 | else | |
97d87491 RS |
8240 | { |
8241 | ext_operand = decode_mips16_operand (c, TRUE); | |
8242 | if (operand != ext_operand) | |
8243 | { | |
8244 | if (arg.token->type == OT_CHAR && arg.token->u.ch == '(') | |
8245 | { | |
8246 | offset_expr.X_op = O_constant; | |
8247 | offset_expr.X_add_number = 0; | |
8248 | relax_char = c; | |
8249 | continue; | |
8250 | } | |
8251 | ||
8252 | /* We need the OT_INTEGER check because some MIPS16 | |
8253 | immediate variants are listed before the register ones. */ | |
8254 | if (arg.token->type != OT_INTEGER | |
8255 | || !match_expression (&arg, &offset_expr, offset_reloc)) | |
8256 | return FALSE; | |
8257 | ||
8258 | /* '8' is used for SLTI(U) and has traditionally not | |
8259 | been allowed to take relocation operators. */ | |
8260 | if (offset_reloc[0] != BFD_RELOC_UNUSED | |
8261 | && (ext_operand->size != 16 || c == '8')) | |
8262 | return FALSE; | |
8263 | ||
8264 | relax_char = c; | |
8265 | continue; | |
8266 | } | |
8267 | } | |
8268 | ||
8269 | if (mips_optional_operand_p (operand) | |
8270 | && args[1] == ',' | |
8271 | && (arg.token[0].type != OT_REG | |
8272 | || arg.token[1].type == OT_END)) | |
8273 | { | |
8274 | /* Assume that the register has been elided and is the | |
8275 | same as the first operand. */ | |
8276 | arg.token = tokens; | |
8277 | arg.argnum = 1; | |
8278 | } | |
8279 | ||
8280 | if (!match_operand (&arg, operand)) | |
8281 | return FALSE; | |
8282 | } | |
8283 | } | |
8284 | ||
60f20e8b RS |
8285 | /* Record that the current instruction is invalid for the current ISA. */ |
8286 | ||
8287 | static void | |
8288 | match_invalid_for_isa (void) | |
8289 | { | |
8290 | set_insn_error_ss | |
1661c76c | 8291 | (0, _("opcode not supported on this processor: %s (%s)"), |
60f20e8b RS |
8292 | mips_cpu_info_from_arch (mips_opts.arch)->name, |
8293 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
8294 | } | |
8295 | ||
8296 | /* Try to match TOKENS against a series of opcode entries, starting at FIRST. | |
8297 | Return true if a definite match or failure was found, storing any match | |
8298 | in INSN. OPCODE_EXTRA is a value that should be ORed into the opcode | |
8299 | (to handle things like VU0 suffixes). LAX_MATCH is true if we have already | |
8300 | tried and failed to match under normal conditions and now want to try a | |
8301 | more relaxed match. */ | |
8302 | ||
8303 | static bfd_boolean | |
8304 | match_insns (struct mips_cl_insn *insn, const struct mips_opcode *first, | |
8305 | const struct mips_opcode *past, struct mips_operand_token *tokens, | |
8306 | int opcode_extra, bfd_boolean lax_match) | |
8307 | { | |
8308 | const struct mips_opcode *opcode; | |
8309 | const struct mips_opcode *invalid_delay_slot; | |
8310 | bfd_boolean seen_valid_for_isa, seen_valid_for_size; | |
8311 | ||
8312 | /* Search for a match, ignoring alternatives that don't satisfy the | |
8313 | current ISA or forced_length. */ | |
8314 | invalid_delay_slot = 0; | |
8315 | seen_valid_for_isa = FALSE; | |
8316 | seen_valid_for_size = FALSE; | |
8317 | opcode = first; | |
8318 | do | |
8319 | { | |
8320 | gas_assert (strcmp (opcode->name, first->name) == 0); | |
8321 | if (is_opcode_valid (opcode)) | |
8322 | { | |
8323 | seen_valid_for_isa = TRUE; | |
8324 | if (is_size_valid (opcode)) | |
8325 | { | |
8326 | bfd_boolean delay_slot_ok; | |
8327 | ||
8328 | seen_valid_for_size = TRUE; | |
8329 | delay_slot_ok = is_delay_slot_valid (opcode); | |
8330 | if (match_insn (insn, opcode, tokens, opcode_extra, | |
8331 | lax_match, delay_slot_ok)) | |
8332 | { | |
8333 | if (!delay_slot_ok) | |
8334 | { | |
8335 | if (!invalid_delay_slot) | |
8336 | invalid_delay_slot = opcode; | |
8337 | } | |
8338 | else | |
8339 | return TRUE; | |
8340 | } | |
8341 | } | |
8342 | } | |
8343 | ++opcode; | |
8344 | } | |
8345 | while (opcode < past && strcmp (opcode->name, first->name) == 0); | |
8346 | ||
8347 | /* If the only matches we found had the wrong length for the delay slot, | |
8348 | pick the first such match. We'll issue an appropriate warning later. */ | |
8349 | if (invalid_delay_slot) | |
8350 | { | |
8351 | if (match_insn (insn, invalid_delay_slot, tokens, opcode_extra, | |
8352 | lax_match, TRUE)) | |
8353 | return TRUE; | |
8354 | abort (); | |
8355 | } | |
8356 | ||
8357 | /* Handle the case where we didn't try to match an instruction because | |
8358 | all the alternatives were incompatible with the current ISA. */ | |
8359 | if (!seen_valid_for_isa) | |
8360 | { | |
8361 | match_invalid_for_isa (); | |
8362 | return TRUE; | |
8363 | } | |
8364 | ||
8365 | /* Handle the case where we didn't try to match an instruction because | |
8366 | all the alternatives were of the wrong size. */ | |
8367 | if (!seen_valid_for_size) | |
8368 | { | |
8369 | if (mips_opts.insn32) | |
1661c76c | 8370 | set_insn_error (0, _("opcode not supported in the `insn32' mode")); |
60f20e8b RS |
8371 | else |
8372 | set_insn_error_i | |
1661c76c | 8373 | (0, _("unrecognized %d-bit version of microMIPS opcode"), |
60f20e8b RS |
8374 | 8 * forced_insn_length); |
8375 | return TRUE; | |
8376 | } | |
8377 | ||
8378 | return FALSE; | |
8379 | } | |
8380 | ||
8381 | /* Like match_insns, but for MIPS16. */ | |
8382 | ||
8383 | static bfd_boolean | |
8384 | match_mips16_insns (struct mips_cl_insn *insn, const struct mips_opcode *first, | |
8385 | struct mips_operand_token *tokens) | |
8386 | { | |
8387 | const struct mips_opcode *opcode; | |
8388 | bfd_boolean seen_valid_for_isa; | |
7fd53920 | 8389 | bfd_boolean seen_valid_for_size; |
60f20e8b RS |
8390 | |
8391 | /* Search for a match, ignoring alternatives that don't satisfy the | |
8392 | current ISA. There are no separate entries for extended forms so | |
8393 | we deal with forced_length later. */ | |
8394 | seen_valid_for_isa = FALSE; | |
7fd53920 | 8395 | seen_valid_for_size = FALSE; |
60f20e8b RS |
8396 | opcode = first; |
8397 | do | |
8398 | { | |
8399 | gas_assert (strcmp (opcode->name, first->name) == 0); | |
8400 | if (is_opcode_valid_16 (opcode)) | |
8401 | { | |
8402 | seen_valid_for_isa = TRUE; | |
7fd53920 MR |
8403 | if (is_size_valid_16 (opcode)) |
8404 | { | |
8405 | seen_valid_for_size = TRUE; | |
8406 | if (match_mips16_insn (insn, opcode, tokens)) | |
8407 | return TRUE; | |
8408 | } | |
60f20e8b RS |
8409 | } |
8410 | ++opcode; | |
8411 | } | |
8412 | while (opcode < &mips16_opcodes[bfd_mips16_num_opcodes] | |
8413 | && strcmp (opcode->name, first->name) == 0); | |
8414 | ||
8415 | /* Handle the case where we didn't try to match an instruction because | |
8416 | all the alternatives were incompatible with the current ISA. */ | |
8417 | if (!seen_valid_for_isa) | |
8418 | { | |
8419 | match_invalid_for_isa (); | |
8420 | return TRUE; | |
8421 | } | |
8422 | ||
7fd53920 MR |
8423 | /* Handle the case where we didn't try to match an instruction because |
8424 | all the alternatives were of the wrong size. */ | |
8425 | if (!seen_valid_for_size) | |
8426 | { | |
8427 | if (forced_insn_length == 2) | |
8428 | set_insn_error | |
8429 | (0, _("unrecognized unextended version of MIPS16 opcode")); | |
8430 | else | |
8431 | set_insn_error | |
8432 | (0, _("unrecognized extended version of MIPS16 opcode")); | |
8433 | return TRUE; | |
8434 | } | |
8435 | ||
60f20e8b RS |
8436 | return FALSE; |
8437 | } | |
8438 | ||
584892a6 RS |
8439 | /* Set up global variables for the start of a new macro. */ |
8440 | ||
8441 | static void | |
8442 | macro_start (void) | |
8443 | { | |
8444 | memset (&mips_macro_warning.sizes, 0, sizeof (mips_macro_warning.sizes)); | |
df58fc94 RS |
8445 | memset (&mips_macro_warning.first_insn_sizes, 0, |
8446 | sizeof (mips_macro_warning.first_insn_sizes)); | |
8447 | memset (&mips_macro_warning.insns, 0, sizeof (mips_macro_warning.insns)); | |
584892a6 | 8448 | mips_macro_warning.delay_slot_p = (mips_opts.noreorder |
11625dd8 | 8449 | && delayed_branch_p (&history[0])); |
7bd374a4 MR |
8450 | if (history[0].frag |
8451 | && history[0].frag->fr_type == rs_machine_dependent | |
8452 | && RELAX_MICROMIPS_P (history[0].frag->fr_subtype) | |
8453 | && RELAX_MICROMIPS_NODS (history[0].frag->fr_subtype)) | |
8454 | mips_macro_warning.delay_slot_length = 0; | |
8455 | else | |
8456 | switch (history[0].insn_mo->pinfo2 | |
8457 | & (INSN2_BRANCH_DELAY_32BIT | INSN2_BRANCH_DELAY_16BIT)) | |
8458 | { | |
8459 | case INSN2_BRANCH_DELAY_32BIT: | |
8460 | mips_macro_warning.delay_slot_length = 4; | |
8461 | break; | |
8462 | case INSN2_BRANCH_DELAY_16BIT: | |
8463 | mips_macro_warning.delay_slot_length = 2; | |
8464 | break; | |
8465 | default: | |
8466 | mips_macro_warning.delay_slot_length = 0; | |
8467 | break; | |
8468 | } | |
df58fc94 | 8469 | mips_macro_warning.first_frag = NULL; |
584892a6 RS |
8470 | } |
8471 | ||
df58fc94 RS |
8472 | /* Given that a macro is longer than one instruction or of the wrong size, |
8473 | return the appropriate warning for it. Return null if no warning is | |
8474 | needed. SUBTYPE is a bitmask of RELAX_DELAY_SLOT, RELAX_DELAY_SLOT_16BIT, | |
8475 | RELAX_DELAY_SLOT_SIZE_FIRST, RELAX_DELAY_SLOT_SIZE_SECOND, | |
8476 | and RELAX_NOMACRO. */ | |
584892a6 RS |
8477 | |
8478 | static const char * | |
8479 | macro_warning (relax_substateT subtype) | |
8480 | { | |
8481 | if (subtype & RELAX_DELAY_SLOT) | |
1661c76c | 8482 | return _("macro instruction expanded into multiple instructions" |
584892a6 RS |
8483 | " in a branch delay slot"); |
8484 | else if (subtype & RELAX_NOMACRO) | |
1661c76c | 8485 | return _("macro instruction expanded into multiple instructions"); |
df58fc94 RS |
8486 | else if (subtype & (RELAX_DELAY_SLOT_SIZE_FIRST |
8487 | | RELAX_DELAY_SLOT_SIZE_SECOND)) | |
8488 | return ((subtype & RELAX_DELAY_SLOT_16BIT) | |
1661c76c | 8489 | ? _("macro instruction expanded into a wrong size instruction" |
df58fc94 | 8490 | " in a 16-bit branch delay slot") |
1661c76c | 8491 | : _("macro instruction expanded into a wrong size instruction" |
df58fc94 | 8492 | " in a 32-bit branch delay slot")); |
584892a6 RS |
8493 | else |
8494 | return 0; | |
8495 | } | |
8496 | ||
8497 | /* Finish up a macro. Emit warnings as appropriate. */ | |
8498 | ||
8499 | static void | |
8500 | macro_end (void) | |
8501 | { | |
df58fc94 RS |
8502 | /* Relaxation warning flags. */ |
8503 | relax_substateT subtype = 0; | |
8504 | ||
8505 | /* Check delay slot size requirements. */ | |
8506 | if (mips_macro_warning.delay_slot_length == 2) | |
8507 | subtype |= RELAX_DELAY_SLOT_16BIT; | |
8508 | if (mips_macro_warning.delay_slot_length != 0) | |
584892a6 | 8509 | { |
df58fc94 RS |
8510 | if (mips_macro_warning.delay_slot_length |
8511 | != mips_macro_warning.first_insn_sizes[0]) | |
8512 | subtype |= RELAX_DELAY_SLOT_SIZE_FIRST; | |
8513 | if (mips_macro_warning.delay_slot_length | |
8514 | != mips_macro_warning.first_insn_sizes[1]) | |
8515 | subtype |= RELAX_DELAY_SLOT_SIZE_SECOND; | |
8516 | } | |
584892a6 | 8517 | |
df58fc94 RS |
8518 | /* Check instruction count requirements. */ |
8519 | if (mips_macro_warning.insns[0] > 1 || mips_macro_warning.insns[1] > 1) | |
8520 | { | |
8521 | if (mips_macro_warning.insns[1] > mips_macro_warning.insns[0]) | |
584892a6 RS |
8522 | subtype |= RELAX_SECOND_LONGER; |
8523 | if (mips_opts.warn_about_macros) | |
8524 | subtype |= RELAX_NOMACRO; | |
8525 | if (mips_macro_warning.delay_slot_p) | |
8526 | subtype |= RELAX_DELAY_SLOT; | |
df58fc94 | 8527 | } |
584892a6 | 8528 | |
df58fc94 RS |
8529 | /* If both alternatives fail to fill a delay slot correctly, |
8530 | emit the warning now. */ | |
8531 | if ((subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0 | |
8532 | && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0) | |
8533 | { | |
8534 | relax_substateT s; | |
8535 | const char *msg; | |
8536 | ||
8537 | s = subtype & (RELAX_DELAY_SLOT_16BIT | |
8538 | | RELAX_DELAY_SLOT_SIZE_FIRST | |
8539 | | RELAX_DELAY_SLOT_SIZE_SECOND); | |
8540 | msg = macro_warning (s); | |
8541 | if (msg != NULL) | |
8542 | as_warn ("%s", msg); | |
8543 | subtype &= ~s; | |
8544 | } | |
8545 | ||
8546 | /* If both implementations are longer than 1 instruction, then emit the | |
8547 | warning now. */ | |
8548 | if (mips_macro_warning.insns[0] > 1 && mips_macro_warning.insns[1] > 1) | |
8549 | { | |
8550 | relax_substateT s; | |
8551 | const char *msg; | |
8552 | ||
8553 | s = subtype & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT); | |
8554 | msg = macro_warning (s); | |
8555 | if (msg != NULL) | |
8556 | as_warn ("%s", msg); | |
8557 | subtype &= ~s; | |
584892a6 | 8558 | } |
df58fc94 RS |
8559 | |
8560 | /* If any flags still set, then one implementation might need a warning | |
8561 | and the other either will need one of a different kind or none at all. | |
8562 | Pass any remaining flags over to relaxation. */ | |
8563 | if (mips_macro_warning.first_frag != NULL) | |
8564 | mips_macro_warning.first_frag->fr_subtype |= subtype; | |
584892a6 RS |
8565 | } |
8566 | ||
df58fc94 RS |
8567 | /* Instruction operand formats used in macros that vary between |
8568 | standard MIPS and microMIPS code. */ | |
8569 | ||
833794fc | 8570 | static const char * const brk_fmt[2][2] = { { "c", "c" }, { "mF", "c" } }; |
df58fc94 RS |
8571 | static const char * const cop12_fmt[2] = { "E,o(b)", "E,~(b)" }; |
8572 | static const char * const jalr_fmt[2] = { "d,s", "t,s" }; | |
8573 | static const char * const lui_fmt[2] = { "t,u", "s,u" }; | |
8574 | static const char * const mem12_fmt[2] = { "t,o(b)", "t,~(b)" }; | |
833794fc | 8575 | static const char * const mfhl_fmt[2][2] = { { "d", "d" }, { "mj", "s" } }; |
df58fc94 RS |
8576 | static const char * const shft_fmt[2] = { "d,w,<", "t,r,<" }; |
8577 | static const char * const trap_fmt[2] = { "s,t,q", "s,t,|" }; | |
8578 | ||
833794fc | 8579 | #define BRK_FMT (brk_fmt[mips_opts.micromips][mips_opts.insn32]) |
7361da2c AB |
8580 | #define COP12_FMT (ISA_IS_R6 (mips_opts.isa) ? "E,+:(d)" \ |
8581 | : cop12_fmt[mips_opts.micromips]) | |
df58fc94 RS |
8582 | #define JALR_FMT (jalr_fmt[mips_opts.micromips]) |
8583 | #define LUI_FMT (lui_fmt[mips_opts.micromips]) | |
8584 | #define MEM12_FMT (mem12_fmt[mips_opts.micromips]) | |
7361da2c AB |
8585 | #define LL_SC_FMT (ISA_IS_R6 (mips_opts.isa) ? "t,+j(b)" \ |
8586 | : mem12_fmt[mips_opts.micromips]) | |
833794fc | 8587 | #define MFHL_FMT (mfhl_fmt[mips_opts.micromips][mips_opts.insn32]) |
df58fc94 RS |
8588 | #define SHFT_FMT (shft_fmt[mips_opts.micromips]) |
8589 | #define TRAP_FMT (trap_fmt[mips_opts.micromips]) | |
8590 | ||
6e1304d8 RS |
8591 | /* Read a macro's relocation codes from *ARGS and store them in *R. |
8592 | The first argument in *ARGS will be either the code for a single | |
8593 | relocation or -1 followed by the three codes that make up a | |
8594 | composite relocation. */ | |
8595 | ||
8596 | static void | |
8597 | macro_read_relocs (va_list *args, bfd_reloc_code_real_type *r) | |
8598 | { | |
8599 | int i, next; | |
8600 | ||
8601 | next = va_arg (*args, int); | |
8602 | if (next >= 0) | |
8603 | r[0] = (bfd_reloc_code_real_type) next; | |
8604 | else | |
f2ae14a1 RS |
8605 | { |
8606 | for (i = 0; i < 3; i++) | |
8607 | r[i] = (bfd_reloc_code_real_type) va_arg (*args, int); | |
8608 | /* This function is only used for 16-bit relocation fields. | |
8609 | To make the macro code simpler, treat an unrelocated value | |
8610 | in the same way as BFD_RELOC_LO16. */ | |
8611 | if (r[0] == BFD_RELOC_UNUSED) | |
8612 | r[0] = BFD_RELOC_LO16; | |
8613 | } | |
6e1304d8 RS |
8614 | } |
8615 | ||
252b5132 RH |
8616 | /* Build an instruction created by a macro expansion. This is passed |
8617 | a pointer to the count of instructions created so far, an | |
8618 | expression, the name of the instruction to build, an operand format | |
8619 | string, and corresponding arguments. */ | |
8620 | ||
252b5132 | 8621 | static void |
67c0d1eb | 8622 | macro_build (expressionS *ep, const char *name, const char *fmt, ...) |
252b5132 | 8623 | { |
df58fc94 | 8624 | const struct mips_opcode *mo = NULL; |
f6688943 | 8625 | bfd_reloc_code_real_type r[3]; |
df58fc94 | 8626 | const struct mips_opcode *amo; |
e077a1c8 | 8627 | const struct mips_operand *operand; |
df58fc94 RS |
8628 | struct hash_control *hash; |
8629 | struct mips_cl_insn insn; | |
252b5132 | 8630 | va_list args; |
e077a1c8 | 8631 | unsigned int uval; |
252b5132 | 8632 | |
252b5132 | 8633 | va_start (args, fmt); |
252b5132 | 8634 | |
252b5132 RH |
8635 | if (mips_opts.mips16) |
8636 | { | |
03ea81db | 8637 | mips16_macro_build (ep, name, fmt, &args); |
252b5132 RH |
8638 | va_end (args); |
8639 | return; | |
8640 | } | |
8641 | ||
f6688943 TS |
8642 | r[0] = BFD_RELOC_UNUSED; |
8643 | r[1] = BFD_RELOC_UNUSED; | |
8644 | r[2] = BFD_RELOC_UNUSED; | |
df58fc94 RS |
8645 | hash = mips_opts.micromips ? micromips_op_hash : op_hash; |
8646 | amo = (struct mips_opcode *) hash_find (hash, name); | |
8647 | gas_assert (amo); | |
8648 | gas_assert (strcmp (name, amo->name) == 0); | |
1e915849 | 8649 | |
df58fc94 | 8650 | do |
8b082fb1 TS |
8651 | { |
8652 | /* Search until we get a match for NAME. It is assumed here that | |
df58fc94 | 8653 | macros will never generate MDMX, MIPS-3D, or MT instructions. |
33eaf5de | 8654 | We try to match an instruction that fulfills the branch delay |
df58fc94 RS |
8655 | slot instruction length requirement (if any) of the previous |
8656 | instruction. While doing this we record the first instruction | |
8657 | seen that matches all the other conditions and use it anyway | |
8658 | if the requirement cannot be met; we will issue an appropriate | |
8659 | warning later on. */ | |
8660 | if (strcmp (fmt, amo->args) == 0 | |
8661 | && amo->pinfo != INSN_MACRO | |
8662 | && is_opcode_valid (amo) | |
8663 | && is_size_valid (amo)) | |
8664 | { | |
8665 | if (is_delay_slot_valid (amo)) | |
8666 | { | |
8667 | mo = amo; | |
8668 | break; | |
8669 | } | |
8670 | else if (!mo) | |
8671 | mo = amo; | |
8672 | } | |
8b082fb1 | 8673 | |
df58fc94 RS |
8674 | ++amo; |
8675 | gas_assert (amo->name); | |
252b5132 | 8676 | } |
df58fc94 | 8677 | while (strcmp (name, amo->name) == 0); |
252b5132 | 8678 | |
df58fc94 | 8679 | gas_assert (mo); |
1e915849 | 8680 | create_insn (&insn, mo); |
e077a1c8 | 8681 | for (; *fmt; ++fmt) |
252b5132 | 8682 | { |
e077a1c8 | 8683 | switch (*fmt) |
252b5132 | 8684 | { |
252b5132 RH |
8685 | case ',': |
8686 | case '(': | |
8687 | case ')': | |
252b5132 | 8688 | case 'z': |
e077a1c8 | 8689 | break; |
252b5132 RH |
8690 | |
8691 | case 'i': | |
8692 | case 'j': | |
6e1304d8 | 8693 | macro_read_relocs (&args, r); |
9c2799c2 | 8694 | gas_assert (*r == BFD_RELOC_GPREL16 |
e391c024 RS |
8695 | || *r == BFD_RELOC_MIPS_HIGHER |
8696 | || *r == BFD_RELOC_HI16_S | |
8697 | || *r == BFD_RELOC_LO16 | |
8698 | || *r == BFD_RELOC_MIPS_GOT_OFST); | |
e077a1c8 | 8699 | break; |
e391c024 RS |
8700 | |
8701 | case 'o': | |
8702 | macro_read_relocs (&args, r); | |
e077a1c8 | 8703 | break; |
252b5132 RH |
8704 | |
8705 | case 'u': | |
6e1304d8 | 8706 | macro_read_relocs (&args, r); |
9c2799c2 | 8707 | gas_assert (ep != NULL |
90ecf173 MR |
8708 | && (ep->X_op == O_constant |
8709 | || (ep->X_op == O_symbol | |
8710 | && (*r == BFD_RELOC_MIPS_HIGHEST | |
8711 | || *r == BFD_RELOC_HI16_S | |
8712 | || *r == BFD_RELOC_HI16 | |
8713 | || *r == BFD_RELOC_GPREL16 | |
8714 | || *r == BFD_RELOC_MIPS_GOT_HI16 | |
8715 | || *r == BFD_RELOC_MIPS_CALL_HI16)))); | |
e077a1c8 | 8716 | break; |
252b5132 RH |
8717 | |
8718 | case 'p': | |
9c2799c2 | 8719 | gas_assert (ep != NULL); |
bad36eac | 8720 | |
252b5132 RH |
8721 | /* |
8722 | * This allows macro() to pass an immediate expression for | |
8723 | * creating short branches without creating a symbol. | |
bad36eac DJ |
8724 | * |
8725 | * We don't allow branch relaxation for these branches, as | |
8726 | * they should only appear in ".set nomacro" anyway. | |
252b5132 RH |
8727 | */ |
8728 | if (ep->X_op == O_constant) | |
8729 | { | |
df58fc94 RS |
8730 | /* For microMIPS we always use relocations for branches. |
8731 | So we should not resolve immediate values. */ | |
8732 | gas_assert (!mips_opts.micromips); | |
8733 | ||
bad36eac DJ |
8734 | if ((ep->X_add_number & 3) != 0) |
8735 | as_bad (_("branch to misaligned address (0x%lx)"), | |
8736 | (unsigned long) ep->X_add_number); | |
8737 | if ((ep->X_add_number + 0x20000) & ~0x3ffff) | |
8738 | as_bad (_("branch address range overflow (0x%lx)"), | |
8739 | (unsigned long) ep->X_add_number); | |
252b5132 RH |
8740 | insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff; |
8741 | ep = NULL; | |
8742 | } | |
8743 | else | |
0b25d3e6 | 8744 | *r = BFD_RELOC_16_PCREL_S2; |
e077a1c8 | 8745 | break; |
252b5132 RH |
8746 | |
8747 | case 'a': | |
9c2799c2 | 8748 | gas_assert (ep != NULL); |
f6688943 | 8749 | *r = BFD_RELOC_MIPS_JMP; |
e077a1c8 | 8750 | break; |
d43b4baf | 8751 | |
252b5132 | 8752 | default: |
e077a1c8 RS |
8753 | operand = (mips_opts.micromips |
8754 | ? decode_micromips_operand (fmt) | |
8755 | : decode_mips_operand (fmt)); | |
8756 | if (!operand) | |
8757 | abort (); | |
8758 | ||
8759 | uval = va_arg (args, int); | |
8760 | if (operand->type == OP_CLO_CLZ_DEST) | |
8761 | uval |= (uval << 5); | |
8762 | insn_insert_operand (&insn, operand, uval); | |
8763 | ||
7361da2c | 8764 | if (*fmt == '+' || *fmt == 'm' || *fmt == '-') |
e077a1c8 RS |
8765 | ++fmt; |
8766 | break; | |
252b5132 | 8767 | } |
252b5132 RH |
8768 | } |
8769 | va_end (args); | |
9c2799c2 | 8770 | gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
252b5132 | 8771 | |
df58fc94 | 8772 | append_insn (&insn, ep, r, TRUE); |
252b5132 RH |
8773 | } |
8774 | ||
8775 | static void | |
67c0d1eb | 8776 | mips16_macro_build (expressionS *ep, const char *name, const char *fmt, |
03ea81db | 8777 | va_list *args) |
252b5132 | 8778 | { |
1e915849 | 8779 | struct mips_opcode *mo; |
252b5132 | 8780 | struct mips_cl_insn insn; |
e077a1c8 | 8781 | const struct mips_operand *operand; |
f6688943 TS |
8782 | bfd_reloc_code_real_type r[3] |
8783 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 8784 | |
1e915849 | 8785 | mo = (struct mips_opcode *) hash_find (mips16_op_hash, name); |
9c2799c2 NC |
8786 | gas_assert (mo); |
8787 | gas_assert (strcmp (name, mo->name) == 0); | |
252b5132 | 8788 | |
1e915849 | 8789 | while (strcmp (fmt, mo->args) != 0 || mo->pinfo == INSN_MACRO) |
252b5132 | 8790 | { |
1e915849 | 8791 | ++mo; |
9c2799c2 NC |
8792 | gas_assert (mo->name); |
8793 | gas_assert (strcmp (name, mo->name) == 0); | |
252b5132 RH |
8794 | } |
8795 | ||
1e915849 | 8796 | create_insn (&insn, mo); |
e077a1c8 | 8797 | for (; *fmt; ++fmt) |
252b5132 RH |
8798 | { |
8799 | int c; | |
8800 | ||
e077a1c8 | 8801 | c = *fmt; |
252b5132 RH |
8802 | switch (c) |
8803 | { | |
252b5132 RH |
8804 | case ',': |
8805 | case '(': | |
8806 | case ')': | |
e077a1c8 | 8807 | break; |
252b5132 | 8808 | |
d8722d76 | 8809 | case '.': |
252b5132 RH |
8810 | case 'S': |
8811 | case 'P': | |
8812 | case 'R': | |
e077a1c8 | 8813 | break; |
252b5132 RH |
8814 | |
8815 | case '<': | |
252b5132 | 8816 | case '5': |
d8722d76 | 8817 | case 'F': |
252b5132 RH |
8818 | case 'H': |
8819 | case 'W': | |
8820 | case 'D': | |
8821 | case 'j': | |
8822 | case '8': | |
8823 | case 'V': | |
8824 | case 'C': | |
8825 | case 'U': | |
8826 | case 'k': | |
8827 | case 'K': | |
8828 | case 'p': | |
8829 | case 'q': | |
8830 | { | |
b886a2ab RS |
8831 | offsetT value; |
8832 | ||
9c2799c2 | 8833 | gas_assert (ep != NULL); |
252b5132 RH |
8834 | |
8835 | if (ep->X_op != O_constant) | |
874e8986 | 8836 | *r = (int) BFD_RELOC_UNUSED + c; |
b886a2ab | 8837 | else if (calculate_reloc (*r, ep->X_add_number, &value)) |
252b5132 | 8838 | { |
b886a2ab | 8839 | mips16_immed (NULL, 0, c, *r, value, 0, &insn.insn_opcode); |
252b5132 | 8840 | ep = NULL; |
f6688943 | 8841 | *r = BFD_RELOC_UNUSED; |
252b5132 RH |
8842 | } |
8843 | } | |
e077a1c8 | 8844 | break; |
252b5132 | 8845 | |
e077a1c8 RS |
8846 | default: |
8847 | operand = decode_mips16_operand (c, FALSE); | |
8848 | if (!operand) | |
8849 | abort (); | |
252b5132 | 8850 | |
4a06e5a2 | 8851 | insn_insert_operand (&insn, operand, va_arg (*args, int)); |
e077a1c8 RS |
8852 | break; |
8853 | } | |
252b5132 RH |
8854 | } |
8855 | ||
9c2799c2 | 8856 | gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
252b5132 | 8857 | |
df58fc94 | 8858 | append_insn (&insn, ep, r, TRUE); |
252b5132 RH |
8859 | } |
8860 | ||
438c16b8 TS |
8861 | /* |
8862 | * Generate a "jalr" instruction with a relocation hint to the called | |
8863 | * function. This occurs in NewABI PIC code. | |
8864 | */ | |
8865 | static void | |
df58fc94 | 8866 | macro_build_jalr (expressionS *ep, int cprestore) |
438c16b8 | 8867 | { |
df58fc94 RS |
8868 | static const bfd_reloc_code_real_type jalr_relocs[2] |
8869 | = { BFD_RELOC_MIPS_JALR, BFD_RELOC_MICROMIPS_JALR }; | |
8870 | bfd_reloc_code_real_type jalr_reloc = jalr_relocs[mips_opts.micromips]; | |
8871 | const char *jalr; | |
685736be | 8872 | char *f = NULL; |
b34976b6 | 8873 | |
1180b5a4 | 8874 | if (MIPS_JALR_HINT_P (ep)) |
f21f8242 | 8875 | { |
cc3d92a5 | 8876 | frag_grow (8); |
f21f8242 AO |
8877 | f = frag_more (0); |
8878 | } | |
2906b037 | 8879 | if (mips_opts.micromips) |
df58fc94 | 8880 | { |
833794fc MR |
8881 | jalr = ((mips_opts.noreorder && !cprestore) || mips_opts.insn32 |
8882 | ? "jalr" : "jalrs"); | |
e64af278 | 8883 | if (MIPS_JALR_HINT_P (ep) |
833794fc | 8884 | || mips_opts.insn32 |
e64af278 | 8885 | || (history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) |
df58fc94 RS |
8886 | macro_build (NULL, jalr, "t,s", RA, PIC_CALL_REG); |
8887 | else | |
8888 | macro_build (NULL, jalr, "mj", PIC_CALL_REG); | |
8889 | } | |
2906b037 MR |
8890 | else |
8891 | macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG); | |
1180b5a4 | 8892 | if (MIPS_JALR_HINT_P (ep)) |
df58fc94 | 8893 | fix_new_exp (frag_now, f - frag_now->fr_literal, 4, ep, FALSE, jalr_reloc); |
438c16b8 TS |
8894 | } |
8895 | ||
252b5132 RH |
8896 | /* |
8897 | * Generate a "lui" instruction. | |
8898 | */ | |
8899 | static void | |
67c0d1eb | 8900 | macro_build_lui (expressionS *ep, int regnum) |
252b5132 | 8901 | { |
9c2799c2 | 8902 | gas_assert (! mips_opts.mips16); |
252b5132 | 8903 | |
df58fc94 | 8904 | if (ep->X_op != O_constant) |
252b5132 | 8905 | { |
9c2799c2 | 8906 | gas_assert (ep->X_op == O_symbol); |
bbe506e8 TS |
8907 | /* _gp_disp is a special case, used from s_cpload. |
8908 | __gnu_local_gp is used if mips_no_shared. */ | |
9c2799c2 | 8909 | gas_assert (mips_pic == NO_PIC |
78e1bb40 | 8910 | || (! HAVE_NEWABI |
aa6975fb ILT |
8911 | && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0) |
8912 | || (! mips_in_shared | |
bbe506e8 TS |
8913 | && strcmp (S_GET_NAME (ep->X_add_symbol), |
8914 | "__gnu_local_gp") == 0)); | |
252b5132 RH |
8915 | } |
8916 | ||
df58fc94 | 8917 | macro_build (ep, "lui", LUI_FMT, regnum, BFD_RELOC_HI16_S); |
252b5132 RH |
8918 | } |
8919 | ||
885add95 CD |
8920 | /* Generate a sequence of instructions to do a load or store from a constant |
8921 | offset off of a base register (breg) into/from a target register (treg), | |
8922 | using AT if necessary. */ | |
8923 | static void | |
67c0d1eb RS |
8924 | macro_build_ldst_constoffset (expressionS *ep, const char *op, |
8925 | int treg, int breg, int dbl) | |
885add95 | 8926 | { |
9c2799c2 | 8927 | gas_assert (ep->X_op == O_constant); |
885add95 | 8928 | |
256ab948 | 8929 | /* Sign-extending 32-bit constants makes their handling easier. */ |
2051e8c4 MR |
8930 | if (!dbl) |
8931 | normalize_constant_expr (ep); | |
256ab948 | 8932 | |
67c1ffbe | 8933 | /* Right now, this routine can only handle signed 32-bit constants. */ |
ecd13cd3 | 8934 | if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000)) |
885add95 CD |
8935 | as_warn (_("operand overflow")); |
8936 | ||
8937 | if (IS_SEXT_16BIT_NUM(ep->X_add_number)) | |
8938 | { | |
8939 | /* Signed 16-bit offset will fit in the op. Easy! */ | |
67c0d1eb | 8940 | macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
885add95 CD |
8941 | } |
8942 | else | |
8943 | { | |
8944 | /* 32-bit offset, need multiple instructions and AT, like: | |
8945 | lui $tempreg,const_hi (BFD_RELOC_HI16_S) | |
8946 | addu $tempreg,$tempreg,$breg | |
8947 | <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16) | |
8948 | to handle the complete offset. */ | |
67c0d1eb RS |
8949 | macro_build_lui (ep, AT); |
8950 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); | |
8951 | macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, AT); | |
885add95 | 8952 | |
741fe287 | 8953 | if (!mips_opts.at) |
1661c76c | 8954 | as_bad (_("macro used $at after \".set noat\"")); |
885add95 CD |
8955 | } |
8956 | } | |
8957 | ||
252b5132 RH |
8958 | /* set_at() |
8959 | * Generates code to set the $at register to true (one) | |
8960 | * if reg is less than the immediate expression. | |
8961 | */ | |
8962 | static void | |
67c0d1eb | 8963 | set_at (int reg, int unsignedp) |
252b5132 | 8964 | { |
b0e6f033 | 8965 | if (imm_expr.X_add_number >= -0x8000 |
252b5132 | 8966 | && imm_expr.X_add_number < 0x8000) |
67c0d1eb RS |
8967 | macro_build (&imm_expr, unsignedp ? "sltiu" : "slti", "t,r,j", |
8968 | AT, reg, BFD_RELOC_LO16); | |
252b5132 RH |
8969 | else |
8970 | { | |
bad1aba3 | 8971 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
67c0d1eb | 8972 | macro_build (NULL, unsignedp ? "sltu" : "slt", "d,v,t", AT, reg, AT); |
252b5132 RH |
8973 | } |
8974 | } | |
8975 | ||
252b5132 RH |
8976 | /* Count the leading zeroes by performing a binary chop. This is a |
8977 | bulky bit of source, but performance is a LOT better for the | |
8978 | majority of values than a simple loop to count the bits: | |
8979 | for (lcnt = 0; (lcnt < 32); lcnt++) | |
8980 | if ((v) & (1 << (31 - lcnt))) | |
8981 | break; | |
8982 | However it is not code size friendly, and the gain will drop a bit | |
8983 | on certain cached systems. | |
8984 | */ | |
8985 | #define COUNT_TOP_ZEROES(v) \ | |
8986 | (((v) & ~0xffff) == 0 \ | |
8987 | ? ((v) & ~0xff) == 0 \ | |
8988 | ? ((v) & ~0xf) == 0 \ | |
8989 | ? ((v) & ~0x3) == 0 \ | |
8990 | ? ((v) & ~0x1) == 0 \ | |
8991 | ? !(v) \ | |
8992 | ? 32 \ | |
8993 | : 31 \ | |
8994 | : 30 \ | |
8995 | : ((v) & ~0x7) == 0 \ | |
8996 | ? 29 \ | |
8997 | : 28 \ | |
8998 | : ((v) & ~0x3f) == 0 \ | |
8999 | ? ((v) & ~0x1f) == 0 \ | |
9000 | ? 27 \ | |
9001 | : 26 \ | |
9002 | : ((v) & ~0x7f) == 0 \ | |
9003 | ? 25 \ | |
9004 | : 24 \ | |
9005 | : ((v) & ~0xfff) == 0 \ | |
9006 | ? ((v) & ~0x3ff) == 0 \ | |
9007 | ? ((v) & ~0x1ff) == 0 \ | |
9008 | ? 23 \ | |
9009 | : 22 \ | |
9010 | : ((v) & ~0x7ff) == 0 \ | |
9011 | ? 21 \ | |
9012 | : 20 \ | |
9013 | : ((v) & ~0x3fff) == 0 \ | |
9014 | ? ((v) & ~0x1fff) == 0 \ | |
9015 | ? 19 \ | |
9016 | : 18 \ | |
9017 | : ((v) & ~0x7fff) == 0 \ | |
9018 | ? 17 \ | |
9019 | : 16 \ | |
9020 | : ((v) & ~0xffffff) == 0 \ | |
9021 | ? ((v) & ~0xfffff) == 0 \ | |
9022 | ? ((v) & ~0x3ffff) == 0 \ | |
9023 | ? ((v) & ~0x1ffff) == 0 \ | |
9024 | ? 15 \ | |
9025 | : 14 \ | |
9026 | : ((v) & ~0x7ffff) == 0 \ | |
9027 | ? 13 \ | |
9028 | : 12 \ | |
9029 | : ((v) & ~0x3fffff) == 0 \ | |
9030 | ? ((v) & ~0x1fffff) == 0 \ | |
9031 | ? 11 \ | |
9032 | : 10 \ | |
9033 | : ((v) & ~0x7fffff) == 0 \ | |
9034 | ? 9 \ | |
9035 | : 8 \ | |
9036 | : ((v) & ~0xfffffff) == 0 \ | |
9037 | ? ((v) & ~0x3ffffff) == 0 \ | |
9038 | ? ((v) & ~0x1ffffff) == 0 \ | |
9039 | ? 7 \ | |
9040 | : 6 \ | |
9041 | : ((v) & ~0x7ffffff) == 0 \ | |
9042 | ? 5 \ | |
9043 | : 4 \ | |
9044 | : ((v) & ~0x3fffffff) == 0 \ | |
9045 | ? ((v) & ~0x1fffffff) == 0 \ | |
9046 | ? 3 \ | |
9047 | : 2 \ | |
9048 | : ((v) & ~0x7fffffff) == 0 \ | |
9049 | ? 1 \ | |
9050 | : 0) | |
9051 | ||
9052 | /* load_register() | |
67c1ffbe | 9053 | * This routine generates the least number of instructions necessary to load |
252b5132 RH |
9054 | * an absolute expression value into a register. |
9055 | */ | |
9056 | static void | |
67c0d1eb | 9057 | load_register (int reg, expressionS *ep, int dbl) |
252b5132 RH |
9058 | { |
9059 | int freg; | |
9060 | expressionS hi32, lo32; | |
9061 | ||
9062 | if (ep->X_op != O_big) | |
9063 | { | |
9c2799c2 | 9064 | gas_assert (ep->X_op == O_constant); |
256ab948 TS |
9065 | |
9066 | /* Sign-extending 32-bit constants makes their handling easier. */ | |
2051e8c4 MR |
9067 | if (!dbl) |
9068 | normalize_constant_expr (ep); | |
256ab948 TS |
9069 | |
9070 | if (IS_SEXT_16BIT_NUM (ep->X_add_number)) | |
252b5132 RH |
9071 | { |
9072 | /* We can handle 16 bit signed values with an addiu to | |
9073 | $zero. No need to ever use daddiu here, since $zero and | |
9074 | the result are always correct in 32 bit mode. */ | |
67c0d1eb | 9075 | macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
9076 | return; |
9077 | } | |
9078 | else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000) | |
9079 | { | |
9080 | /* We can handle 16 bit unsigned values with an ori to | |
9081 | $zero. */ | |
67c0d1eb | 9082 | macro_build (ep, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
9083 | return; |
9084 | } | |
256ab948 | 9085 | else if ((IS_SEXT_32BIT_NUM (ep->X_add_number))) |
252b5132 RH |
9086 | { |
9087 | /* 32 bit values require an lui. */ | |
df58fc94 | 9088 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_HI16); |
252b5132 | 9089 | if ((ep->X_add_number & 0xffff) != 0) |
67c0d1eb | 9090 | macro_build (ep, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16); |
252b5132 RH |
9091 | return; |
9092 | } | |
9093 | } | |
9094 | ||
9095 | /* The value is larger than 32 bits. */ | |
9096 | ||
bad1aba3 | 9097 | if (!dbl || GPR_SIZE == 32) |
252b5132 | 9098 | { |
55e08f71 NC |
9099 | char value[32]; |
9100 | ||
9101 | sprintf_vma (value, ep->X_add_number); | |
1661c76c | 9102 | as_bad (_("number (0x%s) larger than 32 bits"), value); |
67c0d1eb | 9103 | macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
9104 | return; |
9105 | } | |
9106 | ||
9107 | if (ep->X_op != O_big) | |
9108 | { | |
9109 | hi32 = *ep; | |
9110 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
9111 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
9112 | hi32.X_add_number &= 0xffffffff; | |
9113 | lo32 = *ep; | |
9114 | lo32.X_add_number &= 0xffffffff; | |
9115 | } | |
9116 | else | |
9117 | { | |
9c2799c2 | 9118 | gas_assert (ep->X_add_number > 2); |
252b5132 RH |
9119 | if (ep->X_add_number == 3) |
9120 | generic_bignum[3] = 0; | |
9121 | else if (ep->X_add_number > 4) | |
1661c76c | 9122 | as_bad (_("number larger than 64 bits")); |
252b5132 RH |
9123 | lo32.X_op = O_constant; |
9124 | lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16); | |
9125 | hi32.X_op = O_constant; | |
9126 | hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16); | |
9127 | } | |
9128 | ||
9129 | if (hi32.X_add_number == 0) | |
9130 | freg = 0; | |
9131 | else | |
9132 | { | |
9133 | int shift, bit; | |
9134 | unsigned long hi, lo; | |
9135 | ||
956cd1d6 | 9136 | if (hi32.X_add_number == (offsetT) 0xffffffff) |
beae10d5 KH |
9137 | { |
9138 | if ((lo32.X_add_number & 0xffff8000) == 0xffff8000) | |
9139 | { | |
67c0d1eb | 9140 | macro_build (&lo32, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
beae10d5 KH |
9141 | return; |
9142 | } | |
9143 | if (lo32.X_add_number & 0x80000000) | |
9144 | { | |
df58fc94 | 9145 | macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16); |
252b5132 | 9146 | if (lo32.X_add_number & 0xffff) |
67c0d1eb | 9147 | macro_build (&lo32, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16); |
beae10d5 KH |
9148 | return; |
9149 | } | |
9150 | } | |
252b5132 RH |
9151 | |
9152 | /* Check for 16bit shifted constant. We know that hi32 is | |
9153 | non-zero, so start the mask on the first bit of the hi32 | |
9154 | value. */ | |
9155 | shift = 17; | |
9156 | do | |
beae10d5 KH |
9157 | { |
9158 | unsigned long himask, lomask; | |
9159 | ||
9160 | if (shift < 32) | |
9161 | { | |
9162 | himask = 0xffff >> (32 - shift); | |
9163 | lomask = (0xffff << shift) & 0xffffffff; | |
9164 | } | |
9165 | else | |
9166 | { | |
9167 | himask = 0xffff << (shift - 32); | |
9168 | lomask = 0; | |
9169 | } | |
9170 | if ((hi32.X_add_number & ~(offsetT) himask) == 0 | |
9171 | && (lo32.X_add_number & ~(offsetT) lomask) == 0) | |
9172 | { | |
9173 | expressionS tmp; | |
9174 | ||
9175 | tmp.X_op = O_constant; | |
9176 | if (shift < 32) | |
9177 | tmp.X_add_number = ((hi32.X_add_number << (32 - shift)) | |
9178 | | (lo32.X_add_number >> shift)); | |
9179 | else | |
9180 | tmp.X_add_number = hi32.X_add_number >> (shift - 32); | |
67c0d1eb | 9181 | macro_build (&tmp, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16); |
df58fc94 | 9182 | macro_build (NULL, (shift >= 32) ? "dsll32" : "dsll", SHFT_FMT, |
67c0d1eb | 9183 | reg, reg, (shift >= 32) ? shift - 32 : shift); |
beae10d5 KH |
9184 | return; |
9185 | } | |
f9419b05 | 9186 | ++shift; |
beae10d5 KH |
9187 | } |
9188 | while (shift <= (64 - 16)); | |
252b5132 RH |
9189 | |
9190 | /* Find the bit number of the lowest one bit, and store the | |
9191 | shifted value in hi/lo. */ | |
9192 | hi = (unsigned long) (hi32.X_add_number & 0xffffffff); | |
9193 | lo = (unsigned long) (lo32.X_add_number & 0xffffffff); | |
9194 | if (lo != 0) | |
9195 | { | |
9196 | bit = 0; | |
9197 | while ((lo & 1) == 0) | |
9198 | { | |
9199 | lo >>= 1; | |
9200 | ++bit; | |
9201 | } | |
9202 | lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit); | |
9203 | hi >>= bit; | |
9204 | } | |
9205 | else | |
9206 | { | |
9207 | bit = 32; | |
9208 | while ((hi & 1) == 0) | |
9209 | { | |
9210 | hi >>= 1; | |
9211 | ++bit; | |
9212 | } | |
9213 | lo = hi; | |
9214 | hi = 0; | |
9215 | } | |
9216 | ||
9217 | /* Optimize if the shifted value is a (power of 2) - 1. */ | |
9218 | if ((hi == 0 && ((lo + 1) & lo) == 0) | |
9219 | || (lo == 0xffffffff && ((hi + 1) & hi) == 0)) | |
beae10d5 KH |
9220 | { |
9221 | shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number); | |
252b5132 | 9222 | if (shift != 0) |
beae10d5 | 9223 | { |
252b5132 RH |
9224 | expressionS tmp; |
9225 | ||
9226 | /* This instruction will set the register to be all | |
9227 | ones. */ | |
beae10d5 KH |
9228 | tmp.X_op = O_constant; |
9229 | tmp.X_add_number = (offsetT) -1; | |
67c0d1eb | 9230 | macro_build (&tmp, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
beae10d5 KH |
9231 | if (bit != 0) |
9232 | { | |
9233 | bit += shift; | |
df58fc94 | 9234 | macro_build (NULL, (bit >= 32) ? "dsll32" : "dsll", SHFT_FMT, |
67c0d1eb | 9235 | reg, reg, (bit >= 32) ? bit - 32 : bit); |
beae10d5 | 9236 | } |
df58fc94 | 9237 | macro_build (NULL, (shift >= 32) ? "dsrl32" : "dsrl", SHFT_FMT, |
67c0d1eb | 9238 | reg, reg, (shift >= 32) ? shift - 32 : shift); |
beae10d5 KH |
9239 | return; |
9240 | } | |
9241 | } | |
252b5132 RH |
9242 | |
9243 | /* Sign extend hi32 before calling load_register, because we can | |
9244 | generally get better code when we load a sign extended value. */ | |
9245 | if ((hi32.X_add_number & 0x80000000) != 0) | |
beae10d5 | 9246 | hi32.X_add_number |= ~(offsetT) 0xffffffff; |
67c0d1eb | 9247 | load_register (reg, &hi32, 0); |
252b5132 RH |
9248 | freg = reg; |
9249 | } | |
9250 | if ((lo32.X_add_number & 0xffff0000) == 0) | |
9251 | { | |
9252 | if (freg != 0) | |
9253 | { | |
df58fc94 | 9254 | macro_build (NULL, "dsll32", SHFT_FMT, reg, freg, 0); |
252b5132 RH |
9255 | freg = reg; |
9256 | } | |
9257 | } | |
9258 | else | |
9259 | { | |
9260 | expressionS mid16; | |
9261 | ||
956cd1d6 | 9262 | if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff)) |
beae10d5 | 9263 | { |
df58fc94 RS |
9264 | macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16); |
9265 | macro_build (NULL, "dsrl32", SHFT_FMT, reg, reg, 0); | |
beae10d5 KH |
9266 | return; |
9267 | } | |
252b5132 RH |
9268 | |
9269 | if (freg != 0) | |
9270 | { | |
df58fc94 | 9271 | macro_build (NULL, "dsll", SHFT_FMT, reg, freg, 16); |
252b5132 RH |
9272 | freg = reg; |
9273 | } | |
9274 | mid16 = lo32; | |
9275 | mid16.X_add_number >>= 16; | |
67c0d1eb | 9276 | macro_build (&mid16, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16); |
df58fc94 | 9277 | macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16); |
252b5132 RH |
9278 | freg = reg; |
9279 | } | |
9280 | if ((lo32.X_add_number & 0xffff) != 0) | |
67c0d1eb | 9281 | macro_build (&lo32, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16); |
252b5132 RH |
9282 | } |
9283 | ||
269137b2 TS |
9284 | static inline void |
9285 | load_delay_nop (void) | |
9286 | { | |
9287 | if (!gpr_interlocks) | |
9288 | macro_build (NULL, "nop", ""); | |
9289 | } | |
9290 | ||
252b5132 RH |
9291 | /* Load an address into a register. */ |
9292 | ||
9293 | static void | |
67c0d1eb | 9294 | load_address (int reg, expressionS *ep, int *used_at) |
252b5132 | 9295 | { |
252b5132 RH |
9296 | if (ep->X_op != O_constant |
9297 | && ep->X_op != O_symbol) | |
9298 | { | |
9299 | as_bad (_("expression too complex")); | |
9300 | ep->X_op = O_constant; | |
9301 | } | |
9302 | ||
9303 | if (ep->X_op == O_constant) | |
9304 | { | |
67c0d1eb | 9305 | load_register (reg, ep, HAVE_64BIT_ADDRESSES); |
252b5132 RH |
9306 | return; |
9307 | } | |
9308 | ||
9309 | if (mips_pic == NO_PIC) | |
9310 | { | |
9311 | /* If this is a reference to a GP relative symbol, we want | |
cdf6fd85 | 9312 | addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
9313 | Otherwise we want |
9314 | lui $reg,<sym> (BFD_RELOC_HI16_S) | |
9315 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
d6bc6245 | 9316 | If we have an addend, we always use the latter form. |
76b3015f | 9317 | |
d6bc6245 TS |
9318 | With 64bit address space and a usable $at we want |
9319 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
9320 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
9321 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
9322 | daddiu $at,<sym> (BFD_RELOC_LO16) | |
9323 | dsll32 $reg,0 | |
3a482fd5 | 9324 | daddu $reg,$reg,$at |
76b3015f | 9325 | |
c03099e6 | 9326 | If $at is already in use, we use a path which is suboptimal |
d6bc6245 TS |
9327 | on superscalar processors. |
9328 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
9329 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
9330 | dsll $reg,16 | |
9331 | daddiu $reg,<sym> (BFD_RELOC_HI16_S) | |
9332 | dsll $reg,16 | |
9333 | daddiu $reg,<sym> (BFD_RELOC_LO16) | |
6caf9ef4 TS |
9334 | |
9335 | For GP relative symbols in 64bit address space we can use | |
9336 | the same sequence as in 32bit address space. */ | |
aed1a261 | 9337 | if (HAVE_64BIT_SYMBOLS) |
d6bc6245 | 9338 | { |
6caf9ef4 TS |
9339 | if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET |
9340 | && !nopic_need_relax (ep->X_add_symbol, 1)) | |
9341 | { | |
9342 | relax_start (ep->X_add_symbol); | |
9343 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, | |
9344 | mips_gp_register, BFD_RELOC_GPREL16); | |
9345 | relax_switch (); | |
9346 | } | |
d6bc6245 | 9347 | |
741fe287 | 9348 | if (*used_at == 0 && mips_opts.at) |
d6bc6245 | 9349 | { |
df58fc94 RS |
9350 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST); |
9351 | macro_build (ep, "lui", LUI_FMT, AT, BFD_RELOC_HI16_S); | |
67c0d1eb RS |
9352 | macro_build (ep, "daddiu", "t,r,j", reg, reg, |
9353 | BFD_RELOC_MIPS_HIGHER); | |
9354 | macro_build (ep, "daddiu", "t,r,j", AT, AT, BFD_RELOC_LO16); | |
df58fc94 | 9355 | macro_build (NULL, "dsll32", SHFT_FMT, reg, reg, 0); |
67c0d1eb | 9356 | macro_build (NULL, "daddu", "d,v,t", reg, reg, AT); |
d6bc6245 TS |
9357 | *used_at = 1; |
9358 | } | |
9359 | else | |
9360 | { | |
df58fc94 | 9361 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST); |
67c0d1eb RS |
9362 | macro_build (ep, "daddiu", "t,r,j", reg, reg, |
9363 | BFD_RELOC_MIPS_HIGHER); | |
df58fc94 | 9364 | macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16); |
67c0d1eb | 9365 | macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_HI16_S); |
df58fc94 | 9366 | macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16); |
67c0d1eb | 9367 | macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_LO16); |
d6bc6245 | 9368 | } |
6caf9ef4 TS |
9369 | |
9370 | if (mips_relax.sequence) | |
9371 | relax_end (); | |
d6bc6245 | 9372 | } |
252b5132 RH |
9373 | else |
9374 | { | |
d6bc6245 | 9375 | if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 9376 | && !nopic_need_relax (ep->X_add_symbol, 1)) |
d6bc6245 | 9377 | { |
4d7206a2 | 9378 | relax_start (ep->X_add_symbol); |
67c0d1eb | 9379 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, |
17a2f251 | 9380 | mips_gp_register, BFD_RELOC_GPREL16); |
4d7206a2 | 9381 | relax_switch (); |
d6bc6245 | 9382 | } |
67c0d1eb RS |
9383 | macro_build_lui (ep, reg); |
9384 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", | |
9385 | reg, reg, BFD_RELOC_LO16); | |
4d7206a2 RS |
9386 | if (mips_relax.sequence) |
9387 | relax_end (); | |
d6bc6245 | 9388 | } |
252b5132 | 9389 | } |
0a44bf69 | 9390 | else if (!mips_big_got) |
252b5132 RH |
9391 | { |
9392 | expressionS ex; | |
9393 | ||
9394 | /* If this is a reference to an external symbol, we want | |
9395 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
9396 | Otherwise we want | |
9397 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
9398 | nop | |
9399 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
f5040a92 AO |
9400 | If there is a constant, it must be added in after. |
9401 | ||
ed6fb7bd | 9402 | If we have NewABI, we want |
f5040a92 AO |
9403 | lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP) |
9404 | unless we're referencing a global symbol with a non-zero | |
9405 | offset, in which case cst must be added separately. */ | |
ed6fb7bd SC |
9406 | if (HAVE_NEWABI) |
9407 | { | |
f5040a92 AO |
9408 | if (ep->X_add_number) |
9409 | { | |
4d7206a2 | 9410 | ex.X_add_number = ep->X_add_number; |
f5040a92 | 9411 | ep->X_add_number = 0; |
4d7206a2 | 9412 | relax_start (ep->X_add_symbol); |
67c0d1eb RS |
9413 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
9414 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
9415 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) |
9416 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
9417 | ex.X_op = O_constant; | |
67c0d1eb | 9418 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 9419 | reg, reg, BFD_RELOC_LO16); |
f5040a92 | 9420 | ep->X_add_number = ex.X_add_number; |
4d7206a2 | 9421 | relax_switch (); |
f5040a92 | 9422 | } |
67c0d1eb | 9423 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 9424 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); |
4d7206a2 RS |
9425 | if (mips_relax.sequence) |
9426 | relax_end (); | |
ed6fb7bd SC |
9427 | } |
9428 | else | |
9429 | { | |
f5040a92 AO |
9430 | ex.X_add_number = ep->X_add_number; |
9431 | ep->X_add_number = 0; | |
67c0d1eb RS |
9432 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
9433 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 9434 | load_delay_nop (); |
4d7206a2 RS |
9435 | relax_start (ep->X_add_symbol); |
9436 | relax_switch (); | |
67c0d1eb | 9437 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
17a2f251 | 9438 | BFD_RELOC_LO16); |
4d7206a2 | 9439 | relax_end (); |
ed6fb7bd | 9440 | |
f5040a92 AO |
9441 | if (ex.X_add_number != 0) |
9442 | { | |
9443 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
9444 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
9445 | ex.X_op = O_constant; | |
67c0d1eb | 9446 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 9447 | reg, reg, BFD_RELOC_LO16); |
f5040a92 | 9448 | } |
252b5132 RH |
9449 | } |
9450 | } | |
0a44bf69 | 9451 | else if (mips_big_got) |
252b5132 RH |
9452 | { |
9453 | expressionS ex; | |
252b5132 RH |
9454 | |
9455 | /* This is the large GOT case. If this is a reference to an | |
9456 | external symbol, we want | |
9457 | lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
9458 | addu $reg,$reg,$gp | |
9459 | lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16) | |
f5040a92 AO |
9460 | |
9461 | Otherwise, for a reference to a local symbol in old ABI, we want | |
252b5132 RH |
9462 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) |
9463 | nop | |
9464 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
684022ea | 9465 | If there is a constant, it must be added in after. |
f5040a92 AO |
9466 | |
9467 | In the NewABI, for local symbols, with or without offsets, we want: | |
438c16b8 TS |
9468 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) |
9469 | addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) | |
f5040a92 | 9470 | */ |
438c16b8 TS |
9471 | if (HAVE_NEWABI) |
9472 | { | |
4d7206a2 | 9473 | ex.X_add_number = ep->X_add_number; |
f5040a92 | 9474 | ep->X_add_number = 0; |
4d7206a2 | 9475 | relax_start (ep->X_add_symbol); |
df58fc94 | 9476 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
9477 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
9478 | reg, reg, mips_gp_register); | |
9479 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", | |
9480 | reg, BFD_RELOC_MIPS_GOT_LO16, reg); | |
f5040a92 AO |
9481 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) |
9482 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
9483 | else if (ex.X_add_number) | |
9484 | { | |
9485 | ex.X_op = O_constant; | |
67c0d1eb RS |
9486 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
9487 | BFD_RELOC_LO16); | |
f5040a92 AO |
9488 | } |
9489 | ||
9490 | ep->X_add_number = ex.X_add_number; | |
4d7206a2 | 9491 | relax_switch (); |
67c0d1eb | 9492 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 9493 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); |
67c0d1eb RS |
9494 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
9495 | BFD_RELOC_MIPS_GOT_OFST); | |
4d7206a2 | 9496 | relax_end (); |
438c16b8 | 9497 | } |
252b5132 | 9498 | else |
438c16b8 | 9499 | { |
f5040a92 AO |
9500 | ex.X_add_number = ep->X_add_number; |
9501 | ep->X_add_number = 0; | |
4d7206a2 | 9502 | relax_start (ep->X_add_symbol); |
df58fc94 | 9503 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
9504 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
9505 | reg, reg, mips_gp_register); | |
9506 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", | |
9507 | reg, BFD_RELOC_MIPS_GOT_LO16, reg); | |
4d7206a2 RS |
9508 | relax_switch (); |
9509 | if (reg_needs_delay (mips_gp_register)) | |
438c16b8 TS |
9510 | { |
9511 | /* We need a nop before loading from $gp. This special | |
9512 | check is required because the lui which starts the main | |
9513 | instruction stream does not refer to $gp, and so will not | |
9514 | insert the nop which may be required. */ | |
67c0d1eb | 9515 | macro_build (NULL, "nop", ""); |
438c16b8 | 9516 | } |
67c0d1eb | 9517 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 9518 | BFD_RELOC_MIPS_GOT16, mips_gp_register); |
269137b2 | 9519 | load_delay_nop (); |
67c0d1eb | 9520 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
17a2f251 | 9521 | BFD_RELOC_LO16); |
4d7206a2 | 9522 | relax_end (); |
438c16b8 | 9523 | |
f5040a92 AO |
9524 | if (ex.X_add_number != 0) |
9525 | { | |
9526 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
9527 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
9528 | ex.X_op = O_constant; | |
67c0d1eb RS |
9529 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
9530 | BFD_RELOC_LO16); | |
f5040a92 | 9531 | } |
252b5132 RH |
9532 | } |
9533 | } | |
252b5132 RH |
9534 | else |
9535 | abort (); | |
8fc2e39e | 9536 | |
741fe287 | 9537 | if (!mips_opts.at && *used_at == 1) |
1661c76c | 9538 | as_bad (_("macro used $at after \".set noat\"")); |
252b5132 RH |
9539 | } |
9540 | ||
ea1fb5dc RS |
9541 | /* Move the contents of register SOURCE into register DEST. */ |
9542 | ||
9543 | static void | |
67c0d1eb | 9544 | move_register (int dest, int source) |
ea1fb5dc | 9545 | { |
df58fc94 RS |
9546 | /* Prefer to use a 16-bit microMIPS instruction unless the previous |
9547 | instruction specifically requires a 32-bit one. */ | |
9548 | if (mips_opts.micromips | |
833794fc | 9549 | && !mips_opts.insn32 |
df58fc94 | 9550 | && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) |
7951ca42 | 9551 | macro_build (NULL, "move", "mp,mj", dest, source); |
df58fc94 | 9552 | else |
40fc1451 | 9553 | macro_build (NULL, "or", "d,v,t", dest, source, 0); |
ea1fb5dc RS |
9554 | } |
9555 | ||
4d7206a2 | 9556 | /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where |
f6a22291 MR |
9557 | LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement. |
9558 | The two alternatives are: | |
4d7206a2 | 9559 | |
33eaf5de | 9560 | Global symbol Local symbol |
4d7206a2 RS |
9561 | ------------- ------------ |
9562 | lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET) | |
9563 | ... ... | |
9564 | addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET) | |
9565 | ||
9566 | load_got_offset emits the first instruction and add_got_offset | |
f6a22291 MR |
9567 | emits the second for a 16-bit offset or add_got_offset_hilo emits |
9568 | a sequence to add a 32-bit offset using a scratch register. */ | |
4d7206a2 RS |
9569 | |
9570 | static void | |
67c0d1eb | 9571 | load_got_offset (int dest, expressionS *local) |
4d7206a2 RS |
9572 | { |
9573 | expressionS global; | |
9574 | ||
9575 | global = *local; | |
9576 | global.X_add_number = 0; | |
9577 | ||
9578 | relax_start (local->X_add_symbol); | |
67c0d1eb RS |
9579 | macro_build (&global, ADDRESS_LOAD_INSN, "t,o(b)", dest, |
9580 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
4d7206a2 | 9581 | relax_switch (); |
67c0d1eb RS |
9582 | macro_build (local, ADDRESS_LOAD_INSN, "t,o(b)", dest, |
9583 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
4d7206a2 RS |
9584 | relax_end (); |
9585 | } | |
9586 | ||
9587 | static void | |
67c0d1eb | 9588 | add_got_offset (int dest, expressionS *local) |
4d7206a2 RS |
9589 | { |
9590 | expressionS global; | |
9591 | ||
9592 | global.X_op = O_constant; | |
9593 | global.X_op_symbol = NULL; | |
9594 | global.X_add_symbol = NULL; | |
9595 | global.X_add_number = local->X_add_number; | |
9596 | ||
9597 | relax_start (local->X_add_symbol); | |
67c0d1eb | 9598 | macro_build (&global, ADDRESS_ADDI_INSN, "t,r,j", |
4d7206a2 RS |
9599 | dest, dest, BFD_RELOC_LO16); |
9600 | relax_switch (); | |
67c0d1eb | 9601 | macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", dest, dest, BFD_RELOC_LO16); |
4d7206a2 RS |
9602 | relax_end (); |
9603 | } | |
9604 | ||
f6a22291 MR |
9605 | static void |
9606 | add_got_offset_hilo (int dest, expressionS *local, int tmp) | |
9607 | { | |
9608 | expressionS global; | |
9609 | int hold_mips_optimize; | |
9610 | ||
9611 | global.X_op = O_constant; | |
9612 | global.X_op_symbol = NULL; | |
9613 | global.X_add_symbol = NULL; | |
9614 | global.X_add_number = local->X_add_number; | |
9615 | ||
9616 | relax_start (local->X_add_symbol); | |
9617 | load_register (tmp, &global, HAVE_64BIT_ADDRESSES); | |
9618 | relax_switch (); | |
9619 | /* Set mips_optimize around the lui instruction to avoid | |
9620 | inserting an unnecessary nop after the lw. */ | |
9621 | hold_mips_optimize = mips_optimize; | |
9622 | mips_optimize = 2; | |
9623 | macro_build_lui (&global, tmp); | |
9624 | mips_optimize = hold_mips_optimize; | |
9625 | macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", tmp, tmp, BFD_RELOC_LO16); | |
9626 | relax_end (); | |
9627 | ||
9628 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dest, dest, tmp); | |
9629 | } | |
9630 | ||
df58fc94 RS |
9631 | /* Emit a sequence of instructions to emulate a branch likely operation. |
9632 | BR is an ordinary branch corresponding to one to be emulated. BRNEG | |
9633 | is its complementing branch with the original condition negated. | |
9634 | CALL is set if the original branch specified the link operation. | |
9635 | EP, FMT, SREG and TREG specify the usual macro_build() parameters. | |
9636 | ||
9637 | Code like this is produced in the noreorder mode: | |
9638 | ||
9639 | BRNEG <args>, 1f | |
9640 | nop | |
9641 | b <sym> | |
9642 | delay slot (executed only if branch taken) | |
9643 | 1: | |
9644 | ||
9645 | or, if CALL is set: | |
9646 | ||
9647 | BRNEG <args>, 1f | |
9648 | nop | |
9649 | bal <sym> | |
9650 | delay slot (executed only if branch taken) | |
9651 | 1: | |
9652 | ||
9653 | In the reorder mode the delay slot would be filled with a nop anyway, | |
9654 | so code produced is simply: | |
9655 | ||
9656 | BR <args>, <sym> | |
9657 | nop | |
9658 | ||
9659 | This function is used when producing code for the microMIPS ASE that | |
9660 | does not implement branch likely instructions in hardware. */ | |
9661 | ||
9662 | static void | |
9663 | macro_build_branch_likely (const char *br, const char *brneg, | |
9664 | int call, expressionS *ep, const char *fmt, | |
9665 | unsigned int sreg, unsigned int treg) | |
9666 | { | |
9667 | int noreorder = mips_opts.noreorder; | |
9668 | expressionS expr1; | |
9669 | ||
9670 | gas_assert (mips_opts.micromips); | |
9671 | start_noreorder (); | |
9672 | if (noreorder) | |
9673 | { | |
9674 | micromips_label_expr (&expr1); | |
9675 | macro_build (&expr1, brneg, fmt, sreg, treg); | |
9676 | macro_build (NULL, "nop", ""); | |
9677 | macro_build (ep, call ? "bal" : "b", "p"); | |
9678 | ||
9679 | /* Set to true so that append_insn adds a label. */ | |
9680 | emit_branch_likely_macro = TRUE; | |
9681 | } | |
9682 | else | |
9683 | { | |
9684 | macro_build (ep, br, fmt, sreg, treg); | |
9685 | macro_build (NULL, "nop", ""); | |
9686 | } | |
9687 | end_noreorder (); | |
9688 | } | |
9689 | ||
9690 | /* Emit a coprocessor branch-likely macro specified by TYPE, using CC as | |
9691 | the condition code tested. EP specifies the branch target. */ | |
9692 | ||
9693 | static void | |
9694 | macro_build_branch_ccl (int type, expressionS *ep, unsigned int cc) | |
9695 | { | |
9696 | const int call = 0; | |
9697 | const char *brneg; | |
9698 | const char *br; | |
9699 | ||
9700 | switch (type) | |
9701 | { | |
9702 | case M_BC1FL: | |
9703 | br = "bc1f"; | |
9704 | brneg = "bc1t"; | |
9705 | break; | |
9706 | case M_BC1TL: | |
9707 | br = "bc1t"; | |
9708 | brneg = "bc1f"; | |
9709 | break; | |
9710 | case M_BC2FL: | |
9711 | br = "bc2f"; | |
9712 | brneg = "bc2t"; | |
9713 | break; | |
9714 | case M_BC2TL: | |
9715 | br = "bc2t"; | |
9716 | brneg = "bc2f"; | |
9717 | break; | |
9718 | default: | |
9719 | abort (); | |
9720 | } | |
9721 | macro_build_branch_likely (br, brneg, call, ep, "N,p", cc, ZERO); | |
9722 | } | |
9723 | ||
9724 | /* Emit a two-argument branch macro specified by TYPE, using SREG as | |
9725 | the register tested. EP specifies the branch target. */ | |
9726 | ||
9727 | static void | |
9728 | macro_build_branch_rs (int type, expressionS *ep, unsigned int sreg) | |
9729 | { | |
9730 | const char *brneg = NULL; | |
9731 | const char *br; | |
9732 | int call = 0; | |
9733 | ||
9734 | switch (type) | |
9735 | { | |
9736 | case M_BGEZ: | |
9737 | br = "bgez"; | |
9738 | break; | |
9739 | case M_BGEZL: | |
9740 | br = mips_opts.micromips ? "bgez" : "bgezl"; | |
9741 | brneg = "bltz"; | |
9742 | break; | |
9743 | case M_BGEZALL: | |
9744 | gas_assert (mips_opts.micromips); | |
833794fc | 9745 | br = mips_opts.insn32 ? "bgezal" : "bgezals"; |
df58fc94 RS |
9746 | brneg = "bltz"; |
9747 | call = 1; | |
9748 | break; | |
9749 | case M_BGTZ: | |
9750 | br = "bgtz"; | |
9751 | break; | |
9752 | case M_BGTZL: | |
9753 | br = mips_opts.micromips ? "bgtz" : "bgtzl"; | |
9754 | brneg = "blez"; | |
9755 | break; | |
9756 | case M_BLEZ: | |
9757 | br = "blez"; | |
9758 | break; | |
9759 | case M_BLEZL: | |
9760 | br = mips_opts.micromips ? "blez" : "blezl"; | |
9761 | brneg = "bgtz"; | |
9762 | break; | |
9763 | case M_BLTZ: | |
9764 | br = "bltz"; | |
9765 | break; | |
9766 | case M_BLTZL: | |
9767 | br = mips_opts.micromips ? "bltz" : "bltzl"; | |
9768 | brneg = "bgez"; | |
9769 | break; | |
9770 | case M_BLTZALL: | |
9771 | gas_assert (mips_opts.micromips); | |
833794fc | 9772 | br = mips_opts.insn32 ? "bltzal" : "bltzals"; |
df58fc94 RS |
9773 | brneg = "bgez"; |
9774 | call = 1; | |
9775 | break; | |
9776 | default: | |
9777 | abort (); | |
9778 | } | |
9779 | if (mips_opts.micromips && brneg) | |
9780 | macro_build_branch_likely (br, brneg, call, ep, "s,p", sreg, ZERO); | |
9781 | else | |
9782 | macro_build (ep, br, "s,p", sreg); | |
9783 | } | |
9784 | ||
9785 | /* Emit a three-argument branch macro specified by TYPE, using SREG and | |
9786 | TREG as the registers tested. EP specifies the branch target. */ | |
9787 | ||
9788 | static void | |
9789 | macro_build_branch_rsrt (int type, expressionS *ep, | |
9790 | unsigned int sreg, unsigned int treg) | |
9791 | { | |
9792 | const char *brneg = NULL; | |
9793 | const int call = 0; | |
9794 | const char *br; | |
9795 | ||
9796 | switch (type) | |
9797 | { | |
9798 | case M_BEQ: | |
9799 | case M_BEQ_I: | |
9800 | br = "beq"; | |
9801 | break; | |
9802 | case M_BEQL: | |
9803 | case M_BEQL_I: | |
9804 | br = mips_opts.micromips ? "beq" : "beql"; | |
9805 | brneg = "bne"; | |
9806 | break; | |
9807 | case M_BNE: | |
9808 | case M_BNE_I: | |
9809 | br = "bne"; | |
9810 | break; | |
9811 | case M_BNEL: | |
9812 | case M_BNEL_I: | |
9813 | br = mips_opts.micromips ? "bne" : "bnel"; | |
9814 | brneg = "beq"; | |
9815 | break; | |
9816 | default: | |
9817 | abort (); | |
9818 | } | |
9819 | if (mips_opts.micromips && brneg) | |
9820 | macro_build_branch_likely (br, brneg, call, ep, "s,t,p", sreg, treg); | |
9821 | else | |
9822 | macro_build (ep, br, "s,t,p", sreg, treg); | |
9823 | } | |
9824 | ||
f2ae14a1 RS |
9825 | /* Return the high part that should be loaded in order to make the low |
9826 | part of VALUE accessible using an offset of OFFBITS bits. */ | |
9827 | ||
9828 | static offsetT | |
9829 | offset_high_part (offsetT value, unsigned int offbits) | |
9830 | { | |
9831 | offsetT bias; | |
9832 | addressT low_mask; | |
9833 | ||
9834 | if (offbits == 0) | |
9835 | return value; | |
9836 | bias = 1 << (offbits - 1); | |
9837 | low_mask = bias * 2 - 1; | |
9838 | return (value + bias) & ~low_mask; | |
9839 | } | |
9840 | ||
9841 | /* Return true if the value stored in offset_expr and offset_reloc | |
9842 | fits into a signed offset of OFFBITS bits. RANGE is the maximum | |
9843 | amount that the caller wants to add without inducing overflow | |
9844 | and ALIGN is the known alignment of the value in bytes. */ | |
9845 | ||
9846 | static bfd_boolean | |
9847 | small_offset_p (unsigned int range, unsigned int align, unsigned int offbits) | |
9848 | { | |
9849 | if (offbits == 16) | |
9850 | { | |
9851 | /* Accept any relocation operator if overflow isn't a concern. */ | |
9852 | if (range < align && *offset_reloc != BFD_RELOC_UNUSED) | |
9853 | return TRUE; | |
9854 | ||
9855 | /* These relocations are guaranteed not to overflow in correct links. */ | |
9856 | if (*offset_reloc == BFD_RELOC_MIPS_LITERAL | |
9857 | || gprel16_reloc_p (*offset_reloc)) | |
9858 | return TRUE; | |
9859 | } | |
9860 | if (offset_expr.X_op == O_constant | |
9861 | && offset_high_part (offset_expr.X_add_number, offbits) == 0 | |
9862 | && offset_high_part (offset_expr.X_add_number + range, offbits) == 0) | |
9863 | return TRUE; | |
9864 | return FALSE; | |
9865 | } | |
9866 | ||
252b5132 RH |
9867 | /* |
9868 | * Build macros | |
9869 | * This routine implements the seemingly endless macro or synthesized | |
9870 | * instructions and addressing modes in the mips assembly language. Many | |
9871 | * of these macros are simple and are similar to each other. These could | |
67c1ffbe | 9872 | * probably be handled by some kind of table or grammar approach instead of |
252b5132 RH |
9873 | * this verbose method. Others are not simple macros but are more like |
9874 | * optimizing code generation. | |
9875 | * One interesting optimization is when several store macros appear | |
67c1ffbe | 9876 | * consecutively that would load AT with the upper half of the same address. |
2b0f3761 | 9877 | * The ensuing load upper instructions are omitted. This implies some kind |
252b5132 RH |
9878 | * of global optimization. We currently only optimize within a single macro. |
9879 | * For many of the load and store macros if the address is specified as a | |
9880 | * constant expression in the first 64k of memory (ie ld $2,0x4000c) we | |
9881 | * first load register 'at' with zero and use it as the base register. The | |
9882 | * mips assembler simply uses register $zero. Just one tiny optimization | |
9883 | * we're missing. | |
9884 | */ | |
9885 | static void | |
833794fc | 9886 | macro (struct mips_cl_insn *ip, char *str) |
252b5132 | 9887 | { |
c0ebe874 RS |
9888 | const struct mips_operand_array *operands; |
9889 | unsigned int breg, i; | |
741fe287 | 9890 | unsigned int tempreg; |
252b5132 | 9891 | int mask; |
43841e91 | 9892 | int used_at = 0; |
df58fc94 | 9893 | expressionS label_expr; |
252b5132 | 9894 | expressionS expr1; |
df58fc94 | 9895 | expressionS *ep; |
252b5132 RH |
9896 | const char *s; |
9897 | const char *s2; | |
9898 | const char *fmt; | |
9899 | int likely = 0; | |
252b5132 | 9900 | int coproc = 0; |
7f3c4072 | 9901 | int offbits = 16; |
1abe91b1 | 9902 | int call = 0; |
df58fc94 RS |
9903 | int jals = 0; |
9904 | int dbl = 0; | |
9905 | int imm = 0; | |
9906 | int ust = 0; | |
9907 | int lp = 0; | |
f2ae14a1 | 9908 | bfd_boolean large_offset; |
252b5132 | 9909 | int off; |
252b5132 | 9910 | int hold_mips_optimize; |
f2ae14a1 | 9911 | unsigned int align; |
c0ebe874 | 9912 | unsigned int op[MAX_OPERANDS]; |
252b5132 | 9913 | |
9c2799c2 | 9914 | gas_assert (! mips_opts.mips16); |
252b5132 | 9915 | |
c0ebe874 RS |
9916 | operands = insn_operands (ip); |
9917 | for (i = 0; i < MAX_OPERANDS; i++) | |
9918 | if (operands->operand[i]) | |
9919 | op[i] = insn_extract_operand (ip, operands->operand[i]); | |
9920 | else | |
9921 | op[i] = -1; | |
9922 | ||
252b5132 RH |
9923 | mask = ip->insn_mo->mask; |
9924 | ||
df58fc94 RS |
9925 | label_expr.X_op = O_constant; |
9926 | label_expr.X_op_symbol = NULL; | |
9927 | label_expr.X_add_symbol = NULL; | |
9928 | label_expr.X_add_number = 0; | |
9929 | ||
252b5132 RH |
9930 | expr1.X_op = O_constant; |
9931 | expr1.X_op_symbol = NULL; | |
9932 | expr1.X_add_symbol = NULL; | |
9933 | expr1.X_add_number = 1; | |
f2ae14a1 | 9934 | align = 1; |
252b5132 RH |
9935 | |
9936 | switch (mask) | |
9937 | { | |
9938 | case M_DABS: | |
9939 | dbl = 1; | |
1a0670f3 | 9940 | /* Fall through. */ |
252b5132 | 9941 | case M_ABS: |
df58fc94 RS |
9942 | /* bgez $a0,1f |
9943 | move v0,$a0 | |
9944 | sub v0,$zero,$a0 | |
9945 | 1: | |
9946 | */ | |
252b5132 | 9947 | |
7d10b47d | 9948 | start_noreorder (); |
252b5132 | 9949 | |
df58fc94 RS |
9950 | if (mips_opts.micromips) |
9951 | micromips_label_expr (&label_expr); | |
9952 | else | |
9953 | label_expr.X_add_number = 8; | |
c0ebe874 RS |
9954 | macro_build (&label_expr, "bgez", "s,p", op[1]); |
9955 | if (op[0] == op[1]) | |
a605d2b3 | 9956 | macro_build (NULL, "nop", ""); |
252b5132 | 9957 | else |
c0ebe874 RS |
9958 | move_register (op[0], op[1]); |
9959 | macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", op[0], 0, op[1]); | |
df58fc94 RS |
9960 | if (mips_opts.micromips) |
9961 | micromips_add_label (); | |
252b5132 | 9962 | |
7d10b47d | 9963 | end_noreorder (); |
8fc2e39e | 9964 | break; |
252b5132 RH |
9965 | |
9966 | case M_ADD_I: | |
9967 | s = "addi"; | |
9968 | s2 = "add"; | |
9969 | goto do_addi; | |
9970 | case M_ADDU_I: | |
9971 | s = "addiu"; | |
9972 | s2 = "addu"; | |
9973 | goto do_addi; | |
9974 | case M_DADD_I: | |
9975 | dbl = 1; | |
9976 | s = "daddi"; | |
9977 | s2 = "dadd"; | |
df58fc94 RS |
9978 | if (!mips_opts.micromips) |
9979 | goto do_addi; | |
b0e6f033 | 9980 | if (imm_expr.X_add_number >= -0x200 |
df58fc94 RS |
9981 | && imm_expr.X_add_number < 0x200) |
9982 | { | |
b0e6f033 RS |
9983 | macro_build (NULL, s, "t,r,.", op[0], op[1], |
9984 | (int) imm_expr.X_add_number); | |
df58fc94 RS |
9985 | break; |
9986 | } | |
9987 | goto do_addi_i; | |
252b5132 RH |
9988 | case M_DADDU_I: |
9989 | dbl = 1; | |
9990 | s = "daddiu"; | |
9991 | s2 = "daddu"; | |
9992 | do_addi: | |
b0e6f033 | 9993 | if (imm_expr.X_add_number >= -0x8000 |
252b5132 RH |
9994 | && imm_expr.X_add_number < 0x8000) |
9995 | { | |
c0ebe874 | 9996 | macro_build (&imm_expr, s, "t,r,j", op[0], op[1], BFD_RELOC_LO16); |
8fc2e39e | 9997 | break; |
252b5132 | 9998 | } |
df58fc94 | 9999 | do_addi_i: |
8fc2e39e | 10000 | used_at = 1; |
67c0d1eb | 10001 | load_register (AT, &imm_expr, dbl); |
c0ebe874 | 10002 | macro_build (NULL, s2, "d,v,t", op[0], op[1], AT); |
252b5132 RH |
10003 | break; |
10004 | ||
10005 | case M_AND_I: | |
10006 | s = "andi"; | |
10007 | s2 = "and"; | |
10008 | goto do_bit; | |
10009 | case M_OR_I: | |
10010 | s = "ori"; | |
10011 | s2 = "or"; | |
10012 | goto do_bit; | |
10013 | case M_NOR_I: | |
10014 | s = ""; | |
10015 | s2 = "nor"; | |
10016 | goto do_bit; | |
10017 | case M_XOR_I: | |
10018 | s = "xori"; | |
10019 | s2 = "xor"; | |
10020 | do_bit: | |
b0e6f033 | 10021 | if (imm_expr.X_add_number >= 0 |
252b5132 RH |
10022 | && imm_expr.X_add_number < 0x10000) |
10023 | { | |
10024 | if (mask != M_NOR_I) | |
c0ebe874 | 10025 | macro_build (&imm_expr, s, "t,r,i", op[0], op[1], BFD_RELOC_LO16); |
252b5132 RH |
10026 | else |
10027 | { | |
67c0d1eb | 10028 | macro_build (&imm_expr, "ori", "t,r,i", |
c0ebe874 RS |
10029 | op[0], op[1], BFD_RELOC_LO16); |
10030 | macro_build (NULL, "nor", "d,v,t", op[0], op[0], 0); | |
252b5132 | 10031 | } |
8fc2e39e | 10032 | break; |
252b5132 RH |
10033 | } |
10034 | ||
8fc2e39e | 10035 | used_at = 1; |
bad1aba3 | 10036 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
c0ebe874 | 10037 | macro_build (NULL, s2, "d,v,t", op[0], op[1], AT); |
252b5132 RH |
10038 | break; |
10039 | ||
8b082fb1 TS |
10040 | case M_BALIGN: |
10041 | switch (imm_expr.X_add_number) | |
10042 | { | |
10043 | case 0: | |
10044 | macro_build (NULL, "nop", ""); | |
10045 | break; | |
10046 | case 2: | |
c0ebe874 | 10047 | macro_build (NULL, "packrl.ph", "d,s,t", op[0], op[0], op[1]); |
8b082fb1 | 10048 | break; |
03f66e8a MR |
10049 | case 1: |
10050 | case 3: | |
c0ebe874 | 10051 | macro_build (NULL, "balign", "t,s,2", op[0], op[1], |
90ecf173 | 10052 | (int) imm_expr.X_add_number); |
8b082fb1 | 10053 | break; |
03f66e8a MR |
10054 | default: |
10055 | as_bad (_("BALIGN immediate not 0, 1, 2 or 3 (%lu)"), | |
10056 | (unsigned long) imm_expr.X_add_number); | |
10057 | break; | |
8b082fb1 TS |
10058 | } |
10059 | break; | |
10060 | ||
df58fc94 RS |
10061 | case M_BC1FL: |
10062 | case M_BC1TL: | |
10063 | case M_BC2FL: | |
10064 | case M_BC2TL: | |
10065 | gas_assert (mips_opts.micromips); | |
10066 | macro_build_branch_ccl (mask, &offset_expr, | |
10067 | EXTRACT_OPERAND (1, BCC, *ip)); | |
10068 | break; | |
10069 | ||
252b5132 | 10070 | case M_BEQ_I: |
252b5132 | 10071 | case M_BEQL_I: |
252b5132 | 10072 | case M_BNE_I: |
252b5132 | 10073 | case M_BNEL_I: |
b0e6f033 | 10074 | if (imm_expr.X_add_number == 0) |
c0ebe874 | 10075 | op[1] = 0; |
df58fc94 | 10076 | else |
252b5132 | 10077 | { |
c0ebe874 | 10078 | op[1] = AT; |
df58fc94 | 10079 | used_at = 1; |
bad1aba3 | 10080 | load_register (op[1], &imm_expr, GPR_SIZE == 64); |
252b5132 | 10081 | } |
df58fc94 RS |
10082 | /* Fall through. */ |
10083 | case M_BEQL: | |
10084 | case M_BNEL: | |
c0ebe874 | 10085 | macro_build_branch_rsrt (mask, &offset_expr, op[0], op[1]); |
252b5132 RH |
10086 | break; |
10087 | ||
10088 | case M_BGEL: | |
10089 | likely = 1; | |
1a0670f3 | 10090 | /* Fall through. */ |
252b5132 | 10091 | case M_BGE: |
c0ebe874 RS |
10092 | if (op[1] == 0) |
10093 | macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, op[0]); | |
10094 | else if (op[0] == 0) | |
10095 | macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, op[1]); | |
df58fc94 | 10096 | else |
252b5132 | 10097 | { |
df58fc94 | 10098 | used_at = 1; |
c0ebe874 | 10099 | macro_build (NULL, "slt", "d,v,t", AT, op[0], op[1]); |
df58fc94 RS |
10100 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, |
10101 | &offset_expr, AT, ZERO); | |
252b5132 | 10102 | } |
df58fc94 RS |
10103 | break; |
10104 | ||
10105 | case M_BGEZL: | |
10106 | case M_BGEZALL: | |
10107 | case M_BGTZL: | |
10108 | case M_BLEZL: | |
10109 | case M_BLTZL: | |
10110 | case M_BLTZALL: | |
c0ebe874 | 10111 | macro_build_branch_rs (mask, &offset_expr, op[0]); |
252b5132 RH |
10112 | break; |
10113 | ||
10114 | case M_BGTL_I: | |
10115 | likely = 1; | |
1a0670f3 | 10116 | /* Fall through. */ |
252b5132 | 10117 | case M_BGT_I: |
90ecf173 | 10118 | /* Check for > max integer. */ |
b0e6f033 | 10119 | if (imm_expr.X_add_number >= GPR_SMAX) |
252b5132 RH |
10120 | { |
10121 | do_false: | |
90ecf173 | 10122 | /* Result is always false. */ |
252b5132 | 10123 | if (! likely) |
a605d2b3 | 10124 | macro_build (NULL, "nop", ""); |
252b5132 | 10125 | else |
df58fc94 | 10126 | macro_build_branch_rsrt (M_BNEL, &offset_expr, ZERO, ZERO); |
8fc2e39e | 10127 | break; |
252b5132 | 10128 | } |
f9419b05 | 10129 | ++imm_expr.X_add_number; |
252b5132 RH |
10130 | /* FALLTHROUGH */ |
10131 | case M_BGE_I: | |
10132 | case M_BGEL_I: | |
10133 | if (mask == M_BGEL_I) | |
10134 | likely = 1; | |
b0e6f033 | 10135 | if (imm_expr.X_add_number == 0) |
252b5132 | 10136 | { |
df58fc94 | 10137 | macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, |
c0ebe874 | 10138 | &offset_expr, op[0]); |
8fc2e39e | 10139 | break; |
252b5132 | 10140 | } |
b0e6f033 | 10141 | if (imm_expr.X_add_number == 1) |
252b5132 | 10142 | { |
df58fc94 | 10143 | macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, |
c0ebe874 | 10144 | &offset_expr, op[0]); |
8fc2e39e | 10145 | break; |
252b5132 | 10146 | } |
b0e6f033 | 10147 | if (imm_expr.X_add_number <= GPR_SMIN) |
252b5132 RH |
10148 | { |
10149 | do_true: | |
10150 | /* result is always true */ | |
1661c76c | 10151 | as_warn (_("branch %s is always true"), ip->insn_mo->name); |
67c0d1eb | 10152 | macro_build (&offset_expr, "b", "p"); |
8fc2e39e | 10153 | break; |
252b5132 | 10154 | } |
8fc2e39e | 10155 | used_at = 1; |
c0ebe874 | 10156 | set_at (op[0], 0); |
df58fc94 RS |
10157 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, |
10158 | &offset_expr, AT, ZERO); | |
252b5132 RH |
10159 | break; |
10160 | ||
10161 | case M_BGEUL: | |
10162 | likely = 1; | |
1a0670f3 | 10163 | /* Fall through. */ |
252b5132 | 10164 | case M_BGEU: |
c0ebe874 | 10165 | if (op[1] == 0) |
252b5132 | 10166 | goto do_true; |
c0ebe874 | 10167 | else if (op[0] == 0) |
df58fc94 | 10168 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, |
c0ebe874 | 10169 | &offset_expr, ZERO, op[1]); |
df58fc94 | 10170 | else |
252b5132 | 10171 | { |
df58fc94 | 10172 | used_at = 1; |
c0ebe874 | 10173 | macro_build (NULL, "sltu", "d,v,t", AT, op[0], op[1]); |
df58fc94 RS |
10174 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, |
10175 | &offset_expr, AT, ZERO); | |
252b5132 | 10176 | } |
252b5132 RH |
10177 | break; |
10178 | ||
10179 | case M_BGTUL_I: | |
10180 | likely = 1; | |
1a0670f3 | 10181 | /* Fall through. */ |
252b5132 | 10182 | case M_BGTU_I: |
c0ebe874 | 10183 | if (op[0] == 0 |
bad1aba3 | 10184 | || (GPR_SIZE == 32 |
f01dc953 | 10185 | && imm_expr.X_add_number == -1)) |
252b5132 | 10186 | goto do_false; |
f9419b05 | 10187 | ++imm_expr.X_add_number; |
252b5132 RH |
10188 | /* FALLTHROUGH */ |
10189 | case M_BGEU_I: | |
10190 | case M_BGEUL_I: | |
10191 | if (mask == M_BGEUL_I) | |
10192 | likely = 1; | |
b0e6f033 | 10193 | if (imm_expr.X_add_number == 0) |
252b5132 | 10194 | goto do_true; |
b0e6f033 | 10195 | else if (imm_expr.X_add_number == 1) |
df58fc94 | 10196 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, |
c0ebe874 | 10197 | &offset_expr, op[0], ZERO); |
df58fc94 | 10198 | else |
252b5132 | 10199 | { |
df58fc94 | 10200 | used_at = 1; |
c0ebe874 | 10201 | set_at (op[0], 1); |
df58fc94 RS |
10202 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, |
10203 | &offset_expr, AT, ZERO); | |
252b5132 | 10204 | } |
252b5132 RH |
10205 | break; |
10206 | ||
10207 | case M_BGTL: | |
10208 | likely = 1; | |
1a0670f3 | 10209 | /* Fall through. */ |
252b5132 | 10210 | case M_BGT: |
c0ebe874 RS |
10211 | if (op[1] == 0) |
10212 | macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, op[0]); | |
10213 | else if (op[0] == 0) | |
10214 | macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, op[1]); | |
df58fc94 | 10215 | else |
252b5132 | 10216 | { |
df58fc94 | 10217 | used_at = 1; |
c0ebe874 | 10218 | macro_build (NULL, "slt", "d,v,t", AT, op[1], op[0]); |
df58fc94 RS |
10219 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, |
10220 | &offset_expr, AT, ZERO); | |
252b5132 | 10221 | } |
252b5132 RH |
10222 | break; |
10223 | ||
10224 | case M_BGTUL: | |
10225 | likely = 1; | |
1a0670f3 | 10226 | /* Fall through. */ |
252b5132 | 10227 | case M_BGTU: |
c0ebe874 | 10228 | if (op[1] == 0) |
df58fc94 | 10229 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, |
c0ebe874 RS |
10230 | &offset_expr, op[0], ZERO); |
10231 | else if (op[0] == 0) | |
df58fc94 RS |
10232 | goto do_false; |
10233 | else | |
252b5132 | 10234 | { |
df58fc94 | 10235 | used_at = 1; |
c0ebe874 | 10236 | macro_build (NULL, "sltu", "d,v,t", AT, op[1], op[0]); |
df58fc94 RS |
10237 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, |
10238 | &offset_expr, AT, ZERO); | |
252b5132 | 10239 | } |
252b5132 RH |
10240 | break; |
10241 | ||
10242 | case M_BLEL: | |
10243 | likely = 1; | |
1a0670f3 | 10244 | /* Fall through. */ |
252b5132 | 10245 | case M_BLE: |
c0ebe874 RS |
10246 | if (op[1] == 0) |
10247 | macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, op[0]); | |
10248 | else if (op[0] == 0) | |
10249 | macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, op[1]); | |
df58fc94 | 10250 | else |
252b5132 | 10251 | { |
df58fc94 | 10252 | used_at = 1; |
c0ebe874 | 10253 | macro_build (NULL, "slt", "d,v,t", AT, op[1], op[0]); |
df58fc94 RS |
10254 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, |
10255 | &offset_expr, AT, ZERO); | |
252b5132 | 10256 | } |
252b5132 RH |
10257 | break; |
10258 | ||
10259 | case M_BLEL_I: | |
10260 | likely = 1; | |
1a0670f3 | 10261 | /* Fall through. */ |
252b5132 | 10262 | case M_BLE_I: |
b0e6f033 | 10263 | if (imm_expr.X_add_number >= GPR_SMAX) |
252b5132 | 10264 | goto do_true; |
f9419b05 | 10265 | ++imm_expr.X_add_number; |
252b5132 RH |
10266 | /* FALLTHROUGH */ |
10267 | case M_BLT_I: | |
10268 | case M_BLTL_I: | |
10269 | if (mask == M_BLTL_I) | |
10270 | likely = 1; | |
b0e6f033 | 10271 | if (imm_expr.X_add_number == 0) |
c0ebe874 | 10272 | macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, op[0]); |
b0e6f033 | 10273 | else if (imm_expr.X_add_number == 1) |
c0ebe874 | 10274 | macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, op[0]); |
df58fc94 | 10275 | else |
252b5132 | 10276 | { |
df58fc94 | 10277 | used_at = 1; |
c0ebe874 | 10278 | set_at (op[0], 0); |
df58fc94 RS |
10279 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, |
10280 | &offset_expr, AT, ZERO); | |
252b5132 | 10281 | } |
252b5132 RH |
10282 | break; |
10283 | ||
10284 | case M_BLEUL: | |
10285 | likely = 1; | |
1a0670f3 | 10286 | /* Fall through. */ |
252b5132 | 10287 | case M_BLEU: |
c0ebe874 | 10288 | if (op[1] == 0) |
df58fc94 | 10289 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, |
c0ebe874 RS |
10290 | &offset_expr, op[0], ZERO); |
10291 | else if (op[0] == 0) | |
df58fc94 RS |
10292 | goto do_true; |
10293 | else | |
252b5132 | 10294 | { |
df58fc94 | 10295 | used_at = 1; |
c0ebe874 | 10296 | macro_build (NULL, "sltu", "d,v,t", AT, op[1], op[0]); |
df58fc94 RS |
10297 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, |
10298 | &offset_expr, AT, ZERO); | |
252b5132 | 10299 | } |
252b5132 RH |
10300 | break; |
10301 | ||
10302 | case M_BLEUL_I: | |
10303 | likely = 1; | |
1a0670f3 | 10304 | /* Fall through. */ |
252b5132 | 10305 | case M_BLEU_I: |
c0ebe874 | 10306 | if (op[0] == 0 |
bad1aba3 | 10307 | || (GPR_SIZE == 32 |
f01dc953 | 10308 | && imm_expr.X_add_number == -1)) |
252b5132 | 10309 | goto do_true; |
f9419b05 | 10310 | ++imm_expr.X_add_number; |
252b5132 RH |
10311 | /* FALLTHROUGH */ |
10312 | case M_BLTU_I: | |
10313 | case M_BLTUL_I: | |
10314 | if (mask == M_BLTUL_I) | |
10315 | likely = 1; | |
b0e6f033 | 10316 | if (imm_expr.X_add_number == 0) |
252b5132 | 10317 | goto do_false; |
b0e6f033 | 10318 | else if (imm_expr.X_add_number == 1) |
df58fc94 | 10319 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, |
c0ebe874 | 10320 | &offset_expr, op[0], ZERO); |
df58fc94 | 10321 | else |
252b5132 | 10322 | { |
df58fc94 | 10323 | used_at = 1; |
c0ebe874 | 10324 | set_at (op[0], 1); |
df58fc94 RS |
10325 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, |
10326 | &offset_expr, AT, ZERO); | |
252b5132 | 10327 | } |
252b5132 RH |
10328 | break; |
10329 | ||
10330 | case M_BLTL: | |
10331 | likely = 1; | |
1a0670f3 | 10332 | /* Fall through. */ |
252b5132 | 10333 | case M_BLT: |
c0ebe874 RS |
10334 | if (op[1] == 0) |
10335 | macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, op[0]); | |
10336 | else if (op[0] == 0) | |
10337 | macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, op[1]); | |
df58fc94 | 10338 | else |
252b5132 | 10339 | { |
df58fc94 | 10340 | used_at = 1; |
c0ebe874 | 10341 | macro_build (NULL, "slt", "d,v,t", AT, op[0], op[1]); |
df58fc94 RS |
10342 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, |
10343 | &offset_expr, AT, ZERO); | |
252b5132 | 10344 | } |
252b5132 RH |
10345 | break; |
10346 | ||
10347 | case M_BLTUL: | |
10348 | likely = 1; | |
1a0670f3 | 10349 | /* Fall through. */ |
252b5132 | 10350 | case M_BLTU: |
c0ebe874 | 10351 | if (op[1] == 0) |
252b5132 | 10352 | goto do_false; |
c0ebe874 | 10353 | else if (op[0] == 0) |
df58fc94 | 10354 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, |
c0ebe874 | 10355 | &offset_expr, ZERO, op[1]); |
df58fc94 | 10356 | else |
252b5132 | 10357 | { |
df58fc94 | 10358 | used_at = 1; |
c0ebe874 | 10359 | macro_build (NULL, "sltu", "d,v,t", AT, op[0], op[1]); |
df58fc94 RS |
10360 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, |
10361 | &offset_expr, AT, ZERO); | |
252b5132 | 10362 | } |
252b5132 RH |
10363 | break; |
10364 | ||
10365 | case M_DDIV_3: | |
10366 | dbl = 1; | |
1a0670f3 | 10367 | /* Fall through. */ |
252b5132 RH |
10368 | case M_DIV_3: |
10369 | s = "mflo"; | |
10370 | goto do_div3; | |
10371 | case M_DREM_3: | |
10372 | dbl = 1; | |
1a0670f3 | 10373 | /* Fall through. */ |
252b5132 RH |
10374 | case M_REM_3: |
10375 | s = "mfhi"; | |
10376 | do_div3: | |
c0ebe874 | 10377 | if (op[2] == 0) |
252b5132 | 10378 | { |
1661c76c | 10379 | as_warn (_("divide by zero")); |
252b5132 | 10380 | if (mips_trap) |
df58fc94 | 10381 | macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7); |
252b5132 | 10382 | else |
df58fc94 | 10383 | macro_build (NULL, "break", BRK_FMT, 7); |
8fc2e39e | 10384 | break; |
252b5132 RH |
10385 | } |
10386 | ||
7d10b47d | 10387 | start_noreorder (); |
252b5132 RH |
10388 | if (mips_trap) |
10389 | { | |
c0ebe874 RS |
10390 | macro_build (NULL, "teq", TRAP_FMT, op[2], ZERO, 7); |
10391 | macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", op[1], op[2]); | |
252b5132 RH |
10392 | } |
10393 | else | |
10394 | { | |
df58fc94 RS |
10395 | if (mips_opts.micromips) |
10396 | micromips_label_expr (&label_expr); | |
10397 | else | |
10398 | label_expr.X_add_number = 8; | |
c0ebe874 RS |
10399 | macro_build (&label_expr, "bne", "s,t,p", op[2], ZERO); |
10400 | macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", op[1], op[2]); | |
df58fc94 RS |
10401 | macro_build (NULL, "break", BRK_FMT, 7); |
10402 | if (mips_opts.micromips) | |
10403 | micromips_add_label (); | |
252b5132 RH |
10404 | } |
10405 | expr1.X_add_number = -1; | |
8fc2e39e | 10406 | used_at = 1; |
f6a22291 | 10407 | load_register (AT, &expr1, dbl); |
df58fc94 RS |
10408 | if (mips_opts.micromips) |
10409 | micromips_label_expr (&label_expr); | |
10410 | else | |
10411 | label_expr.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16); | |
c0ebe874 | 10412 | macro_build (&label_expr, "bne", "s,t,p", op[2], AT); |
252b5132 RH |
10413 | if (dbl) |
10414 | { | |
10415 | expr1.X_add_number = 1; | |
f6a22291 | 10416 | load_register (AT, &expr1, dbl); |
df58fc94 | 10417 | macro_build (NULL, "dsll32", SHFT_FMT, AT, AT, 31); |
252b5132 RH |
10418 | } |
10419 | else | |
10420 | { | |
10421 | expr1.X_add_number = 0x80000000; | |
df58fc94 | 10422 | macro_build (&expr1, "lui", LUI_FMT, AT, BFD_RELOC_HI16); |
252b5132 RH |
10423 | } |
10424 | if (mips_trap) | |
10425 | { | |
c0ebe874 | 10426 | macro_build (NULL, "teq", TRAP_FMT, op[1], AT, 6); |
252b5132 RH |
10427 | /* We want to close the noreorder block as soon as possible, so |
10428 | that later insns are available for delay slot filling. */ | |
7d10b47d | 10429 | end_noreorder (); |
252b5132 RH |
10430 | } |
10431 | else | |
10432 | { | |
df58fc94 RS |
10433 | if (mips_opts.micromips) |
10434 | micromips_label_expr (&label_expr); | |
10435 | else | |
10436 | label_expr.X_add_number = 8; | |
c0ebe874 | 10437 | macro_build (&label_expr, "bne", "s,t,p", op[1], AT); |
a605d2b3 | 10438 | macro_build (NULL, "nop", ""); |
252b5132 RH |
10439 | |
10440 | /* We want to close the noreorder block as soon as possible, so | |
10441 | that later insns are available for delay slot filling. */ | |
7d10b47d | 10442 | end_noreorder (); |
252b5132 | 10443 | |
df58fc94 | 10444 | macro_build (NULL, "break", BRK_FMT, 6); |
252b5132 | 10445 | } |
df58fc94 RS |
10446 | if (mips_opts.micromips) |
10447 | micromips_add_label (); | |
c0ebe874 | 10448 | macro_build (NULL, s, MFHL_FMT, op[0]); |
252b5132 RH |
10449 | break; |
10450 | ||
10451 | case M_DIV_3I: | |
10452 | s = "div"; | |
10453 | s2 = "mflo"; | |
10454 | goto do_divi; | |
10455 | case M_DIVU_3I: | |
10456 | s = "divu"; | |
10457 | s2 = "mflo"; | |
10458 | goto do_divi; | |
10459 | case M_REM_3I: | |
10460 | s = "div"; | |
10461 | s2 = "mfhi"; | |
10462 | goto do_divi; | |
10463 | case M_REMU_3I: | |
10464 | s = "divu"; | |
10465 | s2 = "mfhi"; | |
10466 | goto do_divi; | |
10467 | case M_DDIV_3I: | |
10468 | dbl = 1; | |
10469 | s = "ddiv"; | |
10470 | s2 = "mflo"; | |
10471 | goto do_divi; | |
10472 | case M_DDIVU_3I: | |
10473 | dbl = 1; | |
10474 | s = "ddivu"; | |
10475 | s2 = "mflo"; | |
10476 | goto do_divi; | |
10477 | case M_DREM_3I: | |
10478 | dbl = 1; | |
10479 | s = "ddiv"; | |
10480 | s2 = "mfhi"; | |
10481 | goto do_divi; | |
10482 | case M_DREMU_3I: | |
10483 | dbl = 1; | |
10484 | s = "ddivu"; | |
10485 | s2 = "mfhi"; | |
10486 | do_divi: | |
b0e6f033 | 10487 | if (imm_expr.X_add_number == 0) |
252b5132 | 10488 | { |
1661c76c | 10489 | as_warn (_("divide by zero")); |
252b5132 | 10490 | if (mips_trap) |
df58fc94 | 10491 | macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7); |
252b5132 | 10492 | else |
df58fc94 | 10493 | macro_build (NULL, "break", BRK_FMT, 7); |
8fc2e39e | 10494 | break; |
252b5132 | 10495 | } |
b0e6f033 | 10496 | if (imm_expr.X_add_number == 1) |
252b5132 RH |
10497 | { |
10498 | if (strcmp (s2, "mflo") == 0) | |
c0ebe874 | 10499 | move_register (op[0], op[1]); |
252b5132 | 10500 | else |
c0ebe874 | 10501 | move_register (op[0], ZERO); |
8fc2e39e | 10502 | break; |
252b5132 | 10503 | } |
b0e6f033 | 10504 | if (imm_expr.X_add_number == -1 && s[strlen (s) - 1] != 'u') |
252b5132 RH |
10505 | { |
10506 | if (strcmp (s2, "mflo") == 0) | |
c0ebe874 | 10507 | macro_build (NULL, dbl ? "dneg" : "neg", "d,w", op[0], op[1]); |
252b5132 | 10508 | else |
c0ebe874 | 10509 | move_register (op[0], ZERO); |
8fc2e39e | 10510 | break; |
252b5132 RH |
10511 | } |
10512 | ||
8fc2e39e | 10513 | used_at = 1; |
67c0d1eb | 10514 | load_register (AT, &imm_expr, dbl); |
c0ebe874 RS |
10515 | macro_build (NULL, s, "z,s,t", op[1], AT); |
10516 | macro_build (NULL, s2, MFHL_FMT, op[0]); | |
252b5132 RH |
10517 | break; |
10518 | ||
10519 | case M_DIVU_3: | |
10520 | s = "divu"; | |
10521 | s2 = "mflo"; | |
10522 | goto do_divu3; | |
10523 | case M_REMU_3: | |
10524 | s = "divu"; | |
10525 | s2 = "mfhi"; | |
10526 | goto do_divu3; | |
10527 | case M_DDIVU_3: | |
10528 | s = "ddivu"; | |
10529 | s2 = "mflo"; | |
10530 | goto do_divu3; | |
10531 | case M_DREMU_3: | |
10532 | s = "ddivu"; | |
10533 | s2 = "mfhi"; | |
10534 | do_divu3: | |
7d10b47d | 10535 | start_noreorder (); |
252b5132 RH |
10536 | if (mips_trap) |
10537 | { | |
c0ebe874 RS |
10538 | macro_build (NULL, "teq", TRAP_FMT, op[2], ZERO, 7); |
10539 | macro_build (NULL, s, "z,s,t", op[1], op[2]); | |
252b5132 RH |
10540 | /* We want to close the noreorder block as soon as possible, so |
10541 | that later insns are available for delay slot filling. */ | |
7d10b47d | 10542 | end_noreorder (); |
252b5132 RH |
10543 | } |
10544 | else | |
10545 | { | |
df58fc94 RS |
10546 | if (mips_opts.micromips) |
10547 | micromips_label_expr (&label_expr); | |
10548 | else | |
10549 | label_expr.X_add_number = 8; | |
c0ebe874 RS |
10550 | macro_build (&label_expr, "bne", "s,t,p", op[2], ZERO); |
10551 | macro_build (NULL, s, "z,s,t", op[1], op[2]); | |
252b5132 RH |
10552 | |
10553 | /* We want to close the noreorder block as soon as possible, so | |
10554 | that later insns are available for delay slot filling. */ | |
7d10b47d | 10555 | end_noreorder (); |
df58fc94 RS |
10556 | macro_build (NULL, "break", BRK_FMT, 7); |
10557 | if (mips_opts.micromips) | |
10558 | micromips_add_label (); | |
252b5132 | 10559 | } |
c0ebe874 | 10560 | macro_build (NULL, s2, MFHL_FMT, op[0]); |
8fc2e39e | 10561 | break; |
252b5132 | 10562 | |
1abe91b1 MR |
10563 | case M_DLCA_AB: |
10564 | dbl = 1; | |
1a0670f3 | 10565 | /* Fall through. */ |
1abe91b1 MR |
10566 | case M_LCA_AB: |
10567 | call = 1; | |
10568 | goto do_la; | |
252b5132 RH |
10569 | case M_DLA_AB: |
10570 | dbl = 1; | |
1a0670f3 | 10571 | /* Fall through. */ |
252b5132 | 10572 | case M_LA_AB: |
1abe91b1 | 10573 | do_la: |
252b5132 RH |
10574 | /* Load the address of a symbol into a register. If breg is not |
10575 | zero, we then add a base register to it. */ | |
10576 | ||
c0ebe874 | 10577 | breg = op[2]; |
bad1aba3 | 10578 | if (dbl && GPR_SIZE == 32) |
ece794d9 MF |
10579 | as_warn (_("dla used to load 32-bit register; recommend using la " |
10580 | "instead")); | |
3bec30a8 | 10581 | |
90ecf173 | 10582 | if (!dbl && HAVE_64BIT_OBJECTS) |
ece794d9 MF |
10583 | as_warn (_("la used to load 64-bit address; recommend using dla " |
10584 | "instead")); | |
3bec30a8 | 10585 | |
f2ae14a1 | 10586 | if (small_offset_p (0, align, 16)) |
0c11417f | 10587 | { |
c0ebe874 | 10588 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", op[0], breg, |
f2ae14a1 | 10589 | -1, offset_reloc[0], offset_reloc[1], offset_reloc[2]); |
8fc2e39e | 10590 | break; |
0c11417f MR |
10591 | } |
10592 | ||
c0ebe874 | 10593 | if (mips_opts.at && (op[0] == breg)) |
afdbd6d0 CD |
10594 | { |
10595 | tempreg = AT; | |
10596 | used_at = 1; | |
10597 | } | |
10598 | else | |
c0ebe874 | 10599 | tempreg = op[0]; |
afdbd6d0 | 10600 | |
252b5132 RH |
10601 | if (offset_expr.X_op != O_symbol |
10602 | && offset_expr.X_op != O_constant) | |
10603 | { | |
1661c76c | 10604 | as_bad (_("expression too complex")); |
252b5132 RH |
10605 | offset_expr.X_op = O_constant; |
10606 | } | |
10607 | ||
252b5132 | 10608 | if (offset_expr.X_op == O_constant) |
aed1a261 | 10609 | load_register (tempreg, &offset_expr, HAVE_64BIT_ADDRESSES); |
252b5132 RH |
10610 | else if (mips_pic == NO_PIC) |
10611 | { | |
d6bc6245 | 10612 | /* If this is a reference to a GP relative symbol, we want |
cdf6fd85 | 10613 | addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
10614 | Otherwise we want |
10615 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
10616 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
10617 | If we have a constant, we need two instructions anyhow, | |
d6bc6245 | 10618 | so we may as well always use the latter form. |
76b3015f | 10619 | |
6caf9ef4 TS |
10620 | With 64bit address space and a usable $at we want |
10621 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
10622 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
10623 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
10624 | daddiu $at,<sym> (BFD_RELOC_LO16) | |
10625 | dsll32 $tempreg,0 | |
10626 | daddu $tempreg,$tempreg,$at | |
10627 | ||
10628 | If $at is already in use, we use a path which is suboptimal | |
10629 | on superscalar processors. | |
10630 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
10631 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
10632 | dsll $tempreg,16 | |
10633 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
10634 | dsll $tempreg,16 | |
10635 | daddiu $tempreg,<sym> (BFD_RELOC_LO16) | |
10636 | ||
10637 | For GP relative symbols in 64bit address space we can use | |
10638 | the same sequence as in 32bit address space. */ | |
aed1a261 | 10639 | if (HAVE_64BIT_SYMBOLS) |
252b5132 | 10640 | { |
6caf9ef4 TS |
10641 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
10642 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) | |
10643 | { | |
10644 | relax_start (offset_expr.X_add_symbol); | |
10645 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
10646 | tempreg, mips_gp_register, BFD_RELOC_GPREL16); | |
10647 | relax_switch (); | |
10648 | } | |
d6bc6245 | 10649 | |
741fe287 | 10650 | if (used_at == 0 && mips_opts.at) |
98d3f06f | 10651 | { |
df58fc94 | 10652 | macro_build (&offset_expr, "lui", LUI_FMT, |
17a2f251 | 10653 | tempreg, BFD_RELOC_MIPS_HIGHEST); |
df58fc94 | 10654 | macro_build (&offset_expr, "lui", LUI_FMT, |
17a2f251 | 10655 | AT, BFD_RELOC_HI16_S); |
67c0d1eb | 10656 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 10657 | tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); |
67c0d1eb | 10658 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 10659 | AT, AT, BFD_RELOC_LO16); |
df58fc94 | 10660 | macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0); |
67c0d1eb | 10661 | macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT); |
98d3f06f KH |
10662 | used_at = 1; |
10663 | } | |
10664 | else | |
10665 | { | |
df58fc94 | 10666 | macro_build (&offset_expr, "lui", LUI_FMT, |
17a2f251 | 10667 | tempreg, BFD_RELOC_MIPS_HIGHEST); |
67c0d1eb | 10668 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 10669 | tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); |
df58fc94 | 10670 | macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16); |
67c0d1eb | 10671 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 10672 | tempreg, tempreg, BFD_RELOC_HI16_S); |
df58fc94 | 10673 | macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16); |
67c0d1eb | 10674 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 10675 | tempreg, tempreg, BFD_RELOC_LO16); |
98d3f06f | 10676 | } |
6caf9ef4 TS |
10677 | |
10678 | if (mips_relax.sequence) | |
10679 | relax_end (); | |
98d3f06f KH |
10680 | } |
10681 | else | |
10682 | { | |
10683 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET | |
6caf9ef4 | 10684 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
98d3f06f | 10685 | { |
4d7206a2 | 10686 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
10687 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
10688 | tempreg, mips_gp_register, BFD_RELOC_GPREL16); | |
4d7206a2 | 10689 | relax_switch (); |
98d3f06f | 10690 | } |
6943caf0 | 10691 | if (!IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) |
1661c76c | 10692 | as_bad (_("offset too large")); |
67c0d1eb RS |
10693 | macro_build_lui (&offset_expr, tempreg); |
10694 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
10695 | tempreg, tempreg, BFD_RELOC_LO16); | |
4d7206a2 RS |
10696 | if (mips_relax.sequence) |
10697 | relax_end (); | |
98d3f06f | 10698 | } |
252b5132 | 10699 | } |
0a44bf69 | 10700 | else if (!mips_big_got && !HAVE_NEWABI) |
252b5132 | 10701 | { |
9117d219 NC |
10702 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
10703 | ||
252b5132 RH |
10704 | /* If this is a reference to an external symbol, and there |
10705 | is no constant, we want | |
10706 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
1abe91b1 | 10707 | or for lca or if tempreg is PIC_CALL_REG |
9117d219 | 10708 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
252b5132 RH |
10709 | For a local symbol, we want |
10710 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
10711 | nop | |
10712 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
10713 | ||
10714 | If we have a small constant, and this is a reference to | |
10715 | an external symbol, we want | |
10716 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
10717 | nop | |
10718 | addiu $tempreg,$tempreg,<constant> | |
10719 | For a local symbol, we want the same instruction | |
10720 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
10721 | addiu instruction. | |
10722 | ||
10723 | If we have a large constant, and this is a reference to | |
10724 | an external symbol, we want | |
10725 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
10726 | lui $at,<hiconstant> | |
10727 | addiu $at,$at,<loconstant> | |
10728 | addu $tempreg,$tempreg,$at | |
10729 | For a local symbol, we want the same instruction | |
10730 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
ed6fb7bd | 10731 | addiu instruction. |
ed6fb7bd SC |
10732 | */ |
10733 | ||
4d7206a2 | 10734 | if (offset_expr.X_add_number == 0) |
252b5132 | 10735 | { |
0a44bf69 RS |
10736 | if (mips_pic == SVR4_PIC |
10737 | && breg == 0 | |
10738 | && (call || tempreg == PIC_CALL_REG)) | |
4d7206a2 RS |
10739 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16; |
10740 | ||
10741 | relax_start (offset_expr.X_add_symbol); | |
67c0d1eb RS |
10742 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
10743 | lw_reloc_type, mips_gp_register); | |
4d7206a2 | 10744 | if (breg != 0) |
252b5132 RH |
10745 | { |
10746 | /* We're going to put in an addu instruction using | |
10747 | tempreg, so we may as well insert the nop right | |
10748 | now. */ | |
269137b2 | 10749 | load_delay_nop (); |
252b5132 | 10750 | } |
4d7206a2 | 10751 | relax_switch (); |
67c0d1eb RS |
10752 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
10753 | tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 10754 | load_delay_nop (); |
67c0d1eb RS |
10755 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
10756 | tempreg, tempreg, BFD_RELOC_LO16); | |
4d7206a2 | 10757 | relax_end (); |
252b5132 RH |
10758 | /* FIXME: If breg == 0, and the next instruction uses |
10759 | $tempreg, then if this variant case is used an extra | |
10760 | nop will be generated. */ | |
10761 | } | |
4d7206a2 RS |
10762 | else if (offset_expr.X_add_number >= -0x8000 |
10763 | && offset_expr.X_add_number < 0x8000) | |
252b5132 | 10764 | { |
67c0d1eb | 10765 | load_got_offset (tempreg, &offset_expr); |
269137b2 | 10766 | load_delay_nop (); |
67c0d1eb | 10767 | add_got_offset (tempreg, &offset_expr); |
252b5132 RH |
10768 | } |
10769 | else | |
10770 | { | |
4d7206a2 RS |
10771 | expr1.X_add_number = offset_expr.X_add_number; |
10772 | offset_expr.X_add_number = | |
43c0598f | 10773 | SEXT_16BIT (offset_expr.X_add_number); |
67c0d1eb | 10774 | load_got_offset (tempreg, &offset_expr); |
f6a22291 | 10775 | offset_expr.X_add_number = expr1.X_add_number; |
252b5132 RH |
10776 | /* If we are going to add in a base register, and the |
10777 | target register and the base register are the same, | |
10778 | then we are using AT as a temporary register. Since | |
10779 | we want to load the constant into AT, we add our | |
10780 | current AT (from the global offset table) and the | |
10781 | register into the register now, and pretend we were | |
10782 | not using a base register. */ | |
c0ebe874 | 10783 | if (breg == op[0]) |
252b5132 | 10784 | { |
269137b2 | 10785 | load_delay_nop (); |
67c0d1eb | 10786 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
c0ebe874 | 10787 | op[0], AT, breg); |
252b5132 | 10788 | breg = 0; |
c0ebe874 | 10789 | tempreg = op[0]; |
252b5132 | 10790 | } |
f6a22291 | 10791 | add_got_offset_hilo (tempreg, &offset_expr, AT); |
252b5132 RH |
10792 | used_at = 1; |
10793 | } | |
10794 | } | |
0a44bf69 | 10795 | else if (!mips_big_got && HAVE_NEWABI) |
f5040a92 | 10796 | { |
67c0d1eb | 10797 | int add_breg_early = 0; |
f5040a92 AO |
10798 | |
10799 | /* If this is a reference to an external, and there is no | |
10800 | constant, or local symbol (*), with or without a | |
10801 | constant, we want | |
10802 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
1abe91b1 | 10803 | or for lca or if tempreg is PIC_CALL_REG |
f5040a92 AO |
10804 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
10805 | ||
10806 | If we have a small constant, and this is a reference to | |
10807 | an external symbol, we want | |
10808 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
10809 | addiu $tempreg,$tempreg,<constant> | |
10810 | ||
10811 | If we have a large constant, and this is a reference to | |
10812 | an external symbol, we want | |
10813 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
10814 | lui $at,<hiconstant> | |
10815 | addiu $at,$at,<loconstant> | |
10816 | addu $tempreg,$tempreg,$at | |
10817 | ||
10818 | (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for | |
10819 | local symbols, even though it introduces an additional | |
10820 | instruction. */ | |
10821 | ||
f5040a92 AO |
10822 | if (offset_expr.X_add_number) |
10823 | { | |
4d7206a2 | 10824 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
10825 | offset_expr.X_add_number = 0; |
10826 | ||
4d7206a2 | 10827 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
10828 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
10829 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
10830 | |
10831 | if (expr1.X_add_number >= -0x8000 | |
10832 | && expr1.X_add_number < 0x8000) | |
10833 | { | |
67c0d1eb RS |
10834 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
10835 | tempreg, tempreg, BFD_RELOC_LO16); | |
f5040a92 | 10836 | } |
ecd13cd3 | 10837 | else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000)) |
f5040a92 | 10838 | { |
c0ebe874 RS |
10839 | unsigned int dreg; |
10840 | ||
f5040a92 AO |
10841 | /* If we are going to add in a base register, and the |
10842 | target register and the base register are the same, | |
10843 | then we are using AT as a temporary register. Since | |
10844 | we want to load the constant into AT, we add our | |
10845 | current AT (from the global offset table) and the | |
10846 | register into the register now, and pretend we were | |
10847 | not using a base register. */ | |
c0ebe874 | 10848 | if (breg != op[0]) |
f5040a92 AO |
10849 | dreg = tempreg; |
10850 | else | |
10851 | { | |
9c2799c2 | 10852 | gas_assert (tempreg == AT); |
67c0d1eb | 10853 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
c0ebe874 RS |
10854 | op[0], AT, breg); |
10855 | dreg = op[0]; | |
67c0d1eb | 10856 | add_breg_early = 1; |
f5040a92 AO |
10857 | } |
10858 | ||
f6a22291 | 10859 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 10860 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 10861 | dreg, dreg, AT); |
f5040a92 | 10862 | |
f5040a92 AO |
10863 | used_at = 1; |
10864 | } | |
10865 | else | |
10866 | as_bad (_("PIC code offset overflow (max 32 signed bits)")); | |
10867 | ||
4d7206a2 | 10868 | relax_switch (); |
f5040a92 AO |
10869 | offset_expr.X_add_number = expr1.X_add_number; |
10870 | ||
67c0d1eb RS |
10871 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
10872 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
10873 | if (add_breg_early) | |
f5040a92 | 10874 | { |
67c0d1eb | 10875 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
c0ebe874 | 10876 | op[0], tempreg, breg); |
f5040a92 | 10877 | breg = 0; |
c0ebe874 | 10878 | tempreg = op[0]; |
f5040a92 | 10879 | } |
4d7206a2 | 10880 | relax_end (); |
f5040a92 | 10881 | } |
4d7206a2 | 10882 | else if (breg == 0 && (call || tempreg == PIC_CALL_REG)) |
f5040a92 | 10883 | { |
4d7206a2 | 10884 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
10885 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
10886 | BFD_RELOC_MIPS_CALL16, mips_gp_register); | |
4d7206a2 | 10887 | relax_switch (); |
67c0d1eb RS |
10888 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
10889 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
4d7206a2 | 10890 | relax_end (); |
f5040a92 | 10891 | } |
4d7206a2 | 10892 | else |
f5040a92 | 10893 | { |
67c0d1eb RS |
10894 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
10895 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
10896 | } |
10897 | } | |
0a44bf69 | 10898 | else if (mips_big_got && !HAVE_NEWABI) |
252b5132 | 10899 | { |
67c0d1eb | 10900 | int gpdelay; |
9117d219 NC |
10901 | int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; |
10902 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; | |
ed6fb7bd | 10903 | int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
252b5132 RH |
10904 | |
10905 | /* This is the large GOT case. If this is a reference to an | |
10906 | external symbol, and there is no constant, we want | |
10907 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
10908 | addu $tempreg,$tempreg,$gp | |
10909 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
1abe91b1 | 10910 | or for lca or if tempreg is PIC_CALL_REG |
9117d219 NC |
10911 | lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) |
10912 | addu $tempreg,$tempreg,$gp | |
10913 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) | |
252b5132 RH |
10914 | For a local symbol, we want |
10915 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
10916 | nop | |
10917 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
10918 | ||
10919 | If we have a small constant, and this is a reference to | |
10920 | an external symbol, we want | |
10921 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
10922 | addu $tempreg,$tempreg,$gp | |
10923 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
10924 | nop | |
10925 | addiu $tempreg,$tempreg,<constant> | |
10926 | For a local symbol, we want | |
10927 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
10928 | nop | |
10929 | addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16) | |
10930 | ||
10931 | If we have a large constant, and this is a reference to | |
10932 | an external symbol, we want | |
10933 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
10934 | addu $tempreg,$tempreg,$gp | |
10935 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
10936 | lui $at,<hiconstant> | |
10937 | addiu $at,$at,<loconstant> | |
10938 | addu $tempreg,$tempreg,$at | |
10939 | For a local symbol, we want | |
10940 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
10941 | lui $at,<hiconstant> | |
10942 | addiu $at,$at,<loconstant> (BFD_RELOC_LO16) | |
10943 | addu $tempreg,$tempreg,$at | |
f5040a92 | 10944 | */ |
438c16b8 | 10945 | |
252b5132 RH |
10946 | expr1.X_add_number = offset_expr.X_add_number; |
10947 | offset_expr.X_add_number = 0; | |
4d7206a2 | 10948 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 10949 | gpdelay = reg_needs_delay (mips_gp_register); |
1abe91b1 MR |
10950 | if (expr1.X_add_number == 0 && breg == 0 |
10951 | && (call || tempreg == PIC_CALL_REG)) | |
9117d219 NC |
10952 | { |
10953 | lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; | |
10954 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; | |
10955 | } | |
df58fc94 | 10956 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type); |
67c0d1eb | 10957 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 10958 | tempreg, tempreg, mips_gp_register); |
67c0d1eb | 10959 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
17a2f251 | 10960 | tempreg, lw_reloc_type, tempreg); |
252b5132 RH |
10961 | if (expr1.X_add_number == 0) |
10962 | { | |
67c0d1eb | 10963 | if (breg != 0) |
252b5132 RH |
10964 | { |
10965 | /* We're going to put in an addu instruction using | |
10966 | tempreg, so we may as well insert the nop right | |
10967 | now. */ | |
269137b2 | 10968 | load_delay_nop (); |
252b5132 | 10969 | } |
252b5132 RH |
10970 | } |
10971 | else if (expr1.X_add_number >= -0x8000 | |
10972 | && expr1.X_add_number < 0x8000) | |
10973 | { | |
269137b2 | 10974 | load_delay_nop (); |
67c0d1eb | 10975 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 10976 | tempreg, tempreg, BFD_RELOC_LO16); |
252b5132 RH |
10977 | } |
10978 | else | |
10979 | { | |
c0ebe874 RS |
10980 | unsigned int dreg; |
10981 | ||
252b5132 RH |
10982 | /* If we are going to add in a base register, and the |
10983 | target register and the base register are the same, | |
10984 | then we are using AT as a temporary register. Since | |
10985 | we want to load the constant into AT, we add our | |
10986 | current AT (from the global offset table) and the | |
10987 | register into the register now, and pretend we were | |
10988 | not using a base register. */ | |
c0ebe874 | 10989 | if (breg != op[0]) |
67c0d1eb | 10990 | dreg = tempreg; |
252b5132 RH |
10991 | else |
10992 | { | |
9c2799c2 | 10993 | gas_assert (tempreg == AT); |
269137b2 | 10994 | load_delay_nop (); |
67c0d1eb | 10995 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
c0ebe874 RS |
10996 | op[0], AT, breg); |
10997 | dreg = op[0]; | |
252b5132 RH |
10998 | } |
10999 | ||
f6a22291 | 11000 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 11001 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT); |
252b5132 | 11002 | |
252b5132 RH |
11003 | used_at = 1; |
11004 | } | |
43c0598f | 11005 | offset_expr.X_add_number = SEXT_16BIT (expr1.X_add_number); |
4d7206a2 | 11006 | relax_switch (); |
252b5132 | 11007 | |
67c0d1eb | 11008 | if (gpdelay) |
252b5132 RH |
11009 | { |
11010 | /* This is needed because this instruction uses $gp, but | |
f5040a92 | 11011 | the first instruction on the main stream does not. */ |
67c0d1eb | 11012 | macro_build (NULL, "nop", ""); |
252b5132 | 11013 | } |
ed6fb7bd | 11014 | |
67c0d1eb RS |
11015 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
11016 | local_reloc_type, mips_gp_register); | |
f5040a92 | 11017 | if (expr1.X_add_number >= -0x8000 |
252b5132 RH |
11018 | && expr1.X_add_number < 0x8000) |
11019 | { | |
269137b2 | 11020 | load_delay_nop (); |
67c0d1eb RS |
11021 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
11022 | tempreg, tempreg, BFD_RELOC_LO16); | |
252b5132 | 11023 | /* FIXME: If add_number is 0, and there was no base |
f5040a92 AO |
11024 | register, the external symbol case ended with a load, |
11025 | so if the symbol turns out to not be external, and | |
11026 | the next instruction uses tempreg, an unnecessary nop | |
11027 | will be inserted. */ | |
252b5132 RH |
11028 | } |
11029 | else | |
11030 | { | |
c0ebe874 | 11031 | if (breg == op[0]) |
252b5132 RH |
11032 | { |
11033 | /* We must add in the base register now, as in the | |
f5040a92 | 11034 | external symbol case. */ |
9c2799c2 | 11035 | gas_assert (tempreg == AT); |
269137b2 | 11036 | load_delay_nop (); |
67c0d1eb | 11037 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
c0ebe874 RS |
11038 | op[0], AT, breg); |
11039 | tempreg = op[0]; | |
252b5132 | 11040 | /* We set breg to 0 because we have arranged to add |
f5040a92 | 11041 | it in in both cases. */ |
252b5132 RH |
11042 | breg = 0; |
11043 | } | |
11044 | ||
67c0d1eb RS |
11045 | macro_build_lui (&expr1, AT); |
11046 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
17a2f251 | 11047 | AT, AT, BFD_RELOC_LO16); |
67c0d1eb | 11048 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 11049 | tempreg, tempreg, AT); |
8fc2e39e | 11050 | used_at = 1; |
252b5132 | 11051 | } |
4d7206a2 | 11052 | relax_end (); |
252b5132 | 11053 | } |
0a44bf69 | 11054 | else if (mips_big_got && HAVE_NEWABI) |
f5040a92 | 11055 | { |
f5040a92 AO |
11056 | int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; |
11057 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; | |
67c0d1eb | 11058 | int add_breg_early = 0; |
f5040a92 AO |
11059 | |
11060 | /* This is the large GOT case. If this is a reference to an | |
11061 | external symbol, and there is no constant, we want | |
11062 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
11063 | add $tempreg,$tempreg,$gp | |
11064 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
1abe91b1 | 11065 | or for lca or if tempreg is PIC_CALL_REG |
f5040a92 AO |
11066 | lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) |
11067 | add $tempreg,$tempreg,$gp | |
11068 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) | |
11069 | ||
11070 | If we have a small constant, and this is a reference to | |
11071 | an external symbol, we want | |
11072 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
11073 | add $tempreg,$tempreg,$gp | |
11074 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
11075 | addi $tempreg,$tempreg,<constant> | |
11076 | ||
11077 | If we have a large constant, and this is a reference to | |
11078 | an external symbol, we want | |
11079 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
11080 | addu $tempreg,$tempreg,$gp | |
11081 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
11082 | lui $at,<hiconstant> | |
11083 | addi $at,$at,<loconstant> | |
11084 | add $tempreg,$tempreg,$at | |
11085 | ||
11086 | If we have NewABI, and we know it's a local symbol, we want | |
11087 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
11088 | addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) | |
11089 | otherwise we have to resort to GOT_HI16/GOT_LO16. */ | |
11090 | ||
4d7206a2 | 11091 | relax_start (offset_expr.X_add_symbol); |
f5040a92 | 11092 | |
4d7206a2 | 11093 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
11094 | offset_expr.X_add_number = 0; |
11095 | ||
1abe91b1 MR |
11096 | if (expr1.X_add_number == 0 && breg == 0 |
11097 | && (call || tempreg == PIC_CALL_REG)) | |
f5040a92 AO |
11098 | { |
11099 | lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; | |
11100 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; | |
11101 | } | |
df58fc94 | 11102 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type); |
67c0d1eb | 11103 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 11104 | tempreg, tempreg, mips_gp_register); |
67c0d1eb RS |
11105 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
11106 | tempreg, lw_reloc_type, tempreg); | |
f5040a92 AO |
11107 | |
11108 | if (expr1.X_add_number == 0) | |
4d7206a2 | 11109 | ; |
f5040a92 AO |
11110 | else if (expr1.X_add_number >= -0x8000 |
11111 | && expr1.X_add_number < 0x8000) | |
11112 | { | |
67c0d1eb | 11113 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 11114 | tempreg, tempreg, BFD_RELOC_LO16); |
f5040a92 | 11115 | } |
ecd13cd3 | 11116 | else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000)) |
f5040a92 | 11117 | { |
c0ebe874 RS |
11118 | unsigned int dreg; |
11119 | ||
f5040a92 AO |
11120 | /* If we are going to add in a base register, and the |
11121 | target register and the base register are the same, | |
11122 | then we are using AT as a temporary register. Since | |
11123 | we want to load the constant into AT, we add our | |
11124 | current AT (from the global offset table) and the | |
11125 | register into the register now, and pretend we were | |
11126 | not using a base register. */ | |
c0ebe874 | 11127 | if (breg != op[0]) |
f5040a92 AO |
11128 | dreg = tempreg; |
11129 | else | |
11130 | { | |
9c2799c2 | 11131 | gas_assert (tempreg == AT); |
67c0d1eb | 11132 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
c0ebe874 RS |
11133 | op[0], AT, breg); |
11134 | dreg = op[0]; | |
67c0d1eb | 11135 | add_breg_early = 1; |
f5040a92 AO |
11136 | } |
11137 | ||
f6a22291 | 11138 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 11139 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT); |
f5040a92 | 11140 | |
f5040a92 AO |
11141 | used_at = 1; |
11142 | } | |
11143 | else | |
11144 | as_bad (_("PIC code offset overflow (max 32 signed bits)")); | |
11145 | ||
4d7206a2 | 11146 | relax_switch (); |
f5040a92 | 11147 | offset_expr.X_add_number = expr1.X_add_number; |
67c0d1eb RS |
11148 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
11149 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
11150 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, | |
11151 | tempreg, BFD_RELOC_MIPS_GOT_OFST); | |
11152 | if (add_breg_early) | |
f5040a92 | 11153 | { |
67c0d1eb | 11154 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
c0ebe874 | 11155 | op[0], tempreg, breg); |
f5040a92 | 11156 | breg = 0; |
c0ebe874 | 11157 | tempreg = op[0]; |
f5040a92 | 11158 | } |
4d7206a2 | 11159 | relax_end (); |
f5040a92 | 11160 | } |
252b5132 RH |
11161 | else |
11162 | abort (); | |
11163 | ||
11164 | if (breg != 0) | |
c0ebe874 | 11165 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", op[0], tempreg, breg); |
252b5132 RH |
11166 | break; |
11167 | ||
52b6b6b9 | 11168 | case M_MSGSND: |
df58fc94 | 11169 | gas_assert (!mips_opts.micromips); |
c0ebe874 | 11170 | macro_build (NULL, "c2", "C", (op[0] << 16) | 0x01); |
c7af4273 | 11171 | break; |
52b6b6b9 JM |
11172 | |
11173 | case M_MSGLD: | |
df58fc94 | 11174 | gas_assert (!mips_opts.micromips); |
c8276761 | 11175 | macro_build (NULL, "c2", "C", 0x02); |
c7af4273 | 11176 | break; |
52b6b6b9 JM |
11177 | |
11178 | case M_MSGLD_T: | |
df58fc94 | 11179 | gas_assert (!mips_opts.micromips); |
c0ebe874 | 11180 | macro_build (NULL, "c2", "C", (op[0] << 16) | 0x02); |
c7af4273 | 11181 | break; |
52b6b6b9 JM |
11182 | |
11183 | case M_MSGWAIT: | |
df58fc94 | 11184 | gas_assert (!mips_opts.micromips); |
52b6b6b9 | 11185 | macro_build (NULL, "c2", "C", 3); |
c7af4273 | 11186 | break; |
52b6b6b9 JM |
11187 | |
11188 | case M_MSGWAIT_T: | |
df58fc94 | 11189 | gas_assert (!mips_opts.micromips); |
c0ebe874 | 11190 | macro_build (NULL, "c2", "C", (op[0] << 16) | 0x03); |
c7af4273 | 11191 | break; |
52b6b6b9 | 11192 | |
252b5132 RH |
11193 | case M_J_A: |
11194 | /* The j instruction may not be used in PIC code, since it | |
11195 | requires an absolute address. We convert it to a b | |
11196 | instruction. */ | |
11197 | if (mips_pic == NO_PIC) | |
67c0d1eb | 11198 | macro_build (&offset_expr, "j", "a"); |
252b5132 | 11199 | else |
67c0d1eb | 11200 | macro_build (&offset_expr, "b", "p"); |
8fc2e39e | 11201 | break; |
252b5132 RH |
11202 | |
11203 | /* The jal instructions must be handled as macros because when | |
11204 | generating PIC code they expand to multi-instruction | |
11205 | sequences. Normally they are simple instructions. */ | |
df58fc94 | 11206 | case M_JALS_1: |
c0ebe874 RS |
11207 | op[1] = op[0]; |
11208 | op[0] = RA; | |
df58fc94 RS |
11209 | /* Fall through. */ |
11210 | case M_JALS_2: | |
11211 | gas_assert (mips_opts.micromips); | |
833794fc MR |
11212 | if (mips_opts.insn32) |
11213 | { | |
1661c76c | 11214 | as_bad (_("opcode not supported in the `insn32' mode `%s'"), str); |
833794fc MR |
11215 | break; |
11216 | } | |
df58fc94 RS |
11217 | jals = 1; |
11218 | goto jal; | |
252b5132 | 11219 | case M_JAL_1: |
c0ebe874 RS |
11220 | op[1] = op[0]; |
11221 | op[0] = RA; | |
252b5132 RH |
11222 | /* Fall through. */ |
11223 | case M_JAL_2: | |
df58fc94 | 11224 | jal: |
3e722fb5 | 11225 | if (mips_pic == NO_PIC) |
df58fc94 RS |
11226 | { |
11227 | s = jals ? "jalrs" : "jalr"; | |
e64af278 | 11228 | if (mips_opts.micromips |
833794fc | 11229 | && !mips_opts.insn32 |
c0ebe874 | 11230 | && op[0] == RA |
e64af278 | 11231 | && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) |
c0ebe874 | 11232 | macro_build (NULL, s, "mj", op[1]); |
df58fc94 | 11233 | else |
c0ebe874 | 11234 | macro_build (NULL, s, JALR_FMT, op[0], op[1]); |
df58fc94 | 11235 | } |
0a44bf69 | 11236 | else |
252b5132 | 11237 | { |
df58fc94 RS |
11238 | int cprestore = (mips_pic == SVR4_PIC && !HAVE_NEWABI |
11239 | && mips_cprestore_offset >= 0); | |
11240 | ||
c0ebe874 | 11241 | if (op[1] != PIC_CALL_REG) |
252b5132 | 11242 | as_warn (_("MIPS PIC call to register other than $25")); |
bdaaa2e1 | 11243 | |
833794fc MR |
11244 | s = ((mips_opts.micromips |
11245 | && !mips_opts.insn32 | |
11246 | && (!mips_opts.noreorder || cprestore)) | |
df58fc94 | 11247 | ? "jalrs" : "jalr"); |
e64af278 | 11248 | if (mips_opts.micromips |
833794fc | 11249 | && !mips_opts.insn32 |
c0ebe874 | 11250 | && op[0] == RA |
e64af278 | 11251 | && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) |
c0ebe874 | 11252 | macro_build (NULL, s, "mj", op[1]); |
df58fc94 | 11253 | else |
c0ebe874 | 11254 | macro_build (NULL, s, JALR_FMT, op[0], op[1]); |
0a44bf69 | 11255 | if (mips_pic == SVR4_PIC && !HAVE_NEWABI) |
252b5132 | 11256 | { |
6478892d | 11257 | if (mips_cprestore_offset < 0) |
1661c76c | 11258 | as_warn (_("no .cprestore pseudo-op used in PIC code")); |
6478892d TS |
11259 | else |
11260 | { | |
90ecf173 | 11261 | if (!mips_frame_reg_valid) |
7a621144 | 11262 | { |
1661c76c | 11263 | as_warn (_("no .frame pseudo-op used in PIC code")); |
7a621144 DJ |
11264 | /* Quiet this warning. */ |
11265 | mips_frame_reg_valid = 1; | |
11266 | } | |
90ecf173 | 11267 | if (!mips_cprestore_valid) |
7a621144 | 11268 | { |
1661c76c | 11269 | as_warn (_("no .cprestore pseudo-op used in PIC code")); |
7a621144 DJ |
11270 | /* Quiet this warning. */ |
11271 | mips_cprestore_valid = 1; | |
11272 | } | |
d3fca0b5 MR |
11273 | if (mips_opts.noreorder) |
11274 | macro_build (NULL, "nop", ""); | |
6478892d | 11275 | expr1.X_add_number = mips_cprestore_offset; |
134c0c8b | 11276 | macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN, |
f899b4b8 | 11277 | mips_gp_register, |
256ab948 TS |
11278 | mips_frame_reg, |
11279 | HAVE_64BIT_ADDRESSES); | |
6478892d | 11280 | } |
252b5132 RH |
11281 | } |
11282 | } | |
252b5132 | 11283 | |
8fc2e39e | 11284 | break; |
252b5132 | 11285 | |
df58fc94 RS |
11286 | case M_JALS_A: |
11287 | gas_assert (mips_opts.micromips); | |
833794fc MR |
11288 | if (mips_opts.insn32) |
11289 | { | |
1661c76c | 11290 | as_bad (_("opcode not supported in the `insn32' mode `%s'"), str); |
833794fc MR |
11291 | break; |
11292 | } | |
df58fc94 RS |
11293 | jals = 1; |
11294 | /* Fall through. */ | |
252b5132 RH |
11295 | case M_JAL_A: |
11296 | if (mips_pic == NO_PIC) | |
df58fc94 | 11297 | macro_build (&offset_expr, jals ? "jals" : "jal", "a"); |
252b5132 RH |
11298 | else if (mips_pic == SVR4_PIC) |
11299 | { | |
11300 | /* If this is a reference to an external symbol, and we are | |
11301 | using a small GOT, we want | |
11302 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16) | |
11303 | nop | |
f9419b05 | 11304 | jalr $ra,$25 |
252b5132 RH |
11305 | nop |
11306 | lw $gp,cprestore($sp) | |
11307 | The cprestore value is set using the .cprestore | |
11308 | pseudo-op. If we are using a big GOT, we want | |
11309 | lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16) | |
11310 | addu $25,$25,$gp | |
11311 | lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16) | |
11312 | nop | |
f9419b05 | 11313 | jalr $ra,$25 |
252b5132 RH |
11314 | nop |
11315 | lw $gp,cprestore($sp) | |
11316 | If the symbol is not external, we want | |
11317 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
11318 | nop | |
11319 | addiu $25,$25,<sym> (BFD_RELOC_LO16) | |
f9419b05 | 11320 | jalr $ra,$25 |
252b5132 | 11321 | nop |
438c16b8 | 11322 | lw $gp,cprestore($sp) |
f5040a92 AO |
11323 | |
11324 | For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16 | |
11325 | sequences above, minus nops, unless the symbol is local, | |
11326 | which enables us to use GOT_PAGE/GOT_OFST (big got) or | |
11327 | GOT_DISP. */ | |
438c16b8 | 11328 | if (HAVE_NEWABI) |
252b5132 | 11329 | { |
90ecf173 | 11330 | if (!mips_big_got) |
f5040a92 | 11331 | { |
4d7206a2 | 11332 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
11333 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
11334 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL16, | |
f5040a92 | 11335 | mips_gp_register); |
4d7206a2 | 11336 | relax_switch (); |
67c0d1eb RS |
11337 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
11338 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT_DISP, | |
4d7206a2 RS |
11339 | mips_gp_register); |
11340 | relax_end (); | |
f5040a92 AO |
11341 | } |
11342 | else | |
11343 | { | |
4d7206a2 | 11344 | relax_start (offset_expr.X_add_symbol); |
df58fc94 | 11345 | macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG, |
67c0d1eb RS |
11346 | BFD_RELOC_MIPS_CALL_HI16); |
11347 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG, | |
11348 | PIC_CALL_REG, mips_gp_register); | |
11349 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", | |
11350 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16, | |
11351 | PIC_CALL_REG); | |
4d7206a2 | 11352 | relax_switch (); |
67c0d1eb RS |
11353 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
11354 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT_PAGE, | |
11355 | mips_gp_register); | |
11356 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
11357 | PIC_CALL_REG, PIC_CALL_REG, | |
17a2f251 | 11358 | BFD_RELOC_MIPS_GOT_OFST); |
4d7206a2 | 11359 | relax_end (); |
f5040a92 | 11360 | } |
684022ea | 11361 | |
df58fc94 | 11362 | macro_build_jalr (&offset_expr, 0); |
252b5132 RH |
11363 | } |
11364 | else | |
11365 | { | |
4d7206a2 | 11366 | relax_start (offset_expr.X_add_symbol); |
90ecf173 | 11367 | if (!mips_big_got) |
438c16b8 | 11368 | { |
67c0d1eb RS |
11369 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
11370 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL16, | |
17a2f251 | 11371 | mips_gp_register); |
269137b2 | 11372 | load_delay_nop (); |
4d7206a2 | 11373 | relax_switch (); |
438c16b8 | 11374 | } |
252b5132 | 11375 | else |
252b5132 | 11376 | { |
67c0d1eb RS |
11377 | int gpdelay; |
11378 | ||
11379 | gpdelay = reg_needs_delay (mips_gp_register); | |
df58fc94 | 11380 | macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG, |
67c0d1eb RS |
11381 | BFD_RELOC_MIPS_CALL_HI16); |
11382 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG, | |
11383 | PIC_CALL_REG, mips_gp_register); | |
11384 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", | |
11385 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16, | |
11386 | PIC_CALL_REG); | |
269137b2 | 11387 | load_delay_nop (); |
4d7206a2 | 11388 | relax_switch (); |
67c0d1eb RS |
11389 | if (gpdelay) |
11390 | macro_build (NULL, "nop", ""); | |
252b5132 | 11391 | } |
67c0d1eb RS |
11392 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
11393 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT16, | |
4d7206a2 | 11394 | mips_gp_register); |
269137b2 | 11395 | load_delay_nop (); |
67c0d1eb RS |
11396 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
11397 | PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16); | |
4d7206a2 | 11398 | relax_end (); |
df58fc94 | 11399 | macro_build_jalr (&offset_expr, mips_cprestore_offset >= 0); |
438c16b8 | 11400 | |
6478892d | 11401 | if (mips_cprestore_offset < 0) |
1661c76c | 11402 | as_warn (_("no .cprestore pseudo-op used in PIC code")); |
6478892d TS |
11403 | else |
11404 | { | |
90ecf173 | 11405 | if (!mips_frame_reg_valid) |
7a621144 | 11406 | { |
1661c76c | 11407 | as_warn (_("no .frame pseudo-op used in PIC code")); |
7a621144 DJ |
11408 | /* Quiet this warning. */ |
11409 | mips_frame_reg_valid = 1; | |
11410 | } | |
90ecf173 | 11411 | if (!mips_cprestore_valid) |
7a621144 | 11412 | { |
1661c76c | 11413 | as_warn (_("no .cprestore pseudo-op used in PIC code")); |
7a621144 DJ |
11414 | /* Quiet this warning. */ |
11415 | mips_cprestore_valid = 1; | |
11416 | } | |
6478892d | 11417 | if (mips_opts.noreorder) |
67c0d1eb | 11418 | macro_build (NULL, "nop", ""); |
6478892d | 11419 | expr1.X_add_number = mips_cprestore_offset; |
134c0c8b | 11420 | macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN, |
f899b4b8 | 11421 | mips_gp_register, |
256ab948 TS |
11422 | mips_frame_reg, |
11423 | HAVE_64BIT_ADDRESSES); | |
6478892d | 11424 | } |
252b5132 RH |
11425 | } |
11426 | } | |
0a44bf69 | 11427 | else if (mips_pic == VXWORKS_PIC) |
1661c76c | 11428 | as_bad (_("non-PIC jump used in PIC library")); |
252b5132 RH |
11429 | else |
11430 | abort (); | |
11431 | ||
8fc2e39e | 11432 | break; |
252b5132 | 11433 | |
7f3c4072 | 11434 | case M_LBUE_AB: |
7f3c4072 CM |
11435 | s = "lbue"; |
11436 | fmt = "t,+j(b)"; | |
11437 | offbits = 9; | |
11438 | goto ld_st; | |
11439 | case M_LHUE_AB: | |
7f3c4072 CM |
11440 | s = "lhue"; |
11441 | fmt = "t,+j(b)"; | |
11442 | offbits = 9; | |
11443 | goto ld_st; | |
11444 | case M_LBE_AB: | |
7f3c4072 CM |
11445 | s = "lbe"; |
11446 | fmt = "t,+j(b)"; | |
11447 | offbits = 9; | |
11448 | goto ld_st; | |
11449 | case M_LHE_AB: | |
7f3c4072 CM |
11450 | s = "lhe"; |
11451 | fmt = "t,+j(b)"; | |
11452 | offbits = 9; | |
11453 | goto ld_st; | |
11454 | case M_LLE_AB: | |
7f3c4072 CM |
11455 | s = "lle"; |
11456 | fmt = "t,+j(b)"; | |
11457 | offbits = 9; | |
11458 | goto ld_st; | |
11459 | case M_LWE_AB: | |
7f3c4072 CM |
11460 | s = "lwe"; |
11461 | fmt = "t,+j(b)"; | |
11462 | offbits = 9; | |
11463 | goto ld_st; | |
11464 | case M_LWLE_AB: | |
7f3c4072 CM |
11465 | s = "lwle"; |
11466 | fmt = "t,+j(b)"; | |
11467 | offbits = 9; | |
11468 | goto ld_st; | |
11469 | case M_LWRE_AB: | |
7f3c4072 CM |
11470 | s = "lwre"; |
11471 | fmt = "t,+j(b)"; | |
11472 | offbits = 9; | |
11473 | goto ld_st; | |
11474 | case M_SBE_AB: | |
7f3c4072 CM |
11475 | s = "sbe"; |
11476 | fmt = "t,+j(b)"; | |
11477 | offbits = 9; | |
11478 | goto ld_st; | |
11479 | case M_SCE_AB: | |
7f3c4072 CM |
11480 | s = "sce"; |
11481 | fmt = "t,+j(b)"; | |
11482 | offbits = 9; | |
11483 | goto ld_st; | |
11484 | case M_SHE_AB: | |
7f3c4072 CM |
11485 | s = "she"; |
11486 | fmt = "t,+j(b)"; | |
11487 | offbits = 9; | |
11488 | goto ld_st; | |
11489 | case M_SWE_AB: | |
7f3c4072 CM |
11490 | s = "swe"; |
11491 | fmt = "t,+j(b)"; | |
11492 | offbits = 9; | |
11493 | goto ld_st; | |
11494 | case M_SWLE_AB: | |
7f3c4072 CM |
11495 | s = "swle"; |
11496 | fmt = "t,+j(b)"; | |
11497 | offbits = 9; | |
11498 | goto ld_st; | |
11499 | case M_SWRE_AB: | |
7f3c4072 CM |
11500 | s = "swre"; |
11501 | fmt = "t,+j(b)"; | |
11502 | offbits = 9; | |
11503 | goto ld_st; | |
dec0624d | 11504 | case M_ACLR_AB: |
dec0624d | 11505 | s = "aclr"; |
dec0624d | 11506 | fmt = "\\,~(b)"; |
7f3c4072 | 11507 | offbits = 12; |
dec0624d MR |
11508 | goto ld_st; |
11509 | case M_ASET_AB: | |
dec0624d | 11510 | s = "aset"; |
dec0624d | 11511 | fmt = "\\,~(b)"; |
7f3c4072 | 11512 | offbits = 12; |
dec0624d | 11513 | goto ld_st; |
252b5132 RH |
11514 | case M_LB_AB: |
11515 | s = "lb"; | |
df58fc94 | 11516 | fmt = "t,o(b)"; |
252b5132 RH |
11517 | goto ld; |
11518 | case M_LBU_AB: | |
11519 | s = "lbu"; | |
df58fc94 | 11520 | fmt = "t,o(b)"; |
252b5132 RH |
11521 | goto ld; |
11522 | case M_LH_AB: | |
11523 | s = "lh"; | |
df58fc94 | 11524 | fmt = "t,o(b)"; |
252b5132 RH |
11525 | goto ld; |
11526 | case M_LHU_AB: | |
11527 | s = "lhu"; | |
df58fc94 | 11528 | fmt = "t,o(b)"; |
252b5132 RH |
11529 | goto ld; |
11530 | case M_LW_AB: | |
11531 | s = "lw"; | |
df58fc94 | 11532 | fmt = "t,o(b)"; |
252b5132 RH |
11533 | goto ld; |
11534 | case M_LWC0_AB: | |
df58fc94 | 11535 | gas_assert (!mips_opts.micromips); |
252b5132 | 11536 | s = "lwc0"; |
df58fc94 | 11537 | fmt = "E,o(b)"; |
bdaaa2e1 | 11538 | /* Itbl support may require additional care here. */ |
252b5132 | 11539 | coproc = 1; |
df58fc94 | 11540 | goto ld_st; |
252b5132 RH |
11541 | case M_LWC1_AB: |
11542 | s = "lwc1"; | |
df58fc94 | 11543 | fmt = "T,o(b)"; |
bdaaa2e1 | 11544 | /* Itbl support may require additional care here. */ |
252b5132 | 11545 | coproc = 1; |
df58fc94 | 11546 | goto ld_st; |
252b5132 RH |
11547 | case M_LWC2_AB: |
11548 | s = "lwc2"; | |
df58fc94 | 11549 | fmt = COP12_FMT; |
7361da2c AB |
11550 | offbits = (mips_opts.micromips ? 12 |
11551 | : ISA_IS_R6 (mips_opts.isa) ? 11 | |
11552 | : 16); | |
bdaaa2e1 | 11553 | /* Itbl support may require additional care here. */ |
252b5132 | 11554 | coproc = 1; |
df58fc94 | 11555 | goto ld_st; |
252b5132 | 11556 | case M_LWC3_AB: |
df58fc94 | 11557 | gas_assert (!mips_opts.micromips); |
252b5132 | 11558 | s = "lwc3"; |
df58fc94 | 11559 | fmt = "E,o(b)"; |
bdaaa2e1 | 11560 | /* Itbl support may require additional care here. */ |
252b5132 | 11561 | coproc = 1; |
df58fc94 | 11562 | goto ld_st; |
252b5132 RH |
11563 | case M_LWL_AB: |
11564 | s = "lwl"; | |
df58fc94 | 11565 | fmt = MEM12_FMT; |
7f3c4072 | 11566 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 | 11567 | goto ld_st; |
252b5132 RH |
11568 | case M_LWR_AB: |
11569 | s = "lwr"; | |
df58fc94 | 11570 | fmt = MEM12_FMT; |
7f3c4072 | 11571 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 | 11572 | goto ld_st; |
252b5132 | 11573 | case M_LDC1_AB: |
252b5132 | 11574 | s = "ldc1"; |
df58fc94 | 11575 | fmt = "T,o(b)"; |
bdaaa2e1 | 11576 | /* Itbl support may require additional care here. */ |
252b5132 | 11577 | coproc = 1; |
df58fc94 | 11578 | goto ld_st; |
252b5132 RH |
11579 | case M_LDC2_AB: |
11580 | s = "ldc2"; | |
df58fc94 | 11581 | fmt = COP12_FMT; |
7361da2c AB |
11582 | offbits = (mips_opts.micromips ? 12 |
11583 | : ISA_IS_R6 (mips_opts.isa) ? 11 | |
11584 | : 16); | |
bdaaa2e1 | 11585 | /* Itbl support may require additional care here. */ |
252b5132 | 11586 | coproc = 1; |
df58fc94 | 11587 | goto ld_st; |
c77c0862 | 11588 | case M_LQC2_AB: |
c77c0862 | 11589 | s = "lqc2"; |
14daeee3 | 11590 | fmt = "+7,o(b)"; |
c77c0862 RS |
11591 | /* Itbl support may require additional care here. */ |
11592 | coproc = 1; | |
11593 | goto ld_st; | |
252b5132 RH |
11594 | case M_LDC3_AB: |
11595 | s = "ldc3"; | |
df58fc94 | 11596 | fmt = "E,o(b)"; |
bdaaa2e1 | 11597 | /* Itbl support may require additional care here. */ |
252b5132 | 11598 | coproc = 1; |
df58fc94 | 11599 | goto ld_st; |
252b5132 RH |
11600 | case M_LDL_AB: |
11601 | s = "ldl"; | |
df58fc94 | 11602 | fmt = MEM12_FMT; |
7f3c4072 | 11603 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 | 11604 | goto ld_st; |
252b5132 RH |
11605 | case M_LDR_AB: |
11606 | s = "ldr"; | |
df58fc94 | 11607 | fmt = MEM12_FMT; |
7f3c4072 | 11608 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 | 11609 | goto ld_st; |
252b5132 RH |
11610 | case M_LL_AB: |
11611 | s = "ll"; | |
7361da2c AB |
11612 | fmt = LL_SC_FMT; |
11613 | offbits = (mips_opts.micromips ? 12 | |
11614 | : ISA_IS_R6 (mips_opts.isa) ? 9 | |
11615 | : 16); | |
252b5132 RH |
11616 | goto ld; |
11617 | case M_LLD_AB: | |
11618 | s = "lld"; | |
7361da2c AB |
11619 | fmt = LL_SC_FMT; |
11620 | offbits = (mips_opts.micromips ? 12 | |
11621 | : ISA_IS_R6 (mips_opts.isa) ? 9 | |
11622 | : 16); | |
252b5132 RH |
11623 | goto ld; |
11624 | case M_LWU_AB: | |
11625 | s = "lwu"; | |
df58fc94 | 11626 | fmt = MEM12_FMT; |
7f3c4072 | 11627 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 RS |
11628 | goto ld; |
11629 | case M_LWP_AB: | |
df58fc94 RS |
11630 | gas_assert (mips_opts.micromips); |
11631 | s = "lwp"; | |
11632 | fmt = "t,~(b)"; | |
7f3c4072 | 11633 | offbits = 12; |
df58fc94 RS |
11634 | lp = 1; |
11635 | goto ld; | |
11636 | case M_LDP_AB: | |
df58fc94 RS |
11637 | gas_assert (mips_opts.micromips); |
11638 | s = "ldp"; | |
11639 | fmt = "t,~(b)"; | |
7f3c4072 | 11640 | offbits = 12; |
df58fc94 RS |
11641 | lp = 1; |
11642 | goto ld; | |
11643 | case M_LWM_AB: | |
df58fc94 RS |
11644 | gas_assert (mips_opts.micromips); |
11645 | s = "lwm"; | |
11646 | fmt = "n,~(b)"; | |
7f3c4072 | 11647 | offbits = 12; |
df58fc94 RS |
11648 | goto ld_st; |
11649 | case M_LDM_AB: | |
df58fc94 RS |
11650 | gas_assert (mips_opts.micromips); |
11651 | s = "ldm"; | |
11652 | fmt = "n,~(b)"; | |
7f3c4072 | 11653 | offbits = 12; |
df58fc94 RS |
11654 | goto ld_st; |
11655 | ||
252b5132 | 11656 | ld: |
f19ccbda | 11657 | /* We don't want to use $0 as tempreg. */ |
c0ebe874 | 11658 | if (op[2] == op[0] + lp || op[0] + lp == ZERO) |
df58fc94 | 11659 | goto ld_st; |
252b5132 | 11660 | else |
c0ebe874 | 11661 | tempreg = op[0] + lp; |
df58fc94 RS |
11662 | goto ld_noat; |
11663 | ||
252b5132 RH |
11664 | case M_SB_AB: |
11665 | s = "sb"; | |
df58fc94 RS |
11666 | fmt = "t,o(b)"; |
11667 | goto ld_st; | |
252b5132 RH |
11668 | case M_SH_AB: |
11669 | s = "sh"; | |
df58fc94 RS |
11670 | fmt = "t,o(b)"; |
11671 | goto ld_st; | |
252b5132 RH |
11672 | case M_SW_AB: |
11673 | s = "sw"; | |
df58fc94 RS |
11674 | fmt = "t,o(b)"; |
11675 | goto ld_st; | |
252b5132 | 11676 | case M_SWC0_AB: |
df58fc94 | 11677 | gas_assert (!mips_opts.micromips); |
252b5132 | 11678 | s = "swc0"; |
df58fc94 | 11679 | fmt = "E,o(b)"; |
bdaaa2e1 | 11680 | /* Itbl support may require additional care here. */ |
252b5132 | 11681 | coproc = 1; |
df58fc94 | 11682 | goto ld_st; |
252b5132 RH |
11683 | case M_SWC1_AB: |
11684 | s = "swc1"; | |
df58fc94 | 11685 | fmt = "T,o(b)"; |
bdaaa2e1 | 11686 | /* Itbl support may require additional care here. */ |
252b5132 | 11687 | coproc = 1; |
df58fc94 | 11688 | goto ld_st; |
252b5132 RH |
11689 | case M_SWC2_AB: |
11690 | s = "swc2"; | |
df58fc94 | 11691 | fmt = COP12_FMT; |
7361da2c AB |
11692 | offbits = (mips_opts.micromips ? 12 |
11693 | : ISA_IS_R6 (mips_opts.isa) ? 11 | |
11694 | : 16); | |
bdaaa2e1 | 11695 | /* Itbl support may require additional care here. */ |
252b5132 | 11696 | coproc = 1; |
df58fc94 | 11697 | goto ld_st; |
252b5132 | 11698 | case M_SWC3_AB: |
df58fc94 | 11699 | gas_assert (!mips_opts.micromips); |
252b5132 | 11700 | s = "swc3"; |
df58fc94 | 11701 | fmt = "E,o(b)"; |
bdaaa2e1 | 11702 | /* Itbl support may require additional care here. */ |
252b5132 | 11703 | coproc = 1; |
df58fc94 | 11704 | goto ld_st; |
252b5132 RH |
11705 | case M_SWL_AB: |
11706 | s = "swl"; | |
df58fc94 | 11707 | fmt = MEM12_FMT; |
7f3c4072 | 11708 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 | 11709 | goto ld_st; |
252b5132 RH |
11710 | case M_SWR_AB: |
11711 | s = "swr"; | |
df58fc94 | 11712 | fmt = MEM12_FMT; |
7f3c4072 | 11713 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 | 11714 | goto ld_st; |
252b5132 RH |
11715 | case M_SC_AB: |
11716 | s = "sc"; | |
7361da2c AB |
11717 | fmt = LL_SC_FMT; |
11718 | offbits = (mips_opts.micromips ? 12 | |
11719 | : ISA_IS_R6 (mips_opts.isa) ? 9 | |
11720 | : 16); | |
df58fc94 | 11721 | goto ld_st; |
252b5132 RH |
11722 | case M_SCD_AB: |
11723 | s = "scd"; | |
7361da2c AB |
11724 | fmt = LL_SC_FMT; |
11725 | offbits = (mips_opts.micromips ? 12 | |
11726 | : ISA_IS_R6 (mips_opts.isa) ? 9 | |
11727 | : 16); | |
df58fc94 | 11728 | goto ld_st; |
d43b4baf TS |
11729 | case M_CACHE_AB: |
11730 | s = "cache"; | |
7361da2c AB |
11731 | fmt = (mips_opts.micromips ? "k,~(b)" |
11732 | : ISA_IS_R6 (mips_opts.isa) ? "k,+j(b)" | |
11733 | : "k,o(b)"); | |
11734 | offbits = (mips_opts.micromips ? 12 | |
11735 | : ISA_IS_R6 (mips_opts.isa) ? 9 | |
11736 | : 16); | |
7f3c4072 CM |
11737 | goto ld_st; |
11738 | case M_CACHEE_AB: | |
7f3c4072 CM |
11739 | s = "cachee"; |
11740 | fmt = "k,+j(b)"; | |
11741 | offbits = 9; | |
df58fc94 | 11742 | goto ld_st; |
3eebd5eb MR |
11743 | case M_PREF_AB: |
11744 | s = "pref"; | |
7361da2c AB |
11745 | fmt = (mips_opts.micromips ? "k,~(b)" |
11746 | : ISA_IS_R6 (mips_opts.isa) ? "k,+j(b)" | |
11747 | : "k,o(b)"); | |
11748 | offbits = (mips_opts.micromips ? 12 | |
11749 | : ISA_IS_R6 (mips_opts.isa) ? 9 | |
11750 | : 16); | |
7f3c4072 CM |
11751 | goto ld_st; |
11752 | case M_PREFE_AB: | |
7f3c4072 CM |
11753 | s = "prefe"; |
11754 | fmt = "k,+j(b)"; | |
11755 | offbits = 9; | |
df58fc94 | 11756 | goto ld_st; |
252b5132 | 11757 | case M_SDC1_AB: |
252b5132 | 11758 | s = "sdc1"; |
df58fc94 | 11759 | fmt = "T,o(b)"; |
252b5132 | 11760 | coproc = 1; |
bdaaa2e1 | 11761 | /* Itbl support may require additional care here. */ |
df58fc94 | 11762 | goto ld_st; |
252b5132 RH |
11763 | case M_SDC2_AB: |
11764 | s = "sdc2"; | |
df58fc94 | 11765 | fmt = COP12_FMT; |
7361da2c AB |
11766 | offbits = (mips_opts.micromips ? 12 |
11767 | : ISA_IS_R6 (mips_opts.isa) ? 11 | |
11768 | : 16); | |
c77c0862 RS |
11769 | /* Itbl support may require additional care here. */ |
11770 | coproc = 1; | |
11771 | goto ld_st; | |
11772 | case M_SQC2_AB: | |
c77c0862 | 11773 | s = "sqc2"; |
14daeee3 | 11774 | fmt = "+7,o(b)"; |
bdaaa2e1 | 11775 | /* Itbl support may require additional care here. */ |
252b5132 | 11776 | coproc = 1; |
df58fc94 | 11777 | goto ld_st; |
252b5132 | 11778 | case M_SDC3_AB: |
df58fc94 | 11779 | gas_assert (!mips_opts.micromips); |
252b5132 | 11780 | s = "sdc3"; |
df58fc94 | 11781 | fmt = "E,o(b)"; |
bdaaa2e1 | 11782 | /* Itbl support may require additional care here. */ |
252b5132 | 11783 | coproc = 1; |
df58fc94 | 11784 | goto ld_st; |
252b5132 RH |
11785 | case M_SDL_AB: |
11786 | s = "sdl"; | |
df58fc94 | 11787 | fmt = MEM12_FMT; |
7f3c4072 | 11788 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 | 11789 | goto ld_st; |
252b5132 RH |
11790 | case M_SDR_AB: |
11791 | s = "sdr"; | |
df58fc94 | 11792 | fmt = MEM12_FMT; |
7f3c4072 | 11793 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 RS |
11794 | goto ld_st; |
11795 | case M_SWP_AB: | |
df58fc94 RS |
11796 | gas_assert (mips_opts.micromips); |
11797 | s = "swp"; | |
11798 | fmt = "t,~(b)"; | |
7f3c4072 | 11799 | offbits = 12; |
df58fc94 RS |
11800 | goto ld_st; |
11801 | case M_SDP_AB: | |
df58fc94 RS |
11802 | gas_assert (mips_opts.micromips); |
11803 | s = "sdp"; | |
11804 | fmt = "t,~(b)"; | |
7f3c4072 | 11805 | offbits = 12; |
df58fc94 RS |
11806 | goto ld_st; |
11807 | case M_SWM_AB: | |
df58fc94 RS |
11808 | gas_assert (mips_opts.micromips); |
11809 | s = "swm"; | |
11810 | fmt = "n,~(b)"; | |
7f3c4072 | 11811 | offbits = 12; |
df58fc94 RS |
11812 | goto ld_st; |
11813 | case M_SDM_AB: | |
df58fc94 RS |
11814 | gas_assert (mips_opts.micromips); |
11815 | s = "sdm"; | |
11816 | fmt = "n,~(b)"; | |
7f3c4072 | 11817 | offbits = 12; |
df58fc94 RS |
11818 | |
11819 | ld_st: | |
8fc2e39e | 11820 | tempreg = AT; |
df58fc94 | 11821 | ld_noat: |
c0ebe874 | 11822 | breg = op[2]; |
f2ae14a1 RS |
11823 | if (small_offset_p (0, align, 16)) |
11824 | { | |
11825 | /* The first case exists for M_LD_AB and M_SD_AB, which are | |
11826 | macros for o32 but which should act like normal instructions | |
11827 | otherwise. */ | |
11828 | if (offbits == 16) | |
c0ebe874 | 11829 | macro_build (&offset_expr, s, fmt, op[0], -1, offset_reloc[0], |
f2ae14a1 RS |
11830 | offset_reloc[1], offset_reloc[2], breg); |
11831 | else if (small_offset_p (0, align, offbits)) | |
11832 | { | |
11833 | if (offbits == 0) | |
c0ebe874 | 11834 | macro_build (NULL, s, fmt, op[0], breg); |
f2ae14a1 | 11835 | else |
c0ebe874 | 11836 | macro_build (NULL, s, fmt, op[0], |
c8276761 | 11837 | (int) offset_expr.X_add_number, breg); |
f2ae14a1 RS |
11838 | } |
11839 | else | |
11840 | { | |
11841 | if (tempreg == AT) | |
11842 | used_at = 1; | |
11843 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
11844 | tempreg, breg, -1, offset_reloc[0], | |
11845 | offset_reloc[1], offset_reloc[2]); | |
11846 | if (offbits == 0) | |
c0ebe874 | 11847 | macro_build (NULL, s, fmt, op[0], tempreg); |
f2ae14a1 | 11848 | else |
c0ebe874 | 11849 | macro_build (NULL, s, fmt, op[0], 0, tempreg); |
f2ae14a1 RS |
11850 | } |
11851 | break; | |
11852 | } | |
11853 | ||
11854 | if (tempreg == AT) | |
11855 | used_at = 1; | |
11856 | ||
252b5132 RH |
11857 | if (offset_expr.X_op != O_constant |
11858 | && offset_expr.X_op != O_symbol) | |
11859 | { | |
1661c76c | 11860 | as_bad (_("expression too complex")); |
252b5132 RH |
11861 | offset_expr.X_op = O_constant; |
11862 | } | |
11863 | ||
2051e8c4 MR |
11864 | if (HAVE_32BIT_ADDRESSES |
11865 | && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) | |
55e08f71 NC |
11866 | { |
11867 | char value [32]; | |
11868 | ||
11869 | sprintf_vma (value, offset_expr.X_add_number); | |
1661c76c | 11870 | as_bad (_("number (0x%s) larger than 32 bits"), value); |
55e08f71 | 11871 | } |
2051e8c4 | 11872 | |
252b5132 RH |
11873 | /* A constant expression in PIC code can be handled just as it |
11874 | is in non PIC code. */ | |
aed1a261 RS |
11875 | if (offset_expr.X_op == O_constant) |
11876 | { | |
f2ae14a1 RS |
11877 | expr1.X_add_number = offset_high_part (offset_expr.X_add_number, |
11878 | offbits == 0 ? 16 : offbits); | |
11879 | offset_expr.X_add_number -= expr1.X_add_number; | |
df58fc94 | 11880 | |
f2ae14a1 RS |
11881 | load_register (tempreg, &expr1, HAVE_64BIT_ADDRESSES); |
11882 | if (breg != 0) | |
11883 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
11884 | tempreg, tempreg, breg); | |
7f3c4072 | 11885 | if (offbits == 0) |
dd6a37e7 | 11886 | { |
f2ae14a1 | 11887 | if (offset_expr.X_add_number != 0) |
dd6a37e7 | 11888 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, |
f2ae14a1 | 11889 | "t,r,j", tempreg, tempreg, BFD_RELOC_LO16); |
c0ebe874 | 11890 | macro_build (NULL, s, fmt, op[0], tempreg); |
dd6a37e7 | 11891 | } |
7f3c4072 | 11892 | else if (offbits == 16) |
c0ebe874 | 11893 | macro_build (&offset_expr, s, fmt, op[0], BFD_RELOC_LO16, tempreg); |
df58fc94 | 11894 | else |
c0ebe874 | 11895 | macro_build (NULL, s, fmt, op[0], |
c8276761 | 11896 | (int) offset_expr.X_add_number, tempreg); |
df58fc94 | 11897 | } |
7f3c4072 | 11898 | else if (offbits != 16) |
df58fc94 | 11899 | { |
7f3c4072 | 11900 | /* The offset field is too narrow to be used for a low-part |
2b0f3761 | 11901 | relocation, so load the whole address into the auxiliary |
f2ae14a1 RS |
11902 | register. */ |
11903 | load_address (tempreg, &offset_expr, &used_at); | |
11904 | if (breg != 0) | |
11905 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
11906 | tempreg, tempreg, breg); | |
7f3c4072 | 11907 | if (offbits == 0) |
c0ebe874 | 11908 | macro_build (NULL, s, fmt, op[0], tempreg); |
dd6a37e7 | 11909 | else |
c0ebe874 | 11910 | macro_build (NULL, s, fmt, op[0], 0, tempreg); |
aed1a261 RS |
11911 | } |
11912 | else if (mips_pic == NO_PIC) | |
252b5132 RH |
11913 | { |
11914 | /* If this is a reference to a GP relative symbol, and there | |
11915 | is no base register, we want | |
c0ebe874 | 11916 | <op> op[0],<sym>($gp) (BFD_RELOC_GPREL16) |
252b5132 RH |
11917 | Otherwise, if there is no base register, we want |
11918 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
c0ebe874 | 11919 | <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16) |
252b5132 RH |
11920 | If we have a constant, we need two instructions anyhow, |
11921 | so we always use the latter form. | |
11922 | ||
11923 | If we have a base register, and this is a reference to a | |
11924 | GP relative symbol, we want | |
11925 | addu $tempreg,$breg,$gp | |
c0ebe874 | 11926 | <op> op[0],<sym>($tempreg) (BFD_RELOC_GPREL16) |
252b5132 RH |
11927 | Otherwise we want |
11928 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
11929 | addu $tempreg,$tempreg,$breg | |
c0ebe874 | 11930 | <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16) |
d6bc6245 | 11931 | With a constant we always use the latter case. |
76b3015f | 11932 | |
d6bc6245 TS |
11933 | With 64bit address space and no base register and $at usable, |
11934 | we want | |
11935 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
11936 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
11937 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
11938 | dsll32 $tempreg,0 | |
11939 | daddu $tempreg,$at | |
c0ebe874 | 11940 | <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16) |
d6bc6245 TS |
11941 | If we have a base register, we want |
11942 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
11943 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
11944 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
11945 | daddu $at,$breg | |
11946 | dsll32 $tempreg,0 | |
11947 | daddu $tempreg,$at | |
c0ebe874 | 11948 | <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16) |
d6bc6245 TS |
11949 | |
11950 | Without $at we can't generate the optimal path for superscalar | |
11951 | processors here since this would require two temporary registers. | |
11952 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
11953 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
11954 | dsll $tempreg,16 | |
11955 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
11956 | dsll $tempreg,16 | |
c0ebe874 | 11957 | <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16) |
d6bc6245 TS |
11958 | If we have a base register, we want |
11959 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
11960 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
11961 | dsll $tempreg,16 | |
11962 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
11963 | dsll $tempreg,16 | |
11964 | daddu $tempreg,$tempreg,$breg | |
c0ebe874 | 11965 | <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16) |
6373ee54 | 11966 | |
6caf9ef4 | 11967 | For GP relative symbols in 64bit address space we can use |
aed1a261 RS |
11968 | the same sequence as in 32bit address space. */ |
11969 | if (HAVE_64BIT_SYMBOLS) | |
d6bc6245 | 11970 | { |
aed1a261 | 11971 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 TS |
11972 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
11973 | { | |
11974 | relax_start (offset_expr.X_add_symbol); | |
11975 | if (breg == 0) | |
11976 | { | |
c0ebe874 | 11977 | macro_build (&offset_expr, s, fmt, op[0], |
6caf9ef4 TS |
11978 | BFD_RELOC_GPREL16, mips_gp_register); |
11979 | } | |
11980 | else | |
11981 | { | |
11982 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
11983 | tempreg, breg, mips_gp_register); | |
c0ebe874 | 11984 | macro_build (&offset_expr, s, fmt, op[0], |
6caf9ef4 TS |
11985 | BFD_RELOC_GPREL16, tempreg); |
11986 | } | |
11987 | relax_switch (); | |
11988 | } | |
d6bc6245 | 11989 | |
741fe287 | 11990 | if (used_at == 0 && mips_opts.at) |
d6bc6245 | 11991 | { |
df58fc94 | 11992 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, |
67c0d1eb | 11993 | BFD_RELOC_MIPS_HIGHEST); |
df58fc94 | 11994 | macro_build (&offset_expr, "lui", LUI_FMT, AT, |
67c0d1eb RS |
11995 | BFD_RELOC_HI16_S); |
11996 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
11997 | tempreg, BFD_RELOC_MIPS_HIGHER); | |
d6bc6245 | 11998 | if (breg != 0) |
67c0d1eb | 11999 | macro_build (NULL, "daddu", "d,v,t", AT, AT, breg); |
df58fc94 | 12000 | macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0); |
67c0d1eb | 12001 | macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT); |
c0ebe874 | 12002 | macro_build (&offset_expr, s, fmt, op[0], BFD_RELOC_LO16, |
67c0d1eb | 12003 | tempreg); |
d6bc6245 TS |
12004 | used_at = 1; |
12005 | } | |
12006 | else | |
12007 | { | |
df58fc94 | 12008 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, |
67c0d1eb RS |
12009 | BFD_RELOC_MIPS_HIGHEST); |
12010 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
12011 | tempreg, BFD_RELOC_MIPS_HIGHER); | |
df58fc94 | 12012 | macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16); |
67c0d1eb RS |
12013 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, |
12014 | tempreg, BFD_RELOC_HI16_S); | |
df58fc94 | 12015 | macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16); |
d6bc6245 | 12016 | if (breg != 0) |
67c0d1eb | 12017 | macro_build (NULL, "daddu", "d,v,t", |
17a2f251 | 12018 | tempreg, tempreg, breg); |
c0ebe874 | 12019 | macro_build (&offset_expr, s, fmt, op[0], |
17a2f251 | 12020 | BFD_RELOC_LO16, tempreg); |
d6bc6245 | 12021 | } |
6caf9ef4 TS |
12022 | |
12023 | if (mips_relax.sequence) | |
12024 | relax_end (); | |
8fc2e39e | 12025 | break; |
d6bc6245 | 12026 | } |
256ab948 | 12027 | |
252b5132 RH |
12028 | if (breg == 0) |
12029 | { | |
67c0d1eb | 12030 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 12031 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 12032 | { |
4d7206a2 | 12033 | relax_start (offset_expr.X_add_symbol); |
c0ebe874 | 12034 | macro_build (&offset_expr, s, fmt, op[0], BFD_RELOC_GPREL16, |
67c0d1eb | 12035 | mips_gp_register); |
4d7206a2 | 12036 | relax_switch (); |
252b5132 | 12037 | } |
67c0d1eb | 12038 | macro_build_lui (&offset_expr, tempreg); |
c0ebe874 | 12039 | macro_build (&offset_expr, s, fmt, op[0], |
17a2f251 | 12040 | BFD_RELOC_LO16, tempreg); |
4d7206a2 RS |
12041 | if (mips_relax.sequence) |
12042 | relax_end (); | |
252b5132 RH |
12043 | } |
12044 | else | |
12045 | { | |
67c0d1eb | 12046 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 12047 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 12048 | { |
4d7206a2 | 12049 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 12050 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 12051 | tempreg, breg, mips_gp_register); |
c0ebe874 | 12052 | macro_build (&offset_expr, s, fmt, op[0], |
17a2f251 | 12053 | BFD_RELOC_GPREL16, tempreg); |
4d7206a2 | 12054 | relax_switch (); |
252b5132 | 12055 | } |
67c0d1eb RS |
12056 | macro_build_lui (&offset_expr, tempreg); |
12057 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 12058 | tempreg, tempreg, breg); |
c0ebe874 | 12059 | macro_build (&offset_expr, s, fmt, op[0], |
17a2f251 | 12060 | BFD_RELOC_LO16, tempreg); |
4d7206a2 RS |
12061 | if (mips_relax.sequence) |
12062 | relax_end (); | |
252b5132 RH |
12063 | } |
12064 | } | |
0a44bf69 | 12065 | else if (!mips_big_got) |
252b5132 | 12066 | { |
ed6fb7bd | 12067 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
f9419b05 | 12068 | |
252b5132 RH |
12069 | /* If this is a reference to an external symbol, we want |
12070 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
12071 | nop | |
c0ebe874 | 12072 | <op> op[0],0($tempreg) |
252b5132 RH |
12073 | Otherwise we want |
12074 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
12075 | nop | |
12076 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
c0ebe874 | 12077 | <op> op[0],0($tempreg) |
f5040a92 AO |
12078 | |
12079 | For NewABI, we want | |
12080 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
c0ebe874 | 12081 | <op> op[0],<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) |
f5040a92 | 12082 | |
252b5132 RH |
12083 | If there is a base register, we add it to $tempreg before |
12084 | the <op>. If there is a constant, we stick it in the | |
12085 | <op> instruction. We don't handle constants larger than | |
12086 | 16 bits, because we have no way to load the upper 16 bits | |
12087 | (actually, we could handle them for the subset of cases | |
12088 | in which we are not using $at). */ | |
9c2799c2 | 12089 | gas_assert (offset_expr.X_op == O_symbol); |
f5040a92 AO |
12090 | if (HAVE_NEWABI) |
12091 | { | |
67c0d1eb RS |
12092 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
12093 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
f5040a92 | 12094 | if (breg != 0) |
67c0d1eb | 12095 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 12096 | tempreg, tempreg, breg); |
c0ebe874 | 12097 | macro_build (&offset_expr, s, fmt, op[0], |
17a2f251 | 12098 | BFD_RELOC_MIPS_GOT_OFST, tempreg); |
f5040a92 AO |
12099 | break; |
12100 | } | |
252b5132 RH |
12101 | expr1.X_add_number = offset_expr.X_add_number; |
12102 | offset_expr.X_add_number = 0; | |
12103 | if (expr1.X_add_number < -0x8000 | |
12104 | || expr1.X_add_number >= 0x8000) | |
12105 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb RS |
12106 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
12107 | lw_reloc_type, mips_gp_register); | |
269137b2 | 12108 | load_delay_nop (); |
4d7206a2 RS |
12109 | relax_start (offset_expr.X_add_symbol); |
12110 | relax_switch (); | |
67c0d1eb RS |
12111 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, |
12112 | tempreg, BFD_RELOC_LO16); | |
4d7206a2 | 12113 | relax_end (); |
252b5132 | 12114 | if (breg != 0) |
67c0d1eb | 12115 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 12116 | tempreg, tempreg, breg); |
c0ebe874 | 12117 | macro_build (&expr1, s, fmt, op[0], BFD_RELOC_LO16, tempreg); |
252b5132 | 12118 | } |
0a44bf69 | 12119 | else if (mips_big_got && !HAVE_NEWABI) |
252b5132 | 12120 | { |
67c0d1eb | 12121 | int gpdelay; |
252b5132 RH |
12122 | |
12123 | /* If this is a reference to an external symbol, we want | |
12124 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
12125 | addu $tempreg,$tempreg,$gp | |
12126 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
c0ebe874 | 12127 | <op> op[0],0($tempreg) |
252b5132 RH |
12128 | Otherwise we want |
12129 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
12130 | nop | |
12131 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
c0ebe874 | 12132 | <op> op[0],0($tempreg) |
252b5132 RH |
12133 | If there is a base register, we add it to $tempreg before |
12134 | the <op>. If there is a constant, we stick it in the | |
12135 | <op> instruction. We don't handle constants larger than | |
12136 | 16 bits, because we have no way to load the upper 16 bits | |
12137 | (actually, we could handle them for the subset of cases | |
f5040a92 | 12138 | in which we are not using $at). */ |
9c2799c2 | 12139 | gas_assert (offset_expr.X_op == O_symbol); |
252b5132 RH |
12140 | expr1.X_add_number = offset_expr.X_add_number; |
12141 | offset_expr.X_add_number = 0; | |
12142 | if (expr1.X_add_number < -0x8000 | |
12143 | || expr1.X_add_number >= 0x8000) | |
12144 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 12145 | gpdelay = reg_needs_delay (mips_gp_register); |
4d7206a2 | 12146 | relax_start (offset_expr.X_add_symbol); |
df58fc94 | 12147 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, |
17a2f251 | 12148 | BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
12149 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, |
12150 | mips_gp_register); | |
12151 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
12152 | BFD_RELOC_MIPS_GOT_LO16, tempreg); | |
4d7206a2 | 12153 | relax_switch (); |
67c0d1eb RS |
12154 | if (gpdelay) |
12155 | macro_build (NULL, "nop", ""); | |
12156 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
12157 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 12158 | load_delay_nop (); |
67c0d1eb RS |
12159 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, |
12160 | tempreg, BFD_RELOC_LO16); | |
4d7206a2 RS |
12161 | relax_end (); |
12162 | ||
252b5132 | 12163 | if (breg != 0) |
67c0d1eb | 12164 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 12165 | tempreg, tempreg, breg); |
c0ebe874 | 12166 | macro_build (&expr1, s, fmt, op[0], BFD_RELOC_LO16, tempreg); |
252b5132 | 12167 | } |
0a44bf69 | 12168 | else if (mips_big_got && HAVE_NEWABI) |
f5040a92 | 12169 | { |
f5040a92 AO |
12170 | /* If this is a reference to an external symbol, we want |
12171 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
12172 | add $tempreg,$tempreg,$gp | |
12173 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
c0ebe874 | 12174 | <op> op[0],<ofst>($tempreg) |
f5040a92 AO |
12175 | Otherwise, for local symbols, we want: |
12176 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
c0ebe874 | 12177 | <op> op[0],<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */ |
9c2799c2 | 12178 | gas_assert (offset_expr.X_op == O_symbol); |
4d7206a2 | 12179 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
12180 | offset_expr.X_add_number = 0; |
12181 | if (expr1.X_add_number < -0x8000 | |
12182 | || expr1.X_add_number >= 0x8000) | |
12183 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4d7206a2 | 12184 | relax_start (offset_expr.X_add_symbol); |
df58fc94 | 12185 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, |
17a2f251 | 12186 | BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
12187 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, |
12188 | mips_gp_register); | |
12189 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
12190 | BFD_RELOC_MIPS_GOT_LO16, tempreg); | |
f5040a92 | 12191 | if (breg != 0) |
67c0d1eb | 12192 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 12193 | tempreg, tempreg, breg); |
c0ebe874 | 12194 | macro_build (&expr1, s, fmt, op[0], BFD_RELOC_LO16, tempreg); |
684022ea | 12195 | |
4d7206a2 | 12196 | relax_switch (); |
f5040a92 | 12197 | offset_expr.X_add_number = expr1.X_add_number; |
67c0d1eb RS |
12198 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
12199 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
f5040a92 | 12200 | if (breg != 0) |
67c0d1eb | 12201 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 12202 | tempreg, tempreg, breg); |
c0ebe874 | 12203 | macro_build (&offset_expr, s, fmt, op[0], |
17a2f251 | 12204 | BFD_RELOC_MIPS_GOT_OFST, tempreg); |
4d7206a2 | 12205 | relax_end (); |
f5040a92 | 12206 | } |
252b5132 RH |
12207 | else |
12208 | abort (); | |
12209 | ||
252b5132 RH |
12210 | break; |
12211 | ||
833794fc MR |
12212 | case M_JRADDIUSP: |
12213 | gas_assert (mips_opts.micromips); | |
12214 | gas_assert (mips_opts.insn32); | |
12215 | start_noreorder (); | |
12216 | macro_build (NULL, "jr", "s", RA); | |
c0ebe874 | 12217 | expr1.X_add_number = op[0] << 2; |
833794fc MR |
12218 | macro_build (&expr1, "addiu", "t,r,j", SP, SP, BFD_RELOC_LO16); |
12219 | end_noreorder (); | |
12220 | break; | |
12221 | ||
12222 | case M_JRC: | |
12223 | gas_assert (mips_opts.micromips); | |
12224 | gas_assert (mips_opts.insn32); | |
c0ebe874 | 12225 | macro_build (NULL, "jr", "s", op[0]); |
833794fc MR |
12226 | if (mips_opts.noreorder) |
12227 | macro_build (NULL, "nop", ""); | |
12228 | break; | |
12229 | ||
252b5132 RH |
12230 | case M_LI: |
12231 | case M_LI_S: | |
c0ebe874 | 12232 | load_register (op[0], &imm_expr, 0); |
8fc2e39e | 12233 | break; |
252b5132 RH |
12234 | |
12235 | case M_DLI: | |
c0ebe874 | 12236 | load_register (op[0], &imm_expr, 1); |
8fc2e39e | 12237 | break; |
252b5132 RH |
12238 | |
12239 | case M_LI_SS: | |
12240 | if (imm_expr.X_op == O_constant) | |
12241 | { | |
8fc2e39e | 12242 | used_at = 1; |
67c0d1eb | 12243 | load_register (AT, &imm_expr, 0); |
c0ebe874 | 12244 | macro_build (NULL, "mtc1", "t,G", AT, op[0]); |
252b5132 RH |
12245 | break; |
12246 | } | |
12247 | else | |
12248 | { | |
b0e6f033 RS |
12249 | gas_assert (imm_expr.X_op == O_absent |
12250 | && offset_expr.X_op == O_symbol | |
90ecf173 MR |
12251 | && strcmp (segment_name (S_GET_SEGMENT |
12252 | (offset_expr.X_add_symbol)), | |
12253 | ".lit4") == 0 | |
12254 | && offset_expr.X_add_number == 0); | |
c0ebe874 | 12255 | macro_build (&offset_expr, "lwc1", "T,o(b)", op[0], |
17a2f251 | 12256 | BFD_RELOC_MIPS_LITERAL, mips_gp_register); |
8fc2e39e | 12257 | break; |
252b5132 RH |
12258 | } |
12259 | ||
12260 | case M_LI_D: | |
ca4e0257 RS |
12261 | /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits |
12262 | wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high | |
12263 | order 32 bits of the value and the low order 32 bits are either | |
12264 | zero or in OFFSET_EXPR. */ | |
b0e6f033 | 12265 | if (imm_expr.X_op == O_constant) |
252b5132 | 12266 | { |
bad1aba3 | 12267 | if (GPR_SIZE == 64) |
c0ebe874 | 12268 | load_register (op[0], &imm_expr, 1); |
252b5132 RH |
12269 | else |
12270 | { | |
12271 | int hreg, lreg; | |
12272 | ||
12273 | if (target_big_endian) | |
12274 | { | |
c0ebe874 RS |
12275 | hreg = op[0]; |
12276 | lreg = op[0] + 1; | |
252b5132 RH |
12277 | } |
12278 | else | |
12279 | { | |
c0ebe874 RS |
12280 | hreg = op[0] + 1; |
12281 | lreg = op[0]; | |
252b5132 RH |
12282 | } |
12283 | ||
12284 | if (hreg <= 31) | |
67c0d1eb | 12285 | load_register (hreg, &imm_expr, 0); |
252b5132 RH |
12286 | if (lreg <= 31) |
12287 | { | |
12288 | if (offset_expr.X_op == O_absent) | |
67c0d1eb | 12289 | move_register (lreg, 0); |
252b5132 RH |
12290 | else |
12291 | { | |
9c2799c2 | 12292 | gas_assert (offset_expr.X_op == O_constant); |
67c0d1eb | 12293 | load_register (lreg, &offset_expr, 0); |
252b5132 RH |
12294 | } |
12295 | } | |
12296 | } | |
8fc2e39e | 12297 | break; |
252b5132 | 12298 | } |
b0e6f033 | 12299 | gas_assert (imm_expr.X_op == O_absent); |
252b5132 RH |
12300 | |
12301 | /* We know that sym is in the .rdata section. First we get the | |
12302 | upper 16 bits of the address. */ | |
12303 | if (mips_pic == NO_PIC) | |
12304 | { | |
67c0d1eb | 12305 | macro_build_lui (&offset_expr, AT); |
8fc2e39e | 12306 | used_at = 1; |
252b5132 | 12307 | } |
0a44bf69 | 12308 | else |
252b5132 | 12309 | { |
67c0d1eb RS |
12310 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, |
12311 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
8fc2e39e | 12312 | used_at = 1; |
252b5132 | 12313 | } |
bdaaa2e1 | 12314 | |
252b5132 | 12315 | /* Now we load the register(s). */ |
bad1aba3 | 12316 | if (GPR_SIZE == 64) |
8fc2e39e TS |
12317 | { |
12318 | used_at = 1; | |
c0ebe874 RS |
12319 | macro_build (&offset_expr, "ld", "t,o(b)", op[0], |
12320 | BFD_RELOC_LO16, AT); | |
8fc2e39e | 12321 | } |
252b5132 RH |
12322 | else |
12323 | { | |
8fc2e39e | 12324 | used_at = 1; |
c0ebe874 RS |
12325 | macro_build (&offset_expr, "lw", "t,o(b)", op[0], |
12326 | BFD_RELOC_LO16, AT); | |
12327 | if (op[0] != RA) | |
252b5132 RH |
12328 | { |
12329 | /* FIXME: How in the world do we deal with the possible | |
12330 | overflow here? */ | |
12331 | offset_expr.X_add_number += 4; | |
67c0d1eb | 12332 | macro_build (&offset_expr, "lw", "t,o(b)", |
c0ebe874 | 12333 | op[0] + 1, BFD_RELOC_LO16, AT); |
252b5132 RH |
12334 | } |
12335 | } | |
252b5132 RH |
12336 | break; |
12337 | ||
12338 | case M_LI_DD: | |
ca4e0257 RS |
12339 | /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits |
12340 | wide, IMM_EXPR is the entire value and the GPRs are known to be 64 | |
12341 | bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of | |
12342 | the value and the low order 32 bits are either zero or in | |
12343 | OFFSET_EXPR. */ | |
b0e6f033 | 12344 | if (imm_expr.X_op == O_constant) |
252b5132 | 12345 | { |
8fc2e39e | 12346 | used_at = 1; |
bad1aba3 | 12347 | load_register (AT, &imm_expr, FPR_SIZE == 64); |
351cdf24 MF |
12348 | if (FPR_SIZE == 64 && GPR_SIZE == 64) |
12349 | macro_build (NULL, "dmtc1", "t,S", AT, op[0]); | |
252b5132 RH |
12350 | else |
12351 | { | |
351cdf24 MF |
12352 | if (ISA_HAS_MXHC1 (mips_opts.isa)) |
12353 | macro_build (NULL, "mthc1", "t,G", AT, op[0]); | |
12354 | else if (FPR_SIZE != 32) | |
12355 | as_bad (_("Unable to generate `%s' compliant code " | |
12356 | "without mthc1"), | |
12357 | (FPR_SIZE == 64) ? "fp64" : "fpxx"); | |
12358 | else | |
12359 | macro_build (NULL, "mtc1", "t,G", AT, op[0] + 1); | |
252b5132 | 12360 | if (offset_expr.X_op == O_absent) |
c0ebe874 | 12361 | macro_build (NULL, "mtc1", "t,G", 0, op[0]); |
252b5132 RH |
12362 | else |
12363 | { | |
9c2799c2 | 12364 | gas_assert (offset_expr.X_op == O_constant); |
67c0d1eb | 12365 | load_register (AT, &offset_expr, 0); |
c0ebe874 | 12366 | macro_build (NULL, "mtc1", "t,G", AT, op[0]); |
252b5132 RH |
12367 | } |
12368 | } | |
12369 | break; | |
12370 | } | |
12371 | ||
b0e6f033 RS |
12372 | gas_assert (imm_expr.X_op == O_absent |
12373 | && offset_expr.X_op == O_symbol | |
90ecf173 | 12374 | && offset_expr.X_add_number == 0); |
252b5132 RH |
12375 | s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol)); |
12376 | if (strcmp (s, ".lit8") == 0) | |
134c0c8b MR |
12377 | { |
12378 | op[2] = mips_gp_register; | |
f2ae14a1 RS |
12379 | offset_reloc[0] = BFD_RELOC_MIPS_LITERAL; |
12380 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
12381 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
12382 | } |
12383 | else | |
12384 | { | |
9c2799c2 | 12385 | gas_assert (strcmp (s, RDATA_SECTION_NAME) == 0); |
8fc2e39e | 12386 | used_at = 1; |
0a44bf69 | 12387 | if (mips_pic != NO_PIC) |
67c0d1eb RS |
12388 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, |
12389 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
252b5132 RH |
12390 | else |
12391 | { | |
12392 | /* FIXME: This won't work for a 64 bit address. */ | |
67c0d1eb | 12393 | macro_build_lui (&offset_expr, AT); |
252b5132 | 12394 | } |
bdaaa2e1 | 12395 | |
c0ebe874 | 12396 | op[2] = AT; |
f2ae14a1 RS |
12397 | offset_reloc[0] = BFD_RELOC_LO16; |
12398 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
12399 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
134c0c8b | 12400 | } |
f2ae14a1 RS |
12401 | align = 8; |
12402 | /* Fall through */ | |
c4a68bea | 12403 | |
252b5132 RH |
12404 | case M_L_DAB: |
12405 | /* | |
12406 | * The MIPS assembler seems to check for X_add_number not | |
12407 | * being double aligned and generating: | |
12408 | * lui at,%hi(foo+1) | |
12409 | * addu at,at,v1 | |
12410 | * addiu at,at,%lo(foo+1) | |
12411 | * lwc1 f2,0(at) | |
12412 | * lwc1 f3,4(at) | |
12413 | * But, the resulting address is the same after relocation so why | |
12414 | * generate the extra instruction? | |
12415 | */ | |
bdaaa2e1 | 12416 | /* Itbl support may require additional care here. */ |
252b5132 | 12417 | coproc = 1; |
df58fc94 | 12418 | fmt = "T,o(b)"; |
0aa27725 | 12419 | if (CPU_HAS_LDC1_SDC1 (mips_opts.arch)) |
252b5132 RH |
12420 | { |
12421 | s = "ldc1"; | |
df58fc94 | 12422 | goto ld_st; |
252b5132 | 12423 | } |
252b5132 | 12424 | s = "lwc1"; |
252b5132 RH |
12425 | goto ldd_std; |
12426 | ||
12427 | case M_S_DAB: | |
df58fc94 RS |
12428 | gas_assert (!mips_opts.micromips); |
12429 | /* Itbl support may require additional care here. */ | |
12430 | coproc = 1; | |
12431 | fmt = "T,o(b)"; | |
0aa27725 | 12432 | if (CPU_HAS_LDC1_SDC1 (mips_opts.arch)) |
252b5132 RH |
12433 | { |
12434 | s = "sdc1"; | |
df58fc94 | 12435 | goto ld_st; |
252b5132 | 12436 | } |
252b5132 | 12437 | s = "swc1"; |
252b5132 RH |
12438 | goto ldd_std; |
12439 | ||
e407c74b NC |
12440 | case M_LQ_AB: |
12441 | fmt = "t,o(b)"; | |
12442 | s = "lq"; | |
12443 | goto ld; | |
12444 | ||
12445 | case M_SQ_AB: | |
12446 | fmt = "t,o(b)"; | |
12447 | s = "sq"; | |
12448 | goto ld_st; | |
12449 | ||
252b5132 | 12450 | case M_LD_AB: |
df58fc94 | 12451 | fmt = "t,o(b)"; |
bad1aba3 | 12452 | if (GPR_SIZE == 64) |
252b5132 RH |
12453 | { |
12454 | s = "ld"; | |
12455 | goto ld; | |
12456 | } | |
252b5132 | 12457 | s = "lw"; |
252b5132 RH |
12458 | goto ldd_std; |
12459 | ||
12460 | case M_SD_AB: | |
df58fc94 | 12461 | fmt = "t,o(b)"; |
bad1aba3 | 12462 | if (GPR_SIZE == 64) |
252b5132 RH |
12463 | { |
12464 | s = "sd"; | |
df58fc94 | 12465 | goto ld_st; |
252b5132 | 12466 | } |
252b5132 | 12467 | s = "sw"; |
252b5132 RH |
12468 | |
12469 | ldd_std: | |
f2ae14a1 RS |
12470 | /* Even on a big endian machine $fn comes before $fn+1. We have |
12471 | to adjust when loading from memory. We set coproc if we must | |
12472 | load $fn+1 first. */ | |
12473 | /* Itbl support may require additional care here. */ | |
12474 | if (!target_big_endian) | |
12475 | coproc = 0; | |
12476 | ||
c0ebe874 | 12477 | breg = op[2]; |
f2ae14a1 RS |
12478 | if (small_offset_p (0, align, 16)) |
12479 | { | |
12480 | ep = &offset_expr; | |
12481 | if (!small_offset_p (4, align, 16)) | |
12482 | { | |
12483 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", AT, breg, | |
12484 | -1, offset_reloc[0], offset_reloc[1], | |
12485 | offset_reloc[2]); | |
12486 | expr1.X_add_number = 0; | |
12487 | ep = &expr1; | |
12488 | breg = AT; | |
12489 | used_at = 1; | |
12490 | offset_reloc[0] = BFD_RELOC_LO16; | |
12491 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
12492 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
12493 | } | |
c0ebe874 | 12494 | if (strcmp (s, "lw") == 0 && op[0] == breg) |
f2ae14a1 RS |
12495 | { |
12496 | ep->X_add_number += 4; | |
c0ebe874 | 12497 | macro_build (ep, s, fmt, op[0] + 1, -1, offset_reloc[0], |
f2ae14a1 RS |
12498 | offset_reloc[1], offset_reloc[2], breg); |
12499 | ep->X_add_number -= 4; | |
c0ebe874 | 12500 | macro_build (ep, s, fmt, op[0], -1, offset_reloc[0], |
f2ae14a1 RS |
12501 | offset_reloc[1], offset_reloc[2], breg); |
12502 | } | |
12503 | else | |
12504 | { | |
c0ebe874 | 12505 | macro_build (ep, s, fmt, coproc ? op[0] + 1 : op[0], -1, |
f2ae14a1 RS |
12506 | offset_reloc[0], offset_reloc[1], offset_reloc[2], |
12507 | breg); | |
12508 | ep->X_add_number += 4; | |
c0ebe874 | 12509 | macro_build (ep, s, fmt, coproc ? op[0] : op[0] + 1, -1, |
f2ae14a1 RS |
12510 | offset_reloc[0], offset_reloc[1], offset_reloc[2], |
12511 | breg); | |
12512 | } | |
12513 | break; | |
12514 | } | |
12515 | ||
252b5132 RH |
12516 | if (offset_expr.X_op != O_symbol |
12517 | && offset_expr.X_op != O_constant) | |
12518 | { | |
1661c76c | 12519 | as_bad (_("expression too complex")); |
252b5132 RH |
12520 | offset_expr.X_op = O_constant; |
12521 | } | |
12522 | ||
2051e8c4 MR |
12523 | if (HAVE_32BIT_ADDRESSES |
12524 | && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) | |
55e08f71 NC |
12525 | { |
12526 | char value [32]; | |
12527 | ||
12528 | sprintf_vma (value, offset_expr.X_add_number); | |
1661c76c | 12529 | as_bad (_("number (0x%s) larger than 32 bits"), value); |
55e08f71 | 12530 | } |
2051e8c4 | 12531 | |
90ecf173 | 12532 | if (mips_pic == NO_PIC || offset_expr.X_op == O_constant) |
252b5132 RH |
12533 | { |
12534 | /* If this is a reference to a GP relative symbol, we want | |
c0ebe874 RS |
12535 | <op> op[0],<sym>($gp) (BFD_RELOC_GPREL16) |
12536 | <op> op[0]+1,<sym>+4($gp) (BFD_RELOC_GPREL16) | |
252b5132 RH |
12537 | If we have a base register, we use this |
12538 | addu $at,$breg,$gp | |
c0ebe874 RS |
12539 | <op> op[0],<sym>($at) (BFD_RELOC_GPREL16) |
12540 | <op> op[0]+1,<sym>+4($at) (BFD_RELOC_GPREL16) | |
252b5132 RH |
12541 | If this is not a GP relative symbol, we want |
12542 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
c0ebe874 RS |
12543 | <op> op[0],<sym>($at) (BFD_RELOC_LO16) |
12544 | <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16) | |
252b5132 RH |
12545 | If there is a base register, we add it to $at after the |
12546 | lui instruction. If there is a constant, we always use | |
12547 | the last case. */ | |
39a59cf8 MR |
12548 | if (offset_expr.X_op == O_symbol |
12549 | && (valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET | |
6caf9ef4 | 12550 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 12551 | { |
4d7206a2 | 12552 | relax_start (offset_expr.X_add_symbol); |
252b5132 RH |
12553 | if (breg == 0) |
12554 | { | |
c9914766 | 12555 | tempreg = mips_gp_register; |
252b5132 RH |
12556 | } |
12557 | else | |
12558 | { | |
67c0d1eb | 12559 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 12560 | AT, breg, mips_gp_register); |
252b5132 | 12561 | tempreg = AT; |
252b5132 RH |
12562 | used_at = 1; |
12563 | } | |
12564 | ||
beae10d5 | 12565 | /* Itbl support may require additional care here. */ |
c0ebe874 | 12566 | macro_build (&offset_expr, s, fmt, coproc ? op[0] + 1 : op[0], |
17a2f251 | 12567 | BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
12568 | offset_expr.X_add_number += 4; |
12569 | ||
12570 | /* Set mips_optimize to 2 to avoid inserting an | |
12571 | undesired nop. */ | |
12572 | hold_mips_optimize = mips_optimize; | |
12573 | mips_optimize = 2; | |
beae10d5 | 12574 | /* Itbl support may require additional care here. */ |
c0ebe874 | 12575 | macro_build (&offset_expr, s, fmt, coproc ? op[0] : op[0] + 1, |
17a2f251 | 12576 | BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
12577 | mips_optimize = hold_mips_optimize; |
12578 | ||
4d7206a2 | 12579 | relax_switch (); |
252b5132 | 12580 | |
0970e49e | 12581 | offset_expr.X_add_number -= 4; |
252b5132 | 12582 | } |
8fc2e39e | 12583 | used_at = 1; |
f2ae14a1 RS |
12584 | if (offset_high_part (offset_expr.X_add_number, 16) |
12585 | != offset_high_part (offset_expr.X_add_number + 4, 16)) | |
12586 | { | |
12587 | load_address (AT, &offset_expr, &used_at); | |
12588 | offset_expr.X_op = O_constant; | |
12589 | offset_expr.X_add_number = 0; | |
12590 | } | |
12591 | else | |
12592 | macro_build_lui (&offset_expr, AT); | |
252b5132 | 12593 | if (breg != 0) |
67c0d1eb | 12594 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 12595 | /* Itbl support may require additional care here. */ |
c0ebe874 | 12596 | macro_build (&offset_expr, s, fmt, coproc ? op[0] + 1 : op[0], |
17a2f251 | 12597 | BFD_RELOC_LO16, AT); |
252b5132 RH |
12598 | /* FIXME: How do we handle overflow here? */ |
12599 | offset_expr.X_add_number += 4; | |
beae10d5 | 12600 | /* Itbl support may require additional care here. */ |
c0ebe874 | 12601 | macro_build (&offset_expr, s, fmt, coproc ? op[0] : op[0] + 1, |
17a2f251 | 12602 | BFD_RELOC_LO16, AT); |
4d7206a2 RS |
12603 | if (mips_relax.sequence) |
12604 | relax_end (); | |
bdaaa2e1 | 12605 | } |
0a44bf69 | 12606 | else if (!mips_big_got) |
252b5132 | 12607 | { |
252b5132 RH |
12608 | /* If this is a reference to an external symbol, we want |
12609 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
12610 | nop | |
c0ebe874 RS |
12611 | <op> op[0],0($at) |
12612 | <op> op[0]+1,4($at) | |
252b5132 RH |
12613 | Otherwise we want |
12614 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
12615 | nop | |
c0ebe874 RS |
12616 | <op> op[0],<sym>($at) (BFD_RELOC_LO16) |
12617 | <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16) | |
252b5132 RH |
12618 | If there is a base register we add it to $at before the |
12619 | lwc1 instructions. If there is a constant we include it | |
12620 | in the lwc1 instructions. */ | |
12621 | used_at = 1; | |
12622 | expr1.X_add_number = offset_expr.X_add_number; | |
252b5132 RH |
12623 | if (expr1.X_add_number < -0x8000 |
12624 | || expr1.X_add_number >= 0x8000 - 4) | |
12625 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 12626 | load_got_offset (AT, &offset_expr); |
269137b2 | 12627 | load_delay_nop (); |
252b5132 | 12628 | if (breg != 0) |
67c0d1eb | 12629 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
252b5132 RH |
12630 | |
12631 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
12632 | nop. */ | |
12633 | hold_mips_optimize = mips_optimize; | |
12634 | mips_optimize = 2; | |
4d7206a2 | 12635 | |
beae10d5 | 12636 | /* Itbl support may require additional care here. */ |
4d7206a2 | 12637 | relax_start (offset_expr.X_add_symbol); |
c0ebe874 | 12638 | macro_build (&expr1, s, fmt, coproc ? op[0] + 1 : op[0], |
67c0d1eb | 12639 | BFD_RELOC_LO16, AT); |
4d7206a2 | 12640 | expr1.X_add_number += 4; |
c0ebe874 | 12641 | macro_build (&expr1, s, fmt, coproc ? op[0] : op[0] + 1, |
67c0d1eb | 12642 | BFD_RELOC_LO16, AT); |
4d7206a2 | 12643 | relax_switch (); |
c0ebe874 | 12644 | macro_build (&offset_expr, s, fmt, coproc ? op[0] + 1 : op[0], |
67c0d1eb | 12645 | BFD_RELOC_LO16, AT); |
4d7206a2 | 12646 | offset_expr.X_add_number += 4; |
c0ebe874 | 12647 | macro_build (&offset_expr, s, fmt, coproc ? op[0] : op[0] + 1, |
67c0d1eb | 12648 | BFD_RELOC_LO16, AT); |
4d7206a2 | 12649 | relax_end (); |
252b5132 | 12650 | |
4d7206a2 | 12651 | mips_optimize = hold_mips_optimize; |
252b5132 | 12652 | } |
0a44bf69 | 12653 | else if (mips_big_got) |
252b5132 | 12654 | { |
67c0d1eb | 12655 | int gpdelay; |
252b5132 RH |
12656 | |
12657 | /* If this is a reference to an external symbol, we want | |
12658 | lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
12659 | addu $at,$at,$gp | |
12660 | lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16) | |
12661 | nop | |
c0ebe874 RS |
12662 | <op> op[0],0($at) |
12663 | <op> op[0]+1,4($at) | |
252b5132 RH |
12664 | Otherwise we want |
12665 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
12666 | nop | |
c0ebe874 RS |
12667 | <op> op[0],<sym>($at) (BFD_RELOC_LO16) |
12668 | <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16) | |
252b5132 RH |
12669 | If there is a base register we add it to $at before the |
12670 | lwc1 instructions. If there is a constant we include it | |
12671 | in the lwc1 instructions. */ | |
12672 | used_at = 1; | |
12673 | expr1.X_add_number = offset_expr.X_add_number; | |
12674 | offset_expr.X_add_number = 0; | |
12675 | if (expr1.X_add_number < -0x8000 | |
12676 | || expr1.X_add_number >= 0x8000 - 4) | |
12677 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 12678 | gpdelay = reg_needs_delay (mips_gp_register); |
4d7206a2 | 12679 | relax_start (offset_expr.X_add_symbol); |
df58fc94 | 12680 | macro_build (&offset_expr, "lui", LUI_FMT, |
67c0d1eb RS |
12681 | AT, BFD_RELOC_MIPS_GOT_HI16); |
12682 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 12683 | AT, AT, mips_gp_register); |
67c0d1eb | 12684 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
17a2f251 | 12685 | AT, BFD_RELOC_MIPS_GOT_LO16, AT); |
269137b2 | 12686 | load_delay_nop (); |
252b5132 | 12687 | if (breg != 0) |
67c0d1eb | 12688 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 12689 | /* Itbl support may require additional care here. */ |
c0ebe874 | 12690 | macro_build (&expr1, s, fmt, coproc ? op[0] + 1 : op[0], |
17a2f251 | 12691 | BFD_RELOC_LO16, AT); |
252b5132 RH |
12692 | expr1.X_add_number += 4; |
12693 | ||
12694 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
12695 | nop. */ | |
12696 | hold_mips_optimize = mips_optimize; | |
12697 | mips_optimize = 2; | |
beae10d5 | 12698 | /* Itbl support may require additional care here. */ |
c0ebe874 | 12699 | macro_build (&expr1, s, fmt, coproc ? op[0] : op[0] + 1, |
17a2f251 | 12700 | BFD_RELOC_LO16, AT); |
252b5132 RH |
12701 | mips_optimize = hold_mips_optimize; |
12702 | expr1.X_add_number -= 4; | |
12703 | ||
4d7206a2 RS |
12704 | relax_switch (); |
12705 | offset_expr.X_add_number = expr1.X_add_number; | |
67c0d1eb RS |
12706 | if (gpdelay) |
12707 | macro_build (NULL, "nop", ""); | |
12708 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, | |
12709 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 12710 | load_delay_nop (); |
252b5132 | 12711 | if (breg != 0) |
67c0d1eb | 12712 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 12713 | /* Itbl support may require additional care here. */ |
c0ebe874 | 12714 | macro_build (&offset_expr, s, fmt, coproc ? op[0] + 1 : op[0], |
67c0d1eb | 12715 | BFD_RELOC_LO16, AT); |
4d7206a2 | 12716 | offset_expr.X_add_number += 4; |
252b5132 RH |
12717 | |
12718 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
12719 | nop. */ | |
12720 | hold_mips_optimize = mips_optimize; | |
12721 | mips_optimize = 2; | |
beae10d5 | 12722 | /* Itbl support may require additional care here. */ |
c0ebe874 | 12723 | macro_build (&offset_expr, s, fmt, coproc ? op[0] : op[0] + 1, |
67c0d1eb | 12724 | BFD_RELOC_LO16, AT); |
252b5132 | 12725 | mips_optimize = hold_mips_optimize; |
4d7206a2 | 12726 | relax_end (); |
252b5132 | 12727 | } |
252b5132 RH |
12728 | else |
12729 | abort (); | |
12730 | ||
252b5132 | 12731 | break; |
3739860c | 12732 | |
dd6a37e7 | 12733 | case M_SAA_AB: |
dd6a37e7 | 12734 | s = "saa"; |
0db377d0 | 12735 | goto saa_saad; |
dd6a37e7 | 12736 | case M_SAAD_AB: |
dd6a37e7 | 12737 | s = "saad"; |
0db377d0 MR |
12738 | saa_saad: |
12739 | gas_assert (!mips_opts.micromips); | |
7f3c4072 | 12740 | offbits = 0; |
dd6a37e7 AP |
12741 | fmt = "t,(b)"; |
12742 | goto ld_st; | |
12743 | ||
252b5132 RH |
12744 | /* New code added to support COPZ instructions. |
12745 | This code builds table entries out of the macros in mip_opcodes. | |
12746 | R4000 uses interlocks to handle coproc delays. | |
12747 | Other chips (like the R3000) require nops to be inserted for delays. | |
12748 | ||
f72c8c98 | 12749 | FIXME: Currently, we require that the user handle delays. |
252b5132 RH |
12750 | In order to fill delay slots for non-interlocked chips, |
12751 | we must have a way to specify delays based on the coprocessor. | |
12752 | Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc. | |
12753 | What are the side-effects of the cop instruction? | |
12754 | What cache support might we have and what are its effects? | |
12755 | Both coprocessor & memory require delays. how long??? | |
bdaaa2e1 | 12756 | What registers are read/set/modified? |
252b5132 RH |
12757 | |
12758 | If an itbl is provided to interpret cop instructions, | |
bdaaa2e1 | 12759 | this knowledge can be encoded in the itbl spec. */ |
252b5132 RH |
12760 | |
12761 | case M_COP0: | |
12762 | s = "c0"; | |
12763 | goto copz; | |
12764 | case M_COP1: | |
12765 | s = "c1"; | |
12766 | goto copz; | |
12767 | case M_COP2: | |
12768 | s = "c2"; | |
12769 | goto copz; | |
12770 | case M_COP3: | |
12771 | s = "c3"; | |
12772 | copz: | |
df58fc94 | 12773 | gas_assert (!mips_opts.micromips); |
252b5132 RH |
12774 | /* For now we just do C (same as Cz). The parameter will be |
12775 | stored in insn_opcode by mips_ip. */ | |
c8276761 | 12776 | macro_build (NULL, s, "C", (int) ip->insn_opcode); |
8fc2e39e | 12777 | break; |
252b5132 | 12778 | |
ea1fb5dc | 12779 | case M_MOVE: |
c0ebe874 | 12780 | move_register (op[0], op[1]); |
8fc2e39e | 12781 | break; |
ea1fb5dc | 12782 | |
833794fc MR |
12783 | case M_MOVEP: |
12784 | gas_assert (mips_opts.micromips); | |
12785 | gas_assert (mips_opts.insn32); | |
c0ebe874 RS |
12786 | move_register (micromips_to_32_reg_h_map1[op[0]], |
12787 | micromips_to_32_reg_m_map[op[1]]); | |
12788 | move_register (micromips_to_32_reg_h_map2[op[0]], | |
12789 | micromips_to_32_reg_n_map[op[2]]); | |
833794fc MR |
12790 | break; |
12791 | ||
252b5132 RH |
12792 | case M_DMUL: |
12793 | dbl = 1; | |
1a0670f3 | 12794 | /* Fall through. */ |
252b5132 | 12795 | case M_MUL: |
e407c74b | 12796 | if (mips_opts.arch == CPU_R5900) |
c0ebe874 RS |
12797 | macro_build (NULL, dbl ? "dmultu" : "multu", "d,s,t", op[0], op[1], |
12798 | op[2]); | |
e407c74b NC |
12799 | else |
12800 | { | |
c0ebe874 RS |
12801 | macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", op[1], op[2]); |
12802 | macro_build (NULL, "mflo", MFHL_FMT, op[0]); | |
e407c74b | 12803 | } |
8fc2e39e | 12804 | break; |
252b5132 RH |
12805 | |
12806 | case M_DMUL_I: | |
12807 | dbl = 1; | |
1a0670f3 | 12808 | /* Fall through. */ |
252b5132 RH |
12809 | case M_MUL_I: |
12810 | /* The MIPS assembler some times generates shifts and adds. I'm | |
12811 | not trying to be that fancy. GCC should do this for us | |
12812 | anyway. */ | |
8fc2e39e | 12813 | used_at = 1; |
67c0d1eb | 12814 | load_register (AT, &imm_expr, dbl); |
c0ebe874 RS |
12815 | macro_build (NULL, dbl ? "dmult" : "mult", "s,t", op[1], AT); |
12816 | macro_build (NULL, "mflo", MFHL_FMT, op[0]); | |
252b5132 RH |
12817 | break; |
12818 | ||
12819 | case M_DMULO_I: | |
12820 | dbl = 1; | |
1a0670f3 | 12821 | /* Fall through. */ |
252b5132 RH |
12822 | case M_MULO_I: |
12823 | imm = 1; | |
12824 | goto do_mulo; | |
12825 | ||
12826 | case M_DMULO: | |
12827 | dbl = 1; | |
1a0670f3 | 12828 | /* Fall through. */ |
252b5132 RH |
12829 | case M_MULO: |
12830 | do_mulo: | |
7d10b47d | 12831 | start_noreorder (); |
8fc2e39e | 12832 | used_at = 1; |
252b5132 | 12833 | if (imm) |
67c0d1eb | 12834 | load_register (AT, &imm_expr, dbl); |
c0ebe874 RS |
12835 | macro_build (NULL, dbl ? "dmult" : "mult", "s,t", |
12836 | op[1], imm ? AT : op[2]); | |
12837 | macro_build (NULL, "mflo", MFHL_FMT, op[0]); | |
12838 | macro_build (NULL, dbl ? "dsra32" : "sra", SHFT_FMT, op[0], op[0], 31); | |
df58fc94 | 12839 | macro_build (NULL, "mfhi", MFHL_FMT, AT); |
252b5132 | 12840 | if (mips_trap) |
c0ebe874 | 12841 | macro_build (NULL, "tne", TRAP_FMT, op[0], AT, 6); |
252b5132 RH |
12842 | else |
12843 | { | |
df58fc94 RS |
12844 | if (mips_opts.micromips) |
12845 | micromips_label_expr (&label_expr); | |
12846 | else | |
12847 | label_expr.X_add_number = 8; | |
c0ebe874 | 12848 | macro_build (&label_expr, "beq", "s,t,p", op[0], AT); |
a605d2b3 | 12849 | macro_build (NULL, "nop", ""); |
df58fc94 RS |
12850 | macro_build (NULL, "break", BRK_FMT, 6); |
12851 | if (mips_opts.micromips) | |
12852 | micromips_add_label (); | |
252b5132 | 12853 | } |
7d10b47d | 12854 | end_noreorder (); |
c0ebe874 | 12855 | macro_build (NULL, "mflo", MFHL_FMT, op[0]); |
252b5132 RH |
12856 | break; |
12857 | ||
12858 | case M_DMULOU_I: | |
12859 | dbl = 1; | |
1a0670f3 | 12860 | /* Fall through. */ |
252b5132 RH |
12861 | case M_MULOU_I: |
12862 | imm = 1; | |
12863 | goto do_mulou; | |
12864 | ||
12865 | case M_DMULOU: | |
12866 | dbl = 1; | |
1a0670f3 | 12867 | /* Fall through. */ |
252b5132 RH |
12868 | case M_MULOU: |
12869 | do_mulou: | |
7d10b47d | 12870 | start_noreorder (); |
8fc2e39e | 12871 | used_at = 1; |
252b5132 | 12872 | if (imm) |
67c0d1eb RS |
12873 | load_register (AT, &imm_expr, dbl); |
12874 | macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", | |
c0ebe874 | 12875 | op[1], imm ? AT : op[2]); |
df58fc94 | 12876 | macro_build (NULL, "mfhi", MFHL_FMT, AT); |
c0ebe874 | 12877 | macro_build (NULL, "mflo", MFHL_FMT, op[0]); |
252b5132 | 12878 | if (mips_trap) |
df58fc94 | 12879 | macro_build (NULL, "tne", TRAP_FMT, AT, ZERO, 6); |
252b5132 RH |
12880 | else |
12881 | { | |
df58fc94 RS |
12882 | if (mips_opts.micromips) |
12883 | micromips_label_expr (&label_expr); | |
12884 | else | |
12885 | label_expr.X_add_number = 8; | |
12886 | macro_build (&label_expr, "beq", "s,t,p", AT, ZERO); | |
a605d2b3 | 12887 | macro_build (NULL, "nop", ""); |
df58fc94 RS |
12888 | macro_build (NULL, "break", BRK_FMT, 6); |
12889 | if (mips_opts.micromips) | |
12890 | micromips_add_label (); | |
252b5132 | 12891 | } |
7d10b47d | 12892 | end_noreorder (); |
252b5132 RH |
12893 | break; |
12894 | ||
771c7ce4 | 12895 | case M_DROL: |
fef14a42 | 12896 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 | 12897 | { |
c0ebe874 | 12898 | if (op[0] == op[1]) |
82dd0097 CD |
12899 | { |
12900 | tempreg = AT; | |
12901 | used_at = 1; | |
12902 | } | |
12903 | else | |
c0ebe874 RS |
12904 | tempreg = op[0]; |
12905 | macro_build (NULL, "dnegu", "d,w", tempreg, op[2]); | |
12906 | macro_build (NULL, "drorv", "d,t,s", op[0], op[1], tempreg); | |
8fc2e39e | 12907 | break; |
82dd0097 | 12908 | } |
8fc2e39e | 12909 | used_at = 1; |
c0ebe874 RS |
12910 | macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, op[2]); |
12911 | macro_build (NULL, "dsrlv", "d,t,s", AT, op[1], AT); | |
12912 | macro_build (NULL, "dsllv", "d,t,s", op[0], op[1], op[2]); | |
12913 | macro_build (NULL, "or", "d,v,t", op[0], op[0], AT); | |
771c7ce4 TS |
12914 | break; |
12915 | ||
252b5132 | 12916 | case M_ROL: |
fef14a42 | 12917 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 | 12918 | { |
c0ebe874 | 12919 | if (op[0] == op[1]) |
82dd0097 CD |
12920 | { |
12921 | tempreg = AT; | |
12922 | used_at = 1; | |
12923 | } | |
12924 | else | |
c0ebe874 RS |
12925 | tempreg = op[0]; |
12926 | macro_build (NULL, "negu", "d,w", tempreg, op[2]); | |
12927 | macro_build (NULL, "rorv", "d,t,s", op[0], op[1], tempreg); | |
8fc2e39e | 12928 | break; |
82dd0097 | 12929 | } |
8fc2e39e | 12930 | used_at = 1; |
c0ebe874 RS |
12931 | macro_build (NULL, "subu", "d,v,t", AT, ZERO, op[2]); |
12932 | macro_build (NULL, "srlv", "d,t,s", AT, op[1], AT); | |
12933 | macro_build (NULL, "sllv", "d,t,s", op[0], op[1], op[2]); | |
12934 | macro_build (NULL, "or", "d,v,t", op[0], op[0], AT); | |
252b5132 RH |
12935 | break; |
12936 | ||
771c7ce4 TS |
12937 | case M_DROL_I: |
12938 | { | |
12939 | unsigned int rot; | |
e0471c16 TS |
12940 | const char *l; |
12941 | const char *rr; | |
771c7ce4 | 12942 | |
771c7ce4 | 12943 | rot = imm_expr.X_add_number & 0x3f; |
fef14a42 | 12944 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
60b63b72 RS |
12945 | { |
12946 | rot = (64 - rot) & 0x3f; | |
12947 | if (rot >= 32) | |
c0ebe874 | 12948 | macro_build (NULL, "dror32", SHFT_FMT, op[0], op[1], rot - 32); |
60b63b72 | 12949 | else |
c0ebe874 | 12950 | macro_build (NULL, "dror", SHFT_FMT, op[0], op[1], rot); |
8fc2e39e | 12951 | break; |
60b63b72 | 12952 | } |
483fc7cd | 12953 | if (rot == 0) |
483fc7cd | 12954 | { |
c0ebe874 | 12955 | macro_build (NULL, "dsrl", SHFT_FMT, op[0], op[1], 0); |
8fc2e39e | 12956 | break; |
483fc7cd | 12957 | } |
82dd0097 | 12958 | l = (rot < 0x20) ? "dsll" : "dsll32"; |
91d6fa6a | 12959 | rr = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32"; |
82dd0097 | 12960 | rot &= 0x1f; |
8fc2e39e | 12961 | used_at = 1; |
c0ebe874 RS |
12962 | macro_build (NULL, l, SHFT_FMT, AT, op[1], rot); |
12963 | macro_build (NULL, rr, SHFT_FMT, op[0], op[1], (0x20 - rot) & 0x1f); | |
12964 | macro_build (NULL, "or", "d,v,t", op[0], op[0], AT); | |
771c7ce4 TS |
12965 | } |
12966 | break; | |
12967 | ||
252b5132 | 12968 | case M_ROL_I: |
771c7ce4 TS |
12969 | { |
12970 | unsigned int rot; | |
12971 | ||
771c7ce4 | 12972 | rot = imm_expr.X_add_number & 0x1f; |
fef14a42 | 12973 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
60b63b72 | 12974 | { |
c0ebe874 RS |
12975 | macro_build (NULL, "ror", SHFT_FMT, op[0], op[1], |
12976 | (32 - rot) & 0x1f); | |
8fc2e39e | 12977 | break; |
60b63b72 | 12978 | } |
483fc7cd | 12979 | if (rot == 0) |
483fc7cd | 12980 | { |
c0ebe874 | 12981 | macro_build (NULL, "srl", SHFT_FMT, op[0], op[1], 0); |
8fc2e39e | 12982 | break; |
483fc7cd | 12983 | } |
8fc2e39e | 12984 | used_at = 1; |
c0ebe874 RS |
12985 | macro_build (NULL, "sll", SHFT_FMT, AT, op[1], rot); |
12986 | macro_build (NULL, "srl", SHFT_FMT, op[0], op[1], (0x20 - rot) & 0x1f); | |
12987 | macro_build (NULL, "or", "d,v,t", op[0], op[0], AT); | |
771c7ce4 TS |
12988 | } |
12989 | break; | |
12990 | ||
12991 | case M_DROR: | |
fef14a42 | 12992 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 | 12993 | { |
c0ebe874 | 12994 | macro_build (NULL, "drorv", "d,t,s", op[0], op[1], op[2]); |
8fc2e39e | 12995 | break; |
82dd0097 | 12996 | } |
8fc2e39e | 12997 | used_at = 1; |
c0ebe874 RS |
12998 | macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, op[2]); |
12999 | macro_build (NULL, "dsllv", "d,t,s", AT, op[1], AT); | |
13000 | macro_build (NULL, "dsrlv", "d,t,s", op[0], op[1], op[2]); | |
13001 | macro_build (NULL, "or", "d,v,t", op[0], op[0], AT); | |
252b5132 RH |
13002 | break; |
13003 | ||
13004 | case M_ROR: | |
fef14a42 | 13005 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 | 13006 | { |
c0ebe874 | 13007 | macro_build (NULL, "rorv", "d,t,s", op[0], op[1], op[2]); |
8fc2e39e | 13008 | break; |
82dd0097 | 13009 | } |
8fc2e39e | 13010 | used_at = 1; |
c0ebe874 RS |
13011 | macro_build (NULL, "subu", "d,v,t", AT, ZERO, op[2]); |
13012 | macro_build (NULL, "sllv", "d,t,s", AT, op[1], AT); | |
13013 | macro_build (NULL, "srlv", "d,t,s", op[0], op[1], op[2]); | |
13014 | macro_build (NULL, "or", "d,v,t", op[0], op[0], AT); | |
252b5132 RH |
13015 | break; |
13016 | ||
771c7ce4 TS |
13017 | case M_DROR_I: |
13018 | { | |
13019 | unsigned int rot; | |
e0471c16 TS |
13020 | const char *l; |
13021 | const char *rr; | |
771c7ce4 | 13022 | |
771c7ce4 | 13023 | rot = imm_expr.X_add_number & 0x3f; |
fef14a42 | 13024 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 CD |
13025 | { |
13026 | if (rot >= 32) | |
c0ebe874 | 13027 | macro_build (NULL, "dror32", SHFT_FMT, op[0], op[1], rot - 32); |
82dd0097 | 13028 | else |
c0ebe874 | 13029 | macro_build (NULL, "dror", SHFT_FMT, op[0], op[1], rot); |
8fc2e39e | 13030 | break; |
82dd0097 | 13031 | } |
483fc7cd | 13032 | if (rot == 0) |
483fc7cd | 13033 | { |
c0ebe874 | 13034 | macro_build (NULL, "dsrl", SHFT_FMT, op[0], op[1], 0); |
8fc2e39e | 13035 | break; |
483fc7cd | 13036 | } |
91d6fa6a | 13037 | rr = (rot < 0x20) ? "dsrl" : "dsrl32"; |
82dd0097 CD |
13038 | l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32"; |
13039 | rot &= 0x1f; | |
8fc2e39e | 13040 | used_at = 1; |
c0ebe874 RS |
13041 | macro_build (NULL, rr, SHFT_FMT, AT, op[1], rot); |
13042 | macro_build (NULL, l, SHFT_FMT, op[0], op[1], (0x20 - rot) & 0x1f); | |
13043 | macro_build (NULL, "or", "d,v,t", op[0], op[0], AT); | |
771c7ce4 TS |
13044 | } |
13045 | break; | |
13046 | ||
252b5132 | 13047 | case M_ROR_I: |
771c7ce4 TS |
13048 | { |
13049 | unsigned int rot; | |
13050 | ||
771c7ce4 | 13051 | rot = imm_expr.X_add_number & 0x1f; |
fef14a42 | 13052 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 | 13053 | { |
c0ebe874 | 13054 | macro_build (NULL, "ror", SHFT_FMT, op[0], op[1], rot); |
8fc2e39e | 13055 | break; |
82dd0097 | 13056 | } |
483fc7cd | 13057 | if (rot == 0) |
483fc7cd | 13058 | { |
c0ebe874 | 13059 | macro_build (NULL, "srl", SHFT_FMT, op[0], op[1], 0); |
8fc2e39e | 13060 | break; |
483fc7cd | 13061 | } |
8fc2e39e | 13062 | used_at = 1; |
c0ebe874 RS |
13063 | macro_build (NULL, "srl", SHFT_FMT, AT, op[1], rot); |
13064 | macro_build (NULL, "sll", SHFT_FMT, op[0], op[1], (0x20 - rot) & 0x1f); | |
13065 | macro_build (NULL, "or", "d,v,t", op[0], op[0], AT); | |
771c7ce4 | 13066 | } |
252b5132 RH |
13067 | break; |
13068 | ||
252b5132 | 13069 | case M_SEQ: |
c0ebe874 RS |
13070 | if (op[1] == 0) |
13071 | macro_build (&expr1, "sltiu", "t,r,j", op[0], op[2], BFD_RELOC_LO16); | |
13072 | else if (op[2] == 0) | |
13073 | macro_build (&expr1, "sltiu", "t,r,j", op[0], op[1], BFD_RELOC_LO16); | |
252b5132 RH |
13074 | else |
13075 | { | |
c0ebe874 RS |
13076 | macro_build (NULL, "xor", "d,v,t", op[0], op[1], op[2]); |
13077 | macro_build (&expr1, "sltiu", "t,r,j", op[0], op[0], BFD_RELOC_LO16); | |
252b5132 | 13078 | } |
8fc2e39e | 13079 | break; |
252b5132 RH |
13080 | |
13081 | case M_SEQ_I: | |
b0e6f033 | 13082 | if (imm_expr.X_add_number == 0) |
252b5132 | 13083 | { |
c0ebe874 | 13084 | macro_build (&expr1, "sltiu", "t,r,j", op[0], op[1], BFD_RELOC_LO16); |
8fc2e39e | 13085 | break; |
252b5132 | 13086 | } |
c0ebe874 | 13087 | if (op[1] == 0) |
252b5132 | 13088 | { |
1661c76c | 13089 | as_warn (_("instruction %s: result is always false"), |
252b5132 | 13090 | ip->insn_mo->name); |
c0ebe874 | 13091 | move_register (op[0], 0); |
8fc2e39e | 13092 | break; |
252b5132 | 13093 | } |
dd3cbb7e NC |
13094 | if (CPU_HAS_SEQ (mips_opts.arch) |
13095 | && -512 <= imm_expr.X_add_number | |
13096 | && imm_expr.X_add_number < 512) | |
13097 | { | |
c0ebe874 | 13098 | macro_build (NULL, "seqi", "t,r,+Q", op[0], op[1], |
750bdd57 | 13099 | (int) imm_expr.X_add_number); |
dd3cbb7e NC |
13100 | break; |
13101 | } | |
b0e6f033 | 13102 | if (imm_expr.X_add_number >= 0 |
252b5132 | 13103 | && imm_expr.X_add_number < 0x10000) |
c0ebe874 | 13104 | macro_build (&imm_expr, "xori", "t,r,i", op[0], op[1], BFD_RELOC_LO16); |
b0e6f033 | 13105 | else if (imm_expr.X_add_number > -0x8000 |
252b5132 RH |
13106 | && imm_expr.X_add_number < 0) |
13107 | { | |
13108 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
bad1aba3 | 13109 | macro_build (&imm_expr, GPR_SIZE == 32 ? "addiu" : "daddiu", |
c0ebe874 | 13110 | "t,r,j", op[0], op[1], BFD_RELOC_LO16); |
252b5132 | 13111 | } |
dd3cbb7e NC |
13112 | else if (CPU_HAS_SEQ (mips_opts.arch)) |
13113 | { | |
13114 | used_at = 1; | |
bad1aba3 | 13115 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
c0ebe874 | 13116 | macro_build (NULL, "seq", "d,v,t", op[0], op[1], AT); |
dd3cbb7e NC |
13117 | break; |
13118 | } | |
252b5132 RH |
13119 | else |
13120 | { | |
bad1aba3 | 13121 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
c0ebe874 | 13122 | macro_build (NULL, "xor", "d,v,t", op[0], op[1], AT); |
252b5132 RH |
13123 | used_at = 1; |
13124 | } | |
c0ebe874 | 13125 | macro_build (&expr1, "sltiu", "t,r,j", op[0], op[0], BFD_RELOC_LO16); |
8fc2e39e | 13126 | break; |
252b5132 | 13127 | |
c0ebe874 | 13128 | case M_SGE: /* X >= Y <==> not (X < Y) */ |
252b5132 RH |
13129 | s = "slt"; |
13130 | goto sge; | |
13131 | case M_SGEU: | |
13132 | s = "sltu"; | |
13133 | sge: | |
c0ebe874 RS |
13134 | macro_build (NULL, s, "d,v,t", op[0], op[1], op[2]); |
13135 | macro_build (&expr1, "xori", "t,r,i", op[0], op[0], BFD_RELOC_LO16); | |
8fc2e39e | 13136 | break; |
252b5132 | 13137 | |
c0ebe874 | 13138 | case M_SGE_I: /* X >= I <==> not (X < I) */ |
252b5132 | 13139 | case M_SGEU_I: |
b0e6f033 | 13140 | if (imm_expr.X_add_number >= -0x8000 |
252b5132 | 13141 | && imm_expr.X_add_number < 0x8000) |
c0ebe874 RS |
13142 | macro_build (&imm_expr, mask == M_SGE_I ? "slti" : "sltiu", "t,r,j", |
13143 | op[0], op[1], BFD_RELOC_LO16); | |
252b5132 RH |
13144 | else |
13145 | { | |
bad1aba3 | 13146 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
67c0d1eb | 13147 | macro_build (NULL, mask == M_SGE_I ? "slt" : "sltu", "d,v,t", |
c0ebe874 | 13148 | op[0], op[1], AT); |
252b5132 RH |
13149 | used_at = 1; |
13150 | } | |
c0ebe874 | 13151 | macro_build (&expr1, "xori", "t,r,i", op[0], op[0], BFD_RELOC_LO16); |
8fc2e39e | 13152 | break; |
252b5132 | 13153 | |
c0ebe874 | 13154 | case M_SGT: /* X > Y <==> Y < X */ |
252b5132 RH |
13155 | s = "slt"; |
13156 | goto sgt; | |
13157 | case M_SGTU: | |
13158 | s = "sltu"; | |
13159 | sgt: | |
c0ebe874 | 13160 | macro_build (NULL, s, "d,v,t", op[0], op[2], op[1]); |
8fc2e39e | 13161 | break; |
252b5132 | 13162 | |
c0ebe874 | 13163 | case M_SGT_I: /* X > I <==> I < X */ |
252b5132 RH |
13164 | s = "slt"; |
13165 | goto sgti; | |
13166 | case M_SGTU_I: | |
13167 | s = "sltu"; | |
13168 | sgti: | |
8fc2e39e | 13169 | used_at = 1; |
bad1aba3 | 13170 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
c0ebe874 | 13171 | macro_build (NULL, s, "d,v,t", op[0], AT, op[1]); |
252b5132 RH |
13172 | break; |
13173 | ||
c0ebe874 | 13174 | case M_SLE: /* X <= Y <==> Y >= X <==> not (Y < X) */ |
252b5132 RH |
13175 | s = "slt"; |
13176 | goto sle; | |
13177 | case M_SLEU: | |
13178 | s = "sltu"; | |
13179 | sle: | |
c0ebe874 RS |
13180 | macro_build (NULL, s, "d,v,t", op[0], op[2], op[1]); |
13181 | macro_build (&expr1, "xori", "t,r,i", op[0], op[0], BFD_RELOC_LO16); | |
8fc2e39e | 13182 | break; |
252b5132 | 13183 | |
c0ebe874 | 13184 | case M_SLE_I: /* X <= I <==> I >= X <==> not (I < X) */ |
252b5132 RH |
13185 | s = "slt"; |
13186 | goto slei; | |
13187 | case M_SLEU_I: | |
13188 | s = "sltu"; | |
13189 | slei: | |
8fc2e39e | 13190 | used_at = 1; |
bad1aba3 | 13191 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
c0ebe874 RS |
13192 | macro_build (NULL, s, "d,v,t", op[0], AT, op[1]); |
13193 | macro_build (&expr1, "xori", "t,r,i", op[0], op[0], BFD_RELOC_LO16); | |
252b5132 RH |
13194 | break; |
13195 | ||
13196 | case M_SLT_I: | |
b0e6f033 | 13197 | if (imm_expr.X_add_number >= -0x8000 |
252b5132 RH |
13198 | && imm_expr.X_add_number < 0x8000) |
13199 | { | |
c0ebe874 RS |
13200 | macro_build (&imm_expr, "slti", "t,r,j", op[0], op[1], |
13201 | BFD_RELOC_LO16); | |
8fc2e39e | 13202 | break; |
252b5132 | 13203 | } |
8fc2e39e | 13204 | used_at = 1; |
bad1aba3 | 13205 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
c0ebe874 | 13206 | macro_build (NULL, "slt", "d,v,t", op[0], op[1], AT); |
252b5132 RH |
13207 | break; |
13208 | ||
13209 | case M_SLTU_I: | |
b0e6f033 | 13210 | if (imm_expr.X_add_number >= -0x8000 |
252b5132 RH |
13211 | && imm_expr.X_add_number < 0x8000) |
13212 | { | |
c0ebe874 | 13213 | macro_build (&imm_expr, "sltiu", "t,r,j", op[0], op[1], |
17a2f251 | 13214 | BFD_RELOC_LO16); |
8fc2e39e | 13215 | break; |
252b5132 | 13216 | } |
8fc2e39e | 13217 | used_at = 1; |
bad1aba3 | 13218 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
c0ebe874 | 13219 | macro_build (NULL, "sltu", "d,v,t", op[0], op[1], AT); |
252b5132 RH |
13220 | break; |
13221 | ||
13222 | case M_SNE: | |
c0ebe874 RS |
13223 | if (op[1] == 0) |
13224 | macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[2]); | |
13225 | else if (op[2] == 0) | |
13226 | macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[1]); | |
252b5132 RH |
13227 | else |
13228 | { | |
c0ebe874 RS |
13229 | macro_build (NULL, "xor", "d,v,t", op[0], op[1], op[2]); |
13230 | macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[0]); | |
252b5132 | 13231 | } |
8fc2e39e | 13232 | break; |
252b5132 RH |
13233 | |
13234 | case M_SNE_I: | |
b0e6f033 | 13235 | if (imm_expr.X_add_number == 0) |
252b5132 | 13236 | { |
c0ebe874 | 13237 | macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[1]); |
8fc2e39e | 13238 | break; |
252b5132 | 13239 | } |
c0ebe874 | 13240 | if (op[1] == 0) |
252b5132 | 13241 | { |
1661c76c | 13242 | as_warn (_("instruction %s: result is always true"), |
252b5132 | 13243 | ip->insn_mo->name); |
bad1aba3 | 13244 | macro_build (&expr1, GPR_SIZE == 32 ? "addiu" : "daddiu", "t,r,j", |
c0ebe874 | 13245 | op[0], 0, BFD_RELOC_LO16); |
8fc2e39e | 13246 | break; |
252b5132 | 13247 | } |
dd3cbb7e NC |
13248 | if (CPU_HAS_SEQ (mips_opts.arch) |
13249 | && -512 <= imm_expr.X_add_number | |
13250 | && imm_expr.X_add_number < 512) | |
13251 | { | |
c0ebe874 | 13252 | macro_build (NULL, "snei", "t,r,+Q", op[0], op[1], |
750bdd57 | 13253 | (int) imm_expr.X_add_number); |
dd3cbb7e NC |
13254 | break; |
13255 | } | |
b0e6f033 | 13256 | if (imm_expr.X_add_number >= 0 |
252b5132 RH |
13257 | && imm_expr.X_add_number < 0x10000) |
13258 | { | |
c0ebe874 RS |
13259 | macro_build (&imm_expr, "xori", "t,r,i", op[0], op[1], |
13260 | BFD_RELOC_LO16); | |
252b5132 | 13261 | } |
b0e6f033 | 13262 | else if (imm_expr.X_add_number > -0x8000 |
252b5132 RH |
13263 | && imm_expr.X_add_number < 0) |
13264 | { | |
13265 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
bad1aba3 | 13266 | macro_build (&imm_expr, GPR_SIZE == 32 ? "addiu" : "daddiu", |
c0ebe874 | 13267 | "t,r,j", op[0], op[1], BFD_RELOC_LO16); |
252b5132 | 13268 | } |
dd3cbb7e NC |
13269 | else if (CPU_HAS_SEQ (mips_opts.arch)) |
13270 | { | |
13271 | used_at = 1; | |
bad1aba3 | 13272 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
c0ebe874 | 13273 | macro_build (NULL, "sne", "d,v,t", op[0], op[1], AT); |
dd3cbb7e NC |
13274 | break; |
13275 | } | |
252b5132 RH |
13276 | else |
13277 | { | |
bad1aba3 | 13278 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
c0ebe874 | 13279 | macro_build (NULL, "xor", "d,v,t", op[0], op[1], AT); |
252b5132 RH |
13280 | used_at = 1; |
13281 | } | |
c0ebe874 | 13282 | macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[0]); |
8fc2e39e | 13283 | break; |
252b5132 | 13284 | |
df58fc94 RS |
13285 | case M_SUB_I: |
13286 | s = "addi"; | |
13287 | s2 = "sub"; | |
13288 | goto do_subi; | |
13289 | case M_SUBU_I: | |
13290 | s = "addiu"; | |
13291 | s2 = "subu"; | |
13292 | goto do_subi; | |
252b5132 RH |
13293 | case M_DSUB_I: |
13294 | dbl = 1; | |
df58fc94 RS |
13295 | s = "daddi"; |
13296 | s2 = "dsub"; | |
13297 | if (!mips_opts.micromips) | |
13298 | goto do_subi; | |
b0e6f033 | 13299 | if (imm_expr.X_add_number > -0x200 |
df58fc94 | 13300 | && imm_expr.X_add_number <= 0x200) |
252b5132 | 13301 | { |
b0e6f033 RS |
13302 | macro_build (NULL, s, "t,r,.", op[0], op[1], |
13303 | (int) -imm_expr.X_add_number); | |
8fc2e39e | 13304 | break; |
252b5132 | 13305 | } |
df58fc94 | 13306 | goto do_subi_i; |
252b5132 RH |
13307 | case M_DSUBU_I: |
13308 | dbl = 1; | |
df58fc94 RS |
13309 | s = "daddiu"; |
13310 | s2 = "dsubu"; | |
13311 | do_subi: | |
b0e6f033 | 13312 | if (imm_expr.X_add_number > -0x8000 |
252b5132 RH |
13313 | && imm_expr.X_add_number <= 0x8000) |
13314 | { | |
13315 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
c0ebe874 | 13316 | macro_build (&imm_expr, s, "t,r,j", op[0], op[1], BFD_RELOC_LO16); |
8fc2e39e | 13317 | break; |
252b5132 | 13318 | } |
df58fc94 | 13319 | do_subi_i: |
8fc2e39e | 13320 | used_at = 1; |
67c0d1eb | 13321 | load_register (AT, &imm_expr, dbl); |
c0ebe874 | 13322 | macro_build (NULL, s2, "d,v,t", op[0], op[1], AT); |
252b5132 RH |
13323 | break; |
13324 | ||
13325 | case M_TEQ_I: | |
13326 | s = "teq"; | |
13327 | goto trap; | |
13328 | case M_TGE_I: | |
13329 | s = "tge"; | |
13330 | goto trap; | |
13331 | case M_TGEU_I: | |
13332 | s = "tgeu"; | |
13333 | goto trap; | |
13334 | case M_TLT_I: | |
13335 | s = "tlt"; | |
13336 | goto trap; | |
13337 | case M_TLTU_I: | |
13338 | s = "tltu"; | |
13339 | goto trap; | |
13340 | case M_TNE_I: | |
13341 | s = "tne"; | |
13342 | trap: | |
8fc2e39e | 13343 | used_at = 1; |
bad1aba3 | 13344 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
c0ebe874 | 13345 | macro_build (NULL, s, "s,t", op[0], AT); |
252b5132 RH |
13346 | break; |
13347 | ||
252b5132 | 13348 | case M_TRUNCWS: |
43841e91 | 13349 | case M_TRUNCWD: |
df58fc94 | 13350 | gas_assert (!mips_opts.micromips); |
0aa27725 | 13351 | gas_assert (mips_opts.isa == ISA_MIPS1); |
8fc2e39e | 13352 | used_at = 1; |
252b5132 RH |
13353 | |
13354 | /* | |
13355 | * Is the double cfc1 instruction a bug in the mips assembler; | |
13356 | * or is there a reason for it? | |
13357 | */ | |
7d10b47d | 13358 | start_noreorder (); |
c0ebe874 RS |
13359 | macro_build (NULL, "cfc1", "t,G", op[2], RA); |
13360 | macro_build (NULL, "cfc1", "t,G", op[2], RA); | |
67c0d1eb | 13361 | macro_build (NULL, "nop", ""); |
252b5132 | 13362 | expr1.X_add_number = 3; |
c0ebe874 | 13363 | macro_build (&expr1, "ori", "t,r,i", AT, op[2], BFD_RELOC_LO16); |
252b5132 | 13364 | expr1.X_add_number = 2; |
67c0d1eb RS |
13365 | macro_build (&expr1, "xori", "t,r,i", AT, AT, BFD_RELOC_LO16); |
13366 | macro_build (NULL, "ctc1", "t,G", AT, RA); | |
13367 | macro_build (NULL, "nop", ""); | |
13368 | macro_build (NULL, mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S", | |
c0ebe874 RS |
13369 | op[0], op[1]); |
13370 | macro_build (NULL, "ctc1", "t,G", op[2], RA); | |
67c0d1eb | 13371 | macro_build (NULL, "nop", ""); |
7d10b47d | 13372 | end_noreorder (); |
252b5132 RH |
13373 | break; |
13374 | ||
f2ae14a1 | 13375 | case M_ULH_AB: |
252b5132 | 13376 | s = "lb"; |
df58fc94 RS |
13377 | s2 = "lbu"; |
13378 | off = 1; | |
13379 | goto uld_st; | |
f2ae14a1 | 13380 | case M_ULHU_AB: |
252b5132 | 13381 | s = "lbu"; |
df58fc94 RS |
13382 | s2 = "lbu"; |
13383 | off = 1; | |
13384 | goto uld_st; | |
f2ae14a1 | 13385 | case M_ULW_AB: |
df58fc94 RS |
13386 | s = "lwl"; |
13387 | s2 = "lwr"; | |
7f3c4072 | 13388 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 RS |
13389 | off = 3; |
13390 | goto uld_st; | |
f2ae14a1 | 13391 | case M_ULD_AB: |
252b5132 RH |
13392 | s = "ldl"; |
13393 | s2 = "ldr"; | |
7f3c4072 | 13394 | offbits = (mips_opts.micromips ? 12 : 16); |
252b5132 | 13395 | off = 7; |
df58fc94 | 13396 | goto uld_st; |
f2ae14a1 | 13397 | case M_USH_AB: |
df58fc94 RS |
13398 | s = "sb"; |
13399 | s2 = "sb"; | |
13400 | off = 1; | |
13401 | ust = 1; | |
13402 | goto uld_st; | |
f2ae14a1 | 13403 | case M_USW_AB: |
df58fc94 RS |
13404 | s = "swl"; |
13405 | s2 = "swr"; | |
7f3c4072 | 13406 | offbits = (mips_opts.micromips ? 12 : 16); |
252b5132 | 13407 | off = 3; |
df58fc94 RS |
13408 | ust = 1; |
13409 | goto uld_st; | |
f2ae14a1 | 13410 | case M_USD_AB: |
df58fc94 RS |
13411 | s = "sdl"; |
13412 | s2 = "sdr"; | |
7f3c4072 | 13413 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 RS |
13414 | off = 7; |
13415 | ust = 1; | |
13416 | ||
13417 | uld_st: | |
c0ebe874 | 13418 | breg = op[2]; |
f2ae14a1 | 13419 | large_offset = !small_offset_p (off, align, offbits); |
df58fc94 RS |
13420 | ep = &offset_expr; |
13421 | expr1.X_add_number = 0; | |
f2ae14a1 | 13422 | if (large_offset) |
df58fc94 RS |
13423 | { |
13424 | used_at = 1; | |
13425 | tempreg = AT; | |
f2ae14a1 RS |
13426 | if (small_offset_p (0, align, 16)) |
13427 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", tempreg, breg, -1, | |
13428 | offset_reloc[0], offset_reloc[1], offset_reloc[2]); | |
13429 | else | |
13430 | { | |
13431 | load_address (tempreg, ep, &used_at); | |
13432 | if (breg != 0) | |
13433 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
13434 | tempreg, tempreg, breg); | |
13435 | } | |
13436 | offset_reloc[0] = BFD_RELOC_LO16; | |
13437 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
13438 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
df58fc94 | 13439 | breg = tempreg; |
c0ebe874 | 13440 | tempreg = op[0]; |
df58fc94 RS |
13441 | ep = &expr1; |
13442 | } | |
c0ebe874 | 13443 | else if (!ust && op[0] == breg) |
8fc2e39e TS |
13444 | { |
13445 | used_at = 1; | |
13446 | tempreg = AT; | |
13447 | } | |
252b5132 | 13448 | else |
c0ebe874 | 13449 | tempreg = op[0]; |
af22f5b2 | 13450 | |
df58fc94 RS |
13451 | if (off == 1) |
13452 | goto ulh_sh; | |
252b5132 | 13453 | |
90ecf173 | 13454 | if (!target_big_endian) |
df58fc94 | 13455 | ep->X_add_number += off; |
f2ae14a1 | 13456 | if (offbits == 12) |
c8276761 | 13457 | macro_build (NULL, s, "t,~(b)", tempreg, (int) ep->X_add_number, breg); |
f2ae14a1 RS |
13458 | else |
13459 | macro_build (ep, s, "t,o(b)", tempreg, -1, | |
13460 | offset_reloc[0], offset_reloc[1], offset_reloc[2], breg); | |
df58fc94 | 13461 | |
90ecf173 | 13462 | if (!target_big_endian) |
df58fc94 | 13463 | ep->X_add_number -= off; |
252b5132 | 13464 | else |
df58fc94 | 13465 | ep->X_add_number += off; |
f2ae14a1 | 13466 | if (offbits == 12) |
df58fc94 | 13467 | macro_build (NULL, s2, "t,~(b)", |
c8276761 | 13468 | tempreg, (int) ep->X_add_number, breg); |
f2ae14a1 RS |
13469 | else |
13470 | macro_build (ep, s2, "t,o(b)", tempreg, -1, | |
13471 | offset_reloc[0], offset_reloc[1], offset_reloc[2], breg); | |
252b5132 | 13472 | |
df58fc94 | 13473 | /* If necessary, move the result in tempreg to the final destination. */ |
c0ebe874 | 13474 | if (!ust && op[0] != tempreg) |
df58fc94 RS |
13475 | { |
13476 | /* Protect second load's delay slot. */ | |
13477 | load_delay_nop (); | |
c0ebe874 | 13478 | move_register (op[0], tempreg); |
df58fc94 | 13479 | } |
8fc2e39e | 13480 | break; |
252b5132 | 13481 | |
df58fc94 | 13482 | ulh_sh: |
d6bc6245 | 13483 | used_at = 1; |
df58fc94 RS |
13484 | if (target_big_endian == ust) |
13485 | ep->X_add_number += off; | |
c0ebe874 | 13486 | tempreg = ust || large_offset ? op[0] : AT; |
f2ae14a1 RS |
13487 | macro_build (ep, s, "t,o(b)", tempreg, -1, |
13488 | offset_reloc[0], offset_reloc[1], offset_reloc[2], breg); | |
df58fc94 RS |
13489 | |
13490 | /* For halfword transfers we need a temporary register to shuffle | |
13491 | bytes. Unfortunately for M_USH_A we have none available before | |
13492 | the next store as AT holds the base address. We deal with this | |
13493 | case by clobbering TREG and then restoring it as with ULH. */ | |
c0ebe874 | 13494 | tempreg = ust == large_offset ? op[0] : AT; |
df58fc94 | 13495 | if (ust) |
c0ebe874 | 13496 | macro_build (NULL, "srl", SHFT_FMT, tempreg, op[0], 8); |
df58fc94 RS |
13497 | |
13498 | if (target_big_endian == ust) | |
13499 | ep->X_add_number -= off; | |
252b5132 | 13500 | else |
df58fc94 | 13501 | ep->X_add_number += off; |
f2ae14a1 RS |
13502 | macro_build (ep, s2, "t,o(b)", tempreg, -1, |
13503 | offset_reloc[0], offset_reloc[1], offset_reloc[2], breg); | |
252b5132 | 13504 | |
df58fc94 | 13505 | /* For M_USH_A re-retrieve the LSB. */ |
f2ae14a1 | 13506 | if (ust && large_offset) |
df58fc94 RS |
13507 | { |
13508 | if (target_big_endian) | |
13509 | ep->X_add_number += off; | |
13510 | else | |
13511 | ep->X_add_number -= off; | |
f2ae14a1 RS |
13512 | macro_build (&expr1, "lbu", "t,o(b)", AT, -1, |
13513 | offset_reloc[0], offset_reloc[1], offset_reloc[2], AT); | |
df58fc94 RS |
13514 | } |
13515 | /* For ULH and M_USH_A OR the LSB in. */ | |
f2ae14a1 | 13516 | if (!ust || large_offset) |
df58fc94 | 13517 | { |
c0ebe874 | 13518 | tempreg = !large_offset ? AT : op[0]; |
df58fc94 | 13519 | macro_build (NULL, "sll", SHFT_FMT, tempreg, tempreg, 8); |
c0ebe874 | 13520 | macro_build (NULL, "or", "d,v,t", op[0], op[0], AT); |
df58fc94 | 13521 | } |
252b5132 RH |
13522 | break; |
13523 | ||
13524 | default: | |
13525 | /* FIXME: Check if this is one of the itbl macros, since they | |
bdaaa2e1 | 13526 | are added dynamically. */ |
1661c76c | 13527 | as_bad (_("macro %s not implemented yet"), ip->insn_mo->name); |
252b5132 RH |
13528 | break; |
13529 | } | |
741fe287 | 13530 | if (!mips_opts.at && used_at) |
1661c76c | 13531 | as_bad (_("macro used $at after \".set noat\"")); |
252b5132 RH |
13532 | } |
13533 | ||
13534 | /* Implement macros in mips16 mode. */ | |
13535 | ||
13536 | static void | |
17a2f251 | 13537 | mips16_macro (struct mips_cl_insn *ip) |
252b5132 | 13538 | { |
c0ebe874 | 13539 | const struct mips_operand_array *operands; |
252b5132 | 13540 | int mask; |
c0ebe874 | 13541 | int tmp; |
252b5132 RH |
13542 | expressionS expr1; |
13543 | int dbl; | |
13544 | const char *s, *s2, *s3; | |
c0ebe874 RS |
13545 | unsigned int op[MAX_OPERANDS]; |
13546 | unsigned int i; | |
252b5132 RH |
13547 | |
13548 | mask = ip->insn_mo->mask; | |
13549 | ||
c0ebe874 RS |
13550 | operands = insn_operands (ip); |
13551 | for (i = 0; i < MAX_OPERANDS; i++) | |
13552 | if (operands->operand[i]) | |
13553 | op[i] = insn_extract_operand (ip, operands->operand[i]); | |
13554 | else | |
13555 | op[i] = -1; | |
252b5132 | 13556 | |
252b5132 RH |
13557 | expr1.X_op = O_constant; |
13558 | expr1.X_op_symbol = NULL; | |
13559 | expr1.X_add_symbol = NULL; | |
13560 | expr1.X_add_number = 1; | |
13561 | ||
13562 | dbl = 0; | |
13563 | ||
13564 | switch (mask) | |
13565 | { | |
13566 | default: | |
b37df7c4 | 13567 | abort (); |
252b5132 RH |
13568 | |
13569 | case M_DDIV_3: | |
13570 | dbl = 1; | |
1a0670f3 | 13571 | /* Fall through. */ |
252b5132 RH |
13572 | case M_DIV_3: |
13573 | s = "mflo"; | |
13574 | goto do_div3; | |
13575 | case M_DREM_3: | |
13576 | dbl = 1; | |
1a0670f3 | 13577 | /* Fall through. */ |
252b5132 RH |
13578 | case M_REM_3: |
13579 | s = "mfhi"; | |
13580 | do_div3: | |
7d10b47d | 13581 | start_noreorder (); |
d8722d76 | 13582 | macro_build (NULL, dbl ? "ddiv" : "div", ".,x,y", op[1], op[2]); |
252b5132 | 13583 | expr1.X_add_number = 2; |
c0ebe874 | 13584 | macro_build (&expr1, "bnez", "x,p", op[2]); |
67c0d1eb | 13585 | macro_build (NULL, "break", "6", 7); |
bdaaa2e1 | 13586 | |
252b5132 RH |
13587 | /* FIXME: The normal code checks for of -1 / -0x80000000 here, |
13588 | since that causes an overflow. We should do that as well, | |
13589 | but I don't see how to do the comparisons without a temporary | |
13590 | register. */ | |
7d10b47d | 13591 | end_noreorder (); |
c0ebe874 | 13592 | macro_build (NULL, s, "x", op[0]); |
252b5132 RH |
13593 | break; |
13594 | ||
13595 | case M_DIVU_3: | |
13596 | s = "divu"; | |
13597 | s2 = "mflo"; | |
13598 | goto do_divu3; | |
13599 | case M_REMU_3: | |
13600 | s = "divu"; | |
13601 | s2 = "mfhi"; | |
13602 | goto do_divu3; | |
13603 | case M_DDIVU_3: | |
13604 | s = "ddivu"; | |
13605 | s2 = "mflo"; | |
13606 | goto do_divu3; | |
13607 | case M_DREMU_3: | |
13608 | s = "ddivu"; | |
13609 | s2 = "mfhi"; | |
13610 | do_divu3: | |
7d10b47d | 13611 | start_noreorder (); |
d8722d76 | 13612 | macro_build (NULL, s, ".,x,y", op[1], op[2]); |
252b5132 | 13613 | expr1.X_add_number = 2; |
c0ebe874 | 13614 | macro_build (&expr1, "bnez", "x,p", op[2]); |
67c0d1eb | 13615 | macro_build (NULL, "break", "6", 7); |
7d10b47d | 13616 | end_noreorder (); |
c0ebe874 | 13617 | macro_build (NULL, s2, "x", op[0]); |
252b5132 RH |
13618 | break; |
13619 | ||
13620 | case M_DMUL: | |
13621 | dbl = 1; | |
1a0670f3 | 13622 | /* Fall through. */ |
252b5132 | 13623 | case M_MUL: |
c0ebe874 RS |
13624 | macro_build (NULL, dbl ? "dmultu" : "multu", "x,y", op[1], op[2]); |
13625 | macro_build (NULL, "mflo", "x", op[0]); | |
8fc2e39e | 13626 | break; |
252b5132 RH |
13627 | |
13628 | case M_DSUBU_I: | |
13629 | dbl = 1; | |
13630 | goto do_subu; | |
13631 | case M_SUBU_I: | |
13632 | do_subu: | |
252b5132 | 13633 | imm_expr.X_add_number = -imm_expr.X_add_number; |
d8722d76 | 13634 | macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "y,x,F", op[0], op[1]); |
252b5132 RH |
13635 | break; |
13636 | ||
13637 | case M_SUBU_I_2: | |
252b5132 | 13638 | imm_expr.X_add_number = -imm_expr.X_add_number; |
c0ebe874 | 13639 | macro_build (&imm_expr, "addiu", "x,k", op[0]); |
252b5132 RH |
13640 | break; |
13641 | ||
13642 | case M_DSUBU_I_2: | |
252b5132 | 13643 | imm_expr.X_add_number = -imm_expr.X_add_number; |
c0ebe874 | 13644 | macro_build (&imm_expr, "daddiu", "y,j", op[0]); |
252b5132 RH |
13645 | break; |
13646 | ||
13647 | case M_BEQ: | |
13648 | s = "cmp"; | |
13649 | s2 = "bteqz"; | |
13650 | goto do_branch; | |
13651 | case M_BNE: | |
13652 | s = "cmp"; | |
13653 | s2 = "btnez"; | |
13654 | goto do_branch; | |
13655 | case M_BLT: | |
13656 | s = "slt"; | |
13657 | s2 = "btnez"; | |
13658 | goto do_branch; | |
13659 | case M_BLTU: | |
13660 | s = "sltu"; | |
13661 | s2 = "btnez"; | |
13662 | goto do_branch; | |
13663 | case M_BLE: | |
13664 | s = "slt"; | |
13665 | s2 = "bteqz"; | |
13666 | goto do_reverse_branch; | |
13667 | case M_BLEU: | |
13668 | s = "sltu"; | |
13669 | s2 = "bteqz"; | |
13670 | goto do_reverse_branch; | |
13671 | case M_BGE: | |
13672 | s = "slt"; | |
13673 | s2 = "bteqz"; | |
13674 | goto do_branch; | |
13675 | case M_BGEU: | |
13676 | s = "sltu"; | |
13677 | s2 = "bteqz"; | |
13678 | goto do_branch; | |
13679 | case M_BGT: | |
13680 | s = "slt"; | |
13681 | s2 = "btnez"; | |
13682 | goto do_reverse_branch; | |
13683 | case M_BGTU: | |
13684 | s = "sltu"; | |
13685 | s2 = "btnez"; | |
13686 | ||
13687 | do_reverse_branch: | |
c0ebe874 RS |
13688 | tmp = op[1]; |
13689 | op[1] = op[0]; | |
13690 | op[0] = tmp; | |
252b5132 RH |
13691 | |
13692 | do_branch: | |
c0ebe874 | 13693 | macro_build (NULL, s, "x,y", op[0], op[1]); |
67c0d1eb | 13694 | macro_build (&offset_expr, s2, "p"); |
252b5132 RH |
13695 | break; |
13696 | ||
13697 | case M_BEQ_I: | |
13698 | s = "cmpi"; | |
13699 | s2 = "bteqz"; | |
13700 | s3 = "x,U"; | |
13701 | goto do_branch_i; | |
13702 | case M_BNE_I: | |
13703 | s = "cmpi"; | |
13704 | s2 = "btnez"; | |
13705 | s3 = "x,U"; | |
13706 | goto do_branch_i; | |
13707 | case M_BLT_I: | |
13708 | s = "slti"; | |
13709 | s2 = "btnez"; | |
13710 | s3 = "x,8"; | |
13711 | goto do_branch_i; | |
13712 | case M_BLTU_I: | |
13713 | s = "sltiu"; | |
13714 | s2 = "btnez"; | |
13715 | s3 = "x,8"; | |
13716 | goto do_branch_i; | |
13717 | case M_BLE_I: | |
13718 | s = "slti"; | |
13719 | s2 = "btnez"; | |
13720 | s3 = "x,8"; | |
13721 | goto do_addone_branch_i; | |
13722 | case M_BLEU_I: | |
13723 | s = "sltiu"; | |
13724 | s2 = "btnez"; | |
13725 | s3 = "x,8"; | |
13726 | goto do_addone_branch_i; | |
13727 | case M_BGE_I: | |
13728 | s = "slti"; | |
13729 | s2 = "bteqz"; | |
13730 | s3 = "x,8"; | |
13731 | goto do_branch_i; | |
13732 | case M_BGEU_I: | |
13733 | s = "sltiu"; | |
13734 | s2 = "bteqz"; | |
13735 | s3 = "x,8"; | |
13736 | goto do_branch_i; | |
13737 | case M_BGT_I: | |
13738 | s = "slti"; | |
13739 | s2 = "bteqz"; | |
13740 | s3 = "x,8"; | |
13741 | goto do_addone_branch_i; | |
13742 | case M_BGTU_I: | |
13743 | s = "sltiu"; | |
13744 | s2 = "bteqz"; | |
13745 | s3 = "x,8"; | |
13746 | ||
13747 | do_addone_branch_i: | |
252b5132 RH |
13748 | ++imm_expr.X_add_number; |
13749 | ||
13750 | do_branch_i: | |
c0ebe874 | 13751 | macro_build (&imm_expr, s, s3, op[0]); |
67c0d1eb | 13752 | macro_build (&offset_expr, s2, "p"); |
252b5132 RH |
13753 | break; |
13754 | ||
13755 | case M_ABS: | |
13756 | expr1.X_add_number = 0; | |
c0ebe874 RS |
13757 | macro_build (&expr1, "slti", "x,8", op[1]); |
13758 | if (op[0] != op[1]) | |
13759 | macro_build (NULL, "move", "y,X", op[0], mips16_to_32_reg_map[op[1]]); | |
252b5132 | 13760 | expr1.X_add_number = 2; |
67c0d1eb | 13761 | macro_build (&expr1, "bteqz", "p"); |
c0ebe874 | 13762 | macro_build (NULL, "neg", "x,w", op[0], op[0]); |
0acfaea6 | 13763 | break; |
252b5132 RH |
13764 | } |
13765 | } | |
13766 | ||
14daeee3 RS |
13767 | /* Look up instruction [START, START + LENGTH) in HASH. Record any extra |
13768 | opcode bits in *OPCODE_EXTRA. */ | |
13769 | ||
13770 | static struct mips_opcode * | |
13771 | mips_lookup_insn (struct hash_control *hash, const char *start, | |
da8bca91 | 13772 | ssize_t length, unsigned int *opcode_extra) |
14daeee3 RS |
13773 | { |
13774 | char *name, *dot, *p; | |
13775 | unsigned int mask, suffix; | |
da8bca91 | 13776 | ssize_t opend; |
14daeee3 RS |
13777 | struct mips_opcode *insn; |
13778 | ||
13779 | /* Make a copy of the instruction so that we can fiddle with it. */ | |
4ec9d7d5 | 13780 | name = xstrndup (start, length); |
14daeee3 RS |
13781 | |
13782 | /* Look up the instruction as-is. */ | |
13783 | insn = (struct mips_opcode *) hash_find (hash, name); | |
ee5734f0 | 13784 | if (insn) |
e1fa0163 | 13785 | goto end; |
14daeee3 RS |
13786 | |
13787 | dot = strchr (name, '.'); | |
13788 | if (dot && dot[1]) | |
13789 | { | |
13790 | /* Try to interpret the text after the dot as a VU0 channel suffix. */ | |
13791 | p = mips_parse_vu0_channels (dot + 1, &mask); | |
13792 | if (*p == 0 && mask != 0) | |
13793 | { | |
13794 | *dot = 0; | |
13795 | insn = (struct mips_opcode *) hash_find (hash, name); | |
13796 | *dot = '.'; | |
13797 | if (insn && (insn->pinfo2 & INSN2_VU0_CHANNEL_SUFFIX) != 0) | |
13798 | { | |
13799 | *opcode_extra |= mask << mips_vu0_channel_mask.lsb; | |
e1fa0163 | 13800 | goto end; |
14daeee3 RS |
13801 | } |
13802 | } | |
13803 | } | |
13804 | ||
13805 | if (mips_opts.micromips) | |
13806 | { | |
13807 | /* See if there's an instruction size override suffix, | |
13808 | either `16' or `32', at the end of the mnemonic proper, | |
13809 | that defines the operation, i.e. before the first `.' | |
13810 | character if any. Strip it and retry. */ | |
13811 | opend = dot != NULL ? dot - name : length; | |
13812 | if (opend >= 3 && name[opend - 2] == '1' && name[opend - 1] == '6') | |
13813 | suffix = 2; | |
13814 | else if (name[opend - 2] == '3' && name[opend - 1] == '2') | |
13815 | suffix = 4; | |
13816 | else | |
13817 | suffix = 0; | |
13818 | if (suffix) | |
13819 | { | |
13820 | memcpy (name + opend - 2, name + opend, length - opend + 1); | |
13821 | insn = (struct mips_opcode *) hash_find (hash, name); | |
ee5734f0 | 13822 | if (insn) |
14daeee3 RS |
13823 | { |
13824 | forced_insn_length = suffix; | |
e1fa0163 | 13825 | goto end; |
14daeee3 RS |
13826 | } |
13827 | } | |
13828 | } | |
13829 | ||
e1fa0163 NC |
13830 | insn = NULL; |
13831 | end: | |
13832 | free (name); | |
13833 | return insn; | |
14daeee3 RS |
13834 | } |
13835 | ||
77bd4346 | 13836 | /* Assemble an instruction into its binary format. If the instruction |
e423441d RS |
13837 | is a macro, set imm_expr and offset_expr to the values associated |
13838 | with "I" and "A" operands respectively. Otherwise store the value | |
13839 | of the relocatable field (if any) in offset_expr. In both cases | |
13840 | set offset_reloc to the relocation operators applied to offset_expr. */ | |
252b5132 RH |
13841 | |
13842 | static void | |
60f20e8b | 13843 | mips_ip (char *str, struct mips_cl_insn *insn) |
252b5132 | 13844 | { |
60f20e8b | 13845 | const struct mips_opcode *first, *past; |
df58fc94 | 13846 | struct hash_control *hash; |
a92713e6 | 13847 | char format; |
14daeee3 | 13848 | size_t end; |
a92713e6 | 13849 | struct mips_operand_token *tokens; |
14daeee3 | 13850 | unsigned int opcode_extra; |
252b5132 | 13851 | |
df58fc94 RS |
13852 | if (mips_opts.micromips) |
13853 | { | |
13854 | hash = micromips_op_hash; | |
13855 | past = µmips_opcodes[bfd_micromips_num_opcodes]; | |
13856 | } | |
13857 | else | |
13858 | { | |
13859 | hash = op_hash; | |
13860 | past = &mips_opcodes[NUMOPCODES]; | |
13861 | } | |
13862 | forced_insn_length = 0; | |
14daeee3 | 13863 | opcode_extra = 0; |
252b5132 | 13864 | |
df58fc94 | 13865 | /* We first try to match an instruction up to a space or to the end. */ |
a40bc9dd RS |
13866 | for (end = 0; str[end] != '\0' && !ISSPACE (str[end]); end++) |
13867 | continue; | |
bdaaa2e1 | 13868 | |
60f20e8b RS |
13869 | first = mips_lookup_insn (hash, str, end, &opcode_extra); |
13870 | if (first == NULL) | |
252b5132 | 13871 | { |
1661c76c | 13872 | set_insn_error (0, _("unrecognized opcode")); |
a40bc9dd | 13873 | return; |
252b5132 RH |
13874 | } |
13875 | ||
60f20e8b | 13876 | if (strcmp (first->name, "li.s") == 0) |
a92713e6 | 13877 | format = 'f'; |
60f20e8b | 13878 | else if (strcmp (first->name, "li.d") == 0) |
a92713e6 RS |
13879 | format = 'd'; |
13880 | else | |
13881 | format = 0; | |
13882 | tokens = mips_parse_arguments (str + end, format); | |
13883 | if (!tokens) | |
13884 | return; | |
13885 | ||
60f20e8b RS |
13886 | if (!match_insns (insn, first, past, tokens, opcode_extra, FALSE) |
13887 | && !match_insns (insn, first, past, tokens, opcode_extra, TRUE)) | |
1661c76c | 13888 | set_insn_error (0, _("invalid operands")); |
df58fc94 | 13889 | |
e3de51ce | 13890 | obstack_free (&mips_operand_tokens, tokens); |
252b5132 RH |
13891 | } |
13892 | ||
77bd4346 RS |
13893 | /* As for mips_ip, but used when assembling MIPS16 code. |
13894 | Also set forced_insn_length to the resulting instruction size in | |
13895 | bytes if the user explicitly requested a small or extended instruction. */ | |
252b5132 RH |
13896 | |
13897 | static void | |
60f20e8b | 13898 | mips16_ip (char *str, struct mips_cl_insn *insn) |
252b5132 | 13899 | { |
1a00e612 | 13900 | char *end, *s, c; |
60f20e8b | 13901 | struct mips_opcode *first; |
a92713e6 | 13902 | struct mips_operand_token *tokens; |
3fb49709 | 13903 | unsigned int l; |
252b5132 | 13904 | |
3882b010 | 13905 | for (s = str; ISLOWER (*s); ++s) |
252b5132 | 13906 | ; |
1a00e612 RS |
13907 | end = s; |
13908 | c = *end; | |
3fb49709 MR |
13909 | |
13910 | l = 0; | |
1a00e612 | 13911 | switch (c) |
252b5132 RH |
13912 | { |
13913 | case '\0': | |
13914 | break; | |
13915 | ||
13916 | case ' ': | |
1a00e612 | 13917 | s++; |
252b5132 RH |
13918 | break; |
13919 | ||
13920 | case '.': | |
3fb49709 MR |
13921 | s++; |
13922 | if (*s == 't') | |
252b5132 | 13923 | { |
3fb49709 MR |
13924 | l = 2; |
13925 | s++; | |
252b5132 | 13926 | } |
3fb49709 | 13927 | else if (*s == 'e') |
252b5132 | 13928 | { |
3fb49709 MR |
13929 | l = 4; |
13930 | s++; | |
252b5132 | 13931 | } |
3fb49709 MR |
13932 | if (*s == '\0') |
13933 | break; | |
13934 | else if (*s++ == ' ') | |
13935 | break; | |
252b5132 RH |
13936 | /* Fall through. */ |
13937 | default: | |
1661c76c | 13938 | set_insn_error (0, _("unrecognized opcode")); |
252b5132 RH |
13939 | return; |
13940 | } | |
3fb49709 | 13941 | forced_insn_length = l; |
252b5132 | 13942 | |
1a00e612 | 13943 | *end = 0; |
60f20e8b | 13944 | first = (struct mips_opcode *) hash_find (mips16_op_hash, str); |
1a00e612 RS |
13945 | *end = c; |
13946 | ||
60f20e8b | 13947 | if (!first) |
252b5132 | 13948 | { |
1661c76c | 13949 | set_insn_error (0, _("unrecognized opcode")); |
252b5132 RH |
13950 | return; |
13951 | } | |
13952 | ||
a92713e6 RS |
13953 | tokens = mips_parse_arguments (s, 0); |
13954 | if (!tokens) | |
13955 | return; | |
13956 | ||
60f20e8b | 13957 | if (!match_mips16_insns (insn, first, tokens)) |
1661c76c | 13958 | set_insn_error (0, _("invalid operands")); |
252b5132 | 13959 | |
e3de51ce | 13960 | obstack_free (&mips_operand_tokens, tokens); |
252b5132 RH |
13961 | } |
13962 | ||
b886a2ab RS |
13963 | /* Marshal immediate value VAL for an extended MIPS16 instruction. |
13964 | NBITS is the number of significant bits in VAL. */ | |
13965 | ||
13966 | static unsigned long | |
13967 | mips16_immed_extend (offsetT val, unsigned int nbits) | |
13968 | { | |
13969 | int extval; | |
13970 | if (nbits == 16) | |
13971 | { | |
13972 | extval = ((val >> 11) & 0x1f) | (val & 0x7e0); | |
13973 | val &= 0x1f; | |
13974 | } | |
13975 | else if (nbits == 15) | |
13976 | { | |
13977 | extval = ((val >> 11) & 0xf) | (val & 0x7f0); | |
13978 | val &= 0xf; | |
13979 | } | |
13980 | else | |
13981 | { | |
13982 | extval = ((val & 0x1f) << 6) | (val & 0x20); | |
13983 | val = 0; | |
13984 | } | |
13985 | return (extval << 16) | val; | |
13986 | } | |
13987 | ||
3ccad066 RS |
13988 | /* Like decode_mips16_operand, but require the operand to be defined and |
13989 | require it to be an integer. */ | |
13990 | ||
13991 | static const struct mips_int_operand * | |
13992 | mips16_immed_operand (int type, bfd_boolean extended_p) | |
13993 | { | |
13994 | const struct mips_operand *operand; | |
13995 | ||
13996 | operand = decode_mips16_operand (type, extended_p); | |
13997 | if (!operand || (operand->type != OP_INT && operand->type != OP_PCREL)) | |
13998 | abort (); | |
13999 | return (const struct mips_int_operand *) operand; | |
14000 | } | |
14001 | ||
14002 | /* Return true if SVAL fits OPERAND. RELOC is as for mips16_immed. */ | |
14003 | ||
14004 | static bfd_boolean | |
14005 | mips16_immed_in_range_p (const struct mips_int_operand *operand, | |
14006 | bfd_reloc_code_real_type reloc, offsetT sval) | |
14007 | { | |
14008 | int min_val, max_val; | |
14009 | ||
14010 | min_val = mips_int_operand_min (operand); | |
14011 | max_val = mips_int_operand_max (operand); | |
14012 | if (reloc != BFD_RELOC_UNUSED) | |
14013 | { | |
14014 | if (min_val < 0) | |
14015 | sval = SEXT_16BIT (sval); | |
14016 | else | |
14017 | sval &= 0xffff; | |
14018 | } | |
14019 | ||
14020 | return (sval >= min_val | |
14021 | && sval <= max_val | |
14022 | && (sval & ((1 << operand->shift) - 1)) == 0); | |
14023 | } | |
14024 | ||
5c04167a RS |
14025 | /* Install immediate value VAL into MIPS16 instruction *INSN, |
14026 | extending it if necessary. The instruction in *INSN may | |
14027 | already be extended. | |
14028 | ||
43c0598f RS |
14029 | RELOC is the relocation that produced VAL, or BFD_RELOC_UNUSED |
14030 | if none. In the former case, VAL is a 16-bit number with no | |
14031 | defined signedness. | |
14032 | ||
14033 | TYPE is the type of the immediate field. USER_INSN_LENGTH | |
14034 | is the length that the user requested, or 0 if none. */ | |
252b5132 RH |
14035 | |
14036 | static void | |
3b4dbbbf | 14037 | mips16_immed (const char *file, unsigned int line, int type, |
43c0598f | 14038 | bfd_reloc_code_real_type reloc, offsetT val, |
5c04167a | 14039 | unsigned int user_insn_length, unsigned long *insn) |
252b5132 | 14040 | { |
3ccad066 RS |
14041 | const struct mips_int_operand *operand; |
14042 | unsigned int uval, length; | |
252b5132 | 14043 | |
3ccad066 RS |
14044 | operand = mips16_immed_operand (type, FALSE); |
14045 | if (!mips16_immed_in_range_p (operand, reloc, val)) | |
5c04167a RS |
14046 | { |
14047 | /* We need an extended instruction. */ | |
14048 | if (user_insn_length == 2) | |
14049 | as_bad_where (file, line, _("invalid unextended operand value")); | |
14050 | else | |
14051 | *insn |= MIPS16_EXTEND; | |
14052 | } | |
14053 | else if (user_insn_length == 4) | |
14054 | { | |
14055 | /* The operand doesn't force an unextended instruction to be extended. | |
14056 | Warn if the user wanted an extended instruction anyway. */ | |
14057 | *insn |= MIPS16_EXTEND; | |
14058 | as_warn_where (file, line, | |
14059 | _("extended operand requested but not required")); | |
14060 | } | |
252b5132 | 14061 | |
3ccad066 RS |
14062 | length = mips16_opcode_length (*insn); |
14063 | if (length == 4) | |
252b5132 | 14064 | { |
3ccad066 RS |
14065 | operand = mips16_immed_operand (type, TRUE); |
14066 | if (!mips16_immed_in_range_p (operand, reloc, val)) | |
14067 | as_bad_where (file, line, | |
14068 | _("operand value out of range for instruction")); | |
252b5132 | 14069 | } |
3ccad066 | 14070 | uval = ((unsigned int) val >> operand->shift) - operand->bias; |
bdd15286 | 14071 | if (length == 2 || operand->root.lsb != 0) |
3ccad066 | 14072 | *insn = mips_insert_operand (&operand->root, *insn, uval); |
252b5132 | 14073 | else |
3ccad066 | 14074 | *insn |= mips16_immed_extend (uval, operand->root.size); |
252b5132 RH |
14075 | } |
14076 | \f | |
d6f16593 | 14077 | struct percent_op_match |
ad8d3bb3 | 14078 | { |
5e0116d5 RS |
14079 | const char *str; |
14080 | bfd_reloc_code_real_type reloc; | |
d6f16593 MR |
14081 | }; |
14082 | ||
14083 | static const struct percent_op_match mips_percent_op[] = | |
ad8d3bb3 | 14084 | { |
5e0116d5 | 14085 | {"%lo", BFD_RELOC_LO16}, |
5e0116d5 RS |
14086 | {"%call_hi", BFD_RELOC_MIPS_CALL_HI16}, |
14087 | {"%call_lo", BFD_RELOC_MIPS_CALL_LO16}, | |
14088 | {"%call16", BFD_RELOC_MIPS_CALL16}, | |
14089 | {"%got_disp", BFD_RELOC_MIPS_GOT_DISP}, | |
14090 | {"%got_page", BFD_RELOC_MIPS_GOT_PAGE}, | |
14091 | {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST}, | |
14092 | {"%got_hi", BFD_RELOC_MIPS_GOT_HI16}, | |
14093 | {"%got_lo", BFD_RELOC_MIPS_GOT_LO16}, | |
14094 | {"%got", BFD_RELOC_MIPS_GOT16}, | |
14095 | {"%gp_rel", BFD_RELOC_GPREL16}, | |
be3f1006 | 14096 | {"%gprel", BFD_RELOC_GPREL16}, |
5e0116d5 RS |
14097 | {"%half", BFD_RELOC_16}, |
14098 | {"%highest", BFD_RELOC_MIPS_HIGHEST}, | |
14099 | {"%higher", BFD_RELOC_MIPS_HIGHER}, | |
14100 | {"%neg", BFD_RELOC_MIPS_SUB}, | |
3f98094e DJ |
14101 | {"%tlsgd", BFD_RELOC_MIPS_TLS_GD}, |
14102 | {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM}, | |
14103 | {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16}, | |
14104 | {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16}, | |
14105 | {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16}, | |
14106 | {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16}, | |
14107 | {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL}, | |
7361da2c AB |
14108 | {"%hi", BFD_RELOC_HI16_S}, |
14109 | {"%pcrel_hi", BFD_RELOC_HI16_S_PCREL}, | |
14110 | {"%pcrel_lo", BFD_RELOC_LO16_PCREL} | |
ad8d3bb3 TS |
14111 | }; |
14112 | ||
d6f16593 MR |
14113 | static const struct percent_op_match mips16_percent_op[] = |
14114 | { | |
14115 | {"%lo", BFD_RELOC_MIPS16_LO16}, | |
be3f1006 | 14116 | {"%gp_rel", BFD_RELOC_MIPS16_GPREL}, |
d6f16593 | 14117 | {"%gprel", BFD_RELOC_MIPS16_GPREL}, |
738e5348 RS |
14118 | {"%got", BFD_RELOC_MIPS16_GOT16}, |
14119 | {"%call16", BFD_RELOC_MIPS16_CALL16}, | |
d0f13682 CLT |
14120 | {"%hi", BFD_RELOC_MIPS16_HI16_S}, |
14121 | {"%tlsgd", BFD_RELOC_MIPS16_TLS_GD}, | |
14122 | {"%tlsldm", BFD_RELOC_MIPS16_TLS_LDM}, | |
14123 | {"%dtprel_hi", BFD_RELOC_MIPS16_TLS_DTPREL_HI16}, | |
14124 | {"%dtprel_lo", BFD_RELOC_MIPS16_TLS_DTPREL_LO16}, | |
14125 | {"%tprel_hi", BFD_RELOC_MIPS16_TLS_TPREL_HI16}, | |
14126 | {"%tprel_lo", BFD_RELOC_MIPS16_TLS_TPREL_LO16}, | |
14127 | {"%gottprel", BFD_RELOC_MIPS16_TLS_GOTTPREL} | |
d6f16593 MR |
14128 | }; |
14129 | ||
252b5132 | 14130 | |
5e0116d5 RS |
14131 | /* Return true if *STR points to a relocation operator. When returning true, |
14132 | move *STR over the operator and store its relocation code in *RELOC. | |
14133 | Leave both *STR and *RELOC alone when returning false. */ | |
14134 | ||
14135 | static bfd_boolean | |
17a2f251 | 14136 | parse_relocation (char **str, bfd_reloc_code_real_type *reloc) |
252b5132 | 14137 | { |
d6f16593 MR |
14138 | const struct percent_op_match *percent_op; |
14139 | size_t limit, i; | |
14140 | ||
14141 | if (mips_opts.mips16) | |
14142 | { | |
14143 | percent_op = mips16_percent_op; | |
14144 | limit = ARRAY_SIZE (mips16_percent_op); | |
14145 | } | |
14146 | else | |
14147 | { | |
14148 | percent_op = mips_percent_op; | |
14149 | limit = ARRAY_SIZE (mips_percent_op); | |
14150 | } | |
76b3015f | 14151 | |
d6f16593 | 14152 | for (i = 0; i < limit; i++) |
5e0116d5 | 14153 | if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0) |
394f9b3a | 14154 | { |
3f98094e DJ |
14155 | int len = strlen (percent_op[i].str); |
14156 | ||
14157 | if (!ISSPACE ((*str)[len]) && (*str)[len] != '(') | |
14158 | continue; | |
14159 | ||
5e0116d5 RS |
14160 | *str += strlen (percent_op[i].str); |
14161 | *reloc = percent_op[i].reloc; | |
394f9b3a | 14162 | |
5e0116d5 RS |
14163 | /* Check whether the output BFD supports this relocation. |
14164 | If not, issue an error and fall back on something safe. */ | |
14165 | if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc)) | |
394f9b3a | 14166 | { |
20203fb9 | 14167 | as_bad (_("relocation %s isn't supported by the current ABI"), |
5e0116d5 | 14168 | percent_op[i].str); |
01a3f561 | 14169 | *reloc = BFD_RELOC_UNUSED; |
394f9b3a | 14170 | } |
5e0116d5 | 14171 | return TRUE; |
394f9b3a | 14172 | } |
5e0116d5 | 14173 | return FALSE; |
394f9b3a | 14174 | } |
ad8d3bb3 | 14175 | |
ad8d3bb3 | 14176 | |
5e0116d5 RS |
14177 | /* Parse string STR as a 16-bit relocatable operand. Store the |
14178 | expression in *EP and the relocations in the array starting | |
14179 | at RELOC. Return the number of relocation operators used. | |
ad8d3bb3 | 14180 | |
01a3f561 | 14181 | On exit, EXPR_END points to the first character after the expression. */ |
ad8d3bb3 | 14182 | |
5e0116d5 | 14183 | static size_t |
17a2f251 TS |
14184 | my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc, |
14185 | char *str) | |
ad8d3bb3 | 14186 | { |
5e0116d5 RS |
14187 | bfd_reloc_code_real_type reversed_reloc[3]; |
14188 | size_t reloc_index, i; | |
09b8f35a RS |
14189 | int crux_depth, str_depth; |
14190 | char *crux; | |
5e0116d5 RS |
14191 | |
14192 | /* Search for the start of the main expression, recoding relocations | |
09b8f35a RS |
14193 | in REVERSED_RELOC. End the loop with CRUX pointing to the start |
14194 | of the main expression and with CRUX_DEPTH containing the number | |
14195 | of open brackets at that point. */ | |
14196 | reloc_index = -1; | |
14197 | str_depth = 0; | |
14198 | do | |
fb1b3232 | 14199 | { |
09b8f35a RS |
14200 | reloc_index++; |
14201 | crux = str; | |
14202 | crux_depth = str_depth; | |
14203 | ||
14204 | /* Skip over whitespace and brackets, keeping count of the number | |
14205 | of brackets. */ | |
14206 | while (*str == ' ' || *str == '\t' || *str == '(') | |
14207 | if (*str++ == '(') | |
14208 | str_depth++; | |
5e0116d5 | 14209 | } |
09b8f35a RS |
14210 | while (*str == '%' |
14211 | && reloc_index < (HAVE_NEWABI ? 3 : 1) | |
14212 | && parse_relocation (&str, &reversed_reloc[reloc_index])); | |
ad8d3bb3 | 14213 | |
09b8f35a | 14214 | my_getExpression (ep, crux); |
5e0116d5 | 14215 | str = expr_end; |
394f9b3a | 14216 | |
5e0116d5 | 14217 | /* Match every open bracket. */ |
09b8f35a | 14218 | while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t')) |
5e0116d5 | 14219 | if (*str++ == ')') |
09b8f35a | 14220 | crux_depth--; |
394f9b3a | 14221 | |
09b8f35a | 14222 | if (crux_depth > 0) |
20203fb9 | 14223 | as_bad (_("unclosed '('")); |
394f9b3a | 14224 | |
5e0116d5 | 14225 | expr_end = str; |
252b5132 | 14226 | |
01a3f561 | 14227 | if (reloc_index != 0) |
64bdfcaf RS |
14228 | { |
14229 | prev_reloc_op_frag = frag_now; | |
14230 | for (i = 0; i < reloc_index; i++) | |
14231 | reloc[i] = reversed_reloc[reloc_index - 1 - i]; | |
14232 | } | |
fb1b3232 | 14233 | |
5e0116d5 | 14234 | return reloc_index; |
252b5132 RH |
14235 | } |
14236 | ||
14237 | static void | |
17a2f251 | 14238 | my_getExpression (expressionS *ep, char *str) |
252b5132 RH |
14239 | { |
14240 | char *save_in; | |
14241 | ||
14242 | save_in = input_line_pointer; | |
14243 | input_line_pointer = str; | |
14244 | expression (ep); | |
14245 | expr_end = input_line_pointer; | |
14246 | input_line_pointer = save_in; | |
252b5132 RH |
14247 | } |
14248 | ||
6d4af3c2 | 14249 | const char * |
17a2f251 | 14250 | md_atof (int type, char *litP, int *sizeP) |
252b5132 | 14251 | { |
499ac353 | 14252 | return ieee_md_atof (type, litP, sizeP, target_big_endian); |
252b5132 RH |
14253 | } |
14254 | ||
14255 | void | |
17a2f251 | 14256 | md_number_to_chars (char *buf, valueT val, int n) |
252b5132 RH |
14257 | { |
14258 | if (target_big_endian) | |
14259 | number_to_chars_bigendian (buf, val, n); | |
14260 | else | |
14261 | number_to_chars_littleendian (buf, val, n); | |
14262 | } | |
14263 | \f | |
e013f690 TS |
14264 | static int support_64bit_objects(void) |
14265 | { | |
14266 | const char **list, **l; | |
aa3d8fdf | 14267 | int yes; |
e013f690 TS |
14268 | |
14269 | list = bfd_target_list (); | |
14270 | for (l = list; *l != NULL; l++) | |
aeffff67 RS |
14271 | if (strcmp (*l, ELF_TARGET ("elf64-", "big")) == 0 |
14272 | || strcmp (*l, ELF_TARGET ("elf64-", "little")) == 0) | |
e013f690 | 14273 | break; |
aa3d8fdf | 14274 | yes = (*l != NULL); |
e013f690 | 14275 | free (list); |
aa3d8fdf | 14276 | return yes; |
e013f690 TS |
14277 | } |
14278 | ||
316f5878 RS |
14279 | /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to |
14280 | NEW_VALUE. Warn if another value was already specified. Note: | |
14281 | we have to defer parsing the -march and -mtune arguments in order | |
14282 | to handle 'from-abi' correctly, since the ABI might be specified | |
14283 | in a later argument. */ | |
14284 | ||
14285 | static void | |
17a2f251 | 14286 | mips_set_option_string (const char **string_ptr, const char *new_value) |
316f5878 RS |
14287 | { |
14288 | if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0) | |
1661c76c | 14289 | as_warn (_("a different %s was already specified, is now %s"), |
316f5878 RS |
14290 | string_ptr == &mips_arch_string ? "-march" : "-mtune", |
14291 | new_value); | |
14292 | ||
14293 | *string_ptr = new_value; | |
14294 | } | |
14295 | ||
252b5132 | 14296 | int |
17b9d67d | 14297 | md_parse_option (int c, const char *arg) |
252b5132 | 14298 | { |
c6278170 RS |
14299 | unsigned int i; |
14300 | ||
14301 | for (i = 0; i < ARRAY_SIZE (mips_ases); i++) | |
14302 | if (c == mips_ases[i].option_on || c == mips_ases[i].option_off) | |
14303 | { | |
919731af | 14304 | file_ase_explicit |= mips_set_ase (&mips_ases[i], &file_mips_opts, |
c6278170 RS |
14305 | c == mips_ases[i].option_on); |
14306 | return 1; | |
14307 | } | |
14308 | ||
252b5132 RH |
14309 | switch (c) |
14310 | { | |
119d663a NC |
14311 | case OPTION_CONSTRUCT_FLOATS: |
14312 | mips_disable_float_construction = 0; | |
14313 | break; | |
bdaaa2e1 | 14314 | |
119d663a NC |
14315 | case OPTION_NO_CONSTRUCT_FLOATS: |
14316 | mips_disable_float_construction = 1; | |
14317 | break; | |
bdaaa2e1 | 14318 | |
252b5132 RH |
14319 | case OPTION_TRAP: |
14320 | mips_trap = 1; | |
14321 | break; | |
14322 | ||
14323 | case OPTION_BREAK: | |
14324 | mips_trap = 0; | |
14325 | break; | |
14326 | ||
14327 | case OPTION_EB: | |
14328 | target_big_endian = 1; | |
14329 | break; | |
14330 | ||
14331 | case OPTION_EL: | |
14332 | target_big_endian = 0; | |
14333 | break; | |
14334 | ||
14335 | case 'O': | |
4ffff32f TS |
14336 | if (arg == NULL) |
14337 | mips_optimize = 1; | |
14338 | else if (arg[0] == '0') | |
14339 | mips_optimize = 0; | |
14340 | else if (arg[0] == '1') | |
252b5132 RH |
14341 | mips_optimize = 1; |
14342 | else | |
14343 | mips_optimize = 2; | |
14344 | break; | |
14345 | ||
14346 | case 'g': | |
14347 | if (arg == NULL) | |
14348 | mips_debug = 2; | |
14349 | else | |
14350 | mips_debug = atoi (arg); | |
252b5132 RH |
14351 | break; |
14352 | ||
14353 | case OPTION_MIPS1: | |
0b35dfee | 14354 | file_mips_opts.isa = ISA_MIPS1; |
252b5132 RH |
14355 | break; |
14356 | ||
14357 | case OPTION_MIPS2: | |
0b35dfee | 14358 | file_mips_opts.isa = ISA_MIPS2; |
252b5132 RH |
14359 | break; |
14360 | ||
14361 | case OPTION_MIPS3: | |
0b35dfee | 14362 | file_mips_opts.isa = ISA_MIPS3; |
252b5132 RH |
14363 | break; |
14364 | ||
14365 | case OPTION_MIPS4: | |
0b35dfee | 14366 | file_mips_opts.isa = ISA_MIPS4; |
e7af610e NC |
14367 | break; |
14368 | ||
84ea6cf2 | 14369 | case OPTION_MIPS5: |
0b35dfee | 14370 | file_mips_opts.isa = ISA_MIPS5; |
84ea6cf2 NC |
14371 | break; |
14372 | ||
e7af610e | 14373 | case OPTION_MIPS32: |
0b35dfee | 14374 | file_mips_opts.isa = ISA_MIPS32; |
252b5132 RH |
14375 | break; |
14376 | ||
af7ee8bf | 14377 | case OPTION_MIPS32R2: |
0b35dfee | 14378 | file_mips_opts.isa = ISA_MIPS32R2; |
af7ee8bf CD |
14379 | break; |
14380 | ||
ae52f483 | 14381 | case OPTION_MIPS32R3: |
0ae19f05 | 14382 | file_mips_opts.isa = ISA_MIPS32R3; |
ae52f483 AB |
14383 | break; |
14384 | ||
14385 | case OPTION_MIPS32R5: | |
0ae19f05 | 14386 | file_mips_opts.isa = ISA_MIPS32R5; |
ae52f483 AB |
14387 | break; |
14388 | ||
7361da2c AB |
14389 | case OPTION_MIPS32R6: |
14390 | file_mips_opts.isa = ISA_MIPS32R6; | |
14391 | break; | |
14392 | ||
5f74bc13 | 14393 | case OPTION_MIPS64R2: |
0b35dfee | 14394 | file_mips_opts.isa = ISA_MIPS64R2; |
5f74bc13 CD |
14395 | break; |
14396 | ||
ae52f483 | 14397 | case OPTION_MIPS64R3: |
0ae19f05 | 14398 | file_mips_opts.isa = ISA_MIPS64R3; |
ae52f483 AB |
14399 | break; |
14400 | ||
14401 | case OPTION_MIPS64R5: | |
0ae19f05 | 14402 | file_mips_opts.isa = ISA_MIPS64R5; |
ae52f483 AB |
14403 | break; |
14404 | ||
7361da2c AB |
14405 | case OPTION_MIPS64R6: |
14406 | file_mips_opts.isa = ISA_MIPS64R6; | |
14407 | break; | |
14408 | ||
84ea6cf2 | 14409 | case OPTION_MIPS64: |
0b35dfee | 14410 | file_mips_opts.isa = ISA_MIPS64; |
84ea6cf2 NC |
14411 | break; |
14412 | ||
ec68c924 | 14413 | case OPTION_MTUNE: |
316f5878 RS |
14414 | mips_set_option_string (&mips_tune_string, arg); |
14415 | break; | |
ec68c924 | 14416 | |
316f5878 RS |
14417 | case OPTION_MARCH: |
14418 | mips_set_option_string (&mips_arch_string, arg); | |
252b5132 RH |
14419 | break; |
14420 | ||
14421 | case OPTION_M4650: | |
316f5878 RS |
14422 | mips_set_option_string (&mips_arch_string, "4650"); |
14423 | mips_set_option_string (&mips_tune_string, "4650"); | |
252b5132 RH |
14424 | break; |
14425 | ||
14426 | case OPTION_NO_M4650: | |
14427 | break; | |
14428 | ||
14429 | case OPTION_M4010: | |
316f5878 RS |
14430 | mips_set_option_string (&mips_arch_string, "4010"); |
14431 | mips_set_option_string (&mips_tune_string, "4010"); | |
252b5132 RH |
14432 | break; |
14433 | ||
14434 | case OPTION_NO_M4010: | |
14435 | break; | |
14436 | ||
14437 | case OPTION_M4100: | |
316f5878 RS |
14438 | mips_set_option_string (&mips_arch_string, "4100"); |
14439 | mips_set_option_string (&mips_tune_string, "4100"); | |
252b5132 RH |
14440 | break; |
14441 | ||
14442 | case OPTION_NO_M4100: | |
14443 | break; | |
14444 | ||
252b5132 | 14445 | case OPTION_M3900: |
316f5878 RS |
14446 | mips_set_option_string (&mips_arch_string, "3900"); |
14447 | mips_set_option_string (&mips_tune_string, "3900"); | |
252b5132 | 14448 | break; |
bdaaa2e1 | 14449 | |
252b5132 RH |
14450 | case OPTION_NO_M3900: |
14451 | break; | |
14452 | ||
df58fc94 | 14453 | case OPTION_MICROMIPS: |
919731af | 14454 | if (file_mips_opts.mips16 == 1) |
df58fc94 RS |
14455 | { |
14456 | as_bad (_("-mmicromips cannot be used with -mips16")); | |
14457 | return 0; | |
14458 | } | |
919731af | 14459 | file_mips_opts.micromips = 1; |
df58fc94 RS |
14460 | mips_no_prev_insn (); |
14461 | break; | |
14462 | ||
14463 | case OPTION_NO_MICROMIPS: | |
919731af | 14464 | file_mips_opts.micromips = 0; |
df58fc94 RS |
14465 | mips_no_prev_insn (); |
14466 | break; | |
14467 | ||
252b5132 | 14468 | case OPTION_MIPS16: |
919731af | 14469 | if (file_mips_opts.micromips == 1) |
df58fc94 RS |
14470 | { |
14471 | as_bad (_("-mips16 cannot be used with -micromips")); | |
14472 | return 0; | |
14473 | } | |
919731af | 14474 | file_mips_opts.mips16 = 1; |
7d10b47d | 14475 | mips_no_prev_insn (); |
252b5132 RH |
14476 | break; |
14477 | ||
14478 | case OPTION_NO_MIPS16: | |
919731af | 14479 | file_mips_opts.mips16 = 0; |
7d10b47d | 14480 | mips_no_prev_insn (); |
252b5132 RH |
14481 | break; |
14482 | ||
6a32d874 CM |
14483 | case OPTION_FIX_24K: |
14484 | mips_fix_24k = 1; | |
14485 | break; | |
14486 | ||
14487 | case OPTION_NO_FIX_24K: | |
14488 | mips_fix_24k = 0; | |
14489 | break; | |
14490 | ||
a8d14a88 CM |
14491 | case OPTION_FIX_RM7000: |
14492 | mips_fix_rm7000 = 1; | |
14493 | break; | |
14494 | ||
14495 | case OPTION_NO_FIX_RM7000: | |
14496 | mips_fix_rm7000 = 0; | |
14497 | break; | |
14498 | ||
c67a084a NC |
14499 | case OPTION_FIX_LOONGSON2F_JUMP: |
14500 | mips_fix_loongson2f_jump = TRUE; | |
14501 | break; | |
14502 | ||
14503 | case OPTION_NO_FIX_LOONGSON2F_JUMP: | |
14504 | mips_fix_loongson2f_jump = FALSE; | |
14505 | break; | |
14506 | ||
14507 | case OPTION_FIX_LOONGSON2F_NOP: | |
14508 | mips_fix_loongson2f_nop = TRUE; | |
14509 | break; | |
14510 | ||
14511 | case OPTION_NO_FIX_LOONGSON2F_NOP: | |
14512 | mips_fix_loongson2f_nop = FALSE; | |
14513 | break; | |
14514 | ||
d766e8ec RS |
14515 | case OPTION_FIX_VR4120: |
14516 | mips_fix_vr4120 = 1; | |
60b63b72 RS |
14517 | break; |
14518 | ||
d766e8ec RS |
14519 | case OPTION_NO_FIX_VR4120: |
14520 | mips_fix_vr4120 = 0; | |
60b63b72 RS |
14521 | break; |
14522 | ||
7d8e00cf RS |
14523 | case OPTION_FIX_VR4130: |
14524 | mips_fix_vr4130 = 1; | |
14525 | break; | |
14526 | ||
14527 | case OPTION_NO_FIX_VR4130: | |
14528 | mips_fix_vr4130 = 0; | |
14529 | break; | |
14530 | ||
d954098f DD |
14531 | case OPTION_FIX_CN63XXP1: |
14532 | mips_fix_cn63xxp1 = TRUE; | |
14533 | break; | |
14534 | ||
14535 | case OPTION_NO_FIX_CN63XXP1: | |
14536 | mips_fix_cn63xxp1 = FALSE; | |
14537 | break; | |
14538 | ||
4a6a3df4 AO |
14539 | case OPTION_RELAX_BRANCH: |
14540 | mips_relax_branch = 1; | |
14541 | break; | |
14542 | ||
14543 | case OPTION_NO_RELAX_BRANCH: | |
14544 | mips_relax_branch = 0; | |
14545 | break; | |
14546 | ||
8b10b0b3 MR |
14547 | case OPTION_IGNORE_BRANCH_ISA: |
14548 | mips_ignore_branch_isa = TRUE; | |
14549 | break; | |
14550 | ||
14551 | case OPTION_NO_IGNORE_BRANCH_ISA: | |
14552 | mips_ignore_branch_isa = FALSE; | |
14553 | break; | |
14554 | ||
833794fc | 14555 | case OPTION_INSN32: |
919731af | 14556 | file_mips_opts.insn32 = TRUE; |
833794fc MR |
14557 | break; |
14558 | ||
14559 | case OPTION_NO_INSN32: | |
919731af | 14560 | file_mips_opts.insn32 = FALSE; |
833794fc MR |
14561 | break; |
14562 | ||
aa6975fb ILT |
14563 | case OPTION_MSHARED: |
14564 | mips_in_shared = TRUE; | |
14565 | break; | |
14566 | ||
14567 | case OPTION_MNO_SHARED: | |
14568 | mips_in_shared = FALSE; | |
14569 | break; | |
14570 | ||
aed1a261 | 14571 | case OPTION_MSYM32: |
919731af | 14572 | file_mips_opts.sym32 = TRUE; |
aed1a261 RS |
14573 | break; |
14574 | ||
14575 | case OPTION_MNO_SYM32: | |
919731af | 14576 | file_mips_opts.sym32 = FALSE; |
aed1a261 RS |
14577 | break; |
14578 | ||
252b5132 RH |
14579 | /* When generating ELF code, we permit -KPIC and -call_shared to |
14580 | select SVR4_PIC, and -non_shared to select no PIC. This is | |
14581 | intended to be compatible with Irix 5. */ | |
14582 | case OPTION_CALL_SHARED: | |
252b5132 | 14583 | mips_pic = SVR4_PIC; |
143d77c5 | 14584 | mips_abicalls = TRUE; |
252b5132 RH |
14585 | break; |
14586 | ||
861fb55a | 14587 | case OPTION_CALL_NONPIC: |
861fb55a DJ |
14588 | mips_pic = NO_PIC; |
14589 | mips_abicalls = TRUE; | |
14590 | break; | |
14591 | ||
252b5132 | 14592 | case OPTION_NON_SHARED: |
252b5132 | 14593 | mips_pic = NO_PIC; |
143d77c5 | 14594 | mips_abicalls = FALSE; |
252b5132 RH |
14595 | break; |
14596 | ||
44075ae2 TS |
14597 | /* The -xgot option tells the assembler to use 32 bit offsets |
14598 | when accessing the got in SVR4_PIC mode. It is for Irix | |
252b5132 RH |
14599 | compatibility. */ |
14600 | case OPTION_XGOT: | |
14601 | mips_big_got = 1; | |
14602 | break; | |
14603 | ||
14604 | case 'G': | |
6caf9ef4 TS |
14605 | g_switch_value = atoi (arg); |
14606 | g_switch_seen = 1; | |
252b5132 RH |
14607 | break; |
14608 | ||
34ba82a8 TS |
14609 | /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32 |
14610 | and -mabi=64. */ | |
252b5132 | 14611 | case OPTION_32: |
f3ded42a | 14612 | mips_abi = O32_ABI; |
252b5132 RH |
14613 | break; |
14614 | ||
e013f690 | 14615 | case OPTION_N32: |
316f5878 | 14616 | mips_abi = N32_ABI; |
e013f690 | 14617 | break; |
252b5132 | 14618 | |
e013f690 | 14619 | case OPTION_64: |
316f5878 | 14620 | mips_abi = N64_ABI; |
f43abd2b | 14621 | if (!support_64bit_objects()) |
1661c76c | 14622 | as_fatal (_("no compiled in support for 64 bit object file format")); |
252b5132 RH |
14623 | break; |
14624 | ||
c97ef257 | 14625 | case OPTION_GP32: |
bad1aba3 | 14626 | file_mips_opts.gp = 32; |
c97ef257 AH |
14627 | break; |
14628 | ||
14629 | case OPTION_GP64: | |
bad1aba3 | 14630 | file_mips_opts.gp = 64; |
c97ef257 | 14631 | break; |
252b5132 | 14632 | |
ca4e0257 | 14633 | case OPTION_FP32: |
0b35dfee | 14634 | file_mips_opts.fp = 32; |
316f5878 RS |
14635 | break; |
14636 | ||
351cdf24 MF |
14637 | case OPTION_FPXX: |
14638 | file_mips_opts.fp = 0; | |
14639 | break; | |
14640 | ||
316f5878 | 14641 | case OPTION_FP64: |
0b35dfee | 14642 | file_mips_opts.fp = 64; |
ca4e0257 RS |
14643 | break; |
14644 | ||
351cdf24 MF |
14645 | case OPTION_ODD_SPREG: |
14646 | file_mips_opts.oddspreg = 1; | |
14647 | break; | |
14648 | ||
14649 | case OPTION_NO_ODD_SPREG: | |
14650 | file_mips_opts.oddspreg = 0; | |
14651 | break; | |
14652 | ||
037b32b9 | 14653 | case OPTION_SINGLE_FLOAT: |
0b35dfee | 14654 | file_mips_opts.single_float = 1; |
037b32b9 AN |
14655 | break; |
14656 | ||
14657 | case OPTION_DOUBLE_FLOAT: | |
0b35dfee | 14658 | file_mips_opts.single_float = 0; |
037b32b9 AN |
14659 | break; |
14660 | ||
14661 | case OPTION_SOFT_FLOAT: | |
0b35dfee | 14662 | file_mips_opts.soft_float = 1; |
037b32b9 AN |
14663 | break; |
14664 | ||
14665 | case OPTION_HARD_FLOAT: | |
0b35dfee | 14666 | file_mips_opts.soft_float = 0; |
037b32b9 AN |
14667 | break; |
14668 | ||
252b5132 | 14669 | case OPTION_MABI: |
e013f690 | 14670 | if (strcmp (arg, "32") == 0) |
316f5878 | 14671 | mips_abi = O32_ABI; |
e013f690 | 14672 | else if (strcmp (arg, "o64") == 0) |
316f5878 | 14673 | mips_abi = O64_ABI; |
e013f690 | 14674 | else if (strcmp (arg, "n32") == 0) |
316f5878 | 14675 | mips_abi = N32_ABI; |
e013f690 TS |
14676 | else if (strcmp (arg, "64") == 0) |
14677 | { | |
316f5878 | 14678 | mips_abi = N64_ABI; |
e013f690 | 14679 | if (! support_64bit_objects()) |
1661c76c | 14680 | as_fatal (_("no compiled in support for 64 bit object file " |
e013f690 TS |
14681 | "format")); |
14682 | } | |
14683 | else if (strcmp (arg, "eabi") == 0) | |
316f5878 | 14684 | mips_abi = EABI_ABI; |
e013f690 | 14685 | else |
da0e507f TS |
14686 | { |
14687 | as_fatal (_("invalid abi -mabi=%s"), arg); | |
14688 | return 0; | |
14689 | } | |
252b5132 RH |
14690 | break; |
14691 | ||
6b76fefe | 14692 | case OPTION_M7000_HILO_FIX: |
b34976b6 | 14693 | mips_7000_hilo_fix = TRUE; |
6b76fefe CM |
14694 | break; |
14695 | ||
9ee72ff1 | 14696 | case OPTION_MNO_7000_HILO_FIX: |
b34976b6 | 14697 | mips_7000_hilo_fix = FALSE; |
6b76fefe CM |
14698 | break; |
14699 | ||
ecb4347a | 14700 | case OPTION_MDEBUG: |
b34976b6 | 14701 | mips_flag_mdebug = TRUE; |
ecb4347a DJ |
14702 | break; |
14703 | ||
14704 | case OPTION_NO_MDEBUG: | |
b34976b6 | 14705 | mips_flag_mdebug = FALSE; |
ecb4347a | 14706 | break; |
dcd410fe RO |
14707 | |
14708 | case OPTION_PDR: | |
14709 | mips_flag_pdr = TRUE; | |
14710 | break; | |
14711 | ||
14712 | case OPTION_NO_PDR: | |
14713 | mips_flag_pdr = FALSE; | |
14714 | break; | |
0a44bf69 RS |
14715 | |
14716 | case OPTION_MVXWORKS_PIC: | |
14717 | mips_pic = VXWORKS_PIC; | |
14718 | break; | |
ecb4347a | 14719 | |
ba92f887 MR |
14720 | case OPTION_NAN: |
14721 | if (strcmp (arg, "2008") == 0) | |
7361da2c | 14722 | mips_nan2008 = 1; |
ba92f887 | 14723 | else if (strcmp (arg, "legacy") == 0) |
7361da2c | 14724 | mips_nan2008 = 0; |
ba92f887 MR |
14725 | else |
14726 | { | |
1661c76c | 14727 | as_fatal (_("invalid NaN setting -mnan=%s"), arg); |
ba92f887 MR |
14728 | return 0; |
14729 | } | |
14730 | break; | |
14731 | ||
252b5132 RH |
14732 | default: |
14733 | return 0; | |
14734 | } | |
14735 | ||
c67a084a NC |
14736 | mips_fix_loongson2f = mips_fix_loongson2f_nop || mips_fix_loongson2f_jump; |
14737 | ||
252b5132 RH |
14738 | return 1; |
14739 | } | |
316f5878 | 14740 | \f |
919731af | 14741 | /* Set up globals to tune for the ISA or processor described by INFO. */ |
252b5132 | 14742 | |
316f5878 | 14743 | static void |
17a2f251 | 14744 | mips_set_tune (const struct mips_cpu_info *info) |
316f5878 RS |
14745 | { |
14746 | if (info != 0) | |
fef14a42 | 14747 | mips_tune = info->cpu; |
316f5878 | 14748 | } |
80cc45a5 | 14749 | |
34ba82a8 | 14750 | |
252b5132 | 14751 | void |
17a2f251 | 14752 | mips_after_parse_args (void) |
e9670677 | 14753 | { |
fef14a42 TS |
14754 | const struct mips_cpu_info *arch_info = 0; |
14755 | const struct mips_cpu_info *tune_info = 0; | |
14756 | ||
e9670677 | 14757 | /* GP relative stuff not working for PE */ |
6caf9ef4 | 14758 | if (strncmp (TARGET_OS, "pe", 2) == 0) |
e9670677 | 14759 | { |
6caf9ef4 | 14760 | if (g_switch_seen && g_switch_value != 0) |
1661c76c | 14761 | as_bad (_("-G not supported in this configuration")); |
e9670677 MR |
14762 | g_switch_value = 0; |
14763 | } | |
14764 | ||
cac012d6 AO |
14765 | if (mips_abi == NO_ABI) |
14766 | mips_abi = MIPS_DEFAULT_ABI; | |
14767 | ||
919731af | 14768 | /* The following code determines the architecture. |
22923709 RS |
14769 | Similar code was added to GCC 3.3 (see override_options() in |
14770 | config/mips/mips.c). The GAS and GCC code should be kept in sync | |
14771 | as much as possible. */ | |
e9670677 | 14772 | |
316f5878 | 14773 | if (mips_arch_string != 0) |
fef14a42 | 14774 | arch_info = mips_parse_cpu ("-march", mips_arch_string); |
e9670677 | 14775 | |
0b35dfee | 14776 | if (file_mips_opts.isa != ISA_UNKNOWN) |
e9670677 | 14777 | { |
0b35dfee | 14778 | /* Handle -mipsN. At this point, file_mips_opts.isa contains the |
fef14a42 | 14779 | ISA level specified by -mipsN, while arch_info->isa contains |
316f5878 | 14780 | the -march selection (if any). */ |
fef14a42 | 14781 | if (arch_info != 0) |
e9670677 | 14782 | { |
316f5878 RS |
14783 | /* -march takes precedence over -mipsN, since it is more descriptive. |
14784 | There's no harm in specifying both as long as the ISA levels | |
14785 | are the same. */ | |
0b35dfee | 14786 | if (file_mips_opts.isa != arch_info->isa) |
1661c76c RS |
14787 | as_bad (_("-%s conflicts with the other architecture options," |
14788 | " which imply -%s"), | |
0b35dfee | 14789 | mips_cpu_info_from_isa (file_mips_opts.isa)->name, |
fef14a42 | 14790 | mips_cpu_info_from_isa (arch_info->isa)->name); |
e9670677 | 14791 | } |
316f5878 | 14792 | else |
0b35dfee | 14793 | arch_info = mips_cpu_info_from_isa (file_mips_opts.isa); |
e9670677 MR |
14794 | } |
14795 | ||
fef14a42 | 14796 | if (arch_info == 0) |
95bfe26e MF |
14797 | { |
14798 | arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT); | |
14799 | gas_assert (arch_info); | |
14800 | } | |
e9670677 | 14801 | |
fef14a42 | 14802 | if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa)) |
20203fb9 | 14803 | as_bad (_("-march=%s is not compatible with the selected ABI"), |
fef14a42 TS |
14804 | arch_info->name); |
14805 | ||
919731af | 14806 | file_mips_opts.arch = arch_info->cpu; |
14807 | file_mips_opts.isa = arch_info->isa; | |
14808 | ||
14809 | /* Set up initial mips_opts state. */ | |
14810 | mips_opts = file_mips_opts; | |
14811 | ||
14812 | /* The register size inference code is now placed in | |
14813 | file_mips_check_options. */ | |
fef14a42 | 14814 | |
0b35dfee | 14815 | /* Optimize for file_mips_opts.arch, unless -mtune selects a different |
14816 | processor. */ | |
fef14a42 TS |
14817 | if (mips_tune_string != 0) |
14818 | tune_info = mips_parse_cpu ("-mtune", mips_tune_string); | |
e9670677 | 14819 | |
fef14a42 TS |
14820 | if (tune_info == 0) |
14821 | mips_set_tune (arch_info); | |
14822 | else | |
14823 | mips_set_tune (tune_info); | |
e9670677 | 14824 | |
ecb4347a | 14825 | if (mips_flag_mdebug < 0) |
e8044f35 | 14826 | mips_flag_mdebug = 0; |
e9670677 MR |
14827 | } |
14828 | \f | |
14829 | void | |
17a2f251 | 14830 | mips_init_after_args (void) |
252b5132 RH |
14831 | { |
14832 | /* initialize opcodes */ | |
14833 | bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes; | |
beae10d5 | 14834 | mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes; |
252b5132 RH |
14835 | } |
14836 | ||
14837 | long | |
17a2f251 | 14838 | md_pcrel_from (fixS *fixP) |
252b5132 | 14839 | { |
a7ebbfdf TS |
14840 | valueT addr = fixP->fx_where + fixP->fx_frag->fr_address; |
14841 | switch (fixP->fx_r_type) | |
14842 | { | |
df58fc94 RS |
14843 | case BFD_RELOC_MICROMIPS_7_PCREL_S1: |
14844 | case BFD_RELOC_MICROMIPS_10_PCREL_S1: | |
14845 | /* Return the address of the delay slot. */ | |
14846 | return addr + 2; | |
14847 | ||
14848 | case BFD_RELOC_MICROMIPS_16_PCREL_S1: | |
14849 | case BFD_RELOC_MICROMIPS_JMP: | |
c9775dde | 14850 | case BFD_RELOC_MIPS16_16_PCREL_S1: |
a7ebbfdf | 14851 | case BFD_RELOC_16_PCREL_S2: |
7361da2c AB |
14852 | case BFD_RELOC_MIPS_21_PCREL_S2: |
14853 | case BFD_RELOC_MIPS_26_PCREL_S2: | |
a7ebbfdf TS |
14854 | case BFD_RELOC_MIPS_JMP: |
14855 | /* Return the address of the delay slot. */ | |
14856 | return addr + 4; | |
df58fc94 | 14857 | |
51f6035b MR |
14858 | case BFD_RELOC_MIPS_18_PCREL_S3: |
14859 | /* Return the aligned address of the doubleword containing | |
14860 | the instruction. */ | |
14861 | return addr & ~7; | |
14862 | ||
a7ebbfdf TS |
14863 | default: |
14864 | return addr; | |
14865 | } | |
252b5132 RH |
14866 | } |
14867 | ||
252b5132 RH |
14868 | /* This is called before the symbol table is processed. In order to |
14869 | work with gcc when using mips-tfile, we must keep all local labels. | |
14870 | However, in other cases, we want to discard them. If we were | |
14871 | called with -g, but we didn't see any debugging information, it may | |
14872 | mean that gcc is smuggling debugging information through to | |
14873 | mips-tfile, in which case we must generate all local labels. */ | |
14874 | ||
14875 | void | |
17a2f251 | 14876 | mips_frob_file_before_adjust (void) |
252b5132 RH |
14877 | { |
14878 | #ifndef NO_ECOFF_DEBUGGING | |
14879 | if (ECOFF_DEBUGGING | |
14880 | && mips_debug != 0 | |
14881 | && ! ecoff_debugging_seen) | |
14882 | flag_keep_locals = 1; | |
14883 | #endif | |
14884 | } | |
14885 | ||
3b91255e | 14886 | /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede |
55cf6793 | 14887 | the corresponding LO16 reloc. This is called before md_apply_fix and |
3b91255e RS |
14888 | tc_gen_reloc. Unmatched relocs can only be generated by use of explicit |
14889 | relocation operators. | |
14890 | ||
14891 | For our purposes, a %lo() expression matches a %got() or %hi() | |
14892 | expression if: | |
14893 | ||
14894 | (a) it refers to the same symbol; and | |
14895 | (b) the offset applied in the %lo() expression is no lower than | |
14896 | the offset applied in the %got() or %hi(). | |
14897 | ||
14898 | (b) allows us to cope with code like: | |
14899 | ||
14900 | lui $4,%hi(foo) | |
14901 | lh $4,%lo(foo+2)($4) | |
14902 | ||
14903 | ...which is legal on RELA targets, and has a well-defined behaviour | |
14904 | if the user knows that adding 2 to "foo" will not induce a carry to | |
14905 | the high 16 bits. | |
14906 | ||
14907 | When several %lo()s match a particular %got() or %hi(), we use the | |
14908 | following rules to distinguish them: | |
14909 | ||
14910 | (1) %lo()s with smaller offsets are a better match than %lo()s with | |
14911 | higher offsets. | |
14912 | ||
14913 | (2) %lo()s with no matching %got() or %hi() are better than those | |
14914 | that already have a matching %got() or %hi(). | |
14915 | ||
14916 | (3) later %lo()s are better than earlier %lo()s. | |
14917 | ||
14918 | These rules are applied in order. | |
14919 | ||
14920 | (1) means, among other things, that %lo()s with identical offsets are | |
14921 | chosen if they exist. | |
14922 | ||
14923 | (2) means that we won't associate several high-part relocations with | |
14924 | the same low-part relocation unless there's no alternative. Having | |
14925 | several high parts for the same low part is a GNU extension; this rule | |
14926 | allows careful users to avoid it. | |
14927 | ||
14928 | (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order, | |
14929 | with the last high-part relocation being at the front of the list. | |
14930 | It therefore makes sense to choose the last matching low-part | |
14931 | relocation, all other things being equal. It's also easier | |
14932 | to code that way. */ | |
252b5132 RH |
14933 | |
14934 | void | |
17a2f251 | 14935 | mips_frob_file (void) |
252b5132 RH |
14936 | { |
14937 | struct mips_hi_fixup *l; | |
35903be0 | 14938 | bfd_reloc_code_real_type looking_for_rtype = BFD_RELOC_UNUSED; |
252b5132 RH |
14939 | |
14940 | for (l = mips_hi_fixup_list; l != NULL; l = l->next) | |
14941 | { | |
14942 | segment_info_type *seginfo; | |
3b91255e RS |
14943 | bfd_boolean matched_lo_p; |
14944 | fixS **hi_pos, **lo_pos, **pos; | |
252b5132 | 14945 | |
9c2799c2 | 14946 | gas_assert (reloc_needs_lo_p (l->fixp->fx_r_type)); |
252b5132 | 14947 | |
5919d012 | 14948 | /* If a GOT16 relocation turns out to be against a global symbol, |
b886a2ab RS |
14949 | there isn't supposed to be a matching LO. Ignore %gots against |
14950 | constants; we'll report an error for those later. */ | |
738e5348 | 14951 | if (got16_reloc_p (l->fixp->fx_r_type) |
b886a2ab | 14952 | && !(l->fixp->fx_addsy |
9e009953 | 14953 | && pic_need_relax (l->fixp->fx_addsy))) |
5919d012 RS |
14954 | continue; |
14955 | ||
14956 | /* Check quickly whether the next fixup happens to be a matching %lo. */ | |
14957 | if (fixup_has_matching_lo_p (l->fixp)) | |
252b5132 RH |
14958 | continue; |
14959 | ||
252b5132 | 14960 | seginfo = seg_info (l->seg); |
252b5132 | 14961 | |
3b91255e RS |
14962 | /* Set HI_POS to the position of this relocation in the chain. |
14963 | Set LO_POS to the position of the chosen low-part relocation. | |
14964 | MATCHED_LO_P is true on entry to the loop if *POS is a low-part | |
14965 | relocation that matches an immediately-preceding high-part | |
14966 | relocation. */ | |
14967 | hi_pos = NULL; | |
14968 | lo_pos = NULL; | |
14969 | matched_lo_p = FALSE; | |
738e5348 | 14970 | looking_for_rtype = matching_lo_reloc (l->fixp->fx_r_type); |
35903be0 | 14971 | |
3b91255e RS |
14972 | for (pos = &seginfo->fix_root; *pos != NULL; pos = &(*pos)->fx_next) |
14973 | { | |
14974 | if (*pos == l->fixp) | |
14975 | hi_pos = pos; | |
14976 | ||
35903be0 | 14977 | if ((*pos)->fx_r_type == looking_for_rtype |
30cfc97a | 14978 | && symbol_same_p ((*pos)->fx_addsy, l->fixp->fx_addsy) |
3b91255e RS |
14979 | && (*pos)->fx_offset >= l->fixp->fx_offset |
14980 | && (lo_pos == NULL | |
14981 | || (*pos)->fx_offset < (*lo_pos)->fx_offset | |
14982 | || (!matched_lo_p | |
14983 | && (*pos)->fx_offset == (*lo_pos)->fx_offset))) | |
14984 | lo_pos = pos; | |
14985 | ||
14986 | matched_lo_p = (reloc_needs_lo_p ((*pos)->fx_r_type) | |
14987 | && fixup_has_matching_lo_p (*pos)); | |
14988 | } | |
14989 | ||
14990 | /* If we found a match, remove the high-part relocation from its | |
14991 | current position and insert it before the low-part relocation. | |
14992 | Make the offsets match so that fixup_has_matching_lo_p() | |
14993 | will return true. | |
14994 | ||
14995 | We don't warn about unmatched high-part relocations since some | |
14996 | versions of gcc have been known to emit dead "lui ...%hi(...)" | |
14997 | instructions. */ | |
14998 | if (lo_pos != NULL) | |
14999 | { | |
15000 | l->fixp->fx_offset = (*lo_pos)->fx_offset; | |
15001 | if (l->fixp->fx_next != *lo_pos) | |
252b5132 | 15002 | { |
3b91255e RS |
15003 | *hi_pos = l->fixp->fx_next; |
15004 | l->fixp->fx_next = *lo_pos; | |
15005 | *lo_pos = l->fixp; | |
252b5132 | 15006 | } |
252b5132 RH |
15007 | } |
15008 | } | |
15009 | } | |
15010 | ||
252b5132 | 15011 | int |
17a2f251 | 15012 | mips_force_relocation (fixS *fixp) |
252b5132 | 15013 | { |
ae6063d4 | 15014 | if (generic_force_reloc (fixp)) |
252b5132 RH |
15015 | return 1; |
15016 | ||
df58fc94 RS |
15017 | /* We want to keep BFD_RELOC_MICROMIPS_*_PCREL_S1 relocation, |
15018 | so that the linker relaxation can update targets. */ | |
15019 | if (fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1 | |
15020 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1 | |
15021 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1) | |
15022 | return 1; | |
15023 | ||
5caa2b07 MR |
15024 | /* We want to keep BFD_RELOC_16_PCREL_S2 BFD_RELOC_MIPS_21_PCREL_S2 |
15025 | and BFD_RELOC_MIPS_26_PCREL_S2 relocations against MIPS16 and | |
15026 | microMIPS symbols so that we can do cross-mode branch diagnostics | |
15027 | and BAL to JALX conversion by the linker. */ | |
15028 | if ((fixp->fx_r_type == BFD_RELOC_16_PCREL_S2 | |
9d862524 MR |
15029 | || fixp->fx_r_type == BFD_RELOC_MIPS_21_PCREL_S2 |
15030 | || fixp->fx_r_type == BFD_RELOC_MIPS_26_PCREL_S2) | |
15031 | && fixp->fx_addsy | |
15032 | && ELF_ST_IS_COMPRESSED (S_GET_OTHER (fixp->fx_addsy))) | |
15033 | return 1; | |
15034 | ||
7361da2c | 15035 | /* We want all PC-relative relocations to be kept for R6 relaxation. */ |
912815f0 | 15036 | if (ISA_IS_R6 (file_mips_opts.isa) |
7361da2c AB |
15037 | && (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2 |
15038 | || fixp->fx_r_type == BFD_RELOC_MIPS_21_PCREL_S2 | |
15039 | || fixp->fx_r_type == BFD_RELOC_MIPS_26_PCREL_S2 | |
15040 | || fixp->fx_r_type == BFD_RELOC_MIPS_18_PCREL_S3 | |
15041 | || fixp->fx_r_type == BFD_RELOC_MIPS_19_PCREL_S2 | |
15042 | || fixp->fx_r_type == BFD_RELOC_HI16_S_PCREL | |
15043 | || fixp->fx_r_type == BFD_RELOC_LO16_PCREL)) | |
15044 | return 1; | |
15045 | ||
3e722fb5 | 15046 | return 0; |
252b5132 RH |
15047 | } |
15048 | ||
b416ba9b MR |
15049 | /* Implement TC_FORCE_RELOCATION_ABS. */ |
15050 | ||
15051 | bfd_boolean | |
15052 | mips_force_relocation_abs (fixS *fixp) | |
15053 | { | |
15054 | if (generic_force_reloc (fixp)) | |
15055 | return TRUE; | |
15056 | ||
15057 | /* These relocations do not have enough bits in the in-place addend | |
15058 | to hold an arbitrary absolute section's offset. */ | |
15059 | if (HAVE_IN_PLACE_ADDENDS && limited_pcrel_reloc_p (fixp->fx_r_type)) | |
15060 | return TRUE; | |
15061 | ||
15062 | return FALSE; | |
15063 | } | |
15064 | ||
b886a2ab RS |
15065 | /* Read the instruction associated with RELOC from BUF. */ |
15066 | ||
15067 | static unsigned int | |
15068 | read_reloc_insn (char *buf, bfd_reloc_code_real_type reloc) | |
15069 | { | |
15070 | if (mips16_reloc_p (reloc) || micromips_reloc_p (reloc)) | |
15071 | return read_compressed_insn (buf, 4); | |
15072 | else | |
15073 | return read_insn (buf); | |
15074 | } | |
15075 | ||
15076 | /* Write instruction INSN to BUF, given that it has been relocated | |
15077 | by RELOC. */ | |
15078 | ||
15079 | static void | |
15080 | write_reloc_insn (char *buf, bfd_reloc_code_real_type reloc, | |
15081 | unsigned long insn) | |
15082 | { | |
15083 | if (mips16_reloc_p (reloc) || micromips_reloc_p (reloc)) | |
15084 | write_compressed_insn (buf, insn, 4); | |
15085 | else | |
15086 | write_insn (buf, insn); | |
15087 | } | |
15088 | ||
9d862524 MR |
15089 | /* Return TRUE if the instruction pointed to by FIXP is an invalid jump |
15090 | to a symbol in another ISA mode, which cannot be converted to JALX. */ | |
15091 | ||
15092 | static bfd_boolean | |
15093 | fix_bad_cross_mode_jump_p (fixS *fixP) | |
15094 | { | |
15095 | unsigned long opcode; | |
15096 | int other; | |
15097 | char *buf; | |
15098 | ||
15099 | if (!fixP->fx_addsy || S_FORCE_RELOC (fixP->fx_addsy, TRUE)) | |
15100 | return FALSE; | |
15101 | ||
15102 | other = S_GET_OTHER (fixP->fx_addsy); | |
15103 | buf = fixP->fx_frag->fr_literal + fixP->fx_where; | |
15104 | opcode = read_reloc_insn (buf, fixP->fx_r_type) >> 26; | |
15105 | switch (fixP->fx_r_type) | |
15106 | { | |
15107 | case BFD_RELOC_MIPS_JMP: | |
15108 | return opcode != 0x1d && opcode != 0x03 && ELF_ST_IS_COMPRESSED (other); | |
15109 | case BFD_RELOC_MICROMIPS_JMP: | |
15110 | return opcode != 0x3c && opcode != 0x3d && !ELF_ST_IS_MICROMIPS (other); | |
15111 | default: | |
15112 | return FALSE; | |
15113 | } | |
15114 | } | |
15115 | ||
15116 | /* Return TRUE if the instruction pointed to by FIXP is an invalid JALX | |
15117 | jump to a symbol in the same ISA mode. */ | |
15118 | ||
15119 | static bfd_boolean | |
15120 | fix_bad_same_mode_jalx_p (fixS *fixP) | |
15121 | { | |
15122 | unsigned long opcode; | |
15123 | int other; | |
15124 | char *buf; | |
15125 | ||
15126 | if (!fixP->fx_addsy || S_FORCE_RELOC (fixP->fx_addsy, TRUE)) | |
15127 | return FALSE; | |
15128 | ||
15129 | other = S_GET_OTHER (fixP->fx_addsy); | |
15130 | buf = fixP->fx_frag->fr_literal + fixP->fx_where; | |
15131 | opcode = read_reloc_insn (buf, fixP->fx_r_type) >> 26; | |
15132 | switch (fixP->fx_r_type) | |
15133 | { | |
15134 | case BFD_RELOC_MIPS_JMP: | |
15135 | return opcode == 0x1d && !ELF_ST_IS_COMPRESSED (other); | |
15136 | case BFD_RELOC_MIPS16_JMP: | |
15137 | return opcode == 0x07 && ELF_ST_IS_COMPRESSED (other); | |
15138 | case BFD_RELOC_MICROMIPS_JMP: | |
15139 | return opcode == 0x3c && ELF_ST_IS_COMPRESSED (other); | |
15140 | default: | |
15141 | return FALSE; | |
15142 | } | |
15143 | } | |
15144 | ||
15145 | /* Return TRUE if the instruction pointed to by FIXP is an invalid jump | |
15146 | to a symbol whose value plus addend is not aligned according to the | |
15147 | ultimate (after linker relaxation) jump instruction's immediate field | |
15148 | requirement, either to (1 << SHIFT), or, for jumps from microMIPS to | |
15149 | regular MIPS code, to (1 << 2). */ | |
15150 | ||
15151 | static bfd_boolean | |
15152 | fix_bad_misaligned_jump_p (fixS *fixP, int shift) | |
15153 | { | |
15154 | bfd_boolean micro_to_mips_p; | |
15155 | valueT val; | |
15156 | int other; | |
15157 | ||
15158 | if (!fixP->fx_addsy || S_FORCE_RELOC (fixP->fx_addsy, TRUE)) | |
15159 | return FALSE; | |
15160 | ||
15161 | other = S_GET_OTHER (fixP->fx_addsy); | |
15162 | val = S_GET_VALUE (fixP->fx_addsy) | ELF_ST_IS_COMPRESSED (other); | |
15163 | val += fixP->fx_offset; | |
15164 | micro_to_mips_p = (fixP->fx_r_type == BFD_RELOC_MICROMIPS_JMP | |
15165 | && !ELF_ST_IS_MICROMIPS (other)); | |
15166 | return ((val & ((1 << (micro_to_mips_p ? 2 : shift)) - 1)) | |
15167 | != ELF_ST_IS_COMPRESSED (other)); | |
15168 | } | |
15169 | ||
15170 | /* Return TRUE if the instruction pointed to by FIXP is an invalid branch | |
15171 | to a symbol whose annotation indicates another ISA mode. For absolute | |
a6ebf616 MR |
15172 | symbols check the ISA bit instead. |
15173 | ||
15174 | We accept BFD_RELOC_16_PCREL_S2 relocations against MIPS16 and microMIPS | |
15175 | symbols or BFD_RELOC_MICROMIPS_16_PCREL_S1 relocations against regular | |
15176 | MIPS symbols and associated with BAL instructions as these instructions | |
15177 | may be be converted to JALX by the linker. */ | |
9d862524 MR |
15178 | |
15179 | static bfd_boolean | |
15180 | fix_bad_cross_mode_branch_p (fixS *fixP) | |
15181 | { | |
15182 | bfd_boolean absolute_p; | |
15183 | unsigned long opcode; | |
15184 | asection *symsec; | |
15185 | valueT val; | |
15186 | int other; | |
15187 | char *buf; | |
15188 | ||
8b10b0b3 MR |
15189 | if (mips_ignore_branch_isa) |
15190 | return FALSE; | |
15191 | ||
9d862524 MR |
15192 | if (!fixP->fx_addsy || S_FORCE_RELOC (fixP->fx_addsy, TRUE)) |
15193 | return FALSE; | |
15194 | ||
15195 | symsec = S_GET_SEGMENT (fixP->fx_addsy); | |
15196 | absolute_p = bfd_is_abs_section (symsec); | |
15197 | ||
15198 | val = S_GET_VALUE (fixP->fx_addsy) + fixP->fx_offset; | |
15199 | other = S_GET_OTHER (fixP->fx_addsy); | |
15200 | ||
15201 | buf = fixP->fx_frag->fr_literal + fixP->fx_where; | |
15202 | opcode = read_reloc_insn (buf, fixP->fx_r_type) >> 16; | |
15203 | switch (fixP->fx_r_type) | |
15204 | { | |
15205 | case BFD_RELOC_16_PCREL_S2: | |
a6ebf616 MR |
15206 | return ((absolute_p ? val & 1 : ELF_ST_IS_COMPRESSED (other)) |
15207 | && opcode != 0x0411); | |
15208 | case BFD_RELOC_MICROMIPS_16_PCREL_S1: | |
15209 | return ((absolute_p ? !(val & 1) : !ELF_ST_IS_MICROMIPS (other)) | |
15210 | && opcode != 0x4060); | |
9d862524 MR |
15211 | case BFD_RELOC_MIPS_21_PCREL_S2: |
15212 | case BFD_RELOC_MIPS_26_PCREL_S2: | |
15213 | return absolute_p ? val & 1 : ELF_ST_IS_COMPRESSED (other); | |
15214 | case BFD_RELOC_MIPS16_16_PCREL_S1: | |
15215 | return absolute_p ? !(val & 1) : !ELF_ST_IS_MIPS16 (other); | |
15216 | case BFD_RELOC_MICROMIPS_7_PCREL_S1: | |
15217 | case BFD_RELOC_MICROMIPS_10_PCREL_S1: | |
9d862524 MR |
15218 | return absolute_p ? !(val & 1) : !ELF_ST_IS_MICROMIPS (other); |
15219 | default: | |
15220 | abort (); | |
15221 | } | |
15222 | } | |
15223 | ||
15224 | /* Return TRUE if the symbol plus addend associated with a regular MIPS | |
15225 | branch instruction pointed to by FIXP is not aligned according to the | |
15226 | branch instruction's immediate field requirement. We need the addend | |
15227 | to preserve the ISA bit and also the sum must not have bit 2 set. We | |
15228 | must explicitly OR in the ISA bit from symbol annotation as the bit | |
15229 | won't be set in the symbol's value then. */ | |
15230 | ||
15231 | static bfd_boolean | |
15232 | fix_bad_misaligned_branch_p (fixS *fixP) | |
15233 | { | |
15234 | bfd_boolean absolute_p; | |
15235 | asection *symsec; | |
15236 | valueT isa_bit; | |
15237 | valueT val; | |
15238 | valueT off; | |
15239 | int other; | |
15240 | ||
15241 | if (!fixP->fx_addsy || S_FORCE_RELOC (fixP->fx_addsy, TRUE)) | |
15242 | return FALSE; | |
15243 | ||
15244 | symsec = S_GET_SEGMENT (fixP->fx_addsy); | |
15245 | absolute_p = bfd_is_abs_section (symsec); | |
15246 | ||
15247 | val = S_GET_VALUE (fixP->fx_addsy); | |
15248 | other = S_GET_OTHER (fixP->fx_addsy); | |
15249 | off = fixP->fx_offset; | |
15250 | ||
15251 | isa_bit = absolute_p ? (val + off) & 1 : ELF_ST_IS_COMPRESSED (other); | |
15252 | val |= ELF_ST_IS_COMPRESSED (other); | |
15253 | val += off; | |
15254 | return (val & 0x3) != isa_bit; | |
15255 | } | |
15256 | ||
15257 | /* Make the necessary checks on a regular MIPS branch pointed to by FIXP | |
15258 | and its calculated value VAL. */ | |
15259 | ||
15260 | static void | |
15261 | fix_validate_branch (fixS *fixP, valueT val) | |
15262 | { | |
15263 | if (fixP->fx_done && (val & 0x3) != 0) | |
15264 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15265 | _("branch to misaligned address (0x%lx)"), | |
15266 | (long) (val + md_pcrel_from (fixP))); | |
15267 | else if (fix_bad_cross_mode_branch_p (fixP)) | |
15268 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15269 | _("branch to a symbol in another ISA mode")); | |
15270 | else if (fix_bad_misaligned_branch_p (fixP)) | |
15271 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15272 | _("branch to misaligned address (0x%lx)"), | |
15273 | (long) (S_GET_VALUE (fixP->fx_addsy) + fixP->fx_offset)); | |
15274 | else if (HAVE_IN_PLACE_ADDENDS && (fixP->fx_offset & 0x3) != 0) | |
15275 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15276 | _("cannot encode misaligned addend " | |
15277 | "in the relocatable field (0x%lx)"), | |
15278 | (long) fixP->fx_offset); | |
15279 | } | |
15280 | ||
252b5132 RH |
15281 | /* Apply a fixup to the object file. */ |
15282 | ||
94f592af | 15283 | void |
55cf6793 | 15284 | md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) |
252b5132 | 15285 | { |
4d68580a | 15286 | char *buf; |
b886a2ab | 15287 | unsigned long insn; |
a7ebbfdf | 15288 | reloc_howto_type *howto; |
252b5132 | 15289 | |
d56a8dda RS |
15290 | if (fixP->fx_pcrel) |
15291 | switch (fixP->fx_r_type) | |
15292 | { | |
15293 | case BFD_RELOC_16_PCREL_S2: | |
c9775dde | 15294 | case BFD_RELOC_MIPS16_16_PCREL_S1: |
d56a8dda RS |
15295 | case BFD_RELOC_MICROMIPS_7_PCREL_S1: |
15296 | case BFD_RELOC_MICROMIPS_10_PCREL_S1: | |
15297 | case BFD_RELOC_MICROMIPS_16_PCREL_S1: | |
15298 | case BFD_RELOC_32_PCREL: | |
7361da2c AB |
15299 | case BFD_RELOC_MIPS_21_PCREL_S2: |
15300 | case BFD_RELOC_MIPS_26_PCREL_S2: | |
15301 | case BFD_RELOC_MIPS_18_PCREL_S3: | |
15302 | case BFD_RELOC_MIPS_19_PCREL_S2: | |
15303 | case BFD_RELOC_HI16_S_PCREL: | |
15304 | case BFD_RELOC_LO16_PCREL: | |
d56a8dda RS |
15305 | break; |
15306 | ||
15307 | case BFD_RELOC_32: | |
15308 | fixP->fx_r_type = BFD_RELOC_32_PCREL; | |
15309 | break; | |
15310 | ||
15311 | default: | |
15312 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15313 | _("PC-relative reference to a different section")); | |
15314 | break; | |
15315 | } | |
15316 | ||
15317 | /* Handle BFD_RELOC_8, since it's easy. Punt on other bfd relocations | |
15318 | that have no MIPS ELF equivalent. */ | |
15319 | if (fixP->fx_r_type != BFD_RELOC_8) | |
15320 | { | |
15321 | howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type); | |
15322 | if (!howto) | |
15323 | return; | |
15324 | } | |
65551fa4 | 15325 | |
df58fc94 RS |
15326 | gas_assert (fixP->fx_size == 2 |
15327 | || fixP->fx_size == 4 | |
d56a8dda | 15328 | || fixP->fx_r_type == BFD_RELOC_8 |
90ecf173 MR |
15329 | || fixP->fx_r_type == BFD_RELOC_16 |
15330 | || fixP->fx_r_type == BFD_RELOC_64 | |
15331 | || fixP->fx_r_type == BFD_RELOC_CTOR | |
15332 | || fixP->fx_r_type == BFD_RELOC_MIPS_SUB | |
df58fc94 | 15333 | || fixP->fx_r_type == BFD_RELOC_MICROMIPS_SUB |
90ecf173 MR |
15334 | || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
15335 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY | |
2f0c68f2 CM |
15336 | || fixP->fx_r_type == BFD_RELOC_MIPS_TLS_DTPREL64 |
15337 | || fixP->fx_r_type == BFD_RELOC_NONE); | |
252b5132 | 15338 | |
4d68580a | 15339 | buf = fixP->fx_frag->fr_literal + fixP->fx_where; |
252b5132 | 15340 | |
b1dca8ee RS |
15341 | /* Don't treat parts of a composite relocation as done. There are two |
15342 | reasons for this: | |
15343 | ||
15344 | (1) The second and third parts will be against 0 (RSS_UNDEF) but | |
15345 | should nevertheless be emitted if the first part is. | |
15346 | ||
15347 | (2) In normal usage, composite relocations are never assembly-time | |
15348 | constants. The easiest way of dealing with the pathological | |
15349 | exceptions is to generate a relocation against STN_UNDEF and | |
15350 | leave everything up to the linker. */ | |
3994f87e | 15351 | if (fixP->fx_addsy == NULL && !fixP->fx_pcrel && fixP->fx_tcbit == 0) |
252b5132 RH |
15352 | fixP->fx_done = 1; |
15353 | ||
15354 | switch (fixP->fx_r_type) | |
15355 | { | |
3f98094e DJ |
15356 | case BFD_RELOC_MIPS_TLS_GD: |
15357 | case BFD_RELOC_MIPS_TLS_LDM: | |
741d6ea8 JM |
15358 | case BFD_RELOC_MIPS_TLS_DTPREL32: |
15359 | case BFD_RELOC_MIPS_TLS_DTPREL64: | |
3f98094e DJ |
15360 | case BFD_RELOC_MIPS_TLS_DTPREL_HI16: |
15361 | case BFD_RELOC_MIPS_TLS_DTPREL_LO16: | |
15362 | case BFD_RELOC_MIPS_TLS_GOTTPREL: | |
d0f13682 CLT |
15363 | case BFD_RELOC_MIPS_TLS_TPREL32: |
15364 | case BFD_RELOC_MIPS_TLS_TPREL64: | |
3f98094e DJ |
15365 | case BFD_RELOC_MIPS_TLS_TPREL_HI16: |
15366 | case BFD_RELOC_MIPS_TLS_TPREL_LO16: | |
df58fc94 RS |
15367 | case BFD_RELOC_MICROMIPS_TLS_GD: |
15368 | case BFD_RELOC_MICROMIPS_TLS_LDM: | |
15369 | case BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16: | |
15370 | case BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16: | |
15371 | case BFD_RELOC_MICROMIPS_TLS_GOTTPREL: | |
15372 | case BFD_RELOC_MICROMIPS_TLS_TPREL_HI16: | |
15373 | case BFD_RELOC_MICROMIPS_TLS_TPREL_LO16: | |
d0f13682 CLT |
15374 | case BFD_RELOC_MIPS16_TLS_GD: |
15375 | case BFD_RELOC_MIPS16_TLS_LDM: | |
15376 | case BFD_RELOC_MIPS16_TLS_DTPREL_HI16: | |
15377 | case BFD_RELOC_MIPS16_TLS_DTPREL_LO16: | |
15378 | case BFD_RELOC_MIPS16_TLS_GOTTPREL: | |
15379 | case BFD_RELOC_MIPS16_TLS_TPREL_HI16: | |
15380 | case BFD_RELOC_MIPS16_TLS_TPREL_LO16: | |
4512dafa MR |
15381 | if (fixP->fx_addsy) |
15382 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
15383 | else | |
15384 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15385 | _("TLS relocation against a constant")); | |
15386 | break; | |
3f98094e | 15387 | |
252b5132 | 15388 | case BFD_RELOC_MIPS_JMP: |
9d862524 MR |
15389 | case BFD_RELOC_MIPS16_JMP: |
15390 | case BFD_RELOC_MICROMIPS_JMP: | |
15391 | { | |
15392 | int shift; | |
15393 | ||
15394 | gas_assert (!fixP->fx_done); | |
15395 | ||
15396 | /* Shift is 2, unusually, for microMIPS JALX. */ | |
15397 | if (fixP->fx_r_type == BFD_RELOC_MICROMIPS_JMP | |
15398 | && (read_compressed_insn (buf, 4) >> 26) != 0x3c) | |
15399 | shift = 1; | |
15400 | else | |
15401 | shift = 2; | |
15402 | ||
15403 | if (fix_bad_cross_mode_jump_p (fixP)) | |
15404 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15405 | _("jump to a symbol in another ISA mode")); | |
15406 | else if (fix_bad_same_mode_jalx_p (fixP)) | |
15407 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15408 | _("JALX to a symbol in the same ISA mode")); | |
15409 | else if (fix_bad_misaligned_jump_p (fixP, shift)) | |
15410 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15411 | _("jump to misaligned address (0x%lx)"), | |
15412 | (long) (S_GET_VALUE (fixP->fx_addsy) | |
15413 | + fixP->fx_offset)); | |
15414 | else if (HAVE_IN_PLACE_ADDENDS | |
15415 | && (fixP->fx_offset & ((1 << shift) - 1)) != 0) | |
15416 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15417 | _("cannot encode misaligned addend " | |
15418 | "in the relocatable field (0x%lx)"), | |
15419 | (long) fixP->fx_offset); | |
15420 | } | |
15421 | /* Fall through. */ | |
15422 | ||
e369bcce TS |
15423 | case BFD_RELOC_MIPS_SHIFT5: |
15424 | case BFD_RELOC_MIPS_SHIFT6: | |
15425 | case BFD_RELOC_MIPS_GOT_DISP: | |
15426 | case BFD_RELOC_MIPS_GOT_PAGE: | |
15427 | case BFD_RELOC_MIPS_GOT_OFST: | |
15428 | case BFD_RELOC_MIPS_SUB: | |
15429 | case BFD_RELOC_MIPS_INSERT_A: | |
15430 | case BFD_RELOC_MIPS_INSERT_B: | |
15431 | case BFD_RELOC_MIPS_DELETE: | |
15432 | case BFD_RELOC_MIPS_HIGHEST: | |
15433 | case BFD_RELOC_MIPS_HIGHER: | |
15434 | case BFD_RELOC_MIPS_SCN_DISP: | |
15435 | case BFD_RELOC_MIPS_REL16: | |
15436 | case BFD_RELOC_MIPS_RELGOT: | |
15437 | case BFD_RELOC_MIPS_JALR: | |
252b5132 RH |
15438 | case BFD_RELOC_HI16: |
15439 | case BFD_RELOC_HI16_S: | |
b886a2ab | 15440 | case BFD_RELOC_LO16: |
cdf6fd85 | 15441 | case BFD_RELOC_GPREL16: |
252b5132 RH |
15442 | case BFD_RELOC_MIPS_LITERAL: |
15443 | case BFD_RELOC_MIPS_CALL16: | |
15444 | case BFD_RELOC_MIPS_GOT16: | |
cdf6fd85 | 15445 | case BFD_RELOC_GPREL32: |
252b5132 RH |
15446 | case BFD_RELOC_MIPS_GOT_HI16: |
15447 | case BFD_RELOC_MIPS_GOT_LO16: | |
15448 | case BFD_RELOC_MIPS_CALL_HI16: | |
15449 | case BFD_RELOC_MIPS_CALL_LO16: | |
41947d9e MR |
15450 | case BFD_RELOC_HI16_S_PCREL: |
15451 | case BFD_RELOC_LO16_PCREL: | |
252b5132 | 15452 | case BFD_RELOC_MIPS16_GPREL: |
738e5348 RS |
15453 | case BFD_RELOC_MIPS16_GOT16: |
15454 | case BFD_RELOC_MIPS16_CALL16: | |
d6f16593 MR |
15455 | case BFD_RELOC_MIPS16_HI16: |
15456 | case BFD_RELOC_MIPS16_HI16_S: | |
b886a2ab | 15457 | case BFD_RELOC_MIPS16_LO16: |
df58fc94 RS |
15458 | case BFD_RELOC_MICROMIPS_GOT_DISP: |
15459 | case BFD_RELOC_MICROMIPS_GOT_PAGE: | |
15460 | case BFD_RELOC_MICROMIPS_GOT_OFST: | |
15461 | case BFD_RELOC_MICROMIPS_SUB: | |
15462 | case BFD_RELOC_MICROMIPS_HIGHEST: | |
15463 | case BFD_RELOC_MICROMIPS_HIGHER: | |
15464 | case BFD_RELOC_MICROMIPS_SCN_DISP: | |
15465 | case BFD_RELOC_MICROMIPS_JALR: | |
15466 | case BFD_RELOC_MICROMIPS_HI16: | |
15467 | case BFD_RELOC_MICROMIPS_HI16_S: | |
b886a2ab | 15468 | case BFD_RELOC_MICROMIPS_LO16: |
df58fc94 RS |
15469 | case BFD_RELOC_MICROMIPS_GPREL16: |
15470 | case BFD_RELOC_MICROMIPS_LITERAL: | |
15471 | case BFD_RELOC_MICROMIPS_CALL16: | |
15472 | case BFD_RELOC_MICROMIPS_GOT16: | |
15473 | case BFD_RELOC_MICROMIPS_GOT_HI16: | |
15474 | case BFD_RELOC_MICROMIPS_GOT_LO16: | |
15475 | case BFD_RELOC_MICROMIPS_CALL_HI16: | |
15476 | case BFD_RELOC_MICROMIPS_CALL_LO16: | |
067ec077 | 15477 | case BFD_RELOC_MIPS_EH: |
b886a2ab RS |
15478 | if (fixP->fx_done) |
15479 | { | |
15480 | offsetT value; | |
15481 | ||
15482 | if (calculate_reloc (fixP->fx_r_type, *valP, &value)) | |
15483 | { | |
15484 | insn = read_reloc_insn (buf, fixP->fx_r_type); | |
15485 | if (mips16_reloc_p (fixP->fx_r_type)) | |
15486 | insn |= mips16_immed_extend (value, 16); | |
15487 | else | |
15488 | insn |= (value & 0xffff); | |
15489 | write_reloc_insn (buf, fixP->fx_r_type, insn); | |
15490 | } | |
15491 | else | |
15492 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
1661c76c | 15493 | _("unsupported constant in relocation")); |
b886a2ab | 15494 | } |
252b5132 RH |
15495 | break; |
15496 | ||
252b5132 RH |
15497 | case BFD_RELOC_64: |
15498 | /* This is handled like BFD_RELOC_32, but we output a sign | |
15499 | extended value if we are only 32 bits. */ | |
3e722fb5 | 15500 | if (fixP->fx_done) |
252b5132 RH |
15501 | { |
15502 | if (8 <= sizeof (valueT)) | |
4d68580a | 15503 | md_number_to_chars (buf, *valP, 8); |
252b5132 RH |
15504 | else |
15505 | { | |
a7ebbfdf | 15506 | valueT hiv; |
252b5132 | 15507 | |
a7ebbfdf | 15508 | if ((*valP & 0x80000000) != 0) |
252b5132 RH |
15509 | hiv = 0xffffffff; |
15510 | else | |
15511 | hiv = 0; | |
4d68580a RS |
15512 | md_number_to_chars (buf + (target_big_endian ? 4 : 0), *valP, 4); |
15513 | md_number_to_chars (buf + (target_big_endian ? 0 : 4), hiv, 4); | |
252b5132 RH |
15514 | } |
15515 | } | |
15516 | break; | |
15517 | ||
056350c6 | 15518 | case BFD_RELOC_RVA: |
252b5132 | 15519 | case BFD_RELOC_32: |
b47468a6 | 15520 | case BFD_RELOC_32_PCREL: |
252b5132 | 15521 | case BFD_RELOC_16: |
d56a8dda | 15522 | case BFD_RELOC_8: |
252b5132 | 15523 | /* If we are deleting this reloc entry, we must fill in the |
54f4ddb3 TS |
15524 | value now. This can happen if we have a .word which is not |
15525 | resolved when it appears but is later defined. */ | |
252b5132 | 15526 | if (fixP->fx_done) |
4d68580a | 15527 | md_number_to_chars (buf, *valP, fixP->fx_size); |
252b5132 RH |
15528 | break; |
15529 | ||
7361da2c | 15530 | case BFD_RELOC_MIPS_21_PCREL_S2: |
9d862524 | 15531 | fix_validate_branch (fixP, *valP); |
41947d9e MR |
15532 | if (!fixP->fx_done) |
15533 | break; | |
15534 | ||
15535 | if (*valP + 0x400000 <= 0x7fffff) | |
15536 | { | |
15537 | insn = read_insn (buf); | |
15538 | insn |= (*valP >> 2) & 0x1fffff; | |
15539 | write_insn (buf, insn); | |
15540 | } | |
15541 | else | |
15542 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15543 | _("branch out of range")); | |
15544 | break; | |
15545 | ||
7361da2c | 15546 | case BFD_RELOC_MIPS_26_PCREL_S2: |
9d862524 | 15547 | fix_validate_branch (fixP, *valP); |
41947d9e MR |
15548 | if (!fixP->fx_done) |
15549 | break; | |
7361da2c | 15550 | |
41947d9e MR |
15551 | if (*valP + 0x8000000 <= 0xfffffff) |
15552 | { | |
15553 | insn = read_insn (buf); | |
15554 | insn |= (*valP >> 2) & 0x3ffffff; | |
15555 | write_insn (buf, insn); | |
15556 | } | |
15557 | else | |
15558 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15559 | _("branch out of range")); | |
7361da2c AB |
15560 | break; |
15561 | ||
15562 | case BFD_RELOC_MIPS_18_PCREL_S3: | |
717ba204 | 15563 | if (fixP->fx_addsy && (S_GET_VALUE (fixP->fx_addsy) & 0x7) != 0) |
7361da2c | 15564 | as_bad_where (fixP->fx_file, fixP->fx_line, |
0866e94c MF |
15565 | _("PC-relative access using misaligned symbol (%lx)"), |
15566 | (long) S_GET_VALUE (fixP->fx_addsy)); | |
15567 | if ((fixP->fx_offset & 0x7) != 0) | |
15568 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15569 | _("PC-relative access using misaligned offset (%lx)"), | |
15570 | (long) fixP->fx_offset); | |
41947d9e MR |
15571 | if (!fixP->fx_done) |
15572 | break; | |
7361da2c | 15573 | |
41947d9e MR |
15574 | if (*valP + 0x100000 <= 0x1fffff) |
15575 | { | |
15576 | insn = read_insn (buf); | |
15577 | insn |= (*valP >> 3) & 0x3ffff; | |
15578 | write_insn (buf, insn); | |
15579 | } | |
15580 | else | |
15581 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15582 | _("PC-relative access out of range")); | |
7361da2c AB |
15583 | break; |
15584 | ||
15585 | case BFD_RELOC_MIPS_19_PCREL_S2: | |
15586 | if ((*valP & 0x3) != 0) | |
15587 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15588 | _("PC-relative access to misaligned address (%lx)"), | |
717ba204 | 15589 | (long) *valP); |
41947d9e MR |
15590 | if (!fixP->fx_done) |
15591 | break; | |
7361da2c | 15592 | |
41947d9e MR |
15593 | if (*valP + 0x100000 <= 0x1fffff) |
15594 | { | |
15595 | insn = read_insn (buf); | |
15596 | insn |= (*valP >> 2) & 0x7ffff; | |
15597 | write_insn (buf, insn); | |
15598 | } | |
15599 | else | |
15600 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15601 | _("PC-relative access out of range")); | |
7361da2c AB |
15602 | break; |
15603 | ||
252b5132 | 15604 | case BFD_RELOC_16_PCREL_S2: |
9d862524 | 15605 | fix_validate_branch (fixP, *valP); |
cb56d3d3 | 15606 | |
54f4ddb3 TS |
15607 | /* We need to save the bits in the instruction since fixup_segment() |
15608 | might be deleting the relocation entry (i.e., a branch within | |
15609 | the current segment). */ | |
a7ebbfdf | 15610 | if (! fixP->fx_done) |
bb2d6cd7 | 15611 | break; |
252b5132 | 15612 | |
54f4ddb3 | 15613 | /* Update old instruction data. */ |
4d68580a | 15614 | insn = read_insn (buf); |
252b5132 | 15615 | |
a7ebbfdf TS |
15616 | if (*valP + 0x20000 <= 0x3ffff) |
15617 | { | |
15618 | insn |= (*valP >> 2) & 0xffff; | |
4d68580a | 15619 | write_insn (buf, insn); |
a7ebbfdf | 15620 | } |
ce8ad872 | 15621 | else if (fixP->fx_tcbit2 |
a7ebbfdf TS |
15622 | && fixP->fx_done |
15623 | && fixP->fx_frag->fr_address >= text_section->vma | |
15624 | && (fixP->fx_frag->fr_address | |
587aac4e | 15625 | < text_section->vma + bfd_get_section_size (text_section)) |
a7ebbfdf TS |
15626 | && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */ |
15627 | || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */ | |
15628 | || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */ | |
252b5132 RH |
15629 | { |
15630 | /* The branch offset is too large. If this is an | |
15631 | unconditional branch, and we are not generating PIC code, | |
15632 | we can convert it to an absolute jump instruction. */ | |
a7ebbfdf TS |
15633 | if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */ |
15634 | insn = 0x0c000000; /* jal */ | |
252b5132 | 15635 | else |
a7ebbfdf TS |
15636 | insn = 0x08000000; /* j */ |
15637 | fixP->fx_r_type = BFD_RELOC_MIPS_JMP; | |
15638 | fixP->fx_done = 0; | |
15639 | fixP->fx_addsy = section_symbol (text_section); | |
15640 | *valP += md_pcrel_from (fixP); | |
4d68580a | 15641 | write_insn (buf, insn); |
a7ebbfdf TS |
15642 | } |
15643 | else | |
15644 | { | |
15645 | /* If we got here, we have branch-relaxation disabled, | |
15646 | and there's nothing we can do to fix this instruction | |
15647 | without turning it into a longer sequence. */ | |
15648 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
1661c76c | 15649 | _("branch out of range")); |
252b5132 | 15650 | } |
252b5132 RH |
15651 | break; |
15652 | ||
c9775dde | 15653 | case BFD_RELOC_MIPS16_16_PCREL_S1: |
df58fc94 RS |
15654 | case BFD_RELOC_MICROMIPS_7_PCREL_S1: |
15655 | case BFD_RELOC_MICROMIPS_10_PCREL_S1: | |
15656 | case BFD_RELOC_MICROMIPS_16_PCREL_S1: | |
96e9ba5f | 15657 | gas_assert (!fixP->fx_done); |
9d862524 MR |
15658 | if (fix_bad_cross_mode_branch_p (fixP)) |
15659 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15660 | _("branch to a symbol in another ISA mode")); | |
15661 | else if (fixP->fx_addsy | |
15662 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) | |
15663 | && !bfd_is_abs_section (S_GET_SEGMENT (fixP->fx_addsy)) | |
15664 | && (fixP->fx_offset & 0x1) != 0) | |
15665 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15666 | _("branch to misaligned address (0x%lx)"), | |
15667 | (long) (S_GET_VALUE (fixP->fx_addsy) + fixP->fx_offset)); | |
15668 | else if (HAVE_IN_PLACE_ADDENDS && (fixP->fx_offset & 0x1) != 0) | |
15669 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15670 | _("cannot encode misaligned addend " | |
15671 | "in the relocatable field (0x%lx)"), | |
15672 | (long) fixP->fx_offset); | |
df58fc94 RS |
15673 | break; |
15674 | ||
252b5132 RH |
15675 | case BFD_RELOC_VTABLE_INHERIT: |
15676 | fixP->fx_done = 0; | |
15677 | if (fixP->fx_addsy | |
15678 | && !S_IS_DEFINED (fixP->fx_addsy) | |
15679 | && !S_IS_WEAK (fixP->fx_addsy)) | |
15680 | S_SET_WEAK (fixP->fx_addsy); | |
15681 | break; | |
15682 | ||
2f0c68f2 | 15683 | case BFD_RELOC_NONE: |
252b5132 RH |
15684 | case BFD_RELOC_VTABLE_ENTRY: |
15685 | fixP->fx_done = 0; | |
15686 | break; | |
15687 | ||
15688 | default: | |
b37df7c4 | 15689 | abort (); |
252b5132 | 15690 | } |
a7ebbfdf TS |
15691 | |
15692 | /* Remember value for tc_gen_reloc. */ | |
15693 | fixP->fx_addnumber = *valP; | |
252b5132 RH |
15694 | } |
15695 | ||
252b5132 | 15696 | static symbolS * |
17a2f251 | 15697 | get_symbol (void) |
252b5132 RH |
15698 | { |
15699 | int c; | |
15700 | char *name; | |
15701 | symbolS *p; | |
15702 | ||
d02603dc | 15703 | c = get_symbol_name (&name); |
252b5132 | 15704 | p = (symbolS *) symbol_find_or_make (name); |
d02603dc | 15705 | (void) restore_line_pointer (c); |
252b5132 RH |
15706 | return p; |
15707 | } | |
15708 | ||
742a56fe RS |
15709 | /* Align the current frag to a given power of two. If a particular |
15710 | fill byte should be used, FILL points to an integer that contains | |
15711 | that byte, otherwise FILL is null. | |
15712 | ||
462427c4 RS |
15713 | This function used to have the comment: |
15714 | ||
15715 | The MIPS assembler also automatically adjusts any preceding label. | |
15716 | ||
15717 | The implementation therefore applied the adjustment to a maximum of | |
15718 | one label. However, other label adjustments are applied to batches | |
15719 | of labels, and adjusting just one caused problems when new labels | |
15720 | were added for the sake of debugging or unwind information. | |
15721 | We therefore adjust all preceding labels (given as LABELS) instead. */ | |
252b5132 RH |
15722 | |
15723 | static void | |
462427c4 | 15724 | mips_align (int to, int *fill, struct insn_label_list *labels) |
252b5132 | 15725 | { |
7d10b47d | 15726 | mips_emit_delays (); |
df58fc94 | 15727 | mips_record_compressed_mode (); |
742a56fe RS |
15728 | if (fill == NULL && subseg_text_p (now_seg)) |
15729 | frag_align_code (to, 0); | |
15730 | else | |
15731 | frag_align (to, fill ? *fill : 0, 0); | |
252b5132 | 15732 | record_alignment (now_seg, to); |
462427c4 | 15733 | mips_move_labels (labels, FALSE); |
252b5132 RH |
15734 | } |
15735 | ||
15736 | /* Align to a given power of two. .align 0 turns off the automatic | |
15737 | alignment used by the data creating pseudo-ops. */ | |
15738 | ||
15739 | static void | |
17a2f251 | 15740 | s_align (int x ATTRIBUTE_UNUSED) |
252b5132 | 15741 | { |
742a56fe | 15742 | int temp, fill_value, *fill_ptr; |
49954fb4 | 15743 | long max_alignment = 28; |
252b5132 | 15744 | |
54f4ddb3 | 15745 | /* o Note that the assembler pulls down any immediately preceding label |
252b5132 | 15746 | to the aligned address. |
54f4ddb3 | 15747 | o It's not documented but auto alignment is reinstated by |
252b5132 | 15748 | a .align pseudo instruction. |
54f4ddb3 | 15749 | o Note also that after auto alignment is turned off the mips assembler |
252b5132 | 15750 | issues an error on attempt to assemble an improperly aligned data item. |
54f4ddb3 | 15751 | We don't. */ |
252b5132 RH |
15752 | |
15753 | temp = get_absolute_expression (); | |
15754 | if (temp > max_alignment) | |
1661c76c | 15755 | as_bad (_("alignment too large, %d assumed"), temp = max_alignment); |
252b5132 RH |
15756 | else if (temp < 0) |
15757 | { | |
1661c76c | 15758 | as_warn (_("alignment negative, 0 assumed")); |
252b5132 RH |
15759 | temp = 0; |
15760 | } | |
15761 | if (*input_line_pointer == ',') | |
15762 | { | |
f9419b05 | 15763 | ++input_line_pointer; |
742a56fe RS |
15764 | fill_value = get_absolute_expression (); |
15765 | fill_ptr = &fill_value; | |
252b5132 RH |
15766 | } |
15767 | else | |
742a56fe | 15768 | fill_ptr = 0; |
252b5132 RH |
15769 | if (temp) |
15770 | { | |
a8dbcb85 TS |
15771 | segment_info_type *si = seg_info (now_seg); |
15772 | struct insn_label_list *l = si->label_list; | |
54f4ddb3 | 15773 | /* Auto alignment should be switched on by next section change. */ |
252b5132 | 15774 | auto_align = 1; |
462427c4 | 15775 | mips_align (temp, fill_ptr, l); |
252b5132 RH |
15776 | } |
15777 | else | |
15778 | { | |
15779 | auto_align = 0; | |
15780 | } | |
15781 | ||
15782 | demand_empty_rest_of_line (); | |
15783 | } | |
15784 | ||
252b5132 | 15785 | static void |
17a2f251 | 15786 | s_change_sec (int sec) |
252b5132 RH |
15787 | { |
15788 | segT seg; | |
15789 | ||
252b5132 RH |
15790 | /* The ELF backend needs to know that we are changing sections, so |
15791 | that .previous works correctly. We could do something like check | |
b6ff326e | 15792 | for an obj_section_change_hook macro, but that might be confusing |
252b5132 RH |
15793 | as it would not be appropriate to use it in the section changing |
15794 | functions in read.c, since obj-elf.c intercepts those. FIXME: | |
15795 | This should be cleaner, somehow. */ | |
f3ded42a | 15796 | obj_elf_section_change_hook (); |
252b5132 | 15797 | |
7d10b47d | 15798 | mips_emit_delays (); |
6a32d874 | 15799 | |
252b5132 RH |
15800 | switch (sec) |
15801 | { | |
15802 | case 't': | |
15803 | s_text (0); | |
15804 | break; | |
15805 | case 'd': | |
15806 | s_data (0); | |
15807 | break; | |
15808 | case 'b': | |
15809 | subseg_set (bss_section, (subsegT) get_absolute_expression ()); | |
15810 | demand_empty_rest_of_line (); | |
15811 | break; | |
15812 | ||
15813 | case 'r': | |
4d0d148d TS |
15814 | seg = subseg_new (RDATA_SECTION_NAME, |
15815 | (subsegT) get_absolute_expression ()); | |
f3ded42a RS |
15816 | bfd_set_section_flags (stdoutput, seg, (SEC_ALLOC | SEC_LOAD |
15817 | | SEC_READONLY | SEC_RELOC | |
15818 | | SEC_DATA)); | |
15819 | if (strncmp (TARGET_OS, "elf", 3) != 0) | |
15820 | record_alignment (seg, 4); | |
4d0d148d | 15821 | demand_empty_rest_of_line (); |
252b5132 RH |
15822 | break; |
15823 | ||
15824 | case 's': | |
4d0d148d | 15825 | seg = subseg_new (".sdata", (subsegT) get_absolute_expression ()); |
f3ded42a RS |
15826 | bfd_set_section_flags (stdoutput, seg, |
15827 | SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA); | |
15828 | if (strncmp (TARGET_OS, "elf", 3) != 0) | |
15829 | record_alignment (seg, 4); | |
4d0d148d TS |
15830 | demand_empty_rest_of_line (); |
15831 | break; | |
998b3c36 MR |
15832 | |
15833 | case 'B': | |
15834 | seg = subseg_new (".sbss", (subsegT) get_absolute_expression ()); | |
f3ded42a RS |
15835 | bfd_set_section_flags (stdoutput, seg, SEC_ALLOC); |
15836 | if (strncmp (TARGET_OS, "elf", 3) != 0) | |
15837 | record_alignment (seg, 4); | |
998b3c36 MR |
15838 | demand_empty_rest_of_line (); |
15839 | break; | |
252b5132 RH |
15840 | } |
15841 | ||
15842 | auto_align = 1; | |
15843 | } | |
b34976b6 | 15844 | |
cca86cc8 | 15845 | void |
17a2f251 | 15846 | s_change_section (int ignore ATTRIBUTE_UNUSED) |
cca86cc8 | 15847 | { |
d02603dc | 15848 | char *saved_ilp; |
cca86cc8 | 15849 | char *section_name; |
d02603dc | 15850 | char c, endc; |
684022ea | 15851 | char next_c = 0; |
cca86cc8 SC |
15852 | int section_type; |
15853 | int section_flag; | |
15854 | int section_entry_size; | |
15855 | int section_alignment; | |
b34976b6 | 15856 | |
d02603dc NC |
15857 | saved_ilp = input_line_pointer; |
15858 | endc = get_symbol_name (§ion_name); | |
15859 | c = (endc == '"' ? input_line_pointer[1] : endc); | |
a816d1ed | 15860 | if (c) |
d02603dc | 15861 | next_c = input_line_pointer [(endc == '"' ? 2 : 1)]; |
cca86cc8 | 15862 | |
4cf0dd0d TS |
15863 | /* Do we have .section Name<,"flags">? */ |
15864 | if (c != ',' || (c == ',' && next_c == '"')) | |
cca86cc8 | 15865 | { |
d02603dc NC |
15866 | /* Just after name is now '\0'. */ |
15867 | (void) restore_line_pointer (endc); | |
15868 | input_line_pointer = saved_ilp; | |
cca86cc8 SC |
15869 | obj_elf_section (ignore); |
15870 | return; | |
15871 | } | |
d02603dc NC |
15872 | |
15873 | section_name = xstrdup (section_name); | |
15874 | c = restore_line_pointer (endc); | |
15875 | ||
cca86cc8 SC |
15876 | input_line_pointer++; |
15877 | ||
15878 | /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */ | |
15879 | if (c == ',') | |
15880 | section_type = get_absolute_expression (); | |
15881 | else | |
15882 | section_type = 0; | |
d02603dc | 15883 | |
cca86cc8 SC |
15884 | if (*input_line_pointer++ == ',') |
15885 | section_flag = get_absolute_expression (); | |
15886 | else | |
15887 | section_flag = 0; | |
d02603dc | 15888 | |
cca86cc8 SC |
15889 | if (*input_line_pointer++ == ',') |
15890 | section_entry_size = get_absolute_expression (); | |
15891 | else | |
15892 | section_entry_size = 0; | |
d02603dc | 15893 | |
cca86cc8 SC |
15894 | if (*input_line_pointer++ == ',') |
15895 | section_alignment = get_absolute_expression (); | |
15896 | else | |
15897 | section_alignment = 0; | |
d02603dc | 15898 | |
87975d2a AM |
15899 | /* FIXME: really ignore? */ |
15900 | (void) section_alignment; | |
cca86cc8 | 15901 | |
8ab8a5c8 RS |
15902 | /* When using the generic form of .section (as implemented by obj-elf.c), |
15903 | there's no way to set the section type to SHT_MIPS_DWARF. Users have | |
15904 | traditionally had to fall back on the more common @progbits instead. | |
15905 | ||
15906 | There's nothing really harmful in this, since bfd will correct | |
15907 | SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it | |
708587a4 | 15908 | means that, for backwards compatibility, the special_section entries |
8ab8a5c8 RS |
15909 | for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF. |
15910 | ||
15911 | Even so, we shouldn't force users of the MIPS .section syntax to | |
15912 | incorrectly label the sections as SHT_PROGBITS. The best compromise | |
15913 | seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the | |
15914 | generic type-checking code. */ | |
15915 | if (section_type == SHT_MIPS_DWARF) | |
15916 | section_type = SHT_PROGBITS; | |
15917 | ||
a91e1603 | 15918 | obj_elf_change_section (section_name, section_type, 0, section_flag, |
cca86cc8 | 15919 | section_entry_size, 0, 0, 0); |
a816d1ed AO |
15920 | |
15921 | if (now_seg->name != section_name) | |
15922 | free (section_name); | |
cca86cc8 | 15923 | } |
252b5132 RH |
15924 | |
15925 | void | |
17a2f251 | 15926 | mips_enable_auto_align (void) |
252b5132 RH |
15927 | { |
15928 | auto_align = 1; | |
15929 | } | |
15930 | ||
15931 | static void | |
17a2f251 | 15932 | s_cons (int log_size) |
252b5132 | 15933 | { |
a8dbcb85 TS |
15934 | segment_info_type *si = seg_info (now_seg); |
15935 | struct insn_label_list *l = si->label_list; | |
252b5132 | 15936 | |
7d10b47d | 15937 | mips_emit_delays (); |
252b5132 | 15938 | if (log_size > 0 && auto_align) |
462427c4 | 15939 | mips_align (log_size, 0, l); |
252b5132 | 15940 | cons (1 << log_size); |
a1facbec | 15941 | mips_clear_insn_labels (); |
252b5132 RH |
15942 | } |
15943 | ||
15944 | static void | |
17a2f251 | 15945 | s_float_cons (int type) |
252b5132 | 15946 | { |
a8dbcb85 TS |
15947 | segment_info_type *si = seg_info (now_seg); |
15948 | struct insn_label_list *l = si->label_list; | |
252b5132 | 15949 | |
7d10b47d | 15950 | mips_emit_delays (); |
252b5132 RH |
15951 | |
15952 | if (auto_align) | |
49309057 ILT |
15953 | { |
15954 | if (type == 'd') | |
462427c4 | 15955 | mips_align (3, 0, l); |
49309057 | 15956 | else |
462427c4 | 15957 | mips_align (2, 0, l); |
49309057 | 15958 | } |
252b5132 | 15959 | |
252b5132 | 15960 | float_cons (type); |
a1facbec | 15961 | mips_clear_insn_labels (); |
252b5132 RH |
15962 | } |
15963 | ||
15964 | /* Handle .globl. We need to override it because on Irix 5 you are | |
15965 | permitted to say | |
15966 | .globl foo .text | |
15967 | where foo is an undefined symbol, to mean that foo should be | |
15968 | considered to be the address of a function. */ | |
15969 | ||
15970 | static void | |
17a2f251 | 15971 | s_mips_globl (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
15972 | { |
15973 | char *name; | |
15974 | int c; | |
15975 | symbolS *symbolP; | |
15976 | flagword flag; | |
15977 | ||
8a06b769 | 15978 | do |
252b5132 | 15979 | { |
d02603dc | 15980 | c = get_symbol_name (&name); |
8a06b769 TS |
15981 | symbolP = symbol_find_or_make (name); |
15982 | S_SET_EXTERNAL (symbolP); | |
15983 | ||
252b5132 | 15984 | *input_line_pointer = c; |
d02603dc | 15985 | SKIP_WHITESPACE_AFTER_NAME (); |
252b5132 | 15986 | |
8a06b769 TS |
15987 | /* On Irix 5, every global symbol that is not explicitly labelled as |
15988 | being a function is apparently labelled as being an object. */ | |
15989 | flag = BSF_OBJECT; | |
252b5132 | 15990 | |
8a06b769 TS |
15991 | if (!is_end_of_line[(unsigned char) *input_line_pointer] |
15992 | && (*input_line_pointer != ',')) | |
15993 | { | |
15994 | char *secname; | |
15995 | asection *sec; | |
15996 | ||
d02603dc | 15997 | c = get_symbol_name (&secname); |
8a06b769 TS |
15998 | sec = bfd_get_section_by_name (stdoutput, secname); |
15999 | if (sec == NULL) | |
16000 | as_bad (_("%s: no such section"), secname); | |
d02603dc | 16001 | (void) restore_line_pointer (c); |
8a06b769 TS |
16002 | |
16003 | if (sec != NULL && (sec->flags & SEC_CODE) != 0) | |
16004 | flag = BSF_FUNCTION; | |
16005 | } | |
16006 | ||
16007 | symbol_get_bfdsym (symbolP)->flags |= flag; | |
16008 | ||
16009 | c = *input_line_pointer; | |
16010 | if (c == ',') | |
16011 | { | |
16012 | input_line_pointer++; | |
16013 | SKIP_WHITESPACE (); | |
16014 | if (is_end_of_line[(unsigned char) *input_line_pointer]) | |
16015 | c = '\n'; | |
16016 | } | |
16017 | } | |
16018 | while (c == ','); | |
252b5132 | 16019 | |
252b5132 RH |
16020 | demand_empty_rest_of_line (); |
16021 | } | |
16022 | ||
16023 | static void | |
17a2f251 | 16024 | s_option (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
16025 | { |
16026 | char *opt; | |
16027 | char c; | |
16028 | ||
d02603dc | 16029 | c = get_symbol_name (&opt); |
252b5132 RH |
16030 | |
16031 | if (*opt == 'O') | |
16032 | { | |
16033 | /* FIXME: What does this mean? */ | |
16034 | } | |
41a1578e | 16035 | else if (strncmp (opt, "pic", 3) == 0 && ISDIGIT (opt[3]) && opt[4] == '\0') |
252b5132 RH |
16036 | { |
16037 | int i; | |
16038 | ||
16039 | i = atoi (opt + 3); | |
668c5ebc MR |
16040 | if (i != 0 && i != 2) |
16041 | as_bad (_(".option pic%d not supported"), i); | |
16042 | else if (mips_pic == VXWORKS_PIC) | |
16043 | as_bad (_(".option pic%d not supported in VxWorks PIC mode"), i); | |
16044 | else if (i == 0) | |
252b5132 RH |
16045 | mips_pic = NO_PIC; |
16046 | else if (i == 2) | |
143d77c5 | 16047 | { |
8b828383 | 16048 | mips_pic = SVR4_PIC; |
143d77c5 EC |
16049 | mips_abicalls = TRUE; |
16050 | } | |
252b5132 | 16051 | |
4d0d148d | 16052 | if (mips_pic == SVR4_PIC) |
252b5132 RH |
16053 | { |
16054 | if (g_switch_seen && g_switch_value != 0) | |
16055 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
16056 | g_switch_value = 0; | |
16057 | bfd_set_gp_size (stdoutput, 0); | |
16058 | } | |
16059 | } | |
16060 | else | |
1661c76c | 16061 | as_warn (_("unrecognized option \"%s\""), opt); |
252b5132 | 16062 | |
d02603dc | 16063 | (void) restore_line_pointer (c); |
252b5132 RH |
16064 | demand_empty_rest_of_line (); |
16065 | } | |
16066 | ||
16067 | /* This structure is used to hold a stack of .set values. */ | |
16068 | ||
e972090a NC |
16069 | struct mips_option_stack |
16070 | { | |
252b5132 RH |
16071 | struct mips_option_stack *next; |
16072 | struct mips_set_options options; | |
16073 | }; | |
16074 | ||
16075 | static struct mips_option_stack *mips_opts_stack; | |
16076 | ||
22522f88 MR |
16077 | /* Return status for .set/.module option handling. */ |
16078 | ||
16079 | enum code_option_type | |
16080 | { | |
16081 | /* Unrecognized option. */ | |
16082 | OPTION_TYPE_BAD = -1, | |
16083 | ||
16084 | /* Ordinary option. */ | |
16085 | OPTION_TYPE_NORMAL, | |
16086 | ||
16087 | /* ISA changing option. */ | |
16088 | OPTION_TYPE_ISA | |
16089 | }; | |
16090 | ||
16091 | /* Handle common .set/.module options. Return status indicating option | |
16092 | type. */ | |
16093 | ||
16094 | static enum code_option_type | |
919731af | 16095 | parse_code_option (char * name) |
252b5132 | 16096 | { |
22522f88 | 16097 | bfd_boolean isa_set = FALSE; |
c6278170 | 16098 | const struct mips_ase *ase; |
22522f88 | 16099 | |
919731af | 16100 | if (strncmp (name, "at=", 3) == 0) |
741fe287 MR |
16101 | { |
16102 | char *s = name + 3; | |
16103 | ||
16104 | if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, &mips_opts.at)) | |
1661c76c | 16105 | as_bad (_("unrecognized register name `%s'"), s); |
741fe287 | 16106 | } |
252b5132 | 16107 | else if (strcmp (name, "at") == 0) |
919731af | 16108 | mips_opts.at = ATREG; |
252b5132 | 16109 | else if (strcmp (name, "noat") == 0) |
919731af | 16110 | mips_opts.at = ZERO; |
252b5132 | 16111 | else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0) |
919731af | 16112 | mips_opts.nomove = 0; |
252b5132 | 16113 | else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0) |
919731af | 16114 | mips_opts.nomove = 1; |
252b5132 | 16115 | else if (strcmp (name, "bopt") == 0) |
919731af | 16116 | mips_opts.nobopt = 0; |
252b5132 | 16117 | else if (strcmp (name, "nobopt") == 0) |
919731af | 16118 | mips_opts.nobopt = 1; |
ad3fea08 | 16119 | else if (strcmp (name, "gp=32") == 0) |
bad1aba3 | 16120 | mips_opts.gp = 32; |
ad3fea08 | 16121 | else if (strcmp (name, "gp=64") == 0) |
919731af | 16122 | mips_opts.gp = 64; |
ad3fea08 | 16123 | else if (strcmp (name, "fp=32") == 0) |
0b35dfee | 16124 | mips_opts.fp = 32; |
351cdf24 MF |
16125 | else if (strcmp (name, "fp=xx") == 0) |
16126 | mips_opts.fp = 0; | |
ad3fea08 | 16127 | else if (strcmp (name, "fp=64") == 0) |
919731af | 16128 | mips_opts.fp = 64; |
037b32b9 AN |
16129 | else if (strcmp (name, "softfloat") == 0) |
16130 | mips_opts.soft_float = 1; | |
16131 | else if (strcmp (name, "hardfloat") == 0) | |
16132 | mips_opts.soft_float = 0; | |
16133 | else if (strcmp (name, "singlefloat") == 0) | |
16134 | mips_opts.single_float = 1; | |
16135 | else if (strcmp (name, "doublefloat") == 0) | |
16136 | mips_opts.single_float = 0; | |
351cdf24 MF |
16137 | else if (strcmp (name, "nooddspreg") == 0) |
16138 | mips_opts.oddspreg = 0; | |
16139 | else if (strcmp (name, "oddspreg") == 0) | |
16140 | mips_opts.oddspreg = 1; | |
252b5132 RH |
16141 | else if (strcmp (name, "mips16") == 0 |
16142 | || strcmp (name, "MIPS-16") == 0) | |
919731af | 16143 | mips_opts.mips16 = 1; |
252b5132 RH |
16144 | else if (strcmp (name, "nomips16") == 0 |
16145 | || strcmp (name, "noMIPS-16") == 0) | |
16146 | mips_opts.mips16 = 0; | |
df58fc94 | 16147 | else if (strcmp (name, "micromips") == 0) |
919731af | 16148 | mips_opts.micromips = 1; |
df58fc94 RS |
16149 | else if (strcmp (name, "nomicromips") == 0) |
16150 | mips_opts.micromips = 0; | |
c6278170 RS |
16151 | else if (name[0] == 'n' |
16152 | && name[1] == 'o' | |
16153 | && (ase = mips_lookup_ase (name + 2))) | |
919731af | 16154 | mips_set_ase (ase, &mips_opts, FALSE); |
c6278170 | 16155 | else if ((ase = mips_lookup_ase (name))) |
919731af | 16156 | mips_set_ase (ase, &mips_opts, TRUE); |
1a2c1fad | 16157 | else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0) |
252b5132 | 16158 | { |
1a2c1fad CD |
16159 | /* Permit the user to change the ISA and architecture on the fly. |
16160 | Needless to say, misuse can cause serious problems. */ | |
919731af | 16161 | if (strncmp (name, "arch=", 5) == 0) |
1a2c1fad CD |
16162 | { |
16163 | const struct mips_cpu_info *p; | |
16164 | ||
919731af | 16165 | p = mips_parse_cpu ("internal use", name + 5); |
1a2c1fad CD |
16166 | if (!p) |
16167 | as_bad (_("unknown architecture %s"), name + 5); | |
16168 | else | |
16169 | { | |
16170 | mips_opts.arch = p->cpu; | |
16171 | mips_opts.isa = p->isa; | |
22522f88 | 16172 | isa_set = TRUE; |
1a2c1fad CD |
16173 | } |
16174 | } | |
81a21e38 TS |
16175 | else if (strncmp (name, "mips", 4) == 0) |
16176 | { | |
16177 | const struct mips_cpu_info *p; | |
16178 | ||
919731af | 16179 | p = mips_parse_cpu ("internal use", name); |
81a21e38 TS |
16180 | if (!p) |
16181 | as_bad (_("unknown ISA level %s"), name + 4); | |
16182 | else | |
16183 | { | |
16184 | mips_opts.arch = p->cpu; | |
16185 | mips_opts.isa = p->isa; | |
22522f88 | 16186 | isa_set = TRUE; |
81a21e38 TS |
16187 | } |
16188 | } | |
af7ee8bf | 16189 | else |
81a21e38 | 16190 | as_bad (_("unknown ISA or architecture %s"), name); |
252b5132 RH |
16191 | } |
16192 | else if (strcmp (name, "autoextend") == 0) | |
16193 | mips_opts.noautoextend = 0; | |
16194 | else if (strcmp (name, "noautoextend") == 0) | |
16195 | mips_opts.noautoextend = 1; | |
833794fc MR |
16196 | else if (strcmp (name, "insn32") == 0) |
16197 | mips_opts.insn32 = TRUE; | |
16198 | else if (strcmp (name, "noinsn32") == 0) | |
16199 | mips_opts.insn32 = FALSE; | |
919731af | 16200 | else if (strcmp (name, "sym32") == 0) |
16201 | mips_opts.sym32 = TRUE; | |
16202 | else if (strcmp (name, "nosym32") == 0) | |
16203 | mips_opts.sym32 = FALSE; | |
16204 | else | |
22522f88 MR |
16205 | return OPTION_TYPE_BAD; |
16206 | ||
16207 | return isa_set ? OPTION_TYPE_ISA : OPTION_TYPE_NORMAL; | |
919731af | 16208 | } |
16209 | ||
16210 | /* Handle the .set pseudo-op. */ | |
16211 | ||
16212 | static void | |
16213 | s_mipsset (int x ATTRIBUTE_UNUSED) | |
16214 | { | |
22522f88 | 16215 | enum code_option_type type = OPTION_TYPE_NORMAL; |
919731af | 16216 | char *name = input_line_pointer, ch; |
919731af | 16217 | |
16218 | file_mips_check_options (); | |
16219 | ||
16220 | while (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
16221 | ++input_line_pointer; | |
16222 | ch = *input_line_pointer; | |
16223 | *input_line_pointer = '\0'; | |
16224 | ||
16225 | if (strchr (name, ',')) | |
16226 | { | |
16227 | /* Generic ".set" directive; use the generic handler. */ | |
16228 | *input_line_pointer = ch; | |
16229 | input_line_pointer = name; | |
16230 | s_set (0); | |
16231 | return; | |
16232 | } | |
16233 | ||
16234 | if (strcmp (name, "reorder") == 0) | |
16235 | { | |
16236 | if (mips_opts.noreorder) | |
16237 | end_noreorder (); | |
16238 | } | |
16239 | else if (strcmp (name, "noreorder") == 0) | |
16240 | { | |
16241 | if (!mips_opts.noreorder) | |
16242 | start_noreorder (); | |
16243 | } | |
16244 | else if (strcmp (name, "macro") == 0) | |
16245 | mips_opts.warn_about_macros = 0; | |
16246 | else if (strcmp (name, "nomacro") == 0) | |
16247 | { | |
16248 | if (mips_opts.noreorder == 0) | |
16249 | as_bad (_("`noreorder' must be set before `nomacro'")); | |
16250 | mips_opts.warn_about_macros = 1; | |
16251 | } | |
16252 | else if (strcmp (name, "gp=default") == 0) | |
16253 | mips_opts.gp = file_mips_opts.gp; | |
16254 | else if (strcmp (name, "fp=default") == 0) | |
16255 | mips_opts.fp = file_mips_opts.fp; | |
16256 | else if (strcmp (name, "mips0") == 0 || strcmp (name, "arch=default") == 0) | |
16257 | { | |
16258 | mips_opts.isa = file_mips_opts.isa; | |
16259 | mips_opts.arch = file_mips_opts.arch; | |
16260 | mips_opts.gp = file_mips_opts.gp; | |
16261 | mips_opts.fp = file_mips_opts.fp; | |
16262 | } | |
252b5132 RH |
16263 | else if (strcmp (name, "push") == 0) |
16264 | { | |
16265 | struct mips_option_stack *s; | |
16266 | ||
325801bd | 16267 | s = XNEW (struct mips_option_stack); |
252b5132 RH |
16268 | s->next = mips_opts_stack; |
16269 | s->options = mips_opts; | |
16270 | mips_opts_stack = s; | |
16271 | } | |
16272 | else if (strcmp (name, "pop") == 0) | |
16273 | { | |
16274 | struct mips_option_stack *s; | |
16275 | ||
16276 | s = mips_opts_stack; | |
16277 | if (s == NULL) | |
16278 | as_bad (_(".set pop with no .set push")); | |
16279 | else | |
16280 | { | |
16281 | /* If we're changing the reorder mode we need to handle | |
16282 | delay slots correctly. */ | |
16283 | if (s->options.noreorder && ! mips_opts.noreorder) | |
7d10b47d | 16284 | start_noreorder (); |
252b5132 | 16285 | else if (! s->options.noreorder && mips_opts.noreorder) |
7d10b47d | 16286 | end_noreorder (); |
252b5132 RH |
16287 | |
16288 | mips_opts = s->options; | |
16289 | mips_opts_stack = s->next; | |
16290 | free (s); | |
16291 | } | |
16292 | } | |
22522f88 MR |
16293 | else |
16294 | { | |
16295 | type = parse_code_option (name); | |
16296 | if (type == OPTION_TYPE_BAD) | |
16297 | as_warn (_("tried to set unrecognized symbol: %s\n"), name); | |
16298 | } | |
919731af | 16299 | |
16300 | /* The use of .set [arch|cpu]= historically 'fixes' the width of gp and fp | |
16301 | registers based on what is supported by the arch/cpu. */ | |
22522f88 | 16302 | if (type == OPTION_TYPE_ISA) |
e6559e01 | 16303 | { |
919731af | 16304 | switch (mips_opts.isa) |
16305 | { | |
16306 | case 0: | |
16307 | break; | |
16308 | case ISA_MIPS1: | |
351cdf24 MF |
16309 | /* MIPS I cannot support FPXX. */ |
16310 | mips_opts.fp = 32; | |
16311 | /* fall-through. */ | |
919731af | 16312 | case ISA_MIPS2: |
16313 | case ISA_MIPS32: | |
16314 | case ISA_MIPS32R2: | |
16315 | case ISA_MIPS32R3: | |
16316 | case ISA_MIPS32R5: | |
16317 | mips_opts.gp = 32; | |
351cdf24 MF |
16318 | if (mips_opts.fp != 0) |
16319 | mips_opts.fp = 32; | |
919731af | 16320 | break; |
7361da2c AB |
16321 | case ISA_MIPS32R6: |
16322 | mips_opts.gp = 32; | |
16323 | mips_opts.fp = 64; | |
16324 | break; | |
919731af | 16325 | case ISA_MIPS3: |
16326 | case ISA_MIPS4: | |
16327 | case ISA_MIPS5: | |
16328 | case ISA_MIPS64: | |
16329 | case ISA_MIPS64R2: | |
16330 | case ISA_MIPS64R3: | |
16331 | case ISA_MIPS64R5: | |
7361da2c | 16332 | case ISA_MIPS64R6: |
919731af | 16333 | mips_opts.gp = 64; |
351cdf24 MF |
16334 | if (mips_opts.fp != 0) |
16335 | { | |
16336 | if (mips_opts.arch == CPU_R5900) | |
16337 | mips_opts.fp = 32; | |
16338 | else | |
16339 | mips_opts.fp = 64; | |
16340 | } | |
919731af | 16341 | break; |
16342 | default: | |
16343 | as_bad (_("unknown ISA level %s"), name + 4); | |
16344 | break; | |
16345 | } | |
e6559e01 | 16346 | } |
919731af | 16347 | |
16348 | mips_check_options (&mips_opts, FALSE); | |
16349 | ||
16350 | mips_check_isa_supports_ases (); | |
16351 | *input_line_pointer = ch; | |
16352 | demand_empty_rest_of_line (); | |
16353 | } | |
16354 | ||
16355 | /* Handle the .module pseudo-op. */ | |
16356 | ||
16357 | static void | |
16358 | s_module (int ignore ATTRIBUTE_UNUSED) | |
16359 | { | |
16360 | char *name = input_line_pointer, ch; | |
16361 | ||
16362 | while (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
16363 | ++input_line_pointer; | |
16364 | ch = *input_line_pointer; | |
16365 | *input_line_pointer = '\0'; | |
16366 | ||
16367 | if (!file_mips_opts_checked) | |
252b5132 | 16368 | { |
22522f88 | 16369 | if (parse_code_option (name) == OPTION_TYPE_BAD) |
919731af | 16370 | as_bad (_(".module used with unrecognized symbol: %s\n"), name); |
16371 | ||
16372 | /* Update module level settings from mips_opts. */ | |
16373 | file_mips_opts = mips_opts; | |
252b5132 | 16374 | } |
919731af | 16375 | else |
16376 | as_bad (_(".module is not permitted after generating code")); | |
16377 | ||
252b5132 RH |
16378 | *input_line_pointer = ch; |
16379 | demand_empty_rest_of_line (); | |
16380 | } | |
16381 | ||
16382 | /* Handle the .abicalls pseudo-op. I believe this is equivalent to | |
16383 | .option pic2. It means to generate SVR4 PIC calls. */ | |
16384 | ||
16385 | static void | |
17a2f251 | 16386 | s_abicalls (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
16387 | { |
16388 | mips_pic = SVR4_PIC; | |
143d77c5 | 16389 | mips_abicalls = TRUE; |
4d0d148d TS |
16390 | |
16391 | if (g_switch_seen && g_switch_value != 0) | |
16392 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
16393 | g_switch_value = 0; | |
16394 | ||
252b5132 RH |
16395 | bfd_set_gp_size (stdoutput, 0); |
16396 | demand_empty_rest_of_line (); | |
16397 | } | |
16398 | ||
16399 | /* Handle the .cpload pseudo-op. This is used when generating SVR4 | |
16400 | PIC code. It sets the $gp register for the function based on the | |
16401 | function address, which is in the register named in the argument. | |
16402 | This uses a relocation against _gp_disp, which is handled specially | |
16403 | by the linker. The result is: | |
16404 | lui $gp,%hi(_gp_disp) | |
16405 | addiu $gp,$gp,%lo(_gp_disp) | |
16406 | addu $gp,$gp,.cpload argument | |
aa6975fb ILT |
16407 | The .cpload argument is normally $25 == $t9. |
16408 | ||
16409 | The -mno-shared option changes this to: | |
bbe506e8 TS |
16410 | lui $gp,%hi(__gnu_local_gp) |
16411 | addiu $gp,$gp,%lo(__gnu_local_gp) | |
aa6975fb ILT |
16412 | and the argument is ignored. This saves an instruction, but the |
16413 | resulting code is not position independent; it uses an absolute | |
bbe506e8 TS |
16414 | address for __gnu_local_gp. Thus code assembled with -mno-shared |
16415 | can go into an ordinary executable, but not into a shared library. */ | |
252b5132 RH |
16416 | |
16417 | static void | |
17a2f251 | 16418 | s_cpload (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
16419 | { |
16420 | expressionS ex; | |
aa6975fb ILT |
16421 | int reg; |
16422 | int in_shared; | |
252b5132 | 16423 | |
919731af | 16424 | file_mips_check_options (); |
16425 | ||
6478892d TS |
16426 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
16427 | .cpload is ignored. */ | |
16428 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) | |
252b5132 RH |
16429 | { |
16430 | s_ignore (0); | |
16431 | return; | |
16432 | } | |
16433 | ||
a276b80c MR |
16434 | if (mips_opts.mips16) |
16435 | { | |
16436 | as_bad (_("%s not supported in MIPS16 mode"), ".cpload"); | |
16437 | ignore_rest_of_line (); | |
16438 | return; | |
16439 | } | |
16440 | ||
d3ecfc59 | 16441 | /* .cpload should be in a .set noreorder section. */ |
252b5132 RH |
16442 | if (mips_opts.noreorder == 0) |
16443 | as_warn (_(".cpload not in noreorder section")); | |
16444 | ||
aa6975fb ILT |
16445 | reg = tc_get_register (0); |
16446 | ||
16447 | /* If we need to produce a 64-bit address, we are better off using | |
16448 | the default instruction sequence. */ | |
aed1a261 | 16449 | in_shared = mips_in_shared || HAVE_64BIT_SYMBOLS; |
aa6975fb | 16450 | |
252b5132 | 16451 | ex.X_op = O_symbol; |
bbe506e8 TS |
16452 | ex.X_add_symbol = symbol_find_or_make (in_shared ? "_gp_disp" : |
16453 | "__gnu_local_gp"); | |
252b5132 RH |
16454 | ex.X_op_symbol = NULL; |
16455 | ex.X_add_number = 0; | |
16456 | ||
16457 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ | |
49309057 | 16458 | symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; |
252b5132 | 16459 | |
8a75745d MR |
16460 | mips_mark_labels (); |
16461 | mips_assembling_insn = TRUE; | |
16462 | ||
584892a6 | 16463 | macro_start (); |
67c0d1eb RS |
16464 | macro_build_lui (&ex, mips_gp_register); |
16465 | macro_build (&ex, "addiu", "t,r,j", mips_gp_register, | |
17a2f251 | 16466 | mips_gp_register, BFD_RELOC_LO16); |
aa6975fb ILT |
16467 | if (in_shared) |
16468 | macro_build (NULL, "addu", "d,v,t", mips_gp_register, | |
16469 | mips_gp_register, reg); | |
584892a6 | 16470 | macro_end (); |
252b5132 | 16471 | |
8a75745d | 16472 | mips_assembling_insn = FALSE; |
252b5132 RH |
16473 | demand_empty_rest_of_line (); |
16474 | } | |
16475 | ||
6478892d TS |
16476 | /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is: |
16477 | .cpsetup $reg1, offset|$reg2, label | |
16478 | ||
16479 | If offset is given, this results in: | |
16480 | sd $gp, offset($sp) | |
956cd1d6 | 16481 | lui $gp, %hi(%neg(%gp_rel(label))) |
698b7d9d TS |
16482 | addiu $gp, $gp, %lo(%neg(%gp_rel(label))) |
16483 | daddu $gp, $gp, $reg1 | |
6478892d TS |
16484 | |
16485 | If $reg2 is given, this results in: | |
40fc1451 | 16486 | or $reg2, $gp, $0 |
956cd1d6 | 16487 | lui $gp, %hi(%neg(%gp_rel(label))) |
698b7d9d TS |
16488 | addiu $gp, $gp, %lo(%neg(%gp_rel(label))) |
16489 | daddu $gp, $gp, $reg1 | |
aa6975fb ILT |
16490 | $reg1 is normally $25 == $t9. |
16491 | ||
16492 | The -mno-shared option replaces the last three instructions with | |
16493 | lui $gp,%hi(_gp) | |
54f4ddb3 | 16494 | addiu $gp,$gp,%lo(_gp) */ |
aa6975fb | 16495 | |
6478892d | 16496 | static void |
17a2f251 | 16497 | s_cpsetup (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
16498 | { |
16499 | expressionS ex_off; | |
16500 | expressionS ex_sym; | |
16501 | int reg1; | |
6478892d | 16502 | |
919731af | 16503 | file_mips_check_options (); |
16504 | ||
8586fc66 | 16505 | /* If we are not generating SVR4 PIC code, .cpsetup is ignored. |
6478892d TS |
16506 | We also need NewABI support. */ |
16507 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
16508 | { | |
16509 | s_ignore (0); | |
16510 | return; | |
16511 | } | |
16512 | ||
a276b80c MR |
16513 | if (mips_opts.mips16) |
16514 | { | |
16515 | as_bad (_("%s not supported in MIPS16 mode"), ".cpsetup"); | |
16516 | ignore_rest_of_line (); | |
16517 | return; | |
16518 | } | |
16519 | ||
6478892d TS |
16520 | reg1 = tc_get_register (0); |
16521 | SKIP_WHITESPACE (); | |
16522 | if (*input_line_pointer != ',') | |
16523 | { | |
16524 | as_bad (_("missing argument separator ',' for .cpsetup")); | |
16525 | return; | |
16526 | } | |
16527 | else | |
80245285 | 16528 | ++input_line_pointer; |
6478892d TS |
16529 | SKIP_WHITESPACE (); |
16530 | if (*input_line_pointer == '$') | |
80245285 TS |
16531 | { |
16532 | mips_cpreturn_register = tc_get_register (0); | |
16533 | mips_cpreturn_offset = -1; | |
16534 | } | |
6478892d | 16535 | else |
80245285 TS |
16536 | { |
16537 | mips_cpreturn_offset = get_absolute_expression (); | |
16538 | mips_cpreturn_register = -1; | |
16539 | } | |
6478892d TS |
16540 | SKIP_WHITESPACE (); |
16541 | if (*input_line_pointer != ',') | |
16542 | { | |
16543 | as_bad (_("missing argument separator ',' for .cpsetup")); | |
16544 | return; | |
16545 | } | |
16546 | else | |
f9419b05 | 16547 | ++input_line_pointer; |
6478892d | 16548 | SKIP_WHITESPACE (); |
f21f8242 | 16549 | expression (&ex_sym); |
6478892d | 16550 | |
8a75745d MR |
16551 | mips_mark_labels (); |
16552 | mips_assembling_insn = TRUE; | |
16553 | ||
584892a6 | 16554 | macro_start (); |
6478892d TS |
16555 | if (mips_cpreturn_register == -1) |
16556 | { | |
16557 | ex_off.X_op = O_constant; | |
16558 | ex_off.X_add_symbol = NULL; | |
16559 | ex_off.X_op_symbol = NULL; | |
16560 | ex_off.X_add_number = mips_cpreturn_offset; | |
16561 | ||
67c0d1eb | 16562 | macro_build (&ex_off, "sd", "t,o(b)", mips_gp_register, |
17a2f251 | 16563 | BFD_RELOC_LO16, SP); |
6478892d TS |
16564 | } |
16565 | else | |
40fc1451 | 16566 | move_register (mips_cpreturn_register, mips_gp_register); |
6478892d | 16567 | |
aed1a261 | 16568 | if (mips_in_shared || HAVE_64BIT_SYMBOLS) |
aa6975fb | 16569 | { |
df58fc94 | 16570 | macro_build (&ex_sym, "lui", LUI_FMT, mips_gp_register, |
aa6975fb ILT |
16571 | -1, BFD_RELOC_GPREL16, BFD_RELOC_MIPS_SUB, |
16572 | BFD_RELOC_HI16_S); | |
16573 | ||
16574 | macro_build (&ex_sym, "addiu", "t,r,j", mips_gp_register, | |
16575 | mips_gp_register, -1, BFD_RELOC_GPREL16, | |
16576 | BFD_RELOC_MIPS_SUB, BFD_RELOC_LO16); | |
16577 | ||
16578 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register, | |
16579 | mips_gp_register, reg1); | |
16580 | } | |
16581 | else | |
16582 | { | |
16583 | expressionS ex; | |
16584 | ||
16585 | ex.X_op = O_symbol; | |
4184909a | 16586 | ex.X_add_symbol = symbol_find_or_make ("__gnu_local_gp"); |
aa6975fb ILT |
16587 | ex.X_op_symbol = NULL; |
16588 | ex.X_add_number = 0; | |
6e1304d8 | 16589 | |
aa6975fb ILT |
16590 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ |
16591 | symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; | |
16592 | ||
16593 | macro_build_lui (&ex, mips_gp_register); | |
16594 | macro_build (&ex, "addiu", "t,r,j", mips_gp_register, | |
16595 | mips_gp_register, BFD_RELOC_LO16); | |
16596 | } | |
f21f8242 | 16597 | |
584892a6 | 16598 | macro_end (); |
6478892d | 16599 | |
8a75745d | 16600 | mips_assembling_insn = FALSE; |
6478892d TS |
16601 | demand_empty_rest_of_line (); |
16602 | } | |
16603 | ||
16604 | static void | |
17a2f251 | 16605 | s_cplocal (int ignore ATTRIBUTE_UNUSED) |
6478892d | 16606 | { |
919731af | 16607 | file_mips_check_options (); |
16608 | ||
6478892d | 16609 | /* If we are not generating SVR4 PIC code, or if this is not NewABI code, |
54f4ddb3 | 16610 | .cplocal is ignored. */ |
6478892d TS |
16611 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) |
16612 | { | |
16613 | s_ignore (0); | |
16614 | return; | |
16615 | } | |
16616 | ||
a276b80c MR |
16617 | if (mips_opts.mips16) |
16618 | { | |
16619 | as_bad (_("%s not supported in MIPS16 mode"), ".cplocal"); | |
16620 | ignore_rest_of_line (); | |
16621 | return; | |
16622 | } | |
16623 | ||
6478892d | 16624 | mips_gp_register = tc_get_register (0); |
85b51719 | 16625 | demand_empty_rest_of_line (); |
6478892d TS |
16626 | } |
16627 | ||
252b5132 RH |
16628 | /* Handle the .cprestore pseudo-op. This stores $gp into a given |
16629 | offset from $sp. The offset is remembered, and after making a PIC | |
16630 | call $gp is restored from that location. */ | |
16631 | ||
16632 | static void | |
17a2f251 | 16633 | s_cprestore (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
16634 | { |
16635 | expressionS ex; | |
252b5132 | 16636 | |
919731af | 16637 | file_mips_check_options (); |
16638 | ||
6478892d | 16639 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
c9914766 | 16640 | .cprestore is ignored. */ |
6478892d | 16641 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) |
252b5132 RH |
16642 | { |
16643 | s_ignore (0); | |
16644 | return; | |
16645 | } | |
16646 | ||
a276b80c MR |
16647 | if (mips_opts.mips16) |
16648 | { | |
16649 | as_bad (_("%s not supported in MIPS16 mode"), ".cprestore"); | |
16650 | ignore_rest_of_line (); | |
16651 | return; | |
16652 | } | |
16653 | ||
252b5132 | 16654 | mips_cprestore_offset = get_absolute_expression (); |
7a621144 | 16655 | mips_cprestore_valid = 1; |
252b5132 RH |
16656 | |
16657 | ex.X_op = O_constant; | |
16658 | ex.X_add_symbol = NULL; | |
16659 | ex.X_op_symbol = NULL; | |
16660 | ex.X_add_number = mips_cprestore_offset; | |
16661 | ||
8a75745d MR |
16662 | mips_mark_labels (); |
16663 | mips_assembling_insn = TRUE; | |
16664 | ||
584892a6 | 16665 | macro_start (); |
67c0d1eb RS |
16666 | macro_build_ldst_constoffset (&ex, ADDRESS_STORE_INSN, mips_gp_register, |
16667 | SP, HAVE_64BIT_ADDRESSES); | |
584892a6 | 16668 | macro_end (); |
252b5132 | 16669 | |
8a75745d | 16670 | mips_assembling_insn = FALSE; |
252b5132 RH |
16671 | demand_empty_rest_of_line (); |
16672 | } | |
16673 | ||
6478892d | 16674 | /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset |
67c1ffbe | 16675 | was given in the preceding .cpsetup, it results in: |
6478892d | 16676 | ld $gp, offset($sp) |
76b3015f | 16677 | |
6478892d | 16678 | If a register $reg2 was given there, it results in: |
40fc1451 | 16679 | or $gp, $reg2, $0 */ |
54f4ddb3 | 16680 | |
6478892d | 16681 | static void |
17a2f251 | 16682 | s_cpreturn (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
16683 | { |
16684 | expressionS ex; | |
6478892d | 16685 | |
919731af | 16686 | file_mips_check_options (); |
16687 | ||
6478892d TS |
16688 | /* If we are not generating SVR4 PIC code, .cpreturn is ignored. |
16689 | We also need NewABI support. */ | |
16690 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
16691 | { | |
16692 | s_ignore (0); | |
16693 | return; | |
16694 | } | |
16695 | ||
a276b80c MR |
16696 | if (mips_opts.mips16) |
16697 | { | |
16698 | as_bad (_("%s not supported in MIPS16 mode"), ".cpreturn"); | |
16699 | ignore_rest_of_line (); | |
16700 | return; | |
16701 | } | |
16702 | ||
8a75745d MR |
16703 | mips_mark_labels (); |
16704 | mips_assembling_insn = TRUE; | |
16705 | ||
584892a6 | 16706 | macro_start (); |
6478892d TS |
16707 | if (mips_cpreturn_register == -1) |
16708 | { | |
16709 | ex.X_op = O_constant; | |
16710 | ex.X_add_symbol = NULL; | |
16711 | ex.X_op_symbol = NULL; | |
16712 | ex.X_add_number = mips_cpreturn_offset; | |
16713 | ||
67c0d1eb | 16714 | macro_build (&ex, "ld", "t,o(b)", mips_gp_register, BFD_RELOC_LO16, SP); |
6478892d TS |
16715 | } |
16716 | else | |
40fc1451 SD |
16717 | move_register (mips_gp_register, mips_cpreturn_register); |
16718 | ||
584892a6 | 16719 | macro_end (); |
6478892d | 16720 | |
8a75745d | 16721 | mips_assembling_insn = FALSE; |
6478892d TS |
16722 | demand_empty_rest_of_line (); |
16723 | } | |
16724 | ||
d0f13682 CLT |
16725 | /* Handle a .dtprelword, .dtpreldword, .tprelword, or .tpreldword |
16726 | pseudo-op; DIRSTR says which. The pseudo-op generates a BYTES-size | |
16727 | DTP- or TP-relative relocation of type RTYPE, for use in either DWARF | |
16728 | debug information or MIPS16 TLS. */ | |
741d6ea8 JM |
16729 | |
16730 | static void | |
d0f13682 CLT |
16731 | s_tls_rel_directive (const size_t bytes, const char *dirstr, |
16732 | bfd_reloc_code_real_type rtype) | |
741d6ea8 JM |
16733 | { |
16734 | expressionS ex; | |
16735 | char *p; | |
16736 | ||
16737 | expression (&ex); | |
16738 | ||
16739 | if (ex.X_op != O_symbol) | |
16740 | { | |
1661c76c | 16741 | as_bad (_("unsupported use of %s"), dirstr); |
741d6ea8 JM |
16742 | ignore_rest_of_line (); |
16743 | } | |
16744 | ||
16745 | p = frag_more (bytes); | |
16746 | md_number_to_chars (p, 0, bytes); | |
d0f13682 | 16747 | fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, FALSE, rtype); |
741d6ea8 | 16748 | demand_empty_rest_of_line (); |
de64cffd | 16749 | mips_clear_insn_labels (); |
741d6ea8 JM |
16750 | } |
16751 | ||
16752 | /* Handle .dtprelword. */ | |
16753 | ||
16754 | static void | |
16755 | s_dtprelword (int ignore ATTRIBUTE_UNUSED) | |
16756 | { | |
d0f13682 | 16757 | s_tls_rel_directive (4, ".dtprelword", BFD_RELOC_MIPS_TLS_DTPREL32); |
741d6ea8 JM |
16758 | } |
16759 | ||
16760 | /* Handle .dtpreldword. */ | |
16761 | ||
16762 | static void | |
16763 | s_dtpreldword (int ignore ATTRIBUTE_UNUSED) | |
16764 | { | |
d0f13682 CLT |
16765 | s_tls_rel_directive (8, ".dtpreldword", BFD_RELOC_MIPS_TLS_DTPREL64); |
16766 | } | |
16767 | ||
16768 | /* Handle .tprelword. */ | |
16769 | ||
16770 | static void | |
16771 | s_tprelword (int ignore ATTRIBUTE_UNUSED) | |
16772 | { | |
16773 | s_tls_rel_directive (4, ".tprelword", BFD_RELOC_MIPS_TLS_TPREL32); | |
16774 | } | |
16775 | ||
16776 | /* Handle .tpreldword. */ | |
16777 | ||
16778 | static void | |
16779 | s_tpreldword (int ignore ATTRIBUTE_UNUSED) | |
16780 | { | |
16781 | s_tls_rel_directive (8, ".tpreldword", BFD_RELOC_MIPS_TLS_TPREL64); | |
741d6ea8 JM |
16782 | } |
16783 | ||
6478892d TS |
16784 | /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC |
16785 | code. It sets the offset to use in gp_rel relocations. */ | |
16786 | ||
16787 | static void | |
17a2f251 | 16788 | s_gpvalue (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
16789 | { |
16790 | /* If we are not generating SVR4 PIC code, .gpvalue is ignored. | |
16791 | We also need NewABI support. */ | |
16792 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
16793 | { | |
16794 | s_ignore (0); | |
16795 | return; | |
16796 | } | |
16797 | ||
def2e0dd | 16798 | mips_gprel_offset = get_absolute_expression (); |
6478892d TS |
16799 | |
16800 | demand_empty_rest_of_line (); | |
16801 | } | |
16802 | ||
252b5132 RH |
16803 | /* Handle the .gpword pseudo-op. This is used when generating PIC |
16804 | code. It generates a 32 bit GP relative reloc. */ | |
16805 | ||
16806 | static void | |
17a2f251 | 16807 | s_gpword (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 16808 | { |
a8dbcb85 TS |
16809 | segment_info_type *si; |
16810 | struct insn_label_list *l; | |
252b5132 RH |
16811 | expressionS ex; |
16812 | char *p; | |
16813 | ||
16814 | /* When not generating PIC code, this is treated as .word. */ | |
16815 | if (mips_pic != SVR4_PIC) | |
16816 | { | |
16817 | s_cons (2); | |
16818 | return; | |
16819 | } | |
16820 | ||
a8dbcb85 TS |
16821 | si = seg_info (now_seg); |
16822 | l = si->label_list; | |
7d10b47d | 16823 | mips_emit_delays (); |
252b5132 | 16824 | if (auto_align) |
462427c4 | 16825 | mips_align (2, 0, l); |
252b5132 RH |
16826 | |
16827 | expression (&ex); | |
a1facbec | 16828 | mips_clear_insn_labels (); |
252b5132 RH |
16829 | |
16830 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
16831 | { | |
1661c76c | 16832 | as_bad (_("unsupported use of .gpword")); |
252b5132 RH |
16833 | ignore_rest_of_line (); |
16834 | } | |
16835 | ||
16836 | p = frag_more (4); | |
17a2f251 | 16837 | md_number_to_chars (p, 0, 4); |
b34976b6 | 16838 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, |
cdf6fd85 | 16839 | BFD_RELOC_GPREL32); |
252b5132 RH |
16840 | |
16841 | demand_empty_rest_of_line (); | |
16842 | } | |
16843 | ||
10181a0d | 16844 | static void |
17a2f251 | 16845 | s_gpdword (int ignore ATTRIBUTE_UNUSED) |
10181a0d | 16846 | { |
a8dbcb85 TS |
16847 | segment_info_type *si; |
16848 | struct insn_label_list *l; | |
10181a0d AO |
16849 | expressionS ex; |
16850 | char *p; | |
16851 | ||
16852 | /* When not generating PIC code, this is treated as .dword. */ | |
16853 | if (mips_pic != SVR4_PIC) | |
16854 | { | |
16855 | s_cons (3); | |
16856 | return; | |
16857 | } | |
16858 | ||
a8dbcb85 TS |
16859 | si = seg_info (now_seg); |
16860 | l = si->label_list; | |
7d10b47d | 16861 | mips_emit_delays (); |
10181a0d | 16862 | if (auto_align) |
462427c4 | 16863 | mips_align (3, 0, l); |
10181a0d AO |
16864 | |
16865 | expression (&ex); | |
a1facbec | 16866 | mips_clear_insn_labels (); |
10181a0d AO |
16867 | |
16868 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
16869 | { | |
1661c76c | 16870 | as_bad (_("unsupported use of .gpdword")); |
10181a0d AO |
16871 | ignore_rest_of_line (); |
16872 | } | |
16873 | ||
16874 | p = frag_more (8); | |
17a2f251 | 16875 | md_number_to_chars (p, 0, 8); |
a105a300 | 16876 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, |
6e1304d8 | 16877 | BFD_RELOC_GPREL32)->fx_tcbit = 1; |
10181a0d AO |
16878 | |
16879 | /* GPREL32 composed with 64 gives a 64-bit GP offset. */ | |
6e1304d8 RS |
16880 | fix_new (frag_now, p - frag_now->fr_literal, 8, NULL, 0, |
16881 | FALSE, BFD_RELOC_64)->fx_tcbit = 1; | |
10181a0d AO |
16882 | |
16883 | demand_empty_rest_of_line (); | |
16884 | } | |
16885 | ||
a3f278e2 CM |
16886 | /* Handle the .ehword pseudo-op. This is used when generating unwinding |
16887 | tables. It generates a R_MIPS_EH reloc. */ | |
16888 | ||
16889 | static void | |
16890 | s_ehword (int ignore ATTRIBUTE_UNUSED) | |
16891 | { | |
16892 | expressionS ex; | |
16893 | char *p; | |
16894 | ||
16895 | mips_emit_delays (); | |
16896 | ||
16897 | expression (&ex); | |
16898 | mips_clear_insn_labels (); | |
16899 | ||
16900 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
16901 | { | |
1661c76c | 16902 | as_bad (_("unsupported use of .ehword")); |
a3f278e2 CM |
16903 | ignore_rest_of_line (); |
16904 | } | |
16905 | ||
16906 | p = frag_more (4); | |
16907 | md_number_to_chars (p, 0, 4); | |
16908 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, | |
2f0c68f2 | 16909 | BFD_RELOC_32_PCREL); |
a3f278e2 CM |
16910 | |
16911 | demand_empty_rest_of_line (); | |
16912 | } | |
16913 | ||
252b5132 RH |
16914 | /* Handle the .cpadd pseudo-op. This is used when dealing with switch |
16915 | tables in SVR4 PIC code. */ | |
16916 | ||
16917 | static void | |
17a2f251 | 16918 | s_cpadd (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 16919 | { |
252b5132 RH |
16920 | int reg; |
16921 | ||
919731af | 16922 | file_mips_check_options (); |
16923 | ||
10181a0d AO |
16924 | /* This is ignored when not generating SVR4 PIC code. */ |
16925 | if (mips_pic != SVR4_PIC) | |
252b5132 RH |
16926 | { |
16927 | s_ignore (0); | |
16928 | return; | |
16929 | } | |
16930 | ||
8a75745d MR |
16931 | mips_mark_labels (); |
16932 | mips_assembling_insn = TRUE; | |
16933 | ||
252b5132 | 16934 | /* Add $gp to the register named as an argument. */ |
584892a6 | 16935 | macro_start (); |
252b5132 | 16936 | reg = tc_get_register (0); |
67c0d1eb | 16937 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register); |
584892a6 | 16938 | macro_end (); |
252b5132 | 16939 | |
8a75745d | 16940 | mips_assembling_insn = FALSE; |
bdaaa2e1 | 16941 | demand_empty_rest_of_line (); |
252b5132 RH |
16942 | } |
16943 | ||
16944 | /* Handle the .insn pseudo-op. This marks instruction labels in | |
df58fc94 | 16945 | mips16/micromips mode. This permits the linker to handle them specially, |
252b5132 RH |
16946 | such as generating jalx instructions when needed. We also make |
16947 | them odd for the duration of the assembly, in order to generate the | |
16948 | right sort of code. We will make them even in the adjust_symtab | |
16949 | routine, while leaving them marked. This is convenient for the | |
16950 | debugger and the disassembler. The linker knows to make them odd | |
16951 | again. */ | |
16952 | ||
16953 | static void | |
17a2f251 | 16954 | s_insn (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 16955 | { |
7bb01e2d MR |
16956 | file_mips_check_options (); |
16957 | file_ase_mips16 |= mips_opts.mips16; | |
16958 | file_ase_micromips |= mips_opts.micromips; | |
16959 | ||
df58fc94 | 16960 | mips_mark_labels (); |
252b5132 RH |
16961 | |
16962 | demand_empty_rest_of_line (); | |
16963 | } | |
16964 | ||
ba92f887 MR |
16965 | /* Handle the .nan pseudo-op. */ |
16966 | ||
16967 | static void | |
16968 | s_nan (int ignore ATTRIBUTE_UNUSED) | |
16969 | { | |
16970 | static const char str_legacy[] = "legacy"; | |
16971 | static const char str_2008[] = "2008"; | |
16972 | size_t i; | |
16973 | ||
16974 | for (i = 0; !is_end_of_line[(unsigned char) input_line_pointer[i]]; i++); | |
16975 | ||
16976 | if (i == sizeof (str_2008) - 1 | |
16977 | && memcmp (input_line_pointer, str_2008, i) == 0) | |
7361da2c | 16978 | mips_nan2008 = 1; |
ba92f887 MR |
16979 | else if (i == sizeof (str_legacy) - 1 |
16980 | && memcmp (input_line_pointer, str_legacy, i) == 0) | |
7361da2c AB |
16981 | { |
16982 | if (ISA_HAS_LEGACY_NAN (file_mips_opts.isa)) | |
16983 | mips_nan2008 = 0; | |
16984 | else | |
16985 | as_bad (_("`%s' does not support legacy NaN"), | |
16986 | mips_cpu_info_from_isa (file_mips_opts.isa)->name); | |
16987 | } | |
ba92f887 | 16988 | else |
1661c76c | 16989 | as_bad (_("bad .nan directive")); |
ba92f887 MR |
16990 | |
16991 | input_line_pointer += i; | |
16992 | demand_empty_rest_of_line (); | |
16993 | } | |
16994 | ||
754e2bb9 RS |
16995 | /* Handle a .stab[snd] directive. Ideally these directives would be |
16996 | implemented in a transparent way, so that removing them would not | |
16997 | have any effect on the generated instructions. However, s_stab | |
16998 | internally changes the section, so in practice we need to decide | |
16999 | now whether the preceding label marks compressed code. We do not | |
17000 | support changing the compression mode of a label after a .stab* | |
17001 | directive, such as in: | |
17002 | ||
17003 | foo: | |
134c0c8b | 17004 | .stabs ... |
754e2bb9 RS |
17005 | .set mips16 |
17006 | ||
17007 | so the current mode wins. */ | |
252b5132 RH |
17008 | |
17009 | static void | |
17a2f251 | 17010 | s_mips_stab (int type) |
252b5132 | 17011 | { |
754e2bb9 | 17012 | mips_mark_labels (); |
252b5132 RH |
17013 | s_stab (type); |
17014 | } | |
17015 | ||
54f4ddb3 | 17016 | /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */ |
252b5132 RH |
17017 | |
17018 | static void | |
17a2f251 | 17019 | s_mips_weakext (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
17020 | { |
17021 | char *name; | |
17022 | int c; | |
17023 | symbolS *symbolP; | |
17024 | expressionS exp; | |
17025 | ||
d02603dc | 17026 | c = get_symbol_name (&name); |
252b5132 RH |
17027 | symbolP = symbol_find_or_make (name); |
17028 | S_SET_WEAK (symbolP); | |
17029 | *input_line_pointer = c; | |
17030 | ||
d02603dc | 17031 | SKIP_WHITESPACE_AFTER_NAME (); |
252b5132 RH |
17032 | |
17033 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
17034 | { | |
17035 | if (S_IS_DEFINED (symbolP)) | |
17036 | { | |
20203fb9 | 17037 | as_bad (_("ignoring attempt to redefine symbol %s"), |
252b5132 RH |
17038 | S_GET_NAME (symbolP)); |
17039 | ignore_rest_of_line (); | |
17040 | return; | |
17041 | } | |
bdaaa2e1 | 17042 | |
252b5132 RH |
17043 | if (*input_line_pointer == ',') |
17044 | { | |
17045 | ++input_line_pointer; | |
17046 | SKIP_WHITESPACE (); | |
17047 | } | |
bdaaa2e1 | 17048 | |
252b5132 RH |
17049 | expression (&exp); |
17050 | if (exp.X_op != O_symbol) | |
17051 | { | |
20203fb9 | 17052 | as_bad (_("bad .weakext directive")); |
98d3f06f | 17053 | ignore_rest_of_line (); |
252b5132 RH |
17054 | return; |
17055 | } | |
49309057 | 17056 | symbol_set_value_expression (symbolP, &exp); |
252b5132 RH |
17057 | } |
17058 | ||
17059 | demand_empty_rest_of_line (); | |
17060 | } | |
17061 | ||
17062 | /* Parse a register string into a number. Called from the ECOFF code | |
17063 | to parse .frame. The argument is non-zero if this is the frame | |
17064 | register, so that we can record it in mips_frame_reg. */ | |
17065 | ||
17066 | int | |
17a2f251 | 17067 | tc_get_register (int frame) |
252b5132 | 17068 | { |
707bfff6 | 17069 | unsigned int reg; |
252b5132 RH |
17070 | |
17071 | SKIP_WHITESPACE (); | |
707bfff6 TS |
17072 | if (! reg_lookup (&input_line_pointer, RWARN | RTYPE_NUM | RTYPE_GP, ®)) |
17073 | reg = 0; | |
252b5132 | 17074 | if (frame) |
7a621144 DJ |
17075 | { |
17076 | mips_frame_reg = reg != 0 ? reg : SP; | |
17077 | mips_frame_reg_valid = 1; | |
17078 | mips_cprestore_valid = 0; | |
17079 | } | |
252b5132 RH |
17080 | return reg; |
17081 | } | |
17082 | ||
17083 | valueT | |
17a2f251 | 17084 | md_section_align (asection *seg, valueT addr) |
252b5132 RH |
17085 | { |
17086 | int align = bfd_get_section_alignment (stdoutput, seg); | |
17087 | ||
f3ded42a RS |
17088 | /* We don't need to align ELF sections to the full alignment. |
17089 | However, Irix 5 may prefer that we align them at least to a 16 | |
17090 | byte boundary. We don't bother to align the sections if we | |
17091 | are targeted for an embedded system. */ | |
17092 | if (strncmp (TARGET_OS, "elf", 3) == 0) | |
17093 | return addr; | |
17094 | if (align > 4) | |
17095 | align = 4; | |
252b5132 | 17096 | |
8d3842cd | 17097 | return ((addr + (1 << align) - 1) & -(1 << align)); |
252b5132 RH |
17098 | } |
17099 | ||
17100 | /* Utility routine, called from above as well. If called while the | |
17101 | input file is still being read, it's only an approximation. (For | |
17102 | example, a symbol may later become defined which appeared to be | |
17103 | undefined earlier.) */ | |
17104 | ||
17105 | static int | |
17a2f251 | 17106 | nopic_need_relax (symbolS *sym, int before_relaxing) |
252b5132 RH |
17107 | { |
17108 | if (sym == 0) | |
17109 | return 0; | |
17110 | ||
4d0d148d | 17111 | if (g_switch_value > 0) |
252b5132 RH |
17112 | { |
17113 | const char *symname; | |
17114 | int change; | |
17115 | ||
c9914766 | 17116 | /* Find out whether this symbol can be referenced off the $gp |
252b5132 RH |
17117 | register. It can be if it is smaller than the -G size or if |
17118 | it is in the .sdata or .sbss section. Certain symbols can | |
c9914766 | 17119 | not be referenced off the $gp, although it appears as though |
252b5132 RH |
17120 | they can. */ |
17121 | symname = S_GET_NAME (sym); | |
17122 | if (symname != (const char *) NULL | |
17123 | && (strcmp (symname, "eprol") == 0 | |
17124 | || strcmp (symname, "etext") == 0 | |
17125 | || strcmp (symname, "_gp") == 0 | |
17126 | || strcmp (symname, "edata") == 0 | |
17127 | || strcmp (symname, "_fbss") == 0 | |
17128 | || strcmp (symname, "_fdata") == 0 | |
17129 | || strcmp (symname, "_ftext") == 0 | |
17130 | || strcmp (symname, "end") == 0 | |
17131 | || strcmp (symname, "_gp_disp") == 0)) | |
17132 | change = 1; | |
17133 | else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym)) | |
17134 | && (0 | |
17135 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 ILT |
17136 | || (symbol_get_obj (sym)->ecoff_extern_size != 0 |
17137 | && (symbol_get_obj (sym)->ecoff_extern_size | |
17138 | <= g_switch_value)) | |
252b5132 RH |
17139 | #endif |
17140 | /* We must defer this decision until after the whole | |
17141 | file has been read, since there might be a .extern | |
17142 | after the first use of this symbol. */ | |
17143 | || (before_relaxing | |
17144 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 | 17145 | && symbol_get_obj (sym)->ecoff_extern_size == 0 |
252b5132 RH |
17146 | #endif |
17147 | && S_GET_VALUE (sym) == 0) | |
17148 | || (S_GET_VALUE (sym) != 0 | |
17149 | && S_GET_VALUE (sym) <= g_switch_value))) | |
17150 | change = 0; | |
17151 | else | |
17152 | { | |
17153 | const char *segname; | |
17154 | ||
17155 | segname = segment_name (S_GET_SEGMENT (sym)); | |
9c2799c2 | 17156 | gas_assert (strcmp (segname, ".lit8") != 0 |
252b5132 RH |
17157 | && strcmp (segname, ".lit4") != 0); |
17158 | change = (strcmp (segname, ".sdata") != 0 | |
fba2b7f9 GK |
17159 | && strcmp (segname, ".sbss") != 0 |
17160 | && strncmp (segname, ".sdata.", 7) != 0 | |
d4dc2f22 TS |
17161 | && strncmp (segname, ".sbss.", 6) != 0 |
17162 | && strncmp (segname, ".gnu.linkonce.sb.", 17) != 0 | |
fba2b7f9 | 17163 | && strncmp (segname, ".gnu.linkonce.s.", 16) != 0); |
252b5132 RH |
17164 | } |
17165 | return change; | |
17166 | } | |
17167 | else | |
c9914766 | 17168 | /* We are not optimizing for the $gp register. */ |
252b5132 RH |
17169 | return 1; |
17170 | } | |
17171 | ||
5919d012 RS |
17172 | |
17173 | /* Return true if the given symbol should be considered local for SVR4 PIC. */ | |
17174 | ||
17175 | static bfd_boolean | |
9e009953 | 17176 | pic_need_relax (symbolS *sym) |
5919d012 RS |
17177 | { |
17178 | asection *symsec; | |
5919d012 RS |
17179 | |
17180 | /* Handle the case of a symbol equated to another symbol. */ | |
17181 | while (symbol_equated_reloc_p (sym)) | |
17182 | { | |
17183 | symbolS *n; | |
17184 | ||
5f0fe04b | 17185 | /* It's possible to get a loop here in a badly written program. */ |
5919d012 RS |
17186 | n = symbol_get_value_expression (sym)->X_add_symbol; |
17187 | if (n == sym) | |
17188 | break; | |
17189 | sym = n; | |
17190 | } | |
17191 | ||
df1f3cda DD |
17192 | if (symbol_section_p (sym)) |
17193 | return TRUE; | |
17194 | ||
5919d012 RS |
17195 | symsec = S_GET_SEGMENT (sym); |
17196 | ||
5919d012 | 17197 | /* This must duplicate the test in adjust_reloc_syms. */ |
45dfa85a AM |
17198 | return (!bfd_is_und_section (symsec) |
17199 | && !bfd_is_abs_section (symsec) | |
5f0fe04b | 17200 | && !bfd_is_com_section (symsec) |
5919d012 | 17201 | /* A global or weak symbol is treated as external. */ |
f3ded42a | 17202 | && (!S_IS_WEAK (sym) && !S_IS_EXTERNAL (sym))); |
5919d012 | 17203 | } |
14f72d45 MR |
17204 | \f |
17205 | /* Given a MIPS16 variant frag FRAGP and PC-relative operand PCREL_OP | |
17206 | convert a section-relative value VAL to the equivalent PC-relative | |
17207 | value. */ | |
17208 | ||
17209 | static offsetT | |
17210 | mips16_pcrel_val (fragS *fragp, const struct mips_pcrel_operand *pcrel_op, | |
17211 | offsetT val, long stretch) | |
17212 | { | |
17213 | fragS *sym_frag; | |
17214 | addressT addr; | |
17215 | ||
17216 | gas_assert (pcrel_op->root.root.type == OP_PCREL); | |
17217 | ||
17218 | sym_frag = symbol_get_frag (fragp->fr_symbol); | |
17219 | ||
17220 | /* If the relax_marker of the symbol fragment differs from the | |
17221 | relax_marker of this fragment, we have not yet adjusted the | |
17222 | symbol fragment fr_address. We want to add in STRETCH in | |
17223 | order to get a better estimate of the address. This | |
17224 | particularly matters because of the shift bits. */ | |
17225 | if (stretch != 0 && sym_frag->relax_marker != fragp->relax_marker) | |
17226 | { | |
17227 | fragS *f; | |
17228 | ||
17229 | /* Adjust stretch for any alignment frag. Note that if have | |
17230 | been expanding the earlier code, the symbol may be | |
17231 | defined in what appears to be an earlier frag. FIXME: | |
17232 | This doesn't handle the fr_subtype field, which specifies | |
17233 | a maximum number of bytes to skip when doing an | |
17234 | alignment. */ | |
17235 | for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next) | |
17236 | { | |
17237 | if (f->fr_type == rs_align || f->fr_type == rs_align_code) | |
17238 | { | |
17239 | if (stretch < 0) | |
17240 | stretch = -(-stretch & ~((1 << (int) f->fr_offset) - 1)); | |
17241 | else | |
17242 | stretch &= ~((1 << (int) f->fr_offset) - 1); | |
17243 | if (stretch == 0) | |
17244 | break; | |
17245 | } | |
17246 | } | |
17247 | if (f != NULL) | |
17248 | val += stretch; | |
17249 | } | |
17250 | ||
17251 | addr = fragp->fr_address + fragp->fr_fix; | |
17252 | ||
17253 | /* The base address rules are complicated. The base address of | |
17254 | a branch is the following instruction. The base address of a | |
17255 | PC relative load or add is the instruction itself, but if it | |
17256 | is in a delay slot (in which case it can not be extended) use | |
17257 | the address of the instruction whose delay slot it is in. */ | |
17258 | if (pcrel_op->include_isa_bit) | |
17259 | { | |
17260 | addr += 2; | |
17261 | ||
17262 | /* If we are currently assuming that this frag should be | |
17263 | extended, then the current address is two bytes higher. */ | |
17264 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
17265 | addr += 2; | |
17266 | ||
17267 | /* Ignore the low bit in the target, since it will be set | |
17268 | for a text label. */ | |
17269 | val &= -2; | |
17270 | } | |
17271 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) | |
17272 | addr -= 4; | |
17273 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
17274 | addr -= 2; | |
5919d012 | 17275 | |
14f72d45 MR |
17276 | val -= addr & -(1 << pcrel_op->align_log2); |
17277 | ||
17278 | return val; | |
17279 | } | |
5919d012 | 17280 | |
252b5132 RH |
17281 | /* Given a mips16 variant frag FRAGP, return non-zero if it needs an |
17282 | extended opcode. SEC is the section the frag is in. */ | |
17283 | ||
17284 | static int | |
17a2f251 | 17285 | mips16_extended_frag (fragS *fragp, asection *sec, long stretch) |
252b5132 | 17286 | { |
3ccad066 | 17287 | const struct mips_int_operand *operand; |
252b5132 | 17288 | offsetT val; |
252b5132 | 17289 | segT symsec; |
14f72d45 | 17290 | int type; |
252b5132 RH |
17291 | |
17292 | if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype)) | |
17293 | return 0; | |
17294 | if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype)) | |
17295 | return 1; | |
17296 | ||
88a7ef16 | 17297 | symsec = S_GET_SEGMENT (fragp->fr_symbol); |
252b5132 | 17298 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); |
3ccad066 | 17299 | operand = mips16_immed_operand (type, FALSE); |
88a7ef16 MR |
17300 | if (S_FORCE_RELOC (fragp->fr_symbol, TRUE) |
17301 | || (operand->root.type == OP_PCREL | |
17302 | ? sec != symsec | |
17303 | : !bfd_is_abs_section (symsec))) | |
17304 | return 1; | |
252b5132 | 17305 | |
88a7ef16 | 17306 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; |
252b5132 | 17307 | |
3ccad066 | 17308 | if (operand->root.type == OP_PCREL) |
252b5132 | 17309 | { |
3ccad066 | 17310 | const struct mips_pcrel_operand *pcrel_op; |
3ccad066 | 17311 | offsetT maxtiny; |
252b5132 | 17312 | |
1425c41d | 17313 | if (RELAX_MIPS16_ALWAYS_EXTENDED (fragp->fr_subtype)) |
88a7ef16 | 17314 | return 1; |
252b5132 | 17315 | |
88a7ef16 | 17316 | pcrel_op = (const struct mips_pcrel_operand *) operand; |
14f72d45 | 17317 | val = mips16_pcrel_val (fragp, pcrel_op, val, stretch); |
252b5132 RH |
17318 | |
17319 | /* If any of the shifted bits are set, we must use an extended | |
17320 | opcode. If the address depends on the size of this | |
17321 | instruction, this can lead to a loop, so we arrange to always | |
88a7ef16 MR |
17322 | use an extended opcode. */ |
17323 | if ((val & ((1 << operand->shift) - 1)) != 0) | |
252b5132 RH |
17324 | { |
17325 | fragp->fr_subtype = | |
1425c41d | 17326 | RELAX_MIPS16_MARK_ALWAYS_EXTENDED (fragp->fr_subtype); |
252b5132 RH |
17327 | return 1; |
17328 | } | |
17329 | ||
17330 | /* If we are about to mark a frag as extended because the value | |
3ccad066 RS |
17331 | is precisely the next value above maxtiny, then there is a |
17332 | chance of an infinite loop as in the following code: | |
252b5132 RH |
17333 | la $4,foo |
17334 | .skip 1020 | |
17335 | .align 2 | |
17336 | foo: | |
17337 | In this case when the la is extended, foo is 0x3fc bytes | |
17338 | away, so the la can be shrunk, but then foo is 0x400 away, so | |
17339 | the la must be extended. To avoid this loop, we mark the | |
17340 | frag as extended if it was small, and is about to become | |
3ccad066 RS |
17341 | extended with the next value above maxtiny. */ |
17342 | maxtiny = mips_int_operand_max (operand); | |
17343 | if (val == maxtiny + (1 << operand->shift) | |
88a7ef16 | 17344 | && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) |
252b5132 RH |
17345 | { |
17346 | fragp->fr_subtype = | |
1425c41d | 17347 | RELAX_MIPS16_MARK_ALWAYS_EXTENDED (fragp->fr_subtype); |
252b5132 RH |
17348 | return 1; |
17349 | } | |
17350 | } | |
252b5132 | 17351 | |
3ccad066 | 17352 | return !mips16_immed_in_range_p (operand, BFD_RELOC_UNUSED, val); |
252b5132 RH |
17353 | } |
17354 | ||
8507b6e7 MR |
17355 | /* Given a MIPS16 variant frag FRAGP, return non-zero if it needs |
17356 | macro expansion. SEC is the section the frag is in. We only | |
17357 | support PC-relative instructions (LA, DLA, LW, LD) here, in | |
17358 | non-PIC code using 32-bit addressing. */ | |
17359 | ||
17360 | static int | |
17361 | mips16_macro_frag (fragS *fragp, asection *sec, long stretch) | |
17362 | { | |
17363 | const struct mips_pcrel_operand *pcrel_op; | |
17364 | const struct mips_int_operand *operand; | |
17365 | offsetT val; | |
17366 | segT symsec; | |
17367 | int type; | |
17368 | ||
17369 | gas_assert (!RELAX_MIPS16_USER_SMALL (fragp->fr_subtype)); | |
17370 | ||
17371 | if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype)) | |
17372 | return 0; | |
17373 | if (!RELAX_MIPS16_SYM32 (fragp->fr_subtype)) | |
17374 | return 0; | |
17375 | ||
17376 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
17377 | switch (type) | |
17378 | { | |
17379 | case 'A': | |
17380 | case 'B': | |
17381 | case 'E': | |
17382 | symsec = S_GET_SEGMENT (fragp->fr_symbol); | |
17383 | if (bfd_is_abs_section (symsec)) | |
17384 | return 1; | |
17385 | if (RELAX_MIPS16_PIC (fragp->fr_subtype)) | |
17386 | return 0; | |
17387 | if (S_FORCE_RELOC (fragp->fr_symbol, TRUE) || sec != symsec) | |
17388 | return 1; | |
17389 | ||
17390 | operand = mips16_immed_operand (type, TRUE); | |
17391 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; | |
17392 | pcrel_op = (const struct mips_pcrel_operand *) operand; | |
17393 | val = mips16_pcrel_val (fragp, pcrel_op, val, stretch); | |
17394 | ||
17395 | return !mips16_immed_in_range_p (operand, BFD_RELOC_UNUSED, val); | |
17396 | ||
17397 | default: | |
17398 | return 0; | |
17399 | } | |
17400 | } | |
17401 | ||
4a6a3df4 AO |
17402 | /* Compute the length of a branch sequence, and adjust the |
17403 | RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the | |
17404 | worst-case length is computed, with UPDATE being used to indicate | |
17405 | whether an unconditional (-1), branch-likely (+1) or regular (0) | |
17406 | branch is to be computed. */ | |
17407 | static int | |
17a2f251 | 17408 | relaxed_branch_length (fragS *fragp, asection *sec, int update) |
4a6a3df4 | 17409 | { |
b34976b6 | 17410 | bfd_boolean toofar; |
4a6a3df4 AO |
17411 | int length; |
17412 | ||
17413 | if (fragp | |
17414 | && S_IS_DEFINED (fragp->fr_symbol) | |
991f40a9 | 17415 | && !S_IS_WEAK (fragp->fr_symbol) |
4a6a3df4 AO |
17416 | && sec == S_GET_SEGMENT (fragp->fr_symbol)) |
17417 | { | |
17418 | addressT addr; | |
17419 | offsetT val; | |
17420 | ||
17421 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; | |
17422 | ||
17423 | addr = fragp->fr_address + fragp->fr_fix + 4; | |
17424 | ||
17425 | val -= addr; | |
17426 | ||
17427 | toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2); | |
17428 | } | |
4a6a3df4 | 17429 | else |
c1f61bd2 MR |
17430 | /* If the symbol is not defined or it's in a different segment, |
17431 | we emit the long sequence. */ | |
b34976b6 | 17432 | toofar = TRUE; |
4a6a3df4 AO |
17433 | |
17434 | if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) | |
17435 | fragp->fr_subtype | |
66b3e8da | 17436 | = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp->fr_subtype), |
ce8ad872 | 17437 | RELAX_BRANCH_PIC (fragp->fr_subtype), |
66b3e8da | 17438 | RELAX_BRANCH_UNCOND (fragp->fr_subtype), |
4a6a3df4 AO |
17439 | RELAX_BRANCH_LIKELY (fragp->fr_subtype), |
17440 | RELAX_BRANCH_LINK (fragp->fr_subtype), | |
17441 | toofar); | |
17442 | ||
17443 | length = 4; | |
17444 | if (toofar) | |
17445 | { | |
17446 | if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0)) | |
17447 | length += 8; | |
17448 | ||
ce8ad872 | 17449 | if (!fragp || RELAX_BRANCH_PIC (fragp->fr_subtype)) |
4a6a3df4 AO |
17450 | { |
17451 | /* Additional space for PIC loading of target address. */ | |
17452 | length += 8; | |
17453 | if (mips_opts.isa == ISA_MIPS1) | |
17454 | /* Additional space for $at-stabilizing nop. */ | |
17455 | length += 4; | |
17456 | } | |
17457 | ||
17458 | /* If branch is conditional. */ | |
17459 | if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0)) | |
17460 | length += 8; | |
17461 | } | |
b34976b6 | 17462 | |
4a6a3df4 AO |
17463 | return length; |
17464 | } | |
17465 | ||
7bd374a4 MR |
17466 | /* Get a FRAG's branch instruction delay slot size, either from the |
17467 | short-delay-slot bit of a branch-and-link instruction if AL is TRUE, | |
17468 | or SHORT_INSN_SIZE otherwise. */ | |
17469 | ||
17470 | static int | |
17471 | frag_branch_delay_slot_size (fragS *fragp, bfd_boolean al, int short_insn_size) | |
17472 | { | |
17473 | char *buf = fragp->fr_literal + fragp->fr_fix; | |
17474 | ||
17475 | if (al) | |
17476 | return (read_compressed_insn (buf, 4) & 0x02000000) ? 2 : 4; | |
17477 | else | |
17478 | return short_insn_size; | |
17479 | } | |
17480 | ||
df58fc94 RS |
17481 | /* Compute the length of a branch sequence, and adjust the |
17482 | RELAX_MICROMIPS_TOOFAR32 bit accordingly. If FRAGP is NULL, the | |
17483 | worst-case length is computed, with UPDATE being used to indicate | |
17484 | whether an unconditional (-1), or regular (0) branch is to be | |
17485 | computed. */ | |
17486 | ||
17487 | static int | |
17488 | relaxed_micromips_32bit_branch_length (fragS *fragp, asection *sec, int update) | |
17489 | { | |
7bd374a4 MR |
17490 | bfd_boolean insn32 = TRUE; |
17491 | bfd_boolean nods = TRUE; | |
ce8ad872 | 17492 | bfd_boolean pic = TRUE; |
7bd374a4 MR |
17493 | bfd_boolean al = TRUE; |
17494 | int short_insn_size; | |
df58fc94 RS |
17495 | bfd_boolean toofar; |
17496 | int length; | |
17497 | ||
7bd374a4 MR |
17498 | if (fragp) |
17499 | { | |
17500 | insn32 = RELAX_MICROMIPS_INSN32 (fragp->fr_subtype); | |
17501 | nods = RELAX_MICROMIPS_NODS (fragp->fr_subtype); | |
ce8ad872 | 17502 | pic = RELAX_MICROMIPS_PIC (fragp->fr_subtype); |
7bd374a4 MR |
17503 | al = RELAX_MICROMIPS_LINK (fragp->fr_subtype); |
17504 | } | |
17505 | short_insn_size = insn32 ? 4 : 2; | |
17506 | ||
df58fc94 RS |
17507 | if (fragp |
17508 | && S_IS_DEFINED (fragp->fr_symbol) | |
991f40a9 | 17509 | && !S_IS_WEAK (fragp->fr_symbol) |
df58fc94 RS |
17510 | && sec == S_GET_SEGMENT (fragp->fr_symbol)) |
17511 | { | |
17512 | addressT addr; | |
17513 | offsetT val; | |
17514 | ||
17515 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; | |
17516 | /* Ignore the low bit in the target, since it will be set | |
17517 | for a text label. */ | |
17518 | if ((val & 1) != 0) | |
17519 | --val; | |
17520 | ||
17521 | addr = fragp->fr_address + fragp->fr_fix + 4; | |
17522 | ||
17523 | val -= addr; | |
17524 | ||
17525 | toofar = val < - (0x8000 << 1) || val >= (0x8000 << 1); | |
17526 | } | |
df58fc94 | 17527 | else |
c1f61bd2 MR |
17528 | /* If the symbol is not defined or it's in a different segment, |
17529 | we emit the long sequence. */ | |
df58fc94 RS |
17530 | toofar = TRUE; |
17531 | ||
17532 | if (fragp && update | |
17533 | && toofar != RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype)) | |
17534 | fragp->fr_subtype = (toofar | |
17535 | ? RELAX_MICROMIPS_MARK_TOOFAR32 (fragp->fr_subtype) | |
17536 | : RELAX_MICROMIPS_CLEAR_TOOFAR32 (fragp->fr_subtype)); | |
17537 | ||
17538 | length = 4; | |
17539 | if (toofar) | |
17540 | { | |
17541 | bfd_boolean compact_known = fragp != NULL; | |
17542 | bfd_boolean compact = FALSE; | |
17543 | bfd_boolean uncond; | |
17544 | ||
df58fc94 | 17545 | if (fragp) |
8484fb75 MR |
17546 | { |
17547 | compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype); | |
17548 | uncond = RELAX_MICROMIPS_UNCOND (fragp->fr_subtype); | |
8484fb75 | 17549 | } |
df58fc94 RS |
17550 | else |
17551 | uncond = update < 0; | |
17552 | ||
17553 | /* If label is out of range, we turn branch <br>: | |
17554 | ||
17555 | <br> label # 4 bytes | |
17556 | 0: | |
17557 | ||
17558 | into: | |
17559 | ||
17560 | j label # 4 bytes | |
8484fb75 MR |
17561 | nop # 2/4 bytes if |
17562 | # compact && (!PIC || insn32) | |
df58fc94 RS |
17563 | 0: |
17564 | */ | |
ce8ad872 | 17565 | if ((!pic || insn32) && (!compact_known || compact)) |
8484fb75 | 17566 | length += short_insn_size; |
df58fc94 RS |
17567 | |
17568 | /* If assembling PIC code, we further turn: | |
17569 | ||
17570 | j label # 4 bytes | |
17571 | ||
17572 | into: | |
17573 | ||
17574 | lw/ld at, %got(label)(gp) # 4 bytes | |
17575 | d/addiu at, %lo(label) # 4 bytes | |
8484fb75 | 17576 | jr/c at # 2/4 bytes |
df58fc94 | 17577 | */ |
ce8ad872 | 17578 | if (pic) |
8484fb75 | 17579 | length += 4 + short_insn_size; |
df58fc94 | 17580 | |
7bd374a4 MR |
17581 | /* Add an extra nop if the jump has no compact form and we need |
17582 | to fill the delay slot. */ | |
ce8ad872 | 17583 | if ((!pic || al) && nods) |
7bd374a4 MR |
17584 | length += (fragp |
17585 | ? frag_branch_delay_slot_size (fragp, al, short_insn_size) | |
17586 | : short_insn_size); | |
17587 | ||
df58fc94 RS |
17588 | /* If branch <br> is conditional, we prepend negated branch <brneg>: |
17589 | ||
17590 | <brneg> 0f # 4 bytes | |
8484fb75 | 17591 | nop # 2/4 bytes if !compact |
df58fc94 RS |
17592 | */ |
17593 | if (!uncond) | |
8484fb75 | 17594 | length += (compact_known && compact) ? 4 : 4 + short_insn_size; |
df58fc94 | 17595 | } |
7bd374a4 MR |
17596 | else if (nods) |
17597 | { | |
17598 | /* Add an extra nop to fill the delay slot. */ | |
17599 | gas_assert (fragp); | |
17600 | length += frag_branch_delay_slot_size (fragp, al, short_insn_size); | |
17601 | } | |
df58fc94 RS |
17602 | |
17603 | return length; | |
17604 | } | |
17605 | ||
17606 | /* Compute the length of a branch, and adjust the RELAX_MICROMIPS_TOOFAR16 | |
17607 | bit accordingly. */ | |
17608 | ||
17609 | static int | |
17610 | relaxed_micromips_16bit_branch_length (fragS *fragp, asection *sec, int update) | |
17611 | { | |
17612 | bfd_boolean toofar; | |
17613 | ||
df58fc94 RS |
17614 | if (fragp |
17615 | && S_IS_DEFINED (fragp->fr_symbol) | |
991f40a9 | 17616 | && !S_IS_WEAK (fragp->fr_symbol) |
df58fc94 RS |
17617 | && sec == S_GET_SEGMENT (fragp->fr_symbol)) |
17618 | { | |
17619 | addressT addr; | |
17620 | offsetT val; | |
17621 | int type; | |
17622 | ||
17623 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; | |
17624 | /* Ignore the low bit in the target, since it will be set | |
17625 | for a text label. */ | |
17626 | if ((val & 1) != 0) | |
17627 | --val; | |
17628 | ||
17629 | /* Assume this is a 2-byte branch. */ | |
17630 | addr = fragp->fr_address + fragp->fr_fix + 2; | |
17631 | ||
17632 | /* We try to avoid the infinite loop by not adding 2 more bytes for | |
17633 | long branches. */ | |
17634 | ||
17635 | val -= addr; | |
17636 | ||
17637 | type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype); | |
17638 | if (type == 'D') | |
17639 | toofar = val < - (0x200 << 1) || val >= (0x200 << 1); | |
17640 | else if (type == 'E') | |
17641 | toofar = val < - (0x40 << 1) || val >= (0x40 << 1); | |
17642 | else | |
17643 | abort (); | |
17644 | } | |
17645 | else | |
17646 | /* If the symbol is not defined or it's in a different segment, | |
17647 | we emit a normal 32-bit branch. */ | |
17648 | toofar = TRUE; | |
17649 | ||
17650 | if (fragp && update | |
17651 | && toofar != RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype)) | |
17652 | fragp->fr_subtype | |
17653 | = toofar ? RELAX_MICROMIPS_MARK_TOOFAR16 (fragp->fr_subtype) | |
17654 | : RELAX_MICROMIPS_CLEAR_TOOFAR16 (fragp->fr_subtype); | |
17655 | ||
17656 | if (toofar) | |
17657 | return 4; | |
17658 | ||
17659 | return 2; | |
17660 | } | |
17661 | ||
252b5132 RH |
17662 | /* Estimate the size of a frag before relaxing. Unless this is the |
17663 | mips16, we are not really relaxing here, and the final size is | |
17664 | encoded in the subtype information. For the mips16, we have to | |
17665 | decide whether we are using an extended opcode or not. */ | |
17666 | ||
252b5132 | 17667 | int |
17a2f251 | 17668 | md_estimate_size_before_relax (fragS *fragp, asection *segtype) |
252b5132 | 17669 | { |
5919d012 | 17670 | int change; |
252b5132 | 17671 | |
4a6a3df4 AO |
17672 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
17673 | { | |
17674 | ||
b34976b6 AM |
17675 | fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE); |
17676 | ||
4a6a3df4 AO |
17677 | return fragp->fr_var; |
17678 | } | |
17679 | ||
252b5132 | 17680 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
8507b6e7 MR |
17681 | { |
17682 | /* We don't want to modify the EXTENDED bit here; it might get us | |
17683 | into infinite loops. We change it only in mips_relax_frag(). */ | |
17684 | if (RELAX_MIPS16_MACRO (fragp->fr_subtype)) | |
17685 | return 12; | |
17686 | else | |
17687 | return RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2; | |
17688 | } | |
252b5132 | 17689 | |
df58fc94 RS |
17690 | if (RELAX_MICROMIPS_P (fragp->fr_subtype)) |
17691 | { | |
17692 | int length = 4; | |
17693 | ||
17694 | if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0) | |
17695 | length = relaxed_micromips_16bit_branch_length (fragp, segtype, FALSE); | |
17696 | if (length == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)) | |
17697 | length = relaxed_micromips_32bit_branch_length (fragp, segtype, FALSE); | |
17698 | fragp->fr_var = length; | |
17699 | ||
17700 | return length; | |
17701 | } | |
17702 | ||
ce8ad872 | 17703 | if (mips_pic == VXWORKS_PIC) |
0a44bf69 RS |
17704 | /* For vxworks, GOT16 relocations never have a corresponding LO16. */ |
17705 | change = 0; | |
ce8ad872 MR |
17706 | else if (RELAX_PIC (fragp->fr_subtype)) |
17707 | change = pic_need_relax (fragp->fr_symbol); | |
252b5132 | 17708 | else |
ce8ad872 | 17709 | change = nopic_need_relax (fragp->fr_symbol, 0); |
252b5132 RH |
17710 | |
17711 | if (change) | |
17712 | { | |
4d7206a2 | 17713 | fragp->fr_subtype |= RELAX_USE_SECOND; |
4d7206a2 | 17714 | return -RELAX_FIRST (fragp->fr_subtype); |
252b5132 | 17715 | } |
4d7206a2 RS |
17716 | else |
17717 | return -RELAX_SECOND (fragp->fr_subtype); | |
252b5132 RH |
17718 | } |
17719 | ||
17720 | /* This is called to see whether a reloc against a defined symbol | |
de7e6852 | 17721 | should be converted into a reloc against a section. */ |
252b5132 RH |
17722 | |
17723 | int | |
17a2f251 | 17724 | mips_fix_adjustable (fixS *fixp) |
252b5132 | 17725 | { |
252b5132 RH |
17726 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
17727 | || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
17728 | return 0; | |
a161fe53 | 17729 | |
252b5132 RH |
17730 | if (fixp->fx_addsy == NULL) |
17731 | return 1; | |
a161fe53 | 17732 | |
2f0c68f2 CM |
17733 | /* Allow relocs used for EH tables. */ |
17734 | if (fixp->fx_r_type == BFD_RELOC_32_PCREL) | |
17735 | return 1; | |
17736 | ||
de7e6852 RS |
17737 | /* If symbol SYM is in a mergeable section, relocations of the form |
17738 | SYM + 0 can usually be made section-relative. The mergeable data | |
17739 | is then identified by the section offset rather than by the symbol. | |
17740 | ||
17741 | However, if we're generating REL LO16 relocations, the offset is split | |
33eaf5de | 17742 | between the LO16 and partnering high part relocation. The linker will |
de7e6852 RS |
17743 | need to recalculate the complete offset in order to correctly identify |
17744 | the merge data. | |
17745 | ||
33eaf5de | 17746 | The linker has traditionally not looked for the partnering high part |
de7e6852 RS |
17747 | relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be |
17748 | placed anywhere. Rather than break backwards compatibility by changing | |
17749 | this, it seems better not to force the issue, and instead keep the | |
17750 | original symbol. This will work with either linker behavior. */ | |
738e5348 | 17751 | if ((lo16_reloc_p (fixp->fx_r_type) |
704803a9 | 17752 | || reloc_needs_lo_p (fixp->fx_r_type)) |
de7e6852 RS |
17753 | && HAVE_IN_PLACE_ADDENDS |
17754 | && (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_MERGE) != 0) | |
17755 | return 0; | |
17756 | ||
97f50151 MR |
17757 | /* There is no place to store an in-place offset for JALR relocations. */ |
17758 | if (jalr_reloc_p (fixp->fx_r_type) && HAVE_IN_PLACE_ADDENDS) | |
17759 | return 0; | |
17760 | ||
17761 | /* Likewise an in-range offset of limited PC-relative relocations may | |
2de39019 | 17762 | overflow the in-place relocatable field if recalculated against the |
7361da2c AB |
17763 | start address of the symbol's containing section. |
17764 | ||
17765 | Also, PC relative relocations for MIPS R6 need to be symbol rather than | |
17766 | section relative to allow linker relaxations to be performed later on. */ | |
97f50151 | 17767 | if (limited_pcrel_reloc_p (fixp->fx_r_type) |
912815f0 | 17768 | && (HAVE_IN_PLACE_ADDENDS || ISA_IS_R6 (file_mips_opts.isa))) |
1180b5a4 RS |
17769 | return 0; |
17770 | ||
b314ec0e RS |
17771 | /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve |
17772 | to a floating-point stub. The same is true for non-R_MIPS16_26 | |
17773 | relocations against MIPS16 functions; in this case, the stub becomes | |
17774 | the function's canonical address. | |
17775 | ||
17776 | Floating-point stubs are stored in unique .mips16.call.* or | |
17777 | .mips16.fn.* sections. If a stub T for function F is in section S, | |
17778 | the first relocation in section S must be against F; this is how the | |
17779 | linker determines the target function. All relocations that might | |
17780 | resolve to T must also be against F. We therefore have the following | |
17781 | restrictions, which are given in an intentionally-redundant way: | |
17782 | ||
17783 | 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16 | |
17784 | symbols. | |
17785 | ||
17786 | 2. We cannot reduce a stub's relocations against non-MIPS16 symbols | |
17787 | if that stub might be used. | |
17788 | ||
17789 | 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16 | |
17790 | symbols. | |
17791 | ||
17792 | 4. We cannot reduce a stub's relocations against MIPS16 symbols if | |
17793 | that stub might be used. | |
17794 | ||
17795 | There is a further restriction: | |
17796 | ||
df58fc94 | 17797 | 5. We cannot reduce jump relocations (R_MIPS_26, R_MIPS16_26 or |
0e9c5a5c | 17798 | R_MICROMIPS_26_S1) or branch relocations (R_MIPS_PC26_S2, |
c9775dde MR |
17799 | R_MIPS_PC21_S2, R_MIPS_PC16, R_MIPS16_PC16_S1, |
17800 | R_MICROMIPS_PC16_S1, R_MICROMIPS_PC10_S1 or R_MICROMIPS_PC7_S1) | |
17801 | against MIPS16 or microMIPS symbols because we need to keep the | |
17802 | MIPS16 or microMIPS symbol for the purpose of mode mismatch | |
a6ebf616 MR |
17803 | detection and JAL or BAL to JALX instruction conversion in the |
17804 | linker. | |
b314ec0e | 17805 | |
df58fc94 | 17806 | For simplicity, we deal with (3)-(4) by not reducing _any_ relocation |
507dcb32 | 17807 | against a MIPS16 symbol. We deal with (5) by additionally leaving |
0e9c5a5c | 17808 | alone any jump and branch relocations against a microMIPS symbol. |
b314ec0e RS |
17809 | |
17810 | We deal with (1)-(2) by saying that, if there's a R_MIPS16_26 | |
17811 | relocation against some symbol R, no relocation against R may be | |
17812 | reduced. (Note that this deals with (2) as well as (1) because | |
17813 | relocations against global symbols will never be reduced on ELF | |
17814 | targets.) This approach is a little simpler than trying to detect | |
17815 | stub sections, and gives the "all or nothing" per-symbol consistency | |
17816 | that we have for MIPS16 symbols. */ | |
f3ded42a | 17817 | if (fixp->fx_subsy == NULL |
30c09090 | 17818 | && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp->fx_addsy)) |
44d3da23 | 17819 | || (ELF_ST_IS_MICROMIPS (S_GET_OTHER (fixp->fx_addsy)) |
0e9c5a5c MR |
17820 | && (jmp_reloc_p (fixp->fx_r_type) |
17821 | || b_reloc_p (fixp->fx_r_type))) | |
44d3da23 | 17822 | || *symbol_get_tc (fixp->fx_addsy))) |
252b5132 | 17823 | return 0; |
a161fe53 | 17824 | |
252b5132 RH |
17825 | return 1; |
17826 | } | |
17827 | ||
17828 | /* Translate internal representation of relocation info to BFD target | |
17829 | format. */ | |
17830 | ||
17831 | arelent ** | |
17a2f251 | 17832 | tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) |
252b5132 RH |
17833 | { |
17834 | static arelent *retval[4]; | |
17835 | arelent *reloc; | |
17836 | bfd_reloc_code_real_type code; | |
17837 | ||
4b0cff4e | 17838 | memset (retval, 0, sizeof(retval)); |
325801bd TS |
17839 | reloc = retval[0] = XCNEW (arelent); |
17840 | reloc->sym_ptr_ptr = XNEW (asymbol *); | |
49309057 | 17841 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); |
252b5132 RH |
17842 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; |
17843 | ||
bad36eac DJ |
17844 | if (fixp->fx_pcrel) |
17845 | { | |
df58fc94 | 17846 | gas_assert (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2 |
c9775dde | 17847 | || fixp->fx_r_type == BFD_RELOC_MIPS16_16_PCREL_S1 |
df58fc94 RS |
17848 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1 |
17849 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1 | |
b47468a6 | 17850 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1 |
7361da2c AB |
17851 | || fixp->fx_r_type == BFD_RELOC_32_PCREL |
17852 | || fixp->fx_r_type == BFD_RELOC_MIPS_21_PCREL_S2 | |
17853 | || fixp->fx_r_type == BFD_RELOC_MIPS_26_PCREL_S2 | |
17854 | || fixp->fx_r_type == BFD_RELOC_MIPS_18_PCREL_S3 | |
17855 | || fixp->fx_r_type == BFD_RELOC_MIPS_19_PCREL_S2 | |
17856 | || fixp->fx_r_type == BFD_RELOC_HI16_S_PCREL | |
17857 | || fixp->fx_r_type == BFD_RELOC_LO16_PCREL); | |
bad36eac DJ |
17858 | |
17859 | /* At this point, fx_addnumber is "symbol offset - pcrel address". | |
17860 | Relocations want only the symbol offset. */ | |
51f6035b MR |
17861 | switch (fixp->fx_r_type) |
17862 | { | |
17863 | case BFD_RELOC_MIPS_18_PCREL_S3: | |
17864 | reloc->addend = fixp->fx_addnumber + (reloc->address & ~7); | |
17865 | break; | |
17866 | default: | |
17867 | reloc->addend = fixp->fx_addnumber + reloc->address; | |
17868 | break; | |
17869 | } | |
bad36eac | 17870 | } |
17c6c9d9 MR |
17871 | else if (HAVE_IN_PLACE_ADDENDS |
17872 | && fixp->fx_r_type == BFD_RELOC_MICROMIPS_JMP | |
17873 | && (read_compressed_insn (fixp->fx_frag->fr_literal | |
17874 | + fixp->fx_where, 4) >> 26) == 0x3c) | |
17875 | { | |
17876 | /* Shift is 2, unusually, for microMIPS JALX. Adjust the in-place | |
17877 | addend accordingly. */ | |
17878 | reloc->addend = fixp->fx_addnumber >> 1; | |
17879 | } | |
bad36eac DJ |
17880 | else |
17881 | reloc->addend = fixp->fx_addnumber; | |
252b5132 | 17882 | |
438c16b8 TS |
17883 | /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable |
17884 | entry to be used in the relocation's section offset. */ | |
17885 | if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
252b5132 RH |
17886 | { |
17887 | reloc->address = reloc->addend; | |
17888 | reloc->addend = 0; | |
17889 | } | |
17890 | ||
252b5132 | 17891 | code = fixp->fx_r_type; |
252b5132 | 17892 | |
bad36eac | 17893 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); |
252b5132 RH |
17894 | if (reloc->howto == NULL) |
17895 | { | |
17896 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
1661c76c RS |
17897 | _("cannot represent %s relocation in this object file" |
17898 | " format"), | |
252b5132 RH |
17899 | bfd_get_reloc_code_name (code)); |
17900 | retval[0] = NULL; | |
17901 | } | |
17902 | ||
17903 | return retval; | |
17904 | } | |
17905 | ||
17906 | /* Relax a machine dependent frag. This returns the amount by which | |
17907 | the current size of the frag should change. */ | |
17908 | ||
17909 | int | |
17a2f251 | 17910 | mips_relax_frag (asection *sec, fragS *fragp, long stretch) |
252b5132 | 17911 | { |
4a6a3df4 AO |
17912 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
17913 | { | |
17914 | offsetT old_var = fragp->fr_var; | |
b34976b6 AM |
17915 | |
17916 | fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE); | |
4a6a3df4 AO |
17917 | |
17918 | return fragp->fr_var - old_var; | |
17919 | } | |
17920 | ||
df58fc94 RS |
17921 | if (RELAX_MICROMIPS_P (fragp->fr_subtype)) |
17922 | { | |
17923 | offsetT old_var = fragp->fr_var; | |
17924 | offsetT new_var = 4; | |
17925 | ||
17926 | if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0) | |
17927 | new_var = relaxed_micromips_16bit_branch_length (fragp, sec, TRUE); | |
17928 | if (new_var == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)) | |
17929 | new_var = relaxed_micromips_32bit_branch_length (fragp, sec, TRUE); | |
17930 | fragp->fr_var = new_var; | |
17931 | ||
17932 | return new_var - old_var; | |
17933 | } | |
17934 | ||
252b5132 RH |
17935 | if (! RELAX_MIPS16_P (fragp->fr_subtype)) |
17936 | return 0; | |
17937 | ||
8507b6e7 | 17938 | if (!mips16_extended_frag (fragp, sec, stretch)) |
252b5132 | 17939 | { |
8507b6e7 MR |
17940 | if (RELAX_MIPS16_MACRO (fragp->fr_subtype)) |
17941 | { | |
17942 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_MACRO (fragp->fr_subtype); | |
17943 | return -10; | |
17944 | } | |
17945 | else if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
17946 | { | |
17947 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype); | |
17948 | return -2; | |
17949 | } | |
17950 | else | |
17951 | return 0; | |
17952 | } | |
17953 | else if (!mips16_macro_frag (fragp, sec, stretch)) | |
17954 | { | |
17955 | if (RELAX_MIPS16_MACRO (fragp->fr_subtype)) | |
17956 | { | |
17957 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_MACRO (fragp->fr_subtype); | |
17958 | fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype); | |
17959 | return -8; | |
17960 | } | |
17961 | else if (!RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
17962 | { | |
17963 | fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype); | |
17964 | return 2; | |
17965 | } | |
17966 | else | |
252b5132 | 17967 | return 0; |
252b5132 RH |
17968 | } |
17969 | else | |
17970 | { | |
8507b6e7 | 17971 | if (RELAX_MIPS16_MACRO (fragp->fr_subtype)) |
252b5132 | 17972 | return 0; |
8507b6e7 MR |
17973 | else if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) |
17974 | { | |
17975 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype); | |
17976 | fragp->fr_subtype = RELAX_MIPS16_MARK_MACRO (fragp->fr_subtype); | |
17977 | return 8; | |
17978 | } | |
17979 | else | |
17980 | { | |
17981 | fragp->fr_subtype = RELAX_MIPS16_MARK_MACRO (fragp->fr_subtype); | |
17982 | return 10; | |
17983 | } | |
252b5132 RH |
17984 | } |
17985 | ||
17986 | return 0; | |
17987 | } | |
17988 | ||
17989 | /* Convert a machine dependent frag. */ | |
17990 | ||
17991 | void | |
17a2f251 | 17992 | md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp) |
252b5132 | 17993 | { |
4a6a3df4 AO |
17994 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
17995 | { | |
4d68580a | 17996 | char *buf; |
4a6a3df4 AO |
17997 | unsigned long insn; |
17998 | expressionS exp; | |
17999 | fixS *fixp; | |
b34976b6 | 18000 | |
4d68580a RS |
18001 | buf = fragp->fr_literal + fragp->fr_fix; |
18002 | insn = read_insn (buf); | |
b34976b6 | 18003 | |
4a6a3df4 AO |
18004 | if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) |
18005 | { | |
18006 | /* We generate a fixup instead of applying it right now | |
18007 | because, if there are linker relaxations, we're going to | |
18008 | need the relocations. */ | |
18009 | exp.X_op = O_symbol; | |
18010 | exp.X_add_symbol = fragp->fr_symbol; | |
18011 | exp.X_add_number = fragp->fr_offset; | |
18012 | ||
4d68580a RS |
18013 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, TRUE, |
18014 | BFD_RELOC_16_PCREL_S2); | |
4a6a3df4 AO |
18015 | fixp->fx_file = fragp->fr_file; |
18016 | fixp->fx_line = fragp->fr_line; | |
b34976b6 | 18017 | |
4d68580a | 18018 | buf = write_insn (buf, insn); |
4a6a3df4 AO |
18019 | } |
18020 | else | |
18021 | { | |
18022 | int i; | |
18023 | ||
18024 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
1661c76c | 18025 | _("relaxed out-of-range branch into a jump")); |
4a6a3df4 AO |
18026 | |
18027 | if (RELAX_BRANCH_UNCOND (fragp->fr_subtype)) | |
18028 | goto uncond; | |
18029 | ||
18030 | if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
18031 | { | |
18032 | /* Reverse the branch. */ | |
18033 | switch ((insn >> 28) & 0xf) | |
18034 | { | |
18035 | case 4: | |
56d438b1 CF |
18036 | if ((insn & 0xff000000) == 0x47000000 |
18037 | || (insn & 0xff600000) == 0x45600000) | |
18038 | { | |
18039 | /* BZ.df/BNZ.df, BZ.V/BNZ.V can have the condition | |
18040 | reversed by tweaking bit 23. */ | |
18041 | insn ^= 0x00800000; | |
18042 | } | |
18043 | else | |
18044 | { | |
18045 | /* bc[0-3][tf]l? instructions can have the condition | |
18046 | reversed by tweaking a single TF bit, and their | |
18047 | opcodes all have 0x4???????. */ | |
18048 | gas_assert ((insn & 0xf3e00000) == 0x41000000); | |
18049 | insn ^= 0x00010000; | |
18050 | } | |
4a6a3df4 AO |
18051 | break; |
18052 | ||
18053 | case 0: | |
18054 | /* bltz 0x04000000 bgez 0x04010000 | |
54f4ddb3 | 18055 | bltzal 0x04100000 bgezal 0x04110000 */ |
9c2799c2 | 18056 | gas_assert ((insn & 0xfc0e0000) == 0x04000000); |
4a6a3df4 AO |
18057 | insn ^= 0x00010000; |
18058 | break; | |
b34976b6 | 18059 | |
4a6a3df4 AO |
18060 | case 1: |
18061 | /* beq 0x10000000 bne 0x14000000 | |
54f4ddb3 | 18062 | blez 0x18000000 bgtz 0x1c000000 */ |
4a6a3df4 AO |
18063 | insn ^= 0x04000000; |
18064 | break; | |
18065 | ||
18066 | default: | |
18067 | abort (); | |
18068 | } | |
18069 | } | |
18070 | ||
18071 | if (RELAX_BRANCH_LINK (fragp->fr_subtype)) | |
18072 | { | |
18073 | /* Clear the and-link bit. */ | |
9c2799c2 | 18074 | gas_assert ((insn & 0xfc1c0000) == 0x04100000); |
4a6a3df4 | 18075 | |
54f4ddb3 TS |
18076 | /* bltzal 0x04100000 bgezal 0x04110000 |
18077 | bltzall 0x04120000 bgezall 0x04130000 */ | |
4a6a3df4 AO |
18078 | insn &= ~0x00100000; |
18079 | } | |
18080 | ||
18081 | /* Branch over the branch (if the branch was likely) or the | |
18082 | full jump (not likely case). Compute the offset from the | |
18083 | current instruction to branch to. */ | |
18084 | if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
18085 | i = 16; | |
18086 | else | |
18087 | { | |
18088 | /* How many bytes in instructions we've already emitted? */ | |
4d68580a | 18089 | i = buf - fragp->fr_literal - fragp->fr_fix; |
4a6a3df4 AO |
18090 | /* How many bytes in instructions from here to the end? */ |
18091 | i = fragp->fr_var - i; | |
18092 | } | |
18093 | /* Convert to instruction count. */ | |
18094 | i >>= 2; | |
18095 | /* Branch counts from the next instruction. */ | |
b34976b6 | 18096 | i--; |
4a6a3df4 AO |
18097 | insn |= i; |
18098 | /* Branch over the jump. */ | |
4d68580a | 18099 | buf = write_insn (buf, insn); |
4a6a3df4 | 18100 | |
54f4ddb3 | 18101 | /* nop */ |
4d68580a | 18102 | buf = write_insn (buf, 0); |
4a6a3df4 AO |
18103 | |
18104 | if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
18105 | { | |
18106 | /* beql $0, $0, 2f */ | |
18107 | insn = 0x50000000; | |
18108 | /* Compute the PC offset from the current instruction to | |
18109 | the end of the variable frag. */ | |
18110 | /* How many bytes in instructions we've already emitted? */ | |
4d68580a | 18111 | i = buf - fragp->fr_literal - fragp->fr_fix; |
4a6a3df4 AO |
18112 | /* How many bytes in instructions from here to the end? */ |
18113 | i = fragp->fr_var - i; | |
18114 | /* Convert to instruction count. */ | |
18115 | i >>= 2; | |
18116 | /* Don't decrement i, because we want to branch over the | |
18117 | delay slot. */ | |
4a6a3df4 | 18118 | insn |= i; |
4a6a3df4 | 18119 | |
4d68580a RS |
18120 | buf = write_insn (buf, insn); |
18121 | buf = write_insn (buf, 0); | |
4a6a3df4 AO |
18122 | } |
18123 | ||
18124 | uncond: | |
ce8ad872 | 18125 | if (!RELAX_BRANCH_PIC (fragp->fr_subtype)) |
4a6a3df4 AO |
18126 | { |
18127 | /* j or jal. */ | |
18128 | insn = (RELAX_BRANCH_LINK (fragp->fr_subtype) | |
18129 | ? 0x0c000000 : 0x08000000); | |
18130 | exp.X_op = O_symbol; | |
18131 | exp.X_add_symbol = fragp->fr_symbol; | |
18132 | exp.X_add_number = fragp->fr_offset; | |
18133 | ||
4d68580a RS |
18134 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, |
18135 | FALSE, BFD_RELOC_MIPS_JMP); | |
4a6a3df4 AO |
18136 | fixp->fx_file = fragp->fr_file; |
18137 | fixp->fx_line = fragp->fr_line; | |
18138 | ||
4d68580a | 18139 | buf = write_insn (buf, insn); |
4a6a3df4 AO |
18140 | } |
18141 | else | |
18142 | { | |
66b3e8da MR |
18143 | unsigned long at = RELAX_BRANCH_AT (fragp->fr_subtype); |
18144 | ||
4a6a3df4 | 18145 | /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */ |
66b3e8da MR |
18146 | insn = HAVE_64BIT_ADDRESSES ? 0xdf800000 : 0x8f800000; |
18147 | insn |= at << OP_SH_RT; | |
4a6a3df4 AO |
18148 | exp.X_op = O_symbol; |
18149 | exp.X_add_symbol = fragp->fr_symbol; | |
18150 | exp.X_add_number = fragp->fr_offset; | |
18151 | ||
18152 | if (fragp->fr_offset) | |
18153 | { | |
18154 | exp.X_add_symbol = make_expr_symbol (&exp); | |
18155 | exp.X_add_number = 0; | |
18156 | } | |
18157 | ||
4d68580a RS |
18158 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, |
18159 | FALSE, BFD_RELOC_MIPS_GOT16); | |
4a6a3df4 AO |
18160 | fixp->fx_file = fragp->fr_file; |
18161 | fixp->fx_line = fragp->fr_line; | |
18162 | ||
4d68580a | 18163 | buf = write_insn (buf, insn); |
b34976b6 | 18164 | |
4a6a3df4 | 18165 | if (mips_opts.isa == ISA_MIPS1) |
4d68580a RS |
18166 | /* nop */ |
18167 | buf = write_insn (buf, 0); | |
4a6a3df4 AO |
18168 | |
18169 | /* d/addiu $at, $at, <sym> R_MIPS_LO16 */ | |
66b3e8da MR |
18170 | insn = HAVE_64BIT_ADDRESSES ? 0x64000000 : 0x24000000; |
18171 | insn |= at << OP_SH_RS | at << OP_SH_RT; | |
4a6a3df4 | 18172 | |
4d68580a RS |
18173 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, |
18174 | FALSE, BFD_RELOC_LO16); | |
4a6a3df4 AO |
18175 | fixp->fx_file = fragp->fr_file; |
18176 | fixp->fx_line = fragp->fr_line; | |
b34976b6 | 18177 | |
4d68580a | 18178 | buf = write_insn (buf, insn); |
4a6a3df4 AO |
18179 | |
18180 | /* j(al)r $at. */ | |
18181 | if (RELAX_BRANCH_LINK (fragp->fr_subtype)) | |
66b3e8da | 18182 | insn = 0x0000f809; |
4a6a3df4 | 18183 | else |
66b3e8da MR |
18184 | insn = 0x00000008; |
18185 | insn |= at << OP_SH_RS; | |
4a6a3df4 | 18186 | |
4d68580a | 18187 | buf = write_insn (buf, insn); |
4a6a3df4 AO |
18188 | } |
18189 | } | |
18190 | ||
4a6a3df4 | 18191 | fragp->fr_fix += fragp->fr_var; |
4d68580a | 18192 | gas_assert (buf == fragp->fr_literal + fragp->fr_fix); |
4a6a3df4 AO |
18193 | return; |
18194 | } | |
18195 | ||
df58fc94 RS |
18196 | /* Relax microMIPS branches. */ |
18197 | if (RELAX_MICROMIPS_P (fragp->fr_subtype)) | |
18198 | { | |
4d68580a | 18199 | char *buf = fragp->fr_literal + fragp->fr_fix; |
df58fc94 | 18200 | bfd_boolean compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype); |
8484fb75 | 18201 | bfd_boolean insn32 = RELAX_MICROMIPS_INSN32 (fragp->fr_subtype); |
7bd374a4 | 18202 | bfd_boolean nods = RELAX_MICROMIPS_NODS (fragp->fr_subtype); |
ce8ad872 | 18203 | bfd_boolean pic = RELAX_MICROMIPS_PIC (fragp->fr_subtype); |
df58fc94 RS |
18204 | bfd_boolean al = RELAX_MICROMIPS_LINK (fragp->fr_subtype); |
18205 | int type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype); | |
2309ddf2 | 18206 | bfd_boolean short_ds; |
df58fc94 RS |
18207 | unsigned long insn; |
18208 | expressionS exp; | |
18209 | fixS *fixp; | |
18210 | ||
18211 | exp.X_op = O_symbol; | |
18212 | exp.X_add_symbol = fragp->fr_symbol; | |
18213 | exp.X_add_number = fragp->fr_offset; | |
18214 | ||
18215 | fragp->fr_fix += fragp->fr_var; | |
18216 | ||
18217 | /* Handle 16-bit branches that fit or are forced to fit. */ | |
18218 | if (type != 0 && !RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype)) | |
18219 | { | |
18220 | /* We generate a fixup instead of applying it right now, | |
18221 | because if there is linker relaxation, we're going to | |
18222 | need the relocations. */ | |
18223 | if (type == 'D') | |
4d68580a | 18224 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 2, &exp, TRUE, |
df58fc94 RS |
18225 | BFD_RELOC_MICROMIPS_10_PCREL_S1); |
18226 | else if (type == 'E') | |
4d68580a | 18227 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 2, &exp, TRUE, |
df58fc94 RS |
18228 | BFD_RELOC_MICROMIPS_7_PCREL_S1); |
18229 | else | |
18230 | abort (); | |
18231 | ||
18232 | fixp->fx_file = fragp->fr_file; | |
18233 | fixp->fx_line = fragp->fr_line; | |
18234 | ||
18235 | /* These relocations can have an addend that won't fit in | |
18236 | 2 octets. */ | |
18237 | fixp->fx_no_overflow = 1; | |
18238 | ||
18239 | return; | |
18240 | } | |
18241 | ||
2309ddf2 | 18242 | /* Handle 32-bit branches that fit or are forced to fit. */ |
df58fc94 RS |
18243 | if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype) |
18244 | || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype)) | |
18245 | { | |
18246 | /* We generate a fixup instead of applying it right now, | |
18247 | because if there is linker relaxation, we're going to | |
18248 | need the relocations. */ | |
4d68580a RS |
18249 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, TRUE, |
18250 | BFD_RELOC_MICROMIPS_16_PCREL_S1); | |
df58fc94 RS |
18251 | fixp->fx_file = fragp->fr_file; |
18252 | fixp->fx_line = fragp->fr_line; | |
18253 | ||
18254 | if (type == 0) | |
7bd374a4 MR |
18255 | { |
18256 | insn = read_compressed_insn (buf, 4); | |
18257 | buf += 4; | |
18258 | ||
18259 | if (nods) | |
18260 | { | |
18261 | /* Check the short-delay-slot bit. */ | |
18262 | if (!al || (insn & 0x02000000) != 0) | |
18263 | buf = write_compressed_insn (buf, 0x0c00, 2); | |
18264 | else | |
18265 | buf = write_compressed_insn (buf, 0x00000000, 4); | |
18266 | } | |
18267 | ||
18268 | gas_assert (buf == fragp->fr_literal + fragp->fr_fix); | |
18269 | return; | |
18270 | } | |
df58fc94 RS |
18271 | } |
18272 | ||
18273 | /* Relax 16-bit branches to 32-bit branches. */ | |
18274 | if (type != 0) | |
18275 | { | |
4d68580a | 18276 | insn = read_compressed_insn (buf, 2); |
df58fc94 RS |
18277 | |
18278 | if ((insn & 0xfc00) == 0xcc00) /* b16 */ | |
18279 | insn = 0x94000000; /* beq */ | |
18280 | else if ((insn & 0xdc00) == 0x8c00) /* beqz16/bnez16 */ | |
18281 | { | |
18282 | unsigned long regno; | |
18283 | ||
18284 | regno = (insn >> MICROMIPSOP_SH_MD) & MICROMIPSOP_MASK_MD; | |
18285 | regno = micromips_to_32_reg_d_map [regno]; | |
18286 | insn = ((insn & 0x2000) << 16) | 0x94000000; /* beq/bne */ | |
18287 | insn |= regno << MICROMIPSOP_SH_RS; | |
18288 | } | |
18289 | else | |
18290 | abort (); | |
18291 | ||
18292 | /* Nothing else to do, just write it out. */ | |
18293 | if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype) | |
18294 | || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype)) | |
18295 | { | |
4d68580a | 18296 | buf = write_compressed_insn (buf, insn, 4); |
7bd374a4 MR |
18297 | if (nods) |
18298 | buf = write_compressed_insn (buf, 0x0c00, 2); | |
4d68580a | 18299 | gas_assert (buf == fragp->fr_literal + fragp->fr_fix); |
df58fc94 RS |
18300 | return; |
18301 | } | |
18302 | } | |
18303 | else | |
4d68580a | 18304 | insn = read_compressed_insn (buf, 4); |
df58fc94 RS |
18305 | |
18306 | /* Relax 32-bit branches to a sequence of instructions. */ | |
18307 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
1661c76c | 18308 | _("relaxed out-of-range branch into a jump")); |
df58fc94 | 18309 | |
2309ddf2 | 18310 | /* Set the short-delay-slot bit. */ |
7bd374a4 | 18311 | short_ds = !al || (insn & 0x02000000) != 0; |
df58fc94 RS |
18312 | |
18313 | if (!RELAX_MICROMIPS_UNCOND (fragp->fr_subtype)) | |
18314 | { | |
18315 | symbolS *l; | |
18316 | ||
18317 | /* Reverse the branch. */ | |
18318 | if ((insn & 0xfc000000) == 0x94000000 /* beq */ | |
18319 | || (insn & 0xfc000000) == 0xb4000000) /* bne */ | |
18320 | insn ^= 0x20000000; | |
18321 | else if ((insn & 0xffe00000) == 0x40000000 /* bltz */ | |
18322 | || (insn & 0xffe00000) == 0x40400000 /* bgez */ | |
18323 | || (insn & 0xffe00000) == 0x40800000 /* blez */ | |
18324 | || (insn & 0xffe00000) == 0x40c00000 /* bgtz */ | |
18325 | || (insn & 0xffe00000) == 0x40a00000 /* bnezc */ | |
18326 | || (insn & 0xffe00000) == 0x40e00000 /* beqzc */ | |
18327 | || (insn & 0xffe00000) == 0x40200000 /* bltzal */ | |
18328 | || (insn & 0xffe00000) == 0x40600000 /* bgezal */ | |
18329 | || (insn & 0xffe00000) == 0x42200000 /* bltzals */ | |
18330 | || (insn & 0xffe00000) == 0x42600000) /* bgezals */ | |
18331 | insn ^= 0x00400000; | |
18332 | else if ((insn & 0xffe30000) == 0x43800000 /* bc1f */ | |
18333 | || (insn & 0xffe30000) == 0x43a00000 /* bc1t */ | |
18334 | || (insn & 0xffe30000) == 0x42800000 /* bc2f */ | |
18335 | || (insn & 0xffe30000) == 0x42a00000) /* bc2t */ | |
18336 | insn ^= 0x00200000; | |
56d438b1 CF |
18337 | else if ((insn & 0xff000000) == 0x83000000 /* BZ.df |
18338 | BNZ.df */ | |
18339 | || (insn & 0xff600000) == 0x81600000) /* BZ.V | |
18340 | BNZ.V */ | |
18341 | insn ^= 0x00800000; | |
df58fc94 RS |
18342 | else |
18343 | abort (); | |
18344 | ||
18345 | if (al) | |
18346 | { | |
18347 | /* Clear the and-link and short-delay-slot bits. */ | |
18348 | gas_assert ((insn & 0xfda00000) == 0x40200000); | |
18349 | ||
18350 | /* bltzal 0x40200000 bgezal 0x40600000 */ | |
18351 | /* bltzals 0x42200000 bgezals 0x42600000 */ | |
18352 | insn &= ~0x02200000; | |
18353 | } | |
18354 | ||
18355 | /* Make a label at the end for use with the branch. */ | |
18356 | l = symbol_new (micromips_label_name (), asec, fragp->fr_fix, fragp); | |
18357 | micromips_label_inc (); | |
f3ded42a | 18358 | S_SET_OTHER (l, ELF_ST_SET_MICROMIPS (S_GET_OTHER (l))); |
df58fc94 RS |
18359 | |
18360 | /* Refer to it. */ | |
4d68580a RS |
18361 | fixp = fix_new (fragp, buf - fragp->fr_literal, 4, l, 0, TRUE, |
18362 | BFD_RELOC_MICROMIPS_16_PCREL_S1); | |
df58fc94 RS |
18363 | fixp->fx_file = fragp->fr_file; |
18364 | fixp->fx_line = fragp->fr_line; | |
18365 | ||
18366 | /* Branch over the jump. */ | |
4d68580a | 18367 | buf = write_compressed_insn (buf, insn, 4); |
8484fb75 | 18368 | |
df58fc94 | 18369 | if (!compact) |
8484fb75 MR |
18370 | { |
18371 | /* nop */ | |
18372 | if (insn32) | |
18373 | buf = write_compressed_insn (buf, 0x00000000, 4); | |
18374 | else | |
18375 | buf = write_compressed_insn (buf, 0x0c00, 2); | |
18376 | } | |
df58fc94 RS |
18377 | } |
18378 | ||
ce8ad872 | 18379 | if (!pic) |
df58fc94 | 18380 | { |
7bd374a4 MR |
18381 | unsigned long jal = (short_ds || nods |
18382 | ? 0x74000000 : 0xf4000000); /* jal/s */ | |
2309ddf2 | 18383 | |
df58fc94 RS |
18384 | /* j/jal/jals <sym> R_MICROMIPS_26_S1 */ |
18385 | insn = al ? jal : 0xd4000000; | |
18386 | ||
4d68580a RS |
18387 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE, |
18388 | BFD_RELOC_MICROMIPS_JMP); | |
df58fc94 RS |
18389 | fixp->fx_file = fragp->fr_file; |
18390 | fixp->fx_line = fragp->fr_line; | |
18391 | ||
4d68580a | 18392 | buf = write_compressed_insn (buf, insn, 4); |
8484fb75 | 18393 | |
7bd374a4 | 18394 | if (compact || nods) |
8484fb75 MR |
18395 | { |
18396 | /* nop */ | |
18397 | if (insn32) | |
18398 | buf = write_compressed_insn (buf, 0x00000000, 4); | |
18399 | else | |
18400 | buf = write_compressed_insn (buf, 0x0c00, 2); | |
18401 | } | |
df58fc94 RS |
18402 | } |
18403 | else | |
18404 | { | |
18405 | unsigned long at = RELAX_MICROMIPS_AT (fragp->fr_subtype); | |
18406 | ||
18407 | /* lw/ld $at, <sym>($gp) R_MICROMIPS_GOT16 */ | |
18408 | insn = HAVE_64BIT_ADDRESSES ? 0xdc1c0000 : 0xfc1c0000; | |
18409 | insn |= at << MICROMIPSOP_SH_RT; | |
18410 | ||
18411 | if (exp.X_add_number) | |
18412 | { | |
18413 | exp.X_add_symbol = make_expr_symbol (&exp); | |
18414 | exp.X_add_number = 0; | |
18415 | } | |
18416 | ||
4d68580a RS |
18417 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE, |
18418 | BFD_RELOC_MICROMIPS_GOT16); | |
df58fc94 RS |
18419 | fixp->fx_file = fragp->fr_file; |
18420 | fixp->fx_line = fragp->fr_line; | |
18421 | ||
4d68580a | 18422 | buf = write_compressed_insn (buf, insn, 4); |
df58fc94 RS |
18423 | |
18424 | /* d/addiu $at, $at, <sym> R_MICROMIPS_LO16 */ | |
18425 | insn = HAVE_64BIT_ADDRESSES ? 0x5c000000 : 0x30000000; | |
18426 | insn |= at << MICROMIPSOP_SH_RT | at << MICROMIPSOP_SH_RS; | |
18427 | ||
4d68580a RS |
18428 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE, |
18429 | BFD_RELOC_MICROMIPS_LO16); | |
df58fc94 RS |
18430 | fixp->fx_file = fragp->fr_file; |
18431 | fixp->fx_line = fragp->fr_line; | |
18432 | ||
4d68580a | 18433 | buf = write_compressed_insn (buf, insn, 4); |
df58fc94 | 18434 | |
8484fb75 MR |
18435 | if (insn32) |
18436 | { | |
18437 | /* jr/jalr $at */ | |
18438 | insn = 0x00000f3c | (al ? RA : ZERO) << MICROMIPSOP_SH_RT; | |
18439 | insn |= at << MICROMIPSOP_SH_RS; | |
18440 | ||
18441 | buf = write_compressed_insn (buf, insn, 4); | |
df58fc94 | 18442 | |
7bd374a4 | 18443 | if (compact || nods) |
8484fb75 MR |
18444 | /* nop */ |
18445 | buf = write_compressed_insn (buf, 0x00000000, 4); | |
18446 | } | |
18447 | else | |
18448 | { | |
18449 | /* jr/jrc/jalr/jalrs $at */ | |
18450 | unsigned long jalr = short_ds ? 0x45e0 : 0x45c0; /* jalr/s */ | |
7bd374a4 | 18451 | unsigned long jr = compact || nods ? 0x45a0 : 0x4580; /* jr/c */ |
8484fb75 MR |
18452 | |
18453 | insn = al ? jalr : jr; | |
18454 | insn |= at << MICROMIPSOP_SH_MJ; | |
18455 | ||
18456 | buf = write_compressed_insn (buf, insn, 2); | |
7bd374a4 MR |
18457 | if (al && nods) |
18458 | { | |
18459 | /* nop */ | |
18460 | if (short_ds) | |
18461 | buf = write_compressed_insn (buf, 0x0c00, 2); | |
18462 | else | |
18463 | buf = write_compressed_insn (buf, 0x00000000, 4); | |
18464 | } | |
8484fb75 | 18465 | } |
df58fc94 RS |
18466 | } |
18467 | ||
4d68580a | 18468 | gas_assert (buf == fragp->fr_literal + fragp->fr_fix); |
df58fc94 RS |
18469 | return; |
18470 | } | |
18471 | ||
252b5132 RH |
18472 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
18473 | { | |
18474 | int type; | |
3ccad066 | 18475 | const struct mips_int_operand *operand; |
252b5132 | 18476 | offsetT val; |
5c04167a | 18477 | char *buf; |
8507b6e7 | 18478 | unsigned int user_length; |
9d862524 | 18479 | bfd_boolean need_reloc; |
252b5132 | 18480 | unsigned long insn; |
8507b6e7 | 18481 | bfd_boolean mac; |
5c04167a | 18482 | bfd_boolean ext; |
88a7ef16 | 18483 | segT symsec; |
252b5132 RH |
18484 | |
18485 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
3ccad066 | 18486 | operand = mips16_immed_operand (type, FALSE); |
252b5132 | 18487 | |
8507b6e7 | 18488 | mac = RELAX_MIPS16_MACRO (fragp->fr_subtype); |
5c04167a | 18489 | ext = RELAX_MIPS16_EXTENDED (fragp->fr_subtype); |
88a7ef16 | 18490 | val = resolve_symbol_value (fragp->fr_symbol) + fragp->fr_offset; |
9d862524 MR |
18491 | |
18492 | symsec = S_GET_SEGMENT (fragp->fr_symbol); | |
18493 | need_reloc = (S_FORCE_RELOC (fragp->fr_symbol, TRUE) | |
8507b6e7 | 18494 | || (operand->root.type == OP_PCREL && !mac |
9d862524 MR |
18495 | ? asec != symsec |
18496 | : !bfd_is_abs_section (symsec))); | |
18497 | ||
8507b6e7 | 18498 | if (operand->root.type == OP_PCREL && !mac) |
252b5132 | 18499 | { |
3ccad066 | 18500 | const struct mips_pcrel_operand *pcrel_op; |
252b5132 | 18501 | |
3ccad066 | 18502 | pcrel_op = (const struct mips_pcrel_operand *) operand; |
252b5132 | 18503 | |
14f72d45 | 18504 | if (pcrel_op->include_isa_bit && !need_reloc) |
252b5132 | 18505 | { |
14f72d45 MR |
18506 | if (!ELF_ST_IS_MIPS16 (S_GET_OTHER (fragp->fr_symbol))) |
18507 | as_bad_where (fragp->fr_file, fragp->fr_line, | |
18508 | _("branch to a symbol in another ISA mode")); | |
18509 | else if ((fragp->fr_offset & 0x1) != 0) | |
18510 | as_bad_where (fragp->fr_file, fragp->fr_line, | |
18511 | _("branch to misaligned address (0x%lx)"), | |
18512 | (long) val); | |
252b5132 | 18513 | } |
252b5132 | 18514 | |
14f72d45 | 18515 | val = mips16_pcrel_val (fragp, pcrel_op, val, 0); |
252b5132 RH |
18516 | |
18517 | /* Make sure the section winds up with the alignment we have | |
18518 | assumed. */ | |
3ccad066 RS |
18519 | if (operand->shift > 0) |
18520 | record_alignment (asec, operand->shift); | |
252b5132 RH |
18521 | } |
18522 | ||
8507b6e7 MR |
18523 | if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype) |
18524 | || RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
18525 | { | |
18526 | if (mac) | |
18527 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
18528 | _("macro instruction expanded into multiple " | |
18529 | "instructions in a branch delay slot")); | |
18530 | else if (ext) | |
18531 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
18532 | _("extended instruction in a branch delay slot")); | |
18533 | } | |
18534 | else if (RELAX_MIPS16_NOMACRO (fragp->fr_subtype) && mac) | |
252b5132 | 18535 | as_warn_where (fragp->fr_file, fragp->fr_line, |
8507b6e7 MR |
18536 | _("macro instruction expanded into multiple " |
18537 | "instructions")); | |
252b5132 | 18538 | |
5c04167a | 18539 | buf = fragp->fr_literal + fragp->fr_fix; |
252b5132 | 18540 | |
4d68580a | 18541 | insn = read_compressed_insn (buf, 2); |
5c04167a RS |
18542 | if (ext) |
18543 | insn |= MIPS16_EXTEND; | |
252b5132 | 18544 | |
5c04167a RS |
18545 | if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype)) |
18546 | user_length = 4; | |
18547 | else if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype)) | |
18548 | user_length = 2; | |
18549 | else | |
18550 | user_length = 0; | |
18551 | ||
8507b6e7 | 18552 | if (mac) |
c9775dde | 18553 | { |
8507b6e7 MR |
18554 | unsigned long reg; |
18555 | unsigned long new; | |
18556 | unsigned long op; | |
18557 | ||
18558 | gas_assert (type == 'A' || type == 'B' || type == 'E'); | |
18559 | gas_assert (RELAX_MIPS16_SYM32 (fragp->fr_subtype)); | |
c9775dde | 18560 | |
8507b6e7 | 18561 | if (need_reloc) |
c9775dde | 18562 | { |
8507b6e7 MR |
18563 | fixS *fixp; |
18564 | ||
18565 | gas_assert (!RELAX_MIPS16_PIC (fragp->fr_subtype)); | |
18566 | ||
18567 | fixp = fix_new (fragp, buf - fragp->fr_literal, 4, | |
18568 | fragp->fr_symbol, fragp->fr_offset, | |
18569 | FALSE, BFD_RELOC_MIPS16_HI16_S); | |
18570 | fixp->fx_file = fragp->fr_file; | |
18571 | fixp->fx_line = fragp->fr_line; | |
18572 | ||
18573 | fixp = fix_new (fragp, buf - fragp->fr_literal + 8, 4, | |
18574 | fragp->fr_symbol, fragp->fr_offset, | |
18575 | FALSE, BFD_RELOC_MIPS16_LO16); | |
18576 | fixp->fx_file = fragp->fr_file; | |
18577 | fixp->fx_line = fragp->fr_line; | |
18578 | ||
18579 | val = 0; | |
18580 | } | |
18581 | ||
18582 | switch (insn & 0xf800) | |
18583 | { | |
18584 | case 0x0800: /* ADDIU */ | |
18585 | reg = (insn >> 8) & 0x7; | |
18586 | op = 0xf0004800 | (reg << 8); | |
c9775dde | 18587 | break; |
8507b6e7 MR |
18588 | case 0xb000: /* LW */ |
18589 | reg = (insn >> 8) & 0x7; | |
18590 | op = 0xf0009800 | (reg << 8) | (reg << 5); | |
c9775dde | 18591 | break; |
8507b6e7 MR |
18592 | case 0xf800: /* I64 */ |
18593 | reg = (insn >> 5) & 0x7; | |
18594 | switch (insn & 0x0700) | |
18595 | { | |
18596 | case 0x0400: /* LD */ | |
18597 | op = 0xf0003800 | (reg << 8) | (reg << 5); | |
18598 | break; | |
18599 | case 0x0600: /* DADDIU */ | |
18600 | op = 0xf000fd00 | (reg << 5); | |
18601 | break; | |
18602 | default: | |
18603 | abort (); | |
18604 | } | |
18605 | break; | |
18606 | default: | |
18607 | abort (); | |
c9775dde | 18608 | } |
8507b6e7 MR |
18609 | |
18610 | new = 0xf0006800 | (reg << 8); /* LI */ | |
18611 | new |= mips16_immed_extend ((val + 0x8000) >> 16, 16); | |
18612 | buf = write_compressed_insn (buf, new, 4); | |
18613 | new = 0xf4003000 | (reg << 8) | (reg << 5); /* SLL */ | |
18614 | buf = write_compressed_insn (buf, new, 4); | |
18615 | op |= mips16_immed_extend (val, 16); | |
18616 | buf = write_compressed_insn (buf, op, 4); | |
18617 | ||
18618 | fragp->fr_fix += 12; | |
18619 | } | |
18620 | else | |
18621 | { | |
18622 | unsigned int length = ext ? 4 : 2; | |
18623 | ||
18624 | if (need_reloc) | |
c9775dde | 18625 | { |
8507b6e7 MR |
18626 | bfd_reloc_code_real_type reloc = BFD_RELOC_NONE; |
18627 | expressionS exp; | |
18628 | fixS *fixp; | |
c9775dde | 18629 | |
8507b6e7 MR |
18630 | switch (type) |
18631 | { | |
18632 | case 'p': | |
18633 | case 'q': | |
18634 | reloc = BFD_RELOC_MIPS16_16_PCREL_S1; | |
18635 | break; | |
18636 | default: | |
18637 | break; | |
18638 | } | |
18639 | if (mac || reloc == BFD_RELOC_NONE) | |
18640 | as_bad_where (fragp->fr_file, fragp->fr_line, | |
18641 | _("unsupported relocation")); | |
18642 | else if (ext) | |
18643 | { | |
18644 | exp.X_op = O_symbol; | |
18645 | exp.X_add_symbol = fragp->fr_symbol; | |
18646 | exp.X_add_number = fragp->fr_offset; | |
c9775dde | 18647 | |
8507b6e7 MR |
18648 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, |
18649 | TRUE, reloc); | |
18650 | ||
18651 | fixp->fx_file = fragp->fr_file; | |
18652 | fixp->fx_line = fragp->fr_line; | |
18653 | } | |
18654 | else | |
18655 | as_bad_where (fragp->fr_file, fragp->fr_line, | |
18656 | _("invalid unextended operand value")); | |
c9775dde | 18657 | } |
eefc3365 | 18658 | else |
8507b6e7 MR |
18659 | mips16_immed (fragp->fr_file, fragp->fr_line, type, |
18660 | BFD_RELOC_UNUSED, val, user_length, &insn); | |
252b5132 | 18661 | |
8507b6e7 MR |
18662 | gas_assert (mips16_opcode_length (insn) == length); |
18663 | write_compressed_insn (buf, insn, length); | |
18664 | fragp->fr_fix += length; | |
18665 | } | |
252b5132 RH |
18666 | } |
18667 | else | |
18668 | { | |
df58fc94 RS |
18669 | relax_substateT subtype = fragp->fr_subtype; |
18670 | bfd_boolean second_longer = (subtype & RELAX_SECOND_LONGER) != 0; | |
18671 | bfd_boolean use_second = (subtype & RELAX_USE_SECOND) != 0; | |
4d7206a2 RS |
18672 | int first, second; |
18673 | fixS *fixp; | |
252b5132 | 18674 | |
df58fc94 RS |
18675 | first = RELAX_FIRST (subtype); |
18676 | second = RELAX_SECOND (subtype); | |
4d7206a2 | 18677 | fixp = (fixS *) fragp->fr_opcode; |
252b5132 | 18678 | |
df58fc94 RS |
18679 | /* If the delay slot chosen does not match the size of the instruction, |
18680 | then emit a warning. */ | |
18681 | if ((!use_second && (subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0) | |
18682 | || (use_second && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0)) | |
18683 | { | |
18684 | relax_substateT s; | |
18685 | const char *msg; | |
18686 | ||
18687 | s = subtype & (RELAX_DELAY_SLOT_16BIT | |
18688 | | RELAX_DELAY_SLOT_SIZE_FIRST | |
18689 | | RELAX_DELAY_SLOT_SIZE_SECOND); | |
18690 | msg = macro_warning (s); | |
18691 | if (msg != NULL) | |
db9b2be4 | 18692 | as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg); |
df58fc94 RS |
18693 | subtype &= ~s; |
18694 | } | |
18695 | ||
584892a6 | 18696 | /* Possibly emit a warning if we've chosen the longer option. */ |
df58fc94 | 18697 | if (use_second == second_longer) |
584892a6 | 18698 | { |
df58fc94 RS |
18699 | relax_substateT s; |
18700 | const char *msg; | |
18701 | ||
18702 | s = (subtype | |
18703 | & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT)); | |
18704 | msg = macro_warning (s); | |
18705 | if (msg != NULL) | |
db9b2be4 | 18706 | as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg); |
df58fc94 | 18707 | subtype &= ~s; |
584892a6 RS |
18708 | } |
18709 | ||
4d7206a2 RS |
18710 | /* Go through all the fixups for the first sequence. Disable them |
18711 | (by marking them as done) if we're going to use the second | |
18712 | sequence instead. */ | |
18713 | while (fixp | |
18714 | && fixp->fx_frag == fragp | |
18715 | && fixp->fx_where < fragp->fr_fix - second) | |
18716 | { | |
df58fc94 | 18717 | if (subtype & RELAX_USE_SECOND) |
4d7206a2 RS |
18718 | fixp->fx_done = 1; |
18719 | fixp = fixp->fx_next; | |
18720 | } | |
252b5132 | 18721 | |
4d7206a2 RS |
18722 | /* Go through the fixups for the second sequence. Disable them if |
18723 | we're going to use the first sequence, otherwise adjust their | |
18724 | addresses to account for the relaxation. */ | |
18725 | while (fixp && fixp->fx_frag == fragp) | |
18726 | { | |
df58fc94 | 18727 | if (subtype & RELAX_USE_SECOND) |
4d7206a2 RS |
18728 | fixp->fx_where -= first; |
18729 | else | |
18730 | fixp->fx_done = 1; | |
18731 | fixp = fixp->fx_next; | |
18732 | } | |
18733 | ||
18734 | /* Now modify the frag contents. */ | |
df58fc94 | 18735 | if (subtype & RELAX_USE_SECOND) |
4d7206a2 RS |
18736 | { |
18737 | char *start; | |
18738 | ||
18739 | start = fragp->fr_literal + fragp->fr_fix - first - second; | |
18740 | memmove (start, start + first, second); | |
18741 | fragp->fr_fix -= first; | |
18742 | } | |
18743 | else | |
18744 | fragp->fr_fix -= second; | |
252b5132 RH |
18745 | } |
18746 | } | |
18747 | ||
252b5132 RH |
18748 | /* This function is called after the relocs have been generated. |
18749 | We've been storing mips16 text labels as odd. Here we convert them | |
18750 | back to even for the convenience of the debugger. */ | |
18751 | ||
18752 | void | |
17a2f251 | 18753 | mips_frob_file_after_relocs (void) |
252b5132 RH |
18754 | { |
18755 | asymbol **syms; | |
18756 | unsigned int count, i; | |
18757 | ||
252b5132 RH |
18758 | syms = bfd_get_outsymbols (stdoutput); |
18759 | count = bfd_get_symcount (stdoutput); | |
18760 | for (i = 0; i < count; i++, syms++) | |
df58fc94 RS |
18761 | if (ELF_ST_IS_COMPRESSED (elf_symbol (*syms)->internal_elf_sym.st_other) |
18762 | && ((*syms)->value & 1) != 0) | |
18763 | { | |
18764 | (*syms)->value &= ~1; | |
18765 | /* If the symbol has an odd size, it was probably computed | |
18766 | incorrectly, so adjust that as well. */ | |
18767 | if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0) | |
18768 | ++elf_symbol (*syms)->internal_elf_sym.st_size; | |
18769 | } | |
252b5132 RH |
18770 | } |
18771 | ||
a1facbec MR |
18772 | /* This function is called whenever a label is defined, including fake |
18773 | labels instantiated off the dot special symbol. It is used when | |
18774 | handling branch delays; if a branch has a label, we assume we cannot | |
18775 | move it. This also bumps the value of the symbol by 1 in compressed | |
18776 | code. */ | |
252b5132 | 18777 | |
e1b47bd5 | 18778 | static void |
a1facbec | 18779 | mips_record_label (symbolS *sym) |
252b5132 | 18780 | { |
a8dbcb85 | 18781 | segment_info_type *si = seg_info (now_seg); |
252b5132 RH |
18782 | struct insn_label_list *l; |
18783 | ||
18784 | if (free_insn_labels == NULL) | |
325801bd | 18785 | l = XNEW (struct insn_label_list); |
252b5132 RH |
18786 | else |
18787 | { | |
18788 | l = free_insn_labels; | |
18789 | free_insn_labels = l->next; | |
18790 | } | |
18791 | ||
18792 | l->label = sym; | |
a8dbcb85 TS |
18793 | l->next = si->label_list; |
18794 | si->label_list = l; | |
a1facbec | 18795 | } |
07a53e5c | 18796 | |
a1facbec MR |
18797 | /* This function is called as tc_frob_label() whenever a label is defined |
18798 | and adds a DWARF-2 record we only want for true labels. */ | |
18799 | ||
18800 | void | |
18801 | mips_define_label (symbolS *sym) | |
18802 | { | |
18803 | mips_record_label (sym); | |
07a53e5c | 18804 | dwarf2_emit_label (sym); |
252b5132 | 18805 | } |
e1b47bd5 RS |
18806 | |
18807 | /* This function is called by tc_new_dot_label whenever a new dot symbol | |
18808 | is defined. */ | |
18809 | ||
18810 | void | |
18811 | mips_add_dot_label (symbolS *sym) | |
18812 | { | |
18813 | mips_record_label (sym); | |
18814 | if (mips_assembling_insn && HAVE_CODE_COMPRESSION) | |
18815 | mips_compressed_mark_label (sym); | |
18816 | } | |
252b5132 | 18817 | \f |
351cdf24 MF |
18818 | /* Converting ASE flags from internal to .MIPS.abiflags values. */ |
18819 | static unsigned int | |
18820 | mips_convert_ase_flags (int ase) | |
18821 | { | |
18822 | unsigned int ext_ases = 0; | |
18823 | ||
18824 | if (ase & ASE_DSP) | |
18825 | ext_ases |= AFL_ASE_DSP; | |
18826 | if (ase & ASE_DSPR2) | |
18827 | ext_ases |= AFL_ASE_DSPR2; | |
8f4f9071 MF |
18828 | if (ase & ASE_DSPR3) |
18829 | ext_ases |= AFL_ASE_DSPR3; | |
351cdf24 MF |
18830 | if (ase & ASE_EVA) |
18831 | ext_ases |= AFL_ASE_EVA; | |
18832 | if (ase & ASE_MCU) | |
18833 | ext_ases |= AFL_ASE_MCU; | |
18834 | if (ase & ASE_MDMX) | |
18835 | ext_ases |= AFL_ASE_MDMX; | |
18836 | if (ase & ASE_MIPS3D) | |
18837 | ext_ases |= AFL_ASE_MIPS3D; | |
18838 | if (ase & ASE_MT) | |
18839 | ext_ases |= AFL_ASE_MT; | |
18840 | if (ase & ASE_SMARTMIPS) | |
18841 | ext_ases |= AFL_ASE_SMARTMIPS; | |
18842 | if (ase & ASE_VIRT) | |
18843 | ext_ases |= AFL_ASE_VIRT; | |
18844 | if (ase & ASE_MSA) | |
18845 | ext_ases |= AFL_ASE_MSA; | |
18846 | if (ase & ASE_XPA) | |
18847 | ext_ases |= AFL_ASE_XPA; | |
18848 | ||
18849 | return ext_ases; | |
18850 | } | |
252b5132 RH |
18851 | /* Some special processing for a MIPS ELF file. */ |
18852 | ||
18853 | void | |
17a2f251 | 18854 | mips_elf_final_processing (void) |
252b5132 | 18855 | { |
351cdf24 MF |
18856 | int fpabi; |
18857 | Elf_Internal_ABIFlags_v0 flags; | |
18858 | ||
18859 | flags.version = 0; | |
18860 | flags.isa_rev = 0; | |
18861 | switch (file_mips_opts.isa) | |
18862 | { | |
18863 | case INSN_ISA1: | |
18864 | flags.isa_level = 1; | |
18865 | break; | |
18866 | case INSN_ISA2: | |
18867 | flags.isa_level = 2; | |
18868 | break; | |
18869 | case INSN_ISA3: | |
18870 | flags.isa_level = 3; | |
18871 | break; | |
18872 | case INSN_ISA4: | |
18873 | flags.isa_level = 4; | |
18874 | break; | |
18875 | case INSN_ISA5: | |
18876 | flags.isa_level = 5; | |
18877 | break; | |
18878 | case INSN_ISA32: | |
18879 | flags.isa_level = 32; | |
18880 | flags.isa_rev = 1; | |
18881 | break; | |
18882 | case INSN_ISA32R2: | |
18883 | flags.isa_level = 32; | |
18884 | flags.isa_rev = 2; | |
18885 | break; | |
18886 | case INSN_ISA32R3: | |
18887 | flags.isa_level = 32; | |
18888 | flags.isa_rev = 3; | |
18889 | break; | |
18890 | case INSN_ISA32R5: | |
18891 | flags.isa_level = 32; | |
18892 | flags.isa_rev = 5; | |
18893 | break; | |
09c14161 MF |
18894 | case INSN_ISA32R6: |
18895 | flags.isa_level = 32; | |
18896 | flags.isa_rev = 6; | |
18897 | break; | |
351cdf24 MF |
18898 | case INSN_ISA64: |
18899 | flags.isa_level = 64; | |
18900 | flags.isa_rev = 1; | |
18901 | break; | |
18902 | case INSN_ISA64R2: | |
18903 | flags.isa_level = 64; | |
18904 | flags.isa_rev = 2; | |
18905 | break; | |
18906 | case INSN_ISA64R3: | |
18907 | flags.isa_level = 64; | |
18908 | flags.isa_rev = 3; | |
18909 | break; | |
18910 | case INSN_ISA64R5: | |
18911 | flags.isa_level = 64; | |
18912 | flags.isa_rev = 5; | |
18913 | break; | |
09c14161 MF |
18914 | case INSN_ISA64R6: |
18915 | flags.isa_level = 64; | |
18916 | flags.isa_rev = 6; | |
18917 | break; | |
351cdf24 MF |
18918 | } |
18919 | ||
18920 | flags.gpr_size = file_mips_opts.gp == 32 ? AFL_REG_32 : AFL_REG_64; | |
18921 | flags.cpr1_size = file_mips_opts.soft_float ? AFL_REG_NONE | |
18922 | : (file_mips_opts.ase & ASE_MSA) ? AFL_REG_128 | |
18923 | : (file_mips_opts.fp == 64) ? AFL_REG_64 | |
18924 | : AFL_REG_32; | |
18925 | flags.cpr2_size = AFL_REG_NONE; | |
18926 | flags.fp_abi = bfd_elf_get_obj_attr_int (stdoutput, OBJ_ATTR_GNU, | |
18927 | Tag_GNU_MIPS_ABI_FP); | |
18928 | flags.isa_ext = bfd_mips_isa_ext (stdoutput); | |
18929 | flags.ases = mips_convert_ase_flags (file_mips_opts.ase); | |
18930 | if (file_ase_mips16) | |
18931 | flags.ases |= AFL_ASE_MIPS16; | |
18932 | if (file_ase_micromips) | |
18933 | flags.ases |= AFL_ASE_MICROMIPS; | |
18934 | flags.flags1 = 0; | |
18935 | if ((ISA_HAS_ODD_SINGLE_FPR (file_mips_opts.isa, file_mips_opts.arch) | |
18936 | || file_mips_opts.fp == 64) | |
18937 | && file_mips_opts.oddspreg) | |
18938 | flags.flags1 |= AFL_FLAGS1_ODDSPREG; | |
18939 | flags.flags2 = 0; | |
18940 | ||
18941 | bfd_mips_elf_swap_abiflags_v0_out (stdoutput, &flags, | |
18942 | ((Elf_External_ABIFlags_v0 *) | |
18943 | mips_flags_frag)); | |
18944 | ||
252b5132 | 18945 | /* Write out the register information. */ |
316f5878 | 18946 | if (mips_abi != N64_ABI) |
252b5132 RH |
18947 | { |
18948 | Elf32_RegInfo s; | |
18949 | ||
18950 | s.ri_gprmask = mips_gprmask; | |
18951 | s.ri_cprmask[0] = mips_cprmask[0]; | |
18952 | s.ri_cprmask[1] = mips_cprmask[1]; | |
18953 | s.ri_cprmask[2] = mips_cprmask[2]; | |
18954 | s.ri_cprmask[3] = mips_cprmask[3]; | |
18955 | /* The gp_value field is set by the MIPS ELF backend. */ | |
18956 | ||
18957 | bfd_mips_elf32_swap_reginfo_out (stdoutput, &s, | |
18958 | ((Elf32_External_RegInfo *) | |
18959 | mips_regmask_frag)); | |
18960 | } | |
18961 | else | |
18962 | { | |
18963 | Elf64_Internal_RegInfo s; | |
18964 | ||
18965 | s.ri_gprmask = mips_gprmask; | |
18966 | s.ri_pad = 0; | |
18967 | s.ri_cprmask[0] = mips_cprmask[0]; | |
18968 | s.ri_cprmask[1] = mips_cprmask[1]; | |
18969 | s.ri_cprmask[2] = mips_cprmask[2]; | |
18970 | s.ri_cprmask[3] = mips_cprmask[3]; | |
18971 | /* The gp_value field is set by the MIPS ELF backend. */ | |
18972 | ||
18973 | bfd_mips_elf64_swap_reginfo_out (stdoutput, &s, | |
18974 | ((Elf64_External_RegInfo *) | |
18975 | mips_regmask_frag)); | |
18976 | } | |
18977 | ||
18978 | /* Set the MIPS ELF flag bits. FIXME: There should probably be some | |
18979 | sort of BFD interface for this. */ | |
18980 | if (mips_any_noreorder) | |
18981 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER; | |
18982 | if (mips_pic != NO_PIC) | |
143d77c5 | 18983 | { |
8b828383 | 18984 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC; |
143d77c5 EC |
18985 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC; |
18986 | } | |
18987 | if (mips_abicalls) | |
18988 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC; | |
252b5132 | 18989 | |
b015e599 AP |
18990 | /* Set MIPS ELF flags for ASEs. Note that not all ASEs have flags |
18991 | defined at present; this might need to change in future. */ | |
a4672219 TS |
18992 | if (file_ase_mips16) |
18993 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16; | |
df58fc94 RS |
18994 | if (file_ase_micromips) |
18995 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MICROMIPS; | |
919731af | 18996 | if (file_mips_opts.ase & ASE_MDMX) |
deec1734 | 18997 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX; |
1f25f5d3 | 18998 | |
bdaaa2e1 | 18999 | /* Set the MIPS ELF ABI flags. */ |
316f5878 | 19000 | if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32) |
252b5132 | 19001 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32; |
316f5878 | 19002 | else if (mips_abi == O64_ABI) |
252b5132 | 19003 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64; |
316f5878 | 19004 | else if (mips_abi == EABI_ABI) |
252b5132 | 19005 | { |
bad1aba3 | 19006 | if (file_mips_opts.gp == 64) |
252b5132 RH |
19007 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64; |
19008 | else | |
19009 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32; | |
19010 | } | |
316f5878 | 19011 | else if (mips_abi == N32_ABI) |
be00bddd TS |
19012 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2; |
19013 | ||
c9914766 | 19014 | /* Nothing to do for N64_ABI. */ |
252b5132 RH |
19015 | |
19016 | if (mips_32bitmode) | |
19017 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE; | |
ad3fea08 | 19018 | |
7361da2c | 19019 | if (mips_nan2008 == 1) |
ba92f887 MR |
19020 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NAN2008; |
19021 | ||
ad3fea08 | 19022 | /* 32 bit code with 64 bit FP registers. */ |
351cdf24 MF |
19023 | fpabi = bfd_elf_get_obj_attr_int (stdoutput, OBJ_ATTR_GNU, |
19024 | Tag_GNU_MIPS_ABI_FP); | |
19025 | if (fpabi == Val_GNU_MIPS_ABI_FP_OLD_64) | |
f1c38003 | 19026 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_FP64; |
252b5132 | 19027 | } |
252b5132 | 19028 | \f |
beae10d5 | 19029 | typedef struct proc { |
9b2f1d35 EC |
19030 | symbolS *func_sym; |
19031 | symbolS *func_end_sym; | |
beae10d5 KH |
19032 | unsigned long reg_mask; |
19033 | unsigned long reg_offset; | |
19034 | unsigned long fpreg_mask; | |
19035 | unsigned long fpreg_offset; | |
19036 | unsigned long frame_offset; | |
19037 | unsigned long frame_reg; | |
19038 | unsigned long pc_reg; | |
19039 | } procS; | |
252b5132 RH |
19040 | |
19041 | static procS cur_proc; | |
19042 | static procS *cur_proc_ptr; | |
19043 | static int numprocs; | |
19044 | ||
df58fc94 RS |
19045 | /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1", a microMIPS nop |
19046 | as "2", and a normal nop as "0". */ | |
19047 | ||
19048 | #define NOP_OPCODE_MIPS 0 | |
19049 | #define NOP_OPCODE_MIPS16 1 | |
19050 | #define NOP_OPCODE_MICROMIPS 2 | |
742a56fe RS |
19051 | |
19052 | char | |
19053 | mips_nop_opcode (void) | |
19054 | { | |
df58fc94 RS |
19055 | if (seg_info (now_seg)->tc_segment_info_data.micromips) |
19056 | return NOP_OPCODE_MICROMIPS; | |
19057 | else if (seg_info (now_seg)->tc_segment_info_data.mips16) | |
19058 | return NOP_OPCODE_MIPS16; | |
19059 | else | |
19060 | return NOP_OPCODE_MIPS; | |
742a56fe RS |
19061 | } |
19062 | ||
df58fc94 RS |
19063 | /* Fill in an rs_align_code fragment. Unlike elsewhere we want to use |
19064 | 32-bit microMIPS NOPs here (if applicable). */ | |
a19d8eb0 | 19065 | |
0a9ef439 | 19066 | void |
17a2f251 | 19067 | mips_handle_align (fragS *fragp) |
a19d8eb0 | 19068 | { |
df58fc94 | 19069 | char nop_opcode; |
742a56fe | 19070 | char *p; |
c67a084a NC |
19071 | int bytes, size, excess; |
19072 | valueT opcode; | |
742a56fe | 19073 | |
0a9ef439 RH |
19074 | if (fragp->fr_type != rs_align_code) |
19075 | return; | |
19076 | ||
742a56fe | 19077 | p = fragp->fr_literal + fragp->fr_fix; |
df58fc94 RS |
19078 | nop_opcode = *p; |
19079 | switch (nop_opcode) | |
a19d8eb0 | 19080 | { |
df58fc94 RS |
19081 | case NOP_OPCODE_MICROMIPS: |
19082 | opcode = micromips_nop32_insn.insn_opcode; | |
19083 | size = 4; | |
19084 | break; | |
19085 | case NOP_OPCODE_MIPS16: | |
c67a084a NC |
19086 | opcode = mips16_nop_insn.insn_opcode; |
19087 | size = 2; | |
df58fc94 RS |
19088 | break; |
19089 | case NOP_OPCODE_MIPS: | |
19090 | default: | |
c67a084a NC |
19091 | opcode = nop_insn.insn_opcode; |
19092 | size = 4; | |
df58fc94 | 19093 | break; |
c67a084a | 19094 | } |
a19d8eb0 | 19095 | |
c67a084a NC |
19096 | bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix; |
19097 | excess = bytes % size; | |
df58fc94 RS |
19098 | |
19099 | /* Handle the leading part if we're not inserting a whole number of | |
19100 | instructions, and make it the end of the fixed part of the frag. | |
19101 | Try to fit in a short microMIPS NOP if applicable and possible, | |
19102 | and use zeroes otherwise. */ | |
19103 | gas_assert (excess < 4); | |
19104 | fragp->fr_fix += excess; | |
19105 | switch (excess) | |
c67a084a | 19106 | { |
df58fc94 RS |
19107 | case 3: |
19108 | *p++ = '\0'; | |
19109 | /* Fall through. */ | |
19110 | case 2: | |
833794fc | 19111 | if (nop_opcode == NOP_OPCODE_MICROMIPS && !mips_opts.insn32) |
df58fc94 | 19112 | { |
4d68580a | 19113 | p = write_compressed_insn (p, micromips_nop16_insn.insn_opcode, 2); |
df58fc94 RS |
19114 | break; |
19115 | } | |
19116 | *p++ = '\0'; | |
19117 | /* Fall through. */ | |
19118 | case 1: | |
19119 | *p++ = '\0'; | |
19120 | /* Fall through. */ | |
19121 | case 0: | |
19122 | break; | |
a19d8eb0 | 19123 | } |
c67a084a NC |
19124 | |
19125 | md_number_to_chars (p, opcode, size); | |
19126 | fragp->fr_var = size; | |
a19d8eb0 CP |
19127 | } |
19128 | ||
252b5132 | 19129 | static long |
17a2f251 | 19130 | get_number (void) |
252b5132 RH |
19131 | { |
19132 | int negative = 0; | |
19133 | long val = 0; | |
19134 | ||
19135 | if (*input_line_pointer == '-') | |
19136 | { | |
19137 | ++input_line_pointer; | |
19138 | negative = 1; | |
19139 | } | |
3882b010 | 19140 | if (!ISDIGIT (*input_line_pointer)) |
956cd1d6 | 19141 | as_bad (_("expected simple number")); |
252b5132 RH |
19142 | if (input_line_pointer[0] == '0') |
19143 | { | |
19144 | if (input_line_pointer[1] == 'x') | |
19145 | { | |
19146 | input_line_pointer += 2; | |
3882b010 | 19147 | while (ISXDIGIT (*input_line_pointer)) |
252b5132 RH |
19148 | { |
19149 | val <<= 4; | |
19150 | val |= hex_value (*input_line_pointer++); | |
19151 | } | |
19152 | return negative ? -val : val; | |
19153 | } | |
19154 | else | |
19155 | { | |
19156 | ++input_line_pointer; | |
3882b010 | 19157 | while (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
19158 | { |
19159 | val <<= 3; | |
19160 | val |= *input_line_pointer++ - '0'; | |
19161 | } | |
19162 | return negative ? -val : val; | |
19163 | } | |
19164 | } | |
3882b010 | 19165 | if (!ISDIGIT (*input_line_pointer)) |
252b5132 RH |
19166 | { |
19167 | printf (_(" *input_line_pointer == '%c' 0x%02x\n"), | |
19168 | *input_line_pointer, *input_line_pointer); | |
956cd1d6 | 19169 | as_warn (_("invalid number")); |
252b5132 RH |
19170 | return -1; |
19171 | } | |
3882b010 | 19172 | while (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
19173 | { |
19174 | val *= 10; | |
19175 | val += *input_line_pointer++ - '0'; | |
19176 | } | |
19177 | return negative ? -val : val; | |
19178 | } | |
19179 | ||
19180 | /* The .file directive; just like the usual .file directive, but there | |
c5dd6aab DJ |
19181 | is an initial number which is the ECOFF file index. In the non-ECOFF |
19182 | case .file implies DWARF-2. */ | |
19183 | ||
19184 | static void | |
17a2f251 | 19185 | s_mips_file (int x ATTRIBUTE_UNUSED) |
c5dd6aab | 19186 | { |
ecb4347a DJ |
19187 | static int first_file_directive = 0; |
19188 | ||
c5dd6aab DJ |
19189 | if (ECOFF_DEBUGGING) |
19190 | { | |
19191 | get_number (); | |
19192 | s_app_file (0); | |
19193 | } | |
19194 | else | |
ecb4347a DJ |
19195 | { |
19196 | char *filename; | |
19197 | ||
19198 | filename = dwarf2_directive_file (0); | |
19199 | ||
19200 | /* Versions of GCC up to 3.1 start files with a ".file" | |
19201 | directive even for stabs output. Make sure that this | |
19202 | ".file" is handled. Note that you need a version of GCC | |
19203 | after 3.1 in order to support DWARF-2 on MIPS. */ | |
19204 | if (filename != NULL && ! first_file_directive) | |
19205 | { | |
19206 | (void) new_logical_line (filename, -1); | |
c04f5787 | 19207 | s_app_file_string (filename, 0); |
ecb4347a DJ |
19208 | } |
19209 | first_file_directive = 1; | |
19210 | } | |
c5dd6aab DJ |
19211 | } |
19212 | ||
19213 | /* The .loc directive, implying DWARF-2. */ | |
252b5132 RH |
19214 | |
19215 | static void | |
17a2f251 | 19216 | s_mips_loc (int x ATTRIBUTE_UNUSED) |
252b5132 | 19217 | { |
c5dd6aab DJ |
19218 | if (!ECOFF_DEBUGGING) |
19219 | dwarf2_directive_loc (0); | |
252b5132 RH |
19220 | } |
19221 | ||
252b5132 RH |
19222 | /* The .end directive. */ |
19223 | ||
19224 | static void | |
17a2f251 | 19225 | s_mips_end (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
19226 | { |
19227 | symbolS *p; | |
252b5132 | 19228 | |
7a621144 DJ |
19229 | /* Following functions need their own .frame and .cprestore directives. */ |
19230 | mips_frame_reg_valid = 0; | |
19231 | mips_cprestore_valid = 0; | |
19232 | ||
252b5132 RH |
19233 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
19234 | { | |
19235 | p = get_symbol (); | |
19236 | demand_empty_rest_of_line (); | |
19237 | } | |
19238 | else | |
19239 | p = NULL; | |
19240 | ||
14949570 | 19241 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0) |
252b5132 RH |
19242 | as_warn (_(".end not in text section")); |
19243 | ||
19244 | if (!cur_proc_ptr) | |
19245 | { | |
1661c76c | 19246 | as_warn (_(".end directive without a preceding .ent directive")); |
252b5132 RH |
19247 | demand_empty_rest_of_line (); |
19248 | return; | |
19249 | } | |
19250 | ||
19251 | if (p != NULL) | |
19252 | { | |
9c2799c2 | 19253 | gas_assert (S_GET_NAME (p)); |
9b2f1d35 | 19254 | if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->func_sym))) |
1661c76c | 19255 | as_warn (_(".end symbol does not match .ent symbol")); |
ecb4347a DJ |
19256 | |
19257 | if (debug_type == DEBUG_STABS) | |
19258 | stabs_generate_asm_endfunc (S_GET_NAME (p), | |
19259 | S_GET_NAME (p)); | |
252b5132 RH |
19260 | } |
19261 | else | |
19262 | as_warn (_(".end directive missing or unknown symbol")); | |
19263 | ||
9b2f1d35 EC |
19264 | /* Create an expression to calculate the size of the function. */ |
19265 | if (p && cur_proc_ptr) | |
19266 | { | |
19267 | OBJ_SYMFIELD_TYPE *obj = symbol_get_obj (p); | |
325801bd | 19268 | expressionS *exp = XNEW (expressionS); |
9b2f1d35 EC |
19269 | |
19270 | obj->size = exp; | |
19271 | exp->X_op = O_subtract; | |
19272 | exp->X_add_symbol = symbol_temp_new_now (); | |
19273 | exp->X_op_symbol = p; | |
19274 | exp->X_add_number = 0; | |
19275 | ||
19276 | cur_proc_ptr->func_end_sym = exp->X_add_symbol; | |
19277 | } | |
19278 | ||
5ff6a06c MR |
19279 | #ifdef md_flush_pending_output |
19280 | md_flush_pending_output (); | |
19281 | #endif | |
19282 | ||
ecb4347a | 19283 | /* Generate a .pdr section. */ |
f3ded42a | 19284 | if (!ECOFF_DEBUGGING && mips_flag_pdr) |
ecb4347a DJ |
19285 | { |
19286 | segT saved_seg = now_seg; | |
19287 | subsegT saved_subseg = now_subseg; | |
ecb4347a DJ |
19288 | expressionS exp; |
19289 | char *fragp; | |
252b5132 | 19290 | |
9c2799c2 | 19291 | gas_assert (pdr_seg); |
ecb4347a | 19292 | subseg_set (pdr_seg, 0); |
252b5132 | 19293 | |
ecb4347a DJ |
19294 | /* Write the symbol. */ |
19295 | exp.X_op = O_symbol; | |
19296 | exp.X_add_symbol = p; | |
19297 | exp.X_add_number = 0; | |
19298 | emit_expr (&exp, 4); | |
252b5132 | 19299 | |
ecb4347a | 19300 | fragp = frag_more (7 * 4); |
252b5132 | 19301 | |
17a2f251 TS |
19302 | md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4); |
19303 | md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4); | |
19304 | md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4); | |
19305 | md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4); | |
19306 | md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4); | |
19307 | md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4); | |
19308 | md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4); | |
252b5132 | 19309 | |
ecb4347a DJ |
19310 | subseg_set (saved_seg, saved_subseg); |
19311 | } | |
252b5132 RH |
19312 | |
19313 | cur_proc_ptr = NULL; | |
19314 | } | |
19315 | ||
19316 | /* The .aent and .ent directives. */ | |
19317 | ||
19318 | static void | |
17a2f251 | 19319 | s_mips_ent (int aent) |
252b5132 | 19320 | { |
252b5132 | 19321 | symbolS *symbolP; |
252b5132 RH |
19322 | |
19323 | symbolP = get_symbol (); | |
19324 | if (*input_line_pointer == ',') | |
f9419b05 | 19325 | ++input_line_pointer; |
252b5132 | 19326 | SKIP_WHITESPACE (); |
3882b010 | 19327 | if (ISDIGIT (*input_line_pointer) |
d9a62219 | 19328 | || *input_line_pointer == '-') |
874e8986 | 19329 | get_number (); |
252b5132 | 19330 | |
14949570 | 19331 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0) |
1661c76c | 19332 | as_warn (_(".ent or .aent not in text section")); |
252b5132 RH |
19333 | |
19334 | if (!aent && cur_proc_ptr) | |
9a41af64 | 19335 | as_warn (_("missing .end")); |
252b5132 RH |
19336 | |
19337 | if (!aent) | |
19338 | { | |
7a621144 DJ |
19339 | /* This function needs its own .frame and .cprestore directives. */ |
19340 | mips_frame_reg_valid = 0; | |
19341 | mips_cprestore_valid = 0; | |
19342 | ||
252b5132 RH |
19343 | cur_proc_ptr = &cur_proc; |
19344 | memset (cur_proc_ptr, '\0', sizeof (procS)); | |
19345 | ||
9b2f1d35 | 19346 | cur_proc_ptr->func_sym = symbolP; |
252b5132 | 19347 | |
f9419b05 | 19348 | ++numprocs; |
ecb4347a DJ |
19349 | |
19350 | if (debug_type == DEBUG_STABS) | |
19351 | stabs_generate_asm_func (S_GET_NAME (symbolP), | |
19352 | S_GET_NAME (symbolP)); | |
252b5132 RH |
19353 | } |
19354 | ||
7c0fc524 MR |
19355 | symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION; |
19356 | ||
252b5132 RH |
19357 | demand_empty_rest_of_line (); |
19358 | } | |
19359 | ||
19360 | /* The .frame directive. If the mdebug section is present (IRIX 5 native) | |
bdaaa2e1 | 19361 | then ecoff.c (ecoff_directive_frame) is used. For embedded targets, |
252b5132 | 19362 | s_mips_frame is used so that we can set the PDR information correctly. |
bdaaa2e1 | 19363 | We can't use the ecoff routines because they make reference to the ecoff |
252b5132 RH |
19364 | symbol table (in the mdebug section). */ |
19365 | ||
19366 | static void | |
17a2f251 | 19367 | s_mips_frame (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 19368 | { |
f3ded42a RS |
19369 | if (ECOFF_DEBUGGING) |
19370 | s_ignore (ignore); | |
19371 | else | |
ecb4347a DJ |
19372 | { |
19373 | long val; | |
252b5132 | 19374 | |
ecb4347a DJ |
19375 | if (cur_proc_ptr == (procS *) NULL) |
19376 | { | |
19377 | as_warn (_(".frame outside of .ent")); | |
19378 | demand_empty_rest_of_line (); | |
19379 | return; | |
19380 | } | |
252b5132 | 19381 | |
ecb4347a DJ |
19382 | cur_proc_ptr->frame_reg = tc_get_register (1); |
19383 | ||
19384 | SKIP_WHITESPACE (); | |
19385 | if (*input_line_pointer++ != ',' | |
19386 | || get_absolute_expression_and_terminator (&val) != ',') | |
19387 | { | |
1661c76c | 19388 | as_warn (_("bad .frame directive")); |
ecb4347a DJ |
19389 | --input_line_pointer; |
19390 | demand_empty_rest_of_line (); | |
19391 | return; | |
19392 | } | |
252b5132 | 19393 | |
ecb4347a DJ |
19394 | cur_proc_ptr->frame_offset = val; |
19395 | cur_proc_ptr->pc_reg = tc_get_register (0); | |
252b5132 | 19396 | |
252b5132 | 19397 | demand_empty_rest_of_line (); |
252b5132 | 19398 | } |
252b5132 RH |
19399 | } |
19400 | ||
bdaaa2e1 KH |
19401 | /* The .fmask and .mask directives. If the mdebug section is present |
19402 | (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For | |
252b5132 | 19403 | embedded targets, s_mips_mask is used so that we can set the PDR |
bdaaa2e1 | 19404 | information correctly. We can't use the ecoff routines because they |
252b5132 RH |
19405 | make reference to the ecoff symbol table (in the mdebug section). */ |
19406 | ||
19407 | static void | |
17a2f251 | 19408 | s_mips_mask (int reg_type) |
252b5132 | 19409 | { |
f3ded42a RS |
19410 | if (ECOFF_DEBUGGING) |
19411 | s_ignore (reg_type); | |
19412 | else | |
252b5132 | 19413 | { |
ecb4347a | 19414 | long mask, off; |
252b5132 | 19415 | |
ecb4347a DJ |
19416 | if (cur_proc_ptr == (procS *) NULL) |
19417 | { | |
19418 | as_warn (_(".mask/.fmask outside of .ent")); | |
19419 | demand_empty_rest_of_line (); | |
19420 | return; | |
19421 | } | |
252b5132 | 19422 | |
ecb4347a DJ |
19423 | if (get_absolute_expression_and_terminator (&mask) != ',') |
19424 | { | |
1661c76c | 19425 | as_warn (_("bad .mask/.fmask directive")); |
ecb4347a DJ |
19426 | --input_line_pointer; |
19427 | demand_empty_rest_of_line (); | |
19428 | return; | |
19429 | } | |
252b5132 | 19430 | |
ecb4347a DJ |
19431 | off = get_absolute_expression (); |
19432 | ||
19433 | if (reg_type == 'F') | |
19434 | { | |
19435 | cur_proc_ptr->fpreg_mask = mask; | |
19436 | cur_proc_ptr->fpreg_offset = off; | |
19437 | } | |
19438 | else | |
19439 | { | |
19440 | cur_proc_ptr->reg_mask = mask; | |
19441 | cur_proc_ptr->reg_offset = off; | |
19442 | } | |
19443 | ||
19444 | demand_empty_rest_of_line (); | |
252b5132 | 19445 | } |
252b5132 RH |
19446 | } |
19447 | ||
316f5878 RS |
19448 | /* A table describing all the processors gas knows about. Names are |
19449 | matched in the order listed. | |
e7af610e | 19450 | |
316f5878 RS |
19451 | To ease comparison, please keep this table in the same order as |
19452 | gcc's mips_cpu_info_table[]. */ | |
e972090a NC |
19453 | static const struct mips_cpu_info mips_cpu_info_table[] = |
19454 | { | |
316f5878 | 19455 | /* Entries for generic ISAs */ |
d16afab6 RS |
19456 | { "mips1", MIPS_CPU_IS_ISA, 0, ISA_MIPS1, CPU_R3000 }, |
19457 | { "mips2", MIPS_CPU_IS_ISA, 0, ISA_MIPS2, CPU_R6000 }, | |
19458 | { "mips3", MIPS_CPU_IS_ISA, 0, ISA_MIPS3, CPU_R4000 }, | |
19459 | { "mips4", MIPS_CPU_IS_ISA, 0, ISA_MIPS4, CPU_R8000 }, | |
19460 | { "mips5", MIPS_CPU_IS_ISA, 0, ISA_MIPS5, CPU_MIPS5 }, | |
19461 | { "mips32", MIPS_CPU_IS_ISA, 0, ISA_MIPS32, CPU_MIPS32 }, | |
19462 | { "mips32r2", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
ae52f483 AB |
19463 | { "mips32r3", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R3, CPU_MIPS32R3 }, |
19464 | { "mips32r5", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R5, CPU_MIPS32R5 }, | |
7361da2c | 19465 | { "mips32r6", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R6, CPU_MIPS32R6 }, |
d16afab6 RS |
19466 | { "mips64", MIPS_CPU_IS_ISA, 0, ISA_MIPS64, CPU_MIPS64 }, |
19467 | { "mips64r2", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R2, CPU_MIPS64R2 }, | |
ae52f483 AB |
19468 | { "mips64r3", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R3, CPU_MIPS64R3 }, |
19469 | { "mips64r5", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R5, CPU_MIPS64R5 }, | |
7361da2c | 19470 | { "mips64r6", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R6, CPU_MIPS64R6 }, |
316f5878 RS |
19471 | |
19472 | /* MIPS I */ | |
d16afab6 RS |
19473 | { "r3000", 0, 0, ISA_MIPS1, CPU_R3000 }, |
19474 | { "r2000", 0, 0, ISA_MIPS1, CPU_R3000 }, | |
19475 | { "r3900", 0, 0, ISA_MIPS1, CPU_R3900 }, | |
316f5878 RS |
19476 | |
19477 | /* MIPS II */ | |
d16afab6 | 19478 | { "r6000", 0, 0, ISA_MIPS2, CPU_R6000 }, |
316f5878 RS |
19479 | |
19480 | /* MIPS III */ | |
d16afab6 RS |
19481 | { "r4000", 0, 0, ISA_MIPS3, CPU_R4000 }, |
19482 | { "r4010", 0, 0, ISA_MIPS2, CPU_R4010 }, | |
19483 | { "vr4100", 0, 0, ISA_MIPS3, CPU_VR4100 }, | |
19484 | { "vr4111", 0, 0, ISA_MIPS3, CPU_R4111 }, | |
19485 | { "vr4120", 0, 0, ISA_MIPS3, CPU_VR4120 }, | |
19486 | { "vr4130", 0, 0, ISA_MIPS3, CPU_VR4120 }, | |
19487 | { "vr4181", 0, 0, ISA_MIPS3, CPU_R4111 }, | |
19488 | { "vr4300", 0, 0, ISA_MIPS3, CPU_R4300 }, | |
19489 | { "r4400", 0, 0, ISA_MIPS3, CPU_R4400 }, | |
19490 | { "r4600", 0, 0, ISA_MIPS3, CPU_R4600 }, | |
19491 | { "orion", 0, 0, ISA_MIPS3, CPU_R4600 }, | |
19492 | { "r4650", 0, 0, ISA_MIPS3, CPU_R4650 }, | |
19493 | { "r5900", 0, 0, ISA_MIPS3, CPU_R5900 }, | |
b15591bb | 19494 | /* ST Microelectronics Loongson 2E and 2F cores */ |
d16afab6 RS |
19495 | { "loongson2e", 0, 0, ISA_MIPS3, CPU_LOONGSON_2E }, |
19496 | { "loongson2f", 0, 0, ISA_MIPS3, CPU_LOONGSON_2F }, | |
316f5878 RS |
19497 | |
19498 | /* MIPS IV */ | |
d16afab6 RS |
19499 | { "r8000", 0, 0, ISA_MIPS4, CPU_R8000 }, |
19500 | { "r10000", 0, 0, ISA_MIPS4, CPU_R10000 }, | |
19501 | { "r12000", 0, 0, ISA_MIPS4, CPU_R12000 }, | |
19502 | { "r14000", 0, 0, ISA_MIPS4, CPU_R14000 }, | |
19503 | { "r16000", 0, 0, ISA_MIPS4, CPU_R16000 }, | |
19504 | { "vr5000", 0, 0, ISA_MIPS4, CPU_R5000 }, | |
19505 | { "vr5400", 0, 0, ISA_MIPS4, CPU_VR5400 }, | |
19506 | { "vr5500", 0, 0, ISA_MIPS4, CPU_VR5500 }, | |
19507 | { "rm5200", 0, 0, ISA_MIPS4, CPU_R5000 }, | |
19508 | { "rm5230", 0, 0, ISA_MIPS4, CPU_R5000 }, | |
19509 | { "rm5231", 0, 0, ISA_MIPS4, CPU_R5000 }, | |
19510 | { "rm5261", 0, 0, ISA_MIPS4, CPU_R5000 }, | |
19511 | { "rm5721", 0, 0, ISA_MIPS4, CPU_R5000 }, | |
19512 | { "rm7000", 0, 0, ISA_MIPS4, CPU_RM7000 }, | |
19513 | { "rm9000", 0, 0, ISA_MIPS4, CPU_RM9000 }, | |
316f5878 RS |
19514 | |
19515 | /* MIPS 32 */ | |
d16afab6 RS |
19516 | { "4kc", 0, 0, ISA_MIPS32, CPU_MIPS32 }, |
19517 | { "4km", 0, 0, ISA_MIPS32, CPU_MIPS32 }, | |
19518 | { "4kp", 0, 0, ISA_MIPS32, CPU_MIPS32 }, | |
19519 | { "4ksc", 0, ASE_SMARTMIPS, ISA_MIPS32, CPU_MIPS32 }, | |
ad3fea08 TS |
19520 | |
19521 | /* MIPS 32 Release 2 */ | |
d16afab6 RS |
19522 | { "4kec", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
19523 | { "4kem", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19524 | { "4kep", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19525 | { "4ksd", 0, ASE_SMARTMIPS, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19526 | { "m4k", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19527 | { "m4kp", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19528 | { "m14k", 0, ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19529 | { "m14kc", 0, ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19530 | { "m14ke", 0, ASE_DSP | ASE_DSPR2 | ASE_MCU, | |
19531 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19532 | { "m14kec", 0, ASE_DSP | ASE_DSPR2 | ASE_MCU, | |
19533 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19534 | { "24kc", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19535 | { "24kf2_1", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19536 | { "24kf", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19537 | { "24kf1_1", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 | 19538 | /* Deprecated forms of the above. */ |
d16afab6 RS |
19539 | { "24kfx", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
19540 | { "24kx", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
01fd108f | 19541 | /* 24KE is a 24K with DSP ASE, other ASEs are optional. */ |
d16afab6 RS |
19542 | { "24kec", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
19543 | { "24kef2_1", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19544 | { "24kef", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19545 | { "24kef1_1", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 | 19546 | /* Deprecated forms of the above. */ |
d16afab6 RS |
19547 | { "24kefx", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
19548 | { "24kex", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
01fd108f | 19549 | /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */ |
d16afab6 RS |
19550 | { "34kc", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, |
19551 | { "34kf2_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19552 | { "34kf", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19553 | { "34kf1_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 | 19554 | /* Deprecated forms of the above. */ |
d16afab6 RS |
19555 | { "34kfx", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, |
19556 | { "34kx", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
711eefe4 | 19557 | /* 34Kn is a 34kc without DSP. */ |
d16afab6 | 19558 | { "34kn", 0, ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, |
01fd108f | 19559 | /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */ |
d16afab6 RS |
19560 | { "74kc", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, |
19561 | { "74kf2_1", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19562 | { "74kf", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19563 | { "74kf1_1", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19564 | { "74kf3_2", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 | 19565 | /* Deprecated forms of the above. */ |
d16afab6 RS |
19566 | { "74kfx", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, |
19567 | { "74kx", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
30f8113a | 19568 | /* 1004K cores are multiprocessor versions of the 34K. */ |
d16afab6 RS |
19569 | { "1004kc", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, |
19570 | { "1004kf2_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19571 | { "1004kf", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19572 | { "1004kf1_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
77403ce9 RS |
19573 | /* interaptiv is the new name for 1004kf */ |
19574 | { "interaptiv", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
c6e5c03a RS |
19575 | /* M5100 family */ |
19576 | { "m5100", 0, ASE_MCU, ISA_MIPS32R5, CPU_MIPS32R5 }, | |
19577 | { "m5101", 0, ASE_MCU, ISA_MIPS32R5, CPU_MIPS32R5 }, | |
bbaa46c0 | 19578 | /* P5600 with EVA and Virtualization ASEs, other ASEs are optional. */ |
134c0c8b | 19579 | { "p5600", 0, ASE_VIRT | ASE_EVA | ASE_XPA, ISA_MIPS32R5, CPU_MIPS32R5 }, |
32b26a03 | 19580 | |
316f5878 | 19581 | /* MIPS 64 */ |
d16afab6 RS |
19582 | { "5kc", 0, 0, ISA_MIPS64, CPU_MIPS64 }, |
19583 | { "5kf", 0, 0, ISA_MIPS64, CPU_MIPS64 }, | |
19584 | { "20kc", 0, ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 }, | |
19585 | { "25kf", 0, ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 }, | |
ad3fea08 | 19586 | |
c7a23324 | 19587 | /* Broadcom SB-1 CPU core */ |
d16afab6 | 19588 | { "sb1", 0, ASE_MIPS3D | ASE_MDMX, ISA_MIPS64, CPU_SB1 }, |
1e85aad8 | 19589 | /* Broadcom SB-1A CPU core */ |
d16afab6 | 19590 | { "sb1a", 0, ASE_MIPS3D | ASE_MDMX, ISA_MIPS64, CPU_SB1 }, |
3739860c | 19591 | |
4ba154f5 | 19592 | { "loongson3a", 0, 0, ISA_MIPS64R2, CPU_LOONGSON_3A }, |
e7af610e | 19593 | |
ed163775 MR |
19594 | /* MIPS 64 Release 2 */ |
19595 | ||
967344c6 | 19596 | /* Cavium Networks Octeon CPU core */ |
d16afab6 RS |
19597 | { "octeon", 0, 0, ISA_MIPS64R2, CPU_OCTEON }, |
19598 | { "octeon+", 0, 0, ISA_MIPS64R2, CPU_OCTEONP }, | |
19599 | { "octeon2", 0, 0, ISA_MIPS64R2, CPU_OCTEON2 }, | |
2c629856 | 19600 | { "octeon3", 0, ASE_VIRT | ASE_VIRT64, ISA_MIPS64R5, CPU_OCTEON3 }, |
967344c6 | 19601 | |
52b6b6b9 | 19602 | /* RMI Xlr */ |
d16afab6 | 19603 | { "xlr", 0, 0, ISA_MIPS64, CPU_XLR }, |
52b6b6b9 | 19604 | |
55a36193 MK |
19605 | /* Broadcom XLP. |
19606 | XLP is mostly like XLR, with the prominent exception that it is | |
19607 | MIPS64R2 rather than MIPS64. */ | |
d16afab6 | 19608 | { "xlp", 0, 0, ISA_MIPS64R2, CPU_XLR }, |
55a36193 | 19609 | |
a4968f42 | 19610 | /* MIPS 64 Release 6 */ |
7ef0d297 | 19611 | { "i6400", 0, ASE_MSA, ISA_MIPS64R6, CPU_MIPS64R6}, |
a4968f42 | 19612 | { "p6600", 0, ASE_VIRT | ASE_MSA, ISA_MIPS64R6, CPU_MIPS64R6}, |
7ef0d297 | 19613 | |
316f5878 | 19614 | /* End marker */ |
d16afab6 | 19615 | { NULL, 0, 0, 0, 0 } |
316f5878 | 19616 | }; |
e7af610e | 19617 | |
84ea6cf2 | 19618 | |
316f5878 RS |
19619 | /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL |
19620 | with a final "000" replaced by "k". Ignore case. | |
e7af610e | 19621 | |
316f5878 | 19622 | Note: this function is shared between GCC and GAS. */ |
c6c98b38 | 19623 | |
b34976b6 | 19624 | static bfd_boolean |
17a2f251 | 19625 | mips_strict_matching_cpu_name_p (const char *canonical, const char *given) |
316f5878 RS |
19626 | { |
19627 | while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical)) | |
19628 | given++, canonical++; | |
19629 | ||
19630 | return ((*given == 0 && *canonical == 0) | |
19631 | || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0)); | |
19632 | } | |
19633 | ||
19634 | ||
19635 | /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied | |
19636 | CPU name. We've traditionally allowed a lot of variation here. | |
19637 | ||
19638 | Note: this function is shared between GCC and GAS. */ | |
19639 | ||
b34976b6 | 19640 | static bfd_boolean |
17a2f251 | 19641 | mips_matching_cpu_name_p (const char *canonical, const char *given) |
316f5878 RS |
19642 | { |
19643 | /* First see if the name matches exactly, or with a final "000" | |
19644 | turned into "k". */ | |
19645 | if (mips_strict_matching_cpu_name_p (canonical, given)) | |
b34976b6 | 19646 | return TRUE; |
316f5878 RS |
19647 | |
19648 | /* If not, try comparing based on numerical designation alone. | |
19649 | See if GIVEN is an unadorned number, or 'r' followed by a number. */ | |
19650 | if (TOLOWER (*given) == 'r') | |
19651 | given++; | |
19652 | if (!ISDIGIT (*given)) | |
b34976b6 | 19653 | return FALSE; |
316f5878 RS |
19654 | |
19655 | /* Skip over some well-known prefixes in the canonical name, | |
19656 | hoping to find a number there too. */ | |
19657 | if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r') | |
19658 | canonical += 2; | |
19659 | else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm') | |
19660 | canonical += 2; | |
19661 | else if (TOLOWER (canonical[0]) == 'r') | |
19662 | canonical += 1; | |
19663 | ||
19664 | return mips_strict_matching_cpu_name_p (canonical, given); | |
19665 | } | |
19666 | ||
19667 | ||
19668 | /* Parse an option that takes the name of a processor as its argument. | |
19669 | OPTION is the name of the option and CPU_STRING is the argument. | |
19670 | Return the corresponding processor enumeration if the CPU_STRING is | |
19671 | recognized, otherwise report an error and return null. | |
19672 | ||
19673 | A similar function exists in GCC. */ | |
e7af610e NC |
19674 | |
19675 | static const struct mips_cpu_info * | |
17a2f251 | 19676 | mips_parse_cpu (const char *option, const char *cpu_string) |
e7af610e | 19677 | { |
316f5878 | 19678 | const struct mips_cpu_info *p; |
e7af610e | 19679 | |
316f5878 RS |
19680 | /* 'from-abi' selects the most compatible architecture for the given |
19681 | ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the | |
19682 | EABIs, we have to decide whether we're using the 32-bit or 64-bit | |
19683 | version. Look first at the -mgp options, if given, otherwise base | |
19684 | the choice on MIPS_DEFAULT_64BIT. | |
e7af610e | 19685 | |
316f5878 RS |
19686 | Treat NO_ABI like the EABIs. One reason to do this is that the |
19687 | plain 'mips' and 'mips64' configs have 'from-abi' as their default | |
19688 | architecture. This code picks MIPS I for 'mips' and MIPS III for | |
19689 | 'mips64', just as we did in the days before 'from-abi'. */ | |
19690 | if (strcasecmp (cpu_string, "from-abi") == 0) | |
19691 | { | |
19692 | if (ABI_NEEDS_32BIT_REGS (mips_abi)) | |
19693 | return mips_cpu_info_from_isa (ISA_MIPS1); | |
19694 | ||
19695 | if (ABI_NEEDS_64BIT_REGS (mips_abi)) | |
19696 | return mips_cpu_info_from_isa (ISA_MIPS3); | |
19697 | ||
bad1aba3 | 19698 | if (file_mips_opts.gp >= 0) |
19699 | return mips_cpu_info_from_isa (file_mips_opts.gp == 32 | |
0b35dfee | 19700 | ? ISA_MIPS1 : ISA_MIPS3); |
316f5878 RS |
19701 | |
19702 | return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT | |
19703 | ? ISA_MIPS3 | |
19704 | : ISA_MIPS1); | |
19705 | } | |
19706 | ||
19707 | /* 'default' has traditionally been a no-op. Probably not very useful. */ | |
19708 | if (strcasecmp (cpu_string, "default") == 0) | |
19709 | return 0; | |
19710 | ||
19711 | for (p = mips_cpu_info_table; p->name != 0; p++) | |
19712 | if (mips_matching_cpu_name_p (p->name, cpu_string)) | |
19713 | return p; | |
19714 | ||
1661c76c | 19715 | as_bad (_("bad value (%s) for %s"), cpu_string, option); |
316f5878 | 19716 | return 0; |
e7af610e NC |
19717 | } |
19718 | ||
316f5878 RS |
19719 | /* Return the canonical processor information for ISA (a member of the |
19720 | ISA_MIPS* enumeration). */ | |
19721 | ||
e7af610e | 19722 | static const struct mips_cpu_info * |
17a2f251 | 19723 | mips_cpu_info_from_isa (int isa) |
e7af610e NC |
19724 | { |
19725 | int i; | |
19726 | ||
19727 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
ad3fea08 | 19728 | if ((mips_cpu_info_table[i].flags & MIPS_CPU_IS_ISA) |
316f5878 | 19729 | && isa == mips_cpu_info_table[i].isa) |
e7af610e NC |
19730 | return (&mips_cpu_info_table[i]); |
19731 | ||
e972090a | 19732 | return NULL; |
e7af610e | 19733 | } |
fef14a42 TS |
19734 | |
19735 | static const struct mips_cpu_info * | |
17a2f251 | 19736 | mips_cpu_info_from_arch (int arch) |
fef14a42 TS |
19737 | { |
19738 | int i; | |
19739 | ||
19740 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
19741 | if (arch == mips_cpu_info_table[i].cpu) | |
19742 | return (&mips_cpu_info_table[i]); | |
19743 | ||
19744 | return NULL; | |
19745 | } | |
316f5878 RS |
19746 | \f |
19747 | static void | |
17a2f251 | 19748 | show (FILE *stream, const char *string, int *col_p, int *first_p) |
316f5878 RS |
19749 | { |
19750 | if (*first_p) | |
19751 | { | |
19752 | fprintf (stream, "%24s", ""); | |
19753 | *col_p = 24; | |
19754 | } | |
19755 | else | |
19756 | { | |
19757 | fprintf (stream, ", "); | |
19758 | *col_p += 2; | |
19759 | } | |
e7af610e | 19760 | |
316f5878 RS |
19761 | if (*col_p + strlen (string) > 72) |
19762 | { | |
19763 | fprintf (stream, "\n%24s", ""); | |
19764 | *col_p = 24; | |
19765 | } | |
19766 | ||
19767 | fprintf (stream, "%s", string); | |
19768 | *col_p += strlen (string); | |
19769 | ||
19770 | *first_p = 0; | |
19771 | } | |
19772 | ||
19773 | void | |
17a2f251 | 19774 | md_show_usage (FILE *stream) |
e7af610e | 19775 | { |
316f5878 RS |
19776 | int column, first; |
19777 | size_t i; | |
19778 | ||
19779 | fprintf (stream, _("\ | |
19780 | MIPS options:\n\ | |
316f5878 RS |
19781 | -EB generate big endian output\n\ |
19782 | -EL generate little endian output\n\ | |
19783 | -g, -g2 do not remove unneeded NOPs or swap branches\n\ | |
19784 | -G NUM allow referencing objects up to NUM bytes\n\ | |
19785 | implicitly with the gp register [default 8]\n")); | |
19786 | fprintf (stream, _("\ | |
19787 | -mips1 generate MIPS ISA I instructions\n\ | |
19788 | -mips2 generate MIPS ISA II instructions\n\ | |
19789 | -mips3 generate MIPS ISA III instructions\n\ | |
19790 | -mips4 generate MIPS ISA IV instructions\n\ | |
19791 | -mips5 generate MIPS ISA V instructions\n\ | |
19792 | -mips32 generate MIPS32 ISA instructions\n\ | |
af7ee8bf | 19793 | -mips32r2 generate MIPS32 release 2 ISA instructions\n\ |
ae52f483 AB |
19794 | -mips32r3 generate MIPS32 release 3 ISA instructions\n\ |
19795 | -mips32r5 generate MIPS32 release 5 ISA instructions\n\ | |
7361da2c | 19796 | -mips32r6 generate MIPS32 release 6 ISA instructions\n\ |
316f5878 | 19797 | -mips64 generate MIPS64 ISA instructions\n\ |
5f74bc13 | 19798 | -mips64r2 generate MIPS64 release 2 ISA instructions\n\ |
ae52f483 AB |
19799 | -mips64r3 generate MIPS64 release 3 ISA instructions\n\ |
19800 | -mips64r5 generate MIPS64 release 5 ISA instructions\n\ | |
7361da2c | 19801 | -mips64r6 generate MIPS64 release 6 ISA instructions\n\ |
316f5878 RS |
19802 | -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n")); |
19803 | ||
19804 | first = 1; | |
e7af610e NC |
19805 | |
19806 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
316f5878 RS |
19807 | show (stream, mips_cpu_info_table[i].name, &column, &first); |
19808 | show (stream, "from-abi", &column, &first); | |
19809 | fputc ('\n', stream); | |
e7af610e | 19810 | |
316f5878 RS |
19811 | fprintf (stream, _("\ |
19812 | -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\ | |
19813 | -no-mCPU don't generate code specific to CPU.\n\ | |
19814 | For -mCPU and -no-mCPU, CPU must be one of:\n")); | |
19815 | ||
19816 | first = 1; | |
19817 | ||
19818 | show (stream, "3900", &column, &first); | |
19819 | show (stream, "4010", &column, &first); | |
19820 | show (stream, "4100", &column, &first); | |
19821 | show (stream, "4650", &column, &first); | |
19822 | fputc ('\n', stream); | |
19823 | ||
19824 | fprintf (stream, _("\ | |
19825 | -mips16 generate mips16 instructions\n\ | |
19826 | -no-mips16 do not generate mips16 instructions\n")); | |
19827 | fprintf (stream, _("\ | |
df58fc94 RS |
19828 | -mmicromips generate microMIPS instructions\n\ |
19829 | -mno-micromips do not generate microMIPS instructions\n")); | |
19830 | fprintf (stream, _("\ | |
e16bfa71 | 19831 | -msmartmips generate smartmips instructions\n\ |
3739860c | 19832 | -mno-smartmips do not generate smartmips instructions\n")); |
e16bfa71 | 19833 | fprintf (stream, _("\ |
74cd071d CF |
19834 | -mdsp generate DSP instructions\n\ |
19835 | -mno-dsp do not generate DSP instructions\n")); | |
19836 | fprintf (stream, _("\ | |
8b082fb1 TS |
19837 | -mdspr2 generate DSP R2 instructions\n\ |
19838 | -mno-dspr2 do not generate DSP R2 instructions\n")); | |
19839 | fprintf (stream, _("\ | |
8f4f9071 MF |
19840 | -mdspr3 generate DSP R3 instructions\n\ |
19841 | -mno-dspr3 do not generate DSP R3 instructions\n")); | |
19842 | fprintf (stream, _("\ | |
ef2e4d86 CF |
19843 | -mmt generate MT instructions\n\ |
19844 | -mno-mt do not generate MT instructions\n")); | |
19845 | fprintf (stream, _("\ | |
dec0624d MR |
19846 | -mmcu generate MCU instructions\n\ |
19847 | -mno-mcu do not generate MCU instructions\n")); | |
19848 | fprintf (stream, _("\ | |
56d438b1 CF |
19849 | -mmsa generate MSA instructions\n\ |
19850 | -mno-msa do not generate MSA instructions\n")); | |
19851 | fprintf (stream, _("\ | |
7d64c587 AB |
19852 | -mxpa generate eXtended Physical Address (XPA) instructions\n\ |
19853 | -mno-xpa do not generate eXtended Physical Address (XPA) instructions\n")); | |
19854 | fprintf (stream, _("\ | |
b015e599 AP |
19855 | -mvirt generate Virtualization instructions\n\ |
19856 | -mno-virt do not generate Virtualization instructions\n")); | |
19857 | fprintf (stream, _("\ | |
833794fc MR |
19858 | -minsn32 only generate 32-bit microMIPS instructions\n\ |
19859 | -mno-insn32 generate all microMIPS instructions\n")); | |
19860 | fprintf (stream, _("\ | |
c67a084a NC |
19861 | -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\ |
19862 | -mfix-loongson2f-nop work around Loongson2F NOP errata\n\ | |
d766e8ec | 19863 | -mfix-vr4120 work around certain VR4120 errata\n\ |
7d8e00cf | 19864 | -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\ |
6a32d874 | 19865 | -mfix-24k insert a nop after ERET and DERET instructions\n\ |
d954098f | 19866 | -mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\ |
316f5878 RS |
19867 | -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\ |
19868 | -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\ | |
aed1a261 | 19869 | -msym32 assume all symbols have 32-bit values\n\ |
316f5878 RS |
19870 | -O0 remove unneeded NOPs, do not swap branches\n\ |
19871 | -O remove unneeded NOPs and swap branches\n\ | |
316f5878 RS |
19872 | --trap, --no-break trap exception on div by 0 and mult overflow\n\ |
19873 | --break, --no-trap break exception on div by 0 and mult overflow\n")); | |
037b32b9 AN |
19874 | fprintf (stream, _("\ |
19875 | -mhard-float allow floating-point instructions\n\ | |
19876 | -msoft-float do not allow floating-point instructions\n\ | |
19877 | -msingle-float only allow 32-bit floating-point operations\n\ | |
19878 | -mdouble-float allow 32-bit and 64-bit floating-point operations\n\ | |
3bf0dbfb | 19879 | --[no-]construct-floats [dis]allow floating point values to be constructed\n\ |
ba92f887 | 19880 | --[no-]relax-branch [dis]allow out-of-range branches to be relaxed\n\ |
8b10b0b3 MR |
19881 | -mignore-branch-isa accept invalid branches requiring an ISA mode switch\n\ |
19882 | -mno-ignore-branch-isa reject invalid branches requiring an ISA mode switch\n\ | |
ba92f887 MR |
19883 | -mnan=ENCODING select an IEEE 754 NaN encoding convention, either of:\n")); |
19884 | ||
19885 | first = 1; | |
19886 | ||
19887 | show (stream, "legacy", &column, &first); | |
19888 | show (stream, "2008", &column, &first); | |
19889 | ||
19890 | fputc ('\n', stream); | |
19891 | ||
316f5878 RS |
19892 | fprintf (stream, _("\ |
19893 | -KPIC, -call_shared generate SVR4 position independent code\n\ | |
861fb55a | 19894 | -call_nonpic generate non-PIC code that can operate with DSOs\n\ |
0c000745 | 19895 | -mvxworks-pic generate VxWorks position independent code\n\ |
861fb55a | 19896 | -non_shared do not generate code that can operate with DSOs\n\ |
316f5878 | 19897 | -xgot assume a 32 bit GOT\n\ |
dcd410fe | 19898 | -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\ |
bbe506e8 | 19899 | -mshared, -mno-shared disable/enable .cpload optimization for\n\ |
d821e36b | 19900 | position dependent (non shared) code\n\ |
316f5878 RS |
19901 | -mabi=ABI create ABI conformant object file for:\n")); |
19902 | ||
19903 | first = 1; | |
19904 | ||
19905 | show (stream, "32", &column, &first); | |
19906 | show (stream, "o64", &column, &first); | |
19907 | show (stream, "n32", &column, &first); | |
19908 | show (stream, "64", &column, &first); | |
19909 | show (stream, "eabi", &column, &first); | |
19910 | ||
19911 | fputc ('\n', stream); | |
19912 | ||
19913 | fprintf (stream, _("\ | |
19914 | -32 create o32 ABI object file (default)\n\ | |
19915 | -n32 create n32 ABI object file\n\ | |
19916 | -64 create 64 ABI object file\n")); | |
e7af610e | 19917 | } |
14e777e0 | 19918 | |
1575952e | 19919 | #ifdef TE_IRIX |
14e777e0 | 19920 | enum dwarf2_format |
413a266c | 19921 | mips_dwarf2_format (asection *sec ATTRIBUTE_UNUSED) |
14e777e0 | 19922 | { |
369943fe | 19923 | if (HAVE_64BIT_SYMBOLS) |
1575952e | 19924 | return dwarf2_format_64bit_irix; |
14e777e0 KB |
19925 | else |
19926 | return dwarf2_format_32bit; | |
19927 | } | |
1575952e | 19928 | #endif |
73369e65 EC |
19929 | |
19930 | int | |
19931 | mips_dwarf2_addr_size (void) | |
19932 | { | |
6b6b3450 | 19933 | if (HAVE_64BIT_OBJECTS) |
73369e65 | 19934 | return 8; |
73369e65 EC |
19935 | else |
19936 | return 4; | |
19937 | } | |
5862107c EC |
19938 | |
19939 | /* Standard calling conventions leave the CFA at SP on entry. */ | |
19940 | void | |
19941 | mips_cfi_frame_initial_instructions (void) | |
19942 | { | |
19943 | cfi_add_CFA_def_cfa_register (SP); | |
19944 | } | |
19945 | ||
707bfff6 TS |
19946 | int |
19947 | tc_mips_regname_to_dw2regnum (char *regname) | |
19948 | { | |
19949 | unsigned int regnum = -1; | |
19950 | unsigned int reg; | |
19951 | ||
19952 | if (reg_lookup (®name, RTYPE_GP | RTYPE_NUM, ®)) | |
19953 | regnum = reg; | |
19954 | ||
19955 | return regnum; | |
19956 | } | |
263b2574 | 19957 | |
19958 | /* Implement CONVERT_SYMBOLIC_ATTRIBUTE. | |
19959 | Given a symbolic attribute NAME, return the proper integer value. | |
19960 | Returns -1 if the attribute is not known. */ | |
19961 | ||
19962 | int | |
19963 | mips_convert_symbolic_attribute (const char *name) | |
19964 | { | |
19965 | static const struct | |
19966 | { | |
19967 | const char * name; | |
19968 | const int tag; | |
19969 | } | |
19970 | attribute_table[] = | |
19971 | { | |
19972 | #define T(tag) {#tag, tag} | |
19973 | T (Tag_GNU_MIPS_ABI_FP), | |
19974 | T (Tag_GNU_MIPS_ABI_MSA), | |
19975 | #undef T | |
19976 | }; | |
19977 | unsigned int i; | |
19978 | ||
19979 | if (name == NULL) | |
19980 | return -1; | |
19981 | ||
19982 | for (i = 0; i < ARRAY_SIZE (attribute_table); i++) | |
19983 | if (streq (name, attribute_table[i].name)) | |
19984 | return attribute_table[i].tag; | |
19985 | ||
19986 | return -1; | |
19987 | } | |
fd5c94ab RS |
19988 | |
19989 | void | |
19990 | md_mips_end (void) | |
19991 | { | |
351cdf24 MF |
19992 | int fpabi = Val_GNU_MIPS_ABI_FP_ANY; |
19993 | ||
fd5c94ab RS |
19994 | mips_emit_delays (); |
19995 | if (cur_proc_ptr) | |
19996 | as_warn (_("missing .end at end of assembly")); | |
919731af | 19997 | |
19998 | /* Just in case no code was emitted, do the consistency check. */ | |
19999 | file_mips_check_options (); | |
351cdf24 MF |
20000 | |
20001 | /* Set a floating-point ABI if the user did not. */ | |
20002 | if (obj_elf_seen_attribute (OBJ_ATTR_GNU, Tag_GNU_MIPS_ABI_FP)) | |
20003 | { | |
20004 | /* Perform consistency checks on the floating-point ABI. */ | |
20005 | fpabi = bfd_elf_get_obj_attr_int (stdoutput, OBJ_ATTR_GNU, | |
20006 | Tag_GNU_MIPS_ABI_FP); | |
20007 | if (fpabi != Val_GNU_MIPS_ABI_FP_ANY) | |
20008 | check_fpabi (fpabi); | |
20009 | } | |
20010 | else | |
20011 | { | |
20012 | /* Soft-float gets precedence over single-float, the two options should | |
20013 | not be used together so this should not matter. */ | |
20014 | if (file_mips_opts.soft_float == 1) | |
20015 | fpabi = Val_GNU_MIPS_ABI_FP_SOFT; | |
20016 | /* Single-float gets precedence over all double_float cases. */ | |
20017 | else if (file_mips_opts.single_float == 1) | |
20018 | fpabi = Val_GNU_MIPS_ABI_FP_SINGLE; | |
20019 | else | |
20020 | { | |
20021 | switch (file_mips_opts.fp) | |
20022 | { | |
20023 | case 32: | |
20024 | if (file_mips_opts.gp == 32) | |
20025 | fpabi = Val_GNU_MIPS_ABI_FP_DOUBLE; | |
20026 | break; | |
20027 | case 0: | |
20028 | fpabi = Val_GNU_MIPS_ABI_FP_XX; | |
20029 | break; | |
20030 | case 64: | |
20031 | if (file_mips_opts.gp == 32 && !file_mips_opts.oddspreg) | |
20032 | fpabi = Val_GNU_MIPS_ABI_FP_64A; | |
20033 | else if (file_mips_opts.gp == 32) | |
20034 | fpabi = Val_GNU_MIPS_ABI_FP_64; | |
20035 | else | |
20036 | fpabi = Val_GNU_MIPS_ABI_FP_DOUBLE; | |
20037 | break; | |
20038 | } | |
20039 | } | |
20040 | ||
20041 | bfd_elf_add_obj_attr_int (stdoutput, OBJ_ATTR_GNU, | |
20042 | Tag_GNU_MIPS_ABI_FP, fpabi); | |
20043 | } | |
fd5c94ab | 20044 | } |
2f0c68f2 CM |
20045 | |
20046 | /* Returns the relocation type required for a particular CFI encoding. */ | |
20047 | ||
20048 | bfd_reloc_code_real_type | |
20049 | mips_cfi_reloc_for_encoding (int encoding) | |
20050 | { | |
20051 | if (encoding == (DW_EH_PE_sdata4 | DW_EH_PE_pcrel)) | |
20052 | return BFD_RELOC_32_PCREL; | |
20053 | else return BFD_RELOC_NONE; | |
20054 | } |