Commit | Line | Data |
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252b5132 | 1 | /* tc-mips.c -- assemble code for a MIPS chip. |
81912461 | 2 | Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, |
c67a084a NC |
3 | 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010 |
4 | Free Software Foundation, Inc. | |
252b5132 RH |
5 | Contributed by the OSF and Ralph Campbell. |
6 | Written by Keith Knowles and Ralph Campbell, working independently. | |
7 | Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus | |
8 | Support. | |
9 | ||
10 | This file is part of GAS. | |
11 | ||
12 | GAS is free software; you can redistribute it and/or modify | |
13 | it under the terms of the GNU General Public License as published by | |
ec2655a6 | 14 | the Free Software Foundation; either version 3, or (at your option) |
252b5132 RH |
15 | any later version. |
16 | ||
17 | GAS is distributed in the hope that it will be useful, | |
18 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | GNU General Public License for more details. | |
21 | ||
22 | You should have received a copy of the GNU General Public License | |
23 | along with GAS; see the file COPYING. If not, write to the Free | |
4b4da160 NC |
24 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
25 | 02110-1301, USA. */ | |
252b5132 RH |
26 | |
27 | #include "as.h" | |
28 | #include "config.h" | |
29 | #include "subsegs.h" | |
3882b010 | 30 | #include "safe-ctype.h" |
252b5132 | 31 | |
252b5132 RH |
32 | #include "opcode/mips.h" |
33 | #include "itbl-ops.h" | |
c5dd6aab | 34 | #include "dwarf2dbg.h" |
5862107c | 35 | #include "dw2gencfi.h" |
252b5132 RH |
36 | |
37 | #ifdef DEBUG | |
38 | #define DBG(x) printf x | |
39 | #else | |
40 | #define DBG(x) | |
41 | #endif | |
42 | ||
43 | #ifdef OBJ_MAYBE_ELF | |
44 | /* Clean up namespace so we can include obj-elf.h too. */ | |
17a2f251 TS |
45 | static int mips_output_flavor (void); |
46 | static int mips_output_flavor (void) { return OUTPUT_FLAVOR; } | |
252b5132 RH |
47 | #undef OBJ_PROCESS_STAB |
48 | #undef OUTPUT_FLAVOR | |
49 | #undef S_GET_ALIGN | |
50 | #undef S_GET_SIZE | |
51 | #undef S_SET_ALIGN | |
52 | #undef S_SET_SIZE | |
252b5132 RH |
53 | #undef obj_frob_file |
54 | #undef obj_frob_file_after_relocs | |
55 | #undef obj_frob_symbol | |
56 | #undef obj_pop_insert | |
57 | #undef obj_sec_sym_ok_for_reloc | |
58 | #undef OBJ_COPY_SYMBOL_ATTRIBUTES | |
59 | ||
60 | #include "obj-elf.h" | |
61 | /* Fix any of them that we actually care about. */ | |
62 | #undef OUTPUT_FLAVOR | |
63 | #define OUTPUT_FLAVOR mips_output_flavor() | |
64 | #endif | |
65 | ||
66 | #if defined (OBJ_ELF) | |
67 | #include "elf/mips.h" | |
68 | #endif | |
69 | ||
70 | #ifndef ECOFF_DEBUGGING | |
71 | #define NO_ECOFF_DEBUGGING | |
72 | #define ECOFF_DEBUGGING 0 | |
73 | #endif | |
74 | ||
ecb4347a DJ |
75 | int mips_flag_mdebug = -1; |
76 | ||
dcd410fe RO |
77 | /* Control generation of .pdr sections. Off by default on IRIX: the native |
78 | linker doesn't know about and discards them, but relocations against them | |
79 | remain, leading to rld crashes. */ | |
80 | #ifdef TE_IRIX | |
81 | int mips_flag_pdr = FALSE; | |
82 | #else | |
83 | int mips_flag_pdr = TRUE; | |
84 | #endif | |
85 | ||
252b5132 RH |
86 | #include "ecoff.h" |
87 | ||
88 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
89 | static char *mips_regmask_frag; | |
90 | #endif | |
91 | ||
85b51719 | 92 | #define ZERO 0 |
741fe287 | 93 | #define ATREG 1 |
252b5132 RH |
94 | #define TREG 24 |
95 | #define PIC_CALL_REG 25 | |
96 | #define KT0 26 | |
97 | #define KT1 27 | |
98 | #define GP 28 | |
99 | #define SP 29 | |
100 | #define FP 30 | |
101 | #define RA 31 | |
102 | ||
103 | #define ILLEGAL_REG (32) | |
104 | ||
741fe287 MR |
105 | #define AT mips_opts.at |
106 | ||
252b5132 RH |
107 | /* Allow override of standard little-endian ECOFF format. */ |
108 | ||
109 | #ifndef ECOFF_LITTLE_FORMAT | |
110 | #define ECOFF_LITTLE_FORMAT "ecoff-littlemips" | |
111 | #endif | |
112 | ||
113 | extern int target_big_endian; | |
114 | ||
252b5132 | 115 | /* The name of the readonly data section. */ |
4d0d148d | 116 | #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_ecoff_flavour \ |
252b5132 | 117 | ? ".rdata" \ |
056350c6 NC |
118 | : OUTPUT_FLAVOR == bfd_target_coff_flavour \ |
119 | ? ".rdata" \ | |
252b5132 RH |
120 | : OUTPUT_FLAVOR == bfd_target_elf_flavour \ |
121 | ? ".rodata" \ | |
122 | : (abort (), "")) | |
123 | ||
47e39b9d RS |
124 | /* Information about an instruction, including its format, operands |
125 | and fixups. */ | |
126 | struct mips_cl_insn | |
127 | { | |
128 | /* The opcode's entry in mips_opcodes or mips16_opcodes. */ | |
129 | const struct mips_opcode *insn_mo; | |
130 | ||
131 | /* True if this is a mips16 instruction and if we want the extended | |
132 | form of INSN_MO. */ | |
133 | bfd_boolean use_extend; | |
134 | ||
135 | /* The 16-bit extension instruction to use when USE_EXTEND is true. */ | |
136 | unsigned short extend; | |
137 | ||
138 | /* The 16-bit or 32-bit bitstring of the instruction itself. This is | |
139 | a copy of INSN_MO->match with the operands filled in. */ | |
140 | unsigned long insn_opcode; | |
141 | ||
142 | /* The frag that contains the instruction. */ | |
143 | struct frag *frag; | |
144 | ||
145 | /* The offset into FRAG of the first instruction byte. */ | |
146 | long where; | |
147 | ||
148 | /* The relocs associated with the instruction, if any. */ | |
149 | fixS *fixp[3]; | |
150 | ||
a38419a5 RS |
151 | /* True if this entry cannot be moved from its current position. */ |
152 | unsigned int fixed_p : 1; | |
47e39b9d | 153 | |
708587a4 | 154 | /* True if this instruction occurred in a .set noreorder block. */ |
47e39b9d RS |
155 | unsigned int noreorder_p : 1; |
156 | ||
2fa15973 RS |
157 | /* True for mips16 instructions that jump to an absolute address. */ |
158 | unsigned int mips16_absolute_jump_p : 1; | |
47e39b9d RS |
159 | }; |
160 | ||
a325df1d TS |
161 | /* The ABI to use. */ |
162 | enum mips_abi_level | |
163 | { | |
164 | NO_ABI = 0, | |
165 | O32_ABI, | |
166 | O64_ABI, | |
167 | N32_ABI, | |
168 | N64_ABI, | |
169 | EABI_ABI | |
170 | }; | |
171 | ||
172 | /* MIPS ABI we are using for this output file. */ | |
316f5878 | 173 | static enum mips_abi_level mips_abi = NO_ABI; |
a325df1d | 174 | |
143d77c5 EC |
175 | /* Whether or not we have code that can call pic code. */ |
176 | int mips_abicalls = FALSE; | |
177 | ||
aa6975fb ILT |
178 | /* Whether or not we have code which can be put into a shared |
179 | library. */ | |
180 | static bfd_boolean mips_in_shared = TRUE; | |
181 | ||
252b5132 RH |
182 | /* This is the set of options which may be modified by the .set |
183 | pseudo-op. We use a struct so that .set push and .set pop are more | |
184 | reliable. */ | |
185 | ||
e972090a NC |
186 | struct mips_set_options |
187 | { | |
252b5132 RH |
188 | /* MIPS ISA (Instruction Set Architecture) level. This is set to -1 |
189 | if it has not been initialized. Changed by `.set mipsN', and the | |
190 | -mipsN command line option, and the default CPU. */ | |
191 | int isa; | |
1f25f5d3 CD |
192 | /* Enabled Application Specific Extensions (ASEs). These are set to -1 |
193 | if they have not been initialized. Changed by `.set <asename>', by | |
194 | command line options, and based on the default architecture. */ | |
195 | int ase_mips3d; | |
deec1734 | 196 | int ase_mdmx; |
e16bfa71 | 197 | int ase_smartmips; |
74cd071d | 198 | int ase_dsp; |
8b082fb1 | 199 | int ase_dspr2; |
ef2e4d86 | 200 | int ase_mt; |
252b5132 RH |
201 | /* Whether we are assembling for the mips16 processor. 0 if we are |
202 | not, 1 if we are, and -1 if the value has not been initialized. | |
203 | Changed by `.set mips16' and `.set nomips16', and the -mips16 and | |
204 | -nomips16 command line options, and the default CPU. */ | |
205 | int mips16; | |
206 | /* Non-zero if we should not reorder instructions. Changed by `.set | |
207 | reorder' and `.set noreorder'. */ | |
208 | int noreorder; | |
741fe287 MR |
209 | /* Non-zero if we should not permit the register designated "assembler |
210 | temporary" to be used in instructions. The value is the register | |
211 | number, normally $at ($1). Changed by `.set at=REG', `.set noat' | |
212 | (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */ | |
213 | unsigned int at; | |
252b5132 RH |
214 | /* Non-zero if we should warn when a macro instruction expands into |
215 | more than one machine instruction. Changed by `.set nomacro' and | |
216 | `.set macro'. */ | |
217 | int warn_about_macros; | |
218 | /* Non-zero if we should not move instructions. Changed by `.set | |
219 | move', `.set volatile', `.set nomove', and `.set novolatile'. */ | |
220 | int nomove; | |
221 | /* Non-zero if we should not optimize branches by moving the target | |
222 | of the branch into the delay slot. Actually, we don't perform | |
223 | this optimization anyhow. Changed by `.set bopt' and `.set | |
224 | nobopt'. */ | |
225 | int nobopt; | |
226 | /* Non-zero if we should not autoextend mips16 instructions. | |
227 | Changed by `.set autoextend' and `.set noautoextend'. */ | |
228 | int noautoextend; | |
a325df1d TS |
229 | /* Restrict general purpose registers and floating point registers |
230 | to 32 bit. This is initially determined when -mgp32 or -mfp32 | |
231 | is passed but can changed if the assembler code uses .set mipsN. */ | |
232 | int gp32; | |
233 | int fp32; | |
fef14a42 TS |
234 | /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march |
235 | command line option, and the default CPU. */ | |
236 | int arch; | |
aed1a261 RS |
237 | /* True if ".set sym32" is in effect. */ |
238 | bfd_boolean sym32; | |
037b32b9 AN |
239 | /* True if floating-point operations are not allowed. Changed by .set |
240 | softfloat or .set hardfloat, by command line options -msoft-float or | |
241 | -mhard-float. The default is false. */ | |
242 | bfd_boolean soft_float; | |
243 | ||
244 | /* True if only single-precision floating-point operations are allowed. | |
245 | Changed by .set singlefloat or .set doublefloat, command-line options | |
246 | -msingle-float or -mdouble-float. The default is false. */ | |
247 | bfd_boolean single_float; | |
252b5132 RH |
248 | }; |
249 | ||
037b32b9 AN |
250 | /* This is the struct we use to hold the current set of options. Note |
251 | that we must set the isa field to ISA_UNKNOWN and the ASE fields to | |
252 | -1 to indicate that they have not been initialized. */ | |
253 | ||
a325df1d | 254 | /* True if -mgp32 was passed. */ |
a8e8e863 | 255 | static int file_mips_gp32 = -1; |
a325df1d TS |
256 | |
257 | /* True if -mfp32 was passed. */ | |
a8e8e863 | 258 | static int file_mips_fp32 = -1; |
a325df1d | 259 | |
037b32b9 AN |
260 | /* 1 if -msoft-float, 0 if -mhard-float. The default is 0. */ |
261 | static int file_mips_soft_float = 0; | |
262 | ||
263 | /* 1 if -msingle-float, 0 if -mdouble-float. The default is 0. */ | |
264 | static int file_mips_single_float = 0; | |
252b5132 | 265 | |
e972090a NC |
266 | static struct mips_set_options mips_opts = |
267 | { | |
037b32b9 AN |
268 | /* isa */ ISA_UNKNOWN, /* ase_mips3d */ -1, /* ase_mdmx */ -1, |
269 | /* ase_smartmips */ 0, /* ase_dsp */ -1, /* ase_dspr2 */ -1, /* ase_mt */ -1, | |
270 | /* mips16 */ -1, /* noreorder */ 0, /* at */ ATREG, | |
271 | /* warn_about_macros */ 0, /* nomove */ 0, /* nobopt */ 0, | |
272 | /* noautoextend */ 0, /* gp32 */ 0, /* fp32 */ 0, /* arch */ CPU_UNKNOWN, | |
273 | /* sym32 */ FALSE, /* soft_float */ FALSE, /* single_float */ FALSE | |
e7af610e | 274 | }; |
252b5132 RH |
275 | |
276 | /* These variables are filled in with the masks of registers used. | |
277 | The object format code reads them and puts them in the appropriate | |
278 | place. */ | |
279 | unsigned long mips_gprmask; | |
280 | unsigned long mips_cprmask[4]; | |
281 | ||
282 | /* MIPS ISA we are using for this output file. */ | |
e7af610e | 283 | static int file_mips_isa = ISA_UNKNOWN; |
252b5132 | 284 | |
a4672219 TS |
285 | /* True if -mips16 was passed or implied by arguments passed on the |
286 | command line (e.g., by -march). */ | |
287 | static int file_ase_mips16; | |
288 | ||
3994f87e TS |
289 | #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \ |
290 | || mips_opts.isa == ISA_MIPS32R2 \ | |
291 | || mips_opts.isa == ISA_MIPS64 \ | |
292 | || mips_opts.isa == ISA_MIPS64R2) | |
293 | ||
b12dd2e4 CF |
294 | /* True if we want to create R_MIPS_JALR for jalr $25. */ |
295 | #ifdef TE_IRIX | |
1180b5a4 | 296 | #define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI |
b12dd2e4 | 297 | #else |
1180b5a4 RS |
298 | /* As a GNU extension, we use R_MIPS_JALR for o32 too. However, |
299 | because there's no place for any addend, the only acceptable | |
300 | expression is a bare symbol. */ | |
301 | #define MIPS_JALR_HINT_P(EXPR) \ | |
302 | (!HAVE_IN_PLACE_ADDENDS \ | |
303 | || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0)) | |
b12dd2e4 CF |
304 | #endif |
305 | ||
1f25f5d3 CD |
306 | /* True if -mips3d was passed or implied by arguments passed on the |
307 | command line (e.g., by -march). */ | |
308 | static int file_ase_mips3d; | |
309 | ||
deec1734 CD |
310 | /* True if -mdmx was passed or implied by arguments passed on the |
311 | command line (e.g., by -march). */ | |
312 | static int file_ase_mdmx; | |
313 | ||
e16bfa71 TS |
314 | /* True if -msmartmips was passed or implied by arguments passed on the |
315 | command line (e.g., by -march). */ | |
316 | static int file_ase_smartmips; | |
317 | ||
ad3fea08 TS |
318 | #define ISA_SUPPORTS_SMARTMIPS (mips_opts.isa == ISA_MIPS32 \ |
319 | || mips_opts.isa == ISA_MIPS32R2) | |
e16bfa71 | 320 | |
74cd071d CF |
321 | /* True if -mdsp was passed or implied by arguments passed on the |
322 | command line (e.g., by -march). */ | |
323 | static int file_ase_dsp; | |
324 | ||
ad3fea08 TS |
325 | #define ISA_SUPPORTS_DSP_ASE (mips_opts.isa == ISA_MIPS32R2 \ |
326 | || mips_opts.isa == ISA_MIPS64R2) | |
327 | ||
65263ce3 TS |
328 | #define ISA_SUPPORTS_DSP64_ASE (mips_opts.isa == ISA_MIPS64R2) |
329 | ||
8b082fb1 TS |
330 | /* True if -mdspr2 was passed or implied by arguments passed on the |
331 | command line (e.g., by -march). */ | |
332 | static int file_ase_dspr2; | |
333 | ||
334 | #define ISA_SUPPORTS_DSPR2_ASE (mips_opts.isa == ISA_MIPS32R2 \ | |
335 | || mips_opts.isa == ISA_MIPS64R2) | |
336 | ||
ef2e4d86 CF |
337 | /* True if -mmt was passed or implied by arguments passed on the |
338 | command line (e.g., by -march). */ | |
339 | static int file_ase_mt; | |
340 | ||
ad3fea08 TS |
341 | #define ISA_SUPPORTS_MT_ASE (mips_opts.isa == ISA_MIPS32R2 \ |
342 | || mips_opts.isa == ISA_MIPS64R2) | |
343 | ||
ec68c924 | 344 | /* The argument of the -march= flag. The architecture we are assembling. */ |
fef14a42 | 345 | static int file_mips_arch = CPU_UNKNOWN; |
316f5878 | 346 | static const char *mips_arch_string; |
ec68c924 EC |
347 | |
348 | /* The argument of the -mtune= flag. The architecture for which we | |
349 | are optimizing. */ | |
350 | static int mips_tune = CPU_UNKNOWN; | |
316f5878 | 351 | static const char *mips_tune_string; |
ec68c924 | 352 | |
316f5878 | 353 | /* True when generating 32-bit code for a 64-bit processor. */ |
252b5132 RH |
354 | static int mips_32bitmode = 0; |
355 | ||
316f5878 RS |
356 | /* True if the given ABI requires 32-bit registers. */ |
357 | #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI) | |
358 | ||
359 | /* Likewise 64-bit registers. */ | |
707bfff6 TS |
360 | #define ABI_NEEDS_64BIT_REGS(ABI) \ |
361 | ((ABI) == N32_ABI \ | |
362 | || (ABI) == N64_ABI \ | |
316f5878 RS |
363 | || (ABI) == O64_ABI) |
364 | ||
ad3fea08 | 365 | /* Return true if ISA supports 64 bit wide gp registers. */ |
707bfff6 TS |
366 | #define ISA_HAS_64BIT_REGS(ISA) \ |
367 | ((ISA) == ISA_MIPS3 \ | |
368 | || (ISA) == ISA_MIPS4 \ | |
369 | || (ISA) == ISA_MIPS5 \ | |
370 | || (ISA) == ISA_MIPS64 \ | |
371 | || (ISA) == ISA_MIPS64R2) | |
9ce8a5dd | 372 | |
ad3fea08 TS |
373 | /* Return true if ISA supports 64 bit wide float registers. */ |
374 | #define ISA_HAS_64BIT_FPRS(ISA) \ | |
375 | ((ISA) == ISA_MIPS3 \ | |
376 | || (ISA) == ISA_MIPS4 \ | |
377 | || (ISA) == ISA_MIPS5 \ | |
378 | || (ISA) == ISA_MIPS32R2 \ | |
379 | || (ISA) == ISA_MIPS64 \ | |
380 | || (ISA) == ISA_MIPS64R2) | |
381 | ||
af7ee8bf CD |
382 | /* Return true if ISA supports 64-bit right rotate (dror et al.) |
383 | instructions. */ | |
707bfff6 TS |
384 | #define ISA_HAS_DROR(ISA) \ |
385 | ((ISA) == ISA_MIPS64R2) | |
af7ee8bf CD |
386 | |
387 | /* Return true if ISA supports 32-bit right rotate (ror et al.) | |
388 | instructions. */ | |
707bfff6 TS |
389 | #define ISA_HAS_ROR(ISA) \ |
390 | ((ISA) == ISA_MIPS32R2 \ | |
391 | || (ISA) == ISA_MIPS64R2 \ | |
392 | || mips_opts.ase_smartmips) | |
393 | ||
7455baf8 TS |
394 | /* Return true if ISA supports single-precision floats in odd registers. */ |
395 | #define ISA_HAS_ODD_SINGLE_FPR(ISA) \ | |
396 | ((ISA) == ISA_MIPS32 \ | |
397 | || (ISA) == ISA_MIPS32R2 \ | |
398 | || (ISA) == ISA_MIPS64 \ | |
399 | || (ISA) == ISA_MIPS64R2) | |
af7ee8bf | 400 | |
ad3fea08 TS |
401 | /* Return true if ISA supports move to/from high part of a 64-bit |
402 | floating-point register. */ | |
403 | #define ISA_HAS_MXHC1(ISA) \ | |
404 | ((ISA) == ISA_MIPS32R2 \ | |
405 | || (ISA) == ISA_MIPS64R2) | |
406 | ||
e013f690 | 407 | #define HAVE_32BIT_GPRS \ |
ad3fea08 | 408 | (mips_opts.gp32 || !ISA_HAS_64BIT_REGS (mips_opts.isa)) |
ca4e0257 | 409 | |
e013f690 | 410 | #define HAVE_32BIT_FPRS \ |
ad3fea08 | 411 | (mips_opts.fp32 || !ISA_HAS_64BIT_FPRS (mips_opts.isa)) |
ca4e0257 | 412 | |
ad3fea08 TS |
413 | #define HAVE_64BIT_GPRS (!HAVE_32BIT_GPRS) |
414 | #define HAVE_64BIT_FPRS (!HAVE_32BIT_FPRS) | |
ca4e0257 | 415 | |
316f5878 | 416 | #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI) |
e013f690 | 417 | |
316f5878 | 418 | #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI) |
e013f690 | 419 | |
3b91255e RS |
420 | /* True if relocations are stored in-place. */ |
421 | #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI) | |
422 | ||
aed1a261 RS |
423 | /* The ABI-derived address size. */ |
424 | #define HAVE_64BIT_ADDRESSES \ | |
425 | (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI)) | |
426 | #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES) | |
e013f690 | 427 | |
aed1a261 RS |
428 | /* The size of symbolic constants (i.e., expressions of the form |
429 | "SYMBOL" or "SYMBOL + OFFSET"). */ | |
430 | #define HAVE_32BIT_SYMBOLS \ | |
431 | (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32) | |
432 | #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS) | |
ca4e0257 | 433 | |
b7c7d6c1 TS |
434 | /* Addresses are loaded in different ways, depending on the address size |
435 | in use. The n32 ABI Documentation also mandates the use of additions | |
436 | with overflow checking, but existing implementations don't follow it. */ | |
f899b4b8 | 437 | #define ADDRESS_ADD_INSN \ |
b7c7d6c1 | 438 | (HAVE_32BIT_ADDRESSES ? "addu" : "daddu") |
f899b4b8 TS |
439 | |
440 | #define ADDRESS_ADDI_INSN \ | |
b7c7d6c1 | 441 | (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu") |
f899b4b8 TS |
442 | |
443 | #define ADDRESS_LOAD_INSN \ | |
444 | (HAVE_32BIT_ADDRESSES ? "lw" : "ld") | |
445 | ||
446 | #define ADDRESS_STORE_INSN \ | |
447 | (HAVE_32BIT_ADDRESSES ? "sw" : "sd") | |
448 | ||
a4672219 | 449 | /* Return true if the given CPU supports the MIPS16 ASE. */ |
3396de36 TS |
450 | #define CPU_HAS_MIPS16(cpu) \ |
451 | (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \ | |
452 | || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0) | |
a4672219 | 453 | |
60b63b72 RS |
454 | /* True if CPU has a dror instruction. */ |
455 | #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500) | |
456 | ||
457 | /* True if CPU has a ror instruction. */ | |
458 | #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU) | |
459 | ||
dd3cbb7e NC |
460 | /* True if CPU has seq/sne and seqi/snei instructions. */ |
461 | #define CPU_HAS_SEQ(CPU) ((CPU) == CPU_OCTEON) | |
462 | ||
b19e8a9b AN |
463 | /* True if CPU does not implement the all the coprocessor insns. For these |
464 | CPUs only those COP insns are accepted that are explicitly marked to be | |
465 | available on the CPU. ISA membership for COP insns is ignored. */ | |
466 | #define NO_ISA_COP(CPU) ((CPU) == CPU_OCTEON) | |
467 | ||
c8978940 CD |
468 | /* True if mflo and mfhi can be immediately followed by instructions |
469 | which write to the HI and LO registers. | |
470 | ||
471 | According to MIPS specifications, MIPS ISAs I, II, and III need | |
472 | (at least) two instructions between the reads of HI/LO and | |
473 | instructions which write them, and later ISAs do not. Contradicting | |
474 | the MIPS specifications, some MIPS IV processor user manuals (e.g. | |
475 | the UM for the NEC Vr5000) document needing the instructions between | |
476 | HI/LO reads and writes, as well. Therefore, we declare only MIPS32, | |
477 | MIPS64 and later ISAs to have the interlocks, plus any specific | |
478 | earlier-ISA CPUs for which CPU documentation declares that the | |
479 | instructions are really interlocked. */ | |
480 | #define hilo_interlocks \ | |
481 | (mips_opts.isa == ISA_MIPS32 \ | |
482 | || mips_opts.isa == ISA_MIPS32R2 \ | |
483 | || mips_opts.isa == ISA_MIPS64 \ | |
484 | || mips_opts.isa == ISA_MIPS64R2 \ | |
485 | || mips_opts.arch == CPU_R4010 \ | |
486 | || mips_opts.arch == CPU_R10000 \ | |
487 | || mips_opts.arch == CPU_R12000 \ | |
3aa3176b TS |
488 | || mips_opts.arch == CPU_R14000 \ |
489 | || mips_opts.arch == CPU_R16000 \ | |
c8978940 | 490 | || mips_opts.arch == CPU_RM7000 \ |
c8978940 CD |
491 | || mips_opts.arch == CPU_VR5500 \ |
492 | ) | |
252b5132 RH |
493 | |
494 | /* Whether the processor uses hardware interlocks to protect reads | |
81912461 ILT |
495 | from the GPRs after they are loaded from memory, and thus does not |
496 | require nops to be inserted. This applies to instructions marked | |
497 | INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA | |
498 | level I. */ | |
252b5132 | 499 | #define gpr_interlocks \ |
e7af610e | 500 | (mips_opts.isa != ISA_MIPS1 \ |
fef14a42 | 501 | || mips_opts.arch == CPU_R3900) |
252b5132 | 502 | |
81912461 ILT |
503 | /* Whether the processor uses hardware interlocks to avoid delays |
504 | required by coprocessor instructions, and thus does not require | |
505 | nops to be inserted. This applies to instructions marked | |
506 | INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays | |
507 | between instructions marked INSN_WRITE_COND_CODE and ones marked | |
508 | INSN_READ_COND_CODE. These nops are only required at MIPS ISA | |
509 | levels I, II, and III. */ | |
bdaaa2e1 | 510 | /* Itbl support may require additional care here. */ |
81912461 ILT |
511 | #define cop_interlocks \ |
512 | ((mips_opts.isa != ISA_MIPS1 \ | |
513 | && mips_opts.isa != ISA_MIPS2 \ | |
514 | && mips_opts.isa != ISA_MIPS3) \ | |
515 | || mips_opts.arch == CPU_R4300 \ | |
81912461 ILT |
516 | ) |
517 | ||
518 | /* Whether the processor uses hardware interlocks to protect reads | |
519 | from coprocessor registers after they are loaded from memory, and | |
520 | thus does not require nops to be inserted. This applies to | |
521 | instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only | |
522 | requires at MIPS ISA level I. */ | |
523 | #define cop_mem_interlocks (mips_opts.isa != ISA_MIPS1) | |
252b5132 | 524 | |
6b76fefe CM |
525 | /* Is this a mfhi or mflo instruction? */ |
526 | #define MF_HILO_INSN(PINFO) \ | |
b19e8a9b AN |
527 | ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO)) |
528 | ||
529 | /* Returns true for a (non floating-point) coprocessor instruction. Reading | |
530 | or writing the condition code is only possible on the coprocessors and | |
531 | these insns are not marked with INSN_COP. Thus for these insns use the | |
a242dc0d | 532 | condition-code flags. */ |
b19e8a9b AN |
533 | #define COP_INSN(PINFO) \ |
534 | (PINFO != INSN_MACRO \ | |
a242dc0d AN |
535 | && ((PINFO) & (FP_S | FP_D)) == 0 \ |
536 | && ((PINFO) & (INSN_COP | INSN_READ_COND_CODE | INSN_WRITE_COND_CODE))) | |
6b76fefe | 537 | |
252b5132 RH |
538 | /* MIPS PIC level. */ |
539 | ||
a161fe53 | 540 | enum mips_pic_level mips_pic; |
252b5132 | 541 | |
c9914766 | 542 | /* 1 if we should generate 32 bit offsets from the $gp register in |
252b5132 | 543 | SVR4_PIC mode. Currently has no meaning in other modes. */ |
c9914766 | 544 | static int mips_big_got = 0; |
252b5132 RH |
545 | |
546 | /* 1 if trap instructions should used for overflow rather than break | |
547 | instructions. */ | |
c9914766 | 548 | static int mips_trap = 0; |
252b5132 | 549 | |
119d663a | 550 | /* 1 if double width floating point constants should not be constructed |
b6ff326e | 551 | by assembling two single width halves into two single width floating |
119d663a NC |
552 | point registers which just happen to alias the double width destination |
553 | register. On some architectures this aliasing can be disabled by a bit | |
d547a75e | 554 | in the status register, and the setting of this bit cannot be determined |
119d663a NC |
555 | automatically at assemble time. */ |
556 | static int mips_disable_float_construction; | |
557 | ||
252b5132 RH |
558 | /* Non-zero if any .set noreorder directives were used. */ |
559 | ||
560 | static int mips_any_noreorder; | |
561 | ||
6b76fefe CM |
562 | /* Non-zero if nops should be inserted when the register referenced in |
563 | an mfhi/mflo instruction is read in the next two instructions. */ | |
564 | static int mips_7000_hilo_fix; | |
565 | ||
02ffd3e4 | 566 | /* The size of objects in the small data section. */ |
156c2f8b | 567 | static unsigned int g_switch_value = 8; |
252b5132 RH |
568 | /* Whether the -G option was used. */ |
569 | static int g_switch_seen = 0; | |
570 | ||
571 | #define N_RMASK 0xc4 | |
572 | #define N_VFP 0xd4 | |
573 | ||
574 | /* If we can determine in advance that GP optimization won't be | |
575 | possible, we can skip the relaxation stuff that tries to produce | |
576 | GP-relative references. This makes delay slot optimization work | |
577 | better. | |
578 | ||
579 | This function can only provide a guess, but it seems to work for | |
fba2b7f9 GK |
580 | gcc output. It needs to guess right for gcc, otherwise gcc |
581 | will put what it thinks is a GP-relative instruction in a branch | |
582 | delay slot. | |
252b5132 RH |
583 | |
584 | I don't know if a fix is needed for the SVR4_PIC mode. I've only | |
585 | fixed it for the non-PIC mode. KR 95/04/07 */ | |
17a2f251 | 586 | static int nopic_need_relax (symbolS *, int); |
252b5132 RH |
587 | |
588 | /* handle of the OPCODE hash table */ | |
589 | static struct hash_control *op_hash = NULL; | |
590 | ||
591 | /* The opcode hash table we use for the mips16. */ | |
592 | static struct hash_control *mips16_op_hash = NULL; | |
593 | ||
594 | /* This array holds the chars that always start a comment. If the | |
595 | pre-processor is disabled, these aren't very useful */ | |
596 | const char comment_chars[] = "#"; | |
597 | ||
598 | /* This array holds the chars that only start a comment at the beginning of | |
599 | a line. If the line seems to have the form '# 123 filename' | |
600 | .line and .file directives will appear in the pre-processed output */ | |
601 | /* Note that input_file.c hand checks for '#' at the beginning of the | |
602 | first line of the input file. This is because the compiler outputs | |
bdaaa2e1 | 603 | #NO_APP at the beginning of its output. */ |
252b5132 RH |
604 | /* Also note that C style comments are always supported. */ |
605 | const char line_comment_chars[] = "#"; | |
606 | ||
bdaaa2e1 | 607 | /* This array holds machine specific line separator characters. */ |
63a0b638 | 608 | const char line_separator_chars[] = ";"; |
252b5132 RH |
609 | |
610 | /* Chars that can be used to separate mant from exp in floating point nums */ | |
611 | const char EXP_CHARS[] = "eE"; | |
612 | ||
613 | /* Chars that mean this number is a floating point constant */ | |
614 | /* As in 0f12.456 */ | |
615 | /* or 0d1.2345e12 */ | |
616 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; | |
617 | ||
618 | /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be | |
619 | changed in read.c . Ideally it shouldn't have to know about it at all, | |
620 | but nothing is ideal around here. | |
621 | */ | |
622 | ||
623 | static char *insn_error; | |
624 | ||
625 | static int auto_align = 1; | |
626 | ||
627 | /* When outputting SVR4 PIC code, the assembler needs to know the | |
628 | offset in the stack frame from which to restore the $gp register. | |
629 | This is set by the .cprestore pseudo-op, and saved in this | |
630 | variable. */ | |
631 | static offsetT mips_cprestore_offset = -1; | |
632 | ||
67c1ffbe | 633 | /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some |
6478892d | 634 | more optimizations, it can use a register value instead of a memory-saved |
956cd1d6 | 635 | offset and even an other register than $gp as global pointer. */ |
6478892d TS |
636 | static offsetT mips_cpreturn_offset = -1; |
637 | static int mips_cpreturn_register = -1; | |
638 | static int mips_gp_register = GP; | |
def2e0dd | 639 | static int mips_gprel_offset = 0; |
6478892d | 640 | |
7a621144 DJ |
641 | /* Whether mips_cprestore_offset has been set in the current function |
642 | (or whether it has already been warned about, if not). */ | |
643 | static int mips_cprestore_valid = 0; | |
644 | ||
252b5132 RH |
645 | /* This is the register which holds the stack frame, as set by the |
646 | .frame pseudo-op. This is needed to implement .cprestore. */ | |
647 | static int mips_frame_reg = SP; | |
648 | ||
7a621144 DJ |
649 | /* Whether mips_frame_reg has been set in the current function |
650 | (or whether it has already been warned about, if not). */ | |
651 | static int mips_frame_reg_valid = 0; | |
652 | ||
252b5132 RH |
653 | /* To output NOP instructions correctly, we need to keep information |
654 | about the previous two instructions. */ | |
655 | ||
656 | /* Whether we are optimizing. The default value of 2 means to remove | |
657 | unneeded NOPs and swap branch instructions when possible. A value | |
658 | of 1 means to not swap branches. A value of 0 means to always | |
659 | insert NOPs. */ | |
660 | static int mips_optimize = 2; | |
661 | ||
662 | /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is | |
663 | equivalent to seeing no -g option at all. */ | |
664 | static int mips_debug = 0; | |
665 | ||
7d8e00cf RS |
666 | /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */ |
667 | #define MAX_VR4130_NOPS 4 | |
668 | ||
669 | /* The maximum number of NOPs needed to fill delay slots. */ | |
670 | #define MAX_DELAY_NOPS 2 | |
671 | ||
672 | /* The maximum number of NOPs needed for any purpose. */ | |
673 | #define MAX_NOPS 4 | |
71400594 RS |
674 | |
675 | /* A list of previous instructions, with index 0 being the most recent. | |
676 | We need to look back MAX_NOPS instructions when filling delay slots | |
677 | or working around processor errata. We need to look back one | |
678 | instruction further if we're thinking about using history[0] to | |
679 | fill a branch delay slot. */ | |
680 | static struct mips_cl_insn history[1 + MAX_NOPS]; | |
252b5132 | 681 | |
1e915849 RS |
682 | /* Nop instructions used by emit_nop. */ |
683 | static struct mips_cl_insn nop_insn, mips16_nop_insn; | |
684 | ||
685 | /* The appropriate nop for the current mode. */ | |
686 | #define NOP_INSN (mips_opts.mips16 ? &mips16_nop_insn : &nop_insn) | |
252b5132 | 687 | |
252b5132 RH |
688 | /* If this is set, it points to a frag holding nop instructions which |
689 | were inserted before the start of a noreorder section. If those | |
690 | nops turn out to be unnecessary, the size of the frag can be | |
691 | decreased. */ | |
692 | static fragS *prev_nop_frag; | |
693 | ||
694 | /* The number of nop instructions we created in prev_nop_frag. */ | |
695 | static int prev_nop_frag_holds; | |
696 | ||
697 | /* The number of nop instructions that we know we need in | |
bdaaa2e1 | 698 | prev_nop_frag. */ |
252b5132 RH |
699 | static int prev_nop_frag_required; |
700 | ||
701 | /* The number of instructions we've seen since prev_nop_frag. */ | |
702 | static int prev_nop_frag_since; | |
703 | ||
704 | /* For ECOFF and ELF, relocations against symbols are done in two | |
705 | parts, with a HI relocation and a LO relocation. Each relocation | |
706 | has only 16 bits of space to store an addend. This means that in | |
707 | order for the linker to handle carries correctly, it must be able | |
708 | to locate both the HI and the LO relocation. This means that the | |
709 | relocations must appear in order in the relocation table. | |
710 | ||
711 | In order to implement this, we keep track of each unmatched HI | |
712 | relocation. We then sort them so that they immediately precede the | |
bdaaa2e1 | 713 | corresponding LO relocation. */ |
252b5132 | 714 | |
e972090a NC |
715 | struct mips_hi_fixup |
716 | { | |
252b5132 RH |
717 | /* Next HI fixup. */ |
718 | struct mips_hi_fixup *next; | |
719 | /* This fixup. */ | |
720 | fixS *fixp; | |
721 | /* The section this fixup is in. */ | |
722 | segT seg; | |
723 | }; | |
724 | ||
725 | /* The list of unmatched HI relocs. */ | |
726 | ||
727 | static struct mips_hi_fixup *mips_hi_fixup_list; | |
728 | ||
64bdfcaf RS |
729 | /* The frag containing the last explicit relocation operator. |
730 | Null if explicit relocations have not been used. */ | |
731 | ||
732 | static fragS *prev_reloc_op_frag; | |
733 | ||
252b5132 RH |
734 | /* Map normal MIPS register numbers to mips16 register numbers. */ |
735 | ||
736 | #define X ILLEGAL_REG | |
e972090a NC |
737 | static const int mips32_to_16_reg_map[] = |
738 | { | |
252b5132 RH |
739 | X, X, 2, 3, 4, 5, 6, 7, |
740 | X, X, X, X, X, X, X, X, | |
741 | 0, 1, X, X, X, X, X, X, | |
742 | X, X, X, X, X, X, X, X | |
743 | }; | |
744 | #undef X | |
745 | ||
746 | /* Map mips16 register numbers to normal MIPS register numbers. */ | |
747 | ||
e972090a NC |
748 | static const unsigned int mips16_to_32_reg_map[] = |
749 | { | |
252b5132 RH |
750 | 16, 17, 2, 3, 4, 5, 6, 7 |
751 | }; | |
60b63b72 | 752 | |
71400594 RS |
753 | /* Classifies the kind of instructions we're interested in when |
754 | implementing -mfix-vr4120. */ | |
c67a084a NC |
755 | enum fix_vr4120_class |
756 | { | |
71400594 RS |
757 | FIX_VR4120_MACC, |
758 | FIX_VR4120_DMACC, | |
759 | FIX_VR4120_MULT, | |
760 | FIX_VR4120_DMULT, | |
761 | FIX_VR4120_DIV, | |
762 | FIX_VR4120_MTHILO, | |
763 | NUM_FIX_VR4120_CLASSES | |
764 | }; | |
765 | ||
c67a084a NC |
766 | /* ...likewise -mfix-loongson2f-jump. */ |
767 | static bfd_boolean mips_fix_loongson2f_jump; | |
768 | ||
769 | /* ...likewise -mfix-loongson2f-nop. */ | |
770 | static bfd_boolean mips_fix_loongson2f_nop; | |
771 | ||
772 | /* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */ | |
773 | static bfd_boolean mips_fix_loongson2f; | |
774 | ||
71400594 RS |
775 | /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if |
776 | there must be at least one other instruction between an instruction | |
777 | of type X and an instruction of type Y. */ | |
778 | static unsigned int vr4120_conflicts[NUM_FIX_VR4120_CLASSES]; | |
779 | ||
780 | /* True if -mfix-vr4120 is in force. */ | |
d766e8ec | 781 | static int mips_fix_vr4120; |
4a6a3df4 | 782 | |
7d8e00cf RS |
783 | /* ...likewise -mfix-vr4130. */ |
784 | static int mips_fix_vr4130; | |
785 | ||
6a32d874 CM |
786 | /* ...likewise -mfix-24k. */ |
787 | static int mips_fix_24k; | |
788 | ||
d954098f DD |
789 | /* ...likewise -mfix-cn63xxp1 */ |
790 | static bfd_boolean mips_fix_cn63xxp1; | |
791 | ||
4a6a3df4 AO |
792 | /* We don't relax branches by default, since this causes us to expand |
793 | `la .l2 - .l1' if there's a branch between .l1 and .l2, because we | |
794 | fail to compute the offset before expanding the macro to the most | |
795 | efficient expansion. */ | |
796 | ||
797 | static int mips_relax_branch; | |
252b5132 | 798 | \f |
4d7206a2 RS |
799 | /* The expansion of many macros depends on the type of symbol that |
800 | they refer to. For example, when generating position-dependent code, | |
801 | a macro that refers to a symbol may have two different expansions, | |
802 | one which uses GP-relative addresses and one which uses absolute | |
803 | addresses. When generating SVR4-style PIC, a macro may have | |
804 | different expansions for local and global symbols. | |
805 | ||
806 | We handle these situations by generating both sequences and putting | |
807 | them in variant frags. In position-dependent code, the first sequence | |
808 | will be the GP-relative one and the second sequence will be the | |
809 | absolute one. In SVR4 PIC, the first sequence will be for global | |
810 | symbols and the second will be for local symbols. | |
811 | ||
584892a6 RS |
812 | The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and |
813 | SECOND are the lengths of the two sequences in bytes. These fields | |
814 | can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition, | |
815 | the subtype has the following flags: | |
4d7206a2 | 816 | |
584892a6 RS |
817 | RELAX_USE_SECOND |
818 | Set if it has been decided that we should use the second | |
819 | sequence instead of the first. | |
820 | ||
821 | RELAX_SECOND_LONGER | |
822 | Set in the first variant frag if the macro's second implementation | |
823 | is longer than its first. This refers to the macro as a whole, | |
824 | not an individual relaxation. | |
825 | ||
826 | RELAX_NOMACRO | |
827 | Set in the first variant frag if the macro appeared in a .set nomacro | |
828 | block and if one alternative requires a warning but the other does not. | |
829 | ||
830 | RELAX_DELAY_SLOT | |
831 | Like RELAX_NOMACRO, but indicates that the macro appears in a branch | |
832 | delay slot. | |
4d7206a2 RS |
833 | |
834 | The frag's "opcode" points to the first fixup for relaxable code. | |
835 | ||
836 | Relaxable macros are generated using a sequence such as: | |
837 | ||
838 | relax_start (SYMBOL); | |
839 | ... generate first expansion ... | |
840 | relax_switch (); | |
841 | ... generate second expansion ... | |
842 | relax_end (); | |
843 | ||
844 | The code and fixups for the unwanted alternative are discarded | |
845 | by md_convert_frag. */ | |
584892a6 | 846 | #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND)) |
4d7206a2 | 847 | |
584892a6 RS |
848 | #define RELAX_FIRST(X) (((X) >> 8) & 0xff) |
849 | #define RELAX_SECOND(X) ((X) & 0xff) | |
850 | #define RELAX_USE_SECOND 0x10000 | |
851 | #define RELAX_SECOND_LONGER 0x20000 | |
852 | #define RELAX_NOMACRO 0x40000 | |
853 | #define RELAX_DELAY_SLOT 0x80000 | |
252b5132 | 854 | |
4a6a3df4 AO |
855 | /* Branch without likely bit. If label is out of range, we turn: |
856 | ||
857 | beq reg1, reg2, label | |
858 | delay slot | |
859 | ||
860 | into | |
861 | ||
862 | bne reg1, reg2, 0f | |
863 | nop | |
864 | j label | |
865 | 0: delay slot | |
866 | ||
867 | with the following opcode replacements: | |
868 | ||
869 | beq <-> bne | |
870 | blez <-> bgtz | |
871 | bltz <-> bgez | |
872 | bc1f <-> bc1t | |
873 | ||
874 | bltzal <-> bgezal (with jal label instead of j label) | |
875 | ||
876 | Even though keeping the delay slot instruction in the delay slot of | |
877 | the branch would be more efficient, it would be very tricky to do | |
878 | correctly, because we'd have to introduce a variable frag *after* | |
879 | the delay slot instruction, and expand that instead. Let's do it | |
880 | the easy way for now, even if the branch-not-taken case now costs | |
881 | one additional instruction. Out-of-range branches are not supposed | |
882 | to be common, anyway. | |
883 | ||
884 | Branch likely. If label is out of range, we turn: | |
885 | ||
886 | beql reg1, reg2, label | |
887 | delay slot (annulled if branch not taken) | |
888 | ||
889 | into | |
890 | ||
891 | beql reg1, reg2, 1f | |
892 | nop | |
893 | beql $0, $0, 2f | |
894 | nop | |
895 | 1: j[al] label | |
896 | delay slot (executed only if branch taken) | |
897 | 2: | |
898 | ||
899 | It would be possible to generate a shorter sequence by losing the | |
900 | likely bit, generating something like: | |
b34976b6 | 901 | |
4a6a3df4 AO |
902 | bne reg1, reg2, 0f |
903 | nop | |
904 | j[al] label | |
905 | delay slot (executed only if branch taken) | |
906 | 0: | |
907 | ||
908 | beql -> bne | |
909 | bnel -> beq | |
910 | blezl -> bgtz | |
911 | bgtzl -> blez | |
912 | bltzl -> bgez | |
913 | bgezl -> bltz | |
914 | bc1fl -> bc1t | |
915 | bc1tl -> bc1f | |
916 | ||
917 | bltzall -> bgezal (with jal label instead of j label) | |
918 | bgezall -> bltzal (ditto) | |
919 | ||
920 | ||
921 | but it's not clear that it would actually improve performance. */ | |
af6ae2ad | 922 | #define RELAX_BRANCH_ENCODE(uncond, likely, link, toofar) \ |
4a6a3df4 AO |
923 | ((relax_substateT) \ |
924 | (0xc0000000 \ | |
925 | | ((toofar) ? 1 : 0) \ | |
926 | | ((link) ? 2 : 0) \ | |
927 | | ((likely) ? 4 : 0) \ | |
af6ae2ad | 928 | | ((uncond) ? 8 : 0))) |
4a6a3df4 | 929 | #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000) |
4a6a3df4 AO |
930 | #define RELAX_BRANCH_UNCOND(i) (((i) & 8) != 0) |
931 | #define RELAX_BRANCH_LIKELY(i) (((i) & 4) != 0) | |
932 | #define RELAX_BRANCH_LINK(i) (((i) & 2) != 0) | |
ae6063d4 | 933 | #define RELAX_BRANCH_TOOFAR(i) (((i) & 1) != 0) |
4a6a3df4 | 934 | |
252b5132 RH |
935 | /* For mips16 code, we use an entirely different form of relaxation. |
936 | mips16 supports two versions of most instructions which take | |
937 | immediate values: a small one which takes some small value, and a | |
938 | larger one which takes a 16 bit value. Since branches also follow | |
939 | this pattern, relaxing these values is required. | |
940 | ||
941 | We can assemble both mips16 and normal MIPS code in a single | |
942 | object. Therefore, we need to support this type of relaxation at | |
943 | the same time that we support the relaxation described above. We | |
944 | use the high bit of the subtype field to distinguish these cases. | |
945 | ||
946 | The information we store for this type of relaxation is the | |
947 | argument code found in the opcode file for this relocation, whether | |
948 | the user explicitly requested a small or extended form, and whether | |
949 | the relocation is in a jump or jal delay slot. That tells us the | |
950 | size of the value, and how it should be stored. We also store | |
951 | whether the fragment is considered to be extended or not. We also | |
952 | store whether this is known to be a branch to a different section, | |
953 | whether we have tried to relax this frag yet, and whether we have | |
954 | ever extended a PC relative fragment because of a shift count. */ | |
955 | #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \ | |
956 | (0x80000000 \ | |
957 | | ((type) & 0xff) \ | |
958 | | ((small) ? 0x100 : 0) \ | |
959 | | ((ext) ? 0x200 : 0) \ | |
960 | | ((dslot) ? 0x400 : 0) \ | |
961 | | ((jal_dslot) ? 0x800 : 0)) | |
4a6a3df4 | 962 | #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000) |
252b5132 RH |
963 | #define RELAX_MIPS16_TYPE(i) ((i) & 0xff) |
964 | #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0) | |
965 | #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0) | |
966 | #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0) | |
967 | #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0) | |
968 | #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0) | |
969 | #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000) | |
970 | #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000) | |
971 | #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0) | |
972 | #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000) | |
973 | #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000) | |
885add95 CD |
974 | |
975 | /* Is the given value a sign-extended 32-bit value? */ | |
976 | #define IS_SEXT_32BIT_NUM(x) \ | |
977 | (((x) &~ (offsetT) 0x7fffffff) == 0 \ | |
978 | || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff)) | |
979 | ||
980 | /* Is the given value a sign-extended 16-bit value? */ | |
981 | #define IS_SEXT_16BIT_NUM(x) \ | |
982 | (((x) &~ (offsetT) 0x7fff) == 0 \ | |
983 | || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff)) | |
984 | ||
2051e8c4 MR |
985 | /* Is the given value a zero-extended 32-bit value? Or a negated one? */ |
986 | #define IS_ZEXT_32BIT_NUM(x) \ | |
987 | (((x) &~ (offsetT) 0xffffffff) == 0 \ | |
988 | || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff)) | |
989 | ||
bf12938e RS |
990 | /* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in |
991 | VALUE << SHIFT. VALUE is evaluated exactly once. */ | |
992 | #define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \ | |
993 | (STRUCT) = (((STRUCT) & ~((MASK) << (SHIFT))) \ | |
994 | | (((VALUE) & (MASK)) << (SHIFT))) | |
995 | ||
996 | /* Extract bits MASK << SHIFT from STRUCT and shift them right | |
997 | SHIFT places. */ | |
998 | #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \ | |
999 | (((STRUCT) >> (SHIFT)) & (MASK)) | |
1000 | ||
1001 | /* Change INSN's opcode so that the operand given by FIELD has value VALUE. | |
1002 | INSN is a mips_cl_insn structure and VALUE is evaluated exactly once. | |
1003 | ||
1004 | include/opcode/mips.h specifies operand fields using the macros | |
1005 | OP_MASK_<FIELD> and OP_SH_<FIELD>. The MIPS16 equivalents start | |
1006 | with "MIPS16OP" instead of "OP". */ | |
1007 | #define INSERT_OPERAND(FIELD, INSN, VALUE) \ | |
1008 | INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD) | |
1009 | #define MIPS16_INSERT_OPERAND(FIELD, INSN, VALUE) \ | |
1010 | INSERT_BITS ((INSN).insn_opcode, VALUE, \ | |
1011 | MIPS16OP_MASK_##FIELD, MIPS16OP_SH_##FIELD) | |
1012 | ||
1013 | /* Extract the operand given by FIELD from mips_cl_insn INSN. */ | |
1014 | #define EXTRACT_OPERAND(FIELD, INSN) \ | |
1015 | EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) | |
1016 | #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \ | |
1017 | EXTRACT_BITS ((INSN).insn_opcode, \ | |
1018 | MIPS16OP_MASK_##FIELD, \ | |
1019 | MIPS16OP_SH_##FIELD) | |
4d7206a2 RS |
1020 | \f |
1021 | /* Global variables used when generating relaxable macros. See the | |
1022 | comment above RELAX_ENCODE for more details about how relaxation | |
1023 | is used. */ | |
1024 | static struct { | |
1025 | /* 0 if we're not emitting a relaxable macro. | |
1026 | 1 if we're emitting the first of the two relaxation alternatives. | |
1027 | 2 if we're emitting the second alternative. */ | |
1028 | int sequence; | |
1029 | ||
1030 | /* The first relaxable fixup in the current frag. (In other words, | |
1031 | the first fixup that refers to relaxable code.) */ | |
1032 | fixS *first_fixup; | |
1033 | ||
1034 | /* sizes[0] says how many bytes of the first alternative are stored in | |
1035 | the current frag. Likewise sizes[1] for the second alternative. */ | |
1036 | unsigned int sizes[2]; | |
1037 | ||
1038 | /* The symbol on which the choice of sequence depends. */ | |
1039 | symbolS *symbol; | |
1040 | } mips_relax; | |
252b5132 | 1041 | \f |
584892a6 RS |
1042 | /* Global variables used to decide whether a macro needs a warning. */ |
1043 | static struct { | |
1044 | /* True if the macro is in a branch delay slot. */ | |
1045 | bfd_boolean delay_slot_p; | |
1046 | ||
1047 | /* For relaxable macros, sizes[0] is the length of the first alternative | |
1048 | in bytes and sizes[1] is the length of the second alternative. | |
1049 | For non-relaxable macros, both elements give the length of the | |
1050 | macro in bytes. */ | |
1051 | unsigned int sizes[2]; | |
1052 | ||
1053 | /* The first variant frag for this macro. */ | |
1054 | fragS *first_frag; | |
1055 | } mips_macro_warning; | |
1056 | \f | |
252b5132 RH |
1057 | /* Prototypes for static functions. */ |
1058 | ||
17a2f251 | 1059 | #define internalError() \ |
252b5132 | 1060 | as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__) |
252b5132 RH |
1061 | |
1062 | enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG }; | |
1063 | ||
b34976b6 | 1064 | static void append_insn |
c67a084a | 1065 | (struct mips_cl_insn *, expressionS *, bfd_reloc_code_real_type *); |
7d10b47d | 1066 | static void mips_no_prev_insn (void); |
c67a084a | 1067 | static void macro_build (expressionS *, const char *, const char *, ...); |
b34976b6 | 1068 | static void mips16_macro_build |
03ea81db | 1069 | (expressionS *, const char *, const char *, va_list *); |
67c0d1eb | 1070 | static void load_register (int, expressionS *, int); |
584892a6 RS |
1071 | static void macro_start (void); |
1072 | static void macro_end (void); | |
17a2f251 TS |
1073 | static void macro (struct mips_cl_insn * ip); |
1074 | static void mips16_macro (struct mips_cl_insn * ip); | |
17a2f251 TS |
1075 | static void mips_ip (char *str, struct mips_cl_insn * ip); |
1076 | static void mips16_ip (char *str, struct mips_cl_insn * ip); | |
b34976b6 | 1077 | static void mips16_immed |
17a2f251 TS |
1078 | (char *, unsigned int, int, offsetT, bfd_boolean, bfd_boolean, bfd_boolean, |
1079 | unsigned long *, bfd_boolean *, unsigned short *); | |
5e0116d5 | 1080 | static size_t my_getSmallExpression |
17a2f251 TS |
1081 | (expressionS *, bfd_reloc_code_real_type *, char *); |
1082 | static void my_getExpression (expressionS *, char *); | |
1083 | static void s_align (int); | |
1084 | static void s_change_sec (int); | |
1085 | static void s_change_section (int); | |
1086 | static void s_cons (int); | |
1087 | static void s_float_cons (int); | |
1088 | static void s_mips_globl (int); | |
1089 | static void s_option (int); | |
1090 | static void s_mipsset (int); | |
1091 | static void s_abicalls (int); | |
1092 | static void s_cpload (int); | |
1093 | static void s_cpsetup (int); | |
1094 | static void s_cplocal (int); | |
1095 | static void s_cprestore (int); | |
1096 | static void s_cpreturn (int); | |
741d6ea8 JM |
1097 | static void s_dtprelword (int); |
1098 | static void s_dtpreldword (int); | |
17a2f251 TS |
1099 | static void s_gpvalue (int); |
1100 | static void s_gpword (int); | |
1101 | static void s_gpdword (int); | |
1102 | static void s_cpadd (int); | |
1103 | static void s_insn (int); | |
1104 | static void md_obj_begin (void); | |
1105 | static void md_obj_end (void); | |
1106 | static void s_mips_ent (int); | |
1107 | static void s_mips_end (int); | |
1108 | static void s_mips_frame (int); | |
1109 | static void s_mips_mask (int reg_type); | |
1110 | static void s_mips_stab (int); | |
1111 | static void s_mips_weakext (int); | |
1112 | static void s_mips_file (int); | |
1113 | static void s_mips_loc (int); | |
1114 | static bfd_boolean pic_need_relax (symbolS *, asection *); | |
4a6a3df4 | 1115 | static int relaxed_branch_length (fragS *, asection *, int); |
17a2f251 | 1116 | static int validate_mips_insn (const struct mips_opcode *); |
e7af610e NC |
1117 | |
1118 | /* Table and functions used to map between CPU/ISA names, and | |
1119 | ISA levels, and CPU numbers. */ | |
1120 | ||
e972090a NC |
1121 | struct mips_cpu_info |
1122 | { | |
e7af610e | 1123 | const char *name; /* CPU or ISA name. */ |
ad3fea08 | 1124 | int flags; /* ASEs available, or ISA flag. */ |
e7af610e NC |
1125 | int isa; /* ISA level. */ |
1126 | int cpu; /* CPU number (default CPU if ISA). */ | |
1127 | }; | |
1128 | ||
ad3fea08 TS |
1129 | #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */ |
1130 | #define MIPS_CPU_ASE_SMARTMIPS 0x0002 /* CPU implements SmartMIPS ASE */ | |
1131 | #define MIPS_CPU_ASE_DSP 0x0004 /* CPU implements DSP ASE */ | |
1132 | #define MIPS_CPU_ASE_MT 0x0008 /* CPU implements MT ASE */ | |
1133 | #define MIPS_CPU_ASE_MIPS3D 0x0010 /* CPU implements MIPS-3D ASE */ | |
1134 | #define MIPS_CPU_ASE_MDMX 0x0020 /* CPU implements MDMX ASE */ | |
8b082fb1 | 1135 | #define MIPS_CPU_ASE_DSPR2 0x0040 /* CPU implements DSP R2 ASE */ |
ad3fea08 | 1136 | |
17a2f251 TS |
1137 | static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *); |
1138 | static const struct mips_cpu_info *mips_cpu_info_from_isa (int); | |
1139 | static const struct mips_cpu_info *mips_cpu_info_from_arch (int); | |
252b5132 RH |
1140 | \f |
1141 | /* Pseudo-op table. | |
1142 | ||
1143 | The following pseudo-ops from the Kane and Heinrich MIPS book | |
1144 | should be defined here, but are currently unsupported: .alias, | |
1145 | .galive, .gjaldef, .gjrlive, .livereg, .noalias. | |
1146 | ||
1147 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
1148 | specific to the type of debugging information being generated, and | |
1149 | should be defined by the object format: .aent, .begin, .bend, | |
1150 | .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp, | |
1151 | .vreg. | |
1152 | ||
1153 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
1154 | not MIPS CPU specific, but are also not specific to the object file | |
1155 | format. This file is probably the best place to define them, but | |
d84bcf09 | 1156 | they are not currently supported: .asm0, .endr, .lab, .struct. */ |
252b5132 | 1157 | |
e972090a NC |
1158 | static const pseudo_typeS mips_pseudo_table[] = |
1159 | { | |
beae10d5 | 1160 | /* MIPS specific pseudo-ops. */ |
252b5132 RH |
1161 | {"option", s_option, 0}, |
1162 | {"set", s_mipsset, 0}, | |
1163 | {"rdata", s_change_sec, 'r'}, | |
1164 | {"sdata", s_change_sec, 's'}, | |
1165 | {"livereg", s_ignore, 0}, | |
1166 | {"abicalls", s_abicalls, 0}, | |
1167 | {"cpload", s_cpload, 0}, | |
6478892d TS |
1168 | {"cpsetup", s_cpsetup, 0}, |
1169 | {"cplocal", s_cplocal, 0}, | |
252b5132 | 1170 | {"cprestore", s_cprestore, 0}, |
6478892d | 1171 | {"cpreturn", s_cpreturn, 0}, |
741d6ea8 JM |
1172 | {"dtprelword", s_dtprelword, 0}, |
1173 | {"dtpreldword", s_dtpreldword, 0}, | |
6478892d | 1174 | {"gpvalue", s_gpvalue, 0}, |
252b5132 | 1175 | {"gpword", s_gpword, 0}, |
10181a0d | 1176 | {"gpdword", s_gpdword, 0}, |
252b5132 RH |
1177 | {"cpadd", s_cpadd, 0}, |
1178 | {"insn", s_insn, 0}, | |
1179 | ||
beae10d5 | 1180 | /* Relatively generic pseudo-ops that happen to be used on MIPS |
252b5132 | 1181 | chips. */ |
38a57ae7 | 1182 | {"asciiz", stringer, 8 + 1}, |
252b5132 RH |
1183 | {"bss", s_change_sec, 'b'}, |
1184 | {"err", s_err, 0}, | |
1185 | {"half", s_cons, 1}, | |
1186 | {"dword", s_cons, 3}, | |
1187 | {"weakext", s_mips_weakext, 0}, | |
7c752c2a TS |
1188 | {"origin", s_org, 0}, |
1189 | {"repeat", s_rept, 0}, | |
252b5132 | 1190 | |
998b3c36 MR |
1191 | /* For MIPS this is non-standard, but we define it for consistency. */ |
1192 | {"sbss", s_change_sec, 'B'}, | |
1193 | ||
beae10d5 | 1194 | /* These pseudo-ops are defined in read.c, but must be overridden |
252b5132 RH |
1195 | here for one reason or another. */ |
1196 | {"align", s_align, 0}, | |
1197 | {"byte", s_cons, 0}, | |
1198 | {"data", s_change_sec, 'd'}, | |
1199 | {"double", s_float_cons, 'd'}, | |
1200 | {"float", s_float_cons, 'f'}, | |
1201 | {"globl", s_mips_globl, 0}, | |
1202 | {"global", s_mips_globl, 0}, | |
1203 | {"hword", s_cons, 1}, | |
1204 | {"int", s_cons, 2}, | |
1205 | {"long", s_cons, 2}, | |
1206 | {"octa", s_cons, 4}, | |
1207 | {"quad", s_cons, 3}, | |
cca86cc8 | 1208 | {"section", s_change_section, 0}, |
252b5132 RH |
1209 | {"short", s_cons, 1}, |
1210 | {"single", s_float_cons, 'f'}, | |
1211 | {"stabn", s_mips_stab, 'n'}, | |
1212 | {"text", s_change_sec, 't'}, | |
1213 | {"word", s_cons, 2}, | |
add56521 | 1214 | |
add56521 | 1215 | { "extern", ecoff_directive_extern, 0}, |
add56521 | 1216 | |
43841e91 | 1217 | { NULL, NULL, 0 }, |
252b5132 RH |
1218 | }; |
1219 | ||
e972090a NC |
1220 | static const pseudo_typeS mips_nonecoff_pseudo_table[] = |
1221 | { | |
beae10d5 KH |
1222 | /* These pseudo-ops should be defined by the object file format. |
1223 | However, a.out doesn't support them, so we have versions here. */ | |
252b5132 RH |
1224 | {"aent", s_mips_ent, 1}, |
1225 | {"bgnb", s_ignore, 0}, | |
1226 | {"end", s_mips_end, 0}, | |
1227 | {"endb", s_ignore, 0}, | |
1228 | {"ent", s_mips_ent, 0}, | |
c5dd6aab | 1229 | {"file", s_mips_file, 0}, |
252b5132 RH |
1230 | {"fmask", s_mips_mask, 'F'}, |
1231 | {"frame", s_mips_frame, 0}, | |
c5dd6aab | 1232 | {"loc", s_mips_loc, 0}, |
252b5132 RH |
1233 | {"mask", s_mips_mask, 'R'}, |
1234 | {"verstamp", s_ignore, 0}, | |
43841e91 | 1235 | { NULL, NULL, 0 }, |
252b5132 RH |
1236 | }; |
1237 | ||
17a2f251 | 1238 | extern void pop_insert (const pseudo_typeS *); |
252b5132 RH |
1239 | |
1240 | void | |
17a2f251 | 1241 | mips_pop_insert (void) |
252b5132 RH |
1242 | { |
1243 | pop_insert (mips_pseudo_table); | |
1244 | if (! ECOFF_DEBUGGING) | |
1245 | pop_insert (mips_nonecoff_pseudo_table); | |
1246 | } | |
1247 | \f | |
1248 | /* Symbols labelling the current insn. */ | |
1249 | ||
e972090a NC |
1250 | struct insn_label_list |
1251 | { | |
252b5132 RH |
1252 | struct insn_label_list *next; |
1253 | symbolS *label; | |
1254 | }; | |
1255 | ||
252b5132 | 1256 | static struct insn_label_list *free_insn_labels; |
742a56fe | 1257 | #define label_list tc_segment_info_data.labels |
252b5132 | 1258 | |
17a2f251 | 1259 | static void mips_clear_insn_labels (void); |
252b5132 RH |
1260 | |
1261 | static inline void | |
17a2f251 | 1262 | mips_clear_insn_labels (void) |
252b5132 RH |
1263 | { |
1264 | register struct insn_label_list **pl; | |
a8dbcb85 | 1265 | segment_info_type *si; |
252b5132 | 1266 | |
a8dbcb85 TS |
1267 | if (now_seg) |
1268 | { | |
1269 | for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next) | |
1270 | ; | |
1271 | ||
1272 | si = seg_info (now_seg); | |
1273 | *pl = si->label_list; | |
1274 | si->label_list = NULL; | |
1275 | } | |
252b5132 | 1276 | } |
a8dbcb85 | 1277 | |
252b5132 RH |
1278 | \f |
1279 | static char *expr_end; | |
1280 | ||
1281 | /* Expressions which appear in instructions. These are set by | |
1282 | mips_ip. */ | |
1283 | ||
1284 | static expressionS imm_expr; | |
5f74bc13 | 1285 | static expressionS imm2_expr; |
252b5132 RH |
1286 | static expressionS offset_expr; |
1287 | ||
1288 | /* Relocs associated with imm_expr and offset_expr. */ | |
1289 | ||
f6688943 TS |
1290 | static bfd_reloc_code_real_type imm_reloc[3] |
1291 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
1292 | static bfd_reloc_code_real_type offset_reloc[3] | |
1293 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 1294 | |
252b5132 RH |
1295 | /* These are set by mips16_ip if an explicit extension is used. */ |
1296 | ||
b34976b6 | 1297 | static bfd_boolean mips16_small, mips16_ext; |
252b5132 | 1298 | |
7ed4a06a | 1299 | #ifdef OBJ_ELF |
ecb4347a DJ |
1300 | /* The pdr segment for per procedure frame/regmask info. Not used for |
1301 | ECOFF debugging. */ | |
252b5132 RH |
1302 | |
1303 | static segT pdr_seg; | |
7ed4a06a | 1304 | #endif |
252b5132 | 1305 | |
e013f690 TS |
1306 | /* The default target format to use. */ |
1307 | ||
1308 | const char * | |
17a2f251 | 1309 | mips_target_format (void) |
e013f690 TS |
1310 | { |
1311 | switch (OUTPUT_FLAVOR) | |
1312 | { | |
e013f690 TS |
1313 | case bfd_target_ecoff_flavour: |
1314 | return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT; | |
1315 | case bfd_target_coff_flavour: | |
1316 | return "pe-mips"; | |
1317 | case bfd_target_elf_flavour: | |
0a44bf69 RS |
1318 | #ifdef TE_VXWORKS |
1319 | if (!HAVE_64BIT_OBJECTS && !HAVE_NEWABI) | |
1320 | return (target_big_endian | |
1321 | ? "elf32-bigmips-vxworks" | |
1322 | : "elf32-littlemips-vxworks"); | |
1323 | #endif | |
e013f690 | 1324 | #ifdef TE_TMIPS |
cfe86eaa | 1325 | /* This is traditional mips. */ |
e013f690 | 1326 | return (target_big_endian |
cfe86eaa TS |
1327 | ? (HAVE_64BIT_OBJECTS |
1328 | ? "elf64-tradbigmips" | |
1329 | : (HAVE_NEWABI | |
1330 | ? "elf32-ntradbigmips" : "elf32-tradbigmips")) | |
1331 | : (HAVE_64BIT_OBJECTS | |
1332 | ? "elf64-tradlittlemips" | |
1333 | : (HAVE_NEWABI | |
1334 | ? "elf32-ntradlittlemips" : "elf32-tradlittlemips"))); | |
e013f690 TS |
1335 | #else |
1336 | return (target_big_endian | |
cfe86eaa TS |
1337 | ? (HAVE_64BIT_OBJECTS |
1338 | ? "elf64-bigmips" | |
1339 | : (HAVE_NEWABI | |
1340 | ? "elf32-nbigmips" : "elf32-bigmips")) | |
1341 | : (HAVE_64BIT_OBJECTS | |
1342 | ? "elf64-littlemips" | |
1343 | : (HAVE_NEWABI | |
1344 | ? "elf32-nlittlemips" : "elf32-littlemips"))); | |
e013f690 TS |
1345 | #endif |
1346 | default: | |
1347 | abort (); | |
1348 | return NULL; | |
1349 | } | |
1350 | } | |
1351 | ||
1e915849 RS |
1352 | /* Return the length of instruction INSN. */ |
1353 | ||
1354 | static inline unsigned int | |
1355 | insn_length (const struct mips_cl_insn *insn) | |
1356 | { | |
1357 | if (!mips_opts.mips16) | |
1358 | return 4; | |
1359 | return insn->mips16_absolute_jump_p || insn->use_extend ? 4 : 2; | |
1360 | } | |
1361 | ||
1362 | /* Initialise INSN from opcode entry MO. Leave its position unspecified. */ | |
1363 | ||
1364 | static void | |
1365 | create_insn (struct mips_cl_insn *insn, const struct mips_opcode *mo) | |
1366 | { | |
1367 | size_t i; | |
1368 | ||
1369 | insn->insn_mo = mo; | |
1370 | insn->use_extend = FALSE; | |
1371 | insn->extend = 0; | |
1372 | insn->insn_opcode = mo->match; | |
1373 | insn->frag = NULL; | |
1374 | insn->where = 0; | |
1375 | for (i = 0; i < ARRAY_SIZE (insn->fixp); i++) | |
1376 | insn->fixp[i] = NULL; | |
1377 | insn->fixed_p = (mips_opts.noreorder > 0); | |
1378 | insn->noreorder_p = (mips_opts.noreorder > 0); | |
1379 | insn->mips16_absolute_jump_p = 0; | |
1380 | } | |
1381 | ||
742a56fe RS |
1382 | /* Record the current MIPS16 mode in now_seg. */ |
1383 | ||
1384 | static void | |
1385 | mips_record_mips16_mode (void) | |
1386 | { | |
1387 | segment_info_type *si; | |
1388 | ||
1389 | si = seg_info (now_seg); | |
1390 | if (si->tc_segment_info_data.mips16 != mips_opts.mips16) | |
1391 | si->tc_segment_info_data.mips16 = mips_opts.mips16; | |
1392 | } | |
1393 | ||
1e915849 RS |
1394 | /* Install INSN at the location specified by its "frag" and "where" fields. */ |
1395 | ||
1396 | static void | |
1397 | install_insn (const struct mips_cl_insn *insn) | |
1398 | { | |
1399 | char *f = insn->frag->fr_literal + insn->where; | |
1400 | if (!mips_opts.mips16) | |
1401 | md_number_to_chars (f, insn->insn_opcode, 4); | |
1402 | else if (insn->mips16_absolute_jump_p) | |
1403 | { | |
1404 | md_number_to_chars (f, insn->insn_opcode >> 16, 2); | |
1405 | md_number_to_chars (f + 2, insn->insn_opcode & 0xffff, 2); | |
1406 | } | |
1407 | else | |
1408 | { | |
1409 | if (insn->use_extend) | |
1410 | { | |
1411 | md_number_to_chars (f, 0xf000 | insn->extend, 2); | |
1412 | f += 2; | |
1413 | } | |
1414 | md_number_to_chars (f, insn->insn_opcode, 2); | |
1415 | } | |
742a56fe | 1416 | mips_record_mips16_mode (); |
1e915849 RS |
1417 | } |
1418 | ||
1419 | /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly | |
1420 | and install the opcode in the new location. */ | |
1421 | ||
1422 | static void | |
1423 | move_insn (struct mips_cl_insn *insn, fragS *frag, long where) | |
1424 | { | |
1425 | size_t i; | |
1426 | ||
1427 | insn->frag = frag; | |
1428 | insn->where = where; | |
1429 | for (i = 0; i < ARRAY_SIZE (insn->fixp); i++) | |
1430 | if (insn->fixp[i] != NULL) | |
1431 | { | |
1432 | insn->fixp[i]->fx_frag = frag; | |
1433 | insn->fixp[i]->fx_where = where; | |
1434 | } | |
1435 | install_insn (insn); | |
1436 | } | |
1437 | ||
1438 | /* Add INSN to the end of the output. */ | |
1439 | ||
1440 | static void | |
1441 | add_fixed_insn (struct mips_cl_insn *insn) | |
1442 | { | |
1443 | char *f = frag_more (insn_length (insn)); | |
1444 | move_insn (insn, frag_now, f - frag_now->fr_literal); | |
1445 | } | |
1446 | ||
1447 | /* Start a variant frag and move INSN to the start of the variant part, | |
1448 | marking it as fixed. The other arguments are as for frag_var. */ | |
1449 | ||
1450 | static void | |
1451 | add_relaxed_insn (struct mips_cl_insn *insn, int max_chars, int var, | |
1452 | relax_substateT subtype, symbolS *symbol, offsetT offset) | |
1453 | { | |
1454 | frag_grow (max_chars); | |
1455 | move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal); | |
1456 | insn->fixed_p = 1; | |
1457 | frag_var (rs_machine_dependent, max_chars, var, | |
1458 | subtype, symbol, offset, NULL); | |
1459 | } | |
1460 | ||
1461 | /* Insert N copies of INSN into the history buffer, starting at | |
1462 | position FIRST. Neither FIRST nor N need to be clipped. */ | |
1463 | ||
1464 | static void | |
1465 | insert_into_history (unsigned int first, unsigned int n, | |
1466 | const struct mips_cl_insn *insn) | |
1467 | { | |
1468 | if (mips_relax.sequence != 2) | |
1469 | { | |
1470 | unsigned int i; | |
1471 | ||
1472 | for (i = ARRAY_SIZE (history); i-- > first;) | |
1473 | if (i >= first + n) | |
1474 | history[i] = history[i - n]; | |
1475 | else | |
1476 | history[i] = *insn; | |
1477 | } | |
1478 | } | |
1479 | ||
1480 | /* Emit a nop instruction, recording it in the history buffer. */ | |
1481 | ||
1482 | static void | |
1483 | emit_nop (void) | |
1484 | { | |
1485 | add_fixed_insn (NOP_INSN); | |
1486 | insert_into_history (0, 1, NOP_INSN); | |
1487 | } | |
1488 | ||
71400594 RS |
1489 | /* Initialize vr4120_conflicts. There is a bit of duplication here: |
1490 | the idea is to make it obvious at a glance that each errata is | |
1491 | included. */ | |
1492 | ||
1493 | static void | |
1494 | init_vr4120_conflicts (void) | |
1495 | { | |
1496 | #define CONFLICT(FIRST, SECOND) \ | |
1497 | vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND | |
1498 | ||
1499 | /* Errata 21 - [D]DIV[U] after [D]MACC */ | |
1500 | CONFLICT (MACC, DIV); | |
1501 | CONFLICT (DMACC, DIV); | |
1502 | ||
1503 | /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */ | |
1504 | CONFLICT (DMULT, DMULT); | |
1505 | CONFLICT (DMULT, DMACC); | |
1506 | CONFLICT (DMACC, DMULT); | |
1507 | CONFLICT (DMACC, DMACC); | |
1508 | ||
1509 | /* Errata 24 - MT{LO,HI} after [D]MACC */ | |
1510 | CONFLICT (MACC, MTHILO); | |
1511 | CONFLICT (DMACC, MTHILO); | |
1512 | ||
1513 | /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU | |
1514 | instruction is executed immediately after a MACC or DMACC | |
1515 | instruction, the result of [either instruction] is incorrect." */ | |
1516 | CONFLICT (MACC, MULT); | |
1517 | CONFLICT (MACC, DMULT); | |
1518 | CONFLICT (DMACC, MULT); | |
1519 | CONFLICT (DMACC, DMULT); | |
1520 | ||
1521 | /* VR4181A errata MD(4): "If a MACC or DMACC instruction is | |
1522 | executed immediately after a DMULT, DMULTU, DIV, DIVU, | |
1523 | DDIV or DDIVU instruction, the result of the MACC or | |
1524 | DMACC instruction is incorrect.". */ | |
1525 | CONFLICT (DMULT, MACC); | |
1526 | CONFLICT (DMULT, DMACC); | |
1527 | CONFLICT (DIV, MACC); | |
1528 | CONFLICT (DIV, DMACC); | |
1529 | ||
1530 | #undef CONFLICT | |
1531 | } | |
1532 | ||
707bfff6 TS |
1533 | struct regname { |
1534 | const char *name; | |
1535 | unsigned int num; | |
1536 | }; | |
1537 | ||
1538 | #define RTYPE_MASK 0x1ff00 | |
1539 | #define RTYPE_NUM 0x00100 | |
1540 | #define RTYPE_FPU 0x00200 | |
1541 | #define RTYPE_FCC 0x00400 | |
1542 | #define RTYPE_VEC 0x00800 | |
1543 | #define RTYPE_GP 0x01000 | |
1544 | #define RTYPE_CP0 0x02000 | |
1545 | #define RTYPE_PC 0x04000 | |
1546 | #define RTYPE_ACC 0x08000 | |
1547 | #define RTYPE_CCC 0x10000 | |
1548 | #define RNUM_MASK 0x000ff | |
1549 | #define RWARN 0x80000 | |
1550 | ||
1551 | #define GENERIC_REGISTER_NUMBERS \ | |
1552 | {"$0", RTYPE_NUM | 0}, \ | |
1553 | {"$1", RTYPE_NUM | 1}, \ | |
1554 | {"$2", RTYPE_NUM | 2}, \ | |
1555 | {"$3", RTYPE_NUM | 3}, \ | |
1556 | {"$4", RTYPE_NUM | 4}, \ | |
1557 | {"$5", RTYPE_NUM | 5}, \ | |
1558 | {"$6", RTYPE_NUM | 6}, \ | |
1559 | {"$7", RTYPE_NUM | 7}, \ | |
1560 | {"$8", RTYPE_NUM | 8}, \ | |
1561 | {"$9", RTYPE_NUM | 9}, \ | |
1562 | {"$10", RTYPE_NUM | 10}, \ | |
1563 | {"$11", RTYPE_NUM | 11}, \ | |
1564 | {"$12", RTYPE_NUM | 12}, \ | |
1565 | {"$13", RTYPE_NUM | 13}, \ | |
1566 | {"$14", RTYPE_NUM | 14}, \ | |
1567 | {"$15", RTYPE_NUM | 15}, \ | |
1568 | {"$16", RTYPE_NUM | 16}, \ | |
1569 | {"$17", RTYPE_NUM | 17}, \ | |
1570 | {"$18", RTYPE_NUM | 18}, \ | |
1571 | {"$19", RTYPE_NUM | 19}, \ | |
1572 | {"$20", RTYPE_NUM | 20}, \ | |
1573 | {"$21", RTYPE_NUM | 21}, \ | |
1574 | {"$22", RTYPE_NUM | 22}, \ | |
1575 | {"$23", RTYPE_NUM | 23}, \ | |
1576 | {"$24", RTYPE_NUM | 24}, \ | |
1577 | {"$25", RTYPE_NUM | 25}, \ | |
1578 | {"$26", RTYPE_NUM | 26}, \ | |
1579 | {"$27", RTYPE_NUM | 27}, \ | |
1580 | {"$28", RTYPE_NUM | 28}, \ | |
1581 | {"$29", RTYPE_NUM | 29}, \ | |
1582 | {"$30", RTYPE_NUM | 30}, \ | |
1583 | {"$31", RTYPE_NUM | 31} | |
1584 | ||
1585 | #define FPU_REGISTER_NAMES \ | |
1586 | {"$f0", RTYPE_FPU | 0}, \ | |
1587 | {"$f1", RTYPE_FPU | 1}, \ | |
1588 | {"$f2", RTYPE_FPU | 2}, \ | |
1589 | {"$f3", RTYPE_FPU | 3}, \ | |
1590 | {"$f4", RTYPE_FPU | 4}, \ | |
1591 | {"$f5", RTYPE_FPU | 5}, \ | |
1592 | {"$f6", RTYPE_FPU | 6}, \ | |
1593 | {"$f7", RTYPE_FPU | 7}, \ | |
1594 | {"$f8", RTYPE_FPU | 8}, \ | |
1595 | {"$f9", RTYPE_FPU | 9}, \ | |
1596 | {"$f10", RTYPE_FPU | 10}, \ | |
1597 | {"$f11", RTYPE_FPU | 11}, \ | |
1598 | {"$f12", RTYPE_FPU | 12}, \ | |
1599 | {"$f13", RTYPE_FPU | 13}, \ | |
1600 | {"$f14", RTYPE_FPU | 14}, \ | |
1601 | {"$f15", RTYPE_FPU | 15}, \ | |
1602 | {"$f16", RTYPE_FPU | 16}, \ | |
1603 | {"$f17", RTYPE_FPU | 17}, \ | |
1604 | {"$f18", RTYPE_FPU | 18}, \ | |
1605 | {"$f19", RTYPE_FPU | 19}, \ | |
1606 | {"$f20", RTYPE_FPU | 20}, \ | |
1607 | {"$f21", RTYPE_FPU | 21}, \ | |
1608 | {"$f22", RTYPE_FPU | 22}, \ | |
1609 | {"$f23", RTYPE_FPU | 23}, \ | |
1610 | {"$f24", RTYPE_FPU | 24}, \ | |
1611 | {"$f25", RTYPE_FPU | 25}, \ | |
1612 | {"$f26", RTYPE_FPU | 26}, \ | |
1613 | {"$f27", RTYPE_FPU | 27}, \ | |
1614 | {"$f28", RTYPE_FPU | 28}, \ | |
1615 | {"$f29", RTYPE_FPU | 29}, \ | |
1616 | {"$f30", RTYPE_FPU | 30}, \ | |
1617 | {"$f31", RTYPE_FPU | 31} | |
1618 | ||
1619 | #define FPU_CONDITION_CODE_NAMES \ | |
1620 | {"$fcc0", RTYPE_FCC | 0}, \ | |
1621 | {"$fcc1", RTYPE_FCC | 1}, \ | |
1622 | {"$fcc2", RTYPE_FCC | 2}, \ | |
1623 | {"$fcc3", RTYPE_FCC | 3}, \ | |
1624 | {"$fcc4", RTYPE_FCC | 4}, \ | |
1625 | {"$fcc5", RTYPE_FCC | 5}, \ | |
1626 | {"$fcc6", RTYPE_FCC | 6}, \ | |
1627 | {"$fcc7", RTYPE_FCC | 7} | |
1628 | ||
1629 | #define COPROC_CONDITION_CODE_NAMES \ | |
1630 | {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \ | |
1631 | {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \ | |
1632 | {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \ | |
1633 | {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \ | |
1634 | {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \ | |
1635 | {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \ | |
1636 | {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \ | |
1637 | {"$cc7", RTYPE_FCC | RTYPE_CCC | 7} | |
1638 | ||
1639 | #define N32N64_SYMBOLIC_REGISTER_NAMES \ | |
1640 | {"$a4", RTYPE_GP | 8}, \ | |
1641 | {"$a5", RTYPE_GP | 9}, \ | |
1642 | {"$a6", RTYPE_GP | 10}, \ | |
1643 | {"$a7", RTYPE_GP | 11}, \ | |
1644 | {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \ | |
1645 | {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \ | |
1646 | {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \ | |
1647 | {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \ | |
1648 | {"$t0", RTYPE_GP | 12}, \ | |
1649 | {"$t1", RTYPE_GP | 13}, \ | |
1650 | {"$t2", RTYPE_GP | 14}, \ | |
1651 | {"$t3", RTYPE_GP | 15} | |
1652 | ||
1653 | #define O32_SYMBOLIC_REGISTER_NAMES \ | |
1654 | {"$t0", RTYPE_GP | 8}, \ | |
1655 | {"$t1", RTYPE_GP | 9}, \ | |
1656 | {"$t2", RTYPE_GP | 10}, \ | |
1657 | {"$t3", RTYPE_GP | 11}, \ | |
1658 | {"$t4", RTYPE_GP | 12}, \ | |
1659 | {"$t5", RTYPE_GP | 13}, \ | |
1660 | {"$t6", RTYPE_GP | 14}, \ | |
1661 | {"$t7", RTYPE_GP | 15}, \ | |
1662 | {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \ | |
1663 | {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \ | |
1664 | {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \ | |
1665 | {"$ta3", RTYPE_GP | 15} /* alias for $t7 */ | |
1666 | ||
1667 | /* Remaining symbolic register names */ | |
1668 | #define SYMBOLIC_REGISTER_NAMES \ | |
1669 | {"$zero", RTYPE_GP | 0}, \ | |
1670 | {"$at", RTYPE_GP | 1}, \ | |
1671 | {"$AT", RTYPE_GP | 1}, \ | |
1672 | {"$v0", RTYPE_GP | 2}, \ | |
1673 | {"$v1", RTYPE_GP | 3}, \ | |
1674 | {"$a0", RTYPE_GP | 4}, \ | |
1675 | {"$a1", RTYPE_GP | 5}, \ | |
1676 | {"$a2", RTYPE_GP | 6}, \ | |
1677 | {"$a3", RTYPE_GP | 7}, \ | |
1678 | {"$s0", RTYPE_GP | 16}, \ | |
1679 | {"$s1", RTYPE_GP | 17}, \ | |
1680 | {"$s2", RTYPE_GP | 18}, \ | |
1681 | {"$s3", RTYPE_GP | 19}, \ | |
1682 | {"$s4", RTYPE_GP | 20}, \ | |
1683 | {"$s5", RTYPE_GP | 21}, \ | |
1684 | {"$s6", RTYPE_GP | 22}, \ | |
1685 | {"$s7", RTYPE_GP | 23}, \ | |
1686 | {"$t8", RTYPE_GP | 24}, \ | |
1687 | {"$t9", RTYPE_GP | 25}, \ | |
1688 | {"$k0", RTYPE_GP | 26}, \ | |
1689 | {"$kt0", RTYPE_GP | 26}, \ | |
1690 | {"$k1", RTYPE_GP | 27}, \ | |
1691 | {"$kt1", RTYPE_GP | 27}, \ | |
1692 | {"$gp", RTYPE_GP | 28}, \ | |
1693 | {"$sp", RTYPE_GP | 29}, \ | |
1694 | {"$s8", RTYPE_GP | 30}, \ | |
1695 | {"$fp", RTYPE_GP | 30}, \ | |
1696 | {"$ra", RTYPE_GP | 31} | |
1697 | ||
1698 | #define MIPS16_SPECIAL_REGISTER_NAMES \ | |
1699 | {"$pc", RTYPE_PC | 0} | |
1700 | ||
1701 | #define MDMX_VECTOR_REGISTER_NAMES \ | |
1702 | /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \ | |
1703 | /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \ | |
1704 | {"$v2", RTYPE_VEC | 2}, \ | |
1705 | {"$v3", RTYPE_VEC | 3}, \ | |
1706 | {"$v4", RTYPE_VEC | 4}, \ | |
1707 | {"$v5", RTYPE_VEC | 5}, \ | |
1708 | {"$v6", RTYPE_VEC | 6}, \ | |
1709 | {"$v7", RTYPE_VEC | 7}, \ | |
1710 | {"$v8", RTYPE_VEC | 8}, \ | |
1711 | {"$v9", RTYPE_VEC | 9}, \ | |
1712 | {"$v10", RTYPE_VEC | 10}, \ | |
1713 | {"$v11", RTYPE_VEC | 11}, \ | |
1714 | {"$v12", RTYPE_VEC | 12}, \ | |
1715 | {"$v13", RTYPE_VEC | 13}, \ | |
1716 | {"$v14", RTYPE_VEC | 14}, \ | |
1717 | {"$v15", RTYPE_VEC | 15}, \ | |
1718 | {"$v16", RTYPE_VEC | 16}, \ | |
1719 | {"$v17", RTYPE_VEC | 17}, \ | |
1720 | {"$v18", RTYPE_VEC | 18}, \ | |
1721 | {"$v19", RTYPE_VEC | 19}, \ | |
1722 | {"$v20", RTYPE_VEC | 20}, \ | |
1723 | {"$v21", RTYPE_VEC | 21}, \ | |
1724 | {"$v22", RTYPE_VEC | 22}, \ | |
1725 | {"$v23", RTYPE_VEC | 23}, \ | |
1726 | {"$v24", RTYPE_VEC | 24}, \ | |
1727 | {"$v25", RTYPE_VEC | 25}, \ | |
1728 | {"$v26", RTYPE_VEC | 26}, \ | |
1729 | {"$v27", RTYPE_VEC | 27}, \ | |
1730 | {"$v28", RTYPE_VEC | 28}, \ | |
1731 | {"$v29", RTYPE_VEC | 29}, \ | |
1732 | {"$v30", RTYPE_VEC | 30}, \ | |
1733 | {"$v31", RTYPE_VEC | 31} | |
1734 | ||
1735 | #define MIPS_DSP_ACCUMULATOR_NAMES \ | |
1736 | {"$ac0", RTYPE_ACC | 0}, \ | |
1737 | {"$ac1", RTYPE_ACC | 1}, \ | |
1738 | {"$ac2", RTYPE_ACC | 2}, \ | |
1739 | {"$ac3", RTYPE_ACC | 3} | |
1740 | ||
1741 | static const struct regname reg_names[] = { | |
1742 | GENERIC_REGISTER_NUMBERS, | |
1743 | FPU_REGISTER_NAMES, | |
1744 | FPU_CONDITION_CODE_NAMES, | |
1745 | COPROC_CONDITION_CODE_NAMES, | |
1746 | ||
1747 | /* The $txx registers depends on the abi, | |
1748 | these will be added later into the symbol table from | |
1749 | one of the tables below once mips_abi is set after | |
1750 | parsing of arguments from the command line. */ | |
1751 | SYMBOLIC_REGISTER_NAMES, | |
1752 | ||
1753 | MIPS16_SPECIAL_REGISTER_NAMES, | |
1754 | MDMX_VECTOR_REGISTER_NAMES, | |
1755 | MIPS_DSP_ACCUMULATOR_NAMES, | |
1756 | {0, 0} | |
1757 | }; | |
1758 | ||
1759 | static const struct regname reg_names_o32[] = { | |
1760 | O32_SYMBOLIC_REGISTER_NAMES, | |
1761 | {0, 0} | |
1762 | }; | |
1763 | ||
1764 | static const struct regname reg_names_n32n64[] = { | |
1765 | N32N64_SYMBOLIC_REGISTER_NAMES, | |
1766 | {0, 0} | |
1767 | }; | |
1768 | ||
1769 | static int | |
1770 | reg_lookup (char **s, unsigned int types, unsigned int *regnop) | |
1771 | { | |
1772 | symbolS *symbolP; | |
1773 | char *e; | |
1774 | char save_c; | |
1775 | int reg = -1; | |
1776 | ||
1777 | /* Find end of name. */ | |
1778 | e = *s; | |
1779 | if (is_name_beginner (*e)) | |
1780 | ++e; | |
1781 | while (is_part_of_name (*e)) | |
1782 | ++e; | |
1783 | ||
1784 | /* Terminate name. */ | |
1785 | save_c = *e; | |
1786 | *e = '\0'; | |
1787 | ||
1788 | /* Look for a register symbol. */ | |
1789 | if ((symbolP = symbol_find (*s)) && S_GET_SEGMENT (symbolP) == reg_section) | |
1790 | { | |
1791 | int r = S_GET_VALUE (symbolP); | |
1792 | if (r & types) | |
1793 | reg = r & RNUM_MASK; | |
1794 | else if ((types & RTYPE_VEC) && (r & ~1) == (RTYPE_GP | 2)) | |
1795 | /* Convert GP reg $v0/1 to MDMX reg $v0/1! */ | |
1796 | reg = (r & RNUM_MASK) - 2; | |
1797 | } | |
1798 | /* Else see if this is a register defined in an itbl entry. */ | |
1799 | else if ((types & RTYPE_GP) && itbl_have_entries) | |
1800 | { | |
1801 | char *n = *s; | |
1802 | unsigned long r; | |
1803 | ||
1804 | if (*n == '$') | |
1805 | ++n; | |
1806 | if (itbl_get_reg_val (n, &r)) | |
1807 | reg = r & RNUM_MASK; | |
1808 | } | |
1809 | ||
1810 | /* Advance to next token if a register was recognised. */ | |
1811 | if (reg >= 0) | |
1812 | *s = e; | |
1813 | else if (types & RWARN) | |
20203fb9 | 1814 | as_warn (_("Unrecognized register name `%s'"), *s); |
707bfff6 TS |
1815 | |
1816 | *e = save_c; | |
1817 | if (regnop) | |
1818 | *regnop = reg; | |
1819 | return reg >= 0; | |
1820 | } | |
1821 | ||
037b32b9 | 1822 | /* Return TRUE if opcode MO is valid on the currently selected ISA and |
f79e2745 | 1823 | architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */ |
037b32b9 AN |
1824 | |
1825 | static bfd_boolean | |
f79e2745 | 1826 | is_opcode_valid (const struct mips_opcode *mo) |
037b32b9 AN |
1827 | { |
1828 | int isa = mips_opts.isa; | |
1829 | int fp_s, fp_d; | |
1830 | ||
1831 | if (mips_opts.ase_mdmx) | |
1832 | isa |= INSN_MDMX; | |
1833 | if (mips_opts.ase_dsp) | |
1834 | isa |= INSN_DSP; | |
1835 | if (mips_opts.ase_dsp && ISA_SUPPORTS_DSP64_ASE) | |
1836 | isa |= INSN_DSP64; | |
1837 | if (mips_opts.ase_dspr2) | |
1838 | isa |= INSN_DSPR2; | |
1839 | if (mips_opts.ase_mt) | |
1840 | isa |= INSN_MT; | |
1841 | if (mips_opts.ase_mips3d) | |
1842 | isa |= INSN_MIPS3D; | |
1843 | if (mips_opts.ase_smartmips) | |
1844 | isa |= INSN_SMARTMIPS; | |
1845 | ||
b19e8a9b AN |
1846 | /* Don't accept instructions based on the ISA if the CPU does not implement |
1847 | all the coprocessor insns. */ | |
1848 | if (NO_ISA_COP (mips_opts.arch) | |
1849 | && COP_INSN (mo->pinfo)) | |
1850 | isa = 0; | |
1851 | ||
037b32b9 AN |
1852 | if (!OPCODE_IS_MEMBER (mo, isa, mips_opts.arch)) |
1853 | return FALSE; | |
1854 | ||
1855 | /* Check whether the instruction or macro requires single-precision or | |
1856 | double-precision floating-point support. Note that this information is | |
1857 | stored differently in the opcode table for insns and macros. */ | |
1858 | if (mo->pinfo == INSN_MACRO) | |
1859 | { | |
1860 | fp_s = mo->pinfo2 & INSN2_M_FP_S; | |
1861 | fp_d = mo->pinfo2 & INSN2_M_FP_D; | |
1862 | } | |
1863 | else | |
1864 | { | |
1865 | fp_s = mo->pinfo & FP_S; | |
1866 | fp_d = mo->pinfo & FP_D; | |
1867 | } | |
1868 | ||
1869 | if (fp_d && (mips_opts.soft_float || mips_opts.single_float)) | |
1870 | return FALSE; | |
1871 | ||
1872 | if (fp_s && mips_opts.soft_float) | |
1873 | return FALSE; | |
1874 | ||
1875 | return TRUE; | |
1876 | } | |
1877 | ||
1878 | /* Return TRUE if the MIPS16 opcode MO is valid on the currently | |
1879 | selected ISA and architecture. */ | |
1880 | ||
1881 | static bfd_boolean | |
1882 | is_opcode_valid_16 (const struct mips_opcode *mo) | |
1883 | { | |
1884 | return OPCODE_IS_MEMBER (mo, mips_opts.isa, mips_opts.arch) ? TRUE : FALSE; | |
1885 | } | |
1886 | ||
707bfff6 TS |
1887 | /* This function is called once, at assembler startup time. It should set up |
1888 | all the tables, etc. that the MD part of the assembler will need. */ | |
156c2f8b | 1889 | |
252b5132 | 1890 | void |
17a2f251 | 1891 | md_begin (void) |
252b5132 | 1892 | { |
3994f87e | 1893 | const char *retval = NULL; |
156c2f8b | 1894 | int i = 0; |
252b5132 | 1895 | int broken = 0; |
1f25f5d3 | 1896 | |
0a44bf69 RS |
1897 | if (mips_pic != NO_PIC) |
1898 | { | |
1899 | if (g_switch_seen && g_switch_value != 0) | |
1900 | as_bad (_("-G may not be used in position-independent code")); | |
1901 | g_switch_value = 0; | |
1902 | } | |
1903 | ||
fef14a42 | 1904 | if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_arch)) |
252b5132 RH |
1905 | as_warn (_("Could not set architecture and machine")); |
1906 | ||
252b5132 RH |
1907 | op_hash = hash_new (); |
1908 | ||
1909 | for (i = 0; i < NUMOPCODES;) | |
1910 | { | |
1911 | const char *name = mips_opcodes[i].name; | |
1912 | ||
17a2f251 | 1913 | retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]); |
252b5132 RH |
1914 | if (retval != NULL) |
1915 | { | |
1916 | fprintf (stderr, _("internal error: can't hash `%s': %s\n"), | |
1917 | mips_opcodes[i].name, retval); | |
1918 | /* Probably a memory allocation problem? Give up now. */ | |
1919 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
1920 | } | |
1921 | do | |
1922 | { | |
1923 | if (mips_opcodes[i].pinfo != INSN_MACRO) | |
1924 | { | |
1925 | if (!validate_mips_insn (&mips_opcodes[i])) | |
1926 | broken = 1; | |
1e915849 RS |
1927 | if (nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0) |
1928 | { | |
1929 | create_insn (&nop_insn, mips_opcodes + i); | |
c67a084a NC |
1930 | if (mips_fix_loongson2f_nop) |
1931 | nop_insn.insn_opcode = LOONGSON2F_NOP_INSN; | |
1e915849 RS |
1932 | nop_insn.fixed_p = 1; |
1933 | } | |
252b5132 RH |
1934 | } |
1935 | ++i; | |
1936 | } | |
1937 | while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name)); | |
1938 | } | |
1939 | ||
1940 | mips16_op_hash = hash_new (); | |
1941 | ||
1942 | i = 0; | |
1943 | while (i < bfd_mips16_num_opcodes) | |
1944 | { | |
1945 | const char *name = mips16_opcodes[i].name; | |
1946 | ||
17a2f251 | 1947 | retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]); |
252b5132 RH |
1948 | if (retval != NULL) |
1949 | as_fatal (_("internal: can't hash `%s': %s"), | |
1950 | mips16_opcodes[i].name, retval); | |
1951 | do | |
1952 | { | |
1953 | if (mips16_opcodes[i].pinfo != INSN_MACRO | |
1954 | && ((mips16_opcodes[i].match & mips16_opcodes[i].mask) | |
1955 | != mips16_opcodes[i].match)) | |
1956 | { | |
1957 | fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"), | |
1958 | mips16_opcodes[i].name, mips16_opcodes[i].args); | |
1959 | broken = 1; | |
1960 | } | |
1e915849 RS |
1961 | if (mips16_nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0) |
1962 | { | |
1963 | create_insn (&mips16_nop_insn, mips16_opcodes + i); | |
1964 | mips16_nop_insn.fixed_p = 1; | |
1965 | } | |
252b5132 RH |
1966 | ++i; |
1967 | } | |
1968 | while (i < bfd_mips16_num_opcodes | |
1969 | && strcmp (mips16_opcodes[i].name, name) == 0); | |
1970 | } | |
1971 | ||
1972 | if (broken) | |
1973 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
1974 | ||
1975 | /* We add all the general register names to the symbol table. This | |
1976 | helps us detect invalid uses of them. */ | |
707bfff6 TS |
1977 | for (i = 0; reg_names[i].name; i++) |
1978 | symbol_table_insert (symbol_new (reg_names[i].name, reg_section, | |
8fc4ee9b | 1979 | reg_names[i].num, /* & RNUM_MASK, */ |
707bfff6 TS |
1980 | &zero_address_frag)); |
1981 | if (HAVE_NEWABI) | |
1982 | for (i = 0; reg_names_n32n64[i].name; i++) | |
1983 | symbol_table_insert (symbol_new (reg_names_n32n64[i].name, reg_section, | |
8fc4ee9b | 1984 | reg_names_n32n64[i].num, /* & RNUM_MASK, */ |
252b5132 | 1985 | &zero_address_frag)); |
707bfff6 TS |
1986 | else |
1987 | for (i = 0; reg_names_o32[i].name; i++) | |
1988 | symbol_table_insert (symbol_new (reg_names_o32[i].name, reg_section, | |
8fc4ee9b | 1989 | reg_names_o32[i].num, /* & RNUM_MASK, */ |
6047c971 | 1990 | &zero_address_frag)); |
6047c971 | 1991 | |
7d10b47d | 1992 | mips_no_prev_insn (); |
252b5132 RH |
1993 | |
1994 | mips_gprmask = 0; | |
1995 | mips_cprmask[0] = 0; | |
1996 | mips_cprmask[1] = 0; | |
1997 | mips_cprmask[2] = 0; | |
1998 | mips_cprmask[3] = 0; | |
1999 | ||
2000 | /* set the default alignment for the text section (2**2) */ | |
2001 | record_alignment (text_section, 2); | |
2002 | ||
4d0d148d | 2003 | bfd_set_gp_size (stdoutput, g_switch_value); |
252b5132 | 2004 | |
707bfff6 | 2005 | #ifdef OBJ_ELF |
f43abd2b | 2006 | if (IS_ELF) |
252b5132 | 2007 | { |
0a44bf69 RS |
2008 | /* On a native system other than VxWorks, sections must be aligned |
2009 | to 16 byte boundaries. When configured for an embedded ELF | |
2010 | target, we don't bother. */ | |
c41e87e3 CF |
2011 | if (strncmp (TARGET_OS, "elf", 3) != 0 |
2012 | && strncmp (TARGET_OS, "vxworks", 7) != 0) | |
252b5132 RH |
2013 | { |
2014 | (void) bfd_set_section_alignment (stdoutput, text_section, 4); | |
2015 | (void) bfd_set_section_alignment (stdoutput, data_section, 4); | |
2016 | (void) bfd_set_section_alignment (stdoutput, bss_section, 4); | |
2017 | } | |
2018 | ||
2019 | /* Create a .reginfo section for register masks and a .mdebug | |
2020 | section for debugging information. */ | |
2021 | { | |
2022 | segT seg; | |
2023 | subsegT subseg; | |
2024 | flagword flags; | |
2025 | segT sec; | |
2026 | ||
2027 | seg = now_seg; | |
2028 | subseg = now_subseg; | |
2029 | ||
2030 | /* The ABI says this section should be loaded so that the | |
2031 | running program can access it. However, we don't load it | |
2032 | if we are configured for an embedded target */ | |
2033 | flags = SEC_READONLY | SEC_DATA; | |
c41e87e3 | 2034 | if (strncmp (TARGET_OS, "elf", 3) != 0) |
252b5132 RH |
2035 | flags |= SEC_ALLOC | SEC_LOAD; |
2036 | ||
316f5878 | 2037 | if (mips_abi != N64_ABI) |
252b5132 RH |
2038 | { |
2039 | sec = subseg_new (".reginfo", (subsegT) 0); | |
2040 | ||
195325d2 TS |
2041 | bfd_set_section_flags (stdoutput, sec, flags); |
2042 | bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2); | |
bdaaa2e1 | 2043 | |
252b5132 | 2044 | mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo)); |
252b5132 RH |
2045 | } |
2046 | else | |
2047 | { | |
2048 | /* The 64-bit ABI uses a .MIPS.options section rather than | |
2049 | .reginfo section. */ | |
2050 | sec = subseg_new (".MIPS.options", (subsegT) 0); | |
195325d2 TS |
2051 | bfd_set_section_flags (stdoutput, sec, flags); |
2052 | bfd_set_section_alignment (stdoutput, sec, 3); | |
252b5132 | 2053 | |
252b5132 RH |
2054 | /* Set up the option header. */ |
2055 | { | |
2056 | Elf_Internal_Options opthdr; | |
2057 | char *f; | |
2058 | ||
2059 | opthdr.kind = ODK_REGINFO; | |
2060 | opthdr.size = (sizeof (Elf_External_Options) | |
2061 | + sizeof (Elf64_External_RegInfo)); | |
2062 | opthdr.section = 0; | |
2063 | opthdr.info = 0; | |
2064 | f = frag_more (sizeof (Elf_External_Options)); | |
2065 | bfd_mips_elf_swap_options_out (stdoutput, &opthdr, | |
2066 | (Elf_External_Options *) f); | |
2067 | ||
2068 | mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo)); | |
2069 | } | |
252b5132 RH |
2070 | } |
2071 | ||
2072 | if (ECOFF_DEBUGGING) | |
2073 | { | |
2074 | sec = subseg_new (".mdebug", (subsegT) 0); | |
2075 | (void) bfd_set_section_flags (stdoutput, sec, | |
2076 | SEC_HAS_CONTENTS | SEC_READONLY); | |
2077 | (void) bfd_set_section_alignment (stdoutput, sec, 2); | |
2078 | } | |
f43abd2b | 2079 | else if (mips_flag_pdr) |
ecb4347a DJ |
2080 | { |
2081 | pdr_seg = subseg_new (".pdr", (subsegT) 0); | |
2082 | (void) bfd_set_section_flags (stdoutput, pdr_seg, | |
2083 | SEC_READONLY | SEC_RELOC | |
2084 | | SEC_DEBUGGING); | |
2085 | (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2); | |
2086 | } | |
252b5132 RH |
2087 | |
2088 | subseg_set (seg, subseg); | |
2089 | } | |
2090 | } | |
707bfff6 | 2091 | #endif /* OBJ_ELF */ |
252b5132 RH |
2092 | |
2093 | if (! ECOFF_DEBUGGING) | |
2094 | md_obj_begin (); | |
71400594 RS |
2095 | |
2096 | if (mips_fix_vr4120) | |
2097 | init_vr4120_conflicts (); | |
252b5132 RH |
2098 | } |
2099 | ||
2100 | void | |
17a2f251 | 2101 | md_mips_end (void) |
252b5132 RH |
2102 | { |
2103 | if (! ECOFF_DEBUGGING) | |
2104 | md_obj_end (); | |
2105 | } | |
2106 | ||
2107 | void | |
17a2f251 | 2108 | md_assemble (char *str) |
252b5132 RH |
2109 | { |
2110 | struct mips_cl_insn insn; | |
f6688943 TS |
2111 | bfd_reloc_code_real_type unused_reloc[3] |
2112 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 RH |
2113 | |
2114 | imm_expr.X_op = O_absent; | |
5f74bc13 | 2115 | imm2_expr.X_op = O_absent; |
252b5132 | 2116 | offset_expr.X_op = O_absent; |
f6688943 TS |
2117 | imm_reloc[0] = BFD_RELOC_UNUSED; |
2118 | imm_reloc[1] = BFD_RELOC_UNUSED; | |
2119 | imm_reloc[2] = BFD_RELOC_UNUSED; | |
2120 | offset_reloc[0] = BFD_RELOC_UNUSED; | |
2121 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
2122 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
2123 | |
2124 | if (mips_opts.mips16) | |
2125 | mips16_ip (str, &insn); | |
2126 | else | |
2127 | { | |
2128 | mips_ip (str, &insn); | |
beae10d5 KH |
2129 | DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"), |
2130 | str, insn.insn_opcode)); | |
252b5132 RH |
2131 | } |
2132 | ||
2133 | if (insn_error) | |
2134 | { | |
2135 | as_bad ("%s `%s'", insn_error, str); | |
2136 | return; | |
2137 | } | |
2138 | ||
2139 | if (insn.insn_mo->pinfo == INSN_MACRO) | |
2140 | { | |
584892a6 | 2141 | macro_start (); |
252b5132 RH |
2142 | if (mips_opts.mips16) |
2143 | mips16_macro (&insn); | |
2144 | else | |
2145 | macro (&insn); | |
584892a6 | 2146 | macro_end (); |
252b5132 RH |
2147 | } |
2148 | else | |
2149 | { | |
2150 | if (imm_expr.X_op != O_absent) | |
4d7206a2 | 2151 | append_insn (&insn, &imm_expr, imm_reloc); |
252b5132 | 2152 | else if (offset_expr.X_op != O_absent) |
4d7206a2 | 2153 | append_insn (&insn, &offset_expr, offset_reloc); |
252b5132 | 2154 | else |
4d7206a2 | 2155 | append_insn (&insn, NULL, unused_reloc); |
252b5132 RH |
2156 | } |
2157 | } | |
2158 | ||
738e5348 RS |
2159 | /* Convenience functions for abstracting away the differences between |
2160 | MIPS16 and non-MIPS16 relocations. */ | |
2161 | ||
2162 | static inline bfd_boolean | |
2163 | mips16_reloc_p (bfd_reloc_code_real_type reloc) | |
2164 | { | |
2165 | switch (reloc) | |
2166 | { | |
2167 | case BFD_RELOC_MIPS16_JMP: | |
2168 | case BFD_RELOC_MIPS16_GPREL: | |
2169 | case BFD_RELOC_MIPS16_GOT16: | |
2170 | case BFD_RELOC_MIPS16_CALL16: | |
2171 | case BFD_RELOC_MIPS16_HI16_S: | |
2172 | case BFD_RELOC_MIPS16_HI16: | |
2173 | case BFD_RELOC_MIPS16_LO16: | |
2174 | return TRUE; | |
2175 | ||
2176 | default: | |
2177 | return FALSE; | |
2178 | } | |
2179 | } | |
2180 | ||
2181 | static inline bfd_boolean | |
2182 | got16_reloc_p (bfd_reloc_code_real_type reloc) | |
2183 | { | |
2184 | return reloc == BFD_RELOC_MIPS_GOT16 || reloc == BFD_RELOC_MIPS16_GOT16; | |
2185 | } | |
2186 | ||
2187 | static inline bfd_boolean | |
2188 | hi16_reloc_p (bfd_reloc_code_real_type reloc) | |
2189 | { | |
2190 | return reloc == BFD_RELOC_HI16_S || reloc == BFD_RELOC_MIPS16_HI16_S; | |
2191 | } | |
2192 | ||
2193 | static inline bfd_boolean | |
2194 | lo16_reloc_p (bfd_reloc_code_real_type reloc) | |
2195 | { | |
2196 | return reloc == BFD_RELOC_LO16 || reloc == BFD_RELOC_MIPS16_LO16; | |
2197 | } | |
2198 | ||
5919d012 | 2199 | /* Return true if the given relocation might need a matching %lo(). |
0a44bf69 RS |
2200 | This is only "might" because SVR4 R_MIPS_GOT16 relocations only |
2201 | need a matching %lo() when applied to local symbols. */ | |
5919d012 RS |
2202 | |
2203 | static inline bfd_boolean | |
17a2f251 | 2204 | reloc_needs_lo_p (bfd_reloc_code_real_type reloc) |
5919d012 | 2205 | { |
3b91255e | 2206 | return (HAVE_IN_PLACE_ADDENDS |
738e5348 | 2207 | && (hi16_reloc_p (reloc) |
0a44bf69 RS |
2208 | /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo(); |
2209 | all GOT16 relocations evaluate to "G". */ | |
738e5348 RS |
2210 | || (got16_reloc_p (reloc) && mips_pic != VXWORKS_PIC))); |
2211 | } | |
2212 | ||
2213 | /* Return the type of %lo() reloc needed by RELOC, given that | |
2214 | reloc_needs_lo_p. */ | |
2215 | ||
2216 | static inline bfd_reloc_code_real_type | |
2217 | matching_lo_reloc (bfd_reloc_code_real_type reloc) | |
2218 | { | |
2219 | return mips16_reloc_p (reloc) ? BFD_RELOC_MIPS16_LO16 : BFD_RELOC_LO16; | |
5919d012 RS |
2220 | } |
2221 | ||
2222 | /* Return true if the given fixup is followed by a matching R_MIPS_LO16 | |
2223 | relocation. */ | |
2224 | ||
2225 | static inline bfd_boolean | |
17a2f251 | 2226 | fixup_has_matching_lo_p (fixS *fixp) |
5919d012 RS |
2227 | { |
2228 | return (fixp->fx_next != NULL | |
738e5348 | 2229 | && fixp->fx_next->fx_r_type == matching_lo_reloc (fixp->fx_r_type) |
5919d012 RS |
2230 | && fixp->fx_addsy == fixp->fx_next->fx_addsy |
2231 | && fixp->fx_offset == fixp->fx_next->fx_offset); | |
2232 | } | |
2233 | ||
252b5132 RH |
2234 | /* See whether instruction IP reads register REG. CLASS is the type |
2235 | of register. */ | |
2236 | ||
2237 | static int | |
71400594 | 2238 | insn_uses_reg (const struct mips_cl_insn *ip, unsigned int reg, |
96d56e9f | 2239 | enum mips_regclass regclass) |
252b5132 | 2240 | { |
96d56e9f | 2241 | if (regclass == MIPS16_REG) |
252b5132 | 2242 | { |
9c2799c2 | 2243 | gas_assert (mips_opts.mips16); |
252b5132 | 2244 | reg = mips16_to_32_reg_map[reg]; |
96d56e9f | 2245 | regclass = MIPS_GR_REG; |
252b5132 RH |
2246 | } |
2247 | ||
85b51719 | 2248 | /* Don't report on general register ZERO, since it never changes. */ |
96d56e9f | 2249 | if (regclass == MIPS_GR_REG && reg == ZERO) |
252b5132 RH |
2250 | return 0; |
2251 | ||
96d56e9f | 2252 | if (regclass == MIPS_FP_REG) |
252b5132 | 2253 | { |
9c2799c2 | 2254 | gas_assert (! mips_opts.mips16); |
252b5132 RH |
2255 | /* If we are called with either $f0 or $f1, we must check $f0. |
2256 | This is not optimal, because it will introduce an unnecessary | |
2257 | NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would | |
2258 | need to distinguish reading both $f0 and $f1 or just one of | |
2259 | them. Note that we don't have to check the other way, | |
2260 | because there is no instruction that sets both $f0 and $f1 | |
2261 | and requires a delay. */ | |
2262 | if ((ip->insn_mo->pinfo & INSN_READ_FPR_S) | |
bf12938e | 2263 | && ((EXTRACT_OPERAND (FS, *ip) & ~(unsigned) 1) |
252b5132 RH |
2264 | == (reg &~ (unsigned) 1))) |
2265 | return 1; | |
2266 | if ((ip->insn_mo->pinfo & INSN_READ_FPR_T) | |
bf12938e | 2267 | && ((EXTRACT_OPERAND (FT, *ip) & ~(unsigned) 1) |
252b5132 RH |
2268 | == (reg &~ (unsigned) 1))) |
2269 | return 1; | |
2270 | } | |
2271 | else if (! mips_opts.mips16) | |
2272 | { | |
2273 | if ((ip->insn_mo->pinfo & INSN_READ_GPR_S) | |
bf12938e | 2274 | && EXTRACT_OPERAND (RS, *ip) == reg) |
252b5132 RH |
2275 | return 1; |
2276 | if ((ip->insn_mo->pinfo & INSN_READ_GPR_T) | |
bf12938e | 2277 | && EXTRACT_OPERAND (RT, *ip) == reg) |
252b5132 RH |
2278 | return 1; |
2279 | } | |
2280 | else | |
2281 | { | |
2282 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_X) | |
bf12938e | 2283 | && mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, *ip)] == reg) |
252b5132 RH |
2284 | return 1; |
2285 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Y) | |
bf12938e | 2286 | && mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RY, *ip)] == reg) |
252b5132 RH |
2287 | return 1; |
2288 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Z) | |
bf12938e | 2289 | && (mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (MOVE32Z, *ip)] |
252b5132 RH |
2290 | == reg)) |
2291 | return 1; | |
2292 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_T) && reg == TREG) | |
2293 | return 1; | |
2294 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_SP) && reg == SP) | |
2295 | return 1; | |
2296 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_31) && reg == RA) | |
2297 | return 1; | |
2298 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_GPR_X) | |
bf12938e | 2299 | && MIPS16_EXTRACT_OPERAND (REGR32, *ip) == reg) |
252b5132 RH |
2300 | return 1; |
2301 | } | |
2302 | ||
2303 | return 0; | |
2304 | } | |
2305 | ||
2306 | /* This function returns true if modifying a register requires a | |
2307 | delay. */ | |
2308 | ||
2309 | static int | |
17a2f251 | 2310 | reg_needs_delay (unsigned int reg) |
252b5132 RH |
2311 | { |
2312 | unsigned long prev_pinfo; | |
2313 | ||
47e39b9d | 2314 | prev_pinfo = history[0].insn_mo->pinfo; |
252b5132 | 2315 | if (! mips_opts.noreorder |
81912461 ILT |
2316 | && (((prev_pinfo & INSN_LOAD_MEMORY_DELAY) |
2317 | && ! gpr_interlocks) | |
2318 | || ((prev_pinfo & INSN_LOAD_COPROC_DELAY) | |
2319 | && ! cop_interlocks))) | |
252b5132 | 2320 | { |
81912461 ILT |
2321 | /* A load from a coprocessor or from memory. All load delays |
2322 | delay the use of general register rt for one instruction. */ | |
bdaaa2e1 | 2323 | /* Itbl support may require additional care here. */ |
252b5132 | 2324 | know (prev_pinfo & INSN_WRITE_GPR_T); |
bf12938e | 2325 | if (reg == EXTRACT_OPERAND (RT, history[0])) |
252b5132 RH |
2326 | return 1; |
2327 | } | |
2328 | ||
2329 | return 0; | |
2330 | } | |
2331 | ||
404a8071 RS |
2332 | /* Move all labels in insn_labels to the current insertion point. */ |
2333 | ||
2334 | static void | |
2335 | mips_move_labels (void) | |
2336 | { | |
a8dbcb85 | 2337 | segment_info_type *si = seg_info (now_seg); |
404a8071 RS |
2338 | struct insn_label_list *l; |
2339 | valueT val; | |
2340 | ||
a8dbcb85 | 2341 | for (l = si->label_list; l != NULL; l = l->next) |
404a8071 | 2342 | { |
9c2799c2 | 2343 | gas_assert (S_GET_SEGMENT (l->label) == now_seg); |
404a8071 RS |
2344 | symbol_set_frag (l->label, frag_now); |
2345 | val = (valueT) frag_now_fix (); | |
2346 | /* mips16 text labels are stored as odd. */ | |
2347 | if (mips_opts.mips16) | |
2348 | ++val; | |
2349 | S_SET_VALUE (l->label, val); | |
2350 | } | |
2351 | } | |
2352 | ||
5f0fe04b TS |
2353 | static bfd_boolean |
2354 | s_is_linkonce (symbolS *sym, segT from_seg) | |
2355 | { | |
2356 | bfd_boolean linkonce = FALSE; | |
2357 | segT symseg = S_GET_SEGMENT (sym); | |
2358 | ||
2359 | if (symseg != from_seg && !S_IS_LOCAL (sym)) | |
2360 | { | |
2361 | if ((bfd_get_section_flags (stdoutput, symseg) & SEC_LINK_ONCE)) | |
2362 | linkonce = TRUE; | |
2363 | #ifdef OBJ_ELF | |
2364 | /* The GNU toolchain uses an extension for ELF: a section | |
2365 | beginning with the magic string .gnu.linkonce is a | |
2366 | linkonce section. */ | |
2367 | if (strncmp (segment_name (symseg), ".gnu.linkonce", | |
2368 | sizeof ".gnu.linkonce" - 1) == 0) | |
2369 | linkonce = TRUE; | |
2370 | #endif | |
2371 | } | |
2372 | return linkonce; | |
2373 | } | |
2374 | ||
252b5132 RH |
2375 | /* Mark instruction labels in mips16 mode. This permits the linker to |
2376 | handle them specially, such as generating jalx instructions when | |
2377 | needed. We also make them odd for the duration of the assembly, in | |
2378 | order to generate the right sort of code. We will make them even | |
2379 | in the adjust_symtab routine, while leaving them marked. This is | |
2380 | convenient for the debugger and the disassembler. The linker knows | |
2381 | to make them odd again. */ | |
2382 | ||
2383 | static void | |
17a2f251 | 2384 | mips16_mark_labels (void) |
252b5132 | 2385 | { |
a8dbcb85 TS |
2386 | segment_info_type *si = seg_info (now_seg); |
2387 | struct insn_label_list *l; | |
252b5132 | 2388 | |
a8dbcb85 TS |
2389 | if (!mips_opts.mips16) |
2390 | return; | |
2391 | ||
2392 | for (l = si->label_list; l != NULL; l = l->next) | |
2393 | { | |
2394 | symbolS *label = l->label; | |
2395 | ||
2396 | #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF) | |
f43abd2b | 2397 | if (IS_ELF) |
30c09090 | 2398 | S_SET_OTHER (label, ELF_ST_SET_MIPS16 (S_GET_OTHER (label))); |
252b5132 | 2399 | #endif |
5f0fe04b TS |
2400 | if ((S_GET_VALUE (label) & 1) == 0 |
2401 | /* Don't adjust the address if the label is global or weak, or | |
2402 | in a link-once section, since we'll be emitting symbol reloc | |
2403 | references to it which will be patched up by the linker, and | |
2404 | the final value of the symbol may or may not be MIPS16. */ | |
2405 | && ! S_IS_WEAK (label) | |
2406 | && ! S_IS_EXTERNAL (label) | |
2407 | && ! s_is_linkonce (label, now_seg)) | |
a8dbcb85 | 2408 | S_SET_VALUE (label, S_GET_VALUE (label) | 1); |
252b5132 RH |
2409 | } |
2410 | } | |
2411 | ||
4d7206a2 RS |
2412 | /* End the current frag. Make it a variant frag and record the |
2413 | relaxation info. */ | |
2414 | ||
2415 | static void | |
2416 | relax_close_frag (void) | |
2417 | { | |
584892a6 | 2418 | mips_macro_warning.first_frag = frag_now; |
4d7206a2 | 2419 | frag_var (rs_machine_dependent, 0, 0, |
584892a6 | 2420 | RELAX_ENCODE (mips_relax.sizes[0], mips_relax.sizes[1]), |
4d7206a2 RS |
2421 | mips_relax.symbol, 0, (char *) mips_relax.first_fixup); |
2422 | ||
2423 | memset (&mips_relax.sizes, 0, sizeof (mips_relax.sizes)); | |
2424 | mips_relax.first_fixup = 0; | |
2425 | } | |
2426 | ||
2427 | /* Start a new relaxation sequence whose expansion depends on SYMBOL. | |
2428 | See the comment above RELAX_ENCODE for more details. */ | |
2429 | ||
2430 | static void | |
2431 | relax_start (symbolS *symbol) | |
2432 | { | |
9c2799c2 | 2433 | gas_assert (mips_relax.sequence == 0); |
4d7206a2 RS |
2434 | mips_relax.sequence = 1; |
2435 | mips_relax.symbol = symbol; | |
2436 | } | |
2437 | ||
2438 | /* Start generating the second version of a relaxable sequence. | |
2439 | See the comment above RELAX_ENCODE for more details. */ | |
252b5132 RH |
2440 | |
2441 | static void | |
4d7206a2 RS |
2442 | relax_switch (void) |
2443 | { | |
9c2799c2 | 2444 | gas_assert (mips_relax.sequence == 1); |
4d7206a2 RS |
2445 | mips_relax.sequence = 2; |
2446 | } | |
2447 | ||
2448 | /* End the current relaxable sequence. */ | |
2449 | ||
2450 | static void | |
2451 | relax_end (void) | |
2452 | { | |
9c2799c2 | 2453 | gas_assert (mips_relax.sequence == 2); |
4d7206a2 RS |
2454 | relax_close_frag (); |
2455 | mips_relax.sequence = 0; | |
2456 | } | |
2457 | ||
71400594 RS |
2458 | /* Classify an instruction according to the FIX_VR4120_* enumeration. |
2459 | Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected | |
2460 | by VR4120 errata. */ | |
4d7206a2 | 2461 | |
71400594 RS |
2462 | static unsigned int |
2463 | classify_vr4120_insn (const char *name) | |
252b5132 | 2464 | { |
71400594 RS |
2465 | if (strncmp (name, "macc", 4) == 0) |
2466 | return FIX_VR4120_MACC; | |
2467 | if (strncmp (name, "dmacc", 5) == 0) | |
2468 | return FIX_VR4120_DMACC; | |
2469 | if (strncmp (name, "mult", 4) == 0) | |
2470 | return FIX_VR4120_MULT; | |
2471 | if (strncmp (name, "dmult", 5) == 0) | |
2472 | return FIX_VR4120_DMULT; | |
2473 | if (strstr (name, "div")) | |
2474 | return FIX_VR4120_DIV; | |
2475 | if (strcmp (name, "mtlo") == 0 || strcmp (name, "mthi") == 0) | |
2476 | return FIX_VR4120_MTHILO; | |
2477 | return NUM_FIX_VR4120_CLASSES; | |
2478 | } | |
252b5132 | 2479 | |
ff239038 CM |
2480 | #define INSN_ERET 0x42000018 |
2481 | #define INSN_DERET 0x4200001f | |
2482 | ||
71400594 RS |
2483 | /* Return the number of instructions that must separate INSN1 and INSN2, |
2484 | where INSN1 is the earlier instruction. Return the worst-case value | |
2485 | for any INSN2 if INSN2 is null. */ | |
252b5132 | 2486 | |
71400594 RS |
2487 | static unsigned int |
2488 | insns_between (const struct mips_cl_insn *insn1, | |
2489 | const struct mips_cl_insn *insn2) | |
2490 | { | |
2491 | unsigned long pinfo1, pinfo2; | |
2492 | ||
2493 | /* This function needs to know which pinfo flags are set for INSN2 | |
2494 | and which registers INSN2 uses. The former is stored in PINFO2 and | |
2495 | the latter is tested via INSN2_USES_REG. If INSN2 is null, PINFO2 | |
2496 | will have every flag set and INSN2_USES_REG will always return true. */ | |
2497 | pinfo1 = insn1->insn_mo->pinfo; | |
2498 | pinfo2 = insn2 ? insn2->insn_mo->pinfo : ~0U; | |
252b5132 | 2499 | |
71400594 RS |
2500 | #define INSN2_USES_REG(REG, CLASS) \ |
2501 | (insn2 == NULL || insn_uses_reg (insn2, REG, CLASS)) | |
2502 | ||
2503 | /* For most targets, write-after-read dependencies on the HI and LO | |
2504 | registers must be separated by at least two instructions. */ | |
2505 | if (!hilo_interlocks) | |
252b5132 | 2506 | { |
71400594 RS |
2507 | if ((pinfo1 & INSN_READ_LO) && (pinfo2 & INSN_WRITE_LO)) |
2508 | return 2; | |
2509 | if ((pinfo1 & INSN_READ_HI) && (pinfo2 & INSN_WRITE_HI)) | |
2510 | return 2; | |
2511 | } | |
2512 | ||
2513 | /* If we're working around r7000 errata, there must be two instructions | |
2514 | between an mfhi or mflo and any instruction that uses the result. */ | |
2515 | if (mips_7000_hilo_fix | |
2516 | && MF_HILO_INSN (pinfo1) | |
2517 | && INSN2_USES_REG (EXTRACT_OPERAND (RD, *insn1), MIPS_GR_REG)) | |
2518 | return 2; | |
2519 | ||
ff239038 CM |
2520 | /* If we're working around 24K errata, one instruction is required |
2521 | if an ERET or DERET is followed by a branch instruction. */ | |
2522 | if (mips_fix_24k) | |
2523 | { | |
2524 | if (insn1->insn_opcode == INSN_ERET | |
2525 | || insn1->insn_opcode == INSN_DERET) | |
2526 | { | |
2527 | if (insn2 == NULL | |
2528 | || insn2->insn_opcode == INSN_ERET | |
2529 | || insn2->insn_opcode == INSN_DERET | |
2530 | || (insn2->insn_mo->pinfo | |
2531 | & (INSN_UNCOND_BRANCH_DELAY | |
2532 | | INSN_COND_BRANCH_DELAY | |
2533 | | INSN_COND_BRANCH_LIKELY)) != 0) | |
2534 | return 1; | |
2535 | } | |
2536 | } | |
2537 | ||
71400594 RS |
2538 | /* If working around VR4120 errata, check for combinations that need |
2539 | a single intervening instruction. */ | |
2540 | if (mips_fix_vr4120) | |
2541 | { | |
2542 | unsigned int class1, class2; | |
252b5132 | 2543 | |
71400594 RS |
2544 | class1 = classify_vr4120_insn (insn1->insn_mo->name); |
2545 | if (class1 != NUM_FIX_VR4120_CLASSES && vr4120_conflicts[class1] != 0) | |
252b5132 | 2546 | { |
71400594 RS |
2547 | if (insn2 == NULL) |
2548 | return 1; | |
2549 | class2 = classify_vr4120_insn (insn2->insn_mo->name); | |
2550 | if (vr4120_conflicts[class1] & (1 << class2)) | |
2551 | return 1; | |
252b5132 | 2552 | } |
71400594 RS |
2553 | } |
2554 | ||
2555 | if (!mips_opts.mips16) | |
2556 | { | |
2557 | /* Check for GPR or coprocessor load delays. All such delays | |
2558 | are on the RT register. */ | |
2559 | /* Itbl support may require additional care here. */ | |
2560 | if ((!gpr_interlocks && (pinfo1 & INSN_LOAD_MEMORY_DELAY)) | |
2561 | || (!cop_interlocks && (pinfo1 & INSN_LOAD_COPROC_DELAY))) | |
252b5132 | 2562 | { |
71400594 RS |
2563 | know (pinfo1 & INSN_WRITE_GPR_T); |
2564 | if (INSN2_USES_REG (EXTRACT_OPERAND (RT, *insn1), MIPS_GR_REG)) | |
2565 | return 1; | |
2566 | } | |
2567 | ||
2568 | /* Check for generic coprocessor hazards. | |
2569 | ||
2570 | This case is not handled very well. There is no special | |
2571 | knowledge of CP0 handling, and the coprocessors other than | |
2572 | the floating point unit are not distinguished at all. */ | |
2573 | /* Itbl support may require additional care here. FIXME! | |
2574 | Need to modify this to include knowledge about | |
2575 | user specified delays! */ | |
2576 | else if ((!cop_interlocks && (pinfo1 & INSN_COPROC_MOVE_DELAY)) | |
2577 | || (!cop_mem_interlocks && (pinfo1 & INSN_COPROC_MEMORY_DELAY))) | |
2578 | { | |
2579 | /* Handle cases where INSN1 writes to a known general coprocessor | |
2580 | register. There must be a one instruction delay before INSN2 | |
2581 | if INSN2 reads that register, otherwise no delay is needed. */ | |
2582 | if (pinfo1 & INSN_WRITE_FPR_T) | |
252b5132 | 2583 | { |
71400594 RS |
2584 | if (INSN2_USES_REG (EXTRACT_OPERAND (FT, *insn1), MIPS_FP_REG)) |
2585 | return 1; | |
252b5132 | 2586 | } |
71400594 | 2587 | else if (pinfo1 & INSN_WRITE_FPR_S) |
252b5132 | 2588 | { |
71400594 RS |
2589 | if (INSN2_USES_REG (EXTRACT_OPERAND (FS, *insn1), MIPS_FP_REG)) |
2590 | return 1; | |
252b5132 RH |
2591 | } |
2592 | else | |
2593 | { | |
71400594 RS |
2594 | /* Read-after-write dependencies on the control registers |
2595 | require a two-instruction gap. */ | |
2596 | if ((pinfo1 & INSN_WRITE_COND_CODE) | |
2597 | && (pinfo2 & INSN_READ_COND_CODE)) | |
2598 | return 2; | |
2599 | ||
2600 | /* We don't know exactly what INSN1 does. If INSN2 is | |
2601 | also a coprocessor instruction, assume there must be | |
2602 | a one instruction gap. */ | |
2603 | if (pinfo2 & INSN_COP) | |
2604 | return 1; | |
252b5132 RH |
2605 | } |
2606 | } | |
6b76fefe | 2607 | |
71400594 RS |
2608 | /* Check for read-after-write dependencies on the coprocessor |
2609 | control registers in cases where INSN1 does not need a general | |
2610 | coprocessor delay. This means that INSN1 is a floating point | |
2611 | comparison instruction. */ | |
2612 | /* Itbl support may require additional care here. */ | |
2613 | else if (!cop_interlocks | |
2614 | && (pinfo1 & INSN_WRITE_COND_CODE) | |
2615 | && (pinfo2 & INSN_READ_COND_CODE)) | |
2616 | return 1; | |
2617 | } | |
6b76fefe | 2618 | |
71400594 | 2619 | #undef INSN2_USES_REG |
6b76fefe | 2620 | |
71400594 RS |
2621 | return 0; |
2622 | } | |
6b76fefe | 2623 | |
7d8e00cf RS |
2624 | /* Return the number of nops that would be needed to work around the |
2625 | VR4130 mflo/mfhi errata if instruction INSN immediately followed | |
91d6fa6a | 2626 | the MAX_VR4130_NOPS instructions described by HIST. */ |
7d8e00cf RS |
2627 | |
2628 | static int | |
91d6fa6a | 2629 | nops_for_vr4130 (const struct mips_cl_insn *hist, |
7d8e00cf RS |
2630 | const struct mips_cl_insn *insn) |
2631 | { | |
2632 | int i, j, reg; | |
2633 | ||
2634 | /* Check if the instruction writes to HI or LO. MTHI and MTLO | |
2635 | are not affected by the errata. */ | |
2636 | if (insn != 0 | |
2637 | && ((insn->insn_mo->pinfo & (INSN_WRITE_HI | INSN_WRITE_LO)) == 0 | |
2638 | || strcmp (insn->insn_mo->name, "mtlo") == 0 | |
2639 | || strcmp (insn->insn_mo->name, "mthi") == 0)) | |
2640 | return 0; | |
2641 | ||
2642 | /* Search for the first MFLO or MFHI. */ | |
2643 | for (i = 0; i < MAX_VR4130_NOPS; i++) | |
91d6fa6a | 2644 | if (MF_HILO_INSN (hist[i].insn_mo->pinfo)) |
7d8e00cf RS |
2645 | { |
2646 | /* Extract the destination register. */ | |
2647 | if (mips_opts.mips16) | |
91d6fa6a | 2648 | reg = mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, hist[i])]; |
7d8e00cf | 2649 | else |
91d6fa6a | 2650 | reg = EXTRACT_OPERAND (RD, hist[i]); |
7d8e00cf RS |
2651 | |
2652 | /* No nops are needed if INSN reads that register. */ | |
2653 | if (insn != NULL && insn_uses_reg (insn, reg, MIPS_GR_REG)) | |
2654 | return 0; | |
2655 | ||
2656 | /* ...or if any of the intervening instructions do. */ | |
2657 | for (j = 0; j < i; j++) | |
91d6fa6a | 2658 | if (insn_uses_reg (&hist[j], reg, MIPS_GR_REG)) |
7d8e00cf RS |
2659 | return 0; |
2660 | ||
2661 | return MAX_VR4130_NOPS - i; | |
2662 | } | |
2663 | return 0; | |
2664 | } | |
2665 | ||
71400594 | 2666 | /* Return the number of nops that would be needed if instruction INSN |
91d6fa6a NC |
2667 | immediately followed the MAX_NOPS instructions given by HIST, |
2668 | where HIST[0] is the most recent instruction. If INSN is null, | |
71400594 | 2669 | return the worse-case number of nops for any instruction. */ |
bdaaa2e1 | 2670 | |
71400594 | 2671 | static int |
91d6fa6a | 2672 | nops_for_insn (const struct mips_cl_insn *hist, |
71400594 RS |
2673 | const struct mips_cl_insn *insn) |
2674 | { | |
2675 | int i, nops, tmp_nops; | |
bdaaa2e1 | 2676 | |
71400594 | 2677 | nops = 0; |
7d8e00cf | 2678 | for (i = 0; i < MAX_DELAY_NOPS; i++) |
65b02341 | 2679 | { |
91d6fa6a | 2680 | tmp_nops = insns_between (hist + i, insn) - i; |
65b02341 RS |
2681 | if (tmp_nops > nops) |
2682 | nops = tmp_nops; | |
2683 | } | |
7d8e00cf RS |
2684 | |
2685 | if (mips_fix_vr4130) | |
2686 | { | |
91d6fa6a | 2687 | tmp_nops = nops_for_vr4130 (hist, insn); |
7d8e00cf RS |
2688 | if (tmp_nops > nops) |
2689 | nops = tmp_nops; | |
2690 | } | |
2691 | ||
71400594 RS |
2692 | return nops; |
2693 | } | |
252b5132 | 2694 | |
71400594 | 2695 | /* The variable arguments provide NUM_INSNS extra instructions that |
91d6fa6a | 2696 | might be added to HIST. Return the largest number of nops that |
71400594 | 2697 | would be needed after the extended sequence. */ |
252b5132 | 2698 | |
71400594 | 2699 | static int |
91d6fa6a | 2700 | nops_for_sequence (int num_insns, const struct mips_cl_insn *hist, ...) |
71400594 RS |
2701 | { |
2702 | va_list args; | |
2703 | struct mips_cl_insn buffer[MAX_NOPS]; | |
2704 | struct mips_cl_insn *cursor; | |
2705 | int nops; | |
2706 | ||
91d6fa6a | 2707 | va_start (args, hist); |
71400594 | 2708 | cursor = buffer + num_insns; |
91d6fa6a | 2709 | memcpy (cursor, hist, (MAX_NOPS - num_insns) * sizeof (*cursor)); |
71400594 RS |
2710 | while (cursor > buffer) |
2711 | *--cursor = *va_arg (args, const struct mips_cl_insn *); | |
2712 | ||
2713 | nops = nops_for_insn (buffer, NULL); | |
2714 | va_end (args); | |
2715 | return nops; | |
2716 | } | |
252b5132 | 2717 | |
71400594 RS |
2718 | /* Like nops_for_insn, but if INSN is a branch, take into account the |
2719 | worst-case delay for the branch target. */ | |
252b5132 | 2720 | |
71400594 | 2721 | static int |
91d6fa6a | 2722 | nops_for_insn_or_target (const struct mips_cl_insn *hist, |
71400594 RS |
2723 | const struct mips_cl_insn *insn) |
2724 | { | |
2725 | int nops, tmp_nops; | |
60b63b72 | 2726 | |
91d6fa6a | 2727 | nops = nops_for_insn (hist, insn); |
71400594 RS |
2728 | if (insn->insn_mo->pinfo & (INSN_UNCOND_BRANCH_DELAY |
2729 | | INSN_COND_BRANCH_DELAY | |
2730 | | INSN_COND_BRANCH_LIKELY)) | |
2731 | { | |
91d6fa6a | 2732 | tmp_nops = nops_for_sequence (2, hist, insn, NOP_INSN); |
71400594 RS |
2733 | if (tmp_nops > nops) |
2734 | nops = tmp_nops; | |
2735 | } | |
9a2c7088 MR |
2736 | else if (mips_opts.mips16 |
2737 | && (insn->insn_mo->pinfo & (MIPS16_INSN_UNCOND_BRANCH | |
2738 | | MIPS16_INSN_COND_BRANCH))) | |
71400594 | 2739 | { |
91d6fa6a | 2740 | tmp_nops = nops_for_sequence (1, hist, insn); |
71400594 RS |
2741 | if (tmp_nops > nops) |
2742 | nops = tmp_nops; | |
2743 | } | |
2744 | return nops; | |
2745 | } | |
2746 | ||
c67a084a NC |
2747 | /* Fix NOP issue: Replace nops by "or at,at,zero". */ |
2748 | ||
2749 | static void | |
2750 | fix_loongson2f_nop (struct mips_cl_insn * ip) | |
2751 | { | |
2752 | if (strcmp (ip->insn_mo->name, "nop") == 0) | |
2753 | ip->insn_opcode = LOONGSON2F_NOP_INSN; | |
2754 | } | |
2755 | ||
2756 | /* Fix Jump Issue: Eliminate instruction fetch from outside 256M region | |
2757 | jr target pc &= 'hffff_ffff_cfff_ffff. */ | |
2758 | ||
2759 | static void | |
2760 | fix_loongson2f_jump (struct mips_cl_insn * ip) | |
2761 | { | |
2762 | if (strcmp (ip->insn_mo->name, "j") == 0 | |
2763 | || strcmp (ip->insn_mo->name, "jr") == 0 | |
2764 | || strcmp (ip->insn_mo->name, "jalr") == 0) | |
2765 | { | |
2766 | int sreg; | |
2767 | expressionS ep; | |
2768 | ||
2769 | if (! mips_opts.at) | |
2770 | return; | |
2771 | ||
2772 | sreg = EXTRACT_OPERAND (RS, *ip); | |
2773 | if (sreg == ZERO || sreg == KT0 || sreg == KT1 || sreg == ATREG) | |
2774 | return; | |
2775 | ||
2776 | ep.X_op = O_constant; | |
2777 | ep.X_add_number = 0xcfff0000; | |
2778 | macro_build (&ep, "lui", "t,u", ATREG, BFD_RELOC_HI16); | |
2779 | ep.X_add_number = 0xffff; | |
2780 | macro_build (&ep, "ori", "t,r,i", ATREG, ATREG, BFD_RELOC_LO16); | |
2781 | macro_build (NULL, "and", "d,v,t", sreg, sreg, ATREG); | |
2782 | } | |
2783 | } | |
2784 | ||
2785 | static void | |
2786 | fix_loongson2f (struct mips_cl_insn * ip) | |
2787 | { | |
2788 | if (mips_fix_loongson2f_nop) | |
2789 | fix_loongson2f_nop (ip); | |
2790 | ||
2791 | if (mips_fix_loongson2f_jump) | |
2792 | fix_loongson2f_jump (ip); | |
2793 | } | |
2794 | ||
71400594 RS |
2795 | /* Output an instruction. IP is the instruction information. |
2796 | ADDRESS_EXPR is an operand of the instruction to be used with | |
2797 | RELOC_TYPE. */ | |
2798 | ||
2799 | static void | |
2800 | append_insn (struct mips_cl_insn *ip, expressionS *address_expr, | |
2801 | bfd_reloc_code_real_type *reloc_type) | |
2802 | { | |
3994f87e | 2803 | unsigned long prev_pinfo, pinfo; |
71400594 RS |
2804 | relax_stateT prev_insn_frag_type = 0; |
2805 | bfd_boolean relaxed_branch = FALSE; | |
a8dbcb85 | 2806 | segment_info_type *si = seg_info (now_seg); |
71400594 | 2807 | |
c67a084a NC |
2808 | if (mips_fix_loongson2f) |
2809 | fix_loongson2f (ip); | |
2810 | ||
71400594 RS |
2811 | /* Mark instruction labels in mips16 mode. */ |
2812 | mips16_mark_labels (); | |
2813 | ||
2814 | prev_pinfo = history[0].insn_mo->pinfo; | |
2815 | pinfo = ip->insn_mo->pinfo; | |
2816 | ||
2817 | if (mips_relax.sequence != 2 && !mips_opts.noreorder) | |
2818 | { | |
2819 | /* There are a lot of optimizations we could do that we don't. | |
2820 | In particular, we do not, in general, reorder instructions. | |
2821 | If you use gcc with optimization, it will reorder | |
2822 | instructions and generally do much more optimization then we | |
2823 | do here; repeating all that work in the assembler would only | |
2824 | benefit hand written assembly code, and does not seem worth | |
2825 | it. */ | |
2826 | int nops = (mips_optimize == 0 | |
2827 | ? nops_for_insn (history, NULL) | |
2828 | : nops_for_insn_or_target (history, ip)); | |
2829 | if (nops > 0) | |
252b5132 RH |
2830 | { |
2831 | fragS *old_frag; | |
2832 | unsigned long old_frag_offset; | |
2833 | int i; | |
252b5132 RH |
2834 | |
2835 | old_frag = frag_now; | |
2836 | old_frag_offset = frag_now_fix (); | |
2837 | ||
2838 | for (i = 0; i < nops; i++) | |
2839 | emit_nop (); | |
2840 | ||
2841 | if (listing) | |
2842 | { | |
2843 | listing_prev_line (); | |
2844 | /* We may be at the start of a variant frag. In case we | |
2845 | are, make sure there is enough space for the frag | |
2846 | after the frags created by listing_prev_line. The | |
2847 | argument to frag_grow here must be at least as large | |
2848 | as the argument to all other calls to frag_grow in | |
2849 | this file. We don't have to worry about being in the | |
2850 | middle of a variant frag, because the variants insert | |
2851 | all needed nop instructions themselves. */ | |
2852 | frag_grow (40); | |
2853 | } | |
2854 | ||
404a8071 | 2855 | mips_move_labels (); |
252b5132 RH |
2856 | |
2857 | #ifndef NO_ECOFF_DEBUGGING | |
2858 | if (ECOFF_DEBUGGING) | |
2859 | ecoff_fix_loc (old_frag, old_frag_offset); | |
2860 | #endif | |
2861 | } | |
71400594 RS |
2862 | } |
2863 | else if (mips_relax.sequence != 2 && prev_nop_frag != NULL) | |
2864 | { | |
2865 | /* Work out how many nops in prev_nop_frag are needed by IP. */ | |
2866 | int nops = nops_for_insn_or_target (history, ip); | |
9c2799c2 | 2867 | gas_assert (nops <= prev_nop_frag_holds); |
252b5132 | 2868 | |
71400594 RS |
2869 | /* Enforce NOPS as a minimum. */ |
2870 | if (nops > prev_nop_frag_required) | |
2871 | prev_nop_frag_required = nops; | |
252b5132 | 2872 | |
71400594 RS |
2873 | if (prev_nop_frag_holds == prev_nop_frag_required) |
2874 | { | |
2875 | /* Settle for the current number of nops. Update the history | |
2876 | accordingly (for the benefit of any future .set reorder code). */ | |
2877 | prev_nop_frag = NULL; | |
2878 | insert_into_history (prev_nop_frag_since, | |
2879 | prev_nop_frag_holds, NOP_INSN); | |
2880 | } | |
2881 | else | |
2882 | { | |
2883 | /* Allow this instruction to replace one of the nops that was | |
2884 | tentatively added to prev_nop_frag. */ | |
2885 | prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4; | |
2886 | prev_nop_frag_holds--; | |
2887 | prev_nop_frag_since++; | |
252b5132 RH |
2888 | } |
2889 | } | |
2890 | ||
58e2ea4d MR |
2891 | #ifdef OBJ_ELF |
2892 | /* The value passed to dwarf2_emit_insn is the distance between | |
2893 | the beginning of the current instruction and the address that | |
2894 | should be recorded in the debug tables. For MIPS16 debug info | |
2895 | we want to use ISA-encoded addresses, so we pass -1 for an | |
2896 | address higher by one than the current. */ | |
2897 | dwarf2_emit_insn (mips_opts.mips16 ? -1 : 0); | |
2898 | #endif | |
2899 | ||
895921c9 | 2900 | /* Record the frag type before frag_var. */ |
47e39b9d RS |
2901 | if (history[0].frag) |
2902 | prev_insn_frag_type = history[0].frag->fr_type; | |
895921c9 | 2903 | |
4d7206a2 | 2904 | if (address_expr |
0b25d3e6 | 2905 | && *reloc_type == BFD_RELOC_16_PCREL_S2 |
4a6a3df4 AO |
2906 | && (pinfo & INSN_UNCOND_BRANCH_DELAY || pinfo & INSN_COND_BRANCH_DELAY |
2907 | || pinfo & INSN_COND_BRANCH_LIKELY) | |
2908 | && mips_relax_branch | |
2909 | /* Don't try branch relaxation within .set nomacro, or within | |
2910 | .set noat if we use $at for PIC computations. If it turns | |
2911 | out that the branch was out-of-range, we'll get an error. */ | |
2912 | && !mips_opts.warn_about_macros | |
741fe287 | 2913 | && (mips_opts.at || mips_pic == NO_PIC) |
4a6a3df4 AO |
2914 | && !mips_opts.mips16) |
2915 | { | |
895921c9 | 2916 | relaxed_branch = TRUE; |
1e915849 RS |
2917 | add_relaxed_insn (ip, (relaxed_branch_length |
2918 | (NULL, NULL, | |
2919 | (pinfo & INSN_UNCOND_BRANCH_DELAY) ? -1 | |
2920 | : (pinfo & INSN_COND_BRANCH_LIKELY) ? 1 | |
2921 | : 0)), 4, | |
2922 | RELAX_BRANCH_ENCODE | |
2923 | (pinfo & INSN_UNCOND_BRANCH_DELAY, | |
2924 | pinfo & INSN_COND_BRANCH_LIKELY, | |
2925 | pinfo & INSN_WRITE_GPR_31, | |
2926 | 0), | |
2927 | address_expr->X_add_symbol, | |
2928 | address_expr->X_add_number); | |
4a6a3df4 AO |
2929 | *reloc_type = BFD_RELOC_UNUSED; |
2930 | } | |
2931 | else if (*reloc_type > BFD_RELOC_UNUSED) | |
252b5132 RH |
2932 | { |
2933 | /* We need to set up a variant frag. */ | |
9c2799c2 | 2934 | gas_assert (mips_opts.mips16 && address_expr != NULL); |
1e915849 RS |
2935 | add_relaxed_insn (ip, 4, 0, |
2936 | RELAX_MIPS16_ENCODE | |
2937 | (*reloc_type - BFD_RELOC_UNUSED, | |
2938 | mips16_small, mips16_ext, | |
2939 | prev_pinfo & INSN_UNCOND_BRANCH_DELAY, | |
2940 | history[0].mips16_absolute_jump_p), | |
2941 | make_expr_symbol (address_expr), 0); | |
252b5132 | 2942 | } |
252b5132 RH |
2943 | else if (mips_opts.mips16 |
2944 | && ! ip->use_extend | |
f6688943 | 2945 | && *reloc_type != BFD_RELOC_MIPS16_JMP) |
9497f5ac | 2946 | { |
b8ee1a6e DU |
2947 | if ((pinfo & INSN_UNCOND_BRANCH_DELAY) == 0) |
2948 | /* Make sure there is enough room to swap this instruction with | |
2949 | a following jump instruction. */ | |
2950 | frag_grow (6); | |
1e915849 | 2951 | add_fixed_insn (ip); |
252b5132 RH |
2952 | } |
2953 | else | |
2954 | { | |
2955 | if (mips_opts.mips16 | |
2956 | && mips_opts.noreorder | |
2957 | && (prev_pinfo & INSN_UNCOND_BRANCH_DELAY) != 0) | |
2958 | as_warn (_("extended instruction in delay slot")); | |
2959 | ||
4d7206a2 RS |
2960 | if (mips_relax.sequence) |
2961 | { | |
2962 | /* If we've reached the end of this frag, turn it into a variant | |
2963 | frag and record the information for the instructions we've | |
2964 | written so far. */ | |
2965 | if (frag_room () < 4) | |
2966 | relax_close_frag (); | |
2967 | mips_relax.sizes[mips_relax.sequence - 1] += 4; | |
2968 | } | |
2969 | ||
584892a6 RS |
2970 | if (mips_relax.sequence != 2) |
2971 | mips_macro_warning.sizes[0] += 4; | |
2972 | if (mips_relax.sequence != 1) | |
2973 | mips_macro_warning.sizes[1] += 4; | |
2974 | ||
1e915849 RS |
2975 | if (mips_opts.mips16) |
2976 | { | |
2977 | ip->fixed_p = 1; | |
2978 | ip->mips16_absolute_jump_p = (*reloc_type == BFD_RELOC_MIPS16_JMP); | |
2979 | } | |
2980 | add_fixed_insn (ip); | |
252b5132 RH |
2981 | } |
2982 | ||
01a3f561 | 2983 | if (address_expr != NULL && *reloc_type <= BFD_RELOC_UNUSED) |
252b5132 RH |
2984 | { |
2985 | if (address_expr->X_op == O_constant) | |
2986 | { | |
f17c130b | 2987 | unsigned int tmp; |
f6688943 TS |
2988 | |
2989 | switch (*reloc_type) | |
252b5132 RH |
2990 | { |
2991 | case BFD_RELOC_32: | |
2992 | ip->insn_opcode |= address_expr->X_add_number; | |
2993 | break; | |
2994 | ||
f6688943 | 2995 | case BFD_RELOC_MIPS_HIGHEST: |
f17c130b AM |
2996 | tmp = (address_expr->X_add_number + 0x800080008000ull) >> 48; |
2997 | ip->insn_opcode |= tmp & 0xffff; | |
f6688943 TS |
2998 | break; |
2999 | ||
3000 | case BFD_RELOC_MIPS_HIGHER: | |
f17c130b AM |
3001 | tmp = (address_expr->X_add_number + 0x80008000ull) >> 32; |
3002 | ip->insn_opcode |= tmp & 0xffff; | |
f6688943 TS |
3003 | break; |
3004 | ||
3005 | case BFD_RELOC_HI16_S: | |
f17c130b AM |
3006 | tmp = (address_expr->X_add_number + 0x8000) >> 16; |
3007 | ip->insn_opcode |= tmp & 0xffff; | |
f6688943 TS |
3008 | break; |
3009 | ||
3010 | case BFD_RELOC_HI16: | |
3011 | ip->insn_opcode |= (address_expr->X_add_number >> 16) & 0xffff; | |
3012 | break; | |
3013 | ||
01a3f561 | 3014 | case BFD_RELOC_UNUSED: |
252b5132 | 3015 | case BFD_RELOC_LO16: |
ed6fb7bd | 3016 | case BFD_RELOC_MIPS_GOT_DISP: |
252b5132 RH |
3017 | ip->insn_opcode |= address_expr->X_add_number & 0xffff; |
3018 | break; | |
3019 | ||
3020 | case BFD_RELOC_MIPS_JMP: | |
3021 | if ((address_expr->X_add_number & 3) != 0) | |
3022 | as_bad (_("jump to misaligned address (0x%lx)"), | |
3023 | (unsigned long) address_expr->X_add_number); | |
3024 | ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0x3ffffff; | |
3025 | break; | |
3026 | ||
3027 | case BFD_RELOC_MIPS16_JMP: | |
3028 | if ((address_expr->X_add_number & 3) != 0) | |
3029 | as_bad (_("jump to misaligned address (0x%lx)"), | |
3030 | (unsigned long) address_expr->X_add_number); | |
3031 | ip->insn_opcode |= | |
3032 | (((address_expr->X_add_number & 0x7c0000) << 3) | |
3033 | | ((address_expr->X_add_number & 0xf800000) >> 7) | |
3034 | | ((address_expr->X_add_number & 0x3fffc) >> 2)); | |
3035 | break; | |
3036 | ||
252b5132 | 3037 | case BFD_RELOC_16_PCREL_S2: |
bad36eac DJ |
3038 | if ((address_expr->X_add_number & 3) != 0) |
3039 | as_bad (_("branch to misaligned address (0x%lx)"), | |
3040 | (unsigned long) address_expr->X_add_number); | |
3041 | if (mips_relax_branch) | |
3042 | goto need_reloc; | |
3043 | if ((address_expr->X_add_number + 0x20000) & ~0x3ffff) | |
3044 | as_bad (_("branch address range overflow (0x%lx)"), | |
3045 | (unsigned long) address_expr->X_add_number); | |
3046 | ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0xffff; | |
3047 | break; | |
252b5132 RH |
3048 | |
3049 | default: | |
3050 | internalError (); | |
3051 | } | |
3052 | } | |
01a3f561 | 3053 | else if (*reloc_type < BFD_RELOC_UNUSED) |
252b5132 | 3054 | need_reloc: |
4d7206a2 RS |
3055 | { |
3056 | reloc_howto_type *howto; | |
3057 | int i; | |
34ce925e | 3058 | |
4d7206a2 RS |
3059 | /* In a compound relocation, it is the final (outermost) |
3060 | operator that determines the relocated field. */ | |
3061 | for (i = 1; i < 3; i++) | |
3062 | if (reloc_type[i] == BFD_RELOC_UNUSED) | |
3063 | break; | |
34ce925e | 3064 | |
4d7206a2 | 3065 | howto = bfd_reloc_type_lookup (stdoutput, reloc_type[i - 1]); |
23fce1e3 NC |
3066 | if (howto == NULL) |
3067 | { | |
3068 | /* To reproduce this failure try assembling gas/testsuites/ | |
3069 | gas/mips/mips16-intermix.s with a mips-ecoff targeted | |
3070 | assembler. */ | |
3071 | as_bad (_("Unsupported MIPS relocation number %d"), reloc_type[i - 1]); | |
3072 | howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_16); | |
3073 | } | |
3074 | ||
1e915849 RS |
3075 | ip->fixp[0] = fix_new_exp (ip->frag, ip->where, |
3076 | bfd_get_reloc_size (howto), | |
3077 | address_expr, | |
3078 | reloc_type[0] == BFD_RELOC_16_PCREL_S2, | |
3079 | reloc_type[0]); | |
4d7206a2 | 3080 | |
b314ec0e RS |
3081 | /* Tag symbols that have a R_MIPS16_26 relocation against them. */ |
3082 | if (reloc_type[0] == BFD_RELOC_MIPS16_JMP | |
3083 | && ip->fixp[0]->fx_addsy) | |
3084 | *symbol_get_tc (ip->fixp[0]->fx_addsy) = 1; | |
3085 | ||
4d7206a2 RS |
3086 | /* These relocations can have an addend that won't fit in |
3087 | 4 octets for 64bit assembly. */ | |
3088 | if (HAVE_64BIT_GPRS | |
3089 | && ! howto->partial_inplace | |
3090 | && (reloc_type[0] == BFD_RELOC_16 | |
3091 | || reloc_type[0] == BFD_RELOC_32 | |
3092 | || reloc_type[0] == BFD_RELOC_MIPS_JMP | |
4d7206a2 RS |
3093 | || reloc_type[0] == BFD_RELOC_GPREL16 |
3094 | || reloc_type[0] == BFD_RELOC_MIPS_LITERAL | |
3095 | || reloc_type[0] == BFD_RELOC_GPREL32 | |
3096 | || reloc_type[0] == BFD_RELOC_64 | |
3097 | || reloc_type[0] == BFD_RELOC_CTOR | |
3098 | || reloc_type[0] == BFD_RELOC_MIPS_SUB | |
3099 | || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST | |
3100 | || reloc_type[0] == BFD_RELOC_MIPS_HIGHER | |
3101 | || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP | |
3102 | || reloc_type[0] == BFD_RELOC_MIPS_REL16 | |
d6f16593 MR |
3103 | || reloc_type[0] == BFD_RELOC_MIPS_RELGOT |
3104 | || reloc_type[0] == BFD_RELOC_MIPS16_GPREL | |
738e5348 RS |
3105 | || hi16_reloc_p (reloc_type[0]) |
3106 | || lo16_reloc_p (reloc_type[0]))) | |
1e915849 | 3107 | ip->fixp[0]->fx_no_overflow = 1; |
4d7206a2 RS |
3108 | |
3109 | if (mips_relax.sequence) | |
3110 | { | |
3111 | if (mips_relax.first_fixup == 0) | |
1e915849 | 3112 | mips_relax.first_fixup = ip->fixp[0]; |
4d7206a2 RS |
3113 | } |
3114 | else if (reloc_needs_lo_p (*reloc_type)) | |
3115 | { | |
3116 | struct mips_hi_fixup *hi_fixup; | |
252b5132 | 3117 | |
4d7206a2 RS |
3118 | /* Reuse the last entry if it already has a matching %lo. */ |
3119 | hi_fixup = mips_hi_fixup_list; | |
3120 | if (hi_fixup == 0 | |
3121 | || !fixup_has_matching_lo_p (hi_fixup->fixp)) | |
3122 | { | |
3123 | hi_fixup = ((struct mips_hi_fixup *) | |
3124 | xmalloc (sizeof (struct mips_hi_fixup))); | |
3125 | hi_fixup->next = mips_hi_fixup_list; | |
3126 | mips_hi_fixup_list = hi_fixup; | |
252b5132 | 3127 | } |
1e915849 | 3128 | hi_fixup->fixp = ip->fixp[0]; |
4d7206a2 RS |
3129 | hi_fixup->seg = now_seg; |
3130 | } | |
f6688943 | 3131 | |
4d7206a2 RS |
3132 | /* Add fixups for the second and third relocations, if given. |
3133 | Note that the ABI allows the second relocation to be | |
3134 | against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the | |
3135 | moment we only use RSS_UNDEF, but we could add support | |
3136 | for the others if it ever becomes necessary. */ | |
3137 | for (i = 1; i < 3; i++) | |
3138 | if (reloc_type[i] != BFD_RELOC_UNUSED) | |
3139 | { | |
1e915849 RS |
3140 | ip->fixp[i] = fix_new (ip->frag, ip->where, |
3141 | ip->fixp[0]->fx_size, NULL, 0, | |
3142 | FALSE, reloc_type[i]); | |
b1dca8ee RS |
3143 | |
3144 | /* Use fx_tcbit to mark compound relocs. */ | |
1e915849 RS |
3145 | ip->fixp[0]->fx_tcbit = 1; |
3146 | ip->fixp[i]->fx_tcbit = 1; | |
4d7206a2 | 3147 | } |
252b5132 RH |
3148 | } |
3149 | } | |
1e915849 | 3150 | install_insn (ip); |
252b5132 RH |
3151 | |
3152 | /* Update the register mask information. */ | |
3153 | if (! mips_opts.mips16) | |
3154 | { | |
3155 | if (pinfo & INSN_WRITE_GPR_D) | |
bf12938e | 3156 | mips_gprmask |= 1 << EXTRACT_OPERAND (RD, *ip); |
252b5132 | 3157 | if ((pinfo & (INSN_WRITE_GPR_T | INSN_READ_GPR_T)) != 0) |
bf12938e | 3158 | mips_gprmask |= 1 << EXTRACT_OPERAND (RT, *ip); |
252b5132 | 3159 | if (pinfo & INSN_READ_GPR_S) |
bf12938e | 3160 | mips_gprmask |= 1 << EXTRACT_OPERAND (RS, *ip); |
252b5132 | 3161 | if (pinfo & INSN_WRITE_GPR_31) |
f9419b05 | 3162 | mips_gprmask |= 1 << RA; |
252b5132 | 3163 | if (pinfo & INSN_WRITE_FPR_D) |
bf12938e | 3164 | mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FD, *ip); |
252b5132 | 3165 | if ((pinfo & (INSN_WRITE_FPR_S | INSN_READ_FPR_S)) != 0) |
bf12938e | 3166 | mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FS, *ip); |
252b5132 | 3167 | if ((pinfo & (INSN_WRITE_FPR_T | INSN_READ_FPR_T)) != 0) |
bf12938e | 3168 | mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FT, *ip); |
252b5132 | 3169 | if ((pinfo & INSN_READ_FPR_R) != 0) |
bf12938e | 3170 | mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FR, *ip); |
252b5132 RH |
3171 | if (pinfo & INSN_COP) |
3172 | { | |
bdaaa2e1 KH |
3173 | /* We don't keep enough information to sort these cases out. |
3174 | The itbl support does keep this information however, although | |
3175 | we currently don't support itbl fprmats as part of the cop | |
3176 | instruction. May want to add this support in the future. */ | |
252b5132 RH |
3177 | } |
3178 | /* Never set the bit for $0, which is always zero. */ | |
beae10d5 | 3179 | mips_gprmask &= ~1 << 0; |
252b5132 RH |
3180 | } |
3181 | else | |
3182 | { | |
3183 | if (pinfo & (MIPS16_INSN_WRITE_X | MIPS16_INSN_READ_X)) | |
bf12938e | 3184 | mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (RX, *ip); |
252b5132 | 3185 | if (pinfo & (MIPS16_INSN_WRITE_Y | MIPS16_INSN_READ_Y)) |
bf12938e | 3186 | mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (RY, *ip); |
252b5132 | 3187 | if (pinfo & MIPS16_INSN_WRITE_Z) |
bf12938e | 3188 | mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (RZ, *ip); |
252b5132 RH |
3189 | if (pinfo & (MIPS16_INSN_WRITE_T | MIPS16_INSN_READ_T)) |
3190 | mips_gprmask |= 1 << TREG; | |
3191 | if (pinfo & (MIPS16_INSN_WRITE_SP | MIPS16_INSN_READ_SP)) | |
3192 | mips_gprmask |= 1 << SP; | |
3193 | if (pinfo & (MIPS16_INSN_WRITE_31 | MIPS16_INSN_READ_31)) | |
3194 | mips_gprmask |= 1 << RA; | |
3195 | if (pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
3196 | mips_gprmask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode); | |
3197 | if (pinfo & MIPS16_INSN_READ_Z) | |
bf12938e | 3198 | mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (MOVE32Z, *ip); |
252b5132 | 3199 | if (pinfo & MIPS16_INSN_READ_GPR_X) |
bf12938e | 3200 | mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (REGR32, *ip); |
252b5132 RH |
3201 | } |
3202 | ||
4d7206a2 | 3203 | if (mips_relax.sequence != 2 && !mips_opts.noreorder) |
252b5132 RH |
3204 | { |
3205 | /* Filling the branch delay slot is more complex. We try to | |
3206 | switch the branch with the previous instruction, which we can | |
3207 | do if the previous instruction does not set up a condition | |
3208 | that the branch tests and if the branch is not itself the | |
3209 | target of any branch. */ | |
3210 | if ((pinfo & INSN_UNCOND_BRANCH_DELAY) | |
3211 | || (pinfo & INSN_COND_BRANCH_DELAY)) | |
3212 | { | |
3213 | if (mips_optimize < 2 | |
3214 | /* If we have seen .set volatile or .set nomove, don't | |
3215 | optimize. */ | |
3216 | || mips_opts.nomove != 0 | |
a38419a5 RS |
3217 | /* We can't swap if the previous instruction's position |
3218 | is fixed. */ | |
3219 | || history[0].fixed_p | |
252b5132 RH |
3220 | /* If the previous previous insn was in a .set |
3221 | noreorder, we can't swap. Actually, the MIPS | |
3222 | assembler will swap in this situation. However, gcc | |
3223 | configured -with-gnu-as will generate code like | |
3224 | .set noreorder | |
3225 | lw $4,XXX | |
3226 | .set reorder | |
3227 | INSN | |
3228 | bne $4,$0,foo | |
3229 | in which we can not swap the bne and INSN. If gcc is | |
3230 | not configured -with-gnu-as, it does not output the | |
a38419a5 | 3231 | .set pseudo-ops. */ |
47e39b9d | 3232 | || history[1].noreorder_p |
252b5132 RH |
3233 | /* If the branch is itself the target of a branch, we |
3234 | can not swap. We cheat on this; all we check for is | |
3235 | whether there is a label on this instruction. If | |
3236 | there are any branches to anything other than a | |
3237 | label, users must use .set noreorder. */ | |
a8dbcb85 | 3238 | || si->label_list != NULL |
895921c9 MR |
3239 | /* If the previous instruction is in a variant frag |
3240 | other than this branch's one, we cannot do the swap. | |
3241 | This does not apply to the mips16, which uses variant | |
3242 | frags for different purposes. */ | |
252b5132 | 3243 | || (! mips_opts.mips16 |
895921c9 | 3244 | && prev_insn_frag_type == rs_machine_dependent) |
71400594 RS |
3245 | /* Check for conflicts between the branch and the instructions |
3246 | before the candidate delay slot. */ | |
3247 | || nops_for_insn (history + 1, ip) > 0 | |
3248 | /* Check for conflicts between the swapped sequence and the | |
3249 | target of the branch. */ | |
3250 | || nops_for_sequence (2, history + 1, ip, history) > 0 | |
252b5132 RH |
3251 | /* We do not swap with a trap instruction, since it |
3252 | complicates trap handlers to have the trap | |
3253 | instruction be in a delay slot. */ | |
3254 | || (prev_pinfo & INSN_TRAP) | |
3255 | /* If the branch reads a register that the previous | |
3256 | instruction sets, we can not swap. */ | |
3257 | || (! mips_opts.mips16 | |
3258 | && (prev_pinfo & INSN_WRITE_GPR_T) | |
bf12938e | 3259 | && insn_uses_reg (ip, EXTRACT_OPERAND (RT, history[0]), |
252b5132 RH |
3260 | MIPS_GR_REG)) |
3261 | || (! mips_opts.mips16 | |
3262 | && (prev_pinfo & INSN_WRITE_GPR_D) | |
bf12938e | 3263 | && insn_uses_reg (ip, EXTRACT_OPERAND (RD, history[0]), |
252b5132 RH |
3264 | MIPS_GR_REG)) |
3265 | || (mips_opts.mips16 | |
3266 | && (((prev_pinfo & MIPS16_INSN_WRITE_X) | |
bf12938e RS |
3267 | && (insn_uses_reg |
3268 | (ip, MIPS16_EXTRACT_OPERAND (RX, history[0]), | |
3269 | MIPS16_REG))) | |
252b5132 | 3270 | || ((prev_pinfo & MIPS16_INSN_WRITE_Y) |
bf12938e RS |
3271 | && (insn_uses_reg |
3272 | (ip, MIPS16_EXTRACT_OPERAND (RY, history[0]), | |
3273 | MIPS16_REG))) | |
252b5132 | 3274 | || ((prev_pinfo & MIPS16_INSN_WRITE_Z) |
bf12938e RS |
3275 | && (insn_uses_reg |
3276 | (ip, MIPS16_EXTRACT_OPERAND (RZ, history[0]), | |
3277 | MIPS16_REG))) | |
252b5132 RH |
3278 | || ((prev_pinfo & MIPS16_INSN_WRITE_T) |
3279 | && insn_uses_reg (ip, TREG, MIPS_GR_REG)) | |
3280 | || ((prev_pinfo & MIPS16_INSN_WRITE_31) | |
3281 | && insn_uses_reg (ip, RA, MIPS_GR_REG)) | |
3282 | || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
3283 | && insn_uses_reg (ip, | |
47e39b9d RS |
3284 | MIPS16OP_EXTRACT_REG32R |
3285 | (history[0].insn_opcode), | |
252b5132 RH |
3286 | MIPS_GR_REG)))) |
3287 | /* If the branch writes a register that the previous | |
3288 | instruction sets, we can not swap (we know that | |
3289 | branches write only to RD or to $31). */ | |
3290 | || (! mips_opts.mips16 | |
3291 | && (prev_pinfo & INSN_WRITE_GPR_T) | |
3292 | && (((pinfo & INSN_WRITE_GPR_D) | |
bf12938e RS |
3293 | && (EXTRACT_OPERAND (RT, history[0]) |
3294 | == EXTRACT_OPERAND (RD, *ip))) | |
252b5132 | 3295 | || ((pinfo & INSN_WRITE_GPR_31) |
bf12938e | 3296 | && EXTRACT_OPERAND (RT, history[0]) == RA))) |
252b5132 RH |
3297 | || (! mips_opts.mips16 |
3298 | && (prev_pinfo & INSN_WRITE_GPR_D) | |
3299 | && (((pinfo & INSN_WRITE_GPR_D) | |
bf12938e RS |
3300 | && (EXTRACT_OPERAND (RD, history[0]) |
3301 | == EXTRACT_OPERAND (RD, *ip))) | |
252b5132 | 3302 | || ((pinfo & INSN_WRITE_GPR_31) |
bf12938e | 3303 | && EXTRACT_OPERAND (RD, history[0]) == RA))) |
252b5132 RH |
3304 | || (mips_opts.mips16 |
3305 | && (pinfo & MIPS16_INSN_WRITE_31) | |
3306 | && ((prev_pinfo & MIPS16_INSN_WRITE_31) | |
3307 | || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
47e39b9d | 3308 | && (MIPS16OP_EXTRACT_REG32R (history[0].insn_opcode) |
252b5132 RH |
3309 | == RA)))) |
3310 | /* If the branch writes a register that the previous | |
3311 | instruction reads, we can not swap (we know that | |
3312 | branches only write to RD or to $31). */ | |
3313 | || (! mips_opts.mips16 | |
3314 | && (pinfo & INSN_WRITE_GPR_D) | |
47e39b9d | 3315 | && insn_uses_reg (&history[0], |
bf12938e | 3316 | EXTRACT_OPERAND (RD, *ip), |
252b5132 RH |
3317 | MIPS_GR_REG)) |
3318 | || (! mips_opts.mips16 | |
3319 | && (pinfo & INSN_WRITE_GPR_31) | |
47e39b9d | 3320 | && insn_uses_reg (&history[0], RA, MIPS_GR_REG)) |
252b5132 RH |
3321 | || (mips_opts.mips16 |
3322 | && (pinfo & MIPS16_INSN_WRITE_31) | |
47e39b9d | 3323 | && insn_uses_reg (&history[0], RA, MIPS_GR_REG)) |
252b5132 RH |
3324 | /* If one instruction sets a condition code and the |
3325 | other one uses a condition code, we can not swap. */ | |
3326 | || ((pinfo & INSN_READ_COND_CODE) | |
3327 | && (prev_pinfo & INSN_WRITE_COND_CODE)) | |
3328 | || ((pinfo & INSN_WRITE_COND_CODE) | |
3329 | && (prev_pinfo & INSN_READ_COND_CODE)) | |
3330 | /* If the previous instruction uses the PC, we can not | |
3331 | swap. */ | |
3332 | || (mips_opts.mips16 | |
3333 | && (prev_pinfo & MIPS16_INSN_READ_PC)) | |
252b5132 RH |
3334 | /* If the previous instruction had a fixup in mips16 |
3335 | mode, we can not swap. This normally means that the | |
3336 | previous instruction was a 4 byte branch anyhow. */ | |
47e39b9d | 3337 | || (mips_opts.mips16 && history[0].fixp[0]) |
bdaaa2e1 KH |
3338 | /* If the previous instruction is a sync, sync.l, or |
3339 | sync.p, we can not swap. */ | |
6a32d874 CM |
3340 | || (prev_pinfo & INSN_SYNC) |
3341 | /* If the previous instruction is an ERET or | |
3342 | DERET, avoid the swap. */ | |
3343 | || (history[0].insn_opcode == INSN_ERET) | |
3344 | || (history[0].insn_opcode == INSN_DERET)) | |
252b5132 | 3345 | { |
29024861 DU |
3346 | if (mips_opts.mips16 |
3347 | && (pinfo & INSN_UNCOND_BRANCH_DELAY) | |
3348 | && (pinfo & (MIPS16_INSN_READ_X | MIPS16_INSN_READ_31)) | |
3994f87e | 3349 | && ISA_SUPPORTS_MIPS16E) |
29024861 DU |
3350 | { |
3351 | /* Convert MIPS16 jr/jalr into a "compact" jump. */ | |
3352 | ip->insn_opcode |= 0x0080; | |
3353 | install_insn (ip); | |
3354 | insert_into_history (0, 1, ip); | |
3355 | } | |
3356 | else | |
3357 | { | |
3358 | /* We could do even better for unconditional branches to | |
3359 | portions of this object file; we could pick up the | |
3360 | instruction at the destination, put it in the delay | |
3361 | slot, and bump the destination address. */ | |
3362 | insert_into_history (0, 1, ip); | |
3363 | emit_nop (); | |
3364 | } | |
3365 | ||
dd22970f ILT |
3366 | if (mips_relax.sequence) |
3367 | mips_relax.sizes[mips_relax.sequence - 1] += 4; | |
252b5132 RH |
3368 | } |
3369 | else | |
3370 | { | |
3371 | /* It looks like we can actually do the swap. */ | |
1e915849 RS |
3372 | struct mips_cl_insn delay = history[0]; |
3373 | if (mips_opts.mips16) | |
252b5132 | 3374 | { |
b8ee1a6e DU |
3375 | know (delay.frag == ip->frag); |
3376 | move_insn (ip, delay.frag, delay.where); | |
3377 | move_insn (&delay, ip->frag, ip->where + insn_length (ip)); | |
1e915849 RS |
3378 | } |
3379 | else if (relaxed_branch) | |
3380 | { | |
3381 | /* Add the delay slot instruction to the end of the | |
3382 | current frag and shrink the fixed part of the | |
3383 | original frag. If the branch occupies the tail of | |
3384 | the latter, move it backwards to cover the gap. */ | |
3385 | delay.frag->fr_fix -= 4; | |
3386 | if (delay.frag == ip->frag) | |
3387 | move_insn (ip, ip->frag, ip->where - 4); | |
3388 | add_fixed_insn (&delay); | |
252b5132 RH |
3389 | } |
3390 | else | |
3391 | { | |
1e915849 RS |
3392 | move_insn (&delay, ip->frag, ip->where); |
3393 | move_insn (ip, history[0].frag, history[0].where); | |
252b5132 | 3394 | } |
1e915849 RS |
3395 | history[0] = *ip; |
3396 | delay.fixed_p = 1; | |
3397 | insert_into_history (0, 1, &delay); | |
252b5132 | 3398 | } |
252b5132 RH |
3399 | |
3400 | /* If that was an unconditional branch, forget the previous | |
3401 | insn information. */ | |
3402 | if (pinfo & INSN_UNCOND_BRANCH_DELAY) | |
6a32d874 | 3403 | { |
6a32d874 CM |
3404 | mips_no_prev_insn (); |
3405 | } | |
252b5132 RH |
3406 | } |
3407 | else if (pinfo & INSN_COND_BRANCH_LIKELY) | |
3408 | { | |
3409 | /* We don't yet optimize a branch likely. What we should do | |
3410 | is look at the target, copy the instruction found there | |
3411 | into the delay slot, and increment the branch to jump to | |
3412 | the next instruction. */ | |
1e915849 | 3413 | insert_into_history (0, 1, ip); |
252b5132 | 3414 | emit_nop (); |
252b5132 RH |
3415 | } |
3416 | else | |
1e915849 | 3417 | insert_into_history (0, 1, ip); |
252b5132 | 3418 | } |
1e915849 RS |
3419 | else |
3420 | insert_into_history (0, 1, ip); | |
252b5132 RH |
3421 | |
3422 | /* We just output an insn, so the next one doesn't have a label. */ | |
3423 | mips_clear_insn_labels (); | |
252b5132 RH |
3424 | } |
3425 | ||
7d10b47d | 3426 | /* Forget that there was any previous instruction or label. */ |
252b5132 RH |
3427 | |
3428 | static void | |
7d10b47d | 3429 | mips_no_prev_insn (void) |
252b5132 | 3430 | { |
7d10b47d RS |
3431 | prev_nop_frag = NULL; |
3432 | insert_into_history (0, ARRAY_SIZE (history), NOP_INSN); | |
252b5132 RH |
3433 | mips_clear_insn_labels (); |
3434 | } | |
3435 | ||
7d10b47d RS |
3436 | /* This function must be called before we emit something other than |
3437 | instructions. It is like mips_no_prev_insn except that it inserts | |
3438 | any NOPS that might be needed by previous instructions. */ | |
252b5132 | 3439 | |
7d10b47d RS |
3440 | void |
3441 | mips_emit_delays (void) | |
252b5132 RH |
3442 | { |
3443 | if (! mips_opts.noreorder) | |
3444 | { | |
71400594 | 3445 | int nops = nops_for_insn (history, NULL); |
252b5132 RH |
3446 | if (nops > 0) |
3447 | { | |
7d10b47d RS |
3448 | while (nops-- > 0) |
3449 | add_fixed_insn (NOP_INSN); | |
3450 | mips_move_labels (); | |
3451 | } | |
3452 | } | |
3453 | mips_no_prev_insn (); | |
3454 | } | |
3455 | ||
3456 | /* Start a (possibly nested) noreorder block. */ | |
3457 | ||
3458 | static void | |
3459 | start_noreorder (void) | |
3460 | { | |
3461 | if (mips_opts.noreorder == 0) | |
3462 | { | |
3463 | unsigned int i; | |
3464 | int nops; | |
3465 | ||
3466 | /* None of the instructions before the .set noreorder can be moved. */ | |
3467 | for (i = 0; i < ARRAY_SIZE (history); i++) | |
3468 | history[i].fixed_p = 1; | |
3469 | ||
3470 | /* Insert any nops that might be needed between the .set noreorder | |
3471 | block and the previous instructions. We will later remove any | |
3472 | nops that turn out not to be needed. */ | |
3473 | nops = nops_for_insn (history, NULL); | |
3474 | if (nops > 0) | |
3475 | { | |
3476 | if (mips_optimize != 0) | |
252b5132 RH |
3477 | { |
3478 | /* Record the frag which holds the nop instructions, so | |
3479 | that we can remove them if we don't need them. */ | |
3480 | frag_grow (mips_opts.mips16 ? nops * 2 : nops * 4); | |
3481 | prev_nop_frag = frag_now; | |
3482 | prev_nop_frag_holds = nops; | |
3483 | prev_nop_frag_required = 0; | |
3484 | prev_nop_frag_since = 0; | |
3485 | } | |
3486 | ||
3487 | for (; nops > 0; --nops) | |
1e915849 | 3488 | add_fixed_insn (NOP_INSN); |
252b5132 | 3489 | |
7d10b47d RS |
3490 | /* Move on to a new frag, so that it is safe to simply |
3491 | decrease the size of prev_nop_frag. */ | |
3492 | frag_wane (frag_now); | |
3493 | frag_new (0); | |
404a8071 | 3494 | mips_move_labels (); |
252b5132 | 3495 | } |
7d10b47d RS |
3496 | mips16_mark_labels (); |
3497 | mips_clear_insn_labels (); | |
252b5132 | 3498 | } |
7d10b47d RS |
3499 | mips_opts.noreorder++; |
3500 | mips_any_noreorder = 1; | |
3501 | } | |
252b5132 | 3502 | |
7d10b47d | 3503 | /* End a nested noreorder block. */ |
252b5132 | 3504 | |
7d10b47d RS |
3505 | static void |
3506 | end_noreorder (void) | |
3507 | { | |
6a32d874 | 3508 | |
7d10b47d RS |
3509 | mips_opts.noreorder--; |
3510 | if (mips_opts.noreorder == 0 && prev_nop_frag != NULL) | |
3511 | { | |
3512 | /* Commit to inserting prev_nop_frag_required nops and go back to | |
3513 | handling nop insertion the .set reorder way. */ | |
3514 | prev_nop_frag->fr_fix -= ((prev_nop_frag_holds - prev_nop_frag_required) | |
3515 | * (mips_opts.mips16 ? 2 : 4)); | |
3516 | insert_into_history (prev_nop_frag_since, | |
3517 | prev_nop_frag_required, NOP_INSN); | |
3518 | prev_nop_frag = NULL; | |
3519 | } | |
252b5132 RH |
3520 | } |
3521 | ||
584892a6 RS |
3522 | /* Set up global variables for the start of a new macro. */ |
3523 | ||
3524 | static void | |
3525 | macro_start (void) | |
3526 | { | |
3527 | memset (&mips_macro_warning.sizes, 0, sizeof (mips_macro_warning.sizes)); | |
3528 | mips_macro_warning.delay_slot_p = (mips_opts.noreorder | |
47e39b9d | 3529 | && (history[0].insn_mo->pinfo |
584892a6 RS |
3530 | & (INSN_UNCOND_BRANCH_DELAY |
3531 | | INSN_COND_BRANCH_DELAY | |
3532 | | INSN_COND_BRANCH_LIKELY)) != 0); | |
3533 | } | |
3534 | ||
3535 | /* Given that a macro is longer than 4 bytes, return the appropriate warning | |
3536 | for it. Return null if no warning is needed. SUBTYPE is a bitmask of | |
3537 | RELAX_DELAY_SLOT and RELAX_NOMACRO. */ | |
3538 | ||
3539 | static const char * | |
3540 | macro_warning (relax_substateT subtype) | |
3541 | { | |
3542 | if (subtype & RELAX_DELAY_SLOT) | |
3543 | return _("Macro instruction expanded into multiple instructions" | |
3544 | " in a branch delay slot"); | |
3545 | else if (subtype & RELAX_NOMACRO) | |
3546 | return _("Macro instruction expanded into multiple instructions"); | |
3547 | else | |
3548 | return 0; | |
3549 | } | |
3550 | ||
3551 | /* Finish up a macro. Emit warnings as appropriate. */ | |
3552 | ||
3553 | static void | |
3554 | macro_end (void) | |
3555 | { | |
3556 | if (mips_macro_warning.sizes[0] > 4 || mips_macro_warning.sizes[1] > 4) | |
3557 | { | |
3558 | relax_substateT subtype; | |
3559 | ||
3560 | /* Set up the relaxation warning flags. */ | |
3561 | subtype = 0; | |
3562 | if (mips_macro_warning.sizes[1] > mips_macro_warning.sizes[0]) | |
3563 | subtype |= RELAX_SECOND_LONGER; | |
3564 | if (mips_opts.warn_about_macros) | |
3565 | subtype |= RELAX_NOMACRO; | |
3566 | if (mips_macro_warning.delay_slot_p) | |
3567 | subtype |= RELAX_DELAY_SLOT; | |
3568 | ||
3569 | if (mips_macro_warning.sizes[0] > 4 && mips_macro_warning.sizes[1] > 4) | |
3570 | { | |
3571 | /* Either the macro has a single implementation or both | |
3572 | implementations are longer than 4 bytes. Emit the | |
3573 | warning now. */ | |
3574 | const char *msg = macro_warning (subtype); | |
3575 | if (msg != 0) | |
520725ea | 3576 | as_warn ("%s", msg); |
584892a6 RS |
3577 | } |
3578 | else | |
3579 | { | |
3580 | /* One implementation might need a warning but the other | |
3581 | definitely doesn't. */ | |
3582 | mips_macro_warning.first_frag->fr_subtype |= subtype; | |
3583 | } | |
3584 | } | |
3585 | } | |
3586 | ||
6e1304d8 RS |
3587 | /* Read a macro's relocation codes from *ARGS and store them in *R. |
3588 | The first argument in *ARGS will be either the code for a single | |
3589 | relocation or -1 followed by the three codes that make up a | |
3590 | composite relocation. */ | |
3591 | ||
3592 | static void | |
3593 | macro_read_relocs (va_list *args, bfd_reloc_code_real_type *r) | |
3594 | { | |
3595 | int i, next; | |
3596 | ||
3597 | next = va_arg (*args, int); | |
3598 | if (next >= 0) | |
3599 | r[0] = (bfd_reloc_code_real_type) next; | |
3600 | else | |
3601 | for (i = 0; i < 3; i++) | |
3602 | r[i] = (bfd_reloc_code_real_type) va_arg (*args, int); | |
3603 | } | |
3604 | ||
252b5132 RH |
3605 | /* Build an instruction created by a macro expansion. This is passed |
3606 | a pointer to the count of instructions created so far, an | |
3607 | expression, the name of the instruction to build, an operand format | |
3608 | string, and corresponding arguments. */ | |
3609 | ||
252b5132 | 3610 | static void |
67c0d1eb | 3611 | macro_build (expressionS *ep, const char *name, const char *fmt, ...) |
252b5132 | 3612 | { |
1e915849 | 3613 | const struct mips_opcode *mo; |
252b5132 | 3614 | struct mips_cl_insn insn; |
f6688943 | 3615 | bfd_reloc_code_real_type r[3]; |
252b5132 | 3616 | va_list args; |
252b5132 | 3617 | |
252b5132 | 3618 | va_start (args, fmt); |
252b5132 | 3619 | |
252b5132 RH |
3620 | if (mips_opts.mips16) |
3621 | { | |
03ea81db | 3622 | mips16_macro_build (ep, name, fmt, &args); |
252b5132 RH |
3623 | va_end (args); |
3624 | return; | |
3625 | } | |
3626 | ||
f6688943 TS |
3627 | r[0] = BFD_RELOC_UNUSED; |
3628 | r[1] = BFD_RELOC_UNUSED; | |
3629 | r[2] = BFD_RELOC_UNUSED; | |
1e915849 | 3630 | mo = (struct mips_opcode *) hash_find (op_hash, name); |
9c2799c2 NC |
3631 | gas_assert (mo); |
3632 | gas_assert (strcmp (name, mo->name) == 0); | |
1e915849 | 3633 | |
8b082fb1 TS |
3634 | while (1) |
3635 | { | |
3636 | /* Search until we get a match for NAME. It is assumed here that | |
3637 | macros will never generate MDMX, MIPS-3D, or MT instructions. */ | |
3638 | if (strcmp (fmt, mo->args) == 0 | |
3639 | && mo->pinfo != INSN_MACRO | |
f79e2745 | 3640 | && is_opcode_valid (mo)) |
8b082fb1 TS |
3641 | break; |
3642 | ||
1e915849 | 3643 | ++mo; |
9c2799c2 NC |
3644 | gas_assert (mo->name); |
3645 | gas_assert (strcmp (name, mo->name) == 0); | |
252b5132 RH |
3646 | } |
3647 | ||
1e915849 | 3648 | create_insn (&insn, mo); |
252b5132 RH |
3649 | for (;;) |
3650 | { | |
3651 | switch (*fmt++) | |
3652 | { | |
3653 | case '\0': | |
3654 | break; | |
3655 | ||
3656 | case ',': | |
3657 | case '(': | |
3658 | case ')': | |
3659 | continue; | |
3660 | ||
5f74bc13 CD |
3661 | case '+': |
3662 | switch (*fmt++) | |
3663 | { | |
3664 | case 'A': | |
3665 | case 'E': | |
bf12938e | 3666 | INSERT_OPERAND (SHAMT, insn, va_arg (args, int)); |
5f74bc13 CD |
3667 | continue; |
3668 | ||
3669 | case 'B': | |
3670 | case 'F': | |
3671 | /* Note that in the macro case, these arguments are already | |
3672 | in MSB form. (When handling the instruction in the | |
3673 | non-macro case, these arguments are sizes from which | |
3674 | MSB values must be calculated.) */ | |
bf12938e | 3675 | INSERT_OPERAND (INSMSB, insn, va_arg (args, int)); |
5f74bc13 CD |
3676 | continue; |
3677 | ||
3678 | case 'C': | |
3679 | case 'G': | |
3680 | case 'H': | |
3681 | /* Note that in the macro case, these arguments are already | |
3682 | in MSBD form. (When handling the instruction in the | |
3683 | non-macro case, these arguments are sizes from which | |
3684 | MSBD values must be calculated.) */ | |
bf12938e | 3685 | INSERT_OPERAND (EXTMSBD, insn, va_arg (args, int)); |
5f74bc13 CD |
3686 | continue; |
3687 | ||
dd3cbb7e NC |
3688 | case 'Q': |
3689 | INSERT_OPERAND (SEQI, insn, va_arg (args, int)); | |
3690 | continue; | |
3691 | ||
5f74bc13 CD |
3692 | default: |
3693 | internalError (); | |
3694 | } | |
3695 | continue; | |
3696 | ||
8b082fb1 TS |
3697 | case '2': |
3698 | INSERT_OPERAND (BP, insn, va_arg (args, int)); | |
3699 | continue; | |
3700 | ||
252b5132 RH |
3701 | case 't': |
3702 | case 'w': | |
3703 | case 'E': | |
bf12938e | 3704 | INSERT_OPERAND (RT, insn, va_arg (args, int)); |
252b5132 RH |
3705 | continue; |
3706 | ||
3707 | case 'c': | |
bf12938e | 3708 | INSERT_OPERAND (CODE, insn, va_arg (args, int)); |
38487616 TS |
3709 | continue; |
3710 | ||
252b5132 RH |
3711 | case 'T': |
3712 | case 'W': | |
bf12938e | 3713 | INSERT_OPERAND (FT, insn, va_arg (args, int)); |
252b5132 RH |
3714 | continue; |
3715 | ||
3716 | case 'd': | |
3717 | case 'G': | |
af7ee8bf | 3718 | case 'K': |
bf12938e | 3719 | INSERT_OPERAND (RD, insn, va_arg (args, int)); |
252b5132 RH |
3720 | continue; |
3721 | ||
4372b673 NC |
3722 | case 'U': |
3723 | { | |
3724 | int tmp = va_arg (args, int); | |
3725 | ||
bf12938e RS |
3726 | INSERT_OPERAND (RT, insn, tmp); |
3727 | INSERT_OPERAND (RD, insn, tmp); | |
beae10d5 | 3728 | continue; |
4372b673 NC |
3729 | } |
3730 | ||
252b5132 RH |
3731 | case 'V': |
3732 | case 'S': | |
bf12938e | 3733 | INSERT_OPERAND (FS, insn, va_arg (args, int)); |
252b5132 RH |
3734 | continue; |
3735 | ||
3736 | case 'z': | |
3737 | continue; | |
3738 | ||
3739 | case '<': | |
bf12938e | 3740 | INSERT_OPERAND (SHAMT, insn, va_arg (args, int)); |
252b5132 RH |
3741 | continue; |
3742 | ||
3743 | case 'D': | |
bf12938e | 3744 | INSERT_OPERAND (FD, insn, va_arg (args, int)); |
252b5132 RH |
3745 | continue; |
3746 | ||
3747 | case 'B': | |
bf12938e | 3748 | INSERT_OPERAND (CODE20, insn, va_arg (args, int)); |
252b5132 RH |
3749 | continue; |
3750 | ||
4372b673 | 3751 | case 'J': |
bf12938e | 3752 | INSERT_OPERAND (CODE19, insn, va_arg (args, int)); |
4372b673 NC |
3753 | continue; |
3754 | ||
252b5132 | 3755 | case 'q': |
bf12938e | 3756 | INSERT_OPERAND (CODE2, insn, va_arg (args, int)); |
252b5132 RH |
3757 | continue; |
3758 | ||
3759 | case 'b': | |
3760 | case 's': | |
3761 | case 'r': | |
3762 | case 'v': | |
bf12938e | 3763 | INSERT_OPERAND (RS, insn, va_arg (args, int)); |
252b5132 RH |
3764 | continue; |
3765 | ||
3766 | case 'i': | |
3767 | case 'j': | |
6e1304d8 | 3768 | macro_read_relocs (&args, r); |
9c2799c2 | 3769 | gas_assert (*r == BFD_RELOC_GPREL16 |
e391c024 RS |
3770 | || *r == BFD_RELOC_MIPS_HIGHER |
3771 | || *r == BFD_RELOC_HI16_S | |
3772 | || *r == BFD_RELOC_LO16 | |
3773 | || *r == BFD_RELOC_MIPS_GOT_OFST); | |
3774 | continue; | |
3775 | ||
3776 | case 'o': | |
3777 | macro_read_relocs (&args, r); | |
252b5132 RH |
3778 | continue; |
3779 | ||
3780 | case 'u': | |
6e1304d8 | 3781 | macro_read_relocs (&args, r); |
9c2799c2 | 3782 | gas_assert (ep != NULL |
90ecf173 MR |
3783 | && (ep->X_op == O_constant |
3784 | || (ep->X_op == O_symbol | |
3785 | && (*r == BFD_RELOC_MIPS_HIGHEST | |
3786 | || *r == BFD_RELOC_HI16_S | |
3787 | || *r == BFD_RELOC_HI16 | |
3788 | || *r == BFD_RELOC_GPREL16 | |
3789 | || *r == BFD_RELOC_MIPS_GOT_HI16 | |
3790 | || *r == BFD_RELOC_MIPS_CALL_HI16)))); | |
252b5132 RH |
3791 | continue; |
3792 | ||
3793 | case 'p': | |
9c2799c2 | 3794 | gas_assert (ep != NULL); |
bad36eac | 3795 | |
252b5132 RH |
3796 | /* |
3797 | * This allows macro() to pass an immediate expression for | |
3798 | * creating short branches without creating a symbol. | |
bad36eac DJ |
3799 | * |
3800 | * We don't allow branch relaxation for these branches, as | |
3801 | * they should only appear in ".set nomacro" anyway. | |
252b5132 RH |
3802 | */ |
3803 | if (ep->X_op == O_constant) | |
3804 | { | |
bad36eac DJ |
3805 | if ((ep->X_add_number & 3) != 0) |
3806 | as_bad (_("branch to misaligned address (0x%lx)"), | |
3807 | (unsigned long) ep->X_add_number); | |
3808 | if ((ep->X_add_number + 0x20000) & ~0x3ffff) | |
3809 | as_bad (_("branch address range overflow (0x%lx)"), | |
3810 | (unsigned long) ep->X_add_number); | |
252b5132 RH |
3811 | insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff; |
3812 | ep = NULL; | |
3813 | } | |
3814 | else | |
0b25d3e6 | 3815 | *r = BFD_RELOC_16_PCREL_S2; |
252b5132 RH |
3816 | continue; |
3817 | ||
3818 | case 'a': | |
9c2799c2 | 3819 | gas_assert (ep != NULL); |
f6688943 | 3820 | *r = BFD_RELOC_MIPS_JMP; |
252b5132 RH |
3821 | continue; |
3822 | ||
3823 | case 'C': | |
a9e24354 | 3824 | INSERT_OPERAND (COPZ, insn, va_arg (args, unsigned long)); |
252b5132 RH |
3825 | continue; |
3826 | ||
d43b4baf | 3827 | case 'k': |
a9e24354 | 3828 | INSERT_OPERAND (CACHE, insn, va_arg (args, unsigned long)); |
d43b4baf TS |
3829 | continue; |
3830 | ||
252b5132 RH |
3831 | default: |
3832 | internalError (); | |
3833 | } | |
3834 | break; | |
3835 | } | |
3836 | va_end (args); | |
9c2799c2 | 3837 | gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
252b5132 | 3838 | |
4d7206a2 | 3839 | append_insn (&insn, ep, r); |
252b5132 RH |
3840 | } |
3841 | ||
3842 | static void | |
67c0d1eb | 3843 | mips16_macro_build (expressionS *ep, const char *name, const char *fmt, |
03ea81db | 3844 | va_list *args) |
252b5132 | 3845 | { |
1e915849 | 3846 | struct mips_opcode *mo; |
252b5132 | 3847 | struct mips_cl_insn insn; |
f6688943 TS |
3848 | bfd_reloc_code_real_type r[3] |
3849 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 3850 | |
1e915849 | 3851 | mo = (struct mips_opcode *) hash_find (mips16_op_hash, name); |
9c2799c2 NC |
3852 | gas_assert (mo); |
3853 | gas_assert (strcmp (name, mo->name) == 0); | |
252b5132 | 3854 | |
1e915849 | 3855 | while (strcmp (fmt, mo->args) != 0 || mo->pinfo == INSN_MACRO) |
252b5132 | 3856 | { |
1e915849 | 3857 | ++mo; |
9c2799c2 NC |
3858 | gas_assert (mo->name); |
3859 | gas_assert (strcmp (name, mo->name) == 0); | |
252b5132 RH |
3860 | } |
3861 | ||
1e915849 | 3862 | create_insn (&insn, mo); |
252b5132 RH |
3863 | for (;;) |
3864 | { | |
3865 | int c; | |
3866 | ||
3867 | c = *fmt++; | |
3868 | switch (c) | |
3869 | { | |
3870 | case '\0': | |
3871 | break; | |
3872 | ||
3873 | case ',': | |
3874 | case '(': | |
3875 | case ')': | |
3876 | continue; | |
3877 | ||
3878 | case 'y': | |
3879 | case 'w': | |
03ea81db | 3880 | MIPS16_INSERT_OPERAND (RY, insn, va_arg (*args, int)); |
252b5132 RH |
3881 | continue; |
3882 | ||
3883 | case 'x': | |
3884 | case 'v': | |
03ea81db | 3885 | MIPS16_INSERT_OPERAND (RX, insn, va_arg (*args, int)); |
252b5132 RH |
3886 | continue; |
3887 | ||
3888 | case 'z': | |
03ea81db | 3889 | MIPS16_INSERT_OPERAND (RZ, insn, va_arg (*args, int)); |
252b5132 RH |
3890 | continue; |
3891 | ||
3892 | case 'Z': | |
03ea81db | 3893 | MIPS16_INSERT_OPERAND (MOVE32Z, insn, va_arg (*args, int)); |
252b5132 RH |
3894 | continue; |
3895 | ||
3896 | case '0': | |
3897 | case 'S': | |
3898 | case 'P': | |
3899 | case 'R': | |
3900 | continue; | |
3901 | ||
3902 | case 'X': | |
03ea81db | 3903 | MIPS16_INSERT_OPERAND (REGR32, insn, va_arg (*args, int)); |
252b5132 RH |
3904 | continue; |
3905 | ||
3906 | case 'Y': | |
3907 | { | |
3908 | int regno; | |
3909 | ||
03ea81db | 3910 | regno = va_arg (*args, int); |
252b5132 | 3911 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); |
a9e24354 | 3912 | MIPS16_INSERT_OPERAND (REG32R, insn, regno); |
252b5132 RH |
3913 | } |
3914 | continue; | |
3915 | ||
3916 | case '<': | |
3917 | case '>': | |
3918 | case '4': | |
3919 | case '5': | |
3920 | case 'H': | |
3921 | case 'W': | |
3922 | case 'D': | |
3923 | case 'j': | |
3924 | case '8': | |
3925 | case 'V': | |
3926 | case 'C': | |
3927 | case 'U': | |
3928 | case 'k': | |
3929 | case 'K': | |
3930 | case 'p': | |
3931 | case 'q': | |
3932 | { | |
9c2799c2 | 3933 | gas_assert (ep != NULL); |
252b5132 RH |
3934 | |
3935 | if (ep->X_op != O_constant) | |
874e8986 | 3936 | *r = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
3937 | else |
3938 | { | |
b34976b6 AM |
3939 | mips16_immed (NULL, 0, c, ep->X_add_number, FALSE, FALSE, |
3940 | FALSE, &insn.insn_opcode, &insn.use_extend, | |
c4e7957c | 3941 | &insn.extend); |
252b5132 | 3942 | ep = NULL; |
f6688943 | 3943 | *r = BFD_RELOC_UNUSED; |
252b5132 RH |
3944 | } |
3945 | } | |
3946 | continue; | |
3947 | ||
3948 | case '6': | |
03ea81db | 3949 | MIPS16_INSERT_OPERAND (IMM6, insn, va_arg (*args, int)); |
252b5132 RH |
3950 | continue; |
3951 | } | |
3952 | ||
3953 | break; | |
3954 | } | |
3955 | ||
9c2799c2 | 3956 | gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
252b5132 | 3957 | |
4d7206a2 | 3958 | append_insn (&insn, ep, r); |
252b5132 RH |
3959 | } |
3960 | ||
2051e8c4 MR |
3961 | /* |
3962 | * Sign-extend 32-bit mode constants that have bit 31 set and all | |
3963 | * higher bits unset. | |
3964 | */ | |
9f872bbe | 3965 | static void |
2051e8c4 MR |
3966 | normalize_constant_expr (expressionS *ex) |
3967 | { | |
9ee2a2d4 | 3968 | if (ex->X_op == O_constant |
2051e8c4 MR |
3969 | && IS_ZEXT_32BIT_NUM (ex->X_add_number)) |
3970 | ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000) | |
3971 | - 0x80000000); | |
3972 | } | |
3973 | ||
3974 | /* | |
3975 | * Sign-extend 32-bit mode address offsets that have bit 31 set and | |
3976 | * all higher bits unset. | |
3977 | */ | |
3978 | static void | |
3979 | normalize_address_expr (expressionS *ex) | |
3980 | { | |
3981 | if (((ex->X_op == O_constant && HAVE_32BIT_ADDRESSES) | |
3982 | || (ex->X_op == O_symbol && HAVE_32BIT_SYMBOLS)) | |
3983 | && IS_ZEXT_32BIT_NUM (ex->X_add_number)) | |
3984 | ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000) | |
3985 | - 0x80000000); | |
3986 | } | |
3987 | ||
438c16b8 TS |
3988 | /* |
3989 | * Generate a "jalr" instruction with a relocation hint to the called | |
3990 | * function. This occurs in NewABI PIC code. | |
3991 | */ | |
3992 | static void | |
67c0d1eb | 3993 | macro_build_jalr (expressionS *ep) |
438c16b8 | 3994 | { |
685736be | 3995 | char *f = NULL; |
b34976b6 | 3996 | |
1180b5a4 | 3997 | if (MIPS_JALR_HINT_P (ep)) |
f21f8242 | 3998 | { |
cc3d92a5 | 3999 | frag_grow (8); |
f21f8242 AO |
4000 | f = frag_more (0); |
4001 | } | |
67c0d1eb | 4002 | macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG); |
1180b5a4 | 4003 | if (MIPS_JALR_HINT_P (ep)) |
f21f8242 | 4004 | fix_new_exp (frag_now, f - frag_now->fr_literal, |
a105a300 | 4005 | 4, ep, FALSE, BFD_RELOC_MIPS_JALR); |
438c16b8 TS |
4006 | } |
4007 | ||
252b5132 RH |
4008 | /* |
4009 | * Generate a "lui" instruction. | |
4010 | */ | |
4011 | static void | |
67c0d1eb | 4012 | macro_build_lui (expressionS *ep, int regnum) |
252b5132 RH |
4013 | { |
4014 | expressionS high_expr; | |
1e915849 | 4015 | const struct mips_opcode *mo; |
252b5132 | 4016 | struct mips_cl_insn insn; |
f6688943 TS |
4017 | bfd_reloc_code_real_type r[3] |
4018 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
5a38dc70 AM |
4019 | const char *name = "lui"; |
4020 | const char *fmt = "t,u"; | |
252b5132 | 4021 | |
9c2799c2 | 4022 | gas_assert (! mips_opts.mips16); |
252b5132 | 4023 | |
4d7206a2 | 4024 | high_expr = *ep; |
252b5132 RH |
4025 | |
4026 | if (high_expr.X_op == O_constant) | |
4027 | { | |
54f4ddb3 | 4028 | /* We can compute the instruction now without a relocation entry. */ |
e7d556df TS |
4029 | high_expr.X_add_number = ((high_expr.X_add_number + 0x8000) |
4030 | >> 16) & 0xffff; | |
f6688943 | 4031 | *r = BFD_RELOC_UNUSED; |
252b5132 | 4032 | } |
78e1bb40 | 4033 | else |
252b5132 | 4034 | { |
9c2799c2 | 4035 | gas_assert (ep->X_op == O_symbol); |
bbe506e8 TS |
4036 | /* _gp_disp is a special case, used from s_cpload. |
4037 | __gnu_local_gp is used if mips_no_shared. */ | |
9c2799c2 | 4038 | gas_assert (mips_pic == NO_PIC |
78e1bb40 | 4039 | || (! HAVE_NEWABI |
aa6975fb ILT |
4040 | && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0) |
4041 | || (! mips_in_shared | |
bbe506e8 TS |
4042 | && strcmp (S_GET_NAME (ep->X_add_symbol), |
4043 | "__gnu_local_gp") == 0)); | |
f6688943 | 4044 | *r = BFD_RELOC_HI16_S; |
252b5132 RH |
4045 | } |
4046 | ||
1e915849 | 4047 | mo = hash_find (op_hash, name); |
9c2799c2 NC |
4048 | gas_assert (strcmp (name, mo->name) == 0); |
4049 | gas_assert (strcmp (fmt, mo->args) == 0); | |
1e915849 | 4050 | create_insn (&insn, mo); |
252b5132 | 4051 | |
bf12938e RS |
4052 | insn.insn_opcode = insn.insn_mo->match; |
4053 | INSERT_OPERAND (RT, insn, regnum); | |
f6688943 | 4054 | if (*r == BFD_RELOC_UNUSED) |
252b5132 RH |
4055 | { |
4056 | insn.insn_opcode |= high_expr.X_add_number; | |
4d7206a2 | 4057 | append_insn (&insn, NULL, r); |
252b5132 RH |
4058 | } |
4059 | else | |
4d7206a2 | 4060 | append_insn (&insn, &high_expr, r); |
252b5132 RH |
4061 | } |
4062 | ||
885add95 CD |
4063 | /* Generate a sequence of instructions to do a load or store from a constant |
4064 | offset off of a base register (breg) into/from a target register (treg), | |
4065 | using AT if necessary. */ | |
4066 | static void | |
67c0d1eb RS |
4067 | macro_build_ldst_constoffset (expressionS *ep, const char *op, |
4068 | int treg, int breg, int dbl) | |
885add95 | 4069 | { |
9c2799c2 | 4070 | gas_assert (ep->X_op == O_constant); |
885add95 | 4071 | |
256ab948 | 4072 | /* Sign-extending 32-bit constants makes their handling easier. */ |
2051e8c4 MR |
4073 | if (!dbl) |
4074 | normalize_constant_expr (ep); | |
256ab948 | 4075 | |
67c1ffbe | 4076 | /* Right now, this routine can only handle signed 32-bit constants. */ |
ecd13cd3 | 4077 | if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000)) |
885add95 CD |
4078 | as_warn (_("operand overflow")); |
4079 | ||
4080 | if (IS_SEXT_16BIT_NUM(ep->X_add_number)) | |
4081 | { | |
4082 | /* Signed 16-bit offset will fit in the op. Easy! */ | |
67c0d1eb | 4083 | macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
885add95 CD |
4084 | } |
4085 | else | |
4086 | { | |
4087 | /* 32-bit offset, need multiple instructions and AT, like: | |
4088 | lui $tempreg,const_hi (BFD_RELOC_HI16_S) | |
4089 | addu $tempreg,$tempreg,$breg | |
4090 | <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16) | |
4091 | to handle the complete offset. */ | |
67c0d1eb RS |
4092 | macro_build_lui (ep, AT); |
4093 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); | |
4094 | macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, AT); | |
885add95 | 4095 | |
741fe287 | 4096 | if (!mips_opts.at) |
8fc2e39e | 4097 | as_bad (_("Macro used $at after \".set noat\"")); |
885add95 CD |
4098 | } |
4099 | } | |
4100 | ||
252b5132 RH |
4101 | /* set_at() |
4102 | * Generates code to set the $at register to true (one) | |
4103 | * if reg is less than the immediate expression. | |
4104 | */ | |
4105 | static void | |
67c0d1eb | 4106 | set_at (int reg, int unsignedp) |
252b5132 RH |
4107 | { |
4108 | if (imm_expr.X_op == O_constant | |
4109 | && imm_expr.X_add_number >= -0x8000 | |
4110 | && imm_expr.X_add_number < 0x8000) | |
67c0d1eb RS |
4111 | macro_build (&imm_expr, unsignedp ? "sltiu" : "slti", "t,r,j", |
4112 | AT, reg, BFD_RELOC_LO16); | |
252b5132 RH |
4113 | else |
4114 | { | |
67c0d1eb RS |
4115 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
4116 | macro_build (NULL, unsignedp ? "sltu" : "slt", "d,v,t", AT, reg, AT); | |
252b5132 RH |
4117 | } |
4118 | } | |
4119 | ||
4120 | /* Warn if an expression is not a constant. */ | |
4121 | ||
4122 | static void | |
17a2f251 | 4123 | check_absolute_expr (struct mips_cl_insn *ip, expressionS *ex) |
252b5132 RH |
4124 | { |
4125 | if (ex->X_op == O_big) | |
4126 | as_bad (_("unsupported large constant")); | |
4127 | else if (ex->X_op != O_constant) | |
9ee2a2d4 MR |
4128 | as_bad (_("Instruction %s requires absolute expression"), |
4129 | ip->insn_mo->name); | |
13757d0c | 4130 | |
9ee2a2d4 MR |
4131 | if (HAVE_32BIT_GPRS) |
4132 | normalize_constant_expr (ex); | |
252b5132 RH |
4133 | } |
4134 | ||
4135 | /* Count the leading zeroes by performing a binary chop. This is a | |
4136 | bulky bit of source, but performance is a LOT better for the | |
4137 | majority of values than a simple loop to count the bits: | |
4138 | for (lcnt = 0; (lcnt < 32); lcnt++) | |
4139 | if ((v) & (1 << (31 - lcnt))) | |
4140 | break; | |
4141 | However it is not code size friendly, and the gain will drop a bit | |
4142 | on certain cached systems. | |
4143 | */ | |
4144 | #define COUNT_TOP_ZEROES(v) \ | |
4145 | (((v) & ~0xffff) == 0 \ | |
4146 | ? ((v) & ~0xff) == 0 \ | |
4147 | ? ((v) & ~0xf) == 0 \ | |
4148 | ? ((v) & ~0x3) == 0 \ | |
4149 | ? ((v) & ~0x1) == 0 \ | |
4150 | ? !(v) \ | |
4151 | ? 32 \ | |
4152 | : 31 \ | |
4153 | : 30 \ | |
4154 | : ((v) & ~0x7) == 0 \ | |
4155 | ? 29 \ | |
4156 | : 28 \ | |
4157 | : ((v) & ~0x3f) == 0 \ | |
4158 | ? ((v) & ~0x1f) == 0 \ | |
4159 | ? 27 \ | |
4160 | : 26 \ | |
4161 | : ((v) & ~0x7f) == 0 \ | |
4162 | ? 25 \ | |
4163 | : 24 \ | |
4164 | : ((v) & ~0xfff) == 0 \ | |
4165 | ? ((v) & ~0x3ff) == 0 \ | |
4166 | ? ((v) & ~0x1ff) == 0 \ | |
4167 | ? 23 \ | |
4168 | : 22 \ | |
4169 | : ((v) & ~0x7ff) == 0 \ | |
4170 | ? 21 \ | |
4171 | : 20 \ | |
4172 | : ((v) & ~0x3fff) == 0 \ | |
4173 | ? ((v) & ~0x1fff) == 0 \ | |
4174 | ? 19 \ | |
4175 | : 18 \ | |
4176 | : ((v) & ~0x7fff) == 0 \ | |
4177 | ? 17 \ | |
4178 | : 16 \ | |
4179 | : ((v) & ~0xffffff) == 0 \ | |
4180 | ? ((v) & ~0xfffff) == 0 \ | |
4181 | ? ((v) & ~0x3ffff) == 0 \ | |
4182 | ? ((v) & ~0x1ffff) == 0 \ | |
4183 | ? 15 \ | |
4184 | : 14 \ | |
4185 | : ((v) & ~0x7ffff) == 0 \ | |
4186 | ? 13 \ | |
4187 | : 12 \ | |
4188 | : ((v) & ~0x3fffff) == 0 \ | |
4189 | ? ((v) & ~0x1fffff) == 0 \ | |
4190 | ? 11 \ | |
4191 | : 10 \ | |
4192 | : ((v) & ~0x7fffff) == 0 \ | |
4193 | ? 9 \ | |
4194 | : 8 \ | |
4195 | : ((v) & ~0xfffffff) == 0 \ | |
4196 | ? ((v) & ~0x3ffffff) == 0 \ | |
4197 | ? ((v) & ~0x1ffffff) == 0 \ | |
4198 | ? 7 \ | |
4199 | : 6 \ | |
4200 | : ((v) & ~0x7ffffff) == 0 \ | |
4201 | ? 5 \ | |
4202 | : 4 \ | |
4203 | : ((v) & ~0x3fffffff) == 0 \ | |
4204 | ? ((v) & ~0x1fffffff) == 0 \ | |
4205 | ? 3 \ | |
4206 | : 2 \ | |
4207 | : ((v) & ~0x7fffffff) == 0 \ | |
4208 | ? 1 \ | |
4209 | : 0) | |
4210 | ||
4211 | /* load_register() | |
67c1ffbe | 4212 | * This routine generates the least number of instructions necessary to load |
252b5132 RH |
4213 | * an absolute expression value into a register. |
4214 | */ | |
4215 | static void | |
67c0d1eb | 4216 | load_register (int reg, expressionS *ep, int dbl) |
252b5132 RH |
4217 | { |
4218 | int freg; | |
4219 | expressionS hi32, lo32; | |
4220 | ||
4221 | if (ep->X_op != O_big) | |
4222 | { | |
9c2799c2 | 4223 | gas_assert (ep->X_op == O_constant); |
256ab948 TS |
4224 | |
4225 | /* Sign-extending 32-bit constants makes their handling easier. */ | |
2051e8c4 MR |
4226 | if (!dbl) |
4227 | normalize_constant_expr (ep); | |
256ab948 TS |
4228 | |
4229 | if (IS_SEXT_16BIT_NUM (ep->X_add_number)) | |
252b5132 RH |
4230 | { |
4231 | /* We can handle 16 bit signed values with an addiu to | |
4232 | $zero. No need to ever use daddiu here, since $zero and | |
4233 | the result are always correct in 32 bit mode. */ | |
67c0d1eb | 4234 | macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
4235 | return; |
4236 | } | |
4237 | else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000) | |
4238 | { | |
4239 | /* We can handle 16 bit unsigned values with an ori to | |
4240 | $zero. */ | |
67c0d1eb | 4241 | macro_build (ep, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
4242 | return; |
4243 | } | |
256ab948 | 4244 | else if ((IS_SEXT_32BIT_NUM (ep->X_add_number))) |
252b5132 RH |
4245 | { |
4246 | /* 32 bit values require an lui. */ | |
67c0d1eb | 4247 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_HI16); |
252b5132 | 4248 | if ((ep->X_add_number & 0xffff) != 0) |
67c0d1eb | 4249 | macro_build (ep, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16); |
252b5132 RH |
4250 | return; |
4251 | } | |
4252 | } | |
4253 | ||
4254 | /* The value is larger than 32 bits. */ | |
4255 | ||
2051e8c4 | 4256 | if (!dbl || HAVE_32BIT_GPRS) |
252b5132 | 4257 | { |
55e08f71 NC |
4258 | char value[32]; |
4259 | ||
4260 | sprintf_vma (value, ep->X_add_number); | |
20e1fcfd | 4261 | as_bad (_("Number (0x%s) larger than 32 bits"), value); |
67c0d1eb | 4262 | macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
4263 | return; |
4264 | } | |
4265 | ||
4266 | if (ep->X_op != O_big) | |
4267 | { | |
4268 | hi32 = *ep; | |
4269 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
4270 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
4271 | hi32.X_add_number &= 0xffffffff; | |
4272 | lo32 = *ep; | |
4273 | lo32.X_add_number &= 0xffffffff; | |
4274 | } | |
4275 | else | |
4276 | { | |
9c2799c2 | 4277 | gas_assert (ep->X_add_number > 2); |
252b5132 RH |
4278 | if (ep->X_add_number == 3) |
4279 | generic_bignum[3] = 0; | |
4280 | else if (ep->X_add_number > 4) | |
4281 | as_bad (_("Number larger than 64 bits")); | |
4282 | lo32.X_op = O_constant; | |
4283 | lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16); | |
4284 | hi32.X_op = O_constant; | |
4285 | hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16); | |
4286 | } | |
4287 | ||
4288 | if (hi32.X_add_number == 0) | |
4289 | freg = 0; | |
4290 | else | |
4291 | { | |
4292 | int shift, bit; | |
4293 | unsigned long hi, lo; | |
4294 | ||
956cd1d6 | 4295 | if (hi32.X_add_number == (offsetT) 0xffffffff) |
beae10d5 KH |
4296 | { |
4297 | if ((lo32.X_add_number & 0xffff8000) == 0xffff8000) | |
4298 | { | |
67c0d1eb | 4299 | macro_build (&lo32, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
beae10d5 KH |
4300 | return; |
4301 | } | |
4302 | if (lo32.X_add_number & 0x80000000) | |
4303 | { | |
67c0d1eb | 4304 | macro_build (&lo32, "lui", "t,u", reg, BFD_RELOC_HI16); |
252b5132 | 4305 | if (lo32.X_add_number & 0xffff) |
67c0d1eb | 4306 | macro_build (&lo32, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16); |
beae10d5 KH |
4307 | return; |
4308 | } | |
4309 | } | |
252b5132 RH |
4310 | |
4311 | /* Check for 16bit shifted constant. We know that hi32 is | |
4312 | non-zero, so start the mask on the first bit of the hi32 | |
4313 | value. */ | |
4314 | shift = 17; | |
4315 | do | |
beae10d5 KH |
4316 | { |
4317 | unsigned long himask, lomask; | |
4318 | ||
4319 | if (shift < 32) | |
4320 | { | |
4321 | himask = 0xffff >> (32 - shift); | |
4322 | lomask = (0xffff << shift) & 0xffffffff; | |
4323 | } | |
4324 | else | |
4325 | { | |
4326 | himask = 0xffff << (shift - 32); | |
4327 | lomask = 0; | |
4328 | } | |
4329 | if ((hi32.X_add_number & ~(offsetT) himask) == 0 | |
4330 | && (lo32.X_add_number & ~(offsetT) lomask) == 0) | |
4331 | { | |
4332 | expressionS tmp; | |
4333 | ||
4334 | tmp.X_op = O_constant; | |
4335 | if (shift < 32) | |
4336 | tmp.X_add_number = ((hi32.X_add_number << (32 - shift)) | |
4337 | | (lo32.X_add_number >> shift)); | |
4338 | else | |
4339 | tmp.X_add_number = hi32.X_add_number >> (shift - 32); | |
67c0d1eb RS |
4340 | macro_build (&tmp, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16); |
4341 | macro_build (NULL, (shift >= 32) ? "dsll32" : "dsll", "d,w,<", | |
4342 | reg, reg, (shift >= 32) ? shift - 32 : shift); | |
beae10d5 KH |
4343 | return; |
4344 | } | |
f9419b05 | 4345 | ++shift; |
beae10d5 KH |
4346 | } |
4347 | while (shift <= (64 - 16)); | |
252b5132 RH |
4348 | |
4349 | /* Find the bit number of the lowest one bit, and store the | |
4350 | shifted value in hi/lo. */ | |
4351 | hi = (unsigned long) (hi32.X_add_number & 0xffffffff); | |
4352 | lo = (unsigned long) (lo32.X_add_number & 0xffffffff); | |
4353 | if (lo != 0) | |
4354 | { | |
4355 | bit = 0; | |
4356 | while ((lo & 1) == 0) | |
4357 | { | |
4358 | lo >>= 1; | |
4359 | ++bit; | |
4360 | } | |
4361 | lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit); | |
4362 | hi >>= bit; | |
4363 | } | |
4364 | else | |
4365 | { | |
4366 | bit = 32; | |
4367 | while ((hi & 1) == 0) | |
4368 | { | |
4369 | hi >>= 1; | |
4370 | ++bit; | |
4371 | } | |
4372 | lo = hi; | |
4373 | hi = 0; | |
4374 | } | |
4375 | ||
4376 | /* Optimize if the shifted value is a (power of 2) - 1. */ | |
4377 | if ((hi == 0 && ((lo + 1) & lo) == 0) | |
4378 | || (lo == 0xffffffff && ((hi + 1) & hi) == 0)) | |
beae10d5 KH |
4379 | { |
4380 | shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number); | |
252b5132 | 4381 | if (shift != 0) |
beae10d5 | 4382 | { |
252b5132 RH |
4383 | expressionS tmp; |
4384 | ||
4385 | /* This instruction will set the register to be all | |
4386 | ones. */ | |
beae10d5 KH |
4387 | tmp.X_op = O_constant; |
4388 | tmp.X_add_number = (offsetT) -1; | |
67c0d1eb | 4389 | macro_build (&tmp, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
beae10d5 KH |
4390 | if (bit != 0) |
4391 | { | |
4392 | bit += shift; | |
67c0d1eb RS |
4393 | macro_build (NULL, (bit >= 32) ? "dsll32" : "dsll", "d,w,<", |
4394 | reg, reg, (bit >= 32) ? bit - 32 : bit); | |
beae10d5 | 4395 | } |
67c0d1eb RS |
4396 | macro_build (NULL, (shift >= 32) ? "dsrl32" : "dsrl", "d,w,<", |
4397 | reg, reg, (shift >= 32) ? shift - 32 : shift); | |
beae10d5 KH |
4398 | return; |
4399 | } | |
4400 | } | |
252b5132 RH |
4401 | |
4402 | /* Sign extend hi32 before calling load_register, because we can | |
4403 | generally get better code when we load a sign extended value. */ | |
4404 | if ((hi32.X_add_number & 0x80000000) != 0) | |
beae10d5 | 4405 | hi32.X_add_number |= ~(offsetT) 0xffffffff; |
67c0d1eb | 4406 | load_register (reg, &hi32, 0); |
252b5132 RH |
4407 | freg = reg; |
4408 | } | |
4409 | if ((lo32.X_add_number & 0xffff0000) == 0) | |
4410 | { | |
4411 | if (freg != 0) | |
4412 | { | |
67c0d1eb | 4413 | macro_build (NULL, "dsll32", "d,w,<", reg, freg, 0); |
252b5132 RH |
4414 | freg = reg; |
4415 | } | |
4416 | } | |
4417 | else | |
4418 | { | |
4419 | expressionS mid16; | |
4420 | ||
956cd1d6 | 4421 | if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff)) |
beae10d5 | 4422 | { |
67c0d1eb RS |
4423 | macro_build (&lo32, "lui", "t,u", reg, BFD_RELOC_HI16); |
4424 | macro_build (NULL, "dsrl32", "d,w,<", reg, reg, 0); | |
beae10d5 KH |
4425 | return; |
4426 | } | |
252b5132 RH |
4427 | |
4428 | if (freg != 0) | |
4429 | { | |
67c0d1eb | 4430 | macro_build (NULL, "dsll", "d,w,<", reg, freg, 16); |
252b5132 RH |
4431 | freg = reg; |
4432 | } | |
4433 | mid16 = lo32; | |
4434 | mid16.X_add_number >>= 16; | |
67c0d1eb RS |
4435 | macro_build (&mid16, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16); |
4436 | macro_build (NULL, "dsll", "d,w,<", reg, reg, 16); | |
252b5132 RH |
4437 | freg = reg; |
4438 | } | |
4439 | if ((lo32.X_add_number & 0xffff) != 0) | |
67c0d1eb | 4440 | macro_build (&lo32, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16); |
252b5132 RH |
4441 | } |
4442 | ||
269137b2 TS |
4443 | static inline void |
4444 | load_delay_nop (void) | |
4445 | { | |
4446 | if (!gpr_interlocks) | |
4447 | macro_build (NULL, "nop", ""); | |
4448 | } | |
4449 | ||
252b5132 RH |
4450 | /* Load an address into a register. */ |
4451 | ||
4452 | static void | |
67c0d1eb | 4453 | load_address (int reg, expressionS *ep, int *used_at) |
252b5132 | 4454 | { |
252b5132 RH |
4455 | if (ep->X_op != O_constant |
4456 | && ep->X_op != O_symbol) | |
4457 | { | |
4458 | as_bad (_("expression too complex")); | |
4459 | ep->X_op = O_constant; | |
4460 | } | |
4461 | ||
4462 | if (ep->X_op == O_constant) | |
4463 | { | |
67c0d1eb | 4464 | load_register (reg, ep, HAVE_64BIT_ADDRESSES); |
252b5132 RH |
4465 | return; |
4466 | } | |
4467 | ||
4468 | if (mips_pic == NO_PIC) | |
4469 | { | |
4470 | /* If this is a reference to a GP relative symbol, we want | |
cdf6fd85 | 4471 | addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
4472 | Otherwise we want |
4473 | lui $reg,<sym> (BFD_RELOC_HI16_S) | |
4474 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
d6bc6245 | 4475 | If we have an addend, we always use the latter form. |
76b3015f | 4476 | |
d6bc6245 TS |
4477 | With 64bit address space and a usable $at we want |
4478 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
4479 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
4480 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
4481 | daddiu $at,<sym> (BFD_RELOC_LO16) | |
4482 | dsll32 $reg,0 | |
3a482fd5 | 4483 | daddu $reg,$reg,$at |
76b3015f | 4484 | |
c03099e6 | 4485 | If $at is already in use, we use a path which is suboptimal |
d6bc6245 TS |
4486 | on superscalar processors. |
4487 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
4488 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
4489 | dsll $reg,16 | |
4490 | daddiu $reg,<sym> (BFD_RELOC_HI16_S) | |
4491 | dsll $reg,16 | |
4492 | daddiu $reg,<sym> (BFD_RELOC_LO16) | |
6caf9ef4 TS |
4493 | |
4494 | For GP relative symbols in 64bit address space we can use | |
4495 | the same sequence as in 32bit address space. */ | |
aed1a261 | 4496 | if (HAVE_64BIT_SYMBOLS) |
d6bc6245 | 4497 | { |
6caf9ef4 TS |
4498 | if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET |
4499 | && !nopic_need_relax (ep->X_add_symbol, 1)) | |
4500 | { | |
4501 | relax_start (ep->X_add_symbol); | |
4502 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, | |
4503 | mips_gp_register, BFD_RELOC_GPREL16); | |
4504 | relax_switch (); | |
4505 | } | |
d6bc6245 | 4506 | |
741fe287 | 4507 | if (*used_at == 0 && mips_opts.at) |
d6bc6245 | 4508 | { |
67c0d1eb RS |
4509 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_HIGHEST); |
4510 | macro_build (ep, "lui", "t,u", AT, BFD_RELOC_HI16_S); | |
4511 | macro_build (ep, "daddiu", "t,r,j", reg, reg, | |
4512 | BFD_RELOC_MIPS_HIGHER); | |
4513 | macro_build (ep, "daddiu", "t,r,j", AT, AT, BFD_RELOC_LO16); | |
4514 | macro_build (NULL, "dsll32", "d,w,<", reg, reg, 0); | |
4515 | macro_build (NULL, "daddu", "d,v,t", reg, reg, AT); | |
d6bc6245 TS |
4516 | *used_at = 1; |
4517 | } | |
4518 | else | |
4519 | { | |
67c0d1eb RS |
4520 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_HIGHEST); |
4521 | macro_build (ep, "daddiu", "t,r,j", reg, reg, | |
4522 | BFD_RELOC_MIPS_HIGHER); | |
4523 | macro_build (NULL, "dsll", "d,w,<", reg, reg, 16); | |
4524 | macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_HI16_S); | |
4525 | macro_build (NULL, "dsll", "d,w,<", reg, reg, 16); | |
4526 | macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_LO16); | |
d6bc6245 | 4527 | } |
6caf9ef4 TS |
4528 | |
4529 | if (mips_relax.sequence) | |
4530 | relax_end (); | |
d6bc6245 | 4531 | } |
252b5132 RH |
4532 | else |
4533 | { | |
d6bc6245 | 4534 | if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 4535 | && !nopic_need_relax (ep->X_add_symbol, 1)) |
d6bc6245 | 4536 | { |
4d7206a2 | 4537 | relax_start (ep->X_add_symbol); |
67c0d1eb | 4538 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, |
17a2f251 | 4539 | mips_gp_register, BFD_RELOC_GPREL16); |
4d7206a2 | 4540 | relax_switch (); |
d6bc6245 | 4541 | } |
67c0d1eb RS |
4542 | macro_build_lui (ep, reg); |
4543 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", | |
4544 | reg, reg, BFD_RELOC_LO16); | |
4d7206a2 RS |
4545 | if (mips_relax.sequence) |
4546 | relax_end (); | |
d6bc6245 | 4547 | } |
252b5132 | 4548 | } |
0a44bf69 | 4549 | else if (!mips_big_got) |
252b5132 RH |
4550 | { |
4551 | expressionS ex; | |
4552 | ||
4553 | /* If this is a reference to an external symbol, we want | |
4554 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4555 | Otherwise we want | |
4556 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4557 | nop | |
4558 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
f5040a92 AO |
4559 | If there is a constant, it must be added in after. |
4560 | ||
ed6fb7bd | 4561 | If we have NewABI, we want |
f5040a92 AO |
4562 | lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP) |
4563 | unless we're referencing a global symbol with a non-zero | |
4564 | offset, in which case cst must be added separately. */ | |
ed6fb7bd SC |
4565 | if (HAVE_NEWABI) |
4566 | { | |
f5040a92 AO |
4567 | if (ep->X_add_number) |
4568 | { | |
4d7206a2 | 4569 | ex.X_add_number = ep->X_add_number; |
f5040a92 | 4570 | ep->X_add_number = 0; |
4d7206a2 | 4571 | relax_start (ep->X_add_symbol); |
67c0d1eb RS |
4572 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
4573 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
4574 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) |
4575 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4576 | ex.X_op = O_constant; | |
67c0d1eb | 4577 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 4578 | reg, reg, BFD_RELOC_LO16); |
f5040a92 | 4579 | ep->X_add_number = ex.X_add_number; |
4d7206a2 | 4580 | relax_switch (); |
f5040a92 | 4581 | } |
67c0d1eb | 4582 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 4583 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); |
4d7206a2 RS |
4584 | if (mips_relax.sequence) |
4585 | relax_end (); | |
ed6fb7bd SC |
4586 | } |
4587 | else | |
4588 | { | |
f5040a92 AO |
4589 | ex.X_add_number = ep->X_add_number; |
4590 | ep->X_add_number = 0; | |
67c0d1eb RS |
4591 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
4592 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 4593 | load_delay_nop (); |
4d7206a2 RS |
4594 | relax_start (ep->X_add_symbol); |
4595 | relax_switch (); | |
67c0d1eb | 4596 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
17a2f251 | 4597 | BFD_RELOC_LO16); |
4d7206a2 | 4598 | relax_end (); |
ed6fb7bd | 4599 | |
f5040a92 AO |
4600 | if (ex.X_add_number != 0) |
4601 | { | |
4602 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
4603 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4604 | ex.X_op = O_constant; | |
67c0d1eb | 4605 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 4606 | reg, reg, BFD_RELOC_LO16); |
f5040a92 | 4607 | } |
252b5132 RH |
4608 | } |
4609 | } | |
0a44bf69 | 4610 | else if (mips_big_got) |
252b5132 RH |
4611 | { |
4612 | expressionS ex; | |
252b5132 RH |
4613 | |
4614 | /* This is the large GOT case. If this is a reference to an | |
4615 | external symbol, we want | |
4616 | lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
4617 | addu $reg,$reg,$gp | |
4618 | lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16) | |
f5040a92 AO |
4619 | |
4620 | Otherwise, for a reference to a local symbol in old ABI, we want | |
252b5132 RH |
4621 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) |
4622 | nop | |
4623 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
684022ea | 4624 | If there is a constant, it must be added in after. |
f5040a92 AO |
4625 | |
4626 | In the NewABI, for local symbols, with or without offsets, we want: | |
438c16b8 TS |
4627 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) |
4628 | addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) | |
f5040a92 | 4629 | */ |
438c16b8 TS |
4630 | if (HAVE_NEWABI) |
4631 | { | |
4d7206a2 | 4632 | ex.X_add_number = ep->X_add_number; |
f5040a92 | 4633 | ep->X_add_number = 0; |
4d7206a2 | 4634 | relax_start (ep->X_add_symbol); |
67c0d1eb RS |
4635 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_GOT_HI16); |
4636 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
4637 | reg, reg, mips_gp_register); | |
4638 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", | |
4639 | reg, BFD_RELOC_MIPS_GOT_LO16, reg); | |
f5040a92 AO |
4640 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) |
4641 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4642 | else if (ex.X_add_number) | |
4643 | { | |
4644 | ex.X_op = O_constant; | |
67c0d1eb RS |
4645 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
4646 | BFD_RELOC_LO16); | |
f5040a92 AO |
4647 | } |
4648 | ||
4649 | ep->X_add_number = ex.X_add_number; | |
4d7206a2 | 4650 | relax_switch (); |
67c0d1eb | 4651 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 4652 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); |
67c0d1eb RS |
4653 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
4654 | BFD_RELOC_MIPS_GOT_OFST); | |
4d7206a2 | 4655 | relax_end (); |
438c16b8 | 4656 | } |
252b5132 | 4657 | else |
438c16b8 | 4658 | { |
f5040a92 AO |
4659 | ex.X_add_number = ep->X_add_number; |
4660 | ep->X_add_number = 0; | |
4d7206a2 | 4661 | relax_start (ep->X_add_symbol); |
67c0d1eb RS |
4662 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_GOT_HI16); |
4663 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
4664 | reg, reg, mips_gp_register); | |
4665 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", | |
4666 | reg, BFD_RELOC_MIPS_GOT_LO16, reg); | |
4d7206a2 RS |
4667 | relax_switch (); |
4668 | if (reg_needs_delay (mips_gp_register)) | |
438c16b8 TS |
4669 | { |
4670 | /* We need a nop before loading from $gp. This special | |
4671 | check is required because the lui which starts the main | |
4672 | instruction stream does not refer to $gp, and so will not | |
4673 | insert the nop which may be required. */ | |
67c0d1eb | 4674 | macro_build (NULL, "nop", ""); |
438c16b8 | 4675 | } |
67c0d1eb | 4676 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 4677 | BFD_RELOC_MIPS_GOT16, mips_gp_register); |
269137b2 | 4678 | load_delay_nop (); |
67c0d1eb | 4679 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
17a2f251 | 4680 | BFD_RELOC_LO16); |
4d7206a2 | 4681 | relax_end (); |
438c16b8 | 4682 | |
f5040a92 AO |
4683 | if (ex.X_add_number != 0) |
4684 | { | |
4685 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
4686 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4687 | ex.X_op = O_constant; | |
67c0d1eb RS |
4688 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
4689 | BFD_RELOC_LO16); | |
f5040a92 | 4690 | } |
252b5132 RH |
4691 | } |
4692 | } | |
252b5132 RH |
4693 | else |
4694 | abort (); | |
8fc2e39e | 4695 | |
741fe287 | 4696 | if (!mips_opts.at && *used_at == 1) |
8fc2e39e | 4697 | as_bad (_("Macro used $at after \".set noat\"")); |
252b5132 RH |
4698 | } |
4699 | ||
ea1fb5dc RS |
4700 | /* Move the contents of register SOURCE into register DEST. */ |
4701 | ||
4702 | static void | |
67c0d1eb | 4703 | move_register (int dest, int source) |
ea1fb5dc | 4704 | { |
67c0d1eb RS |
4705 | macro_build (NULL, HAVE_32BIT_GPRS ? "addu" : "daddu", "d,v,t", |
4706 | dest, source, 0); | |
ea1fb5dc RS |
4707 | } |
4708 | ||
4d7206a2 | 4709 | /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where |
f6a22291 MR |
4710 | LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement. |
4711 | The two alternatives are: | |
4d7206a2 RS |
4712 | |
4713 | Global symbol Local sybmol | |
4714 | ------------- ------------ | |
4715 | lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET) | |
4716 | ... ... | |
4717 | addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET) | |
4718 | ||
4719 | load_got_offset emits the first instruction and add_got_offset | |
f6a22291 MR |
4720 | emits the second for a 16-bit offset or add_got_offset_hilo emits |
4721 | a sequence to add a 32-bit offset using a scratch register. */ | |
4d7206a2 RS |
4722 | |
4723 | static void | |
67c0d1eb | 4724 | load_got_offset (int dest, expressionS *local) |
4d7206a2 RS |
4725 | { |
4726 | expressionS global; | |
4727 | ||
4728 | global = *local; | |
4729 | global.X_add_number = 0; | |
4730 | ||
4731 | relax_start (local->X_add_symbol); | |
67c0d1eb RS |
4732 | macro_build (&global, ADDRESS_LOAD_INSN, "t,o(b)", dest, |
4733 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
4d7206a2 | 4734 | relax_switch (); |
67c0d1eb RS |
4735 | macro_build (local, ADDRESS_LOAD_INSN, "t,o(b)", dest, |
4736 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
4d7206a2 RS |
4737 | relax_end (); |
4738 | } | |
4739 | ||
4740 | static void | |
67c0d1eb | 4741 | add_got_offset (int dest, expressionS *local) |
4d7206a2 RS |
4742 | { |
4743 | expressionS global; | |
4744 | ||
4745 | global.X_op = O_constant; | |
4746 | global.X_op_symbol = NULL; | |
4747 | global.X_add_symbol = NULL; | |
4748 | global.X_add_number = local->X_add_number; | |
4749 | ||
4750 | relax_start (local->X_add_symbol); | |
67c0d1eb | 4751 | macro_build (&global, ADDRESS_ADDI_INSN, "t,r,j", |
4d7206a2 RS |
4752 | dest, dest, BFD_RELOC_LO16); |
4753 | relax_switch (); | |
67c0d1eb | 4754 | macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", dest, dest, BFD_RELOC_LO16); |
4d7206a2 RS |
4755 | relax_end (); |
4756 | } | |
4757 | ||
f6a22291 MR |
4758 | static void |
4759 | add_got_offset_hilo (int dest, expressionS *local, int tmp) | |
4760 | { | |
4761 | expressionS global; | |
4762 | int hold_mips_optimize; | |
4763 | ||
4764 | global.X_op = O_constant; | |
4765 | global.X_op_symbol = NULL; | |
4766 | global.X_add_symbol = NULL; | |
4767 | global.X_add_number = local->X_add_number; | |
4768 | ||
4769 | relax_start (local->X_add_symbol); | |
4770 | load_register (tmp, &global, HAVE_64BIT_ADDRESSES); | |
4771 | relax_switch (); | |
4772 | /* Set mips_optimize around the lui instruction to avoid | |
4773 | inserting an unnecessary nop after the lw. */ | |
4774 | hold_mips_optimize = mips_optimize; | |
4775 | mips_optimize = 2; | |
4776 | macro_build_lui (&global, tmp); | |
4777 | mips_optimize = hold_mips_optimize; | |
4778 | macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", tmp, tmp, BFD_RELOC_LO16); | |
4779 | relax_end (); | |
4780 | ||
4781 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dest, dest, tmp); | |
4782 | } | |
4783 | ||
252b5132 RH |
4784 | /* |
4785 | * Build macros | |
4786 | * This routine implements the seemingly endless macro or synthesized | |
4787 | * instructions and addressing modes in the mips assembly language. Many | |
4788 | * of these macros are simple and are similar to each other. These could | |
67c1ffbe | 4789 | * probably be handled by some kind of table or grammar approach instead of |
252b5132 RH |
4790 | * this verbose method. Others are not simple macros but are more like |
4791 | * optimizing code generation. | |
4792 | * One interesting optimization is when several store macros appear | |
67c1ffbe | 4793 | * consecutively that would load AT with the upper half of the same address. |
252b5132 RH |
4794 | * The ensuing load upper instructions are ommited. This implies some kind |
4795 | * of global optimization. We currently only optimize within a single macro. | |
4796 | * For many of the load and store macros if the address is specified as a | |
4797 | * constant expression in the first 64k of memory (ie ld $2,0x4000c) we | |
4798 | * first load register 'at' with zero and use it as the base register. The | |
4799 | * mips assembler simply uses register $zero. Just one tiny optimization | |
4800 | * we're missing. | |
4801 | */ | |
4802 | static void | |
17a2f251 | 4803 | macro (struct mips_cl_insn *ip) |
252b5132 | 4804 | { |
741fe287 MR |
4805 | unsigned int treg, sreg, dreg, breg; |
4806 | unsigned int tempreg; | |
252b5132 | 4807 | int mask; |
43841e91 | 4808 | int used_at = 0; |
252b5132 RH |
4809 | expressionS expr1; |
4810 | const char *s; | |
4811 | const char *s2; | |
4812 | const char *fmt; | |
4813 | int likely = 0; | |
4814 | int dbl = 0; | |
4815 | int coproc = 0; | |
4816 | int lr = 0; | |
4817 | int imm = 0; | |
1abe91b1 | 4818 | int call = 0; |
252b5132 | 4819 | int off; |
67c0d1eb | 4820 | offsetT maxnum; |
252b5132 | 4821 | bfd_reloc_code_real_type r; |
252b5132 RH |
4822 | int hold_mips_optimize; |
4823 | ||
9c2799c2 | 4824 | gas_assert (! mips_opts.mips16); |
252b5132 | 4825 | |
bbea7ebc MR |
4826 | treg = EXTRACT_OPERAND (RT, *ip); |
4827 | dreg = EXTRACT_OPERAND (RD, *ip); | |
4828 | sreg = breg = EXTRACT_OPERAND (RS, *ip); | |
252b5132 RH |
4829 | mask = ip->insn_mo->mask; |
4830 | ||
4831 | expr1.X_op = O_constant; | |
4832 | expr1.X_op_symbol = NULL; | |
4833 | expr1.X_add_symbol = NULL; | |
4834 | expr1.X_add_number = 1; | |
4835 | ||
4836 | switch (mask) | |
4837 | { | |
4838 | case M_DABS: | |
4839 | dbl = 1; | |
4840 | case M_ABS: | |
4841 | /* bgez $a0,.+12 | |
4842 | move v0,$a0 | |
4843 | sub v0,$zero,$a0 | |
4844 | */ | |
4845 | ||
7d10b47d | 4846 | start_noreorder (); |
252b5132 RH |
4847 | |
4848 | expr1.X_add_number = 8; | |
67c0d1eb | 4849 | macro_build (&expr1, "bgez", "s,p", sreg); |
252b5132 | 4850 | if (dreg == sreg) |
a605d2b3 | 4851 | macro_build (NULL, "nop", ""); |
252b5132 | 4852 | else |
67c0d1eb RS |
4853 | move_register (dreg, sreg); |
4854 | macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, 0, sreg); | |
252b5132 | 4855 | |
7d10b47d | 4856 | end_noreorder (); |
8fc2e39e | 4857 | break; |
252b5132 RH |
4858 | |
4859 | case M_ADD_I: | |
4860 | s = "addi"; | |
4861 | s2 = "add"; | |
4862 | goto do_addi; | |
4863 | case M_ADDU_I: | |
4864 | s = "addiu"; | |
4865 | s2 = "addu"; | |
4866 | goto do_addi; | |
4867 | case M_DADD_I: | |
4868 | dbl = 1; | |
4869 | s = "daddi"; | |
4870 | s2 = "dadd"; | |
4871 | goto do_addi; | |
4872 | case M_DADDU_I: | |
4873 | dbl = 1; | |
4874 | s = "daddiu"; | |
4875 | s2 = "daddu"; | |
4876 | do_addi: | |
4877 | if (imm_expr.X_op == O_constant | |
4878 | && imm_expr.X_add_number >= -0x8000 | |
4879 | && imm_expr.X_add_number < 0x8000) | |
4880 | { | |
67c0d1eb | 4881 | macro_build (&imm_expr, s, "t,r,j", treg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 4882 | break; |
252b5132 | 4883 | } |
8fc2e39e | 4884 | used_at = 1; |
67c0d1eb RS |
4885 | load_register (AT, &imm_expr, dbl); |
4886 | macro_build (NULL, s2, "d,v,t", treg, sreg, AT); | |
252b5132 RH |
4887 | break; |
4888 | ||
4889 | case M_AND_I: | |
4890 | s = "andi"; | |
4891 | s2 = "and"; | |
4892 | goto do_bit; | |
4893 | case M_OR_I: | |
4894 | s = "ori"; | |
4895 | s2 = "or"; | |
4896 | goto do_bit; | |
4897 | case M_NOR_I: | |
4898 | s = ""; | |
4899 | s2 = "nor"; | |
4900 | goto do_bit; | |
4901 | case M_XOR_I: | |
4902 | s = "xori"; | |
4903 | s2 = "xor"; | |
4904 | do_bit: | |
4905 | if (imm_expr.X_op == O_constant | |
4906 | && imm_expr.X_add_number >= 0 | |
4907 | && imm_expr.X_add_number < 0x10000) | |
4908 | { | |
4909 | if (mask != M_NOR_I) | |
67c0d1eb | 4910 | macro_build (&imm_expr, s, "t,r,i", treg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
4911 | else |
4912 | { | |
67c0d1eb RS |
4913 | macro_build (&imm_expr, "ori", "t,r,i", |
4914 | treg, sreg, BFD_RELOC_LO16); | |
4915 | macro_build (NULL, "nor", "d,v,t", treg, treg, 0); | |
252b5132 | 4916 | } |
8fc2e39e | 4917 | break; |
252b5132 RH |
4918 | } |
4919 | ||
8fc2e39e | 4920 | used_at = 1; |
67c0d1eb RS |
4921 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
4922 | macro_build (NULL, s2, "d,v,t", treg, sreg, AT); | |
252b5132 RH |
4923 | break; |
4924 | ||
8b082fb1 TS |
4925 | case M_BALIGN: |
4926 | switch (imm_expr.X_add_number) | |
4927 | { | |
4928 | case 0: | |
4929 | macro_build (NULL, "nop", ""); | |
4930 | break; | |
4931 | case 2: | |
4932 | macro_build (NULL, "packrl.ph", "d,s,t", treg, treg, sreg); | |
4933 | break; | |
4934 | default: | |
4935 | macro_build (NULL, "balign", "t,s,2", treg, sreg, | |
90ecf173 | 4936 | (int) imm_expr.X_add_number); |
8b082fb1 TS |
4937 | break; |
4938 | } | |
4939 | break; | |
4940 | ||
252b5132 RH |
4941 | case M_BEQ_I: |
4942 | s = "beq"; | |
4943 | goto beq_i; | |
4944 | case M_BEQL_I: | |
4945 | s = "beql"; | |
4946 | likely = 1; | |
4947 | goto beq_i; | |
4948 | case M_BNE_I: | |
4949 | s = "bne"; | |
4950 | goto beq_i; | |
4951 | case M_BNEL_I: | |
4952 | s = "bnel"; | |
4953 | likely = 1; | |
4954 | beq_i: | |
4955 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4956 | { | |
c80c840e | 4957 | macro_build (&offset_expr, s, "s,t,p", sreg, ZERO); |
8fc2e39e | 4958 | break; |
252b5132 | 4959 | } |
8fc2e39e | 4960 | used_at = 1; |
67c0d1eb RS |
4961 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
4962 | macro_build (&offset_expr, s, "s,t,p", sreg, AT); | |
252b5132 RH |
4963 | break; |
4964 | ||
4965 | case M_BGEL: | |
4966 | likely = 1; | |
4967 | case M_BGE: | |
4968 | if (treg == 0) | |
4969 | { | |
67c0d1eb | 4970 | macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", sreg); |
8fc2e39e | 4971 | break; |
252b5132 RH |
4972 | } |
4973 | if (sreg == 0) | |
4974 | { | |
67c0d1eb | 4975 | macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", treg); |
8fc2e39e | 4976 | break; |
252b5132 | 4977 | } |
8fc2e39e | 4978 | used_at = 1; |
67c0d1eb | 4979 | macro_build (NULL, "slt", "d,v,t", AT, sreg, treg); |
c80c840e | 4980 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, ZERO); |
252b5132 RH |
4981 | break; |
4982 | ||
4983 | case M_BGTL_I: | |
4984 | likely = 1; | |
4985 | case M_BGT_I: | |
90ecf173 | 4986 | /* Check for > max integer. */ |
252b5132 | 4987 | maxnum = 0x7fffffff; |
ca4e0257 | 4988 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
4989 | { |
4990 | maxnum <<= 16; | |
4991 | maxnum |= 0xffff; | |
4992 | maxnum <<= 16; | |
4993 | maxnum |= 0xffff; | |
4994 | } | |
4995 | if (imm_expr.X_op == O_constant | |
4996 | && imm_expr.X_add_number >= maxnum | |
ca4e0257 | 4997 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
4998 | { |
4999 | do_false: | |
90ecf173 | 5000 | /* Result is always false. */ |
252b5132 | 5001 | if (! likely) |
a605d2b3 | 5002 | macro_build (NULL, "nop", ""); |
252b5132 | 5003 | else |
c80c840e | 5004 | macro_build (&offset_expr, "bnel", "s,t,p", ZERO, ZERO); |
8fc2e39e | 5005 | break; |
252b5132 RH |
5006 | } |
5007 | if (imm_expr.X_op != O_constant) | |
5008 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 5009 | ++imm_expr.X_add_number; |
252b5132 RH |
5010 | /* FALLTHROUGH */ |
5011 | case M_BGE_I: | |
5012 | case M_BGEL_I: | |
5013 | if (mask == M_BGEL_I) | |
5014 | likely = 1; | |
5015 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
5016 | { | |
67c0d1eb | 5017 | macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", sreg); |
8fc2e39e | 5018 | break; |
252b5132 RH |
5019 | } |
5020 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
5021 | { | |
67c0d1eb | 5022 | macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", sreg); |
8fc2e39e | 5023 | break; |
252b5132 RH |
5024 | } |
5025 | maxnum = 0x7fffffff; | |
ca4e0257 | 5026 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
5027 | { |
5028 | maxnum <<= 16; | |
5029 | maxnum |= 0xffff; | |
5030 | maxnum <<= 16; | |
5031 | maxnum |= 0xffff; | |
5032 | } | |
5033 | maxnum = - maxnum - 1; | |
5034 | if (imm_expr.X_op == O_constant | |
5035 | && imm_expr.X_add_number <= maxnum | |
ca4e0257 | 5036 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
5037 | { |
5038 | do_true: | |
5039 | /* result is always true */ | |
5040 | as_warn (_("Branch %s is always true"), ip->insn_mo->name); | |
67c0d1eb | 5041 | macro_build (&offset_expr, "b", "p"); |
8fc2e39e | 5042 | break; |
252b5132 | 5043 | } |
8fc2e39e | 5044 | used_at = 1; |
67c0d1eb | 5045 | set_at (sreg, 0); |
c80c840e | 5046 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, ZERO); |
252b5132 RH |
5047 | break; |
5048 | ||
5049 | case M_BGEUL: | |
5050 | likely = 1; | |
5051 | case M_BGEU: | |
5052 | if (treg == 0) | |
5053 | goto do_true; | |
5054 | if (sreg == 0) | |
5055 | { | |
67c0d1eb | 5056 | macro_build (&offset_expr, likely ? "beql" : "beq", |
c80c840e | 5057 | "s,t,p", ZERO, treg); |
8fc2e39e | 5058 | break; |
252b5132 | 5059 | } |
8fc2e39e | 5060 | used_at = 1; |
67c0d1eb | 5061 | macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg); |
c80c840e | 5062 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, ZERO); |
252b5132 RH |
5063 | break; |
5064 | ||
5065 | case M_BGTUL_I: | |
5066 | likely = 1; | |
5067 | case M_BGTU_I: | |
5068 | if (sreg == 0 | |
ca4e0257 | 5069 | || (HAVE_32BIT_GPRS |
252b5132 | 5070 | && imm_expr.X_op == O_constant |
f01dc953 | 5071 | && imm_expr.X_add_number == -1)) |
252b5132 RH |
5072 | goto do_false; |
5073 | if (imm_expr.X_op != O_constant) | |
5074 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 5075 | ++imm_expr.X_add_number; |
252b5132 RH |
5076 | /* FALLTHROUGH */ |
5077 | case M_BGEU_I: | |
5078 | case M_BGEUL_I: | |
5079 | if (mask == M_BGEUL_I) | |
5080 | likely = 1; | |
5081 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
5082 | goto do_true; | |
5083 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
5084 | { | |
67c0d1eb | 5085 | macro_build (&offset_expr, likely ? "bnel" : "bne", |
c80c840e | 5086 | "s,t,p", sreg, ZERO); |
8fc2e39e | 5087 | break; |
252b5132 | 5088 | } |
8fc2e39e | 5089 | used_at = 1; |
67c0d1eb | 5090 | set_at (sreg, 1); |
c80c840e | 5091 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, ZERO); |
252b5132 RH |
5092 | break; |
5093 | ||
5094 | case M_BGTL: | |
5095 | likely = 1; | |
5096 | case M_BGT: | |
5097 | if (treg == 0) | |
5098 | { | |
67c0d1eb | 5099 | macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", sreg); |
8fc2e39e | 5100 | break; |
252b5132 RH |
5101 | } |
5102 | if (sreg == 0) | |
5103 | { | |
67c0d1eb | 5104 | macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", treg); |
8fc2e39e | 5105 | break; |
252b5132 | 5106 | } |
8fc2e39e | 5107 | used_at = 1; |
67c0d1eb | 5108 | macro_build (NULL, "slt", "d,v,t", AT, treg, sreg); |
c80c840e | 5109 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, ZERO); |
252b5132 RH |
5110 | break; |
5111 | ||
5112 | case M_BGTUL: | |
5113 | likely = 1; | |
5114 | case M_BGTU: | |
5115 | if (treg == 0) | |
5116 | { | |
67c0d1eb | 5117 | macro_build (&offset_expr, likely ? "bnel" : "bne", |
c80c840e | 5118 | "s,t,p", sreg, ZERO); |
8fc2e39e | 5119 | break; |
252b5132 RH |
5120 | } |
5121 | if (sreg == 0) | |
5122 | goto do_false; | |
8fc2e39e | 5123 | used_at = 1; |
67c0d1eb | 5124 | macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg); |
c80c840e | 5125 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, ZERO); |
252b5132 RH |
5126 | break; |
5127 | ||
5128 | case M_BLEL: | |
5129 | likely = 1; | |
5130 | case M_BLE: | |
5131 | if (treg == 0) | |
5132 | { | |
67c0d1eb | 5133 | macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", sreg); |
8fc2e39e | 5134 | break; |
252b5132 RH |
5135 | } |
5136 | if (sreg == 0) | |
5137 | { | |
67c0d1eb | 5138 | macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", treg); |
8fc2e39e | 5139 | break; |
252b5132 | 5140 | } |
8fc2e39e | 5141 | used_at = 1; |
67c0d1eb | 5142 | macro_build (NULL, "slt", "d,v,t", AT, treg, sreg); |
c80c840e | 5143 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, ZERO); |
252b5132 RH |
5144 | break; |
5145 | ||
5146 | case M_BLEL_I: | |
5147 | likely = 1; | |
5148 | case M_BLE_I: | |
5149 | maxnum = 0x7fffffff; | |
ca4e0257 | 5150 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
5151 | { |
5152 | maxnum <<= 16; | |
5153 | maxnum |= 0xffff; | |
5154 | maxnum <<= 16; | |
5155 | maxnum |= 0xffff; | |
5156 | } | |
5157 | if (imm_expr.X_op == O_constant | |
5158 | && imm_expr.X_add_number >= maxnum | |
ca4e0257 | 5159 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
5160 | goto do_true; |
5161 | if (imm_expr.X_op != O_constant) | |
5162 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 5163 | ++imm_expr.X_add_number; |
252b5132 RH |
5164 | /* FALLTHROUGH */ |
5165 | case M_BLT_I: | |
5166 | case M_BLTL_I: | |
5167 | if (mask == M_BLTL_I) | |
5168 | likely = 1; | |
5169 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
5170 | { | |
67c0d1eb | 5171 | macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", sreg); |
8fc2e39e | 5172 | break; |
252b5132 RH |
5173 | } |
5174 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
5175 | { | |
67c0d1eb | 5176 | macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", sreg); |
8fc2e39e | 5177 | break; |
252b5132 | 5178 | } |
8fc2e39e | 5179 | used_at = 1; |
67c0d1eb | 5180 | set_at (sreg, 0); |
c80c840e | 5181 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, ZERO); |
252b5132 RH |
5182 | break; |
5183 | ||
5184 | case M_BLEUL: | |
5185 | likely = 1; | |
5186 | case M_BLEU: | |
5187 | if (treg == 0) | |
5188 | { | |
67c0d1eb | 5189 | macro_build (&offset_expr, likely ? "beql" : "beq", |
c80c840e | 5190 | "s,t,p", sreg, ZERO); |
8fc2e39e | 5191 | break; |
252b5132 RH |
5192 | } |
5193 | if (sreg == 0) | |
5194 | goto do_true; | |
8fc2e39e | 5195 | used_at = 1; |
67c0d1eb | 5196 | macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg); |
c80c840e | 5197 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, ZERO); |
252b5132 RH |
5198 | break; |
5199 | ||
5200 | case M_BLEUL_I: | |
5201 | likely = 1; | |
5202 | case M_BLEU_I: | |
5203 | if (sreg == 0 | |
ca4e0257 | 5204 | || (HAVE_32BIT_GPRS |
252b5132 | 5205 | && imm_expr.X_op == O_constant |
f01dc953 | 5206 | && imm_expr.X_add_number == -1)) |
252b5132 RH |
5207 | goto do_true; |
5208 | if (imm_expr.X_op != O_constant) | |
5209 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 5210 | ++imm_expr.X_add_number; |
252b5132 RH |
5211 | /* FALLTHROUGH */ |
5212 | case M_BLTU_I: | |
5213 | case M_BLTUL_I: | |
5214 | if (mask == M_BLTUL_I) | |
5215 | likely = 1; | |
5216 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
5217 | goto do_false; | |
5218 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
5219 | { | |
67c0d1eb | 5220 | macro_build (&offset_expr, likely ? "beql" : "beq", |
c80c840e | 5221 | "s,t,p", sreg, ZERO); |
8fc2e39e | 5222 | break; |
252b5132 | 5223 | } |
8fc2e39e | 5224 | used_at = 1; |
67c0d1eb | 5225 | set_at (sreg, 1); |
c80c840e | 5226 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, ZERO); |
252b5132 RH |
5227 | break; |
5228 | ||
5229 | case M_BLTL: | |
5230 | likely = 1; | |
5231 | case M_BLT: | |
5232 | if (treg == 0) | |
5233 | { | |
67c0d1eb | 5234 | macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", sreg); |
8fc2e39e | 5235 | break; |
252b5132 RH |
5236 | } |
5237 | if (sreg == 0) | |
5238 | { | |
67c0d1eb | 5239 | macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", treg); |
8fc2e39e | 5240 | break; |
252b5132 | 5241 | } |
8fc2e39e | 5242 | used_at = 1; |
67c0d1eb | 5243 | macro_build (NULL, "slt", "d,v,t", AT, sreg, treg); |
c80c840e | 5244 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, ZERO); |
252b5132 RH |
5245 | break; |
5246 | ||
5247 | case M_BLTUL: | |
5248 | likely = 1; | |
5249 | case M_BLTU: | |
5250 | if (treg == 0) | |
5251 | goto do_false; | |
5252 | if (sreg == 0) | |
5253 | { | |
67c0d1eb | 5254 | macro_build (&offset_expr, likely ? "bnel" : "bne", |
c80c840e | 5255 | "s,t,p", ZERO, treg); |
8fc2e39e | 5256 | break; |
252b5132 | 5257 | } |
8fc2e39e | 5258 | used_at = 1; |
67c0d1eb | 5259 | macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg); |
c80c840e | 5260 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, ZERO); |
252b5132 RH |
5261 | break; |
5262 | ||
5f74bc13 CD |
5263 | case M_DEXT: |
5264 | { | |
d5818fca MR |
5265 | /* Use unsigned arithmetic. */ |
5266 | addressT pos; | |
5267 | addressT size; | |
5f74bc13 | 5268 | |
90ecf173 | 5269 | if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant) |
5f74bc13 CD |
5270 | { |
5271 | as_bad (_("Unsupported large constant")); | |
5272 | pos = size = 1; | |
5273 | } | |
5274 | else | |
5275 | { | |
d5818fca MR |
5276 | pos = imm_expr.X_add_number; |
5277 | size = imm2_expr.X_add_number; | |
5f74bc13 CD |
5278 | } |
5279 | ||
5280 | if (pos > 63) | |
5281 | { | |
d5818fca | 5282 | as_bad (_("Improper position (%lu)"), (unsigned long) pos); |
5f74bc13 CD |
5283 | pos = 1; |
5284 | } | |
90ecf173 | 5285 | if (size == 0 || size > 64 || (pos + size - 1) > 63) |
5f74bc13 CD |
5286 | { |
5287 | as_bad (_("Improper extract size (%lu, position %lu)"), | |
d5818fca | 5288 | (unsigned long) size, (unsigned long) pos); |
5f74bc13 CD |
5289 | size = 1; |
5290 | } | |
5291 | ||
5292 | if (size <= 32 && pos < 32) | |
5293 | { | |
5294 | s = "dext"; | |
5295 | fmt = "t,r,+A,+C"; | |
5296 | } | |
5297 | else if (size <= 32) | |
5298 | { | |
5299 | s = "dextu"; | |
5300 | fmt = "t,r,+E,+H"; | |
5301 | } | |
5302 | else | |
5303 | { | |
5304 | s = "dextm"; | |
5305 | fmt = "t,r,+A,+G"; | |
5306 | } | |
d5818fca MR |
5307 | macro_build ((expressionS *) NULL, s, fmt, treg, sreg, (int) pos, |
5308 | (int) (size - 1)); | |
5f74bc13 | 5309 | } |
8fc2e39e | 5310 | break; |
5f74bc13 CD |
5311 | |
5312 | case M_DINS: | |
5313 | { | |
d5818fca MR |
5314 | /* Use unsigned arithmetic. */ |
5315 | addressT pos; | |
5316 | addressT size; | |
5f74bc13 | 5317 | |
90ecf173 | 5318 | if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant) |
5f74bc13 CD |
5319 | { |
5320 | as_bad (_("Unsupported large constant")); | |
5321 | pos = size = 1; | |
5322 | } | |
5323 | else | |
5324 | { | |
d5818fca MR |
5325 | pos = imm_expr.X_add_number; |
5326 | size = imm2_expr.X_add_number; | |
5f74bc13 CD |
5327 | } |
5328 | ||
5329 | if (pos > 63) | |
5330 | { | |
d5818fca | 5331 | as_bad (_("Improper position (%lu)"), (unsigned long) pos); |
5f74bc13 CD |
5332 | pos = 1; |
5333 | } | |
90ecf173 | 5334 | if (size == 0 || size > 64 || (pos + size - 1) > 63) |
5f74bc13 CD |
5335 | { |
5336 | as_bad (_("Improper insert size (%lu, position %lu)"), | |
d5818fca | 5337 | (unsigned long) size, (unsigned long) pos); |
5f74bc13 CD |
5338 | size = 1; |
5339 | } | |
5340 | ||
5341 | if (pos < 32 && (pos + size - 1) < 32) | |
5342 | { | |
5343 | s = "dins"; | |
5344 | fmt = "t,r,+A,+B"; | |
5345 | } | |
5346 | else if (pos >= 32) | |
5347 | { | |
5348 | s = "dinsu"; | |
5349 | fmt = "t,r,+E,+F"; | |
5350 | } | |
5351 | else | |
5352 | { | |
5353 | s = "dinsm"; | |
5354 | fmt = "t,r,+A,+F"; | |
5355 | } | |
750bdd57 AS |
5356 | macro_build ((expressionS *) NULL, s, fmt, treg, sreg, (int) pos, |
5357 | (int) (pos + size - 1)); | |
5f74bc13 | 5358 | } |
8fc2e39e | 5359 | break; |
5f74bc13 | 5360 | |
252b5132 RH |
5361 | case M_DDIV_3: |
5362 | dbl = 1; | |
5363 | case M_DIV_3: | |
5364 | s = "mflo"; | |
5365 | goto do_div3; | |
5366 | case M_DREM_3: | |
5367 | dbl = 1; | |
5368 | case M_REM_3: | |
5369 | s = "mfhi"; | |
5370 | do_div3: | |
5371 | if (treg == 0) | |
5372 | { | |
5373 | as_warn (_("Divide by zero.")); | |
5374 | if (mips_trap) | |
c80c840e | 5375 | macro_build (NULL, "teq", "s,t,q", ZERO, ZERO, 7); |
252b5132 | 5376 | else |
67c0d1eb | 5377 | macro_build (NULL, "break", "c", 7); |
8fc2e39e | 5378 | break; |
252b5132 RH |
5379 | } |
5380 | ||
7d10b47d | 5381 | start_noreorder (); |
252b5132 RH |
5382 | if (mips_trap) |
5383 | { | |
c80c840e | 5384 | macro_build (NULL, "teq", "s,t,q", treg, ZERO, 7); |
67c0d1eb | 5385 | macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg); |
252b5132 RH |
5386 | } |
5387 | else | |
5388 | { | |
5389 | expr1.X_add_number = 8; | |
c80c840e | 5390 | macro_build (&expr1, "bne", "s,t,p", treg, ZERO); |
67c0d1eb RS |
5391 | macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg); |
5392 | macro_build (NULL, "break", "c", 7); | |
252b5132 RH |
5393 | } |
5394 | expr1.X_add_number = -1; | |
8fc2e39e | 5395 | used_at = 1; |
f6a22291 | 5396 | load_register (AT, &expr1, dbl); |
252b5132 | 5397 | expr1.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16); |
67c0d1eb | 5398 | macro_build (&expr1, "bne", "s,t,p", treg, AT); |
252b5132 RH |
5399 | if (dbl) |
5400 | { | |
5401 | expr1.X_add_number = 1; | |
f6a22291 | 5402 | load_register (AT, &expr1, dbl); |
67c0d1eb | 5403 | macro_build (NULL, "dsll32", "d,w,<", AT, AT, 31); |
252b5132 RH |
5404 | } |
5405 | else | |
5406 | { | |
5407 | expr1.X_add_number = 0x80000000; | |
67c0d1eb | 5408 | macro_build (&expr1, "lui", "t,u", AT, BFD_RELOC_HI16); |
252b5132 RH |
5409 | } |
5410 | if (mips_trap) | |
5411 | { | |
67c0d1eb | 5412 | macro_build (NULL, "teq", "s,t,q", sreg, AT, 6); |
252b5132 RH |
5413 | /* We want to close the noreorder block as soon as possible, so |
5414 | that later insns are available for delay slot filling. */ | |
7d10b47d | 5415 | end_noreorder (); |
252b5132 RH |
5416 | } |
5417 | else | |
5418 | { | |
5419 | expr1.X_add_number = 8; | |
67c0d1eb | 5420 | macro_build (&expr1, "bne", "s,t,p", sreg, AT); |
a605d2b3 | 5421 | macro_build (NULL, "nop", ""); |
252b5132 RH |
5422 | |
5423 | /* We want to close the noreorder block as soon as possible, so | |
5424 | that later insns are available for delay slot filling. */ | |
7d10b47d | 5425 | end_noreorder (); |
252b5132 | 5426 | |
67c0d1eb | 5427 | macro_build (NULL, "break", "c", 6); |
252b5132 | 5428 | } |
67c0d1eb | 5429 | macro_build (NULL, s, "d", dreg); |
252b5132 RH |
5430 | break; |
5431 | ||
5432 | case M_DIV_3I: | |
5433 | s = "div"; | |
5434 | s2 = "mflo"; | |
5435 | goto do_divi; | |
5436 | case M_DIVU_3I: | |
5437 | s = "divu"; | |
5438 | s2 = "mflo"; | |
5439 | goto do_divi; | |
5440 | case M_REM_3I: | |
5441 | s = "div"; | |
5442 | s2 = "mfhi"; | |
5443 | goto do_divi; | |
5444 | case M_REMU_3I: | |
5445 | s = "divu"; | |
5446 | s2 = "mfhi"; | |
5447 | goto do_divi; | |
5448 | case M_DDIV_3I: | |
5449 | dbl = 1; | |
5450 | s = "ddiv"; | |
5451 | s2 = "mflo"; | |
5452 | goto do_divi; | |
5453 | case M_DDIVU_3I: | |
5454 | dbl = 1; | |
5455 | s = "ddivu"; | |
5456 | s2 = "mflo"; | |
5457 | goto do_divi; | |
5458 | case M_DREM_3I: | |
5459 | dbl = 1; | |
5460 | s = "ddiv"; | |
5461 | s2 = "mfhi"; | |
5462 | goto do_divi; | |
5463 | case M_DREMU_3I: | |
5464 | dbl = 1; | |
5465 | s = "ddivu"; | |
5466 | s2 = "mfhi"; | |
5467 | do_divi: | |
5468 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
5469 | { | |
5470 | as_warn (_("Divide by zero.")); | |
5471 | if (mips_trap) | |
c80c840e | 5472 | macro_build (NULL, "teq", "s,t,q", ZERO, ZERO, 7); |
252b5132 | 5473 | else |
67c0d1eb | 5474 | macro_build (NULL, "break", "c", 7); |
8fc2e39e | 5475 | break; |
252b5132 RH |
5476 | } |
5477 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
5478 | { | |
5479 | if (strcmp (s2, "mflo") == 0) | |
67c0d1eb | 5480 | move_register (dreg, sreg); |
252b5132 | 5481 | else |
c80c840e | 5482 | move_register (dreg, ZERO); |
8fc2e39e | 5483 | break; |
252b5132 RH |
5484 | } |
5485 | if (imm_expr.X_op == O_constant | |
5486 | && imm_expr.X_add_number == -1 | |
5487 | && s[strlen (s) - 1] != 'u') | |
5488 | { | |
5489 | if (strcmp (s2, "mflo") == 0) | |
5490 | { | |
67c0d1eb | 5491 | macro_build (NULL, dbl ? "dneg" : "neg", "d,w", dreg, sreg); |
252b5132 RH |
5492 | } |
5493 | else | |
c80c840e | 5494 | move_register (dreg, ZERO); |
8fc2e39e | 5495 | break; |
252b5132 RH |
5496 | } |
5497 | ||
8fc2e39e | 5498 | used_at = 1; |
67c0d1eb RS |
5499 | load_register (AT, &imm_expr, dbl); |
5500 | macro_build (NULL, s, "z,s,t", sreg, AT); | |
5501 | macro_build (NULL, s2, "d", dreg); | |
252b5132 RH |
5502 | break; |
5503 | ||
5504 | case M_DIVU_3: | |
5505 | s = "divu"; | |
5506 | s2 = "mflo"; | |
5507 | goto do_divu3; | |
5508 | case M_REMU_3: | |
5509 | s = "divu"; | |
5510 | s2 = "mfhi"; | |
5511 | goto do_divu3; | |
5512 | case M_DDIVU_3: | |
5513 | s = "ddivu"; | |
5514 | s2 = "mflo"; | |
5515 | goto do_divu3; | |
5516 | case M_DREMU_3: | |
5517 | s = "ddivu"; | |
5518 | s2 = "mfhi"; | |
5519 | do_divu3: | |
7d10b47d | 5520 | start_noreorder (); |
252b5132 RH |
5521 | if (mips_trap) |
5522 | { | |
c80c840e | 5523 | macro_build (NULL, "teq", "s,t,q", treg, ZERO, 7); |
67c0d1eb | 5524 | macro_build (NULL, s, "z,s,t", sreg, treg); |
252b5132 RH |
5525 | /* We want to close the noreorder block as soon as possible, so |
5526 | that later insns are available for delay slot filling. */ | |
7d10b47d | 5527 | end_noreorder (); |
252b5132 RH |
5528 | } |
5529 | else | |
5530 | { | |
5531 | expr1.X_add_number = 8; | |
c80c840e | 5532 | macro_build (&expr1, "bne", "s,t,p", treg, ZERO); |
67c0d1eb | 5533 | macro_build (NULL, s, "z,s,t", sreg, treg); |
252b5132 RH |
5534 | |
5535 | /* We want to close the noreorder block as soon as possible, so | |
5536 | that later insns are available for delay slot filling. */ | |
7d10b47d | 5537 | end_noreorder (); |
67c0d1eb | 5538 | macro_build (NULL, "break", "c", 7); |
252b5132 | 5539 | } |
67c0d1eb | 5540 | macro_build (NULL, s2, "d", dreg); |
8fc2e39e | 5541 | break; |
252b5132 | 5542 | |
1abe91b1 MR |
5543 | case M_DLCA_AB: |
5544 | dbl = 1; | |
5545 | case M_LCA_AB: | |
5546 | call = 1; | |
5547 | goto do_la; | |
252b5132 RH |
5548 | case M_DLA_AB: |
5549 | dbl = 1; | |
5550 | case M_LA_AB: | |
1abe91b1 | 5551 | do_la: |
252b5132 RH |
5552 | /* Load the address of a symbol into a register. If breg is not |
5553 | zero, we then add a base register to it. */ | |
5554 | ||
3bec30a8 TS |
5555 | if (dbl && HAVE_32BIT_GPRS) |
5556 | as_warn (_("dla used to load 32-bit register")); | |
5557 | ||
90ecf173 | 5558 | if (!dbl && HAVE_64BIT_OBJECTS) |
3bec30a8 TS |
5559 | as_warn (_("la used to load 64-bit address")); |
5560 | ||
0c11417f MR |
5561 | if (offset_expr.X_op == O_constant |
5562 | && offset_expr.X_add_number >= -0x8000 | |
5563 | && offset_expr.X_add_number < 0x8000) | |
5564 | { | |
aed1a261 | 5565 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, |
17a2f251 | 5566 | "t,r,j", treg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 5567 | break; |
0c11417f MR |
5568 | } |
5569 | ||
741fe287 | 5570 | if (mips_opts.at && (treg == breg)) |
afdbd6d0 CD |
5571 | { |
5572 | tempreg = AT; | |
5573 | used_at = 1; | |
5574 | } | |
5575 | else | |
5576 | { | |
5577 | tempreg = treg; | |
afdbd6d0 CD |
5578 | } |
5579 | ||
252b5132 RH |
5580 | if (offset_expr.X_op != O_symbol |
5581 | && offset_expr.X_op != O_constant) | |
5582 | { | |
f71d0d44 | 5583 | as_bad (_("Expression too complex")); |
252b5132 RH |
5584 | offset_expr.X_op = O_constant; |
5585 | } | |
5586 | ||
252b5132 | 5587 | if (offset_expr.X_op == O_constant) |
aed1a261 | 5588 | load_register (tempreg, &offset_expr, HAVE_64BIT_ADDRESSES); |
252b5132 RH |
5589 | else if (mips_pic == NO_PIC) |
5590 | { | |
d6bc6245 | 5591 | /* If this is a reference to a GP relative symbol, we want |
cdf6fd85 | 5592 | addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
5593 | Otherwise we want |
5594 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
5595 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
5596 | If we have a constant, we need two instructions anyhow, | |
d6bc6245 | 5597 | so we may as well always use the latter form. |
76b3015f | 5598 | |
6caf9ef4 TS |
5599 | With 64bit address space and a usable $at we want |
5600 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5601 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
5602 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5603 | daddiu $at,<sym> (BFD_RELOC_LO16) | |
5604 | dsll32 $tempreg,0 | |
5605 | daddu $tempreg,$tempreg,$at | |
5606 | ||
5607 | If $at is already in use, we use a path which is suboptimal | |
5608 | on superscalar processors. | |
5609 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5610 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5611 | dsll $tempreg,16 | |
5612 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
5613 | dsll $tempreg,16 | |
5614 | daddiu $tempreg,<sym> (BFD_RELOC_LO16) | |
5615 | ||
5616 | For GP relative symbols in 64bit address space we can use | |
5617 | the same sequence as in 32bit address space. */ | |
aed1a261 | 5618 | if (HAVE_64BIT_SYMBOLS) |
252b5132 | 5619 | { |
6caf9ef4 TS |
5620 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
5621 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) | |
5622 | { | |
5623 | relax_start (offset_expr.X_add_symbol); | |
5624 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
5625 | tempreg, mips_gp_register, BFD_RELOC_GPREL16); | |
5626 | relax_switch (); | |
5627 | } | |
d6bc6245 | 5628 | |
741fe287 | 5629 | if (used_at == 0 && mips_opts.at) |
98d3f06f | 5630 | { |
67c0d1eb | 5631 | macro_build (&offset_expr, "lui", "t,u", |
17a2f251 | 5632 | tempreg, BFD_RELOC_MIPS_HIGHEST); |
67c0d1eb | 5633 | macro_build (&offset_expr, "lui", "t,u", |
17a2f251 | 5634 | AT, BFD_RELOC_HI16_S); |
67c0d1eb | 5635 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 5636 | tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); |
67c0d1eb | 5637 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 5638 | AT, AT, BFD_RELOC_LO16); |
67c0d1eb RS |
5639 | macro_build (NULL, "dsll32", "d,w,<", tempreg, tempreg, 0); |
5640 | macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT); | |
98d3f06f KH |
5641 | used_at = 1; |
5642 | } | |
5643 | else | |
5644 | { | |
67c0d1eb | 5645 | macro_build (&offset_expr, "lui", "t,u", |
17a2f251 | 5646 | tempreg, BFD_RELOC_MIPS_HIGHEST); |
67c0d1eb | 5647 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 5648 | tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); |
67c0d1eb RS |
5649 | macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16); |
5650 | macro_build (&offset_expr, "daddiu", "t,r,j", | |
17a2f251 | 5651 | tempreg, tempreg, BFD_RELOC_HI16_S); |
67c0d1eb RS |
5652 | macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16); |
5653 | macro_build (&offset_expr, "daddiu", "t,r,j", | |
17a2f251 | 5654 | tempreg, tempreg, BFD_RELOC_LO16); |
98d3f06f | 5655 | } |
6caf9ef4 TS |
5656 | |
5657 | if (mips_relax.sequence) | |
5658 | relax_end (); | |
98d3f06f KH |
5659 | } |
5660 | else | |
5661 | { | |
5662 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET | |
6caf9ef4 | 5663 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
98d3f06f | 5664 | { |
4d7206a2 | 5665 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
5666 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
5667 | tempreg, mips_gp_register, BFD_RELOC_GPREL16); | |
4d7206a2 | 5668 | relax_switch (); |
98d3f06f | 5669 | } |
6943caf0 | 5670 | if (!IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) |
f71d0d44 | 5671 | as_bad (_("Offset too large")); |
67c0d1eb RS |
5672 | macro_build_lui (&offset_expr, tempreg); |
5673 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
5674 | tempreg, tempreg, BFD_RELOC_LO16); | |
4d7206a2 RS |
5675 | if (mips_relax.sequence) |
5676 | relax_end (); | |
98d3f06f | 5677 | } |
252b5132 | 5678 | } |
0a44bf69 | 5679 | else if (!mips_big_got && !HAVE_NEWABI) |
252b5132 | 5680 | { |
9117d219 NC |
5681 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
5682 | ||
252b5132 RH |
5683 | /* If this is a reference to an external symbol, and there |
5684 | is no constant, we want | |
5685 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
1abe91b1 | 5686 | or for lca or if tempreg is PIC_CALL_REG |
9117d219 | 5687 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
252b5132 RH |
5688 | For a local symbol, we want |
5689 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5690 | nop | |
5691 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
5692 | ||
5693 | If we have a small constant, and this is a reference to | |
5694 | an external symbol, we want | |
5695 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5696 | nop | |
5697 | addiu $tempreg,$tempreg,<constant> | |
5698 | For a local symbol, we want the same instruction | |
5699 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
5700 | addiu instruction. | |
5701 | ||
5702 | If we have a large constant, and this is a reference to | |
5703 | an external symbol, we want | |
5704 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5705 | lui $at,<hiconstant> | |
5706 | addiu $at,$at,<loconstant> | |
5707 | addu $tempreg,$tempreg,$at | |
5708 | For a local symbol, we want the same instruction | |
5709 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
ed6fb7bd | 5710 | addiu instruction. |
ed6fb7bd SC |
5711 | */ |
5712 | ||
4d7206a2 | 5713 | if (offset_expr.X_add_number == 0) |
252b5132 | 5714 | { |
0a44bf69 RS |
5715 | if (mips_pic == SVR4_PIC |
5716 | && breg == 0 | |
5717 | && (call || tempreg == PIC_CALL_REG)) | |
4d7206a2 RS |
5718 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16; |
5719 | ||
5720 | relax_start (offset_expr.X_add_symbol); | |
67c0d1eb RS |
5721 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5722 | lw_reloc_type, mips_gp_register); | |
4d7206a2 | 5723 | if (breg != 0) |
252b5132 RH |
5724 | { |
5725 | /* We're going to put in an addu instruction using | |
5726 | tempreg, so we may as well insert the nop right | |
5727 | now. */ | |
269137b2 | 5728 | load_delay_nop (); |
252b5132 | 5729 | } |
4d7206a2 | 5730 | relax_switch (); |
67c0d1eb RS |
5731 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5732 | tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 5733 | load_delay_nop (); |
67c0d1eb RS |
5734 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
5735 | tempreg, tempreg, BFD_RELOC_LO16); | |
4d7206a2 | 5736 | relax_end (); |
252b5132 RH |
5737 | /* FIXME: If breg == 0, and the next instruction uses |
5738 | $tempreg, then if this variant case is used an extra | |
5739 | nop will be generated. */ | |
5740 | } | |
4d7206a2 RS |
5741 | else if (offset_expr.X_add_number >= -0x8000 |
5742 | && offset_expr.X_add_number < 0x8000) | |
252b5132 | 5743 | { |
67c0d1eb | 5744 | load_got_offset (tempreg, &offset_expr); |
269137b2 | 5745 | load_delay_nop (); |
67c0d1eb | 5746 | add_got_offset (tempreg, &offset_expr); |
252b5132 RH |
5747 | } |
5748 | else | |
5749 | { | |
4d7206a2 RS |
5750 | expr1.X_add_number = offset_expr.X_add_number; |
5751 | offset_expr.X_add_number = | |
5752 | ((offset_expr.X_add_number + 0x8000) & 0xffff) - 0x8000; | |
67c0d1eb | 5753 | load_got_offset (tempreg, &offset_expr); |
f6a22291 | 5754 | offset_expr.X_add_number = expr1.X_add_number; |
252b5132 RH |
5755 | /* If we are going to add in a base register, and the |
5756 | target register and the base register are the same, | |
5757 | then we are using AT as a temporary register. Since | |
5758 | we want to load the constant into AT, we add our | |
5759 | current AT (from the global offset table) and the | |
5760 | register into the register now, and pretend we were | |
5761 | not using a base register. */ | |
67c0d1eb | 5762 | if (breg == treg) |
252b5132 | 5763 | { |
269137b2 | 5764 | load_delay_nop (); |
67c0d1eb | 5765 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5766 | treg, AT, breg); |
252b5132 RH |
5767 | breg = 0; |
5768 | tempreg = treg; | |
252b5132 | 5769 | } |
f6a22291 | 5770 | add_got_offset_hilo (tempreg, &offset_expr, AT); |
252b5132 RH |
5771 | used_at = 1; |
5772 | } | |
5773 | } | |
0a44bf69 | 5774 | else if (!mips_big_got && HAVE_NEWABI) |
f5040a92 | 5775 | { |
67c0d1eb | 5776 | int add_breg_early = 0; |
f5040a92 AO |
5777 | |
5778 | /* If this is a reference to an external, and there is no | |
5779 | constant, or local symbol (*), with or without a | |
5780 | constant, we want | |
5781 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
1abe91b1 | 5782 | or for lca or if tempreg is PIC_CALL_REG |
f5040a92 AO |
5783 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
5784 | ||
5785 | If we have a small constant, and this is a reference to | |
5786 | an external symbol, we want | |
5787 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
5788 | addiu $tempreg,$tempreg,<constant> | |
5789 | ||
5790 | If we have a large constant, and this is a reference to | |
5791 | an external symbol, we want | |
5792 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
5793 | lui $at,<hiconstant> | |
5794 | addiu $at,$at,<loconstant> | |
5795 | addu $tempreg,$tempreg,$at | |
5796 | ||
5797 | (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for | |
5798 | local symbols, even though it introduces an additional | |
5799 | instruction. */ | |
5800 | ||
f5040a92 AO |
5801 | if (offset_expr.X_add_number) |
5802 | { | |
4d7206a2 | 5803 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
5804 | offset_expr.X_add_number = 0; |
5805 | ||
4d7206a2 | 5806 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
5807 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5808 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
5809 | |
5810 | if (expr1.X_add_number >= -0x8000 | |
5811 | && expr1.X_add_number < 0x8000) | |
5812 | { | |
67c0d1eb RS |
5813 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
5814 | tempreg, tempreg, BFD_RELOC_LO16); | |
f5040a92 | 5815 | } |
ecd13cd3 | 5816 | else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000)) |
f5040a92 | 5817 | { |
f5040a92 AO |
5818 | /* If we are going to add in a base register, and the |
5819 | target register and the base register are the same, | |
5820 | then we are using AT as a temporary register. Since | |
5821 | we want to load the constant into AT, we add our | |
5822 | current AT (from the global offset table) and the | |
5823 | register into the register now, and pretend we were | |
5824 | not using a base register. */ | |
5825 | if (breg != treg) | |
5826 | dreg = tempreg; | |
5827 | else | |
5828 | { | |
9c2799c2 | 5829 | gas_assert (tempreg == AT); |
67c0d1eb RS |
5830 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
5831 | treg, AT, breg); | |
f5040a92 | 5832 | dreg = treg; |
67c0d1eb | 5833 | add_breg_early = 1; |
f5040a92 AO |
5834 | } |
5835 | ||
f6a22291 | 5836 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 5837 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5838 | dreg, dreg, AT); |
f5040a92 | 5839 | |
f5040a92 AO |
5840 | used_at = 1; |
5841 | } | |
5842 | else | |
5843 | as_bad (_("PIC code offset overflow (max 32 signed bits)")); | |
5844 | ||
4d7206a2 | 5845 | relax_switch (); |
f5040a92 AO |
5846 | offset_expr.X_add_number = expr1.X_add_number; |
5847 | ||
67c0d1eb RS |
5848 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5849 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
5850 | if (add_breg_early) | |
f5040a92 | 5851 | { |
67c0d1eb | 5852 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
f899b4b8 | 5853 | treg, tempreg, breg); |
f5040a92 AO |
5854 | breg = 0; |
5855 | tempreg = treg; | |
5856 | } | |
4d7206a2 | 5857 | relax_end (); |
f5040a92 | 5858 | } |
4d7206a2 | 5859 | else if (breg == 0 && (call || tempreg == PIC_CALL_REG)) |
f5040a92 | 5860 | { |
4d7206a2 | 5861 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
5862 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5863 | BFD_RELOC_MIPS_CALL16, mips_gp_register); | |
4d7206a2 | 5864 | relax_switch (); |
67c0d1eb RS |
5865 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5866 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
4d7206a2 | 5867 | relax_end (); |
f5040a92 | 5868 | } |
4d7206a2 | 5869 | else |
f5040a92 | 5870 | { |
67c0d1eb RS |
5871 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5872 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
5873 | } |
5874 | } | |
0a44bf69 | 5875 | else if (mips_big_got && !HAVE_NEWABI) |
252b5132 | 5876 | { |
67c0d1eb | 5877 | int gpdelay; |
9117d219 NC |
5878 | int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; |
5879 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; | |
ed6fb7bd | 5880 | int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
252b5132 RH |
5881 | |
5882 | /* This is the large GOT case. If this is a reference to an | |
5883 | external symbol, and there is no constant, we want | |
5884 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5885 | addu $tempreg,$tempreg,$gp | |
5886 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
1abe91b1 | 5887 | or for lca or if tempreg is PIC_CALL_REG |
9117d219 NC |
5888 | lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) |
5889 | addu $tempreg,$tempreg,$gp | |
5890 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) | |
252b5132 RH |
5891 | For a local symbol, we want |
5892 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5893 | nop | |
5894 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
5895 | ||
5896 | If we have a small constant, and this is a reference to | |
5897 | an external symbol, we want | |
5898 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5899 | addu $tempreg,$tempreg,$gp | |
5900 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5901 | nop | |
5902 | addiu $tempreg,$tempreg,<constant> | |
5903 | For a local symbol, we want | |
5904 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5905 | nop | |
5906 | addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16) | |
5907 | ||
5908 | If we have a large constant, and this is a reference to | |
5909 | an external symbol, we want | |
5910 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5911 | addu $tempreg,$tempreg,$gp | |
5912 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5913 | lui $at,<hiconstant> | |
5914 | addiu $at,$at,<loconstant> | |
5915 | addu $tempreg,$tempreg,$at | |
5916 | For a local symbol, we want | |
5917 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5918 | lui $at,<hiconstant> | |
5919 | addiu $at,$at,<loconstant> (BFD_RELOC_LO16) | |
5920 | addu $tempreg,$tempreg,$at | |
f5040a92 | 5921 | */ |
438c16b8 | 5922 | |
252b5132 RH |
5923 | expr1.X_add_number = offset_expr.X_add_number; |
5924 | offset_expr.X_add_number = 0; | |
4d7206a2 | 5925 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 5926 | gpdelay = reg_needs_delay (mips_gp_register); |
1abe91b1 MR |
5927 | if (expr1.X_add_number == 0 && breg == 0 |
5928 | && (call || tempreg == PIC_CALL_REG)) | |
9117d219 NC |
5929 | { |
5930 | lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; | |
5931 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; | |
5932 | } | |
67c0d1eb RS |
5933 | macro_build (&offset_expr, "lui", "t,u", tempreg, lui_reloc_type); |
5934 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 5935 | tempreg, tempreg, mips_gp_register); |
67c0d1eb | 5936 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
17a2f251 | 5937 | tempreg, lw_reloc_type, tempreg); |
252b5132 RH |
5938 | if (expr1.X_add_number == 0) |
5939 | { | |
67c0d1eb | 5940 | if (breg != 0) |
252b5132 RH |
5941 | { |
5942 | /* We're going to put in an addu instruction using | |
5943 | tempreg, so we may as well insert the nop right | |
5944 | now. */ | |
269137b2 | 5945 | load_delay_nop (); |
252b5132 | 5946 | } |
252b5132 RH |
5947 | } |
5948 | else if (expr1.X_add_number >= -0x8000 | |
5949 | && expr1.X_add_number < 0x8000) | |
5950 | { | |
269137b2 | 5951 | load_delay_nop (); |
67c0d1eb | 5952 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 5953 | tempreg, tempreg, BFD_RELOC_LO16); |
252b5132 RH |
5954 | } |
5955 | else | |
5956 | { | |
252b5132 RH |
5957 | /* If we are going to add in a base register, and the |
5958 | target register and the base register are the same, | |
5959 | then we are using AT as a temporary register. Since | |
5960 | we want to load the constant into AT, we add our | |
5961 | current AT (from the global offset table) and the | |
5962 | register into the register now, and pretend we were | |
5963 | not using a base register. */ | |
5964 | if (breg != treg) | |
67c0d1eb | 5965 | dreg = tempreg; |
252b5132 RH |
5966 | else |
5967 | { | |
9c2799c2 | 5968 | gas_assert (tempreg == AT); |
269137b2 | 5969 | load_delay_nop (); |
67c0d1eb | 5970 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5971 | treg, AT, breg); |
252b5132 | 5972 | dreg = treg; |
252b5132 RH |
5973 | } |
5974 | ||
f6a22291 | 5975 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 5976 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT); |
252b5132 | 5977 | |
252b5132 RH |
5978 | used_at = 1; |
5979 | } | |
4d7206a2 RS |
5980 | offset_expr.X_add_number = |
5981 | ((expr1.X_add_number + 0x8000) & 0xffff) - 0x8000; | |
5982 | relax_switch (); | |
252b5132 | 5983 | |
67c0d1eb | 5984 | if (gpdelay) |
252b5132 RH |
5985 | { |
5986 | /* This is needed because this instruction uses $gp, but | |
f5040a92 | 5987 | the first instruction on the main stream does not. */ |
67c0d1eb | 5988 | macro_build (NULL, "nop", ""); |
252b5132 | 5989 | } |
ed6fb7bd | 5990 | |
67c0d1eb RS |
5991 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5992 | local_reloc_type, mips_gp_register); | |
f5040a92 | 5993 | if (expr1.X_add_number >= -0x8000 |
252b5132 RH |
5994 | && expr1.X_add_number < 0x8000) |
5995 | { | |
269137b2 | 5996 | load_delay_nop (); |
67c0d1eb RS |
5997 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
5998 | tempreg, tempreg, BFD_RELOC_LO16); | |
252b5132 | 5999 | /* FIXME: If add_number is 0, and there was no base |
f5040a92 AO |
6000 | register, the external symbol case ended with a load, |
6001 | so if the symbol turns out to not be external, and | |
6002 | the next instruction uses tempreg, an unnecessary nop | |
6003 | will be inserted. */ | |
252b5132 RH |
6004 | } |
6005 | else | |
6006 | { | |
6007 | if (breg == treg) | |
6008 | { | |
6009 | /* We must add in the base register now, as in the | |
f5040a92 | 6010 | external symbol case. */ |
9c2799c2 | 6011 | gas_assert (tempreg == AT); |
269137b2 | 6012 | load_delay_nop (); |
67c0d1eb | 6013 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6014 | treg, AT, breg); |
252b5132 RH |
6015 | tempreg = treg; |
6016 | /* We set breg to 0 because we have arranged to add | |
f5040a92 | 6017 | it in in both cases. */ |
252b5132 RH |
6018 | breg = 0; |
6019 | } | |
6020 | ||
67c0d1eb RS |
6021 | macro_build_lui (&expr1, AT); |
6022 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
17a2f251 | 6023 | AT, AT, BFD_RELOC_LO16); |
67c0d1eb | 6024 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6025 | tempreg, tempreg, AT); |
8fc2e39e | 6026 | used_at = 1; |
252b5132 | 6027 | } |
4d7206a2 | 6028 | relax_end (); |
252b5132 | 6029 | } |
0a44bf69 | 6030 | else if (mips_big_got && HAVE_NEWABI) |
f5040a92 | 6031 | { |
f5040a92 AO |
6032 | int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; |
6033 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; | |
67c0d1eb | 6034 | int add_breg_early = 0; |
f5040a92 AO |
6035 | |
6036 | /* This is the large GOT case. If this is a reference to an | |
6037 | external symbol, and there is no constant, we want | |
6038 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
6039 | add $tempreg,$tempreg,$gp | |
6040 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
1abe91b1 | 6041 | or for lca or if tempreg is PIC_CALL_REG |
f5040a92 AO |
6042 | lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) |
6043 | add $tempreg,$tempreg,$gp | |
6044 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) | |
6045 | ||
6046 | If we have a small constant, and this is a reference to | |
6047 | an external symbol, we want | |
6048 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
6049 | add $tempreg,$tempreg,$gp | |
6050 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
6051 | addi $tempreg,$tempreg,<constant> | |
6052 | ||
6053 | If we have a large constant, and this is a reference to | |
6054 | an external symbol, we want | |
6055 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
6056 | addu $tempreg,$tempreg,$gp | |
6057 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
6058 | lui $at,<hiconstant> | |
6059 | addi $at,$at,<loconstant> | |
6060 | add $tempreg,$tempreg,$at | |
6061 | ||
6062 | If we have NewABI, and we know it's a local symbol, we want | |
6063 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
6064 | addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) | |
6065 | otherwise we have to resort to GOT_HI16/GOT_LO16. */ | |
6066 | ||
4d7206a2 | 6067 | relax_start (offset_expr.X_add_symbol); |
f5040a92 | 6068 | |
4d7206a2 | 6069 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
6070 | offset_expr.X_add_number = 0; |
6071 | ||
1abe91b1 MR |
6072 | if (expr1.X_add_number == 0 && breg == 0 |
6073 | && (call || tempreg == PIC_CALL_REG)) | |
f5040a92 AO |
6074 | { |
6075 | lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; | |
6076 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; | |
6077 | } | |
67c0d1eb RS |
6078 | macro_build (&offset_expr, "lui", "t,u", tempreg, lui_reloc_type); |
6079 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 6080 | tempreg, tempreg, mips_gp_register); |
67c0d1eb RS |
6081 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
6082 | tempreg, lw_reloc_type, tempreg); | |
f5040a92 AO |
6083 | |
6084 | if (expr1.X_add_number == 0) | |
4d7206a2 | 6085 | ; |
f5040a92 AO |
6086 | else if (expr1.X_add_number >= -0x8000 |
6087 | && expr1.X_add_number < 0x8000) | |
6088 | { | |
67c0d1eb | 6089 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 6090 | tempreg, tempreg, BFD_RELOC_LO16); |
f5040a92 | 6091 | } |
ecd13cd3 | 6092 | else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000)) |
f5040a92 | 6093 | { |
f5040a92 AO |
6094 | /* If we are going to add in a base register, and the |
6095 | target register and the base register are the same, | |
6096 | then we are using AT as a temporary register. Since | |
6097 | we want to load the constant into AT, we add our | |
6098 | current AT (from the global offset table) and the | |
6099 | register into the register now, and pretend we were | |
6100 | not using a base register. */ | |
6101 | if (breg != treg) | |
6102 | dreg = tempreg; | |
6103 | else | |
6104 | { | |
9c2799c2 | 6105 | gas_assert (tempreg == AT); |
67c0d1eb | 6106 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6107 | treg, AT, breg); |
f5040a92 | 6108 | dreg = treg; |
67c0d1eb | 6109 | add_breg_early = 1; |
f5040a92 AO |
6110 | } |
6111 | ||
f6a22291 | 6112 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 6113 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT); |
f5040a92 | 6114 | |
f5040a92 AO |
6115 | used_at = 1; |
6116 | } | |
6117 | else | |
6118 | as_bad (_("PIC code offset overflow (max 32 signed bits)")); | |
6119 | ||
4d7206a2 | 6120 | relax_switch (); |
f5040a92 | 6121 | offset_expr.X_add_number = expr1.X_add_number; |
67c0d1eb RS |
6122 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
6123 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
6124 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, | |
6125 | tempreg, BFD_RELOC_MIPS_GOT_OFST); | |
6126 | if (add_breg_early) | |
f5040a92 | 6127 | { |
67c0d1eb | 6128 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6129 | treg, tempreg, breg); |
f5040a92 AO |
6130 | breg = 0; |
6131 | tempreg = treg; | |
6132 | } | |
4d7206a2 | 6133 | relax_end (); |
f5040a92 | 6134 | } |
252b5132 RH |
6135 | else |
6136 | abort (); | |
6137 | ||
6138 | if (breg != 0) | |
aed1a261 | 6139 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", treg, tempreg, breg); |
252b5132 RH |
6140 | break; |
6141 | ||
52b6b6b9 JM |
6142 | case M_MSGSND: |
6143 | { | |
6144 | unsigned long temp = (treg << 16) | (0x01); | |
6145 | macro_build (NULL, "c2", "C", temp); | |
6146 | } | |
c7af4273 | 6147 | break; |
52b6b6b9 JM |
6148 | |
6149 | case M_MSGLD: | |
6150 | { | |
6151 | unsigned long temp = (0x02); | |
6152 | macro_build (NULL, "c2", "C", temp); | |
6153 | } | |
c7af4273 | 6154 | break; |
52b6b6b9 JM |
6155 | |
6156 | case M_MSGLD_T: | |
6157 | { | |
6158 | unsigned long temp = (treg << 16) | (0x02); | |
6159 | macro_build (NULL, "c2", "C", temp); | |
6160 | } | |
c7af4273 | 6161 | break; |
52b6b6b9 JM |
6162 | |
6163 | case M_MSGWAIT: | |
6164 | macro_build (NULL, "c2", "C", 3); | |
c7af4273 | 6165 | break; |
52b6b6b9 JM |
6166 | |
6167 | case M_MSGWAIT_T: | |
6168 | { | |
6169 | unsigned long temp = (treg << 16) | 0x03; | |
6170 | macro_build (NULL, "c2", "C", temp); | |
6171 | } | |
c7af4273 | 6172 | break; |
52b6b6b9 | 6173 | |
252b5132 RH |
6174 | case M_J_A: |
6175 | /* The j instruction may not be used in PIC code, since it | |
6176 | requires an absolute address. We convert it to a b | |
6177 | instruction. */ | |
6178 | if (mips_pic == NO_PIC) | |
67c0d1eb | 6179 | macro_build (&offset_expr, "j", "a"); |
252b5132 | 6180 | else |
67c0d1eb | 6181 | macro_build (&offset_expr, "b", "p"); |
8fc2e39e | 6182 | break; |
252b5132 RH |
6183 | |
6184 | /* The jal instructions must be handled as macros because when | |
6185 | generating PIC code they expand to multi-instruction | |
6186 | sequences. Normally they are simple instructions. */ | |
6187 | case M_JAL_1: | |
6188 | dreg = RA; | |
6189 | /* Fall through. */ | |
6190 | case M_JAL_2: | |
3e722fb5 | 6191 | if (mips_pic == NO_PIC) |
67c0d1eb | 6192 | macro_build (NULL, "jalr", "d,s", dreg, sreg); |
0a44bf69 | 6193 | else |
252b5132 RH |
6194 | { |
6195 | if (sreg != PIC_CALL_REG) | |
6196 | as_warn (_("MIPS PIC call to register other than $25")); | |
bdaaa2e1 | 6197 | |
67c0d1eb | 6198 | macro_build (NULL, "jalr", "d,s", dreg, sreg); |
0a44bf69 | 6199 | if (mips_pic == SVR4_PIC && !HAVE_NEWABI) |
252b5132 | 6200 | { |
6478892d TS |
6201 | if (mips_cprestore_offset < 0) |
6202 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
6203 | else | |
6204 | { | |
90ecf173 | 6205 | if (!mips_frame_reg_valid) |
7a621144 DJ |
6206 | { |
6207 | as_warn (_("No .frame pseudo-op used in PIC code")); | |
6208 | /* Quiet this warning. */ | |
6209 | mips_frame_reg_valid = 1; | |
6210 | } | |
90ecf173 | 6211 | if (!mips_cprestore_valid) |
7a621144 DJ |
6212 | { |
6213 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
6214 | /* Quiet this warning. */ | |
6215 | mips_cprestore_valid = 1; | |
6216 | } | |
d3fca0b5 MR |
6217 | if (mips_opts.noreorder) |
6218 | macro_build (NULL, "nop", ""); | |
6478892d | 6219 | expr1.X_add_number = mips_cprestore_offset; |
67c0d1eb | 6220 | macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN, |
f899b4b8 | 6221 | mips_gp_register, |
256ab948 TS |
6222 | mips_frame_reg, |
6223 | HAVE_64BIT_ADDRESSES); | |
6478892d | 6224 | } |
252b5132 RH |
6225 | } |
6226 | } | |
252b5132 | 6227 | |
8fc2e39e | 6228 | break; |
252b5132 RH |
6229 | |
6230 | case M_JAL_A: | |
6231 | if (mips_pic == NO_PIC) | |
67c0d1eb | 6232 | macro_build (&offset_expr, "jal", "a"); |
252b5132 RH |
6233 | else if (mips_pic == SVR4_PIC) |
6234 | { | |
6235 | /* If this is a reference to an external symbol, and we are | |
6236 | using a small GOT, we want | |
6237 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16) | |
6238 | nop | |
f9419b05 | 6239 | jalr $ra,$25 |
252b5132 RH |
6240 | nop |
6241 | lw $gp,cprestore($sp) | |
6242 | The cprestore value is set using the .cprestore | |
6243 | pseudo-op. If we are using a big GOT, we want | |
6244 | lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16) | |
6245 | addu $25,$25,$gp | |
6246 | lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16) | |
6247 | nop | |
f9419b05 | 6248 | jalr $ra,$25 |
252b5132 RH |
6249 | nop |
6250 | lw $gp,cprestore($sp) | |
6251 | If the symbol is not external, we want | |
6252 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6253 | nop | |
6254 | addiu $25,$25,<sym> (BFD_RELOC_LO16) | |
f9419b05 | 6255 | jalr $ra,$25 |
252b5132 | 6256 | nop |
438c16b8 | 6257 | lw $gp,cprestore($sp) |
f5040a92 AO |
6258 | |
6259 | For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16 | |
6260 | sequences above, minus nops, unless the symbol is local, | |
6261 | which enables us to use GOT_PAGE/GOT_OFST (big got) or | |
6262 | GOT_DISP. */ | |
438c16b8 | 6263 | if (HAVE_NEWABI) |
252b5132 | 6264 | { |
90ecf173 | 6265 | if (!mips_big_got) |
f5040a92 | 6266 | { |
4d7206a2 | 6267 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
6268 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
6269 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL16, | |
f5040a92 | 6270 | mips_gp_register); |
4d7206a2 | 6271 | relax_switch (); |
67c0d1eb RS |
6272 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
6273 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT_DISP, | |
4d7206a2 RS |
6274 | mips_gp_register); |
6275 | relax_end (); | |
f5040a92 AO |
6276 | } |
6277 | else | |
6278 | { | |
4d7206a2 | 6279 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
6280 | macro_build (&offset_expr, "lui", "t,u", PIC_CALL_REG, |
6281 | BFD_RELOC_MIPS_CALL_HI16); | |
6282 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG, | |
6283 | PIC_CALL_REG, mips_gp_register); | |
6284 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", | |
6285 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16, | |
6286 | PIC_CALL_REG); | |
4d7206a2 | 6287 | relax_switch (); |
67c0d1eb RS |
6288 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
6289 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT_PAGE, | |
6290 | mips_gp_register); | |
6291 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
6292 | PIC_CALL_REG, PIC_CALL_REG, | |
17a2f251 | 6293 | BFD_RELOC_MIPS_GOT_OFST); |
4d7206a2 | 6294 | relax_end (); |
f5040a92 | 6295 | } |
684022ea | 6296 | |
67c0d1eb | 6297 | macro_build_jalr (&offset_expr); |
252b5132 RH |
6298 | } |
6299 | else | |
6300 | { | |
4d7206a2 | 6301 | relax_start (offset_expr.X_add_symbol); |
90ecf173 | 6302 | if (!mips_big_got) |
438c16b8 | 6303 | { |
67c0d1eb RS |
6304 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
6305 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL16, | |
17a2f251 | 6306 | mips_gp_register); |
269137b2 | 6307 | load_delay_nop (); |
4d7206a2 | 6308 | relax_switch (); |
438c16b8 | 6309 | } |
252b5132 | 6310 | else |
252b5132 | 6311 | { |
67c0d1eb RS |
6312 | int gpdelay; |
6313 | ||
6314 | gpdelay = reg_needs_delay (mips_gp_register); | |
6315 | macro_build (&offset_expr, "lui", "t,u", PIC_CALL_REG, | |
6316 | BFD_RELOC_MIPS_CALL_HI16); | |
6317 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG, | |
6318 | PIC_CALL_REG, mips_gp_register); | |
6319 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", | |
6320 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16, | |
6321 | PIC_CALL_REG); | |
269137b2 | 6322 | load_delay_nop (); |
4d7206a2 | 6323 | relax_switch (); |
67c0d1eb RS |
6324 | if (gpdelay) |
6325 | macro_build (NULL, "nop", ""); | |
252b5132 | 6326 | } |
67c0d1eb RS |
6327 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
6328 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT16, | |
4d7206a2 | 6329 | mips_gp_register); |
269137b2 | 6330 | load_delay_nop (); |
67c0d1eb RS |
6331 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
6332 | PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16); | |
4d7206a2 | 6333 | relax_end (); |
67c0d1eb | 6334 | macro_build_jalr (&offset_expr); |
438c16b8 | 6335 | |
6478892d TS |
6336 | if (mips_cprestore_offset < 0) |
6337 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
6338 | else | |
6339 | { | |
90ecf173 | 6340 | if (!mips_frame_reg_valid) |
7a621144 DJ |
6341 | { |
6342 | as_warn (_("No .frame pseudo-op used in PIC code")); | |
6343 | /* Quiet this warning. */ | |
6344 | mips_frame_reg_valid = 1; | |
6345 | } | |
90ecf173 | 6346 | if (!mips_cprestore_valid) |
7a621144 DJ |
6347 | { |
6348 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
6349 | /* Quiet this warning. */ | |
6350 | mips_cprestore_valid = 1; | |
6351 | } | |
6478892d | 6352 | if (mips_opts.noreorder) |
67c0d1eb | 6353 | macro_build (NULL, "nop", ""); |
6478892d | 6354 | expr1.X_add_number = mips_cprestore_offset; |
67c0d1eb | 6355 | macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN, |
f899b4b8 | 6356 | mips_gp_register, |
256ab948 TS |
6357 | mips_frame_reg, |
6358 | HAVE_64BIT_ADDRESSES); | |
6478892d | 6359 | } |
252b5132 RH |
6360 | } |
6361 | } | |
0a44bf69 RS |
6362 | else if (mips_pic == VXWORKS_PIC) |
6363 | as_bad (_("Non-PIC jump used in PIC library")); | |
252b5132 RH |
6364 | else |
6365 | abort (); | |
6366 | ||
8fc2e39e | 6367 | break; |
252b5132 RH |
6368 | |
6369 | case M_LB_AB: | |
6370 | s = "lb"; | |
6371 | goto ld; | |
6372 | case M_LBU_AB: | |
6373 | s = "lbu"; | |
6374 | goto ld; | |
6375 | case M_LH_AB: | |
6376 | s = "lh"; | |
6377 | goto ld; | |
6378 | case M_LHU_AB: | |
6379 | s = "lhu"; | |
6380 | goto ld; | |
6381 | case M_LW_AB: | |
6382 | s = "lw"; | |
6383 | goto ld; | |
6384 | case M_LWC0_AB: | |
6385 | s = "lwc0"; | |
bdaaa2e1 | 6386 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6387 | coproc = 1; |
6388 | goto ld; | |
6389 | case M_LWC1_AB: | |
6390 | s = "lwc1"; | |
bdaaa2e1 | 6391 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6392 | coproc = 1; |
6393 | goto ld; | |
6394 | case M_LWC2_AB: | |
6395 | s = "lwc2"; | |
bdaaa2e1 | 6396 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6397 | coproc = 1; |
6398 | goto ld; | |
6399 | case M_LWC3_AB: | |
6400 | s = "lwc3"; | |
bdaaa2e1 | 6401 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6402 | coproc = 1; |
6403 | goto ld; | |
6404 | case M_LWL_AB: | |
6405 | s = "lwl"; | |
6406 | lr = 1; | |
6407 | goto ld; | |
6408 | case M_LWR_AB: | |
6409 | s = "lwr"; | |
6410 | lr = 1; | |
6411 | goto ld; | |
6412 | case M_LDC1_AB: | |
252b5132 | 6413 | s = "ldc1"; |
bdaaa2e1 | 6414 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6415 | coproc = 1; |
6416 | goto ld; | |
6417 | case M_LDC2_AB: | |
6418 | s = "ldc2"; | |
bdaaa2e1 | 6419 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6420 | coproc = 1; |
6421 | goto ld; | |
6422 | case M_LDC3_AB: | |
6423 | s = "ldc3"; | |
bdaaa2e1 | 6424 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6425 | coproc = 1; |
6426 | goto ld; | |
6427 | case M_LDL_AB: | |
6428 | s = "ldl"; | |
6429 | lr = 1; | |
6430 | goto ld; | |
6431 | case M_LDR_AB: | |
6432 | s = "ldr"; | |
6433 | lr = 1; | |
6434 | goto ld; | |
6435 | case M_LL_AB: | |
6436 | s = "ll"; | |
6437 | goto ld; | |
6438 | case M_LLD_AB: | |
6439 | s = "lld"; | |
6440 | goto ld; | |
6441 | case M_LWU_AB: | |
6442 | s = "lwu"; | |
6443 | ld: | |
8fc2e39e | 6444 | if (breg == treg || coproc || lr) |
252b5132 RH |
6445 | { |
6446 | tempreg = AT; | |
6447 | used_at = 1; | |
6448 | } | |
6449 | else | |
6450 | { | |
6451 | tempreg = treg; | |
252b5132 RH |
6452 | } |
6453 | goto ld_st; | |
6454 | case M_SB_AB: | |
6455 | s = "sb"; | |
6456 | goto st; | |
6457 | case M_SH_AB: | |
6458 | s = "sh"; | |
6459 | goto st; | |
6460 | case M_SW_AB: | |
6461 | s = "sw"; | |
6462 | goto st; | |
6463 | case M_SWC0_AB: | |
6464 | s = "swc0"; | |
bdaaa2e1 | 6465 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6466 | coproc = 1; |
6467 | goto st; | |
6468 | case M_SWC1_AB: | |
6469 | s = "swc1"; | |
bdaaa2e1 | 6470 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6471 | coproc = 1; |
6472 | goto st; | |
6473 | case M_SWC2_AB: | |
6474 | s = "swc2"; | |
bdaaa2e1 | 6475 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6476 | coproc = 1; |
6477 | goto st; | |
6478 | case M_SWC3_AB: | |
6479 | s = "swc3"; | |
bdaaa2e1 | 6480 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6481 | coproc = 1; |
6482 | goto st; | |
6483 | case M_SWL_AB: | |
6484 | s = "swl"; | |
6485 | goto st; | |
6486 | case M_SWR_AB: | |
6487 | s = "swr"; | |
6488 | goto st; | |
6489 | case M_SC_AB: | |
6490 | s = "sc"; | |
6491 | goto st; | |
6492 | case M_SCD_AB: | |
6493 | s = "scd"; | |
6494 | goto st; | |
d43b4baf TS |
6495 | case M_CACHE_AB: |
6496 | s = "cache"; | |
6497 | goto st; | |
252b5132 | 6498 | case M_SDC1_AB: |
252b5132 RH |
6499 | s = "sdc1"; |
6500 | coproc = 1; | |
bdaaa2e1 | 6501 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6502 | goto st; |
6503 | case M_SDC2_AB: | |
6504 | s = "sdc2"; | |
bdaaa2e1 | 6505 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6506 | coproc = 1; |
6507 | goto st; | |
6508 | case M_SDC3_AB: | |
6509 | s = "sdc3"; | |
bdaaa2e1 | 6510 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6511 | coproc = 1; |
6512 | goto st; | |
6513 | case M_SDL_AB: | |
6514 | s = "sdl"; | |
6515 | goto st; | |
6516 | case M_SDR_AB: | |
6517 | s = "sdr"; | |
6518 | st: | |
8fc2e39e TS |
6519 | tempreg = AT; |
6520 | used_at = 1; | |
252b5132 | 6521 | ld_st: |
b19e8a9b AN |
6522 | if (coproc |
6523 | && NO_ISA_COP (mips_opts.arch) | |
6524 | && (ip->insn_mo->pinfo2 & (INSN2_M_FP_S | INSN2_M_FP_D)) == 0) | |
6525 | { | |
f71d0d44 | 6526 | as_bad (_("Opcode not supported on this processor: %s"), |
b19e8a9b AN |
6527 | mips_cpu_info_from_arch (mips_opts.arch)->name); |
6528 | break; | |
6529 | } | |
6530 | ||
bdaaa2e1 | 6531 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6532 | if (mask == M_LWC1_AB |
6533 | || mask == M_SWC1_AB | |
6534 | || mask == M_LDC1_AB | |
6535 | || mask == M_SDC1_AB | |
6536 | || mask == M_L_DAB | |
6537 | || mask == M_S_DAB) | |
6538 | fmt = "T,o(b)"; | |
d43b4baf TS |
6539 | else if (mask == M_CACHE_AB) |
6540 | fmt = "k,o(b)"; | |
252b5132 RH |
6541 | else if (coproc) |
6542 | fmt = "E,o(b)"; | |
6543 | else | |
6544 | fmt = "t,o(b)"; | |
6545 | ||
6546 | if (offset_expr.X_op != O_constant | |
6547 | && offset_expr.X_op != O_symbol) | |
6548 | { | |
f71d0d44 | 6549 | as_bad (_("Expression too complex")); |
252b5132 RH |
6550 | offset_expr.X_op = O_constant; |
6551 | } | |
6552 | ||
2051e8c4 MR |
6553 | if (HAVE_32BIT_ADDRESSES |
6554 | && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) | |
55e08f71 NC |
6555 | { |
6556 | char value [32]; | |
6557 | ||
6558 | sprintf_vma (value, offset_expr.X_add_number); | |
20e1fcfd | 6559 | as_bad (_("Number (0x%s) larger than 32 bits"), value); |
55e08f71 | 6560 | } |
2051e8c4 | 6561 | |
252b5132 RH |
6562 | /* A constant expression in PIC code can be handled just as it |
6563 | is in non PIC code. */ | |
aed1a261 RS |
6564 | if (offset_expr.X_op == O_constant) |
6565 | { | |
842f8b2a | 6566 | expr1.X_add_number = offset_expr.X_add_number; |
2051e8c4 | 6567 | normalize_address_expr (&expr1); |
842f8b2a MR |
6568 | if (!IS_SEXT_16BIT_NUM (expr1.X_add_number)) |
6569 | { | |
6570 | expr1.X_add_number = ((expr1.X_add_number + 0x8000) | |
6571 | & ~(bfd_vma) 0xffff); | |
6572 | load_register (tempreg, &expr1, HAVE_64BIT_ADDRESSES); | |
6573 | if (breg != 0) | |
6574 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
6575 | tempreg, tempreg, breg); | |
6576 | breg = tempreg; | |
6577 | } | |
6578 | macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, breg); | |
aed1a261 RS |
6579 | } |
6580 | else if (mips_pic == NO_PIC) | |
252b5132 RH |
6581 | { |
6582 | /* If this is a reference to a GP relative symbol, and there | |
6583 | is no base register, we want | |
cdf6fd85 | 6584 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
252b5132 RH |
6585 | Otherwise, if there is no base register, we want |
6586 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
6587 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
6588 | If we have a constant, we need two instructions anyhow, | |
6589 | so we always use the latter form. | |
6590 | ||
6591 | If we have a base register, and this is a reference to a | |
6592 | GP relative symbol, we want | |
6593 | addu $tempreg,$breg,$gp | |
cdf6fd85 | 6594 | <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16) |
252b5132 RH |
6595 | Otherwise we want |
6596 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
6597 | addu $tempreg,$tempreg,$breg | |
6598 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
d6bc6245 | 6599 | With a constant we always use the latter case. |
76b3015f | 6600 | |
d6bc6245 TS |
6601 | With 64bit address space and no base register and $at usable, |
6602 | we want | |
6603 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
6604 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
6605 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
6606 | dsll32 $tempreg,0 | |
6607 | daddu $tempreg,$at | |
6608 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
6609 | If we have a base register, we want | |
6610 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
6611 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
6612 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
6613 | daddu $at,$breg | |
6614 | dsll32 $tempreg,0 | |
6615 | daddu $tempreg,$at | |
6616 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
6617 | ||
6618 | Without $at we can't generate the optimal path for superscalar | |
6619 | processors here since this would require two temporary registers. | |
6620 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
6621 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
6622 | dsll $tempreg,16 | |
6623 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
6624 | dsll $tempreg,16 | |
6625 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
6626 | If we have a base register, we want | |
6627 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
6628 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
6629 | dsll $tempreg,16 | |
6630 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
6631 | dsll $tempreg,16 | |
6632 | daddu $tempreg,$tempreg,$breg | |
6633 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
6373ee54 | 6634 | |
6caf9ef4 | 6635 | For GP relative symbols in 64bit address space we can use |
aed1a261 RS |
6636 | the same sequence as in 32bit address space. */ |
6637 | if (HAVE_64BIT_SYMBOLS) | |
d6bc6245 | 6638 | { |
aed1a261 | 6639 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 TS |
6640 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
6641 | { | |
6642 | relax_start (offset_expr.X_add_symbol); | |
6643 | if (breg == 0) | |
6644 | { | |
6645 | macro_build (&offset_expr, s, fmt, treg, | |
6646 | BFD_RELOC_GPREL16, mips_gp_register); | |
6647 | } | |
6648 | else | |
6649 | { | |
6650 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
6651 | tempreg, breg, mips_gp_register); | |
6652 | macro_build (&offset_expr, s, fmt, treg, | |
6653 | BFD_RELOC_GPREL16, tempreg); | |
6654 | } | |
6655 | relax_switch (); | |
6656 | } | |
d6bc6245 | 6657 | |
741fe287 | 6658 | if (used_at == 0 && mips_opts.at) |
d6bc6245 | 6659 | { |
67c0d1eb RS |
6660 | macro_build (&offset_expr, "lui", "t,u", tempreg, |
6661 | BFD_RELOC_MIPS_HIGHEST); | |
6662 | macro_build (&offset_expr, "lui", "t,u", AT, | |
6663 | BFD_RELOC_HI16_S); | |
6664 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
6665 | tempreg, BFD_RELOC_MIPS_HIGHER); | |
d6bc6245 | 6666 | if (breg != 0) |
67c0d1eb RS |
6667 | macro_build (NULL, "daddu", "d,v,t", AT, AT, breg); |
6668 | macro_build (NULL, "dsll32", "d,w,<", tempreg, tempreg, 0); | |
6669 | macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT); | |
6670 | macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, | |
6671 | tempreg); | |
d6bc6245 TS |
6672 | used_at = 1; |
6673 | } | |
6674 | else | |
6675 | { | |
67c0d1eb RS |
6676 | macro_build (&offset_expr, "lui", "t,u", tempreg, |
6677 | BFD_RELOC_MIPS_HIGHEST); | |
6678 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
6679 | tempreg, BFD_RELOC_MIPS_HIGHER); | |
6680 | macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16); | |
6681 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
6682 | tempreg, BFD_RELOC_HI16_S); | |
6683 | macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16); | |
d6bc6245 | 6684 | if (breg != 0) |
67c0d1eb | 6685 | macro_build (NULL, "daddu", "d,v,t", |
17a2f251 | 6686 | tempreg, tempreg, breg); |
67c0d1eb | 6687 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 6688 | BFD_RELOC_LO16, tempreg); |
d6bc6245 | 6689 | } |
6caf9ef4 TS |
6690 | |
6691 | if (mips_relax.sequence) | |
6692 | relax_end (); | |
8fc2e39e | 6693 | break; |
d6bc6245 | 6694 | } |
256ab948 | 6695 | |
252b5132 RH |
6696 | if (breg == 0) |
6697 | { | |
67c0d1eb | 6698 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 6699 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 6700 | { |
4d7206a2 | 6701 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
6702 | macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_GPREL16, |
6703 | mips_gp_register); | |
4d7206a2 | 6704 | relax_switch (); |
252b5132 | 6705 | } |
67c0d1eb RS |
6706 | macro_build_lui (&offset_expr, tempreg); |
6707 | macro_build (&offset_expr, s, fmt, treg, | |
17a2f251 | 6708 | BFD_RELOC_LO16, tempreg); |
4d7206a2 RS |
6709 | if (mips_relax.sequence) |
6710 | relax_end (); | |
252b5132 RH |
6711 | } |
6712 | else | |
6713 | { | |
67c0d1eb | 6714 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 6715 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 6716 | { |
4d7206a2 | 6717 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 6718 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6719 | tempreg, breg, mips_gp_register); |
67c0d1eb | 6720 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 6721 | BFD_RELOC_GPREL16, tempreg); |
4d7206a2 | 6722 | relax_switch (); |
252b5132 | 6723 | } |
67c0d1eb RS |
6724 | macro_build_lui (&offset_expr, tempreg); |
6725 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 6726 | tempreg, tempreg, breg); |
67c0d1eb | 6727 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 6728 | BFD_RELOC_LO16, tempreg); |
4d7206a2 RS |
6729 | if (mips_relax.sequence) |
6730 | relax_end (); | |
252b5132 RH |
6731 | } |
6732 | } | |
0a44bf69 | 6733 | else if (!mips_big_got) |
252b5132 | 6734 | { |
ed6fb7bd | 6735 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
f9419b05 | 6736 | |
252b5132 RH |
6737 | /* If this is a reference to an external symbol, we want |
6738 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6739 | nop | |
6740 | <op> $treg,0($tempreg) | |
6741 | Otherwise we want | |
6742 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6743 | nop | |
6744 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
6745 | <op> $treg,0($tempreg) | |
f5040a92 AO |
6746 | |
6747 | For NewABI, we want | |
6748 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
6749 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) | |
6750 | ||
252b5132 RH |
6751 | If there is a base register, we add it to $tempreg before |
6752 | the <op>. If there is a constant, we stick it in the | |
6753 | <op> instruction. We don't handle constants larger than | |
6754 | 16 bits, because we have no way to load the upper 16 bits | |
6755 | (actually, we could handle them for the subset of cases | |
6756 | in which we are not using $at). */ | |
9c2799c2 | 6757 | gas_assert (offset_expr.X_op == O_symbol); |
f5040a92 AO |
6758 | if (HAVE_NEWABI) |
6759 | { | |
67c0d1eb RS |
6760 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
6761 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
f5040a92 | 6762 | if (breg != 0) |
67c0d1eb | 6763 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6764 | tempreg, tempreg, breg); |
67c0d1eb | 6765 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 6766 | BFD_RELOC_MIPS_GOT_OFST, tempreg); |
f5040a92 AO |
6767 | break; |
6768 | } | |
252b5132 RH |
6769 | expr1.X_add_number = offset_expr.X_add_number; |
6770 | offset_expr.X_add_number = 0; | |
6771 | if (expr1.X_add_number < -0x8000 | |
6772 | || expr1.X_add_number >= 0x8000) | |
6773 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb RS |
6774 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
6775 | lw_reloc_type, mips_gp_register); | |
269137b2 | 6776 | load_delay_nop (); |
4d7206a2 RS |
6777 | relax_start (offset_expr.X_add_symbol); |
6778 | relax_switch (); | |
67c0d1eb RS |
6779 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, |
6780 | tempreg, BFD_RELOC_LO16); | |
4d7206a2 | 6781 | relax_end (); |
252b5132 | 6782 | if (breg != 0) |
67c0d1eb | 6783 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6784 | tempreg, tempreg, breg); |
67c0d1eb | 6785 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
252b5132 | 6786 | } |
0a44bf69 | 6787 | else if (mips_big_got && !HAVE_NEWABI) |
252b5132 | 6788 | { |
67c0d1eb | 6789 | int gpdelay; |
252b5132 RH |
6790 | |
6791 | /* If this is a reference to an external symbol, we want | |
6792 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
6793 | addu $tempreg,$tempreg,$gp | |
6794 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
6795 | <op> $treg,0($tempreg) | |
6796 | Otherwise we want | |
6797 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6798 | nop | |
6799 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
6800 | <op> $treg,0($tempreg) | |
6801 | If there is a base register, we add it to $tempreg before | |
6802 | the <op>. If there is a constant, we stick it in the | |
6803 | <op> instruction. We don't handle constants larger than | |
6804 | 16 bits, because we have no way to load the upper 16 bits | |
6805 | (actually, we could handle them for the subset of cases | |
f5040a92 | 6806 | in which we are not using $at). */ |
9c2799c2 | 6807 | gas_assert (offset_expr.X_op == O_symbol); |
252b5132 RH |
6808 | expr1.X_add_number = offset_expr.X_add_number; |
6809 | offset_expr.X_add_number = 0; | |
6810 | if (expr1.X_add_number < -0x8000 | |
6811 | || expr1.X_add_number >= 0x8000) | |
6812 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 6813 | gpdelay = reg_needs_delay (mips_gp_register); |
4d7206a2 | 6814 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 6815 | macro_build (&offset_expr, "lui", "t,u", tempreg, |
17a2f251 | 6816 | BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
6817 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, |
6818 | mips_gp_register); | |
6819 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
6820 | BFD_RELOC_MIPS_GOT_LO16, tempreg); | |
4d7206a2 | 6821 | relax_switch (); |
67c0d1eb RS |
6822 | if (gpdelay) |
6823 | macro_build (NULL, "nop", ""); | |
6824 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
6825 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 6826 | load_delay_nop (); |
67c0d1eb RS |
6827 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, |
6828 | tempreg, BFD_RELOC_LO16); | |
4d7206a2 RS |
6829 | relax_end (); |
6830 | ||
252b5132 | 6831 | if (breg != 0) |
67c0d1eb | 6832 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6833 | tempreg, tempreg, breg); |
67c0d1eb | 6834 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
252b5132 | 6835 | } |
0a44bf69 | 6836 | else if (mips_big_got && HAVE_NEWABI) |
f5040a92 | 6837 | { |
f5040a92 AO |
6838 | /* If this is a reference to an external symbol, we want |
6839 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
6840 | add $tempreg,$tempreg,$gp | |
6841 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
6842 | <op> $treg,<ofst>($tempreg) | |
6843 | Otherwise, for local symbols, we want: | |
6844 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
6845 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */ | |
9c2799c2 | 6846 | gas_assert (offset_expr.X_op == O_symbol); |
4d7206a2 | 6847 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
6848 | offset_expr.X_add_number = 0; |
6849 | if (expr1.X_add_number < -0x8000 | |
6850 | || expr1.X_add_number >= 0x8000) | |
6851 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4d7206a2 | 6852 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 6853 | macro_build (&offset_expr, "lui", "t,u", tempreg, |
17a2f251 | 6854 | BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
6855 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, |
6856 | mips_gp_register); | |
6857 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
6858 | BFD_RELOC_MIPS_GOT_LO16, tempreg); | |
f5040a92 | 6859 | if (breg != 0) |
67c0d1eb | 6860 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6861 | tempreg, tempreg, breg); |
67c0d1eb | 6862 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
684022ea | 6863 | |
4d7206a2 | 6864 | relax_switch (); |
f5040a92 | 6865 | offset_expr.X_add_number = expr1.X_add_number; |
67c0d1eb RS |
6866 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
6867 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
f5040a92 | 6868 | if (breg != 0) |
67c0d1eb | 6869 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6870 | tempreg, tempreg, breg); |
67c0d1eb | 6871 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 6872 | BFD_RELOC_MIPS_GOT_OFST, tempreg); |
4d7206a2 | 6873 | relax_end (); |
f5040a92 | 6874 | } |
252b5132 RH |
6875 | else |
6876 | abort (); | |
6877 | ||
252b5132 RH |
6878 | break; |
6879 | ||
6880 | case M_LI: | |
6881 | case M_LI_S: | |
67c0d1eb | 6882 | load_register (treg, &imm_expr, 0); |
8fc2e39e | 6883 | break; |
252b5132 RH |
6884 | |
6885 | case M_DLI: | |
67c0d1eb | 6886 | load_register (treg, &imm_expr, 1); |
8fc2e39e | 6887 | break; |
252b5132 RH |
6888 | |
6889 | case M_LI_SS: | |
6890 | if (imm_expr.X_op == O_constant) | |
6891 | { | |
8fc2e39e | 6892 | used_at = 1; |
67c0d1eb RS |
6893 | load_register (AT, &imm_expr, 0); |
6894 | macro_build (NULL, "mtc1", "t,G", AT, treg); | |
252b5132 RH |
6895 | break; |
6896 | } | |
6897 | else | |
6898 | { | |
9c2799c2 | 6899 | gas_assert (offset_expr.X_op == O_symbol |
90ecf173 MR |
6900 | && strcmp (segment_name (S_GET_SEGMENT |
6901 | (offset_expr.X_add_symbol)), | |
6902 | ".lit4") == 0 | |
6903 | && offset_expr.X_add_number == 0); | |
67c0d1eb | 6904 | macro_build (&offset_expr, "lwc1", "T,o(b)", treg, |
17a2f251 | 6905 | BFD_RELOC_MIPS_LITERAL, mips_gp_register); |
8fc2e39e | 6906 | break; |
252b5132 RH |
6907 | } |
6908 | ||
6909 | case M_LI_D: | |
ca4e0257 RS |
6910 | /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits |
6911 | wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high | |
6912 | order 32 bits of the value and the low order 32 bits are either | |
6913 | zero or in OFFSET_EXPR. */ | |
252b5132 RH |
6914 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) |
6915 | { | |
ca4e0257 | 6916 | if (HAVE_64BIT_GPRS) |
67c0d1eb | 6917 | load_register (treg, &imm_expr, 1); |
252b5132 RH |
6918 | else |
6919 | { | |
6920 | int hreg, lreg; | |
6921 | ||
6922 | if (target_big_endian) | |
6923 | { | |
6924 | hreg = treg; | |
6925 | lreg = treg + 1; | |
6926 | } | |
6927 | else | |
6928 | { | |
6929 | hreg = treg + 1; | |
6930 | lreg = treg; | |
6931 | } | |
6932 | ||
6933 | if (hreg <= 31) | |
67c0d1eb | 6934 | load_register (hreg, &imm_expr, 0); |
252b5132 RH |
6935 | if (lreg <= 31) |
6936 | { | |
6937 | if (offset_expr.X_op == O_absent) | |
67c0d1eb | 6938 | move_register (lreg, 0); |
252b5132 RH |
6939 | else |
6940 | { | |
9c2799c2 | 6941 | gas_assert (offset_expr.X_op == O_constant); |
67c0d1eb | 6942 | load_register (lreg, &offset_expr, 0); |
252b5132 RH |
6943 | } |
6944 | } | |
6945 | } | |
8fc2e39e | 6946 | break; |
252b5132 RH |
6947 | } |
6948 | ||
6949 | /* We know that sym is in the .rdata section. First we get the | |
6950 | upper 16 bits of the address. */ | |
6951 | if (mips_pic == NO_PIC) | |
6952 | { | |
67c0d1eb | 6953 | macro_build_lui (&offset_expr, AT); |
8fc2e39e | 6954 | used_at = 1; |
252b5132 | 6955 | } |
0a44bf69 | 6956 | else |
252b5132 | 6957 | { |
67c0d1eb RS |
6958 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, |
6959 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
8fc2e39e | 6960 | used_at = 1; |
252b5132 | 6961 | } |
bdaaa2e1 | 6962 | |
252b5132 | 6963 | /* Now we load the register(s). */ |
ca4e0257 | 6964 | if (HAVE_64BIT_GPRS) |
8fc2e39e TS |
6965 | { |
6966 | used_at = 1; | |
6967 | macro_build (&offset_expr, "ld", "t,o(b)", treg, BFD_RELOC_LO16, AT); | |
6968 | } | |
252b5132 RH |
6969 | else |
6970 | { | |
8fc2e39e | 6971 | used_at = 1; |
67c0d1eb | 6972 | macro_build (&offset_expr, "lw", "t,o(b)", treg, BFD_RELOC_LO16, AT); |
f9419b05 | 6973 | if (treg != RA) |
252b5132 RH |
6974 | { |
6975 | /* FIXME: How in the world do we deal with the possible | |
6976 | overflow here? */ | |
6977 | offset_expr.X_add_number += 4; | |
67c0d1eb | 6978 | macro_build (&offset_expr, "lw", "t,o(b)", |
17a2f251 | 6979 | treg + 1, BFD_RELOC_LO16, AT); |
252b5132 RH |
6980 | } |
6981 | } | |
252b5132 RH |
6982 | break; |
6983 | ||
6984 | case M_LI_DD: | |
ca4e0257 RS |
6985 | /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits |
6986 | wide, IMM_EXPR is the entire value and the GPRs are known to be 64 | |
6987 | bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of | |
6988 | the value and the low order 32 bits are either zero or in | |
6989 | OFFSET_EXPR. */ | |
252b5132 RH |
6990 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) |
6991 | { | |
8fc2e39e | 6992 | used_at = 1; |
67c0d1eb | 6993 | load_register (AT, &imm_expr, HAVE_64BIT_FPRS); |
ca4e0257 RS |
6994 | if (HAVE_64BIT_FPRS) |
6995 | { | |
9c2799c2 | 6996 | gas_assert (HAVE_64BIT_GPRS); |
67c0d1eb | 6997 | macro_build (NULL, "dmtc1", "t,S", AT, treg); |
ca4e0257 | 6998 | } |
252b5132 RH |
6999 | else |
7000 | { | |
67c0d1eb | 7001 | macro_build (NULL, "mtc1", "t,G", AT, treg + 1); |
252b5132 | 7002 | if (offset_expr.X_op == O_absent) |
67c0d1eb | 7003 | macro_build (NULL, "mtc1", "t,G", 0, treg); |
252b5132 RH |
7004 | else |
7005 | { | |
9c2799c2 | 7006 | gas_assert (offset_expr.X_op == O_constant); |
67c0d1eb RS |
7007 | load_register (AT, &offset_expr, 0); |
7008 | macro_build (NULL, "mtc1", "t,G", AT, treg); | |
252b5132 RH |
7009 | } |
7010 | } | |
7011 | break; | |
7012 | } | |
7013 | ||
9c2799c2 | 7014 | gas_assert (offset_expr.X_op == O_symbol |
90ecf173 | 7015 | && offset_expr.X_add_number == 0); |
252b5132 RH |
7016 | s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol)); |
7017 | if (strcmp (s, ".lit8") == 0) | |
7018 | { | |
e7af610e | 7019 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 | 7020 | { |
67c0d1eb | 7021 | macro_build (&offset_expr, "ldc1", "T,o(b)", treg, |
17a2f251 | 7022 | BFD_RELOC_MIPS_LITERAL, mips_gp_register); |
8fc2e39e | 7023 | break; |
252b5132 | 7024 | } |
c9914766 | 7025 | breg = mips_gp_register; |
252b5132 RH |
7026 | r = BFD_RELOC_MIPS_LITERAL; |
7027 | goto dob; | |
7028 | } | |
7029 | else | |
7030 | { | |
9c2799c2 | 7031 | gas_assert (strcmp (s, RDATA_SECTION_NAME) == 0); |
8fc2e39e | 7032 | used_at = 1; |
0a44bf69 | 7033 | if (mips_pic != NO_PIC) |
67c0d1eb RS |
7034 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, |
7035 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
252b5132 RH |
7036 | else |
7037 | { | |
7038 | /* FIXME: This won't work for a 64 bit address. */ | |
67c0d1eb | 7039 | macro_build_lui (&offset_expr, AT); |
252b5132 | 7040 | } |
bdaaa2e1 | 7041 | |
e7af610e | 7042 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 | 7043 | { |
67c0d1eb RS |
7044 | macro_build (&offset_expr, "ldc1", "T,o(b)", |
7045 | treg, BFD_RELOC_LO16, AT); | |
252b5132 RH |
7046 | break; |
7047 | } | |
7048 | breg = AT; | |
7049 | r = BFD_RELOC_LO16; | |
7050 | goto dob; | |
7051 | } | |
7052 | ||
7053 | case M_L_DOB: | |
252b5132 RH |
7054 | /* Even on a big endian machine $fn comes before $fn+1. We have |
7055 | to adjust when loading from memory. */ | |
7056 | r = BFD_RELOC_LO16; | |
7057 | dob: | |
9c2799c2 | 7058 | gas_assert (mips_opts.isa == ISA_MIPS1); |
67c0d1eb | 7059 | macro_build (&offset_expr, "lwc1", "T,o(b)", |
17a2f251 | 7060 | target_big_endian ? treg + 1 : treg, r, breg); |
252b5132 RH |
7061 | /* FIXME: A possible overflow which I don't know how to deal |
7062 | with. */ | |
7063 | offset_expr.X_add_number += 4; | |
67c0d1eb | 7064 | macro_build (&offset_expr, "lwc1", "T,o(b)", |
17a2f251 | 7065 | target_big_endian ? treg : treg + 1, r, breg); |
252b5132 RH |
7066 | break; |
7067 | ||
c4a68bea MR |
7068 | case M_S_DOB: |
7069 | gas_assert (mips_opts.isa == ISA_MIPS1); | |
7070 | /* Even on a big endian machine $fn comes before $fn+1. We have | |
7071 | to adjust when storing to memory. */ | |
7072 | macro_build (&offset_expr, "swc1", "T,o(b)", | |
7073 | target_big_endian ? treg + 1 : treg, BFD_RELOC_LO16, breg); | |
7074 | offset_expr.X_add_number += 4; | |
7075 | macro_build (&offset_expr, "swc1", "T,o(b)", | |
7076 | target_big_endian ? treg : treg + 1, BFD_RELOC_LO16, breg); | |
7077 | break; | |
7078 | ||
252b5132 RH |
7079 | case M_L_DAB: |
7080 | /* | |
7081 | * The MIPS assembler seems to check for X_add_number not | |
7082 | * being double aligned and generating: | |
7083 | * lui at,%hi(foo+1) | |
7084 | * addu at,at,v1 | |
7085 | * addiu at,at,%lo(foo+1) | |
7086 | * lwc1 f2,0(at) | |
7087 | * lwc1 f3,4(at) | |
7088 | * But, the resulting address is the same after relocation so why | |
7089 | * generate the extra instruction? | |
7090 | */ | |
bdaaa2e1 | 7091 | /* Itbl support may require additional care here. */ |
252b5132 | 7092 | coproc = 1; |
e7af610e | 7093 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 RH |
7094 | { |
7095 | s = "ldc1"; | |
7096 | goto ld; | |
7097 | } | |
7098 | ||
7099 | s = "lwc1"; | |
7100 | fmt = "T,o(b)"; | |
7101 | goto ldd_std; | |
7102 | ||
7103 | case M_S_DAB: | |
e7af610e | 7104 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 RH |
7105 | { |
7106 | s = "sdc1"; | |
7107 | goto st; | |
7108 | } | |
7109 | ||
7110 | s = "swc1"; | |
7111 | fmt = "T,o(b)"; | |
bdaaa2e1 | 7112 | /* Itbl support may require additional care here. */ |
252b5132 RH |
7113 | coproc = 1; |
7114 | goto ldd_std; | |
7115 | ||
7116 | case M_LD_AB: | |
ca4e0257 | 7117 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
7118 | { |
7119 | s = "ld"; | |
7120 | goto ld; | |
7121 | } | |
7122 | ||
7123 | s = "lw"; | |
7124 | fmt = "t,o(b)"; | |
7125 | goto ldd_std; | |
7126 | ||
7127 | case M_SD_AB: | |
ca4e0257 | 7128 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
7129 | { |
7130 | s = "sd"; | |
7131 | goto st; | |
7132 | } | |
7133 | ||
7134 | s = "sw"; | |
7135 | fmt = "t,o(b)"; | |
7136 | ||
7137 | ldd_std: | |
7138 | if (offset_expr.X_op != O_symbol | |
7139 | && offset_expr.X_op != O_constant) | |
7140 | { | |
f71d0d44 | 7141 | as_bad (_("Expression too complex")); |
252b5132 RH |
7142 | offset_expr.X_op = O_constant; |
7143 | } | |
7144 | ||
2051e8c4 MR |
7145 | if (HAVE_32BIT_ADDRESSES |
7146 | && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) | |
55e08f71 NC |
7147 | { |
7148 | char value [32]; | |
7149 | ||
7150 | sprintf_vma (value, offset_expr.X_add_number); | |
20e1fcfd | 7151 | as_bad (_("Number (0x%s) larger than 32 bits"), value); |
55e08f71 | 7152 | } |
2051e8c4 | 7153 | |
252b5132 RH |
7154 | /* Even on a big endian machine $fn comes before $fn+1. We have |
7155 | to adjust when loading from memory. We set coproc if we must | |
7156 | load $fn+1 first. */ | |
bdaaa2e1 | 7157 | /* Itbl support may require additional care here. */ |
90ecf173 | 7158 | if (!target_big_endian) |
252b5132 RH |
7159 | coproc = 0; |
7160 | ||
90ecf173 | 7161 | if (mips_pic == NO_PIC || offset_expr.X_op == O_constant) |
252b5132 RH |
7162 | { |
7163 | /* If this is a reference to a GP relative symbol, we want | |
cdf6fd85 TS |
7164 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
7165 | <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16) | |
252b5132 RH |
7166 | If we have a base register, we use this |
7167 | addu $at,$breg,$gp | |
cdf6fd85 TS |
7168 | <op> $treg,<sym>($at) (BFD_RELOC_GPREL16) |
7169 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16) | |
252b5132 RH |
7170 | If this is not a GP relative symbol, we want |
7171 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
7172 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
7173 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
7174 | If there is a base register, we add it to $at after the | |
7175 | lui instruction. If there is a constant, we always use | |
7176 | the last case. */ | |
39a59cf8 MR |
7177 | if (offset_expr.X_op == O_symbol |
7178 | && (valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET | |
6caf9ef4 | 7179 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 7180 | { |
4d7206a2 | 7181 | relax_start (offset_expr.X_add_symbol); |
252b5132 RH |
7182 | if (breg == 0) |
7183 | { | |
c9914766 | 7184 | tempreg = mips_gp_register; |
252b5132 RH |
7185 | } |
7186 | else | |
7187 | { | |
67c0d1eb | 7188 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7189 | AT, breg, mips_gp_register); |
252b5132 | 7190 | tempreg = AT; |
252b5132 RH |
7191 | used_at = 1; |
7192 | } | |
7193 | ||
beae10d5 | 7194 | /* Itbl support may require additional care here. */ |
67c0d1eb | 7195 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 7196 | BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
7197 | offset_expr.X_add_number += 4; |
7198 | ||
7199 | /* Set mips_optimize to 2 to avoid inserting an | |
7200 | undesired nop. */ | |
7201 | hold_mips_optimize = mips_optimize; | |
7202 | mips_optimize = 2; | |
beae10d5 | 7203 | /* Itbl support may require additional care here. */ |
67c0d1eb | 7204 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 7205 | BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
7206 | mips_optimize = hold_mips_optimize; |
7207 | ||
4d7206a2 | 7208 | relax_switch (); |
252b5132 | 7209 | |
0970e49e | 7210 | offset_expr.X_add_number -= 4; |
252b5132 | 7211 | } |
8fc2e39e | 7212 | used_at = 1; |
67c0d1eb | 7213 | macro_build_lui (&offset_expr, AT); |
252b5132 | 7214 | if (breg != 0) |
67c0d1eb | 7215 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 7216 | /* Itbl support may require additional care here. */ |
67c0d1eb | 7217 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 7218 | BFD_RELOC_LO16, AT); |
252b5132 RH |
7219 | /* FIXME: How do we handle overflow here? */ |
7220 | offset_expr.X_add_number += 4; | |
beae10d5 | 7221 | /* Itbl support may require additional care here. */ |
67c0d1eb | 7222 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 7223 | BFD_RELOC_LO16, AT); |
4d7206a2 RS |
7224 | if (mips_relax.sequence) |
7225 | relax_end (); | |
bdaaa2e1 | 7226 | } |
0a44bf69 | 7227 | else if (!mips_big_got) |
252b5132 | 7228 | { |
252b5132 RH |
7229 | /* If this is a reference to an external symbol, we want |
7230 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7231 | nop | |
7232 | <op> $treg,0($at) | |
7233 | <op> $treg+1,4($at) | |
7234 | Otherwise we want | |
7235 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7236 | nop | |
7237 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
7238 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
7239 | If there is a base register we add it to $at before the | |
7240 | lwc1 instructions. If there is a constant we include it | |
7241 | in the lwc1 instructions. */ | |
7242 | used_at = 1; | |
7243 | expr1.X_add_number = offset_expr.X_add_number; | |
252b5132 RH |
7244 | if (expr1.X_add_number < -0x8000 |
7245 | || expr1.X_add_number >= 0x8000 - 4) | |
7246 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 7247 | load_got_offset (AT, &offset_expr); |
269137b2 | 7248 | load_delay_nop (); |
252b5132 | 7249 | if (breg != 0) |
67c0d1eb | 7250 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
252b5132 RH |
7251 | |
7252 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
7253 | nop. */ | |
7254 | hold_mips_optimize = mips_optimize; | |
7255 | mips_optimize = 2; | |
4d7206a2 | 7256 | |
beae10d5 | 7257 | /* Itbl support may require additional care here. */ |
4d7206a2 | 7258 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
7259 | macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg, |
7260 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 7261 | expr1.X_add_number += 4; |
67c0d1eb RS |
7262 | macro_build (&expr1, s, fmt, coproc ? treg : treg + 1, |
7263 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 7264 | relax_switch (); |
67c0d1eb RS |
7265 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
7266 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 7267 | offset_expr.X_add_number += 4; |
67c0d1eb RS |
7268 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
7269 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 7270 | relax_end (); |
252b5132 | 7271 | |
4d7206a2 | 7272 | mips_optimize = hold_mips_optimize; |
252b5132 | 7273 | } |
0a44bf69 | 7274 | else if (mips_big_got) |
252b5132 | 7275 | { |
67c0d1eb | 7276 | int gpdelay; |
252b5132 RH |
7277 | |
7278 | /* If this is a reference to an external symbol, we want | |
7279 | lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
7280 | addu $at,$at,$gp | |
7281 | lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16) | |
7282 | nop | |
7283 | <op> $treg,0($at) | |
7284 | <op> $treg+1,4($at) | |
7285 | Otherwise we want | |
7286 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7287 | nop | |
7288 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
7289 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
7290 | If there is a base register we add it to $at before the | |
7291 | lwc1 instructions. If there is a constant we include it | |
7292 | in the lwc1 instructions. */ | |
7293 | used_at = 1; | |
7294 | expr1.X_add_number = offset_expr.X_add_number; | |
7295 | offset_expr.X_add_number = 0; | |
7296 | if (expr1.X_add_number < -0x8000 | |
7297 | || expr1.X_add_number >= 0x8000 - 4) | |
7298 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 7299 | gpdelay = reg_needs_delay (mips_gp_register); |
4d7206a2 | 7300 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
7301 | macro_build (&offset_expr, "lui", "t,u", |
7302 | AT, BFD_RELOC_MIPS_GOT_HI16); | |
7303 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 7304 | AT, AT, mips_gp_register); |
67c0d1eb | 7305 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
17a2f251 | 7306 | AT, BFD_RELOC_MIPS_GOT_LO16, AT); |
269137b2 | 7307 | load_delay_nop (); |
252b5132 | 7308 | if (breg != 0) |
67c0d1eb | 7309 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 7310 | /* Itbl support may require additional care here. */ |
67c0d1eb | 7311 | macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 7312 | BFD_RELOC_LO16, AT); |
252b5132 RH |
7313 | expr1.X_add_number += 4; |
7314 | ||
7315 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
7316 | nop. */ | |
7317 | hold_mips_optimize = mips_optimize; | |
7318 | mips_optimize = 2; | |
beae10d5 | 7319 | /* Itbl support may require additional care here. */ |
67c0d1eb | 7320 | macro_build (&expr1, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 7321 | BFD_RELOC_LO16, AT); |
252b5132 RH |
7322 | mips_optimize = hold_mips_optimize; |
7323 | expr1.X_add_number -= 4; | |
7324 | ||
4d7206a2 RS |
7325 | relax_switch (); |
7326 | offset_expr.X_add_number = expr1.X_add_number; | |
67c0d1eb RS |
7327 | if (gpdelay) |
7328 | macro_build (NULL, "nop", ""); | |
7329 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, | |
7330 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 7331 | load_delay_nop (); |
252b5132 | 7332 | if (breg != 0) |
67c0d1eb | 7333 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 7334 | /* Itbl support may require additional care here. */ |
67c0d1eb RS |
7335 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
7336 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 7337 | offset_expr.X_add_number += 4; |
252b5132 RH |
7338 | |
7339 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
7340 | nop. */ | |
7341 | hold_mips_optimize = mips_optimize; | |
7342 | mips_optimize = 2; | |
beae10d5 | 7343 | /* Itbl support may require additional care here. */ |
67c0d1eb RS |
7344 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
7345 | BFD_RELOC_LO16, AT); | |
252b5132 | 7346 | mips_optimize = hold_mips_optimize; |
4d7206a2 | 7347 | relax_end (); |
252b5132 | 7348 | } |
252b5132 RH |
7349 | else |
7350 | abort (); | |
7351 | ||
252b5132 RH |
7352 | break; |
7353 | ||
7354 | case M_LD_OB: | |
704897fb | 7355 | s = HAVE_64BIT_GPRS ? "ld" : "lw"; |
252b5132 RH |
7356 | goto sd_ob; |
7357 | case M_SD_OB: | |
704897fb | 7358 | s = HAVE_64BIT_GPRS ? "sd" : "sw"; |
252b5132 | 7359 | sd_ob: |
4614d845 MR |
7360 | macro_build (&offset_expr, s, "t,o(b)", treg, |
7361 | -1, offset_reloc[0], offset_reloc[1], offset_reloc[2], | |
7362 | breg); | |
704897fb MR |
7363 | if (!HAVE_64BIT_GPRS) |
7364 | { | |
7365 | offset_expr.X_add_number += 4; | |
7366 | macro_build (&offset_expr, s, "t,o(b)", treg + 1, | |
4614d845 MR |
7367 | -1, offset_reloc[0], offset_reloc[1], offset_reloc[2], |
7368 | breg); | |
704897fb | 7369 | } |
8fc2e39e | 7370 | break; |
252b5132 RH |
7371 | |
7372 | /* New code added to support COPZ instructions. | |
7373 | This code builds table entries out of the macros in mip_opcodes. | |
7374 | R4000 uses interlocks to handle coproc delays. | |
7375 | Other chips (like the R3000) require nops to be inserted for delays. | |
7376 | ||
f72c8c98 | 7377 | FIXME: Currently, we require that the user handle delays. |
252b5132 RH |
7378 | In order to fill delay slots for non-interlocked chips, |
7379 | we must have a way to specify delays based on the coprocessor. | |
7380 | Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc. | |
7381 | What are the side-effects of the cop instruction? | |
7382 | What cache support might we have and what are its effects? | |
7383 | Both coprocessor & memory require delays. how long??? | |
bdaaa2e1 | 7384 | What registers are read/set/modified? |
252b5132 RH |
7385 | |
7386 | If an itbl is provided to interpret cop instructions, | |
bdaaa2e1 | 7387 | this knowledge can be encoded in the itbl spec. */ |
252b5132 RH |
7388 | |
7389 | case M_COP0: | |
7390 | s = "c0"; | |
7391 | goto copz; | |
7392 | case M_COP1: | |
7393 | s = "c1"; | |
7394 | goto copz; | |
7395 | case M_COP2: | |
7396 | s = "c2"; | |
7397 | goto copz; | |
7398 | case M_COP3: | |
7399 | s = "c3"; | |
7400 | copz: | |
b19e8a9b AN |
7401 | if (NO_ISA_COP (mips_opts.arch) |
7402 | && (ip->insn_mo->pinfo2 & INSN2_M_FP_S) == 0) | |
7403 | { | |
7404 | as_bad (_("opcode not supported on this processor: %s"), | |
7405 | mips_cpu_info_from_arch (mips_opts.arch)->name); | |
7406 | break; | |
7407 | } | |
7408 | ||
252b5132 RH |
7409 | /* For now we just do C (same as Cz). The parameter will be |
7410 | stored in insn_opcode by mips_ip. */ | |
67c0d1eb | 7411 | macro_build (NULL, s, "C", ip->insn_opcode); |
8fc2e39e | 7412 | break; |
252b5132 | 7413 | |
ea1fb5dc | 7414 | case M_MOVE: |
67c0d1eb | 7415 | move_register (dreg, sreg); |
8fc2e39e | 7416 | break; |
ea1fb5dc | 7417 | |
252b5132 RH |
7418 | case M_DMUL: |
7419 | dbl = 1; | |
7420 | case M_MUL: | |
67c0d1eb RS |
7421 | macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", sreg, treg); |
7422 | macro_build (NULL, "mflo", "d", dreg); | |
8fc2e39e | 7423 | break; |
252b5132 RH |
7424 | |
7425 | case M_DMUL_I: | |
7426 | dbl = 1; | |
7427 | case M_MUL_I: | |
7428 | /* The MIPS assembler some times generates shifts and adds. I'm | |
7429 | not trying to be that fancy. GCC should do this for us | |
7430 | anyway. */ | |
8fc2e39e | 7431 | used_at = 1; |
67c0d1eb RS |
7432 | load_register (AT, &imm_expr, dbl); |
7433 | macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, AT); | |
7434 | macro_build (NULL, "mflo", "d", dreg); | |
252b5132 RH |
7435 | break; |
7436 | ||
7437 | case M_DMULO_I: | |
7438 | dbl = 1; | |
7439 | case M_MULO_I: | |
7440 | imm = 1; | |
7441 | goto do_mulo; | |
7442 | ||
7443 | case M_DMULO: | |
7444 | dbl = 1; | |
7445 | case M_MULO: | |
7446 | do_mulo: | |
7d10b47d | 7447 | start_noreorder (); |
8fc2e39e | 7448 | used_at = 1; |
252b5132 | 7449 | if (imm) |
67c0d1eb RS |
7450 | load_register (AT, &imm_expr, dbl); |
7451 | macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, imm ? AT : treg); | |
7452 | macro_build (NULL, "mflo", "d", dreg); | |
7453 | macro_build (NULL, dbl ? "dsra32" : "sra", "d,w,<", dreg, dreg, RA); | |
7454 | macro_build (NULL, "mfhi", "d", AT); | |
252b5132 | 7455 | if (mips_trap) |
67c0d1eb | 7456 | macro_build (NULL, "tne", "s,t,q", dreg, AT, 6); |
252b5132 RH |
7457 | else |
7458 | { | |
7459 | expr1.X_add_number = 8; | |
67c0d1eb | 7460 | macro_build (&expr1, "beq", "s,t,p", dreg, AT); |
a605d2b3 | 7461 | macro_build (NULL, "nop", ""); |
67c0d1eb | 7462 | macro_build (NULL, "break", "c", 6); |
252b5132 | 7463 | } |
7d10b47d | 7464 | end_noreorder (); |
67c0d1eb | 7465 | macro_build (NULL, "mflo", "d", dreg); |
252b5132 RH |
7466 | break; |
7467 | ||
7468 | case M_DMULOU_I: | |
7469 | dbl = 1; | |
7470 | case M_MULOU_I: | |
7471 | imm = 1; | |
7472 | goto do_mulou; | |
7473 | ||
7474 | case M_DMULOU: | |
7475 | dbl = 1; | |
7476 | case M_MULOU: | |
7477 | do_mulou: | |
7d10b47d | 7478 | start_noreorder (); |
8fc2e39e | 7479 | used_at = 1; |
252b5132 | 7480 | if (imm) |
67c0d1eb RS |
7481 | load_register (AT, &imm_expr, dbl); |
7482 | macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", | |
17a2f251 | 7483 | sreg, imm ? AT : treg); |
67c0d1eb RS |
7484 | macro_build (NULL, "mfhi", "d", AT); |
7485 | macro_build (NULL, "mflo", "d", dreg); | |
252b5132 | 7486 | if (mips_trap) |
c80c840e | 7487 | macro_build (NULL, "tne", "s,t,q", AT, ZERO, 6); |
252b5132 RH |
7488 | else |
7489 | { | |
7490 | expr1.X_add_number = 8; | |
c80c840e | 7491 | macro_build (&expr1, "beq", "s,t,p", AT, ZERO); |
a605d2b3 | 7492 | macro_build (NULL, "nop", ""); |
67c0d1eb | 7493 | macro_build (NULL, "break", "c", 6); |
252b5132 | 7494 | } |
7d10b47d | 7495 | end_noreorder (); |
252b5132 RH |
7496 | break; |
7497 | ||
771c7ce4 | 7498 | case M_DROL: |
fef14a42 | 7499 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 CD |
7500 | { |
7501 | if (dreg == sreg) | |
7502 | { | |
7503 | tempreg = AT; | |
7504 | used_at = 1; | |
7505 | } | |
7506 | else | |
7507 | { | |
7508 | tempreg = dreg; | |
82dd0097 | 7509 | } |
67c0d1eb RS |
7510 | macro_build (NULL, "dnegu", "d,w", tempreg, treg); |
7511 | macro_build (NULL, "drorv", "d,t,s", dreg, sreg, tempreg); | |
8fc2e39e | 7512 | break; |
82dd0097 | 7513 | } |
8fc2e39e | 7514 | used_at = 1; |
c80c840e | 7515 | macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, treg); |
67c0d1eb RS |
7516 | macro_build (NULL, "dsrlv", "d,t,s", AT, sreg, AT); |
7517 | macro_build (NULL, "dsllv", "d,t,s", dreg, sreg, treg); | |
7518 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
7519 | break; |
7520 | ||
252b5132 | 7521 | case M_ROL: |
fef14a42 | 7522 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 CD |
7523 | { |
7524 | if (dreg == sreg) | |
7525 | { | |
7526 | tempreg = AT; | |
7527 | used_at = 1; | |
7528 | } | |
7529 | else | |
7530 | { | |
7531 | tempreg = dreg; | |
82dd0097 | 7532 | } |
67c0d1eb RS |
7533 | macro_build (NULL, "negu", "d,w", tempreg, treg); |
7534 | macro_build (NULL, "rorv", "d,t,s", dreg, sreg, tempreg); | |
8fc2e39e | 7535 | break; |
82dd0097 | 7536 | } |
8fc2e39e | 7537 | used_at = 1; |
c80c840e | 7538 | macro_build (NULL, "subu", "d,v,t", AT, ZERO, treg); |
67c0d1eb RS |
7539 | macro_build (NULL, "srlv", "d,t,s", AT, sreg, AT); |
7540 | macro_build (NULL, "sllv", "d,t,s", dreg, sreg, treg); | |
7541 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
7542 | break; |
7543 | ||
771c7ce4 TS |
7544 | case M_DROL_I: |
7545 | { | |
7546 | unsigned int rot; | |
91d6fa6a NC |
7547 | char *l; |
7548 | char *rr; | |
771c7ce4 TS |
7549 | |
7550 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 7551 | as_bad (_("Improper rotate count")); |
771c7ce4 | 7552 | rot = imm_expr.X_add_number & 0x3f; |
fef14a42 | 7553 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
60b63b72 RS |
7554 | { |
7555 | rot = (64 - rot) & 0x3f; | |
7556 | if (rot >= 32) | |
67c0d1eb | 7557 | macro_build (NULL, "dror32", "d,w,<", dreg, sreg, rot - 32); |
60b63b72 | 7558 | else |
67c0d1eb | 7559 | macro_build (NULL, "dror", "d,w,<", dreg, sreg, rot); |
8fc2e39e | 7560 | break; |
60b63b72 | 7561 | } |
483fc7cd | 7562 | if (rot == 0) |
483fc7cd | 7563 | { |
67c0d1eb | 7564 | macro_build (NULL, "dsrl", "d,w,<", dreg, sreg, 0); |
8fc2e39e | 7565 | break; |
483fc7cd | 7566 | } |
82dd0097 | 7567 | l = (rot < 0x20) ? "dsll" : "dsll32"; |
91d6fa6a | 7568 | rr = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32"; |
82dd0097 | 7569 | rot &= 0x1f; |
8fc2e39e | 7570 | used_at = 1; |
67c0d1eb | 7571 | macro_build (NULL, l, "d,w,<", AT, sreg, rot); |
91d6fa6a | 7572 | macro_build (NULL, rr, "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); |
67c0d1eb | 7573 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); |
771c7ce4 TS |
7574 | } |
7575 | break; | |
7576 | ||
252b5132 | 7577 | case M_ROL_I: |
771c7ce4 TS |
7578 | { |
7579 | unsigned int rot; | |
7580 | ||
7581 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 7582 | as_bad (_("Improper rotate count")); |
771c7ce4 | 7583 | rot = imm_expr.X_add_number & 0x1f; |
fef14a42 | 7584 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
60b63b72 | 7585 | { |
67c0d1eb | 7586 | macro_build (NULL, "ror", "d,w,<", dreg, sreg, (32 - rot) & 0x1f); |
8fc2e39e | 7587 | break; |
60b63b72 | 7588 | } |
483fc7cd | 7589 | if (rot == 0) |
483fc7cd | 7590 | { |
67c0d1eb | 7591 | macro_build (NULL, "srl", "d,w,<", dreg, sreg, 0); |
8fc2e39e | 7592 | break; |
483fc7cd | 7593 | } |
8fc2e39e | 7594 | used_at = 1; |
67c0d1eb RS |
7595 | macro_build (NULL, "sll", "d,w,<", AT, sreg, rot); |
7596 | macro_build (NULL, "srl", "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); | |
7597 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
7598 | } |
7599 | break; | |
7600 | ||
7601 | case M_DROR: | |
fef14a42 | 7602 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 | 7603 | { |
67c0d1eb | 7604 | macro_build (NULL, "drorv", "d,t,s", dreg, sreg, treg); |
8fc2e39e | 7605 | break; |
82dd0097 | 7606 | } |
8fc2e39e | 7607 | used_at = 1; |
c80c840e | 7608 | macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, treg); |
67c0d1eb RS |
7609 | macro_build (NULL, "dsllv", "d,t,s", AT, sreg, AT); |
7610 | macro_build (NULL, "dsrlv", "d,t,s", dreg, sreg, treg); | |
7611 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
7612 | break; |
7613 | ||
7614 | case M_ROR: | |
fef14a42 | 7615 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 | 7616 | { |
67c0d1eb | 7617 | macro_build (NULL, "rorv", "d,t,s", dreg, sreg, treg); |
8fc2e39e | 7618 | break; |
82dd0097 | 7619 | } |
8fc2e39e | 7620 | used_at = 1; |
c80c840e | 7621 | macro_build (NULL, "subu", "d,v,t", AT, ZERO, treg); |
67c0d1eb RS |
7622 | macro_build (NULL, "sllv", "d,t,s", AT, sreg, AT); |
7623 | macro_build (NULL, "srlv", "d,t,s", dreg, sreg, treg); | |
7624 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
7625 | break; |
7626 | ||
771c7ce4 TS |
7627 | case M_DROR_I: |
7628 | { | |
7629 | unsigned int rot; | |
91d6fa6a NC |
7630 | char *l; |
7631 | char *rr; | |
771c7ce4 TS |
7632 | |
7633 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 7634 | as_bad (_("Improper rotate count")); |
771c7ce4 | 7635 | rot = imm_expr.X_add_number & 0x3f; |
fef14a42 | 7636 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 CD |
7637 | { |
7638 | if (rot >= 32) | |
67c0d1eb | 7639 | macro_build (NULL, "dror32", "d,w,<", dreg, sreg, rot - 32); |
82dd0097 | 7640 | else |
67c0d1eb | 7641 | macro_build (NULL, "dror", "d,w,<", dreg, sreg, rot); |
8fc2e39e | 7642 | break; |
82dd0097 | 7643 | } |
483fc7cd | 7644 | if (rot == 0) |
483fc7cd | 7645 | { |
67c0d1eb | 7646 | macro_build (NULL, "dsrl", "d,w,<", dreg, sreg, 0); |
8fc2e39e | 7647 | break; |
483fc7cd | 7648 | } |
91d6fa6a | 7649 | rr = (rot < 0x20) ? "dsrl" : "dsrl32"; |
82dd0097 CD |
7650 | l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32"; |
7651 | rot &= 0x1f; | |
8fc2e39e | 7652 | used_at = 1; |
91d6fa6a | 7653 | macro_build (NULL, rr, "d,w,<", AT, sreg, rot); |
67c0d1eb RS |
7654 | macro_build (NULL, l, "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); |
7655 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
7656 | } |
7657 | break; | |
7658 | ||
252b5132 | 7659 | case M_ROR_I: |
771c7ce4 TS |
7660 | { |
7661 | unsigned int rot; | |
7662 | ||
7663 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 7664 | as_bad (_("Improper rotate count")); |
771c7ce4 | 7665 | rot = imm_expr.X_add_number & 0x1f; |
fef14a42 | 7666 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 | 7667 | { |
67c0d1eb | 7668 | macro_build (NULL, "ror", "d,w,<", dreg, sreg, rot); |
8fc2e39e | 7669 | break; |
82dd0097 | 7670 | } |
483fc7cd | 7671 | if (rot == 0) |
483fc7cd | 7672 | { |
67c0d1eb | 7673 | macro_build (NULL, "srl", "d,w,<", dreg, sreg, 0); |
8fc2e39e | 7674 | break; |
483fc7cd | 7675 | } |
8fc2e39e | 7676 | used_at = 1; |
67c0d1eb RS |
7677 | macro_build (NULL, "srl", "d,w,<", AT, sreg, rot); |
7678 | macro_build (NULL, "sll", "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); | |
7679 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 | 7680 | } |
252b5132 RH |
7681 | break; |
7682 | ||
252b5132 RH |
7683 | case M_SEQ: |
7684 | if (sreg == 0) | |
67c0d1eb | 7685 | macro_build (&expr1, "sltiu", "t,r,j", dreg, treg, BFD_RELOC_LO16); |
252b5132 | 7686 | else if (treg == 0) |
67c0d1eb | 7687 | macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7688 | else |
7689 | { | |
67c0d1eb RS |
7690 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg); |
7691 | macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16); | |
252b5132 | 7692 | } |
8fc2e39e | 7693 | break; |
252b5132 RH |
7694 | |
7695 | case M_SEQ_I: | |
7696 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
7697 | { | |
67c0d1eb | 7698 | macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 7699 | break; |
252b5132 RH |
7700 | } |
7701 | if (sreg == 0) | |
7702 | { | |
7703 | as_warn (_("Instruction %s: result is always false"), | |
7704 | ip->insn_mo->name); | |
67c0d1eb | 7705 | move_register (dreg, 0); |
8fc2e39e | 7706 | break; |
252b5132 | 7707 | } |
dd3cbb7e NC |
7708 | if (CPU_HAS_SEQ (mips_opts.arch) |
7709 | && -512 <= imm_expr.X_add_number | |
7710 | && imm_expr.X_add_number < 512) | |
7711 | { | |
7712 | macro_build (NULL, "seqi", "t,r,+Q", dreg, sreg, | |
750bdd57 | 7713 | (int) imm_expr.X_add_number); |
dd3cbb7e NC |
7714 | break; |
7715 | } | |
252b5132 RH |
7716 | if (imm_expr.X_op == O_constant |
7717 | && imm_expr.X_add_number >= 0 | |
7718 | && imm_expr.X_add_number < 0x10000) | |
7719 | { | |
67c0d1eb | 7720 | macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7721 | } |
7722 | else if (imm_expr.X_op == O_constant | |
7723 | && imm_expr.X_add_number > -0x8000 | |
7724 | && imm_expr.X_add_number < 0) | |
7725 | { | |
7726 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 7727 | macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu", |
17a2f251 | 7728 | "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 | 7729 | } |
dd3cbb7e NC |
7730 | else if (CPU_HAS_SEQ (mips_opts.arch)) |
7731 | { | |
7732 | used_at = 1; | |
7733 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); | |
7734 | macro_build (NULL, "seq", "d,v,t", dreg, sreg, AT); | |
7735 | break; | |
7736 | } | |
252b5132 RH |
7737 | else |
7738 | { | |
67c0d1eb RS |
7739 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7740 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7741 | used_at = 1; |
7742 | } | |
67c0d1eb | 7743 | macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16); |
8fc2e39e | 7744 | break; |
252b5132 RH |
7745 | |
7746 | case M_SGE: /* sreg >= treg <==> not (sreg < treg) */ | |
7747 | s = "slt"; | |
7748 | goto sge; | |
7749 | case M_SGEU: | |
7750 | s = "sltu"; | |
7751 | sge: | |
67c0d1eb RS |
7752 | macro_build (NULL, s, "d,v,t", dreg, sreg, treg); |
7753 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
8fc2e39e | 7754 | break; |
252b5132 RH |
7755 | |
7756 | case M_SGE_I: /* sreg >= I <==> not (sreg < I) */ | |
7757 | case M_SGEU_I: | |
7758 | if (imm_expr.X_op == O_constant | |
7759 | && imm_expr.X_add_number >= -0x8000 | |
7760 | && imm_expr.X_add_number < 0x8000) | |
7761 | { | |
67c0d1eb RS |
7762 | macro_build (&imm_expr, mask == M_SGE_I ? "slti" : "sltiu", "t,r,j", |
7763 | dreg, sreg, BFD_RELOC_LO16); | |
252b5132 RH |
7764 | } |
7765 | else | |
7766 | { | |
67c0d1eb RS |
7767 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7768 | macro_build (NULL, mask == M_SGE_I ? "slt" : "sltu", "d,v,t", | |
7769 | dreg, sreg, AT); | |
252b5132 RH |
7770 | used_at = 1; |
7771 | } | |
67c0d1eb | 7772 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); |
8fc2e39e | 7773 | break; |
252b5132 RH |
7774 | |
7775 | case M_SGT: /* sreg > treg <==> treg < sreg */ | |
7776 | s = "slt"; | |
7777 | goto sgt; | |
7778 | case M_SGTU: | |
7779 | s = "sltu"; | |
7780 | sgt: | |
67c0d1eb | 7781 | macro_build (NULL, s, "d,v,t", dreg, treg, sreg); |
8fc2e39e | 7782 | break; |
252b5132 RH |
7783 | |
7784 | case M_SGT_I: /* sreg > I <==> I < sreg */ | |
7785 | s = "slt"; | |
7786 | goto sgti; | |
7787 | case M_SGTU_I: | |
7788 | s = "sltu"; | |
7789 | sgti: | |
8fc2e39e | 7790 | used_at = 1; |
67c0d1eb RS |
7791 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7792 | macro_build (NULL, s, "d,v,t", dreg, AT, sreg); | |
252b5132 RH |
7793 | break; |
7794 | ||
2396cfb9 | 7795 | case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */ |
252b5132 RH |
7796 | s = "slt"; |
7797 | goto sle; | |
7798 | case M_SLEU: | |
7799 | s = "sltu"; | |
7800 | sle: | |
67c0d1eb RS |
7801 | macro_build (NULL, s, "d,v,t", dreg, treg, sreg); |
7802 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
8fc2e39e | 7803 | break; |
252b5132 | 7804 | |
2396cfb9 | 7805 | case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */ |
252b5132 RH |
7806 | s = "slt"; |
7807 | goto slei; | |
7808 | case M_SLEU_I: | |
7809 | s = "sltu"; | |
7810 | slei: | |
8fc2e39e | 7811 | used_at = 1; |
67c0d1eb RS |
7812 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7813 | macro_build (NULL, s, "d,v,t", dreg, AT, sreg); | |
7814 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
252b5132 RH |
7815 | break; |
7816 | ||
7817 | case M_SLT_I: | |
7818 | if (imm_expr.X_op == O_constant | |
7819 | && imm_expr.X_add_number >= -0x8000 | |
7820 | && imm_expr.X_add_number < 0x8000) | |
7821 | { | |
67c0d1eb | 7822 | macro_build (&imm_expr, "slti", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 7823 | break; |
252b5132 | 7824 | } |
8fc2e39e | 7825 | used_at = 1; |
67c0d1eb RS |
7826 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7827 | macro_build (NULL, "slt", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7828 | break; |
7829 | ||
7830 | case M_SLTU_I: | |
7831 | if (imm_expr.X_op == O_constant | |
7832 | && imm_expr.X_add_number >= -0x8000 | |
7833 | && imm_expr.X_add_number < 0x8000) | |
7834 | { | |
67c0d1eb | 7835 | macro_build (&imm_expr, "sltiu", "t,r,j", dreg, sreg, |
17a2f251 | 7836 | BFD_RELOC_LO16); |
8fc2e39e | 7837 | break; |
252b5132 | 7838 | } |
8fc2e39e | 7839 | used_at = 1; |
67c0d1eb RS |
7840 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7841 | macro_build (NULL, "sltu", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7842 | break; |
7843 | ||
7844 | case M_SNE: | |
7845 | if (sreg == 0) | |
67c0d1eb | 7846 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, treg); |
252b5132 | 7847 | else if (treg == 0) |
67c0d1eb | 7848 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg); |
252b5132 RH |
7849 | else |
7850 | { | |
67c0d1eb RS |
7851 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg); |
7852 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg); | |
252b5132 | 7853 | } |
8fc2e39e | 7854 | break; |
252b5132 RH |
7855 | |
7856 | case M_SNE_I: | |
7857 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
7858 | { | |
67c0d1eb | 7859 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg); |
8fc2e39e | 7860 | break; |
252b5132 RH |
7861 | } |
7862 | if (sreg == 0) | |
7863 | { | |
7864 | as_warn (_("Instruction %s: result is always true"), | |
7865 | ip->insn_mo->name); | |
67c0d1eb RS |
7866 | macro_build (&expr1, HAVE_32BIT_GPRS ? "addiu" : "daddiu", "t,r,j", |
7867 | dreg, 0, BFD_RELOC_LO16); | |
8fc2e39e | 7868 | break; |
252b5132 | 7869 | } |
dd3cbb7e NC |
7870 | if (CPU_HAS_SEQ (mips_opts.arch) |
7871 | && -512 <= imm_expr.X_add_number | |
7872 | && imm_expr.X_add_number < 512) | |
7873 | { | |
7874 | macro_build (NULL, "snei", "t,r,+Q", dreg, sreg, | |
750bdd57 | 7875 | (int) imm_expr.X_add_number); |
dd3cbb7e NC |
7876 | break; |
7877 | } | |
252b5132 RH |
7878 | if (imm_expr.X_op == O_constant |
7879 | && imm_expr.X_add_number >= 0 | |
7880 | && imm_expr.X_add_number < 0x10000) | |
7881 | { | |
67c0d1eb | 7882 | macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7883 | } |
7884 | else if (imm_expr.X_op == O_constant | |
7885 | && imm_expr.X_add_number > -0x8000 | |
7886 | && imm_expr.X_add_number < 0) | |
7887 | { | |
7888 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 7889 | macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu", |
17a2f251 | 7890 | "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 | 7891 | } |
dd3cbb7e NC |
7892 | else if (CPU_HAS_SEQ (mips_opts.arch)) |
7893 | { | |
7894 | used_at = 1; | |
7895 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); | |
7896 | macro_build (NULL, "sne", "d,v,t", dreg, sreg, AT); | |
7897 | break; | |
7898 | } | |
252b5132 RH |
7899 | else |
7900 | { | |
67c0d1eb RS |
7901 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7902 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7903 | used_at = 1; |
7904 | } | |
67c0d1eb | 7905 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg); |
8fc2e39e | 7906 | break; |
252b5132 RH |
7907 | |
7908 | case M_DSUB_I: | |
7909 | dbl = 1; | |
7910 | case M_SUB_I: | |
7911 | if (imm_expr.X_op == O_constant | |
7912 | && imm_expr.X_add_number > -0x8000 | |
7913 | && imm_expr.X_add_number <= 0x8000) | |
7914 | { | |
7915 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb RS |
7916 | macro_build (&imm_expr, dbl ? "daddi" : "addi", "t,r,j", |
7917 | dreg, sreg, BFD_RELOC_LO16); | |
8fc2e39e | 7918 | break; |
252b5132 | 7919 | } |
8fc2e39e | 7920 | used_at = 1; |
67c0d1eb RS |
7921 | load_register (AT, &imm_expr, dbl); |
7922 | macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7923 | break; |
7924 | ||
7925 | case M_DSUBU_I: | |
7926 | dbl = 1; | |
7927 | case M_SUBU_I: | |
7928 | if (imm_expr.X_op == O_constant | |
7929 | && imm_expr.X_add_number > -0x8000 | |
7930 | && imm_expr.X_add_number <= 0x8000) | |
7931 | { | |
7932 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb RS |
7933 | macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "t,r,j", |
7934 | dreg, sreg, BFD_RELOC_LO16); | |
8fc2e39e | 7935 | break; |
252b5132 | 7936 | } |
8fc2e39e | 7937 | used_at = 1; |
67c0d1eb RS |
7938 | load_register (AT, &imm_expr, dbl); |
7939 | macro_build (NULL, dbl ? "dsubu" : "subu", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7940 | break; |
7941 | ||
7942 | case M_TEQ_I: | |
7943 | s = "teq"; | |
7944 | goto trap; | |
7945 | case M_TGE_I: | |
7946 | s = "tge"; | |
7947 | goto trap; | |
7948 | case M_TGEU_I: | |
7949 | s = "tgeu"; | |
7950 | goto trap; | |
7951 | case M_TLT_I: | |
7952 | s = "tlt"; | |
7953 | goto trap; | |
7954 | case M_TLTU_I: | |
7955 | s = "tltu"; | |
7956 | goto trap; | |
7957 | case M_TNE_I: | |
7958 | s = "tne"; | |
7959 | trap: | |
8fc2e39e | 7960 | used_at = 1; |
67c0d1eb RS |
7961 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7962 | macro_build (NULL, s, "s,t", sreg, AT); | |
252b5132 RH |
7963 | break; |
7964 | ||
252b5132 | 7965 | case M_TRUNCWS: |
43841e91 | 7966 | case M_TRUNCWD: |
9c2799c2 | 7967 | gas_assert (mips_opts.isa == ISA_MIPS1); |
8fc2e39e | 7968 | used_at = 1; |
252b5132 RH |
7969 | sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */ |
7970 | dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */ | |
7971 | ||
7972 | /* | |
7973 | * Is the double cfc1 instruction a bug in the mips assembler; | |
7974 | * or is there a reason for it? | |
7975 | */ | |
7d10b47d | 7976 | start_noreorder (); |
67c0d1eb RS |
7977 | macro_build (NULL, "cfc1", "t,G", treg, RA); |
7978 | macro_build (NULL, "cfc1", "t,G", treg, RA); | |
7979 | macro_build (NULL, "nop", ""); | |
252b5132 | 7980 | expr1.X_add_number = 3; |
67c0d1eb | 7981 | macro_build (&expr1, "ori", "t,r,i", AT, treg, BFD_RELOC_LO16); |
252b5132 | 7982 | expr1.X_add_number = 2; |
67c0d1eb RS |
7983 | macro_build (&expr1, "xori", "t,r,i", AT, AT, BFD_RELOC_LO16); |
7984 | macro_build (NULL, "ctc1", "t,G", AT, RA); | |
7985 | macro_build (NULL, "nop", ""); | |
7986 | macro_build (NULL, mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S", | |
7987 | dreg, sreg); | |
7988 | macro_build (NULL, "ctc1", "t,G", treg, RA); | |
7989 | macro_build (NULL, "nop", ""); | |
7d10b47d | 7990 | end_noreorder (); |
252b5132 RH |
7991 | break; |
7992 | ||
7993 | case M_ULH: | |
7994 | s = "lb"; | |
7995 | goto ulh; | |
7996 | case M_ULHU: | |
7997 | s = "lbu"; | |
7998 | ulh: | |
8fc2e39e | 7999 | used_at = 1; |
252b5132 | 8000 | if (offset_expr.X_add_number >= 0x7fff) |
f71d0d44 | 8001 | as_bad (_("Operand overflow")); |
90ecf173 | 8002 | if (!target_big_endian) |
f9419b05 | 8003 | ++offset_expr.X_add_number; |
67c0d1eb | 8004 | macro_build (&offset_expr, s, "t,o(b)", AT, BFD_RELOC_LO16, breg); |
90ecf173 | 8005 | if (!target_big_endian) |
f9419b05 | 8006 | --offset_expr.X_add_number; |
252b5132 | 8007 | else |
f9419b05 | 8008 | ++offset_expr.X_add_number; |
67c0d1eb RS |
8009 | macro_build (&offset_expr, "lbu", "t,o(b)", treg, BFD_RELOC_LO16, breg); |
8010 | macro_build (NULL, "sll", "d,w,<", AT, AT, 8); | |
8011 | macro_build (NULL, "or", "d,v,t", treg, treg, AT); | |
252b5132 RH |
8012 | break; |
8013 | ||
8014 | case M_ULD: | |
8015 | s = "ldl"; | |
8016 | s2 = "ldr"; | |
8017 | off = 7; | |
8018 | goto ulw; | |
8019 | case M_ULW: | |
8020 | s = "lwl"; | |
8021 | s2 = "lwr"; | |
8022 | off = 3; | |
8023 | ulw: | |
8024 | if (offset_expr.X_add_number >= 0x8000 - off) | |
f71d0d44 | 8025 | as_bad (_("Operand overflow")); |
af22f5b2 CD |
8026 | if (treg != breg) |
8027 | tempreg = treg; | |
8028 | else | |
8fc2e39e TS |
8029 | { |
8030 | used_at = 1; | |
8031 | tempreg = AT; | |
8032 | } | |
90ecf173 | 8033 | if (!target_big_endian) |
252b5132 | 8034 | offset_expr.X_add_number += off; |
67c0d1eb | 8035 | macro_build (&offset_expr, s, "t,o(b)", tempreg, BFD_RELOC_LO16, breg); |
90ecf173 | 8036 | if (!target_big_endian) |
252b5132 RH |
8037 | offset_expr.X_add_number -= off; |
8038 | else | |
8039 | offset_expr.X_add_number += off; | |
67c0d1eb | 8040 | macro_build (&offset_expr, s2, "t,o(b)", tempreg, BFD_RELOC_LO16, breg); |
af22f5b2 | 8041 | |
90ecf173 | 8042 | /* If necessary, move the result in tempreg to the final destination. */ |
af22f5b2 | 8043 | if (treg == tempreg) |
8fc2e39e | 8044 | break; |
af22f5b2 | 8045 | /* Protect second load's delay slot. */ |
017315e4 | 8046 | load_delay_nop (); |
67c0d1eb | 8047 | move_register (treg, tempreg); |
af22f5b2 | 8048 | break; |
252b5132 RH |
8049 | |
8050 | case M_ULD_A: | |
8051 | s = "ldl"; | |
8052 | s2 = "ldr"; | |
8053 | off = 7; | |
8054 | goto ulwa; | |
8055 | case M_ULW_A: | |
8056 | s = "lwl"; | |
8057 | s2 = "lwr"; | |
8058 | off = 3; | |
8059 | ulwa: | |
d6bc6245 | 8060 | used_at = 1; |
67c0d1eb | 8061 | load_address (AT, &offset_expr, &used_at); |
252b5132 | 8062 | if (breg != 0) |
67c0d1eb | 8063 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); |
90ecf173 | 8064 | if (!target_big_endian) |
252b5132 RH |
8065 | expr1.X_add_number = off; |
8066 | else | |
8067 | expr1.X_add_number = 0; | |
67c0d1eb | 8068 | macro_build (&expr1, s, "t,o(b)", treg, BFD_RELOC_LO16, AT); |
90ecf173 | 8069 | if (!target_big_endian) |
252b5132 RH |
8070 | expr1.X_add_number = 0; |
8071 | else | |
8072 | expr1.X_add_number = off; | |
67c0d1eb | 8073 | macro_build (&expr1, s2, "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
8074 | break; |
8075 | ||
8076 | case M_ULH_A: | |
8077 | case M_ULHU_A: | |
d6bc6245 | 8078 | used_at = 1; |
67c0d1eb | 8079 | load_address (AT, &offset_expr, &used_at); |
252b5132 | 8080 | if (breg != 0) |
67c0d1eb | 8081 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); |
252b5132 RH |
8082 | if (target_big_endian) |
8083 | expr1.X_add_number = 0; | |
67c0d1eb | 8084 | macro_build (&expr1, mask == M_ULH_A ? "lb" : "lbu", "t,o(b)", |
17a2f251 | 8085 | treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
8086 | if (target_big_endian) |
8087 | expr1.X_add_number = 1; | |
8088 | else | |
8089 | expr1.X_add_number = 0; | |
67c0d1eb RS |
8090 | macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT); |
8091 | macro_build (NULL, "sll", "d,w,<", treg, treg, 8); | |
8092 | macro_build (NULL, "or", "d,v,t", treg, treg, AT); | |
252b5132 RH |
8093 | break; |
8094 | ||
8095 | case M_USH: | |
8fc2e39e | 8096 | used_at = 1; |
252b5132 | 8097 | if (offset_expr.X_add_number >= 0x7fff) |
f71d0d44 | 8098 | as_bad (_("Operand overflow")); |
252b5132 | 8099 | if (target_big_endian) |
f9419b05 | 8100 | ++offset_expr.X_add_number; |
67c0d1eb RS |
8101 | macro_build (&offset_expr, "sb", "t,o(b)", treg, BFD_RELOC_LO16, breg); |
8102 | macro_build (NULL, "srl", "d,w,<", AT, treg, 8); | |
252b5132 | 8103 | if (target_big_endian) |
f9419b05 | 8104 | --offset_expr.X_add_number; |
252b5132 | 8105 | else |
f9419b05 | 8106 | ++offset_expr.X_add_number; |
67c0d1eb | 8107 | macro_build (&offset_expr, "sb", "t,o(b)", AT, BFD_RELOC_LO16, breg); |
252b5132 RH |
8108 | break; |
8109 | ||
8110 | case M_USD: | |
8111 | s = "sdl"; | |
8112 | s2 = "sdr"; | |
8113 | off = 7; | |
8114 | goto usw; | |
8115 | case M_USW: | |
8116 | s = "swl"; | |
8117 | s2 = "swr"; | |
8118 | off = 3; | |
8119 | usw: | |
8120 | if (offset_expr.X_add_number >= 0x8000 - off) | |
f71d0d44 | 8121 | as_bad (_("Operand overflow")); |
90ecf173 | 8122 | if (!target_big_endian) |
252b5132 | 8123 | offset_expr.X_add_number += off; |
67c0d1eb | 8124 | macro_build (&offset_expr, s, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
90ecf173 | 8125 | if (!target_big_endian) |
252b5132 RH |
8126 | offset_expr.X_add_number -= off; |
8127 | else | |
8128 | offset_expr.X_add_number += off; | |
67c0d1eb | 8129 | macro_build (&offset_expr, s2, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
8fc2e39e | 8130 | break; |
252b5132 RH |
8131 | |
8132 | case M_USD_A: | |
8133 | s = "sdl"; | |
8134 | s2 = "sdr"; | |
8135 | off = 7; | |
8136 | goto uswa; | |
8137 | case M_USW_A: | |
8138 | s = "swl"; | |
8139 | s2 = "swr"; | |
8140 | off = 3; | |
8141 | uswa: | |
d6bc6245 | 8142 | used_at = 1; |
67c0d1eb | 8143 | load_address (AT, &offset_expr, &used_at); |
252b5132 | 8144 | if (breg != 0) |
67c0d1eb | 8145 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); |
90ecf173 | 8146 | if (!target_big_endian) |
252b5132 RH |
8147 | expr1.X_add_number = off; |
8148 | else | |
8149 | expr1.X_add_number = 0; | |
67c0d1eb | 8150 | macro_build (&expr1, s, "t,o(b)", treg, BFD_RELOC_LO16, AT); |
90ecf173 | 8151 | if (!target_big_endian) |
252b5132 RH |
8152 | expr1.X_add_number = 0; |
8153 | else | |
8154 | expr1.X_add_number = off; | |
67c0d1eb | 8155 | macro_build (&expr1, s2, "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
8156 | break; |
8157 | ||
8158 | case M_USH_A: | |
d6bc6245 | 8159 | used_at = 1; |
67c0d1eb | 8160 | load_address (AT, &offset_expr, &used_at); |
252b5132 | 8161 | if (breg != 0) |
67c0d1eb | 8162 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); |
90ecf173 | 8163 | if (!target_big_endian) |
252b5132 | 8164 | expr1.X_add_number = 0; |
67c0d1eb RS |
8165 | macro_build (&expr1, "sb", "t,o(b)", treg, BFD_RELOC_LO16, AT); |
8166 | macro_build (NULL, "srl", "d,w,<", treg, treg, 8); | |
90ecf173 | 8167 | if (!target_big_endian) |
252b5132 RH |
8168 | expr1.X_add_number = 1; |
8169 | else | |
8170 | expr1.X_add_number = 0; | |
67c0d1eb | 8171 | macro_build (&expr1, "sb", "t,o(b)", treg, BFD_RELOC_LO16, AT); |
90ecf173 | 8172 | if (!target_big_endian) |
252b5132 RH |
8173 | expr1.X_add_number = 0; |
8174 | else | |
8175 | expr1.X_add_number = 1; | |
67c0d1eb RS |
8176 | macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT); |
8177 | macro_build (NULL, "sll", "d,w,<", treg, treg, 8); | |
8178 | macro_build (NULL, "or", "d,v,t", treg, treg, AT); | |
252b5132 RH |
8179 | break; |
8180 | ||
8181 | default: | |
8182 | /* FIXME: Check if this is one of the itbl macros, since they | |
bdaaa2e1 | 8183 | are added dynamically. */ |
252b5132 RH |
8184 | as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name); |
8185 | break; | |
8186 | } | |
741fe287 | 8187 | if (!mips_opts.at && used_at) |
8fc2e39e | 8188 | as_bad (_("Macro used $at after \".set noat\"")); |
252b5132 RH |
8189 | } |
8190 | ||
8191 | /* Implement macros in mips16 mode. */ | |
8192 | ||
8193 | static void | |
17a2f251 | 8194 | mips16_macro (struct mips_cl_insn *ip) |
252b5132 RH |
8195 | { |
8196 | int mask; | |
8197 | int xreg, yreg, zreg, tmp; | |
252b5132 RH |
8198 | expressionS expr1; |
8199 | int dbl; | |
8200 | const char *s, *s2, *s3; | |
8201 | ||
8202 | mask = ip->insn_mo->mask; | |
8203 | ||
bf12938e RS |
8204 | xreg = MIPS16_EXTRACT_OPERAND (RX, *ip); |
8205 | yreg = MIPS16_EXTRACT_OPERAND (RY, *ip); | |
8206 | zreg = MIPS16_EXTRACT_OPERAND (RZ, *ip); | |
252b5132 | 8207 | |
252b5132 RH |
8208 | expr1.X_op = O_constant; |
8209 | expr1.X_op_symbol = NULL; | |
8210 | expr1.X_add_symbol = NULL; | |
8211 | expr1.X_add_number = 1; | |
8212 | ||
8213 | dbl = 0; | |
8214 | ||
8215 | switch (mask) | |
8216 | { | |
8217 | default: | |
8218 | internalError (); | |
8219 | ||
8220 | case M_DDIV_3: | |
8221 | dbl = 1; | |
8222 | case M_DIV_3: | |
8223 | s = "mflo"; | |
8224 | goto do_div3; | |
8225 | case M_DREM_3: | |
8226 | dbl = 1; | |
8227 | case M_REM_3: | |
8228 | s = "mfhi"; | |
8229 | do_div3: | |
7d10b47d | 8230 | start_noreorder (); |
67c0d1eb | 8231 | macro_build (NULL, dbl ? "ddiv" : "div", "0,x,y", xreg, yreg); |
252b5132 | 8232 | expr1.X_add_number = 2; |
67c0d1eb RS |
8233 | macro_build (&expr1, "bnez", "x,p", yreg); |
8234 | macro_build (NULL, "break", "6", 7); | |
bdaaa2e1 | 8235 | |
252b5132 RH |
8236 | /* FIXME: The normal code checks for of -1 / -0x80000000 here, |
8237 | since that causes an overflow. We should do that as well, | |
8238 | but I don't see how to do the comparisons without a temporary | |
8239 | register. */ | |
7d10b47d | 8240 | end_noreorder (); |
67c0d1eb | 8241 | macro_build (NULL, s, "x", zreg); |
252b5132 RH |
8242 | break; |
8243 | ||
8244 | case M_DIVU_3: | |
8245 | s = "divu"; | |
8246 | s2 = "mflo"; | |
8247 | goto do_divu3; | |
8248 | case M_REMU_3: | |
8249 | s = "divu"; | |
8250 | s2 = "mfhi"; | |
8251 | goto do_divu3; | |
8252 | case M_DDIVU_3: | |
8253 | s = "ddivu"; | |
8254 | s2 = "mflo"; | |
8255 | goto do_divu3; | |
8256 | case M_DREMU_3: | |
8257 | s = "ddivu"; | |
8258 | s2 = "mfhi"; | |
8259 | do_divu3: | |
7d10b47d | 8260 | start_noreorder (); |
67c0d1eb | 8261 | macro_build (NULL, s, "0,x,y", xreg, yreg); |
252b5132 | 8262 | expr1.X_add_number = 2; |
67c0d1eb RS |
8263 | macro_build (&expr1, "bnez", "x,p", yreg); |
8264 | macro_build (NULL, "break", "6", 7); | |
7d10b47d | 8265 | end_noreorder (); |
67c0d1eb | 8266 | macro_build (NULL, s2, "x", zreg); |
252b5132 RH |
8267 | break; |
8268 | ||
8269 | case M_DMUL: | |
8270 | dbl = 1; | |
8271 | case M_MUL: | |
67c0d1eb RS |
8272 | macro_build (NULL, dbl ? "dmultu" : "multu", "x,y", xreg, yreg); |
8273 | macro_build (NULL, "mflo", "x", zreg); | |
8fc2e39e | 8274 | break; |
252b5132 RH |
8275 | |
8276 | case M_DSUBU_I: | |
8277 | dbl = 1; | |
8278 | goto do_subu; | |
8279 | case M_SUBU_I: | |
8280 | do_subu: | |
8281 | if (imm_expr.X_op != O_constant) | |
8282 | as_bad (_("Unsupported large constant")); | |
8283 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 8284 | macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "y,x,4", yreg, xreg); |
252b5132 RH |
8285 | break; |
8286 | ||
8287 | case M_SUBU_I_2: | |
8288 | if (imm_expr.X_op != O_constant) | |
8289 | as_bad (_("Unsupported large constant")); | |
8290 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 8291 | macro_build (&imm_expr, "addiu", "x,k", xreg); |
252b5132 RH |
8292 | break; |
8293 | ||
8294 | case M_DSUBU_I_2: | |
8295 | if (imm_expr.X_op != O_constant) | |
8296 | as_bad (_("Unsupported large constant")); | |
8297 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 8298 | macro_build (&imm_expr, "daddiu", "y,j", yreg); |
252b5132 RH |
8299 | break; |
8300 | ||
8301 | case M_BEQ: | |
8302 | s = "cmp"; | |
8303 | s2 = "bteqz"; | |
8304 | goto do_branch; | |
8305 | case M_BNE: | |
8306 | s = "cmp"; | |
8307 | s2 = "btnez"; | |
8308 | goto do_branch; | |
8309 | case M_BLT: | |
8310 | s = "slt"; | |
8311 | s2 = "btnez"; | |
8312 | goto do_branch; | |
8313 | case M_BLTU: | |
8314 | s = "sltu"; | |
8315 | s2 = "btnez"; | |
8316 | goto do_branch; | |
8317 | case M_BLE: | |
8318 | s = "slt"; | |
8319 | s2 = "bteqz"; | |
8320 | goto do_reverse_branch; | |
8321 | case M_BLEU: | |
8322 | s = "sltu"; | |
8323 | s2 = "bteqz"; | |
8324 | goto do_reverse_branch; | |
8325 | case M_BGE: | |
8326 | s = "slt"; | |
8327 | s2 = "bteqz"; | |
8328 | goto do_branch; | |
8329 | case M_BGEU: | |
8330 | s = "sltu"; | |
8331 | s2 = "bteqz"; | |
8332 | goto do_branch; | |
8333 | case M_BGT: | |
8334 | s = "slt"; | |
8335 | s2 = "btnez"; | |
8336 | goto do_reverse_branch; | |
8337 | case M_BGTU: | |
8338 | s = "sltu"; | |
8339 | s2 = "btnez"; | |
8340 | ||
8341 | do_reverse_branch: | |
8342 | tmp = xreg; | |
8343 | xreg = yreg; | |
8344 | yreg = tmp; | |
8345 | ||
8346 | do_branch: | |
67c0d1eb RS |
8347 | macro_build (NULL, s, "x,y", xreg, yreg); |
8348 | macro_build (&offset_expr, s2, "p"); | |
252b5132 RH |
8349 | break; |
8350 | ||
8351 | case M_BEQ_I: | |
8352 | s = "cmpi"; | |
8353 | s2 = "bteqz"; | |
8354 | s3 = "x,U"; | |
8355 | goto do_branch_i; | |
8356 | case M_BNE_I: | |
8357 | s = "cmpi"; | |
8358 | s2 = "btnez"; | |
8359 | s3 = "x,U"; | |
8360 | goto do_branch_i; | |
8361 | case M_BLT_I: | |
8362 | s = "slti"; | |
8363 | s2 = "btnez"; | |
8364 | s3 = "x,8"; | |
8365 | goto do_branch_i; | |
8366 | case M_BLTU_I: | |
8367 | s = "sltiu"; | |
8368 | s2 = "btnez"; | |
8369 | s3 = "x,8"; | |
8370 | goto do_branch_i; | |
8371 | case M_BLE_I: | |
8372 | s = "slti"; | |
8373 | s2 = "btnez"; | |
8374 | s3 = "x,8"; | |
8375 | goto do_addone_branch_i; | |
8376 | case M_BLEU_I: | |
8377 | s = "sltiu"; | |
8378 | s2 = "btnez"; | |
8379 | s3 = "x,8"; | |
8380 | goto do_addone_branch_i; | |
8381 | case M_BGE_I: | |
8382 | s = "slti"; | |
8383 | s2 = "bteqz"; | |
8384 | s3 = "x,8"; | |
8385 | goto do_branch_i; | |
8386 | case M_BGEU_I: | |
8387 | s = "sltiu"; | |
8388 | s2 = "bteqz"; | |
8389 | s3 = "x,8"; | |
8390 | goto do_branch_i; | |
8391 | case M_BGT_I: | |
8392 | s = "slti"; | |
8393 | s2 = "bteqz"; | |
8394 | s3 = "x,8"; | |
8395 | goto do_addone_branch_i; | |
8396 | case M_BGTU_I: | |
8397 | s = "sltiu"; | |
8398 | s2 = "bteqz"; | |
8399 | s3 = "x,8"; | |
8400 | ||
8401 | do_addone_branch_i: | |
8402 | if (imm_expr.X_op != O_constant) | |
8403 | as_bad (_("Unsupported large constant")); | |
8404 | ++imm_expr.X_add_number; | |
8405 | ||
8406 | do_branch_i: | |
67c0d1eb RS |
8407 | macro_build (&imm_expr, s, s3, xreg); |
8408 | macro_build (&offset_expr, s2, "p"); | |
252b5132 RH |
8409 | break; |
8410 | ||
8411 | case M_ABS: | |
8412 | expr1.X_add_number = 0; | |
67c0d1eb | 8413 | macro_build (&expr1, "slti", "x,8", yreg); |
252b5132 | 8414 | if (xreg != yreg) |
67c0d1eb | 8415 | move_register (xreg, yreg); |
252b5132 | 8416 | expr1.X_add_number = 2; |
67c0d1eb RS |
8417 | macro_build (&expr1, "bteqz", "p"); |
8418 | macro_build (NULL, "neg", "x,w", xreg, xreg); | |
252b5132 RH |
8419 | } |
8420 | } | |
8421 | ||
8422 | /* For consistency checking, verify that all bits are specified either | |
8423 | by the match/mask part of the instruction definition, or by the | |
8424 | operand list. */ | |
8425 | static int | |
17a2f251 | 8426 | validate_mips_insn (const struct mips_opcode *opc) |
252b5132 RH |
8427 | { |
8428 | const char *p = opc->args; | |
8429 | char c; | |
8430 | unsigned long used_bits = opc->mask; | |
8431 | ||
8432 | if ((used_bits & opc->match) != opc->match) | |
8433 | { | |
8434 | as_bad (_("internal: bad mips opcode (mask error): %s %s"), | |
8435 | opc->name, opc->args); | |
8436 | return 0; | |
8437 | } | |
8438 | #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift))) | |
8439 | while (*p) | |
8440 | switch (c = *p++) | |
8441 | { | |
8442 | case ',': break; | |
8443 | case '(': break; | |
8444 | case ')': break; | |
af7ee8bf CD |
8445 | case '+': |
8446 | switch (c = *p++) | |
8447 | { | |
9bcd4f99 TS |
8448 | case '1': USE_BITS (OP_MASK_UDI1, OP_SH_UDI1); break; |
8449 | case '2': USE_BITS (OP_MASK_UDI2, OP_SH_UDI2); break; | |
8450 | case '3': USE_BITS (OP_MASK_UDI3, OP_SH_UDI3); break; | |
8451 | case '4': USE_BITS (OP_MASK_UDI4, OP_SH_UDI4); break; | |
af7ee8bf CD |
8452 | case 'A': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
8453 | case 'B': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break; | |
8454 | case 'C': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
bbcc0807 CD |
8455 | case 'D': USE_BITS (OP_MASK_RD, OP_SH_RD); |
8456 | USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; | |
5f74bc13 CD |
8457 | case 'E': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
8458 | case 'F': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break; | |
8459 | case 'G': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
8460 | case 'H': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
8461 | case 'I': break; | |
ef2e4d86 CF |
8462 | case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break; |
8463 | case 'T': USE_BITS (OP_MASK_RT, OP_SH_RT); | |
8464 | USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; | |
bb35fb24 NC |
8465 | case 'x': USE_BITS (OP_MASK_BBITIND, OP_SH_BBITIND); break; |
8466 | case 'X': USE_BITS (OP_MASK_BBITIND, OP_SH_BBITIND); break; | |
8467 | case 'p': USE_BITS (OP_MASK_CINSPOS, OP_SH_CINSPOS); break; | |
8468 | case 'P': USE_BITS (OP_MASK_CINSPOS, OP_SH_CINSPOS); break; | |
dd3cbb7e | 8469 | case 'Q': USE_BITS (OP_MASK_SEQI, OP_SH_SEQI); break; |
bb35fb24 NC |
8470 | case 's': USE_BITS (OP_MASK_CINSLM1, OP_SH_CINSLM1); break; |
8471 | case 'S': USE_BITS (OP_MASK_CINSLM1, OP_SH_CINSLM1); break; | |
8472 | ||
af7ee8bf CD |
8473 | default: |
8474 | as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"), | |
8475 | c, opc->name, opc->args); | |
8476 | return 0; | |
8477 | } | |
8478 | break; | |
252b5132 RH |
8479 | case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
8480 | case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; | |
8481 | case 'A': break; | |
4372b673 | 8482 | case 'B': USE_BITS (OP_MASK_CODE20, OP_SH_CODE20); break; |
252b5132 RH |
8483 | case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break; |
8484 | case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break; | |
8485 | case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
8486 | case 'F': break; | |
8487 | case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
156c2f8b | 8488 | case 'H': USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; |
252b5132 | 8489 | case 'I': break; |
e972090a | 8490 | case 'J': USE_BITS (OP_MASK_CODE19, OP_SH_CODE19); break; |
af7ee8bf | 8491 | case 'K': USE_BITS (OP_MASK_RD, OP_SH_RD); break; |
252b5132 RH |
8492 | case 'L': break; |
8493 | case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break; | |
8494 | case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break; | |
deec1734 CD |
8495 | case 'O': USE_BITS (OP_MASK_ALN, OP_SH_ALN); break; |
8496 | case 'Q': USE_BITS (OP_MASK_VSEL, OP_SH_VSEL); | |
8497 | USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
252b5132 RH |
8498 | case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break; |
8499 | case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
8500 | case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
8501 | case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
8502 | case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
deec1734 CD |
8503 | case 'X': USE_BITS (OP_MASK_FD, OP_SH_FD); break; |
8504 | case 'Y': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
8505 | case 'Z': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
252b5132 RH |
8506 | case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break; |
8507 | case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
8508 | case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break; | |
8509 | case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
8510 | case 'f': break; | |
8511 | case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break; | |
8512 | case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; | |
8513 | case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
8514 | case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break; | |
8515 | case 'l': break; | |
8516 | case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
8517 | case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
8518 | case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break; | |
8519 | case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
8520 | case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
8521 | case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
8522 | case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; | |
8523 | case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
8524 | case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
8525 | case 'x': break; | |
8526 | case 'z': break; | |
8527 | case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break; | |
4372b673 NC |
8528 | case 'U': USE_BITS (OP_MASK_RD, OP_SH_RD); |
8529 | USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
60b63b72 RS |
8530 | case 'e': USE_BITS (OP_MASK_VECBYTE, OP_SH_VECBYTE); break; |
8531 | case '%': USE_BITS (OP_MASK_VECALIGN, OP_SH_VECALIGN); break; | |
8532 | case '[': break; | |
8533 | case ']': break; | |
620edafd | 8534 | case '1': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
8b082fb1 | 8535 | case '2': USE_BITS (OP_MASK_BP, OP_SH_BP); break; |
74cd071d CF |
8536 | case '3': USE_BITS (OP_MASK_SA3, OP_SH_SA3); break; |
8537 | case '4': USE_BITS (OP_MASK_SA4, OP_SH_SA4); break; | |
8538 | case '5': USE_BITS (OP_MASK_IMM8, OP_SH_IMM8); break; | |
8539 | case '6': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
8540 | case '7': USE_BITS (OP_MASK_DSPACC, OP_SH_DSPACC); break; | |
8541 | case '8': USE_BITS (OP_MASK_WRDSP, OP_SH_WRDSP); break; | |
8542 | case '9': USE_BITS (OP_MASK_DSPACC_S, OP_SH_DSPACC_S);break; | |
8543 | case '0': USE_BITS (OP_MASK_DSPSFT, OP_SH_DSPSFT); break; | |
8544 | case '\'': USE_BITS (OP_MASK_RDDSP, OP_SH_RDDSP); break; | |
8545 | case ':': USE_BITS (OP_MASK_DSPSFT_7, OP_SH_DSPSFT_7);break; | |
8546 | case '@': USE_BITS (OP_MASK_IMM10, OP_SH_IMM10); break; | |
ef2e4d86 CF |
8547 | case '!': USE_BITS (OP_MASK_MT_U, OP_SH_MT_U); break; |
8548 | case '$': USE_BITS (OP_MASK_MT_H, OP_SH_MT_H); break; | |
8549 | case '*': USE_BITS (OP_MASK_MTACC_T, OP_SH_MTACC_T); break; | |
8550 | case '&': USE_BITS (OP_MASK_MTACC_D, OP_SH_MTACC_D); break; | |
8551 | case 'g': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
252b5132 RH |
8552 | default: |
8553 | as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"), | |
8554 | c, opc->name, opc->args); | |
8555 | return 0; | |
8556 | } | |
8557 | #undef USE_BITS | |
8558 | if (used_bits != 0xffffffff) | |
8559 | { | |
8560 | as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"), | |
8561 | ~used_bits & 0xffffffff, opc->name, opc->args); | |
8562 | return 0; | |
8563 | } | |
8564 | return 1; | |
8565 | } | |
8566 | ||
9bcd4f99 TS |
8567 | /* UDI immediates. */ |
8568 | struct mips_immed { | |
8569 | char type; | |
8570 | unsigned int shift; | |
8571 | unsigned long mask; | |
8572 | const char * desc; | |
8573 | }; | |
8574 | ||
8575 | static const struct mips_immed mips_immed[] = { | |
8576 | { '1', OP_SH_UDI1, OP_MASK_UDI1, 0}, | |
8577 | { '2', OP_SH_UDI2, OP_MASK_UDI2, 0}, | |
8578 | { '3', OP_SH_UDI3, OP_MASK_UDI3, 0}, | |
8579 | { '4', OP_SH_UDI4, OP_MASK_UDI4, 0}, | |
8580 | { 0,0,0,0 } | |
8581 | }; | |
8582 | ||
7455baf8 TS |
8583 | /* Check whether an odd floating-point register is allowed. */ |
8584 | static int | |
8585 | mips_oddfpreg_ok (const struct mips_opcode *insn, int argnum) | |
8586 | { | |
8587 | const char *s = insn->name; | |
8588 | ||
8589 | if (insn->pinfo == INSN_MACRO) | |
8590 | /* Let a macro pass, we'll catch it later when it is expanded. */ | |
8591 | return 1; | |
8592 | ||
8593 | if (ISA_HAS_ODD_SINGLE_FPR (mips_opts.isa)) | |
8594 | { | |
8595 | /* Allow odd registers for single-precision ops. */ | |
8596 | switch (insn->pinfo & (FP_S | FP_D)) | |
8597 | { | |
8598 | case FP_S: | |
8599 | case 0: | |
8600 | return 1; /* both single precision - ok */ | |
8601 | case FP_D: | |
8602 | return 0; /* both double precision - fail */ | |
8603 | default: | |
8604 | break; | |
8605 | } | |
8606 | ||
8607 | /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */ | |
8608 | s = strchr (insn->name, '.'); | |
8609 | if (argnum == 2) | |
8610 | s = s != NULL ? strchr (s + 1, '.') : NULL; | |
8611 | return (s != NULL && (s[1] == 'w' || s[1] == 's')); | |
8612 | } | |
8613 | ||
8614 | /* Single-precision coprocessor loads and moves are OK too. */ | |
8615 | if ((insn->pinfo & FP_S) | |
8616 | && (insn->pinfo & (INSN_COPROC_MEMORY_DELAY | INSN_STORE_MEMORY | |
8617 | | INSN_LOAD_COPROC_DELAY | INSN_COPROC_MOVE_DELAY))) | |
8618 | return 1; | |
8619 | ||
8620 | return 0; | |
8621 | } | |
8622 | ||
252b5132 RH |
8623 | /* This routine assembles an instruction into its binary format. As a |
8624 | side effect, it sets one of the global variables imm_reloc or | |
8625 | offset_reloc to the type of relocation to do if one of the operands | |
8626 | is an address expression. */ | |
8627 | ||
8628 | static void | |
17a2f251 | 8629 | mips_ip (char *str, struct mips_cl_insn *ip) |
252b5132 RH |
8630 | { |
8631 | char *s; | |
8632 | const char *args; | |
43841e91 | 8633 | char c = 0; |
252b5132 RH |
8634 | struct mips_opcode *insn; |
8635 | char *argsStart; | |
8636 | unsigned int regno; | |
34224acf | 8637 | unsigned int lastregno; |
af7ee8bf | 8638 | unsigned int lastpos = 0; |
071742cf | 8639 | unsigned int limlo, limhi; |
252b5132 RH |
8640 | char *s_reset; |
8641 | char save_c = 0; | |
74cd071d | 8642 | offsetT min_range, max_range; |
707bfff6 TS |
8643 | int argnum; |
8644 | unsigned int rtype; | |
252b5132 RH |
8645 | |
8646 | insn_error = NULL; | |
8647 | ||
8648 | /* If the instruction contains a '.', we first try to match an instruction | |
8649 | including the '.'. Then we try again without the '.'. */ | |
8650 | insn = NULL; | |
3882b010 | 8651 | for (s = str; *s != '\0' && !ISSPACE (*s); ++s) |
252b5132 RH |
8652 | continue; |
8653 | ||
8654 | /* If we stopped on whitespace, then replace the whitespace with null for | |
8655 | the call to hash_find. Save the character we replaced just in case we | |
8656 | have to re-parse the instruction. */ | |
3882b010 | 8657 | if (ISSPACE (*s)) |
252b5132 RH |
8658 | { |
8659 | save_c = *s; | |
8660 | *s++ = '\0'; | |
8661 | } | |
bdaaa2e1 | 8662 | |
252b5132 RH |
8663 | insn = (struct mips_opcode *) hash_find (op_hash, str); |
8664 | ||
8665 | /* If we didn't find the instruction in the opcode table, try again, but | |
8666 | this time with just the instruction up to, but not including the | |
8667 | first '.'. */ | |
8668 | if (insn == NULL) | |
8669 | { | |
bdaaa2e1 | 8670 | /* Restore the character we overwrite above (if any). */ |
252b5132 RH |
8671 | if (save_c) |
8672 | *(--s) = save_c; | |
8673 | ||
8674 | /* Scan up to the first '.' or whitespace. */ | |
3882b010 L |
8675 | for (s = str; |
8676 | *s != '\0' && *s != '.' && !ISSPACE (*s); | |
8677 | ++s) | |
252b5132 RH |
8678 | continue; |
8679 | ||
8680 | /* If we did not find a '.', then we can quit now. */ | |
8681 | if (*s != '.') | |
8682 | { | |
f71d0d44 | 8683 | insn_error = _("Unrecognized opcode"); |
252b5132 RH |
8684 | return; |
8685 | } | |
8686 | ||
8687 | /* Lookup the instruction in the hash table. */ | |
8688 | *s++ = '\0'; | |
8689 | if ((insn = (struct mips_opcode *) hash_find (op_hash, str)) == NULL) | |
8690 | { | |
f71d0d44 | 8691 | insn_error = _("Unrecognized opcode"); |
252b5132 RH |
8692 | return; |
8693 | } | |
252b5132 RH |
8694 | } |
8695 | ||
8696 | argsStart = s; | |
8697 | for (;;) | |
8698 | { | |
b34976b6 | 8699 | bfd_boolean ok; |
252b5132 | 8700 | |
9c2799c2 | 8701 | gas_assert (strcmp (insn->name, str) == 0); |
252b5132 | 8702 | |
f79e2745 | 8703 | ok = is_opcode_valid (insn); |
252b5132 RH |
8704 | if (! ok) |
8705 | { | |
8706 | if (insn + 1 < &mips_opcodes[NUMOPCODES] | |
8707 | && strcmp (insn->name, insn[1].name) == 0) | |
8708 | { | |
8709 | ++insn; | |
8710 | continue; | |
8711 | } | |
252b5132 | 8712 | else |
beae10d5 | 8713 | { |
268f6bed L |
8714 | if (!insn_error) |
8715 | { | |
8716 | static char buf[100]; | |
fef14a42 TS |
8717 | sprintf (buf, |
8718 | _("opcode not supported on this processor: %s (%s)"), | |
8719 | mips_cpu_info_from_arch (mips_opts.arch)->name, | |
8720 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
268f6bed L |
8721 | insn_error = buf; |
8722 | } | |
8723 | if (save_c) | |
8724 | *(--s) = save_c; | |
2bd7f1f3 | 8725 | return; |
252b5132 | 8726 | } |
252b5132 RH |
8727 | } |
8728 | ||
1e915849 | 8729 | create_insn (ip, insn); |
268f6bed | 8730 | insn_error = NULL; |
707bfff6 | 8731 | argnum = 1; |
24864476 | 8732 | lastregno = 0xffffffff; |
252b5132 RH |
8733 | for (args = insn->args;; ++args) |
8734 | { | |
deec1734 CD |
8735 | int is_mdmx; |
8736 | ||
ad8d3bb3 | 8737 | s += strspn (s, " \t"); |
deec1734 | 8738 | is_mdmx = 0; |
252b5132 RH |
8739 | switch (*args) |
8740 | { | |
8741 | case '\0': /* end of args */ | |
8742 | if (*s == '\0') | |
8743 | return; | |
8744 | break; | |
8745 | ||
90ecf173 | 8746 | case '2': /* DSP 2-bit unsigned immediate in bit 11. */ |
8b082fb1 TS |
8747 | my_getExpression (&imm_expr, s); |
8748 | check_absolute_expr (ip, &imm_expr); | |
8749 | if ((unsigned long) imm_expr.X_add_number != 1 | |
8750 | && (unsigned long) imm_expr.X_add_number != 3) | |
8751 | { | |
8752 | as_bad (_("BALIGN immediate not 1 or 3 (%lu)"), | |
8753 | (unsigned long) imm_expr.X_add_number); | |
8754 | } | |
8755 | INSERT_OPERAND (BP, *ip, imm_expr.X_add_number); | |
8756 | imm_expr.X_op = O_absent; | |
8757 | s = expr_end; | |
8758 | continue; | |
8759 | ||
90ecf173 | 8760 | case '3': /* DSP 3-bit unsigned immediate in bit 21. */ |
74cd071d CF |
8761 | my_getExpression (&imm_expr, s); |
8762 | check_absolute_expr (ip, &imm_expr); | |
8763 | if (imm_expr.X_add_number & ~OP_MASK_SA3) | |
8764 | { | |
a9e24354 TS |
8765 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), |
8766 | OP_MASK_SA3, (unsigned long) imm_expr.X_add_number); | |
74cd071d | 8767 | } |
a9e24354 | 8768 | INSERT_OPERAND (SA3, *ip, imm_expr.X_add_number); |
74cd071d CF |
8769 | imm_expr.X_op = O_absent; |
8770 | s = expr_end; | |
8771 | continue; | |
8772 | ||
90ecf173 | 8773 | case '4': /* DSP 4-bit unsigned immediate in bit 21. */ |
74cd071d CF |
8774 | my_getExpression (&imm_expr, s); |
8775 | check_absolute_expr (ip, &imm_expr); | |
8776 | if (imm_expr.X_add_number & ~OP_MASK_SA4) | |
8777 | { | |
a9e24354 TS |
8778 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), |
8779 | OP_MASK_SA4, (unsigned long) imm_expr.X_add_number); | |
74cd071d | 8780 | } |
a9e24354 | 8781 | INSERT_OPERAND (SA4, *ip, imm_expr.X_add_number); |
74cd071d CF |
8782 | imm_expr.X_op = O_absent; |
8783 | s = expr_end; | |
8784 | continue; | |
8785 | ||
90ecf173 | 8786 | case '5': /* DSP 8-bit unsigned immediate in bit 16. */ |
74cd071d CF |
8787 | my_getExpression (&imm_expr, s); |
8788 | check_absolute_expr (ip, &imm_expr); | |
8789 | if (imm_expr.X_add_number & ~OP_MASK_IMM8) | |
8790 | { | |
a9e24354 TS |
8791 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), |
8792 | OP_MASK_IMM8, (unsigned long) imm_expr.X_add_number); | |
74cd071d | 8793 | } |
a9e24354 | 8794 | INSERT_OPERAND (IMM8, *ip, imm_expr.X_add_number); |
74cd071d CF |
8795 | imm_expr.X_op = O_absent; |
8796 | s = expr_end; | |
8797 | continue; | |
8798 | ||
90ecf173 | 8799 | case '6': /* DSP 5-bit unsigned immediate in bit 21. */ |
74cd071d CF |
8800 | my_getExpression (&imm_expr, s); |
8801 | check_absolute_expr (ip, &imm_expr); | |
8802 | if (imm_expr.X_add_number & ~OP_MASK_RS) | |
8803 | { | |
a9e24354 TS |
8804 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), |
8805 | OP_MASK_RS, (unsigned long) imm_expr.X_add_number); | |
74cd071d | 8806 | } |
a9e24354 | 8807 | INSERT_OPERAND (RS, *ip, imm_expr.X_add_number); |
74cd071d CF |
8808 | imm_expr.X_op = O_absent; |
8809 | s = expr_end; | |
8810 | continue; | |
8811 | ||
90ecf173 | 8812 | case '7': /* Four DSP accumulators in bits 11,12. */ |
74cd071d CF |
8813 | if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' && |
8814 | s[3] >= '0' && s[3] <= '3') | |
8815 | { | |
8816 | regno = s[3] - '0'; | |
8817 | s += 4; | |
a9e24354 | 8818 | INSERT_OPERAND (DSPACC, *ip, regno); |
74cd071d CF |
8819 | continue; |
8820 | } | |
8821 | else | |
8822 | as_bad (_("Invalid dsp acc register")); | |
8823 | break; | |
8824 | ||
90ecf173 | 8825 | case '8': /* DSP 6-bit unsigned immediate in bit 11. */ |
74cd071d CF |
8826 | my_getExpression (&imm_expr, s); |
8827 | check_absolute_expr (ip, &imm_expr); | |
8828 | if (imm_expr.X_add_number & ~OP_MASK_WRDSP) | |
8829 | { | |
a9e24354 TS |
8830 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), |
8831 | OP_MASK_WRDSP, | |
8832 | (unsigned long) imm_expr.X_add_number); | |
74cd071d | 8833 | } |
a9e24354 | 8834 | INSERT_OPERAND (WRDSP, *ip, imm_expr.X_add_number); |
74cd071d CF |
8835 | imm_expr.X_op = O_absent; |
8836 | s = expr_end; | |
8837 | continue; | |
8838 | ||
90ecf173 | 8839 | case '9': /* Four DSP accumulators in bits 21,22. */ |
74cd071d CF |
8840 | if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' && |
8841 | s[3] >= '0' && s[3] <= '3') | |
8842 | { | |
8843 | regno = s[3] - '0'; | |
8844 | s += 4; | |
a9e24354 | 8845 | INSERT_OPERAND (DSPACC_S, *ip, regno); |
74cd071d CF |
8846 | continue; |
8847 | } | |
8848 | else | |
8849 | as_bad (_("Invalid dsp acc register")); | |
8850 | break; | |
8851 | ||
90ecf173 | 8852 | case '0': /* DSP 6-bit signed immediate in bit 20. */ |
74cd071d CF |
8853 | my_getExpression (&imm_expr, s); |
8854 | check_absolute_expr (ip, &imm_expr); | |
8855 | min_range = -((OP_MASK_DSPSFT + 1) >> 1); | |
8856 | max_range = ((OP_MASK_DSPSFT + 1) >> 1) - 1; | |
8857 | if (imm_expr.X_add_number < min_range || | |
8858 | imm_expr.X_add_number > max_range) | |
8859 | { | |
a9e24354 TS |
8860 | as_bad (_("DSP immediate not in range %ld..%ld (%ld)"), |
8861 | (long) min_range, (long) max_range, | |
8862 | (long) imm_expr.X_add_number); | |
74cd071d | 8863 | } |
a9e24354 | 8864 | INSERT_OPERAND (DSPSFT, *ip, imm_expr.X_add_number); |
74cd071d CF |
8865 | imm_expr.X_op = O_absent; |
8866 | s = expr_end; | |
8867 | continue; | |
8868 | ||
90ecf173 | 8869 | case '\'': /* DSP 6-bit unsigned immediate in bit 16. */ |
74cd071d CF |
8870 | my_getExpression (&imm_expr, s); |
8871 | check_absolute_expr (ip, &imm_expr); | |
8872 | if (imm_expr.X_add_number & ~OP_MASK_RDDSP) | |
8873 | { | |
a9e24354 TS |
8874 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), |
8875 | OP_MASK_RDDSP, | |
8876 | (unsigned long) imm_expr.X_add_number); | |
74cd071d | 8877 | } |
a9e24354 | 8878 | INSERT_OPERAND (RDDSP, *ip, imm_expr.X_add_number); |
74cd071d CF |
8879 | imm_expr.X_op = O_absent; |
8880 | s = expr_end; | |
8881 | continue; | |
8882 | ||
90ecf173 | 8883 | case ':': /* DSP 7-bit signed immediate in bit 19. */ |
74cd071d CF |
8884 | my_getExpression (&imm_expr, s); |
8885 | check_absolute_expr (ip, &imm_expr); | |
8886 | min_range = -((OP_MASK_DSPSFT_7 + 1) >> 1); | |
8887 | max_range = ((OP_MASK_DSPSFT_7 + 1) >> 1) - 1; | |
8888 | if (imm_expr.X_add_number < min_range || | |
8889 | imm_expr.X_add_number > max_range) | |
8890 | { | |
a9e24354 TS |
8891 | as_bad (_("DSP immediate not in range %ld..%ld (%ld)"), |
8892 | (long) min_range, (long) max_range, | |
8893 | (long) imm_expr.X_add_number); | |
74cd071d | 8894 | } |
a9e24354 | 8895 | INSERT_OPERAND (DSPSFT_7, *ip, imm_expr.X_add_number); |
74cd071d CF |
8896 | imm_expr.X_op = O_absent; |
8897 | s = expr_end; | |
8898 | continue; | |
8899 | ||
90ecf173 | 8900 | case '@': /* DSP 10-bit signed immediate in bit 16. */ |
74cd071d CF |
8901 | my_getExpression (&imm_expr, s); |
8902 | check_absolute_expr (ip, &imm_expr); | |
8903 | min_range = -((OP_MASK_IMM10 + 1) >> 1); | |
8904 | max_range = ((OP_MASK_IMM10 + 1) >> 1) - 1; | |
8905 | if (imm_expr.X_add_number < min_range || | |
8906 | imm_expr.X_add_number > max_range) | |
8907 | { | |
a9e24354 TS |
8908 | as_bad (_("DSP immediate not in range %ld..%ld (%ld)"), |
8909 | (long) min_range, (long) max_range, | |
8910 | (long) imm_expr.X_add_number); | |
74cd071d | 8911 | } |
a9e24354 | 8912 | INSERT_OPERAND (IMM10, *ip, imm_expr.X_add_number); |
74cd071d CF |
8913 | imm_expr.X_op = O_absent; |
8914 | s = expr_end; | |
8915 | continue; | |
8916 | ||
a9e24354 | 8917 | case '!': /* MT usermode flag bit. */ |
ef2e4d86 CF |
8918 | my_getExpression (&imm_expr, s); |
8919 | check_absolute_expr (ip, &imm_expr); | |
8920 | if (imm_expr.X_add_number & ~OP_MASK_MT_U) | |
a9e24354 TS |
8921 | as_bad (_("MT usermode bit not 0 or 1 (%lu)"), |
8922 | (unsigned long) imm_expr.X_add_number); | |
8923 | INSERT_OPERAND (MT_U, *ip, imm_expr.X_add_number); | |
ef2e4d86 CF |
8924 | imm_expr.X_op = O_absent; |
8925 | s = expr_end; | |
8926 | continue; | |
8927 | ||
a9e24354 | 8928 | case '$': /* MT load high flag bit. */ |
ef2e4d86 CF |
8929 | my_getExpression (&imm_expr, s); |
8930 | check_absolute_expr (ip, &imm_expr); | |
8931 | if (imm_expr.X_add_number & ~OP_MASK_MT_H) | |
a9e24354 TS |
8932 | as_bad (_("MT load high bit not 0 or 1 (%lu)"), |
8933 | (unsigned long) imm_expr.X_add_number); | |
8934 | INSERT_OPERAND (MT_H, *ip, imm_expr.X_add_number); | |
ef2e4d86 CF |
8935 | imm_expr.X_op = O_absent; |
8936 | s = expr_end; | |
8937 | continue; | |
8938 | ||
90ecf173 | 8939 | case '*': /* Four DSP accumulators in bits 18,19. */ |
ef2e4d86 CF |
8940 | if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' && |
8941 | s[3] >= '0' && s[3] <= '3') | |
8942 | { | |
8943 | regno = s[3] - '0'; | |
8944 | s += 4; | |
a9e24354 | 8945 | INSERT_OPERAND (MTACC_T, *ip, regno); |
ef2e4d86 CF |
8946 | continue; |
8947 | } | |
8948 | else | |
8949 | as_bad (_("Invalid dsp/smartmips acc register")); | |
8950 | break; | |
8951 | ||
90ecf173 | 8952 | case '&': /* Four DSP accumulators in bits 13,14. */ |
ef2e4d86 CF |
8953 | if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' && |
8954 | s[3] >= '0' && s[3] <= '3') | |
8955 | { | |
8956 | regno = s[3] - '0'; | |
8957 | s += 4; | |
a9e24354 | 8958 | INSERT_OPERAND (MTACC_D, *ip, regno); |
ef2e4d86 CF |
8959 | continue; |
8960 | } | |
8961 | else | |
8962 | as_bad (_("Invalid dsp/smartmips acc register")); | |
8963 | break; | |
8964 | ||
252b5132 | 8965 | case ',': |
a339155f | 8966 | ++argnum; |
252b5132 RH |
8967 | if (*s++ == *args) |
8968 | continue; | |
8969 | s--; | |
8970 | switch (*++args) | |
8971 | { | |
8972 | case 'r': | |
8973 | case 'v': | |
bf12938e | 8974 | INSERT_OPERAND (RS, *ip, lastregno); |
252b5132 RH |
8975 | continue; |
8976 | ||
8977 | case 'w': | |
bf12938e | 8978 | INSERT_OPERAND (RT, *ip, lastregno); |
38487616 TS |
8979 | continue; |
8980 | ||
252b5132 | 8981 | case 'W': |
bf12938e | 8982 | INSERT_OPERAND (FT, *ip, lastregno); |
252b5132 RH |
8983 | continue; |
8984 | ||
8985 | case 'V': | |
bf12938e | 8986 | INSERT_OPERAND (FS, *ip, lastregno); |
252b5132 RH |
8987 | continue; |
8988 | } | |
8989 | break; | |
8990 | ||
8991 | case '(': | |
8992 | /* Handle optional base register. | |
8993 | Either the base register is omitted or | |
bdaaa2e1 | 8994 | we must have a left paren. */ |
252b5132 RH |
8995 | /* This is dependent on the next operand specifier |
8996 | is a base register specification. */ | |
f9bbfb18 | 8997 | gas_assert (args[1] == 'b'); |
252b5132 RH |
8998 | if (*s == '\0') |
8999 | return; | |
9000 | ||
90ecf173 | 9001 | case ')': /* These must match exactly. */ |
60b63b72 RS |
9002 | case '[': |
9003 | case ']': | |
252b5132 RH |
9004 | if (*s++ == *args) |
9005 | continue; | |
9006 | break; | |
9007 | ||
af7ee8bf CD |
9008 | case '+': /* Opcode extension character. */ |
9009 | switch (*++args) | |
9010 | { | |
9bcd4f99 TS |
9011 | case '1': /* UDI immediates. */ |
9012 | case '2': | |
9013 | case '3': | |
9014 | case '4': | |
9015 | { | |
9016 | const struct mips_immed *imm = mips_immed; | |
9017 | ||
9018 | while (imm->type && imm->type != *args) | |
9019 | ++imm; | |
9020 | if (! imm->type) | |
9021 | internalError (); | |
9022 | my_getExpression (&imm_expr, s); | |
9023 | check_absolute_expr (ip, &imm_expr); | |
9024 | if ((unsigned long) imm_expr.X_add_number & ~imm->mask) | |
9025 | { | |
9026 | as_warn (_("Illegal %s number (%lu, 0x%lx)"), | |
9027 | imm->desc ? imm->desc : ip->insn_mo->name, | |
9028 | (unsigned long) imm_expr.X_add_number, | |
9029 | (unsigned long) imm_expr.X_add_number); | |
90ecf173 | 9030 | imm_expr.X_add_number &= imm->mask; |
9bcd4f99 TS |
9031 | } |
9032 | ip->insn_opcode |= ((unsigned long) imm_expr.X_add_number | |
9033 | << imm->shift); | |
9034 | imm_expr.X_op = O_absent; | |
9035 | s = expr_end; | |
9036 | } | |
9037 | continue; | |
90ecf173 | 9038 | |
071742cf CD |
9039 | case 'A': /* ins/ext position, becomes LSB. */ |
9040 | limlo = 0; | |
9041 | limhi = 31; | |
5f74bc13 CD |
9042 | goto do_lsb; |
9043 | case 'E': | |
9044 | limlo = 32; | |
9045 | limhi = 63; | |
9046 | goto do_lsb; | |
90ecf173 | 9047 | do_lsb: |
071742cf CD |
9048 | my_getExpression (&imm_expr, s); |
9049 | check_absolute_expr (ip, &imm_expr); | |
9050 | if ((unsigned long) imm_expr.X_add_number < limlo | |
9051 | || (unsigned long) imm_expr.X_add_number > limhi) | |
9052 | { | |
9053 | as_bad (_("Improper position (%lu)"), | |
9054 | (unsigned long) imm_expr.X_add_number); | |
9055 | imm_expr.X_add_number = limlo; | |
9056 | } | |
9057 | lastpos = imm_expr.X_add_number; | |
bf12938e | 9058 | INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number); |
071742cf CD |
9059 | imm_expr.X_op = O_absent; |
9060 | s = expr_end; | |
9061 | continue; | |
9062 | ||
9063 | case 'B': /* ins size, becomes MSB. */ | |
9064 | limlo = 1; | |
9065 | limhi = 32; | |
5f74bc13 CD |
9066 | goto do_msb; |
9067 | case 'F': | |
9068 | limlo = 33; | |
9069 | limhi = 64; | |
9070 | goto do_msb; | |
90ecf173 | 9071 | do_msb: |
071742cf CD |
9072 | my_getExpression (&imm_expr, s); |
9073 | check_absolute_expr (ip, &imm_expr); | |
9074 | /* Check for negative input so that small negative numbers | |
9075 | will not succeed incorrectly. The checks against | |
9076 | (pos+size) transitively check "size" itself, | |
9077 | assuming that "pos" is reasonable. */ | |
9078 | if ((long) imm_expr.X_add_number < 0 | |
9079 | || ((unsigned long) imm_expr.X_add_number | |
9080 | + lastpos) < limlo | |
9081 | || ((unsigned long) imm_expr.X_add_number | |
9082 | + lastpos) > limhi) | |
9083 | { | |
9084 | as_bad (_("Improper insert size (%lu, position %lu)"), | |
9085 | (unsigned long) imm_expr.X_add_number, | |
9086 | (unsigned long) lastpos); | |
9087 | imm_expr.X_add_number = limlo - lastpos; | |
9088 | } | |
bf12938e RS |
9089 | INSERT_OPERAND (INSMSB, *ip, |
9090 | lastpos + imm_expr.X_add_number - 1); | |
071742cf CD |
9091 | imm_expr.X_op = O_absent; |
9092 | s = expr_end; | |
9093 | continue; | |
9094 | ||
9095 | case 'C': /* ext size, becomes MSBD. */ | |
9096 | limlo = 1; | |
9097 | limhi = 32; | |
5f74bc13 CD |
9098 | goto do_msbd; |
9099 | case 'G': | |
9100 | limlo = 33; | |
9101 | limhi = 64; | |
9102 | goto do_msbd; | |
9103 | case 'H': | |
9104 | limlo = 33; | |
9105 | limhi = 64; | |
9106 | goto do_msbd; | |
90ecf173 | 9107 | do_msbd: |
071742cf CD |
9108 | my_getExpression (&imm_expr, s); |
9109 | check_absolute_expr (ip, &imm_expr); | |
9110 | /* Check for negative input so that small negative numbers | |
9111 | will not succeed incorrectly. The checks against | |
9112 | (pos+size) transitively check "size" itself, | |
9113 | assuming that "pos" is reasonable. */ | |
9114 | if ((long) imm_expr.X_add_number < 0 | |
9115 | || ((unsigned long) imm_expr.X_add_number | |
9116 | + lastpos) < limlo | |
9117 | || ((unsigned long) imm_expr.X_add_number | |
9118 | + lastpos) > limhi) | |
9119 | { | |
9120 | as_bad (_("Improper extract size (%lu, position %lu)"), | |
9121 | (unsigned long) imm_expr.X_add_number, | |
9122 | (unsigned long) lastpos); | |
9123 | imm_expr.X_add_number = limlo - lastpos; | |
9124 | } | |
bf12938e | 9125 | INSERT_OPERAND (EXTMSBD, *ip, imm_expr.X_add_number - 1); |
071742cf CD |
9126 | imm_expr.X_op = O_absent; |
9127 | s = expr_end; | |
9128 | continue; | |
af7ee8bf | 9129 | |
bbcc0807 CD |
9130 | case 'D': |
9131 | /* +D is for disassembly only; never match. */ | |
9132 | break; | |
9133 | ||
5f74bc13 CD |
9134 | case 'I': |
9135 | /* "+I" is like "I", except that imm2_expr is used. */ | |
9136 | my_getExpression (&imm2_expr, s); | |
9137 | if (imm2_expr.X_op != O_big | |
9138 | && imm2_expr.X_op != O_constant) | |
9139 | insn_error = _("absolute expression required"); | |
9ee2a2d4 MR |
9140 | if (HAVE_32BIT_GPRS) |
9141 | normalize_constant_expr (&imm2_expr); | |
5f74bc13 CD |
9142 | s = expr_end; |
9143 | continue; | |
9144 | ||
707bfff6 | 9145 | case 'T': /* Coprocessor register. */ |
ef2e4d86 CF |
9146 | /* +T is for disassembly only; never match. */ |
9147 | break; | |
9148 | ||
707bfff6 | 9149 | case 't': /* Coprocessor register number. */ |
ef2e4d86 CF |
9150 | if (s[0] == '$' && ISDIGIT (s[1])) |
9151 | { | |
9152 | ++s; | |
9153 | regno = 0; | |
9154 | do | |
9155 | { | |
9156 | regno *= 10; | |
9157 | regno += *s - '0'; | |
9158 | ++s; | |
9159 | } | |
9160 | while (ISDIGIT (*s)); | |
9161 | if (regno > 31) | |
9162 | as_bad (_("Invalid register number (%d)"), regno); | |
9163 | else | |
9164 | { | |
a9e24354 | 9165 | INSERT_OPERAND (RT, *ip, regno); |
ef2e4d86 CF |
9166 | continue; |
9167 | } | |
9168 | } | |
9169 | else | |
9170 | as_bad (_("Invalid coprocessor 0 register number")); | |
9171 | break; | |
9172 | ||
bb35fb24 NC |
9173 | case 'x': |
9174 | /* bbit[01] and bbit[01]32 bit index. Give error if index | |
9175 | is not in the valid range. */ | |
9176 | my_getExpression (&imm_expr, s); | |
9177 | check_absolute_expr (ip, &imm_expr); | |
9178 | if ((unsigned) imm_expr.X_add_number > 31) | |
9179 | { | |
9180 | as_bad (_("Improper bit index (%lu)"), | |
9181 | (unsigned long) imm_expr.X_add_number); | |
9182 | imm_expr.X_add_number = 0; | |
9183 | } | |
9184 | INSERT_OPERAND (BBITIND, *ip, imm_expr.X_add_number); | |
9185 | imm_expr.X_op = O_absent; | |
9186 | s = expr_end; | |
9187 | continue; | |
9188 | ||
9189 | case 'X': | |
9190 | /* bbit[01] bit index when bbit is used but we generate | |
9191 | bbit[01]32 because the index is over 32. Move to the | |
9192 | next candidate if index is not in the valid range. */ | |
9193 | my_getExpression (&imm_expr, s); | |
9194 | check_absolute_expr (ip, &imm_expr); | |
9195 | if ((unsigned) imm_expr.X_add_number < 32 | |
9196 | || (unsigned) imm_expr.X_add_number > 63) | |
9197 | break; | |
9198 | INSERT_OPERAND (BBITIND, *ip, imm_expr.X_add_number - 32); | |
9199 | imm_expr.X_op = O_absent; | |
9200 | s = expr_end; | |
9201 | continue; | |
9202 | ||
9203 | case 'p': | |
9204 | /* cins, cins32, exts and exts32 position field. Give error | |
9205 | if it's not in the valid range. */ | |
9206 | my_getExpression (&imm_expr, s); | |
9207 | check_absolute_expr (ip, &imm_expr); | |
9208 | if ((unsigned) imm_expr.X_add_number > 31) | |
9209 | { | |
9210 | as_bad (_("Improper position (%lu)"), | |
9211 | (unsigned long) imm_expr.X_add_number); | |
9212 | imm_expr.X_add_number = 0; | |
9213 | } | |
9214 | /* Make the pos explicit to simplify +S. */ | |
9215 | lastpos = imm_expr.X_add_number + 32; | |
9216 | INSERT_OPERAND (CINSPOS, *ip, imm_expr.X_add_number); | |
9217 | imm_expr.X_op = O_absent; | |
9218 | s = expr_end; | |
9219 | continue; | |
9220 | ||
9221 | case 'P': | |
9222 | /* cins, cins32, exts and exts32 position field. Move to | |
9223 | the next candidate if it's not in the valid range. */ | |
9224 | my_getExpression (&imm_expr, s); | |
9225 | check_absolute_expr (ip, &imm_expr); | |
9226 | if ((unsigned) imm_expr.X_add_number < 32 | |
9227 | || (unsigned) imm_expr.X_add_number > 63) | |
9228 | break; | |
9229 | lastpos = imm_expr.X_add_number; | |
9230 | INSERT_OPERAND (CINSPOS, *ip, imm_expr.X_add_number - 32); | |
9231 | imm_expr.X_op = O_absent; | |
9232 | s = expr_end; | |
9233 | continue; | |
9234 | ||
9235 | case 's': | |
9236 | /* cins and exts length-minus-one field. */ | |
9237 | my_getExpression (&imm_expr, s); | |
9238 | check_absolute_expr (ip, &imm_expr); | |
9239 | if ((unsigned long) imm_expr.X_add_number > 31) | |
9240 | { | |
9241 | as_bad (_("Improper size (%lu)"), | |
9242 | (unsigned long) imm_expr.X_add_number); | |
9243 | imm_expr.X_add_number = 0; | |
9244 | } | |
9245 | INSERT_OPERAND (CINSLM1, *ip, imm_expr.X_add_number); | |
9246 | imm_expr.X_op = O_absent; | |
9247 | s = expr_end; | |
9248 | continue; | |
9249 | ||
9250 | case 'S': | |
9251 | /* cins32/exts32 and cins/exts aliasing cint32/exts32 | |
9252 | length-minus-one field. */ | |
9253 | my_getExpression (&imm_expr, s); | |
9254 | check_absolute_expr (ip, &imm_expr); | |
9255 | if ((long) imm_expr.X_add_number < 0 | |
9256 | || (unsigned long) imm_expr.X_add_number + lastpos > 63) | |
9257 | { | |
9258 | as_bad (_("Improper size (%lu)"), | |
9259 | (unsigned long) imm_expr.X_add_number); | |
9260 | imm_expr.X_add_number = 0; | |
9261 | } | |
9262 | INSERT_OPERAND (CINSLM1, *ip, imm_expr.X_add_number); | |
9263 | imm_expr.X_op = O_absent; | |
9264 | s = expr_end; | |
9265 | continue; | |
9266 | ||
dd3cbb7e NC |
9267 | case 'Q': |
9268 | /* seqi/snei immediate field. */ | |
9269 | my_getExpression (&imm_expr, s); | |
9270 | check_absolute_expr (ip, &imm_expr); | |
9271 | if ((long) imm_expr.X_add_number < -512 | |
9272 | || (long) imm_expr.X_add_number >= 512) | |
9273 | { | |
9274 | as_bad (_("Improper immediate (%ld)"), | |
9275 | (long) imm_expr.X_add_number); | |
9276 | imm_expr.X_add_number = 0; | |
9277 | } | |
9278 | INSERT_OPERAND (SEQI, *ip, imm_expr.X_add_number); | |
9279 | imm_expr.X_op = O_absent; | |
9280 | s = expr_end; | |
9281 | continue; | |
9282 | ||
af7ee8bf | 9283 | default: |
f71d0d44 | 9284 | as_bad (_("Internal error: bad mips opcode " |
90ecf173 MR |
9285 | "(unknown extension operand type `+%c'): %s %s"), |
9286 | *args, insn->name, insn->args); | |
af7ee8bf CD |
9287 | /* Further processing is fruitless. */ |
9288 | return; | |
9289 | } | |
9290 | break; | |
9291 | ||
252b5132 RH |
9292 | case '<': /* must be at least one digit */ |
9293 | /* | |
9294 | * According to the manual, if the shift amount is greater | |
b6ff326e KH |
9295 | * than 31 or less than 0, then the shift amount should be |
9296 | * mod 32. In reality the mips assembler issues an error. | |
252b5132 RH |
9297 | * We issue a warning and mask out all but the low 5 bits. |
9298 | */ | |
9299 | my_getExpression (&imm_expr, s); | |
9300 | check_absolute_expr (ip, &imm_expr); | |
9301 | if ((unsigned long) imm_expr.X_add_number > 31) | |
bf12938e RS |
9302 | as_warn (_("Improper shift amount (%lu)"), |
9303 | (unsigned long) imm_expr.X_add_number); | |
9304 | INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number); | |
252b5132 RH |
9305 | imm_expr.X_op = O_absent; |
9306 | s = expr_end; | |
9307 | continue; | |
9308 | ||
9309 | case '>': /* shift amount minus 32 */ | |
9310 | my_getExpression (&imm_expr, s); | |
9311 | check_absolute_expr (ip, &imm_expr); | |
9312 | if ((unsigned long) imm_expr.X_add_number < 32 | |
9313 | || (unsigned long) imm_expr.X_add_number > 63) | |
9314 | break; | |
bf12938e | 9315 | INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number - 32); |
252b5132 RH |
9316 | imm_expr.X_op = O_absent; |
9317 | s = expr_end; | |
9318 | continue; | |
9319 | ||
90ecf173 MR |
9320 | case 'k': /* CACHE code. */ |
9321 | case 'h': /* PREFX code. */ | |
9322 | case '1': /* SYNC type. */ | |
252b5132 RH |
9323 | my_getExpression (&imm_expr, s); |
9324 | check_absolute_expr (ip, &imm_expr); | |
9325 | if ((unsigned long) imm_expr.X_add_number > 31) | |
bf12938e RS |
9326 | as_warn (_("Invalid value for `%s' (%lu)"), |
9327 | ip->insn_mo->name, | |
9328 | (unsigned long) imm_expr.X_add_number); | |
252b5132 | 9329 | if (*args == 'k') |
d954098f DD |
9330 | { |
9331 | if (mips_fix_cn63xxp1 && strcmp ("pref", insn->name) == 0) | |
9332 | switch (imm_expr.X_add_number) | |
9333 | { | |
9334 | case 5: | |
9335 | case 25: | |
9336 | case 26: | |
9337 | case 27: | |
9338 | case 28: | |
9339 | case 29: | |
9340 | case 30: | |
9341 | case 31: /* These are ok. */ | |
9342 | break; | |
9343 | ||
9344 | default: /* The rest must be changed to 28. */ | |
9345 | imm_expr.X_add_number = 28; | |
9346 | break; | |
9347 | } | |
9348 | INSERT_OPERAND (CACHE, *ip, imm_expr.X_add_number); | |
9349 | } | |
620edafd | 9350 | else if (*args == 'h') |
bf12938e | 9351 | INSERT_OPERAND (PREFX, *ip, imm_expr.X_add_number); |
620edafd CF |
9352 | else |
9353 | INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number); | |
252b5132 RH |
9354 | imm_expr.X_op = O_absent; |
9355 | s = expr_end; | |
9356 | continue; | |
9357 | ||
90ecf173 | 9358 | case 'c': /* BREAK code. */ |
252b5132 RH |
9359 | my_getExpression (&imm_expr, s); |
9360 | check_absolute_expr (ip, &imm_expr); | |
a9e24354 TS |
9361 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE) |
9362 | as_warn (_("Code for %s not in range 0..1023 (%lu)"), | |
9363 | ip->insn_mo->name, | |
bf12938e RS |
9364 | (unsigned long) imm_expr.X_add_number); |
9365 | INSERT_OPERAND (CODE, *ip, imm_expr.X_add_number); | |
252b5132 RH |
9366 | imm_expr.X_op = O_absent; |
9367 | s = expr_end; | |
9368 | continue; | |
9369 | ||
90ecf173 | 9370 | case 'q': /* Lower BREAK code. */ |
252b5132 RH |
9371 | my_getExpression (&imm_expr, s); |
9372 | check_absolute_expr (ip, &imm_expr); | |
a9e24354 TS |
9373 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE2) |
9374 | as_warn (_("Lower code for %s not in range 0..1023 (%lu)"), | |
9375 | ip->insn_mo->name, | |
bf12938e RS |
9376 | (unsigned long) imm_expr.X_add_number); |
9377 | INSERT_OPERAND (CODE2, *ip, imm_expr.X_add_number); | |
252b5132 RH |
9378 | imm_expr.X_op = O_absent; |
9379 | s = expr_end; | |
9380 | continue; | |
9381 | ||
90ecf173 | 9382 | case 'B': /* 20-bit SYSCALL/BREAK code. */ |
156c2f8b | 9383 | my_getExpression (&imm_expr, s); |
156c2f8b | 9384 | check_absolute_expr (ip, &imm_expr); |
793b27f4 | 9385 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE20) |
a9e24354 TS |
9386 | as_warn (_("Code for %s not in range 0..1048575 (%lu)"), |
9387 | ip->insn_mo->name, | |
793b27f4 | 9388 | (unsigned long) imm_expr.X_add_number); |
bf12938e | 9389 | INSERT_OPERAND (CODE20, *ip, imm_expr.X_add_number); |
252b5132 RH |
9390 | imm_expr.X_op = O_absent; |
9391 | s = expr_end; | |
9392 | continue; | |
9393 | ||
90ecf173 | 9394 | case 'C': /* Coprocessor code. */ |
beae10d5 | 9395 | my_getExpression (&imm_expr, s); |
252b5132 | 9396 | check_absolute_expr (ip, &imm_expr); |
a9e24354 | 9397 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_COPZ) |
252b5132 | 9398 | { |
793b27f4 TS |
9399 | as_warn (_("Coproccesor code > 25 bits (%lu)"), |
9400 | (unsigned long) imm_expr.X_add_number); | |
a9e24354 | 9401 | imm_expr.X_add_number &= OP_MASK_COPZ; |
252b5132 | 9402 | } |
a9e24354 | 9403 | INSERT_OPERAND (COPZ, *ip, imm_expr.X_add_number); |
beae10d5 KH |
9404 | imm_expr.X_op = O_absent; |
9405 | s = expr_end; | |
9406 | continue; | |
252b5132 | 9407 | |
90ecf173 | 9408 | case 'J': /* 19-bit WAIT code. */ |
4372b673 NC |
9409 | my_getExpression (&imm_expr, s); |
9410 | check_absolute_expr (ip, &imm_expr); | |
793b27f4 | 9411 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE19) |
a9e24354 TS |
9412 | { |
9413 | as_warn (_("Illegal 19-bit code (%lu)"), | |
9414 | (unsigned long) imm_expr.X_add_number); | |
9415 | imm_expr.X_add_number &= OP_MASK_CODE19; | |
9416 | } | |
bf12938e | 9417 | INSERT_OPERAND (CODE19, *ip, imm_expr.X_add_number); |
4372b673 NC |
9418 | imm_expr.X_op = O_absent; |
9419 | s = expr_end; | |
9420 | continue; | |
9421 | ||
707bfff6 | 9422 | case 'P': /* Performance register. */ |
beae10d5 | 9423 | my_getExpression (&imm_expr, s); |
252b5132 | 9424 | check_absolute_expr (ip, &imm_expr); |
beae10d5 | 9425 | if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1) |
bf12938e RS |
9426 | as_warn (_("Invalid performance register (%lu)"), |
9427 | (unsigned long) imm_expr.X_add_number); | |
9428 | INSERT_OPERAND (PERFREG, *ip, imm_expr.X_add_number); | |
beae10d5 KH |
9429 | imm_expr.X_op = O_absent; |
9430 | s = expr_end; | |
9431 | continue; | |
252b5132 | 9432 | |
707bfff6 TS |
9433 | case 'G': /* Coprocessor destination register. */ |
9434 | if (((ip->insn_opcode >> OP_SH_OP) & OP_MASK_OP) == OP_OP_COP0) | |
9435 | ok = reg_lookup (&s, RTYPE_NUM | RTYPE_CP0, ®no); | |
9436 | else | |
9437 | ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no); | |
a9e24354 | 9438 | INSERT_OPERAND (RD, *ip, regno); |
707bfff6 TS |
9439 | if (ok) |
9440 | { | |
9441 | lastregno = regno; | |
9442 | continue; | |
9443 | } | |
9444 | else | |
9445 | break; | |
9446 | ||
90ecf173 MR |
9447 | case 'b': /* Base register. */ |
9448 | case 'd': /* Destination register. */ | |
9449 | case 's': /* Source register. */ | |
9450 | case 't': /* Target register. */ | |
9451 | case 'r': /* Both target and source. */ | |
9452 | case 'v': /* Both dest and source. */ | |
9453 | case 'w': /* Both dest and target. */ | |
9454 | case 'E': /* Coprocessor target register. */ | |
9455 | case 'K': /* RDHWR destination register. */ | |
9456 | case 'x': /* Ignore register name. */ | |
9457 | case 'z': /* Must be zero register. */ | |
9458 | case 'U': /* Destination register (CLO/CLZ). */ | |
9459 | case 'g': /* Coprocessor destination register. */ | |
9460 | s_reset = s; | |
707bfff6 TS |
9461 | if (*args == 'E' || *args == 'K') |
9462 | ok = reg_lookup (&s, RTYPE_NUM, ®no); | |
9463 | else | |
9464 | { | |
9465 | ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no); | |
741fe287 MR |
9466 | if (regno == AT && mips_opts.at) |
9467 | { | |
9468 | if (mips_opts.at == ATREG) | |
f71d0d44 | 9469 | as_warn (_("Used $at without \".set noat\"")); |
741fe287 | 9470 | else |
f71d0d44 | 9471 | as_warn (_("Used $%u with \".set at=$%u\""), |
741fe287 MR |
9472 | regno, mips_opts.at); |
9473 | } | |
707bfff6 TS |
9474 | } |
9475 | if (ok) | |
252b5132 | 9476 | { |
252b5132 RH |
9477 | c = *args; |
9478 | if (*s == ' ') | |
f9419b05 | 9479 | ++s; |
252b5132 RH |
9480 | if (args[1] != *s) |
9481 | { | |
9482 | if (c == 'r' || c == 'v' || c == 'w') | |
9483 | { | |
9484 | regno = lastregno; | |
9485 | s = s_reset; | |
f9419b05 | 9486 | ++args; |
252b5132 RH |
9487 | } |
9488 | } | |
9489 | /* 'z' only matches $0. */ | |
9490 | if (c == 'z' && regno != 0) | |
9491 | break; | |
9492 | ||
24864476 | 9493 | if (c == 's' && !strncmp (ip->insn_mo->name, "jalr", 4)) |
e7c604dd CM |
9494 | { |
9495 | if (regno == lastregno) | |
90ecf173 MR |
9496 | { |
9497 | insn_error | |
f71d0d44 | 9498 | = _("Source and destination must be different"); |
e7c604dd | 9499 | continue; |
90ecf173 | 9500 | } |
24864476 | 9501 | if (regno == 31 && lastregno == 0xffffffff) |
90ecf173 MR |
9502 | { |
9503 | insn_error | |
f71d0d44 | 9504 | = _("A destination register must be supplied"); |
e7c604dd | 9505 | continue; |
90ecf173 | 9506 | } |
e7c604dd | 9507 | } |
90ecf173 MR |
9508 | /* Now that we have assembled one operand, we use the args |
9509 | string to figure out where it goes in the instruction. */ | |
252b5132 RH |
9510 | switch (c) |
9511 | { | |
9512 | case 'r': | |
9513 | case 's': | |
9514 | case 'v': | |
9515 | case 'b': | |
bf12938e | 9516 | INSERT_OPERAND (RS, *ip, regno); |
252b5132 RH |
9517 | break; |
9518 | case 'd': | |
9519 | case 'G': | |
af7ee8bf | 9520 | case 'K': |
ef2e4d86 | 9521 | case 'g': |
bf12938e | 9522 | INSERT_OPERAND (RD, *ip, regno); |
252b5132 | 9523 | break; |
4372b673 | 9524 | case 'U': |
bf12938e RS |
9525 | INSERT_OPERAND (RD, *ip, regno); |
9526 | INSERT_OPERAND (RT, *ip, regno); | |
4372b673 | 9527 | break; |
252b5132 RH |
9528 | case 'w': |
9529 | case 't': | |
9530 | case 'E': | |
bf12938e | 9531 | INSERT_OPERAND (RT, *ip, regno); |
252b5132 RH |
9532 | break; |
9533 | case 'x': | |
9534 | /* This case exists because on the r3000 trunc | |
9535 | expands into a macro which requires a gp | |
9536 | register. On the r6000 or r4000 it is | |
9537 | assembled into a single instruction which | |
9538 | ignores the register. Thus the insn version | |
9539 | is MIPS_ISA2 and uses 'x', and the macro | |
9540 | version is MIPS_ISA1 and uses 't'. */ | |
9541 | break; | |
9542 | case 'z': | |
9543 | /* This case is for the div instruction, which | |
9544 | acts differently if the destination argument | |
9545 | is $0. This only matches $0, and is checked | |
9546 | outside the switch. */ | |
9547 | break; | |
9548 | case 'D': | |
9549 | /* Itbl operand; not yet implemented. FIXME ?? */ | |
9550 | break; | |
9551 | /* What about all other operands like 'i', which | |
9552 | can be specified in the opcode table? */ | |
9553 | } | |
9554 | lastregno = regno; | |
9555 | continue; | |
9556 | } | |
252b5132 RH |
9557 | switch (*args++) |
9558 | { | |
9559 | case 'r': | |
9560 | case 'v': | |
bf12938e | 9561 | INSERT_OPERAND (RS, *ip, lastregno); |
252b5132 RH |
9562 | continue; |
9563 | case 'w': | |
bf12938e | 9564 | INSERT_OPERAND (RT, *ip, lastregno); |
252b5132 RH |
9565 | continue; |
9566 | } | |
9567 | break; | |
9568 | ||
deec1734 CD |
9569 | case 'O': /* MDMX alignment immediate constant. */ |
9570 | my_getExpression (&imm_expr, s); | |
9571 | check_absolute_expr (ip, &imm_expr); | |
9572 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_ALN) | |
20203fb9 | 9573 | as_warn (_("Improper align amount (%ld), using low bits"), |
bf12938e RS |
9574 | (long) imm_expr.X_add_number); |
9575 | INSERT_OPERAND (ALN, *ip, imm_expr.X_add_number); | |
deec1734 CD |
9576 | imm_expr.X_op = O_absent; |
9577 | s = expr_end; | |
9578 | continue; | |
9579 | ||
9580 | case 'Q': /* MDMX vector, element sel, or const. */ | |
9581 | if (s[0] != '$') | |
9582 | { | |
9583 | /* MDMX Immediate. */ | |
9584 | my_getExpression (&imm_expr, s); | |
9585 | check_absolute_expr (ip, &imm_expr); | |
9586 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_FT) | |
bf12938e RS |
9587 | as_warn (_("Invalid MDMX Immediate (%ld)"), |
9588 | (long) imm_expr.X_add_number); | |
9589 | INSERT_OPERAND (FT, *ip, imm_expr.X_add_number); | |
deec1734 CD |
9590 | if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL)) |
9591 | ip->insn_opcode |= MDMX_FMTSEL_IMM_QH << OP_SH_VSEL; | |
9592 | else | |
9593 | ip->insn_opcode |= MDMX_FMTSEL_IMM_OB << OP_SH_VSEL; | |
deec1734 CD |
9594 | imm_expr.X_op = O_absent; |
9595 | s = expr_end; | |
9596 | continue; | |
9597 | } | |
9598 | /* Not MDMX Immediate. Fall through. */ | |
9599 | case 'X': /* MDMX destination register. */ | |
9600 | case 'Y': /* MDMX source register. */ | |
9601 | case 'Z': /* MDMX target register. */ | |
9602 | is_mdmx = 1; | |
90ecf173 MR |
9603 | case 'D': /* Floating point destination register. */ |
9604 | case 'S': /* Floating point source register. */ | |
9605 | case 'T': /* Floating point target register. */ | |
9606 | case 'R': /* Floating point source register. */ | |
252b5132 RH |
9607 | case 'V': |
9608 | case 'W': | |
707bfff6 TS |
9609 | rtype = RTYPE_FPU; |
9610 | if (is_mdmx | |
9611 | || (mips_opts.ase_mdmx | |
9612 | && (ip->insn_mo->pinfo & FP_D) | |
9613 | && (ip->insn_mo->pinfo & (INSN_COPROC_MOVE_DELAY | |
9614 | | INSN_COPROC_MEMORY_DELAY | |
9615 | | INSN_LOAD_COPROC_DELAY | |
9616 | | INSN_LOAD_MEMORY_DELAY | |
9617 | | INSN_STORE_MEMORY)))) | |
9618 | rtype |= RTYPE_VEC; | |
252b5132 | 9619 | s_reset = s; |
707bfff6 | 9620 | if (reg_lookup (&s, rtype, ®no)) |
252b5132 | 9621 | { |
252b5132 | 9622 | if ((regno & 1) != 0 |
ca4e0257 | 9623 | && HAVE_32BIT_FPRS |
90ecf173 | 9624 | && !mips_oddfpreg_ok (ip->insn_mo, argnum)) |
252b5132 RH |
9625 | as_warn (_("Float register should be even, was %d"), |
9626 | regno); | |
9627 | ||
9628 | c = *args; | |
9629 | if (*s == ' ') | |
f9419b05 | 9630 | ++s; |
252b5132 RH |
9631 | if (args[1] != *s) |
9632 | { | |
9633 | if (c == 'V' || c == 'W') | |
9634 | { | |
9635 | regno = lastregno; | |
9636 | s = s_reset; | |
f9419b05 | 9637 | ++args; |
252b5132 RH |
9638 | } |
9639 | } | |
9640 | switch (c) | |
9641 | { | |
9642 | case 'D': | |
deec1734 | 9643 | case 'X': |
bf12938e | 9644 | INSERT_OPERAND (FD, *ip, regno); |
252b5132 RH |
9645 | break; |
9646 | case 'V': | |
9647 | case 'S': | |
deec1734 | 9648 | case 'Y': |
bf12938e | 9649 | INSERT_OPERAND (FS, *ip, regno); |
252b5132 | 9650 | break; |
deec1734 CD |
9651 | case 'Q': |
9652 | /* This is like 'Z', but also needs to fix the MDMX | |
9653 | vector/scalar select bits. Note that the | |
9654 | scalar immediate case is handled above. */ | |
9655 | if (*s == '[') | |
9656 | { | |
9657 | int is_qh = (ip->insn_opcode & (1 << OP_SH_VSEL)); | |
9658 | int max_el = (is_qh ? 3 : 7); | |
9659 | s++; | |
9660 | my_getExpression(&imm_expr, s); | |
9661 | check_absolute_expr (ip, &imm_expr); | |
9662 | s = expr_end; | |
9663 | if (imm_expr.X_add_number > max_el) | |
20203fb9 NC |
9664 | as_bad (_("Bad element selector %ld"), |
9665 | (long) imm_expr.X_add_number); | |
deec1734 CD |
9666 | imm_expr.X_add_number &= max_el; |
9667 | ip->insn_opcode |= (imm_expr.X_add_number | |
9668 | << (OP_SH_VSEL + | |
9669 | (is_qh ? 2 : 1))); | |
01a3f561 | 9670 | imm_expr.X_op = O_absent; |
deec1734 | 9671 | if (*s != ']') |
20203fb9 | 9672 | as_warn (_("Expecting ']' found '%s'"), s); |
deec1734 CD |
9673 | else |
9674 | s++; | |
9675 | } | |
9676 | else | |
9677 | { | |
9678 | if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL)) | |
9679 | ip->insn_opcode |= (MDMX_FMTSEL_VEC_QH | |
9680 | << OP_SH_VSEL); | |
9681 | else | |
9682 | ip->insn_opcode |= (MDMX_FMTSEL_VEC_OB << | |
9683 | OP_SH_VSEL); | |
9684 | } | |
90ecf173 | 9685 | /* Fall through. */ |
252b5132 RH |
9686 | case 'W': |
9687 | case 'T': | |
deec1734 | 9688 | case 'Z': |
bf12938e | 9689 | INSERT_OPERAND (FT, *ip, regno); |
252b5132 RH |
9690 | break; |
9691 | case 'R': | |
bf12938e | 9692 | INSERT_OPERAND (FR, *ip, regno); |
252b5132 RH |
9693 | break; |
9694 | } | |
9695 | lastregno = regno; | |
9696 | continue; | |
9697 | } | |
9698 | ||
252b5132 RH |
9699 | switch (*args++) |
9700 | { | |
9701 | case 'V': | |
bf12938e | 9702 | INSERT_OPERAND (FS, *ip, lastregno); |
252b5132 RH |
9703 | continue; |
9704 | case 'W': | |
bf12938e | 9705 | INSERT_OPERAND (FT, *ip, lastregno); |
252b5132 RH |
9706 | continue; |
9707 | } | |
9708 | break; | |
9709 | ||
9710 | case 'I': | |
9711 | my_getExpression (&imm_expr, s); | |
9712 | if (imm_expr.X_op != O_big | |
9713 | && imm_expr.X_op != O_constant) | |
9714 | insn_error = _("absolute expression required"); | |
9ee2a2d4 MR |
9715 | if (HAVE_32BIT_GPRS) |
9716 | normalize_constant_expr (&imm_expr); | |
252b5132 RH |
9717 | s = expr_end; |
9718 | continue; | |
9719 | ||
9720 | case 'A': | |
9721 | my_getExpression (&offset_expr, s); | |
2051e8c4 | 9722 | normalize_address_expr (&offset_expr); |
f6688943 | 9723 | *imm_reloc = BFD_RELOC_32; |
252b5132 RH |
9724 | s = expr_end; |
9725 | continue; | |
9726 | ||
9727 | case 'F': | |
9728 | case 'L': | |
9729 | case 'f': | |
9730 | case 'l': | |
9731 | { | |
9732 | int f64; | |
ca4e0257 | 9733 | int using_gprs; |
252b5132 RH |
9734 | char *save_in; |
9735 | char *err; | |
9736 | unsigned char temp[8]; | |
9737 | int len; | |
9738 | unsigned int length; | |
9739 | segT seg; | |
9740 | subsegT subseg; | |
9741 | char *p; | |
9742 | ||
9743 | /* These only appear as the last operand in an | |
9744 | instruction, and every instruction that accepts | |
9745 | them in any variant accepts them in all variants. | |
9746 | This means we don't have to worry about backing out | |
9747 | any changes if the instruction does not match. | |
9748 | ||
9749 | The difference between them is the size of the | |
9750 | floating point constant and where it goes. For 'F' | |
9751 | and 'L' the constant is 64 bits; for 'f' and 'l' it | |
9752 | is 32 bits. Where the constant is placed is based | |
9753 | on how the MIPS assembler does things: | |
9754 | F -- .rdata | |
9755 | L -- .lit8 | |
9756 | f -- immediate value | |
9757 | l -- .lit4 | |
9758 | ||
9759 | The .lit4 and .lit8 sections are only used if | |
9760 | permitted by the -G argument. | |
9761 | ||
ca4e0257 RS |
9762 | The code below needs to know whether the target register |
9763 | is 32 or 64 bits wide. It relies on the fact 'f' and | |
9764 | 'F' are used with GPR-based instructions and 'l' and | |
9765 | 'L' are used with FPR-based instructions. */ | |
252b5132 RH |
9766 | |
9767 | f64 = *args == 'F' || *args == 'L'; | |
ca4e0257 | 9768 | using_gprs = *args == 'F' || *args == 'f'; |
252b5132 RH |
9769 | |
9770 | save_in = input_line_pointer; | |
9771 | input_line_pointer = s; | |
9772 | err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len); | |
9773 | length = len; | |
9774 | s = input_line_pointer; | |
9775 | input_line_pointer = save_in; | |
9776 | if (err != NULL && *err != '\0') | |
9777 | { | |
9778 | as_bad (_("Bad floating point constant: %s"), err); | |
9779 | memset (temp, '\0', sizeof temp); | |
9780 | length = f64 ? 8 : 4; | |
9781 | } | |
9782 | ||
9c2799c2 | 9783 | gas_assert (length == (unsigned) (f64 ? 8 : 4)); |
252b5132 RH |
9784 | |
9785 | if (*args == 'f' | |
9786 | || (*args == 'l' | |
3e722fb5 | 9787 | && (g_switch_value < 4 |
252b5132 RH |
9788 | || (temp[0] == 0 && temp[1] == 0) |
9789 | || (temp[2] == 0 && temp[3] == 0)))) | |
9790 | { | |
9791 | imm_expr.X_op = O_constant; | |
90ecf173 | 9792 | if (!target_big_endian) |
252b5132 RH |
9793 | imm_expr.X_add_number = bfd_getl32 (temp); |
9794 | else | |
9795 | imm_expr.X_add_number = bfd_getb32 (temp); | |
9796 | } | |
9797 | else if (length > 4 | |
90ecf173 | 9798 | && !mips_disable_float_construction |
ca4e0257 RS |
9799 | /* Constants can only be constructed in GPRs and |
9800 | copied to FPRs if the GPRs are at least as wide | |
9801 | as the FPRs. Force the constant into memory if | |
9802 | we are using 64-bit FPRs but the GPRs are only | |
9803 | 32 bits wide. */ | |
9804 | && (using_gprs | |
90ecf173 | 9805 | || !(HAVE_64BIT_FPRS && HAVE_32BIT_GPRS)) |
252b5132 RH |
9806 | && ((temp[0] == 0 && temp[1] == 0) |
9807 | || (temp[2] == 0 && temp[3] == 0)) | |
9808 | && ((temp[4] == 0 && temp[5] == 0) | |
9809 | || (temp[6] == 0 && temp[7] == 0))) | |
9810 | { | |
ca4e0257 | 9811 | /* The value is simple enough to load with a couple of |
90ecf173 MR |
9812 | instructions. If using 32-bit registers, set |
9813 | imm_expr to the high order 32 bits and offset_expr to | |
9814 | the low order 32 bits. Otherwise, set imm_expr to | |
9815 | the entire 64 bit constant. */ | |
ca4e0257 | 9816 | if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS) |
252b5132 RH |
9817 | { |
9818 | imm_expr.X_op = O_constant; | |
9819 | offset_expr.X_op = O_constant; | |
90ecf173 | 9820 | if (!target_big_endian) |
252b5132 RH |
9821 | { |
9822 | imm_expr.X_add_number = bfd_getl32 (temp + 4); | |
9823 | offset_expr.X_add_number = bfd_getl32 (temp); | |
9824 | } | |
9825 | else | |
9826 | { | |
9827 | imm_expr.X_add_number = bfd_getb32 (temp); | |
9828 | offset_expr.X_add_number = bfd_getb32 (temp + 4); | |
9829 | } | |
9830 | if (offset_expr.X_add_number == 0) | |
9831 | offset_expr.X_op = O_absent; | |
9832 | } | |
9833 | else if (sizeof (imm_expr.X_add_number) > 4) | |
9834 | { | |
9835 | imm_expr.X_op = O_constant; | |
90ecf173 | 9836 | if (!target_big_endian) |
252b5132 RH |
9837 | imm_expr.X_add_number = bfd_getl64 (temp); |
9838 | else | |
9839 | imm_expr.X_add_number = bfd_getb64 (temp); | |
9840 | } | |
9841 | else | |
9842 | { | |
9843 | imm_expr.X_op = O_big; | |
9844 | imm_expr.X_add_number = 4; | |
90ecf173 | 9845 | if (!target_big_endian) |
252b5132 RH |
9846 | { |
9847 | generic_bignum[0] = bfd_getl16 (temp); | |
9848 | generic_bignum[1] = bfd_getl16 (temp + 2); | |
9849 | generic_bignum[2] = bfd_getl16 (temp + 4); | |
9850 | generic_bignum[3] = bfd_getl16 (temp + 6); | |
9851 | } | |
9852 | else | |
9853 | { | |
9854 | generic_bignum[0] = bfd_getb16 (temp + 6); | |
9855 | generic_bignum[1] = bfd_getb16 (temp + 4); | |
9856 | generic_bignum[2] = bfd_getb16 (temp + 2); | |
9857 | generic_bignum[3] = bfd_getb16 (temp); | |
9858 | } | |
9859 | } | |
9860 | } | |
9861 | else | |
9862 | { | |
9863 | const char *newname; | |
9864 | segT new_seg; | |
9865 | ||
9866 | /* Switch to the right section. */ | |
9867 | seg = now_seg; | |
9868 | subseg = now_subseg; | |
9869 | switch (*args) | |
9870 | { | |
9871 | default: /* unused default case avoids warnings. */ | |
9872 | case 'L': | |
9873 | newname = RDATA_SECTION_NAME; | |
3e722fb5 | 9874 | if (g_switch_value >= 8) |
252b5132 RH |
9875 | newname = ".lit8"; |
9876 | break; | |
9877 | case 'F': | |
3e722fb5 | 9878 | newname = RDATA_SECTION_NAME; |
252b5132 RH |
9879 | break; |
9880 | case 'l': | |
9c2799c2 | 9881 | gas_assert (g_switch_value >= 4); |
252b5132 RH |
9882 | newname = ".lit4"; |
9883 | break; | |
9884 | } | |
9885 | new_seg = subseg_new (newname, (subsegT) 0); | |
f43abd2b | 9886 | if (IS_ELF) |
252b5132 RH |
9887 | bfd_set_section_flags (stdoutput, new_seg, |
9888 | (SEC_ALLOC | |
9889 | | SEC_LOAD | |
9890 | | SEC_READONLY | |
9891 | | SEC_DATA)); | |
9892 | frag_align (*args == 'l' ? 2 : 3, 0, 0); | |
c41e87e3 | 9893 | if (IS_ELF && strncmp (TARGET_OS, "elf", 3) != 0) |
252b5132 RH |
9894 | record_alignment (new_seg, 4); |
9895 | else | |
9896 | record_alignment (new_seg, *args == 'l' ? 2 : 3); | |
9897 | if (seg == now_seg) | |
9898 | as_bad (_("Can't use floating point insn in this section")); | |
9899 | ||
9900 | /* Set the argument to the current address in the | |
9901 | section. */ | |
9902 | offset_expr.X_op = O_symbol; | |
8680f6e1 | 9903 | offset_expr.X_add_symbol = symbol_temp_new_now (); |
252b5132 RH |
9904 | offset_expr.X_add_number = 0; |
9905 | ||
9906 | /* Put the floating point number into the section. */ | |
9907 | p = frag_more ((int) length); | |
9908 | memcpy (p, temp, length); | |
9909 | ||
9910 | /* Switch back to the original section. */ | |
9911 | subseg_set (seg, subseg); | |
9912 | } | |
9913 | } | |
9914 | continue; | |
9915 | ||
90ecf173 MR |
9916 | case 'i': /* 16-bit unsigned immediate. */ |
9917 | case 'j': /* 16-bit signed immediate. */ | |
f6688943 | 9918 | *imm_reloc = BFD_RELOC_LO16; |
5e0116d5 | 9919 | if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0) |
252b5132 RH |
9920 | { |
9921 | int more; | |
5e0116d5 RS |
9922 | offsetT minval, maxval; |
9923 | ||
9924 | more = (insn + 1 < &mips_opcodes[NUMOPCODES] | |
9925 | && strcmp (insn->name, insn[1].name) == 0); | |
9926 | ||
9927 | /* If the expression was written as an unsigned number, | |
9928 | only treat it as signed if there are no more | |
9929 | alternatives. */ | |
9930 | if (more | |
9931 | && *args == 'j' | |
9932 | && sizeof (imm_expr.X_add_number) <= 4 | |
9933 | && imm_expr.X_op == O_constant | |
9934 | && imm_expr.X_add_number < 0 | |
9935 | && imm_expr.X_unsigned | |
9936 | && HAVE_64BIT_GPRS) | |
9937 | break; | |
9938 | ||
9939 | /* For compatibility with older assemblers, we accept | |
9940 | 0x8000-0xffff as signed 16-bit numbers when only | |
9941 | signed numbers are allowed. */ | |
9942 | if (*args == 'i') | |
9943 | minval = 0, maxval = 0xffff; | |
9944 | else if (more) | |
9945 | minval = -0x8000, maxval = 0x7fff; | |
252b5132 | 9946 | else |
5e0116d5 RS |
9947 | minval = -0x8000, maxval = 0xffff; |
9948 | ||
9949 | if (imm_expr.X_op != O_constant | |
9950 | || imm_expr.X_add_number < minval | |
9951 | || imm_expr.X_add_number > maxval) | |
252b5132 RH |
9952 | { |
9953 | if (more) | |
9954 | break; | |
2ae7e77b AH |
9955 | if (imm_expr.X_op == O_constant |
9956 | || imm_expr.X_op == O_big) | |
f71d0d44 | 9957 | as_bad (_("Expression out of range")); |
252b5132 RH |
9958 | } |
9959 | } | |
9960 | s = expr_end; | |
9961 | continue; | |
9962 | ||
90ecf173 | 9963 | case 'o': /* 16-bit offset. */ |
4614d845 MR |
9964 | offset_reloc[0] = BFD_RELOC_LO16; |
9965 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
9966 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
9967 | ||
5e0116d5 RS |
9968 | /* Check whether there is only a single bracketed expression |
9969 | left. If so, it must be the base register and the | |
9970 | constant must be zero. */ | |
e391c024 RS |
9971 | offset_reloc[0] = BFD_RELOC_LO16; |
9972 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
9973 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
5e0116d5 RS |
9974 | if (*s == '(' && strchr (s + 1, '(') == 0) |
9975 | { | |
9976 | offset_expr.X_op = O_constant; | |
9977 | offset_expr.X_add_number = 0; | |
9978 | continue; | |
9979 | } | |
252b5132 RH |
9980 | |
9981 | /* If this value won't fit into a 16 bit offset, then go | |
9982 | find a macro that will generate the 32 bit offset | |
afdbd6d0 | 9983 | code pattern. */ |
5e0116d5 | 9984 | if (my_getSmallExpression (&offset_expr, offset_reloc, s) == 0 |
252b5132 RH |
9985 | && (offset_expr.X_op != O_constant |
9986 | || offset_expr.X_add_number >= 0x8000 | |
afdbd6d0 | 9987 | || offset_expr.X_add_number < -0x8000)) |
252b5132 RH |
9988 | break; |
9989 | ||
252b5132 RH |
9990 | s = expr_end; |
9991 | continue; | |
9992 | ||
90ecf173 | 9993 | case 'p': /* PC-relative offset. */ |
0b25d3e6 | 9994 | *offset_reloc = BFD_RELOC_16_PCREL_S2; |
252b5132 RH |
9995 | my_getExpression (&offset_expr, s); |
9996 | s = expr_end; | |
9997 | continue; | |
9998 | ||
90ecf173 | 9999 | case 'u': /* Upper 16 bits. */ |
5e0116d5 RS |
10000 | if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0 |
10001 | && imm_expr.X_op == O_constant | |
10002 | && (imm_expr.X_add_number < 0 | |
10003 | || imm_expr.X_add_number >= 0x10000)) | |
88320db2 MR |
10004 | as_bad (_("lui expression (%lu) not in range 0..65535"), |
10005 | (unsigned long) imm_expr.X_add_number); | |
252b5132 RH |
10006 | s = expr_end; |
10007 | continue; | |
10008 | ||
90ecf173 | 10009 | case 'a': /* 26-bit address. */ |
252b5132 RH |
10010 | my_getExpression (&offset_expr, s); |
10011 | s = expr_end; | |
f6688943 | 10012 | *offset_reloc = BFD_RELOC_MIPS_JMP; |
252b5132 RH |
10013 | continue; |
10014 | ||
90ecf173 MR |
10015 | case 'N': /* 3-bit branch condition code. */ |
10016 | case 'M': /* 3-bit compare condition code. */ | |
707bfff6 | 10017 | rtype = RTYPE_CCC; |
90ecf173 | 10018 | if (ip->insn_mo->pinfo & (FP_D | FP_S)) |
707bfff6 TS |
10019 | rtype |= RTYPE_FCC; |
10020 | if (!reg_lookup (&s, rtype, ®no)) | |
252b5132 | 10021 | break; |
90ecf173 MR |
10022 | if ((strcmp (str + strlen (str) - 3, ".ps") == 0 |
10023 | || strcmp (str + strlen (str) - 5, "any2f") == 0 | |
10024 | || strcmp (str + strlen (str) - 5, "any2t") == 0) | |
30c378fd | 10025 | && (regno & 1) != 0) |
90ecf173 MR |
10026 | as_warn (_("Condition code register should be even for %s, " |
10027 | "was %d"), | |
20203fb9 | 10028 | str, regno); |
90ecf173 MR |
10029 | if ((strcmp (str + strlen (str) - 5, "any4f") == 0 |
10030 | || strcmp (str + strlen (str) - 5, "any4t") == 0) | |
30c378fd | 10031 | && (regno & 3) != 0) |
90ecf173 MR |
10032 | as_warn (_("Condition code register should be 0 or 4 for %s, " |
10033 | "was %d"), | |
20203fb9 | 10034 | str, regno); |
252b5132 | 10035 | if (*args == 'N') |
bf12938e | 10036 | INSERT_OPERAND (BCC, *ip, regno); |
252b5132 | 10037 | else |
bf12938e | 10038 | INSERT_OPERAND (CCC, *ip, regno); |
beae10d5 | 10039 | continue; |
252b5132 | 10040 | |
156c2f8b NC |
10041 | case 'H': |
10042 | if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X')) | |
10043 | s += 2; | |
3882b010 | 10044 | if (ISDIGIT (*s)) |
156c2f8b NC |
10045 | { |
10046 | c = 0; | |
10047 | do | |
10048 | { | |
10049 | c *= 10; | |
10050 | c += *s - '0'; | |
10051 | ++s; | |
10052 | } | |
3882b010 | 10053 | while (ISDIGIT (*s)); |
156c2f8b NC |
10054 | } |
10055 | else | |
10056 | c = 8; /* Invalid sel value. */ | |
10057 | ||
10058 | if (c > 7) | |
f71d0d44 | 10059 | as_bad (_("Invalid coprocessor sub-selection value (0-7)")); |
156c2f8b NC |
10060 | ip->insn_opcode |= c; |
10061 | continue; | |
10062 | ||
60b63b72 RS |
10063 | case 'e': |
10064 | /* Must be at least one digit. */ | |
10065 | my_getExpression (&imm_expr, s); | |
10066 | check_absolute_expr (ip, &imm_expr); | |
10067 | ||
10068 | if ((unsigned long) imm_expr.X_add_number | |
10069 | > (unsigned long) OP_MASK_VECBYTE) | |
10070 | { | |
10071 | as_bad (_("bad byte vector index (%ld)"), | |
10072 | (long) imm_expr.X_add_number); | |
10073 | imm_expr.X_add_number = 0; | |
10074 | } | |
10075 | ||
bf12938e | 10076 | INSERT_OPERAND (VECBYTE, *ip, imm_expr.X_add_number); |
60b63b72 RS |
10077 | imm_expr.X_op = O_absent; |
10078 | s = expr_end; | |
10079 | continue; | |
10080 | ||
10081 | case '%': | |
10082 | my_getExpression (&imm_expr, s); | |
10083 | check_absolute_expr (ip, &imm_expr); | |
10084 | ||
10085 | if ((unsigned long) imm_expr.X_add_number | |
10086 | > (unsigned long) OP_MASK_VECALIGN) | |
10087 | { | |
10088 | as_bad (_("bad byte vector index (%ld)"), | |
10089 | (long) imm_expr.X_add_number); | |
10090 | imm_expr.X_add_number = 0; | |
10091 | } | |
10092 | ||
bf12938e | 10093 | INSERT_OPERAND (VECALIGN, *ip, imm_expr.X_add_number); |
60b63b72 RS |
10094 | imm_expr.X_op = O_absent; |
10095 | s = expr_end; | |
10096 | continue; | |
10097 | ||
252b5132 | 10098 | default: |
f71d0d44 | 10099 | as_bad (_("Bad char = '%c'\n"), *args); |
252b5132 RH |
10100 | internalError (); |
10101 | } | |
10102 | break; | |
10103 | } | |
10104 | /* Args don't match. */ | |
10105 | if (insn + 1 < &mips_opcodes[NUMOPCODES] && | |
10106 | !strcmp (insn->name, insn[1].name)) | |
10107 | { | |
10108 | ++insn; | |
10109 | s = argsStart; | |
f71d0d44 | 10110 | insn_error = _("Illegal operands"); |
252b5132 RH |
10111 | continue; |
10112 | } | |
268f6bed | 10113 | if (save_c) |
570de991 | 10114 | *(--argsStart) = save_c; |
f71d0d44 | 10115 | insn_error = _("Illegal operands"); |
252b5132 RH |
10116 | return; |
10117 | } | |
10118 | } | |
10119 | ||
0499d65b TS |
10120 | #define SKIP_SPACE_TABS(S) { while (*(S) == ' ' || *(S) == '\t') ++(S); } |
10121 | ||
252b5132 RH |
10122 | /* This routine assembles an instruction into its binary format when |
10123 | assembling for the mips16. As a side effect, it sets one of the | |
10124 | global variables imm_reloc or offset_reloc to the type of | |
10125 | relocation to do if one of the operands is an address expression. | |
10126 | It also sets mips16_small and mips16_ext if the user explicitly | |
10127 | requested a small or extended instruction. */ | |
10128 | ||
10129 | static void | |
17a2f251 | 10130 | mips16_ip (char *str, struct mips_cl_insn *ip) |
252b5132 RH |
10131 | { |
10132 | char *s; | |
10133 | const char *args; | |
10134 | struct mips_opcode *insn; | |
10135 | char *argsstart; | |
10136 | unsigned int regno; | |
10137 | unsigned int lastregno = 0; | |
10138 | char *s_reset; | |
d6f16593 | 10139 | size_t i; |
252b5132 RH |
10140 | |
10141 | insn_error = NULL; | |
10142 | ||
b34976b6 AM |
10143 | mips16_small = FALSE; |
10144 | mips16_ext = FALSE; | |
252b5132 | 10145 | |
3882b010 | 10146 | for (s = str; ISLOWER (*s); ++s) |
252b5132 RH |
10147 | ; |
10148 | switch (*s) | |
10149 | { | |
10150 | case '\0': | |
10151 | break; | |
10152 | ||
10153 | case ' ': | |
10154 | *s++ = '\0'; | |
10155 | break; | |
10156 | ||
10157 | case '.': | |
10158 | if (s[1] == 't' && s[2] == ' ') | |
10159 | { | |
10160 | *s = '\0'; | |
b34976b6 | 10161 | mips16_small = TRUE; |
252b5132 RH |
10162 | s += 3; |
10163 | break; | |
10164 | } | |
10165 | else if (s[1] == 'e' && s[2] == ' ') | |
10166 | { | |
10167 | *s = '\0'; | |
b34976b6 | 10168 | mips16_ext = TRUE; |
252b5132 RH |
10169 | s += 3; |
10170 | break; | |
10171 | } | |
10172 | /* Fall through. */ | |
10173 | default: | |
10174 | insn_error = _("unknown opcode"); | |
10175 | return; | |
10176 | } | |
10177 | ||
10178 | if (mips_opts.noautoextend && ! mips16_ext) | |
b34976b6 | 10179 | mips16_small = TRUE; |
252b5132 RH |
10180 | |
10181 | if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL) | |
10182 | { | |
10183 | insn_error = _("unrecognized opcode"); | |
10184 | return; | |
10185 | } | |
10186 | ||
10187 | argsstart = s; | |
10188 | for (;;) | |
10189 | { | |
9b3f89ee TS |
10190 | bfd_boolean ok; |
10191 | ||
9c2799c2 | 10192 | gas_assert (strcmp (insn->name, str) == 0); |
252b5132 | 10193 | |
037b32b9 | 10194 | ok = is_opcode_valid_16 (insn); |
9b3f89ee TS |
10195 | if (! ok) |
10196 | { | |
10197 | if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] | |
10198 | && strcmp (insn->name, insn[1].name) == 0) | |
10199 | { | |
10200 | ++insn; | |
10201 | continue; | |
10202 | } | |
10203 | else | |
10204 | { | |
10205 | if (!insn_error) | |
10206 | { | |
10207 | static char buf[100]; | |
10208 | sprintf (buf, | |
10209 | _("opcode not supported on this processor: %s (%s)"), | |
10210 | mips_cpu_info_from_arch (mips_opts.arch)->name, | |
10211 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
10212 | insn_error = buf; | |
10213 | } | |
10214 | return; | |
10215 | } | |
10216 | } | |
10217 | ||
1e915849 | 10218 | create_insn (ip, insn); |
252b5132 | 10219 | imm_expr.X_op = O_absent; |
f6688943 TS |
10220 | imm_reloc[0] = BFD_RELOC_UNUSED; |
10221 | imm_reloc[1] = BFD_RELOC_UNUSED; | |
10222 | imm_reloc[2] = BFD_RELOC_UNUSED; | |
5f74bc13 | 10223 | imm2_expr.X_op = O_absent; |
252b5132 | 10224 | offset_expr.X_op = O_absent; |
f6688943 TS |
10225 | offset_reloc[0] = BFD_RELOC_UNUSED; |
10226 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
10227 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
10228 | for (args = insn->args; 1; ++args) |
10229 | { | |
10230 | int c; | |
10231 | ||
10232 | if (*s == ' ') | |
10233 | ++s; | |
10234 | ||
10235 | /* In this switch statement we call break if we did not find | |
10236 | a match, continue if we did find a match, or return if we | |
10237 | are done. */ | |
10238 | ||
10239 | c = *args; | |
10240 | switch (c) | |
10241 | { | |
10242 | case '\0': | |
10243 | if (*s == '\0') | |
10244 | { | |
10245 | /* Stuff the immediate value in now, if we can. */ | |
10246 | if (imm_expr.X_op == O_constant | |
f6688943 | 10247 | && *imm_reloc > BFD_RELOC_UNUSED |
738e5348 RS |
10248 | && *imm_reloc != BFD_RELOC_MIPS16_GOT16 |
10249 | && *imm_reloc != BFD_RELOC_MIPS16_CALL16 | |
252b5132 RH |
10250 | && insn->pinfo != INSN_MACRO) |
10251 | { | |
d6f16593 MR |
10252 | valueT tmp; |
10253 | ||
10254 | switch (*offset_reloc) | |
10255 | { | |
10256 | case BFD_RELOC_MIPS16_HI16_S: | |
10257 | tmp = (imm_expr.X_add_number + 0x8000) >> 16; | |
10258 | break; | |
10259 | ||
10260 | case BFD_RELOC_MIPS16_HI16: | |
10261 | tmp = imm_expr.X_add_number >> 16; | |
10262 | break; | |
10263 | ||
10264 | case BFD_RELOC_MIPS16_LO16: | |
10265 | tmp = ((imm_expr.X_add_number + 0x8000) & 0xffff) | |
10266 | - 0x8000; | |
10267 | break; | |
10268 | ||
10269 | case BFD_RELOC_UNUSED: | |
10270 | tmp = imm_expr.X_add_number; | |
10271 | break; | |
10272 | ||
10273 | default: | |
10274 | internalError (); | |
10275 | } | |
10276 | *offset_reloc = BFD_RELOC_UNUSED; | |
10277 | ||
c4e7957c | 10278 | mips16_immed (NULL, 0, *imm_reloc - BFD_RELOC_UNUSED, |
d6f16593 | 10279 | tmp, TRUE, mips16_small, |
252b5132 RH |
10280 | mips16_ext, &ip->insn_opcode, |
10281 | &ip->use_extend, &ip->extend); | |
10282 | imm_expr.X_op = O_absent; | |
f6688943 | 10283 | *imm_reloc = BFD_RELOC_UNUSED; |
252b5132 RH |
10284 | } |
10285 | ||
10286 | return; | |
10287 | } | |
10288 | break; | |
10289 | ||
10290 | case ',': | |
10291 | if (*s++ == c) | |
10292 | continue; | |
10293 | s--; | |
10294 | switch (*++args) | |
10295 | { | |
10296 | case 'v': | |
bf12938e | 10297 | MIPS16_INSERT_OPERAND (RX, *ip, lastregno); |
252b5132 RH |
10298 | continue; |
10299 | case 'w': | |
bf12938e | 10300 | MIPS16_INSERT_OPERAND (RY, *ip, lastregno); |
252b5132 RH |
10301 | continue; |
10302 | } | |
10303 | break; | |
10304 | ||
10305 | case '(': | |
10306 | case ')': | |
10307 | if (*s++ == c) | |
10308 | continue; | |
10309 | break; | |
10310 | ||
10311 | case 'v': | |
10312 | case 'w': | |
10313 | if (s[0] != '$') | |
10314 | { | |
10315 | if (c == 'v') | |
bf12938e | 10316 | MIPS16_INSERT_OPERAND (RX, *ip, lastregno); |
252b5132 | 10317 | else |
bf12938e | 10318 | MIPS16_INSERT_OPERAND (RY, *ip, lastregno); |
252b5132 RH |
10319 | ++args; |
10320 | continue; | |
10321 | } | |
10322 | /* Fall through. */ | |
10323 | case 'x': | |
10324 | case 'y': | |
10325 | case 'z': | |
10326 | case 'Z': | |
10327 | case '0': | |
10328 | case 'S': | |
10329 | case 'R': | |
10330 | case 'X': | |
10331 | case 'Y': | |
707bfff6 TS |
10332 | s_reset = s; |
10333 | if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no)) | |
252b5132 | 10334 | { |
707bfff6 | 10335 | if (c == 'v' || c == 'w') |
85b51719 | 10336 | { |
707bfff6 | 10337 | if (c == 'v') |
a9e24354 | 10338 | MIPS16_INSERT_OPERAND (RX, *ip, lastregno); |
707bfff6 | 10339 | else |
a9e24354 | 10340 | MIPS16_INSERT_OPERAND (RY, *ip, lastregno); |
707bfff6 TS |
10341 | ++args; |
10342 | continue; | |
85b51719 | 10343 | } |
707bfff6 | 10344 | break; |
252b5132 RH |
10345 | } |
10346 | ||
10347 | if (*s == ' ') | |
10348 | ++s; | |
10349 | if (args[1] != *s) | |
10350 | { | |
10351 | if (c == 'v' || c == 'w') | |
10352 | { | |
10353 | regno = mips16_to_32_reg_map[lastregno]; | |
10354 | s = s_reset; | |
f9419b05 | 10355 | ++args; |
252b5132 RH |
10356 | } |
10357 | } | |
10358 | ||
10359 | switch (c) | |
10360 | { | |
10361 | case 'x': | |
10362 | case 'y': | |
10363 | case 'z': | |
10364 | case 'v': | |
10365 | case 'w': | |
10366 | case 'Z': | |
10367 | regno = mips32_to_16_reg_map[regno]; | |
10368 | break; | |
10369 | ||
10370 | case '0': | |
10371 | if (regno != 0) | |
10372 | regno = ILLEGAL_REG; | |
10373 | break; | |
10374 | ||
10375 | case 'S': | |
10376 | if (regno != SP) | |
10377 | regno = ILLEGAL_REG; | |
10378 | break; | |
10379 | ||
10380 | case 'R': | |
10381 | if (regno != RA) | |
10382 | regno = ILLEGAL_REG; | |
10383 | break; | |
10384 | ||
10385 | case 'X': | |
10386 | case 'Y': | |
741fe287 MR |
10387 | if (regno == AT && mips_opts.at) |
10388 | { | |
10389 | if (mips_opts.at == ATREG) | |
10390 | as_warn (_("used $at without \".set noat\"")); | |
10391 | else | |
10392 | as_warn (_("used $%u with \".set at=$%u\""), | |
10393 | regno, mips_opts.at); | |
10394 | } | |
252b5132 RH |
10395 | break; |
10396 | ||
10397 | default: | |
10398 | internalError (); | |
10399 | } | |
10400 | ||
10401 | if (regno == ILLEGAL_REG) | |
10402 | break; | |
10403 | ||
10404 | switch (c) | |
10405 | { | |
10406 | case 'x': | |
10407 | case 'v': | |
bf12938e | 10408 | MIPS16_INSERT_OPERAND (RX, *ip, regno); |
252b5132 RH |
10409 | break; |
10410 | case 'y': | |
10411 | case 'w': | |
bf12938e | 10412 | MIPS16_INSERT_OPERAND (RY, *ip, regno); |
252b5132 RH |
10413 | break; |
10414 | case 'z': | |
bf12938e | 10415 | MIPS16_INSERT_OPERAND (RZ, *ip, regno); |
252b5132 RH |
10416 | break; |
10417 | case 'Z': | |
bf12938e | 10418 | MIPS16_INSERT_OPERAND (MOVE32Z, *ip, regno); |
252b5132 RH |
10419 | case '0': |
10420 | case 'S': | |
10421 | case 'R': | |
10422 | break; | |
10423 | case 'X': | |
bf12938e | 10424 | MIPS16_INSERT_OPERAND (REGR32, *ip, regno); |
252b5132 RH |
10425 | break; |
10426 | case 'Y': | |
10427 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); | |
bf12938e | 10428 | MIPS16_INSERT_OPERAND (REG32R, *ip, regno); |
252b5132 RH |
10429 | break; |
10430 | default: | |
10431 | internalError (); | |
10432 | } | |
10433 | ||
10434 | lastregno = regno; | |
10435 | continue; | |
10436 | ||
10437 | case 'P': | |
10438 | if (strncmp (s, "$pc", 3) == 0) | |
10439 | { | |
10440 | s += 3; | |
10441 | continue; | |
10442 | } | |
10443 | break; | |
10444 | ||
252b5132 RH |
10445 | case '5': |
10446 | case 'H': | |
10447 | case 'W': | |
10448 | case 'D': | |
10449 | case 'j': | |
252b5132 RH |
10450 | case 'V': |
10451 | case 'C': | |
10452 | case 'U': | |
10453 | case 'k': | |
10454 | case 'K': | |
d6f16593 MR |
10455 | i = my_getSmallExpression (&imm_expr, imm_reloc, s); |
10456 | if (i > 0) | |
252b5132 | 10457 | { |
d6f16593 | 10458 | if (imm_expr.X_op != O_constant) |
252b5132 | 10459 | { |
b34976b6 | 10460 | mips16_ext = TRUE; |
b34976b6 | 10461 | ip->use_extend = TRUE; |
252b5132 | 10462 | ip->extend = 0; |
252b5132 | 10463 | } |
d6f16593 MR |
10464 | else |
10465 | { | |
10466 | /* We need to relax this instruction. */ | |
10467 | *offset_reloc = *imm_reloc; | |
10468 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; | |
10469 | } | |
10470 | s = expr_end; | |
10471 | continue; | |
252b5132 | 10472 | } |
d6f16593 MR |
10473 | *imm_reloc = BFD_RELOC_UNUSED; |
10474 | /* Fall through. */ | |
10475 | case '<': | |
10476 | case '>': | |
10477 | case '[': | |
10478 | case ']': | |
10479 | case '4': | |
10480 | case '8': | |
10481 | my_getExpression (&imm_expr, s); | |
252b5132 RH |
10482 | if (imm_expr.X_op == O_register) |
10483 | { | |
10484 | /* What we thought was an expression turned out to | |
10485 | be a register. */ | |
10486 | ||
10487 | if (s[0] == '(' && args[1] == '(') | |
10488 | { | |
10489 | /* It looks like the expression was omitted | |
10490 | before a register indirection, which means | |
10491 | that the expression is implicitly zero. We | |
10492 | still set up imm_expr, so that we handle | |
10493 | explicit extensions correctly. */ | |
10494 | imm_expr.X_op = O_constant; | |
10495 | imm_expr.X_add_number = 0; | |
f6688943 | 10496 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
10497 | continue; |
10498 | } | |
10499 | ||
10500 | break; | |
10501 | } | |
10502 | ||
10503 | /* We need to relax this instruction. */ | |
f6688943 | 10504 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
10505 | s = expr_end; |
10506 | continue; | |
10507 | ||
10508 | case 'p': | |
10509 | case 'q': | |
10510 | case 'A': | |
10511 | case 'B': | |
10512 | case 'E': | |
10513 | /* We use offset_reloc rather than imm_reloc for the PC | |
10514 | relative operands. This lets macros with both | |
10515 | immediate and address operands work correctly. */ | |
10516 | my_getExpression (&offset_expr, s); | |
10517 | ||
10518 | if (offset_expr.X_op == O_register) | |
10519 | break; | |
10520 | ||
10521 | /* We need to relax this instruction. */ | |
f6688943 | 10522 | *offset_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
10523 | s = expr_end; |
10524 | continue; | |
10525 | ||
10526 | case '6': /* break code */ | |
10527 | my_getExpression (&imm_expr, s); | |
10528 | check_absolute_expr (ip, &imm_expr); | |
10529 | if ((unsigned long) imm_expr.X_add_number > 63) | |
bf12938e RS |
10530 | as_warn (_("Invalid value for `%s' (%lu)"), |
10531 | ip->insn_mo->name, | |
10532 | (unsigned long) imm_expr.X_add_number); | |
10533 | MIPS16_INSERT_OPERAND (IMM6, *ip, imm_expr.X_add_number); | |
252b5132 RH |
10534 | imm_expr.X_op = O_absent; |
10535 | s = expr_end; | |
10536 | continue; | |
10537 | ||
10538 | case 'a': /* 26 bit address */ | |
10539 | my_getExpression (&offset_expr, s); | |
10540 | s = expr_end; | |
f6688943 | 10541 | *offset_reloc = BFD_RELOC_MIPS16_JMP; |
252b5132 RH |
10542 | ip->insn_opcode <<= 16; |
10543 | continue; | |
10544 | ||
10545 | case 'l': /* register list for entry macro */ | |
10546 | case 'L': /* register list for exit macro */ | |
10547 | { | |
10548 | int mask; | |
10549 | ||
10550 | if (c == 'l') | |
10551 | mask = 0; | |
10552 | else | |
10553 | mask = 7 << 3; | |
10554 | while (*s != '\0') | |
10555 | { | |
707bfff6 | 10556 | unsigned int freg, reg1, reg2; |
252b5132 RH |
10557 | |
10558 | while (*s == ' ' || *s == ',') | |
10559 | ++s; | |
707bfff6 | 10560 | if (reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®1)) |
252b5132 | 10561 | freg = 0; |
707bfff6 TS |
10562 | else if (reg_lookup (&s, RTYPE_FPU, ®1)) |
10563 | freg = 1; | |
252b5132 RH |
10564 | else |
10565 | { | |
707bfff6 TS |
10566 | as_bad (_("can't parse register list")); |
10567 | break; | |
252b5132 RH |
10568 | } |
10569 | if (*s == ' ') | |
10570 | ++s; | |
10571 | if (*s != '-') | |
10572 | reg2 = reg1; | |
10573 | else | |
10574 | { | |
10575 | ++s; | |
707bfff6 TS |
10576 | if (!reg_lookup (&s, freg ? RTYPE_FPU |
10577 | : (RTYPE_GP | RTYPE_NUM), ®2)) | |
252b5132 | 10578 | { |
707bfff6 TS |
10579 | as_bad (_("invalid register list")); |
10580 | break; | |
252b5132 RH |
10581 | } |
10582 | } | |
10583 | if (freg && reg1 == 0 && reg2 == 0 && c == 'L') | |
10584 | { | |
10585 | mask &= ~ (7 << 3); | |
10586 | mask |= 5 << 3; | |
10587 | } | |
10588 | else if (freg && reg1 == 0 && reg2 == 1 && c == 'L') | |
10589 | { | |
10590 | mask &= ~ (7 << 3); | |
10591 | mask |= 6 << 3; | |
10592 | } | |
10593 | else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L') | |
10594 | mask |= (reg2 - 3) << 3; | |
10595 | else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17) | |
10596 | mask |= (reg2 - 15) << 1; | |
f9419b05 | 10597 | else if (reg1 == RA && reg2 == RA) |
252b5132 RH |
10598 | mask |= 1; |
10599 | else | |
10600 | { | |
10601 | as_bad (_("invalid register list")); | |
10602 | break; | |
10603 | } | |
10604 | } | |
10605 | /* The mask is filled in in the opcode table for the | |
10606 | benefit of the disassembler. We remove it before | |
10607 | applying the actual mask. */ | |
10608 | ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6); | |
10609 | ip->insn_opcode |= mask << MIPS16OP_SH_IMM6; | |
10610 | } | |
10611 | continue; | |
10612 | ||
0499d65b TS |
10613 | case 'm': /* Register list for save insn. */ |
10614 | case 'M': /* Register list for restore insn. */ | |
10615 | { | |
10616 | int opcode = 0; | |
10617 | int framesz = 0, seen_framesz = 0; | |
91d6fa6a | 10618 | int nargs = 0, statics = 0, sregs = 0; |
0499d65b TS |
10619 | |
10620 | while (*s != '\0') | |
10621 | { | |
10622 | unsigned int reg1, reg2; | |
10623 | ||
10624 | SKIP_SPACE_TABS (s); | |
10625 | while (*s == ',') | |
10626 | ++s; | |
10627 | SKIP_SPACE_TABS (s); | |
10628 | ||
10629 | my_getExpression (&imm_expr, s); | |
10630 | if (imm_expr.X_op == O_constant) | |
10631 | { | |
10632 | /* Handle the frame size. */ | |
10633 | if (seen_framesz) | |
10634 | { | |
10635 | as_bad (_("more than one frame size in list")); | |
10636 | break; | |
10637 | } | |
10638 | seen_framesz = 1; | |
10639 | framesz = imm_expr.X_add_number; | |
10640 | imm_expr.X_op = O_absent; | |
10641 | s = expr_end; | |
10642 | continue; | |
10643 | } | |
10644 | ||
707bfff6 | 10645 | if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®1)) |
0499d65b TS |
10646 | { |
10647 | as_bad (_("can't parse register list")); | |
10648 | break; | |
10649 | } | |
0499d65b | 10650 | |
707bfff6 TS |
10651 | while (*s == ' ') |
10652 | ++s; | |
10653 | ||
0499d65b TS |
10654 | if (*s != '-') |
10655 | reg2 = reg1; | |
10656 | else | |
10657 | { | |
10658 | ++s; | |
707bfff6 TS |
10659 | if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®2) |
10660 | || reg2 < reg1) | |
0499d65b TS |
10661 | { |
10662 | as_bad (_("can't parse register list")); | |
10663 | break; | |
10664 | } | |
0499d65b TS |
10665 | } |
10666 | ||
10667 | while (reg1 <= reg2) | |
10668 | { | |
10669 | if (reg1 >= 4 && reg1 <= 7) | |
10670 | { | |
3a93f742 | 10671 | if (!seen_framesz) |
0499d65b | 10672 | /* args $a0-$a3 */ |
91d6fa6a | 10673 | nargs |= 1 << (reg1 - 4); |
0499d65b TS |
10674 | else |
10675 | /* statics $a0-$a3 */ | |
10676 | statics |= 1 << (reg1 - 4); | |
10677 | } | |
10678 | else if ((reg1 >= 16 && reg1 <= 23) || reg1 == 30) | |
10679 | { | |
10680 | /* $s0-$s8 */ | |
10681 | sregs |= 1 << ((reg1 == 30) ? 8 : (reg1 - 16)); | |
10682 | } | |
10683 | else if (reg1 == 31) | |
10684 | { | |
10685 | /* Add $ra to insn. */ | |
10686 | opcode |= 0x40; | |
10687 | } | |
10688 | else | |
10689 | { | |
10690 | as_bad (_("unexpected register in list")); | |
10691 | break; | |
10692 | } | |
10693 | if (++reg1 == 24) | |
10694 | reg1 = 30; | |
10695 | } | |
10696 | } | |
10697 | ||
10698 | /* Encode args/statics combination. */ | |
91d6fa6a | 10699 | if (nargs & statics) |
0499d65b | 10700 | as_bad (_("arg/static registers overlap")); |
91d6fa6a | 10701 | else if (nargs == 0xf) |
0499d65b TS |
10702 | /* All $a0-$a3 are args. */ |
10703 | opcode |= MIPS16_ALL_ARGS << 16; | |
10704 | else if (statics == 0xf) | |
10705 | /* All $a0-$a3 are statics. */ | |
10706 | opcode |= MIPS16_ALL_STATICS << 16; | |
10707 | else | |
10708 | { | |
10709 | int narg = 0, nstat = 0; | |
10710 | ||
10711 | /* Count arg registers. */ | |
91d6fa6a | 10712 | while (nargs & 0x1) |
0499d65b | 10713 | { |
91d6fa6a | 10714 | nargs >>= 1; |
0499d65b TS |
10715 | narg++; |
10716 | } | |
91d6fa6a | 10717 | if (nargs != 0) |
0499d65b TS |
10718 | as_bad (_("invalid arg register list")); |
10719 | ||
10720 | /* Count static registers. */ | |
10721 | while (statics & 0x8) | |
10722 | { | |
10723 | statics = (statics << 1) & 0xf; | |
10724 | nstat++; | |
10725 | } | |
10726 | if (statics != 0) | |
10727 | as_bad (_("invalid static register list")); | |
10728 | ||
10729 | /* Encode args/statics. */ | |
10730 | opcode |= ((narg << 2) | nstat) << 16; | |
10731 | } | |
10732 | ||
10733 | /* Encode $s0/$s1. */ | |
10734 | if (sregs & (1 << 0)) /* $s0 */ | |
10735 | opcode |= 0x20; | |
10736 | if (sregs & (1 << 1)) /* $s1 */ | |
10737 | opcode |= 0x10; | |
10738 | sregs >>= 2; | |
10739 | ||
10740 | if (sregs != 0) | |
10741 | { | |
10742 | /* Count regs $s2-$s8. */ | |
10743 | int nsreg = 0; | |
10744 | while (sregs & 1) | |
10745 | { | |
10746 | sregs >>= 1; | |
10747 | nsreg++; | |
10748 | } | |
10749 | if (sregs != 0) | |
10750 | as_bad (_("invalid static register list")); | |
10751 | /* Encode $s2-$s8. */ | |
10752 | opcode |= nsreg << 24; | |
10753 | } | |
10754 | ||
10755 | /* Encode frame size. */ | |
10756 | if (!seen_framesz) | |
10757 | as_bad (_("missing frame size")); | |
10758 | else if ((framesz & 7) != 0 || framesz < 0 | |
10759 | || framesz > 0xff * 8) | |
10760 | as_bad (_("invalid frame size")); | |
10761 | else if (framesz != 128 || (opcode >> 16) != 0) | |
10762 | { | |
10763 | framesz /= 8; | |
10764 | opcode |= (((framesz & 0xf0) << 16) | |
10765 | | (framesz & 0x0f)); | |
10766 | } | |
10767 | ||
10768 | /* Finally build the instruction. */ | |
10769 | if ((opcode >> 16) != 0 || framesz == 0) | |
10770 | { | |
10771 | ip->use_extend = TRUE; | |
10772 | ip->extend = opcode >> 16; | |
10773 | } | |
10774 | ip->insn_opcode |= opcode & 0x7f; | |
10775 | } | |
10776 | continue; | |
10777 | ||
252b5132 RH |
10778 | case 'e': /* extend code */ |
10779 | my_getExpression (&imm_expr, s); | |
10780 | check_absolute_expr (ip, &imm_expr); | |
10781 | if ((unsigned long) imm_expr.X_add_number > 0x7ff) | |
10782 | { | |
10783 | as_warn (_("Invalid value for `%s' (%lu)"), | |
10784 | ip->insn_mo->name, | |
10785 | (unsigned long) imm_expr.X_add_number); | |
10786 | imm_expr.X_add_number &= 0x7ff; | |
10787 | } | |
10788 | ip->insn_opcode |= imm_expr.X_add_number; | |
10789 | imm_expr.X_op = O_absent; | |
10790 | s = expr_end; | |
10791 | continue; | |
10792 | ||
10793 | default: | |
10794 | internalError (); | |
10795 | } | |
10796 | break; | |
10797 | } | |
10798 | ||
10799 | /* Args don't match. */ | |
10800 | if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] && | |
10801 | strcmp (insn->name, insn[1].name) == 0) | |
10802 | { | |
10803 | ++insn; | |
10804 | s = argsstart; | |
10805 | continue; | |
10806 | } | |
10807 | ||
10808 | insn_error = _("illegal operands"); | |
10809 | ||
10810 | return; | |
10811 | } | |
10812 | } | |
10813 | ||
10814 | /* This structure holds information we know about a mips16 immediate | |
10815 | argument type. */ | |
10816 | ||
e972090a NC |
10817 | struct mips16_immed_operand |
10818 | { | |
252b5132 RH |
10819 | /* The type code used in the argument string in the opcode table. */ |
10820 | int type; | |
10821 | /* The number of bits in the short form of the opcode. */ | |
10822 | int nbits; | |
10823 | /* The number of bits in the extended form of the opcode. */ | |
10824 | int extbits; | |
10825 | /* The amount by which the short form is shifted when it is used; | |
10826 | for example, the sw instruction has a shift count of 2. */ | |
10827 | int shift; | |
10828 | /* The amount by which the short form is shifted when it is stored | |
10829 | into the instruction code. */ | |
10830 | int op_shift; | |
10831 | /* Non-zero if the short form is unsigned. */ | |
10832 | int unsp; | |
10833 | /* Non-zero if the extended form is unsigned. */ | |
10834 | int extu; | |
10835 | /* Non-zero if the value is PC relative. */ | |
10836 | int pcrel; | |
10837 | }; | |
10838 | ||
10839 | /* The mips16 immediate operand types. */ | |
10840 | ||
10841 | static const struct mips16_immed_operand mips16_immed_operands[] = | |
10842 | { | |
10843 | { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
10844 | { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
10845 | { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
10846 | { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
10847 | { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 }, | |
10848 | { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
10849 | { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
10850 | { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
10851 | { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
10852 | { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 }, | |
10853 | { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
10854 | { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
10855 | { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
10856 | { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 }, | |
10857 | { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
10858 | { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
10859 | { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
10860 | { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
10861 | { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 }, | |
10862 | { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 }, | |
10863 | { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 } | |
10864 | }; | |
10865 | ||
10866 | #define MIPS16_NUM_IMMED \ | |
10867 | (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0]) | |
10868 | ||
10869 | /* Handle a mips16 instruction with an immediate value. This or's the | |
10870 | small immediate value into *INSN. It sets *USE_EXTEND to indicate | |
10871 | whether an extended value is needed; if one is needed, it sets | |
10872 | *EXTEND to the value. The argument type is TYPE. The value is VAL. | |
10873 | If SMALL is true, an unextended opcode was explicitly requested. | |
10874 | If EXT is true, an extended opcode was explicitly requested. If | |
10875 | WARN is true, warn if EXT does not match reality. */ | |
10876 | ||
10877 | static void | |
17a2f251 TS |
10878 | mips16_immed (char *file, unsigned int line, int type, offsetT val, |
10879 | bfd_boolean warn, bfd_boolean small, bfd_boolean ext, | |
10880 | unsigned long *insn, bfd_boolean *use_extend, | |
10881 | unsigned short *extend) | |
252b5132 | 10882 | { |
3994f87e | 10883 | const struct mips16_immed_operand *op; |
252b5132 | 10884 | int mintiny, maxtiny; |
b34976b6 | 10885 | bfd_boolean needext; |
252b5132 RH |
10886 | |
10887 | op = mips16_immed_operands; | |
10888 | while (op->type != type) | |
10889 | { | |
10890 | ++op; | |
9c2799c2 | 10891 | gas_assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); |
252b5132 RH |
10892 | } |
10893 | ||
10894 | if (op->unsp) | |
10895 | { | |
10896 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
10897 | { | |
10898 | mintiny = 1; | |
10899 | maxtiny = 1 << op->nbits; | |
10900 | } | |
10901 | else | |
10902 | { | |
10903 | mintiny = 0; | |
10904 | maxtiny = (1 << op->nbits) - 1; | |
10905 | } | |
10906 | } | |
10907 | else | |
10908 | { | |
10909 | mintiny = - (1 << (op->nbits - 1)); | |
10910 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
10911 | } | |
10912 | ||
10913 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
10914 | if (type == 'p' || type == 'q') | |
10915 | val /= 2; | |
10916 | ||
10917 | if ((val & ((1 << op->shift) - 1)) != 0 | |
10918 | || val < (mintiny << op->shift) | |
10919 | || val > (maxtiny << op->shift)) | |
b34976b6 | 10920 | needext = TRUE; |
252b5132 | 10921 | else |
b34976b6 | 10922 | needext = FALSE; |
252b5132 RH |
10923 | |
10924 | if (warn && ext && ! needext) | |
beae10d5 KH |
10925 | as_warn_where (file, line, |
10926 | _("extended operand requested but not required")); | |
252b5132 RH |
10927 | if (small && needext) |
10928 | as_bad_where (file, line, _("invalid unextended operand value")); | |
10929 | ||
10930 | if (small || (! ext && ! needext)) | |
10931 | { | |
10932 | int insnval; | |
10933 | ||
b34976b6 | 10934 | *use_extend = FALSE; |
252b5132 RH |
10935 | insnval = ((val >> op->shift) & ((1 << op->nbits) - 1)); |
10936 | insnval <<= op->op_shift; | |
10937 | *insn |= insnval; | |
10938 | } | |
10939 | else | |
10940 | { | |
10941 | long minext, maxext; | |
10942 | int extval; | |
10943 | ||
10944 | if (op->extu) | |
10945 | { | |
10946 | minext = 0; | |
10947 | maxext = (1 << op->extbits) - 1; | |
10948 | } | |
10949 | else | |
10950 | { | |
10951 | minext = - (1 << (op->extbits - 1)); | |
10952 | maxext = (1 << (op->extbits - 1)) - 1; | |
10953 | } | |
10954 | if (val < minext || val > maxext) | |
10955 | as_bad_where (file, line, | |
10956 | _("operand value out of range for instruction")); | |
10957 | ||
b34976b6 | 10958 | *use_extend = TRUE; |
252b5132 RH |
10959 | if (op->extbits == 16) |
10960 | { | |
10961 | extval = ((val >> 11) & 0x1f) | (val & 0x7e0); | |
10962 | val &= 0x1f; | |
10963 | } | |
10964 | else if (op->extbits == 15) | |
10965 | { | |
10966 | extval = ((val >> 11) & 0xf) | (val & 0x7f0); | |
10967 | val &= 0xf; | |
10968 | } | |
10969 | else | |
10970 | { | |
10971 | extval = ((val & 0x1f) << 6) | (val & 0x20); | |
10972 | val = 0; | |
10973 | } | |
10974 | ||
10975 | *extend = (unsigned short) extval; | |
10976 | *insn |= val; | |
10977 | } | |
10978 | } | |
10979 | \f | |
d6f16593 | 10980 | struct percent_op_match |
ad8d3bb3 | 10981 | { |
5e0116d5 RS |
10982 | const char *str; |
10983 | bfd_reloc_code_real_type reloc; | |
d6f16593 MR |
10984 | }; |
10985 | ||
10986 | static const struct percent_op_match mips_percent_op[] = | |
ad8d3bb3 | 10987 | { |
5e0116d5 | 10988 | {"%lo", BFD_RELOC_LO16}, |
ad8d3bb3 | 10989 | #ifdef OBJ_ELF |
5e0116d5 RS |
10990 | {"%call_hi", BFD_RELOC_MIPS_CALL_HI16}, |
10991 | {"%call_lo", BFD_RELOC_MIPS_CALL_LO16}, | |
10992 | {"%call16", BFD_RELOC_MIPS_CALL16}, | |
10993 | {"%got_disp", BFD_RELOC_MIPS_GOT_DISP}, | |
10994 | {"%got_page", BFD_RELOC_MIPS_GOT_PAGE}, | |
10995 | {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST}, | |
10996 | {"%got_hi", BFD_RELOC_MIPS_GOT_HI16}, | |
10997 | {"%got_lo", BFD_RELOC_MIPS_GOT_LO16}, | |
10998 | {"%got", BFD_RELOC_MIPS_GOT16}, | |
10999 | {"%gp_rel", BFD_RELOC_GPREL16}, | |
11000 | {"%half", BFD_RELOC_16}, | |
11001 | {"%highest", BFD_RELOC_MIPS_HIGHEST}, | |
11002 | {"%higher", BFD_RELOC_MIPS_HIGHER}, | |
11003 | {"%neg", BFD_RELOC_MIPS_SUB}, | |
3f98094e DJ |
11004 | {"%tlsgd", BFD_RELOC_MIPS_TLS_GD}, |
11005 | {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM}, | |
11006 | {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16}, | |
11007 | {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16}, | |
11008 | {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16}, | |
11009 | {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16}, | |
11010 | {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL}, | |
ad8d3bb3 | 11011 | #endif |
5e0116d5 | 11012 | {"%hi", BFD_RELOC_HI16_S} |
ad8d3bb3 TS |
11013 | }; |
11014 | ||
d6f16593 MR |
11015 | static const struct percent_op_match mips16_percent_op[] = |
11016 | { | |
11017 | {"%lo", BFD_RELOC_MIPS16_LO16}, | |
11018 | {"%gprel", BFD_RELOC_MIPS16_GPREL}, | |
738e5348 RS |
11019 | {"%got", BFD_RELOC_MIPS16_GOT16}, |
11020 | {"%call16", BFD_RELOC_MIPS16_CALL16}, | |
d6f16593 MR |
11021 | {"%hi", BFD_RELOC_MIPS16_HI16_S} |
11022 | }; | |
11023 | ||
252b5132 | 11024 | |
5e0116d5 RS |
11025 | /* Return true if *STR points to a relocation operator. When returning true, |
11026 | move *STR over the operator and store its relocation code in *RELOC. | |
11027 | Leave both *STR and *RELOC alone when returning false. */ | |
11028 | ||
11029 | static bfd_boolean | |
17a2f251 | 11030 | parse_relocation (char **str, bfd_reloc_code_real_type *reloc) |
252b5132 | 11031 | { |
d6f16593 MR |
11032 | const struct percent_op_match *percent_op; |
11033 | size_t limit, i; | |
11034 | ||
11035 | if (mips_opts.mips16) | |
11036 | { | |
11037 | percent_op = mips16_percent_op; | |
11038 | limit = ARRAY_SIZE (mips16_percent_op); | |
11039 | } | |
11040 | else | |
11041 | { | |
11042 | percent_op = mips_percent_op; | |
11043 | limit = ARRAY_SIZE (mips_percent_op); | |
11044 | } | |
76b3015f | 11045 | |
d6f16593 | 11046 | for (i = 0; i < limit; i++) |
5e0116d5 | 11047 | if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0) |
394f9b3a | 11048 | { |
3f98094e DJ |
11049 | int len = strlen (percent_op[i].str); |
11050 | ||
11051 | if (!ISSPACE ((*str)[len]) && (*str)[len] != '(') | |
11052 | continue; | |
11053 | ||
5e0116d5 RS |
11054 | *str += strlen (percent_op[i].str); |
11055 | *reloc = percent_op[i].reloc; | |
394f9b3a | 11056 | |
5e0116d5 RS |
11057 | /* Check whether the output BFD supports this relocation. |
11058 | If not, issue an error and fall back on something safe. */ | |
11059 | if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc)) | |
394f9b3a | 11060 | { |
20203fb9 | 11061 | as_bad (_("relocation %s isn't supported by the current ABI"), |
5e0116d5 | 11062 | percent_op[i].str); |
01a3f561 | 11063 | *reloc = BFD_RELOC_UNUSED; |
394f9b3a | 11064 | } |
5e0116d5 | 11065 | return TRUE; |
394f9b3a | 11066 | } |
5e0116d5 | 11067 | return FALSE; |
394f9b3a | 11068 | } |
ad8d3bb3 | 11069 | |
ad8d3bb3 | 11070 | |
5e0116d5 RS |
11071 | /* Parse string STR as a 16-bit relocatable operand. Store the |
11072 | expression in *EP and the relocations in the array starting | |
11073 | at RELOC. Return the number of relocation operators used. | |
ad8d3bb3 | 11074 | |
01a3f561 | 11075 | On exit, EXPR_END points to the first character after the expression. */ |
ad8d3bb3 | 11076 | |
5e0116d5 | 11077 | static size_t |
17a2f251 TS |
11078 | my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc, |
11079 | char *str) | |
ad8d3bb3 | 11080 | { |
5e0116d5 RS |
11081 | bfd_reloc_code_real_type reversed_reloc[3]; |
11082 | size_t reloc_index, i; | |
09b8f35a RS |
11083 | int crux_depth, str_depth; |
11084 | char *crux; | |
5e0116d5 RS |
11085 | |
11086 | /* Search for the start of the main expression, recoding relocations | |
09b8f35a RS |
11087 | in REVERSED_RELOC. End the loop with CRUX pointing to the start |
11088 | of the main expression and with CRUX_DEPTH containing the number | |
11089 | of open brackets at that point. */ | |
11090 | reloc_index = -1; | |
11091 | str_depth = 0; | |
11092 | do | |
fb1b3232 | 11093 | { |
09b8f35a RS |
11094 | reloc_index++; |
11095 | crux = str; | |
11096 | crux_depth = str_depth; | |
11097 | ||
11098 | /* Skip over whitespace and brackets, keeping count of the number | |
11099 | of brackets. */ | |
11100 | while (*str == ' ' || *str == '\t' || *str == '(') | |
11101 | if (*str++ == '(') | |
11102 | str_depth++; | |
5e0116d5 | 11103 | } |
09b8f35a RS |
11104 | while (*str == '%' |
11105 | && reloc_index < (HAVE_NEWABI ? 3 : 1) | |
11106 | && parse_relocation (&str, &reversed_reloc[reloc_index])); | |
ad8d3bb3 | 11107 | |
09b8f35a | 11108 | my_getExpression (ep, crux); |
5e0116d5 | 11109 | str = expr_end; |
394f9b3a | 11110 | |
5e0116d5 | 11111 | /* Match every open bracket. */ |
09b8f35a | 11112 | while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t')) |
5e0116d5 | 11113 | if (*str++ == ')') |
09b8f35a | 11114 | crux_depth--; |
394f9b3a | 11115 | |
09b8f35a | 11116 | if (crux_depth > 0) |
20203fb9 | 11117 | as_bad (_("unclosed '('")); |
394f9b3a | 11118 | |
5e0116d5 | 11119 | expr_end = str; |
252b5132 | 11120 | |
01a3f561 | 11121 | if (reloc_index != 0) |
64bdfcaf RS |
11122 | { |
11123 | prev_reloc_op_frag = frag_now; | |
11124 | for (i = 0; i < reloc_index; i++) | |
11125 | reloc[i] = reversed_reloc[reloc_index - 1 - i]; | |
11126 | } | |
fb1b3232 | 11127 | |
5e0116d5 | 11128 | return reloc_index; |
252b5132 RH |
11129 | } |
11130 | ||
11131 | static void | |
17a2f251 | 11132 | my_getExpression (expressionS *ep, char *str) |
252b5132 RH |
11133 | { |
11134 | char *save_in; | |
98aa84af | 11135 | valueT val; |
252b5132 RH |
11136 | |
11137 | save_in = input_line_pointer; | |
11138 | input_line_pointer = str; | |
11139 | expression (ep); | |
11140 | expr_end = input_line_pointer; | |
11141 | input_line_pointer = save_in; | |
11142 | ||
11143 | /* If we are in mips16 mode, and this is an expression based on `.', | |
11144 | then we bump the value of the symbol by 1 since that is how other | |
11145 | text symbols are handled. We don't bother to handle complex | |
11146 | expressions, just `.' plus or minus a constant. */ | |
11147 | if (mips_opts.mips16 | |
11148 | && ep->X_op == O_symbol | |
11149 | && strcmp (S_GET_NAME (ep->X_add_symbol), FAKE_LABEL_NAME) == 0 | |
11150 | && S_GET_SEGMENT (ep->X_add_symbol) == now_seg | |
49309057 ILT |
11151 | && symbol_get_frag (ep->X_add_symbol) == frag_now |
11152 | && symbol_constant_p (ep->X_add_symbol) | |
98aa84af AM |
11153 | && (val = S_GET_VALUE (ep->X_add_symbol)) == frag_now_fix ()) |
11154 | S_SET_VALUE (ep->X_add_symbol, val + 1); | |
252b5132 RH |
11155 | } |
11156 | ||
252b5132 | 11157 | char * |
17a2f251 | 11158 | md_atof (int type, char *litP, int *sizeP) |
252b5132 | 11159 | { |
499ac353 | 11160 | return ieee_md_atof (type, litP, sizeP, target_big_endian); |
252b5132 RH |
11161 | } |
11162 | ||
11163 | void | |
17a2f251 | 11164 | md_number_to_chars (char *buf, valueT val, int n) |
252b5132 RH |
11165 | { |
11166 | if (target_big_endian) | |
11167 | number_to_chars_bigendian (buf, val, n); | |
11168 | else | |
11169 | number_to_chars_littleendian (buf, val, n); | |
11170 | } | |
11171 | \f | |
ae948b86 | 11172 | #ifdef OBJ_ELF |
e013f690 TS |
11173 | static int support_64bit_objects(void) |
11174 | { | |
11175 | const char **list, **l; | |
aa3d8fdf | 11176 | int yes; |
e013f690 TS |
11177 | |
11178 | list = bfd_target_list (); | |
11179 | for (l = list; *l != NULL; l++) | |
11180 | #ifdef TE_TMIPS | |
11181 | /* This is traditional mips */ | |
11182 | if (strcmp (*l, "elf64-tradbigmips") == 0 | |
11183 | || strcmp (*l, "elf64-tradlittlemips") == 0) | |
11184 | #else | |
11185 | if (strcmp (*l, "elf64-bigmips") == 0 | |
11186 | || strcmp (*l, "elf64-littlemips") == 0) | |
11187 | #endif | |
11188 | break; | |
aa3d8fdf | 11189 | yes = (*l != NULL); |
e013f690 | 11190 | free (list); |
aa3d8fdf | 11191 | return yes; |
e013f690 | 11192 | } |
ae948b86 | 11193 | #endif /* OBJ_ELF */ |
e013f690 | 11194 | |
78849248 | 11195 | const char *md_shortopts = "O::g::G:"; |
252b5132 | 11196 | |
23fce1e3 NC |
11197 | enum options |
11198 | { | |
11199 | OPTION_MARCH = OPTION_MD_BASE, | |
11200 | OPTION_MTUNE, | |
11201 | OPTION_MIPS1, | |
11202 | OPTION_MIPS2, | |
11203 | OPTION_MIPS3, | |
11204 | OPTION_MIPS4, | |
11205 | OPTION_MIPS5, | |
11206 | OPTION_MIPS32, | |
11207 | OPTION_MIPS64, | |
11208 | OPTION_MIPS32R2, | |
11209 | OPTION_MIPS64R2, | |
11210 | OPTION_MIPS16, | |
11211 | OPTION_NO_MIPS16, | |
11212 | OPTION_MIPS3D, | |
11213 | OPTION_NO_MIPS3D, | |
11214 | OPTION_MDMX, | |
11215 | OPTION_NO_MDMX, | |
11216 | OPTION_DSP, | |
11217 | OPTION_NO_DSP, | |
11218 | OPTION_MT, | |
11219 | OPTION_NO_MT, | |
11220 | OPTION_SMARTMIPS, | |
11221 | OPTION_NO_SMARTMIPS, | |
11222 | OPTION_DSPR2, | |
11223 | OPTION_NO_DSPR2, | |
11224 | OPTION_COMPAT_ARCH_BASE, | |
11225 | OPTION_M4650, | |
11226 | OPTION_NO_M4650, | |
11227 | OPTION_M4010, | |
11228 | OPTION_NO_M4010, | |
11229 | OPTION_M4100, | |
11230 | OPTION_NO_M4100, | |
11231 | OPTION_M3900, | |
11232 | OPTION_NO_M3900, | |
11233 | OPTION_M7000_HILO_FIX, | |
6a32d874 CM |
11234 | OPTION_MNO_7000_HILO_FIX, |
11235 | OPTION_FIX_24K, | |
11236 | OPTION_NO_FIX_24K, | |
c67a084a NC |
11237 | OPTION_FIX_LOONGSON2F_JUMP, |
11238 | OPTION_NO_FIX_LOONGSON2F_JUMP, | |
11239 | OPTION_FIX_LOONGSON2F_NOP, | |
11240 | OPTION_NO_FIX_LOONGSON2F_NOP, | |
23fce1e3 NC |
11241 | OPTION_FIX_VR4120, |
11242 | OPTION_NO_FIX_VR4120, | |
11243 | OPTION_FIX_VR4130, | |
11244 | OPTION_NO_FIX_VR4130, | |
d954098f DD |
11245 | OPTION_FIX_CN63XXP1, |
11246 | OPTION_NO_FIX_CN63XXP1, | |
23fce1e3 NC |
11247 | OPTION_TRAP, |
11248 | OPTION_BREAK, | |
11249 | OPTION_EB, | |
11250 | OPTION_EL, | |
11251 | OPTION_FP32, | |
11252 | OPTION_GP32, | |
11253 | OPTION_CONSTRUCT_FLOATS, | |
11254 | OPTION_NO_CONSTRUCT_FLOATS, | |
11255 | OPTION_FP64, | |
11256 | OPTION_GP64, | |
11257 | OPTION_RELAX_BRANCH, | |
11258 | OPTION_NO_RELAX_BRANCH, | |
11259 | OPTION_MSHARED, | |
11260 | OPTION_MNO_SHARED, | |
11261 | OPTION_MSYM32, | |
11262 | OPTION_MNO_SYM32, | |
11263 | OPTION_SOFT_FLOAT, | |
11264 | OPTION_HARD_FLOAT, | |
11265 | OPTION_SINGLE_FLOAT, | |
11266 | OPTION_DOUBLE_FLOAT, | |
11267 | OPTION_32, | |
11268 | #ifdef OBJ_ELF | |
11269 | OPTION_CALL_SHARED, | |
11270 | OPTION_CALL_NONPIC, | |
11271 | OPTION_NON_SHARED, | |
11272 | OPTION_XGOT, | |
11273 | OPTION_MABI, | |
11274 | OPTION_N32, | |
11275 | OPTION_64, | |
11276 | OPTION_MDEBUG, | |
11277 | OPTION_NO_MDEBUG, | |
11278 | OPTION_PDR, | |
11279 | OPTION_NO_PDR, | |
11280 | OPTION_MVXWORKS_PIC, | |
11281 | #endif /* OBJ_ELF */ | |
11282 | OPTION_END_OF_ENUM | |
11283 | }; | |
11284 | ||
e972090a NC |
11285 | struct option md_longopts[] = |
11286 | { | |
f9b4148d | 11287 | /* Options which specify architecture. */ |
f9b4148d | 11288 | {"march", required_argument, NULL, OPTION_MARCH}, |
f9b4148d | 11289 | {"mtune", required_argument, NULL, OPTION_MTUNE}, |
252b5132 RH |
11290 | {"mips0", no_argument, NULL, OPTION_MIPS1}, |
11291 | {"mips1", no_argument, NULL, OPTION_MIPS1}, | |
252b5132 | 11292 | {"mips2", no_argument, NULL, OPTION_MIPS2}, |
252b5132 | 11293 | {"mips3", no_argument, NULL, OPTION_MIPS3}, |
252b5132 | 11294 | {"mips4", no_argument, NULL, OPTION_MIPS4}, |
ae948b86 | 11295 | {"mips5", no_argument, NULL, OPTION_MIPS5}, |
ae948b86 | 11296 | {"mips32", no_argument, NULL, OPTION_MIPS32}, |
ae948b86 | 11297 | {"mips64", no_argument, NULL, OPTION_MIPS64}, |
f9b4148d | 11298 | {"mips32r2", no_argument, NULL, OPTION_MIPS32R2}, |
5f74bc13 | 11299 | {"mips64r2", no_argument, NULL, OPTION_MIPS64R2}, |
f9b4148d CD |
11300 | |
11301 | /* Options which specify Application Specific Extensions (ASEs). */ | |
f9b4148d | 11302 | {"mips16", no_argument, NULL, OPTION_MIPS16}, |
f9b4148d | 11303 | {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16}, |
f9b4148d | 11304 | {"mips3d", no_argument, NULL, OPTION_MIPS3D}, |
f9b4148d | 11305 | {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D}, |
f9b4148d | 11306 | {"mdmx", no_argument, NULL, OPTION_MDMX}, |
f9b4148d | 11307 | {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX}, |
74cd071d | 11308 | {"mdsp", no_argument, NULL, OPTION_DSP}, |
74cd071d | 11309 | {"mno-dsp", no_argument, NULL, OPTION_NO_DSP}, |
ef2e4d86 | 11310 | {"mmt", no_argument, NULL, OPTION_MT}, |
ef2e4d86 | 11311 | {"mno-mt", no_argument, NULL, OPTION_NO_MT}, |
e16bfa71 | 11312 | {"msmartmips", no_argument, NULL, OPTION_SMARTMIPS}, |
e16bfa71 | 11313 | {"mno-smartmips", no_argument, NULL, OPTION_NO_SMARTMIPS}, |
8b082fb1 | 11314 | {"mdspr2", no_argument, NULL, OPTION_DSPR2}, |
8b082fb1 | 11315 | {"mno-dspr2", no_argument, NULL, OPTION_NO_DSPR2}, |
f9b4148d CD |
11316 | |
11317 | /* Old-style architecture options. Don't add more of these. */ | |
f9b4148d | 11318 | {"m4650", no_argument, NULL, OPTION_M4650}, |
f9b4148d | 11319 | {"no-m4650", no_argument, NULL, OPTION_NO_M4650}, |
f9b4148d | 11320 | {"m4010", no_argument, NULL, OPTION_M4010}, |
f9b4148d | 11321 | {"no-m4010", no_argument, NULL, OPTION_NO_M4010}, |
f9b4148d | 11322 | {"m4100", no_argument, NULL, OPTION_M4100}, |
f9b4148d | 11323 | {"no-m4100", no_argument, NULL, OPTION_NO_M4100}, |
f9b4148d | 11324 | {"m3900", no_argument, NULL, OPTION_M3900}, |
f9b4148d CD |
11325 | {"no-m3900", no_argument, NULL, OPTION_NO_M3900}, |
11326 | ||
11327 | /* Options which enable bug fixes. */ | |
f9b4148d | 11328 | {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX}, |
f9b4148d CD |
11329 | {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, |
11330 | {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, | |
c67a084a NC |
11331 | {"mfix-loongson2f-jump", no_argument, NULL, OPTION_FIX_LOONGSON2F_JUMP}, |
11332 | {"mno-fix-loongson2f-jump", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_JUMP}, | |
11333 | {"mfix-loongson2f-nop", no_argument, NULL, OPTION_FIX_LOONGSON2F_NOP}, | |
11334 | {"mno-fix-loongson2f-nop", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_NOP}, | |
d766e8ec RS |
11335 | {"mfix-vr4120", no_argument, NULL, OPTION_FIX_VR4120}, |
11336 | {"mno-fix-vr4120", no_argument, NULL, OPTION_NO_FIX_VR4120}, | |
7d8e00cf RS |
11337 | {"mfix-vr4130", no_argument, NULL, OPTION_FIX_VR4130}, |
11338 | {"mno-fix-vr4130", no_argument, NULL, OPTION_NO_FIX_VR4130}, | |
6a32d874 CM |
11339 | {"mfix-24k", no_argument, NULL, OPTION_FIX_24K}, |
11340 | {"mno-fix-24k", no_argument, NULL, OPTION_NO_FIX_24K}, | |
d954098f DD |
11341 | {"mfix-cn63xxp1", no_argument, NULL, OPTION_FIX_CN63XXP1}, |
11342 | {"mno-fix-cn63xxp1", no_argument, NULL, OPTION_NO_FIX_CN63XXP1}, | |
f9b4148d CD |
11343 | |
11344 | /* Miscellaneous options. */ | |
252b5132 RH |
11345 | {"trap", no_argument, NULL, OPTION_TRAP}, |
11346 | {"no-break", no_argument, NULL, OPTION_TRAP}, | |
252b5132 RH |
11347 | {"break", no_argument, NULL, OPTION_BREAK}, |
11348 | {"no-trap", no_argument, NULL, OPTION_BREAK}, | |
252b5132 | 11349 | {"EB", no_argument, NULL, OPTION_EB}, |
252b5132 | 11350 | {"EL", no_argument, NULL, OPTION_EL}, |
ae948b86 | 11351 | {"mfp32", no_argument, NULL, OPTION_FP32}, |
c97ef257 | 11352 | {"mgp32", no_argument, NULL, OPTION_GP32}, |
119d663a | 11353 | {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS}, |
119d663a | 11354 | {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS}, |
316f5878 | 11355 | {"mfp64", no_argument, NULL, OPTION_FP64}, |
ae948b86 | 11356 | {"mgp64", no_argument, NULL, OPTION_GP64}, |
4a6a3df4 AO |
11357 | {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH}, |
11358 | {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH}, | |
aa6975fb ILT |
11359 | {"mshared", no_argument, NULL, OPTION_MSHARED}, |
11360 | {"mno-shared", no_argument, NULL, OPTION_MNO_SHARED}, | |
aed1a261 RS |
11361 | {"msym32", no_argument, NULL, OPTION_MSYM32}, |
11362 | {"mno-sym32", no_argument, NULL, OPTION_MNO_SYM32}, | |
037b32b9 AN |
11363 | {"msoft-float", no_argument, NULL, OPTION_SOFT_FLOAT}, |
11364 | {"mhard-float", no_argument, NULL, OPTION_HARD_FLOAT}, | |
037b32b9 AN |
11365 | {"msingle-float", no_argument, NULL, OPTION_SINGLE_FLOAT}, |
11366 | {"mdouble-float", no_argument, NULL, OPTION_DOUBLE_FLOAT}, | |
23fce1e3 NC |
11367 | |
11368 | /* Strictly speaking this next option is ELF specific, | |
11369 | but we allow it for other ports as well in order to | |
11370 | make testing easier. */ | |
11371 | {"32", no_argument, NULL, OPTION_32}, | |
037b32b9 | 11372 | |
f9b4148d | 11373 | /* ELF-specific options. */ |
156c2f8b | 11374 | #ifdef OBJ_ELF |
156c2f8b NC |
11375 | {"KPIC", no_argument, NULL, OPTION_CALL_SHARED}, |
11376 | {"call_shared", no_argument, NULL, OPTION_CALL_SHARED}, | |
861fb55a | 11377 | {"call_nonpic", no_argument, NULL, OPTION_CALL_NONPIC}, |
156c2f8b NC |
11378 | {"non_shared", no_argument, NULL, OPTION_NON_SHARED}, |
11379 | {"xgot", no_argument, NULL, OPTION_XGOT}, | |
ae948b86 | 11380 | {"mabi", required_argument, NULL, OPTION_MABI}, |
e013f690 | 11381 | {"n32", no_argument, NULL, OPTION_N32}, |
156c2f8b | 11382 | {"64", no_argument, NULL, OPTION_64}, |
ecb4347a | 11383 | {"mdebug", no_argument, NULL, OPTION_MDEBUG}, |
ecb4347a | 11384 | {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG}, |
dcd410fe | 11385 | {"mpdr", no_argument, NULL, OPTION_PDR}, |
dcd410fe | 11386 | {"mno-pdr", no_argument, NULL, OPTION_NO_PDR}, |
0a44bf69 | 11387 | {"mvxworks-pic", no_argument, NULL, OPTION_MVXWORKS_PIC}, |
ae948b86 | 11388 | #endif /* OBJ_ELF */ |
f9b4148d | 11389 | |
252b5132 RH |
11390 | {NULL, no_argument, NULL, 0} |
11391 | }; | |
156c2f8b | 11392 | size_t md_longopts_size = sizeof (md_longopts); |
252b5132 | 11393 | |
316f5878 RS |
11394 | /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to |
11395 | NEW_VALUE. Warn if another value was already specified. Note: | |
11396 | we have to defer parsing the -march and -mtune arguments in order | |
11397 | to handle 'from-abi' correctly, since the ABI might be specified | |
11398 | in a later argument. */ | |
11399 | ||
11400 | static void | |
17a2f251 | 11401 | mips_set_option_string (const char **string_ptr, const char *new_value) |
316f5878 RS |
11402 | { |
11403 | if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0) | |
11404 | as_warn (_("A different %s was already specified, is now %s"), | |
11405 | string_ptr == &mips_arch_string ? "-march" : "-mtune", | |
11406 | new_value); | |
11407 | ||
11408 | *string_ptr = new_value; | |
11409 | } | |
11410 | ||
252b5132 | 11411 | int |
17a2f251 | 11412 | md_parse_option (int c, char *arg) |
252b5132 RH |
11413 | { |
11414 | switch (c) | |
11415 | { | |
119d663a NC |
11416 | case OPTION_CONSTRUCT_FLOATS: |
11417 | mips_disable_float_construction = 0; | |
11418 | break; | |
bdaaa2e1 | 11419 | |
119d663a NC |
11420 | case OPTION_NO_CONSTRUCT_FLOATS: |
11421 | mips_disable_float_construction = 1; | |
11422 | break; | |
bdaaa2e1 | 11423 | |
252b5132 RH |
11424 | case OPTION_TRAP: |
11425 | mips_trap = 1; | |
11426 | break; | |
11427 | ||
11428 | case OPTION_BREAK: | |
11429 | mips_trap = 0; | |
11430 | break; | |
11431 | ||
11432 | case OPTION_EB: | |
11433 | target_big_endian = 1; | |
11434 | break; | |
11435 | ||
11436 | case OPTION_EL: | |
11437 | target_big_endian = 0; | |
11438 | break; | |
11439 | ||
11440 | case 'O': | |
4ffff32f TS |
11441 | if (arg == NULL) |
11442 | mips_optimize = 1; | |
11443 | else if (arg[0] == '0') | |
11444 | mips_optimize = 0; | |
11445 | else if (arg[0] == '1') | |
252b5132 RH |
11446 | mips_optimize = 1; |
11447 | else | |
11448 | mips_optimize = 2; | |
11449 | break; | |
11450 | ||
11451 | case 'g': | |
11452 | if (arg == NULL) | |
11453 | mips_debug = 2; | |
11454 | else | |
11455 | mips_debug = atoi (arg); | |
252b5132 RH |
11456 | break; |
11457 | ||
11458 | case OPTION_MIPS1: | |
316f5878 | 11459 | file_mips_isa = ISA_MIPS1; |
252b5132 RH |
11460 | break; |
11461 | ||
11462 | case OPTION_MIPS2: | |
316f5878 | 11463 | file_mips_isa = ISA_MIPS2; |
252b5132 RH |
11464 | break; |
11465 | ||
11466 | case OPTION_MIPS3: | |
316f5878 | 11467 | file_mips_isa = ISA_MIPS3; |
252b5132 RH |
11468 | break; |
11469 | ||
11470 | case OPTION_MIPS4: | |
316f5878 | 11471 | file_mips_isa = ISA_MIPS4; |
e7af610e NC |
11472 | break; |
11473 | ||
84ea6cf2 | 11474 | case OPTION_MIPS5: |
316f5878 | 11475 | file_mips_isa = ISA_MIPS5; |
84ea6cf2 NC |
11476 | break; |
11477 | ||
e7af610e | 11478 | case OPTION_MIPS32: |
316f5878 | 11479 | file_mips_isa = ISA_MIPS32; |
252b5132 RH |
11480 | break; |
11481 | ||
af7ee8bf CD |
11482 | case OPTION_MIPS32R2: |
11483 | file_mips_isa = ISA_MIPS32R2; | |
11484 | break; | |
11485 | ||
5f74bc13 CD |
11486 | case OPTION_MIPS64R2: |
11487 | file_mips_isa = ISA_MIPS64R2; | |
11488 | break; | |
11489 | ||
84ea6cf2 | 11490 | case OPTION_MIPS64: |
316f5878 | 11491 | file_mips_isa = ISA_MIPS64; |
84ea6cf2 NC |
11492 | break; |
11493 | ||
ec68c924 | 11494 | case OPTION_MTUNE: |
316f5878 RS |
11495 | mips_set_option_string (&mips_tune_string, arg); |
11496 | break; | |
ec68c924 | 11497 | |
316f5878 RS |
11498 | case OPTION_MARCH: |
11499 | mips_set_option_string (&mips_arch_string, arg); | |
252b5132 RH |
11500 | break; |
11501 | ||
11502 | case OPTION_M4650: | |
316f5878 RS |
11503 | mips_set_option_string (&mips_arch_string, "4650"); |
11504 | mips_set_option_string (&mips_tune_string, "4650"); | |
252b5132 RH |
11505 | break; |
11506 | ||
11507 | case OPTION_NO_M4650: | |
11508 | break; | |
11509 | ||
11510 | case OPTION_M4010: | |
316f5878 RS |
11511 | mips_set_option_string (&mips_arch_string, "4010"); |
11512 | mips_set_option_string (&mips_tune_string, "4010"); | |
252b5132 RH |
11513 | break; |
11514 | ||
11515 | case OPTION_NO_M4010: | |
11516 | break; | |
11517 | ||
11518 | case OPTION_M4100: | |
316f5878 RS |
11519 | mips_set_option_string (&mips_arch_string, "4100"); |
11520 | mips_set_option_string (&mips_tune_string, "4100"); | |
252b5132 RH |
11521 | break; |
11522 | ||
11523 | case OPTION_NO_M4100: | |
11524 | break; | |
11525 | ||
252b5132 | 11526 | case OPTION_M3900: |
316f5878 RS |
11527 | mips_set_option_string (&mips_arch_string, "3900"); |
11528 | mips_set_option_string (&mips_tune_string, "3900"); | |
252b5132 | 11529 | break; |
bdaaa2e1 | 11530 | |
252b5132 RH |
11531 | case OPTION_NO_M3900: |
11532 | break; | |
11533 | ||
deec1734 CD |
11534 | case OPTION_MDMX: |
11535 | mips_opts.ase_mdmx = 1; | |
11536 | break; | |
11537 | ||
11538 | case OPTION_NO_MDMX: | |
11539 | mips_opts.ase_mdmx = 0; | |
11540 | break; | |
11541 | ||
74cd071d CF |
11542 | case OPTION_DSP: |
11543 | mips_opts.ase_dsp = 1; | |
8b082fb1 | 11544 | mips_opts.ase_dspr2 = 0; |
74cd071d CF |
11545 | break; |
11546 | ||
11547 | case OPTION_NO_DSP: | |
8b082fb1 TS |
11548 | mips_opts.ase_dsp = 0; |
11549 | mips_opts.ase_dspr2 = 0; | |
11550 | break; | |
11551 | ||
11552 | case OPTION_DSPR2: | |
11553 | mips_opts.ase_dspr2 = 1; | |
11554 | mips_opts.ase_dsp = 1; | |
11555 | break; | |
11556 | ||
11557 | case OPTION_NO_DSPR2: | |
11558 | mips_opts.ase_dspr2 = 0; | |
74cd071d CF |
11559 | mips_opts.ase_dsp = 0; |
11560 | break; | |
11561 | ||
ef2e4d86 CF |
11562 | case OPTION_MT: |
11563 | mips_opts.ase_mt = 1; | |
11564 | break; | |
11565 | ||
11566 | case OPTION_NO_MT: | |
11567 | mips_opts.ase_mt = 0; | |
11568 | break; | |
11569 | ||
252b5132 RH |
11570 | case OPTION_MIPS16: |
11571 | mips_opts.mips16 = 1; | |
7d10b47d | 11572 | mips_no_prev_insn (); |
252b5132 RH |
11573 | break; |
11574 | ||
11575 | case OPTION_NO_MIPS16: | |
11576 | mips_opts.mips16 = 0; | |
7d10b47d | 11577 | mips_no_prev_insn (); |
252b5132 RH |
11578 | break; |
11579 | ||
1f25f5d3 CD |
11580 | case OPTION_MIPS3D: |
11581 | mips_opts.ase_mips3d = 1; | |
11582 | break; | |
11583 | ||
11584 | case OPTION_NO_MIPS3D: | |
11585 | mips_opts.ase_mips3d = 0; | |
11586 | break; | |
11587 | ||
e16bfa71 TS |
11588 | case OPTION_SMARTMIPS: |
11589 | mips_opts.ase_smartmips = 1; | |
11590 | break; | |
11591 | ||
11592 | case OPTION_NO_SMARTMIPS: | |
11593 | mips_opts.ase_smartmips = 0; | |
11594 | break; | |
11595 | ||
6a32d874 CM |
11596 | case OPTION_FIX_24K: |
11597 | mips_fix_24k = 1; | |
11598 | break; | |
11599 | ||
11600 | case OPTION_NO_FIX_24K: | |
11601 | mips_fix_24k = 0; | |
11602 | break; | |
11603 | ||
c67a084a NC |
11604 | case OPTION_FIX_LOONGSON2F_JUMP: |
11605 | mips_fix_loongson2f_jump = TRUE; | |
11606 | break; | |
11607 | ||
11608 | case OPTION_NO_FIX_LOONGSON2F_JUMP: | |
11609 | mips_fix_loongson2f_jump = FALSE; | |
11610 | break; | |
11611 | ||
11612 | case OPTION_FIX_LOONGSON2F_NOP: | |
11613 | mips_fix_loongson2f_nop = TRUE; | |
11614 | break; | |
11615 | ||
11616 | case OPTION_NO_FIX_LOONGSON2F_NOP: | |
11617 | mips_fix_loongson2f_nop = FALSE; | |
11618 | break; | |
11619 | ||
d766e8ec RS |
11620 | case OPTION_FIX_VR4120: |
11621 | mips_fix_vr4120 = 1; | |
60b63b72 RS |
11622 | break; |
11623 | ||
d766e8ec RS |
11624 | case OPTION_NO_FIX_VR4120: |
11625 | mips_fix_vr4120 = 0; | |
60b63b72 RS |
11626 | break; |
11627 | ||
7d8e00cf RS |
11628 | case OPTION_FIX_VR4130: |
11629 | mips_fix_vr4130 = 1; | |
11630 | break; | |
11631 | ||
11632 | case OPTION_NO_FIX_VR4130: | |
11633 | mips_fix_vr4130 = 0; | |
11634 | break; | |
11635 | ||
d954098f DD |
11636 | case OPTION_FIX_CN63XXP1: |
11637 | mips_fix_cn63xxp1 = TRUE; | |
11638 | break; | |
11639 | ||
11640 | case OPTION_NO_FIX_CN63XXP1: | |
11641 | mips_fix_cn63xxp1 = FALSE; | |
11642 | break; | |
11643 | ||
4a6a3df4 AO |
11644 | case OPTION_RELAX_BRANCH: |
11645 | mips_relax_branch = 1; | |
11646 | break; | |
11647 | ||
11648 | case OPTION_NO_RELAX_BRANCH: | |
11649 | mips_relax_branch = 0; | |
11650 | break; | |
11651 | ||
aa6975fb ILT |
11652 | case OPTION_MSHARED: |
11653 | mips_in_shared = TRUE; | |
11654 | break; | |
11655 | ||
11656 | case OPTION_MNO_SHARED: | |
11657 | mips_in_shared = FALSE; | |
11658 | break; | |
11659 | ||
aed1a261 RS |
11660 | case OPTION_MSYM32: |
11661 | mips_opts.sym32 = TRUE; | |
11662 | break; | |
11663 | ||
11664 | case OPTION_MNO_SYM32: | |
11665 | mips_opts.sym32 = FALSE; | |
11666 | break; | |
11667 | ||
0f074f60 | 11668 | #ifdef OBJ_ELF |
252b5132 RH |
11669 | /* When generating ELF code, we permit -KPIC and -call_shared to |
11670 | select SVR4_PIC, and -non_shared to select no PIC. This is | |
11671 | intended to be compatible with Irix 5. */ | |
11672 | case OPTION_CALL_SHARED: | |
f43abd2b | 11673 | if (!IS_ELF) |
252b5132 RH |
11674 | { |
11675 | as_bad (_("-call_shared is supported only for ELF format")); | |
11676 | return 0; | |
11677 | } | |
11678 | mips_pic = SVR4_PIC; | |
143d77c5 | 11679 | mips_abicalls = TRUE; |
252b5132 RH |
11680 | break; |
11681 | ||
861fb55a DJ |
11682 | case OPTION_CALL_NONPIC: |
11683 | if (!IS_ELF) | |
11684 | { | |
11685 | as_bad (_("-call_nonpic is supported only for ELF format")); | |
11686 | return 0; | |
11687 | } | |
11688 | mips_pic = NO_PIC; | |
11689 | mips_abicalls = TRUE; | |
11690 | break; | |
11691 | ||
252b5132 | 11692 | case OPTION_NON_SHARED: |
f43abd2b | 11693 | if (!IS_ELF) |
252b5132 RH |
11694 | { |
11695 | as_bad (_("-non_shared is supported only for ELF format")); | |
11696 | return 0; | |
11697 | } | |
11698 | mips_pic = NO_PIC; | |
143d77c5 | 11699 | mips_abicalls = FALSE; |
252b5132 RH |
11700 | break; |
11701 | ||
44075ae2 TS |
11702 | /* The -xgot option tells the assembler to use 32 bit offsets |
11703 | when accessing the got in SVR4_PIC mode. It is for Irix | |
252b5132 RH |
11704 | compatibility. */ |
11705 | case OPTION_XGOT: | |
11706 | mips_big_got = 1; | |
11707 | break; | |
0f074f60 | 11708 | #endif /* OBJ_ELF */ |
252b5132 RH |
11709 | |
11710 | case 'G': | |
6caf9ef4 TS |
11711 | g_switch_value = atoi (arg); |
11712 | g_switch_seen = 1; | |
252b5132 RH |
11713 | break; |
11714 | ||
34ba82a8 TS |
11715 | /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32 |
11716 | and -mabi=64. */ | |
252b5132 | 11717 | case OPTION_32: |
23fce1e3 NC |
11718 | if (IS_ELF) |
11719 | mips_abi = O32_ABI; | |
11720 | /* We silently ignore -32 for non-ELF targets. This greatly | |
11721 | simplifies the construction of the MIPS GAS test cases. */ | |
252b5132 RH |
11722 | break; |
11723 | ||
23fce1e3 | 11724 | #ifdef OBJ_ELF |
e013f690 | 11725 | case OPTION_N32: |
f43abd2b | 11726 | if (!IS_ELF) |
34ba82a8 TS |
11727 | { |
11728 | as_bad (_("-n32 is supported for ELF format only")); | |
11729 | return 0; | |
11730 | } | |
316f5878 | 11731 | mips_abi = N32_ABI; |
e013f690 | 11732 | break; |
252b5132 | 11733 | |
e013f690 | 11734 | case OPTION_64: |
f43abd2b | 11735 | if (!IS_ELF) |
34ba82a8 TS |
11736 | { |
11737 | as_bad (_("-64 is supported for ELF format only")); | |
11738 | return 0; | |
11739 | } | |
316f5878 | 11740 | mips_abi = N64_ABI; |
f43abd2b | 11741 | if (!support_64bit_objects()) |
e013f690 | 11742 | as_fatal (_("No compiled in support for 64 bit object file format")); |
252b5132 | 11743 | break; |
ae948b86 | 11744 | #endif /* OBJ_ELF */ |
252b5132 | 11745 | |
c97ef257 | 11746 | case OPTION_GP32: |
a325df1d | 11747 | file_mips_gp32 = 1; |
c97ef257 AH |
11748 | break; |
11749 | ||
11750 | case OPTION_GP64: | |
a325df1d | 11751 | file_mips_gp32 = 0; |
c97ef257 | 11752 | break; |
252b5132 | 11753 | |
ca4e0257 | 11754 | case OPTION_FP32: |
a325df1d | 11755 | file_mips_fp32 = 1; |
316f5878 RS |
11756 | break; |
11757 | ||
11758 | case OPTION_FP64: | |
11759 | file_mips_fp32 = 0; | |
ca4e0257 RS |
11760 | break; |
11761 | ||
037b32b9 AN |
11762 | case OPTION_SINGLE_FLOAT: |
11763 | file_mips_single_float = 1; | |
11764 | break; | |
11765 | ||
11766 | case OPTION_DOUBLE_FLOAT: | |
11767 | file_mips_single_float = 0; | |
11768 | break; | |
11769 | ||
11770 | case OPTION_SOFT_FLOAT: | |
11771 | file_mips_soft_float = 1; | |
11772 | break; | |
11773 | ||
11774 | case OPTION_HARD_FLOAT: | |
11775 | file_mips_soft_float = 0; | |
11776 | break; | |
11777 | ||
ae948b86 | 11778 | #ifdef OBJ_ELF |
252b5132 | 11779 | case OPTION_MABI: |
f43abd2b | 11780 | if (!IS_ELF) |
34ba82a8 TS |
11781 | { |
11782 | as_bad (_("-mabi is supported for ELF format only")); | |
11783 | return 0; | |
11784 | } | |
e013f690 | 11785 | if (strcmp (arg, "32") == 0) |
316f5878 | 11786 | mips_abi = O32_ABI; |
e013f690 | 11787 | else if (strcmp (arg, "o64") == 0) |
316f5878 | 11788 | mips_abi = O64_ABI; |
e013f690 | 11789 | else if (strcmp (arg, "n32") == 0) |
316f5878 | 11790 | mips_abi = N32_ABI; |
e013f690 TS |
11791 | else if (strcmp (arg, "64") == 0) |
11792 | { | |
316f5878 | 11793 | mips_abi = N64_ABI; |
e013f690 TS |
11794 | if (! support_64bit_objects()) |
11795 | as_fatal (_("No compiled in support for 64 bit object file " | |
11796 | "format")); | |
11797 | } | |
11798 | else if (strcmp (arg, "eabi") == 0) | |
316f5878 | 11799 | mips_abi = EABI_ABI; |
e013f690 | 11800 | else |
da0e507f TS |
11801 | { |
11802 | as_fatal (_("invalid abi -mabi=%s"), arg); | |
11803 | return 0; | |
11804 | } | |
252b5132 | 11805 | break; |
e013f690 | 11806 | #endif /* OBJ_ELF */ |
252b5132 | 11807 | |
6b76fefe | 11808 | case OPTION_M7000_HILO_FIX: |
b34976b6 | 11809 | mips_7000_hilo_fix = TRUE; |
6b76fefe CM |
11810 | break; |
11811 | ||
9ee72ff1 | 11812 | case OPTION_MNO_7000_HILO_FIX: |
b34976b6 | 11813 | mips_7000_hilo_fix = FALSE; |
6b76fefe CM |
11814 | break; |
11815 | ||
ecb4347a DJ |
11816 | #ifdef OBJ_ELF |
11817 | case OPTION_MDEBUG: | |
b34976b6 | 11818 | mips_flag_mdebug = TRUE; |
ecb4347a DJ |
11819 | break; |
11820 | ||
11821 | case OPTION_NO_MDEBUG: | |
b34976b6 | 11822 | mips_flag_mdebug = FALSE; |
ecb4347a | 11823 | break; |
dcd410fe RO |
11824 | |
11825 | case OPTION_PDR: | |
11826 | mips_flag_pdr = TRUE; | |
11827 | break; | |
11828 | ||
11829 | case OPTION_NO_PDR: | |
11830 | mips_flag_pdr = FALSE; | |
11831 | break; | |
0a44bf69 RS |
11832 | |
11833 | case OPTION_MVXWORKS_PIC: | |
11834 | mips_pic = VXWORKS_PIC; | |
11835 | break; | |
ecb4347a DJ |
11836 | #endif /* OBJ_ELF */ |
11837 | ||
252b5132 RH |
11838 | default: |
11839 | return 0; | |
11840 | } | |
11841 | ||
c67a084a NC |
11842 | mips_fix_loongson2f = mips_fix_loongson2f_nop || mips_fix_loongson2f_jump; |
11843 | ||
252b5132 RH |
11844 | return 1; |
11845 | } | |
316f5878 RS |
11846 | \f |
11847 | /* Set up globals to generate code for the ISA or processor | |
11848 | described by INFO. */ | |
252b5132 | 11849 | |
252b5132 | 11850 | static void |
17a2f251 | 11851 | mips_set_architecture (const struct mips_cpu_info *info) |
252b5132 | 11852 | { |
316f5878 | 11853 | if (info != 0) |
252b5132 | 11854 | { |
fef14a42 TS |
11855 | file_mips_arch = info->cpu; |
11856 | mips_opts.arch = info->cpu; | |
316f5878 | 11857 | mips_opts.isa = info->isa; |
252b5132 | 11858 | } |
252b5132 RH |
11859 | } |
11860 | ||
252b5132 | 11861 | |
316f5878 | 11862 | /* Likewise for tuning. */ |
252b5132 | 11863 | |
316f5878 | 11864 | static void |
17a2f251 | 11865 | mips_set_tune (const struct mips_cpu_info *info) |
316f5878 RS |
11866 | { |
11867 | if (info != 0) | |
fef14a42 | 11868 | mips_tune = info->cpu; |
316f5878 | 11869 | } |
80cc45a5 | 11870 | |
34ba82a8 | 11871 | |
252b5132 | 11872 | void |
17a2f251 | 11873 | mips_after_parse_args (void) |
e9670677 | 11874 | { |
fef14a42 TS |
11875 | const struct mips_cpu_info *arch_info = 0; |
11876 | const struct mips_cpu_info *tune_info = 0; | |
11877 | ||
e9670677 | 11878 | /* GP relative stuff not working for PE */ |
6caf9ef4 | 11879 | if (strncmp (TARGET_OS, "pe", 2) == 0) |
e9670677 | 11880 | { |
6caf9ef4 | 11881 | if (g_switch_seen && g_switch_value != 0) |
e9670677 MR |
11882 | as_bad (_("-G not supported in this configuration.")); |
11883 | g_switch_value = 0; | |
11884 | } | |
11885 | ||
cac012d6 AO |
11886 | if (mips_abi == NO_ABI) |
11887 | mips_abi = MIPS_DEFAULT_ABI; | |
11888 | ||
22923709 RS |
11889 | /* The following code determines the architecture and register size. |
11890 | Similar code was added to GCC 3.3 (see override_options() in | |
11891 | config/mips/mips.c). The GAS and GCC code should be kept in sync | |
11892 | as much as possible. */ | |
e9670677 | 11893 | |
316f5878 | 11894 | if (mips_arch_string != 0) |
fef14a42 | 11895 | arch_info = mips_parse_cpu ("-march", mips_arch_string); |
e9670677 | 11896 | |
316f5878 | 11897 | if (file_mips_isa != ISA_UNKNOWN) |
e9670677 | 11898 | { |
316f5878 | 11899 | /* Handle -mipsN. At this point, file_mips_isa contains the |
fef14a42 | 11900 | ISA level specified by -mipsN, while arch_info->isa contains |
316f5878 | 11901 | the -march selection (if any). */ |
fef14a42 | 11902 | if (arch_info != 0) |
e9670677 | 11903 | { |
316f5878 RS |
11904 | /* -march takes precedence over -mipsN, since it is more descriptive. |
11905 | There's no harm in specifying both as long as the ISA levels | |
11906 | are the same. */ | |
fef14a42 | 11907 | if (file_mips_isa != arch_info->isa) |
316f5878 RS |
11908 | as_bad (_("-%s conflicts with the other architecture options, which imply -%s"), |
11909 | mips_cpu_info_from_isa (file_mips_isa)->name, | |
fef14a42 | 11910 | mips_cpu_info_from_isa (arch_info->isa)->name); |
e9670677 | 11911 | } |
316f5878 | 11912 | else |
fef14a42 | 11913 | arch_info = mips_cpu_info_from_isa (file_mips_isa); |
e9670677 MR |
11914 | } |
11915 | ||
fef14a42 TS |
11916 | if (arch_info == 0) |
11917 | arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT); | |
e9670677 | 11918 | |
fef14a42 | 11919 | if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa)) |
20203fb9 | 11920 | as_bad (_("-march=%s is not compatible with the selected ABI"), |
fef14a42 TS |
11921 | arch_info->name); |
11922 | ||
11923 | mips_set_architecture (arch_info); | |
11924 | ||
11925 | /* Optimize for file_mips_arch, unless -mtune selects a different processor. */ | |
11926 | if (mips_tune_string != 0) | |
11927 | tune_info = mips_parse_cpu ("-mtune", mips_tune_string); | |
e9670677 | 11928 | |
fef14a42 TS |
11929 | if (tune_info == 0) |
11930 | mips_set_tune (arch_info); | |
11931 | else | |
11932 | mips_set_tune (tune_info); | |
e9670677 | 11933 | |
316f5878 | 11934 | if (file_mips_gp32 >= 0) |
e9670677 | 11935 | { |
316f5878 RS |
11936 | /* The user specified the size of the integer registers. Make sure |
11937 | it agrees with the ABI and ISA. */ | |
11938 | if (file_mips_gp32 == 0 && !ISA_HAS_64BIT_REGS (mips_opts.isa)) | |
11939 | as_bad (_("-mgp64 used with a 32-bit processor")); | |
11940 | else if (file_mips_gp32 == 1 && ABI_NEEDS_64BIT_REGS (mips_abi)) | |
11941 | as_bad (_("-mgp32 used with a 64-bit ABI")); | |
11942 | else if (file_mips_gp32 == 0 && ABI_NEEDS_32BIT_REGS (mips_abi)) | |
11943 | as_bad (_("-mgp64 used with a 32-bit ABI")); | |
e9670677 MR |
11944 | } |
11945 | else | |
11946 | { | |
316f5878 RS |
11947 | /* Infer the integer register size from the ABI and processor. |
11948 | Restrict ourselves to 32-bit registers if that's all the | |
11949 | processor has, or if the ABI cannot handle 64-bit registers. */ | |
11950 | file_mips_gp32 = (ABI_NEEDS_32BIT_REGS (mips_abi) | |
11951 | || !ISA_HAS_64BIT_REGS (mips_opts.isa)); | |
e9670677 MR |
11952 | } |
11953 | ||
ad3fea08 TS |
11954 | switch (file_mips_fp32) |
11955 | { | |
11956 | default: | |
11957 | case -1: | |
11958 | /* No user specified float register size. | |
11959 | ??? GAS treats single-float processors as though they had 64-bit | |
11960 | float registers (although it complains when double-precision | |
11961 | instructions are used). As things stand, saying they have 32-bit | |
11962 | registers would lead to spurious "register must be even" messages. | |
11963 | So here we assume float registers are never smaller than the | |
11964 | integer ones. */ | |
11965 | if (file_mips_gp32 == 0) | |
11966 | /* 64-bit integer registers implies 64-bit float registers. */ | |
11967 | file_mips_fp32 = 0; | |
11968 | else if ((mips_opts.ase_mips3d > 0 || mips_opts.ase_mdmx > 0) | |
11969 | && ISA_HAS_64BIT_FPRS (mips_opts.isa)) | |
11970 | /* -mips3d and -mdmx imply 64-bit float registers, if possible. */ | |
11971 | file_mips_fp32 = 0; | |
11972 | else | |
11973 | /* 32-bit float registers. */ | |
11974 | file_mips_fp32 = 1; | |
11975 | break; | |
11976 | ||
11977 | /* The user specified the size of the float registers. Check if it | |
11978 | agrees with the ABI and ISA. */ | |
11979 | case 0: | |
11980 | if (!ISA_HAS_64BIT_FPRS (mips_opts.isa)) | |
11981 | as_bad (_("-mfp64 used with a 32-bit fpu")); | |
11982 | else if (ABI_NEEDS_32BIT_REGS (mips_abi) | |
11983 | && !ISA_HAS_MXHC1 (mips_opts.isa)) | |
11984 | as_warn (_("-mfp64 used with a 32-bit ABI")); | |
11985 | break; | |
11986 | case 1: | |
11987 | if (ABI_NEEDS_64BIT_REGS (mips_abi)) | |
11988 | as_warn (_("-mfp32 used with a 64-bit ABI")); | |
11989 | break; | |
11990 | } | |
e9670677 | 11991 | |
316f5878 | 11992 | /* End of GCC-shared inference code. */ |
e9670677 | 11993 | |
17a2f251 TS |
11994 | /* This flag is set when we have a 64-bit capable CPU but use only |
11995 | 32-bit wide registers. Note that EABI does not use it. */ | |
11996 | if (ISA_HAS_64BIT_REGS (mips_opts.isa) | |
11997 | && ((mips_abi == NO_ABI && file_mips_gp32 == 1) | |
11998 | || mips_abi == O32_ABI)) | |
316f5878 | 11999 | mips_32bitmode = 1; |
e9670677 MR |
12000 | |
12001 | if (mips_opts.isa == ISA_MIPS1 && mips_trap) | |
12002 | as_bad (_("trap exception not supported at ISA 1")); | |
12003 | ||
e9670677 MR |
12004 | /* If the selected architecture includes support for ASEs, enable |
12005 | generation of code for them. */ | |
a4672219 | 12006 | if (mips_opts.mips16 == -1) |
fef14a42 | 12007 | mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_arch)) ? 1 : 0; |
ffdefa66 | 12008 | if (mips_opts.ase_mips3d == -1) |
65263ce3 | 12009 | mips_opts.ase_mips3d = ((arch_info->flags & MIPS_CPU_ASE_MIPS3D) |
ad3fea08 TS |
12010 | && file_mips_fp32 == 0) ? 1 : 0; |
12011 | if (mips_opts.ase_mips3d && file_mips_fp32 == 1) | |
12012 | as_bad (_("-mfp32 used with -mips3d")); | |
12013 | ||
ffdefa66 | 12014 | if (mips_opts.ase_mdmx == -1) |
65263ce3 | 12015 | mips_opts.ase_mdmx = ((arch_info->flags & MIPS_CPU_ASE_MDMX) |
ad3fea08 TS |
12016 | && file_mips_fp32 == 0) ? 1 : 0; |
12017 | if (mips_opts.ase_mdmx && file_mips_fp32 == 1) | |
12018 | as_bad (_("-mfp32 used with -mdmx")); | |
12019 | ||
12020 | if (mips_opts.ase_smartmips == -1) | |
12021 | mips_opts.ase_smartmips = (arch_info->flags & MIPS_CPU_ASE_SMARTMIPS) ? 1 : 0; | |
12022 | if (mips_opts.ase_smartmips && !ISA_SUPPORTS_SMARTMIPS) | |
20203fb9 NC |
12023 | as_warn (_("%s ISA does not support SmartMIPS"), |
12024 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
ad3fea08 | 12025 | |
74cd071d | 12026 | if (mips_opts.ase_dsp == -1) |
ad3fea08 TS |
12027 | mips_opts.ase_dsp = (arch_info->flags & MIPS_CPU_ASE_DSP) ? 1 : 0; |
12028 | if (mips_opts.ase_dsp && !ISA_SUPPORTS_DSP_ASE) | |
20203fb9 NC |
12029 | as_warn (_("%s ISA does not support DSP ASE"), |
12030 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
ad3fea08 | 12031 | |
8b082fb1 TS |
12032 | if (mips_opts.ase_dspr2 == -1) |
12033 | { | |
12034 | mips_opts.ase_dspr2 = (arch_info->flags & MIPS_CPU_ASE_DSPR2) ? 1 : 0; | |
12035 | mips_opts.ase_dsp = (arch_info->flags & MIPS_CPU_ASE_DSP) ? 1 : 0; | |
12036 | } | |
12037 | if (mips_opts.ase_dspr2 && !ISA_SUPPORTS_DSPR2_ASE) | |
20203fb9 NC |
12038 | as_warn (_("%s ISA does not support DSP R2 ASE"), |
12039 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
8b082fb1 | 12040 | |
ef2e4d86 | 12041 | if (mips_opts.ase_mt == -1) |
ad3fea08 TS |
12042 | mips_opts.ase_mt = (arch_info->flags & MIPS_CPU_ASE_MT) ? 1 : 0; |
12043 | if (mips_opts.ase_mt && !ISA_SUPPORTS_MT_ASE) | |
20203fb9 NC |
12044 | as_warn (_("%s ISA does not support MT ASE"), |
12045 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
e9670677 | 12046 | |
e9670677 | 12047 | file_mips_isa = mips_opts.isa; |
a4672219 | 12048 | file_ase_mips16 = mips_opts.mips16; |
e9670677 MR |
12049 | file_ase_mips3d = mips_opts.ase_mips3d; |
12050 | file_ase_mdmx = mips_opts.ase_mdmx; | |
e16bfa71 | 12051 | file_ase_smartmips = mips_opts.ase_smartmips; |
74cd071d | 12052 | file_ase_dsp = mips_opts.ase_dsp; |
8b082fb1 | 12053 | file_ase_dspr2 = mips_opts.ase_dspr2; |
ef2e4d86 | 12054 | file_ase_mt = mips_opts.ase_mt; |
e9670677 MR |
12055 | mips_opts.gp32 = file_mips_gp32; |
12056 | mips_opts.fp32 = file_mips_fp32; | |
037b32b9 AN |
12057 | mips_opts.soft_float = file_mips_soft_float; |
12058 | mips_opts.single_float = file_mips_single_float; | |
e9670677 | 12059 | |
ecb4347a DJ |
12060 | if (mips_flag_mdebug < 0) |
12061 | { | |
12062 | #ifdef OBJ_MAYBE_ECOFF | |
12063 | if (OUTPUT_FLAVOR == bfd_target_ecoff_flavour) | |
12064 | mips_flag_mdebug = 1; | |
12065 | else | |
12066 | #endif /* OBJ_MAYBE_ECOFF */ | |
12067 | mips_flag_mdebug = 0; | |
12068 | } | |
e9670677 MR |
12069 | } |
12070 | \f | |
12071 | void | |
17a2f251 | 12072 | mips_init_after_args (void) |
252b5132 RH |
12073 | { |
12074 | /* initialize opcodes */ | |
12075 | bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes; | |
beae10d5 | 12076 | mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes; |
252b5132 RH |
12077 | } |
12078 | ||
12079 | long | |
17a2f251 | 12080 | md_pcrel_from (fixS *fixP) |
252b5132 | 12081 | { |
a7ebbfdf TS |
12082 | valueT addr = fixP->fx_where + fixP->fx_frag->fr_address; |
12083 | switch (fixP->fx_r_type) | |
12084 | { | |
12085 | case BFD_RELOC_16_PCREL_S2: | |
12086 | case BFD_RELOC_MIPS_JMP: | |
12087 | /* Return the address of the delay slot. */ | |
12088 | return addr + 4; | |
12089 | default: | |
58ea3d6a | 12090 | /* We have no relocation type for PC relative MIPS16 instructions. */ |
64817874 TS |
12091 | if (fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != now_seg) |
12092 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
12093 | _("PC relative MIPS16 instruction references a different section")); | |
a7ebbfdf TS |
12094 | return addr; |
12095 | } | |
252b5132 RH |
12096 | } |
12097 | ||
252b5132 RH |
12098 | /* This is called before the symbol table is processed. In order to |
12099 | work with gcc when using mips-tfile, we must keep all local labels. | |
12100 | However, in other cases, we want to discard them. If we were | |
12101 | called with -g, but we didn't see any debugging information, it may | |
12102 | mean that gcc is smuggling debugging information through to | |
12103 | mips-tfile, in which case we must generate all local labels. */ | |
12104 | ||
12105 | void | |
17a2f251 | 12106 | mips_frob_file_before_adjust (void) |
252b5132 RH |
12107 | { |
12108 | #ifndef NO_ECOFF_DEBUGGING | |
12109 | if (ECOFF_DEBUGGING | |
12110 | && mips_debug != 0 | |
12111 | && ! ecoff_debugging_seen) | |
12112 | flag_keep_locals = 1; | |
12113 | #endif | |
12114 | } | |
12115 | ||
3b91255e | 12116 | /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede |
55cf6793 | 12117 | the corresponding LO16 reloc. This is called before md_apply_fix and |
3b91255e RS |
12118 | tc_gen_reloc. Unmatched relocs can only be generated by use of explicit |
12119 | relocation operators. | |
12120 | ||
12121 | For our purposes, a %lo() expression matches a %got() or %hi() | |
12122 | expression if: | |
12123 | ||
12124 | (a) it refers to the same symbol; and | |
12125 | (b) the offset applied in the %lo() expression is no lower than | |
12126 | the offset applied in the %got() or %hi(). | |
12127 | ||
12128 | (b) allows us to cope with code like: | |
12129 | ||
12130 | lui $4,%hi(foo) | |
12131 | lh $4,%lo(foo+2)($4) | |
12132 | ||
12133 | ...which is legal on RELA targets, and has a well-defined behaviour | |
12134 | if the user knows that adding 2 to "foo" will not induce a carry to | |
12135 | the high 16 bits. | |
12136 | ||
12137 | When several %lo()s match a particular %got() or %hi(), we use the | |
12138 | following rules to distinguish them: | |
12139 | ||
12140 | (1) %lo()s with smaller offsets are a better match than %lo()s with | |
12141 | higher offsets. | |
12142 | ||
12143 | (2) %lo()s with no matching %got() or %hi() are better than those | |
12144 | that already have a matching %got() or %hi(). | |
12145 | ||
12146 | (3) later %lo()s are better than earlier %lo()s. | |
12147 | ||
12148 | These rules are applied in order. | |
12149 | ||
12150 | (1) means, among other things, that %lo()s with identical offsets are | |
12151 | chosen if they exist. | |
12152 | ||
12153 | (2) means that we won't associate several high-part relocations with | |
12154 | the same low-part relocation unless there's no alternative. Having | |
12155 | several high parts for the same low part is a GNU extension; this rule | |
12156 | allows careful users to avoid it. | |
12157 | ||
12158 | (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order, | |
12159 | with the last high-part relocation being at the front of the list. | |
12160 | It therefore makes sense to choose the last matching low-part | |
12161 | relocation, all other things being equal. It's also easier | |
12162 | to code that way. */ | |
252b5132 RH |
12163 | |
12164 | void | |
17a2f251 | 12165 | mips_frob_file (void) |
252b5132 RH |
12166 | { |
12167 | struct mips_hi_fixup *l; | |
35903be0 | 12168 | bfd_reloc_code_real_type looking_for_rtype = BFD_RELOC_UNUSED; |
252b5132 RH |
12169 | |
12170 | for (l = mips_hi_fixup_list; l != NULL; l = l->next) | |
12171 | { | |
12172 | segment_info_type *seginfo; | |
3b91255e RS |
12173 | bfd_boolean matched_lo_p; |
12174 | fixS **hi_pos, **lo_pos, **pos; | |
252b5132 | 12175 | |
9c2799c2 | 12176 | gas_assert (reloc_needs_lo_p (l->fixp->fx_r_type)); |
252b5132 | 12177 | |
5919d012 RS |
12178 | /* If a GOT16 relocation turns out to be against a global symbol, |
12179 | there isn't supposed to be a matching LO. */ | |
738e5348 | 12180 | if (got16_reloc_p (l->fixp->fx_r_type) |
5919d012 RS |
12181 | && !pic_need_relax (l->fixp->fx_addsy, l->seg)) |
12182 | continue; | |
12183 | ||
12184 | /* Check quickly whether the next fixup happens to be a matching %lo. */ | |
12185 | if (fixup_has_matching_lo_p (l->fixp)) | |
252b5132 RH |
12186 | continue; |
12187 | ||
252b5132 | 12188 | seginfo = seg_info (l->seg); |
252b5132 | 12189 | |
3b91255e RS |
12190 | /* Set HI_POS to the position of this relocation in the chain. |
12191 | Set LO_POS to the position of the chosen low-part relocation. | |
12192 | MATCHED_LO_P is true on entry to the loop if *POS is a low-part | |
12193 | relocation that matches an immediately-preceding high-part | |
12194 | relocation. */ | |
12195 | hi_pos = NULL; | |
12196 | lo_pos = NULL; | |
12197 | matched_lo_p = FALSE; | |
738e5348 | 12198 | looking_for_rtype = matching_lo_reloc (l->fixp->fx_r_type); |
35903be0 | 12199 | |
3b91255e RS |
12200 | for (pos = &seginfo->fix_root; *pos != NULL; pos = &(*pos)->fx_next) |
12201 | { | |
12202 | if (*pos == l->fixp) | |
12203 | hi_pos = pos; | |
12204 | ||
35903be0 | 12205 | if ((*pos)->fx_r_type == looking_for_rtype |
30cfc97a | 12206 | && symbol_same_p ((*pos)->fx_addsy, l->fixp->fx_addsy) |
3b91255e RS |
12207 | && (*pos)->fx_offset >= l->fixp->fx_offset |
12208 | && (lo_pos == NULL | |
12209 | || (*pos)->fx_offset < (*lo_pos)->fx_offset | |
12210 | || (!matched_lo_p | |
12211 | && (*pos)->fx_offset == (*lo_pos)->fx_offset))) | |
12212 | lo_pos = pos; | |
12213 | ||
12214 | matched_lo_p = (reloc_needs_lo_p ((*pos)->fx_r_type) | |
12215 | && fixup_has_matching_lo_p (*pos)); | |
12216 | } | |
12217 | ||
12218 | /* If we found a match, remove the high-part relocation from its | |
12219 | current position and insert it before the low-part relocation. | |
12220 | Make the offsets match so that fixup_has_matching_lo_p() | |
12221 | will return true. | |
12222 | ||
12223 | We don't warn about unmatched high-part relocations since some | |
12224 | versions of gcc have been known to emit dead "lui ...%hi(...)" | |
12225 | instructions. */ | |
12226 | if (lo_pos != NULL) | |
12227 | { | |
12228 | l->fixp->fx_offset = (*lo_pos)->fx_offset; | |
12229 | if (l->fixp->fx_next != *lo_pos) | |
252b5132 | 12230 | { |
3b91255e RS |
12231 | *hi_pos = l->fixp->fx_next; |
12232 | l->fixp->fx_next = *lo_pos; | |
12233 | *lo_pos = l->fixp; | |
252b5132 | 12234 | } |
252b5132 RH |
12235 | } |
12236 | } | |
12237 | } | |
12238 | ||
3e722fb5 | 12239 | /* We may have combined relocations without symbols in the N32/N64 ABI. |
f6688943 | 12240 | We have to prevent gas from dropping them. */ |
252b5132 | 12241 | |
252b5132 | 12242 | int |
17a2f251 | 12243 | mips_force_relocation (fixS *fixp) |
252b5132 | 12244 | { |
ae6063d4 | 12245 | if (generic_force_reloc (fixp)) |
252b5132 RH |
12246 | return 1; |
12247 | ||
f6688943 TS |
12248 | if (HAVE_NEWABI |
12249 | && S_GET_SEGMENT (fixp->fx_addsy) == bfd_abs_section_ptr | |
12250 | && (fixp->fx_r_type == BFD_RELOC_MIPS_SUB | |
738e5348 RS |
12251 | || hi16_reloc_p (fixp->fx_r_type) |
12252 | || lo16_reloc_p (fixp->fx_r_type))) | |
f6688943 TS |
12253 | return 1; |
12254 | ||
3e722fb5 | 12255 | return 0; |
252b5132 RH |
12256 | } |
12257 | ||
12258 | /* Apply a fixup to the object file. */ | |
12259 | ||
94f592af | 12260 | void |
55cf6793 | 12261 | md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) |
252b5132 | 12262 | { |
874e8986 | 12263 | bfd_byte *buf; |
98aa84af | 12264 | long insn; |
a7ebbfdf | 12265 | reloc_howto_type *howto; |
252b5132 | 12266 | |
a7ebbfdf TS |
12267 | /* We ignore generic BFD relocations we don't know about. */ |
12268 | howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type); | |
12269 | if (! howto) | |
12270 | return; | |
65551fa4 | 12271 | |
9c2799c2 | 12272 | gas_assert (fixP->fx_size == 4 |
90ecf173 MR |
12273 | || fixP->fx_r_type == BFD_RELOC_16 |
12274 | || fixP->fx_r_type == BFD_RELOC_64 | |
12275 | || fixP->fx_r_type == BFD_RELOC_CTOR | |
12276 | || fixP->fx_r_type == BFD_RELOC_MIPS_SUB | |
12277 | || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT | |
12278 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY | |
12279 | || fixP->fx_r_type == BFD_RELOC_MIPS_TLS_DTPREL64); | |
252b5132 | 12280 | |
a7ebbfdf | 12281 | buf = (bfd_byte *) (fixP->fx_frag->fr_literal + fixP->fx_where); |
252b5132 | 12282 | |
9c2799c2 | 12283 | gas_assert (!fixP->fx_pcrel || fixP->fx_r_type == BFD_RELOC_16_PCREL_S2); |
b1dca8ee RS |
12284 | |
12285 | /* Don't treat parts of a composite relocation as done. There are two | |
12286 | reasons for this: | |
12287 | ||
12288 | (1) The second and third parts will be against 0 (RSS_UNDEF) but | |
12289 | should nevertheless be emitted if the first part is. | |
12290 | ||
12291 | (2) In normal usage, composite relocations are never assembly-time | |
12292 | constants. The easiest way of dealing with the pathological | |
12293 | exceptions is to generate a relocation against STN_UNDEF and | |
12294 | leave everything up to the linker. */ | |
3994f87e | 12295 | if (fixP->fx_addsy == NULL && !fixP->fx_pcrel && fixP->fx_tcbit == 0) |
252b5132 RH |
12296 | fixP->fx_done = 1; |
12297 | ||
12298 | switch (fixP->fx_r_type) | |
12299 | { | |
3f98094e DJ |
12300 | case BFD_RELOC_MIPS_TLS_GD: |
12301 | case BFD_RELOC_MIPS_TLS_LDM: | |
741d6ea8 JM |
12302 | case BFD_RELOC_MIPS_TLS_DTPREL32: |
12303 | case BFD_RELOC_MIPS_TLS_DTPREL64: | |
3f98094e DJ |
12304 | case BFD_RELOC_MIPS_TLS_DTPREL_HI16: |
12305 | case BFD_RELOC_MIPS_TLS_DTPREL_LO16: | |
12306 | case BFD_RELOC_MIPS_TLS_GOTTPREL: | |
12307 | case BFD_RELOC_MIPS_TLS_TPREL_HI16: | |
12308 | case BFD_RELOC_MIPS_TLS_TPREL_LO16: | |
12309 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
12310 | /* fall through */ | |
12311 | ||
252b5132 | 12312 | case BFD_RELOC_MIPS_JMP: |
e369bcce TS |
12313 | case BFD_RELOC_MIPS_SHIFT5: |
12314 | case BFD_RELOC_MIPS_SHIFT6: | |
12315 | case BFD_RELOC_MIPS_GOT_DISP: | |
12316 | case BFD_RELOC_MIPS_GOT_PAGE: | |
12317 | case BFD_RELOC_MIPS_GOT_OFST: | |
12318 | case BFD_RELOC_MIPS_SUB: | |
12319 | case BFD_RELOC_MIPS_INSERT_A: | |
12320 | case BFD_RELOC_MIPS_INSERT_B: | |
12321 | case BFD_RELOC_MIPS_DELETE: | |
12322 | case BFD_RELOC_MIPS_HIGHEST: | |
12323 | case BFD_RELOC_MIPS_HIGHER: | |
12324 | case BFD_RELOC_MIPS_SCN_DISP: | |
12325 | case BFD_RELOC_MIPS_REL16: | |
12326 | case BFD_RELOC_MIPS_RELGOT: | |
12327 | case BFD_RELOC_MIPS_JALR: | |
252b5132 RH |
12328 | case BFD_RELOC_HI16: |
12329 | case BFD_RELOC_HI16_S: | |
cdf6fd85 | 12330 | case BFD_RELOC_GPREL16: |
252b5132 RH |
12331 | case BFD_RELOC_MIPS_LITERAL: |
12332 | case BFD_RELOC_MIPS_CALL16: | |
12333 | case BFD_RELOC_MIPS_GOT16: | |
cdf6fd85 | 12334 | case BFD_RELOC_GPREL32: |
252b5132 RH |
12335 | case BFD_RELOC_MIPS_GOT_HI16: |
12336 | case BFD_RELOC_MIPS_GOT_LO16: | |
12337 | case BFD_RELOC_MIPS_CALL_HI16: | |
12338 | case BFD_RELOC_MIPS_CALL_LO16: | |
12339 | case BFD_RELOC_MIPS16_GPREL: | |
738e5348 RS |
12340 | case BFD_RELOC_MIPS16_GOT16: |
12341 | case BFD_RELOC_MIPS16_CALL16: | |
d6f16593 MR |
12342 | case BFD_RELOC_MIPS16_HI16: |
12343 | case BFD_RELOC_MIPS16_HI16_S: | |
252b5132 | 12344 | case BFD_RELOC_MIPS16_JMP: |
54f4ddb3 | 12345 | /* Nothing needed to do. The value comes from the reloc entry. */ |
252b5132 RH |
12346 | break; |
12347 | ||
252b5132 RH |
12348 | case BFD_RELOC_64: |
12349 | /* This is handled like BFD_RELOC_32, but we output a sign | |
12350 | extended value if we are only 32 bits. */ | |
3e722fb5 | 12351 | if (fixP->fx_done) |
252b5132 RH |
12352 | { |
12353 | if (8 <= sizeof (valueT)) | |
2132e3a3 | 12354 | md_number_to_chars ((char *) buf, *valP, 8); |
252b5132 RH |
12355 | else |
12356 | { | |
a7ebbfdf | 12357 | valueT hiv; |
252b5132 | 12358 | |
a7ebbfdf | 12359 | if ((*valP & 0x80000000) != 0) |
252b5132 RH |
12360 | hiv = 0xffffffff; |
12361 | else | |
12362 | hiv = 0; | |
b215186b | 12363 | md_number_to_chars ((char *)(buf + (target_big_endian ? 4 : 0)), |
a7ebbfdf | 12364 | *valP, 4); |
b215186b | 12365 | md_number_to_chars ((char *)(buf + (target_big_endian ? 0 : 4)), |
a7ebbfdf | 12366 | hiv, 4); |
252b5132 RH |
12367 | } |
12368 | } | |
12369 | break; | |
12370 | ||
056350c6 | 12371 | case BFD_RELOC_RVA: |
252b5132 | 12372 | case BFD_RELOC_32: |
252b5132 RH |
12373 | case BFD_RELOC_16: |
12374 | /* If we are deleting this reloc entry, we must fill in the | |
54f4ddb3 TS |
12375 | value now. This can happen if we have a .word which is not |
12376 | resolved when it appears but is later defined. */ | |
252b5132 | 12377 | if (fixP->fx_done) |
54f4ddb3 | 12378 | md_number_to_chars ((char *) buf, *valP, fixP->fx_size); |
252b5132 RH |
12379 | break; |
12380 | ||
12381 | case BFD_RELOC_LO16: | |
d6f16593 | 12382 | case BFD_RELOC_MIPS16_LO16: |
3e722fb5 CD |
12383 | /* FIXME: Now that embedded-PIC is gone, some of this code/comment |
12384 | may be safe to remove, but if so it's not obvious. */ | |
252b5132 RH |
12385 | /* When handling an embedded PIC switch statement, we can wind |
12386 | up deleting a LO16 reloc. See the 'o' case in mips_ip. */ | |
12387 | if (fixP->fx_done) | |
12388 | { | |
a7ebbfdf | 12389 | if (*valP + 0x8000 > 0xffff) |
252b5132 RH |
12390 | as_bad_where (fixP->fx_file, fixP->fx_line, |
12391 | _("relocation overflow")); | |
252b5132 RH |
12392 | if (target_big_endian) |
12393 | buf += 2; | |
2132e3a3 | 12394 | md_number_to_chars ((char *) buf, *valP, 2); |
252b5132 RH |
12395 | } |
12396 | break; | |
12397 | ||
12398 | case BFD_RELOC_16_PCREL_S2: | |
a7ebbfdf | 12399 | if ((*valP & 0x3) != 0) |
cb56d3d3 | 12400 | as_bad_where (fixP->fx_file, fixP->fx_line, |
bad36eac | 12401 | _("Branch to misaligned address (%lx)"), (long) *valP); |
cb56d3d3 | 12402 | |
54f4ddb3 TS |
12403 | /* We need to save the bits in the instruction since fixup_segment() |
12404 | might be deleting the relocation entry (i.e., a branch within | |
12405 | the current segment). */ | |
a7ebbfdf | 12406 | if (! fixP->fx_done) |
bb2d6cd7 | 12407 | break; |
252b5132 | 12408 | |
54f4ddb3 | 12409 | /* Update old instruction data. */ |
252b5132 RH |
12410 | if (target_big_endian) |
12411 | insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3]; | |
12412 | else | |
12413 | insn = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0]; | |
12414 | ||
a7ebbfdf TS |
12415 | if (*valP + 0x20000 <= 0x3ffff) |
12416 | { | |
12417 | insn |= (*valP >> 2) & 0xffff; | |
2132e3a3 | 12418 | md_number_to_chars ((char *) buf, insn, 4); |
a7ebbfdf TS |
12419 | } |
12420 | else if (mips_pic == NO_PIC | |
12421 | && fixP->fx_done | |
12422 | && fixP->fx_frag->fr_address >= text_section->vma | |
12423 | && (fixP->fx_frag->fr_address | |
587aac4e | 12424 | < text_section->vma + bfd_get_section_size (text_section)) |
a7ebbfdf TS |
12425 | && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */ |
12426 | || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */ | |
12427 | || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */ | |
252b5132 RH |
12428 | { |
12429 | /* The branch offset is too large. If this is an | |
12430 | unconditional branch, and we are not generating PIC code, | |
12431 | we can convert it to an absolute jump instruction. */ | |
a7ebbfdf TS |
12432 | if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */ |
12433 | insn = 0x0c000000; /* jal */ | |
252b5132 | 12434 | else |
a7ebbfdf TS |
12435 | insn = 0x08000000; /* j */ |
12436 | fixP->fx_r_type = BFD_RELOC_MIPS_JMP; | |
12437 | fixP->fx_done = 0; | |
12438 | fixP->fx_addsy = section_symbol (text_section); | |
12439 | *valP += md_pcrel_from (fixP); | |
2132e3a3 | 12440 | md_number_to_chars ((char *) buf, insn, 4); |
a7ebbfdf TS |
12441 | } |
12442 | else | |
12443 | { | |
12444 | /* If we got here, we have branch-relaxation disabled, | |
12445 | and there's nothing we can do to fix this instruction | |
12446 | without turning it into a longer sequence. */ | |
12447 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
12448 | _("Branch out of range")); | |
252b5132 | 12449 | } |
252b5132 RH |
12450 | break; |
12451 | ||
12452 | case BFD_RELOC_VTABLE_INHERIT: | |
12453 | fixP->fx_done = 0; | |
12454 | if (fixP->fx_addsy | |
12455 | && !S_IS_DEFINED (fixP->fx_addsy) | |
12456 | && !S_IS_WEAK (fixP->fx_addsy)) | |
12457 | S_SET_WEAK (fixP->fx_addsy); | |
12458 | break; | |
12459 | ||
12460 | case BFD_RELOC_VTABLE_ENTRY: | |
12461 | fixP->fx_done = 0; | |
12462 | break; | |
12463 | ||
12464 | default: | |
12465 | internalError (); | |
12466 | } | |
a7ebbfdf TS |
12467 | |
12468 | /* Remember value for tc_gen_reloc. */ | |
12469 | fixP->fx_addnumber = *valP; | |
252b5132 RH |
12470 | } |
12471 | ||
252b5132 | 12472 | static symbolS * |
17a2f251 | 12473 | get_symbol (void) |
252b5132 RH |
12474 | { |
12475 | int c; | |
12476 | char *name; | |
12477 | symbolS *p; | |
12478 | ||
12479 | name = input_line_pointer; | |
12480 | c = get_symbol_end (); | |
12481 | p = (symbolS *) symbol_find_or_make (name); | |
12482 | *input_line_pointer = c; | |
12483 | return p; | |
12484 | } | |
12485 | ||
742a56fe RS |
12486 | /* Align the current frag to a given power of two. If a particular |
12487 | fill byte should be used, FILL points to an integer that contains | |
12488 | that byte, otherwise FILL is null. | |
12489 | ||
12490 | The MIPS assembler also automatically adjusts any preceding | |
12491 | label. */ | |
252b5132 RH |
12492 | |
12493 | static void | |
742a56fe | 12494 | mips_align (int to, int *fill, symbolS *label) |
252b5132 | 12495 | { |
7d10b47d | 12496 | mips_emit_delays (); |
742a56fe RS |
12497 | mips_record_mips16_mode (); |
12498 | if (fill == NULL && subseg_text_p (now_seg)) | |
12499 | frag_align_code (to, 0); | |
12500 | else | |
12501 | frag_align (to, fill ? *fill : 0, 0); | |
252b5132 RH |
12502 | record_alignment (now_seg, to); |
12503 | if (label != NULL) | |
12504 | { | |
9c2799c2 | 12505 | gas_assert (S_GET_SEGMENT (label) == now_seg); |
49309057 | 12506 | symbol_set_frag (label, frag_now); |
252b5132 RH |
12507 | S_SET_VALUE (label, (valueT) frag_now_fix ()); |
12508 | } | |
12509 | } | |
12510 | ||
12511 | /* Align to a given power of two. .align 0 turns off the automatic | |
12512 | alignment used by the data creating pseudo-ops. */ | |
12513 | ||
12514 | static void | |
17a2f251 | 12515 | s_align (int x ATTRIBUTE_UNUSED) |
252b5132 | 12516 | { |
742a56fe | 12517 | int temp, fill_value, *fill_ptr; |
49954fb4 | 12518 | long max_alignment = 28; |
252b5132 | 12519 | |
54f4ddb3 | 12520 | /* o Note that the assembler pulls down any immediately preceding label |
252b5132 | 12521 | to the aligned address. |
54f4ddb3 | 12522 | o It's not documented but auto alignment is reinstated by |
252b5132 | 12523 | a .align pseudo instruction. |
54f4ddb3 | 12524 | o Note also that after auto alignment is turned off the mips assembler |
252b5132 | 12525 | issues an error on attempt to assemble an improperly aligned data item. |
54f4ddb3 | 12526 | We don't. */ |
252b5132 RH |
12527 | |
12528 | temp = get_absolute_expression (); | |
12529 | if (temp > max_alignment) | |
12530 | as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment); | |
12531 | else if (temp < 0) | |
12532 | { | |
12533 | as_warn (_("Alignment negative: 0 assumed.")); | |
12534 | temp = 0; | |
12535 | } | |
12536 | if (*input_line_pointer == ',') | |
12537 | { | |
f9419b05 | 12538 | ++input_line_pointer; |
742a56fe RS |
12539 | fill_value = get_absolute_expression (); |
12540 | fill_ptr = &fill_value; | |
252b5132 RH |
12541 | } |
12542 | else | |
742a56fe | 12543 | fill_ptr = 0; |
252b5132 RH |
12544 | if (temp) |
12545 | { | |
a8dbcb85 TS |
12546 | segment_info_type *si = seg_info (now_seg); |
12547 | struct insn_label_list *l = si->label_list; | |
54f4ddb3 | 12548 | /* Auto alignment should be switched on by next section change. */ |
252b5132 | 12549 | auto_align = 1; |
742a56fe | 12550 | mips_align (temp, fill_ptr, l != NULL ? l->label : NULL); |
252b5132 RH |
12551 | } |
12552 | else | |
12553 | { | |
12554 | auto_align = 0; | |
12555 | } | |
12556 | ||
12557 | demand_empty_rest_of_line (); | |
12558 | } | |
12559 | ||
252b5132 | 12560 | static void |
17a2f251 | 12561 | s_change_sec (int sec) |
252b5132 RH |
12562 | { |
12563 | segT seg; | |
12564 | ||
252b5132 RH |
12565 | #ifdef OBJ_ELF |
12566 | /* The ELF backend needs to know that we are changing sections, so | |
12567 | that .previous works correctly. We could do something like check | |
b6ff326e | 12568 | for an obj_section_change_hook macro, but that might be confusing |
252b5132 RH |
12569 | as it would not be appropriate to use it in the section changing |
12570 | functions in read.c, since obj-elf.c intercepts those. FIXME: | |
12571 | This should be cleaner, somehow. */ | |
f43abd2b TS |
12572 | if (IS_ELF) |
12573 | obj_elf_section_change_hook (); | |
252b5132 RH |
12574 | #endif |
12575 | ||
7d10b47d | 12576 | mips_emit_delays (); |
6a32d874 | 12577 | |
252b5132 RH |
12578 | switch (sec) |
12579 | { | |
12580 | case 't': | |
12581 | s_text (0); | |
12582 | break; | |
12583 | case 'd': | |
12584 | s_data (0); | |
12585 | break; | |
12586 | case 'b': | |
12587 | subseg_set (bss_section, (subsegT) get_absolute_expression ()); | |
12588 | demand_empty_rest_of_line (); | |
12589 | break; | |
12590 | ||
12591 | case 'r': | |
4d0d148d TS |
12592 | seg = subseg_new (RDATA_SECTION_NAME, |
12593 | (subsegT) get_absolute_expression ()); | |
f43abd2b | 12594 | if (IS_ELF) |
252b5132 | 12595 | { |
4d0d148d TS |
12596 | bfd_set_section_flags (stdoutput, seg, (SEC_ALLOC | SEC_LOAD |
12597 | | SEC_READONLY | SEC_RELOC | |
12598 | | SEC_DATA)); | |
c41e87e3 | 12599 | if (strncmp (TARGET_OS, "elf", 3) != 0) |
4d0d148d | 12600 | record_alignment (seg, 4); |
252b5132 | 12601 | } |
4d0d148d | 12602 | demand_empty_rest_of_line (); |
252b5132 RH |
12603 | break; |
12604 | ||
12605 | case 's': | |
4d0d148d | 12606 | seg = subseg_new (".sdata", (subsegT) get_absolute_expression ()); |
f43abd2b | 12607 | if (IS_ELF) |
252b5132 | 12608 | { |
4d0d148d TS |
12609 | bfd_set_section_flags (stdoutput, seg, |
12610 | SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA); | |
c41e87e3 | 12611 | if (strncmp (TARGET_OS, "elf", 3) != 0) |
4d0d148d | 12612 | record_alignment (seg, 4); |
252b5132 | 12613 | } |
4d0d148d TS |
12614 | demand_empty_rest_of_line (); |
12615 | break; | |
998b3c36 MR |
12616 | |
12617 | case 'B': | |
12618 | seg = subseg_new (".sbss", (subsegT) get_absolute_expression ()); | |
12619 | if (IS_ELF) | |
12620 | { | |
12621 | bfd_set_section_flags (stdoutput, seg, SEC_ALLOC); | |
12622 | if (strncmp (TARGET_OS, "elf", 3) != 0) | |
12623 | record_alignment (seg, 4); | |
12624 | } | |
12625 | demand_empty_rest_of_line (); | |
12626 | break; | |
252b5132 RH |
12627 | } |
12628 | ||
12629 | auto_align = 1; | |
12630 | } | |
b34976b6 | 12631 | |
cca86cc8 | 12632 | void |
17a2f251 | 12633 | s_change_section (int ignore ATTRIBUTE_UNUSED) |
cca86cc8 | 12634 | { |
7ed4a06a | 12635 | #ifdef OBJ_ELF |
cca86cc8 SC |
12636 | char *section_name; |
12637 | char c; | |
684022ea | 12638 | char next_c = 0; |
cca86cc8 SC |
12639 | int section_type; |
12640 | int section_flag; | |
12641 | int section_entry_size; | |
12642 | int section_alignment; | |
b34976b6 | 12643 | |
f43abd2b | 12644 | if (!IS_ELF) |
7ed4a06a TS |
12645 | return; |
12646 | ||
cca86cc8 SC |
12647 | section_name = input_line_pointer; |
12648 | c = get_symbol_end (); | |
a816d1ed AO |
12649 | if (c) |
12650 | next_c = *(input_line_pointer + 1); | |
cca86cc8 | 12651 | |
4cf0dd0d TS |
12652 | /* Do we have .section Name<,"flags">? */ |
12653 | if (c != ',' || (c == ',' && next_c == '"')) | |
cca86cc8 | 12654 | { |
4cf0dd0d TS |
12655 | /* just after name is now '\0'. */ |
12656 | *input_line_pointer = c; | |
cca86cc8 SC |
12657 | input_line_pointer = section_name; |
12658 | obj_elf_section (ignore); | |
12659 | return; | |
12660 | } | |
12661 | input_line_pointer++; | |
12662 | ||
12663 | /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */ | |
12664 | if (c == ',') | |
12665 | section_type = get_absolute_expression (); | |
12666 | else | |
12667 | section_type = 0; | |
12668 | if (*input_line_pointer++ == ',') | |
12669 | section_flag = get_absolute_expression (); | |
12670 | else | |
12671 | section_flag = 0; | |
12672 | if (*input_line_pointer++ == ',') | |
12673 | section_entry_size = get_absolute_expression (); | |
12674 | else | |
12675 | section_entry_size = 0; | |
12676 | if (*input_line_pointer++ == ',') | |
12677 | section_alignment = get_absolute_expression (); | |
12678 | else | |
12679 | section_alignment = 0; | |
87975d2a AM |
12680 | /* FIXME: really ignore? */ |
12681 | (void) section_alignment; | |
cca86cc8 | 12682 | |
a816d1ed AO |
12683 | section_name = xstrdup (section_name); |
12684 | ||
8ab8a5c8 RS |
12685 | /* When using the generic form of .section (as implemented by obj-elf.c), |
12686 | there's no way to set the section type to SHT_MIPS_DWARF. Users have | |
12687 | traditionally had to fall back on the more common @progbits instead. | |
12688 | ||
12689 | There's nothing really harmful in this, since bfd will correct | |
12690 | SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it | |
708587a4 | 12691 | means that, for backwards compatibility, the special_section entries |
8ab8a5c8 RS |
12692 | for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF. |
12693 | ||
12694 | Even so, we shouldn't force users of the MIPS .section syntax to | |
12695 | incorrectly label the sections as SHT_PROGBITS. The best compromise | |
12696 | seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the | |
12697 | generic type-checking code. */ | |
12698 | if (section_type == SHT_MIPS_DWARF) | |
12699 | section_type = SHT_PROGBITS; | |
12700 | ||
cca86cc8 SC |
12701 | obj_elf_change_section (section_name, section_type, section_flag, |
12702 | section_entry_size, 0, 0, 0); | |
a816d1ed AO |
12703 | |
12704 | if (now_seg->name != section_name) | |
12705 | free (section_name); | |
7ed4a06a | 12706 | #endif /* OBJ_ELF */ |
cca86cc8 | 12707 | } |
252b5132 RH |
12708 | |
12709 | void | |
17a2f251 | 12710 | mips_enable_auto_align (void) |
252b5132 RH |
12711 | { |
12712 | auto_align = 1; | |
12713 | } | |
12714 | ||
12715 | static void | |
17a2f251 | 12716 | s_cons (int log_size) |
252b5132 | 12717 | { |
a8dbcb85 TS |
12718 | segment_info_type *si = seg_info (now_seg); |
12719 | struct insn_label_list *l = si->label_list; | |
252b5132 RH |
12720 | symbolS *label; |
12721 | ||
a8dbcb85 | 12722 | label = l != NULL ? l->label : NULL; |
7d10b47d | 12723 | mips_emit_delays (); |
252b5132 RH |
12724 | if (log_size > 0 && auto_align) |
12725 | mips_align (log_size, 0, label); | |
12726 | mips_clear_insn_labels (); | |
12727 | cons (1 << log_size); | |
12728 | } | |
12729 | ||
12730 | static void | |
17a2f251 | 12731 | s_float_cons (int type) |
252b5132 | 12732 | { |
a8dbcb85 TS |
12733 | segment_info_type *si = seg_info (now_seg); |
12734 | struct insn_label_list *l = si->label_list; | |
252b5132 RH |
12735 | symbolS *label; |
12736 | ||
a8dbcb85 | 12737 | label = l != NULL ? l->label : NULL; |
252b5132 | 12738 | |
7d10b47d | 12739 | mips_emit_delays (); |
252b5132 RH |
12740 | |
12741 | if (auto_align) | |
49309057 ILT |
12742 | { |
12743 | if (type == 'd') | |
12744 | mips_align (3, 0, label); | |
12745 | else | |
12746 | mips_align (2, 0, label); | |
12747 | } | |
252b5132 RH |
12748 | |
12749 | mips_clear_insn_labels (); | |
12750 | ||
12751 | float_cons (type); | |
12752 | } | |
12753 | ||
12754 | /* Handle .globl. We need to override it because on Irix 5 you are | |
12755 | permitted to say | |
12756 | .globl foo .text | |
12757 | where foo is an undefined symbol, to mean that foo should be | |
12758 | considered to be the address of a function. */ | |
12759 | ||
12760 | static void | |
17a2f251 | 12761 | s_mips_globl (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
12762 | { |
12763 | char *name; | |
12764 | int c; | |
12765 | symbolS *symbolP; | |
12766 | flagword flag; | |
12767 | ||
8a06b769 | 12768 | do |
252b5132 | 12769 | { |
8a06b769 | 12770 | name = input_line_pointer; |
252b5132 | 12771 | c = get_symbol_end (); |
8a06b769 TS |
12772 | symbolP = symbol_find_or_make (name); |
12773 | S_SET_EXTERNAL (symbolP); | |
12774 | ||
252b5132 | 12775 | *input_line_pointer = c; |
8a06b769 | 12776 | SKIP_WHITESPACE (); |
252b5132 | 12777 | |
8a06b769 TS |
12778 | /* On Irix 5, every global symbol that is not explicitly labelled as |
12779 | being a function is apparently labelled as being an object. */ | |
12780 | flag = BSF_OBJECT; | |
252b5132 | 12781 | |
8a06b769 TS |
12782 | if (!is_end_of_line[(unsigned char) *input_line_pointer] |
12783 | && (*input_line_pointer != ',')) | |
12784 | { | |
12785 | char *secname; | |
12786 | asection *sec; | |
12787 | ||
12788 | secname = input_line_pointer; | |
12789 | c = get_symbol_end (); | |
12790 | sec = bfd_get_section_by_name (stdoutput, secname); | |
12791 | if (sec == NULL) | |
12792 | as_bad (_("%s: no such section"), secname); | |
12793 | *input_line_pointer = c; | |
12794 | ||
12795 | if (sec != NULL && (sec->flags & SEC_CODE) != 0) | |
12796 | flag = BSF_FUNCTION; | |
12797 | } | |
12798 | ||
12799 | symbol_get_bfdsym (symbolP)->flags |= flag; | |
12800 | ||
12801 | c = *input_line_pointer; | |
12802 | if (c == ',') | |
12803 | { | |
12804 | input_line_pointer++; | |
12805 | SKIP_WHITESPACE (); | |
12806 | if (is_end_of_line[(unsigned char) *input_line_pointer]) | |
12807 | c = '\n'; | |
12808 | } | |
12809 | } | |
12810 | while (c == ','); | |
252b5132 | 12811 | |
252b5132 RH |
12812 | demand_empty_rest_of_line (); |
12813 | } | |
12814 | ||
12815 | static void | |
17a2f251 | 12816 | s_option (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
12817 | { |
12818 | char *opt; | |
12819 | char c; | |
12820 | ||
12821 | opt = input_line_pointer; | |
12822 | c = get_symbol_end (); | |
12823 | ||
12824 | if (*opt == 'O') | |
12825 | { | |
12826 | /* FIXME: What does this mean? */ | |
12827 | } | |
12828 | else if (strncmp (opt, "pic", 3) == 0) | |
12829 | { | |
12830 | int i; | |
12831 | ||
12832 | i = atoi (opt + 3); | |
12833 | if (i == 0) | |
12834 | mips_pic = NO_PIC; | |
12835 | else if (i == 2) | |
143d77c5 | 12836 | { |
252b5132 | 12837 | mips_pic = SVR4_PIC; |
143d77c5 EC |
12838 | mips_abicalls = TRUE; |
12839 | } | |
252b5132 RH |
12840 | else |
12841 | as_bad (_(".option pic%d not supported"), i); | |
12842 | ||
4d0d148d | 12843 | if (mips_pic == SVR4_PIC) |
252b5132 RH |
12844 | { |
12845 | if (g_switch_seen && g_switch_value != 0) | |
12846 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
12847 | g_switch_value = 0; | |
12848 | bfd_set_gp_size (stdoutput, 0); | |
12849 | } | |
12850 | } | |
12851 | else | |
12852 | as_warn (_("Unrecognized option \"%s\""), opt); | |
12853 | ||
12854 | *input_line_pointer = c; | |
12855 | demand_empty_rest_of_line (); | |
12856 | } | |
12857 | ||
12858 | /* This structure is used to hold a stack of .set values. */ | |
12859 | ||
e972090a NC |
12860 | struct mips_option_stack |
12861 | { | |
252b5132 RH |
12862 | struct mips_option_stack *next; |
12863 | struct mips_set_options options; | |
12864 | }; | |
12865 | ||
12866 | static struct mips_option_stack *mips_opts_stack; | |
12867 | ||
12868 | /* Handle the .set pseudo-op. */ | |
12869 | ||
12870 | static void | |
17a2f251 | 12871 | s_mipsset (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
12872 | { |
12873 | char *name = input_line_pointer, ch; | |
12874 | ||
12875 | while (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
f9419b05 | 12876 | ++input_line_pointer; |
252b5132 RH |
12877 | ch = *input_line_pointer; |
12878 | *input_line_pointer = '\0'; | |
12879 | ||
12880 | if (strcmp (name, "reorder") == 0) | |
12881 | { | |
7d10b47d RS |
12882 | if (mips_opts.noreorder) |
12883 | end_noreorder (); | |
252b5132 RH |
12884 | } |
12885 | else if (strcmp (name, "noreorder") == 0) | |
12886 | { | |
7d10b47d RS |
12887 | if (!mips_opts.noreorder) |
12888 | start_noreorder (); | |
252b5132 | 12889 | } |
741fe287 MR |
12890 | else if (strncmp (name, "at=", 3) == 0) |
12891 | { | |
12892 | char *s = name + 3; | |
12893 | ||
12894 | if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, &mips_opts.at)) | |
12895 | as_bad (_("Unrecognized register name `%s'"), s); | |
12896 | } | |
252b5132 RH |
12897 | else if (strcmp (name, "at") == 0) |
12898 | { | |
741fe287 | 12899 | mips_opts.at = ATREG; |
252b5132 RH |
12900 | } |
12901 | else if (strcmp (name, "noat") == 0) | |
12902 | { | |
741fe287 | 12903 | mips_opts.at = ZERO; |
252b5132 RH |
12904 | } |
12905 | else if (strcmp (name, "macro") == 0) | |
12906 | { | |
12907 | mips_opts.warn_about_macros = 0; | |
12908 | } | |
12909 | else if (strcmp (name, "nomacro") == 0) | |
12910 | { | |
12911 | if (mips_opts.noreorder == 0) | |
12912 | as_bad (_("`noreorder' must be set before `nomacro'")); | |
12913 | mips_opts.warn_about_macros = 1; | |
12914 | } | |
12915 | else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0) | |
12916 | { | |
12917 | mips_opts.nomove = 0; | |
12918 | } | |
12919 | else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0) | |
12920 | { | |
12921 | mips_opts.nomove = 1; | |
12922 | } | |
12923 | else if (strcmp (name, "bopt") == 0) | |
12924 | { | |
12925 | mips_opts.nobopt = 0; | |
12926 | } | |
12927 | else if (strcmp (name, "nobopt") == 0) | |
12928 | { | |
12929 | mips_opts.nobopt = 1; | |
12930 | } | |
ad3fea08 TS |
12931 | else if (strcmp (name, "gp=default") == 0) |
12932 | mips_opts.gp32 = file_mips_gp32; | |
12933 | else if (strcmp (name, "gp=32") == 0) | |
12934 | mips_opts.gp32 = 1; | |
12935 | else if (strcmp (name, "gp=64") == 0) | |
12936 | { | |
12937 | if (!ISA_HAS_64BIT_REGS (mips_opts.isa)) | |
20203fb9 | 12938 | as_warn (_("%s isa does not support 64-bit registers"), |
ad3fea08 TS |
12939 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
12940 | mips_opts.gp32 = 0; | |
12941 | } | |
12942 | else if (strcmp (name, "fp=default") == 0) | |
12943 | mips_opts.fp32 = file_mips_fp32; | |
12944 | else if (strcmp (name, "fp=32") == 0) | |
12945 | mips_opts.fp32 = 1; | |
12946 | else if (strcmp (name, "fp=64") == 0) | |
12947 | { | |
12948 | if (!ISA_HAS_64BIT_FPRS (mips_opts.isa)) | |
20203fb9 | 12949 | as_warn (_("%s isa does not support 64-bit floating point registers"), |
ad3fea08 TS |
12950 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
12951 | mips_opts.fp32 = 0; | |
12952 | } | |
037b32b9 AN |
12953 | else if (strcmp (name, "softfloat") == 0) |
12954 | mips_opts.soft_float = 1; | |
12955 | else if (strcmp (name, "hardfloat") == 0) | |
12956 | mips_opts.soft_float = 0; | |
12957 | else if (strcmp (name, "singlefloat") == 0) | |
12958 | mips_opts.single_float = 1; | |
12959 | else if (strcmp (name, "doublefloat") == 0) | |
12960 | mips_opts.single_float = 0; | |
252b5132 RH |
12961 | else if (strcmp (name, "mips16") == 0 |
12962 | || strcmp (name, "MIPS-16") == 0) | |
12963 | mips_opts.mips16 = 1; | |
12964 | else if (strcmp (name, "nomips16") == 0 | |
12965 | || strcmp (name, "noMIPS-16") == 0) | |
12966 | mips_opts.mips16 = 0; | |
e16bfa71 TS |
12967 | else if (strcmp (name, "smartmips") == 0) |
12968 | { | |
ad3fea08 | 12969 | if (!ISA_SUPPORTS_SMARTMIPS) |
20203fb9 | 12970 | as_warn (_("%s ISA does not support SmartMIPS ASE"), |
e16bfa71 TS |
12971 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
12972 | mips_opts.ase_smartmips = 1; | |
12973 | } | |
12974 | else if (strcmp (name, "nosmartmips") == 0) | |
12975 | mips_opts.ase_smartmips = 0; | |
1f25f5d3 CD |
12976 | else if (strcmp (name, "mips3d") == 0) |
12977 | mips_opts.ase_mips3d = 1; | |
12978 | else if (strcmp (name, "nomips3d") == 0) | |
12979 | mips_opts.ase_mips3d = 0; | |
a4672219 TS |
12980 | else if (strcmp (name, "mdmx") == 0) |
12981 | mips_opts.ase_mdmx = 1; | |
12982 | else if (strcmp (name, "nomdmx") == 0) | |
12983 | mips_opts.ase_mdmx = 0; | |
74cd071d | 12984 | else if (strcmp (name, "dsp") == 0) |
ad3fea08 TS |
12985 | { |
12986 | if (!ISA_SUPPORTS_DSP_ASE) | |
20203fb9 | 12987 | as_warn (_("%s ISA does not support DSP ASE"), |
ad3fea08 TS |
12988 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
12989 | mips_opts.ase_dsp = 1; | |
8b082fb1 | 12990 | mips_opts.ase_dspr2 = 0; |
ad3fea08 | 12991 | } |
74cd071d | 12992 | else if (strcmp (name, "nodsp") == 0) |
8b082fb1 TS |
12993 | { |
12994 | mips_opts.ase_dsp = 0; | |
12995 | mips_opts.ase_dspr2 = 0; | |
12996 | } | |
12997 | else if (strcmp (name, "dspr2") == 0) | |
12998 | { | |
12999 | if (!ISA_SUPPORTS_DSPR2_ASE) | |
20203fb9 | 13000 | as_warn (_("%s ISA does not support DSP R2 ASE"), |
8b082fb1 TS |
13001 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
13002 | mips_opts.ase_dspr2 = 1; | |
13003 | mips_opts.ase_dsp = 1; | |
13004 | } | |
13005 | else if (strcmp (name, "nodspr2") == 0) | |
13006 | { | |
13007 | mips_opts.ase_dspr2 = 0; | |
13008 | mips_opts.ase_dsp = 0; | |
13009 | } | |
ef2e4d86 | 13010 | else if (strcmp (name, "mt") == 0) |
ad3fea08 TS |
13011 | { |
13012 | if (!ISA_SUPPORTS_MT_ASE) | |
20203fb9 | 13013 | as_warn (_("%s ISA does not support MT ASE"), |
ad3fea08 TS |
13014 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
13015 | mips_opts.ase_mt = 1; | |
13016 | } | |
ef2e4d86 CF |
13017 | else if (strcmp (name, "nomt") == 0) |
13018 | mips_opts.ase_mt = 0; | |
1a2c1fad | 13019 | else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0) |
252b5132 | 13020 | { |
af7ee8bf | 13021 | int reset = 0; |
252b5132 | 13022 | |
1a2c1fad CD |
13023 | /* Permit the user to change the ISA and architecture on the fly. |
13024 | Needless to say, misuse can cause serious problems. */ | |
81a21e38 | 13025 | if (strcmp (name, "mips0") == 0 || strcmp (name, "arch=default") == 0) |
af7ee8bf CD |
13026 | { |
13027 | reset = 1; | |
13028 | mips_opts.isa = file_mips_isa; | |
1a2c1fad | 13029 | mips_opts.arch = file_mips_arch; |
1a2c1fad CD |
13030 | } |
13031 | else if (strncmp (name, "arch=", 5) == 0) | |
13032 | { | |
13033 | const struct mips_cpu_info *p; | |
13034 | ||
13035 | p = mips_parse_cpu("internal use", name + 5); | |
13036 | if (!p) | |
13037 | as_bad (_("unknown architecture %s"), name + 5); | |
13038 | else | |
13039 | { | |
13040 | mips_opts.arch = p->cpu; | |
13041 | mips_opts.isa = p->isa; | |
13042 | } | |
13043 | } | |
81a21e38 TS |
13044 | else if (strncmp (name, "mips", 4) == 0) |
13045 | { | |
13046 | const struct mips_cpu_info *p; | |
13047 | ||
13048 | p = mips_parse_cpu("internal use", name); | |
13049 | if (!p) | |
13050 | as_bad (_("unknown ISA level %s"), name + 4); | |
13051 | else | |
13052 | { | |
13053 | mips_opts.arch = p->cpu; | |
13054 | mips_opts.isa = p->isa; | |
13055 | } | |
13056 | } | |
af7ee8bf | 13057 | else |
81a21e38 | 13058 | as_bad (_("unknown ISA or architecture %s"), name); |
af7ee8bf CD |
13059 | |
13060 | switch (mips_opts.isa) | |
98d3f06f KH |
13061 | { |
13062 | case 0: | |
98d3f06f | 13063 | break; |
af7ee8bf CD |
13064 | case ISA_MIPS1: |
13065 | case ISA_MIPS2: | |
13066 | case ISA_MIPS32: | |
13067 | case ISA_MIPS32R2: | |
98d3f06f KH |
13068 | mips_opts.gp32 = 1; |
13069 | mips_opts.fp32 = 1; | |
13070 | break; | |
af7ee8bf CD |
13071 | case ISA_MIPS3: |
13072 | case ISA_MIPS4: | |
13073 | case ISA_MIPS5: | |
13074 | case ISA_MIPS64: | |
5f74bc13 | 13075 | case ISA_MIPS64R2: |
98d3f06f KH |
13076 | mips_opts.gp32 = 0; |
13077 | mips_opts.fp32 = 0; | |
13078 | break; | |
13079 | default: | |
13080 | as_bad (_("unknown ISA level %s"), name + 4); | |
13081 | break; | |
13082 | } | |
af7ee8bf | 13083 | if (reset) |
98d3f06f | 13084 | { |
af7ee8bf CD |
13085 | mips_opts.gp32 = file_mips_gp32; |
13086 | mips_opts.fp32 = file_mips_fp32; | |
98d3f06f | 13087 | } |
252b5132 RH |
13088 | } |
13089 | else if (strcmp (name, "autoextend") == 0) | |
13090 | mips_opts.noautoextend = 0; | |
13091 | else if (strcmp (name, "noautoextend") == 0) | |
13092 | mips_opts.noautoextend = 1; | |
13093 | else if (strcmp (name, "push") == 0) | |
13094 | { | |
13095 | struct mips_option_stack *s; | |
13096 | ||
13097 | s = (struct mips_option_stack *) xmalloc (sizeof *s); | |
13098 | s->next = mips_opts_stack; | |
13099 | s->options = mips_opts; | |
13100 | mips_opts_stack = s; | |
13101 | } | |
13102 | else if (strcmp (name, "pop") == 0) | |
13103 | { | |
13104 | struct mips_option_stack *s; | |
13105 | ||
13106 | s = mips_opts_stack; | |
13107 | if (s == NULL) | |
13108 | as_bad (_(".set pop with no .set push")); | |
13109 | else | |
13110 | { | |
13111 | /* If we're changing the reorder mode we need to handle | |
13112 | delay slots correctly. */ | |
13113 | if (s->options.noreorder && ! mips_opts.noreorder) | |
7d10b47d | 13114 | start_noreorder (); |
252b5132 | 13115 | else if (! s->options.noreorder && mips_opts.noreorder) |
7d10b47d | 13116 | end_noreorder (); |
252b5132 RH |
13117 | |
13118 | mips_opts = s->options; | |
13119 | mips_opts_stack = s->next; | |
13120 | free (s); | |
13121 | } | |
13122 | } | |
aed1a261 RS |
13123 | else if (strcmp (name, "sym32") == 0) |
13124 | mips_opts.sym32 = TRUE; | |
13125 | else if (strcmp (name, "nosym32") == 0) | |
13126 | mips_opts.sym32 = FALSE; | |
e6559e01 JM |
13127 | else if (strchr (name, ',')) |
13128 | { | |
13129 | /* Generic ".set" directive; use the generic handler. */ | |
13130 | *input_line_pointer = ch; | |
13131 | input_line_pointer = name; | |
13132 | s_set (0); | |
13133 | return; | |
13134 | } | |
252b5132 RH |
13135 | else |
13136 | { | |
13137 | as_warn (_("Tried to set unrecognized symbol: %s\n"), name); | |
13138 | } | |
13139 | *input_line_pointer = ch; | |
13140 | demand_empty_rest_of_line (); | |
13141 | } | |
13142 | ||
13143 | /* Handle the .abicalls pseudo-op. I believe this is equivalent to | |
13144 | .option pic2. It means to generate SVR4 PIC calls. */ | |
13145 | ||
13146 | static void | |
17a2f251 | 13147 | s_abicalls (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
13148 | { |
13149 | mips_pic = SVR4_PIC; | |
143d77c5 | 13150 | mips_abicalls = TRUE; |
4d0d148d TS |
13151 | |
13152 | if (g_switch_seen && g_switch_value != 0) | |
13153 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
13154 | g_switch_value = 0; | |
13155 | ||
252b5132 RH |
13156 | bfd_set_gp_size (stdoutput, 0); |
13157 | demand_empty_rest_of_line (); | |
13158 | } | |
13159 | ||
13160 | /* Handle the .cpload pseudo-op. This is used when generating SVR4 | |
13161 | PIC code. It sets the $gp register for the function based on the | |
13162 | function address, which is in the register named in the argument. | |
13163 | This uses a relocation against _gp_disp, which is handled specially | |
13164 | by the linker. The result is: | |
13165 | lui $gp,%hi(_gp_disp) | |
13166 | addiu $gp,$gp,%lo(_gp_disp) | |
13167 | addu $gp,$gp,.cpload argument | |
aa6975fb ILT |
13168 | The .cpload argument is normally $25 == $t9. |
13169 | ||
13170 | The -mno-shared option changes this to: | |
bbe506e8 TS |
13171 | lui $gp,%hi(__gnu_local_gp) |
13172 | addiu $gp,$gp,%lo(__gnu_local_gp) | |
aa6975fb ILT |
13173 | and the argument is ignored. This saves an instruction, but the |
13174 | resulting code is not position independent; it uses an absolute | |
bbe506e8 TS |
13175 | address for __gnu_local_gp. Thus code assembled with -mno-shared |
13176 | can go into an ordinary executable, but not into a shared library. */ | |
252b5132 RH |
13177 | |
13178 | static void | |
17a2f251 | 13179 | s_cpload (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
13180 | { |
13181 | expressionS ex; | |
aa6975fb ILT |
13182 | int reg; |
13183 | int in_shared; | |
252b5132 | 13184 | |
6478892d TS |
13185 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
13186 | .cpload is ignored. */ | |
13187 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) | |
252b5132 RH |
13188 | { |
13189 | s_ignore (0); | |
13190 | return; | |
13191 | } | |
13192 | ||
d3ecfc59 | 13193 | /* .cpload should be in a .set noreorder section. */ |
252b5132 RH |
13194 | if (mips_opts.noreorder == 0) |
13195 | as_warn (_(".cpload not in noreorder section")); | |
13196 | ||
aa6975fb ILT |
13197 | reg = tc_get_register (0); |
13198 | ||
13199 | /* If we need to produce a 64-bit address, we are better off using | |
13200 | the default instruction sequence. */ | |
aed1a261 | 13201 | in_shared = mips_in_shared || HAVE_64BIT_SYMBOLS; |
aa6975fb | 13202 | |
252b5132 | 13203 | ex.X_op = O_symbol; |
bbe506e8 TS |
13204 | ex.X_add_symbol = symbol_find_or_make (in_shared ? "_gp_disp" : |
13205 | "__gnu_local_gp"); | |
252b5132 RH |
13206 | ex.X_op_symbol = NULL; |
13207 | ex.X_add_number = 0; | |
13208 | ||
13209 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ | |
49309057 | 13210 | symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; |
252b5132 | 13211 | |
584892a6 | 13212 | macro_start (); |
67c0d1eb RS |
13213 | macro_build_lui (&ex, mips_gp_register); |
13214 | macro_build (&ex, "addiu", "t,r,j", mips_gp_register, | |
17a2f251 | 13215 | mips_gp_register, BFD_RELOC_LO16); |
aa6975fb ILT |
13216 | if (in_shared) |
13217 | macro_build (NULL, "addu", "d,v,t", mips_gp_register, | |
13218 | mips_gp_register, reg); | |
584892a6 | 13219 | macro_end (); |
252b5132 RH |
13220 | |
13221 | demand_empty_rest_of_line (); | |
13222 | } | |
13223 | ||
6478892d TS |
13224 | /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is: |
13225 | .cpsetup $reg1, offset|$reg2, label | |
13226 | ||
13227 | If offset is given, this results in: | |
13228 | sd $gp, offset($sp) | |
956cd1d6 | 13229 | lui $gp, %hi(%neg(%gp_rel(label))) |
698b7d9d TS |
13230 | addiu $gp, $gp, %lo(%neg(%gp_rel(label))) |
13231 | daddu $gp, $gp, $reg1 | |
6478892d TS |
13232 | |
13233 | If $reg2 is given, this results in: | |
13234 | daddu $reg2, $gp, $0 | |
956cd1d6 | 13235 | lui $gp, %hi(%neg(%gp_rel(label))) |
698b7d9d TS |
13236 | addiu $gp, $gp, %lo(%neg(%gp_rel(label))) |
13237 | daddu $gp, $gp, $reg1 | |
aa6975fb ILT |
13238 | $reg1 is normally $25 == $t9. |
13239 | ||
13240 | The -mno-shared option replaces the last three instructions with | |
13241 | lui $gp,%hi(_gp) | |
54f4ddb3 | 13242 | addiu $gp,$gp,%lo(_gp) */ |
aa6975fb | 13243 | |
6478892d | 13244 | static void |
17a2f251 | 13245 | s_cpsetup (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
13246 | { |
13247 | expressionS ex_off; | |
13248 | expressionS ex_sym; | |
13249 | int reg1; | |
6478892d | 13250 | |
8586fc66 | 13251 | /* If we are not generating SVR4 PIC code, .cpsetup is ignored. |
6478892d TS |
13252 | We also need NewABI support. */ |
13253 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
13254 | { | |
13255 | s_ignore (0); | |
13256 | return; | |
13257 | } | |
13258 | ||
13259 | reg1 = tc_get_register (0); | |
13260 | SKIP_WHITESPACE (); | |
13261 | if (*input_line_pointer != ',') | |
13262 | { | |
13263 | as_bad (_("missing argument separator ',' for .cpsetup")); | |
13264 | return; | |
13265 | } | |
13266 | else | |
80245285 | 13267 | ++input_line_pointer; |
6478892d TS |
13268 | SKIP_WHITESPACE (); |
13269 | if (*input_line_pointer == '$') | |
80245285 TS |
13270 | { |
13271 | mips_cpreturn_register = tc_get_register (0); | |
13272 | mips_cpreturn_offset = -1; | |
13273 | } | |
6478892d | 13274 | else |
80245285 TS |
13275 | { |
13276 | mips_cpreturn_offset = get_absolute_expression (); | |
13277 | mips_cpreturn_register = -1; | |
13278 | } | |
6478892d TS |
13279 | SKIP_WHITESPACE (); |
13280 | if (*input_line_pointer != ',') | |
13281 | { | |
13282 | as_bad (_("missing argument separator ',' for .cpsetup")); | |
13283 | return; | |
13284 | } | |
13285 | else | |
f9419b05 | 13286 | ++input_line_pointer; |
6478892d | 13287 | SKIP_WHITESPACE (); |
f21f8242 | 13288 | expression (&ex_sym); |
6478892d | 13289 | |
584892a6 | 13290 | macro_start (); |
6478892d TS |
13291 | if (mips_cpreturn_register == -1) |
13292 | { | |
13293 | ex_off.X_op = O_constant; | |
13294 | ex_off.X_add_symbol = NULL; | |
13295 | ex_off.X_op_symbol = NULL; | |
13296 | ex_off.X_add_number = mips_cpreturn_offset; | |
13297 | ||
67c0d1eb | 13298 | macro_build (&ex_off, "sd", "t,o(b)", mips_gp_register, |
17a2f251 | 13299 | BFD_RELOC_LO16, SP); |
6478892d TS |
13300 | } |
13301 | else | |
67c0d1eb | 13302 | macro_build (NULL, "daddu", "d,v,t", mips_cpreturn_register, |
17a2f251 | 13303 | mips_gp_register, 0); |
6478892d | 13304 | |
aed1a261 | 13305 | if (mips_in_shared || HAVE_64BIT_SYMBOLS) |
aa6975fb ILT |
13306 | { |
13307 | macro_build (&ex_sym, "lui", "t,u", mips_gp_register, | |
13308 | -1, BFD_RELOC_GPREL16, BFD_RELOC_MIPS_SUB, | |
13309 | BFD_RELOC_HI16_S); | |
13310 | ||
13311 | macro_build (&ex_sym, "addiu", "t,r,j", mips_gp_register, | |
13312 | mips_gp_register, -1, BFD_RELOC_GPREL16, | |
13313 | BFD_RELOC_MIPS_SUB, BFD_RELOC_LO16); | |
13314 | ||
13315 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register, | |
13316 | mips_gp_register, reg1); | |
13317 | } | |
13318 | else | |
13319 | { | |
13320 | expressionS ex; | |
13321 | ||
13322 | ex.X_op = O_symbol; | |
4184909a | 13323 | ex.X_add_symbol = symbol_find_or_make ("__gnu_local_gp"); |
aa6975fb ILT |
13324 | ex.X_op_symbol = NULL; |
13325 | ex.X_add_number = 0; | |
6e1304d8 | 13326 | |
aa6975fb ILT |
13327 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ |
13328 | symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; | |
13329 | ||
13330 | macro_build_lui (&ex, mips_gp_register); | |
13331 | macro_build (&ex, "addiu", "t,r,j", mips_gp_register, | |
13332 | mips_gp_register, BFD_RELOC_LO16); | |
13333 | } | |
f21f8242 | 13334 | |
584892a6 | 13335 | macro_end (); |
6478892d TS |
13336 | |
13337 | demand_empty_rest_of_line (); | |
13338 | } | |
13339 | ||
13340 | static void | |
17a2f251 | 13341 | s_cplocal (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
13342 | { |
13343 | /* If we are not generating SVR4 PIC code, or if this is not NewABI code, | |
54f4ddb3 | 13344 | .cplocal is ignored. */ |
6478892d TS |
13345 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) |
13346 | { | |
13347 | s_ignore (0); | |
13348 | return; | |
13349 | } | |
13350 | ||
13351 | mips_gp_register = tc_get_register (0); | |
85b51719 | 13352 | demand_empty_rest_of_line (); |
6478892d TS |
13353 | } |
13354 | ||
252b5132 RH |
13355 | /* Handle the .cprestore pseudo-op. This stores $gp into a given |
13356 | offset from $sp. The offset is remembered, and after making a PIC | |
13357 | call $gp is restored from that location. */ | |
13358 | ||
13359 | static void | |
17a2f251 | 13360 | s_cprestore (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
13361 | { |
13362 | expressionS ex; | |
252b5132 | 13363 | |
6478892d | 13364 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
c9914766 | 13365 | .cprestore is ignored. */ |
6478892d | 13366 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) |
252b5132 RH |
13367 | { |
13368 | s_ignore (0); | |
13369 | return; | |
13370 | } | |
13371 | ||
13372 | mips_cprestore_offset = get_absolute_expression (); | |
7a621144 | 13373 | mips_cprestore_valid = 1; |
252b5132 RH |
13374 | |
13375 | ex.X_op = O_constant; | |
13376 | ex.X_add_symbol = NULL; | |
13377 | ex.X_op_symbol = NULL; | |
13378 | ex.X_add_number = mips_cprestore_offset; | |
13379 | ||
584892a6 | 13380 | macro_start (); |
67c0d1eb RS |
13381 | macro_build_ldst_constoffset (&ex, ADDRESS_STORE_INSN, mips_gp_register, |
13382 | SP, HAVE_64BIT_ADDRESSES); | |
584892a6 | 13383 | macro_end (); |
252b5132 RH |
13384 | |
13385 | demand_empty_rest_of_line (); | |
13386 | } | |
13387 | ||
6478892d | 13388 | /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset |
67c1ffbe | 13389 | was given in the preceding .cpsetup, it results in: |
6478892d | 13390 | ld $gp, offset($sp) |
76b3015f | 13391 | |
6478892d | 13392 | If a register $reg2 was given there, it results in: |
54f4ddb3 TS |
13393 | daddu $gp, $reg2, $0 */ |
13394 | ||
6478892d | 13395 | static void |
17a2f251 | 13396 | s_cpreturn (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
13397 | { |
13398 | expressionS ex; | |
6478892d TS |
13399 | |
13400 | /* If we are not generating SVR4 PIC code, .cpreturn is ignored. | |
13401 | We also need NewABI support. */ | |
13402 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
13403 | { | |
13404 | s_ignore (0); | |
13405 | return; | |
13406 | } | |
13407 | ||
584892a6 | 13408 | macro_start (); |
6478892d TS |
13409 | if (mips_cpreturn_register == -1) |
13410 | { | |
13411 | ex.X_op = O_constant; | |
13412 | ex.X_add_symbol = NULL; | |
13413 | ex.X_op_symbol = NULL; | |
13414 | ex.X_add_number = mips_cpreturn_offset; | |
13415 | ||
67c0d1eb | 13416 | macro_build (&ex, "ld", "t,o(b)", mips_gp_register, BFD_RELOC_LO16, SP); |
6478892d TS |
13417 | } |
13418 | else | |
67c0d1eb | 13419 | macro_build (NULL, "daddu", "d,v,t", mips_gp_register, |
17a2f251 | 13420 | mips_cpreturn_register, 0); |
584892a6 | 13421 | macro_end (); |
6478892d TS |
13422 | |
13423 | demand_empty_rest_of_line (); | |
13424 | } | |
13425 | ||
741d6ea8 JM |
13426 | /* Handle the .dtprelword and .dtpreldword pseudo-ops. They generate |
13427 | a 32-bit or 64-bit DTP-relative relocation (BYTES says which) for | |
13428 | use in DWARF debug information. */ | |
13429 | ||
13430 | static void | |
13431 | s_dtprel_internal (size_t bytes) | |
13432 | { | |
13433 | expressionS ex; | |
13434 | char *p; | |
13435 | ||
13436 | expression (&ex); | |
13437 | ||
13438 | if (ex.X_op != O_symbol) | |
13439 | { | |
13440 | as_bad (_("Unsupported use of %s"), (bytes == 8 | |
13441 | ? ".dtpreldword" | |
13442 | : ".dtprelword")); | |
13443 | ignore_rest_of_line (); | |
13444 | } | |
13445 | ||
13446 | p = frag_more (bytes); | |
13447 | md_number_to_chars (p, 0, bytes); | |
13448 | fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, FALSE, | |
13449 | (bytes == 8 | |
13450 | ? BFD_RELOC_MIPS_TLS_DTPREL64 | |
13451 | : BFD_RELOC_MIPS_TLS_DTPREL32)); | |
13452 | ||
13453 | demand_empty_rest_of_line (); | |
13454 | } | |
13455 | ||
13456 | /* Handle .dtprelword. */ | |
13457 | ||
13458 | static void | |
13459 | s_dtprelword (int ignore ATTRIBUTE_UNUSED) | |
13460 | { | |
13461 | s_dtprel_internal (4); | |
13462 | } | |
13463 | ||
13464 | /* Handle .dtpreldword. */ | |
13465 | ||
13466 | static void | |
13467 | s_dtpreldword (int ignore ATTRIBUTE_UNUSED) | |
13468 | { | |
13469 | s_dtprel_internal (8); | |
13470 | } | |
13471 | ||
6478892d TS |
13472 | /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC |
13473 | code. It sets the offset to use in gp_rel relocations. */ | |
13474 | ||
13475 | static void | |
17a2f251 | 13476 | s_gpvalue (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
13477 | { |
13478 | /* If we are not generating SVR4 PIC code, .gpvalue is ignored. | |
13479 | We also need NewABI support. */ | |
13480 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
13481 | { | |
13482 | s_ignore (0); | |
13483 | return; | |
13484 | } | |
13485 | ||
def2e0dd | 13486 | mips_gprel_offset = get_absolute_expression (); |
6478892d TS |
13487 | |
13488 | demand_empty_rest_of_line (); | |
13489 | } | |
13490 | ||
252b5132 RH |
13491 | /* Handle the .gpword pseudo-op. This is used when generating PIC |
13492 | code. It generates a 32 bit GP relative reloc. */ | |
13493 | ||
13494 | static void | |
17a2f251 | 13495 | s_gpword (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 13496 | { |
a8dbcb85 TS |
13497 | segment_info_type *si; |
13498 | struct insn_label_list *l; | |
252b5132 RH |
13499 | symbolS *label; |
13500 | expressionS ex; | |
13501 | char *p; | |
13502 | ||
13503 | /* When not generating PIC code, this is treated as .word. */ | |
13504 | if (mips_pic != SVR4_PIC) | |
13505 | { | |
13506 | s_cons (2); | |
13507 | return; | |
13508 | } | |
13509 | ||
a8dbcb85 TS |
13510 | si = seg_info (now_seg); |
13511 | l = si->label_list; | |
13512 | label = l != NULL ? l->label : NULL; | |
7d10b47d | 13513 | mips_emit_delays (); |
252b5132 RH |
13514 | if (auto_align) |
13515 | mips_align (2, 0, label); | |
13516 | mips_clear_insn_labels (); | |
13517 | ||
13518 | expression (&ex); | |
13519 | ||
13520 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
13521 | { | |
13522 | as_bad (_("Unsupported use of .gpword")); | |
13523 | ignore_rest_of_line (); | |
13524 | } | |
13525 | ||
13526 | p = frag_more (4); | |
17a2f251 | 13527 | md_number_to_chars (p, 0, 4); |
b34976b6 | 13528 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, |
cdf6fd85 | 13529 | BFD_RELOC_GPREL32); |
252b5132 RH |
13530 | |
13531 | demand_empty_rest_of_line (); | |
13532 | } | |
13533 | ||
10181a0d | 13534 | static void |
17a2f251 | 13535 | s_gpdword (int ignore ATTRIBUTE_UNUSED) |
10181a0d | 13536 | { |
a8dbcb85 TS |
13537 | segment_info_type *si; |
13538 | struct insn_label_list *l; | |
10181a0d AO |
13539 | symbolS *label; |
13540 | expressionS ex; | |
13541 | char *p; | |
13542 | ||
13543 | /* When not generating PIC code, this is treated as .dword. */ | |
13544 | if (mips_pic != SVR4_PIC) | |
13545 | { | |
13546 | s_cons (3); | |
13547 | return; | |
13548 | } | |
13549 | ||
a8dbcb85 TS |
13550 | si = seg_info (now_seg); |
13551 | l = si->label_list; | |
13552 | label = l != NULL ? l->label : NULL; | |
7d10b47d | 13553 | mips_emit_delays (); |
10181a0d AO |
13554 | if (auto_align) |
13555 | mips_align (3, 0, label); | |
13556 | mips_clear_insn_labels (); | |
13557 | ||
13558 | expression (&ex); | |
13559 | ||
13560 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
13561 | { | |
13562 | as_bad (_("Unsupported use of .gpdword")); | |
13563 | ignore_rest_of_line (); | |
13564 | } | |
13565 | ||
13566 | p = frag_more (8); | |
17a2f251 | 13567 | md_number_to_chars (p, 0, 8); |
a105a300 | 13568 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, |
6e1304d8 | 13569 | BFD_RELOC_GPREL32)->fx_tcbit = 1; |
10181a0d AO |
13570 | |
13571 | /* GPREL32 composed with 64 gives a 64-bit GP offset. */ | |
6e1304d8 RS |
13572 | fix_new (frag_now, p - frag_now->fr_literal, 8, NULL, 0, |
13573 | FALSE, BFD_RELOC_64)->fx_tcbit = 1; | |
10181a0d AO |
13574 | |
13575 | demand_empty_rest_of_line (); | |
13576 | } | |
13577 | ||
252b5132 RH |
13578 | /* Handle the .cpadd pseudo-op. This is used when dealing with switch |
13579 | tables in SVR4 PIC code. */ | |
13580 | ||
13581 | static void | |
17a2f251 | 13582 | s_cpadd (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 13583 | { |
252b5132 RH |
13584 | int reg; |
13585 | ||
10181a0d AO |
13586 | /* This is ignored when not generating SVR4 PIC code. */ |
13587 | if (mips_pic != SVR4_PIC) | |
252b5132 RH |
13588 | { |
13589 | s_ignore (0); | |
13590 | return; | |
13591 | } | |
13592 | ||
13593 | /* Add $gp to the register named as an argument. */ | |
584892a6 | 13594 | macro_start (); |
252b5132 | 13595 | reg = tc_get_register (0); |
67c0d1eb | 13596 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register); |
584892a6 | 13597 | macro_end (); |
252b5132 | 13598 | |
bdaaa2e1 | 13599 | demand_empty_rest_of_line (); |
252b5132 RH |
13600 | } |
13601 | ||
13602 | /* Handle the .insn pseudo-op. This marks instruction labels in | |
13603 | mips16 mode. This permits the linker to handle them specially, | |
13604 | such as generating jalx instructions when needed. We also make | |
13605 | them odd for the duration of the assembly, in order to generate the | |
13606 | right sort of code. We will make them even in the adjust_symtab | |
13607 | routine, while leaving them marked. This is convenient for the | |
13608 | debugger and the disassembler. The linker knows to make them odd | |
13609 | again. */ | |
13610 | ||
13611 | static void | |
17a2f251 | 13612 | s_insn (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 13613 | { |
f9419b05 | 13614 | mips16_mark_labels (); |
252b5132 RH |
13615 | |
13616 | demand_empty_rest_of_line (); | |
13617 | } | |
13618 | ||
13619 | /* Handle a .stabn directive. We need these in order to mark a label | |
13620 | as being a mips16 text label correctly. Sometimes the compiler | |
13621 | will emit a label, followed by a .stabn, and then switch sections. | |
13622 | If the label and .stabn are in mips16 mode, then the label is | |
13623 | really a mips16 text label. */ | |
13624 | ||
13625 | static void | |
17a2f251 | 13626 | s_mips_stab (int type) |
252b5132 | 13627 | { |
f9419b05 | 13628 | if (type == 'n') |
252b5132 RH |
13629 | mips16_mark_labels (); |
13630 | ||
13631 | s_stab (type); | |
13632 | } | |
13633 | ||
54f4ddb3 | 13634 | /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */ |
252b5132 RH |
13635 | |
13636 | static void | |
17a2f251 | 13637 | s_mips_weakext (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
13638 | { |
13639 | char *name; | |
13640 | int c; | |
13641 | symbolS *symbolP; | |
13642 | expressionS exp; | |
13643 | ||
13644 | name = input_line_pointer; | |
13645 | c = get_symbol_end (); | |
13646 | symbolP = symbol_find_or_make (name); | |
13647 | S_SET_WEAK (symbolP); | |
13648 | *input_line_pointer = c; | |
13649 | ||
13650 | SKIP_WHITESPACE (); | |
13651 | ||
13652 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
13653 | { | |
13654 | if (S_IS_DEFINED (symbolP)) | |
13655 | { | |
20203fb9 | 13656 | as_bad (_("ignoring attempt to redefine symbol %s"), |
252b5132 RH |
13657 | S_GET_NAME (symbolP)); |
13658 | ignore_rest_of_line (); | |
13659 | return; | |
13660 | } | |
bdaaa2e1 | 13661 | |
252b5132 RH |
13662 | if (*input_line_pointer == ',') |
13663 | { | |
13664 | ++input_line_pointer; | |
13665 | SKIP_WHITESPACE (); | |
13666 | } | |
bdaaa2e1 | 13667 | |
252b5132 RH |
13668 | expression (&exp); |
13669 | if (exp.X_op != O_symbol) | |
13670 | { | |
20203fb9 | 13671 | as_bad (_("bad .weakext directive")); |
98d3f06f | 13672 | ignore_rest_of_line (); |
252b5132 RH |
13673 | return; |
13674 | } | |
49309057 | 13675 | symbol_set_value_expression (symbolP, &exp); |
252b5132 RH |
13676 | } |
13677 | ||
13678 | demand_empty_rest_of_line (); | |
13679 | } | |
13680 | ||
13681 | /* Parse a register string into a number. Called from the ECOFF code | |
13682 | to parse .frame. The argument is non-zero if this is the frame | |
13683 | register, so that we can record it in mips_frame_reg. */ | |
13684 | ||
13685 | int | |
17a2f251 | 13686 | tc_get_register (int frame) |
252b5132 | 13687 | { |
707bfff6 | 13688 | unsigned int reg; |
252b5132 RH |
13689 | |
13690 | SKIP_WHITESPACE (); | |
707bfff6 TS |
13691 | if (! reg_lookup (&input_line_pointer, RWARN | RTYPE_NUM | RTYPE_GP, ®)) |
13692 | reg = 0; | |
252b5132 | 13693 | if (frame) |
7a621144 DJ |
13694 | { |
13695 | mips_frame_reg = reg != 0 ? reg : SP; | |
13696 | mips_frame_reg_valid = 1; | |
13697 | mips_cprestore_valid = 0; | |
13698 | } | |
252b5132 RH |
13699 | return reg; |
13700 | } | |
13701 | ||
13702 | valueT | |
17a2f251 | 13703 | md_section_align (asection *seg, valueT addr) |
252b5132 RH |
13704 | { |
13705 | int align = bfd_get_section_alignment (stdoutput, seg); | |
13706 | ||
b4c71f56 TS |
13707 | if (IS_ELF) |
13708 | { | |
13709 | /* We don't need to align ELF sections to the full alignment. | |
13710 | However, Irix 5 may prefer that we align them at least to a 16 | |
13711 | byte boundary. We don't bother to align the sections if we | |
13712 | are targeted for an embedded system. */ | |
c41e87e3 | 13713 | if (strncmp (TARGET_OS, "elf", 3) == 0) |
b4c71f56 TS |
13714 | return addr; |
13715 | if (align > 4) | |
13716 | align = 4; | |
13717 | } | |
252b5132 RH |
13718 | |
13719 | return ((addr + (1 << align) - 1) & (-1 << align)); | |
13720 | } | |
13721 | ||
13722 | /* Utility routine, called from above as well. If called while the | |
13723 | input file is still being read, it's only an approximation. (For | |
13724 | example, a symbol may later become defined which appeared to be | |
13725 | undefined earlier.) */ | |
13726 | ||
13727 | static int | |
17a2f251 | 13728 | nopic_need_relax (symbolS *sym, int before_relaxing) |
252b5132 RH |
13729 | { |
13730 | if (sym == 0) | |
13731 | return 0; | |
13732 | ||
4d0d148d | 13733 | if (g_switch_value > 0) |
252b5132 RH |
13734 | { |
13735 | const char *symname; | |
13736 | int change; | |
13737 | ||
c9914766 | 13738 | /* Find out whether this symbol can be referenced off the $gp |
252b5132 RH |
13739 | register. It can be if it is smaller than the -G size or if |
13740 | it is in the .sdata or .sbss section. Certain symbols can | |
c9914766 | 13741 | not be referenced off the $gp, although it appears as though |
252b5132 RH |
13742 | they can. */ |
13743 | symname = S_GET_NAME (sym); | |
13744 | if (symname != (const char *) NULL | |
13745 | && (strcmp (symname, "eprol") == 0 | |
13746 | || strcmp (symname, "etext") == 0 | |
13747 | || strcmp (symname, "_gp") == 0 | |
13748 | || strcmp (symname, "edata") == 0 | |
13749 | || strcmp (symname, "_fbss") == 0 | |
13750 | || strcmp (symname, "_fdata") == 0 | |
13751 | || strcmp (symname, "_ftext") == 0 | |
13752 | || strcmp (symname, "end") == 0 | |
13753 | || strcmp (symname, "_gp_disp") == 0)) | |
13754 | change = 1; | |
13755 | else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym)) | |
13756 | && (0 | |
13757 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 ILT |
13758 | || (symbol_get_obj (sym)->ecoff_extern_size != 0 |
13759 | && (symbol_get_obj (sym)->ecoff_extern_size | |
13760 | <= g_switch_value)) | |
252b5132 RH |
13761 | #endif |
13762 | /* We must defer this decision until after the whole | |
13763 | file has been read, since there might be a .extern | |
13764 | after the first use of this symbol. */ | |
13765 | || (before_relaxing | |
13766 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 | 13767 | && symbol_get_obj (sym)->ecoff_extern_size == 0 |
252b5132 RH |
13768 | #endif |
13769 | && S_GET_VALUE (sym) == 0) | |
13770 | || (S_GET_VALUE (sym) != 0 | |
13771 | && S_GET_VALUE (sym) <= g_switch_value))) | |
13772 | change = 0; | |
13773 | else | |
13774 | { | |
13775 | const char *segname; | |
13776 | ||
13777 | segname = segment_name (S_GET_SEGMENT (sym)); | |
9c2799c2 | 13778 | gas_assert (strcmp (segname, ".lit8") != 0 |
252b5132 RH |
13779 | && strcmp (segname, ".lit4") != 0); |
13780 | change = (strcmp (segname, ".sdata") != 0 | |
fba2b7f9 GK |
13781 | && strcmp (segname, ".sbss") != 0 |
13782 | && strncmp (segname, ".sdata.", 7) != 0 | |
d4dc2f22 TS |
13783 | && strncmp (segname, ".sbss.", 6) != 0 |
13784 | && strncmp (segname, ".gnu.linkonce.sb.", 17) != 0 | |
fba2b7f9 | 13785 | && strncmp (segname, ".gnu.linkonce.s.", 16) != 0); |
252b5132 RH |
13786 | } |
13787 | return change; | |
13788 | } | |
13789 | else | |
c9914766 | 13790 | /* We are not optimizing for the $gp register. */ |
252b5132 RH |
13791 | return 1; |
13792 | } | |
13793 | ||
5919d012 RS |
13794 | |
13795 | /* Return true if the given symbol should be considered local for SVR4 PIC. */ | |
13796 | ||
13797 | static bfd_boolean | |
17a2f251 | 13798 | pic_need_relax (symbolS *sym, asection *segtype) |
5919d012 RS |
13799 | { |
13800 | asection *symsec; | |
5919d012 RS |
13801 | |
13802 | /* Handle the case of a symbol equated to another symbol. */ | |
13803 | while (symbol_equated_reloc_p (sym)) | |
13804 | { | |
13805 | symbolS *n; | |
13806 | ||
5f0fe04b | 13807 | /* It's possible to get a loop here in a badly written program. */ |
5919d012 RS |
13808 | n = symbol_get_value_expression (sym)->X_add_symbol; |
13809 | if (n == sym) | |
13810 | break; | |
13811 | sym = n; | |
13812 | } | |
13813 | ||
df1f3cda DD |
13814 | if (symbol_section_p (sym)) |
13815 | return TRUE; | |
13816 | ||
5919d012 RS |
13817 | symsec = S_GET_SEGMENT (sym); |
13818 | ||
5919d012 RS |
13819 | /* This must duplicate the test in adjust_reloc_syms. */ |
13820 | return (symsec != &bfd_und_section | |
13821 | && symsec != &bfd_abs_section | |
5f0fe04b TS |
13822 | && !bfd_is_com_section (symsec) |
13823 | && !s_is_linkonce (sym, segtype) | |
5919d012 RS |
13824 | #ifdef OBJ_ELF |
13825 | /* A global or weak symbol is treated as external. */ | |
f43abd2b | 13826 | && (!IS_ELF || (! S_IS_WEAK (sym) && ! S_IS_EXTERNAL (sym))) |
5919d012 RS |
13827 | #endif |
13828 | ); | |
13829 | } | |
13830 | ||
13831 | ||
252b5132 RH |
13832 | /* Given a mips16 variant frag FRAGP, return non-zero if it needs an |
13833 | extended opcode. SEC is the section the frag is in. */ | |
13834 | ||
13835 | static int | |
17a2f251 | 13836 | mips16_extended_frag (fragS *fragp, asection *sec, long stretch) |
252b5132 RH |
13837 | { |
13838 | int type; | |
3994f87e | 13839 | const struct mips16_immed_operand *op; |
252b5132 RH |
13840 | offsetT val; |
13841 | int mintiny, maxtiny; | |
13842 | segT symsec; | |
98aa84af | 13843 | fragS *sym_frag; |
252b5132 RH |
13844 | |
13845 | if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype)) | |
13846 | return 0; | |
13847 | if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype)) | |
13848 | return 1; | |
13849 | ||
13850 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
13851 | op = mips16_immed_operands; | |
13852 | while (op->type != type) | |
13853 | { | |
13854 | ++op; | |
9c2799c2 | 13855 | gas_assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); |
252b5132 RH |
13856 | } |
13857 | ||
13858 | if (op->unsp) | |
13859 | { | |
13860 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
13861 | { | |
13862 | mintiny = 1; | |
13863 | maxtiny = 1 << op->nbits; | |
13864 | } | |
13865 | else | |
13866 | { | |
13867 | mintiny = 0; | |
13868 | maxtiny = (1 << op->nbits) - 1; | |
13869 | } | |
13870 | } | |
13871 | else | |
13872 | { | |
13873 | mintiny = - (1 << (op->nbits - 1)); | |
13874 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
13875 | } | |
13876 | ||
98aa84af | 13877 | sym_frag = symbol_get_frag (fragp->fr_symbol); |
ac62c346 | 13878 | val = S_GET_VALUE (fragp->fr_symbol); |
98aa84af | 13879 | symsec = S_GET_SEGMENT (fragp->fr_symbol); |
252b5132 RH |
13880 | |
13881 | if (op->pcrel) | |
13882 | { | |
13883 | addressT addr; | |
13884 | ||
13885 | /* We won't have the section when we are called from | |
13886 | mips_relax_frag. However, we will always have been called | |
13887 | from md_estimate_size_before_relax first. If this is a | |
13888 | branch to a different section, we mark it as such. If SEC is | |
13889 | NULL, and the frag is not marked, then it must be a branch to | |
13890 | the same section. */ | |
13891 | if (sec == NULL) | |
13892 | { | |
13893 | if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype)) | |
13894 | return 1; | |
13895 | } | |
13896 | else | |
13897 | { | |
98aa84af | 13898 | /* Must have been called from md_estimate_size_before_relax. */ |
252b5132 RH |
13899 | if (symsec != sec) |
13900 | { | |
13901 | fragp->fr_subtype = | |
13902 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
13903 | ||
13904 | /* FIXME: We should support this, and let the linker | |
13905 | catch branches and loads that are out of range. */ | |
13906 | as_bad_where (fragp->fr_file, fragp->fr_line, | |
13907 | _("unsupported PC relative reference to different section")); | |
13908 | ||
13909 | return 1; | |
13910 | } | |
98aa84af AM |
13911 | if (fragp != sym_frag && sym_frag->fr_address == 0) |
13912 | /* Assume non-extended on the first relaxation pass. | |
13913 | The address we have calculated will be bogus if this is | |
13914 | a forward branch to another frag, as the forward frag | |
13915 | will have fr_address == 0. */ | |
13916 | return 0; | |
252b5132 RH |
13917 | } |
13918 | ||
13919 | /* In this case, we know for sure that the symbol fragment is in | |
98aa84af AM |
13920 | the same section. If the relax_marker of the symbol fragment |
13921 | differs from the relax_marker of this fragment, we have not | |
13922 | yet adjusted the symbol fragment fr_address. We want to add | |
252b5132 RH |
13923 | in STRETCH in order to get a better estimate of the address. |
13924 | This particularly matters because of the shift bits. */ | |
13925 | if (stretch != 0 | |
98aa84af | 13926 | && sym_frag->relax_marker != fragp->relax_marker) |
252b5132 RH |
13927 | { |
13928 | fragS *f; | |
13929 | ||
13930 | /* Adjust stretch for any alignment frag. Note that if have | |
13931 | been expanding the earlier code, the symbol may be | |
13932 | defined in what appears to be an earlier frag. FIXME: | |
13933 | This doesn't handle the fr_subtype field, which specifies | |
13934 | a maximum number of bytes to skip when doing an | |
13935 | alignment. */ | |
98aa84af | 13936 | for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next) |
252b5132 RH |
13937 | { |
13938 | if (f->fr_type == rs_align || f->fr_type == rs_align_code) | |
13939 | { | |
13940 | if (stretch < 0) | |
13941 | stretch = - ((- stretch) | |
13942 | & ~ ((1 << (int) f->fr_offset) - 1)); | |
13943 | else | |
13944 | stretch &= ~ ((1 << (int) f->fr_offset) - 1); | |
13945 | if (stretch == 0) | |
13946 | break; | |
13947 | } | |
13948 | } | |
13949 | if (f != NULL) | |
13950 | val += stretch; | |
13951 | } | |
13952 | ||
13953 | addr = fragp->fr_address + fragp->fr_fix; | |
13954 | ||
13955 | /* The base address rules are complicated. The base address of | |
13956 | a branch is the following instruction. The base address of a | |
13957 | PC relative load or add is the instruction itself, but if it | |
13958 | is in a delay slot (in which case it can not be extended) use | |
13959 | the address of the instruction whose delay slot it is in. */ | |
13960 | if (type == 'p' || type == 'q') | |
13961 | { | |
13962 | addr += 2; | |
13963 | ||
13964 | /* If we are currently assuming that this frag should be | |
13965 | extended, then, the current address is two bytes | |
bdaaa2e1 | 13966 | higher. */ |
252b5132 RH |
13967 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) |
13968 | addr += 2; | |
13969 | ||
13970 | /* Ignore the low bit in the target, since it will be set | |
13971 | for a text label. */ | |
13972 | if ((val & 1) != 0) | |
13973 | --val; | |
13974 | } | |
13975 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) | |
13976 | addr -= 4; | |
13977 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
13978 | addr -= 2; | |
13979 | ||
13980 | val -= addr & ~ ((1 << op->shift) - 1); | |
13981 | ||
13982 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
13983 | if (type == 'p' || type == 'q') | |
13984 | val /= 2; | |
13985 | ||
13986 | /* If any of the shifted bits are set, we must use an extended | |
13987 | opcode. If the address depends on the size of this | |
13988 | instruction, this can lead to a loop, so we arrange to always | |
13989 | use an extended opcode. We only check this when we are in | |
13990 | the main relaxation loop, when SEC is NULL. */ | |
13991 | if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL) | |
13992 | { | |
13993 | fragp->fr_subtype = | |
13994 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
13995 | return 1; | |
13996 | } | |
13997 | ||
13998 | /* If we are about to mark a frag as extended because the value | |
13999 | is precisely maxtiny + 1, then there is a chance of an | |
14000 | infinite loop as in the following code: | |
14001 | la $4,foo | |
14002 | .skip 1020 | |
14003 | .align 2 | |
14004 | foo: | |
14005 | In this case when the la is extended, foo is 0x3fc bytes | |
14006 | away, so the la can be shrunk, but then foo is 0x400 away, so | |
14007 | the la must be extended. To avoid this loop, we mark the | |
14008 | frag as extended if it was small, and is about to become | |
14009 | extended with a value of maxtiny + 1. */ | |
14010 | if (val == ((maxtiny + 1) << op->shift) | |
14011 | && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype) | |
14012 | && sec == NULL) | |
14013 | { | |
14014 | fragp->fr_subtype = | |
14015 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
14016 | return 1; | |
14017 | } | |
14018 | } | |
14019 | else if (symsec != absolute_section && sec != NULL) | |
14020 | as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation")); | |
14021 | ||
14022 | if ((val & ((1 << op->shift) - 1)) != 0 | |
14023 | || val < (mintiny << op->shift) | |
14024 | || val > (maxtiny << op->shift)) | |
14025 | return 1; | |
14026 | else | |
14027 | return 0; | |
14028 | } | |
14029 | ||
4a6a3df4 AO |
14030 | /* Compute the length of a branch sequence, and adjust the |
14031 | RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the | |
14032 | worst-case length is computed, with UPDATE being used to indicate | |
14033 | whether an unconditional (-1), branch-likely (+1) or regular (0) | |
14034 | branch is to be computed. */ | |
14035 | static int | |
17a2f251 | 14036 | relaxed_branch_length (fragS *fragp, asection *sec, int update) |
4a6a3df4 | 14037 | { |
b34976b6 | 14038 | bfd_boolean toofar; |
4a6a3df4 AO |
14039 | int length; |
14040 | ||
14041 | if (fragp | |
14042 | && S_IS_DEFINED (fragp->fr_symbol) | |
14043 | && sec == S_GET_SEGMENT (fragp->fr_symbol)) | |
14044 | { | |
14045 | addressT addr; | |
14046 | offsetT val; | |
14047 | ||
14048 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; | |
14049 | ||
14050 | addr = fragp->fr_address + fragp->fr_fix + 4; | |
14051 | ||
14052 | val -= addr; | |
14053 | ||
14054 | toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2); | |
14055 | } | |
14056 | else if (fragp) | |
14057 | /* If the symbol is not defined or it's in a different segment, | |
14058 | assume the user knows what's going on and emit a short | |
14059 | branch. */ | |
b34976b6 | 14060 | toofar = FALSE; |
4a6a3df4 | 14061 | else |
b34976b6 | 14062 | toofar = TRUE; |
4a6a3df4 AO |
14063 | |
14064 | if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) | |
14065 | fragp->fr_subtype | |
af6ae2ad | 14066 | = RELAX_BRANCH_ENCODE (RELAX_BRANCH_UNCOND (fragp->fr_subtype), |
4a6a3df4 AO |
14067 | RELAX_BRANCH_LIKELY (fragp->fr_subtype), |
14068 | RELAX_BRANCH_LINK (fragp->fr_subtype), | |
14069 | toofar); | |
14070 | ||
14071 | length = 4; | |
14072 | if (toofar) | |
14073 | { | |
14074 | if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0)) | |
14075 | length += 8; | |
14076 | ||
14077 | if (mips_pic != NO_PIC) | |
14078 | { | |
14079 | /* Additional space for PIC loading of target address. */ | |
14080 | length += 8; | |
14081 | if (mips_opts.isa == ISA_MIPS1) | |
14082 | /* Additional space for $at-stabilizing nop. */ | |
14083 | length += 4; | |
14084 | } | |
14085 | ||
14086 | /* If branch is conditional. */ | |
14087 | if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0)) | |
14088 | length += 8; | |
14089 | } | |
b34976b6 | 14090 | |
4a6a3df4 AO |
14091 | return length; |
14092 | } | |
14093 | ||
252b5132 RH |
14094 | /* Estimate the size of a frag before relaxing. Unless this is the |
14095 | mips16, we are not really relaxing here, and the final size is | |
14096 | encoded in the subtype information. For the mips16, we have to | |
14097 | decide whether we are using an extended opcode or not. */ | |
14098 | ||
252b5132 | 14099 | int |
17a2f251 | 14100 | md_estimate_size_before_relax (fragS *fragp, asection *segtype) |
252b5132 | 14101 | { |
5919d012 | 14102 | int change; |
252b5132 | 14103 | |
4a6a3df4 AO |
14104 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
14105 | { | |
14106 | ||
b34976b6 AM |
14107 | fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE); |
14108 | ||
4a6a3df4 AO |
14109 | return fragp->fr_var; |
14110 | } | |
14111 | ||
252b5132 | 14112 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
177b4a6a AO |
14113 | /* We don't want to modify the EXTENDED bit here; it might get us |
14114 | into infinite loops. We change it only in mips_relax_frag(). */ | |
14115 | return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2); | |
252b5132 RH |
14116 | |
14117 | if (mips_pic == NO_PIC) | |
5919d012 | 14118 | change = nopic_need_relax (fragp->fr_symbol, 0); |
252b5132 | 14119 | else if (mips_pic == SVR4_PIC) |
5919d012 | 14120 | change = pic_need_relax (fragp->fr_symbol, segtype); |
0a44bf69 RS |
14121 | else if (mips_pic == VXWORKS_PIC) |
14122 | /* For vxworks, GOT16 relocations never have a corresponding LO16. */ | |
14123 | change = 0; | |
252b5132 RH |
14124 | else |
14125 | abort (); | |
14126 | ||
14127 | if (change) | |
14128 | { | |
4d7206a2 | 14129 | fragp->fr_subtype |= RELAX_USE_SECOND; |
4d7206a2 | 14130 | return -RELAX_FIRST (fragp->fr_subtype); |
252b5132 | 14131 | } |
4d7206a2 RS |
14132 | else |
14133 | return -RELAX_SECOND (fragp->fr_subtype); | |
252b5132 RH |
14134 | } |
14135 | ||
14136 | /* This is called to see whether a reloc against a defined symbol | |
de7e6852 | 14137 | should be converted into a reloc against a section. */ |
252b5132 RH |
14138 | |
14139 | int | |
17a2f251 | 14140 | mips_fix_adjustable (fixS *fixp) |
252b5132 | 14141 | { |
252b5132 RH |
14142 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
14143 | || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
14144 | return 0; | |
a161fe53 | 14145 | |
252b5132 RH |
14146 | if (fixp->fx_addsy == NULL) |
14147 | return 1; | |
a161fe53 | 14148 | |
de7e6852 RS |
14149 | /* If symbol SYM is in a mergeable section, relocations of the form |
14150 | SYM + 0 can usually be made section-relative. The mergeable data | |
14151 | is then identified by the section offset rather than by the symbol. | |
14152 | ||
14153 | However, if we're generating REL LO16 relocations, the offset is split | |
14154 | between the LO16 and parterning high part relocation. The linker will | |
14155 | need to recalculate the complete offset in order to correctly identify | |
14156 | the merge data. | |
14157 | ||
14158 | The linker has traditionally not looked for the parterning high part | |
14159 | relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be | |
14160 | placed anywhere. Rather than break backwards compatibility by changing | |
14161 | this, it seems better not to force the issue, and instead keep the | |
14162 | original symbol. This will work with either linker behavior. */ | |
738e5348 | 14163 | if ((lo16_reloc_p (fixp->fx_r_type) |
704803a9 | 14164 | || reloc_needs_lo_p (fixp->fx_r_type)) |
de7e6852 RS |
14165 | && HAVE_IN_PLACE_ADDENDS |
14166 | && (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_MERGE) != 0) | |
14167 | return 0; | |
14168 | ||
1180b5a4 RS |
14169 | /* There is no place to store an in-place offset for JALR relocations. */ |
14170 | if (fixp->fx_r_type == BFD_RELOC_MIPS_JALR && HAVE_IN_PLACE_ADDENDS) | |
14171 | return 0; | |
14172 | ||
252b5132 | 14173 | #ifdef OBJ_ELF |
b314ec0e RS |
14174 | /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve |
14175 | to a floating-point stub. The same is true for non-R_MIPS16_26 | |
14176 | relocations against MIPS16 functions; in this case, the stub becomes | |
14177 | the function's canonical address. | |
14178 | ||
14179 | Floating-point stubs are stored in unique .mips16.call.* or | |
14180 | .mips16.fn.* sections. If a stub T for function F is in section S, | |
14181 | the first relocation in section S must be against F; this is how the | |
14182 | linker determines the target function. All relocations that might | |
14183 | resolve to T must also be against F. We therefore have the following | |
14184 | restrictions, which are given in an intentionally-redundant way: | |
14185 | ||
14186 | 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16 | |
14187 | symbols. | |
14188 | ||
14189 | 2. We cannot reduce a stub's relocations against non-MIPS16 symbols | |
14190 | if that stub might be used. | |
14191 | ||
14192 | 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16 | |
14193 | symbols. | |
14194 | ||
14195 | 4. We cannot reduce a stub's relocations against MIPS16 symbols if | |
14196 | that stub might be used. | |
14197 | ||
14198 | There is a further restriction: | |
14199 | ||
14200 | 5. We cannot reduce R_MIPS16_26 relocations against MIPS16 symbols | |
14201 | on targets with in-place addends; the relocation field cannot | |
14202 | encode the low bit. | |
14203 | ||
14204 | For simplicity, we deal with (3)-(5) by not reducing _any_ relocation | |
14205 | against a MIPS16 symbol. | |
14206 | ||
14207 | We deal with (1)-(2) by saying that, if there's a R_MIPS16_26 | |
14208 | relocation against some symbol R, no relocation against R may be | |
14209 | reduced. (Note that this deals with (2) as well as (1) because | |
14210 | relocations against global symbols will never be reduced on ELF | |
14211 | targets.) This approach is a little simpler than trying to detect | |
14212 | stub sections, and gives the "all or nothing" per-symbol consistency | |
14213 | that we have for MIPS16 symbols. */ | |
f43abd2b | 14214 | if (IS_ELF |
b314ec0e | 14215 | && fixp->fx_subsy == NULL |
30c09090 | 14216 | && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp->fx_addsy)) |
b314ec0e | 14217 | || *symbol_get_tc (fixp->fx_addsy))) |
252b5132 RH |
14218 | return 0; |
14219 | #endif | |
a161fe53 | 14220 | |
252b5132 RH |
14221 | return 1; |
14222 | } | |
14223 | ||
14224 | /* Translate internal representation of relocation info to BFD target | |
14225 | format. */ | |
14226 | ||
14227 | arelent ** | |
17a2f251 | 14228 | tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) |
252b5132 RH |
14229 | { |
14230 | static arelent *retval[4]; | |
14231 | arelent *reloc; | |
14232 | bfd_reloc_code_real_type code; | |
14233 | ||
4b0cff4e TS |
14234 | memset (retval, 0, sizeof(retval)); |
14235 | reloc = retval[0] = (arelent *) xcalloc (1, sizeof (arelent)); | |
49309057 ILT |
14236 | reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); |
14237 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
252b5132 RH |
14238 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; |
14239 | ||
bad36eac DJ |
14240 | if (fixp->fx_pcrel) |
14241 | { | |
9c2799c2 | 14242 | gas_assert (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2); |
bad36eac DJ |
14243 | |
14244 | /* At this point, fx_addnumber is "symbol offset - pcrel address". | |
14245 | Relocations want only the symbol offset. */ | |
14246 | reloc->addend = fixp->fx_addnumber + reloc->address; | |
f43abd2b | 14247 | if (!IS_ELF) |
bad36eac DJ |
14248 | { |
14249 | /* A gruesome hack which is a result of the gruesome gas | |
14250 | reloc handling. What's worse, for COFF (as opposed to | |
14251 | ECOFF), we might need yet another copy of reloc->address. | |
14252 | See bfd_install_relocation. */ | |
14253 | reloc->addend += reloc->address; | |
14254 | } | |
14255 | } | |
14256 | else | |
14257 | reloc->addend = fixp->fx_addnumber; | |
252b5132 | 14258 | |
438c16b8 TS |
14259 | /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable |
14260 | entry to be used in the relocation's section offset. */ | |
14261 | if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
252b5132 RH |
14262 | { |
14263 | reloc->address = reloc->addend; | |
14264 | reloc->addend = 0; | |
14265 | } | |
14266 | ||
252b5132 | 14267 | code = fixp->fx_r_type; |
252b5132 | 14268 | |
bad36eac | 14269 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); |
252b5132 RH |
14270 | if (reloc->howto == NULL) |
14271 | { | |
14272 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
14273 | _("Can not represent %s relocation in this object file format"), | |
14274 | bfd_get_reloc_code_name (code)); | |
14275 | retval[0] = NULL; | |
14276 | } | |
14277 | ||
14278 | return retval; | |
14279 | } | |
14280 | ||
14281 | /* Relax a machine dependent frag. This returns the amount by which | |
14282 | the current size of the frag should change. */ | |
14283 | ||
14284 | int | |
17a2f251 | 14285 | mips_relax_frag (asection *sec, fragS *fragp, long stretch) |
252b5132 | 14286 | { |
4a6a3df4 AO |
14287 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
14288 | { | |
14289 | offsetT old_var = fragp->fr_var; | |
b34976b6 AM |
14290 | |
14291 | fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE); | |
4a6a3df4 AO |
14292 | |
14293 | return fragp->fr_var - old_var; | |
14294 | } | |
14295 | ||
252b5132 RH |
14296 | if (! RELAX_MIPS16_P (fragp->fr_subtype)) |
14297 | return 0; | |
14298 | ||
c4e7957c | 14299 | if (mips16_extended_frag (fragp, NULL, stretch)) |
252b5132 RH |
14300 | { |
14301 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
14302 | return 0; | |
14303 | fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype); | |
14304 | return 2; | |
14305 | } | |
14306 | else | |
14307 | { | |
14308 | if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
14309 | return 0; | |
14310 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype); | |
14311 | return -2; | |
14312 | } | |
14313 | ||
14314 | return 0; | |
14315 | } | |
14316 | ||
14317 | /* Convert a machine dependent frag. */ | |
14318 | ||
14319 | void | |
17a2f251 | 14320 | md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp) |
252b5132 | 14321 | { |
4a6a3df4 AO |
14322 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
14323 | { | |
14324 | bfd_byte *buf; | |
14325 | unsigned long insn; | |
14326 | expressionS exp; | |
14327 | fixS *fixp; | |
b34976b6 | 14328 | |
4a6a3df4 AO |
14329 | buf = (bfd_byte *)fragp->fr_literal + fragp->fr_fix; |
14330 | ||
14331 | if (target_big_endian) | |
14332 | insn = bfd_getb32 (buf); | |
14333 | else | |
14334 | insn = bfd_getl32 (buf); | |
b34976b6 | 14335 | |
4a6a3df4 AO |
14336 | if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) |
14337 | { | |
14338 | /* We generate a fixup instead of applying it right now | |
14339 | because, if there are linker relaxations, we're going to | |
14340 | need the relocations. */ | |
14341 | exp.X_op = O_symbol; | |
14342 | exp.X_add_symbol = fragp->fr_symbol; | |
14343 | exp.X_add_number = fragp->fr_offset; | |
14344 | ||
14345 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
3994f87e | 14346 | 4, &exp, TRUE, BFD_RELOC_16_PCREL_S2); |
4a6a3df4 AO |
14347 | fixp->fx_file = fragp->fr_file; |
14348 | fixp->fx_line = fragp->fr_line; | |
b34976b6 | 14349 | |
2132e3a3 | 14350 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
14351 | buf += 4; |
14352 | } | |
14353 | else | |
14354 | { | |
14355 | int i; | |
14356 | ||
14357 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
14358 | _("relaxed out-of-range branch into a jump")); | |
14359 | ||
14360 | if (RELAX_BRANCH_UNCOND (fragp->fr_subtype)) | |
14361 | goto uncond; | |
14362 | ||
14363 | if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
14364 | { | |
14365 | /* Reverse the branch. */ | |
14366 | switch ((insn >> 28) & 0xf) | |
14367 | { | |
14368 | case 4: | |
14369 | /* bc[0-3][tf]l? and bc1any[24][ft] instructions can | |
14370 | have the condition reversed by tweaking a single | |
14371 | bit, and their opcodes all have 0x4???????. */ | |
9c2799c2 | 14372 | gas_assert ((insn & 0xf1000000) == 0x41000000); |
4a6a3df4 AO |
14373 | insn ^= 0x00010000; |
14374 | break; | |
14375 | ||
14376 | case 0: | |
14377 | /* bltz 0x04000000 bgez 0x04010000 | |
54f4ddb3 | 14378 | bltzal 0x04100000 bgezal 0x04110000 */ |
9c2799c2 | 14379 | gas_assert ((insn & 0xfc0e0000) == 0x04000000); |
4a6a3df4 AO |
14380 | insn ^= 0x00010000; |
14381 | break; | |
b34976b6 | 14382 | |
4a6a3df4 AO |
14383 | case 1: |
14384 | /* beq 0x10000000 bne 0x14000000 | |
54f4ddb3 | 14385 | blez 0x18000000 bgtz 0x1c000000 */ |
4a6a3df4 AO |
14386 | insn ^= 0x04000000; |
14387 | break; | |
14388 | ||
14389 | default: | |
14390 | abort (); | |
14391 | } | |
14392 | } | |
14393 | ||
14394 | if (RELAX_BRANCH_LINK (fragp->fr_subtype)) | |
14395 | { | |
14396 | /* Clear the and-link bit. */ | |
9c2799c2 | 14397 | gas_assert ((insn & 0xfc1c0000) == 0x04100000); |
4a6a3df4 | 14398 | |
54f4ddb3 TS |
14399 | /* bltzal 0x04100000 bgezal 0x04110000 |
14400 | bltzall 0x04120000 bgezall 0x04130000 */ | |
4a6a3df4 AO |
14401 | insn &= ~0x00100000; |
14402 | } | |
14403 | ||
14404 | /* Branch over the branch (if the branch was likely) or the | |
14405 | full jump (not likely case). Compute the offset from the | |
14406 | current instruction to branch to. */ | |
14407 | if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
14408 | i = 16; | |
14409 | else | |
14410 | { | |
14411 | /* How many bytes in instructions we've already emitted? */ | |
14412 | i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix; | |
14413 | /* How many bytes in instructions from here to the end? */ | |
14414 | i = fragp->fr_var - i; | |
14415 | } | |
14416 | /* Convert to instruction count. */ | |
14417 | i >>= 2; | |
14418 | /* Branch counts from the next instruction. */ | |
b34976b6 | 14419 | i--; |
4a6a3df4 AO |
14420 | insn |= i; |
14421 | /* Branch over the jump. */ | |
2132e3a3 | 14422 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
14423 | buf += 4; |
14424 | ||
54f4ddb3 | 14425 | /* nop */ |
2132e3a3 | 14426 | md_number_to_chars ((char *) buf, 0, 4); |
4a6a3df4 AO |
14427 | buf += 4; |
14428 | ||
14429 | if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
14430 | { | |
14431 | /* beql $0, $0, 2f */ | |
14432 | insn = 0x50000000; | |
14433 | /* Compute the PC offset from the current instruction to | |
14434 | the end of the variable frag. */ | |
14435 | /* How many bytes in instructions we've already emitted? */ | |
14436 | i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix; | |
14437 | /* How many bytes in instructions from here to the end? */ | |
14438 | i = fragp->fr_var - i; | |
14439 | /* Convert to instruction count. */ | |
14440 | i >>= 2; | |
14441 | /* Don't decrement i, because we want to branch over the | |
14442 | delay slot. */ | |
14443 | ||
14444 | insn |= i; | |
2132e3a3 | 14445 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
14446 | buf += 4; |
14447 | ||
2132e3a3 | 14448 | md_number_to_chars ((char *) buf, 0, 4); |
4a6a3df4 AO |
14449 | buf += 4; |
14450 | } | |
14451 | ||
14452 | uncond: | |
14453 | if (mips_pic == NO_PIC) | |
14454 | { | |
14455 | /* j or jal. */ | |
14456 | insn = (RELAX_BRANCH_LINK (fragp->fr_subtype) | |
14457 | ? 0x0c000000 : 0x08000000); | |
14458 | exp.X_op = O_symbol; | |
14459 | exp.X_add_symbol = fragp->fr_symbol; | |
14460 | exp.X_add_number = fragp->fr_offset; | |
14461 | ||
14462 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
3994f87e | 14463 | 4, &exp, FALSE, BFD_RELOC_MIPS_JMP); |
4a6a3df4 AO |
14464 | fixp->fx_file = fragp->fr_file; |
14465 | fixp->fx_line = fragp->fr_line; | |
14466 | ||
2132e3a3 | 14467 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
14468 | buf += 4; |
14469 | } | |
14470 | else | |
14471 | { | |
14472 | /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */ | |
14473 | insn = HAVE_64BIT_ADDRESSES ? 0xdf810000 : 0x8f810000; | |
14474 | exp.X_op = O_symbol; | |
14475 | exp.X_add_symbol = fragp->fr_symbol; | |
14476 | exp.X_add_number = fragp->fr_offset; | |
14477 | ||
14478 | if (fragp->fr_offset) | |
14479 | { | |
14480 | exp.X_add_symbol = make_expr_symbol (&exp); | |
14481 | exp.X_add_number = 0; | |
14482 | } | |
14483 | ||
14484 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
3994f87e | 14485 | 4, &exp, FALSE, BFD_RELOC_MIPS_GOT16); |
4a6a3df4 AO |
14486 | fixp->fx_file = fragp->fr_file; |
14487 | fixp->fx_line = fragp->fr_line; | |
14488 | ||
2132e3a3 | 14489 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 | 14490 | buf += 4; |
b34976b6 | 14491 | |
4a6a3df4 AO |
14492 | if (mips_opts.isa == ISA_MIPS1) |
14493 | { | |
14494 | /* nop */ | |
2132e3a3 | 14495 | md_number_to_chars ((char *) buf, 0, 4); |
4a6a3df4 AO |
14496 | buf += 4; |
14497 | } | |
14498 | ||
14499 | /* d/addiu $at, $at, <sym> R_MIPS_LO16 */ | |
14500 | insn = HAVE_64BIT_ADDRESSES ? 0x64210000 : 0x24210000; | |
14501 | ||
14502 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
3994f87e | 14503 | 4, &exp, FALSE, BFD_RELOC_LO16); |
4a6a3df4 AO |
14504 | fixp->fx_file = fragp->fr_file; |
14505 | fixp->fx_line = fragp->fr_line; | |
b34976b6 | 14506 | |
2132e3a3 | 14507 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
14508 | buf += 4; |
14509 | ||
14510 | /* j(al)r $at. */ | |
14511 | if (RELAX_BRANCH_LINK (fragp->fr_subtype)) | |
14512 | insn = 0x0020f809; | |
14513 | else | |
14514 | insn = 0x00200008; | |
14515 | ||
2132e3a3 | 14516 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
14517 | buf += 4; |
14518 | } | |
14519 | } | |
14520 | ||
9c2799c2 | 14521 | gas_assert (buf == (bfd_byte *)fragp->fr_literal |
4a6a3df4 AO |
14522 | + fragp->fr_fix + fragp->fr_var); |
14523 | ||
14524 | fragp->fr_fix += fragp->fr_var; | |
14525 | ||
14526 | return; | |
14527 | } | |
14528 | ||
252b5132 RH |
14529 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
14530 | { | |
14531 | int type; | |
3994f87e | 14532 | const struct mips16_immed_operand *op; |
b34976b6 | 14533 | bfd_boolean small, ext; |
252b5132 RH |
14534 | offsetT val; |
14535 | bfd_byte *buf; | |
14536 | unsigned long insn; | |
b34976b6 | 14537 | bfd_boolean use_extend; |
252b5132 RH |
14538 | unsigned short extend; |
14539 | ||
14540 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
14541 | op = mips16_immed_operands; | |
14542 | while (op->type != type) | |
14543 | ++op; | |
14544 | ||
14545 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
14546 | { | |
b34976b6 AM |
14547 | small = FALSE; |
14548 | ext = TRUE; | |
252b5132 RH |
14549 | } |
14550 | else | |
14551 | { | |
b34976b6 AM |
14552 | small = TRUE; |
14553 | ext = FALSE; | |
252b5132 RH |
14554 | } |
14555 | ||
5f5f22c0 | 14556 | val = resolve_symbol_value (fragp->fr_symbol); |
252b5132 RH |
14557 | if (op->pcrel) |
14558 | { | |
14559 | addressT addr; | |
14560 | ||
14561 | addr = fragp->fr_address + fragp->fr_fix; | |
14562 | ||
14563 | /* The rules for the base address of a PC relative reloc are | |
14564 | complicated; see mips16_extended_frag. */ | |
14565 | if (type == 'p' || type == 'q') | |
14566 | { | |
14567 | addr += 2; | |
14568 | if (ext) | |
14569 | addr += 2; | |
14570 | /* Ignore the low bit in the target, since it will be | |
14571 | set for a text label. */ | |
14572 | if ((val & 1) != 0) | |
14573 | --val; | |
14574 | } | |
14575 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) | |
14576 | addr -= 4; | |
14577 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
14578 | addr -= 2; | |
14579 | ||
14580 | addr &= ~ (addressT) ((1 << op->shift) - 1); | |
14581 | val -= addr; | |
14582 | ||
14583 | /* Make sure the section winds up with the alignment we have | |
14584 | assumed. */ | |
14585 | if (op->shift > 0) | |
14586 | record_alignment (asec, op->shift); | |
14587 | } | |
14588 | ||
14589 | if (ext | |
14590 | && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype) | |
14591 | || RELAX_MIPS16_DSLOT (fragp->fr_subtype))) | |
14592 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
14593 | _("extended instruction in delay slot")); | |
14594 | ||
14595 | buf = (bfd_byte *) (fragp->fr_literal + fragp->fr_fix); | |
14596 | ||
14597 | if (target_big_endian) | |
14598 | insn = bfd_getb16 (buf); | |
14599 | else | |
14600 | insn = bfd_getl16 (buf); | |
14601 | ||
14602 | mips16_immed (fragp->fr_file, fragp->fr_line, type, val, | |
14603 | RELAX_MIPS16_USER_EXT (fragp->fr_subtype), | |
14604 | small, ext, &insn, &use_extend, &extend); | |
14605 | ||
14606 | if (use_extend) | |
14607 | { | |
2132e3a3 | 14608 | md_number_to_chars ((char *) buf, 0xf000 | extend, 2); |
252b5132 RH |
14609 | fragp->fr_fix += 2; |
14610 | buf += 2; | |
14611 | } | |
14612 | ||
2132e3a3 | 14613 | md_number_to_chars ((char *) buf, insn, 2); |
252b5132 RH |
14614 | fragp->fr_fix += 2; |
14615 | buf += 2; | |
14616 | } | |
14617 | else | |
14618 | { | |
4d7206a2 RS |
14619 | int first, second; |
14620 | fixS *fixp; | |
252b5132 | 14621 | |
4d7206a2 RS |
14622 | first = RELAX_FIRST (fragp->fr_subtype); |
14623 | second = RELAX_SECOND (fragp->fr_subtype); | |
14624 | fixp = (fixS *) fragp->fr_opcode; | |
252b5132 | 14625 | |
584892a6 RS |
14626 | /* Possibly emit a warning if we've chosen the longer option. */ |
14627 | if (((fragp->fr_subtype & RELAX_USE_SECOND) != 0) | |
14628 | == ((fragp->fr_subtype & RELAX_SECOND_LONGER) != 0)) | |
14629 | { | |
14630 | const char *msg = macro_warning (fragp->fr_subtype); | |
14631 | if (msg != 0) | |
520725ea | 14632 | as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg); |
584892a6 RS |
14633 | } |
14634 | ||
4d7206a2 RS |
14635 | /* Go through all the fixups for the first sequence. Disable them |
14636 | (by marking them as done) if we're going to use the second | |
14637 | sequence instead. */ | |
14638 | while (fixp | |
14639 | && fixp->fx_frag == fragp | |
14640 | && fixp->fx_where < fragp->fr_fix - second) | |
14641 | { | |
14642 | if (fragp->fr_subtype & RELAX_USE_SECOND) | |
14643 | fixp->fx_done = 1; | |
14644 | fixp = fixp->fx_next; | |
14645 | } | |
252b5132 | 14646 | |
4d7206a2 RS |
14647 | /* Go through the fixups for the second sequence. Disable them if |
14648 | we're going to use the first sequence, otherwise adjust their | |
14649 | addresses to account for the relaxation. */ | |
14650 | while (fixp && fixp->fx_frag == fragp) | |
14651 | { | |
14652 | if (fragp->fr_subtype & RELAX_USE_SECOND) | |
14653 | fixp->fx_where -= first; | |
14654 | else | |
14655 | fixp->fx_done = 1; | |
14656 | fixp = fixp->fx_next; | |
14657 | } | |
14658 | ||
14659 | /* Now modify the frag contents. */ | |
14660 | if (fragp->fr_subtype & RELAX_USE_SECOND) | |
14661 | { | |
14662 | char *start; | |
14663 | ||
14664 | start = fragp->fr_literal + fragp->fr_fix - first - second; | |
14665 | memmove (start, start + first, second); | |
14666 | fragp->fr_fix -= first; | |
14667 | } | |
14668 | else | |
14669 | fragp->fr_fix -= second; | |
252b5132 RH |
14670 | } |
14671 | } | |
14672 | ||
14673 | #ifdef OBJ_ELF | |
14674 | ||
14675 | /* This function is called after the relocs have been generated. | |
14676 | We've been storing mips16 text labels as odd. Here we convert them | |
14677 | back to even for the convenience of the debugger. */ | |
14678 | ||
14679 | void | |
17a2f251 | 14680 | mips_frob_file_after_relocs (void) |
252b5132 RH |
14681 | { |
14682 | asymbol **syms; | |
14683 | unsigned int count, i; | |
14684 | ||
f43abd2b | 14685 | if (!IS_ELF) |
252b5132 RH |
14686 | return; |
14687 | ||
14688 | syms = bfd_get_outsymbols (stdoutput); | |
14689 | count = bfd_get_symcount (stdoutput); | |
14690 | for (i = 0; i < count; i++, syms++) | |
14691 | { | |
30c09090 | 14692 | if (ELF_ST_IS_MIPS16 (elf_symbol (*syms)->internal_elf_sym.st_other) |
252b5132 RH |
14693 | && ((*syms)->value & 1) != 0) |
14694 | { | |
14695 | (*syms)->value &= ~1; | |
14696 | /* If the symbol has an odd size, it was probably computed | |
14697 | incorrectly, so adjust that as well. */ | |
14698 | if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0) | |
14699 | ++elf_symbol (*syms)->internal_elf_sym.st_size; | |
14700 | } | |
14701 | } | |
14702 | } | |
14703 | ||
14704 | #endif | |
14705 | ||
14706 | /* This function is called whenever a label is defined. It is used | |
14707 | when handling branch delays; if a branch has a label, we assume we | |
14708 | can not move it. */ | |
14709 | ||
14710 | void | |
17a2f251 | 14711 | mips_define_label (symbolS *sym) |
252b5132 | 14712 | { |
a8dbcb85 | 14713 | segment_info_type *si = seg_info (now_seg); |
252b5132 RH |
14714 | struct insn_label_list *l; |
14715 | ||
14716 | if (free_insn_labels == NULL) | |
14717 | l = (struct insn_label_list *) xmalloc (sizeof *l); | |
14718 | else | |
14719 | { | |
14720 | l = free_insn_labels; | |
14721 | free_insn_labels = l->next; | |
14722 | } | |
14723 | ||
14724 | l->label = sym; | |
a8dbcb85 TS |
14725 | l->next = si->label_list; |
14726 | si->label_list = l; | |
07a53e5c RH |
14727 | |
14728 | #ifdef OBJ_ELF | |
14729 | dwarf2_emit_label (sym); | |
14730 | #endif | |
252b5132 RH |
14731 | } |
14732 | \f | |
14733 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
14734 | ||
14735 | /* Some special processing for a MIPS ELF file. */ | |
14736 | ||
14737 | void | |
17a2f251 | 14738 | mips_elf_final_processing (void) |
252b5132 RH |
14739 | { |
14740 | /* Write out the register information. */ | |
316f5878 | 14741 | if (mips_abi != N64_ABI) |
252b5132 RH |
14742 | { |
14743 | Elf32_RegInfo s; | |
14744 | ||
14745 | s.ri_gprmask = mips_gprmask; | |
14746 | s.ri_cprmask[0] = mips_cprmask[0]; | |
14747 | s.ri_cprmask[1] = mips_cprmask[1]; | |
14748 | s.ri_cprmask[2] = mips_cprmask[2]; | |
14749 | s.ri_cprmask[3] = mips_cprmask[3]; | |
14750 | /* The gp_value field is set by the MIPS ELF backend. */ | |
14751 | ||
14752 | bfd_mips_elf32_swap_reginfo_out (stdoutput, &s, | |
14753 | ((Elf32_External_RegInfo *) | |
14754 | mips_regmask_frag)); | |
14755 | } | |
14756 | else | |
14757 | { | |
14758 | Elf64_Internal_RegInfo s; | |
14759 | ||
14760 | s.ri_gprmask = mips_gprmask; | |
14761 | s.ri_pad = 0; | |
14762 | s.ri_cprmask[0] = mips_cprmask[0]; | |
14763 | s.ri_cprmask[1] = mips_cprmask[1]; | |
14764 | s.ri_cprmask[2] = mips_cprmask[2]; | |
14765 | s.ri_cprmask[3] = mips_cprmask[3]; | |
14766 | /* The gp_value field is set by the MIPS ELF backend. */ | |
14767 | ||
14768 | bfd_mips_elf64_swap_reginfo_out (stdoutput, &s, | |
14769 | ((Elf64_External_RegInfo *) | |
14770 | mips_regmask_frag)); | |
14771 | } | |
14772 | ||
14773 | /* Set the MIPS ELF flag bits. FIXME: There should probably be some | |
14774 | sort of BFD interface for this. */ | |
14775 | if (mips_any_noreorder) | |
14776 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER; | |
14777 | if (mips_pic != NO_PIC) | |
143d77c5 | 14778 | { |
252b5132 | 14779 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC; |
143d77c5 EC |
14780 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC; |
14781 | } | |
14782 | if (mips_abicalls) | |
14783 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC; | |
252b5132 | 14784 | |
98d3f06f | 14785 | /* Set MIPS ELF flags for ASEs. */ |
74cd071d CF |
14786 | /* We may need to define a new flag for DSP ASE, and set this flag when |
14787 | file_ase_dsp is true. */ | |
8b082fb1 | 14788 | /* Same for DSP R2. */ |
ef2e4d86 CF |
14789 | /* We may need to define a new flag for MT ASE, and set this flag when |
14790 | file_ase_mt is true. */ | |
a4672219 TS |
14791 | if (file_ase_mips16) |
14792 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16; | |
1f25f5d3 CD |
14793 | #if 0 /* XXX FIXME */ |
14794 | if (file_ase_mips3d) | |
14795 | elf_elfheader (stdoutput)->e_flags |= ???; | |
14796 | #endif | |
deec1734 CD |
14797 | if (file_ase_mdmx) |
14798 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX; | |
1f25f5d3 | 14799 | |
bdaaa2e1 | 14800 | /* Set the MIPS ELF ABI flags. */ |
316f5878 | 14801 | if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32) |
252b5132 | 14802 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32; |
316f5878 | 14803 | else if (mips_abi == O64_ABI) |
252b5132 | 14804 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64; |
316f5878 | 14805 | else if (mips_abi == EABI_ABI) |
252b5132 | 14806 | { |
316f5878 | 14807 | if (!file_mips_gp32) |
252b5132 RH |
14808 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64; |
14809 | else | |
14810 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32; | |
14811 | } | |
316f5878 | 14812 | else if (mips_abi == N32_ABI) |
be00bddd TS |
14813 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2; |
14814 | ||
c9914766 | 14815 | /* Nothing to do for N64_ABI. */ |
252b5132 RH |
14816 | |
14817 | if (mips_32bitmode) | |
14818 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE; | |
ad3fea08 TS |
14819 | |
14820 | #if 0 /* XXX FIXME */ | |
14821 | /* 32 bit code with 64 bit FP registers. */ | |
14822 | if (!file_mips_fp32 && ABI_NEEDS_32BIT_REGS (mips_abi)) | |
14823 | elf_elfheader (stdoutput)->e_flags |= ???; | |
14824 | #endif | |
252b5132 RH |
14825 | } |
14826 | ||
14827 | #endif /* OBJ_ELF || OBJ_MAYBE_ELF */ | |
14828 | \f | |
beae10d5 | 14829 | typedef struct proc { |
9b2f1d35 EC |
14830 | symbolS *func_sym; |
14831 | symbolS *func_end_sym; | |
beae10d5 KH |
14832 | unsigned long reg_mask; |
14833 | unsigned long reg_offset; | |
14834 | unsigned long fpreg_mask; | |
14835 | unsigned long fpreg_offset; | |
14836 | unsigned long frame_offset; | |
14837 | unsigned long frame_reg; | |
14838 | unsigned long pc_reg; | |
14839 | } procS; | |
252b5132 RH |
14840 | |
14841 | static procS cur_proc; | |
14842 | static procS *cur_proc_ptr; | |
14843 | static int numprocs; | |
14844 | ||
742a56fe RS |
14845 | /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1" and a normal |
14846 | nop as "0". */ | |
14847 | ||
14848 | char | |
14849 | mips_nop_opcode (void) | |
14850 | { | |
14851 | return seg_info (now_seg)->tc_segment_info_data.mips16; | |
14852 | } | |
14853 | ||
14854 | /* Fill in an rs_align_code fragment. This only needs to do something | |
14855 | for MIPS16 code, where 0 is not a nop. */ | |
a19d8eb0 | 14856 | |
0a9ef439 | 14857 | void |
17a2f251 | 14858 | mips_handle_align (fragS *fragp) |
a19d8eb0 | 14859 | { |
742a56fe | 14860 | char *p; |
c67a084a NC |
14861 | int bytes, size, excess; |
14862 | valueT opcode; | |
742a56fe | 14863 | |
0a9ef439 RH |
14864 | if (fragp->fr_type != rs_align_code) |
14865 | return; | |
14866 | ||
742a56fe RS |
14867 | p = fragp->fr_literal + fragp->fr_fix; |
14868 | if (*p) | |
a19d8eb0 | 14869 | { |
c67a084a NC |
14870 | opcode = mips16_nop_insn.insn_opcode; |
14871 | size = 2; | |
14872 | } | |
14873 | else | |
14874 | { | |
14875 | opcode = nop_insn.insn_opcode; | |
14876 | size = 4; | |
14877 | } | |
a19d8eb0 | 14878 | |
c67a084a NC |
14879 | bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix; |
14880 | excess = bytes % size; | |
14881 | if (excess != 0) | |
14882 | { | |
14883 | /* If we're not inserting a whole number of instructions, | |
14884 | pad the end of the fixed part of the frag with zeros. */ | |
14885 | memset (p, 0, excess); | |
14886 | p += excess; | |
14887 | fragp->fr_fix += excess; | |
a19d8eb0 | 14888 | } |
c67a084a NC |
14889 | |
14890 | md_number_to_chars (p, opcode, size); | |
14891 | fragp->fr_var = size; | |
a19d8eb0 CP |
14892 | } |
14893 | ||
252b5132 | 14894 | static void |
17a2f251 | 14895 | md_obj_begin (void) |
252b5132 RH |
14896 | { |
14897 | } | |
14898 | ||
14899 | static void | |
17a2f251 | 14900 | md_obj_end (void) |
252b5132 | 14901 | { |
54f4ddb3 | 14902 | /* Check for premature end, nesting errors, etc. */ |
252b5132 | 14903 | if (cur_proc_ptr) |
9a41af64 | 14904 | as_warn (_("missing .end at end of assembly")); |
252b5132 RH |
14905 | } |
14906 | ||
14907 | static long | |
17a2f251 | 14908 | get_number (void) |
252b5132 RH |
14909 | { |
14910 | int negative = 0; | |
14911 | long val = 0; | |
14912 | ||
14913 | if (*input_line_pointer == '-') | |
14914 | { | |
14915 | ++input_line_pointer; | |
14916 | negative = 1; | |
14917 | } | |
3882b010 | 14918 | if (!ISDIGIT (*input_line_pointer)) |
956cd1d6 | 14919 | as_bad (_("expected simple number")); |
252b5132 RH |
14920 | if (input_line_pointer[0] == '0') |
14921 | { | |
14922 | if (input_line_pointer[1] == 'x') | |
14923 | { | |
14924 | input_line_pointer += 2; | |
3882b010 | 14925 | while (ISXDIGIT (*input_line_pointer)) |
252b5132 RH |
14926 | { |
14927 | val <<= 4; | |
14928 | val |= hex_value (*input_line_pointer++); | |
14929 | } | |
14930 | return negative ? -val : val; | |
14931 | } | |
14932 | else | |
14933 | { | |
14934 | ++input_line_pointer; | |
3882b010 | 14935 | while (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
14936 | { |
14937 | val <<= 3; | |
14938 | val |= *input_line_pointer++ - '0'; | |
14939 | } | |
14940 | return negative ? -val : val; | |
14941 | } | |
14942 | } | |
3882b010 | 14943 | if (!ISDIGIT (*input_line_pointer)) |
252b5132 RH |
14944 | { |
14945 | printf (_(" *input_line_pointer == '%c' 0x%02x\n"), | |
14946 | *input_line_pointer, *input_line_pointer); | |
956cd1d6 | 14947 | as_warn (_("invalid number")); |
252b5132 RH |
14948 | return -1; |
14949 | } | |
3882b010 | 14950 | while (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
14951 | { |
14952 | val *= 10; | |
14953 | val += *input_line_pointer++ - '0'; | |
14954 | } | |
14955 | return negative ? -val : val; | |
14956 | } | |
14957 | ||
14958 | /* The .file directive; just like the usual .file directive, but there | |
c5dd6aab DJ |
14959 | is an initial number which is the ECOFF file index. In the non-ECOFF |
14960 | case .file implies DWARF-2. */ | |
14961 | ||
14962 | static void | |
17a2f251 | 14963 | s_mips_file (int x ATTRIBUTE_UNUSED) |
c5dd6aab | 14964 | { |
ecb4347a DJ |
14965 | static int first_file_directive = 0; |
14966 | ||
c5dd6aab DJ |
14967 | if (ECOFF_DEBUGGING) |
14968 | { | |
14969 | get_number (); | |
14970 | s_app_file (0); | |
14971 | } | |
14972 | else | |
ecb4347a DJ |
14973 | { |
14974 | char *filename; | |
14975 | ||
14976 | filename = dwarf2_directive_file (0); | |
14977 | ||
14978 | /* Versions of GCC up to 3.1 start files with a ".file" | |
14979 | directive even for stabs output. Make sure that this | |
14980 | ".file" is handled. Note that you need a version of GCC | |
14981 | after 3.1 in order to support DWARF-2 on MIPS. */ | |
14982 | if (filename != NULL && ! first_file_directive) | |
14983 | { | |
14984 | (void) new_logical_line (filename, -1); | |
c04f5787 | 14985 | s_app_file_string (filename, 0); |
ecb4347a DJ |
14986 | } |
14987 | first_file_directive = 1; | |
14988 | } | |
c5dd6aab DJ |
14989 | } |
14990 | ||
14991 | /* The .loc directive, implying DWARF-2. */ | |
252b5132 RH |
14992 | |
14993 | static void | |
17a2f251 | 14994 | s_mips_loc (int x ATTRIBUTE_UNUSED) |
252b5132 | 14995 | { |
c5dd6aab DJ |
14996 | if (!ECOFF_DEBUGGING) |
14997 | dwarf2_directive_loc (0); | |
252b5132 RH |
14998 | } |
14999 | ||
252b5132 RH |
15000 | /* The .end directive. */ |
15001 | ||
15002 | static void | |
17a2f251 | 15003 | s_mips_end (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
15004 | { |
15005 | symbolS *p; | |
252b5132 | 15006 | |
7a621144 DJ |
15007 | /* Following functions need their own .frame and .cprestore directives. */ |
15008 | mips_frame_reg_valid = 0; | |
15009 | mips_cprestore_valid = 0; | |
15010 | ||
252b5132 RH |
15011 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
15012 | { | |
15013 | p = get_symbol (); | |
15014 | demand_empty_rest_of_line (); | |
15015 | } | |
15016 | else | |
15017 | p = NULL; | |
15018 | ||
14949570 | 15019 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0) |
252b5132 RH |
15020 | as_warn (_(".end not in text section")); |
15021 | ||
15022 | if (!cur_proc_ptr) | |
15023 | { | |
15024 | as_warn (_(".end directive without a preceding .ent directive.")); | |
15025 | demand_empty_rest_of_line (); | |
15026 | return; | |
15027 | } | |
15028 | ||
15029 | if (p != NULL) | |
15030 | { | |
9c2799c2 | 15031 | gas_assert (S_GET_NAME (p)); |
9b2f1d35 | 15032 | if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->func_sym))) |
252b5132 | 15033 | as_warn (_(".end symbol does not match .ent symbol.")); |
ecb4347a DJ |
15034 | |
15035 | if (debug_type == DEBUG_STABS) | |
15036 | stabs_generate_asm_endfunc (S_GET_NAME (p), | |
15037 | S_GET_NAME (p)); | |
252b5132 RH |
15038 | } |
15039 | else | |
15040 | as_warn (_(".end directive missing or unknown symbol")); | |
15041 | ||
2132e3a3 | 15042 | #ifdef OBJ_ELF |
9b2f1d35 EC |
15043 | /* Create an expression to calculate the size of the function. */ |
15044 | if (p && cur_proc_ptr) | |
15045 | { | |
15046 | OBJ_SYMFIELD_TYPE *obj = symbol_get_obj (p); | |
15047 | expressionS *exp = xmalloc (sizeof (expressionS)); | |
15048 | ||
15049 | obj->size = exp; | |
15050 | exp->X_op = O_subtract; | |
15051 | exp->X_add_symbol = symbol_temp_new_now (); | |
15052 | exp->X_op_symbol = p; | |
15053 | exp->X_add_number = 0; | |
15054 | ||
15055 | cur_proc_ptr->func_end_sym = exp->X_add_symbol; | |
15056 | } | |
15057 | ||
ecb4347a | 15058 | /* Generate a .pdr section. */ |
f43abd2b | 15059 | if (IS_ELF && !ECOFF_DEBUGGING && mips_flag_pdr) |
ecb4347a DJ |
15060 | { |
15061 | segT saved_seg = now_seg; | |
15062 | subsegT saved_subseg = now_subseg; | |
ecb4347a DJ |
15063 | expressionS exp; |
15064 | char *fragp; | |
252b5132 | 15065 | |
252b5132 | 15066 | #ifdef md_flush_pending_output |
ecb4347a | 15067 | md_flush_pending_output (); |
252b5132 RH |
15068 | #endif |
15069 | ||
9c2799c2 | 15070 | gas_assert (pdr_seg); |
ecb4347a | 15071 | subseg_set (pdr_seg, 0); |
252b5132 | 15072 | |
ecb4347a DJ |
15073 | /* Write the symbol. */ |
15074 | exp.X_op = O_symbol; | |
15075 | exp.X_add_symbol = p; | |
15076 | exp.X_add_number = 0; | |
15077 | emit_expr (&exp, 4); | |
252b5132 | 15078 | |
ecb4347a | 15079 | fragp = frag_more (7 * 4); |
252b5132 | 15080 | |
17a2f251 TS |
15081 | md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4); |
15082 | md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4); | |
15083 | md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4); | |
15084 | md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4); | |
15085 | md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4); | |
15086 | md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4); | |
15087 | md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4); | |
252b5132 | 15088 | |
ecb4347a DJ |
15089 | subseg_set (saved_seg, saved_subseg); |
15090 | } | |
15091 | #endif /* OBJ_ELF */ | |
252b5132 RH |
15092 | |
15093 | cur_proc_ptr = NULL; | |
15094 | } | |
15095 | ||
15096 | /* The .aent and .ent directives. */ | |
15097 | ||
15098 | static void | |
17a2f251 | 15099 | s_mips_ent (int aent) |
252b5132 | 15100 | { |
252b5132 | 15101 | symbolS *symbolP; |
252b5132 RH |
15102 | |
15103 | symbolP = get_symbol (); | |
15104 | if (*input_line_pointer == ',') | |
f9419b05 | 15105 | ++input_line_pointer; |
252b5132 | 15106 | SKIP_WHITESPACE (); |
3882b010 | 15107 | if (ISDIGIT (*input_line_pointer) |
d9a62219 | 15108 | || *input_line_pointer == '-') |
874e8986 | 15109 | get_number (); |
252b5132 | 15110 | |
14949570 | 15111 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0) |
252b5132 RH |
15112 | as_warn (_(".ent or .aent not in text section.")); |
15113 | ||
15114 | if (!aent && cur_proc_ptr) | |
9a41af64 | 15115 | as_warn (_("missing .end")); |
252b5132 RH |
15116 | |
15117 | if (!aent) | |
15118 | { | |
7a621144 DJ |
15119 | /* This function needs its own .frame and .cprestore directives. */ |
15120 | mips_frame_reg_valid = 0; | |
15121 | mips_cprestore_valid = 0; | |
15122 | ||
252b5132 RH |
15123 | cur_proc_ptr = &cur_proc; |
15124 | memset (cur_proc_ptr, '\0', sizeof (procS)); | |
15125 | ||
9b2f1d35 | 15126 | cur_proc_ptr->func_sym = symbolP; |
252b5132 | 15127 | |
f9419b05 | 15128 | ++numprocs; |
ecb4347a DJ |
15129 | |
15130 | if (debug_type == DEBUG_STABS) | |
15131 | stabs_generate_asm_func (S_GET_NAME (symbolP), | |
15132 | S_GET_NAME (symbolP)); | |
252b5132 RH |
15133 | } |
15134 | ||
7c0fc524 MR |
15135 | symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION; |
15136 | ||
252b5132 RH |
15137 | demand_empty_rest_of_line (); |
15138 | } | |
15139 | ||
15140 | /* The .frame directive. If the mdebug section is present (IRIX 5 native) | |
bdaaa2e1 | 15141 | then ecoff.c (ecoff_directive_frame) is used. For embedded targets, |
252b5132 | 15142 | s_mips_frame is used so that we can set the PDR information correctly. |
bdaaa2e1 | 15143 | We can't use the ecoff routines because they make reference to the ecoff |
252b5132 RH |
15144 | symbol table (in the mdebug section). */ |
15145 | ||
15146 | static void | |
17a2f251 | 15147 | s_mips_frame (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 15148 | { |
ecb4347a | 15149 | #ifdef OBJ_ELF |
f43abd2b | 15150 | if (IS_ELF && !ECOFF_DEBUGGING) |
ecb4347a DJ |
15151 | { |
15152 | long val; | |
252b5132 | 15153 | |
ecb4347a DJ |
15154 | if (cur_proc_ptr == (procS *) NULL) |
15155 | { | |
15156 | as_warn (_(".frame outside of .ent")); | |
15157 | demand_empty_rest_of_line (); | |
15158 | return; | |
15159 | } | |
252b5132 | 15160 | |
ecb4347a DJ |
15161 | cur_proc_ptr->frame_reg = tc_get_register (1); |
15162 | ||
15163 | SKIP_WHITESPACE (); | |
15164 | if (*input_line_pointer++ != ',' | |
15165 | || get_absolute_expression_and_terminator (&val) != ',') | |
15166 | { | |
15167 | as_warn (_("Bad .frame directive")); | |
15168 | --input_line_pointer; | |
15169 | demand_empty_rest_of_line (); | |
15170 | return; | |
15171 | } | |
252b5132 | 15172 | |
ecb4347a DJ |
15173 | cur_proc_ptr->frame_offset = val; |
15174 | cur_proc_ptr->pc_reg = tc_get_register (0); | |
252b5132 | 15175 | |
252b5132 | 15176 | demand_empty_rest_of_line (); |
252b5132 | 15177 | } |
ecb4347a DJ |
15178 | else |
15179 | #endif /* OBJ_ELF */ | |
15180 | s_ignore (ignore); | |
252b5132 RH |
15181 | } |
15182 | ||
bdaaa2e1 KH |
15183 | /* The .fmask and .mask directives. If the mdebug section is present |
15184 | (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For | |
252b5132 | 15185 | embedded targets, s_mips_mask is used so that we can set the PDR |
bdaaa2e1 | 15186 | information correctly. We can't use the ecoff routines because they |
252b5132 RH |
15187 | make reference to the ecoff symbol table (in the mdebug section). */ |
15188 | ||
15189 | static void | |
17a2f251 | 15190 | s_mips_mask (int reg_type) |
252b5132 | 15191 | { |
ecb4347a | 15192 | #ifdef OBJ_ELF |
f43abd2b | 15193 | if (IS_ELF && !ECOFF_DEBUGGING) |
252b5132 | 15194 | { |
ecb4347a | 15195 | long mask, off; |
252b5132 | 15196 | |
ecb4347a DJ |
15197 | if (cur_proc_ptr == (procS *) NULL) |
15198 | { | |
15199 | as_warn (_(".mask/.fmask outside of .ent")); | |
15200 | demand_empty_rest_of_line (); | |
15201 | return; | |
15202 | } | |
252b5132 | 15203 | |
ecb4347a DJ |
15204 | if (get_absolute_expression_and_terminator (&mask) != ',') |
15205 | { | |
15206 | as_warn (_("Bad .mask/.fmask directive")); | |
15207 | --input_line_pointer; | |
15208 | demand_empty_rest_of_line (); | |
15209 | return; | |
15210 | } | |
252b5132 | 15211 | |
ecb4347a DJ |
15212 | off = get_absolute_expression (); |
15213 | ||
15214 | if (reg_type == 'F') | |
15215 | { | |
15216 | cur_proc_ptr->fpreg_mask = mask; | |
15217 | cur_proc_ptr->fpreg_offset = off; | |
15218 | } | |
15219 | else | |
15220 | { | |
15221 | cur_proc_ptr->reg_mask = mask; | |
15222 | cur_proc_ptr->reg_offset = off; | |
15223 | } | |
15224 | ||
15225 | demand_empty_rest_of_line (); | |
252b5132 RH |
15226 | } |
15227 | else | |
ecb4347a DJ |
15228 | #endif /* OBJ_ELF */ |
15229 | s_ignore (reg_type); | |
252b5132 RH |
15230 | } |
15231 | ||
316f5878 RS |
15232 | /* A table describing all the processors gas knows about. Names are |
15233 | matched in the order listed. | |
e7af610e | 15234 | |
316f5878 RS |
15235 | To ease comparison, please keep this table in the same order as |
15236 | gcc's mips_cpu_info_table[]. */ | |
e972090a NC |
15237 | static const struct mips_cpu_info mips_cpu_info_table[] = |
15238 | { | |
316f5878 | 15239 | /* Entries for generic ISAs */ |
ad3fea08 TS |
15240 | { "mips1", MIPS_CPU_IS_ISA, ISA_MIPS1, CPU_R3000 }, |
15241 | { "mips2", MIPS_CPU_IS_ISA, ISA_MIPS2, CPU_R6000 }, | |
15242 | { "mips3", MIPS_CPU_IS_ISA, ISA_MIPS3, CPU_R4000 }, | |
15243 | { "mips4", MIPS_CPU_IS_ISA, ISA_MIPS4, CPU_R8000 }, | |
15244 | { "mips5", MIPS_CPU_IS_ISA, ISA_MIPS5, CPU_MIPS5 }, | |
15245 | { "mips32", MIPS_CPU_IS_ISA, ISA_MIPS32, CPU_MIPS32 }, | |
15246 | { "mips32r2", MIPS_CPU_IS_ISA, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
15247 | { "mips64", MIPS_CPU_IS_ISA, ISA_MIPS64, CPU_MIPS64 }, | |
15248 | { "mips64r2", MIPS_CPU_IS_ISA, ISA_MIPS64R2, CPU_MIPS64R2 }, | |
316f5878 RS |
15249 | |
15250 | /* MIPS I */ | |
ad3fea08 TS |
15251 | { "r3000", 0, ISA_MIPS1, CPU_R3000 }, |
15252 | { "r2000", 0, ISA_MIPS1, CPU_R3000 }, | |
15253 | { "r3900", 0, ISA_MIPS1, CPU_R3900 }, | |
316f5878 RS |
15254 | |
15255 | /* MIPS II */ | |
ad3fea08 | 15256 | { "r6000", 0, ISA_MIPS2, CPU_R6000 }, |
316f5878 RS |
15257 | |
15258 | /* MIPS III */ | |
ad3fea08 TS |
15259 | { "r4000", 0, ISA_MIPS3, CPU_R4000 }, |
15260 | { "r4010", 0, ISA_MIPS2, CPU_R4010 }, | |
15261 | { "vr4100", 0, ISA_MIPS3, CPU_VR4100 }, | |
15262 | { "vr4111", 0, ISA_MIPS3, CPU_R4111 }, | |
15263 | { "vr4120", 0, ISA_MIPS3, CPU_VR4120 }, | |
15264 | { "vr4130", 0, ISA_MIPS3, CPU_VR4120 }, | |
15265 | { "vr4181", 0, ISA_MIPS3, CPU_R4111 }, | |
15266 | { "vr4300", 0, ISA_MIPS3, CPU_R4300 }, | |
15267 | { "r4400", 0, ISA_MIPS3, CPU_R4400 }, | |
15268 | { "r4600", 0, ISA_MIPS3, CPU_R4600 }, | |
15269 | { "orion", 0, ISA_MIPS3, CPU_R4600 }, | |
15270 | { "r4650", 0, ISA_MIPS3, CPU_R4650 }, | |
b15591bb AN |
15271 | /* ST Microelectronics Loongson 2E and 2F cores */ |
15272 | { "loongson2e", 0, ISA_MIPS3, CPU_LOONGSON_2E }, | |
15273 | { "loongson2f", 0, ISA_MIPS3, CPU_LOONGSON_2F }, | |
316f5878 RS |
15274 | |
15275 | /* MIPS IV */ | |
ad3fea08 TS |
15276 | { "r8000", 0, ISA_MIPS4, CPU_R8000 }, |
15277 | { "r10000", 0, ISA_MIPS4, CPU_R10000 }, | |
15278 | { "r12000", 0, ISA_MIPS4, CPU_R12000 }, | |
3aa3176b TS |
15279 | { "r14000", 0, ISA_MIPS4, CPU_R14000 }, |
15280 | { "r16000", 0, ISA_MIPS4, CPU_R16000 }, | |
ad3fea08 TS |
15281 | { "vr5000", 0, ISA_MIPS4, CPU_R5000 }, |
15282 | { "vr5400", 0, ISA_MIPS4, CPU_VR5400 }, | |
15283 | { "vr5500", 0, ISA_MIPS4, CPU_VR5500 }, | |
15284 | { "rm5200", 0, ISA_MIPS4, CPU_R5000 }, | |
15285 | { "rm5230", 0, ISA_MIPS4, CPU_R5000 }, | |
15286 | { "rm5231", 0, ISA_MIPS4, CPU_R5000 }, | |
15287 | { "rm5261", 0, ISA_MIPS4, CPU_R5000 }, | |
15288 | { "rm5721", 0, ISA_MIPS4, CPU_R5000 }, | |
15289 | { "rm7000", 0, ISA_MIPS4, CPU_RM7000 }, | |
15290 | { "rm9000", 0, ISA_MIPS4, CPU_RM9000 }, | |
316f5878 RS |
15291 | |
15292 | /* MIPS 32 */ | |
ad3fea08 TS |
15293 | { "4kc", 0, ISA_MIPS32, CPU_MIPS32 }, |
15294 | { "4km", 0, ISA_MIPS32, CPU_MIPS32 }, | |
15295 | { "4kp", 0, ISA_MIPS32, CPU_MIPS32 }, | |
15296 | { "4ksc", MIPS_CPU_ASE_SMARTMIPS, ISA_MIPS32, CPU_MIPS32 }, | |
15297 | ||
15298 | /* MIPS 32 Release 2 */ | |
15299 | { "4kec", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
15300 | { "4kem", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
15301 | { "4kep", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
15302 | { "4ksd", MIPS_CPU_ASE_SMARTMIPS, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
15303 | { "m4k", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
15304 | { "m4kp", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
ad3fea08 | 15305 | { "24kc", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
0fdf1951 | 15306 | { "24kf2_1", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
ad3fea08 | 15307 | { "24kf", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
0fdf1951 RS |
15308 | { "24kf1_1", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
15309 | /* Deprecated forms of the above. */ | |
15310 | { "24kfx", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
ad3fea08 | 15311 | { "24kx", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
01fd108f | 15312 | /* 24KE is a 24K with DSP ASE, other ASEs are optional. */ |
ad3fea08 | 15313 | { "24kec", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
0fdf1951 | 15314 | { "24kef2_1", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
ad3fea08 | 15315 | { "24kef", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
0fdf1951 RS |
15316 | { "24kef1_1", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
15317 | /* Deprecated forms of the above. */ | |
15318 | { "24kefx", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
65263ce3 | 15319 | { "24kex", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
01fd108f | 15320 | /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */ |
a360e743 TS |
15321 | { "34kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, |
15322 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 RS |
15323 | { "34kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, |
15324 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
a360e743 TS |
15325 | { "34kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, |
15326 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 RS |
15327 | { "34kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, |
15328 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
15329 | /* Deprecated forms of the above. */ | |
15330 | { "34kfx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, | |
15331 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
a360e743 TS |
15332 | { "34kx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, |
15333 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
01fd108f TS |
15334 | /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */ |
15335 | { "74kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, | |
15336 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 RS |
15337 | { "74kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, |
15338 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
01fd108f TS |
15339 | { "74kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, |
15340 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 RS |
15341 | { "74kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, |
15342 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
15343 | { "74kf3_2", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, | |
15344 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
15345 | /* Deprecated forms of the above. */ | |
15346 | { "74kfx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, | |
15347 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
01fd108f TS |
15348 | { "74kx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, |
15349 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
30f8113a SL |
15350 | /* 1004K cores are multiprocessor versions of the 34K. */ |
15351 | { "1004kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, | |
15352 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
15353 | { "1004kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, | |
15354 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
15355 | { "1004kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, | |
15356 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
15357 | { "1004kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, | |
15358 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
32b26a03 | 15359 | |
316f5878 | 15360 | /* MIPS 64 */ |
ad3fea08 TS |
15361 | { "5kc", 0, ISA_MIPS64, CPU_MIPS64 }, |
15362 | { "5kf", 0, ISA_MIPS64, CPU_MIPS64 }, | |
15363 | { "20kc", MIPS_CPU_ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 }, | |
7764b395 | 15364 | { "25kf", MIPS_CPU_ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 }, |
ad3fea08 | 15365 | |
c7a23324 | 15366 | /* Broadcom SB-1 CPU core */ |
65263ce3 TS |
15367 | { "sb1", MIPS_CPU_ASE_MIPS3D | MIPS_CPU_ASE_MDMX, |
15368 | ISA_MIPS64, CPU_SB1 }, | |
1e85aad8 JW |
15369 | /* Broadcom SB-1A CPU core */ |
15370 | { "sb1a", MIPS_CPU_ASE_MIPS3D | MIPS_CPU_ASE_MDMX, | |
15371 | ISA_MIPS64, CPU_SB1 }, | |
d051516a NC |
15372 | |
15373 | { "loongson3a", 0, ISA_MIPS64, CPU_LOONGSON_3A }, | |
e7af610e | 15374 | |
ed163775 MR |
15375 | /* MIPS 64 Release 2 */ |
15376 | ||
967344c6 AN |
15377 | /* Cavium Networks Octeon CPU core */ |
15378 | { "octeon", 0, ISA_MIPS64R2, CPU_OCTEON }, | |
15379 | ||
52b6b6b9 JM |
15380 | /* RMI Xlr */ |
15381 | { "xlr", 0, ISA_MIPS64, CPU_XLR }, | |
15382 | ||
316f5878 RS |
15383 | /* End marker */ |
15384 | { NULL, 0, 0, 0 } | |
15385 | }; | |
e7af610e | 15386 | |
84ea6cf2 | 15387 | |
316f5878 RS |
15388 | /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL |
15389 | with a final "000" replaced by "k". Ignore case. | |
e7af610e | 15390 | |
316f5878 | 15391 | Note: this function is shared between GCC and GAS. */ |
c6c98b38 | 15392 | |
b34976b6 | 15393 | static bfd_boolean |
17a2f251 | 15394 | mips_strict_matching_cpu_name_p (const char *canonical, const char *given) |
316f5878 RS |
15395 | { |
15396 | while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical)) | |
15397 | given++, canonical++; | |
15398 | ||
15399 | return ((*given == 0 && *canonical == 0) | |
15400 | || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0)); | |
15401 | } | |
15402 | ||
15403 | ||
15404 | /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied | |
15405 | CPU name. We've traditionally allowed a lot of variation here. | |
15406 | ||
15407 | Note: this function is shared between GCC and GAS. */ | |
15408 | ||
b34976b6 | 15409 | static bfd_boolean |
17a2f251 | 15410 | mips_matching_cpu_name_p (const char *canonical, const char *given) |
316f5878 RS |
15411 | { |
15412 | /* First see if the name matches exactly, or with a final "000" | |
15413 | turned into "k". */ | |
15414 | if (mips_strict_matching_cpu_name_p (canonical, given)) | |
b34976b6 | 15415 | return TRUE; |
316f5878 RS |
15416 | |
15417 | /* If not, try comparing based on numerical designation alone. | |
15418 | See if GIVEN is an unadorned number, or 'r' followed by a number. */ | |
15419 | if (TOLOWER (*given) == 'r') | |
15420 | given++; | |
15421 | if (!ISDIGIT (*given)) | |
b34976b6 | 15422 | return FALSE; |
316f5878 RS |
15423 | |
15424 | /* Skip over some well-known prefixes in the canonical name, | |
15425 | hoping to find a number there too. */ | |
15426 | if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r') | |
15427 | canonical += 2; | |
15428 | else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm') | |
15429 | canonical += 2; | |
15430 | else if (TOLOWER (canonical[0]) == 'r') | |
15431 | canonical += 1; | |
15432 | ||
15433 | return mips_strict_matching_cpu_name_p (canonical, given); | |
15434 | } | |
15435 | ||
15436 | ||
15437 | /* Parse an option that takes the name of a processor as its argument. | |
15438 | OPTION is the name of the option and CPU_STRING is the argument. | |
15439 | Return the corresponding processor enumeration if the CPU_STRING is | |
15440 | recognized, otherwise report an error and return null. | |
15441 | ||
15442 | A similar function exists in GCC. */ | |
e7af610e NC |
15443 | |
15444 | static const struct mips_cpu_info * | |
17a2f251 | 15445 | mips_parse_cpu (const char *option, const char *cpu_string) |
e7af610e | 15446 | { |
316f5878 | 15447 | const struct mips_cpu_info *p; |
e7af610e | 15448 | |
316f5878 RS |
15449 | /* 'from-abi' selects the most compatible architecture for the given |
15450 | ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the | |
15451 | EABIs, we have to decide whether we're using the 32-bit or 64-bit | |
15452 | version. Look first at the -mgp options, if given, otherwise base | |
15453 | the choice on MIPS_DEFAULT_64BIT. | |
e7af610e | 15454 | |
316f5878 RS |
15455 | Treat NO_ABI like the EABIs. One reason to do this is that the |
15456 | plain 'mips' and 'mips64' configs have 'from-abi' as their default | |
15457 | architecture. This code picks MIPS I for 'mips' and MIPS III for | |
15458 | 'mips64', just as we did in the days before 'from-abi'. */ | |
15459 | if (strcasecmp (cpu_string, "from-abi") == 0) | |
15460 | { | |
15461 | if (ABI_NEEDS_32BIT_REGS (mips_abi)) | |
15462 | return mips_cpu_info_from_isa (ISA_MIPS1); | |
15463 | ||
15464 | if (ABI_NEEDS_64BIT_REGS (mips_abi)) | |
15465 | return mips_cpu_info_from_isa (ISA_MIPS3); | |
15466 | ||
15467 | if (file_mips_gp32 >= 0) | |
15468 | return mips_cpu_info_from_isa (file_mips_gp32 ? ISA_MIPS1 : ISA_MIPS3); | |
15469 | ||
15470 | return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT | |
15471 | ? ISA_MIPS3 | |
15472 | : ISA_MIPS1); | |
15473 | } | |
15474 | ||
15475 | /* 'default' has traditionally been a no-op. Probably not very useful. */ | |
15476 | if (strcasecmp (cpu_string, "default") == 0) | |
15477 | return 0; | |
15478 | ||
15479 | for (p = mips_cpu_info_table; p->name != 0; p++) | |
15480 | if (mips_matching_cpu_name_p (p->name, cpu_string)) | |
15481 | return p; | |
15482 | ||
20203fb9 | 15483 | as_bad (_("Bad value (%s) for %s"), cpu_string, option); |
316f5878 | 15484 | return 0; |
e7af610e NC |
15485 | } |
15486 | ||
316f5878 RS |
15487 | /* Return the canonical processor information for ISA (a member of the |
15488 | ISA_MIPS* enumeration). */ | |
15489 | ||
e7af610e | 15490 | static const struct mips_cpu_info * |
17a2f251 | 15491 | mips_cpu_info_from_isa (int isa) |
e7af610e NC |
15492 | { |
15493 | int i; | |
15494 | ||
15495 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
ad3fea08 | 15496 | if ((mips_cpu_info_table[i].flags & MIPS_CPU_IS_ISA) |
316f5878 | 15497 | && isa == mips_cpu_info_table[i].isa) |
e7af610e NC |
15498 | return (&mips_cpu_info_table[i]); |
15499 | ||
e972090a | 15500 | return NULL; |
e7af610e | 15501 | } |
fef14a42 TS |
15502 | |
15503 | static const struct mips_cpu_info * | |
17a2f251 | 15504 | mips_cpu_info_from_arch (int arch) |
fef14a42 TS |
15505 | { |
15506 | int i; | |
15507 | ||
15508 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
15509 | if (arch == mips_cpu_info_table[i].cpu) | |
15510 | return (&mips_cpu_info_table[i]); | |
15511 | ||
15512 | return NULL; | |
15513 | } | |
316f5878 RS |
15514 | \f |
15515 | static void | |
17a2f251 | 15516 | show (FILE *stream, const char *string, int *col_p, int *first_p) |
316f5878 RS |
15517 | { |
15518 | if (*first_p) | |
15519 | { | |
15520 | fprintf (stream, "%24s", ""); | |
15521 | *col_p = 24; | |
15522 | } | |
15523 | else | |
15524 | { | |
15525 | fprintf (stream, ", "); | |
15526 | *col_p += 2; | |
15527 | } | |
e7af610e | 15528 | |
316f5878 RS |
15529 | if (*col_p + strlen (string) > 72) |
15530 | { | |
15531 | fprintf (stream, "\n%24s", ""); | |
15532 | *col_p = 24; | |
15533 | } | |
15534 | ||
15535 | fprintf (stream, "%s", string); | |
15536 | *col_p += strlen (string); | |
15537 | ||
15538 | *first_p = 0; | |
15539 | } | |
15540 | ||
15541 | void | |
17a2f251 | 15542 | md_show_usage (FILE *stream) |
e7af610e | 15543 | { |
316f5878 RS |
15544 | int column, first; |
15545 | size_t i; | |
15546 | ||
15547 | fprintf (stream, _("\ | |
15548 | MIPS options:\n\ | |
316f5878 RS |
15549 | -EB generate big endian output\n\ |
15550 | -EL generate little endian output\n\ | |
15551 | -g, -g2 do not remove unneeded NOPs or swap branches\n\ | |
15552 | -G NUM allow referencing objects up to NUM bytes\n\ | |
15553 | implicitly with the gp register [default 8]\n")); | |
15554 | fprintf (stream, _("\ | |
15555 | -mips1 generate MIPS ISA I instructions\n\ | |
15556 | -mips2 generate MIPS ISA II instructions\n\ | |
15557 | -mips3 generate MIPS ISA III instructions\n\ | |
15558 | -mips4 generate MIPS ISA IV instructions\n\ | |
15559 | -mips5 generate MIPS ISA V instructions\n\ | |
15560 | -mips32 generate MIPS32 ISA instructions\n\ | |
af7ee8bf | 15561 | -mips32r2 generate MIPS32 release 2 ISA instructions\n\ |
316f5878 | 15562 | -mips64 generate MIPS64 ISA instructions\n\ |
5f74bc13 | 15563 | -mips64r2 generate MIPS64 release 2 ISA instructions\n\ |
316f5878 RS |
15564 | -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n")); |
15565 | ||
15566 | first = 1; | |
e7af610e NC |
15567 | |
15568 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
316f5878 RS |
15569 | show (stream, mips_cpu_info_table[i].name, &column, &first); |
15570 | show (stream, "from-abi", &column, &first); | |
15571 | fputc ('\n', stream); | |
e7af610e | 15572 | |
316f5878 RS |
15573 | fprintf (stream, _("\ |
15574 | -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\ | |
15575 | -no-mCPU don't generate code specific to CPU.\n\ | |
15576 | For -mCPU and -no-mCPU, CPU must be one of:\n")); | |
15577 | ||
15578 | first = 1; | |
15579 | ||
15580 | show (stream, "3900", &column, &first); | |
15581 | show (stream, "4010", &column, &first); | |
15582 | show (stream, "4100", &column, &first); | |
15583 | show (stream, "4650", &column, &first); | |
15584 | fputc ('\n', stream); | |
15585 | ||
15586 | fprintf (stream, _("\ | |
15587 | -mips16 generate mips16 instructions\n\ | |
15588 | -no-mips16 do not generate mips16 instructions\n")); | |
15589 | fprintf (stream, _("\ | |
e16bfa71 TS |
15590 | -msmartmips generate smartmips instructions\n\ |
15591 | -mno-smartmips do not generate smartmips instructions\n")); | |
15592 | fprintf (stream, _("\ | |
74cd071d CF |
15593 | -mdsp generate DSP instructions\n\ |
15594 | -mno-dsp do not generate DSP instructions\n")); | |
15595 | fprintf (stream, _("\ | |
8b082fb1 TS |
15596 | -mdspr2 generate DSP R2 instructions\n\ |
15597 | -mno-dspr2 do not generate DSP R2 instructions\n")); | |
15598 | fprintf (stream, _("\ | |
ef2e4d86 CF |
15599 | -mmt generate MT instructions\n\ |
15600 | -mno-mt do not generate MT instructions\n")); | |
15601 | fprintf (stream, _("\ | |
c67a084a NC |
15602 | -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\ |
15603 | -mfix-loongson2f-nop work around Loongson2F NOP errata\n\ | |
d766e8ec | 15604 | -mfix-vr4120 work around certain VR4120 errata\n\ |
7d8e00cf | 15605 | -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\ |
6a32d874 | 15606 | -mfix-24k insert a nop after ERET and DERET instructions\n\ |
d954098f | 15607 | -mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\ |
316f5878 RS |
15608 | -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\ |
15609 | -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\ | |
aed1a261 | 15610 | -msym32 assume all symbols have 32-bit values\n\ |
316f5878 RS |
15611 | -O0 remove unneeded NOPs, do not swap branches\n\ |
15612 | -O remove unneeded NOPs and swap branches\n\ | |
316f5878 RS |
15613 | --trap, --no-break trap exception on div by 0 and mult overflow\n\ |
15614 | --break, --no-trap break exception on div by 0 and mult overflow\n")); | |
037b32b9 AN |
15615 | fprintf (stream, _("\ |
15616 | -mhard-float allow floating-point instructions\n\ | |
15617 | -msoft-float do not allow floating-point instructions\n\ | |
15618 | -msingle-float only allow 32-bit floating-point operations\n\ | |
15619 | -mdouble-float allow 32-bit and 64-bit floating-point operations\n\ | |
15620 | --[no-]construct-floats [dis]allow floating point values to be constructed\n" | |
15621 | )); | |
316f5878 RS |
15622 | #ifdef OBJ_ELF |
15623 | fprintf (stream, _("\ | |
15624 | -KPIC, -call_shared generate SVR4 position independent code\n\ | |
861fb55a | 15625 | -call_nonpic generate non-PIC code that can operate with DSOs\n\ |
0c000745 | 15626 | -mvxworks-pic generate VxWorks position independent code\n\ |
861fb55a | 15627 | -non_shared do not generate code that can operate with DSOs\n\ |
316f5878 | 15628 | -xgot assume a 32 bit GOT\n\ |
dcd410fe | 15629 | -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\ |
bbe506e8 | 15630 | -mshared, -mno-shared disable/enable .cpload optimization for\n\ |
d821e36b | 15631 | position dependent (non shared) code\n\ |
316f5878 RS |
15632 | -mabi=ABI create ABI conformant object file for:\n")); |
15633 | ||
15634 | first = 1; | |
15635 | ||
15636 | show (stream, "32", &column, &first); | |
15637 | show (stream, "o64", &column, &first); | |
15638 | show (stream, "n32", &column, &first); | |
15639 | show (stream, "64", &column, &first); | |
15640 | show (stream, "eabi", &column, &first); | |
15641 | ||
15642 | fputc ('\n', stream); | |
15643 | ||
15644 | fprintf (stream, _("\ | |
15645 | -32 create o32 ABI object file (default)\n\ | |
15646 | -n32 create n32 ABI object file\n\ | |
15647 | -64 create 64 ABI object file\n")); | |
15648 | #endif | |
e7af610e | 15649 | } |
14e777e0 | 15650 | |
1575952e | 15651 | #ifdef TE_IRIX |
14e777e0 | 15652 | enum dwarf2_format |
413a266c | 15653 | mips_dwarf2_format (asection *sec ATTRIBUTE_UNUSED) |
14e777e0 | 15654 | { |
369943fe | 15655 | if (HAVE_64BIT_SYMBOLS) |
1575952e | 15656 | return dwarf2_format_64bit_irix; |
14e777e0 KB |
15657 | else |
15658 | return dwarf2_format_32bit; | |
15659 | } | |
1575952e | 15660 | #endif |
73369e65 EC |
15661 | |
15662 | int | |
15663 | mips_dwarf2_addr_size (void) | |
15664 | { | |
6b6b3450 | 15665 | if (HAVE_64BIT_OBJECTS) |
73369e65 | 15666 | return 8; |
73369e65 EC |
15667 | else |
15668 | return 4; | |
15669 | } | |
5862107c EC |
15670 | |
15671 | /* Standard calling conventions leave the CFA at SP on entry. */ | |
15672 | void | |
15673 | mips_cfi_frame_initial_instructions (void) | |
15674 | { | |
15675 | cfi_add_CFA_def_cfa_register (SP); | |
15676 | } | |
15677 | ||
707bfff6 TS |
15678 | int |
15679 | tc_mips_regname_to_dw2regnum (char *regname) | |
15680 | { | |
15681 | unsigned int regnum = -1; | |
15682 | unsigned int reg; | |
15683 | ||
15684 | if (reg_lookup (®name, RTYPE_GP | RTYPE_NUM, ®)) | |
15685 | regnum = reg; | |
15686 | ||
15687 | return regnum; | |
15688 | } |