Commit | Line | Data |
---|---|---|
252b5132 | 1 | /* tc-mips.c -- assemble code for a MIPS chip. |
81912461 | 2 | Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, |
f17c130b | 3 | 2003, 2004, 2005 Free Software Foundation, Inc. |
252b5132 RH |
4 | Contributed by the OSF and Ralph Campbell. |
5 | Written by Keith Knowles and Ralph Campbell, working independently. | |
6 | Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus | |
7 | Support. | |
8 | ||
9 | This file is part of GAS. | |
10 | ||
11 | GAS is free software; you can redistribute it and/or modify | |
12 | it under the terms of the GNU General Public License as published by | |
13 | the Free Software Foundation; either version 2, or (at your option) | |
14 | any later version. | |
15 | ||
16 | GAS is distributed in the hope that it will be useful, | |
17 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | GNU General Public License for more details. | |
20 | ||
21 | You should have received a copy of the GNU General Public License | |
22 | along with GAS; see the file COPYING. If not, write to the Free | |
4b4da160 NC |
23 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
24 | 02110-1301, USA. */ | |
252b5132 RH |
25 | |
26 | #include "as.h" | |
27 | #include "config.h" | |
28 | #include "subsegs.h" | |
3882b010 | 29 | #include "safe-ctype.h" |
252b5132 | 30 | |
252b5132 | 31 | #include <stdarg.h> |
252b5132 RH |
32 | |
33 | #include "opcode/mips.h" | |
34 | #include "itbl-ops.h" | |
c5dd6aab | 35 | #include "dwarf2dbg.h" |
5862107c | 36 | #include "dw2gencfi.h" |
252b5132 RH |
37 | |
38 | #ifdef DEBUG | |
39 | #define DBG(x) printf x | |
40 | #else | |
41 | #define DBG(x) | |
42 | #endif | |
43 | ||
44 | #ifdef OBJ_MAYBE_ELF | |
45 | /* Clean up namespace so we can include obj-elf.h too. */ | |
17a2f251 TS |
46 | static int mips_output_flavor (void); |
47 | static int mips_output_flavor (void) { return OUTPUT_FLAVOR; } | |
252b5132 RH |
48 | #undef OBJ_PROCESS_STAB |
49 | #undef OUTPUT_FLAVOR | |
50 | #undef S_GET_ALIGN | |
51 | #undef S_GET_SIZE | |
52 | #undef S_SET_ALIGN | |
53 | #undef S_SET_SIZE | |
252b5132 RH |
54 | #undef obj_frob_file |
55 | #undef obj_frob_file_after_relocs | |
56 | #undef obj_frob_symbol | |
57 | #undef obj_pop_insert | |
58 | #undef obj_sec_sym_ok_for_reloc | |
59 | #undef OBJ_COPY_SYMBOL_ATTRIBUTES | |
60 | ||
61 | #include "obj-elf.h" | |
62 | /* Fix any of them that we actually care about. */ | |
63 | #undef OUTPUT_FLAVOR | |
64 | #define OUTPUT_FLAVOR mips_output_flavor() | |
65 | #endif | |
66 | ||
67 | #if defined (OBJ_ELF) | |
68 | #include "elf/mips.h" | |
69 | #endif | |
70 | ||
71 | #ifndef ECOFF_DEBUGGING | |
72 | #define NO_ECOFF_DEBUGGING | |
73 | #define ECOFF_DEBUGGING 0 | |
74 | #endif | |
75 | ||
ecb4347a DJ |
76 | int mips_flag_mdebug = -1; |
77 | ||
dcd410fe RO |
78 | /* Control generation of .pdr sections. Off by default on IRIX: the native |
79 | linker doesn't know about and discards them, but relocations against them | |
80 | remain, leading to rld crashes. */ | |
81 | #ifdef TE_IRIX | |
82 | int mips_flag_pdr = FALSE; | |
83 | #else | |
84 | int mips_flag_pdr = TRUE; | |
85 | #endif | |
86 | ||
252b5132 RH |
87 | #include "ecoff.h" |
88 | ||
89 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
90 | static char *mips_regmask_frag; | |
91 | #endif | |
92 | ||
85b51719 | 93 | #define ZERO 0 |
252b5132 RH |
94 | #define AT 1 |
95 | #define TREG 24 | |
96 | #define PIC_CALL_REG 25 | |
97 | #define KT0 26 | |
98 | #define KT1 27 | |
99 | #define GP 28 | |
100 | #define SP 29 | |
101 | #define FP 30 | |
102 | #define RA 31 | |
103 | ||
104 | #define ILLEGAL_REG (32) | |
105 | ||
106 | /* Allow override of standard little-endian ECOFF format. */ | |
107 | ||
108 | #ifndef ECOFF_LITTLE_FORMAT | |
109 | #define ECOFF_LITTLE_FORMAT "ecoff-littlemips" | |
110 | #endif | |
111 | ||
112 | extern int target_big_endian; | |
113 | ||
252b5132 | 114 | /* The name of the readonly data section. */ |
4d0d148d | 115 | #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_ecoff_flavour \ |
252b5132 | 116 | ? ".rdata" \ |
056350c6 NC |
117 | : OUTPUT_FLAVOR == bfd_target_coff_flavour \ |
118 | ? ".rdata" \ | |
252b5132 RH |
119 | : OUTPUT_FLAVOR == bfd_target_elf_flavour \ |
120 | ? ".rodata" \ | |
121 | : (abort (), "")) | |
122 | ||
47e39b9d RS |
123 | /* Information about an instruction, including its format, operands |
124 | and fixups. */ | |
125 | struct mips_cl_insn | |
126 | { | |
127 | /* The opcode's entry in mips_opcodes or mips16_opcodes. */ | |
128 | const struct mips_opcode *insn_mo; | |
129 | ||
130 | /* True if this is a mips16 instruction and if we want the extended | |
131 | form of INSN_MO. */ | |
132 | bfd_boolean use_extend; | |
133 | ||
134 | /* The 16-bit extension instruction to use when USE_EXTEND is true. */ | |
135 | unsigned short extend; | |
136 | ||
137 | /* The 16-bit or 32-bit bitstring of the instruction itself. This is | |
138 | a copy of INSN_MO->match with the operands filled in. */ | |
139 | unsigned long insn_opcode; | |
140 | ||
141 | /* The frag that contains the instruction. */ | |
142 | struct frag *frag; | |
143 | ||
144 | /* The offset into FRAG of the first instruction byte. */ | |
145 | long where; | |
146 | ||
147 | /* The relocs associated with the instruction, if any. */ | |
148 | fixS *fixp[3]; | |
149 | ||
a38419a5 RS |
150 | /* True if this entry cannot be moved from its current position. */ |
151 | unsigned int fixed_p : 1; | |
47e39b9d RS |
152 | |
153 | /* True if this instruction occured in a .set noreorder block. */ | |
154 | unsigned int noreorder_p : 1; | |
155 | ||
2fa15973 RS |
156 | /* True for mips16 instructions that jump to an absolute address. */ |
157 | unsigned int mips16_absolute_jump_p : 1; | |
47e39b9d RS |
158 | }; |
159 | ||
a325df1d TS |
160 | /* The ABI to use. */ |
161 | enum mips_abi_level | |
162 | { | |
163 | NO_ABI = 0, | |
164 | O32_ABI, | |
165 | O64_ABI, | |
166 | N32_ABI, | |
167 | N64_ABI, | |
168 | EABI_ABI | |
169 | }; | |
170 | ||
171 | /* MIPS ABI we are using for this output file. */ | |
316f5878 | 172 | static enum mips_abi_level mips_abi = NO_ABI; |
a325df1d | 173 | |
143d77c5 EC |
174 | /* Whether or not we have code that can call pic code. */ |
175 | int mips_abicalls = FALSE; | |
176 | ||
aa6975fb ILT |
177 | /* Whether or not we have code which can be put into a shared |
178 | library. */ | |
179 | static bfd_boolean mips_in_shared = TRUE; | |
180 | ||
252b5132 RH |
181 | /* This is the set of options which may be modified by the .set |
182 | pseudo-op. We use a struct so that .set push and .set pop are more | |
183 | reliable. */ | |
184 | ||
e972090a NC |
185 | struct mips_set_options |
186 | { | |
252b5132 RH |
187 | /* MIPS ISA (Instruction Set Architecture) level. This is set to -1 |
188 | if it has not been initialized. Changed by `.set mipsN', and the | |
189 | -mipsN command line option, and the default CPU. */ | |
190 | int isa; | |
1f25f5d3 CD |
191 | /* Enabled Application Specific Extensions (ASEs). These are set to -1 |
192 | if they have not been initialized. Changed by `.set <asename>', by | |
193 | command line options, and based on the default architecture. */ | |
194 | int ase_mips3d; | |
deec1734 | 195 | int ase_mdmx; |
74cd071d | 196 | int ase_dsp; |
ef2e4d86 | 197 | int ase_mt; |
252b5132 RH |
198 | /* Whether we are assembling for the mips16 processor. 0 if we are |
199 | not, 1 if we are, and -1 if the value has not been initialized. | |
200 | Changed by `.set mips16' and `.set nomips16', and the -mips16 and | |
201 | -nomips16 command line options, and the default CPU. */ | |
202 | int mips16; | |
203 | /* Non-zero if we should not reorder instructions. Changed by `.set | |
204 | reorder' and `.set noreorder'. */ | |
205 | int noreorder; | |
206 | /* Non-zero if we should not permit the $at ($1) register to be used | |
207 | in instructions. Changed by `.set at' and `.set noat'. */ | |
208 | int noat; | |
209 | /* Non-zero if we should warn when a macro instruction expands into | |
210 | more than one machine instruction. Changed by `.set nomacro' and | |
211 | `.set macro'. */ | |
212 | int warn_about_macros; | |
213 | /* Non-zero if we should not move instructions. Changed by `.set | |
214 | move', `.set volatile', `.set nomove', and `.set novolatile'. */ | |
215 | int nomove; | |
216 | /* Non-zero if we should not optimize branches by moving the target | |
217 | of the branch into the delay slot. Actually, we don't perform | |
218 | this optimization anyhow. Changed by `.set bopt' and `.set | |
219 | nobopt'. */ | |
220 | int nobopt; | |
221 | /* Non-zero if we should not autoextend mips16 instructions. | |
222 | Changed by `.set autoextend' and `.set noautoextend'. */ | |
223 | int noautoextend; | |
a325df1d TS |
224 | /* Restrict general purpose registers and floating point registers |
225 | to 32 bit. This is initially determined when -mgp32 or -mfp32 | |
226 | is passed but can changed if the assembler code uses .set mipsN. */ | |
227 | int gp32; | |
228 | int fp32; | |
fef14a42 TS |
229 | /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march |
230 | command line option, and the default CPU. */ | |
231 | int arch; | |
aed1a261 RS |
232 | /* True if ".set sym32" is in effect. */ |
233 | bfd_boolean sym32; | |
252b5132 RH |
234 | }; |
235 | ||
a325df1d | 236 | /* True if -mgp32 was passed. */ |
a8e8e863 | 237 | static int file_mips_gp32 = -1; |
a325df1d TS |
238 | |
239 | /* True if -mfp32 was passed. */ | |
a8e8e863 | 240 | static int file_mips_fp32 = -1; |
a325df1d | 241 | |
252b5132 | 242 | /* This is the struct we use to hold the current set of options. Note |
a4672219 | 243 | that we must set the isa field to ISA_UNKNOWN and the ASE fields to |
e7af610e | 244 | -1 to indicate that they have not been initialized. */ |
252b5132 | 245 | |
e972090a NC |
246 | static struct mips_set_options mips_opts = |
247 | { | |
ef2e4d86 | 248 | ISA_UNKNOWN, -1, -1, -1, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0, CPU_UNKNOWN, FALSE |
e7af610e | 249 | }; |
252b5132 RH |
250 | |
251 | /* These variables are filled in with the masks of registers used. | |
252 | The object format code reads them and puts them in the appropriate | |
253 | place. */ | |
254 | unsigned long mips_gprmask; | |
255 | unsigned long mips_cprmask[4]; | |
256 | ||
257 | /* MIPS ISA we are using for this output file. */ | |
e7af610e | 258 | static int file_mips_isa = ISA_UNKNOWN; |
252b5132 | 259 | |
a4672219 TS |
260 | /* True if -mips16 was passed or implied by arguments passed on the |
261 | command line (e.g., by -march). */ | |
262 | static int file_ase_mips16; | |
263 | ||
1f25f5d3 CD |
264 | /* True if -mips3d was passed or implied by arguments passed on the |
265 | command line (e.g., by -march). */ | |
266 | static int file_ase_mips3d; | |
267 | ||
deec1734 CD |
268 | /* True if -mdmx was passed or implied by arguments passed on the |
269 | command line (e.g., by -march). */ | |
270 | static int file_ase_mdmx; | |
271 | ||
74cd071d CF |
272 | /* True if -mdsp was passed or implied by arguments passed on the |
273 | command line (e.g., by -march). */ | |
274 | static int file_ase_dsp; | |
275 | ||
ef2e4d86 CF |
276 | /* True if -mmt was passed or implied by arguments passed on the |
277 | command line (e.g., by -march). */ | |
278 | static int file_ase_mt; | |
279 | ||
ec68c924 | 280 | /* The argument of the -march= flag. The architecture we are assembling. */ |
fef14a42 | 281 | static int file_mips_arch = CPU_UNKNOWN; |
316f5878 | 282 | static const char *mips_arch_string; |
ec68c924 EC |
283 | |
284 | /* The argument of the -mtune= flag. The architecture for which we | |
285 | are optimizing. */ | |
286 | static int mips_tune = CPU_UNKNOWN; | |
316f5878 | 287 | static const char *mips_tune_string; |
ec68c924 | 288 | |
316f5878 | 289 | /* True when generating 32-bit code for a 64-bit processor. */ |
252b5132 RH |
290 | static int mips_32bitmode = 0; |
291 | ||
316f5878 RS |
292 | /* True if the given ABI requires 32-bit registers. */ |
293 | #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI) | |
294 | ||
295 | /* Likewise 64-bit registers. */ | |
296 | #define ABI_NEEDS_64BIT_REGS(ABI) \ | |
297 | ((ABI) == N32_ABI \ | |
298 | || (ABI) == N64_ABI \ | |
299 | || (ABI) == O64_ABI) | |
300 | ||
bdaaa2e1 | 301 | /* Return true if ISA supports 64 bit gp register instructions. */ |
9ce8a5dd | 302 | #define ISA_HAS_64BIT_REGS(ISA) ( \ |
e7af610e NC |
303 | (ISA) == ISA_MIPS3 \ |
304 | || (ISA) == ISA_MIPS4 \ | |
84ea6cf2 | 305 | || (ISA) == ISA_MIPS5 \ |
d1cf510e | 306 | || (ISA) == ISA_MIPS64 \ |
5f74bc13 | 307 | || (ISA) == ISA_MIPS64R2 \ |
9ce8a5dd GRK |
308 | ) |
309 | ||
af7ee8bf CD |
310 | /* Return true if ISA supports 64-bit right rotate (dror et al.) |
311 | instructions. */ | |
312 | #define ISA_HAS_DROR(ISA) ( \ | |
5f74bc13 | 313 | (ISA) == ISA_MIPS64R2 \ |
af7ee8bf CD |
314 | ) |
315 | ||
316 | /* Return true if ISA supports 32-bit right rotate (ror et al.) | |
317 | instructions. */ | |
318 | #define ISA_HAS_ROR(ISA) ( \ | |
319 | (ISA) == ISA_MIPS32R2 \ | |
5f74bc13 | 320 | || (ISA) == ISA_MIPS64R2 \ |
af7ee8bf CD |
321 | ) |
322 | ||
e013f690 | 323 | #define HAVE_32BIT_GPRS \ |
316f5878 | 324 | (mips_opts.gp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
ca4e0257 | 325 | |
e013f690 | 326 | #define HAVE_32BIT_FPRS \ |
316f5878 | 327 | (mips_opts.fp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
ca4e0257 RS |
328 | |
329 | #define HAVE_64BIT_GPRS (! HAVE_32BIT_GPRS) | |
330 | #define HAVE_64BIT_FPRS (! HAVE_32BIT_FPRS) | |
331 | ||
316f5878 | 332 | #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI) |
e013f690 | 333 | |
316f5878 | 334 | #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI) |
e013f690 | 335 | |
3b91255e RS |
336 | /* True if relocations are stored in-place. */ |
337 | #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI) | |
338 | ||
aed1a261 RS |
339 | /* The ABI-derived address size. */ |
340 | #define HAVE_64BIT_ADDRESSES \ | |
341 | (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI)) | |
342 | #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES) | |
e013f690 | 343 | |
aed1a261 RS |
344 | /* The size of symbolic constants (i.e., expressions of the form |
345 | "SYMBOL" or "SYMBOL + OFFSET"). */ | |
346 | #define HAVE_32BIT_SYMBOLS \ | |
347 | (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32) | |
348 | #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS) | |
ca4e0257 | 349 | |
b7c7d6c1 TS |
350 | /* Addresses are loaded in different ways, depending on the address size |
351 | in use. The n32 ABI Documentation also mandates the use of additions | |
352 | with overflow checking, but existing implementations don't follow it. */ | |
f899b4b8 | 353 | #define ADDRESS_ADD_INSN \ |
b7c7d6c1 | 354 | (HAVE_32BIT_ADDRESSES ? "addu" : "daddu") |
f899b4b8 TS |
355 | |
356 | #define ADDRESS_ADDI_INSN \ | |
b7c7d6c1 | 357 | (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu") |
f899b4b8 TS |
358 | |
359 | #define ADDRESS_LOAD_INSN \ | |
360 | (HAVE_32BIT_ADDRESSES ? "lw" : "ld") | |
361 | ||
362 | #define ADDRESS_STORE_INSN \ | |
363 | (HAVE_32BIT_ADDRESSES ? "sw" : "sd") | |
364 | ||
a4672219 | 365 | /* Return true if the given CPU supports the MIPS16 ASE. */ |
3396de36 TS |
366 | #define CPU_HAS_MIPS16(cpu) \ |
367 | (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \ | |
368 | || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0) | |
a4672219 | 369 | |
1f25f5d3 CD |
370 | /* Return true if the given CPU supports the MIPS3D ASE. */ |
371 | #define CPU_HAS_MIPS3D(cpu) ((cpu) == CPU_SB1 \ | |
372 | ) | |
373 | ||
deec1734 | 374 | /* Return true if the given CPU supports the MDMX ASE. */ |
b34976b6 | 375 | #define CPU_HAS_MDMX(cpu) (FALSE \ |
deec1734 CD |
376 | ) |
377 | ||
74cd071d CF |
378 | /* Return true if the given CPU supports the DSP ASE. */ |
379 | #define CPU_HAS_DSP(cpu) (FALSE \ | |
380 | ) | |
381 | ||
ef2e4d86 CF |
382 | /* Return true if the given CPU supports the MT ASE. */ |
383 | #define CPU_HAS_MT(cpu) (FALSE \ | |
384 | ) | |
385 | ||
60b63b72 RS |
386 | /* True if CPU has a dror instruction. */ |
387 | #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500) | |
388 | ||
389 | /* True if CPU has a ror instruction. */ | |
390 | #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU) | |
391 | ||
c8978940 CD |
392 | /* True if mflo and mfhi can be immediately followed by instructions |
393 | which write to the HI and LO registers. | |
394 | ||
395 | According to MIPS specifications, MIPS ISAs I, II, and III need | |
396 | (at least) two instructions between the reads of HI/LO and | |
397 | instructions which write them, and later ISAs do not. Contradicting | |
398 | the MIPS specifications, some MIPS IV processor user manuals (e.g. | |
399 | the UM for the NEC Vr5000) document needing the instructions between | |
400 | HI/LO reads and writes, as well. Therefore, we declare only MIPS32, | |
401 | MIPS64 and later ISAs to have the interlocks, plus any specific | |
402 | earlier-ISA CPUs for which CPU documentation declares that the | |
403 | instructions are really interlocked. */ | |
404 | #define hilo_interlocks \ | |
405 | (mips_opts.isa == ISA_MIPS32 \ | |
406 | || mips_opts.isa == ISA_MIPS32R2 \ | |
407 | || mips_opts.isa == ISA_MIPS64 \ | |
408 | || mips_opts.isa == ISA_MIPS64R2 \ | |
409 | || mips_opts.arch == CPU_R4010 \ | |
410 | || mips_opts.arch == CPU_R10000 \ | |
411 | || mips_opts.arch == CPU_R12000 \ | |
412 | || mips_opts.arch == CPU_RM7000 \ | |
c8978940 CD |
413 | || mips_opts.arch == CPU_VR5500 \ |
414 | ) | |
252b5132 RH |
415 | |
416 | /* Whether the processor uses hardware interlocks to protect reads | |
81912461 ILT |
417 | from the GPRs after they are loaded from memory, and thus does not |
418 | require nops to be inserted. This applies to instructions marked | |
419 | INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA | |
420 | level I. */ | |
252b5132 | 421 | #define gpr_interlocks \ |
e7af610e | 422 | (mips_opts.isa != ISA_MIPS1 \ |
fef14a42 | 423 | || mips_opts.arch == CPU_R3900) |
252b5132 | 424 | |
81912461 ILT |
425 | /* Whether the processor uses hardware interlocks to avoid delays |
426 | required by coprocessor instructions, and thus does not require | |
427 | nops to be inserted. This applies to instructions marked | |
428 | INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays | |
429 | between instructions marked INSN_WRITE_COND_CODE and ones marked | |
430 | INSN_READ_COND_CODE. These nops are only required at MIPS ISA | |
431 | levels I, II, and III. */ | |
bdaaa2e1 | 432 | /* Itbl support may require additional care here. */ |
81912461 ILT |
433 | #define cop_interlocks \ |
434 | ((mips_opts.isa != ISA_MIPS1 \ | |
435 | && mips_opts.isa != ISA_MIPS2 \ | |
436 | && mips_opts.isa != ISA_MIPS3) \ | |
437 | || mips_opts.arch == CPU_R4300 \ | |
81912461 ILT |
438 | ) |
439 | ||
440 | /* Whether the processor uses hardware interlocks to protect reads | |
441 | from coprocessor registers after they are loaded from memory, and | |
442 | thus does not require nops to be inserted. This applies to | |
443 | instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only | |
444 | requires at MIPS ISA level I. */ | |
445 | #define cop_mem_interlocks (mips_opts.isa != ISA_MIPS1) | |
252b5132 | 446 | |
6b76fefe CM |
447 | /* Is this a mfhi or mflo instruction? */ |
448 | #define MF_HILO_INSN(PINFO) \ | |
449 | ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO)) | |
450 | ||
252b5132 RH |
451 | /* MIPS PIC level. */ |
452 | ||
a161fe53 | 453 | enum mips_pic_level mips_pic; |
252b5132 | 454 | |
c9914766 | 455 | /* 1 if we should generate 32 bit offsets from the $gp register in |
252b5132 | 456 | SVR4_PIC mode. Currently has no meaning in other modes. */ |
c9914766 | 457 | static int mips_big_got = 0; |
252b5132 RH |
458 | |
459 | /* 1 if trap instructions should used for overflow rather than break | |
460 | instructions. */ | |
c9914766 | 461 | static int mips_trap = 0; |
252b5132 | 462 | |
119d663a | 463 | /* 1 if double width floating point constants should not be constructed |
b6ff326e | 464 | by assembling two single width halves into two single width floating |
119d663a NC |
465 | point registers which just happen to alias the double width destination |
466 | register. On some architectures this aliasing can be disabled by a bit | |
d547a75e | 467 | in the status register, and the setting of this bit cannot be determined |
119d663a NC |
468 | automatically at assemble time. */ |
469 | static int mips_disable_float_construction; | |
470 | ||
252b5132 RH |
471 | /* Non-zero if any .set noreorder directives were used. */ |
472 | ||
473 | static int mips_any_noreorder; | |
474 | ||
6b76fefe CM |
475 | /* Non-zero if nops should be inserted when the register referenced in |
476 | an mfhi/mflo instruction is read in the next two instructions. */ | |
477 | static int mips_7000_hilo_fix; | |
478 | ||
252b5132 | 479 | /* The size of the small data section. */ |
156c2f8b | 480 | static unsigned int g_switch_value = 8; |
252b5132 RH |
481 | /* Whether the -G option was used. */ |
482 | static int g_switch_seen = 0; | |
483 | ||
484 | #define N_RMASK 0xc4 | |
485 | #define N_VFP 0xd4 | |
486 | ||
487 | /* If we can determine in advance that GP optimization won't be | |
488 | possible, we can skip the relaxation stuff that tries to produce | |
489 | GP-relative references. This makes delay slot optimization work | |
490 | better. | |
491 | ||
492 | This function can only provide a guess, but it seems to work for | |
fba2b7f9 GK |
493 | gcc output. It needs to guess right for gcc, otherwise gcc |
494 | will put what it thinks is a GP-relative instruction in a branch | |
495 | delay slot. | |
252b5132 RH |
496 | |
497 | I don't know if a fix is needed for the SVR4_PIC mode. I've only | |
498 | fixed it for the non-PIC mode. KR 95/04/07 */ | |
17a2f251 | 499 | static int nopic_need_relax (symbolS *, int); |
252b5132 RH |
500 | |
501 | /* handle of the OPCODE hash table */ | |
502 | static struct hash_control *op_hash = NULL; | |
503 | ||
504 | /* The opcode hash table we use for the mips16. */ | |
505 | static struct hash_control *mips16_op_hash = NULL; | |
506 | ||
507 | /* This array holds the chars that always start a comment. If the | |
508 | pre-processor is disabled, these aren't very useful */ | |
509 | const char comment_chars[] = "#"; | |
510 | ||
511 | /* This array holds the chars that only start a comment at the beginning of | |
512 | a line. If the line seems to have the form '# 123 filename' | |
513 | .line and .file directives will appear in the pre-processed output */ | |
514 | /* Note that input_file.c hand checks for '#' at the beginning of the | |
515 | first line of the input file. This is because the compiler outputs | |
bdaaa2e1 | 516 | #NO_APP at the beginning of its output. */ |
252b5132 RH |
517 | /* Also note that C style comments are always supported. */ |
518 | const char line_comment_chars[] = "#"; | |
519 | ||
bdaaa2e1 | 520 | /* This array holds machine specific line separator characters. */ |
63a0b638 | 521 | const char line_separator_chars[] = ";"; |
252b5132 RH |
522 | |
523 | /* Chars that can be used to separate mant from exp in floating point nums */ | |
524 | const char EXP_CHARS[] = "eE"; | |
525 | ||
526 | /* Chars that mean this number is a floating point constant */ | |
527 | /* As in 0f12.456 */ | |
528 | /* or 0d1.2345e12 */ | |
529 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; | |
530 | ||
531 | /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be | |
532 | changed in read.c . Ideally it shouldn't have to know about it at all, | |
533 | but nothing is ideal around here. | |
534 | */ | |
535 | ||
536 | static char *insn_error; | |
537 | ||
538 | static int auto_align = 1; | |
539 | ||
540 | /* When outputting SVR4 PIC code, the assembler needs to know the | |
541 | offset in the stack frame from which to restore the $gp register. | |
542 | This is set by the .cprestore pseudo-op, and saved in this | |
543 | variable. */ | |
544 | static offsetT mips_cprestore_offset = -1; | |
545 | ||
67c1ffbe | 546 | /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some |
6478892d | 547 | more optimizations, it can use a register value instead of a memory-saved |
956cd1d6 | 548 | offset and even an other register than $gp as global pointer. */ |
6478892d TS |
549 | static offsetT mips_cpreturn_offset = -1; |
550 | static int mips_cpreturn_register = -1; | |
551 | static int mips_gp_register = GP; | |
def2e0dd | 552 | static int mips_gprel_offset = 0; |
6478892d | 553 | |
7a621144 DJ |
554 | /* Whether mips_cprestore_offset has been set in the current function |
555 | (or whether it has already been warned about, if not). */ | |
556 | static int mips_cprestore_valid = 0; | |
557 | ||
252b5132 RH |
558 | /* This is the register which holds the stack frame, as set by the |
559 | .frame pseudo-op. This is needed to implement .cprestore. */ | |
560 | static int mips_frame_reg = SP; | |
561 | ||
7a621144 DJ |
562 | /* Whether mips_frame_reg has been set in the current function |
563 | (or whether it has already been warned about, if not). */ | |
564 | static int mips_frame_reg_valid = 0; | |
565 | ||
252b5132 RH |
566 | /* To output NOP instructions correctly, we need to keep information |
567 | about the previous two instructions. */ | |
568 | ||
569 | /* Whether we are optimizing. The default value of 2 means to remove | |
570 | unneeded NOPs and swap branch instructions when possible. A value | |
571 | of 1 means to not swap branches. A value of 0 means to always | |
572 | insert NOPs. */ | |
573 | static int mips_optimize = 2; | |
574 | ||
575 | /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is | |
576 | equivalent to seeing no -g option at all. */ | |
577 | static int mips_debug = 0; | |
578 | ||
7d8e00cf RS |
579 | /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */ |
580 | #define MAX_VR4130_NOPS 4 | |
581 | ||
582 | /* The maximum number of NOPs needed to fill delay slots. */ | |
583 | #define MAX_DELAY_NOPS 2 | |
584 | ||
585 | /* The maximum number of NOPs needed for any purpose. */ | |
586 | #define MAX_NOPS 4 | |
71400594 RS |
587 | |
588 | /* A list of previous instructions, with index 0 being the most recent. | |
589 | We need to look back MAX_NOPS instructions when filling delay slots | |
590 | or working around processor errata. We need to look back one | |
591 | instruction further if we're thinking about using history[0] to | |
592 | fill a branch delay slot. */ | |
593 | static struct mips_cl_insn history[1 + MAX_NOPS]; | |
252b5132 | 594 | |
1e915849 RS |
595 | /* Nop instructions used by emit_nop. */ |
596 | static struct mips_cl_insn nop_insn, mips16_nop_insn; | |
597 | ||
598 | /* The appropriate nop for the current mode. */ | |
599 | #define NOP_INSN (mips_opts.mips16 ? &mips16_nop_insn : &nop_insn) | |
252b5132 | 600 | |
252b5132 RH |
601 | /* If this is set, it points to a frag holding nop instructions which |
602 | were inserted before the start of a noreorder section. If those | |
603 | nops turn out to be unnecessary, the size of the frag can be | |
604 | decreased. */ | |
605 | static fragS *prev_nop_frag; | |
606 | ||
607 | /* The number of nop instructions we created in prev_nop_frag. */ | |
608 | static int prev_nop_frag_holds; | |
609 | ||
610 | /* The number of nop instructions that we know we need in | |
bdaaa2e1 | 611 | prev_nop_frag. */ |
252b5132 RH |
612 | static int prev_nop_frag_required; |
613 | ||
614 | /* The number of instructions we've seen since prev_nop_frag. */ | |
615 | static int prev_nop_frag_since; | |
616 | ||
617 | /* For ECOFF and ELF, relocations against symbols are done in two | |
618 | parts, with a HI relocation and a LO relocation. Each relocation | |
619 | has only 16 bits of space to store an addend. This means that in | |
620 | order for the linker to handle carries correctly, it must be able | |
621 | to locate both the HI and the LO relocation. This means that the | |
622 | relocations must appear in order in the relocation table. | |
623 | ||
624 | In order to implement this, we keep track of each unmatched HI | |
625 | relocation. We then sort them so that they immediately precede the | |
bdaaa2e1 | 626 | corresponding LO relocation. */ |
252b5132 | 627 | |
e972090a NC |
628 | struct mips_hi_fixup |
629 | { | |
252b5132 RH |
630 | /* Next HI fixup. */ |
631 | struct mips_hi_fixup *next; | |
632 | /* This fixup. */ | |
633 | fixS *fixp; | |
634 | /* The section this fixup is in. */ | |
635 | segT seg; | |
636 | }; | |
637 | ||
638 | /* The list of unmatched HI relocs. */ | |
639 | ||
640 | static struct mips_hi_fixup *mips_hi_fixup_list; | |
641 | ||
64bdfcaf RS |
642 | /* The frag containing the last explicit relocation operator. |
643 | Null if explicit relocations have not been used. */ | |
644 | ||
645 | static fragS *prev_reloc_op_frag; | |
646 | ||
252b5132 RH |
647 | /* Map normal MIPS register numbers to mips16 register numbers. */ |
648 | ||
649 | #define X ILLEGAL_REG | |
e972090a NC |
650 | static const int mips32_to_16_reg_map[] = |
651 | { | |
252b5132 RH |
652 | X, X, 2, 3, 4, 5, 6, 7, |
653 | X, X, X, X, X, X, X, X, | |
654 | 0, 1, X, X, X, X, X, X, | |
655 | X, X, X, X, X, X, X, X | |
656 | }; | |
657 | #undef X | |
658 | ||
659 | /* Map mips16 register numbers to normal MIPS register numbers. */ | |
660 | ||
e972090a NC |
661 | static const unsigned int mips16_to_32_reg_map[] = |
662 | { | |
252b5132 RH |
663 | 16, 17, 2, 3, 4, 5, 6, 7 |
664 | }; | |
60b63b72 | 665 | |
71400594 RS |
666 | /* Classifies the kind of instructions we're interested in when |
667 | implementing -mfix-vr4120. */ | |
668 | enum fix_vr4120_class { | |
669 | FIX_VR4120_MACC, | |
670 | FIX_VR4120_DMACC, | |
671 | FIX_VR4120_MULT, | |
672 | FIX_VR4120_DMULT, | |
673 | FIX_VR4120_DIV, | |
674 | FIX_VR4120_MTHILO, | |
675 | NUM_FIX_VR4120_CLASSES | |
676 | }; | |
677 | ||
678 | /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if | |
679 | there must be at least one other instruction between an instruction | |
680 | of type X and an instruction of type Y. */ | |
681 | static unsigned int vr4120_conflicts[NUM_FIX_VR4120_CLASSES]; | |
682 | ||
683 | /* True if -mfix-vr4120 is in force. */ | |
d766e8ec | 684 | static int mips_fix_vr4120; |
4a6a3df4 | 685 | |
7d8e00cf RS |
686 | /* ...likewise -mfix-vr4130. */ |
687 | static int mips_fix_vr4130; | |
688 | ||
4a6a3df4 AO |
689 | /* We don't relax branches by default, since this causes us to expand |
690 | `la .l2 - .l1' if there's a branch between .l1 and .l2, because we | |
691 | fail to compute the offset before expanding the macro to the most | |
692 | efficient expansion. */ | |
693 | ||
694 | static int mips_relax_branch; | |
252b5132 | 695 | \f |
4d7206a2 RS |
696 | /* The expansion of many macros depends on the type of symbol that |
697 | they refer to. For example, when generating position-dependent code, | |
698 | a macro that refers to a symbol may have two different expansions, | |
699 | one which uses GP-relative addresses and one which uses absolute | |
700 | addresses. When generating SVR4-style PIC, a macro may have | |
701 | different expansions for local and global symbols. | |
702 | ||
703 | We handle these situations by generating both sequences and putting | |
704 | them in variant frags. In position-dependent code, the first sequence | |
705 | will be the GP-relative one and the second sequence will be the | |
706 | absolute one. In SVR4 PIC, the first sequence will be for global | |
707 | symbols and the second will be for local symbols. | |
708 | ||
584892a6 RS |
709 | The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and |
710 | SECOND are the lengths of the two sequences in bytes. These fields | |
711 | can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition, | |
712 | the subtype has the following flags: | |
4d7206a2 | 713 | |
584892a6 RS |
714 | RELAX_USE_SECOND |
715 | Set if it has been decided that we should use the second | |
716 | sequence instead of the first. | |
717 | ||
718 | RELAX_SECOND_LONGER | |
719 | Set in the first variant frag if the macro's second implementation | |
720 | is longer than its first. This refers to the macro as a whole, | |
721 | not an individual relaxation. | |
722 | ||
723 | RELAX_NOMACRO | |
724 | Set in the first variant frag if the macro appeared in a .set nomacro | |
725 | block and if one alternative requires a warning but the other does not. | |
726 | ||
727 | RELAX_DELAY_SLOT | |
728 | Like RELAX_NOMACRO, but indicates that the macro appears in a branch | |
729 | delay slot. | |
4d7206a2 RS |
730 | |
731 | The frag's "opcode" points to the first fixup for relaxable code. | |
732 | ||
733 | Relaxable macros are generated using a sequence such as: | |
734 | ||
735 | relax_start (SYMBOL); | |
736 | ... generate first expansion ... | |
737 | relax_switch (); | |
738 | ... generate second expansion ... | |
739 | relax_end (); | |
740 | ||
741 | The code and fixups for the unwanted alternative are discarded | |
742 | by md_convert_frag. */ | |
584892a6 | 743 | #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND)) |
4d7206a2 | 744 | |
584892a6 RS |
745 | #define RELAX_FIRST(X) (((X) >> 8) & 0xff) |
746 | #define RELAX_SECOND(X) ((X) & 0xff) | |
747 | #define RELAX_USE_SECOND 0x10000 | |
748 | #define RELAX_SECOND_LONGER 0x20000 | |
749 | #define RELAX_NOMACRO 0x40000 | |
750 | #define RELAX_DELAY_SLOT 0x80000 | |
252b5132 | 751 | |
4a6a3df4 AO |
752 | /* Branch without likely bit. If label is out of range, we turn: |
753 | ||
754 | beq reg1, reg2, label | |
755 | delay slot | |
756 | ||
757 | into | |
758 | ||
759 | bne reg1, reg2, 0f | |
760 | nop | |
761 | j label | |
762 | 0: delay slot | |
763 | ||
764 | with the following opcode replacements: | |
765 | ||
766 | beq <-> bne | |
767 | blez <-> bgtz | |
768 | bltz <-> bgez | |
769 | bc1f <-> bc1t | |
770 | ||
771 | bltzal <-> bgezal (with jal label instead of j label) | |
772 | ||
773 | Even though keeping the delay slot instruction in the delay slot of | |
774 | the branch would be more efficient, it would be very tricky to do | |
775 | correctly, because we'd have to introduce a variable frag *after* | |
776 | the delay slot instruction, and expand that instead. Let's do it | |
777 | the easy way for now, even if the branch-not-taken case now costs | |
778 | one additional instruction. Out-of-range branches are not supposed | |
779 | to be common, anyway. | |
780 | ||
781 | Branch likely. If label is out of range, we turn: | |
782 | ||
783 | beql reg1, reg2, label | |
784 | delay slot (annulled if branch not taken) | |
785 | ||
786 | into | |
787 | ||
788 | beql reg1, reg2, 1f | |
789 | nop | |
790 | beql $0, $0, 2f | |
791 | nop | |
792 | 1: j[al] label | |
793 | delay slot (executed only if branch taken) | |
794 | 2: | |
795 | ||
796 | It would be possible to generate a shorter sequence by losing the | |
797 | likely bit, generating something like: | |
b34976b6 | 798 | |
4a6a3df4 AO |
799 | bne reg1, reg2, 0f |
800 | nop | |
801 | j[al] label | |
802 | delay slot (executed only if branch taken) | |
803 | 0: | |
804 | ||
805 | beql -> bne | |
806 | bnel -> beq | |
807 | blezl -> bgtz | |
808 | bgtzl -> blez | |
809 | bltzl -> bgez | |
810 | bgezl -> bltz | |
811 | bc1fl -> bc1t | |
812 | bc1tl -> bc1f | |
813 | ||
814 | bltzall -> bgezal (with jal label instead of j label) | |
815 | bgezall -> bltzal (ditto) | |
816 | ||
817 | ||
818 | but it's not clear that it would actually improve performance. */ | |
af6ae2ad | 819 | #define RELAX_BRANCH_ENCODE(uncond, likely, link, toofar) \ |
4a6a3df4 AO |
820 | ((relax_substateT) \ |
821 | (0xc0000000 \ | |
822 | | ((toofar) ? 1 : 0) \ | |
823 | | ((link) ? 2 : 0) \ | |
824 | | ((likely) ? 4 : 0) \ | |
af6ae2ad | 825 | | ((uncond) ? 8 : 0))) |
4a6a3df4 | 826 | #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000) |
4a6a3df4 AO |
827 | #define RELAX_BRANCH_UNCOND(i) (((i) & 8) != 0) |
828 | #define RELAX_BRANCH_LIKELY(i) (((i) & 4) != 0) | |
829 | #define RELAX_BRANCH_LINK(i) (((i) & 2) != 0) | |
ae6063d4 | 830 | #define RELAX_BRANCH_TOOFAR(i) (((i) & 1) != 0) |
4a6a3df4 | 831 | |
252b5132 RH |
832 | /* For mips16 code, we use an entirely different form of relaxation. |
833 | mips16 supports two versions of most instructions which take | |
834 | immediate values: a small one which takes some small value, and a | |
835 | larger one which takes a 16 bit value. Since branches also follow | |
836 | this pattern, relaxing these values is required. | |
837 | ||
838 | We can assemble both mips16 and normal MIPS code in a single | |
839 | object. Therefore, we need to support this type of relaxation at | |
840 | the same time that we support the relaxation described above. We | |
841 | use the high bit of the subtype field to distinguish these cases. | |
842 | ||
843 | The information we store for this type of relaxation is the | |
844 | argument code found in the opcode file for this relocation, whether | |
845 | the user explicitly requested a small or extended form, and whether | |
846 | the relocation is in a jump or jal delay slot. That tells us the | |
847 | size of the value, and how it should be stored. We also store | |
848 | whether the fragment is considered to be extended or not. We also | |
849 | store whether this is known to be a branch to a different section, | |
850 | whether we have tried to relax this frag yet, and whether we have | |
851 | ever extended a PC relative fragment because of a shift count. */ | |
852 | #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \ | |
853 | (0x80000000 \ | |
854 | | ((type) & 0xff) \ | |
855 | | ((small) ? 0x100 : 0) \ | |
856 | | ((ext) ? 0x200 : 0) \ | |
857 | | ((dslot) ? 0x400 : 0) \ | |
858 | | ((jal_dslot) ? 0x800 : 0)) | |
4a6a3df4 | 859 | #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000) |
252b5132 RH |
860 | #define RELAX_MIPS16_TYPE(i) ((i) & 0xff) |
861 | #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0) | |
862 | #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0) | |
863 | #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0) | |
864 | #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0) | |
865 | #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0) | |
866 | #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000) | |
867 | #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000) | |
868 | #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0) | |
869 | #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000) | |
870 | #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000) | |
885add95 CD |
871 | |
872 | /* Is the given value a sign-extended 32-bit value? */ | |
873 | #define IS_SEXT_32BIT_NUM(x) \ | |
874 | (((x) &~ (offsetT) 0x7fffffff) == 0 \ | |
875 | || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff)) | |
876 | ||
877 | /* Is the given value a sign-extended 16-bit value? */ | |
878 | #define IS_SEXT_16BIT_NUM(x) \ | |
879 | (((x) &~ (offsetT) 0x7fff) == 0 \ | |
880 | || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff)) | |
881 | ||
2051e8c4 MR |
882 | /* Is the given value a zero-extended 32-bit value? Or a negated one? */ |
883 | #define IS_ZEXT_32BIT_NUM(x) \ | |
884 | (((x) &~ (offsetT) 0xffffffff) == 0 \ | |
885 | || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff)) | |
886 | ||
bf12938e RS |
887 | /* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in |
888 | VALUE << SHIFT. VALUE is evaluated exactly once. */ | |
889 | #define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \ | |
890 | (STRUCT) = (((STRUCT) & ~((MASK) << (SHIFT))) \ | |
891 | | (((VALUE) & (MASK)) << (SHIFT))) | |
892 | ||
893 | /* Extract bits MASK << SHIFT from STRUCT and shift them right | |
894 | SHIFT places. */ | |
895 | #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \ | |
896 | (((STRUCT) >> (SHIFT)) & (MASK)) | |
897 | ||
898 | /* Change INSN's opcode so that the operand given by FIELD has value VALUE. | |
899 | INSN is a mips_cl_insn structure and VALUE is evaluated exactly once. | |
900 | ||
901 | include/opcode/mips.h specifies operand fields using the macros | |
902 | OP_MASK_<FIELD> and OP_SH_<FIELD>. The MIPS16 equivalents start | |
903 | with "MIPS16OP" instead of "OP". */ | |
904 | #define INSERT_OPERAND(FIELD, INSN, VALUE) \ | |
905 | INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD) | |
906 | #define MIPS16_INSERT_OPERAND(FIELD, INSN, VALUE) \ | |
907 | INSERT_BITS ((INSN).insn_opcode, VALUE, \ | |
908 | MIPS16OP_MASK_##FIELD, MIPS16OP_SH_##FIELD) | |
909 | ||
910 | /* Extract the operand given by FIELD from mips_cl_insn INSN. */ | |
911 | #define EXTRACT_OPERAND(FIELD, INSN) \ | |
912 | EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) | |
913 | #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \ | |
914 | EXTRACT_BITS ((INSN).insn_opcode, \ | |
915 | MIPS16OP_MASK_##FIELD, \ | |
916 | MIPS16OP_SH_##FIELD) | |
4d7206a2 RS |
917 | \f |
918 | /* Global variables used when generating relaxable macros. See the | |
919 | comment above RELAX_ENCODE for more details about how relaxation | |
920 | is used. */ | |
921 | static struct { | |
922 | /* 0 if we're not emitting a relaxable macro. | |
923 | 1 if we're emitting the first of the two relaxation alternatives. | |
924 | 2 if we're emitting the second alternative. */ | |
925 | int sequence; | |
926 | ||
927 | /* The first relaxable fixup in the current frag. (In other words, | |
928 | the first fixup that refers to relaxable code.) */ | |
929 | fixS *first_fixup; | |
930 | ||
931 | /* sizes[0] says how many bytes of the first alternative are stored in | |
932 | the current frag. Likewise sizes[1] for the second alternative. */ | |
933 | unsigned int sizes[2]; | |
934 | ||
935 | /* The symbol on which the choice of sequence depends. */ | |
936 | symbolS *symbol; | |
937 | } mips_relax; | |
252b5132 | 938 | \f |
584892a6 RS |
939 | /* Global variables used to decide whether a macro needs a warning. */ |
940 | static struct { | |
941 | /* True if the macro is in a branch delay slot. */ | |
942 | bfd_boolean delay_slot_p; | |
943 | ||
944 | /* For relaxable macros, sizes[0] is the length of the first alternative | |
945 | in bytes and sizes[1] is the length of the second alternative. | |
946 | For non-relaxable macros, both elements give the length of the | |
947 | macro in bytes. */ | |
948 | unsigned int sizes[2]; | |
949 | ||
950 | /* The first variant frag for this macro. */ | |
951 | fragS *first_frag; | |
952 | } mips_macro_warning; | |
953 | \f | |
252b5132 RH |
954 | /* Prototypes for static functions. */ |
955 | ||
17a2f251 | 956 | #define internalError() \ |
252b5132 | 957 | as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__) |
252b5132 RH |
958 | |
959 | enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG }; | |
960 | ||
b34976b6 | 961 | static void append_insn |
4d7206a2 | 962 | (struct mips_cl_insn *ip, expressionS *p, bfd_reloc_code_real_type *r); |
7d10b47d | 963 | static void mips_no_prev_insn (void); |
b34976b6 | 964 | static void mips16_macro_build |
67c0d1eb RS |
965 | (expressionS *, const char *, const char *, va_list); |
966 | static void load_register (int, expressionS *, int); | |
584892a6 RS |
967 | static void macro_start (void); |
968 | static void macro_end (void); | |
17a2f251 TS |
969 | static void macro (struct mips_cl_insn * ip); |
970 | static void mips16_macro (struct mips_cl_insn * ip); | |
252b5132 | 971 | #ifdef LOSING_COMPILER |
17a2f251 | 972 | static void macro2 (struct mips_cl_insn * ip); |
252b5132 | 973 | #endif |
17a2f251 TS |
974 | static void mips_ip (char *str, struct mips_cl_insn * ip); |
975 | static void mips16_ip (char *str, struct mips_cl_insn * ip); | |
b34976b6 | 976 | static void mips16_immed |
17a2f251 TS |
977 | (char *, unsigned int, int, offsetT, bfd_boolean, bfd_boolean, bfd_boolean, |
978 | unsigned long *, bfd_boolean *, unsigned short *); | |
5e0116d5 | 979 | static size_t my_getSmallExpression |
17a2f251 TS |
980 | (expressionS *, bfd_reloc_code_real_type *, char *); |
981 | static void my_getExpression (expressionS *, char *); | |
982 | static void s_align (int); | |
983 | static void s_change_sec (int); | |
984 | static void s_change_section (int); | |
985 | static void s_cons (int); | |
986 | static void s_float_cons (int); | |
987 | static void s_mips_globl (int); | |
988 | static void s_option (int); | |
989 | static void s_mipsset (int); | |
990 | static void s_abicalls (int); | |
991 | static void s_cpload (int); | |
992 | static void s_cpsetup (int); | |
993 | static void s_cplocal (int); | |
994 | static void s_cprestore (int); | |
995 | static void s_cpreturn (int); | |
996 | static void s_gpvalue (int); | |
997 | static void s_gpword (int); | |
998 | static void s_gpdword (int); | |
999 | static void s_cpadd (int); | |
1000 | static void s_insn (int); | |
1001 | static void md_obj_begin (void); | |
1002 | static void md_obj_end (void); | |
1003 | static void s_mips_ent (int); | |
1004 | static void s_mips_end (int); | |
1005 | static void s_mips_frame (int); | |
1006 | static void s_mips_mask (int reg_type); | |
1007 | static void s_mips_stab (int); | |
1008 | static void s_mips_weakext (int); | |
1009 | static void s_mips_file (int); | |
1010 | static void s_mips_loc (int); | |
1011 | static bfd_boolean pic_need_relax (symbolS *, asection *); | |
4a6a3df4 | 1012 | static int relaxed_branch_length (fragS *, asection *, int); |
17a2f251 | 1013 | static int validate_mips_insn (const struct mips_opcode *); |
e7af610e NC |
1014 | |
1015 | /* Table and functions used to map between CPU/ISA names, and | |
1016 | ISA levels, and CPU numbers. */ | |
1017 | ||
e972090a NC |
1018 | struct mips_cpu_info |
1019 | { | |
e7af610e NC |
1020 | const char *name; /* CPU or ISA name. */ |
1021 | int is_isa; /* Is this an ISA? (If 0, a CPU.) */ | |
1022 | int isa; /* ISA level. */ | |
1023 | int cpu; /* CPU number (default CPU if ISA). */ | |
1024 | }; | |
1025 | ||
17a2f251 TS |
1026 | static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *); |
1027 | static const struct mips_cpu_info *mips_cpu_info_from_isa (int); | |
1028 | static const struct mips_cpu_info *mips_cpu_info_from_arch (int); | |
252b5132 RH |
1029 | \f |
1030 | /* Pseudo-op table. | |
1031 | ||
1032 | The following pseudo-ops from the Kane and Heinrich MIPS book | |
1033 | should be defined here, but are currently unsupported: .alias, | |
1034 | .galive, .gjaldef, .gjrlive, .livereg, .noalias. | |
1035 | ||
1036 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
1037 | specific to the type of debugging information being generated, and | |
1038 | should be defined by the object format: .aent, .begin, .bend, | |
1039 | .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp, | |
1040 | .vreg. | |
1041 | ||
1042 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
1043 | not MIPS CPU specific, but are also not specific to the object file | |
1044 | format. This file is probably the best place to define them, but | |
1045 | they are not currently supported: .asm0, .endr, .lab, .repeat, | |
1046 | .struct. */ | |
1047 | ||
e972090a NC |
1048 | static const pseudo_typeS mips_pseudo_table[] = |
1049 | { | |
beae10d5 | 1050 | /* MIPS specific pseudo-ops. */ |
252b5132 RH |
1051 | {"option", s_option, 0}, |
1052 | {"set", s_mipsset, 0}, | |
1053 | {"rdata", s_change_sec, 'r'}, | |
1054 | {"sdata", s_change_sec, 's'}, | |
1055 | {"livereg", s_ignore, 0}, | |
1056 | {"abicalls", s_abicalls, 0}, | |
1057 | {"cpload", s_cpload, 0}, | |
6478892d TS |
1058 | {"cpsetup", s_cpsetup, 0}, |
1059 | {"cplocal", s_cplocal, 0}, | |
252b5132 | 1060 | {"cprestore", s_cprestore, 0}, |
6478892d TS |
1061 | {"cpreturn", s_cpreturn, 0}, |
1062 | {"gpvalue", s_gpvalue, 0}, | |
252b5132 | 1063 | {"gpword", s_gpword, 0}, |
10181a0d | 1064 | {"gpdword", s_gpdword, 0}, |
252b5132 RH |
1065 | {"cpadd", s_cpadd, 0}, |
1066 | {"insn", s_insn, 0}, | |
1067 | ||
beae10d5 | 1068 | /* Relatively generic pseudo-ops that happen to be used on MIPS |
252b5132 RH |
1069 | chips. */ |
1070 | {"asciiz", stringer, 1}, | |
1071 | {"bss", s_change_sec, 'b'}, | |
1072 | {"err", s_err, 0}, | |
1073 | {"half", s_cons, 1}, | |
1074 | {"dword", s_cons, 3}, | |
1075 | {"weakext", s_mips_weakext, 0}, | |
1076 | ||
beae10d5 | 1077 | /* These pseudo-ops are defined in read.c, but must be overridden |
252b5132 RH |
1078 | here for one reason or another. */ |
1079 | {"align", s_align, 0}, | |
1080 | {"byte", s_cons, 0}, | |
1081 | {"data", s_change_sec, 'd'}, | |
1082 | {"double", s_float_cons, 'd'}, | |
1083 | {"float", s_float_cons, 'f'}, | |
1084 | {"globl", s_mips_globl, 0}, | |
1085 | {"global", s_mips_globl, 0}, | |
1086 | {"hword", s_cons, 1}, | |
1087 | {"int", s_cons, 2}, | |
1088 | {"long", s_cons, 2}, | |
1089 | {"octa", s_cons, 4}, | |
1090 | {"quad", s_cons, 3}, | |
cca86cc8 | 1091 | {"section", s_change_section, 0}, |
252b5132 RH |
1092 | {"short", s_cons, 1}, |
1093 | {"single", s_float_cons, 'f'}, | |
1094 | {"stabn", s_mips_stab, 'n'}, | |
1095 | {"text", s_change_sec, 't'}, | |
1096 | {"word", s_cons, 2}, | |
add56521 | 1097 | |
add56521 | 1098 | { "extern", ecoff_directive_extern, 0}, |
add56521 | 1099 | |
43841e91 | 1100 | { NULL, NULL, 0 }, |
252b5132 RH |
1101 | }; |
1102 | ||
e972090a NC |
1103 | static const pseudo_typeS mips_nonecoff_pseudo_table[] = |
1104 | { | |
beae10d5 KH |
1105 | /* These pseudo-ops should be defined by the object file format. |
1106 | However, a.out doesn't support them, so we have versions here. */ | |
252b5132 RH |
1107 | {"aent", s_mips_ent, 1}, |
1108 | {"bgnb", s_ignore, 0}, | |
1109 | {"end", s_mips_end, 0}, | |
1110 | {"endb", s_ignore, 0}, | |
1111 | {"ent", s_mips_ent, 0}, | |
c5dd6aab | 1112 | {"file", s_mips_file, 0}, |
252b5132 RH |
1113 | {"fmask", s_mips_mask, 'F'}, |
1114 | {"frame", s_mips_frame, 0}, | |
c5dd6aab | 1115 | {"loc", s_mips_loc, 0}, |
252b5132 RH |
1116 | {"mask", s_mips_mask, 'R'}, |
1117 | {"verstamp", s_ignore, 0}, | |
43841e91 | 1118 | { NULL, NULL, 0 }, |
252b5132 RH |
1119 | }; |
1120 | ||
17a2f251 | 1121 | extern void pop_insert (const pseudo_typeS *); |
252b5132 RH |
1122 | |
1123 | void | |
17a2f251 | 1124 | mips_pop_insert (void) |
252b5132 RH |
1125 | { |
1126 | pop_insert (mips_pseudo_table); | |
1127 | if (! ECOFF_DEBUGGING) | |
1128 | pop_insert (mips_nonecoff_pseudo_table); | |
1129 | } | |
1130 | \f | |
1131 | /* Symbols labelling the current insn. */ | |
1132 | ||
e972090a NC |
1133 | struct insn_label_list |
1134 | { | |
252b5132 RH |
1135 | struct insn_label_list *next; |
1136 | symbolS *label; | |
1137 | }; | |
1138 | ||
1139 | static struct insn_label_list *insn_labels; | |
1140 | static struct insn_label_list *free_insn_labels; | |
1141 | ||
17a2f251 | 1142 | static void mips_clear_insn_labels (void); |
252b5132 RH |
1143 | |
1144 | static inline void | |
17a2f251 | 1145 | mips_clear_insn_labels (void) |
252b5132 RH |
1146 | { |
1147 | register struct insn_label_list **pl; | |
1148 | ||
1149 | for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next) | |
1150 | ; | |
1151 | *pl = insn_labels; | |
1152 | insn_labels = NULL; | |
1153 | } | |
1154 | \f | |
1155 | static char *expr_end; | |
1156 | ||
1157 | /* Expressions which appear in instructions. These are set by | |
1158 | mips_ip. */ | |
1159 | ||
1160 | static expressionS imm_expr; | |
5f74bc13 | 1161 | static expressionS imm2_expr; |
252b5132 RH |
1162 | static expressionS offset_expr; |
1163 | ||
1164 | /* Relocs associated with imm_expr and offset_expr. */ | |
1165 | ||
f6688943 TS |
1166 | static bfd_reloc_code_real_type imm_reloc[3] |
1167 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
1168 | static bfd_reloc_code_real_type offset_reloc[3] | |
1169 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 1170 | |
252b5132 RH |
1171 | /* These are set by mips16_ip if an explicit extension is used. */ |
1172 | ||
b34976b6 | 1173 | static bfd_boolean mips16_small, mips16_ext; |
252b5132 | 1174 | |
7ed4a06a | 1175 | #ifdef OBJ_ELF |
ecb4347a DJ |
1176 | /* The pdr segment for per procedure frame/regmask info. Not used for |
1177 | ECOFF debugging. */ | |
252b5132 RH |
1178 | |
1179 | static segT pdr_seg; | |
7ed4a06a | 1180 | #endif |
252b5132 | 1181 | |
e013f690 TS |
1182 | /* The default target format to use. */ |
1183 | ||
1184 | const char * | |
17a2f251 | 1185 | mips_target_format (void) |
e013f690 TS |
1186 | { |
1187 | switch (OUTPUT_FLAVOR) | |
1188 | { | |
e013f690 TS |
1189 | case bfd_target_ecoff_flavour: |
1190 | return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT; | |
1191 | case bfd_target_coff_flavour: | |
1192 | return "pe-mips"; | |
1193 | case bfd_target_elf_flavour: | |
1194 | #ifdef TE_TMIPS | |
cfe86eaa | 1195 | /* This is traditional mips. */ |
e013f690 | 1196 | return (target_big_endian |
cfe86eaa TS |
1197 | ? (HAVE_64BIT_OBJECTS |
1198 | ? "elf64-tradbigmips" | |
1199 | : (HAVE_NEWABI | |
1200 | ? "elf32-ntradbigmips" : "elf32-tradbigmips")) | |
1201 | : (HAVE_64BIT_OBJECTS | |
1202 | ? "elf64-tradlittlemips" | |
1203 | : (HAVE_NEWABI | |
1204 | ? "elf32-ntradlittlemips" : "elf32-tradlittlemips"))); | |
e013f690 TS |
1205 | #else |
1206 | return (target_big_endian | |
cfe86eaa TS |
1207 | ? (HAVE_64BIT_OBJECTS |
1208 | ? "elf64-bigmips" | |
1209 | : (HAVE_NEWABI | |
1210 | ? "elf32-nbigmips" : "elf32-bigmips")) | |
1211 | : (HAVE_64BIT_OBJECTS | |
1212 | ? "elf64-littlemips" | |
1213 | : (HAVE_NEWABI | |
1214 | ? "elf32-nlittlemips" : "elf32-littlemips"))); | |
e013f690 TS |
1215 | #endif |
1216 | default: | |
1217 | abort (); | |
1218 | return NULL; | |
1219 | } | |
1220 | } | |
1221 | ||
1e915849 RS |
1222 | /* Return the length of instruction INSN. */ |
1223 | ||
1224 | static inline unsigned int | |
1225 | insn_length (const struct mips_cl_insn *insn) | |
1226 | { | |
1227 | if (!mips_opts.mips16) | |
1228 | return 4; | |
1229 | return insn->mips16_absolute_jump_p || insn->use_extend ? 4 : 2; | |
1230 | } | |
1231 | ||
1232 | /* Initialise INSN from opcode entry MO. Leave its position unspecified. */ | |
1233 | ||
1234 | static void | |
1235 | create_insn (struct mips_cl_insn *insn, const struct mips_opcode *mo) | |
1236 | { | |
1237 | size_t i; | |
1238 | ||
1239 | insn->insn_mo = mo; | |
1240 | insn->use_extend = FALSE; | |
1241 | insn->extend = 0; | |
1242 | insn->insn_opcode = mo->match; | |
1243 | insn->frag = NULL; | |
1244 | insn->where = 0; | |
1245 | for (i = 0; i < ARRAY_SIZE (insn->fixp); i++) | |
1246 | insn->fixp[i] = NULL; | |
1247 | insn->fixed_p = (mips_opts.noreorder > 0); | |
1248 | insn->noreorder_p = (mips_opts.noreorder > 0); | |
1249 | insn->mips16_absolute_jump_p = 0; | |
1250 | } | |
1251 | ||
1252 | /* Install INSN at the location specified by its "frag" and "where" fields. */ | |
1253 | ||
1254 | static void | |
1255 | install_insn (const struct mips_cl_insn *insn) | |
1256 | { | |
1257 | char *f = insn->frag->fr_literal + insn->where; | |
1258 | if (!mips_opts.mips16) | |
1259 | md_number_to_chars (f, insn->insn_opcode, 4); | |
1260 | else if (insn->mips16_absolute_jump_p) | |
1261 | { | |
1262 | md_number_to_chars (f, insn->insn_opcode >> 16, 2); | |
1263 | md_number_to_chars (f + 2, insn->insn_opcode & 0xffff, 2); | |
1264 | } | |
1265 | else | |
1266 | { | |
1267 | if (insn->use_extend) | |
1268 | { | |
1269 | md_number_to_chars (f, 0xf000 | insn->extend, 2); | |
1270 | f += 2; | |
1271 | } | |
1272 | md_number_to_chars (f, insn->insn_opcode, 2); | |
1273 | } | |
1274 | } | |
1275 | ||
1276 | /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly | |
1277 | and install the opcode in the new location. */ | |
1278 | ||
1279 | static void | |
1280 | move_insn (struct mips_cl_insn *insn, fragS *frag, long where) | |
1281 | { | |
1282 | size_t i; | |
1283 | ||
1284 | insn->frag = frag; | |
1285 | insn->where = where; | |
1286 | for (i = 0; i < ARRAY_SIZE (insn->fixp); i++) | |
1287 | if (insn->fixp[i] != NULL) | |
1288 | { | |
1289 | insn->fixp[i]->fx_frag = frag; | |
1290 | insn->fixp[i]->fx_where = where; | |
1291 | } | |
1292 | install_insn (insn); | |
1293 | } | |
1294 | ||
1295 | /* Add INSN to the end of the output. */ | |
1296 | ||
1297 | static void | |
1298 | add_fixed_insn (struct mips_cl_insn *insn) | |
1299 | { | |
1300 | char *f = frag_more (insn_length (insn)); | |
1301 | move_insn (insn, frag_now, f - frag_now->fr_literal); | |
1302 | } | |
1303 | ||
1304 | /* Start a variant frag and move INSN to the start of the variant part, | |
1305 | marking it as fixed. The other arguments are as for frag_var. */ | |
1306 | ||
1307 | static void | |
1308 | add_relaxed_insn (struct mips_cl_insn *insn, int max_chars, int var, | |
1309 | relax_substateT subtype, symbolS *symbol, offsetT offset) | |
1310 | { | |
1311 | frag_grow (max_chars); | |
1312 | move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal); | |
1313 | insn->fixed_p = 1; | |
1314 | frag_var (rs_machine_dependent, max_chars, var, | |
1315 | subtype, symbol, offset, NULL); | |
1316 | } | |
1317 | ||
1318 | /* Insert N copies of INSN into the history buffer, starting at | |
1319 | position FIRST. Neither FIRST nor N need to be clipped. */ | |
1320 | ||
1321 | static void | |
1322 | insert_into_history (unsigned int first, unsigned int n, | |
1323 | const struct mips_cl_insn *insn) | |
1324 | { | |
1325 | if (mips_relax.sequence != 2) | |
1326 | { | |
1327 | unsigned int i; | |
1328 | ||
1329 | for (i = ARRAY_SIZE (history); i-- > first;) | |
1330 | if (i >= first + n) | |
1331 | history[i] = history[i - n]; | |
1332 | else | |
1333 | history[i] = *insn; | |
1334 | } | |
1335 | } | |
1336 | ||
1337 | /* Emit a nop instruction, recording it in the history buffer. */ | |
1338 | ||
1339 | static void | |
1340 | emit_nop (void) | |
1341 | { | |
1342 | add_fixed_insn (NOP_INSN); | |
1343 | insert_into_history (0, 1, NOP_INSN); | |
1344 | } | |
1345 | ||
71400594 RS |
1346 | /* Initialize vr4120_conflicts. There is a bit of duplication here: |
1347 | the idea is to make it obvious at a glance that each errata is | |
1348 | included. */ | |
1349 | ||
1350 | static void | |
1351 | init_vr4120_conflicts (void) | |
1352 | { | |
1353 | #define CONFLICT(FIRST, SECOND) \ | |
1354 | vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND | |
1355 | ||
1356 | /* Errata 21 - [D]DIV[U] after [D]MACC */ | |
1357 | CONFLICT (MACC, DIV); | |
1358 | CONFLICT (DMACC, DIV); | |
1359 | ||
1360 | /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */ | |
1361 | CONFLICT (DMULT, DMULT); | |
1362 | CONFLICT (DMULT, DMACC); | |
1363 | CONFLICT (DMACC, DMULT); | |
1364 | CONFLICT (DMACC, DMACC); | |
1365 | ||
1366 | /* Errata 24 - MT{LO,HI} after [D]MACC */ | |
1367 | CONFLICT (MACC, MTHILO); | |
1368 | CONFLICT (DMACC, MTHILO); | |
1369 | ||
1370 | /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU | |
1371 | instruction is executed immediately after a MACC or DMACC | |
1372 | instruction, the result of [either instruction] is incorrect." */ | |
1373 | CONFLICT (MACC, MULT); | |
1374 | CONFLICT (MACC, DMULT); | |
1375 | CONFLICT (DMACC, MULT); | |
1376 | CONFLICT (DMACC, DMULT); | |
1377 | ||
1378 | /* VR4181A errata MD(4): "If a MACC or DMACC instruction is | |
1379 | executed immediately after a DMULT, DMULTU, DIV, DIVU, | |
1380 | DDIV or DDIVU instruction, the result of the MACC or | |
1381 | DMACC instruction is incorrect.". */ | |
1382 | CONFLICT (DMULT, MACC); | |
1383 | CONFLICT (DMULT, DMACC); | |
1384 | CONFLICT (DIV, MACC); | |
1385 | CONFLICT (DIV, DMACC); | |
1386 | ||
1387 | #undef CONFLICT | |
1388 | } | |
1389 | ||
156c2f8b NC |
1390 | /* This function is called once, at assembler startup time. It should |
1391 | set up all the tables, etc. that the MD part of the assembler will need. */ | |
1392 | ||
252b5132 | 1393 | void |
17a2f251 | 1394 | md_begin (void) |
252b5132 | 1395 | { |
252b5132 | 1396 | register const char *retval = NULL; |
156c2f8b | 1397 | int i = 0; |
252b5132 | 1398 | int broken = 0; |
1f25f5d3 | 1399 | |
fef14a42 | 1400 | if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_arch)) |
252b5132 RH |
1401 | as_warn (_("Could not set architecture and machine")); |
1402 | ||
252b5132 RH |
1403 | op_hash = hash_new (); |
1404 | ||
1405 | for (i = 0; i < NUMOPCODES;) | |
1406 | { | |
1407 | const char *name = mips_opcodes[i].name; | |
1408 | ||
17a2f251 | 1409 | retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]); |
252b5132 RH |
1410 | if (retval != NULL) |
1411 | { | |
1412 | fprintf (stderr, _("internal error: can't hash `%s': %s\n"), | |
1413 | mips_opcodes[i].name, retval); | |
1414 | /* Probably a memory allocation problem? Give up now. */ | |
1415 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
1416 | } | |
1417 | do | |
1418 | { | |
1419 | if (mips_opcodes[i].pinfo != INSN_MACRO) | |
1420 | { | |
1421 | if (!validate_mips_insn (&mips_opcodes[i])) | |
1422 | broken = 1; | |
1e915849 RS |
1423 | if (nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0) |
1424 | { | |
1425 | create_insn (&nop_insn, mips_opcodes + i); | |
1426 | nop_insn.fixed_p = 1; | |
1427 | } | |
252b5132 RH |
1428 | } |
1429 | ++i; | |
1430 | } | |
1431 | while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name)); | |
1432 | } | |
1433 | ||
1434 | mips16_op_hash = hash_new (); | |
1435 | ||
1436 | i = 0; | |
1437 | while (i < bfd_mips16_num_opcodes) | |
1438 | { | |
1439 | const char *name = mips16_opcodes[i].name; | |
1440 | ||
17a2f251 | 1441 | retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]); |
252b5132 RH |
1442 | if (retval != NULL) |
1443 | as_fatal (_("internal: can't hash `%s': %s"), | |
1444 | mips16_opcodes[i].name, retval); | |
1445 | do | |
1446 | { | |
1447 | if (mips16_opcodes[i].pinfo != INSN_MACRO | |
1448 | && ((mips16_opcodes[i].match & mips16_opcodes[i].mask) | |
1449 | != mips16_opcodes[i].match)) | |
1450 | { | |
1451 | fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"), | |
1452 | mips16_opcodes[i].name, mips16_opcodes[i].args); | |
1453 | broken = 1; | |
1454 | } | |
1e915849 RS |
1455 | if (mips16_nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0) |
1456 | { | |
1457 | create_insn (&mips16_nop_insn, mips16_opcodes + i); | |
1458 | mips16_nop_insn.fixed_p = 1; | |
1459 | } | |
252b5132 RH |
1460 | ++i; |
1461 | } | |
1462 | while (i < bfd_mips16_num_opcodes | |
1463 | && strcmp (mips16_opcodes[i].name, name) == 0); | |
1464 | } | |
1465 | ||
1466 | if (broken) | |
1467 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
1468 | ||
1469 | /* We add all the general register names to the symbol table. This | |
1470 | helps us detect invalid uses of them. */ | |
1471 | for (i = 0; i < 32; i++) | |
1472 | { | |
1473 | char buf[5]; | |
1474 | ||
1475 | sprintf (buf, "$%d", i); | |
1476 | symbol_table_insert (symbol_new (buf, reg_section, i, | |
1477 | &zero_address_frag)); | |
1478 | } | |
76db943d TS |
1479 | symbol_table_insert (symbol_new ("$ra", reg_section, RA, |
1480 | &zero_address_frag)); | |
252b5132 RH |
1481 | symbol_table_insert (symbol_new ("$fp", reg_section, FP, |
1482 | &zero_address_frag)); | |
1483 | symbol_table_insert (symbol_new ("$sp", reg_section, SP, | |
1484 | &zero_address_frag)); | |
1485 | symbol_table_insert (symbol_new ("$gp", reg_section, GP, | |
1486 | &zero_address_frag)); | |
1487 | symbol_table_insert (symbol_new ("$at", reg_section, AT, | |
1488 | &zero_address_frag)); | |
1489 | symbol_table_insert (symbol_new ("$kt0", reg_section, KT0, | |
1490 | &zero_address_frag)); | |
1491 | symbol_table_insert (symbol_new ("$kt1", reg_section, KT1, | |
1492 | &zero_address_frag)); | |
85b51719 TS |
1493 | symbol_table_insert (symbol_new ("$zero", reg_section, ZERO, |
1494 | &zero_address_frag)); | |
252b5132 RH |
1495 | symbol_table_insert (symbol_new ("$pc", reg_section, -1, |
1496 | &zero_address_frag)); | |
1497 | ||
6047c971 AO |
1498 | /* If we don't add these register names to the symbol table, they |
1499 | may end up being added as regular symbols by operand(), and then | |
1500 | make it to the object file as undefined in case they're not | |
1501 | regarded as local symbols. They're local in o32, since `$' is a | |
1502 | local symbol prefix, but not in n32 or n64. */ | |
1503 | for (i = 0; i < 8; i++) | |
1504 | { | |
1505 | char buf[6]; | |
1506 | ||
1507 | sprintf (buf, "$fcc%i", i); | |
1508 | symbol_table_insert (symbol_new (buf, reg_section, -1, | |
1509 | &zero_address_frag)); | |
1510 | } | |
1511 | ||
7d10b47d | 1512 | mips_no_prev_insn (); |
252b5132 RH |
1513 | |
1514 | mips_gprmask = 0; | |
1515 | mips_cprmask[0] = 0; | |
1516 | mips_cprmask[1] = 0; | |
1517 | mips_cprmask[2] = 0; | |
1518 | mips_cprmask[3] = 0; | |
1519 | ||
1520 | /* set the default alignment for the text section (2**2) */ | |
1521 | record_alignment (text_section, 2); | |
1522 | ||
4d0d148d | 1523 | bfd_set_gp_size (stdoutput, g_switch_value); |
252b5132 RH |
1524 | |
1525 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
1526 | { | |
1527 | /* On a native system, sections must be aligned to 16 byte | |
1528 | boundaries. When configured for an embedded ELF target, we | |
1529 | don't bother. */ | |
1530 | if (strcmp (TARGET_OS, "elf") != 0) | |
1531 | { | |
1532 | (void) bfd_set_section_alignment (stdoutput, text_section, 4); | |
1533 | (void) bfd_set_section_alignment (stdoutput, data_section, 4); | |
1534 | (void) bfd_set_section_alignment (stdoutput, bss_section, 4); | |
1535 | } | |
1536 | ||
1537 | /* Create a .reginfo section for register masks and a .mdebug | |
1538 | section for debugging information. */ | |
1539 | { | |
1540 | segT seg; | |
1541 | subsegT subseg; | |
1542 | flagword flags; | |
1543 | segT sec; | |
1544 | ||
1545 | seg = now_seg; | |
1546 | subseg = now_subseg; | |
1547 | ||
1548 | /* The ABI says this section should be loaded so that the | |
1549 | running program can access it. However, we don't load it | |
1550 | if we are configured for an embedded target */ | |
1551 | flags = SEC_READONLY | SEC_DATA; | |
1552 | if (strcmp (TARGET_OS, "elf") != 0) | |
1553 | flags |= SEC_ALLOC | SEC_LOAD; | |
1554 | ||
316f5878 | 1555 | if (mips_abi != N64_ABI) |
252b5132 RH |
1556 | { |
1557 | sec = subseg_new (".reginfo", (subsegT) 0); | |
1558 | ||
195325d2 TS |
1559 | bfd_set_section_flags (stdoutput, sec, flags); |
1560 | bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2); | |
bdaaa2e1 | 1561 | |
252b5132 RH |
1562 | #ifdef OBJ_ELF |
1563 | mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo)); | |
1564 | #endif | |
1565 | } | |
1566 | else | |
1567 | { | |
1568 | /* The 64-bit ABI uses a .MIPS.options section rather than | |
1569 | .reginfo section. */ | |
1570 | sec = subseg_new (".MIPS.options", (subsegT) 0); | |
195325d2 TS |
1571 | bfd_set_section_flags (stdoutput, sec, flags); |
1572 | bfd_set_section_alignment (stdoutput, sec, 3); | |
252b5132 RH |
1573 | |
1574 | #ifdef OBJ_ELF | |
1575 | /* Set up the option header. */ | |
1576 | { | |
1577 | Elf_Internal_Options opthdr; | |
1578 | char *f; | |
1579 | ||
1580 | opthdr.kind = ODK_REGINFO; | |
1581 | opthdr.size = (sizeof (Elf_External_Options) | |
1582 | + sizeof (Elf64_External_RegInfo)); | |
1583 | opthdr.section = 0; | |
1584 | opthdr.info = 0; | |
1585 | f = frag_more (sizeof (Elf_External_Options)); | |
1586 | bfd_mips_elf_swap_options_out (stdoutput, &opthdr, | |
1587 | (Elf_External_Options *) f); | |
1588 | ||
1589 | mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo)); | |
1590 | } | |
1591 | #endif | |
1592 | } | |
1593 | ||
1594 | if (ECOFF_DEBUGGING) | |
1595 | { | |
1596 | sec = subseg_new (".mdebug", (subsegT) 0); | |
1597 | (void) bfd_set_section_flags (stdoutput, sec, | |
1598 | SEC_HAS_CONTENTS | SEC_READONLY); | |
1599 | (void) bfd_set_section_alignment (stdoutput, sec, 2); | |
1600 | } | |
ecb4347a | 1601 | #ifdef OBJ_ELF |
dcd410fe | 1602 | else if (OUTPUT_FLAVOR == bfd_target_elf_flavour && mips_flag_pdr) |
ecb4347a DJ |
1603 | { |
1604 | pdr_seg = subseg_new (".pdr", (subsegT) 0); | |
1605 | (void) bfd_set_section_flags (stdoutput, pdr_seg, | |
1606 | SEC_READONLY | SEC_RELOC | |
1607 | | SEC_DEBUGGING); | |
1608 | (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2); | |
1609 | } | |
252b5132 RH |
1610 | #endif |
1611 | ||
1612 | subseg_set (seg, subseg); | |
1613 | } | |
1614 | } | |
1615 | ||
1616 | if (! ECOFF_DEBUGGING) | |
1617 | md_obj_begin (); | |
71400594 RS |
1618 | |
1619 | if (mips_fix_vr4120) | |
1620 | init_vr4120_conflicts (); | |
252b5132 RH |
1621 | } |
1622 | ||
1623 | void | |
17a2f251 | 1624 | md_mips_end (void) |
252b5132 RH |
1625 | { |
1626 | if (! ECOFF_DEBUGGING) | |
1627 | md_obj_end (); | |
1628 | } | |
1629 | ||
1630 | void | |
17a2f251 | 1631 | md_assemble (char *str) |
252b5132 RH |
1632 | { |
1633 | struct mips_cl_insn insn; | |
f6688943 TS |
1634 | bfd_reloc_code_real_type unused_reloc[3] |
1635 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 RH |
1636 | |
1637 | imm_expr.X_op = O_absent; | |
5f74bc13 | 1638 | imm2_expr.X_op = O_absent; |
252b5132 | 1639 | offset_expr.X_op = O_absent; |
f6688943 TS |
1640 | imm_reloc[0] = BFD_RELOC_UNUSED; |
1641 | imm_reloc[1] = BFD_RELOC_UNUSED; | |
1642 | imm_reloc[2] = BFD_RELOC_UNUSED; | |
1643 | offset_reloc[0] = BFD_RELOC_UNUSED; | |
1644 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
1645 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
1646 | |
1647 | if (mips_opts.mips16) | |
1648 | mips16_ip (str, &insn); | |
1649 | else | |
1650 | { | |
1651 | mips_ip (str, &insn); | |
beae10d5 KH |
1652 | DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"), |
1653 | str, insn.insn_opcode)); | |
252b5132 RH |
1654 | } |
1655 | ||
1656 | if (insn_error) | |
1657 | { | |
1658 | as_bad ("%s `%s'", insn_error, str); | |
1659 | return; | |
1660 | } | |
1661 | ||
1662 | if (insn.insn_mo->pinfo == INSN_MACRO) | |
1663 | { | |
584892a6 | 1664 | macro_start (); |
252b5132 RH |
1665 | if (mips_opts.mips16) |
1666 | mips16_macro (&insn); | |
1667 | else | |
1668 | macro (&insn); | |
584892a6 | 1669 | macro_end (); |
252b5132 RH |
1670 | } |
1671 | else | |
1672 | { | |
1673 | if (imm_expr.X_op != O_absent) | |
4d7206a2 | 1674 | append_insn (&insn, &imm_expr, imm_reloc); |
252b5132 | 1675 | else if (offset_expr.X_op != O_absent) |
4d7206a2 | 1676 | append_insn (&insn, &offset_expr, offset_reloc); |
252b5132 | 1677 | else |
4d7206a2 | 1678 | append_insn (&insn, NULL, unused_reloc); |
252b5132 RH |
1679 | } |
1680 | } | |
1681 | ||
5919d012 RS |
1682 | /* Return true if the given relocation might need a matching %lo(). |
1683 | Note that R_MIPS_GOT16 relocations only need a matching %lo() when | |
1684 | applied to local symbols. */ | |
1685 | ||
1686 | static inline bfd_boolean | |
17a2f251 | 1687 | reloc_needs_lo_p (bfd_reloc_code_real_type reloc) |
5919d012 | 1688 | { |
3b91255e RS |
1689 | return (HAVE_IN_PLACE_ADDENDS |
1690 | && (reloc == BFD_RELOC_HI16_S | |
d6f16593 MR |
1691 | || reloc == BFD_RELOC_MIPS_GOT16 |
1692 | || reloc == BFD_RELOC_MIPS16_HI16_S)); | |
5919d012 RS |
1693 | } |
1694 | ||
1695 | /* Return true if the given fixup is followed by a matching R_MIPS_LO16 | |
1696 | relocation. */ | |
1697 | ||
1698 | static inline bfd_boolean | |
17a2f251 | 1699 | fixup_has_matching_lo_p (fixS *fixp) |
5919d012 RS |
1700 | { |
1701 | return (fixp->fx_next != NULL | |
d6f16593 MR |
1702 | && (fixp->fx_next->fx_r_type == BFD_RELOC_LO16 |
1703 | || fixp->fx_next->fx_r_type == BFD_RELOC_MIPS16_LO16) | |
5919d012 RS |
1704 | && fixp->fx_addsy == fixp->fx_next->fx_addsy |
1705 | && fixp->fx_offset == fixp->fx_next->fx_offset); | |
1706 | } | |
1707 | ||
252b5132 RH |
1708 | /* See whether instruction IP reads register REG. CLASS is the type |
1709 | of register. */ | |
1710 | ||
1711 | static int | |
71400594 | 1712 | insn_uses_reg (const struct mips_cl_insn *ip, unsigned int reg, |
17a2f251 | 1713 | enum mips_regclass class) |
252b5132 RH |
1714 | { |
1715 | if (class == MIPS16_REG) | |
1716 | { | |
1717 | assert (mips_opts.mips16); | |
1718 | reg = mips16_to_32_reg_map[reg]; | |
1719 | class = MIPS_GR_REG; | |
1720 | } | |
1721 | ||
85b51719 TS |
1722 | /* Don't report on general register ZERO, since it never changes. */ |
1723 | if (class == MIPS_GR_REG && reg == ZERO) | |
252b5132 RH |
1724 | return 0; |
1725 | ||
1726 | if (class == MIPS_FP_REG) | |
1727 | { | |
1728 | assert (! mips_opts.mips16); | |
1729 | /* If we are called with either $f0 or $f1, we must check $f0. | |
1730 | This is not optimal, because it will introduce an unnecessary | |
1731 | NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would | |
1732 | need to distinguish reading both $f0 and $f1 or just one of | |
1733 | them. Note that we don't have to check the other way, | |
1734 | because there is no instruction that sets both $f0 and $f1 | |
1735 | and requires a delay. */ | |
1736 | if ((ip->insn_mo->pinfo & INSN_READ_FPR_S) | |
bf12938e | 1737 | && ((EXTRACT_OPERAND (FS, *ip) & ~(unsigned) 1) |
252b5132 RH |
1738 | == (reg &~ (unsigned) 1))) |
1739 | return 1; | |
1740 | if ((ip->insn_mo->pinfo & INSN_READ_FPR_T) | |
bf12938e | 1741 | && ((EXTRACT_OPERAND (FT, *ip) & ~(unsigned) 1) |
252b5132 RH |
1742 | == (reg &~ (unsigned) 1))) |
1743 | return 1; | |
1744 | } | |
1745 | else if (! mips_opts.mips16) | |
1746 | { | |
1747 | if ((ip->insn_mo->pinfo & INSN_READ_GPR_S) | |
bf12938e | 1748 | && EXTRACT_OPERAND (RS, *ip) == reg) |
252b5132 RH |
1749 | return 1; |
1750 | if ((ip->insn_mo->pinfo & INSN_READ_GPR_T) | |
bf12938e | 1751 | && EXTRACT_OPERAND (RT, *ip) == reg) |
252b5132 RH |
1752 | return 1; |
1753 | } | |
1754 | else | |
1755 | { | |
1756 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_X) | |
bf12938e | 1757 | && mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, *ip)] == reg) |
252b5132 RH |
1758 | return 1; |
1759 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Y) | |
bf12938e | 1760 | && mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RY, *ip)] == reg) |
252b5132 RH |
1761 | return 1; |
1762 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Z) | |
bf12938e | 1763 | && (mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (MOVE32Z, *ip)] |
252b5132 RH |
1764 | == reg)) |
1765 | return 1; | |
1766 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_T) && reg == TREG) | |
1767 | return 1; | |
1768 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_SP) && reg == SP) | |
1769 | return 1; | |
1770 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_31) && reg == RA) | |
1771 | return 1; | |
1772 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_GPR_X) | |
bf12938e | 1773 | && MIPS16_EXTRACT_OPERAND (REGR32, *ip) == reg) |
252b5132 RH |
1774 | return 1; |
1775 | } | |
1776 | ||
1777 | return 0; | |
1778 | } | |
1779 | ||
1780 | /* This function returns true if modifying a register requires a | |
1781 | delay. */ | |
1782 | ||
1783 | static int | |
17a2f251 | 1784 | reg_needs_delay (unsigned int reg) |
252b5132 RH |
1785 | { |
1786 | unsigned long prev_pinfo; | |
1787 | ||
47e39b9d | 1788 | prev_pinfo = history[0].insn_mo->pinfo; |
252b5132 | 1789 | if (! mips_opts.noreorder |
81912461 ILT |
1790 | && (((prev_pinfo & INSN_LOAD_MEMORY_DELAY) |
1791 | && ! gpr_interlocks) | |
1792 | || ((prev_pinfo & INSN_LOAD_COPROC_DELAY) | |
1793 | && ! cop_interlocks))) | |
252b5132 | 1794 | { |
81912461 ILT |
1795 | /* A load from a coprocessor or from memory. All load delays |
1796 | delay the use of general register rt for one instruction. */ | |
bdaaa2e1 | 1797 | /* Itbl support may require additional care here. */ |
252b5132 | 1798 | know (prev_pinfo & INSN_WRITE_GPR_T); |
bf12938e | 1799 | if (reg == EXTRACT_OPERAND (RT, history[0])) |
252b5132 RH |
1800 | return 1; |
1801 | } | |
1802 | ||
1803 | return 0; | |
1804 | } | |
1805 | ||
404a8071 RS |
1806 | /* Move all labels in insn_labels to the current insertion point. */ |
1807 | ||
1808 | static void | |
1809 | mips_move_labels (void) | |
1810 | { | |
1811 | struct insn_label_list *l; | |
1812 | valueT val; | |
1813 | ||
1814 | for (l = insn_labels; l != NULL; l = l->next) | |
1815 | { | |
1816 | assert (S_GET_SEGMENT (l->label) == now_seg); | |
1817 | symbol_set_frag (l->label, frag_now); | |
1818 | val = (valueT) frag_now_fix (); | |
1819 | /* mips16 text labels are stored as odd. */ | |
1820 | if (mips_opts.mips16) | |
1821 | ++val; | |
1822 | S_SET_VALUE (l->label, val); | |
1823 | } | |
1824 | } | |
1825 | ||
252b5132 RH |
1826 | /* Mark instruction labels in mips16 mode. This permits the linker to |
1827 | handle them specially, such as generating jalx instructions when | |
1828 | needed. We also make them odd for the duration of the assembly, in | |
1829 | order to generate the right sort of code. We will make them even | |
1830 | in the adjust_symtab routine, while leaving them marked. This is | |
1831 | convenient for the debugger and the disassembler. The linker knows | |
1832 | to make them odd again. */ | |
1833 | ||
1834 | static void | |
17a2f251 | 1835 | mips16_mark_labels (void) |
252b5132 RH |
1836 | { |
1837 | if (mips_opts.mips16) | |
1838 | { | |
1839 | struct insn_label_list *l; | |
98aa84af | 1840 | valueT val; |
252b5132 RH |
1841 | |
1842 | for (l = insn_labels; l != NULL; l = l->next) | |
1843 | { | |
1844 | #ifdef OBJ_ELF | |
1845 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
1846 | S_SET_OTHER (l->label, STO_MIPS16); | |
1847 | #endif | |
98aa84af AM |
1848 | val = S_GET_VALUE (l->label); |
1849 | if ((val & 1) == 0) | |
1850 | S_SET_VALUE (l->label, val + 1); | |
252b5132 RH |
1851 | } |
1852 | } | |
1853 | } | |
1854 | ||
4d7206a2 RS |
1855 | /* End the current frag. Make it a variant frag and record the |
1856 | relaxation info. */ | |
1857 | ||
1858 | static void | |
1859 | relax_close_frag (void) | |
1860 | { | |
584892a6 | 1861 | mips_macro_warning.first_frag = frag_now; |
4d7206a2 | 1862 | frag_var (rs_machine_dependent, 0, 0, |
584892a6 | 1863 | RELAX_ENCODE (mips_relax.sizes[0], mips_relax.sizes[1]), |
4d7206a2 RS |
1864 | mips_relax.symbol, 0, (char *) mips_relax.first_fixup); |
1865 | ||
1866 | memset (&mips_relax.sizes, 0, sizeof (mips_relax.sizes)); | |
1867 | mips_relax.first_fixup = 0; | |
1868 | } | |
1869 | ||
1870 | /* Start a new relaxation sequence whose expansion depends on SYMBOL. | |
1871 | See the comment above RELAX_ENCODE for more details. */ | |
1872 | ||
1873 | static void | |
1874 | relax_start (symbolS *symbol) | |
1875 | { | |
1876 | assert (mips_relax.sequence == 0); | |
1877 | mips_relax.sequence = 1; | |
1878 | mips_relax.symbol = symbol; | |
1879 | } | |
1880 | ||
1881 | /* Start generating the second version of a relaxable sequence. | |
1882 | See the comment above RELAX_ENCODE for more details. */ | |
252b5132 RH |
1883 | |
1884 | static void | |
4d7206a2 RS |
1885 | relax_switch (void) |
1886 | { | |
1887 | assert (mips_relax.sequence == 1); | |
1888 | mips_relax.sequence = 2; | |
1889 | } | |
1890 | ||
1891 | /* End the current relaxable sequence. */ | |
1892 | ||
1893 | static void | |
1894 | relax_end (void) | |
1895 | { | |
1896 | assert (mips_relax.sequence == 2); | |
1897 | relax_close_frag (); | |
1898 | mips_relax.sequence = 0; | |
1899 | } | |
1900 | ||
71400594 RS |
1901 | /* Classify an instruction according to the FIX_VR4120_* enumeration. |
1902 | Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected | |
1903 | by VR4120 errata. */ | |
4d7206a2 | 1904 | |
71400594 RS |
1905 | static unsigned int |
1906 | classify_vr4120_insn (const char *name) | |
252b5132 | 1907 | { |
71400594 RS |
1908 | if (strncmp (name, "macc", 4) == 0) |
1909 | return FIX_VR4120_MACC; | |
1910 | if (strncmp (name, "dmacc", 5) == 0) | |
1911 | return FIX_VR4120_DMACC; | |
1912 | if (strncmp (name, "mult", 4) == 0) | |
1913 | return FIX_VR4120_MULT; | |
1914 | if (strncmp (name, "dmult", 5) == 0) | |
1915 | return FIX_VR4120_DMULT; | |
1916 | if (strstr (name, "div")) | |
1917 | return FIX_VR4120_DIV; | |
1918 | if (strcmp (name, "mtlo") == 0 || strcmp (name, "mthi") == 0) | |
1919 | return FIX_VR4120_MTHILO; | |
1920 | return NUM_FIX_VR4120_CLASSES; | |
1921 | } | |
252b5132 | 1922 | |
71400594 RS |
1923 | /* Return the number of instructions that must separate INSN1 and INSN2, |
1924 | where INSN1 is the earlier instruction. Return the worst-case value | |
1925 | for any INSN2 if INSN2 is null. */ | |
252b5132 | 1926 | |
71400594 RS |
1927 | static unsigned int |
1928 | insns_between (const struct mips_cl_insn *insn1, | |
1929 | const struct mips_cl_insn *insn2) | |
1930 | { | |
1931 | unsigned long pinfo1, pinfo2; | |
1932 | ||
1933 | /* This function needs to know which pinfo flags are set for INSN2 | |
1934 | and which registers INSN2 uses. The former is stored in PINFO2 and | |
1935 | the latter is tested via INSN2_USES_REG. If INSN2 is null, PINFO2 | |
1936 | will have every flag set and INSN2_USES_REG will always return true. */ | |
1937 | pinfo1 = insn1->insn_mo->pinfo; | |
1938 | pinfo2 = insn2 ? insn2->insn_mo->pinfo : ~0U; | |
252b5132 | 1939 | |
71400594 RS |
1940 | #define INSN2_USES_REG(REG, CLASS) \ |
1941 | (insn2 == NULL || insn_uses_reg (insn2, REG, CLASS)) | |
1942 | ||
1943 | /* For most targets, write-after-read dependencies on the HI and LO | |
1944 | registers must be separated by at least two instructions. */ | |
1945 | if (!hilo_interlocks) | |
252b5132 | 1946 | { |
71400594 RS |
1947 | if ((pinfo1 & INSN_READ_LO) && (pinfo2 & INSN_WRITE_LO)) |
1948 | return 2; | |
1949 | if ((pinfo1 & INSN_READ_HI) && (pinfo2 & INSN_WRITE_HI)) | |
1950 | return 2; | |
1951 | } | |
1952 | ||
1953 | /* If we're working around r7000 errata, there must be two instructions | |
1954 | between an mfhi or mflo and any instruction that uses the result. */ | |
1955 | if (mips_7000_hilo_fix | |
1956 | && MF_HILO_INSN (pinfo1) | |
1957 | && INSN2_USES_REG (EXTRACT_OPERAND (RD, *insn1), MIPS_GR_REG)) | |
1958 | return 2; | |
1959 | ||
1960 | /* If working around VR4120 errata, check for combinations that need | |
1961 | a single intervening instruction. */ | |
1962 | if (mips_fix_vr4120) | |
1963 | { | |
1964 | unsigned int class1, class2; | |
252b5132 | 1965 | |
71400594 RS |
1966 | class1 = classify_vr4120_insn (insn1->insn_mo->name); |
1967 | if (class1 != NUM_FIX_VR4120_CLASSES && vr4120_conflicts[class1] != 0) | |
252b5132 | 1968 | { |
71400594 RS |
1969 | if (insn2 == NULL) |
1970 | return 1; | |
1971 | class2 = classify_vr4120_insn (insn2->insn_mo->name); | |
1972 | if (vr4120_conflicts[class1] & (1 << class2)) | |
1973 | return 1; | |
252b5132 | 1974 | } |
71400594 RS |
1975 | } |
1976 | ||
1977 | if (!mips_opts.mips16) | |
1978 | { | |
1979 | /* Check for GPR or coprocessor load delays. All such delays | |
1980 | are on the RT register. */ | |
1981 | /* Itbl support may require additional care here. */ | |
1982 | if ((!gpr_interlocks && (pinfo1 & INSN_LOAD_MEMORY_DELAY)) | |
1983 | || (!cop_interlocks && (pinfo1 & INSN_LOAD_COPROC_DELAY))) | |
252b5132 | 1984 | { |
71400594 RS |
1985 | know (pinfo1 & INSN_WRITE_GPR_T); |
1986 | if (INSN2_USES_REG (EXTRACT_OPERAND (RT, *insn1), MIPS_GR_REG)) | |
1987 | return 1; | |
1988 | } | |
1989 | ||
1990 | /* Check for generic coprocessor hazards. | |
1991 | ||
1992 | This case is not handled very well. There is no special | |
1993 | knowledge of CP0 handling, and the coprocessors other than | |
1994 | the floating point unit are not distinguished at all. */ | |
1995 | /* Itbl support may require additional care here. FIXME! | |
1996 | Need to modify this to include knowledge about | |
1997 | user specified delays! */ | |
1998 | else if ((!cop_interlocks && (pinfo1 & INSN_COPROC_MOVE_DELAY)) | |
1999 | || (!cop_mem_interlocks && (pinfo1 & INSN_COPROC_MEMORY_DELAY))) | |
2000 | { | |
2001 | /* Handle cases where INSN1 writes to a known general coprocessor | |
2002 | register. There must be a one instruction delay before INSN2 | |
2003 | if INSN2 reads that register, otherwise no delay is needed. */ | |
2004 | if (pinfo1 & INSN_WRITE_FPR_T) | |
252b5132 | 2005 | { |
71400594 RS |
2006 | if (INSN2_USES_REG (EXTRACT_OPERAND (FT, *insn1), MIPS_FP_REG)) |
2007 | return 1; | |
252b5132 | 2008 | } |
71400594 | 2009 | else if (pinfo1 & INSN_WRITE_FPR_S) |
252b5132 | 2010 | { |
71400594 RS |
2011 | if (INSN2_USES_REG (EXTRACT_OPERAND (FS, *insn1), MIPS_FP_REG)) |
2012 | return 1; | |
252b5132 RH |
2013 | } |
2014 | else | |
2015 | { | |
71400594 RS |
2016 | /* Read-after-write dependencies on the control registers |
2017 | require a two-instruction gap. */ | |
2018 | if ((pinfo1 & INSN_WRITE_COND_CODE) | |
2019 | && (pinfo2 & INSN_READ_COND_CODE)) | |
2020 | return 2; | |
2021 | ||
2022 | /* We don't know exactly what INSN1 does. If INSN2 is | |
2023 | also a coprocessor instruction, assume there must be | |
2024 | a one instruction gap. */ | |
2025 | if (pinfo2 & INSN_COP) | |
2026 | return 1; | |
252b5132 RH |
2027 | } |
2028 | } | |
6b76fefe | 2029 | |
71400594 RS |
2030 | /* Check for read-after-write dependencies on the coprocessor |
2031 | control registers in cases where INSN1 does not need a general | |
2032 | coprocessor delay. This means that INSN1 is a floating point | |
2033 | comparison instruction. */ | |
2034 | /* Itbl support may require additional care here. */ | |
2035 | else if (!cop_interlocks | |
2036 | && (pinfo1 & INSN_WRITE_COND_CODE) | |
2037 | && (pinfo2 & INSN_READ_COND_CODE)) | |
2038 | return 1; | |
2039 | } | |
6b76fefe | 2040 | |
71400594 | 2041 | #undef INSN2_USES_REG |
6b76fefe | 2042 | |
71400594 RS |
2043 | return 0; |
2044 | } | |
6b76fefe | 2045 | |
7d8e00cf RS |
2046 | /* Return the number of nops that would be needed to work around the |
2047 | VR4130 mflo/mfhi errata if instruction INSN immediately followed | |
2048 | the MAX_VR4130_NOPS instructions described by HISTORY. */ | |
2049 | ||
2050 | static int | |
2051 | nops_for_vr4130 (const struct mips_cl_insn *history, | |
2052 | const struct mips_cl_insn *insn) | |
2053 | { | |
2054 | int i, j, reg; | |
2055 | ||
2056 | /* Check if the instruction writes to HI or LO. MTHI and MTLO | |
2057 | are not affected by the errata. */ | |
2058 | if (insn != 0 | |
2059 | && ((insn->insn_mo->pinfo & (INSN_WRITE_HI | INSN_WRITE_LO)) == 0 | |
2060 | || strcmp (insn->insn_mo->name, "mtlo") == 0 | |
2061 | || strcmp (insn->insn_mo->name, "mthi") == 0)) | |
2062 | return 0; | |
2063 | ||
2064 | /* Search for the first MFLO or MFHI. */ | |
2065 | for (i = 0; i < MAX_VR4130_NOPS; i++) | |
2066 | if (!history[i].noreorder_p && MF_HILO_INSN (history[i].insn_mo->pinfo)) | |
2067 | { | |
2068 | /* Extract the destination register. */ | |
2069 | if (mips_opts.mips16) | |
2070 | reg = mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, history[i])]; | |
2071 | else | |
2072 | reg = EXTRACT_OPERAND (RD, history[i]); | |
2073 | ||
2074 | /* No nops are needed if INSN reads that register. */ | |
2075 | if (insn != NULL && insn_uses_reg (insn, reg, MIPS_GR_REG)) | |
2076 | return 0; | |
2077 | ||
2078 | /* ...or if any of the intervening instructions do. */ | |
2079 | for (j = 0; j < i; j++) | |
2080 | if (insn_uses_reg (&history[j], reg, MIPS_GR_REG)) | |
2081 | return 0; | |
2082 | ||
2083 | return MAX_VR4130_NOPS - i; | |
2084 | } | |
2085 | return 0; | |
2086 | } | |
2087 | ||
71400594 RS |
2088 | /* Return the number of nops that would be needed if instruction INSN |
2089 | immediately followed the MAX_NOPS instructions given by HISTORY, | |
2090 | where HISTORY[0] is the most recent instruction. If INSN is null, | |
2091 | return the worse-case number of nops for any instruction. */ | |
bdaaa2e1 | 2092 | |
71400594 RS |
2093 | static int |
2094 | nops_for_insn (const struct mips_cl_insn *history, | |
2095 | const struct mips_cl_insn *insn) | |
2096 | { | |
2097 | int i, nops, tmp_nops; | |
bdaaa2e1 | 2098 | |
71400594 | 2099 | nops = 0; |
7d8e00cf | 2100 | for (i = 0; i < MAX_DELAY_NOPS; i++) |
71400594 RS |
2101 | if (!history[i].noreorder_p) |
2102 | { | |
2103 | tmp_nops = insns_between (history + i, insn) - i; | |
2104 | if (tmp_nops > nops) | |
2105 | nops = tmp_nops; | |
2106 | } | |
7d8e00cf RS |
2107 | |
2108 | if (mips_fix_vr4130) | |
2109 | { | |
2110 | tmp_nops = nops_for_vr4130 (history, insn); | |
2111 | if (tmp_nops > nops) | |
2112 | nops = tmp_nops; | |
2113 | } | |
2114 | ||
71400594 RS |
2115 | return nops; |
2116 | } | |
252b5132 | 2117 | |
71400594 RS |
2118 | /* The variable arguments provide NUM_INSNS extra instructions that |
2119 | might be added to HISTORY. Return the largest number of nops that | |
2120 | would be needed after the extended sequence. */ | |
252b5132 | 2121 | |
71400594 RS |
2122 | static int |
2123 | nops_for_sequence (int num_insns, const struct mips_cl_insn *history, ...) | |
2124 | { | |
2125 | va_list args; | |
2126 | struct mips_cl_insn buffer[MAX_NOPS]; | |
2127 | struct mips_cl_insn *cursor; | |
2128 | int nops; | |
2129 | ||
2130 | va_start (args, history); | |
2131 | cursor = buffer + num_insns; | |
2132 | memcpy (cursor, history, (MAX_NOPS - num_insns) * sizeof (*cursor)); | |
2133 | while (cursor > buffer) | |
2134 | *--cursor = *va_arg (args, const struct mips_cl_insn *); | |
2135 | ||
2136 | nops = nops_for_insn (buffer, NULL); | |
2137 | va_end (args); | |
2138 | return nops; | |
2139 | } | |
252b5132 | 2140 | |
71400594 RS |
2141 | /* Like nops_for_insn, but if INSN is a branch, take into account the |
2142 | worst-case delay for the branch target. */ | |
252b5132 | 2143 | |
71400594 RS |
2144 | static int |
2145 | nops_for_insn_or_target (const struct mips_cl_insn *history, | |
2146 | const struct mips_cl_insn *insn) | |
2147 | { | |
2148 | int nops, tmp_nops; | |
60b63b72 | 2149 | |
71400594 RS |
2150 | nops = nops_for_insn (history, insn); |
2151 | if (insn->insn_mo->pinfo & (INSN_UNCOND_BRANCH_DELAY | |
2152 | | INSN_COND_BRANCH_DELAY | |
2153 | | INSN_COND_BRANCH_LIKELY)) | |
2154 | { | |
2155 | tmp_nops = nops_for_sequence (2, history, insn, NOP_INSN); | |
2156 | if (tmp_nops > nops) | |
2157 | nops = tmp_nops; | |
2158 | } | |
2159 | else if (mips_opts.mips16 && (insn->insn_mo->pinfo & MIPS16_INSN_BRANCH)) | |
2160 | { | |
2161 | tmp_nops = nops_for_sequence (1, history, insn); | |
2162 | if (tmp_nops > nops) | |
2163 | nops = tmp_nops; | |
2164 | } | |
2165 | return nops; | |
2166 | } | |
2167 | ||
2168 | /* Output an instruction. IP is the instruction information. | |
2169 | ADDRESS_EXPR is an operand of the instruction to be used with | |
2170 | RELOC_TYPE. */ | |
2171 | ||
2172 | static void | |
2173 | append_insn (struct mips_cl_insn *ip, expressionS *address_expr, | |
2174 | bfd_reloc_code_real_type *reloc_type) | |
2175 | { | |
2176 | register unsigned long prev_pinfo, pinfo; | |
2177 | relax_stateT prev_insn_frag_type = 0; | |
2178 | bfd_boolean relaxed_branch = FALSE; | |
2179 | ||
2180 | /* Mark instruction labels in mips16 mode. */ | |
2181 | mips16_mark_labels (); | |
2182 | ||
2183 | prev_pinfo = history[0].insn_mo->pinfo; | |
2184 | pinfo = ip->insn_mo->pinfo; | |
2185 | ||
2186 | if (mips_relax.sequence != 2 && !mips_opts.noreorder) | |
2187 | { | |
2188 | /* There are a lot of optimizations we could do that we don't. | |
2189 | In particular, we do not, in general, reorder instructions. | |
2190 | If you use gcc with optimization, it will reorder | |
2191 | instructions and generally do much more optimization then we | |
2192 | do here; repeating all that work in the assembler would only | |
2193 | benefit hand written assembly code, and does not seem worth | |
2194 | it. */ | |
2195 | int nops = (mips_optimize == 0 | |
2196 | ? nops_for_insn (history, NULL) | |
2197 | : nops_for_insn_or_target (history, ip)); | |
2198 | if (nops > 0) | |
252b5132 RH |
2199 | { |
2200 | fragS *old_frag; | |
2201 | unsigned long old_frag_offset; | |
2202 | int i; | |
252b5132 RH |
2203 | |
2204 | old_frag = frag_now; | |
2205 | old_frag_offset = frag_now_fix (); | |
2206 | ||
2207 | for (i = 0; i < nops; i++) | |
2208 | emit_nop (); | |
2209 | ||
2210 | if (listing) | |
2211 | { | |
2212 | listing_prev_line (); | |
2213 | /* We may be at the start of a variant frag. In case we | |
2214 | are, make sure there is enough space for the frag | |
2215 | after the frags created by listing_prev_line. The | |
2216 | argument to frag_grow here must be at least as large | |
2217 | as the argument to all other calls to frag_grow in | |
2218 | this file. We don't have to worry about being in the | |
2219 | middle of a variant frag, because the variants insert | |
2220 | all needed nop instructions themselves. */ | |
2221 | frag_grow (40); | |
2222 | } | |
2223 | ||
404a8071 | 2224 | mips_move_labels (); |
252b5132 RH |
2225 | |
2226 | #ifndef NO_ECOFF_DEBUGGING | |
2227 | if (ECOFF_DEBUGGING) | |
2228 | ecoff_fix_loc (old_frag, old_frag_offset); | |
2229 | #endif | |
2230 | } | |
71400594 RS |
2231 | } |
2232 | else if (mips_relax.sequence != 2 && prev_nop_frag != NULL) | |
2233 | { | |
2234 | /* Work out how many nops in prev_nop_frag are needed by IP. */ | |
2235 | int nops = nops_for_insn_or_target (history, ip); | |
2236 | assert (nops <= prev_nop_frag_holds); | |
252b5132 | 2237 | |
71400594 RS |
2238 | /* Enforce NOPS as a minimum. */ |
2239 | if (nops > prev_nop_frag_required) | |
2240 | prev_nop_frag_required = nops; | |
252b5132 | 2241 | |
71400594 RS |
2242 | if (prev_nop_frag_holds == prev_nop_frag_required) |
2243 | { | |
2244 | /* Settle for the current number of nops. Update the history | |
2245 | accordingly (for the benefit of any future .set reorder code). */ | |
2246 | prev_nop_frag = NULL; | |
2247 | insert_into_history (prev_nop_frag_since, | |
2248 | prev_nop_frag_holds, NOP_INSN); | |
2249 | } | |
2250 | else | |
2251 | { | |
2252 | /* Allow this instruction to replace one of the nops that was | |
2253 | tentatively added to prev_nop_frag. */ | |
2254 | prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4; | |
2255 | prev_nop_frag_holds--; | |
2256 | prev_nop_frag_since++; | |
252b5132 RH |
2257 | } |
2258 | } | |
2259 | ||
58e2ea4d MR |
2260 | #ifdef OBJ_ELF |
2261 | /* The value passed to dwarf2_emit_insn is the distance between | |
2262 | the beginning of the current instruction and the address that | |
2263 | should be recorded in the debug tables. For MIPS16 debug info | |
2264 | we want to use ISA-encoded addresses, so we pass -1 for an | |
2265 | address higher by one than the current. */ | |
2266 | dwarf2_emit_insn (mips_opts.mips16 ? -1 : 0); | |
2267 | #endif | |
2268 | ||
895921c9 | 2269 | /* Record the frag type before frag_var. */ |
47e39b9d RS |
2270 | if (history[0].frag) |
2271 | prev_insn_frag_type = history[0].frag->fr_type; | |
895921c9 | 2272 | |
4d7206a2 | 2273 | if (address_expr |
0b25d3e6 | 2274 | && *reloc_type == BFD_RELOC_16_PCREL_S2 |
4a6a3df4 AO |
2275 | && (pinfo & INSN_UNCOND_BRANCH_DELAY || pinfo & INSN_COND_BRANCH_DELAY |
2276 | || pinfo & INSN_COND_BRANCH_LIKELY) | |
2277 | && mips_relax_branch | |
2278 | /* Don't try branch relaxation within .set nomacro, or within | |
2279 | .set noat if we use $at for PIC computations. If it turns | |
2280 | out that the branch was out-of-range, we'll get an error. */ | |
2281 | && !mips_opts.warn_about_macros | |
2282 | && !(mips_opts.noat && mips_pic != NO_PIC) | |
2283 | && !mips_opts.mips16) | |
2284 | { | |
895921c9 | 2285 | relaxed_branch = TRUE; |
1e915849 RS |
2286 | add_relaxed_insn (ip, (relaxed_branch_length |
2287 | (NULL, NULL, | |
2288 | (pinfo & INSN_UNCOND_BRANCH_DELAY) ? -1 | |
2289 | : (pinfo & INSN_COND_BRANCH_LIKELY) ? 1 | |
2290 | : 0)), 4, | |
2291 | RELAX_BRANCH_ENCODE | |
2292 | (pinfo & INSN_UNCOND_BRANCH_DELAY, | |
2293 | pinfo & INSN_COND_BRANCH_LIKELY, | |
2294 | pinfo & INSN_WRITE_GPR_31, | |
2295 | 0), | |
2296 | address_expr->X_add_symbol, | |
2297 | address_expr->X_add_number); | |
4a6a3df4 AO |
2298 | *reloc_type = BFD_RELOC_UNUSED; |
2299 | } | |
2300 | else if (*reloc_type > BFD_RELOC_UNUSED) | |
252b5132 RH |
2301 | { |
2302 | /* We need to set up a variant frag. */ | |
2303 | assert (mips_opts.mips16 && address_expr != NULL); | |
1e915849 RS |
2304 | add_relaxed_insn (ip, 4, 0, |
2305 | RELAX_MIPS16_ENCODE | |
2306 | (*reloc_type - BFD_RELOC_UNUSED, | |
2307 | mips16_small, mips16_ext, | |
2308 | prev_pinfo & INSN_UNCOND_BRANCH_DELAY, | |
2309 | history[0].mips16_absolute_jump_p), | |
2310 | make_expr_symbol (address_expr), 0); | |
252b5132 | 2311 | } |
252b5132 RH |
2312 | else if (mips_opts.mips16 |
2313 | && ! ip->use_extend | |
f6688943 | 2314 | && *reloc_type != BFD_RELOC_MIPS16_JMP) |
b8ee1a6e DU |
2315 | { |
2316 | if ((pinfo & INSN_UNCOND_BRANCH_DELAY) == 0) | |
2317 | /* Make sure there is enough room to swap this instruction with | |
2318 | a following jump instruction. */ | |
2319 | frag_grow (6); | |
1e915849 | 2320 | add_fixed_insn (ip); |
252b5132 RH |
2321 | } |
2322 | else | |
2323 | { | |
2324 | if (mips_opts.mips16 | |
2325 | && mips_opts.noreorder | |
2326 | && (prev_pinfo & INSN_UNCOND_BRANCH_DELAY) != 0) | |
2327 | as_warn (_("extended instruction in delay slot")); | |
2328 | ||
4d7206a2 RS |
2329 | if (mips_relax.sequence) |
2330 | { | |
2331 | /* If we've reached the end of this frag, turn it into a variant | |
2332 | frag and record the information for the instructions we've | |
2333 | written so far. */ | |
2334 | if (frag_room () < 4) | |
2335 | relax_close_frag (); | |
2336 | mips_relax.sizes[mips_relax.sequence - 1] += 4; | |
2337 | } | |
2338 | ||
584892a6 RS |
2339 | if (mips_relax.sequence != 2) |
2340 | mips_macro_warning.sizes[0] += 4; | |
2341 | if (mips_relax.sequence != 1) | |
2342 | mips_macro_warning.sizes[1] += 4; | |
2343 | ||
1e915849 RS |
2344 | if (mips_opts.mips16) |
2345 | { | |
2346 | ip->fixed_p = 1; | |
2347 | ip->mips16_absolute_jump_p = (*reloc_type == BFD_RELOC_MIPS16_JMP); | |
2348 | } | |
2349 | add_fixed_insn (ip); | |
252b5132 RH |
2350 | } |
2351 | ||
01a3f561 | 2352 | if (address_expr != NULL && *reloc_type <= BFD_RELOC_UNUSED) |
252b5132 RH |
2353 | { |
2354 | if (address_expr->X_op == O_constant) | |
2355 | { | |
f17c130b | 2356 | unsigned int tmp; |
f6688943 TS |
2357 | |
2358 | switch (*reloc_type) | |
252b5132 RH |
2359 | { |
2360 | case BFD_RELOC_32: | |
2361 | ip->insn_opcode |= address_expr->X_add_number; | |
2362 | break; | |
2363 | ||
f6688943 | 2364 | case BFD_RELOC_MIPS_HIGHEST: |
f17c130b AM |
2365 | tmp = (address_expr->X_add_number + 0x800080008000ull) >> 48; |
2366 | ip->insn_opcode |= tmp & 0xffff; | |
f6688943 TS |
2367 | break; |
2368 | ||
2369 | case BFD_RELOC_MIPS_HIGHER: | |
f17c130b AM |
2370 | tmp = (address_expr->X_add_number + 0x80008000ull) >> 32; |
2371 | ip->insn_opcode |= tmp & 0xffff; | |
f6688943 TS |
2372 | break; |
2373 | ||
2374 | case BFD_RELOC_HI16_S: | |
f17c130b AM |
2375 | tmp = (address_expr->X_add_number + 0x8000) >> 16; |
2376 | ip->insn_opcode |= tmp & 0xffff; | |
f6688943 TS |
2377 | break; |
2378 | ||
2379 | case BFD_RELOC_HI16: | |
2380 | ip->insn_opcode |= (address_expr->X_add_number >> 16) & 0xffff; | |
2381 | break; | |
2382 | ||
01a3f561 | 2383 | case BFD_RELOC_UNUSED: |
252b5132 | 2384 | case BFD_RELOC_LO16: |
ed6fb7bd | 2385 | case BFD_RELOC_MIPS_GOT_DISP: |
252b5132 RH |
2386 | ip->insn_opcode |= address_expr->X_add_number & 0xffff; |
2387 | break; | |
2388 | ||
2389 | case BFD_RELOC_MIPS_JMP: | |
2390 | if ((address_expr->X_add_number & 3) != 0) | |
2391 | as_bad (_("jump to misaligned address (0x%lx)"), | |
2392 | (unsigned long) address_expr->X_add_number); | |
f3c0ec86 | 2393 | if (address_expr->X_add_number & ~0xfffffff) |
7496292d TS |
2394 | as_bad (_("jump address range overflow (0x%lx)"), |
2395 | (unsigned long) address_expr->X_add_number); | |
252b5132 RH |
2396 | ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0x3ffffff; |
2397 | break; | |
2398 | ||
2399 | case BFD_RELOC_MIPS16_JMP: | |
2400 | if ((address_expr->X_add_number & 3) != 0) | |
2401 | as_bad (_("jump to misaligned address (0x%lx)"), | |
2402 | (unsigned long) address_expr->X_add_number); | |
f3c0ec86 | 2403 | if (address_expr->X_add_number & ~0xfffffff) |
7496292d TS |
2404 | as_bad (_("jump address range overflow (0x%lx)"), |
2405 | (unsigned long) address_expr->X_add_number); | |
252b5132 RH |
2406 | ip->insn_opcode |= |
2407 | (((address_expr->X_add_number & 0x7c0000) << 3) | |
2408 | | ((address_expr->X_add_number & 0xf800000) >> 7) | |
2409 | | ((address_expr->X_add_number & 0x3fffc) >> 2)); | |
2410 | break; | |
2411 | ||
252b5132 RH |
2412 | case BFD_RELOC_16_PCREL_S2: |
2413 | goto need_reloc; | |
2414 | ||
2415 | default: | |
2416 | internalError (); | |
2417 | } | |
2418 | } | |
01a3f561 | 2419 | else if (*reloc_type < BFD_RELOC_UNUSED) |
252b5132 | 2420 | need_reloc: |
4d7206a2 RS |
2421 | { |
2422 | reloc_howto_type *howto; | |
2423 | int i; | |
34ce925e | 2424 | |
4d7206a2 RS |
2425 | /* In a compound relocation, it is the final (outermost) |
2426 | operator that determines the relocated field. */ | |
2427 | for (i = 1; i < 3; i++) | |
2428 | if (reloc_type[i] == BFD_RELOC_UNUSED) | |
2429 | break; | |
34ce925e | 2430 | |
4d7206a2 | 2431 | howto = bfd_reloc_type_lookup (stdoutput, reloc_type[i - 1]); |
1e915849 RS |
2432 | ip->fixp[0] = fix_new_exp (ip->frag, ip->where, |
2433 | bfd_get_reloc_size (howto), | |
2434 | address_expr, | |
2435 | reloc_type[0] == BFD_RELOC_16_PCREL_S2, | |
2436 | reloc_type[0]); | |
4d7206a2 RS |
2437 | |
2438 | /* These relocations can have an addend that won't fit in | |
2439 | 4 octets for 64bit assembly. */ | |
2440 | if (HAVE_64BIT_GPRS | |
2441 | && ! howto->partial_inplace | |
2442 | && (reloc_type[0] == BFD_RELOC_16 | |
2443 | || reloc_type[0] == BFD_RELOC_32 | |
2444 | || reloc_type[0] == BFD_RELOC_MIPS_JMP | |
2445 | || reloc_type[0] == BFD_RELOC_HI16_S | |
2446 | || reloc_type[0] == BFD_RELOC_LO16 | |
2447 | || reloc_type[0] == BFD_RELOC_GPREL16 | |
2448 | || reloc_type[0] == BFD_RELOC_MIPS_LITERAL | |
2449 | || reloc_type[0] == BFD_RELOC_GPREL32 | |
2450 | || reloc_type[0] == BFD_RELOC_64 | |
2451 | || reloc_type[0] == BFD_RELOC_CTOR | |
2452 | || reloc_type[0] == BFD_RELOC_MIPS_SUB | |
2453 | || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST | |
2454 | || reloc_type[0] == BFD_RELOC_MIPS_HIGHER | |
2455 | || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP | |
2456 | || reloc_type[0] == BFD_RELOC_MIPS_REL16 | |
d6f16593 MR |
2457 | || reloc_type[0] == BFD_RELOC_MIPS_RELGOT |
2458 | || reloc_type[0] == BFD_RELOC_MIPS16_GPREL | |
2459 | || reloc_type[0] == BFD_RELOC_MIPS16_HI16_S | |
2460 | || reloc_type[0] == BFD_RELOC_MIPS16_LO16)) | |
1e915849 | 2461 | ip->fixp[0]->fx_no_overflow = 1; |
4d7206a2 RS |
2462 | |
2463 | if (mips_relax.sequence) | |
2464 | { | |
2465 | if (mips_relax.first_fixup == 0) | |
1e915849 | 2466 | mips_relax.first_fixup = ip->fixp[0]; |
4d7206a2 RS |
2467 | } |
2468 | else if (reloc_needs_lo_p (*reloc_type)) | |
2469 | { | |
2470 | struct mips_hi_fixup *hi_fixup; | |
252b5132 | 2471 | |
4d7206a2 RS |
2472 | /* Reuse the last entry if it already has a matching %lo. */ |
2473 | hi_fixup = mips_hi_fixup_list; | |
2474 | if (hi_fixup == 0 | |
2475 | || !fixup_has_matching_lo_p (hi_fixup->fixp)) | |
2476 | { | |
2477 | hi_fixup = ((struct mips_hi_fixup *) | |
2478 | xmalloc (sizeof (struct mips_hi_fixup))); | |
2479 | hi_fixup->next = mips_hi_fixup_list; | |
2480 | mips_hi_fixup_list = hi_fixup; | |
252b5132 | 2481 | } |
1e915849 | 2482 | hi_fixup->fixp = ip->fixp[0]; |
4d7206a2 RS |
2483 | hi_fixup->seg = now_seg; |
2484 | } | |
f6688943 | 2485 | |
4d7206a2 RS |
2486 | /* Add fixups for the second and third relocations, if given. |
2487 | Note that the ABI allows the second relocation to be | |
2488 | against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the | |
2489 | moment we only use RSS_UNDEF, but we could add support | |
2490 | for the others if it ever becomes necessary. */ | |
2491 | for (i = 1; i < 3; i++) | |
2492 | if (reloc_type[i] != BFD_RELOC_UNUSED) | |
2493 | { | |
1e915849 RS |
2494 | ip->fixp[i] = fix_new (ip->frag, ip->where, |
2495 | ip->fixp[0]->fx_size, NULL, 0, | |
2496 | FALSE, reloc_type[i]); | |
b1dca8ee RS |
2497 | |
2498 | /* Use fx_tcbit to mark compound relocs. */ | |
1e915849 RS |
2499 | ip->fixp[0]->fx_tcbit = 1; |
2500 | ip->fixp[i]->fx_tcbit = 1; | |
4d7206a2 | 2501 | } |
252b5132 RH |
2502 | } |
2503 | } | |
1e915849 | 2504 | install_insn (ip); |
252b5132 RH |
2505 | |
2506 | /* Update the register mask information. */ | |
2507 | if (! mips_opts.mips16) | |
2508 | { | |
2509 | if (pinfo & INSN_WRITE_GPR_D) | |
bf12938e | 2510 | mips_gprmask |= 1 << EXTRACT_OPERAND (RD, *ip); |
252b5132 | 2511 | if ((pinfo & (INSN_WRITE_GPR_T | INSN_READ_GPR_T)) != 0) |
bf12938e | 2512 | mips_gprmask |= 1 << EXTRACT_OPERAND (RT, *ip); |
252b5132 | 2513 | if (pinfo & INSN_READ_GPR_S) |
bf12938e | 2514 | mips_gprmask |= 1 << EXTRACT_OPERAND (RS, *ip); |
252b5132 | 2515 | if (pinfo & INSN_WRITE_GPR_31) |
f9419b05 | 2516 | mips_gprmask |= 1 << RA; |
252b5132 | 2517 | if (pinfo & INSN_WRITE_FPR_D) |
bf12938e | 2518 | mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FD, *ip); |
252b5132 | 2519 | if ((pinfo & (INSN_WRITE_FPR_S | INSN_READ_FPR_S)) != 0) |
bf12938e | 2520 | mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FS, *ip); |
252b5132 | 2521 | if ((pinfo & (INSN_WRITE_FPR_T | INSN_READ_FPR_T)) != 0) |
bf12938e | 2522 | mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FT, *ip); |
252b5132 | 2523 | if ((pinfo & INSN_READ_FPR_R) != 0) |
bf12938e | 2524 | mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FR, *ip); |
252b5132 RH |
2525 | if (pinfo & INSN_COP) |
2526 | { | |
bdaaa2e1 KH |
2527 | /* We don't keep enough information to sort these cases out. |
2528 | The itbl support does keep this information however, although | |
2529 | we currently don't support itbl fprmats as part of the cop | |
2530 | instruction. May want to add this support in the future. */ | |
252b5132 RH |
2531 | } |
2532 | /* Never set the bit for $0, which is always zero. */ | |
beae10d5 | 2533 | mips_gprmask &= ~1 << 0; |
252b5132 RH |
2534 | } |
2535 | else | |
2536 | { | |
2537 | if (pinfo & (MIPS16_INSN_WRITE_X | MIPS16_INSN_READ_X)) | |
bf12938e | 2538 | mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (RX, *ip); |
252b5132 | 2539 | if (pinfo & (MIPS16_INSN_WRITE_Y | MIPS16_INSN_READ_Y)) |
bf12938e | 2540 | mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (RY, *ip); |
252b5132 | 2541 | if (pinfo & MIPS16_INSN_WRITE_Z) |
bf12938e | 2542 | mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (RZ, *ip); |
252b5132 RH |
2543 | if (pinfo & (MIPS16_INSN_WRITE_T | MIPS16_INSN_READ_T)) |
2544 | mips_gprmask |= 1 << TREG; | |
2545 | if (pinfo & (MIPS16_INSN_WRITE_SP | MIPS16_INSN_READ_SP)) | |
2546 | mips_gprmask |= 1 << SP; | |
2547 | if (pinfo & (MIPS16_INSN_WRITE_31 | MIPS16_INSN_READ_31)) | |
2548 | mips_gprmask |= 1 << RA; | |
2549 | if (pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
2550 | mips_gprmask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode); | |
2551 | if (pinfo & MIPS16_INSN_READ_Z) | |
bf12938e | 2552 | mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (MOVE32Z, *ip); |
252b5132 | 2553 | if (pinfo & MIPS16_INSN_READ_GPR_X) |
bf12938e | 2554 | mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (REGR32, *ip); |
252b5132 RH |
2555 | } |
2556 | ||
4d7206a2 | 2557 | if (mips_relax.sequence != 2 && !mips_opts.noreorder) |
252b5132 RH |
2558 | { |
2559 | /* Filling the branch delay slot is more complex. We try to | |
2560 | switch the branch with the previous instruction, which we can | |
2561 | do if the previous instruction does not set up a condition | |
2562 | that the branch tests and if the branch is not itself the | |
2563 | target of any branch. */ | |
2564 | if ((pinfo & INSN_UNCOND_BRANCH_DELAY) | |
2565 | || (pinfo & INSN_COND_BRANCH_DELAY)) | |
2566 | { | |
2567 | if (mips_optimize < 2 | |
2568 | /* If we have seen .set volatile or .set nomove, don't | |
2569 | optimize. */ | |
2570 | || mips_opts.nomove != 0 | |
a38419a5 RS |
2571 | /* We can't swap if the previous instruction's position |
2572 | is fixed. */ | |
2573 | || history[0].fixed_p | |
252b5132 RH |
2574 | /* If the previous previous insn was in a .set |
2575 | noreorder, we can't swap. Actually, the MIPS | |
2576 | assembler will swap in this situation. However, gcc | |
2577 | configured -with-gnu-as will generate code like | |
2578 | .set noreorder | |
2579 | lw $4,XXX | |
2580 | .set reorder | |
2581 | INSN | |
2582 | bne $4,$0,foo | |
2583 | in which we can not swap the bne and INSN. If gcc is | |
2584 | not configured -with-gnu-as, it does not output the | |
a38419a5 | 2585 | .set pseudo-ops. */ |
47e39b9d | 2586 | || history[1].noreorder_p |
252b5132 RH |
2587 | /* If the branch is itself the target of a branch, we |
2588 | can not swap. We cheat on this; all we check for is | |
2589 | whether there is a label on this instruction. If | |
2590 | there are any branches to anything other than a | |
2591 | label, users must use .set noreorder. */ | |
2592 | || insn_labels != NULL | |
895921c9 MR |
2593 | /* If the previous instruction is in a variant frag |
2594 | other than this branch's one, we cannot do the swap. | |
2595 | This does not apply to the mips16, which uses variant | |
2596 | frags for different purposes. */ | |
252b5132 | 2597 | || (! mips_opts.mips16 |
895921c9 | 2598 | && prev_insn_frag_type == rs_machine_dependent) |
71400594 RS |
2599 | /* Check for conflicts between the branch and the instructions |
2600 | before the candidate delay slot. */ | |
2601 | || nops_for_insn (history + 1, ip) > 0 | |
2602 | /* Check for conflicts between the swapped sequence and the | |
2603 | target of the branch. */ | |
2604 | || nops_for_sequence (2, history + 1, ip, history) > 0 | |
252b5132 RH |
2605 | /* We do not swap with a trap instruction, since it |
2606 | complicates trap handlers to have the trap | |
2607 | instruction be in a delay slot. */ | |
2608 | || (prev_pinfo & INSN_TRAP) | |
2609 | /* If the branch reads a register that the previous | |
2610 | instruction sets, we can not swap. */ | |
2611 | || (! mips_opts.mips16 | |
2612 | && (prev_pinfo & INSN_WRITE_GPR_T) | |
bf12938e | 2613 | && insn_uses_reg (ip, EXTRACT_OPERAND (RT, history[0]), |
252b5132 RH |
2614 | MIPS_GR_REG)) |
2615 | || (! mips_opts.mips16 | |
2616 | && (prev_pinfo & INSN_WRITE_GPR_D) | |
bf12938e | 2617 | && insn_uses_reg (ip, EXTRACT_OPERAND (RD, history[0]), |
252b5132 RH |
2618 | MIPS_GR_REG)) |
2619 | || (mips_opts.mips16 | |
2620 | && (((prev_pinfo & MIPS16_INSN_WRITE_X) | |
bf12938e RS |
2621 | && (insn_uses_reg |
2622 | (ip, MIPS16_EXTRACT_OPERAND (RX, history[0]), | |
2623 | MIPS16_REG))) | |
252b5132 | 2624 | || ((prev_pinfo & MIPS16_INSN_WRITE_Y) |
bf12938e RS |
2625 | && (insn_uses_reg |
2626 | (ip, MIPS16_EXTRACT_OPERAND (RY, history[0]), | |
2627 | MIPS16_REG))) | |
252b5132 | 2628 | || ((prev_pinfo & MIPS16_INSN_WRITE_Z) |
bf12938e RS |
2629 | && (insn_uses_reg |
2630 | (ip, MIPS16_EXTRACT_OPERAND (RZ, history[0]), | |
2631 | MIPS16_REG))) | |
252b5132 RH |
2632 | || ((prev_pinfo & MIPS16_INSN_WRITE_T) |
2633 | && insn_uses_reg (ip, TREG, MIPS_GR_REG)) | |
2634 | || ((prev_pinfo & MIPS16_INSN_WRITE_31) | |
2635 | && insn_uses_reg (ip, RA, MIPS_GR_REG)) | |
2636 | || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
2637 | && insn_uses_reg (ip, | |
47e39b9d RS |
2638 | MIPS16OP_EXTRACT_REG32R |
2639 | (history[0].insn_opcode), | |
252b5132 RH |
2640 | MIPS_GR_REG)))) |
2641 | /* If the branch writes a register that the previous | |
2642 | instruction sets, we can not swap (we know that | |
2643 | branches write only to RD or to $31). */ | |
2644 | || (! mips_opts.mips16 | |
2645 | && (prev_pinfo & INSN_WRITE_GPR_T) | |
2646 | && (((pinfo & INSN_WRITE_GPR_D) | |
bf12938e RS |
2647 | && (EXTRACT_OPERAND (RT, history[0]) |
2648 | == EXTRACT_OPERAND (RD, *ip))) | |
252b5132 | 2649 | || ((pinfo & INSN_WRITE_GPR_31) |
bf12938e | 2650 | && EXTRACT_OPERAND (RT, history[0]) == RA))) |
252b5132 RH |
2651 | || (! mips_opts.mips16 |
2652 | && (prev_pinfo & INSN_WRITE_GPR_D) | |
2653 | && (((pinfo & INSN_WRITE_GPR_D) | |
bf12938e RS |
2654 | && (EXTRACT_OPERAND (RD, history[0]) |
2655 | == EXTRACT_OPERAND (RD, *ip))) | |
252b5132 | 2656 | || ((pinfo & INSN_WRITE_GPR_31) |
bf12938e | 2657 | && EXTRACT_OPERAND (RD, history[0]) == RA))) |
252b5132 RH |
2658 | || (mips_opts.mips16 |
2659 | && (pinfo & MIPS16_INSN_WRITE_31) | |
2660 | && ((prev_pinfo & MIPS16_INSN_WRITE_31) | |
2661 | || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
47e39b9d | 2662 | && (MIPS16OP_EXTRACT_REG32R (history[0].insn_opcode) |
252b5132 RH |
2663 | == RA)))) |
2664 | /* If the branch writes a register that the previous | |
2665 | instruction reads, we can not swap (we know that | |
2666 | branches only write to RD or to $31). */ | |
2667 | || (! mips_opts.mips16 | |
2668 | && (pinfo & INSN_WRITE_GPR_D) | |
47e39b9d | 2669 | && insn_uses_reg (&history[0], |
bf12938e | 2670 | EXTRACT_OPERAND (RD, *ip), |
252b5132 RH |
2671 | MIPS_GR_REG)) |
2672 | || (! mips_opts.mips16 | |
2673 | && (pinfo & INSN_WRITE_GPR_31) | |
47e39b9d | 2674 | && insn_uses_reg (&history[0], RA, MIPS_GR_REG)) |
252b5132 RH |
2675 | || (mips_opts.mips16 |
2676 | && (pinfo & MIPS16_INSN_WRITE_31) | |
47e39b9d | 2677 | && insn_uses_reg (&history[0], RA, MIPS_GR_REG)) |
252b5132 RH |
2678 | /* If one instruction sets a condition code and the |
2679 | other one uses a condition code, we can not swap. */ | |
2680 | || ((pinfo & INSN_READ_COND_CODE) | |
2681 | && (prev_pinfo & INSN_WRITE_COND_CODE)) | |
2682 | || ((pinfo & INSN_WRITE_COND_CODE) | |
2683 | && (prev_pinfo & INSN_READ_COND_CODE)) | |
2684 | /* If the previous instruction uses the PC, we can not | |
2685 | swap. */ | |
2686 | || (mips_opts.mips16 | |
2687 | && (prev_pinfo & MIPS16_INSN_READ_PC)) | |
252b5132 RH |
2688 | /* If the previous instruction had a fixup in mips16 |
2689 | mode, we can not swap. This normally means that the | |
2690 | previous instruction was a 4 byte branch anyhow. */ | |
47e39b9d | 2691 | || (mips_opts.mips16 && history[0].fixp[0]) |
bdaaa2e1 KH |
2692 | /* If the previous instruction is a sync, sync.l, or |
2693 | sync.p, we can not swap. */ | |
f173e82e | 2694 | || (prev_pinfo & INSN_SYNC)) |
252b5132 RH |
2695 | { |
2696 | /* We could do even better for unconditional branches to | |
2697 | portions of this object file; we could pick up the | |
2698 | instruction at the destination, put it in the delay | |
2699 | slot, and bump the destination address. */ | |
1e915849 | 2700 | insert_into_history (0, 1, ip); |
252b5132 | 2701 | emit_nop (); |
dd22970f ILT |
2702 | if (mips_relax.sequence) |
2703 | mips_relax.sizes[mips_relax.sequence - 1] += 4; | |
252b5132 RH |
2704 | } |
2705 | else | |
2706 | { | |
2707 | /* It looks like we can actually do the swap. */ | |
1e915849 RS |
2708 | struct mips_cl_insn delay = history[0]; |
2709 | if (mips_opts.mips16) | |
252b5132 | 2710 | { |
b8ee1a6e DU |
2711 | know (delay.frag == ip->frag); |
2712 | move_insn (ip, delay.frag, delay.where); | |
2713 | move_insn (&delay, ip->frag, ip->where + insn_length (ip)); | |
1e915849 RS |
2714 | } |
2715 | else if (relaxed_branch) | |
2716 | { | |
2717 | /* Add the delay slot instruction to the end of the | |
2718 | current frag and shrink the fixed part of the | |
2719 | original frag. If the branch occupies the tail of | |
2720 | the latter, move it backwards to cover the gap. */ | |
2721 | delay.frag->fr_fix -= 4; | |
2722 | if (delay.frag == ip->frag) | |
2723 | move_insn (ip, ip->frag, ip->where - 4); | |
2724 | add_fixed_insn (&delay); | |
252b5132 RH |
2725 | } |
2726 | else | |
2727 | { | |
1e915849 RS |
2728 | move_insn (&delay, ip->frag, ip->where); |
2729 | move_insn (ip, history[0].frag, history[0].where); | |
252b5132 | 2730 | } |
1e915849 RS |
2731 | history[0] = *ip; |
2732 | delay.fixed_p = 1; | |
2733 | insert_into_history (0, 1, &delay); | |
252b5132 | 2734 | } |
252b5132 RH |
2735 | |
2736 | /* If that was an unconditional branch, forget the previous | |
2737 | insn information. */ | |
2738 | if (pinfo & INSN_UNCOND_BRANCH_DELAY) | |
7d10b47d | 2739 | mips_no_prev_insn (); |
252b5132 RH |
2740 | } |
2741 | else if (pinfo & INSN_COND_BRANCH_LIKELY) | |
2742 | { | |
2743 | /* We don't yet optimize a branch likely. What we should do | |
2744 | is look at the target, copy the instruction found there | |
2745 | into the delay slot, and increment the branch to jump to | |
2746 | the next instruction. */ | |
1e915849 | 2747 | insert_into_history (0, 1, ip); |
252b5132 | 2748 | emit_nop (); |
252b5132 RH |
2749 | } |
2750 | else | |
1e915849 | 2751 | insert_into_history (0, 1, ip); |
252b5132 | 2752 | } |
1e915849 RS |
2753 | else |
2754 | insert_into_history (0, 1, ip); | |
252b5132 RH |
2755 | |
2756 | /* We just output an insn, so the next one doesn't have a label. */ | |
2757 | mips_clear_insn_labels (); | |
252b5132 RH |
2758 | } |
2759 | ||
7d10b47d | 2760 | /* Forget that there was any previous instruction or label. */ |
252b5132 RH |
2761 | |
2762 | static void | |
7d10b47d | 2763 | mips_no_prev_insn (void) |
252b5132 | 2764 | { |
7d10b47d RS |
2765 | prev_nop_frag = NULL; |
2766 | insert_into_history (0, ARRAY_SIZE (history), NOP_INSN); | |
252b5132 RH |
2767 | mips_clear_insn_labels (); |
2768 | } | |
2769 | ||
7d10b47d RS |
2770 | /* This function must be called before we emit something other than |
2771 | instructions. It is like mips_no_prev_insn except that it inserts | |
2772 | any NOPS that might be needed by previous instructions. */ | |
252b5132 | 2773 | |
7d10b47d RS |
2774 | void |
2775 | mips_emit_delays (void) | |
252b5132 RH |
2776 | { |
2777 | if (! mips_opts.noreorder) | |
2778 | { | |
71400594 | 2779 | int nops = nops_for_insn (history, NULL); |
252b5132 RH |
2780 | if (nops > 0) |
2781 | { | |
7d10b47d RS |
2782 | while (nops-- > 0) |
2783 | add_fixed_insn (NOP_INSN); | |
2784 | mips_move_labels (); | |
2785 | } | |
2786 | } | |
2787 | mips_no_prev_insn (); | |
2788 | } | |
2789 | ||
2790 | /* Start a (possibly nested) noreorder block. */ | |
2791 | ||
2792 | static void | |
2793 | start_noreorder (void) | |
2794 | { | |
2795 | if (mips_opts.noreorder == 0) | |
2796 | { | |
2797 | unsigned int i; | |
2798 | int nops; | |
2799 | ||
2800 | /* None of the instructions before the .set noreorder can be moved. */ | |
2801 | for (i = 0; i < ARRAY_SIZE (history); i++) | |
2802 | history[i].fixed_p = 1; | |
2803 | ||
2804 | /* Insert any nops that might be needed between the .set noreorder | |
2805 | block and the previous instructions. We will later remove any | |
2806 | nops that turn out not to be needed. */ | |
2807 | nops = nops_for_insn (history, NULL); | |
2808 | if (nops > 0) | |
2809 | { | |
2810 | if (mips_optimize != 0) | |
252b5132 RH |
2811 | { |
2812 | /* Record the frag which holds the nop instructions, so | |
2813 | that we can remove them if we don't need them. */ | |
2814 | frag_grow (mips_opts.mips16 ? nops * 2 : nops * 4); | |
2815 | prev_nop_frag = frag_now; | |
2816 | prev_nop_frag_holds = nops; | |
2817 | prev_nop_frag_required = 0; | |
2818 | prev_nop_frag_since = 0; | |
2819 | } | |
2820 | ||
2821 | for (; nops > 0; --nops) | |
1e915849 | 2822 | add_fixed_insn (NOP_INSN); |
252b5132 | 2823 | |
7d10b47d RS |
2824 | /* Move on to a new frag, so that it is safe to simply |
2825 | decrease the size of prev_nop_frag. */ | |
2826 | frag_wane (frag_now); | |
2827 | frag_new (0); | |
404a8071 | 2828 | mips_move_labels (); |
252b5132 | 2829 | } |
7d10b47d RS |
2830 | mips16_mark_labels (); |
2831 | mips_clear_insn_labels (); | |
252b5132 | 2832 | } |
7d10b47d RS |
2833 | mips_opts.noreorder++; |
2834 | mips_any_noreorder = 1; | |
2835 | } | |
252b5132 | 2836 | |
7d10b47d | 2837 | /* End a nested noreorder block. */ |
252b5132 | 2838 | |
7d10b47d RS |
2839 | static void |
2840 | end_noreorder (void) | |
2841 | { | |
2842 | mips_opts.noreorder--; | |
2843 | if (mips_opts.noreorder == 0 && prev_nop_frag != NULL) | |
2844 | { | |
2845 | /* Commit to inserting prev_nop_frag_required nops and go back to | |
2846 | handling nop insertion the .set reorder way. */ | |
2847 | prev_nop_frag->fr_fix -= ((prev_nop_frag_holds - prev_nop_frag_required) | |
2848 | * (mips_opts.mips16 ? 2 : 4)); | |
2849 | insert_into_history (prev_nop_frag_since, | |
2850 | prev_nop_frag_required, NOP_INSN); | |
2851 | prev_nop_frag = NULL; | |
2852 | } | |
252b5132 RH |
2853 | } |
2854 | ||
584892a6 RS |
2855 | /* Set up global variables for the start of a new macro. */ |
2856 | ||
2857 | static void | |
2858 | macro_start (void) | |
2859 | { | |
2860 | memset (&mips_macro_warning.sizes, 0, sizeof (mips_macro_warning.sizes)); | |
2861 | mips_macro_warning.delay_slot_p = (mips_opts.noreorder | |
47e39b9d | 2862 | && (history[0].insn_mo->pinfo |
584892a6 RS |
2863 | & (INSN_UNCOND_BRANCH_DELAY |
2864 | | INSN_COND_BRANCH_DELAY | |
2865 | | INSN_COND_BRANCH_LIKELY)) != 0); | |
2866 | } | |
2867 | ||
2868 | /* Given that a macro is longer than 4 bytes, return the appropriate warning | |
2869 | for it. Return null if no warning is needed. SUBTYPE is a bitmask of | |
2870 | RELAX_DELAY_SLOT and RELAX_NOMACRO. */ | |
2871 | ||
2872 | static const char * | |
2873 | macro_warning (relax_substateT subtype) | |
2874 | { | |
2875 | if (subtype & RELAX_DELAY_SLOT) | |
2876 | return _("Macro instruction expanded into multiple instructions" | |
2877 | " in a branch delay slot"); | |
2878 | else if (subtype & RELAX_NOMACRO) | |
2879 | return _("Macro instruction expanded into multiple instructions"); | |
2880 | else | |
2881 | return 0; | |
2882 | } | |
2883 | ||
2884 | /* Finish up a macro. Emit warnings as appropriate. */ | |
2885 | ||
2886 | static void | |
2887 | macro_end (void) | |
2888 | { | |
2889 | if (mips_macro_warning.sizes[0] > 4 || mips_macro_warning.sizes[1] > 4) | |
2890 | { | |
2891 | relax_substateT subtype; | |
2892 | ||
2893 | /* Set up the relaxation warning flags. */ | |
2894 | subtype = 0; | |
2895 | if (mips_macro_warning.sizes[1] > mips_macro_warning.sizes[0]) | |
2896 | subtype |= RELAX_SECOND_LONGER; | |
2897 | if (mips_opts.warn_about_macros) | |
2898 | subtype |= RELAX_NOMACRO; | |
2899 | if (mips_macro_warning.delay_slot_p) | |
2900 | subtype |= RELAX_DELAY_SLOT; | |
2901 | ||
2902 | if (mips_macro_warning.sizes[0] > 4 && mips_macro_warning.sizes[1] > 4) | |
2903 | { | |
2904 | /* Either the macro has a single implementation or both | |
2905 | implementations are longer than 4 bytes. Emit the | |
2906 | warning now. */ | |
2907 | const char *msg = macro_warning (subtype); | |
2908 | if (msg != 0) | |
2909 | as_warn (msg); | |
2910 | } | |
2911 | else | |
2912 | { | |
2913 | /* One implementation might need a warning but the other | |
2914 | definitely doesn't. */ | |
2915 | mips_macro_warning.first_frag->fr_subtype |= subtype; | |
2916 | } | |
2917 | } | |
2918 | } | |
2919 | ||
6e1304d8 RS |
2920 | /* Read a macro's relocation codes from *ARGS and store them in *R. |
2921 | The first argument in *ARGS will be either the code for a single | |
2922 | relocation or -1 followed by the three codes that make up a | |
2923 | composite relocation. */ | |
2924 | ||
2925 | static void | |
2926 | macro_read_relocs (va_list *args, bfd_reloc_code_real_type *r) | |
2927 | { | |
2928 | int i, next; | |
2929 | ||
2930 | next = va_arg (*args, int); | |
2931 | if (next >= 0) | |
2932 | r[0] = (bfd_reloc_code_real_type) next; | |
2933 | else | |
2934 | for (i = 0; i < 3; i++) | |
2935 | r[i] = (bfd_reloc_code_real_type) va_arg (*args, int); | |
2936 | } | |
2937 | ||
252b5132 RH |
2938 | /* Build an instruction created by a macro expansion. This is passed |
2939 | a pointer to the count of instructions created so far, an | |
2940 | expression, the name of the instruction to build, an operand format | |
2941 | string, and corresponding arguments. */ | |
2942 | ||
252b5132 | 2943 | static void |
67c0d1eb | 2944 | macro_build (expressionS *ep, const char *name, const char *fmt, ...) |
252b5132 | 2945 | { |
1e915849 | 2946 | const struct mips_opcode *mo; |
252b5132 | 2947 | struct mips_cl_insn insn; |
f6688943 | 2948 | bfd_reloc_code_real_type r[3]; |
252b5132 | 2949 | va_list args; |
252b5132 | 2950 | |
252b5132 | 2951 | va_start (args, fmt); |
252b5132 | 2952 | |
252b5132 RH |
2953 | if (mips_opts.mips16) |
2954 | { | |
67c0d1eb | 2955 | mips16_macro_build (ep, name, fmt, args); |
252b5132 RH |
2956 | va_end (args); |
2957 | return; | |
2958 | } | |
2959 | ||
f6688943 TS |
2960 | r[0] = BFD_RELOC_UNUSED; |
2961 | r[1] = BFD_RELOC_UNUSED; | |
2962 | r[2] = BFD_RELOC_UNUSED; | |
1e915849 RS |
2963 | mo = (struct mips_opcode *) hash_find (op_hash, name); |
2964 | assert (mo); | |
2965 | assert (strcmp (name, mo->name) == 0); | |
2966 | ||
2967 | /* Search until we get a match for NAME. It is assumed here that | |
2968 | macros will never generate MDMX or MIPS-3D instructions. */ | |
2969 | while (strcmp (fmt, mo->args) != 0 | |
2970 | || mo->pinfo == INSN_MACRO | |
2971 | || !OPCODE_IS_MEMBER (mo, | |
2972 | (mips_opts.isa | |
2973 | | (file_ase_mips16 ? INSN_MIPS16 : 0)), | |
fef14a42 | 2974 | mips_opts.arch) |
1e915849 RS |
2975 | || (mips_opts.arch == CPU_R4650 && (mo->pinfo & FP_D) != 0)) |
2976 | { | |
2977 | ++mo; | |
2978 | assert (mo->name); | |
2979 | assert (strcmp (name, mo->name) == 0); | |
252b5132 RH |
2980 | } |
2981 | ||
1e915849 | 2982 | create_insn (&insn, mo); |
252b5132 RH |
2983 | for (;;) |
2984 | { | |
2985 | switch (*fmt++) | |
2986 | { | |
2987 | case '\0': | |
2988 | break; | |
2989 | ||
2990 | case ',': | |
2991 | case '(': | |
2992 | case ')': | |
2993 | continue; | |
2994 | ||
5f74bc13 CD |
2995 | case '+': |
2996 | switch (*fmt++) | |
2997 | { | |
2998 | case 'A': | |
2999 | case 'E': | |
bf12938e | 3000 | INSERT_OPERAND (SHAMT, insn, va_arg (args, int)); |
5f74bc13 CD |
3001 | continue; |
3002 | ||
3003 | case 'B': | |
3004 | case 'F': | |
3005 | /* Note that in the macro case, these arguments are already | |
3006 | in MSB form. (When handling the instruction in the | |
3007 | non-macro case, these arguments are sizes from which | |
3008 | MSB values must be calculated.) */ | |
bf12938e | 3009 | INSERT_OPERAND (INSMSB, insn, va_arg (args, int)); |
5f74bc13 CD |
3010 | continue; |
3011 | ||
3012 | case 'C': | |
3013 | case 'G': | |
3014 | case 'H': | |
3015 | /* Note that in the macro case, these arguments are already | |
3016 | in MSBD form. (When handling the instruction in the | |
3017 | non-macro case, these arguments are sizes from which | |
3018 | MSBD values must be calculated.) */ | |
bf12938e | 3019 | INSERT_OPERAND (EXTMSBD, insn, va_arg (args, int)); |
5f74bc13 CD |
3020 | continue; |
3021 | ||
3022 | default: | |
3023 | internalError (); | |
3024 | } | |
3025 | continue; | |
3026 | ||
252b5132 RH |
3027 | case 't': |
3028 | case 'w': | |
3029 | case 'E': | |
bf12938e | 3030 | INSERT_OPERAND (RT, insn, va_arg (args, int)); |
252b5132 RH |
3031 | continue; |
3032 | ||
3033 | case 'c': | |
bf12938e | 3034 | INSERT_OPERAND (CODE, insn, va_arg (args, int)); |
38487616 TS |
3035 | continue; |
3036 | ||
252b5132 RH |
3037 | case 'T': |
3038 | case 'W': | |
bf12938e | 3039 | INSERT_OPERAND (FT, insn, va_arg (args, int)); |
252b5132 RH |
3040 | continue; |
3041 | ||
3042 | case 'd': | |
3043 | case 'G': | |
af7ee8bf | 3044 | case 'K': |
bf12938e | 3045 | INSERT_OPERAND (RD, insn, va_arg (args, int)); |
252b5132 RH |
3046 | continue; |
3047 | ||
4372b673 NC |
3048 | case 'U': |
3049 | { | |
3050 | int tmp = va_arg (args, int); | |
3051 | ||
bf12938e RS |
3052 | INSERT_OPERAND (RT, insn, tmp); |
3053 | INSERT_OPERAND (RD, insn, tmp); | |
beae10d5 | 3054 | continue; |
4372b673 NC |
3055 | } |
3056 | ||
252b5132 RH |
3057 | case 'V': |
3058 | case 'S': | |
bf12938e | 3059 | INSERT_OPERAND (FS, insn, va_arg (args, int)); |
252b5132 RH |
3060 | continue; |
3061 | ||
3062 | case 'z': | |
3063 | continue; | |
3064 | ||
3065 | case '<': | |
bf12938e | 3066 | INSERT_OPERAND (SHAMT, insn, va_arg (args, int)); |
252b5132 RH |
3067 | continue; |
3068 | ||
3069 | case 'D': | |
bf12938e | 3070 | INSERT_OPERAND (FD, insn, va_arg (args, int)); |
252b5132 RH |
3071 | continue; |
3072 | ||
3073 | case 'B': | |
bf12938e | 3074 | INSERT_OPERAND (CODE20, insn, va_arg (args, int)); |
252b5132 RH |
3075 | continue; |
3076 | ||
4372b673 | 3077 | case 'J': |
bf12938e | 3078 | INSERT_OPERAND (CODE19, insn, va_arg (args, int)); |
4372b673 NC |
3079 | continue; |
3080 | ||
252b5132 | 3081 | case 'q': |
bf12938e | 3082 | INSERT_OPERAND (CODE2, insn, va_arg (args, int)); |
252b5132 RH |
3083 | continue; |
3084 | ||
3085 | case 'b': | |
3086 | case 's': | |
3087 | case 'r': | |
3088 | case 'v': | |
bf12938e | 3089 | INSERT_OPERAND (RS, insn, va_arg (args, int)); |
252b5132 RH |
3090 | continue; |
3091 | ||
3092 | case 'i': | |
3093 | case 'j': | |
3094 | case 'o': | |
6e1304d8 | 3095 | macro_read_relocs (&args, r); |
cdf6fd85 | 3096 | assert (*r == BFD_RELOC_GPREL16 |
f6688943 TS |
3097 | || *r == BFD_RELOC_MIPS_LITERAL |
3098 | || *r == BFD_RELOC_MIPS_HIGHER | |
3099 | || *r == BFD_RELOC_HI16_S | |
3100 | || *r == BFD_RELOC_LO16 | |
3101 | || *r == BFD_RELOC_MIPS_GOT16 | |
3102 | || *r == BFD_RELOC_MIPS_CALL16 | |
438c16b8 TS |
3103 | || *r == BFD_RELOC_MIPS_GOT_DISP |
3104 | || *r == BFD_RELOC_MIPS_GOT_PAGE | |
3105 | || *r == BFD_RELOC_MIPS_GOT_OFST | |
f6688943 | 3106 | || *r == BFD_RELOC_MIPS_GOT_LO16 |
3e722fb5 | 3107 | || *r == BFD_RELOC_MIPS_CALL_LO16); |
252b5132 RH |
3108 | continue; |
3109 | ||
3110 | case 'u': | |
6e1304d8 | 3111 | macro_read_relocs (&args, r); |
252b5132 RH |
3112 | assert (ep != NULL |
3113 | && (ep->X_op == O_constant | |
3114 | || (ep->X_op == O_symbol | |
f6688943 TS |
3115 | && (*r == BFD_RELOC_MIPS_HIGHEST |
3116 | || *r == BFD_RELOC_HI16_S | |
3117 | || *r == BFD_RELOC_HI16 | |
3118 | || *r == BFD_RELOC_GPREL16 | |
3119 | || *r == BFD_RELOC_MIPS_GOT_HI16 | |
3e722fb5 | 3120 | || *r == BFD_RELOC_MIPS_CALL_HI16)))); |
252b5132 RH |
3121 | continue; |
3122 | ||
3123 | case 'p': | |
3124 | assert (ep != NULL); | |
3125 | /* | |
3126 | * This allows macro() to pass an immediate expression for | |
3127 | * creating short branches without creating a symbol. | |
0b25d3e6 AO |
3128 | * Note that the expression still might come from the assembly |
3129 | * input, in which case the value is not checked for range nor | |
3130 | * is a relocation entry generated (yuck). | |
252b5132 RH |
3131 | */ |
3132 | if (ep->X_op == O_constant) | |
3133 | { | |
3134 | insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff; | |
3135 | ep = NULL; | |
3136 | } | |
3137 | else | |
0b25d3e6 | 3138 | *r = BFD_RELOC_16_PCREL_S2; |
252b5132 RH |
3139 | continue; |
3140 | ||
3141 | case 'a': | |
3142 | assert (ep != NULL); | |
f6688943 | 3143 | *r = BFD_RELOC_MIPS_JMP; |
252b5132 RH |
3144 | continue; |
3145 | ||
3146 | case 'C': | |
3147 | insn.insn_opcode |= va_arg (args, unsigned long); | |
3148 | continue; | |
3149 | ||
3150 | default: | |
3151 | internalError (); | |
3152 | } | |
3153 | break; | |
3154 | } | |
3155 | va_end (args); | |
f6688943 | 3156 | assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
252b5132 | 3157 | |
4d7206a2 | 3158 | append_insn (&insn, ep, r); |
252b5132 RH |
3159 | } |
3160 | ||
3161 | static void | |
67c0d1eb | 3162 | mips16_macro_build (expressionS *ep, const char *name, const char *fmt, |
17a2f251 | 3163 | va_list args) |
252b5132 | 3164 | { |
1e915849 | 3165 | struct mips_opcode *mo; |
252b5132 | 3166 | struct mips_cl_insn insn; |
f6688943 TS |
3167 | bfd_reloc_code_real_type r[3] |
3168 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 3169 | |
1e915849 RS |
3170 | mo = (struct mips_opcode *) hash_find (mips16_op_hash, name); |
3171 | assert (mo); | |
3172 | assert (strcmp (name, mo->name) == 0); | |
252b5132 | 3173 | |
1e915849 | 3174 | while (strcmp (fmt, mo->args) != 0 || mo->pinfo == INSN_MACRO) |
252b5132 | 3175 | { |
1e915849 RS |
3176 | ++mo; |
3177 | assert (mo->name); | |
3178 | assert (strcmp (name, mo->name) == 0); | |
252b5132 RH |
3179 | } |
3180 | ||
1e915849 | 3181 | create_insn (&insn, mo); |
252b5132 RH |
3182 | for (;;) |
3183 | { | |
3184 | int c; | |
3185 | ||
3186 | c = *fmt++; | |
3187 | switch (c) | |
3188 | { | |
3189 | case '\0': | |
3190 | break; | |
3191 | ||
3192 | case ',': | |
3193 | case '(': | |
3194 | case ')': | |
3195 | continue; | |
3196 | ||
3197 | case 'y': | |
3198 | case 'w': | |
bf12938e | 3199 | MIPS16_INSERT_OPERAND (RY, insn, va_arg (args, int)); |
252b5132 RH |
3200 | continue; |
3201 | ||
3202 | case 'x': | |
3203 | case 'v': | |
bf12938e | 3204 | MIPS16_INSERT_OPERAND (RX, insn, va_arg (args, int)); |
252b5132 RH |
3205 | continue; |
3206 | ||
3207 | case 'z': | |
bf12938e | 3208 | MIPS16_INSERT_OPERAND (RZ, insn, va_arg (args, int)); |
252b5132 RH |
3209 | continue; |
3210 | ||
3211 | case 'Z': | |
bf12938e | 3212 | MIPS16_INSERT_OPERAND (MOVE32Z, insn, va_arg (args, int)); |
252b5132 RH |
3213 | continue; |
3214 | ||
3215 | case '0': | |
3216 | case 'S': | |
3217 | case 'P': | |
3218 | case 'R': | |
3219 | continue; | |
3220 | ||
3221 | case 'X': | |
bf12938e | 3222 | MIPS16_INSERT_OPERAND (REGR32, insn, va_arg (args, int)); |
252b5132 RH |
3223 | continue; |
3224 | ||
3225 | case 'Y': | |
3226 | { | |
3227 | int regno; | |
3228 | ||
3229 | regno = va_arg (args, int); | |
3230 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); | |
3231 | insn.insn_opcode |= regno << MIPS16OP_SH_REG32R; | |
3232 | } | |
3233 | continue; | |
3234 | ||
3235 | case '<': | |
3236 | case '>': | |
3237 | case '4': | |
3238 | case '5': | |
3239 | case 'H': | |
3240 | case 'W': | |
3241 | case 'D': | |
3242 | case 'j': | |
3243 | case '8': | |
3244 | case 'V': | |
3245 | case 'C': | |
3246 | case 'U': | |
3247 | case 'k': | |
3248 | case 'K': | |
3249 | case 'p': | |
3250 | case 'q': | |
3251 | { | |
3252 | assert (ep != NULL); | |
3253 | ||
3254 | if (ep->X_op != O_constant) | |
874e8986 | 3255 | *r = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
3256 | else |
3257 | { | |
b34976b6 AM |
3258 | mips16_immed (NULL, 0, c, ep->X_add_number, FALSE, FALSE, |
3259 | FALSE, &insn.insn_opcode, &insn.use_extend, | |
c4e7957c | 3260 | &insn.extend); |
252b5132 | 3261 | ep = NULL; |
f6688943 | 3262 | *r = BFD_RELOC_UNUSED; |
252b5132 RH |
3263 | } |
3264 | } | |
3265 | continue; | |
3266 | ||
3267 | case '6': | |
bf12938e | 3268 | MIPS16_INSERT_OPERAND (IMM6, insn, va_arg (args, int)); |
252b5132 RH |
3269 | continue; |
3270 | } | |
3271 | ||
3272 | break; | |
3273 | } | |
3274 | ||
f6688943 | 3275 | assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
252b5132 | 3276 | |
4d7206a2 | 3277 | append_insn (&insn, ep, r); |
252b5132 RH |
3278 | } |
3279 | ||
2051e8c4 MR |
3280 | /* |
3281 | * Sign-extend 32-bit mode constants that have bit 31 set and all | |
3282 | * higher bits unset. | |
3283 | */ | |
9f872bbe | 3284 | static void |
2051e8c4 MR |
3285 | normalize_constant_expr (expressionS *ex) |
3286 | { | |
9ee2a2d4 | 3287 | if (ex->X_op == O_constant |
2051e8c4 MR |
3288 | && IS_ZEXT_32BIT_NUM (ex->X_add_number)) |
3289 | ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000) | |
3290 | - 0x80000000); | |
3291 | } | |
3292 | ||
3293 | /* | |
3294 | * Sign-extend 32-bit mode address offsets that have bit 31 set and | |
3295 | * all higher bits unset. | |
3296 | */ | |
3297 | static void | |
3298 | normalize_address_expr (expressionS *ex) | |
3299 | { | |
3300 | if (((ex->X_op == O_constant && HAVE_32BIT_ADDRESSES) | |
3301 | || (ex->X_op == O_symbol && HAVE_32BIT_SYMBOLS)) | |
3302 | && IS_ZEXT_32BIT_NUM (ex->X_add_number)) | |
3303 | ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000) | |
3304 | - 0x80000000); | |
3305 | } | |
3306 | ||
438c16b8 TS |
3307 | /* |
3308 | * Generate a "jalr" instruction with a relocation hint to the called | |
3309 | * function. This occurs in NewABI PIC code. | |
3310 | */ | |
3311 | static void | |
67c0d1eb | 3312 | macro_build_jalr (expressionS *ep) |
438c16b8 | 3313 | { |
685736be | 3314 | char *f = NULL; |
b34976b6 | 3315 | |
438c16b8 | 3316 | if (HAVE_NEWABI) |
f21f8242 | 3317 | { |
cc3d92a5 | 3318 | frag_grow (8); |
f21f8242 AO |
3319 | f = frag_more (0); |
3320 | } | |
67c0d1eb | 3321 | macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG); |
438c16b8 | 3322 | if (HAVE_NEWABI) |
f21f8242 | 3323 | fix_new_exp (frag_now, f - frag_now->fr_literal, |
a105a300 | 3324 | 4, ep, FALSE, BFD_RELOC_MIPS_JALR); |
438c16b8 TS |
3325 | } |
3326 | ||
252b5132 RH |
3327 | /* |
3328 | * Generate a "lui" instruction. | |
3329 | */ | |
3330 | static void | |
67c0d1eb | 3331 | macro_build_lui (expressionS *ep, int regnum) |
252b5132 RH |
3332 | { |
3333 | expressionS high_expr; | |
1e915849 | 3334 | const struct mips_opcode *mo; |
252b5132 | 3335 | struct mips_cl_insn insn; |
f6688943 TS |
3336 | bfd_reloc_code_real_type r[3] |
3337 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
5a38dc70 AM |
3338 | const char *name = "lui"; |
3339 | const char *fmt = "t,u"; | |
252b5132 RH |
3340 | |
3341 | assert (! mips_opts.mips16); | |
3342 | ||
4d7206a2 | 3343 | high_expr = *ep; |
252b5132 RH |
3344 | |
3345 | if (high_expr.X_op == O_constant) | |
3346 | { | |
3347 | /* we can compute the instruction now without a relocation entry */ | |
e7d556df TS |
3348 | high_expr.X_add_number = ((high_expr.X_add_number + 0x8000) |
3349 | >> 16) & 0xffff; | |
f6688943 | 3350 | *r = BFD_RELOC_UNUSED; |
252b5132 | 3351 | } |
78e1bb40 | 3352 | else |
252b5132 RH |
3353 | { |
3354 | assert (ep->X_op == O_symbol); | |
bbe506e8 TS |
3355 | /* _gp_disp is a special case, used from s_cpload. |
3356 | __gnu_local_gp is used if mips_no_shared. */ | |
252b5132 | 3357 | assert (mips_pic == NO_PIC |
78e1bb40 | 3358 | || (! HAVE_NEWABI |
aa6975fb ILT |
3359 | && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0) |
3360 | || (! mips_in_shared | |
bbe506e8 TS |
3361 | && strcmp (S_GET_NAME (ep->X_add_symbol), |
3362 | "__gnu_local_gp") == 0)); | |
f6688943 | 3363 | *r = BFD_RELOC_HI16_S; |
252b5132 RH |
3364 | } |
3365 | ||
1e915849 RS |
3366 | mo = hash_find (op_hash, name); |
3367 | assert (strcmp (name, mo->name) == 0); | |
3368 | assert (strcmp (fmt, mo->args) == 0); | |
3369 | create_insn (&insn, mo); | |
252b5132 | 3370 | |
bf12938e RS |
3371 | insn.insn_opcode = insn.insn_mo->match; |
3372 | INSERT_OPERAND (RT, insn, regnum); | |
f6688943 | 3373 | if (*r == BFD_RELOC_UNUSED) |
252b5132 RH |
3374 | { |
3375 | insn.insn_opcode |= high_expr.X_add_number; | |
4d7206a2 | 3376 | append_insn (&insn, NULL, r); |
252b5132 RH |
3377 | } |
3378 | else | |
4d7206a2 | 3379 | append_insn (&insn, &high_expr, r); |
252b5132 RH |
3380 | } |
3381 | ||
885add95 CD |
3382 | /* Generate a sequence of instructions to do a load or store from a constant |
3383 | offset off of a base register (breg) into/from a target register (treg), | |
3384 | using AT if necessary. */ | |
3385 | static void | |
67c0d1eb RS |
3386 | macro_build_ldst_constoffset (expressionS *ep, const char *op, |
3387 | int treg, int breg, int dbl) | |
885add95 CD |
3388 | { |
3389 | assert (ep->X_op == O_constant); | |
3390 | ||
256ab948 | 3391 | /* Sign-extending 32-bit constants makes their handling easier. */ |
2051e8c4 MR |
3392 | if (!dbl) |
3393 | normalize_constant_expr (ep); | |
256ab948 | 3394 | |
67c1ffbe | 3395 | /* Right now, this routine can only handle signed 32-bit constants. */ |
ecd13cd3 | 3396 | if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000)) |
885add95 CD |
3397 | as_warn (_("operand overflow")); |
3398 | ||
3399 | if (IS_SEXT_16BIT_NUM(ep->X_add_number)) | |
3400 | { | |
3401 | /* Signed 16-bit offset will fit in the op. Easy! */ | |
67c0d1eb | 3402 | macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
885add95 CD |
3403 | } |
3404 | else | |
3405 | { | |
3406 | /* 32-bit offset, need multiple instructions and AT, like: | |
3407 | lui $tempreg,const_hi (BFD_RELOC_HI16_S) | |
3408 | addu $tempreg,$tempreg,$breg | |
3409 | <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16) | |
3410 | to handle the complete offset. */ | |
67c0d1eb RS |
3411 | macro_build_lui (ep, AT); |
3412 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); | |
3413 | macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, AT); | |
885add95 CD |
3414 | |
3415 | if (mips_opts.noat) | |
8fc2e39e | 3416 | as_bad (_("Macro used $at after \".set noat\"")); |
885add95 CD |
3417 | } |
3418 | } | |
3419 | ||
252b5132 RH |
3420 | /* set_at() |
3421 | * Generates code to set the $at register to true (one) | |
3422 | * if reg is less than the immediate expression. | |
3423 | */ | |
3424 | static void | |
67c0d1eb | 3425 | set_at (int reg, int unsignedp) |
252b5132 RH |
3426 | { |
3427 | if (imm_expr.X_op == O_constant | |
3428 | && imm_expr.X_add_number >= -0x8000 | |
3429 | && imm_expr.X_add_number < 0x8000) | |
67c0d1eb RS |
3430 | macro_build (&imm_expr, unsignedp ? "sltiu" : "slti", "t,r,j", |
3431 | AT, reg, BFD_RELOC_LO16); | |
252b5132 RH |
3432 | else |
3433 | { | |
67c0d1eb RS |
3434 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
3435 | macro_build (NULL, unsignedp ? "sltu" : "slt", "d,v,t", AT, reg, AT); | |
252b5132 RH |
3436 | } |
3437 | } | |
3438 | ||
3439 | /* Warn if an expression is not a constant. */ | |
3440 | ||
3441 | static void | |
17a2f251 | 3442 | check_absolute_expr (struct mips_cl_insn *ip, expressionS *ex) |
252b5132 RH |
3443 | { |
3444 | if (ex->X_op == O_big) | |
3445 | as_bad (_("unsupported large constant")); | |
3446 | else if (ex->X_op != O_constant) | |
9ee2a2d4 MR |
3447 | as_bad (_("Instruction %s requires absolute expression"), |
3448 | ip->insn_mo->name); | |
13757d0c | 3449 | |
9ee2a2d4 MR |
3450 | if (HAVE_32BIT_GPRS) |
3451 | normalize_constant_expr (ex); | |
252b5132 RH |
3452 | } |
3453 | ||
3454 | /* Count the leading zeroes by performing a binary chop. This is a | |
3455 | bulky bit of source, but performance is a LOT better for the | |
3456 | majority of values than a simple loop to count the bits: | |
3457 | for (lcnt = 0; (lcnt < 32); lcnt++) | |
3458 | if ((v) & (1 << (31 - lcnt))) | |
3459 | break; | |
3460 | However it is not code size friendly, and the gain will drop a bit | |
3461 | on certain cached systems. | |
3462 | */ | |
3463 | #define COUNT_TOP_ZEROES(v) \ | |
3464 | (((v) & ~0xffff) == 0 \ | |
3465 | ? ((v) & ~0xff) == 0 \ | |
3466 | ? ((v) & ~0xf) == 0 \ | |
3467 | ? ((v) & ~0x3) == 0 \ | |
3468 | ? ((v) & ~0x1) == 0 \ | |
3469 | ? !(v) \ | |
3470 | ? 32 \ | |
3471 | : 31 \ | |
3472 | : 30 \ | |
3473 | : ((v) & ~0x7) == 0 \ | |
3474 | ? 29 \ | |
3475 | : 28 \ | |
3476 | : ((v) & ~0x3f) == 0 \ | |
3477 | ? ((v) & ~0x1f) == 0 \ | |
3478 | ? 27 \ | |
3479 | : 26 \ | |
3480 | : ((v) & ~0x7f) == 0 \ | |
3481 | ? 25 \ | |
3482 | : 24 \ | |
3483 | : ((v) & ~0xfff) == 0 \ | |
3484 | ? ((v) & ~0x3ff) == 0 \ | |
3485 | ? ((v) & ~0x1ff) == 0 \ | |
3486 | ? 23 \ | |
3487 | : 22 \ | |
3488 | : ((v) & ~0x7ff) == 0 \ | |
3489 | ? 21 \ | |
3490 | : 20 \ | |
3491 | : ((v) & ~0x3fff) == 0 \ | |
3492 | ? ((v) & ~0x1fff) == 0 \ | |
3493 | ? 19 \ | |
3494 | : 18 \ | |
3495 | : ((v) & ~0x7fff) == 0 \ | |
3496 | ? 17 \ | |
3497 | : 16 \ | |
3498 | : ((v) & ~0xffffff) == 0 \ | |
3499 | ? ((v) & ~0xfffff) == 0 \ | |
3500 | ? ((v) & ~0x3ffff) == 0 \ | |
3501 | ? ((v) & ~0x1ffff) == 0 \ | |
3502 | ? 15 \ | |
3503 | : 14 \ | |
3504 | : ((v) & ~0x7ffff) == 0 \ | |
3505 | ? 13 \ | |
3506 | : 12 \ | |
3507 | : ((v) & ~0x3fffff) == 0 \ | |
3508 | ? ((v) & ~0x1fffff) == 0 \ | |
3509 | ? 11 \ | |
3510 | : 10 \ | |
3511 | : ((v) & ~0x7fffff) == 0 \ | |
3512 | ? 9 \ | |
3513 | : 8 \ | |
3514 | : ((v) & ~0xfffffff) == 0 \ | |
3515 | ? ((v) & ~0x3ffffff) == 0 \ | |
3516 | ? ((v) & ~0x1ffffff) == 0 \ | |
3517 | ? 7 \ | |
3518 | : 6 \ | |
3519 | : ((v) & ~0x7ffffff) == 0 \ | |
3520 | ? 5 \ | |
3521 | : 4 \ | |
3522 | : ((v) & ~0x3fffffff) == 0 \ | |
3523 | ? ((v) & ~0x1fffffff) == 0 \ | |
3524 | ? 3 \ | |
3525 | : 2 \ | |
3526 | : ((v) & ~0x7fffffff) == 0 \ | |
3527 | ? 1 \ | |
3528 | : 0) | |
3529 | ||
3530 | /* load_register() | |
67c1ffbe | 3531 | * This routine generates the least number of instructions necessary to load |
252b5132 RH |
3532 | * an absolute expression value into a register. |
3533 | */ | |
3534 | static void | |
67c0d1eb | 3535 | load_register (int reg, expressionS *ep, int dbl) |
252b5132 RH |
3536 | { |
3537 | int freg; | |
3538 | expressionS hi32, lo32; | |
3539 | ||
3540 | if (ep->X_op != O_big) | |
3541 | { | |
3542 | assert (ep->X_op == O_constant); | |
256ab948 TS |
3543 | |
3544 | /* Sign-extending 32-bit constants makes their handling easier. */ | |
2051e8c4 MR |
3545 | if (!dbl) |
3546 | normalize_constant_expr (ep); | |
256ab948 TS |
3547 | |
3548 | if (IS_SEXT_16BIT_NUM (ep->X_add_number)) | |
252b5132 RH |
3549 | { |
3550 | /* We can handle 16 bit signed values with an addiu to | |
3551 | $zero. No need to ever use daddiu here, since $zero and | |
3552 | the result are always correct in 32 bit mode. */ | |
67c0d1eb | 3553 | macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
3554 | return; |
3555 | } | |
3556 | else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000) | |
3557 | { | |
3558 | /* We can handle 16 bit unsigned values with an ori to | |
3559 | $zero. */ | |
67c0d1eb | 3560 | macro_build (ep, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
3561 | return; |
3562 | } | |
256ab948 | 3563 | else if ((IS_SEXT_32BIT_NUM (ep->X_add_number))) |
252b5132 RH |
3564 | { |
3565 | /* 32 bit values require an lui. */ | |
67c0d1eb | 3566 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_HI16); |
252b5132 | 3567 | if ((ep->X_add_number & 0xffff) != 0) |
67c0d1eb | 3568 | macro_build (ep, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16); |
252b5132 RH |
3569 | return; |
3570 | } | |
3571 | } | |
3572 | ||
3573 | /* The value is larger than 32 bits. */ | |
3574 | ||
2051e8c4 | 3575 | if (!dbl || HAVE_32BIT_GPRS) |
252b5132 | 3576 | { |
55e08f71 NC |
3577 | char value[32]; |
3578 | ||
3579 | sprintf_vma (value, ep->X_add_number); | |
20e1fcfd | 3580 | as_bad (_("Number (0x%s) larger than 32 bits"), value); |
67c0d1eb | 3581 | macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
3582 | return; |
3583 | } | |
3584 | ||
3585 | if (ep->X_op != O_big) | |
3586 | { | |
3587 | hi32 = *ep; | |
3588 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
3589 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
3590 | hi32.X_add_number &= 0xffffffff; | |
3591 | lo32 = *ep; | |
3592 | lo32.X_add_number &= 0xffffffff; | |
3593 | } | |
3594 | else | |
3595 | { | |
3596 | assert (ep->X_add_number > 2); | |
3597 | if (ep->X_add_number == 3) | |
3598 | generic_bignum[3] = 0; | |
3599 | else if (ep->X_add_number > 4) | |
3600 | as_bad (_("Number larger than 64 bits")); | |
3601 | lo32.X_op = O_constant; | |
3602 | lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16); | |
3603 | hi32.X_op = O_constant; | |
3604 | hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16); | |
3605 | } | |
3606 | ||
3607 | if (hi32.X_add_number == 0) | |
3608 | freg = 0; | |
3609 | else | |
3610 | { | |
3611 | int shift, bit; | |
3612 | unsigned long hi, lo; | |
3613 | ||
956cd1d6 | 3614 | if (hi32.X_add_number == (offsetT) 0xffffffff) |
beae10d5 KH |
3615 | { |
3616 | if ((lo32.X_add_number & 0xffff8000) == 0xffff8000) | |
3617 | { | |
67c0d1eb | 3618 | macro_build (&lo32, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
beae10d5 KH |
3619 | return; |
3620 | } | |
3621 | if (lo32.X_add_number & 0x80000000) | |
3622 | { | |
67c0d1eb | 3623 | macro_build (&lo32, "lui", "t,u", reg, BFD_RELOC_HI16); |
252b5132 | 3624 | if (lo32.X_add_number & 0xffff) |
67c0d1eb | 3625 | macro_build (&lo32, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16); |
beae10d5 KH |
3626 | return; |
3627 | } | |
3628 | } | |
252b5132 RH |
3629 | |
3630 | /* Check for 16bit shifted constant. We know that hi32 is | |
3631 | non-zero, so start the mask on the first bit of the hi32 | |
3632 | value. */ | |
3633 | shift = 17; | |
3634 | do | |
beae10d5 KH |
3635 | { |
3636 | unsigned long himask, lomask; | |
3637 | ||
3638 | if (shift < 32) | |
3639 | { | |
3640 | himask = 0xffff >> (32 - shift); | |
3641 | lomask = (0xffff << shift) & 0xffffffff; | |
3642 | } | |
3643 | else | |
3644 | { | |
3645 | himask = 0xffff << (shift - 32); | |
3646 | lomask = 0; | |
3647 | } | |
3648 | if ((hi32.X_add_number & ~(offsetT) himask) == 0 | |
3649 | && (lo32.X_add_number & ~(offsetT) lomask) == 0) | |
3650 | { | |
3651 | expressionS tmp; | |
3652 | ||
3653 | tmp.X_op = O_constant; | |
3654 | if (shift < 32) | |
3655 | tmp.X_add_number = ((hi32.X_add_number << (32 - shift)) | |
3656 | | (lo32.X_add_number >> shift)); | |
3657 | else | |
3658 | tmp.X_add_number = hi32.X_add_number >> (shift - 32); | |
67c0d1eb RS |
3659 | macro_build (&tmp, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16); |
3660 | macro_build (NULL, (shift >= 32) ? "dsll32" : "dsll", "d,w,<", | |
3661 | reg, reg, (shift >= 32) ? shift - 32 : shift); | |
beae10d5 KH |
3662 | return; |
3663 | } | |
f9419b05 | 3664 | ++shift; |
beae10d5 KH |
3665 | } |
3666 | while (shift <= (64 - 16)); | |
252b5132 RH |
3667 | |
3668 | /* Find the bit number of the lowest one bit, and store the | |
3669 | shifted value in hi/lo. */ | |
3670 | hi = (unsigned long) (hi32.X_add_number & 0xffffffff); | |
3671 | lo = (unsigned long) (lo32.X_add_number & 0xffffffff); | |
3672 | if (lo != 0) | |
3673 | { | |
3674 | bit = 0; | |
3675 | while ((lo & 1) == 0) | |
3676 | { | |
3677 | lo >>= 1; | |
3678 | ++bit; | |
3679 | } | |
3680 | lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit); | |
3681 | hi >>= bit; | |
3682 | } | |
3683 | else | |
3684 | { | |
3685 | bit = 32; | |
3686 | while ((hi & 1) == 0) | |
3687 | { | |
3688 | hi >>= 1; | |
3689 | ++bit; | |
3690 | } | |
3691 | lo = hi; | |
3692 | hi = 0; | |
3693 | } | |
3694 | ||
3695 | /* Optimize if the shifted value is a (power of 2) - 1. */ | |
3696 | if ((hi == 0 && ((lo + 1) & lo) == 0) | |
3697 | || (lo == 0xffffffff && ((hi + 1) & hi) == 0)) | |
beae10d5 KH |
3698 | { |
3699 | shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number); | |
252b5132 | 3700 | if (shift != 0) |
beae10d5 | 3701 | { |
252b5132 RH |
3702 | expressionS tmp; |
3703 | ||
3704 | /* This instruction will set the register to be all | |
3705 | ones. */ | |
beae10d5 KH |
3706 | tmp.X_op = O_constant; |
3707 | tmp.X_add_number = (offsetT) -1; | |
67c0d1eb | 3708 | macro_build (&tmp, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
beae10d5 KH |
3709 | if (bit != 0) |
3710 | { | |
3711 | bit += shift; | |
67c0d1eb RS |
3712 | macro_build (NULL, (bit >= 32) ? "dsll32" : "dsll", "d,w,<", |
3713 | reg, reg, (bit >= 32) ? bit - 32 : bit); | |
beae10d5 | 3714 | } |
67c0d1eb RS |
3715 | macro_build (NULL, (shift >= 32) ? "dsrl32" : "dsrl", "d,w,<", |
3716 | reg, reg, (shift >= 32) ? shift - 32 : shift); | |
beae10d5 KH |
3717 | return; |
3718 | } | |
3719 | } | |
252b5132 RH |
3720 | |
3721 | /* Sign extend hi32 before calling load_register, because we can | |
3722 | generally get better code when we load a sign extended value. */ | |
3723 | if ((hi32.X_add_number & 0x80000000) != 0) | |
beae10d5 | 3724 | hi32.X_add_number |= ~(offsetT) 0xffffffff; |
67c0d1eb | 3725 | load_register (reg, &hi32, 0); |
252b5132 RH |
3726 | freg = reg; |
3727 | } | |
3728 | if ((lo32.X_add_number & 0xffff0000) == 0) | |
3729 | { | |
3730 | if (freg != 0) | |
3731 | { | |
67c0d1eb | 3732 | macro_build (NULL, "dsll32", "d,w,<", reg, freg, 0); |
252b5132 RH |
3733 | freg = reg; |
3734 | } | |
3735 | } | |
3736 | else | |
3737 | { | |
3738 | expressionS mid16; | |
3739 | ||
956cd1d6 | 3740 | if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff)) |
beae10d5 | 3741 | { |
67c0d1eb RS |
3742 | macro_build (&lo32, "lui", "t,u", reg, BFD_RELOC_HI16); |
3743 | macro_build (NULL, "dsrl32", "d,w,<", reg, reg, 0); | |
beae10d5 KH |
3744 | return; |
3745 | } | |
252b5132 RH |
3746 | |
3747 | if (freg != 0) | |
3748 | { | |
67c0d1eb | 3749 | macro_build (NULL, "dsll", "d,w,<", reg, freg, 16); |
252b5132 RH |
3750 | freg = reg; |
3751 | } | |
3752 | mid16 = lo32; | |
3753 | mid16.X_add_number >>= 16; | |
67c0d1eb RS |
3754 | macro_build (&mid16, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16); |
3755 | macro_build (NULL, "dsll", "d,w,<", reg, reg, 16); | |
252b5132 RH |
3756 | freg = reg; |
3757 | } | |
3758 | if ((lo32.X_add_number & 0xffff) != 0) | |
67c0d1eb | 3759 | macro_build (&lo32, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16); |
252b5132 RH |
3760 | } |
3761 | ||
269137b2 TS |
3762 | static inline void |
3763 | load_delay_nop (void) | |
3764 | { | |
3765 | if (!gpr_interlocks) | |
3766 | macro_build (NULL, "nop", ""); | |
3767 | } | |
3768 | ||
252b5132 RH |
3769 | /* Load an address into a register. */ |
3770 | ||
3771 | static void | |
67c0d1eb | 3772 | load_address (int reg, expressionS *ep, int *used_at) |
252b5132 | 3773 | { |
252b5132 RH |
3774 | if (ep->X_op != O_constant |
3775 | && ep->X_op != O_symbol) | |
3776 | { | |
3777 | as_bad (_("expression too complex")); | |
3778 | ep->X_op = O_constant; | |
3779 | } | |
3780 | ||
3781 | if (ep->X_op == O_constant) | |
3782 | { | |
67c0d1eb | 3783 | load_register (reg, ep, HAVE_64BIT_ADDRESSES); |
252b5132 RH |
3784 | return; |
3785 | } | |
3786 | ||
3787 | if (mips_pic == NO_PIC) | |
3788 | { | |
3789 | /* If this is a reference to a GP relative symbol, we want | |
cdf6fd85 | 3790 | addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
3791 | Otherwise we want |
3792 | lui $reg,<sym> (BFD_RELOC_HI16_S) | |
3793 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
d6bc6245 | 3794 | If we have an addend, we always use the latter form. |
76b3015f | 3795 | |
d6bc6245 TS |
3796 | With 64bit address space and a usable $at we want |
3797 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
3798 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
3799 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
3800 | daddiu $at,<sym> (BFD_RELOC_LO16) | |
3801 | dsll32 $reg,0 | |
3a482fd5 | 3802 | daddu $reg,$reg,$at |
76b3015f | 3803 | |
c03099e6 | 3804 | If $at is already in use, we use a path which is suboptimal |
d6bc6245 TS |
3805 | on superscalar processors. |
3806 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
3807 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
3808 | dsll $reg,16 | |
3809 | daddiu $reg,<sym> (BFD_RELOC_HI16_S) | |
3810 | dsll $reg,16 | |
3811 | daddiu $reg,<sym> (BFD_RELOC_LO16) | |
6caf9ef4 TS |
3812 | |
3813 | For GP relative symbols in 64bit address space we can use | |
3814 | the same sequence as in 32bit address space. */ | |
aed1a261 | 3815 | if (HAVE_64BIT_SYMBOLS) |
d6bc6245 | 3816 | { |
6caf9ef4 TS |
3817 | if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET |
3818 | && !nopic_need_relax (ep->X_add_symbol, 1)) | |
3819 | { | |
3820 | relax_start (ep->X_add_symbol); | |
3821 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, | |
3822 | mips_gp_register, BFD_RELOC_GPREL16); | |
3823 | relax_switch (); | |
3824 | } | |
d6bc6245 | 3825 | |
b8285c27 | 3826 | if (*used_at == 0 && !mips_opts.noat) |
d6bc6245 | 3827 | { |
67c0d1eb RS |
3828 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_HIGHEST); |
3829 | macro_build (ep, "lui", "t,u", AT, BFD_RELOC_HI16_S); | |
3830 | macro_build (ep, "daddiu", "t,r,j", reg, reg, | |
3831 | BFD_RELOC_MIPS_HIGHER); | |
3832 | macro_build (ep, "daddiu", "t,r,j", AT, AT, BFD_RELOC_LO16); | |
3833 | macro_build (NULL, "dsll32", "d,w,<", reg, reg, 0); | |
3834 | macro_build (NULL, "daddu", "d,v,t", reg, reg, AT); | |
d6bc6245 TS |
3835 | *used_at = 1; |
3836 | } | |
3837 | else | |
3838 | { | |
67c0d1eb RS |
3839 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_HIGHEST); |
3840 | macro_build (ep, "daddiu", "t,r,j", reg, reg, | |
3841 | BFD_RELOC_MIPS_HIGHER); | |
3842 | macro_build (NULL, "dsll", "d,w,<", reg, reg, 16); | |
3843 | macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_HI16_S); | |
3844 | macro_build (NULL, "dsll", "d,w,<", reg, reg, 16); | |
3845 | macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_LO16); | |
d6bc6245 | 3846 | } |
6caf9ef4 TS |
3847 | |
3848 | if (mips_relax.sequence) | |
3849 | relax_end (); | |
d6bc6245 | 3850 | } |
252b5132 RH |
3851 | else |
3852 | { | |
d6bc6245 | 3853 | if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 3854 | && !nopic_need_relax (ep->X_add_symbol, 1)) |
d6bc6245 | 3855 | { |
4d7206a2 | 3856 | relax_start (ep->X_add_symbol); |
67c0d1eb | 3857 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, |
17a2f251 | 3858 | mips_gp_register, BFD_RELOC_GPREL16); |
4d7206a2 | 3859 | relax_switch (); |
d6bc6245 | 3860 | } |
67c0d1eb RS |
3861 | macro_build_lui (ep, reg); |
3862 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", | |
3863 | reg, reg, BFD_RELOC_LO16); | |
4d7206a2 RS |
3864 | if (mips_relax.sequence) |
3865 | relax_end (); | |
d6bc6245 | 3866 | } |
252b5132 RH |
3867 | } |
3868 | else if (mips_pic == SVR4_PIC && ! mips_big_got) | |
3869 | { | |
3870 | expressionS ex; | |
3871 | ||
3872 | /* If this is a reference to an external symbol, we want | |
3873 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3874 | Otherwise we want | |
3875 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3876 | nop | |
3877 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
f5040a92 AO |
3878 | If there is a constant, it must be added in after. |
3879 | ||
ed6fb7bd | 3880 | If we have NewABI, we want |
f5040a92 AO |
3881 | lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP) |
3882 | unless we're referencing a global symbol with a non-zero | |
3883 | offset, in which case cst must be added separately. */ | |
ed6fb7bd SC |
3884 | if (HAVE_NEWABI) |
3885 | { | |
f5040a92 AO |
3886 | if (ep->X_add_number) |
3887 | { | |
4d7206a2 | 3888 | ex.X_add_number = ep->X_add_number; |
f5040a92 | 3889 | ep->X_add_number = 0; |
4d7206a2 | 3890 | relax_start (ep->X_add_symbol); |
67c0d1eb RS |
3891 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
3892 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
3893 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) |
3894 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
3895 | ex.X_op = O_constant; | |
67c0d1eb | 3896 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 3897 | reg, reg, BFD_RELOC_LO16); |
f5040a92 | 3898 | ep->X_add_number = ex.X_add_number; |
4d7206a2 | 3899 | relax_switch (); |
f5040a92 | 3900 | } |
67c0d1eb | 3901 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 3902 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); |
4d7206a2 RS |
3903 | if (mips_relax.sequence) |
3904 | relax_end (); | |
ed6fb7bd SC |
3905 | } |
3906 | else | |
3907 | { | |
f5040a92 AO |
3908 | ex.X_add_number = ep->X_add_number; |
3909 | ep->X_add_number = 0; | |
67c0d1eb RS |
3910 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
3911 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 3912 | load_delay_nop (); |
4d7206a2 RS |
3913 | relax_start (ep->X_add_symbol); |
3914 | relax_switch (); | |
67c0d1eb | 3915 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
17a2f251 | 3916 | BFD_RELOC_LO16); |
4d7206a2 | 3917 | relax_end (); |
ed6fb7bd | 3918 | |
f5040a92 AO |
3919 | if (ex.X_add_number != 0) |
3920 | { | |
3921 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
3922 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
3923 | ex.X_op = O_constant; | |
67c0d1eb | 3924 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 3925 | reg, reg, BFD_RELOC_LO16); |
f5040a92 | 3926 | } |
252b5132 RH |
3927 | } |
3928 | } | |
3929 | else if (mips_pic == SVR4_PIC) | |
3930 | { | |
3931 | expressionS ex; | |
252b5132 RH |
3932 | |
3933 | /* This is the large GOT case. If this is a reference to an | |
3934 | external symbol, we want | |
3935 | lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
3936 | addu $reg,$reg,$gp | |
3937 | lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16) | |
f5040a92 AO |
3938 | |
3939 | Otherwise, for a reference to a local symbol in old ABI, we want | |
252b5132 RH |
3940 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) |
3941 | nop | |
3942 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
684022ea | 3943 | If there is a constant, it must be added in after. |
f5040a92 AO |
3944 | |
3945 | In the NewABI, for local symbols, with or without offsets, we want: | |
438c16b8 TS |
3946 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) |
3947 | addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) | |
f5040a92 | 3948 | */ |
438c16b8 TS |
3949 | if (HAVE_NEWABI) |
3950 | { | |
4d7206a2 | 3951 | ex.X_add_number = ep->X_add_number; |
f5040a92 | 3952 | ep->X_add_number = 0; |
4d7206a2 | 3953 | relax_start (ep->X_add_symbol); |
67c0d1eb RS |
3954 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_GOT_HI16); |
3955 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
3956 | reg, reg, mips_gp_register); | |
3957 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", | |
3958 | reg, BFD_RELOC_MIPS_GOT_LO16, reg); | |
f5040a92 AO |
3959 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) |
3960 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
3961 | else if (ex.X_add_number) | |
3962 | { | |
3963 | ex.X_op = O_constant; | |
67c0d1eb RS |
3964 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
3965 | BFD_RELOC_LO16); | |
f5040a92 AO |
3966 | } |
3967 | ||
3968 | ep->X_add_number = ex.X_add_number; | |
4d7206a2 | 3969 | relax_switch (); |
67c0d1eb | 3970 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 3971 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); |
67c0d1eb RS |
3972 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
3973 | BFD_RELOC_MIPS_GOT_OFST); | |
4d7206a2 | 3974 | relax_end (); |
438c16b8 | 3975 | } |
252b5132 | 3976 | else |
438c16b8 | 3977 | { |
f5040a92 AO |
3978 | ex.X_add_number = ep->X_add_number; |
3979 | ep->X_add_number = 0; | |
4d7206a2 | 3980 | relax_start (ep->X_add_symbol); |
67c0d1eb RS |
3981 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_GOT_HI16); |
3982 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
3983 | reg, reg, mips_gp_register); | |
3984 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", | |
3985 | reg, BFD_RELOC_MIPS_GOT_LO16, reg); | |
4d7206a2 RS |
3986 | relax_switch (); |
3987 | if (reg_needs_delay (mips_gp_register)) | |
438c16b8 TS |
3988 | { |
3989 | /* We need a nop before loading from $gp. This special | |
3990 | check is required because the lui which starts the main | |
3991 | instruction stream does not refer to $gp, and so will not | |
3992 | insert the nop which may be required. */ | |
67c0d1eb | 3993 | macro_build (NULL, "nop", ""); |
438c16b8 | 3994 | } |
67c0d1eb | 3995 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 3996 | BFD_RELOC_MIPS_GOT16, mips_gp_register); |
269137b2 | 3997 | load_delay_nop (); |
67c0d1eb | 3998 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
17a2f251 | 3999 | BFD_RELOC_LO16); |
4d7206a2 | 4000 | relax_end (); |
438c16b8 | 4001 | |
f5040a92 AO |
4002 | if (ex.X_add_number != 0) |
4003 | { | |
4004 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
4005 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4006 | ex.X_op = O_constant; | |
67c0d1eb RS |
4007 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
4008 | BFD_RELOC_LO16); | |
f5040a92 | 4009 | } |
252b5132 RH |
4010 | } |
4011 | } | |
252b5132 RH |
4012 | else |
4013 | abort (); | |
8fc2e39e TS |
4014 | |
4015 | if (mips_opts.noat && *used_at == 1) | |
4016 | as_bad (_("Macro used $at after \".set noat\"")); | |
252b5132 RH |
4017 | } |
4018 | ||
ea1fb5dc RS |
4019 | /* Move the contents of register SOURCE into register DEST. */ |
4020 | ||
4021 | static void | |
67c0d1eb | 4022 | move_register (int dest, int source) |
ea1fb5dc | 4023 | { |
67c0d1eb RS |
4024 | macro_build (NULL, HAVE_32BIT_GPRS ? "addu" : "daddu", "d,v,t", |
4025 | dest, source, 0); | |
ea1fb5dc RS |
4026 | } |
4027 | ||
4d7206a2 | 4028 | /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where |
f6a22291 MR |
4029 | LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement. |
4030 | The two alternatives are: | |
4d7206a2 RS |
4031 | |
4032 | Global symbol Local sybmol | |
4033 | ------------- ------------ | |
4034 | lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET) | |
4035 | ... ... | |
4036 | addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET) | |
4037 | ||
4038 | load_got_offset emits the first instruction and add_got_offset | |
f6a22291 MR |
4039 | emits the second for a 16-bit offset or add_got_offset_hilo emits |
4040 | a sequence to add a 32-bit offset using a scratch register. */ | |
4d7206a2 RS |
4041 | |
4042 | static void | |
67c0d1eb | 4043 | load_got_offset (int dest, expressionS *local) |
4d7206a2 RS |
4044 | { |
4045 | expressionS global; | |
4046 | ||
4047 | global = *local; | |
4048 | global.X_add_number = 0; | |
4049 | ||
4050 | relax_start (local->X_add_symbol); | |
67c0d1eb RS |
4051 | macro_build (&global, ADDRESS_LOAD_INSN, "t,o(b)", dest, |
4052 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
4d7206a2 | 4053 | relax_switch (); |
67c0d1eb RS |
4054 | macro_build (local, ADDRESS_LOAD_INSN, "t,o(b)", dest, |
4055 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
4d7206a2 RS |
4056 | relax_end (); |
4057 | } | |
4058 | ||
4059 | static void | |
67c0d1eb | 4060 | add_got_offset (int dest, expressionS *local) |
4d7206a2 RS |
4061 | { |
4062 | expressionS global; | |
4063 | ||
4064 | global.X_op = O_constant; | |
4065 | global.X_op_symbol = NULL; | |
4066 | global.X_add_symbol = NULL; | |
4067 | global.X_add_number = local->X_add_number; | |
4068 | ||
4069 | relax_start (local->X_add_symbol); | |
67c0d1eb | 4070 | macro_build (&global, ADDRESS_ADDI_INSN, "t,r,j", |
4d7206a2 RS |
4071 | dest, dest, BFD_RELOC_LO16); |
4072 | relax_switch (); | |
67c0d1eb | 4073 | macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", dest, dest, BFD_RELOC_LO16); |
4d7206a2 RS |
4074 | relax_end (); |
4075 | } | |
4076 | ||
f6a22291 MR |
4077 | static void |
4078 | add_got_offset_hilo (int dest, expressionS *local, int tmp) | |
4079 | { | |
4080 | expressionS global; | |
4081 | int hold_mips_optimize; | |
4082 | ||
4083 | global.X_op = O_constant; | |
4084 | global.X_op_symbol = NULL; | |
4085 | global.X_add_symbol = NULL; | |
4086 | global.X_add_number = local->X_add_number; | |
4087 | ||
4088 | relax_start (local->X_add_symbol); | |
4089 | load_register (tmp, &global, HAVE_64BIT_ADDRESSES); | |
4090 | relax_switch (); | |
4091 | /* Set mips_optimize around the lui instruction to avoid | |
4092 | inserting an unnecessary nop after the lw. */ | |
4093 | hold_mips_optimize = mips_optimize; | |
4094 | mips_optimize = 2; | |
4095 | macro_build_lui (&global, tmp); | |
4096 | mips_optimize = hold_mips_optimize; | |
4097 | macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", tmp, tmp, BFD_RELOC_LO16); | |
4098 | relax_end (); | |
4099 | ||
4100 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dest, dest, tmp); | |
4101 | } | |
4102 | ||
252b5132 RH |
4103 | /* |
4104 | * Build macros | |
4105 | * This routine implements the seemingly endless macro or synthesized | |
4106 | * instructions and addressing modes in the mips assembly language. Many | |
4107 | * of these macros are simple and are similar to each other. These could | |
67c1ffbe | 4108 | * probably be handled by some kind of table or grammar approach instead of |
252b5132 RH |
4109 | * this verbose method. Others are not simple macros but are more like |
4110 | * optimizing code generation. | |
4111 | * One interesting optimization is when several store macros appear | |
67c1ffbe | 4112 | * consecutively that would load AT with the upper half of the same address. |
252b5132 RH |
4113 | * The ensuing load upper instructions are ommited. This implies some kind |
4114 | * of global optimization. We currently only optimize within a single macro. | |
4115 | * For many of the load and store macros if the address is specified as a | |
4116 | * constant expression in the first 64k of memory (ie ld $2,0x4000c) we | |
4117 | * first load register 'at' with zero and use it as the base register. The | |
4118 | * mips assembler simply uses register $zero. Just one tiny optimization | |
4119 | * we're missing. | |
4120 | */ | |
4121 | static void | |
17a2f251 | 4122 | macro (struct mips_cl_insn *ip) |
252b5132 RH |
4123 | { |
4124 | register int treg, sreg, dreg, breg; | |
4125 | int tempreg; | |
4126 | int mask; | |
43841e91 | 4127 | int used_at = 0; |
252b5132 RH |
4128 | expressionS expr1; |
4129 | const char *s; | |
4130 | const char *s2; | |
4131 | const char *fmt; | |
4132 | int likely = 0; | |
4133 | int dbl = 0; | |
4134 | int coproc = 0; | |
4135 | int lr = 0; | |
4136 | int imm = 0; | |
1abe91b1 | 4137 | int call = 0; |
252b5132 | 4138 | int off; |
67c0d1eb | 4139 | offsetT maxnum; |
252b5132 | 4140 | bfd_reloc_code_real_type r; |
252b5132 RH |
4141 | int hold_mips_optimize; |
4142 | ||
4143 | assert (! mips_opts.mips16); | |
4144 | ||
4145 | treg = (ip->insn_opcode >> 16) & 0x1f; | |
4146 | dreg = (ip->insn_opcode >> 11) & 0x1f; | |
4147 | sreg = breg = (ip->insn_opcode >> 21) & 0x1f; | |
4148 | mask = ip->insn_mo->mask; | |
4149 | ||
4150 | expr1.X_op = O_constant; | |
4151 | expr1.X_op_symbol = NULL; | |
4152 | expr1.X_add_symbol = NULL; | |
4153 | expr1.X_add_number = 1; | |
4154 | ||
4155 | switch (mask) | |
4156 | { | |
4157 | case M_DABS: | |
4158 | dbl = 1; | |
4159 | case M_ABS: | |
4160 | /* bgez $a0,.+12 | |
4161 | move v0,$a0 | |
4162 | sub v0,$zero,$a0 | |
4163 | */ | |
4164 | ||
7d10b47d | 4165 | start_noreorder (); |
252b5132 RH |
4166 | |
4167 | expr1.X_add_number = 8; | |
67c0d1eb | 4168 | macro_build (&expr1, "bgez", "s,p", sreg); |
252b5132 | 4169 | if (dreg == sreg) |
67c0d1eb | 4170 | macro_build (NULL, "nop", "", 0); |
252b5132 | 4171 | else |
67c0d1eb RS |
4172 | move_register (dreg, sreg); |
4173 | macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, 0, sreg); | |
252b5132 | 4174 | |
7d10b47d | 4175 | end_noreorder (); |
8fc2e39e | 4176 | break; |
252b5132 RH |
4177 | |
4178 | case M_ADD_I: | |
4179 | s = "addi"; | |
4180 | s2 = "add"; | |
4181 | goto do_addi; | |
4182 | case M_ADDU_I: | |
4183 | s = "addiu"; | |
4184 | s2 = "addu"; | |
4185 | goto do_addi; | |
4186 | case M_DADD_I: | |
4187 | dbl = 1; | |
4188 | s = "daddi"; | |
4189 | s2 = "dadd"; | |
4190 | goto do_addi; | |
4191 | case M_DADDU_I: | |
4192 | dbl = 1; | |
4193 | s = "daddiu"; | |
4194 | s2 = "daddu"; | |
4195 | do_addi: | |
4196 | if (imm_expr.X_op == O_constant | |
4197 | && imm_expr.X_add_number >= -0x8000 | |
4198 | && imm_expr.X_add_number < 0x8000) | |
4199 | { | |
67c0d1eb | 4200 | macro_build (&imm_expr, s, "t,r,j", treg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 4201 | break; |
252b5132 | 4202 | } |
8fc2e39e | 4203 | used_at = 1; |
67c0d1eb RS |
4204 | load_register (AT, &imm_expr, dbl); |
4205 | macro_build (NULL, s2, "d,v,t", treg, sreg, AT); | |
252b5132 RH |
4206 | break; |
4207 | ||
4208 | case M_AND_I: | |
4209 | s = "andi"; | |
4210 | s2 = "and"; | |
4211 | goto do_bit; | |
4212 | case M_OR_I: | |
4213 | s = "ori"; | |
4214 | s2 = "or"; | |
4215 | goto do_bit; | |
4216 | case M_NOR_I: | |
4217 | s = ""; | |
4218 | s2 = "nor"; | |
4219 | goto do_bit; | |
4220 | case M_XOR_I: | |
4221 | s = "xori"; | |
4222 | s2 = "xor"; | |
4223 | do_bit: | |
4224 | if (imm_expr.X_op == O_constant | |
4225 | && imm_expr.X_add_number >= 0 | |
4226 | && imm_expr.X_add_number < 0x10000) | |
4227 | { | |
4228 | if (mask != M_NOR_I) | |
67c0d1eb | 4229 | macro_build (&imm_expr, s, "t,r,i", treg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
4230 | else |
4231 | { | |
67c0d1eb RS |
4232 | macro_build (&imm_expr, "ori", "t,r,i", |
4233 | treg, sreg, BFD_RELOC_LO16); | |
4234 | macro_build (NULL, "nor", "d,v,t", treg, treg, 0); | |
252b5132 | 4235 | } |
8fc2e39e | 4236 | break; |
252b5132 RH |
4237 | } |
4238 | ||
8fc2e39e | 4239 | used_at = 1; |
67c0d1eb RS |
4240 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
4241 | macro_build (NULL, s2, "d,v,t", treg, sreg, AT); | |
252b5132 RH |
4242 | break; |
4243 | ||
4244 | case M_BEQ_I: | |
4245 | s = "beq"; | |
4246 | goto beq_i; | |
4247 | case M_BEQL_I: | |
4248 | s = "beql"; | |
4249 | likely = 1; | |
4250 | goto beq_i; | |
4251 | case M_BNE_I: | |
4252 | s = "bne"; | |
4253 | goto beq_i; | |
4254 | case M_BNEL_I: | |
4255 | s = "bnel"; | |
4256 | likely = 1; | |
4257 | beq_i: | |
4258 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4259 | { | |
67c0d1eb | 4260 | macro_build (&offset_expr, s, "s,t,p", sreg, 0); |
8fc2e39e | 4261 | break; |
252b5132 | 4262 | } |
8fc2e39e | 4263 | used_at = 1; |
67c0d1eb RS |
4264 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
4265 | macro_build (&offset_expr, s, "s,t,p", sreg, AT); | |
252b5132 RH |
4266 | break; |
4267 | ||
4268 | case M_BGEL: | |
4269 | likely = 1; | |
4270 | case M_BGE: | |
4271 | if (treg == 0) | |
4272 | { | |
67c0d1eb | 4273 | macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", sreg); |
8fc2e39e | 4274 | break; |
252b5132 RH |
4275 | } |
4276 | if (sreg == 0) | |
4277 | { | |
67c0d1eb | 4278 | macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", treg); |
8fc2e39e | 4279 | break; |
252b5132 | 4280 | } |
8fc2e39e | 4281 | used_at = 1; |
67c0d1eb RS |
4282 | macro_build (NULL, "slt", "d,v,t", AT, sreg, treg); |
4283 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
4284 | break; |
4285 | ||
4286 | case M_BGTL_I: | |
4287 | likely = 1; | |
4288 | case M_BGT_I: | |
4289 | /* check for > max integer */ | |
4290 | maxnum = 0x7fffffff; | |
ca4e0257 | 4291 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
4292 | { |
4293 | maxnum <<= 16; | |
4294 | maxnum |= 0xffff; | |
4295 | maxnum <<= 16; | |
4296 | maxnum |= 0xffff; | |
4297 | } | |
4298 | if (imm_expr.X_op == O_constant | |
4299 | && imm_expr.X_add_number >= maxnum | |
ca4e0257 | 4300 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
4301 | { |
4302 | do_false: | |
4303 | /* result is always false */ | |
4304 | if (! likely) | |
67c0d1eb | 4305 | macro_build (NULL, "nop", "", 0); |
252b5132 | 4306 | else |
67c0d1eb | 4307 | macro_build (&offset_expr, "bnel", "s,t,p", 0, 0); |
8fc2e39e | 4308 | break; |
252b5132 RH |
4309 | } |
4310 | if (imm_expr.X_op != O_constant) | |
4311 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 4312 | ++imm_expr.X_add_number; |
252b5132 RH |
4313 | /* FALLTHROUGH */ |
4314 | case M_BGE_I: | |
4315 | case M_BGEL_I: | |
4316 | if (mask == M_BGEL_I) | |
4317 | likely = 1; | |
4318 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4319 | { | |
67c0d1eb | 4320 | macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", sreg); |
8fc2e39e | 4321 | break; |
252b5132 RH |
4322 | } |
4323 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4324 | { | |
67c0d1eb | 4325 | macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", sreg); |
8fc2e39e | 4326 | break; |
252b5132 RH |
4327 | } |
4328 | maxnum = 0x7fffffff; | |
ca4e0257 | 4329 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
4330 | { |
4331 | maxnum <<= 16; | |
4332 | maxnum |= 0xffff; | |
4333 | maxnum <<= 16; | |
4334 | maxnum |= 0xffff; | |
4335 | } | |
4336 | maxnum = - maxnum - 1; | |
4337 | if (imm_expr.X_op == O_constant | |
4338 | && imm_expr.X_add_number <= maxnum | |
ca4e0257 | 4339 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
4340 | { |
4341 | do_true: | |
4342 | /* result is always true */ | |
4343 | as_warn (_("Branch %s is always true"), ip->insn_mo->name); | |
67c0d1eb | 4344 | macro_build (&offset_expr, "b", "p"); |
8fc2e39e | 4345 | break; |
252b5132 | 4346 | } |
8fc2e39e | 4347 | used_at = 1; |
67c0d1eb RS |
4348 | set_at (sreg, 0); |
4349 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
4350 | break; |
4351 | ||
4352 | case M_BGEUL: | |
4353 | likely = 1; | |
4354 | case M_BGEU: | |
4355 | if (treg == 0) | |
4356 | goto do_true; | |
4357 | if (sreg == 0) | |
4358 | { | |
67c0d1eb | 4359 | macro_build (&offset_expr, likely ? "beql" : "beq", |
17a2f251 | 4360 | "s,t,p", 0, treg); |
8fc2e39e | 4361 | break; |
252b5132 | 4362 | } |
8fc2e39e | 4363 | used_at = 1; |
67c0d1eb RS |
4364 | macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg); |
4365 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
4366 | break; |
4367 | ||
4368 | case M_BGTUL_I: | |
4369 | likely = 1; | |
4370 | case M_BGTU_I: | |
4371 | if (sreg == 0 | |
ca4e0257 | 4372 | || (HAVE_32BIT_GPRS |
252b5132 | 4373 | && imm_expr.X_op == O_constant |
956cd1d6 | 4374 | && imm_expr.X_add_number == (offsetT) 0xffffffff)) |
252b5132 RH |
4375 | goto do_false; |
4376 | if (imm_expr.X_op != O_constant) | |
4377 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 4378 | ++imm_expr.X_add_number; |
252b5132 RH |
4379 | /* FALLTHROUGH */ |
4380 | case M_BGEU_I: | |
4381 | case M_BGEUL_I: | |
4382 | if (mask == M_BGEUL_I) | |
4383 | likely = 1; | |
4384 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4385 | goto do_true; | |
4386 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4387 | { | |
67c0d1eb | 4388 | macro_build (&offset_expr, likely ? "bnel" : "bne", |
17a2f251 | 4389 | "s,t,p", sreg, 0); |
8fc2e39e | 4390 | break; |
252b5132 | 4391 | } |
8fc2e39e | 4392 | used_at = 1; |
67c0d1eb RS |
4393 | set_at (sreg, 1); |
4394 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
4395 | break; |
4396 | ||
4397 | case M_BGTL: | |
4398 | likely = 1; | |
4399 | case M_BGT: | |
4400 | if (treg == 0) | |
4401 | { | |
67c0d1eb | 4402 | macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", sreg); |
8fc2e39e | 4403 | break; |
252b5132 RH |
4404 | } |
4405 | if (sreg == 0) | |
4406 | { | |
67c0d1eb | 4407 | macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", treg); |
8fc2e39e | 4408 | break; |
252b5132 | 4409 | } |
8fc2e39e | 4410 | used_at = 1; |
67c0d1eb RS |
4411 | macro_build (NULL, "slt", "d,v,t", AT, treg, sreg); |
4412 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
4413 | break; |
4414 | ||
4415 | case M_BGTUL: | |
4416 | likely = 1; | |
4417 | case M_BGTU: | |
4418 | if (treg == 0) | |
4419 | { | |
67c0d1eb | 4420 | macro_build (&offset_expr, likely ? "bnel" : "bne", |
17a2f251 | 4421 | "s,t,p", sreg, 0); |
8fc2e39e | 4422 | break; |
252b5132 RH |
4423 | } |
4424 | if (sreg == 0) | |
4425 | goto do_false; | |
8fc2e39e | 4426 | used_at = 1; |
67c0d1eb RS |
4427 | macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg); |
4428 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
4429 | break; |
4430 | ||
4431 | case M_BLEL: | |
4432 | likely = 1; | |
4433 | case M_BLE: | |
4434 | if (treg == 0) | |
4435 | { | |
67c0d1eb | 4436 | macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", sreg); |
8fc2e39e | 4437 | break; |
252b5132 RH |
4438 | } |
4439 | if (sreg == 0) | |
4440 | { | |
67c0d1eb | 4441 | macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", treg); |
8fc2e39e | 4442 | break; |
252b5132 | 4443 | } |
8fc2e39e | 4444 | used_at = 1; |
67c0d1eb RS |
4445 | macro_build (NULL, "slt", "d,v,t", AT, treg, sreg); |
4446 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
4447 | break; |
4448 | ||
4449 | case M_BLEL_I: | |
4450 | likely = 1; | |
4451 | case M_BLE_I: | |
4452 | maxnum = 0x7fffffff; | |
ca4e0257 | 4453 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
4454 | { |
4455 | maxnum <<= 16; | |
4456 | maxnum |= 0xffff; | |
4457 | maxnum <<= 16; | |
4458 | maxnum |= 0xffff; | |
4459 | } | |
4460 | if (imm_expr.X_op == O_constant | |
4461 | && imm_expr.X_add_number >= maxnum | |
ca4e0257 | 4462 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
4463 | goto do_true; |
4464 | if (imm_expr.X_op != O_constant) | |
4465 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 4466 | ++imm_expr.X_add_number; |
252b5132 RH |
4467 | /* FALLTHROUGH */ |
4468 | case M_BLT_I: | |
4469 | case M_BLTL_I: | |
4470 | if (mask == M_BLTL_I) | |
4471 | likely = 1; | |
4472 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4473 | { | |
67c0d1eb | 4474 | macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", sreg); |
8fc2e39e | 4475 | break; |
252b5132 RH |
4476 | } |
4477 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4478 | { | |
67c0d1eb | 4479 | macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", sreg); |
8fc2e39e | 4480 | break; |
252b5132 | 4481 | } |
8fc2e39e | 4482 | used_at = 1; |
67c0d1eb RS |
4483 | set_at (sreg, 0); |
4484 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
4485 | break; |
4486 | ||
4487 | case M_BLEUL: | |
4488 | likely = 1; | |
4489 | case M_BLEU: | |
4490 | if (treg == 0) | |
4491 | { | |
67c0d1eb | 4492 | macro_build (&offset_expr, likely ? "beql" : "beq", |
17a2f251 | 4493 | "s,t,p", sreg, 0); |
8fc2e39e | 4494 | break; |
252b5132 RH |
4495 | } |
4496 | if (sreg == 0) | |
4497 | goto do_true; | |
8fc2e39e | 4498 | used_at = 1; |
67c0d1eb RS |
4499 | macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg); |
4500 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
4501 | break; |
4502 | ||
4503 | case M_BLEUL_I: | |
4504 | likely = 1; | |
4505 | case M_BLEU_I: | |
4506 | if (sreg == 0 | |
ca4e0257 | 4507 | || (HAVE_32BIT_GPRS |
252b5132 | 4508 | && imm_expr.X_op == O_constant |
956cd1d6 | 4509 | && imm_expr.X_add_number == (offsetT) 0xffffffff)) |
252b5132 RH |
4510 | goto do_true; |
4511 | if (imm_expr.X_op != O_constant) | |
4512 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 4513 | ++imm_expr.X_add_number; |
252b5132 RH |
4514 | /* FALLTHROUGH */ |
4515 | case M_BLTU_I: | |
4516 | case M_BLTUL_I: | |
4517 | if (mask == M_BLTUL_I) | |
4518 | likely = 1; | |
4519 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4520 | goto do_false; | |
4521 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4522 | { | |
67c0d1eb | 4523 | macro_build (&offset_expr, likely ? "beql" : "beq", |
252b5132 | 4524 | "s,t,p", sreg, 0); |
8fc2e39e | 4525 | break; |
252b5132 | 4526 | } |
8fc2e39e | 4527 | used_at = 1; |
67c0d1eb RS |
4528 | set_at (sreg, 1); |
4529 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
4530 | break; |
4531 | ||
4532 | case M_BLTL: | |
4533 | likely = 1; | |
4534 | case M_BLT: | |
4535 | if (treg == 0) | |
4536 | { | |
67c0d1eb | 4537 | macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", sreg); |
8fc2e39e | 4538 | break; |
252b5132 RH |
4539 | } |
4540 | if (sreg == 0) | |
4541 | { | |
67c0d1eb | 4542 | macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", treg); |
8fc2e39e | 4543 | break; |
252b5132 | 4544 | } |
8fc2e39e | 4545 | used_at = 1; |
67c0d1eb RS |
4546 | macro_build (NULL, "slt", "d,v,t", AT, sreg, treg); |
4547 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
4548 | break; |
4549 | ||
4550 | case M_BLTUL: | |
4551 | likely = 1; | |
4552 | case M_BLTU: | |
4553 | if (treg == 0) | |
4554 | goto do_false; | |
4555 | if (sreg == 0) | |
4556 | { | |
67c0d1eb | 4557 | macro_build (&offset_expr, likely ? "bnel" : "bne", |
17a2f251 | 4558 | "s,t,p", 0, treg); |
8fc2e39e | 4559 | break; |
252b5132 | 4560 | } |
8fc2e39e | 4561 | used_at = 1; |
67c0d1eb RS |
4562 | macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg); |
4563 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
4564 | break; |
4565 | ||
5f74bc13 CD |
4566 | case M_DEXT: |
4567 | { | |
4568 | unsigned long pos; | |
4569 | unsigned long size; | |
4570 | ||
4571 | if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant) | |
4572 | { | |
4573 | as_bad (_("Unsupported large constant")); | |
4574 | pos = size = 1; | |
4575 | } | |
4576 | else | |
4577 | { | |
4578 | pos = (unsigned long) imm_expr.X_add_number; | |
4579 | size = (unsigned long) imm2_expr.X_add_number; | |
4580 | } | |
4581 | ||
4582 | if (pos > 63) | |
4583 | { | |
4584 | as_bad (_("Improper position (%lu)"), pos); | |
4585 | pos = 1; | |
4586 | } | |
4587 | if (size == 0 || size > 64 | |
4588 | || (pos + size - 1) > 63) | |
4589 | { | |
4590 | as_bad (_("Improper extract size (%lu, position %lu)"), | |
4591 | size, pos); | |
4592 | size = 1; | |
4593 | } | |
4594 | ||
4595 | if (size <= 32 && pos < 32) | |
4596 | { | |
4597 | s = "dext"; | |
4598 | fmt = "t,r,+A,+C"; | |
4599 | } | |
4600 | else if (size <= 32) | |
4601 | { | |
4602 | s = "dextu"; | |
4603 | fmt = "t,r,+E,+H"; | |
4604 | } | |
4605 | else | |
4606 | { | |
4607 | s = "dextm"; | |
4608 | fmt = "t,r,+A,+G"; | |
4609 | } | |
67c0d1eb | 4610 | macro_build ((expressionS *) NULL, s, fmt, treg, sreg, pos, size - 1); |
5f74bc13 | 4611 | } |
8fc2e39e | 4612 | break; |
5f74bc13 CD |
4613 | |
4614 | case M_DINS: | |
4615 | { | |
4616 | unsigned long pos; | |
4617 | unsigned long size; | |
4618 | ||
4619 | if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant) | |
4620 | { | |
4621 | as_bad (_("Unsupported large constant")); | |
4622 | pos = size = 1; | |
4623 | } | |
4624 | else | |
4625 | { | |
4626 | pos = (unsigned long) imm_expr.X_add_number; | |
4627 | size = (unsigned long) imm2_expr.X_add_number; | |
4628 | } | |
4629 | ||
4630 | if (pos > 63) | |
4631 | { | |
4632 | as_bad (_("Improper position (%lu)"), pos); | |
4633 | pos = 1; | |
4634 | } | |
4635 | if (size == 0 || size > 64 | |
4636 | || (pos + size - 1) > 63) | |
4637 | { | |
4638 | as_bad (_("Improper insert size (%lu, position %lu)"), | |
4639 | size, pos); | |
4640 | size = 1; | |
4641 | } | |
4642 | ||
4643 | if (pos < 32 && (pos + size - 1) < 32) | |
4644 | { | |
4645 | s = "dins"; | |
4646 | fmt = "t,r,+A,+B"; | |
4647 | } | |
4648 | else if (pos >= 32) | |
4649 | { | |
4650 | s = "dinsu"; | |
4651 | fmt = "t,r,+E,+F"; | |
4652 | } | |
4653 | else | |
4654 | { | |
4655 | s = "dinsm"; | |
4656 | fmt = "t,r,+A,+F"; | |
4657 | } | |
67c0d1eb RS |
4658 | macro_build ((expressionS *) NULL, s, fmt, treg, sreg, pos, |
4659 | pos + size - 1); | |
5f74bc13 | 4660 | } |
8fc2e39e | 4661 | break; |
5f74bc13 | 4662 | |
252b5132 RH |
4663 | case M_DDIV_3: |
4664 | dbl = 1; | |
4665 | case M_DIV_3: | |
4666 | s = "mflo"; | |
4667 | goto do_div3; | |
4668 | case M_DREM_3: | |
4669 | dbl = 1; | |
4670 | case M_REM_3: | |
4671 | s = "mfhi"; | |
4672 | do_div3: | |
4673 | if (treg == 0) | |
4674 | { | |
4675 | as_warn (_("Divide by zero.")); | |
4676 | if (mips_trap) | |
67c0d1eb | 4677 | macro_build (NULL, "teq", "s,t,q", 0, 0, 7); |
252b5132 | 4678 | else |
67c0d1eb | 4679 | macro_build (NULL, "break", "c", 7); |
8fc2e39e | 4680 | break; |
252b5132 RH |
4681 | } |
4682 | ||
7d10b47d | 4683 | start_noreorder (); |
252b5132 RH |
4684 | if (mips_trap) |
4685 | { | |
67c0d1eb RS |
4686 | macro_build (NULL, "teq", "s,t,q", treg, 0, 7); |
4687 | macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg); | |
252b5132 RH |
4688 | } |
4689 | else | |
4690 | { | |
4691 | expr1.X_add_number = 8; | |
67c0d1eb RS |
4692 | macro_build (&expr1, "bne", "s,t,p", treg, 0); |
4693 | macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg); | |
4694 | macro_build (NULL, "break", "c", 7); | |
252b5132 RH |
4695 | } |
4696 | expr1.X_add_number = -1; | |
8fc2e39e | 4697 | used_at = 1; |
f6a22291 | 4698 | load_register (AT, &expr1, dbl); |
252b5132 | 4699 | expr1.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16); |
67c0d1eb | 4700 | macro_build (&expr1, "bne", "s,t,p", treg, AT); |
252b5132 RH |
4701 | if (dbl) |
4702 | { | |
4703 | expr1.X_add_number = 1; | |
f6a22291 | 4704 | load_register (AT, &expr1, dbl); |
67c0d1eb | 4705 | macro_build (NULL, "dsll32", "d,w,<", AT, AT, 31); |
252b5132 RH |
4706 | } |
4707 | else | |
4708 | { | |
4709 | expr1.X_add_number = 0x80000000; | |
67c0d1eb | 4710 | macro_build (&expr1, "lui", "t,u", AT, BFD_RELOC_HI16); |
252b5132 RH |
4711 | } |
4712 | if (mips_trap) | |
4713 | { | |
67c0d1eb | 4714 | macro_build (NULL, "teq", "s,t,q", sreg, AT, 6); |
252b5132 RH |
4715 | /* We want to close the noreorder block as soon as possible, so |
4716 | that later insns are available for delay slot filling. */ | |
7d10b47d | 4717 | end_noreorder (); |
252b5132 RH |
4718 | } |
4719 | else | |
4720 | { | |
4721 | expr1.X_add_number = 8; | |
67c0d1eb RS |
4722 | macro_build (&expr1, "bne", "s,t,p", sreg, AT); |
4723 | macro_build (NULL, "nop", "", 0); | |
252b5132 RH |
4724 | |
4725 | /* We want to close the noreorder block as soon as possible, so | |
4726 | that later insns are available for delay slot filling. */ | |
7d10b47d | 4727 | end_noreorder (); |
252b5132 | 4728 | |
67c0d1eb | 4729 | macro_build (NULL, "break", "c", 6); |
252b5132 | 4730 | } |
67c0d1eb | 4731 | macro_build (NULL, s, "d", dreg); |
252b5132 RH |
4732 | break; |
4733 | ||
4734 | case M_DIV_3I: | |
4735 | s = "div"; | |
4736 | s2 = "mflo"; | |
4737 | goto do_divi; | |
4738 | case M_DIVU_3I: | |
4739 | s = "divu"; | |
4740 | s2 = "mflo"; | |
4741 | goto do_divi; | |
4742 | case M_REM_3I: | |
4743 | s = "div"; | |
4744 | s2 = "mfhi"; | |
4745 | goto do_divi; | |
4746 | case M_REMU_3I: | |
4747 | s = "divu"; | |
4748 | s2 = "mfhi"; | |
4749 | goto do_divi; | |
4750 | case M_DDIV_3I: | |
4751 | dbl = 1; | |
4752 | s = "ddiv"; | |
4753 | s2 = "mflo"; | |
4754 | goto do_divi; | |
4755 | case M_DDIVU_3I: | |
4756 | dbl = 1; | |
4757 | s = "ddivu"; | |
4758 | s2 = "mflo"; | |
4759 | goto do_divi; | |
4760 | case M_DREM_3I: | |
4761 | dbl = 1; | |
4762 | s = "ddiv"; | |
4763 | s2 = "mfhi"; | |
4764 | goto do_divi; | |
4765 | case M_DREMU_3I: | |
4766 | dbl = 1; | |
4767 | s = "ddivu"; | |
4768 | s2 = "mfhi"; | |
4769 | do_divi: | |
4770 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4771 | { | |
4772 | as_warn (_("Divide by zero.")); | |
4773 | if (mips_trap) | |
67c0d1eb | 4774 | macro_build (NULL, "teq", "s,t,q", 0, 0, 7); |
252b5132 | 4775 | else |
67c0d1eb | 4776 | macro_build (NULL, "break", "c", 7); |
8fc2e39e | 4777 | break; |
252b5132 RH |
4778 | } |
4779 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4780 | { | |
4781 | if (strcmp (s2, "mflo") == 0) | |
67c0d1eb | 4782 | move_register (dreg, sreg); |
252b5132 | 4783 | else |
67c0d1eb | 4784 | move_register (dreg, 0); |
8fc2e39e | 4785 | break; |
252b5132 RH |
4786 | } |
4787 | if (imm_expr.X_op == O_constant | |
4788 | && imm_expr.X_add_number == -1 | |
4789 | && s[strlen (s) - 1] != 'u') | |
4790 | { | |
4791 | if (strcmp (s2, "mflo") == 0) | |
4792 | { | |
67c0d1eb | 4793 | macro_build (NULL, dbl ? "dneg" : "neg", "d,w", dreg, sreg); |
252b5132 RH |
4794 | } |
4795 | else | |
67c0d1eb | 4796 | move_register (dreg, 0); |
8fc2e39e | 4797 | break; |
252b5132 RH |
4798 | } |
4799 | ||
8fc2e39e | 4800 | used_at = 1; |
67c0d1eb RS |
4801 | load_register (AT, &imm_expr, dbl); |
4802 | macro_build (NULL, s, "z,s,t", sreg, AT); | |
4803 | macro_build (NULL, s2, "d", dreg); | |
252b5132 RH |
4804 | break; |
4805 | ||
4806 | case M_DIVU_3: | |
4807 | s = "divu"; | |
4808 | s2 = "mflo"; | |
4809 | goto do_divu3; | |
4810 | case M_REMU_3: | |
4811 | s = "divu"; | |
4812 | s2 = "mfhi"; | |
4813 | goto do_divu3; | |
4814 | case M_DDIVU_3: | |
4815 | s = "ddivu"; | |
4816 | s2 = "mflo"; | |
4817 | goto do_divu3; | |
4818 | case M_DREMU_3: | |
4819 | s = "ddivu"; | |
4820 | s2 = "mfhi"; | |
4821 | do_divu3: | |
7d10b47d | 4822 | start_noreorder (); |
252b5132 RH |
4823 | if (mips_trap) |
4824 | { | |
67c0d1eb RS |
4825 | macro_build (NULL, "teq", "s,t,q", treg, 0, 7); |
4826 | macro_build (NULL, s, "z,s,t", sreg, treg); | |
252b5132 RH |
4827 | /* We want to close the noreorder block as soon as possible, so |
4828 | that later insns are available for delay slot filling. */ | |
7d10b47d | 4829 | end_noreorder (); |
252b5132 RH |
4830 | } |
4831 | else | |
4832 | { | |
4833 | expr1.X_add_number = 8; | |
67c0d1eb RS |
4834 | macro_build (&expr1, "bne", "s,t,p", treg, 0); |
4835 | macro_build (NULL, s, "z,s,t", sreg, treg); | |
252b5132 RH |
4836 | |
4837 | /* We want to close the noreorder block as soon as possible, so | |
4838 | that later insns are available for delay slot filling. */ | |
7d10b47d | 4839 | end_noreorder (); |
67c0d1eb | 4840 | macro_build (NULL, "break", "c", 7); |
252b5132 | 4841 | } |
67c0d1eb | 4842 | macro_build (NULL, s2, "d", dreg); |
8fc2e39e | 4843 | break; |
252b5132 | 4844 | |
1abe91b1 MR |
4845 | case M_DLCA_AB: |
4846 | dbl = 1; | |
4847 | case M_LCA_AB: | |
4848 | call = 1; | |
4849 | goto do_la; | |
252b5132 RH |
4850 | case M_DLA_AB: |
4851 | dbl = 1; | |
4852 | case M_LA_AB: | |
1abe91b1 | 4853 | do_la: |
252b5132 RH |
4854 | /* Load the address of a symbol into a register. If breg is not |
4855 | zero, we then add a base register to it. */ | |
4856 | ||
3bec30a8 TS |
4857 | if (dbl && HAVE_32BIT_GPRS) |
4858 | as_warn (_("dla used to load 32-bit register")); | |
4859 | ||
c90bbe5b | 4860 | if (! dbl && HAVE_64BIT_OBJECTS) |
3bec30a8 TS |
4861 | as_warn (_("la used to load 64-bit address")); |
4862 | ||
0c11417f MR |
4863 | if (offset_expr.X_op == O_constant |
4864 | && offset_expr.X_add_number >= -0x8000 | |
4865 | && offset_expr.X_add_number < 0x8000) | |
4866 | { | |
aed1a261 | 4867 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, |
17a2f251 | 4868 | "t,r,j", treg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 4869 | break; |
0c11417f MR |
4870 | } |
4871 | ||
b8285c27 | 4872 | if (!mips_opts.noat && (treg == breg)) |
afdbd6d0 CD |
4873 | { |
4874 | tempreg = AT; | |
4875 | used_at = 1; | |
4876 | } | |
4877 | else | |
4878 | { | |
4879 | tempreg = treg; | |
afdbd6d0 CD |
4880 | } |
4881 | ||
252b5132 RH |
4882 | if (offset_expr.X_op != O_symbol |
4883 | && offset_expr.X_op != O_constant) | |
4884 | { | |
4885 | as_bad (_("expression too complex")); | |
4886 | offset_expr.X_op = O_constant; | |
4887 | } | |
4888 | ||
252b5132 | 4889 | if (offset_expr.X_op == O_constant) |
aed1a261 | 4890 | load_register (tempreg, &offset_expr, HAVE_64BIT_ADDRESSES); |
252b5132 RH |
4891 | else if (mips_pic == NO_PIC) |
4892 | { | |
d6bc6245 | 4893 | /* If this is a reference to a GP relative symbol, we want |
cdf6fd85 | 4894 | addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
4895 | Otherwise we want |
4896 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
4897 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
4898 | If we have a constant, we need two instructions anyhow, | |
d6bc6245 | 4899 | so we may as well always use the latter form. |
76b3015f | 4900 | |
6caf9ef4 TS |
4901 | With 64bit address space and a usable $at we want |
4902 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
4903 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
4904 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
4905 | daddiu $at,<sym> (BFD_RELOC_LO16) | |
4906 | dsll32 $tempreg,0 | |
4907 | daddu $tempreg,$tempreg,$at | |
4908 | ||
4909 | If $at is already in use, we use a path which is suboptimal | |
4910 | on superscalar processors. | |
4911 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
4912 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
4913 | dsll $tempreg,16 | |
4914 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
4915 | dsll $tempreg,16 | |
4916 | daddiu $tempreg,<sym> (BFD_RELOC_LO16) | |
4917 | ||
4918 | For GP relative symbols in 64bit address space we can use | |
4919 | the same sequence as in 32bit address space. */ | |
aed1a261 | 4920 | if (HAVE_64BIT_SYMBOLS) |
252b5132 | 4921 | { |
6caf9ef4 TS |
4922 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
4923 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) | |
4924 | { | |
4925 | relax_start (offset_expr.X_add_symbol); | |
4926 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
4927 | tempreg, mips_gp_register, BFD_RELOC_GPREL16); | |
4928 | relax_switch (); | |
4929 | } | |
d6bc6245 | 4930 | |
b8285c27 | 4931 | if (used_at == 0 && !mips_opts.noat) |
98d3f06f | 4932 | { |
67c0d1eb | 4933 | macro_build (&offset_expr, "lui", "t,u", |
17a2f251 | 4934 | tempreg, BFD_RELOC_MIPS_HIGHEST); |
67c0d1eb | 4935 | macro_build (&offset_expr, "lui", "t,u", |
17a2f251 | 4936 | AT, BFD_RELOC_HI16_S); |
67c0d1eb | 4937 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 4938 | tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); |
67c0d1eb | 4939 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 4940 | AT, AT, BFD_RELOC_LO16); |
67c0d1eb RS |
4941 | macro_build (NULL, "dsll32", "d,w,<", tempreg, tempreg, 0); |
4942 | macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT); | |
98d3f06f KH |
4943 | used_at = 1; |
4944 | } | |
4945 | else | |
4946 | { | |
67c0d1eb | 4947 | macro_build (&offset_expr, "lui", "t,u", |
17a2f251 | 4948 | tempreg, BFD_RELOC_MIPS_HIGHEST); |
67c0d1eb | 4949 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 4950 | tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); |
67c0d1eb RS |
4951 | macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16); |
4952 | macro_build (&offset_expr, "daddiu", "t,r,j", | |
17a2f251 | 4953 | tempreg, tempreg, BFD_RELOC_HI16_S); |
67c0d1eb RS |
4954 | macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16); |
4955 | macro_build (&offset_expr, "daddiu", "t,r,j", | |
17a2f251 | 4956 | tempreg, tempreg, BFD_RELOC_LO16); |
98d3f06f | 4957 | } |
6caf9ef4 TS |
4958 | |
4959 | if (mips_relax.sequence) | |
4960 | relax_end (); | |
98d3f06f KH |
4961 | } |
4962 | else | |
4963 | { | |
4964 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET | |
6caf9ef4 | 4965 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
98d3f06f | 4966 | { |
4d7206a2 | 4967 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
4968 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
4969 | tempreg, mips_gp_register, BFD_RELOC_GPREL16); | |
4d7206a2 | 4970 | relax_switch (); |
98d3f06f | 4971 | } |
6943caf0 ILT |
4972 | if (!IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) |
4973 | as_bad (_("offset too large")); | |
67c0d1eb RS |
4974 | macro_build_lui (&offset_expr, tempreg); |
4975 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
4976 | tempreg, tempreg, BFD_RELOC_LO16); | |
4d7206a2 RS |
4977 | if (mips_relax.sequence) |
4978 | relax_end (); | |
98d3f06f | 4979 | } |
252b5132 | 4980 | } |
f5040a92 | 4981 | else if (mips_pic == SVR4_PIC && ! mips_big_got && ! HAVE_NEWABI) |
252b5132 | 4982 | { |
9117d219 NC |
4983 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
4984 | ||
252b5132 RH |
4985 | /* If this is a reference to an external symbol, and there |
4986 | is no constant, we want | |
4987 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
1abe91b1 | 4988 | or for lca or if tempreg is PIC_CALL_REG |
9117d219 | 4989 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
252b5132 RH |
4990 | For a local symbol, we want |
4991 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4992 | nop | |
4993 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
4994 | ||
4995 | If we have a small constant, and this is a reference to | |
4996 | an external symbol, we want | |
4997 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4998 | nop | |
4999 | addiu $tempreg,$tempreg,<constant> | |
5000 | For a local symbol, we want the same instruction | |
5001 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
5002 | addiu instruction. | |
5003 | ||
5004 | If we have a large constant, and this is a reference to | |
5005 | an external symbol, we want | |
5006 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5007 | lui $at,<hiconstant> | |
5008 | addiu $at,$at,<loconstant> | |
5009 | addu $tempreg,$tempreg,$at | |
5010 | For a local symbol, we want the same instruction | |
5011 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
ed6fb7bd | 5012 | addiu instruction. |
ed6fb7bd SC |
5013 | */ |
5014 | ||
4d7206a2 | 5015 | if (offset_expr.X_add_number == 0) |
252b5132 | 5016 | { |
4d7206a2 RS |
5017 | if (breg == 0 && (call || tempreg == PIC_CALL_REG)) |
5018 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16; | |
5019 | ||
5020 | relax_start (offset_expr.X_add_symbol); | |
67c0d1eb RS |
5021 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5022 | lw_reloc_type, mips_gp_register); | |
4d7206a2 | 5023 | if (breg != 0) |
252b5132 RH |
5024 | { |
5025 | /* We're going to put in an addu instruction using | |
5026 | tempreg, so we may as well insert the nop right | |
5027 | now. */ | |
269137b2 | 5028 | load_delay_nop (); |
252b5132 | 5029 | } |
4d7206a2 | 5030 | relax_switch (); |
67c0d1eb RS |
5031 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5032 | tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 5033 | load_delay_nop (); |
67c0d1eb RS |
5034 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
5035 | tempreg, tempreg, BFD_RELOC_LO16); | |
4d7206a2 | 5036 | relax_end (); |
252b5132 RH |
5037 | /* FIXME: If breg == 0, and the next instruction uses |
5038 | $tempreg, then if this variant case is used an extra | |
5039 | nop will be generated. */ | |
5040 | } | |
4d7206a2 RS |
5041 | else if (offset_expr.X_add_number >= -0x8000 |
5042 | && offset_expr.X_add_number < 0x8000) | |
252b5132 | 5043 | { |
67c0d1eb | 5044 | load_got_offset (tempreg, &offset_expr); |
269137b2 | 5045 | load_delay_nop (); |
67c0d1eb | 5046 | add_got_offset (tempreg, &offset_expr); |
252b5132 RH |
5047 | } |
5048 | else | |
5049 | { | |
4d7206a2 RS |
5050 | expr1.X_add_number = offset_expr.X_add_number; |
5051 | offset_expr.X_add_number = | |
5052 | ((offset_expr.X_add_number + 0x8000) & 0xffff) - 0x8000; | |
67c0d1eb | 5053 | load_got_offset (tempreg, &offset_expr); |
f6a22291 | 5054 | offset_expr.X_add_number = expr1.X_add_number; |
252b5132 RH |
5055 | /* If we are going to add in a base register, and the |
5056 | target register and the base register are the same, | |
5057 | then we are using AT as a temporary register. Since | |
5058 | we want to load the constant into AT, we add our | |
5059 | current AT (from the global offset table) and the | |
5060 | register into the register now, and pretend we were | |
5061 | not using a base register. */ | |
67c0d1eb | 5062 | if (breg == treg) |
252b5132 | 5063 | { |
269137b2 | 5064 | load_delay_nop (); |
67c0d1eb | 5065 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5066 | treg, AT, breg); |
252b5132 RH |
5067 | breg = 0; |
5068 | tempreg = treg; | |
252b5132 | 5069 | } |
f6a22291 | 5070 | add_got_offset_hilo (tempreg, &offset_expr, AT); |
252b5132 RH |
5071 | used_at = 1; |
5072 | } | |
5073 | } | |
f5040a92 AO |
5074 | else if (mips_pic == SVR4_PIC && ! mips_big_got && HAVE_NEWABI) |
5075 | { | |
67c0d1eb | 5076 | int add_breg_early = 0; |
f5040a92 AO |
5077 | |
5078 | /* If this is a reference to an external, and there is no | |
5079 | constant, or local symbol (*), with or without a | |
5080 | constant, we want | |
5081 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
1abe91b1 | 5082 | or for lca or if tempreg is PIC_CALL_REG |
f5040a92 AO |
5083 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
5084 | ||
5085 | If we have a small constant, and this is a reference to | |
5086 | an external symbol, we want | |
5087 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
5088 | addiu $tempreg,$tempreg,<constant> | |
5089 | ||
5090 | If we have a large constant, and this is a reference to | |
5091 | an external symbol, we want | |
5092 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
5093 | lui $at,<hiconstant> | |
5094 | addiu $at,$at,<loconstant> | |
5095 | addu $tempreg,$tempreg,$at | |
5096 | ||
5097 | (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for | |
5098 | local symbols, even though it introduces an additional | |
5099 | instruction. */ | |
5100 | ||
f5040a92 AO |
5101 | if (offset_expr.X_add_number) |
5102 | { | |
4d7206a2 | 5103 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
5104 | offset_expr.X_add_number = 0; |
5105 | ||
4d7206a2 | 5106 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
5107 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5108 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
5109 | |
5110 | if (expr1.X_add_number >= -0x8000 | |
5111 | && expr1.X_add_number < 0x8000) | |
5112 | { | |
67c0d1eb RS |
5113 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
5114 | tempreg, tempreg, BFD_RELOC_LO16); | |
f5040a92 | 5115 | } |
ecd13cd3 | 5116 | else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000)) |
f5040a92 AO |
5117 | { |
5118 | int dreg; | |
5119 | ||
5120 | /* If we are going to add in a base register, and the | |
5121 | target register and the base register are the same, | |
5122 | then we are using AT as a temporary register. Since | |
5123 | we want to load the constant into AT, we add our | |
5124 | current AT (from the global offset table) and the | |
5125 | register into the register now, and pretend we were | |
5126 | not using a base register. */ | |
5127 | if (breg != treg) | |
5128 | dreg = tempreg; | |
5129 | else | |
5130 | { | |
5131 | assert (tempreg == AT); | |
67c0d1eb RS |
5132 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
5133 | treg, AT, breg); | |
f5040a92 | 5134 | dreg = treg; |
67c0d1eb | 5135 | add_breg_early = 1; |
f5040a92 AO |
5136 | } |
5137 | ||
f6a22291 | 5138 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 5139 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5140 | dreg, dreg, AT); |
f5040a92 | 5141 | |
f5040a92 AO |
5142 | used_at = 1; |
5143 | } | |
5144 | else | |
5145 | as_bad (_("PIC code offset overflow (max 32 signed bits)")); | |
5146 | ||
4d7206a2 | 5147 | relax_switch (); |
f5040a92 AO |
5148 | offset_expr.X_add_number = expr1.X_add_number; |
5149 | ||
67c0d1eb RS |
5150 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5151 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
5152 | if (add_breg_early) | |
f5040a92 | 5153 | { |
67c0d1eb | 5154 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
f899b4b8 | 5155 | treg, tempreg, breg); |
f5040a92 AO |
5156 | breg = 0; |
5157 | tempreg = treg; | |
5158 | } | |
4d7206a2 | 5159 | relax_end (); |
f5040a92 | 5160 | } |
4d7206a2 | 5161 | else if (breg == 0 && (call || tempreg == PIC_CALL_REG)) |
f5040a92 | 5162 | { |
4d7206a2 | 5163 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
5164 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5165 | BFD_RELOC_MIPS_CALL16, mips_gp_register); | |
4d7206a2 | 5166 | relax_switch (); |
67c0d1eb RS |
5167 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5168 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
4d7206a2 | 5169 | relax_end (); |
f5040a92 | 5170 | } |
4d7206a2 | 5171 | else |
f5040a92 | 5172 | { |
67c0d1eb RS |
5173 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5174 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
5175 | } |
5176 | } | |
5177 | else if (mips_pic == SVR4_PIC && ! HAVE_NEWABI) | |
252b5132 | 5178 | { |
67c0d1eb | 5179 | int gpdelay; |
9117d219 NC |
5180 | int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; |
5181 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; | |
ed6fb7bd | 5182 | int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
252b5132 RH |
5183 | |
5184 | /* This is the large GOT case. If this is a reference to an | |
5185 | external symbol, and there is no constant, we want | |
5186 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5187 | addu $tempreg,$tempreg,$gp | |
5188 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
1abe91b1 | 5189 | or for lca or if tempreg is PIC_CALL_REG |
9117d219 NC |
5190 | lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) |
5191 | addu $tempreg,$tempreg,$gp | |
5192 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) | |
252b5132 RH |
5193 | For a local symbol, we want |
5194 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5195 | nop | |
5196 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
5197 | ||
5198 | If we have a small constant, and this is a reference to | |
5199 | an external symbol, we want | |
5200 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5201 | addu $tempreg,$tempreg,$gp | |
5202 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5203 | nop | |
5204 | addiu $tempreg,$tempreg,<constant> | |
5205 | For a local symbol, we want | |
5206 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5207 | nop | |
5208 | addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16) | |
5209 | ||
5210 | If we have a large constant, and this is a reference to | |
5211 | an external symbol, we want | |
5212 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5213 | addu $tempreg,$tempreg,$gp | |
5214 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5215 | lui $at,<hiconstant> | |
5216 | addiu $at,$at,<loconstant> | |
5217 | addu $tempreg,$tempreg,$at | |
5218 | For a local symbol, we want | |
5219 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5220 | lui $at,<hiconstant> | |
5221 | addiu $at,$at,<loconstant> (BFD_RELOC_LO16) | |
5222 | addu $tempreg,$tempreg,$at | |
f5040a92 | 5223 | */ |
438c16b8 | 5224 | |
252b5132 RH |
5225 | expr1.X_add_number = offset_expr.X_add_number; |
5226 | offset_expr.X_add_number = 0; | |
4d7206a2 | 5227 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 5228 | gpdelay = reg_needs_delay (mips_gp_register); |
1abe91b1 MR |
5229 | if (expr1.X_add_number == 0 && breg == 0 |
5230 | && (call || tempreg == PIC_CALL_REG)) | |
9117d219 NC |
5231 | { |
5232 | lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; | |
5233 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; | |
5234 | } | |
67c0d1eb RS |
5235 | macro_build (&offset_expr, "lui", "t,u", tempreg, lui_reloc_type); |
5236 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 5237 | tempreg, tempreg, mips_gp_register); |
67c0d1eb | 5238 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
17a2f251 | 5239 | tempreg, lw_reloc_type, tempreg); |
252b5132 RH |
5240 | if (expr1.X_add_number == 0) |
5241 | { | |
67c0d1eb | 5242 | if (breg != 0) |
252b5132 RH |
5243 | { |
5244 | /* We're going to put in an addu instruction using | |
5245 | tempreg, so we may as well insert the nop right | |
5246 | now. */ | |
269137b2 | 5247 | load_delay_nop (); |
252b5132 | 5248 | } |
252b5132 RH |
5249 | } |
5250 | else if (expr1.X_add_number >= -0x8000 | |
5251 | && expr1.X_add_number < 0x8000) | |
5252 | { | |
269137b2 | 5253 | load_delay_nop (); |
67c0d1eb | 5254 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 5255 | tempreg, tempreg, BFD_RELOC_LO16); |
252b5132 RH |
5256 | } |
5257 | else | |
5258 | { | |
67c0d1eb | 5259 | int dreg; |
252b5132 RH |
5260 | |
5261 | /* If we are going to add in a base register, and the | |
5262 | target register and the base register are the same, | |
5263 | then we are using AT as a temporary register. Since | |
5264 | we want to load the constant into AT, we add our | |
5265 | current AT (from the global offset table) and the | |
5266 | register into the register now, and pretend we were | |
5267 | not using a base register. */ | |
5268 | if (breg != treg) | |
67c0d1eb | 5269 | dreg = tempreg; |
252b5132 RH |
5270 | else |
5271 | { | |
5272 | assert (tempreg == AT); | |
269137b2 | 5273 | load_delay_nop (); |
67c0d1eb | 5274 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5275 | treg, AT, breg); |
252b5132 | 5276 | dreg = treg; |
252b5132 RH |
5277 | } |
5278 | ||
f6a22291 | 5279 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 5280 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT); |
252b5132 | 5281 | |
252b5132 RH |
5282 | used_at = 1; |
5283 | } | |
4d7206a2 RS |
5284 | offset_expr.X_add_number = |
5285 | ((expr1.X_add_number + 0x8000) & 0xffff) - 0x8000; | |
5286 | relax_switch (); | |
252b5132 | 5287 | |
67c0d1eb | 5288 | if (gpdelay) |
252b5132 RH |
5289 | { |
5290 | /* This is needed because this instruction uses $gp, but | |
f5040a92 | 5291 | the first instruction on the main stream does not. */ |
67c0d1eb | 5292 | macro_build (NULL, "nop", ""); |
252b5132 | 5293 | } |
ed6fb7bd | 5294 | |
67c0d1eb RS |
5295 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5296 | local_reloc_type, mips_gp_register); | |
f5040a92 | 5297 | if (expr1.X_add_number >= -0x8000 |
252b5132 RH |
5298 | && expr1.X_add_number < 0x8000) |
5299 | { | |
269137b2 | 5300 | load_delay_nop (); |
67c0d1eb RS |
5301 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
5302 | tempreg, tempreg, BFD_RELOC_LO16); | |
252b5132 | 5303 | /* FIXME: If add_number is 0, and there was no base |
f5040a92 AO |
5304 | register, the external symbol case ended with a load, |
5305 | so if the symbol turns out to not be external, and | |
5306 | the next instruction uses tempreg, an unnecessary nop | |
5307 | will be inserted. */ | |
252b5132 RH |
5308 | } |
5309 | else | |
5310 | { | |
5311 | if (breg == treg) | |
5312 | { | |
5313 | /* We must add in the base register now, as in the | |
f5040a92 | 5314 | external symbol case. */ |
252b5132 | 5315 | assert (tempreg == AT); |
269137b2 | 5316 | load_delay_nop (); |
67c0d1eb | 5317 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5318 | treg, AT, breg); |
252b5132 RH |
5319 | tempreg = treg; |
5320 | /* We set breg to 0 because we have arranged to add | |
f5040a92 | 5321 | it in in both cases. */ |
252b5132 RH |
5322 | breg = 0; |
5323 | } | |
5324 | ||
67c0d1eb RS |
5325 | macro_build_lui (&expr1, AT); |
5326 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
17a2f251 | 5327 | AT, AT, BFD_RELOC_LO16); |
67c0d1eb | 5328 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5329 | tempreg, tempreg, AT); |
8fc2e39e | 5330 | used_at = 1; |
252b5132 | 5331 | } |
4d7206a2 | 5332 | relax_end (); |
252b5132 | 5333 | } |
f5040a92 AO |
5334 | else if (mips_pic == SVR4_PIC && HAVE_NEWABI) |
5335 | { | |
f5040a92 AO |
5336 | int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; |
5337 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; | |
67c0d1eb | 5338 | int add_breg_early = 0; |
f5040a92 AO |
5339 | |
5340 | /* This is the large GOT case. If this is a reference to an | |
5341 | external symbol, and there is no constant, we want | |
5342 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5343 | add $tempreg,$tempreg,$gp | |
5344 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
1abe91b1 | 5345 | or for lca or if tempreg is PIC_CALL_REG |
f5040a92 AO |
5346 | lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) |
5347 | add $tempreg,$tempreg,$gp | |
5348 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) | |
5349 | ||
5350 | If we have a small constant, and this is a reference to | |
5351 | an external symbol, we want | |
5352 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5353 | add $tempreg,$tempreg,$gp | |
5354 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5355 | addi $tempreg,$tempreg,<constant> | |
5356 | ||
5357 | If we have a large constant, and this is a reference to | |
5358 | an external symbol, we want | |
5359 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5360 | addu $tempreg,$tempreg,$gp | |
5361 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5362 | lui $at,<hiconstant> | |
5363 | addi $at,$at,<loconstant> | |
5364 | add $tempreg,$tempreg,$at | |
5365 | ||
5366 | If we have NewABI, and we know it's a local symbol, we want | |
5367 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
5368 | addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) | |
5369 | otherwise we have to resort to GOT_HI16/GOT_LO16. */ | |
5370 | ||
4d7206a2 | 5371 | relax_start (offset_expr.X_add_symbol); |
f5040a92 | 5372 | |
4d7206a2 | 5373 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
5374 | offset_expr.X_add_number = 0; |
5375 | ||
1abe91b1 MR |
5376 | if (expr1.X_add_number == 0 && breg == 0 |
5377 | && (call || tempreg == PIC_CALL_REG)) | |
f5040a92 AO |
5378 | { |
5379 | lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; | |
5380 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; | |
5381 | } | |
67c0d1eb RS |
5382 | macro_build (&offset_expr, "lui", "t,u", tempreg, lui_reloc_type); |
5383 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 5384 | tempreg, tempreg, mips_gp_register); |
67c0d1eb RS |
5385 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5386 | tempreg, lw_reloc_type, tempreg); | |
f5040a92 AO |
5387 | |
5388 | if (expr1.X_add_number == 0) | |
4d7206a2 | 5389 | ; |
f5040a92 AO |
5390 | else if (expr1.X_add_number >= -0x8000 |
5391 | && expr1.X_add_number < 0x8000) | |
5392 | { | |
67c0d1eb | 5393 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 5394 | tempreg, tempreg, BFD_RELOC_LO16); |
f5040a92 | 5395 | } |
ecd13cd3 | 5396 | else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000)) |
f5040a92 AO |
5397 | { |
5398 | int dreg; | |
5399 | ||
5400 | /* If we are going to add in a base register, and the | |
5401 | target register and the base register are the same, | |
5402 | then we are using AT as a temporary register. Since | |
5403 | we want to load the constant into AT, we add our | |
5404 | current AT (from the global offset table) and the | |
5405 | register into the register now, and pretend we were | |
5406 | not using a base register. */ | |
5407 | if (breg != treg) | |
5408 | dreg = tempreg; | |
5409 | else | |
5410 | { | |
5411 | assert (tempreg == AT); | |
67c0d1eb | 5412 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5413 | treg, AT, breg); |
f5040a92 | 5414 | dreg = treg; |
67c0d1eb | 5415 | add_breg_early = 1; |
f5040a92 AO |
5416 | } |
5417 | ||
f6a22291 | 5418 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 5419 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT); |
f5040a92 | 5420 | |
f5040a92 AO |
5421 | used_at = 1; |
5422 | } | |
5423 | else | |
5424 | as_bad (_("PIC code offset overflow (max 32 signed bits)")); | |
5425 | ||
4d7206a2 | 5426 | relax_switch (); |
f5040a92 | 5427 | offset_expr.X_add_number = expr1.X_add_number; |
67c0d1eb RS |
5428 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5429 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
5430 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, | |
5431 | tempreg, BFD_RELOC_MIPS_GOT_OFST); | |
5432 | if (add_breg_early) | |
f5040a92 | 5433 | { |
67c0d1eb | 5434 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5435 | treg, tempreg, breg); |
f5040a92 AO |
5436 | breg = 0; |
5437 | tempreg = treg; | |
5438 | } | |
4d7206a2 | 5439 | relax_end (); |
f5040a92 | 5440 | } |
252b5132 RH |
5441 | else |
5442 | abort (); | |
5443 | ||
5444 | if (breg != 0) | |
aed1a261 | 5445 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", treg, tempreg, breg); |
252b5132 RH |
5446 | break; |
5447 | ||
5448 | case M_J_A: | |
5449 | /* The j instruction may not be used in PIC code, since it | |
5450 | requires an absolute address. We convert it to a b | |
5451 | instruction. */ | |
5452 | if (mips_pic == NO_PIC) | |
67c0d1eb | 5453 | macro_build (&offset_expr, "j", "a"); |
252b5132 | 5454 | else |
67c0d1eb | 5455 | macro_build (&offset_expr, "b", "p"); |
8fc2e39e | 5456 | break; |
252b5132 RH |
5457 | |
5458 | /* The jal instructions must be handled as macros because when | |
5459 | generating PIC code they expand to multi-instruction | |
5460 | sequences. Normally they are simple instructions. */ | |
5461 | case M_JAL_1: | |
5462 | dreg = RA; | |
5463 | /* Fall through. */ | |
5464 | case M_JAL_2: | |
3e722fb5 | 5465 | if (mips_pic == NO_PIC) |
67c0d1eb | 5466 | macro_build (NULL, "jalr", "d,s", dreg, sreg); |
252b5132 RH |
5467 | else if (mips_pic == SVR4_PIC) |
5468 | { | |
5469 | if (sreg != PIC_CALL_REG) | |
5470 | as_warn (_("MIPS PIC call to register other than $25")); | |
bdaaa2e1 | 5471 | |
67c0d1eb | 5472 | macro_build (NULL, "jalr", "d,s", dreg, sreg); |
6478892d | 5473 | if (! HAVE_NEWABI) |
252b5132 | 5474 | { |
6478892d TS |
5475 | if (mips_cprestore_offset < 0) |
5476 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
5477 | else | |
5478 | { | |
7a621144 DJ |
5479 | if (! mips_frame_reg_valid) |
5480 | { | |
5481 | as_warn (_("No .frame pseudo-op used in PIC code")); | |
5482 | /* Quiet this warning. */ | |
5483 | mips_frame_reg_valid = 1; | |
5484 | } | |
5485 | if (! mips_cprestore_valid) | |
5486 | { | |
5487 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
5488 | /* Quiet this warning. */ | |
5489 | mips_cprestore_valid = 1; | |
5490 | } | |
6478892d | 5491 | expr1.X_add_number = mips_cprestore_offset; |
67c0d1eb | 5492 | macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN, |
f899b4b8 | 5493 | mips_gp_register, |
256ab948 TS |
5494 | mips_frame_reg, |
5495 | HAVE_64BIT_ADDRESSES); | |
6478892d | 5496 | } |
252b5132 RH |
5497 | } |
5498 | } | |
5499 | else | |
5500 | abort (); | |
5501 | ||
8fc2e39e | 5502 | break; |
252b5132 RH |
5503 | |
5504 | case M_JAL_A: | |
5505 | if (mips_pic == NO_PIC) | |
67c0d1eb | 5506 | macro_build (&offset_expr, "jal", "a"); |
252b5132 RH |
5507 | else if (mips_pic == SVR4_PIC) |
5508 | { | |
5509 | /* If this is a reference to an external symbol, and we are | |
5510 | using a small GOT, we want | |
5511 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16) | |
5512 | nop | |
f9419b05 | 5513 | jalr $ra,$25 |
252b5132 RH |
5514 | nop |
5515 | lw $gp,cprestore($sp) | |
5516 | The cprestore value is set using the .cprestore | |
5517 | pseudo-op. If we are using a big GOT, we want | |
5518 | lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16) | |
5519 | addu $25,$25,$gp | |
5520 | lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16) | |
5521 | nop | |
f9419b05 | 5522 | jalr $ra,$25 |
252b5132 RH |
5523 | nop |
5524 | lw $gp,cprestore($sp) | |
5525 | If the symbol is not external, we want | |
5526 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5527 | nop | |
5528 | addiu $25,$25,<sym> (BFD_RELOC_LO16) | |
f9419b05 | 5529 | jalr $ra,$25 |
252b5132 | 5530 | nop |
438c16b8 | 5531 | lw $gp,cprestore($sp) |
f5040a92 AO |
5532 | |
5533 | For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16 | |
5534 | sequences above, minus nops, unless the symbol is local, | |
5535 | which enables us to use GOT_PAGE/GOT_OFST (big got) or | |
5536 | GOT_DISP. */ | |
438c16b8 | 5537 | if (HAVE_NEWABI) |
252b5132 | 5538 | { |
f5040a92 AO |
5539 | if (! mips_big_got) |
5540 | { | |
4d7206a2 | 5541 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
5542 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5543 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL16, | |
f5040a92 | 5544 | mips_gp_register); |
4d7206a2 | 5545 | relax_switch (); |
67c0d1eb RS |
5546 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5547 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT_DISP, | |
4d7206a2 RS |
5548 | mips_gp_register); |
5549 | relax_end (); | |
f5040a92 AO |
5550 | } |
5551 | else | |
5552 | { | |
4d7206a2 | 5553 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
5554 | macro_build (&offset_expr, "lui", "t,u", PIC_CALL_REG, |
5555 | BFD_RELOC_MIPS_CALL_HI16); | |
5556 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG, | |
5557 | PIC_CALL_REG, mips_gp_register); | |
5558 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", | |
5559 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16, | |
5560 | PIC_CALL_REG); | |
4d7206a2 | 5561 | relax_switch (); |
67c0d1eb RS |
5562 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5563 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT_PAGE, | |
5564 | mips_gp_register); | |
5565 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
5566 | PIC_CALL_REG, PIC_CALL_REG, | |
17a2f251 | 5567 | BFD_RELOC_MIPS_GOT_OFST); |
4d7206a2 | 5568 | relax_end (); |
f5040a92 | 5569 | } |
684022ea | 5570 | |
67c0d1eb | 5571 | macro_build_jalr (&offset_expr); |
252b5132 RH |
5572 | } |
5573 | else | |
5574 | { | |
4d7206a2 | 5575 | relax_start (offset_expr.X_add_symbol); |
438c16b8 TS |
5576 | if (! mips_big_got) |
5577 | { | |
67c0d1eb RS |
5578 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5579 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL16, | |
17a2f251 | 5580 | mips_gp_register); |
269137b2 | 5581 | load_delay_nop (); |
4d7206a2 | 5582 | relax_switch (); |
438c16b8 | 5583 | } |
252b5132 | 5584 | else |
252b5132 | 5585 | { |
67c0d1eb RS |
5586 | int gpdelay; |
5587 | ||
5588 | gpdelay = reg_needs_delay (mips_gp_register); | |
5589 | macro_build (&offset_expr, "lui", "t,u", PIC_CALL_REG, | |
5590 | BFD_RELOC_MIPS_CALL_HI16); | |
5591 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG, | |
5592 | PIC_CALL_REG, mips_gp_register); | |
5593 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", | |
5594 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16, | |
5595 | PIC_CALL_REG); | |
269137b2 | 5596 | load_delay_nop (); |
4d7206a2 | 5597 | relax_switch (); |
67c0d1eb RS |
5598 | if (gpdelay) |
5599 | macro_build (NULL, "nop", ""); | |
252b5132 | 5600 | } |
67c0d1eb RS |
5601 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5602 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT16, | |
4d7206a2 | 5603 | mips_gp_register); |
269137b2 | 5604 | load_delay_nop (); |
67c0d1eb RS |
5605 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
5606 | PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16); | |
4d7206a2 | 5607 | relax_end (); |
67c0d1eb | 5608 | macro_build_jalr (&offset_expr); |
438c16b8 | 5609 | |
6478892d TS |
5610 | if (mips_cprestore_offset < 0) |
5611 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
5612 | else | |
5613 | { | |
7a621144 DJ |
5614 | if (! mips_frame_reg_valid) |
5615 | { | |
5616 | as_warn (_("No .frame pseudo-op used in PIC code")); | |
5617 | /* Quiet this warning. */ | |
5618 | mips_frame_reg_valid = 1; | |
5619 | } | |
5620 | if (! mips_cprestore_valid) | |
5621 | { | |
5622 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
5623 | /* Quiet this warning. */ | |
5624 | mips_cprestore_valid = 1; | |
5625 | } | |
6478892d | 5626 | if (mips_opts.noreorder) |
67c0d1eb | 5627 | macro_build (NULL, "nop", ""); |
6478892d | 5628 | expr1.X_add_number = mips_cprestore_offset; |
67c0d1eb | 5629 | macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN, |
f899b4b8 | 5630 | mips_gp_register, |
256ab948 TS |
5631 | mips_frame_reg, |
5632 | HAVE_64BIT_ADDRESSES); | |
6478892d | 5633 | } |
252b5132 RH |
5634 | } |
5635 | } | |
252b5132 RH |
5636 | else |
5637 | abort (); | |
5638 | ||
8fc2e39e | 5639 | break; |
252b5132 RH |
5640 | |
5641 | case M_LB_AB: | |
5642 | s = "lb"; | |
5643 | goto ld; | |
5644 | case M_LBU_AB: | |
5645 | s = "lbu"; | |
5646 | goto ld; | |
5647 | case M_LH_AB: | |
5648 | s = "lh"; | |
5649 | goto ld; | |
5650 | case M_LHU_AB: | |
5651 | s = "lhu"; | |
5652 | goto ld; | |
5653 | case M_LW_AB: | |
5654 | s = "lw"; | |
5655 | goto ld; | |
5656 | case M_LWC0_AB: | |
5657 | s = "lwc0"; | |
bdaaa2e1 | 5658 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5659 | coproc = 1; |
5660 | goto ld; | |
5661 | case M_LWC1_AB: | |
5662 | s = "lwc1"; | |
bdaaa2e1 | 5663 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5664 | coproc = 1; |
5665 | goto ld; | |
5666 | case M_LWC2_AB: | |
5667 | s = "lwc2"; | |
bdaaa2e1 | 5668 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5669 | coproc = 1; |
5670 | goto ld; | |
5671 | case M_LWC3_AB: | |
5672 | s = "lwc3"; | |
bdaaa2e1 | 5673 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5674 | coproc = 1; |
5675 | goto ld; | |
5676 | case M_LWL_AB: | |
5677 | s = "lwl"; | |
5678 | lr = 1; | |
5679 | goto ld; | |
5680 | case M_LWR_AB: | |
5681 | s = "lwr"; | |
5682 | lr = 1; | |
5683 | goto ld; | |
5684 | case M_LDC1_AB: | |
fef14a42 | 5685 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
5686 | { |
5687 | as_bad (_("opcode not supported on this processor")); | |
8fc2e39e | 5688 | break; |
252b5132 RH |
5689 | } |
5690 | s = "ldc1"; | |
bdaaa2e1 | 5691 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5692 | coproc = 1; |
5693 | goto ld; | |
5694 | case M_LDC2_AB: | |
5695 | s = "ldc2"; | |
bdaaa2e1 | 5696 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5697 | coproc = 1; |
5698 | goto ld; | |
5699 | case M_LDC3_AB: | |
5700 | s = "ldc3"; | |
bdaaa2e1 | 5701 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5702 | coproc = 1; |
5703 | goto ld; | |
5704 | case M_LDL_AB: | |
5705 | s = "ldl"; | |
5706 | lr = 1; | |
5707 | goto ld; | |
5708 | case M_LDR_AB: | |
5709 | s = "ldr"; | |
5710 | lr = 1; | |
5711 | goto ld; | |
5712 | case M_LL_AB: | |
5713 | s = "ll"; | |
5714 | goto ld; | |
5715 | case M_LLD_AB: | |
5716 | s = "lld"; | |
5717 | goto ld; | |
5718 | case M_LWU_AB: | |
5719 | s = "lwu"; | |
5720 | ld: | |
8fc2e39e | 5721 | if (breg == treg || coproc || lr) |
252b5132 RH |
5722 | { |
5723 | tempreg = AT; | |
5724 | used_at = 1; | |
5725 | } | |
5726 | else | |
5727 | { | |
5728 | tempreg = treg; | |
252b5132 RH |
5729 | } |
5730 | goto ld_st; | |
5731 | case M_SB_AB: | |
5732 | s = "sb"; | |
5733 | goto st; | |
5734 | case M_SH_AB: | |
5735 | s = "sh"; | |
5736 | goto st; | |
5737 | case M_SW_AB: | |
5738 | s = "sw"; | |
5739 | goto st; | |
5740 | case M_SWC0_AB: | |
5741 | s = "swc0"; | |
bdaaa2e1 | 5742 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5743 | coproc = 1; |
5744 | goto st; | |
5745 | case M_SWC1_AB: | |
5746 | s = "swc1"; | |
bdaaa2e1 | 5747 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5748 | coproc = 1; |
5749 | goto st; | |
5750 | case M_SWC2_AB: | |
5751 | s = "swc2"; | |
bdaaa2e1 | 5752 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5753 | coproc = 1; |
5754 | goto st; | |
5755 | case M_SWC3_AB: | |
5756 | s = "swc3"; | |
bdaaa2e1 | 5757 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5758 | coproc = 1; |
5759 | goto st; | |
5760 | case M_SWL_AB: | |
5761 | s = "swl"; | |
5762 | goto st; | |
5763 | case M_SWR_AB: | |
5764 | s = "swr"; | |
5765 | goto st; | |
5766 | case M_SC_AB: | |
5767 | s = "sc"; | |
5768 | goto st; | |
5769 | case M_SCD_AB: | |
5770 | s = "scd"; | |
5771 | goto st; | |
5772 | case M_SDC1_AB: | |
fef14a42 | 5773 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
5774 | { |
5775 | as_bad (_("opcode not supported on this processor")); | |
8fc2e39e | 5776 | break; |
252b5132 RH |
5777 | } |
5778 | s = "sdc1"; | |
5779 | coproc = 1; | |
bdaaa2e1 | 5780 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5781 | goto st; |
5782 | case M_SDC2_AB: | |
5783 | s = "sdc2"; | |
bdaaa2e1 | 5784 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5785 | coproc = 1; |
5786 | goto st; | |
5787 | case M_SDC3_AB: | |
5788 | s = "sdc3"; | |
bdaaa2e1 | 5789 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5790 | coproc = 1; |
5791 | goto st; | |
5792 | case M_SDL_AB: | |
5793 | s = "sdl"; | |
5794 | goto st; | |
5795 | case M_SDR_AB: | |
5796 | s = "sdr"; | |
5797 | st: | |
8fc2e39e TS |
5798 | tempreg = AT; |
5799 | used_at = 1; | |
252b5132 | 5800 | ld_st: |
bdaaa2e1 | 5801 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5802 | if (mask == M_LWC1_AB |
5803 | || mask == M_SWC1_AB | |
5804 | || mask == M_LDC1_AB | |
5805 | || mask == M_SDC1_AB | |
5806 | || mask == M_L_DAB | |
5807 | || mask == M_S_DAB) | |
5808 | fmt = "T,o(b)"; | |
5809 | else if (coproc) | |
5810 | fmt = "E,o(b)"; | |
5811 | else | |
5812 | fmt = "t,o(b)"; | |
5813 | ||
5814 | if (offset_expr.X_op != O_constant | |
5815 | && offset_expr.X_op != O_symbol) | |
5816 | { | |
5817 | as_bad (_("expression too complex")); | |
5818 | offset_expr.X_op = O_constant; | |
5819 | } | |
5820 | ||
2051e8c4 MR |
5821 | if (HAVE_32BIT_ADDRESSES |
5822 | && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) | |
55e08f71 NC |
5823 | { |
5824 | char value [32]; | |
5825 | ||
5826 | sprintf_vma (value, offset_expr.X_add_number); | |
20e1fcfd | 5827 | as_bad (_("Number (0x%s) larger than 32 bits"), value); |
55e08f71 | 5828 | } |
2051e8c4 | 5829 | |
252b5132 RH |
5830 | /* A constant expression in PIC code can be handled just as it |
5831 | is in non PIC code. */ | |
aed1a261 RS |
5832 | if (offset_expr.X_op == O_constant) |
5833 | { | |
aed1a261 RS |
5834 | expr1.X_add_number = ((offset_expr.X_add_number + 0x8000) |
5835 | & ~(bfd_vma) 0xffff); | |
2051e8c4 | 5836 | normalize_address_expr (&expr1); |
aed1a261 RS |
5837 | load_register (tempreg, &expr1, HAVE_64BIT_ADDRESSES); |
5838 | if (breg != 0) | |
5839 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
5840 | tempreg, tempreg, breg); | |
5841 | macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, tempreg); | |
5842 | } | |
5843 | else if (mips_pic == NO_PIC) | |
252b5132 RH |
5844 | { |
5845 | /* If this is a reference to a GP relative symbol, and there | |
5846 | is no base register, we want | |
cdf6fd85 | 5847 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
252b5132 RH |
5848 | Otherwise, if there is no base register, we want |
5849 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
5850 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
5851 | If we have a constant, we need two instructions anyhow, | |
5852 | so we always use the latter form. | |
5853 | ||
5854 | If we have a base register, and this is a reference to a | |
5855 | GP relative symbol, we want | |
5856 | addu $tempreg,$breg,$gp | |
cdf6fd85 | 5857 | <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16) |
252b5132 RH |
5858 | Otherwise we want |
5859 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
5860 | addu $tempreg,$tempreg,$breg | |
5861 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
d6bc6245 | 5862 | With a constant we always use the latter case. |
76b3015f | 5863 | |
d6bc6245 TS |
5864 | With 64bit address space and no base register and $at usable, |
5865 | we want | |
5866 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5867 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
5868 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5869 | dsll32 $tempreg,0 | |
5870 | daddu $tempreg,$at | |
5871 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
5872 | If we have a base register, we want | |
5873 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5874 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
5875 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5876 | daddu $at,$breg | |
5877 | dsll32 $tempreg,0 | |
5878 | daddu $tempreg,$at | |
5879 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
5880 | ||
5881 | Without $at we can't generate the optimal path for superscalar | |
5882 | processors here since this would require two temporary registers. | |
5883 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5884 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5885 | dsll $tempreg,16 | |
5886 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
5887 | dsll $tempreg,16 | |
5888 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
5889 | If we have a base register, we want | |
5890 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5891 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5892 | dsll $tempreg,16 | |
5893 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
5894 | dsll $tempreg,16 | |
5895 | daddu $tempreg,$tempreg,$breg | |
5896 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
6373ee54 | 5897 | |
6caf9ef4 | 5898 | For GP relative symbols in 64bit address space we can use |
aed1a261 RS |
5899 | the same sequence as in 32bit address space. */ |
5900 | if (HAVE_64BIT_SYMBOLS) | |
d6bc6245 | 5901 | { |
aed1a261 | 5902 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 TS |
5903 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
5904 | { | |
5905 | relax_start (offset_expr.X_add_symbol); | |
5906 | if (breg == 0) | |
5907 | { | |
5908 | macro_build (&offset_expr, s, fmt, treg, | |
5909 | BFD_RELOC_GPREL16, mips_gp_register); | |
5910 | } | |
5911 | else | |
5912 | { | |
5913 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
5914 | tempreg, breg, mips_gp_register); | |
5915 | macro_build (&offset_expr, s, fmt, treg, | |
5916 | BFD_RELOC_GPREL16, tempreg); | |
5917 | } | |
5918 | relax_switch (); | |
5919 | } | |
d6bc6245 | 5920 | |
b8285c27 | 5921 | if (used_at == 0 && !mips_opts.noat) |
d6bc6245 | 5922 | { |
67c0d1eb RS |
5923 | macro_build (&offset_expr, "lui", "t,u", tempreg, |
5924 | BFD_RELOC_MIPS_HIGHEST); | |
5925 | macro_build (&offset_expr, "lui", "t,u", AT, | |
5926 | BFD_RELOC_HI16_S); | |
5927 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
5928 | tempreg, BFD_RELOC_MIPS_HIGHER); | |
d6bc6245 | 5929 | if (breg != 0) |
67c0d1eb RS |
5930 | macro_build (NULL, "daddu", "d,v,t", AT, AT, breg); |
5931 | macro_build (NULL, "dsll32", "d,w,<", tempreg, tempreg, 0); | |
5932 | macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT); | |
5933 | macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, | |
5934 | tempreg); | |
d6bc6245 TS |
5935 | used_at = 1; |
5936 | } | |
5937 | else | |
5938 | { | |
67c0d1eb RS |
5939 | macro_build (&offset_expr, "lui", "t,u", tempreg, |
5940 | BFD_RELOC_MIPS_HIGHEST); | |
5941 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
5942 | tempreg, BFD_RELOC_MIPS_HIGHER); | |
5943 | macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16); | |
5944 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
5945 | tempreg, BFD_RELOC_HI16_S); | |
5946 | macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16); | |
d6bc6245 | 5947 | if (breg != 0) |
67c0d1eb | 5948 | macro_build (NULL, "daddu", "d,v,t", |
17a2f251 | 5949 | tempreg, tempreg, breg); |
67c0d1eb | 5950 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 5951 | BFD_RELOC_LO16, tempreg); |
d6bc6245 | 5952 | } |
6caf9ef4 TS |
5953 | |
5954 | if (mips_relax.sequence) | |
5955 | relax_end (); | |
8fc2e39e | 5956 | break; |
d6bc6245 | 5957 | } |
256ab948 | 5958 | |
252b5132 RH |
5959 | if (breg == 0) |
5960 | { | |
67c0d1eb | 5961 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 5962 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 5963 | { |
4d7206a2 | 5964 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
5965 | macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_GPREL16, |
5966 | mips_gp_register); | |
4d7206a2 | 5967 | relax_switch (); |
252b5132 | 5968 | } |
67c0d1eb RS |
5969 | macro_build_lui (&offset_expr, tempreg); |
5970 | macro_build (&offset_expr, s, fmt, treg, | |
17a2f251 | 5971 | BFD_RELOC_LO16, tempreg); |
4d7206a2 RS |
5972 | if (mips_relax.sequence) |
5973 | relax_end (); | |
252b5132 RH |
5974 | } |
5975 | else | |
5976 | { | |
67c0d1eb | 5977 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 5978 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 5979 | { |
4d7206a2 | 5980 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 5981 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5982 | tempreg, breg, mips_gp_register); |
67c0d1eb | 5983 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 5984 | BFD_RELOC_GPREL16, tempreg); |
4d7206a2 | 5985 | relax_switch (); |
252b5132 | 5986 | } |
67c0d1eb RS |
5987 | macro_build_lui (&offset_expr, tempreg); |
5988 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 5989 | tempreg, tempreg, breg); |
67c0d1eb | 5990 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 5991 | BFD_RELOC_LO16, tempreg); |
4d7206a2 RS |
5992 | if (mips_relax.sequence) |
5993 | relax_end (); | |
252b5132 RH |
5994 | } |
5995 | } | |
5996 | else if (mips_pic == SVR4_PIC && ! mips_big_got) | |
5997 | { | |
ed6fb7bd | 5998 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
f9419b05 | 5999 | |
252b5132 RH |
6000 | /* If this is a reference to an external symbol, we want |
6001 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6002 | nop | |
6003 | <op> $treg,0($tempreg) | |
6004 | Otherwise we want | |
6005 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6006 | nop | |
6007 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
6008 | <op> $treg,0($tempreg) | |
f5040a92 AO |
6009 | |
6010 | For NewABI, we want | |
6011 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
6012 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) | |
6013 | ||
252b5132 RH |
6014 | If there is a base register, we add it to $tempreg before |
6015 | the <op>. If there is a constant, we stick it in the | |
6016 | <op> instruction. We don't handle constants larger than | |
6017 | 16 bits, because we have no way to load the upper 16 bits | |
6018 | (actually, we could handle them for the subset of cases | |
6019 | in which we are not using $at). */ | |
6020 | assert (offset_expr.X_op == O_symbol); | |
f5040a92 AO |
6021 | if (HAVE_NEWABI) |
6022 | { | |
67c0d1eb RS |
6023 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
6024 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
f5040a92 | 6025 | if (breg != 0) |
67c0d1eb | 6026 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6027 | tempreg, tempreg, breg); |
67c0d1eb | 6028 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 6029 | BFD_RELOC_MIPS_GOT_OFST, tempreg); |
f5040a92 AO |
6030 | break; |
6031 | } | |
252b5132 RH |
6032 | expr1.X_add_number = offset_expr.X_add_number; |
6033 | offset_expr.X_add_number = 0; | |
6034 | if (expr1.X_add_number < -0x8000 | |
6035 | || expr1.X_add_number >= 0x8000) | |
6036 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb RS |
6037 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
6038 | lw_reloc_type, mips_gp_register); | |
269137b2 | 6039 | load_delay_nop (); |
4d7206a2 RS |
6040 | relax_start (offset_expr.X_add_symbol); |
6041 | relax_switch (); | |
67c0d1eb RS |
6042 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, |
6043 | tempreg, BFD_RELOC_LO16); | |
4d7206a2 | 6044 | relax_end (); |
252b5132 | 6045 | if (breg != 0) |
67c0d1eb | 6046 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6047 | tempreg, tempreg, breg); |
67c0d1eb | 6048 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
252b5132 | 6049 | } |
f5040a92 | 6050 | else if (mips_pic == SVR4_PIC && ! HAVE_NEWABI) |
252b5132 | 6051 | { |
67c0d1eb | 6052 | int gpdelay; |
252b5132 RH |
6053 | |
6054 | /* If this is a reference to an external symbol, we want | |
6055 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
6056 | addu $tempreg,$tempreg,$gp | |
6057 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
6058 | <op> $treg,0($tempreg) | |
6059 | Otherwise we want | |
6060 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6061 | nop | |
6062 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
6063 | <op> $treg,0($tempreg) | |
6064 | If there is a base register, we add it to $tempreg before | |
6065 | the <op>. If there is a constant, we stick it in the | |
6066 | <op> instruction. We don't handle constants larger than | |
6067 | 16 bits, because we have no way to load the upper 16 bits | |
6068 | (actually, we could handle them for the subset of cases | |
f5040a92 | 6069 | in which we are not using $at). */ |
252b5132 RH |
6070 | assert (offset_expr.X_op == O_symbol); |
6071 | expr1.X_add_number = offset_expr.X_add_number; | |
6072 | offset_expr.X_add_number = 0; | |
6073 | if (expr1.X_add_number < -0x8000 | |
6074 | || expr1.X_add_number >= 0x8000) | |
6075 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 6076 | gpdelay = reg_needs_delay (mips_gp_register); |
4d7206a2 | 6077 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 6078 | macro_build (&offset_expr, "lui", "t,u", tempreg, |
17a2f251 | 6079 | BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
6080 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, |
6081 | mips_gp_register); | |
6082 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
6083 | BFD_RELOC_MIPS_GOT_LO16, tempreg); | |
4d7206a2 | 6084 | relax_switch (); |
67c0d1eb RS |
6085 | if (gpdelay) |
6086 | macro_build (NULL, "nop", ""); | |
6087 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
6088 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 6089 | load_delay_nop (); |
67c0d1eb RS |
6090 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, |
6091 | tempreg, BFD_RELOC_LO16); | |
4d7206a2 RS |
6092 | relax_end (); |
6093 | ||
252b5132 | 6094 | if (breg != 0) |
67c0d1eb | 6095 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6096 | tempreg, tempreg, breg); |
67c0d1eb | 6097 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
252b5132 | 6098 | } |
f5040a92 AO |
6099 | else if (mips_pic == SVR4_PIC && HAVE_NEWABI) |
6100 | { | |
f5040a92 AO |
6101 | /* If this is a reference to an external symbol, we want |
6102 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
6103 | add $tempreg,$tempreg,$gp | |
6104 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
6105 | <op> $treg,<ofst>($tempreg) | |
6106 | Otherwise, for local symbols, we want: | |
6107 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
6108 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */ | |
6109 | assert (offset_expr.X_op == O_symbol); | |
4d7206a2 | 6110 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
6111 | offset_expr.X_add_number = 0; |
6112 | if (expr1.X_add_number < -0x8000 | |
6113 | || expr1.X_add_number >= 0x8000) | |
6114 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4d7206a2 | 6115 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 6116 | macro_build (&offset_expr, "lui", "t,u", tempreg, |
17a2f251 | 6117 | BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
6118 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, |
6119 | mips_gp_register); | |
6120 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
6121 | BFD_RELOC_MIPS_GOT_LO16, tempreg); | |
f5040a92 | 6122 | if (breg != 0) |
67c0d1eb | 6123 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6124 | tempreg, tempreg, breg); |
67c0d1eb | 6125 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
684022ea | 6126 | |
4d7206a2 | 6127 | relax_switch (); |
f5040a92 | 6128 | offset_expr.X_add_number = expr1.X_add_number; |
67c0d1eb RS |
6129 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
6130 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
f5040a92 | 6131 | if (breg != 0) |
67c0d1eb | 6132 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6133 | tempreg, tempreg, breg); |
67c0d1eb | 6134 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 6135 | BFD_RELOC_MIPS_GOT_OFST, tempreg); |
4d7206a2 | 6136 | relax_end (); |
f5040a92 | 6137 | } |
252b5132 RH |
6138 | else |
6139 | abort (); | |
6140 | ||
252b5132 RH |
6141 | break; |
6142 | ||
6143 | case M_LI: | |
6144 | case M_LI_S: | |
67c0d1eb | 6145 | load_register (treg, &imm_expr, 0); |
8fc2e39e | 6146 | break; |
252b5132 RH |
6147 | |
6148 | case M_DLI: | |
67c0d1eb | 6149 | load_register (treg, &imm_expr, 1); |
8fc2e39e | 6150 | break; |
252b5132 RH |
6151 | |
6152 | case M_LI_SS: | |
6153 | if (imm_expr.X_op == O_constant) | |
6154 | { | |
8fc2e39e | 6155 | used_at = 1; |
67c0d1eb RS |
6156 | load_register (AT, &imm_expr, 0); |
6157 | macro_build (NULL, "mtc1", "t,G", AT, treg); | |
252b5132 RH |
6158 | break; |
6159 | } | |
6160 | else | |
6161 | { | |
6162 | assert (offset_expr.X_op == O_symbol | |
6163 | && strcmp (segment_name (S_GET_SEGMENT | |
6164 | (offset_expr.X_add_symbol)), | |
6165 | ".lit4") == 0 | |
6166 | && offset_expr.X_add_number == 0); | |
67c0d1eb | 6167 | macro_build (&offset_expr, "lwc1", "T,o(b)", treg, |
17a2f251 | 6168 | BFD_RELOC_MIPS_LITERAL, mips_gp_register); |
8fc2e39e | 6169 | break; |
252b5132 RH |
6170 | } |
6171 | ||
6172 | case M_LI_D: | |
ca4e0257 RS |
6173 | /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits |
6174 | wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high | |
6175 | order 32 bits of the value and the low order 32 bits are either | |
6176 | zero or in OFFSET_EXPR. */ | |
252b5132 RH |
6177 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) |
6178 | { | |
ca4e0257 | 6179 | if (HAVE_64BIT_GPRS) |
67c0d1eb | 6180 | load_register (treg, &imm_expr, 1); |
252b5132 RH |
6181 | else |
6182 | { | |
6183 | int hreg, lreg; | |
6184 | ||
6185 | if (target_big_endian) | |
6186 | { | |
6187 | hreg = treg; | |
6188 | lreg = treg + 1; | |
6189 | } | |
6190 | else | |
6191 | { | |
6192 | hreg = treg + 1; | |
6193 | lreg = treg; | |
6194 | } | |
6195 | ||
6196 | if (hreg <= 31) | |
67c0d1eb | 6197 | load_register (hreg, &imm_expr, 0); |
252b5132 RH |
6198 | if (lreg <= 31) |
6199 | { | |
6200 | if (offset_expr.X_op == O_absent) | |
67c0d1eb | 6201 | move_register (lreg, 0); |
252b5132 RH |
6202 | else |
6203 | { | |
6204 | assert (offset_expr.X_op == O_constant); | |
67c0d1eb | 6205 | load_register (lreg, &offset_expr, 0); |
252b5132 RH |
6206 | } |
6207 | } | |
6208 | } | |
8fc2e39e | 6209 | break; |
252b5132 RH |
6210 | } |
6211 | ||
6212 | /* We know that sym is in the .rdata section. First we get the | |
6213 | upper 16 bits of the address. */ | |
6214 | if (mips_pic == NO_PIC) | |
6215 | { | |
67c0d1eb | 6216 | macro_build_lui (&offset_expr, AT); |
8fc2e39e | 6217 | used_at = 1; |
252b5132 RH |
6218 | } |
6219 | else if (mips_pic == SVR4_PIC) | |
6220 | { | |
67c0d1eb RS |
6221 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, |
6222 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
8fc2e39e | 6223 | used_at = 1; |
252b5132 | 6224 | } |
252b5132 RH |
6225 | else |
6226 | abort (); | |
bdaaa2e1 | 6227 | |
252b5132 | 6228 | /* Now we load the register(s). */ |
ca4e0257 | 6229 | if (HAVE_64BIT_GPRS) |
8fc2e39e TS |
6230 | { |
6231 | used_at = 1; | |
6232 | macro_build (&offset_expr, "ld", "t,o(b)", treg, BFD_RELOC_LO16, AT); | |
6233 | } | |
252b5132 RH |
6234 | else |
6235 | { | |
8fc2e39e | 6236 | used_at = 1; |
67c0d1eb | 6237 | macro_build (&offset_expr, "lw", "t,o(b)", treg, BFD_RELOC_LO16, AT); |
f9419b05 | 6238 | if (treg != RA) |
252b5132 RH |
6239 | { |
6240 | /* FIXME: How in the world do we deal with the possible | |
6241 | overflow here? */ | |
6242 | offset_expr.X_add_number += 4; | |
67c0d1eb | 6243 | macro_build (&offset_expr, "lw", "t,o(b)", |
17a2f251 | 6244 | treg + 1, BFD_RELOC_LO16, AT); |
252b5132 RH |
6245 | } |
6246 | } | |
252b5132 RH |
6247 | break; |
6248 | ||
6249 | case M_LI_DD: | |
ca4e0257 RS |
6250 | /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits |
6251 | wide, IMM_EXPR is the entire value and the GPRs are known to be 64 | |
6252 | bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of | |
6253 | the value and the low order 32 bits are either zero or in | |
6254 | OFFSET_EXPR. */ | |
252b5132 RH |
6255 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) |
6256 | { | |
8fc2e39e | 6257 | used_at = 1; |
67c0d1eb | 6258 | load_register (AT, &imm_expr, HAVE_64BIT_FPRS); |
ca4e0257 RS |
6259 | if (HAVE_64BIT_FPRS) |
6260 | { | |
6261 | assert (HAVE_64BIT_GPRS); | |
67c0d1eb | 6262 | macro_build (NULL, "dmtc1", "t,S", AT, treg); |
ca4e0257 | 6263 | } |
252b5132 RH |
6264 | else |
6265 | { | |
67c0d1eb | 6266 | macro_build (NULL, "mtc1", "t,G", AT, treg + 1); |
252b5132 | 6267 | if (offset_expr.X_op == O_absent) |
67c0d1eb | 6268 | macro_build (NULL, "mtc1", "t,G", 0, treg); |
252b5132 RH |
6269 | else |
6270 | { | |
6271 | assert (offset_expr.X_op == O_constant); | |
67c0d1eb RS |
6272 | load_register (AT, &offset_expr, 0); |
6273 | macro_build (NULL, "mtc1", "t,G", AT, treg); | |
252b5132 RH |
6274 | } |
6275 | } | |
6276 | break; | |
6277 | } | |
6278 | ||
6279 | assert (offset_expr.X_op == O_symbol | |
6280 | && offset_expr.X_add_number == 0); | |
6281 | s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol)); | |
6282 | if (strcmp (s, ".lit8") == 0) | |
6283 | { | |
e7af610e | 6284 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 | 6285 | { |
67c0d1eb | 6286 | macro_build (&offset_expr, "ldc1", "T,o(b)", treg, |
17a2f251 | 6287 | BFD_RELOC_MIPS_LITERAL, mips_gp_register); |
8fc2e39e | 6288 | break; |
252b5132 | 6289 | } |
c9914766 | 6290 | breg = mips_gp_register; |
252b5132 RH |
6291 | r = BFD_RELOC_MIPS_LITERAL; |
6292 | goto dob; | |
6293 | } | |
6294 | else | |
6295 | { | |
6296 | assert (strcmp (s, RDATA_SECTION_NAME) == 0); | |
8fc2e39e | 6297 | used_at = 1; |
252b5132 | 6298 | if (mips_pic == SVR4_PIC) |
67c0d1eb RS |
6299 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, |
6300 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
252b5132 RH |
6301 | else |
6302 | { | |
6303 | /* FIXME: This won't work for a 64 bit address. */ | |
67c0d1eb | 6304 | macro_build_lui (&offset_expr, AT); |
252b5132 | 6305 | } |
bdaaa2e1 | 6306 | |
e7af610e | 6307 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 | 6308 | { |
67c0d1eb RS |
6309 | macro_build (&offset_expr, "ldc1", "T,o(b)", |
6310 | treg, BFD_RELOC_LO16, AT); | |
252b5132 RH |
6311 | break; |
6312 | } | |
6313 | breg = AT; | |
6314 | r = BFD_RELOC_LO16; | |
6315 | goto dob; | |
6316 | } | |
6317 | ||
6318 | case M_L_DOB: | |
fef14a42 | 6319 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
6320 | { |
6321 | as_bad (_("opcode not supported on this processor")); | |
8fc2e39e | 6322 | break; |
252b5132 RH |
6323 | } |
6324 | /* Even on a big endian machine $fn comes before $fn+1. We have | |
6325 | to adjust when loading from memory. */ | |
6326 | r = BFD_RELOC_LO16; | |
6327 | dob: | |
e7af610e | 6328 | assert (mips_opts.isa == ISA_MIPS1); |
67c0d1eb | 6329 | macro_build (&offset_expr, "lwc1", "T,o(b)", |
17a2f251 | 6330 | target_big_endian ? treg + 1 : treg, r, breg); |
252b5132 RH |
6331 | /* FIXME: A possible overflow which I don't know how to deal |
6332 | with. */ | |
6333 | offset_expr.X_add_number += 4; | |
67c0d1eb | 6334 | macro_build (&offset_expr, "lwc1", "T,o(b)", |
17a2f251 | 6335 | target_big_endian ? treg : treg + 1, r, breg); |
252b5132 RH |
6336 | break; |
6337 | ||
6338 | case M_L_DAB: | |
6339 | /* | |
6340 | * The MIPS assembler seems to check for X_add_number not | |
6341 | * being double aligned and generating: | |
6342 | * lui at,%hi(foo+1) | |
6343 | * addu at,at,v1 | |
6344 | * addiu at,at,%lo(foo+1) | |
6345 | * lwc1 f2,0(at) | |
6346 | * lwc1 f3,4(at) | |
6347 | * But, the resulting address is the same after relocation so why | |
6348 | * generate the extra instruction? | |
6349 | */ | |
fef14a42 | 6350 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
6351 | { |
6352 | as_bad (_("opcode not supported on this processor")); | |
8fc2e39e | 6353 | break; |
252b5132 | 6354 | } |
bdaaa2e1 | 6355 | /* Itbl support may require additional care here. */ |
252b5132 | 6356 | coproc = 1; |
e7af610e | 6357 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 RH |
6358 | { |
6359 | s = "ldc1"; | |
6360 | goto ld; | |
6361 | } | |
6362 | ||
6363 | s = "lwc1"; | |
6364 | fmt = "T,o(b)"; | |
6365 | goto ldd_std; | |
6366 | ||
6367 | case M_S_DAB: | |
fef14a42 | 6368 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
6369 | { |
6370 | as_bad (_("opcode not supported on this processor")); | |
8fc2e39e | 6371 | break; |
252b5132 RH |
6372 | } |
6373 | ||
e7af610e | 6374 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 RH |
6375 | { |
6376 | s = "sdc1"; | |
6377 | goto st; | |
6378 | } | |
6379 | ||
6380 | s = "swc1"; | |
6381 | fmt = "T,o(b)"; | |
bdaaa2e1 | 6382 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6383 | coproc = 1; |
6384 | goto ldd_std; | |
6385 | ||
6386 | case M_LD_AB: | |
ca4e0257 | 6387 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
6388 | { |
6389 | s = "ld"; | |
6390 | goto ld; | |
6391 | } | |
6392 | ||
6393 | s = "lw"; | |
6394 | fmt = "t,o(b)"; | |
6395 | goto ldd_std; | |
6396 | ||
6397 | case M_SD_AB: | |
ca4e0257 | 6398 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
6399 | { |
6400 | s = "sd"; | |
6401 | goto st; | |
6402 | } | |
6403 | ||
6404 | s = "sw"; | |
6405 | fmt = "t,o(b)"; | |
6406 | ||
6407 | ldd_std: | |
6408 | if (offset_expr.X_op != O_symbol | |
6409 | && offset_expr.X_op != O_constant) | |
6410 | { | |
6411 | as_bad (_("expression too complex")); | |
6412 | offset_expr.X_op = O_constant; | |
6413 | } | |
6414 | ||
2051e8c4 MR |
6415 | if (HAVE_32BIT_ADDRESSES |
6416 | && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) | |
55e08f71 NC |
6417 | { |
6418 | char value [32]; | |
6419 | ||
6420 | sprintf_vma (value, offset_expr.X_add_number); | |
20e1fcfd | 6421 | as_bad (_("Number (0x%s) larger than 32 bits"), value); |
55e08f71 | 6422 | } |
2051e8c4 | 6423 | |
252b5132 RH |
6424 | /* Even on a big endian machine $fn comes before $fn+1. We have |
6425 | to adjust when loading from memory. We set coproc if we must | |
6426 | load $fn+1 first. */ | |
bdaaa2e1 | 6427 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6428 | if (! target_big_endian) |
6429 | coproc = 0; | |
6430 | ||
6431 | if (mips_pic == NO_PIC | |
6432 | || offset_expr.X_op == O_constant) | |
6433 | { | |
6434 | /* If this is a reference to a GP relative symbol, we want | |
cdf6fd85 TS |
6435 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
6436 | <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16) | |
252b5132 RH |
6437 | If we have a base register, we use this |
6438 | addu $at,$breg,$gp | |
cdf6fd85 TS |
6439 | <op> $treg,<sym>($at) (BFD_RELOC_GPREL16) |
6440 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16) | |
252b5132 RH |
6441 | If this is not a GP relative symbol, we want |
6442 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
6443 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
6444 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
6445 | If there is a base register, we add it to $at after the | |
6446 | lui instruction. If there is a constant, we always use | |
6447 | the last case. */ | |
39a59cf8 MR |
6448 | if (offset_expr.X_op == O_symbol |
6449 | && (valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET | |
6caf9ef4 | 6450 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 6451 | { |
4d7206a2 | 6452 | relax_start (offset_expr.X_add_symbol); |
252b5132 RH |
6453 | if (breg == 0) |
6454 | { | |
c9914766 | 6455 | tempreg = mips_gp_register; |
252b5132 RH |
6456 | } |
6457 | else | |
6458 | { | |
67c0d1eb | 6459 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6460 | AT, breg, mips_gp_register); |
252b5132 | 6461 | tempreg = AT; |
252b5132 RH |
6462 | used_at = 1; |
6463 | } | |
6464 | ||
beae10d5 | 6465 | /* Itbl support may require additional care here. */ |
67c0d1eb | 6466 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 6467 | BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
6468 | offset_expr.X_add_number += 4; |
6469 | ||
6470 | /* Set mips_optimize to 2 to avoid inserting an | |
6471 | undesired nop. */ | |
6472 | hold_mips_optimize = mips_optimize; | |
6473 | mips_optimize = 2; | |
beae10d5 | 6474 | /* Itbl support may require additional care here. */ |
67c0d1eb | 6475 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 6476 | BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
6477 | mips_optimize = hold_mips_optimize; |
6478 | ||
4d7206a2 | 6479 | relax_switch (); |
252b5132 RH |
6480 | |
6481 | /* We just generated two relocs. When tc_gen_reloc | |
6482 | handles this case, it will skip the first reloc and | |
6483 | handle the second. The second reloc already has an | |
6484 | extra addend of 4, which we added above. We must | |
6485 | subtract it out, and then subtract another 4 to make | |
6486 | the first reloc come out right. The second reloc | |
6487 | will come out right because we are going to add 4 to | |
6488 | offset_expr when we build its instruction below. | |
6489 | ||
6490 | If we have a symbol, then we don't want to include | |
6491 | the offset, because it will wind up being included | |
6492 | when we generate the reloc. */ | |
6493 | ||
6494 | if (offset_expr.X_op == O_constant) | |
6495 | offset_expr.X_add_number -= 8; | |
6496 | else | |
6497 | { | |
6498 | offset_expr.X_add_number = -4; | |
6499 | offset_expr.X_op = O_constant; | |
6500 | } | |
6501 | } | |
8fc2e39e | 6502 | used_at = 1; |
67c0d1eb | 6503 | macro_build_lui (&offset_expr, AT); |
252b5132 | 6504 | if (breg != 0) |
67c0d1eb | 6505 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 6506 | /* Itbl support may require additional care here. */ |
67c0d1eb | 6507 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 6508 | BFD_RELOC_LO16, AT); |
252b5132 RH |
6509 | /* FIXME: How do we handle overflow here? */ |
6510 | offset_expr.X_add_number += 4; | |
beae10d5 | 6511 | /* Itbl support may require additional care here. */ |
67c0d1eb | 6512 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 6513 | BFD_RELOC_LO16, AT); |
4d7206a2 RS |
6514 | if (mips_relax.sequence) |
6515 | relax_end (); | |
bdaaa2e1 | 6516 | } |
252b5132 RH |
6517 | else if (mips_pic == SVR4_PIC && ! mips_big_got) |
6518 | { | |
252b5132 RH |
6519 | /* If this is a reference to an external symbol, we want |
6520 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6521 | nop | |
6522 | <op> $treg,0($at) | |
6523 | <op> $treg+1,4($at) | |
6524 | Otherwise we want | |
6525 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6526 | nop | |
6527 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
6528 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
6529 | If there is a base register we add it to $at before the | |
6530 | lwc1 instructions. If there is a constant we include it | |
6531 | in the lwc1 instructions. */ | |
6532 | used_at = 1; | |
6533 | expr1.X_add_number = offset_expr.X_add_number; | |
252b5132 RH |
6534 | if (expr1.X_add_number < -0x8000 |
6535 | || expr1.X_add_number >= 0x8000 - 4) | |
6536 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 6537 | load_got_offset (AT, &offset_expr); |
269137b2 | 6538 | load_delay_nop (); |
252b5132 | 6539 | if (breg != 0) |
67c0d1eb | 6540 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
252b5132 RH |
6541 | |
6542 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
6543 | nop. */ | |
6544 | hold_mips_optimize = mips_optimize; | |
6545 | mips_optimize = 2; | |
4d7206a2 | 6546 | |
beae10d5 | 6547 | /* Itbl support may require additional care here. */ |
4d7206a2 | 6548 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
6549 | macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg, |
6550 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 6551 | expr1.X_add_number += 4; |
67c0d1eb RS |
6552 | macro_build (&expr1, s, fmt, coproc ? treg : treg + 1, |
6553 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 6554 | relax_switch (); |
67c0d1eb RS |
6555 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
6556 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 6557 | offset_expr.X_add_number += 4; |
67c0d1eb RS |
6558 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
6559 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 6560 | relax_end (); |
252b5132 | 6561 | |
4d7206a2 | 6562 | mips_optimize = hold_mips_optimize; |
252b5132 RH |
6563 | } |
6564 | else if (mips_pic == SVR4_PIC) | |
6565 | { | |
67c0d1eb | 6566 | int gpdelay; |
252b5132 RH |
6567 | |
6568 | /* If this is a reference to an external symbol, we want | |
6569 | lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
6570 | addu $at,$at,$gp | |
6571 | lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16) | |
6572 | nop | |
6573 | <op> $treg,0($at) | |
6574 | <op> $treg+1,4($at) | |
6575 | Otherwise we want | |
6576 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6577 | nop | |
6578 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
6579 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
6580 | If there is a base register we add it to $at before the | |
6581 | lwc1 instructions. If there is a constant we include it | |
6582 | in the lwc1 instructions. */ | |
6583 | used_at = 1; | |
6584 | expr1.X_add_number = offset_expr.X_add_number; | |
6585 | offset_expr.X_add_number = 0; | |
6586 | if (expr1.X_add_number < -0x8000 | |
6587 | || expr1.X_add_number >= 0x8000 - 4) | |
6588 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 6589 | gpdelay = reg_needs_delay (mips_gp_register); |
4d7206a2 | 6590 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
6591 | macro_build (&offset_expr, "lui", "t,u", |
6592 | AT, BFD_RELOC_MIPS_GOT_HI16); | |
6593 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 6594 | AT, AT, mips_gp_register); |
67c0d1eb | 6595 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
17a2f251 | 6596 | AT, BFD_RELOC_MIPS_GOT_LO16, AT); |
269137b2 | 6597 | load_delay_nop (); |
252b5132 | 6598 | if (breg != 0) |
67c0d1eb | 6599 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 6600 | /* Itbl support may require additional care here. */ |
67c0d1eb | 6601 | macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 6602 | BFD_RELOC_LO16, AT); |
252b5132 RH |
6603 | expr1.X_add_number += 4; |
6604 | ||
6605 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
6606 | nop. */ | |
6607 | hold_mips_optimize = mips_optimize; | |
6608 | mips_optimize = 2; | |
beae10d5 | 6609 | /* Itbl support may require additional care here. */ |
67c0d1eb | 6610 | macro_build (&expr1, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 6611 | BFD_RELOC_LO16, AT); |
252b5132 RH |
6612 | mips_optimize = hold_mips_optimize; |
6613 | expr1.X_add_number -= 4; | |
6614 | ||
4d7206a2 RS |
6615 | relax_switch (); |
6616 | offset_expr.X_add_number = expr1.X_add_number; | |
67c0d1eb RS |
6617 | if (gpdelay) |
6618 | macro_build (NULL, "nop", ""); | |
6619 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, | |
6620 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 6621 | load_delay_nop (); |
252b5132 | 6622 | if (breg != 0) |
67c0d1eb | 6623 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 6624 | /* Itbl support may require additional care here. */ |
67c0d1eb RS |
6625 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
6626 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 6627 | offset_expr.X_add_number += 4; |
252b5132 RH |
6628 | |
6629 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
6630 | nop. */ | |
6631 | hold_mips_optimize = mips_optimize; | |
6632 | mips_optimize = 2; | |
beae10d5 | 6633 | /* Itbl support may require additional care here. */ |
67c0d1eb RS |
6634 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
6635 | BFD_RELOC_LO16, AT); | |
252b5132 | 6636 | mips_optimize = hold_mips_optimize; |
4d7206a2 | 6637 | relax_end (); |
252b5132 | 6638 | } |
252b5132 RH |
6639 | else |
6640 | abort (); | |
6641 | ||
252b5132 RH |
6642 | break; |
6643 | ||
6644 | case M_LD_OB: | |
6645 | s = "lw"; | |
6646 | goto sd_ob; | |
6647 | case M_SD_OB: | |
6648 | s = "sw"; | |
6649 | sd_ob: | |
ca4e0257 | 6650 | assert (HAVE_32BIT_ADDRESSES); |
67c0d1eb | 6651 | macro_build (&offset_expr, s, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
252b5132 | 6652 | offset_expr.X_add_number += 4; |
67c0d1eb | 6653 | macro_build (&offset_expr, s, "t,o(b)", treg + 1, BFD_RELOC_LO16, breg); |
8fc2e39e | 6654 | break; |
252b5132 RH |
6655 | |
6656 | /* New code added to support COPZ instructions. | |
6657 | This code builds table entries out of the macros in mip_opcodes. | |
6658 | R4000 uses interlocks to handle coproc delays. | |
6659 | Other chips (like the R3000) require nops to be inserted for delays. | |
6660 | ||
f72c8c98 | 6661 | FIXME: Currently, we require that the user handle delays. |
252b5132 RH |
6662 | In order to fill delay slots for non-interlocked chips, |
6663 | we must have a way to specify delays based on the coprocessor. | |
6664 | Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc. | |
6665 | What are the side-effects of the cop instruction? | |
6666 | What cache support might we have and what are its effects? | |
6667 | Both coprocessor & memory require delays. how long??? | |
bdaaa2e1 | 6668 | What registers are read/set/modified? |
252b5132 RH |
6669 | |
6670 | If an itbl is provided to interpret cop instructions, | |
bdaaa2e1 | 6671 | this knowledge can be encoded in the itbl spec. */ |
252b5132 RH |
6672 | |
6673 | case M_COP0: | |
6674 | s = "c0"; | |
6675 | goto copz; | |
6676 | case M_COP1: | |
6677 | s = "c1"; | |
6678 | goto copz; | |
6679 | case M_COP2: | |
6680 | s = "c2"; | |
6681 | goto copz; | |
6682 | case M_COP3: | |
6683 | s = "c3"; | |
6684 | copz: | |
6685 | /* For now we just do C (same as Cz). The parameter will be | |
6686 | stored in insn_opcode by mips_ip. */ | |
67c0d1eb | 6687 | macro_build (NULL, s, "C", ip->insn_opcode); |
8fc2e39e | 6688 | break; |
252b5132 | 6689 | |
ea1fb5dc | 6690 | case M_MOVE: |
67c0d1eb | 6691 | move_register (dreg, sreg); |
8fc2e39e | 6692 | break; |
ea1fb5dc | 6693 | |
252b5132 RH |
6694 | #ifdef LOSING_COMPILER |
6695 | default: | |
6696 | /* Try and see if this is a new itbl instruction. | |
6697 | This code builds table entries out of the macros in mip_opcodes. | |
6698 | FIXME: For now we just assemble the expression and pass it's | |
6699 | value along as a 32-bit immediate. | |
bdaaa2e1 | 6700 | We may want to have the assembler assemble this value, |
252b5132 RH |
6701 | so that we gain the assembler's knowledge of delay slots, |
6702 | symbols, etc. | |
6703 | Would it be more efficient to use mask (id) here? */ | |
bdaaa2e1 | 6704 | if (itbl_have_entries |
252b5132 | 6705 | && (immed_expr = itbl_assemble (ip->insn_mo->name, ""))) |
beae10d5 | 6706 | { |
252b5132 RH |
6707 | s = ip->insn_mo->name; |
6708 | s2 = "cop3"; | |
6709 | coproc = ITBL_DECODE_PNUM (immed_expr);; | |
67c0d1eb | 6710 | macro_build (&immed_expr, s, "C"); |
8fc2e39e | 6711 | break; |
beae10d5 | 6712 | } |
252b5132 | 6713 | macro2 (ip); |
8fc2e39e | 6714 | break; |
252b5132 | 6715 | } |
8fc2e39e TS |
6716 | if (mips_opts.noat && used_at) |
6717 | as_bad (_("Macro used $at after \".set noat\"")); | |
252b5132 | 6718 | } |
bdaaa2e1 | 6719 | |
252b5132 | 6720 | static void |
17a2f251 | 6721 | macro2 (struct mips_cl_insn *ip) |
252b5132 RH |
6722 | { |
6723 | register int treg, sreg, dreg, breg; | |
6724 | int tempreg; | |
6725 | int mask; | |
252b5132 RH |
6726 | int used_at; |
6727 | expressionS expr1; | |
6728 | const char *s; | |
6729 | const char *s2; | |
6730 | const char *fmt; | |
6731 | int likely = 0; | |
6732 | int dbl = 0; | |
6733 | int coproc = 0; | |
6734 | int lr = 0; | |
6735 | int imm = 0; | |
6736 | int off; | |
6737 | offsetT maxnum; | |
6738 | bfd_reloc_code_real_type r; | |
bdaaa2e1 | 6739 | |
252b5132 RH |
6740 | treg = (ip->insn_opcode >> 16) & 0x1f; |
6741 | dreg = (ip->insn_opcode >> 11) & 0x1f; | |
6742 | sreg = breg = (ip->insn_opcode >> 21) & 0x1f; | |
6743 | mask = ip->insn_mo->mask; | |
bdaaa2e1 | 6744 | |
252b5132 RH |
6745 | expr1.X_op = O_constant; |
6746 | expr1.X_op_symbol = NULL; | |
6747 | expr1.X_add_symbol = NULL; | |
6748 | expr1.X_add_number = 1; | |
bdaaa2e1 | 6749 | |
252b5132 RH |
6750 | switch (mask) |
6751 | { | |
6752 | #endif /* LOSING_COMPILER */ | |
6753 | ||
6754 | case M_DMUL: | |
6755 | dbl = 1; | |
6756 | case M_MUL: | |
67c0d1eb RS |
6757 | macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", sreg, treg); |
6758 | macro_build (NULL, "mflo", "d", dreg); | |
8fc2e39e | 6759 | break; |
252b5132 RH |
6760 | |
6761 | case M_DMUL_I: | |
6762 | dbl = 1; | |
6763 | case M_MUL_I: | |
6764 | /* The MIPS assembler some times generates shifts and adds. I'm | |
6765 | not trying to be that fancy. GCC should do this for us | |
6766 | anyway. */ | |
8fc2e39e | 6767 | used_at = 1; |
67c0d1eb RS |
6768 | load_register (AT, &imm_expr, dbl); |
6769 | macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, AT); | |
6770 | macro_build (NULL, "mflo", "d", dreg); | |
252b5132 RH |
6771 | break; |
6772 | ||
6773 | case M_DMULO_I: | |
6774 | dbl = 1; | |
6775 | case M_MULO_I: | |
6776 | imm = 1; | |
6777 | goto do_mulo; | |
6778 | ||
6779 | case M_DMULO: | |
6780 | dbl = 1; | |
6781 | case M_MULO: | |
6782 | do_mulo: | |
7d10b47d | 6783 | start_noreorder (); |
8fc2e39e | 6784 | used_at = 1; |
252b5132 | 6785 | if (imm) |
67c0d1eb RS |
6786 | load_register (AT, &imm_expr, dbl); |
6787 | macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, imm ? AT : treg); | |
6788 | macro_build (NULL, "mflo", "d", dreg); | |
6789 | macro_build (NULL, dbl ? "dsra32" : "sra", "d,w,<", dreg, dreg, RA); | |
6790 | macro_build (NULL, "mfhi", "d", AT); | |
252b5132 | 6791 | if (mips_trap) |
67c0d1eb | 6792 | macro_build (NULL, "tne", "s,t,q", dreg, AT, 6); |
252b5132 RH |
6793 | else |
6794 | { | |
6795 | expr1.X_add_number = 8; | |
67c0d1eb RS |
6796 | macro_build (&expr1, "beq", "s,t,p", dreg, AT); |
6797 | macro_build (NULL, "nop", "", 0); | |
6798 | macro_build (NULL, "break", "c", 6); | |
252b5132 | 6799 | } |
7d10b47d | 6800 | end_noreorder (); |
67c0d1eb | 6801 | macro_build (NULL, "mflo", "d", dreg); |
252b5132 RH |
6802 | break; |
6803 | ||
6804 | case M_DMULOU_I: | |
6805 | dbl = 1; | |
6806 | case M_MULOU_I: | |
6807 | imm = 1; | |
6808 | goto do_mulou; | |
6809 | ||
6810 | case M_DMULOU: | |
6811 | dbl = 1; | |
6812 | case M_MULOU: | |
6813 | do_mulou: | |
7d10b47d | 6814 | start_noreorder (); |
8fc2e39e | 6815 | used_at = 1; |
252b5132 | 6816 | if (imm) |
67c0d1eb RS |
6817 | load_register (AT, &imm_expr, dbl); |
6818 | macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", | |
17a2f251 | 6819 | sreg, imm ? AT : treg); |
67c0d1eb RS |
6820 | macro_build (NULL, "mfhi", "d", AT); |
6821 | macro_build (NULL, "mflo", "d", dreg); | |
252b5132 | 6822 | if (mips_trap) |
67c0d1eb | 6823 | macro_build (NULL, "tne", "s,t,q", AT, 0, 6); |
252b5132 RH |
6824 | else |
6825 | { | |
6826 | expr1.X_add_number = 8; | |
67c0d1eb RS |
6827 | macro_build (&expr1, "beq", "s,t,p", AT, 0); |
6828 | macro_build (NULL, "nop", "", 0); | |
6829 | macro_build (NULL, "break", "c", 6); | |
252b5132 | 6830 | } |
7d10b47d | 6831 | end_noreorder (); |
252b5132 RH |
6832 | break; |
6833 | ||
771c7ce4 | 6834 | case M_DROL: |
fef14a42 | 6835 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 CD |
6836 | { |
6837 | if (dreg == sreg) | |
6838 | { | |
6839 | tempreg = AT; | |
6840 | used_at = 1; | |
6841 | } | |
6842 | else | |
6843 | { | |
6844 | tempreg = dreg; | |
82dd0097 | 6845 | } |
67c0d1eb RS |
6846 | macro_build (NULL, "dnegu", "d,w", tempreg, treg); |
6847 | macro_build (NULL, "drorv", "d,t,s", dreg, sreg, tempreg); | |
8fc2e39e | 6848 | break; |
82dd0097 | 6849 | } |
8fc2e39e | 6850 | used_at = 1; |
67c0d1eb RS |
6851 | macro_build (NULL, "dsubu", "d,v,t", AT, 0, treg); |
6852 | macro_build (NULL, "dsrlv", "d,t,s", AT, sreg, AT); | |
6853 | macro_build (NULL, "dsllv", "d,t,s", dreg, sreg, treg); | |
6854 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
6855 | break; |
6856 | ||
252b5132 | 6857 | case M_ROL: |
fef14a42 | 6858 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 CD |
6859 | { |
6860 | if (dreg == sreg) | |
6861 | { | |
6862 | tempreg = AT; | |
6863 | used_at = 1; | |
6864 | } | |
6865 | else | |
6866 | { | |
6867 | tempreg = dreg; | |
82dd0097 | 6868 | } |
67c0d1eb RS |
6869 | macro_build (NULL, "negu", "d,w", tempreg, treg); |
6870 | macro_build (NULL, "rorv", "d,t,s", dreg, sreg, tempreg); | |
8fc2e39e | 6871 | break; |
82dd0097 | 6872 | } |
8fc2e39e | 6873 | used_at = 1; |
67c0d1eb RS |
6874 | macro_build (NULL, "subu", "d,v,t", AT, 0, treg); |
6875 | macro_build (NULL, "srlv", "d,t,s", AT, sreg, AT); | |
6876 | macro_build (NULL, "sllv", "d,t,s", dreg, sreg, treg); | |
6877 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
6878 | break; |
6879 | ||
771c7ce4 TS |
6880 | case M_DROL_I: |
6881 | { | |
6882 | unsigned int rot; | |
82dd0097 | 6883 | char *l, *r; |
771c7ce4 TS |
6884 | |
6885 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 6886 | as_bad (_("Improper rotate count")); |
771c7ce4 | 6887 | rot = imm_expr.X_add_number & 0x3f; |
fef14a42 | 6888 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
60b63b72 RS |
6889 | { |
6890 | rot = (64 - rot) & 0x3f; | |
6891 | if (rot >= 32) | |
67c0d1eb | 6892 | macro_build (NULL, "dror32", "d,w,<", dreg, sreg, rot - 32); |
60b63b72 | 6893 | else |
67c0d1eb | 6894 | macro_build (NULL, "dror", "d,w,<", dreg, sreg, rot); |
8fc2e39e | 6895 | break; |
60b63b72 | 6896 | } |
483fc7cd | 6897 | if (rot == 0) |
483fc7cd | 6898 | { |
67c0d1eb | 6899 | macro_build (NULL, "dsrl", "d,w,<", dreg, sreg, 0); |
8fc2e39e | 6900 | break; |
483fc7cd | 6901 | } |
82dd0097 CD |
6902 | l = (rot < 0x20) ? "dsll" : "dsll32"; |
6903 | r = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32"; | |
6904 | rot &= 0x1f; | |
8fc2e39e | 6905 | used_at = 1; |
67c0d1eb RS |
6906 | macro_build (NULL, l, "d,w,<", AT, sreg, rot); |
6907 | macro_build (NULL, r, "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); | |
6908 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
6909 | } |
6910 | break; | |
6911 | ||
252b5132 | 6912 | case M_ROL_I: |
771c7ce4 TS |
6913 | { |
6914 | unsigned int rot; | |
6915 | ||
6916 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 6917 | as_bad (_("Improper rotate count")); |
771c7ce4 | 6918 | rot = imm_expr.X_add_number & 0x1f; |
fef14a42 | 6919 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
60b63b72 | 6920 | { |
67c0d1eb | 6921 | macro_build (NULL, "ror", "d,w,<", dreg, sreg, (32 - rot) & 0x1f); |
8fc2e39e | 6922 | break; |
60b63b72 | 6923 | } |
483fc7cd | 6924 | if (rot == 0) |
483fc7cd | 6925 | { |
67c0d1eb | 6926 | macro_build (NULL, "srl", "d,w,<", dreg, sreg, 0); |
8fc2e39e | 6927 | break; |
483fc7cd | 6928 | } |
8fc2e39e | 6929 | used_at = 1; |
67c0d1eb RS |
6930 | macro_build (NULL, "sll", "d,w,<", AT, sreg, rot); |
6931 | macro_build (NULL, "srl", "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); | |
6932 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
6933 | } |
6934 | break; | |
6935 | ||
6936 | case M_DROR: | |
fef14a42 | 6937 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 | 6938 | { |
67c0d1eb | 6939 | macro_build (NULL, "drorv", "d,t,s", dreg, sreg, treg); |
8fc2e39e | 6940 | break; |
82dd0097 | 6941 | } |
8fc2e39e | 6942 | used_at = 1; |
67c0d1eb RS |
6943 | macro_build (NULL, "dsubu", "d,v,t", AT, 0, treg); |
6944 | macro_build (NULL, "dsllv", "d,t,s", AT, sreg, AT); | |
6945 | macro_build (NULL, "dsrlv", "d,t,s", dreg, sreg, treg); | |
6946 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
6947 | break; |
6948 | ||
6949 | case M_ROR: | |
fef14a42 | 6950 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 | 6951 | { |
67c0d1eb | 6952 | macro_build (NULL, "rorv", "d,t,s", dreg, sreg, treg); |
8fc2e39e | 6953 | break; |
82dd0097 | 6954 | } |
8fc2e39e | 6955 | used_at = 1; |
67c0d1eb RS |
6956 | macro_build (NULL, "subu", "d,v,t", AT, 0, treg); |
6957 | macro_build (NULL, "sllv", "d,t,s", AT, sreg, AT); | |
6958 | macro_build (NULL, "srlv", "d,t,s", dreg, sreg, treg); | |
6959 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
6960 | break; |
6961 | ||
771c7ce4 TS |
6962 | case M_DROR_I: |
6963 | { | |
6964 | unsigned int rot; | |
82dd0097 | 6965 | char *l, *r; |
771c7ce4 TS |
6966 | |
6967 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 6968 | as_bad (_("Improper rotate count")); |
771c7ce4 | 6969 | rot = imm_expr.X_add_number & 0x3f; |
fef14a42 | 6970 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 CD |
6971 | { |
6972 | if (rot >= 32) | |
67c0d1eb | 6973 | macro_build (NULL, "dror32", "d,w,<", dreg, sreg, rot - 32); |
82dd0097 | 6974 | else |
67c0d1eb | 6975 | macro_build (NULL, "dror", "d,w,<", dreg, sreg, rot); |
8fc2e39e | 6976 | break; |
82dd0097 | 6977 | } |
483fc7cd | 6978 | if (rot == 0) |
483fc7cd | 6979 | { |
67c0d1eb | 6980 | macro_build (NULL, "dsrl", "d,w,<", dreg, sreg, 0); |
8fc2e39e | 6981 | break; |
483fc7cd | 6982 | } |
82dd0097 CD |
6983 | r = (rot < 0x20) ? "dsrl" : "dsrl32"; |
6984 | l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32"; | |
6985 | rot &= 0x1f; | |
8fc2e39e | 6986 | used_at = 1; |
67c0d1eb RS |
6987 | macro_build (NULL, r, "d,w,<", AT, sreg, rot); |
6988 | macro_build (NULL, l, "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); | |
6989 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
6990 | } |
6991 | break; | |
6992 | ||
252b5132 | 6993 | case M_ROR_I: |
771c7ce4 TS |
6994 | { |
6995 | unsigned int rot; | |
6996 | ||
6997 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 6998 | as_bad (_("Improper rotate count")); |
771c7ce4 | 6999 | rot = imm_expr.X_add_number & 0x1f; |
fef14a42 | 7000 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 | 7001 | { |
67c0d1eb | 7002 | macro_build (NULL, "ror", "d,w,<", dreg, sreg, rot); |
8fc2e39e | 7003 | break; |
82dd0097 | 7004 | } |
483fc7cd | 7005 | if (rot == 0) |
483fc7cd | 7006 | { |
67c0d1eb | 7007 | macro_build (NULL, "srl", "d,w,<", dreg, sreg, 0); |
8fc2e39e | 7008 | break; |
483fc7cd | 7009 | } |
8fc2e39e | 7010 | used_at = 1; |
67c0d1eb RS |
7011 | macro_build (NULL, "srl", "d,w,<", AT, sreg, rot); |
7012 | macro_build (NULL, "sll", "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); | |
7013 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 | 7014 | } |
252b5132 RH |
7015 | break; |
7016 | ||
7017 | case M_S_DOB: | |
fef14a42 | 7018 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
7019 | { |
7020 | as_bad (_("opcode not supported on this processor")); | |
8fc2e39e | 7021 | break; |
252b5132 | 7022 | } |
e7af610e | 7023 | assert (mips_opts.isa == ISA_MIPS1); |
252b5132 RH |
7024 | /* Even on a big endian machine $fn comes before $fn+1. We have |
7025 | to adjust when storing to memory. */ | |
67c0d1eb RS |
7026 | macro_build (&offset_expr, "swc1", "T,o(b)", |
7027 | target_big_endian ? treg + 1 : treg, BFD_RELOC_LO16, breg); | |
252b5132 | 7028 | offset_expr.X_add_number += 4; |
67c0d1eb RS |
7029 | macro_build (&offset_expr, "swc1", "T,o(b)", |
7030 | target_big_endian ? treg : treg + 1, BFD_RELOC_LO16, breg); | |
8fc2e39e | 7031 | break; |
252b5132 RH |
7032 | |
7033 | case M_SEQ: | |
7034 | if (sreg == 0) | |
67c0d1eb | 7035 | macro_build (&expr1, "sltiu", "t,r,j", dreg, treg, BFD_RELOC_LO16); |
252b5132 | 7036 | else if (treg == 0) |
67c0d1eb | 7037 | macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7038 | else |
7039 | { | |
67c0d1eb RS |
7040 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg); |
7041 | macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16); | |
252b5132 | 7042 | } |
8fc2e39e | 7043 | break; |
252b5132 RH |
7044 | |
7045 | case M_SEQ_I: | |
7046 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
7047 | { | |
67c0d1eb | 7048 | macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 7049 | break; |
252b5132 RH |
7050 | } |
7051 | if (sreg == 0) | |
7052 | { | |
7053 | as_warn (_("Instruction %s: result is always false"), | |
7054 | ip->insn_mo->name); | |
67c0d1eb | 7055 | move_register (dreg, 0); |
8fc2e39e | 7056 | break; |
252b5132 RH |
7057 | } |
7058 | if (imm_expr.X_op == O_constant | |
7059 | && imm_expr.X_add_number >= 0 | |
7060 | && imm_expr.X_add_number < 0x10000) | |
7061 | { | |
67c0d1eb | 7062 | macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7063 | } |
7064 | else if (imm_expr.X_op == O_constant | |
7065 | && imm_expr.X_add_number > -0x8000 | |
7066 | && imm_expr.X_add_number < 0) | |
7067 | { | |
7068 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 7069 | macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu", |
17a2f251 | 7070 | "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7071 | } |
7072 | else | |
7073 | { | |
67c0d1eb RS |
7074 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7075 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7076 | used_at = 1; |
7077 | } | |
67c0d1eb | 7078 | macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16); |
8fc2e39e | 7079 | break; |
252b5132 RH |
7080 | |
7081 | case M_SGE: /* sreg >= treg <==> not (sreg < treg) */ | |
7082 | s = "slt"; | |
7083 | goto sge; | |
7084 | case M_SGEU: | |
7085 | s = "sltu"; | |
7086 | sge: | |
67c0d1eb RS |
7087 | macro_build (NULL, s, "d,v,t", dreg, sreg, treg); |
7088 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
8fc2e39e | 7089 | break; |
252b5132 RH |
7090 | |
7091 | case M_SGE_I: /* sreg >= I <==> not (sreg < I) */ | |
7092 | case M_SGEU_I: | |
7093 | if (imm_expr.X_op == O_constant | |
7094 | && imm_expr.X_add_number >= -0x8000 | |
7095 | && imm_expr.X_add_number < 0x8000) | |
7096 | { | |
67c0d1eb RS |
7097 | macro_build (&imm_expr, mask == M_SGE_I ? "slti" : "sltiu", "t,r,j", |
7098 | dreg, sreg, BFD_RELOC_LO16); | |
252b5132 RH |
7099 | } |
7100 | else | |
7101 | { | |
67c0d1eb RS |
7102 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7103 | macro_build (NULL, mask == M_SGE_I ? "slt" : "sltu", "d,v,t", | |
7104 | dreg, sreg, AT); | |
252b5132 RH |
7105 | used_at = 1; |
7106 | } | |
67c0d1eb | 7107 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); |
8fc2e39e | 7108 | break; |
252b5132 RH |
7109 | |
7110 | case M_SGT: /* sreg > treg <==> treg < sreg */ | |
7111 | s = "slt"; | |
7112 | goto sgt; | |
7113 | case M_SGTU: | |
7114 | s = "sltu"; | |
7115 | sgt: | |
67c0d1eb | 7116 | macro_build (NULL, s, "d,v,t", dreg, treg, sreg); |
8fc2e39e | 7117 | break; |
252b5132 RH |
7118 | |
7119 | case M_SGT_I: /* sreg > I <==> I < sreg */ | |
7120 | s = "slt"; | |
7121 | goto sgti; | |
7122 | case M_SGTU_I: | |
7123 | s = "sltu"; | |
7124 | sgti: | |
8fc2e39e | 7125 | used_at = 1; |
67c0d1eb RS |
7126 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7127 | macro_build (NULL, s, "d,v,t", dreg, AT, sreg); | |
252b5132 RH |
7128 | break; |
7129 | ||
2396cfb9 | 7130 | case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */ |
252b5132 RH |
7131 | s = "slt"; |
7132 | goto sle; | |
7133 | case M_SLEU: | |
7134 | s = "sltu"; | |
7135 | sle: | |
67c0d1eb RS |
7136 | macro_build (NULL, s, "d,v,t", dreg, treg, sreg); |
7137 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
8fc2e39e | 7138 | break; |
252b5132 | 7139 | |
2396cfb9 | 7140 | case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */ |
252b5132 RH |
7141 | s = "slt"; |
7142 | goto slei; | |
7143 | case M_SLEU_I: | |
7144 | s = "sltu"; | |
7145 | slei: | |
8fc2e39e | 7146 | used_at = 1; |
67c0d1eb RS |
7147 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7148 | macro_build (NULL, s, "d,v,t", dreg, AT, sreg); | |
7149 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
252b5132 RH |
7150 | break; |
7151 | ||
7152 | case M_SLT_I: | |
7153 | if (imm_expr.X_op == O_constant | |
7154 | && imm_expr.X_add_number >= -0x8000 | |
7155 | && imm_expr.X_add_number < 0x8000) | |
7156 | { | |
67c0d1eb | 7157 | macro_build (&imm_expr, "slti", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 7158 | break; |
252b5132 | 7159 | } |
8fc2e39e | 7160 | used_at = 1; |
67c0d1eb RS |
7161 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7162 | macro_build (NULL, "slt", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7163 | break; |
7164 | ||
7165 | case M_SLTU_I: | |
7166 | if (imm_expr.X_op == O_constant | |
7167 | && imm_expr.X_add_number >= -0x8000 | |
7168 | && imm_expr.X_add_number < 0x8000) | |
7169 | { | |
67c0d1eb | 7170 | macro_build (&imm_expr, "sltiu", "t,r,j", dreg, sreg, |
17a2f251 | 7171 | BFD_RELOC_LO16); |
8fc2e39e | 7172 | break; |
252b5132 | 7173 | } |
8fc2e39e | 7174 | used_at = 1; |
67c0d1eb RS |
7175 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7176 | macro_build (NULL, "sltu", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7177 | break; |
7178 | ||
7179 | case M_SNE: | |
7180 | if (sreg == 0) | |
67c0d1eb | 7181 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, treg); |
252b5132 | 7182 | else if (treg == 0) |
67c0d1eb | 7183 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg); |
252b5132 RH |
7184 | else |
7185 | { | |
67c0d1eb RS |
7186 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg); |
7187 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg); | |
252b5132 | 7188 | } |
8fc2e39e | 7189 | break; |
252b5132 RH |
7190 | |
7191 | case M_SNE_I: | |
7192 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
7193 | { | |
67c0d1eb | 7194 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg); |
8fc2e39e | 7195 | break; |
252b5132 RH |
7196 | } |
7197 | if (sreg == 0) | |
7198 | { | |
7199 | as_warn (_("Instruction %s: result is always true"), | |
7200 | ip->insn_mo->name); | |
67c0d1eb RS |
7201 | macro_build (&expr1, HAVE_32BIT_GPRS ? "addiu" : "daddiu", "t,r,j", |
7202 | dreg, 0, BFD_RELOC_LO16); | |
8fc2e39e | 7203 | break; |
252b5132 RH |
7204 | } |
7205 | if (imm_expr.X_op == O_constant | |
7206 | && imm_expr.X_add_number >= 0 | |
7207 | && imm_expr.X_add_number < 0x10000) | |
7208 | { | |
67c0d1eb | 7209 | macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7210 | } |
7211 | else if (imm_expr.X_op == O_constant | |
7212 | && imm_expr.X_add_number > -0x8000 | |
7213 | && imm_expr.X_add_number < 0) | |
7214 | { | |
7215 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 7216 | macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu", |
17a2f251 | 7217 | "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7218 | } |
7219 | else | |
7220 | { | |
67c0d1eb RS |
7221 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7222 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7223 | used_at = 1; |
7224 | } | |
67c0d1eb | 7225 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg); |
8fc2e39e | 7226 | break; |
252b5132 RH |
7227 | |
7228 | case M_DSUB_I: | |
7229 | dbl = 1; | |
7230 | case M_SUB_I: | |
7231 | if (imm_expr.X_op == O_constant | |
7232 | && imm_expr.X_add_number > -0x8000 | |
7233 | && imm_expr.X_add_number <= 0x8000) | |
7234 | { | |
7235 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb RS |
7236 | macro_build (&imm_expr, dbl ? "daddi" : "addi", "t,r,j", |
7237 | dreg, sreg, BFD_RELOC_LO16); | |
8fc2e39e | 7238 | break; |
252b5132 | 7239 | } |
8fc2e39e | 7240 | used_at = 1; |
67c0d1eb RS |
7241 | load_register (AT, &imm_expr, dbl); |
7242 | macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7243 | break; |
7244 | ||
7245 | case M_DSUBU_I: | |
7246 | dbl = 1; | |
7247 | case M_SUBU_I: | |
7248 | if (imm_expr.X_op == O_constant | |
7249 | && imm_expr.X_add_number > -0x8000 | |
7250 | && imm_expr.X_add_number <= 0x8000) | |
7251 | { | |
7252 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb RS |
7253 | macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "t,r,j", |
7254 | dreg, sreg, BFD_RELOC_LO16); | |
8fc2e39e | 7255 | break; |
252b5132 | 7256 | } |
8fc2e39e | 7257 | used_at = 1; |
67c0d1eb RS |
7258 | load_register (AT, &imm_expr, dbl); |
7259 | macro_build (NULL, dbl ? "dsubu" : "subu", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7260 | break; |
7261 | ||
7262 | case M_TEQ_I: | |
7263 | s = "teq"; | |
7264 | goto trap; | |
7265 | case M_TGE_I: | |
7266 | s = "tge"; | |
7267 | goto trap; | |
7268 | case M_TGEU_I: | |
7269 | s = "tgeu"; | |
7270 | goto trap; | |
7271 | case M_TLT_I: | |
7272 | s = "tlt"; | |
7273 | goto trap; | |
7274 | case M_TLTU_I: | |
7275 | s = "tltu"; | |
7276 | goto trap; | |
7277 | case M_TNE_I: | |
7278 | s = "tne"; | |
7279 | trap: | |
8fc2e39e | 7280 | used_at = 1; |
67c0d1eb RS |
7281 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7282 | macro_build (NULL, s, "s,t", sreg, AT); | |
252b5132 RH |
7283 | break; |
7284 | ||
252b5132 | 7285 | case M_TRUNCWS: |
43841e91 | 7286 | case M_TRUNCWD: |
e7af610e | 7287 | assert (mips_opts.isa == ISA_MIPS1); |
8fc2e39e | 7288 | used_at = 1; |
252b5132 RH |
7289 | sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */ |
7290 | dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */ | |
7291 | ||
7292 | /* | |
7293 | * Is the double cfc1 instruction a bug in the mips assembler; | |
7294 | * or is there a reason for it? | |
7295 | */ | |
7d10b47d | 7296 | start_noreorder (); |
67c0d1eb RS |
7297 | macro_build (NULL, "cfc1", "t,G", treg, RA); |
7298 | macro_build (NULL, "cfc1", "t,G", treg, RA); | |
7299 | macro_build (NULL, "nop", ""); | |
252b5132 | 7300 | expr1.X_add_number = 3; |
67c0d1eb | 7301 | macro_build (&expr1, "ori", "t,r,i", AT, treg, BFD_RELOC_LO16); |
252b5132 | 7302 | expr1.X_add_number = 2; |
67c0d1eb RS |
7303 | macro_build (&expr1, "xori", "t,r,i", AT, AT, BFD_RELOC_LO16); |
7304 | macro_build (NULL, "ctc1", "t,G", AT, RA); | |
7305 | macro_build (NULL, "nop", ""); | |
7306 | macro_build (NULL, mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S", | |
7307 | dreg, sreg); | |
7308 | macro_build (NULL, "ctc1", "t,G", treg, RA); | |
7309 | macro_build (NULL, "nop", ""); | |
7d10b47d | 7310 | end_noreorder (); |
252b5132 RH |
7311 | break; |
7312 | ||
7313 | case M_ULH: | |
7314 | s = "lb"; | |
7315 | goto ulh; | |
7316 | case M_ULHU: | |
7317 | s = "lbu"; | |
7318 | ulh: | |
8fc2e39e | 7319 | used_at = 1; |
252b5132 RH |
7320 | if (offset_expr.X_add_number >= 0x7fff) |
7321 | as_bad (_("operand overflow")); | |
252b5132 | 7322 | if (! target_big_endian) |
f9419b05 | 7323 | ++offset_expr.X_add_number; |
67c0d1eb | 7324 | macro_build (&offset_expr, s, "t,o(b)", AT, BFD_RELOC_LO16, breg); |
252b5132 | 7325 | if (! target_big_endian) |
f9419b05 | 7326 | --offset_expr.X_add_number; |
252b5132 | 7327 | else |
f9419b05 | 7328 | ++offset_expr.X_add_number; |
67c0d1eb RS |
7329 | macro_build (&offset_expr, "lbu", "t,o(b)", treg, BFD_RELOC_LO16, breg); |
7330 | macro_build (NULL, "sll", "d,w,<", AT, AT, 8); | |
7331 | macro_build (NULL, "or", "d,v,t", treg, treg, AT); | |
252b5132 RH |
7332 | break; |
7333 | ||
7334 | case M_ULD: | |
7335 | s = "ldl"; | |
7336 | s2 = "ldr"; | |
7337 | off = 7; | |
7338 | goto ulw; | |
7339 | case M_ULW: | |
7340 | s = "lwl"; | |
7341 | s2 = "lwr"; | |
7342 | off = 3; | |
7343 | ulw: | |
7344 | if (offset_expr.X_add_number >= 0x8000 - off) | |
7345 | as_bad (_("operand overflow")); | |
af22f5b2 CD |
7346 | if (treg != breg) |
7347 | tempreg = treg; | |
7348 | else | |
8fc2e39e TS |
7349 | { |
7350 | used_at = 1; | |
7351 | tempreg = AT; | |
7352 | } | |
252b5132 RH |
7353 | if (! target_big_endian) |
7354 | offset_expr.X_add_number += off; | |
67c0d1eb | 7355 | macro_build (&offset_expr, s, "t,o(b)", tempreg, BFD_RELOC_LO16, breg); |
252b5132 RH |
7356 | if (! target_big_endian) |
7357 | offset_expr.X_add_number -= off; | |
7358 | else | |
7359 | offset_expr.X_add_number += off; | |
67c0d1eb | 7360 | macro_build (&offset_expr, s2, "t,o(b)", tempreg, BFD_RELOC_LO16, breg); |
af22f5b2 CD |
7361 | |
7362 | /* If necessary, move the result in tempreg the final destination. */ | |
7363 | if (treg == tempreg) | |
8fc2e39e | 7364 | break; |
af22f5b2 | 7365 | /* Protect second load's delay slot. */ |
017315e4 | 7366 | load_delay_nop (); |
67c0d1eb | 7367 | move_register (treg, tempreg); |
af22f5b2 | 7368 | break; |
252b5132 RH |
7369 | |
7370 | case M_ULD_A: | |
7371 | s = "ldl"; | |
7372 | s2 = "ldr"; | |
7373 | off = 7; | |
7374 | goto ulwa; | |
7375 | case M_ULW_A: | |
7376 | s = "lwl"; | |
7377 | s2 = "lwr"; | |
7378 | off = 3; | |
7379 | ulwa: | |
d6bc6245 | 7380 | used_at = 1; |
67c0d1eb | 7381 | load_address (AT, &offset_expr, &used_at); |
252b5132 | 7382 | if (breg != 0) |
67c0d1eb | 7383 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); |
252b5132 RH |
7384 | if (! target_big_endian) |
7385 | expr1.X_add_number = off; | |
7386 | else | |
7387 | expr1.X_add_number = 0; | |
67c0d1eb | 7388 | macro_build (&expr1, s, "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
7389 | if (! target_big_endian) |
7390 | expr1.X_add_number = 0; | |
7391 | else | |
7392 | expr1.X_add_number = off; | |
67c0d1eb | 7393 | macro_build (&expr1, s2, "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
7394 | break; |
7395 | ||
7396 | case M_ULH_A: | |
7397 | case M_ULHU_A: | |
d6bc6245 | 7398 | used_at = 1; |
67c0d1eb | 7399 | load_address (AT, &offset_expr, &used_at); |
252b5132 | 7400 | if (breg != 0) |
67c0d1eb | 7401 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); |
252b5132 RH |
7402 | if (target_big_endian) |
7403 | expr1.X_add_number = 0; | |
67c0d1eb | 7404 | macro_build (&expr1, mask == M_ULH_A ? "lb" : "lbu", "t,o(b)", |
17a2f251 | 7405 | treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
7406 | if (target_big_endian) |
7407 | expr1.X_add_number = 1; | |
7408 | else | |
7409 | expr1.X_add_number = 0; | |
67c0d1eb RS |
7410 | macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT); |
7411 | macro_build (NULL, "sll", "d,w,<", treg, treg, 8); | |
7412 | macro_build (NULL, "or", "d,v,t", treg, treg, AT); | |
252b5132 RH |
7413 | break; |
7414 | ||
7415 | case M_USH: | |
8fc2e39e | 7416 | used_at = 1; |
252b5132 RH |
7417 | if (offset_expr.X_add_number >= 0x7fff) |
7418 | as_bad (_("operand overflow")); | |
7419 | if (target_big_endian) | |
f9419b05 | 7420 | ++offset_expr.X_add_number; |
67c0d1eb RS |
7421 | macro_build (&offset_expr, "sb", "t,o(b)", treg, BFD_RELOC_LO16, breg); |
7422 | macro_build (NULL, "srl", "d,w,<", AT, treg, 8); | |
252b5132 | 7423 | if (target_big_endian) |
f9419b05 | 7424 | --offset_expr.X_add_number; |
252b5132 | 7425 | else |
f9419b05 | 7426 | ++offset_expr.X_add_number; |
67c0d1eb | 7427 | macro_build (&offset_expr, "sb", "t,o(b)", AT, BFD_RELOC_LO16, breg); |
252b5132 RH |
7428 | break; |
7429 | ||
7430 | case M_USD: | |
7431 | s = "sdl"; | |
7432 | s2 = "sdr"; | |
7433 | off = 7; | |
7434 | goto usw; | |
7435 | case M_USW: | |
7436 | s = "swl"; | |
7437 | s2 = "swr"; | |
7438 | off = 3; | |
7439 | usw: | |
7440 | if (offset_expr.X_add_number >= 0x8000 - off) | |
7441 | as_bad (_("operand overflow")); | |
7442 | if (! target_big_endian) | |
7443 | offset_expr.X_add_number += off; | |
67c0d1eb | 7444 | macro_build (&offset_expr, s, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
252b5132 RH |
7445 | if (! target_big_endian) |
7446 | offset_expr.X_add_number -= off; | |
7447 | else | |
7448 | offset_expr.X_add_number += off; | |
67c0d1eb | 7449 | macro_build (&offset_expr, s2, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
8fc2e39e | 7450 | break; |
252b5132 RH |
7451 | |
7452 | case M_USD_A: | |
7453 | s = "sdl"; | |
7454 | s2 = "sdr"; | |
7455 | off = 7; | |
7456 | goto uswa; | |
7457 | case M_USW_A: | |
7458 | s = "swl"; | |
7459 | s2 = "swr"; | |
7460 | off = 3; | |
7461 | uswa: | |
d6bc6245 | 7462 | used_at = 1; |
67c0d1eb | 7463 | load_address (AT, &offset_expr, &used_at); |
252b5132 | 7464 | if (breg != 0) |
67c0d1eb | 7465 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); |
252b5132 RH |
7466 | if (! target_big_endian) |
7467 | expr1.X_add_number = off; | |
7468 | else | |
7469 | expr1.X_add_number = 0; | |
67c0d1eb | 7470 | macro_build (&expr1, s, "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
7471 | if (! target_big_endian) |
7472 | expr1.X_add_number = 0; | |
7473 | else | |
7474 | expr1.X_add_number = off; | |
67c0d1eb | 7475 | macro_build (&expr1, s2, "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
7476 | break; |
7477 | ||
7478 | case M_USH_A: | |
d6bc6245 | 7479 | used_at = 1; |
67c0d1eb | 7480 | load_address (AT, &offset_expr, &used_at); |
252b5132 | 7481 | if (breg != 0) |
67c0d1eb | 7482 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); |
252b5132 RH |
7483 | if (! target_big_endian) |
7484 | expr1.X_add_number = 0; | |
67c0d1eb RS |
7485 | macro_build (&expr1, "sb", "t,o(b)", treg, BFD_RELOC_LO16, AT); |
7486 | macro_build (NULL, "srl", "d,w,<", treg, treg, 8); | |
252b5132 RH |
7487 | if (! target_big_endian) |
7488 | expr1.X_add_number = 1; | |
7489 | else | |
7490 | expr1.X_add_number = 0; | |
67c0d1eb | 7491 | macro_build (&expr1, "sb", "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
7492 | if (! target_big_endian) |
7493 | expr1.X_add_number = 0; | |
7494 | else | |
7495 | expr1.X_add_number = 1; | |
67c0d1eb RS |
7496 | macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT); |
7497 | macro_build (NULL, "sll", "d,w,<", treg, treg, 8); | |
7498 | macro_build (NULL, "or", "d,v,t", treg, treg, AT); | |
252b5132 RH |
7499 | break; |
7500 | ||
7501 | default: | |
7502 | /* FIXME: Check if this is one of the itbl macros, since they | |
bdaaa2e1 | 7503 | are added dynamically. */ |
252b5132 RH |
7504 | as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name); |
7505 | break; | |
7506 | } | |
8fc2e39e TS |
7507 | if (mips_opts.noat && used_at) |
7508 | as_bad (_("Macro used $at after \".set noat\"")); | |
252b5132 RH |
7509 | } |
7510 | ||
7511 | /* Implement macros in mips16 mode. */ | |
7512 | ||
7513 | static void | |
17a2f251 | 7514 | mips16_macro (struct mips_cl_insn *ip) |
252b5132 RH |
7515 | { |
7516 | int mask; | |
7517 | int xreg, yreg, zreg, tmp; | |
252b5132 RH |
7518 | expressionS expr1; |
7519 | int dbl; | |
7520 | const char *s, *s2, *s3; | |
7521 | ||
7522 | mask = ip->insn_mo->mask; | |
7523 | ||
bf12938e RS |
7524 | xreg = MIPS16_EXTRACT_OPERAND (RX, *ip); |
7525 | yreg = MIPS16_EXTRACT_OPERAND (RY, *ip); | |
7526 | zreg = MIPS16_EXTRACT_OPERAND (RZ, *ip); | |
252b5132 | 7527 | |
252b5132 RH |
7528 | expr1.X_op = O_constant; |
7529 | expr1.X_op_symbol = NULL; | |
7530 | expr1.X_add_symbol = NULL; | |
7531 | expr1.X_add_number = 1; | |
7532 | ||
7533 | dbl = 0; | |
7534 | ||
7535 | switch (mask) | |
7536 | { | |
7537 | default: | |
7538 | internalError (); | |
7539 | ||
7540 | case M_DDIV_3: | |
7541 | dbl = 1; | |
7542 | case M_DIV_3: | |
7543 | s = "mflo"; | |
7544 | goto do_div3; | |
7545 | case M_DREM_3: | |
7546 | dbl = 1; | |
7547 | case M_REM_3: | |
7548 | s = "mfhi"; | |
7549 | do_div3: | |
7d10b47d | 7550 | start_noreorder (); |
67c0d1eb | 7551 | macro_build (NULL, dbl ? "ddiv" : "div", "0,x,y", xreg, yreg); |
252b5132 | 7552 | expr1.X_add_number = 2; |
67c0d1eb RS |
7553 | macro_build (&expr1, "bnez", "x,p", yreg); |
7554 | macro_build (NULL, "break", "6", 7); | |
bdaaa2e1 | 7555 | |
252b5132 RH |
7556 | /* FIXME: The normal code checks for of -1 / -0x80000000 here, |
7557 | since that causes an overflow. We should do that as well, | |
7558 | but I don't see how to do the comparisons without a temporary | |
7559 | register. */ | |
7d10b47d | 7560 | end_noreorder (); |
67c0d1eb | 7561 | macro_build (NULL, s, "x", zreg); |
252b5132 RH |
7562 | break; |
7563 | ||
7564 | case M_DIVU_3: | |
7565 | s = "divu"; | |
7566 | s2 = "mflo"; | |
7567 | goto do_divu3; | |
7568 | case M_REMU_3: | |
7569 | s = "divu"; | |
7570 | s2 = "mfhi"; | |
7571 | goto do_divu3; | |
7572 | case M_DDIVU_3: | |
7573 | s = "ddivu"; | |
7574 | s2 = "mflo"; | |
7575 | goto do_divu3; | |
7576 | case M_DREMU_3: | |
7577 | s = "ddivu"; | |
7578 | s2 = "mfhi"; | |
7579 | do_divu3: | |
7d10b47d | 7580 | start_noreorder (); |
67c0d1eb | 7581 | macro_build (NULL, s, "0,x,y", xreg, yreg); |
252b5132 | 7582 | expr1.X_add_number = 2; |
67c0d1eb RS |
7583 | macro_build (&expr1, "bnez", "x,p", yreg); |
7584 | macro_build (NULL, "break", "6", 7); | |
7d10b47d | 7585 | end_noreorder (); |
67c0d1eb | 7586 | macro_build (NULL, s2, "x", zreg); |
252b5132 RH |
7587 | break; |
7588 | ||
7589 | case M_DMUL: | |
7590 | dbl = 1; | |
7591 | case M_MUL: | |
67c0d1eb RS |
7592 | macro_build (NULL, dbl ? "dmultu" : "multu", "x,y", xreg, yreg); |
7593 | macro_build (NULL, "mflo", "x", zreg); | |
8fc2e39e | 7594 | break; |
252b5132 RH |
7595 | |
7596 | case M_DSUBU_I: | |
7597 | dbl = 1; | |
7598 | goto do_subu; | |
7599 | case M_SUBU_I: | |
7600 | do_subu: | |
7601 | if (imm_expr.X_op != O_constant) | |
7602 | as_bad (_("Unsupported large constant")); | |
7603 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 7604 | macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "y,x,4", yreg, xreg); |
252b5132 RH |
7605 | break; |
7606 | ||
7607 | case M_SUBU_I_2: | |
7608 | if (imm_expr.X_op != O_constant) | |
7609 | as_bad (_("Unsupported large constant")); | |
7610 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 7611 | macro_build (&imm_expr, "addiu", "x,k", xreg); |
252b5132 RH |
7612 | break; |
7613 | ||
7614 | case M_DSUBU_I_2: | |
7615 | if (imm_expr.X_op != O_constant) | |
7616 | as_bad (_("Unsupported large constant")); | |
7617 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 7618 | macro_build (&imm_expr, "daddiu", "y,j", yreg); |
252b5132 RH |
7619 | break; |
7620 | ||
7621 | case M_BEQ: | |
7622 | s = "cmp"; | |
7623 | s2 = "bteqz"; | |
7624 | goto do_branch; | |
7625 | case M_BNE: | |
7626 | s = "cmp"; | |
7627 | s2 = "btnez"; | |
7628 | goto do_branch; | |
7629 | case M_BLT: | |
7630 | s = "slt"; | |
7631 | s2 = "btnez"; | |
7632 | goto do_branch; | |
7633 | case M_BLTU: | |
7634 | s = "sltu"; | |
7635 | s2 = "btnez"; | |
7636 | goto do_branch; | |
7637 | case M_BLE: | |
7638 | s = "slt"; | |
7639 | s2 = "bteqz"; | |
7640 | goto do_reverse_branch; | |
7641 | case M_BLEU: | |
7642 | s = "sltu"; | |
7643 | s2 = "bteqz"; | |
7644 | goto do_reverse_branch; | |
7645 | case M_BGE: | |
7646 | s = "slt"; | |
7647 | s2 = "bteqz"; | |
7648 | goto do_branch; | |
7649 | case M_BGEU: | |
7650 | s = "sltu"; | |
7651 | s2 = "bteqz"; | |
7652 | goto do_branch; | |
7653 | case M_BGT: | |
7654 | s = "slt"; | |
7655 | s2 = "btnez"; | |
7656 | goto do_reverse_branch; | |
7657 | case M_BGTU: | |
7658 | s = "sltu"; | |
7659 | s2 = "btnez"; | |
7660 | ||
7661 | do_reverse_branch: | |
7662 | tmp = xreg; | |
7663 | xreg = yreg; | |
7664 | yreg = tmp; | |
7665 | ||
7666 | do_branch: | |
67c0d1eb RS |
7667 | macro_build (NULL, s, "x,y", xreg, yreg); |
7668 | macro_build (&offset_expr, s2, "p"); | |
252b5132 RH |
7669 | break; |
7670 | ||
7671 | case M_BEQ_I: | |
7672 | s = "cmpi"; | |
7673 | s2 = "bteqz"; | |
7674 | s3 = "x,U"; | |
7675 | goto do_branch_i; | |
7676 | case M_BNE_I: | |
7677 | s = "cmpi"; | |
7678 | s2 = "btnez"; | |
7679 | s3 = "x,U"; | |
7680 | goto do_branch_i; | |
7681 | case M_BLT_I: | |
7682 | s = "slti"; | |
7683 | s2 = "btnez"; | |
7684 | s3 = "x,8"; | |
7685 | goto do_branch_i; | |
7686 | case M_BLTU_I: | |
7687 | s = "sltiu"; | |
7688 | s2 = "btnez"; | |
7689 | s3 = "x,8"; | |
7690 | goto do_branch_i; | |
7691 | case M_BLE_I: | |
7692 | s = "slti"; | |
7693 | s2 = "btnez"; | |
7694 | s3 = "x,8"; | |
7695 | goto do_addone_branch_i; | |
7696 | case M_BLEU_I: | |
7697 | s = "sltiu"; | |
7698 | s2 = "btnez"; | |
7699 | s3 = "x,8"; | |
7700 | goto do_addone_branch_i; | |
7701 | case M_BGE_I: | |
7702 | s = "slti"; | |
7703 | s2 = "bteqz"; | |
7704 | s3 = "x,8"; | |
7705 | goto do_branch_i; | |
7706 | case M_BGEU_I: | |
7707 | s = "sltiu"; | |
7708 | s2 = "bteqz"; | |
7709 | s3 = "x,8"; | |
7710 | goto do_branch_i; | |
7711 | case M_BGT_I: | |
7712 | s = "slti"; | |
7713 | s2 = "bteqz"; | |
7714 | s3 = "x,8"; | |
7715 | goto do_addone_branch_i; | |
7716 | case M_BGTU_I: | |
7717 | s = "sltiu"; | |
7718 | s2 = "bteqz"; | |
7719 | s3 = "x,8"; | |
7720 | ||
7721 | do_addone_branch_i: | |
7722 | if (imm_expr.X_op != O_constant) | |
7723 | as_bad (_("Unsupported large constant")); | |
7724 | ++imm_expr.X_add_number; | |
7725 | ||
7726 | do_branch_i: | |
67c0d1eb RS |
7727 | macro_build (&imm_expr, s, s3, xreg); |
7728 | macro_build (&offset_expr, s2, "p"); | |
252b5132 RH |
7729 | break; |
7730 | ||
7731 | case M_ABS: | |
7732 | expr1.X_add_number = 0; | |
67c0d1eb | 7733 | macro_build (&expr1, "slti", "x,8", yreg); |
252b5132 | 7734 | if (xreg != yreg) |
67c0d1eb | 7735 | move_register (xreg, yreg); |
252b5132 | 7736 | expr1.X_add_number = 2; |
67c0d1eb RS |
7737 | macro_build (&expr1, "bteqz", "p"); |
7738 | macro_build (NULL, "neg", "x,w", xreg, xreg); | |
252b5132 RH |
7739 | } |
7740 | } | |
7741 | ||
7742 | /* For consistency checking, verify that all bits are specified either | |
7743 | by the match/mask part of the instruction definition, or by the | |
7744 | operand list. */ | |
7745 | static int | |
17a2f251 | 7746 | validate_mips_insn (const struct mips_opcode *opc) |
252b5132 RH |
7747 | { |
7748 | const char *p = opc->args; | |
7749 | char c; | |
7750 | unsigned long used_bits = opc->mask; | |
7751 | ||
7752 | if ((used_bits & opc->match) != opc->match) | |
7753 | { | |
7754 | as_bad (_("internal: bad mips opcode (mask error): %s %s"), | |
7755 | opc->name, opc->args); | |
7756 | return 0; | |
7757 | } | |
7758 | #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift))) | |
7759 | while (*p) | |
7760 | switch (c = *p++) | |
7761 | { | |
7762 | case ',': break; | |
7763 | case '(': break; | |
7764 | case ')': break; | |
af7ee8bf CD |
7765 | case '+': |
7766 | switch (c = *p++) | |
7767 | { | |
7768 | case 'A': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; | |
7769 | case 'B': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break; | |
7770 | case 'C': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
bbcc0807 CD |
7771 | case 'D': USE_BITS (OP_MASK_RD, OP_SH_RD); |
7772 | USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; | |
5f74bc13 CD |
7773 | case 'E': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
7774 | case 'F': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break; | |
7775 | case 'G': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
7776 | case 'H': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
7777 | case 'I': break; | |
ef2e4d86 CF |
7778 | case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break; |
7779 | case 'T': USE_BITS (OP_MASK_RT, OP_SH_RT); | |
7780 | USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; | |
af7ee8bf CD |
7781 | default: |
7782 | as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"), | |
7783 | c, opc->name, opc->args); | |
7784 | return 0; | |
7785 | } | |
7786 | break; | |
252b5132 RH |
7787 | case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
7788 | case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; | |
7789 | case 'A': break; | |
4372b673 | 7790 | case 'B': USE_BITS (OP_MASK_CODE20, OP_SH_CODE20); break; |
252b5132 RH |
7791 | case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break; |
7792 | case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break; | |
7793 | case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
7794 | case 'F': break; | |
7795 | case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
156c2f8b | 7796 | case 'H': USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; |
252b5132 | 7797 | case 'I': break; |
e972090a | 7798 | case 'J': USE_BITS (OP_MASK_CODE19, OP_SH_CODE19); break; |
af7ee8bf | 7799 | case 'K': USE_BITS (OP_MASK_RD, OP_SH_RD); break; |
252b5132 RH |
7800 | case 'L': break; |
7801 | case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break; | |
7802 | case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break; | |
deec1734 CD |
7803 | case 'O': USE_BITS (OP_MASK_ALN, OP_SH_ALN); break; |
7804 | case 'Q': USE_BITS (OP_MASK_VSEL, OP_SH_VSEL); | |
7805 | USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
252b5132 RH |
7806 | case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break; |
7807 | case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
7808 | case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
7809 | case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
7810 | case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
deec1734 CD |
7811 | case 'X': USE_BITS (OP_MASK_FD, OP_SH_FD); break; |
7812 | case 'Y': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
7813 | case 'Z': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
252b5132 RH |
7814 | case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break; |
7815 | case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
7816 | case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break; | |
7817 | case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
7818 | case 'f': break; | |
7819 | case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break; | |
7820 | case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; | |
7821 | case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
7822 | case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break; | |
7823 | case 'l': break; | |
7824 | case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
7825 | case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
7826 | case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break; | |
7827 | case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
7828 | case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
7829 | case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
7830 | case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; | |
7831 | case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
7832 | case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
7833 | case 'x': break; | |
7834 | case 'z': break; | |
7835 | case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break; | |
4372b673 NC |
7836 | case 'U': USE_BITS (OP_MASK_RD, OP_SH_RD); |
7837 | USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
60b63b72 RS |
7838 | case 'e': USE_BITS (OP_MASK_VECBYTE, OP_SH_VECBYTE); break; |
7839 | case '%': USE_BITS (OP_MASK_VECALIGN, OP_SH_VECALIGN); break; | |
7840 | case '[': break; | |
7841 | case ']': break; | |
74cd071d CF |
7842 | case '3': USE_BITS (OP_MASK_SA3, OP_SH_SA3); break; |
7843 | case '4': USE_BITS (OP_MASK_SA4, OP_SH_SA4); break; | |
7844 | case '5': USE_BITS (OP_MASK_IMM8, OP_SH_IMM8); break; | |
7845 | case '6': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
7846 | case '7': USE_BITS (OP_MASK_DSPACC, OP_SH_DSPACC); break; | |
7847 | case '8': USE_BITS (OP_MASK_WRDSP, OP_SH_WRDSP); break; | |
7848 | case '9': USE_BITS (OP_MASK_DSPACC_S, OP_SH_DSPACC_S);break; | |
7849 | case '0': USE_BITS (OP_MASK_DSPSFT, OP_SH_DSPSFT); break; | |
7850 | case '\'': USE_BITS (OP_MASK_RDDSP, OP_SH_RDDSP); break; | |
7851 | case ':': USE_BITS (OP_MASK_DSPSFT_7, OP_SH_DSPSFT_7);break; | |
7852 | case '@': USE_BITS (OP_MASK_IMM10, OP_SH_IMM10); break; | |
ef2e4d86 CF |
7853 | case '!': USE_BITS (OP_MASK_MT_U, OP_SH_MT_U); break; |
7854 | case '$': USE_BITS (OP_MASK_MT_H, OP_SH_MT_H); break; | |
7855 | case '*': USE_BITS (OP_MASK_MTACC_T, OP_SH_MTACC_T); break; | |
7856 | case '&': USE_BITS (OP_MASK_MTACC_D, OP_SH_MTACC_D); break; | |
7857 | case 'g': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
252b5132 RH |
7858 | default: |
7859 | as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"), | |
7860 | c, opc->name, opc->args); | |
7861 | return 0; | |
7862 | } | |
7863 | #undef USE_BITS | |
7864 | if (used_bits != 0xffffffff) | |
7865 | { | |
7866 | as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"), | |
7867 | ~used_bits & 0xffffffff, opc->name, opc->args); | |
7868 | return 0; | |
7869 | } | |
7870 | return 1; | |
7871 | } | |
7872 | ||
7873 | /* This routine assembles an instruction into its binary format. As a | |
7874 | side effect, it sets one of the global variables imm_reloc or | |
7875 | offset_reloc to the type of relocation to do if one of the operands | |
7876 | is an address expression. */ | |
7877 | ||
7878 | static void | |
17a2f251 | 7879 | mips_ip (char *str, struct mips_cl_insn *ip) |
252b5132 RH |
7880 | { |
7881 | char *s; | |
7882 | const char *args; | |
43841e91 | 7883 | char c = 0; |
252b5132 RH |
7884 | struct mips_opcode *insn; |
7885 | char *argsStart; | |
7886 | unsigned int regno; | |
7887 | unsigned int lastregno = 0; | |
af7ee8bf | 7888 | unsigned int lastpos = 0; |
071742cf | 7889 | unsigned int limlo, limhi; |
252b5132 RH |
7890 | char *s_reset; |
7891 | char save_c = 0; | |
74cd071d | 7892 | offsetT min_range, max_range; |
252b5132 RH |
7893 | |
7894 | insn_error = NULL; | |
7895 | ||
7896 | /* If the instruction contains a '.', we first try to match an instruction | |
7897 | including the '.'. Then we try again without the '.'. */ | |
7898 | insn = NULL; | |
3882b010 | 7899 | for (s = str; *s != '\0' && !ISSPACE (*s); ++s) |
252b5132 RH |
7900 | continue; |
7901 | ||
7902 | /* If we stopped on whitespace, then replace the whitespace with null for | |
7903 | the call to hash_find. Save the character we replaced just in case we | |
7904 | have to re-parse the instruction. */ | |
3882b010 | 7905 | if (ISSPACE (*s)) |
252b5132 RH |
7906 | { |
7907 | save_c = *s; | |
7908 | *s++ = '\0'; | |
7909 | } | |
bdaaa2e1 | 7910 | |
252b5132 RH |
7911 | insn = (struct mips_opcode *) hash_find (op_hash, str); |
7912 | ||
7913 | /* If we didn't find the instruction in the opcode table, try again, but | |
7914 | this time with just the instruction up to, but not including the | |
7915 | first '.'. */ | |
7916 | if (insn == NULL) | |
7917 | { | |
bdaaa2e1 | 7918 | /* Restore the character we overwrite above (if any). */ |
252b5132 RH |
7919 | if (save_c) |
7920 | *(--s) = save_c; | |
7921 | ||
7922 | /* Scan up to the first '.' or whitespace. */ | |
3882b010 L |
7923 | for (s = str; |
7924 | *s != '\0' && *s != '.' && !ISSPACE (*s); | |
7925 | ++s) | |
252b5132 RH |
7926 | continue; |
7927 | ||
7928 | /* If we did not find a '.', then we can quit now. */ | |
7929 | if (*s != '.') | |
7930 | { | |
7931 | insn_error = "unrecognized opcode"; | |
7932 | return; | |
7933 | } | |
7934 | ||
7935 | /* Lookup the instruction in the hash table. */ | |
7936 | *s++ = '\0'; | |
7937 | if ((insn = (struct mips_opcode *) hash_find (op_hash, str)) == NULL) | |
7938 | { | |
7939 | insn_error = "unrecognized opcode"; | |
7940 | return; | |
7941 | } | |
252b5132 RH |
7942 | } |
7943 | ||
7944 | argsStart = s; | |
7945 | for (;;) | |
7946 | { | |
b34976b6 | 7947 | bfd_boolean ok; |
252b5132 RH |
7948 | |
7949 | assert (strcmp (insn->name, str) == 0); | |
7950 | ||
1f25f5d3 CD |
7951 | if (OPCODE_IS_MEMBER (insn, |
7952 | (mips_opts.isa | |
3396de36 | 7953 | | (file_ase_mips16 ? INSN_MIPS16 : 0) |
deec1734 | 7954 | | (mips_opts.ase_mdmx ? INSN_MDMX : 0) |
74cd071d | 7955 | | (mips_opts.ase_dsp ? INSN_DSP : 0) |
ef2e4d86 | 7956 | | (mips_opts.ase_mt ? INSN_MT : 0) |
98d3f06f | 7957 | | (mips_opts.ase_mips3d ? INSN_MIPS3D : 0)), |
fef14a42 | 7958 | mips_opts.arch)) |
b34976b6 | 7959 | ok = TRUE; |
bdaaa2e1 | 7960 | else |
b34976b6 | 7961 | ok = FALSE; |
bdaaa2e1 | 7962 | |
252b5132 RH |
7963 | if (insn->pinfo != INSN_MACRO) |
7964 | { | |
fef14a42 | 7965 | if (mips_opts.arch == CPU_R4650 && (insn->pinfo & FP_D) != 0) |
b34976b6 | 7966 | ok = FALSE; |
252b5132 RH |
7967 | } |
7968 | ||
7969 | if (! ok) | |
7970 | { | |
7971 | if (insn + 1 < &mips_opcodes[NUMOPCODES] | |
7972 | && strcmp (insn->name, insn[1].name) == 0) | |
7973 | { | |
7974 | ++insn; | |
7975 | continue; | |
7976 | } | |
252b5132 | 7977 | else |
beae10d5 | 7978 | { |
268f6bed L |
7979 | if (!insn_error) |
7980 | { | |
7981 | static char buf[100]; | |
fef14a42 TS |
7982 | sprintf (buf, |
7983 | _("opcode not supported on this processor: %s (%s)"), | |
7984 | mips_cpu_info_from_arch (mips_opts.arch)->name, | |
7985 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
268f6bed L |
7986 | insn_error = buf; |
7987 | } | |
7988 | if (save_c) | |
7989 | *(--s) = save_c; | |
2bd7f1f3 | 7990 | return; |
252b5132 | 7991 | } |
252b5132 RH |
7992 | } |
7993 | ||
1e915849 | 7994 | create_insn (ip, insn); |
268f6bed | 7995 | insn_error = NULL; |
252b5132 RH |
7996 | for (args = insn->args;; ++args) |
7997 | { | |
deec1734 CD |
7998 | int is_mdmx; |
7999 | ||
ad8d3bb3 | 8000 | s += strspn (s, " \t"); |
deec1734 | 8001 | is_mdmx = 0; |
252b5132 RH |
8002 | switch (*args) |
8003 | { | |
8004 | case '\0': /* end of args */ | |
8005 | if (*s == '\0') | |
8006 | return; | |
8007 | break; | |
8008 | ||
74cd071d CF |
8009 | case '3': /* dsp 3-bit unsigned immediate in bit 21 */ |
8010 | my_getExpression (&imm_expr, s); | |
8011 | check_absolute_expr (ip, &imm_expr); | |
8012 | if (imm_expr.X_add_number & ~OP_MASK_SA3) | |
8013 | { | |
8014 | as_warn (_("DSP immediate not in range 0..%d (%lu)"), | |
8015 | OP_MASK_SA3, (unsigned long) imm_expr.X_add_number); | |
8016 | imm_expr.X_add_number &= OP_MASK_SA3; | |
8017 | } | |
8018 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_SA3; | |
8019 | imm_expr.X_op = O_absent; | |
8020 | s = expr_end; | |
8021 | continue; | |
8022 | ||
8023 | case '4': /* dsp 4-bit unsigned immediate in bit 21 */ | |
8024 | my_getExpression (&imm_expr, s); | |
8025 | check_absolute_expr (ip, &imm_expr); | |
8026 | if (imm_expr.X_add_number & ~OP_MASK_SA4) | |
8027 | { | |
8028 | as_warn (_("DSP immediate not in range 0..%d (%lu)"), | |
8029 | OP_MASK_SA4, (unsigned long) imm_expr.X_add_number); | |
8030 | imm_expr.X_add_number &= OP_MASK_SA4; | |
8031 | } | |
8032 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_SA4; | |
8033 | imm_expr.X_op = O_absent; | |
8034 | s = expr_end; | |
8035 | continue; | |
8036 | ||
8037 | case '5': /* dsp 8-bit unsigned immediate in bit 16 */ | |
8038 | my_getExpression (&imm_expr, s); | |
8039 | check_absolute_expr (ip, &imm_expr); | |
8040 | if (imm_expr.X_add_number & ~OP_MASK_IMM8) | |
8041 | { | |
8042 | as_warn (_("DSP immediate not in range 0..%d (%lu)"), | |
8043 | OP_MASK_IMM8, (unsigned long) imm_expr.X_add_number); | |
8044 | imm_expr.X_add_number &= OP_MASK_IMM8; | |
8045 | } | |
8046 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_IMM8; | |
8047 | imm_expr.X_op = O_absent; | |
8048 | s = expr_end; | |
8049 | continue; | |
8050 | ||
8051 | case '6': /* dsp 5-bit unsigned immediate in bit 21 */ | |
8052 | my_getExpression (&imm_expr, s); | |
8053 | check_absolute_expr (ip, &imm_expr); | |
8054 | if (imm_expr.X_add_number & ~OP_MASK_RS) | |
8055 | { | |
8056 | as_warn (_("DSP immediate not in range 0..%d (%lu)"), | |
8057 | OP_MASK_RS, (unsigned long) imm_expr.X_add_number); | |
8058 | imm_expr.X_add_number &= OP_MASK_RS; | |
8059 | } | |
8060 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_RS; | |
8061 | imm_expr.X_op = O_absent; | |
8062 | s = expr_end; | |
8063 | continue; | |
8064 | ||
8065 | case '7': /* four dsp accumulators in bits 11,12 */ | |
8066 | if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' && | |
8067 | s[3] >= '0' && s[3] <= '3') | |
8068 | { | |
8069 | regno = s[3] - '0'; | |
8070 | s += 4; | |
8071 | ip->insn_opcode |= regno << OP_SH_DSPACC; | |
8072 | continue; | |
8073 | } | |
8074 | else | |
8075 | as_bad (_("Invalid dsp acc register")); | |
8076 | break; | |
8077 | ||
8078 | case '8': /* dsp 6-bit unsigned immediate in bit 11 */ | |
8079 | my_getExpression (&imm_expr, s); | |
8080 | check_absolute_expr (ip, &imm_expr); | |
8081 | if (imm_expr.X_add_number & ~OP_MASK_WRDSP) | |
8082 | { | |
8083 | as_warn (_("DSP immediate not in range 0..%d (%lu)"), | |
8084 | OP_MASK_WRDSP, | |
8085 | (unsigned long) imm_expr.X_add_number); | |
8086 | imm_expr.X_add_number &= OP_MASK_WRDSP; | |
8087 | } | |
8088 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_WRDSP; | |
8089 | imm_expr.X_op = O_absent; | |
8090 | s = expr_end; | |
8091 | continue; | |
8092 | ||
8093 | case '9': /* four dsp accumulators in bits 21,22 */ | |
8094 | if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' && | |
8095 | s[3] >= '0' && s[3] <= '3') | |
8096 | { | |
8097 | regno = s[3] - '0'; | |
8098 | s += 4; | |
8099 | ip->insn_opcode |= regno << OP_SH_DSPACC_S; | |
8100 | continue; | |
8101 | } | |
8102 | else | |
8103 | as_bad (_("Invalid dsp acc register")); | |
8104 | break; | |
8105 | ||
8106 | case '0': /* dsp 6-bit signed immediate in bit 20 */ | |
8107 | my_getExpression (&imm_expr, s); | |
8108 | check_absolute_expr (ip, &imm_expr); | |
8109 | min_range = -((OP_MASK_DSPSFT + 1) >> 1); | |
8110 | max_range = ((OP_MASK_DSPSFT + 1) >> 1) - 1; | |
8111 | if (imm_expr.X_add_number < min_range || | |
8112 | imm_expr.X_add_number > max_range) | |
8113 | { | |
8114 | as_warn (_("DSP immediate not in range %ld..%ld (%ld)"), | |
8115 | (long) min_range, (long) max_range, | |
8116 | (long) imm_expr.X_add_number); | |
8117 | } | |
8118 | imm_expr.X_add_number &= OP_MASK_DSPSFT; | |
8119 | ip->insn_opcode |= ((unsigned long) imm_expr.X_add_number | |
8120 | << OP_SH_DSPSFT); | |
8121 | imm_expr.X_op = O_absent; | |
8122 | s = expr_end; | |
8123 | continue; | |
8124 | ||
8125 | case '\'': /* dsp 6-bit unsigned immediate in bit 16 */ | |
8126 | my_getExpression (&imm_expr, s); | |
8127 | check_absolute_expr (ip, &imm_expr); | |
8128 | if (imm_expr.X_add_number & ~OP_MASK_RDDSP) | |
8129 | { | |
8130 | as_warn (_("DSP immediate not in range 0..%d (%lu)"), | |
8131 | OP_MASK_RDDSP, | |
8132 | (unsigned long) imm_expr.X_add_number); | |
8133 | imm_expr.X_add_number &= OP_MASK_RDDSP; | |
8134 | } | |
8135 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_RDDSP; | |
8136 | imm_expr.X_op = O_absent; | |
8137 | s = expr_end; | |
8138 | continue; | |
8139 | ||
8140 | case ':': /* dsp 7-bit signed immediate in bit 19 */ | |
8141 | my_getExpression (&imm_expr, s); | |
8142 | check_absolute_expr (ip, &imm_expr); | |
8143 | min_range = -((OP_MASK_DSPSFT_7 + 1) >> 1); | |
8144 | max_range = ((OP_MASK_DSPSFT_7 + 1) >> 1) - 1; | |
8145 | if (imm_expr.X_add_number < min_range || | |
8146 | imm_expr.X_add_number > max_range) | |
8147 | { | |
8148 | as_warn (_("DSP immediate not in range %ld..%ld (%ld)"), | |
8149 | (long) min_range, (long) max_range, | |
8150 | (long) imm_expr.X_add_number); | |
8151 | } | |
8152 | imm_expr.X_add_number &= OP_MASK_DSPSFT_7; | |
8153 | ip->insn_opcode |= ((unsigned long) imm_expr.X_add_number | |
8154 | << OP_SH_DSPSFT_7); | |
8155 | imm_expr.X_op = O_absent; | |
8156 | s = expr_end; | |
8157 | continue; | |
8158 | ||
8159 | case '@': /* dsp 10-bit signed immediate in bit 16 */ | |
8160 | my_getExpression (&imm_expr, s); | |
8161 | check_absolute_expr (ip, &imm_expr); | |
8162 | min_range = -((OP_MASK_IMM10 + 1) >> 1); | |
8163 | max_range = ((OP_MASK_IMM10 + 1) >> 1) - 1; | |
8164 | if (imm_expr.X_add_number < min_range || | |
8165 | imm_expr.X_add_number > max_range) | |
8166 | { | |
8167 | as_warn (_("DSP immediate not in range %ld..%ld (%ld)"), | |
8168 | (long) min_range, (long) max_range, | |
8169 | (long) imm_expr.X_add_number); | |
8170 | } | |
8171 | imm_expr.X_add_number &= OP_MASK_IMM10; | |
8172 | ip->insn_opcode |= ((unsigned long) imm_expr.X_add_number | |
8173 | << OP_SH_IMM10); | |
8174 | imm_expr.X_op = O_absent; | |
8175 | s = expr_end; | |
8176 | continue; | |
8177 | ||
ef2e4d86 CF |
8178 | case '!': /* mt 1-bit unsigned immediate in bit 5 */ |
8179 | my_getExpression (&imm_expr, s); | |
8180 | check_absolute_expr (ip, &imm_expr); | |
8181 | if (imm_expr.X_add_number & ~OP_MASK_MT_U) | |
8182 | { | |
8183 | as_warn (_("MT immediate not in range 0..%d (%lu)"), | |
8184 | OP_MASK_MT_U, (unsigned long) imm_expr.X_add_number); | |
8185 | imm_expr.X_add_number &= OP_MASK_MT_U; | |
8186 | } | |
8187 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_MT_U; | |
8188 | imm_expr.X_op = O_absent; | |
8189 | s = expr_end; | |
8190 | continue; | |
8191 | ||
8192 | case '$': /* mt 1-bit unsigned immediate in bit 4 */ | |
8193 | my_getExpression (&imm_expr, s); | |
8194 | check_absolute_expr (ip, &imm_expr); | |
8195 | if (imm_expr.X_add_number & ~OP_MASK_MT_H) | |
8196 | { | |
8197 | as_warn (_("MT immediate not in range 0..%d (%lu)"), | |
8198 | OP_MASK_MT_H, (unsigned long) imm_expr.X_add_number); | |
8199 | imm_expr.X_add_number &= OP_MASK_MT_H; | |
8200 | } | |
8201 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_MT_H; | |
8202 | imm_expr.X_op = O_absent; | |
8203 | s = expr_end; | |
8204 | continue; | |
8205 | ||
8206 | case '*': /* four dsp accumulators in bits 18,19 */ | |
8207 | if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' && | |
8208 | s[3] >= '0' && s[3] <= '3') | |
8209 | { | |
8210 | regno = s[3] - '0'; | |
8211 | s += 4; | |
8212 | ip->insn_opcode |= regno << OP_SH_MTACC_T; | |
8213 | continue; | |
8214 | } | |
8215 | else | |
8216 | as_bad (_("Invalid dsp/smartmips acc register")); | |
8217 | break; | |
8218 | ||
8219 | case '&': /* four dsp accumulators in bits 13,14 */ | |
8220 | if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' && | |
8221 | s[3] >= '0' && s[3] <= '3') | |
8222 | { | |
8223 | regno = s[3] - '0'; | |
8224 | s += 4; | |
8225 | ip->insn_opcode |= regno << OP_SH_MTACC_D; | |
8226 | continue; | |
8227 | } | |
8228 | else | |
8229 | as_bad (_("Invalid dsp/smartmips acc register")); | |
8230 | break; | |
8231 | ||
252b5132 RH |
8232 | case ',': |
8233 | if (*s++ == *args) | |
8234 | continue; | |
8235 | s--; | |
8236 | switch (*++args) | |
8237 | { | |
8238 | case 'r': | |
8239 | case 'v': | |
bf12938e | 8240 | INSERT_OPERAND (RS, *ip, lastregno); |
252b5132 RH |
8241 | continue; |
8242 | ||
8243 | case 'w': | |
bf12938e | 8244 | INSERT_OPERAND (RT, *ip, lastregno); |
38487616 TS |
8245 | continue; |
8246 | ||
252b5132 | 8247 | case 'W': |
bf12938e | 8248 | INSERT_OPERAND (FT, *ip, lastregno); |
252b5132 RH |
8249 | continue; |
8250 | ||
8251 | case 'V': | |
bf12938e | 8252 | INSERT_OPERAND (FS, *ip, lastregno); |
252b5132 RH |
8253 | continue; |
8254 | } | |
8255 | break; | |
8256 | ||
8257 | case '(': | |
8258 | /* Handle optional base register. | |
8259 | Either the base register is omitted or | |
bdaaa2e1 | 8260 | we must have a left paren. */ |
252b5132 RH |
8261 | /* This is dependent on the next operand specifier |
8262 | is a base register specification. */ | |
8263 | assert (args[1] == 'b' || args[1] == '5' | |
8264 | || args[1] == '-' || args[1] == '4'); | |
8265 | if (*s == '\0') | |
8266 | return; | |
8267 | ||
8268 | case ')': /* these must match exactly */ | |
60b63b72 RS |
8269 | case '[': |
8270 | case ']': | |
252b5132 RH |
8271 | if (*s++ == *args) |
8272 | continue; | |
8273 | break; | |
8274 | ||
af7ee8bf CD |
8275 | case '+': /* Opcode extension character. */ |
8276 | switch (*++args) | |
8277 | { | |
071742cf CD |
8278 | case 'A': /* ins/ext position, becomes LSB. */ |
8279 | limlo = 0; | |
8280 | limhi = 31; | |
5f74bc13 CD |
8281 | goto do_lsb; |
8282 | case 'E': | |
8283 | limlo = 32; | |
8284 | limhi = 63; | |
8285 | goto do_lsb; | |
8286 | do_lsb: | |
071742cf CD |
8287 | my_getExpression (&imm_expr, s); |
8288 | check_absolute_expr (ip, &imm_expr); | |
8289 | if ((unsigned long) imm_expr.X_add_number < limlo | |
8290 | || (unsigned long) imm_expr.X_add_number > limhi) | |
8291 | { | |
8292 | as_bad (_("Improper position (%lu)"), | |
8293 | (unsigned long) imm_expr.X_add_number); | |
8294 | imm_expr.X_add_number = limlo; | |
8295 | } | |
8296 | lastpos = imm_expr.X_add_number; | |
bf12938e | 8297 | INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number); |
071742cf CD |
8298 | imm_expr.X_op = O_absent; |
8299 | s = expr_end; | |
8300 | continue; | |
8301 | ||
8302 | case 'B': /* ins size, becomes MSB. */ | |
8303 | limlo = 1; | |
8304 | limhi = 32; | |
5f74bc13 CD |
8305 | goto do_msb; |
8306 | case 'F': | |
8307 | limlo = 33; | |
8308 | limhi = 64; | |
8309 | goto do_msb; | |
8310 | do_msb: | |
071742cf CD |
8311 | my_getExpression (&imm_expr, s); |
8312 | check_absolute_expr (ip, &imm_expr); | |
8313 | /* Check for negative input so that small negative numbers | |
8314 | will not succeed incorrectly. The checks against | |
8315 | (pos+size) transitively check "size" itself, | |
8316 | assuming that "pos" is reasonable. */ | |
8317 | if ((long) imm_expr.X_add_number < 0 | |
8318 | || ((unsigned long) imm_expr.X_add_number | |
8319 | + lastpos) < limlo | |
8320 | || ((unsigned long) imm_expr.X_add_number | |
8321 | + lastpos) > limhi) | |
8322 | { | |
8323 | as_bad (_("Improper insert size (%lu, position %lu)"), | |
8324 | (unsigned long) imm_expr.X_add_number, | |
8325 | (unsigned long) lastpos); | |
8326 | imm_expr.X_add_number = limlo - lastpos; | |
8327 | } | |
bf12938e RS |
8328 | INSERT_OPERAND (INSMSB, *ip, |
8329 | lastpos + imm_expr.X_add_number - 1); | |
071742cf CD |
8330 | imm_expr.X_op = O_absent; |
8331 | s = expr_end; | |
8332 | continue; | |
8333 | ||
8334 | case 'C': /* ext size, becomes MSBD. */ | |
8335 | limlo = 1; | |
8336 | limhi = 32; | |
5f74bc13 CD |
8337 | goto do_msbd; |
8338 | case 'G': | |
8339 | limlo = 33; | |
8340 | limhi = 64; | |
8341 | goto do_msbd; | |
8342 | case 'H': | |
8343 | limlo = 33; | |
8344 | limhi = 64; | |
8345 | goto do_msbd; | |
8346 | do_msbd: | |
071742cf CD |
8347 | my_getExpression (&imm_expr, s); |
8348 | check_absolute_expr (ip, &imm_expr); | |
8349 | /* Check for negative input so that small negative numbers | |
8350 | will not succeed incorrectly. The checks against | |
8351 | (pos+size) transitively check "size" itself, | |
8352 | assuming that "pos" is reasonable. */ | |
8353 | if ((long) imm_expr.X_add_number < 0 | |
8354 | || ((unsigned long) imm_expr.X_add_number | |
8355 | + lastpos) < limlo | |
8356 | || ((unsigned long) imm_expr.X_add_number | |
8357 | + lastpos) > limhi) | |
8358 | { | |
8359 | as_bad (_("Improper extract size (%lu, position %lu)"), | |
8360 | (unsigned long) imm_expr.X_add_number, | |
8361 | (unsigned long) lastpos); | |
8362 | imm_expr.X_add_number = limlo - lastpos; | |
8363 | } | |
bf12938e | 8364 | INSERT_OPERAND (EXTMSBD, *ip, imm_expr.X_add_number - 1); |
071742cf CD |
8365 | imm_expr.X_op = O_absent; |
8366 | s = expr_end; | |
8367 | continue; | |
af7ee8bf | 8368 | |
bbcc0807 CD |
8369 | case 'D': |
8370 | /* +D is for disassembly only; never match. */ | |
8371 | break; | |
8372 | ||
5f74bc13 CD |
8373 | case 'I': |
8374 | /* "+I" is like "I", except that imm2_expr is used. */ | |
8375 | my_getExpression (&imm2_expr, s); | |
8376 | if (imm2_expr.X_op != O_big | |
8377 | && imm2_expr.X_op != O_constant) | |
8378 | insn_error = _("absolute expression required"); | |
9ee2a2d4 MR |
8379 | if (HAVE_32BIT_GPRS) |
8380 | normalize_constant_expr (&imm2_expr); | |
5f74bc13 CD |
8381 | s = expr_end; |
8382 | continue; | |
8383 | ||
ef2e4d86 CF |
8384 | case 'T': /* Coprocessor register */ |
8385 | /* +T is for disassembly only; never match. */ | |
8386 | break; | |
8387 | ||
8388 | case 't': /* Coprocessor register number */ | |
8389 | if (s[0] == '$' && ISDIGIT (s[1])) | |
8390 | { | |
8391 | ++s; | |
8392 | regno = 0; | |
8393 | do | |
8394 | { | |
8395 | regno *= 10; | |
8396 | regno += *s - '0'; | |
8397 | ++s; | |
8398 | } | |
8399 | while (ISDIGIT (*s)); | |
8400 | if (regno > 31) | |
8401 | as_bad (_("Invalid register number (%d)"), regno); | |
8402 | else | |
8403 | { | |
8404 | ip->insn_opcode |= regno << OP_SH_RT; | |
8405 | continue; | |
8406 | } | |
8407 | } | |
8408 | else | |
8409 | as_bad (_("Invalid coprocessor 0 register number")); | |
8410 | break; | |
8411 | ||
af7ee8bf CD |
8412 | default: |
8413 | as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"), | |
8414 | *args, insn->name, insn->args); | |
8415 | /* Further processing is fruitless. */ | |
8416 | return; | |
8417 | } | |
8418 | break; | |
8419 | ||
252b5132 RH |
8420 | case '<': /* must be at least one digit */ |
8421 | /* | |
8422 | * According to the manual, if the shift amount is greater | |
b6ff326e KH |
8423 | * than 31 or less than 0, then the shift amount should be |
8424 | * mod 32. In reality the mips assembler issues an error. | |
252b5132 RH |
8425 | * We issue a warning and mask out all but the low 5 bits. |
8426 | */ | |
8427 | my_getExpression (&imm_expr, s); | |
8428 | check_absolute_expr (ip, &imm_expr); | |
8429 | if ((unsigned long) imm_expr.X_add_number > 31) | |
bf12938e RS |
8430 | as_warn (_("Improper shift amount (%lu)"), |
8431 | (unsigned long) imm_expr.X_add_number); | |
8432 | INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number); | |
252b5132 RH |
8433 | imm_expr.X_op = O_absent; |
8434 | s = expr_end; | |
8435 | continue; | |
8436 | ||
8437 | case '>': /* shift amount minus 32 */ | |
8438 | my_getExpression (&imm_expr, s); | |
8439 | check_absolute_expr (ip, &imm_expr); | |
8440 | if ((unsigned long) imm_expr.X_add_number < 32 | |
8441 | || (unsigned long) imm_expr.X_add_number > 63) | |
8442 | break; | |
bf12938e | 8443 | INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number - 32); |
252b5132 RH |
8444 | imm_expr.X_op = O_absent; |
8445 | s = expr_end; | |
8446 | continue; | |
8447 | ||
252b5132 RH |
8448 | case 'k': /* cache code */ |
8449 | case 'h': /* prefx code */ | |
8450 | my_getExpression (&imm_expr, s); | |
8451 | check_absolute_expr (ip, &imm_expr); | |
8452 | if ((unsigned long) imm_expr.X_add_number > 31) | |
bf12938e RS |
8453 | as_warn (_("Invalid value for `%s' (%lu)"), |
8454 | ip->insn_mo->name, | |
8455 | (unsigned long) imm_expr.X_add_number); | |
252b5132 | 8456 | if (*args == 'k') |
bf12938e | 8457 | INSERT_OPERAND (CACHE, *ip, imm_expr.X_add_number); |
252b5132 | 8458 | else |
bf12938e | 8459 | INSERT_OPERAND (PREFX, *ip, imm_expr.X_add_number); |
252b5132 RH |
8460 | imm_expr.X_op = O_absent; |
8461 | s = expr_end; | |
8462 | continue; | |
8463 | ||
8464 | case 'c': /* break code */ | |
8465 | my_getExpression (&imm_expr, s); | |
8466 | check_absolute_expr (ip, &imm_expr); | |
793b27f4 | 8467 | if ((unsigned long) imm_expr.X_add_number > 1023) |
bf12938e RS |
8468 | as_warn (_("Illegal break code (%lu)"), |
8469 | (unsigned long) imm_expr.X_add_number); | |
8470 | INSERT_OPERAND (CODE, *ip, imm_expr.X_add_number); | |
252b5132 RH |
8471 | imm_expr.X_op = O_absent; |
8472 | s = expr_end; | |
8473 | continue; | |
8474 | ||
8475 | case 'q': /* lower break code */ | |
8476 | my_getExpression (&imm_expr, s); | |
8477 | check_absolute_expr (ip, &imm_expr); | |
793b27f4 | 8478 | if ((unsigned long) imm_expr.X_add_number > 1023) |
bf12938e RS |
8479 | as_warn (_("Illegal lower break code (%lu)"), |
8480 | (unsigned long) imm_expr.X_add_number); | |
8481 | INSERT_OPERAND (CODE2, *ip, imm_expr.X_add_number); | |
252b5132 RH |
8482 | imm_expr.X_op = O_absent; |
8483 | s = expr_end; | |
8484 | continue; | |
8485 | ||
4372b673 | 8486 | case 'B': /* 20-bit syscall/break code. */ |
156c2f8b | 8487 | my_getExpression (&imm_expr, s); |
156c2f8b | 8488 | check_absolute_expr (ip, &imm_expr); |
793b27f4 TS |
8489 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE20) |
8490 | as_warn (_("Illegal 20-bit code (%lu)"), | |
8491 | (unsigned long) imm_expr.X_add_number); | |
bf12938e | 8492 | INSERT_OPERAND (CODE20, *ip, imm_expr.X_add_number); |
252b5132 RH |
8493 | imm_expr.X_op = O_absent; |
8494 | s = expr_end; | |
8495 | continue; | |
8496 | ||
98d3f06f | 8497 | case 'C': /* Coprocessor code */ |
beae10d5 | 8498 | my_getExpression (&imm_expr, s); |
252b5132 | 8499 | check_absolute_expr (ip, &imm_expr); |
98d3f06f | 8500 | if ((unsigned long) imm_expr.X_add_number >= (1 << 25)) |
252b5132 | 8501 | { |
793b27f4 TS |
8502 | as_warn (_("Coproccesor code > 25 bits (%lu)"), |
8503 | (unsigned long) imm_expr.X_add_number); | |
98d3f06f | 8504 | imm_expr.X_add_number &= ((1 << 25) - 1); |
252b5132 | 8505 | } |
beae10d5 KH |
8506 | ip->insn_opcode |= imm_expr.X_add_number; |
8507 | imm_expr.X_op = O_absent; | |
8508 | s = expr_end; | |
8509 | continue; | |
252b5132 | 8510 | |
4372b673 NC |
8511 | case 'J': /* 19-bit wait code. */ |
8512 | my_getExpression (&imm_expr, s); | |
8513 | check_absolute_expr (ip, &imm_expr); | |
793b27f4 TS |
8514 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE19) |
8515 | as_warn (_("Illegal 19-bit code (%lu)"), | |
8516 | (unsigned long) imm_expr.X_add_number); | |
bf12938e | 8517 | INSERT_OPERAND (CODE19, *ip, imm_expr.X_add_number); |
4372b673 NC |
8518 | imm_expr.X_op = O_absent; |
8519 | s = expr_end; | |
8520 | continue; | |
8521 | ||
252b5132 | 8522 | case 'P': /* Performance register */ |
beae10d5 | 8523 | my_getExpression (&imm_expr, s); |
252b5132 | 8524 | check_absolute_expr (ip, &imm_expr); |
beae10d5 | 8525 | if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1) |
bf12938e RS |
8526 | as_warn (_("Invalid performance register (%lu)"), |
8527 | (unsigned long) imm_expr.X_add_number); | |
8528 | INSERT_OPERAND (PERFREG, *ip, imm_expr.X_add_number); | |
beae10d5 KH |
8529 | imm_expr.X_op = O_absent; |
8530 | s = expr_end; | |
8531 | continue; | |
252b5132 RH |
8532 | |
8533 | case 'b': /* base register */ | |
8534 | case 'd': /* destination register */ | |
8535 | case 's': /* source register */ | |
8536 | case 't': /* target register */ | |
8537 | case 'r': /* both target and source */ | |
8538 | case 'v': /* both dest and source */ | |
8539 | case 'w': /* both dest and target */ | |
8540 | case 'E': /* coprocessor target register */ | |
8541 | case 'G': /* coprocessor destination register */ | |
af7ee8bf | 8542 | case 'K': /* 'rdhwr' destination register */ |
252b5132 RH |
8543 | case 'x': /* ignore register name */ |
8544 | case 'z': /* must be zero register */ | |
4372b673 | 8545 | case 'U': /* destination register (clo/clz). */ |
ef2e4d86 | 8546 | case 'g': /* coprocessor destination register */ |
252b5132 RH |
8547 | s_reset = s; |
8548 | if (s[0] == '$') | |
8549 | { | |
8550 | ||
3882b010 | 8551 | if (ISDIGIT (s[1])) |
252b5132 RH |
8552 | { |
8553 | ++s; | |
8554 | regno = 0; | |
8555 | do | |
8556 | { | |
8557 | regno *= 10; | |
8558 | regno += *s - '0'; | |
8559 | ++s; | |
8560 | } | |
3882b010 | 8561 | while (ISDIGIT (*s)); |
252b5132 RH |
8562 | if (regno > 31) |
8563 | as_bad (_("Invalid register number (%d)"), regno); | |
8564 | } | |
af7ee8bf | 8565 | else if (*args == 'E' || *args == 'G' || *args == 'K') |
252b5132 RH |
8566 | goto notreg; |
8567 | else | |
8568 | { | |
76db943d TS |
8569 | if (s[1] == 'r' && s[2] == 'a') |
8570 | { | |
8571 | s += 3; | |
8572 | regno = RA; | |
8573 | } | |
8574 | else if (s[1] == 'f' && s[2] == 'p') | |
252b5132 RH |
8575 | { |
8576 | s += 3; | |
8577 | regno = FP; | |
8578 | } | |
8579 | else if (s[1] == 's' && s[2] == 'p') | |
8580 | { | |
8581 | s += 3; | |
8582 | regno = SP; | |
8583 | } | |
8584 | else if (s[1] == 'g' && s[2] == 'p') | |
8585 | { | |
8586 | s += 3; | |
8587 | regno = GP; | |
8588 | } | |
8589 | else if (s[1] == 'a' && s[2] == 't') | |
8590 | { | |
8591 | s += 3; | |
8592 | regno = AT; | |
8593 | } | |
8594 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '0') | |
8595 | { | |
8596 | s += 4; | |
8597 | regno = KT0; | |
8598 | } | |
8599 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '1') | |
8600 | { | |
8601 | s += 4; | |
8602 | regno = KT1; | |
8603 | } | |
85b51719 TS |
8604 | else if (s[1] == 'z' && s[2] == 'e' && s[3] == 'r' && s[4] == 'o') |
8605 | { | |
8606 | s += 5; | |
8607 | regno = ZERO; | |
8608 | } | |
252b5132 RH |
8609 | else if (itbl_have_entries) |
8610 | { | |
8611 | char *p, *n; | |
d7ba4a77 | 8612 | unsigned long r; |
252b5132 | 8613 | |
d7ba4a77 | 8614 | p = s + 1; /* advance past '$' */ |
252b5132 RH |
8615 | n = itbl_get_field (&p); /* n is name */ |
8616 | ||
d7ba4a77 ILT |
8617 | /* See if this is a register defined in an |
8618 | itbl entry. */ | |
8619 | if (itbl_get_reg_val (n, &r)) | |
252b5132 RH |
8620 | { |
8621 | /* Get_field advances to the start of | |
8622 | the next field, so we need to back | |
d7ba4a77 | 8623 | rack to the end of the last field. */ |
bdaaa2e1 | 8624 | if (p) |
252b5132 | 8625 | s = p - 1; |
bdaaa2e1 | 8626 | else |
d7ba4a77 | 8627 | s = strchr (s, '\0'); |
252b5132 RH |
8628 | regno = r; |
8629 | } | |
8630 | else | |
8631 | goto notreg; | |
beae10d5 | 8632 | } |
252b5132 RH |
8633 | else |
8634 | goto notreg; | |
8635 | } | |
8636 | if (regno == AT | |
8637 | && ! mips_opts.noat | |
8638 | && *args != 'E' | |
af7ee8bf CD |
8639 | && *args != 'G' |
8640 | && *args != 'K') | |
252b5132 RH |
8641 | as_warn (_("Used $at without \".set noat\"")); |
8642 | c = *args; | |
8643 | if (*s == ' ') | |
f9419b05 | 8644 | ++s; |
252b5132 RH |
8645 | if (args[1] != *s) |
8646 | { | |
8647 | if (c == 'r' || c == 'v' || c == 'w') | |
8648 | { | |
8649 | regno = lastregno; | |
8650 | s = s_reset; | |
f9419b05 | 8651 | ++args; |
252b5132 RH |
8652 | } |
8653 | } | |
8654 | /* 'z' only matches $0. */ | |
8655 | if (c == 'z' && regno != 0) | |
8656 | break; | |
8657 | ||
bdaaa2e1 KH |
8658 | /* Now that we have assembled one operand, we use the args string |
8659 | * to figure out where it goes in the instruction. */ | |
252b5132 RH |
8660 | switch (c) |
8661 | { | |
8662 | case 'r': | |
8663 | case 's': | |
8664 | case 'v': | |
8665 | case 'b': | |
bf12938e | 8666 | INSERT_OPERAND (RS, *ip, regno); |
252b5132 RH |
8667 | break; |
8668 | case 'd': | |
8669 | case 'G': | |
af7ee8bf | 8670 | case 'K': |
ef2e4d86 | 8671 | case 'g': |
bf12938e | 8672 | INSERT_OPERAND (RD, *ip, regno); |
252b5132 | 8673 | break; |
4372b673 | 8674 | case 'U': |
bf12938e RS |
8675 | INSERT_OPERAND (RD, *ip, regno); |
8676 | INSERT_OPERAND (RT, *ip, regno); | |
4372b673 | 8677 | break; |
252b5132 RH |
8678 | case 'w': |
8679 | case 't': | |
8680 | case 'E': | |
bf12938e | 8681 | INSERT_OPERAND (RT, *ip, regno); |
252b5132 RH |
8682 | break; |
8683 | case 'x': | |
8684 | /* This case exists because on the r3000 trunc | |
8685 | expands into a macro which requires a gp | |
8686 | register. On the r6000 or r4000 it is | |
8687 | assembled into a single instruction which | |
8688 | ignores the register. Thus the insn version | |
8689 | is MIPS_ISA2 and uses 'x', and the macro | |
8690 | version is MIPS_ISA1 and uses 't'. */ | |
8691 | break; | |
8692 | case 'z': | |
8693 | /* This case is for the div instruction, which | |
8694 | acts differently if the destination argument | |
8695 | is $0. This only matches $0, and is checked | |
8696 | outside the switch. */ | |
8697 | break; | |
8698 | case 'D': | |
8699 | /* Itbl operand; not yet implemented. FIXME ?? */ | |
8700 | break; | |
8701 | /* What about all other operands like 'i', which | |
8702 | can be specified in the opcode table? */ | |
8703 | } | |
8704 | lastregno = regno; | |
8705 | continue; | |
8706 | } | |
8707 | notreg: | |
8708 | switch (*args++) | |
8709 | { | |
8710 | case 'r': | |
8711 | case 'v': | |
bf12938e | 8712 | INSERT_OPERAND (RS, *ip, lastregno); |
252b5132 RH |
8713 | continue; |
8714 | case 'w': | |
bf12938e | 8715 | INSERT_OPERAND (RT, *ip, lastregno); |
252b5132 RH |
8716 | continue; |
8717 | } | |
8718 | break; | |
8719 | ||
deec1734 CD |
8720 | case 'O': /* MDMX alignment immediate constant. */ |
8721 | my_getExpression (&imm_expr, s); | |
8722 | check_absolute_expr (ip, &imm_expr); | |
8723 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_ALN) | |
bf12938e RS |
8724 | as_warn ("Improper align amount (%ld), using low bits", |
8725 | (long) imm_expr.X_add_number); | |
8726 | INSERT_OPERAND (ALN, *ip, imm_expr.X_add_number); | |
deec1734 CD |
8727 | imm_expr.X_op = O_absent; |
8728 | s = expr_end; | |
8729 | continue; | |
8730 | ||
8731 | case 'Q': /* MDMX vector, element sel, or const. */ | |
8732 | if (s[0] != '$') | |
8733 | { | |
8734 | /* MDMX Immediate. */ | |
8735 | my_getExpression (&imm_expr, s); | |
8736 | check_absolute_expr (ip, &imm_expr); | |
8737 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_FT) | |
bf12938e RS |
8738 | as_warn (_("Invalid MDMX Immediate (%ld)"), |
8739 | (long) imm_expr.X_add_number); | |
8740 | INSERT_OPERAND (FT, *ip, imm_expr.X_add_number); | |
deec1734 CD |
8741 | if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL)) |
8742 | ip->insn_opcode |= MDMX_FMTSEL_IMM_QH << OP_SH_VSEL; | |
8743 | else | |
8744 | ip->insn_opcode |= MDMX_FMTSEL_IMM_OB << OP_SH_VSEL; | |
deec1734 CD |
8745 | imm_expr.X_op = O_absent; |
8746 | s = expr_end; | |
8747 | continue; | |
8748 | } | |
8749 | /* Not MDMX Immediate. Fall through. */ | |
8750 | case 'X': /* MDMX destination register. */ | |
8751 | case 'Y': /* MDMX source register. */ | |
8752 | case 'Z': /* MDMX target register. */ | |
8753 | is_mdmx = 1; | |
252b5132 RH |
8754 | case 'D': /* floating point destination register */ |
8755 | case 'S': /* floating point source register */ | |
8756 | case 'T': /* floating point target register */ | |
8757 | case 'R': /* floating point source register */ | |
8758 | case 'V': | |
8759 | case 'W': | |
8760 | s_reset = s; | |
deec1734 CD |
8761 | /* Accept $fN for FP and MDMX register numbers, and in |
8762 | addition accept $vN for MDMX register numbers. */ | |
8763 | if ((s[0] == '$' && s[1] == 'f' && ISDIGIT (s[2])) | |
8764 | || (is_mdmx != 0 && s[0] == '$' && s[1] == 'v' | |
8765 | && ISDIGIT (s[2]))) | |
252b5132 RH |
8766 | { |
8767 | s += 2; | |
8768 | regno = 0; | |
8769 | do | |
8770 | { | |
8771 | regno *= 10; | |
8772 | regno += *s - '0'; | |
8773 | ++s; | |
8774 | } | |
3882b010 | 8775 | while (ISDIGIT (*s)); |
252b5132 RH |
8776 | |
8777 | if (regno > 31) | |
8778 | as_bad (_("Invalid float register number (%d)"), regno); | |
8779 | ||
8780 | if ((regno & 1) != 0 | |
ca4e0257 | 8781 | && HAVE_32BIT_FPRS |
252b5132 RH |
8782 | && ! (strcmp (str, "mtc1") == 0 |
8783 | || strcmp (str, "mfc1") == 0 | |
8784 | || strcmp (str, "lwc1") == 0 | |
8785 | || strcmp (str, "swc1") == 0 | |
8786 | || strcmp (str, "l.s") == 0 | |
ef2e4d86 CF |
8787 | || strcmp (str, "s.s") == 0 |
8788 | || strcmp (str, "mftc1") == 0 | |
8789 | || strcmp (str, "mfthc1") == 0 | |
8790 | || strcmp (str, "cftc1") == 0 | |
8791 | || strcmp (str, "mttc1") == 0 | |
8792 | || strcmp (str, "mtthc1") == 0 | |
8793 | || strcmp (str, "cttc1") == 0)) | |
252b5132 RH |
8794 | as_warn (_("Float register should be even, was %d"), |
8795 | regno); | |
8796 | ||
8797 | c = *args; | |
8798 | if (*s == ' ') | |
f9419b05 | 8799 | ++s; |
252b5132 RH |
8800 | if (args[1] != *s) |
8801 | { | |
8802 | if (c == 'V' || c == 'W') | |
8803 | { | |
8804 | regno = lastregno; | |
8805 | s = s_reset; | |
f9419b05 | 8806 | ++args; |
252b5132 RH |
8807 | } |
8808 | } | |
8809 | switch (c) | |
8810 | { | |
8811 | case 'D': | |
deec1734 | 8812 | case 'X': |
bf12938e | 8813 | INSERT_OPERAND (FD, *ip, regno); |
252b5132 RH |
8814 | break; |
8815 | case 'V': | |
8816 | case 'S': | |
deec1734 | 8817 | case 'Y': |
bf12938e | 8818 | INSERT_OPERAND (FS, *ip, regno); |
252b5132 | 8819 | break; |
deec1734 CD |
8820 | case 'Q': |
8821 | /* This is like 'Z', but also needs to fix the MDMX | |
8822 | vector/scalar select bits. Note that the | |
8823 | scalar immediate case is handled above. */ | |
8824 | if (*s == '[') | |
8825 | { | |
8826 | int is_qh = (ip->insn_opcode & (1 << OP_SH_VSEL)); | |
8827 | int max_el = (is_qh ? 3 : 7); | |
8828 | s++; | |
8829 | my_getExpression(&imm_expr, s); | |
8830 | check_absolute_expr (ip, &imm_expr); | |
8831 | s = expr_end; | |
8832 | if (imm_expr.X_add_number > max_el) | |
8833 | as_bad(_("Bad element selector %ld"), | |
8834 | (long) imm_expr.X_add_number); | |
8835 | imm_expr.X_add_number &= max_el; | |
8836 | ip->insn_opcode |= (imm_expr.X_add_number | |
8837 | << (OP_SH_VSEL + | |
8838 | (is_qh ? 2 : 1))); | |
01a3f561 | 8839 | imm_expr.X_op = O_absent; |
deec1734 CD |
8840 | if (*s != ']') |
8841 | as_warn(_("Expecting ']' found '%s'"), s); | |
8842 | else | |
8843 | s++; | |
8844 | } | |
8845 | else | |
8846 | { | |
8847 | if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL)) | |
8848 | ip->insn_opcode |= (MDMX_FMTSEL_VEC_QH | |
8849 | << OP_SH_VSEL); | |
8850 | else | |
8851 | ip->insn_opcode |= (MDMX_FMTSEL_VEC_OB << | |
8852 | OP_SH_VSEL); | |
8853 | } | |
8854 | /* Fall through */ | |
252b5132 RH |
8855 | case 'W': |
8856 | case 'T': | |
deec1734 | 8857 | case 'Z': |
bf12938e | 8858 | INSERT_OPERAND (FT, *ip, regno); |
252b5132 RH |
8859 | break; |
8860 | case 'R': | |
bf12938e | 8861 | INSERT_OPERAND (FR, *ip, regno); |
252b5132 RH |
8862 | break; |
8863 | } | |
8864 | lastregno = regno; | |
8865 | continue; | |
8866 | } | |
8867 | ||
252b5132 RH |
8868 | switch (*args++) |
8869 | { | |
8870 | case 'V': | |
bf12938e | 8871 | INSERT_OPERAND (FS, *ip, lastregno); |
252b5132 RH |
8872 | continue; |
8873 | case 'W': | |
bf12938e | 8874 | INSERT_OPERAND (FT, *ip, lastregno); |
252b5132 RH |
8875 | continue; |
8876 | } | |
8877 | break; | |
8878 | ||
8879 | case 'I': | |
8880 | my_getExpression (&imm_expr, s); | |
8881 | if (imm_expr.X_op != O_big | |
8882 | && imm_expr.X_op != O_constant) | |
8883 | insn_error = _("absolute expression required"); | |
9ee2a2d4 MR |
8884 | if (HAVE_32BIT_GPRS) |
8885 | normalize_constant_expr (&imm_expr); | |
252b5132 RH |
8886 | s = expr_end; |
8887 | continue; | |
8888 | ||
8889 | case 'A': | |
8890 | my_getExpression (&offset_expr, s); | |
2051e8c4 | 8891 | normalize_address_expr (&offset_expr); |
f6688943 | 8892 | *imm_reloc = BFD_RELOC_32; |
252b5132 RH |
8893 | s = expr_end; |
8894 | continue; | |
8895 | ||
8896 | case 'F': | |
8897 | case 'L': | |
8898 | case 'f': | |
8899 | case 'l': | |
8900 | { | |
8901 | int f64; | |
ca4e0257 | 8902 | int using_gprs; |
252b5132 RH |
8903 | char *save_in; |
8904 | char *err; | |
8905 | unsigned char temp[8]; | |
8906 | int len; | |
8907 | unsigned int length; | |
8908 | segT seg; | |
8909 | subsegT subseg; | |
8910 | char *p; | |
8911 | ||
8912 | /* These only appear as the last operand in an | |
8913 | instruction, and every instruction that accepts | |
8914 | them in any variant accepts them in all variants. | |
8915 | This means we don't have to worry about backing out | |
8916 | any changes if the instruction does not match. | |
8917 | ||
8918 | The difference between them is the size of the | |
8919 | floating point constant and where it goes. For 'F' | |
8920 | and 'L' the constant is 64 bits; for 'f' and 'l' it | |
8921 | is 32 bits. Where the constant is placed is based | |
8922 | on how the MIPS assembler does things: | |
8923 | F -- .rdata | |
8924 | L -- .lit8 | |
8925 | f -- immediate value | |
8926 | l -- .lit4 | |
8927 | ||
8928 | The .lit4 and .lit8 sections are only used if | |
8929 | permitted by the -G argument. | |
8930 | ||
ca4e0257 RS |
8931 | The code below needs to know whether the target register |
8932 | is 32 or 64 bits wide. It relies on the fact 'f' and | |
8933 | 'F' are used with GPR-based instructions and 'l' and | |
8934 | 'L' are used with FPR-based instructions. */ | |
252b5132 RH |
8935 | |
8936 | f64 = *args == 'F' || *args == 'L'; | |
ca4e0257 | 8937 | using_gprs = *args == 'F' || *args == 'f'; |
252b5132 RH |
8938 | |
8939 | save_in = input_line_pointer; | |
8940 | input_line_pointer = s; | |
8941 | err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len); | |
8942 | length = len; | |
8943 | s = input_line_pointer; | |
8944 | input_line_pointer = save_in; | |
8945 | if (err != NULL && *err != '\0') | |
8946 | { | |
8947 | as_bad (_("Bad floating point constant: %s"), err); | |
8948 | memset (temp, '\0', sizeof temp); | |
8949 | length = f64 ? 8 : 4; | |
8950 | } | |
8951 | ||
156c2f8b | 8952 | assert (length == (unsigned) (f64 ? 8 : 4)); |
252b5132 RH |
8953 | |
8954 | if (*args == 'f' | |
8955 | || (*args == 'l' | |
3e722fb5 | 8956 | && (g_switch_value < 4 |
252b5132 RH |
8957 | || (temp[0] == 0 && temp[1] == 0) |
8958 | || (temp[2] == 0 && temp[3] == 0)))) | |
8959 | { | |
8960 | imm_expr.X_op = O_constant; | |
8961 | if (! target_big_endian) | |
8962 | imm_expr.X_add_number = bfd_getl32 (temp); | |
8963 | else | |
8964 | imm_expr.X_add_number = bfd_getb32 (temp); | |
8965 | } | |
8966 | else if (length > 4 | |
119d663a | 8967 | && ! mips_disable_float_construction |
ca4e0257 RS |
8968 | /* Constants can only be constructed in GPRs and |
8969 | copied to FPRs if the GPRs are at least as wide | |
8970 | as the FPRs. Force the constant into memory if | |
8971 | we are using 64-bit FPRs but the GPRs are only | |
8972 | 32 bits wide. */ | |
8973 | && (using_gprs | |
8974 | || ! (HAVE_64BIT_FPRS && HAVE_32BIT_GPRS)) | |
252b5132 RH |
8975 | && ((temp[0] == 0 && temp[1] == 0) |
8976 | || (temp[2] == 0 && temp[3] == 0)) | |
8977 | && ((temp[4] == 0 && temp[5] == 0) | |
8978 | || (temp[6] == 0 && temp[7] == 0))) | |
8979 | { | |
ca4e0257 RS |
8980 | /* The value is simple enough to load with a couple of |
8981 | instructions. If using 32-bit registers, set | |
8982 | imm_expr to the high order 32 bits and offset_expr to | |
8983 | the low order 32 bits. Otherwise, set imm_expr to | |
8984 | the entire 64 bit constant. */ | |
8985 | if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS) | |
252b5132 RH |
8986 | { |
8987 | imm_expr.X_op = O_constant; | |
8988 | offset_expr.X_op = O_constant; | |
8989 | if (! target_big_endian) | |
8990 | { | |
8991 | imm_expr.X_add_number = bfd_getl32 (temp + 4); | |
8992 | offset_expr.X_add_number = bfd_getl32 (temp); | |
8993 | } | |
8994 | else | |
8995 | { | |
8996 | imm_expr.X_add_number = bfd_getb32 (temp); | |
8997 | offset_expr.X_add_number = bfd_getb32 (temp + 4); | |
8998 | } | |
8999 | if (offset_expr.X_add_number == 0) | |
9000 | offset_expr.X_op = O_absent; | |
9001 | } | |
9002 | else if (sizeof (imm_expr.X_add_number) > 4) | |
9003 | { | |
9004 | imm_expr.X_op = O_constant; | |
9005 | if (! target_big_endian) | |
9006 | imm_expr.X_add_number = bfd_getl64 (temp); | |
9007 | else | |
9008 | imm_expr.X_add_number = bfd_getb64 (temp); | |
9009 | } | |
9010 | else | |
9011 | { | |
9012 | imm_expr.X_op = O_big; | |
9013 | imm_expr.X_add_number = 4; | |
9014 | if (! target_big_endian) | |
9015 | { | |
9016 | generic_bignum[0] = bfd_getl16 (temp); | |
9017 | generic_bignum[1] = bfd_getl16 (temp + 2); | |
9018 | generic_bignum[2] = bfd_getl16 (temp + 4); | |
9019 | generic_bignum[3] = bfd_getl16 (temp + 6); | |
9020 | } | |
9021 | else | |
9022 | { | |
9023 | generic_bignum[0] = bfd_getb16 (temp + 6); | |
9024 | generic_bignum[1] = bfd_getb16 (temp + 4); | |
9025 | generic_bignum[2] = bfd_getb16 (temp + 2); | |
9026 | generic_bignum[3] = bfd_getb16 (temp); | |
9027 | } | |
9028 | } | |
9029 | } | |
9030 | else | |
9031 | { | |
9032 | const char *newname; | |
9033 | segT new_seg; | |
9034 | ||
9035 | /* Switch to the right section. */ | |
9036 | seg = now_seg; | |
9037 | subseg = now_subseg; | |
9038 | switch (*args) | |
9039 | { | |
9040 | default: /* unused default case avoids warnings. */ | |
9041 | case 'L': | |
9042 | newname = RDATA_SECTION_NAME; | |
3e722fb5 | 9043 | if (g_switch_value >= 8) |
252b5132 RH |
9044 | newname = ".lit8"; |
9045 | break; | |
9046 | case 'F': | |
3e722fb5 | 9047 | newname = RDATA_SECTION_NAME; |
252b5132 RH |
9048 | break; |
9049 | case 'l': | |
4d0d148d | 9050 | assert (g_switch_value >= 4); |
252b5132 RH |
9051 | newname = ".lit4"; |
9052 | break; | |
9053 | } | |
9054 | new_seg = subseg_new (newname, (subsegT) 0); | |
9055 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
9056 | bfd_set_section_flags (stdoutput, new_seg, | |
9057 | (SEC_ALLOC | |
9058 | | SEC_LOAD | |
9059 | | SEC_READONLY | |
9060 | | SEC_DATA)); | |
9061 | frag_align (*args == 'l' ? 2 : 3, 0, 0); | |
9062 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour | |
9063 | && strcmp (TARGET_OS, "elf") != 0) | |
9064 | record_alignment (new_seg, 4); | |
9065 | else | |
9066 | record_alignment (new_seg, *args == 'l' ? 2 : 3); | |
9067 | if (seg == now_seg) | |
9068 | as_bad (_("Can't use floating point insn in this section")); | |
9069 | ||
9070 | /* Set the argument to the current address in the | |
9071 | section. */ | |
9072 | offset_expr.X_op = O_symbol; | |
9073 | offset_expr.X_add_symbol = | |
9074 | symbol_new ("L0\001", now_seg, | |
9075 | (valueT) frag_now_fix (), frag_now); | |
9076 | offset_expr.X_add_number = 0; | |
9077 | ||
9078 | /* Put the floating point number into the section. */ | |
9079 | p = frag_more ((int) length); | |
9080 | memcpy (p, temp, length); | |
9081 | ||
9082 | /* Switch back to the original section. */ | |
9083 | subseg_set (seg, subseg); | |
9084 | } | |
9085 | } | |
9086 | continue; | |
9087 | ||
9088 | case 'i': /* 16 bit unsigned immediate */ | |
9089 | case 'j': /* 16 bit signed immediate */ | |
f6688943 | 9090 | *imm_reloc = BFD_RELOC_LO16; |
5e0116d5 | 9091 | if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0) |
252b5132 RH |
9092 | { |
9093 | int more; | |
5e0116d5 RS |
9094 | offsetT minval, maxval; |
9095 | ||
9096 | more = (insn + 1 < &mips_opcodes[NUMOPCODES] | |
9097 | && strcmp (insn->name, insn[1].name) == 0); | |
9098 | ||
9099 | /* If the expression was written as an unsigned number, | |
9100 | only treat it as signed if there are no more | |
9101 | alternatives. */ | |
9102 | if (more | |
9103 | && *args == 'j' | |
9104 | && sizeof (imm_expr.X_add_number) <= 4 | |
9105 | && imm_expr.X_op == O_constant | |
9106 | && imm_expr.X_add_number < 0 | |
9107 | && imm_expr.X_unsigned | |
9108 | && HAVE_64BIT_GPRS) | |
9109 | break; | |
9110 | ||
9111 | /* For compatibility with older assemblers, we accept | |
9112 | 0x8000-0xffff as signed 16-bit numbers when only | |
9113 | signed numbers are allowed. */ | |
9114 | if (*args == 'i') | |
9115 | minval = 0, maxval = 0xffff; | |
9116 | else if (more) | |
9117 | minval = -0x8000, maxval = 0x7fff; | |
252b5132 | 9118 | else |
5e0116d5 RS |
9119 | minval = -0x8000, maxval = 0xffff; |
9120 | ||
9121 | if (imm_expr.X_op != O_constant | |
9122 | || imm_expr.X_add_number < minval | |
9123 | || imm_expr.X_add_number > maxval) | |
252b5132 RH |
9124 | { |
9125 | if (more) | |
9126 | break; | |
2ae7e77b AH |
9127 | if (imm_expr.X_op == O_constant |
9128 | || imm_expr.X_op == O_big) | |
5e0116d5 | 9129 | as_bad (_("expression out of range")); |
252b5132 RH |
9130 | } |
9131 | } | |
9132 | s = expr_end; | |
9133 | continue; | |
9134 | ||
9135 | case 'o': /* 16 bit offset */ | |
5e0116d5 RS |
9136 | /* Check whether there is only a single bracketed expression |
9137 | left. If so, it must be the base register and the | |
9138 | constant must be zero. */ | |
9139 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
9140 | { | |
9141 | offset_expr.X_op = O_constant; | |
9142 | offset_expr.X_add_number = 0; | |
9143 | continue; | |
9144 | } | |
252b5132 RH |
9145 | |
9146 | /* If this value won't fit into a 16 bit offset, then go | |
9147 | find a macro that will generate the 32 bit offset | |
afdbd6d0 | 9148 | code pattern. */ |
5e0116d5 | 9149 | if (my_getSmallExpression (&offset_expr, offset_reloc, s) == 0 |
252b5132 RH |
9150 | && (offset_expr.X_op != O_constant |
9151 | || offset_expr.X_add_number >= 0x8000 | |
afdbd6d0 | 9152 | || offset_expr.X_add_number < -0x8000)) |
252b5132 RH |
9153 | break; |
9154 | ||
252b5132 RH |
9155 | s = expr_end; |
9156 | continue; | |
9157 | ||
9158 | case 'p': /* pc relative offset */ | |
0b25d3e6 | 9159 | *offset_reloc = BFD_RELOC_16_PCREL_S2; |
252b5132 RH |
9160 | my_getExpression (&offset_expr, s); |
9161 | s = expr_end; | |
9162 | continue; | |
9163 | ||
9164 | case 'u': /* upper 16 bits */ | |
5e0116d5 RS |
9165 | if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0 |
9166 | && imm_expr.X_op == O_constant | |
9167 | && (imm_expr.X_add_number < 0 | |
9168 | || imm_expr.X_add_number >= 0x10000)) | |
252b5132 RH |
9169 | as_bad (_("lui expression not in range 0..65535")); |
9170 | s = expr_end; | |
9171 | continue; | |
9172 | ||
9173 | case 'a': /* 26 bit address */ | |
9174 | my_getExpression (&offset_expr, s); | |
9175 | s = expr_end; | |
f6688943 | 9176 | *offset_reloc = BFD_RELOC_MIPS_JMP; |
252b5132 RH |
9177 | continue; |
9178 | ||
9179 | case 'N': /* 3 bit branch condition code */ | |
9180 | case 'M': /* 3 bit compare condition code */ | |
9181 | if (strncmp (s, "$fcc", 4) != 0) | |
9182 | break; | |
9183 | s += 4; | |
9184 | regno = 0; | |
9185 | do | |
9186 | { | |
9187 | regno *= 10; | |
9188 | regno += *s - '0'; | |
9189 | ++s; | |
9190 | } | |
3882b010 | 9191 | while (ISDIGIT (*s)); |
252b5132 | 9192 | if (regno > 7) |
30c378fd CD |
9193 | as_bad (_("Invalid condition code register $fcc%d"), regno); |
9194 | if ((strcmp(str + strlen(str) - 3, ".ps") == 0 | |
9195 | || strcmp(str + strlen(str) - 5, "any2f") == 0 | |
9196 | || strcmp(str + strlen(str) - 5, "any2t") == 0) | |
9197 | && (regno & 1) != 0) | |
9198 | as_warn(_("Condition code register should be even for %s, was %d"), | |
9199 | str, regno); | |
9200 | if ((strcmp(str + strlen(str) - 5, "any4f") == 0 | |
9201 | || strcmp(str + strlen(str) - 5, "any4t") == 0) | |
9202 | && (regno & 3) != 0) | |
9203 | as_warn(_("Condition code register should be 0 or 4 for %s, was %d"), | |
9204 | str, regno); | |
252b5132 | 9205 | if (*args == 'N') |
bf12938e | 9206 | INSERT_OPERAND (BCC, *ip, regno); |
252b5132 | 9207 | else |
bf12938e | 9208 | INSERT_OPERAND (CCC, *ip, regno); |
beae10d5 | 9209 | continue; |
252b5132 | 9210 | |
156c2f8b NC |
9211 | case 'H': |
9212 | if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X')) | |
9213 | s += 2; | |
3882b010 | 9214 | if (ISDIGIT (*s)) |
156c2f8b NC |
9215 | { |
9216 | c = 0; | |
9217 | do | |
9218 | { | |
9219 | c *= 10; | |
9220 | c += *s - '0'; | |
9221 | ++s; | |
9222 | } | |
3882b010 | 9223 | while (ISDIGIT (*s)); |
156c2f8b NC |
9224 | } |
9225 | else | |
9226 | c = 8; /* Invalid sel value. */ | |
9227 | ||
9228 | if (c > 7) | |
9229 | as_bad (_("invalid coprocessor sub-selection value (0-7)")); | |
9230 | ip->insn_opcode |= c; | |
9231 | continue; | |
9232 | ||
60b63b72 RS |
9233 | case 'e': |
9234 | /* Must be at least one digit. */ | |
9235 | my_getExpression (&imm_expr, s); | |
9236 | check_absolute_expr (ip, &imm_expr); | |
9237 | ||
9238 | if ((unsigned long) imm_expr.X_add_number | |
9239 | > (unsigned long) OP_MASK_VECBYTE) | |
9240 | { | |
9241 | as_bad (_("bad byte vector index (%ld)"), | |
9242 | (long) imm_expr.X_add_number); | |
9243 | imm_expr.X_add_number = 0; | |
9244 | } | |
9245 | ||
bf12938e | 9246 | INSERT_OPERAND (VECBYTE, *ip, imm_expr.X_add_number); |
60b63b72 RS |
9247 | imm_expr.X_op = O_absent; |
9248 | s = expr_end; | |
9249 | continue; | |
9250 | ||
9251 | case '%': | |
9252 | my_getExpression (&imm_expr, s); | |
9253 | check_absolute_expr (ip, &imm_expr); | |
9254 | ||
9255 | if ((unsigned long) imm_expr.X_add_number | |
9256 | > (unsigned long) OP_MASK_VECALIGN) | |
9257 | { | |
9258 | as_bad (_("bad byte vector index (%ld)"), | |
9259 | (long) imm_expr.X_add_number); | |
9260 | imm_expr.X_add_number = 0; | |
9261 | } | |
9262 | ||
bf12938e | 9263 | INSERT_OPERAND (VECALIGN, *ip, imm_expr.X_add_number); |
60b63b72 RS |
9264 | imm_expr.X_op = O_absent; |
9265 | s = expr_end; | |
9266 | continue; | |
9267 | ||
252b5132 RH |
9268 | default: |
9269 | as_bad (_("bad char = '%c'\n"), *args); | |
9270 | internalError (); | |
9271 | } | |
9272 | break; | |
9273 | } | |
9274 | /* Args don't match. */ | |
9275 | if (insn + 1 < &mips_opcodes[NUMOPCODES] && | |
9276 | !strcmp (insn->name, insn[1].name)) | |
9277 | { | |
9278 | ++insn; | |
9279 | s = argsStart; | |
268f6bed | 9280 | insn_error = _("illegal operands"); |
252b5132 RH |
9281 | continue; |
9282 | } | |
268f6bed L |
9283 | if (save_c) |
9284 | *(--s) = save_c; | |
252b5132 RH |
9285 | insn_error = _("illegal operands"); |
9286 | return; | |
9287 | } | |
9288 | } | |
9289 | ||
9290 | /* This routine assembles an instruction into its binary format when | |
9291 | assembling for the mips16. As a side effect, it sets one of the | |
9292 | global variables imm_reloc or offset_reloc to the type of | |
9293 | relocation to do if one of the operands is an address expression. | |
9294 | It also sets mips16_small and mips16_ext if the user explicitly | |
9295 | requested a small or extended instruction. */ | |
9296 | ||
9297 | static void | |
17a2f251 | 9298 | mips16_ip (char *str, struct mips_cl_insn *ip) |
252b5132 RH |
9299 | { |
9300 | char *s; | |
9301 | const char *args; | |
9302 | struct mips_opcode *insn; | |
9303 | char *argsstart; | |
9304 | unsigned int regno; | |
9305 | unsigned int lastregno = 0; | |
9306 | char *s_reset; | |
d6f16593 | 9307 | size_t i; |
252b5132 RH |
9308 | |
9309 | insn_error = NULL; | |
9310 | ||
b34976b6 AM |
9311 | mips16_small = FALSE; |
9312 | mips16_ext = FALSE; | |
252b5132 | 9313 | |
3882b010 | 9314 | for (s = str; ISLOWER (*s); ++s) |
252b5132 RH |
9315 | ; |
9316 | switch (*s) | |
9317 | { | |
9318 | case '\0': | |
9319 | break; | |
9320 | ||
9321 | case ' ': | |
9322 | *s++ = '\0'; | |
9323 | break; | |
9324 | ||
9325 | case '.': | |
9326 | if (s[1] == 't' && s[2] == ' ') | |
9327 | { | |
9328 | *s = '\0'; | |
b34976b6 | 9329 | mips16_small = TRUE; |
252b5132 RH |
9330 | s += 3; |
9331 | break; | |
9332 | } | |
9333 | else if (s[1] == 'e' && s[2] == ' ') | |
9334 | { | |
9335 | *s = '\0'; | |
b34976b6 | 9336 | mips16_ext = TRUE; |
252b5132 RH |
9337 | s += 3; |
9338 | break; | |
9339 | } | |
9340 | /* Fall through. */ | |
9341 | default: | |
9342 | insn_error = _("unknown opcode"); | |
9343 | return; | |
9344 | } | |
9345 | ||
9346 | if (mips_opts.noautoextend && ! mips16_ext) | |
b34976b6 | 9347 | mips16_small = TRUE; |
252b5132 RH |
9348 | |
9349 | if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL) | |
9350 | { | |
9351 | insn_error = _("unrecognized opcode"); | |
9352 | return; | |
9353 | } | |
9354 | ||
9355 | argsstart = s; | |
9356 | for (;;) | |
9357 | { | |
9358 | assert (strcmp (insn->name, str) == 0); | |
9359 | ||
1e915849 | 9360 | create_insn (ip, insn); |
252b5132 | 9361 | imm_expr.X_op = O_absent; |
f6688943 TS |
9362 | imm_reloc[0] = BFD_RELOC_UNUSED; |
9363 | imm_reloc[1] = BFD_RELOC_UNUSED; | |
9364 | imm_reloc[2] = BFD_RELOC_UNUSED; | |
5f74bc13 | 9365 | imm2_expr.X_op = O_absent; |
252b5132 | 9366 | offset_expr.X_op = O_absent; |
f6688943 TS |
9367 | offset_reloc[0] = BFD_RELOC_UNUSED; |
9368 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
9369 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
9370 | for (args = insn->args; 1; ++args) |
9371 | { | |
9372 | int c; | |
9373 | ||
9374 | if (*s == ' ') | |
9375 | ++s; | |
9376 | ||
9377 | /* In this switch statement we call break if we did not find | |
9378 | a match, continue if we did find a match, or return if we | |
9379 | are done. */ | |
9380 | ||
9381 | c = *args; | |
9382 | switch (c) | |
9383 | { | |
9384 | case '\0': | |
9385 | if (*s == '\0') | |
9386 | { | |
9387 | /* Stuff the immediate value in now, if we can. */ | |
9388 | if (imm_expr.X_op == O_constant | |
f6688943 | 9389 | && *imm_reloc > BFD_RELOC_UNUSED |
252b5132 RH |
9390 | && insn->pinfo != INSN_MACRO) |
9391 | { | |
d6f16593 MR |
9392 | valueT tmp; |
9393 | ||
9394 | switch (*offset_reloc) | |
9395 | { | |
9396 | case BFD_RELOC_MIPS16_HI16_S: | |
9397 | tmp = (imm_expr.X_add_number + 0x8000) >> 16; | |
9398 | break; | |
9399 | ||
9400 | case BFD_RELOC_MIPS16_HI16: | |
9401 | tmp = imm_expr.X_add_number >> 16; | |
9402 | break; | |
9403 | ||
9404 | case BFD_RELOC_MIPS16_LO16: | |
9405 | tmp = ((imm_expr.X_add_number + 0x8000) & 0xffff) | |
9406 | - 0x8000; | |
9407 | break; | |
9408 | ||
9409 | case BFD_RELOC_UNUSED: | |
9410 | tmp = imm_expr.X_add_number; | |
9411 | break; | |
9412 | ||
9413 | default: | |
9414 | internalError (); | |
9415 | } | |
9416 | *offset_reloc = BFD_RELOC_UNUSED; | |
9417 | ||
c4e7957c | 9418 | mips16_immed (NULL, 0, *imm_reloc - BFD_RELOC_UNUSED, |
d6f16593 | 9419 | tmp, TRUE, mips16_small, |
252b5132 RH |
9420 | mips16_ext, &ip->insn_opcode, |
9421 | &ip->use_extend, &ip->extend); | |
9422 | imm_expr.X_op = O_absent; | |
f6688943 | 9423 | *imm_reloc = BFD_RELOC_UNUSED; |
252b5132 RH |
9424 | } |
9425 | ||
9426 | return; | |
9427 | } | |
9428 | break; | |
9429 | ||
9430 | case ',': | |
9431 | if (*s++ == c) | |
9432 | continue; | |
9433 | s--; | |
9434 | switch (*++args) | |
9435 | { | |
9436 | case 'v': | |
bf12938e | 9437 | MIPS16_INSERT_OPERAND (RX, *ip, lastregno); |
252b5132 RH |
9438 | continue; |
9439 | case 'w': | |
bf12938e | 9440 | MIPS16_INSERT_OPERAND (RY, *ip, lastregno); |
252b5132 RH |
9441 | continue; |
9442 | } | |
9443 | break; | |
9444 | ||
9445 | case '(': | |
9446 | case ')': | |
9447 | if (*s++ == c) | |
9448 | continue; | |
9449 | break; | |
9450 | ||
9451 | case 'v': | |
9452 | case 'w': | |
9453 | if (s[0] != '$') | |
9454 | { | |
9455 | if (c == 'v') | |
bf12938e | 9456 | MIPS16_INSERT_OPERAND (RX, *ip, lastregno); |
252b5132 | 9457 | else |
bf12938e | 9458 | MIPS16_INSERT_OPERAND (RY, *ip, lastregno); |
252b5132 RH |
9459 | ++args; |
9460 | continue; | |
9461 | } | |
9462 | /* Fall through. */ | |
9463 | case 'x': | |
9464 | case 'y': | |
9465 | case 'z': | |
9466 | case 'Z': | |
9467 | case '0': | |
9468 | case 'S': | |
9469 | case 'R': | |
9470 | case 'X': | |
9471 | case 'Y': | |
9472 | if (s[0] != '$') | |
9473 | break; | |
9474 | s_reset = s; | |
3882b010 | 9475 | if (ISDIGIT (s[1])) |
252b5132 RH |
9476 | { |
9477 | ++s; | |
9478 | regno = 0; | |
9479 | do | |
9480 | { | |
9481 | regno *= 10; | |
9482 | regno += *s - '0'; | |
9483 | ++s; | |
9484 | } | |
3882b010 | 9485 | while (ISDIGIT (*s)); |
252b5132 RH |
9486 | if (regno > 31) |
9487 | { | |
9488 | as_bad (_("invalid register number (%d)"), regno); | |
9489 | regno = 2; | |
9490 | } | |
9491 | } | |
9492 | else | |
9493 | { | |
76db943d TS |
9494 | if (s[1] == 'r' && s[2] == 'a') |
9495 | { | |
9496 | s += 3; | |
9497 | regno = RA; | |
9498 | } | |
9499 | else if (s[1] == 'f' && s[2] == 'p') | |
252b5132 RH |
9500 | { |
9501 | s += 3; | |
9502 | regno = FP; | |
9503 | } | |
9504 | else if (s[1] == 's' && s[2] == 'p') | |
9505 | { | |
9506 | s += 3; | |
9507 | regno = SP; | |
9508 | } | |
9509 | else if (s[1] == 'g' && s[2] == 'p') | |
9510 | { | |
9511 | s += 3; | |
9512 | regno = GP; | |
9513 | } | |
9514 | else if (s[1] == 'a' && s[2] == 't') | |
9515 | { | |
9516 | s += 3; | |
9517 | regno = AT; | |
9518 | } | |
9519 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '0') | |
9520 | { | |
9521 | s += 4; | |
9522 | regno = KT0; | |
9523 | } | |
9524 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '1') | |
9525 | { | |
9526 | s += 4; | |
9527 | regno = KT1; | |
9528 | } | |
85b51719 TS |
9529 | else if (s[1] == 'z' && s[2] == 'e' && s[3] == 'r' && s[4] == 'o') |
9530 | { | |
9531 | s += 5; | |
9532 | regno = ZERO; | |
9533 | } | |
252b5132 RH |
9534 | else |
9535 | break; | |
9536 | } | |
9537 | ||
9538 | if (*s == ' ') | |
9539 | ++s; | |
9540 | if (args[1] != *s) | |
9541 | { | |
9542 | if (c == 'v' || c == 'w') | |
9543 | { | |
9544 | regno = mips16_to_32_reg_map[lastregno]; | |
9545 | s = s_reset; | |
f9419b05 | 9546 | ++args; |
252b5132 RH |
9547 | } |
9548 | } | |
9549 | ||
9550 | switch (c) | |
9551 | { | |
9552 | case 'x': | |
9553 | case 'y': | |
9554 | case 'z': | |
9555 | case 'v': | |
9556 | case 'w': | |
9557 | case 'Z': | |
9558 | regno = mips32_to_16_reg_map[regno]; | |
9559 | break; | |
9560 | ||
9561 | case '0': | |
9562 | if (regno != 0) | |
9563 | regno = ILLEGAL_REG; | |
9564 | break; | |
9565 | ||
9566 | case 'S': | |
9567 | if (regno != SP) | |
9568 | regno = ILLEGAL_REG; | |
9569 | break; | |
9570 | ||
9571 | case 'R': | |
9572 | if (regno != RA) | |
9573 | regno = ILLEGAL_REG; | |
9574 | break; | |
9575 | ||
9576 | case 'X': | |
9577 | case 'Y': | |
9578 | if (regno == AT && ! mips_opts.noat) | |
9579 | as_warn (_("used $at without \".set noat\"")); | |
9580 | break; | |
9581 | ||
9582 | default: | |
9583 | internalError (); | |
9584 | } | |
9585 | ||
9586 | if (regno == ILLEGAL_REG) | |
9587 | break; | |
9588 | ||
9589 | switch (c) | |
9590 | { | |
9591 | case 'x': | |
9592 | case 'v': | |
bf12938e | 9593 | MIPS16_INSERT_OPERAND (RX, *ip, regno); |
252b5132 RH |
9594 | break; |
9595 | case 'y': | |
9596 | case 'w': | |
bf12938e | 9597 | MIPS16_INSERT_OPERAND (RY, *ip, regno); |
252b5132 RH |
9598 | break; |
9599 | case 'z': | |
bf12938e | 9600 | MIPS16_INSERT_OPERAND (RZ, *ip, regno); |
252b5132 RH |
9601 | break; |
9602 | case 'Z': | |
bf12938e | 9603 | MIPS16_INSERT_OPERAND (MOVE32Z, *ip, regno); |
252b5132 RH |
9604 | case '0': |
9605 | case 'S': | |
9606 | case 'R': | |
9607 | break; | |
9608 | case 'X': | |
bf12938e | 9609 | MIPS16_INSERT_OPERAND (REGR32, *ip, regno); |
252b5132 RH |
9610 | break; |
9611 | case 'Y': | |
9612 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); | |
bf12938e | 9613 | MIPS16_INSERT_OPERAND (REG32R, *ip, regno); |
252b5132 RH |
9614 | break; |
9615 | default: | |
9616 | internalError (); | |
9617 | } | |
9618 | ||
9619 | lastregno = regno; | |
9620 | continue; | |
9621 | ||
9622 | case 'P': | |
9623 | if (strncmp (s, "$pc", 3) == 0) | |
9624 | { | |
9625 | s += 3; | |
9626 | continue; | |
9627 | } | |
9628 | break; | |
9629 | ||
252b5132 RH |
9630 | case '5': |
9631 | case 'H': | |
9632 | case 'W': | |
9633 | case 'D': | |
9634 | case 'j': | |
252b5132 RH |
9635 | case 'V': |
9636 | case 'C': | |
9637 | case 'U': | |
9638 | case 'k': | |
9639 | case 'K': | |
d6f16593 MR |
9640 | i = my_getSmallExpression (&imm_expr, imm_reloc, s); |
9641 | if (i > 0) | |
252b5132 | 9642 | { |
d6f16593 | 9643 | if (imm_expr.X_op != O_constant) |
252b5132 | 9644 | { |
b34976b6 | 9645 | mips16_ext = TRUE; |
b34976b6 | 9646 | ip->use_extend = TRUE; |
252b5132 | 9647 | ip->extend = 0; |
252b5132 | 9648 | } |
d6f16593 MR |
9649 | else |
9650 | { | |
9651 | /* We need to relax this instruction. */ | |
9652 | *offset_reloc = *imm_reloc; | |
9653 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; | |
9654 | } | |
9655 | s = expr_end; | |
9656 | continue; | |
252b5132 | 9657 | } |
d6f16593 MR |
9658 | *imm_reloc = BFD_RELOC_UNUSED; |
9659 | /* Fall through. */ | |
9660 | case '<': | |
9661 | case '>': | |
9662 | case '[': | |
9663 | case ']': | |
9664 | case '4': | |
9665 | case '8': | |
9666 | my_getExpression (&imm_expr, s); | |
252b5132 RH |
9667 | if (imm_expr.X_op == O_register) |
9668 | { | |
9669 | /* What we thought was an expression turned out to | |
9670 | be a register. */ | |
9671 | ||
9672 | if (s[0] == '(' && args[1] == '(') | |
9673 | { | |
9674 | /* It looks like the expression was omitted | |
9675 | before a register indirection, which means | |
9676 | that the expression is implicitly zero. We | |
9677 | still set up imm_expr, so that we handle | |
9678 | explicit extensions correctly. */ | |
9679 | imm_expr.X_op = O_constant; | |
9680 | imm_expr.X_add_number = 0; | |
f6688943 | 9681 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
9682 | continue; |
9683 | } | |
9684 | ||
9685 | break; | |
9686 | } | |
9687 | ||
9688 | /* We need to relax this instruction. */ | |
f6688943 | 9689 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
9690 | s = expr_end; |
9691 | continue; | |
9692 | ||
9693 | case 'p': | |
9694 | case 'q': | |
9695 | case 'A': | |
9696 | case 'B': | |
9697 | case 'E': | |
9698 | /* We use offset_reloc rather than imm_reloc for the PC | |
9699 | relative operands. This lets macros with both | |
9700 | immediate and address operands work correctly. */ | |
9701 | my_getExpression (&offset_expr, s); | |
9702 | ||
9703 | if (offset_expr.X_op == O_register) | |
9704 | break; | |
9705 | ||
9706 | /* We need to relax this instruction. */ | |
f6688943 | 9707 | *offset_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
9708 | s = expr_end; |
9709 | continue; | |
9710 | ||
9711 | case '6': /* break code */ | |
9712 | my_getExpression (&imm_expr, s); | |
9713 | check_absolute_expr (ip, &imm_expr); | |
9714 | if ((unsigned long) imm_expr.X_add_number > 63) | |
bf12938e RS |
9715 | as_warn (_("Invalid value for `%s' (%lu)"), |
9716 | ip->insn_mo->name, | |
9717 | (unsigned long) imm_expr.X_add_number); | |
9718 | MIPS16_INSERT_OPERAND (IMM6, *ip, imm_expr.X_add_number); | |
252b5132 RH |
9719 | imm_expr.X_op = O_absent; |
9720 | s = expr_end; | |
9721 | continue; | |
9722 | ||
9723 | case 'a': /* 26 bit address */ | |
9724 | my_getExpression (&offset_expr, s); | |
9725 | s = expr_end; | |
f6688943 | 9726 | *offset_reloc = BFD_RELOC_MIPS16_JMP; |
252b5132 RH |
9727 | ip->insn_opcode <<= 16; |
9728 | continue; | |
9729 | ||
9730 | case 'l': /* register list for entry macro */ | |
9731 | case 'L': /* register list for exit macro */ | |
9732 | { | |
9733 | int mask; | |
9734 | ||
9735 | if (c == 'l') | |
9736 | mask = 0; | |
9737 | else | |
9738 | mask = 7 << 3; | |
9739 | while (*s != '\0') | |
9740 | { | |
9741 | int freg, reg1, reg2; | |
9742 | ||
9743 | while (*s == ' ' || *s == ',') | |
9744 | ++s; | |
9745 | if (*s != '$') | |
9746 | { | |
9747 | as_bad (_("can't parse register list")); | |
9748 | break; | |
9749 | } | |
9750 | ++s; | |
9751 | if (*s != 'f') | |
9752 | freg = 0; | |
9753 | else | |
9754 | { | |
9755 | freg = 1; | |
9756 | ++s; | |
9757 | } | |
9758 | reg1 = 0; | |
3882b010 | 9759 | while (ISDIGIT (*s)) |
252b5132 RH |
9760 | { |
9761 | reg1 *= 10; | |
9762 | reg1 += *s - '0'; | |
9763 | ++s; | |
9764 | } | |
9765 | if (*s == ' ') | |
9766 | ++s; | |
9767 | if (*s != '-') | |
9768 | reg2 = reg1; | |
9769 | else | |
9770 | { | |
9771 | ++s; | |
9772 | if (*s != '$') | |
9773 | break; | |
9774 | ++s; | |
9775 | if (freg) | |
9776 | { | |
9777 | if (*s == 'f') | |
9778 | ++s; | |
9779 | else | |
9780 | { | |
9781 | as_bad (_("invalid register list")); | |
9782 | break; | |
9783 | } | |
9784 | } | |
9785 | reg2 = 0; | |
3882b010 | 9786 | while (ISDIGIT (*s)) |
252b5132 RH |
9787 | { |
9788 | reg2 *= 10; | |
9789 | reg2 += *s - '0'; | |
9790 | ++s; | |
9791 | } | |
9792 | } | |
9793 | if (freg && reg1 == 0 && reg2 == 0 && c == 'L') | |
9794 | { | |
9795 | mask &= ~ (7 << 3); | |
9796 | mask |= 5 << 3; | |
9797 | } | |
9798 | else if (freg && reg1 == 0 && reg2 == 1 && c == 'L') | |
9799 | { | |
9800 | mask &= ~ (7 << 3); | |
9801 | mask |= 6 << 3; | |
9802 | } | |
9803 | else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L') | |
9804 | mask |= (reg2 - 3) << 3; | |
9805 | else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17) | |
9806 | mask |= (reg2 - 15) << 1; | |
f9419b05 | 9807 | else if (reg1 == RA && reg2 == RA) |
252b5132 RH |
9808 | mask |= 1; |
9809 | else | |
9810 | { | |
9811 | as_bad (_("invalid register list")); | |
9812 | break; | |
9813 | } | |
9814 | } | |
9815 | /* The mask is filled in in the opcode table for the | |
9816 | benefit of the disassembler. We remove it before | |
9817 | applying the actual mask. */ | |
9818 | ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6); | |
9819 | ip->insn_opcode |= mask << MIPS16OP_SH_IMM6; | |
9820 | } | |
9821 | continue; | |
9822 | ||
9823 | case 'e': /* extend code */ | |
9824 | my_getExpression (&imm_expr, s); | |
9825 | check_absolute_expr (ip, &imm_expr); | |
9826 | if ((unsigned long) imm_expr.X_add_number > 0x7ff) | |
9827 | { | |
9828 | as_warn (_("Invalid value for `%s' (%lu)"), | |
9829 | ip->insn_mo->name, | |
9830 | (unsigned long) imm_expr.X_add_number); | |
9831 | imm_expr.X_add_number &= 0x7ff; | |
9832 | } | |
9833 | ip->insn_opcode |= imm_expr.X_add_number; | |
9834 | imm_expr.X_op = O_absent; | |
9835 | s = expr_end; | |
9836 | continue; | |
9837 | ||
9838 | default: | |
9839 | internalError (); | |
9840 | } | |
9841 | break; | |
9842 | } | |
9843 | ||
9844 | /* Args don't match. */ | |
9845 | if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] && | |
9846 | strcmp (insn->name, insn[1].name) == 0) | |
9847 | { | |
9848 | ++insn; | |
9849 | s = argsstart; | |
9850 | continue; | |
9851 | } | |
9852 | ||
9853 | insn_error = _("illegal operands"); | |
9854 | ||
9855 | return; | |
9856 | } | |
9857 | } | |
9858 | ||
9859 | /* This structure holds information we know about a mips16 immediate | |
9860 | argument type. */ | |
9861 | ||
e972090a NC |
9862 | struct mips16_immed_operand |
9863 | { | |
252b5132 RH |
9864 | /* The type code used in the argument string in the opcode table. */ |
9865 | int type; | |
9866 | /* The number of bits in the short form of the opcode. */ | |
9867 | int nbits; | |
9868 | /* The number of bits in the extended form of the opcode. */ | |
9869 | int extbits; | |
9870 | /* The amount by which the short form is shifted when it is used; | |
9871 | for example, the sw instruction has a shift count of 2. */ | |
9872 | int shift; | |
9873 | /* The amount by which the short form is shifted when it is stored | |
9874 | into the instruction code. */ | |
9875 | int op_shift; | |
9876 | /* Non-zero if the short form is unsigned. */ | |
9877 | int unsp; | |
9878 | /* Non-zero if the extended form is unsigned. */ | |
9879 | int extu; | |
9880 | /* Non-zero if the value is PC relative. */ | |
9881 | int pcrel; | |
9882 | }; | |
9883 | ||
9884 | /* The mips16 immediate operand types. */ | |
9885 | ||
9886 | static const struct mips16_immed_operand mips16_immed_operands[] = | |
9887 | { | |
9888 | { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
9889 | { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
9890 | { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
9891 | { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
9892 | { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 }, | |
9893 | { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
9894 | { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
9895 | { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
9896 | { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
9897 | { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 }, | |
9898 | { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
9899 | { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
9900 | { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
9901 | { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 }, | |
9902 | { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
9903 | { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
9904 | { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
9905 | { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
9906 | { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 }, | |
9907 | { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 }, | |
9908 | { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 } | |
9909 | }; | |
9910 | ||
9911 | #define MIPS16_NUM_IMMED \ | |
9912 | (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0]) | |
9913 | ||
9914 | /* Handle a mips16 instruction with an immediate value. This or's the | |
9915 | small immediate value into *INSN. It sets *USE_EXTEND to indicate | |
9916 | whether an extended value is needed; if one is needed, it sets | |
9917 | *EXTEND to the value. The argument type is TYPE. The value is VAL. | |
9918 | If SMALL is true, an unextended opcode was explicitly requested. | |
9919 | If EXT is true, an extended opcode was explicitly requested. If | |
9920 | WARN is true, warn if EXT does not match reality. */ | |
9921 | ||
9922 | static void | |
17a2f251 TS |
9923 | mips16_immed (char *file, unsigned int line, int type, offsetT val, |
9924 | bfd_boolean warn, bfd_boolean small, bfd_boolean ext, | |
9925 | unsigned long *insn, bfd_boolean *use_extend, | |
9926 | unsigned short *extend) | |
252b5132 RH |
9927 | { |
9928 | register const struct mips16_immed_operand *op; | |
9929 | int mintiny, maxtiny; | |
b34976b6 | 9930 | bfd_boolean needext; |
252b5132 RH |
9931 | |
9932 | op = mips16_immed_operands; | |
9933 | while (op->type != type) | |
9934 | { | |
9935 | ++op; | |
9936 | assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); | |
9937 | } | |
9938 | ||
9939 | if (op->unsp) | |
9940 | { | |
9941 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
9942 | { | |
9943 | mintiny = 1; | |
9944 | maxtiny = 1 << op->nbits; | |
9945 | } | |
9946 | else | |
9947 | { | |
9948 | mintiny = 0; | |
9949 | maxtiny = (1 << op->nbits) - 1; | |
9950 | } | |
9951 | } | |
9952 | else | |
9953 | { | |
9954 | mintiny = - (1 << (op->nbits - 1)); | |
9955 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
9956 | } | |
9957 | ||
9958 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
9959 | if (type == 'p' || type == 'q') | |
9960 | val /= 2; | |
9961 | ||
9962 | if ((val & ((1 << op->shift) - 1)) != 0 | |
9963 | || val < (mintiny << op->shift) | |
9964 | || val > (maxtiny << op->shift)) | |
b34976b6 | 9965 | needext = TRUE; |
252b5132 | 9966 | else |
b34976b6 | 9967 | needext = FALSE; |
252b5132 RH |
9968 | |
9969 | if (warn && ext && ! needext) | |
beae10d5 KH |
9970 | as_warn_where (file, line, |
9971 | _("extended operand requested but not required")); | |
252b5132 RH |
9972 | if (small && needext) |
9973 | as_bad_where (file, line, _("invalid unextended operand value")); | |
9974 | ||
9975 | if (small || (! ext && ! needext)) | |
9976 | { | |
9977 | int insnval; | |
9978 | ||
b34976b6 | 9979 | *use_extend = FALSE; |
252b5132 RH |
9980 | insnval = ((val >> op->shift) & ((1 << op->nbits) - 1)); |
9981 | insnval <<= op->op_shift; | |
9982 | *insn |= insnval; | |
9983 | } | |
9984 | else | |
9985 | { | |
9986 | long minext, maxext; | |
9987 | int extval; | |
9988 | ||
9989 | if (op->extu) | |
9990 | { | |
9991 | minext = 0; | |
9992 | maxext = (1 << op->extbits) - 1; | |
9993 | } | |
9994 | else | |
9995 | { | |
9996 | minext = - (1 << (op->extbits - 1)); | |
9997 | maxext = (1 << (op->extbits - 1)) - 1; | |
9998 | } | |
9999 | if (val < minext || val > maxext) | |
10000 | as_bad_where (file, line, | |
10001 | _("operand value out of range for instruction")); | |
10002 | ||
b34976b6 | 10003 | *use_extend = TRUE; |
252b5132 RH |
10004 | if (op->extbits == 16) |
10005 | { | |
10006 | extval = ((val >> 11) & 0x1f) | (val & 0x7e0); | |
10007 | val &= 0x1f; | |
10008 | } | |
10009 | else if (op->extbits == 15) | |
10010 | { | |
10011 | extval = ((val >> 11) & 0xf) | (val & 0x7f0); | |
10012 | val &= 0xf; | |
10013 | } | |
10014 | else | |
10015 | { | |
10016 | extval = ((val & 0x1f) << 6) | (val & 0x20); | |
10017 | val = 0; | |
10018 | } | |
10019 | ||
10020 | *extend = (unsigned short) extval; | |
10021 | *insn |= val; | |
10022 | } | |
10023 | } | |
10024 | \f | |
d6f16593 | 10025 | struct percent_op_match |
ad8d3bb3 | 10026 | { |
5e0116d5 RS |
10027 | const char *str; |
10028 | bfd_reloc_code_real_type reloc; | |
d6f16593 MR |
10029 | }; |
10030 | ||
10031 | static const struct percent_op_match mips_percent_op[] = | |
ad8d3bb3 | 10032 | { |
5e0116d5 | 10033 | {"%lo", BFD_RELOC_LO16}, |
ad8d3bb3 | 10034 | #ifdef OBJ_ELF |
5e0116d5 RS |
10035 | {"%call_hi", BFD_RELOC_MIPS_CALL_HI16}, |
10036 | {"%call_lo", BFD_RELOC_MIPS_CALL_LO16}, | |
10037 | {"%call16", BFD_RELOC_MIPS_CALL16}, | |
10038 | {"%got_disp", BFD_RELOC_MIPS_GOT_DISP}, | |
10039 | {"%got_page", BFD_RELOC_MIPS_GOT_PAGE}, | |
10040 | {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST}, | |
10041 | {"%got_hi", BFD_RELOC_MIPS_GOT_HI16}, | |
10042 | {"%got_lo", BFD_RELOC_MIPS_GOT_LO16}, | |
10043 | {"%got", BFD_RELOC_MIPS_GOT16}, | |
10044 | {"%gp_rel", BFD_RELOC_GPREL16}, | |
10045 | {"%half", BFD_RELOC_16}, | |
10046 | {"%highest", BFD_RELOC_MIPS_HIGHEST}, | |
10047 | {"%higher", BFD_RELOC_MIPS_HIGHER}, | |
10048 | {"%neg", BFD_RELOC_MIPS_SUB}, | |
3f98094e DJ |
10049 | {"%tlsgd", BFD_RELOC_MIPS_TLS_GD}, |
10050 | {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM}, | |
10051 | {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16}, | |
10052 | {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16}, | |
10053 | {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16}, | |
10054 | {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16}, | |
10055 | {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL}, | |
ad8d3bb3 | 10056 | #endif |
5e0116d5 | 10057 | {"%hi", BFD_RELOC_HI16_S} |
ad8d3bb3 TS |
10058 | }; |
10059 | ||
d6f16593 MR |
10060 | static const struct percent_op_match mips16_percent_op[] = |
10061 | { | |
10062 | {"%lo", BFD_RELOC_MIPS16_LO16}, | |
10063 | {"%gprel", BFD_RELOC_MIPS16_GPREL}, | |
10064 | {"%hi", BFD_RELOC_MIPS16_HI16_S} | |
10065 | }; | |
10066 | ||
252b5132 | 10067 | |
5e0116d5 RS |
10068 | /* Return true if *STR points to a relocation operator. When returning true, |
10069 | move *STR over the operator and store its relocation code in *RELOC. | |
10070 | Leave both *STR and *RELOC alone when returning false. */ | |
10071 | ||
10072 | static bfd_boolean | |
17a2f251 | 10073 | parse_relocation (char **str, bfd_reloc_code_real_type *reloc) |
252b5132 | 10074 | { |
d6f16593 MR |
10075 | const struct percent_op_match *percent_op; |
10076 | size_t limit, i; | |
10077 | ||
10078 | if (mips_opts.mips16) | |
10079 | { | |
10080 | percent_op = mips16_percent_op; | |
10081 | limit = ARRAY_SIZE (mips16_percent_op); | |
10082 | } | |
10083 | else | |
10084 | { | |
10085 | percent_op = mips_percent_op; | |
10086 | limit = ARRAY_SIZE (mips_percent_op); | |
10087 | } | |
76b3015f | 10088 | |
d6f16593 | 10089 | for (i = 0; i < limit; i++) |
5e0116d5 | 10090 | if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0) |
394f9b3a | 10091 | { |
3f98094e DJ |
10092 | int len = strlen (percent_op[i].str); |
10093 | ||
10094 | if (!ISSPACE ((*str)[len]) && (*str)[len] != '(') | |
10095 | continue; | |
10096 | ||
5e0116d5 RS |
10097 | *str += strlen (percent_op[i].str); |
10098 | *reloc = percent_op[i].reloc; | |
394f9b3a | 10099 | |
5e0116d5 RS |
10100 | /* Check whether the output BFD supports this relocation. |
10101 | If not, issue an error and fall back on something safe. */ | |
10102 | if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc)) | |
394f9b3a | 10103 | { |
5e0116d5 RS |
10104 | as_bad ("relocation %s isn't supported by the current ABI", |
10105 | percent_op[i].str); | |
01a3f561 | 10106 | *reloc = BFD_RELOC_UNUSED; |
394f9b3a | 10107 | } |
5e0116d5 | 10108 | return TRUE; |
394f9b3a | 10109 | } |
5e0116d5 | 10110 | return FALSE; |
394f9b3a | 10111 | } |
ad8d3bb3 | 10112 | |
ad8d3bb3 | 10113 | |
5e0116d5 RS |
10114 | /* Parse string STR as a 16-bit relocatable operand. Store the |
10115 | expression in *EP and the relocations in the array starting | |
10116 | at RELOC. Return the number of relocation operators used. | |
ad8d3bb3 | 10117 | |
01a3f561 | 10118 | On exit, EXPR_END points to the first character after the expression. */ |
ad8d3bb3 | 10119 | |
5e0116d5 | 10120 | static size_t |
17a2f251 TS |
10121 | my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc, |
10122 | char *str) | |
ad8d3bb3 | 10123 | { |
5e0116d5 RS |
10124 | bfd_reloc_code_real_type reversed_reloc[3]; |
10125 | size_t reloc_index, i; | |
09b8f35a RS |
10126 | int crux_depth, str_depth; |
10127 | char *crux; | |
5e0116d5 RS |
10128 | |
10129 | /* Search for the start of the main expression, recoding relocations | |
09b8f35a RS |
10130 | in REVERSED_RELOC. End the loop with CRUX pointing to the start |
10131 | of the main expression and with CRUX_DEPTH containing the number | |
10132 | of open brackets at that point. */ | |
10133 | reloc_index = -1; | |
10134 | str_depth = 0; | |
10135 | do | |
fb1b3232 | 10136 | { |
09b8f35a RS |
10137 | reloc_index++; |
10138 | crux = str; | |
10139 | crux_depth = str_depth; | |
10140 | ||
10141 | /* Skip over whitespace and brackets, keeping count of the number | |
10142 | of brackets. */ | |
10143 | while (*str == ' ' || *str == '\t' || *str == '(') | |
10144 | if (*str++ == '(') | |
10145 | str_depth++; | |
5e0116d5 | 10146 | } |
09b8f35a RS |
10147 | while (*str == '%' |
10148 | && reloc_index < (HAVE_NEWABI ? 3 : 1) | |
10149 | && parse_relocation (&str, &reversed_reloc[reloc_index])); | |
ad8d3bb3 | 10150 | |
09b8f35a | 10151 | my_getExpression (ep, crux); |
5e0116d5 | 10152 | str = expr_end; |
394f9b3a | 10153 | |
5e0116d5 | 10154 | /* Match every open bracket. */ |
09b8f35a | 10155 | while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t')) |
5e0116d5 | 10156 | if (*str++ == ')') |
09b8f35a | 10157 | crux_depth--; |
394f9b3a | 10158 | |
09b8f35a | 10159 | if (crux_depth > 0) |
5e0116d5 | 10160 | as_bad ("unclosed '('"); |
394f9b3a | 10161 | |
5e0116d5 | 10162 | expr_end = str; |
252b5132 | 10163 | |
01a3f561 | 10164 | if (reloc_index != 0) |
64bdfcaf RS |
10165 | { |
10166 | prev_reloc_op_frag = frag_now; | |
10167 | for (i = 0; i < reloc_index; i++) | |
10168 | reloc[i] = reversed_reloc[reloc_index - 1 - i]; | |
10169 | } | |
fb1b3232 | 10170 | |
5e0116d5 | 10171 | return reloc_index; |
252b5132 RH |
10172 | } |
10173 | ||
10174 | static void | |
17a2f251 | 10175 | my_getExpression (expressionS *ep, char *str) |
252b5132 RH |
10176 | { |
10177 | char *save_in; | |
98aa84af | 10178 | valueT val; |
252b5132 RH |
10179 | |
10180 | save_in = input_line_pointer; | |
10181 | input_line_pointer = str; | |
10182 | expression (ep); | |
10183 | expr_end = input_line_pointer; | |
10184 | input_line_pointer = save_in; | |
10185 | ||
10186 | /* If we are in mips16 mode, and this is an expression based on `.', | |
10187 | then we bump the value of the symbol by 1 since that is how other | |
10188 | text symbols are handled. We don't bother to handle complex | |
10189 | expressions, just `.' plus or minus a constant. */ | |
10190 | if (mips_opts.mips16 | |
10191 | && ep->X_op == O_symbol | |
10192 | && strcmp (S_GET_NAME (ep->X_add_symbol), FAKE_LABEL_NAME) == 0 | |
10193 | && S_GET_SEGMENT (ep->X_add_symbol) == now_seg | |
49309057 ILT |
10194 | && symbol_get_frag (ep->X_add_symbol) == frag_now |
10195 | && symbol_constant_p (ep->X_add_symbol) | |
98aa84af AM |
10196 | && (val = S_GET_VALUE (ep->X_add_symbol)) == frag_now_fix ()) |
10197 | S_SET_VALUE (ep->X_add_symbol, val + 1); | |
252b5132 RH |
10198 | } |
10199 | ||
10200 | /* Turn a string in input_line_pointer into a floating point constant | |
bc0d738a NC |
10201 | of type TYPE, and store the appropriate bytes in *LITP. The number |
10202 | of LITTLENUMS emitted is stored in *SIZEP. An error message is | |
252b5132 RH |
10203 | returned, or NULL on OK. */ |
10204 | ||
10205 | char * | |
17a2f251 | 10206 | md_atof (int type, char *litP, int *sizeP) |
252b5132 RH |
10207 | { |
10208 | int prec; | |
10209 | LITTLENUM_TYPE words[4]; | |
10210 | char *t; | |
10211 | int i; | |
10212 | ||
10213 | switch (type) | |
10214 | { | |
10215 | case 'f': | |
10216 | prec = 2; | |
10217 | break; | |
10218 | ||
10219 | case 'd': | |
10220 | prec = 4; | |
10221 | break; | |
10222 | ||
10223 | default: | |
10224 | *sizeP = 0; | |
10225 | return _("bad call to md_atof"); | |
10226 | } | |
10227 | ||
10228 | t = atof_ieee (input_line_pointer, type, words); | |
10229 | if (t) | |
10230 | input_line_pointer = t; | |
10231 | ||
10232 | *sizeP = prec * 2; | |
10233 | ||
10234 | if (! target_big_endian) | |
10235 | { | |
10236 | for (i = prec - 1; i >= 0; i--) | |
10237 | { | |
17a2f251 | 10238 | md_number_to_chars (litP, words[i], 2); |
252b5132 RH |
10239 | litP += 2; |
10240 | } | |
10241 | } | |
10242 | else | |
10243 | { | |
10244 | for (i = 0; i < prec; i++) | |
10245 | { | |
17a2f251 | 10246 | md_number_to_chars (litP, words[i], 2); |
252b5132 RH |
10247 | litP += 2; |
10248 | } | |
10249 | } | |
bdaaa2e1 | 10250 | |
252b5132 RH |
10251 | return NULL; |
10252 | } | |
10253 | ||
10254 | void | |
17a2f251 | 10255 | md_number_to_chars (char *buf, valueT val, int n) |
252b5132 RH |
10256 | { |
10257 | if (target_big_endian) | |
10258 | number_to_chars_bigendian (buf, val, n); | |
10259 | else | |
10260 | number_to_chars_littleendian (buf, val, n); | |
10261 | } | |
10262 | \f | |
ae948b86 | 10263 | #ifdef OBJ_ELF |
e013f690 TS |
10264 | static int support_64bit_objects(void) |
10265 | { | |
10266 | const char **list, **l; | |
aa3d8fdf | 10267 | int yes; |
e013f690 TS |
10268 | |
10269 | list = bfd_target_list (); | |
10270 | for (l = list; *l != NULL; l++) | |
10271 | #ifdef TE_TMIPS | |
10272 | /* This is traditional mips */ | |
10273 | if (strcmp (*l, "elf64-tradbigmips") == 0 | |
10274 | || strcmp (*l, "elf64-tradlittlemips") == 0) | |
10275 | #else | |
10276 | if (strcmp (*l, "elf64-bigmips") == 0 | |
10277 | || strcmp (*l, "elf64-littlemips") == 0) | |
10278 | #endif | |
10279 | break; | |
aa3d8fdf | 10280 | yes = (*l != NULL); |
e013f690 | 10281 | free (list); |
aa3d8fdf | 10282 | return yes; |
e013f690 | 10283 | } |
ae948b86 | 10284 | #endif /* OBJ_ELF */ |
e013f690 | 10285 | |
78849248 | 10286 | const char *md_shortopts = "O::g::G:"; |
252b5132 | 10287 | |
e972090a NC |
10288 | struct option md_longopts[] = |
10289 | { | |
f9b4148d CD |
10290 | /* Options which specify architecture. */ |
10291 | #define OPTION_ARCH_BASE (OPTION_MD_BASE) | |
10292 | #define OPTION_MARCH (OPTION_ARCH_BASE + 0) | |
10293 | {"march", required_argument, NULL, OPTION_MARCH}, | |
10294 | #define OPTION_MTUNE (OPTION_ARCH_BASE + 1) | |
10295 | {"mtune", required_argument, NULL, OPTION_MTUNE}, | |
10296 | #define OPTION_MIPS1 (OPTION_ARCH_BASE + 2) | |
252b5132 RH |
10297 | {"mips0", no_argument, NULL, OPTION_MIPS1}, |
10298 | {"mips1", no_argument, NULL, OPTION_MIPS1}, | |
f9b4148d | 10299 | #define OPTION_MIPS2 (OPTION_ARCH_BASE + 3) |
252b5132 | 10300 | {"mips2", no_argument, NULL, OPTION_MIPS2}, |
f9b4148d | 10301 | #define OPTION_MIPS3 (OPTION_ARCH_BASE + 4) |
252b5132 | 10302 | {"mips3", no_argument, NULL, OPTION_MIPS3}, |
f9b4148d | 10303 | #define OPTION_MIPS4 (OPTION_ARCH_BASE + 5) |
252b5132 | 10304 | {"mips4", no_argument, NULL, OPTION_MIPS4}, |
f9b4148d | 10305 | #define OPTION_MIPS5 (OPTION_ARCH_BASE + 6) |
ae948b86 | 10306 | {"mips5", no_argument, NULL, OPTION_MIPS5}, |
f9b4148d | 10307 | #define OPTION_MIPS32 (OPTION_ARCH_BASE + 7) |
ae948b86 | 10308 | {"mips32", no_argument, NULL, OPTION_MIPS32}, |
f9b4148d | 10309 | #define OPTION_MIPS64 (OPTION_ARCH_BASE + 8) |
ae948b86 | 10310 | {"mips64", no_argument, NULL, OPTION_MIPS64}, |
f9b4148d CD |
10311 | #define OPTION_MIPS32R2 (OPTION_ARCH_BASE + 9) |
10312 | {"mips32r2", no_argument, NULL, OPTION_MIPS32R2}, | |
5f74bc13 CD |
10313 | #define OPTION_MIPS64R2 (OPTION_ARCH_BASE + 10) |
10314 | {"mips64r2", no_argument, NULL, OPTION_MIPS64R2}, | |
f9b4148d CD |
10315 | |
10316 | /* Options which specify Application Specific Extensions (ASEs). */ | |
5f74bc13 | 10317 | #define OPTION_ASE_BASE (OPTION_ARCH_BASE + 11) |
f9b4148d CD |
10318 | #define OPTION_MIPS16 (OPTION_ASE_BASE + 0) |
10319 | {"mips16", no_argument, NULL, OPTION_MIPS16}, | |
10320 | #define OPTION_NO_MIPS16 (OPTION_ASE_BASE + 1) | |
10321 | {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16}, | |
10322 | #define OPTION_MIPS3D (OPTION_ASE_BASE + 2) | |
10323 | {"mips3d", no_argument, NULL, OPTION_MIPS3D}, | |
10324 | #define OPTION_NO_MIPS3D (OPTION_ASE_BASE + 3) | |
10325 | {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D}, | |
10326 | #define OPTION_MDMX (OPTION_ASE_BASE + 4) | |
10327 | {"mdmx", no_argument, NULL, OPTION_MDMX}, | |
10328 | #define OPTION_NO_MDMX (OPTION_ASE_BASE + 5) | |
10329 | {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX}, | |
74cd071d CF |
10330 | #define OPTION_DSP (OPTION_ASE_BASE + 6) |
10331 | {"mdsp", no_argument, NULL, OPTION_DSP}, | |
10332 | #define OPTION_NO_DSP (OPTION_ASE_BASE + 7) | |
10333 | {"mno-dsp", no_argument, NULL, OPTION_NO_DSP}, | |
ef2e4d86 CF |
10334 | #define OPTION_MT (OPTION_ASE_BASE + 8) |
10335 | {"mmt", no_argument, NULL, OPTION_MT}, | |
10336 | #define OPTION_NO_MT (OPTION_ASE_BASE + 9) | |
10337 | {"mno-mt", no_argument, NULL, OPTION_NO_MT}, | |
f9b4148d CD |
10338 | |
10339 | /* Old-style architecture options. Don't add more of these. */ | |
ef2e4d86 | 10340 | #define OPTION_COMPAT_ARCH_BASE (OPTION_ASE_BASE + 10) |
f9b4148d CD |
10341 | #define OPTION_M4650 (OPTION_COMPAT_ARCH_BASE + 0) |
10342 | {"m4650", no_argument, NULL, OPTION_M4650}, | |
10343 | #define OPTION_NO_M4650 (OPTION_COMPAT_ARCH_BASE + 1) | |
10344 | {"no-m4650", no_argument, NULL, OPTION_NO_M4650}, | |
10345 | #define OPTION_M4010 (OPTION_COMPAT_ARCH_BASE + 2) | |
10346 | {"m4010", no_argument, NULL, OPTION_M4010}, | |
10347 | #define OPTION_NO_M4010 (OPTION_COMPAT_ARCH_BASE + 3) | |
10348 | {"no-m4010", no_argument, NULL, OPTION_NO_M4010}, | |
10349 | #define OPTION_M4100 (OPTION_COMPAT_ARCH_BASE + 4) | |
10350 | {"m4100", no_argument, NULL, OPTION_M4100}, | |
10351 | #define OPTION_NO_M4100 (OPTION_COMPAT_ARCH_BASE + 5) | |
10352 | {"no-m4100", no_argument, NULL, OPTION_NO_M4100}, | |
10353 | #define OPTION_M3900 (OPTION_COMPAT_ARCH_BASE + 6) | |
10354 | {"m3900", no_argument, NULL, OPTION_M3900}, | |
10355 | #define OPTION_NO_M3900 (OPTION_COMPAT_ARCH_BASE + 7) | |
10356 | {"no-m3900", no_argument, NULL, OPTION_NO_M3900}, | |
10357 | ||
10358 | /* Options which enable bug fixes. */ | |
10359 | #define OPTION_FIX_BASE (OPTION_COMPAT_ARCH_BASE + 8) | |
10360 | #define OPTION_M7000_HILO_FIX (OPTION_FIX_BASE + 0) | |
10361 | {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX}, | |
10362 | #define OPTION_MNO_7000_HILO_FIX (OPTION_FIX_BASE + 1) | |
10363 | {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, | |
10364 | {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, | |
d766e8ec RS |
10365 | #define OPTION_FIX_VR4120 (OPTION_FIX_BASE + 2) |
10366 | #define OPTION_NO_FIX_VR4120 (OPTION_FIX_BASE + 3) | |
10367 | {"mfix-vr4120", no_argument, NULL, OPTION_FIX_VR4120}, | |
10368 | {"mno-fix-vr4120", no_argument, NULL, OPTION_NO_FIX_VR4120}, | |
7d8e00cf RS |
10369 | #define OPTION_FIX_VR4130 (OPTION_FIX_BASE + 4) |
10370 | #define OPTION_NO_FIX_VR4130 (OPTION_FIX_BASE + 5) | |
10371 | {"mfix-vr4130", no_argument, NULL, OPTION_FIX_VR4130}, | |
10372 | {"mno-fix-vr4130", no_argument, NULL, OPTION_NO_FIX_VR4130}, | |
f9b4148d CD |
10373 | |
10374 | /* Miscellaneous options. */ | |
7d8e00cf | 10375 | #define OPTION_MISC_BASE (OPTION_FIX_BASE + 6) |
1ffcab4b | 10376 | #define OPTION_TRAP (OPTION_MISC_BASE + 0) |
252b5132 RH |
10377 | {"trap", no_argument, NULL, OPTION_TRAP}, |
10378 | {"no-break", no_argument, NULL, OPTION_TRAP}, | |
1ffcab4b | 10379 | #define OPTION_BREAK (OPTION_MISC_BASE + 1) |
252b5132 RH |
10380 | {"break", no_argument, NULL, OPTION_BREAK}, |
10381 | {"no-trap", no_argument, NULL, OPTION_BREAK}, | |
1ffcab4b | 10382 | #define OPTION_EB (OPTION_MISC_BASE + 2) |
252b5132 | 10383 | {"EB", no_argument, NULL, OPTION_EB}, |
1ffcab4b | 10384 | #define OPTION_EL (OPTION_MISC_BASE + 3) |
252b5132 | 10385 | {"EL", no_argument, NULL, OPTION_EL}, |
1ffcab4b | 10386 | #define OPTION_FP32 (OPTION_MISC_BASE + 4) |
ae948b86 | 10387 | {"mfp32", no_argument, NULL, OPTION_FP32}, |
1ffcab4b | 10388 | #define OPTION_GP32 (OPTION_MISC_BASE + 5) |
c97ef257 | 10389 | {"mgp32", no_argument, NULL, OPTION_GP32}, |
1ffcab4b | 10390 | #define OPTION_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 6) |
119d663a | 10391 | {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS}, |
1ffcab4b | 10392 | #define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 7) |
119d663a | 10393 | {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS}, |
1ffcab4b | 10394 | #define OPTION_FP64 (OPTION_MISC_BASE + 8) |
316f5878 | 10395 | {"mfp64", no_argument, NULL, OPTION_FP64}, |
1ffcab4b | 10396 | #define OPTION_GP64 (OPTION_MISC_BASE + 9) |
ae948b86 | 10397 | {"mgp64", no_argument, NULL, OPTION_GP64}, |
1ffcab4b CD |
10398 | #define OPTION_RELAX_BRANCH (OPTION_MISC_BASE + 10) |
10399 | #define OPTION_NO_RELAX_BRANCH (OPTION_MISC_BASE + 11) | |
4a6a3df4 AO |
10400 | {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH}, |
10401 | {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH}, | |
aa6975fb ILT |
10402 | #define OPTION_MSHARED (OPTION_MISC_BASE + 12) |
10403 | #define OPTION_MNO_SHARED (OPTION_MISC_BASE + 13) | |
10404 | {"mshared", no_argument, NULL, OPTION_MSHARED}, | |
10405 | {"mno-shared", no_argument, NULL, OPTION_MNO_SHARED}, | |
aed1a261 RS |
10406 | #define OPTION_MSYM32 (OPTION_MISC_BASE + 14) |
10407 | #define OPTION_MNO_SYM32 (OPTION_MISC_BASE + 15) | |
10408 | {"msym32", no_argument, NULL, OPTION_MSYM32}, | |
10409 | {"mno-sym32", no_argument, NULL, OPTION_MNO_SYM32}, | |
f9b4148d CD |
10410 | |
10411 | /* ELF-specific options. */ | |
156c2f8b | 10412 | #ifdef OBJ_ELF |
aed1a261 | 10413 | #define OPTION_ELF_BASE (OPTION_MISC_BASE + 16) |
156c2f8b | 10414 | #define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0) |
156c2f8b NC |
10415 | {"KPIC", no_argument, NULL, OPTION_CALL_SHARED}, |
10416 | {"call_shared", no_argument, NULL, OPTION_CALL_SHARED}, | |
ae948b86 | 10417 | #define OPTION_NON_SHARED (OPTION_ELF_BASE + 1) |
156c2f8b | 10418 | {"non_shared", no_argument, NULL, OPTION_NON_SHARED}, |
ae948b86 | 10419 | #define OPTION_XGOT (OPTION_ELF_BASE + 2) |
156c2f8b | 10420 | {"xgot", no_argument, NULL, OPTION_XGOT}, |
ae948b86 TS |
10421 | #define OPTION_MABI (OPTION_ELF_BASE + 3) |
10422 | {"mabi", required_argument, NULL, OPTION_MABI}, | |
10423 | #define OPTION_32 (OPTION_ELF_BASE + 4) | |
156c2f8b | 10424 | {"32", no_argument, NULL, OPTION_32}, |
ae948b86 | 10425 | #define OPTION_N32 (OPTION_ELF_BASE + 5) |
e013f690 | 10426 | {"n32", no_argument, NULL, OPTION_N32}, |
ae948b86 | 10427 | #define OPTION_64 (OPTION_ELF_BASE + 6) |
156c2f8b | 10428 | {"64", no_argument, NULL, OPTION_64}, |
ecb4347a DJ |
10429 | #define OPTION_MDEBUG (OPTION_ELF_BASE + 7) |
10430 | {"mdebug", no_argument, NULL, OPTION_MDEBUG}, | |
10431 | #define OPTION_NO_MDEBUG (OPTION_ELF_BASE + 8) | |
10432 | {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG}, | |
dcd410fe RO |
10433 | #define OPTION_PDR (OPTION_ELF_BASE + 9) |
10434 | {"mpdr", no_argument, NULL, OPTION_PDR}, | |
10435 | #define OPTION_NO_PDR (OPTION_ELF_BASE + 10) | |
10436 | {"mno-pdr", no_argument, NULL, OPTION_NO_PDR}, | |
ae948b86 | 10437 | #endif /* OBJ_ELF */ |
f9b4148d | 10438 | |
252b5132 RH |
10439 | {NULL, no_argument, NULL, 0} |
10440 | }; | |
156c2f8b | 10441 | size_t md_longopts_size = sizeof (md_longopts); |
252b5132 | 10442 | |
316f5878 RS |
10443 | /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to |
10444 | NEW_VALUE. Warn if another value was already specified. Note: | |
10445 | we have to defer parsing the -march and -mtune arguments in order | |
10446 | to handle 'from-abi' correctly, since the ABI might be specified | |
10447 | in a later argument. */ | |
10448 | ||
10449 | static void | |
17a2f251 | 10450 | mips_set_option_string (const char **string_ptr, const char *new_value) |
316f5878 RS |
10451 | { |
10452 | if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0) | |
10453 | as_warn (_("A different %s was already specified, is now %s"), | |
10454 | string_ptr == &mips_arch_string ? "-march" : "-mtune", | |
10455 | new_value); | |
10456 | ||
10457 | *string_ptr = new_value; | |
10458 | } | |
10459 | ||
252b5132 | 10460 | int |
17a2f251 | 10461 | md_parse_option (int c, char *arg) |
252b5132 RH |
10462 | { |
10463 | switch (c) | |
10464 | { | |
119d663a NC |
10465 | case OPTION_CONSTRUCT_FLOATS: |
10466 | mips_disable_float_construction = 0; | |
10467 | break; | |
bdaaa2e1 | 10468 | |
119d663a NC |
10469 | case OPTION_NO_CONSTRUCT_FLOATS: |
10470 | mips_disable_float_construction = 1; | |
10471 | break; | |
bdaaa2e1 | 10472 | |
252b5132 RH |
10473 | case OPTION_TRAP: |
10474 | mips_trap = 1; | |
10475 | break; | |
10476 | ||
10477 | case OPTION_BREAK: | |
10478 | mips_trap = 0; | |
10479 | break; | |
10480 | ||
10481 | case OPTION_EB: | |
10482 | target_big_endian = 1; | |
10483 | break; | |
10484 | ||
10485 | case OPTION_EL: | |
10486 | target_big_endian = 0; | |
10487 | break; | |
10488 | ||
10489 | case 'O': | |
10490 | if (arg && arg[1] == '0') | |
10491 | mips_optimize = 1; | |
10492 | else | |
10493 | mips_optimize = 2; | |
10494 | break; | |
10495 | ||
10496 | case 'g': | |
10497 | if (arg == NULL) | |
10498 | mips_debug = 2; | |
10499 | else | |
10500 | mips_debug = atoi (arg); | |
10501 | /* When the MIPS assembler sees -g or -g2, it does not do | |
10502 | optimizations which limit full symbolic debugging. We take | |
10503 | that to be equivalent to -O0. */ | |
10504 | if (mips_debug == 2) | |
10505 | mips_optimize = 1; | |
10506 | break; | |
10507 | ||
10508 | case OPTION_MIPS1: | |
316f5878 | 10509 | file_mips_isa = ISA_MIPS1; |
252b5132 RH |
10510 | break; |
10511 | ||
10512 | case OPTION_MIPS2: | |
316f5878 | 10513 | file_mips_isa = ISA_MIPS2; |
252b5132 RH |
10514 | break; |
10515 | ||
10516 | case OPTION_MIPS3: | |
316f5878 | 10517 | file_mips_isa = ISA_MIPS3; |
252b5132 RH |
10518 | break; |
10519 | ||
10520 | case OPTION_MIPS4: | |
316f5878 | 10521 | file_mips_isa = ISA_MIPS4; |
e7af610e NC |
10522 | break; |
10523 | ||
84ea6cf2 | 10524 | case OPTION_MIPS5: |
316f5878 | 10525 | file_mips_isa = ISA_MIPS5; |
84ea6cf2 NC |
10526 | break; |
10527 | ||
e7af610e | 10528 | case OPTION_MIPS32: |
316f5878 | 10529 | file_mips_isa = ISA_MIPS32; |
252b5132 RH |
10530 | break; |
10531 | ||
af7ee8bf CD |
10532 | case OPTION_MIPS32R2: |
10533 | file_mips_isa = ISA_MIPS32R2; | |
10534 | break; | |
10535 | ||
5f74bc13 CD |
10536 | case OPTION_MIPS64R2: |
10537 | file_mips_isa = ISA_MIPS64R2; | |
10538 | break; | |
10539 | ||
84ea6cf2 | 10540 | case OPTION_MIPS64: |
316f5878 | 10541 | file_mips_isa = ISA_MIPS64; |
84ea6cf2 NC |
10542 | break; |
10543 | ||
ec68c924 | 10544 | case OPTION_MTUNE: |
316f5878 RS |
10545 | mips_set_option_string (&mips_tune_string, arg); |
10546 | break; | |
ec68c924 | 10547 | |
316f5878 RS |
10548 | case OPTION_MARCH: |
10549 | mips_set_option_string (&mips_arch_string, arg); | |
252b5132 RH |
10550 | break; |
10551 | ||
10552 | case OPTION_M4650: | |
316f5878 RS |
10553 | mips_set_option_string (&mips_arch_string, "4650"); |
10554 | mips_set_option_string (&mips_tune_string, "4650"); | |
252b5132 RH |
10555 | break; |
10556 | ||
10557 | case OPTION_NO_M4650: | |
10558 | break; | |
10559 | ||
10560 | case OPTION_M4010: | |
316f5878 RS |
10561 | mips_set_option_string (&mips_arch_string, "4010"); |
10562 | mips_set_option_string (&mips_tune_string, "4010"); | |
252b5132 RH |
10563 | break; |
10564 | ||
10565 | case OPTION_NO_M4010: | |
10566 | break; | |
10567 | ||
10568 | case OPTION_M4100: | |
316f5878 RS |
10569 | mips_set_option_string (&mips_arch_string, "4100"); |
10570 | mips_set_option_string (&mips_tune_string, "4100"); | |
252b5132 RH |
10571 | break; |
10572 | ||
10573 | case OPTION_NO_M4100: | |
10574 | break; | |
10575 | ||
252b5132 | 10576 | case OPTION_M3900: |
316f5878 RS |
10577 | mips_set_option_string (&mips_arch_string, "3900"); |
10578 | mips_set_option_string (&mips_tune_string, "3900"); | |
252b5132 | 10579 | break; |
bdaaa2e1 | 10580 | |
252b5132 RH |
10581 | case OPTION_NO_M3900: |
10582 | break; | |
10583 | ||
deec1734 CD |
10584 | case OPTION_MDMX: |
10585 | mips_opts.ase_mdmx = 1; | |
10586 | break; | |
10587 | ||
10588 | case OPTION_NO_MDMX: | |
10589 | mips_opts.ase_mdmx = 0; | |
10590 | break; | |
10591 | ||
74cd071d CF |
10592 | case OPTION_DSP: |
10593 | mips_opts.ase_dsp = 1; | |
10594 | break; | |
10595 | ||
10596 | case OPTION_NO_DSP: | |
10597 | mips_opts.ase_dsp = 0; | |
10598 | break; | |
10599 | ||
ef2e4d86 CF |
10600 | case OPTION_MT: |
10601 | mips_opts.ase_mt = 1; | |
10602 | break; | |
10603 | ||
10604 | case OPTION_NO_MT: | |
10605 | mips_opts.ase_mt = 0; | |
10606 | break; | |
10607 | ||
252b5132 RH |
10608 | case OPTION_MIPS16: |
10609 | mips_opts.mips16 = 1; | |
7d10b47d | 10610 | mips_no_prev_insn (); |
252b5132 RH |
10611 | break; |
10612 | ||
10613 | case OPTION_NO_MIPS16: | |
10614 | mips_opts.mips16 = 0; | |
7d10b47d | 10615 | mips_no_prev_insn (); |
252b5132 RH |
10616 | break; |
10617 | ||
1f25f5d3 CD |
10618 | case OPTION_MIPS3D: |
10619 | mips_opts.ase_mips3d = 1; | |
10620 | break; | |
10621 | ||
10622 | case OPTION_NO_MIPS3D: | |
10623 | mips_opts.ase_mips3d = 0; | |
10624 | break; | |
10625 | ||
d766e8ec RS |
10626 | case OPTION_FIX_VR4120: |
10627 | mips_fix_vr4120 = 1; | |
60b63b72 RS |
10628 | break; |
10629 | ||
d766e8ec RS |
10630 | case OPTION_NO_FIX_VR4120: |
10631 | mips_fix_vr4120 = 0; | |
60b63b72 RS |
10632 | break; |
10633 | ||
7d8e00cf RS |
10634 | case OPTION_FIX_VR4130: |
10635 | mips_fix_vr4130 = 1; | |
10636 | break; | |
10637 | ||
10638 | case OPTION_NO_FIX_VR4130: | |
10639 | mips_fix_vr4130 = 0; | |
10640 | break; | |
10641 | ||
4a6a3df4 AO |
10642 | case OPTION_RELAX_BRANCH: |
10643 | mips_relax_branch = 1; | |
10644 | break; | |
10645 | ||
10646 | case OPTION_NO_RELAX_BRANCH: | |
10647 | mips_relax_branch = 0; | |
10648 | break; | |
10649 | ||
aa6975fb ILT |
10650 | case OPTION_MSHARED: |
10651 | mips_in_shared = TRUE; | |
10652 | break; | |
10653 | ||
10654 | case OPTION_MNO_SHARED: | |
10655 | mips_in_shared = FALSE; | |
10656 | break; | |
10657 | ||
aed1a261 RS |
10658 | case OPTION_MSYM32: |
10659 | mips_opts.sym32 = TRUE; | |
10660 | break; | |
10661 | ||
10662 | case OPTION_MNO_SYM32: | |
10663 | mips_opts.sym32 = FALSE; | |
10664 | break; | |
10665 | ||
0f074f60 | 10666 | #ifdef OBJ_ELF |
252b5132 RH |
10667 | /* When generating ELF code, we permit -KPIC and -call_shared to |
10668 | select SVR4_PIC, and -non_shared to select no PIC. This is | |
10669 | intended to be compatible with Irix 5. */ | |
10670 | case OPTION_CALL_SHARED: | |
10671 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
10672 | { | |
10673 | as_bad (_("-call_shared is supported only for ELF format")); | |
10674 | return 0; | |
10675 | } | |
10676 | mips_pic = SVR4_PIC; | |
143d77c5 | 10677 | mips_abicalls = TRUE; |
252b5132 RH |
10678 | if (g_switch_seen && g_switch_value != 0) |
10679 | { | |
10680 | as_bad (_("-G may not be used with SVR4 PIC code")); | |
10681 | return 0; | |
10682 | } | |
10683 | g_switch_value = 0; | |
10684 | break; | |
10685 | ||
10686 | case OPTION_NON_SHARED: | |
10687 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
10688 | { | |
10689 | as_bad (_("-non_shared is supported only for ELF format")); | |
10690 | return 0; | |
10691 | } | |
10692 | mips_pic = NO_PIC; | |
143d77c5 | 10693 | mips_abicalls = FALSE; |
252b5132 RH |
10694 | break; |
10695 | ||
10696 | /* The -xgot option tells the assembler to use 32 offsets when | |
10697 | accessing the got in SVR4_PIC mode. It is for Irix | |
10698 | compatibility. */ | |
10699 | case OPTION_XGOT: | |
10700 | mips_big_got = 1; | |
10701 | break; | |
0f074f60 | 10702 | #endif /* OBJ_ELF */ |
252b5132 RH |
10703 | |
10704 | case 'G': | |
6caf9ef4 TS |
10705 | g_switch_value = atoi (arg); |
10706 | g_switch_seen = 1; | |
10707 | if (mips_pic == SVR4_PIC && g_switch_value != 0) | |
252b5132 | 10708 | { |
3e722fb5 | 10709 | as_bad (_("-G may not be used with SVR4 PIC code")); |
252b5132 RH |
10710 | return 0; |
10711 | } | |
252b5132 RH |
10712 | break; |
10713 | ||
0f074f60 | 10714 | #ifdef OBJ_ELF |
34ba82a8 TS |
10715 | /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32 |
10716 | and -mabi=64. */ | |
252b5132 | 10717 | case OPTION_32: |
34ba82a8 TS |
10718 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
10719 | { | |
10720 | as_bad (_("-32 is supported for ELF format only")); | |
10721 | return 0; | |
10722 | } | |
316f5878 | 10723 | mips_abi = O32_ABI; |
252b5132 RH |
10724 | break; |
10725 | ||
e013f690 | 10726 | case OPTION_N32: |
34ba82a8 TS |
10727 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
10728 | { | |
10729 | as_bad (_("-n32 is supported for ELF format only")); | |
10730 | return 0; | |
10731 | } | |
316f5878 | 10732 | mips_abi = N32_ABI; |
e013f690 | 10733 | break; |
252b5132 | 10734 | |
e013f690 | 10735 | case OPTION_64: |
34ba82a8 TS |
10736 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
10737 | { | |
10738 | as_bad (_("-64 is supported for ELF format only")); | |
10739 | return 0; | |
10740 | } | |
316f5878 | 10741 | mips_abi = N64_ABI; |
e013f690 TS |
10742 | if (! support_64bit_objects()) |
10743 | as_fatal (_("No compiled in support for 64 bit object file format")); | |
252b5132 | 10744 | break; |
ae948b86 | 10745 | #endif /* OBJ_ELF */ |
252b5132 | 10746 | |
c97ef257 | 10747 | case OPTION_GP32: |
a325df1d | 10748 | file_mips_gp32 = 1; |
c97ef257 AH |
10749 | break; |
10750 | ||
10751 | case OPTION_GP64: | |
a325df1d | 10752 | file_mips_gp32 = 0; |
c97ef257 | 10753 | break; |
252b5132 | 10754 | |
ca4e0257 | 10755 | case OPTION_FP32: |
a325df1d | 10756 | file_mips_fp32 = 1; |
316f5878 RS |
10757 | break; |
10758 | ||
10759 | case OPTION_FP64: | |
10760 | file_mips_fp32 = 0; | |
ca4e0257 RS |
10761 | break; |
10762 | ||
ae948b86 | 10763 | #ifdef OBJ_ELF |
252b5132 | 10764 | case OPTION_MABI: |
34ba82a8 TS |
10765 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
10766 | { | |
10767 | as_bad (_("-mabi is supported for ELF format only")); | |
10768 | return 0; | |
10769 | } | |
e013f690 | 10770 | if (strcmp (arg, "32") == 0) |
316f5878 | 10771 | mips_abi = O32_ABI; |
e013f690 | 10772 | else if (strcmp (arg, "o64") == 0) |
316f5878 | 10773 | mips_abi = O64_ABI; |
e013f690 | 10774 | else if (strcmp (arg, "n32") == 0) |
316f5878 | 10775 | mips_abi = N32_ABI; |
e013f690 TS |
10776 | else if (strcmp (arg, "64") == 0) |
10777 | { | |
316f5878 | 10778 | mips_abi = N64_ABI; |
e013f690 TS |
10779 | if (! support_64bit_objects()) |
10780 | as_fatal (_("No compiled in support for 64 bit object file " | |
10781 | "format")); | |
10782 | } | |
10783 | else if (strcmp (arg, "eabi") == 0) | |
316f5878 | 10784 | mips_abi = EABI_ABI; |
e013f690 | 10785 | else |
da0e507f TS |
10786 | { |
10787 | as_fatal (_("invalid abi -mabi=%s"), arg); | |
10788 | return 0; | |
10789 | } | |
252b5132 | 10790 | break; |
e013f690 | 10791 | #endif /* OBJ_ELF */ |
252b5132 | 10792 | |
6b76fefe | 10793 | case OPTION_M7000_HILO_FIX: |
b34976b6 | 10794 | mips_7000_hilo_fix = TRUE; |
6b76fefe CM |
10795 | break; |
10796 | ||
9ee72ff1 | 10797 | case OPTION_MNO_7000_HILO_FIX: |
b34976b6 | 10798 | mips_7000_hilo_fix = FALSE; |
6b76fefe CM |
10799 | break; |
10800 | ||
ecb4347a DJ |
10801 | #ifdef OBJ_ELF |
10802 | case OPTION_MDEBUG: | |
b34976b6 | 10803 | mips_flag_mdebug = TRUE; |
ecb4347a DJ |
10804 | break; |
10805 | ||
10806 | case OPTION_NO_MDEBUG: | |
b34976b6 | 10807 | mips_flag_mdebug = FALSE; |
ecb4347a | 10808 | break; |
dcd410fe RO |
10809 | |
10810 | case OPTION_PDR: | |
10811 | mips_flag_pdr = TRUE; | |
10812 | break; | |
10813 | ||
10814 | case OPTION_NO_PDR: | |
10815 | mips_flag_pdr = FALSE; | |
10816 | break; | |
ecb4347a DJ |
10817 | #endif /* OBJ_ELF */ |
10818 | ||
252b5132 RH |
10819 | default: |
10820 | return 0; | |
10821 | } | |
10822 | ||
10823 | return 1; | |
10824 | } | |
316f5878 RS |
10825 | \f |
10826 | /* Set up globals to generate code for the ISA or processor | |
10827 | described by INFO. */ | |
252b5132 | 10828 | |
252b5132 | 10829 | static void |
17a2f251 | 10830 | mips_set_architecture (const struct mips_cpu_info *info) |
252b5132 | 10831 | { |
316f5878 | 10832 | if (info != 0) |
252b5132 | 10833 | { |
fef14a42 TS |
10834 | file_mips_arch = info->cpu; |
10835 | mips_opts.arch = info->cpu; | |
316f5878 | 10836 | mips_opts.isa = info->isa; |
252b5132 | 10837 | } |
252b5132 RH |
10838 | } |
10839 | ||
252b5132 | 10840 | |
316f5878 | 10841 | /* Likewise for tuning. */ |
252b5132 | 10842 | |
316f5878 | 10843 | static void |
17a2f251 | 10844 | mips_set_tune (const struct mips_cpu_info *info) |
316f5878 RS |
10845 | { |
10846 | if (info != 0) | |
fef14a42 | 10847 | mips_tune = info->cpu; |
316f5878 | 10848 | } |
80cc45a5 | 10849 | |
34ba82a8 | 10850 | |
252b5132 | 10851 | void |
17a2f251 | 10852 | mips_after_parse_args (void) |
e9670677 | 10853 | { |
fef14a42 TS |
10854 | const struct mips_cpu_info *arch_info = 0; |
10855 | const struct mips_cpu_info *tune_info = 0; | |
10856 | ||
e9670677 | 10857 | /* GP relative stuff not working for PE */ |
6caf9ef4 | 10858 | if (strncmp (TARGET_OS, "pe", 2) == 0) |
e9670677 | 10859 | { |
6caf9ef4 | 10860 | if (g_switch_seen && g_switch_value != 0) |
e9670677 MR |
10861 | as_bad (_("-G not supported in this configuration.")); |
10862 | g_switch_value = 0; | |
10863 | } | |
10864 | ||
cac012d6 AO |
10865 | if (mips_abi == NO_ABI) |
10866 | mips_abi = MIPS_DEFAULT_ABI; | |
10867 | ||
22923709 RS |
10868 | /* The following code determines the architecture and register size. |
10869 | Similar code was added to GCC 3.3 (see override_options() in | |
10870 | config/mips/mips.c). The GAS and GCC code should be kept in sync | |
10871 | as much as possible. */ | |
e9670677 | 10872 | |
316f5878 | 10873 | if (mips_arch_string != 0) |
fef14a42 | 10874 | arch_info = mips_parse_cpu ("-march", mips_arch_string); |
e9670677 | 10875 | |
316f5878 | 10876 | if (file_mips_isa != ISA_UNKNOWN) |
e9670677 | 10877 | { |
316f5878 | 10878 | /* Handle -mipsN. At this point, file_mips_isa contains the |
fef14a42 | 10879 | ISA level specified by -mipsN, while arch_info->isa contains |
316f5878 | 10880 | the -march selection (if any). */ |
fef14a42 | 10881 | if (arch_info != 0) |
e9670677 | 10882 | { |
316f5878 RS |
10883 | /* -march takes precedence over -mipsN, since it is more descriptive. |
10884 | There's no harm in specifying both as long as the ISA levels | |
10885 | are the same. */ | |
fef14a42 | 10886 | if (file_mips_isa != arch_info->isa) |
316f5878 RS |
10887 | as_bad (_("-%s conflicts with the other architecture options, which imply -%s"), |
10888 | mips_cpu_info_from_isa (file_mips_isa)->name, | |
fef14a42 | 10889 | mips_cpu_info_from_isa (arch_info->isa)->name); |
e9670677 | 10890 | } |
316f5878 | 10891 | else |
fef14a42 | 10892 | arch_info = mips_cpu_info_from_isa (file_mips_isa); |
e9670677 MR |
10893 | } |
10894 | ||
fef14a42 TS |
10895 | if (arch_info == 0) |
10896 | arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT); | |
e9670677 | 10897 | |
fef14a42 | 10898 | if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa)) |
316f5878 | 10899 | as_bad ("-march=%s is not compatible with the selected ABI", |
fef14a42 TS |
10900 | arch_info->name); |
10901 | ||
10902 | mips_set_architecture (arch_info); | |
10903 | ||
10904 | /* Optimize for file_mips_arch, unless -mtune selects a different processor. */ | |
10905 | if (mips_tune_string != 0) | |
10906 | tune_info = mips_parse_cpu ("-mtune", mips_tune_string); | |
e9670677 | 10907 | |
fef14a42 TS |
10908 | if (tune_info == 0) |
10909 | mips_set_tune (arch_info); | |
10910 | else | |
10911 | mips_set_tune (tune_info); | |
e9670677 | 10912 | |
316f5878 | 10913 | if (file_mips_gp32 >= 0) |
e9670677 | 10914 | { |
316f5878 RS |
10915 | /* The user specified the size of the integer registers. Make sure |
10916 | it agrees with the ABI and ISA. */ | |
10917 | if (file_mips_gp32 == 0 && !ISA_HAS_64BIT_REGS (mips_opts.isa)) | |
10918 | as_bad (_("-mgp64 used with a 32-bit processor")); | |
10919 | else if (file_mips_gp32 == 1 && ABI_NEEDS_64BIT_REGS (mips_abi)) | |
10920 | as_bad (_("-mgp32 used with a 64-bit ABI")); | |
10921 | else if (file_mips_gp32 == 0 && ABI_NEEDS_32BIT_REGS (mips_abi)) | |
10922 | as_bad (_("-mgp64 used with a 32-bit ABI")); | |
e9670677 MR |
10923 | } |
10924 | else | |
10925 | { | |
316f5878 RS |
10926 | /* Infer the integer register size from the ABI and processor. |
10927 | Restrict ourselves to 32-bit registers if that's all the | |
10928 | processor has, or if the ABI cannot handle 64-bit registers. */ | |
10929 | file_mips_gp32 = (ABI_NEEDS_32BIT_REGS (mips_abi) | |
10930 | || !ISA_HAS_64BIT_REGS (mips_opts.isa)); | |
e9670677 MR |
10931 | } |
10932 | ||
316f5878 RS |
10933 | /* ??? GAS treats single-float processors as though they had 64-bit |
10934 | float registers (although it complains when double-precision | |
10935 | instructions are used). As things stand, saying they have 32-bit | |
10936 | registers would lead to spurious "register must be even" messages. | |
10937 | So here we assume float registers are always the same size as | |
10938 | integer ones, unless the user says otherwise. */ | |
10939 | if (file_mips_fp32 < 0) | |
10940 | file_mips_fp32 = file_mips_gp32; | |
e9670677 | 10941 | |
316f5878 | 10942 | /* End of GCC-shared inference code. */ |
e9670677 | 10943 | |
17a2f251 TS |
10944 | /* This flag is set when we have a 64-bit capable CPU but use only |
10945 | 32-bit wide registers. Note that EABI does not use it. */ | |
10946 | if (ISA_HAS_64BIT_REGS (mips_opts.isa) | |
10947 | && ((mips_abi == NO_ABI && file_mips_gp32 == 1) | |
10948 | || mips_abi == O32_ABI)) | |
316f5878 | 10949 | mips_32bitmode = 1; |
e9670677 MR |
10950 | |
10951 | if (mips_opts.isa == ISA_MIPS1 && mips_trap) | |
10952 | as_bad (_("trap exception not supported at ISA 1")); | |
10953 | ||
e9670677 MR |
10954 | /* If the selected architecture includes support for ASEs, enable |
10955 | generation of code for them. */ | |
a4672219 | 10956 | if (mips_opts.mips16 == -1) |
fef14a42 | 10957 | mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_arch)) ? 1 : 0; |
ffdefa66 | 10958 | if (mips_opts.ase_mips3d == -1) |
fef14a42 | 10959 | mips_opts.ase_mips3d = (CPU_HAS_MIPS3D (file_mips_arch)) ? 1 : 0; |
ffdefa66 | 10960 | if (mips_opts.ase_mdmx == -1) |
fef14a42 | 10961 | mips_opts.ase_mdmx = (CPU_HAS_MDMX (file_mips_arch)) ? 1 : 0; |
74cd071d CF |
10962 | if (mips_opts.ase_dsp == -1) |
10963 | mips_opts.ase_dsp = (CPU_HAS_DSP (file_mips_arch)) ? 1 : 0; | |
ef2e4d86 CF |
10964 | if (mips_opts.ase_mt == -1) |
10965 | mips_opts.ase_mt = (CPU_HAS_MT (file_mips_arch)) ? 1 : 0; | |
e9670677 | 10966 | |
e9670677 | 10967 | file_mips_isa = mips_opts.isa; |
a4672219 | 10968 | file_ase_mips16 = mips_opts.mips16; |
e9670677 MR |
10969 | file_ase_mips3d = mips_opts.ase_mips3d; |
10970 | file_ase_mdmx = mips_opts.ase_mdmx; | |
74cd071d | 10971 | file_ase_dsp = mips_opts.ase_dsp; |
ef2e4d86 | 10972 | file_ase_mt = mips_opts.ase_mt; |
e9670677 MR |
10973 | mips_opts.gp32 = file_mips_gp32; |
10974 | mips_opts.fp32 = file_mips_fp32; | |
10975 | ||
ecb4347a DJ |
10976 | if (mips_flag_mdebug < 0) |
10977 | { | |
10978 | #ifdef OBJ_MAYBE_ECOFF | |
10979 | if (OUTPUT_FLAVOR == bfd_target_ecoff_flavour) | |
10980 | mips_flag_mdebug = 1; | |
10981 | else | |
10982 | #endif /* OBJ_MAYBE_ECOFF */ | |
10983 | mips_flag_mdebug = 0; | |
10984 | } | |
e9670677 MR |
10985 | } |
10986 | \f | |
10987 | void | |
17a2f251 | 10988 | mips_init_after_args (void) |
252b5132 RH |
10989 | { |
10990 | /* initialize opcodes */ | |
10991 | bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes; | |
beae10d5 | 10992 | mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes; |
252b5132 RH |
10993 | } |
10994 | ||
10995 | long | |
17a2f251 | 10996 | md_pcrel_from (fixS *fixP) |
252b5132 | 10997 | { |
a7ebbfdf TS |
10998 | valueT addr = fixP->fx_where + fixP->fx_frag->fr_address; |
10999 | switch (fixP->fx_r_type) | |
11000 | { | |
11001 | case BFD_RELOC_16_PCREL_S2: | |
11002 | case BFD_RELOC_MIPS_JMP: | |
11003 | /* Return the address of the delay slot. */ | |
11004 | return addr + 4; | |
11005 | default: | |
11006 | return addr; | |
11007 | } | |
252b5132 RH |
11008 | } |
11009 | ||
252b5132 RH |
11010 | /* This is called before the symbol table is processed. In order to |
11011 | work with gcc when using mips-tfile, we must keep all local labels. | |
11012 | However, in other cases, we want to discard them. If we were | |
11013 | called with -g, but we didn't see any debugging information, it may | |
11014 | mean that gcc is smuggling debugging information through to | |
11015 | mips-tfile, in which case we must generate all local labels. */ | |
11016 | ||
11017 | void | |
17a2f251 | 11018 | mips_frob_file_before_adjust (void) |
252b5132 RH |
11019 | { |
11020 | #ifndef NO_ECOFF_DEBUGGING | |
11021 | if (ECOFF_DEBUGGING | |
11022 | && mips_debug != 0 | |
11023 | && ! ecoff_debugging_seen) | |
11024 | flag_keep_locals = 1; | |
11025 | #endif | |
11026 | } | |
11027 | ||
3b91255e | 11028 | /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede |
55cf6793 | 11029 | the corresponding LO16 reloc. This is called before md_apply_fix and |
3b91255e RS |
11030 | tc_gen_reloc. Unmatched relocs can only be generated by use of explicit |
11031 | relocation operators. | |
11032 | ||
11033 | For our purposes, a %lo() expression matches a %got() or %hi() | |
11034 | expression if: | |
11035 | ||
11036 | (a) it refers to the same symbol; and | |
11037 | (b) the offset applied in the %lo() expression is no lower than | |
11038 | the offset applied in the %got() or %hi(). | |
11039 | ||
11040 | (b) allows us to cope with code like: | |
11041 | ||
11042 | lui $4,%hi(foo) | |
11043 | lh $4,%lo(foo+2)($4) | |
11044 | ||
11045 | ...which is legal on RELA targets, and has a well-defined behaviour | |
11046 | if the user knows that adding 2 to "foo" will not induce a carry to | |
11047 | the high 16 bits. | |
11048 | ||
11049 | When several %lo()s match a particular %got() or %hi(), we use the | |
11050 | following rules to distinguish them: | |
11051 | ||
11052 | (1) %lo()s with smaller offsets are a better match than %lo()s with | |
11053 | higher offsets. | |
11054 | ||
11055 | (2) %lo()s with no matching %got() or %hi() are better than those | |
11056 | that already have a matching %got() or %hi(). | |
11057 | ||
11058 | (3) later %lo()s are better than earlier %lo()s. | |
11059 | ||
11060 | These rules are applied in order. | |
11061 | ||
11062 | (1) means, among other things, that %lo()s with identical offsets are | |
11063 | chosen if they exist. | |
11064 | ||
11065 | (2) means that we won't associate several high-part relocations with | |
11066 | the same low-part relocation unless there's no alternative. Having | |
11067 | several high parts for the same low part is a GNU extension; this rule | |
11068 | allows careful users to avoid it. | |
11069 | ||
11070 | (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order, | |
11071 | with the last high-part relocation being at the front of the list. | |
11072 | It therefore makes sense to choose the last matching low-part | |
11073 | relocation, all other things being equal. It's also easier | |
11074 | to code that way. */ | |
252b5132 RH |
11075 | |
11076 | void | |
17a2f251 | 11077 | mips_frob_file (void) |
252b5132 RH |
11078 | { |
11079 | struct mips_hi_fixup *l; | |
11080 | ||
11081 | for (l = mips_hi_fixup_list; l != NULL; l = l->next) | |
11082 | { | |
11083 | segment_info_type *seginfo; | |
3b91255e RS |
11084 | bfd_boolean matched_lo_p; |
11085 | fixS **hi_pos, **lo_pos, **pos; | |
252b5132 | 11086 | |
5919d012 | 11087 | assert (reloc_needs_lo_p (l->fixp->fx_r_type)); |
252b5132 | 11088 | |
5919d012 RS |
11089 | /* If a GOT16 relocation turns out to be against a global symbol, |
11090 | there isn't supposed to be a matching LO. */ | |
11091 | if (l->fixp->fx_r_type == BFD_RELOC_MIPS_GOT16 | |
11092 | && !pic_need_relax (l->fixp->fx_addsy, l->seg)) | |
11093 | continue; | |
11094 | ||
11095 | /* Check quickly whether the next fixup happens to be a matching %lo. */ | |
11096 | if (fixup_has_matching_lo_p (l->fixp)) | |
252b5132 RH |
11097 | continue; |
11098 | ||
252b5132 | 11099 | seginfo = seg_info (l->seg); |
252b5132 | 11100 | |
3b91255e RS |
11101 | /* Set HI_POS to the position of this relocation in the chain. |
11102 | Set LO_POS to the position of the chosen low-part relocation. | |
11103 | MATCHED_LO_P is true on entry to the loop if *POS is a low-part | |
11104 | relocation that matches an immediately-preceding high-part | |
11105 | relocation. */ | |
11106 | hi_pos = NULL; | |
11107 | lo_pos = NULL; | |
11108 | matched_lo_p = FALSE; | |
11109 | for (pos = &seginfo->fix_root; *pos != NULL; pos = &(*pos)->fx_next) | |
11110 | { | |
11111 | if (*pos == l->fixp) | |
11112 | hi_pos = pos; | |
11113 | ||
704803a9 MR |
11114 | if (((*pos)->fx_r_type == BFD_RELOC_LO16 |
11115 | || (*pos)->fx_r_type == BFD_RELOC_MIPS16_LO16) | |
3b91255e RS |
11116 | && (*pos)->fx_addsy == l->fixp->fx_addsy |
11117 | && (*pos)->fx_offset >= l->fixp->fx_offset | |
11118 | && (lo_pos == NULL | |
11119 | || (*pos)->fx_offset < (*lo_pos)->fx_offset | |
11120 | || (!matched_lo_p | |
11121 | && (*pos)->fx_offset == (*lo_pos)->fx_offset))) | |
11122 | lo_pos = pos; | |
11123 | ||
11124 | matched_lo_p = (reloc_needs_lo_p ((*pos)->fx_r_type) | |
11125 | && fixup_has_matching_lo_p (*pos)); | |
11126 | } | |
11127 | ||
11128 | /* If we found a match, remove the high-part relocation from its | |
11129 | current position and insert it before the low-part relocation. | |
11130 | Make the offsets match so that fixup_has_matching_lo_p() | |
11131 | will return true. | |
11132 | ||
11133 | We don't warn about unmatched high-part relocations since some | |
11134 | versions of gcc have been known to emit dead "lui ...%hi(...)" | |
11135 | instructions. */ | |
11136 | if (lo_pos != NULL) | |
11137 | { | |
11138 | l->fixp->fx_offset = (*lo_pos)->fx_offset; | |
11139 | if (l->fixp->fx_next != *lo_pos) | |
252b5132 | 11140 | { |
3b91255e RS |
11141 | *hi_pos = l->fixp->fx_next; |
11142 | l->fixp->fx_next = *lo_pos; | |
11143 | *lo_pos = l->fixp; | |
252b5132 | 11144 | } |
252b5132 RH |
11145 | } |
11146 | } | |
11147 | } | |
11148 | ||
3e722fb5 | 11149 | /* We may have combined relocations without symbols in the N32/N64 ABI. |
f6688943 | 11150 | We have to prevent gas from dropping them. */ |
252b5132 | 11151 | |
252b5132 | 11152 | int |
17a2f251 | 11153 | mips_force_relocation (fixS *fixp) |
252b5132 | 11154 | { |
ae6063d4 | 11155 | if (generic_force_reloc (fixp)) |
252b5132 RH |
11156 | return 1; |
11157 | ||
f6688943 TS |
11158 | if (HAVE_NEWABI |
11159 | && S_GET_SEGMENT (fixp->fx_addsy) == bfd_abs_section_ptr | |
11160 | && (fixp->fx_r_type == BFD_RELOC_MIPS_SUB | |
11161 | || fixp->fx_r_type == BFD_RELOC_HI16_S | |
11162 | || fixp->fx_r_type == BFD_RELOC_LO16)) | |
11163 | return 1; | |
11164 | ||
3e722fb5 | 11165 | return 0; |
252b5132 RH |
11166 | } |
11167 | ||
45f8dfe8 AO |
11168 | /* This hook is called before a fix is simplified. We don't really |
11169 | decide whether to skip a fix here. Rather, we turn global symbols | |
11170 | used as branch targets into local symbols, such that they undergo | |
11171 | simplification. We can only do this if the symbol is defined and | |
11172 | it is in the same section as the branch. If this doesn't hold, we | |
11173 | emit a better error message than just saying the relocation is not | |
11174 | valid for the selected object format. | |
11175 | ||
11176 | FIXP is the fix-up we're going to try to simplify, SEG is the | |
11177 | segment in which the fix up occurs. The return value should be | |
11178 | non-zero to indicate the fix-up is valid for further | |
11179 | simplifications. */ | |
11180 | ||
11181 | int | |
17a2f251 | 11182 | mips_validate_fix (struct fix *fixP, asection *seg) |
45f8dfe8 AO |
11183 | { |
11184 | /* There's a lot of discussion on whether it should be possible to | |
11185 | use R_MIPS_PC16 to represent branch relocations. The outcome | |
11186 | seems to be that it can, but gas/bfd are very broken in creating | |
11187 | RELA relocations for this, so for now we only accept branches to | |
11188 | symbols in the same section. Anything else is of dubious value, | |
11189 | since there's no guarantee that at link time the symbol would be | |
11190 | in range. Even for branches to local symbols this is arguably | |
11191 | wrong, since it we assume the symbol is not going to be | |
11192 | overridden, which should be possible per ELF library semantics, | |
11193 | but then, there isn't a dynamic relocation that could be used to | |
11194 | this effect, and the target would likely be out of range as well. | |
11195 | ||
11196 | Unfortunately, it seems that there is too much code out there | |
11197 | that relies on branches to symbols that are global to be resolved | |
11198 | as if they were local, like the IRIX tools do, so we do it as | |
11199 | well, but with a warning so that people are reminded to fix their | |
11200 | code. If we ever get back to using R_MIPS_PC16 for branch | |
11201 | targets, this entire block should go away (and probably the | |
11202 | whole function). */ | |
11203 | ||
11204 | if (fixP->fx_r_type == BFD_RELOC_16_PCREL_S2 | |
3e722fb5 CD |
11205 | && ((OUTPUT_FLAVOR == bfd_target_ecoff_flavour |
11206 | || OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
45f8dfe8 AO |
11207 | || bfd_reloc_type_lookup (stdoutput, BFD_RELOC_16_PCREL_S2) == NULL) |
11208 | && fixP->fx_addsy) | |
11209 | { | |
11210 | if (! S_IS_DEFINED (fixP->fx_addsy)) | |
11211 | { | |
11212 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11213 | _("Cannot branch to undefined symbol.")); | |
11214 | /* Avoid any further errors about this fixup. */ | |
11215 | fixP->fx_done = 1; | |
11216 | } | |
11217 | else if (S_GET_SEGMENT (fixP->fx_addsy) != seg) | |
11218 | { | |
11219 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11220 | _("Cannot branch to symbol in another section.")); | |
11221 | fixP->fx_done = 1; | |
11222 | } | |
11223 | else if (S_IS_EXTERNAL (fixP->fx_addsy)) | |
11224 | { | |
11225 | symbolS *sym = fixP->fx_addsy; | |
11226 | ||
115695a8 CD |
11227 | if (mips_pic == SVR4_PIC) |
11228 | as_warn_where (fixP->fx_file, fixP->fx_line, | |
11229 | _("Pretending global symbol used as branch target is local.")); | |
45f8dfe8 AO |
11230 | |
11231 | fixP->fx_addsy = symbol_create (S_GET_NAME (sym), | |
11232 | S_GET_SEGMENT (sym), | |
11233 | S_GET_VALUE (sym), | |
11234 | symbol_get_frag (sym)); | |
11235 | copy_symbol_attributes (fixP->fx_addsy, sym); | |
11236 | S_CLEAR_EXTERNAL (fixP->fx_addsy); | |
11237 | assert (symbol_resolved_p (sym)); | |
11238 | symbol_mark_resolved (fixP->fx_addsy); | |
11239 | } | |
11240 | } | |
11241 | ||
11242 | return 1; | |
11243 | } | |
11244 | ||
252b5132 RH |
11245 | /* Apply a fixup to the object file. */ |
11246 | ||
94f592af | 11247 | void |
55cf6793 | 11248 | md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) |
252b5132 | 11249 | { |
874e8986 | 11250 | bfd_byte *buf; |
98aa84af | 11251 | long insn; |
a7ebbfdf | 11252 | reloc_howto_type *howto; |
252b5132 | 11253 | |
a7ebbfdf TS |
11254 | /* We ignore generic BFD relocations we don't know about. */ |
11255 | howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type); | |
11256 | if (! howto) | |
11257 | return; | |
65551fa4 | 11258 | |
252b5132 RH |
11259 | assert (fixP->fx_size == 4 |
11260 | || fixP->fx_r_type == BFD_RELOC_16 | |
11261 | || fixP->fx_r_type == BFD_RELOC_64 | |
f6688943 TS |
11262 | || fixP->fx_r_type == BFD_RELOC_CTOR |
11263 | || fixP->fx_r_type == BFD_RELOC_MIPS_SUB | |
252b5132 | 11264 | || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
a7ebbfdf | 11265 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY); |
252b5132 | 11266 | |
a7ebbfdf | 11267 | buf = (bfd_byte *) (fixP->fx_frag->fr_literal + fixP->fx_where); |
252b5132 | 11268 | |
3e722fb5 | 11269 | assert (! fixP->fx_pcrel); |
b1dca8ee RS |
11270 | |
11271 | /* Don't treat parts of a composite relocation as done. There are two | |
11272 | reasons for this: | |
11273 | ||
11274 | (1) The second and third parts will be against 0 (RSS_UNDEF) but | |
11275 | should nevertheless be emitted if the first part is. | |
11276 | ||
11277 | (2) In normal usage, composite relocations are never assembly-time | |
11278 | constants. The easiest way of dealing with the pathological | |
11279 | exceptions is to generate a relocation against STN_UNDEF and | |
11280 | leave everything up to the linker. */ | |
11281 | if (fixP->fx_addsy == NULL && fixP->fx_tcbit == 0) | |
252b5132 RH |
11282 | fixP->fx_done = 1; |
11283 | ||
11284 | switch (fixP->fx_r_type) | |
11285 | { | |
3f98094e DJ |
11286 | case BFD_RELOC_MIPS_TLS_GD: |
11287 | case BFD_RELOC_MIPS_TLS_LDM: | |
11288 | case BFD_RELOC_MIPS_TLS_DTPREL_HI16: | |
11289 | case BFD_RELOC_MIPS_TLS_DTPREL_LO16: | |
11290 | case BFD_RELOC_MIPS_TLS_GOTTPREL: | |
11291 | case BFD_RELOC_MIPS_TLS_TPREL_HI16: | |
11292 | case BFD_RELOC_MIPS_TLS_TPREL_LO16: | |
11293 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
11294 | /* fall through */ | |
11295 | ||
252b5132 | 11296 | case BFD_RELOC_MIPS_JMP: |
e369bcce TS |
11297 | case BFD_RELOC_MIPS_SHIFT5: |
11298 | case BFD_RELOC_MIPS_SHIFT6: | |
11299 | case BFD_RELOC_MIPS_GOT_DISP: | |
11300 | case BFD_RELOC_MIPS_GOT_PAGE: | |
11301 | case BFD_RELOC_MIPS_GOT_OFST: | |
11302 | case BFD_RELOC_MIPS_SUB: | |
11303 | case BFD_RELOC_MIPS_INSERT_A: | |
11304 | case BFD_RELOC_MIPS_INSERT_B: | |
11305 | case BFD_RELOC_MIPS_DELETE: | |
11306 | case BFD_RELOC_MIPS_HIGHEST: | |
11307 | case BFD_RELOC_MIPS_HIGHER: | |
11308 | case BFD_RELOC_MIPS_SCN_DISP: | |
11309 | case BFD_RELOC_MIPS_REL16: | |
11310 | case BFD_RELOC_MIPS_RELGOT: | |
11311 | case BFD_RELOC_MIPS_JALR: | |
252b5132 RH |
11312 | case BFD_RELOC_HI16: |
11313 | case BFD_RELOC_HI16_S: | |
cdf6fd85 | 11314 | case BFD_RELOC_GPREL16: |
252b5132 RH |
11315 | case BFD_RELOC_MIPS_LITERAL: |
11316 | case BFD_RELOC_MIPS_CALL16: | |
11317 | case BFD_RELOC_MIPS_GOT16: | |
cdf6fd85 | 11318 | case BFD_RELOC_GPREL32: |
252b5132 RH |
11319 | case BFD_RELOC_MIPS_GOT_HI16: |
11320 | case BFD_RELOC_MIPS_GOT_LO16: | |
11321 | case BFD_RELOC_MIPS_CALL_HI16: | |
11322 | case BFD_RELOC_MIPS_CALL_LO16: | |
11323 | case BFD_RELOC_MIPS16_GPREL: | |
d6f16593 MR |
11324 | case BFD_RELOC_MIPS16_HI16: |
11325 | case BFD_RELOC_MIPS16_HI16_S: | |
3e722fb5 | 11326 | assert (! fixP->fx_pcrel); |
252b5132 RH |
11327 | /* Nothing needed to do. The value comes from the reloc entry */ |
11328 | break; | |
11329 | ||
11330 | case BFD_RELOC_MIPS16_JMP: | |
11331 | /* We currently always generate a reloc against a symbol, which | |
11332 | means that we don't want an addend even if the symbol is | |
11333 | defined. */ | |
a7ebbfdf | 11334 | *valP = 0; |
252b5132 RH |
11335 | break; |
11336 | ||
252b5132 RH |
11337 | case BFD_RELOC_64: |
11338 | /* This is handled like BFD_RELOC_32, but we output a sign | |
11339 | extended value if we are only 32 bits. */ | |
3e722fb5 | 11340 | if (fixP->fx_done) |
252b5132 RH |
11341 | { |
11342 | if (8 <= sizeof (valueT)) | |
2132e3a3 | 11343 | md_number_to_chars ((char *) buf, *valP, 8); |
252b5132 RH |
11344 | else |
11345 | { | |
a7ebbfdf | 11346 | valueT hiv; |
252b5132 | 11347 | |
a7ebbfdf | 11348 | if ((*valP & 0x80000000) != 0) |
252b5132 RH |
11349 | hiv = 0xffffffff; |
11350 | else | |
11351 | hiv = 0; | |
b215186b | 11352 | md_number_to_chars ((char *)(buf + (target_big_endian ? 4 : 0)), |
a7ebbfdf | 11353 | *valP, 4); |
b215186b | 11354 | md_number_to_chars ((char *)(buf + (target_big_endian ? 0 : 4)), |
a7ebbfdf | 11355 | hiv, 4); |
252b5132 RH |
11356 | } |
11357 | } | |
11358 | break; | |
11359 | ||
056350c6 | 11360 | case BFD_RELOC_RVA: |
252b5132 RH |
11361 | case BFD_RELOC_32: |
11362 | /* If we are deleting this reloc entry, we must fill in the | |
11363 | value now. This can happen if we have a .word which is not | |
3e722fb5 CD |
11364 | resolved when it appears but is later defined. */ |
11365 | if (fixP->fx_done) | |
2132e3a3 | 11366 | md_number_to_chars ((char *) buf, *valP, 4); |
252b5132 RH |
11367 | break; |
11368 | ||
11369 | case BFD_RELOC_16: | |
11370 | /* If we are deleting this reloc entry, we must fill in the | |
11371 | value now. */ | |
252b5132 | 11372 | if (fixP->fx_done) |
2132e3a3 | 11373 | md_number_to_chars ((char *) buf, *valP, 2); |
252b5132 RH |
11374 | break; |
11375 | ||
11376 | case BFD_RELOC_LO16: | |
d6f16593 | 11377 | case BFD_RELOC_MIPS16_LO16: |
3e722fb5 CD |
11378 | /* FIXME: Now that embedded-PIC is gone, some of this code/comment |
11379 | may be safe to remove, but if so it's not obvious. */ | |
252b5132 RH |
11380 | /* When handling an embedded PIC switch statement, we can wind |
11381 | up deleting a LO16 reloc. See the 'o' case in mips_ip. */ | |
11382 | if (fixP->fx_done) | |
11383 | { | |
a7ebbfdf | 11384 | if (*valP + 0x8000 > 0xffff) |
252b5132 RH |
11385 | as_bad_where (fixP->fx_file, fixP->fx_line, |
11386 | _("relocation overflow")); | |
252b5132 RH |
11387 | if (target_big_endian) |
11388 | buf += 2; | |
2132e3a3 | 11389 | md_number_to_chars ((char *) buf, *valP, 2); |
252b5132 RH |
11390 | } |
11391 | break; | |
11392 | ||
11393 | case BFD_RELOC_16_PCREL_S2: | |
a7ebbfdf | 11394 | if ((*valP & 0x3) != 0) |
cb56d3d3 | 11395 | as_bad_where (fixP->fx_file, fixP->fx_line, |
a7ebbfdf | 11396 | _("Branch to odd address (%lx)"), (long) *valP); |
cb56d3d3 | 11397 | |
252b5132 RH |
11398 | /* |
11399 | * We need to save the bits in the instruction since fixup_segment() | |
11400 | * might be deleting the relocation entry (i.e., a branch within | |
11401 | * the current segment). | |
11402 | */ | |
a7ebbfdf | 11403 | if (! fixP->fx_done) |
bb2d6cd7 | 11404 | break; |
252b5132 RH |
11405 | |
11406 | /* update old instruction data */ | |
252b5132 RH |
11407 | if (target_big_endian) |
11408 | insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3]; | |
11409 | else | |
11410 | insn = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0]; | |
11411 | ||
a7ebbfdf TS |
11412 | if (*valP + 0x20000 <= 0x3ffff) |
11413 | { | |
11414 | insn |= (*valP >> 2) & 0xffff; | |
2132e3a3 | 11415 | md_number_to_chars ((char *) buf, insn, 4); |
a7ebbfdf TS |
11416 | } |
11417 | else if (mips_pic == NO_PIC | |
11418 | && fixP->fx_done | |
11419 | && fixP->fx_frag->fr_address >= text_section->vma | |
11420 | && (fixP->fx_frag->fr_address | |
587aac4e | 11421 | < text_section->vma + bfd_get_section_size (text_section)) |
a7ebbfdf TS |
11422 | && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */ |
11423 | || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */ | |
11424 | || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */ | |
252b5132 RH |
11425 | { |
11426 | /* The branch offset is too large. If this is an | |
11427 | unconditional branch, and we are not generating PIC code, | |
11428 | we can convert it to an absolute jump instruction. */ | |
a7ebbfdf TS |
11429 | if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */ |
11430 | insn = 0x0c000000; /* jal */ | |
252b5132 | 11431 | else |
a7ebbfdf TS |
11432 | insn = 0x08000000; /* j */ |
11433 | fixP->fx_r_type = BFD_RELOC_MIPS_JMP; | |
11434 | fixP->fx_done = 0; | |
11435 | fixP->fx_addsy = section_symbol (text_section); | |
11436 | *valP += md_pcrel_from (fixP); | |
2132e3a3 | 11437 | md_number_to_chars ((char *) buf, insn, 4); |
a7ebbfdf TS |
11438 | } |
11439 | else | |
11440 | { | |
11441 | /* If we got here, we have branch-relaxation disabled, | |
11442 | and there's nothing we can do to fix this instruction | |
11443 | without turning it into a longer sequence. */ | |
11444 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11445 | _("Branch out of range")); | |
252b5132 | 11446 | } |
252b5132 RH |
11447 | break; |
11448 | ||
11449 | case BFD_RELOC_VTABLE_INHERIT: | |
11450 | fixP->fx_done = 0; | |
11451 | if (fixP->fx_addsy | |
11452 | && !S_IS_DEFINED (fixP->fx_addsy) | |
11453 | && !S_IS_WEAK (fixP->fx_addsy)) | |
11454 | S_SET_WEAK (fixP->fx_addsy); | |
11455 | break; | |
11456 | ||
11457 | case BFD_RELOC_VTABLE_ENTRY: | |
11458 | fixP->fx_done = 0; | |
11459 | break; | |
11460 | ||
11461 | default: | |
11462 | internalError (); | |
11463 | } | |
a7ebbfdf TS |
11464 | |
11465 | /* Remember value for tc_gen_reloc. */ | |
11466 | fixP->fx_addnumber = *valP; | |
252b5132 RH |
11467 | } |
11468 | ||
252b5132 | 11469 | static symbolS * |
17a2f251 | 11470 | get_symbol (void) |
252b5132 RH |
11471 | { |
11472 | int c; | |
11473 | char *name; | |
11474 | symbolS *p; | |
11475 | ||
11476 | name = input_line_pointer; | |
11477 | c = get_symbol_end (); | |
11478 | p = (symbolS *) symbol_find_or_make (name); | |
11479 | *input_line_pointer = c; | |
11480 | return p; | |
11481 | } | |
11482 | ||
11483 | /* Align the current frag to a given power of two. The MIPS assembler | |
11484 | also automatically adjusts any preceding label. */ | |
11485 | ||
11486 | static void | |
17a2f251 | 11487 | mips_align (int to, int fill, symbolS *label) |
252b5132 | 11488 | { |
7d10b47d | 11489 | mips_emit_delays (); |
252b5132 RH |
11490 | frag_align (to, fill, 0); |
11491 | record_alignment (now_seg, to); | |
11492 | if (label != NULL) | |
11493 | { | |
11494 | assert (S_GET_SEGMENT (label) == now_seg); | |
49309057 | 11495 | symbol_set_frag (label, frag_now); |
252b5132 RH |
11496 | S_SET_VALUE (label, (valueT) frag_now_fix ()); |
11497 | } | |
11498 | } | |
11499 | ||
11500 | /* Align to a given power of two. .align 0 turns off the automatic | |
11501 | alignment used by the data creating pseudo-ops. */ | |
11502 | ||
11503 | static void | |
17a2f251 | 11504 | s_align (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
11505 | { |
11506 | register int temp; | |
11507 | register long temp_fill; | |
11508 | long max_alignment = 15; | |
11509 | ||
11510 | /* | |
11511 | ||
67c1ffbe | 11512 | o Note that the assembler pulls down any immediately preceding label |
252b5132 RH |
11513 | to the aligned address. |
11514 | o It's not documented but auto alignment is reinstated by | |
11515 | a .align pseudo instruction. | |
11516 | o Note also that after auto alignment is turned off the mips assembler | |
11517 | issues an error on attempt to assemble an improperly aligned data item. | |
11518 | We don't. | |
11519 | ||
11520 | */ | |
11521 | ||
11522 | temp = get_absolute_expression (); | |
11523 | if (temp > max_alignment) | |
11524 | as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment); | |
11525 | else if (temp < 0) | |
11526 | { | |
11527 | as_warn (_("Alignment negative: 0 assumed.")); | |
11528 | temp = 0; | |
11529 | } | |
11530 | if (*input_line_pointer == ',') | |
11531 | { | |
f9419b05 | 11532 | ++input_line_pointer; |
252b5132 RH |
11533 | temp_fill = get_absolute_expression (); |
11534 | } | |
11535 | else | |
11536 | temp_fill = 0; | |
11537 | if (temp) | |
11538 | { | |
11539 | auto_align = 1; | |
11540 | mips_align (temp, (int) temp_fill, | |
11541 | insn_labels != NULL ? insn_labels->label : NULL); | |
11542 | } | |
11543 | else | |
11544 | { | |
11545 | auto_align = 0; | |
11546 | } | |
11547 | ||
11548 | demand_empty_rest_of_line (); | |
11549 | } | |
11550 | ||
252b5132 | 11551 | static void |
17a2f251 | 11552 | s_change_sec (int sec) |
252b5132 RH |
11553 | { |
11554 | segT seg; | |
11555 | ||
252b5132 RH |
11556 | #ifdef OBJ_ELF |
11557 | /* The ELF backend needs to know that we are changing sections, so | |
11558 | that .previous works correctly. We could do something like check | |
b6ff326e | 11559 | for an obj_section_change_hook macro, but that might be confusing |
252b5132 RH |
11560 | as it would not be appropriate to use it in the section changing |
11561 | functions in read.c, since obj-elf.c intercepts those. FIXME: | |
11562 | This should be cleaner, somehow. */ | |
11563 | obj_elf_section_change_hook (); | |
11564 | #endif | |
11565 | ||
7d10b47d | 11566 | mips_emit_delays (); |
252b5132 RH |
11567 | switch (sec) |
11568 | { | |
11569 | case 't': | |
11570 | s_text (0); | |
11571 | break; | |
11572 | case 'd': | |
11573 | s_data (0); | |
11574 | break; | |
11575 | case 'b': | |
11576 | subseg_set (bss_section, (subsegT) get_absolute_expression ()); | |
11577 | demand_empty_rest_of_line (); | |
11578 | break; | |
11579 | ||
11580 | case 'r': | |
4d0d148d TS |
11581 | seg = subseg_new (RDATA_SECTION_NAME, |
11582 | (subsegT) get_absolute_expression ()); | |
11583 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
252b5132 | 11584 | { |
4d0d148d TS |
11585 | bfd_set_section_flags (stdoutput, seg, (SEC_ALLOC | SEC_LOAD |
11586 | | SEC_READONLY | SEC_RELOC | |
11587 | | SEC_DATA)); | |
11588 | if (strcmp (TARGET_OS, "elf") != 0) | |
11589 | record_alignment (seg, 4); | |
252b5132 | 11590 | } |
4d0d148d | 11591 | demand_empty_rest_of_line (); |
252b5132 RH |
11592 | break; |
11593 | ||
11594 | case 's': | |
4d0d148d TS |
11595 | seg = subseg_new (".sdata", (subsegT) get_absolute_expression ()); |
11596 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
252b5132 | 11597 | { |
4d0d148d TS |
11598 | bfd_set_section_flags (stdoutput, seg, |
11599 | SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA); | |
11600 | if (strcmp (TARGET_OS, "elf") != 0) | |
11601 | record_alignment (seg, 4); | |
252b5132 | 11602 | } |
4d0d148d TS |
11603 | demand_empty_rest_of_line (); |
11604 | break; | |
252b5132 RH |
11605 | } |
11606 | ||
11607 | auto_align = 1; | |
11608 | } | |
b34976b6 | 11609 | |
cca86cc8 | 11610 | void |
17a2f251 | 11611 | s_change_section (int ignore ATTRIBUTE_UNUSED) |
cca86cc8 | 11612 | { |
7ed4a06a | 11613 | #ifdef OBJ_ELF |
cca86cc8 SC |
11614 | char *section_name; |
11615 | char c; | |
684022ea | 11616 | char next_c = 0; |
cca86cc8 SC |
11617 | int section_type; |
11618 | int section_flag; | |
11619 | int section_entry_size; | |
11620 | int section_alignment; | |
b34976b6 | 11621 | |
7ed4a06a TS |
11622 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
11623 | return; | |
11624 | ||
cca86cc8 SC |
11625 | section_name = input_line_pointer; |
11626 | c = get_symbol_end (); | |
a816d1ed AO |
11627 | if (c) |
11628 | next_c = *(input_line_pointer + 1); | |
cca86cc8 | 11629 | |
4cf0dd0d TS |
11630 | /* Do we have .section Name<,"flags">? */ |
11631 | if (c != ',' || (c == ',' && next_c == '"')) | |
cca86cc8 | 11632 | { |
4cf0dd0d TS |
11633 | /* just after name is now '\0'. */ |
11634 | *input_line_pointer = c; | |
cca86cc8 SC |
11635 | input_line_pointer = section_name; |
11636 | obj_elf_section (ignore); | |
11637 | return; | |
11638 | } | |
11639 | input_line_pointer++; | |
11640 | ||
11641 | /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */ | |
11642 | if (c == ',') | |
11643 | section_type = get_absolute_expression (); | |
11644 | else | |
11645 | section_type = 0; | |
11646 | if (*input_line_pointer++ == ',') | |
11647 | section_flag = get_absolute_expression (); | |
11648 | else | |
11649 | section_flag = 0; | |
11650 | if (*input_line_pointer++ == ',') | |
11651 | section_entry_size = get_absolute_expression (); | |
11652 | else | |
11653 | section_entry_size = 0; | |
11654 | if (*input_line_pointer++ == ',') | |
11655 | section_alignment = get_absolute_expression (); | |
11656 | else | |
11657 | section_alignment = 0; | |
11658 | ||
a816d1ed AO |
11659 | section_name = xstrdup (section_name); |
11660 | ||
8ab8a5c8 RS |
11661 | /* When using the generic form of .section (as implemented by obj-elf.c), |
11662 | there's no way to set the section type to SHT_MIPS_DWARF. Users have | |
11663 | traditionally had to fall back on the more common @progbits instead. | |
11664 | ||
11665 | There's nothing really harmful in this, since bfd will correct | |
11666 | SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it | |
11667 | means that, for backwards compatibiltiy, the special_section entries | |
11668 | for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF. | |
11669 | ||
11670 | Even so, we shouldn't force users of the MIPS .section syntax to | |
11671 | incorrectly label the sections as SHT_PROGBITS. The best compromise | |
11672 | seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the | |
11673 | generic type-checking code. */ | |
11674 | if (section_type == SHT_MIPS_DWARF) | |
11675 | section_type = SHT_PROGBITS; | |
11676 | ||
cca86cc8 SC |
11677 | obj_elf_change_section (section_name, section_type, section_flag, |
11678 | section_entry_size, 0, 0, 0); | |
a816d1ed AO |
11679 | |
11680 | if (now_seg->name != section_name) | |
11681 | free (section_name); | |
7ed4a06a | 11682 | #endif /* OBJ_ELF */ |
cca86cc8 | 11683 | } |
252b5132 RH |
11684 | |
11685 | void | |
17a2f251 | 11686 | mips_enable_auto_align (void) |
252b5132 RH |
11687 | { |
11688 | auto_align = 1; | |
11689 | } | |
11690 | ||
11691 | static void | |
17a2f251 | 11692 | s_cons (int log_size) |
252b5132 RH |
11693 | { |
11694 | symbolS *label; | |
11695 | ||
11696 | label = insn_labels != NULL ? insn_labels->label : NULL; | |
7d10b47d | 11697 | mips_emit_delays (); |
252b5132 RH |
11698 | if (log_size > 0 && auto_align) |
11699 | mips_align (log_size, 0, label); | |
11700 | mips_clear_insn_labels (); | |
11701 | cons (1 << log_size); | |
11702 | } | |
11703 | ||
11704 | static void | |
17a2f251 | 11705 | s_float_cons (int type) |
252b5132 RH |
11706 | { |
11707 | symbolS *label; | |
11708 | ||
11709 | label = insn_labels != NULL ? insn_labels->label : NULL; | |
11710 | ||
7d10b47d | 11711 | mips_emit_delays (); |
252b5132 RH |
11712 | |
11713 | if (auto_align) | |
49309057 ILT |
11714 | { |
11715 | if (type == 'd') | |
11716 | mips_align (3, 0, label); | |
11717 | else | |
11718 | mips_align (2, 0, label); | |
11719 | } | |
252b5132 RH |
11720 | |
11721 | mips_clear_insn_labels (); | |
11722 | ||
11723 | float_cons (type); | |
11724 | } | |
11725 | ||
11726 | /* Handle .globl. We need to override it because on Irix 5 you are | |
11727 | permitted to say | |
11728 | .globl foo .text | |
11729 | where foo is an undefined symbol, to mean that foo should be | |
11730 | considered to be the address of a function. */ | |
11731 | ||
11732 | static void | |
17a2f251 | 11733 | s_mips_globl (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
11734 | { |
11735 | char *name; | |
11736 | int c; | |
11737 | symbolS *symbolP; | |
11738 | flagword flag; | |
11739 | ||
8a06b769 | 11740 | do |
252b5132 | 11741 | { |
8a06b769 | 11742 | name = input_line_pointer; |
252b5132 | 11743 | c = get_symbol_end (); |
8a06b769 TS |
11744 | symbolP = symbol_find_or_make (name); |
11745 | S_SET_EXTERNAL (symbolP); | |
11746 | ||
252b5132 | 11747 | *input_line_pointer = c; |
8a06b769 | 11748 | SKIP_WHITESPACE (); |
252b5132 | 11749 | |
8a06b769 TS |
11750 | /* On Irix 5, every global symbol that is not explicitly labelled as |
11751 | being a function is apparently labelled as being an object. */ | |
11752 | flag = BSF_OBJECT; | |
252b5132 | 11753 | |
8a06b769 TS |
11754 | if (!is_end_of_line[(unsigned char) *input_line_pointer] |
11755 | && (*input_line_pointer != ',')) | |
11756 | { | |
11757 | char *secname; | |
11758 | asection *sec; | |
11759 | ||
11760 | secname = input_line_pointer; | |
11761 | c = get_symbol_end (); | |
11762 | sec = bfd_get_section_by_name (stdoutput, secname); | |
11763 | if (sec == NULL) | |
11764 | as_bad (_("%s: no such section"), secname); | |
11765 | *input_line_pointer = c; | |
11766 | ||
11767 | if (sec != NULL && (sec->flags & SEC_CODE) != 0) | |
11768 | flag = BSF_FUNCTION; | |
11769 | } | |
11770 | ||
11771 | symbol_get_bfdsym (symbolP)->flags |= flag; | |
11772 | ||
11773 | c = *input_line_pointer; | |
11774 | if (c == ',') | |
11775 | { | |
11776 | input_line_pointer++; | |
11777 | SKIP_WHITESPACE (); | |
11778 | if (is_end_of_line[(unsigned char) *input_line_pointer]) | |
11779 | c = '\n'; | |
11780 | } | |
11781 | } | |
11782 | while (c == ','); | |
252b5132 | 11783 | |
252b5132 RH |
11784 | demand_empty_rest_of_line (); |
11785 | } | |
11786 | ||
11787 | static void | |
17a2f251 | 11788 | s_option (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
11789 | { |
11790 | char *opt; | |
11791 | char c; | |
11792 | ||
11793 | opt = input_line_pointer; | |
11794 | c = get_symbol_end (); | |
11795 | ||
11796 | if (*opt == 'O') | |
11797 | { | |
11798 | /* FIXME: What does this mean? */ | |
11799 | } | |
11800 | else if (strncmp (opt, "pic", 3) == 0) | |
11801 | { | |
11802 | int i; | |
11803 | ||
11804 | i = atoi (opt + 3); | |
11805 | if (i == 0) | |
11806 | mips_pic = NO_PIC; | |
11807 | else if (i == 2) | |
143d77c5 | 11808 | { |
252b5132 | 11809 | mips_pic = SVR4_PIC; |
143d77c5 EC |
11810 | mips_abicalls = TRUE; |
11811 | } | |
252b5132 RH |
11812 | else |
11813 | as_bad (_(".option pic%d not supported"), i); | |
11814 | ||
4d0d148d | 11815 | if (mips_pic == SVR4_PIC) |
252b5132 RH |
11816 | { |
11817 | if (g_switch_seen && g_switch_value != 0) | |
11818 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
11819 | g_switch_value = 0; | |
11820 | bfd_set_gp_size (stdoutput, 0); | |
11821 | } | |
11822 | } | |
11823 | else | |
11824 | as_warn (_("Unrecognized option \"%s\""), opt); | |
11825 | ||
11826 | *input_line_pointer = c; | |
11827 | demand_empty_rest_of_line (); | |
11828 | } | |
11829 | ||
11830 | /* This structure is used to hold a stack of .set values. */ | |
11831 | ||
e972090a NC |
11832 | struct mips_option_stack |
11833 | { | |
252b5132 RH |
11834 | struct mips_option_stack *next; |
11835 | struct mips_set_options options; | |
11836 | }; | |
11837 | ||
11838 | static struct mips_option_stack *mips_opts_stack; | |
11839 | ||
11840 | /* Handle the .set pseudo-op. */ | |
11841 | ||
11842 | static void | |
17a2f251 | 11843 | s_mipsset (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
11844 | { |
11845 | char *name = input_line_pointer, ch; | |
11846 | ||
11847 | while (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
f9419b05 | 11848 | ++input_line_pointer; |
252b5132 RH |
11849 | ch = *input_line_pointer; |
11850 | *input_line_pointer = '\0'; | |
11851 | ||
11852 | if (strcmp (name, "reorder") == 0) | |
11853 | { | |
7d10b47d RS |
11854 | if (mips_opts.noreorder) |
11855 | end_noreorder (); | |
252b5132 RH |
11856 | } |
11857 | else if (strcmp (name, "noreorder") == 0) | |
11858 | { | |
7d10b47d RS |
11859 | if (!mips_opts.noreorder) |
11860 | start_noreorder (); | |
252b5132 RH |
11861 | } |
11862 | else if (strcmp (name, "at") == 0) | |
11863 | { | |
11864 | mips_opts.noat = 0; | |
11865 | } | |
11866 | else if (strcmp (name, "noat") == 0) | |
11867 | { | |
11868 | mips_opts.noat = 1; | |
11869 | } | |
11870 | else if (strcmp (name, "macro") == 0) | |
11871 | { | |
11872 | mips_opts.warn_about_macros = 0; | |
11873 | } | |
11874 | else if (strcmp (name, "nomacro") == 0) | |
11875 | { | |
11876 | if (mips_opts.noreorder == 0) | |
11877 | as_bad (_("`noreorder' must be set before `nomacro'")); | |
11878 | mips_opts.warn_about_macros = 1; | |
11879 | } | |
11880 | else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0) | |
11881 | { | |
11882 | mips_opts.nomove = 0; | |
11883 | } | |
11884 | else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0) | |
11885 | { | |
11886 | mips_opts.nomove = 1; | |
11887 | } | |
11888 | else if (strcmp (name, "bopt") == 0) | |
11889 | { | |
11890 | mips_opts.nobopt = 0; | |
11891 | } | |
11892 | else if (strcmp (name, "nobopt") == 0) | |
11893 | { | |
11894 | mips_opts.nobopt = 1; | |
11895 | } | |
11896 | else if (strcmp (name, "mips16") == 0 | |
11897 | || strcmp (name, "MIPS-16") == 0) | |
11898 | mips_opts.mips16 = 1; | |
11899 | else if (strcmp (name, "nomips16") == 0 | |
11900 | || strcmp (name, "noMIPS-16") == 0) | |
11901 | mips_opts.mips16 = 0; | |
1f25f5d3 CD |
11902 | else if (strcmp (name, "mips3d") == 0) |
11903 | mips_opts.ase_mips3d = 1; | |
11904 | else if (strcmp (name, "nomips3d") == 0) | |
11905 | mips_opts.ase_mips3d = 0; | |
a4672219 TS |
11906 | else if (strcmp (name, "mdmx") == 0) |
11907 | mips_opts.ase_mdmx = 1; | |
11908 | else if (strcmp (name, "nomdmx") == 0) | |
11909 | mips_opts.ase_mdmx = 0; | |
74cd071d CF |
11910 | else if (strcmp (name, "dsp") == 0) |
11911 | mips_opts.ase_dsp = 1; | |
11912 | else if (strcmp (name, "nodsp") == 0) | |
11913 | mips_opts.ase_dsp = 0; | |
ef2e4d86 CF |
11914 | else if (strcmp (name, "mt") == 0) |
11915 | mips_opts.ase_mt = 1; | |
11916 | else if (strcmp (name, "nomt") == 0) | |
11917 | mips_opts.ase_mt = 0; | |
1a2c1fad | 11918 | else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0) |
252b5132 | 11919 | { |
af7ee8bf | 11920 | int reset = 0; |
252b5132 | 11921 | |
1a2c1fad CD |
11922 | /* Permit the user to change the ISA and architecture on the fly. |
11923 | Needless to say, misuse can cause serious problems. */ | |
81a21e38 | 11924 | if (strcmp (name, "mips0") == 0 || strcmp (name, "arch=default") == 0) |
af7ee8bf CD |
11925 | { |
11926 | reset = 1; | |
11927 | mips_opts.isa = file_mips_isa; | |
1a2c1fad | 11928 | mips_opts.arch = file_mips_arch; |
1a2c1fad CD |
11929 | } |
11930 | else if (strncmp (name, "arch=", 5) == 0) | |
11931 | { | |
11932 | const struct mips_cpu_info *p; | |
11933 | ||
11934 | p = mips_parse_cpu("internal use", name + 5); | |
11935 | if (!p) | |
11936 | as_bad (_("unknown architecture %s"), name + 5); | |
11937 | else | |
11938 | { | |
11939 | mips_opts.arch = p->cpu; | |
11940 | mips_opts.isa = p->isa; | |
11941 | } | |
11942 | } | |
81a21e38 TS |
11943 | else if (strncmp (name, "mips", 4) == 0) |
11944 | { | |
11945 | const struct mips_cpu_info *p; | |
11946 | ||
11947 | p = mips_parse_cpu("internal use", name); | |
11948 | if (!p) | |
11949 | as_bad (_("unknown ISA level %s"), name + 4); | |
11950 | else | |
11951 | { | |
11952 | mips_opts.arch = p->cpu; | |
11953 | mips_opts.isa = p->isa; | |
11954 | } | |
11955 | } | |
af7ee8bf | 11956 | else |
81a21e38 | 11957 | as_bad (_("unknown ISA or architecture %s"), name); |
af7ee8bf CD |
11958 | |
11959 | switch (mips_opts.isa) | |
98d3f06f KH |
11960 | { |
11961 | case 0: | |
98d3f06f | 11962 | break; |
af7ee8bf CD |
11963 | case ISA_MIPS1: |
11964 | case ISA_MIPS2: | |
11965 | case ISA_MIPS32: | |
11966 | case ISA_MIPS32R2: | |
98d3f06f KH |
11967 | mips_opts.gp32 = 1; |
11968 | mips_opts.fp32 = 1; | |
11969 | break; | |
af7ee8bf CD |
11970 | case ISA_MIPS3: |
11971 | case ISA_MIPS4: | |
11972 | case ISA_MIPS5: | |
11973 | case ISA_MIPS64: | |
5f74bc13 | 11974 | case ISA_MIPS64R2: |
98d3f06f KH |
11975 | mips_opts.gp32 = 0; |
11976 | mips_opts.fp32 = 0; | |
11977 | break; | |
11978 | default: | |
11979 | as_bad (_("unknown ISA level %s"), name + 4); | |
11980 | break; | |
11981 | } | |
af7ee8bf | 11982 | if (reset) |
98d3f06f | 11983 | { |
af7ee8bf CD |
11984 | mips_opts.gp32 = file_mips_gp32; |
11985 | mips_opts.fp32 = file_mips_fp32; | |
98d3f06f | 11986 | } |
252b5132 RH |
11987 | } |
11988 | else if (strcmp (name, "autoextend") == 0) | |
11989 | mips_opts.noautoextend = 0; | |
11990 | else if (strcmp (name, "noautoextend") == 0) | |
11991 | mips_opts.noautoextend = 1; | |
11992 | else if (strcmp (name, "push") == 0) | |
11993 | { | |
11994 | struct mips_option_stack *s; | |
11995 | ||
11996 | s = (struct mips_option_stack *) xmalloc (sizeof *s); | |
11997 | s->next = mips_opts_stack; | |
11998 | s->options = mips_opts; | |
11999 | mips_opts_stack = s; | |
12000 | } | |
12001 | else if (strcmp (name, "pop") == 0) | |
12002 | { | |
12003 | struct mips_option_stack *s; | |
12004 | ||
12005 | s = mips_opts_stack; | |
12006 | if (s == NULL) | |
12007 | as_bad (_(".set pop with no .set push")); | |
12008 | else | |
12009 | { | |
12010 | /* If we're changing the reorder mode we need to handle | |
12011 | delay slots correctly. */ | |
12012 | if (s->options.noreorder && ! mips_opts.noreorder) | |
7d10b47d | 12013 | start_noreorder (); |
252b5132 | 12014 | else if (! s->options.noreorder && mips_opts.noreorder) |
7d10b47d | 12015 | end_noreorder (); |
252b5132 RH |
12016 | |
12017 | mips_opts = s->options; | |
12018 | mips_opts_stack = s->next; | |
12019 | free (s); | |
12020 | } | |
12021 | } | |
aed1a261 RS |
12022 | else if (strcmp (name, "sym32") == 0) |
12023 | mips_opts.sym32 = TRUE; | |
12024 | else if (strcmp (name, "nosym32") == 0) | |
12025 | mips_opts.sym32 = FALSE; | |
252b5132 RH |
12026 | else |
12027 | { | |
12028 | as_warn (_("Tried to set unrecognized symbol: %s\n"), name); | |
12029 | } | |
12030 | *input_line_pointer = ch; | |
12031 | demand_empty_rest_of_line (); | |
12032 | } | |
12033 | ||
12034 | /* Handle the .abicalls pseudo-op. I believe this is equivalent to | |
12035 | .option pic2. It means to generate SVR4 PIC calls. */ | |
12036 | ||
12037 | static void | |
17a2f251 | 12038 | s_abicalls (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
12039 | { |
12040 | mips_pic = SVR4_PIC; | |
143d77c5 | 12041 | mips_abicalls = TRUE; |
4d0d148d TS |
12042 | |
12043 | if (g_switch_seen && g_switch_value != 0) | |
12044 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
12045 | g_switch_value = 0; | |
12046 | ||
252b5132 RH |
12047 | bfd_set_gp_size (stdoutput, 0); |
12048 | demand_empty_rest_of_line (); | |
12049 | } | |
12050 | ||
12051 | /* Handle the .cpload pseudo-op. This is used when generating SVR4 | |
12052 | PIC code. It sets the $gp register for the function based on the | |
12053 | function address, which is in the register named in the argument. | |
12054 | This uses a relocation against _gp_disp, which is handled specially | |
12055 | by the linker. The result is: | |
12056 | lui $gp,%hi(_gp_disp) | |
12057 | addiu $gp,$gp,%lo(_gp_disp) | |
12058 | addu $gp,$gp,.cpload argument | |
aa6975fb ILT |
12059 | The .cpload argument is normally $25 == $t9. |
12060 | ||
12061 | The -mno-shared option changes this to: | |
bbe506e8 TS |
12062 | lui $gp,%hi(__gnu_local_gp) |
12063 | addiu $gp,$gp,%lo(__gnu_local_gp) | |
aa6975fb ILT |
12064 | and the argument is ignored. This saves an instruction, but the |
12065 | resulting code is not position independent; it uses an absolute | |
bbe506e8 TS |
12066 | address for __gnu_local_gp. Thus code assembled with -mno-shared |
12067 | can go into an ordinary executable, but not into a shared library. */ | |
252b5132 RH |
12068 | |
12069 | static void | |
17a2f251 | 12070 | s_cpload (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
12071 | { |
12072 | expressionS ex; | |
aa6975fb ILT |
12073 | int reg; |
12074 | int in_shared; | |
252b5132 | 12075 | |
6478892d TS |
12076 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
12077 | .cpload is ignored. */ | |
12078 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) | |
252b5132 RH |
12079 | { |
12080 | s_ignore (0); | |
12081 | return; | |
12082 | } | |
12083 | ||
d3ecfc59 | 12084 | /* .cpload should be in a .set noreorder section. */ |
252b5132 RH |
12085 | if (mips_opts.noreorder == 0) |
12086 | as_warn (_(".cpload not in noreorder section")); | |
12087 | ||
aa6975fb ILT |
12088 | reg = tc_get_register (0); |
12089 | ||
12090 | /* If we need to produce a 64-bit address, we are better off using | |
12091 | the default instruction sequence. */ | |
aed1a261 | 12092 | in_shared = mips_in_shared || HAVE_64BIT_SYMBOLS; |
aa6975fb | 12093 | |
252b5132 | 12094 | ex.X_op = O_symbol; |
bbe506e8 TS |
12095 | ex.X_add_symbol = symbol_find_or_make (in_shared ? "_gp_disp" : |
12096 | "__gnu_local_gp"); | |
252b5132 RH |
12097 | ex.X_op_symbol = NULL; |
12098 | ex.X_add_number = 0; | |
12099 | ||
12100 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ | |
49309057 | 12101 | symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; |
252b5132 | 12102 | |
584892a6 | 12103 | macro_start (); |
67c0d1eb RS |
12104 | macro_build_lui (&ex, mips_gp_register); |
12105 | macro_build (&ex, "addiu", "t,r,j", mips_gp_register, | |
17a2f251 | 12106 | mips_gp_register, BFD_RELOC_LO16); |
aa6975fb ILT |
12107 | if (in_shared) |
12108 | macro_build (NULL, "addu", "d,v,t", mips_gp_register, | |
12109 | mips_gp_register, reg); | |
584892a6 | 12110 | macro_end (); |
252b5132 RH |
12111 | |
12112 | demand_empty_rest_of_line (); | |
12113 | } | |
12114 | ||
6478892d TS |
12115 | /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is: |
12116 | .cpsetup $reg1, offset|$reg2, label | |
12117 | ||
12118 | If offset is given, this results in: | |
12119 | sd $gp, offset($sp) | |
956cd1d6 | 12120 | lui $gp, %hi(%neg(%gp_rel(label))) |
698b7d9d TS |
12121 | addiu $gp, $gp, %lo(%neg(%gp_rel(label))) |
12122 | daddu $gp, $gp, $reg1 | |
6478892d TS |
12123 | |
12124 | If $reg2 is given, this results in: | |
12125 | daddu $reg2, $gp, $0 | |
956cd1d6 | 12126 | lui $gp, %hi(%neg(%gp_rel(label))) |
698b7d9d TS |
12127 | addiu $gp, $gp, %lo(%neg(%gp_rel(label))) |
12128 | daddu $gp, $gp, $reg1 | |
aa6975fb ILT |
12129 | $reg1 is normally $25 == $t9. |
12130 | ||
12131 | The -mno-shared option replaces the last three instructions with | |
12132 | lui $gp,%hi(_gp) | |
12133 | addiu $gp,$gp,%lo(_gp) | |
12134 | */ | |
12135 | ||
6478892d | 12136 | static void |
17a2f251 | 12137 | s_cpsetup (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
12138 | { |
12139 | expressionS ex_off; | |
12140 | expressionS ex_sym; | |
12141 | int reg1; | |
6478892d | 12142 | |
8586fc66 | 12143 | /* If we are not generating SVR4 PIC code, .cpsetup is ignored. |
6478892d TS |
12144 | We also need NewABI support. */ |
12145 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
12146 | { | |
12147 | s_ignore (0); | |
12148 | return; | |
12149 | } | |
12150 | ||
12151 | reg1 = tc_get_register (0); | |
12152 | SKIP_WHITESPACE (); | |
12153 | if (*input_line_pointer != ',') | |
12154 | { | |
12155 | as_bad (_("missing argument separator ',' for .cpsetup")); | |
12156 | return; | |
12157 | } | |
12158 | else | |
80245285 | 12159 | ++input_line_pointer; |
6478892d TS |
12160 | SKIP_WHITESPACE (); |
12161 | if (*input_line_pointer == '$') | |
80245285 TS |
12162 | { |
12163 | mips_cpreturn_register = tc_get_register (0); | |
12164 | mips_cpreturn_offset = -1; | |
12165 | } | |
6478892d | 12166 | else |
80245285 TS |
12167 | { |
12168 | mips_cpreturn_offset = get_absolute_expression (); | |
12169 | mips_cpreturn_register = -1; | |
12170 | } | |
6478892d TS |
12171 | SKIP_WHITESPACE (); |
12172 | if (*input_line_pointer != ',') | |
12173 | { | |
12174 | as_bad (_("missing argument separator ',' for .cpsetup")); | |
12175 | return; | |
12176 | } | |
12177 | else | |
f9419b05 | 12178 | ++input_line_pointer; |
6478892d | 12179 | SKIP_WHITESPACE (); |
f21f8242 | 12180 | expression (&ex_sym); |
6478892d | 12181 | |
584892a6 | 12182 | macro_start (); |
6478892d TS |
12183 | if (mips_cpreturn_register == -1) |
12184 | { | |
12185 | ex_off.X_op = O_constant; | |
12186 | ex_off.X_add_symbol = NULL; | |
12187 | ex_off.X_op_symbol = NULL; | |
12188 | ex_off.X_add_number = mips_cpreturn_offset; | |
12189 | ||
67c0d1eb | 12190 | macro_build (&ex_off, "sd", "t,o(b)", mips_gp_register, |
17a2f251 | 12191 | BFD_RELOC_LO16, SP); |
6478892d TS |
12192 | } |
12193 | else | |
67c0d1eb | 12194 | macro_build (NULL, "daddu", "d,v,t", mips_cpreturn_register, |
17a2f251 | 12195 | mips_gp_register, 0); |
6478892d | 12196 | |
aed1a261 | 12197 | if (mips_in_shared || HAVE_64BIT_SYMBOLS) |
aa6975fb ILT |
12198 | { |
12199 | macro_build (&ex_sym, "lui", "t,u", mips_gp_register, | |
12200 | -1, BFD_RELOC_GPREL16, BFD_RELOC_MIPS_SUB, | |
12201 | BFD_RELOC_HI16_S); | |
12202 | ||
12203 | macro_build (&ex_sym, "addiu", "t,r,j", mips_gp_register, | |
12204 | mips_gp_register, -1, BFD_RELOC_GPREL16, | |
12205 | BFD_RELOC_MIPS_SUB, BFD_RELOC_LO16); | |
12206 | ||
12207 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register, | |
12208 | mips_gp_register, reg1); | |
12209 | } | |
12210 | else | |
12211 | { | |
12212 | expressionS ex; | |
12213 | ||
12214 | ex.X_op = O_symbol; | |
4184909a | 12215 | ex.X_add_symbol = symbol_find_or_make ("__gnu_local_gp"); |
aa6975fb ILT |
12216 | ex.X_op_symbol = NULL; |
12217 | ex.X_add_number = 0; | |
6e1304d8 | 12218 | |
aa6975fb ILT |
12219 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ |
12220 | symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; | |
12221 | ||
12222 | macro_build_lui (&ex, mips_gp_register); | |
12223 | macro_build (&ex, "addiu", "t,r,j", mips_gp_register, | |
12224 | mips_gp_register, BFD_RELOC_LO16); | |
12225 | } | |
f21f8242 | 12226 | |
584892a6 | 12227 | macro_end (); |
6478892d TS |
12228 | |
12229 | demand_empty_rest_of_line (); | |
12230 | } | |
12231 | ||
12232 | static void | |
17a2f251 | 12233 | s_cplocal (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
12234 | { |
12235 | /* If we are not generating SVR4 PIC code, or if this is not NewABI code, | |
12236 | .cplocal is ignored. */ | |
12237 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
12238 | { | |
12239 | s_ignore (0); | |
12240 | return; | |
12241 | } | |
12242 | ||
12243 | mips_gp_register = tc_get_register (0); | |
85b51719 | 12244 | demand_empty_rest_of_line (); |
6478892d TS |
12245 | } |
12246 | ||
252b5132 RH |
12247 | /* Handle the .cprestore pseudo-op. This stores $gp into a given |
12248 | offset from $sp. The offset is remembered, and after making a PIC | |
12249 | call $gp is restored from that location. */ | |
12250 | ||
12251 | static void | |
17a2f251 | 12252 | s_cprestore (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
12253 | { |
12254 | expressionS ex; | |
252b5132 | 12255 | |
6478892d | 12256 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
c9914766 | 12257 | .cprestore is ignored. */ |
6478892d | 12258 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) |
252b5132 RH |
12259 | { |
12260 | s_ignore (0); | |
12261 | return; | |
12262 | } | |
12263 | ||
12264 | mips_cprestore_offset = get_absolute_expression (); | |
7a621144 | 12265 | mips_cprestore_valid = 1; |
252b5132 RH |
12266 | |
12267 | ex.X_op = O_constant; | |
12268 | ex.X_add_symbol = NULL; | |
12269 | ex.X_op_symbol = NULL; | |
12270 | ex.X_add_number = mips_cprestore_offset; | |
12271 | ||
584892a6 | 12272 | macro_start (); |
67c0d1eb RS |
12273 | macro_build_ldst_constoffset (&ex, ADDRESS_STORE_INSN, mips_gp_register, |
12274 | SP, HAVE_64BIT_ADDRESSES); | |
584892a6 | 12275 | macro_end (); |
252b5132 RH |
12276 | |
12277 | demand_empty_rest_of_line (); | |
12278 | } | |
12279 | ||
6478892d | 12280 | /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset |
67c1ffbe | 12281 | was given in the preceding .cpsetup, it results in: |
6478892d | 12282 | ld $gp, offset($sp) |
76b3015f | 12283 | |
6478892d | 12284 | If a register $reg2 was given there, it results in: |
609f23f4 | 12285 | daddu $gp, $reg2, $0 |
6478892d TS |
12286 | */ |
12287 | static void | |
17a2f251 | 12288 | s_cpreturn (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
12289 | { |
12290 | expressionS ex; | |
6478892d TS |
12291 | |
12292 | /* If we are not generating SVR4 PIC code, .cpreturn is ignored. | |
12293 | We also need NewABI support. */ | |
12294 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
12295 | { | |
12296 | s_ignore (0); | |
12297 | return; | |
12298 | } | |
12299 | ||
584892a6 | 12300 | macro_start (); |
6478892d TS |
12301 | if (mips_cpreturn_register == -1) |
12302 | { | |
12303 | ex.X_op = O_constant; | |
12304 | ex.X_add_symbol = NULL; | |
12305 | ex.X_op_symbol = NULL; | |
12306 | ex.X_add_number = mips_cpreturn_offset; | |
12307 | ||
67c0d1eb | 12308 | macro_build (&ex, "ld", "t,o(b)", mips_gp_register, BFD_RELOC_LO16, SP); |
6478892d TS |
12309 | } |
12310 | else | |
67c0d1eb | 12311 | macro_build (NULL, "daddu", "d,v,t", mips_gp_register, |
17a2f251 | 12312 | mips_cpreturn_register, 0); |
584892a6 | 12313 | macro_end (); |
6478892d TS |
12314 | |
12315 | demand_empty_rest_of_line (); | |
12316 | } | |
12317 | ||
12318 | /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC | |
12319 | code. It sets the offset to use in gp_rel relocations. */ | |
12320 | ||
12321 | static void | |
17a2f251 | 12322 | s_gpvalue (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
12323 | { |
12324 | /* If we are not generating SVR4 PIC code, .gpvalue is ignored. | |
12325 | We also need NewABI support. */ | |
12326 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
12327 | { | |
12328 | s_ignore (0); | |
12329 | return; | |
12330 | } | |
12331 | ||
def2e0dd | 12332 | mips_gprel_offset = get_absolute_expression (); |
6478892d TS |
12333 | |
12334 | demand_empty_rest_of_line (); | |
12335 | } | |
12336 | ||
252b5132 RH |
12337 | /* Handle the .gpword pseudo-op. This is used when generating PIC |
12338 | code. It generates a 32 bit GP relative reloc. */ | |
12339 | ||
12340 | static void | |
17a2f251 | 12341 | s_gpword (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
12342 | { |
12343 | symbolS *label; | |
12344 | expressionS ex; | |
12345 | char *p; | |
12346 | ||
12347 | /* When not generating PIC code, this is treated as .word. */ | |
12348 | if (mips_pic != SVR4_PIC) | |
12349 | { | |
12350 | s_cons (2); | |
12351 | return; | |
12352 | } | |
12353 | ||
12354 | label = insn_labels != NULL ? insn_labels->label : NULL; | |
7d10b47d | 12355 | mips_emit_delays (); |
252b5132 RH |
12356 | if (auto_align) |
12357 | mips_align (2, 0, label); | |
12358 | mips_clear_insn_labels (); | |
12359 | ||
12360 | expression (&ex); | |
12361 | ||
12362 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
12363 | { | |
12364 | as_bad (_("Unsupported use of .gpword")); | |
12365 | ignore_rest_of_line (); | |
12366 | } | |
12367 | ||
12368 | p = frag_more (4); | |
17a2f251 | 12369 | md_number_to_chars (p, 0, 4); |
b34976b6 | 12370 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, |
cdf6fd85 | 12371 | BFD_RELOC_GPREL32); |
252b5132 RH |
12372 | |
12373 | demand_empty_rest_of_line (); | |
12374 | } | |
12375 | ||
10181a0d | 12376 | static void |
17a2f251 | 12377 | s_gpdword (int ignore ATTRIBUTE_UNUSED) |
10181a0d AO |
12378 | { |
12379 | symbolS *label; | |
12380 | expressionS ex; | |
12381 | char *p; | |
12382 | ||
12383 | /* When not generating PIC code, this is treated as .dword. */ | |
12384 | if (mips_pic != SVR4_PIC) | |
12385 | { | |
12386 | s_cons (3); | |
12387 | return; | |
12388 | } | |
12389 | ||
12390 | label = insn_labels != NULL ? insn_labels->label : NULL; | |
7d10b47d | 12391 | mips_emit_delays (); |
10181a0d AO |
12392 | if (auto_align) |
12393 | mips_align (3, 0, label); | |
12394 | mips_clear_insn_labels (); | |
12395 | ||
12396 | expression (&ex); | |
12397 | ||
12398 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
12399 | { | |
12400 | as_bad (_("Unsupported use of .gpdword")); | |
12401 | ignore_rest_of_line (); | |
12402 | } | |
12403 | ||
12404 | p = frag_more (8); | |
17a2f251 | 12405 | md_number_to_chars (p, 0, 8); |
a105a300 | 12406 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, |
6e1304d8 | 12407 | BFD_RELOC_GPREL32)->fx_tcbit = 1; |
10181a0d AO |
12408 | |
12409 | /* GPREL32 composed with 64 gives a 64-bit GP offset. */ | |
6e1304d8 RS |
12410 | fix_new (frag_now, p - frag_now->fr_literal, 8, NULL, 0, |
12411 | FALSE, BFD_RELOC_64)->fx_tcbit = 1; | |
10181a0d AO |
12412 | |
12413 | demand_empty_rest_of_line (); | |
12414 | } | |
12415 | ||
252b5132 RH |
12416 | /* Handle the .cpadd pseudo-op. This is used when dealing with switch |
12417 | tables in SVR4 PIC code. */ | |
12418 | ||
12419 | static void | |
17a2f251 | 12420 | s_cpadd (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 12421 | { |
252b5132 RH |
12422 | int reg; |
12423 | ||
10181a0d AO |
12424 | /* This is ignored when not generating SVR4 PIC code. */ |
12425 | if (mips_pic != SVR4_PIC) | |
252b5132 RH |
12426 | { |
12427 | s_ignore (0); | |
12428 | return; | |
12429 | } | |
12430 | ||
12431 | /* Add $gp to the register named as an argument. */ | |
584892a6 | 12432 | macro_start (); |
252b5132 | 12433 | reg = tc_get_register (0); |
67c0d1eb | 12434 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register); |
584892a6 | 12435 | macro_end (); |
252b5132 | 12436 | |
bdaaa2e1 | 12437 | demand_empty_rest_of_line (); |
252b5132 RH |
12438 | } |
12439 | ||
12440 | /* Handle the .insn pseudo-op. This marks instruction labels in | |
12441 | mips16 mode. This permits the linker to handle them specially, | |
12442 | such as generating jalx instructions when needed. We also make | |
12443 | them odd for the duration of the assembly, in order to generate the | |
12444 | right sort of code. We will make them even in the adjust_symtab | |
12445 | routine, while leaving them marked. This is convenient for the | |
12446 | debugger and the disassembler. The linker knows to make them odd | |
12447 | again. */ | |
12448 | ||
12449 | static void | |
17a2f251 | 12450 | s_insn (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 12451 | { |
f9419b05 | 12452 | mips16_mark_labels (); |
252b5132 RH |
12453 | |
12454 | demand_empty_rest_of_line (); | |
12455 | } | |
12456 | ||
12457 | /* Handle a .stabn directive. We need these in order to mark a label | |
12458 | as being a mips16 text label correctly. Sometimes the compiler | |
12459 | will emit a label, followed by a .stabn, and then switch sections. | |
12460 | If the label and .stabn are in mips16 mode, then the label is | |
12461 | really a mips16 text label. */ | |
12462 | ||
12463 | static void | |
17a2f251 | 12464 | s_mips_stab (int type) |
252b5132 | 12465 | { |
f9419b05 | 12466 | if (type == 'n') |
252b5132 RH |
12467 | mips16_mark_labels (); |
12468 | ||
12469 | s_stab (type); | |
12470 | } | |
12471 | ||
12472 | /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. | |
12473 | */ | |
12474 | ||
12475 | static void | |
17a2f251 | 12476 | s_mips_weakext (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
12477 | { |
12478 | char *name; | |
12479 | int c; | |
12480 | symbolS *symbolP; | |
12481 | expressionS exp; | |
12482 | ||
12483 | name = input_line_pointer; | |
12484 | c = get_symbol_end (); | |
12485 | symbolP = symbol_find_or_make (name); | |
12486 | S_SET_WEAK (symbolP); | |
12487 | *input_line_pointer = c; | |
12488 | ||
12489 | SKIP_WHITESPACE (); | |
12490 | ||
12491 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
12492 | { | |
12493 | if (S_IS_DEFINED (symbolP)) | |
12494 | { | |
956cd1d6 | 12495 | as_bad ("ignoring attempt to redefine symbol %s", |
252b5132 RH |
12496 | S_GET_NAME (symbolP)); |
12497 | ignore_rest_of_line (); | |
12498 | return; | |
12499 | } | |
bdaaa2e1 | 12500 | |
252b5132 RH |
12501 | if (*input_line_pointer == ',') |
12502 | { | |
12503 | ++input_line_pointer; | |
12504 | SKIP_WHITESPACE (); | |
12505 | } | |
bdaaa2e1 | 12506 | |
252b5132 RH |
12507 | expression (&exp); |
12508 | if (exp.X_op != O_symbol) | |
12509 | { | |
12510 | as_bad ("bad .weakext directive"); | |
98d3f06f | 12511 | ignore_rest_of_line (); |
252b5132 RH |
12512 | return; |
12513 | } | |
49309057 | 12514 | symbol_set_value_expression (symbolP, &exp); |
252b5132 RH |
12515 | } |
12516 | ||
12517 | demand_empty_rest_of_line (); | |
12518 | } | |
12519 | ||
12520 | /* Parse a register string into a number. Called from the ECOFF code | |
12521 | to parse .frame. The argument is non-zero if this is the frame | |
12522 | register, so that we can record it in mips_frame_reg. */ | |
12523 | ||
12524 | int | |
17a2f251 | 12525 | tc_get_register (int frame) |
252b5132 RH |
12526 | { |
12527 | int reg; | |
12528 | ||
12529 | SKIP_WHITESPACE (); | |
12530 | if (*input_line_pointer++ != '$') | |
12531 | { | |
12532 | as_warn (_("expected `$'")); | |
85b51719 | 12533 | reg = ZERO; |
252b5132 | 12534 | } |
3882b010 | 12535 | else if (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
12536 | { |
12537 | reg = get_absolute_expression (); | |
12538 | if (reg < 0 || reg >= 32) | |
12539 | { | |
12540 | as_warn (_("Bad register number")); | |
85b51719 | 12541 | reg = ZERO; |
252b5132 RH |
12542 | } |
12543 | } | |
12544 | else | |
12545 | { | |
76db943d | 12546 | if (strncmp (input_line_pointer, "ra", 2) == 0) |
85b51719 TS |
12547 | { |
12548 | reg = RA; | |
12549 | input_line_pointer += 2; | |
12550 | } | |
76db943d | 12551 | else if (strncmp (input_line_pointer, "fp", 2) == 0) |
85b51719 TS |
12552 | { |
12553 | reg = FP; | |
12554 | input_line_pointer += 2; | |
12555 | } | |
252b5132 | 12556 | else if (strncmp (input_line_pointer, "sp", 2) == 0) |
85b51719 TS |
12557 | { |
12558 | reg = SP; | |
12559 | input_line_pointer += 2; | |
12560 | } | |
252b5132 | 12561 | else if (strncmp (input_line_pointer, "gp", 2) == 0) |
85b51719 TS |
12562 | { |
12563 | reg = GP; | |
12564 | input_line_pointer += 2; | |
12565 | } | |
252b5132 | 12566 | else if (strncmp (input_line_pointer, "at", 2) == 0) |
85b51719 TS |
12567 | { |
12568 | reg = AT; | |
12569 | input_line_pointer += 2; | |
12570 | } | |
12571 | else if (strncmp (input_line_pointer, "kt0", 3) == 0) | |
12572 | { | |
12573 | reg = KT0; | |
12574 | input_line_pointer += 3; | |
12575 | } | |
12576 | else if (strncmp (input_line_pointer, "kt1", 3) == 0) | |
12577 | { | |
12578 | reg = KT1; | |
12579 | input_line_pointer += 3; | |
12580 | } | |
12581 | else if (strncmp (input_line_pointer, "zero", 4) == 0) | |
12582 | { | |
12583 | reg = ZERO; | |
12584 | input_line_pointer += 4; | |
12585 | } | |
252b5132 RH |
12586 | else |
12587 | { | |
12588 | as_warn (_("Unrecognized register name")); | |
85b51719 TS |
12589 | reg = ZERO; |
12590 | while (ISALNUM(*input_line_pointer)) | |
12591 | input_line_pointer++; | |
252b5132 | 12592 | } |
252b5132 RH |
12593 | } |
12594 | if (frame) | |
7a621144 DJ |
12595 | { |
12596 | mips_frame_reg = reg != 0 ? reg : SP; | |
12597 | mips_frame_reg_valid = 1; | |
12598 | mips_cprestore_valid = 0; | |
12599 | } | |
252b5132 RH |
12600 | return reg; |
12601 | } | |
12602 | ||
12603 | valueT | |
17a2f251 | 12604 | md_section_align (asection *seg, valueT addr) |
252b5132 RH |
12605 | { |
12606 | int align = bfd_get_section_alignment (stdoutput, seg); | |
12607 | ||
12608 | #ifdef OBJ_ELF | |
12609 | /* We don't need to align ELF sections to the full alignment. | |
12610 | However, Irix 5 may prefer that we align them at least to a 16 | |
12611 | byte boundary. We don't bother to align the sections if we are | |
12612 | targeted for an embedded system. */ | |
12613 | if (strcmp (TARGET_OS, "elf") == 0) | |
12614 | return addr; | |
12615 | if (align > 4) | |
12616 | align = 4; | |
12617 | #endif | |
12618 | ||
12619 | return ((addr + (1 << align) - 1) & (-1 << align)); | |
12620 | } | |
12621 | ||
12622 | /* Utility routine, called from above as well. If called while the | |
12623 | input file is still being read, it's only an approximation. (For | |
12624 | example, a symbol may later become defined which appeared to be | |
12625 | undefined earlier.) */ | |
12626 | ||
12627 | static int | |
17a2f251 | 12628 | nopic_need_relax (symbolS *sym, int before_relaxing) |
252b5132 RH |
12629 | { |
12630 | if (sym == 0) | |
12631 | return 0; | |
12632 | ||
4d0d148d | 12633 | if (g_switch_value > 0) |
252b5132 RH |
12634 | { |
12635 | const char *symname; | |
12636 | int change; | |
12637 | ||
c9914766 | 12638 | /* Find out whether this symbol can be referenced off the $gp |
252b5132 RH |
12639 | register. It can be if it is smaller than the -G size or if |
12640 | it is in the .sdata or .sbss section. Certain symbols can | |
c9914766 | 12641 | not be referenced off the $gp, although it appears as though |
252b5132 RH |
12642 | they can. */ |
12643 | symname = S_GET_NAME (sym); | |
12644 | if (symname != (const char *) NULL | |
12645 | && (strcmp (symname, "eprol") == 0 | |
12646 | || strcmp (symname, "etext") == 0 | |
12647 | || strcmp (symname, "_gp") == 0 | |
12648 | || strcmp (symname, "edata") == 0 | |
12649 | || strcmp (symname, "_fbss") == 0 | |
12650 | || strcmp (symname, "_fdata") == 0 | |
12651 | || strcmp (symname, "_ftext") == 0 | |
12652 | || strcmp (symname, "end") == 0 | |
12653 | || strcmp (symname, "_gp_disp") == 0)) | |
12654 | change = 1; | |
12655 | else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym)) | |
12656 | && (0 | |
12657 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 ILT |
12658 | || (symbol_get_obj (sym)->ecoff_extern_size != 0 |
12659 | && (symbol_get_obj (sym)->ecoff_extern_size | |
12660 | <= g_switch_value)) | |
252b5132 RH |
12661 | #endif |
12662 | /* We must defer this decision until after the whole | |
12663 | file has been read, since there might be a .extern | |
12664 | after the first use of this symbol. */ | |
12665 | || (before_relaxing | |
12666 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 | 12667 | && symbol_get_obj (sym)->ecoff_extern_size == 0 |
252b5132 RH |
12668 | #endif |
12669 | && S_GET_VALUE (sym) == 0) | |
12670 | || (S_GET_VALUE (sym) != 0 | |
12671 | && S_GET_VALUE (sym) <= g_switch_value))) | |
12672 | change = 0; | |
12673 | else | |
12674 | { | |
12675 | const char *segname; | |
12676 | ||
12677 | segname = segment_name (S_GET_SEGMENT (sym)); | |
12678 | assert (strcmp (segname, ".lit8") != 0 | |
12679 | && strcmp (segname, ".lit4") != 0); | |
12680 | change = (strcmp (segname, ".sdata") != 0 | |
fba2b7f9 GK |
12681 | && strcmp (segname, ".sbss") != 0 |
12682 | && strncmp (segname, ".sdata.", 7) != 0 | |
12683 | && strncmp (segname, ".gnu.linkonce.s.", 16) != 0); | |
252b5132 RH |
12684 | } |
12685 | return change; | |
12686 | } | |
12687 | else | |
c9914766 | 12688 | /* We are not optimizing for the $gp register. */ |
252b5132 RH |
12689 | return 1; |
12690 | } | |
12691 | ||
5919d012 RS |
12692 | |
12693 | /* Return true if the given symbol should be considered local for SVR4 PIC. */ | |
12694 | ||
12695 | static bfd_boolean | |
17a2f251 | 12696 | pic_need_relax (symbolS *sym, asection *segtype) |
5919d012 RS |
12697 | { |
12698 | asection *symsec; | |
12699 | bfd_boolean linkonce; | |
12700 | ||
12701 | /* Handle the case of a symbol equated to another symbol. */ | |
12702 | while (symbol_equated_reloc_p (sym)) | |
12703 | { | |
12704 | symbolS *n; | |
12705 | ||
12706 | /* It's possible to get a loop here in a badly written | |
12707 | program. */ | |
12708 | n = symbol_get_value_expression (sym)->X_add_symbol; | |
12709 | if (n == sym) | |
12710 | break; | |
12711 | sym = n; | |
12712 | } | |
12713 | ||
12714 | symsec = S_GET_SEGMENT (sym); | |
12715 | ||
12716 | /* duplicate the test for LINK_ONCE sections as in adjust_reloc_syms */ | |
12717 | linkonce = FALSE; | |
12718 | if (symsec != segtype && ! S_IS_LOCAL (sym)) | |
12719 | { | |
12720 | if ((bfd_get_section_flags (stdoutput, symsec) & SEC_LINK_ONCE) | |
12721 | != 0) | |
12722 | linkonce = TRUE; | |
12723 | ||
12724 | /* The GNU toolchain uses an extension for ELF: a section | |
12725 | beginning with the magic string .gnu.linkonce is a linkonce | |
12726 | section. */ | |
12727 | if (strncmp (segment_name (symsec), ".gnu.linkonce", | |
12728 | sizeof ".gnu.linkonce" - 1) == 0) | |
12729 | linkonce = TRUE; | |
12730 | } | |
12731 | ||
12732 | /* This must duplicate the test in adjust_reloc_syms. */ | |
12733 | return (symsec != &bfd_und_section | |
12734 | && symsec != &bfd_abs_section | |
12735 | && ! bfd_is_com_section (symsec) | |
12736 | && !linkonce | |
12737 | #ifdef OBJ_ELF | |
12738 | /* A global or weak symbol is treated as external. */ | |
12739 | && (OUTPUT_FLAVOR != bfd_target_elf_flavour | |
3e722fb5 | 12740 | || (! S_IS_WEAK (sym) && ! S_IS_EXTERNAL (sym))) |
5919d012 RS |
12741 | #endif |
12742 | ); | |
12743 | } | |
12744 | ||
12745 | ||
252b5132 RH |
12746 | /* Given a mips16 variant frag FRAGP, return non-zero if it needs an |
12747 | extended opcode. SEC is the section the frag is in. */ | |
12748 | ||
12749 | static int | |
17a2f251 | 12750 | mips16_extended_frag (fragS *fragp, asection *sec, long stretch) |
252b5132 RH |
12751 | { |
12752 | int type; | |
12753 | register const struct mips16_immed_operand *op; | |
12754 | offsetT val; | |
12755 | int mintiny, maxtiny; | |
12756 | segT symsec; | |
98aa84af | 12757 | fragS *sym_frag; |
252b5132 RH |
12758 | |
12759 | if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype)) | |
12760 | return 0; | |
12761 | if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype)) | |
12762 | return 1; | |
12763 | ||
12764 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
12765 | op = mips16_immed_operands; | |
12766 | while (op->type != type) | |
12767 | { | |
12768 | ++op; | |
12769 | assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); | |
12770 | } | |
12771 | ||
12772 | if (op->unsp) | |
12773 | { | |
12774 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
12775 | { | |
12776 | mintiny = 1; | |
12777 | maxtiny = 1 << op->nbits; | |
12778 | } | |
12779 | else | |
12780 | { | |
12781 | mintiny = 0; | |
12782 | maxtiny = (1 << op->nbits) - 1; | |
12783 | } | |
12784 | } | |
12785 | else | |
12786 | { | |
12787 | mintiny = - (1 << (op->nbits - 1)); | |
12788 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
12789 | } | |
12790 | ||
98aa84af | 12791 | sym_frag = symbol_get_frag (fragp->fr_symbol); |
ac62c346 | 12792 | val = S_GET_VALUE (fragp->fr_symbol); |
98aa84af | 12793 | symsec = S_GET_SEGMENT (fragp->fr_symbol); |
252b5132 RH |
12794 | |
12795 | if (op->pcrel) | |
12796 | { | |
12797 | addressT addr; | |
12798 | ||
12799 | /* We won't have the section when we are called from | |
12800 | mips_relax_frag. However, we will always have been called | |
12801 | from md_estimate_size_before_relax first. If this is a | |
12802 | branch to a different section, we mark it as such. If SEC is | |
12803 | NULL, and the frag is not marked, then it must be a branch to | |
12804 | the same section. */ | |
12805 | if (sec == NULL) | |
12806 | { | |
12807 | if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype)) | |
12808 | return 1; | |
12809 | } | |
12810 | else | |
12811 | { | |
98aa84af | 12812 | /* Must have been called from md_estimate_size_before_relax. */ |
252b5132 RH |
12813 | if (symsec != sec) |
12814 | { | |
12815 | fragp->fr_subtype = | |
12816 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
12817 | ||
12818 | /* FIXME: We should support this, and let the linker | |
12819 | catch branches and loads that are out of range. */ | |
12820 | as_bad_where (fragp->fr_file, fragp->fr_line, | |
12821 | _("unsupported PC relative reference to different section")); | |
12822 | ||
12823 | return 1; | |
12824 | } | |
98aa84af AM |
12825 | if (fragp != sym_frag && sym_frag->fr_address == 0) |
12826 | /* Assume non-extended on the first relaxation pass. | |
12827 | The address we have calculated will be bogus if this is | |
12828 | a forward branch to another frag, as the forward frag | |
12829 | will have fr_address == 0. */ | |
12830 | return 0; | |
252b5132 RH |
12831 | } |
12832 | ||
12833 | /* In this case, we know for sure that the symbol fragment is in | |
98aa84af AM |
12834 | the same section. If the relax_marker of the symbol fragment |
12835 | differs from the relax_marker of this fragment, we have not | |
12836 | yet adjusted the symbol fragment fr_address. We want to add | |
252b5132 RH |
12837 | in STRETCH in order to get a better estimate of the address. |
12838 | This particularly matters because of the shift bits. */ | |
12839 | if (stretch != 0 | |
98aa84af | 12840 | && sym_frag->relax_marker != fragp->relax_marker) |
252b5132 RH |
12841 | { |
12842 | fragS *f; | |
12843 | ||
12844 | /* Adjust stretch for any alignment frag. Note that if have | |
12845 | been expanding the earlier code, the symbol may be | |
12846 | defined in what appears to be an earlier frag. FIXME: | |
12847 | This doesn't handle the fr_subtype field, which specifies | |
12848 | a maximum number of bytes to skip when doing an | |
12849 | alignment. */ | |
98aa84af | 12850 | for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next) |
252b5132 RH |
12851 | { |
12852 | if (f->fr_type == rs_align || f->fr_type == rs_align_code) | |
12853 | { | |
12854 | if (stretch < 0) | |
12855 | stretch = - ((- stretch) | |
12856 | & ~ ((1 << (int) f->fr_offset) - 1)); | |
12857 | else | |
12858 | stretch &= ~ ((1 << (int) f->fr_offset) - 1); | |
12859 | if (stretch == 0) | |
12860 | break; | |
12861 | } | |
12862 | } | |
12863 | if (f != NULL) | |
12864 | val += stretch; | |
12865 | } | |
12866 | ||
12867 | addr = fragp->fr_address + fragp->fr_fix; | |
12868 | ||
12869 | /* The base address rules are complicated. The base address of | |
12870 | a branch is the following instruction. The base address of a | |
12871 | PC relative load or add is the instruction itself, but if it | |
12872 | is in a delay slot (in which case it can not be extended) use | |
12873 | the address of the instruction whose delay slot it is in. */ | |
12874 | if (type == 'p' || type == 'q') | |
12875 | { | |
12876 | addr += 2; | |
12877 | ||
12878 | /* If we are currently assuming that this frag should be | |
12879 | extended, then, the current address is two bytes | |
bdaaa2e1 | 12880 | higher. */ |
252b5132 RH |
12881 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) |
12882 | addr += 2; | |
12883 | ||
12884 | /* Ignore the low bit in the target, since it will be set | |
12885 | for a text label. */ | |
12886 | if ((val & 1) != 0) | |
12887 | --val; | |
12888 | } | |
12889 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) | |
12890 | addr -= 4; | |
12891 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
12892 | addr -= 2; | |
12893 | ||
12894 | val -= addr & ~ ((1 << op->shift) - 1); | |
12895 | ||
12896 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
12897 | if (type == 'p' || type == 'q') | |
12898 | val /= 2; | |
12899 | ||
12900 | /* If any of the shifted bits are set, we must use an extended | |
12901 | opcode. If the address depends on the size of this | |
12902 | instruction, this can lead to a loop, so we arrange to always | |
12903 | use an extended opcode. We only check this when we are in | |
12904 | the main relaxation loop, when SEC is NULL. */ | |
12905 | if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL) | |
12906 | { | |
12907 | fragp->fr_subtype = | |
12908 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
12909 | return 1; | |
12910 | } | |
12911 | ||
12912 | /* If we are about to mark a frag as extended because the value | |
12913 | is precisely maxtiny + 1, then there is a chance of an | |
12914 | infinite loop as in the following code: | |
12915 | la $4,foo | |
12916 | .skip 1020 | |
12917 | .align 2 | |
12918 | foo: | |
12919 | In this case when the la is extended, foo is 0x3fc bytes | |
12920 | away, so the la can be shrunk, but then foo is 0x400 away, so | |
12921 | the la must be extended. To avoid this loop, we mark the | |
12922 | frag as extended if it was small, and is about to become | |
12923 | extended with a value of maxtiny + 1. */ | |
12924 | if (val == ((maxtiny + 1) << op->shift) | |
12925 | && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype) | |
12926 | && sec == NULL) | |
12927 | { | |
12928 | fragp->fr_subtype = | |
12929 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
12930 | return 1; | |
12931 | } | |
12932 | } | |
12933 | else if (symsec != absolute_section && sec != NULL) | |
12934 | as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation")); | |
12935 | ||
12936 | if ((val & ((1 << op->shift) - 1)) != 0 | |
12937 | || val < (mintiny << op->shift) | |
12938 | || val > (maxtiny << op->shift)) | |
12939 | return 1; | |
12940 | else | |
12941 | return 0; | |
12942 | } | |
12943 | ||
4a6a3df4 AO |
12944 | /* Compute the length of a branch sequence, and adjust the |
12945 | RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the | |
12946 | worst-case length is computed, with UPDATE being used to indicate | |
12947 | whether an unconditional (-1), branch-likely (+1) or regular (0) | |
12948 | branch is to be computed. */ | |
12949 | static int | |
17a2f251 | 12950 | relaxed_branch_length (fragS *fragp, asection *sec, int update) |
4a6a3df4 | 12951 | { |
b34976b6 | 12952 | bfd_boolean toofar; |
4a6a3df4 AO |
12953 | int length; |
12954 | ||
12955 | if (fragp | |
12956 | && S_IS_DEFINED (fragp->fr_symbol) | |
12957 | && sec == S_GET_SEGMENT (fragp->fr_symbol)) | |
12958 | { | |
12959 | addressT addr; | |
12960 | offsetT val; | |
12961 | ||
12962 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; | |
12963 | ||
12964 | addr = fragp->fr_address + fragp->fr_fix + 4; | |
12965 | ||
12966 | val -= addr; | |
12967 | ||
12968 | toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2); | |
12969 | } | |
12970 | else if (fragp) | |
12971 | /* If the symbol is not defined or it's in a different segment, | |
12972 | assume the user knows what's going on and emit a short | |
12973 | branch. */ | |
b34976b6 | 12974 | toofar = FALSE; |
4a6a3df4 | 12975 | else |
b34976b6 | 12976 | toofar = TRUE; |
4a6a3df4 AO |
12977 | |
12978 | if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) | |
12979 | fragp->fr_subtype | |
af6ae2ad | 12980 | = RELAX_BRANCH_ENCODE (RELAX_BRANCH_UNCOND (fragp->fr_subtype), |
4a6a3df4 AO |
12981 | RELAX_BRANCH_LIKELY (fragp->fr_subtype), |
12982 | RELAX_BRANCH_LINK (fragp->fr_subtype), | |
12983 | toofar); | |
12984 | ||
12985 | length = 4; | |
12986 | if (toofar) | |
12987 | { | |
12988 | if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0)) | |
12989 | length += 8; | |
12990 | ||
12991 | if (mips_pic != NO_PIC) | |
12992 | { | |
12993 | /* Additional space for PIC loading of target address. */ | |
12994 | length += 8; | |
12995 | if (mips_opts.isa == ISA_MIPS1) | |
12996 | /* Additional space for $at-stabilizing nop. */ | |
12997 | length += 4; | |
12998 | } | |
12999 | ||
13000 | /* If branch is conditional. */ | |
13001 | if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0)) | |
13002 | length += 8; | |
13003 | } | |
b34976b6 | 13004 | |
4a6a3df4 AO |
13005 | return length; |
13006 | } | |
13007 | ||
252b5132 RH |
13008 | /* Estimate the size of a frag before relaxing. Unless this is the |
13009 | mips16, we are not really relaxing here, and the final size is | |
13010 | encoded in the subtype information. For the mips16, we have to | |
13011 | decide whether we are using an extended opcode or not. */ | |
13012 | ||
252b5132 | 13013 | int |
17a2f251 | 13014 | md_estimate_size_before_relax (fragS *fragp, asection *segtype) |
252b5132 | 13015 | { |
5919d012 | 13016 | int change; |
252b5132 | 13017 | |
4a6a3df4 AO |
13018 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
13019 | { | |
13020 | ||
b34976b6 AM |
13021 | fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE); |
13022 | ||
4a6a3df4 AO |
13023 | return fragp->fr_var; |
13024 | } | |
13025 | ||
252b5132 | 13026 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
177b4a6a AO |
13027 | /* We don't want to modify the EXTENDED bit here; it might get us |
13028 | into infinite loops. We change it only in mips_relax_frag(). */ | |
13029 | return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2); | |
252b5132 RH |
13030 | |
13031 | if (mips_pic == NO_PIC) | |
5919d012 | 13032 | change = nopic_need_relax (fragp->fr_symbol, 0); |
252b5132 | 13033 | else if (mips_pic == SVR4_PIC) |
5919d012 | 13034 | change = pic_need_relax (fragp->fr_symbol, segtype); |
252b5132 RH |
13035 | else |
13036 | abort (); | |
13037 | ||
13038 | if (change) | |
13039 | { | |
4d7206a2 | 13040 | fragp->fr_subtype |= RELAX_USE_SECOND; |
4d7206a2 | 13041 | return -RELAX_FIRST (fragp->fr_subtype); |
252b5132 | 13042 | } |
4d7206a2 RS |
13043 | else |
13044 | return -RELAX_SECOND (fragp->fr_subtype); | |
252b5132 RH |
13045 | } |
13046 | ||
13047 | /* This is called to see whether a reloc against a defined symbol | |
de7e6852 | 13048 | should be converted into a reloc against a section. */ |
252b5132 RH |
13049 | |
13050 | int | |
17a2f251 | 13051 | mips_fix_adjustable (fixS *fixp) |
252b5132 | 13052 | { |
de7e6852 RS |
13053 | /* Don't adjust MIPS16 jump relocations, so we don't have to worry |
13054 | about the format of the offset in the .o file. */ | |
252b5132 RH |
13055 | if (fixp->fx_r_type == BFD_RELOC_MIPS16_JMP) |
13056 | return 0; | |
a161fe53 | 13057 | |
252b5132 RH |
13058 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
13059 | || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
13060 | return 0; | |
a161fe53 | 13061 | |
252b5132 RH |
13062 | if (fixp->fx_addsy == NULL) |
13063 | return 1; | |
a161fe53 | 13064 | |
de7e6852 RS |
13065 | /* If symbol SYM is in a mergeable section, relocations of the form |
13066 | SYM + 0 can usually be made section-relative. The mergeable data | |
13067 | is then identified by the section offset rather than by the symbol. | |
13068 | ||
13069 | However, if we're generating REL LO16 relocations, the offset is split | |
13070 | between the LO16 and parterning high part relocation. The linker will | |
13071 | need to recalculate the complete offset in order to correctly identify | |
13072 | the merge data. | |
13073 | ||
13074 | The linker has traditionally not looked for the parterning high part | |
13075 | relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be | |
13076 | placed anywhere. Rather than break backwards compatibility by changing | |
13077 | this, it seems better not to force the issue, and instead keep the | |
13078 | original symbol. This will work with either linker behavior. */ | |
704803a9 MR |
13079 | if ((fixp->fx_r_type == BFD_RELOC_LO16 |
13080 | || fixp->fx_r_type == BFD_RELOC_MIPS16_LO16 | |
13081 | || reloc_needs_lo_p (fixp->fx_r_type)) | |
de7e6852 RS |
13082 | && HAVE_IN_PLACE_ADDENDS |
13083 | && (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_MERGE) != 0) | |
13084 | return 0; | |
13085 | ||
252b5132 | 13086 | #ifdef OBJ_ELF |
de7e6852 RS |
13087 | /* Don't adjust relocations against mips16 symbols, so that the linker |
13088 | can find them if it needs to set up a stub. */ | |
252b5132 RH |
13089 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour |
13090 | && S_GET_OTHER (fixp->fx_addsy) == STO_MIPS16 | |
13091 | && fixp->fx_subsy == NULL) | |
13092 | return 0; | |
13093 | #endif | |
a161fe53 | 13094 | |
252b5132 RH |
13095 | return 1; |
13096 | } | |
13097 | ||
13098 | /* Translate internal representation of relocation info to BFD target | |
13099 | format. */ | |
13100 | ||
13101 | arelent ** | |
17a2f251 | 13102 | tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) |
252b5132 RH |
13103 | { |
13104 | static arelent *retval[4]; | |
13105 | arelent *reloc; | |
13106 | bfd_reloc_code_real_type code; | |
13107 | ||
4b0cff4e TS |
13108 | memset (retval, 0, sizeof(retval)); |
13109 | reloc = retval[0] = (arelent *) xcalloc (1, sizeof (arelent)); | |
49309057 ILT |
13110 | reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); |
13111 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
252b5132 RH |
13112 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; |
13113 | ||
3e722fb5 CD |
13114 | assert (! fixp->fx_pcrel); |
13115 | reloc->addend = fixp->fx_addnumber; | |
252b5132 | 13116 | |
438c16b8 TS |
13117 | /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable |
13118 | entry to be used in the relocation's section offset. */ | |
13119 | if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
252b5132 RH |
13120 | { |
13121 | reloc->address = reloc->addend; | |
13122 | reloc->addend = 0; | |
13123 | } | |
13124 | ||
252b5132 | 13125 | code = fixp->fx_r_type; |
252b5132 | 13126 | |
3e722fb5 CD |
13127 | /* To support a PC relative reloc, we used a Cygnus extension. |
13128 | We check for that here to make sure that we don't let such a | |
13129 | reloc escape normally. (FIXME: This was formerly used by | |
13130 | embedded-PIC support, but is now used by branch handling in | |
13131 | general. That probably should be fixed.) */ | |
0b25d3e6 AO |
13132 | if ((OUTPUT_FLAVOR == bfd_target_ecoff_flavour |
13133 | || OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
3e722fb5 | 13134 | && code == BFD_RELOC_16_PCREL_S2) |
0b25d3e6 AO |
13135 | reloc->howto = NULL; |
13136 | else | |
13137 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); | |
13138 | ||
252b5132 RH |
13139 | if (reloc->howto == NULL) |
13140 | { | |
13141 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
13142 | _("Can not represent %s relocation in this object file format"), | |
13143 | bfd_get_reloc_code_name (code)); | |
13144 | retval[0] = NULL; | |
13145 | } | |
13146 | ||
13147 | return retval; | |
13148 | } | |
13149 | ||
13150 | /* Relax a machine dependent frag. This returns the amount by which | |
13151 | the current size of the frag should change. */ | |
13152 | ||
13153 | int | |
17a2f251 | 13154 | mips_relax_frag (asection *sec, fragS *fragp, long stretch) |
252b5132 | 13155 | { |
4a6a3df4 AO |
13156 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
13157 | { | |
13158 | offsetT old_var = fragp->fr_var; | |
b34976b6 AM |
13159 | |
13160 | fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE); | |
4a6a3df4 AO |
13161 | |
13162 | return fragp->fr_var - old_var; | |
13163 | } | |
13164 | ||
252b5132 RH |
13165 | if (! RELAX_MIPS16_P (fragp->fr_subtype)) |
13166 | return 0; | |
13167 | ||
c4e7957c | 13168 | if (mips16_extended_frag (fragp, NULL, stretch)) |
252b5132 RH |
13169 | { |
13170 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
13171 | return 0; | |
13172 | fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype); | |
13173 | return 2; | |
13174 | } | |
13175 | else | |
13176 | { | |
13177 | if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
13178 | return 0; | |
13179 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype); | |
13180 | return -2; | |
13181 | } | |
13182 | ||
13183 | return 0; | |
13184 | } | |
13185 | ||
13186 | /* Convert a machine dependent frag. */ | |
13187 | ||
13188 | void | |
17a2f251 | 13189 | md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp) |
252b5132 | 13190 | { |
4a6a3df4 AO |
13191 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
13192 | { | |
13193 | bfd_byte *buf; | |
13194 | unsigned long insn; | |
13195 | expressionS exp; | |
13196 | fixS *fixp; | |
b34976b6 | 13197 | |
4a6a3df4 AO |
13198 | buf = (bfd_byte *)fragp->fr_literal + fragp->fr_fix; |
13199 | ||
13200 | if (target_big_endian) | |
13201 | insn = bfd_getb32 (buf); | |
13202 | else | |
13203 | insn = bfd_getl32 (buf); | |
b34976b6 | 13204 | |
4a6a3df4 AO |
13205 | if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) |
13206 | { | |
13207 | /* We generate a fixup instead of applying it right now | |
13208 | because, if there are linker relaxations, we're going to | |
13209 | need the relocations. */ | |
13210 | exp.X_op = O_symbol; | |
13211 | exp.X_add_symbol = fragp->fr_symbol; | |
13212 | exp.X_add_number = fragp->fr_offset; | |
13213 | ||
13214 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
0b25d3e6 AO |
13215 | 4, &exp, 1, |
13216 | BFD_RELOC_16_PCREL_S2); | |
4a6a3df4 AO |
13217 | fixp->fx_file = fragp->fr_file; |
13218 | fixp->fx_line = fragp->fr_line; | |
b34976b6 | 13219 | |
2132e3a3 | 13220 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
13221 | buf += 4; |
13222 | } | |
13223 | else | |
13224 | { | |
13225 | int i; | |
13226 | ||
13227 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
13228 | _("relaxed out-of-range branch into a jump")); | |
13229 | ||
13230 | if (RELAX_BRANCH_UNCOND (fragp->fr_subtype)) | |
13231 | goto uncond; | |
13232 | ||
13233 | if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
13234 | { | |
13235 | /* Reverse the branch. */ | |
13236 | switch ((insn >> 28) & 0xf) | |
13237 | { | |
13238 | case 4: | |
13239 | /* bc[0-3][tf]l? and bc1any[24][ft] instructions can | |
13240 | have the condition reversed by tweaking a single | |
13241 | bit, and their opcodes all have 0x4???????. */ | |
13242 | assert ((insn & 0xf1000000) == 0x41000000); | |
13243 | insn ^= 0x00010000; | |
13244 | break; | |
13245 | ||
13246 | case 0: | |
13247 | /* bltz 0x04000000 bgez 0x04010000 | |
13248 | bltzal 0x04100000 bgezal 0x04110000 */ | |
13249 | assert ((insn & 0xfc0e0000) == 0x04000000); | |
13250 | insn ^= 0x00010000; | |
13251 | break; | |
b34976b6 | 13252 | |
4a6a3df4 AO |
13253 | case 1: |
13254 | /* beq 0x10000000 bne 0x14000000 | |
13255 | blez 0x18000000 bgtz 0x1c000000 */ | |
13256 | insn ^= 0x04000000; | |
13257 | break; | |
13258 | ||
13259 | default: | |
13260 | abort (); | |
13261 | } | |
13262 | } | |
13263 | ||
13264 | if (RELAX_BRANCH_LINK (fragp->fr_subtype)) | |
13265 | { | |
13266 | /* Clear the and-link bit. */ | |
13267 | assert ((insn & 0xfc1c0000) == 0x04100000); | |
13268 | ||
13269 | /* bltzal 0x04100000 bgezal 0x04110000 | |
13270 | bltzall 0x04120000 bgezall 0x04130000 */ | |
13271 | insn &= ~0x00100000; | |
13272 | } | |
13273 | ||
13274 | /* Branch over the branch (if the branch was likely) or the | |
13275 | full jump (not likely case). Compute the offset from the | |
13276 | current instruction to branch to. */ | |
13277 | if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
13278 | i = 16; | |
13279 | else | |
13280 | { | |
13281 | /* How many bytes in instructions we've already emitted? */ | |
13282 | i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix; | |
13283 | /* How many bytes in instructions from here to the end? */ | |
13284 | i = fragp->fr_var - i; | |
13285 | } | |
13286 | /* Convert to instruction count. */ | |
13287 | i >>= 2; | |
13288 | /* Branch counts from the next instruction. */ | |
b34976b6 | 13289 | i--; |
4a6a3df4 AO |
13290 | insn |= i; |
13291 | /* Branch over the jump. */ | |
2132e3a3 | 13292 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
13293 | buf += 4; |
13294 | ||
13295 | /* Nop */ | |
2132e3a3 | 13296 | md_number_to_chars ((char *) buf, 0, 4); |
4a6a3df4 AO |
13297 | buf += 4; |
13298 | ||
13299 | if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
13300 | { | |
13301 | /* beql $0, $0, 2f */ | |
13302 | insn = 0x50000000; | |
13303 | /* Compute the PC offset from the current instruction to | |
13304 | the end of the variable frag. */ | |
13305 | /* How many bytes in instructions we've already emitted? */ | |
13306 | i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix; | |
13307 | /* How many bytes in instructions from here to the end? */ | |
13308 | i = fragp->fr_var - i; | |
13309 | /* Convert to instruction count. */ | |
13310 | i >>= 2; | |
13311 | /* Don't decrement i, because we want to branch over the | |
13312 | delay slot. */ | |
13313 | ||
13314 | insn |= i; | |
2132e3a3 | 13315 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
13316 | buf += 4; |
13317 | ||
2132e3a3 | 13318 | md_number_to_chars ((char *) buf, 0, 4); |
4a6a3df4 AO |
13319 | buf += 4; |
13320 | } | |
13321 | ||
13322 | uncond: | |
13323 | if (mips_pic == NO_PIC) | |
13324 | { | |
13325 | /* j or jal. */ | |
13326 | insn = (RELAX_BRANCH_LINK (fragp->fr_subtype) | |
13327 | ? 0x0c000000 : 0x08000000); | |
13328 | exp.X_op = O_symbol; | |
13329 | exp.X_add_symbol = fragp->fr_symbol; | |
13330 | exp.X_add_number = fragp->fr_offset; | |
13331 | ||
13332 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
13333 | 4, &exp, 0, BFD_RELOC_MIPS_JMP); | |
13334 | fixp->fx_file = fragp->fr_file; | |
13335 | fixp->fx_line = fragp->fr_line; | |
13336 | ||
2132e3a3 | 13337 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
13338 | buf += 4; |
13339 | } | |
13340 | else | |
13341 | { | |
13342 | /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */ | |
13343 | insn = HAVE_64BIT_ADDRESSES ? 0xdf810000 : 0x8f810000; | |
13344 | exp.X_op = O_symbol; | |
13345 | exp.X_add_symbol = fragp->fr_symbol; | |
13346 | exp.X_add_number = fragp->fr_offset; | |
13347 | ||
13348 | if (fragp->fr_offset) | |
13349 | { | |
13350 | exp.X_add_symbol = make_expr_symbol (&exp); | |
13351 | exp.X_add_number = 0; | |
13352 | } | |
13353 | ||
13354 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
13355 | 4, &exp, 0, BFD_RELOC_MIPS_GOT16); | |
13356 | fixp->fx_file = fragp->fr_file; | |
13357 | fixp->fx_line = fragp->fr_line; | |
13358 | ||
2132e3a3 | 13359 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 | 13360 | buf += 4; |
b34976b6 | 13361 | |
4a6a3df4 AO |
13362 | if (mips_opts.isa == ISA_MIPS1) |
13363 | { | |
13364 | /* nop */ | |
2132e3a3 | 13365 | md_number_to_chars ((char *) buf, 0, 4); |
4a6a3df4 AO |
13366 | buf += 4; |
13367 | } | |
13368 | ||
13369 | /* d/addiu $at, $at, <sym> R_MIPS_LO16 */ | |
13370 | insn = HAVE_64BIT_ADDRESSES ? 0x64210000 : 0x24210000; | |
13371 | ||
13372 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
13373 | 4, &exp, 0, BFD_RELOC_LO16); | |
13374 | fixp->fx_file = fragp->fr_file; | |
13375 | fixp->fx_line = fragp->fr_line; | |
b34976b6 | 13376 | |
2132e3a3 | 13377 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
13378 | buf += 4; |
13379 | ||
13380 | /* j(al)r $at. */ | |
13381 | if (RELAX_BRANCH_LINK (fragp->fr_subtype)) | |
13382 | insn = 0x0020f809; | |
13383 | else | |
13384 | insn = 0x00200008; | |
13385 | ||
2132e3a3 | 13386 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
13387 | buf += 4; |
13388 | } | |
13389 | } | |
13390 | ||
13391 | assert (buf == (bfd_byte *)fragp->fr_literal | |
13392 | + fragp->fr_fix + fragp->fr_var); | |
13393 | ||
13394 | fragp->fr_fix += fragp->fr_var; | |
13395 | ||
13396 | return; | |
13397 | } | |
13398 | ||
252b5132 RH |
13399 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
13400 | { | |
13401 | int type; | |
13402 | register const struct mips16_immed_operand *op; | |
b34976b6 | 13403 | bfd_boolean small, ext; |
252b5132 RH |
13404 | offsetT val; |
13405 | bfd_byte *buf; | |
13406 | unsigned long insn; | |
b34976b6 | 13407 | bfd_boolean use_extend; |
252b5132 RH |
13408 | unsigned short extend; |
13409 | ||
13410 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
13411 | op = mips16_immed_operands; | |
13412 | while (op->type != type) | |
13413 | ++op; | |
13414 | ||
13415 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
13416 | { | |
b34976b6 AM |
13417 | small = FALSE; |
13418 | ext = TRUE; | |
252b5132 RH |
13419 | } |
13420 | else | |
13421 | { | |
b34976b6 AM |
13422 | small = TRUE; |
13423 | ext = FALSE; | |
252b5132 RH |
13424 | } |
13425 | ||
6386f3a7 | 13426 | resolve_symbol_value (fragp->fr_symbol); |
252b5132 RH |
13427 | val = S_GET_VALUE (fragp->fr_symbol); |
13428 | if (op->pcrel) | |
13429 | { | |
13430 | addressT addr; | |
13431 | ||
13432 | addr = fragp->fr_address + fragp->fr_fix; | |
13433 | ||
13434 | /* The rules for the base address of a PC relative reloc are | |
13435 | complicated; see mips16_extended_frag. */ | |
13436 | if (type == 'p' || type == 'q') | |
13437 | { | |
13438 | addr += 2; | |
13439 | if (ext) | |
13440 | addr += 2; | |
13441 | /* Ignore the low bit in the target, since it will be | |
13442 | set for a text label. */ | |
13443 | if ((val & 1) != 0) | |
13444 | --val; | |
13445 | } | |
13446 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) | |
13447 | addr -= 4; | |
13448 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
13449 | addr -= 2; | |
13450 | ||
13451 | addr &= ~ (addressT) ((1 << op->shift) - 1); | |
13452 | val -= addr; | |
13453 | ||
13454 | /* Make sure the section winds up with the alignment we have | |
13455 | assumed. */ | |
13456 | if (op->shift > 0) | |
13457 | record_alignment (asec, op->shift); | |
13458 | } | |
13459 | ||
13460 | if (ext | |
13461 | && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype) | |
13462 | || RELAX_MIPS16_DSLOT (fragp->fr_subtype))) | |
13463 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
13464 | _("extended instruction in delay slot")); | |
13465 | ||
13466 | buf = (bfd_byte *) (fragp->fr_literal + fragp->fr_fix); | |
13467 | ||
13468 | if (target_big_endian) | |
13469 | insn = bfd_getb16 (buf); | |
13470 | else | |
13471 | insn = bfd_getl16 (buf); | |
13472 | ||
13473 | mips16_immed (fragp->fr_file, fragp->fr_line, type, val, | |
13474 | RELAX_MIPS16_USER_EXT (fragp->fr_subtype), | |
13475 | small, ext, &insn, &use_extend, &extend); | |
13476 | ||
13477 | if (use_extend) | |
13478 | { | |
2132e3a3 | 13479 | md_number_to_chars ((char *) buf, 0xf000 | extend, 2); |
252b5132 RH |
13480 | fragp->fr_fix += 2; |
13481 | buf += 2; | |
13482 | } | |
13483 | ||
2132e3a3 | 13484 | md_number_to_chars ((char *) buf, insn, 2); |
252b5132 RH |
13485 | fragp->fr_fix += 2; |
13486 | buf += 2; | |
13487 | } | |
13488 | else | |
13489 | { | |
4d7206a2 RS |
13490 | int first, second; |
13491 | fixS *fixp; | |
252b5132 | 13492 | |
4d7206a2 RS |
13493 | first = RELAX_FIRST (fragp->fr_subtype); |
13494 | second = RELAX_SECOND (fragp->fr_subtype); | |
13495 | fixp = (fixS *) fragp->fr_opcode; | |
252b5132 | 13496 | |
584892a6 RS |
13497 | /* Possibly emit a warning if we've chosen the longer option. */ |
13498 | if (((fragp->fr_subtype & RELAX_USE_SECOND) != 0) | |
13499 | == ((fragp->fr_subtype & RELAX_SECOND_LONGER) != 0)) | |
13500 | { | |
13501 | const char *msg = macro_warning (fragp->fr_subtype); | |
13502 | if (msg != 0) | |
13503 | as_warn_where (fragp->fr_file, fragp->fr_line, msg); | |
13504 | } | |
13505 | ||
4d7206a2 RS |
13506 | /* Go through all the fixups for the first sequence. Disable them |
13507 | (by marking them as done) if we're going to use the second | |
13508 | sequence instead. */ | |
13509 | while (fixp | |
13510 | && fixp->fx_frag == fragp | |
13511 | && fixp->fx_where < fragp->fr_fix - second) | |
13512 | { | |
13513 | if (fragp->fr_subtype & RELAX_USE_SECOND) | |
13514 | fixp->fx_done = 1; | |
13515 | fixp = fixp->fx_next; | |
13516 | } | |
252b5132 | 13517 | |
4d7206a2 RS |
13518 | /* Go through the fixups for the second sequence. Disable them if |
13519 | we're going to use the first sequence, otherwise adjust their | |
13520 | addresses to account for the relaxation. */ | |
13521 | while (fixp && fixp->fx_frag == fragp) | |
13522 | { | |
13523 | if (fragp->fr_subtype & RELAX_USE_SECOND) | |
13524 | fixp->fx_where -= first; | |
13525 | else | |
13526 | fixp->fx_done = 1; | |
13527 | fixp = fixp->fx_next; | |
13528 | } | |
13529 | ||
13530 | /* Now modify the frag contents. */ | |
13531 | if (fragp->fr_subtype & RELAX_USE_SECOND) | |
13532 | { | |
13533 | char *start; | |
13534 | ||
13535 | start = fragp->fr_literal + fragp->fr_fix - first - second; | |
13536 | memmove (start, start + first, second); | |
13537 | fragp->fr_fix -= first; | |
13538 | } | |
13539 | else | |
13540 | fragp->fr_fix -= second; | |
252b5132 RH |
13541 | } |
13542 | } | |
13543 | ||
13544 | #ifdef OBJ_ELF | |
13545 | ||
13546 | /* This function is called after the relocs have been generated. | |
13547 | We've been storing mips16 text labels as odd. Here we convert them | |
13548 | back to even for the convenience of the debugger. */ | |
13549 | ||
13550 | void | |
17a2f251 | 13551 | mips_frob_file_after_relocs (void) |
252b5132 RH |
13552 | { |
13553 | asymbol **syms; | |
13554 | unsigned int count, i; | |
13555 | ||
13556 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
13557 | return; | |
13558 | ||
13559 | syms = bfd_get_outsymbols (stdoutput); | |
13560 | count = bfd_get_symcount (stdoutput); | |
13561 | for (i = 0; i < count; i++, syms++) | |
13562 | { | |
13563 | if (elf_symbol (*syms)->internal_elf_sym.st_other == STO_MIPS16 | |
13564 | && ((*syms)->value & 1) != 0) | |
13565 | { | |
13566 | (*syms)->value &= ~1; | |
13567 | /* If the symbol has an odd size, it was probably computed | |
13568 | incorrectly, so adjust that as well. */ | |
13569 | if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0) | |
13570 | ++elf_symbol (*syms)->internal_elf_sym.st_size; | |
13571 | } | |
13572 | } | |
13573 | } | |
13574 | ||
13575 | #endif | |
13576 | ||
13577 | /* This function is called whenever a label is defined. It is used | |
13578 | when handling branch delays; if a branch has a label, we assume we | |
13579 | can not move it. */ | |
13580 | ||
13581 | void | |
17a2f251 | 13582 | mips_define_label (symbolS *sym) |
252b5132 RH |
13583 | { |
13584 | struct insn_label_list *l; | |
13585 | ||
13586 | if (free_insn_labels == NULL) | |
13587 | l = (struct insn_label_list *) xmalloc (sizeof *l); | |
13588 | else | |
13589 | { | |
13590 | l = free_insn_labels; | |
13591 | free_insn_labels = l->next; | |
13592 | } | |
13593 | ||
13594 | l->label = sym; | |
13595 | l->next = insn_labels; | |
13596 | insn_labels = l; | |
13597 | } | |
13598 | \f | |
13599 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
13600 | ||
13601 | /* Some special processing for a MIPS ELF file. */ | |
13602 | ||
13603 | void | |
17a2f251 | 13604 | mips_elf_final_processing (void) |
252b5132 RH |
13605 | { |
13606 | /* Write out the register information. */ | |
316f5878 | 13607 | if (mips_abi != N64_ABI) |
252b5132 RH |
13608 | { |
13609 | Elf32_RegInfo s; | |
13610 | ||
13611 | s.ri_gprmask = mips_gprmask; | |
13612 | s.ri_cprmask[0] = mips_cprmask[0]; | |
13613 | s.ri_cprmask[1] = mips_cprmask[1]; | |
13614 | s.ri_cprmask[2] = mips_cprmask[2]; | |
13615 | s.ri_cprmask[3] = mips_cprmask[3]; | |
13616 | /* The gp_value field is set by the MIPS ELF backend. */ | |
13617 | ||
13618 | bfd_mips_elf32_swap_reginfo_out (stdoutput, &s, | |
13619 | ((Elf32_External_RegInfo *) | |
13620 | mips_regmask_frag)); | |
13621 | } | |
13622 | else | |
13623 | { | |
13624 | Elf64_Internal_RegInfo s; | |
13625 | ||
13626 | s.ri_gprmask = mips_gprmask; | |
13627 | s.ri_pad = 0; | |
13628 | s.ri_cprmask[0] = mips_cprmask[0]; | |
13629 | s.ri_cprmask[1] = mips_cprmask[1]; | |
13630 | s.ri_cprmask[2] = mips_cprmask[2]; | |
13631 | s.ri_cprmask[3] = mips_cprmask[3]; | |
13632 | /* The gp_value field is set by the MIPS ELF backend. */ | |
13633 | ||
13634 | bfd_mips_elf64_swap_reginfo_out (stdoutput, &s, | |
13635 | ((Elf64_External_RegInfo *) | |
13636 | mips_regmask_frag)); | |
13637 | } | |
13638 | ||
13639 | /* Set the MIPS ELF flag bits. FIXME: There should probably be some | |
13640 | sort of BFD interface for this. */ | |
13641 | if (mips_any_noreorder) | |
13642 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER; | |
13643 | if (mips_pic != NO_PIC) | |
143d77c5 | 13644 | { |
252b5132 | 13645 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC; |
143d77c5 EC |
13646 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC; |
13647 | } | |
13648 | if (mips_abicalls) | |
13649 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC; | |
252b5132 | 13650 | |
98d3f06f | 13651 | /* Set MIPS ELF flags for ASEs. */ |
74cd071d CF |
13652 | /* We may need to define a new flag for DSP ASE, and set this flag when |
13653 | file_ase_dsp is true. */ | |
ef2e4d86 CF |
13654 | /* We may need to define a new flag for MT ASE, and set this flag when |
13655 | file_ase_mt is true. */ | |
a4672219 TS |
13656 | if (file_ase_mips16) |
13657 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16; | |
1f25f5d3 CD |
13658 | #if 0 /* XXX FIXME */ |
13659 | if (file_ase_mips3d) | |
13660 | elf_elfheader (stdoutput)->e_flags |= ???; | |
13661 | #endif | |
deec1734 CD |
13662 | if (file_ase_mdmx) |
13663 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX; | |
1f25f5d3 | 13664 | |
bdaaa2e1 | 13665 | /* Set the MIPS ELF ABI flags. */ |
316f5878 | 13666 | if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32) |
252b5132 | 13667 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32; |
316f5878 | 13668 | else if (mips_abi == O64_ABI) |
252b5132 | 13669 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64; |
316f5878 | 13670 | else if (mips_abi == EABI_ABI) |
252b5132 | 13671 | { |
316f5878 | 13672 | if (!file_mips_gp32) |
252b5132 RH |
13673 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64; |
13674 | else | |
13675 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32; | |
13676 | } | |
316f5878 | 13677 | else if (mips_abi == N32_ABI) |
be00bddd TS |
13678 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2; |
13679 | ||
c9914766 | 13680 | /* Nothing to do for N64_ABI. */ |
252b5132 RH |
13681 | |
13682 | if (mips_32bitmode) | |
13683 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE; | |
13684 | } | |
13685 | ||
13686 | #endif /* OBJ_ELF || OBJ_MAYBE_ELF */ | |
13687 | \f | |
beae10d5 | 13688 | typedef struct proc { |
9b2f1d35 EC |
13689 | symbolS *func_sym; |
13690 | symbolS *func_end_sym; | |
beae10d5 KH |
13691 | unsigned long reg_mask; |
13692 | unsigned long reg_offset; | |
13693 | unsigned long fpreg_mask; | |
13694 | unsigned long fpreg_offset; | |
13695 | unsigned long frame_offset; | |
13696 | unsigned long frame_reg; | |
13697 | unsigned long pc_reg; | |
13698 | } procS; | |
252b5132 RH |
13699 | |
13700 | static procS cur_proc; | |
13701 | static procS *cur_proc_ptr; | |
13702 | static int numprocs; | |
13703 | ||
0a9ef439 | 13704 | /* Fill in an rs_align_code fragment. */ |
a19d8eb0 | 13705 | |
0a9ef439 | 13706 | void |
17a2f251 | 13707 | mips_handle_align (fragS *fragp) |
a19d8eb0 | 13708 | { |
0a9ef439 RH |
13709 | if (fragp->fr_type != rs_align_code) |
13710 | return; | |
13711 | ||
13712 | if (mips_opts.mips16) | |
a19d8eb0 CP |
13713 | { |
13714 | static const unsigned char be_nop[] = { 0x65, 0x00 }; | |
13715 | static const unsigned char le_nop[] = { 0x00, 0x65 }; | |
13716 | ||
0a9ef439 RH |
13717 | int bytes; |
13718 | char *p; | |
a19d8eb0 | 13719 | |
0a9ef439 RH |
13720 | bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix; |
13721 | p = fragp->fr_literal + fragp->fr_fix; | |
13722 | ||
13723 | if (bytes & 1) | |
13724 | { | |
13725 | *p++ = 0; | |
f9419b05 | 13726 | fragp->fr_fix++; |
0a9ef439 RH |
13727 | } |
13728 | ||
13729 | memcpy (p, (target_big_endian ? be_nop : le_nop), 2); | |
13730 | fragp->fr_var = 2; | |
a19d8eb0 CP |
13731 | } |
13732 | ||
0a9ef439 | 13733 | /* For mips32, a nop is a zero, which we trivially get by doing nothing. */ |
a19d8eb0 CP |
13734 | } |
13735 | ||
252b5132 | 13736 | static void |
17a2f251 | 13737 | md_obj_begin (void) |
252b5132 RH |
13738 | { |
13739 | } | |
13740 | ||
13741 | static void | |
17a2f251 | 13742 | md_obj_end (void) |
252b5132 RH |
13743 | { |
13744 | /* check for premature end, nesting errors, etc */ | |
13745 | if (cur_proc_ptr) | |
9a41af64 | 13746 | as_warn (_("missing .end at end of assembly")); |
252b5132 RH |
13747 | } |
13748 | ||
13749 | static long | |
17a2f251 | 13750 | get_number (void) |
252b5132 RH |
13751 | { |
13752 | int negative = 0; | |
13753 | long val = 0; | |
13754 | ||
13755 | if (*input_line_pointer == '-') | |
13756 | { | |
13757 | ++input_line_pointer; | |
13758 | negative = 1; | |
13759 | } | |
3882b010 | 13760 | if (!ISDIGIT (*input_line_pointer)) |
956cd1d6 | 13761 | as_bad (_("expected simple number")); |
252b5132 RH |
13762 | if (input_line_pointer[0] == '0') |
13763 | { | |
13764 | if (input_line_pointer[1] == 'x') | |
13765 | { | |
13766 | input_line_pointer += 2; | |
3882b010 | 13767 | while (ISXDIGIT (*input_line_pointer)) |
252b5132 RH |
13768 | { |
13769 | val <<= 4; | |
13770 | val |= hex_value (*input_line_pointer++); | |
13771 | } | |
13772 | return negative ? -val : val; | |
13773 | } | |
13774 | else | |
13775 | { | |
13776 | ++input_line_pointer; | |
3882b010 | 13777 | while (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
13778 | { |
13779 | val <<= 3; | |
13780 | val |= *input_line_pointer++ - '0'; | |
13781 | } | |
13782 | return negative ? -val : val; | |
13783 | } | |
13784 | } | |
3882b010 | 13785 | if (!ISDIGIT (*input_line_pointer)) |
252b5132 RH |
13786 | { |
13787 | printf (_(" *input_line_pointer == '%c' 0x%02x\n"), | |
13788 | *input_line_pointer, *input_line_pointer); | |
956cd1d6 | 13789 | as_warn (_("invalid number")); |
252b5132 RH |
13790 | return -1; |
13791 | } | |
3882b010 | 13792 | while (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
13793 | { |
13794 | val *= 10; | |
13795 | val += *input_line_pointer++ - '0'; | |
13796 | } | |
13797 | return negative ? -val : val; | |
13798 | } | |
13799 | ||
13800 | /* The .file directive; just like the usual .file directive, but there | |
c5dd6aab DJ |
13801 | is an initial number which is the ECOFF file index. In the non-ECOFF |
13802 | case .file implies DWARF-2. */ | |
13803 | ||
13804 | static void | |
17a2f251 | 13805 | s_mips_file (int x ATTRIBUTE_UNUSED) |
c5dd6aab | 13806 | { |
ecb4347a DJ |
13807 | static int first_file_directive = 0; |
13808 | ||
c5dd6aab DJ |
13809 | if (ECOFF_DEBUGGING) |
13810 | { | |
13811 | get_number (); | |
13812 | s_app_file (0); | |
13813 | } | |
13814 | else | |
ecb4347a DJ |
13815 | { |
13816 | char *filename; | |
13817 | ||
13818 | filename = dwarf2_directive_file (0); | |
13819 | ||
13820 | /* Versions of GCC up to 3.1 start files with a ".file" | |
13821 | directive even for stabs output. Make sure that this | |
13822 | ".file" is handled. Note that you need a version of GCC | |
13823 | after 3.1 in order to support DWARF-2 on MIPS. */ | |
13824 | if (filename != NULL && ! first_file_directive) | |
13825 | { | |
13826 | (void) new_logical_line (filename, -1); | |
c04f5787 | 13827 | s_app_file_string (filename, 0); |
ecb4347a DJ |
13828 | } |
13829 | first_file_directive = 1; | |
13830 | } | |
c5dd6aab DJ |
13831 | } |
13832 | ||
13833 | /* The .loc directive, implying DWARF-2. */ | |
252b5132 RH |
13834 | |
13835 | static void | |
17a2f251 | 13836 | s_mips_loc (int x ATTRIBUTE_UNUSED) |
252b5132 | 13837 | { |
c5dd6aab DJ |
13838 | if (!ECOFF_DEBUGGING) |
13839 | dwarf2_directive_loc (0); | |
252b5132 RH |
13840 | } |
13841 | ||
252b5132 RH |
13842 | /* The .end directive. */ |
13843 | ||
13844 | static void | |
17a2f251 | 13845 | s_mips_end (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
13846 | { |
13847 | symbolS *p; | |
252b5132 | 13848 | |
7a621144 DJ |
13849 | /* Following functions need their own .frame and .cprestore directives. */ |
13850 | mips_frame_reg_valid = 0; | |
13851 | mips_cprestore_valid = 0; | |
13852 | ||
252b5132 RH |
13853 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
13854 | { | |
13855 | p = get_symbol (); | |
13856 | demand_empty_rest_of_line (); | |
13857 | } | |
13858 | else | |
13859 | p = NULL; | |
13860 | ||
14949570 | 13861 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0) |
252b5132 RH |
13862 | as_warn (_(".end not in text section")); |
13863 | ||
13864 | if (!cur_proc_ptr) | |
13865 | { | |
13866 | as_warn (_(".end directive without a preceding .ent directive.")); | |
13867 | demand_empty_rest_of_line (); | |
13868 | return; | |
13869 | } | |
13870 | ||
13871 | if (p != NULL) | |
13872 | { | |
13873 | assert (S_GET_NAME (p)); | |
9b2f1d35 | 13874 | if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->func_sym))) |
252b5132 | 13875 | as_warn (_(".end symbol does not match .ent symbol.")); |
ecb4347a DJ |
13876 | |
13877 | if (debug_type == DEBUG_STABS) | |
13878 | stabs_generate_asm_endfunc (S_GET_NAME (p), | |
13879 | S_GET_NAME (p)); | |
252b5132 RH |
13880 | } |
13881 | else | |
13882 | as_warn (_(".end directive missing or unknown symbol")); | |
13883 | ||
2132e3a3 | 13884 | #ifdef OBJ_ELF |
9b2f1d35 EC |
13885 | /* Create an expression to calculate the size of the function. */ |
13886 | if (p && cur_proc_ptr) | |
13887 | { | |
13888 | OBJ_SYMFIELD_TYPE *obj = symbol_get_obj (p); | |
13889 | expressionS *exp = xmalloc (sizeof (expressionS)); | |
13890 | ||
13891 | obj->size = exp; | |
13892 | exp->X_op = O_subtract; | |
13893 | exp->X_add_symbol = symbol_temp_new_now (); | |
13894 | exp->X_op_symbol = p; | |
13895 | exp->X_add_number = 0; | |
13896 | ||
13897 | cur_proc_ptr->func_end_sym = exp->X_add_symbol; | |
13898 | } | |
13899 | ||
ecb4347a | 13900 | /* Generate a .pdr section. */ |
dcd410fe RO |
13901 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING |
13902 | && mips_flag_pdr) | |
ecb4347a DJ |
13903 | { |
13904 | segT saved_seg = now_seg; | |
13905 | subsegT saved_subseg = now_subseg; | |
13906 | valueT dot; | |
13907 | expressionS exp; | |
13908 | char *fragp; | |
252b5132 | 13909 | |
ecb4347a | 13910 | dot = frag_now_fix (); |
252b5132 RH |
13911 | |
13912 | #ifdef md_flush_pending_output | |
ecb4347a | 13913 | md_flush_pending_output (); |
252b5132 RH |
13914 | #endif |
13915 | ||
ecb4347a DJ |
13916 | assert (pdr_seg); |
13917 | subseg_set (pdr_seg, 0); | |
252b5132 | 13918 | |
ecb4347a DJ |
13919 | /* Write the symbol. */ |
13920 | exp.X_op = O_symbol; | |
13921 | exp.X_add_symbol = p; | |
13922 | exp.X_add_number = 0; | |
13923 | emit_expr (&exp, 4); | |
252b5132 | 13924 | |
ecb4347a | 13925 | fragp = frag_more (7 * 4); |
252b5132 | 13926 | |
17a2f251 TS |
13927 | md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4); |
13928 | md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4); | |
13929 | md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4); | |
13930 | md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4); | |
13931 | md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4); | |
13932 | md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4); | |
13933 | md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4); | |
252b5132 | 13934 | |
ecb4347a DJ |
13935 | subseg_set (saved_seg, saved_subseg); |
13936 | } | |
13937 | #endif /* OBJ_ELF */ | |
252b5132 RH |
13938 | |
13939 | cur_proc_ptr = NULL; | |
13940 | } | |
13941 | ||
13942 | /* The .aent and .ent directives. */ | |
13943 | ||
13944 | static void | |
17a2f251 | 13945 | s_mips_ent (int aent) |
252b5132 | 13946 | { |
252b5132 | 13947 | symbolS *symbolP; |
252b5132 RH |
13948 | |
13949 | symbolP = get_symbol (); | |
13950 | if (*input_line_pointer == ',') | |
f9419b05 | 13951 | ++input_line_pointer; |
252b5132 | 13952 | SKIP_WHITESPACE (); |
3882b010 | 13953 | if (ISDIGIT (*input_line_pointer) |
d9a62219 | 13954 | || *input_line_pointer == '-') |
874e8986 | 13955 | get_number (); |
252b5132 | 13956 | |
14949570 | 13957 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0) |
252b5132 RH |
13958 | as_warn (_(".ent or .aent not in text section.")); |
13959 | ||
13960 | if (!aent && cur_proc_ptr) | |
9a41af64 | 13961 | as_warn (_("missing .end")); |
252b5132 RH |
13962 | |
13963 | if (!aent) | |
13964 | { | |
7a621144 DJ |
13965 | /* This function needs its own .frame and .cprestore directives. */ |
13966 | mips_frame_reg_valid = 0; | |
13967 | mips_cprestore_valid = 0; | |
13968 | ||
252b5132 RH |
13969 | cur_proc_ptr = &cur_proc; |
13970 | memset (cur_proc_ptr, '\0', sizeof (procS)); | |
13971 | ||
9b2f1d35 | 13972 | cur_proc_ptr->func_sym = symbolP; |
252b5132 | 13973 | |
49309057 | 13974 | symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION; |
252b5132 | 13975 | |
f9419b05 | 13976 | ++numprocs; |
ecb4347a DJ |
13977 | |
13978 | if (debug_type == DEBUG_STABS) | |
13979 | stabs_generate_asm_func (S_GET_NAME (symbolP), | |
13980 | S_GET_NAME (symbolP)); | |
252b5132 RH |
13981 | } |
13982 | ||
13983 | demand_empty_rest_of_line (); | |
13984 | } | |
13985 | ||
13986 | /* The .frame directive. If the mdebug section is present (IRIX 5 native) | |
bdaaa2e1 | 13987 | then ecoff.c (ecoff_directive_frame) is used. For embedded targets, |
252b5132 | 13988 | s_mips_frame is used so that we can set the PDR information correctly. |
bdaaa2e1 | 13989 | We can't use the ecoff routines because they make reference to the ecoff |
252b5132 RH |
13990 | symbol table (in the mdebug section). */ |
13991 | ||
13992 | static void | |
17a2f251 | 13993 | s_mips_frame (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 13994 | { |
ecb4347a DJ |
13995 | #ifdef OBJ_ELF |
13996 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING) | |
13997 | { | |
13998 | long val; | |
252b5132 | 13999 | |
ecb4347a DJ |
14000 | if (cur_proc_ptr == (procS *) NULL) |
14001 | { | |
14002 | as_warn (_(".frame outside of .ent")); | |
14003 | demand_empty_rest_of_line (); | |
14004 | return; | |
14005 | } | |
252b5132 | 14006 | |
ecb4347a DJ |
14007 | cur_proc_ptr->frame_reg = tc_get_register (1); |
14008 | ||
14009 | SKIP_WHITESPACE (); | |
14010 | if (*input_line_pointer++ != ',' | |
14011 | || get_absolute_expression_and_terminator (&val) != ',') | |
14012 | { | |
14013 | as_warn (_("Bad .frame directive")); | |
14014 | --input_line_pointer; | |
14015 | demand_empty_rest_of_line (); | |
14016 | return; | |
14017 | } | |
252b5132 | 14018 | |
ecb4347a DJ |
14019 | cur_proc_ptr->frame_offset = val; |
14020 | cur_proc_ptr->pc_reg = tc_get_register (0); | |
252b5132 | 14021 | |
252b5132 | 14022 | demand_empty_rest_of_line (); |
252b5132 | 14023 | } |
ecb4347a DJ |
14024 | else |
14025 | #endif /* OBJ_ELF */ | |
14026 | s_ignore (ignore); | |
252b5132 RH |
14027 | } |
14028 | ||
bdaaa2e1 KH |
14029 | /* The .fmask and .mask directives. If the mdebug section is present |
14030 | (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For | |
252b5132 | 14031 | embedded targets, s_mips_mask is used so that we can set the PDR |
bdaaa2e1 | 14032 | information correctly. We can't use the ecoff routines because they |
252b5132 RH |
14033 | make reference to the ecoff symbol table (in the mdebug section). */ |
14034 | ||
14035 | static void | |
17a2f251 | 14036 | s_mips_mask (int reg_type) |
252b5132 | 14037 | { |
ecb4347a DJ |
14038 | #ifdef OBJ_ELF |
14039 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING) | |
252b5132 | 14040 | { |
ecb4347a | 14041 | long mask, off; |
252b5132 | 14042 | |
ecb4347a DJ |
14043 | if (cur_proc_ptr == (procS *) NULL) |
14044 | { | |
14045 | as_warn (_(".mask/.fmask outside of .ent")); | |
14046 | demand_empty_rest_of_line (); | |
14047 | return; | |
14048 | } | |
252b5132 | 14049 | |
ecb4347a DJ |
14050 | if (get_absolute_expression_and_terminator (&mask) != ',') |
14051 | { | |
14052 | as_warn (_("Bad .mask/.fmask directive")); | |
14053 | --input_line_pointer; | |
14054 | demand_empty_rest_of_line (); | |
14055 | return; | |
14056 | } | |
252b5132 | 14057 | |
ecb4347a DJ |
14058 | off = get_absolute_expression (); |
14059 | ||
14060 | if (reg_type == 'F') | |
14061 | { | |
14062 | cur_proc_ptr->fpreg_mask = mask; | |
14063 | cur_proc_ptr->fpreg_offset = off; | |
14064 | } | |
14065 | else | |
14066 | { | |
14067 | cur_proc_ptr->reg_mask = mask; | |
14068 | cur_proc_ptr->reg_offset = off; | |
14069 | } | |
14070 | ||
14071 | demand_empty_rest_of_line (); | |
252b5132 RH |
14072 | } |
14073 | else | |
ecb4347a DJ |
14074 | #endif /* OBJ_ELF */ |
14075 | s_ignore (reg_type); | |
252b5132 RH |
14076 | } |
14077 | ||
316f5878 RS |
14078 | /* A table describing all the processors gas knows about. Names are |
14079 | matched in the order listed. | |
e7af610e | 14080 | |
316f5878 RS |
14081 | To ease comparison, please keep this table in the same order as |
14082 | gcc's mips_cpu_info_table[]. */ | |
e972090a NC |
14083 | static const struct mips_cpu_info mips_cpu_info_table[] = |
14084 | { | |
316f5878 RS |
14085 | /* Entries for generic ISAs */ |
14086 | { "mips1", 1, ISA_MIPS1, CPU_R3000 }, | |
14087 | { "mips2", 1, ISA_MIPS2, CPU_R6000 }, | |
14088 | { "mips3", 1, ISA_MIPS3, CPU_R4000 }, | |
14089 | { "mips4", 1, ISA_MIPS4, CPU_R8000 }, | |
14090 | { "mips5", 1, ISA_MIPS5, CPU_MIPS5 }, | |
14091 | { "mips32", 1, ISA_MIPS32, CPU_MIPS32 }, | |
af7ee8bf | 14092 | { "mips32r2", 1, ISA_MIPS32R2, CPU_MIPS32R2 }, |
316f5878 | 14093 | { "mips64", 1, ISA_MIPS64, CPU_MIPS64 }, |
5f74bc13 | 14094 | { "mips64r2", 1, ISA_MIPS64R2, CPU_MIPS64R2 }, |
316f5878 RS |
14095 | |
14096 | /* MIPS I */ | |
14097 | { "r3000", 0, ISA_MIPS1, CPU_R3000 }, | |
14098 | { "r2000", 0, ISA_MIPS1, CPU_R3000 }, | |
14099 | { "r3900", 0, ISA_MIPS1, CPU_R3900 }, | |
14100 | ||
14101 | /* MIPS II */ | |
14102 | { "r6000", 0, ISA_MIPS2, CPU_R6000 }, | |
14103 | ||
14104 | /* MIPS III */ | |
14105 | { "r4000", 0, ISA_MIPS3, CPU_R4000 }, | |
14106 | { "r4010", 0, ISA_MIPS2, CPU_R4010 }, | |
14107 | { "vr4100", 0, ISA_MIPS3, CPU_VR4100 }, | |
14108 | { "vr4111", 0, ISA_MIPS3, CPU_R4111 }, | |
60b63b72 RS |
14109 | { "vr4120", 0, ISA_MIPS3, CPU_VR4120 }, |
14110 | { "vr4130", 0, ISA_MIPS3, CPU_VR4120 }, | |
14111 | { "vr4181", 0, ISA_MIPS3, CPU_R4111 }, | |
316f5878 RS |
14112 | { "vr4300", 0, ISA_MIPS3, CPU_R4300 }, |
14113 | { "r4400", 0, ISA_MIPS3, CPU_R4400 }, | |
14114 | { "r4600", 0, ISA_MIPS3, CPU_R4600 }, | |
14115 | { "orion", 0, ISA_MIPS3, CPU_R4600 }, | |
14116 | { "r4650", 0, ISA_MIPS3, CPU_R4650 }, | |
14117 | ||
14118 | /* MIPS IV */ | |
14119 | { "r8000", 0, ISA_MIPS4, CPU_R8000 }, | |
14120 | { "r10000", 0, ISA_MIPS4, CPU_R10000 }, | |
14121 | { "r12000", 0, ISA_MIPS4, CPU_R12000 }, | |
14122 | { "vr5000", 0, ISA_MIPS4, CPU_R5000 }, | |
60b63b72 RS |
14123 | { "vr5400", 0, ISA_MIPS4, CPU_VR5400 }, |
14124 | { "vr5500", 0, ISA_MIPS4, CPU_VR5500 }, | |
316f5878 RS |
14125 | { "rm5200", 0, ISA_MIPS4, CPU_R5000 }, |
14126 | { "rm5230", 0, ISA_MIPS4, CPU_R5000 }, | |
14127 | { "rm5231", 0, ISA_MIPS4, CPU_R5000 }, | |
14128 | { "rm5261", 0, ISA_MIPS4, CPU_R5000 }, | |
14129 | { "rm5721", 0, ISA_MIPS4, CPU_R5000 }, | |
5a7ea749 | 14130 | { "rm7000", 0, ISA_MIPS4, CPU_RM7000 }, |
9a92f48d | 14131 | { "rm9000", 0, ISA_MIPS4, CPU_RM9000 }, |
316f5878 RS |
14132 | |
14133 | /* MIPS 32 */ | |
fef14a42 | 14134 | { "4kc", 0, ISA_MIPS32, CPU_MIPS32 }, |
316f5878 RS |
14135 | { "4km", 0, ISA_MIPS32, CPU_MIPS32 }, |
14136 | { "4kp", 0, ISA_MIPS32, CPU_MIPS32 }, | |
e7af610e | 14137 | |
32b26a03 MR |
14138 | /* MIPS32 Release 2 */ |
14139 | { "m4k", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
14140 | { "24k", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
14141 | { "24kc", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
14142 | { "24kf", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
14143 | { "24kx", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
14144 | ||
316f5878 RS |
14145 | /* MIPS 64 */ |
14146 | { "5kc", 0, ISA_MIPS64, CPU_MIPS64 }, | |
ff324200 | 14147 | { "5kf", 0, ISA_MIPS64, CPU_MIPS64 }, |
316f5878 | 14148 | { "20kc", 0, ISA_MIPS64, CPU_MIPS64 }, |
e7af610e | 14149 | |
c7a23324 | 14150 | /* Broadcom SB-1 CPU core */ |
316f5878 | 14151 | { "sb1", 0, ISA_MIPS64, CPU_SB1 }, |
e7af610e | 14152 | |
316f5878 RS |
14153 | /* End marker */ |
14154 | { NULL, 0, 0, 0 } | |
14155 | }; | |
e7af610e | 14156 | |
84ea6cf2 | 14157 | |
316f5878 RS |
14158 | /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL |
14159 | with a final "000" replaced by "k". Ignore case. | |
e7af610e | 14160 | |
316f5878 | 14161 | Note: this function is shared between GCC and GAS. */ |
c6c98b38 | 14162 | |
b34976b6 | 14163 | static bfd_boolean |
17a2f251 | 14164 | mips_strict_matching_cpu_name_p (const char *canonical, const char *given) |
316f5878 RS |
14165 | { |
14166 | while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical)) | |
14167 | given++, canonical++; | |
14168 | ||
14169 | return ((*given == 0 && *canonical == 0) | |
14170 | || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0)); | |
14171 | } | |
14172 | ||
14173 | ||
14174 | /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied | |
14175 | CPU name. We've traditionally allowed a lot of variation here. | |
14176 | ||
14177 | Note: this function is shared between GCC and GAS. */ | |
14178 | ||
b34976b6 | 14179 | static bfd_boolean |
17a2f251 | 14180 | mips_matching_cpu_name_p (const char *canonical, const char *given) |
316f5878 RS |
14181 | { |
14182 | /* First see if the name matches exactly, or with a final "000" | |
14183 | turned into "k". */ | |
14184 | if (mips_strict_matching_cpu_name_p (canonical, given)) | |
b34976b6 | 14185 | return TRUE; |
316f5878 RS |
14186 | |
14187 | /* If not, try comparing based on numerical designation alone. | |
14188 | See if GIVEN is an unadorned number, or 'r' followed by a number. */ | |
14189 | if (TOLOWER (*given) == 'r') | |
14190 | given++; | |
14191 | if (!ISDIGIT (*given)) | |
b34976b6 | 14192 | return FALSE; |
316f5878 RS |
14193 | |
14194 | /* Skip over some well-known prefixes in the canonical name, | |
14195 | hoping to find a number there too. */ | |
14196 | if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r') | |
14197 | canonical += 2; | |
14198 | else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm') | |
14199 | canonical += 2; | |
14200 | else if (TOLOWER (canonical[0]) == 'r') | |
14201 | canonical += 1; | |
14202 | ||
14203 | return mips_strict_matching_cpu_name_p (canonical, given); | |
14204 | } | |
14205 | ||
14206 | ||
14207 | /* Parse an option that takes the name of a processor as its argument. | |
14208 | OPTION is the name of the option and CPU_STRING is the argument. | |
14209 | Return the corresponding processor enumeration if the CPU_STRING is | |
14210 | recognized, otherwise report an error and return null. | |
14211 | ||
14212 | A similar function exists in GCC. */ | |
e7af610e NC |
14213 | |
14214 | static const struct mips_cpu_info * | |
17a2f251 | 14215 | mips_parse_cpu (const char *option, const char *cpu_string) |
e7af610e | 14216 | { |
316f5878 | 14217 | const struct mips_cpu_info *p; |
e7af610e | 14218 | |
316f5878 RS |
14219 | /* 'from-abi' selects the most compatible architecture for the given |
14220 | ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the | |
14221 | EABIs, we have to decide whether we're using the 32-bit or 64-bit | |
14222 | version. Look first at the -mgp options, if given, otherwise base | |
14223 | the choice on MIPS_DEFAULT_64BIT. | |
e7af610e | 14224 | |
316f5878 RS |
14225 | Treat NO_ABI like the EABIs. One reason to do this is that the |
14226 | plain 'mips' and 'mips64' configs have 'from-abi' as their default | |
14227 | architecture. This code picks MIPS I for 'mips' and MIPS III for | |
14228 | 'mips64', just as we did in the days before 'from-abi'. */ | |
14229 | if (strcasecmp (cpu_string, "from-abi") == 0) | |
14230 | { | |
14231 | if (ABI_NEEDS_32BIT_REGS (mips_abi)) | |
14232 | return mips_cpu_info_from_isa (ISA_MIPS1); | |
14233 | ||
14234 | if (ABI_NEEDS_64BIT_REGS (mips_abi)) | |
14235 | return mips_cpu_info_from_isa (ISA_MIPS3); | |
14236 | ||
14237 | if (file_mips_gp32 >= 0) | |
14238 | return mips_cpu_info_from_isa (file_mips_gp32 ? ISA_MIPS1 : ISA_MIPS3); | |
14239 | ||
14240 | return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT | |
14241 | ? ISA_MIPS3 | |
14242 | : ISA_MIPS1); | |
14243 | } | |
14244 | ||
14245 | /* 'default' has traditionally been a no-op. Probably not very useful. */ | |
14246 | if (strcasecmp (cpu_string, "default") == 0) | |
14247 | return 0; | |
14248 | ||
14249 | for (p = mips_cpu_info_table; p->name != 0; p++) | |
14250 | if (mips_matching_cpu_name_p (p->name, cpu_string)) | |
14251 | return p; | |
14252 | ||
14253 | as_bad ("Bad value (%s) for %s", cpu_string, option); | |
14254 | return 0; | |
e7af610e NC |
14255 | } |
14256 | ||
316f5878 RS |
14257 | /* Return the canonical processor information for ISA (a member of the |
14258 | ISA_MIPS* enumeration). */ | |
14259 | ||
e7af610e | 14260 | static const struct mips_cpu_info * |
17a2f251 | 14261 | mips_cpu_info_from_isa (int isa) |
e7af610e NC |
14262 | { |
14263 | int i; | |
14264 | ||
14265 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
14266 | if (mips_cpu_info_table[i].is_isa | |
316f5878 | 14267 | && isa == mips_cpu_info_table[i].isa) |
e7af610e NC |
14268 | return (&mips_cpu_info_table[i]); |
14269 | ||
e972090a | 14270 | return NULL; |
e7af610e | 14271 | } |
fef14a42 TS |
14272 | |
14273 | static const struct mips_cpu_info * | |
17a2f251 | 14274 | mips_cpu_info_from_arch (int arch) |
fef14a42 TS |
14275 | { |
14276 | int i; | |
14277 | ||
14278 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
14279 | if (arch == mips_cpu_info_table[i].cpu) | |
14280 | return (&mips_cpu_info_table[i]); | |
14281 | ||
14282 | return NULL; | |
14283 | } | |
316f5878 RS |
14284 | \f |
14285 | static void | |
17a2f251 | 14286 | show (FILE *stream, const char *string, int *col_p, int *first_p) |
316f5878 RS |
14287 | { |
14288 | if (*first_p) | |
14289 | { | |
14290 | fprintf (stream, "%24s", ""); | |
14291 | *col_p = 24; | |
14292 | } | |
14293 | else | |
14294 | { | |
14295 | fprintf (stream, ", "); | |
14296 | *col_p += 2; | |
14297 | } | |
e7af610e | 14298 | |
316f5878 RS |
14299 | if (*col_p + strlen (string) > 72) |
14300 | { | |
14301 | fprintf (stream, "\n%24s", ""); | |
14302 | *col_p = 24; | |
14303 | } | |
14304 | ||
14305 | fprintf (stream, "%s", string); | |
14306 | *col_p += strlen (string); | |
14307 | ||
14308 | *first_p = 0; | |
14309 | } | |
14310 | ||
14311 | void | |
17a2f251 | 14312 | md_show_usage (FILE *stream) |
e7af610e | 14313 | { |
316f5878 RS |
14314 | int column, first; |
14315 | size_t i; | |
14316 | ||
14317 | fprintf (stream, _("\ | |
14318 | MIPS options:\n\ | |
316f5878 RS |
14319 | -EB generate big endian output\n\ |
14320 | -EL generate little endian output\n\ | |
14321 | -g, -g2 do not remove unneeded NOPs or swap branches\n\ | |
14322 | -G NUM allow referencing objects up to NUM bytes\n\ | |
14323 | implicitly with the gp register [default 8]\n")); | |
14324 | fprintf (stream, _("\ | |
14325 | -mips1 generate MIPS ISA I instructions\n\ | |
14326 | -mips2 generate MIPS ISA II instructions\n\ | |
14327 | -mips3 generate MIPS ISA III instructions\n\ | |
14328 | -mips4 generate MIPS ISA IV instructions\n\ | |
14329 | -mips5 generate MIPS ISA V instructions\n\ | |
14330 | -mips32 generate MIPS32 ISA instructions\n\ | |
af7ee8bf | 14331 | -mips32r2 generate MIPS32 release 2 ISA instructions\n\ |
316f5878 | 14332 | -mips64 generate MIPS64 ISA instructions\n\ |
5f74bc13 | 14333 | -mips64r2 generate MIPS64 release 2 ISA instructions\n\ |
316f5878 RS |
14334 | -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n")); |
14335 | ||
14336 | first = 1; | |
e7af610e NC |
14337 | |
14338 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
316f5878 RS |
14339 | show (stream, mips_cpu_info_table[i].name, &column, &first); |
14340 | show (stream, "from-abi", &column, &first); | |
14341 | fputc ('\n', stream); | |
e7af610e | 14342 | |
316f5878 RS |
14343 | fprintf (stream, _("\ |
14344 | -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\ | |
14345 | -no-mCPU don't generate code specific to CPU.\n\ | |
14346 | For -mCPU and -no-mCPU, CPU must be one of:\n")); | |
14347 | ||
14348 | first = 1; | |
14349 | ||
14350 | show (stream, "3900", &column, &first); | |
14351 | show (stream, "4010", &column, &first); | |
14352 | show (stream, "4100", &column, &first); | |
14353 | show (stream, "4650", &column, &first); | |
14354 | fputc ('\n', stream); | |
14355 | ||
14356 | fprintf (stream, _("\ | |
14357 | -mips16 generate mips16 instructions\n\ | |
14358 | -no-mips16 do not generate mips16 instructions\n")); | |
14359 | fprintf (stream, _("\ | |
74cd071d CF |
14360 | -mdsp generate DSP instructions\n\ |
14361 | -mno-dsp do not generate DSP instructions\n")); | |
14362 | fprintf (stream, _("\ | |
ef2e4d86 CF |
14363 | -mmt generate MT instructions\n\ |
14364 | -mno-mt do not generate MT instructions\n")); | |
14365 | fprintf (stream, _("\ | |
d766e8ec | 14366 | -mfix-vr4120 work around certain VR4120 errata\n\ |
7d8e00cf | 14367 | -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\ |
316f5878 RS |
14368 | -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\ |
14369 | -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\ | |
aed1a261 RS |
14370 | -mno-shared optimize output for executables\n\ |
14371 | -msym32 assume all symbols have 32-bit values\n\ | |
316f5878 RS |
14372 | -O0 remove unneeded NOPs, do not swap branches\n\ |
14373 | -O remove unneeded NOPs and swap branches\n\ | |
316f5878 RS |
14374 | --[no-]construct-floats [dis]allow floating point values to be constructed\n\ |
14375 | --trap, --no-break trap exception on div by 0 and mult overflow\n\ | |
14376 | --break, --no-trap break exception on div by 0 and mult overflow\n")); | |
14377 | #ifdef OBJ_ELF | |
14378 | fprintf (stream, _("\ | |
14379 | -KPIC, -call_shared generate SVR4 position independent code\n\ | |
14380 | -non_shared do not generate position independent code\n\ | |
14381 | -xgot assume a 32 bit GOT\n\ | |
dcd410fe | 14382 | -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\ |
bbe506e8 TS |
14383 | -mshared, -mno-shared disable/enable .cpload optimization for\n\ |
14384 | non-shared code\n\ | |
316f5878 RS |
14385 | -mabi=ABI create ABI conformant object file for:\n")); |
14386 | ||
14387 | first = 1; | |
14388 | ||
14389 | show (stream, "32", &column, &first); | |
14390 | show (stream, "o64", &column, &first); | |
14391 | show (stream, "n32", &column, &first); | |
14392 | show (stream, "64", &column, &first); | |
14393 | show (stream, "eabi", &column, &first); | |
14394 | ||
14395 | fputc ('\n', stream); | |
14396 | ||
14397 | fprintf (stream, _("\ | |
14398 | -32 create o32 ABI object file (default)\n\ | |
14399 | -n32 create n32 ABI object file\n\ | |
14400 | -64 create 64 ABI object file\n")); | |
14401 | #endif | |
e7af610e | 14402 | } |
14e777e0 KB |
14403 | |
14404 | enum dwarf2_format | |
17a2f251 | 14405 | mips_dwarf2_format (void) |
14e777e0 KB |
14406 | { |
14407 | if (mips_abi == N64_ABI) | |
1de5b6a1 AO |
14408 | { |
14409 | #ifdef TE_IRIX | |
14410 | return dwarf2_format_64bit_irix; | |
14411 | #else | |
14412 | return dwarf2_format_64bit; | |
14413 | #endif | |
14414 | } | |
14e777e0 KB |
14415 | else |
14416 | return dwarf2_format_32bit; | |
14417 | } | |
73369e65 EC |
14418 | |
14419 | int | |
14420 | mips_dwarf2_addr_size (void) | |
14421 | { | |
14422 | if (mips_abi == N64_ABI) | |
14423 | return 8; | |
73369e65 EC |
14424 | else |
14425 | return 4; | |
14426 | } | |
5862107c EC |
14427 | |
14428 | /* Standard calling conventions leave the CFA at SP on entry. */ | |
14429 | void | |
14430 | mips_cfi_frame_initial_instructions (void) | |
14431 | { | |
14432 | cfi_add_CFA_def_cfa_register (SP); | |
14433 | } | |
14434 |